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authorWaldemar Brodkorb <wbx@openadk.org>2016-06-19 23:31:38 +0200
committerWaldemar Brodkorb <wbx@openadk.org>2016-06-19 23:31:52 +0200
commit0dc6006d7b1acfbba6790287cc3afbf34f14ef6a (patch)
treef4a7d85a1c441e9559f4d13d3d11abf376404446 /target/arm/solidrun-imx6/patches/3.14.72
parenta6d2c6d3270fdcff05a873c33fed5ceade300b8e (diff)
linux: update to 3.14.72, add working solidrun patch
Diffstat (limited to 'target/arm/solidrun-imx6/patches/3.14.72')
-rw-r--r--target/arm/solidrun-imx6/patches/3.14.72/0001-solidrun-imx6.patch696919
1 files changed, 696919 insertions, 0 deletions
diff --git a/target/arm/solidrun-imx6/patches/3.14.72/0001-solidrun-imx6.patch b/target/arm/solidrun-imx6/patches/3.14.72/0001-solidrun-imx6.patch
new file mode 100644
index 000000000..3e6393cb2
--- /dev/null
+++ b/target/arm/solidrun-imx6/patches/3.14.72/0001-solidrun-imx6.patch
@@ -0,0 +1,696919 @@
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-cm-fx6.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-cm-fx6.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-cm-fx6.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-cm-fx6.dts 2016-06-19 22:11:55.009158180 +0200
+@@ -0,0 +1,21 @@
++/*
++ * Copyright 2015 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++#include "imx6dl.dtsi"
++#include "imx6qdl-cm-fx6.dtsi"
++
++/ {
++ model = "CompuLab CM-FX6";
++ compatible = "compulab,cm-fx6", "fsl,imx6dl";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-cubox-i.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-cubox-i.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-cubox-i.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-cubox-i.dts 2016-06-19 22:11:55.009158180 +0200
+@@ -1,5 +1,43 @@
+ /*
+ * Copyright (C) 2014 Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ /dts-v1/;
+
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl.dtsi linux-3.14.72/arch/arm/boot/dts/imx6dl.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl.dtsi 2016-06-19 22:11:55.009158180 +0200
+@@ -8,6 +8,7 @@
+ *
+ */
+
++#include <dt-bindings/interrupt-controller/irq.h>
+ #include "imx6dl-pinfunc.h"
+ #include "imx6qdl.dtsi"
+
+@@ -16,11 +17,37 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- cpu@0 {
++ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
++ operating-points = <
++ /* kHz uV */
++ 996000 1275000
++ 792000 1175000
++ 396000 1175000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 996000 1175000
++ 792000 1175000
++ 396000 1175000
++ >;
++ clock-latency = <61036>; /* two CLK32 periods */
++ clocks = <&clks IMX6QDL_CLK_ARM>,
++ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
++ <&clks IMX6QDL_CLK_STEP>,
++ <&clks IMX6QDL_CLK_PLL1_SW>,
++ <&clks IMX6QDL_CLK_PLL1_SYS>,
++ <&clks IMX6QDL_PLL1_BYPASS>,
++ <&clks IMX6QDL_CLK_PLL1>,
++ <&clks IMX6QDL_PLL1_BYPASS_SRC> ;
++ clock-names = "arm", "pll2_pfd2_396m", "step",
++ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
++ arm-supply = <&reg_arm>;
++ pu-supply = <&reg_pu>;
++ soc-supply = <&reg_soc>;
+ };
+
+ cpu@1 {
+@@ -32,40 +59,117 @@
+ };
+
+ soc {
+- ocram: sram@00900000 {
++ busfreq {
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
++ <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>,
++ <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>,
++ <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>,
++ <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>,
++ <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> ,
++ <&clks IMX6QDL_CLK_PLL3_PFD1_540M>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
++ interrupts = <0 107 0x04>, <0 112 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
++ fsl,max_ddr_freq = <400000000>;
++ };
++
++ gpu@00130000 {
++ compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
++ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
++ <0x0 0x0>;
++ reg-names = "iobase_3d", "iobase_2d",
++ "phys_baseaddr";
++ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
++ <0 10 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "irq_3d", "irq_2d";
++ clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>,
++ <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>,
++ <&clks IMX6QDL_CLK_DUMMY>;
++ clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
++ "gpu2d_clk", "gpu3d_clk",
++ "gpu3d_shader_clk";
++ resets = <&src 0>, <&src 3>;
++ reset-names = "gpu3d", "gpu2d";
++ power-domains = <&gpc 1>;
++ };
++
++ ocrams: sram@00900000 {
++ compatible = "fsl,lpm-sram";
++ reg = <0x00900000 0x4000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocrams_ddr: sram@00904000 {
++ compatible = "fsl,ddr-lpm-sram";
++ reg = <0x00904000 0x1000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocram: sram@00905000 {
+ compatible = "mmio-sram";
+- reg = <0x00900000 0x20000>;
+- clocks = <&clks 142>;
++ reg = <0x00905000 0x1B000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ aips1: aips-bus@02000000 {
++ vpu@02040000 {
++ iramsize = <0>;
++ };
++
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6dl-iomuxc";
+ };
+
++ dcic2: dcic@020e8000 {
++ clocks = <&clks IMX6QDL_CLK_DCIC1 >,
++ <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/
++ clock-names = "dcic", "disp-axi";
++ };
++
+ pxp: pxp@020f0000 {
++ compatible = "fsl,imx6dl-pxp-dma";
+ reg = <0x020f0000 0x4000>;
+- interrupts = <0 98 0x04>;
++ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>;
++ clock-names = "pxp-axi", "disp-axi";
++ status = "disabled";
+ };
+
+ epdc: epdc@020f4000 {
++ compatible = "fsl,imx6dl-epdc";
+ reg = <0x020f4000 0x4000>;
+- interrupts = <0 97 0x04>;
++ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>;
++ clock-names = "epdc_axi", "epdc_pix";
++ status = "disabled";
+ };
+
+ lcdif: lcdif@020f8000 {
+ reg = <0x020f8000 0x4000>;
+- interrupts = <0 39 0x04>;
++ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ aips2: aips-bus@02100000 {
++ mipi_dsi: mipi@021e0000 {
++ compatible = "fsl,imx6dl-mipi-dsi";
++ reg = <0x021e0000 0x4000>;
++ interrupts = <0 102 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
++ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
++ status = "disabled";
++ };
++
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+- compatible = "fsl,imx1-i2c";
++ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+- interrupts = <0 35 0x04>;
++ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6DL_CLK_I2C4>;
+ status = "disabled";
+ };
+ };
+@@ -73,18 +177,18 @@
+ };
+
+ &ldb {
+- clocks = <&clks 33>, <&clks 34>,
+- <&clks 39>, <&clks 40>,
+- <&clks 135>, <&clks 136>;
+- clock-names = "di0_pll", "di1_pll",
+- "di0_sel", "di1_sel",
+- "di0", "di1";
+-
+- lvds-channel@0 {
+- crtcs = <&ipu1 0>, <&ipu1 1>;
+- };
++ compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb";
+
+- lvds-channel@1 {
+- crtcs = <&ipu1 0>, <&ipu1 1>;
+- };
++ clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
++ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
++ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
++ clock-names = "ldb_di0", "ldb_di1",
++ "di0_sel", "di1_sel",
++ "di2_sel",
++ "ldb_di0_div_3_5", "ldb_di1_div_3_5",
++ "ldb_di0_div_7", "ldb_di1_div_7",
++ "ldb_di0_div_sel", "ldb_di1_div_sel";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-hummingboard2.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-hummingboard2.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-hummingboard2.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-hummingboard2.dts 2016-06-19 22:11:55.009158180 +0200
+@@ -0,0 +1,52 @@
++/*
++ * Device Tree file for SolidRun HummingBoard2
++ * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
++ * Based on work by Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "imx6dl.dtsi"
++#include "imx6qdl-hummingboard2.dtsi"
++
++/ {
++ model = "SolidRun HummingBoard2 Solo/DualLite";
++ compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-hummingboard.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-hummingboard.dts 2016-06-19 22:11:55.013158022 +0200
+@@ -1,163 +1,51 @@
+ /*
+- * Copyright (C) 2013,2014 Russell King
++ * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
++ * Based on dt work by Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ /dts-v1/;
+
+ #include "imx6dl.dtsi"
+-#include "imx6qdl-microsom.dtsi"
+-#include "imx6qdl-microsom-ar8035.dtsi"
++#include "imx6qdl-hummingboard.dtsi"
+
+ / {
+- model = "SolidRun HummingBoard DL/Solo";
+- compatible = "solidrun,hummingboard", "fsl,imx6dl";
+-
+- ir_recv: ir-receiver {
+- compatible = "gpio-ir-receiver";
+- gpios = <&gpio1 2 1>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>;
+- };
+-
+- regulators {
+- compatible = "simple-bus";
+-
+- reg_3p3v: 3p3v {
+- compatible = "regulator-fixed";
+- regulator-name = "3P3V";
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-always-on;
+- };
+-
+- reg_usbh1_vbus: usb-h1-vbus {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpio = <&gpio1 0 0>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
+- regulator-name = "usb_h1_vbus";
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- };
+-
+- reg_usbotg_vbus: usb-otg-vbus {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpio = <&gpio3 22 0>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
+- regulator-name = "usb_otg_vbus";
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- };
+- };
+-
+- sound-spdif {
+- compatible = "fsl,imx-audio-spdif";
+- model = "imx-spdif";
+- /* IMX6 doesn't implement this yet */
+- spdif-controller = <&spdif>;
+- spdif-out;
+- };
+-};
+-
+-&can1 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
+- status = "okay";
+-};
+-
+-&i2c1 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
+-
+- /*
+- * Not fitted on Carrier-1 board... yet
+- status = "okay";
+-
+- rtc: pcf8523@68 {
+- compatible = "nxp,pcf8523";
+- reg = <0x68>;
+- };
+- */
+-};
+-
+-&iomuxc {
+- hummingboard {
+- pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
+- MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
+- >;
+- };
+-
+- pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
+- >;
+- };
+-
+- pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_hummingboard_spdif: hummingboard-spdif {
+- fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
+- };
+-
+- pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
+- fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
+- };
+-
+- pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
+- fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
+- };
+-
+- pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
+- >;
+- };
+-
+- pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
+- fsl,pins = <
+- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+- >;
+- };
+- };
+-};
+-
+-&spdif {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_hummingboard_spdif>;
+- status = "okay";
+-};
+-
+-&usbh1 {
+- vbus-supply = <&reg_usbh1_vbus>;
+- status = "okay";
+-};
+-
+-&usbotg {
+- vbus-supply = <&reg_usbotg_vbus>;
+- status = "okay";
+-};
+-
+-&usdhc2 {
+- pinctrl-names = "default";
+- pinctrl-0 = <
+- &pinctrl_hummingboard_usdhc2_aux
+- &pinctrl_hummingboard_usdhc2
+- >;
+- vmmc-supply = <&reg_3p3v>;
+- cd-gpios = <&gpio1 4 0>;
+- status = "okay";
++ model = "SolidRun HummingBoard Solo/DualLite";
++ compatible = "solidrun,hummingboard/dl", "fsl,imx6dl";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-pinfunc.h linux-3.14.72/arch/arm/boot/dts/imx6dl-pinfunc.h
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-pinfunc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-pinfunc.h 2016-06-19 22:11:55.013158022 +0200
+@@ -755,6 +755,7 @@
+ #define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
+ #define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
+ #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
++#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x234 0x604 0x03c 0x11 0xff000609
+ #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
+ #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
+ #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto.dts 2016-06-19 22:11:55.013158022 +0200
+@@ -15,3 +15,21 @@
+ model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
+ compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
+ };
++
++&ldb {
++ lvds-channel@0 {
++ crtc = "ipu1-di0";
++ };
++
++ lvds-channel@1 {
++ crtc = "ipu1-di1";
++ };
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto-ecspi.dts 2016-06-19 22:11:55.013158022 +0200
+@@ -0,0 +1,39 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabreauto.dts"
++
++&ecspi1 {
++ pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&i2c3 {
++ /* pin conflict with ecspi1 */
++ status = "disabled";
++};
++
++&uart3 {
++ /* the uart3 depends on the i2c3, so disable it too. */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ dr_mode = "peripheral";
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto-flexcan1.dts 2016-06-19 22:11:55.013158022 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabreauto.dts"
++
++&flexcan1{
++ status = "okay";
++};
++
++&fec {
++ /* pin conflict with flexcan1 */
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabreauto-gpmi-weim.dts 2016-06-19 22:11:55.013158022 +0200
+@@ -0,0 +1,48 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabreauto.dts"
++
++&ecspi1 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&gpmi {
++ status = "okay";
++};
++
++&i2c3 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&uart3 {
++ /* pin conflict with gpmi and weim */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ dr_mode = "peripheral";
++ status = "okay";
++};
++
++&weim {
++ pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd.dts 2016-06-19 22:11:55.013158022 +0200
+@@ -15,3 +15,138 @@
+ model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
+ compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
+ };
++
++&battery {
++ offset-charger = <1485>;
++ offset-discharger = <1464>;
++ offset-usb-charger = <1285>;
++};
++
++&iomuxc {
++ epdc {
++ pinctrl_epdc_0: epdcgrp-0 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
++ MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
++ MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
++ MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
++ MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
++ MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
++ MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
++ MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
++ MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
++ MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
++ MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
++ MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
++ MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
++ MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
++ MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
++ MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
++ MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
++ MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
++ MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
++ MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
++ >;
++ };
++ };
++};
++
++&epdc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_epdc_0>;
++ V3P3-supply = <&V3P3_reg>;
++ VCOM-supply = <&VCOM_reg>;
++ DISPLAY-supply = <&DISPLAY_reg>;
++ status = "okay";
++};
++
++&i2c3 {
++ max17135@48 {
++ compatible = "maxim,max17135";
++ reg = <0x48>;
++ vneg_pwrup = <1>;
++ gvee_pwrup = <1>;
++ vpos_pwrup = <2>;
++ gvdd_pwrup = <1>;
++ gvdd_pwrdn = <1>;
++ vpos_pwrdn = <2>;
++ gvee_pwrdn = <1>;
++ vneg_pwrdn = <1>;
++ SENSOR-supply = <&reg_sensor>;
++ gpio_pmic_pwrgood = <&gpio2 21 0>;
++ gpio_pmic_vcom_ctrl = <&gpio3 17 0>;
++ gpio_pmic_wakeup = <&gpio3 20 0>;
++ gpio_pmic_v3p3 = <&gpio2 20 0>;
++ gpio_pmic_intr = <&gpio2 25 0>;
++
++ regulators {
++ DISPLAY_reg: DISPLAY {
++ regulator-name = "DISPLAY";
++ };
++
++ GVDD_reg: GVDD {
++ /* 20v */
++ regulator-name = "GVDD";
++ };
++
++ GVEE_reg: GVEE {
++ /* -22v */
++ regulator-name = "GVEE";
++ };
++
++ HVINN_reg: HVINN {
++ /* -22v */
++ regulator-name = "HVINN";
++ };
++
++ HVINP_reg: HVINP {
++ /* 20v */
++ regulator-name = "HVINP";
++ };
++
++ VCOM_reg: VCOM {
++ regulator-name = "VCOM";
++ /* 2's-compliment, -4325000 */
++ regulator-min-microvolt = <0xffbe0178>;
++ /* 2's-compliment, -500000 */
++ regulator-max-microvolt = <0xfff85ee0>;
++ };
++
++ VNEG_reg: VNEG {
++ /* -15v */
++ regulator-name = "VNEG";
++ };
++
++ VPOS_reg: VPOS {
++ /* 15v */
++ regulator-name = "VPOS";
++ };
++
++ V3P3_reg: V3P3 {
++ regulator-name = "V3P3";
++ };
++ };
++ };
++};
++
++&ldb {
++ lvds-channel@0 {
++ crtc = "ipu1-di0";
++ };
++
++ lvds-channel@1 {
++ crtc = "ipu1-di1";
++ };
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&pxp {
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-enetirq.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabresd.dts"
++
++&fec {
++ pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
++ interrupts-extended = <&gpio1 6 0x04>, <&intc 0 119 0x04>;
++};
++
++&i2c3 {
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-hdcp.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,19 @@
++/*
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabresd.dts"
++
++&hdmi_video {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_hdcp>;
++ fsl,hdcp;
++};
++
++&i2c2 {
++ status = "disable";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-ldo.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabresd.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++};
++
++&gpc {
++ /* use ldo-enable, u-boot will check it and configure */
++ fsl,ldo-bypass = <0>;
++ /* watchdog select of reset source */
++ fsl,wdog-reset = <1>;
++};
++
++&wdog1 {
++ status = "okay";
++};
++
++&wdog2 {
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-pf200.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-pf200.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sabresd-pf200.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sabresd-pf200.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,13 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6dl-sabresd-ldo.dts"
++
++&pmic {
++ compatible = "fsl,pfuze200";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sbc-fx6.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sbc-fx6.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sbc-fx6.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sbc-fx6.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,23 @@
++/*
++* Copyright 2015 CompuLab Ltd.
++*
++* Author: Valentin Raevsky <valentin@compulab.co.il>
++*
++* The code contained herein is licensed under the GNU General Public
++* License. You may obtain a copy of the GNU General Public License
++* Version 2 or later at the following locations:
++*
++* http://www.opensource.org/licenses/gpl-license.html
++* http://www.gnu.org/copyleft/gpl.html
++*/
++
++/dts-v1/;
++#include "imx6dl.dtsi"
++#include "imx6qdl-cm-fx6.dtsi"
++#include "imx6qdl-sb-fx6x.dtsi"
++#include "imx6qdl-sb-fx6.dtsi"
++
++/ {
++ model = "CompuLab CM-FX6 on SBC-FX6";
++ compatible = "compulab,cm-fx6", "compulab,sbc-fx6", "fsl,imx6dl";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,23 @@
++/*
++* Copyright 2015 CompuLab Ltd.
++*
++* Author: Valentin Raevsky <valentin@compulab.co.il>
++*
++* The code contained herein is licensed under the GNU General Public
++* License. You may obtain a copy of the GNU General Public License
++* Version 2 or later at the following locations:
++*
++* http://www.opensource.org/licenses/gpl-license.html
++* http://www.gnu.org/copyleft/gpl.html
++*/
++
++/dts-v1/;
++#include "imx6dl.dtsi"
++#include "imx6qdl-cm-fx6.dtsi"
++#include "imx6qdl-sb-fx6x.dtsi"
++#include "imx6qdl-sb-fx6m.dtsi"
++
++/ {
++ model = "CompuLab CM-FX6 on SBC-FX6m";
++ compatible = "compulab,cm-fx6", "compulab,sbc-fx6m", "fsl,imx6dl";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-udoo.dts linux-3.14.72/arch/arm/boot/dts/imx6dl-udoo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6dl-udoo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6dl-udoo.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,21 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ *
++ * Author: Fabio Estevam <fabio.estevam@freescale.com>
++ * Author: Ettore Chimenti <ettore.chimenti@udoo.org>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++/dts-v1/;
++#include "imx6dl.dtsi"
++#include "imx6qdl-udoo.dtsi"
++
++/ {
++ model = "Udoo i.MX6 Dual-lite Board";
++ compatible = "udoo,imx6dl-udoo", "fsl,imx6dl";
++};
++
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-arm2.dts linux-3.14.72/arch/arm/boot/dts/imx6q-arm2.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-arm2.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-arm2.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -23,14 +23,27 @@
+
+ regulators {
+ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
+
+- reg_3p3v: 3p3v {
++ reg_3p3v: regulator@0 {
+ compatible = "regulator-fixed";
++ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
++
++ reg_usb_otg_vbus: regulator@1 {
++ compatible = "regulator-fixed";
++ reg = <1>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio3 22 0>;
++ enable-active-high;
++ };
+ };
+
+ leds {
+@@ -46,46 +59,173 @@
+
+ &gpmi {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ status = "disabled"; /* gpmi nand conflicts with SD */
++ nand-on-flash-bbt;
+ };
+
+ &iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+- hog {
++ imx6q-arm2 {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
+ >;
+ };
+- };
+
+- arm2 {
+- pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpmi_nand: gpminandgrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart4: uart4grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbh2_1: usbh2grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
++ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
++ >;
++ };
++
++ pinctrl_usbh2_2: usbh2grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
++ >;
++ };
++
++ pinctrl_usbh3_1: usbh3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
++ MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
++ >;
++ };
++
++ pinctrl_usbh3_2: usbh3grp-2 {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_cdwp: usdhc3cdwp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
+ >;
+ };
++
++ pinctrl_usdhc4: usdhc4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
++ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
++ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
++ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
++ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
++ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
++ >;
++ };
+ };
+ };
+
+ &fec {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_2>;
++ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ status = "okay";
+ };
+
++&usbotg {
++ vbus-supply = <&reg_usb_otg_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ status = "okay";
++};
++
+ &usdhc3 {
+ cd-gpios = <&gpio6 11 0>;
+ wp-gpios = <&gpio6 14 0>;
+ vmmc-supply = <&reg_3p3v>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_1
+- &pinctrl_usdhc3_arm2>;
++ pinctrl-0 = <&pinctrl_usdhc3
++ &pinctrl_usdhc3_cdwp>;
+ status = "okay";
+ };
+
+@@ -93,13 +233,13 @@
+ non-removable;
+ vmmc-supply = <&reg_3p3v>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc4_1>;
++ pinctrl-0 = <&pinctrl_usdhc4>;
+ status = "okay";
+ };
+
+ &uart2 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart2_2>;
++ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,dte-mode;
+ fsl,uart-has-rtscts;
+ status = "okay";
+@@ -107,6 +247,6 @@
+
+ &uart4 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart4_1>;
++ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-arm2-hsic.dts linux-3.14.72/arch/arm/boot/dts/imx6q-arm2-hsic.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-arm2-hsic.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-arm2-hsic.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,32 @@
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include "imx6q-arm2.dts"
++
++&fec {
++ status = "disabled";
++};
++
++&usbh2 {
++ pinctrl-names = "idle", "active";
++ pinctrl-0 = <&pinctrl_usbh2_1>;
++ pinctrl-1 = <&pinctrl_usbh2_2>;
++ osc-clkgate-delay = <0x3>;
++ status = "okay";
++};
++
++&usbh3 {
++ pinctrl-names = "idle", "active";
++ pinctrl-0 = <&pinctrl_usbh3_1>;
++ pinctrl-1 = <&pinctrl_usbh3_2>;
++ osc-clkgate-delay = <0x3>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-auvidea.dts linux-3.14.72/arch/arm/boot/dts/imx6q-auvidea.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-auvidea.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-auvidea.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,51 @@
++/*
++ * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
++ * Based on dt work by Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include "imx6qdl-auvidea.dtsi"
++
++/ {
++ model = "SolidRun HummingBoard Dual/Quad";
++ compatible = "solidrun,hummingboard/q", "fsl,imx6q";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts linux-3.14.72/arch/arm/boot/dts/imx6q-cm-fx6.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-cm-fx6.dts 2016-06-19 22:11:55.017158023 +0200
+@@ -0,0 +1,21 @@
++/*
++ * Copyright 2014 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++#include "imx6q.dtsi"
++#include "imx6q-cm-fx6.dtsi"
++
++/ {
++ model = "CompuLab CM-FX6";
++ compatible = "compulab,cm-fx6", "fsl,imx6q";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-cm-fx6.dtsi linux-3.14.72/arch/arm/boot/dts/imx6q-cm-fx6.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-cm-fx6.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-cm-fx6.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -0,0 +1,95 @@
++/*
++ * Copyright 2014 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include "imx6qdl-cm-fx6.dtsi"
++
++/ {
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_sata_ldo_en: sata_ldo_en {
++ compatible = "regulator-fixed";
++ regulator-name = "cm_fx6_sata_ldo_en";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio2 16 0>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ };
++
++ reg_sata_phy_slp: sata_phy_slp {
++ compatible = "regulator-fixed";
++ regulator-name = "cm_fx6_sata_phy_slp";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio3 23 0>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ vin-supply = <&reg_sata_ldo_en>;
++ };
++
++ reg_sata_nrstdly: sata_nrstdly {
++ compatible = "regulator-fixed";
++ regulator-name = "cm_fx6_sata_nrstdly";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio6 6 0>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ vin-supply = <&reg_sata_phy_slp>;
++ };
++
++ reg_sata_pwren: sata_pwren {
++ compatible = "regulator-fixed";
++ regulator-name = "cm_fx6_sata_pwren";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio1 28 0>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ vin-supply = <&reg_sata_nrstdly>;
++ };
++
++ reg_sata_nstandby1: sata_nstandby1 {
++ compatible = "regulator-fixed";
++ regulator-name = "cm_fx6_sata_nstandby1";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio3 20 0>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ vin-supply = <&reg_sata_pwren>;
++ };
++
++ reg_sata_nstandby2: sata_nstandby2 {
++ compatible = "regulator-fixed";
++ regulator-name = "cm_fx6_sata_nstandby2";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio5 2 0>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ regulator-boot-on;
++ vin-supply = <&reg_sata_nstandby1>;
++ };
++
++ };
++
++};
++
++/* sata */
++&sata {
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-cubox-i.dts linux-3.14.72/arch/arm/boot/dts/imx6q-cubox-i.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-cubox-i.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-cubox-i.dts 2016-06-19 22:11:55.021158011 +0200
+@@ -1,5 +1,43 @@
+ /*
+ * Copyright (C) 2014 Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ /dts-v1/;
+
+@@ -13,4 +51,8 @@
+
+ &sata {
+ status = "okay";
++ fsl,transmit-level-mV = <1104>;
++ fsl,transmit-boost-mdB = <0>;
++ fsl,transmit-atten-16ths = <9>;
++ fsl,no-spread-spectrum;
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-auvidea.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-auvidea.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-auvidea.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-auvidea.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -0,0 +1,393 @@
++/*
++ * Copyright (C) 2013,2014 Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++#include "imx6qdl-microsom.dtsi"
++#include "imx6qdl-microsom-ar8035.dtsi"
++
++/ {
++ aliases {
++ mmc0 = &usdhc2;
++ mmc1 = &usdhc1;
++ mxcfb0 = &mxcfb1;
++ };
++
++ chosen {
++ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw";
++ stdout-path = &uart1;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_usbh1_vbus: usb-h1-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio1 0 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usbotg_vbus: usb-otg-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 22 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usdhc2_vbus: usdhc-2-vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "USDHC2-VBUS";
++ gpio = <&gpio4 30 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usdhc2_pwr>;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++ };
++
++ sound-sgtl5000 {
++ audio-codec = <&sgtl5000>;
++ audio-routing =
++ "MIC_IN", "Mic Jack",
++ "Mic Jack", "Mic Bias",
++ "Headphone Jack", "HP_OUT";
++ compatible = "fsl,imx-audio-sgtl5000";
++ model = "On-board Codec";
++ mux-ext-port = <5>;
++ mux-int-port = <1>;
++ cpu-dai = <&ssi1>;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ mipi_camera = <1>;
++ default_input = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&audmux {
++ status = "okay";
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
++ status = "okay";
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
++ status = "okay";
++
++ /* Pro baseboard model */
++ sgtl5000: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&clks IMX6QDL_CLK_CKO>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
++ VDDA-supply = <&reg_3p3v>;
++ VDDIO-supply = <&reg_3p3v>;
++ };
++
++ tc358743_mipi: tc358743_mipi@0f {
++ compatible = "tc358743_mipi";
++ reg = <0x0f>;
++ clocks = <&clks IMX6QDL_CLK_CKO>;
++ clock-names = "csi_mclk";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_mipi>;
++ rst-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
++ interrupts-extended = <&gpio2 10 IRQ_TYPE_LEVEL_LOW>;
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk = <27000000>;
++ mclk_source = <0>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
++ status = "okay";
++
++ ddc: imx6_hdmi_i2c@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++ hummingboard {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ /*
++ * 26 pin header GPIO description. The pins
++ * numbering as following -
++ * GPIO number | GPIO (bank,num) | PIN number
++ * ------------+-----------------+------------
++ * gpio1 | (1,1) | IO7
++ * gpio73 | (3,9) | IO11
++ * gpio72 | (3,8) | IO12
++ * gpio71 | (3,7) | IO13
++ * gpio70 | (3,6) | IO15
++ * gpio194 | (7,2) | IO16
++ * gpio195 | (7,3) | IO18
++ * gpio67 | (3,3) | IO22
++ *
++ * Notice the gpioX and GPIO (Y,Z) mapping forumla :
++ * X = (Y-1) * 32 + Z
++ */
++ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x400130b1
++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1
++ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1
++ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1
++ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1
++ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x400130b1
++ MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x400130b1
++ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1
++ >;
++ };
++
++ pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
++ >;
++ };
++
++ pinctrl_hummingboard_hdmi: hummingboard-hdmi {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard_mipi: hummingboard_mipi {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x17059
++ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x13059
++ >;
++ };
++
++ pinctrl_hummingboard_pwm1: pwm1grp {
++ fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
++ };
++
++ pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
++ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
++ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
++ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
++ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
++ >;
++ };
++
++ pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
++ fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
++ /*
++ * Similar to pinctrl_usbotg_2, but we want it
++ * pulled down for a fixed host connection.
++ */
++ fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>;
++ };
++
++ pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
++ fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usdhc2_pwr: hummingboard-usdhc2-pwr {
++ fsl,pins = <MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071
++ >;
++ };
++
++ pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
++ >;
++ };
++ };
++};
++
++&mipi_csi {
++ ipu_id = <0>;
++ csi_id = <0>;
++ v_channel = <0>;
++ lanes = <4>;
++ mipi_dphy_clk = /bits/ 8 <0x14>;
++ status = "okay";
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&usbh1 {
++ disable-over-current;
++ vbus-supply = <&reg_usbh1_vbus>;
++ status = "okay";
++};
++
++&usbotg {
++ disable-over-current;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
++ vbus-supply = <&reg_usbotg_vbus>;
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &pinctrl_hummingboard_usdhc2_aux
++ &pinctrl_hummingboard_usdhc2
++ >;
++
++ card-external-vcc-supply = <&reg_usdhc2_vbus>;
++ cd-gpios = <&gpio1 4 0>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -0,0 +1,643 @@
++/*
++ * Copyright 2014 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#define MX6QDL_GPR1 0x04 0x04 0x000 0x0 0x0
++#define MX6QDL_GPR6 0x18 0x18 0x000 0x0 0x0
++#define MX6QDL_GPR7 0x1c 0x1c 0x000 0x0 0x0
++
++/ {
++ memory {
++ reg = <0x10000000 0x20000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ heartbeat-led {
++ label = "Heartbeat";
++ gpios = <&gpio2 31 0>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ /* regulator for usb otg */
++ reg_usb_otg_vbus: usb_otg_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio3 22 0>;
++ enable-active-high;
++ };
++
++ /* regulator1 for pcie power-on-gpio */
++ pcie_power_on_gpio: regulator-pcie-power-on-gpio {
++ compatible = "regulator-fixed";
++ regulator-name = "regulator-pcie-power-on-gpio";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio2 24 0>;
++ enable-active-high;
++ };
++
++ /* regulator for usb hub1 */
++ reg_usb_h1_vbus: usb_h1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio7 8 0>;
++ enable-active-high;
++ };
++
++ /* regulator1 for wifi/bt */
++ awnh387_npoweron: regulator-awnh387-npoweron {
++ compatible = "regulator-fixed";
++ regulator-name = "regulator-awnh387-npoweron";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio7 12 0>;
++ enable-active-high;
++ };
++
++ /* regulator2 for wifi/bt */
++ awnh387_wifi_nreset: regulator-awnh387-wifi-nreset {
++ compatible = "regulator-fixed";
++ regulator-name = "regulator-awnh387-wifi-nreset";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio6 16 0>;
++ startup-delay-us = <10000>;
++ };
++
++ tsc2046reg: tsc2046-reg {
++ compatible = "regulator-fixed";
++ regulator-name = "tsc2046-reg";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ };
++
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb1 = &mxcfb2;
++ mxcfb2 = &mxcfb3;
++ mxcfb3 = &mxcfb4;
++ };
++
++ sound {
++ compatible = "fsl,imx-audio-wm8731";
++ model = "wm8731-audio";
++ ssi-controller = <&ssi2>;
++ src-port = <2>;
++ ext-port = <4>;
++ audio-codec = <&codec>;
++ audio-routing = "LOUT", "ROUT", "LLINEIN", "RLINEIN";
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ spdif-in;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "lcd";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb3: fb@2 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="1366x768M-18@60";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="1280x800M-18@60";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ lcd@0 {
++ compatible = "fsl,lcd";
++ ipu_id = <0>;
++ disp_id = <0>;
++ default_ifmt = "RGB24";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_lcd>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++
++ restart_poweroff {
++ compatible = "fsl,snvs-poweroff";
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++
++ hog {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6QDL_GPR1 0x48400005
++ /* ipu3 QoS */
++ MX6QDL_GPR6 0x007f007f
++ MX6QDL_GPR7 0x007f007f
++ /* SATA PWR */
++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
++ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000
++ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
++ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
++ /* SATA CTRL */
++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000
++ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
++ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000
++ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
++ /* POWER_BUTTON */
++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
++ >;
++ };
++ };
++
++ imx6q-cm-fx6 {
++ /* pins for eth0 */
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ >;
++ };
++
++ pinctrl_ipu1_lcd: ipu1grp-lcd {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
++ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
++ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
++ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
++ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000028
++ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
++ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
++ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
++ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
++ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
++ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
++ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
++ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
++ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
++ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
++ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
++ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
++ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
++ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
++ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
++ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
++ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
++ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
++ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
++ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
++ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
++ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
++ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
++ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
++ >;
++ };
++
++ /* pins for spi */
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
++ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1
++ >;
++ };
++
++ /* pins for nand */
++ pinctrl_gpmi_nand: gpminandgrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
++ >;
++ };
++
++ /* pins for i2c2 */
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ /* pins for i2c3 */
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ /* pins for console */
++ pinctrl_uart4: uart4grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
++ >;
++ };
++
++ /* pins for usb hub1 */
++ pinctrl_usbh1: usbh1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
++ >;
++ };
++
++ /* pins for usb otg */
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
++ >;
++ };
++
++ /* pins for wifi/bt */
++ pinctrl_usdhc1: usdhc1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
++ >;
++ };
++
++ /* pins for wifi/bt */
++ pinctrl_mrvl1: mrvl1grp {
++ fsl,pins = <
++ /* WIFI_PWR_RST */
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
++ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
++ >;
++ };
++
++ /* pins for tsc2046 pendown */
++ pinctrl_tsc2046: tsc2046grp {
++ fsl,pins = <
++ /* tsc2046 PENDOWN */
++ MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000
++ >;
++ };
++
++ /* pins for pcie */
++ pinctrl_pcie: pciegrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000
++ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
++ >;
++ };
++
++ /* pins for spdif */
++ pinctrl_spdif: spdifgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
++ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
++ >;
++ };
++
++ /* pins for audmux */
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059
++ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059
++ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059
++ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059
++ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059
++ /* master mode pin */
++ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x17059
++ >;
++ };
++
++ pinctrl_hdmi_hdcp: hdmihdcpgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_pwm3_1: pwm3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_flexcan1_1: flexcan1grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
++ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
++ >;
++ };
++ };
++};
++
++&cpu0 {
++ operating-points = <
++ /* kHz uV */
++ 1248000 1300000
++ 1200000 1275000
++ 1128000 1275000
++ 996000 1250000
++ 852000 1250000
++ 792000 1150000
++ 396000 975000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 1248000 1300000
++ 1200000 1275000
++ 1128000 1275000
++ 996000 1250000
++ 852000 1250000
++ 792000 1175000
++ 396000 1175000
++ >;
++};
++
++/* spi */
++&ecspi1 {
++ fsl,spi-num-chipselects = <2>;
++ cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi1>;
++ status = "okay";
++
++ flash: m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25px16", "st,m25p";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++
++ partition@0 {
++ label = "uboot";
++ reg = <0x0 0xc0000>;
++ };
++
++ partition@c0000 {
++ label = "uboot environment";
++ reg = <0xc0000 0x40000>;
++ };
++
++ partition@100000 {
++ label = "reserved";
++ reg = <0x100000 0x100000>;
++ };
++ };
++
++ /* touch controller */
++ touch: tsc2046@1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_tsc2046>;
++
++ compatible = "ti,tsc2046";
++ vcc-supply = <&tsc2046reg>;
++
++ reg = <1>; /* CS1 */
++ spi-max-frequency = <1500000>;
++
++ interrupt-parent = <&gpio2>;
++ interrupts = <15 0>;
++ pendown-gpio = <&gpio2 15 0>;
++
++ ti,x-min = /bits/ 16 <0x0>;
++ ti,x-max = /bits/ 16 <0x0fff>;
++ ti,y-min = /bits/ 16 <0x0>;
++ ti,y-max = /bits/ 16 <0x0fff>;
++
++ ti,x-plate-ohms = /bits/ 16 <180>;
++ ti,pressure-max = /bits/ 16 <255>;
++
++ ti,debounce-max = /bits/ 16 <30>;
++ ti,debounce-tol = /bits/ 16 <10>;
++ ti,debounce-rep = /bits/ 16 <1>;
++
++ linux,wakeup;
++ };
++};
++
++/* eth0 */
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii";
++ status = "okay";
++};
++
++/* nand */
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand>;
++ status = "okay";
++
++ partition@0 {
++ label = "linux";
++ reg = <0x0 0x800000>;
++ };
++
++ partition@800000 {
++ label = "rootfs";
++ reg = < 0x800000 0x0>;
++ };
++};
++
++/* i2c3 */
++&i2c3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++
++ eeprom@50 {
++ compatible = "at24,24c02";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++
++ codec: wm8731@1a {
++ compatible = "wlf,wm8731";
++ reg = <0x1a>;
++ clocks = <&clks 173>, <&clks 158>, <&clks 201>, <&clks 200>;
++ clock-names = "pll4", "imx-ssi.1", "cko", "cko2";
++ AVDD-supply = <&reg_3p3v>;
++ HPVDD-supply = <&reg_3p3v>;
++ DCVDD-supply = <&reg_3p3v>;
++ DBVDD-supply = <&reg_3p3v>;
++ };
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio1 26 0>;
++ vdd-supply = <&pcie_power_on_gpio>;
++ status = "okay";
++};
++
++/* console */
++&uart4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart4>;
++ status = "okay";
++};
++
++/* usb otg */
++&usbotg {
++ vbus-supply = <&reg_usb_otg_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ dr_mode = "otg";
++ status = "okay";
++};
++
++/* usb hub1 */
++&usbh1 {
++ vbus-supply = <&reg_usb_h1_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbh1>;
++ status = "okay";
++};
++
++/* wifi/bt */
++&usdhc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_mrvl1>;
++ non-removable;
++ vmmc-supply = <&awnh387_npoweron>;
++ vmmc_aux-supply = <&awnh387_wifi_nreset>;
++ status = "okay";
++};
++
++&ssi2 {
++ fsl,mode = "i2s-master";
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <1>;
++ status = "okay";
++};
++
++&hdmi_video {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_hdcp>;
++ fsl,hdcp;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif>;
++ status = "okay";
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -1,15 +1,102 @@
+ /*
+ * Copyright (C) 2014 Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ #include "imx6qdl-microsom.dtsi"
+ #include "imx6qdl-microsom-ar8035.dtsi"
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/gpio/gpio.h>
+
+ / {
++ aliases {
++ mmc0 = &usdhc2;
++ mmc1 = &usdhc1;
++ mxcfb0 = &mxcfb1;
++ };
++
++ chosen {
++ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw";
++ };
++
+ ir_recv: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio3 9 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cubox_i_ir>;
++ linux,rc-map-name = "rc-rc6-mce";
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-0 = <&pinctrl_gpio_key>;
++ pinctrl-names = "default";
++
++ button_0 {
++ label = "Button 0";
++ gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_0>;
++ };
++ };
++
++ pwmleds {
++ compatible = "pwm-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_pwm1>;
++
++ front {
++ active-low;
++ label = "imx6:red:front";
++ max-brightness = <248>;
++ pwms = <&pwm1 0 50000>;
++ };
+ };
+
+ regulators {
+@@ -48,11 +135,58 @@
+
+ sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+- model = "imx-spdif";
++ model = "Integrated SPDIF";
+ /* IMX6 doesn't implement this yet */
+ spdif-controller = <&spdif>;
+ spdif-out;
+ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
++ status = "okay";
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_i2c2>;
++ status = "okay";
++
++ ddc: imx6_hdmi_i2c@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
+ };
+
+ &i2c3 {
+@@ -64,11 +198,25 @@
+ rtc: pcf8523@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
++ nxp,12p5_pf;
+ };
+ };
+
+ &iomuxc {
+ cubox_i {
++ pinctrl_cubox_i_hdmi: cubox-i-hdmi {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_cubox_i_i2c2: cubox-i-i2c2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
+ pinctrl_cubox_i_i2c3: cubox-i-i2c3 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+@@ -82,21 +230,40 @@
+ >;
+ };
+
++ pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led {
++ fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>;
++ };
++
+ pinctrl_cubox_i_spdif: cubox-i-spdif {
+ fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
+ };
+
++ pinctrl_cubox_i_usbh1: cubox-i-usbh1 {
++ fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>;
++ };
++
+ pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
+ fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
+ };
+
++ pinctrl_cubox_i_usbotg: cubox-i-usbotg {
++ /*
++ * The Cubox-i pulls ID low, but as it's pointless
++ * leaving it as a pull-up, even if it is just 10uA.
++ */
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
++ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
++ >;
++ };
++
+ pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
+ fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x4001b0b0>;
+ };
+
+ pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux {
+ fsl,pins = <
+- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071
+ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071
+ >;
+ };
+@@ -111,9 +278,19 @@
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
+ >;
+ };
++
++ pinctrl_gpio_key: gpio-key {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059
++ >;
++ };
+ };
+ };
+
++&pwm1 {
++ status = "okay";
++};
++
+ &spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cubox_i_spdif>;
+@@ -121,11 +298,15 @@
+ };
+
+ &usbh1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_usbh1>;
+ vbus-supply = <&reg_usbh1_vbus>;
+ status = "okay";
+ };
+
+ &usbotg {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_cubox_i_usbotg>;
+ vbus-supply = <&reg_usbotg_vbus>;
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -10,6 +10,9 @@
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
++#include <dt-bindings/clock/imx6qdl-clock.h>
++#include <dt-bindings/gpio/gpio.h>
++
+ #include "skeleton.dtsi"
+
+ / {
+@@ -24,6 +27,11 @@
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
++ ipu0 = &ipu1;
++ mmc0 = &usdhc1;
++ mmc1 = &usdhc2;
++ mmc2 = &usdhc3;
++ mmc3 = &usdhc4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+@@ -33,13 +41,13 @@
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
++ usbphy0 = &usbphy1;
++ usbphy1 = &usbphy2;
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+@@ -72,14 +80,28 @@
+ interrupt-parent = <&intc>;
+ ranges;
+
++ caam_sm: caam-sm@00100000 {
++ compatible = "fsl,imx6q-caam-sm";
++ reg = <0x00100000 0x3fff>;
++ };
++
+ dma_apbh: dma-apbh@00110000 {
+ compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x00110000 0x2000>;
+- interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
++ interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
++ <0 13 IRQ_TYPE_LEVEL_HIGH>,
++ <0 13 IRQ_TYPE_LEVEL_HIGH>,
++ <0 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+- clocks = <&clks 106>;
++ clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
++ };
++
++ irq_sec_vio: caam_secvio {
++ compatible = "fsl,imx6q-caam-secvio";
++ interrupts = <0 20 0x04>;
++ secvio_src = <0x8000001d>;
+ };
+
+ gpmi: gpmi-nand@00112000 {
+@@ -88,10 +110,13 @@
+ #size-cells = <1>;
+ reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+ reg-names = "gpmi-nand", "bch";
+- interrupts = <0 15 0x04>;
++ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+- clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+- <&clks 150>, <&clks 149>;
++ clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
++ <&clks IMX6QDL_CLK_GPMI_APB>,
++ <&clks IMX6QDL_CLK_GPMI_BCH>,
++ <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
++ <&clks IMX6QDL_CLK_PER1_BCH>;
+ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+ "gpmi_bch_apb", "per1_bch";
+ dmas = <&dma_apbh 0>;
+@@ -103,38 +128,88 @@
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x00a00600 0x20>;
+ interrupts = <1 13 0xf01>;
+- clocks = <&clks 15>;
++ clocks = <&clks IMX6QDL_CLK_TWD>;
+ };
+
+ L2: l2-cache@00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+- interrupts = <0 92 0x04>;
++ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
++ arm,dynamic-clk-gating;
++ arm,standby-mode;
+ };
+
+ pcie: pcie@0x01000000 {
+ compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
+- reg = <0x01ffc000 0x4000>; /* DBI */
++ reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>;
++ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+- ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
+- 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
++ ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
+ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+- interrupts = <0 123 0x04>;
+- clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
+- clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
++ interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>,
++ <&clks IMX6QDL_CLK_SATA_REF_100M>,
++ <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>;
++ clock-names = "pcie_phy", "ref_100m", "pcie_bus", "pcie";
+ status = "disabled";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+- interrupts = <0 94 0x04>;
++ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ hdmi_core: hdmi_core@00120000 {
++ compatible = "fsl,imx6q-hdmi-core";
++ reg = <0x00120000 0x9000>;
++ clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
++ <&clks IMX6QDL_CLK_HDMI_IAHB>,
++ <&clks IMX6QDL_CLK_HSI_TX>;
++ clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
++ status = "disabled";
++ };
++
++ hdmi_video: hdmi_video@020e0000 {
++ compatible = "fsl,imx6q-hdmi-video";
++ reg = <0x020e0000 0x1000>;
++ reg-names = "hdmi_gpr";
++ interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
++ <&clks IMX6QDL_CLK_HDMI_IAHB>,
++ <&clks IMX6QDL_CLK_HSI_TX>;
++ clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
++ status = "disabled";
++ };
++
++ hdmi_audio: hdmi_audio@00120000 {
++ compatible = "fsl,imx6q-hdmi-audio";
++ clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>,
++ <&clks IMX6QDL_CLK_HDMI_IAHB>,
++ <&clks IMX6QDL_CLK_HSI_TX>;
++ clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core";
++ dmas = <&sdma 2 24 0>;
++ dma-names = "tx";
++ status = "disabled";
++ };
++
++ hdmi_cec: hdmi_cec@00120000 {
++ compatible = "fsl,imx6q-hdmi-cec";
++ interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
+ };
+
+ aips-bus@02000000 { /* AIPS1 */
+@@ -154,20 +229,20 @@
+ spdif: spdif@02004000 {
+ compatible = "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+- interrupts = <0 52 0x04>;
++ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&sdma 14 18 0>,
+ <&sdma 15 18 0>;
+ dma-names = "rx", "tx";
+- clocks = <&clks 197>, <&clks 3>,
+- <&clks 197>, <&clks 107>,
+- <&clks 0>, <&clks 118>,
+- <&clks 0>, <&clks 139>,
+- <&clks 0>;
++ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
++ <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
++ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
++ <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
++ <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+- "rxtx7";
++ "rxtx7", "dma";
+ status = "disabled";
+ };
+
+@@ -176,8 +251,9 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+- interrupts = <0 31 0x04>;
+- clocks = <&clks 112>, <&clks 112>;
++ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ECSPI1>,
++ <&clks IMX6QDL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+@@ -187,8 +263,9 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+- interrupts = <0 32 0x04>;
+- clocks = <&clks 113>, <&clks 113>;
++ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ECSPI2>,
++ <&clks IMX6QDL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+@@ -198,8 +275,9 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+- interrupts = <0 33 0x04>;
+- clocks = <&clks 114>, <&clks 114>;
++ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ECSPI3>,
++ <&clks IMX6QDL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+@@ -209,8 +287,9 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+- interrupts = <0 34 0x04>;
+- clocks = <&clks 115>, <&clks 115>;
++ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ECSPI4>,
++ <&clks IMX6QDL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+@@ -218,8 +297,9 @@
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+- interrupts = <0 26 0x04>;
+- clocks = <&clks 160>, <&clks 161>;
++ interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
++ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+ dma-names = "rx", "tx";
+@@ -227,15 +307,28 @@
+ };
+
+ esai: esai@02024000 {
++ compatible = "fsl,imx35-esai";
+ reg = <0x02024000 0x4000>;
+- interrupts = <0 51 0x04>;
++ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
++ <&clks IMX6QDL_CLK_ESAI_MEM>,
++ <&clks IMX6QDL_CLK_ESAI_EXTAL>,
++ <&clks IMX6QDL_CLK_ESAI_IPG>,
++ <&clks IMX6QDL_CLK_SPBA>;
++ clock-names = "core", "mem", "extal", "fsys", "dma";
++ dmas = <&sdma 23 21 0>,
++ <&sdma 24 21 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
+ };
+
+ ssi1: ssi@02028000 {
+ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+ reg = <0x02028000 0x4000>;
+- interrupts = <0 46 0x04>;
+- clocks = <&clks 178>;
++ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
++ <&clks IMX6QDL_CLK_SSI1>;
++ clock-names = "ipg", "baud";
+ dmas = <&sdma 37 1 0>,
+ <&sdma 38 1 0>;
+ dma-names = "rx", "tx";
+@@ -247,8 +340,10 @@
+ ssi2: ssi@0202c000 {
+ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+ reg = <0x0202c000 0x4000>;
+- interrupts = <0 47 0x04>;
+- clocks = <&clks 179>;
++ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
++ <&clks IMX6QDL_CLK_SSI2>;
++ clock-names = "ipg", "baud";
+ dmas = <&sdma 41 1 0>,
+ <&sdma 42 1 0>;
+ dma-names = "rx", "tx";
+@@ -260,8 +355,10 @@
+ ssi3: ssi@02030000 {
+ compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
+ reg = <0x02030000 0x4000>;
+- interrupts = <0 48 0x04>;
+- clocks = <&clks 180>;
++ interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
++ <&clks IMX6QDL_CLK_SSI3>;
++ clock-names = "ipg", "baud";
+ dmas = <&sdma 45 1 0>,
+ <&sdma 46 1 0>;
+ dma-names = "rx", "tx";
+@@ -271,8 +368,28 @@
+ };
+
+ asrc: asrc@02034000 {
++ compatible = "fsl,imx53-asrc";
+ reg = <0x02034000 0x4000>;
+- interrupts = <0 50 0x04>;
++ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
++ <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
++ <&clks IMX6QDL_CLK_SPBA>;
++ clock-names = "mem", "ipg", "asrck_0",
++ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
++ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
++ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
++ "asrck_d", "asrck_e", "asrck_f", "dma";
++ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
++ <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
++ dma-names = "rxa", "rxb", "rxc",
++ "txa", "txb", "txc";
++ fsl,asrc-rate = <48000>;
++ fsl,asrc-width = <16>;
++ status = "okay";
+ };
+
+ spba@0203c000 {
+@@ -281,8 +398,20 @@
+ };
+
+ vpu: vpu@02040000 {
++ compatible = "fsl,imx6-vpu";
+ reg = <0x02040000 0x3c000>;
+- interrupts = <0 3 0x04 0 12 0x04>;
++ reg-names = "vpu_regs";
++ interrupts = <0 3 IRQ_TYPE_EDGE_RISING>,
++ <0 12 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
++ clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
++ <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
++ <&clks IMX6QDL_CLK_OCRAM>;
++ clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
++ iramsize = <0x21000>;
++ iram = <&ocram>;
++ resets = <&src 1>;
++ power-domains = <&gpc 1>;
+ };
+
+ aipstz@0207c000 { /* AIPSTZ1 */
+@@ -293,8 +422,9 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+- interrupts = <0 83 0x04>;
+- clocks = <&clks 62>, <&clks 145>;
++ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPG>,
++ <&clks IMX6QDL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+ };
+
+@@ -302,8 +432,9 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+- interrupts = <0 84 0x04>;
+- clocks = <&clks 62>, <&clks 146>;
++ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPG>,
++ <&clks IMX6QDL_CLK_PWM2>;
+ clock-names = "ipg", "per";
+ };
+
+@@ -311,8 +442,9 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+- interrupts = <0 85 0x04>;
+- clocks = <&clks 62>, <&clks 147>;
++ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPG>,
++ <&clks IMX6QDL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+ };
+
+@@ -320,39 +452,48 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+- interrupts = <0 86 0x04>;
+- clocks = <&clks 62>, <&clks 148>;
++ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPG>,
++ <&clks IMX6QDL_CLK_PWM4>;
+ clock-names = "ipg", "per";
+ };
+
+- can1: flexcan@02090000 {
++ flexcan1: can@02090000 {
+ compatible = "fsl,imx6q-flexcan";
+ reg = <0x02090000 0x4000>;
+- interrupts = <0 110 0x04>;
+- clocks = <&clks 108>, <&clks 109>;
++ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
++ <&clks IMX6QDL_CLK_CAN1_SERIAL>;
+ clock-names = "ipg", "per";
++ stop-mode = <&gpr 0x34 28 0x10 17>;
++ status = "disabled";
+ };
+
+- can2: flexcan@02094000 {
++ flexcan2: can@02094000 {
+ compatible = "fsl,imx6q-flexcan";
+ reg = <0x02094000 0x4000>;
+- interrupts = <0 111 0x04>;
+- clocks = <&clks 110>, <&clks 111>;
++ interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
++ <&clks IMX6QDL_CLK_CAN2_SERIAL>;
+ clock-names = "ipg", "per";
++ stop-mode = <&gpr 0x34 29 0x10 18>;
++ status = "disabled";
+ };
+
+ gpt: gpt@02098000 {
+ compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
+ reg = <0x02098000 0x4000>;
+- interrupts = <0 55 0x04>;
+- clocks = <&clks 119>, <&clks 120>;
++ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
++ <&clks IMX6QDL_CLK_GPT_IPG_PER>;
+ clock-names = "ipg", "per";
+ };
+
+ gpio1: gpio@0209c000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+- interrupts = <0 66 0x04 0 67 0x04>;
++ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
++ <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -362,7 +503,8 @@
+ gpio2: gpio@020a0000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+- interrupts = <0 68 0x04 0 69 0x04>;
++ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
++ <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -372,7 +514,8 @@
+ gpio3: gpio@020a4000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+- interrupts = <0 70 0x04 0 71 0x04>;
++ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
++ <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -382,7 +525,8 @@
+ gpio4: gpio@020a8000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+- interrupts = <0 72 0x04 0 73 0x04>;
++ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
++ <0 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -392,7 +536,8 @@
+ gpio5: gpio@020ac000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+- interrupts = <0 74 0x04 0 75 0x04>;
++ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
++ <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -402,7 +547,8 @@
+ gpio6: gpio@020b0000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020b0000 0x4000>;
+- interrupts = <0 76 0x04 0 77 0x04>;
++ interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
++ <0 77 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -412,7 +558,8 @@
+ gpio7: gpio@020b4000 {
+ compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
+ reg = <0x020b4000 0x4000>;
+- interrupts = <0 78 0x04 0 79 0x04>;
++ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
++ <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -421,35 +568,38 @@
+
+ kpp: kpp@020b8000 {
+ reg = <0x020b8000 0x4000>;
+- interrupts = <0 82 0x04>;
++ interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+- interrupts = <0 80 0x04>;
+- clocks = <&clks 0>;
++ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_DUMMY>;
+ };
+
+ wdog2: wdog@020c0000 {
+ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+- interrupts = <0 81 0x04>;
+- clocks = <&clks 0>;
++ interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_DUMMY>;
+ status = "disabled";
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6q-ccm";
+ reg = <0x020c4000 0x4000>;
+- interrupts = <0 87 0x04 0 88 0x04>;
++ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
++ <0 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+- interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
++ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
++ <0 54 IRQ_TYPE_LEVEL_HIGH>,
++ <0 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ regulator-1p1@110 {
+ compatible = "fsl,anatop-regulator";
+@@ -495,7 +645,7 @@
+
+ reg_arm: regulator-vddcore@140 {
+ compatible = "fsl,anatop-regulator";
+- regulator-name = "cpu";
++ regulator-name = "vddarm";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+@@ -508,6 +658,8 @@
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
++ regulator-allow-bypass;
++ linux,phandle = <&reg_arm>;
+ };
+
+ reg_pu: regulator-vddpu@140 {
+@@ -515,7 +667,8 @@
+ regulator-name = "vddpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+- regulator-always-on;
++ regulator-enable-ramp-delay = <150>;
++ regulator-boot-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <9>;
+ anatop-vol-bit-width = <5>;
+@@ -525,6 +678,7 @@
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
++ regulator-allow-bypass;
+ };
+
+ reg_soc: regulator-vddsoc@140 {
+@@ -542,28 +696,50 @@
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
++ regulator-allow-bypass;
++ linux,phandle = <&reg_soc>;
+ };
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx6q-tempmon";
+- interrupts = <0 49 0x04>;
++ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon = <&anatop>;
+ fsl,tempmon-data = <&ocotp>;
++ clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+ };
+
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+- interrupts = <0 44 0x04>;
+- clocks = <&clks 182>;
++ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USBPHY1>;
++ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+- interrupts = <0 45 0x04>;
+- clocks = <&clks 183>;
++ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USBPHY2>;
++ fsl,anatop = <&anatop>;
++ };
++
++ usbphy_nop1: usbphy_nop1 {
++ compatible = "usb-nop-xceiv";
++ clocks = <&clks IMX6QDL_CLK_USBPHY1>;
++ clock-names = "main_clk";
++ };
++
++ usbphy_nop2: usbphy_nop2 {
++ compatible = "usb-nop-xceiv";
++ clocks = <&clks IMX6QDL_CLK_USBPHY1>;
++ clock-names = "main_clk";
++ };
++
++ caam_snvs: caam-snvs@020cc000 {
++ compatible = "fsl,imx6q-caam-snvs";
++ reg = <0x020cc000 0x4000>;
+ };
+
+ snvs@020cc000 {
+@@ -575,31 +751,42 @@
+ snvs-rtc-lp@34 {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ reg = <0x34 0x58>;
+- interrupts = <0 19 0x04 0 20 0x04>;
++ interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
++ <0 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ epit1: epit@020d0000 { /* EPIT1 */
+ reg = <0x020d0000 0x4000>;
+- interrupts = <0 56 0x04>;
++ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit@020d4000 { /* EPIT2 */
+ reg = <0x020d4000 0x4000>;
+- interrupts = <0 57 0x04>;
++ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6q-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+- interrupts = <0 91 0x04 0 96 0x04>;
++ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
++ <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+- interrupts = <0 89 0x04 0 90 0x04>;
++ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
++ <0 90 IRQ_TYPE_LEVEL_HIGH>;
++ pu-supply = <&reg_pu>;
++ clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
++ <&clks IMX6QDL_CLK_GPU3D_SHADER>,
++ <&clks IMX6QDL_CLK_GPU2D_CORE>,
++ <&clks IMX6QDL_CLK_GPU2D_AXI>,
++ <&clks IMX6QDL_CLK_OPENVG_AXI>,
++ <&clks IMX6QDL_CLK_VPU_AXI>;
++ #power-domain-cells = <1>;
+ };
+
+ gpr: iomuxc-gpr@020e0000 {
+@@ -610,750 +797,11 @@
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
+ reg = <0x020e0000 0x4000>;
+-
+- audmux {
+- pinctrl_audmux_1: audmux-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
+- MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
+- MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
+- MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+- >;
+- };
+-
+- pinctrl_audmux_2: audmux-2 {
+- fsl,pins = <
+- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
+- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
+- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
+- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+- >;
+- };
+-
+- pinctrl_audmux_3: audmux-3 {
+- fsl,pins = <
+- MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
+- MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
+- MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
+- >;
+- };
+- };
+-
+- ecspi1 {
+- pinctrl_ecspi1_1: ecspi1grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+- MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+- MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+- >;
+- };
+-
+- pinctrl_ecspi1_2: ecspi1grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+- MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+- MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+- >;
+- };
+- };
+-
+- ecspi3 {
+- pinctrl_ecspi3_1: ecspi3grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+- MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+- MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+- >;
+- };
+- };
+-
+- enet {
+- pinctrl_enet_1: enetgrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+- >;
+- };
+-
+- pinctrl_enet_2: enetgrp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
+- MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
+- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+- >;
+- };
+-
+- pinctrl_enet_3: enetgrp-3 {
+- fsl,pins = <
+- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
+- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
+- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
+- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
+- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
+- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
+- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+- >;
+- };
+- };
+-
+- esai {
+- pinctrl_esai_1: esaigrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
+- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
+- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
+- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
+- MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
+- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
+- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
+- MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
+- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
+- >;
+- };
+-
+- pinctrl_esai_2: esaigrp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
+- MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
+- MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
+- MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
+- MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
+- MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
+- MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
+- MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
+- MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
+- MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
+- >;
+- };
+- };
+-
+- flexcan1 {
+- pinctrl_flexcan1_1: flexcan1grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+- MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+- >;
+- };
+-
+- pinctrl_flexcan1_2: flexcan1grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
+- MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+- >;
+- };
+- };
+-
+- flexcan2 {
+- pinctrl_flexcan2_1: flexcan2grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+- >;
+- };
+- };
+-
+- gpmi-nand {
+- pinctrl_gpmi_nand_1: gpmi-nand-1 {
+- fsl,pins = <
+- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
+- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
+- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
+- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
+- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
+- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
+- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
+- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
+- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
+- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
+- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
+- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
+- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
+- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
+- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
+- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
+- >;
+- };
+- };
+-
+- hdmi_hdcp {
+- pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
+- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
+- MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
+- MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
+- >;
+- };
+- };
+-
+- hdmi_cec {
+- pinctrl_hdmi_cec_1: hdmicecgrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+- >;
+- };
+-
+- pinctrl_hdmi_cec_2: hdmicecgrp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+- >;
+- };
+- };
+-
+- i2c1 {
+- pinctrl_i2c1_1: i2c1grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+- MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_i2c1_2: i2c1grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+- MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+- >;
+- };
+- };
+-
+- i2c2 {
+- pinctrl_i2c2_1: i2c2grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+- MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_i2c2_2: i2c2grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_i2c2_3: i2c2grp-3 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+- MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+- >;
+- };
+- };
+-
+- i2c3 {
+- pinctrl_i2c3_1: i2c3grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_i2c3_2: i2c3grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+- MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_i2c3_3: i2c3grp-3 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+- MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+- >;
+- };
+-
+- pinctrl_i2c3_4: i2c3grp-4 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+- >;
+- };
+- };
+-
+- ipu1 {
+- pinctrl_ipu1_1: ipu1grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+- MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
+- MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
+- MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
+- MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
+- MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
+- MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
+- MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
+- MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
+- MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
+- MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
+- MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
+- MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
+- MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
+- MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
+- MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
+- MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
+- MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
+- MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
+- MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
+- MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
+- MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
+- MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
+- MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
+- MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
+- MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
+- MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
+- MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
+- MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
+- >;
+- };
+-
+- pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
+- fsl,pins = <
+- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+- MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+- >;
+- };
+-
+- pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
+- fsl,pins = <
+- MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
+- MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
+- MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
+- MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
+- MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
+- MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
+- MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
+- MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
+- MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+- MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+- MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+- MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+- MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+- MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+- MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+- MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+- MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+- MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+- MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+- >;
+- };
+- };
+-
+- mlb {
+- pinctrl_mlb_1: mlbgrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
+- MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
+- MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
+- >;
+- };
+-
+- pinctrl_mlb_2: mlbgrp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
+- MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
+- MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
+- >;
+- };
+- };
+-
+- pwm0 {
+- pinctrl_pwm0_1: pwm0grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
+- >;
+- };
+- };
+-
+- pwm3 {
+- pinctrl_pwm3_1: pwm3grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+- >;
+- };
+- };
+-
+- spdif {
+- pinctrl_spdif_1: spdifgrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
+- >;
+- };
+-
+- pinctrl_spdif_2: spdifgrp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
+- MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+- >;
+- };
+-
+- pinctrl_spdif_3: spdifgrp-3 {
+- fsl,pins = <
+- MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
+- >;
+- };
+- };
+-
+- uart1 {
+- pinctrl_uart1_1: uart1grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+- MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- uart2 {
+- pinctrl_uart2_1: uart2grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+- MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+- >;
+- };
+-
+- pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
+- fsl,pins = <
+- MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
+- MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
+- MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
+- MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
+- >;
+- };
+- };
+-
+- uart3 {
+- pinctrl_uart3_1: uart3grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
+- MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
+- MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
+- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+- >;
+- };
+-
+- pinctrl_uart3_2: uart3grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
+- MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
+- MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+- MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
+- >;
+- };
+- };
+-
+- uart4 {
+- pinctrl_uart4_1: uart4grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- usbotg {
+- pinctrl_usbotg_1: usbotggrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg_2: usbotggrp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+- >;
+- };
+- };
+-
+- usbh2 {
+- pinctrl_usbh2_1: usbh2grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
+- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
+- >;
+- };
+-
+- pinctrl_usbh2_2: usbh2grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
+- >;
+- };
+- };
+-
+- usbh3 {
+- pinctrl_usbh3_1: usbh3grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
+- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
+- >;
+- };
+-
+- pinctrl_usbh3_2: usbh3grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
+- >;
+- };
+- };
+-
+- usdhc1 {
+- pinctrl_usdhc1_1: usdhc1grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+- MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
+- MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
+- MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
+- MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc1_2: usdhc1grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+- MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+- MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+- MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+- MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+- MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+- >;
+- };
+- };
+-
+- usdhc2 {
+- pinctrl_usdhc2_1: usdhc2grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+- MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
+- MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
+- MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
+- MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc2_2: usdhc2grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+- MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+- MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+- MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+- MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+- >;
+- };
+- };
+-
+- usdhc3 {
+- pinctrl_usdhc3_1: usdhc3grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { /* 100Mhz */
+- fsl,pins = <
+- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
+- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
+- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
+- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
+- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
+- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
+- >;
+- };
+-
+- pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { /* 200Mhz */
+- fsl,pins = <
+- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
+- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
+- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+- MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
+- MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
+- MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
+- MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
+- >;
+- };
+-
+- pinctrl_usdhc3_2: usdhc3grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+- MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+- MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+- MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+- MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+- MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+- >;
+- };
+- };
+-
+- usdhc4 {
+- pinctrl_usdhc4_1: usdhc4grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+- MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+- MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+- MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+- MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc4_2: usdhc4grp-2 {
+- fsl,pins = <
+- MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
+- MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
+- MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+- MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+- MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+- MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+- >;
+- };
+- };
+-
+- weim {
+- pinctrl_weim_cs0_1: weim_cs0grp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
+- >;
+- };
+-
+- pinctrl_weim_nor_1: weim_norgrp-1 {
+- fsl,pins = <
+- MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+- MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+- MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+- /* data */
+- MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+- MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+- MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+- MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+- MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+- MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+- MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+- MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+- MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+- MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+- MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+- MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+- MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+- MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+- MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+- MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+- /* address */
+- MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+- MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+- MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+- MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+- MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+- MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+- MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+- MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+- MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+- MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+- MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+- MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+- MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+- MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+- MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+- MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+- MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+- MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+- MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+- MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+- MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+- MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+- MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+- MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+- >;
+- };
+- };
+ };
+
+ ldb: ldb@020e0008 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+- compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
+ gpr = <&gpr>;
+ status = "disabled";
+
+@@ -1369,20 +817,31 @@
+ };
+
+ dcic1: dcic@020e4000 {
++ compatible = "fsl,imx6q-dcic";
+ reg = <0x020e4000 0x4000>;
+- interrupts = <0 124 0x04>;
++ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>;
++ clock-names = "dcic", "disp-axi";
++ gpr = <&gpr>;
++ status = "disabled";
+ };
+
+ dcic2: dcic@020e8000 {
++ compatible = "fsl,imx6q-dcic";
+ reg = <0x020e8000 0x4000>;
+- interrupts = <0 125 0x04>;
++ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>;
++ clock-names = "dcic", "disp-axi";
++ gpr = <&gpr>;
++ status = "disabled";
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+- interrupts = <0 2 0x04>;
+- clocks = <&clks 155>, <&clks 155>;
++ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_SDMA>,
++ <&clks IMX6QDL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+@@ -1396,9 +855,29 @@
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+- caam@02100000 {
+- reg = <0x02100000 0x40000>;
+- interrupts = <0 105 0x04 0 106 0x04>;
++ crypto: caam@2100000 {
++ compatible = "fsl,sec-v4.0";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x2100000 0x40000>;
++ ranges = <0 0x2100000 0x40000>;
++ interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
++ clocks = <&clks IMX6QDL_CAAM_MEM>, <&clks IMX6QDL_CAAM_ACLK>, <&clks IMX6QDL_CAAM_IPG> ,<&clks IMX6QDL_CLK_EIM_SLOW>;
++ clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
++
++ sec_jr0: jr0@1000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x1000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 105 0x4>;
++ };
++
++ sec_jr1: jr1@2000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x2000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 106 0x4>;
++ };
+ };
+
+ aipstz@0217c000 { /* AIPSTZ2 */
+@@ -1408,18 +887,19 @@
+ usbotg: usb@02184000 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+- interrupts = <0 43 0x04>;
+- clocks = <&clks 162>;
++ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
++ fsl,anatop = <&anatop>;
+ status = "disabled";
+ };
+
+ usbh1: usb@02184200 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+- interrupts = <0 40 0x04>;
+- clocks = <&clks 162>;
++ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+ status = "disabled";
+@@ -1428,18 +908,24 @@
+ usbh2: usb@02184400 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184400 0x200>;
+- interrupts = <0 41 0x04>;
+- clocks = <&clks 162>;
++ interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbmisc = <&usbmisc 2>;
++ phy_type = "hsic";
++ fsl,usbphy = <&usbphy_nop1>;
++ fsl,anatop = <&anatop>;
+ status = "disabled";
+ };
+
+ usbh3: usb@02184600 {
+ compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+ reg = <0x02184600 0x200>;
+- interrupts = <0 42 0x04>;
+- clocks = <&clks 162>;
++ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ fsl,usbmisc = <&usbmisc 3>;
++ phy_type = "hsic";
++ fsl,usbphy = <&usbphy_nop2>;
++ fsl,anatop = <&anatop>;
+ status = "disabled";
+ };
+
+@@ -1447,28 +933,43 @@
+ #index-cells = <1>;
+ compatible = "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+- clocks = <&clks 162>;
++ clocks = <&clks IMX6QDL_CLK_USBOH3>;
+ };
+
+ fec: ethernet@02188000 {
+ compatible = "fsl,imx6q-fec";
+ reg = <0x02188000 0x4000>;
+- interrupts = <0 118 0x04 0 119 0x04>;
+- clocks = <&clks 117>, <&clks 117>, <&clks 190>;
++ interrupts-extended =
++ <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
++ <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_ENET>,
++ <&clks IMX6QDL_CLK_ENET>,
++ <&clks IMX6QDL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp";
++ local-mac-address = [FF FF FF FF FF FF];
+ status = "disabled";
+ };
+
+- mlb@0218c000 {
++ mlb: mlb@0218c000 {
++ compatible = "fsl,imx6q-mlb150";
+ reg = <0x0218c000 0x4000>;
+- interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
++ interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
++ <0 117 IRQ_TYPE_LEVEL_HIGH>,
++ <0 126 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_MLB>,
++ <&clks IMX6QDL_CLK_PLL8_MLB>;
++ clock-names = "mlb", "pll8_mlb";
++ iram = <&ocram>;
++ status = "disabled";
+ };
+
+ usdhc1: usdhc@02190000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02190000 0x4000>;
+- interrupts = <0 22 0x04>;
+- clocks = <&clks 163>, <&clks 163>, <&clks 163>;
++ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USDHC1>,
++ <&clks IMX6QDL_CLK_USDHC1>,
++ <&clks IMX6QDL_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+@@ -1477,8 +978,10 @@
+ usdhc2: usdhc@02194000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02194000 0x4000>;
+- interrupts = <0 23 0x04>;
+- clocks = <&clks 164>, <&clks 164>, <&clks 164>;
++ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USDHC2>,
++ <&clks IMX6QDL_CLK_USDHC2>,
++ <&clks IMX6QDL_CLK_USDHC2>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+@@ -1487,8 +990,10 @@
+ usdhc3: usdhc@02198000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x02198000 0x4000>;
+- interrupts = <0 24 0x04>;
+- clocks = <&clks 165>, <&clks 165>, <&clks 165>;
++ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USDHC3>,
++ <&clks IMX6QDL_CLK_USDHC3>,
++ <&clks IMX6QDL_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+@@ -1497,8 +1002,10 @@
+ usdhc4: usdhc@0219c000 {
+ compatible = "fsl,imx6q-usdhc";
+ reg = <0x0219c000 0x4000>;
+- interrupts = <0 25 0x04>;
+- clocks = <&clks 166>, <&clks 166>, <&clks 166>;
++ interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_USDHC4>,
++ <&clks IMX6QDL_CLK_USDHC4>,
++ <&clks IMX6QDL_CLK_USDHC4>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+@@ -1509,8 +1016,8 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+- interrupts = <0 36 0x04>;
+- clocks = <&clks 125>;
++ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_I2C1>;
+ status = "disabled";
+ };
+
+@@ -1519,8 +1026,8 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+- interrupts = <0 37 0x04>;
+- clocks = <&clks 126>;
++ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_I2C2>;
+ status = "disabled";
+ };
+
+@@ -1529,8 +1036,8 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+- interrupts = <0 38 0x04>;
+- clocks = <&clks 127>;
++ interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_I2C3>;
+ status = "disabled";
+ };
+
+@@ -1538,6 +1045,11 @@
+ reg = <0x021ac000 0x4000>;
+ };
+
++ mmdc0-1@021b0000 { /* MMDC0-1 */
++ compatible = "fsl,imx6q-mmdc-combine";
++ reg = <0x021b0000 0x8000>;
++ };
++
+ mmdc0: mmdc@021b0000 { /* MMDC0 */
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+@@ -1550,23 +1062,30 @@
+ weim: weim@021b8000 {
+ compatible = "fsl,imx6q-weim";
+ reg = <0x021b8000 0x4000>;
+- interrupts = <0 14 0x04>;
+- clocks = <&clks 196>;
++ interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
+ };
+
+- ocotp: ocotp@021bc000 {
+- compatible = "fsl,imx6q-ocotp", "syscon";
++ ocotp: ocotp-ctrl@021bc000 {
++ compatible = "syscon";
+ reg = <0x021bc000 0x4000>;
++ clocks = <&clks IMX6QDL_CLK_IIM>;
++ };
++
++ ocotp-fuse@021bc000 {
++ compatible = "fsl,imx6q-ocotp";
++ reg = <0x021bc000 0x4000>;
++ clocks = <&clks IMX6QDL_CLK_IIM>;
+ };
+
+ tzasc@021d0000 { /* TZASC1 */
+ reg = <0x021d0000 0x4000>;
+- interrupts = <0 108 0x04>;
++ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ tzasc@021d4000 { /* TZASC2 */
+ reg = <0x021d4000 0x4000>;
+- interrupts = <0 109 0x04>;
++ interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ audmux: audmux@021d8000 {
+@@ -1575,8 +1094,20 @@
+ status = "disabled";
+ };
+
+- mipi@021dc000 { /* MIPI-CSI */
++ mipi_csi: mipi_csi@021dc000 { /* MIPI-CSI */
++ compatible = "fsl,imx6q-mipi-csi2";
+ reg = <0x021dc000 0x4000>;
++ interrupts = <0 100 0x04>, <0 101 0x04>;
++ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
++ <&clks IMX6QDL_CLK_EMI_SEL>,
++ <&clks IMX6QDL_CLK_VIDEO_27M>;
++ /* Note: clks 138 is hsi_tx, however, the dphy_c
++ * hsi_tx and pll_refclk use the same clk gate.
++ * In current clk driver, open/close clk gate do
++ * use hsi_tx for a temporary debug purpose.
++ */
++ clock-names = "dphy_clk", "pixel_clk", "cfg_clk";
++ status = "disabled";
+ };
+
+ mipi@021e0000 { /* MIPI-DSI */
+@@ -1584,15 +1115,19 @@
+ };
+
+ vdoa@021e4000 {
++ compatible = "fsl,imx6q-vdoa";
+ reg = <0x021e4000 0x4000>;
+- interrupts = <0 18 0x04>;
++ interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_VDOA>;
++ iram = <&ocram>;
+ };
+
+ uart2: serial@021e8000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021e8000 0x4000>;
+- interrupts = <0 27 0x04>;
+- clocks = <&clks 160>, <&clks 161>;
++ interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
++ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+@@ -1602,8 +1137,9 @@
+ uart3: serial@021ec000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021ec000 0x4000>;
+- interrupts = <0 28 0x04>;
+- clocks = <&clks 160>, <&clks 161>;
++ interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
++ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
+ dma-names = "rx", "tx";
+@@ -1613,8 +1149,9 @@
+ uart4: serial@021f0000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f0000 0x4000>;
+- interrupts = <0 29 0x04>;
+- clocks = <&clks 160>, <&clks 161>;
++ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
++ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
+ dma-names = "rx", "tx";
+@@ -1624,8 +1161,9 @@
+ uart5: serial@021f4000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021f4000 0x4000>;
+- interrupts = <0 30 0x04>;
+- clocks = <&clks 160>, <&clks 161>;
++ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_UART_IPG>,
++ <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
+ dma-names = "rx", "tx";
+@@ -1634,13 +1172,20 @@
+ };
+
+ ipu1: ipu@02400000 {
+- #crtc-cells = <1>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02400000 0x400000>;
+- interrupts = <0 6 0x4 0 5 0x4>;
+- clocks = <&clks 130>, <&clks 131>, <&clks 132>;
+- clock-names = "bus", "di0", "di1";
++ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
++ <0 5 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPU1>,
++ <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>,
++ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
++ <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
++ clock-names = "bus",
++ "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
+ resets = <&src 2>;
++ bypass_reset = <0>;
+ };
+ };
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -0,0 +1,700 @@
++/*
++ * Device Tree file for SolidRun HummingBoard2
++ * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++#include "imx6qdl-microsom.dtsi"
++#include "imx6qdl-microsom-ar8035.dtsi"
++
++/ {
++ aliases {
++ mmc0 = &usdhc2;
++ mmc1 = &usdhc1;
++ mxcfb0 = &mxcfb1;
++ mxcfb2 = &mxcfb2;
++ };
++
++ chosen {
++ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw";
++ stdout-path = &uart1;
++ };
++
++ ir_recv: ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio7 9 1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>;
++ linux,rc-map-name = "rc-rc6-mce";
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_1p8v: 1p8v {
++ compatible = "regulator-fixed";
++ regulator-name = "1P8V";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ };
++
++ reg_usbh1_vbus: usb-h1-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio1 0 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>;
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usbotg_vbus: usb-otg-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 22 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usbh2_vbus: usb-h2-vbus {
++ compatible = "regulator-gpio";
++ enable-active-high;
++ enable-gpio = <&gpio2 13 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>;
++ regulator-name = "usb_h2_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-boot-on;
++ };
++
++ reg_usbh3_vbus: usb-h3-vbus {
++ compatible = "regulator-gpio";
++ enable-active-high;
++ enable-gpio = <&gpio7 10 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>;
++ regulator-name = "usb_h3_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-boot-on;
++ };
++
++ reg_usdhc2_vbus: usdhc-2-vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "USDHC2-VBUS";
++ gpio = <&gpio4 30 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_usdhc2_pwr>;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++ };
++
++ sound-sgtl5000 {
++ audio-codec = <&sgtl5000>;
++ audio-routing =
++ "MIC_IN", "Mic Jack",
++ "Mic Jack", "Mic Bias",
++ "Headphone Jack", "HP_OUT";
++ compatible = "fsl,imx-audio-sgtl5000";
++ model = "On-board Codec";
++ mux-ext-port = <5>;
++ mux-int-port = <1>;
++ cpu-dai = <&ssi1>;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ mipi_camera = <1>;
++ default_input = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&audmux {
++ status = "okay";
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds1";
++ status = "okay";
++};
++
++&ecspi2 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio2 26 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>;
++ status = "okay";
++
++ spidev0: spi@0 {
++ compatible = "spidev";
++ reg = <0>;
++ spi-max-frequency = <20000000>;
++ };
++};
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0xf>;
++ fsl,cpu_pupscr_sw = <0xf>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_hdmi>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_i2c1>;
++ status = "okay";
++
++ ov5640_mipi: ov5640_mipi@3c {
++ compatible = "ovti,ov5640_mipi";
++ reg = <0x3c>;
++ clocks = <&clks IMX6QDL_CLK_CKO2>;
++ clock-names = "csi_mclk";
++/*
++ DOVDD-supply = <&reg_3p3v>;
++ AVDD-supply = <&reg_3p3v>;
++ DVDD-supply = <&reg_3p3v>;
++*/
++ pwn-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
++ rst-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_mipi>;
++ extended-buffer;
++ };
++
++ rtc: pcf8523@68 {
++ compatible = "nxp,pcf8523";
++ reg = <0x68>;
++ nxp,12p5_pf;
++ };
++
++ sgtl5000: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&clks IMX6QDL_CLK_CKO>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>;
++ VDDA-supply = <&reg_3p3v>;
++ VDDIO-supply = <&reg_3p3v>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_i2c2>;
++ status = "okay";
++
++ ddc: imx6_hdmi_i2c@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_i2c3>;
++ status = "okay";
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++ hummingboard2 {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ /*
++ * 36 pin headers GPIO description. The pins
++ * numbering as following -
++ *
++ * 3.2v 5v 74 75
++ * 73 72 71 70
++ * 69 68 67 66
++ *
++ * 77 78 79 76
++ * 65 64 61 60
++ * 53 52 51 50
++ * 49 48 166 132
++ * 95 94 90 91
++ * GND 54 24 204
++ *
++ * The GPIO numbers can be extracted using
++ * signal name from below.
++ * Example -
++ * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is
++ * GPIO(3,10) which is (3-1)*32+10 = gpio 74
++ *
++ * i.e. The mapping of GPIO(X,Y) to Linux gpio
++ * number is : gpio number = (X-1) * 32 + Y
++ */
++ /* DI1_PIN15 */
++ MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1
++ /* DI1_PIN02 */
++ MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1
++ /* DISP1_DATA00 */
++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1
++ /* DISP1_DATA01 */
++ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1
++ /* DISP1_DATA02 */
++ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1
++ /* DISP1_DATA03 */
++ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1
++ /* DISP1_DATA04 */
++ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1
++ /* DISP1_DATA05 */
++ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1
++ /* DISP1_DATA06 */
++ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1
++ /* DISP1_DATA07 */
++ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1
++ /* DI1_D0_CS */
++ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1
++ /* DI1_D1_CS */
++ MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1
++ /* DI1_PIN01 */
++ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1
++ /* DI1_PIN03 */
++ MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1
++ /* DISP1_DATA08 */
++ MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1
++ /* DISP1_DATA09 */
++ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1
++ /* DISP1_DATA10 */
++ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1
++ /* DISP1_DATA11 */
++ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1
++ /* DISP1_DATA12 */
++ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1
++ /* DISP1_DATA13 */
++ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1
++ /* DISP1_DATA14 */
++ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1
++ /* DISP1_DATA15 */
++ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1
++ /* DISP1_DATA16 */
++ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1
++ /* DISP1_DATA17 */
++ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1
++ /* DISP1_DATA18 */
++ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1
++ /* DISP1_DATA19 */
++ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1
++ /* DISP1_DATA20 */
++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1
++ /* DISP1_DATA21 */
++ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1
++ /* DISP1_DATA22 */
++ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1
++ /* DISP1_DATA23 */
++ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1
++ /* DI1_DISP_CLK */
++ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1
++ /* SPDIF_IN */
++ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1
++ /* SPDIF_OUT */
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1
++
++ /* MikroBUS GPIO pin number 10 */
++ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1
++ >;
++ };
++
++ pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000
++ >;
++ };
++
++ pinctrl_hummingboard2_hdmi: hummingboard2-hdmi {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard2_mipi: hummingboard2_mipi {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1
++ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1
++ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
++ >;
++ };
++
++ pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1
++ >;
++ };
++
++ pinctrl_hummingboard2_pwm1: pwm1grp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
++ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
++ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
++ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
++ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
++ >;
++ };
++
++ pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus {
++ fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus {
++ fsl,pins = <MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus {
++ fsl,pins = <MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id {
++ /*
++ * Similar to pinctrl_usbotg_2, but we want it
++ * pulled down for a fixed host connection.
++ */
++ fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
++ };
++
++ pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus {
++ fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard2_usdhc2_pwr: hummingboard2-usdhc2-pwr {
++ fsl,pins = <MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071
++ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071
++ >;
++ };
++
++ pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
++ >;
++ };
++
++ pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9
++ >;
++ };
++
++ pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9
++ >;
++ };
++
++ pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059
++ >;
++ };
++ pinctrl_hummingboard2_uart3: hummingboard2-uart3 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000
++ >;
++ };
++ pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
++ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
++ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
++ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */
++ >;
++ };
++ };
++};
++
++&ldb {
++ status = "disabled";
++
++ lvds-channel@0 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ crtc = "ipu2-di0";
++ primary;
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&mipi_csi {
++ ipu_id = <0>;
++ csi_id = <1>;
++ v_channel = <0>;
++ lanes = <2>;
++ mipi_dphy_clk = <0x14>;
++ status = "okay";
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &pinctrl_hummingboard2_pcie_reset
++ >;
++ reset-gpio = <&gpio2 11 0>;
++ status = "okay";
++ no-msi;
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_pwm1>;
++ status = "okay";
++};
++
++&pwm3 {
++ status = "disabled";
++};
++
++&pwm4 {
++ status = "disabled";
++};
++
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&usbh1 {
++ disable-over-current;
++ vbus-supply = <&reg_usbh1_vbus>;
++ status = "okay";
++};
++
++&usbotg {
++ disable-over-current;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>;
++ vbus-supply = <&reg_usbotg_vbus>;
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <
++ &pinctrl_hummingboard2_usdhc2_aux
++ &pinctrl_hummingboard2_usdhc2
++ >;
++ pinctrl-1 = <
++ &pinctrl_hummingboard2_usdhc2_aux
++ &pinctrl_hummingboard2_usdhc2_100mhz
++ >;
++ pinctrl-2 = <
++ &pinctrl_hummingboard2_usdhc2_aux
++ &pinctrl_hummingboard2_usdhc2_200mhz
++ >;
++
++ card-external-vcc-supply = <&reg_usdhc2_vbus>;
++ cd-gpios = <&gpio1 4 0>;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &pinctrl_hummingboard2_usdhc3
++ >;
++ vmmc-supply = <&reg_3p3v>;
++ bus-width = <8>;
++ non-removable;
++ status = "okay";
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard2_uart3>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -0,0 +1,569 @@
++/*
++ * Copyright (C) 2013,2014 Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++#include "imx6qdl-microsom.dtsi"
++#include "imx6qdl-microsom-ar8035.dtsi"
++
++/ {
++ aliases {
++ mmc0 = &usdhc2;
++ mmc1 = &usdhc1;
++ mxcfb0 = &mxcfb1;
++ mxcfb2 = &mxcfb2;
++ };
++
++ chosen {
++ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw";
++ stdout-path = &uart1;
++ };
++
++ ir_recv: ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio3 5 1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>;
++ linux,rc-map-name = "rc-rc6-mce";
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_usbh1_vbus: usb-h1-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio1 0 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>;
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usbotg_vbus: usb-otg-vbus {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 22 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ reg_usdhc2_vbus: usdhc-2-vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "USDHC2-VBUS";
++ gpio = <&gpio4 30 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usdhc2_pwr>;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++ };
++
++ sound-sgtl5000 {
++ audio-codec = <&sgtl5000>;
++ audio-routing =
++ "MIC_IN", "Mic Jack",
++ "Mic Jack", "Mic Bias",
++ "Headphone Jack", "HP_OUT";
++ compatible = "fsl,imx-audio-sgtl5000";
++ model = "On-board Codec";
++ mux-ext-port = <5>;
++ mux-int-port = <1>;
++ cpu-dai = <&ssi1>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "On-board SPDIF";
++ /* IMX6 doesn't implement this yet */
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ mipi_camera = <1>;
++ default_input = <1>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&audmux {
++ status = "okay";
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds1";
++ status = "okay";
++};
++
++&ecspi2 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio2 26 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_ecspi2>;
++ status = "okay";
++
++ spidev0: spi@0 {
++ compatible = "spidev";
++ reg = <0>;
++ spi-max-frequency = <20000000>;
++ };
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
++ status = "disabled";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
++ status = "okay";
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
++ status = "okay";
++
++ /* Raspberry Pi camera rev 1.3 */
++ ov5647_mipi: ov5647_mipi@36 {
++ compatible = "ovti,ov5647_mipi";
++ reg = <0x36>;
++ /* Pi camera has its own 25MHz clock. */
++ clocks = <&clks 0>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&reg_3p3v>;
++ AVDD-supply = <&reg_3p3v>;
++ DVDD-supply = <&reg_3p3v>;
++ pwn-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
++ led-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk = <25000000>;
++ mclk_source = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_mipi>;
++ extended-buffer;
++ };
++
++ /* Pro baseboard model */
++ rtc: pcf8523@68 {
++ compatible = "nxp,pcf8523";
++ reg = <0x68>;
++ nxp,12p5_pf;
++ };
++
++ /* Pro baseboard model */
++ sgtl5000: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&clks IMX6QDL_CLK_CKO>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
++ VDDA-supply = <&reg_3p3v>;
++ VDDIO-supply = <&reg_3p3v>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
++ status = "okay";
++
++ ddc: imx6_hdmi_i2c@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_i2c3>;
++ status = "okay";
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++ hummingboard {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ /*
++ * 26 pin header GPIO description. The pins
++ * numbering as following -
++ * GPIO number | GPIO (bank,num) | PIN number
++ * ------------+-----------------+------------
++ * gpio1 | (1,1) | IO7
++ * gpio73 | (3,9) | IO11
++ * gpio72 | (3,8) | IO12
++ * gpio71 | (3,7) | IO13
++ * gpio70 | (3,6) | IO15
++ * gpio194 | (7,2) | IO16
++ * gpio195 | (7,3) | IO18
++ * gpio67 | (3,3) | IO22
++ *
++ * Notice the gpioX and GPIO (Y,Z) mapping forumla :
++ * X = (Y-1) * 32 + Z
++ */
++ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x400130b1
++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1
++ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1
++ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1
++ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1
++ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x400130b1
++ MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x400130b1
++ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1
++ >;
++ };
++
++ pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
++ MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000
++ >;
++ };
++
++ pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1
++ >;
++ };
++
++ pinctrl_hummingboard_hdmi: hummingboard-hdmi {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard_i2c3: hummingboard-i2c3 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_hummingboard_mipi: hummingboard_mipi {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x17059
++ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x13059
++ >;
++ };
++
++ pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1
++ >;
++ };
++
++ pinctrl_hummingboard_pwm1: pwm1grp {
++ fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
++ };
++
++ pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
++ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
++ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
++ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
++ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
++ >;
++ };
++
++ pinctrl_hummingboard_spdif: hummingboard-spdif {
++ fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
++ };
++
++ pinctrl_hummingboard_ecspi2: hummingboard_ecspi2 {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
++ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
++ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
++ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */
++ >;
++ };
++
++ pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus {
++ fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id {
++ /*
++ * Similar to pinctrl_usbotg_2, but we want it
++ * pulled down for a fixed host connection.
++ */
++ fsl,pins = <MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059>;
++ };
++
++ pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus {
++ fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usdhc2_pwr: hummingboard-usdhc2-pwr {
++ fsl,pins = <MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0>;
++ };
++
++ pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071
++ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071
++ >;
++ };
++
++ pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
++ >;
++ };
++
++ pinctrl_hummingboard_usdhc2_100mhz: hummingboard-usdhc2-100mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9
++ >;
++ };
++
++ pinctrl_hummingboard_usdhc2_200mhz: hummingboard-usdhc2-200mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9
++ >;
++ };
++ };
++};
++
++&ldb {
++ status = "disabled";
++
++ lvds-channel@0 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ crtc = "ipu2-di0";
++ primary;
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&mipi_csi {
++ ipu_id = <0>;
++ csi_id = <1>;
++ v_channel = <0>;
++ lanes = <2>;
++ mipi_dphy_clk = /bits/ 8 <0x28>;
++ status = "okay";
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>;
++ reset-gpio = <&gpio3 4 0>;
++ status = "okay";
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_spdif>;
++ status = "okay";
++};
++
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&usbh1 {
++ disable-over-current;
++ vbus-supply = <&reg_usbh1_vbus>;
++ status = "okay";
++};
++
++&usbotg {
++ disable-over-current;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
++ vbus-supply = <&reg_usbotg_vbus>;
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <
++ &pinctrl_hummingboard_usdhc2_aux
++ &pinctrl_hummingboard_usdhc2
++ >;
++ pinctrl-1 = <
++ &pinctrl_hummingboard_usdhc2_aux
++ &pinctrl_hummingboard_usdhc2_100mhz
++ >;
++ pinctrl-2 = <
++ &pinctrl_hummingboard_usdhc2_aux
++ &pinctrl_hummingboard_usdhc2_200mhz
++ >;
++
++ card-external-vcc-supply = <&reg_usdhc2_vbus>;
++ cd-gpios = <&gpio1 4 0>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -3,6 +3,44 @@
+ *
+ * This describes the hookup for an AR8035 to the iMX6 on the SolidRun
+ * MicroSOM.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+ &fec {
+ pinctrl-names = "default";
+@@ -11,13 +49,15 @@
+ phy-reset-duration = <2>;
+ phy-reset-gpios = <&gpio4 15 0>;
+ status = "okay";
++ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
++ assigned-clock-rates = <25000000>;
+ };
+
+ &iomuxc {
+ enet {
+ pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
+ fsl,pins = <
+- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ /* AR8035 reset */
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0
+@@ -26,25 +66,25 @@
+ /* GPIO16 -> AR8035 25MHz */
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
+- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
+- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
+- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
+- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
+- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
+ /* AR8035 pin strapping: IO voltage: pull up */
+- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ /* AR8035 pin strapping: PHYADDR#0: pull down */
+- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
+ /* AR8035 pin strapping: PHYADDR#1: pull down */
+- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ /* AR8035 pin strapping: MODE#1: pull up */
+- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ /* AR8035 pin strapping: MODE#3: pull up */
+- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ /* AR8035 pin strapping: MODE#0: pull down */
+- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+
+ /*
+ * As the RMII pins are also connected to RGMII
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -1,9 +1,123 @@
+ /*
+ * Copyright (C) 2013,2014 Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
+ */
++#include <dt-bindings/gpio/gpio.h>
++/ {
++ clk_sdio: sdio-clock {
++ compatible = "gpio-gate-clock";
++ #clock-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_osc>;
++ enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_brcm_osc: brcm-osc-reg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio5 5 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_osc>;
++ regulator-name = "brcm_osc_reg";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++ };
++
++ reg_brcm: brcm-reg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 19 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
++ regulator-name = "brcm_reg";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <200000>;
++ };
++ };
++
++ usdhc1_pwrseq: usdhc1_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>,
++ <&gpio6 0 GPIO_ACTIVE_LOW>;
++ clocks = <&clk_sdio>;
++ clock-names = "ext_clock";
++ };
++};
+
+ &iomuxc {
+ microsom {
++ pinctrl_microsom_brcm_bt: microsom-brcm-bt {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070
++ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070
++ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_osc: microsom-brcm-osc {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_reg: microsom-brcm-reg {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070
++ >;
++ };
++
++ pinctrl_microsom_brcm_wifi: microsom-brcm-wifi {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0
++ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070
++ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070
++ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070
++ >;
++ };
++
+ pinctrl_microsom_uart1: microsom-uart1 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+@@ -11,12 +125,24 @@
+ >;
+ };
+
+- pinctrl_microsom_usbotg: microsom-usbotg {
+- /*
+- * Similar to pinctrl_usbotg_2, but we want it
+- * pulled down for a fixed host connection.
+- */
+- fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
++ pinctrl_microsom_uart4: microsom-uart4 {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_microsom_usdhc1: microsom-usdhc1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ >;
+ };
+ };
+ };
+@@ -27,7 +153,24 @@
+ status = "okay";
+ };
+
+-&usbotg {
++/* UART4 - Connected to optional BRCM Wifi/BT/FM */
++&uart4 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_microsom_usbotg>;
++ pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++};
++
++/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */
++&usdhc1 {
++ card-external-vcc-supply = <&reg_brcm>;
++ card-reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, <&gpio6 0 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>;
++ bus-width = <4>;
++ keep-power-in-suspend;
++ non-removable;
++ no-1-8-v;
++ vmmc-supply = <&reg_brcm>;
++ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi 2016-06-19 22:11:55.021158011 +0200
+@@ -9,18 +9,290 @@
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
++#include <dt-bindings/input/input.h>
+
+ / {
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb1 = &mxcfb2;
++ mxcfb2 = &mxcfb3;
++ mxcfb3 = &mxcfb4;
++ };
++
+ memory {
+ reg = <0x10000000 0x80000000>;
+ };
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <7>;
++ };
++
++ clocks {
++ codec_osc: anaclk2 {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <24576000>;
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ home {
++ label = "Home";
++ gpios = <&gpio1 11 1>;
++ gpio-key,wakeup;
++ linux,code = <KEY_HOME>;
++ };
++
++ back {
++ label = "Back";
++ gpios = <&gpio1 12 1>;
++ gpio-key,wakeup;
++ linux,code = <KEY_BACK>;
++ };
++
++ program {
++ label = "Program";
++ gpios = <&gpio2 12 1>;
++ gpio-key,wakeup;
++ linux,code = <KEY_PROGRAM>;
++ };
++
++ volume-up {
++ label = "Volume Up";
++ gpios = <&gpio2 15 1>;
++ gpio-key,wakeup;
++ linux,code = <KEY_VOLUMEUP>;
++ };
++
++ volume-down {
++ label = "Volume Down";
++ gpios = <&gpio5 14 1>;
++ gpio-key,wakeup;
++ linux,code = <KEY_VOLUMEDOWN>;
++ };
++ };
++
++ hannstar_cabc {
++ compatible = "hannstar,cabc";
++
++ lvds_share {
++ gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif",
++ "fsl,imx-sabreauto-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-in;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ max7310_reset: max7310-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <1>;
++ #reset-cells = <0>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <24>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb3: fb@2 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "lcd";
++ interface_pix_fmt = "RGB565";
++ mode_str ="CLAA-WVGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ sound-cs42888 {
++ compatible = "fsl,imx6-sabreauto-cs42888",
++ "fsl,imx-audio-cs42888";
++ model = "imx-cs42888";
++ esai-controller = <&esai>;
++ asrc-controller = <&asrc>;
++ audio-codec = <&codec>;
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_audio: regulator@0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ regulator-name = "cs42888_supply";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_si4763_vio1: regulator@1 {
++ compatible = "regulator-fixed";
++ reg = <1>;
++ regulator-name = "vio1";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_si4763_vio2: regulator@2 {
++ compatible = "regulator-fixed";
++ reg = <2>;
++ regulator-name = "vio2";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_si4763_vd: regulator@3 {
++ compatible = "regulator-fixed";
++ reg = <3>;
++ regulator-name = "vd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_si4763_va: regulator@4 {
++ compatible = "regulator-fixed";
++ reg = <4>;
++ regulator-name = "va";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++
++ reg_usb_h1_vbus: usb_h1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_usb_otg_vbus: usb_otg_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_sd3_vmmc: sd3_vmmc{
++ compatible = "regulator-fixed";
++ regulator-name = "P3V3_SDa_SWITCHED";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ /* remove below line to enable this regulator */
++ status="disabled";
++ };
++ };
++
++ sound-fm {
++ compatible = "fsl,imx-audio-si476x",
++ "fsl,imx-tuner-si476x";
++ model = "imx-radio-si4763";
++ ssi-controller = <&ssi2>;
++ fm-controller = <&si476x_codec>;
++ mux-int-port = <2>;
++ mux-ext-port = <5>;
++ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux>;
++ status = "okay";
++};
++
++&clks {
++ assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
++ <&clks IMX6QDL_PLL4_BYPASS>,
++ <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
++ assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
++ <&clks IMX6QDL_PLL4_BYPASS_SRC>;
++ assigned-clock-rates = <0>, <0>, <24576000>;
+ };
+
+ &ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 0>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
++ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+ status = "disabled"; /* pin conflict with WEIM NOR */
+
+ flash: m25p80@0 {
+@@ -32,16 +304,252 @@
+ };
+ };
+
++&esai {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_esai>;
++ assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
++ <&clks IMX6QDL_CLK_ESAI_EXTAL>;
++ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
++ assigned-clock-rates = <0>, <24576000>;
++ status = "okay";
++};
++
+ &fec {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_2>;
++ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
++ fsl,magic-packet;
+ status = "okay";
+ };
+
+ &gpmi {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ pinctrl-0 = <&pinctrl_gpmi_nand>;
++ status = "disabled"; /* pin conflict with uart3 */
++ nand-on-flash-bbt;
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_egalax_int>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <28 2>;
++ wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
++ };
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++ hdmi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++
++ codec: cs42888@48 {
++ compatible = "cirrus,cs42888";
++ reg = <0x48>;
++ clocks = <&codec_osc>;
++ clock-names = "mclk";
++ VA-supply = <&reg_audio>;
++ VD-supply = <&reg_audio>;
++ VLS-supply = <&reg_audio>;
++ VLC-supply = <&reg_audio>;
++ };
++
++ si4763: si4763@63 {
++ compatible = "si4761";
++ reg = <0x63>;
++ va-supply = <&reg_si4763_va>;
++ vd-supply = <&reg_si4763_vd>;
++ vio1-supply = <&reg_si4763_vio1>;
++ vio2-supply = <&reg_si4763_vio2>;
++ revision-a10; /* set to default A10 compatible command set */
++
++ si476x_codec: si476x-codec {
++ compatible = "si476x-codec";
++ };
++ };
++};
++
++&i2c3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++
++ adv7180: adv7180@21 {
++ compatible = "adv,adv7180";
++ reg = <0x21>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_1>;
++ clocks = <&clks IMX6QDL_CLK_CKO>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&reg_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */
++ AVDD-supply = <&reg_3p3v>; /* 1.8v */
++ DVDD-supply = <&reg_3p3v>; /* 1.8v */
++ PVDD-supply = <&reg_3p3v>; /* 1.8v */
++ pwn-gpios = <&max7310_b 2 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ cvbs = <1>;
++ };
++
++ max7310_a: gpio@30 {
++ compatible = "maxim,max7310";
++ reg = <0x30>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7310_reset>;
++ };
++
++ max7310_b: gpio@32 {
++ compatible = "maxim,max7310";
++ reg = <0x32>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ max7310_c: gpio@34 {
++ compatible = "maxim,max7310";
++ reg = <0x34>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ mma8451@1c {
++ compatible = "fsl,mma8451";
++ reg = <0x1c>;
++ position = <7>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <31 8>;
++ interrupt-route = <1>;
++ };
++
++ mag3110@0e {
++ compatible = "fsl,mag3110";
++ reg = <0x0e>;
++ position = <2>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <29 1>;
++ };
++
++ isl29023@44 {
++ compatible = "fsl,isl29023";
++ reg = <0x44>;
++ rext = <499>;
++ interrupt-parent = <&gpio5>;
++ interrupts = <17 2>;
++ };
++};
++
++&mlb {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mlb>;
+ status = "okay";
+ };
+
+@@ -49,44 +557,435 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+- hog {
++ imx6qdl-sabreauto {
++ pinctrl_audmux: audmux {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
++ MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
++ >;
++ };
++
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+- MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
++ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059
+ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
+ MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
++ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
++ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
++ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000
++ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
++ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
++ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059
++ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059
++ >;
++ };
++
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ >;
+ };
+- };
+
+- ecspi1 {
+- pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
++ pinctrl_ecspi1_cs: ecspi1cs {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
+ >;
+ };
++
++ pinctrl_egalax_int: egalax_intgrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ >;
++ };
++
++ pinctrl_esai: esaigrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
++ MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
++ MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
++ MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
++ MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
++ MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
++ MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
++ MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
++ MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
++ MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
++ >;
++ };
++
++ pinctrl_flexcan1: flexcan1grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
++ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
++ >;
++ };
++
++ pinctrl_flexcan2: flexcan2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
++ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
++ >;
++ };
++
++ pinctrl_gpio_keys: gpio_keysgrp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0
++ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
++ MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
++ MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0
++ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpmi_nand: gpminandgrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
++ MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
++ MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
++ MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
++ MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
++ MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
++ MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
++ MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
++ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
++ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
++ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
++ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
++ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
++ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
++ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
++ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
++ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
++ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
++ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_mlb: mlb {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000
++ MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000
++ MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000
++ >;
++ };
++
++ pinctrl_spdif: spdifgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
++ >;
++ };
++
++ pinctrl_uart3_1: uart3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart3dte_1: uart3dtegrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart4: uart4grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc1: usdhc1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_weim_cs0: weimcs0grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
++ >;
++ };
++
++ pinctrl_weim_nor: weimnorgrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
++ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
++ MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
++ MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
++ MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
++ MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
++ MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
++ MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
++ MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
++ MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
++ MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
++ MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
++ MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
++ MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
++ MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
++ MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
++ MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
++ MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
++ MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
++ MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
++ MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
++ MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
++ MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
++ MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
++ MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
++ MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
++ MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
++ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
++ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
++ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
++ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
++ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
++ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
++ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
++ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
++ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
++ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
++ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
++ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
++ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
++ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
++ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
++ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
++ >;
++ };
++
++ pinctrl_hdmi_cec: hdmicecgrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_pwm3_1: pwm3grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
+ };
+ };
+
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3_1>;
++ status = "okay";
++};
++
++&pcie {
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif>;
++ assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>,
++ <&clks IMX6QDL_CLK_SPDIF_PODF>;
++ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>;
++ assigned-clock-rates = <0>, <227368421>;
++ status = "okay";
++};
++
++&ssi2 {
++ assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>;
++ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
++ assigned-clock-rates = <0>;
++ fsl,mode = "i2s-master";
++ status = "okay";
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart3_1>;
++ pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */
++ <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */
++ fsl,uart-has-rtscts;
++ status = "okay";
++ /* for DTE mode, add below change */
++ /* fsl,dte-mode; */
++ /* pinctrl-0 = <&pinctrl_uart3dte_1>; */
++};
++
+ &uart4 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart4_1>;
++ pinctrl-0 = <&pinctrl_uart4>;
++ status = "okay";
++};
++
++&usdhc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc1>;
++ cd-gpios = <&gpio1 1 0>;
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ status = "okay";
++};
++
++&usbh1 {
++ vbus-supply = <&reg_usb_h1_vbus>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_usb_otg_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
+ status = "okay";
+ };
+
+ &usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+- pinctrl-0 = <&pinctrl_usdhc3_1>;
+- pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
+- pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio6 15 0>;
+ wp-gpios = <&gpio1 13 0>;
++ /*
++ * Due to board issue, we can not use external regulator for card slot
++ * by default since the card power is shared with card detect pullup.
++ * Disabling the vmmc regulator will cause unexpected card detect
++ * interrupts.
++ * HW rework is needed to fix this isssue. Remove R695 first, then you
++ * can open below line to enable the using of external regulator.
++ * Then you will be able to power off the card during suspend. This is
++ * especially needed for a SD3.0 card re-enumeration working on UHS mode
++ * Note: reg_sd3_vmmc is also need to be enabled
++ */
++ /* vmmc-supply = <&reg_sd3_vmmc>; */
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
+ status = "okay";
+ };
+
+ &weim {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
++ pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x08000000 0x08000000>;
+@@ -102,3 +1001,101 @@
+ 0x0000c000 0x1404a38e 0x00000000>;
+ };
+ };
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds0";
++ status = "okay";
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1>;
++ pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */
++ trx-en-gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
++ status = "disabled"; /* pin conflict with fec */
++};
++
++&flexcan2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan2>;
++ trx-en-gpio = <&max7310_c 6 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&max7310_c 5 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_cec>;
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <1>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&ldb {
++ status = "okay";
++
++ lvds-channel@0 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ primary;
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++
++ lvds-channel@1 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing1>;
++ timing1: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -10,16 +10,51 @@
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
++#include <dt-bindings/input/input.h>
++
+ / {
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb1 = &mxcfb2;
++ mxcfb2 = &mxcfb3;
++ mxcfb3 = &mxcfb4;
++ };
++
++ battery: max8903@0 {
++ compatible = "fsl,max8903-charger";
++ pinctrl-names = "default";
++ dok_input = <&gpio2 24 1>;
++ uok_input = <&gpio1 27 1>;
++ chg_input = <&gpio3 23 1>;
++ flt_input = <&gpio5 2 1>;
++ fsl,dcm_always_high;
++ fsl,dc_valid;
++ fsl,usb_valid;
++ status = "okay";
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ charger-led {
++ gpios = <&gpio1 2 0>;
++ linux,default-trigger = "max8903-charger-charging";
++ retain-state-suspended;
++ };
++ };
++
+ memory {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
+
+- reg_usb_otg_vbus: usb_otg_vbus {
++ reg_usb_otg_vbus: regulator@0 {
+ compatible = "regulator-fixed";
++ reg = <0>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+@@ -27,8 +62,9 @@
+ enable-active-high;
+ };
+
+- reg_usb_h1_vbus: usb_h1_vbus {
++ reg_usb_h1_vbus: regulator@1 {
+ compatible = "regulator-fixed";
++ reg = <1>;
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+@@ -36,29 +72,57 @@
+ enable-active-high;
+ };
+
+- reg_audio: wm8962_supply {
++ reg_audio: regulator@2 {
+ compatible = "regulator-fixed";
++ reg = <2>;
+ regulator-name = "wm8962-supply";
+ gpio = <&gpio4 10 0>;
+ enable-active-high;
+ };
++
++ reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
++ compatible = "regulator-fixed";
++ regulator-name = "mipi_dsi_pwr_on";
++ gpio = <&gpio6 14 0>;
++ enable-active-high;
++ };
++
++ reg_sensor: regulator@3 {
++ compatible = "regulator-fixed";
++ reg = <3>;
++ regulator-name = "sensor-supply";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio2 31 0>;
++ startup-delay-us = <500>;
++ enable-active-high;
++ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ power {
++ label = "Power Button";
++ gpios = <&gpio3 29 1>;
++ gpio-key,wakeup;
++ linux,code = <KEY_POWER>;
++ };
+
+ volume-up {
+ label = "Volume Up";
+- gpios = <&gpio1 4 0>;
++ gpios = <&gpio1 4 1>;
+ gpio-key,wakeup;
+- linux,code = <115>; /* KEY_VOLUMEUP */
++ linux,code = <KEY_VOLUMEUP>;
+ };
+
+ volume-down {
+ label = "Volume Down";
+- gpios = <&gpio1 5 0>;
++ gpios = <&gpio1 5 1>;
+ gpio-key,wakeup;
+- linux,code = <114>; /* KEY_VOLUMEDOWN */
++ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+@@ -66,7 +130,7 @@
+ compatible = "fsl,imx6q-sabresd-wm8962",
+ "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+- ssi-controller = <&ssi2>;
++ cpu-dai = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+@@ -79,6 +143,67 @@
+ "DMICDAT", "DMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
++ hp-det-gpios = <&gpio7 8 1>;
++ mic-det-gpios = <&gpio1 9 1>;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <24>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb3: fb@2 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "lcd";
++ interface_pix_fmt = "RGB565";
++ mode_str ="CLAA-WVGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ lcd@0 {
++ compatible = "fsl,lcd";
++ ipu_id = <0>;
++ disp_id = <0>;
++ default_ifmt = "RGB565";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1>;
++ status = "okay";
+ };
+
+ backlight {
+@@ -88,19 +213,52 @@
+ default-brightness-level = <7>;
+ status = "okay";
+ };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_1 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++
++ mipi_dsi_reset: mipi-dsi-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <50>;
++ #reset-cells = <0>;
++ };
+ };
+
+ &audmux {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_audmux_2>;
++ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+ };
+
++&cpu0 {
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1c_reg>;
++};
++
+ &ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 9 0>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_ecspi1_2>;
++ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80@0 {
+@@ -114,16 +272,17 @@
+
+ &fec {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_1>;
++ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio1 25 0>;
++ fsl,magic-packet;
+ status = "okay";
+ };
+
+ &i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_i2c1_2>;
++ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ codec: wm8962@1a {
+@@ -138,6 +297,7 @@
+ PLLVDD-supply = <&reg_audio>;
+ SPKVDD1-supply = <&reg_audio>;
+ SPKVDD2-supply = <&reg_audio>;
++ amic-mono;
+ gpio-cfg = <
+ 0x0000 /* 0:Default */
+ 0x0000 /* 1:Default */
+@@ -147,12 +307,185 @@
+ 0x0000 /* 5:Default */
+ >;
+ };
++
++ mma8451@1c {
++ compatible = "fsl,mma8451";
++ reg = <0x1c>;
++ position = <0>;
++ vdd-supply = <&reg_sensor>;
++ vddio-supply = <&reg_sensor>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <18 8>;
++ interrupt-route = <1>;
++ };
++
++ ov564x: ov564x@3c {
++ compatible = "ovti,ov564x";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ipu1_2>;
++ clocks = <&clks IMX6QDL_CLK_CKO>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
++ AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3,
++ on rev B board is VGEN5 */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
++ rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++
++ hdmi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++
++ max11801@48 {
++ compatible = "maxim,max11801";
++ reg = <0x48>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <26 2>;
++ work-mode = <1>;/*DCM mode*/
++ };
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++ ov5640_mipi: ov5640_mipi@3c { /* i2c2 driver */
++ compatible = "ovti,ov5640_mipi";
++ reg = <0x3c>;
++ clocks = <&clks 201>;
++ clock-names = "csi_mclk";
++ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
++ AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
++ rev B board is VGEN5 */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
++ rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
++ csi_id = <1>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <8 2>;
++ wakeup-gpios = <&gpio6 8 0>;
++ };
++
+ };
+
+ &i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_i2c3_2>;
++ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ egalax_ts@04 {
+@@ -162,35 +495,327 @@
+ interrupts = <7 2>;
+ wakeup-gpios = <&gpio6 7 0>;
+ };
++
++ mag3110@0e {
++ compatible = "fsl,mag3110";
++ reg = <0x0e>;
++ position = <2>;
++ vdd-supply = <&reg_sensor>;
++ vddio-supply = <&reg_sensor>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <16 1>;
++ };
++
++ isl29023@44 {
++ compatible = "fsl,isl29023";
++ reg = <0x44>;
++ rext = <499>;
++ vdd-supply = <&reg_sensor>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <9 2>;
++ };
+ };
+
+ &iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+- hog {
++ imx6qdl-sabresd {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
+- MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
++ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
++ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
++ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
++ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
++ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
++ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
++ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
++ MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
++ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
++ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
++ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
++ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
++ MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
++ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
++ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
+ >;
+ };
++
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
++ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
++ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
++ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
++ >;
++ };
++
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ >;
++ };
++
++ pinctrl_enet_irq: enetirqgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
++ >;
++ };
++
++ pinctrl_gpio_keys: gpio_keysgrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
++ >;
++ };
++
++ pinctrl_hdmi_cec: hdmicecgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_hdmi_hdcp: hdmihdcpgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_ipu1: ipu1grp {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
++ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
++ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
++ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
++ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
++ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
++ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
++ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
++ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
++ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
++ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
++ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
++ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
++ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
++ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
++ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
++ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
++ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
++ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
++ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
++ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
++ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
++ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
++ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
++ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
++ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
++ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
++ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
++ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
++ >;
++ };
++
++ pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
++ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
++ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
++ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
++ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
++ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
++ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
++ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
++ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
++ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
++ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
++ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
++ >;
++ };
++
++ pinctrl_pwm1: pwm1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5_1: uart5grp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1
++ MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5dte_1: uart5dtegrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1
++ MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
++ MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
++ MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
++ MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc4: usdhc4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
++ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
++ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
++ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
++ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
++ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
++ >;
++ };
++
+ };
+ };
+
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds1";
++ status = "okay";
++};
++
++&gpc {
++ /* use ldo-bypass, u-boot will check it and configure */
++ fsl,ldo-bypass = <1>;
++ fsl,wdog-reset = <2>;
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_cec>;
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
+ &ldb {
+ status = "okay";
+
+- lvds-channel@1 {
++ lvds-channel@0 {
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ status = "okay";
+@@ -210,11 +835,56 @@
+ };
+ };
+ };
++
++ lvds-channel@1 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ primary;
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing1>;
++ timing1: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&mipi_csi {
++ status = "okay";
++ ipu_id = <0>;
++ csi_id = <1>;
++ v_channel = <0>;
++ lanes = <2>;
++};
++
++&mipi_dsi {
++ dev_id = <0>;
++ disp_id = <1>;
++ lcd_panel = "TRULY-WVGA";
++ disp-power-on-supply = <&reg_mipi_dsi_pwr_on>;
++ resets = <&mipi_dsi_reset>;
++ status = "okay";
++};
++
++&pcie {
++ power-on-gpio = <&gpio3 19 0>;
++ reset-gpio = <&gpio7 12 0>;
++ status = "okay";
+ };
+
+ &pwm1 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_pwm0_1>;
++ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+ };
+
+@@ -225,7 +895,7 @@
+
+ &uart1 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart1_1>;
++ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+ };
+
+@@ -237,25 +907,49 @@
+ &usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usbotg_2>;
++ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+ };
+
+ &usdhc2 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc2_1>;
++ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <8>;
+ cd-gpios = <&gpio2 2 0>;
+ wp-gpios = <&gpio2 3 0>;
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
+ status = "okay";
+ };
+
+ &usdhc3 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_1>;
++ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ cd-gpios = <&gpio2 0 0>;
+ wp-gpios = <&gpio2 1 0>;
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ status = "okay";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4>;
++ bus-width = <8>;
++ non-removable;
++ no-1-8-v;
++ keep-power-in-suspend;
++ status = "okay";
++};
++
++&wdog1 {
++ status = "disabled";
++};
++
++&wdog2 {
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,116 @@
++/*
++ * Copyright 2014 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/ {
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <7>;
++ };
++
++ i2cmux {
++ compatible = "i2c-mux-gpio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ mux-gpios = <&gpio1 2 0>;
++ i2c-parent = <&i2c1>;
++
++ i2c@0 {
++ reg = <0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pca9555@26 {
++ compatible = "nxp,pca9555";
++ gpio-controller;
++ #gpio-cells = <2>;
++ reg = <0x26>;
++ };
++
++ hx8526@4a {
++ compatible = "himax,himax_ts";
++ reg = <0x4a>;
++ gpio_intr = <&gpio1 4 0>;
++ };
++
++ eeprom@50 {
++ compatible = "at24,24c02";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++
++ };
++
++ i2c@1 {
++ reg = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ dvi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++ };
++
++ };
++};
++
++&i2c1 {
++ status = "okay";
++};
++
++&usdhc3 {
++ wp-gpios = <&gpio7 0 0>;
++ cd-gpios = <&gpio7 1 0>;
++ status = "okay";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3_1>;
++ status = "okay";
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ mode_str ="KD050C-WVGA";
++ status = "okay";
++};
++
++&mxcfb3 {
++ status = "okay";
++};
++
++&mxcfb4 {
++ status = "okay";
++};
++
++&ldb {
++ ipu_id = <1>;
++ disp_id = <0>;
++ ext_ref = <1>;
++ mode = "sep0";
++ sec_ipu_id = <1>;
++ sec_disp_id = <1>;
++ status = "okay";
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1_1>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,114 @@
++/*
++ * Copyright 2014 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/ {
++ iomux_uart2: pinmux@20E0924 {
++ compatible = "pinctrl-single";
++ reg = <0x20E0000 0x924>; /* Single register */
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-single,register-width = <32>;
++ pinctrl-single,function-mask = <0x4>;
++ };
++
++ eth@pcie {
++ compatible = "intel,i211";
++ local-mac-address = [FF FF FF FF FF FF];
++ status = "okay";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ power {
++ label = "Power Button";
++ gpios = <&gpio1 29 1>;
++ linux,code = <116>; /* KEY_POWER */
++ gpio-key,wakeup;
++ };
++ };
++
++ i2cmux {
++ compatible = "i2c-mux-gpio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ mux-gpios = <&gpio1 2 0>;
++ i2c-parent = <&i2c1>;
++
++ i2c@0 {
++ reg = <0>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ eeprom@50 {
++ compatible = "at24,24c02";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++
++ rtc@56 {
++ compatible = "emmicro,em3027";
++ reg = <0x56>;
++ };
++ };
++
++ i2c@1 {
++ reg = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ dvi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++ };
++ };
++};
++
++&iomuxc {
++ imx6q-sbc-fx6m {
++ /* pins for uart2 */
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
++ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
++ >;
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++};
++
++&usdhc3 {
++ non-removable;
++ status = "okay";
++};
++
++/* rear serial console */
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,110 @@
++/*
++ * Copyright 2014 CompuLab Ltd.
++ *
++ * Author: Valentin Raevsky <valentin@compulab.co.il>
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/ {
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* regulator for mmc */
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>, <&pinctrl_dvi0>;
++
++ imx6q-sb-fx6x {
++ /* pins for i2c1 */
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ /* pins for mmc */
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { /* 100Mhz */
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { /* 200Mhz */
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
++ >;
++ };
++
++ /* pins for dvi/ts */
++ pinctrl_dvi0: dvi0grp {
++ fsl,pins = <
++ /* DVI_DDC_SEL */
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
++ /* SB-FX6 Himax TS PENDOWN or SB-FX6m DVI HPD */
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
++ >;
++ };
++ };
++};
++
++/* i2c1 */
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "disabled";
++};
++
++/* mmc */
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++ no-1-8-v;
++ keep-power-in-suspend;
++ vmmc-supply = <&reg_3p3v>;
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-udoo.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-udoo.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-udoo.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,664 @@
++/*
++ * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2014 Jasbir
++ * Copyright 2015 Aidilab, Srl.
++ *
++ * Author: Fabio Estevam <fabio.estevam@freescale.com>
++ * Author: Ettore Chimenti <ettore.chimenti@udoo.org>
++ * Author: Francesco Montefoschi <francesco.monte@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++/ {
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb2 = &mxcfb2;
++// reg_can_xcvr = &reg_can_xcvr;
++ mmc0 = &usdhc3;
++ mmc1 = &usdhc2;
++ mmc2 = &usdhc1;
++ mmc3 = &usdhc4;
++ ssi0 = &ssi1;
++ serial0 = &uart2; // console on ttymxc0
++ serial1 = &uart1;
++ };
++
++ memory {
++ reg = <0x10000000 0x40000000>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str = "";
++ default_bpp = <32>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_usb_h1_vbus: regulator@0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ regulator-name = "usb_h1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ enable-active-high;
++ startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
++ gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
++ };
++
++ reg_lcd0_pwr: regulator@1 {
++ compatible = "regulator-fixed";
++ regulator-name = "LCD0 POWER";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ regulator-boot-on;
++ regulator-always-on;
++ status = "disabled";
++ };
++
++ reg_lcd0_backlight: regulator@2 {
++ compatible = "regulator-fixed";
++ regulator-name = "LCD0 BACKLIGHT";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ regulator-boot-on;
++ regulator-always-on;
++ status = "disabled";
++ };
++
++// reg_can_xcvr: regulator@3 {
++// compatible = "regulator-fixed";
++// reg = <3>;
++// regulator-name = "CAN XCVR";
++// regulator-min-microvolt = <3300000>;
++// regulator-max-microvolt = <3300000>;
++// regulator-always-on;
++// enable-active-low;
++// };
++
++ reg_usb_otg_vbus: regulator@4 {
++ compatible = "regulator-fixed";
++ reg = <4>;
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ enable-active-high;
++ };
++
++ reg_2p5v: regulator@5 {
++ compatible = "regulator-fixed";
++ reg = <5>;
++ regulator-name = "2P5V";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ regulator-always-on;
++ };
++ };
++
++ gpio-poweroff {
++ compatible = "gpio-poweroff";
++ gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
++ };
++
++ codec: vt1613 {
++ compatible = "via,vt1613";
++ };
++
++ sound {
++ compatible = "udoo,imx-vt1613-audio";
++ ssi-controller = <&ssi1>;
++ audio-codec = <&codec>;
++ mux-int-port = <1>;
++ mux-ext-port = <6>;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++
++// sound-spdif {
++// compatible = "fsl,imx-audio-spdif",
++// "fsl,imx-sabreauto-spdif";
++// model = "imx-spdif";
++// spdif-controller = <&spdif>;
++// spdif-in;
++// status = "disabled";
++// };
++
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_cap_1 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <1>;
++ mclk_source = <0>;
++ status = "okay";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++
++ udoo_ard: udoo_ard_manager {
++ compatible = "udoo,imx6q-udoo-ard";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_udoo_ard_alt>;
++ bossac-clk-gpio = <&gpio6 3 GPIO_ACTIVE_LOW>;
++ bossac-dat-gpio = <&gpio5 18 GPIO_ACTIVE_LOW>;
++ bossac-erase-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
++ bossac-reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
++ status = "okay";
++ };
++};
++
++&audmux {
++ status = "okay";
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-hdmi";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds1";
++ status = "okay";
++};
++
++&gpc { // General power controller
++ /* use ldo-bypass, u-boot will check it and configure */
++ fsl,ldo-bypass = <1>;
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&ldb { // LVDS display bridge
++ status = "disabled";
++ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>;
++ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>;
++
++ lvds-channel@0 {
++ status = "disabled";
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>; // 7" display
++ //fsl,data-width = <24>; // 15.6" display
++ crtc = "ipu2-di0";
++ primary;
++
++ display-timings {
++ native-mode = <&timing1>;
++
++ timing1: 800x480 { // 7" display
++ clock-frequency = <33660000>;
++ hactive = <800>;
++ vactive = <480>;
++ hback-porch = <56>;
++ hfront-porch = <50>;
++ vback-porch = <23>;
++ vfront-porch = <20>;
++ hsync-len = <150>;
++ vsync-len = <2>;
++ };
++
++ timing2: 1366x768 { // 15.6" display
++ clock-frequency = <76000000>;
++ hactive = <1366>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&i2c1 { // external pinout pin 20-21
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++};
++
++&i2c2 { // internal (hdmi)
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++
++ hdmi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++};
++
++&i2c3 { // CSI camera (CN11) and LVDS 7 inches touch panel (CN13)
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++
++ ov5640_mipi: ov5640_mipi@3c {
++ compatible = "ovti,ov5640_mipi";
++ reg = <0x3c>;
++ clocks = <&clks IMX6QDL_CLK_CKO>;
++ clock-names = "csi_mclk";
++ pwn-gpios = <&gpio6 4 GPIO_ACTIVE_LOW>;
++ rst-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ };
++
++ touchscreen: st1232@55 {
++ compatible = "sitronix,st1232";
++ reg = <0x55>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-0 = <&pinctrl_st1232>;
++ pinctrl-names = "default";
++ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&fec { //ethernet
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii";
++ /* doesn't work with solidrun's kernel 3.14.48+
++ phy-reset-gpios = <&gpio3 23 0>;
++ phy-reset-duration = <50>;*/
++ status = "okay";
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog &external_hog>;
++
++ imx6q-udoo {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ // Internal GPIOs
++ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 // 5v enable
++ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 // Vtt enable
++
++ MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x80000000 // Debug UART (J18)
++
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 // USB hub reset
++ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 // USB hub clock
++ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0b1 // USB OTG select
++
++ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 // SD card power
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 // SD card detect
++
++ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0xb0b1 // SAM3X OTG vbus_en
++ MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000 // SAM3X usb host
++ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x30b1 // Arduino pinout pin 12
++
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 // LVDS panel on (CN13)
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 // LVDS backlight on (CN13)
++
++ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1f071 // CSI camera enable (CN11)
++ MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1f071 // CSI camera reset (CN11)
++ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0 // CSI master clock (CN11)
++ >;
++ };
++
++ external_hog: hoggrp-2 {
++ fsl,pins = <
++ // External Pinout GPIOs
++ MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x80000000 // pin 00
++ MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x80000000 // pin 01
++ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x80000000 // pin 02
++ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 // pin 03
++ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 // pin 04
++ MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 // pin 05
++ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 // pin 06
++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 // pin 07
++ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 // pin 08
++ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x80000000 // pin 09
++ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x80000000 // pin 10
++ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 // pin 11
++ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x80000000 // pin 12
++ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000 // pin 13
++ MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x80000000 // pin 14
++ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x80000000 // pin 15
++ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x80000000 // pin 16
++ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x80000000 // pin 17
++ MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 // pin 18
++ MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x80000000 // pin 19
++ // pin 20, 21 in pinctrl_i2c1
++ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 // pin 22
++ MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x80000000 // pin 23
++ MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x80000000 // pin 24
++ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x80000000 // pin 25
++ MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x80000000 // pin 26
++ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x80000000 // pin 27
++ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x80000000 // pin 28
++ MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x80000000 // pin 29
++ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x80000000 // pin 30
++ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x80000000 // pin 31
++ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x80000000 // pin 32
++ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x80000000 // pin 33
++ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x80000000 // pin 34
++ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x80000000 // pin 35
++ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x80000000 // pin 36
++ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000 // pin 37
++ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000 // pin 38
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 // pin 39 KEY_VOL_UP
++ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 // pin 40 HOME
++ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 // pin 41 SEARCH
++ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 // pin 42 BACK
++ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 // pin 43 MENU
++ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 // pin 44 KEY_VOL_DOWN
++ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x80000000 // pin 45
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000 // pin 46
++ MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 // pin 47
++ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x80000000 // pin 48
++ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x80000000 // pin 49
++ MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x80000000 // pin 50
++ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 // pin 51
++ MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x80000000 // pin 52
++ MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x80000000 // pin 53
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* RGMII_nRST */
++ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* EN_ETH_PWR */
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_st1232: st1232grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000 // Touch panel reset
++ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 // Touch panel interrupt
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart4: uart4grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 // or 0x100b1
++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 // or 0x100b1
++ >;
++ };
++
++ pinctrl_udoo_ard_alt: udooard2grp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x80000000
++ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x80000000
++ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
++ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000
++ >;
++ };
++
++// pinctrl_flexcan1: can1grp {
++// fsl,pins = <
++// MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b1
++// MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b1
++// >;
++// };
++
++
++// pinctrl_pwm4: pwm4grp {
++// fls,pins = <
++// MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
++// >;
++// };
++//
++// pinctrl_pwm3: pwm3grp {
++// fls,pins = <
++// MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++// >;
++// };
++//
++// pinctrl_pwm1: pwm1grp {
++// fsl,pins = <
++// MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
++// >;
++// };
++//
++// pinctrl_pwm2: pwm2grp {
++// fsl,pins = <
++// MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
++// >;
++// };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
++
++
++ pinctrl_spdif_1: spdifgrp-1 {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
++ >;
++ };
++
++ ac97link_running: ac97link_runninggrp {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x80000000
++ MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x80000000
++ MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x80000000
++ MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x80000000
++ >;
++ };
++
++ ac97link_reset: ac97link_resetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000
++ MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x80000000
++ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000
++ >;
++ };
++
++ ac97link_warm_reset: ac97link_warm_resetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x80000000
++ >;
++ };
++
++ };
++};
++
++&ssi1 {
++ compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi";
++ fsl,mode = "ac97-slave";
++ pinctrl-names = "default", "ac97-running", "ac97-reset", "ac97-warm-reset";
++ pinctrl-0 = <&ac97link_running>;
++ pinctrl-1 = <&ac97link_running>;
++ pinctrl-2 = <&ac97link_reset>;
++ pinctrl-3 = <&ac97link_warm_reset>;
++ /* sync, sdata (output), reset */
++ ac97-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH
++ &gpio4 18 GPIO_ACTIVE_HIGH
++ &gpio2 30 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&uart2 { // iMX6 serial debug port - ttymxc1, available on micro USB CN6 (jumper J18 plugged)
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++&uart4 { // iMX6-Arduino internal serial port - ttymxc3
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart4>;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ non-removable;
++ keep-power-in-suspend;
++ no-1-8-v;
++ enable-sdio-wakeup;
++ status = "okay";
++};
++
++&usbotg {
++ pinctrl-names = "default";
++ vbus-supply = <&reg_usb_otg_vbus>;
++ status = "okay";
++};
++
++&usbh1 {
++ vbus-supply = <&reg_usb_h1_vbus>;
++ clocks = <&clks 201>;
++ clock-names = "phy";
++ status = "okay";
++};
++
++/*
++ * &pwm1 {
++ * pinctrl-names = "default";
++ * pinctrl-0 = <&pinctrl_pwm1>;
++ * #pwm-cells = <3>;
++ * status = "okay";
++ * };
++ *
++ * &pwm2 {
++ * pinctrl-names = "default";
++ * pinctrl-0 = <&pinctrl_pwm2>;
++ * #pwm-cells = <3>;
++ * status = "okay";
++ * };
++ *
++ * &pwm3 {
++ * pinctrl-names = "default";
++ * pinctrl-0 = <&pinctrl_pwm3>;
++ * #pwm-cells = <3>;
++ * status = "okay";
++ * };
++ *
++ * &pwm4 {
++ * pinctrl-names = "default";
++ * pinctrl-0 = <&pinctrl_pwm4>;
++ * #pwm-cells = <3>;
++ * status = "okay";
++ * };
++ */
++
++
++&mipi_csi {
++ status = "okay";
++ ipu_id = <0>;
++ csi_id = <0>;
++ v_channel = <0>;
++ lanes = <2>;
++};
++
++// &spdif {
++// pinctrl-names = "default";
++// pinctrl-0 = <&pinctrl_spdif_1>;
++// status = "disabled";
++// };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-wandboard.dtsi linux-3.14.72/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6qdl-wandboard.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6qdl-wandboard.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -12,17 +12,21 @@
+ / {
+ regulators {
+ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
+
+- reg_2p5v: 2p5v {
++ reg_2p5v: regulator@0 {
+ compatible = "regulator-fixed";
++ reg = <0>;
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+- reg_3p3v: 3p3v {
++ reg_3p3v: regulator@1 {
+ compatible = "regulator-fixed";
++ reg = <1>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+@@ -54,14 +58,14 @@
+
+ &audmux {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_audmux_2>;
++ pinctrl-0 = <&pinctrl_audmux>;
+ status = "okay";
+ };
+
+ &i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_i2c2_2>;
++ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ codec: sgtl5000@0a {
+@@ -77,7 +81,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+- hog {
++ imx6qdl-wandboard {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+@@ -91,12 +95,110 @@
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
+ >;
+ };
++
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
++ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
++ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
++ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_spdif: spdifgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart3: uart3grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc1: usdhc1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
+ };
+ };
+
+ &fec {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_1>;
++ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio3 29 0>;
+ status = "okay";
+@@ -104,7 +206,7 @@
+
+ &spdif {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_spdif_3>;
++ pinctrl-0 = <&pinctrl_spdif>;
+ status = "okay";
+ };
+
+@@ -115,13 +217,13 @@
+
+ &uart1 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart1_1>;
++ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+ };
+
+ &uart3 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart3_2>;
++ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+ };
+@@ -132,7 +234,7 @@
+
+ &usbotg {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usbotg_1>;
++ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ dr_mode = "peripheral";
+ status = "okay";
+@@ -140,21 +242,21 @@
+
+ &usdhc1 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc1_2>;
++ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 2 0>;
+ status = "okay";
+ };
+
+ &usdhc2 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc2_2>;
++ pinctrl-0 = <&pinctrl_usdhc2>;
+ non-removable;
+ status = "okay";
+ };
+
+ &usdhc3 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_2>;
++ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio3 9 0>;
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q.dtsi linux-3.14.72/arch/arm/boot/dts/imx6q.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -1,6 +1,6 @@
+
+ /*
+- * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -8,15 +8,20 @@
+ *
+ */
+
++#include <dt-bindings/interrupt-controller/irq.h>
+ #include "imx6q-pinfunc.h"
+ #include "imx6qdl.dtsi"
+
+ / {
++ aliases {
++ ipu1 = &ipu2;
++ };
++
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- cpu@0 {
++ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+@@ -25,14 +30,29 @@
+ /* kHz uV */
+ 1200000 1275000
+ 996000 1250000
+- 792000 1150000
+- 396000 950000
++ 852000 1250000
++ 792000 1175000
++ 396000 1175000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 1200000 1275000
++ 996000 1250000
++ 852000 1250000
++ 792000 1175000
++ 396000 1175000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+- clocks = <&clks 104>, <&clks 6>, <&clks 16>,
+- <&clks 17>, <&clks 170>;
++ clocks = <&clks IMX6QDL_CLK_ARM>,
++ <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
++ <&clks IMX6QDL_CLK_STEP>,
++ <&clks IMX6QDL_CLK_PLL1_SW>,
++ <&clks IMX6QDL_CLK_PLL1_SYS>,
++ <&clks IMX6QDL_PLL1_BYPASS>,
++ <&clks IMX6QDL_CLK_PLL1>,
++ <&clks IMX6QDL_PLL1_BYPASS_SRC> ;
+ clock-names = "arm", "pll2_pfd2_396m", "step",
+- "pll1_sw", "pll1_sys";
++ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
+ arm-supply = <&reg_arm>;
+ pu-supply = <&reg_pu>;
+ soc-supply = <&reg_soc>;
+@@ -61,10 +81,54 @@
+ };
+
+ soc {
+- ocram: sram@00900000 {
++ busfreq {
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
++ interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
++ fsl,max_ddr_freq = <528000000>;
++ };
++
++ gpu@00130000 {
++ compatible = "fsl,imx6q-gpu";
++ reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
++ <0x02204000 0x4000>, <0x0 0x0>;
++ reg-names = "iobase_3d", "iobase_2d",
++ "iobase_vg", "phys_baseaddr";
++ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>,
++ <0 10 IRQ_TYPE_LEVEL_HIGH>,
++ <0 11 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "irq_3d", "irq_2d", "irq_vg";
++ clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>,
++ <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>,
++ <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>;
++ clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
++ "gpu3d_axi_clk", "gpu2d_clk",
++ "gpu3d_clk", "gpu3d_shader_clk";
++ resets = <&src 0>, <&src 3>, <&src 3>;
++ reset-names = "gpu3d", "gpu2d", "gpuvg";
++ power-domains = <&gpc 1>;
++ };
++
++ ocrams: sram@00900000 {
++ compatible = "fsl,lpm-sram";
++ reg = <0x00900000 0x4000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocrams_ddr: sram@00904000 {
++ compatible = "fsl,ddr-lpm-sram";
++ reg = <0x00904000 0x1000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
++ };
++
++ ocram: sram@00905000 {
+ compatible = "mmio-sram";
+- reg = <0x00900000 0x40000>;
+- clocks = <&clks 142>;
++ reg = <0x00905000 0x3B000>;
++ clocks = <&clks IMX6QDL_CLK_OCRAM>;
+ };
+
+ aips-bus@02000000 { /* AIPS1 */
+@@ -74,8 +138,9 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02018000 0x4000>;
+- interrupts = <0 35 0x04>;
+- clocks = <&clks 116>, <&clks 116>;
++ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6Q_CLK_ECSPI5>,
++ <&clks IMX6Q_CLK_ECSPI5>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+@@ -122,40 +187,81 @@
+ };
+ };
+
++ aips-bus@02100000 { /* AIPS2 */
++ mipi_dsi: mipi@021e0000 {
++ compatible = "fsl,imx6q-mipi-dsi";
++ reg = <0x021e0000 0x4000>;
++ interrupts = <0 102 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>;
++ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
++ status = "disabled";
++ };
++ };
++
+ sata: sata@02200000 {
+ compatible = "fsl,imx6q-ahci";
+ reg = <0x02200000 0x4000>;
+- interrupts = <0 39 0x04>;
+- clocks = <&clks 154>, <&clks 187>, <&clks 105>;
++ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_SATA>,
++ <&clks IMX6QDL_CLK_SATA_REF_100M>,
++ <&clks IMX6QDL_CLK_AHB>;
+ clock-names = "sata", "sata_ref", "ahb";
+ status = "disabled";
+ };
+
+ ipu2: ipu@02800000 {
+- #crtc-cells = <1>;
+ compatible = "fsl,imx6q-ipu";
+ reg = <0x02800000 0x400000>;
+- interrupts = <0 8 0x4 0 7 0x4>;
+- clocks = <&clks 133>, <&clks 134>, <&clks 137>;
+- clock-names = "bus", "di0", "di1";
++ interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
++ <0 7 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6QDL_CLK_IPU2>,
++ <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>,
++ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
++ <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
++ clock-names = "bus",
++ "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
+ resets = <&src 4>;
++ bypass_reset = <0>;
+ };
+ };
+ };
+
+-&ldb {
+- clocks = <&clks 33>, <&clks 34>,
+- <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
+- <&clks 135>, <&clks 136>;
+- clock-names = "di0_pll", "di1_pll",
+- "di0_sel", "di1_sel", "di2_sel", "di3_sel",
+- "di0", "di1";
++&ecspi1 {
++ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
++ dma-names = "rx", "tx";
++};
+
+- lvds-channel@0 {
+- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+- };
++&ecspi2 {
++ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
++ dma-names = "rx", "tx";
++};
+
+- lvds-channel@1 {
+- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+- };
++&ecspi3 {
++ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
++ dma-names = "rx", "tx";
++};
++
++&ecspi4 {
++ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
++ dma-names = "rx", "tx";
++};
++
++&ldb {
++ compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
++
++ clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>,
++ <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
++ <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>,
++ <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>;
++ clock-names = "ldb_di0", "ldb_di1",
++ "di0_sel", "di1_sel",
++ "di2_sel", "di3_sel",
++ "ldb_di0_div_3_5", "ldb_di1_div_3_5",
++ "ldb_di0_div_7", "ldb_di1_div_7",
++ "ldb_di0_div_sel", "ldb_di1_div_sel";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-hummingboard2.dts linux-3.14.72/arch/arm/boot/dts/imx6q-hummingboard2.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-hummingboard2.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-hummingboard2.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,60 @@
++/*
++ * Device Tree file for SolidRun HummingBoard2
++ * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
++ * Based on work by Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include "imx6qdl-hummingboard2.dtsi"
++
++/ {
++ model = "SolidRun HummingBoard2 Dual/Quad";
++ compatible = "solidrun,hummingboard2/q", "fsl,imx6q";
++};
++
++&sata {
++ status = "okay";
++ fsl,transmit-level-mV = <1104>;
++ fsl,transmit-boost-mdB = <0>;
++ fsl,transmit-atten-16ths = <9>;
++ fsl,no-spread-spectrum;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-hummingboard.dts linux-3.14.72/arch/arm/boot/dts/imx6q-hummingboard.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-hummingboard.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-hummingboard.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,59 @@
++/*
++ * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
++ * Based on dt work by Russell King
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ * a) This file is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License.
++ *
++ * This file is distributed in the hope that it will be useful
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Or, alternatively
++ *
++ * b) Permission is hereby granted, free of charge, to any person
++ * obtaining a copy of this software and associated documentation
++ * files (the "Software"), to deal in the Software without
++ * restriction, including without limitation the rights to use
++ * copy, modify, merge, publish, distribute, sublicense, and/or
++ * sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following
++ * conditions:
++ *
++ * The above copyright notice and this permission notice shall be
++ * included in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include "imx6qdl-hummingboard.dtsi"
++
++/ {
++ model = "SolidRun HummingBoard Dual/Quad";
++ compatible = "solidrun,hummingboard/q", "fsl,imx6q";
++};
++
++&sata {
++ status = "okay";
++ fsl,transmit-level-mV = <1025>;
++ fsl,transmit-boost-mdB = <3330>;
++ fsl,transmit-atten-16ths = <9>;
++ fsl,receive-eq-mdB = <3000>;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi linux-3.14.72/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi 2016-06-19 22:11:55.025157951 +0200
+@@ -22,7 +22,7 @@
+
+ &ecspi3 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_ecspi3_1>;
++ pinctrl-0 = <&pinctrl_ecspi3>;
+ status = "okay";
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 24 0>;
+@@ -36,7 +36,7 @@
+
+ &i2c1 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_i2c1_1>;
++ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ eeprom@50 {
+@@ -128,7 +128,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+- hog {
++ imx6q-phytec-pfla02 {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+@@ -136,10 +136,73 @@
+ MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
+ >;
+ };
+- };
+
+- pfla02 {
+- pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
++ pinctrl_ecspi3: ecspi3grp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
++ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
++ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_uart4: uart4grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_cdwp: usdhc3cdwp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+@@ -150,7 +213,7 @@
+
+ &fec {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_3>;
++ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio3 23 0>;
+ status = "disabled";
+@@ -158,13 +221,13 @@
+
+ &uart4 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart4_1>;
++ pinctrl-0 = <&pinctrl_uart4>;
+ status = "disabled";
+ };
+
+ &usdhc2 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc2_2>;
++ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 0>;
+ wp-gpios = <&gpio1 2 0>;
+ status = "disabled";
+@@ -172,8 +235,8 @@
+
+ &usdhc3 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_2
+- &pinctrl_usdhc3_pfla02>;
++ pinctrl-0 = <&pinctrl_usdhc3
++ &pinctrl_usdhc3_cdwp>;
+ cd-gpios = <&gpio1 27 0>;
+ wp-gpios = <&gpio1 29 0>;
+ status = "disabled";
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-pinfunc.h linux-3.14.72/arch/arm/boot/dts/imx6q-pinfunc.h
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-pinfunc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-pinfunc.h 2016-06-19 22:11:55.025157951 +0200
+@@ -673,6 +673,7 @@
+ #define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
+ #define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
+ #define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
++#define MX6QDL_PAD_GPIO_6__ENET_IRQ 0x230 0x600 0x03c 0x11 0xff000609
+ #define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
+ #define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
+ #define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -20,6 +20,32 @@
+ compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+ };
+
++&ldb {
++ lvds-channel@0 {
++ crtc = "ipu2-di0";
++ };
++
++ lvds-channel@1 {
++ crtc = "ipu2-di1";
++ };
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&mxcfb3 {
++ status = "okay";
++};
++
++&mxcfb4 {
++ status = "okay";
++};
++
+ &sata {
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto-ecspi.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,40 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabreauto.dts"
++
++&ecspi1 {
++ pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&i2c3 {
++ /* pin conflict with ecspi1 */
++ status = "disabled";
++};
++
++&uart3 {
++ /* the uart3 depends on the i2c3, so disable it too. */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ /* max7310_c on i2c3 is gone */
++ status = "okay";
++ dr_mode = "peripheral";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto-flexcan1.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabreauto.dts"
++
++&flexcan1{
++ status = "okay";
++};
++
++&fec {
++ /* pin conflict with flexcan1 */
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabreauto-gpmi-weim.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabreauto.dts"
++
++&ecspi1 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&flexcan2 {
++ /* max7310_c on i2c3 is gone */
++ status = "disabled";
++};
++
++&gpmi {
++ status = "okay";
++};
++
++&i2c3 {
++ /* pin conflict with weim */
++ status = "disabled";
++};
++
++&uart3 {
++ /* pin conflict with gpmi and weim */
++ status = "disabled";
++};
++
++&usbh1 {
++ /* max7310_b on i2c3 is gone */
++ status = "disabled";
++};
++
++&usbotg {
++ /* max7310_c on i2c3 is gone */
++ status = "okay";
++ dr_mode = "peripheral";
++};
++
++&weim {
++ pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabrelite.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabrelite.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabrelite.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabrelite.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -23,25 +23,30 @@
+
+ regulators {
+ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
+
+- reg_2p5v: 2p5v {
++ reg_2p5v: regulator@0 {
+ compatible = "regulator-fixed";
++ reg = <0>;
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+- reg_3p3v: 3p3v {
++ reg_3p3v: regulator@1 {
+ compatible = "regulator-fixed";
++ reg = <1>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+- reg_usb_otg_vbus: usb_otg_vbus {
++ reg_usb_otg_vbus: regulator@2 {
+ compatible = "regulator-fixed";
++ reg = <2>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+@@ -54,7 +59,7 @@
+ compatible = "fsl,imx6q-sabrelite-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6q-sabrelite-sgtl5000";
+- ssi-controller = <&ssi1>;
++ cpu-dai = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+@@ -68,14 +73,14 @@
+ &audmux {
+ status = "okay";
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_audmux_1>;
++ pinctrl-0 = <&pinctrl_audmux>;
+ };
+
+ &ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 19 0>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_ecspi1_1>;
++ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80@0 {
+@@ -87,7 +92,7 @@
+
+ &fec {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_1>;
++ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-gpios = <&gpio3 23 0>;
+ status = "okay";
+@@ -97,7 +102,7 @@
+ status = "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_i2c1_1>;
++ pinctrl-0 = <&pinctrl_i2c1>;
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+@@ -112,7 +117,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+- hog {
++ imx6q-sabrelite {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
+@@ -126,6 +131,86 @@
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+ >;
+ };
++
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
++ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
++ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
++ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
++ >;
++ };
++
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc4: usdhc4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
++ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
++ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++ >;
++ };
+ };
+ };
+
+@@ -166,7 +251,7 @@
+ &uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart2_1>;
++ pinctrl-0 = <&pinctrl_uart2>;
+ };
+
+ &usbh1 {
+@@ -176,14 +261,14 @@
+ &usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usbotg_1>;
++ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+ };
+
+ &usdhc3 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_2>;
++ pinctrl-0 = <&pinctrl_usdhc3>;
+ cd-gpios = <&gpio7 0 0>;
+ wp-gpios = <&gpio7 1 0>;
+ vmmc-supply = <&reg_3p3v>;
+@@ -192,7 +277,7 @@
+
+ &usdhc4 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc4_2>;
++ pinctrl-0 = <&pinctrl_usdhc4>;
+ cd-gpios = <&gpio2 6 0>;
+ wp-gpios = <&gpio2 7 0>;
+ vmmc-supply = <&reg_3p3v>;
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -20,6 +20,38 @@
+ compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
+ };
+
++&battery {
++ offset-charger = <1900>;
++ offset-discharger = <1694>;
++ offset-usb-charger = <1685>;
++};
++
++&ldb {
++ lvds-channel@0 {
++ crtc = "ipu2-di0";
++ };
++
++ lvds-channel@1 {
++ crtc = "ipu2-di1";
++ };
++};
++
++&mxcfb1 {
++ status = "okay";
++};
++
++&mxcfb2 {
++ status = "okay";
++};
++
++&mxcfb3 {
++ status = "okay";
++};
++
++&mxcfb4 {
++ status = "okay";
++};
++
+ &sata {
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-enetirq.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabresd.dts"
++
++&fec {
++ pinctrl-0 = <&pinctrl_enet &pinctrl_enet_irq>;
++ interrupts-extended = <&gpio1 6 0x04>, <&intc 0 119 0x04>;
++};
++
++&i2c3 {
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-hdcp.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,23 @@
++/*
++ * Copyright 2012-2014 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include "imx6q-sabresd.dts"
++
++&hdmi_video {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_hdcp>;
++ fsl,hdcp;
++};
++
++&i2c2 {
++ status = "disable";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-ldo.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-ldo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-ldo.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabresd.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++};
++
++&gpc {
++ /* use ldo-enable, u-boot will check it and configure */
++ fsl,ldo-bypass = <0>;
++ /* watchdog select of reset source */
++ fsl,wdog-reset = <1>;
++};
++
++&wdog1 {
++ status = "okay";
++};
++
++&wdog2 {
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-uart.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-uart.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sabresd-uart.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sabresd-uart.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,30 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6q-sabresd.dts"
++
++/ {
++ leds {
++ compatible = "gpio-leds";
++ status = "disabled";
++ };
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5_1>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++ /* for DTE mode, add below change */
++ /* fsl,dte-mode; */
++ /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
++};
++
++&ecspi1 {
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sbc6x.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sbc6x.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sbc6x.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sbc6x.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -17,28 +17,78 @@
+ };
+ };
+
++
+ &fec {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_enet_1>;
++ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ status = "okay";
+ };
+
++&iomuxc {
++ imx6q-sbc6x {
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
++ };
++};
++
+ &uart1 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart1_1>;
++ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+ };
+
+ &usbotg {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usbotg_1>;
++ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+ };
+
+ &usdhc3 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_2>;
++ pinctrl-0 = <&pinctrl_usdhc3>;
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sbc-fx6.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sbc-fx6.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sbc-fx6.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sbc-fx6.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,23 @@
++/*
++* Copyright 2014 CompuLab Ltd.
++*
++* Author: Valentin Raevsky <valentin@compulab.co.il>
++*
++* The code contained herein is licensed under the GNU General Public
++* License. You may obtain a copy of the GNU General Public License
++* Version 2 or later at the following locations:
++*
++* http://www.opensource.org/licenses/gpl-license.html
++* http://www.gnu.org/copyleft/gpl.html
++*/
++
++/dts-v1/;
++#include "imx6q.dtsi"
++#include "imx6q-cm-fx6.dtsi"
++#include "imx6qdl-sb-fx6x.dtsi"
++#include "imx6qdl-sb-fx6.dtsi"
++
++/ {
++ model = "CompuLab CM-FX6 on SBC-FX6";
++ compatible = "compulab,cm-fx6", "compulab,sbc-fx6", "fsl,imx6q";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sbc-fx6m.dts linux-3.14.72/arch/arm/boot/dts/imx6q-sbc-fx6m.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-sbc-fx6m.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-sbc-fx6m.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,33 @@
++/*
++* Copyright 2014 CompuLab Ltd.
++*
++* Author: Valentin Raevsky <valentin@compulab.co.il>
++*
++* The code contained herein is licensed under the GNU General Public
++* License. You may obtain a copy of the GNU General Public License
++* Version 2 or later at the following locations:
++*
++* http://www.opensource.org/licenses/gpl-license.html
++* http://www.gnu.org/copyleft/gpl.html
++*/
++
++/dts-v1/;
++#include "imx6q.dtsi"
++#include "imx6q-cm-fx6.dtsi"
++#include "imx6qdl-sb-fx6x.dtsi"
++#include "imx6qdl-sb-fx6m.dtsi"
++
++/ {
++ model = "CompuLab CM-FX6 on SBC-FX6m";
++ compatible = "compulab,cm-fx6", "compulab,sbc-fx6m", "fsl,imx6q";
++
++ aliases {
++ mmc0 = &usdhc3;
++ };
++};
++
++&hdmi_core {
++ ipu_id = <1>;
++ disp_id = <0>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-tbs2910.dts linux-3.14.72/arch/arm/boot/dts/imx6q-tbs2910.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-tbs2910.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-tbs2910.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -0,0 +1,643 @@
++/*
++ * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "TBS Matrix";
++ compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
++
++ aliases {
++ mxcfb0 = &mxcfb1;
++ mxcfb1 = &mxcfb2;
++ mxcfb2 = &mxcfb3;
++ mxcfb3 = &mxcfb4;
++ mmc0 = &usdhc4;
++ };
++
++ chosen {
++ stdout-path = &uart1;
++ };
++
++ memory {
++ reg = <0x10000000 0x80000000>;
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_2p5v: regulator@0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ regulator-name = "2P5V";
++ regulator-min-microvolt = <2500000>;
++ regulator-max-microvolt = <2500000>;
++ };
++
++ reg_3p3v: regulator@1 {
++ compatible = "regulator-fixed";
++ reg = <1>;
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ reg_5p0v: regulator@2 {
++ compatible = "regulator-fixed";
++ reg = <2>;
++ regulator-name = "5P0V";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++ };
++
++ ir_recv: ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ir>;
++ linux,rc-map-name = "rc-rc6-mce";
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_leds>;
++
++ red {
++ label = "red";
++ gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ fan {
++ compatible = "gpio-fan";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_fan>;
++ gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
++ gpio-fan,speed-map = <0 0
++ 3000 1>;
++ };
++
++ sound {
++ compatible = "fsl,imx-audio-sgtl5000";
++ model = "imx-sgtl5000";
++ cpu-dai = <&ssi2>;
++ audio-codec = <&codec>;
++ audio-routing = "MIC_IN", "Mic Jack",
++ "Mic Jack", "Mic Bias",
++ "Headphone Jack", "HP_OUT";
++ mux-int-port = <2>;
++ mux-ext-port = <3>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ mxcfb2: fb@1 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <24>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb3: fb@2 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "lcd";
++ interface_pix_fmt = "RGB565";
++ mode_str ="CLAA-WVGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ mxcfb4: fb@3 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "disabled";
++ };
++
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
++ };
++
++ restart_poweroff {
++ compatible = "fsl,snvs-poweroff";
++ };
++};
++
++&sata {
++ status = "okay";
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux>;
++ status = "okay";
++};
++
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii";
++ phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ codec: sgtl5000@0a {
++ clocks = <&clks 201>;
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_sgtl5000>;
++ VDDA-supply = <&reg_2p5v>;
++ VDDIO-supply = <&reg_3p3v>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++
++ hdmi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++};
++
++&i2c3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++
++ rtc: ds1307@68 {
++ compatible = "dallas,ds1307";
++ reg = <0x68>;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++
++ imx6qdl-sabresd {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* HUB_GPIO_RST */
++ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* eMMC_RST */
++ >;
++ };
++
++ pinctrl_sgtl5000: sgtl5000grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
++ >;
++ };
++
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
++ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
++ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
++ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
++ >;
++ };
++
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
++ >;
++ };
++
++ pinctrl_ir: sabresd-ir {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059
++ >;
++ };
++
++ pinctrl_sabresd_spdif: sabresd-spdif {
++ fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091>;
++ };
++
++ pinctrl_hdmi_cec: hdmi_cecgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
++ >;
++ };
++
++ pinctrl_hdmi_hdcp: hdmi_hdcpgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_pcie: pciegrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059
++ >;
++ };
++
++ pinctrl_pwm1: pwm1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059
++ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059
++ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059
++ >;
++ };
++
++ pinctrl_usdhc4: usdhc4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
++ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
++ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
++ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
++ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
++ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
++ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
++ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
++ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
++ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
++ >;
++ };
++ };
++
++ gpio_leds {
++ pinctrl_gpio_leds: gpioledsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1
++ >;
++ };
++ };
++
++ gpio_fan {
++ pinctrl_gpio_fan: gpiofangrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1
++ >;
++ };
++ };
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ power-on-gpio = <&gpio3 19 0>;
++ reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm1>;
++ status = "okay";
++};
++
++&ldb {
++ ipu_id = <1>;
++ disp_id = <1>;
++ ext_ref = <1>;
++ mode = "sep1";
++ sec_ipu_id = <1>;
++ sec_disp_id = <0>;
++ status = "okay";
++};
++
++&ssi2 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_sabresd_spdif>;
++ status = "okay";
++};
++
++&usbh1 {
++ vbus-supply = <&reg_5p0v>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_5p0v>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2>;
++ bus-width = <4>;
++ cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
++ card-external-vcc-supply = <&reg_3p3v>;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ bus-width = <4>;
++ cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
++ card-external-vcc-supply = <&reg_3p3v>;
++ status = "okay";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4>;
++ bus-width = <8>;
++ non-removable;
++ no-1-8-v;
++ status = "okay";
++};
++
++&hdmi_core {
++ ipu_id = <0>;
++ disp_id = <0>;
++ status = "okay";
++};
++
++&hdmi_video {
++ fsl,phy_reg_vlev = <0x0294>;
++ fsl,phy_reg_cksymtx = <0x800d>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
++};
++
++&hdmi_cec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hdmi_cec>;
++ status = "okay";
++};
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0xf>;
++ fsl,cpu_pupscr_sw = <0xf>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6q-udoo.dts linux-3.14.72/arch/arm/boot/dts/imx6q-udoo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6q-udoo.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6q-udoo.dts 2016-06-19 22:11:55.025157951 +0200
+@@ -2,6 +2,7 @@
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
++ * Author: Ettore Chimenti <ettore.chimenti@udoo.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -11,29 +12,14 @@
+
+ /dts-v1/;
+ #include "imx6q.dtsi"
++#include "imx6qdl-udoo.dtsi"
+
+ / {
+ model = "Udoo i.MX6 Quad Board";
+ compatible = "udoo,imx6q-udoo", "fsl,imx6q";
+-
+- memory {
+- reg = <0x10000000 0x40000000>;
+- };
+ };
+
+ &sata {
+ status = "okay";
+ };
+
+-&uart2 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart2_1>;
+- status = "okay";
+-};
+-
+-&usdhc3 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usdhc3_2>;
+- non-removable;
+- status = "okay";
+-};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sl.dtsi linux-3.14.72/arch/arm/boot/dts/imx6sl.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sl.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6sl.dtsi 2016-06-19 22:11:55.029157811 +0200
+@@ -7,6 +7,8 @@
+ *
+ */
+
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include "skeleton.dtsi"
+ #include "imx6sl-pinfunc.h"
+ #include <dt-bindings/clock/imx6sl-clock.h>
+@@ -18,6 +20,10 @@
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
++ mmc0 = &usdhc1;
++ mmc1 = &usdhc2;
++ mmc2 = &usdhc3;
++ mmc3 = &usdhc4;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+@@ -27,25 +33,49 @@
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
++ usbphy0 = &usbphy1;
++ usbphy1 = &usbphy2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- cpu@0 {
++ cpu0: cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
++ operating-points = <
++ /* kHz uV */
++ 996000 1275000
++ 792000 1175000
++ 396000 975000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC-PU uV */
++ 996000 1225000
++ 792000 1175000
++ 396000 1175000
++ >;
++ clock-latency = <61036>; /* two CLK32 periods */
++ clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
++ <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
++ <&clks IMX6SL_CLK_PLL1_SYS>,
++ <&clks IMX6SL_PLL1_BYPASS>,
++ <&clks IMX6SL_CLK_PLL1>,
++ <&clks IMX6SL_PLL1_BYPASS_SRC> ;
++ clock-names = "arm", "pll2_pfd2_396m", "step",
++ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
++ arm-supply = <&reg_arm>;
++ pu-supply = <&reg_pu>;
++ soc-supply = <&reg_soc>;
+ };
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+- #address-cells = <1>;
+- #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+@@ -66,6 +96,10 @@
+ };
+ };
+
++ reg_vbus_wakeup: usb_vbus_wakeup {
++ compatible = "fsl,imx6-dummy-ldo2p5";
++ };
++
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+@@ -73,19 +107,60 @@
+ interrupt-parent = <&intc>;
+ ranges;
+
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>,
++ <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>,
++ <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>,
++ <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>,
++ <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>,
++ <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>,
++ <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM>,
++ <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
++ <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>,
++ <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>,
++ <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>,
++ <&clks IMX6SL_PLL1_BYPASS_SRC>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb",
++ "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src",
++ "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src";
++ fsl,max_ddr_freq = <400000000>;
++ };
++
++ ocrams: sram@00900000 {
++ compatible = "fsl,lpm-sram";
++ reg = <0x00900000 0x4000>;
++ clocks = <&clks IMX6SL_CLK_OCRAM>;
++ };
++
++ ocrams_ddr: sram@00904000 {
++ compatible = "fsl,ddr-lpm-sram";
++ reg = <0x00904000 0x1000>;
++ clocks = <&clks IMX6SL_CLK_OCRAM>;
++ };
++
++ ocram: sram@00905000 {
++ compatible = "mmio-sram";
++ reg = <0x00905000 0x1B000>;
++ clocks = <&clks IMX6SL_CLK_OCRAM>;
++ };
++
+ L2: l2-cache@00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+- interrupts = <0 92 0x04>;
++ interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
++ arm,dynamic-clk-gating;
++ arm,standby-mode;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+- interrupts = <0 94 0x04>;
++ interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ aips1: aips-bus@02000000 {
+@@ -103,8 +178,24 @@
+ ranges;
+
+ spdif: spdif@02004000 {
++ compatible = "fsl,imx6sl-spdif",
++ "fsl,imx35-spdif";
+ reg = <0x02004000 0x4000>;
+- interrupts = <0 52 0x04>;
++ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&sdma 14 18 0>,
++ <&sdma 15 18 0>;
++ dma-names = "rx", "tx";
++ clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
++ <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
++ <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
++ <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
++ <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
++ clock-names = "core", "rxtx0",
++ "rxtx1", "rxtx2",
++ "rxtx3", "rxtx4",
++ "rxtx5", "rxtx6",
++ "rxtx7", "dma";
++ status = "disabled";
+ };
+
+ ecspi1: ecspi@02008000 {
+@@ -112,10 +203,12 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02008000 0x4000>;
+- interrupts = <0 31 0x04>;
++ interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_ECSPI1>,
+ <&clks IMX6SL_CLK_ECSPI1>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+@@ -124,10 +217,12 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+ reg = <0x0200c000 0x4000>;
+- interrupts = <0 32 0x04>;
++ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_ECSPI2>,
+ <&clks IMX6SL_CLK_ECSPI2>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+@@ -136,10 +231,12 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02010000 0x4000>;
+- interrupts = <0 33 0x04>;
++ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_ECSPI3>,
+ <&clks IMX6SL_CLK_ECSPI3>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+@@ -148,10 +245,12 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+ reg = <0x02014000 0x4000>;
+- interrupts = <0 34 0x04>;
++ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_ECSPI4>,
+ <&clks IMX6SL_CLK_ECSPI4>;
+ clock-names = "ipg", "per";
++ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
++ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+@@ -159,7 +258,7 @@
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02018000 0x4000>;
+- interrupts = <0 30 0x04>;
++ interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_UART>,
+ <&clks IMX6SL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+@@ -172,7 +271,7 @@
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+- interrupts = <0 26 0x04>;
++ interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_UART>,
+ <&clks IMX6SL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+@@ -185,7 +284,7 @@
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02024000 0x4000>;
+- interrupts = <0 27 0x04>;
++ interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_UART>,
+ <&clks IMX6SL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+@@ -197,8 +296,10 @@
+ ssi1: ssi@02028000 {
+ compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+ reg = <0x02028000 0x4000>;
+- interrupts = <0 46 0x04>;
+- clocks = <&clks IMX6SL_CLK_SSI1>;
++ interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
++ <&clks IMX6SL_CLK_SSI1>;
++ clock-names = "ipg", "baud";
+ dmas = <&sdma 37 1 0>,
+ <&sdma 38 1 0>;
+ dma-names = "rx", "tx";
+@@ -209,8 +310,10 @@
+ ssi2: ssi@0202c000 {
+ compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+ reg = <0x0202c000 0x4000>;
+- interrupts = <0 47 0x04>;
+- clocks = <&clks IMX6SL_CLK_SSI2>;
++ interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
++ <&clks IMX6SL_CLK_SSI2>;
++ clock-names = "ipg", "baud";
+ dmas = <&sdma 41 1 0>,
+ <&sdma 42 1 0>;
+ dma-names = "rx", "tx";
+@@ -221,8 +324,10 @@
+ ssi3: ssi@02030000 {
+ compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+ reg = <0x02030000 0x4000>;
+- interrupts = <0 48 0x04>;
+- clocks = <&clks IMX6SL_CLK_SSI3>;
++ interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
++ <&clks IMX6SL_CLK_SSI3>;
++ clock-names = "ipg", "baud";
+ dmas = <&sdma 45 1 0>,
+ <&sdma 46 1 0>;
+ dma-names = "rx", "tx";
+@@ -234,7 +339,7 @@
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02034000 0x4000>;
+- interrupts = <0 28 0x04>;
++ interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_UART>,
+ <&clks IMX6SL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+@@ -247,7 +352,7 @@
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02038000 0x4000>;
+- interrupts = <0 29 0x04>;
++ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_UART>,
+ <&clks IMX6SL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+@@ -261,7 +366,7 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+ reg = <0x02080000 0x4000>;
+- interrupts = <0 83 0x04>;
++ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_PWM1>,
+ <&clks IMX6SL_CLK_PWM1>;
+ clock-names = "ipg", "per";
+@@ -271,7 +376,7 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+ reg = <0x02084000 0x4000>;
+- interrupts = <0 84 0x04>;
++ interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_PWM2>,
+ <&clks IMX6SL_CLK_PWM2>;
+ clock-names = "ipg", "per";
+@@ -281,7 +386,7 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+ reg = <0x02088000 0x4000>;
+- interrupts = <0 85 0x04>;
++ interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_PWM3>,
+ <&clks IMX6SL_CLK_PWM3>;
+ clock-names = "ipg", "per";
+@@ -291,7 +396,7 @@
+ #pwm-cells = <2>;
+ compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+ reg = <0x0208c000 0x4000>;
+- interrupts = <0 86 0x04>;
++ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_PWM4>,
+ <&clks IMX6SL_CLK_PWM4>;
+ clock-names = "ipg", "per";
+@@ -300,7 +405,7 @@
+ gpt: gpt@02098000 {
+ compatible = "fsl,imx6sl-gpt";
+ reg = <0x02098000 0x4000>;
+- interrupts = <0 55 0x04>;
++ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_GPT>,
+ <&clks IMX6SL_CLK_GPT_SERIAL>;
+ clock-names = "ipg", "per";
+@@ -309,7 +414,8 @@
+ gpio1: gpio@0209c000 {
+ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+ reg = <0x0209c000 0x4000>;
+- interrupts = <0 66 0x04 0 67 0x04>;
++ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
++ <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -319,7 +425,8 @@
+ gpio2: gpio@020a0000 {
+ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+ reg = <0x020a0000 0x4000>;
+- interrupts = <0 68 0x04 0 69 0x04>;
++ interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
++ <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -329,7 +436,8 @@
+ gpio3: gpio@020a4000 {
+ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+ reg = <0x020a4000 0x4000>;
+- interrupts = <0 70 0x04 0 71 0x04>;
++ interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
++ <0 71 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -339,7 +447,8 @@
+ gpio4: gpio@020a8000 {
+ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+ reg = <0x020a8000 0x4000>;
+- interrupts = <0 72 0x04 0 73 0x04>;
++ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
++ <0 73 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -349,7 +458,8 @@
+ gpio5: gpio@020ac000 {
+ compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+ reg = <0x020ac000 0x4000>;
+- interrupts = <0 74 0x04 0 75 0x04>;
++ interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
++ <0 75 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+@@ -357,21 +467,23 @@
+ };
+
+ kpp: kpp@020b8000 {
++ compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
+ reg = <0x020b8000 0x4000>;
+- interrupts = <0 82 0x04>;
++ interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_DUMMY>;
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+- interrupts = <0 80 0x04>;
++ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_DUMMY>;
+ };
+
+ wdog2: wdog@020c0000 {
+ compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+ reg = <0x020c0000 0x4000>;
+- interrupts = <0 81 0x04>;
++ interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_DUMMY>;
+ status = "disabled";
+ };
+@@ -379,7 +491,8 @@
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6sl-ccm";
+ reg = <0x020c4000 0x4000>;
+- interrupts = <0 87 0x04 0 88 0x04>;
++ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
++ <0 88 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+
+@@ -388,7 +501,9 @@
+ "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+- interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
++ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
++ <0 54 IRQ_TYPE_LEVEL_HIGH>,
++ <0 127 IRQ_TYPE_LEVEL_HIGH>;
+
+ regulator-1p1@110 {
+ compatible = "fsl,anatop-regulator";
+@@ -434,7 +549,7 @@
+
+ reg_arm: regulator-vddcore@140 {
+ compatible = "fsl,anatop-regulator";
+- regulator-name = "cpu";
++ regulator-name = "vddarm";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-always-on;
+@@ -447,6 +562,7 @@
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
++ regulator-allow-bypass;
+ };
+
+ reg_pu: regulator-vddpu@140 {
+@@ -454,7 +570,8 @@
+ regulator-name = "vddpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1450000>;
+- regulator-always-on;
++ regulator-enable-ramp-delay = <150>;
++ regulator-boot-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <9>;
+ anatop-vol-bit-width = <5>;
+@@ -464,6 +581,7 @@
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
++ regulator-allow-bypass;
+ };
+
+ reg_soc: regulator-vddsoc@140 {
+@@ -481,21 +599,38 @@
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1450000>;
++ regulator-allow-bypass;
+ };
+ };
+
++ tempmon: tempmon {
++ compatible = "fsl,imx6sl-tempmon", "fsl,imx6q-tempmon";
++ interrupts = <0 49 0x04>;
++ fsl,tempmon = <&anatop>;
++ fsl,tempmon-data = <&ocotp>;
++ clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
++ };
++
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+- interrupts = <0 44 0x04>;
++ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USBPHY1>;
++ fsl,anatop = <&anatop>;
+ };
+
+ usbphy2: usbphy@020ca000 {
+ compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020ca000 0x1000>;
+- interrupts = <0 45 0x04>;
++ interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USBPHY2>;
++ fsl,anatop = <&anatop>;
++ };
++
++ usbphy_nop1: usbphy_nop1 {
++ compatible = "usb-nop-xceiv";
++ clocks = <&clks IMX6SL_CLK_USBPHY1>;
++ clock-names = "main_clk";
+ };
+
+ snvs@020cc000 {
+@@ -507,31 +642,41 @@
+ snvs-rtc-lp@34 {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ reg = <0x34 0x58>;
+- interrupts = <0 19 0x04 0 20 0x04>;
++ interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
++ <0 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ epit1: epit@020d0000 {
+ reg = <0x020d0000 0x4000>;
+- interrupts = <0 56 0x04>;
++ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ epit2: epit@020d4000 {
+ reg = <0x020d4000 0x4000>;
+- interrupts = <0 57 0x04>;
++ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6sl-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+- interrupts = <0 91 0x04 0 96 0x04>;
++ interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
++ <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+- interrupts = <0 89 0x04>;
++ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
++ pu-supply = <&reg_pu>;
++ clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>,
++ <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>,
++ <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>,
++ <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>;
++ clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi",
++ "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi";
++ #power-domain-cells = <1>;
+ };
+
+ gpr: iomuxc-gpr@020e0000 {
+@@ -543,261 +688,69 @@
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6sl-iomuxc";
+ reg = <0x020e0000 0x4000>;
+-
+- ecspi1 {
+- pinctrl_ecspi1_1: ecspi1grp-1 {
+- fsl,pins = <
+- MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
+- MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
+- MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
+- >;
+- };
+- };
+-
+- fec {
+- pinctrl_fec_1: fecgrp-1 {
+- fsl,pins = <
+- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
+- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
+- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
+- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
+- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
+- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
+- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
+- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
+- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+- >;
+- };
+- };
+-
+- uart1 {
+- pinctrl_uart1_1: uart1grp-1 {
+- fsl,pins = <
+- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+- >;
+- };
+- };
+-
+- usbotg1 {
+- pinctrl_usbotg1_1: usbotg1grp-1 {
+- fsl,pins = <
+- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg1_2: usbotg1grp-2 {
+- fsl,pins = <
+- MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg1_3: usbotg1grp-3 {
+- fsl,pins = <
+- MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg1_4: usbotg1grp-4 {
+- fsl,pins = <
+- MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg1_5: usbotg1grp-5 {
+- fsl,pins = <
+- MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
+- >;
+- };
+- };
+-
+- usbotg2 {
+- pinctrl_usbotg2_1: usbotg2grp-1 {
+- fsl,pins = <
+- MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg2_2: usbotg2grp-2 {
+- fsl,pins = <
+- MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg2_3: usbotg2grp-3 {
+- fsl,pins = <
+- MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
+- >;
+- };
+-
+- pinctrl_usbotg2_4: usbotg2grp-4 {
+- fsl,pins = <
+- MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
+- >;
+- };
+- };
+-
+- usdhc1 {
+- pinctrl_usdhc1_1: usdhc1grp-1 {
+- fsl,pins = <
+- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
+- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
+- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
+- fsl,pins = <
+- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
+- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
+- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
+- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
+- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
+- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
+- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
+- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
+- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
+- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
+- >;
+- };
+-
+- pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
+- fsl,pins = <
+- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
+- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
+- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
+- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
+- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
+- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
+- >;
+- };
+-
+-
+- };
+-
+- usdhc2 {
+- pinctrl_usdhc2_1: usdhc2grp-1 {
+- fsl,pins = <
+- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
+- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
+- fsl,pins = <
+- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
+- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+- >;
+- };
+-
+- pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
+- fsl,pins = <
+- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
+- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+- >;
+- };
+-
+- };
+-
+- usdhc3 {
+- pinctrl_usdhc3_1: usdhc3grp-1 {
+- fsl,pins = <
+- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
+- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
+- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+- >;
+- };
+-
+- pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
+- fsl,pins = <
+- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
+- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+- >;
+- };
+-
+- pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
+- fsl,pins = <
+- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
+- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+- >;
+- };
+- };
+ };
+
+ csi: csi@020e4000 {
++ compatible = "fsl,imx6s-csi";
+ reg = <0x020e4000 0x4000>;
+- interrupts = <0 7 0x04>;
++ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_DUMMY>,
++ <&clks IMX6SL_CLK_DUMMY>,
++ <&clks IMX6SL_CLK_DUMMY>;
++ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
++ status = "disabled";
+ };
+
+ spdc: spdc@020e8000 {
+ reg = <0x020e8000 0x4000>;
+- interrupts = <0 6 0x04>;
++ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+- interrupts = <0 2 0x04>;
++ interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_SDMA>,
+ <&clks IMX6SL_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
++ iram = <&ocram>;
+ /* imx6sl reuses imx6q sdma firmware */
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
+ };
+
+ pxp: pxp@020f0000 {
++ compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
+ reg = <0x020f0000 0x4000>;
+- interrupts = <0 98 0x04>;
++ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>;
++ clock-names = "pxp-axi", "disp-axi";
++ status = "disabled";
+ };
+
+ epdc: epdc@020f4000 {
++ compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc";
+ reg = <0x020f4000 0x4000>;
+- interrupts = <0 97 0x04>;
++ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>;
++ clock-names = "epdc_axi", "epdc_pix";
+ };
+
+ lcdif: lcdif@020f8000 {
++ compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
+ reg = <0x020f8000 0x4000>;
+- interrupts = <0 39 0x04>;
++ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
++ <&clks IMX6SL_CLK_LCDIF_AXI>,
++ <&clks IMX6SL_CLK_DUMMY>;
++ clock-names = "pix", "axi", "disp_axi";
++ status = "disabled";
+ };
+
++
+ dcp: dcp@020fc000 {
+ reg = <0x020fc000 0x4000>;
+- interrupts = <0 99 0x04>;
++ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+@@ -811,17 +764,18 @@
+ usbotg1: usb@02184000 {
+ compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+ reg = <0x02184000 0x200>;
+- interrupts = <0 43 0x04>;
++ interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc 0>;
++ fsl,anatop = <&anatop>;
+ status = "disabled";
+ };
+
+ usbotg2: usb@02184200 {
+ compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+ reg = <0x02184200 0x200>;
+- interrupts = <0 42 0x04>;
++ interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USBOH3>;
+ fsl,usbphy = <&usbphy2>;
+ fsl,usbmisc = <&usbmisc 1>;
+@@ -831,9 +785,12 @@
+ usbh: usb@02184400 {
+ compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+ reg = <0x02184400 0x200>;
+- interrupts = <0 40 0x04>;
++ interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USBOH3>;
+ fsl,usbmisc = <&usbmisc 2>;
++ phy_type = "hsic";
++ fsl,usbphy = <&usbphy_nop1>;
++ fsl,anatop = <&anatop>;
+ status = "disabled";
+ };
+
+@@ -842,12 +799,13 @@
+ compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x02184800 0x200>;
+ clocks = <&clks IMX6SL_CLK_USBOH3>;
++ vbus-wakeup-supply = <&reg_vbus_wakeup>;
+ };
+
+ fec: ethernet@02188000 {
+ compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
+ reg = <0x02188000 0x4000>;
+- interrupts = <0 114 0x04>;
++ interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_ENET_REF>,
+ <&clks IMX6SL_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb";
+@@ -857,7 +815,7 @@
+ usdhc1: usdhc@02190000 {
+ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+ reg = <0x02190000 0x4000>;
+- interrupts = <0 22 0x04>;
++ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USDHC1>,
+ <&clks IMX6SL_CLK_USDHC1>,
+ <&clks IMX6SL_CLK_USDHC1>;
+@@ -869,7 +827,7 @@
+ usdhc2: usdhc@02194000 {
+ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+ reg = <0x02194000 0x4000>;
+- interrupts = <0 23 0x04>;
++ interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USDHC2>,
+ <&clks IMX6SL_CLK_USDHC2>,
+ <&clks IMX6SL_CLK_USDHC2>;
+@@ -881,7 +839,7 @@
+ usdhc3: usdhc@02198000 {
+ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+ reg = <0x02198000 0x4000>;
+- interrupts = <0 24 0x04>;
++ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USDHC3>,
+ <&clks IMX6SL_CLK_USDHC3>,
+ <&clks IMX6SL_CLK_USDHC3>;
+@@ -893,7 +851,7 @@
+ usdhc4: usdhc@0219c000 {
+ compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+ reg = <0x0219c000 0x4000>;
+- interrupts = <0 25 0x04>;
++ interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_USDHC4>,
+ <&clks IMX6SL_CLK_USDHC4>,
+ <&clks IMX6SL_CLK_USDHC4>;
+@@ -907,7 +865,7 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+- interrupts = <0 36 0x04>;
++ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_I2C1>;
+ status = "disabled";
+ };
+@@ -917,7 +875,7 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+- interrupts = <0 37 0x04>;
++ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_I2C2>;
+ status = "disabled";
+ };
+@@ -927,7 +885,7 @@
+ #size-cells = <0>;
+ compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+- interrupts = <0 38 0x04>;
++ interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6SL_CLK_I2C3>;
+ status = "disabled";
+ };
+@@ -937,19 +895,28 @@
+ reg = <0x021b0000 0x4000>;
+ };
+
+- rngb: rngb@021b4000 {
++ rng: rng@021b4000 {
++ compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
+ reg = <0x021b4000 0x4000>;
+- interrupts = <0 5 0x04>;
++ interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SL_CLK_DUMMY>;
+ };
+
+ weim: weim@021b8000 {
+ reg = <0x021b8000 0x4000>;
+- interrupts = <0 14 0x04>;
++ interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+- ocotp: ocotp@021bc000 {
+- compatible = "fsl,imx6sl-ocotp";
++ ocotp: ocotp-ctrl@021bc000 {
++ compatible = "syscon";
+ reg = <0x021bc000 0x4000>;
++ clocks = <&clks IMX6SL_CLK_OCOTP>;
++ };
++
++ ocotp-fuse@021bc000 {
++ compatible = "fsl,imx6sl-ocotp", "fsl,imx6q-ocotp";
++ reg = <0x021bc000 0x4000>;
++ clocks = <&clks IMX6SL_CLK_OCOTP>;
+ };
+
+ audmux: audmux@021d8000 {
+@@ -957,6 +924,24 @@
+ reg = <0x021d8000 0x4000>;
+ status = "disabled";
+ };
++
++ gpu: gpu@02200000 {
++ compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu";
++ reg = <0x02200000 0x4000>, <0x02204000 0x4000>,
++ <0x80000000 0x0>;
++ reg-names = "iobase_2d", "iobase_vg",
++ "phys_baseaddr";
++ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "irq_2d", "irq_vg";
++ clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
++ <&clks IMX6SL_CLK_MMDC_ROOT>,
++ <&clks IMX6SL_CLK_GPU2D_OVG>;
++ clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
++ "gpu2d_clk";
++ resets = <&src 3>, <&src 3>;
++ reset-names = "gpu2d", "gpuvg";
++ power-domains = <&gpc 1>;
++ };
+ };
+ };
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-csi.dts linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-csi.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-csi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-csi.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,21 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sl-evk.dts"
++
++&csi {
++ status = "okay";
++};
++
++&i2c3 {
++ status = "okay";
++};
++
++&epdc {
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk.dts linux-3.14.72/arch/arm/boot/dts/imx6sl-evk.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk.dts 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/imx6sl-evk.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -8,21 +8,45 @@
+
+ /dts-v1/;
+
++#include <dt-bindings/input/input.h>
+ #include "imx6sl.dtsi"
+
+ / {
+ model = "Freescale i.MX6 SoloLite EVK Board";
+ compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
+
++ battery: max8903@0 {
++ compatible = "fsl,max8903-charger";
++ pinctrl-names = "default";
++ dok_input = <&gpio4 13 1>;
++ uok_input = <&gpio4 13 1>;
++ chg_input = <&gpio4 15 1>;
++ flt_input = <&gpio4 14 1>;
++ fsl,dcm_always_high;
++ fsl,dc_valid;
++ fsl,adc_disable;
++ status = "okay";
++ };
++
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_lcd_3v3: lcd-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "lcd-3v3";
++ gpio = <&gpio4 3 0>;
++ enable-active-high;
++ };
+
+- reg_usb_otg1_vbus: usb_otg1_vbus {
++ reg_usb_otg1_vbus: regulator@0 {
+ compatible = "regulator-fixed";
++ reg = <0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+@@ -30,22 +54,119 @@
+ enable-active-high;
+ };
+
+- reg_usb_otg2_vbus: usb_otg2_vbus {
++ reg_usb_otg2_vbus: regulator@1 {
+ compatible = "regulator-fixed";
++ reg = <1>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 2 0>;
+ enable-active-high;
+ };
++
++ reg_aud3v: regulator@2 {
++ compatible = "regulator-fixed";
++ reg = <2>;
++ regulator-name = "wm8962-supply-3v15";
++ regulator-min-microvolt = <3150000>;
++ regulator-max-microvolt = <3150000>;
++ regulator-boot-on;
++ };
++
++ reg_aud4v: regulator@3 {
++ compatible = "regulator-fixed";
++ reg = <3>;
++ regulator-name = "wm8962-supply-4v2";
++ regulator-min-microvolt = <4325000>;
++ regulator-max-microvolt = <4325000>;
++ regulator-boot-on;
++ };
++ };
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm1 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ sound {
++ compatible = "fsl,imx6q-sabresd-wm8962",
++ "fsl,imx-audio-wm8962";
++ model = "wm8962-audio";
++ cpu-dai = <&ssi2>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "Headphone Jack", "HPOUTL",
++ "Headphone Jack", "HPOUTR",
++ "Ext Spk", "SPKOUTL",
++ "Ext Spk", "SPKOUTR",
++ "AMIC", "MICBIAS",
++ "IN3R", "AMIC";
++ amic-mono;
++ mux-int-port = <2>;
++ mux-ext-port = <3>;
++ hp-det-gpios = <&gpio4 19 1>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif",
++ "fsl,imx6sl-evk-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sii902x_reset: sii902x-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio2 19 1>;
++ reset-delay-us = <100000>;
++ #reset-cells = <0>;
+ };
+ };
+
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux>;
++ status = "okay";
++};
++
++&clks {
++ assigned-clocks = <&clks IMX6SL_PLL4_BYPASS_SRC>,
++ <&clks IMX6SL_PLL4_BYPASS>,
++ <&clks IMX6SL_CLK_EXTERN_AUDIO_SEL>,
++ <&clks IMX6SL_CLK_EXTERN_AUDIO>,
++ <&clks IMX6SL_CLK_PLL4_POST_DIV>;
++ assigned-clock-parents = <&clks IMX6SL_CLK_OSC>,
++ <&clks IMX6SL_PLL4_BYPASS_SRC>,
++ <&clks IMX6SL_CLK_PLL4_AUDIO_DIV>;
++ assigned-clock-rates = <0>, <0>, <0>, <24000000>,
++ <24000000>;
++};
++
++&csi {
++ port {
++ csi_ep: endpoint {
++ remote-endpoint = <&ov5640_ep>;
++ };
++ };
++};
++
++&cpu0 {
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1c_reg>;
++};
++
+ &ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 11 0>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_ecspi1_1>;
++ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ flash: m25p80@0 {
+@@ -57,18 +178,287 @@
+ };
+ };
+
++&epdc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_epdc_0>;
++ V3P3-supply = <&V3P3_reg>;
++ VCOM-supply = <&VCOM_reg>;
++ DISPLAY-supply = <&DISPLAY_reg>;
++ status = "okay";
++};
++
+ &fec {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_fec_1>;
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&pinctrl_fec>;
++ pinctrl-1 = <&pinctrl_fec_sleep>;
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
++&gpc {
++ /* use ldo-bypass, u-boot will check it and configure */
++ fsl,ldo-bypass = <1>;
++ /* watchdog select of reset source */
++ fsl,wdog-reset = <1>;
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ regulator-always-on;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++ elan@10 {
++ compatible = "elan,elan-touch";
++ reg = <0x10>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <10 2>;
++ gpio_elan_cs = <&gpio2 9 0>;
++ gpio_elan_rst = <&gpio4 4 0>;
++ gpio_intr = <&gpio2 10 0>;
++ status = "okay";
++ };
++
++ mma8450@1c {
++ compatible = "fsl,mma8450";
++ reg = <0x1c>;
++ };
++
++ max17135@48 {
++ compatible = "maxim,max17135";
++ reg = <0x48>;
++ vneg_pwrup = <1>;
++ gvee_pwrup = <2>;
++ vpos_pwrup = <10>;
++ gvdd_pwrup = <12>;
++ gvdd_pwrdn = <1>;
++ vpos_pwrdn = <2>;
++ gvee_pwrdn = <8>;
++ vneg_pwrdn = <10>;
++ gpio_pmic_pwrgood = <&gpio2 13 0>;
++ gpio_pmic_vcom_ctrl = <&gpio2 3 0>;
++ gpio_pmic_wakeup = <&gpio2 14 0>;
++ gpio_pmic_v3p3 = <&gpio2 7 0>;
++ gpio_pmic_intr = <&gpio2 12 0>;
++
++ regulators {
++ DISPLAY_reg: DISPLAY {
++ regulator-name = "DISPLAY";
++ };
++
++ GVDD_reg: GVDD {
++ /* 20v */
++ regulator-name = "GVDD";
++ };
++
++ GVEE_reg: GVEE {
++ /* -22v */
++ regulator-name = "GVEE";
++ };
++
++ HVINN_reg: HVINN {
++ /* -22v */
++ regulator-name = "HVINN";
++ };
++
++ HVINP_reg: HVINP {
++ /* 20v */
++ regulator-name = "HVINP";
++ };
++
++ VCOM_reg: VCOM {
++ regulator-name = "VCOM";
++ /* 2's-compliment, -4325000 */
++ regulator-min-microvolt = <0xffbe0178>;
++ /* 2's-compliment, -500000 */
++ regulator-max-microvolt = <0xfff85ee0>;
++ };
++
++ VNEG_reg: VNEG {
++ /* -15v */
++ regulator-name = "VNEG";
++ };
++
++ VPOS_reg: VPOS {
++ /* 15v */
++ regulator-name = "VPOS";
++ };
++
++ V3P3_reg: V3P3 {
++ regulator-name = "V3P3";
++ };
++ };
++ };
++
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++
++ codec: wm8962@1a {
++ compatible = "wlf,wm8962";
++ reg = <0x1a>;
++ clocks = <&clks IMX6SL_CLK_EXTERN_AUDIO>;
++ DCVDD-supply = <&vgen3_reg>;
++ DBVDD-supply = <&reg_aud3v>;
++ AVDD-supply = <&vgen3_reg>;
++ CPVDD-supply = <&vgen3_reg>;
++ MICVDD-supply = <&reg_aud3v>;
++ PLLVDD-supply = <&vgen3_reg>;
++ SPKVDD1-supply = <&reg_aud4v>;
++ SPKVDD2-supply = <&reg_aud4v>;
++ amic-mono;
++ };
++
++ sii902x@39 {
++ compatible = "SiI,sii902x";
++ interrupt-parent = <&gpio2>;
++ interrupts = <10 2>;
++ mode_str ="1280x720M@60";
++ bits-per-pixel = <16>;
++ resets = <&sii902x_reset>;
++ reg = <0x39>;
++ };
++
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "disabled";
++
++ ov5640: ov5640@3c {
++ compatible = "ovti,ov5640";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_csi_0>;
++ clocks = <&clks IMX6SL_CLK_CSI>;
++ clock-names = "csi_mclk";
++ AVDD-supply = <&vgen6_reg>; /* 2.8v */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio1 25 1>;
++ rst-gpios = <&gpio1 26 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ port {
++ ov5640_ep: endpoint {
++ remote-endpoint = <&csi_ep>;
++ };
++ };
++ };
++};
++
+ &iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+- hog {
++ imx6sl-evk {
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
+@@ -78,21 +468,438 @@
+ MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
+ MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
++ MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000
++ MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000
++ MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000
++ MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0
++ MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000
++ MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000
++ MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0
++ MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0
++ >;
++ };
++
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
++ MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
++ MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
++ MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
++ MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0
++ >;
++ };
++
++
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
++ MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
++ MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
++ >;
++ };
++
++ pinctrl_epdc_0: epdcgrp-0 {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000
++ MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000
++ MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000
++ MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000
++ MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000
++ MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000
++ MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000
++ MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000
++ MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000
++ MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000
++ MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000
++ MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000
++ MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000
++ MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000
++ MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000
++ MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000
++ MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000
++ MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000
++ MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000
++ MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000
++ MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000
++ MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000
++ MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000
++ MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000
++ MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000
++ MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000
++ MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000
++ MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000
++ >;
++ };
++
++ pinctrl_fec: fecgrp {
++ fsl,pins = <
++ MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
++ MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
++ MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
++ MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
++ MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
++ MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
++ MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
++ MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
++ MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
++ >;
++ };
++
++ pinctrl_fec_sleep: fecgrp-sleep {
++ fsl,pins = <
++ MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
++ MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x3080
++ MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
++ MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
++ MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
++ MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
++ MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
++ MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
++ MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
++ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
++ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1
++ MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_kpp: kppgrp {
++ fsl,pins = <
++ MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
++ MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
++ MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
++ MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
++ MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
++ MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
++ >;
++ };
++
++ pinctrl_lcdif_dat: lcdifdatgrp {
++ fsl,pins = <
++ MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0
++ MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0
++ MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0
++ MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0
++ MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0
++ MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0
++ MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0
++ MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0
++ MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0
++ MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0
++ MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0
++ MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0
++ MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0
++ MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0
++ MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0
++ MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0
++ MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0
++ MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0
++ MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0
++ MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0
++ MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0
++ MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0
++ MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0
++ MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0
++ >;
++ };
++
++ pinctrl_lcdif_ctrl: lcdifctrlgrp {
++ fsl,pins = <
++ MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0
++ MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0
++ MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0
++ MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0
++ >;
++ };
++
++ pinctrl_pwm1: pwm1grp {
++ fsl,pins = <
++ MX6SL_PAD_PWM1__PWM1_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_pwm1_sleep: pwm1grp-sleep {
++ fsl,pins = <
++ MX6SL_PAD_PWM1__GPIO3_IO23 0x3080
++ >;
++ };
++
++ pinctrl_spdif: spdifgrp {
++ fsl,pins = <
++ MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
++ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart4_1: uart4grp-1 {
++ fsl,pins = <
++ MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1
++ MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1
++ MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1
++ MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart4dte_1: uart4dtegrp-1 {
++ fsl,pins = <
++ MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1
++ MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1
++ MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1
++ MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg1: usbotg1grp {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc1: usdhc1grp {
++ fsl,pins = <
++ MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
++ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
++ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
++ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
++ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
++ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
++ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
++ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
++ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
++ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
++ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
++ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
++ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
++ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
++ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
++ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
++ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
++ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
++ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
++ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
++ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
++ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
++ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
++ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
++ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
++ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
++ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
++ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
++ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
++ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
++ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
++ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
++ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
++ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
++ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
++ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
++ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
++ fsl,pins = <
++ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
++ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
++ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
++ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
++ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
++ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
++ >;
++ };
++
++ pinctrl_csi_0: csigrp-0 {
++ fsl,pins = <
++ MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0
++ MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0
++ MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0
++ MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0
++ MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0
++ MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0
++ MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0
++ MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0
++ MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0
++ MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0
++ MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0
++ MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0
++ MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0
++ MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0
++ MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000
++ MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000
+ >;
+ };
+ };
+ };
+
++&pxp {
++ status = "okay";
++};
++
++&kpp {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_kpp>;
++ linux,keymap = <
++ MATRIX_KEY(0x0, 0x0, KEY_UP) /* ROW0, COL0 */
++ MATRIX_KEY(0x0, 0x1, KEY_DOWN) /* ROW0, COL1 */
++ MATRIX_KEY(0x0, 0x2, KEY_ENTER) /* ROW0, COL2 */
++ MATRIX_KEY(0x1, 0x0, KEY_HOME) /* ROW1, COL0 */
++ MATRIX_KEY(0x1, 0x1, KEY_RIGHT) /* ROW1, COL1 */
++ MATRIX_KEY(0x1, 0x2, KEY_LEFT) /* ROW1, COL2 */
++ MATRIX_KEY(0x2, 0x0, KEY_VOLUMEDOWN) /* ROW2, COL0 */
++ MATRIX_KEY(0x2, 0x1, KEY_VOLUMEUP) /* ROW2, COL1 */
++ >;
++ status = "okay";
++};
++
++&lcdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_lcdif_dat
++ &pinctrl_lcdif_ctrl>;
++ lcd-supply = <&reg_lcd_3v3>;
++ display = <&display>;
++ status = "okay";
++
++ display: display {
++ bits-per-pixel = <16>;
++ bus-width = <24>;
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: timing0 {
++ clock-frequency = <33500000>;
++ hactive = <800>;
++ vactive = <480>;
++ hback-porch = <89>;
++ hfront-porch = <164>;
++ vback-porch = <23>;
++ vfront-porch = <10>;
++ hsync-len = <10>;
++ vsync-len = <10>;
++ hsync-active = <0>;
++ vsync-active = <0>;
++ de-active = <1>;
++ pixelclk-active = <0>;
++ };
++ };
++ };
++};
++
++&pwm1 {
++ pinctrl-names = "default", "sleep";
++ pinctrl-0 = <&pinctrl_pwm1>;
++ pinctrl-1 = <&pinctrl_pwm1_sleep>;
++ status = "okay";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif>;
++ assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>,
++ <&clks IMX6SL_CLK_SPDIF0_PODF>;
++ assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>;
++ assigned-clock-rates = <0>, <227368421>;
++ status = "okay";
++};
++
++&ssi2 {
++ fsl,mode = "i2s-slave";
++ assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>,
++ <&clks IMX6SL_CLK_SSI2>;
++ assigned-clock-rates = <0>, <24000000>;
++ status = "okay";
++};
++
+ &uart1 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart1_1>;
++ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+ };
+
+ &usbotg1 {
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_usbotg1_1>;
++ pinctrl-0 = <&pinctrl_usbotg1>;
+ disable-over-current;
+ status = "okay";
+ };
+@@ -106,30 +913,36 @@
+
+ &usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+- pinctrl-0 = <&pinctrl_usdhc1_1>;
+- pinctrl-1 = <&pinctrl_usdhc1_1_100mhz>;
+- pinctrl-2 = <&pinctrl_usdhc1_1_200mhz>;
++ pinctrl-0 = <&pinctrl_usdhc1>;
++ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ cd-gpios = <&gpio4 7 0>;
+ wp-gpios = <&gpio4 6 0>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
+ status = "okay";
+ };
+
+ &usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+- pinctrl-0 = <&pinctrl_usdhc2_1>;
+- pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>;
+- pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>;
++ pinctrl-0 = <&pinctrl_usdhc2>;
++ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ cd-gpios = <&gpio5 0 0>;
+ wp-gpios = <&gpio4 29 0>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
+ status = "okay";
+ };
+
+ &usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+- pinctrl-0 = <&pinctrl_usdhc3_1>;
+- pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
+- pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ cd-gpios = <&gpio3 22 0>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-ldo.dts linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-ldo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-ldo.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,20 @@
++
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sl-evk.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++};
++
++&gpc {
++ /* use ldo-enable, u-boot will check it and configure */
++ fsl,ldo-bypass = <0>;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-pf200.dts linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-pf200.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-pf200.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-pf200.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,13 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sl-evk-ldo.dts"
++
++&pmic {
++ compatible = "fsl,pfuze200";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-uart.dts linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-uart.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sl-evk-uart.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sl-evk-uart.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,23 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sl-evk.dts"
++
++&uart4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart4_1>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++ /* for DTE mode, add below change */
++ /* fsl,dte-mode; */
++ /* pinctrl-0 = <&pinctrl_uart4dte_1>; */
++};
++
++&usdhc1 {
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,1251 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/dts-v1/;
++
++#include "imx6sx.dtsi"
++
++/ {
++ model = "Freescale i.MX6 SoloX 17x17 ARM2 Board";
++ compatible = "fsl,imx6sx-17x17-arm2", "fsl,imx6sx";
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ };
++
++ clocks {
++ codec_osc: codec_osc {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <12000000>;
++ };
++ };
++
++ max7322_reset: max7322-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <1>;
++ #reset-cells = <0>;
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_sdb_vmmc: sdb_vmmc{
++ compatible = "regulator-fixed";
++ regulator-name = "SD2_SPWR";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio2 11 GPIO_ACTIVE_LOW>;
++ };
++
++ reg_usb_otg1_vbus: usb_otg1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 9 0>;
++ enable-active-high;
++ };
++
++ reg_usb_otg2_vbus: usb_otg2_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg2_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 12 0>;
++ enable-active-high;
++ };
++
++ reg_vref_3v3: regulator@0 {
++ compatible = "regulator-fixed";
++ regulator-name = "vref-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++ };
++
++ memory {
++ reg = <0x80000000 0x40000000>;
++ };
++
++ sound {
++ compatible = "fsl,imx6sx-arm2-sgtl5000",
++ "fsl,imx-audio-sgtl5000";
++ model = "imx6sx-arm2-sgtl5000";
++ cpu-dai = <&ssi1>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "LINE_IN", "Line In Jack",
++ "Headphone Jack", "HP_OUT";
++ mux-int-port = <1>;
++ mux-ext-port = <4>;
++ };
++};
++
++&adc1 {
++ vref-supply = <&reg_vref_3v3>;
++ status = "okay";
++};
++
++&adc2 {
++ vref-supply = <&reg_vref_3v3>;
++ status = "okay";
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux_2>;
++ status = "okay";
++};
++
++&cpu0 {
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1c_reg>;
++};
++
++&ecspi4 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio7 4 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
++ status = "disabled"; /* pin conflict with USDHC3 */
++
++ flash: m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p32";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++&fec1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet1_1>;
++ phy-mode = "rgmii";
++ phy-handle = <&ethphy1>;
++ pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
++ fsl,magic-packet;
++ status = "okay";
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethphy0: ethernet-phy@0 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ };
++ };
++};
++
++&fec2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet2_1>;
++ phy-mode = "rgmii";
++ phy-handle = <&ethphy0>;
++ pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
++ fsl,magic-packet;
++ status = "okay";
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1_1>;
++ trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
++ trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&flexcan2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan2_1>;
++ trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
++ trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0x2>;
++ fsl,cpu_pupscr_sw = <0x1>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++ fsl,wdog-reset = <1>; /* watchdog select of reset source */
++ fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1_1>;
++ status = "okay";
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_1>;
++ status = "okay";
++
++ max7322_1: gpio@68 {
++ compatible = "maxim,max7322";
++ reg = <0x68>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7322_reset>;
++ };
++
++ max7322_2: gpio@69 {
++ compatible = "maxim,max7322";
++ reg = <0x69>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7322_reset>;
++ };
++
++ codec: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&codec_osc>;
++ VDDA-supply = <&vgen4_reg>;
++ VDDIO-supply = <&reg_3p3v>;
++ };
++};
++
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_1>;
++ status = "okay";
++};
++
++&i2c4 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c4_1>;
++ status = "okay";
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog_1>;
++
++ hog {
++ pinctrl_hog_1: hoggrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059
++ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059
++ MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000
++ /* CAN1_2_EN */
++ MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
++ /* CAN1_2_STBY_B */
++ MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
++ /* CAN1_ERR_B */
++ MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059
++ /* CAN2_ERR_B */
++ MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059
++ /* SD2_PWROFF */
++ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
++ /* WDOG_B reset */
++ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
++ >;
++ };
++ };
++};
++
++&lcdif1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_lcdif_dat_0
++ &pinctrl_lcdif_ctrl_0>;
++ display = <&display>;
++ status = "okay";
++
++ display: display {
++ bits-per-pixel = <16>;
++ bus-width = <24>;
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: timing0 {
++ clock-frequency = <33500000>;
++ hactive = <800>;
++ vactive = <480>;
++ hback-porch = <89>;
++ hfront-porch = <164>;
++ vback-porch = <23>;
++ vfront-porch = <10>;
++ hsync-len = <10>;
++ vsync-len = <10>;
++ hsync-active = <0>;
++ vsync-active = <0>;
++ de-active = <1>;
++ pixelclk-active = <0>;
++ };
++ };
++ };
++};
++
++&mlb {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mlb_1>;
++ status = "disabled";/* pin conflict with usdhc2*/
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3_0>;
++ status = "okay";
++};
++
++&pxp {
++ status = "okay";
++};
++
++&qspi2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_qspi2_1>;
++ status = "okay";
++ ddrsmp=<2>;
++
++ flash0: n25q256a@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ reg = <0>;
++ };
++
++ flash1: n25q256a@1 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ reg = <1>;
++ };
++};
++
++&sai2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_sai2_1>;
++ status = "disabled";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif_1>;
++ status = "disabled";
++};
++
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1_1>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2_1>;
++ status = "okay";
++};
++
++&usbh {
++ pinctrl-names = "idle", "active";
++ pinctrl-0 = <&pinctrl_usbh_1>;
++ pinctrl-1 = <&pinctrl_usbh_2>;
++ osc-clkgate-delay = <0x3>;
++ pad-supply = <&vgen1_reg>;
++ status = "okay";
++};
++
++&usbotg1 {
++ vbus-supply = <&reg_usb_otg1_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg1_1>;
++ disable-over-current;
++ status = "okay";
++};
++
++&usbotg2 {
++ /*
++ * Pin conflict with others, need to switch R580 & R579
++ * to B and disable pwm3 to enable it.
++ */
++ vbus-supply = <&reg_usb_otg2_vbus>;
++ disable-over-current;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg2_1>;
++ status = "disabled";
++};
++
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2_1>;
++ non-removable;
++ /* need hw rework to enable signal voltage switch */
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3_1>;
++ pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
++ bus-width = <8>;
++ cd-gpios = <&gpio2 10 0>;
++ wp-gpios = <&gpio2 15 0>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ vmmc-supply = <&reg_sdb_vmmc>;
++ status = "okay";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4_1>;
++ bus-width = <8>;
++ non-removable;
++ /* need hw rework to enable signal voltage switch */
++ no-1-8-v;
++ status = "okay";
++};
++
++&iomuxc {
++ audmux {
++ pinctrl_audmux_1: audmuxgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0
++ MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0
++ MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0
++ MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0
++ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
++ >;
++ };
++
++ pinctrl_audmux_2: audmuxgrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0
++ MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0
++ MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
++ MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0
++ >;
++ };
++ };
++
++ ecspi4 {
++ pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000
++ >;
++ };
++
++ pinctrl_ecspi4_1: ecspi4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
++ MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1
++ MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1
++ >;
++ };
++ };
++
++ canfd1 {
++ pinctrl_canfd1_1: canfd1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0
++ >;
++ };
++ };
++
++ canfd2 {
++ pinctrl_canfd2_1: canfd2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0
++ >;
++ };
++ };
++
++ csi {
++ pinctrl_csi_0: csigrp-0 {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
++ MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
++ MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
++ MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
++ MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
++ MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
++ MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
++ MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
++ MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
++ MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
++ MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
++ MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
++ MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
++ MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
++ MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
++ >;
++ };
++
++ pinctrl_csi_1: csigrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0
++ MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0
++ MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0
++ MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0
++ MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0
++ MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0
++ MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0
++ MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0
++ MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0
++ MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0
++ MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0
++ MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0
++
++ MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000
++ MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000
++ >;
++ };
++ };
++
++ enet1 {
++ pinctrl_enet1_1: enet1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
++ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
++ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
++ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
++ >;
++ };
++
++ pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
++ >;
++ };
++ };
++
++ enet2 {
++ pinctrl_enet2_1: enet2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
++ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
++ >;
++ };
++ };
++
++ esai {
++ pinctrl_esai_1: esaigrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
++ MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
++ MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
++ MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
++ MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
++ MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
++ MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
++ MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
++ >;
++ };
++ };
++
++ flexcan1 {
++ pinctrl_flexcan1_1: flexcan1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
++ >;
++ };
++ };
++
++ flexcan2 {
++ pinctrl_flexcan2_1: flexcan2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
++ >;
++ };
++ };
++
++ gpmi-nand {
++ pinctrl_gpmi_nand_1: gpmi-nand-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
++ MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
++ MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
++ MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
++ MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
++ MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
++ MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
++ MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
++ MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
++ MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
++ MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
++ MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
++ MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
++ MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
++ MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
++ MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
++ >;
++ };
++ };
++
++ i2c1 {
++ pinctrl_i2c1_1: i2c1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c1_2: i2c1grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1
++ MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c2 {
++ pinctrl_i2c2_1: i2c2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c3 {
++ pinctrl_i2c3_1: i2c3grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3_2: i2c3grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c4 {
++ pinctrl_i2c4_1: i2c4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
++ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
++ >;
++ };
++ pinctrl_i2c4_2: i2c4grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1
++ MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ lcdif1 {
++ pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
++ >;
++ };
++
++ pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
++ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
++ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
++ >;
++ };
++ };
++
++ mlb {
++ pinctrl_mlb_1: mlbgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31
++ MX6SX_PAD_SD2_CLK__MLB_SIG 0x31
++ MX6SX_PAD_SD2_CMD__MLB_CLK 0x31
++ >;
++ };
++ };
++
++ pwm3 {
++ pinctrl_pwm3_0: pwm3grp-0 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_pwm3_1: pwm3grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
++ >;
++ };
++ };
++
++ pwm4 {
++ pinctrl_pwm4_0: pwm4grp-0 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
++ >;
++ };
++ };
++
++ qspi2 {
++ pinctrl_qspi2_1: qspi2grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1
++ MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1
++ MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1
++ MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1
++ MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1
++ MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1
++ MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1
++ MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1
++ MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1
++ MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1
++ MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1
++ MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1
++ >;
++ };
++ };
++
++ sai1 {
++ pinctrl_sai1_1: sai1grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030
++ MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030
++ MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030
++ MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030
++ MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030
++ MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030
++ >;
++ };
++
++ pinctrl_sai1_2: sai1grp_2 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0
++ MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0
++ MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0
++ MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0
++ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
++ >;
++ };
++ };
++
++ sai2 {
++ pinctrl_sai2_1: sai2grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030
++ MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030
++ MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030
++ MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030
++ >;
++ };
++ };
++
++
++ spdif {
++ pinctrl_spdif_1: spdifgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0
++ MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
++ >;
++ };
++
++ pinctrl_spdif_2: spdifgrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
++ >;
++ };
++ };
++
++ uart1 {
++ pinctrl_uart1_1: uart1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1_2: uart1grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
++ MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
++ >;
++ };
++ };
++
++ uart2 {
++ pinctrl_uart2_1: uart2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2_2: uart2grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
++ MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
++ >;
++ };
++ };
++
++ uart5 {
++ pinctrl_uart5_1: uart5grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5dte_1: uart5dtegrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
++ >;
++ };
++ };
++
++ usbh {
++ pinctrl_usbh_1: usbhgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030
++ MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
++ >;
++ };
++
++ pinctrl_usbh_2: usbhgrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030
++ >;
++ };
++ };
++
++ usbotg1 {
++ pinctrl_usbotg1_1: usbotg1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_2: usbotg1grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_3: usbotg1grp-3 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++ };
++
++ usbotg2 {
++ pinctrl_usbotg2_1: usbotg2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg2_2: usbotg2grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg2_3: usbotg2grp-3 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
++ >;
++ };
++ };
++
++ usdhc1 {
++ pinctrl_usdhc1_1: usdhc1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059
++ MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059
++ MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
++ MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
++ MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
++ MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
++ >;
++ };
++ };
++
++ usdhc2 {
++ pinctrl_usdhc2_1: usdhc2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
++ MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
++ MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
++ MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
++ MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
++ MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
++ >;
++ };
++ };
++
++ usdhc3 {
++ pinctrl_usdhc3_1: usdhc3grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
++ >;
++ };
++
++ };
++
++ usdhc4 {
++ pinctrl_usdhc4_1: usdhc4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc4_2: usdhc4grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ >;
++ };
++
++ };
++
++ weim {
++ pinctrl_weim_cs0_1: weim_cs0grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1
++ >;
++ };
++
++ pinctrl_weim_nor_1: weim_norgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1
++ MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1
++ MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060
++ /* data */
++ MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0
++ MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0
++ MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0
++ MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
++ MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0
++ /* address */
++ MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1
++ MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1
++ MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1
++ MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1
++ MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1
++ MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1
++ MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1
++ MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1
++ MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1
++ MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1
++ MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1
++ MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1
++ MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1
++ MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1
++ MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1
++ MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1
++ MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1
++ MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1
++ MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1
++ MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1
++ MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1
++ MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1
++ MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1
++ MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1
++ MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1
++ MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1
++ >;
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-ecspi.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-ecspi.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-ecspi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-ecspi.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,459 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "imx6sx.dtsi"
++
++/ {
++ model = "Freescale i.MX6 SoloX SDB Board";
++ compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
++
++ chosen {
++ stdout-path = &uart1;
++ };
++
++ memory {
++ reg = <0x80000000 0x40000000>;
++ };
++
++ backlight1 {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ fb-names = "mxs-lcdif0";
++ };
++
++ backlight2 {
++ compatible = "pwm-backlight";
++ pwms = <&pwm4 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ fb-names = "mxs-lcdif1";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ volume-up {
++ label = "Volume Up";
++ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_VOLUMEUP>;
++ };
++
++ volume-down {
++ label = "Volume Down";
++ gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_VOLUMEDOWN>;
++ };
++ };
++
++ hannstar_cabc {
++ compatible = "hannstar,cabc";
++
++ lvds0 {
++ gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_lcd_3v3: lcd-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "lcd-3v3";
++ gpio = <&gpio3 27 0>;
++ enable-active-high;
++ status = "disabled";
++ };
++
++ vcc_sd3: regulator@0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_vcc_sd3>;
++ regulator-name = "VCC_SD3";
++ regulator-min-microvolt = <3000000>;
++ regulator-max-microvolt = <3000000>;
++ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++ };
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ status = "okay"; /* pin conflict with qspi*/
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++&uart5 { /* for bluetooth */
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++ /* for DTE mode, add below change */
++ /* fsl,dte-mode;*/
++ /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
++};
++
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2>;
++ non-removable;
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++ bus-width = <8>;
++ cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ vmmc-supply = <&vcc_sd3>;
++ status = "disabled";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4>;
++ cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&ecspi4 {
++ fsl,spi-num-chipselects = <1>;
++ cs-gpios = <&gpio7 4 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>;
++ status = "okay"; /* pin conflict with USDHC3 */
++
++ flash: m25p80@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "st,m25p32";
++ spi-max-frequency = <20000000>;
++ reg = <0>;
++ };
++};
++
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++
++ imx6x-sdb {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
++ MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
++ >;
++ };
++
++ pinctrl_canfd1: canfd1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0
++ >;
++ };
++
++ pinctrl_canfd2: canfd2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0
++ >;
++ };
++
++ pinctrl_egalax_int: egalax_intgrp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
++ >;
++ };
++
++ pinctrl_enet1: enet1grp {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
++ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
++ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
++ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
++ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
++ >;
++ };
++
++ pinctrl_flexcan1: flexcan1grp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
++ >;
++ };
++
++ pinctrl_flexcan2: flexcan2grp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpio_keys: gpio_keysgrp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
++ MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c4: i2c4grp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
++ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_lcdif_dat: lcdifdatgrp {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
++ >;
++ };
++
++ pinctrl_lcdif_ctrl: lcdifctrlgrp {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
++ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
++ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
++ >;
++ };
++
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_pwm4: pwm4grp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_gpmi_nand_1: gpmi-nand-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
++ MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
++ MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
++ MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
++ MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
++ MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
++ MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
++ MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
++ MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
++ MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
++ MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
++ MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
++ MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
++ MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
++ MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
++ MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
++ >;
++ };
++
++ pinctrl_vcc_sd3: vccsd3grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5dte_1: uart5dtegrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
++ MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
++ MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
++ MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
++ MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
++ MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
++ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
++ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc4: usdhc4grp {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
++ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
++ >;
++ };
++
++ pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000
++ >;
++ };
++
++ pinctrl_ecspi4_1: ecspi4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
++ MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1
++ MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1
++ >;
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-gpmi-weim.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,429 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "imx6sx.dtsi"
++
++/ {
++ model = "Freescale i.MX6 SoloX SDB Board";
++ compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
++
++ chosen {
++ stdout-path = &uart1;
++ };
++
++ memory {
++ reg = <0x80000000 0x40000000>;
++ };
++
++ backlight1 {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ fb-names = "mxs-lcdif0";
++ };
++
++ backlight2 {
++ compatible = "pwm-backlight";
++ pwms = <&pwm4 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ fb-names = "mxs-lcdif1";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ volume-up {
++ label = "Volume Up";
++ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_VOLUMEUP>;
++ };
++
++ volume-down {
++ label = "Volume Down";
++ gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_VOLUMEDOWN>;
++ };
++ };
++
++ hannstar_cabc {
++ compatible = "hannstar,cabc";
++
++ lvds0 {
++ gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_lcd_3v3: lcd-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "lcd-3v3";
++ gpio = <&gpio3 27 0>;
++ enable-active-high;
++ status = "disabled";
++ };
++
++ vcc_sd3: regulator@0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_vcc_sd3>;
++ regulator-name = "VCC_SD3";
++ regulator-min-microvolt = <3000000>;
++ regulator-max-microvolt = <3000000>;
++ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++ };
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ status = "okay"; /* pin conflict with qspi*/
++ nand-on-flash-bbt;
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++&uart5 { /* for bluetooth */
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++ /* for DTE mode, add below change */
++ /* fsl,dte-mode;*/
++ /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
++};
++
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2>;
++ non-removable;
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++ bus-width = <8>;
++ cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ vmmc-supply = <&vcc_sd3>;
++ status = "okay";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4>;
++ cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++
++ imx6x-sdb {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
++ MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
++ >;
++ };
++
++ pinctrl_canfd1: canfd1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0
++ >;
++ };
++
++ pinctrl_canfd2: canfd2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0
++ >;
++ };
++
++ pinctrl_egalax_int: egalax_intgrp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
++ >;
++ };
++
++ pinctrl_enet1: enet1grp {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
++ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
++ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
++ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
++ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
++ >;
++ };
++
++ pinctrl_flexcan1: flexcan1grp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
++ >;
++ };
++
++ pinctrl_flexcan2: flexcan2grp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpio_keys: gpio_keysgrp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
++ MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c4: i2c4grp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
++ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_lcdif_dat: lcdifdatgrp {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
++ >;
++ };
++
++ pinctrl_lcdif_ctrl: lcdifctrlgrp {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
++ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
++ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
++ >;
++ };
++
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_pwm4: pwm4grp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_gpmi_nand_1: gpmi-nand-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
++ MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
++ MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
++ MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
++ MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
++ MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
++ MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
++ MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
++ MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
++ MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
++ MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
++ MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
++ MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
++ MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
++ MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
++ MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
++ >;
++ };
++
++ pinctrl_vcc_sd3: vccsd3grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5dte_1: uart5dtegrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
++ MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
++ MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
++ MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
++ MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
++ MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
++ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
++ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc4: usdhc4grp {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
++ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
++ >;
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-ldo.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-ldo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-ldo.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-17x17-arm2.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++};
++
++&gpc {
++ fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-mlb.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-mlb.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-mlb.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-mlb.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-17x17-arm2.dts"
++
++&mlb {
++ status = "okay";
++};
++
++&usdhc2 {
++ /* pin conflict with mlb */
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-sai.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-sai.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-sai.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-sai.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,65 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-17x17-arm2.dts"
++
++/ {
++ sound {
++ cpu-dai = <&sai2>;
++ };
++};
++
++&audmux {
++ /* Pin conflict with SAI */
++ status = "disabled";
++};
++
++&pinctrl_hog_1 {
++ /* Pin conflict with SAI */
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000
++ /* CAN1_2_EN */
++ MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
++ /* CAN1_2_STBY_B */
++ MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
++ /* CAN1_ERR_B */
++ MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059
++ /* CAN2_ERR_B */
++ MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059
++ >;
++};
++
++&reg_sdb_vmmc{
++ /* Pin conflict with SAI */
++ gpio = <0 0 0>;
++};
++
++&sai2 {
++ status = "okay";
++};
++
++&sdma {
++ gpr = <&gpr>;
++ /* SDMA event remap for SAI2 */
++ fsl,sdma-event-remap = <0 17 1>, <0 18 1>;
++};
++
++&usdhc2 {
++ /* Pin conflict with SAI */
++ status = "disabled";
++};
++
++&usdhc3 {
++ /* Pin conflict with SAI */
++ status = "disabled";
++};
++
++&usdhc4 {
++ /* Pin conflict with SAI */
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-spdif.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-spdif.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-spdif.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-spdif.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-17x17-arm2.dts"
++
++/ {
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif",
++ "fsl,imx-sabreauto-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-in;
++ spdif-out;
++ };
++};
++
++&audmux {
++ /* pin conflict with spdif */
++ status = "disabled";
++};
++
++&spdif {
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-ssi.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-ssi.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-17x17-arm2-ssi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-17x17-arm2-ssi.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,44 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-17x17-arm2.dts"
++
++&pinctrl_hog_1 {
++ /* Pin conflict with SSI */
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000
++ /* CAN1_2_EN */
++ MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
++ /* CAN1_2_STBY_B */
++ MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
++ /* CAN1_ERR_B */
++ MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059
++ /* CAN2_ERR_B */
++ MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059
++ >;
++};
++
++&reg_sdb_vmmc{
++ /* Pin conflict with SSI */
++ gpio = <0 0 0>;
++};
++
++&usdhc2 {
++ /* Pin conflict with SSI */
++ status = "disabled";
++};
++
++&usdhc3 {
++ /* Pin conflict with SSI */
++ status = "disabled";
++};
++
++&usdhc4 {
++ /* Pin conflict with SSI */
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-csi.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-19x19-arm2.dts"
++
++&esai {
++ /* pin conflict with sai */
++ status = "disabled";
++};
++
++&sai1 {
++ status = "disabled";
++};
++
++&i2c2 {
++ ov5640: ov5640@3c {
++ status = "okay";
++ };
++};
++
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,1260 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/dts-v1/;
++
++#include "imx6sx.dtsi"
++
++/ {
++ model = "Freescale i.MX6 SoloX 19x19 ARM2 Board";
++ compatible = "fsl,imx6sx-19x19-arm2", "fsl,imx6sx";
++
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ };
++
++ hannstar_cabc {
++ compatible = "hannstar,cabc";
++
++ lvds0 {
++ gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ clocks {
++ codec_osc: codec_osc {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <12000000>;
++ };
++ };
++
++ max7322_reset: max7322-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <1>;
++ #reset-cells = <0>;
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_3p3v: 3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_usb_otg1_vbus: usb_otg1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 9 0>;
++ enable-active-high;
++ };
++ };
++
++ memory {
++ reg = <0x80000000 0x40000000>;
++ };
++
++ sound-cs42888 {
++ compatible = "fsl,imx6-sabreauto-cs42888",
++ "fsl,imx-audio-cs42888";
++ model = "imx-cs42888";
++ esai-controller = <&esai>;
++ asrc-controller = <&asrc>;
++ audio-codec = <&cs42888>;
++ };
++};
++
++&esai {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_esai_1>;
++ status = "okay";
++};
++
++&csi1 {
++ status = "okay";
++
++ port {
++ csi1_ep: endpoint {
++ remote-endpoint = <&ov5640_ep>;
++ };
++ };
++};
++
++&csi2 {
++ status = "okay";
++ port {
++ csi2_ep: endpoint {
++ remote-endpoint = <&vadc_ep>;
++ };
++ };
++};
++
++&cpu0 {
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1c_reg>;
++};
++
++&fec1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet1_1>;
++ phy-mode = "rgmii";
++ phy-handle = <&ethphy1>;
++ pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>;
++ fsl,magic-packet;
++ status = "okay";
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethphy0: ethernet-phy@0 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ };
++ };
++};
++
++&fec2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet2_1>;
++ phy-mode = "rgmii";
++ phy-handle = <&ethphy0>;
++ pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>;
++ fsl,magic-packet;
++ status = "okay";
++};
++
++&gpc {
++ fsl,cpu_pupscr_sw2iso = <0x2>;
++ fsl,cpu_pupscr_sw = <0x1>;
++ fsl,cpu_pdnscr_iso2sw = <0x1>;
++ fsl,cpu_pdnscr_iso = <0x1>;
++ fsl,wdog-reset = <1>; /* watchdog select of reset source */
++ fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1_1>;
++ status = "okay";
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_1>;
++ status = "okay";
++
++ max7322_1: gpio@68 {
++ compatible = "maxim,max7322";
++ reg = <0x68>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7322_reset>;
++ };
++
++ max7322_2: gpio@69 {
++ compatible = "maxim,max7322";
++ reg = <0x69>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7322_reset>;
++ };
++
++ ov5640: ov5640@3c {
++ compatible = "ovti,ov5640";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_csi_1>;
++ clocks = <&clks IMX6SX_CLK_CSI>;
++ clock-names = "csi_mclk";
++ AVDD-supply = <&vgen3_reg>; /* 2.8v */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio3 26 1>;
++ rst-gpios = <&gpio3 25 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ status = "disabled";
++ port {
++ ov5640_ep: endpoint {
++ remote-endpoint = <&csi1_ep>;
++ };
++ };
++ };
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_1>;
++ status = "okay";
++};
++
++&i2c4 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c4_2>;
++ status = "okay";
++
++ sgtl5000: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&codec_osc>;
++ VDDA-supply = <&vgen4_reg>;
++ VDDIO-supply = <&reg_3p3v>;
++ };
++
++ cs42888: cs42888@048 {
++ compatible = "cirrus,cs42888";
++ reg = <0x048>;
++ clocks = <&clks IMX6SX_CLK_ESAI_EXTAL>;
++ clock-names = "mclk";
++ VA-supply = <&reg_3p3v>;
++ VD-supply = <&reg_3p3v>;
++ VLS-supply = <&reg_3p3v>;
++ VLC-supply = <&reg_3p3v>;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog_1>;
++
++ hog {
++ pinctrl_hog_1: hoggrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x1b0b0
++ MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x1b0b0
++ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
++ >;
++ };
++ };
++};
++
++&lcdif1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_lcdif_dat_0
++ &pinctrl_lcdif_ctrl_0>;
++ display = <&display0>;
++ status = "disabled";
++
++ display0: display {
++ bits-per-pixel = <16>;
++ bus-width = <24>;
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: timing0 {
++ clock-frequency = <33500000>;
++ hactive = <800>;
++ vactive = <480>;
++ hback-porch = <89>;
++ hfront-porch = <164>;
++ vback-porch = <23>;
++ vfront-porch = <10>;
++ hsync-len = <10>;
++ vsync-len = <10>;
++ hsync-active = <0>;
++ vsync-active = <0>;
++ de-active = <1>;
++ pixelclk-active = <0>;
++ };
++ };
++ };
++};
++
++&lcdif2 {
++ display = <&display1>;
++ disp-dev = "ldb";
++ status = "okay";
++
++ display1: display {
++ bits-per-pixel = <16>;
++ bus-width = <18>;
++ };
++};
++
++&ldb {
++ status = "okay";
++
++ lvds-channel@0 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ crtc = "lcdif2";
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing1>;
++ timing1: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-lcdif1";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds";
++ status = "okay";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3_0>;
++ status = "okay";
++};
++
++&pxp {
++ status = "okay";
++};
++
++&sai1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_sai1_1>;
++ status = "disabled";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1_1>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2_1>;
++ status = "okay";
++};
++
++&qspi2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_qspi2_1>;
++ status = "okay";
++ ddrsmp=<2>;
++
++ flash0: n25q256a@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ reg = <0>;
++ };
++
++ flash1: n25q256a@1 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ reg = <1>;
++ };
++};
++
++&usbh {
++ pinctrl-names = "idle", "active";
++ pinctrl-0 = <&pinctrl_usbh_1>;
++ pinctrl-1 = <&pinctrl_usbh_2>;
++ osc-clkgate-delay = <0x3>;
++ pad-supply = <&vgen1_reg>;
++ status = "okay";
++};
++
++&usbotg1 {
++ vbus-supply = <&reg_usb_otg1_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg1_1>;
++ disable-over-current;
++ status = "okay";
++};
++
++&usdhc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc1_1>;
++ bus-width = <4>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ no-1-8-v;
++ status = "okay";
++};
++
++&weim {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
++ #address-cells = <2>;
++ #size-cells = <1>;
++ ranges = <0 0 0x50000000 0x08000000>;
++ status = "disabled"; /* pin conflict with qspi, nand and lcd1 */
++
++ nor@0,0 {
++ compatible = "cfi-flash";
++ reg = <0 0 0x02000000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ bank-width = <2>;
++ fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000
++ 0x0000c000 0x1404a38e 0x00000000>;
++ };
++};
++
++&vadc {
++ vadc_in = <0>;
++ csi_id = <1>;
++ status = "okay";
++ port {
++ vadc_ep: endpoint {
++ remote-endpoint = <&csi2_ep>;
++ };
++ };
++};
++
++&iomuxc {
++ audmux {
++ pinctrl_audmux_1: audmuxgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0
++ MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0
++ MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0
++ MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0
++ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
++ >;
++ };
++
++ pinctrl_audmux_2: audmuxgrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0
++ MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0
++ MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0
++ MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0
++ >;
++ };
++ };
++
++ ecspi4 {
++ pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000
++ >;
++ };
++
++ pinctrl_ecspi4_1: ecspi4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1
++ MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1
++ MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1
++ >;
++ };
++ };
++
++ canfd1 {
++ pinctrl_canfd1_1: canfd1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0
++ >;
++ };
++ };
++
++ canfd2 {
++ pinctrl_canfd2_1: canfd2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0
++ >;
++ };
++ };
++
++ csi {
++ pinctrl_csi_0: csigrp-0 {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
++ MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
++ MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
++ MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
++ MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
++ MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
++ MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
++ MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
++ MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
++ MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
++ MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
++ MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
++ MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
++ MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
++ MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
++ >;
++ };
++
++ pinctrl_csi_1: csigrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0
++ MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0
++ MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0
++ MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0
++ MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0
++ MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0
++ MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0
++ MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0
++ MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0
++ MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0
++ MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0
++ MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0
++
++ MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000
++ MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000
++ >;
++ };
++ };
++
++ enet1 {
++ pinctrl_enet1_1: enet1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
++ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
++ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
++ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
++ >;
++ };
++
++ pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
++ >;
++ };
++ };
++
++ enet2 {
++ pinctrl_enet2_1: enet2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
++ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
++ >;
++ };
++ };
++
++ esai {
++ pinctrl_esai_1: esaigrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
++ MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
++ MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
++ MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
++ MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
++ MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
++ MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
++ MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
++ >;
++ };
++ };
++
++ flexcan1 {
++ pinctrl_flexcan1_1: flexcan1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
++ >;
++ };
++ };
++
++ flexcan2 {
++ pinctrl_flexcan2_1: flexcan2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
++ >;
++ };
++ };
++
++ gpmi-nand {
++ pinctrl_gpmi_nand_1: gpmi-nand-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
++ MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
++ MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
++ MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
++ MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
++ MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
++ MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
++ MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
++ MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
++ MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
++ MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
++ MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
++ MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
++ MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
++ MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
++ MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
++ >;
++ };
++ };
++
++ i2c1 {
++ pinctrl_i2c1_1: i2c1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c1_2: i2c1grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1
++ MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c2 {
++ pinctrl_i2c2_1: i2c2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c3 {
++ pinctrl_i2c3_1: i2c3grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3_2: i2c3grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ i2c4 {
++ pinctrl_i2c4_1: i2c4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
++ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
++ >;
++ };
++ pinctrl_i2c4_2: i2c4grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1
++ MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1
++ >;
++ };
++ };
++
++ lcdif1 {
++ pinctrl_lcdif_dat_0: lcdifdatgrp-0 {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
++ >;
++ };
++
++ pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
++ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
++ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
++ >;
++ };
++ };
++
++ mlb {
++ pinctrl_mlb_1: mlbgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31
++ MX6SX_PAD_SD2_CLK__MLB_SIG 0x31
++ MX6SX_PAD_SD2_CMD__MLB_CLK 0x31
++ >;
++ };
++ };
++
++ mqs {
++ pinctrl_mqs_1: mqsgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000
++ MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000
++ >;
++ };
++ };
++
++ pwm3 {
++ pinctrl_pwm3_0: pwm3grp-0 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_pwm3_1: pwm3grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
++ >;
++ };
++ };
++
++ pwm4 {
++ pinctrl_pwm4_0: pwm4grp-0 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
++ >;
++ };
++ };
++
++ qspi2 {
++ pinctrl_qspi2_1: qspi2grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1
++ MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1
++ MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1
++ MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1
++ MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1
++ MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1
++ MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1
++ MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1
++ MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1
++ MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1
++ MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1
++ MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1
++ >;
++ };
++ };
++
++ sai1 {
++ pinctrl_sai1_1: sai1grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030
++ MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030
++ MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030
++ MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030
++ MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030
++ MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030
++ >;
++ };
++
++ pinctrl_sai1_2: sai1grp_2 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0
++ MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0
++ MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0
++ MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0
++ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0
++ >;
++ };
++ };
++
++ sai2 {
++ pinctrl_sai2_1: sai2grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030
++ MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030
++ MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030
++ MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030
++ >;
++ };
++ };
++
++
++ spdif {
++ pinctrl_spdif_1: spdifgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0
++ MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
++ >;
++ };
++
++ pinctrl_spdif_2: spdifgrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
++ >;
++ };
++ };
++
++ uart1 {
++ pinctrl_uart1_1: uart1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1_2: uart1grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
++ MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
++ >;
++ };
++ };
++
++ uart2 {
++ pinctrl_uart2_1: uart2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2_2: uart2grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
++ MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
++ >;
++ };
++ };
++
++ uart5 {
++ pinctrl_uart5_1: uart5grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5dte_1: uart5dtegrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
++ >;
++ };
++ };
++
++ usbh {
++ pinctrl_usbh_1: usbhgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030
++ MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030
++ >;
++ };
++
++ pinctrl_usbh_2: usbhgrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030
++ >;
++ };
++ };
++
++ usbotg1 {
++ pinctrl_usbotg1_1: usbotg1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_2: usbotg1grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg1_3: usbotg1grp-3 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++ };
++
++ usbotg2 {
++ pinctrl_usbotg2_1: usbotg2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg2_2: usbotg2grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059
++ >;
++ };
++
++ pinctrl_usbotg2_3: usbotg2grp-3 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059
++ >;
++ };
++ };
++
++ usdhc1 {
++ pinctrl_usdhc1_1: usdhc1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059
++ MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059
++ MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
++ MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
++ MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
++ MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
++ >;
++ };
++ };
++
++ usdhc2 {
++ pinctrl_usdhc2_1: usdhc2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
++ MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
++ MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
++ MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
++ MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
++ MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
++ >;
++ };
++ };
++
++ usdhc3 {
++ pinctrl_usdhc3_1: usdhc3grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
++ >;
++ };
++
++ };
++
++ usdhc4 {
++ pinctrl_usdhc4_1: usdhc4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc4_2: usdhc4grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ >;
++ };
++
++ };
++
++ weim {
++ pinctrl_weim_cs0_1: weim_cs0grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1
++ >;
++ };
++
++ pinctrl_weim_nor_1: weim_norgrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1
++ MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1
++ MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060
++ /* data */
++ MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0
++ MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0
++ MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0
++ MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0
++ MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0
++ MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0
++ MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0
++ /* address */
++ MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1
++ MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1
++ MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1
++ MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1
++ MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1
++ MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1
++ MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1
++ MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1
++ MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1
++ MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1
++ MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1
++ MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1
++ MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1
++ MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1
++ MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1
++ MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1
++ MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1
++ MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1
++ MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1
++ MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1
++ MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1
++ MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1
++ MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1
++ MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1
++ MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1
++ MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1
++ >;
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-gpmi-weim.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-19x19-arm2.dts"
++
++&qspi2 {
++ status = "disabled";
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ status = "okay"; /* pin conflict with qspi*/
++ nand-on-flash-bbt;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-lcdif1.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-lcdif1.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-lcdif1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-lcdif1.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,19 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-19x19-arm2.dts"
++
++&i2c2 {
++ ov5640: ov5640@3c {
++ status = "disabled";
++ };
++};
++
++&lcdif1 {
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-ldo.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-ldo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-ldo.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-19x19-arm2.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++};
++
++&gpc {
++ fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-mqs.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,42 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-19x19-arm2.dts"
++
++/ {
++ sound-mqs {
++ compatible = "fsl,imx6sx-sdb-mqs",
++ "fsl,imx-audio-mqs";
++ model = "mqs-audio";
++ cpu-dai = <&sai1>;
++ audio-codec = <&mqs>;
++ };
++};
++
++&esai {
++ /* pin conflict with sai */
++ status = "disabled";
++};
++
++&mqs {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mqs_1>;
++ clocks = <&clks IMX6SX_CLK_SAI1>;
++ clock-names = "mclk";
++ status = "okay";
++};
++
++&sai1 {
++ status = "okay";
++};
++
++&sdma {
++ gpr = <&gpr>;
++ /* SDMA event remap for SAI1 */
++ fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-sai.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-sai.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-19x19-arm2-sai.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-19x19-arm2-sai.dts 2016-06-19 22:11:55.029157811 +0200
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-19x19-arm2.dts"
++
++/ {
++ sound-sgtl5000 {
++ compatible = "fsl,imx6sx-arm2-sgtl5000",
++ "fsl,imx-audio-sgtl5000";
++ model = "imx6sx-arm2-sgtl5000";
++ cpu-dai = <&sai1>;
++ audio-codec = <&sgtl5000>;
++ audio-routing =
++ "LINE_IN", "Line In Jack",
++ "Headphone Jack", "HP_OUT";
++ };
++};
++
++&esai {
++ /* pin conflict with sai */
++ status = "disabled";
++};
++
++&sai1 {
++ status = "okay";
++};
++
++&sdma {
++ gpr = <&gpr>;
++ /* SDMA event remap for SAI1 */
++ fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx.dtsi linux-3.14.72/arch/arm/boot/dts/imx6sx.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx.dtsi 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx.dtsi 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,1492 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <dt-bindings/clock/imx6sx-clock.h>
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include "imx6sx-pinfunc.h"
++#include "skeleton.dtsi"
++
++/ {
++ aliases {
++ can0 = &flexcan1;
++ can1 = &flexcan2;
++ ethernet0 = &fec1;
++ ethernet1 = &fec2;
++ gpio0 = &gpio1;
++ gpio1 = &gpio2;
++ gpio2 = &gpio3;
++ gpio3 = &gpio4;
++ gpio4 = &gpio5;
++ gpio5 = &gpio6;
++ gpio6 = &gpio7;
++ i2c0 = &i2c1;
++ i2c1 = &i2c2;
++ i2c2 = &i2c3;
++ i2c3 = &i2c4;
++ mmc0 = &usdhc1;
++ mmc1 = &usdhc2;
++ mmc2 = &usdhc3;
++ mmc3 = &usdhc4;
++ serial0 = &uart1;
++ serial1 = &uart2;
++ serial2 = &uart3;
++ serial3 = &uart4;
++ serial4 = &uart5;
++ serial5 = &uart6;
++ spi0 = &ecspi1;
++ spi1 = &ecspi2;
++ spi2 = &ecspi3;
++ spi3 = &ecspi4;
++ spi4 = &ecspi5;
++ usbphy0 = &usbphy1;
++ usbphy1 = &usbphy2;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu0: cpu@0 {
++ compatible = "arm,cortex-a9";
++ device_type = "cpu";
++ reg = <0>;
++ next-level-cache = <&L2>;
++ operating-points = <
++ /* kHz uV */
++ 996000 1250000
++ 792000 1175000
++ 396000 1075000
++ 198000 975000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC uV */
++ 996000 1175000
++ 792000 1175000
++ 396000 1175000
++ 198000 1175000
++ >;
++ clock-latency = <61036>; /* two CLK32 periods */
++ clocks = <&clks IMX6SX_CLK_ARM>,
++ <&clks IMX6SX_CLK_PLL2_PFD2>,
++ <&clks IMX6SX_CLK_STEP>,
++ <&clks IMX6SX_CLK_PLL1_SW>,
++ <&clks IMX6SX_CLK_PLL1_SYS>,
++ <&clks IMX6SX_PLL1_BYPASS>,
++ <&clks IMX6SX_CLK_PLL1>,
++ <&clks IMX6SX_PLL1_BYPASS_SRC> ;
++ clock-names = "arm", "pll2_pfd2_396m", "step",
++ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++ };
++ };
++
++ intc: interrupt-controller@00a01000 {
++ compatible = "arm,cortex-a9-gic";
++ #interrupt-cells = <3>;
++ interrupt-controller;
++ reg = <0x00a01000 0x1000>,
++ <0x00a00100 0x100>;
++ };
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ckil: clock@0 {
++ compatible = "fixed-clock";
++ reg = <0>;
++ #clock-cells = <0>;
++ clock-frequency = <32768>;
++ clock-output-names = "ckil";
++ };
++
++ osc: clock@1 {
++ compatible = "fixed-clock";
++ reg = <1>;
++ #clock-cells = <0>;
++ clock-frequency = <24000000>;
++ clock-output-names = "osc";
++ };
++
++ ipp_di0: clock@2 {
++ compatible = "fixed-clock";
++ reg = <2>;
++ #clock-cells = <0>;
++ clock-frequency = <0>;
++ clock-output-names = "ipp_di0";
++ };
++
++ ipp_di1: clock@3 {
++ compatible = "fixed-clock";
++ reg = <3>;
++ #clock-cells = <0>;
++ clock-frequency = <0>;
++ clock-output-names = "ipp_di1";
++ };
++ };
++
++ soc {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "simple-bus";
++ interrupt-parent = <&intc>;
++ ranges;
++
++ busfreq {
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>,
++ <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>,
++ <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>,
++ <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>,
++ <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>,
++ <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>,
++ <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM>,
++ <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>,
++ <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>,
++ <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_P0_FAST>,
++ <&clks IMX6SX_CLK_M4>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", "ocram", "pll1_sw",
++ "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", "m4";
++ fsl,max_ddr_freq = <400000000>;
++ };
++
++ pmu {
++ compatible = "arm,cortex-a9-pmu";
++ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ ocrams: sram@008f8000 {
++ compatible = "fsl,lpm-sram";
++ reg = <0x008f8000 0x4000>;
++ clocks = <&clks IMX6SX_CLK_OCRAM_S>;
++ };
++
++ ocrams_ddr: sram@00900000 {
++ compatible = "fsl,ddr-lpm-sram";
++ reg = <0x00900000 0x1000>;
++ clocks = <&clks IMX6SX_CLK_OCRAM>;
++ };
++
++ ocram: sram@00901000 {
++ compatible = "mmio-sram";
++ reg = <0x00901000 0x1F000>;
++ clocks = <&clks IMX6SX_CLK_OCRAM>;
++ };
++
++ ocram_mf: sram-mf@00900000 {
++ compatible = "fsl,mega-fast-sram";
++ reg = <0x00900000 0x20000>;
++ clocks = <&clks IMX6SX_CLK_OCRAM>;
++ };
++
++ L2: l2-cache@00a02000 {
++ compatible = "arm,pl310-cache";
++ reg = <0x00a02000 0x1000>;
++ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
++ cache-unified;
++ cache-level = <2>;
++ arm,tag-latency = <4 2 3>;
++ arm,data-latency = <4 2 3>;
++ };
++
++ gpu: gpu@01800000 {
++ compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu";
++ reg = <0x01800000 0x4000>, <0x80000000 0x0>;
++ reg-names = "iobase_3d", "phys_baseaddr";
++ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "irq_3d";
++ clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>,
++ <&clks 0>;
++ clock-names = "gpu3d_axi_clk", "gpu3d_clk",
++ "gpu3d_shader_clk";
++ resets = <&src 0>;
++ reset-names = "gpu3d";
++ power-domains = <&gpc 1>;
++ };
++
++ caam_sm: caam-sm@00100000 {
++ compatible = "fsl,imx6q-caam-sm";
++ reg = <0x00100000 0x3fff>;
++ };
++
++ dma_apbh: dma-apbh@01804000 {
++ compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
++ reg = <0x01804000 0x2000>;
++ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
++ #dma-cells = <1>;
++ dma-channels = <4>;
++ clocks = <&clks IMX6SX_CLK_APBH_DMA>;
++ };
++
++ irq_sec_vio: caam_secvio {
++ compatible = "fsl,imx6q-caam-secvio";
++ interrupts = <0 20 0x04>;
++ secvio_src = <0x8000001d>;
++ };
++
++ gpmi: gpmi-nand@01806000{
++ compatible = "fsl,imx6sx-gpmi-nand";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
++ reg-names = "gpmi-nand", "bch";
++ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "bch";
++ clocks = <&clks IMX6SX_CLK_GPMI_IO>,
++ <&clks IMX6SX_CLK_GPMI_APB>,
++ <&clks IMX6SX_CLK_GPMI_BCH>,
++ <&clks IMX6SX_CLK_GPMI_BCH_APB>,
++ <&clks IMX6SX_CLK_PER1_BCH>;
++ clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
++ "gpmi_bch_apb", "per1_bch";
++ dmas = <&dma_apbh 0>;
++ dma-names = "rx-tx";
++ status = "disabled";
++ };
++
++ aips1: aips-bus@02000000 {
++ compatible = "fsl,aips-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02000000 0x100000>;
++ ranges;
++
++ spba-bus@02000000 {
++ compatible = "fsl,spba-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02000000 0x40000>;
++ ranges;
++
++ spdif: spdif@02004000 {
++ compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
++ reg = <0x02004000 0x4000>;
++ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&sdma 14 18 0>,
++ <&sdma 15 18 0>;
++ dma-names = "rx", "tx";
++ clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
++ <&clks IMX6SX_CLK_OSC>,
++ <&clks IMX6SX_CLK_SPDIF>,
++ <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks IMX6SX_CLK_IPG>,
++ <&clks 0>, <&clks 0>,
++ <&clks IMX6SX_CLK_SPBA>;
++ clock-names = "core", "rxtx0",
++ "rxtx1", "rxtx2",
++ "rxtx3", "rxtx4",
++ "rxtx5", "rxtx6",
++ "rxtx7", "dma";
++ status = "disabled";
++ };
++
++ ecspi1: ecspi@02008000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
++ reg = <0x02008000 0x4000>;
++ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ECSPI1>,
++ <&clks IMX6SX_CLK_ECSPI1>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ ecspi2: ecspi@0200c000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
++ reg = <0x0200c000 0x4000>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ECSPI2>,
++ <&clks IMX6SX_CLK_ECSPI2>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ ecspi3: ecspi@02010000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
++ reg = <0x02010000 0x4000>;
++ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ECSPI3>,
++ <&clks IMX6SX_CLK_ECSPI3>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ ecspi4: ecspi@02014000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
++ reg = <0x02014000 0x4000>;
++ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ECSPI4>,
++ <&clks IMX6SX_CLK_ECSPI4>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ uart1: serial@02020000 {
++ compatible = "fsl,imx6sx-uart",
++ "fsl,imx6q-uart", "fsl,imx21-uart";
++ reg = <0x02020000 0x4000>;
++ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_UART_IPG>,
++ <&clks IMX6SX_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ esai: esai@02024000 {
++ compatible = "fsl,imx35-esai";
++ reg = <0x02024000 0x4000>;
++ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
++ <&clks IMX6SX_CLK_ESAI_MEM>,
++ <&clks IMX6SX_CLK_ESAI_EXTAL>,
++ <&clks IMX6SX_CLK_ESAI_IPG>,
++ <&clks IMX6SX_CLK_SPBA>;
++ clock-names = "core", "mem", "extal",
++ "fsys", "dma";
++ dmas = <&sdma 23 21 0>,
++ <&sdma 24 21 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ ssi1: ssi@02028000 {
++ compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
++ reg = <0x02028000 0x4000>;
++ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
++ <&clks IMX6SX_CLK_SSI1>;
++ clock-names = "ipg", "baud";
++ dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ ssi2: ssi@0202c000 {
++ compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
++ reg = <0x0202c000 0x4000>;
++ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
++ <&clks IMX6SX_CLK_SSI2>;
++ clock-names = "ipg", "baud";
++ dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ ssi3: ssi@02030000 {
++ compatible = "fsl,imx6sx-ssi", "fsl,imx21-ssi";
++ reg = <0x02030000 0x4000>;
++ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
++ <&clks IMX6SX_CLK_SSI3>;
++ clock-names = "ipg", "baud";
++ dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ asrc: asrc@02034000 {
++ compatible = "fsl,imx53-asrc";
++ reg = <0x02034000 0x4000>;
++ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ASRC_IPG>,
++ <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>,
++ <&clks IMX6SX_CLK_SPBA>;
++ clock-names = "mem", "ipg", "asrck_0",
++ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
++ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
++ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
++ "asrck_d", "asrck_e", "asrck_f", "dma";
++ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
++ <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
++ dma-names = "rxa", "rxb", "rxc",
++ "txa", "txb", "txc";
++ fsl,asrc-rate = <48000>;
++ fsl,asrc-width = <16>;
++ status = "okay";
++ };
++
++ asrc_p2p: asrc_p2p {
++ compatible = "fsl,imx6q-asrc-p2p";
++ fsl,p2p-rate = <48000>;
++ fsl,p2p-width = <16>;
++ fsl,asrc-dma-rx-events = <17 18 19>;
++ fsl,asrc-dma-tx-events = <20 21 22>;
++ status = "okay";
++ };
++ };
++
++ pwm1: pwm@02080000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x02080000 0x4000>;
++ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM1>,
++ <&clks IMX6SX_CLK_PWM1>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++
++ pwm2: pwm@02084000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x02084000 0x4000>;
++ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM2>,
++ <&clks IMX6SX_CLK_PWM2>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++
++ pwm3: pwm@02088000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x02088000 0x4000>;
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM3>,
++ <&clks IMX6SX_CLK_PWM3>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++
++ pwm4: pwm@0208c000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x0208c000 0x4000>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM4>,
++ <&clks IMX6SX_CLK_PWM4>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++
++ flexcan1: can@02090000 {
++ compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
++ reg = <0x02090000 0x4000>;
++ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
++ <&clks IMX6SX_CLK_CAN1_SERIAL>;
++ clock-names = "ipg", "per";
++ stop-mode = <&gpr 0x10 1 0x10 17>;
++ status = "disabled";
++ };
++
++ flexcan2: can@02094000 {
++ compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
++ reg = <0x02094000 0x4000>;
++ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
++ <&clks IMX6SX_CLK_CAN2_SERIAL>;
++ clock-names = "ipg", "per";
++ stop-mode = <&gpr 0x10 2 0x10 18>;
++ status = "disabled";
++ };
++
++ gpt: gpt@02098000 {
++ compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
++ reg = <0x02098000 0x4000>;
++ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_GPT_BUS>,
++ <&clks IMX6SX_CLK_GPT_SERIAL>;
++ clock-names = "ipg", "per";
++ };
++
++ gpio1: gpio@0209c000 {
++ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
++ reg = <0x0209c000 0x4000>;
++ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio2: gpio@020a0000 {
++ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
++ reg = <0x020a0000 0x4000>;
++ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio3: gpio@020a4000 {
++ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
++ reg = <0x020a4000 0x4000>;
++ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio4: gpio@020a8000 {
++ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
++ reg = <0x020a8000 0x4000>;
++ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio5: gpio@020ac000 {
++ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
++ reg = <0x020ac000 0x4000>;
++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio6: gpio@020b0000 {
++ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
++ reg = <0x020b0000 0x4000>;
++ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio7: gpio@020b4000 {
++ compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
++ reg = <0x020b4000 0x4000>;
++ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ kpp: kpp@020b8000 {
++ compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
++ reg = <0x020b8000 0x4000>;
++ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DUMMY>;
++ status = "disabled";
++ };
++
++ wdog1: wdog@020bc000 {
++ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
++ reg = <0x020bc000 0x4000>;
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DUMMY>;
++ };
++
++ wdog2: wdog@020c0000 {
++ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
++ reg = <0x020c0000 0x4000>;
++ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DUMMY>;
++ status = "disabled";
++ };
++
++ clks: ccm@020c4000 {
++ compatible = "fsl,imx6sx-ccm";
++ reg = <0x020c4000 0x4000>;
++ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
++ #clock-cells = <1>;
++ clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
++ clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
++ };
++
++ anatop: anatop@020c8000 {
++ compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
++ "syscon", "simple-bus";
++ reg = <0x020c8000 0x1000>;
++ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
++
++ regulator-1p1@110 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vdd1p1";
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1375000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x110>;
++ anatop-vol-bit-shift = <8>;
++ anatop-vol-bit-width = <5>;
++ anatop-min-bit-val = <4>;
++ anatop-min-voltage = <800000>;
++ anatop-max-voltage = <1375000>;
++ };
++
++ regulator-3p0@120 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vdd3p0";
++ regulator-min-microvolt = <2800000>;
++ regulator-max-microvolt = <3150000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x120>;
++ anatop-vol-bit-shift = <8>;
++ anatop-vol-bit-width = <5>;
++ anatop-min-bit-val = <0>;
++ anatop-min-voltage = <2625000>;
++ anatop-max-voltage = <3400000>;
++ };
++
++ regulator-2p5@130 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vdd2p5";
++ regulator-min-microvolt = <2100000>;
++ regulator-max-microvolt = <2875000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x130>;
++ anatop-vol-bit-shift = <8>;
++ anatop-vol-bit-width = <5>;
++ anatop-min-bit-val = <0>;
++ anatop-min-voltage = <2100000>;
++ anatop-max-voltage = <2875000>;
++ };
++
++ reg_arm: regulator-vddcore@140 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "cpu";
++ regulator-min-microvolt = <725000>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x140>;
++ anatop-vol-bit-shift = <0>;
++ anatop-vol-bit-width = <5>;
++ anatop-delay-reg-offset = <0x170>;
++ anatop-delay-bit-shift = <24>;
++ anatop-delay-bit-width = <2>;
++ anatop-min-bit-val = <1>;
++ anatop-min-voltage = <725000>;
++ anatop-max-voltage = <1450000>;
++ };
++
++ reg_pcie_phy: regulator-vddpcie-phy@140 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vddpcie-phy";
++ regulator-min-microvolt = <725000>;
++ regulator-max-microvolt = <1450000>;
++ anatop-reg-offset = <0x140>;
++ anatop-vol-bit-shift = <9>;
++ anatop-vol-bit-width = <5>;
++ anatop-delay-reg-offset = <0x170>;
++ anatop-delay-bit-shift = <26>;
++ anatop-delay-bit-width = <2>;
++ anatop-min-bit-val = <1>;
++ anatop-min-voltage = <725000>;
++ anatop-max-voltage = <1450000>;
++ };
++
++ reg_soc: regulator-vddsoc@140 {
++ compatible = "fsl,anatop-regulator";
++ regulator-name = "vddsoc";
++ regulator-min-microvolt = <725000>;
++ regulator-max-microvolt = <1450000>;
++ regulator-always-on;
++ anatop-reg-offset = <0x140>;
++ anatop-vol-bit-shift = <18>;
++ anatop-vol-bit-width = <5>;
++ anatop-delay-reg-offset = <0x170>;
++ anatop-delay-bit-shift = <28>;
++ anatop-delay-bit-width = <2>;
++ anatop-min-bit-val = <1>;
++ anatop-min-voltage = <725000>;
++ anatop-max-voltage = <1450000>;
++ };
++ };
++
++ tempmon: tempmon {
++ compatible = "fsl,imx6sx-tempmon";
++ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++ fsl,tempmon = <&anatop>;
++ fsl,tempmon-data = <&ocotp>;
++ clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
++ };
++
++ usbphy1: usbphy@020c9000 {
++ compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
++ reg = <0x020c9000 0x1000>;
++ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USBPHY1>;
++ fsl,anatop = <&anatop>;
++ };
++
++ usbphy2: usbphy@020ca000 {
++ compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
++ reg = <0x020ca000 0x1000>;
++ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USBPHY2>;
++ fsl,anatop = <&anatop>;
++ };
++
++ usbphy_nop1: usbphy_nop1 {
++ compatible = "usb-nop-xceiv";
++ clocks = <&clks IMX6SX_CLK_USBPHY1>;
++ clock-names = "main_clk";
++ };
++
++ mqs: mqs {
++ compatible = "fsl,imx6sx-mqs";
++ gpr = <&gpr>;
++ status = "disabled";
++ };
++
++ caam_snvs: caam-snvs@020cc000 {
++ compatible = "fsl,imx6q-caam-snvs";
++ reg = <0x020cc000 0x4000>;
++ };
++
++ snvs: snvs@020cc000 {
++ compatible = "fsl,sec-v4.0-mon", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x020cc000 0x4000>;
++
++ snvs-rtc-lp@34 {
++ compatible = "fsl,sec-v4.0-mon-rtc-lp";
++ reg = <0x34 0x58>;
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
++ };
++ };
++
++ snvs-pwrkey@0x020cc000 {
++ compatible = "fsl,imx6sx-snvs-pwrkey";
++ reg = <0x020cc000 0x4000>;
++ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
++ fsl,keycode = <116>; /* KEY_POWER */
++ fsl,wakeup;
++ };
++
++ epit1: epit@020d0000 {
++ reg = <0x020d0000 0x4000>;
++ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ epit2: epit@020d4000 {
++ reg = <0x020d4000 0x4000>;
++ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ src: src@020d8000 {
++ compatible = "fsl,imx6sx-src", "fsl,imx51-src";
++ reg = <0x020d8000 0x4000>;
++ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++ #reset-cells = <1>;
++ };
++
++ gpc: gpc@020dc000 {
++ compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
++ reg = <0x020dc000 0x4000>;
++ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
++ fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>;
++ clocks = <&clks IMX6SX_CLK_GPU>, <&clks IMX6SX_CLK_IPG>,
++ <&clks IMX6SX_CLK_PXP_AXI>, <&clks IMX6SX_CLK_DISPLAY_AXI>,
++ <&clks IMX6SX_CLK_LCDIF1_PIX>, <&clks IMX6SX_CLK_LCDIF_APB>,
++ <&clks IMX6SX_CLK_LCDIF2_PIX>, <&clks IMX6SX_CLK_CSI>,
++ <&clks IMX6SX_CLK_VADC>;
++ clock-names = "gpu3d_core", "ipg", "pxp_axi", "disp_axi", "lcdif1_pix",
++ "lcdif_axi", "lcdif2_pix", "csi_mclk";
++ pcie-phy-supply = <&reg_pcie_phy>;
++ #power-domain-cells = <1>;
++ };
++
++ iomuxc: iomuxc@020e0000 {
++ compatible = "fsl,imx6sx-iomuxc";
++ reg = <0x020e0000 0x4000>;
++ };
++
++ gpr: iomuxc-gpr@020e4000 {
++ compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
++ reg = <0x020e4000 0x4000>;
++ };
++
++ ldb: ldb@020e0014 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb";
++ gpr = <&gpr>;
++ status = "disabled";
++
++ clocks = <&clks IMX6SX_CLK_LDB_DI0>,
++ <&clks IMX6SX_CLK_LCDIF1_SEL>,
++ <&clks IMX6SX_CLK_LCDIF2_SEL>,
++ <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>,
++ <&clks IMX6SX_CLK_LDB_DI0_DIV_7>,
++ <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>;
++ clock-names = "ldb_di0",
++ "di0_sel",
++ "di1_sel",
++ "ldb_di0_div_3_5",
++ "ldb_di0_div_7",
++ "ldb_di0_div_sel";
++
++ lvds-channel@0 {
++ reg = <0>;
++ status = "disabled";
++ };
++ };
++
++ sdma: sdma@020ec000 {
++ compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma";
++ reg = <0x020ec000 0x4000>;
++ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_SDMA>,
++ <&clks IMX6SX_CLK_SDMA>;
++ clock-names = "ipg", "ahb";
++ #dma-cells = <3>;
++ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
++ };
++ };
++
++ aips2: aips-bus@02100000 {
++ compatible = "fsl,aips-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02100000 0x100000>;
++ ranges;
++
++ crypto: caam@2100000 {
++ compatible = "fsl,sec-v4.0";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x2100000 0x40000>;
++ ranges = <0 0x2100000 0x40000>;
++ interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */
++ clocks = <&clks IMX6SX_CLK_CAAM_MEM>, <&clks IMX6SX_CLK_CAAM_ACLK>,
++ <&clks IMX6SX_CLK_CAAM_IPG> ,<&clks IMX6SX_CLK_EIM_SLOW>;
++ clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow";
++
++ sec_jr0: jr0@1000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x1000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 105 0x4>;
++ };
++
++ sec_jr1: jr1@2000 {
++ compatible = "fsl,sec-v4.0-job-ring";
++ reg = <0x2000 0x1000>;
++ interrupt-parent = <&intc>;
++ interrupts = <0 106 0x4>;
++ };
++ };
++
++ usbotg1: usb@02184000 {
++ compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
++ reg = <0x02184000 0x200>;
++ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USBOH3>;
++ fsl,usbphy = <&usbphy1>;
++ fsl,usbmisc = <&usbmisc 0>;
++ fsl,anatop = <&anatop>;
++ status = "disabled";
++ };
++
++ usbotg2: usb@02184200 {
++ compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
++ reg = <0x02184200 0x200>;
++ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USBOH3>;
++ fsl,usbphy = <&usbphy2>;
++ fsl,usbmisc = <&usbmisc 1>;
++ status = "disabled";
++ };
++
++ usbh: usb@02184400 {
++ compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
++ reg = <0x02184400 0x200>;
++ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USBOH3>;
++ fsl,usbmisc = <&usbmisc 2>;
++ phy_type = "hsic";
++ fsl,usbphy = <&usbphy_nop1>;
++ fsl,anatop = <&anatop>;
++ status = "disabled";
++ };
++
++ usbmisc: usbmisc@02184800 {
++ #index-cells = <1>;
++ compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
++ reg = <0x02184800 0x200>;
++ clocks = <&clks IMX6SX_CLK_USBOH3>;
++ };
++
++ fec1: ethernet@02188000 {
++ compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
++ reg = <0x02188000 0x4000>;
++ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ENET>,
++ <&clks IMX6SX_CLK_ENET_AHB>,
++ <&clks IMX6SX_CLK_ENET_PTP>,
++ <&clks IMX6SX_CLK_ENET_REF>,
++ <&clks IMX6SX_CLK_ENET_PTP>;
++ clock-names = "ipg", "ahb", "ptp",
++ "enet_clk_ref", "enet_out";
++ fsl,num-tx-queues=<3>;
++ fsl,num-rx-queues=<3>;
++ status = "disabled";
++ };
++
++ mlb: mlb@0218c000 {
++ compatible = "fsl,imx6sx-mlb50";
++ reg = <0x0218c000 0x4000>;
++ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_MLB>;
++ clock-names = "mlb";
++ iram = <&ocram>;
++ status = "disabled";
++ };
++
++ usdhc1: usdhc@02190000 {
++ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
++ reg = <0x02190000 0x4000>;
++ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USDHC1>,
++ <&clks IMX6SX_CLK_USDHC1>,
++ <&clks IMX6SX_CLK_USDHC1>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ usdhc2: usdhc@02194000 {
++ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
++ reg = <0x02194000 0x4000>;
++ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USDHC2>,
++ <&clks IMX6SX_CLK_USDHC2>,
++ <&clks IMX6SX_CLK_USDHC2>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ usdhc3: usdhc@02198000 {
++ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
++ reg = <0x02198000 0x4000>;
++ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USDHC3>,
++ <&clks IMX6SX_CLK_USDHC3>,
++ <&clks IMX6SX_CLK_USDHC3>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ usdhc4: usdhc@0219c000 {
++ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
++ reg = <0x0219c000 0x4000>;
++ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_USDHC4>,
++ <&clks IMX6SX_CLK_USDHC4>,
++ <&clks IMX6SX_CLK_USDHC4>;
++ clock-names = "ipg", "ahb", "per";
++ bus-width = <4>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@021a0000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
++ reg = <0x021a0000 0x4000>;
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_I2C1>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@021a4000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
++ reg = <0x021a4000 0x4000>;
++ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_I2C2>;
++ status = "disabled";
++ };
++
++ i2c3: i2c@021a8000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
++ reg = <0x021a8000 0x4000>;
++ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_I2C3>;
++ status = "disabled";
++ };
++
++ mmdc: mmdc@021b0000 {
++ compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
++ reg = <0x021b0000 0x4000>;
++ };
++
++ fec2: ethernet@021b4000 {
++ compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
++ reg = <0x021b4000 0x4000>;
++ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ENET>,
++ <&clks IMX6SX_CLK_ENET_AHB>,
++ <&clks IMX6SX_CLK_ENET_PTP>,
++ <&clks IMX6SX_CLK_ENET2_REF_125M>,
++ <&clks IMX6SX_CLK_ENET_PTP>;
++ clock-names = "ipg", "ahb", "ptp",
++ "enet_clk_ref", "enet_out";
++ fsl,num-tx-queues=<3>;
++ fsl,num-rx-queues=<3>;
++ status = "disabled";
++ };
++
++ weim: weim@021b8000 {
++ compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
++ reg = <0x021b8000 0x4000>;
++ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
++ };
++
++ ocotp: ocotp-ctrl@021bc000 {
++ compatible = "syscon";
++ reg = <0x021bc000 0x4000>;
++ clocks = <&clks IMX6SX_CLK_OCOTP>;
++ };
++
++ ocotp-fuse@021bc000 {
++ compatible = "fsl,imx6sx-ocotp", "fsl,imx6q-ocotp";
++ reg = <0x021bc000 0x4000>;
++ clocks = <&clks IMX6SX_CLK_OCOTP>;
++ };
++
++ romcp@021ac000 {
++ compatible = "fsl,imx6sx-romcp", "syscon";
++ reg = <0x021ac000 0x4000>;
++ };
++
++ sai1: sai@021d4000 {
++ compatible = "fsl,imx6sx-sai";
++ reg = <0x021d4000 0x4000>;
++ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
++ <&clks IMX6SX_CLK_SAI1>,
++ <&clks 0>, <&clks 0>;
++ clock-names = "bus", "mclk1", "mclk2", "mclk3";
++ dma-names = "rx", "tx";
++ dmas = <&sdma 31 25 0>, <&sdma 32 25 0>;
++ dma-source = <&gpr 0 15 0 16>;
++ status = "disabled";
++ };
++
++ audmux: audmux@021d8000 {
++ compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
++ reg = <0x021d8000 0x4000>;
++ status = "disabled";
++ };
++
++ sai2: sai@021dc000 {
++ compatible = "fsl,imx6sx-sai";
++ reg = <0x021dc000 0x4000>;
++ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
++ <&clks IMX6SX_CLK_SAI2>,
++ <&clks 0>, <&clks 0>;
++ clock-names = "bus", "mclk1", "mclk2", "mclk3";
++ dma-names = "rx", "tx";
++ dmas = <&sdma 33 25 0>, <&sdma 34 25 0>;
++ dma-source = <&gpr 0 17 0 18>;
++ status = "disabled";
++ };
++
++ qspi1: qspi@021e0000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-qspi";
++ reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_QSPI1>,
++ <&clks IMX6SX_CLK_QSPI1>;
++ clock-names = "qspi_en", "qspi";
++ status = "disabled";
++ };
++
++ qspi2: qspi@021e4000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-qspi";
++ reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_QSPI2>,
++ <&clks IMX6SX_CLK_QSPI2>;
++ clock-names = "qspi_en", "qspi";
++ status = "disabled";
++ };
++
++ qspi_m4: qspi-m4 {
++ compatible = "fsl,imx6sx-qspi-m4-restore";
++ reg = <0x021e4000 0x4000>;
++ status = "disabled";
++ };
++
++ uart2: serial@021e8000 {
++ compatible = "fsl,imx6sx-uart",
++ "fsl,imx6q-uart", "fsl,imx21-uart";
++ reg = <0x021e8000 0x4000>;
++ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_UART_IPG>,
++ <&clks IMX6SX_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ uart3: serial@021ec000 {
++ compatible = "fsl,imx6sx-uart",
++ "fsl,imx6q-uart", "fsl,imx21-uart";
++ reg = <0x021ec000 0x4000>;
++ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_UART_IPG>,
++ <&clks IMX6SX_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ uart4: serial@021f0000 {
++ compatible = "fsl,imx6sx-uart",
++ "fsl,imx6q-uart", "fsl,imx21-uart";
++ reg = <0x021f0000 0x4000>;
++ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_UART_IPG>,
++ <&clks IMX6SX_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ uart5: serial@021f4000 {
++ compatible = "fsl,imx6sx-uart",
++ "fsl,imx6q-uart", "fsl,imx21-uart";
++ reg = <0x021f4000 0x4000>;
++ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_UART_IPG>,
++ <&clks IMX6SX_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ i2c4: i2c@021f8000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
++ reg = <0x021f8000 0x4000>;
++ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_I2C4>;
++ status = "disabled";
++ };
++
++ qosc: qosc@021fc000 {
++ compatible = "fsl,imx6sx-qosc";
++ reg = <0x021fc000 0x4000>;
++ };
++ };
++
++ aips3: aips-bus@02200000 {
++ compatible = "fsl,aips-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02200000 0x100000>;
++ ranges;
++
++ spba-bus@02200000 {
++ compatible = "fsl,spba-bus", "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ reg = <0x02240000 0x40000>;
++ ranges;
++
++ dcic1: dcic@0220c000 {
++ compatible = "fsl,imx6sx-dcic";
++ reg = <0x0220c000 0x4000>;
++ interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DCIC1>,
++ <&clks IMX6SX_CLK_DISPLAY_AXI>;
++ clock-names = "dcic", "disp-axi";
++ gpr = <&gpr>;
++ status = "disabled";
++ };
++
++ dcic2: dcic@02210000 {
++ compatible = "fsl,imx6sx-dcic";
++ reg = <0x02210000 0x4000>;
++ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DCIC2>,
++ <&clks IMX6SX_CLK_DISPLAY_AXI>;
++ clock-names = "dcic", "disp-axi";
++ gpr = <&gpr>;
++ status = "disabled";
++ };
++
++ csi1: csi@02214000 {
++ compatible = "fsl,imx6s-csi";
++ reg = <0x02214000 0x4000>;
++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
++ <&clks IMX6SX_CLK_CSI>,
++ <&clks IMX6SX_CLK_DCIC1>;
++ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
++ power-domains = <&gpc 2>;
++ status = "disabled";
++ };
++
++ pxp: pxp@02218000 {
++ compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
++ reg = <0x02218000 0x4000>;
++ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PXP_AXI>,
++ <&clks IMX6SX_CLK_DISPLAY_AXI>;
++ clock-names = "pxp-axi", "disp-axi";
++ power-domains = <&gpc 2>;
++ status = "disabled";
++ };
++
++ csi2: csi@0221c000 {
++ compatible = "fsl,imx6s-csi";
++ reg = <0x0221c000 0x4000>;
++ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
++ <&clks IMX6SX_CLK_CSI>,
++ <&clks IMX6SX_CLK_DCIC2>;
++ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
++ power-domains = <&gpc 2>;
++ status = "disabled";
++ };
++
++ lcdif1: lcdif@02220000 {
++ compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
++ reg = <0x02220000 0x4000>;
++ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
++ <&clks IMX6SX_CLK_LCDIF_APB>,
++ <&clks IMX6SX_CLK_DISPLAY_AXI>;
++ clock-names = "pix", "axi", "disp_axi";
++ power-domains = <&gpc 2>;
++ status = "disabled";
++ };
++
++ lcdif2: lcdif@02224000 {
++ compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif";
++ reg = <0x02224000 0x4000>;
++ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
++ <&clks IMX6SX_CLK_LCDIF_APB>,
++ <&clks IMX6SX_CLK_DISPLAY_AXI>;
++ clock-names = "pix", "axi", "disp_axi";
++ power-domains = <&gpc 2>;
++ status = "disabled";
++ };
++
++ vadc: vadc@02228000 {
++ compatible = "fsl,imx6sx-vadc";
++ reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
++ reg-names = "vadc-vafe", "vadc-vdec";
++ clocks = <&clks IMX6SX_CLK_VADC>,
++ <&clks IMX6SX_CLK_CSI>;
++ clock-names = "vadc", "csi";
++ power-domains = <&gpc 2>;
++ gpr = <&gpr>;
++ status = "disabled";
++ };
++ };
++
++ adc1: adc@02280000 {
++ compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
++ reg = <0x02280000 0x4000>;
++ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_IPG>;
++ num-channels = <4>;
++ clock-names = "adc";
++ status = "disabled";
++ };
++
++ adc2: adc@02284000 {
++ compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
++ reg = <0x02284000 0x4000>;
++ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_IPG>;
++ num-channels = <4>;
++ clock-names = "adc";
++ status = "disabled";
++ };
++
++ wdog3: wdog@02288000 {
++ compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
++ reg = <0x02288000 0x4000>;
++ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_DUMMY>;
++ status = "disabled";
++ };
++
++ ecspi5: ecspi@0228c000 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
++ reg = <0x0228c000 0x4000>;
++ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_ECSPI5>,
++ <&clks IMX6SX_CLK_ECSPI5>;
++ clock-names = "ipg", "per";
++ status = "disabled";
++ };
++
++ sema4: sema4@02290000 { /* sema4 */
++ compatible = "fsl,imx6sx-sema4";
++ reg = <0x02290000 0x4000>;
++ interrupts = <0 116 0x04>;
++ status = "okay";
++ };
++
++ mu: mu@02294000 { /* mu */
++ compatible = "fsl,imx6sx-mu";
++ reg = <0x02294000 0x4000>;
++ interrupts = <0 90 0x04>;
++ status = "okay";
++ };
++
++ mcctest: mcctest{
++ compatible = "fsl,imx6sx-mcc-test";
++ status = "disabled";
++ };
++
++ mcctty: mcctty{
++ compatible = "fsl,imx6sx-mcc-tty";
++ status = "disabled";
++ };
++
++ uart6: serial@022a0000 {
++ compatible = "fsl,imx6sx-uart",
++ "fsl,imx6q-uart", "fsl,imx21-uart";
++ reg = <0x022a0000 0x4000>;
++ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_UART_IPG>,
++ <&clks IMX6SX_CLK_UART_SERIAL>;
++ clock-names = "ipg", "per";
++ dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
++ dma-names = "rx", "tx";
++ status = "disabled";
++ };
++
++ pwm5: pwm@022a4000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x022a4000 0x4000>;
++ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM5>,
++ <&clks IMX6SX_CLK_PWM5>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++
++ pwm6: pwm@022a8000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x022a8000 0x4000>;
++ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM6>,
++ <&clks IMX6SX_CLK_PWM6>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++
++ pwm7: pwm@022ac000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x022ac000 0x4000>;
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM7>,
++ <&clks IMX6SX_CLK_PWM7>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++
++ pwm8: pwm@0022b0000 {
++ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
++ reg = <0x0022b0000 0x4000>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PWM8>,
++ <&clks IMX6SX_CLK_PWM8>;
++ clock-names = "ipg", "per";
++ #pwm-cells = <2>;
++ };
++ };
++
++ pcie: pcie@0x08000000 {
++ compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
++ reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>;
++ reg-names = "dbi", "config";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
++ num-lanes = <1>;
++ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
++ <&clks IMX6SX_CLK_LVDS1_OUT>,
++ <&clks IMX6SX_CLK_PCIE_REF_125M>,
++ <&clks IMX6SX_CLK_DISPLAY_AXI>;
++ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
++ pcie-phy-supply = <&reg_pcie_phy>;
++ power-domains = <&gpc 2>;
++ status = "disabled";
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-pinfunc.h linux-3.14.72/arch/arm/boot/dts/imx6sx-pinfunc.h
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-pinfunc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-pinfunc.h 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,1570 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DTS_IMX6SX_PINFUNC_H
++#define __DTS_IMX6SX_PINFUNC_H
++
++/*
++ * The pin function ID is a tuple of
++ * <mux_reg conf_reg input_reg mux_mode input_val>
++ */
++#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
++#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
++#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1
++#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1
++#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1
++#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1
++#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1
++#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1
++#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B 0x002C 0x0374 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1
++#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
++#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B 0x0030 0x0378 0x082C 0x4 0x1
++#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0
++#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
++#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B 0x0034 0x037C 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0
++#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B 0x0038 0x0380 0x0834 0x4 0x1
++#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0
++#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1
++#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0
++#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2
++#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0
++#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0
++#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0
++#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0
++#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0
++#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0
++#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0
++#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0
++#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0
++#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0
++#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0
++#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1
++#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1
++#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0
++#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0
++#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0
++#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1
++#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1
++#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0
++#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0
++#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0
++#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1
++#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1
++#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0
++#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0
++#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0
++#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1
++#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1
++#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0
++#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0
++#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0
++#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1
++#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
++#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0
++#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0
++#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0
++#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0
++#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1
++#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
++#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0
++#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1
++#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0
++#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0
++#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1
++#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
++#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
++#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
++#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B 0x0064 0x03AC 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
++#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0
++#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
++#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
++#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
++#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B 0x0068 0x03B0 0x0854 0x4 0x1
++#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
++#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0
++#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
++#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
++#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
++#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B 0x006C 0x03B4 0x0000 0x3 0x0
++#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0
++#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0
++#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1
++#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
++#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
++#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0
++#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0
++#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0
++#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1
++#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
++#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3
++#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0
++#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2
++#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0
++#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
++#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
++#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
++#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0
++#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B 0x0078 0x03C0 0x0844 0x3 0x3
++#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
++#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
++#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
++#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0
++#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0
++#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0
++#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0
++#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1
++#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1
++#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0
++#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0
++#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1
++#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1
++#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0
++#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0
++#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0
++#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0
++#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1
++#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0
++#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0
++#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1
++#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2
++#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0
++#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0
++#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1
++#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1
++#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
++#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
++#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0
++#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0
++#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
++#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
++#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3
++#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1
++#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0
++#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
++#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
++#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3
++#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1
++#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1
++#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0
++#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
++#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
++#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
++#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B 0x009C 0x03E4 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
++#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
++#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0
++#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
++#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
++#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
++#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0
++#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B 0x00A0 0x03E8 0x082C 0x3 0x3
++#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
++#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
++#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
++#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0
++#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0
++#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0
++#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
++#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
++#define MX6SX_PAD_KEY_COL0__UART6_CTS_B 0x00A4 0x03EC 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
++#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
++#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1
++#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0
++#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0
++#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0
++#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
++#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0
++#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0
++#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0
++#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
++#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
++#define MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x00AC 0x03F4 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
++#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
++#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0
++#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0
++#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
++#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0
++#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0
++#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0
++#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0
++#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2
++#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0
++#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0
++#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
++#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
++#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B 0x00B8 0x0400 0x0854 0x2 0x3
++#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
++#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
++#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1
++#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0
++#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0
++#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0
++#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
++#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0
++#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0
++#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0
++#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
++#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
++#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x00C0 0x0408 0x084C 0x2 0x3
++#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
++#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
++#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0
++#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0
++#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
++#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
++#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1
++#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1
++#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0
++#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0
++#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3
++#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2
++#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0
++#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0
++#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0
++#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0
++#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0
++#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1
++#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0
++#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0
++#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1
++#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0
++#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0
++#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0
++#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1
++#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0
++#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0
++#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0
++#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1
++#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0
++#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0
++#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0
++#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1
++#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0
++#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0
++#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0
++#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0
++#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1
++#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1
++#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0
++#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0
++#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0
++#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0
++#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0
++#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0
++#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0
++#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0
++#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0
++#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0
++#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0
++#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0
++#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0
++#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0
++#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0
++#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0
++#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0
++#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0
++#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0
++#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0
++#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0
++#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0
++#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0
++#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0
++#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
++#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B 0x0160 0x04A8 0x0000 0x3 0x0
++#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
++#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0
++#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B 0x0164 0x04AC 0x083C 0x3 0x1
++#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
++#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0
++#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0
++#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0
++#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1
++#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0
++#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0
++#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0
++#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0
++#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0
++#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0
++#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0
++#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0
++#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0
++#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0
++#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0
++#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0
++#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0
++#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0
++#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0
++#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0
++#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0
++#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0
++#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2
++#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1
++#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2
++#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1
++#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2
++#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1
++#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2
++#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1
++#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0
++#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0
++#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2
++#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1
++#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2
++#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0
++#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2
++#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1
++#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0
++#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0
++#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1
++#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1
++#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2
++#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1
++#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2
++#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1
++#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0
++#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1
++#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2
++#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1
++#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2
++#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2
++#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1
++#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1
++#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
++#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0
++#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B 0x01A0 0x04E8 0x083C 0x1 0x4
++#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
++#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
++#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
++#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
++#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B 0x01A4 0x04EC 0x0000 0x1 0x0
++#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
++#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
++#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
++#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2
++#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0
++#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2
++#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1
++#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2
++#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0
++#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2
++#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1
++#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0
++#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0
++#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1
++#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1
++#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4
++#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
++#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
++#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
++#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5
++#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0
++#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
++#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3
++#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1
++#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0
++#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0
++#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2
++#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2
++#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1
++#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1
++#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0
++#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0
++#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1
++#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0
++#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1
++#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1
++#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1
++#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1
++#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1
++#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0
++#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0
++#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0
++#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0
++#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0
++#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0
++#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1
++#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0
++#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1
++#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0
++#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1
++#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0
++#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1
++#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0
++#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1
++#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0
++#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1
++#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0
++#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0
++#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0
++#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0
++#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0
++#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0
++#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0
++#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0
++#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0
++#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0
++#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1
++#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0
++#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0
++#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0
++#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0
++#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0
++#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0
++#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0
++#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0
++#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0
++#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1
++#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0
++#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0
++#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0
++#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0
++#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0
++#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0
++#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0
++#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0
++#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0
++#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1
++#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
++#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0
++#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
++#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0
++#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0
++#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0
++#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0
++#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0
++#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0
++#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0
++#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1
++#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
++#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0
++#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3
++#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0
++#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0
++#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0
++#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0
++#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0
++#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0
++#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0
++#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
++#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
++#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
++#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0
++#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B 0x0230 0x0578 0x0834 0x4 0x2
++#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
++#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
++#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
++#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0
++#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0
++#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1
++#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
++#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
++#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
++#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B 0x0234 0x057C 0x0000 0x4 0x0
++#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
++#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
++#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
++#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0
++#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0
++#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2
++#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1
++#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1
++#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2
++#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0
++#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0
++#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0
++#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0
++#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0
++#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0
++#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2
++#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1
++#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1
++#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2
++#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0
++#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0
++#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0
++#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0
++#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0
++#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0
++#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2
++#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1
++#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0
++#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3
++#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0
++#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0
++#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4
++#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0
++#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0
++#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0
++#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0
++#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2
++#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1
++#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0
++#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3
++#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0
++#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0
++#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5
++#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0
++#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0
++#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0
++#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0
++#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2
++#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1
++#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1
++#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
++#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0
++#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0
++#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4
++#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0
++#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0
++#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0
++#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0
++#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2
++#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1
++#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1
++#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
++#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0
++#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4
++#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5
++#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0
++#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
++#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0
++#define MX6SX_PAD_SD3_CLK__UART4_RTS_B 0x0250 0x0598 0x0844 0x1 0x0
++#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
++#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
++#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0
++#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0
++#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0
++#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
++#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0
++#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1
++#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0
++#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0
++#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0
++#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0
++#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0
++#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0
++#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
++#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B 0x0260 0x05A8 0x0000 0x1 0x0
++#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
++#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
++#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1
++#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0
++#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
++#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0
++#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0
++#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
++#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
++#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0
++#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0
++#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
++#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3
++#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0
++#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
++#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
++#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
++#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B 0x0270 0x05B8 0x0000 0x3 0x0
++#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0
++#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
++#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
++#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
++#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0
++#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B 0x0274 0x05BC 0x083C 0x3 0x3
++#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
++#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
++#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
++#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0
++#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0
++#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1
++#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0
++#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1
++#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0
++#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1
++#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0
++#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1
++#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0
++#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0
++#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0
++#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0
++#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0
++#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
++#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
++#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0
++#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
++#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
++#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0
++#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0
++#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
++#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B 0x0298 0x05E0 0x0000 0x2 0x0
++#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
++#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0
++#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0
++#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B 0x029C 0x05E4 0x084C 0x2 0x1
++#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
++#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0
++#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0
++#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0
++#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0
++#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0
++#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0
++#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0
++#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0
++#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0
++#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0
++#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0
++#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0
++#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0
++#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0
++#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0
++#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1
++#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0
++#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0
++#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0
++#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0
++#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0
++#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1
++#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0
++#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0
++
++#endif /* __DTS_IMX6SX_PINFUNC_H */
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sabreauto.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sabreauto.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sabreauto.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sabreauto.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,925 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/dts-v1/;
++
++#include "imx6sx.dtsi"
++
++/ {
++ model = "Freescale i.MX6 SoloX Sabre Auto Board";
++ compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx";
++
++ backlight2 {
++ compatible = "pwm-backlight";
++ pwms = <&pwm4 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ fb-names = "mxs-lcdif1";
++ };
++
++ clocks {
++ codec_osc: anaclk2 {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <24576000>;
++ };
++ };
++
++ max7322_reset: max7322-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <1>;
++ #reset-cells = <0>;
++ };
++
++ hannstar_cabc {
++ compatible = "hannstar,cabc";
++
++ lvds0 {
++ gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ max7310_reset: max7310-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <1>;
++ #reset-cells = <0>;
++ };
++
++ memory {
++ reg = <0x80000000 0x80000000>;
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++
++ reg_audio: cs42888_supply {
++ compatible = "regulator-fixed";
++ regulator-name = "cs42888_supply";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_vio1: vio1_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "vio1";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_vio2: vio2_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "vio2";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_vd: f3v3_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "vd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ si4763_va: f5v_tnr {
++ compatible = "regulator-fixed";
++ regulator-name = "va";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++
++ reg_lcd_3v3: lcd-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "lcd-3v3";
++ gpio = <&gpio3 27 0>;
++ enable-active-high;
++ status = "disabled";
++ };
++
++ reg_sd3_vmmc: sd3_vmmc{
++ compatible = "regulator-fixed";
++ regulator-name = "VCC_SD3";
++ regulator-min-microvolt = <3000000>;
++ regulator-max-microvolt = <3000000>;
++ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_vref_3v3: regulator@0 {
++ compatible = "regulator-fixed";
++ regulator-name = "vref-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ reg_psu_5v: psu_5v0 {
++ compatible = "regulator-fixed";
++ regulator-name = "PSU-5V0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-boot-on;
++ };
++
++ reg_usb_otg1_vbus: usb_otg1_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 9 0>;
++ enable-active-high;
++ };
++
++ reg_usb_otg2_vbus: usb_otg2_vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg2_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 12 0>;
++ enable-active-high;
++ };
++ };
++
++ sound-cs42888 {
++ compatible = "fsl,imx6-sabreauto-cs42888",
++ "fsl,imx-audio-cs42888";
++ model = "imx-cs42888";
++ esai-controller = <&esai>;
++ asrc-controller = <&asrc>;
++ audio-codec = <&codec>;
++ };
++
++ sound-fm {
++ compatible = "fsl,imx-audio-si476x",
++ "fsl,imx-tuner-si476x";
++ model = "imx-radio-si4763";
++
++ ssi-controller = <&ssi2>;
++ fm-controller = <&si476x_codec>;
++ mux-int-port = <2>;
++ mux-ext-port = <5>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-in;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++
++ imx6x-sabreauto {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x17059
++ MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x17059
++ MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x17059
++ MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x80000000
++ MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x80000000
++ MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x80000000
++ MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x80000000
++ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0
++ >;
++ };
++
++ pinctrl_audmux_3: audmux-3 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0
++ MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0
++ MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0
++ >;
++ };
++
++ pinctrl_enet1_1: enet1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
++ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
++ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
++ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
++ >;
++ };
++
++ pinctrl_enet2_1: enet2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
++ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
++ >;
++ };
++
++ pinctrl_esai_2: esaigrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030
++ MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030
++ MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030
++ MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030
++ MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030
++ MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030
++ MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030
++ MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030
++ MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030
++ >;
++ };
++
++ pinctrl_flexcan1_1: flexcan1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
++ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
++ >;
++ };
++
++ pinctrl_flexcan2_1: flexcan2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
++ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
++ >;
++ };
++
++ pinctrl_gpmi_nand_1: gpmi-nand-1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
++ MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
++ MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
++ MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
++ MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
++ MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
++ MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
++ MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
++ MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
++ MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
++ MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
++ MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
++ MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
++ MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
++ MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
++ MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
++ >;
++ };
++
++ pinctrl_i2c2_1: i2c2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3_2: i2c3grp-2 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_mlb_2: mlbgrp-2 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31
++ MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31
++ MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31
++ >;
++ };
++
++ pinctrl_pwm4_0: pwm4grp-0 {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_qspi1_1: qspi1grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1
++ MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1
++ MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1
++ MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1
++ MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1
++ MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1
++ MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1
++ MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1
++ MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1
++ MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1
++ MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1
++ MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1
++ >;
++ };
++
++ pinctrl_spdif_3: spdifgrp-3 {
++ fsl,pins = <
++ MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0
++ >;
++ };
++
++ pinctrl_uart1_1: uart1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2_1: uart2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5_1: uart5grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5dte_1: uart5dtegrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg1_1: usbotg1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_1: usdhc3grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc4_3: usdhc4grp-3 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071
++ >;
++ };
++ };
++};
++
++&adc1 {
++ vref-supply = <&reg_vref_3v3>;
++ status = "okay";
++};
++
++&adc2 {
++ vref-supply = <&reg_vref_3v3>;
++ status = "okay";
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux_3>;
++ status = "okay";
++};
++
++&clks {
++ assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>,
++ <&clks IMX6SX_PLL4_BYPASS>,
++ <&clks IMX6SX_CLK_PLL4_POST_DIV>;
++ assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>,
++ <&clks IMX6SX_PLL4_BYPASS_SRC>;
++ assigned-clock-rates = <0>, <0>, <24576000>;
++};
++
++&csi2 {
++ status = "okay";
++ port {
++ csi2_ep: endpoint {
++ remote-endpoint = <&vadc_ep>;
++ };
++ };
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-lcdif1";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds";
++ status = "okay";
++};
++
++&esai {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_esai_2>;
++ assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>,
++ <&clks IMX6SX_CLK_ESAI_EXTAL>;
++ assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>;
++ assigned-clock-rates = <0>, <24576000>;
++ status = "okay";
++};
++
++&fec1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet1_1>;
++ phy-mode = "rgmii";
++ phy-handle = <&ethphy1>;
++ pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
++ fsl,magic-packet;
++ status = "okay";
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ ethphy0: ethernet-phy@0 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0>;
++ };
++
++ ethphy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ };
++ };
++};
++
++&fec2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet2_1>;
++ phy-mode = "rgmii";
++ phy-handle = <&ethphy0>;
++ fsl,magic-packet;
++ status = "okay";
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1_1>;
++ trx-en-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
++ trx-wakeup-gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&flexcan2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan2_1>;
++ trx-en-gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>;
++ trx-wakeup-gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2_1>;
++ status = "okay";
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <22 2>;
++ wakeup-gpios = <&gpio6 22 0>;
++ };
++
++ codec: cs42888@048 {
++ compatible = "cirrus,cs42888";
++ reg = <0x048>;
++ clocks = <&codec_osc 0>;
++ clock-names = "mclk";
++ VA-supply = <&reg_audio>;
++ VD-supply = <&reg_audio>;
++ VLS-supply = <&reg_audio>;
++ VLC-supply = <&reg_audio>;
++ };
++
++ si4763: si4763@63 {
++ compatible = "si4761";
++ reg = <0x63>;
++ va-supply = <&si4763_va>;
++ vd-supply = <&si4763_vd>;
++ vio1-supply = <&si4763_vio1>;
++ vio2-supply = <&si4763_vio2>;
++ revision-a10; /* set to default A10 compatible command set */
++
++ si476x_codec: si476x-codec {
++ compatible = "si476x-codec";
++ };
++ };
++
++ max7322: gpio@68 {
++ compatible = "maxim,max7322";
++ reg = <0x68>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7322_reset>;
++ };
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze100";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ regulator-always-on;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif_3>;
++ status = "okay";
++};
++
++&ssi2 {
++ fsl,mode = "i2s-master";
++ status = "okay";
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3_2>;
++ status = "okay";
++
++ max7310_a: gpio@30 {
++ compatible = "maxim,max7310";
++ reg = <0x30>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7310_reset>;
++ };
++
++ max7310_b: gpio@32 {
++ compatible = "maxim,max7310";
++ reg = <0x32>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ resets = <&max7310_reset>;
++ };
++
++ mma8451@1c {
++ compatible = "fsl,mma8451";
++ reg = <0x1c>;
++ position = <7>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <24 8>;
++ interrupt-route = <1>;
++ };
++
++ mag3110@0e {
++ compatible = "fsl,mag3110";
++ reg = <0x0e>;
++ position = <2>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <6 1>;
++ };
++
++ isl29023@44 {
++ compatible = "fsl,isl29023";
++ reg = <0x44>;
++ rext = <499>;
++ interrupt-parent = <&gpio3>;
++ interrupts = <23 2>;
++ };
++};
++
++&lcdif2 {
++ display = <&display1>;
++ disp-dev = "ldb";
++ status = "okay";
++
++ display1: display {
++ bits-per-pixel = <16>;
++ bus-width = <18>;
++ };
++};
++
++&ldb {
++ status = "okay";
++
++ lvds-channel@0 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ crtc = "lcdif2";
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing1>;
++ timing1: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&mlb {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mlb_2>;
++ status = "okay";
++};
++
++&pcie {
++ reset-gpio = <&max7310_b 3 0>;
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1_1>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2_1>;
++ status = "okay";
++};
++
++&uart5 { /* for bluetooth */
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5_1>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++ /* for DTE mode, add below change */
++ /* fsl,dte-mode;*/
++ /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
++};
++
++&usbotg1 {
++ vbus-supply = <&reg_usb_otg1_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg1_1>;
++ status = "okay";
++};
++
++&usbotg2 {
++ vbus-supply = <&reg_usb_otg2_vbus>;
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3_1>;
++ pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>;
++ bus-width = <8>;
++ cd-gpios = <&gpio7 10 0>;
++ wp-gpios = <&gpio3 19 0>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ vmmc-supply = <&reg_sd3_vmmc>;
++ status = "okay";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4_3>;
++ bus-width = <8>;
++ cd-gpios = <&gpio7 11 0>;
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakup;
++ status = "okay";
++};
++
++&pwm4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm4_0>;
++ status = "okay";
++};
++
++&pxp {
++ status = "okay";
++};
++
++&qspi1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_qspi1_1>;
++ /* only map 128MB */
++ reg = <0x021e0000 0x4000>, <0x60000000 0x8000000>;
++ status = "okay";
++ ddrsmp=<2>;
++
++ flash0: n25q256a@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ reg = <0>;
++ };
++
++ flash1: n25q256a@1 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ reg = <1>;
++ };
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand_1>;
++ status = "okay";
++ nand-on-flash-bbt;
++};
++
++&vadc {
++ vadc_in = <0>;
++ csi_id = <1>;
++ status = "okay";
++ port {
++ vadc_ep: endpoint {
++ remote-endpoint = <&csi2_ep>;
++ };
++ };
++};
++
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sabreauto-m4.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sabreauto-m4.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sabreauto-m4.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sabreauto-m4.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,90 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-sabreauto.dts"
++
++/{
++ memory {
++ linux,usable-memory = <0x80000000 0x3ff00000>;
++ reg = <0x80000000 0x40000000>;
++ };
++};
++
++/*
++ * The flollowing modules are conflicting with M4, disable them when m4
++ * is running.
++ */
++&flexcan1 {
++ status = "disabled";
++};
++
++&flexcan2 {
++ status = "disabled";
++};
++
++&i2c3 {
++ status = "disabled";
++};
++
++&mcctest{
++ status = "okay";
++};
++
++&mcctty{
++ status = "okay";
++};
++
++&uart2 {
++ status = "disabled";
++};
++
++&adc1 {
++ status = "disabled";
++};
++
++&adc2 {
++ status = "disabled";
++};
++
++&qspi1 {
++ status = "disabled";
++};
++
++&qspi_m4 {
++ reg = <0x021e0000 0x4000>;
++ status = "okay";
++};
++
++&ocram {
++ reg = <0x00901000 0x1E000>;
++};
++
++&clks {
++ fsl,shared-clks-number = <0x23>;
++ fsl,shared-clks-index = <IMX6SX_CLK_PLL2_BUS IMX6SX_CLK_PLL2_PFD0
++ IMX6SX_CLK_PLL2_PFD2 IMX6SX_CLK_PLL3_USB_OTG
++ IMX6SX_CLK_PLL3_PFD1 IMX6SX_CLK_PLL3_PFD2
++ IMX6SX_CLK_PLL3_PFD3 IMX6SX_CLK_PLL4_AUDIO
++ IMX6SX_CLK_PLL5_VIDEO
++ IMX6SX_CLK_OCRAM IMX6SX_CLK_CAN1_SERIAL
++ IMX6SX_CLK_CAN1_IPG IMX6SX_CLK_CAN2_SERIAL
++ IMX6SX_CLK_CAN2_IPG IMX6SX_CLK_CANFD
++ IMX6SX_CLK_ECSPI1 IMX6SX_CLK_ECSPI2
++ IMX6SX_CLK_ECSPI3 IMX6SX_CLK_ECSPI4
++ IMX6SX_CLK_ECSPI5 IMX6SX_CLK_QSPI1
++ IMX6SX_CLK_QSPI2 IMX6SX_CLK_SSI1
++ IMX6SX_CLK_SSI2 IMX6SX_CLK_SSI3
++ IMX6SX_CLK_UART_SERIAL IMX6SX_CLK_UART_IPG
++ IMX6SX_CLK_PERIPH_CLK2_SEL IMX6SX_CLK_OCRAM_ALT_SEL
++ IMX6SX_CLK_I2C1 IMX6SX_CLK_I2C2
++ IMX6SX_CLK_I2C3 IMX6SX_CLK_I2C4
++ IMX6SX_CLK_EPIT1 IMX6SX_CLK_EPIT2>;
++ fsl,shared-mem-addr = <0x91F000>;
++ fsl,shared-mem-size = <0x1000>;
++};
++
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,1121 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include "imx6sx.dtsi"
++
++/ {
++ model = "Freescale i.MX6 SoloX SDB Board";
++ compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
++
++ chosen {
++ stdout-path = &uart1;
++ };
++
++ memory {
++ reg = <0x80000000 0x40000000>;
++ };
++
++ backlight1 {
++ compatible = "pwm-backlight";
++ pwms = <&pwm3 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ fb-names = "mxs-lcdif0";
++ };
++
++ backlight2 {
++ compatible = "pwm-backlight";
++ pwms = <&pwm4 0 5000000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <6>;
++ fb-names = "mxs-lcdif1";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ volume-up {
++ label = "Volume Up";
++ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_VOLUMEUP>;
++ };
++
++ volume-down {
++ label = "Volume Down";
++ gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_VOLUMEDOWN>;
++ };
++ };
++
++ hannstar_cabc {
++ compatible = "hannstar,cabc";
++
++ lvds0 {
++ gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ pxp_v4l2_out {
++ compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
++ status = "okay";
++ };
++
++ regulators {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ reg_lcd_3v3: lcd-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "lcd-3v3";
++ gpio = <&gpio3 27 0>;
++ enable-active-high;
++ status = "disabled";
++ };
++
++ vcc_sd3: regulator@0 {
++ compatible = "regulator-fixed";
++ reg = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_vcc_sd3>;
++ regulator-name = "VCC_SD3";
++ regulator-min-microvolt = <3000000>;
++ regulator-max-microvolt = <3000000>;
++ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_psu_5v: regulator@1 {
++ compatible = "regulator-fixed";
++ reg = <1>;
++ regulator-name = "PSU-5V0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-boot-on;
++ };
++
++ reg_vref_3v3: regulator@2 {
++ compatible = "regulator-fixed";
++ regulator-name = "vref-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ reg_usb_otg1_vbus: regulator@3 {
++ compatible = "regulator-fixed";
++ reg = <3>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usb_otg1>;
++ regulator-name = "usb_otg1_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_usb_otg2_vbus: regulator@4 {
++ compatible = "regulator-fixed";
++ reg = <4>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usb_otg2>;
++ regulator-name = "usb_otg2_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++
++ reg_pcie: regulator@5 {
++ compatible = "regulator-fixed";
++ reg = <5>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie_reg>;
++ regulator-name = "MPCIE_3V3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ gpio = <&gpio2 1 0>;
++ regulator-always-on;
++ enable-active-high;
++ };
++ };
++
++ sound {
++ compatible = "fsl,imx6q-sabresd-wm8962",
++ "fsl,imx-audio-wm8962";
++ model = "wm8962-audio";
++ cpu-dai = <&ssi2>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "Headphone Jack", "HPOUTL",
++ "Headphone Jack", "HPOUTR",
++ "Ext Spk", "SPKOUTL",
++ "Ext Spk", "SPKOUTR",
++ "AMIC", "MICBIAS",
++ "IN3R", "AMIC";
++ mux-int-port = <2>;
++ mux-ext-port = <6>;
++ hp-det-gpios = <&gpio1 17 1>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif",
++ "fsl,imx6sx-sdb-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sii902x_reset: sii902x-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio3 27 1>;
++ reset-delay-us = <100000>;
++ #reset-cells = <0>;
++ status = "disabled";
++ };
++};
++
++&adc1 {
++ vref-supply = <&reg_vref_3v3>;
++ status = "okay";
++};
++
++&adc2 {
++ vref-supply = <&reg_vref_3v3>;
++ status = "okay";
++};
++
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux>;
++ status = "okay";
++};
++
++&csi1 {
++ status = "okay";
++
++ port {
++ csi1_ep: endpoint {
++ remote-endpoint = <&ov5640_ep>;
++ };
++ };
++};
++
++&csi2 {
++ status = "okay";
++ port {
++ csi2_ep: endpoint {
++ remote-endpoint = <&vadc_ep>;
++ };
++ };
++};
++
++&cpu0 {
++ operating-points = <
++ /* kHz uV */
++ 996000 1250000
++ 792000 1175000
++ 396000 1175000
++ 198000 1175000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC uV */
++ 996000 1250000
++ 792000 1175000
++ 396000 1175000
++ 198000 1175000
++ >;
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1a_reg>;
++ fsl,arm-soc-shared = <1>;
++};
++
++&gpc {
++ /* use ldo-bypass, u-boot will check it and configure */
++ fsl,ldo-bypass = <1>;
++};
++
++&lcdif1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_lcdif_dat
++ &pinctrl_lcdif_ctrl>;
++ lcd-supply = <&reg_lcd_3v3>;
++ display = <&display0>;
++ status = "disabled";
++
++ display0: display {
++ bits-per-pixel = <16>;
++ bus-width = <24>;
++
++ display-timings {
++ native-mode = <&timing0>;
++ timing0: timing0 {
++ clock-frequency = <33500000>;
++ hactive = <800>;
++ vactive = <480>;
++ hback-porch = <89>;
++ hfront-porch = <164>;
++ vback-porch = <23>;
++ vfront-porch = <10>;
++ hsync-len = <10>;
++ vsync-len = <10>;
++ hsync-active = <0>;
++ vsync-active = <0>;
++ de-active = <1>;
++ pixelclk-active = <0>;
++ };
++ };
++ };
++};
++
++&lcdif2 {
++ display = <&display1>;
++ disp-dev = "ldb";
++ status = "okay";
++
++ display1: display {
++ bits-per-pixel = <16>;
++ bus-width = <18>;
++ };
++};
++
++&ldb {
++ status = "okay";
++
++ lvds-channel@0 {
++ fsl,data-mapping = "spwg";
++ fsl,data-width = <18>;
++ crtc = "lcdif2";
++ status = "okay";
++
++ display-timings {
++ native-mode = <&timing1>;
++ timing1: hsd100pxn1 {
++ clock-frequency = <65000000>;
++ hactive = <1024>;
++ vactive = <768>;
++ hback-porch = <220>;
++ hfront-porch = <40>;
++ vback-porch = <21>;
++ vfront-porch = <7>;
++ hsync-len = <60>;
++ vsync-len = <10>;
++ };
++ };
++ };
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3>;
++ status = "okay";
++};
++
++&pwm4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm4>;
++ status = "okay";
++};
++
++&dcic1 {
++ dcic_id = <0>;
++ dcic_mux = "dcic-lcdif1";
++ status = "okay";
++};
++
++&dcic2 {
++ dcic_id = <1>;
++ dcic_mux = "dcic-lvds";
++ status = "okay";
++};
++
++&fec1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet1>;
++ pinctrl-assert-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>, <&gpio2 6 GPIO_ACTIVE_LOW>;
++ phy-mode = "rgmii";
++ status = "okay";
++};
++
++&fec2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet2>;
++ phy-mode = "rgmii";
++ status = "okay";
++};
++
++&flexcan1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1>;
++ trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_LOW>;
++ trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&flexcan2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan2>;
++ trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_LOW>;
++ trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio2 0 0>;
++ status = "okay";
++};
++
++&qspi2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_qspi2_1>;
++ status = "okay";
++
++#ifndef SPANSIONFLASH
++ ddrsmp=<0>;
++
++ flash0: n25q256a@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ spi-nor,ddr-quad-read-dummy = <6>;
++ reg = <0>;
++ };
++
++ flash1: n25q256a@1 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q256a";
++ spi-max-frequency = <29000000>;
++ spi-nor,ddr-quad-read-dummy = <6>;
++ reg = <1>;
++ };
++#endif
++};
++
++&pxp {
++ status = "okay";
++};
++
++&sai1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_sai1>;
++ status = "disabled";
++};
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif>;
++ status = "okay";
++};
++
++&ssi2 {
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++&uart5 { /* for bluetooth */
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
++ fsl,uart-has-rtscts;
++ status = "okay";
++ /* for DTE mode, add below change */
++ /* fsl,dte-mode;*/
++ /* pinctrl-0 = <&pinctrl_uart5dte_1>; */
++};
++
++&usbotg1 {
++ vbus-supply = <&reg_usb_otg1_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usb_otg1_id>;
++ status = "okay";
++};
++
++&usbotg2 {
++ vbus-supply = <&reg_usb_otg2_vbus>;
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2>;
++ non-removable;
++ no-1-8-v;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++ bus-width = <8>;
++ cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
++ keep-power-in-suspend;
++ enable-sdio-wakeup;
++ vmmc-supply = <&vcc_sd3>;
++ status = "okay";
++};
++
++&usdhc4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc4>;
++ cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
++ wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ pmic: pfuze100@08 {
++ compatible = "fsl,pfuze200";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ regulator-always-on;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++ ov5640: ov5640@3c {
++ compatible = "ovti,ov5640";
++ reg = <0x3c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_csi_0>;
++ clocks = <&clks IMX6SX_CLK_CSI>;
++ clock-names = "csi_mclk";
++ AVDD-supply = <&vgen3_reg>; /* 2.8v */
++ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
++ pwn-gpios = <&gpio3 28 1>;
++ rst-gpios = <&gpio3 27 0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
++ port {
++ ov5640_ep: endpoint {
++ remote-endpoint = <&csi1_ep>;
++ };
++ };
++ };
++
++ sii902x@39 {
++ compatible = "SiI,sii902x";
++ interrupt-parent = <&gpio4>;
++ interrupts = <21 2>;
++ mode_str ="1280x720M@60";
++ bits-per-pixel = <16>;
++ resets = <&sii902x_reset>;
++ reg = <0x39>;
++ status = "disabled";
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++
++ egalax_ts@04 {
++ compatible = "eeti,egalax_ts";
++ reg = <0x04>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_egalax_int>;
++ interrupt-parent = <&gpio4>;
++ interrupts = <19 2>;
++ wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
++ };
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++
++ mma8451@1c {
++ compatible = "fsl,mma8451";
++ reg = <0x1c>;
++ position = <1>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <2 8>;
++ interrupt-route = <2>;
++ };
++
++ mag3110@0e {
++ compatible = "fsl,mag3110";
++ reg = <0x0e>;
++ position = <2>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <5 1>;
++ shared-interrupt;
++ };
++
++ isl29023@44 {
++ compatible = "fsl,isl29023";
++ reg = <0x44>;
++ rext = <499>;
++ interrupt-parent = <&gpio6>;
++ interrupts = <5 1>;
++ shared-interrupt;
++ };
++};
++
++&i2c4 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c4>;
++ status = "okay";
++
++ codec: wm8962@1a {
++ compatible = "wlf,wm8962";
++ reg = <0x1a>;
++ clocks = <&clks IMX6SX_CLK_AUDIO>;
++ DCVDD-supply = <&vgen4_reg>;
++ DBVDD-supply = <&vgen4_reg>;
++ AVDD-supply = <&vgen4_reg>;
++ CPVDD-supply = <&vgen4_reg>;
++ MICVDD-supply = <&vgen3_reg>;
++ PLLVDD-supply = <&vgen4_reg>;
++ SPKVDD1-supply = <&reg_psu_5v>;
++ SPKVDD2-supply = <&reg_psu_5v>;
++ amic-mono;
++ };
++};
++
++&vadc {
++ vadc_in = <0>;
++ csi_id = <1>;
++ status = "okay";
++ port {
++ vadc_ep: endpoint {
++ remote-endpoint = <&csi2_ep>;
++ };
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>;
++
++ imx6x-sdb {
++ pinctrl_hog: hoggrp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059
++ MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000
++ MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059
++ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
++ MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x17059
++ >;
++ };
++
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
++ MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
++ MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
++ MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
++ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
++ >;
++ };
++
++ pinctrl_canfd1: canfd1grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0
++ MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0
++ >;
++ };
++
++ pinctrl_canfd2: canfd2grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0
++ MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0
++ >;
++ };
++
++ pinctrl_csi_0: csigrp-0 {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0
++ MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0
++ MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0
++ MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0
++ MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0
++ MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0
++ MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0
++ MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0
++ MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0
++ MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0
++ MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0
++ MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0
++ MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0
++ MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000
++ MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000
++ >;
++ };
++
++ pinctrl_egalax_int: egalax_intgrp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000
++ >;
++ };
++
++ pinctrl_enet1: enet1grp {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
++ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
++ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
++ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
++ MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
++ MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
++ MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
++ >;
++ };
++
++ pinctrl_enet2: enet2grp {
++ fsl,pins = <
++ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
++ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
++ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
++ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
++ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
++ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
++ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
++ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
++ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
++ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
++ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
++ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
++ >;
++ };
++
++ pinctrl_flexcan1: flexcan1grp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020
++ MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020
++ >;
++ };
++
++ pinctrl_flexcan2: flexcan2grp {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020
++ MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020
++ >;
++ };
++
++ pinctrl_gpio_keys: gpio_keysgrp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
++ MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
++ >;
++ };
++
++ pinctrl_can_gpios: can-gpios {
++ fsl,pins = <
++ MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059
++ MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
++ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
++ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c4: i2c4grp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
++ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_lcdif_dat: lcdifdatgrp {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
++ MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
++ >;
++ };
++
++ pinctrl_lcdif_ctrl: lcdifctrlgrp {
++ fsl,pins = <
++ MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
++ MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
++ MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
++ MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
++ >;
++ };
++
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_pwm4: pwm4grp {
++ fsl,pins = <
++ MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0
++ >;
++ };
++
++ pinctrl_qspi2_1: qspi2grp_1 {
++ fsl,pins = <
++ MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
++ MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
++ MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
++ MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
++ MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
++ MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
++ MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
++ MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
++ MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
++ MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
++ MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
++ MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
++ >;
++ };
++
++ pinctrl_sai1: sai1grp {
++ fsl,pins = <
++ MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0
++ MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0
++ MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0
++ MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0
++ MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
++ >;
++ };
++
++ pinctrl_spdif: spdifgrp {
++ fsl,pins = <
++ MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0
++ >;
++ };
++
++ pinctrl_pcie: pciegrp {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0
++ >;
++ };
++
++ pinctrl_pcie_reg: pciereggrp {
++ fsl,pins = <
++ MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x10b0
++ >;
++ };
++
++ pinctrl_vcc_sd3: vccsd3grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
++ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5dte_1: uart5dtegrp-1 {
++ fsl,pins = <
++ MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1
++ MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1
++ MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1
++ MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_usb_otg1: usbotg1grp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
++ >;
++ };
++
++ pinctrl_usb_otg1_id: usbotg1idgrp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
++ >;
++ };
++
++ pinctrl_usb_otg2: usbot2ggrp {
++ fsl,pins = <
++ MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
++ MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
++ MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
++ MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
++ MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
++ MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17069
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17069
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17069
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17069
++ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
++ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
++ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
++ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
++ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
++ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
++ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
++ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
++ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
++ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
++ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
++ >;
++ };
++
++ pinctrl_usdhc4: usdhc4grp {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
++ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
++ >;
++ };
++
++ pinctrl_usdhc4_1: usdhc4grp-1 {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
++ >;
++ };
++
++ pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz {
++ fsl,pins = <
++ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
++ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
++ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
++ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
++ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
++ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
++ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
++ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
++ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
++ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
++ >;
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-emmc.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-emmc.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-emmc.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-emmc.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,30 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-sdb.dts"
++
++/*
++ * The eMMC chip on imx6sx sdb board is DNP by default.
++ * Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4
++ * and connect eMMC signals as well as disconnect BOOT SD CARD slot signals
++ */
++&usdhc4 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc4_1>;
++ pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>;
++ bus-width = <8>;
++ /*
++ * overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA
++ * signals after rework
++ */
++ cd-gpios = <>;
++ wp-gpios = <>;
++ non-removable;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-lcdif1.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,35 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-sdb.dts"
++
++/ {
++ regulators {
++ reg_lcd_3v3: lcd-3v3 {
++ status = "okay";
++ };
++ };
++
++ sii902x_reset: sii902x-reset {
++ status = "okay";
++ };
++};
++
++&csi1 {
++ status = "disabled";
++};
++
++&lcdif1 {
++ status = "okay";
++};
++
++&i2c1 {
++ sii902x@39 {
++ status = "okay";
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-ldo.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-ldo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-ldo.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,33 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-sdb.dts"
++
++&cpu0 {
++ operating-points = <
++ /* kHz uV */
++ 996000 1250000
++ 792000 1175000
++ 396000 1075000
++ 198000 975000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC uV */
++ 996000 1175000
++ 792000 1175000
++ 396000 1175000
++ 198000 1175000
++ >;
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++ fsl,arm-soc-shared = <0>;
++};
++
++&gpc {
++ fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-m4.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-m4.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-m4.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-m4.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,93 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-sdb.dts"
++
++/{
++ memory {
++ linux,usable-memory = <0x80000000 0x3ff00000>;
++ reg = <0x80000000 0x40000000>;
++ };
++};
++
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hog>;
++};
++
++/*
++ * The flollowing modules are conflicting with M4, disable them when m4
++ * is running.
++ */
++&flexcan1 {
++ status = "disabled";
++};
++
++&flexcan2 {
++ status = "disabled";
++};
++
++&i2c3 {
++ status = "disabled";
++};
++
++&mcctest{
++ status = "okay";
++};
++
++&mcctty{
++ status = "okay";
++};
++
++&uart2 {
++ status = "disabled";
++};
++
++&adc1 {
++ status = "disabled";
++};
++
++&adc2 {
++ status = "disabled";
++};
++
++&qspi2 {
++ status = "disabled";
++};
++
++&qspi_m4 {
++ status = "okay";
++};
++
++&ocram {
++ reg = <0x00901000 0x1E000>;
++};
++
++&clks {
++ fsl,shared-clks-number = <0x23>;
++ fsl,shared-clks-index = <IMX6SX_CLK_PLL2_BUS IMX6SX_CLK_PLL2_PFD0
++ IMX6SX_CLK_PLL2_PFD2 IMX6SX_CLK_PLL3_USB_OTG
++ IMX6SX_CLK_PLL3_PFD1 IMX6SX_CLK_PLL3_PFD2
++ IMX6SX_CLK_PLL3_PFD3 IMX6SX_CLK_PLL4_AUDIO
++ IMX6SX_CLK_PLL5_VIDEO
++ IMX6SX_CLK_OCRAM IMX6SX_CLK_CAN1_SERIAL
++ IMX6SX_CLK_CAN1_IPG IMX6SX_CLK_CAN2_SERIAL
++ IMX6SX_CLK_CAN2_IPG IMX6SX_CLK_CANFD
++ IMX6SX_CLK_ECSPI1 IMX6SX_CLK_ECSPI2
++ IMX6SX_CLK_ECSPI3 IMX6SX_CLK_ECSPI4
++ IMX6SX_CLK_ECSPI5 IMX6SX_CLK_QSPI1
++ IMX6SX_CLK_QSPI2 IMX6SX_CLK_SSI1
++ IMX6SX_CLK_SSI2 IMX6SX_CLK_SSI3
++ IMX6SX_CLK_UART_SERIAL IMX6SX_CLK_UART_IPG
++ IMX6SX_CLK_PERIPH_CLK2_SEL IMX6SX_CLK_OCRAM_ALT_SEL
++ IMX6SX_CLK_I2C1 IMX6SX_CLK_I2C2
++ IMX6SX_CLK_I2C3 IMX6SX_CLK_I2C4
++ IMX6SX_CLK_EPIT1 IMX6SX_CLK_EPIT2>;
++ fsl,shared-mem-addr = <0x91F000>;
++ fsl,shared-mem-size = <0x1000>;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-reva.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-reva.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-reva.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-reva.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,86 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#define SPANSIONFLASH
++#include "imx6sx-sdb.dts"
++
++/*
++ * The CAN transceiver is changed on RevB board.
++ * This dts is used for support the old CAN transceiver on RevA board
++ */
++
++&cpu0 {
++ operating-points = <
++ /* kHz uV */
++ 996000 1250000
++ 792000 1175000
++ 396000 1075000
++ 198000 975000
++ >;
++ fsl,soc-operating-points = <
++ /* ARM kHz SOC uV */
++ 996000 1175000
++ 792000 1175000
++ 396000 1175000
++ 198000 1175000
++ >;
++ arm-supply = <&sw1a_reg>;
++ soc-supply = <&sw1c_reg>;
++ fsl,arm-soc-shared = <0>;
++};
++
++&flexcan1 {
++ trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
++};
++
++&flexcan2 {
++ trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
++ trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
++};
++
++&pmic {
++ compatible = "fsl,pfuze100";
++
++ regulators {
++ sw1c_reg: sw1c {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++ };
++};
++
++&qspi2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_qspi2_1>;
++ status = "okay";
++ ddrsmp=<0>;
++
++ flash0: s25fl128s@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spansion,s25fl128s";
++ spi-max-frequency = <29000000>;
++ reg = <0>;
++ };
++
++ flash1: s25fl128s@1 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "spansion,s25fl128s";
++ spi-max-frequency = <29000000>;
++ reg = <1>;
++ };
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-reva-ldo.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,18 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-sdb-reva.dts"
++
++&cpu0 {
++ arm-supply = <&reg_arm>;
++ soc-supply = <&reg_soc>;
++};
++
++&gpc {
++ fsl,ldo-bypass = <0>; /* use ldo-enable, u-boot will check it and configure */
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-sai.dts linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-sai.dts
+--- linux-3.14.72.orig/arch/arm/boot/dts/imx6sx-sdb-sai.dts 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/boot/dts/imx6sx-sdb-sai.dts 2016-06-19 22:11:55.033157684 +0200
+@@ -0,0 +1,30 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include "imx6sx-sdb.dts"
++
++/ {
++ sound {
++ cpu-dai = <&sai1>;
++ };
++};
++
++&audmux {
++ /* pin conflict with sai */
++ status = "disabled";
++};
++
++&sai1 {
++ status = "okay";
++};
++
++&sdma {
++ gpr = <&gpr>;
++ /* SDMA event remap for SAI1 */
++ fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
++};
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/Makefile linux-3.14.72/arch/arm/boot/dts/Makefile
+--- linux-3.14.72.orig/arch/arm/boot/dts/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/Makefile 2016-06-19 22:11:55.037157623 +0200
+@@ -153,22 +153,72 @@
+ imx53-mba53.dtb \
+ imx53-qsb.dtb \
+ imx53-smd.dtb \
++ imx6dl-cm-fx6.dtb \
+ imx6dl-cubox-i.dtb \
+ imx6dl-hummingboard.dtb \
++ imx6dl-hummingboard2.dtb \
+ imx6dl-sabreauto.dtb \
++ imx6dl-sabreauto-flexcan1.dtb \
++ imx6dl-sabreauto-ecspi.dtb \
++ imx6dl-sabreauto-gpmi-weim.dtb \
+ imx6dl-sabresd.dtb \
++ imx6dl-sabresd-enetirq.dtb \
++ imx6dl-sabresd-ldo.dtb \
++ imx6dl-sabresd-pf200.dtb \
++ imx6dl-sabresd-hdcp.dtb \
++ imx6dl-udoo.dtb \
++ imx6dl-sbc-fx6.dtb \
++ imx6dl-sbc-fx6m.dtb \
+ imx6dl-wandboard.dtb \
+ imx6q-arm2.dtb \
++ imx6q-auvidea.dtb \
++ imx6q-cm-fx6.dtb \
+ imx6q-cubox-i.dtb \
++ imx6q-hummingboard.dtb \
++ imx6q-hummingboard2.dtb \
+ imx6q-phytec-pbab01.dtb \
+ imx6q-sabreauto.dtb \
++ imx6q-sabreauto-flexcan1.dtb \
++ imx6q-sabreauto-ecspi.dtb \
++ imx6q-sabreauto-gpmi-weim.dtb \
+ imx6q-sabrelite.dtb \
+ imx6q-sabresd.dtb \
++ imx6q-sabresd-ldo.dtb \
++ imx6q-sabresd-enetirq.dtb \
++ imx6q-sabresd-uart.dtb \
++ imx6q-sabresd-hdcp.dtb \
++ imx6q-sabresd-ldo.dtb \
++ imx6q-sbc-fx6.dtb \
++ imx6q-sbc-fx6m.dtb \
+ imx6q-sbc6x.dtb \
+ imx6q-udoo.dtb \
+ imx6q-wandboard.dtb \
++ imx6q-tbs2910.dtb \
+ imx6sl-evk.dtb \
++ imx6sl-evk-csi.dtb \
++ imx6sl-evk-ldo.dtb \
++ imx6sl-evk-pf200.dtb \
++ imx6sl-evk-uart.dtb \
++ imx6sx-17x17-arm2.dtb \
++ imx6sx-17x17-arm2-ldo.dtb \
++ imx6sx-17x17-arm2-ecspi.dtb \
++ imx6sx-17x17-arm2-gpmi-weim.dtb \
++ imx6sx-17x17-arm2-mlb.dtb \
++ imx6sx-19x19-arm2.dtb \
++ imx6sx-19x19-arm2-ldo.dtb \
++ imx6sx-19x19-arm2-csi.dtb \
++ imx6sx-19x19-arm2-lcdif1.dtb \
++ imx6sx-19x19-arm2-gpmi-weim.dtb \
++ imx6sx-sdb.dtb \
++ imx6sx-sdb-ldo.dtb \
++ imx6sx-sdb-reva.dtb \
++ imx6sx-sdb-reva-ldo.dtb \
++ imx6sx-sabreauto.dtb \
++ imx6sx-sabreauto-m4.dtb \
++ imx6sx-sdb-lcdif1.dtb \
+ vf610-cosmic.dtb \
++ imx6sx-sdb-emmc.dtb \
++ imx6sx-sdb-m4.dtb \
+ vf610-twr.dtb
+ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
+ imx23-olinuxino.dtb \
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/marco.dtsi linux-3.14.72/arch/arm/boot/dts/marco.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/marco.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/marco.dtsi 2016-06-19 22:11:55.037157623 +0200
+@@ -36,7 +36,7 @@
+ ranges = <0x40000000 0x40000000 0xa0000000>;
+
+ l2-cache-controller@c0030000 {
+- compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
++ compatible = "arm,pl310-cache";
+ reg = <0xc0030000 0x1000>;
+ interrupts = <0 59 0>;
+ arm,tag-latency = <1 1 1>;
+diff -Nur linux-3.14.72.orig/arch/arm/boot/dts/prima2.dtsi linux-3.14.72/arch/arm/boot/dts/prima2.dtsi
+--- linux-3.14.72.orig/arch/arm/boot/dts/prima2.dtsi 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/boot/dts/prima2.dtsi 2016-06-19 22:11:55.037157623 +0200
+@@ -48,7 +48,7 @@
+ ranges = <0x40000000 0x40000000 0x80000000>;
+
+ l2-cache-controller@80040000 {
+- compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
++ compatible = "arm,pl310-cache";
+ reg = <0x80040000 0x1000>;
+ interrupts = <59>;
+ arm,tag-latency = <1 1 1>;
+diff -Nur linux-3.14.72.orig/arch/arm/configs/cm_fx6_defconfig linux-3.14.72/arch/arm/configs/cm_fx6_defconfig
+--- linux-3.14.72.orig/arch/arm/configs/cm_fx6_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/configs/cm_fx6_defconfig 2016-06-19 22:11:55.037157623 +0200
+@@ -0,0 +1,443 @@
++CONFIG_LOCALVERSION="-cm-fx6"
++CONFIG_KERNEL_LZO=y
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++CONFIG_MXC_DEBUG_BOARD=y
++CONFIG_MACH_IMX51_DT=y
++CONFIG_MACH_EUKREA_CPUIMX51SD=y
++CONFIG_SOC_IMX53=y
++CONFIG_SOC_IMX6Q=y
++CONFIG_SOC_IMX6SL=y
++CONFIG_SOC_IMX6SX=y
++CONFIG_SOC_VF610=y
++# CONFIG_SWP_EMULATE is not set
++CONFIG_PCI=y
++CONFIG_PCI_IMX6=y
++CONFIG_SMP=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_PREEMPT=y
++CONFIG_AEABI=y
++CONFIG_HIGHMEM=y
++CONFIG_CMA=y
++CONFIG_CMDLINE="console=ttymxc3,115200 root=/dev/mmcblk0p1 rootwait"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6Q_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_TEST_SUSPEND=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_DEBUG=y
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
++CONFIG_NETFILTER_XT_TARGET_DSCP=m
++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
++CONFIG_NETFILTER_XT_TARGET_LED=m
++CONFIG_NETFILTER_XT_TARGET_MARK=m
++CONFIG_NETFILTER_XT_TARGET_NFLOG=m
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_TEE=m
++CONFIG_NETFILTER_XT_TARGET_TRACE=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
++CONFIG_NETFILTER_XT_MATCH_CPU=m
++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
++CONFIG_NETFILTER_XT_MATCH_DSCP=m
++CONFIG_NETFILTER_XT_MATCH_ESP=m
++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_HELPER=m
++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
++CONFIG_NETFILTER_XT_MATCH_LENGTH=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MARK=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_OSF=m
++CONFIG_NETFILTER_XT_MATCH_OWNER=m
++CONFIG_NETFILTER_XT_MATCH_POLICY=m
++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
++CONFIG_NETFILTER_XT_MATCH_QUOTA=m
++CONFIG_NETFILTER_XT_MATCH_RATEEST=m
++CONFIG_NETFILTER_XT_MATCH_REALM=m
++CONFIG_NETFILTER_XT_MATCH_RECENT=m
++CONFIG_NETFILTER_XT_MATCH_STATE=m
++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
++CONFIG_NETFILTER_XT_MATCH_STRING=m
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NETFILTER_XT_MATCH_U32=m
++CONFIG_NF_CONNTRACK_IPV4=m
++CONFIG_IP_NF_IPTABLES=y
++CONFIG_IP_NF_MATCH_AH=m
++CONFIG_IP_NF_MATCH_ECN=m
++CONFIG_IP_NF_MATCH_RPFILTER=m
++CONFIG_IP_NF_MATCH_TTL=m
++CONFIG_IP_NF_FILTER=y
++CONFIG_IP_NF_TARGET_REJECT=y
++CONFIG_IP_NF_TARGET_ULOG=m
++CONFIG_NF_NAT_IPV4=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_TARGET_NETMAP=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_TARGET_ECN=m
++CONFIG_IP_NF_TARGET_TTL=m
++CONFIG_IP_NF_RAW=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_IP_NF_ARPFILTER=m
++CONFIG_IP_NF_ARP_MANGLE=m
++CONFIG_VLAN_8021Q=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_CAN=y
++CONFIG_CAN_FLEXCAN=y
++CONFIG_BT=m
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_CFG80211=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_IMX_WEIM=y
++CONFIG_CONNECTOR=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_GPMI_NAND=y
++CONFIG_MTD_NAND_MXC=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_EEPROM_AT24=y
++CONFIG_EEPROM_AT25=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_PATA_IMX=y
++CONFIG_NETDEVICES=y
++CONFIG_TUN=m
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_CS89x0=y
++CONFIG_CS89x0_PLATFORM=y
++# CONFIG_NET_VENDOR_FARADAY is not set
++CONFIG_IGB=m
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_SMC91X=y
++CONFIG_SMC911X=y
++CONFIG_SMSC911X=y
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_ATH_CARDS=y
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_SDIO=m
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_EVDEV=y
++CONFIG_INPUT_EVBUG=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_IMX=y
++CONFIG_MOUSE_PS2=m
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EGALAX=y
++CONFIG_TOUCHSCREEN_ELAN=y
++CONFIG_TOUCHSCREEN_MAX11801=y
++CONFIG_TOUCHSCREEN_MC13783=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_MMA8450=y
++CONFIG_INPUT_ISL29023=y
++CONFIG_SERIO_SERPORT=m
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_FSL_OTP=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX_GPIO=y
++CONFIG_I2C_MUX_PCA954x=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_SABRESD_MAX8903=y
++CONFIG_IMX6_USB_CHARGER=y
++CONFIG_SENSORS_MAX17135=y
++CONFIG_SENSORS_MAG3110=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_MAX17135=y
++CONFIG_MFD_SI476X_CORE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_DA9052=y
++CONFIG_REGULATOR_MAX17135=y
++CONFIG_REGULATOR_MC13783=y
++CONFIG_REGULATOR_MC13892=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_CAPTURE=m
++CONFIG_MXC_CAMERA_OV5640=m
++CONFIG_MXC_CAMERA_OV5642=m
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_VIDEO_MXC_CSI_CAMERA=m
++CONFIG_SOC_CAMERA=y
++CONFIG_VIDEO_MX3=y
++CONFIG_RADIO_SI476X=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB_MXS=y
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_LCD_L4F00242T03=y
++CONFIG_LCD_PLATFORM=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_MIPI_DSI=y
++CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FB_MXC_EINK_PANEL=y
++CONFIG_FB_MXS_SII902X=y
++CONFIG_HANNSTAR_CABC=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_SOC_FSL_ASRC=y
++CONFIG_SND_SOC_FSL_SAI=y
++CONFIG_SND_SOC_FSL_SSI=y
++CONFIG_SND_SOC_FSL_ESAI=y
++CONFIG_SND_SOC_IMX_AUDMUX=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_SND_SOC_CS42XX8_I2C=y
++CONFIG_USB=y
++CONFIG_USB_OTG=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_MXC=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_FSL_USB2=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_AUDIO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++CONFIG_MXC_GPU_VIV=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_MXC_MLB150=m
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_INTF_DEV_UIE_EMUL=y
++CONFIG_RTC_DRV_EM3027=y
++CONFIG_RTC_DRV_MC13XXX=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_STAGING=y
++CONFIG_DRM_IMX=y
++CONFIG_DRM_IMX_FB_HELPER=y
++CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
++CONFIG_DRM_IMX_LDB=y
++CONFIG_DRM_IMX_IPUV3_CORE=y
++CONFIG_DRM_IMX_IPUV3=y
++CONFIG_DRM_IMX_HDMI=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_IMX=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_TEST=m
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++CONFIG_CRYPTO_XTS=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++CONFIG_CRYPTO_RMD128=y
++CONFIG_CRYPTO_RMD160=y
++CONFIG_CRYPTO_RMD256=y
++CONFIG_CRYPTO_RMD320=y
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA256=y
++CONFIG_CRYPTO_SHA512=y
++CONFIG_CRYPTO_TGR192=y
++CONFIG_CRYPTO_WP512=y
++CONFIG_CRYPTO_BLOWFISH=y
++CONFIG_CRYPTO_CAMELLIA=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_TWOFISH=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
+diff -Nur linux-3.14.72.orig/arch/arm/configs/imx_v6_v7_defconfig linux-3.14.72/arch/arm/configs/imx_v6_v7_defconfig
+--- linux-3.14.72.orig/arch/arm/configs/imx_v6_v7_defconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/configs/imx_v6_v7_defconfig 2016-06-19 22:11:55.037157623 +0200
+@@ -87,6 +87,7 @@
+ CONFIG_MTD_NAND=y
+ CONFIG_MTD_NAND_GPMI_NAND=y
+ CONFIG_MTD_NAND_MXC=y
++CONFIG_MTD_SPI_NOR=y
+ CONFIG_MTD_UBI=y
+ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_RAM=y
+diff -Nur linux-3.14.72.orig/arch/arm/configs/imx_v7_cbi_hb_base_defconfig linux-3.14.72/arch/arm/configs/imx_v7_cbi_hb_base_defconfig
+--- linux-3.14.72.orig/arch/arm/configs/imx_v7_cbi_hb_base_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/configs/imx_v7_cbi_hb_base_defconfig 2016-06-19 22:11:55.037157623 +0200
+@@ -0,0 +1,405 @@
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_KERNEL_LZO=y
++CONFIG_SYSVIPC=y
++CONFIG_FHANDLE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++# CONFIG_CGROUP_DEBUG is not set
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CPUSETS=y
++CONFIG_PROC_PID_CPUSET=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_RESOURCE_COUNTERS=y
++CONFIG_MEMCG=y
++CONFIG_MEMCG_SWAP=y
++CONFIG_MEMCG_SWAP_ENABLED=y
++CONFIG_MEMCG_KMEM=y
++# CONFIG_CGROUP_PERF is not set
++CONFIG_CGROUP_SCHED=y
++# CONFIG_CFS_BANDWIDTH is not set
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_BLK_CGROUP=y
++# CONFIG_DEBUG_BLK_CGROUP is not set
++CONFIG_CHECKPOINT_RESTORE=y
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++CONFIG_USER_NS=y
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++CONFIG_CLEANCACHE=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++CONFIG_MXC_DEBUG_BOARD=y
++CONFIG_SOC_IMX6Q=y
++# CONFIG_SOC_IMX6SL is not set
++# CONFIG_SOC_IMX6SX is not set
++# CONFIG_SWP_EMULATE is not set
++CONFIG_PCI=y
++CONFIG_PCIE_DW=y
++CONFIG_PCI_IMX6=y
++CONFIG_SMP=y
++CONFIG_VMSPLIT_3G=y
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_HIGHMEM=y
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
++CONFIG_PM=y
++CONFIG_SUSPEND=y
++# CONFIG_PM_DEBUG is not set
++# CONFIG_PM_TEST_SUSPEND is not set
++CONFIG_IOSCHED_BFQ=y
++CONFIG_CGROUP_BFQIO=y
++CONFIG_DEFAULT_BFQ=y
++CONFIG_DEFAULT_IOSCHED="bfq"
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_VLAN_8021Q=y
++CONFIG_WIRELESS=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_WEXT_CORE=y
++CONFIG_WEXT_PROC=y
++CONFIG_WEXT_SPY=y
++CONFIG_WEXT_PRIV=y
++CONFIG_CFG80211=y
++CONFIG_ETHERNET=y
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_NET_VENDOR_FARADAY
++# CONFIG_NET_VENDOR_INTEL
++# CONFIG_NET_VENDOR_I825XX
++# CONFIG_NET_VENDOR_MARVELL
++# CONFIG_NET_VENDOR_MICROCHIP
++# CONFIG_NET_VENDOR_MICROCHIP=y
++# CONFIG_ENC28J60 is not set
++# CONFIG_NET_VENDOR_NATSEMI=y
++# CONFIG_NET_VENDOR_8390=y
++# CONFIG_AX88796 is not set
++# CONFIG_ETHOC is not set
++# CONFIG_SH_ETH is not set
++# CONFIG_NET_VENDOR_SEEQ=y
++# CONFIG_NET_VENDOR_SMSC=y
++# CONFIG_SMC91X is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SMSC911X is not set
++# CONFIG_NET_VENDOR_STMICRO=y
++# CONFIG_STMMAC_ETH is not set
++# CONFIG_NET_VENDOR_VIA=y
++# CONFIG_VIA_VELOCITY is not set
++# CONFIG_NET_VENDOR_WIZNET=y
++CONFIG_NET_VENDOR_FREESCALE=y
++CONFIG_FEC=y
++CONFIG_PHYLIB=y
++CONFIG_AT803X_PHY=y
++CONFIG_WLAN=y
++CONFIG_BRCMUTIL=m
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_SDIO=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_DMA_CMA=y
++CONFIG_CMA=y
++CONFIG_CMA_SIZE_MBYTES=256
++CONFIG_CONNECTOR=y
++# CONFIG_MTD is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_NETDEVICES=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_IMX=y
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_MOUSE_PS2 is not set
++CONFIG_INPUT_MISC=y
++CONFIG_SERIO_SERPORT=m
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_FSL_OTP=y
++CONFIG_GPIO_MXC=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_SI476X_CORE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++CONFIG_VIDEO_V4L2_INT_DEVICE=y
++# CONFIG_MEDIA_USB_SUPPORT isnot set
++# CONFIG_USB_VIDEO_CLASS is not set
++# CONFIG_RADIO_ADAPTERS is not set
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_CAPTURE=m
++CONFIG_VIDEO_MXC_CSI_CAMERA=m
++CONFIG_MXC_CAMERA_OV5640=m
++CONFIG_MXC_CAMERA_OV5642=m
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_SOC_CAMERA=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_VIVANTE_GALCORE=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB=y
++# CONFIG_FB_MX3 is not set
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_PHY=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++# CONFIG_MXC_GPU_VIV is not set
++CONFIG_MXC_ASRC=y
++CONFIG_MXC_HDMI_CEC=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_MXC_MLB150=m
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_RTC_DRV_PCF8523=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_SRAM=y
++CONFIG_STAGING=y
++CONFIG_COMMON_CLK_DEBUG=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_SYSFS=y
++CONFIG_PWM_IMX=y
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++# CONFIG_IPACK_BUS is not set
++CONFIG_ARCH_HAS_RESET_CONTROLLER=y
++CONFIG_RESET_CONTROLLER=y
++CONFIG_RESET_GPIO=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT23=y
++CONFIG_EXT4_FS_XATTR=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_FANOTIFY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++CONFIG_CRYPTO_CRYPTODEV=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_TEST=m
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++CONFIG_CRYPTO_XTS=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++CONFIG_CRYPTO_RMD128=y
++CONFIG_CRYPTO_RMD160=y
++CONFIG_CRYPTO_RMD256=y
++CONFIG_CRYPTO_RMD320=y
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA256=y
++CONFIG_CRYPTO_SHA512=y
++CONFIG_CRYPTO_TGR192=y
++CONFIG_CRYPTO_WP512=y
++CONFIG_CRYPTO_BLOWFISH=y
++CONFIG_CRYPTO_CAMELLIA=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_TWOFISH=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
++# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
++# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
++# CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST is not set
++# CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO is not set
++# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
++# CONFIG_MXC_MMA8451 is not set
++CONFIG_RC_CORE=m
++CONFIG_RC_DECODERS=y
++CONFIG_LIRC=m
++CONFIG_RC_LOOPBACK=m
++CONFIG_RC_MAP=m
++CONFIG_RC_DEVICES=y
++CONFIG_RC_ATI_REMOTE=m
++CONFIG_IR_NEC_DECODER=m
++CONFIG_IR_RC5_DECODER=m
++CONFIG_IR_RC6_DECODER=m
++CONFIG_IR_JVC_DECODER=m
++CONFIG_IR_SONY_DECODER=m
++CONFIG_IR_RC5_SZ_DECODER=m
++CONFIG_IR_SANYO_DECODER=m
++CONFIG_IR_MCE_KBD_DECODER=m
++CONFIG_IR_LIRC_CODEC=m
++CONFIG_IR_IMON=m
++CONFIG_IR_MCEUSB=m
++CONFIG_IR_ITE_CIR=m
++CONFIG_IR_NUVOTON=m
++CONFIG_IR_FINTEK=m
++CONFIG_IR_REDRAT3=m
++CONFIG_IR_ENE=m
++CONFIG_IR_STREAMZAP=m
++CONFIG_IR_WINBOND_CIR=m
++CONFIG_IR_IGUANA=m
++CONFIG_IR_TTUSBIR=m
++CONFIG_IR_GPIO_CIR=m
+diff -Nur linux-3.14.72.orig/arch/arm/configs/imx_v7_cbi_hb_defconfig linux-3.14.72/arch/arm/configs/imx_v7_cbi_hb_defconfig
+--- linux-3.14.72.orig/arch/arm/configs/imx_v7_cbi_hb_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/configs/imx_v7_cbi_hb_defconfig 2016-06-19 22:11:55.037157623 +0200
+@@ -0,0 +1,5154 @@
++#
++# Automatically generated make config: don't edit
++#
++CONFIG_MMU=y
++CONFIG_HOTPLUG_CPU=y
++# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
++# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
++CONFIG_LOCALVERSION=""
++CONFIG_CROSS_COMPILE=""
++CONFIG_DEFAULT_HOSTNAME="(none)"
++
++#
++# Code maturity level options
++#
++CONFIG_EXPERIMENTAL=y
++CONFIG_HOTPLUG=y
++CONFIG_UEVENT_HELPER_PATH=""
++CONFIG_PREVENT_FIRMWARE_BUILD=y
++
++CONFIG_BUILD_DOCSRC=y
++
++#
++# General setup
++#
++CONFIG_KERNEL_LZO=y
++# CONFIG_KERNEL_BZIP2 is not set
++# CONFIG_KERNEL_LZMA is not set
++CONFIG_SWAP=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++# CONFIG_COMPILE_TEST is not set
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_SYSCTL=y
++# CONFIG_IKCONFIG is not set
++# CONFIG_EMBEDDED is not set
++CONFIG_KALLSYMS=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_FUTEX=y
++CONFIG_EPOLL=y
++CONFIG_IOSCHED_NOOP=y
++CONFIG_IOSCHED_DEADLINE=y
++CONFIG_IOSCHED_CFQ=y
++CONFIG_CFQ_GROUP_IOSCHED=y
++CONFIG_IOSCHED_BFQ=y
++CONFIG_CGROUP_BFQIO=y
++CONFIG_DEFAULT_BFQ=y
++CONFIG_DEFAULT_IOSCHED="bfq"
++# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set
++CONFIG_SYSVIPC=y
++CONFIG_FHANDLE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++# CONFIG_CGROUP_DEBUG is not set
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CPUSETS=y
++CONFIG_PROC_PID_CPUSET=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_RESOURCE_COUNTERS=y
++CONFIG_MEMCG=y
++CONFIG_MEMCG_SWAP=y
++CONFIG_MEMCG_SWAP_ENABLED=y
++CONFIG_MEMCG_KMEM=y
++# CONFIG_CGROUP_PERF is not set
++CONFIG_CGROUP_SCHED=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_BLK_CGROUP=y
++# CONFIG_DEBUG_BLK_CGROUP is not set
++CONFIG_CHECKPOINT_RESTORE=y
++CONFIG_NAMESPACES=y
++CONFIG_UTS_NS=y
++CONFIG_IPC_NS=y
++CONFIG_USER_NS=y
++CONFIG_PID_NS=y
++CONFIG_NET_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++
++CONFIG_POSIX_MQUEUE=y
++CONFIG_PREEMPT_VOLUNTARY=y
++
++CONFIG_SLUB=y
++CONFIG_SLUB_CPU_PARTIAL=y
++# CONFIG_SLUB_STATS is not set
++# CONFIG_SLUB_DEBUG_ON is not set
++
++# CONFIG_AD525X_DPOT is not set
++# CONFIG_ATMEL_PWM is not set
++# CONFIG_IWMC3200TOP is not set
++# CONFIG_BLK_DEV_BSG is not set
++
++# MX6 specific kernel configuration
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++CONFIG_MXC_DEBUG_BOARD=y
++CONFIG_SOC_IMX6Q=y
++# CONFIG_SOC_IMX6SL is not set
++# CONFIG_SOC_IMX6SX is not set
++# CONFIG_SWP_EMULATE is not set
++CONFIG_PCI=y
++CONFIG_PCIE_DW=y
++CONFIG_PCI_IMX6=y
++CONFIG_SMP=y
++CONFIG_VMSPLIT_3G=y
++CONFIG_AEABI=y
++# CONFIG_OABI_COMPAT is not set
++CONFIG_HIGHMEM=y
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_VFPv3=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_BINFMT_MISC=m
++# CONFIG_PM_DEBUG is not set
++# CONFIG_PM_TEST_SUSPEND is not set
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_VLAN_8021Q=y
++CONFIG_WIRELESS=y
++CONFIG_WIRELESS_EXT=y
++CONFIG_WEXT_CORE=y
++CONFIG_WEXT_PROC=y
++CONFIG_WEXT_SPY=y
++CONFIG_WEXT_PRIV=y
++CONFIG_CFG80211=y
++CONFIG_ETHERNET=y
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_NET_VENDOR_FARADAY
++# CONFIG_NET_VENDOR_INTEL
++# CONFIG_NET_VENDOR_I825XX
++# CONFIG_NET_VENDOR_MARVELL
++# CONFIG_NET_VENDOR_MICROCHIP
++# CONFIG_NET_VENDOR_MICROCHIP=y
++# CONFIG_ENC28J60 is not set
++# CONFIG_NET_VENDOR_NATSEMI=y
++# CONFIG_NET_VENDOR_8390=y
++# CONFIG_AX88796 is not set
++# CONFIG_ETHOC is not set
++# CONFIG_SH_ETH is not set
++# CONFIG_NET_VENDOR_SEEQ=y
++# CONFIG_NET_VENDOR_SMSC=y
++# CONFIG_SMC91X is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SMSC911X is not set
++# CONFIG_NET_VENDOR_STMICRO=y
++# CONFIG_STMMAC_ETH is not set
++# CONFIG_NET_VENDOR_VIA=y
++# CONFIG_VIA_VELOCITY is not set
++# CONFIG_NET_VENDOR_WIZNET=y
++CONFIG_NET_VENDOR_FREESCALE=y
++CONFIG_FEC=y
++CONFIG_PHYLIB=y
++CONFIG_AT803X_PHY=y
++CONFIG_WLAN=y
++CONFIG_BRCMUTIL=m
++CONFIG_BRCMFMAC=m
++CONFIG_BRCMFMAC_SDIO=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_DMA_CMA=y
++CONFIG_CMA=y
++CONFIG_CMA_SIZE_MBYTES=256
++CONFIG_CONNECTOR=y
++# CONFIG_MTD is not set
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_NETDEVICES=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_INPUT_EVBUG is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_IMX=y
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++# CONFIG_KEYBOARD_ATKBD is not set
++# CONFIG_MOUSE_PS2 is not set
++CONFIG_INPUT_MISC=y
++CONFIG_SERIO_SERPORT=m
++CONFIG_VT_HW_CONSOLE_BINDING=y
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_FSL_OTP=y
++CONFIG_GPIO_MXC=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_SI476X_CORE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++# CONFIG_MEDIA_RADIO_SUPPORT is not set
++CONFIG_VIDEO_V4L2_INT_DEVICE=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++# CONFIG_RADIO_ADAPTERS is not set
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_CAPTURE=m
++CONFIG_VIDEO_MXC_CSI_CAMERA=m
++# CONFIG_MXC_CAMERA_OV5640 is not set
++# CONFIG_MXC_CAMERA_OV5642 is not set
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_CAMERA_OV5647_MIPI=m
++CONFIG_MXC_HDMI_CSI2_TC358743=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_SOC_CAMERA=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_VIVANTE_GALCORE=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB=y
++# CONFIG_FB_MX3 is not set
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_PHY=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++# CONFIG_MXC_GPU_VIV is not set
++CONFIG_MXC_ASRC=y
++CONFIG_MXC_HDMI_CEC=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_MXC_MLB150=m
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_RTC_DRV_PCF8523=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_SRAM=y
++CONFIG_STAGING=y
++CONFIG_COMMON_CLK_DEBUG=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_SYSFS=y
++CONFIG_PWM_IMX=y
++CONFIG_IRQCHIP=y
++CONFIG_ARM_GIC=y
++CONFIG_ARCH_HAS_RESET_CONTROLLER=y
++CONFIG_RESET_CONTROLLER=y
++CONFIG_RESET_GPIO=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_USE_FOR_EXT23=y
++CONFIG_EXT4_FS_XATTR=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++CONFIG_CRYPTO_TEST=m
++CONFIG_CRYPTO_CCM=y
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_ECB=y
++CONFIG_CRYPTO_LRW=y
++CONFIG_CRYPTO_XTS=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++CONFIG_CRYPTO_RMD128=y
++CONFIG_CRYPTO_RMD160=y
++CONFIG_CRYPTO_RMD256=y
++CONFIG_CRYPTO_RMD320=y
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA256=y
++CONFIG_CRYPTO_SHA512=y
++CONFIG_CRYPTO_TGR192=y
++CONFIG_CRYPTO_WP512=y
++CONFIG_CRYPTO_BLOWFISH=y
++CONFIG_CRYPTO_CAMELLIA=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_TWOFISH=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
++# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
++# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
++# CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST is not set
++# CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO is not set
++# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
++# CONFIG_MXC_MMA8451 is not set
++
++CONFIG_XZ_DEC=y
++# CONFIG_XZ_DEC_X86 is not set
++# CONFIG_XZ_DEC_POWERPC is not set
++# CONFIG_XZ_DEC_IA64 is not set
++CONFIG_XZ_DEC_ARM=y
++CONFIG_XZ_DEC_ARMTHUMB=y
++# CONFIG_XZ_DEC_SPARC is not set
++CONFIG_XZ_DEC_BCJ=y
++# CONFIG_XZ_DEC_TEST is not set
++CONFIG_DECOMPRESS_GZIP=y
++
++#
++# Loadable module support
++#
++# CONFIG_MODULE_FORCE_LOAD is not set
++# -- MODULE_FORCE_UNLOAD is controlled by config-debug/nodebug
++
++# CONFIG_PCI_DEBUG is not set
++CONFIG_PCI_STUB=y
++CONFIG_PCI_IOV=y
++CONFIG_PCI_PRI=y
++CONFIG_PCI_PASID=y
++CONFIG_HT_IRQ=y
++CONFIG_PCI_MSI=y
++# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
++CONFIG_PCIEPORTBUS=y
++CONFIG_PCIEAER=y
++CONFIG_PCIEASPM=y
++# CONFIG_PCIEASPM_DEBUG is not set
++CONFIG_PCIE_ECRC=y
++CONFIG_PCIEAER_INJECT=m
++CONFIG_HOTPLUG_PCI_PCIE=y
++CONFIG_HOTPLUG_PCI_FAKE=m
++
++# CONFIG_SGI_IOC4 is not set
++
++# CONFIG_ISA is not set
++# CONFIG_SCx200 is not set
++
++#
++# PCMCIA/CardBus support
++# FIXME: Deprecate Cardbus ?
++#
++CONFIG_PCMCIA=y
++CONFIG_PCMCIA_LOAD_CIS=y
++# CONFIG_PCMCIA_DEBUG is not set
++CONFIG_YENTA=m
++CONFIG_CARDBUS=y
++CONFIG_I82092=m
++CONFIG_PD6729=m
++
++CONFIG_PCCARD=y
++CONFIG_SDIO_UART=m
++# CONFIG_MMC_TEST is not set
++# CONFIG_MMC_DEBUG is not set
++# https://lists.fedoraproject.org/pipermail/kernel/2014-February/004889.html
++# CONFIG_MMC_CLKGATE is not set
++CONFIG_MMC_BLOCK=y
++CONFIG_MMC_BLOCK_MINORS=8
++CONFIG_MMC_BLOCK_BOUNCE=y
++CONFIG_MMC_SDHCI_PCI=m
++CONFIG_MMC_SDHCI_ACPI=m
++CONFIG_MMC_SDRICOH_CS=m
++CONFIG_MMC_TIFM_SD=m
++CONFIG_MMC_WBSD=m
++CONFIG_MMC_VIA_SDMMC=m
++CONFIG_MMC_CB710=m
++CONFIG_MMC_RICOH_MMC=y
++CONFIG_MMC_USHC=m
++CONFIG_MMC_REALTEK_PCI=m
++CONFIG_MMC_VUB300=m
++# CONFIG_MMC_SDHCI_PXAV2 is not set
++# CONFIG_MMC_SDHCI_PXAV3 is not set
++# CONFIG_MMC_SDHCI_OF_ARASAN is not set
++
++
++CONFIG_CB710_CORE=m
++# CONFIG_CB710_DEBUG is not set
++
++CONFIG_INFINIBAND=m
++CONFIG_INFINIBAND_MTHCA=m
++# CONFIG_INFINIBAND_MTHCA_DEBUG is not set
++CONFIG_INFINIBAND_IPOIB=m
++CONFIG_INFINIBAND_IPOIB_DEBUG=y
++CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
++CONFIG_INFINIBAND_IPOIB_CM=y
++CONFIG_INFINIBAND_SRP=m
++CONFIG_INFINIBAND_SRPT=m
++CONFIG_INFINIBAND_USER_MAD=m
++CONFIG_INFINIBAND_USER_ACCESS=m
++# CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING is not set #staging
++CONFIG_INFINIBAND_IPATH=m
++CONFIG_INFINIBAND_ISER=m
++CONFIG_INFINIBAND_ISERT=m
++CONFIG_INFINIBAND_AMSO1100=m
++# CONFIG_INFINIBAND_AMSO1100_DEBUG is not set
++CONFIG_INFINIBAND_CXGB3=m
++CONFIG_INFINIBAND_CXGB4=m
++CONFIG_SCSI_CXGB3_ISCSI=m
++CONFIG_SCSI_CXGB4_ISCSI=m
++# CONFIG_INFINIBAND_CXGB3_DEBUG is not set
++CONFIG_MLX4_INFINIBAND=m
++CONFIG_MLX5_INFINIBAND=m
++CONFIG_INFINIBAND_NES=m
++# CONFIG_INFINIBAND_NES_DEBUG is not set
++CONFIG_INFINIBAND_QIB=m
++CONFIG_INFINIBAND_QIB_DCA=y
++# CONFIG_INFINIBAND_OCRDMA is not set
++# CONFIG_INFINIBAND_USNIC is not set
++
++#
++# Executable file formats
++#
++CONFIG_BINFMT_ELF=y
++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
++# CONFIG_BINFMT_AOUT is not set
++CONFIG_BINFMT_SCRIPT=y
++
++#
++# Device Drivers
++#
++
++# CONFIG_COMMON_CLK_SI5351 is not set
++
++#
++# Generic Driver Options
++#
++CONFIG_FW_LOADER=y
++# CONFIG_FIRMWARE_IN_KERNEL is not set
++CONFIG_EXTRA_FIRMWARE=""
++
++# Give this a try in rawhide for now
++# CONFIG_FW_LOADER_USER_HELPER is not set
++
++
++
++#
++# Memory Technology Devices (MTD)
++#
++# CONFIG_MTD_TESTS is not set
++# CONFIG_MTD_REDBOOT_PARTS is not set
++# CONFIG_MTD_AR7_PARTS is not set
++# CONFIG_MTD_CMDLINE_PARTS is not set
++
++#
++# User Modules And Translation Layers
++#
++# CONFIG_MTD_CHAR is not set
++# CONFIG_MTD_BLKDEVS is not set
++# CONFIG_MTD_BLOCK is not set
++# CONFIG_MTD_BLOCK_RO is not set
++# CONFIG_FTL is not set
++# CONFIG_NFTL is not set
++# CONFIG_INFTL is not set
++# CONFIG_RFD_FTL is not set
++# CONFIG_SSFDC is not set
++# CONFIG_SM_FTL is not set
++# CONFIG_MTD_OOPS is not set
++# CONFIG_MTD_SWAP is not set
++
++#
++# RAM/ROM/Flash chip drivers
++#
++# CONFIG_MTD_CFI is not set
++# CONFIG_MTD_JEDECPROBE is not set
++CONFIG_MTD_MAP_BANK_WIDTH_1=y
++CONFIG_MTD_MAP_BANK_WIDTH_2=y
++CONFIG_MTD_MAP_BANK_WIDTH_4=y
++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
++CONFIG_MTD_CFI_I1=y
++CONFIG_MTD_CFI_I2=y
++# CONFIG_MTD_CFI_I4 is not set
++# CONFIG_MTD_CFI_I8 is not set
++# CONFIG_MTD_RAM is not set
++# CONFIG_MTD_ROM is not set
++# CONFIG_MTD_ABSENT is not set
++
++#
++# Mapping drivers for chip access
++#
++# CONFIG_MTD_COMPLEX_MAPPINGS is not set
++# CONFIG_MTD_TS5500 is not set
++# CONFIG_MTD_INTEL_VR_NOR is not set
++# CONFIG_MTD_PLATRAM is not set
++
++# Self-contained MTD device drivers
++# CONFIG_MTD_PMC551 is not set
++# CONFIG_MTD_SLRAM is not set
++# CONFIG_MTD_PHRAM is not set
++# CONFIG_MTD_MTDRAM is not set
++# CONFIG_MTD_BLOCK2MTD is not set
++
++#
++# Disk-On-Chip Device Drivers
++#
++# CONFIG_MTD_DOCG3 is not set
++# CONFIG_MTD_NAND is not set
++# CONFIG_MTD_ONENAND is not set
++# CONFIG_MTD_NAND_VERIFY_WRITE is not set
++# CONFIG_MTD_NAND_ECC_BCH is not set
++# CONFIG_MTD_NAND_MUSEUM_IDS is not set
++# CONFIG_MTD_NAND_DISKONCHIP is not set
++# CONFIG_MTD_LPDDR is not set
++CONFIG_MTD_UBI=m
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_MTD_UBI_GLUEBI is not set
++
++#
++# Parallel port support
++#
++CONFIG_PARPORT=m
++CONFIG_PARPORT_PC=m
++CONFIG_PARPORT_SERIAL=m
++# CONFIG_PARPORT_PC_FIFO is not set
++# CONFIG_PARPORT_PC_SUPERIO is not set
++CONFIG_PARPORT_PC_PCMCIA=m
++CONFIG_PARPORT_1284=y
++# CONFIG_PARPORT_AX88796 is not set
++
++CONFIG_ACPI_PCI_SLOT=y
++CONFIG_HOTPLUG_PCI_ACPI=y
++CONFIG_HOTPLUG_PCI_ACPI_IBM=m
++
++#
++# Block devices
++#
++CONFIG_BLK_DEV=y
++CONFIG_BLK_DEV_NULL_BLK=m
++CONFIG_BLK_DEV_FD=m
++# CONFIG_PARIDE is not set
++CONFIG_ZRAM=m
++# CONFIG_ZRAM_DEBUG is not set
++CONFIG_ENHANCEIO=m
++
++CONFIG_BLK_CPQ_DA=m
++CONFIG_BLK_CPQ_CISS_DA=m
++CONFIG_CISS_SCSI_TAPE=y
++CONFIG_BLK_DEV_DAC960=m
++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
++CONFIG_BLK_DEV_DRBD=m
++CONFIG_BLK_DEV_UMEM=m
++CONFIG_BLK_DEV_LOOP_MIN_COUNT=0
++# Fedora 18 util-linux is the last release that supports cryptoloop devices
++# CONFIG_BLK_DEV_CRYPTOLOOP is not set
++CONFIG_BLK_DEV_NBD=m
++CONFIG_BLK_DEV_NVME=m
++CONFIG_BLK_DEV_SKD=m # 64-bit only but easier to put here
++CONFIG_BLK_DEV_OSD=m
++CONFIG_BLK_DEV_RAM_COUNT=16
++CONFIG_BLK_DEV_IO_TRACE=y
++
++CONFIG_BLK_DEV_BSGLIB=y
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_THROTTLING=y
++# CONFIG_BLK_CMDLINE_PARSER is not set
++
++
++#
++# ATA/ATAPI/MFM/RLL support
++#
++# CONFIG_IDE is not set
++
++# CONFIG_BLK_DEV_HD is not set
++# CONFIG_BLK_DEV_RSXX is not set
++
++CONFIG_SCSI_VIRTIO=m
++CONFIG_VIRTIO_BLK=m
++CONFIG_VIRTIO_PCI=m
++CONFIG_VIRTIO_BALLOON=m
++CONFIG_VIRTIO_MMIO=m
++# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
++CONFIG_VIRTIO_NET=m
++CONFIG_HW_RANDOM_VIRTIO=m
++CONFIG_VIRTIO_CONSOLE=m
++CONFIG_VHOST_NET=m
++CONFIG_TCM_VHOST=m
++CONFIG_VHOST_SCSI=m
++
++#
++# SCSI device support
++#
++CONFIG_SCSI=y
++
++CONFIG_SCSI_ENCLOSURE=m
++CONFIG_SCSI_SRP=m
++CONFIG_SCSI_SRP_ATTRS=m
++CONFIG_SCSI_TGT=m
++CONFIG_SCSI_ISCI=m
++CONFIG_SCSI_CHELSIO_FCOE=m
++
++CONFIG_SCSI_DH=y
++CONFIG_SCSI_DH_RDAC=m
++CONFIG_SCSI_DH_HP_SW=m
++CONFIG_SCSI_DH_EMC=m
++CONFIG_SCSI_DH_ALUA=m
++
++#
++# SCSI support type (disk, tape, CD-ROM)
++#
++CONFIG_CHR_DEV_ST=m
++CONFIG_CHR_DEV_OSST=m
++CONFIG_BLK_DEV_SR=y
++CONFIG_BLK_DEV_SR_VENDOR=y
++CONFIG_CHR_DEV_SG=y
++CONFIG_CHR_DEV_SCH=m
++
++#
++# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
++#
++CONFIG_SCSI_SPI_ATTRS=m
++CONFIG_SCSI_FC_ATTRS=m
++CONFIG_SCSI_FC_TGT_ATTRS=y
++CONFIG_SCSI_ISCSI_ATTRS=m
++CONFIG_SCSI_SAS_ATTRS=m
++CONFIG_SCSI_SRP_TGT_ATTRS=y
++CONFIG_SCSI_SAS_LIBSAS=m
++CONFIG_SCSI_SAS_ATA=y
++CONFIG_SCSI_SAS_HOST_SMP=y
++CONFIG_RAID_ATTRS=m
++
++CONFIG_ISCSI_TCP=m
++CONFIG_ISCSI_BOOT_SYSFS=m
++
++#
++# SCSI low-level drivers
++#
++CONFIG_BLK_DEV_3W_XXXX_RAID=m
++CONFIG_SCSI_3W_9XXX=m
++CONFIG_SCSI_ACARD=m
++CONFIG_SCSI_AACRAID=m
++CONFIG_SCSI_AIC7XXX=m
++# http://lists.fedoraproject.org/pipermail/kernel/2013-February/004102.html
++# CONFIG_SCSI_AIC7XXX_OLD is not set
++CONFIG_AIC7XXX_CMDS_PER_DEVICE=4
++CONFIG_AIC7XXX_RESET_DELAY_MS=15000
++# CONFIG_AIC7XXX_BUILD_FIRMWARE is not set
++# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
++CONFIG_AIC7XXX_DEBUG_MASK=0
++# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set
++CONFIG_SCSI_AIC79XX=m
++CONFIG_AIC79XX_CMDS_PER_DEVICE=4
++CONFIG_AIC79XX_RESET_DELAY_MS=15000
++# CONFIG_AIC79XX_BUILD_FIRMWARE is not set
++# CONFIG_AIC79XX_DEBUG_ENABLE is not set
++CONFIG_AIC79XX_DEBUG_MASK=0
++# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set
++CONFIG_SCSI_AIC94XX=m
++# CONFIG_AIC94XX_DEBUG is not set
++# CONFIG_SCSI_ADVANSYS is not set
++CONFIG_SCSI_BFA_FC=m
++CONFIG_MEGARAID_NEWGEN=y
++CONFIG_MEGARAID_MM=m
++CONFIG_MEGARAID_MAILBOX=m
++CONFIG_MEGARAID_LEGACY=m
++CONFIG_MEGARAID_SAS=m
++CONFIG_SCSI_ESAS2R=m
++CONFIG_SCSI_MVSAS=m
++# CONFIG_SCSI_MVSAS_DEBUG is not set
++CONFIG_SCSI_MVSAS_TASKLET=y
++CONFIG_SCSI_MPT2SAS=m
++CONFIG_SCSI_MPT2SAS_MAX_SGE=128
++CONFIG_SCSI_MPT2SAS_LOGGING=y
++CONFIG_SCSI_MPT3SAS=m
++CONFIG_SCSI_MPT3SAS_MAX_SGE=128
++CONFIG_SCSI_MPT3SAS_LOGGING=y
++
++CONFIG_SCSI_UFSHCD=m
++CONFIG_SCSI_UFSHCD_PCI=m
++# CONFIG_SCSI_UFSHCD_PLATFORM is not set
++
++CONFIG_SCSI_MVUMI=m
++
++CONFIG_SCSI_OSD_INITIATOR=m
++CONFIG_SCSI_OSD_ULD=m
++CONFIG_SCSI_OSD_DPRINT_SENSE=1
++# CONFIG_SCSI_OSD_DEBUG is not set
++
++CONFIG_SCSI_BNX2_ISCSI=m
++CONFIG_SCSI_BNX2X_FCOE=m
++CONFIG_BE2ISCSI=m
++CONFIG_SCSI_PMCRAID=m
++
++CONFIG_SCSI_HPSA=m
++CONFIG_SCSI_3W_SAS=m
++CONFIG_SCSI_PM8001=m
++CONFIG_VMWARE_PVSCSI=m
++CONFIG_VMWARE_BALLOON=m
++
++CONFIG_SCSI_ARCMSR=m
++CONFIG_SCSI_BUSLOGIC=m
++CONFIG_SCSI_INITIO=m
++CONFIG_SCSI_FLASHPOINT=y
++CONFIG_SCSI_DMX3191D=m
++# CONFIG_SCSI_EATA is not set
++# CONFIG_SCSI_EATA_PIO is not set
++# CONFIG_SCSI_FUTURE_DOMAIN is not set
++CONFIG_SCSI_GDTH=m
++CONFIG_SCSI_HPTIOP=m
++CONFIG_SCSI_IPS=m
++CONFIG_SCSI_INIA100=m
++# CONFIG_SCSI_PPA is not set
++# CONFIG_SCSI_IMM is not set
++# CONFIG_SCSI_IZIP_EPP16 is not set
++# CONFIG_SCSI_IZIP_SLOW_CTR is not set
++CONFIG_SCSI_STEX=m
++CONFIG_SCSI_SYM53C8XX_2=m
++CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
++CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
++CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
++CONFIG_SCSI_SYM53C8XX_MMIO=y
++CONFIG_SCSI_QLOGIC_1280=m
++CONFIG_SCSI_DC395x=m
++# CONFIG_SCSI_NSP32 is not set
++CONFIG_SCSI_DEBUG=m
++CONFIG_SCSI_DC390T=m
++CONFIG_SCSI_QLA_FC=m
++CONFIG_TCM_QLA2XXX=m
++CONFIG_SCSI_QLA_ISCSI=m
++CONFIG_SCSI_IPR=m
++CONFIG_SCSI_IPR_TRACE=y
++CONFIG_SCSI_IPR_DUMP=y
++# CONFIG_SCSI_DPT_I2O is not set
++CONFIG_SCSI_LPFC=m
++# CONFIG_SCSI_LPFC_DEBUG_FS is not set
++
++# PCMCIA SCSI adapter support
++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
++
++CONFIG_ATA_BMDMA=y
++CONFIG_ATA_VERBOSE_ERROR=y
++CONFIG_ATA_SFF=y
++CONFIG_ATA_PIIX=y
++# CONFIG_SATA_HIGHBANK is not set
++CONFIG_ATA_ACPI=y
++CONFIG_BLK_DEV_SX8=m
++CONFIG_PDC_ADMA=m
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_INIC162X=m
++CONFIG_SATA_MV=m
++CONFIG_SATA_NV=m
++CONFIG_SATA_PMP=y
++CONFIG_SATA_PROMISE=m
++CONFIG_SATA_QSTOR=m
++CONFIG_SATA_RCAR=m
++CONFIG_SATA_SIL=m
++CONFIG_SATA_SIL24=m
++CONFIG_SATA_SIS=m
++CONFIG_SATA_SVW=m
++CONFIG_SATA_SX4=m
++CONFIG_SATA_ULI=m
++CONFIG_SATA_VIA=m
++CONFIG_SATA_VITESSE=m
++# CONFIG_SATA_ZPODD is not set
++CONFIG_SATA_ACARD_AHCI=m
++
++# CONFIG_PATA_LEGACY is not set
++CONFIG_PATA_ACPI=m
++CONFIG_PATA_ALI=m
++CONFIG_PATA_AMD=m
++CONFIG_PATA_ARASAN_CF=m
++CONFIG_PATA_ARTOP=m
++CONFIG_PATA_ATIIXP=m
++CONFIG_PATA_CMD640_PCI=m
++CONFIG_PATA_CMD64X=m
++CONFIG_PATA_CS5520=m
++CONFIG_PATA_CS5530=m
++CONFIG_PATA_CS5535=m
++CONFIG_PATA_CS5536=m
++CONFIG_PATA_CYPRESS=m
++CONFIG_PATA_EFAR=m
++CONFIG_ATA_GENERIC=m
++CONFIG_PATA_HPT366=m
++CONFIG_PATA_HPT37X=m
++CONFIG_PATA_HPT3X2N=m
++CONFIG_PATA_HPT3X3=m
++# CONFIG_PATA_HPT3X3_DMA is not set
++CONFIG_PATA_IT821X=m
++CONFIG_PATA_IT8213=m
++CONFIG_PATA_JMICRON=m
++CONFIG_PATA_NINJA32=m
++CONFIG_PATA_MARVELL=m
++CONFIG_PATA_MPIIX=m
++CONFIG_PATA_NETCELL=m
++CONFIG_PATA_NS87410=m
++CONFIG_PATA_NS87415=m
++CONFIG_PATA_OLDPIIX=m
++CONFIG_PATA_OPTI=m
++CONFIG_PATA_OPTIDMA=m
++CONFIG_PATA_PCMCIA=m
++CONFIG_PATA_PDC_OLD=m
++# CONFIG_PATA_RADISYS is not set
++CONFIG_PATA_RDC=m
++# CONFIG_PATA_RZ1000 is not set
++# CONFIG_PATA_SC1200 is not set
++CONFIG_PATA_SERVERWORKS=m
++CONFIG_PATA_PDC2027X=m
++CONFIG_PATA_SCH=m
++CONFIG_PATA_SIL680=m
++CONFIG_PATA_SIS=m
++CONFIG_PATA_TOSHIBA=m
++CONFIG_PATA_TRIFLEX=m
++CONFIG_PATA_VIA=m
++CONFIG_PATA_WINBOND=m
++CONFIG_PATA_ATP867X=m
++
++
++#
++# Multi-device support (RAID and LVM)
++#
++CONFIG_MD=y
++CONFIG_BLK_DEV_MD=y
++CONFIG_MD_AUTODETECT=y
++CONFIG_MD_FAULTY=m
++CONFIG_MD_LINEAR=m
++CONFIG_MD_MULTIPATH=m
++CONFIG_MD_RAID0=m
++CONFIG_MD_RAID1=m
++CONFIG_MD_RAID10=m
++CONFIG_MD_RAID456=m
++
++CONFIG_BCACHE=m
++# CONFIG_BCACHE_DEBUG is not set
++# CONFIG_BCACHE_EDEBUG is not set
++# CONFIG_BCACHE_CLOSURES_DEBUG is not set
++
++# CONFIG_MULTICORE_RAID456 is not set
++CONFIG_ASYNC_RAID6_TEST=m
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=m
++CONFIG_DM_DEBUG=y
++CONFIG_DM_DELAY=m
++CONFIG_DM_MIRROR=y
++CONFIG_DM_MULTIPATH=m
++CONFIG_DM_SNAPSHOT=y
++CONFIG_DM_THIN_PROVISIONING=m
++CONFIG_DM_CACHE=m
++CONFIG_DM_CACHE_MQ=m
++CONFIG_DM_CACHE_CLEANER=m
++# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set
++# CONFIG_DM_DEBUG_SPACE_MAPS is not set
++CONFIG_DM_UEVENT=y
++CONFIG_DM_ZERO=y
++CONFIG_DM_LOG_USERSPACE=m
++CONFIG_DM_MULTIPATH_QL=m
++CONFIG_DM_MULTIPATH_ST=m
++CONFIG_DM_RAID=m
++CONFIG_DM_FLAKEY=m
++CONFIG_DM_VERITY=m
++CONFIG_DM_SWITCH=m
++
++#
++# Fusion MPT device support
++#
++CONFIG_FUSION=y
++CONFIG_FUSION_SPI=m
++CONFIG_FUSION_FC=m
++CONFIG_FUSION_MAX_SGE=40
++CONFIG_FUSION_CTL=m
++CONFIG_FUSION_LAN=m
++CONFIG_FUSION_SAS=m
++CONFIG_FUSION_LOGGING=y
++
++#
++# IEEE 1394 (FireWire) support (JUJU alternative stack)
++#
++CONFIG_FIREWIRE=m
++CONFIG_FIREWIRE_OHCI=m
++CONFIG_FIREWIRE_SBP2=m
++CONFIG_FIREWIRE_NET=m
++CONFIG_FIREWIRE_OHCI_DEBUG=y
++CONFIG_FIREWIRE_NOSY=m
++# CONFIG_FIREWIRE_SERIAL is not set
++# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set
++
++#
++# IEEE 1394 (FireWire) support
++#
++
++#
++# I2O device support
++#
++# CONFIG_I2O is not set
++# CONFIG_I2O_LCT_NOTIFY_ON_CHANGES is not set
++
++#
++# Virtualization support drivers
++#
++# CONFIG_VIRT_DRIVERS is not set
++
++# Networking support
++#
++
++CONFIG_NET_DMA=y
++
++CONFIG_NETLINK_MMAP=y
++CONFIG_NETLINK_DIAG=m
++
++CONFIG_TCP_CONG_ADVANCED=y
++CONFIG_TCP_CONG_BIC=m
++CONFIG_TCP_CONG_CUBIC=y
++CONFIG_TCP_CONG_HTCP=m
++CONFIG_TCP_CONG_HSTCP=m
++CONFIG_TCP_CONG_HYBLA=m
++CONFIG_TCP_CONG_ILLINOIS=m
++CONFIG_TCP_CONG_LP=m
++CONFIG_TCP_CONG_SCALABLE=m
++CONFIG_TCP_CONG_VEGAS=m
++CONFIG_TCP_CONG_VENO=m
++CONFIG_TCP_CONG_WESTWOOD=m
++CONFIG_TCP_CONG_YEAH=m
++
++CONFIG_TCP_MD5SIG=y
++
++#
++# Networking options
++#
++CONFIG_PACKET_DIAG=m
++CONFIG_UNIX_DIAG=m
++CONFIG_NET_KEY=m
++CONFIG_NET_KEY_MIGRATE=y
++CONFIG_INET_TUNNEL=m
++CONFIG_INET_DIAG=m
++CONFIG_INET_UDP_DIAG=m
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_FIB_TRIE_STATS=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_NF_SECURITY=m
++CONFIG_NET_IPIP=m
++CONFIG_NET_IPGRE_DEMUX=m
++CONFIG_NET_IPGRE=m
++CONFIG_NET_IPGRE_BROADCAST=y
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IP_PIMSM_V1=y
++CONFIG_IP_PIMSM_V2=y
++CONFIG_ARPD=y
++CONFIG_SYN_COOKIES=y
++CONFIG_NET_IPVTI=m
++CONFIG_INET_AH=m
++CONFIG_INET_ESP=m
++CONFIG_INET_IPCOMP=m
++CONFIG_NETCONSOLE=m
++CONFIG_NETCONSOLE_DYNAMIC=y
++CONFIG_NETPOLL_TRAP=y
++CONFIG_NET_POLL_CONTROLLER=y
++
++#
++# IP: Virtual Server Configuration
++#
++CONFIG_IP_VS=m
++# CONFIG_IP_VS_DEBUG is not set
++CONFIG_IP_VS_TAB_BITS=12
++CONFIG_IP_VS_PROTO_TCP=y
++CONFIG_IP_VS_PROTO_UDP=y
++CONFIG_IP_VS_PROTO_ESP=y
++CONFIG_IP_VS_PROTO_AH=y
++CONFIG_IP_VS_PROTO_SCTP=y
++CONFIG_IP_VS_IPV6=y
++CONFIG_IP_VS_RR=m
++CONFIG_IP_VS_WRR=m
++CONFIG_IP_VS_LC=m
++CONFIG_IP_VS_WLC=m
++CONFIG_IP_VS_LBLC=m
++CONFIG_IP_VS_LBLCR=m
++CONFIG_IP_VS_DH=m
++CONFIG_IP_VS_SH=m
++CONFIG_IP_VS_SED=m
++CONFIG_IP_VS_NQ=m
++
++#
++# IPVS SH scheduler
++#
++CONFIG_IP_VS_SH_TAB_BITS=8
++
++CONFIG_IP_VS_FTP=m
++CONFIG_IP_VS_PE_SIP=m
++
++CONFIG_IPV6_PRIVACY=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_INET6_AH=m
++CONFIG_INET6_ESP=m
++CONFIG_INET6_IPCOMP=m
++CONFIG_IPV6_MIP6=y
++CONFIG_IPV6_VTI=m
++CONFIG_IPV6_SIT=m
++CONFIG_IPV6_SIT_6RD=y
++CONFIG_IPV6_TUNNEL=m
++# CONFIG_IPV6_GRE is not set
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_IPV6_PIMSM_V2=y
++
++CONFIG_RDS=m
++# CONFIG_RDS_DEBUG is not set
++CONFIG_RDS_RDMA=m
++CONFIG_RDS_TCP=m
++
++CONFIG_NET_9P=m
++CONFIG_NET_9P_VIRTIO=m
++# CONFIG_NET_9P_DEBUG is not set
++CONFIG_NET_9P_RDMA=m
++
++# CONFIG_DECNET is not set
++CONFIG_BRIDGE=m
++CONFIG_BRIDGE_IGMP_SNOOPING=y
++CONFIG_BRIDGE_VLAN_FILTERING=y
++
++# PHY timestamping adds overhead
++CONFIG_NETWORK_PHY_TIMESTAMPING=y
++
++CONFIG_NETFILTER_ADVANCED=y
++CONFIG_NF_CONNTRACK=m
++CONFIG_NETFILTER_NETLINK=m
++CONFIG_NETFILTER_NETLINK_ACCT=m
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_QUEUE_CT=y
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NETFILTER_TPROXY=m
++CONFIG_NETFILTER_XTABLES=y
++CONFIG_NETFILTER_XT_SET=m
++CONFIG_NETFILTER_XT_MARK=m
++CONFIG_NETFILTER_XT_CONNMARK=m
++
++CONFIG_NETFILTER_XT_TARGET_AUDIT=m
++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
++CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
++CONFIG_NETFILTER_XT_TARGET_CT=m
++CONFIG_NETFILTER_XT_TARGET_DSCP=m
++CONFIG_NETFILTER_XT_TARGET_HMARK=m
++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
++CONFIG_NETFILTER_XT_TARGET_LED=m
++CONFIG_NETFILTER_XT_TARGET_LOG=m
++CONFIG_NETFILTER_XT_TARGET_MARK=m
++CONFIG_NETFILTER_XT_TARGET_NFLOG=m
++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
++CONFIG_NETFILTER_XT_TARGET_RATEEST=m
++CONFIG_NETFILTER_XT_TARGET_SECMARK=m
++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
++CONFIG_NETFILTER_XT_TARGET_TRACE=m
++CONFIG_NETFILTER_XT_TARGET_TEE=m
++CONFIG_NETFILTER_XT_TARGET_TPROXY=m
++
++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
++CONFIG_NETFILTER_XT_MATCH_BPF=m
++CONFIG_NETFILTER_XT_MATCH_CGROUP=m
++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
++CONFIG_NETFILTER_XT_MATCH_COMMENT=m
++CONFIG_NETFILTER_XT_MATCH_CPU=m
++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
++CONFIG_NETFILTER_XT_MATCH_DCCP=m
++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
++CONFIG_NETFILTER_XT_MATCH_DSCP=m
++CONFIG_NETFILTER_XT_MATCH_ECN=m
++CONFIG_NETFILTER_XT_MATCH_ESP=m
++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
++CONFIG_NETFILTER_XT_MATCH_HELPER=m
++CONFIG_NETFILTER_XT_MATCH_HL=m
++CONFIG_NETFILTER_XT_MATCH_IPCOMP=m
++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
++CONFIG_NETFILTER_XT_MATCH_IPVS=m
++CONFIG_NETFILTER_XT_MATCH_L2TP=m
++CONFIG_NETFILTER_XT_MATCH_LENGTH=m
++CONFIG_NETFILTER_XT_MATCH_LIMIT=m
++CONFIG_NETFILTER_XT_MATCH_MAC=m
++CONFIG_NETFILTER_XT_MATCH_MARK=m
++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
++CONFIG_NETFILTER_XT_MATCH_NFACCT=m
++CONFIG_NETFILTER_XT_MATCH_OSF=m
++CONFIG_NETFILTER_XT_MATCH_OWNER=m
++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
++CONFIG_NETFILTER_XT_MATCH_POLICY=m
++CONFIG_NETFILTER_XT_MATCH_QUOTA=m
++CONFIG_NETFILTER_XT_MATCH_RATEEST=m
++CONFIG_NETFILTER_XT_MATCH_REALM=m
++CONFIG_NETFILTER_XT_MATCH_RECENT=m
++CONFIG_NETFILTER_XT_MATCH_SCTP=m
++CONFIG_NETFILTER_XT_MATCH_SOCKET=m
++CONFIG_NETFILTER_XT_MATCH_STATE=y
++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
++CONFIG_NETFILTER_XT_MATCH_STRING=m
++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
++CONFIG_NETFILTER_XT_MATCH_TIME=m
++CONFIG_NETFILTER_XT_MATCH_U32=m
++
++# CONFIG_NETFILTER_DEBUG is not set
++CONFIG_BRIDGE_NETFILTER=y
++
++#
++# IP: Netfilter Configuration
++#
++
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_SECMARK=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_ZONES=y
++CONFIG_NF_CONNTRACK_PROCFS=y # check if contrack(8) in f17 supports netlink
++# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
++CONFIG_NF_CONNTRACK_AMANDA=m
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SANE=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CONNTRACK_IPV4=y
++CONFIG_NF_CONNTRACK_IPV6=y
++# CONFIG_NF_CONNTRACK_TIMEOUT is not set
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_NAT=m
++CONFIG_NF_NAT_NEEDED=y
++CONFIG_NF_NAT_SNMP_BASIC=m
++CONFIG_NF_CT_PROTO_DCCP=m
++CONFIG_NF_CT_PROTO_SCTP=m
++CONFIG_NF_CT_NETLINK=m
++# CONFIG_NF_CT_NETLINK_TIMEOUT is not set
++CONFIG_NF_CT_NETLINK_HELPER=m
++CONFIG_NF_CT_PROTO_UDPLITE=m
++
++CONFIG_IP_NF_MATCH_AH=m
++CONFIG_IP_NF_MATCH_ECN=m
++CONFIG_IP_NF_MATCH_RPFILTER=m
++CONFIG_IP_NF_MATCH_TTL=m
++CONFIG_IP_NF_TARGET_CLUSTERIP=m
++CONFIG_IP_NF_TARGET_REDIRECT=m
++CONFIG_IP_NF_TARGET_NETMAP=m
++CONFIG_IP_NF_TARGET_ECN=m
++CONFIG_IP_NF_TARGET_LOG=m
++CONFIG_IP_NF_TARGET_ULOG=m
++CONFIG_IP_NF_TARGET_REJECT=y
++CONFIG_IP_NF_TARGET_SYNPROXY=m
++CONFIG_IP_NF_TARGET_TTL=m
++CONFIG_NF_NAT_IPV4=m
++CONFIG_IP_NF_TARGET_MASQUERADE=m
++CONFIG_IP_NF_MANGLE=m
++CONFIG_IP_NF_ARPTABLES=m
++CONFIG_IP_NF_ARPFILTER=m
++CONFIG_IP_NF_ARP_MANGLE=m
++CONFIG_IP_NF_QUEUE=m
++CONFIG_IP_NF_RAW=m
++
++CONFIG_IP_NF_IPTABLES=y
++CONFIG_IP_NF_FILTER=y
++
++#
++# IPv6: Netfilter Configuration
++#
++CONFIG_IP6_NF_FILTER=m
++CONFIG_IP6_NF_IPTABLES=m
++CONFIG_IP6_NF_MANGLE=m
++CONFIG_IP6_NF_MATCH_AH=m
++CONFIG_IP6_NF_MATCH_EUI64=m
++CONFIG_IP6_NF_MATCH_FRAG=m
++CONFIG_IP6_NF_MATCH_HL=m
++CONFIG_IP6_NF_MATCH_IPV6HEADER=m
++CONFIG_IP6_NF_MATCH_MH=m
++CONFIG_IP6_NF_MATCH_RPFILTER=m
++CONFIG_IP6_NF_MATCH_OPTS=m
++CONFIG_IP6_NF_MATCH_RT=m
++CONFIG_IP6_NF_QUEUE=m
++CONFIG_IP6_NF_RAW=m
++CONFIG_IP6_NF_SECURITY=m
++CONFIG_IP6_NF_TARGET_LOG=m
++CONFIG_IP6_NF_TARGET_REJECT=m
++CONFIG_IP6_NF_TARGET_SYNPROXY=m
++CONFIG_IP6_NF_TARGET_HL=m
++CONFIG_NF_NAT_IPV6=m
++CONFIG_IP6_NF_TARGET_MASQUERADE=m
++# CONFIG_IP6_NF_TARGET_NPT is not set
++
++# nf_tables support
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=m
++CONFIG_NFT_EXTHDR=m
++CONFIG_NFT_META=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_RBTREE=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_COUNTER=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_COMPAT=m
++
++CONFIG_NF_TABLES_IPV4=m
++CONFIG_NFT_REJECT_IPV4=m
++CONFIG_NFT_CHAIN_ROUTE_IPV4=m
++CONFIG_NFT_CHAIN_NAT_IPV4=m
++CONFIG_NF_TABLES_ARP=m
++
++CONFIG_NF_TABLES_IPV6=m
++CONFIG_NFT_CHAIN_ROUTE_IPV6=m
++CONFIG_NFT_CHAIN_NAT_IPV6=m
++
++CONFIG_NF_TABLES_BRIDGE=m
++#
++# Bridge: Netfilter Configuration
++#
++CONFIG_BRIDGE_NF_EBTABLES=m
++CONFIG_BRIDGE_EBT_802_3=m
++CONFIG_BRIDGE_EBT_AMONG=m
++CONFIG_BRIDGE_EBT_ARP=m
++CONFIG_BRIDGE_EBT_ARPREPLY=m
++CONFIG_BRIDGE_EBT_BROUTE=m
++CONFIG_BRIDGE_EBT_DNAT=m
++CONFIG_BRIDGE_EBT_IP=m
++CONFIG_BRIDGE_EBT_IP6=m
++CONFIG_BRIDGE_EBT_LIMIT=m
++CONFIG_BRIDGE_EBT_LOG=m
++CONFIG_BRIDGE_EBT_MARK=m
++CONFIG_BRIDGE_EBT_MARK_T=m
++CONFIG_BRIDGE_EBT_NFLOG=m
++CONFIG_BRIDGE_EBT_PKTTYPE=m
++CONFIG_BRIDGE_EBT_REDIRECT=m
++CONFIG_BRIDGE_EBT_SNAT=m
++CONFIG_BRIDGE_EBT_STP=m
++CONFIG_BRIDGE_EBT_T_FILTER=m
++CONFIG_BRIDGE_EBT_T_NAT=m
++CONFIG_BRIDGE_EBT_ULOG=m
++CONFIG_BRIDGE_EBT_VLAN=m
++CONFIG_XFRM=y
++CONFIG_XFRM_MIGRATE=y
++CONFIG_XFRM_SUB_POLICY=y
++CONFIG_XFRM_STATISTICS=y
++CONFIG_XFRM_USER=y
++CONFIG_INET6_XFRM_MODE_TRANSPORT=m
++CONFIG_INET6_XFRM_MODE_TUNNEL=m
++CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
++CONFIG_INET6_XFRM_MODE_BEET=m
++
++CONFIG_IP_SET=m
++CONFIG_IP_SET_MAX=256
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++
++#
++# SCTP Configuration (EXPERIMENTAL)
++#
++CONFIG_IP_SCTP=m
++CONFIG_NET_SCTPPROBE=m
++# CONFIG_SCTP_DBG_MSG is not set
++# CONFIG_SCTP_DBG_OBJCNT is not set
++CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
++# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set
++# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
++CONFIG_SCTP_COOKIE_HMAC_MD5=y
++CONFIG_SCTP_COOKIE_HMAC_SHA1=y
++CONFIG_ATM=m
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_VLAN_8021Q_MVRP=y
++CONFIG_LLC=m
++# CONFIG_LLC2 is not set
++CONFIG_IPX=m
++# CONFIG_IPX_INTERN is not set
++CONFIG_ATALK=m
++CONFIG_DEV_APPLETALK=m
++CONFIG_IPDDP=m
++CONFIG_IPDDP_ENCAP=y
++CONFIG_IPDDP_DECAP=y
++# CONFIG_X25 is not set
++# CONFIG_LAPB is not set
++# CONFIG_ECONET is not set
++CONFIG_WAN_ROUTER=m
++CONFIG_IP_DCCP=m
++CONFIG_IP_DCCP_CCID2=m
++# CONFIG_IP_DCCP_CCID2_DEBUG is not set
++CONFIG_IP_DCCP_CCID3=y
++# CONFIG_IP_DCCP_CCID3_DEBUG is not set
++# CONFIG_IP_DCCP_DEBUG is not set
++# CONFIG_NET_DCCPPROBE is not set
++
++#
++# TIPC Configuration (EXPERIMENTAL)
++#
++CONFIG_TIPC=m
++CONFIG_TIPC_PORTS=8192
++# CONFIG_TIPC_MEDIA_IB is not set
++# CONFIG_TIPC_ADVANCED is not set
++# CONFIG_TIPC_DEBUG is not set
++
++CONFIG_NETLABEL=y
++
++#
++# QoS and/or fair queueing
++#
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_CBQ=m
++CONFIG_NET_SCH_DSMARK=m
++CONFIG_NET_SCH_DRR=m
++CONFIG_NET_SCH_GRED=m
++CONFIG_NET_SCH_HFSC=m
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_SCH_INGRESS=m
++CONFIG_NET_SCH_NETEM=m
++CONFIG_NET_SCH_PRIO=m
++CONFIG_NET_SCH_RED=m
++CONFIG_NET_SCH_SFQ=m
++CONFIG_NET_SCH_TBF=m
++CONFIG_NET_SCH_TEQL=m
++CONFIG_NET_SCH_SFB=m
++CONFIG_NET_SCH_MQPRIO=m
++CONFIG_NET_SCH_MULTIQ=m
++CONFIG_NET_SCH_CHOKE=m
++CONFIG_NET_SCH_QFQ=m
++CONFIG_NET_SCH_CODEL=m
++CONFIG_NET_SCH_FQ_CODEL=m
++CONFIG_NET_SCH_FQ=m
++CONFIG_NET_SCH_HHF=m
++CONFIG_NET_SCH_PIE=m
++CONFIG_NET_SCH_PLUG=m
++CONFIG_NET_CLS=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=m
++CONFIG_NET_CLS_FLOW=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_IND=y
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_ROUTE=y
++CONFIG_NET_CLS_RSVP=m
++CONFIG_NET_CLS_RSVP6=m
++CONFIG_NET_CLS_TCINDEX=m
++CONFIG_NET_CLS_U32=m
++CONFIG_CLS_U32_MARK=y
++CONFIG_CLS_U32_PERF=y
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=m
++CONFIG_NET_EMATCH_META=m
++CONFIG_NET_EMATCH_NBYTE=m
++CONFIG_NET_EMATCH_STACK=32
++CONFIG_NET_EMATCH_TEXT=m
++CONFIG_NET_EMATCH_IPSET=m
++CONFIG_NET_EMATCH_U32=m
++
++CONFIG_NET_ACT_CSUM=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_GACT_PROB=y
++CONFIG_NET_ACT_IPT=m
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NET_ACT_NAT=m
++CONFIG_NET_ACT_PEDIT=m
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_SIMP=m
++CONFIG_NET_ACT_SKBEDIT=m
++
++CONFIG_DCB=y
++CONFIG_DNS_RESOLVER=m
++CONFIG_BATMAN_ADV=m
++CONFIG_BATMAN_ADV_BLA=y
++CONFIG_BATMAN_ADV_DAT=y
++CONFIG_BATMAN_ADV_NC=y
++
++# CONFIG_BATMAN_ADV_DEBUG is not set
++CONFIG_OPENVSWITCH=m
++CONFIG_OPENVSWITCH_GRE=y
++CONFIG_OPENVSWITCH_VXLAN=y
++CONFIG_VSOCKETS=m
++
++
++#
++# Network testing
++#
++CONFIG_NET_PKTGEN=m
++# CONFIG_NET_TCPPROBE is not set
++CONFIG_NET_DROP_MONITOR=y
++
++# disable later --kyle
++
++#
++# ARCnet devices
++#
++# CONFIG_ARCNET is not set
++CONFIG_IFB=m
++CONFIG_NET_TEAM=m
++CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
++CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
++CONFIG_NET_TEAM_MODE_LOADBALANCE=m
++CONFIG_NET_TEAM_MODE_BROADCAST=m
++CONFIG_NET_TEAM_MODE_RANDOM=m
++CONFIG_DUMMY=m
++CONFIG_BONDING=m
++CONFIG_MACVLAN=m
++CONFIG_MACVTAP=m
++CONFIG_VXLAN=m
++CONFIG_EQUALIZER=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++CONFIG_NLMON=m
++
++#
++# ATM
++#
++CONFIG_ATM_DRIVERS=y
++# CONFIG_ATM_DUMMY is not set
++CONFIG_ATM_CLIP=m
++CONFIG_ATM_LANE=m
++CONFIG_ATM_BR2684=m
++CONFIG_NET_SCH_ATM=m
++CONFIG_ATM_TCP=m
++# CONFIG_ATM_LANAI is not set
++CONFIG_ATM_ENI=m
++CONFIG_ATM_FIRESTREAM=m
++# CONFIG_ATM_ZATM is not set
++# CONFIG_ATM_IDT77252 is not set
++# CONFIG_ATM_AMBASSADOR is not set
++# CONFIG_ATM_HORIZON is not set
++# CONFIG_ATM_FORE200E is not set
++# CONFIG_ATM_FORE200E_USE_TASKLET is not set
++CONFIG_ATM_FORE200E_TX_RETRY=16
++CONFIG_ATM_FORE200E_DEBUG=0
++
++CONFIG_ATM_HE=m
++CONFIG_PPTP=m
++CONFIG_PPPOATM=m
++CONFIG_PPPOL2TP=m
++CONFIG_ATM_NICSTAR=m
++# CONFIG_ATM_IA is not set
++# CONFIG_ATM_CLIP_NO_ICMP is not set
++# CONFIG_ATM_MPOA is not set
++# CONFIG_ATM_BR2684_IPFILTER is not set
++# CONFIG_ATM_ENI_DEBUG is not set
++# CONFIG_ATM_ENI_TUNE_BURST is not set
++# CONFIG_ATM_ZATM_DEBUG is not set
++# CONFIG_ATM_IDT77252_DEBUG is not set
++# CONFIG_ATM_IDT77252_RCV_ALL is not set
++# CONFIG_ATM_AMBASSADOR_DEBUG is not set
++# CONFIG_ATM_HORIZON_DEBUG is not set
++# CONFIG_ATM_HE_USE_SUNI is not set
++# CONFIG_ATM_NICSTAR_USE_SUNI is not set
++# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
++# CONFIG_ATM_IA_DEBUG is not set
++CONFIG_ATM_SOLOS=m
++
++CONFIG_L2TP=m
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=m
++CONFIG_L2TP_ETH=m
++
++# CONFIG_CAIF is not set
++
++CONFIG_RFKILL=m
++CONFIG_RFKILL_GPIO=m
++CONFIG_RFKILL_INPUT=y
++
++
++#
++# Ethernet (10 or 100Mbit)
++#
++
++CONFIG_NET_VENDOR_ADAPTEC=y
++CONFIG_ADAPTEC_STARFIRE=m
++
++CONFIG_NET_VENDOR_ALTEON=y
++CONFIG_ACENIC=m
++# CONFIG_ACENIC_OMIT_TIGON_I is not set
++
++CONFIG_NET_VENDOR_AMD=y
++CONFIG_PCNET32=m
++CONFIG_AMD8111_ETH=m
++CONFIG_PCMCIA_NMCLAN=m
++
++CONFIG_NET_VENDOR_ARC=y
++CONFIG_ARC_EMAC=m
++
++CONFIG_NET_VENDOR_ATHEROS=y
++CONFIG_ALX=m
++CONFIG_ATL2=m
++CONFIG_ATL1=m
++CONFIG_ATL1C=m
++CONFIG_ATL1E=m
++CONFIG_NET_CADENCE=y
++CONFIG_ARM_AT91_ETHER=m
++CONFIG_MACB=m
++
++CONFIG_NET_VENDOR_BROCADE=y
++CONFIG_BNA=m
++CONFIG_NET_CALXEDA_XGMAC=m
++
++CONFIG_NET_VENDOR_CHELSIO=y
++CONFIG_CHELSIO_T1=m
++CONFIG_CHELSIO_T1_1G=y
++CONFIG_CHELSIO_T3=m
++CONFIG_CHELSIO_T4=m
++CONFIG_CHELSIO_T4VF=m
++
++CONFIG_NET_VENDOR_CISCO=y
++CONFIG_ENIC=m
++
++CONFIG_NET_VENDOR_DEC=y
++#
++# Tulip family network device support
++#
++CONFIG_NET_TULIP=y
++CONFIG_DE2104X=m
++CONFIG_DE2104X_DSL=0
++CONFIG_TULIP=m
++# CONFIG_TULIP_NAPI is not set
++# CONFIG_TULIP_MWI is not set
++CONFIG_TULIP_MMIO=y
++# CONFIG_NI5010 is not set
++CONFIG_DE4X5=m
++CONFIG_WINBOND_840=m
++CONFIG_DM9102=m
++CONFIG_PCMCIA_XIRCOM=m
++CONFIG_ULI526X=m
++
++CONFIG_NET_VENDOR_DLINK=y
++CONFIG_DE600=m
++CONFIG_DE620=m
++CONFIG_DL2K=m
++CONFIG_SUNDANCE=m
++# CONFIG_SUNDANCE_MMIO is not set
++
++CONFIG_NET_VENDOR_EMULEX=y
++CONFIG_BE2NET=m
++
++CONFIG_NET_VENDOR_EXAR=y
++CONFIG_S2IO=m
++CONFIG_VXGE=m
++# CONFIG_VXGE_DEBUG_TRACE_ALL is not set
++
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_FUJITSU is not set
++# CONFIG_NET_VENDOR_HP is not set
++CONFIG_NET_VENDOR_INTEL=y
++CONFIG_E100=m
++CONFIG_E1000=m
++CONFIG_E1000E=m
++CONFIG_IGB=m
++CONFIG_IGB_HWMON=y
++CONFIG_IGB_DCA=y
++CONFIG_IGB_PTP=y
++CONFIG_IGBVF=m
++CONFIG_IXGB=m
++CONFIG_IXGBEVF=m
++CONFIG_IXGBE=m
++CONFIG_IXGBE_DCA=y
++CONFIG_IXGBE_DCB=y
++CONFIG_IXGBE_HWMON=y
++CONFIG_IXGBE_PTP=y
++CONFIG_I40E=m
++# CONFIG_I40E_VXLAN is not set
++# CONFIG_I40E_DCB is not set
++# CONFIG_I40EVF is not set
++
++
++# CONFIG_NET_VENDOR_I825XX is not set
++CONFIG_NET_VENDOR_MARVELL=y
++CONFIG_MVMDIO=m
++CONFIG_SKGE=m
++# CONFIG_SKGE_DEBUG is not set
++CONFIG_SKGE_GENESIS=y
++CONFIG_SKY2=m
++# CONFIG_SKY2_DEBUG is not set
++
++CONFIG_NET_VENDOR_MICREL=y
++CONFIG_KSZ884X_PCI=m
++# CONFIG_KS8842 is not set
++# CONFIG_KS8851_MLL is not set
++
++CONFIG_NET_VENDOR_MYRI=y
++CONFIG_MYRI10GE=m
++CONFIG_MYRI10GE_DCA=y
++
++CONFIG_NATSEMI=m
++CONFIG_NS83820=m
++
++CONFIG_PCMCIA_AXNET=m
++CONFIG_NE2K_PCI=m
++CONFIG_NE3210=m
++CONFIG_PCMCIA_PCNET=m
++
++CONFIG_NET_VENDOR_NVIDIA=y
++CONFIG_FORCEDETH=m
++
++CONFIG_NET_VENDOR_OKI=y
++# CONFIG_PCH_GBE is not set
++# CONFIG_PCH_PTP is not set
++
++CONFIG_NET_PACKET_ENGINE=y
++CONFIG_HAMACHI=m
++CONFIG_YELLOWFIN=m
++
++CONFIG_NET_VENDOR_QLOGIC=y
++CONFIG_QLA3XXX=m
++CONFIG_QLCNIC=m
++CONFIG_QLCNIC_SRIOV=y
++CONFIG_QLCNIC_DCB=y
++CONFIG_QLGE=m
++CONFIG_NETXEN_NIC=m
++
++CONFIG_NET_VENDOR_REALTEK=y
++CONFIG_ATP=m
++CONFIG_8139CP=m
++CONFIG_8139TOO=m
++# CONFIG_8139TOO_PIO is not set
++# CONFIG_8139TOO_TUNE_TWISTER is not set
++CONFIG_8139TOO_8129=y
++# CONFIG_8139_OLD_RX_RESET is not set
++CONFIG_R8169=m
++
++
++CONFIG_NET_VENDOR_RDC=y
++CONFIG_R6040=m
++
++
++CONFIG_NET_VENDOR_SILAN=y
++CONFIG_SC92031=m
++
++CONFIG_NET_VENDOR_SIS=y
++CONFIG_SIS900=m
++CONFIG_SIS190=m
++
++CONFIG_PCMCIA_SMC91C92=m
++CONFIG_EPIC100=m
++CONFIG_SMSC9420=m
++
++# CONFIG_STMMAC_PLATFORM is not set
++# CONFIG_STMMAC_PCI is not set
++# CONFIG_STMMAC_DA is not set
++# CONFIG_STMMAC_DUAL_MAC is not set
++# CONFIG_STMMAC_TIMER is not set
++# CONFIG_STMMAC_DEBUG_FS is not set
++
++CONFIG_NET_VENDOR_SUN=y
++CONFIG_HAPPYMEAL=m
++CONFIG_SUNGEM=m
++CONFIG_CASSINI=m
++CONFIG_NIU=m
++
++CONFIG_NET_VENDOR_TEHUTI=y
++CONFIG_TEHUTI=m
++
++CONFIG_NET_VENDOR_TI=y
++CONFIG_TLAN=m
++
++CONFIG_VIA_RHINE=m
++CONFIG_VIA_RHINE_MMIO=y
++
++CONFIG_WIZNET_W5100=m
++CONFIG_WIZNET_W5300=m
++CONFIG_NET_VENDOR_XIRCOM=y
++CONFIG_PCMCIA_XIRC2PS=m
++
++CONFIG_AMD_PHY=m
++CONFIG_BROADCOM_PHY=m
++CONFIG_BCM87XX_PHY=m
++CONFIG_CICADA_PHY=m
++CONFIG_DAVICOM_PHY=m
++CONFIG_DP83640_PHY=m
++CONFIG_FIXED_PHY=y
++CONFIG_MDIO_BITBANG=m
++CONFIG_NATIONAL_PHY=m
++CONFIG_ICPLUS_PHY=m
++CONFIG_BCM63XX_PHY=m
++CONFIG_LSI_ET1011C_PHY=m
++CONFIG_LXT_PHY=m
++CONFIG_MARVELL_PHY=m
++CONFIG_QSEMI_PHY=m
++CONFIG_REALTEK_PHY=m
++CONFIG_SMSC_PHY=m
++CONFIG_STE10XP=m
++CONFIG_VITESSE_PHY=m
++CONFIG_MICREL_PHY=m
++
++CONFIG_MII=m
++CONFIG_NET_CORE=y
++CONFIG_NET_VENDOR_3COM=y
++CONFIG_VORTEX=m
++CONFIG_TYPHOON=m
++CONFIG_DNET=m
++
++
++CONFIG_LNE390=m
++CONFIG_ES3210=m
++CONFIG_NET_PCI=y
++CONFIG_B44=m
++CONFIG_B44_PCI=y
++CONFIG_BNX2=m
++CONFIG_BNX2X=m
++CONFIG_BNX2X_SRIOV=y
++CONFIG_CNIC=m
++CONFIG_FEALNX=m
++CONFIG_NET_POCKET=y
++
++#
++# Ethernet (1000 Mbit)
++#
++CONFIG_TIGON3=m
++CONFIG_JME=m
++
++#
++# Ethernet (10000 Mbit)
++#
++# CONFIG_IP1000 is not set
++# CONFIG_MLX4_EN is not set
++# CONFIG_SFC is not set
++
++# CONFIG_FDDI is not set
++# CONFIG_DEFXX is not set
++# CONFIG_SKFP is not set
++# CONFIG_HIPPI is not set
++# CONFIG_PLIP is not set
++CONFIG_PPP=m
++CONFIG_PPP_MULTILINK=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_IPPP_FILTER=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPPOE=m
++CONFIG_PPP_MPPE=m
++CONFIG_SLIP=m
++CONFIG_SLIP_COMPRESSED=y
++CONFIG_SLIP_SMART=y
++# CONFIG_SLIP_MODE_SLIP6 is not set
++
++#
++# Wireless LAN
++#
++#
++# CONFIG_STRIP is not set
++# CONFIG_PCMCIA_RAYCS is not set
++
++CONFIG_CFG80211_WEXT=y
++# CONFIG_CFG80211_REG_DEBUG is not set
++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
++CONFIG_CFG80211_DEFAULT_PS=y
++CONFIG_NL80211=y
++# CONFIG_NL80211_TESTMODE is not set
++# CONFIG_WIRELESS_EXT_SYSFS is not set
++CONFIG_LIB80211=m
++CONFIG_LIB80211_CRYPT_WEP=m
++CONFIG_LIB80211_CRYPT_CCMP=m
++CONFIG_LIB80211_CRYPT_TKIP=m
++# CONFIG_LIB80211_DEBUG is not set
++
++CONFIG_MAC80211=m
++CONFIG_MAC80211_RC_MINSTREL=y
++# CONFIG_MAC80211_RC_DEFAULT_PID is not set
++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
++CONFIG_MAC80211_RC_DEFAULT="minstrel"
++CONFIG_MAC80211_MESH=y
++CONFIG_MAC80211_LEDS=y
++# CONFIG_MAC80211_DEBUG_MENU is not set
++
++# CONFIG_WIMAX is not set
++
++# CONFIG_ADM8211 is not set
++CONFIG_ATH_COMMON=m
++CONFIG_ATH_CARDS=m
++CONFIG_ATH5K=m
++CONFIG_ATH5K_DEBUG=y
++# CONFIG_ATH5K_TRACER is not set
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_DEBUG=y
++CONFIG_ATH6KL_SDIO=m
++CONFIG_ATH6KL_USB=m
++# CONFIG_ATH6KL_TRACING is not set
++CONFIG_AR5523=m
++CONFIG_ATH9K=m
++CONFIG_ATH9K_PCI=y
++CONFIG_ATH9K_AHB=y
++# CONFIG_ATH9K_DEBUG is not set
++# CONFIG_ATH9K_MAC_DEBUG is not set
++CONFIG_ATH9K_HTC=m
++CONFIG_ATH9K_BTCOEX_SUPPORT=y
++# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set
++# CONFIG_ATH9K_WOW is not set
++#
++CONFIG_ATH10K=m
++CONFIG_ATH10K_PCI=m
++# CONFIG_ATH10K_DEBUG is not set
++# CONFIG_ATH10K_TRACING is not set
++CONFIG_ATH10K_DEBUGFS=y
++CONFIG_WCN36XX=m
++# CONFIG_WCN36XX_DEBUGFS is not set
++CONFIG_WIL6210=m
++CONFIG_WIL6210_ISR_COR=y
++# CONFIG_WIL6210_TRACING is not set
++CONFIG_CARL9170=m
++CONFIG_CARL9170_LEDS=y
++# CONFIG_CARL9170_HWRNG is not set
++CONFIG_AT76C50X_USB=m
++# CONFIG_AIRO is not set
++# CONFIG_AIRO_CS is not set
++# CONFIG_ATMEL is not set
++CONFIG_B43=m
++CONFIG_B43_PCMCIA=y
++CONFIG_B43_SDIO=y
++CONFIG_B43_BCMA=y
++# CONFIG_B43_BCMA_EXTRA is not set
++CONFIG_B43_BCMA_PIO=y
++# CONFIG_B43_DEBUG is not set
++CONFIG_B43_PHY_LP=y
++CONFIG_B43_PHY_N=y
++CONFIG_B43_PHY_HT=y
++# CONFIG_B43_FORCE_PIO is not set
++CONFIG_B43LEGACY=m
++# CONFIG_B43LEGACY_DEBUG is not set
++CONFIG_B43LEGACY_DMA=y
++CONFIG_B43LEGACY_PIO=y
++CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y
++# CONFIG_B43LEGACY_DMA_MODE is not set
++# CONFIG_B43LEGACY_PIO_MODE is not set
++CONFIG_BRCMSMAC=m
++# CONFIG_BRCMFMAC_SDIO_OOB is not set
++CONFIG_BRCMFMAC_USB=y
++# CONFIG_BRCM_TRACING is not set
++# CONFIG_BRCMISCAN is not set
++# CONFIG_BRCMDBG is not set
++CONFIG_HERMES=m
++CONFIG_HERMES_CACHE_FW_ON_INIT=y
++# CONFIG_HERMES_PRISM is not set
++CONFIG_NORTEL_HERMES=m
++CONFIG_PCI_HERMES=m
++CONFIG_PLX_HERMES=m
++CONFIG_PCMCIA_HERMES=m
++CONFIG_ORINOCO_USB=m
++# CONFIG_TMD_HERMES is not set
++# CONFIG_PCMCIA_SPECTRUM is not set
++CONFIG_CW1200=m
++CONFIG_CW1200_WLAN_SDIO=m
++CONFIG_CW1200_WLAN_SPI=m
++# CONFIG_HOSTAP is not set
++# CONFIG_IPW2100 is not set
++# CONFIG_IPW2200 is not set
++# CONFIG_IPW2100_DEBUG is not set
++# CONFIG_IPW2200_DEBUG is not set
++# CONFIG_LIBIPW_DEBUG is not set
++CONFIG_LIBERTAS=m
++CONFIG_LIBERTAS_USB=m
++CONFIG_LIBERTAS_CS=m
++CONFIG_LIBERTAS_SDIO=m
++# CONFIG_LIBERTAS_DEBUG is not set
++# CONFIG_LIBERTAS_THINFIRM is not set
++CONFIG_LIBERTAS_MESH=y
++CONFIG_IWLWIFI=m
++CONFIG_IWLDVM=m
++CONFIG_IWLMVM=m
++CONFIG_IWLWIFI_DEBUG=y
++CONFIG_IWLWIFI_DEVICE_SVTOOL=y
++# CONFIG_IWLWIFI_EXPERIMENTAL_MFP is not set
++CONFIG_IWLWIFI_UCODE16=y
++# CONFIG_IWLWIFI_P2P is not set
++CONFIG_IWLEGACY=m
++CONFIG_IWLEGACY_DEBUG=y
++# CONFIG_IWLWIFI_LEGACY_DEVICE_TRACING is not set
++CONFIG_IWL4965=y
++CONFIG_IWL3945=m
++# CONFIG_IWM is not set
++# CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE is not set
++CONFIG_MAC80211_HWSIM=m
++CONFIG_P54_COMMON=m
++CONFIG_P54_USB=m
++CONFIG_P54_PCI=m
++CONFIG_MWL8K=m
++# CONFIG_PRISM54 is not set
++# CONFIG_PCMCIA_WL3501 is not set
++CONFIG_RT2X00=m
++# CONFIG_RT2X00_DEBUG is not set
++CONFIG_RT2400PCI=m
++CONFIG_RT2500PCI=m
++CONFIG_RT61PCI=m
++CONFIG_RT2500USB=m
++CONFIG_RT2800USB=m
++CONFIG_RT2800USB_RT33XX=y
++CONFIG_RT2800USB_RT35XX=y
++CONFIG_RT2800USB_RT3573=y
++CONFIG_RT2800USB_RT53XX=y
++CONFIG_RT2800USB_RT55XX=y
++CONFIG_RT2800USB_UNKNOWN=y
++CONFIG_RT2800PCI=m
++CONFIG_RT2800PCI_RT3290=y
++CONFIG_RT2800PCI_RT33XX=y
++CONFIG_RT2800PCI_RT35XX=y
++CONFIG_RT2800PCI_RT53XX=y
++CONFIG_RT73USB=m
++CONFIG_RTL8180=m
++CONFIG_RTL8187=m
++# CONFIG_USB_ZD1201 is not set
++# CONFIG_USB_NET_SR9800 is not set
++CONFIG_USB_NET_RNDIS_WLAN=m
++CONFIG_USB_NET_KALMIA=m
++CONFIG_USB_NET_QMI_WWAN=m
++CONFIG_USB_NET_SMSC75XX=m
++# CONFIG_WL_TI is not set
++CONFIG_ZD1211RW=m
++# CONFIG_ZD1211RW_DEBUG is not set
++
++CONFIG_WL12XX=m
++CONFIG_WL12XX_SPI=m
++CONFIG_WL12XX_SDIO=m
++
++CONFIG_WL1251=m
++CONFIG_WL1251_SPI=m
++CONFIG_WL1251_SDIO=m
++
++CONFIG_RTL_CARDS=m
++CONFIG_RTLWIFI=m
++CONFIG_RTL8192CE=m
++CONFIG_RTL8192SE=m
++CONFIG_RTL8192CU=m
++CONFIG_RTL8192DE=m
++CONFIG_RTL8723AE=m
++CONFIG_RTL8188EE=m
++
++CONFIG_MWIFIEX=m
++CONFIG_MWIFIEX_SDIO=m
++CONFIG_MWIFIEX_PCIE=m
++CONFIG_MWIFIEX_USB=m
++
++#
++# Token Ring devices
++#
++# CONFIG_TR is not set
++
++CONFIG_NET_FC=y
++
++#
++# Wan interfaces
++#
++# CONFIG_WAN is not set
++
++#
++# PCMCIA network device support
++#
++CONFIG_NET_PCMCIA=y
++CONFIG_PCMCIA_3C589=m
++CONFIG_PCMCIA_3C574=m
++CONFIG_PCMCIA_FMVJ18X=m
++
++#
++# Amateur Radio support
++#
++CONFIG_HAMRADIO=y
++CONFIG_AX25=m
++CONFIG_AX25_DAMA_SLAVE=y
++
++# CONFIG_CAN is not set
++
++CONFIG_NETROM=m
++CONFIG_ROSE=m
++CONFIG_MKISS=m
++CONFIG_6PACK=m
++CONFIG_BPQETHER=m
++CONFIG_BAYCOM_SER_FDX=m
++CONFIG_BAYCOM_SER_HDX=m
++CONFIG_BAYCOM_PAR=m
++CONFIG_BAYCOM_EPP=m
++CONFIG_YAM=m
++
++CONFIG_NFC=m
++CONFIG_NFC_DIGITAL=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_HCI=m
++CONFIG_NFC_SHDLC=y
++CONFIG_NFC_LLCP=y
++CONFIG_NFC_SIM=m
++CONFIG_NFC_MRVL=m
++CONFIG_NFC_MRVL_USB=m
++
++#
++# Near Field Communication (NFC) devices
++#
++CONFIG_NFC_PORT100=m
++CONFIG_NFC_PN544=m
++CONFIG_NFC_PN544_I2C=m
++CONFIG_NFC_PN533=m
++CONFIG_NFC_MICROREAD=m
++CONFIG_NFC_MICROREAD_I2C=m
++
++#
++# IrDA (infrared) support
++#
++CONFIG_IRDA=m
++# CONFIG_IRDA_DEBUG is not set
++CONFIG_IRLAN=m
++CONFIG_IRNET=m
++CONFIG_IRCOMM=m
++# CONFIG_IRDA_ULTRA is not set
++CONFIG_IRDA_CACHE_LAST_LSAP=y
++CONFIG_IRDA_FAST_RR=y
++CONFIG_IRTTY_SIR=m
++CONFIG_DONGLE=y
++CONFIG_ACTISYS_DONGLE=m
++CONFIG_ACT200L_DONGLE=m
++CONFIG_ESI_DONGLE=m
++CONFIG_GIRBIL_DONGLE=m
++CONFIG_KINGSUN_DONGLE=m
++CONFIG_KSDAZZLE_DONGLE=m
++CONFIG_KS959_DONGLE=m
++CONFIG_LITELINK_DONGLE=m
++CONFIG_MA600_DONGLE=m
++CONFIG_MCP2120_DONGLE=m
++CONFIG_OLD_BELKIN_DONGLE=m
++CONFIG_TEKRAM_DONGLE=m
++CONFIG_TOIM3232_DONGLE=m
++
++CONFIG_ALI_FIR=m
++CONFIG_MCS_FIR=m
++CONFIG_NSC_FIR=m
++CONFIG_SIGMATEL_FIR=m
++CONFIG_SMC_IRCC_FIR=m
++# CONFIG_TOSHIBA_FIR is not set
++CONFIG_USB_IRDA=m
++CONFIG_VLSI_FIR=m
++CONFIG_VIA_FIR=m
++CONFIG_WINBOND_FIR=m
++
++#
++# Bluetooth support
++#
++CONFIG_BT=m
++CONFIG_BT_L2CAP=y
++CONFIG_BT_SCO=y
++CONFIG_BT_CMTP=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++
++#
++# Bluetooth device drivers
++#
++CONFIG_BT_HCIBTUSB=m
++# Disable the BT_HCIUSB driver.
++# It sucks more power than BT_HCIBTUSB which has the same functionality.
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_H4=y
++CONFIG_BT_HCIUART_BCSP=y
++CONFIG_BT_HCIUART_ATH3K=y
++CONFIG_BT_HCIUART_3WIRE=y
++CONFIG_BT_HCIDTL1=m
++CONFIG_BT_HCIBT3C=m
++CONFIG_BT_HCIBLUECARD=m
++CONFIG_BT_HCIBTUART=m
++CONFIG_BT_HCIVHCI=m
++CONFIG_BT_HCIBCM203X=m
++CONFIG_BT_HCIBFUSB=m
++CONFIG_BT_HCIBPA10X=m
++CONFIG_BT_HCIBTSDIO=m
++CONFIG_BT_HCIUART_LL=y
++CONFIG_BT_MRVL=m
++CONFIG_BT_MRVL_SDIO=m
++CONFIG_BT_ATH3K=m
++CONFIG_BT_WILINK=m
++
++#
++# ISDN subsystem
++#
++CONFIG_ISDN=y
++CONFIG_MISDN=m
++CONFIG_MISDN_DSP=m
++CONFIG_MISDN_L1OIP=m
++CONFIG_MISDN_AVMFRITZ=m
++CONFIG_MISDN_SPEEDFAX=m
++CONFIG_MISDN_INFINEON=m
++CONFIG_MISDN_W6692=m
++CONFIG_MISDN_NETJET=m
++
++#
++# mISDN hardware drivers
++#
++CONFIG_MISDN_HFCPCI=m
++CONFIG_MISDN_HFCMULTI=m
++CONFIG_ISDN_I4L=m
++CONFIG_ISDN_DRV_AVMB1_B1PCI=m
++CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m
++CONFIG_ISDN_DRV_AVMB1_T1PCI=m
++CONFIG_ISDN_DRV_AVMB1_C4=m
++
++CONFIG_MISDN_HFCUSB=m
++
++CONFIG_ISDN_PPP=y
++CONFIG_ISDN_PPP_VJ=y
++CONFIG_ISDN_MPP=y
++# CONFIG_ISDN_PPP_BSDCOMP is not set
++CONFIG_ISDN_TTY_FAX=y
++CONFIG_DE_AOC=y
++
++CONFIG_ISDN_AUDIO=y
++
++CONFIG_ISDN_DRV_HISAX=m
++CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y
++CONFIG_ISDN_DRV_AVMB1_AVM_CS=m
++
++CONFIG_ISDN_CAPI_CAPIDRV=m
++CONFIG_ISDN_DIVERSION=m
++
++CONFIG_HISAX_EURO=y
++CONFIG_HISAX_1TR6=y
++CONFIG_HISAX_NI1=y
++CONFIG_HISAX_MAX_CARDS=8
++CONFIG_HISAX_16_3=y
++CONFIG_HISAX_TELESPCI=y
++CONFIG_HISAX_S0BOX=y
++CONFIG_HISAX_FRITZPCI=y
++CONFIG_HISAX_AVM_A1_PCMCIA=y
++CONFIG_HISAX_ELSA=y
++CONFIG_HISAX_DIEHLDIVA=y
++CONFIG_HISAX_SEDLBAUER=y
++CONFIG_HISAX_NETJET=y
++CONFIG_HISAX_NETJET_U=y
++CONFIG_HISAX_NICCY=y
++CONFIG_HISAX_BKM_A4T=y
++CONFIG_HISAX_SCT_QUADRO=y
++CONFIG_HISAX_GAZEL=y
++CONFIG_HISAX_HFC_PCI=y
++CONFIG_HISAX_W6692=y
++CONFIG_HISAX_HFC_SX=y
++CONFIG_HISAX_ENTERNOW_PCI=y
++# CONFIG_HISAX_DEBUG is not set
++CONFIG_HISAX_AVM_A1_CS=m
++CONFIG_HISAX_ST5481=m
++# CONFIG_HISAX_HFCUSB is not set
++CONFIG_HISAX_FRITZ_PCIPNP=m
++CONFIG_HISAX_NO_SENDCOMPLETE=y
++CONFIG_HISAX_NO_LLC=y
++CONFIG_HISAX_NO_KEYPAD=y
++CONFIG_HISAX_SEDLBAUER_CS=m
++CONFIG_HISAX_ELSA_CS=m
++CONFIG_HISAX_TELES_CS=m
++CONFIG_HISAX_HFC4S8S=m
++
++CONFIG_ISDN_DRV_LOOP=m
++CONFIG_HYSDN=m
++CONFIG_HYSDN_CAPI=y
++
++
++#
++# CAPI subsystem
++#
++CONFIG_ISDN_CAPI=m
++# CONFIG_CAPI_TRACE is not set
++CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y
++CONFIG_ISDN_CAPI_MIDDLEWARE=y
++CONFIG_ISDN_CAPI_CAPI20=m
++
++#
++# CAPI hardware drivers
++#
++
++#
++# Active AVM cards
++#
++CONFIG_CAPI_AVM=y
++
++#
++# Active Eicon DIVA Server cards
++#
++# CONFIG_CAPI_EICON is not set
++CONFIG_ISDN_DIVAS=m
++CONFIG_ISDN_DIVAS_BRIPCI=y
++CONFIG_ISDN_DIVAS_PRIPCI=y
++CONFIG_ISDN_DIVAS_DIVACAPI=m
++CONFIG_ISDN_DIVAS_USERIDI=m
++CONFIG_ISDN_DIVAS_MAINT=m
++
++CONFIG_ISDN_DRV_GIGASET=m
++CONFIG_GIGASET_CAPI=y
++CONFIG_GIGASET_BASE=m
++CONFIG_GIGASET_M101=m
++CONFIG_GIGASET_M105=m
++# CONFIG_GIGASET_DEBUG is not set
++
++#
++# Telephony Support
++#
++# CONFIG_PHONE is not set
++
++#
++# Input device support
++#
++CONFIG_INPUT=y
++CONFIG_INPUT_FF_MEMLESS=m
++
++#
++# Userland interfaces
++#
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
++CONFIG_INPUT_JOYDEV=m
++# CONFIG_INPUT_MATRIXKMAP is not set
++
++CONFIG_INPUT_TABLET=y
++CONFIG_TABLET_USB_ACECAD=m
++CONFIG_TABLET_USB_AIPTEK=m
++CONFIG_TABLET_USB_GTCO=m
++CONFIG_TABLET_USB_HANWANG=m
++CONFIG_TABLET_USB_KBTAB=m
++CONFIG_TABLET_USB_WACOM=m
++
++CONFIG_INPUT_POWERMATE=m
++CONFIG_INPUT_YEALINK=m
++CONFIG_INPUT_CM109=m
++CONFIG_INPUT_POLLDEV=m
++CONFIG_INPUT_SPARSEKMAP=m
++# CONFIG_INPUT_ADXL34X is not set
++# CONFIG_INPUT_BMA150 is not set
++# CONFIG_INPUT_IMS_PCU is not set
++CONFIG_INPUT_CMA3000=m
++CONFIG_INPUT_CMA3000_I2C=m
++CONFIG_INPUT_IDEAPAD_SLIDEBAR=m
++
++#
++# Input I/O drivers
++#
++CONFIG_GAMEPORT=m
++CONFIG_GAMEPORT_NS558=m
++CONFIG_GAMEPORT_L4=m
++CONFIG_GAMEPORT_EMU10K1=m
++CONFIG_GAMEPORT_FM801=m
++CONFIG_SERIO=y
++CONFIG_SERIO_I8042=y
++CONFIG_SERIO_RAW=m
++CONFIG_SERIO_ALTERA_PS2=m
++# CONFIG_SERIO_PS2MULT is not set
++CONFIG_SERIO_ARC_PS2=m
++# CONFIG_SERIO_APBPS2 is not set
++
++# CONFIG_SERIO_CT82C710 is not set
++# CONFIG_SERIO_OLPC_APSP is not set
++# CONFIG_SERIO_PARKBD is not set
++# CONFIG_SERIO_PCIPS2 is not set
++# CONFIG_SERIO_LIBPS2 is not set
++
++#
++# Input Device Drivers
++#
++CONFIG_INPUT_KEYBOARD=y
++# CONFIG_KEYBOARD_SUNKBD is not set
++# CONFIG_KEYBOARD_SH_KEYSC is not set
++# CONFIG_KEYBOARD_XTKBD is not set
++# CONFIG_KEYBOARD_MATRIX is not set
++# CONFIG_KEYBOARD_NEWTON is not set
++# CONFIG_KEYBOARD_STOWAWAY is not set
++# CONFIG_KEYBOARD_LKKBD is not set
++# CONFIG_KEYBOARD_LM8323 is not set
++# CONFIG_KEYBOARD_LM8333 is not set
++# CONFIG_KEYBOARD_MAX7359 is not set
++# CONFIG_KEYBOARD_ADP5589 is not set
++# CONFIG_KEYBOARD_MPR121 is not set
++# CONFIG_KEYBOARD_QT1070 is not set
++# CONFIG_KEYBOARD_MCS is not set
++# CONFIG_KEYBOARD_OPENCORES is not set
++# CONFIG_KEYBOARD_SAMSUNG is not set
++# CONFIG_KEYBOARD_QT2160 is not set
++# CONFIG_KEYBOARD_TCA6416 is not set
++# CONFIG_KEYBOARD_TCA8418 is not set
++# CONFIG_KEYBOARD_OMAP4 is not set
++CONFIG_INPUT_MOUSE=y
++# CONFIG_MOUSE_PS2_TOUCHKIT is not set
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_MOUSE_PS2_SENTELIC=y
++CONFIG_MOUSE_SERIAL=m
++CONFIG_MOUSE_VSXXXAA=m
++CONFIG_MOUSE_APPLETOUCH=m
++CONFIG_MOUSE_BCM5974=m
++CONFIG_MOUSE_SYNAPTICS_I2C=m
++CONFIG_MOUSE_SYNAPTICS_USB=m
++CONFIG_MOUSE_CYAPA=m
++CONFIG_INPUT_JOYSTICK=y
++CONFIG_JOYSTICK_ANALOG=m
++CONFIG_JOYSTICK_A3D=m
++CONFIG_JOYSTICK_ADI=m
++CONFIG_JOYSTICK_COBRA=m
++CONFIG_JOYSTICK_GF2K=m
++CONFIG_JOYSTICK_GRIP=m
++CONFIG_JOYSTICK_GRIP_MP=m
++CONFIG_JOYSTICK_GUILLEMOT=m
++CONFIG_JOYSTICK_INTERACT=m
++CONFIG_JOYSTICK_SIDEWINDER=m
++CONFIG_JOYSTICK_TMDC=m
++CONFIG_JOYSTICK_IFORCE=m
++CONFIG_JOYSTICK_IFORCE_USB=y
++CONFIG_JOYSTICK_IFORCE_232=y
++CONFIG_JOYSTICK_WARRIOR=m
++CONFIG_JOYSTICK_MAGELLAN=m
++CONFIG_JOYSTICK_SPACEORB=m
++CONFIG_JOYSTICK_SPACEBALL=m
++CONFIG_JOYSTICK_STINGER=m
++CONFIG_JOYSTICK_DB9=m
++CONFIG_JOYSTICK_GAMECON=m
++CONFIG_JOYSTICK_TURBOGRAFX=m
++CONFIG_JOYSTICK_JOYDUMP=m
++CONFIG_JOYSTICK_TWIDJOY=m
++CONFIG_JOYSTICK_WALKERA0701=m
++CONFIG_JOYSTICK_XPAD=m
++CONFIG_JOYSTICK_XPAD_FF=y
++CONFIG_JOYSTICK_XPAD_LEDS=y
++CONFIG_JOYSTICK_ZHENHUA=m
++# CONFIG_JOYSTICK_AS5011 is not set
++
++CONFIG_INPUT_TOUCHSCREEN=y
++# CONFIG_TOUCHSCREEN_AD7879 is not set
++CONFIG_TOUCHSCREEN_AD7879_I2C=m
++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
++CONFIG_TOUCHSCREEN_DYNAPRO=m
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_TOUCHSCREEN_EETI=m
++CONFIG_TOUCHSCREEN_EGALAX=m
++CONFIG_TOUCHSCREEN_ELO=m
++CONFIG_TOUCHSCREEN_FUJITSU=m
++CONFIG_TOUCHSCREEN_GUNZE=m
++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
++CONFIG_TOUCHSCREEN_INEXIO=m
++CONFIG_TOUCHSCREEN_ILI210X=m
++CONFIG_TOUCHSCREEN_MMS114=m
++CONFIG_TOUCHSCREEN_MTOUCH=m
++CONFIG_TOUCHSCREEN_MCS5000=m
++CONFIG_TOUCHSCREEN_MK712=m
++CONFIG_TOUCHSCREEN_PENMOUNT=m
++# CONFIG_TOUCHSCREEN_SUR40 is not set
++# CONFIG_TOUCHSCREEN_TPS6507X is not set
++CONFIG_TOUCHSCREEN_TSC_SERIO=m
++CONFIG_TOUCHSCREEN_TSC2007=m
++CONFIG_TOUCHSCREEN_TOUCHIT213=m
++CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
++CONFIG_TOUCHSCREEN_TOUCHWIN=m
++CONFIG_TOUCHSCREEN_PIXCIR=m
++CONFIG_TOUCHSCREEN_UCB1400=m
++CONFIG_TOUCHSCREEN_WACOM_W8001=m
++CONFIG_TOUCHSCREEN_WACOM_I2C=m
++CONFIG_TOUCHSCREEN_USB_E2I=y
++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m
++# CONFIG_TOUCHSCREEN_WM97XX is not set
++CONFIG_TOUCHSCREEN_W90X900=m
++# CONFIG_TOUCHSCREEN_BU21013 is not set
++CONFIG_TOUCHSCREEN_ST1232=m
++CONFIG_TOUCHSCREEN_ATMEL_MXT=m
++# CONFIG_TOUCHSCREEN_MAX11801 is not set
++CONFIG_TOUCHSCREEN_AUO_PIXCIR=m
++CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m
++CONFIG_TOUCHSCREEN_ZFORCE=m
++
++CONFIG_INPUT_PCSPKR=m
++CONFIG_INPUT_RETU_PWRBUTTON=m
++CONFIG_INPUT_UINPUT=m
++CONFIG_INPUT_WISTRON_BTNS=m
++CONFIG_INPUT_ATLAS_BTNS=m
++
++CONFIG_INPUT_ATI_REMOTE2=m
++CONFIG_INPUT_KEYSPAN_REMOTE=m
++
++CONFIG_MAC_EMUMOUSEBTN=y
++
++CONFIG_INPUT_WM831X_ON=m
++
++
++# CONFIG_INPUT_AD714X is not set
++# CONFIG_INPUT_PCF8574 is not set
++CONFIG_INPUT_MMA8450=m
++CONFIG_INPUT_MPU3050=m
++CONFIG_INPUT_KXTJ9=m
++# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set
++
++#
++# Character devices
++#
++CONFIG_VT=y
++CONFIG_VT_CONSOLE=y
++CONFIG_HW_CONSOLE=y
++CONFIG_SERIAL_NONSTANDARD=y
++CONFIG_ROCKETPORT=m
++CONFIG_SYNCLINK=m
++CONFIG_SYNCLINKMP=m
++CONFIG_SYNCLINK_GT=m
++CONFIG_N_HDLC=m
++CONFIG_N_GSM=m
++# CONFIG_TRACE_SINK is not set
++# CONFIG_STALDRV is not set
++# CONFIG_DUMMY_IRQ is not set
++# CONFIG_IBM_ASM is not set
++CONFIG_TIFM_CORE=m
++CONFIG_TIFM_7XX1=m
++CONFIG_TCG_TPM=m
++CONFIG_TCG_TIS=m
++# CONFIG_TCG_TIS_I2C_INFINEON is not set
++# CONFIG_TCG_TIS_I2C_ATMEL is not set
++# CONFIG_TCG_TIS_I2C_NUVOTON is not set
++CONFIG_TCG_NSC=m
++CONFIG_TCG_ATMEL=m
++# CONFIG_TCG_INFINEON is not set
++# CONFIG_TCG_ST33_I2C is not set
++# CONFIG_TCG_XEN is not set
++CONFIG_TELCLOCK=m
++
++#
++# Serial drivers
++#
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_CS=m
++CONFIG_SERIAL_8250_NR_UARTS=32
++CONFIG_SERIAL_8250_RUNTIME_UARTS=4
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_MANY_PORTS=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++# CONFIG_SERIAL_8250_DETECT_IRQ is not set
++CONFIG_SERIAL_8250_RSA=y
++# CONFIG_SERIAL_8250_DW is not set
++CONFIG_CYCLADES=m
++# CONFIG_CYZ_INTR is not set
++# CONFIG_MOXA_INTELLIO is not set
++# CONFIG_MOXA_SMARTIO is not set
++# CONFIG_ISI is not set
++# CONFIG_RIO is not set
++CONFIG_SERIAL_JSM=m
++# CONFIG_SERIAL_SCCNXP is not set
++# CONFIG_SERIAL_MFD_HSU is not set
++
++# CONFIG_SERIAL_ALTERA_JTAGUART is not set
++# CONFIG_SERIAL_ALTERA_UART is not set
++
++#
++# Non-8250 serial port support
++#
++CONFIG_SERIAL_CORE=y
++CONFIG_SERIAL_CORE_CONSOLE=y
++# CONFIG_SERIAL_XILINX_PS_UART is not set
++# CONFIG_SERIAL_TIMBERDALE is not set
++CONFIG_SERIAL_ARC=m
++CONFIG_SERIAL_ARC_NR_PORTS=1
++# CONFIG_SERIAL_RP2 is not set
++# CONFIG_SERIAL_ST_ASC is not set
++# CONFIG_SERIAL_PCH_UART is not set
++
++CONFIG_UNIX98_PTYS=y
++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
++CONFIG_PRINTER=m
++CONFIG_LP_CONSOLE=y
++CONFIG_PPDEV=m
++
++#
++# I2C support
++#
++CONFIG_I2C=y
++# CONFIG_I2C_MUX is not set
++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
++# CONFIG_I2C_MUX_PCA954x is not set
++# CONFIG_I2C_MUX_GPIO is not set
++# CONFIG_I2C_MUX_PCA9541 is not set
++# CONFIG_I2C_MUX_PINCTRL is not set
++#
++
++#
++# I2C Algorithms
++#
++# CONFIG_I2C_DEBUG_ALGO is not set
++CONFIG_I2C_ALGOBIT=m
++
++#
++# I2C Hardware Bus support
++#
++
++# CONFIG_I2C_ALI1535 is not set
++# CONFIG_I2C_ALI1563 is not set
++# CONFIG_I2C_ALI15X3 is not set
++# CONFIG_I2C_AMD756 is not set
++# CONFIG_I2C_AMD756_S4882 is not set
++# CONFIG_I2C_AMD8111 is not set
++# CONFIG_I2C_DEBUG_CORE is not set
++# CONFIG_I2C_DEBUG_BUS is not set
++# CONFIG_I2C_I801 is not set
++# CONFIG_I2C_ISCH is not set
++# CONFIG_I2C_NFORCE2_S4985 is not set
++# CONFIG_I2C_INTEL_MID is not set
++# CONFIG_I2C_EG20T is not set
++# CONFIG_I2C_CBUS_GPIO is not set
++CONFIG_I2C_VIPERBOARD=m
++
++CONFIG_EEPROM_AT24=m
++CONFIG_EEPROM_LEGACY=m
++CONFIG_EEPROM_93CX6=m
++CONFIG_EEPROM_MAX6875=m
++
++CONFIG_I2C_NFORCE2=m
++# CONFIG_I2C_OCORES is not set
++CONFIG_I2C_PARPORT=m
++CONFIG_I2C_PARPORT_LIGHT=m
++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set
++CONFIG_I2C_PASEMI=m
++CONFIG_I2C_PCA_PLATFORM=m
++# CONFIG_I2C_PIIX4 is not set
++# CONFIG_SCx200_ACB is not set
++# CONFIG_I2C_SIS5595 is not set
++# CONFIG_I2C_SIS630 is not set
++# CONFIG_I2C_SIS96X is not set
++CONFIG_I2C_SIMTEC=m
++CONFIG_I2C_STUB=m
++CONFIG_I2C_TINY_USB=m
++# CONFIG_I2C_TAOS_EVM is not set
++# CONFIG_I2C_VIA is not set
++# CONFIG_I2C_VIAPRO is not set
++# CONFIG_I2C_DESIGNWARE is not set
++# CONFIG_I2C_XILINX is not set
++
++CONFIG_I2C_DIOLAN_U2C=m
++
++#
++# I2C Hardware Sensors Chip support
++#
++CONFIG_SENSORS_ATK0110=m
++CONFIG_SENSORS_ABITUGURU=m
++CONFIG_SENSORS_ABITUGURU3=m
++CONFIG_SENSORS_AD7414=m
++CONFIG_SENSORS_AD7418=m
++CONFIG_SENSORS_ADM1021=m
++CONFIG_SENSORS_ADM1025=m
++CONFIG_SENSORS_ADM1026=m
++CONFIG_SENSORS_ADM1029=m
++CONFIG_SENSORS_ADM1031=m
++CONFIG_SENSORS_ADM9240=m
++CONFIG_SENSORS_ADT7310=m
++CONFIG_SENSORS_ADT7410=m
++CONFIG_SENSORS_ADS7828=m
++CONFIG_SENSORS_ADT7462=m
++CONFIG_SENSORS_ADT7470=m
++CONFIG_SENSORS_ADT7475=m
++CONFIG_SENSORS_APPLESMC=m
++CONFIG_SENSORS_ASB100=m
++CONFIG_SENSORS_ATXP1=m
++CONFIG_SENSORS_CORETEMP=m
++CONFIG_SENSORS_DME1737=m
++CONFIG_SENSORS_DS1621=m
++# CONFIG_DS1682 is not set
++CONFIG_SENSORS_F71805F=m
++CONFIG_SENSORS_F71882FG=m
++CONFIG_SENSORS_F75375S=m
++CONFIG_SENSORS_FSCHMD=m
++CONFIG_SENSORS_G760A=m
++CONFIG_SENSORS_G762=m
++CONFIG_SENSORS_GL518SM=m
++CONFIG_SENSORS_GL520SM=m
++CONFIG_SENSORS_HDAPS=m
++# CONFIG_SENSORS_HIH6130 is not set
++# CONFIG_SENSORS_HTU21 is not set
++# CONFIG_SENSORS_I5K_AMB is not set
++# FIXME: IBMAEM x86 only?
++CONFIG_SENSORS_IBMAEM=m
++CONFIG_SENSORS_IBMPEX=m
++# CONFIG_SENSORS_IIO_HWMON is not set
++CONFIG_SENSORS_IT87=m
++CONFIG_SENSORS_K8TEMP=m
++CONFIG_SENSORS_K10TEMP=m
++CONFIG_SENSORS_LIS3LV02D=m
++CONFIG_SENSORS_LIS3_SPI=m
++CONFIG_SENSORS_LIS3_I2C=m
++CONFIG_SENSORS_LM63=m
++CONFIG_SENSORS_LM75=m
++CONFIG_SENSORS_LM77=m
++CONFIG_SENSORS_LM78=m
++CONFIG_SENSORS_LM80=m
++CONFIG_SENSORS_LM83=m
++CONFIG_SENSORS_LM85=m
++CONFIG_SENSORS_LM87=m
++CONFIG_SENSORS_LM90=m
++CONFIG_SENSORS_LM92=m
++CONFIG_SENSORS_LM93=m
++CONFIG_SENSORS_LM95234=m
++CONFIG_SENSORS_LTC4245=m
++CONFIG_SENSORS_MAX1619=m
++CONFIG_SENSORS_MAX6650=m
++CONFIG_SENSORS_MAX6697=m
++CONFIG_SENSORS_MCP3021=m
++CONFIG_SENSORS_NCT6775=m
++CONFIG_SENSORS_NTC_THERMISTOR=m
++CONFIG_SENSORS_PC87360=m
++CONFIG_SENSORS_PC87427=m
++CONFIG_SENSORS_PCF8591=m
++CONFIG_SENSORS_SHT15=m
++CONFIG_SENSORS_SIS5595=m
++CONFIG_CHARGER_SMB347=m
++CONFIG_SENSORS_SMSC47M1=m
++CONFIG_SENSORS_SMSC47M192=m
++CONFIG_SENSORS_SMSC47B397=m
++CONFIG_SENSORS_THMC50=m
++CONFIG_SENSORS_TMP401=m
++CONFIG_APDS9802ALS=m
++CONFIG_ISL29020=m
++CONFIG_ISL29003=m
++CONFIG_SENSORS_BH1770=m
++CONFIG_SENSORS_APDS990X=m
++CONFIG_SENSORS_TSL2550=m
++CONFIG_SENSORS_VIA686A=m
++CONFIG_SENSORS_VIA_CPUTEMP=m
++CONFIG_SENSORS_VT1211=m
++CONFIG_SENSORS_VT8231=m
++CONFIG_SENSORS_W83627HF=m
++CONFIG_SENSORS_W83781D=m
++CONFIG_SENSORS_W83L785TS=m
++CONFIG_SENSORS_W83L786NG=m
++CONFIG_SENSORS_W83627EHF=m
++CONFIG_SENSORS_W83791D=m
++CONFIG_SENSORS_W83792D=m
++CONFIG_SENSORS_W83793=m
++CONFIG_SENSORS_LTC4215=m
++CONFIG_SENSORS_LM95241=m
++CONFIG_SENSORS_LM95245=m
++CONFIG_SENSORS_TMP421=m
++CONFIG_SENSORS_WM8350=m
++CONFIG_SENSORS_WM831X=m
++CONFIG_SENSORS_LM73=m
++CONFIG_SENSORS_AMC6821=m
++CONFIG_SENSORS_INA2XX=m
++CONFIG_SENSORS_INA209=m
++CONFIG_SENSORS_ADT7411=m
++CONFIG_SENSORS_ASC7621=m
++CONFIG_SENSORS_EMC1403=m
++CONFIG_SENSORS_TMP102=m
++CONFIG_SENSORS_LTC4261=m
++# CONFIG_SENSORS_BH1780 is not set
++# CONFIG_SENSORS_JC42 is not set
++# CONFIG_SENSORS_SMM665 is not set
++# CONFIG_SENSORS_EMC2103 is not set
++# CONFIG_SENSORS_GPIO_FAN is not set
++CONFIG_SENSORS_W83795=m
++# CONFIG_SENSORS_W83795_FANCTRL is not set
++CONFIG_SENSORS_DS620=m
++CONFIG_SENSORS_SHT21=m
++CONFIG_SENSORS_LINEAGE=m
++CONFIG_SENSORS_LTC4151=m
++CONFIG_SENSORS_MAX6639=m
++CONFIG_SENSORS_SCH5627=m
++CONFIG_SENSORS_SCH5636=m
++CONFIG_SENSORS_ADS1015=m
++CONFIG_SENSORS_MAX16065=m
++CONFIG_SENSORS_MAX6642=m
++CONFIG_SENSORS_ADM1275=m
++CONFIG_SENSORS_UCD9000=m
++CONFIG_SENSORS_UCD9200=m
++CONFIG_SENSORS_ZL6100=m
++CONFIG_SENSORS_EMC6W201=m
++
++CONFIG_PMBUS=m
++CONFIG_SENSORS_PMBUS=m
++CONFIG_SENSORS_MAX16064=m
++CONFIG_SENSORS_LM25066=m
++CONFIG_SENSORS_LTC2978=m
++CONFIG_SENSORS_MAX34440=m
++CONFIG_SENSORS_MAX8688=m
++CONFIG_SENSORS_MAX1668=m
++CONFIG_SENSORS_MAX197=m
++
++# Industrial I/O subsystem configuration
++CONFIG_IIO=m
++CONFIG_IIO_BUFFER=y
++CONFIG_IIO_BUFFER_CB=y
++# CONFIG_IIO_KFIFO_BUF is not set
++CONFIG_IIO_TRIGGERED_BUFFER=m
++CONFIG_IIO_TRIGGER=y
++CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
++CONFIG_IIO_INTERRUPT_TRIGGER=m
++CONFIG_HID_SENSOR_IIO_COMMON=m
++CONFIG_HID_SENSOR_IIO_TRIGGER=m
++CONFIG_HID_SENSOR_ENUM_BASE_QUIRKS=y
++# CONFIG_IIO_SYSFS_TRIGGER is not set
++# CONFIG_AD5446 is not set
++# CONFIG_AD5380 is not set
++# CONFIG_AD5064 is not set
++# CONFIG_BMA180 is not set
++# CONFIG_MAX1363 is not set
++# CONFIG_MAX517 is not set
++# CONFIG_MCP4725 is not set
++# CONFIG_ITG3200 is not set
++# CONFIG_APDS9300 is not set
++# CONFIG_CM32181 is not set
++# CONFIG_CM36651 is not set
++# CONFIG_GP2AP020A00F is not set
++# CONFIG_TSL2583 is not set
++# CONFIG_TSL2x7x is not set
++# CONFIG_TCS3472 is not set
++# CONFIG_TSL4531 is not set
++# CONFIG_NAU7802 is not set
++# CONFIG_TI_ADC081C is not set
++# CONFIG_EXYNOS_ADC is not set
++# CONFIG_VIPERBOARD_ADC is not set
++# CONFIG_INV_MPU6050_IIO is not set
++CONFIG_IIO_ST_GYRO_3AXIS=m
++CONFIG_IIO_ST_MAGN_3AXIS=m
++CONFIG_IIO_ST_ACCEL_3AXIS=m
++CONFIG_HID_SENSOR_INCLINOMETER_3D=m
++# CONFIG_ADJD_S311 is not set
++# CONFIG_SENSORS_TSL2563 is not set
++# CONFIG_VCNL4000 is not set
++# CONFIG_AK8975 is not set
++# CONFIG_MAG3110 is not set
++# CONFIG_TMP006 is not set
++# CONFIG_IIO_ST_PRESS is not set
++# CONFIG_KXSD9 is not set
++# CONFIG_AD7266 is not set
++# CONFIG_AD7298 is not set
++# CONFIG_AD7476 is not set
++# CONFIG_AD7791 is not set
++# CONFIG_AD7793 is not set
++# CONFIG_AD7887 is not set
++# CONFIG_AD7923 is not set
++# CONFIG_MCP320X is not set
++# CONFIG_MCP3422 is not set
++# CONFIG_AD8366 is not set
++# CONFIG_AD5360 is not set
++# CONFIG_AD5421 is not set
++# CONFIG_AD5449 is not set
++# CONFIG_AD5504 is not set
++# CONFIG_AD5624R_SPI is not set
++# CONFIG_AD5686 is not set
++# CONFIG_AD5755 is not set
++# CONFIG_AD5764 is not set
++# CONFIG_AD5791 is not set
++# CONFIG_AD7303 is not set
++# CONFIG_AD9523 is not set
++# CONFIG_ADF4350 is not set
++# CONFIG_ADIS16080 is not set
++# CONFIG_ADIS16130 is not set
++# CONFIG_ADIS16136 is not set
++# CONFIG_ADIS16260 is not set
++# CONFIG_ADXRS450 is not set
++# CONFIG_ADIS16400 is not set
++# CONFIG_ADIS16480 is not set
++# CONFIG_DHT11 is not set
++# CONFIG_MPL3115 is not set
++
++# staging IIO drivers
++# CONFIG_AD7291 is not set
++# CONFIG_AD7606 is not set
++# CONFIG_AD799X is not set
++# CONFIG_ADT7316 is not set
++# CONFIG_AD7150 is not set
++# CONFIG_AD7152 is not set
++# CONFIG_AD7746 is not set
++# CONFIG_AD5933 is not set
++# CONFIG_ADE7854 is not set
++# CONFIG_SENSORS_ISL29018 is not set
++# CONFIG_SENSORS_ISL29028 is not set
++# CONFIG_SENSORS_HMC5843 is not set
++# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set
++# CONFIG_IIO_SIMPLE_DUMMY is not set
++# CONFIG_ADIS16201 is not set
++# CONFIG_ADIS16203 is not set
++# CONFIG_ADIS16204 is not set
++# CONFIG_ADIS16209 is not set
++# CONFIG_ADIS16220 is not set
++# CONFIG_ADIS16240 is not set
++# CONFIG_LIS3L02DQ is not set
++# CONFIG_SCA3000 is not set
++# CONFIG_AD7780 is not set
++# CONFIG_AD7816 is not set
++# CONFIG_AD7192 is not set
++# CONFIG_AD7280 is not set
++# CONFIG_AD5930 is not set
++# CONFIG_AD9832 is not set
++# CONFIG_AD9834 is not set
++# CONFIG_AD9850 is not set
++# CONFIG_AD9852 is not set
++# CONFIG_AD9910 is not set
++# CONFIG_AD9951 is not set
++# CONFIG_ADIS16060 is not set
++# CONFIG_ADE7753 is not set
++# CONFIG_ADE7754 is not set
++# CONFIG_ADE7758 is not set
++# CONFIG_ADE7759 is not set
++# CONFIG_AD2S90 is not set
++# CONFIG_AD2S1200 is not set
++# CONFIG_AD2S1210 is not set
++
++
++
++# CONFIG_HMC6352 is not set
++# CONFIG_BMP085 is not set
++# CONFIG_BMP085_I2C is not set
++# CONFIG_PCH_PHUB is not set
++# CONFIG_USB_SWITCH_FSA9480 is not set
++
++CONFIG_W1=m
++CONFIG_W1_CON=y
++# CONFIG_W1_MASTER_MATROX is not set
++CONFIG_W1_MASTER_DS2490=m
++CONFIG_W1_MASTER_DS2482=m
++CONFIG_W1_MASTER_DS1WM=m
++CONFIG_W1_MASTER_GPIO=m
++# CONFIG_HDQ_MASTER_OMAP is not set
++CONFIG_W1_SLAVE_THERM=m
++CONFIG_W1_SLAVE_SMEM=m
++CONFIG_W1_SLAVE_DS2408=m
++# CONFIG_W1_SLAVE_DS2408_READBACK is not set
++CONFIG_W1_SLAVE_DS2413=m
++CONFIG_W1_SLAVE_DS2423=m
++CONFIG_W1_SLAVE_DS2431=m
++CONFIG_W1_SLAVE_DS2433=m
++CONFIG_W1_SLAVE_DS2433_CRC=y
++CONFIG_W1_SLAVE_DS2760=m
++CONFIG_W1_SLAVE_DS2780=m
++CONFIG_W1_SLAVE_DS2781=m
++CONFIG_W1_SLAVE_DS28E04=m
++CONFIG_W1_SLAVE_BQ27000=m
++
++#
++# Mice
++#
++
++#
++# IPMI
++#
++CONFIG_IPMI_HANDLER=m
++# CONFIG_IPMI_PANIC_EVENT is not set
++CONFIG_IPMI_DEVICE_INTERFACE=m
++CONFIG_IPMI_WATCHDOG=m
++CONFIG_IPMI_SI=m
++CONFIG_IPMI_POWEROFF=m
++
++#
++# Watchdog Cards
++#
++CONFIG_WATCHDOG_CORE=y
++# CONFIG_WATCHDOG_NOWAYOUT is not set
++CONFIG_SOFT_WATCHDOG=m
++CONFIG_WDTPCI=m
++# CONFIG_ACQUIRE_WDT is not set
++# CONFIG_ADVANTECH_WDT is not set
++# CONFIG_EUROTECH_WDT is not set
++CONFIG_IB700_WDT=m
++# CONFIG_SCx200_WDT is not set
++# CONFIG_60XX_WDT is not set
++CONFIG_W83877F_WDT=m
++CONFIG_W83627HF_WDT=m
++CONFIG_MACHZ_WDT=m
++# CONFIG_SC520_WDT is not set
++CONFIG_ALIM7101_WDT=m
++CONFIG_ALIM1535_WDT=m
++CONFIG_IT87_WDT=m
++CONFIG_ITCO_WDT=m
++CONFIG_ITCO_VENDOR_SUPPORT=y
++# CONFIG_SC1200_WDT is not set
++# CONFIG_PC87413_WDT is not set
++# CONFIG_WAFER_WDT is not set
++# CONFIG_CPU5_WDT is not set
++CONFIG_I6300ESB_WDT=m
++CONFIG_IT8712F_WDT=m
++# CONFIG_SBC8360_WDT is not set
++# CONFIG_SBC7240_WDT is not set
++CONFIG_SMSC_SCH311X_WDT=m
++CONFIG_W83977F_WDT=m
++CONFIG_PCIPCWATCHDOG=m
++CONFIG_USBPCWATCHDOG=m
++# CONFIG_SBC_EPX_C3_WATCHDOG is not set
++CONFIG_WM8350_WATCHDOG=m
++CONFIG_WM831X_WATCHDOG=m
++# CONFIG_MAX63XX_WATCHDOG is not set
++# CONFIG_DW_WATCHDOG is not set
++CONFIG_W83697UG_WDT=m
++# CONFIG_MEN_A21_WDT is not set
++# CONFIG_GPIO_WATCHDOG is not set
++
++CONFIG_HW_RANDOM=y
++CONFIG_HW_RANDOM_TIMERIOMEM=m
++CONFIG_HW_RANDOM_TPM=m
++# CONFIG_HW_RANDOM_ATMEL is not set
++# CONFIG_HW_RANDOM_EXYNOS is not set
++# CONFIG_NVRAM is not set
++# CONFIG_RTC is not set
++# CONFIG_RTC_DEBUG is not set
++# CONFIG_GEN_RTC is not set
++CONFIG_RTC_HCTOSYS=y
++# CONFIG_RTC_SYSTOHC is not set
++CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
++CONFIG_RTC_INTF_SYSFS=y
++CONFIG_RTC_INTF_PROC=y
++CONFIG_RTC_INTF_DEV=y
++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
++CONFIG_RTC_DRV_CMOS=y
++CONFIG_RTC_DRV_DS1307=m
++CONFIG_RTC_DRV_DS1511=m
++CONFIG_RTC_DRV_DS1553=m
++CONFIG_RTC_DRV_DS1672=m
++CONFIG_RTC_DRV_DS1742=m
++CONFIG_RTC_DRV_DS1374=m
++# CONFIG_RTC_DRV_EP93XX is not set
++CONFIG_RTC_DRV_FM3130=m
++CONFIG_RTC_DRV_ISL1208=m
++CONFIG_RTC_DRV_M41T80=m
++CONFIG_RTC_DRV_M41T80_WDT=y
++CONFIG_RTC_DRV_M48T59=m
++CONFIG_RTC_DRV_MAX6900=m
++# CONFIG_RTC_DRV_M48T86 is not set
++CONFIG_RTC_DRV_PCF2127=m
++CONFIG_RTC_DRV_PCF8563=m
++CONFIG_RTC_DRV_PCF8583=m
++CONFIG_RTC_DRV_RS5C372=m
++# CONFIG_RTC_DRV_SA1100 is not set
++# CONFIG_RTC_DRV_TEST is not set
++CONFIG_RTC_DRV_X1205=m
++CONFIG_RTC_DRV_V3020=m
++CONFIG_RTC_DRV_DS2404=m
++CONFIG_RTC_DRV_STK17TA8=m
++# CONFIG_RTC_DRV_S35390A is not set
++CONFIG_RTC_DRV_RX8581=m
++CONFIG_RTC_DRV_RX8025=m
++CONFIG_RTC_DRV_DS1286=m
++CONFIG_RTC_DRV_M48T35=m
++CONFIG_RTC_DRV_BQ4802=m
++CONFIG_RTC_DRV_WM8350=m
++# CONFIG_RTC_DRV_AB3100 is not set
++CONFIG_RTC_DRV_WM831X=m
++CONFIG_RTC_DRV_BQ32K=m
++CONFIG_RTC_DRV_MSM6242=m
++CONFIG_RTC_DRV_RP5C01=m
++CONFIG_RTC_DRV_EM3027=m
++CONFIG_RTC_DRV_RV3029C2=m
++CONFIG_RTC_DRV_PCF50633=m
++CONFIG_RTC_DRV_DS3232=m
++CONFIG_RTC_DRV_ISL12022=m
++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
++# CONFIG_RTC_DRV_MOXART is not set
++# CONFIG_RTC_DRV_ISL12057 is not set
++
++CONFIG_R3964=m
++# CONFIG_APPLICOM is not set
++# CONFIG_SONYPI is not set
++
++#
++# Ftape, the floppy tape device driver
++#
++CONFIG_AGP=y
++CONFIG_AGP_ALI=y
++CONFIG_AGP_ATI=y
++CONFIG_AGP_AMD=y
++CONFIG_AGP_AMD64=y
++CONFIG_AGP_INTEL=y
++CONFIG_AGP_NVIDIA=y
++CONFIG_AGP_SIS=y
++CONFIG_AGP_SWORKS=y
++CONFIG_AGP_VIA=y
++CONFIG_AGP_EFFICEON=y
++
++CONFIG_VGA_ARB=y
++CONFIG_VGA_ARB_MAX_GPUS=16
++
++# CONFIG_STUB_POULSBO is not set
++
++#
++# PCMCIA character devices
++#
++# CONFIG_SYNCLINK_CS is not set
++
++CONFIG_CARDMAN_4000=m
++CONFIG_CARDMAN_4040=m
++
++CONFIG_MWAVE=m
++CONFIG_RAW_DRIVER=y
++CONFIG_MAX_RAW_DEVS=8192
++CONFIG_HANGCHECK_TIMER=m
++
++CONFIG_MEDIA_PCI_SUPPORT=y
++#
++# Multimedia devices
++#
++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_MEDIA_CONTROLLER=y
++CONFIG_VIDEO_DEV=m
++# CONFIG_VIDEO_ADV_DEBUG is not set
++CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
++CONFIG_VIDEO_V4L2=y
++CONFIG_VIDEO_V4L2_SUBDEV_API=y
++# CONFIG_VIDEO_VIVI is not set
++# CONFIG_USB_SI4713 is not set
++# CONFIG_PLATFORM_SI4713 is not set
++# CONFIG_I2C_SI4713 is not set
++# CONFIG_USB_RAREMONO is not set
++
++#
++# Video For Linux
++#
++
++#
++# Video Adapters
++#
++CONFIG_V4L_USB_DRIVERS=y
++CONFIG_VIDEO_CAPTURE_DRIVERS=y
++CONFIG_V4L_PCI_DRIVERS=y
++CONFIG_VIDEO_AU0828=m
++CONFIG_VIDEO_AU0828_V4L2=y
++CONFIG_VIDEO_BT848=m
++CONFIG_VIDEO_BT848_DVB=y
++CONFIG_VIDEO_BWQCAM=m
++CONFIG_VIDEO_SR030PC30=m
++CONFIG_VIDEO_NOON010PC30=m
++CONFIG_VIDEO_CAFE_CCIC=m
++# CONFIG_VIDEO_CPIA is not set
++CONFIG_VIDEO_CPIA2=m
++CONFIG_VIDEO_CQCAM=m
++CONFIG_VIDEO_CX23885=m
++CONFIG_MEDIA_ALTERA_CI=m
++CONFIG_VIDEO_CX18=m
++CONFIG_VIDEO_CX18_ALSA=m
++CONFIG_VIDEO_CX88=m
++CONFIG_VIDEO_CX88_DVB=m
++CONFIG_VIDEO_CX88_ALSA=m
++CONFIG_VIDEO_CX88_BLACKBIRD=m
++CONFIG_VIDEO_CX88_ENABLE_VP3054=y
++CONFIG_VIDEO_CX88_VP3054=m
++CONFIG_VIDEO_EM28XX=m
++CONFIG_VIDEO_EM28XX_V4L2=m
++CONFIG_VIDEO_EM28XX_ALSA=m
++CONFIG_VIDEO_EM28XX_DVB=m
++CONFIG_VIDEO_EM28XX_RC=y
++CONFIG_VIDEO_CX231XX=m
++CONFIG_VIDEO_CX231XX_ALSA=m
++CONFIG_VIDEO_CX231XX_DVB=m
++CONFIG_VIDEO_CX231XX_RC=y
++CONFIG_VIDEO_HEXIUM_ORION=m
++CONFIG_VIDEO_HEXIUM_GEMINI=m
++CONFIG_VIDEO_IVTV=m
++# CONFIG_VIDEO_IVTV_ALSA is not set
++CONFIG_VIDEO_MEYE=m
++CONFIG_VIDEO_MXB=m
++CONFIG_VIDEO_PVRUSB2_DVB=y
++# CONFIG_VIDEO_PMS is not set
++CONFIG_VIDEO_HDPVR=m
++CONFIG_VIDEO_SAA6588=m
++CONFIG_VIDEO_SAA7134=m
++CONFIG_VIDEO_SAA7134_ALSA=m
++CONFIG_VIDEO_SAA7134_DVB=m
++CONFIG_VIDEO_SAA7134_RC=y
++CONFIG_VIDEO_USBVISION=m
++CONFIG_VIDEO_STK1160_COMMON=m
++CONFIG_VIDEO_STK1160=m
++CONFIG_VIDEO_STK1160_AC97=y
++CONFIG_VIDEO_W9966=m
++CONFIG_VIDEO_ZORAN=m
++CONFIG_VIDEO_ZORAN_AVS6EYES=m
++CONFIG_VIDEO_ZORAN_BUZ=m
++CONFIG_VIDEO_ZORAN_DC10=m
++CONFIG_VIDEO_ZORAN_DC30=m
++CONFIG_VIDEO_ZORAN_LML33=m
++CONFIG_VIDEO_ZORAN_LML33R10=m
++CONFIG_VIDEO_ZORAN_ZR36060=m
++# CONFIG_V4L_ISA_PARPORT_DRIVERS is not set
++CONFIG_VIDEO_FB_IVTV=m
++CONFIG_VIDEO_SAA7164=m
++CONFIG_VIDEO_TM6000=m
++CONFIG_VIDEO_TM6000_ALSA=m
++CONFIG_VIDEO_TM6000_DVB=m
++CONFIG_VIDEO_TLG2300=m
++CONFIG_VIDEO_USBTV=m
++
++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
++
++#
++# Radio Adapters
++#
++CONFIG_RADIO_MAXIRADIO=m
++CONFIG_RADIO_SHARK=m
++CONFIG_RADIO_SHARK2=m
++CONFIG_RADIO_WL1273=m
++
++CONFIG_MEDIA_ATTACH=y
++
++#
++# V4L/DVB tuners
++# Selected automatically by not setting CONFIG_MEDIA_TUNER_CUSTOMISE
++#
++# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
++
++#
++# Digital Video Broadcasting Devices
++#
++CONFIG_DVB_CAPTURE_DRIVERS=y
++CONFIG_DVB_CORE=m
++CONFIG_DVB_NET=y
++CONFIG_DVB_MAX_ADAPTERS=8
++CONFIG_DVB_DYNAMIC_MINORS=y
++
++#
++# DVB frontends
++# Selected automatically by not setting CONFIG_DVB_FE_CUSTOMISE
++#
++# CONFIG_DVB_FE_CUSTOMISE is not set
++
++#
++# Supported DVB bridge Modules
++#
++CONFIG_DVB_BT8XX=m
++CONFIG_DVB_BUDGET_CORE=m
++CONFIG_DVB_PLUTO2=m
++CONFIG_SMS_SIANO_MDTV=m
++CONFIG_SMS_SIANO_RC=y
++# CONFIG_SMS_SIANO_DEBUGFS is not set
++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y
++CONFIG_SMS_USB_DRV=m
++CONFIG_SMS_SDIO_DRV=m
++CONFIG_DVB_TTUSB_DEC=m
++CONFIG_DVB_USB_DTV5100=m
++CONFIG_DVB_USB_AF9015=m
++CONFIG_DVB_USB_ANYSEE=m
++CONFIG_DVB_USB_DW2102=m
++CONFIG_DVB_USB_FRIIO=m
++CONFIG_DVB_USB_EC168=m
++CONFIG_DVB_USB_PCTV452E=m
++CONFIG_DVB_USB_IT913X=m
++CONFIG_DVB_USB_MXL111SF=m
++CONFIG_DVB_DM1105=m
++CONFIG_DVB_FIREDTV=m
++CONFIG_DVB_NGENE=m
++CONFIG_DVB_DDBRIDGE=m
++CONFIG_DVB_USB_TECHNISAT_USB2=m
++CONFIG_DVB_USB_V2=m
++
++CONFIG_DVB_AV7110=m
++CONFIG_DVB_AV7110_OSD=y
++CONFIG_DVB_BUDGET=m
++CONFIG_DVB_BUDGET_CI=m
++CONFIG_DVB_BUDGET_AV=m
++CONFIG_DVB_BUDGET_PATCH=m
++
++CONFIG_DVB_TTUSB_BUDGET=m
++
++CONFIG_DVB_USB_CINERGY_T2=m
++CONFIG_DVB_B2C2_FLEXCOP=m
++# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set
++
++CONFIG_DVB_B2C2_FLEXCOP_PCI=m
++# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set
++CONFIG_DVB_B2C2_FLEXCOP_USB=m
++# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
++CONFIG_DVB_USB=m
++# CONFIG_DVB_USB_DEBUG is not set
++CONFIG_DVB_USB_A800=m
++CONFIG_DVB_USB_AF9005=m
++CONFIG_DVB_USB_AF9005_REMOTE=m
++CONFIG_DVB_USB_AU6610=m
++CONFIG_DVB_USB_CXUSB=m
++CONFIG_DVB_USB_DIBUSB_MB=m
++# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set
++CONFIG_DVB_USB_DIBUSB_MC=m
++CONFIG_DVB_USB_DIB0700=m
++CONFIG_DVB_USB_DIGITV=m
++CONFIG_DVB_USB_DTT200U=m
++CONFIG_DVB_USB_GL861=m
++CONFIG_DVB_USB_GP8PSK=m
++CONFIG_DVB_USB_M920X=m
++CONFIG_DVB_USB_NOVA_T_USB2=m
++CONFIG_DVB_USB_CE6230=m
++CONFIG_DVB_USB_OPERA1=m
++CONFIG_DVB_USB_TTUSB2=m
++CONFIG_DVB_USB_UMT_010=m
++CONFIG_DVB_USB_VP702X=m
++CONFIG_DVB_USB_VP7045=m
++CONFIG_DVB_USB_AZ6027=m
++CONFIG_DVB_USB_AZ6007=m
++CONFIG_DVB_USB_LME2510=m
++CONFIG_DVB_USB_RTL28XXU=m
++CONFIG_DVB_USB_AF9035=m
++
++CONFIG_DVB_PT1=m
++
++CONFIG_MANTIS_CORE=m
++CONFIG_DVB_MANTIS=m
++CONFIG_DVB_HOPPER=m
++
++CONFIG_VIDEO_SAA7146=m
++CONFIG_VIDEO_SAA7146_VV=m
++CONFIG_VIDEO_TVP5150=m
++CONFIG_VIDEO_TUNER=m
++CONFIG_VIDEO_BTCX=m
++CONFIG_VIDEO_PVRUSB2=m
++CONFIG_VIDEO_PVRUSB2_SYSFS=y
++# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
++
++CONFIG_RC_CORE=m
++CONFIG_RC_DECODERS=y
++CONFIG_LIRC=m
++CONFIG_RC_LOOPBACK=m
++CONFIG_RC_MAP=m
++CONFIG_RC_DEVICES=y
++CONFIG_RC_ATI_REMOTE=m
++CONFIG_IR_NEC_DECODER=m
++CONFIG_IR_RC5_DECODER=m
++CONFIG_IR_RC6_DECODER=m
++CONFIG_IR_JVC_DECODER=m
++CONFIG_IR_SONY_DECODER=m
++CONFIG_IR_RC5_SZ_DECODER=m
++CONFIG_IR_SANYO_DECODER=m
++CONFIG_IR_MCE_KBD_DECODER=m
++CONFIG_IR_LIRC_CODEC=m
++CONFIG_IR_IMON=m
++CONFIG_IR_MCEUSB=m
++CONFIG_IR_ITE_CIR=m
++CONFIG_IR_NUVOTON=m
++CONFIG_IR_FINTEK=m
++CONFIG_IR_REDRAT3=m
++CONFIG_IR_ENE=m
++CONFIG_IR_STREAMZAP=m
++CONFIG_IR_WINBOND_CIR=m
++CONFIG_IR_IGUANA=m
++CONFIG_IR_TTUSBIR=m
++CONFIG_IR_GPIO_CIR=m
++
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set
++# CONFIG_VIDEO_SH_VEU is not set
++# CONFIG_VIDEO_RENESAS_VSP1 is not set
++# CONFIG_V4L_TEST_DRIVERS is not set
++
++# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
++
++#
++# Broadcom Crystal HD video decoder driver
++#
++CONFIG_CRYSTALHD=m
++
++#
++# Graphics support
++#
++
++CONFIG_DISPLAY_SUPPORT=m
++CONFIG_VIDEO_OUTPUT_CONTROL=m
++
++#
++# Console display driver support
++#
++CONFIG_VGA_CONSOLE=y
++CONFIG_VGACON_SOFT_SCROLLBACK=y
++CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
++CONFIG_DUMMY_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++
++#
++# Logo configuration
++#
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_LOGO_LINUX_CLUT224=y
++
++#
++# Sound
++#
++
++#
++# Advanced Linux Sound Architecture
++#
++CONFIG_SOUND_OSS_CORE_PRECLAIM=y
++# CONFIG_SND_DEBUG_VERBOSE is not set
++CONFIG_SND_VERBOSE_PROCFS=y
++CONFIG_SND_SEQUENCER=y
++CONFIG_SND_HRTIMER=y
++CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_SEQUENCER_OSS=y
++CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_PCM_OSS_PLUGINS=y
++CONFIG_SND_RTCTIMER=y
++CONFIG_SND_DYNAMIC_MINORS=y
++CONFIG_SND_MAX_CARDS=32
++# CONFIG_SND_SUPPORT_OLD_API is not set
++
++#
++# Generic devices
++#
++CONFIG_SND_DUMMY=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_VIRMIDI=m
++CONFIG_SND_MTPAV=m
++CONFIG_SND_MTS64=m
++CONFIG_SND_SERIAL_U16550=m
++CONFIG_SND_MPU401=m
++CONFIG_SND_PORTMAN2X4=m
++CONFIG_SND_AC97_POWER_SAVE=y
++CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0
++
++CONFIG_SND_DRIVERS=y
++
++#
++# ISA devices
++#
++CONFIG_SND_AD1889=m
++
++#
++# PCI devices
++#
++CONFIG_SND_PCI=y
++CONFIG_SND_ALI5451=m
++CONFIG_SND_ALS300=m
++CONFIG_SND_ALS4000=m
++CONFIG_SND_ATIIXP=m
++CONFIG_SND_ATIIXP_MODEM=m
++CONFIG_SND_AU8810=m
++CONFIG_SND_AU8820=m
++CONFIG_SND_AU8830=m
++# CONFIG_SND_AW2 is not set
++CONFIG_SND_AZT3328=m
++CONFIG_SND_BT87X=m
++# CONFIG_SND_BT87X_OVERCLOCK is not set
++CONFIG_SND_CA0106=m
++CONFIG_SND_CMIPCI=m
++CONFIG_SND_CS46XX=m
++CONFIG_SND_CS46XX_NEW_DSP=y
++CONFIG_SND_CS4281=m
++CONFIG_SND_CS5530=m
++CONFIG_SND_CS5535AUDIO=m
++CONFIG_SND_EMU10K1=m
++CONFIG_SND_EMU10K1X=m
++CONFIG_SND_ENS1370=m
++CONFIG_SND_ENS1371=m
++CONFIG_SND_ES1938=m
++CONFIG_SND_ES1968=m
++CONFIG_SND_ES1968_INPUT=y
++CONFIG_SND_ES1968_RADIO=y
++CONFIG_SND_FM801=m
++CONFIG_SND_FM801_TEA575X_BOOL=y
++CONFIG_SND_CTXFI=m
++CONFIG_SND_LX6464ES=m
++CONFIG_SND_HDA_INTEL=y
++CONFIG_SND_HDA_INPUT_BEEP=y
++CONFIG_SND_HDA_INPUT_BEEP_MODE=0
++CONFIG_SND_HDA_INPUT_JACK=y
++CONFIG_SND_HDA_PATCH_LOADER=y
++CONFIG_SND_HDA_HWDEP=y
++CONFIG_SND_HDA_CODEC_REALTEK=y
++CONFIG_SND_HDA_ENABLE_REALTEK_QUIRKS=y
++CONFIG_SND_HDA_CODEC_CA0110=y
++CONFIG_SND_HDA_CODEC_ANALOG=y
++CONFIG_SND_HDA_CODEC_SIGMATEL=y
++CONFIG_SND_HDA_CODEC_VIA=y
++CONFIG_SND_HDA_CODEC_CIRRUS=y
++CONFIG_SND_HDA_CODEC_CONEXANT=y
++CONFIG_SND_HDA_CODEC_CMEDIA=y
++CONFIG_SND_HDA_CODEC_SI3054=y
++CONFIG_SND_HDA_CODEC_HDMI=y
++CONFIG_SND_HDA_I915=y
++CONFIG_SND_HDA_CODEC_CA0132=y
++CONFIG_SND_HDA_CODEC_CA0132_DSP=y
++CONFIG_SND_HDA_GENERIC=y
++CONFIG_SND_HDA_POWER_SAVE=y
++CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0
++CONFIG_SND_HDA_RECONFIG=y
++CONFIG_SND_HDA_PREALLOC_SIZE=4096
++CONFIG_SND_HDSPM=m
++CONFIG_SND_ICE1712=m
++CONFIG_SND_ICE1724=m
++CONFIG_SND_INTEL8X0=y
++CONFIG_SND_INTEL8X0M=m
++CONFIG_SND_KORG1212=m
++CONFIG_SND_MAESTRO3=m
++CONFIG_SND_MAESTRO3_INPUT=y
++CONFIG_SND_MIXART=m
++CONFIG_SND_NM256=m
++CONFIG_SND_OXYGEN=m
++CONFIG_SND_RME32=m
++CONFIG_SND_PCSP=m
++CONFIG_SND_PCXHR=m
++CONFIG_SND_RIPTIDE=m
++CONFIG_SND_RME96=m
++CONFIG_SND_RME9652=m
++CONFIG_SND_SIS7019=m
++CONFIG_SND_SONICVIBES=m
++CONFIG_SND_HDSP=m
++CONFIG_SND_TRIDENT=m
++CONFIG_SND_VIA82XX=m
++CONFIG_SND_VIA82XX_MODEM=m
++CONFIG_SND_VIRTUOSO=m
++CONFIG_SND_VX222=m
++CONFIG_SND_YMFPCI=m
++CONFIG_SND_ASIHPI=m
++CONFIG_SND_LOLA=m
++
++#
++# ALSA USB devices
++#
++CONFIG_SND_USB=y
++CONFIG_SND_USB_CAIAQ=m
++CONFIG_SND_USB_CAIAQ_INPUT=y
++CONFIG_SND_USB_USX2Y=m
++CONFIG_SND_USB_US122L=m
++CONFIG_SND_USB_UA101=m
++CONFIG_SND_USB_6FIRE=m
++CONFIG_SND_USB_HIFACE=m
++
++#
++# PCMCIA devices
++#
++# CONFIG_SND_PCMCIA is not set
++
++CONFIG_SND_FIREWIRE=y
++CONFIG_SND_FIREWIRE_SPEAKERS=m
++CONFIG_SND_ISIGHT=m
++CONFIG_SND_SCS1X=m
++CONFIG_SND_DICE=m
++
++#
++# Open Sound System
++#
++# CONFIG_SOUND_PRIME is not set
++
++#
++# USB support
++#
++CONFIG_USB_SUPPORT=y
++# CONFIG_USB_DEBUG is not set
++
++# DEPRECATED: See bug 362221. Fix udev.
++# CONFIG_USB_DEVICE_CLASS is not set
++
++
++#
++# Miscellaneous USB options
++#
++
++# Deprecated.
++# CONFIG_USB_DEVICEFS is not set
++
++CONFIG_USB_DEFAULT_PERSIST=y
++# CONFIG_USB_DYNAMIC_MINORS is not set
++CONFIG_USB_SUSPEND=y
++
++#
++# USB Host Controller Drivers
++#
++CONFIG_USB_EHCI_ROOT_HUB_TT=y
++CONFIG_USB_EHCI_TT_NEWSCHED=y
++# CONFIG_USB_EHCI_MV is not set
++# CONFIG_USB_EHCI_HCD_PLATFORM is not set
++# CONFIG_USB_ISP116X_HCD is not set
++# CONFIG_USB_ISP1760_HCD is not set
++CONFIG_USB_ISP1362_HCD=m
++CONFIG_USB_FUSBH200_HCD=m
++# CONFIG_USB_FOTG210_HCD is not set
++# CONFIG_USB_GR_UDC is not set
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PCI=y
++# CONFIG_USB_OHCI_HCD_SSB is not set
++# CONFIG_USB_HCD_TEST_MODE is not set
++# CONFIG_USB_OHCI_HCD_PLATFORM is not set
++CONFIG_USB_UHCI_HCD=y
++CONFIG_USB_SL811_HCD=m
++CONFIG_USB_SL811_HCD_ISO=y
++# CONFIG_USB_SL811_CS is not set
++# CONFIG_USB_R8A66597_HCD is not set
++CONFIG_USB_XHCI_HCD=y
++# CONFIG_USB_XHCI_HCD_DEBUGGING is not set
++
++#
++# USB Device Class drivers
++#
++
++#
++# USB Bluetooth TTY can only be used with disabled Bluetooth subsystem
++#
++CONFIG_USB_ACM=m
++CONFIG_USB_PRINTER=m
++CONFIG_USB_WDM=m
++CONFIG_USB_TMC=m
++# CONFIG_BLK_DEV_UB is not set
++# CONFIG_USB_STORAGE_DEBUG is not set
++CONFIG_USB_STORAGE_CYPRESS_ATACB=m
++CONFIG_USB_STORAGE_DATAFAB=m
++CONFIG_USB_STORAGE_FREECOM=m
++CONFIG_USB_STORAGE_ISD200=m
++CONFIG_USB_STORAGE_SDDR09=m
++CONFIG_USB_STORAGE_SDDR55=m
++CONFIG_USB_STORAGE_JUMPSHOT=m
++CONFIG_USB_STORAGE_USBAT=y
++CONFIG_USB_STORAGE_ONETOUCH=m
++CONFIG_USB_STORAGE_ALAUDA=m
++CONFIG_USB_STORAGE_KARMA=m
++CONFIG_USB_STORAGE_REALTEK=m
++CONFIG_REALTEK_AUTOPM=y
++CONFIG_USB_STORAGE_ENE_UB6250=m
++# CONFIG_USB_LIBUSUAL is not set
++# CONFIG_USB_UAS is not set
++
++
++#
++# USB Human Interface Devices (HID)
++#
++CONFIG_USB_HID=y
++
++CONFIG_HID_SUPPORT=y
++
++CONFIG_HID=y
++CONFIG_I2C_HID=m
++CONFIG_HID_BATTERY_STRENGTH=y
++# debugging default is y upstream now
++CONFIG_HIDRAW=y
++CONFIG_UHID=m
++CONFIG_HID_PID=y
++CONFIG_LOGITECH_FF=y
++CONFIG_HID_LOGITECH_DJ=m
++CONFIG_LOGIWII_FF=y
++CONFIG_LOGIRUMBLEPAD2_FF=y
++CONFIG_PANTHERLORD_FF=y
++CONFIG_THRUSTMASTER_FF=y
++CONFIG_HID_WACOM=m
++CONFIG_HID_WACOM_POWER_SUPPLY=y
++CONFIG_ZEROPLUS_FF=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_IDMOUSE=m
++CONFIG_DRAGONRISE_FF=y
++CONFIG_GREENASIA_FF=y
++CONFIG_SMARTJOYPLUS_FF=y
++CONFIG_LOGIG940_FF=y
++CONFIG_LOGIWHEELS_FF=y
++CONFIG_HID_MAGICMOUSE=y
++CONFIG_HID_MULTITOUCH=m
++CONFIG_HID_NTRIG=y
++CONFIG_HID_QUANTA=y
++CONFIG_HID_PRIMAX=m
++CONFIG_HID_PS3REMOTE=m
++CONFIG_HID_PRODIKEYS=m
++CONFIG_HID_DRAGONRISE=m
++CONFIG_HID_GYRATION=m
++CONFIG_HID_ICADE=m
++CONFIG_HID_TWINHAN=m
++CONFIG_HID_ORTEK=m
++CONFIG_HID_PANTHERLORD=m
++CONFIG_HID_PETALYNX=m
++CONFIG_HID_PICOLCD=m
++CONFIG_HID_RMI=m
++CONFIG_HID_ROCCAT=m
++CONFIG_HID_ROCCAT_KONE=m
++CONFIG_HID_SAMSUNG=m
++CONFIG_HID_SONY=m
++CONFIG_SONY_FF=y
++CONFIG_HID_SUNPLUS=m
++CONFIG_HID_STEELSERIES=m
++CONFIG_HID_GREENASIA=m
++CONFIG_HID_SMARTJOYPLUS=m
++CONFIG_HID_TOPSEED=m
++CONFIG_HID_THINGM=m
++CONFIG_HID_THRUSTMASTER=m
++CONFIG_HID_XINMO=m
++CONFIG_HID_ZEROPLUS=m
++CONFIG_HID_ZYDACRON=m
++CONFIG_HID_SENSOR_HUB=m
++CONFIG_HID_SENSOR_GYRO_3D=m
++CONFIG_HID_SENSOR_MAGNETOMETER_3D=m
++CONFIG_HID_SENSOR_ALS=m
++CONFIG_HID_SENSOR_ACCEL_3D=m
++CONFIG_HID_EMS_FF=m
++CONFIG_HID_ELECOM=m
++CONFIG_HID_ELO=m
++CONFIG_HID_UCLOGIC=m
++CONFIG_HID_WALTOP=m
++CONFIG_HID_ROCCAT_PYRA=m
++CONFIG_HID_ROCCAT_KONEPLUS=m
++CONFIG_HID_ACRUX=m
++CONFIG_HID_ACRUX_FF=y
++CONFIG_HID_KEYTOUCH=m
++CONFIG_HID_LCPOWER=m
++CONFIG_HID_LENOVO_TPKBD=m
++CONFIG_HID_ROCCAT_ARVO=m
++CONFIG_HID_ROCCAT_ISKU=m
++CONFIG_HID_ROCCAT_KOVAPLUS=m
++CONFIG_HID_HOLTEK=m
++CONFIG_HOLTEK_FF=y
++CONFIG_HID_HUION=m
++CONFIG_HID_SPEEDLINK=m
++CONFIG_HID_WIIMOTE=m
++CONFIG_HID_WIIMOTE_EXT=y
++CONFIG_HID_KYE=m
++CONFIG_HID_SAITEK=m
++CONFIG_HID_TIVO=m
++CONFIG_HID_GENERIC=y
++CONFIG_HID_AUREAL=m
++CONFIG_HID_APPLEIR=m
++
++
++#
++# USB Imaging devices
++#
++CONFIG_USB_MDC800=m
++CONFIG_USB_MICROTEK=m
++
++#
++# USB Multimedia devices
++#
++
++CONFIG_USB_DSBR=m
++# CONFIG_USB_ET61X251 is not set
++CONFIG_USB_M5602=m
++CONFIG_USB_STV06XX=m
++CONFIG_USB_GSPCA=m
++CONFIG_USB_GSPCA_MR97310A=m
++CONFIG_USB_GSPCA_BENQ=m
++CONFIG_USB_GSPCA_CONEX=m
++CONFIG_USB_GSPCA_CPIA1=m
++CONFIG_USB_GSPCA_ETOMS=m
++CONFIG_USB_GSPCA_FINEPIX=m
++CONFIG_USB_GSPCA_MARS=m
++CONFIG_USB_GSPCA_OV519=m
++CONFIG_USB_GSPCA_OV534=m
++CONFIG_USB_GSPCA_OV534_9=m
++CONFIG_USB_GSPCA_PAC207=m
++CONFIG_USB_GSPCA_PAC7311=m
++CONFIG_USB_GSPCA_SN9C2028=m
++CONFIG_USB_GSPCA_SN9C20X=m
++CONFIG_USB_GSPCA_SONIXB=m
++CONFIG_USB_GSPCA_SONIXJ=m
++CONFIG_USB_GSPCA_SPCA500=m
++CONFIG_USB_GSPCA_SPCA501=m
++CONFIG_USB_GSPCA_SPCA505=m
++CONFIG_USB_GSPCA_SPCA506=m
++CONFIG_USB_GSPCA_SPCA508=m
++CONFIG_USB_GSPCA_SPCA561=m
++CONFIG_USB_GSPCA_STK014=m
++CONFIG_USB_GSPCA_STK1135=m
++CONFIG_USB_GSPCA_SUNPLUS=m
++CONFIG_USB_GSPCA_T613=m
++CONFIG_USB_GSPCA_TOPRO=m
++CONFIG_USB_GSPCA_TV8532=m
++CONFIG_USB_GSPCA_VC032X=m
++CONFIG_USB_GSPCA_ZC3XX=m
++CONFIG_USB_GSPCA_SQ905=m
++CONFIG_USB_GSPCA_SQ905C=m
++CONFIG_USB_GSPCA_PAC7302=m
++CONFIG_USB_GSPCA_STV0680=m
++CONFIG_USB_GL860=m
++CONFIG_USB_GSPCA_JEILINJ=m
++CONFIG_USB_GSPCA_JL2005BCD=m
++CONFIG_USB_GSPCA_KONICA=m
++CONFIG_USB_GSPCA_XIRLINK_CIT=m
++CONFIG_USB_GSPCA_SPCA1528=m
++CONFIG_USB_GSPCA_SQ930X=m
++CONFIG_USB_GSPCA_NW80X=m
++CONFIG_USB_GSPCA_VICAM=m
++CONFIG_USB_GSPCA_KINECT=m
++CONFIG_USB_GSPCA_SE401=m
++
++CONFIG_USB_S2255=m
++# CONFIG_VIDEO_SH_MOBILE_CEU is not set
++# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
++# CONFIG_USB_SN9C102 is not set
++CONFIG_USB_ZR364XX=m
++
++#
++# USB Network adaptors
++#
++CONFIG_USB_CATC=m
++CONFIG_USB_HSO=m
++CONFIG_USB_KAWETH=m
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_USBNET=m
++CONFIG_USB_SPEEDTOUCH=m
++CONFIG_USB_NET_AX8817X=m
++CONFIG_USB_NET_AX88179_178A=m
++CONFIG_USB_NET_DM9601=m
++CONFIG_USB_NET_SR9700=m
++CONFIG_USB_NET_SMSC95XX=m
++CONFIG_USB_NET_GL620A=m
++CONFIG_USB_NET_NET1080=m
++CONFIG_USB_NET_PLUSB=m
++CONFIG_USB_NET_MCS7830=m
++CONFIG_USB_NET_RNDIS_HOST=m
++CONFIG_USB_NET_CDC_SUBSET=m
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_CDC_NCM=m
++CONFIG_USB_NET_HUAWEI_CDC_NCM=m
++CONFIG_USB_NET_CDC_MBIM=m
++CONFIG_USB_NET_ZAURUS=m
++CONFIG_USB_NET_CX82310_ETH=m
++CONFIG_USB_NET_INT51X1=m
++CONFIG_USB_CDC_PHONET=m
++CONFIG_USB_IPHETH=m
++CONFIG_USB_SIERRA_NET=m
++CONFIG_USB_VL600=m
++
++#
++# USB Host-to-Host Cables
++#
++CONFIG_USB_AN2720=y
++CONFIG_USB_BELKIN=y
++
++#
++# Intelligent USB Devices/Gadgets
++#
++CONFIG_USB_ARMLINUX=y
++CONFIG_USB_EPSON2888=y
++CONFIG_USB_KC2190=y
++
++# CONFIG_USB_MUSB_HDRC is not set
++
++#
++# USB port drivers
++#
++CONFIG_USB_USS720=m
++
++#
++# USB Serial Converter support
++#
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=m
++CONFIG_USB_SERIAL_AIRCABLE=m
++CONFIG_USB_SERIAL_ARK3116=m
++CONFIG_USB_SERIAL_BELKIN=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_CYPRESS_M8=m
++CONFIG_USB_SERIAL_CYBERJACK=m
++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_SYMBOL=m
++CONFIG_USB_SERIAL_EDGEPORT=m
++CONFIG_USB_SERIAL_EDGEPORT_TI=m
++CONFIG_USB_SERIAL_EMPEG=m
++# CONFIG_USB_SERIAL_F81232 is not set
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_FUNSOFT=m
++CONFIG_USB_SERIAL_GARMIN=m
++CONFIG_USB_SERIAL_HP4X=m
++CONFIG_USB_SERIAL_IPAQ=m
++CONFIG_USB_SERIAL_IPW=m
++CONFIG_USB_SERIAL_IR=m
++CONFIG_USB_SERIAL_IUU=m
++CONFIG_USB_SERIAL_KEYSPAN_PDA=m
++CONFIG_USB_SERIAL_KEYSPAN=m
++CONFIG_USB_SERIAL_KEYSPAN_MPR=y
++CONFIG_USB_SERIAL_KEYSPAN_USA28=y
++CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
++CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
++CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
++CONFIG_USB_SERIAL_KEYSPAN_USA19=y
++CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
++CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
++CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
++CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
++CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
++CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
++CONFIG_USB_SERIAL_KLSI=m
++CONFIG_USB_SERIAL_KOBIL_SCT=m
++CONFIG_USB_SERIAL_MCT_U232=m
++# CONFIG_USB_SERIAL_METRO is not set
++CONFIG_USB_SERIAL_MOS7720=m
++CONFIG_USB_SERIAL_MOS7715_PARPORT=y
++# CONFIG_USB_SERIAL_ZIO is not set
++# CONFIG_USB_SERIAL_WISHBONE is not set
++# CONFIG_USB_SERIAL_ZTE is not set
++CONFIG_USB_SERIAL_MOS7840=m
++CONFIG_USB_SERIAL_MOTOROLA=m
++# CONFIG_USB_SERIAL_MXUPORT is not set
++CONFIG_USB_SERIAL_NAVMAN=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_SERIAL_OTI6858=m
++CONFIG_USB_SERIAL_OPTICON=m
++CONFIG_USB_SERIAL_OMNINET=m
++CONFIG_USB_SERIAL_PL2303=m
++# CONFIG_USB_SERIAL_QUATECH2 is not set
++CONFIG_USB_SERIAL_SAFE=m
++CONFIG_USB_SERIAL_SAFE_PADDED=y
++CONFIG_USB_SERIAL_SIERRAWIRELESS=m
++CONFIG_USB_SERIAL_SIEMENS_MPI=m
++CONFIG_USB_SERIAL_SPCP8X5=m
++CONFIG_USB_SERIAL_TI=m
++CONFIG_USB_SERIAL_VISOR=m
++CONFIG_USB_SERIAL_WHITEHEAT=m
++CONFIG_USB_SERIAL_XIRCOM=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
++CONFIG_USB_SERIAL_XSENS_MT=m
++CONFIG_USB_SERIAL_DEBUG=m
++CONFIG_USB_SERIAL_SSU100=m
++CONFIG_USB_SERIAL_QT2=m
++CONFIG_USB_SERIAL_FLASHLOADER=m
++CONFIG_USB_SERIAL_SUUNTO=m
++CONFIG_USB_SERIAL_CONSOLE=y
++
++CONFIG_USB_EZUSB=y
++CONFIG_USB_EMI62=m
++CONFIG_USB_LED=m
++# CONFIG_USB_CYPRESS_CY7C63 is not set
++
++#
++# USB Miscellaneous drivers
++#
++
++CONFIG_USB_ADUTUX=m
++CONFIG_USB_SEVSEG=m
++CONFIG_USB_ALI_M5632=y
++CONFIG_USB_APPLEDISPLAY=m
++
++# Physical Layer USB driver
++# CONFIG_USB_OTG_FSM is not set
++
++# CONFIG_GENERIC_PHY is not set
++# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set
++# CONFIG_PHY_EXYNOS_DP_VIDEO is not set
++# CONFIG_OMAP_USB2 is not set
++# CONFIG_OMAP_USB3 is not set
++# CONFIG_OMAP_CONTROL_USB is not set
++# CONFIG_AM335X_PHY_USB is not set
++# CONFIG_SAMSUNG_USBPHY is not set
++# CONFIG_SAMSUNG_USB2PHY is not set
++# CONFIG_SAMSUNG_USB3PHY is not set
++# CONFIG_BCM_KONA_USB2_PHY is not set
++CONFIG_USB_RCAR_PHY=m
++CONFIG_USB_ATM=m
++CONFIG_USB_CXACRU=m
++# CONFIG_USB_C67X00_HCD is not set
++# CONFIG_USB_CYTHERM is not set
++CONFIG_USB_EMI26=m
++CONFIG_USB_FTDI_ELAN=m
++CONFIG_USB_FILE_STORAGE=m
++# CONFIG_USB_FILE_STORAGE_TEST is not set
++# CONFIG_USB_DWC3 is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_OXU210HP_HCD is not set
++CONFIG_USB_IOWARRIOR=m
++CONFIG_USB_ISIGHTFW=m
++CONFIG_USB_YUREX=m
++CONFIG_USB_EZUSB_FX2=m
++CONFIG_USB_HSIC_USB3503=m
++CONFIG_USB_LCD=m
++CONFIG_USB_LD=m
++CONFIG_USB_LEGOTOWER=m
++CONFIG_USB_MON=y
++CONFIG_USB_PWC=m
++CONFIG_USB_PWC_INPUT_EVDEV=y
++# CONFIG_USB_PWC_DEBUG is not set
++# CONFIG_USB_RIO500 is not set
++CONFIG_USB_SISUSBVGA=m
++CONFIG_USB_SISUSBVGA_CON=y
++CONFIG_RADIO_SI470X=y
++CONFIG_USB_KEENE=m
++CONFIG_USB_MA901=m
++CONFIG_USB_SI470X=m
++CONFIG_I2C_SI470X=m
++CONFIG_RADIO_SI4713=m
++# CONFIG_RADIO_TEF6862 is not set
++CONFIG_USB_MR800=m
++CONFIG_USB_STKWEBCAM=m
++# CONFIG_USB_TEST is not set
++# CONFIG_USB_EHSET_TEST_FIXTURE is not set
++CONFIG_USB_TRANCEVIBRATOR=m
++CONFIG_USB_U132_HCD=m
++CONFIG_USB_UEAGLEATM=m
++CONFIG_USB_XUSBATM=m
++
++# CONFIG_USB_DWC2 is not set
++
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++
++# CONFIG_USB_ISP1301 is not set
++
++# CONFIG_USB_OTG is not set
++
++#
++# Sonics Silicon Backplane
++#
++CONFIG_SSB=m
++CONFIG_SSB_PCIHOST=y
++CONFIG_SSB_SDIOHOST=y
++CONFIG_SSB_PCMCIAHOST=y
++# CONFIG_SSB_SILENT is not set
++# CONFIG_SSB_DEBUG is not set
++CONFIG_SSB_DRIVER_PCICORE=y
++CONFIG_SSB_DRIVER_GPIO=y
++
++# Multifunction USB devices
++# CONFIG_MFD_PCF50633 is not set
++CONFIG_PCF50633_ADC=m
++CONFIG_PCF50633_GPIO=m
++# CONFIG_AB3100_CORE is not set
++CONFIG_INPUT_PCF50633_PMU=m
++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
++
++CONFIG_MFD_SUPPORT=y
++CONFIG_MFD_VX855=m
++CONFIG_MFD_SM501=m
++CONFIG_MFD_SM501_GPIO=y
++CONFIG_MFD_RTSX_PCI=m
++# CONFIG_MFD_TI_AM335X_TSCADC is not set
++CONFIG_MFD_VIPERBOARD=m
++# CONFIG_MFD_RETU is not set
++# CONFIG_MFD_TC6393XB is not set
++# CONFIG_MFD_WM8400 is not set
++# CONFIG_MFD_WM8350_I2C is not set
++# CONFIG_MFD_WM8350 is not set
++# CONFIG_MFD_WM831X is not set
++# CONFIG_AB3100_OTP is not set
++# CONFIG_MFD_TIMBERDALE is not set
++# CONFIG_MFD_WM8994 is not set
++# CONFIG_MFD_88PM860X is not set
++# CONFIG_LPC_SCH is not set
++# CONFIG_LPC_ICH is not set
++# CONFIG_HTC_I2CPLD is not set
++# CONFIG_MFD_MAX8925 is not set
++# CONFIG_MFD_ASIC3 is not set
++# CONFIG_MFD_AS3722 is not set
++# CONFIG_HTC_EGPIO is not set
++# CONFIG_TPS6507X is not set
++# CONFIG_ABX500_CORE is not set
++# CONFIG_MFD_RDC321X is not set
++# CONFIG_MFD_JANZ_CMODIO is not set
++# CONFIG_MFD_KEMPLD is not set
++# CONFIG_MFD_WM831X_I2C is not set
++# CONFIG_MFD_CS5535 is not set
++# CONFIG_MFD_STMPE is not set
++# CONFIG_MFD_MAX8998 is not set
++# CONFIG_MFD_TPS6586X is not set
++# CONFIG_MFD_TC3589X is not set
++# CONFIG_MFD_WL1273_CORE is not set
++# CONFIG_MFD_TPS65217 is not set
++# CONFIG_MFD_LM3533 is not set
++# CONFIG_MFD_ARIZONA is not set
++# CONFIG_MFD_ARIZONA_I2C is not set
++# CONFIG_MFD_CROS_EC is not set
++# CONFIG_MFD_TPS65912 is not set
++# CONFIG_MFD_SYSCON is not set
++# CONFIG_MFD_DA9063 is not set
++# CONFIG_MFD_LP3943 is not set
++
++#
++# File systems
++#
++CONFIG_MISC_FILESYSTEMS=y
++
++# ext4 is used for ext2 and ext3 filesystems
++CONFIG_JBD2=y
++CONFIG_FS_MBCACHE=y
++CONFIG_REISERFS_FS=m
++# CONFIG_REISERFS_CHECK is not set
++CONFIG_REISERFS_PROC_INFO=y
++CONFIG_REISERFS_FS_XATTR=y
++CONFIG_REISERFS_FS_POSIX_ACL=y
++CONFIG_REISERFS_FS_SECURITY=y
++CONFIG_JFS_FS=m
++# CONFIG_JFS_DEBUG is not set
++# CONFIG_JFS_STATISTICS is not set
++CONFIG_JFS_POSIX_ACL=y
++CONFIG_JFS_SECURITY=y
++CONFIG_XFS_FS=m
++# CONFIG_XFS_DEBUG is not set
++# CONFIG_XFS_RT is not set
++CONFIG_XFS_QUOTA=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_MINIX_FS=m
++CONFIG_ROMFS_FS=m
++# CONFIG_QFMT_V1 is not set
++CONFIG_QFMT_V2=y
++CONFIG_QUOTACTL=y
++CONFIG_DNOTIFY=y
++# Autofsv3 is obsolete.
++# systemd is dependant upon AUTOFS, so build it in.
++# CONFIG_EXOFS_FS is not set
++# CONFIG_EXOFS_DEBUG is not set
++CONFIG_NILFS2_FS=m
++# CONFIG_LOGFS is not set
++CONFIG_CEPH_FS=m
++CONFIG_CEPH_FSCACHE=y
++CONFIG_BLK_DEV_RBD=m
++CONFIG_CEPH_LIB=m
++CONFIG_CEPH_FS_POSIX_ACL=y
++# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
++
++CONFIG_FSCACHE=m
++CONFIG_FSCACHE_STATS=y
++# CONFIG_FSCACHE_HISTOGRAM is not set
++# CONFIG_FSCACHE_DEBUG is not set
++CONFIG_FSCACHE_OBJECT_LIST=y
++
++CONFIG_CACHEFILES=m
++# CONFIG_CACHEFILES_DEBUG is not set
++# CONFIG_CACHEFILES_HISTOGRAM is not set
++
++#
++# CD-ROM/DVD Filesystems
++#
++
++#
++# DOS/FAT/NT Filesystems
++#
++CONFIG_FAT_FS=m
++CONFIG_FAT_DEFAULT_CODEPAGE=437
++CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
++# CONFIG_NTFS_FS is not set
++
++#
++# Pseudo filesystems
++#
++CONFIG_PROC_FS=y
++CONFIG_PROC_KCORE=y
++CONFIG_PROC_VMCORE=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_XATTR=y
++CONFIG_HUGETLBFS=y
++CONFIG_HUGETLB_PAGE=y
++# CONFIG_DEBUG_FS is not set
++
++#
++# Miscellaneous filesystems
++#
++# CONFIG_ADFS_FS is not set
++CONFIG_AFFS_FS=m
++CONFIG_ECRYPT_FS=m
++# CONFIG_ECRYPT_FS_MESSAGING is not set
++CONFIG_HFS_FS=m
++CONFIG_HFSPLUS_FS=m
++# CONFIG_HFSPLUS_FS_POSIX_ACL is not set
++CONFIG_BEFS_FS=m
++# CONFIG_BEFS_DEBUG is not set
++# CONFIG_BFS_FS is not set
++# CONFIG_EFS_FS is not set
++
++CONFIG_CRAMFS=m
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZLIB=y
++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
++# CONFIG_SQUASHFS_EMBEDDED is not set
++# CONFIG_VXFS_FS is not set
++# CONFIG_HPFS_FS is not set
++# CONFIG_QNX4FS_FS is not set
++# CONFIG_QNX6FS_FS is not set
++CONFIG_SYSV_FS=m
++CONFIG_UFS_FS=m
++# CONFIG_UFS_FS_WRITE is not set
++# CONFIG_UFS_DEBUG is not set
++CONFIG_9P_FS=m
++CONFIG_9P_FSCACHE=y
++CONFIG_9P_FS_POSIX_ACL=y
++CONFIG_9P_FS_SECURITY=y
++# CONFIG_OMFS_FS is not set
++CONFIG_CUSE=m
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_XATTR=y
++CONFIG_F2FS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS_SECURITY=y
++# CONFIG_F2FS_CHECK_FS is not set
++
++
++#
++# Network File Systems
++#
++CONFIG_NETWORK_FILESYSTEMS=y
++CONFIG_NFS_V2=y
++CONFIG_NFS_V3=y
++CONFIG_NFS_SWAP=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org"
++# CONFIG_NFS_V4_1_MIGRATION is not set
++CONFIG_NFS_V4_2=y
++CONFIG_NFSD=m
++CONFIG_NFSD_V3=y
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++CONFIG_NFSD_V4_SECURITY_LABEL=y
++CONFIG_NFS_FSCACHE=y
++# CONFIG_NFS_USE_LEGACY_DNS is not set
++CONFIG_PNFS_OBJLAYOUT=m
++CONFIG_PNFS_BLOCK=m
++CONFIG_LOCKD=m
++CONFIG_LOCKD_V4=y
++CONFIG_EXPORTFS=y
++CONFIG_SUNRPC=m
++CONFIG_SUNRPC_GSS=m
++CONFIG_SUNRPC_XPRT_RDMA=m
++CONFIG_SUNRPC_DEBUG=y
++CONFIG_RPCSEC_GSS_KRB5=m
++CONFIG_CIFS=m
++CONFIG_CIFS_STATS=y
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_SMB2=y
++CONFIG_CIFS_UPCALL=y
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++CONFIG_CIFS_FSCACHE=y
++CONFIG_CIFS_ACL=y
++CONFIG_CIFS_WEAK_PW_HASH=y
++CONFIG_CIFS_DEBUG=y
++# CONFIG_CIFS_DEBUG2 is not set
++CONFIG_CIFS_DFS_UPCALL=y
++CONFIG_CIFS_NFSD_EXPORT=y
++CONFIG_NCP_FS=m
++CONFIG_NCPFS_PACKET_SIGNING=y
++CONFIG_NCPFS_IOCTL_LOCKING=y
++CONFIG_NCPFS_STRONG=y
++CONFIG_NCPFS_NFS_NS=y
++CONFIG_NCPFS_OS2_NS=y
++CONFIG_NCPFS_SMALLDOS=y
++CONFIG_NCPFS_NLS=y
++CONFIG_NCPFS_EXTRAS=y
++CONFIG_CODA_FS=m
++# CONFIG_AFS_FS is not set
++# CONFIG_AF_RXRPC is not set
++
++CONFIG_OCFS2_FS=m
++# CONFIG_OCFS2_DEBUG_FS is not set
++# CONFIG_OCFS2_DEBUG_MASKLOG is not set
++CONFIG_OCFS2_FS_O2CB=m
++CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m
++# CONFIG_OCFS2_FS_STATS is not set
++
++CONFIG_BTRFS_FS=m
++CONFIG_BTRFS_FS_POSIX_ACL=y
++# Maybe see if we want this on for debug kernels?
++# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
++# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set
++# CONFIG_BTRFS_DEBUG is not set
++# CONFIG_BTRFS_ASSERT is not set
++
++CONFIG_CONFIGFS_FS=y
++
++CONFIG_DLM=m
++CONFIG_DLM_DEBUG=y
++CONFIG_GFS2_FS=m
++CONFIG_GFS2_FS_LOCKING_DLM=y
++
++
++CONFIG_UBIFS_FS_XATTR=y
++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
++# CONFIG_UBIFS_FS_DEBUG is not set
++
++#
++# Partition Types
++#
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_ACORN_PARTITION is not set
++CONFIG_AIX_PARTITION=y
++CONFIG_AMIGA_PARTITION=y
++# CONFIG_ATARI_PARTITION is not set
++CONFIG_BSD_DISKLABEL=y
++CONFIG_EFI_PARTITION=y
++CONFIG_KARMA_PARTITION=y
++CONFIG_LDM_PARTITION=y
++# CONFIG_LDM_DEBUG is not set
++CONFIG_MAC_PARTITION=y
++CONFIG_MSDOS_PARTITION=y
++CONFIG_MINIX_SUBPARTITION=y
++CONFIG_OSF_PARTITION=y
++CONFIG_SGI_PARTITION=y
++CONFIG_SOLARIS_X86_PARTITION=y
++CONFIG_SUN_PARTITION=y
++# CONFIG_SYSV68_PARTITION is not set
++CONFIG_UNIXWARE_DISKLABEL=y
++# CONFIG_ULTRIX_PARTITION is not set
++# CONFIG_CMDLINE_PARTITION is not set
++
++CONFIG_NLS=y
++
++#
++# Native Language Support
++#
++CONFIG_NLS_CODEPAGE_737=m
++CONFIG_NLS_CODEPAGE_775=m
++CONFIG_NLS_CODEPAGE_850=m
++CONFIG_NLS_CODEPAGE_852=m
++CONFIG_NLS_CODEPAGE_855=m
++CONFIG_NLS_CODEPAGE_857=m
++CONFIG_NLS_CODEPAGE_860=m
++CONFIG_NLS_CODEPAGE_861=m
++CONFIG_NLS_CODEPAGE_862=m
++CONFIG_NLS_CODEPAGE_863=m
++CONFIG_NLS_CODEPAGE_864=m
++CONFIG_NLS_CODEPAGE_865=m
++CONFIG_NLS_CODEPAGE_866=m
++CONFIG_NLS_CODEPAGE_869=m
++CONFIG_NLS_CODEPAGE_936=m
++CONFIG_NLS_CODEPAGE_950=m
++CONFIG_NLS_CODEPAGE_932=m
++CONFIG_NLS_CODEPAGE_949=m
++CONFIG_NLS_CODEPAGE_874=m
++CONFIG_NLS_ISO8859_8=m
++CONFIG_NLS_CODEPAGE_1250=m
++CONFIG_NLS_CODEPAGE_1251=m
++CONFIG_NLS_ISO8859_2=m
++CONFIG_NLS_ISO8859_3=m
++CONFIG_NLS_ISO8859_4=m
++CONFIG_NLS_ISO8859_5=m
++CONFIG_NLS_ISO8859_6=m
++CONFIG_NLS_ISO8859_7=m
++CONFIG_NLS_ISO8859_9=m
++CONFIG_NLS_ISO8859_13=m
++CONFIG_NLS_ISO8859_14=m
++CONFIG_NLS_KOI8_R=m
++CONFIG_NLS_KOI8_U=m
++CONFIG_NLS_MAC_ROMAN=m
++CONFIG_NLS_MAC_CELTIC=m
++CONFIG_NLS_MAC_CENTEURO=m
++CONFIG_NLS_MAC_CROATIAN=m
++CONFIG_NLS_MAC_CYRILLIC=m
++CONFIG_NLS_MAC_GAELIC=m
++CONFIG_NLS_MAC_GREEK=m
++CONFIG_NLS_MAC_ICELAND=m
++CONFIG_NLS_MAC_INUIT=m
++CONFIG_NLS_MAC_ROMANIAN=m
++CONFIG_NLS_MAC_TURKISH=m
++
++#
++# Profiling support
++#
++CONFIG_PROFILING=y
++CONFIG_OPROFILE=m
++CONFIG_OPROFILE_EVENT_MULTIPLEX=y
++
++#
++# Kernel hacking
++#
++CONFIG_DEBUG_KERNEL=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0
++# CONFIG_DEBUG_INFO is not set
++CONFIG_FRAME_POINTER=y
++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
++# CONFIG_DEBUG_DRIVER is not set
++CONFIG_HEADERS_CHECK=y
++# CONFIG_LKDTM is not set
++# CONFIG_NOTIFIER_ERROR_INJECTION is not set
++# CONFIG_READABLE_ASM is not set
++
++# CONFIG_RT_MUTEX_TESTER is not set
++# CONFIG_DEBUG_LOCKDEP is not set
++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
++
++# DEBUG options that don't get enabled/disabled with 'make debug/release'
++
++# This generates a huge amount of dmesg spew
++# CONFIG_DEBUG_KOBJECT is not set
++#
++# This breaks booting until the module patches are in-tree
++# CONFIG_DEBUG_KOBJECT_RELEASE is not set
++#
++#
++# These debug options are deliberatly left on (even in 'make release' kernels).
++# They aren't that much of a performance impact, and the value
++# from getting useful bug-reports makes it worth leaving them on.
++# CONFIG_DEBUG_HIGHMEM is not set
++# CONFIG_DEBUG_SHIRQ is not set
++CONFIG_BOOT_PRINTK_DELAY=y
++CONFIG_DEBUG_DEVRES=y
++CONFIG_DEBUG_RODATA_TEST=y
++CONFIG_DEBUG_NX_TEST=m
++CONFIG_DEBUG_SET_MODULE_RONX=y
++CONFIG_DEBUG_BOOT_PARAMS=y
++# CONFIG_DEBUG_VM is not set
++# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set
++CONFIG_LOCKUP_DETECTOR=y
++# CONFIG_DEBUG_INFO_REDUCED is not set
++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
++# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
++# CONFIG_PANIC_ON_OOPS is not set
++CONFIG_PANIC_TIMEOUT=0
++CONFIG_ATOMIC64_SELFTEST=y
++CONFIG_MEMORY_FAILURE=y
++CONFIG_HWPOISON_INJECT=m
++CONFIG_CROSS_MEMORY_ATTACH=y
++# CONFIG_DEBUG_SECTION_MISMATCH is not set
++# CONFIG_BACKTRACE_SELF_TEST is not set
++# CONFIG_DEBUG_VIRTUAL is not set
++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
++CONFIG_EARLY_PRINTK_DBGP=y
++# CONFIG_PAGE_POISONING is not set
++# CONFIG_CRASH_DUMP is not set
++# CONFIG_CRASH is not set
++# CONFIG_GCOV_KERNEL is not set
++# CONFIG_RAMOOPS is not set
++
++
++#
++# Security options
++#
++CONFIG_SECURITY=y
++# CONFIG_SECURITY_DMESG_RESTRICT is not set
++CONFIG_SECURITY_NETWORK=y
++CONFIG_SECURITY_NETWORK_XFRM=y
++# CONFIG_SECURITY_PATH is not set
++CONFIG_SECURITY_SELINUX=y
++CONFIG_SECURITY_SELINUX_BOOTPARAM=y
++CONFIG_SECURITY_SELINUX_DISABLE=y
++CONFIG_SECURITY_SELINUX_DEVELOP=y
++CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
++CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
++CONFIG_SECURITY_SELINUX_AVC_STATS=y
++# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
++# CONFIG_SECURITY_SMACK is not set
++# CONFIG_SECURITY_TOMOYO is not set
++# CONFIG_SECURITY_APPARMOR is not set
++# CONFIG_SECURITY_YAMA is not set
++CONFIG_AUDIT=y
++CONFIG_AUDITSYSCALL=y
++# http://lists.fedoraproject.org/pipermail/kernel/2013-February/004125.html
++CONFIG_AUDIT_LOGINUID_IMMUTABLE=y
++
++CONFIG_SECCOMP=y
++
++# CONFIG_SSBI is not set
++
++#
++# Cryptographic options
++#
++CONFIG_CRYPTO=y
++CONFIG_CRYPTO_FIPS=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_CRYPTODEV=y
++CONFIG_CRYPTO_MANAGER=y
++CONFIG_CRYPTO_MANAGER2=y
++CONFIG_CRYPTO_USER=y
++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
++CONFIG_CRYPTO_HW=y
++CONFIG_CRYPTO_BLKCIPHER=y
++# CONFIG_CRYPTO_CRYPTD is not set
++CONFIG_CRYPTO_AES=y
++CONFIG_CRYPTO_ARC4=m
++CONFIG_CRYPTO_ANUBIS=m
++CONFIG_CRYPTO_AUTHENC=m
++CONFIG_CRYPTO_CAST5=m
++CONFIG_CRYPTO_CAST6=m
++CONFIG_CRYPTO_CRC32C=y
++CONFIG_CRYPTO_CRC32=m
++CONFIG_CRYPTO_CTR=y
++CONFIG_CRYPTO_DEFLATE=m
++CONFIG_CRYPTO_FCRYPT=m
++CONFIG_CRYPTO_GF128MUL=m
++CONFIG_CRYPTO_CMAC=m
++CONFIG_CRYPTO_HMAC=y
++CONFIG_CRYPTO_KHAZAD=m
++CONFIG_CRYPTO_LZO=m
++CONFIG_CRYPTO_LZ4=m
++CONFIG_CRYPTO_LZ4HC=m
++CONFIG_CRYPTO_NULL=m
++CONFIG_CRYPTO_PCBC=m
++CONFIG_CRYPTO_SALSA20=m
++CONFIG_CRYPTO_SALSA20_586=m
++CONFIG_CRYPTO_SEED=m
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_SERPENT=m
++CONFIG_CRYPTO_TEA=m
++CONFIG_CRYPTO_XCBC=m
++CONFIG_CRYPTO_VMAC=m
++CONFIG_CRYPTO_CRC32C_INTEL=m
++CONFIG_CRYPTO_GHASH=m
++CONFIG_CRYPTO_DEV_HIFN_795X=m
++CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
++CONFIG_CRYPTO_PCRYPT=m
++
++
++
++# Random number generation
++
++#
++# Library routines
++#
++CONFIG_CRC16=y
++CONFIG_CRC32=m
++# CONFIG_CRC32_SELFTEST is not set
++CONFIG_CRC_ITU_T=m
++CONFIG_CRC8=m
++# CONFIG_RANDOM32_SELFTEST is not set
++CONFIG_CORDIC=m
++# CONFIG_DDR is not set
++
++CONFIG_CRYPTO_ZLIB=m
++CONFIG_ZLIB_INFLATE=y
++CONFIG_ZLIB_DEFLATE=m
++
++CONFIG_INITRAMFS_SOURCE=""
++CONFIG_RD_GZIP=y
++CONFIG_RD_XZ=y
++CONFIG_KEYS=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_TRUSTED_KEYS=m
++CONFIG_ENCRYPTED_KEYS=m
++CONFIG_KEYS_DEBUG_PROC_KEYS=y
++CONFIG_CDROM_PKTCDVD=m
++CONFIG_CDROM_PKTCDVD_BUFFERS=8
++# CONFIG_CDROM_PKTCDVD_WCACHE is not set
++
++CONFIG_ATA_OVER_ETH=m
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=m
++# CONFIG_BACKLIGHT_GENERIC is not set
++CONFIG_BACKLIGHT_PROGEAR=m
++
++CONFIG_LCD_CLASS_DEVICE=m
++CONFIG_LCD_PLATFORM=m
++
++CONFIG_FAIR_GROUP_SCHED=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_SCHED_OMIT_FRAME_POINTER=y
++
++# CONFIG_SYSFS_DEPRECATED is not set
++# CONFIG_SYSFS_DEPRECATED_V2 is not set
++
++CONFIG_PRINTK_TIME=y
++
++CONFIG_ENABLE_MUST_CHECK=y
++# CONFIG_ENABLE_WARN_DEPRECATED is not set
++
++CONFIG_KEXEC=y
++
++CONFIG_HWMON=y
++# CONFIG_HWMON_DEBUG_CHIP is not set
++CONFIG_THERMAL_HWMON=y
++# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
++# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++# CONFIG_THERMAL_GOV_USER_SPACE is not set
++CONFIG_THERMAL_GOV_STEP_WISE=y
++# CONFIG_THERMAL_EMULATION is not set
++
++CONFIG_INOTIFY=y
++CONFIG_INOTIFY_USER=y
++
++#
++# Bus devices
++#
++# CONFIG_OMAP_OCP2SCP is not set
++CONFIG_PROC_EVENTS=y
++
++CONFIG_IBMASR=m
++
++CONFIG_PM_RUNTIME=y
++CONFIG_PM=y
++CONFIG_PM_STD_PARTITION=""
++# CONFIG_DPM_WATCHDOG is not set # revisit this in debug
++CONFIG_PM_TRACE=y
++CONFIG_PM_TRACE_RTC=y
++# CONFIG_PM_OPP is not set
++# CONFIG_PM_AUTOSLEEP is not set
++# CONFIG_PM_WAKELOCKS is not set
++# CONFIG_HIBERNATION is not set
++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
++CONFIG_SUSPEND=y
++
++CONFIG_CPU_FREQ_TABLE=y
++CONFIG_CPU_FREQ_STAT=m
++CONFIG_CPU_FREQ_STAT_DETAILS=y
++
++
++CONFIG_NET_VENDOR_SMC=y
++# CONFIG_IBMTR is not set
++# CONFIG_SKISA is not set
++# CONFIG_PROTEON is not set
++# CONFIG_SMCTR is not set
++
++# CONFIG_MOUSE_ATIXL is not set
++
++# CONFIG_MEDIA_PARPORT_SUPPORT is not set
++
++CONFIG_RADIO_TEA5764=m
++CONFIG_RADIO_SAA7706H=m
++CONFIG_RADIO_CADET=m
++CONFIG_RADIO_RTRACK=m
++CONFIG_RADIO_RTRACK2=m
++CONFIG_RADIO_AZTECH=m
++CONFIG_RADIO_GEMTEK=m
++CONFIG_RADIO_SF16FMI=m
++CONFIG_RADIO_SF16FMR2=m
++CONFIG_RADIO_TERRATEC=m
++CONFIG_RADIO_TRUST=m
++CONFIG_RADIO_TYPHOON=m
++CONFIG_RADIO_ZOLTRIX=m
++
++CONFIG_SND_DARLA20=m
++CONFIG_SND_GINA20=m
++CONFIG_SND_LAYLA20=m
++CONFIG_SND_DARLA24=m
++CONFIG_SND_GINA24=m
++CONFIG_SND_LAYLA24=m
++CONFIG_SND_MONA=m
++CONFIG_SND_MIA=m
++CONFIG_SND_ECHO3G=m
++CONFIG_SND_INDIGO=m
++CONFIG_SND_INDIGOIO=m
++CONFIG_SND_INDIGODJ=m
++CONFIG_SND_INDIGOIOX=m
++CONFIG_SND_INDIGODJX=m
++
++CONFIG_BALLOON_COMPACTION=y
++CONFIG_COMPACTION=y
++CONFIG_MIGRATION=y
++CONFIG_BOUNCE=y
++# CONFIG_LEDS_AMS_DELTA is not set
++# CONFIG_LEDS_LOCOMO is not set
++# CONFIG_LEDS_NET48XX is not set
++# CONFIG_LEDS_NET5501 is not set
++# CONFIG_LEDS_PCA9532 is not set
++# CONFIG_LEDS_PCA955X is not set
++# CONFIG_LEDS_BD2802 is not set
++# CONFIG_LEDS_S3C24XX is not set
++# CONFIG_LEDS_PCA9633 is not set
++CONFIG_LEDS_DELL_NETBOOKS=m
++# CONFIG_LEDS_TCA6507 is not set
++# CONFIG_LEDS_LM355x is not set
++# CONFIG_LEDS_OT200 is not set
++# CONFIG_LEDS_PWM is not set
++# CONFIG_LEDS_LP8501 is not set
++# CONFIG_LEDS_PCA963X is not set
++# CONFIG_LEDS_PCA9685 is not set
++CONFIG_LEDS_TRIGGER_TIMER=m
++CONFIG_LEDS_TRIGGER_ONESHOT=m
++CONFIG_LEDS_TRIGGER_IDE_DISK=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=m
++CONFIG_LEDS_TRIGGER_BACKLIGHT=m
++# CONFIG_LEDS_TRIGGER_CPU is not set
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_ALIX2=m
++CONFIG_LEDS_CLEVO_MAIL=m
++CONFIG_LEDS_INTEL_SS4200=m
++CONFIG_LEDS_LM3530=m
++# CONFIG_LEDS_LM3642 is not set
++CONFIG_LEDS_LM3556=m
++CONFIG_LEDS_BLINKM=m
++CONFIG_LEDS_LP3944=m
++CONFIG_LEDS_LP5521=m
++CONFIG_LEDS_LP5523=m
++CONFIG_LEDS_LP5562=m
++CONFIG_LEDS_LT3593=m
++CONFIG_LEDS_REGULATOR=m
++CONFIG_LEDS_WM8350=m
++CONFIG_LEDS_WM831X_STATUS=m
++
++CONFIG_DMA_ENGINE=y
++CONFIG_DW_DMAC_CORE=m
++CONFIG_DW_DMAC=m
++CONFIG_DW_DMAC_PCI=m
++# CONFIG_DW_DMAC_BIG_ENDIAN_IO is not set
++# CONFIG_TIMB_DMA is not set
++# CONFIG_DMATEST is not set
++CONFIG_ASYNC_TX_DMA=y
++
++CONFIG_UNUSED_SYMBOLS=y
++
++CONFIG_UPROBE_EVENT=y
++
++CONFIG_DYNAMIC_FTRACE=y
++# CONFIG_IRQSOFF_TRACER is not set
++CONFIG_SCHED_TRACER=y
++CONFIG_CONTEXT_SWITCH_TRACER=y
++CONFIG_TRACER_SNAPSHOT=y
++# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_FTRACE_MCOUNT_RECORD=y
++# CONFIG_FTRACE_STARTUP_TEST is not set
++# CONFIG_TRACE_BRANCH_PROFILING is not set
++CONFIG_FUNCTION_PROFILER=y
++CONFIG_RING_BUFFER_BENCHMARK=m
++# CONFIG_RING_BUFFER_STARTUP_TEST is not set
++# CONFIG_RBTREE_TEST is not set
++# CONFIG_INTERVAL_TREE_TEST is not set
++CONFIG_FUNCTION_TRACER=y
++CONFIG_STACK_TRACER=y
++# CONFIG_FUNCTION_GRAPH_TRACER is not set
++
++CONFIG_KPROBES=y
++CONFIG_KPROBE_EVENT=y
++# CONFIG_KPROBES_SANITY_TEST is not set
++# CONFIG_JUMP_LABEL is not set
++CONFIG_OPTPROBES=y
++
++CONFIG_HZ_1000=y
++
++CONFIG_TIMER_STATS=y
++CONFIG_PERF_COUNTERS=y
++
++# Auxillary displays
++CONFIG_KS0108=m
++CONFIG_KS0108_PORT=0x378
++CONFIG_KS0108_DELAY=2
++CONFIG_CFAG12864B=y
++CONFIG_CFAG12864B_RATE=20
++
++# CONFIG_PHANTOM is not set
++
++# CONFIG_POWER_SUPPLY_DEBUG is not set
++
++# CONFIG_TEST_POWER is not set
++CONFIG_APM_POWER=m
++# CONFIG_GENERIC_ADC_BATTERY is not set
++# CONFIG_WM831X_POWER is not set
++
++# CONFIG_BATTERY_DS2760 is not set
++# CONFIG_BATTERY_DS2781 is not set
++# CONFIG_BATTERY_DS2782 is not set
++# CONFIG_BATTERY_SBS is not set
++# CONFIG_BATTERY_BQ20Z75 is not set
++# CONFIG_BATTERY_DS2780 is not set
++# CONFIG_BATTERY_BQ27x00 is not set
++# CONFIG_BATTERY_MAX17040 is not set
++# CONFIG_BATTERY_MAX17042 is not set
++# CONFIG_BATTERY_GOLDFISH is not set
++
++# CONFIG_CHARGER_ISP1704 is not set
++# CONFIG_CHARGER_MAX8903 is not set
++# CONFIG_CHARGER_LP8727 is not set
++# CONFIG_CHARGER_GPIO is not set
++# CONFIG_CHARGER_PCF50633 is not set
++# CONFIG_CHARGER_BQ2415X is not set
++# CONFIG_CHARGER_BQ24190 is not set
++# CONFIG_CHARGER_BQ24735 is not set
++CONFIG_POWER_RESET=y
++
++# CONFIG_PDA_POWER is not set
++
++CONFIG_AUXDISPLAY=y
++
++CONFIG_UIO=m
++CONFIG_UIO_CIF=m
++# CONFIG_UIO_PDRV is not set
++# CONFIG_UIO_PDRV_GENIRQ is not set
++# CONFIG_UIO_DMEM_GENIRQ is not set
++CONFIG_UIO_AEC=m
++CONFIG_UIO_SERCOS3=m
++CONFIG_UIO_PCI_GENERIC=m
++# CONFIG_UIO_NETX is not set
++# CONFIG_UIO_MF624 is not set
++
++CONFIG_VFIO=m
++CONFIG_VFIO_IOMMU_TYPE1=m
++CONFIG_VFIO_PCI=m
++
++
++# LIRC
++CONFIG_LIRC_STAGING=y
++CONFIG_LIRC_BT829=m
++CONFIG_LIRC_IGORPLUGUSB=m
++CONFIG_LIRC_IMON=m
++CONFIG_LIRC_ZILOG=m
++CONFIG_LIRC_PARALLEL=m
++CONFIG_LIRC_SERIAL=m
++CONFIG_LIRC_SERIAL_TRANSMITTER=y
++CONFIG_LIRC_SASEM=m
++CONFIG_LIRC_SIR=m
++CONFIG_LIRC_TTUSBIR=m
++
++# CONFIG_SAMPLES is not set
++
++
++CONFIG_NOZOMI=m
++# CONFIG_TPS65010 is not set
++
++CONFIG_INPUT_APANEL=m
++CONFIG_INPUT_GP2A=m
++# CONFIG_INPUT_GPIO_TILT_POLLED is not set
++# CONFIG_INPUT_GPIO_BEEPER is not set
++
++# CONFIG_INTEL_MENLOW is not set
++CONFIG_ENCLOSURE_SERVICES=m
++CONFIG_IPWIRELESS=m
++
++# CONFIG_BLK_DEV_XIP is not set
++CONFIG_MEMSTICK=m
++# CONFIG_MEMSTICK_DEBUG is not set
++# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
++CONFIG_MSPRO_BLOCK=m
++# CONFIG_MS_BLOCK is not set
++CONFIG_MEMSTICK_TIFM_MS=m
++CONFIG_MEMSTICK_JMICRON_38X=m
++CONFIG_MEMSTICK_R592=m
++CONFIG_MEMSTICK_REALTEK_PCI=m
++
++CONFIG_ACCESSIBILITY=y
++CONFIG_A11Y_BRAILLE_CONSOLE=y
++
++# CONFIG_HTC_PASIC3 is not set
++
++# MT9V022_PCA9536_SWITCH is not set
++
++CONFIG_OPTIMIZE_INLINING=y
++
++# FIXME: This should be x86/ia64 only
++# CONFIG_HP_ILO is not set
++
++CONFIG_GPIOLIB=y
++# CONFIG_PINCTRL is not set
++# CONFIG_DEBUG_PINCTRL is not set
++# CONFIG_PINMUX is not set
++# CONFIG_PINCONF is not set
++
++CONFIG_NET_DSA=m
++CONFIG_NET_DSA_MV88E6060=m
++CONFIG_NET_DSA_MV88E6131=m
++CONFIG_NET_DSA_MV88E6123_61_65=m
++
++# Used by Maemo, we don't care.
++# CONFIG_PHONET is not set
++
++# CONFIG_ICS932S401 is not set
++# CONFIG_ATMEL_SSC is not set
++
++# CONFIG_C2PORT is not set
++
++# CONFIG_REGULATOR_DEBUG is not set
++
++CONFIG_WM8350_POWER=m
++
++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
++
++CONFIG_USB_WUSB=m
++CONFIG_USB_WUSB_CBAF=m
++# CONFIG_USB_WUSB_CBAF_DEBUG is not set
++CONFIG_USB_WHCI_HCD=m
++CONFIG_USB_HWA_HCD=m
++# CONFIG_USB_HCD_BCMA is not set
++# CONFIG_USB_HCD_SSB is not set
++
++CONFIG_UWB=m
++CONFIG_UWB_HWA=m
++CONFIG_UWB_WHCI=m
++CONFIG_UWB_I1480U=m
++
++# CONFIG_ANDROID is not set
++CONFIG_STAGING_MEDIA=y
++# CONFIG_DVB_AS102 is not set
++# CONFIG_ET131X is not set
++# CONFIG_SLICOSS is not set
++# CONFIG_WLAGS49_H2 is not set
++# CONFIG_WLAGS49_H25 is not set
++# CONFIG_VIDEO_DT3155 is not set
++# CONFIG_TI_ST is not set
++# CONFIG_FB_XGI is not set
++# CONFIG_VIDEO_GO7007 is not set
++# CONFIG_I2C_BCM2048 is not set
++# CONFIG_VIDEO_TCM825X is not set
++# CONFIG_VIDEO_OMAP4 is not set
++# CONFIG_USB_MSI3101 is not set
++# CONFIG_DT3155 is not set
++# CONFIG_W35UND is not set
++# CONFIG_PRISM2_USB is not set
++# CONFIG_ECHO is not set
++CONFIG_USB_ATMEL=m
++# CONFIG_COMEDI is not set
++# CONFIG_ASUS_OLED is not set
++# CONFIG_PANEL is not set
++# CONFIG_TRANZPORT is not set
++# CONFIG_POHMELFS is not set
++# CONFIG_IDE_PHISON is not set
++# CONFIG_LINE6_USB is not set
++# CONFIG_VME_BUS is not set
++# CONFIG_RAR_REGISTER is not set
++# CONFIG_VT6656 is not set
++# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
++# Larry Finger maintains these (rhbz 913753)
++CONFIG_RTLLIB=m
++CONFIG_RTLLIB_CRYPTO_CCMP=m
++CONFIG_RTLLIB_CRYPTO_TKIP=m
++CONFIG_RTLLIB_CRYPTO_WEP=m
++CONFIG_RTL8192E=m
++# CONFIG_INPUT_GPIO is not set
++# CONFIG_VIDEO_CX25821 is not set
++# CONFIG_R8187SE is not set
++# CONFIG_R8188EU is not set
++# CONFIG_R8821AE is not set
++# CONFIG_RTL8192U is not set
++# CONFIG_FB_SM7XX is not set
++# CONFIG_SPECTRA is not set
++# CONFIG_EASYCAP is not set
++# CONFIG_SOLO6X10 is not set
++# CONFIG_ACPI_QUICKSTART is not set
++# CONFIG_LTE_GDM724X is not set
++CONFIG_R8712U=m # Larry Finger maintains this (rhbz 699618)
++# CONFIG_R8712_AP is not set
++# CONFIG_ATH6K_LEGACY is not set
++# CONFIG_USB_ENESTORAGE is not set
++# CONFIG_BCM_WIMAX is not set
++# CONFIG_USB_BTMTK is not set
++# CONFIG_FT1000 is not set
++# CONFIG_SPEAKUP is not set
++# CONFIG_DX_SEP is not set
++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
++# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
++# CONFIG_RTS_PSTOR is not set
++CONFIG_ALTERA_STAPL=m
++# CONFIG_DVB_CXD2099 is not set
++# CONFIG_USBIP_CORE is not set
++# CONFIG_INTEL_MEI is not set
++# CONFIG_ZCACHE is not set
++# CONFIG_RTS5139 is not set
++# CONFIG_NVEC_LEDS is not set
++# CONFIG_VT6655 is not set
++# CONFIG_RAMSTER is not set
++# CONFIG_USB_WPAN_HCD is not set
++# CONFIG_WIMAX_GDM72XX is not set
++# CONFIG_IPACK_BUS is not set
++# CONFIG_CSR_WIFI is not set
++# CONFIG_ZCACHE2 is not set
++# CONFIG_NET_VENDOR_SILICOM is not set
++# CONFIG_SBYPASS is not set
++# CONFIG_BPCTL is not set
++# CONFIG_CED1401 is not set
++# CONFIG_DGRP is not set
++# CONFIG_SB105X is not set
++# CONFIG_LUSTRE_FS is not set
++# CONFIG_XILLYBUS is not set
++# CONFIG_DGAP is not set
++# CONFIG_DGNC is not set
++# CONFIG_RTS5208 is not set
++# END OF STAGING
++
++#
++# Remoteproc drivers (EXPERIMENTAL)
++#
++# CONFIG_STE_MODEM_RPROC is not set
++
++CONFIG_LIBFC=m
++CONFIG_LIBFCOE=m
++CONFIG_FCOE=m
++CONFIG_FCOE_FNIC=m
++
++
++# CONFIG_IMA is not set
++CONFIG_IMA_MEASURE_PCR_IDX=10
++CONFIG_IMA_AUDIT=y
++CONFIG_IMA_LSM_RULES=y
++
++# CONFIG_EVM is not set
++# CONFIG_PWM_PCA9685 is not set
++
++CONFIG_LSM_MMAP_MIN_ADDR=65536
++
++CONFIG_STRIP_ASM_SYMS=y
++
++# CONFIG_RCU_FANOUT_EXACT is not set
++# FIXME: Revisit FAST_NO_HZ after it's fixed
++# CONFIG_RCU_FAST_NO_HZ is not set
++# CONFIG_RCU_NOCB_CPU is not set
++CONFIG_RCU_CPU_STALL_TIMEOUT=60
++# CONFIG_RCU_TORTURE_TEST is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_RCU_CPU_STALL_INFO is not set
++# CONFIG_RCU_USER_QS is not set
++
++CONFIG_KSM=y
++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
++
++CONFIG_FSNOTIFY=y
++CONFIG_FANOTIFY=y
++CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
++
++CONFIG_IEEE802154=m
++CONFIG_IEEE802154_6LOWPAN=m
++CONFIG_IEEE802154_DRIVERS=m
++CONFIG_IEEE802154_FAKEHARD=m
++CONFIG_IEEE802154_FAKELB=m
++
++CONFIG_MAC802154=m
++CONFIG_NET_MPLS_GSO=m
++
++# CONFIG_HSR is not set
++
++# CONFIG_EXTCON is not set
++# CONFIG_EXTCON_ADC_JACK is not set
++# CONFIG_MEMORY is not set
++
++CONFIG_PPS=m
++# CONFIG_PPS_CLIENT_KTIMER is not set
++CONFIG_PPS_CLIENT_LDISC=m
++# CONFIG_PPS_DEBUG is not set
++CONFIG_PPS_CLIENT_PARPORT=m
++CONFIG_PPS_GENERATOR_PARPORT=m
++CONFIG_PPS_CLIENT_GPIO=m
++CONFIG_NTP_PPS=y
++
++CONFIG_PTP_1588_CLOCK=m
++CONFIG_PTP_1588_CLOCK_PCH=m
++
++CONFIG_CLEANCACHE=y
++# CONFIG_PGTABLE_MAPPING is not set
++
++# CONFIG_MDIO_GPIO is not set
++# CONFIG_KEYBOARD_GPIO_POLLED is not set
++# CONFIG_MOUSE_GPIO is not set
++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
++# CONFIG_I2C_DESIGNWARE_PCI is not set
++# CONFIG_I2C_GPIO is not set
++# CONFIG_DEBUG_GPIO is not set
++# CONFIG_GPIO_GENERIC_PLATFORM is not set
++# CONFIG_GPIO_CS5535 is not set
++# CONFIG_GPIO_IT8761E is not set
++# CONFIG SB105x is not set
++# CONFIG_GPIO_TS5500 is not set
++# CONFIG_GPIO_VIPERBOARD is not set
++# CONFIG_UCB1400_CORE is not set
++# CONFIG_TPS6105X is not set
++# CONFIG_RADIO_MIROPCM20 is not set
++# CONFIG_USB_GPIO_VBUS is not set
++# CONFIG_GPIO_SCH is not set
++# CONFIG_GPIO_LANGWELL is not set
++# CONFIG_GPIO_RDC321X is not set
++# CONFIG_GPIO_VX855 is not set
++# CONFIG_GPIO_PCH is not set
++# CONFIG_GPIO_ML_IOH is not set
++# CONFIG_GPIO_AMD8111 is not set
++# CONFIG_GPIO_BT8XX is not set
++# CONFIG_GPIO_GRGPIO is not set
++# CONFIG_GPIO_PL061 is not set
++# CONFIG_GPIO_BCM_KONA is not set
++# CONFIG_GPIO_SCH311X is not set
++CONFIG_GPIO_MAX730X=m
++CONFIG_GPIO_MAX7300=m
++CONFIG_GPIO_MAX732X=m
++CONFIG_GPIO_PCF857X=m
++CONFIG_GPIO_SX150X=y
++CONFIG_GPIO_ADP5588=m
++CONFIG_GPIO_ADNP=m
++CONFIG_GPIO_MAX7301=m
++CONFIG_GPIO_MCP23S08=m
++CONFIG_GPIO_MC33880=m
++CONFIG_GPIO_74X164=m
++
++CONFIG_TEST_KSTRTOX=y
++
++# CONFIG_POWER_AVS is not set
++
++CONFIG_TARGET_CORE=m
++CONFIG_ISCSI_TARGET=m
++CONFIG_LOOPBACK_TARGET=m
++CONFIG_SBP_TARGET=m
++CONFIG_TCM_IBLOCK=m
++CONFIG_TCM_FILEIO=m
++CONFIG_TCM_PSCSI=m
++CONFIG_TCM_FC=m
++
++CONFIG_HWSPINLOCK=m
++
++CONFIG_PSTORE=y
++CONFIG_PSTORE_RAM=m
++# CONFIG_PSTORE_CONSOLE is not set
++# CONFIG_PSTORE_FTRACE is not set
++
++# CONFIG_TEST_MODULE is not set
++# CONFIG_TEST_USER_COPY is not set
++
++# CONFIG_AVERAGE is not set
++# CONFIG_VMXNET3 is not set
++
++# CONFIG_SIGMA is not set
++
++CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
++
++CONFIG_BCMA=m
++CONFIG_BCMA_BLOCKIO=y
++CONFIG_BCMA_HOST_PCI_POSSIBLE=y
++CONFIG_BCMA_HOST_PCI=y
++# CONFIG_BCMA_HOST_SOC is not set
++CONFIG_BCMA_DRIVER_GMAC_CMN=y
++CONFIG_BCMA_DRIVER_GPIO=y
++# CONFIG_BCMA_DEBUG is not set
++
++# CONFIG_GOOGLE_FIRMWARE is not set
++# CONFIG_INTEL_MID_PTI is not set
++
++# CONFIG_MAILBOX is not set
++
++CONFIG_FMC=m
++CONFIG_FMC_FAKEDEV=m
++CONFIG_FMC_TRIVIAL=m
++CONFIG_FMC_WRITE_EEPROM=m
++CONFIG_FMC_CHARDEV=m
++
++# CONFIG_GENWQE is not set
++
++# CONFIG_POWERCAP is not set
++
++# CONFIG_HSI is not set
++
++
++# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
++
++# CONFIG_PM_DEVFREQ is not set
++# CONFIG_MODULE_SIG is not set
++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set
++# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set
++# CONFIG_MODULE_VERIFY_ELF is not set
++# CONFIG_CRYPTO_KEY_TYPE is not set
++# CONFIG_PGP_LIBRARY is not set
++# CONFIG_PGP_PRELOAD is not set
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_PROC_DEVICETREE=y
++
+diff -Nur linux-3.14.72.orig/arch/arm/configs/imx_v7_defconfig linux-3.14.72/arch/arm/configs/imx_v7_defconfig
+--- linux-3.14.72.orig/arch/arm/configs/imx_v7_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/configs/imx_v7_defconfig 2016-06-19 22:11:55.037157623 +0200
+@@ -0,0 +1,414 @@
++CONFIG_KERNEL_LZO=y
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PERF_EVENTS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++CONFIG_MACH_IMX51_DT=y
++CONFIG_MACH_EUKREA_CPUIMX51SD=y
++CONFIG_SOC_IMX50=y
++CONFIG_SOC_IMX53=y
++CONFIG_SOC_IMX6Q=y
++CONFIG_SOC_IMX6SL=y
++CONFIG_SOC_IMX6SX=y
++CONFIG_SOC_VF610=y
++# CONFIG_SWP_EMULATE is not set
++CONFIG_SMP=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_PREEMPT=y
++CONFIG_AEABI=y
++CONFIG_HIGHMEM=y
++CONFIG_CMA=y
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_KEXEC=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6Q_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_TEST_SUSPEND=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_VLAN_8021Q=y
++CONFIG_LLC2=y
++CONFIG_CAN=y
++CONFIG_CAN_FLEXCAN=y
++CONFIG_CAN_M_CAN=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_HCIBTUSB=y
++CONFIG_BT_HCIBTSDIO=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_H4=y
++CONFIG_BT_HCIUART_BCSP=y
++CONFIG_BT_HCIUART_ATH3K=y
++CONFIG_BT_HCIBCM203X=y
++CONFIG_BT_ATH3K=y
++CONFIG_CFG80211=y
++CONFIG_MAC80211=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=320
++CONFIG_IMX_WEIM=y
++CONFIG_CONNECTOR=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_M25P80=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_GPMI_NAND=y
++CONFIG_MTD_NAND_MXC=y
++CONFIG_MTD_SPI_NOR=y
++CONFIG_SPI_FSL_QUADSPI=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_EEPROM_AT24=y
++CONFIG_EEPROM_AT25=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_PATA_IMX=y
++CONFIG_NETDEVICES=y
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_CS89x0=y
++CONFIG_CS89x0_PLATFORM=y
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_SMC91X=y
++CONFIG_SMC911X=y
++CONFIG_SMSC911X=y
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_USB_PEGASUS=m
++CONFIG_USB_RTL8150=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_USBNET=m
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_ATH_CARDS=y
++CONFIG_ATH6KL=m
++CONFIG_ATH6KL_SDIO=m
++CONFIG_BRCMFMAC=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_EVDEV=y
++CONFIG_INPUT_EVBUG=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_SNVS_PWRKEY=y
++CONFIG_KEYBOARD_IMX=y
++CONFIG_MOUSE_PS2=m
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EGALAX=y
++CONFIG_TOUCHSCREEN_ELAN=y
++CONFIG_TOUCHSCREEN_MAX11801=y
++CONFIG_TOUCHSCREEN_MC13783=y
++CONFIG_TOUCHSCREEN_TSC2007=y
++CONFIG_TOUCHSCREEN_STMPE=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_MMA8450=y
++CONFIG_INPUT_ISL29023=y
++CONFIG_SERIO_SERPORT=m
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_FSL_OTP=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_GPIO_SYSFS=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_SABRESD_MAX8903=y
++CONFIG_SENSORS_MAX17135=y
++CONFIG_SENSORS_MAG3110=y
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_MAX17135=y
++CONFIG_MFD_SI476X_CORE=y
++CONFIG_MFD_STMPE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_DA9052=y
++CONFIG_REGULATOR_MAX17135=y
++CONFIG_REGULATOR_MC13783=y
++CONFIG_REGULATOR_MC13892=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_RADIO_SUPPORT=y
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_CAPTURE=m
++CONFIG_MXC_CAMERA_OV5640=m
++CONFIG_MXC_CAMERA_OV5642=m
++CONFIG_MXC_CAMERA_OV5640_MIPI=m
++CONFIG_MXC_TVIN_ADV7180=m
++CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_VIDEO_MXC_CSI_CAMERA=m
++CONFIG_MXC_VADC=m
++CONFIG_SOC_CAMERA=y
++CONFIG_VIDEO_MX3=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_CODA=y
++CONFIG_RADIO_SI476X=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB=y
++CONFIG_FB_MXS=y
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_LCD_L4F00242T03=y
++CONFIG_LCD_PLATFORM=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_MIPI_DSI=y
++CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FB_MXC_EINK_PANEL=y
++CONFIG_FB_MXS_SII902X=y
++CONFIG_FB_MXC_DCIC=m
++CONFIG_HANNSTAR_CABC=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_EUKREA_TLV320=y
++CONFIG_SND_SOC_IMX_CS42888=y
++CONFIG_SND_SOC_IMX_WM8962=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++CONFIG_SND_SOC_IMX_MQS=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_MC13783=y
++CONFIG_SND_SOC_IMX_HDMI=y
++CONFIG_SND_SOC_IMX_SI476X=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_MXC=y
++CONFIG_USB_ACM=m
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_USB_EHSET_TEST_FIXTURE=m
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_ZERO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_G_NCM=m
++CONFIG_USB_GADGETFS=m
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++CONFIG_MXC_GPU_VIV=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_MXC_MLB150=m
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_INTF_DEV_UIE_EMUL=y
++CONFIG_RTC_DRV_MC13XXX=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_IIO=y
++CONFIG_VF610_ADC=y
++CONFIG_PWM=y
++CONFIG_PWM_IMX=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_DEBUG_FS=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_TEST=m
++CONFIG_CRYPTO_GCM=y
++CONFIG_CRYPTO_CBC=y
++CONFIG_CRYPTO_CTS=y
++CONFIG_CRYPTO_LRW=y
++CONFIG_CRYPTO_XTS=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_MICHAEL_MIC=y
++CONFIG_CRYPTO_RMD128=y
++CONFIG_CRYPTO_RMD160=y
++CONFIG_CRYPTO_RMD256=y
++CONFIG_CRYPTO_RMD320=y
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA512=y
++CONFIG_CRYPTO_TGR192=y
++CONFIG_CRYPTO_WP512=y
++CONFIG_CRYPTO_BLOWFISH=y
++CONFIG_CRYPTO_CAMELLIA=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_TWOFISH=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++CONFIG_CRYPTO_DEV_FSL_CAAM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
++CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
+diff -Nur linux-3.14.72.orig/arch/arm/configs/imx_v7_mfg_defconfig linux-3.14.72/arch/arm/configs/imx_v7_mfg_defconfig
+--- linux-3.14.72.orig/arch/arm/configs/imx_v7_mfg_defconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/configs/imx_v7_mfg_defconfig 2016-06-19 22:11:55.037157623 +0200
+@@ -0,0 +1,332 @@
++# CONFIG_LOCALVERSION_AUTO is not set
++CONFIG_KERNEL_LZO=y
++CONFIG_SYSVIPC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_CGROUPS=y
++CONFIG_RELAY=y
++CONFIG_BLK_DEV_INITRD=y
++CONFIG_EXPERT=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PERF_EVENTS=y
++# CONFIG_SLUB_DEBUG is not set
++# CONFIG_COMPAT_BRK is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_MODULE_SRCVERSION_ALL=y
++# CONFIG_BLK_DEV_BSG is not set
++CONFIG_ARCH_MULTI_V6=y
++CONFIG_GPIO_PCA953X=y
++CONFIG_ARCH_MXC=y
++# CONFIG_MACH_MX31ADS is not set
++# CONFIG_MACH_BUG is not set
++CONFIG_MACH_IMX51_DT=y
++CONFIG_MACH_EUKREA_CPUIMX51SD=y
++CONFIG_SOC_IMX50=y
++CONFIG_SOC_IMX53=y
++CONFIG_SOC_IMX6Q=y
++CONFIG_SOC_IMX6SL=y
++CONFIG_SOC_IMX6SX=y
++CONFIG_SOC_VF610=y
++CONFIG_SMP=y
++CONFIG_VMSPLIT_2G=y
++CONFIG_PREEMPT=y
++CONFIG_AEABI=y
++CONFIG_HIGHMEM=y
++CONFIG_CMA=y
++CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_ARM_IMX6Q_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_BINFMT_MISC=m
++CONFIG_PM_RUNTIME=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_TEST_SUSPEND=y
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_UNIX=y
++CONFIG_INET=y
++CONFIG_IP_PNP=y
++CONFIG_IP_PNP_DHCP=y
++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
++# CONFIG_INET_XFRM_MODE_TUNNEL is not set
++# CONFIG_INET_XFRM_MODE_BEET is not set
++# CONFIG_INET_LRO is not set
++CONFIG_IPV6=y
++CONFIG_NETFILTER=y
++CONFIG_CFG80211=y
++CONFIG_MAC80211=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_INPUT=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++# CONFIG_STANDALONE is not set
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=320
++CONFIG_IMX_WEIM=y
++CONFIG_CONNECTOR=y
++CONFIG_MTD=y
++CONFIG_MTD_CMDLINE_PARTS=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_CFI=y
++CONFIG_MTD_JEDECPROBE=y
++CONFIG_MTD_CFI_INTELEXT=y
++CONFIG_MTD_CFI_AMDSTD=y
++CONFIG_MTD_CFI_STAA=y
++CONFIG_MTD_PHYSMAP_OF=y
++CONFIG_MTD_DATAFLASH=y
++CONFIG_MTD_M25P80=y
++CONFIG_MTD_SST25L=y
++CONFIG_MTD_NAND=y
++CONFIG_MTD_NAND_GPMI_NAND=y
++CONFIG_MTD_NAND_MXC=y
++CONFIG_MTD_SPI_NOR=y
++CONFIG_SPI_FSL_QUADSPI=y
++CONFIG_MTD_UBI=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_RAM=y
++CONFIG_BLK_DEV_RAM_SIZE=65536
++CONFIG_EEPROM_AT24=y
++CONFIG_EEPROM_AT25=y
++# CONFIG_SCSI_PROC_FS is not set
++CONFIG_BLK_DEV_SD=y
++CONFIG_SCSI_MULTI_LUN=y
++CONFIG_SCSI_CONSTANTS=y
++CONFIG_SCSI_LOGGING=y
++CONFIG_SCSI_SCAN_ASYNC=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_IMX=y
++CONFIG_PATA_IMX=y
++CONFIG_NETDEVICES=y
++# CONFIG_NET_VENDOR_BROADCOM is not set
++CONFIG_CS89x0=y
++CONFIG_CS89x0_PLATFORM=y
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++CONFIG_SMC91X=y
++CONFIG_SMC911X=y
++CONFIG_SMSC911X=y
++# CONFIG_NET_VENDOR_STMICRO is not set
++CONFIG_AT803X_PHY=y
++CONFIG_BRCMFMAC=m
++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
++CONFIG_INPUT_EVDEV=y
++CONFIG_INPUT_EVBUG=m
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_IMX=y
++CONFIG_MOUSE_PS2=m
++CONFIG_MOUSE_PS2_ELANTECH=y
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EGALAX=y
++CONFIG_TOUCHSCREEN_MC13783=y
++CONFIG_TOUCHSCREEN_TSC2007=y
++CONFIG_TOUCHSCREEN_STMPE=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_MMA8450=y
++CONFIG_SERIO_SERPORT=m
++# CONFIG_LEGACY_PTYS is not set
++# CONFIG_DEVKMEM is not set
++CONFIG_SERIAL_IMX=y
++CONFIG_SERIAL_IMX_CONSOLE=y
++CONFIG_SERIAL_FSL_LPUART=y
++CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
++CONFIG_HW_RANDOM=y
++CONFIG_IMX_SEMA4=y
++# CONFIG_I2C_COMPAT is not set
++CONFIG_I2C_CHARDEV=y
++# CONFIG_I2C_HELPER_AUTO is not set
++CONFIG_I2C_ALGOPCF=m
++CONFIG_I2C_ALGOPCA=m
++CONFIG_I2C_IMX=y
++CONFIG_SPI=y
++CONFIG_SPI_IMX=y
++CONFIG_GPIO_SYSFS=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_CPU_THERMAL=y
++CONFIG_IMX_THERMAL=y
++CONFIG_DEVICE_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_IMX2_WDT=y
++CONFIG_MFD_DA9052_I2C=y
++CONFIG_MFD_MC13XXX_SPI=y
++CONFIG_MFD_MC13XXX_I2C=y
++CONFIG_MFD_STMPE=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_ANATOP=y
++CONFIG_REGULATOR_DA9052=y
++CONFIG_REGULATOR_MC13783=y
++CONFIG_REGULATOR_MC13892=y
++CONFIG_REGULATOR_PFUZE100=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_RC_SUPPORT=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_VIDEO_MXC_OUTPUT=y
++CONFIG_VIDEO_MXC_IPU_OUTPUT=y
++CONFIG_VIDEO_MXC_PXP_V4L2=y
++CONFIG_SOC_CAMERA=y
++CONFIG_VIDEO_MX3=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_CODA=y
++CONFIG_SOC_CAMERA_OV2640=y
++CONFIG_DRM=y
++CONFIG_DRM_VIVANTE=y
++CONFIG_FB=y
++CONFIG_FB_MXS=y
++CONFIG_BACKLIGHT_LCD_SUPPORT=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_LCD_L4F00242T03=y
++CONFIG_LCD_PLATFORM=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FB_MXC_SYNC_PANEL=y
++CONFIG_FB_MXC_LDB=y
++CONFIG_FB_MXC_MIPI_DSI=y
++CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
++CONFIG_FB_MXC_HDMI=y
++CONFIG_FB_MXC_EINK_PANEL=y
++CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE=y
++CONFIG_FB_MXS_SII902X=y
++CONFIG_HANNSTAR_CABC=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_SOC=y
++CONFIG_SND_IMX_SOC=y
++CONFIG_SND_SOC_EUKREA_TLV320=y
++CONFIG_SND_SOC_IMX_WM8962=y
++CONFIG_SND_SOC_IMX_SGTL5000=y
++CONFIG_SND_SOC_IMX_SPDIF=y
++CONFIG_SND_SOC_IMX_MC13783=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_MXC=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_CHIPIDEA=y
++CONFIG_USB_CHIPIDEA_UDC=y
++CONFIG_USB_CHIPIDEA_HOST=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_MXS_PHY=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_ETH=m
++CONFIG_USB_PHY=y
++# CONFIG_USB_ZERO is not set
++# CONFIG_USB_AUDIO is not set
++# CONFIG_USB_ETH is not set
++# CONFIG_USB_G_NCM is not set
++# CONFIG_USB_GADGETFS is not set
++# CONFIG_USB_FUNCTIONFS is not set
++CONFIG_USB_MASS_STORAGE=y
++CONFIG_FSL_UTP=y
++# CONFIG_USB_G_SERIAL is not set
++# CONFIG_USB_MIDI_GADGET is not set
++# CONFIG_USB_G_PRINTER is not set
++# CONFIG_USB_CDC_COMPOSITE is not set
++# CONFIG_USB_G_ACM_MS is not set
++# CONFIG_USB_G_MULTI is not set
++# CONFIG_USB_G_HID is not set
++# CONFIG_USB_G_DBGP is not set
++# CONFIG_USB_G_WEBCAM is not set
++CONFIG_MMC=y
++CONFIG_MMC_UNSAFE_RESUME=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_ESDHC_IMX=y
++CONFIG_MXC_IPU=y
++CONFIG_MXC_GPU_VIV=y
++CONFIG_MXC_MIPI_CSI2=y
++CONFIG_MXC_MLB150=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGERS=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_GPIO=y
++CONFIG_RTC_CLASS=y
++CONFIG_RTC_INTF_DEV_UIE_EMUL=y
++CONFIG_RTC_DRV_MC13XXX=y
++CONFIG_RTC_DRV_MXC=y
++CONFIG_RTC_DRV_SNVS=y
++CONFIG_DMADEVICES=y
++CONFIG_MXC_PXP_V2=y
++CONFIG_IMX_SDMA=y
++CONFIG_MXS_DMA=y
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PWM=y
++CONFIG_PWM_IMX=y
++CONFIG_EXT2_FS=y
++CONFIG_EXT2_FS_XATTR=y
++CONFIG_EXT2_FS_POSIX_ACL=y
++CONFIG_EXT2_FS_SECURITY=y
++CONFIG_EXT3_FS=y
++CONFIG_EXT3_FS_POSIX_ACL=y
++CONFIG_EXT3_FS_SECURITY=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_EXT4_FS_SECURITY=y
++CONFIG_QUOTA=y
++CONFIG_QUOTA_NETLINK_INTERFACE=y
++# CONFIG_PRINT_QUOTA_WARNING is not set
++CONFIG_AUTOFS4_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_ISO9660_FS=m
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=m
++CONFIG_MSDOS_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_TMPFS=y
++CONFIG_JFFS2_FS=y
++CONFIG_UBIFS_FS=y
++CONFIG_NFS_FS=y
++CONFIG_NFS_V3_ACL=y
++CONFIG_NFS_V4=y
++CONFIG_ROOT_NFS=y
++CONFIG_NLS_DEFAULT="cp437"
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_ASCII=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_15=m
++CONFIG_NLS_UTF8=y
++CONFIG_MAGIC_SYSRQ=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_DEBUG_BUGVERBOSE is not set
++# CONFIG_FTRACE is not set
++CONFIG_SECURITYFS=y
++# CONFIG_CRYPTO_ANSI_CPRNG is not set
++# CONFIG_CRYPTO_HW is not set
++CONFIG_CRC_CCITT=m
++CONFIG_CRC_T10DIF=y
++CONFIG_CRC7=m
++CONFIG_LIBCRC32C=m
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
+diff -Nur linux-3.14.72.orig/arch/arm/configs/mxs_defconfig linux-3.14.72/arch/arm/configs/mxs_defconfig
+--- linux-3.14.72.orig/arch/arm/configs/mxs_defconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/configs/mxs_defconfig 2016-06-19 22:11:55.037157623 +0200
+@@ -55,6 +55,7 @@
+ CONFIG_MTD_SST25L=y
+ CONFIG_MTD_NAND=y
+ CONFIG_MTD_NAND_GPMI_NAND=y
++CONFIG_MTD_SPI_NOR=y
+ CONFIG_MTD_UBI=y
+ # CONFIG_BLK_DEV is not set
+ CONFIG_EEPROM_AT24=y
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/atomic.h linux-3.14.72/arch/arm/include/asm/atomic.h
+--- linux-3.14.72.orig/arch/arm/include/asm/atomic.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/atomic.h 2016-06-19 22:11:55.037157623 +0200
+@@ -60,6 +60,7 @@
+ int result;
+
+ smp_mb();
++ prefetchw(&v->counter);
+
+ __asm__ __volatile__("@ atomic_add_return\n"
+ "1: ldrex %0, [%3]\n"
+@@ -99,6 +100,7 @@
+ int result;
+
+ smp_mb();
++ prefetchw(&v->counter);
+
+ __asm__ __volatile__("@ atomic_sub_return\n"
+ "1: ldrex %0, [%3]\n"
+@@ -121,6 +123,7 @@
+ unsigned long res;
+
+ smp_mb();
++ prefetchw(&ptr->counter);
+
+ do {
+ __asm__ __volatile__("@ atomic_cmpxchg\n"
+@@ -138,6 +141,33 @@
+ return oldval;
+ }
+
++static inline int __atomic_add_unless(atomic_t *v, int a, int u)
++{
++ int oldval, newval;
++ unsigned long tmp;
++
++ smp_mb();
++ prefetchw(&v->counter);
++
++ __asm__ __volatile__ ("@ atomic_add_unless\n"
++"1: ldrex %0, [%4]\n"
++" teq %0, %5\n"
++" beq 2f\n"
++" add %1, %0, %6\n"
++" strex %2, %1, [%4]\n"
++" teq %2, #0\n"
++" bne 1b\n"
++"2:"
++ : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
++ : "r" (&v->counter), "r" (u), "r" (a)
++ : "cc");
++
++ if (oldval != u)
++ smp_mb();
++
++ return oldval;
++}
++
+ #else /* ARM_ARCH_6 */
+
+ #ifdef CONFIG_SMP
+@@ -186,10 +216,6 @@
+ return ret;
+ }
+
+-#endif /* __LINUX_ARM_ARCH__ */
+-
+-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+-
+ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+ {
+ int c, old;
+@@ -200,6 +226,10 @@
+ return c;
+ }
+
++#endif /* __LINUX_ARM_ARCH__ */
++
++#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
++
+ #define atomic_inc(v) atomic_add(1, v)
+ #define atomic_dec(v) atomic_sub(1, v)
+
+@@ -299,6 +329,7 @@
+ unsigned long tmp;
+
+ smp_mb();
++ prefetchw(&v->counter);
+
+ __asm__ __volatile__("@ atomic64_add_return\n"
+ "1: ldrexd %0, %H0, [%3]\n"
+@@ -340,6 +371,7 @@
+ unsigned long tmp;
+
+ smp_mb();
++ prefetchw(&v->counter);
+
+ __asm__ __volatile__("@ atomic64_sub_return\n"
+ "1: ldrexd %0, %H0, [%3]\n"
+@@ -364,6 +396,7 @@
+ unsigned long res;
+
+ smp_mb();
++ prefetchw(&ptr->counter);
+
+ do {
+ __asm__ __volatile__("@ atomic64_cmpxchg\n"
+@@ -388,6 +421,7 @@
+ unsigned long tmp;
+
+ smp_mb();
++ prefetchw(&ptr->counter);
+
+ __asm__ __volatile__("@ atomic64_xchg\n"
+ "1: ldrexd %0, %H0, [%3]\n"
+@@ -409,6 +443,7 @@
+ unsigned long tmp;
+
+ smp_mb();
++ prefetchw(&v->counter);
+
+ __asm__ __volatile__("@ atomic64_dec_if_positive\n"
+ "1: ldrexd %0, %H0, [%3]\n"
+@@ -436,6 +471,7 @@
+ int ret = 1;
+
+ smp_mb();
++ prefetchw(&v->counter);
+
+ __asm__ __volatile__("@ atomic64_add_unless\n"
+ "1: ldrexd %0, %H0, [%4]\n"
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/cmpxchg.h linux-3.14.72/arch/arm/include/asm/cmpxchg.h
+--- linux-3.14.72.orig/arch/arm/include/asm/cmpxchg.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/cmpxchg.h 2016-06-19 22:11:55.041157465 +0200
+@@ -2,6 +2,7 @@
+ #define __ASM_ARM_CMPXCHG_H
+
+ #include <linux/irqflags.h>
++#include <linux/prefetch.h>
+ #include <asm/barrier.h>
+
+ #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+@@ -35,6 +36,7 @@
+ #endif
+
+ smp_mb();
++ prefetchw((const void *)ptr);
+
+ switch (size) {
+ #if __LINUX_ARM_ARCH__ >= 6
+@@ -138,6 +140,8 @@
+ {
+ unsigned long oldval, res;
+
++ prefetchw((const void *)ptr);
++
+ switch (size) {
+ #ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
+ case 1:
+@@ -230,6 +234,8 @@
+ unsigned long long oldval;
+ unsigned long res;
+
++ prefetchw(ptr);
++
+ __asm__ __volatile__(
+ "1: ldrexd %1, %H1, [%3]\n"
+ " teq %1, %4\n"
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/futex.h linux-3.14.72/arch/arm/include/asm/futex.h
+--- linux-3.14.72.orig/arch/arm/include/asm/futex.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/futex.h 2016-06-19 22:11:55.041157465 +0200
+@@ -23,6 +23,7 @@
+
+ #define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
+ smp_mb(); \
++ prefetchw(uaddr); \
+ __asm__ __volatile__( \
+ "1: ldrex %1, [%3]\n" \
+ " " insn "\n" \
+@@ -46,6 +47,8 @@
+ return -EFAULT;
+
+ smp_mb();
++ /* Prefetching cannot fault */
++ prefetchw(uaddr);
+ __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
+ "1: ldrex %1, [%4]\n"
+ " teq %1, %2\n"
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/glue-proc.h linux-3.14.72/arch/arm/include/asm/glue-proc.h
+--- linux-3.14.72.orig/arch/arm/include/asm/glue-proc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/glue-proc.h 2016-06-19 22:11:55.041157465 +0200
+@@ -221,15 +221,6 @@
+ # endif
+ #endif
+
+-#ifdef CONFIG_CPU_V7
+-# ifdef CPU_NAME
+-# undef MULTI_CPU
+-# define MULTI_CPU
+-# else
+-# define CPU_NAME cpu_v7
+-# endif
+-#endif
+-
+ #ifdef CONFIG_CPU_V7M
+ # ifdef CPU_NAME
+ # undef MULTI_CPU
+@@ -248,6 +239,15 @@
+ # endif
+ #endif
+
++#ifdef CONFIG_CPU_V7
++/*
++ * Cortex-A9 needs a different suspend/resume function, so we need
++ * multiple CPU support for ARMv7 anyway.
++ */
++# undef MULTI_CPU
++# define MULTI_CPU
++#endif
++
+ #ifndef MULTI_CPU
+ #define cpu_proc_init __glue(CPU_NAME,_proc_init)
+ #define cpu_proc_fin __glue(CPU_NAME,_proc_fin)
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/hardware/cache-l2x0.h linux-3.14.72/arch/arm/include/asm/hardware/cache-l2x0.h
+--- linux-3.14.72.orig/arch/arm/include/asm/hardware/cache-l2x0.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/hardware/cache-l2x0.h 2016-06-19 22:11:55.041157465 +0200
+@@ -26,8 +26,8 @@
+ #define L2X0_CACHE_TYPE 0x004
+ #define L2X0_CTRL 0x100
+ #define L2X0_AUX_CTRL 0x104
+-#define L2X0_TAG_LATENCY_CTRL 0x108
+-#define L2X0_DATA_LATENCY_CTRL 0x10C
++#define L310_TAG_LATENCY_CTRL 0x108
++#define L310_DATA_LATENCY_CTRL 0x10C
+ #define L2X0_EVENT_CNT_CTRL 0x200
+ #define L2X0_EVENT_CNT1_CFG 0x204
+ #define L2X0_EVENT_CNT0_CFG 0x208
+@@ -54,53 +54,85 @@
+ #define L2X0_LOCKDOWN_WAY_D_BASE 0x900
+ #define L2X0_LOCKDOWN_WAY_I_BASE 0x904
+ #define L2X0_LOCKDOWN_STRIDE 0x08
+-#define L2X0_ADDR_FILTER_START 0xC00
+-#define L2X0_ADDR_FILTER_END 0xC04
++#define L310_ADDR_FILTER_START 0xC00
++#define L310_ADDR_FILTER_END 0xC04
+ #define L2X0_TEST_OPERATION 0xF00
+ #define L2X0_LINE_DATA 0xF10
+ #define L2X0_LINE_TAG 0xF30
+ #define L2X0_DEBUG_CTRL 0xF40
+-#define L2X0_PREFETCH_CTRL 0xF60
+-#define L2X0_POWER_CTRL 0xF80
+-#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
+-#define L2X0_STNDBY_MODE_EN (1 << 0)
++#define L310_PREFETCH_CTRL 0xF60
++#define L310_POWER_CTRL 0xF80
++#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
++#define L310_STNDBY_MODE_EN (1 << 0)
+
+ /* Registers shifts and masks */
+ #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+ #define L2X0_CACHE_ID_PART_L210 (1 << 6)
++#define L2X0_CACHE_ID_PART_L220 (2 << 6)
+ #define L2X0_CACHE_ID_PART_L310 (3 << 6)
+ #define L2X0_CACHE_ID_RTL_MASK 0x3f
+-#define L2X0_CACHE_ID_RTL_R0P0 0x0
+-#define L2X0_CACHE_ID_RTL_R1P0 0x2
+-#define L2X0_CACHE_ID_RTL_R2P0 0x4
+-#define L2X0_CACHE_ID_RTL_R3P0 0x5
+-#define L2X0_CACHE_ID_RTL_R3P1 0x6
+-#define L2X0_CACHE_ID_RTL_R3P2 0x8
+-
+-#define L2X0_AUX_CTRL_MASK 0xc0000fff
++#define L210_CACHE_ID_RTL_R0P2_02 0x00
++#define L210_CACHE_ID_RTL_R0P1 0x01
++#define L210_CACHE_ID_RTL_R0P2_01 0x02
++#define L210_CACHE_ID_RTL_R0P3 0x03
++#define L210_CACHE_ID_RTL_R0P4 0x0b
++#define L210_CACHE_ID_RTL_R0P5 0x0f
++#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
++#define L310_CACHE_ID_RTL_R0P0 0x00
++#define L310_CACHE_ID_RTL_R1P0 0x02
++#define L310_CACHE_ID_RTL_R2P0 0x04
++#define L310_CACHE_ID_RTL_R3P0 0x05
++#define L310_CACHE_ID_RTL_R3P1 0x06
++#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
++#define L310_CACHE_ID_RTL_R3P2 0x08
++#define L310_CACHE_ID_RTL_R3P3 0x09
++
++/* L2C auxiliary control register - bits common to L2C-210/220/310 */
++#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
++#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
++#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
++#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
++#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
++#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
++/* L2C-210/220 common bits */
+ #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
+-#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
++#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
+ #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
+-#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
++#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
+ #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
+-#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
++#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
+ #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
+-#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
+-#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
+-#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
+-#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
+-#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
+-#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
+-#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
+-#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28
+-#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
+-#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
+-
+-#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
+-#define L2X0_LATENCY_CTRL_RD_SHIFT 4
+-#define L2X0_LATENCY_CTRL_WR_SHIFT 8
++#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
++#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
++#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
++/* L2C-210 specific bits */
++#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
++#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
++#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
++/* L2C-220 specific bits */
++#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
++#define L220_AUX_CTRL_FWA_SHIFT 23
++#define L220_AUX_CTRL_FWA_MASK (3 << 23)
++#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
++#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
++/* L2C-310 specific bits */
++#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
++#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
++#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
++#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
++#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
++#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
++#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
++#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
++#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
++#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
++#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
++
++#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
++#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
++#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
+
+-#define L2X0_ADDR_FILTER_EN 1
++#define L310_ADDR_FILTER_EN 1
+
+ #define L2X0_CTRL_EN 1
+
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/Kbuild linux-3.14.72/arch/arm/include/asm/Kbuild
+--- linux-3.14.72.orig/arch/arm/include/asm/Kbuild 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/Kbuild 2016-06-19 22:11:55.041157465 +0200
+@@ -18,6 +18,7 @@
+ generic-y += parport.h
+ generic-y += poll.h
+ generic-y += resource.h
++generic-y += rwsem.h
+ generic-y += sections.h
+ generic-y += segment.h
+ generic-y += sembuf.h
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/outercache.h linux-3.14.72/arch/arm/include/asm/outercache.h
+--- linux-3.14.72.orig/arch/arm/include/asm/outercache.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/outercache.h 2016-06-19 22:11:55.041157465 +0200
+@@ -21,6 +21,7 @@
+ #ifndef __ASM_OUTERCACHE_H
+ #define __ASM_OUTERCACHE_H
+
++#include <linux/bug.h>
+ #include <linux/types.h>
+
+ struct outer_cache_fns {
+@@ -28,53 +29,84 @@
+ void (*clean_range)(unsigned long, unsigned long);
+ void (*flush_range)(unsigned long, unsigned long);
+ void (*flush_all)(void);
+- void (*inv_all)(void);
+ void (*disable)(void);
+ #ifdef CONFIG_OUTER_CACHE_SYNC
+ void (*sync)(void);
+ #endif
+- void (*set_debug)(unsigned long);
+ void (*resume)(void);
++
++ /* This is an ARM L2C thing */
++ void (*write_sec)(unsigned long, unsigned);
+ };
+
+ extern struct outer_cache_fns outer_cache;
+
+ #ifdef CONFIG_OUTER_CACHE
+-
++/**
++ * outer_inv_range - invalidate range of outer cache lines
++ * @start: starting physical address, inclusive
++ * @end: end physical address, exclusive
++ */
+ static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
+ {
+ if (outer_cache.inv_range)
+ outer_cache.inv_range(start, end);
+ }
++
++/**
++ * outer_clean_range - clean dirty outer cache lines
++ * @start: starting physical address, inclusive
++ * @end: end physical address, exclusive
++ */
+ static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
+ {
+ if (outer_cache.clean_range)
+ outer_cache.clean_range(start, end);
+ }
++
++/**
++ * outer_flush_range - clean and invalidate outer cache lines
++ * @start: starting physical address, inclusive
++ * @end: end physical address, exclusive
++ */
+ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
+ {
+ if (outer_cache.flush_range)
+ outer_cache.flush_range(start, end);
+ }
+
++/**
++ * outer_flush_all - clean and invalidate all cache lines in the outer cache
++ *
++ * Note: depending on implementation, this may not be atomic - it must
++ * only be called with interrupts disabled and no other active outer
++ * cache masters.
++ *
++ * It is intended that this function is only used by implementations
++ * needing to override the outer_cache.disable() method due to security.
++ * (Some implementations perform this as a clean followed by an invalidate.)
++ */
+ static inline void outer_flush_all(void)
+ {
+ if (outer_cache.flush_all)
+ outer_cache.flush_all();
+ }
+
+-static inline void outer_inv_all(void)
+-{
+- if (outer_cache.inv_all)
+- outer_cache.inv_all();
+-}
+-
+-static inline void outer_disable(void)
+-{
+- if (outer_cache.disable)
+- outer_cache.disable();
+-}
+-
++/**
++ * outer_disable - clean, invalidate and disable the outer cache
++ *
++ * Disable the outer cache, ensuring that any data contained in the outer
++ * cache is pushed out to lower levels of system memory. The note and
++ * conditions above concerning outer_flush_all() applies here.
++ */
++extern void outer_disable(void);
++
++/**
++ * outer_resume - restore the cache configuration and re-enable outer cache
++ *
++ * Restore any configuration that the cache had when previously enabled,
++ * and re-enable the outer cache.
++ */
+ static inline void outer_resume(void)
+ {
+ if (outer_cache.resume)
+@@ -90,13 +122,18 @@
+ static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
+ { }
+ static inline void outer_flush_all(void) { }
+-static inline void outer_inv_all(void) { }
+ static inline void outer_disable(void) { }
+ static inline void outer_resume(void) { }
+
+ #endif
+
+ #ifdef CONFIG_OUTER_CACHE_SYNC
++/**
++ * outer_sync - perform a sync point for outer cache
++ *
++ * Ensure that all outer cache operations are complete and any store
++ * buffers are drained.
++ */
+ static inline void outer_sync(void)
+ {
+ if (outer_cache.sync)
+diff -Nur linux-3.14.72.orig/arch/arm/include/asm/smp_plat.h linux-3.14.72/arch/arm/include/asm/smp_plat.h
+--- linux-3.14.72.orig/arch/arm/include/asm/smp_plat.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/asm/smp_plat.h 2016-06-19 22:11:55.041157465 +0200
+@@ -89,6 +89,7 @@
+ return 1 << mpidr_hash.bits;
+ }
+
++extern int platform_can_secondary_boot(void);
+ extern int platform_can_cpu_hotplug(void);
+
+ #endif
+diff -Nur linux-3.14.72.orig/arch/arm/include/debug/imx.S linux-3.14.72/arch/arm/include/debug/imx.S
+--- linux-3.14.72.orig/arch/arm/include/debug/imx.S 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/debug/imx.S 2016-06-19 22:11:55.041157465 +0200
+@@ -19,12 +19,11 @@
+ * globally for multi-platform build to use a fixed virtual address
+ * for low-level debug uart port across platforms.
+ */
+-#define IMX_IO_P2V(x) ( \
+- (((x) & 0x80000000) >> 7) | \
+- (0xf4000000 + \
+- (((x) & 0x50000000) >> 6) + \
+- (((x) & 0x0b000000) >> 4) + \
+- (((x) & 0x000fffff))))
++#define IMX_IO_P2V(x) ( \
++ (0xf4000000 + \
++ (((x) & 0x50000000) >> 4) + \
++ (((x) & 0x0a000000) >> 4) + \
++ (((x) & 0x00ffffff))))
+
+ #define UART_VADDR IMX_IO_P2V(UART_PADDR)
+
+diff -Nur linux-3.14.72.orig/arch/arm/include/debug/imx-uart.h linux-3.14.72/arch/arm/include/debug/imx-uart.h
+--- linux-3.14.72.orig/arch/arm/include/debug/imx-uart.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/include/debug/imx-uart.h 2016-06-19 22:11:55.041157465 +0200
+@@ -81,6 +81,15 @@
+ #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
+ #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
+
++#define IMX6SX_UART1_BASE_ADDR 0x02020000
++#define IMX6SX_UART2_BASE_ADDR 0x021e8000
++#define IMX6SX_UART3_BASE_ADDR 0x021ec000
++#define IMX6SX_UART4_BASE_ADDR 0x021f0000
++#define IMX6SX_UART5_BASE_ADDR 0x021f4000
++#define IMX6SX_UART6_BASE_ADDR 0x022a0000
++#define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR
++#define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n)
++
+ #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
+
+ #ifdef CONFIG_DEBUG_IMX1_UART
+@@ -103,6 +112,8 @@
+ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
+ #elif defined(CONFIG_DEBUG_IMX6SL_UART)
+ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
++#elif defined(CONFIG_DEBUG_IMX6SX_UART)
++#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX)
+ #endif
+
+ #endif /* __DEBUG_IMX_UART_H */
+diff -Nur linux-3.14.72.orig/arch/arm/Kconfig linux-3.14.72/arch/arm/Kconfig
+--- linux-3.14.72.orig/arch/arm/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/Kconfig 2016-06-19 22:11:55.041157465 +0200
+@@ -168,12 +168,9 @@
+ bool
+ default y
+
+-config RWSEM_GENERIC_SPINLOCK
+- bool
+- default y
+-
+ config RWSEM_XCHGADD_ALGORITHM
+ bool
++ default y
+
+ config ARCH_HAS_ILOG2_U32
+ bool
+@@ -1216,19 +1213,6 @@
+ register of the Cortex-A9 which reduces the linefill issuing
+ capabilities of the processor.
+
+-config PL310_ERRATA_588369
+- bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
+- depends on CACHE_L2X0
+- help
+- The PL310 L2 cache controller implements three types of Clean &
+- Invalidate maintenance operations: by Physical Address
+- (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+- They are architecturally defined to behave as the execution of a
+- clean operation followed immediately by an invalidate operation,
+- both performing to the same memory location. This functionality
+- is not correctly implemented in PL310 as clean lines are not
+- invalidated as a result of these operations.
+-
+ config ARM_ERRATA_643719
+ bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
+ depends on CPU_V7 && SMP
+@@ -1251,17 +1235,6 @@
+ tables. The workaround changes the TLB flushing routines to invalidate
+ entries regardless of the ASID.
+
+-config PL310_ERRATA_727915
+- bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
+- depends on CACHE_L2X0
+- help
+- PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+- operation (offset 0x7FC). This operation runs in background so that
+- PL310 can handle normal accesses while it is in progress. Under very
+- rare circumstances, due to this erratum, write data can be lost when
+- PL310 treats a cacheable write transaction during a Clean &
+- Invalidate by Way operation.
+-
+ config ARM_ERRATA_743622
+ bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
+ depends on CPU_V7
+@@ -1287,21 +1260,6 @@
+ operation is received by a CPU before the ICIALLUIS has completed,
+ potentially leading to corrupted entries in the cache or TLB.
+
+-config PL310_ERRATA_753970
+- bool "PL310 errata: cache sync operation may be faulty"
+- depends on CACHE_PL310
+- help
+- This option enables the workaround for the 753970 PL310 (r3p0) erratum.
+-
+- Under some condition the effect of cache sync operation on
+- the store buffer still remains when the operation completes.
+- This means that the store buffer is always asked to drain and
+- this prevents it from merging any further writes. The workaround
+- is to replace the normal offset of cache sync operation (0x730)
+- by another offset targeting an unmapped PL310 register 0x740.
+- This has the same effect as the cache sync operation: store buffer
+- drain and waiting for all buffers empty.
+-
+ config ARM_ERRATA_754322
+ bool "ARM errata: possible faulty MMU translations following an ASID switch"
+ depends on CPU_V7
+@@ -1350,18 +1308,6 @@
+ relevant cache maintenance functions and sets a specific bit
+ in the diagnostic control register of the SCU.
+
+-config PL310_ERRATA_769419
+- bool "PL310 errata: no automatic Store Buffer drain"
+- depends on CACHE_L2X0
+- help
+- On revisions of the PL310 prior to r3p2, the Store Buffer does
+- not automatically drain. This can cause normal, non-cacheable
+- writes to be retained when the memory system is idle, leading
+- to suboptimal I/O performance for drivers using coherent DMA.
+- This option adds a write barrier to the cpu_idle loop so that,
+- on systems with an outer cache, the store buffer is drained
+- explicitly.
+-
+ config ARM_ERRATA_775420
+ bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
+ depends on CPU_V7
+@@ -1835,6 +1781,7 @@
+ range 11 64 if ARCH_SHMOBILE_LEGACY
+ default "12" if SOC_AM33XX
+ default "9" if SA1111 || ARCH_EFM32
++ default "14" if ARCH_MXC
+ default "11"
+ help
+ The kernel memory allocator divides physically contiguous memory
+diff -Nur linux-3.14.72.orig/arch/arm/Kconfig.debug linux-3.14.72/arch/arm/Kconfig.debug
+--- linux-3.14.72.orig/arch/arm/Kconfig.debug 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/Kconfig.debug 2016-06-19 22:11:55.041157465 +0200
+@@ -321,6 +321,13 @@
+ Say Y here if you want kernel low-level debugging support
+ on i.MX6SL.
+
++ config DEBUG_IMX6SX_UART
++ bool "i.MX6SX Debug UART"
++ depends on SOC_IMX6SX
++ help
++ Say Y here if you want kernel low-level debugging support
++ on i.MX6SX.
++
+ config DEBUG_KEYSTONE_UART0
+ bool "Kernel low-level debugging on KEYSTONE2 using UART0"
+ depends on ARCH_KEYSTONE
+@@ -939,7 +946,8 @@
+ DEBUG_IMX51_UART || \
+ DEBUG_IMX53_UART || \
+ DEBUG_IMX6Q_UART || \
+- DEBUG_IMX6SL_UART
++ DEBUG_IMX6SL_UART || \
++ DEBUG_IMX6SX_UART
+ default 1
+ depends on ARCH_MXC
+ help
+@@ -974,7 +982,8 @@
+ DEBUG_IMX51_UART || \
+ DEBUG_IMX53_UART ||\
+ DEBUG_IMX6Q_UART || \
+- DEBUG_IMX6SL_UART
++ DEBUG_IMX6SL_UART || \
++ DEBUG_IMX6SX_UART
+ default "debug/msm.S" if DEBUG_MSM_UART
+ default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
+ default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
+diff -Nur linux-3.14.72.orig/arch/arm/kernel/machine_kexec.c linux-3.14.72/arch/arm/kernel/machine_kexec.c
+--- linux-3.14.72.orig/arch/arm/kernel/machine_kexec.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/kernel/machine_kexec.c 2016-06-19 22:11:55.041157465 +0200
+@@ -45,7 +45,8 @@
+ * and implements CPU hotplug for the current HW. If not, we won't be
+ * able to kexec reliably, so fail the prepare operation.
+ */
+- if (num_possible_cpus() > 1 && !platform_can_cpu_hotplug())
++ if (num_possible_cpus() > 1 && platform_can_secondary_boot() &&
++ !platform_can_cpu_hotplug())
+ return -EINVAL;
+
+ /*
+diff -Nur linux-3.14.72.orig/arch/arm/kernel/process.c linux-3.14.72/arch/arm/kernel/process.c
+--- linux-3.14.72.orig/arch/arm/kernel/process.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/kernel/process.c 2016-06-19 22:11:55.041157465 +0200
+@@ -149,6 +149,7 @@
+
+ void arch_cpu_idle_enter(void)
+ {
++ idle_notifier_call_chain(IDLE_START);
+ ledtrig_cpu(CPU_LED_IDLE_START);
+ #ifdef CONFIG_PL310_ERRATA_769419
+ wmb();
+@@ -158,6 +159,7 @@
+ void arch_cpu_idle_exit(void)
+ {
+ ledtrig_cpu(CPU_LED_IDLE_END);
++ idle_notifier_call_chain(IDLE_END);
+ }
+
+ #ifdef CONFIG_HOTPLUG_CPU
+diff -Nur linux-3.14.72.orig/arch/arm/kernel/setup.c linux-3.14.72/arch/arm/kernel/setup.c
+--- linux-3.14.72.orig/arch/arm/kernel/setup.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/kernel/setup.c 2016-06-19 22:11:55.041157465 +0200
+@@ -1089,3 +1089,12 @@
+ .stop = c_stop,
+ .show = c_show
+ };
++
++/* export the cache management functions */
++#ifndef MULTI_CACHE
++
++EXPORT_SYMBOL(__glue(_CACHE,_dma_map_area));
++EXPORT_SYMBOL(__glue(_CACHE,_dma_unmap_area));
++EXPORT_SYMBOL(__glue(_CACHE,_dma_flush_range));
++
++#endif
+diff -Nur linux-3.14.72.orig/arch/arm/kernel/smp.c linux-3.14.72/arch/arm/kernel/smp.c
+--- linux-3.14.72.orig/arch/arm/kernel/smp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/kernel/smp.c 2016-06-19 22:11:55.041157465 +0200
+@@ -146,6 +146,11 @@
+ return -ENOSYS;
+ }
+
++int platform_can_secondary_boot(void)
++{
++ return !!smp_ops.smp_boot_secondary;
++}
++
+ int platform_can_cpu_hotplug(void)
+ {
+ #ifdef CONFIG_HOTPLUG_CPU
+diff -Nur linux-3.14.72.orig/arch/arm/kernel/smp_scu.c linux-3.14.72/arch/arm/kernel/smp_scu.c
+--- linux-3.14.72.orig/arch/arm/kernel/smp_scu.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/kernel/smp_scu.c 2016-06-19 22:11:55.041157465 +0200
+@@ -17,6 +17,8 @@
+ #include <asm/cputype.h>
+
+ #define SCU_CTRL 0x00
++#define SCU_ENABLE (1 << 0)
++#define SCU_STANDBY_ENABLE (1 << 5)
+ #define SCU_CONFIG 0x04
+ #define SCU_CPU_STATUS 0x08
+ #define SCU_INVALIDATE 0x0c
+@@ -50,10 +52,16 @@
+
+ scu_ctrl = readl_relaxed(scu_base + SCU_CTRL);
+ /* already enabled? */
+- if (scu_ctrl & 1)
++ if (scu_ctrl & SCU_ENABLE)
+ return;
+
+- scu_ctrl |= 1;
++ scu_ctrl |= SCU_ENABLE;
++
++ /* Cortex-A9 earlier than r2p0 has no standby bit in SCU */
++ if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090 &&
++ (read_cpuid_id() & 0x00f0000f) >= 0x00200000)
++ scu_ctrl |= SCU_STANDBY_ENABLE;
++
+ writel_relaxed(scu_ctrl, scu_base + SCU_CTRL);
+
+ /*
+diff -Nur linux-3.14.72.orig/arch/arm/lib/bitops.h linux-3.14.72/arch/arm/lib/bitops.h
+--- linux-3.14.72.orig/arch/arm/lib/bitops.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/lib/bitops.h 2016-06-19 22:11:55.041157465 +0200
+@@ -37,6 +37,11 @@
+ add r1, r1, r0, lsl #2 @ Get word offset
+ mov r3, r2, lsl r3 @ create mask
+ smp_dmb
++#if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
++ .arch_extension mp
++ ALT_SMP(W(pldw) [r1])
++ ALT_UP(W(nop))
++#endif
+ 1: ldrex r2, [r1]
+ ands r0, r2, r3 @ save old value of bit
+ \instr r2, r2, r3 @ toggle bit
+diff -Nur linux-3.14.72.orig/arch/arm/mach-berlin/berlin.c linux-3.14.72/arch/arm/mach-berlin/berlin.c
+--- linux-3.14.72.orig/arch/arm/mach-berlin/berlin.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-berlin/berlin.c 2016-06-19 22:11:55.041157465 +0200
+@@ -24,7 +24,7 @@
+ * with DT probing for L2CCs, berlin_init_machine can be removed.
+ * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
+ */
+- l2x0_of_init(0x70c00000, 0xfeffffff);
++ l2x0_of_init(0x30c00000, 0xfeffffff);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-cns3xxx/core.c linux-3.14.72/arch/arm/mach-cns3xxx/core.c
+--- linux-3.14.72.orig/arch/arm/mach-cns3xxx/core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-cns3xxx/core.c 2016-06-19 22:11:55.041157465 +0200
+@@ -240,9 +240,9 @@
+ *
+ * 1 cycle of latency for setup, read and write accesses
+ */
+- val = readl(base + L2X0_TAG_LATENCY_CTRL);
++ val = readl(base + L310_TAG_LATENCY_CTRL);
+ val &= 0xfffff888;
+- writel(val, base + L2X0_TAG_LATENCY_CTRL);
++ writel(val, base + L310_TAG_LATENCY_CTRL);
+
+ /*
+ * Data RAM Control register
+@@ -253,12 +253,12 @@
+ *
+ * 1 cycle of latency for setup, read and write accesses
+ */
+- val = readl(base + L2X0_DATA_LATENCY_CTRL);
++ val = readl(base + L310_DATA_LATENCY_CTRL);
+ val &= 0xfffff888;
+- writel(val, base + L2X0_DATA_LATENCY_CTRL);
++ writel(val, base + L310_DATA_LATENCY_CTRL);
+
+ /* 32 KiB, 8-way, parity disable */
+- l2x0_init(base, 0x00540000, 0xfe000fff);
++ l2x0_init(base, 0x00500000, 0xfe0f0fff);
+ }
+
+ #endif /* CONFIG_CACHE_L2X0 */
+diff -Nur linux-3.14.72.orig/arch/arm/mach-exynos/common.c linux-3.14.72/arch/arm/mach-exynos/common.c
+--- linux-3.14.72.orig/arch/arm/mach-exynos/common.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-exynos/common.c 2016-06-19 22:11:55.041157465 +0200
+@@ -45,9 +45,6 @@
+ #include "common.h"
+ #include "regs-pmu.h"
+
+-#define L2_AUX_VAL 0x7C470001
+-#define L2_AUX_MASK 0xC200ffff
+-
+ static const char name_exynos4210[] = "EXYNOS4210";
+ static const char name_exynos4212[] = "EXYNOS4212";
+ static const char name_exynos4412[] = "EXYNOS4412";
+@@ -400,7 +397,7 @@
+ {
+ int ret;
+
+- ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
++ ret = l2x0_of_init(0x3c400001, 0xc20fffff);
+ if (ret)
+ return ret;
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-highbank/highbank.c linux-3.14.72/arch/arm/mach-highbank/highbank.c
+--- linux-3.14.72.orig/arch/arm/mach-highbank/highbank.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-highbank/highbank.c 2016-06-19 22:11:55.041157465 +0200
+@@ -51,11 +51,13 @@
+ }
+
+
+-static void highbank_l2x0_disable(void)
++static void highbank_l2c310_write_sec(unsigned long val, unsigned reg)
+ {
+- outer_flush_all();
+- /* Disable PL310 L2 Cache controller */
+- highbank_smc1(0x102, 0x0);
++ if (reg == L2X0_CTRL)
++ highbank_smc1(0x102, val);
++ else
++ WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n",
++ reg);
+ }
+
+ static void __init highbank_init_irq(void)
+@@ -66,11 +68,9 @@
+ highbank_scu_map_io();
+
+ /* Enable PL310 L2 Cache controller */
+- if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
+- of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
+- highbank_smc1(0x102, 0x1);
+- l2x0_of_init(0, ~0UL);
+- outer_cache.disable = highbank_l2x0_disable;
++ if (IS_ENABLED(CONFIG_CACHE_L2X0)) {
++ outer_cache.write_sec = highbank_l2c310_write_sec;
++ l2x0_of_init(0, ~0);
+ }
+ }
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/anatop.c linux-3.14.72/arch/arm/mach-imx/anatop.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/anatop.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/anatop.c 2016-06-19 22:11:55.041157465 +0200
+@@ -30,8 +30,11 @@
+ #define ANADIG_DIGPROG_IMX6SL 0x280
+
+ #define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x40000
++#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x8
+ #define BM_ANADIG_REG_CORE_FET_ODRIVE 0x20000000
+ #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
++/* Below MISC0_DISCON_HIGH_SNVS is only for i.MX6SL */
++#define BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS 0x2000
+ #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x80000
+ #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x100000
+
+@@ -56,16 +59,43 @@
+ BM_ANADIG_REG_CORE_FET_ODRIVE);
+ }
+
++static inline void imx_anatop_enable_2p5_pulldown(bool enable)
++{
++ regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR),
++ BM_ANADIG_REG_2P5_ENABLE_PULLDOWN);
++}
++
++static inline void imx_anatop_disconnect_high_snvs(bool enable)
++{
++ regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR),
++ BM_ANADIG_ANA_MISC0_DISCON_HIGH_SNVS);
++}
++
+ void imx_anatop_pre_suspend(void)
+ {
+- imx_anatop_enable_weak2p5(true);
++ if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
++ imx_anatop_enable_2p5_pulldown(true);
++ else
++ imx_anatop_enable_weak2p5(true);
++
+ imx_anatop_enable_fet_odrive(true);
++
++ if (cpu_is_imx6sl())
++ imx_anatop_disconnect_high_snvs(true);
+ }
+
+ void imx_anatop_post_resume(void)
+ {
++ if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
++ imx_anatop_enable_2p5_pulldown(false);
++ else
++ imx_anatop_enable_weak2p5(false);
++
+ imx_anatop_enable_fet_odrive(false);
+- imx_anatop_enable_weak2p5(false);
++
++ if (cpu_is_imx6sl())
++ imx_anatop_disconnect_high_snvs(false);
++
+ }
+
+ static void imx_anatop_usb_chrg_detect_disable(void)
+@@ -104,6 +134,19 @@
+ case 2:
+ revision = IMX_CHIP_REVISION_1_2;
+ break;
++ case 3:
++ revision = IMX_CHIP_REVISION_1_3;
++ break;
++ case 4:
++ revision = IMX_CHIP_REVISION_1_4;
++ break;
++ case 5:
++ /*
++ * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked
++ * as 'D' in Part Number last character.
++ */
++ revision = IMX_CHIP_REVISION_1_5;
++ break;
+ default:
+ revision = IMX_CHIP_REVISION_UNKNOWN;
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/busfreq_ddr3.c linux-3.14.72/arch/arm/mach-imx/busfreq_ddr3.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/busfreq_ddr3.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/busfreq_ddr3.c 2016-06-19 22:11:55.045157162 +0200
+@@ -0,0 +1,656 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file busfreq_ddr3.c
++ *
++ * @brief iMX6 DDR3 frequency change specific file.
++ *
++ * @ingroup PM
++ */
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/clk.h>
++#include <linux/clockchips.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/sched.h>
++#include <linux/smp.h>
++
++#include "hardware.h"
++
++
++/*
++ * This structure is for passing necessary data for low level ocram
++ * busfreq code(arch/arm/mach-imx/ddr3_freq_imx6.S), if this struct
++ * definition is changed, the offset definition in
++ * arch/arm/mach-imx/ddr3_freq_imx6.S must be also changed accordingly,
++ * otherwise, the busfreq change function will be broken!
++ *
++ * This structure will be placed in front of the asm code on ocram.
++ */
++struct imx6_busfreq_info {
++ u32 freq;
++ void *ddr_settings;
++ u32 dll_off;
++ void *iomux_offsets;
++ u32 mu_delay_val;
++} __aligned(8);
++
++static struct imx6_busfreq_info *imx6sx_busfreq_info;
++
++/* DDR settings */
++static unsigned long (*iram_ddr_settings)[2];
++static unsigned long (*normal_mmdc_settings)[2];
++static unsigned long (*iram_iomux_settings)[2];
++
++static void __iomem *mmdc_base;
++static void __iomem *iomux_base;
++static void __iomem *gic_dist_base;
++
++static int ddr_settings_size;
++static int iomux_settings_size;
++static int curr_ddr_rate;
++
++void (*imx6sx_change_ddr_freq)(struct imx6_busfreq_info *busfreq_info);
++extern void imx6sx_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info);
++
++void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings,
++ bool dll_mode, void *iomux_offsets) = NULL;
++
++extern unsigned int ddr_med_rate;
++extern unsigned int ddr_normal_rate;
++extern int low_bus_freq_mode;
++extern int audio_bus_freq_mode;
++extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings,
++ bool dll_mode, void *iomux_offsets);
++
++extern unsigned long save_ttbr1(void);
++extern void restore_ttbr1(unsigned long ttbr1);
++extern unsigned long ddr_freq_change_iram_base;
++
++extern unsigned long ddr_freq_change_total_size;
++extern unsigned long iram_tlb_phys_addr;
++
++extern unsigned long mx6_ddr3_freq_change_start asm("mx6_ddr3_freq_change_start");
++extern unsigned long mx6_ddr3_freq_change_end asm("mx6_ddr3_freq_change_end");
++extern unsigned long imx6sx_ddr3_freq_change_start asm("imx6sx_ddr3_freq_change_start");
++extern unsigned long imx6sx_ddr3_freq_change_end asm("imx6sx_ddr3_freq_change_end");
++#ifdef CONFIG_SMP
++#ifdef CONFIG_SOC_IMX6Q
++static unsigned long wfe_freq_change_iram_base;
++#endif
++u32 *wait_for_ddr_freq_update;
++static unsigned int online_cpus;
++static u32 *irqs_used;
++
++void (*wfe_change_ddr_freq)(u32 cpuid, u32 *ddr_freq_change_done);
++extern void wfe_ddr3_freq_change(u32 cpuid, u32 *ddr_freq_change_done);
++extern unsigned long wfe_ddr3_freq_change_start asm("wfe_ddr3_freq_change_start");
++extern unsigned long wfe_ddr3_freq_change_end asm("wfe_ddr3_freq_change_end");
++extern void __iomem *imx_scu_base;
++#endif
++
++#define MIN_DLL_ON_FREQ 333000000
++#define MAX_DLL_OFF_FREQ 125000000
++#define MMDC0_MPMUR0 0x8b8
++#define MMDC0_MPMUR0_OFFSET 16
++#define MMDC0_MPMUR0_MASK 0x3ff
++
++unsigned long ddr3_dll_mx6sx[][2] = {
++ {0x0c, 0x0},
++ {0x10, 0x0},
++ {0x1C, 0x04008032},
++ {0x1C, 0x00048031},
++ {0x1C, 0x05208030},
++ {0x1C, 0x04008040},
++ {0x818, 0x0},
++};
++
++unsigned long ddr3_calibration_mx6sx[][2] = {
++ {0x83c, 0x0},
++ {0x840, 0x0},
++ {0x848, 0x0},
++ {0x850, 0x0},
++};
++
++unsigned long iomux_offsets_mx6sx[][2] = {
++ {0x330, 0x0},
++ {0x334, 0x0},
++ {0x338, 0x0},
++ {0x33c, 0x0},
++};
++
++unsigned long ddr3_dll_mx6q[][2] = {
++ {0x0c, 0x0},
++ {0x10, 0x0},
++ {0x1C, 0x04088032},
++ {0x1C, 0x0408803a},
++ {0x1C, 0x08408030},
++ {0x1C, 0x08408038},
++ {0x818, 0x0},
++};
++
++unsigned long ddr3_calibration[][2] = {
++ {0x83c, 0x0},
++ {0x840, 0x0},
++ {0x483c, 0x0},
++ {0x4840, 0x0},
++ {0x848, 0x0},
++ {0x4848, 0x0},
++ {0x850, 0x0},
++ {0x4850, 0x0},
++};
++
++unsigned long ddr3_dll_mx6dl[][2] = {
++ {0x0c, 0x0},
++ {0x10, 0x0},
++ {0x1C, 0x04008032},
++ {0x1C, 0x0400803a},
++ {0x1C, 0x07208030},
++ {0x1C, 0x07208038},
++ {0x818, 0x0},
++};
++
++unsigned long iomux_offsets_mx6q[][2] = {
++ {0x5A8, 0x0},
++ {0x5B0, 0x0},
++ {0x524, 0x0},
++ {0x51C, 0x0},
++ {0x518, 0x0},
++ {0x50C, 0x0},
++ {0x5B8, 0x0},
++ {0x5C0, 0x0},
++};
++
++unsigned long iomux_offsets_mx6dl[][2] = {
++ {0x4BC, 0x0},
++ {0x4C0, 0x0},
++ {0x4C4, 0x0},
++ {0x4C8, 0x0},
++ {0x4CC, 0x0},
++ {0x4D0, 0x0},
++ {0x4D4, 0x0},
++ {0x4D8, 0x0},
++};
++
++unsigned long ddr3_400[][2] = {
++ {0x83c, 0x42490249},
++ {0x840, 0x02470247},
++ {0x483c, 0x42570257},
++ {0x4840, 0x02400240},
++ {0x848, 0x4039363C},
++ {0x4848, 0x3A39333F},
++ {0x850, 0x38414441},
++ {0x4850, 0x472D4833}
++};
++
++int can_change_ddr_freq(void)
++{
++ return 1;
++}
++
++#ifdef CONFIG_SMP
++/*
++ * each active core apart from the one changing
++ * the DDR frequency will execute this function.
++ * the rest of the cores have to remain in WFE
++ * state until the frequency is changed.
++ */
++irqreturn_t wait_in_wfe_irq(int irq, void *dev_id)
++{
++ u32 me;
++
++ me = smp_processor_id();
++#ifdef CONFIG_LOCAL_TIMERS
++ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER,
++ &me);
++#endif
++ wfe_change_ddr_freq(0xff << (me * 8), (u32 *)&iram_iomux_settings[0][1]);
++
++#ifdef CONFIG_LOCAL_TIMERS
++ clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT,
++ &me);
++#endif
++
++ return IRQ_HANDLED;
++}
++#endif
++
++int update_ddr_freq_imx6sx(int ddr_rate)
++{
++ int i;
++ bool dll_off = false;
++ unsigned long ttbr1;
++
++ if (ddr_rate == curr_ddr_rate)
++ return 0;
++
++ pr_debug("Bus freq set to %d start...\n", ddr_rate);
++
++ if (low_bus_freq_mode || audio_bus_freq_mode)
++ dll_off = true;
++
++ imx6sx_busfreq_info->dll_off = dll_off;
++ iram_ddr_settings[0][0] = ddr_settings_size;
++ iram_iomux_settings[0][0] = iomux_settings_size;
++ for (i = 0; i < iram_ddr_settings[0][0]; i++) {
++ iram_ddr_settings[i + 1][0] =
++ normal_mmdc_settings[i][0];
++ iram_ddr_settings[i + 1][1] =
++ normal_mmdc_settings[i][1];
++ }
++
++ local_irq_disable();
++
++ ttbr1 = save_ttbr1();
++ imx6sx_busfreq_info->freq = ddr_rate;
++ imx6sx_busfreq_info->ddr_settings = iram_ddr_settings;
++ imx6sx_busfreq_info->iomux_offsets = iram_iomux_settings;
++ imx6sx_busfreq_info->mu_delay_val = ((readl_relaxed(mmdc_base + MMDC0_MPMUR0)
++ >> MMDC0_MPMUR0_OFFSET) & MMDC0_MPMUR0_MASK);
++
++ imx6sx_change_ddr_freq(imx6sx_busfreq_info);
++ restore_ttbr1(ttbr1);
++ curr_ddr_rate = ddr_rate;
++
++ local_irq_enable();
++
++ pr_debug("Bus freq set to %d done!\n", ddr_rate);
++
++ return 0;
++}
++
++/* change the DDR frequency. */
++int update_ddr_freq_imx6q(int ddr_rate)
++{
++ int i, j;
++ bool dll_off = false;
++ int me = 0;
++ unsigned long ttbr1;
++#ifdef CONFIG_SMP
++ unsigned int reg;
++ int cpu = 0;
++#endif
++
++ if (!can_change_ddr_freq())
++ return -1;
++
++ if (ddr_rate == curr_ddr_rate)
++ return 0;
++
++ pr_debug("Bus freq set to %d start...\n", ddr_rate);
++
++ if (low_bus_freq_mode || audio_bus_freq_mode)
++ dll_off = true;
++
++ iram_ddr_settings[0][0] = ddr_settings_size;
++ iram_iomux_settings[0][0] = iomux_settings_size;
++ if (ddr_rate == ddr_med_rate && cpu_is_imx6q()) {
++ for (i = 0; i < ARRAY_SIZE(ddr3_dll_mx6q); i++) {
++ iram_ddr_settings[i + 1][0] =
++ normal_mmdc_settings[i][0];
++ iram_ddr_settings[i + 1][1] =
++ normal_mmdc_settings[i][1];
++ }
++ for (j = 0, i = ARRAY_SIZE(ddr3_dll_mx6q);
++ i < iram_ddr_settings[0][0]; j++, i++) {
++ iram_ddr_settings[i + 1][0] =
++ ddr3_400[j][0];
++ iram_ddr_settings[i + 1][1] =
++ ddr3_400[j][1];
++ }
++ } else if (ddr_rate == ddr_normal_rate) {
++ for (i = 0; i < iram_ddr_settings[0][0]; i++) {
++ iram_ddr_settings[i + 1][0] =
++ normal_mmdc_settings[i][0];
++ iram_ddr_settings[i + 1][1] =
++ normal_mmdc_settings[i][1];
++ }
++ }
++
++ /* ensure that all Cores are in WFE. */
++ local_irq_disable();
++
++#ifdef CONFIG_SMP
++ me = smp_processor_id();
++
++ /* Make sure all the online cores are active */
++ while (1) {
++ bool not_exited_busfreq = false;
++ for_each_online_cpu(cpu) {
++ u32 reg = __raw_readl(imx_scu_base + 0x08);
++ if (reg & (0x02 << (cpu * 8)))
++ not_exited_busfreq = true;
++ }
++ if (!not_exited_busfreq)
++ break;
++ }
++
++ wmb();
++ *wait_for_ddr_freq_update = 1;
++ dsb();
++
++ online_cpus = readl_relaxed(imx_scu_base + 0x08);
++ for_each_online_cpu(cpu) {
++ *((char *)(&online_cpus) + (u8)cpu) = 0x02;
++ if (cpu != me) {
++ /* set the interrupt to be pending in the GIC. */
++ reg = 1 << (irqs_used[cpu] % 32);
++ writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET
++ + (irqs_used[cpu] / 32) * 4);
++ }
++ }
++ /* Wait for the other active CPUs to idle */
++ while (1) {
++ u32 reg = readl_relaxed(imx_scu_base + 0x08);
++ reg |= (0x02 << (me * 8));
++ if (reg == online_cpus)
++ break;
++ }
++#endif
++
++ /* Ensure iram_tlb_phys_addr is flushed to DDR. */
++ __cpuc_flush_dcache_area(&iram_tlb_phys_addr, sizeof(iram_tlb_phys_addr));
++ outer_clean_range(virt_to_phys(&iram_tlb_phys_addr), virt_to_phys(&iram_tlb_phys_addr + 1));
++
++ ttbr1 = save_ttbr1();
++ /* Now we can change the DDR frequency. */
++ mx6_change_ddr_freq(ddr_rate, iram_ddr_settings,
++ dll_off, iram_iomux_settings);
++ restore_ttbr1(ttbr1);
++ curr_ddr_rate = ddr_rate;
++
++#ifdef CONFIG_SMP
++ wmb();
++ /* DDR frequency change is done . */
++ *wait_for_ddr_freq_update = 0;
++ dsb();
++
++ /* wake up all the cores. */
++ sev();
++#endif
++
++ local_irq_enable();
++
++ pr_debug("Bus freq set to %d done! cpu=%d\n", ddr_rate, me);
++
++ return 0;
++}
++
++#ifdef CONFIG_SOC_IMX6SX
++int init_mmdc_ddr3_settings_imx6sx(struct platform_device *busfreq_pdev)
++{
++ int i;
++ struct device_node *node;
++ unsigned long ddr_code_size;
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc");
++ if (!node) {
++ printk(KERN_ERR "failed to find mmdc device tree data!\n");
++ return -EINVAL;
++ }
++ mmdc_base = of_iomap(node, 0);
++ WARN(!mmdc_base, "unable to map mmdc registers\n");
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-iomuxc");
++ if (!node) {
++ printk(KERN_ERR "failed to find iomuxc device tree data!\n");
++ return -EINVAL;
++ }
++ iomux_base = of_iomap(node, 0);
++ WARN(!iomux_base, "unable to map iomux registers\n");
++
++ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6sx) +
++ ARRAY_SIZE(ddr3_calibration_mx6sx);
++
++ normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL);
++ memcpy(normal_mmdc_settings, ddr3_dll_mx6sx,
++ sizeof(ddr3_dll_mx6sx));
++ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6sx)),
++ ddr3_calibration_mx6sx, sizeof(ddr3_calibration_mx6sx));
++
++ /* store the original DDR settings at boot. */
++ for (i = 0; i < ddr_settings_size; i++) {
++ /*
++ * writes via command mode register cannot be read back.
++ * hence hardcode them in the initial static array.
++ * this may require modification on a per customer basis.
++ */
++ if (normal_mmdc_settings[i][0] != 0x1C)
++ normal_mmdc_settings[i][1] =
++ readl_relaxed(mmdc_base
++ + normal_mmdc_settings[i][0]);
++ }
++
++ iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6sx);
++
++ ddr_code_size = (&imx6sx_ddr3_freq_change_end -&imx6sx_ddr3_freq_change_start) *4 +
++ sizeof(*imx6sx_busfreq_info);
++
++ imx6sx_busfreq_info = (struct imx6_busfreq_info *)ddr_freq_change_iram_base;
++
++ imx6sx_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + sizeof(*imx6sx_busfreq_info),
++ &imx6sx_ddr3_freq_change, ddr_code_size - sizeof(*imx6sx_busfreq_info));
++
++ /*
++ * Store the size of the array in iRAM also,
++ * increase the size by 8 bytes.
++ */
++ iram_iomux_settings = (void *)(ddr_freq_change_iram_base + ddr_code_size);
++ iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8;
++
++ if ((ddr_code_size + (iomux_settings_size + ddr_settings_size) * 8 + 16)
++ > ddr_freq_change_total_size) {
++ printk(KERN_ERR "Not enough memory allocated for DDR Frequency change code.\n");
++ return EINVAL;
++ }
++
++ for (i = 0; i < iomux_settings_size; i++) {
++ iomux_offsets_mx6sx[i][1] =
++ readl_relaxed(iomux_base +
++ iomux_offsets_mx6sx[i][0]);
++ iram_iomux_settings[i + 1][0] =
++ iomux_offsets_mx6sx[i][0];
++ iram_iomux_settings[i + 1][1] =
++ iomux_offsets_mx6sx[i][1];
++ }
++
++ curr_ddr_rate = ddr_normal_rate;
++
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_SOC_IMX6Q
++int init_mmdc_ddr3_settings_imx6q(struct platform_device *busfreq_pdev)
++{
++ int i;
++ struct device_node *node;
++ unsigned long ddr_code_size;
++ unsigned long wfe_code_size = 0;
++#ifdef CONFIG_SMP
++ u32 cpu;
++ struct device *dev = &busfreq_pdev->dev;
++ int err;
++#endif
++
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-mmdc device tree data!\n");
++ return -EINVAL;
++ }
++ mmdc_base = of_iomap(node, 0);
++ WARN(!mmdc_base, "unable to map mmdc registers\n");
++
++ node = NULL;
++ if (cpu_is_imx6q())
++ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc");
++ if (cpu_is_imx6dl())
++ node = of_find_compatible_node(NULL, NULL,
++ "fsl,imx6dl-iomuxc");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-iomux device tree data!\n");
++ return -EINVAL;
++ }
++ iomux_base = of_iomap(node, 0);
++ WARN(!iomux_base, "unable to map iomux registers\n");
++
++ node = NULL;
++ node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
++ if (!node) {
++ printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n");
++ return -EINVAL;
++ }
++ gic_dist_base = of_iomap(node, 0);
++ WARN(!gic_dist_base, "unable to map gic dist registers\n");
++
++ if (cpu_is_imx6q())
++ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) +
++ ARRAY_SIZE(ddr3_calibration);
++ if (cpu_is_imx6dl())
++ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) +
++ ARRAY_SIZE(ddr3_calibration);
++
++ normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL);
++ if (cpu_is_imx6q()) {
++ memcpy(normal_mmdc_settings, ddr3_dll_mx6q,
++ sizeof(ddr3_dll_mx6q));
++ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)),
++ ddr3_calibration, sizeof(ddr3_calibration));
++ }
++ if (cpu_is_imx6dl()) {
++ memcpy(normal_mmdc_settings, ddr3_dll_mx6dl,
++ sizeof(ddr3_dll_mx6dl));
++ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)),
++ ddr3_calibration, sizeof(ddr3_calibration));
++ }
++ /* store the original DDR settings at boot. */
++ for (i = 0; i < ddr_settings_size; i++) {
++ /*
++ * writes via command mode register cannot be read back.
++ * hence hardcode them in the initial static array.
++ * this may require modification on a per customer basis.
++ */
++ if (normal_mmdc_settings[i][0] != 0x1C)
++ normal_mmdc_settings[i][1] =
++ readl_relaxed(mmdc_base
++ + normal_mmdc_settings[i][0]);
++ }
++
++#ifdef CONFIG_SMP
++ irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(),
++ GFP_KERNEL);
++
++ for_each_online_cpu(cpu) {
++ int irq;
++
++ /*
++ * set up a reserved interrupt to get all
++ * the active cores into a WFE state
++ * before changing the DDR frequency.
++ */
++ irq = platform_get_irq(busfreq_pdev, cpu);
++ err = request_irq(irq, wait_in_wfe_irq,
++ IRQF_PERCPU, "mmdc_1", NULL);
++ if (err) {
++ dev_err(dev,
++ "Busfreq:request_irq failed %d, err = %d\n",
++ irq, err);
++ return err;
++ }
++ err = irq_set_affinity(irq, cpumask_of(cpu));
++ if (err) {
++ dev_err(dev,
++ "Busfreq: Cannot set irq affinity irq=%d,\n",
++ irq);
++ return err;
++ }
++ irqs_used[cpu] = irq;
++ }
++#endif
++ iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q);
++
++ ddr_code_size = (&mx6_ddr3_freq_change_end -&mx6_ddr3_freq_change_start) *4;
++
++ mx6_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base,
++ &mx6_ddr3_freq_change, ddr_code_size);
++
++ /*
++ * Store the size of the array in iRAM also,
++ * increase the size by 8 bytes.
++ */
++ iram_iomux_settings = (void *)(ddr_freq_change_iram_base + ddr_code_size);
++ iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8;
++
++#ifdef CONFIG_SMP
++ wfe_freq_change_iram_base = (unsigned long)((u32 *)iram_ddr_settings + (ddr_settings_size * 8) + 8);
++
++ if (wfe_freq_change_iram_base & (FNCPY_ALIGN - 1))
++ wfe_freq_change_iram_base += FNCPY_ALIGN - ((uintptr_t)wfe_freq_change_iram_base % (FNCPY_ALIGN));
++
++ wfe_code_size = (&wfe_ddr3_freq_change_end -&wfe_ddr3_freq_change_start) *4;
++
++ wfe_change_ddr_freq = (void *)fncpy((void *)wfe_freq_change_iram_base,
++ &wfe_ddr3_freq_change, wfe_code_size);
++
++ /* Store the variable used to communicate between cores in a non-cacheable IRAM area */
++ wait_for_ddr_freq_update = (u32 *)&iram_iomux_settings[0][1];
++#endif
++
++ if ((ddr_code_size + wfe_code_size + (iomux_settings_size + ddr_settings_size) * 8 + 16)
++ > ddr_freq_change_total_size) {
++ printk(KERN_ERR "Not enough memory allocated for DDR Frequency change code.\n");
++ return EINVAL;
++ }
++
++ if (cpu_is_imx6q()) {
++ /* store the IOMUX settings at boot. */
++ for (i = 0; i < iomux_settings_size; i++) {
++ iomux_offsets_mx6q[i][1] =
++ readl_relaxed(iomux_base +
++ iomux_offsets_mx6q[i][0]);
++ iram_iomux_settings[i+1][0] = iomux_offsets_mx6q[i][0];
++ iram_iomux_settings[i+1][1] = iomux_offsets_mx6q[i][1];
++ }
++ }
++
++ if (cpu_is_imx6dl()) {
++ for (i = 0; i < iomux_settings_size; i++) {
++ iomux_offsets_mx6dl[i][1] =
++ readl_relaxed(iomux_base +
++ iomux_offsets_mx6dl[i][0]);
++ iram_iomux_settings[i+1][0] = iomux_offsets_mx6dl[i][0];
++ iram_iomux_settings[i+1][1] = iomux_offsets_mx6dl[i][1];
++ }
++ }
++
++ curr_ddr_rate = ddr_normal_rate;
++
++ return 0;
++}
++#endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/busfreq-imx6.c linux-3.14.72/arch/arm/mach-imx/busfreq-imx6.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/busfreq-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/busfreq-imx6.c 2016-06-19 22:11:55.045157162 +0200
+@@ -0,0 +1,1268 @@
++/*
++ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file busfreq-imx6.c
++ *
++ * @brief A common API for the Freescale Semiconductor iMX6 Busfreq API
++ *
++ * The APIs are for setting bus frequency to different values based on the
++ * highest freqeuncy requested.
++ *
++ * @ingroup PM
++ */
++
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/reboot.h>
++#include <linux/regulator/consumer.h>
++#include <linux/sched.h>
++#include <linux/suspend.h>
++#include "clk.h"
++#include "hardware.h"
++#include "common.h"
++
++#define LPAPM_CLK 24000000
++#define DDR3_AUDIO_CLK 50000000
++#define LPDDR2_AUDIO_CLK 100000000
++
++#define MMDC_MDMISC_DDR_TYPE_DDR3 0
++#define MMDC_MDMISC_DDR_TYPE_LPDDR2 1
++
++#ifdef CONFIG_SOC_IMX6SX
++static int ddr_type;
++#endif
++int high_bus_freq_mode;
++int med_bus_freq_mode;
++int audio_bus_freq_mode;
++int low_bus_freq_mode;
++int ultra_low_bus_freq_mode;
++unsigned int ddr_med_rate;
++unsigned int ddr_normal_rate;
++unsigned long ddr_freq_change_total_size;
++unsigned long ddr_freq_change_iram_base;
++unsigned long ddr_freq_change_iram_phys;
++
++static int bus_freq_scaling_initialized;
++static struct device *busfreq_dev;
++static int busfreq_suspended;
++#ifdef CONFIG_SOC_IMX6SL
++static u32 org_arm_rate;
++#endif
++static int bus_freq_scaling_is_active;
++static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count;
++static unsigned int ddr_low_rate;
++
++extern unsigned long iram_tlb_phys_addr;
++extern int unsigned long iram_tlb_base_addr;
++
++extern int init_mmdc_lpddr2_settings(struct platform_device *dev);
++extern int init_mmdc_ddr3_settings_imx6q(struct platform_device *dev);
++extern int init_mmdc_ddr3_settings_imx6sx(struct platform_device *dev);
++extern int update_ddr_freq_imx6q(int ddr_rate);
++extern int update_ddr_freq_imx6sx(int ddr_rate);
++extern int update_lpddr2_freq(int ddr_rate);
++
++DEFINE_MUTEX(bus_freq_mutex);
++
++static struct clk *mmdc_clk;
++static struct clk *pll2_400;
++static struct clk *periph_clk;
++static struct clk *periph_pre_clk;
++static struct clk *periph_clk2_sel;
++static struct clk *periph_clk2;
++static struct clk *osc_clk;
++static struct clk *cpu_clk;
++static struct clk *pll3;
++static struct clk *pll2;
++static struct clk *pll2_bus;
++static struct clk *pll2_bypass_src;
++static struct clk *pll2_bypass;
++static struct clk *pll2_200;
++static struct clk *pll1_sys;
++static struct clk *periph2_clk;
++static struct clk *ocram_clk;
++static struct clk *ahb_clk;
++static struct clk *pll1_sw_clk;
++static struct clk *periph2_pre_clk;
++static struct clk *periph2_clk2_sel;
++static struct clk *periph2_clk2;
++static struct clk *step_clk;
++static struct clk *axi_alt_sel_clk;
++static struct clk *axi_sel_clk;
++static struct clk *pll3_pfd1_540m;
++static struct clk *m4_clk;
++static struct clk *pll1;
++static struct clk *pll1_bypass;
++static struct clk *pll1_bypass_src;
++
++#ifdef CONFIG_SOC_IMX6SL
++static u32 pll2_org_rate;
++#endif
++static struct delayed_work low_bus_freq_handler;
++static struct delayed_work bus_freq_daemon;
++
++static RAW_NOTIFIER_HEAD(busfreq_notifier_chain);
++
++static int busfreq_notify(enum busfreq_event event)
++{
++ int ret;
++
++ ret = raw_notifier_call_chain(&busfreq_notifier_chain, event, NULL);
++
++ return notifier_to_errno(ret);
++}
++
++int register_busfreq_notifier(struct notifier_block *nb)
++{
++ return raw_notifier_chain_register(&busfreq_notifier_chain, nb);
++}
++EXPORT_SYMBOL(register_busfreq_notifier);
++
++int unregister_busfreq_notifier(struct notifier_block *nb)
++{
++ return raw_notifier_chain_unregister(&busfreq_notifier_chain, nb);
++}
++EXPORT_SYMBOL(unregister_busfreq_notifier);
++
++#ifdef CONFIG_SOC_IMX6SX
++static bool check_m4_sleep(void)
++{
++ unsigned long timeout = jiffies + msecs_to_jiffies(500);
++
++ while (imx_gpc_is_m4_sleeping() == 0)
++ if (time_after(jiffies, timeout))
++ return false;
++ return true;
++}
++
++static void enter_lpm_imx6sx(void)
++{
++ if (imx_src_is_m4_enabled())
++ if (!check_m4_sleep())
++ pr_err("M4 is NOT in sleep!!!\n");
++
++ /* set periph_clk2 to source from OSC for periph */
++ imx_clk_set_parent(periph_clk2_sel, osc_clk);
++ imx_clk_set_parent(periph_clk, periph_clk2);
++ /* set ahb/ocram to 24MHz */
++ imx_clk_set_rate(ahb_clk, LPAPM_CLK);
++ imx_clk_set_rate(ocram_clk, LPAPM_CLK);
++
++ if (audio_bus_count) {
++ /* Need to ensure that PLL2_PFD_400M is kept ON. */
++ clk_prepare_enable(pll2_400);
++ if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
++ update_ddr_freq_imx6sx(DDR3_AUDIO_CLK);
++ else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
++ update_lpddr2_freq(LPDDR2_AUDIO_CLK);
++ imx_clk_set_parent(periph2_clk2_sel, pll3);
++ imx_clk_set_parent(periph2_pre_clk, pll2_400);
++ imx_clk_set_parent(periph2_clk, periph2_pre_clk);
++ /*
++ * As periph2_clk's parent is not changed from
++ * high mode to audio mode, so clk framework
++ * will not update its children's freq, but we
++ * change the mmdc's podf in asm code, so here
++ * need to update mmdc rate to make sure clk
++ * tree is right, although it will not do any
++ * change to hardware.
++ */
++ if (high_bus_freq_mode) {
++ if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
++ imx_clk_set_rate(mmdc_clk, DDR3_AUDIO_CLK);
++ else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
++ imx_clk_set_rate(mmdc_clk, LPDDR2_AUDIO_CLK);
++ }
++ audio_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ } else {
++ if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
++ update_ddr_freq_imx6sx(LPAPM_CLK);
++ else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
++ update_lpddr2_freq(LPAPM_CLK);
++ imx_clk_set_parent(periph2_clk2_sel, osc_clk);
++ imx_clk_set_parent(periph2_clk, periph2_clk2);
++
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++ low_bus_freq_mode = 1;
++ audio_bus_freq_mode = 0;
++ }
++}
++
++static void exit_lpm_imx6sx(void)
++{
++ clk_prepare_enable(pll2_400);
++
++ /*
++ * lower ahb/ocram's freq first to avoid too high
++ * freq during parent switch from OSC to pll3.
++ */
++ imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3);
++ imx_clk_set_rate(ocram_clk, LPAPM_CLK / 2);
++ /* set periph_clk2 to pll3 */
++ imx_clk_set_parent(periph_clk2_sel, pll3);
++ /* set periph clk to from pll2_400 */
++ imx_clk_set_parent(periph_pre_clk, pll2_400);
++ imx_clk_set_parent(periph_clk, periph_pre_clk);
++
++ if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
++ update_ddr_freq_imx6sx(ddr_normal_rate);
++ else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
++ update_lpddr2_freq(ddr_normal_rate);
++ /* correct parent info after ddr freq change in asm code */
++ imx_clk_set_parent(periph2_pre_clk, pll2_400);
++ imx_clk_set_parent(periph2_clk, periph2_pre_clk);
++ imx_clk_set_parent(periph2_clk2_sel, pll3);
++
++ /*
++ * As periph2_clk's parent is not changed from
++ * audio mode to high mode, so clk framework
++ * will not update its children's freq, but we
++ * change the mmdc's podf in asm code, so here
++ * need to update mmdc rate to make sure clk
++ * tree is right, although it will not do any
++ * change to hardware.
++ */
++ if (audio_bus_freq_mode)
++ imx_clk_set_rate(mmdc_clk, ddr_normal_rate);
++
++ clk_disable_unprepare(pll2_400);
++
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++}
++#endif
++
++#ifdef CONFIG_SOC_IMX6SL
++static void enter_lpm_imx6sl(void)
++{
++ if (high_bus_freq_mode) {
++ pll2_org_rate = clk_get_rate(pll2_bus);
++ /* Set periph_clk to be sourced from OSC_CLK */
++ imx_clk_set_parent(periph_clk2_sel, osc_clk);
++ imx_clk_set_parent(periph_clk, periph_clk2);
++ /* Ensure AHB/AXI clks are at 24MHz. */
++ imx_clk_set_rate(ahb_clk, LPAPM_CLK);
++ imx_clk_set_rate(ocram_clk, LPAPM_CLK);
++ }
++ if (audio_bus_count) {
++ /* Set AHB to 8MHz to lower pwer.*/
++ imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3);
++
++ /* Set up DDR to 100MHz. */
++ update_lpddr2_freq(LPDDR2_AUDIO_CLK);
++
++ /* Fix the clock tree in kernel */
++ imx_clk_set_parent(periph2_pre_clk, pll2_200);
++ imx_clk_set_parent(periph2_clk, periph2_pre_clk);
++
++ if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
++ /*
++ * Fix the clock tree in kernel, make sure
++ * pll2_bypass is updated as it is
++ * sourced from PLL2.
++ */
++ imx_clk_set_parent(pll2_bypass, pll2);
++ /*
++ * Swtich ARM to run off PLL2_PFD2_400MHz
++ * since DDR is anyway at 100MHz.
++ */
++ imx_clk_set_parent(step_clk, pll2_400);
++ imx_clk_set_parent(pll1_sw_clk, step_clk);
++ /*
++ * Need to ensure that PLL1 is bypassed and enabled
++ * before ARM-PODF is set.
++ */
++ clk_set_parent(pll1_bypass, pll1_bypass_src);
++
++ /*
++ * Ensure that the clock will be
++ * at original speed.
++ */
++ imx_clk_set_rate(cpu_clk, org_arm_rate);
++ }
++ low_bus_freq_mode = 0;
++ ultra_low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 1;
++ } else {
++ u32 arm_div, pll1_rate;
++ org_arm_rate = clk_get_rate(cpu_clk);
++ if (low_bus_freq_mode && low_bus_count == 0) {
++ /*
++ * We are already in DDR @ 24MHz state, but
++ * no one but ARM needs the DDR. In this case,
++ * we can lower the DDR freq to 1MHz when ARM
++ * enters WFI in this state. Keep track of this state.
++ */
++ ultra_low_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++ } else {
++ if (!ultra_low_bus_freq_mode && !low_bus_freq_mode) {
++ /*
++ * Anyway, make sure the AHB is running at 24MHz
++ * in low_bus_freq_mode.
++ */
++ if (audio_bus_freq_mode)
++ imx_clk_set_rate(ahb_clk, LPAPM_CLK);
++ /*
++ * Set DDR to 24MHz.
++ * Since we are going to bypass PLL2,
++ * we need to move ARM clk off PLL2_PFD2
++ * to PLL1. Make sure the PLL1 is running
++ * at the lowest possible freq.
++ * To work well with CPUFREQ we want to ensure that
++ * the CPU freq does not change, so attempt to
++ * get a freq as close to 396MHz as possible.
++ */
++ imx_clk_set_rate(pll1,
++ clk_round_rate(pll1, (org_arm_rate * 2)));
++ pll1_rate = clk_get_rate(pll1);
++ arm_div = pll1_rate / org_arm_rate;
++ if (pll1_rate / arm_div > org_arm_rate)
++ arm_div++;
++ /*
++ * Need to ensure that PLL1 is bypassed and enabled
++ * before ARM-PODF is set.
++ */
++ clk_set_parent(pll1_bypass, pll1);
++ /*
++ * Ensure ARM CLK is lower before
++ * changing the parent.
++ */
++ imx_clk_set_rate(cpu_clk, org_arm_rate / arm_div);
++ /* Now set the ARM clk parent to PLL1_SYS. */
++ imx_clk_set_parent(pll1_sw_clk, pll1_sys);
++
++ /*
++ * Set STEP_CLK back to OSC to save power and
++ * also to maintain the parent.The WFI iram code
++ * will switch step_clk to osc, but the clock API
++ * is not aware of the change and when a new request
++ * to change the step_clk parent to pll2_pfd2_400M
++ * is requested sometime later, the change is ignored.
++ */
++ imx_clk_set_parent(step_clk, osc_clk);
++ /* Now set DDR to 24MHz. */
++ update_lpddr2_freq(LPAPM_CLK);
++
++ /*
++ * Fix the clock tree in kernel.
++ * Make sure PLL2 rate is updated as it gets
++ * bypassed in the DDR freq change code.
++ */
++ imx_clk_set_parent(pll2_bypass, pll2_bypass_src);
++ imx_clk_set_parent(periph2_clk2_sel, pll2_bus);
++ imx_clk_set_parent(periph2_clk, periph2_clk2);
++
++ }
++ if (low_bus_count == 0) {
++ ultra_low_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ } else {
++ ultra_low_bus_freq_mode = 0;
++ low_bus_freq_mode = 1;
++ }
++ audio_bus_freq_mode = 0;
++ }
++ }
++}
++
++static void exit_lpm_imx6sl(void)
++{
++ /* Change DDR freq in IRAM. */
++ update_lpddr2_freq(ddr_normal_rate);
++
++ /*
++ * Fix the clock tree in kernel.
++ * Make sure PLL2 rate is updated as it gets
++ * un-bypassed in the DDR freq change code.
++ */
++ imx_clk_set_parent(pll2_bypass, pll2);
++ imx_clk_set_parent(periph2_pre_clk, pll2_400);
++ imx_clk_set_parent(periph2_clk, periph2_pre_clk);
++
++ /* Ensure that periph_clk is sourced from PLL2_400. */
++ imx_clk_set_parent(periph_pre_clk, pll2_400);
++ /*
++ * Before switching the perhiph_clk, ensure that the
++ * AHB/AXI will not be too fast.
++ */
++ imx_clk_set_rate(ahb_clk, LPAPM_CLK / 3);
++ imx_clk_set_rate(ocram_clk, LPAPM_CLK / 2);
++ imx_clk_set_parent(periph_clk, periph_pre_clk);
++
++ if (low_bus_freq_mode || ultra_low_bus_freq_mode) {
++ /* Move ARM from PLL1_SW_CLK to PLL2_400. */
++ imx_clk_set_parent(step_clk, pll2_400);
++ imx_clk_set_parent(pll1_sw_clk, step_clk);
++ /*
++ * Need to ensure that PLL1 is bypassed and enabled
++ * before ARM-PODF is set.
++ */
++ clk_set_parent(pll1_bypass, pll1_bypass_src);
++ imx_clk_set_rate(cpu_clk, org_arm_rate);
++ ultra_low_bus_freq_mode = 0;
++ }
++}
++#endif
++
++static void reduce_bus_freq(void)
++{
++ clk_prepare_enable(pll3);
++ if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode))
++ busfreq_notify(LOW_BUSFREQ_EXIT);
++ else if (!audio_bus_count)
++ busfreq_notify(LOW_BUSFREQ_ENTER);
++ switch(__mxc_cpu_type) {
++ case MXC_CPU_IMX6SL:
++#ifdef CONFIG_SOC_IMX6SL
++ enter_lpm_imx6sl();
++#endif
++ break;
++ case MXC_CPU_IMX6SX:
++#ifdef CONFIG_SOC_IMX6SX
++ enter_lpm_imx6sx();
++#endif
++ break;
++ default:
++#ifdef CONFIG_SOC_IMX6Q
++ if (cpu_is_imx6dl())
++ /* Set axi to periph_clk */
++ imx_clk_set_parent(axi_sel_clk, periph_clk);
++
++ if (audio_bus_count) {
++ /* Need to ensure that PLL2_PFD_400M is kept ON. */
++ clk_prepare_enable(pll2_400);
++ update_ddr_freq_imx6q(DDR3_AUDIO_CLK);
++ /* Make sure periph clk's parent also got updated */
++ imx_clk_set_parent(periph_clk2_sel, pll3);
++ imx_clk_set_parent(periph_pre_clk, pll2_200);
++ imx_clk_set_parent(periph_clk, periph_pre_clk);
++ audio_bus_freq_mode = 1;
++ low_bus_freq_mode = 0;
++ } else {
++ update_ddr_freq_imx6q(LPAPM_CLK);
++ /* Make sure periph clk's parent also got updated */
++ imx_clk_set_parent(periph_clk2_sel, osc_clk);
++ /* Set periph_clk parent to OSC via periph_clk2_sel */
++ imx_clk_set_parent(periph_clk, periph_clk2);
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++ low_bus_freq_mode = 1;
++ audio_bus_freq_mode = 0;
++ }
++#endif
++ break;
++ }
++ clk_disable_unprepare(pll3);
++
++ med_bus_freq_mode = 0;
++ high_bus_freq_mode = 0;
++
++ if (audio_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to audio mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++ if (low_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to low mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++}
++
++static void reduce_bus_freq_handler(struct work_struct *work)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ reduce_bus_freq();
++
++ mutex_unlock(&bus_freq_mutex);
++}
++
++/*
++ * Set the DDR, AHB to 24MHz.
++ * This mode will be activated only when none of the modules that
++ * need a higher DDR or AHB frequency are active.
++ */
++int set_low_bus_freq(void)
++{
++ if (busfreq_suspended)
++ return 0;
++
++ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
++ return 0;
++
++ /*
++ * Check to see if we need to got from
++ * low bus freq mode to audio bus freq mode.
++ * If so, the change needs to be done immediately.
++ */
++ if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode))
++ reduce_bus_freq();
++ else
++ /*
++ * Don't lower the frequency immediately. Instead
++ * scheduled a delayed work and drop the freq if
++ * the conditions still remain the same.
++ */
++ schedule_delayed_work(&low_bus_freq_handler,
++ usecs_to_jiffies(3000000));
++ return 0;
++}
++
++/*
++ * Set the DDR to either 528MHz or 400MHz for iMX6qd
++ * or 400MHz for iMX6dl.
++ */
++static int set_high_bus_freq(int high_bus_freq)
++{
++ struct clk *periph_clk_parent;
++
++ if (bus_freq_scaling_initialized && bus_freq_scaling_is_active)
++ cancel_delayed_work_sync(&low_bus_freq_handler);
++
++ if (busfreq_suspended)
++ return 0;
++
++ if (cpu_is_imx6q())
++ periph_clk_parent = pll2_bus;
++ else
++ periph_clk_parent = pll2_400;
++
++ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active)
++ return 0;
++
++ if (high_bus_freq_mode)
++ return 0;
++
++ /* medium bus freq is only supported for MX6DQ */
++ if (med_bus_freq_mode && !high_bus_freq)
++ return 0;
++
++ if (low_bus_freq_mode || ultra_low_bus_freq_mode)
++ busfreq_notify(LOW_BUSFREQ_EXIT);
++
++ clk_prepare_enable(pll3);
++
++ switch(__mxc_cpu_type) {
++ case MXC_CPU_IMX6SL:
++#ifdef CONFIG_SOC_IMX6SL
++ exit_lpm_imx6sl();
++#endif
++ break;
++ case MXC_CPU_IMX6SX:
++#ifdef CONFIG_SOC_IMX6SX
++ exit_lpm_imx6sx();
++#endif
++ break;
++ default:
++#ifdef CONFIG_SOC_IMX6Q
++ if (high_bus_freq) {
++ clk_prepare_enable(pll2_400);
++ update_ddr_freq_imx6q(ddr_normal_rate);
++ /* Make sure periph clk's parent also got updated */
++ imx_clk_set_parent(periph_clk2_sel, pll3);
++ imx_clk_set_parent(periph_pre_clk, periph_clk_parent);
++ imx_clk_set_parent(periph_clk, periph_pre_clk);
++ if (cpu_is_imx6dl()) {
++ /* Set axi to pll3_pfd1_540m */
++ imx_clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m);
++ imx_clk_set_parent(axi_sel_clk, axi_alt_sel_clk);
++ }
++ clk_disable_unprepare(pll2_400);
++ } else {
++ update_ddr_freq_imx6q(ddr_med_rate);
++ /* Make sure periph clk's parent also got updated */
++ imx_clk_set_parent(periph_clk2_sel, pll3);
++ imx_clk_set_parent(periph_pre_clk, pll2_400);
++ imx_clk_set_parent(periph_clk, periph_pre_clk);
++ }
++ if (audio_bus_freq_mode)
++ clk_disable_unprepare(pll2_400);
++#endif
++ break;
++ }
++
++ high_bus_freq_mode = 1;
++ med_bus_freq_mode = 0;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++
++ clk_disable_unprepare(pll3);
++ if (high_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to high mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++ if (med_bus_freq_mode)
++ dev_dbg(busfreq_dev, "Bus freq set to med mode. Count:\
++ high %d, med %d, audio %d\n",
++ high_bus_count, med_bus_count, audio_bus_count);
++
++ return 0;
++}
++
++void request_bus_freq(enum bus_freq_mode mode)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ if (mode == BUS_FREQ_HIGH)
++ high_bus_count++;
++ else if (mode == BUS_FREQ_MED)
++ med_bus_count++;
++ else if (mode == BUS_FREQ_AUDIO)
++ audio_bus_count++;
++ else if (mode == BUS_FREQ_LOW)
++ low_bus_count++;
++
++ if (busfreq_suspended || !bus_freq_scaling_initialized ||
++ !bus_freq_scaling_is_active) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ cancel_delayed_work_sync(&low_bus_freq_handler);
++
++ if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
++ /* No support for medium setpoint on i.MX6DL and i.MX6SX. */
++ if (mode == BUS_FREQ_MED) {
++ high_bus_count++;
++ mode = BUS_FREQ_HIGH;
++ }
++ }
++
++ if ((mode == BUS_FREQ_HIGH) && (!high_bus_freq_mode)) {
++ set_high_bus_freq(1);
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ if ((mode == BUS_FREQ_MED) && (!high_bus_freq_mode) &&
++ (!med_bus_freq_mode)) {
++ set_high_bus_freq(0);
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((mode == BUS_FREQ_AUDIO) && (!high_bus_freq_mode) &&
++ (!med_bus_freq_mode) && (!audio_bus_freq_mode)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ mutex_unlock(&bus_freq_mutex);
++ return;
++}
++EXPORT_SYMBOL(request_bus_freq);
++
++void release_bus_freq(enum bus_freq_mode mode)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ if (mode == BUS_FREQ_HIGH) {
++ if (high_bus_count == 0) {
++ dev_err(busfreq_dev, "high bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ high_bus_count--;
++ } else if (mode == BUS_FREQ_MED) {
++ if (med_bus_count == 0) {
++ dev_err(busfreq_dev, "med bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ med_bus_count--;
++ } else if (mode == BUS_FREQ_AUDIO) {
++ if (audio_bus_count == 0) {
++ dev_err(busfreq_dev, "audio bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ audio_bus_count--;
++ } else if (mode == BUS_FREQ_LOW) {
++ if (low_bus_count == 0) {
++ dev_err(busfreq_dev, "low bus count mismatch!\n");
++ dump_stack();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ low_bus_count--;
++ }
++
++ if (busfreq_suspended || !bus_freq_scaling_initialized ||
++ !bus_freq_scaling_is_active) {
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
++ /* No support for medium setpoint on i.MX6DL and i.MX6SX. */
++ if (mode == BUS_FREQ_MED) {
++ high_bus_count--;
++ mode = BUS_FREQ_HIGH;
++ }
++ }
++
++ if ((!audio_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count != 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((!low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0) &&
++ (low_bus_count != 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++ if ((!ultra_low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0) &&
++ (low_bus_count == 0)) {
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++ return;
++ }
++
++ mutex_unlock(&bus_freq_mutex);
++ return;
++}
++EXPORT_SYMBOL(release_bus_freq);
++
++static struct map_desc ddr_iram_io_desc __initdata = {
++ /* .virtual and .pfn are run-time assigned */
++ .length = SZ_1M,
++ .type = MT_MEMORY_RWX_NONCACHED,
++};
++
++const static char *ddr_freq_iram_match[] __initconst = {
++ "fsl,ddr-lpm-sram",
++ NULL
++};
++
++static int __init imx6_dt_find_ddr_sram(unsigned long node,
++ const char *uname, int depth, void *data)
++{
++ unsigned long ddr_iram_addr;
++ __be32 *prop;
++
++ if (of_flat_dt_match(node, ddr_freq_iram_match)) {
++ unsigned long len;
++ prop = of_get_flat_dt_prop(node, "reg", &len);
++ if (prop == NULL || len != (sizeof(unsigned long) * 2))
++ return EINVAL;
++ ddr_iram_addr = be32_to_cpu(prop[0]);
++ ddr_freq_change_total_size = be32_to_cpu(prop[1]);
++ ddr_freq_change_iram_phys = ddr_iram_addr;
++
++ /* Make sure ddr_freq_change_iram_phys is 8 byte aligned. */
++ if ((uintptr_t)(ddr_freq_change_iram_phys) & (FNCPY_ALIGN - 1))
++ ddr_freq_change_iram_phys += FNCPY_ALIGN - ((uintptr_t)ddr_freq_change_iram_phys % (FNCPY_ALIGN));
++ }
++ return 0;
++}
++
++void __init imx6_busfreq_map_io(void)
++{
++ /*
++ * Get the address of IRAM to be used by the ddr frequency
++ * change code from the device tree.
++ */
++ WARN_ON(of_scan_flat_dt(imx6_dt_find_ddr_sram, NULL));
++
++ if (ddr_freq_change_iram_phys) {
++ ddr_freq_change_iram_base = IMX_IO_P2V(ddr_freq_change_iram_phys);
++ if ((iram_tlb_phys_addr & 0xFFF00000) != (ddr_freq_change_iram_phys & 0xFFF00000)) {
++ /* We need to create a 1M page table entry. */
++ ddr_iram_io_desc.virtual = IMX_IO_P2V(ddr_freq_change_iram_phys & 0xFFF00000);
++ ddr_iram_io_desc.pfn = __phys_to_pfn(ddr_freq_change_iram_phys & 0xFFF00000);
++ iotable_init(&ddr_iram_io_desc, 1);
++ }
++ memset((void *)ddr_freq_change_iram_base, 0, ddr_freq_change_total_size);
++ }
++}
++
++static void bus_freq_daemon_handler(struct work_struct *work)
++{
++ mutex_lock(&bus_freq_mutex);
++ if ((!low_bus_freq_mode) && (!ultra_low_bus_freq_mode) && (high_bus_count == 0) &&
++ (med_bus_count == 0) && (audio_bus_count == 0))
++ set_low_bus_freq();
++ mutex_unlock(&bus_freq_mutex);
++}
++
++static ssize_t bus_freq_scaling_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ if (bus_freq_scaling_is_active)
++ return sprintf(buf, "Bus frequency scaling is enabled\n");
++ else
++ return sprintf(buf, "Bus frequency scaling is disabled\n");
++}
++
++static ssize_t bus_freq_scaling_enable_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t size)
++{
++ if (strncmp(buf, "1", 1) == 0) {
++ bus_freq_scaling_is_active = 1;
++ set_high_bus_freq(1);
++ /*
++ * We set bus freq to highest at the beginning,
++ * so we use this daemon thread to make sure system
++ * can enter low bus mode if
++ * there is no high bus request pending
++ */
++ schedule_delayed_work(&bus_freq_daemon,
++ usecs_to_jiffies(5000000));
++ } else if (strncmp(buf, "0", 1) == 0) {
++ if (bus_freq_scaling_is_active)
++ set_high_bus_freq(1);
++ bus_freq_scaling_is_active = 0;
++ }
++ return size;
++}
++
++static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ mutex_lock(&bus_freq_mutex);
++
++ if (event == PM_SUSPEND_PREPARE) {
++ high_bus_count++;
++ set_high_bus_freq(1);
++ busfreq_suspended = 1;
++ } else if (event == PM_POST_SUSPEND) {
++ busfreq_suspended = 0;
++ high_bus_count--;
++ schedule_delayed_work(&bus_freq_daemon,
++ usecs_to_jiffies(5000000));
++ }
++
++ mutex_unlock(&bus_freq_mutex);
++
++ return NOTIFY_OK;
++}
++
++static int busfreq_reboot_notifier_event(struct notifier_block *this,
++ unsigned long event, void *ptr)
++{
++ /* System is rebooting. Set the system into high_bus_freq_mode. */
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ return 0;
++}
++
++static struct notifier_block imx_bus_freq_pm_notifier = {
++ .notifier_call = bus_freq_pm_notify,
++};
++
++static struct notifier_block imx_busfreq_reboot_notifier = {
++ .notifier_call = busfreq_reboot_notifier_event,
++};
++
++
++static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show,
++ bus_freq_scaling_enable_store);
++
++/*!
++ * This is the probe routine for the bus frequency driver.
++ *
++ * @param pdev The platform device structure
++ *
++ * @return The function returns 0 on success
++ *
++ */
++
++static int busfreq_probe(struct platform_device *pdev)
++{
++ u32 err;
++
++ busfreq_dev = &pdev->dev;
++
++ /* Return if no IRAM space is allocated for ddr freq change code. */
++ if (!ddr_freq_change_iram_base)
++ return ENOMEM;
++
++ pll2_400 = devm_clk_get(&pdev->dev, "pll2_pfd2_396m");
++ if (IS_ERR(pll2_400)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_pfd2_396m\n",
++ __func__);
++ return PTR_ERR(pll2_400);
++ }
++
++ pll2_200 = devm_clk_get(&pdev->dev, "pll2_198m");
++ if (IS_ERR(pll2_200)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_198m\n",
++ __func__);
++ return PTR_ERR(pll2_200);
++ }
++
++ pll2_bus = devm_clk_get(&pdev->dev, "pll2_bus");
++ if (IS_ERR(pll2_bus)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_bus\n",
++ __func__);
++ return PTR_ERR(pll2_bus);
++ }
++
++ cpu_clk = devm_clk_get(&pdev->dev, "arm");
++ if (IS_ERR(cpu_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get cpu_clk\n",
++ __func__);
++ return PTR_ERR(cpu_clk);
++ }
++
++ pll3 = devm_clk_get(&pdev->dev, "pll3_usb_otg");
++ if (IS_ERR(pll3)) {
++ dev_err(busfreq_dev, "%s: failed to get pll3_usb_otg\n",
++ __func__);
++ return PTR_ERR(pll3);
++ }
++
++ periph_clk = devm_clk_get(&pdev->dev, "periph");
++ if (IS_ERR(periph_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph\n",
++ __func__);
++ return PTR_ERR(periph_clk);
++ }
++
++ periph_pre_clk = devm_clk_get(&pdev->dev, "periph_pre");
++ if (IS_ERR(periph_pre_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_pre\n",
++ __func__);
++ return PTR_ERR(periph_pre_clk);
++ }
++
++ periph_clk2 = devm_clk_get(&pdev->dev, "periph_clk2");
++ if (IS_ERR(periph_clk2)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_clk2\n",
++ __func__);
++ return PTR_ERR(periph_clk2);
++ }
++
++ periph_clk2_sel = devm_clk_get(&pdev->dev, "periph_clk2_sel");
++ if (IS_ERR(periph_clk2_sel)) {
++ dev_err(busfreq_dev, "%s: failed to get periph_clk2_sel\n",
++ __func__);
++ return PTR_ERR(periph_clk2_sel);
++ }
++
++ osc_clk = devm_clk_get(&pdev->dev, "osc");
++ if (IS_ERR(osc_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get osc_clk\n",
++ __func__);
++ return PTR_ERR(osc_clk);
++ }
++
++ if (cpu_is_imx6dl()) {
++ axi_alt_sel_clk = devm_clk_get(&pdev->dev, "axi_alt_sel");
++ if (IS_ERR(axi_alt_sel_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get axi_alt_sel_clk\n",
++ __func__);
++ return PTR_ERR(axi_alt_sel_clk);
++ }
++
++ axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel");
++ if (IS_ERR(axi_sel_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get axi_sel_clk\n",
++ __func__);
++ return PTR_ERR(axi_sel_clk);
++ }
++
++ pll3_pfd1_540m = devm_clk_get(&pdev->dev, "pll3_pfd1_540m");
++ if (IS_ERR(pll3_pfd1_540m)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get pll3_pfd1_540m\n", __func__);
++ return PTR_ERR(pll3_pfd1_540m);
++ }
++ }
++
++ if (cpu_is_imx6sl() || cpu_is_imx6sx()) {
++ ahb_clk = devm_clk_get(&pdev->dev, "ahb");
++ if (IS_ERR(ahb_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get ahb_clk\n",
++ __func__);
++ return PTR_ERR(ahb_clk);
++ }
++
++ ocram_clk = devm_clk_get(&pdev->dev, "ocram");
++ if (IS_ERR(ocram_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get ocram_clk\n",
++ __func__);
++ return PTR_ERR(ocram_clk);
++ }
++
++ periph2_clk = devm_clk_get(&pdev->dev, "periph2");
++ if (IS_ERR(periph2_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get periph2\n",
++ __func__);
++ return PTR_ERR(periph2_clk);
++ }
++
++ periph2_pre_clk = devm_clk_get(&pdev->dev, "periph2_pre");
++ if (IS_ERR(periph2_pre_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_pre_clk\n",
++ __func__);
++ return PTR_ERR(periph2_pre_clk);
++ }
++
++ periph2_clk2 = devm_clk_get(&pdev->dev, "periph2_clk2");
++ if (IS_ERR(periph2_clk2)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_clk2\n",
++ __func__);
++ return PTR_ERR(periph2_clk2);
++ }
++
++ periph2_clk2_sel = devm_clk_get(&pdev->dev, "periph2_clk2_sel");
++ if (IS_ERR(periph2_clk2_sel)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get periph2_clk2_sel\n",
++ __func__);
++ return PTR_ERR(periph2_clk2_sel);
++ }
++
++ step_clk = devm_clk_get(&pdev->dev, "step");
++ if (IS_ERR(step_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get step_clk\n",
++ __func__);
++ return PTR_ERR(step_clk);
++ }
++ }
++ if (cpu_is_imx6sl()) {
++ pll1 = devm_clk_get(&pdev->dev, "pll1");
++ if (IS_ERR(pll1)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1\n",
++ __func__);
++ return PTR_ERR(pll1);
++ }
++
++ pll1_bypass = devm_clk_get(&pdev->dev, "pll1_bypass");
++ if (IS_ERR(pll1_bypass)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_bypass\n",
++ __func__);
++ return PTR_ERR(pll1_bypass);
++ }
++
++ pll1_bypass_src = devm_clk_get(&pdev->dev, "pll1_bypass_src");
++ if (IS_ERR(pll1_bypass_src)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_bypass_src\n",
++ __func__);
++ return PTR_ERR(pll1_bypass_src);
++ }
++
++ pll1_sys = devm_clk_get(&pdev->dev, "pll1_sys");
++ if (IS_ERR(pll1_sys)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_sys\n",
++ __func__);
++ return PTR_ERR(pll1_sys);
++ }
++
++ pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw");
++ if (IS_ERR(pll1_sw_clk)) {
++ dev_err(busfreq_dev, "%s: failed to get pll1_sw_clk\n",
++ __func__);
++ return PTR_ERR(pll1_sw_clk);
++ }
++
++ pll2_bypass_src = devm_clk_get(&pdev->dev, "pll2_bypass_src");
++ if (IS_ERR(pll2_bypass_src)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_bypass_src\n",
++ __func__);
++ return PTR_ERR(pll2_bypass_src);
++ }
++
++ pll2 = devm_clk_get(&pdev->dev, "pll2");
++ if (IS_ERR(pll2)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2\n",
++ __func__);
++ return PTR_ERR(pll2);
++ }
++
++ pll2_bypass = devm_clk_get(&pdev->dev, "pll2_bypass");
++ if (IS_ERR(pll2_bypass)) {
++ dev_err(busfreq_dev, "%s: failed to get pll2_bypass\n",
++ __func__);
++ return PTR_ERR(pll2_bypass);
++ }
++ }
++ if (cpu_is_imx6sx()) {
++ mmdc_clk = devm_clk_get(&pdev->dev, "mmdc");
++ if (IS_ERR(mmdc_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get mmdc_clk\n",
++ __func__);
++ return PTR_ERR(mmdc_clk);
++ }
++ m4_clk = devm_clk_get(&pdev->dev, "m4");
++ if (IS_ERR(m4_clk)) {
++ dev_err(busfreq_dev,
++ "%s: failed to get m4_clk\n",
++ __func__);
++ return PTR_ERR(m4_clk);
++ }
++ }
++
++ err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
++ if (err) {
++ dev_err(busfreq_dev,
++ "Unable to register sysdev entry for BUSFREQ");
++ return err;
++ }
++
++ if (of_property_read_u32(pdev->dev.of_node, "fsl,max_ddr_freq",
++ &ddr_normal_rate)) {
++ dev_err(busfreq_dev, "max_ddr_freq entry missing\n");
++ return -EINVAL;
++ }
++
++ high_bus_freq_mode = 1;
++ med_bus_freq_mode = 0;
++ low_bus_freq_mode = 0;
++ audio_bus_freq_mode = 0;
++ ultra_low_bus_freq_mode = 0;
++
++ bus_freq_scaling_is_active = 0;
++ bus_freq_scaling_initialized = 1;
++
++ ddr_low_rate = LPAPM_CLK;
++ if (cpu_is_imx6q()) {
++ if (of_property_read_u32(pdev->dev.of_node, "fsl,med_ddr_freq",
++ &ddr_med_rate)) {
++ dev_info(busfreq_dev,
++ "DDR medium rate not supported.\n");
++ ddr_med_rate = ddr_normal_rate;
++ }
++ }
++
++ INIT_DELAYED_WORK(&low_bus_freq_handler, reduce_bus_freq_handler);
++ INIT_DELAYED_WORK(&bus_freq_daemon, bus_freq_daemon_handler);
++ register_pm_notifier(&imx_bus_freq_pm_notifier);
++ register_reboot_notifier(&imx_busfreq_reboot_notifier);
++
++ /*
++ * Need to make sure to an entry for the ddr freq change code address in the IRAM page table.
++ * This is only required if the DDR freq code and suspend/idle code are in different OCRAM spaces.
++ */
++ if ((iram_tlb_phys_addr & 0xFFF00000) != (ddr_freq_change_iram_phys & 0xFFF00000)) {
++ unsigned long i;
++
++ /*
++ * Make sure the ddr_iram virtual address has a mapping
++ * in the IRAM page table.
++ */
++ i = ((IMX_IO_P2V(ddr_freq_change_iram_phys) >> 20) << 2) / 4;
++ *((unsigned long *)iram_tlb_base_addr + i) =
++ (ddr_freq_change_iram_phys & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M;
++ }
++
++#if defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6SL)
++ if (cpu_is_imx6sl()) {
++ err = init_mmdc_lpddr2_settings(pdev);
++#ifdef CONFIG_SOC_IMX6SX
++ } else if (cpu_is_imx6sx()) {
++ ddr_type = imx_mmdc_get_ddr_type();
++ /* check whether it is a DDR3 or LPDDR2 board */
++ if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3)
++ err = init_mmdc_ddr3_settings_imx6sx(pdev);
++ else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2)
++ err = init_mmdc_lpddr2_settings(pdev);
++ /* if M4 is enabled and rate > 24MHz, add high bus count */
++ if (imx_src_is_m4_enabled() &&
++ (clk_get_rate(m4_clk) > LPAPM_CLK))
++ high_bus_count++;
++#endif
++ }
++#endif
++#ifdef CONFIG_SOC_IMX6Q
++ else
++ err = init_mmdc_ddr3_settings_imx6q(pdev);
++#endif
++
++ if (err) {
++ dev_err(busfreq_dev, "Busfreq init of MMDC failed\n");
++ return err;
++ }
++ return 0;
++}
++
++static const struct of_device_id imx6_busfreq_ids[] = {
++ { .compatible = "fsl,imx6_busfreq", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver busfreq_driver = {
++ .driver = {
++ .name = "imx6_busfreq",
++ .owner = THIS_MODULE,
++ .of_match_table = imx6_busfreq_ids,
++ },
++ .probe = busfreq_probe,
++};
++
++/*!
++ * Initialise the busfreq_driver.
++ *
++ * @return The function always returns 0.
++ */
++
++static int __init busfreq_init(void)
++{
++#ifndef CONFIG_MX6_VPU_352M
++ if (platform_driver_register(&busfreq_driver) != 0)
++ return -ENODEV;
++
++ printk(KERN_INFO "Bus freq driver module loaded\n");
++#endif
++ return 0;
++}
++
++static void __exit busfreq_cleanup(void)
++{
++ sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr);
++
++ /* Unregister the device structure */
++ platform_driver_unregister(&busfreq_driver);
++ bus_freq_scaling_initialized = 0;
++}
++
++module_init(busfreq_init);
++module_exit(busfreq_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("BusFreq driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/busfreq_lpddr2.c linux-3.14.72/arch/arm/mach-imx/busfreq_lpddr2.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/busfreq_lpddr2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/busfreq_lpddr2.c 2016-06-19 22:11:55.045157162 +0200
+@@ -0,0 +1,116 @@
++/*
++ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file busfreq_lpddr2.c
++ *
++ * @brief iMX6 LPDDR2 frequency change specific file.
++ *
++ * @ingroup PM
++ */
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/io.h>
++#include <asm/mach/map.h>
++#include <asm/mach-types.h>
++#include <asm/tlb.h>
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/irqchip/arm-gic.h>
++#include <linux/kernel.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/proc_fs.h>
++#include <linux/sched.h>
++#include <linux/smp.h>
++
++#include "hardware.h"
++
++
++static struct device *busfreq_dev;
++static int curr_ddr_rate;
++static DEFINE_SPINLOCK(freq_lock);
++
++void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode) = NULL;
++
++extern unsigned int ddr_normal_rate;
++extern int low_bus_freq_mode;
++extern int ultra_low_bus_freq_mode;
++extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode);
++#ifdef CONFIG_SOC_IMX6SX
++extern void imx6sx_lpddr2_freq_change(u32 freq, int bus_freq_mode);
++#endif
++extern unsigned long save_ttbr1(void);
++extern void restore_ttbr1(unsigned long ttbr1);
++extern unsigned long ddr_freq_change_iram_base;
++extern unsigned long imx6_lpddr2_freq_change_start asm("imx6_lpddr2_freq_change_start");
++extern unsigned long imx6_lpddr2_freq_change_end asm("imx6_lpddr2_freq_change_end");
++
++/* change the DDR frequency. */
++int update_lpddr2_freq(int ddr_rate)
++{
++ unsigned long ttbr1, flags;
++
++ if (ddr_rate == curr_ddr_rate)
++ return 0;
++
++ pr_debug("Bus freq set to %d start...\n", ddr_rate);
++
++ spin_lock_irqsave(&freq_lock, flags);
++ /*
++ * Flush the TLB, to ensure no TLB maintenance occurs
++ * when DDR is in self-refresh.
++ */
++ ttbr1 = save_ttbr1();
++
++ /* Now change DDR frequency. */
++ mx6_change_lpddr2_freq(ddr_rate,
++ (low_bus_freq_mode | ultra_low_bus_freq_mode));
++ restore_ttbr1(ttbr1);
++
++ curr_ddr_rate = ddr_rate;
++ spin_unlock_irqrestore(&freq_lock, flags);
++
++ pr_debug("Bus freq set to %d done...\n", ddr_rate);
++
++ return 0;
++}
++
++int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev)
++{
++ unsigned long ddr_code_size;
++ busfreq_dev = &busfreq_pdev->dev;
++
++ ddr_code_size = (&imx6_lpddr2_freq_change_end -&imx6_lpddr2_freq_change_start) *4;
++
++ if (cpu_is_imx6sl())
++ mx6_change_lpddr2_freq = (void *)fncpy(
++ (void *)ddr_freq_change_iram_base,
++ &mx6_lpddr2_freq_change, ddr_code_size);
++#ifdef CONFIG_SOC_IMX6SX
++ else if (cpu_is_imx6sx())
++ mx6_change_lpddr2_freq = (void *)fncpy(
++ (void *)ddr_freq_change_iram_base,
++ &imx6sx_lpddr2_freq_change, ddr_code_size);
++#endif
++
++ curr_ddr_rate = ddr_normal_rate;
++
++ return 0;
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-busy.c linux-3.14.72/arch/arm/mach-imx/clk-busy.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-busy.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-busy.c 2016-06-19 22:11:55.045157162 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2015 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -187,3 +187,12 @@
+
+ return clk;
+ }
++
++struct clk *imx_clk_busy_gate(const char *name, const char *parent,
++ void __iomem *reg, u8 shift)
++{
++ return clk_register_gate2(NULL, name, parent,
++ CLK_SET_RATE_PARENT,
++ reg, shift, 0, &imx_ccm_lock, NULL);
++}
++
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-gate2.c linux-3.14.72/arch/arm/mach-imx/clk-gate2.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-gate2.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-gate2.c 2016-06-19 22:11:55.045157162 +0200
+@@ -1,6 +1,7 @@
+ /*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -10,12 +11,14 @@
+ */
+
+ #include <linux/clk-provider.h>
++#include <linux/imx_sema4.h>
+ #include <linux/module.h>
+ #include <linux/slab.h>
+ #include <linux/io.h>
+ #include <linux/err.h>
+ #include <linux/string.h>
+ #include "clk.h"
++#include "common.h"
+
+ /**
+ * DOC: basic gatable clock which can gate and ungate it's ouput
+@@ -27,57 +30,118 @@
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
++struct clk_gate2 {
++ struct clk_hw hw;
++ void __iomem *reg;
++ u8 bit_idx;
++ u8 flags;
++ spinlock_t *lock;
++ unsigned int *share_count;
++};
+
+-static int clk_gate2_enable(struct clk_hw *hw)
++#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
++#define CCM_CCGR_FULL_ENABLE 0x3
++
++static void clk_gate2_do_hardware(struct clk_gate2 *gate, bool enable)
+ {
+- struct clk_gate *gate = to_clk_gate(hw);
+ u32 reg;
+- unsigned long flags = 0;
+-
+- if (gate->lock)
+- spin_lock_irqsave(gate->lock, flags);
+
+ reg = readl(gate->reg);
+- reg |= 3 << gate->bit_idx;
++ if (enable)
++ reg |= CCM_CCGR_FULL_ENABLE << gate->bit_idx;
++ else
++ reg &= ~(CCM_CCGR_FULL_ENABLE << gate->bit_idx);
+ writel(reg, gate->reg);
++}
+
+- if (gate->lock)
+- spin_unlock_irqrestore(gate->lock, flags);
++static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable)
++{
++ struct clk_gate2 *gate = to_clk_gate2(hw);
+
+- return 0;
++#ifdef CONFIG_SOC_IMX6SX
++ if (imx_src_is_m4_enabled()) {
++ if (!amp_power_mutex || !shared_mem) {
++ if (enable)
++ clk_gate2_do_hardware(gate, enable);
++ return;
++ }
++
++ imx_sema4_mutex_lock(amp_power_mutex);
++ if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER ||
++ shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) {
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ return;
++ }
++
++ if (!imx_update_shared_mem(hw, enable)) {
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ return;
++ }
++
++ clk_gate2_do_hardware(gate, enable);
++
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ } else
++#endif
++ clk_gate2_do_hardware(gate, enable);
+ }
+
+-static void clk_gate2_disable(struct clk_hw *hw)
++static int clk_gate2_enable(struct clk_hw *hw)
+ {
+- struct clk_gate *gate = to_clk_gate(hw);
+- u32 reg;
++ struct clk_gate2 *gate = to_clk_gate2(hw);
+ unsigned long flags = 0;
+
+- if (gate->lock)
+- spin_lock_irqsave(gate->lock, flags);
++ spin_lock_irqsave(gate->lock, flags);
+
+- reg = readl(gate->reg);
+- reg &= ~(3 << gate->bit_idx);
+- writel(reg, gate->reg);
++ if (gate->share_count && (*gate->share_count)++ > 0)
++ goto out;
++
++ clk_gate2_do_shared_clks(hw, true);
++out:
++ spin_unlock_irqrestore(gate->lock, flags);
+
+- if (gate->lock)
+- spin_unlock_irqrestore(gate->lock, flags);
++ return 0;
+ }
+
+-static int clk_gate2_is_enabled(struct clk_hw *hw)
++static void clk_gate2_disable(struct clk_hw *hw)
+ {
+- u32 reg;
+- struct clk_gate *gate = to_clk_gate(hw);
++ struct clk_gate2 *gate = to_clk_gate2(hw);
++ unsigned long flags = 0;
+
+- reg = readl(gate->reg);
++ spin_lock_irqsave(gate->lock, flags);
++
++ if (gate->share_count) {
++ if (WARN_ON(*gate->share_count == 0))
++ goto out;
++ else if (--(*gate->share_count) > 0)
++ goto out;
++ }
++
++ clk_gate2_do_shared_clks(hw, false);
++out:
++ spin_unlock_irqrestore(gate->lock, flags);
++}
+
+- if (((reg >> gate->bit_idx) & 1) == 1)
++static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
++{
++ u32 val = readl(reg);
++
++ if (((val >> bit_idx) & 1) == 1)
+ return 1;
+
+ return 0;
+ }
+
++static int clk_gate2_is_enabled(struct clk_hw *hw)
++{
++ struct clk_gate2 *gate = to_clk_gate2(hw);
++
++ if (gate->share_count)
++ return !!__clk_get_enable_count(hw->clk);
++ else
++ return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
++}
++
+ static struct clk_ops clk_gate2_ops = {
+ .enable = clk_gate2_enable,
+ .disable = clk_gate2_disable,
+@@ -87,21 +151,23 @@
+ struct clk *clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+- u8 clk_gate2_flags, spinlock_t *lock)
++ u8 clk_gate2_flags, spinlock_t *lock,
++ unsigned int *share_count)
+ {
+- struct clk_gate *gate;
++ struct clk_gate2 *gate;
+ struct clk *clk;
+ struct clk_init_data init;
+
+- gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
++ gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+- /* struct clk_gate assignments */
++ /* struct clk_gate2 assignments */
+ gate->reg = reg;
+ gate->bit_idx = bit_idx;
+ gate->flags = clk_gate2_flags;
+ gate->lock = lock;
++ gate->share_count = share_count;
+
+ init.name = name;
+ init.ops = &clk_gate2_ops;
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-gate-exclusive.c linux-3.14.72/arch/arm/mach-imx/clk-gate-exclusive.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-gate-exclusive.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/clk-gate-exclusive.c 2016-06-19 22:11:55.045157162 +0200
+@@ -0,0 +1,94 @@
++/*
++ * Copyright 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include "clk.h"
++
++/**
++ * struct clk_gate_exclusive - i.MX specific gate clock which is mutually
++ * exclusive with other gate clocks
++ *
++ * @gate: the parent class
++ * @exclusive_mask: mask of gate bits which are mutually exclusive to this
++ * gate clock
++ *
++ * The imx exclusive gate clock is a subclass of basic clk_gate
++ * with an addtional mask to indicate which other gate bits in the same
++ * register is mutually exclusive to this gate clock.
++ */
++struct clk_gate_exclusive {
++ struct clk_gate gate;
++ u32 exclusive_mask;
++};
++
++static int clk_gate_exclusive_enable(struct clk_hw *hw)
++{
++ struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
++ struct clk_gate_exclusive *exgate = container_of(gate,
++ struct clk_gate_exclusive, gate);
++ u32 val = readl(gate->reg);
++
++ if (val & exgate->exclusive_mask)
++ return -EBUSY;
++
++ return clk_gate_ops.enable(hw);
++}
++
++static void clk_gate_exclusive_disable(struct clk_hw *hw)
++{
++ clk_gate_ops.disable(hw);
++}
++
++static int clk_gate_exclusive_is_enabled(struct clk_hw *hw)
++{
++ return clk_gate_ops.is_enabled(hw);
++}
++
++static const struct clk_ops clk_gate_exclusive_ops = {
++ .enable = clk_gate_exclusive_enable,
++ .disable = clk_gate_exclusive_disable,
++ .is_enabled = clk_gate_exclusive_is_enabled,
++};
++
++struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
++ void __iomem *reg, u8 shift, u32 exclusive_mask)
++{
++ struct clk_gate_exclusive *exgate;
++ struct clk_gate *gate;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ if (exclusive_mask == 0)
++ return ERR_PTR(-EINVAL);
++
++ exgate = kzalloc(sizeof(*exgate), GFP_KERNEL);
++ if (!exgate)
++ return ERR_PTR(-ENOMEM);
++ gate = &exgate->gate;
++
++ init.name = name;
++ init.ops = &clk_gate_exclusive_ops;
++ init.flags = CLK_SET_RATE_PARENT;
++ init.parent_names = parent ? &parent : NULL;
++ init.num_parents = parent ? 1 : 0;
++
++ gate->reg = reg;
++ gate->bit_idx = shift;
++ gate->lock = &imx_ccm_lock;
++ gate->hw.init = &init;
++ exgate->exclusive_mask = exclusive_mask;
++
++ clk = clk_register(NULL, &gate->hw);
++ if (IS_ERR(clk))
++ kfree(exgate);
++
++ return clk;
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk.h linux-3.14.72/arch/arm/mach-imx/clk.h
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk.h 2016-06-19 22:11:55.045157162 +0200
+@@ -7,6 +7,8 @@
+ extern spinlock_t imx_ccm_lock;
+
+ extern void imx_cscmr1_fixup(u32 *val);
++extern struct imx_sema4_mutex *amp_power_mutex;
++extern struct imx_shared_mem *shared_mem;
+
+ struct clk *imx_clk_pllv1(const char *name, const char *parent,
+ void __iomem *base);
+@@ -22,22 +24,80 @@
+ IMX_PLLV3_ENET,
+ };
+
++#define MAX_SHARED_CLK_NUMBER 100
++#define SHARED_MEM_MAGIC_NUMBER 0x12345678
++#define MCC_POWER_SHMEM_NUMBER (6)
++
++struct imx_shared_clk {
++ struct clk *self;
++ struct clk *parent;
++ void *m4_clk;
++ void *m4_clk_parent;
++ u8 ca9_enabled;
++ u8 cm4_enabled;
++};
++
++struct imx_shared_mem {
++ u32 ca9_valid;
++ u32 cm4_valid;
++ struct imx_shared_clk imx_clk[MAX_SHARED_CLK_NUMBER];
++};
++
+ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
+ const char *parent_name, void __iomem *base, u32 div_mask);
+
+ struct clk *clk_register_gate2(struct device *dev, const char *name,
+ const char *parent_name, unsigned long flags,
+ void __iomem *reg, u8 bit_idx,
+- u8 clk_gate_flags, spinlock_t *lock);
++ u8 clk_gate_flags, spinlock_t *lock,
++ unsigned int *share_count);
+
+ struct clk * imx_obtain_fixed_clock(
+ const char *name, unsigned long rate);
+
++struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
++ void __iomem *reg, u8 shift, u32 exclusive_mask);
++
+ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
+ void __iomem *reg, u8 shift)
+ {
+ return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+- shift, 0, &imx_ccm_lock);
++ shift, 0, &imx_ccm_lock, NULL);
++}
++
++static inline struct clk *imx_clk_gate2_shared(const char *name,
++ const char *parent, void __iomem *reg, u8 shift,
++ unsigned int *share_count)
++{
++ return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
++ shift, 0, &imx_ccm_lock, share_count);
++}
++
++static inline void imx_clk_prepare_enable(struct clk *clk)
++{
++ int ret = clk_prepare_enable(clk);
++
++ if (ret)
++ pr_err("failed to prepare and enable clk %s: %d\n",
++ __clk_get_name(clk), ret);
++}
++
++static inline void imx_clk_set_parent(struct clk *clk, struct clk *parent)
++{
++ int ret = clk_set_parent(clk, parent);
++
++ if (ret)
++ pr_err("failed to set parent of clk %s to %s: %d\n",
++ __clk_get_name(clk), __clk_get_name(parent), ret);
++}
++
++static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate)
++{
++ int ret = clk_set_rate(clk, rate);
++
++ if (ret)
++ pr_err("failed to set rate of clk %s to %ld: %d\n",
++ __clk_get_name(clk), rate, ret);
+ }
+
+ struct clk *imx_clk_pfd(const char *name, const char *parent_name,
+@@ -51,6 +111,9 @@
+ u8 width, void __iomem *busy_reg, u8 busy_shift,
+ const char **parent_names, int num_parents);
+
++struct clk *imx_clk_busy_gate(const char *name, const char *parent,
++ void __iomem *reg, u8 shift);
++
+ struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
+ void __iomem *reg, u8 shift, u8 width,
+ void (*fixup)(u32 *val));
+@@ -86,12 +149,20 @@
+ shift, 0, &imx_ccm_lock);
+ }
+
++static inline struct clk *imx_clk_mux_bus(const char *name, void __iomem *reg,
++ u8 shift, u8 width, const char **parents, int num_parents)
++{
++ return clk_register_mux(NULL, name, parents, num_parents,
++ CLK_SET_RATE_NO_REPARENT,
++ reg, shift, width, 0, &imx_ccm_lock);
++}
++
+ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
+ u8 shift, u8 width, const char **parents, int num_parents)
+ {
+ return clk_register_mux(NULL, name, parents, num_parents,
+- CLK_SET_RATE_NO_REPARENT, reg, shift,
+- width, 0, &imx_ccm_lock);
++ CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
++ reg, shift, width, 0, &imx_ccm_lock);
+ }
+
+ static inline struct clk *imx_clk_mux_flags(const char *name,
+@@ -99,10 +170,28 @@
+ int num_parents, unsigned long flags)
+ {
+ return clk_register_mux(NULL, name, parents, num_parents,
+- flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
++ flags | CLK_SET_PARENT_GATE, reg, shift, width, 0,
+ &imx_ccm_lock);
+ }
+
++static inline struct clk *imx_clk_mux_flags_bus(const char *name,
++ void __iomem *reg, u8 shift, u8 width, const char **paretns,
++ int num_parents, unsigned long flags)
++{
++ return clk_register_mux(NULL, name, paretns, num_parents,
++ flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
++ width, 0, &imx_ccm_lock);
++}
++
++static inline struct clk *imx_clk_mux_glitchless(const char *name,
++ void __iomem *reg, u8 shift, u8 width, const char **parents,
++ int num_parents)
++{
++ return clk_register_mux(NULL, name, parents, num_parents,
++ 0, reg, shift,
++ width, 0, &imx_ccm_lock);
++}
++
+ static inline struct clk *imx_clk_fixed_factor(const char *name,
+ const char *parent, unsigned int mult, unsigned int div)
+ {
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-imx25.c linux-3.14.72/arch/arm/mach-imx/clk-imx25.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-imx25.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-imx25.c 2016-06-19 22:11:55.045157162 +0200
+@@ -312,8 +312,6 @@
+ int __init mx25_clocks_init_dt(void)
+ {
+ struct device_node *np;
+- void __iomem *base;
+- int irq;
+ unsigned long osc_rate = 24000000;
+
+ /* retrieve the freqency of fixed clocks from device tree */
+@@ -333,12 +331,7 @@
+
+ __mx25_clocks_init(osc_rate);
+
+- np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
+- base = of_iomap(np, 0);
+- WARN_ON(!base);
+- irq = irq_of_parse_and_map(np, 0);
+-
+- mxc_timer_init(base, irq);
++ mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
+
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-imx51-imx53.c linux-3.14.72/arch/arm/mach-imx/clk-imx51-imx53.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-imx51-imx53.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-imx51-imx53.c 2016-06-19 22:11:55.045157162 +0200
+@@ -324,9 +324,8 @@
+
+ static void __init mx50_clocks_init(struct device_node *np)
+ {
+- void __iomem *base;
+ unsigned long r;
+- int i, irq;
++ int i;
+
+ clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
+ clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
+@@ -374,11 +373,7 @@
+ r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
+ clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
+
+- np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
+- base = of_iomap(np, 0);
+- WARN_ON(!base);
+- irq = irq_of_parse_and_map(np, 0);
+- mxc_timer_init(base, irq);
++ mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
+ }
+ CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
+
+@@ -494,9 +489,8 @@
+
+ static void __init mx53_clocks_init(struct device_node *np)
+ {
+- int i, irq;
++ int i;
+ unsigned long r;
+- void __iomem *base;
+
+ clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
+ clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
+@@ -594,10 +588,6 @@
+ r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
+ clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
+
+- np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
+- base = of_iomap(np, 0);
+- WARN_ON(!base);
+- irq = irq_of_parse_and_map(np, 0);
+- mxc_timer_init(base, irq);
++ mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
+ }
+ CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-imx6q.c linux-3.14.72/arch/arm/mach-imx/clk-imx6q.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-imx6q.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-imx6q.c 2016-06-19 22:11:55.045157162 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011-2013 Freescale Semiconductor, Inc.
++ * Copyright 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -19,6 +19,7 @@
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <dt-bindings/clock/imx6qdl-clock.h>
+
+ #include "clk.h"
+ #include "common.h"
+@@ -31,7 +32,8 @@
+ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
+ static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
+ static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
+-static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
++static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
++static const char *axi_sels[] = { "periph", "axi_alt_sel", };
+ static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
+ static const char *gpu_axi_sels[] = { "axi", "ahb", };
+ static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
+@@ -39,6 +41,8 @@
+ static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
+ static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
+ static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
++static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
++static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
+ static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
+ static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+ static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
+@@ -63,7 +67,7 @@
+ "ipu2", "vdo_axi", "osc", "gpu2d_core",
+ "gpu3d_core", "usdhc2", "ssi1", "ssi2",
+ "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
+- "ldb_di0", "ldb_di1", "esai", "eim_slow",
++ "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
+ "uart_serial", "spdif", "asrc", "hsi_tx",
+ };
+ static const char *cko_sels[] = { "cko1", "cko2", };
+@@ -72,49 +76,23 @@
+ "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
+ "pcie_ref", "sata_ref",
+ };
+-
+-enum mx6q_clks {
+- dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
+- pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
+- pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
+- periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
+- esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
+- gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
+- ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
+- ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
+- ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
+- usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
+- emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
+- periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
+- asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
+- gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
+- ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
+- ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
+- ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
+- usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
+- emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
+- mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
+- can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
+- esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
+- hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
+- ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
+- mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
+- gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
+- ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
+- usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
+- pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
+- ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
+- sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
+- usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
+- spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
+- lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
+-};
+-
+-static struct clk *clk[clk_max];
++static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
++static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
++static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
++static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
++static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
++static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
++static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
++static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
++
++static struct clk *clk[IMX6QDL_CLK_END];
+ static struct clk_onecell_data clk_data;
+
+-static enum mx6q_clks const clks_init_on[] __initconst = {
+- mmdc_ch0_axi, rom, arm,
++static unsigned int const clks_init_on[] __initconst = {
++ IMX6QDL_CLK_MMDC_CH0_AXI,
++ IMX6QDL_CLK_ROM,
++ IMX6QDL_CLK_ARM,
++ IMX6QDL_CLK_OCRAM,
+ };
+
+ static struct clk_div_table clk_enet_ref_table[] = {
+@@ -140,17 +118,26 @@
+ { /* sentinel */ }
+ };
+
++static unsigned int share_count_esai;
++static unsigned int share_count_asrc;
++static unsigned int share_count_ssi1;
++static unsigned int share_count_ssi2;
++static unsigned int share_count_ssi3;
++static unsigned int share_count_spdif;
++
+ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ {
+ struct device_node *np;
+ void __iomem *base;
+- int i, irq;
+- int ret;
++ int i;
+
+- clk[dummy] = imx_clk_fixed("dummy", 0);
+- clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
+- clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
+- clk[osc] = imx_obtain_fixed_clock("osc", 0);
++ clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
++ clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
++ clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0);
++ clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
++ /* Clock source from external clock via CLK1/2 PADs */
++ clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
++ clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+ base = of_iomap(np, 0);
+@@ -164,43 +151,76 @@
+ video_div_table[3].div = 1;
+ }
+
+- /* type name parent_name base div_mask */
+- clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
+- clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
+- clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
+- clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
+- clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
+- clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
+- clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
+-
++ clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++
++ /* type name parent_name base div_mask */
++ clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
++ clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
++ clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
++ clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
++ clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
++ clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
++ clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
++
++ clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
++
++ /* Do not bypass PLLs initially */
++ imx_clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]);
++ imx_clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]);
++
++ clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
++ clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
++ clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
++ clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
++ clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
++ clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
++ clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
++
+ /*
+ * Bit 20 is the reserved and read-only bit, we do this only for:
+ * - Do nothing for usbphy clk_enable/disable
+ * - Keep refcount when do usbphy clk_enable/disable, in that case,
+ * the clk framework may need to enable/disable usbphy's parent
+ */
+- clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
+- clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
++ clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
++ clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
+
+ /*
+ * usbphy*_gate needs to be on after system boots up, and software
+ * never needs to control it anymore.
+ */
+- clk[usbphy1_gate] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
+- clk[usbphy2_gate] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
++ clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
++ clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
+
+- clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
+- clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
++ clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
++ clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
+
+- clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
+- clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
++ clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
++ clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+
+- clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
++ clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+ base + 0xe0, 0, 2, 0, clk_enet_ref_table,
+ &imx_ccm_lock);
+
+- clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+- clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
++ clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
++ clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
+
+ /*
+ * lvds1_gate and lvds2_gate are pseudo-gates. Both can be
+@@ -208,29 +228,38 @@
+ * the "output_enable" bit as a gate, even though it's really just
+ * enabling clock output.
+ */
+- clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
+- clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
++ clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
++ clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
++
++ clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
++ clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
++
++ /* name parent_name reg idx */
++ clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
++ clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
++ clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
++ clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
++ clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
++ clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
++ clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
++
++ /* name parent_name mult div */
++ clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
++ clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
++ clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
++ clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
++ clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
++ clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
++ clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
++ if (cpu_is_imx6dl()) {
++ clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi", 1, 1);
++ clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi", 1, 1);
++ }
+
+- /* name parent_name reg idx */
+- clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
+- clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
+- clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
+- clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
+- clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
+- clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
+- clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
+-
+- /* name parent_name mult div */
+- clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
+- clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
+- clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
+- clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
+- clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
+-
+- clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+- clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+- clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+- clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
++ clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
++ clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+
+ np = ccm_node;
+ base = of_iomap(np, 0);
+@@ -238,193 +267,212 @@
+
+ imx6q_pm_set_ccm_base(base);
+
+- /* name reg shift width parent_names num_parents */
+- clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
+- clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
+- clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
+- clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
+- clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
+- clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+- clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
+- clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
+- clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
+- clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
+- clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
+- clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
+- clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
+- clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
+- clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
+- clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+- clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
+- clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+- clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
+- clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
+- clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
+- clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
+- clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
+- clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
+- clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
+- clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
+- clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+- clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+- clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+- clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+- clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+- clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+- clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+- clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
+- clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
+- clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
+- clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
+- clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
+- clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
+- clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
+- clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
+-
+- /* name reg shift width busy: reg, shift parent_names num_parents */
+- clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
+- clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
+-
+- /* name parent_name reg shift width */
+- clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
+- clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
+- clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
+- clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
+- clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
+- clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
+- clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
+- clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
+- clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
+- clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
+- clk[can_root] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
+- clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
+- clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
+- clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
+- clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
+- clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
+- clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
+- clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+- clk[ldb_di0_podf] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
+- clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+- clk[ldb_di1_podf] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
+- clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
+- clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
+- clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
+- clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
+- clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
+- clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
+- clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
+- clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
+- clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
+- clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
+- clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
+- clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
+- clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
+- clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
+- clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
+- clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
+- clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
+- clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
+- clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
+- clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
+- clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
+- clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
+- clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
+-
+- /* name parent_name reg shift width busy: reg, shift */
+- clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
+- clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
+- clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
+- clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
+- clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
+-
+- /* name parent_name reg shift */
+- clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
+- clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
+- clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
+- clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
+- clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
+- clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
+- clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
+- clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
+- clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
+- clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
+- clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
+- clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
+- clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
+- clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
+- clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
++ /* name reg shift width parent_names num_parents */
++ clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
++ clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
++ clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
++ clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
++ clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
++ clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
++ clk[IMX6QDL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
++ clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux_glitchless("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels));
++ clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ if (cpu_is_imx6q()) {
++ clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
++ clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
++ }
++ clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
++ clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
++ clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
++ clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
++ clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
++ clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
++ clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
++ clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
++ clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
++ clk[IMX6QDL_CLK_EMI_SEL] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_EMI_SLOW_SEL] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
++ clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
++ clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
++ clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
++ clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
++
++ /* name reg shift width busy: reg, shift parent_names num_parents */
++ clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
++ clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
++
++ /* name parent_name reg shift width */
++ clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
++ clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
++ clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
++ clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
++ clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
++ clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
++ clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
++ clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
++ clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
++ clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
++ clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
++ clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
++ clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
++ clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
++ clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
++ clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
++ clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
++ clk[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
++ clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
++ clk[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
++ clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
++ clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
++ clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
++ clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
++ clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
++ clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
++ clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
++ clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
++ clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
++ clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
++ clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
++ clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
++ clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
++ clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
++ clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
++ clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
++ clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
++ clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
++ clk[IMX6QDL_CLK_EMI_PODF] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_EMI_SLOW_PODF] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
++ clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
++ clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
++ clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
++
++ /* name parent_name reg shift width busy: reg, shift */
++ clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
++ clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_busy_divider("mmdc_ch0_axi", "periph", base + 0x14, 19, 3, base + 0x48, 4);
++ clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_busy_divider("mmdc_ch1_axi", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
++ clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
++ clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
++
++ /* name parent_name reg shift */
++ clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
++ clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
++ clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
++ clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
++ clk[IMX6QDL_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
++ clk[IMX6QDL_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
++ clk[IMX6QDL_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
++ clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
++ clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
++ clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
++ clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
++ clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
++ clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
++ clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
++ clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
++ clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
++ clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
++ if (cpu_is_imx6dl())
++ clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
++ else
++ clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
++ clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
++ clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
++ clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
++ clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
++ clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
++ clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
+ if (cpu_is_imx6dl())
+ /*
+ * The multiplexer and divider of imx6q clock gpu3d_shader get
+ * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
+ */
+- clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
++ clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
+ else
+- clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
+- clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
+- clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
+- clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
+- clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
+- clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
+- clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
+- clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
+- clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
+- clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
+- clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
+- clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
+- clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
+- clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
+- clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
+- clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
+- clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
+- clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
+- clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
++ clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
++ clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
++ clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
++ clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
++ clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
++ clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
++ clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
++ clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
++ clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
++ clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
++ clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
++ clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
++ clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
++ clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
++ clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
++ clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
++ clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_div_sel", base + 0x74, 14);
++ clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
++ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
+ if (cpu_is_imx6dl())
+ /*
+ * The multiplexer and divider of the imx6q clock gpu2d get
+ * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
+ */
+- clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
++ clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
+ else
+- clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
+- clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
+- clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
+- clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
+- clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
+- clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
+- clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
+- clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
+- clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
+- clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
+- clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
+- clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
+- clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
+- clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
+- clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
+- clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
+- clk[sata] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
+- clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
+- clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
+- clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
+- clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
+- clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
+- clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
+- clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
+- clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
+- clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
+- clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
+- clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
+- clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
+- clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
+- clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
+- clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
+- clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
+- clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
+- clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
++ clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
++ clk[IMX6QDL_CLK_OCRAM] = imx_clk_busy_gate("ocram", "ahb", base + 0x74, 28);
++ clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
++ clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
++ clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
++ clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
++ clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
++ clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
++ clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
++ clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
++ clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
++ clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
++ clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
++ clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
++ clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
++ clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
++ clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
++ clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
++ clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
++ clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
++ clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
++ clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
++ clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
++ clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
++ clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
++ clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
++ clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
++ clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
++ clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
++ clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
++ clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
++ clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
++ clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
++ clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
++ clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
++ clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
++ clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
+
+ for (i = 0; i < ARRAY_SIZE(clk); i++)
+ if (IS_ERR(clk[i]))
+@@ -435,19 +483,30 @@
+ clk_data.clk_num = ARRAY_SIZE(clk);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+- clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
+- clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+- clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
+- clk_register_clkdev(clk[ahb], "ahb", NULL);
+- clk_register_clkdev(clk[cko1], "cko1", NULL);
+- clk_register_clkdev(clk[arm], NULL, "cpu0");
+- clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
+- clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
+-
+- if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
+- cpu_is_imx6dl()) {
+- clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
+- clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
++ clk_register_clkdev(clk[IMX6QDL_CLK_GPT_IPG], "ipg", "imx-gpt.0");
++ clk_register_clkdev(clk[IMX6QDL_CLK_GPT_IPG_PER], "per", "imx-gpt.0");
++ clk_register_clkdev(clk[IMX6QDL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0");
++ clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
++
++ /* ipu clock initialization */
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]);
++ /* set epdc/pxp axi clock to 200Mhz */
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_IPU2], 200000000);
++ if (cpu_is_imx6q()) {
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
+ }
+
+ /*
+@@ -455,40 +514,84 @@
+ * We can not get the 100MHz from the pll2_pfd0_352m.
+ * So choose pll2_pfd2_396m as enfc_sel's parent.
+ */
+- clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+-
+- for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+- clk_prepare_enable(clk[clks_init_on[i]]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
+
+- if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+- clk_prepare_enable(clk[usbphy1_gate]);
+- clk_prepare_enable(clk[usbphy2_gate]);
++ /* gpu clock initilazation */
++ /*
++ * On mx6dl, 2d core clock sources(sel, podf) is from 3d
++ * shader core clock, but 3d shader clock multiplexer of
++ * mx6dl is different. For instance the equivalent of
++ * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl.
++ * Make a note here.
++ */
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
++ if (cpu_is_imx6dl()) {
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 528000000);
++ /* for mx6dl, change gpu3d_core parent to 594_PFD*/
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]);
++ } else if (cpu_is_imx6q()) {
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]);
++ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 480000000);
+ }
+
+ /*
+ * Let's initially set up CLKO with OSC24M, since this configuration
+ * is widely used by imx6q board designs to clock audio codec.
+ */
+- ret = clk_set_parent(clk[cko2_sel], clk[osc]);
+- if (!ret)
+- ret = clk_set_parent(clk[cko], clk[cko2]);
+- if (ret)
+- pr_warn("failed to set up CLKO: %d\n", ret);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]);
+
+ /* Audio-related clocks configuration */
+- clk_set_parent(clk[spdif_sel], clk[pll3_pfd3_454m]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
+
+ /* All existing boards with PCIe use LVDS1 */
+ if (IS_ENABLED(CONFIG_PCI_IMX6))
+- clk_set_parent(clk[lvds1_sel], clk[sata_ref]);
++ imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF]);
++
++ /*
++ * Enable clocks only after both parent and rate are all initialized
++ * as needed
++ */
++ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
++ imx_clk_prepare_enable(clk[clks_init_on[i]]);
++
++ if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
++ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]);
++ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
++ }
++
++ /*Set enet_ref clock to 125M to supply for RGMII tx_clk */
++ clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000);
++
++ imx_clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]);
++
++ if (cpu_is_imx6dl())
++ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 306000000);
++ else
++ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 327000000);
++
++#ifdef CONFIG_MX6_VPU_352M
++ /*
++ * If VPU 352M is enabled, then PLL2_PDF2 need to be
++ * set to 352M, cpufreq will be disabled as VDDSOC/PU
++ * need to be at highest voltage, scaling cpu freq is
++ * not saving any power, and busfreq will be also disabled
++ * as the PLL2_PFD2 is not at default freq, in a word,
++ * all modules that sourceing clk from PLL2_PFD2 will
++ * be impacted.
++ */
++ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 352000000);
++ pr_info("VPU 352M is enabled!\n");
++#endif
+
+ /* Set initial power mode */
+ imx6q_set_lpm(WAIT_CLOCKED);
+
+- np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
+- base = of_iomap(np, 0);
+- WARN_ON(!base);
+- irq = irq_of_parse_and_map(np, 0);
+- mxc_timer_init(base, irq);
++ mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
+ }
+ CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-imx6sl.c linux-3.14.72/arch/arm/mach-imx/clk-imx6sl.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-imx6sl.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-imx6sl.c 2016-06-19 22:11:55.045157162 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -10,6 +10,7 @@
+ #include <linux/clk.h>
+ #include <linux/clkdev.h>
+ #include <linux/err.h>
++#include <linux/init.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+@@ -18,28 +19,64 @@
+ #include "clk.h"
+ #include "common.h"
+
+-static const char const *step_sels[] = { "osc", "pll2_pfd2", };
+-static const char const *pll1_sw_sels[] = { "pll1_sys", "step", };
+-static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
+-static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", };
+-static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+-static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
+-static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
+-static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
+-static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
+-static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+-static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
+-static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
+-static const char const *perclk_sels[] = { "ipg", "osc", };
+-static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+-static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+-static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+-static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+-static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+-static const char const *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+-static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
+-static const char const *uart_sels[] = { "pll3_80m", "osc", };
+-
++#define CCSR 0xc
++#define CCDR 0x04
++#define CCDR_CH0_HS_BYP 17
++#define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
++#define BM_CCSR_STEP_CLK_SEL (1 << 8)
++#define CACRR 0x10
++#define CDHIPR 0x48
++#define BM_CDHIPR_ARM_PODF_BUSY (1 << 16)
++#define ARM_WAIT_DIV_396M 2
++#define ARM_WAIT_DIV_792M 4
++#define ARM_WAIT_DIV_996M 6
++
++#define PLL_ARM 0x0
++#define BM_PLL_ARM_DIV_SELECT (0x7f << 0)
++#define BM_PLL_ARM_POWERDOWN (1 << 12)
++#define BM_PLL_ARM_ENABLE (1 << 13)
++#define BM_PLL_ARM_LOCK (1 << 31)
++#define PLL_ARM_DIV_792M 66
++
++static bool uart_from_osc;
++static const char *step_sels[] = { "osc", "pll2_pfd2", };
++static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
++static const char *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
++static const char *ocram_sels[] = { "periph", "ocram_alt_sel", };
++static const char *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
++static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
++static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
++static const char *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
++static const char *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
++static const char *csi_core_sels[] = { "osc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
++static const char *lcdif_axi_sels[] = { "pll2_bus", "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", };
++static const char *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
++static const char *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_audio_div", "dummy", };
++static const char *perclk_sels[] = { "ipg", "osc", };
++static const char *pxp_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd3", };
++static const char *epdc_axi_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd2", };
++static const char *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
++static const char *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
++static const char *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
++static const char *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
++static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
++static const char *ecspi_sels[] = { "pll3_60m", "osc", };
++static const char *uart_sels[] = { "pll3_80m", "uart_osc_4m", };
++static const char *lvds_sels[] = {
++ "pll1_sys", "pll2_bus", "pll2_pfd0", "pll2_pfd1", "pll2_pfd2", "dummy", "pll4_audio", "pll5_video",
++ "dummy", "enet_ref", "dummy", "dummy", "pll3_usb_otg", "pll7_usb_host", "pll3_pfd0", "pll3_pfd1",
++ "pll3_pfd2", "pll3_pfd3", "osc", "dummy", "dummy", "dummy", "dummy", "dummy",
++ "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
++};
++static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", };
++static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
++static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
++static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
++static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
++static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
++static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
++static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
++
+ static struct clk_div_table clk_enet_ref_table[] = {
+ { .val = 0, .div = 20, },
+ { .val = 1, .div = 10, },
+@@ -63,33 +100,160 @@
+ { }
+ };
+
++static unsigned int share_count_ssi1;
++static unsigned int share_count_ssi2;
++static unsigned int share_count_ssi3;
++static unsigned int share_count_spdif;
++
+ static struct clk *clks[IMX6SL_CLK_END];
+ static struct clk_onecell_data clk_data;
++static void __iomem *ccm_base;
++static void __iomem *anatop_base;
++
++static const u32 clks_init_on[] __initconst = {
++ IMX6SL_CLK_IPG, IMX6SL_CLK_ARM, IMX6SL_CLK_MMDC_ROOT,
++};
++
++extern int low_bus_freq_mode;
++/*
++ * ERR005311 CCM: After exit from WAIT mode, unwanted interrupt(s) taken
++ * during WAIT mode entry process could cause cache memory
++ * corruption.
++ *
++ * Software workaround:
++ * To prevent this issue from occurring, software should ensure that the
++ * ARM to IPG clock ratio is less than 12:5 (that is < 2.4x), before
++ * entering WAIT mode.
++ *
++ * This function will set the ARM clk to max value within the 12:5 limit.
++ * As IPG clock is fixed at 66MHz(so ARM freq must not exceed 158.4MHz),
++ * ARM freq are one of below setpoints: 396MHz, 792MHz and 996MHz, since
++ * the clk APIs can NOT be called in idle thread(may cause kernel schedule
++ * as there is sleep function in PLL wait function), so here we just slow
++ * down ARM to below freq according to previous freq:
++ *
++ * run mode wait mode
++ * 396MHz -> 132MHz;
++ * 792MHz -> 158.4MHz;
++ * 996MHz -> 142.3MHz;
++ */
++static int imx6sl_get_arm_divider_for_wait(void)
++{
++ if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) {
++ return ARM_WAIT_DIV_396M;
++ } else {
++ if ((readl_relaxed(anatop_base + PLL_ARM) &
++ BM_PLL_ARM_DIV_SELECT) == PLL_ARM_DIV_792M)
++ return ARM_WAIT_DIV_792M;
++ else
++ return ARM_WAIT_DIV_996M;
++ }
++}
++
++void imx6sl_set_wait_clk(bool enter)
++{
++ static unsigned long saved_arm_div;
++ u32 val;
++ int arm_div_for_wait = imx6sl_get_arm_divider_for_wait();
++
++ if (enter) {
++ /*
++ * If in this mode, the IPG clock is at 12MHz, we can
++ * only run ARM at a max 28.8MHz, so we need to run
++ * from the 24MHz OSC, as there is no way to get
++ * 28.8MHz, when ARM is sourced from PLl1.
++ */
++ if (low_bus_freq_mode) {
++ val = readl_relaxed(ccm_base + CCSR);
++ val |= BM_CCSR_PLL1_SW_CLK_SEL;
++ writel_relaxed(val, ccm_base + CCSR);
++ } else {
++ saved_arm_div = readl_relaxed(ccm_base + CACRR);
++ writel_relaxed(arm_div_for_wait, ccm_base + CACRR);
++ }
++ } else {
++ if (low_bus_freq_mode) {
++ val = readl_relaxed(ccm_base + CCSR);
++ val &= ~BM_CCSR_PLL1_SW_CLK_SEL;
++ writel_relaxed(val, ccm_base + CCSR);
++ } else {
++ writel_relaxed(saved_arm_div, ccm_base + CACRR);
++ }
++ }
++ while (__raw_readl(ccm_base + CDHIPR) & BM_CDHIPR_ARM_PODF_BUSY)
++ ;
++}
++
++static int __init setup_uart_clk(char *uart_rate)
++{
++ uart_from_osc = true;
++ return 1;
++}
++__setup("uart_at_4M", setup_uart_clk);
+
+ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
+ {
+ struct device_node *np;
+ void __iomem *base;
+- int irq;
+- int i;
++ int i, reg;
+
+ clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+ clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
+ clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
++ /* Clock source from external clock via CLK1 PAD */
++ clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
++ anatop_base = base;
+
+- /* type name parent base div_mask */
+- clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
+- clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
+- clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
+- clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
+- clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
+- clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
+- clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
+-
++ clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++
++ /* type name parent_name base div_mask */
++ clks[IMX6SL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
++ clks[IMX6SL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
++ clks[IMX6SL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
++ clks[IMX6SL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
++ clks[IMX6SL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
++ clks[IMX6SL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
++ clks[IMX6SL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
++
++ clks[IMX6SL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_PLL2_BYPASS] = imx_clk_mux_flags_bus("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
++
++ /* Do not bypass PLLs initially */
++ imx_clk_set_parent(clks[IMX6SL_PLL1_BYPASS], clks[IMX6SL_CLK_PLL1]);
++ imx_clk_set_parent(clks[IMX6SL_PLL2_BYPASS], clks[IMX6SL_CLK_PLL2]);
++ imx_clk_set_parent(clks[IMX6SL_PLL3_BYPASS], clks[IMX6SL_CLK_PLL3]);
++ imx_clk_set_parent(clks[IMX6SL_PLL4_BYPASS], clks[IMX6SL_CLK_PLL4]);
++ imx_clk_set_parent(clks[IMX6SL_PLL5_BYPASS], clks[IMX6SL_CLK_PLL5]);
++ imx_clk_set_parent(clks[IMX6SL_PLL6_BYPASS], clks[IMX6SL_CLK_PLL6]);
++ imx_clk_set_parent(clks[IMX6SL_PLL7_BYPASS], clks[IMX6SL_CLK_PLL7]);
++
++ clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
++ clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
++ clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
++ clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
++ clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
++ clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
++ clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
++
++ clks[IMX6SL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
++ clks[IMX6SL_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
++ clks[IMX6SL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
++
+ /*
+ * usbphy1 and usbphy2 are implemented as dummy gates using reserve
+ * bit 20. They are used by phy driver to keep the refcount of
+@@ -103,10 +267,10 @@
+ clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
+
+ /* dev name parent_name flags reg shift width div: flags, div_table lock */
+- clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+- clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+- clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+- clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
++ clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clks[IMX6SL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
++ clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+ clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
+
+ /* name parent_name reg idx */
+@@ -123,25 +287,27 @@
+ clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
+ clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
+ clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
++ clks[IMX6SL_CLK_UART_OSC_4M] = imx_clk_fixed_factor("uart_osc_4m", "osc", 1, 6);
+
+ np = ccm_node;
+ base = of_iomap(np, 0);
+ WARN_ON(!base);
++ ccm_base = base;
+
+ /* Reuse imx6q pm code */
+ imx6q_pm_set_ccm_base(base);
+
+ /* name reg shift width parent_names num_parents */
+ clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
+- clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
++ clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
+ clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
+- clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
+- clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
+- clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
+- clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+- clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
+- clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
+- clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
++ clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux_glitchless("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
++ clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux_bus("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
++ clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux_bus("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
++ clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux_bus("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
++ clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
++ clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_core_sels, ARRAY_SIZE(csi_core_sels));
++ clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, lcdif_axi_sels, ARRAY_SIZE(lcdif_axi_sels));
+ clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+ clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+ clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
+@@ -150,12 +316,12 @@
+ clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+ clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
+ clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
+- clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
+- clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
++ clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, pxp_axi_sels, ARRAY_SIZE(pxp_axi_sels));
++ clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_axi_sels, ARRAY_SIZE(epdc_axi_sels));
+ clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
+ clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
+- clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
+- clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels));
++ clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux_flags("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux_flags("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels), CLK_SET_RATE_PARENT);
+ clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
+ clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
+ clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
+@@ -167,7 +333,7 @@
+ clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
+
+ /* name parent_name reg shift width */
+- clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3);
++ clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
+ clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
+ clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
+ clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
+@@ -227,17 +393,21 @@
+ clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6);
+ clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8);
+ clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10);
+- clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
++ clks[IMX6SL_CLK_OCRAM] = imx_clk_busy_gate("ocram", "ocram_podf", base + 0x74, 28);
+ clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
+ clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
+ clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
+ clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
+ clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
+ clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
+- clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
+- clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
+- clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
+- clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
++ clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif);
++ clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
++ clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
++ clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
++ clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
++ clks[IMX6SL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
++ clks[IMX6SL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
++ clks[IMX6SL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
+ clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
+ clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
+ clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
+@@ -255,24 +425,75 @@
+ clk_data.clk_num = ARRAY_SIZE(clks);
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
++ /* Ensure that CH0 handshake is bypassed */
++ reg = readl_relaxed(base + CCDR);
++ reg |= 1 << CCDR_CH0_HS_BYP;
++ writel_relaxed(reg, base + CCDR);
++
+ clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
+ clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+
+- if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+- clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+- clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+- }
++ /* Ensure the AHB clk is at 132MHz. */
++ imx_clk_set_rate(clks[IMX6SL_CLK_AHB], 132000000);
++
++ /* set perclk to source from OSC 24MHz */
++ imx_clk_set_parent(clks[IMX6SL_CLK_PERCLK_SEL], clks[IMX6SL_CLK_OSC]);
+
+ /* Audio-related clocks configuration */
+- clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
++ imx_clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
++
++ /* Configure pxp clocks */
++ imx_clk_set_parent(clks[IMX6SL_CLK_PXP_AXI_SEL], clks[IMX6SL_CLK_PLL2_PFD2]);
++ imx_clk_set_rate(clks[IMX6SL_CLK_PXP_AXI], 200000000);
++
++ /* Initialize Video PLLs to valid frequency (650MHz). */
++ imx_clk_set_rate(clks[IMX6SL_CLK_PLL5_VIDEO_DIV], 650000000);
++ /* set PLL5 video as lcdif pix parent clock */
++ imx_clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL],
++ clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
++
++ /* Set the UART parent if needed */
++ if (uart_from_osc)
++ imx_clk_set_parent(clks[IMX6SL_CLK_UART_SEL], clks[IMX6SL_CLK_UART_OSC_4M]);
++ /*
++ * Enable clocks only after both parent and rate are all initialized
++ * as needed
++ */
++
++ /*
++ * Make sure those always on clocks are enabled to maintain the correct
++ * usecount and enabling/disabling of parent PLLs.
++ */
++ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
++ imx_clk_prepare_enable(clks[clks_init_on[i]]);
++
++ /*
++ * Make sure the OCRAM clk is enabled to maintain the correct usecount
++ * and enabling/disabling of parent PLLs.
++ */
++ imx_clk_prepare_enable(clks[IMX6SL_CLK_OCRAM]);
++
++ if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
++ imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
++ imx_clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
++ }
+
+ /* Set initial power mode */
+ imx6q_set_lpm(WAIT_CLOCKED);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
+- base = of_iomap(np, 0);
+- WARN_ON(!base);
+- irq = irq_of_parse_and_map(np, 0);
+- mxc_timer_init(base, irq);
++ mxc_timer_init_dt(np);
++
++ /* Configure EPDC clocks */
++ clk_set_parent(clks[IMX6SL_CLK_EPDC_PIX_SEL],
++ clks[IMX6SL_CLK_PLL5_VIDEO_DIV]);
++ clk_set_parent(clks[IMX6SL_CLK_EPDC_AXI_SEL],
++ clks[IMX6SL_CLK_PLL2_PFD2]);
++ clk_set_rate(clks[IMX6SL_CLK_EPDC_AXI], 200000000);
++
++ /* Configure LCDIF clocks */
++ clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
++ clks[IMX6SL_CLK_PLL2_PFD2]);
++ clk_set_rate(clks[IMX6SL_CLK_LCDIF_AXI], 200000000);
+ }
+ CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-imx6sx.c linux-3.14.72/arch/arm/mach-imx/clk-imx6sx.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-imx6sx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/clk-imx6sx.c 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,739 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <dt-bindings/clock/imx6sx-clock.h>
++#include <linux/clk.h>
++#include <linux/clkdev.h>
++#include <linux/err.h>
++#include <linux/imx_sema4.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/types.h>
++
++#include "clk.h"
++#include "common.h"
++
++#define CCM_CCGR_OFFSET(index) (index * 2)
++#define CCDR 0x4
++#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
++
++static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
++static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
++static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
++static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
++static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
++static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
++static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
++static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
++static const char *ocram_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
++static const char *ocram_sels[] = { "periph", "ocram_alt_sel", };
++static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
++static const char *gpu_axi_sels[] = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
++static const char *gpu_core_sels[] = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
++static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
++static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
++static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
++static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
++static const char *pcie_axi_sels[] = { "axi", "ahb", };
++static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
++static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
++static const char *perclk_sels[] = { "ipg", "osc", };
++static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
++static const char *vid_sels[] = { "pll3_pfd1_540m", "pll3_usb_otg", "pll3_pfd3_454m", "pll4_audio_div", "pll5_video_div", };
++static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
++static const char *uart_sels[] = { "pll3_80m", "osc", };
++static const char *qspi2_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
++static const char *enet_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
++static const char *enet_sels[] = { "enet_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
++static const char *m4_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "osc", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd3_454m", };
++static const char *m4_sels[] = { "m4_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
++static const char *eim_slow_sels[] = { "ocram", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
++static const char *ecspi_sels[] = { "pll3_60m", "osc", };
++static const char *lcdif1_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
++static const char *lcdif1_sels[] = { "lcdif1_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
++static const char *lcdif2_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd3_594m", "pll3_pfd1_540m", };
++static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
++static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
++static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
++static const char *cko1_sels[] = {
++ "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
++ "dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",
++ "epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
++};
++static const char *cko2_sels[] = {
++ "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
++ "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
++ "lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",
++ "usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",
++ "dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial",
++ "spdif", "asrc", "dummy",
++};
++static const char *cko_sels[] = { "cko1", "cko2", };
++static const char *lvds_sels[] = {
++ "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
++ "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
++};
++static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
++static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
++static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
++static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
++static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
++static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
++static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
++static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
++
++static struct clk *clks[IMX6SX_CLK_CLK_END];
++static struct clk_onecell_data clk_data;
++struct imx_sema4_mutex *amp_power_mutex;
++
++static int clks_shared[MAX_SHARED_CLK_NUMBER];
++
++struct imx_shared_mem *shared_mem;
++static unsigned int shared_mem_paddr, shared_mem_size;
++
++static int const clks_init_on[] __initconst = {
++ IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3,
++ IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
++ IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
++ IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
++ IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK,
++};
++
++static struct clk_div_table clk_enet_ref_table[] = {
++ { .val = 0, .div = 20, },
++ { .val = 1, .div = 10, },
++ { .val = 2, .div = 5, },
++ { .val = 3, .div = 4, },
++ { }
++};
++
++static struct clk_div_table post_div_table[] = {
++ { .val = 2, .div = 1, },
++ { .val = 1, .div = 2, },
++ { .val = 0, .div = 4, },
++ { }
++};
++
++static struct clk_div_table video_div_table[] = {
++ { .val = 0, .div = 1, },
++ { .val = 1, .div = 2, },
++ { .val = 2, .div = 1, },
++ { .val = 3, .div = 4, },
++ { }
++};
++
++static u32 share_count_asrc;
++static u32 share_count_audio;
++static u32 share_count_esai;
++static u32 share_count_ssi1;
++static u32 share_count_ssi2;
++static u32 share_count_ssi3;
++static u32 share_count_sai1;
++static u32 share_count_sai2;
++static bool uart_from_osc;
++
++/*
++ * As IMX6SX_CLK_M4_PRE_SEL is NOT a glitchless MUX, so when
++ * M4 is trying to change its clk parent, need to ask A9 to
++ * help do it, and M4 must be hold in wfi. To avoid glitch
++ * occur, need to gate M4 clk first before switching its parent.
++ */
++void imx6sx_set_m4_highfreq(bool high_freq)
++{
++ static struct clk *m4_high_freq_sel;
++
++ imx_gpc_hold_m4_in_sleep();
++
++ clk_disable_unprepare(clks[IMX6SX_CLK_M4]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_M4_SEL],
++ clks[IMX6SX_CLK_LDB_DI0]);
++
++ if (high_freq) {
++ imx_clk_set_parent(clks[IMX6SX_CLK_M4_PRE_SEL],
++ m4_high_freq_sel);
++ } else {
++ m4_high_freq_sel = clk_get_parent(clks[IMX6SX_CLK_M4_PRE_SEL]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_M4_PRE_SEL],
++ clks[IMX6SX_CLK_OSC]);
++ }
++
++ imx_clk_set_parent(clks[IMX6SX_CLK_M4_SEL],
++ clks[IMX6SX_CLK_M4_PRE_SEL]);
++ clk_prepare_enable(clks[IMX6SX_CLK_M4]);
++
++ imx_gpc_release_m4_in_sleep();
++}
++
++static int __init setup_uart_clk(char *uart_rate)
++{
++ uart_from_osc = true;
++ return 1;
++}
++__setup("uart_from_osc", setup_uart_clk);
++
++static void __init imx6sx_clocks_init(struct device_node *ccm_node)
++{
++ struct device_node *np;
++ void __iomem *base;
++ int i;
++
++ clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
++
++ clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
++ clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
++
++ /* ipp_di clock is external input */
++ clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
++ clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
++
++ /* Clock source from external clock via CLK1 PAD */
++ clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0);
++ clks[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0);
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
++ base = of_iomap(np, 0);
++ WARN_ON(!base);
++
++ clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++ clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
++
++ /* type name parent_name base div_mask */
++ clks[IMX6SX_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f);
++ clks[IMX6SX_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1);
++ clks[IMX6SX_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3);
++ clks[IMX6SX_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f);
++ clks[IMX6SX_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f);
++ clks[IMX6SX_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3);
++ clks[IMX6SX_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3);
++
++ clks[IMX6SX_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
++
++ /* Do not bypass PLLs initially */
++ imx_clk_set_parent(clks[IMX6SX_PLL1_BYPASS], clks[IMX6SX_CLK_PLL1]);
++ imx_clk_set_parent(clks[IMX6SX_PLL2_BYPASS], clks[IMX6SX_CLK_PLL2]);
++ imx_clk_set_parent(clks[IMX6SX_PLL3_BYPASS], clks[IMX6SX_CLK_PLL3]);
++ imx_clk_set_parent(clks[IMX6SX_PLL4_BYPASS], clks[IMX6SX_CLK_PLL4]);
++ imx_clk_set_parent(clks[IMX6SX_PLL5_BYPASS], clks[IMX6SX_CLK_PLL5]);
++ imx_clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]);
++ imx_clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]);
++
++ clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1);
++ clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
++ clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
++ clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
++ clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
++ clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
++ clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
++
++ /*
++ * Bit 20 is the reserved and read-only bit, we do this only for:
++ * - Do nothing for usbphy clk_enable/disable
++ * - Keep refcount when do usbphy clk_enable/disable, in that case,
++ * the clk framework may need to enable/disable usbphy's parent
++ */
++ clks[IMX6SX_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
++ clks[IMX6SX_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
++
++ /*
++ * usbphy*_gate needs to be on after system boots up, and software
++ * never needs to control it anymore.
++ */
++ clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
++ clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
++
++ /* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */
++ clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
++ clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
++
++ clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x160, 10, BIT(12));
++ clks[IMX6SX_CLK_LVDS2_OUT] = imx_clk_gate_exclusive("lvds2_out", "lvds2_sel", base + 0x160, 11, BIT(13));
++ clks[IMX6SX_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
++ clks[IMX6SX_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
++
++ clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
++ base + 0xe0, 0, 2, 0, clk_enet_ref_table,
++ &imx_ccm_lock);
++ clks[IMX6SX_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
++ base + 0xe0, 2, 2, 0, clk_enet_ref_table,
++ &imx_ccm_lock);
++ clks[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
++
++ clks[IMX6SX_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
++ clks[IMX6SX_CLK_ENET_PTP] = imx_clk_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21);
++
++ /* name parent_name reg idx */
++ clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
++ clks[IMX6SX_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
++ clks[IMX6SX_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
++ clks[IMX6SX_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
++ clks[IMX6SX_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
++ clks[IMX6SX_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
++ clks[IMX6SX_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
++ clks[IMX6SX_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
++
++ /* name parent_name mult div */
++ clks[IMX6SX_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
++ clks[IMX6SX_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
++ clks[IMX6SX_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
++ clks[IMX6SX_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
++ clks[IMX6SX_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
++ clks[IMX6SX_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
++
++ clks[IMX6SX_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
++ CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clks[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
++ CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
++ clks[IMX6SX_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
++ CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
++ clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
++ CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
++
++ /* name reg shift width parent_names num_parents */
++ clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
++ clks[IMX6SX_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
++
++ np = ccm_node;
++ base = of_iomap(np, 0);
++ WARN_ON(!base);
++
++ imx6q_pm_set_ccm_base(base);
++
++ /* name reg shift width parent_names num_parents */
++ clks[IMX6SX_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
++ clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux_glitchless("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
++ clks[IMX6SX_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
++ clks[IMX6SX_CLK_OCRAM_SEL] = imx_clk_mux_glitchless("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
++ clks[IMX6SX_CLK_PERIPH_PRE] = imx_clk_mux_bus("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
++ clks[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_mux_bus("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
++ clks[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_mux_bus("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
++ clks[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux_bus("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
++ clks[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
++ clks[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
++ clks[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels));
++ clks[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
++ clks[IMX6SX_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
++ clks[IMX6SX_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
++ clks[IMX6SX_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
++ clks[IMX6SX_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
++ clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
++ clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
++ clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
++ clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
++ clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
++ clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels));
++ clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
++ clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
++ clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels));
++ clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ clks[IMX6SX_CLK_AUDIO_SEL] = imx_clk_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
++ clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels));
++ clks[IMX6SX_CLK_ENET_SEL] = imx_clk_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels));
++ clks[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels));
++ clks[IMX6SX_CLK_M4_SEL] = imx_clk_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels));
++ clks[IMX6SX_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
++ clks[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels));
++ clks[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels));
++ clks[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels));
++ clks[IMX6SX_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
++ clks[IMX6SX_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
++ clks[IMX6SX_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
++ clks[IMX6SX_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
++
++ clks[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);
++ clks[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT);
++
++ /* name parent_name reg shift width */
++ clks[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
++ clks[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
++ clks[IMX6SX_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
++ clks[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3);
++ clks[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3);
++ clks[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_divider("lcdif1_podf", "lcdif1_pred", base + 0x18, 23, 3);
++ clks[IMX6SX_CLK_QSPI1_PODF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
++ clks[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
++ clks[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3);
++ clks[IMX6SX_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
++ clks[IMX6SX_CLK_VID_PODF] = imx_clk_divider("vid_podf", "vid_sel", base + 0x20, 24, 2);
++ clks[IMX6SX_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6);
++ clks[IMX6SX_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
++ clks[IMX6SX_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
++ clks[IMX6SX_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
++ clks[IMX6SX_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
++ clks[IMX6SX_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
++ clks[IMX6SX_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
++ clks[IMX6SX_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
++ clks[IMX6SX_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
++ clks[IMX6SX_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
++ clks[IMX6SX_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
++ clks[IMX6SX_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
++ clks[IMX6SX_CLK_QSPI2_PRED] = imx_clk_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3);
++ clks[IMX6SX_CLK_QSPI2_PODF] = imx_clk_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6);
++ clks[IMX6SX_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
++ clks[IMX6SX_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
++ clks[IMX6SX_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
++ clks[IMX6SX_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
++ clks[IMX6SX_CLK_AUDIO_PRED] = imx_clk_divider("audio_pred", "audio_sel", base + 0x30, 12, 3);
++ clks[IMX6SX_CLK_AUDIO_PODF] = imx_clk_divider("audio_podf", "audio_pred", base + 0x30, 9, 3);
++ clks[IMX6SX_CLK_ENET_PODF] = imx_clk_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3);
++ clks[IMX6SX_CLK_M4_PODF] = imx_clk_divider("m4_podf", "m4_sel", base + 0x34, 3, 3);
++ clks[IMX6SX_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
++ clks[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_divider("lcdif1_pred", "lcdif1_pre_sel", base + 0x38, 12, 3);
++ clks[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_divider("lcdif2_pred", "lcdif2_pre_sel", base + 0x38, 3, 3);
++ clks[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_divider("display_podf", "display_sel", base + 0x3c, 16, 3);
++ clks[IMX6SX_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
++ clks[IMX6SX_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
++ clks[IMX6SX_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
++
++ clks[IMX6SX_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
++ clks[IMX6SX_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
++ clks[IMX6SX_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
++ clks[IMX6SX_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
++
++ /* name reg shift width busy: reg, shift parent_names num_parents */
++ clks[IMX6SX_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
++ clks[IMX6SX_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
++ /* name parent_name reg shift width busy: reg, shift */
++ clks[IMX6SX_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
++ clks[IMX6SX_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
++ clks[IMX6SX_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
++ clks[IMX6SX_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
++
++ /* name parent_name reg shift */
++ /* CCGR0 */
++ clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
++ clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
++ clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
++ clks[IMX6SX_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
++ clks[IMX6SX_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
++ clks[IMX6SX_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
++ clks[IMX6SX_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
++ clks[IMX6SX_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
++ clks[IMX6SX_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
++ clks[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
++ clks[IMX6SX_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
++ clks[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
++ clks[IMX6SX_CLK_DCIC1] = imx_clk_gate2("dcic1", "display_podf", base + 0x68, 24);
++ clks[IMX6SX_CLK_DCIC2] = imx_clk_gate2("dcic2", "display_podf", base + 0x68, 26);
++ clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
++
++ /* CCGR1 */
++ clks[IMX6SX_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
++ clks[IMX6SX_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
++ clks[IMX6SX_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
++ clks[IMX6SX_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
++ clks[IMX6SX_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8);
++ clks[IMX6SX_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
++ clks[IMX6SX_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
++ clks[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
++ clks[IMX6SX_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
++ clks[IMX6SX_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
++ clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18);
++ clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20);
++ clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
++ clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26);
++ clks[IMX6SX_CLK_CANFD] = imx_clk_gate2("canfd", "can_podf", base + 0x6c, 30);
++
++ /* CCGR2 */
++ clks[IMX6SX_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2);
++ clks[IMX6SX_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
++ clks[IMX6SX_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
++ clks[IMX6SX_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
++ clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
++ clks[IMX6SX_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14);
++ clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2("ipmux1", "ahb", base + 0x70, 16);
++ clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2("ipmux2", "ahb", base + 0x70, 18);
++ clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2("ipmux3", "ahb", base + 0x70, 20);
++ clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2("tzasc1", "mmdc_podf", base + 0x70, 22);
++ clks[IMX6SX_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "display_podf", base + 0x70, 28);
++ clks[IMX6SX_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "display_podf", base + 0x70, 30);
++
++ /* CCGR3 */
++ clks[IMX6SX_CLK_M4] = imx_clk_gate2("m4", "m4_podf", base + 0x74, 2);
++ clks[IMX6SX_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4);
++ clks[IMX6SX_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "enet_sel", base + 0x74, 4);
++ clks[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_gate2("display_axi", "display_podf", base + 0x74, 6);
++ clks[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_gate2("lcdif2_pix", "lcdif2_sel", base + 0x74, 8);
++ clks[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_gate2("lcdif1_pix", "lcdif1_sel", base + 0x74, 10);
++ clks[IMX6SX_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
++ clks[IMX6SX_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
++ clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18);
++ clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_busy_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
++ clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
++ clks[IMX6SX_CLK_OCRAM] = imx_clk_busy_gate("ocram", "ocram_podf", base + 0x74, 28);
++
++ /* CCGR4 */
++ clks[IMX6SX_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "display_podf", base + 0x78, 0);
++ clks[IMX6SX_CLK_QSPI2] = imx_clk_gate2("qspi2", "qspi2_podf", base + 0x78, 10);
++ clks[IMX6SX_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
++ clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
++ clks[IMX6SX_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
++ clks[IMX6SX_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
++ clks[IMX6SX_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
++ clks[IMX6SX_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
++ clks[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
++ clks[IMX6SX_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
++ clks[IMX6SX_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28);
++ clks[IMX6SX_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
++
++ /* CCGR5 */
++ clks[IMX6SX_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
++ clks[IMX6SX_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
++ clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
++ clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
++ clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
++ clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
++ clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
++ clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
++ clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
++ clks[IMX6SX_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
++ clks[IMX6SX_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
++ clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
++ clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
++ clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
++ clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1);
++ clks[IMX6SX_CLK_SAI2_IPG] = imx_clk_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2);
++ clks[IMX6SX_CLK_SAI1] = imx_clk_gate2_shared("sai1", "ssi1_podf", base + 0x7c, 28, &share_count_sai1);
++ clks[IMX6SX_CLK_SAI2] = imx_clk_gate2_shared("sai2", "ssi2_podf", base + 0x7c, 30, &share_count_sai2);
++
++ /* CCGR6 */
++ clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
++ clks[IMX6SX_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
++ clks[IMX6SX_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
++ clks[IMX6SX_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
++ clks[IMX6SX_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
++ clks[IMX6SX_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
++ clks[IMX6SX_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16);
++ clks[IMX6SX_CLK_VADC] = imx_clk_gate2("vadc", "vid_podf", base + 0x80, 20);
++ clks[IMX6SX_CLK_GIS] = imx_clk_gate2("gis", "display_podf", base + 0x80, 22);
++ clks[IMX6SX_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24);
++ clks[IMX6SX_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26);
++ clks[IMX6SX_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
++ clks[IMX6SX_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30);
++
++ clks[IMX6SX_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
++ clks[IMX6SX_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
++
++ /* get those shared clk nodes if M4 is active */
++ if (imx_src_is_m4_enabled()) {
++ u32 num;
++ of_property_read_u32(np, "fsl,shared-clks-number", &num);
++ if (num > MAX_SHARED_CLK_NUMBER)
++ pr_err("clk: shared clk nodes exceed the max number!\n");
++ of_property_read_u32_array(np, "fsl,shared-clks-index",
++ clks_shared, num);
++ if (of_property_read_u32(np, "fsl,shared-mem-addr",
++ &shared_mem_paddr))
++ pr_err("clk: fsl,shared-mem-addr NOT found!\n");
++ if (of_property_read_u32(np, "fsl,shared-mem-size",
++ &shared_mem_size))
++ pr_err("clk: fsl,shared-mem-size NOT found!\n");
++ }
++
++ /* mask handshake of mmdc */
++ writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
++
++ for (i = 0; i < ARRAY_SIZE(clks); i++)
++ if (IS_ERR(clks[i]))
++ pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
++
++ /*
++ * QSPI2/GPMI_IO share the same clock source but with the
++ * different gate, need explicitely gate the QSPI2 & GPMI_IO
++ * during the clock init phase according to the SOC design.
++ */
++ if (!imx_src_is_m4_enabled()) {
++ writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78);
++ writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78);
++ }
++ clk_data.clks = clks;
++ clk_data.clk_num = ARRAY_SIZE(clks);
++ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
++
++ /*
++ * As some of the modules need to access ocotp in MSL,
++ * need to make sure ocotp clk(CCM_CCGR2_CG6) is enabled
++ * during MSL, as on i.MX6SX, accessing OCOTP registers
++ * needs its clk on, it will be disabled by clk late
++ * init and managed by ocotp driver.
++ */
++ writel_relaxed(readl_relaxed(base + 0x70) | 1 << 12, base + 0x70);
++
++ clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
++ clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
++ clk_register_clkdev(clks[IMX6SX_CLK_GPT_3M], "gpt_3m", "imx-gpt.0");
++
++ /* maintain M4 usecount */
++ if (imx_src_is_m4_enabled())
++ imx_clk_prepare_enable(clks[IMX6SX_CLK_M4]);
++
++ /* set perclk to from OSC */
++ imx_clk_set_parent(clks[IMX6SX_CLK_PERCLK_SEL], clks[IMX6SX_CLK_OSC]);
++
++ /* Set the default 132MHz for EIM module */
++ imx_clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
++ imx_clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
++
++ /* set parent clock for LCDIF1 pixel clock */
++ imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
++
++ /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
++ imx_clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]);
++
++ /*
++ * Init enet system AHB clock, set to 200Mhz
++ * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
++ */
++ imx_clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
++ imx_clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
++ imx_clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
++ imx_clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
++
++ /* Audio clocks */
++ imx_clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
++
++ imx_clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
++ imx_clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
++
++ imx_clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
++ imx_clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
++
++ imx_clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
++ imx_clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
++ imx_clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
++ imx_clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
++
++ imx_clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
++ imx_clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
++
++ /* Set parent clock for vadc */
++ imx_clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
++
++ /* Update gpu clock from default 528M to 720M */
++ imx_clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
++
++ /* Set the UART parent if needed. */
++ if (uart_from_osc)
++ imx_clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_OSC]);
++ else
++ imx_clk_set_parent(clks[IMX6SX_CLK_UART_SEL], clks[IMX6SX_CLK_PLL3_80M]);
++
++ /* pll2_bus is the best parent of QSPI clock */
++ imx_clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
++ imx_clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
++
++ if (!imx_src_is_m4_enabled())
++ /* default parent of can_sel clock is invalid, manually set it here */
++ imx_clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
++ /*
++ * Enable clocks only after both parent and rate are all initialized
++ * as needed
++ */
++ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
++ imx_clk_prepare_enable(clks[clks_init_on[i]]);
++
++ if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
++ imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
++ imx_clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
++ }
++
++ /* Set initial power mode */
++ imx6q_set_lpm(WAIT_CLOCKED);
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
++ mxc_timer_init_dt(np);
++}
++CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
++
++int imx_update_shared_mem(struct clk_hw *hw, bool enable)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(clks_shared); i++) {
++ if (shared_mem->imx_clk[i].self == hw->clk)
++ break;
++ }
++
++ if (i >= ARRAY_SIZE(clks_shared))
++ return 1;
++
++ /* update ca9 clk status in shared memory */
++ if (enable)
++ shared_mem->imx_clk[i].ca9_enabled = 1;
++ else
++ shared_mem->imx_clk[i].ca9_enabled = 0;
++
++ if (shared_mem->imx_clk[i].cm4_enabled == 0)
++ return 1;
++
++ return 0;
++}
++
++static int __init imx_amp_power_init(void)
++{
++ int i;
++ void __iomem *shared_mem_base;
++
++ if (!imx_src_is_m4_enabled())
++ return 0;
++
++ amp_power_mutex = imx_sema4_mutex_create(0, MCC_POWER_SHMEM_NUMBER);
++
++ shared_mem_base = ioremap_nocache(shared_mem_paddr, shared_mem_size);
++
++ if (!amp_power_mutex) {
++ pr_err("Failed to create sema4 mutex!\n");
++ return 0;
++ }
++
++ shared_mem = (struct imx_shared_mem *)shared_mem_base;
++
++ for (i = 0; i < ARRAY_SIZE(clks_shared); i++) {
++ shared_mem->imx_clk[i].self = clks[clks_shared[i]];
++ shared_mem->imx_clk[i].ca9_enabled = 1;
++ pr_debug("%d: name %s, addr 0x%x\n", i,
++ __clk_get_name(shared_mem->imx_clk[i].self),
++ (u32)&(shared_mem->imx_clk[i]));
++ }
++ /* enable amp power management */
++ shared_mem->ca9_valid = SHARED_MEM_MAGIC_NUMBER;
++
++ pr_info("A9-M4 sema4 num %d, A9-M4 magic number 0x%x - 0x%x.\n",
++ amp_power_mutex->gate_num, shared_mem->ca9_valid,
++ shared_mem->cm4_valid);
++
++ return 0;
++}
++late_initcall(imx_amp_power_init);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-pfd.c linux-3.14.72/arch/arm/mach-imx/clk-pfd.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-pfd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-pfd.c 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2014 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -12,10 +12,12 @@
+
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
++#include <linux/imx_sema4.h>
+ #include <linux/io.h>
+ #include <linux/slab.h>
+ #include <linux/err.h>
+ #include "clk.h"
++#include "common.h"
+
+ /**
+ * struct clk_pfd - IMX PFD clock
+@@ -39,20 +41,56 @@
+ #define CLR 0x8
+ #define OTG 0xc
+
+-static int clk_pfd_enable(struct clk_hw *hw)
++static void clk_pfd_do_hardware(struct clk_pfd *pfd, bool enable)
++{
++ if (enable)
++ writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
++ else
++ writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
++}
++
++static void clk_pfd_do_shared_clks(struct clk_hw *hw, bool enable)
+ {
+ struct clk_pfd *pfd = to_clk_pfd(hw);
+
+- writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR);
++#ifdef CONFIG_SOC_IMX6SX
++ if (imx_src_is_m4_enabled()) {
++ if (!amp_power_mutex || !shared_mem) {
++ if (enable)
++ clk_pfd_do_hardware(pfd, enable);
++ return;
++ }
++
++ imx_sema4_mutex_lock(amp_power_mutex);
++ if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER ||
++ shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) {
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ return;
++ }
++
++ if (!imx_update_shared_mem(hw, enable)) {
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ return;
++ }
++
++ clk_pfd_do_hardware(pfd, enable);
++
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ } else
++#endif
++ clk_pfd_do_hardware(pfd, enable);
++}
++
++static int clk_pfd_enable(struct clk_hw *hw)
++{
++ clk_pfd_do_shared_clks(hw, true);
+
+ return 0;
+ }
+
+ static void clk_pfd_disable(struct clk_hw *hw)
+ {
+- struct clk_pfd *pfd = to_clk_pfd(hw);
+-
+- writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET);
++ clk_pfd_do_shared_clks(hw, false);
+ }
+
+ static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/clk-pllv3.c linux-3.14.72/arch/arm/mach-imx/clk-pllv3.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/clk-pllv3.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/clk-pllv3.c 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2015 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -13,18 +13,18 @@
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+ #include <linux/delay.h>
++#include <linux/imx_sema4.h>
+ #include <linux/io.h>
+ #include <linux/slab.h>
+ #include <linux/jiffies.h>
+ #include <linux/err.h>
+ #include "clk.h"
++#include "common.h"
+
+ #define PLL_NUM_OFFSET 0x10
+ #define PLL_DENOM_OFFSET 0x20
+
+ #define BM_PLL_POWER (0x1 << 12)
+-#define BM_PLL_ENABLE (0x1 << 13)
+-#define BM_PLL_BYPASS (0x1 << 16)
+ #define BM_PLL_LOCK (0x1 << 31)
+
+ /**
+@@ -61,70 +61,78 @@
+ break;
+ if (time_after(jiffies, timeout))
+ break;
+- usleep_range(50, 500);
+ } while (1);
+
+ return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
+ }
+
+-static int clk_pllv3_prepare(struct clk_hw *hw)
++static int clk_pllv3_do_hardware(struct clk_hw *hw, bool enable)
+ {
+ struct clk_pllv3 *pll = to_clk_pllv3(hw);
+ u32 val;
+ int ret;
+
+ val = readl_relaxed(pll->base);
+- if (pll->powerup_set)
+- val |= BM_PLL_POWER;
+- else
+- val &= ~BM_PLL_POWER;
+- writel_relaxed(val, pll->base);
+-
+- ret = clk_pllv3_wait_lock(pll);
+- if (ret)
+- return ret;
+-
+- val = readl_relaxed(pll->base);
+- val &= ~BM_PLL_BYPASS;
+- writel_relaxed(val, pll->base);
++ if (enable) {
++ if (pll->powerup_set)
++ val |= BM_PLL_POWER;
++ else
++ val &= ~BM_PLL_POWER;
++ writel_relaxed(val, pll->base);
++
++ ret = clk_pllv3_wait_lock(pll);
++ if (ret)
++ return ret;
++ } else {
++ if (pll->powerup_set)
++ val &= ~BM_PLL_POWER;
++ else
++ val |= BM_PLL_POWER;
++ writel_relaxed(val, pll->base);
++ }
+
+ return 0;
+ }
+
+-static void clk_pllv3_unprepare(struct clk_hw *hw)
++static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable)
+ {
+- struct clk_pllv3 *pll = to_clk_pllv3(hw);
+- u32 val;
+-
+- val = readl_relaxed(pll->base);
+- val |= BM_PLL_BYPASS;
+- if (pll->powerup_set)
+- val &= ~BM_PLL_POWER;
+- else
+- val |= BM_PLL_POWER;
+- writel_relaxed(val, pll->base);
++#ifdef CONFIG_SOC_IMX6SX
++ if (imx_src_is_m4_enabled()) {
++ if (!amp_power_mutex || !shared_mem) {
++ if (enable)
++ clk_pllv3_do_hardware(hw, enable);
++ return;
++ }
++
++ imx_sema4_mutex_lock(amp_power_mutex);
++ if (shared_mem->ca9_valid != SHARED_MEM_MAGIC_NUMBER ||
++ shared_mem->cm4_valid != SHARED_MEM_MAGIC_NUMBER) {
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ return;
++ }
++
++ if (!imx_update_shared_mem(hw, enable)) {
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ return;
++ }
++ clk_pllv3_do_hardware(hw, enable);
++
++ imx_sema4_mutex_unlock(amp_power_mutex);
++ } else
++#endif
++ clk_pllv3_do_hardware(hw, enable);
+ }
+
+-static int clk_pllv3_enable(struct clk_hw *hw)
++static int clk_pllv3_prepare(struct clk_hw *hw)
+ {
+- struct clk_pllv3 *pll = to_clk_pllv3(hw);
+- u32 val;
+-
+- val = readl_relaxed(pll->base);
+- val |= BM_PLL_ENABLE;
+- writel_relaxed(val, pll->base);
++ clk_pllv3_do_shared_clks(hw, true);
+
+ return 0;
+ }
+
+-static void clk_pllv3_disable(struct clk_hw *hw)
++static void clk_pllv3_unprepare(struct clk_hw *hw)
+ {
+- struct clk_pllv3 *pll = to_clk_pllv3(hw);
+- u32 val;
+-
+- val = readl_relaxed(pll->base);
+- val &= ~BM_PLL_ENABLE;
+- writel_relaxed(val, pll->base);
++ clk_pllv3_do_shared_clks(hw, false);
+ }
+
+ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
+@@ -169,8 +177,6 @@
+ static const struct clk_ops clk_pllv3_ops = {
+ .prepare = clk_pllv3_prepare,
+ .unprepare = clk_pllv3_unprepare,
+- .enable = clk_pllv3_enable,
+- .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_recalc_rate,
+ .round_rate = clk_pllv3_round_rate,
+ .set_rate = clk_pllv3_set_rate,
+@@ -225,8 +231,6 @@
+ static const struct clk_ops clk_pllv3_sys_ops = {
+ .prepare = clk_pllv3_prepare,
+ .unprepare = clk_pllv3_unprepare,
+- .enable = clk_pllv3_enable,
+- .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_sys_recalc_rate,
+ .round_rate = clk_pllv3_sys_round_rate,
+ .set_rate = clk_pllv3_sys_set_rate,
+@@ -299,8 +303,6 @@
+ static const struct clk_ops clk_pllv3_av_ops = {
+ .prepare = clk_pllv3_prepare,
+ .unprepare = clk_pllv3_unprepare,
+- .enable = clk_pllv3_enable,
+- .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_av_recalc_rate,
+ .round_rate = clk_pllv3_av_round_rate,
+ .set_rate = clk_pllv3_av_set_rate,
+@@ -315,8 +317,6 @@
+ static const struct clk_ops clk_pllv3_enet_ops = {
+ .prepare = clk_pllv3_prepare,
+ .unprepare = clk_pllv3_unprepare,
+- .enable = clk_pllv3_enable,
+- .disable = clk_pllv3_disable,
+ .recalc_rate = clk_pllv3_enet_recalc_rate,
+ };
+
+@@ -355,7 +355,7 @@
+
+ init.name = name;
+ init.ops = ops;
+- init.flags = 0;
++ init.flags = CLK_SET_RATE_GATE | CLK_GET_RATE_NOCACHE;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/common.h linux-3.14.72/arch/arm/mach-imx/common.h
+--- linux-3.14.72.orig/arch/arm/mach-imx/common.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/common.h 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+ /*
+@@ -17,6 +17,8 @@
+ struct platform_device;
+ struct pt_regs;
+ struct clk;
++struct clk_hw;
++struct device_node;
+ enum mxc_cpu_pwr_mode;
+
+ void mx1_map_io(void);
+@@ -56,6 +58,7 @@
+ void imx53_init_late(void);
+ void epit_timer_init(void __iomem *base, int irq);
+ void mxc_timer_init(void __iomem *, int);
++void mxc_timer_init_dt(struct device_node *);
+ int mx1_clocks_init(unsigned long fref);
+ int mx21_clocks_init(unsigned long lref, unsigned long fref);
+ int mx25_clocks_init(void);
+@@ -80,6 +83,18 @@
+ unsigned int imx_get_soc_revision(void);
+ void imx_init_revision_from_anatop(void);
+ struct device *imx_soc_device_init(void);
++unsigned int imx_gpc_is_mf_mix_off(void);
++void imx6sx_set_m4_highfreq(bool high_freq);
++void imx_mu_enable_m4_irqs_in_gic(bool enable);
++void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable);
++void imx_gpc_hold_m4_in_sleep(void);
++void imx_gpc_release_m4_in_sleep(void);
++int imx_update_shared_mem(struct clk_hw *hw, bool enable);
++bool imx_src_is_m4_enabled(void);
++void mcc_receive_from_mu_buffer(unsigned int index, unsigned int *data);
++void mcc_send_via_mu_buffer(unsigned int index, unsigned int data);
++unsigned int imx_gpc_is_m4_sleeping(void);
++bool imx_mu_is_m4_in_low_freq(void);
+
+ enum mxc_cpu_pwr_mode {
+ WAIT_CLOCKED, /* wfi only */
+@@ -116,20 +131,19 @@
+ void imx_set_cpu_jump(int cpu, void *jump_addr);
+ u32 imx_get_cpu_arg(int cpu);
+ void imx_set_cpu_arg(int cpu, u32 arg);
+-void v7_cpu_resume(void);
+ #ifdef CONFIG_SMP
+ void v7_secondary_startup(void);
+ void imx_scu_map_io(void);
+ void imx_smp_prepare(void);
+-void imx_scu_standby_enable(void);
+ #else
+ static inline void imx_scu_map_io(void) {}
+ static inline void imx_smp_prepare(void) {}
+-static inline void imx_scu_standby_enable(void) {}
+ #endif
++extern void imx6_pm_map_io(void);
++
+ void imx_src_init(void);
+ void imx_gpc_init(void);
+-void imx_gpc_pre_suspend(void);
++void imx_gpc_pre_suspend(bool arm_power_off);
+ void imx_gpc_post_resume(void);
+ void imx_gpc_mask_all(void);
+ void imx_gpc_restore_all(void);
+@@ -139,13 +153,31 @@
+ void imx_anatop_pre_suspend(void);
+ void imx_anatop_post_resume(void);
+ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
+-void imx6q_set_chicken_bit(void);
++void imx6q_set_int_mem_clk_lpm(bool enable);
++void imx6sl_set_wait_clk(bool enter);
++void imx6_enet_mac_init(const char *compatible);
++int imx_mmdc_get_ddr_type(void);
++void imx6_busfreq_map_io(void);
++void imx6sx_low_power_idle(void);
++void imx6q_enable_rbc(bool enable);
+
+ void imx_cpu_die(unsigned int cpu);
+ int imx_cpu_kill(unsigned int cpu);
+
++#ifdef CONFIG_SUSPEND
++void v7_cpu_resume(void);
++void imx6_suspend(void __iomem *ocram_vbase);
++#else
++static inline void v7_cpu_resume(void) {}
++static inline void imx6_suspend(void __iomem *ocram_vbase) {}
++#endif
++
+ void imx6q_pm_init(void);
++void imx6dl_pm_init(void);
++void imx6sl_pm_init(void);
++void imx6sx_pm_init(void);
+ void imx6q_pm_set_ccm_base(void __iomem *base);
++
+ #ifdef CONFIG_PM
+ void imx5_pm_init(void);
+ #else
+@@ -165,5 +197,5 @@
+ #endif
+
+ extern struct smp_operations imx_smp_ops;
+-
++extern void imx6sl_low_power_wfi(void __iomem *base);
+ #endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/common-imx6.c linux-3.14.72/arch/arm/mach-imx/common-imx6.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/common-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/common-imx6.c 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,96 @@
++/*
++ * Copyright 2011-2015 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_net.h>
++#include <linux/netdevice.h>
++
++#include "common.h"
++#define OCOTP_MACn(n) (0x00000620 + (n) * 0x10)
++
++void __init imx6_enet_mac_init(const char *compatible)
++{
++ struct device_node *ocotp_np, *enet_np, *from = NULL;
++ void __iomem *base;
++ struct property *newmac;
++ u32 macaddr_low;
++ u32 macaddr_high = 0;
++ u32 macaddr1_high = 0;
++ u8 *macaddr;
++ int i;
++
++ for (i = 0; i < 2; i++) {
++ enet_np = of_find_compatible_node(from, NULL, compatible);
++ if (!enet_np)
++ return;
++
++ from = enet_np;
++
++ if (of_get_mac_address(enet_np))
++ goto put_enet_node;
++
++ ocotp_np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
++ if (!ocotp_np) {
++ pr_warn("failed to find ocotp node\n");
++ goto put_enet_node;
++ }
++
++ base = of_iomap(ocotp_np, 0);
++ if (!base) {
++ pr_warn("failed to map ocotp\n");
++ goto put_ocotp_node;
++ }
++
++ macaddr_low = readl_relaxed(base + OCOTP_MACn(1));
++ if (i)
++ macaddr1_high = readl_relaxed(base + OCOTP_MACn(2));
++ else
++ macaddr_high = readl_relaxed(base + OCOTP_MACn(0));
++
++ newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
++ if (!newmac)
++ goto put_ocotp_node;
++
++ newmac->value = newmac + 1;
++ newmac->length = 6;
++ newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
++ if (!newmac->name) {
++ kfree(newmac);
++ goto put_ocotp_node;
++ }
++
++ macaddr = newmac->value;
++ if (i) {
++ macaddr[5] = (macaddr_low >> 16) & 0xff;
++ macaddr[4] = (macaddr_low >> 24) & 0xff;
++ macaddr[3] = macaddr1_high & 0xff;
++ macaddr[2] = (macaddr1_high >> 8) & 0xff;
++ macaddr[1] = (macaddr1_high >> 16) & 0xff;
++ macaddr[0] = (macaddr1_high >> 24) & 0xff;
++ } else {
++ macaddr[5] = macaddr_high & 0xff;
++ macaddr[4] = (macaddr_high >> 8) & 0xff;
++ macaddr[3] = (macaddr_high >> 16) & 0xff;
++ macaddr[2] = (macaddr_high >> 24) & 0xff;
++ macaddr[1] = macaddr_low & 0xff;
++ macaddr[0] = (macaddr_low >> 8) & 0xff;
++ }
++
++ of_update_property(enet_np, newmac);
++
++put_ocotp_node:
++ of_node_put(ocotp_np);
++put_enet_node:
++ of_node_put(enet_np);
++ }
++}
++
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/cpu.c linux-3.14.72/arch/arm/mach-imx/cpu.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/cpu.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/cpu.c 2016-06-19 22:11:55.049156848 +0200
+@@ -111,6 +111,9 @@
+ case MXC_CPU_IMX6DL:
+ soc_id = "i.MX6DL";
+ break;
++ case MXC_CPU_IMX6SX:
++ soc_id = "i.MX6SX";
++ break;
+ case MXC_CPU_IMX6Q:
+ soc_id = "i.MX6Q";
+ break;
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/cpuidle.h linux-3.14.72/arch/arm/mach-imx/cpuidle.h
+--- linux-3.14.72.orig/arch/arm/mach-imx/cpuidle.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/cpuidle.h 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2014 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -13,6 +13,8 @@
+ #ifdef CONFIG_CPU_IDLE
+ extern int imx5_cpuidle_init(void);
+ extern int imx6q_cpuidle_init(void);
++extern int imx6sl_cpuidle_init(void);
++extern int imx6sx_cpuidle_init(void);
+ #else
+ static inline int imx5_cpuidle_init(void)
+ {
+@@ -22,4 +24,12 @@
+ {
+ return 0;
+ }
++static inline int imx6sl_cpuidle_init(void)
++{
++ return 0;
++}
++static inline int imx6sx_cpuidle_init(void)
++{
++ return 0;
++}
+ #endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/cpuidle-imx6q.c linux-3.14.72/arch/arm/mach-imx/cpuidle-imx6q.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/cpuidle-imx6q.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/cpuidle-imx6q.c 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -65,11 +65,8 @@
+
+ int __init imx6q_cpuidle_init(void)
+ {
+- /* Need to enable SCU standby for entering WAIT modes */
+- imx_scu_standby_enable();
+-
+- /* Set chicken bit to get a reliable WAIT mode support */
+- imx6q_set_chicken_bit();
++ /* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
++ imx6q_set_int_mem_clk_lpm(true);
+
+ return cpuidle_register(&imx6q_cpuidle_driver, NULL);
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/cpuidle-imx6sl.c linux-3.14.72/arch/arm/mach-imx/cpuidle-imx6sl.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/cpuidle-imx6sl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/cpuidle-imx6sl.c 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,209 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/cpuidle.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/machine.h>
++#include <asm/cpuidle.h>
++#include <asm/fncpy.h>
++#include <asm/proc-fns.h>
++
++#include "common.h"
++#include "cpuidle.h"
++#include "hardware.h"
++
++#define MAX_MMDC_IO_NUM 19
++
++static void __iomem *wfi_iram_base;
++extern unsigned long iram_tlb_base_addr;
++extern int ultra_low_bus_freq_mode;
++extern int audio_bus_freq_mode;
++extern unsigned long mx6sl_lpm_wfi_start asm("mx6sl_lpm_wfi_start");
++extern unsigned long mx6sl_lpm_wfi_end asm("mx6sl_lpm_wfi_end");
++
++struct imx6_cpuidle_pm_info {
++ u32 pm_info_size; /* Size of pm_info */
++ u32 ttbr;
++ void __iomem *mmdc_base;
++ void __iomem *iomuxc_base;
++ void __iomem *ccm_base;
++ void __iomem *l2_base;
++ void __iomem *anatop_base;
++ u32 mmdc_io_num; /*Number of MMDC IOs which need saved/restored. */
++ u32 mmdc_io_val[MAX_MMDC_IO_NUM][2]; /* To save offset and value */
++} __aligned(8);
++
++static const u32 imx6sl_mmdc_io_offset[] __initconst = {
++ 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
++ 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
++ 0x300, 0x31c, 0x338, 0x5ac, /*CAS, RAS, SDCLK_0, GPR_ADDS */
++ 0x33c, 0x340, 0x5b0, 0x5c0, /*SODT0, SODT1, ,MODE_CTL, MODE */
++ 0x330, 0x334, 0x320, /*SDCKE0, SDCK1, RESET */
++};
++
++static struct regulator *vbus_ldo;
++static struct regulator_dev *ldo2p5_dummy_regulator_rdev;
++static struct regulator_init_data ldo2p5_dummy_initdata = {
++ .constraints = {
++ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
++ },
++};
++static int ldo2p5_dummy_enable;
++
++static void (*imx6sl_wfi_in_iram_fn)(void __iomem *iram_vbase,
++ int audio_mode, bool vbus_ldo);
++
++static int imx6sl_enter_wait(struct cpuidle_device *dev,
++ struct cpuidle_driver *drv, int index)
++{
++ imx6q_set_lpm(WAIT_UNCLOCKED);
++ if (audio_bus_freq_mode || ultra_low_bus_freq_mode) {
++ imx6sl_wfi_in_iram_fn(wfi_iram_base, audio_bus_freq_mode,
++ regulator_is_enabled(vbus_ldo));
++ } else {
++ /*
++ * Software workaround for ERR005311, see function
++ * description for details.
++ */
++ imx6sl_set_wait_clk(true);
++ cpu_do_idle();
++ imx6sl_set_wait_clk(false);
++ }
++ imx6q_set_lpm(WAIT_CLOCKED);
++
++ return index;
++}
++
++static struct cpuidle_driver imx6sl_cpuidle_driver = {
++ .name = "imx6sl_cpuidle",
++ .owner = THIS_MODULE,
++ .states = {
++ /* WFI */
++ ARM_CPUIDLE_WFI_STATE,
++ /* WAIT */
++ {
++ .exit_latency = 50,
++ .target_residency = 75,
++ .flags = CPUIDLE_FLAG_TIME_VALID |
++ CPUIDLE_FLAG_TIMER_STOP,
++ .enter = imx6sl_enter_wait,
++ .name = "WAIT",
++ .desc = "Clock off",
++ },
++ },
++ .state_count = 2,
++ .safe_state_index = 0,
++};
++
++int __init imx6sl_cpuidle_init(void)
++{
++ struct imx6_cpuidle_pm_info *pm_info;
++ int i;
++ const u32 *mmdc_offset_array;
++ u32 wfi_code_size;
++
++ vbus_ldo = regulator_get(NULL, "ldo2p5-dummy");
++ if (IS_ERR(vbus_ldo))
++ vbus_ldo = NULL;
++
++ wfi_iram_base = (void *)(iram_tlb_base_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET);
++
++ /* Make sure wif_iram_base is 8 byte aligned. */
++ if ((uintptr_t)(wfi_iram_base) & (FNCPY_ALIGN - 1))
++ wfi_iram_base += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base % (FNCPY_ALIGN));
++
++ pm_info = wfi_iram_base;
++ pm_info->pm_info_size = sizeof(*pm_info);
++ pm_info->mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset);
++ mmdc_offset_array = imx6sl_mmdc_io_offset;
++ pm_info->mmdc_base = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR);
++ pm_info->ccm_base = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR);
++ pm_info->anatop_base = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR);
++ pm_info->iomuxc_base = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR);
++ pm_info->l2_base = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR);
++
++ /* Only save mmdc io offset, settings will be saved in asm code */
++ for (i = 0; i < pm_info->mmdc_io_num; i++)
++ pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i];
++
++ /* calculate the wfi code size */
++ wfi_code_size = (&mx6sl_lpm_wfi_end -&mx6sl_lpm_wfi_start) *4;
++
++ imx6sl_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*pm_info),
++ &imx6sl_low_power_wfi, wfi_code_size);
++
++ return cpuidle_register(&imx6sl_cpuidle_driver, NULL);
++}
++
++static int imx_ldo2p5_dummy_enable(struct regulator_dev *rdev)
++{
++ ldo2p5_dummy_enable = 1;
++ return 0;
++}
++
++static int imx_ldo2p5_dummy_disable(struct regulator_dev *rdev)
++{
++ ldo2p5_dummy_enable = 0;
++ return 0;
++}
++
++static int imx_ldo2p5_dummy_is_enable(struct regulator_dev *rdev)
++{
++ return ldo2p5_dummy_enable;
++}
++
++static struct regulator_ops ldo2p5_dummy_ops = {
++ .enable = imx_ldo2p5_dummy_enable,
++ .disable = imx_ldo2p5_dummy_disable,
++ .is_enabled = imx_ldo2p5_dummy_is_enable,
++};
++
++static struct regulator_desc ldo2p5_dummy_desc = {
++ .name = "ldo2p5-dummy",
++ .id = -1,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++ .ops = &ldo2p5_dummy_ops,
++};
++
++static int ldo2p5_dummy_probe(struct platform_device *pdev)
++{
++ struct regulator_config config = { };
++ int ret;
++
++ config.dev = &pdev->dev;
++ config.init_data = &ldo2p5_dummy_initdata;
++ config.of_node = pdev->dev.of_node;
++
++ ldo2p5_dummy_regulator_rdev = regulator_register(&ldo2p5_dummy_desc, &config);
++ if (IS_ERR(ldo2p5_dummy_regulator_rdev)) {
++ ret = PTR_ERR(ldo2p5_dummy_regulator_rdev);
++ dev_err(&pdev->dev, "Failed to register dummy ldo2p5 regulator: %d\n", ret);
++ return ret;
++ }
++ return 0;
++}
++
++static const struct of_device_id imx_ldo2p5_dummy_ids[] = {
++ { .compatible = "fsl,imx6-dummy-ldo2p5"},
++ };
++MODULE_DEVICE_TABLE(ofm, imx_ldo2p5_dummy_ids);
++
++static struct platform_driver ldo2p5_dummy_driver = {
++ .probe = ldo2p5_dummy_probe,
++ .driver = {
++ .name = "ldo2p5-dummy",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_ldo2p5_dummy_ids,
++ },
++};
++
++module_platform_driver(ldo2p5_dummy_driver);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/cpuidle-imx6sx.c linux-3.14.72/arch/arm/mach-imx/cpuidle-imx6sx.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/cpuidle-imx6sx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/cpuidle-imx6sx.c 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,276 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/cpuidle.h>
++#include <linux/cpu_pm.h>
++#include <linux/delay.h>
++#include <linux/genalloc.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <asm/cpuidle.h>
++#include <asm/fncpy.h>
++#include <asm/mach/map.h>
++#include <asm/proc-fns.h>
++#include <asm/suspend.h>
++#include <asm/tlb.h>
++
++#include "common.h"
++#include "cpuidle.h"
++#include "hardware.h"
++
++#define MX6_MAX_MMDC_IO_NUM 19
++
++#define PMU_LOW_PWR_CTRL 0x270
++#define XTALOSC24M_OSC_CONFIG0 0x2a0
++#define XTALOSC24M_OSC_CONFIG1 0x2b0
++#define XTALOSC24M_OSC_CONFIG2 0x2c0
++#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24
++#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf
++#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16
++#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf
++#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12
++#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4
++#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1
++#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0
++#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20
++#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0
++#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff
++#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0
++
++static void __iomem *wfi_iram_base;
++static void __iomem *wfi_iram_base_phys;
++extern unsigned long iram_tlb_phys_addr;
++extern unsigned long mx6sx_lpm_wfi_start asm("mx6sx_lpm_wfi_start");
++extern unsigned long mx6sx_lpm_wfi_end asm("mx6sx_lpm_wfi_end");
++extern u32 low_bus_freq_mode;
++
++struct imx6_pm_base {
++ phys_addr_t pbase;
++ void __iomem *vbase;
++};
++
++static const u32 imx6sx_mmdc_io_offset[] __initconst = {
++ 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
++ 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
++ 0x60c, 0x610, 0x61c, 0x620, /* B0DS ~ B3DS */
++ 0x5f8, 0x608, 0x310, 0x314, /* CTL, MODE, SODT0, SODT1 */
++ 0x300, 0x2fc, 0x32c, /* CAS, RAS, SDCLK_0 */
++};
++
++struct imx6_cpuidle_pm_info {
++ phys_addr_t pbase; /* The physical address of pm_info. */
++ phys_addr_t resume_addr; /* The physical resume address for asm code */
++ u32 pm_info_size; /* Size of pm_info. */
++ u32 ttbr;
++ struct imx6_pm_base mmdc_base;
++ struct imx6_pm_base iomuxc_base;
++ struct imx6_pm_base ccm_base;
++ struct imx6_pm_base gpc_base;
++ struct imx6_pm_base l2_base;
++ struct imx6_pm_base anatop_base;
++ struct imx6_pm_base src_base;
++ struct imx6_pm_base sema4_base;
++ u32 saved_diagnostic; /* To save disagnostic register */
++ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
++ u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
++} __aligned(8);
++
++static void (*imx6sx_wfi_in_iram_fn)(void __iomem *iram_vbase);
++
++static int imx6_idle_finish(unsigned long val)
++{
++ imx6sx_wfi_in_iram_fn(wfi_iram_base);
++
++ return 0;
++}
++
++static int imx6sx_enter_wait(struct cpuidle_device *dev,
++ struct cpuidle_driver *drv, int index)
++{
++ imx6q_set_lpm(WAIT_UNCLOCKED);
++ if ((index == 1) || (!low_bus_freq_mode && index == 2)) {
++ cpu_do_idle();
++ } else {
++ /* Need to notify there is a cpu pm operation. */
++ cpu_pm_enter();
++ cpu_cluster_pm_enter();
++
++ cpu_suspend(0, imx6_idle_finish);
++
++ cpu_cluster_pm_exit();
++ cpu_pm_exit();
++ imx6q_enable_rbc(false);
++ }
++
++ imx6q_set_lpm(WAIT_CLOCKED);
++
++ return index;
++}
++
++static struct cpuidle_driver imx6sx_cpuidle_driver = {
++ .name = "imx6sx_cpuidle",
++ .owner = THIS_MODULE,
++ .states = {
++ /* WFI */
++ ARM_CPUIDLE_WFI_STATE,
++ /* WAIT MODE */
++ {
++ .exit_latency = 50,
++ .target_residency = 75,
++ .flags = CPUIDLE_FLAG_TIME_VALID,
++ .enter = imx6sx_enter_wait,
++ .name = "WAIT",
++ .desc = "Clock off",
++ },
++ /* LOW POWER IDLE */
++ {
++ /*
++ * RBC 31us + ARM gating 93us + RBC clear 65us
++ * + PLL2 relock 450us and some margin, here set
++ * it to 650us.
++ */
++ .exit_latency = 650,
++ .target_residency = 1000,
++ .flags = CPUIDLE_FLAG_TIME_VALID,
++ .enter = imx6sx_enter_wait,
++ .name = "LOW-POWER-IDLE",
++ .desc = "ARM power off",
++ },
++
++ },
++ .state_count = 3,
++ .safe_state_index = 0,
++};
++
++int __init imx6sx_cpuidle_init(void)
++{
++ struct imx6_cpuidle_pm_info *cpuidle_pm_info;
++ int i;
++ const u32 *mmdc_offset_array;
++ u32 wfi_code_size, val;
++
++ wfi_iram_base_phys = (void *)(iram_tlb_phys_addr + MX6_CPUIDLE_IRAM_ADDR_OFFSET);
++
++ /* Make sure wfi_iram_base is 8 byte aligned. */
++ if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1))
++ wfi_iram_base_phys += FNCPY_ALIGN - ((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN));
++
++ wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys);
++
++ cpuidle_pm_info = wfi_iram_base;
++ cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys;
++ cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info);
++ cpuidle_pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
++ cpuidle_pm_info->mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset);
++ mmdc_offset_array = imx6sx_mmdc_io_offset;
++
++ cpuidle_pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR;
++ cpuidle_pm_info->mmdc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR);
++
++ cpuidle_pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR;
++ cpuidle_pm_info->ccm_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_CCM_BASE_ADDR);
++
++ cpuidle_pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR;
++ cpuidle_pm_info->anatop_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR);
++
++ cpuidle_pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR;
++ cpuidle_pm_info->gpc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_GPC_BASE_ADDR);
++
++ cpuidle_pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR;
++ cpuidle_pm_info->iomuxc_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR);
++
++ cpuidle_pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR;
++ cpuidle_pm_info->l2_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_L2_BASE_ADDR);
++
++ cpuidle_pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR;
++ cpuidle_pm_info->src_base.vbase = (void __iomem *)IMX_IO_P2V(MX6Q_SRC_BASE_ADDR);
++
++ cpuidle_pm_info->sema4_base.pbase = MX6Q_SEMA4_BASE_ADDR;
++ cpuidle_pm_info->sema4_base.vbase =
++ (void __iomem *)IMX_IO_P2V(MX6Q_SEMA4_BASE_ADDR);
++
++ /* only save mmdc io offset, settings will be saved in asm code */
++ for (i = 0; i < cpuidle_pm_info->mmdc_io_num; i++)
++ cpuidle_pm_info->mmdc_io_val[i][0] = mmdc_offset_array[i];
++
++ /* code size should include cpuidle_pm_info size */
++ wfi_code_size = (&mx6sx_lpm_wfi_end -&mx6sx_lpm_wfi_start) *4 + sizeof(*cpuidle_pm_info);
++ imx6sx_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base + sizeof(*cpuidle_pm_info),
++ &imx6sx_low_power_idle, wfi_code_size);
++
++ imx6q_set_int_mem_clk_lpm(true);
++
++ if (imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) {
++ /*
++ * enable RC-OSC here, as it needs at least 4ms for RC-OSC to
++ * be stable, low power idle flow can NOT endure this big
++ * latency, so we make RC-OSC self-tuning enabled here.
++ */
++ val = readl_relaxed(cpuidle_pm_info->anatop_base.vbase +
++ PMU_LOW_PWR_CTRL);
++ val |= 0x1;
++ writel_relaxed(val, cpuidle_pm_info->anatop_base.vbase +
++ PMU_LOW_PWR_CTRL);
++ /*
++ * config RC-OSC freq
++ * tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0;
++ * osc_prog = 0xa7;
++ */
++ writel_relaxed(
++ 0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT |
++ 0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT |
++ 0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT |
++ 0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT,
++ cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG0);
++ /* set count_trg = 0x2dc */
++ writel_relaxed(
++ 0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT |
++ 0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT,
++ cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG1);
++ /* wait 4ms according to hardware design */
++ msleep(4);
++ /*
++ * now add some hysteresis, hyst_plus=3, hyst_minus=3
++ * (the minimum hysteresis that looks good is 2)
++ */
++ val = readl_relaxed(cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG0);
++ val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK <<
++ XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) |
++ (XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK <<
++ XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT));
++ val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) |
++ (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT);
++ writel_relaxed(val, cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG0);
++ /* set the count_1m_trg = 0x2d7 */
++ val = readl_relaxed(cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG2);
++ val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK <<
++ XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT);
++ val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT;
++ writel_relaxed(val, cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG2);
++ /*
++ * hardware design require to write XTALOSC24M_OSC_CONFIG0 or
++ * XTALOSC24M_OSC_CONFIG1 to
++ * make XTALOSC24M_OSC_CONFIG2 write work
++ */
++ val = readl_relaxed(cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG1);
++ writel_relaxed(val, cpuidle_pm_info->anatop_base.vbase +
++ XTALOSC24M_OSC_CONFIG1);
++ }
++
++ return cpuidle_register(&imx6sx_cpuidle_driver, NULL);
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/ddr3_freq_imx6.S linux-3.14.72/arch/arm/mach-imx/ddr3_freq_imx6.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/ddr3_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/ddr3_freq_imx6.S 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,1116 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/linkage.h>
++#include <asm/smp_scu.h>
++#include "hardware.h"
++
++#define MMDC0_MDPDC 0x4
++#define MMDC0_MDCF0 0x0c
++#define MMDC0_MDCF1 0x10
++#define MMDC0_MDMISC 0x18
++#define MMDC0_MDSCR 0x1c
++#define MMDC0_MAPSR 0x404
++#define MMDC0_MADPCR0 0x410
++#define MMDC0_MPZQHWCTRL 0x800
++#define MMDC1_MPZQHWCTRL 0x4800
++#define MMDC0_MPODTCTRL 0x818
++#define MMDC1_MPODTCTRL 0x4818
++#define MMDC0_MPDGCTRL0 0x83c
++#define MMDC1_MPDGCTRL0 0x483c
++#define MMDC0_MPMUR0 0x8b8
++#define MMDC1_MPMUR0 0x48b8
++
++#define CCM_CBCDR 0x14
++#define CCM_CBCMR 0x18
++#define CCM_CSCMR1 0x1c
++#define CCM_CDHIPR 0x48
++
++#define L2_CACHE_SYNC 0x730
++
++.extern iram_tlb_phys_addr
++#ifdef CONFIG_SMP
++.extern imx_scu_base
++#endif
++
++.globl mx6_ddr3_freq_change_start
++.globl mx6_ddr3_freq_change_end
++.globl wfe_ddr3_freq_change_start
++.globl wfe_ddr3_freq_change_end
++
++ .align 3
++
++ .macro switch_to_528MHz
++
++ /* check if periph_clk_sel is already set */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq set_ahb_podf_before_switch
++
++ /* change periph_clk to be sourced from pll3_clk. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 20)
++ str r0, [r6, #CCM_CBCDR]
++
++ /*
++ * set the AHB dividers before the switch,
++ * don't change AXI clock divider,
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #0xd00
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update528:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update528
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch3:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch3
++
++ b switch_pre_periph_clk_528
++
++set_ahb_podf_before_switch:
++ /*
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #0xd00
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update528_1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update528_1
++
++switch_pre_periph_clk_528:
++
++ /* now switch pre_periph_clk to PLL2_528MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0xc << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch4:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch4
++
++ .endm
++
++ .macro switch_to_400MHz
++
++ /* check if periph_clk_sel is already set. */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq set_ahb_podf_before_switch1
++
++ /* change periph_clk to be sourced from pll3_clk. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch5:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch5
++
++ b switch_pre_periph_clk_400
++
++set_ahb_podf_before_switch1:
++ /*
++ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x9 << 8)
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update400_1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update400_1
++
++switch_pre_periph_clk_400:
++
++ /* now switch pre_periph_clk to PFD_400MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0xc << 16)
++ orr r0, r0, #(0x4 << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch6:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch6
++
++ /*
++ * change AHB divider so that we are at 400/3=133MHz.
++ * don't change AXI clock divider.
++ * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x9 << 8)
++ orr r0, r0, #(1 << 16)
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update400_2:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update400_2
++
++ .endm
++
++ .macro switch_to_50MHz
++
++ /* check if periph_clk_sel is already set. */
++ ldr r0, [r6, #CCM_CBCDR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq switch_pre_periph_clk_50
++
++ /*
++ * set the periph_clk to be sourced from PLL2_PFD_200M
++ * change periph_clk to be sourced from pll3_clk.
++ * ensure PLL3 is the source and set the divider to 1.
++ */
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0x3 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to pll3_main_clk. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch_50:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch_50
++
++switch_pre_periph_clk_50:
++
++ /* now switch pre_periph_clk to PFD_200MHz. */
++ ldr r0, [r6, #CCM_CBCMR]
++ orr r0, r0, #(0xc << 16)
++ str r0, [r6, #CCM_CBCMR]
++
++ /*
++ * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8,
++ */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(0x18 << 16)
++ orr r0, r0, #(0x3 << 16)
++
++ /*
++ * if changing AHB divider remember to change
++ * the IPGPER divider too below.
++ */
++ orr r0, r0, #0x1d00
++ str r0, [r6, #CCM_CBCDR]
++
++wait_div_update_50:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update_50
++
++ /* now switch periph_clk back. */
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch2:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch2
++
++ .endm
++
++ .macro switch_to_24MHz
++ /*
++ * change the freq now try setting DDR to 24MHz.
++ * source it from the periph_clk2 ensure the
++ * periph_clk2 is sourced from 24MHz and the
++ * divider is 1.
++ */
++
++ ldr r0, [r6, #CCM_CBCMR]
++ bic r0, r0, #(0x3 << 12)
++ orr r0, r0, #(1 << 12)
++ str r0, [r6, #CCM_CBCMR]
++
++ ldr r0, [r6, #CCM_CBCDR]
++ bic r0, r0, #(0x38 << 24)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* now switch periph_clk to 24MHz. */
++ ldr r0, [r6, #CCM_CBCDR]
++ orr r0, r0, #(1 << 25)
++ str r0, [r6, #CCM_CBCDR]
++
++periph_clk_switch1:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne periph_clk_switch1
++
++ /* change all the dividers to 1. */
++ ldr r0, [r6, #CCM_CBCDR]
++ ldr r2, =0x3f1f00
++ bic r0, r0, r2
++ orr r0, r0, #(1 << 8)
++ str r0, [r6, #CCM_CBCDR]
++
++ /* Wait for the divider to change. */
++wait_div_update:
++ ldr r0, [r6, #CCM_CDHIPR]
++ cmp r0, #0
++ bne wait_div_update
++
++ .endm
++
++ .macro disable_l1_dcache
++
++ /*
++ * Flush all data from the L1 data cache before disabling
++ * SCTLR.C bit.
++ */
++ push {r0 - r11, lr}
++
++ ldr r7, =v7_flush_kern_cache_all
++ mov lr, pc
++ mov pc, r7
++ pop {r0 - r11, lr}
++
++ /* disable d-cache */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++ dsb
++ isb
++
++ push {r0 - r11, lr}
++
++ ldr r7, =v7_flush_kern_cache_all
++ mov lr, pc
++ mov pc, r7
++ pop {r0 - r11, lr}
++
++ .endm
++
++/*
++ * mx6_ddr3_freq_change
++ *
++ * idle the processor (eg, wait for interrupt).
++ * make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ */
++ENTRY(mx6_ddr3_freq_change)
++
++mx6_ddr3_freq_change_start:
++ stmfd sp!, {r4-r12}
++
++ /*
++ * r5 -> mmdc_base
++ * r6 -> ccm_base
++ * r7 -> iomux_base
++ * r12 -> l2_base
++ */
++ mov r4, r0
++ mov r8, r1
++ mov r9, r2
++ mov r11, r3
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ ldr r6, =iram_tlb_phys_addr
++ ldr r7, [r6]
++
++ /*
++ * Need to flush and disable L1 before disabling L2, we need data to
++ * coherent. Flushing L1 pushes everyhting to L2. We sync L2 later, but
++ * it can still have dirty lines. While exiting, we need to enable L2 first
++ * and then L1.
++ . */
++ disable_l1_dcache
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Make sure the L2 buffers are drained.
++ * Sync operation on L2 drains the buffers.
++ */
++ ldr r12, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++
++ /* Wait for background operations to complete. */
++wait_for_l2_to_idle:
++ ldr r1, [r12, #L2_CACHE_SYNC]
++ cmp r1, #0x0
++ bne wait_for_l2_to_idle
++
++ mov r1, #0x0
++ str r1, [r12, #L2_CACHE_SYNC]
++
++ /* Disable L2. */
++ str r1, [r12, #0x100]
++
++ dsb
++ isb
++#endif
++
++ /*
++ * To ensure no page table walks occur in DDR, we
++ * have a another page table stored in IRAM that only
++ * contains entries pointing to IRAM, AIPS1 and AIPS2.
++ * We need to set the TTBR1 to the new IRAM TLB.
++ * Do the following steps:
++ * 1. Flush the Branch Target Address Cache (BTAC)
++ * 2. Set TTBR1 to point to IRAM page table.
++ * 3. Disable page table walks in TTBR0 (PD0 = 1)
++ * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
++ * and 2-4G is translated by TTBR1.
++ */
++
++
++ /* Now switch the TTBR. */
++ /* Disable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ dsb
++ isb
++
++ /* Store the IRAM table in TTBR1 */
++ mcr p15, 0, r7, c2, c0, 1
++
++ /* Read TTBCR and set PD0=1, N = 1 */
++ mrc p15, 0, r6, c2, c0, 2
++ orr r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++
++ ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
++ ldr r6, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
++ ldr r7, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR)
++
++ /* Read the Original MU delay value */
++ ldr r1, [r5, #MMDC0_MPMUR0]
++ mov r10, r1, lsr #16
++ ldr r1, =0x3ff
++ and r10, r10, r1
++
++ /* disable automatic power saving. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* disable MMDC power down timer. */
++ ldr r0, [r5, #MMDC0_MDPDC]
++ bic r0, r0, #(0xff << 8)
++ str r0, [r5, #MMDC0_MDPDC]
++
++ /* delay for a while */
++ ldr r1, =4
++delay1:
++ ldr r2, =0
++cont1:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont1
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay1
++
++ /* set CON_REG */
++ ldr r0, =0x8000
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_set_1:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ bne poll_conreq_set_1
++
++ ldr r0, =0x00008010
++ str r0, [r5, #MMDC0_MDSCR]
++ ldr r0, =0x00008018
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /*
++ * if requested frequency is greater than
++ * 300MHz go to DLL on mode.
++ */
++ ldr r1, =300000000
++ cmp r4, r1
++ bge dll_on_mode
++
++dll_off_mode:
++
++ /* if DLL is currently on, turn it off. */
++ cmp r9, #1
++ beq continue_dll_off_1
++
++ ldr r0, =0x00018031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00018039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r1, =10
++delay1a:
++ ldr r2, =0
++cont1a:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont1a
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay1a
++
++continue_dll_off_1:
++ /* set DVFS - enter self refresh mode */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* de-assert con_req */
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++
++poll_dvfs_set_1:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ bne poll_dvfs_set_1
++
++ ldr r1, =24000000
++ cmp r4, r1
++ beq switch_freq_24
++
++ switch_to_50MHz
++ b continue_dll_off_2
++
++switch_freq_24:
++ switch_to_24MHz
++
++continue_dll_off_2:
++
++ /* set SBS - block ddr accesses */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ orr r0, r0, #(1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit from self refresh mode */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_clear_1:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq poll_dvfs_clear_1
++
++ /* if DLL was previously on, continue DLL off routine. */
++ cmp r9, #1
++ beq continue_dll_off_3
++
++ ldr r0, =0x00018031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00018039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x08208030
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x08208038
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00088032
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x0008803A
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for a while. */
++ ldr r1, =4
++delay_1:
++ ldr r2, =0
++cont_1:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont_1
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay_1
++
++ ldr r0, [r5, #MMDC0_MDCF0]
++ bic r0, r0, #0xf
++ orr r0, r0, #0x3
++ str r0, [r5, #MMDC0_MDCF0]
++
++ ldr r0, [r5, #MMDC0_MDCF1]
++ bic r0, r0, #0x7
++ orr r0, r0, #0x4
++ str r0, [r5, #MMDC0_MDCF1]
++
++ ldr r0, =0x00091680
++ str r0, [r5, #MMDC0_MDMISC]
++
++ /* enable dqs pull down in the IOMUX. */
++ ldr r1, [r11]
++ add r11, r11, #8
++ ldr r2, =0x3028
++update_iomux:
++ ldr r0, [r11, #0x0]
++ ldr r3, [r7, r0]
++ bic r3, r3, r2
++ orr r3, r3, #(0x3 << 12)
++ orr r3, r3, #0x28
++ str r3, [r7, r0]
++ add r11, r11, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_iomux
++
++ /* ODT disabled. */
++ ldr r0, =0x0
++ ldr r2, =MMDC0_MPODTCTRL
++ str r0, [r5, r2]
++ ldr r2, =MMDC1_MPODTCTRL
++ str r0, [r5, r2]
++
++ /* DQS gating disabled. */
++ ldr r2, =MMDC0_MPDGCTRL0
++ ldr r0, [r5, r2]
++ orr r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ ldr r2, =MMDC1_MPDGCTRL0
++ ldr r0, [r5, r2]
++ orr r0, r0, #(0x1 << 29)
++ str r0, [r5, r2]
++
++ /* Add workaround for ERR005778.*/
++ /* double the original MU_UNIT_DEL_NUM. */
++ lsl r10, r10, #1
++
++ /* Bypass the automatic MU by setting the mu_byp_en */
++ ldr r2, [r5, #MMDC0_MPMUR0]
++ orr r2, r2, #0x400
++ orr r2, r2, r10
++ str r2, [r5, #MMDC0_MPMUR0]
++ ldr r0, =MMDC1_MPMUR0
++ str r2, [r5, r0]
++
++ /* Now perform a force measure */
++ ldr r0, [r5, #MMDC0_MPMUR0]
++ orr r0, r0, #0x800
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++ /* Wait for FRC_MSR to clear. */
++1:
++ ldr r0, [r5, #MMDC0_MPMUR0]
++ and r0, r0, #0x800
++ ldr r1, [r5, r2]
++ and r1, r1, #0x800
++ orr r0, r0, r1
++ cmp r0, #0x0
++ bne 1b
++
++continue_dll_off_3:
++ /* clear SBS - unblock accesses to DDR. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ bic r0, r0, #(0x1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_clear_1:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ beq poll_conreq_clear_1
++
++ b done
++
++dll_on_mode:
++ /* assert DVFS - enter self refresh mode. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ orr r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++ /* de-assert CON_REQ. */
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* poll DVFS ack. */
++poll_dvfs_set_2:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ bne poll_dvfs_set_2
++
++ ldr r1, =528000000
++ cmp r4, r1
++ beq switch_freq_528
++
++ switch_to_400MHz
++
++ b continue_dll_on
++
++switch_freq_528:
++ switch_to_528MHz
++
++continue_dll_on:
++
++ /* set SBS step-by-step mode. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ orr r0, r0, #( 1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit self refresh mode. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #(1 << 21)
++ str r0, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_clear_2:
++ ldr r0, [r5, #MMDC0_MAPSR]
++ and r0, r0, #(1 << 25)
++ cmp r0, #(1 << 25)
++ beq poll_dvfs_clear_2
++
++ /* if DLL is currently off, turn it back on. */
++ cmp r9, #0
++ beq update_calibration_only
++
++ ldr r0, =0xa1390003
++ str r0, [r5, #MMDC0_MPZQHWCTRL]
++ ldr r2, =MMDC1_MPZQHWCTRL
++ str r0, [r5, r2]
++
++ /* enable DQS gating. */
++ ldr r2, =MMDC0_MPDGCTRL0
++ ldr r0, [r5, r2]
++ bic r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ ldr r2, =MMDC1_MPDGCTRL0
++ ldr r0, [r5, r2]
++ bic r0, r0, #(1 << 29)
++ str r0, [r5, r2]
++
++ /* force measure. */
++ ldr r0, =0x00000800
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++ /* Wait for FRC_MSR to clear. */
++1:
++ ldr r0, [r5, #MMDC0_MPMUR0]
++ and r0, r0, #0x800
++ ldr r1, [r5, r2]
++ and r1, r1, #0x800
++ orr r0, r0, r1
++ cmp r0, #0x0
++ bne 1b
++
++ /* disable dqs pull down in the IOMUX. */
++ ldr r1, [r11]
++ add r11, r11, #8
++update_iomux1:
++ ldr r0, [r11, #0x0]
++ ldr r3, [r11, #0x4]
++ str r3, [r7, r0]
++ add r11, r11, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_iomux1
++
++ /* config MMDC timings to 528MHz. */
++ ldr r9, [r8]
++ add r8, r8, #8
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ /* update MISC register: WALAT, RALAT */
++ ldr r0, =0x00081740
++ str r0, [r5, #MMDC0_MDMISC]
++
++ /* configure ddr devices to dll on, odt. */
++ ldr r0, =0x00028031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00028039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r1, =4
++delay7:
++ ldr r2, =0
++cont7:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont7
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay7
++
++ /* reset dll. */
++ ldr r0, =0x09208030
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x09208038
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r1, =100
++delay8:
++ ldr r2, =0
++cont8:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, =0x00428031
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x00428039
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ /* issue a zq command. */
++ ldr r0, =0x04008040
++ str r0, [r5, #MMDC0_MDSCR]
++
++ ldr r0, =0x04008048
++ str r0, [r5, #MMDC0_MDSCR]
++
++ /* MMDC ODT enable. */
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++
++ ldr r2, =0x4818
++ str r0, [r5, r2]
++
++ /* delay for while. */
++ ldr r1, =40
++delay15:
++ ldr r2, =0
++cont15:
++ ldr r0, [r5, r2]
++ add r2, r2, #4
++ cmp r2, #16
++ bne cont15
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt delay15
++
++ /* enable MMDC power down timer. */
++ ldr r0, [r5, #MMDC0_MDPDC]
++ orr r0, r0, #(0x55 << 8)
++ str r0, [r5, #MMDC0_MDPDC]
++
++ b update_calibration
++
++update_calibration_only:
++ ldr r1, [r8]
++ sub r1, r1, #7
++ add r8, r8, #64
++ b update_calib
++
++update_calibration:
++ /* write the new calibration values. */
++ mov r1, r9
++ sub r1, r1, #7
++
++update_calib:
++ ldr r0, [r8, #0x0]
++ ldr r3, [r8, #0x4]
++ str r3, [r5, r0]
++ add r8, r8, #8
++ sub r1, r1, #1
++ cmp r1, #0
++ bgt update_calib
++
++ /* perform a force measurement. */
++ ldr r0, =0x800
++ str r0, [r5, #MMDC0_MPMUR0]
++ ldr r2, =MMDC1_MPMUR0
++ str r0, [r5, r2]
++
++ /* Wait for FRC_MSR to clear. */
++1:
++ ldr r0, [r5, #MMDC0_MPMUR0]
++ and r0, r0, #0x800
++ ldr r1, [r5, r2]
++ and r1, r1, #0x800
++ orr r0, r0, r1
++ cmp r0, #0x0
++ bne 1b
++
++ /* clear SBS - unblock DDR accesses. */
++ ldr r0, [r5, #MMDC0_MADPCR0]
++ bic r0, r0, #(1 << 8)
++ str r0, [r5, #MMDC0_MADPCR0]
++
++ mov r0, #0x0
++ str r0, [r5, #MMDC0_MDSCR]
++poll_conreq_clear_2:
++ ldr r0, [r5, #MMDC0_MDSCR]
++ and r0, r0, #(0x4 << 12)
++ cmp r0, #(0x4 << 12)
++ beq poll_conreq_clear_2
++
++done:
++ /* MMDC0_MAPSR adopt power down enable. */
++ ldr r0, [r5, #MMDC0_MAPSR]
++ bic r0, r0, #0x01
++ str r0, [r5, #MMDC0_MAPSR]
++
++#ifdef CONFIG_CACHE_L2X0
++ /* Enable L2. */
++ ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++ ldr r6, =0x1
++ str r6, [r7, #0x100]
++ isb
++ dsb
++#endif
++
++ /* Enable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Restore the TTBCR */
++ dsb
++ isb
++
++ /* Read TTBCR and set PD0=0, N = 0 */
++ mrc p15, 0, r6, c2, c0, 2
++ bic r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++ /* Enable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ isb
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++ isb
++ dsb
++
++ /* restore registers */
++ ldmfd sp!, {r4-r12}
++ mov pc, lr
++
++ /*
++ * Add ltorg here to ensure that all
++ * literals are stored here and are
++ * within the text space.
++ */
++ .ltorg
++mx6_ddr3_freq_change_end:
++
++#ifdef CONFIG_SMP
++ .align 3
++
++ENTRY(wfe_ddr3_freq_change)
++wfe_ddr3_freq_change_start:
++ push {r4 - r11, lr}
++
++ mov r6, r0
++ mov r7, r1
++
++ dsb
++ isb
++
++ disable_l1_dcache
++
++ isb
++
++ /* Turn off SMP bit. */
++ mrc p15, 0, r8, c1, c0, 1
++ bic r8, r8, #0x40
++ mcr p15, 0, r8, c1, c0, 1
++
++ isb
++
++ /* Inform the SCU we are going to enter WFE. */
++ push {r0 - r11, lr}
++
++ ldr r0,=imx_scu_base
++ ldr r0, [r0]
++ mov r1, #SCU_PM_DORMANT
++ ldr r3, =scu_power_mode
++ mov lr, pc
++ mov pc, r3
++
++ pop {r0 - r11, lr}
++
++go_back_wfe:
++ wfe
++
++ ldr r3, [r7]
++ cmp r3, #1
++ beq go_back_wfe
++
++ /* Turn ON SMP bit. */
++ mrc p15, 0, r8, c1, c0, 1
++ orr r8, r8, #0x40
++ mcr p15, 0, r8, c1, c0, 1
++
++ isb
++ /* Enable L1 data cache. */
++ mrc p15, 0, r8, c1, c0, 0
++ orr r8, r8, #0x4
++ mcr p15, 0, r8, c1, c0, 0
++ isb
++
++ /* Inform the SCU we have exited WFE. */
++ push {r0 - r11, lr}
++
++ ldr r0,=imx_scu_base
++ ldr r0, [r0]
++ mov r1, #SCU_PM_NORMAL
++ ldr r3, =scu_power_mode
++ mov lr, pc
++ mov pc, r3
++
++ pop {r0 - r11, lr}
++
++ /* Pop all saved registers. */
++ pop {r4 - r11, lr}
++ mov pc, lr
++ .ltorg
++wfe_ddr3_freq_change_end:
++#endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/ddr3_freq_imx6sx.S linux-3.14.72/arch/arm/mach-imx/ddr3_freq_imx6sx.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/ddr3_freq_imx6sx.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/ddr3_freq_imx6sx.S 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,714 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/linkage.h>
++#include "hardware.h"
++
++.globl imx6sx_ddr3_freq_change_start
++.globl imx6sx_ddr3_freq_change_end
++
++#define MMDC0_MDPDC 0x4
++#define MMDC0_MDCF0 0xc
++#define MMDC0_MDCF1 0x10
++#define MMDC0_MDMISC 0x18
++#define MMDC0_MDSCR 0x1c
++#define MMDC0_MAPSR 0x404
++#define MMDC0_MADPCR0 0x410
++#define MMDC0_MPZQHWCTRL 0x800
++#define MMDC0_MPODTCTRL 0x818
++#define MMDC0_MPDGCTRL0 0x83c
++#define MMDC0_MPMUR0 0x8b8
++
++#define CCM_CBCDR 0x14
++#define CCM_CBCMR 0x18
++#define CCM_CSCMR1 0x1c
++#define CCM_CDHIPR 0x48
++
++#define L2_CACHE_SYNC 0x730
++
++#define BUSFREQ_INFO_FREQ_OFFSET 0x0
++#define BUSFREQ_INFO_DDR_SETTINGS_OFFSET 0x4
++#define BUSFREQ_INFO_DLL_OFF_OFFSET 0x8
++#define BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET 0xc
++#define BUSFREQ_INFO_MU_DELAY_OFFSET 0x10
++
++.extern iram_tlb_phys_addr
++
++ .align 3
++
++ .macro do_delay
++
++1:
++ ldr r9, =0
++2:
++ ldr r10, [r4, r9]
++ add r9, r9, #4
++ cmp r9, #16
++ bne 2b
++ sub r8, r8, #1
++ cmp r8, #0
++ bgt 1b
++
++ .endm
++
++ .macro wait_for_ccm_handshake
++
++3:
++ ldr r8, [r5, #CCM_CDHIPR]
++ cmp r8, #0
++ bne 3b
++
++ .endm
++
++ .macro switch_to_400MHz
++
++ /* check whether periph2_clk is already from top path */
++ ldr r8, [r5, #CCM_CBCDR]
++ ands r8, #(1 << 26)
++ beq skip_periph2_clk2_switch_400m
++
++ /* now switch periph2_clk back. */
++ ldr r8, [r5, #CCM_CBCDR]
++ bic r8, r8, #(1 << 26)
++ str r8, [r5, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ /*
++ * on i.MX6SX, pre_periph2_clk will be always from
++ * pll2_pfd2, so no need to set pre_periph2_clk
++ * parent, just set the mmdc divider directly.
++ */
++skip_periph2_clk2_switch_400m:
++
++ /* fabric_mmdc_podf to 0 */
++ ldr r8, [r5, #CCM_CBCDR]
++ bic r8, r8, #(0x7 << 3)
++ str r8, [r5, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ .endm
++
++ .macro switch_to_50MHz
++
++ /* check whether periph2_clk is already from top path */
++ ldr r8, [r5, #CCM_CBCDR]
++ ands r8, #(1 << 26)
++ beq skip_periph2_clk2_switch_50m
++
++ /* now switch periph2_clk back. */
++ ldr r8, [r5, #CCM_CBCDR]
++ bic r8, r8, #(1 << 26)
++ str r8, [r5, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ /*
++ * on i.MX6SX, pre_periph2_clk will be always from
++ * pll2_pfd2, so no need to set pre_periph2_clk
++ * parent, just set the mmdc divider directly.
++ */
++skip_periph2_clk2_switch_50m:
++
++ /* fabric_mmdc_podf to 7 so that mmdc is 400 / 8 = 50MHz */
++ ldr r8, [r5, #CCM_CBCDR]
++ orr r8, r8, #(0x7 << 3)
++ str r8, [r5, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ .endm
++
++ .macro switch_to_24MHz
++
++ /* periph2_clk2 sel to OSC_CLK */
++ ldr r8, [r5, #CCM_CBCMR]
++ orr r8, r8, #(1 << 20)
++ str r8, [r5, #CCM_CBCMR]
++
++ /* periph2_clk2_podf to 0 */
++ ldr r8, [r5, #CCM_CBCDR]
++ bic r8, r8, #0x7
++ str r8, [r5, #CCM_CBCDR]
++
++ /* periph2_clk sel to periph2_clk2 */
++ ldr r8, [r5, #CCM_CBCDR]
++ orr r8, r8, #(0x1 << 26)
++ str r8, [r5, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ /* fabric_mmdc_podf to 0 */
++ ldr r8, [r5, #CCM_CBCDR]
++ bic r8, r8, #(0x7 << 3)
++ str r8, [r5, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ .endm
++
++/*
++ * imx6sx_ddr3_freq_change
++ *
++ * idle the processor (eg, wait for interrupt).
++ * make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ */
++ENTRY(imx6sx_ddr3_freq_change)
++
++imx6sx_ddr3_freq_change_start:
++ stmfd sp!, {r4 - r11}
++
++ ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET]
++ ldr r2, [r0, #BUSFREQ_INFO_DLL_OFF_OFFSET]
++ ldr r3, [r0, #BUSFREQ_INFO_IOMUX_OFFSETS_OFFSET]
++
++ /*
++ * To ensure no page table walks occur in DDR, we
++ * have a another page table stored in IRAM that only
++ * contains entries pointing to IRAM, AIPS1 and AIPS2.
++ * We need to set the TTBR1 to the new IRAM TLB.
++ * Do the following steps:
++ * 1. Flush the Branch Target Address Cache (BTAC)
++ * 2. Set TTBR1 to point to IRAM page table.
++ * 3. Disable page table walks in TTBR0 (PD0 = 1)
++ * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
++ * and 2-4G is translated by TTBR1.
++ */
++
++ ldr r6, =iram_tlb_phys_addr
++ ldr r7, [r6]
++
++ /* Disable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ dsb
++ isb
++
++ /* Store the IRAM table in TTBR1 */
++ mcr p15, 0, r7, c2, c0, 1
++
++ /* Read TTBCR and set PD0=1, N = 1 */
++ mrc p15, 0, r6, c2, c0, 2
++ orr r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++ /* Disable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ ldr r4, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
++ ldr r5, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
++ ldr r6, =IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR)
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * make sure the L2 buffers are drained,
++ * sync operation on L2 drains the buffers.
++ */
++ ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++
++ /* Wait for background operations to complete. */
++wait_for_l2_to_idle:
++ ldr r7, [r8, #0x730]
++ cmp r7, #0x0
++ bne wait_for_l2_to_idle
++
++ mov r7, #0x0
++ str r7, [r8, #L2_CACHE_SYNC]
++
++ /* Disable L2. */
++ mov r7, #0x0
++ str r7, [r8, #0x100]
++
++ /*
++ * The second dsb might be needed to keep cache sync (device write)
++ * ordering with the memory accesses before it.
++ */
++ dsb
++ isb
++#endif
++
++ /* disable automatic power saving. */
++ ldr r8, [r4, #MMDC0_MAPSR]
++ orr r8, r8, #0x1
++ str r8, [r4, #MMDC0_MAPSR]
++
++ /* disable MMDC power down timer. */
++ ldr r8, [r4, #MMDC0_MDPDC]
++ bic r8, r8, #(0xff << 8)
++ str r8, [r4, #MMDC0_MDPDC]
++
++ /* delay for a while */
++ ldr r8, =4
++ do_delay
++
++ /* set CON_REG */
++ ldr r8, =0x8000
++ str r8, [r4, #MMDC0_MDSCR]
++poll_conreq_set_1:
++ ldr r8, [r4, #MMDC0_MDSCR]
++ and r8, r8, #(0x4 << 12)
++ cmp r8, #(0x4 << 12)
++ bne poll_conreq_set_1
++
++ /*
++ * if requested frequency is greater than
++ * 300MHz go to DLL on mode.
++ */
++ ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET]
++ ldr r9, =300000000
++ cmp r8, r9
++ bge dll_on_mode
++
++dll_off_mode:
++ /* if DLL is currently on, turn it off. */
++ cmp r2, #1
++ beq continue_dll_off_1
++
++ ldr r8, =0x00018031
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x00018039
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =10
++ do_delay
++
++continue_dll_off_1:
++ /* set DVFS - enter self refresh mode */
++ ldr r8, [r4, #MMDC0_MAPSR]
++ orr r8, r8, #(1 << 21)
++ str r8, [r4, #MMDC0_MAPSR]
++
++ /* de-assert con_req */
++ mov r8, #0x0
++ str r8, [r4, #MMDC0_MDSCR]
++
++poll_dvfs_set_1:
++ ldr r8, [r4, #MMDC0_MAPSR]
++ and r8, r8, #(1 << 25)
++ cmp r8, #(1 << 25)
++ bne poll_dvfs_set_1
++
++ ldr r8, [r0, #BUSFREQ_INFO_FREQ_OFFSET]
++ ldr r9, =24000000
++ cmp r8, r9
++ beq switch_freq_24
++
++ switch_to_50MHz
++ b continue_dll_off_2
++
++switch_freq_24:
++ switch_to_24MHz
++
++continue_dll_off_2:
++ /* set SBS - block ddr accesses */
++ ldr r8, [r4, #MMDC0_MADPCR0]
++ orr r8, r8, #(1 << 8)
++ str r8, [r4, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit from self refresh mode */
++ ldr r8, [r4, #MMDC0_MAPSR]
++ bic r8, r8, #(1 << 21)
++ str r8, [r4, #MMDC0_MAPSR]
++
++poll_dvfs_clear_1:
++ ldr r8, [r4, #MMDC0_MAPSR]
++ and r8, r8, #(1 << 25)
++ cmp r8, #(1 << 25)
++ beq poll_dvfs_clear_1
++
++ /* if DLL was previously on, continue DLL off routine. */
++ cmp r2, #1
++ beq continue_dll_off_3
++
++ ldr r8, =0x00018031
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x00018039
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x04208030
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x04208038
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x00088032
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x0008803A
++ str r8, [r4, #MMDC0_MDSCR]
++
++ /* delay for a while. */
++ ldr r8, =4
++ do_delay
++
++ ldr r8, [r4, #MMDC0_MDCF0]
++ bic r8, r8, #0xf
++ orr r8, r8, #0x3
++ str r8, [r4, #MMDC0_MDCF0]
++
++ ldr r8, [r4, #MMDC0_MDCF1]
++ bic r8, r8, #0x7
++ orr r8, r8, #0x4
++ str r8, [r4, #MMDC0_MDCF1]
++
++ ldr r8, =0x00091680
++ str r8, [r4, #MMDC0_MDMISC]
++
++ /* enable dqs pull down in the IOMUX. */
++ ldr r8, [r3]
++ add r3, r3, #8
++ ldr r9, =0x3028
++update_iomux:
++ ldr r10, [r3]
++ ldr r11, [r6, r10]
++ bic r11, r11, r9
++ orr r11, r11, #(0x3 << 12)
++ orr r11, r11, #0x28
++ str r11, [r6, r10]
++ add r3, r3, #8
++ sub r8, r8, #1
++ cmp r8, #0
++ bgt update_iomux
++
++ /* ODT disabled. */
++ ldr r8, =0x0
++ str r8, [r4, #MMDC0_MPODTCTRL]
++
++ /* DQS gating disabled. */
++ ldr r8, [r4, #MMDC0_MPDGCTRL0]
++ orr r8, r8, #(1 << 29)
++ str r8, [r4, #MMDC0_MPDGCTRL0]
++
++ /* Add workaround for ERR005778.*/
++ /* double the original MU_UNIT_DEL_NUM. */
++ ldr r8, [r0, #BUSFREQ_INFO_MU_DELAY_OFFSET]
++ lsl r8, r8, #1
++
++ /* Bypass the automatic MU by setting the mu_byp_en */
++ ldr r10, [r4, #MMDC0_MPMUR0]
++ orr r10, r10, #0x400
++ /* Set the MU_BYP_VAL */
++ orr r10, r10, r8
++ str r10, [r4, #MMDC0_MPMUR0]
++
++ /* Now perform a force measure */
++ ldr r8, [r4, #MMDC0_MPMUR0]
++ orr r8, r8, #0x800
++ str r8, [r4, #MMDC0_MPMUR0]
++ /* Wait for FRC_MSR to clear. */
++1:
++ ldr r8, [r4, #MMDC0_MPMUR0]
++ and r8, r8, #0x800
++ cmp r8, #0x0
++ bne 1b
++
++continue_dll_off_3:
++ /* clear SBS - unblock accesses to DDR. */
++ ldr r8, [r4, #MMDC0_MADPCR0]
++ bic r8, r8, #(0x1 << 8)
++ str r8, [r4, #MMDC0_MADPCR0]
++
++ mov r8, #0x0
++ str r8, [r4, #MMDC0_MDSCR]
++poll_conreq_clear_1:
++ ldr r8, [r4, #MMDC0_MDSCR]
++ and r8, r8, #(0x4 << 12)
++ cmp r8, #(0x4 << 12)
++ beq poll_conreq_clear_1
++
++ b done
++
++dll_on_mode:
++ /* assert DVFS - enter self refresh mode. */
++ ldr r8, [r4, #MMDC0_MAPSR]
++ orr r8, r8, #(1 << 21)
++ str r8, [r4, #MMDC0_MAPSR]
++
++ /* de-assert CON_REQ. */
++ mov r8, #0x0
++ str r8, [r4, #MMDC0_MDSCR]
++
++ /* poll DVFS ack. */
++poll_dvfs_set_2:
++ ldr r8, [r4, #MMDC0_MAPSR]
++ and r8, r8, #(1 << 25)
++ cmp r8, #(1 << 25)
++ bne poll_dvfs_set_2
++
++ switch_to_400MHz
++
++ /* set SBS step-by-step mode. */
++ ldr r8, [r4, #MMDC0_MADPCR0]
++ orr r8, r8, #(1 << 8)
++ str r8, [r4, #MMDC0_MADPCR0]
++
++ /* clear DVFS - exit self refresh mode. */
++ ldr r8, [r4, #MMDC0_MAPSR]
++ bic r8, r8, #(1 << 21)
++ str r8, [r4, #MMDC0_MAPSR]
++
++poll_dvfs_clear_2:
++ ldr r8, [r4, #MMDC0_MAPSR]
++ ands r8, r8, #(1 << 25)
++ bne poll_dvfs_clear_2
++
++ /* if DLL is currently off, turn it back on. */
++ cmp r2, #0
++ beq update_calibration_only
++
++ ldr r8, =0xa5390003
++ str r8, [r4, #MMDC0_MPZQHWCTRL]
++
++ /* enable DQS gating. */
++ ldr r10, =MMDC0_MPDGCTRL0
++ ldr r8, [r4, r10]
++ bic r8, r8, #(1 << 29)
++ str r8, [r4, r10]
++
++ /* Now perform a force measure */
++ ldr r8, =0x00000800
++ str r8, [r4, #MMDC0_MPMUR0]
++ /* Wait for FRC_MSR to clear. */
++1:
++ ldr r8, [r4, #MMDC0_MPMUR0]
++ and r8, r8, #0x800
++ cmp r8, #0x0
++ bne 1b
++
++ /* disable dqs pull down in the IOMUX. */
++ ldr r8, [r3]
++ add r3, r3, #8
++update_iomux1:
++ ldr r10, [r3, #0x0]
++ ldr r11, [r3, #0x4]
++ str r11, [r6, r10]
++ add r3, r3, #8
++ sub r8, r8, #1
++ cmp r8, #0
++ bgt update_iomux1
++
++ /* config MMDC timings to 400MHz. */
++ ldr r1, [r0, #BUSFREQ_INFO_DDR_SETTINGS_OFFSET]
++ ldr r7, [r1]
++ add r1, r1, #8
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++
++ /* update MISC register: WALAT, RALAT */
++ ldr r8, =0x00081740
++ str r8, [r4, #MMDC0_MDMISC]
++
++ /* configure ddr devices to dll on, odt. */
++ ldr r8, =0x00028031
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x00028039
++ str r8, [r4, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r8, =4
++ do_delay
++
++ /* reset dll. */
++ ldr r8, =0x09208030
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x09208038
++ str r8, [r4, #MMDC0_MDSCR]
++
++ /* delay for while. */
++ ldr r8, =100
++ do_delay
++
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++
++ ldr r8, =0x00428031
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x00428039
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++
++ /* issue a zq command. */
++ ldr r8, =0x04008040
++ str r8, [r4, #MMDC0_MDSCR]
++
++ ldr r8, =0x04008048
++ str r8, [r4, #MMDC0_MDSCR]
++
++ /* MMDC ODT enable. */
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++
++ /* delay for while. */
++ ldr r8, =40
++ do_delay
++
++ /* enable MMDC power down timer. */
++ ldr r8, [r4, #MMDC0_MDPDC]
++ orr r8, r8, #(0x55 << 8)
++ str r8, [r4, #MMDC0_MDPDC]
++
++ b update_calibration
++
++update_calibration_only:
++ ldr r8, [r1]
++ sub r8, r8, #7
++ add r1, r1, #64
++ b update_calib
++
++update_calibration:
++ /* write the new calibration values. */
++ mov r8, r7
++ sub r8, r8, #7
++
++update_calib:
++ ldr r10, [r1, #0x0]
++ ldr r11, [r1, #0x4]
++ str r11, [r4, r10]
++ add r1, r1, #8
++ sub r8, r8, #1
++ cmp r8, #0
++ bgt update_calib
++
++ /* perform a force measurement. */
++ ldr r8, =0x800
++ str r8, [r4, #MMDC0_MPMUR0]
++ /* Wait for FRC_MSR to clear. */
++1:
++ ldr r8, [r4, #MMDC0_MPMUR0]
++ and r8, r8, #0x800
++ cmp r8, #0x0
++ bne 1b
++
++ /* clear SBS - unblock DDR accesses. */
++ ldr r8, [r4, #MMDC0_MADPCR0]
++ bic r8, r8, #(1 << 8)
++ str r8, [r4, #MMDC0_MADPCR0]
++
++ mov r8, #0x0
++ str r8, [r4, #MMDC0_MDSCR]
++poll_conreq_clear_2:
++ ldr r8, [r4, #MMDC0_MDSCR]
++ and r8, r8, #(0x4 << 12)
++ cmp r8, #(0x4 << 12)
++ beq poll_conreq_clear_2
++
++done:
++
++ /* MMDC0_MAPSR adopt power down enable. */
++ ldr r8, [r4, #MMDC0_MAPSR]
++ bic r8, r8, #0x01
++ str r8, [r4, #MMDC0_MAPSR]
++
++#ifdef CONFIG_CACHE_L2X0
++ /* Enable L2. */
++ ldr r8, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++ ldr r7, =0x1
++ str r7, [r8, #0x100]
++#endif
++
++ /* Enable L1 data cache. */
++ mrc p15, 0, r7, c1, c0, 0
++ orr r7, r7, #0x4
++ mcr p15, 0, r7, c1, c0, 0
++
++ /* Restore the TTBCR */
++ dsb
++ isb
++
++ /* Read TTBCR and set PD0=0, N = 0 */
++ mrc p15, 0, r6, c2, c0, 2
++ bic r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++ /* Enable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r7, c1, c0, 0
++ orr r7, r7, #0x800
++ mcr p15, 0, r7, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r7, =0x0
++ mcr p15, 0, r7, c7, c1, 6
++
++ /* restore registers */
++ ldmfd sp!, {r4 - r11}
++ mov pc, lr
++
++ /*
++ * Add ltorg here to ensure that all
++ * literals are stored here and are
++ * within the text space.
++ */
++ .ltorg
++imx6sx_ddr3_freq_change_end:
++ENDPROC(imx6sx_ddr3_freq_change)
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/gpc.c linux-3.14.72/arch/arm/mach-imx/gpc.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/gpc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/gpc.c 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011-2013 Freescale Semiconductor, Inc.
++ * Copyright 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -10,30 +10,162 @@
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
++#include <linux/clk.h>
++#include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
++#include <linux/platform_device.h>
++#include <linux/pm_domain.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/irqchip/arm-gic.h>
+ #include "common.h"
++#include "hardware.h"
+
++#define GPC_CNTR 0x000
++#define GPC_CNTR_PCIE_PHY_PDU_SHIFT 0x7
++#define GPC_CNTR_PCIE_PHY_PDN_SHIFT 0x6
++#define PGC_PCIE_PHY_CTRL 0x200
++#define PGC_PCIE_PHY_PDN_EN 0x1
+ #define GPC_IMR1 0x008
++#define GPC_PGC_MF_PDN 0x220
++#define GPC_PGC_GPU_PDN 0x260
++#define GPC_PGC_GPU_PUPSCR 0x264
++#define GPC_PGC_GPU_PDNSCR 0x268
+ #define GPC_PGC_CPU_PDN 0x2a0
++#define GPC_PGC_DISP_PGCR_OFFSET 0x240
++#define GPC_PGC_DISP_PUPSCR_OFFSET 0x244
++#define GPC_PGC_DISP_PDNSCR_OFFSET 0x248
++#define GPC_PGC_DISP_SR_OFFSET 0x24c
++#define GPC_M4_LPSR 0x2c
++#define GPC_M4_LPSR_M4_SLEEPING_SHIFT 4
++#define GPC_M4_LPSR_M4_SLEEPING_MASK 0x1
++#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK 0x1
++#define GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT 0
++#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK 0x1
++#define GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT 1
+
+ #define IMR_NUM 4
+
++#define GPU_VPU_PUP_REQ BIT(1)
++#define GPU_VPU_PDN_REQ BIT(0)
++
++#define GPC_CLK_MAX 10
++
++struct pu_domain {
++ struct generic_pm_domain base;
++ struct regulator *reg;
++ struct clk *clk[GPC_CLK_MAX];
++ int num_clks;
++};
++
++struct disp_domain {
++ struct generic_pm_domain base;
++ struct clk *clk[GPC_CLK_MAX];
++ int num_clks;
++};
++
+ static void __iomem *gpc_base;
++static u32 gpc_mf_irqs[IMR_NUM];
+ static u32 gpc_wake_irqs[IMR_NUM];
+ static u32 gpc_saved_imrs[IMR_NUM];
++static u32 gpc_mf_request_on[IMR_NUM];
++static u32 bypass;
++static DEFINE_SPINLOCK(gpc_lock);
++static struct notifier_block nb_pcie;
++
++void imx_gpc_add_m4_wake_up_irq(u32 irq, bool enable)
++{
++ unsigned int idx = irq / 32 - 1;
++ unsigned long flags;
++ u32 mask;
++
++ /* Sanity check for SPI irq */
++ if (irq < 32)
++ return;
++
++ mask = 1 << irq % 32;
++ spin_lock_irqsave(&gpc_lock, flags);
++ gpc_wake_irqs[idx] = enable ? gpc_wake_irqs[idx] | mask :
++ gpc_wake_irqs[idx] & ~mask;
++ spin_unlock_irqrestore(&gpc_lock, flags);
++}
++
++void imx_gpc_hold_m4_in_sleep(void)
++{
++ int val;
++ unsigned long timeout = jiffies + msecs_to_jiffies(500);
++
++ /* wait M4 in wfi before asserting hold request */
++ while (!imx_gpc_is_m4_sleeping())
++ if (time_after(jiffies, timeout))
++ pr_err("M4 is NOT in expected sleep!\n");
++
++ val = readl_relaxed(gpc_base + GPC_M4_LPSR);
++ val &= ~(GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK <<
++ GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT);
++ writel_relaxed(val, gpc_base + GPC_M4_LPSR);
++
++ timeout = jiffies + msecs_to_jiffies(500);
++ while (readl_relaxed(gpc_base + GPC_M4_LPSR)
++ & (GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_MASK <<
++ GPC_M4_LPSR_M4_SLEEP_HOLD_ACK_SHIFT))
++ if (time_after(jiffies, timeout))
++ pr_err("Wait M4 hold ack timeout!\n");
++}
+
+-void imx_gpc_pre_suspend(void)
++void imx_gpc_release_m4_in_sleep(void)
++{
++ int val;
++
++ val = readl_relaxed(gpc_base + GPC_M4_LPSR);
++ val |= GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_MASK <<
++ GPC_M4_LPSR_M4_SLEEP_HOLD_REQ_SHIFT;
++ writel_relaxed(val, gpc_base + GPC_M4_LPSR);
++}
++
++unsigned int imx_gpc_is_m4_sleeping(void)
++{
++ if (readl_relaxed(gpc_base + GPC_M4_LPSR) &
++ (GPC_M4_LPSR_M4_SLEEPING_MASK <<
++ GPC_M4_LPSR_M4_SLEEPING_SHIFT))
++ return 1;
++
++ return 0;
++}
++
++unsigned int imx_gpc_is_mf_mix_off(void)
++{
++ return readl_relaxed(gpc_base + GPC_PGC_MF_PDN);
++}
++
++static void imx_gpc_mf_mix_off(void)
++{
++ int i;
++
++ for (i = 0; i < IMR_NUM; i++)
++ if (((gpc_wake_irqs[i] | gpc_mf_request_on[i]) &
++ gpc_mf_irqs[i]) != 0)
++ return;
++
++ pr_info("Turn off M/F mix!\n");
++ /* turn off mega/fast mix */
++ writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN);
++}
++
++void imx_gpc_pre_suspend(bool arm_power_off)
+ {
+ void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
+ int i;
+
+ /* Tell GPC to power off ARM core when suspend */
+- writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
++ if (cpu_is_imx6sx() && arm_power_off)
++ imx_gpc_mf_mix_off();
++
++ if (arm_power_off)
++ writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+
+ for (i = 0; i < IMR_NUM; i++) {
+ gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
+@@ -48,6 +180,9 @@
+
+ /* Keep ARM core powered on for other low-power modes */
+ writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
++ /* Keep M/F mix powered on for other low-power modes */
++ if (cpu_is_imx6sx())
++ writel_relaxed(0x0, gpc_base + GPC_PGC_MF_PDN);
+
+ for (i = 0; i < IMR_NUM; i++)
+ writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);
+@@ -56,6 +191,7 @@
+ static int imx_gpc_irq_set_wake(struct irq_data *d, unsigned int on)
+ {
+ unsigned int idx = d->irq / 32 - 1;
++ unsigned long flags;
+ u32 mask;
+
+ /* Sanity check for SPI irq */
+@@ -63,8 +199,10 @@
+ return -EINVAL;
+
+ mask = 1 << d->irq % 32;
++ spin_lock_irqsave(&gpc_lock, flags);
+ gpc_wake_irqs[idx] = on ? gpc_wake_irqs[idx] | mask :
+ gpc_wake_irqs[idx] & ~mask;
++ spin_unlock_irqrestore(&gpc_lock, flags);
+
+ return 0;
+ }
+@@ -120,6 +258,46 @@
+ writel_relaxed(val, reg);
+ }
+
++static int imx_pcie_regulator_notify(struct notifier_block *nb,
++ unsigned long event,
++ void *ignored)
++{
++ u32 value = readl_relaxed(gpc_base + GPC_CNTR);
++
++ switch (event) {
++ case REGULATOR_EVENT_PRE_ENABLE:
++ value |= 1 << GPC_CNTR_PCIE_PHY_PDU_SHIFT;
++ writel_relaxed(value, gpc_base + GPC_CNTR);
++ break;
++ case REGULATOR_EVENT_PRE_DISABLE:
++ value |= 1 << GPC_CNTR_PCIE_PHY_PDN_SHIFT;
++ writel_relaxed(value, gpc_base + GPC_CNTR);
++ writel_relaxed(PGC_PCIE_PHY_PDN_EN,
++ gpc_base + PGC_PCIE_PHY_CTRL);
++ break;
++ default:
++ break;
++ }
++
++ return NOTIFY_OK;
++}
++
++int imx_gpc_mf_request_on(unsigned int irq, unsigned int on)
++{
++ unsigned int idx = irq / 32 - 1;
++ unsigned long flags;
++ u32 mask;
++
++ mask = 1 << (irq % 32);
++ spin_lock_irqsave(&gpc_lock, flags);
++ gpc_mf_request_on[idx] = on ? gpc_mf_request_on[idx] | mask :
++ gpc_mf_request_on[idx] & ~mask;
++ spin_unlock_irqrestore(&gpc_lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(imx_gpc_mf_request_on);
++
+ void __init imx_gpc_init(void)
+ {
+ struct device_node *np;
+@@ -133,8 +311,307 @@
+ for (i = 0; i < IMR_NUM; i++)
+ writel_relaxed(~0, gpc_base + GPC_IMR1 + i * 4);
+
++ /* Read supported wakeup source in M/F domain */
++ if (cpu_is_imx6sx()) {
++ of_property_read_u32_index(np, "fsl,mf-mix-wakeup-irq", 0,
++ &gpc_mf_irqs[0]);
++ of_property_read_u32_index(np, "fsl,mf-mix-wakeup-irq", 1,
++ &gpc_mf_irqs[1]);
++ of_property_read_u32_index(np, "fsl,mf-mix-wakeup-irq", 2,
++ &gpc_mf_irqs[2]);
++ of_property_read_u32_index(np, "fsl,mf-mix-wakeup-irq", 3,
++ &gpc_mf_irqs[3]);
++ if (!(gpc_mf_irqs[0] | gpc_mf_irqs[1] |
++ gpc_mf_irqs[2] | gpc_mf_irqs[3]))
++ pr_info("No wakeup source in Mega/Fast domain found!\n");
++ }
++
+ /* Register GPC as the secondary interrupt controller behind GIC */
+ gic_arch_extn.irq_mask = imx_gpc_irq_mask;
+ gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
+ gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
+ }
++
++#ifdef CONFIG_PM
++
++static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
++{
++ struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
++ int iso, iso2sw;
++ u32 val;
++
++ /* Read ISO and ISO2SW power down delays */
++ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
++ iso = val & 0x3f;
++ iso2sw = (val >> 8) & 0x3f;
++
++ /* Gate off PU domain when GPU/VPU when powered down */
++ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
++
++ /* Request GPC to power down GPU/VPU */
++ val = readl_relaxed(gpc_base + GPC_CNTR);
++ val |= GPU_VPU_PDN_REQ;
++ writel_relaxed(val, gpc_base + GPC_CNTR);
++
++ /* Wait ISO + ISO2SW IPG clock cycles */
++ ndelay((iso + iso2sw) * 1000 / 66);
++
++ if (pu->reg)
++ regulator_disable(pu->reg);
++
++ return 0;
++}
++
++static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
++{
++ struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
++ int i, ret, sw, sw2iso;
++ u32 val;
++
++ if (pu->reg) {
++ ret = regulator_enable(pu->reg);
++ if (ret) {
++ pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
++ return ret;
++ }
++ }
++ /* Enable reset clocks for all devices in the PU domain */
++ for (i = 0; i < pu->num_clks; i++)
++ clk_prepare_enable(pu->clk[i]);
++
++ /* Gate off PU domain when GPU/VPU when powered down */
++ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
++
++ /* Read ISO and ISO2SW power down delays */
++ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
++ sw = val & 0x3f;
++ sw2iso = (val >> 8) & 0x3f;
++
++ /* Request GPC to power up GPU/VPU */
++ val = readl_relaxed(gpc_base + GPC_CNTR);
++ val |= GPU_VPU_PUP_REQ;
++ writel_relaxed(val, gpc_base + GPC_CNTR);
++
++ /* Wait ISO + ISO2SW IPG clock cycles */
++ ndelay((sw + sw2iso) * 1000 / 66);
++
++ /* Disable reset clocks for all devices in the PU domain */
++ for (i = 0; i < pu->num_clks; i++)
++ clk_disable_unprepare(pu->clk[i]);
++
++ return 0;
++}
++
++static int imx_pm_dispmix_on(struct generic_pm_domain *genpd)
++{
++ struct disp_domain *disp = container_of(genpd, struct disp_domain, base);
++ u32 val = readl_relaxed(gpc_base + GPC_CNTR);
++ int i;
++
++ if ((cpu_is_imx6sl() &&
++ imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) {
++
++ /* Enable reset clocks for all devices in the disp domain */
++ for (i = 0; i < disp->num_clks; i++)
++ clk_prepare_enable(disp->clk[i]);
++
++ writel_relaxed(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
++ writel_relaxed(0x20 | val, gpc_base + GPC_CNTR);
++ while (readl_relaxed(gpc_base + GPC_CNTR) & 0x20)
++ ;
++
++ writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET);
++
++ /* Disable reset clocks for all devices in the disp domain */
++ for (i = 0; i < disp->num_clks; i++)
++ clk_disable_unprepare(disp->clk[i]);
++ }
++ return 0;
++}
++
++static int imx_pm_dispmix_off(struct generic_pm_domain *genpd)
++{
++ struct disp_domain *disp = container_of(genpd, struct disp_domain, base);
++ u32 val = readl_relaxed(gpc_base + GPC_CNTR);
++ int i;
++
++ if ((cpu_is_imx6sl() &&
++ imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2) || cpu_is_imx6sx()) {
++
++ /* Enable reset clocks for all devices in the disp domain */
++ for (i = 0; i < disp->num_clks; i++)
++ clk_prepare_enable(disp->clk[i]);
++
++ writel_relaxed(0xFFFFFFFF,
++ gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET);
++ writel_relaxed(0xFFFFFFFF,
++ gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET);
++ writel_relaxed(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET);
++ writel_relaxed(0x10 | val, gpc_base + GPC_CNTR);
++ while (readl_relaxed(gpc_base + GPC_CNTR) & 0x10)
++ ;
++
++ /* Disable reset clocks for all devices in the disp domain */
++ for (i = 0; i < disp->num_clks; i++)
++ clk_disable_unprepare(disp->clk[i]);
++ }
++ return 0;
++}
++
++static struct generic_pm_domain imx6q_arm_domain = {
++ .name = "ARM",
++};
++
++static struct pu_domain imx6q_pu_domain = {
++ .base = {
++ .name = "PU",
++ .power_off = imx6q_pm_pu_power_off,
++ .power_on = imx6q_pm_pu_power_on,
++ .power_off_latency_ns = 25000,
++ .power_on_latency_ns = 2000000,
++ },
++};
++
++static struct disp_domain imx6s_display_domain = {
++ .base = {
++ .name = "DISPLAY",
++ .power_off = imx_pm_dispmix_off,
++ .power_on = imx_pm_dispmix_on,
++ },
++};
++
++static struct generic_pm_domain *imx_gpc_domains[] = {
++ &imx6q_arm_domain,
++ &imx6q_pu_domain.base,
++ &imx6s_display_domain.base,
++};
++
++static struct genpd_onecell_data imx_gpc_onecell_data = {
++ .domains = imx_gpc_domains,
++ .num_domains = ARRAY_SIZE(imx_gpc_domains),
++};
++
++static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
++{
++ struct clk *clk;
++ bool is_off;
++ int pu_clks, disp_clks;
++ int i = 0, k = 0;
++
++ imx6q_pu_domain.base.of_node = dev->of_node;
++ imx6q_pu_domain.reg = pu_reg;
++
++ imx6s_display_domain.base.of_node = dev->of_node;
++
++ if ((cpu_is_imx6sl() &&
++ imx_get_soc_revision() >= IMX_CHIP_REVISION_1_2)) {
++ pu_clks = 2 ;
++ disp_clks = 6;
++ } else if (cpu_is_imx6sx()) {
++ pu_clks = 1;
++ disp_clks = 8;
++ } else {
++ pu_clks = GPC_CLK_MAX;
++ disp_clks = 0;
++ }
++
++ /* Get pu domain clks */
++ for (i = 0; i < pu_clks ; i++) {
++ clk = of_clk_get(dev->of_node, i);
++ if (IS_ERR(clk))
++ break;
++ imx6q_pu_domain.clk[i] = clk;
++ }
++ imx6q_pu_domain.num_clks = i;
++
++ /* Get disp domain clks */
++ for (k = 0, i = pu_clks; i < pu_clks + disp_clks ; i++, k++) {
++ clk = of_clk_get(dev->of_node, i);
++ if (IS_ERR(clk))
++ break;
++ imx6s_display_domain.clk[k] = clk;
++ }
++ imx6s_display_domain.num_clks = k;
++
++ is_off = IS_ENABLED(CONFIG_PM_RUNTIME);
++ if (is_off)
++ imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
++
++ pm_genpd_init(&imx6q_pu_domain.base, NULL, is_off);
++ pm_genpd_init(&imx6s_display_domain.base, NULL, is_off);
++
++ return __of_genpd_add_provider(dev->of_node, __of_genpd_xlate_onecell,
++ &imx_gpc_onecell_data);
++
++}
++
++#else
++static inline int imx_gpc_genpd_init(struct device *dev, struct regulator *reg)
++{
++ return 0;
++}
++#endif /* CONFIG_PM */
++
++static int imx_gpc_probe(struct platform_device *pdev)
++{
++ struct regulator *pu_reg;
++ int ret;
++
++ of_property_read_u32(pdev->dev.of_node, "fsl,ldo-bypass", &bypass);
++ pu_reg = devm_regulator_get(&pdev->dev, "pu");
++ if (!IS_ERR(pu_reg)) {
++ /* The regulator is initially enabled */
++ ret = regulator_enable(pu_reg);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to enable pu regulator: %d\n", ret);
++ return ret;
++ }
++ /* We only bypass pu since arm and soc has been set in u-boot */
++ if (bypass)
++ regulator_allow_bypass(pu_reg, true);
++ } else {
++ pu_reg = NULL;
++ }
++
++ if (cpu_is_imx6sx()) {
++ struct regulator *pcie_reg;
++
++ pcie_reg = devm_regulator_get(&pdev->dev, "pcie-phy");
++ if (IS_ERR(pcie_reg)) {
++ ret = PTR_ERR(pcie_reg);
++ dev_info(&pdev->dev, "pcie regulator not ready.\n");
++ return ret;
++ }
++ nb_pcie.notifier_call = &imx_pcie_regulator_notify;
++
++ ret = regulator_register_notifier(pcie_reg, &nb_pcie);
++ if (ret) {
++ dev_err(&pdev->dev,
++ "pcie regulator notifier request failed\n");
++ return ret;
++ }
++ }
++
++ return imx_gpc_genpd_init(&pdev->dev, pu_reg);
++}
++
++static struct of_device_id imx_gpc_dt_ids[] = {
++ { .compatible = "fsl,imx6q-gpc" },
++ { .compatible = "fsl,imx6sl-gpc" },
++ { }
++};
++
++static struct platform_driver imx_gpc_driver = {
++ .driver = {
++ .name = "imx-gpc",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_gpc_dt_ids,
++ },
++ .probe = imx_gpc_probe,
++};
++
++static int __init imx_pgc_init(void)
++{
++ return platform_driver_register(&imx_gpc_driver);
++}
++subsys_initcall(imx_pgc_init);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/hardware.h linux-3.14.72/arch/arm/mach-imx/hardware.h
+--- linux-3.14.72.orig/arch/arm/mach-imx/hardware.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/hardware.h 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2007, 2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+@@ -20,7 +20,9 @@
+ #ifndef __ASM_ARCH_MXC_HARDWARE_H__
+ #define __ASM_ARCH_MXC_HARDWARE_H__
+
++#ifndef __ASSEMBLY__
+ #include <asm/io.h>
++#endif
+ #include <asm/sizes.h>
+
+ #define addr_in_module(addr, mod) \
+@@ -87,17 +89,16 @@
+ * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
+ * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
+ * mx6q:
+- * SCU 0x00a00000+0x004000 -> 0xf4000000+0x004000
++ * SCU 0x00a00000+0x004000 -> 0xf4a00000+0x004000
+ * CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
+ * ANATOP 0x020c8000+0x004000 -> 0xf42c8000+0x004000
+- * UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
++ * UART4 0x021f0000+0x004000 -> 0xf43f0000+0x004000
+ */
+-#define IMX_IO_P2V(x) ( \
+- (((x) & 0x80000000) >> 7) | \
+- (0xf4000000 + \
+- (((x) & 0x50000000) >> 6) + \
+- (((x) & 0x0b000000) >> 4) + \
+- (((x) & 0x000fffff))))
++#define IMX_IO_P2V(x) ( \
++ (0xf4000000 + \
++ (((x) & 0x50000000) >> 4) + \
++ (((x) & 0x0a000000) >> 4) + \
++ (((x) & 0x00ffffff))))
+
+ #define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
+
+@@ -113,6 +114,7 @@
+ #include "mx27.h"
+ #include "mx1.h"
+ #include "mx25.h"
++#include "mx6.h"
+
+ #define imx_map_entry(soc, name, _type) { \
+ .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/headsmp.S linux-3.14.72/arch/arm/mach-imx/headsmp.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/headsmp.S 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/headsmp.S 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -14,8 +14,12 @@
+ #include <linux/init.h>
+ #include <asm/asm-offsets.h>
+ #include <asm/hardware/cache-l2x0.h>
++#include <asm/smp_scu.h>
++
++#define SCU_CPU_STATUS 0x08
+
+ .section ".text.head", "ax"
++.extern imx_scu_base
+
+ #ifdef CONFIG_SMP
+ diag_reg_offset:
+@@ -32,6 +36,16 @@
+ ENTRY(v7_secondary_startup)
+ bl v7_invalidate_l1
+ set_diag_reg
++
++ /* Set the CPU status in SCU CPU status register. */
++ mrc p15, 0, r0, c0, c0, 5
++ and r0, r0, #3
++ mrc p15, 4, r1, c15, c0, 0
++ ldr r2, =SCU_CPU_STATUS
++ orr r2, r2, r0
++ ldr r0, =SCU_PM_NORMAL
++ strb r0, [r1, r2]
++
+ b secondary_startup
+ ENDPROC(v7_secondary_startup)
+ #endif
+@@ -51,6 +65,10 @@
+ ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
+ ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
+ str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
++ ldr r1, [r2, #L2X0_R_TAG_LATENCY] @ get tag latency value
++ str r1, [r0, #L2X0_TAG_LATENCY_CTRL] @ restore tag latency
++ ldr r1, [r2, #L2X0_R_DATA_LATENCY] @ get data latency value
++ str r1, [r0, #L2X0_DATA_LATENCY_CTRL] @ restore data latency
+ mov r1, #0x1
+ str r1, [r0, #L2X0_CTRL] @ re-enable L2
+ .endm
+@@ -62,10 +80,4 @@
+ .macro pl310_resume
+ .endm
+ #endif
+-
+-ENTRY(v7_cpu_resume)
+- bl v7_invalidate_l1
+- pl310_resume
+- b cpu_resume
+-ENDPROC(v7_cpu_resume)
+ #endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/hotplug.c linux-3.14.72/arch/arm/mach-imx/hotplug.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/hotplug.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/hotplug.c 2016-06-19 22:11:55.049156848 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -14,9 +14,12 @@
+ #include <linux/jiffies.h>
+ #include <asm/cp15.h>
+ #include <asm/proc-fns.h>
++#include <asm/smp_scu.h>
+
+ #include "common.h"
+
++extern void __iomem *imx_scu_base;
++
+ static inline void cpu_enter_lowpower(void)
+ {
+ unsigned int v;
+@@ -36,6 +39,8 @@
+ : "=&r" (v)
+ : "r" (0), "Ir" (CR_C), "Ir" (0x40)
+ : "cc");
++
++ scu_power_mode(imx_scu_base, SCU_PM_DORMANT);
+ }
+
+ /*
+@@ -52,8 +57,7 @@
+ * the register being cleared to kill the cpu.
+ */
+ imx_set_cpu_arg(cpu, ~0);
+-
+- while (1)
++ for (;;)
+ cpu_do_idle();
+ }
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/imx6sl_lpm_wfi.S linux-3.14.72/arch/arm/mach-imx/imx6sl_lpm_wfi.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/imx6sl_lpm_wfi.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/imx6sl_lpm_wfi.S 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,777 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the license, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in teh hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/linkage.h>
++
++#define PM_INFO_PM_INFO_SIZE_OFFSET 0x0
++#define PM_INFO_TTBR_OFFSET 0x4
++#define PM_INFO_MMDC_V_OFFSET 0x8
++#define PM_INFO_IOMUXC_V_OFFSET 0xc
++#define PM_INFO_CCM_V_OFFSET 0x10
++#define PM_INFO_L2_V_OFFSET 0x14
++#define PM_INFO_ANATOP_V_OFFSET 0x18
++#define PM_INFO_IO_NUM_OFFSET 0x1c
++#define PM_INFO_IO_VAL_OFFSET 0x20
++
++#define MX6Q_MMDC_MAPSR 0x404
++#define MX6Q_MMDC_MPDGCTRL0 0x83c
++
++.global mx6sl_lpm_wfi_start
++.global mx6sl_lpm_wfi_end
++
++ .macro pll_do_wait_lock
++1:
++ ldr r7, [r10, r8]
++ ands r7, #0x80000000
++ beq 1b
++
++ .endm
++
++ .macro ccm_do_wait
++2:
++ ldr r7, [r10, #0x48]
++ cmp r7, #0x0
++ bne 2b
++
++ .endm
++
++ .macro ccm_enter_idle
++
++ ldr r10, [r0, #PM_INFO_CCM_V_OFFSET]
++ /*
++ * if in audio_bus_freq_mode, skip to
++ * audio_mode low power setting.
++ */
++ cmp r1, #0x1
++ beq audio_mode
++ /*
++ * Now set DDR rate to 1MHz.
++ * DDR is from bypassed PLL2 on periph2_clk2 path.
++ * Set the periph2_clk2_podf to divide by 8.
++ */
++ ldr r6, [r10, #0x14]
++ orr r6, r6, #0x07
++ str r6, [r10, #0x14]
++
++ /* Now set MMDC PODF to divide by 3. */
++ ldr r6, [r10, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, #0x10
++ str r6, [r10, #0x14]
++
++ ccm_do_wait
++
++ /* Set the AHB to 3MHz. AXI to 3MHz. */
++ ldr r6, [r10, #0x14]
++ /*r12 stores the origin AHB podf value */
++ mov r12, r6
++ orr r6, r6, #0x1c00
++ orr r6, r6, #0x70000
++ str r6, [r10, #0x14]
++
++ ccm_do_wait
++
++ /* Now set ARM to 24MHz.
++ * Move ARM to be sourced from step_clk
++ * after setting step_clk to 24MHz.
++ */
++ ldr r6, [r10, #0x0c]
++ bic r6, r6, #0x100
++ str r6, [r10, #0xc]
++ /*Now pll1_sw_clk to step_clk */
++ ldr r6, [r10, #0x0c]
++ orr r6, r6, #0x4
++ str r6, [r10, #0x0c]
++
++ /* Bypass PLL1 and power it down */
++ ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET]
++ ldr r6, =(1 << 16)
++ orr r6, r6, #0x1000
++ str r6, [r10, #0x04]
++
++ /*
++ * Set the ARM PODF to divide by 8.
++ * IPG is at 1.5MHz here, we need ARM to
++ * run at the 12:5 ratio (WAIT mode issue).
++ */
++ ldr r10, [r0, #PM_INFO_CCM_V_OFFSET]
++ ldr r11, [r10, #0x10]
++ ldr r6, =0x07
++ str r6, [r10, #0x10]
++
++ ccm_do_wait
++
++ b ccm_idle_done
++
++audio_mode:
++ /*
++ * MMDC is sourced from pll2_200M.
++ * Set the mmdc_podf to div by 8
++ */
++ ldr r10, [r0, #PM_INFO_CCM_V_OFFSET]
++ ldr r6, [r10, #0x14]
++ orr r6, r6, #0x38
++ str r6, [r10, #0x14]
++
++ ccm_do_wait
++
++ /*
++ * ARM is sourced from pll2_pfd2_400M here.
++ * switch ARM to bypassed PLL1
++ */
++ ldr r10, [r0, #PM_INFO_CCM_V_OFFSET]
++ ldr r6, [r10, #0x0c]
++ bic r6, r6, #0x4
++ str r6, [r10, #0xc]
++
++ /*
++ * set the arm_podf to divide by 3
++ * as IPG is at 4MHz, we cannot run
++ * arm clk above 9.6MHz when system
++ * enter WAIT mode
++ */
++ ldr r11, [r10, #0x10]
++ ldr r6, =0x2
++ str r6, [r10, #0x10]
++
++ ccm_do_wait
++
++ccm_idle_done:
++
++ .endm
++
++ .macro ccm_exit_idle
++
++ /*
++ * If in audio_bus_freq_mode, skip to
++ * audio_mode ccm restore.
++ */
++ cmp r1, #0x1
++ beq audio_ccm_restore
++
++ ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET]
++ /* Power up PLL1 and un-bypass it. */
++ ldr r6, =(1 << 12)
++ str r6, [r10, #0x08]
++
++ /* Wait for PLL1 to relock */
++ ldr r8, =0x0
++ pll_do_wait_lock
++
++ ldr r6, =(1 << 16)
++ str r6, [r10, #0x08]
++
++ ldr r10, [r0, #PM_INFO_CCM_V_OFFSET]
++ /* Set PLL1_sw_clk back to PLL1 */
++ ldr r6, [r10, #0x0c]
++ bic r6, r6, #0x4
++ str r6, [r10, #0x0c]
++
++ /* Restore AHB/AXI back */
++ str r12, [r10, #0x14]
++
++ ccm_do_wait
++
++ /* restore mmdc back to 24MHz*/
++ ldr r6, [r10, #0x14]
++ bic r6, r6, #0x3f
++ str r6, [r10, #0x14]
++
++ ccm_do_wait
++ b ccm_exit_done
++
++audio_ccm_restore:
++ /* move arm clk back to pll2_pfd2_400M */
++ ldr r6, [r10, #0xc]
++ orr r6, r6, #0x4
++ str r6, [r10, #0xc]
++
++ /* restore mmdc podf */
++ ldr r10, [r0, #PM_INFO_CCM_V_OFFSET]
++ ldr r6, [r10, #0x14]
++ bic r6, r6, #0x38
++ orr r6, #0x8
++ str r6, [r10, #0x14]
++
++ ccm_do_wait
++
++ccm_exit_done:
++
++ .endm
++
++ .macro check_pll_state
++
++ ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET]
++ /*
++ * Check whether any PLL is enabled, as only when
++ * there is no PLLs enabled, 2p5 can be off and
++ * only enable the weak one. PLL1 will be powered
++ * down late, so no need to check PLL1 state.
++ */
++
++ /* sys PLL2 */
++ ldr r6, [r10, #0x30]
++ ands r6, r6, #(1 << 31)
++ bne 1f
++
++ /* usb PLL3 */
++ ldr r6, [r10, #0x10]
++ ands r6, r6, #(1 << 31)
++ bne 1f
++
++ /* audio PLL4 */
++ ldr r6, [r10, #0x70]
++ ands r6, r6, #(1 << 31)
++ bne 1f
++
++ /* video PLL5 */
++ ldr r6, [r10, #0xa0]
++ ands r6, r6, #(1 << 31)
++ bne 1f
++
++ /* enet PLL6 */
++ ldr r6, [r10, #0xe0]
++ ands r6, r6, #(1 << 31)
++ bne 1f
++
++ /* usb host PLL7 */
++ ldr r6, [r10, #0x20]
++ ands r6, r6, #(1 << 31)
++ bne 1f
++
++ ldr r4, =0x1
++ b check_done
++1:
++ ldr r4, =0x0
++
++check_done:
++ .endm
++
++ .macro anatop_enter_idle
++
++ ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET]
++ cmp r4, #0x0
++ beq anatop_enter_done
++
++ /* Disable 1p1 brown out. */
++ ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET]
++ ldr r6, [r10, #0x110]
++ bic r6, r6, #0x2
++ str r6, [r10, #0x110]
++ /*
++ * Set the OSC bias current to -37.5%
++ * to drop the power on VDDHIGH.
++ */
++ ldr r6, [r10, #0x150]
++ orr r6, r6, #0xc000
++ str r6, [r10, #0x150]
++
++ /*
++ * if the usb VBUS wakeup is enabled, skip
++ * disable main 2p5.
++ */
++ cmp r2, #0x1
++ beq anatop_enter_done
++
++ /* Enable the week 2p5 */
++ ldr r6, [r10, #0x130]
++ orr r6, r6, #0x40000
++ str r6, [r10, #0x130]
++
++ /* Disable main 2p5. */
++ ldr r6, [r10, #0x130]
++ bic r6, r6, #0x1
++ str r6, [r10, #0x130]
++
++ /*
++ * Cannot diable regular bandgap
++ * in LDO-enable mode. The bandgap
++ * is required for ARM-LDO to regulate
++ * the voltage.
++ */
++ ldr r6, [r10, #0x140]
++ and r6, r6, #0x1f
++ cmp r6, #0x1f
++ bne anatop_enter_done
++
++ /* Enable low power bandgap */
++ ldr r6, [r10, #0x260]
++ orr r6, r6, #0x20
++ str r6, [r10, #0x260]
++
++ /*
++ * Turn off the bias current
++ * from the regular bandgap.
++ */
++ ldr r6, [r10, #0x260]
++ orr r6, r6, #0x80
++ str r6, [r10, #0x260]
++
++ /*
++ * Clear the REFTTOP+SELFBIASOFF,
++ * self_bais circuit of the band gap.
++ * Per RM, should be cleared when
++ * band gap is powered down.
++ */
++ ldr r6, [r10, #0x150]
++ bic r6, r6, #0x8
++ str r6, [r10, #0x150]
++
++ /* Power down the regular bandgap */
++ ldr r6, [r10, #0x150]
++ orr r6, r6, #0x1
++ str r6, [r10, #0x150]
++anatop_enter_done:
++
++ .endm
++
++ .macro anatop_exit_idle
++
++ ldr r10, [r0, #PM_INFO_ANATOP_V_OFFSET]
++ cmp r4, #0x0
++ beq skip_anatop_restore
++
++ cmp r2, #0x1
++ beq ldo2p5_not_disabled
++ /*
++ * Regular bandgap will not be disabled
++ * in LDO-enabled mode as it is required
++ * for ARM-LDO to reguulate the voltage.
++ */
++ ldr r6, [r10, #0x140]
++ and r6, r6, #0x1f
++ cmp r6, #0x1f
++ bne skip_bandgap_restore
++
++ /* Power up the regular bandgap */
++ ldr r6, [r10, #0x150]
++ bic r6, r6, #0x1
++ str r6, [r10, #0x150]
++
++ /* wait for bandgap stable */
++3:
++ ldr r6, [r10, #0x150]
++ and r6, r6, #0x80
++ cmp r6, #0x80
++ bne 3b
++
++ /* now disable bandgap self-bias circuit */
++ ldr r6, [r10, #0x150]
++ orr r6, r6, #0x8
++ str r6, [r10, #0x150]
++
++ /* Turn on the bias current
++ * from the regular bandgap.
++ */
++ ldr r6, [r10, #0x260]
++ bic r6, r6, #0x80
++ str r6, [r10, #0x260]
++
++ /* Disable the low power bandgap */
++ ldr r6, [r10, #0x260]
++ bic r6, r6, #0x20
++ str r6, [r10, #0x260]
++
++skip_bandgap_restore:
++ /* Enable main 2p5. */
++ ldr r6, [r10, #0x130]
++ orr r6, r6, #0x1
++ str r6, [r10, #0x130]
++
++ /* Ensure the 2p5 is up */
++5:
++ ldr r6, [r10, #0x130]
++ and r6, r6, #0x20000
++ cmp r6, #0x20000
++ bne 5b
++
++ /* Disable the weak 2p5 */
++ ldr r6, [r10, #0x130]
++ bic r6, r6, #0x40000
++ str r6, [r10, #0x130]
++
++ldo2p5_not_disabled:
++ /*
++ * Set the OSC bias current to max
++ * value for normal operation.
++ */
++ ldr r6, [r10, #0x150]
++ bic r6, r6, #0xc000
++ str r6, [r10, #0x150]
++
++ /* Enable 1p1 brown out, */
++ ldr r6, [r10, #0x110]
++ orr r6, r6, #0x2
++ str r6, [r10, #0x110]
++
++skip_anatop_restore:
++
++ .endm
++
++ .macro disable_l1_dcache
++
++ /* disable d-cache */
++ mrc p15, 0, r7, c1, c0, 0
++ bic r7, r7, #(1 << 2)
++ mcr p15, 0, r7, c1, c0, 0
++
++ dsb
++ isb
++
++ .endm
++
++ .macro mmdc_enter_dvfs_mode
++
++ /* disable automatic power saving. */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #0x1
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++
++ /* disable power down timer */
++ ldr r7, [r10, #0x04]
++ bic r7, r7, #0xff00
++ str r7, [r10, #0x04]
++
++ /* Make the DDR explicitly enter self-refresh. */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #(1 << 21)
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++
++poll_dvfs_set:
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ beq poll_dvfs_set
++
++ /* set SBS step-by step mode */
++ ldr r7, [r10, #0x410]
++ orr r7, r7, #0x100
++ str r7, [r10, #0x410]
++
++ .endm
++
++ .macro resume_mmdc
++ /* restore MMDC IO */
++ ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET]
++
++ ldr r6, [r0, #PM_INFO_IO_NUM_OFFSET]
++ ldr r7, =PM_INFO_IO_VAL_OFFSET
++ add r7, r7, r0
++6:
++ ldr r8, [r7], #0x4
++ ldr r9, [r7], #0x4
++ str r9, [r10, r8]
++ subs r6, r6, #0x1
++ bne 6b
++
++ /*
++ * Need to reset the FIFO to avoid MMDC lockup
++ * caused because of floating/changing the
++ * configuration of many DDR IO pads.
++ */
++ ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET]
++ /* reset read FIFO, RST_RD_FIFO */
++ ldr r7, =MX6Q_MMDC_MPDGCTRL0
++ ldr r6, [r10, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r10, r7]
++7:
++ ldr r6, [r10, r7]
++ ands r6, r6, #(1 << 31)
++ bne 7b
++
++ /* reset FIFO a second time */
++ ldr r7, =MX6Q_MMDC_MPDGCTRL0
++ ldr r6, [r10, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r10, r7]
++8:
++ ldr r6, [r10, r7]
++ ands r6, r6, #(1 <<31)
++ bne 8b
++
++ ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET]
++ /* Let DDR out of self-refresh */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #(1 << 21)
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++9:
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ bne 9b
++
++ /* enable power down timer */
++ ldr r7, [r10, #0x04]
++ orr r7, r7, #0x5500
++ str r7, [r10, #0x04]
++
++ /* enable DDR auto power saving */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #0x1
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++
++ /* Clear SBS - unblock DDR accesses */
++ ldr r7, [r10, #0x410]
++ bic r7, r7, #0x100
++ str r7, [r10, #0x410]
++
++ .endm
++
++ .macro tlb_set_to_ocram
++
++ /* save ttbr */
++ mrc p15, 0, r7, c2, c0, 1
++ str r7, [r0, #PM_INFO_TTBR_OFFSET]
++
++ /*
++ * To ensure no page table walks occur in DDR, we
++ * have a another page table stored in IRAM that only
++ * contains entries pointing to IRAM, AIPS1 and AIPS2.
++ * we need to set the TTBR1 to the new IRAM TLB.
++ * Do the following steps:
++ * 1. Flush the Branch Target Address Cache (BTAC)
++ * 2. Set TTBR1 to point to the IRAM page table.
++ * 3. Disable page table walks in TTBR0 (PD0 = 1)
++ * 4. Set TTBR0.N=1, implying 0-2G is transslated by TTBR0
++ * and 2-4G is translated by TTBR1.
++ */
++
++ ldr r6, =iram_tlb_phys_addr
++ ldr r7, [r6]
++
++ /* Disable Branch Prediction, Z bit in SCTLR */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the BTAC. */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ dsb
++ isb
++
++ /* store the IRAM table in TTBR1 */
++ mcr p15, 0, r7, c2, c0, 1
++ /* Read TTBCR and set PD0=1, N=1 */
++ mrc p15, 0, r6, c2, c0, 2
++ orr r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* Flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ .endm
++
++ .macro tlb_back_to_ddr
++
++ /* Restore the TTBCR */
++ dsb
++ isb
++
++ /* Read TTBCR and set PD0=0, N=0 */
++ mrc p15, 0, r6, c2, c0, 2
++ bic r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++ /* Flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++ /* Enable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x800
++ mcr p15, 0 ,r6, c1, c0, 0
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++ /* Restore ttbr */
++ ldr r7, [r0, #PM_INFO_TTBR_OFFSET]
++ mcr p15, 0, r7, c2, c0, 1
++
++ .endm
++
++.extern iram_tlb_phys_addr
++
++/*
++ * imx6sl_low_power_wfi code
++ * r0: wfi code base address
++ * r1: audio_bus_freq mode stat
++ * r2: vbus_ldo status
++ * r4: used for store the PLLs state
++ * r11: used for saving the ARM_PODF origin value
++ * r12: used for saving AHB_PODF origin value
++ */
++ .align 3
++ENTRY(imx6sl_low_power_wfi)
++
++mx6sl_lpm_wfi_start:
++
++ push {r4-r12}
++
++ tlb_set_to_ocram
++ disable_l1_dcache
++
++#ifdef CONFIG_CACHE_L2X0
++ /* sync L2 */
++ ldr r10, [r0, #PM_INFO_L2_V_OFFSET]
++ /* Wait for background operations to complete. */
++wait_for_l2_idle:
++ ldr r6, [r10, #0x730]
++ cmp r6, #0x0
++ bne wait_for_l2_idle
++
++ mov r6, #0x0
++ str r6, [r10, #0x730]
++ /* disable L2 */
++ str r6, [r10, #0x100]
++
++ dsb
++ isb
++#endif
++
++ /* make sure MMDC in self-refresh */
++ ldr r10, [r0, #PM_INFO_MMDC_V_OFFSET]
++ mmdc_enter_dvfs_mode
++ /* save DDR IO settings and set to LPM mode*/
++ ldr r10, [r0, #PM_INFO_IOMUXC_V_OFFSET]
++ ldr r6, =0x0
++ ldr r7, [r0, #PM_INFO_IO_NUM_OFFSET]
++ ldr r8, =PM_INFO_IO_VAL_OFFSET
++ add r8, r8, r0
++
++ /* imx6sl's last 3 IOs need special setting */
++ sub r7, r7, #0x3
++save_and_set_mmdc_io_lpm:
++ ldr r9, [r8], #0x4
++ ldr r5, [r10, r9]
++ str r6, [r10, r9]
++ str r5, [r8], #0x4
++ subs r7, r7, #0x1
++ bne save_and_set_mmdc_io_lpm
++ ldr r6, =0x1000
++ ldr r9, [r8], #0x4
++ ldr r5, [r10, r9]
++ str r5, [r8], #0x4
++ str r6, [r10, r9]
++ ldr r9, [r8], #0x4
++ ldr r5, [r10, r9]
++ str r6, [r10, r9]
++ str r5, [r8], #0x4
++ ldr r6, =0x80000
++ ldr r9, [r8], #0x4
++ ldr r5, [r10, r9]
++ str r6, [r10, r9]
++ str r5, [r8], #0x4
++
++
++ /* check the PLLs lock state */
++ check_pll_state
++
++ ccm_enter_idle
++ /* if in audio low power mode, no
++ * need to do anatop setting.
++ */
++ cmp r1, #0x1
++ beq do_wfi
++ anatop_enter_idle
++do_wfi:
++ wfi
++ /*
++ * Add these nops so that the
++ * prefetcher will not try to get
++ * any instrutions from DDR.
++ * The prefetch depth is about 23
++ * on A9, so adding 25 nops.
++ */
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ /*
++ * restore the ARM PODF first to speed
++ * up the restore procedure
++ */
++ ldr r10, [r0, #PM_INFO_CCM_V_OFFSET]
++ /* Restore arm_clk_podf */
++ str r11, [r10, #0x10]
++ ccm_do_wait
++
++ /*
++ * if in audio low power mode, skip
++ * restore the anatop setting.
++ */
++ cmp r1, #0x1
++ beq skip_analog_restore
++ anatop_exit_idle
++
++skip_analog_restore:
++ ccm_exit_idle
++ resume_mmdc
++
++ /* enable d-cache */
++ mrc p15, 0, r7, c1, c0, 0
++ orr r7, r7, #(1 << 2)
++ mcr p15, 0, r7, c1, c0, 0
++
++#ifdef CONFIG_CACHE_L2X0
++ ldr r10, [r0, #PM_INFO_L2_V_OFFSET]
++ mov r7, #0x1
++ /* enable L2 */
++ str r7, [r10, #0x100]
++#endif
++ tlb_back_to_ddr
++
++ /* Restore register */
++ pop {r4 - r12}
++ mov pc, lr
++
++ /*
++ * Add ltorg here to ensure that all
++ * literals are stored here and are
++ * within the text space.
++ */
++ .ltorg
++mx6sl_lpm_wfi_end:
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/imx6sx_low_power_idle.S linux-3.14.72/arch/arm/mach-imx/imx6sx_low_power_idle.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/imx6sx_low_power_idle.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/imx6sx_low_power_idle.S 2016-06-19 22:11:55.049156848 +0200
+@@ -0,0 +1,887 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/linkage.h>
++
++#define PM_INFO_PBASE_OFFSET 0x0
++#define PM_INFO_RESUME_ADDR_OFFSET 0x4
++#define PM_INFO_PM_INFO_SIZE_OFFSET 0x8
++#define PM_INFO_PM_INFO_TTBR_OFFSET 0xc
++#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
++#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
++#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x18
++#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x1c
++#define PM_INFO_MX6Q_CCM_P_OFFSET 0x20
++#define PM_INFO_MX6Q_CCM_V_OFFSET 0x24
++#define PM_INFO_MX6Q_GPC_P_OFFSET 0x28
++#define PM_INFO_MX6Q_GPC_V_OFFSET 0x2c
++#define PM_INFO_MX6Q_L2_P_OFFSET 0x30
++#define PM_INFO_MX6Q_L2_V_OFFSET 0x34
++#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x38
++#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x3c
++#define PM_INFO_MX6Q_SRC_P_OFFSET 0x40
++#define PM_INFO_MX6Q_SRC_V_OFFSET 0x44
++#define PM_INFO_MX6Q_SEMA4_P_OFFSET 0x48
++#define PM_INFO_MX6Q_SEMA4_V_OFFSET 0x4c
++#define PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET 0x50
++#define PM_INFO_MMDC_IO_NUM_OFFSET 0x54
++#define PM_INFO_MMDC_IO_VAL_OFFSET 0x58
++
++#define MX6Q_MMDC_MAPSR 0x404
++#define MX6Q_MMDC_MPDGCTRL0 0x83c
++#define MX6Q_SRC_GPR1 0x20
++#define MX6Q_SRC_GPR2 0x24
++#define MX6Q_GPC_IMR1 0x08
++#define MX6Q_GPC_IMR2 0x0c
++#define MX6Q_GPC_IMR3 0x10
++#define MX6Q_GPC_IMR4 0x14
++#define MX6Q_CCM_CCR 0x0
++
++.globl mx6sx_lpm_wfi_start
++.globl mx6sx_lpm_wfi_end
++
++ .macro pll_do_wait_lock
++1:
++ ldr r7, [r10, r8]
++ ands r7, #0x80000000
++ beq 1b
++
++ .endm
++
++ .macro ccm_do_wait
++2:
++ ldr r7, [r10, #0x48]
++ cmp r7, #0x0
++ bne 2b
++
++ .endm
++
++ .macro ccm_enter_idle
++
++ ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
++
++ /* set ahb to 3MHz */
++ ldr r7, [r10, #0x14]
++ orr r7, r7, #0x1c00
++ str r7, [r10, #0x14]
++
++ /* set perclk to 6MHz */
++ ldr r7, [r10, #0x1c]
++ bic r7, r7, #0x3f
++ orr r7, r7, #0x3
++ str r7, [r10, #0x1c]
++
++ /* set mmdc to 1MHz, periph2_clk2 need to be @8MHz */
++ ldr r7, [r10, #0x14]
++ orr r7, r7, #0x2
++ orr r7, r7, #(0x7 << 3)
++ str r7, [r10, #0x14]
++
++ ccm_do_wait
++
++ ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
++
++ /* set pll1_sw to from pll1 main */
++ ldr r7, [r10, #0xc]
++ bic r7, r7, #0x4
++ str r7, [r10, #0xc]
++
++ /* set step from osc */
++ ldr r7, [r10, #0xc]
++ bic r7, r7, #0x100
++ str r7, [r10, #0xc]
++
++ /* set pll1_sw to from step */
++ ldr r7, [r10, #0xc]
++ orr r7, r7, #0x4
++ str r7, [r10, #0xc]
++
++ ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
++
++ /* Disable PLL1 bypass output */
++ ldr r7, [r10]
++ bic r7, r7, #0x12000
++ str r7, [r10]
++
++ /*
++ * disable pll2, suppose when system enter low
++ * power idle mode, only 396MHz pfd needs pll2,
++ * now we switch arm clock to OSC, we can disable
++ * pll2 now, gate pll2_pfd2 first.
++ */
++ ldr r7, [r10, #0x100]
++ orr r7, #0x800000
++ str r7, [r10, #0x100]
++
++ ldr r7, [r10, #0x30]
++ orr r7, r7, #0x1000
++ bic r7, r7, #0x2000
++ str r7, [r10, #0x30]
++
++ .endm
++
++ .macro ccm_exit_idle
++
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET]
++
++ /* enable pll2 and pll2_pfd2 */
++ ldr r7, [r10, #0x30]
++ bic r7, r7, #0x1000
++ orr r7, r7, #0x2000
++ str r7, [r10, #0x30]
++
++ ldr r8, =0x30
++ pll_do_wait_lock
++
++ ldr r7, [r10, #0x100]
++ bic r7, #0x800000
++ str r7, [r10, #0x100]
++
++ /* enable PLL1 bypass output */
++ ldr r7, [r10]
++ orr r7, r7, #0x12000
++ str r7, [r10]
++
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_CCM_P_OFFSET]
++
++ /* set perclk back to 24MHz */
++ ldr r7, [r10, #0x1c]
++ bic r7, r7, #0x3f
++ str r7, [r10, #0x1c]
++
++ /* set mmdc back to 24MHz */
++ ldr r7, [r10, #0x14]
++ bic r7, r7, #0x7
++ bic r7, r7, #(0x7 << 3)
++ str r7, [r10, #0x14]
++
++ /* set ahb div back to 24MHz */
++ ldr r7, [r10, #0x14]
++ bic r7, r7, #0x1c00
++ str r7, [r10, #0x14]
++
++ ccm_do_wait
++
++ /* set pll1_sw to from pll1 main */
++ ldr r7, [r10, #0xc]
++ bic r7, r7, #0x4
++ str r7, [r10, #0xc]
++
++ /* set step from pll2_pfd2 */
++ ldr r7, [r10, #0xc]
++ orr r7, r7, #0x100
++ str r7, [r10, #0xc]
++
++ /* set pll1_sw to from step */
++ ldr r7, [r10, #0xc]
++ orr r7, r7, #0x4
++ str r7, [r10, #0xc]
++
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET]
++
++ .endm
++
++ .macro anatop_enter_idle
++
++ ldr r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
++
++ /*
++ * check whether any PLL is enabled, as only when
++ * there is no PLLs enabled, 2P5 and 1P1 can be
++ * off and only enable weak ones.
++ */
++
++ /* arm pll1 */
++ ldr r7, [r10, #0]
++ ands r7, r7, #(1 << 31)
++ bne 10f
++
++ /* sys pll2 */
++ ldr r7, [r10, #0x30]
++ ands r7, r7, #(1 << 31)
++ bne 10f
++
++ /* usb pll3 */
++ ldr r7, [r10, #0x10]
++ ands r7, r7, #(1 << 31)
++ bne 10f
++
++ /* audio pll4 */
++ ldr r7, [r10, #0x70]
++ ands r7, r7, #(1 << 31)
++ bne 10f
++
++ /* vidio pll5 */
++ ldr r7, [r10, #0xa0]
++ ands r7, r7, #(1 << 31)
++ bne 10f
++
++ /* enet pll6 */
++ ldr r7, [r10, #0xe0]
++ ands r7, r7, #(1 << 31)
++ bne 10f
++
++ /* usb host pll7 */
++ ldr r7, [r10, #0x20]
++ ands r7, r7, #(1 << 31)
++ bne 10f
++
++ /* enable weak 2P5 and turn off regular 2P5 */
++ ldr r7, [r10, #0x130]
++ orr r7, r7, #0x40000
++ str r7, [r10, #0x130]
++ bic r7, r7, #0x1
++ str r7, [r10, #0x130]
++
++ /* enable weak 1p1 and turn off regular 1P1 */
++ ldr r7, [r10, #0x110]
++ orr r7, r7, #0x40000
++ str r7, [r10, #0x110]
++ bic r7, r7, #0x1
++ str r7, [r10, #0x110]
++
++ /* check whether ARM LDO is bypassed */
++ ldr r7, [r10, #0x140]
++ and r7, r7, #0x1f
++ cmp r7, #0x1f
++ bne 10f
++
++ /* low power band gap enable */
++ ldr r7, [r10, #0x270]
++ orr r7, r7, #0x20
++ str r7, [r10, #0x270]
++
++ /* turn off the bias current from the regular bandgap */
++ ldr r7, [r10, #0x270]
++ orr r7, r7, #0x80
++ str r7, [r10, #0x270]
++
++ /*
++ * clear the REFTOP_SELFBIASOFF,
++ * self-bias circuit of the band gap.
++ * Per RM, should be cleared when
++ * band gap is powered down.
++ */
++ ldr r7, [r10, #0x150]
++ bic r7, r7, #0x8
++ str r7, [r10, #0x150]
++
++ /* turn off regular bandgap */
++ ldr r7, [r10, #0x150]
++ orr r7, r7, #0x1
++ str r7, [r10, #0x150]
++
++ /* only switch to RC-OSC clk after TO1.2 */
++ ldr r7, [r10, #0x260]
++ and r7, r7, #0x3
++ cmp r7, #0x2
++ blt 10f
++
++ /* switch to RC-OSC */
++ ldr r7, [r10, #0x270]
++ orr r7, r7, #0x10
++ str r7, [r10, #0x270]
++
++ /* turn off XTAL-OSC */
++ ldr r7, [r10, #0x150]
++ orr r7, r7, #0x40000000
++ str r7, [r10, #0x150]
++10:
++ /* lower OSC current by 37.5% */
++ ldr r7, [r10, #0x150]
++ orr r7, r7, #0x6000
++ str r7, [r10, #0x150]
++
++ .endm
++
++ .macro anatop_exit_idle
++
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET]
++
++ /* increase OSC current to normal */
++ ldr r7, [r10, #0x150]
++ bic r7, r7, #0x6000
++ str r7, [r10, #0x150]
++
++ /* only switch to RC-OSC after TO1.2 */
++ ldr r7, [r10, #0x260]
++ and r7, r7, #0x3
++ cmp r7, #0x2
++ blt 15f
++
++ /* turn on XTAL-OSC and detector */
++ ldr r7, [r10, #0x150]
++ bic r7, r7, #0x40000000
++ orr r7, r7, #0x10000
++ str r7, [r10, #0x150]
++
++ /* wait for XTAL stable */
++14:
++ ldr r7, [r10, #0x150]
++ ands r7, r7, #0x8000
++ beq 14b
++
++ /* switch to XTAL-OSC */
++ ldr r7, [r10, #0x270]
++ bic r7, r7, #0x10
++ str r7, [r10, #0x270]
++
++ /* turn off XTAL-OSC detector */
++ ldr r7, [r10, #0x150]
++ bic r7, r7, #0x10000
++ str r7, [r10, #0x150]
++15:
++ /* check whether we need to enable 2P5/1P1 */
++ ldr r7, [r10, #0x110]
++ ands r7, r7, #0x40000
++ beq 11f
++
++ /* check whether ARM LDO is bypassed */
++ ldr r7, [r10, #0x140]
++ and r7, r7, #0x1f
++ cmp r7, #0x1f
++ bne 12f
++
++ /* turn on regular bandgap and wait for stable */
++ ldr r7, [r10, #0x150]
++ bic r7, r7, #0x1
++ str r7, [r10, #0x150]
++13:
++ ldr r7, [r10, #0x150]
++ ands r7, #0x80
++ beq 13b
++
++ /*
++ * set the REFTOP_SELFBIASOFF,
++ * self-bias circuit of the band gap.
++ */
++ ldr r7, [r10, #0x150]
++ orr r7, r7, #0x8
++ str r7, [r10, #0x150]
++
++ /* turn on the bias current from the regular bandgap */
++ ldr r7, [r10, #0x270]
++ bic r7, r7, #0x80
++ str r7, [r10, #0x270]
++
++ /* low power band gap disable */
++ ldr r7, [r10, #0x270]
++ bic r7, r7, #0x20
++ str r7, [r10, #0x270]
++12:
++ /* enable regular 2P5 and turn off weak 2P5 */
++ ldr r7, [r10, #0x130]
++ orr r7, r7, #0x1
++ str r7, [r10, #0x130]
++
++ /* Ensure the 2P5 is up. */
++3:
++ ldr r7, [r10, #0x130]
++ ands r7, r7, #0x20000
++ beq 3b
++ ldr r7, [r10, #0x130]
++ bic r7, r7, #0x40000
++ str r7, [r10, #0x130]
++
++ /* enable regular 1p1 and turn off weak 1P1 */
++ ldr r7, [r10, #0x110]
++ orr r7, r7, #0x1
++ str r7, [r10, #0x110]
++4:
++ ldr r7, [r10, #0x110]
++ ands r7, r7, #0x20000
++ beq 4b
++ ldr r7, [r10, #0x110]
++ bic r7, r7, #0x40000
++ str r7, [r10, #0x110]
++11:
++ .endm
++
++ .macro disable_l1_dcache
++
++ /*
++ * Flush all data from the L1 data cache before disabling
++ * SCTLR.C bit.
++ */
++ push {r0 - r10, lr}
++ ldr r7, =v7_flush_dcache_all
++ mov lr, pc
++ mov pc, r7
++ pop {r0 - r10, lr}
++
++ /* disable d-cache */
++ mrc p15, 0, r7, c1, c0, 0
++ bic r7, r7, #(1 << 2)
++ mcr p15, 0, r7, c1, c0, 0
++ dsb
++ isb
++
++ push {r0 - r10, lr}
++ ldr r7, =v7_flush_dcache_all
++ mov lr, pc
++ mov pc, r7
++ pop {r0 - r10, lr}
++
++ .endm
++
++ .macro mmdc_enter_dvfs_mode
++
++ /* disable automatic power savings. */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #0x1
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++
++ /* disable power down timer */
++ ldr r7, [r10, #0x4]
++ bic r7, r7, #0xff00
++ str r7, [r10, #0x4]
++
++ /* make the DDR explicitly enter self-refresh. */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #(1 << 21)
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++5:
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ beq 5b
++
++ .endm
++
++ .macro resume_mmdc
++
++ /* restore MMDC IO */
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
++
++ ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
++ ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
++ add r7, r7, r0
++6:
++ ldr r8, [r7], #0x4
++ ldr r9, [r7], #0x4
++ str r9, [r10, r8]
++ subs r6, r6, #0x1
++ bne 6b
++
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
++
++ /* reset read FIFO, RST_RD_FIFO */
++ ldr r7, =MX6Q_MMDC_MPDGCTRL0
++ ldr r6, [r10, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r10, r7]
++7:
++ ldr r6, [r10, r7]
++ ands r6, r6, #(1 << 31)
++ bne 7b
++
++ /* reset FIFO a second time */
++ ldr r6, [r10, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r10, r7]
++8:
++ ldr r6, [r10, r7]
++ ands r6, r6, #(1 << 31)
++ bne 8b
++
++ /* let DDR out of self-refresh */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #(1 << 21)
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++9:
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ bne 9b
++
++ /* enable power down timer */
++ ldr r7, [r10, #0x4]
++ orr r7, r7, #0x5500
++ str r7, [r10, #0x4]
++
++ /* enable DDR auto power saving */
++ ldr r7, [r10, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #0x1
++ str r7, [r10, #MX6Q_MMDC_MAPSR]
++
++ .endm
++
++ .macro sema4_lock
++
++ /* lock share memory sema4 */
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET]
++ ldrb r6, =0x1
++16:
++ ldrb r7, [r10, #0x6]
++ cmp r7, #0x0
++ bne 16b
++ strb r6, [r10, #0x6]
++
++ .endm
++
++ .macro sema4_unlock
++
++ /* unlock share memory sema4 */
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_SEMA4_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_SEMA4_P_OFFSET]
++ ldrb r6, =0x0
++ strb r6, [r10, #0x6]
++
++ .endm
++
++ .macro tlb_set_to_ocram
++
++ /* save ttbr */
++ mrc p15, 0, r7, c2, c0, 1
++ str r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET]
++
++ /*
++ * To ensure no page table walks occur in DDR, we
++ * have a another page table stored in IRAM that only
++ * contains entries pointing to IRAM, AIPS1 and AIPS2.
++ * We need to set the TTBR1 to the new IRAM TLB.
++ * Do the following steps:
++ * 1. Flush the Branch Target Address Cache (BTAC)
++ * 2. Set TTBR1 to point to IRAM page table.
++ * 3. Disable page table walks in TTBR0 (PD0 = 1)
++ * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
++ * and 2-4G is translated by TTBR1.
++ */
++
++ ldr r6, =iram_tlb_phys_addr
++ ldr r7, [r6]
++
++ /* Flush the BTAC. */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ /* Disable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ dsb
++ isb
++
++ /* Store the IRAM table in TTBR1 */
++ mcr p15, 0, r7, c2, c0, 1
++
++ /* Read TTBCR and set PD0=1, N = 1 */
++ mrc p15, 0, r6, c2, c0, 2
++ orr r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ .endm
++
++ .macro tlb_back_to_ddr
++
++ /* Restore the TTBCR */
++
++ dsb
++ isb
++
++ /* Read TTBCR and set PD0=0, N = 0 */
++ mrc p15, 0, r6, c2, c0, 2
++ bic r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++ /* Enable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ /* restore ttbr */
++ ldr r7, [r0, #PM_INFO_PM_INFO_TTBR_OFFSET]
++ mcr p15, 0, r7, c2, c0, 1
++
++ .endm
++
++.extern iram_tlb_phys_addr
++
++/* imx6sx_low_power_idle */
++
++ .align 3
++ENTRY(imx6sx_low_power_idle)
++mx6sx_lpm_wfi_start:
++ push {r4 - r10}
++
++ /* get necessary info from pm_info */
++ ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
++ ldr r2, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
++
++ /*
++ * counting the resume address in iram
++ * to set it in SRC register.
++ */
++ ldr r5, =imx6sx_low_power_idle
++ ldr r6, =wakeup
++ sub r6, r6, r5
++ add r8, r1, r2
++ add r3, r8, r6
++
++ /* store physical resume addr and pm_info address. */
++ ldr r10, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
++ str r3, [r10, #0x20]
++ str r1, [r10, #0x24]
++
++ /* save disagnostic register */
++ mrc p15, 0, r7, c15, c0, 1
++ str r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET]
++
++ /* set ARM power to be gated */
++ ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
++ ldr r7, =0x1
++ str r7, [r10, #0x2a0]
++
++ disable_l1_dcache
++
++#ifdef CONFIG_CACHE_L2X0
++ /* sync L2 */
++ ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
++
++ /* Wait for background operations to complete. */
++wait_for_l2_to_idle:
++ ldr r7, [r10, #0x730]
++ cmp r7, #0x0
++ bne wait_for_l2_to_idle
++
++ mov r7, #0x0
++ str r7, [r10, #0x730]
++ /* disable L2 */
++ str r7, [r10, #0x100]
++
++ dsb
++ isb
++#endif
++
++ tlb_set_to_ocram
++
++ /* make sure MMDC in self-refresh */
++ ldr r10, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
++ mmdc_enter_dvfs_mode
++
++ /* save DDR IO settings */
++ ldr r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
++ ldr r6, =0x0
++ ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
++ ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
++ add r8, r8, r0
++save_and_set_mmdc_io_lpm:
++ ldr r9, [r8], #0x4
++ ldr r5, [r10, r9]
++ str r6, [r10, r9]
++ str r5, [r8], #0x4
++ subs r7, r7, #0x1
++ bne save_and_set_mmdc_io_lpm
++
++ mov r5, #0x0
++ sema4_lock
++ ccm_enter_idle
++ anatop_enter_idle
++ sema4_unlock
++
++ /*
++ * mask all GPC interrupts before
++ * enabling the RBC counters to
++ * avoid the counter starting too
++ * early if an interupt is already
++ * pending.
++ */
++ ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
++ ldr r4, [r10, #MX6Q_GPC_IMR1]
++ ldr r5, [r10, #MX6Q_GPC_IMR2]
++ ldr r6, [r10, #MX6Q_GPC_IMR3]
++ ldr r7, [r10, #MX6Q_GPC_IMR4]
++
++ ldr r3, =0xffffffff
++ str r3, [r10, #MX6Q_GPC_IMR1]
++ str r3, [r10, #MX6Q_GPC_IMR2]
++ str r3, [r10, #MX6Q_GPC_IMR3]
++ str r3, [r10, #MX6Q_GPC_IMR4]
++
++ /*
++ * enable the RBC bypass counter here
++ * to hold off the interrupts. RBC counter
++ * = 1 (30us). With this setting, the latency
++ * from wakeup interrupt to ARM power up
++ * is ~40uS.
++ */
++ ldr r10, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
++ ldr r3, [r10, #MX6Q_CCM_CCR]
++ bic r3, r3, #(0x3f << 21)
++ orr r3, r3, #(0x1 << 21)
++ str r3, [r10, #MX6Q_CCM_CCR]
++
++ /* enable the counter. */
++ ldr r3, [r10, #MX6Q_CCM_CCR]
++ orr r3, r3, #(0x1 << 27)
++ str r3, [r10, #MX6Q_CCM_CCR]
++
++ /* unmask all the GPC interrupts. */
++ ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
++ str r4, [r10, #MX6Q_GPC_IMR1]
++ str r5, [r10, #MX6Q_GPC_IMR2]
++ str r6, [r10, #MX6Q_GPC_IMR3]
++ str r7, [r10, #MX6Q_GPC_IMR4]
++
++ /*
++ * now delay for a short while (3usec)
++ * ARM is at 1GHz at this point
++ * so a short loop should be enough.
++ * this delay is required to ensure that
++ * the RBC counter can start counting in
++ * case an interrupt is already pending
++ * or in case an interrupt arrives just
++ * as ARM is about to assert DSM_request.
++ */
++ ldr r4, =2000
++rbc_loop:
++ subs r4, r4, #0x1
++ bne rbc_loop
++
++ wfi
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ mov r5, #0x0
++ sema4_lock
++ anatop_exit_idle
++ ccm_exit_idle
++ sema4_unlock
++ resume_mmdc
++
++ /* clear ARM power gate setting */
++ ldr r10, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
++ ldr r7, =0x0
++ str r7, [r10, #0x2a0]
++
++ /* enable d-cache */
++ mrc p15, 0, r7, c1, c0, 0
++ orr r7, r7, #(1 << 2)
++ mcr p15, 0, r7, c1, c0, 0
++
++#ifdef CONFIG_CACHE_L2X0
++ ldr r10, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
++ mov r7, #0x1
++ /* enable L2 */
++ str r7, [r10, #0x100]
++#endif
++
++ tlb_back_to_ddr
++
++ /* Restore registers */
++ pop {r4 - r10}
++ mov pc, lr
++
++wakeup:
++
++ /* invalidate L1 I-cache first */
++ mov r1, #0x0
++ mcr p15, 0, r1, c7, c5, 0
++ mcr p15, 0, r1, c7, c5, 0
++ mcr p15, 0, r1, c7, c5, 6
++ /* enable the Icache and branch prediction */
++ mov r1, #0x1800
++ mcr p15, 0, r1, c1, c0, 0
++ isb
++ /* restore disagnostic register */
++ ldr r7, [r0, #PM_INFO_MX6Q_SAVED_DIAGNOSTIC_OFFSET]
++ mcr p15, 0, r7, c15, c0, 1
++
++ /* get physical resume address from pm_info. */
++ ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
++ /* clear core0's entry and parameter */
++ ldr r10, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
++ mov r7, #0x0
++ str r7, [r10, #MX6Q_SRC_GPR1]
++ str r7, [r10, #MX6Q_SRC_GPR2]
++
++ /* clear ARM power gate setting */
++ ldr r10, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET]
++ ldr r7, =0x0
++ str r7, [r10, #0x2a0]
++
++ mov r5, #0x1
++ sema4_lock
++ anatop_exit_idle
++ ccm_exit_idle
++ sema4_unlock
++ resume_mmdc
++
++ /* Restore registers */
++ mov pc, lr
++ .ltorg
++mx6sx_lpm_wfi_end:
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/Kconfig linux-3.14.72/arch/arm/mach-imx/Kconfig
+--- linux-3.14.72.orig/arch/arm/mach-imx/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/Kconfig 2016-06-19 22:11:55.049156848 +0200
+@@ -1,19 +1,23 @@
+ config ARCH_MXC
+ bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
++ select ARCH_HAS_CPUFREQ
++ select ARCH_HAS_OPP
++ select ARCH_HAS_RESET_CONTROLLER
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_CPU_SUSPEND if PM
+ select ARM_PATCH_PHYS_VIRT
+ select CLKSRC_MMIO
+ select COMMON_CLK
+- select GENERIC_ALLOCATOR
+ select GENERIC_CLOCKEVENTS
+ select GENERIC_IRQ_CHIP
+ select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
+ select MULTI_IRQ_HANDLER
+ select PINCTRL
++ select PM_OPP if PM
+ select SOC_BUS
+ select SPARSE_IRQ
+ select USE_OF
++ select SRAM
+ help
+ Support for Freescale MXC/iMX-based family of processors
+
+@@ -52,18 +56,28 @@
+ config ARCH_HAS_RNGA
+ bool
+
++config HAVE_IMX_RNG
++ bool
++
+ config HAVE_IMX_ANATOP
+ bool
+
+ config HAVE_IMX_GPC
+ bool
++ select PM_GENERIC_DOMAINS if PM
+
+ config HAVE_IMX_MMDC
+ bool
+
+ config HAVE_IMX_SRC
+ def_bool y if SMP
+- select ARCH_HAS_RESET_CONTROLLER
++
++config HAVE_IMX_MCC
++ select IMX_SEMA4
++ bool
++
++config HAVE_IMX_AMP
++ bool
+
+ config IMX_HAVE_IOMUX_V1
+ bool
+@@ -784,53 +798,54 @@
+ help
+ This enables support for Freescale i.MX53 processor.
+
+-config SOC_IMX6Q
+- bool "i.MX6 Quad/DualLite support"
+- select ARCH_HAS_CPUFREQ
+- select ARCH_HAS_OPP
++config SOC_IMX6
++ bool
+ select ARM_ERRATA_754322
+- select ARM_ERRATA_764369 if SMP
+ select ARM_ERRATA_775420
+ select ARM_GIC
+ select CPU_V7
+- select HAVE_ARM_SCU if SMP
+- select HAVE_ARM_TWD if SMP
+ select HAVE_IMX_ANATOP
+ select HAVE_IMX_GPC
+ select HAVE_IMX_MMDC
+ select HAVE_IMX_SRC
+ select HAVE_SMP
+ select MFD_SYSCON
++ select PL310_ERRATA_769419 if CACHE_PL310
++ select ARM_IMX6Q_CPUFREQ
++
++config SOC_IMX6Q
++ bool "i.MX6 Quad/DualLite support"
++ select ARM_ERRATA_764369 if SMP
++ select HAVE_ARM_SCU if SMP
++ select HAVE_ARM_TWD if SMP
+ select MIGHT_HAVE_PCI
+ select PCI_DOMAINS if PCI
+ select PINCTRL_IMX6Q
+- select PL310_ERRATA_588369 if CACHE_PL310
+- select PL310_ERRATA_727915 if CACHE_PL310
+- select PL310_ERRATA_769419 if CACHE_PL310
+- select PM_OPP if PM
++ select SOC_IMX6
++ select ZONE_DMA
+
+ help
+ This enables support for Freescale i.MX6 Quad processor.
+
+ config SOC_IMX6SL
+ bool "i.MX6 SoloLite support"
+- select ARM_ERRATA_754322
+- select ARM_ERRATA_775420
+- select ARM_GIC
+- select CPU_V7
+- select HAVE_IMX_ANATOP
+- select HAVE_IMX_GPC
+- select HAVE_IMX_MMDC
+- select HAVE_IMX_SRC
+- select MFD_SYSCON
++ select HAVE_IMX_RNG
+ select PINCTRL_IMX6SL
+- select PL310_ERRATA_588369 if CACHE_PL310
+- select PL310_ERRATA_727915 if CACHE_PL310
+- select PL310_ERRATA_769419 if CACHE_PL310
++ select SOC_IMX6
+
+ help
+ This enables support for Freescale i.MX6 SoloLite processor.
+
++config SOC_IMX6SX
++ bool "i.MX6 SoloX support"
++ select PINCTRL_IMX6SX
++ select HAVE_IMX_AMP
++ select HAVE_IMX_MCC
++ select SOC_IMX6
++
++ help
++ This enables support for Freescale i.MX6 SoloX processor.
++
+ config SOC_VF610
+ bool "Vybrid Family VF610 support"
+ select CPU_V7
+@@ -838,8 +853,6 @@
+ select CLKSRC_OF
+ select PINCTRL_VF610
+ select VF_PIT_TIMER
+- select PL310_ERRATA_588369 if CACHE_PL310
+- select PL310_ERRATA_727915 if CACHE_PL310
+ select PL310_ERRATA_769419 if CACHE_PL310
+
+ help
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/lpddr2_freq_imx6.S linux-3.14.72/arch/arm/mach-imx/lpddr2_freq_imx6.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/lpddr2_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/lpddr2_freq_imx6.S 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,603 @@
++/*
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/linkage.h>
++#include "hardware.h"
++
++.globl imx6_lpddr2_freq_change_start
++.globl imx6_lpddr2_freq_change_end
++
++ .macro mx6sl_switch_to_24MHz
++
++ /*
++ * Set MMDC clock to be sourced from PLL3.
++ * Ensure first periph2_clk2 is sourced from PLL3.
++ * Set the PERIPH2_CLK2_PODF to divide by 2.
++ */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x7
++ orr r6, r6, #0x1
++ str r6, [r2, #0x14]
++
++ /* Select PLL3 to source MMDC. */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* Swtich periph2_clk_sel to run from PLL3. */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch1
++
++ /*
++ * Need to clock gate the 528 PFDs before
++ * powering down PLL2.
++ * Only the PLL2_PFD2_400M should be ON
++ * at this time, so only clock gate that one.
++ */
++ ldr r6, [r3, #0x100]
++ orr r6, r6, #0x800000
++ str r6, [r3, #0x100]
++
++ /*
++ * Set PLL2 to bypass state. We should be here
++ * only if MMDC is not sourced from PLL2.
++ */
++ ldr r6, [r3, #0x30]
++ orr r6, r6, #0x10000
++ str r6, [r3, #0x30]
++
++ ldr r6, [r3, #0x30]
++ orr r6, r6, #0x1000
++ str r6, [r3, #0x30]
++
++ /* Ensure pre_periph2_clk_mux is set to pll2 */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x600000
++ str r6, [r2, #0x18]
++
++ /* Set MMDC clock to be sourced from the bypassed PLL2. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch2:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch2
++
++ /*
++ * Now move MMDC back to periph2_clk2 source.
++ * after selecting PLL2 as the option.
++ * Select PLL2 as the source.
++ */
++ ldr r6, [r2, #0x18]
++ orr r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* set periph2_clk2_podf to divide by 1. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x7
++ str r6, [r2, #0x14]
++
++ /* Now move periph2_clk to periph2_clk2 source */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch3:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch3
++
++ /* Now set the MMDC PODF back to 1.*/
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ str r6, [r2, #0x14]
++
++mmdc_podf0:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf0
++
++ .endm
++
++ .macro ddr_switch_400MHz
++
++ /* Set MMDC divider first, in case PLL3 is at 480MHz. */
++ ldr r6, [r3, #0x10]
++ and r6, r6, #0x10000
++ cmp r6, #0x10000
++ beq pll3_in_bypass
++
++ /* Set MMDC divder to divide by 2. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, #0x8
++ str r6, [r2, #0x14]
++
++mmdc_podf:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf
++
++pll3_in_bypass:
++ /*
++ * Check if we are switching between
++ * 400Mhz <-> 100MHz.If so, we should
++ * try to source MMDC from PLL2_200M.
++ */
++ cmp r1, #0
++ beq not_low_bus_freq
++
++ /* Ensure that MMDC is sourced from PLL2 mux first. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch4:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch4
++
++not_low_bus_freq:
++ /* Now ensure periph2_clk2_sel mux is set to PLL3 */
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x100000
++ str r6, [r2, #0x18]
++
++ /* Now switch MMDC to PLL3. */
++ ldr r6, [r2, #0x14]
++ orr r6, r6, #0x4000000
++ str r6, [r2, #0x14]
++
++periph2_clk_switch5:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne periph2_clk_switch5
++
++ /*
++ * Check if PLL2 is already unlocked.
++ * If so do nothing with PLL2.
++ */
++ cmp r1, #0
++ beq pll2_already_on
++
++ /* Now power up PLL2 and unbypass it. */
++ ldr r6, [r3, #0x30]
++ bic r6, r6, #0x1000
++ str r6, [r3, #0x30]
++
++ /* Make sure PLL2 has locked.*/
++wait_for_pll_lock:
++ ldr r6, [r3, #0x30]
++ and r6, r6, #0x80000000
++ cmp r6, #0x80000000
++ bne wait_for_pll_lock
++
++ ldr r6, [r3, #0x30]
++ bic r6, r6, #0x10000
++ str r6, [r3, #0x30]
++
++ /*
++ * Need to enable the 528 PFDs after
++ * powering up PLL2.
++ * Only the PLL2_PFD2_400M should be ON
++ * as it feeds the MMDC. Rest should have
++ * been managed by clock code.
++ */
++ ldr r6, [r3, #0x100]
++ bic r6, r6, #0x800000
++ str r6, [r3, #0x100]
++
++pll2_already_on:
++ /*
++ * Now switch MMDC clk back to pll2_mux option.
++ * Ensure pre_periph2_clk2 is set to pll2_pfd_400M.
++ * If switching to audio DDR freq, set the
++ * pre_periph2_clk2 to PLL2_PFD_200M
++ */
++ ldr r6, =400000000
++ cmp r6, r0
++ bne use_pll2_pfd_200M
++
++ ldr r6, [r2, #0x18]
++ bic r6, r6, #0x600000
++ orr r6, r6, #0x200000
++ str r6, [r2, #0x18]
++ ldr r6, =400000000
++ b cont2
++
++use_pll2_pfd_200M:
++ ldr r6, [r2, #0x18]
++ orr r6, r6, #0x600000
++ str r6, [r2, #0x18]
++ ldr r6, =200000000
++
++cont2:
++ ldr r4, [r2, #0x14]
++ bic r4, r4, #0x4000000
++ str r4, [r2, #0x14]
++
++periph2_clk_switch6:
++ ldr r4, [r2, #0x48]
++ cmp r4, #0
++ bne periph2_clk_switch6
++
++change_divider_only:
++ /*
++ * Calculate the MMDC divider
++ * based on the requested freq.
++ */
++ ldr r4, =0
++Loop2:
++ sub r6, r6, r0
++ cmp r6, r0
++ blt Div_Found
++ add r4, r4, #1
++ bgt Loop2
++
++ /* Shift divider into correct offset. */
++ lsl r4, r4, #3
++Div_Found:
++ /* Set the MMDC PODF. */
++ ldr r6, [r2, #0x14]
++ bic r6, r6, #0x38
++ orr r6, r6, r4
++ str r6, [r2, #0x14]
++
++mmdc_podf1:
++ ldr r6, [r2, #0x48]
++ cmp r6, #0
++ bne mmdc_podf1
++
++ .endm
++
++ .macro mmdc_clk_lower_100MHz
++
++ /*
++ * Prior to reducing the DDR frequency (at 528/400 MHz),
++ * read the Measure unit count bits (MU_UNIT_DEL_NUM)
++ */
++ ldr r5, =0x8B8
++ ldr r6, [r8, r5]
++ /* Original MU unit count */
++ mov r6, r6, LSR #16
++ ldr r4, =0x3FF
++ and r6, r6, r4
++ /* Original MU unit count * 2 */
++ mov r7, r6, LSL #1
++ /*
++ * Bypass the automatic measure unit when below 100 MHz
++ * by setting the Measure unit bypass enable bit (MU_BYP_EN)
++ */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x400
++ str r6, [r8, r5]
++ /*
++ * Double the measure count value read in step 1 and program it in the
++ * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit
++ * Register for the reduced frequency operation below 100 MHz
++ */
++ ldr r6, [r8, r5]
++ ldr r4, =0x3FF
++ bic r6, r6, r4
++ orr r6, r6, r7
++ str r6, [r8, r5]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x800
++ str r6, [r8, r5]
++ /* Wait for FRC_MSR to clear. */
++force_measure:
++ ldr r6, [r8, r5]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure
++
++ .endm
++
++ .macro mmdc_clk_above_100MHz
++
++ /* Make sure that the PHY measurement unit is NOT in bypass mode */
++ ldr r5, =0x8B8
++ ldr r6, [r8, r5]
++ bic r6, r6, #0x400
++ str r6, [r8, r5]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r8, r5]
++ orr r6, r6, #0x800
++ str r6, [r8, r5]
++ /* Wait for FRC_MSR to clear. */
++force_measure1:
++ ldr r6, [r8, r5]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure1
++ .endm
++
++/*
++ * mx6_lpddr2_freq_change
++ *
++ * Make sure DDR is in self-refresh.
++ * IRQs are already disabled.
++ * r0 : DDR freq.
++ * r1: low_bus_freq_mode flag
++ */
++ .align 3
++ENTRY(mx6_lpddr2_freq_change)
++imx6_lpddr2_freq_change_start:
++ push {r4-r10}
++
++ /*
++ * To ensure no page table walks occur in DDR, we
++ * have a another page table stored in IRAM that only
++ * contains entries pointing to IRAM, AIPS1 and AIPS2.
++ * We need to set the TTBR1 to the new IRAM TLB.
++ * Do the following steps:
++ * 1. Flush the Branch Target Address Cache (BTAC)
++ * 2. Set TTBR1 to point to IRAM page table.
++ * 3. Disable page table walks in TTBR0 (PD0 = 1)
++ * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
++ * and 2-4G is translated by TTBR1.
++ */
++
++ ldr r6, =iram_tlb_phys_addr
++ ldr r7, [r6]
++
++ /* Disable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ dsb
++ isb
++ /* Store the IRAM table in TTBR1 */
++ mcr p15, 0, r7, c2, c0, 1
++
++ /* Read TTBCR and set PD0=1, N = 1 */
++ mrc p15, 0, r6, c2, c0, 2
++ orr r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ /* Disable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ dsb
++ isb
++
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Need to make sure the buffers in L2 are drained.
++ * Performing a sync operation does this.
++ */
++ ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++
++ /* Wait for background operations to complete. */
++wait_for_l2_to_idle:
++ ldr r6, [r7, #0x730]
++ cmp r6, #0x0
++ bne wait_for_l2_to_idle
++
++ mov r6, #0x0
++ str r6, [r7, #0x730]
++
++ /*
++ * The second dsb might be needed to keep cache sync (device write)
++ * ordering with the memory accesses before it.
++ */
++ dsb
++ isb
++
++ /* Disable L2. */
++ str r6, [r7, #0x100]
++#endif
++
++ ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
++ ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
++ ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
++
++ /* Disable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ /* MMDC0_MDPDC disable power down timer */
++ ldr r6, [r8, #0x4]
++ bic r6, r6, #0xff00
++ str r6, [r8, #0x4]
++
++ /* Delay for a while */
++ ldr r10, =10
++delay1:
++ ldr r7, =0
++cont1:
++ ldr r6, [r8, r7]
++ add r7, r7, #4
++ cmp r7, #16
++ bne cont1
++ sub r10, r10, #1
++ cmp r10, #0
++ bgt delay1
++
++ /* Make the DDR explicitly enter self-refresh. */
++ ldr r6, [r8, #0x404]
++ orr r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_set_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ bne poll_dvfs_set_1
++
++ /* set SBS step-by-step mode */
++ ldr r6, [r8, #0x410]
++ orr r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++ ldr r10, =100000000
++ cmp r0, r10
++ bgt set_ddr_mu_above_100
++ mmdc_clk_lower_100MHz
++
++set_ddr_mu_above_100:
++ ldr r10, =24000000
++ cmp r0, r10
++ beq set_to_24MHz
++
++ ddr_switch_400MHz
++
++ ldr r10,=100000000
++ cmp r0, r10
++ blt done
++ mmdc_clk_above_100MHz
++
++ b done
++
++set_to_24MHz:
++ mx6sl_switch_to_24MHz
++
++done:
++ /* clear DVFS - exit from self refresh mode */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x200000
++ str r6, [r8, #0x404]
++
++poll_dvfs_clear_1:
++ ldr r6, [r8, #0x404]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ beq poll_dvfs_clear_1
++
++ /* Enable Automatic power savings. */
++ ldr r6, [r8, #0x404]
++ bic r6, r6, #0x01
++ str r6, [r8, #0x404]
++
++ ldr r10, =24000000
++ cmp r0, r10
++ beq skip_power_down
++
++ /* Enable MMDC power down timer. */
++ ldr r6, [r8, #0x4]
++ orr r6, r6, #0x5500
++ str r6, [r8, #0x4]
++
++skip_power_down:
++ /* clear SBS - unblock DDR accesses */
++ ldr r6, [r8, #0x410]
++ bic r6, r6, #0x100
++ str r6, [r8, #0x410]
++
++#ifdef CONFIG_CACHE_L2X0
++ /* Enable L2. */
++ ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++ ldr r6, =0x1
++ str r6, [r7, #0x100]
++#endif
++
++ /* Enable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Restore the TTBCR */
++ dsb
++ isb
++
++ /* Read TTBCR and set PD0=0, N = 0 */
++ mrc p15, 0, r6, c2, c0, 2
++ bic r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++ /* Enable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ pop {r4-r10}
++
++ /* Restore registers */
++ mov pc, lr
++
++ /*
++ * Add ltorg here to ensure that all
++ * literals are stored here and are
++ * within the text space.
++ */
++ .ltorg
++imx6_lpddr2_freq_change_end:
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/lpddr2_freq_imx6sx.S linux-3.14.72/arch/arm/mach-imx/lpddr2_freq_imx6sx.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/lpddr2_freq_imx6sx.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/lpddr2_freq_imx6sx.S 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,450 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/linkage.h>
++#include "hardware.h"
++
++#define CCM_CBCDR 0x14
++#define CCM_CBCMR 0x18
++#define CCM_CSCMR1 0x1c
++#define CCM_CDHIPR 0x48
++
++#define L2_CACHE_SYNC 0x730
++
++#define MMDC0_MDPDC 0x4
++#define MMDC0_MAPSR 0x404
++#define MMDC0_MADPCR0 0x410
++
++ .macro wait_for_ccm_handshake
++
++1:
++ ldr r8, [r2, #CCM_CDHIPR]
++ cmp r8, #0
++ bne 1b
++
++ .endm
++
++ .macro switch_to_24MHz
++
++ /* periph2_clk2 sel to OSC_CLK */
++ ldr r8, [r2, #CCM_CBCMR]
++ orr r8, r8, #(1 << 20)
++ str r8, [r2, #CCM_CBCMR]
++
++ /* periph2_clk2_podf to 0 */
++ ldr r8, [r2, #CCM_CBCDR]
++ bic r8, r8, #0x7
++ str r8, [r2, #CCM_CBCDR]
++
++ /* periph2_clk sel to periph2_clk2 */
++ ldr r8, [r2, #CCM_CBCDR]
++ orr r8, r8, #(0x1 << 26)
++ str r8, [r2, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ /* fabric_mmdc_podf to 0 */
++ ldr r8, [r2, #CCM_CBCDR]
++ bic r8, r8, #(0x7 << 3)
++ str r8, [r2, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ .endm
++
++ .macro switch_to_100MHz
++
++ /* check whether periph2_clk is from top path */
++ ldr r8, [r2, #CCM_CBCDR]
++ ands r8, #(1 << 26)
++ beq skip_periph2_clk2_switch_100m
++
++ /* now switch periph2_clk back. */
++ ldr r8, [r2, #CCM_CBCDR]
++ bic r8, r8, #(1 << 26)
++ str r8, [r2, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ /*
++ * on i.MX6SX, pre_periph2_clk will be always from
++ * pll2_pfd2, so no need to set pre_periph2_clk
++ * parent, just set the mmdc divider directly.
++ */
++skip_periph2_clk2_switch_100m:
++
++ /* fabric_mmdc_podf to 3 so that mmdc is 400 / 4 = 100MHz */
++ ldr r8, [r2, #CCM_CBCDR]
++ bic r8, r8, #(0x7 << 3)
++ orr r8, r8, #(0x3 << 3)
++ str r8, [r2, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ .endm
++
++ .macro switch_to_400MHz
++
++ /* check whether periph2_clk is from top path */
++ ldr r8, [r2, #CCM_CBCDR]
++ ands r8, #(1 << 26)
++ beq skip_periph2_clk2_switch_400m
++
++ /* now switch periph2_clk back. */
++ ldr r8, [r2, #CCM_CBCDR]
++ bic r8, r8, #(1 << 26)
++ str r8, [r2, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ /*
++ * on i.MX6SX, pre_periph2_clk will be always from
++ * pll2_pfd2, so no need to set pre_periph2_clk
++ * parent, just set the mmdc divider directly.
++ */
++skip_periph2_clk2_switch_400m:
++
++ /* fabric_mmdc_podf to 0 */
++ ldr r8, [r2, #CCM_CBCDR]
++ bic r8, r8, #(0x7 << 3)
++ str r8, [r2, #CCM_CBCDR]
++
++ wait_for_ccm_handshake
++
++ .endm
++
++ .macro mmdc_clk_lower_100MHz
++
++ /*
++ * Prior to reducing the DDR frequency (at 528/400 MHz),
++ * read the Measure unit count bits (MU_UNIT_DEL_NUM)
++ */
++ ldr r8, =0x8B8
++ ldr r6, [r5, r8]
++ /* Original MU unit count */
++ mov r6, r6, LSR #16
++ ldr r4, =0x3FF
++ and r6, r6, r4
++ /* Original MU unit count * 2 */
++ mov r7, r6, LSL #1
++ /*
++ * Bypass the automatic measure unit when below 100 MHz
++ * by setting the Measure unit bypass enable bit (MU_BYP_EN)
++ */
++ ldr r6, [r5, r8]
++ orr r6, r6, #0x400
++ str r6, [r5, r8]
++ /*
++ * Double the measure count value read in step 1 and program it in the
++ * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit
++ * Register for the reduced frequency operation below 100 MHz
++ */
++ ldr r6, [r5, r8]
++ ldr r4, =0x3FF
++ bic r6, r6, r4
++ orr r6, r6, r7
++ str r6, [r5, r8]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r5, r8]
++ orr r6, r6, #0x800
++ str r6, [r5, r8]
++ /* Wait for FRC_MSR to clear. */
++force_measure:
++ ldr r6, [r5, r8]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure
++
++ /* For freq lower than 100MHz, need to set RALAT to 2 */
++ ldr r6, [r5, #0x18]
++ bic r6, r6, #(0x7 << 6)
++ orr r6, r6, #(0x2 << 6)
++ str r6, [r5, #0x18]
++
++ .endm
++
++ .macro mmdc_clk_above_100MHz
++
++ /* Make sure that the PHY measurement unit is NOT in bypass mode */
++ ldr r8, =0x8B8
++ ldr r6, [r5, r8]
++ bic r6, r6, #0x400
++ str r6, [r5, r8]
++ /* Now perform a Force Measurement. */
++ ldr r6, [r5, r8]
++ orr r6, r6, #0x800
++ str r6, [r5, r8]
++ /* Wait for FRC_MSR to clear. */
++force_measure1:
++ ldr r6, [r5, r8]
++ and r6, r6, #0x800
++ cmp r6, #0x0
++ bne force_measure1
++
++ /* For freq higher than 100MHz, need to set RALAT to 5 */
++ ldr r6, [r5, #0x18]
++ bic r6, r6, #(0x7 << 6)
++ orr r6, r6, #(0x5 << 6)
++ str r6, [r5, #0x18]
++
++ .endm
++
++ .align 3
++ENTRY(imx6sx_lpddr2_freq_change)
++
++ push {r2 - r8}
++
++ /*
++ * To ensure no page table walks occur in DDR, we
++ * have a another page table stored in IRAM that only
++ * contains entries pointing to IRAM, AIPS1 and AIPS2.
++ * We need to set the TTBR1 to the new IRAM TLB.
++ * Do the following steps:
++ * 1. Flush the Branch Target Address Cache (BTAC)
++ * 2. Set TTBR1 to point to IRAM page table.
++ * 3. Disable page table walks in TTBR0 (PD0 = 1)
++ * 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
++ * and 2-4G is translated by TTBR1.
++ */
++
++ ldr r6, =iram_tlb_phys_addr
++ ldr r7, [r6]
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ /* Disable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ dsb
++ isb
++ /* Store the IRAM table in TTBR1 */
++ mcr p15, 0, r7, c2, c0, 1
++
++ /* Read TTBCR and set PD0=1, N = 1 */
++ mrc p15, 0, r6, c2, c0, 2
++ orr r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ /* Disable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ dsb
++ isb
++
++#ifdef CONFIG_CACHE_L2X0
++ /*
++ * Need to make sure the buffers in L2 are drained.
++ * Performing a sync operation does this.
++ */
++ ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++ mov r6, #0x0
++ str r6, [r7, #L2_CACHE_SYNC]
++
++ /*
++ * The second dsb might be needed to keep cache sync (device write)
++ * ordering with the memory accesses before it.
++ */
++ dsb
++ isb
++
++ /* Disable L2. */
++ str r6, [r7, #0x100]
++#endif
++
++ ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
++ ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
++ ldr r5, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
++
++ /* Disable Automatic power savings. */
++ ldr r6, [r5, #MMDC0_MAPSR]
++ orr r6, r6, #0x1
++ str r6, [r5, #MMDC0_MAPSR]
++
++ /* MMDC0_MDPDC disable power down timer */
++ ldr r6, [r5, #MMDC0_MDPDC]
++ bic r6, r6, #0xff00
++ str r6, [r5, #MMDC0_MDPDC]
++
++ /* Delay for a while */
++ ldr r8, =10
++delay:
++ ldr r7, =0
++cont:
++ ldr r6, [r5, r7]
++ add r7, r7, #4
++ cmp r7, #16
++ bne cont
++ sub r8, r8, #1
++ cmp r8, #0
++ bgt delay
++
++ /* Make the DDR explicitly enter self-refresh. */
++ ldr r6, [r5, #MMDC0_MAPSR]
++ orr r6, r6, #0x200000
++ str r6, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_set_1:
++ ldr r6, [r5, #MMDC0_MAPSR]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ bne poll_dvfs_set_1
++
++ /* set SBS step-by-step mode */
++ ldr r6, [r5, #MMDC0_MADPCR0]
++ orr r6, r6, #0x100
++ str r6, [r5, #MMDC0_MADPCR0]
++
++ ldr r6, =100000000
++ cmp r0, r6
++ bgt set_ddr_mu_above_100
++ mmdc_clk_lower_100MHz
++
++set_ddr_mu_above_100:
++ ldr r6, =24000000
++ cmp r0, r6
++ beq set_to_24MHz
++
++ ldr r6, =100000000
++ cmp r0, r6
++ beq set_to_100MHz
++
++ switch_to_400MHz
++
++ mmdc_clk_above_100MHz
++
++ b done
++
++set_to_24MHz:
++ switch_to_24MHz
++ b done
++set_to_100MHz:
++ switch_to_100MHz
++done:
++ /* clear DVFS - exit from self refresh mode */
++ ldr r6, [r5, #MMDC0_MAPSR]
++ bic r6, r6, #0x200000
++ str r6, [r5, #MMDC0_MAPSR]
++
++poll_dvfs_clear_1:
++ ldr r6, [r5, #MMDC0_MAPSR]
++ and r6, r6, #0x2000000
++ cmp r6, #0x2000000
++ beq poll_dvfs_clear_1
++
++ /* Enable Automatic power savings. */
++ ldr r6, [r5, #MMDC0_MAPSR]
++ bic r6, r6, #0x1
++ str r6, [r5, #MMDC0_MAPSR]
++
++ ldr r6, =24000000
++ cmp r0, r6
++ beq skip_power_down
++
++ /* Enable MMDC power down timer. */
++ ldr r6, [r5, #MMDC0_MDPDC]
++ orr r6, r6, #0x5500
++ str r6, [r5, #MMDC0_MDPDC]
++
++skip_power_down:
++ /* clear SBS - unblock DDR accesses */
++ ldr r6, [r5, #MMDC0_MADPCR0]
++ bic r6, r6, #0x100
++ str r6, [r5, #MMDC0_MADPCR0]
++
++
++#ifdef CONFIG_CACHE_L2X0
++ /* Enable L2. */
++ ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
++ ldr r6, =0x1
++ str r6, [r7, #0x100]
++#endif
++
++ /* Enable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Restore the TTBCR */
++ dsb
++ isb
++
++ /* Read TTBCR and set PD0=0, N = 0 */
++ mrc p15, 0, r6, c2, c0, 2
++ bic r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ dsb
++ isb
++
++ /* Enable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ nop
++ nop
++ nop
++ nop
++ nop
++
++ /* Restore registers */
++ pop {r2 - r8}
++ mov pc, lr
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mach-imx6q.c linux-3.14.72/arch/arm/mach-imx/mach-imx6q.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mach-imx6q.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/mach-imx6q.c 2016-06-19 22:11:55.053156547 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011-2013 Freescale Semiconductor, Inc.
++ * Copyright 2011-2015 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -10,17 +10,20 @@
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
++#include <linux/can/platform/flexcan.h>
+ #include <linux/clk.h>
+ #include <linux/clkdev.h>
+ #include <linux/cpu.h>
+ #include <linux/delay.h>
+ #include <linux/export.h>
++#include <linux/gpio.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+ #include <linux/irqchip.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
++#include <linux/of_gpio.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
+ #include <linux/pm_opp.h>
+@@ -31,6 +34,9 @@
+ #include <linux/micrel_phy.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/of_net.h>
++#include <linux/fec.h>
++#include <linux/netdevice.h>
+ #include <asm/mach/arch.h>
+ #include <asm/mach/map.h>
+ #include <asm/system_misc.h>
+@@ -39,6 +45,108 @@
+ #include "cpuidle.h"
+ #include "hardware.h"
+
++static struct fec_platform_data fec_pdata;
++static struct flexcan_platform_data flexcan_pdata[2];
++static int flexcan_en_gpio;
++static int flexcan_stby_gpio;
++static int flexcan0_en;
++static int flexcan1_en;
++
++static int ar803x_smarteee = 0;
++
++static int __init ar803x_smarteee_setup(char *__unused)
++{
++ ar803x_smarteee = 1;
++ return 1;
++}
++
++__setup("ar803x_smarteee", ar803x_smarteee_setup);
++
++
++static void imx6q_fec_sleep_enable(int enabled)
++{
++ struct regmap *gpr;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ if (enabled)
++ regmap_update_bits(gpr, IOMUXC_GPR13,
++ IMX6Q_GPR13_ENET_STOP_REQ,
++ IMX6Q_GPR13_ENET_STOP_REQ);
++ else
++ regmap_update_bits(gpr, IOMUXC_GPR13,
++ IMX6Q_GPR13_ENET_STOP_REQ, 0);
++ } else
++ pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
++}
++
++static void __init imx6q_enet_plt_init(void)
++{
++ struct device_node *np;
++
++ np = of_find_node_by_path("/soc/aips-bus@02100000/ethernet@02188000");
++ if (np && of_get_property(np, "fsl,magic-packet", NULL))
++ fec_pdata.sleep_mode_enable = imx6q_fec_sleep_enable;
++}
++
++static void mx6q_flexcan_switch(void)
++{
++ if (flexcan0_en || flexcan1_en) {
++ /*
++ * The transceiver TJA1041A on sabreauto RevE baseboard will
++ * fail to transit to Normal state if EN/STBY is high by default
++ * after board power up. So we set the EN/STBY initial state to low
++ * first then to high to guarantee the state transition successfully.
++ */
++ gpio_set_value_cansleep(flexcan_en_gpio, 0);
++ gpio_set_value_cansleep(flexcan_stby_gpio, 0);
++
++ gpio_set_value_cansleep(flexcan_en_gpio, 1);
++ gpio_set_value_cansleep(flexcan_stby_gpio, 1);
++ } else {
++ /*
++ * avoid to disable CAN xcvr if any of the CAN interfaces
++ * are down. XCRV will be disabled only if both CAN2
++ * interfaces are DOWN.
++ */
++ gpio_set_value_cansleep(flexcan_en_gpio, 0);
++ gpio_set_value_cansleep(flexcan_stby_gpio, 0);
++ }
++}
++
++static void imx6q_flexcan0_switch_auto(int enable)
++{
++ flexcan0_en = enable;
++ mx6q_flexcan_switch();
++}
++
++static void imx6q_flexcan1_switch_auto(int enable)
++{
++ flexcan1_en = enable;
++ mx6q_flexcan_switch();
++}
++
++static int __init imx6q_flexcan_fixup_auto(void)
++{
++ struct device_node *np;
++
++ np = of_find_node_by_path("/soc/aips-bus@02000000/can@02090000");
++ if (!np)
++ return -ENODEV;
++
++ flexcan_en_gpio = of_get_named_gpio(np, "trx-en-gpio", 0);
++ flexcan_stby_gpio = of_get_named_gpio(np, "trx-stby-gpio", 0);
++ if (gpio_is_valid(flexcan_en_gpio) && gpio_is_valid(flexcan_stby_gpio) &&
++ !gpio_request_one(flexcan_en_gpio, GPIOF_DIR_OUT, "flexcan-trx-en") &&
++ !gpio_request_one(flexcan_stby_gpio, GPIOF_DIR_OUT, "flexcan-trx-stby")) {
++ /* flexcan 0 & 1 are using the same GPIOs for transceiver */
++ flexcan_pdata[0].transceiver_switch = imx6q_flexcan0_switch_auto;
++ flexcan_pdata[1].transceiver_switch = imx6q_flexcan1_switch_auto;
++ }
++
++ return 0;
++}
++
+ /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
+ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
+ {
+@@ -112,6 +220,14 @@
+ {
+ u16 val;
+
++ /* disable phy AR8031 SmartEEE function. */
++ phy_write(dev, 0xd, 0x3);
++ phy_write(dev, 0xe, 0x805d);
++ phy_write(dev, 0xd, 0x4003);
++ val = phy_read(dev, 0xe);
++ val &= ~(0x1 << 8);
++ phy_write(dev, 0xe, val);
++
+ /* To enable AR8031 output a 125MHz clk from CLK_25M */
+ phy_write(dev, 0xd, 0x7);
+ phy_write(dev, 0xe, 0x8016);
+@@ -137,20 +253,11 @@
+ {
+ u16 val;
+
+- /* Ar803x phy SmartEEE feature cause link status generates glitch,
+- * which cause ethernet link down/up issue, so disable SmartEEE
+- */
+- phy_write(dev, 0xd, 0x3);
+- phy_write(dev, 0xe, 0x805d);
+- phy_write(dev, 0xd, 0x4003);
+-
+- val = phy_read(dev, 0xe);
+- phy_write(dev, 0xe, val & ~(1 << 8));
+-
+ /*
+- * Enable 125MHz clock from CLK_25M on the AR8031. This
+- * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
+- * Also, introduce a tx clock delay.
++ * Disable SmartEEE and Enable 125MHz clock from
++ * CLK_25M on the AR8031. This is fed in to the
++ * IMX6 on the ENET_REF_CLK (V22) pad. Also,
++ * introduce a tx clock delay.
+ *
+ * This is the same as is the AR8031 fixup.
+ */
+@@ -161,6 +268,31 @@
+ if (val & BMCR_PDOWN)
+ phy_write(dev, 0x0, val & ~BMCR_PDOWN);
+
++ if (!ar803x_smarteee)
++ return 0;
++
++ /* Ar803x phy SmartEEE feature cause link status generates glitch,
++ * which cause ethernet link down/up issue, so disable SmartEEE
++ */
++ phy_write(dev, 0xd, 0x3);
++ phy_write(dev, 0xe, 0x805d);
++ phy_write(dev, 0xd, 0x4003);
++ val = phy_read(dev, 0xe);
++ val |= (0x1 << 8);
++ phy_write(dev, 0xe, val);
++
++ /* Increase 1000BT tw time for SmartEEE. It seems that we need
++ * a bit more time than standard to git up and running. Bumping
++ * up the Tw time allows us to enable SmartEEE without generating
++ * ethernet disconnects occasionally
++ */
++ phy_write(dev, 0xd, 0x3);
++ phy_write(dev, 0xe, 0x805b);
++ phy_write(dev, 0xd, 0x4003);
++ val = phy_read(dev, 0xe);
++ val = 0x1717;
++ phy_write(dev, 0xe, val);
++
+ return 0;
+ }
+
+@@ -182,8 +314,27 @@
+
+ static void __init imx6q_1588_init(void)
+ {
++ struct device_node *np;
++ struct clk *ptp_clk;
+ struct regmap *gpr;
+
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec");
++ if (!np) {
++ pr_warn("%s: failed to find fec node\n", __func__);
++ return;
++ }
++
++ ptp_clk = of_clk_get(np, 2);
++ if (IS_ERR(ptp_clk)) {
++ pr_warn("%s: failed to get ptp clock\n", __func__);
++ goto put_node;
++ }
++
++ /*
++ * If enet_ref from ANATOP/CCM is the PTP clock source, we need to
++ * set bit IOMUXC_GPR1[21]. Or the PTP clock must be from pad
++ * (external OSC), and we need to clear the bit.
++ */
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr))
+ regmap_update_bits(gpr, IOMUXC_GPR1,
+@@ -192,6 +343,87 @@
+ else
+ pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
+
++ clk_put(ptp_clk);
++put_node:
++ of_node_put(np);
++}
++
++static void __init imx6q_csi_mux_init(void)
++{
++ /*
++ * MX6Q SabreSD board:
++ * IPU1 CSI0 connects to parallel interface.
++ * Set GPR1 bit 19 to 0x1.
++ *
++ * MX6DL SabreSD board:
++ * IPU1 CSI0 connects to parallel interface.
++ * Set GPR13 bit 0-2 to 0x4.
++ * IPU1 CSI1 connects to MIPI CSI2 virtual channel 1.
++ * Set GPR13 bit 3-5 to 0x1.
++ */
++ struct regmap *gpr;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
++ of_machine_is_compatible("fsl,imx6q-sabreauto"))
++ regmap_update_bits(gpr, IOMUXC_GPR1, 1 << 19, 1 << 19);
++ else if (of_machine_is_compatible("fsl,imx6dl-sabresd") ||
++ of_machine_is_compatible("fsl,imx6dl-sabreauto"))
++ regmap_update_bits(gpr, IOMUXC_GPR13, 0x3F, 0x0C);
++ } else {
++ pr_err("%s(): failed to find fsl,imx6q-iomux-gpr regmap\n",
++ __func__);
++ }
++}
++
++static inline void imx6q_enet_init(void)
++{
++ imx6_enet_mac_init("fsl,imx6q-fec");
++ imx6q_enet_phy_init();
++ imx6q_1588_init();
++ imx6q_enet_plt_init();
++}
++
++/* Add auxdata to pass platform data */
++static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = {
++ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02090000, NULL, &flexcan_pdata[0]),
++ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02094000, NULL, &flexcan_pdata[1]),
++ OF_DEV_AUXDATA("fsl,imx6q-fec", 0x02188000, NULL, &fec_pdata),
++ { /* sentinel */ }
++};
++
++static void __init imx6q_axi_init(void)
++{
++ struct regmap *gpr;
++ unsigned int mask;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ /*
++ * Enable the cacheable attribute of VPU and IPU
++ * AXI transactions.
++ */
++ mask = IMX6Q_GPR4_VPU_WR_CACHE_SEL |
++ IMX6Q_GPR4_VPU_RD_CACHE_SEL |
++ IMX6Q_GPR4_VPU_P_WR_CACHE_VAL |
++ IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK |
++ IMX6Q_GPR4_IPU_WR_CACHE_CTL |
++ IMX6Q_GPR4_IPU_RD_CACHE_CTL;
++ regmap_update_bits(gpr, IOMUXC_GPR4, mask, mask);
++
++ /* Increase IPU read QoS priority */
++ regmap_update_bits(gpr, IOMUXC_GPR6,
++ IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK |
++ IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK,
++ (0xf << 16) | (0x7 << 20));
++ regmap_update_bits(gpr, IOMUXC_GPR7,
++ IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK |
++ IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK,
++ (0xf << 16) | (0x7 << 20));
++ } else {
++ pr_warn("failed to find fsl,imx6q-iomuxc-gpr regmap\n");
++ }
+ }
+
+ static void __init imx6q_init_machine(void)
+@@ -207,22 +439,26 @@
+ if (parent == NULL)
+ pr_warn("failed to initialize soc device\n");
+
+- imx6q_enet_phy_init();
+-
+- of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
++ of_platform_populate(NULL, of_default_bus_match_table,
++ imx6q_auxdata_lookup, parent);
+
++ imx6q_enet_init();
+ imx_anatop_init();
+- imx6q_pm_init();
+- imx6q_1588_init();
++ imx6q_csi_mux_init();
++ cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
++ imx6q_axi_init();
+ }
+
+ #define OCOTP_CFG3 0x440
+ #define OCOTP_CFG3_SPEED_SHIFT 16
+ #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
++#define OCOTP_CFG3_SPEED_996MHZ 0x2
++#define OCOTP_CFG3_SPEED_852MHZ 0x1
+
+-static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
++static void __init imx6q_opp_check_speed_grading(struct device *cpu_dev)
+ {
+ struct device_node *np;
++ struct dev_pm_opp *opp;
+ void __iomem *base;
+ u32 val;
+
+@@ -238,11 +474,50 @@
+ goto put_node;
+ }
+
++ /*
++ * SPEED_GRADING[1:0] defines the max speed of ARM:
++ * 2b'11: 1200000000Hz;
++ * 2b'10: 996000000Hz;
++ * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
++ * 2b'00: 792000000Hz;
++ * We need to set the max speed of ARM according to fuse map.
++ */
+ val = readl_relaxed(base + OCOTP_CFG3);
+ val >>= OCOTP_CFG3_SPEED_SHIFT;
+- if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
+- if (dev_pm_opp_disable(cpu_dev, 1200000000))
+- pr_warn("failed to disable 1.2 GHz OPP\n");
++ val &= 0x3;
++
++ if (val != OCOTP_CFG3_SPEED_1P2GHZ) {
++ opp = dev_pm_opp_find_freq_exact(cpu_dev, 1200000000, true);
++ if (!IS_ERR(opp)) {
++ if (dev_pm_opp_disable(cpu_dev, 1200000000))
++ pr_warn("failed to disable 1.2 GHz OPP\n");
++ }
++ }
++ if (val < OCOTP_CFG3_SPEED_996MHZ) {
++ opp = dev_pm_opp_find_freq_exact(cpu_dev, 996000000, true);
++ if (!IS_ERR(opp)) {
++ if (dev_pm_opp_disable(cpu_dev, 996000000))
++ pr_warn("failed to disable 996 MHz OPP\n");
++ }
++ }
++ if (cpu_is_imx6q()) {
++ if (val != OCOTP_CFG3_SPEED_852MHZ) {
++ opp = dev_pm_opp_find_freq_exact(cpu_dev, 852000000, true);
++ if (!IS_ERR(opp)) {
++ if (dev_pm_opp_disable(cpu_dev, 852000000))
++ pr_warn("failed to disable 852 MHz OPP\n");
++ }
++ }
++ }
++
++ if (IS_ENABLED(CONFIG_MX6_VPU_352M)) {
++ opp = dev_pm_opp_find_freq_exact(cpu_dev, 352000000, true);
++ if (!IS_ERR(opp)) {
++ if (dev_pm_opp_disable(cpu_dev, 396000000))
++ pr_warn("failed to disable 396MHz OPP\n");
++ pr_info("remove 396MHz OPP for VPU running at 352MHz!\n");
++ }
++ }
+
+ put_node:
+ of_node_put(np);
+@@ -268,7 +543,7 @@
+ goto put_node;
+ }
+
+- imx6q_opp_check_1p2ghz(cpu_dev);
++ imx6q_opp_check_speed_grading(cpu_dev);
+
+ put_node:
+ of_node_put(np);
+@@ -284,19 +559,27 @@
+ * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
+ * to run cpuidle on them.
+ */
+- if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
++ if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_1)
++ || (cpu_is_imx6dl() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_0))
+ imx6q_cpuidle_init();
+
+ if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
+ imx6q_opp_init();
+ platform_device_register(&imx6q_cpufreq_pdev);
+ }
++
++ if (of_machine_is_compatible("fsl,imx6q-sabreauto")
++ || of_machine_is_compatible("fsl,imx6dl-sabreauto"))
++ imx6q_flexcan_fixup_auto();
+ }
+
+ static void __init imx6q_map_io(void)
+ {
+ debug_ll_io_init();
+ imx_scu_map_io();
++ imx6_pm_map_io();
++ imx6_busfreq_map_io();
+ }
+
+ static void __init imx6q_init_irq(void)
+@@ -308,13 +591,19 @@
+ irqchip_init();
+ }
+
+-static const char *imx6q_dt_compat[] __initconst = {
++static const char *imx6q_dt_compat[] __initdata = {
+ "fsl,imx6dl",
+ "fsl,imx6q",
+ NULL,
+ };
+
+ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
++ /*
++ * i.MX6Q/DL maps system memory at 0x10000000 (offset 256MiB), and
++ * GPU has a limit on physical address that it accesses, which must
++ * be below 2GiB.
++ */
++ .dma_zone_size = (SZ_2G - SZ_256M),
+ .smp = smp_ops(imx_smp_ops),
+ .map_io = imx6q_map_io,
+ .init_irq = imx6q_init_irq,
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mach-imx6sl.c linux-3.14.72/arch/arm/mach-imx/mach-imx6sl.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mach-imx6sl.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/mach-imx6sl.c 2016-06-19 22:11:55.053156547 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -17,8 +17,9 @@
+ #include <asm/mach/map.h>
+
+ #include "common.h"
++#include "cpuidle.h"
+
+-static void __init imx6sl_fec_init(void)
++static void __init imx6sl_fec_clk_init(void)
+ {
+ struct regmap *gpr;
+
+@@ -29,9 +30,14 @@
+ IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK, 0);
+ regmap_update_bits(gpr, IOMUXC_GPR1,
+ IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK, 0);
+- } else {
++ } else
+ pr_err("failed to find fsl,imx6sl-iomux-gpr regmap\n");
+- }
++}
++
++static inline void imx6sl_fec_init(void)
++{
++ imx6sl_fec_clk_init();
++ imx6_enet_mac_init("fsl,imx6sl-fec");
+ }
+
+ static void __init imx6sl_init_late(void)
+@@ -39,6 +45,8 @@
+ /* imx6sl reuses imx6q cpufreq driver */
+ if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
+ platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
++
++ imx6sl_cpuidle_init();
+ }
+
+ static void __init imx6sl_init_machine(void)
+@@ -55,8 +63,7 @@
+
+ imx6sl_fec_init();
+ imx_anatop_init();
+- /* Reuse imx6q pm code */
+- imx6q_pm_init();
++ imx6sl_pm_init();
+ }
+
+ static void __init imx6sl_init_irq(void)
+@@ -73,8 +80,15 @@
+ NULL,
+ };
+
++static void __init imx6sl_map_io(void)
++{
++ debug_ll_io_init();
++ imx6_pm_map_io();
++ imx6_busfreq_map_io();
++}
++
+ DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
+- .map_io = debug_ll_io_init,
++ .map_io = imx6sl_map_io,
+ .init_irq = imx6sl_init_irq,
+ .init_machine = imx6sl_init_machine,
+ .init_late = imx6sl_init_late,
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mach-imx6sx.c linux-3.14.72/arch/arm/mach-imx/mach-imx6sx.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mach-imx6sx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mach-imx6sx.c 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,340 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/can/platform/flexcan.h>
++#include <linux/gpio.h>
++#include <linux/irqchip.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <linux/of_platform.h>
++#include <linux/phy.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/pm_opp.h>
++#include <linux/fec.h>
++#include <linux/netdevice.h>
++#include <asm/mach/arch.h>
++#include <asm/mach/map.h>
++
++#include "common.h"
++#include "cpuidle.h"
++
++static struct fec_platform_data fec_pdata[2];
++static struct flexcan_platform_data flexcan_pdata[2];
++static int flexcan_en_gpio;
++static int flexcan_en_active_high;
++static int flexcan_stby_gpio;
++static int flexcan_stby_active_high;
++static int flexcan0_en;
++static int flexcan1_en;
++
++static void imx6sx_fec1_sleep_enable(int enabled)
++{
++ struct regmap *gpr;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ if (enabled)
++ regmap_update_bits(gpr, IOMUXC_GPR4,
++ IMX6SX_GPR4_FEC_ENET1_STOP_REQ,
++ IMX6SX_GPR4_FEC_ENET1_STOP_REQ);
++ else
++ regmap_update_bits(gpr, IOMUXC_GPR4,
++ IMX6SX_GPR4_FEC_ENET1_STOP_REQ, 0);
++ } else
++ pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
++}
++
++static void imx6sx_fec2_sleep_enable(int enabled)
++{
++ struct regmap *gpr;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ if (enabled)
++ regmap_update_bits(gpr, IOMUXC_GPR4,
++ IMX6SX_GPR4_FEC_ENET2_STOP_REQ,
++ IMX6SX_GPR4_FEC_ENET2_STOP_REQ);
++ else
++ regmap_update_bits(gpr, IOMUXC_GPR4,
++ IMX6SX_GPR4_FEC_ENET2_STOP_REQ, 0);
++ } else
++ pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
++}
++
++static void __init imx6sx_enet_plt_init(void)
++{
++ struct device_node *np;
++
++ np = of_find_node_by_path("/soc/aips-bus@02100000/ethernet@02188000");
++ if (np && of_get_property(np, "fsl,magic-packet", NULL))
++ fec_pdata[0].sleep_mode_enable = imx6sx_fec1_sleep_enable;
++ np = of_find_node_by_path("/soc/aips-bus@02100000/ethernet@021b4000");
++ if (np && of_get_property(np, "fsl,magic-packet", NULL))
++ fec_pdata[1].sleep_mode_enable = imx6sx_fec2_sleep_enable;
++}
++
++static void mx6sx_flexcan_switch(void)
++{
++ if (flexcan0_en || flexcan1_en) {
++ gpio_set_value_cansleep(flexcan_en_gpio,
++ !flexcan_en_active_high);
++ gpio_set_value_cansleep(flexcan_stby_gpio,
++ !flexcan_stby_active_high);
++ gpio_set_value_cansleep(flexcan_en_gpio,
++ flexcan_en_active_high);
++ gpio_set_value_cansleep(flexcan_stby_gpio,
++ flexcan_stby_active_high);
++ } else {
++ /*
++ * avoid to disable CAN xcvr if any of the CAN interfaces
++ * are down. XCRV will be disabled only if both CAN2
++ * interfaces are DOWN.
++ */
++ gpio_set_value_cansleep(flexcan_en_gpio,
++ !flexcan_en_active_high);
++ gpio_set_value_cansleep(flexcan_stby_gpio,
++ !flexcan_stby_active_high);
++ }
++}
++
++static void imx6sx_arm2_flexcan0_switch(int enable)
++{
++ flexcan0_en = enable;
++ mx6sx_flexcan_switch();
++}
++
++static void imx6sx_arm2_flexcan1_switch(int enable)
++{
++ flexcan1_en = enable;
++ mx6sx_flexcan_switch();
++}
++
++static int __init imx6sx_arm2_flexcan_fixup(void)
++{
++ struct device_node *np;
++ enum of_gpio_flags en_flags, stby_flags;
++ bool canfd_en = false;
++ int wakeup_gpio;
++
++ np = of_find_node_by_path("/soc/aips-bus@02000000/can@02090000");
++ if (!np)
++ return -ENODEV;
++
++
++ /* Wakeup transceiver first in case it's in sleep mode by default */
++ wakeup_gpio = of_get_named_gpio(np, "trx-wakeup-gpio", 0);
++ if (gpio_is_valid(wakeup_gpio) &&
++ !gpio_request_one(wakeup_gpio, GPIOF_OUT_INIT_HIGH, "flexcan-trx-wakeup")) {
++ gpio_set_value_cansleep(wakeup_gpio, 0);
++ gpio_set_value_cansleep(wakeup_gpio, 1);
++ }
++
++ flexcan_en_gpio = of_get_named_gpio_flags(np, "trx-en-gpio", 0, &en_flags);
++ flexcan_stby_gpio = of_get_named_gpio_flags(np, "trx-stby-gpio", 0, &stby_flags);
++
++ if (gpio_is_valid(flexcan_en_gpio) && gpio_is_valid(flexcan_stby_gpio) &&
++ !gpio_request_one(flexcan_en_gpio, GPIOF_DIR_OUT, "flexcan-trx-en") &&
++ !gpio_request_one(flexcan_stby_gpio, GPIOF_DIR_OUT, "flexcan-trx-stby")) {
++ /* flexcan 0 & 1 are using the same GPIOs for transceiver */
++ flexcan_pdata[0].transceiver_switch = imx6sx_arm2_flexcan0_switch;
++ flexcan_pdata[1].transceiver_switch = imx6sx_arm2_flexcan1_switch;
++ if (!(en_flags & OF_GPIO_ACTIVE_LOW))
++ flexcan_en_active_high = 1;
++
++ if (!(stby_flags & OF_GPIO_ACTIVE_LOW))
++ flexcan_stby_active_high = 1;
++ }
++
++ /*
++ * Switch on the transceiver by default for board with canfd enabled
++ * since canfd driver does not handle it.
++ * Two CAN instances share the same switch.
++ */
++ for_each_node_by_name(np, "canfd") {
++ if (of_device_is_available(np)) {
++ canfd_en = true;
++ break;
++ }
++ }
++
++ if (of_machine_is_compatible("fsl,imx6sx-sdb") && canfd_en)
++ imx6sx_arm2_flexcan0_switch(1);
++
++ return 0;
++}
++
++static int ar8031_phy_fixup(struct phy_device *dev)
++{
++ u16 val;
++
++ /* Set RGMII IO voltage to 1.8V */
++ phy_write(dev, 0x1d, 0x1f);
++ phy_write(dev, 0x1e, 0x8);
++
++ /* disable phy AR8031 SmartEEE function. */
++ phy_write(dev, 0xd, 0x3);
++ phy_write(dev, 0xe, 0x805d);
++ phy_write(dev, 0xd, 0x4003);
++ val = phy_read(dev, 0xe);
++ val &= ~(0x1 << 8);
++ phy_write(dev, 0xe, val);
++
++ /* introduce tx clock delay */
++ phy_write(dev, 0x1d, 0x5);
++ val = phy_read(dev, 0x1e);
++ val |= 0x0100;
++ phy_write(dev, 0x1e, val);
++ return 0;
++}
++
++#define PHY_ID_AR8031 0x004dd074
++static void __init imx6sx_enet_phy_init(void)
++{
++ if (IS_BUILTIN(CONFIG_PHYLIB))
++ phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
++ ar8031_phy_fixup);
++}
++
++static void __init imx6sx_enet_clk_sel(void)
++{
++ struct regmap *gpr;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ regmap_update_bits(gpr, IOMUXC_GPR1,
++ IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
++ regmap_update_bits(gpr, IOMUXC_GPR1,
++ IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
++ } else {
++ pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
++ }
++}
++
++static inline void imx6sx_enet_init(void)
++{
++ imx6_enet_mac_init("fsl,imx6sx-fec");
++ imx6sx_enet_phy_init();
++ imx6sx_enet_clk_sel();
++ imx6sx_enet_plt_init();
++}
++
++/* Add auxdata to pass platform data */
++static const struct of_dev_auxdata imx6sx_auxdata_lookup[] __initconst = {
++ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02090000, NULL, &flexcan_pdata[0]),
++ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02094000, NULL, &flexcan_pdata[1]),
++ OF_DEV_AUXDATA("fsl,imx6sx-fec", 0x02188000, NULL, &fec_pdata[0]),
++ OF_DEV_AUXDATA("fsl,imx6sx-fec", 0x021b4000, NULL, &fec_pdata[1]),
++ { /* sentinel */ }
++};
++
++static inline void imx6sx_qos_init(void)
++{
++ struct device_node *np;
++ void __iomem *src_base;
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpu");
++ if (!np || !of_device_is_available(np))
++ return;
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-qosc");
++ if (!np)
++ return;
++ src_base = of_iomap(np, 0);
++ writel_relaxed(0, src_base); /* Disable clkgate & soft_rst */
++ writel_relaxed(0, src_base+0x60); /* Enable all masters */
++ writel_relaxed(0, src_base+0x1400); /* Disable clkgate & soft_rst for gpu */
++ writel_relaxed(0x0f000222, src_base+0x1400+0xd0); /* Set Write QoS 2 for gpu */
++ writel_relaxed(0x0f000822, src_base+0x1400+0xe0); /* Set Read QoS 8 for gpu */
++ return;
++}
++
++static void __init imx6sx_init_machine(void)
++{
++ struct device *parent;
++
++ mxc_arch_reset_init_dt();
++
++ parent = imx_soc_device_init();
++ if (parent == NULL)
++ pr_warn("failed to initialize soc device\n");
++
++ of_platform_populate(NULL, of_default_bus_match_table,
++ imx6sx_auxdata_lookup, parent);
++
++ imx6sx_enet_init();
++ imx_anatop_init();
++ imx6sx_pm_init();
++ imx6sx_qos_init();
++}
++
++static void __init imx6sx_init_irq(void)
++{
++ imx_init_revision_from_anatop();
++ imx_init_l2cache();
++ imx_src_init();
++ imx_gpc_init();
++ irqchip_init();
++}
++
++static const char *imx6sx_dt_compat[] __initdata = {
++ "fsl,imx6sx",
++ NULL,
++};
++
++static void __init imx6sx_opp_init(struct device *cpu_dev)
++{
++ struct device_node *np;
++
++ np = of_find_node_by_path("/cpus/cpu@0");
++ if (!np) {
++ pr_warn("failed to find cpu0 node\n");
++ return;
++ }
++
++ cpu_dev->of_node = np;
++ if (of_init_opp_table(cpu_dev))
++ pr_warn("failed to init OPP table\n");
++
++ of_node_put(np);
++}
++
++static struct platform_device imx6sx_cpufreq_pdev = {
++ .name = "imx6q-cpufreq",
++};
++
++static void __init imx6sx_init_late(void)
++{
++ if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
++ imx6sx_opp_init(&imx6sx_cpufreq_pdev.dev);
++ platform_device_register(&imx6sx_cpufreq_pdev);
++ }
++
++ if (of_machine_is_compatible("fsl,imx6sx-sdb") ||
++ of_machine_is_compatible("fsl,imx6sx-sabreauto"))
++ imx6sx_arm2_flexcan_fixup();
++
++ imx6sx_cpuidle_init();
++}
++
++static void __init imx6sx_map_io(void)
++{
++ debug_ll_io_init();
++ imx6_pm_map_io();
++ imx6_busfreq_map_io();
++}
++
++DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
++ .map_io = imx6sx_map_io,
++ .init_irq = imx6sx_init_irq,
++ .init_machine = imx6sx_init_machine,
++ .init_late = imx6sx_init_late,
++ .dt_compat = imx6sx_dt_compat,
++ .restart = mxc_restart,
++MACHINE_END
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mach-vf610.c linux-3.14.72/arch/arm/mach-imx/mach-vf610.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mach-vf610.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/mach-vf610.c 2016-06-19 22:11:55.053156547 +0200
+@@ -22,7 +22,7 @@
+
+ static void __init vf610_init_irq(void)
+ {
+- l2x0_of_init(0, ~0UL);
++ l2x0_of_init(0, ~0);
+ irqchip_init();
+ }
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/Makefile linux-3.14.72/arch/arm/mach-imx/Makefile
+--- linux-3.14.72.orig/arch/arm/mach-imx/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/Makefile 2016-06-19 22:11:55.053156547 +0200
+@@ -16,7 +16,8 @@
+
+ obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
+ clk-pfd.o clk-busy.o clk.o \
+- clk-fixup-div.o clk-fixup-mux.o
++ clk-fixup-div.o clk-fixup-mux.o \
++ clk-gate-exclusive.o
+
+ obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
+ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
+@@ -30,6 +31,8 @@
+ ifeq ($(CONFIG_CPU_IDLE),y)
+ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
+ obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o
++obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o
++obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o
+ endif
+
+ ifdef CONFIG_SND_IMX_SOC
+@@ -95,15 +98,34 @@
+ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
+ obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
+ obj-$(CONFIG_HAVE_IMX_SRC) += src.o
++obj-$(CONFIG_HAVE_IMX_MCC) += mcc_api.o mcc_common.o mcc_linux.o mcc_imx6sx.o
+ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
+ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+-obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
+-obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
++obj-$(CONFIG_SOC_IMX6Q) += common-imx6.o clk-imx6q.o mach-imx6q.o
++obj-$(CONFIG_SOC_IMX6SL) += common-imx6.o clk-imx6sl.o mach-imx6sl.o
++obj-$(CONFIG_SOC_IMX6SX) += common-imx6.o clk-imx6sx.o mach-imx6sx.o mu.o
++
++ifeq ($(CONFIG_SUSPEND),y)
++AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
++obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
++endif
++obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
++
++ifeq ($(CONFIG_ARM_IMX6Q_CPUFREQ),y)
++obj-y += busfreq-imx6.o
++AFLAGS_ddr3_freq_imx6.o :=-Wa,-march=armv7-a
++obj-$(CONFIG_SOC_IMX6Q) += ddr3_freq_imx6.o busfreq_ddr3.o
++AFLAGS_lpddr2_freq_imx6.o :=-Wa,-march=armv7-a
++AFLAGS_imx6sl_lpm_wfi.o :=-Wa,-march=armv7-a
++obj-$(CONFIG_SOC_IMX6SL) += busfreq_lpddr2.o lpddr2_freq_imx6.o imx6sl_lpm_wfi.o
++AFLAGS_lpddr2_freq_imx6sx.o :=-Wa,-march=armv7-a
++AFLAGS_ddr3_freq_imx6sx.o :=-Wa,-march=armv7-a
++AFLAGS_imx6sx_low_power_idle.o :=-Wa,-march=armv7-a
++obj-$(CONFIG_SOC_IMX6SX) += ddr3_freq_imx6sx.o busfreq_ddr3.o lpddr2_freq_imx6sx.o \
++ imx6sx_low_power_idle.o busfreq_lpddr2.o lpddr2_freq_imx6.o
++endif
+
+-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
+-# i.MX6SL reuses i.MX6Q code
+-obj-$(CONFIG_SOC_IMX6SL) += pm-imx6q.o headsmp.o
+
+ # i.MX5 based machines
+ obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mcc_api.c linux-3.14.72/arch/arm/mach-imx/mcc_api.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mcc_api.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mcc_api.c 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,951 @@
++/*
++ * This file contains MCC library API functions implementation
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#include "mcc_config.h"
++#if (MCC_OS_USED == MCC_MQX)
++#include <string.h>
++#include "mcc_config.h"
++#include "mcc_common.h"
++#include "mcc_api.h"
++#include "mcc_mqx.h"
++#elif (MCC_OS_USED == MCC_LINUX)
++#include <linux/mcc_api.h>
++#include <linux/mcc_imx6sx.h>
++#include <linux/mcc_linux.h>
++#include <linux/imx_sema4.h>
++#endif
++
++const char * const init_string = MCC_INIT_STRING;
++const char * const version_string = MCC_VERSION_STRING;
++
++static int mcc_recv_common_part(MCC_ENDPOINT *endpoint, unsigned int timeout_ms, MCC_RECEIVE_LIST **list);
++static int mcc_get_buffer_internal(void **buffer, MCC_MEM_SIZE *buf_size, unsigned int timeout_ms);
++static int mcc_free_buffer_internal(void *buffer);
++/*!
++ * \brief This function initializes the Multi Core Communication subsystem for a given node.
++ *
++ * This function should only be called once per node (once in MQX, once per a process in Linux).
++ * It tries to initialize the bookkeeping structure when the init_string member of this structure
++ * is not equal to MCC_INIT_STRING, i.e. when no other core had performed the initialization yet.
++ * Note, that this way of bookkeeping data re-initialization protection is not powerful enough and
++ * the user application should not rely on this method. Instead, the application should be designed
++ * to unambiguously assign the core that will perform the MCC initialization.
++ * Clear the shared memory before the first core is attempting to initialize the MCC
++ * (in some cases MCC_INIT_STRING remains in the shared memory after the application reset and could
++ * cause that the bookkeeping data structure is not initialized correctly).
++ *
++ * \param[in] node Node number that will be used in endpoints created by this process.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_INT (interrupt registration error)
++ * \return MCC_ERR_VERSION (incorrect MCC version used - compatibility issue)
++ * \return MCC_ERR_OSSYNC (OS synchronization module(s) initialization failed)
++ *
++ * \see mcc_destroy
++ * \see MCC_BOOKEEPING_STRUCT
++ */
++int mcc_initialize(MCC_NODE node)
++{
++ int i,j = 0;
++ int return_value = MCC_SUCCESS;
++ MCC_SIGNAL tmp_signals_received = {(MCC_SIGNAL_TYPE)0, {(MCC_CORE)0, (MCC_NODE)0, (MCC_PORT)0}};
++
++ /* Initialize synchronization module for shared data protection */
++ return_value = mcc_init_semaphore(MCC_SHMEM_SEMAPHORE_NUMBER);
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Initialize all necessary OS synchronization module(s)
++ (for unblocking tasks waiting for new received data and for unblocking tasks waiting for a free buffer) */
++ return_value = mcc_init_os_sync();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Register CPU-to-CPU interrupt for inter-core signaling */
++ //mcc_register_cpu_to_cpu_isr(MCC_CORE0_CPU_TO_CPU_VECTOR);
++ return_value = mcc_register_cpu_to_cpu_isr();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Initialize the bookeeping structure */
++ bookeeping_data = (MCC_BOOKEEPING_STRUCT *)mcc_get_bookeeping_data();
++ MCC_DCACHE_INVALIDATE_MLINES(bookeeping_data, sizeof(MCC_BOOKEEPING_STRUCT));
++ if(strcmp(bookeeping_data->init_string, init_string) != 0) {
++ /* MCC not initialized yet, do it now */
++ /* Zero it all - no guarantee Linux or uboot didnt touch it before it was reserved */
++ memset((void*) bookeeping_data, 0, sizeof(struct mcc_bookeeping_struct));
++
++ /* Set init_string in case it has not been set yet by another core */
++ mcc_memcpy((void*)init_string, bookeeping_data->init_string, (unsigned int)sizeof(bookeeping_data->init_string));
++
++ /* Set version_string */
++ mcc_memcpy((void*)version_string, bookeeping_data->version_string, (unsigned int)sizeof(bookeeping_data->version_string));
++
++ /* Initialize the free list */
++ bookeeping_data->free_list.head = (MCC_RECEIVE_BUFFER*)MCC_MEM_VIRT_TO_PHYS(&bookeeping_data->r_buffers[0]);
++ bookeeping_data->free_list.tail = (MCC_RECEIVE_BUFFER*)MCC_MEM_VIRT_TO_PHYS(&bookeeping_data->r_buffers[MCC_ATTR_NUM_RECEIVE_BUFFERS-1]);
++
++ /* Initialize receive buffers */
++ for(i=0; i<MCC_ATTR_NUM_RECEIVE_BUFFERS-1; i++) {
++ bookeeping_data->r_buffers[i].next = (MCC_RECEIVE_BUFFER*)MCC_MEM_VIRT_TO_PHYS(&bookeeping_data->r_buffers[i+1]);
++ }
++ bookeeping_data->r_buffers[MCC_ATTR_NUM_RECEIVE_BUFFERS-1].next = null;
++
++ /* Initialize signal queues */
++ for(i=0; i<MCC_NUM_CORES; i++) {
++ for(j=0; j<MCC_MAX_OUTSTANDING_SIGNALS; j++) {
++ bookeeping_data->signals_received[i][j] = tmp_signals_received;
++ }
++ bookeeping_data->signal_queue_head[i] = 0;
++ bookeeping_data->signal_queue_tail[i] = 0;
++ }
++
++ /* Mark all endpoint ports as free */
++ for(i=0; i<MCC_ATTR_MAX_RECEIVE_ENDPOINTS; i++) {
++ bookeeping_data->endpoint_table[i].endpoint.port = MCC_RESERVED_PORT_NUMBER;
++ }
++ }
++ else {
++ /* MCC already initialized - check the major number of the version string to ensure compatibility */
++ if(strncmp(bookeeping_data->version_string, version_string, 4) != 0) {
++ return_value = MCC_ERR_VERSION;
++ }
++ }
++
++ MCC_DCACHE_FLUSH_MLINES(bookeeping_data, sizeof(MCC_BOOKEEPING_STRUCT));
++ return return_value;
++}
++
++/*!
++ * \brief This function de-initializes the Multi Core Communication subsystem for a given node.
++ *
++ * The function frees all resources of the node. Deletes all endpoints and frees any buffers that may have been queued there.
++ *
++ * \param[in] node Node number to be deinitialized.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_OSSYNC (OS synchronization module(s) deinitialization failed)
++ *
++ * \see mcc_initialize
++ */
++int mcc_destroy(MCC_NODE node)
++{
++ int i = 0, return_value;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* All endpoints of the particular node have to be removed from the endpoint table */
++ MCC_DCACHE_INVALIDATE_MLINES(&bookeeping_data->endpoint_table[0], MCC_ATTR_MAX_RECEIVE_ENDPOINTS * sizeof(MCC_ENDPOINT_MAP_ITEM));
++ for(i = 0; i < MCC_ATTR_MAX_RECEIVE_ENDPOINTS; i++) {
++ if (bookeeping_data->endpoint_table[i].endpoint.node == node) {
++ /* Remove the endpoint from the table */
++ mcc_remove_endpoint(bookeeping_data->endpoint_table[i].endpoint);
++ }
++ }
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Deinitialize synchronization module */
++ mcc_deinit_semaphore(MCC_SHMEM_SEMAPHORE_NUMBER);
++
++ /* De-initialize OS synchronization module(s)
++ (for unblocking tasks waiting for new data and for unblocking tasks waiting for a free buffer */
++ return_value = mcc_deinit_os_sync();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
++
++/*!
++ * \brief This function creates an endpoint.
++ *
++ * The function creates an endpoint on the local node with the specified port number.
++ * The core and node provided in the endpoint must match the caller's core and
++ * node, and the port argument must match the endpoint port.
++ *
++ * \param[out] endpoint Pointer to the endpoint triplet to be created.
++ * \param[in] port Port number.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_NOMEM (maximum number of endpoints exceeded)
++ * \return MCC_ERR_ENDPOINT (invalid value for port or endpoint already registered)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ *
++ * \see mcc_destroy_endpoint
++ * \see MCC_ENDPOINT
++ */
++int mcc_create_endpoint(MCC_ENDPOINT *endpoint, MCC_PORT port)
++{
++ int return_value = MCC_SUCCESS;
++
++ /* Fill the endpoint structure */
++ endpoint->core = (MCC_CORE)MCC_CORE_NUMBER;
++ endpoint->node = (MCC_NODE)MCC_NODE_NUMBER;
++ endpoint->port = (MCC_PORT)port;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Add new endpoint data into the book-keeping structure */
++ return_value = mcc_register_endpoint(*endpoint);
++ if(return_value != MCC_SUCCESS) {
++ mcc_release_semaphore();
++ return return_value;
++ }
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
++
++/*!
++ * \brief This function destroys an endpoint.
++ *
++ * The function destroys an endpoint on the local node and frees any buffers that may be queued.
++ *
++ * \param[in] endpoint Pointer to the endpoint triplet to be deleted.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_ENDPOINT (the endpoint doesn't exist)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ *
++ * \see mcc_create_endpoint
++ * \see MCC_ENDPOINT
++ */
++int mcc_destroy_endpoint(MCC_ENDPOINT *endpoint)
++{
++ int return_value = MCC_SUCCESS;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Remove the endpoint data from the book-keeping structure */
++ return_value = mcc_remove_endpoint(*endpoint);
++ if(return_value != MCC_SUCCESS) {
++ mcc_release_semaphore();
++ return return_value;
++ }
++
++ /* Clear OS synchronization module parts associated with the endpoint to be destroyed */
++ mcc_clear_os_sync_for_ep(endpoint);
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
++
++/*!
++ * \brief This function sends a message to an endpoint.
++ *
++ * The message is copied into the MCC buffer and the destination core is signaled.
++ *
++ * \param[in] src_endpoint Pointer to the local endpoint identifying the source endpoint.
++ * \param[in] dest_endpoint Pointer to the destination endpoint to send the message to.
++ * \param[in] msg Pointer to the message to be sent.
++ * \param[in] msg_size Size of the message to be sent in bytes.
++ * \param[in] timeout_ms Timeout, in milliseconds, to wait for a free buffer. A value of 0 means don't wait (non-blocking call). A value of 0xffffffff means wait forever (blocking call).
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_ENDPOINT (the endpoint does not exist)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_INVAL (the msg_size exceeds the size of a data buffer)
++ * \return MCC_ERR_TIMEOUT (timeout exceeded before a buffer became available)
++ * \return MCC_ERR_NOMEM (no free buffer available and timeout_ms set to 0)
++ * \return MCC_ERR_SQ_FULL (signal queue is full)
++ *
++ * \see mcc_recv
++ * \see mcc_recv_nocopy
++ * \see MCC_ENDPOINT
++ */
++int mcc_send(MCC_ENDPOINT *src_endpoint, MCC_ENDPOINT *dest_endpoint, void *msg, MCC_MEM_SIZE msg_size, unsigned int timeout_ms)
++{
++ int return_value;
++ MCC_RECEIVE_LIST *list;
++ MCC_RECEIVE_BUFFER * buf;
++ MCC_SIGNAL affiliated_signal;
++ MCC_MEM_SIZE buffer_size;
++
++ /* Reuse the mcc_get_buffer_internal() function to get the MCC buffer pointer. */
++ return_value = mcc_get_buffer_internal((void**)&buf, &buffer_size, timeout_ms);
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Check if the size of the message to be sent does not exceed the size of the mcc buffer */
++ if(msg_size > buffer_size) {
++ while(MCC_SUCCESS != mcc_free_buffer_internal(buf)) {};
++ return MCC_ERR_INVAL;
++ }
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* As the mcc_get_buffer_internal() returns the pointer to the data field, it
++ is necessary to adjust the pointer to point at the MCC buffer structure beginning. */
++ buf = (MCC_RECEIVE_BUFFER *)((unsigned int)buf - (unsigned int)(&(((MCC_RECEIVE_BUFFER*)0)->data)));
++
++ /* Copy the message into the MCC receive buffer */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)buf, sizeof(MCC_RECEIVE_BUFFER));
++ mcc_memcpy(msg, (void*)buf->data, (unsigned int)msg_size);
++ mcc_memcpy((void*)src_endpoint, (void*)&buf->source, sizeof(MCC_ENDPOINT));
++ buf->data_len = msg_size;
++ MCC_DCACHE_FLUSH_MLINES((void*)buf, sizeof(MCC_RECEIVE_BUFFER));
++
++ /* Get list of buffers kept by the particular endpoint */
++ list = mcc_get_endpoint_list(*dest_endpoint);
++
++ if(list == null) {
++ /* The endpoint does not exists (has not been registered so far),
++ free the buffer and return immediately - error */
++ /* Enqueue the buffer back into the free list */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->free_list, sizeof(MCC_RECEIVE_LIST*));
++ mcc_queue_buffer(&bookeeping_data->free_list, buf);
++
++ mcc_release_semaphore();
++ return MCC_ERR_ENDPOINT;
++ }
++
++ /* Write the signal type into the signal queue of the particular core */
++ affiliated_signal.type = BUFFER_QUEUED;
++ affiliated_signal.destination = *dest_endpoint;
++ return_value = mcc_queue_signal(dest_endpoint->core, affiliated_signal);
++ if(return_value != MCC_SUCCESS) {
++ /* Signal queue is full, free the buffer and return immediately - error */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->free_list, sizeof(MCC_RECEIVE_LIST*));
++ mcc_queue_buffer(&bookeeping_data->free_list, buf);
++
++ mcc_release_semaphore();
++ return return_value;
++ }
++
++ /* Enqueue the buffer into the endpoint buffer list */
++ mcc_queue_buffer(list, buf);
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Signal the other core by generating the CPU-to-CPU interrupt */
++ return_value = mcc_generate_cpu_to_cpu_interrupt();
++
++ return return_value;
++}
++
++/*!
++ * \private
++ *
++ * \brief This function dequeues a buffer from the free list.
++ *
++ * This is an internal implementation of the mcc_get_buffer() function. It is called
++ * either from the mcc_send() or from mcc_get_buffer() when the non-copy-send
++ * mechanism is enabled by the MCC_SEND_RECV_NOCOPY_API_ENABLED macro in mcc_config.h.
++ *
++ * \param[out] buffer Pointer to the MCC buffer dequeued from the free list.
++ * \param[out] buf_size Pointer to an MCC_MEM_SIZE that is used for passing the size of the dequeued MCC buffer to the application.
++ * \param[in] timeout_ms Timeout, in milliseconds, to wait for a free buffer. A value of 0 means don't wait (non-blocking call). A value of 0xffffffff means wait forever (blocking call).
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_TIMEOUT (timeout exceeded before a buffer became available)
++ * \return MCC_ERR_NOMEM (no free buffer available and timeout_ms set to 0)
++ *
++ * \see mcc_send_nocopy
++ * \see mcc_send
++ * \see mcc_get_buffer
++ */
++static int mcc_get_buffer_internal(void **buffer, MCC_MEM_SIZE *buf_size, unsigned int timeout_ms)
++{
++ int return_value;
++ MCC_RECEIVE_BUFFER * buf = null;
++
++ *buffer = null;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Dequeue the buffer from the free list */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->free_list, sizeof(MCC_RECEIVE_LIST*));
++ buf = mcc_dequeue_buffer(&bookeeping_data->free_list);
++
++ /* Semaphore-protected section end */
++ mcc_release_semaphore();
++
++ if(buf == null) {
++ /* Non-blocking call */
++ if(timeout_ms == 0) {
++ return MCC_ERR_NOMEM;
++ } else {
++ /* Wait for the buffer freed event */
++ return_value = mcc_wait_for_buffer_freed((MCC_RECEIVE_BUFFER **)&buf, timeout_ms);
++ if(MCC_SUCCESS != return_value) {
++ return return_value;
++ }
++ }
++ }
++
++ /* Return the MCC buffer size and the pointer to the dequeued MCC buffer */
++ *buf_size = (MCC_MEM_SIZE)sizeof(bookeeping_data->r_buffers[0].data);
++ *buffer = (void*)buf->data;
++ return MCC_SUCCESS;
++}
++
++#if MCC_SEND_RECV_NOCOPY_API_ENABLED
++/*!
++ * \brief This function dequeues a buffer from the free list.
++ *
++ * The application has take the responsibility for MCC buffer de-allocation and
++ * filling the data to be sent into the pre-allocated MCC buffer.
++ *
++ * \param[out] buffer Pointer to the MCC buffer dequeued from the free list.
++ * \param[out] buf_size Pointer to an MCC_MEM_SIZE that is used for passing the size of the dequeued MCC buffer to the application.
++ * \param[in] timeout_ms Timeout, in milliseconds, to wait for a free buffer. A value of 0 means don't wait (non-blocking call). A value of 0xffffffff means wait forever (blocking call).
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_TIMEOUT (timeout exceeded before a buffer became available)
++ * \return MCC_ERR_NOMEM (no free buffer available and timeout_ms set to 0)
++ *
++ * \see mcc_send_nocopy
++ */
++int mcc_get_buffer(void **buffer, MCC_MEM_SIZE *buf_size, unsigned int timeout_ms)
++{
++ return mcc_get_buffer_internal(buffer, buf_size, timeout_ms);
++}
++
++/*!
++ * \brief This function sends a message to an endpoint. The data is NOT copied
++ * from the user-app. buffer but the pointer to already filled message buffer is
++ * provided.
++ *
++ * The application has to take the responsibility for:
++ * 1. MCC buffer de-allocation
++ * 2. filling the data to be sent into the pre-allocated MCC buffer
++ * 3. not exceeding the buffer size when filling the data (MCC_ATTR_BUFFER_SIZE_IN_BYTES)
++ *
++ * Once the data cache is used on the target platform it is good to have MCC buffers
++ * in shared RAM aligned to the cache line size in order not to corrupt entities placed
++ * just before and just after the MCC buffer when flushing the MCC buffer content into
++ * the shared RAM. It is also the application responsibility to flush the data in
++ * that case. If the alignment condition is not fulfilled the application
++ * has to take care about the data cache coherency.
++ * The following scenarios can happen:
++ * A. Data cache is OFF:
++ * - No cache operation needs to be done, the application just
++ * 1. calls the mcc_get_buffer() function,
++ * 2. fills data into the provided MCC buffer,
++ * 3. and finally issues the mcc_send_nocopy() function.
++ * B. Data cache is ON, shared RAM MCC buffers ALIGNED to the cache line size:
++ * - The application has to perform following steps:
++ * 1. call the mcc_get_buffer() to get the pointer to a free message buffer
++ * 2. copy data to be sent into the message buffer
++ * 3. flush all cache lines occupied by the message buffer new data
++ * (maximum of MCC_ATTR_BUFFER_SIZE_IN_BYTES bytes).
++ * 4. call the mcc_send_nocopy() with the correct buffer pointer and the message size passed
++ * C. Data cache is ON, shared RAM MCC buffers NOT ALIGNED:
++ * - The application has to perform following steps:
++ * 1. call the mcc_get_buffer() to get the pointer to a free message buffer
++ * 2. grab the hw semaphore by calling the mcc_get_semaphore() low level MCC function.
++ * 3. invalidate all cache lines occupied by data to be filled into the free message buffer.
++ * (maximum of MCC_ATTR_BUFFER_SIZE_IN_BYTES bytes).
++ * 4. copy data to be sent into the message buffer.
++ * 5. flush all cache lines occupied by the message buffer new data
++ * (maximum of MCC_ATTR_BUFFER_SIZE_IN_BYTES bytes).
++ * 6. release the hw semaphore by calling the mcc_release_semaphore() low level MCC function.
++ * 7. call the mcc_send_nocopy() with the correct buffer pointer and the message size passed.
++ *
++ * After the mcc_send_nocopy() function is issued the message buffer is no more owned
++ * by the sending task and must not be touched anymore unless the mcc_send_nocopy()
++ * function fails and returns an error. In that case the application should try
++ * to re-issue the mcc_send_nocopy() again and if it is still not possible to send
++ * the message and the application wants to give it up from whatever reasons
++ * (for instance the MCC_ERR_ENDPOINT error is returned meaning the endpoint
++ * has not been created yet) the mcc_free_buffer() function could be called,
++ * passing the pointer to the buffer to be freed as a parameter.
++ *
++ * \param[in] src_endpoint Pointer to the local endpoint identifying the source endpoint.
++ * \param[in] dest_endpoint Pointer to the destination endpoint to send the message to.
++ * \param[in] buffer_p Pointer to the MCC buffer of the shared memory where the
++ * data to be sent is stored.
++ * \param[in] msg_size Size of the message to be sent in bytes.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_INVAL (the msg_size exceeds the size of a data buffer)
++ * \return MCC_ERR_ENDPOINT (the endpoint does not exist)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_SQ_FULL (signal queue is full)
++ *
++ * \see mcc_send
++ * \see mcc_get_buffer
++ * \see MCC_ENDPOINT
++ */
++int mcc_send_nocopy(MCC_ENDPOINT *src_endpoint, MCC_ENDPOINT *dest_endpoint, void *buffer_p, MCC_MEM_SIZE msg_size)
++{
++ int return_value;
++ MCC_RECEIVE_BUFFER * buf;
++ MCC_RECEIVE_LIST *list;
++ MCC_SIGNAL affiliated_signal;
++
++ /* Check if the size of the message to be sent does not exceed the size of the mcc buffer */
++ if(msg_size > sizeof(bookeeping_data->r_buffers[0].data)) {
++ return MCC_ERR_INVAL;
++ }
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Get list of buffers kept by the particular endpoint */
++ list = mcc_get_endpoint_list(*dest_endpoint);
++
++ if(list == null) {
++ /* The endpoint does not exists (has not been registered so far) */
++ mcc_release_semaphore();
++ return MCC_ERR_ENDPOINT;
++ }
++
++ /* Store the message size and the source endpoint in the MCC_RECEIVE_BUFFER structure */
++ buf = (MCC_RECEIVE_BUFFER *)((unsigned int)buffer_p - (unsigned int)(&(((MCC_RECEIVE_BUFFER*)0)->data)));
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&buf->source, sizeof(MCC_ENDPOINT) + sizeof(MCC_MEM_SIZE));
++ ((MCC_RECEIVE_BUFFER*)buf)->data_len = msg_size;
++ mcc_memcpy((void*)src_endpoint, (void*)&buf->source, sizeof(MCC_ENDPOINT));
++ MCC_DCACHE_FLUSH_MLINES((void*)(void*)&buf->source, sizeof(MCC_ENDPOINT) + sizeof(MCC_MEM_SIZE));
++
++
++ /* Write the signal type into the signal queue of the particular core */
++ affiliated_signal.type = BUFFER_QUEUED;
++ affiliated_signal.destination = *dest_endpoint;
++ return_value = mcc_queue_signal(dest_endpoint->core, affiliated_signal);
++ if(return_value != MCC_SUCCESS) {
++ /* Signal queue is full - error */
++ mcc_release_semaphore();
++ return return_value;
++ }
++
++ /* Enqueue the buffer into the endpoint buffer list */
++ mcc_queue_buffer(list, (MCC_RECEIVE_BUFFER*)buf);
++
++ /* Semaphore-protected section end */
++ mcc_release_semaphore();
++
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Signal the other core by generating the CPU-to-CPU interrupt */
++ return_value = mcc_generate_cpu_to_cpu_interrupt();
++
++ return return_value;
++}
++#endif /* MCC_SEND_RECV_NOCOPY_API_ENABLED */
++
++/*!
++ * \brief This function receives a message from the specified endpoint if one is available.
++ * The data is copied from the receive buffer into the user supplied buffer.
++ *
++ * This is the "receive with copy" version of the MCC receive function. This version is simple
++ * to use but it requires copying data from shared memory into the user space buffer.
++ * The user has no obligation or burden to manage the shared memory buffers.
++ *
++ * \param[out] src_endpoint Pointer to the MCC_ENDPOINT structure to be filled by the endpoint identifying the message sender.
++ * \param[in] dest_endpoint Pointer to the local receiving endpoint to receive from.
++ * \param[in] buffer Pointer to the user-app. buffer where data will be copied into.
++ * \param[in] buffer_size The maximum number of bytes to copy.
++ * \param[out] recv_size Pointer to an MCC_MEM_SIZE that will contain the number of bytes actually copied into the buffer.
++ * \param[in] timeout_ms Timeout, in milliseconds, to wait for a free buffer. A value of 0 means don't wait (non-blocking call). A value of 0xffffffff means wait forever (blocking call).
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_ENDPOINT (the endpoint does not exist)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_TIMEOUT (timeout exceeded before a new message came)
++ *
++ * \see mcc_send
++ * \see mcc_recv_nocopy
++ * \see MCC_ENDPOINT
++ */
++int mcc_recv(MCC_ENDPOINT *src_endpoint, MCC_ENDPOINT *dest_endpoint, void *buffer, MCC_MEM_SIZE buffer_size, MCC_MEM_SIZE *recv_size, unsigned int timeout_ms)
++{
++ MCC_RECEIVE_LIST *list = null;
++ MCC_RECEIVE_BUFFER * buf;
++ MCC_SIGNAL affiliated_signal;
++ MCC_ENDPOINT tmp_destination = {(MCC_CORE)0, (MCC_NODE)0, (MCC_PORT)0};
++ int return_value, i = 0;
++
++ return_value = mcc_recv_common_part(dest_endpoint, timeout_ms, (MCC_RECEIVE_LIST**)&list);
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void*)list, sizeof(MCC_RECEIVE_LIST*));
++
++ if(list->head == (MCC_RECEIVE_BUFFER*)0) {
++ /* Buffer not dequeued before the timeout */
++ mcc_release_semaphore();
++ return MCC_ERR_TIMEOUT;
++ }
++
++ /* Copy the message from the MCC receive buffer into the user-app. buffer */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&list->head->source, sizeof(MCC_ENDPOINT) + sizeof(MCC_MEM_SIZE));
++ mcc_memcpy((void*)&list->head->source, (void*)src_endpoint, sizeof(MCC_ENDPOINT));
++ if (list->head->data_len > buffer_size) {
++ list->head->data_len = buffer_size;
++ }
++ *recv_size = (MCC_MEM_SIZE)(list->head->data_len);
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&list->head->data, list->head->data_len);
++ mcc_memcpy((void*)list->head->data, buffer, list->head->data_len);
++
++ /* Dequeue the buffer from the endpoint list */
++ list->head = (MCC_RECEIVE_BUFFER*)MCC_MEM_VIRT_TO_PHYS(list->head);
++ buf = mcc_dequeue_buffer(list);
++
++ /* Enqueue the buffer into the free list */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->free_list, sizeof(MCC_RECEIVE_LIST*));
++ mcc_queue_buffer(&bookeeping_data->free_list, buf);
++
++ /* Notify all cores (except of itself) via CPU-to-CPU interrupt that a buffer has been freed */
++ affiliated_signal.type = BUFFER_FREED;
++ affiliated_signal.destination = tmp_destination;
++ for (i=0; i<MCC_NUM_CORES; i++) {
++ if(i != MCC_CORE_NUMBER) {
++ mcc_queue_signal(i, affiliated_signal);
++ }
++ }
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++
++ mcc_generate_cpu_to_cpu_interrupt();
++
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
++
++#if MCC_SEND_RECV_NOCOPY_API_ENABLED
++/*!
++ * \brief This function receives a message from the specified endpoint if one is available. The data is NOT copied into the user-app. buffer.
++ *
++ * This is the "zero-copy receive" version of the MCC receive function. No data is copied.
++ * Only the pointer to the data is returned. This version is fast, but it requires the user to manage
++ * buffer allocation. Specifically, the user must decide when a buffer is no longer in use and
++ * make the appropriate API call to free it, see mcc_free_buffer.
++ *
++ * \param[out] src_endpoint Pointer to the MCC_ENDPOINT structure to be filled by the endpoint identifying the message sender.
++ * \param[in] dest_endpoint Pointer to the local receiving endpoint to receive from.
++ * \param[out] buffer_p Pointer to the MCC buffer of the shared memory where the received data is stored.
++ * \param[out] recv_size Pointer to an MCC_MEM_SIZE that will contain the number of valid bytes in the buffer.
++ * \param[in] timeout_ms Timeout, in milliseconds, to wait for a free buffer. A value of 0 means don't wait (non-blocking call). A value of 0xffffffff means wait forever (blocking call).
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_ENDPOINT (the endpoint does not exist)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_TIMEOUT (timeout exceeded before a new message came)
++ *
++ * \see mcc_send
++ * \see mcc_recv
++ * \see MCC_ENDPOINT
++ */
++int mcc_recv_nocopy(MCC_ENDPOINT *src_endpoint, MCC_ENDPOINT *dest_endpoint, void **buffer_p, MCC_MEM_SIZE *recv_size, unsigned int timeout_ms)
++{
++ MCC_RECEIVE_LIST *list = null;
++ int return_value;
++
++ return_value = mcc_recv_common_part(dest_endpoint, timeout_ms, (MCC_RECEIVE_LIST**)&list);
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void*)list, sizeof(MCC_RECEIVE_LIST*));
++
++ if(list->head == (MCC_RECEIVE_BUFFER*)0) {
++ /* Buffer not dequeued before the timeout */
++ mcc_release_semaphore();
++ return MCC_ERR_TIMEOUT;
++ }
++
++ /* Get the message pointer from the head of the receive buffer list */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&list->head->data, list->head->data_len);
++ *buffer_p = (void*)&list->head->data;
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&list->head->source, sizeof(MCC_ENDPOINT) + sizeof(MCC_MEM_SIZE));
++ mcc_memcpy((void*)&list->head->source, (void*)src_endpoint, sizeof(MCC_ENDPOINT));
++ *recv_size = (MCC_MEM_SIZE)(list->head->data_len);
++
++ /* Dequeue the buffer from the endpoint list */
++ mcc_dequeue_buffer(list);
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
++#endif /* MCC_SEND_RECV_NOCOPY_API_ENABLED */
++
++/*!
++ * \private
++ *
++ * \brief This function is common part for mcc_recv() and mcc_recv_nocopy() function.
++ *
++ * It tries to get the list of buffers kept by the particular endpoint. If the list is empty
++ * it waits for a new message until the timeout expires.
++ *
++ * \param[in] endpoint Pointer to the receiving endpoint to receive from.
++ * \param[in] timeout_ms Timeout, in milliseconds, to wait for a free buffer. A value of 0 means don't wait (non-blocking call). A value of 0xffffffff means wait forever (blocking call).
++ * \param[out] list Pointer to the list of buffers kept by the particular endpoint.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_ENDPOINT (the endpoint does not exist)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ * \return MCC_ERR_TIMEOUT (timeout exceeded before a new message came)
++ *
++ * \see mcc_recv
++ * \see mcc_recv_nocopy
++ * \see MCC_ENDPOINT
++ */
++static int mcc_recv_common_part(MCC_ENDPOINT *endpoint, unsigned int timeout_ms, MCC_RECEIVE_LIST **list)
++{
++ MCC_RECEIVE_LIST *tmp_list;
++ int return_value;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Get list of buffers kept by the particular endpoint */
++ tmp_list = mcc_get_endpoint_list(*endpoint);
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* The endpoint is not valid */
++ if(tmp_list == null) {
++ return MCC_ERR_ENDPOINT;
++ }
++
++ if(tmp_list->head == (MCC_RECEIVE_BUFFER*)0) {
++ /* Non-blocking call */
++ if(timeout_ms == 0) {
++ return MCC_ERR_TIMEOUT;
++ }
++ /* Blocking call */
++ else {
++ /* Wait for the buffer queued event */
++ return_value = mcc_wait_for_buffer_queued(endpoint, timeout_ms);
++ if(MCC_SUCCESS != return_value) {
++ return return_value;
++ }
++ }
++ }
++ else {
++ tmp_list->head = (MCC_RECEIVE_BUFFER*)MCC_MEM_PHYS_TO_VIRT(tmp_list->head);
++ }
++ /* Clear event bit specified for the particular endpoint */
++ mcc_clear_os_sync_for_ep(endpoint);
++
++ *list = (MCC_RECEIVE_LIST*)tmp_list;
++ return MCC_SUCCESS;
++}
++
++/*!
++ * \brief This function returns the number of buffers currently queued at the endpoint.
++ *
++ * The function checks if messages are available on a receive endpoint. While the call only checks the
++ * availability of messages, it does not dequeue them.
++ *
++ * \param[in] endpoint Pointer to the endpoint structure.
++ * \param[out] num_msgs Pointer to an unsigned int that will contain the number of buffers queued.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_ENDPOINT (the endpoint does not exist)
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ *
++ * \see mcc_recv
++ * \see mcc_recv_nocopy
++ * \see MCC_ENDPOINT
++ */
++int mcc_msgs_available(MCC_ENDPOINT *endpoint, unsigned int *num_msgs)
++{
++ unsigned int count = 0;
++ MCC_RECEIVE_LIST *list;
++ MCC_RECEIVE_BUFFER * buf;
++ int return_value;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Get list of buffers kept by the particular endpoint */
++ list = mcc_get_endpoint_list(*endpoint);
++ if(list == null) {
++ /* The endpoint does not exists (has not been registered so far), return immediately - error */
++ mcc_release_semaphore();
++ return MCC_ERR_ENDPOINT;
++ }
++
++ buf = list->head;
++ while(buf != (MCC_RECEIVE_BUFFER*)0) {
++ count++;
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&buf->next, sizeof(MCC_RECEIVE_BUFFER*));
++ buf = (MCC_RECEIVE_BUFFER*)buf->next;
++ }
++ *num_msgs = count;
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
++
++/*!
++ * \private
++ *
++ * \brief This function frees a buffer previously returned by mcc_recv_nocopy().
++ *
++ * Once the zero-copy mechanism of receiving data is used, this function
++ * has to be called to free a buffer and to make it available for the next data
++ * transfer.
++ *
++ * \param[in] buffer Pointer to the buffer to be freed.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ *
++ * \see mcc_recv_nocopy
++ */
++static int mcc_free_buffer_internal(void *buffer)
++{
++ MCC_SIGNAL affiliated_signal;
++ MCC_ENDPOINT tmp_destination = {(MCC_CORE)0, (MCC_NODE)0, (MCC_PORT)0};
++ int return_value, i = 0;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ /* Enqueue the buffer into the free list */
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->free_list, sizeof(MCC_RECEIVE_LIST*));
++ mcc_queue_buffer(&bookeeping_data->free_list, (MCC_RECEIVE_BUFFER *)((unsigned int)buffer - (unsigned int)(&(((MCC_RECEIVE_BUFFER*)0)->data))));
++
++ /* Notify all cores (except of itself) via CPU-to-CPU interrupt that a buffer has been freed */
++ affiliated_signal.type = BUFFER_FREED;
++ affiliated_signal.destination = tmp_destination;
++ for (i=0; i<MCC_NUM_CORES; i++) {
++ if(i != MCC_CORE_NUMBER) {
++ mcc_queue_signal(i, affiliated_signal);
++ }
++ }
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++
++ mcc_generate_cpu_to_cpu_interrupt();
++
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
++#if MCC_SEND_RECV_NOCOPY_API_ENABLED
++/*!
++ * \brief This function frees a buffer previously returned by mcc_recv_nocopy().
++ *
++ * Once the zero-copy mechanism of receiving data is used, this function
++ * has to be called to free a buffer and to make it available for the next data
++ * transfer.
++ *
++ * \param[in] buffer Pointer to the buffer to be freed.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ *
++ * \see mcc_recv_nocopy
++ */
++int mcc_free_buffer(void *buffer)
++{
++ return mcc_free_buffer_internal(buffer);
++}
++#endif /* MCC_SEND_RECV_NOCOPY_API_ENABLED */
++
++/*!
++ * \brief This function returns information about the MCC sub system.
++ *
++ * The function returns implementation-specific information.
++ *
++ * \param[in] node Node number.
++ * \param[out] info_data Pointer to the MCC_INFO_STRUCT structure to hold returned data.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SEMAPHORE (semaphore handling error)
++ *
++ * \see MCC_INFO_STRUCT
++ */
++int mcc_get_info(MCC_NODE node, MCC_INFO_STRUCT* info_data)
++{
++ int return_value;
++
++ /* Semaphore-protected section start */
++ return_value = mcc_get_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ mcc_memcpy(bookeeping_data->version_string, (void*)info_data->version_string, (unsigned int)sizeof(bookeeping_data->version_string));
++
++ /* Semaphore-protected section end */
++ return_value = mcc_release_semaphore();
++ if(return_value != MCC_SUCCESS)
++ return return_value;
++
++ return return_value;
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mcc_common.c linux-3.14.72/arch/arm/mach-imx/mcc_common.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mcc_common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mcc_common.c 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,262 @@
++/*
++ * This file contains MCC library common functions
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#include "mcc_config.h"
++#if (MCC_OS_USED == MCC_MQX)
++#include "mcc_common.h"
++#include "mcc_mqx.h"
++#elif (MCC_OS_USED == MCC_LINUX)
++#include <linux/mcc_api.h>
++#include <linux/mcc_linux.h>
++#endif
++
++
++/*!
++ * \brief This function registers an endpoint.
++ *
++ * Register an endpoint with specified structure / params (core, node and port).
++ *
++ * \param[in] endpoint Pointer to the endpoint structure.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_NOMEM (maximum number of endpoints exceeded)
++ * \return MCC_ERR_ENDPOINT (invalid value for port or endpoint already registered)
++ */
++int mcc_register_endpoint(MCC_ENDPOINT endpoint)
++{
++ int i;
++
++ /* must be valid */
++ if(endpoint.port == MCC_RESERVED_PORT_NUMBER)
++ return MCC_ERR_ENDPOINT;
++
++ /* check not already registered */
++ if(mcc_get_endpoint_list(endpoint))
++ return MCC_ERR_ENDPOINT;
++
++ MCC_DCACHE_INVALIDATE_MLINES(&bookeeping_data->endpoint_table[0], MCC_ATTR_MAX_RECEIVE_ENDPOINTS * sizeof(MCC_ENDPOINT_MAP_ITEM));
++ for(i = 0; i < MCC_ATTR_MAX_RECEIVE_ENDPOINTS; i++) {
++ if(bookeeping_data->endpoint_table[i].endpoint.port == MCC_RESERVED_PORT_NUMBER) {
++ bookeeping_data->endpoint_table[i].endpoint.core = endpoint.core;
++ bookeeping_data->endpoint_table[i].endpoint.node = endpoint.node;
++ bookeeping_data->endpoint_table[i].endpoint.port = endpoint.port;
++ MCC_DCACHE_FLUSH_MLINES(&bookeeping_data->endpoint_table[i], sizeof(MCC_ENDPOINT_MAP_ITEM));
++ return MCC_SUCCESS;
++ }
++ }
++ return MCC_ERR_NOMEM;
++}
++
++/*!
++ * \brief This function removes an endpoint.
++ *
++ * Removes an endpoint with specified structure / params (core, node and port).
++ *
++ * \param[in] endpoint Pointer to the endpoint structure.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_ENDPOINT (invalid value for port or the endpoint doesn't exist)
++ */
++int mcc_remove_endpoint(MCC_ENDPOINT endpoint)
++{
++ int i=0;
++
++ /* must be valid */
++ if(endpoint.port == MCC_RESERVED_PORT_NUMBER)
++ return MCC_ERR_ENDPOINT;
++
++ MCC_DCACHE_INVALIDATE_MLINES(&bookeeping_data->endpoint_table[0], MCC_ATTR_MAX_RECEIVE_ENDPOINTS * sizeof(MCC_ENDPOINT_MAP_ITEM));
++ for(i = 0; i < MCC_ATTR_MAX_RECEIVE_ENDPOINTS; i++) {
++
++ if(MCC_ENDPOINTS_EQUAL(bookeeping_data->endpoint_table[i].endpoint, endpoint)) {
++ /* clear the queue */
++ MCC_RECEIVE_BUFFER * buffer = mcc_dequeue_buffer((MCC_RECEIVE_LIST *)&bookeeping_data->endpoint_table[i].list);
++ while(buffer) {
++ mcc_queue_buffer(&bookeeping_data->free_list, buffer);
++ buffer = mcc_dequeue_buffer((MCC_RECEIVE_LIST *)&bookeeping_data->endpoint_table[i].list);
++ }
++ /* indicate free */
++ bookeeping_data->endpoint_table[i].endpoint.port = MCC_RESERVED_PORT_NUMBER;
++ MCC_DCACHE_FLUSH_MLINES((void*)&bookeeping_data->endpoint_table[i].endpoint.port, sizeof(MCC_PORT));
++ return MCC_SUCCESS;
++ }
++ }
++ return MCC_ERR_ENDPOINT;
++}
++
++/*!
++ * \brief This function dequeues the buffer.
++ *
++ * Dequeues the buffer from the list.
++ *
++ * \param[in] list Pointer to the MCC_RECEIVE_LIST structure.
++ *
++ * \return Pointer to MCC_RECEIVE_BUFFER
++ */
++MCC_RECEIVE_BUFFER * mcc_dequeue_buffer(MCC_RECEIVE_LIST *list)
++{
++ MCC_RECEIVE_BUFFER * next_buf, * next_buf_virt;
++ MCC_DCACHE_INVALIDATE_MLINES((void*)list, sizeof(MCC_RECEIVE_LIST));
++
++ next_buf = list->head;
++
++ next_buf_virt = (MCC_RECEIVE_BUFFER *)MCC_MEM_PHYS_TO_VIRT(next_buf);
++ if(next_buf) {
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&next_buf_virt->next, sizeof(MCC_RECEIVE_BUFFER*));
++ list->head = next_buf_virt->next;
++ if(list->tail == next_buf)
++ list->tail = null;
++ }
++ MCC_DCACHE_FLUSH_MLINES(list, sizeof(MCC_RECEIVE_LIST));
++ return next_buf_virt;
++}
++
++/*!
++ * \brief This function queues the buffer.
++ *
++ * Queues the buffer in the list.
++ *
++ * \param[in] list Pointer to the MCC_RECEIVE_LIST structure.
++ * \param[in] r_buffer Pointer to MCC_RECEIVE_BUFFER.
++ *
++ * \return none
++ */
++void mcc_queue_buffer(MCC_RECEIVE_LIST *list, MCC_RECEIVE_BUFFER * r_buffer)
++{
++ MCC_RECEIVE_BUFFER * last_buf;
++ MCC_RECEIVE_BUFFER * r_buffer_phys;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void*)list, sizeof(MCC_RECEIVE_LIST));
++
++ last_buf = (MCC_RECEIVE_BUFFER *)MCC_MEM_PHYS_TO_VIRT(list->tail);
++ r_buffer_phys = (MCC_RECEIVE_BUFFER *)MCC_MEM_VIRT_TO_PHYS(r_buffer);
++ if(last_buf) {
++ last_buf->next = r_buffer_phys;
++ MCC_DCACHE_FLUSH_MLINES((void*)&last_buf->next, sizeof(MCC_RECEIVE_BUFFER*));
++ }
++ else {
++ list->head = r_buffer_phys;
++ }
++ r_buffer->next = null;
++ list->tail = r_buffer_phys;
++ MCC_DCACHE_FLUSH_MLINES(list, sizeof(MCC_RECEIVE_LIST));
++ MCC_DCACHE_FLUSH_MLINES((void*)&r_buffer->next, sizeof(MCC_RECEIVE_BUFFER*));
++}
++
++/*!
++ * \brief This function returns the endpoint list.
++ *
++ * Returns the MCC_RECEIVE_LIST respective to the endpoint structure provided.
++ *
++ * \param[in] endpoint Pointer to the MCC_ENDPOINT structure.
++ *
++ * \return MCC_RECEIVE_LIST pointer
++ * \return null pointer
++ */
++MCC_RECEIVE_LIST * mcc_get_endpoint_list(MCC_ENDPOINT endpoint)
++{
++ int i=0;
++
++ /* must be valid */
++ if(endpoint.port == MCC_RESERVED_PORT_NUMBER)
++ return null;
++
++ MCC_DCACHE_INVALIDATE_MLINES(&bookeeping_data->endpoint_table[0], MCC_ATTR_MAX_RECEIVE_ENDPOINTS * sizeof(MCC_ENDPOINT_MAP_ITEM));
++ for(i = 0; i<MCC_ATTR_MAX_RECEIVE_ENDPOINTS; i++) {
++
++ if(MCC_ENDPOINTS_EQUAL(bookeeping_data->endpoint_table[i].endpoint, endpoint)) {
++ return (MCC_RECEIVE_LIST *)&bookeeping_data->endpoint_table[i].list;
++ }
++ }
++ return null;
++}
++
++/*!
++ * \brief This function queues a signal
++ *
++ * Signal circular queue rules:
++ * tail points to next free slot
++ * head points to first occupied slot
++ * head == tail indicates empty
++ * (tail + 1) % len = fill
++ * This method costs 1 slot since you need to differentiate
++ * between full and empty (if you fill the last slot it looks
++ * like empty since h == t)
++ *
++ * \param[in] core Core number.
++ * \param[in] signal Signal to be queued.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SQ_FULL (signal queue is full - no more that MCC_MAX_OUTSTANDING_SIGNALS items allowed)
++ */
++int mcc_queue_signal(MCC_CORE core, MCC_SIGNAL signal)
++{
++ int tail, new_tail;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->signal_queue_head[core], sizeof(unsigned int));
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->signal_queue_tail[core], sizeof(unsigned int));
++ tail = bookeeping_data->signal_queue_tail[core];
++ new_tail = tail == (MCC_MAX_OUTSTANDING_SIGNALS-1) ? 0 : tail+1;
++
++ if(MCC_SIGNAL_QUEUE_FULL(core))
++ return MCC_ERR_SQ_FULL;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->signals_received[core][tail], sizeof(MCC_SIGNAL));
++ bookeeping_data->signals_received[core][tail].type = signal.type;
++ bookeeping_data->signals_received[core][tail].destination.core = signal.destination.core;
++ bookeeping_data->signals_received[core][tail].destination.node = signal.destination.node;
++ bookeeping_data->signals_received[core][tail].destination.port = signal.destination.port;
++
++ bookeeping_data->signal_queue_tail[core] = new_tail;
++ MCC_DCACHE_FLUSH_MLINES((void*)&bookeeping_data->signal_queue_tail[core], sizeof(unsigned int));
++ MCC_DCACHE_FLUSH_MLINES((void*)&bookeeping_data->signals_received[core][tail], sizeof(MCC_SIGNAL));
++
++ return MCC_SUCCESS;
++}
++
++/*!
++ * \brief This function dequeues a signal
++ *
++ * It dequeues a signal from the signal queue for the particular core.
++ *
++ * \param[in] core Core number.
++ * \param[in] signal Signal to be dequeued.
++ *
++ * \return MCC_SUCCESS
++ * \return MCC_ERR_SQ_EMPTY (signal queue is empty, nothing to dequeue)
++ */
++int mcc_dequeue_signal(MCC_CORE core, MCC_SIGNAL *signal)
++{
++ int head;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->signal_queue_head[core], sizeof(unsigned int));
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->signal_queue_tail[core], sizeof(unsigned int));
++ head = bookeeping_data->signal_queue_head[core];
++
++ if(MCC_SIGNAL_QUEUE_EMPTY(core))
++ return MCC_ERR_SQ_EMPTY;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void*)&bookeeping_data->signals_received[core][head], sizeof(MCC_SIGNAL));
++ signal->type = bookeeping_data->signals_received[core][head].type;
++ signal->destination.core = bookeeping_data->signals_received[core][head].destination.core;
++ signal->destination.node = bookeeping_data->signals_received[core][head].destination.node;
++ signal->destination.port = bookeeping_data->signals_received[core][head].destination.port;
++
++ bookeeping_data->signal_queue_head[core] = head == (MCC_MAX_OUTSTANDING_SIGNALS-1) ? 0 : head+1;
++ MCC_DCACHE_FLUSH_MLINES((void*)&bookeeping_data->signal_queue_head[core], sizeof(unsigned int));
++
++ return MCC_SUCCESS;
++}
++
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mcc_config.h linux-3.14.72/arch/arm/mach-imx/mcc_config.h
+--- linux-3.14.72.orig/arch/arm/mach-imx/mcc_config.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mcc_config.h 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,25 @@
++/*
++ * This is the main MCC configuration file
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#ifndef __MCC_CONFIG__
++#define __MCC_CONFIG__
++
++#include <linux/mcc_config_linux.h>
++#include <linux/mcc_common.h>
++
++/* used OS */
++#define MCC_OS_USED (MCC_LINUX)
++
++#endif /* __MCC_CONFIG__ */
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mcc_imx6sx.c linux-3.14.72/arch/arm/mach-imx/mcc_imx6sx.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mcc_imx6sx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mcc_imx6sx.c 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,35 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#include <linux/mcc_config_linux.h>
++#include <linux/mcc_common.h>
++#include <linux/mcc_linux.h>
++
++/*!
++ * \brief This function returns the core number
++ *
++ * \return int
++ */
++unsigned int _psp_core_num(void)
++{
++ return 0;
++}
++
++/*!
++ * \brief This function returns the node number
++ *
++ * \return unsigned int
++ */
++unsigned int _psp_node_num(void)
++{
++ return MCC_LINUX_NODE_NUMBER;
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mcc_linux.c linux-3.14.72/arch/arm/mach-imx/mcc_linux.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mcc_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mcc_linux.c 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,200 @@
++/*
++ * This file contains Linux-specific MCC library functions
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#include <linux/io.h>
++#include <linux/string.h>
++#include <linux/wait.h>
++#include <linux/imx_sema4.h>
++#include "mcc_config.h"
++#include <linux/mcc_imx6sx.h>
++
++/* Global variables */
++static unsigned long mcc_shm_offset;
++
++MCC_BOOKEEPING_STRUCT *bookeeping_data;
++
++/*!
++ * \brief This function initializes the hw semaphore (SEMA4).
++ *
++ * Calls core-mutex driver to create a core mutex.
++ *
++ * \param[in] sem_num SEMA4 gate number.
++ */
++int mcc_init_semaphore(unsigned int sem_num)
++{
++ /* Create a core mutex */
++ mcc_shm_ptr = imx_sema4_mutex_create(0, sem_num);
++
++ if (NULL == mcc_shm_ptr)
++ return MCC_ERR_SEMAPHORE;
++ else
++ return MCC_SUCCESS;
++}
++
++/*!
++ * \brief This function de-initializes the hw semaphore (SEMA4).
++ *
++ * Calls core-mutex driver to destroy a core mutex.
++ *
++ * \param[in] sem_num SEMA4 gate number.
++ */
++int mcc_deinit_semaphore(unsigned int sem_num)
++{
++ /* Destroy the core mutex */
++ if (0 == imx_sema4_mutex_destroy(mcc_shm_ptr))
++ return MCC_SUCCESS;
++ else
++ return MCC_ERR_SEMAPHORE;
++}
++
++/*!
++ * \brief This function locks the specified core mutex.
++ *
++ * Calls core-mutex driver to lock the core mutex.
++ *
++ */
++int mcc_get_semaphore(void)
++{
++ if (imx_mcc_bsp_int_disable()) {
++ pr_err("ERR:failed to disable mcc int.\n");
++ return MCC_ERR_SEMAPHORE;
++ }
++
++ if (0 == imx_sema4_mutex_lock(mcc_shm_ptr)) {
++ return MCC_SUCCESS;
++ } else {
++ if (imx_mcc_bsp_int_enable()) {
++ pr_err("ERR:failed to enable mcc int.\n");
++ return MCC_ERR_INT;
++ }
++ return MCC_ERR_SEMAPHORE;
++ }
++}
++
++/*!
++ * \brief This function unlocks the specified core mutex.
++ *
++ * Calls core-mutex driver to unlock the core mutex.
++ *
++ */
++int mcc_release_semaphore(void)
++{
++ if (0 == imx_sema4_mutex_unlock(mcc_shm_ptr)) {
++ /*
++ * Enable the cpu-to-cpu isr just in case imx_semae_mutex_unlock
++ * function has not woke up another task waiting for the core
++ * mutex.
++ */
++ if (mcc_shm_ptr->gate_val != (MCC_CORE_NUMBER + 1))
++ imx_mcc_bsp_int_enable();
++ return MCC_SUCCESS;
++ }
++
++ return MCC_ERR_SEMAPHORE;
++}
++
++/*!
++ * \brief This function registers the CPU-to-CPU interrupt.
++ *
++ * Calls interrupt component functions to install and enable the
++ * CPU-to-CPU interrupt.
++ *
++ */
++int mcc_register_cpu_to_cpu_isr(void)
++{
++ /*
++ * CPU to CPU ISR had been registered in MU driver.
++ * return success directly.
++ */
++ return MCC_SUCCESS;
++}
++
++/*!
++ * \brief This function triggers an interrupt to other core(s).
++ *
++ */
++int mcc_generate_cpu_to_cpu_interrupt(void)
++{
++ int ret;
++
++ /*
++ * Assert directed CPU interrupts for all processors except
++ * the requesting core
++ */
++ ret = mcc_triger_cpu_to_cpu_interrupt();
++
++ if (ret == 0)
++ return MCC_SUCCESS;
++ else
++ return ret;
++}
++
++/*!
++ * \brief This function copies data.
++ *
++ * Copies the number of single-addressable units from the source address
++ * to destination address.
++ *
++ * \param[in] src Source address.
++ * \param[in] dest Destination address.
++ * \param[in] size Number of single-addressable units to copy.
++ */
++void mcc_memcpy(void *src, void *dest, unsigned int size)
++{
++ memcpy(dest, src, size);
++}
++
++void *mcc_virt_to_phys(void *x)
++{
++ if (null == x)
++ return NULL;
++ else
++ return (void *)((unsigned long) (x) - mcc_shm_offset);
++}
++
++void *mcc_phys_to_virt(void *x)
++{
++ if (null == x)
++ return NULL;
++ else
++ return (void *)((unsigned long) (x) + mcc_shm_offset);
++}
++
++int mcc_init_os_sync(void)
++{
++ /* No used in linux */
++ return MCC_SUCCESS;
++}
++
++int mcc_deinit_os_sync(void)
++{
++ /* No used in linux */
++ return MCC_SUCCESS;
++}
++
++void mcc_clear_os_sync_for_ep(MCC_ENDPOINT *endpoint)
++{
++ /* No used in linux */
++}
++
++MCC_BOOKEEPING_STRUCT *mcc_get_bookeeping_data(void)
++{
++ bookeeping_data = (MCC_BOOKEEPING_STRUCT *)ioremap_nocache
++ (MCC_BASE_ADDRESS, sizeof(struct mcc_bookeeping_struct));
++ mcc_shm_offset = (unsigned long)bookeeping_data
++ - (unsigned long)MCC_BASE_ADDRESS;
++
++ return bookeeping_data;
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mmdc.c linux-3.14.72/arch/arm/mach-imx/mmdc.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mmdc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/mmdc.c 2016-06-19 22:11:55.053156547 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -21,6 +21,12 @@
+ #define BP_MMDC_MAPSR_PSD 0
+ #define BP_MMDC_MAPSR_PSS 4
+
++#define MMDC_MDMISC 0x18
++#define BM_MMDC_MDMISC_DDR_TYPE 0x18
++#define BP_MMDC_MDMISC_DDR_TYPE 0x3
++
++static int ddr_type;
++
+ static int imx_mmdc_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+@@ -31,6 +37,13 @@
+ mmdc_base = of_iomap(np, 0);
+ WARN_ON(!mmdc_base);
+
++ reg = mmdc_base + MMDC_MDMISC;
++ /* Get ddr type */
++ val = readl_relaxed(reg);
++ val &= BM_MMDC_MDMISC_DDR_TYPE;
++ val >>= BP_MMDC_MDMISC_DDR_TYPE;
++ ddr_type = val;
++
+ reg = mmdc_base + MMDC_MAPSR;
+
+ /* Enable automatic power saving */
+@@ -51,6 +64,11 @@
+ return 0;
+ }
+
++int imx_mmdc_get_ddr_type(void)
++{
++ return ddr_type;
++}
++
+ static struct of_device_id imx_mmdc_dt_ids[] = {
+ { .compatible = "fsl,imx6q-mmdc", },
+ { /* sentinel */ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mu.c linux-3.14.72/arch/arm/mach-imx/mu.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/mu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mu.c 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,475 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/busfreq-imx6.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/platform_device.h>
++#include "common.h"
++#include "hardware.h"
++#include "mcc_config.h"
++#include <linux/imx_sema4.h>
++#include <linux/mcc_imx6sx.h>
++#include <linux/mcc_linux.h>
++
++#define MU_ATR0_OFFSET 0x0
++#define MU_ARR0_OFFSET 0x10
++#define MU_ASR 0x20
++#define MU_ACR 0x24
++
++#define MU_LPM_HANDSHAKE_INDEX 0
++#define MU_LPM_BUS_HIGH_READY_FOR_M4 0xFFFF6666
++#define MU_LPM_M4_FREQ_CHANGE_READY 0xFFFF7777
++#define MU_LPM_M4_REQUEST_HIGH_BUS 0x2222CCCC
++#define MU_LPM_M4_RELEASE_HIGH_BUS 0x2222BBBB
++#define MU_LPM_M4_WAKEUP_SRC_VAL 0x55555000
++#define MU_LPM_M4_WAKEUP_SRC_MASK 0xFFFFF000
++#define MU_LPM_M4_WAKEUP_IRQ_MASK 0xFF0
++#define MU_LPM_M4_WAKEUP_IRQ_SHIFT 0x4
++#define MU_LPM_M4_WAKEUP_ENABLE_MASK 0xF
++#define MU_LPM_M4_WAKEUP_ENABLE_SHIFT 0x0
++
++static void __iomem *mu_base;
++static u32 m4_message;
++static struct delayed_work mu_work;
++static u32 m4_wake_irqs[4];
++static bool m4_freq_low;
++
++struct imx_sema4_mutex *mcc_shm_ptr;
++unsigned int imx_mcc_buffer_freed = 0, imx_mcc_buffer_queued = 0;
++/* Used for blocking send */
++static DECLARE_WAIT_QUEUE_HEAD(buffer_freed_wait_queue);
++/* Used for blocking recv */
++static DECLARE_WAIT_QUEUE_HEAD(buffer_queued_wait_queue);
++
++bool imx_mu_is_m4_in_low_freq(void)
++{
++ return m4_freq_low;
++}
++
++void imx_mu_enable_m4_irqs_in_gic(bool enable)
++{
++ int i, j;
++
++ for (i = 0; i < 4; i++) {
++ if (m4_wake_irqs[i] == 0)
++ continue;
++ for (j = 0; j < 32; j++) {
++ if (m4_wake_irqs[i] & (1 << j)) {
++ if (enable)
++ enable_irq((i + 1) * 32 + j);
++ else
++ disable_irq((i + 1) * 32 + j);
++ }
++ }
++ }
++}
++
++static irqreturn_t mcc_m4_dummy_isr(int irq, void *param)
++{
++ return IRQ_HANDLED;
++}
++
++static void imx_mu_send_message(unsigned int index, unsigned int data)
++{
++ u32 val;
++ unsigned long timeout = jiffies + msecs_to_jiffies(500);
++
++ /* wait for transfer buffer empty */
++ do {
++ val = readl_relaxed(mu_base + MU_ASR);
++ if (time_after(jiffies, timeout)) {
++ pr_err("Waiting MU transmit buffer empty timeout!\n");
++ break;
++ }
++ } while ((val & (1 << (20 + index))) == 0);
++
++ writel_relaxed(data, mu_base + index * 0x4 + MU_ATR0_OFFSET);
++}
++
++static void mu_work_handler(struct work_struct *work)
++{
++ int ret;
++ u32 irq, enable, idx, mask;
++
++ pr_debug("receive M4 message 0x%x\n", m4_message);
++
++ switch (m4_message) {
++ case MU_LPM_M4_REQUEST_HIGH_BUS:
++ request_bus_freq(BUS_FREQ_HIGH);
++ imx6sx_set_m4_highfreq(true);
++ imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX,
++ MU_LPM_BUS_HIGH_READY_FOR_M4);
++ m4_freq_low = false;
++ break;
++ case MU_LPM_M4_RELEASE_HIGH_BUS:
++ release_bus_freq(BUS_FREQ_HIGH);
++ imx6sx_set_m4_highfreq(false);
++ imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX,
++ MU_LPM_M4_FREQ_CHANGE_READY);
++ m4_freq_low = true;
++ break;
++ default:
++ if ((m4_message & MU_LPM_M4_WAKEUP_SRC_MASK) ==
++ MU_LPM_M4_WAKEUP_SRC_VAL) {
++ irq = (m4_message & MU_LPM_M4_WAKEUP_IRQ_MASK) >>
++ MU_LPM_M4_WAKEUP_IRQ_SHIFT;
++
++ enable = (m4_message & MU_LPM_M4_WAKEUP_ENABLE_MASK) >>
++ MU_LPM_M4_WAKEUP_ENABLE_SHIFT;
++
++ idx = irq / 32 - 1;
++ mask = 1 << irq % 32;
++
++ if (enable && can_request_irq(irq, 0)) {
++ ret = request_irq(irq, mcc_m4_dummy_isr,
++ IRQF_NO_SUSPEND, "imx-m4-dummy", NULL);
++ if (ret) {
++ pr_err("%s: register interrupt %d failed, rc %d\n",
++ __func__, irq, ret);
++ break;
++ }
++ disable_irq(irq);
++ m4_wake_irqs[idx] = m4_wake_irqs[idx] | mask;
++ }
++ imx_gpc_add_m4_wake_up_irq(irq, enable);
++ }
++ break;
++ }
++ m4_message = 0;
++ /* enable RIE3 interrupt */
++ writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(27),
++ mu_base + MU_ACR);
++}
++
++/*!
++ * \brief This function clears the CPU-to-CPU int flag for the particular core.
++ *
++ * Implementation is platform-specific.
++ */
++void mcc_clear_cpu_to_cpu_interrupt(void)
++{
++ u32 val;
++
++ val = readl_relaxed(mu_base + MU_ASR);
++ /* write 1 to BIT31 to clear the bit31(GIP3) of MU_ASR */
++ val = val | (1 << 31);
++ writel_relaxed(val, mu_base + MU_ASR);
++}
++
++/*!
++ * \brief This function triggers the CPU-to-CPU interrupt.
++ *
++ * Platform-specific software triggering the inter-CPU interrupts.
++ */
++int mcc_triger_cpu_to_cpu_interrupt(void)
++{
++ int i = 0;
++ u32 val;
++
++ val = readl_relaxed(mu_base + MU_ACR);
++
++ if ((val & BIT(19)) != 0) {
++ do {
++ val = readl_relaxed(mu_base + MU_ACR);
++ msleep(1);
++ } while (((val & BIT(19)) > 0) && (i++ < 100));
++ }
++
++ if ((val & BIT(19)) == 0) {
++ /* Enable the bit19(GIR3) of MU_ACR */
++ val = readl_relaxed(mu_base + MU_ACR);
++ val |= BIT(19);
++ writel_relaxed(val, mu_base + MU_ACR);
++ return 0;
++ } else {
++ pr_info("mcc int still be triggered after %d ms polling!\n", i);
++ return -EIO;
++ }
++}
++
++/*!
++ * \brief This function disable the CPU-to-CPU interrupt.
++ *
++ * Platform-specific software disable the inter-CPU interrupts.
++ */
++int imx_mcc_bsp_int_disable(void)
++{
++ u32 val;
++
++ /* Disablethe bit31(GIE3) and bit19(GIR3) of MU_ACR */
++ val = readl_relaxed(mu_base + MU_ACR);
++ val &= ~(BIT(31) | BIT(27));
++ writel_relaxed(val, mu_base + MU_ACR);
++
++ /* flush */
++ val = readl_relaxed(mu_base + MU_ACR);
++ return 0;
++}
++
++/*!
++ * \brief This function enable the CPU-to-CPU interrupt.
++ *
++ * Platform-specific software enable the inter-CPU interrupts.
++ */
++int imx_mcc_bsp_int_enable(void)
++{
++ u32 val;
++
++ /* Enable bit31(GIE3) and bit19(GIR3) of MU_ACR */
++ val = readl_relaxed(mu_base + MU_ACR);
++ val |= (BIT(31) | BIT(27));
++ writel_relaxed(val, mu_base + MU_ACR);
++
++ /* flush */
++ val = readl_relaxed(mu_base + MU_ACR);
++ return 0;
++}
++
++int mcc_wait_for_buffer_freed(MCC_RECEIVE_BUFFER **buffer, unsigned int timeout)
++{
++ int return_value;
++ unsigned long timeout_j; /* jiffies */
++ MCC_RECEIVE_BUFFER *buf = null;
++
++ /*
++ * Blocking calls: CPU-to-CPU ISR sets the event and thus
++ * resumes tasks waiting for a free MCC buffer.
++ * As the interrupt request is send to all cores when a buffer
++ * is freed it could happen that several tasks from different
++ * cores/nodes are waiting for a free buffer and all of them
++ * are notified that the buffer has been freed. This function
++ * has to check (after the wake up) that a buffer is really
++ * available and has not been already grabbed by another
++ * "competitor task" that has been faster. If so, it has to
++ * wait again for the next notification.
++ */
++ while (buf == null) {
++ if (timeout == 0xffffffff) {
++ /*
++ * In order to level up the robust, do not always
++ * wait event here. Wake up itself after every 1~s.
++ */
++ timeout_j = usecs_to_jiffies(1000);
++ wait_event_timeout(buffer_freed_wait_queue,
++ imx_mcc_buffer_freed == 1, timeout_j);
++ } else {
++ timeout_j = msecs_to_jiffies(timeout);
++ wait_event_timeout(buffer_freed_wait_queue,
++ imx_mcc_buffer_freed == 1, timeout_j);
++ }
++
++ return_value = mcc_get_semaphore();
++ if (return_value != MCC_SUCCESS)
++ return return_value;
++
++ MCC_DCACHE_INVALIDATE_MLINES((void *)
++ &bookeeping_data->free_list,
++ sizeof(MCC_RECEIVE_LIST *));
++
++ buf = mcc_dequeue_buffer(&bookeeping_data->free_list);
++ mcc_release_semaphore();
++ if (imx_mcc_buffer_freed)
++ imx_mcc_buffer_freed = 0;
++ }
++
++ *buffer = buf;
++ return MCC_SUCCESS;
++}
++
++int mcc_wait_for_buffer_queued(MCC_ENDPOINT *endpoint, unsigned int timeout)
++{
++ unsigned long timeout_j; /* jiffies */
++ MCC_RECEIVE_LIST *tmp_list;
++
++ /* Get list of buffers kept by the particular endpoint */
++ tmp_list = mcc_get_endpoint_list(*endpoint);
++
++ if (timeout == 0xffffffff) {
++ wait_event(buffer_queued_wait_queue,
++ imx_mcc_buffer_queued == 1);
++ mcc_get_semaphore();
++ /*
++ * double check if the tmp_list head is still null
++ * or not, if yes, wait again.
++ */
++ while (tmp_list->head == null) {
++ imx_mcc_buffer_queued = 0;
++ mcc_release_semaphore();
++ wait_event(buffer_queued_wait_queue,
++ imx_mcc_buffer_queued == 1);
++ mcc_get_semaphore();
++ }
++ } else {
++ timeout_j = msecs_to_jiffies(timeout);
++ wait_event_timeout(buffer_queued_wait_queue,
++ imx_mcc_buffer_queued == 1, timeout_j);
++ mcc_get_semaphore();
++ }
++
++ if (imx_mcc_buffer_queued)
++ imx_mcc_buffer_queued = 0;
++
++ if (tmp_list->head == null) {
++ pr_err("%s can't get queued buffer.\n", __func__);
++ mcc_release_semaphore();
++ return MCC_ERR_TIMEOUT;
++ }
++
++ tmp_list->head = (MCC_RECEIVE_BUFFER *)
++ MCC_MEM_PHYS_TO_VIRT(tmp_list->head);
++ mcc_release_semaphore();
++
++ return MCC_SUCCESS;
++}
++
++static irqreturn_t imx_mu_isr(int irq, void *param)
++{
++ u32 irqs;
++
++ irqs = readl_relaxed(mu_base + MU_ASR);
++
++ if (irqs & (1 << 27)) {
++ /* get message from receive buffer */
++ m4_message = readl_relaxed(mu_base + MU_ARR0_OFFSET);
++ /* disable RIE3 interrupt */
++ writel_relaxed(readl_relaxed(mu_base + MU_ACR) & (~BIT(27)),
++ mu_base + MU_ACR);
++ schedule_delayed_work(&mu_work, 0);
++ }
++
++ /*
++ * MCC CPU-to-CPU interrupt.
++ * Each core can interrupt the other. There are two logical signals:
++ * - Receive data available for (Node,Port)
++ * - signaled when a buffer is queued to a Receive Data Queue.
++ * - Buffer available
++ * - signaled when a buffer is queued to the Free Buffer Queue.
++ * It is possible that several signals can occur while one interrupt
++ * is being processed.
++ * Therefore, a Receive Signal Queue of received signals is also
++ * required
++ * - one for each core.
++ * The interrupting core queues to the tail and the interrupted core
++ * pulls from the head.
++ * For a circular file, no semaphore is required since only the sender
++ * modifies the tail and only the receiver modifies the head.
++ */
++ if (irqs & (1 << 31)) {
++ /*
++ * Try to lock the core mutex. If successfully locked, perform
++ * mcc_dequeue_signal(), release the gate and finally clear the
++ * interrupt flag. If trylock fails (HW semaphore already locked
++ * by another core), do not clear the interrupt flag – this
++ * way the CPU-to-CPU isr is re-issued again until the HW
++ * semaphore is locked. Higher priority ISRs will be serviced
++ * while issued at the time we are waiting for the unlocked
++ * gate. To prevent trylog failure due to core mutex currently
++ * locked by our own core(a task), the cpu-to-cpu isr is
++ * temporarily disabled when mcc_get_semaphore() is called and
++ * re-enabled again when mcc_release_semaphore() is issued.
++ */
++ MCC_SIGNAL serviced_signal;
++ if (SEMA4_A9_LOCK == imx_sema4_mutex_trylock(mcc_shm_ptr)) {
++ while (MCC_SUCCESS == mcc_dequeue_signal(
++ MCC_CORE_NUMBER, &serviced_signal)) {
++ if ((serviced_signal.type == BUFFER_QUEUED) &&
++ (serviced_signal.destination.core ==
++ MCC_CORE_NUMBER)) {
++ /*
++ * Unblock receiver, in case of
++ * asynchronous communication
++ */
++ imx_mcc_buffer_queued = 1;
++ wake_up(&buffer_queued_wait_queue);
++ } else if (serviced_signal.type ==
++ BUFFER_FREED) {
++ /*
++ * Unblock sender, in case of
++ * asynchronous communication
++ */
++ imx_mcc_buffer_freed = 1;
++ wake_up(&buffer_freed_wait_queue);
++ }
++ }
++
++ /* Clear the interrupt flag */
++ mcc_clear_cpu_to_cpu_interrupt();
++
++ /* Unlocks the core mutex */
++ imx_sema4_mutex_unlock(mcc_shm_ptr);
++ }
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int imx_mu_probe(struct platform_device *pdev)
++{
++ int ret;
++ u32 irq;
++ struct device_node *np;
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-mu");
++ mu_base = of_iomap(np, 0);
++ WARN_ON(!mu_base);
++
++ irq = platform_get_irq(pdev, 0);
++
++ ret = request_irq(irq, imx_mu_isr,
++ IRQF_EARLY_RESUME, "imx-mu", NULL);
++ if (ret) {
++ pr_err("%s: register interrupt %d failed, rc %d\n",
++ __func__, irq, ret);
++ return ret;
++ }
++ INIT_DELAYED_WORK(&mu_work, mu_work_handler);
++
++ /* enable the bit27(RIE3) of MU_ACR */
++ writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(27),
++ mu_base + MU_ACR);
++ /* enable the bit31(GIE3) of MU_ACR, used for MCC */
++ writel_relaxed(readl_relaxed(mu_base + MU_ACR) | BIT(31),
++ mu_base + MU_ACR);
++
++ /* MU always as a wakeup source for low power mode */
++ imx_gpc_add_m4_wake_up_irq(irq, true);
++
++ pr_info("MU is ready for cross core communication!\n");
++
++ return 0;
++}
++
++static const struct of_device_id imx_mu_ids[] = {
++ { .compatible = "fsl,imx6sx-mu" },
++ { }
++};
++
++static struct platform_driver imx_mu_driver = {
++ .driver = {
++ .name = "imx-mu",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_mu_ids,
++ },
++ .probe = imx_mu_probe,
++};
++
++static int __init imx6_mu_init(void)
++{
++ return platform_driver_register(&imx_mu_driver);
++}
++subsys_initcall(imx6_mu_init);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mx6.h linux-3.14.72/arch/arm/mach-imx/mx6.h
+--- linux-3.14.72.orig/arch/arm/mach-imx/mx6.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/mx6.h 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,51 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * * This program is free software; you can redistribute it and/or modify
++ * * it under the terms of the GNU General Public License version 2 as
++ * * published by the Free Software Foundation.
++ * */
++
++#ifndef __ASM_ARCH_MXC_IOMAP_H__
++#define __ASM_ARCH_MXC_IOMAP_H__
++
++#define MX6Q_IO_P2V(x) IMX_IO_P2V(x)
++#define MX6Q_IO_ADDRESS(x) IOMEM(MX6Q_IO_P2V(x))
++
++#define MX6Q_L2_BASE_ADDR 0x00a02000
++#define MX6Q_L2_SIZE 0x1000
++#define MX6Q_IOMUXC_BASE_ADDR 0x020e0000
++#define MX6Q_IOMUXC_SIZE 0x4000
++#define MX6Q_SRC_BASE_ADDR 0x020d8000
++#define MX6Q_SRC_SIZE 0x4000
++#define MX6Q_CCM_BASE_ADDR 0x020c4000
++#define MX6Q_CCM_SIZE 0x4000
++#define MX6Q_ANATOP_BASE_ADDR 0x020c8000
++#define MX6Q_ANATOP_SIZE 0x1000
++#define MX6Q_GPC_BASE_ADDR 0x020dc000
++#define MX6Q_GPC_SIZE 0x4000
++#define MX6Q_SEMA4_BASE_ADDR 0x02290000
++#define MX6Q_SEMA4_SIZE 0x4000
++#define MX6Q_MMDC_P0_BASE_ADDR 0x021b0000
++#define MX6Q_MMDC_P0_SIZE 0x4000
++#define MX6Q_MMDC_P1_BASE_ADDR 0x021b4000
++#define MX6Q_MMDC_P1_SIZE 0x4000
++#define MX6Q_AIPS1_BASE_ADDR 0x02000000
++#define MX6Q_AIPS1_SIZE 0x100000
++#define MX6Q_AIPS2_BASE_ADDR 0x02100000
++#define MX6Q_AIPS2_SIZE 0x100000
++#define MX6Q_AIPS3_BASE_ADDR 0x02200000
++#define MX6Q_AIPS3_SIZE 0x100000
++
++#define MX6SX_IRAM_TLB_BASE_ADDR 0x008f8000
++#define MX6Q_IRAM_TLB_BASE_ADDR 0x00900000
++#define MX6Q_IRAM_TLB_SIZE 0x4000
++#define TT_ATTRIB_NON_CACHEABLE_1M 0x802
++#define MX6_SUSPEND_IRAM_DATA_SIZE 256
++#define MX6SL_WFI_IRAM_DATA_SIZE 100
++
++#define MX6_SUSPEND_IRAM_ADDR_OFFSET 0
++#define MX6_CPUIDLE_IRAM_ADDR_OFFSET 0x1000
++#endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/mxc.h linux-3.14.72/arch/arm/mach-imx/mxc.h
+--- linux-3.14.72.orig/arch/arm/mach-imx/mxc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/mxc.h 2016-06-19 22:11:55.053156547 +0200
+@@ -36,12 +36,15 @@
+ #define MXC_CPU_MX53 53
+ #define MXC_CPU_IMX6SL 0x60
+ #define MXC_CPU_IMX6DL 0x61
++#define MXC_CPU_IMX6SX 0x62
+ #define MXC_CPU_IMX6Q 0x63
+
+ #define IMX_CHIP_REVISION_1_0 0x10
+ #define IMX_CHIP_REVISION_1_1 0x11
+ #define IMX_CHIP_REVISION_1_2 0x12
+ #define IMX_CHIP_REVISION_1_3 0x13
++#define IMX_CHIP_REVISION_1_4 0x14
++#define IMX_CHIP_REVISION_1_5 0x15
+ #define IMX_CHIP_REVISION_2_0 0x20
+ #define IMX_CHIP_REVISION_2_1 0x21
+ #define IMX_CHIP_REVISION_2_2 0x22
+@@ -52,6 +55,8 @@
+ #define IMX_CHIP_REVISION_3_3 0x33
+ #define IMX_CHIP_REVISION_UNKNOWN 0xff
+
++#define IMX_DDR_TYPE_LPDDR2 1
++
+ #ifndef __ASSEMBLY__
+ extern unsigned int __mxc_cpu_type;
+ #endif
+@@ -153,16 +158,25 @@
+ #endif
+
+ #ifndef __ASSEMBLY__
++#ifdef CONFIG_SOC_IMX6SL
+ static inline bool cpu_is_imx6sl(void)
+ {
+ return __mxc_cpu_type == MXC_CPU_IMX6SL;
+ }
++#else
++# define cpu_is_imx6sl() (0)
++#endif
+
+ static inline bool cpu_is_imx6dl(void)
+ {
+ return __mxc_cpu_type == MXC_CPU_IMX6DL;
+ }
+
++static inline bool cpu_is_imx6sx(void)
++{
++ return __mxc_cpu_type == MXC_CPU_IMX6SX;
++}
++
+ static inline bool cpu_is_imx6q(void)
+ {
+ return __mxc_cpu_type == MXC_CPU_IMX6Q;
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/platsmp.c linux-3.14.72/arch/arm/mach-imx/platsmp.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/platsmp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/platsmp.c 2016-06-19 22:11:55.053156547 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -23,7 +23,7 @@
+ #define SCU_STANDBY_ENABLE (1 << 5)
+
+ u32 g_diag_reg;
+-static void __iomem *scu_base;
++void __iomem *imx_scu_base;
+
+ static struct map_desc scu_io_desc __initdata = {
+ /* .virtual and .pfn are run-time assigned */
+@@ -42,18 +42,18 @@
+ scu_io_desc.pfn = __phys_to_pfn(base);
+ iotable_init(&scu_io_desc, 1);
+
+- scu_base = IMX_IO_ADDRESS(base);
++ imx_scu_base = IMX_IO_ADDRESS(base);
+ }
+
+ void imx_scu_standby_enable(void)
+ {
+- u32 val = readl_relaxed(scu_base);
++ u32 val = readl_relaxed(imx_scu_base);
+
+ val |= SCU_STANDBY_ENABLE;
+- writel_relaxed(val, scu_base);
++ writel_relaxed(val, imx_scu_base);
+ }
+
+-static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
++static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
+ {
+ imx_set_cpu_jump(cpu, v7_secondary_startup);
+ imx_enable_cpu(cpu, true);
+@@ -66,17 +66,27 @@
+ */
+ static void __init imx_smp_init_cpus(void)
+ {
+- int i, ncores;
++ int i, ncores = scu_get_core_count(imx_scu_base);
++ u32 me = smp_processor_id();
+
+- ncores = scu_get_core_count(scu_base);
++ if (setup_max_cpus < ncores)
++ ncores = (setup_max_cpus) ? setup_max_cpus : 1;
+
+ for (i = ncores; i < NR_CPUS; i++)
+ set_cpu_possible(i, false);
++
++ /* Set the SCU CPU Power status for each inactive core. */
++ for (i = 0; i < NR_CPUS; i++) {
++ if (i != me)
++ __raw_writeb(SCU_PM_POWEROFF, imx_scu_base + 0x08 + i);
++ }
+ }
+
+ void imx_smp_prepare(void)
+ {
+- scu_enable(scu_base);
++ scu_enable(imx_scu_base);
++ /* Need to enable SCU standby for entering WAIT mode */
++ imx_scu_standby_enable();
+ }
+
+ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
+@@ -92,7 +102,8 @@
+ * secondary cores when booting them.
+ */
+ asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
+- sync_cache_w(&g_diag_reg);
++ __cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg));
++ outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1));
+ }
+
+ struct smp_operations imx_smp_ops __initdata = {
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/pm-imx6.c linux-3.14.72/arch/arm/mach-imx/pm-imx6.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/pm-imx6.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/pm-imx6.c 2016-06-19 22:11:55.053156547 +0200
+@@ -0,0 +1,1129 @@
++/*
++ * Copyright 2011-2014 Freescale Semiconductor, Inc.
++ * Copyright 2011 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/of_fdt.h>
++#include <linux/of_irq.h>
++#include <linux/suspend.h>
++#include <linux/genalloc.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_fdt.h>
++#include <linux/of_platform.h>
++#include <linux/regmap.h>
++#include <linux/suspend.h>
++#include <asm/cacheflush.h>
++#include <asm/fncpy.h>
++#include <asm/mach/map.h>
++#include <asm/proc-fns.h>
++#include <asm/suspend.h>
++#include <asm/tlb.h>
++
++#include "common.h"
++#include "hardware.h"
++
++#define CCR 0x0
++#define BM_CCR_WB_COUNT (0x7 << 16)
++#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
++#define BM_CCR_RBC_EN (0x1 << 27)
++
++#define CLPCR 0x54
++#define BP_CLPCR_LPM 0
++#define BM_CLPCR_LPM (0x3 << 0)
++#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
++#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
++#define BM_CLPCR_SBYOS (0x1 << 6)
++#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
++#define BM_CLPCR_VSTBY (0x1 << 8)
++#define BP_CLPCR_STBY_COUNT 9
++#define BM_CLPCR_STBY_COUNT (0x3 << 9)
++#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
++#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
++#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
++#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
++#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
++#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
++#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
++#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
++#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
++#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
++#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
++
++#define CGPR 0x64
++#define BM_CGPR_INT_MEM_CLK_LPM (0x1 << 17)
++#define CCGR4 0x78
++#define CCGR6 0x80
++
++#define MX6Q_SUSPEND_OCRAM_SIZE 0x1000
++#define MX6_MAX_MMDC_IO_NUM 33
++#define MX6_MAX_MMDC_NUM 34
++
++#define ROMC_ROMPATCH0D 0xf0
++#define ROMC_ROMPATCHCNTL 0xf4
++#define ROMC_ROMPATCHENL 0xfc
++#define ROMC_ROMPATCH0A 0x100
++#define BM_ROMPATCHCNTL_0D (0x1 << 0)
++#define BM_ROMPATCHCNTL_DIS (0x1 << 29)
++#define BM_ROMPATCHENL_0D (0x1 << 0)
++#define ROM_ADDR_FOR_INTERNAL_RAM_BASE 0x10d7c
++
++#define UART_UCR1 0x80
++#define UART_UCR2 0x84
++#define UART_UCR3 0x88
++#define UART_UCR4 0x8c
++#define UART_UFCR 0x90
++#define UART_UESC 0x9c
++#define UART_UTIM 0xa0
++#define UART_UBIR 0xa4
++#define UART_UBMR 0xa8
++#define UART_UBRC 0xac
++#define UART_UTS 0xb4
++
++/* QSPI register layout */
++#define QSPI_MCR 0x00
++#define QSPI_IPCR 0x08
++#define QSPI_BUF0CR 0x10
++#define QSPI_BUF1CR 0x14
++#define QSPI_BUF2CR 0x18
++#define QSPI_BUF3CR 0x1c
++#define QSPI_BFGENCR 0x20
++#define QSPI_BUF0IND 0x30
++#define QSPI_BUF1IND 0x34
++#define QSPI_BUF2IND 0x38
++#define QSPI_SFAR 0x100
++#define QSPI_SMPR 0x108
++#define QSPI_RBSR 0x10c
++#define QSPI_RBCT 0x110
++#define QSPI_TBSR 0x150
++#define QSPI_TBDR 0x154
++#define QSPI_SFA1AD 0x180
++#define QSPI_SFA2AD 0x184
++#define QSPI_SFB1AD 0x188
++#define QSPI_SFB2AD 0x18c
++#define QSPI_RBDR_BASE 0x200
++#define QSPI_LUTKEY 0x300
++#define QSPI_LCKCR 0x304
++#define QSPI_LUT_BASE 0x310
++
++#define QSPI_RBDR_(x) (QSPI_RBDR_BASE + (x) * 4)
++#define QSPI_LUT(x) (QSPI_LUT_BASE + (x) * 4)
++
++#define QSPI_LUTKEY_VALUE 0x5AF05AF0
++#define QSPI_LCKER_LOCK 0x1
++#define QSPI_LCKER_UNLOCK 0x2
++
++enum qspi_regs_valuetype {
++ QSPI_PREDEFINED,
++ QSPI_RETRIEVED,
++};
++
++struct qspi_regs {
++ int offset;
++ unsigned int value;
++ enum qspi_regs_valuetype valuetype;
++};
++
++struct qspi_regs qspi_regs_imx6sx[] = {
++ {QSPI_IPCR, 0, QSPI_RETRIEVED},
++ {QSPI_BUF0CR, 0, QSPI_RETRIEVED},
++ {QSPI_BUF1CR, 0, QSPI_RETRIEVED},
++ {QSPI_BUF2CR, 0, QSPI_RETRIEVED},
++ {QSPI_BUF3CR, 0, QSPI_RETRIEVED},
++ {QSPI_BFGENCR, 0, QSPI_RETRIEVED},
++ {QSPI_BUF0IND, 0, QSPI_RETRIEVED},
++ {QSPI_BUF1IND, 0, QSPI_RETRIEVED},
++ {QSPI_BUF2IND, 0, QSPI_RETRIEVED},
++ {QSPI_SFAR, 0, QSPI_RETRIEVED},
++ {QSPI_SMPR, 0, QSPI_RETRIEVED},
++ {QSPI_RBSR, 0, QSPI_RETRIEVED},
++ {QSPI_RBCT, 0, QSPI_RETRIEVED},
++ {QSPI_TBSR, 0, QSPI_RETRIEVED},
++ {QSPI_TBDR, 0, QSPI_RETRIEVED},
++ {QSPI_SFA1AD, 0, QSPI_RETRIEVED},
++ {QSPI_SFA2AD, 0, QSPI_RETRIEVED},
++ {QSPI_SFB1AD, 0, QSPI_RETRIEVED},
++ {QSPI_SFB2AD, 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(0), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(1), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(2), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(3), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(4), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(5), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(6), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(7), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(8), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(9), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(10), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(11), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(12), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(13), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(14), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(15), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(16), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(17), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(18), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(19), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(20), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(21), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(22), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(23), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(24), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(25), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(26), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(27), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(28), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(29), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(30), 0, QSPI_RETRIEVED},
++ {QSPI_RBDR_(31), 0, QSPI_RETRIEVED},
++ {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED},
++ {QSPI_LCKCR, QSPI_LCKER_UNLOCK, QSPI_PREDEFINED},
++ {QSPI_LUT(0), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(1), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(2), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(3), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(4), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(5), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(6), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(7), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(8), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(9), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(10), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(11), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(12), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(13), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(14), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(15), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(16), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(17), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(18), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(19), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(20), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(21), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(22), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(23), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(24), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(25), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(26), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(27), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(28), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(29), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(30), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(31), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(32), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(33), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(34), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(35), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(36), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(37), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(38), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(39), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(40), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(41), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(42), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(43), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(44), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(45), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(46), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(47), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(48), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(49), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(50), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(51), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(52), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(53), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(54), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(55), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(56), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(57), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(58), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(59), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(60), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(61), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(62), 0, QSPI_RETRIEVED},
++ {QSPI_LUT(63), 0, QSPI_RETRIEVED},
++ {QSPI_LUTKEY, QSPI_LUTKEY_VALUE, QSPI_PREDEFINED},
++ {QSPI_LCKCR, QSPI_LCKER_LOCK, QSPI_PREDEFINED},
++ {QSPI_MCR, 0, QSPI_RETRIEVED},
++};
++
++unsigned long iram_tlb_base_addr;
++unsigned long iram_tlb_phys_addr;
++
++static unsigned int *ocram_saved_in_ddr;
++static void __iomem *ocram_base;
++static void __iomem *console_base;
++static void __iomem *qspi_base;
++static unsigned int ocram_size;
++static void __iomem *ccm_base;
++static void __iomem *suspend_ocram_base;
++static void (*imx6_suspend_in_ocram_fn)(void __iomem *ocram_vbase);
++struct regmap *romcp;
++/*
++ * suspend ocram space layout:
++ * ======================== high address ======================
++ * .
++ * .
++ * .
++ * ^
++ * ^
++ * ^
++ * imx6_suspend code
++ * PM_INFO structure(imx6_cpu_pm_info)
++ * ======================== low address =======================
++ */
++
++struct imx6_pm_base {
++ phys_addr_t pbase;
++ void __iomem *vbase;
++};
++
++struct imx6_pm_socdata {
++ u32 ddr_type;
++ const char *mmdc_compat;
++ const char *src_compat;
++ const char *iomuxc_compat;
++ const char *gpc_compat;
++ const u32 mmdc_io_num;
++ const u32 *mmdc_io_offset;
++ const u32 mmdc_num;
++ const u32 *mmdc_offset;
++};
++
++static const u32 imx6q_mmdc_io_offset[] __initconst = {
++ 0x5ac, 0x5b4, 0x528, 0x520, /* DQM0 ~ DQM3 */
++ 0x514, 0x510, 0x5bc, 0x5c4, /* DQM4 ~ DQM7 */
++ 0x56c, 0x578, 0x588, 0x594, /* CAS, RAS, SDCLK_0, SDCLK_1 */
++ 0x5a8, 0x5b0, 0x524, 0x51c, /* SDQS0 ~ SDQS3 */
++ 0x518, 0x50c, 0x5b8, 0x5c0, /* SDQS4 ~ SDQS7 */
++ 0x784, 0x788, 0x794, 0x79c, /* GPR_B0DS ~ GPR_B3DS */
++ 0x7a0, 0x7a4, 0x7a8, 0x748, /* GPR_B4DS ~ GPR_B7DS */
++ 0x59c, 0x5a0, 0x750, 0x774, /* SODT0, SODT1, MODE_CTL, MODE */
++ 0x74c, /* GPR_ADDS */
++};
++
++static const u32 imx6dl_mmdc_io_offset[] __initconst = {
++ 0x470, 0x474, 0x478, 0x47c, /* DQM0 ~ DQM3 */
++ 0x480, 0x484, 0x488, 0x48c, /* DQM4 ~ DQM7 */
++ 0x464, 0x490, 0x4ac, 0x4b0, /* CAS, RAS, SDCLK_0, SDCLK_1 */
++ 0x4bc, 0x4c0, 0x4c4, 0x4c8, /* DRAM_SDQS0 ~ DRAM_SDQS3 */
++ 0x4cc, 0x4d0, 0x4d4, 0x4d8, /* DRAM_SDQS4 ~ DRAM_SDQS7 */
++ 0x764, 0x770, 0x778, 0x77c, /* GPR_B0DS ~ GPR_B3DS */
++ 0x780, 0x784, 0x78c, 0x748, /* GPR_B4DS ~ GPR_B7DS */
++ 0x4b4, 0x4b8, 0x750, 0x760, /* SODT0, SODT1, MODE_CTL, MODE */
++ 0x74c, /* GPR_ADDS */
++};
++
++static const u32 imx6sl_mmdc_io_offset[] __initconst = {
++ 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */
++ 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */
++ 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */
++ 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */
++ 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */
++};
++
++static const u32 imx6sx_mmdc_io_offset[] __initconst = {
++ 0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
++ 0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
++ 0x300, 0x2fc, 0x32c, 0x5f4, /* CAS, RAS, SDCLK_0, GPR_ADDS */
++ 0x310, 0x314, 0x5f8, 0x608, /* SODT0, SODT1, MODE_CTL, MODE */
++ 0x330, 0x334, 0x338, 0x33c, /* SDQS0 ~ SDQS3 */
++};
++
++static const u32 imx6sx_mmdc_offset[] __initconst = {
++ 0x800, 0x80c, 0x810, 0x83c,
++ 0x840, 0x848, 0x850, 0x81c,
++ 0x820, 0x824, 0x828, 0x8b8,
++ 0x004, 0x008, 0x00c, 0x010,
++ 0x014, 0x018, 0x01c, 0x02c,
++ 0x030, 0x040, 0x000, 0x01c,
++ 0x020, 0x818, 0x01c,
++};
++
++static const struct imx6_pm_socdata imx6q_pm_data __initconst = {
++ .mmdc_compat = "fsl,imx6q-mmdc",
++ .src_compat = "fsl,imx6q-src",
++ .iomuxc_compat = "fsl,imx6q-iomuxc",
++ .gpc_compat = "fsl,imx6q-gpc",
++ .mmdc_io_num = ARRAY_SIZE(imx6q_mmdc_io_offset),
++ .mmdc_io_offset = imx6q_mmdc_io_offset,
++ .mmdc_num = 0,
++ .mmdc_offset = NULL,
++};
++
++static const struct imx6_pm_socdata imx6dl_pm_data __initconst = {
++ .mmdc_compat = "fsl,imx6q-mmdc",
++ .src_compat = "fsl,imx6q-src",
++ .iomuxc_compat = "fsl,imx6dl-iomuxc",
++ .gpc_compat = "fsl,imx6q-gpc",
++ .mmdc_io_num = ARRAY_SIZE(imx6dl_mmdc_io_offset),
++ .mmdc_io_offset = imx6dl_mmdc_io_offset,
++ .mmdc_num = 0,
++ .mmdc_offset = NULL,
++};
++
++static const struct imx6_pm_socdata imx6sl_pm_data __initconst = {
++ .mmdc_compat = "fsl,imx6sl-mmdc",
++ .src_compat = "fsl,imx6sl-src",
++ .iomuxc_compat = "fsl,imx6sl-iomuxc",
++ .gpc_compat = "fsl,imx6sl-gpc",
++ .mmdc_io_num = ARRAY_SIZE(imx6sl_mmdc_io_offset),
++ .mmdc_io_offset = imx6sl_mmdc_io_offset,
++ .mmdc_num = 0,
++ .mmdc_offset = NULL,
++};
++
++static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
++ .mmdc_compat = "fsl,imx6sx-mmdc",
++ .src_compat = "fsl,imx6sx-src",
++ .iomuxc_compat = "fsl,imx6sx-iomuxc",
++ .gpc_compat = "fsl,imx6sx-gpc",
++ .mmdc_io_num = ARRAY_SIZE(imx6sx_mmdc_io_offset),
++ .mmdc_io_offset = imx6sx_mmdc_io_offset,
++ .mmdc_num = ARRAY_SIZE(imx6sx_mmdc_offset),
++ .mmdc_offset = imx6sx_mmdc_offset,
++};
++
++/*
++ * This structure is for passing necessary data for low level ocram
++ * suspend code(arch/arm/mach-imx/suspend-imx6.S), if this struct
++ * definition is changed, the offset definition in
++ * arch/arm/mach-imx/suspend-imx6.S must be also changed accordingly,
++ * otherwise, the suspend to ocram function will be broken!
++ */
++struct imx6_cpu_pm_info {
++ phys_addr_t pbase; /* The physical address of pm_info. */
++ phys_addr_t resume_addr; /* The physical resume address for asm code */
++ u32 ddr_type;
++ u32 pm_info_size; /* Size of pm_info. */
++ struct imx6_pm_base mmdc_base;
++ struct imx6_pm_base src_base;
++ struct imx6_pm_base iomuxc_base;
++ struct imx6_pm_base ccm_base;
++ struct imx6_pm_base gpc_base;
++ struct imx6_pm_base l2_base;
++ struct imx6_pm_base anatop_base;
++ u32 ttbr1; /* Store TTBR1 */
++ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */
++ u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
++ u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */
++ u32 mmdc_val[MX6_MAX_MMDC_NUM][2]; /* To save offset and value */
++} __aligned(8);
++
++unsigned long save_ttbr1(void)
++{
++ unsigned long lttbr1;
++ asm volatile(
++ ".align 4\n"
++ "mrc p15, 0, %0, c2, c0, 1\n"
++ : "=r" (lttbr1)
++ );
++ return lttbr1;
++}
++
++void restore_ttbr1(unsigned long ttbr1)
++{
++ asm volatile(
++ ".align 4\n"
++ "mcr p15, 0, %0, c2, c0, 1\n"
++ : : "r" (ttbr1)
++ );
++}
++
++void imx6q_set_int_mem_clk_lpm(bool enable)
++{
++ if ((cpu_is_imx6q() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_1) ||
++ (cpu_is_imx6dl() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_0) || cpu_is_imx6sx()) {
++ u32 val;
++
++ val = readl_relaxed(ccm_base + CGPR);
++ if (enable)
++ val |= BM_CGPR_INT_MEM_CLK_LPM;
++ else
++ val &= ~BM_CGPR_INT_MEM_CLK_LPM;
++ writel_relaxed(val, ccm_base + CGPR);
++ }
++}
++
++void imx6q_enable_rbc(bool enable)
++{
++ u32 val;
++
++ /*
++ * need to mask all interrupts in GPC before
++ * operating RBC configurations
++ */
++ imx_gpc_mask_all();
++
++ /* configure RBC enable bit */
++ val = readl_relaxed(ccm_base + CCR);
++ val &= ~BM_CCR_RBC_EN;
++ val |= enable ? BM_CCR_RBC_EN : 0;
++ writel_relaxed(val, ccm_base + CCR);
++
++ /* configure RBC count */
++ val = readl_relaxed(ccm_base + CCR);
++ val &= ~BM_CCR_RBC_BYPASS_COUNT;
++ val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
++ writel(val, ccm_base + CCR);
++
++ /*
++ * need to delay at least 2 cycles of CKIL(32K)
++ * due to hardware design requirement, which is
++ * ~61us, here we use 65us for safe
++ */
++ udelay(65);
++
++ /* restore GPC interrupt mask settings */
++ imx_gpc_restore_all();
++}
++
++static void imx6q_enable_wb(bool enable)
++{
++ u32 val;
++
++ /* configure well bias enable bit */
++ val = readl_relaxed(ccm_base + CLPCR);
++ val &= ~BM_CLPCR_WB_PER_AT_LPM;
++ val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
++ writel_relaxed(val, ccm_base + CLPCR);
++
++ /* configure well bias count */
++ val = readl_relaxed(ccm_base + CCR);
++ val &= ~BM_CCR_WB_COUNT;
++ val |= enable ? BM_CCR_WB_COUNT : 0;
++ writel_relaxed(val, ccm_base + CCR);
++}
++
++int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
++{
++ struct irq_desc *iomuxc_irq_desc;
++ u32 val = readl_relaxed(ccm_base + CLPCR);
++
++ val &= ~BM_CLPCR_LPM;
++ switch (mode) {
++ case WAIT_CLOCKED:
++ break;
++ case WAIT_UNCLOCKED:
++ val |= 0x1 << BP_CLPCR_LPM;
++ val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
++ break;
++ case STOP_POWER_ON:
++ val |= 0x2 << BP_CLPCR_LPM;
++ val &= ~BM_CLPCR_VSTBY;
++ val &= ~BM_CLPCR_SBYOS;
++ if (cpu_is_imx6sl())
++ val |= BM_CLPCR_BYPASS_PMIC_READY;
++ if (cpu_is_imx6sl() || cpu_is_imx6sx())
++ val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
++ else
++ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
++ break;
++ case WAIT_UNCLOCKED_POWER_OFF:
++ val |= 0x1 << BP_CLPCR_LPM;
++ val &= ~BM_CLPCR_VSTBY;
++ val &= ~BM_CLPCR_SBYOS;
++ break;
++ case STOP_POWER_OFF:
++ val |= 0x2 << BP_CLPCR_LPM;
++ val |= 0x3 << BP_CLPCR_STBY_COUNT;
++ val |= BM_CLPCR_VSTBY;
++ val |= BM_CLPCR_SBYOS;
++ if (cpu_is_imx6sl())
++ val |= BM_CLPCR_BYPASS_PMIC_READY;
++ if (cpu_is_imx6sl() || cpu_is_imx6sx())
++ val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
++ else
++ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /*
++ * ERR007265: CCM: When improper low-power sequence is used,
++ * the SoC enters low power mode before the ARM core executes WFI.
++ *
++ * Software workaround:
++ * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
++ * by setting IOMUX_GPR1_GINT.
++ * 2) Software should then unmask IRQ #32 in GPC before setting CCM
++ * Low-Power mode.
++ * 3) Software should mask IRQ #32 right after CCM Low-Power mode
++ * is set (set bits 0-1 of CCM_CLPCR).
++ */
++ iomuxc_irq_desc = irq_to_desc(32);
++ imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
++ writel_relaxed(val, ccm_base + CLPCR);
++ imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
++
++ return 0;
++}
++
++static int imx6q_suspend_finish(unsigned long val)
++{
++ if (!imx6_suspend_in_ocram_fn) {
++ cpu_do_idle();
++ } else {
++ /*
++ * call low level suspend function in ocram,
++ * as we need to float DDR IO.
++ */
++ local_flush_tlb_all();
++ imx6_suspend_in_ocram_fn(suspend_ocram_base);
++ }
++
++ return 0;
++}
++
++static void imx6_console_save(unsigned int *regs)
++{
++ if (!console_base)
++ return;
++
++ regs[0] = readl_relaxed(console_base + UART_UCR1);
++ regs[1] = readl_relaxed(console_base + UART_UCR2);
++ regs[2] = readl_relaxed(console_base + UART_UCR3);
++ regs[3] = readl_relaxed(console_base + UART_UCR4);
++ regs[4] = readl_relaxed(console_base + UART_UFCR);
++ regs[5] = readl_relaxed(console_base + UART_UESC);
++ regs[6] = readl_relaxed(console_base + UART_UTIM);
++ regs[7] = readl_relaxed(console_base + UART_UBIR);
++ regs[8] = readl_relaxed(console_base + UART_UBMR);
++ regs[9] = readl_relaxed(console_base + UART_UBRC);
++ regs[10] = readl_relaxed(console_base + UART_UTS);
++}
++
++static void imx6_console_restore(unsigned int *regs)
++{
++ if (!console_base)
++ return;
++
++ writel_relaxed(regs[4], console_base + UART_UFCR);
++ writel_relaxed(regs[5], console_base + UART_UESC);
++ writel_relaxed(regs[6], console_base + UART_UTIM);
++ writel_relaxed(regs[7], console_base + UART_UBIR);
++ writel_relaxed(regs[8], console_base + UART_UBMR);
++ writel_relaxed(regs[9], console_base + UART_UBRC);
++ writel_relaxed(regs[10], console_base + UART_UTS);
++ writel_relaxed(regs[0], console_base + UART_UCR1);
++ writel_relaxed(regs[1] | 0x1, console_base + UART_UCR2);
++ writel_relaxed(regs[2], console_base + UART_UCR3);
++ writel_relaxed(regs[3], console_base + UART_UCR4);
++}
++
++static void imx6_qspi_save(struct qspi_regs *pregs, int reg_num)
++{
++ int i;
++
++ if (!qspi_base)
++ return;
++
++ for (i = 0; i < reg_num; i++) {
++ if (QSPI_RETRIEVED == pregs[i].valuetype)
++ pregs[i].value = readl_relaxed(qspi_base +
++ pregs[i].offset);
++ }
++}
++
++static void imx6_qspi_restore(struct qspi_regs *pregs, int reg_num)
++{
++ int i;
++
++ if (!qspi_base)
++ return;
++
++ for (i = 0; i < reg_num; i++)
++ writel_relaxed(pregs[i].value, qspi_base + pregs[i].offset);
++}
++
++static int imx6q_pm_enter(suspend_state_t state)
++{
++ unsigned int console_saved_reg[11] = {0};
++ static unsigned int ccm_ccgr4, ccm_ccgr6;
++
++#ifdef CONFIG_SOC_IMX6SX
++ if (imx_src_is_m4_enabled()) {
++ if (imx_gpc_is_m4_sleeping() && imx_mu_is_m4_in_low_freq()) {
++ imx_gpc_hold_m4_in_sleep();
++ imx_mu_enable_m4_irqs_in_gic(true);
++ } else {
++ pr_info("M4 is busy, enter WAIT mode instead of STOP!\n");
++ imx6q_set_lpm(WAIT_UNCLOCKED);
++ imx6q_set_int_mem_clk_lpm(true);
++ imx_gpc_pre_suspend(false);
++ /* Zzz ... */
++ cpu_do_idle();
++ imx_gpc_post_resume();
++ imx6q_set_lpm(WAIT_CLOCKED);
++
++ return 0;
++ }
++ }
++#endif
++
++ if (!iram_tlb_base_addr) {
++ pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \
++ code. Please ensure device tree has an entry for \
++ fsl,lpm-sram.\n");
++ return -EINVAL;
++ }
++
++ switch (state) {
++ case PM_SUSPEND_STANDBY:
++ imx6q_set_lpm(STOP_POWER_ON);
++ imx6q_set_int_mem_clk_lpm(true);
++ imx_gpc_pre_suspend(false);
++ if (cpu_is_imx6sl())
++ imx6sl_set_wait_clk(true);
++ /* Zzz ... */
++ cpu_do_idle();
++ if (cpu_is_imx6sl())
++ imx6sl_set_wait_clk(false);
++ imx_gpc_post_resume();
++ imx6q_set_lpm(WAIT_CLOCKED);
++ break;
++ case PM_SUSPEND_MEM:
++ imx6q_set_lpm(STOP_POWER_OFF);
++ imx6q_set_int_mem_clk_lpm(false);
++ imx6q_enable_wb(true);
++ /*
++ * For suspend into ocram, asm code already take care of
++ * RBC setting, so we do NOT need to do that here.
++ */
++ if (!imx6_suspend_in_ocram_fn)
++ imx6q_enable_rbc(true);
++ imx_gpc_pre_suspend(true);
++ imx_anatop_pre_suspend();
++ imx_set_cpu_jump(0, v7_cpu_resume);
++ if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) {
++ ccm_ccgr4 = readl_relaxed(ccm_base + CCGR4);
++ ccm_ccgr6 = readl_relaxed(ccm_base + CCGR6);
++ /*
++ * i.MX6SX RDC needs PCIe and eim clk to be enabled
++ * if Mega/Fast off, it is better to check cpu type
++ * and whether Mega/Fast is off in this suspend flow,
++ * but we need to add cpu type check for 3 places which
++ * will increase code size, so here we just do it
++ * for all cases, as when STOP mode is entered, CCM
++ * hardware will gate all clocks, so it will NOT impact
++ * any function or power.
++ */
++ writel_relaxed(ccm_ccgr4 | (0x3 << 0), ccm_base +
++ CCGR4);
++ writel_relaxed(ccm_ccgr6 | (0x3 << 10), ccm_base +
++ CCGR6);
++ memcpy(ocram_saved_in_ddr, ocram_base, ocram_size);
++ imx6_console_save(console_saved_reg);
++ if (imx_src_is_m4_enabled())
++ imx6_qspi_save(qspi_regs_imx6sx,
++ sizeof(qspi_regs_imx6sx) /
++ sizeof(struct qspi_regs));
++ }
++
++ /* Zzz ... */
++ cpu_suspend(0, imx6q_suspend_finish);
++
++ if (cpu_is_imx6sx() && imx_gpc_is_mf_mix_off()) {
++ writel_relaxed(ccm_ccgr4, ccm_base + CCGR4);
++ writel_relaxed(ccm_ccgr6, ccm_base + CCGR6);
++ memcpy(ocram_base, ocram_saved_in_ddr, ocram_size);
++ imx6_console_restore(console_saved_reg);
++ if (imx_src_is_m4_enabled())
++ imx6_qspi_restore(qspi_regs_imx6sx,
++ sizeof(qspi_regs_imx6sx) /
++ sizeof(struct qspi_regs));
++ }
++ if (cpu_is_imx6q() || cpu_is_imx6dl())
++ imx_smp_prepare();
++ imx_anatop_post_resume();
++ imx_gpc_post_resume();
++ imx6q_enable_rbc(false);
++ imx6q_enable_wb(false);
++ imx6q_set_int_mem_clk_lpm(true);
++ imx6q_set_lpm(WAIT_CLOCKED);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++#ifdef CONFIG_SOC_IMX6SX
++ if (imx_src_is_m4_enabled()) {
++ imx_mu_enable_m4_irqs_in_gic(false);
++ imx_gpc_release_m4_in_sleep();
++ }
++#endif
++
++ return 0;
++}
++
++static int imx6q_pm_valid(suspend_state_t state)
++{
++ return (state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM);
++}
++
++static const struct platform_suspend_ops imx6q_pm_ops = {
++ .enter = imx6q_pm_enter,
++ .valid = imx6q_pm_valid,
++};
++
++void __init imx6q_pm_set_ccm_base(void __iomem *base)
++{
++ ccm_base = base;
++}
++
++static struct map_desc iram_tlb_io_desc __initdata = {
++ /* .virtual and .pfn are run-time assigned */
++ .length = SZ_1M,
++ .type = MT_MEMORY_RWX_NONCACHED,
++};
++
++static const char * const low_power_ocram_match[] __initconst = {
++ "fsl,lpm-sram",
++ NULL
++};
++
++static int __init imx6_dt_find_lpsram(unsigned long node, const char *uname,
++ int depth, void *data)
++{
++ unsigned long lpram_addr;
++ __be32 *prop;
++
++ if (of_flat_dt_match(node, low_power_ocram_match)) {
++ prop = of_get_flat_dt_prop(node, "reg", NULL);
++ if (!prop)
++ return -EINVAL;
++
++ lpram_addr = be32_to_cpup(prop);
++
++ /* We need to create a 1M page table entry. */
++ iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000);
++ iram_tlb_io_desc.pfn = __phys_to_pfn(lpram_addr & 0xFFF00000);
++ iram_tlb_phys_addr = lpram_addr;
++ iram_tlb_base_addr = IMX_IO_P2V(lpram_addr);
++
++ iotable_init(&iram_tlb_io_desc, 1);
++ }
++
++ return 0;
++}
++
++/*
++ * AIPS1 and AIPS2 is not used, because it will trigger a BUG_ON if
++ * lowlevel debug and earlyprintk are configured.
++ *
++ * it is because there is a vm conflict because UART1 is mapped early if
++ * AIPS1 is mapped using 1M size.
++ *
++ * Thus no use AIPS1 and AIPS2 to avoid kernel BUG_ON.
++ */
++static struct map_desc imx6_pm_io_desc[] __initdata = {
++ imx_map_entry(MX6Q, MMDC_P0, MT_DEVICE),
++ imx_map_entry(MX6Q, MMDC_P1, MT_DEVICE),
++ imx_map_entry(MX6Q, SRC, MT_DEVICE),
++ imx_map_entry(MX6Q, IOMUXC, MT_DEVICE),
++ imx_map_entry(MX6Q, CCM, MT_DEVICE),
++ imx_map_entry(MX6Q, ANATOP, MT_DEVICE),
++ imx_map_entry(MX6Q, GPC, MT_DEVICE),
++ imx_map_entry(MX6Q, L2, MT_DEVICE),
++ imx_map_entry(MX6Q, SEMA4, MT_DEVICE),
++};
++
++void __init imx6_pm_map_io(void)
++{
++ unsigned long i;
++
++ iotable_init(imx6_pm_io_desc, ARRAY_SIZE(imx6_pm_io_desc));
++
++ /*
++ * Get the address of IRAM or OCRAM to be used by the low
++ * power code from the device tree.
++ */
++ WARN_ON(of_scan_flat_dt(imx6_dt_find_lpsram, NULL));
++
++ /* Return if no IRAM space is allocated for suspend/resume code. */
++ if (!iram_tlb_base_addr) {
++ pr_warn("No IRAM/OCRAM memory allocated for suspend/resume \
++ code. Please ensure device tree has an entry for \
++ fsl,lpm-sram.\n");
++ return;
++ }
++
++ /* Set all entries to 0. */
++ memset((void *)iram_tlb_base_addr, 0, MX6Q_IRAM_TLB_SIZE);
++
++ /*
++ * Make sure the IRAM virtual address has a mapping in the IRAM
++ * page table.
++ *
++ * Only use the top 11 bits [31-20] when storing the physical
++ * address in the page table as only these bits are required
++ * for 1M mapping.
++ */
++ i = ((iram_tlb_base_addr >> 20) << 2) / 4;
++ *((unsigned long *)iram_tlb_base_addr + i) =
++ (iram_tlb_phys_addr & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M;
++
++ /*
++ * Make sure the AIPS1 virtual address has a mapping in the
++ * IRAM page table.
++ */
++ i = ((IMX_IO_P2V(MX6Q_AIPS1_BASE_ADDR) >> 20) << 2) / 4;
++ *((unsigned long *)iram_tlb_base_addr + i) =
++ (MX6Q_AIPS1_BASE_ADDR & 0xFFF00000) |
++ TT_ATTRIB_NON_CACHEABLE_1M;
++
++ /*
++ * Make sure the AIPS2 virtual address has a mapping in the
++ * IRAM page table.
++ */
++ i = ((IMX_IO_P2V(MX6Q_AIPS2_BASE_ADDR) >> 20) << 2) / 4;
++ *((unsigned long *)iram_tlb_base_addr + i) =
++ (MX6Q_AIPS2_BASE_ADDR & 0xFFF00000) |
++ TT_ATTRIB_NON_CACHEABLE_1M;
++
++ /*
++ * Make sure the AIPS3 virtual address has a mapping
++ * in the IRAM page table.
++ */
++ i = ((IMX_IO_P2V(MX6Q_AIPS3_BASE_ADDR) >> 20) << 2) / 4;
++ *((unsigned long *)iram_tlb_base_addr + i) =
++ (MX6Q_AIPS3_BASE_ADDR & 0xFFF00000) |
++ TT_ATTRIB_NON_CACHEABLE_1M;
++
++ /*
++ * Make sure the L2 controller virtual address has a mapping
++ * in the IRAM page table.
++ */
++ i = ((IMX_IO_P2V(MX6Q_L2_BASE_ADDR) >> 20) << 2) / 4;
++ *((unsigned long *)iram_tlb_base_addr + i) =
++ (MX6Q_L2_BASE_ADDR & 0xFFF00000) | TT_ATTRIB_NON_CACHEABLE_1M;
++}
++
++static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
++{
++ struct device_node *node;
++ struct imx6_cpu_pm_info *pm_info;
++ int i, ret = 0;
++ const u32 *mmdc_io_offset_array;
++ const u32 *mmdc_offset_array;
++ unsigned long iram_paddr;
++
++ suspend_set_ops(&imx6q_pm_ops);
++
++ if (!socdata) {
++ pr_warn("%s: invalid argument!\n", __func__);
++ return -EINVAL;
++ }
++
++ /*
++ * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB,
++ * The lower 8K is not used, so use the lower 8K for IRAM code and
++ * pm_info.
++ *
++ */
++ iram_paddr = iram_tlb_phys_addr + MX6_SUSPEND_IRAM_ADDR_OFFSET;
++
++ /* Make sure iram_paddr is 8 byte aligned. */
++ if ((uintptr_t)(iram_paddr) & (FNCPY_ALIGN - 1))
++ iram_paddr += FNCPY_ALIGN - iram_paddr % (FNCPY_ALIGN);
++
++ /* Get the virtual address of the suspend code. */
++ suspend_ocram_base = (void *)IMX_IO_P2V(iram_paddr);
++
++ pm_info = suspend_ocram_base;
++ /* pbase points to iram_paddr. */
++ pm_info->pbase = iram_paddr;
++ pm_info->resume_addr = virt_to_phys(v7_cpu_resume);
++ pm_info->pm_info_size = sizeof(*pm_info);
++
++ /*
++ * ccm physical address is not used by asm code currently,
++ * so get ccm virtual address directly, as we already have
++ * it from ccm driver.
++ */
++ pm_info->ccm_base.pbase = MX6Q_CCM_BASE_ADDR;
++ pm_info->ccm_base.vbase = (void __iomem *)
++ IMX_IO_P2V(MX6Q_CCM_BASE_ADDR);
++
++ pm_info->mmdc_base.pbase = MX6Q_MMDC_P0_BASE_ADDR;
++ pm_info->mmdc_base.vbase = (void __iomem *)
++ IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR);
++
++ pm_info->src_base.pbase = MX6Q_SRC_BASE_ADDR;
++ pm_info->src_base.vbase = (void __iomem *)
++ IMX_IO_P2V(MX6Q_SRC_BASE_ADDR);
++
++ pm_info->iomuxc_base.pbase = MX6Q_IOMUXC_BASE_ADDR;
++ pm_info->iomuxc_base.vbase = (void __iomem *)
++ IMX_IO_P2V(MX6Q_IOMUXC_BASE_ADDR);
++
++ pm_info->gpc_base.pbase = MX6Q_GPC_BASE_ADDR;
++ pm_info->gpc_base.vbase = (void __iomem *)
++ IMX_IO_P2V(MX6Q_GPC_BASE_ADDR);
++
++ pm_info->l2_base.pbase = MX6Q_L2_BASE_ADDR;
++ pm_info->l2_base.vbase = (void __iomem *)
++ IMX_IO_P2V(MX6Q_L2_BASE_ADDR);
++
++ pm_info->anatop_base.pbase = MX6Q_ANATOP_BASE_ADDR;
++ pm_info->anatop_base.vbase = (void __iomem *)
++ IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR);
++
++ pm_info->ddr_type = imx_mmdc_get_ddr_type();
++ pm_info->mmdc_io_num = socdata->mmdc_io_num;
++ mmdc_io_offset_array = socdata->mmdc_io_offset;
++ pm_info->mmdc_num = socdata->mmdc_num;
++ mmdc_offset_array = socdata->mmdc_offset;
++
++ /* initialize MMDC IO settings */
++ for (i = 0; i < pm_info->mmdc_io_num; i++) {
++ pm_info->mmdc_io_val[i][0] =
++ mmdc_io_offset_array[i];
++ pm_info->mmdc_io_val[i][1] =
++ readl_relaxed(pm_info->iomuxc_base.vbase +
++ mmdc_io_offset_array[i]);
++ }
++ /* initialize MMDC settings */
++ for (i = 0; i < pm_info->mmdc_num; i++) {
++ pm_info->mmdc_val[i][0] =
++ mmdc_offset_array[i];
++ pm_info->mmdc_val[i][1] =
++ readl_relaxed(pm_info->mmdc_base.vbase +
++ mmdc_offset_array[i]);
++ }
++
++ /* need to overwrite the value for some mmdc registers */
++ if (cpu_is_imx6sx()) {
++ pm_info->mmdc_val[20][1] = (pm_info->mmdc_val[20][1]
++ & 0xffff0000) | 0x0202;
++ pm_info->mmdc_val[23][1] = 0x8033;
++ }
++
++ imx6_suspend_in_ocram_fn = fncpy(
++ suspend_ocram_base + sizeof(*pm_info),
++ &imx6_suspend,
++ MX6Q_SUSPEND_OCRAM_SIZE - sizeof(*pm_info));
++
++ goto put_node;
++
++put_node:
++ of_node_put(node);
++
++ return ret;
++}
++
++static void __init imx6_pm_common_init(const struct imx6_pm_socdata
++ *socdata)
++{
++ struct regmap *gpr;
++ int ret;
++
++ WARN_ON(!ccm_base);
++
++ if (IS_ENABLED(CONFIG_SUSPEND)) {
++ ret = imx6q_suspend_init(socdata);
++ if (ret)
++ pr_warn("%s: No DDR LPM support with suspend %d!\n",
++ __func__, ret);
++ }
++
++ /*
++ * This is for SW workaround step #1 of ERR007265, see comments
++ * in imx6q_set_lpm for details of this errata.
++ * Force IOMUXC irq pending, so that the interrupt to GPC can be
++ * used to deassert dsm_request signal when the signal gets
++ * asserted unexpectedly.
++ */
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr))
++ regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
++ IMX6Q_GPR1_GINT);
++}
++
++void __init imx6q_pm_init(void)
++{
++ imx6_pm_common_init(&imx6q_pm_data);
++}
++
++void __init imx6dl_pm_init(void)
++{
++ imx6_pm_common_init(&imx6dl_pm_data);
++}
++
++void __init imx6sl_pm_init(void)
++{
++ imx6_pm_common_init(&imx6sl_pm_data);
++}
++
++void __init imx6sx_pm_init(void)
++{
++ struct device_node *np;
++ struct resource res;
++
++ imx6_pm_common_init(&imx6sx_pm_data);
++ if (imx_get_soc_revision() < IMX_CHIP_REVISION_1_2) {
++ /*
++ * As there is a 16K OCRAM(start from 0x8f8000)
++ * dedicated for low power function on i.MX6SX,
++ * but ROM did NOT do the ocram address change
++ * accordingly, so we need to add a data patch
++ * to workaround this issue, otherwise, system
++ * will fail to resume from DSM mode. TO1.2 fixes
++ * this issue.
++ */
++ romcp = syscon_regmap_lookup_by_compatible(
++ "fsl,imx6sx-romcp");
++ if (IS_ERR(romcp)) {
++ pr_err("failed to find fsl,imx6sx-romcp regmap\n");
++ return;
++ }
++ regmap_write(romcp, ROMC_ROMPATCH0D, iram_tlb_phys_addr);
++ regmap_update_bits(romcp, ROMC_ROMPATCHCNTL,
++ BM_ROMPATCHCNTL_0D, BM_ROMPATCHCNTL_0D);
++ regmap_update_bits(romcp, ROMC_ROMPATCHENL,
++ BM_ROMPATCHENL_0D, BM_ROMPATCHENL_0D);
++ regmap_write(romcp, ROMC_ROMPATCH0A,
++ ROM_ADDR_FOR_INTERNAL_RAM_BASE);
++ regmap_update_bits(romcp, ROMC_ROMPATCHCNTL,
++ BM_ROMPATCHCNTL_DIS, ~BM_ROMPATCHCNTL_DIS);
++ }
++
++ np = of_find_compatible_node(NULL, NULL, "fsl,mega-fast-sram");
++ ocram_base = of_iomap(np, 0);
++ WARN_ON(!ocram_base);
++ WARN_ON(of_address_to_resource(np, 0, &res));
++ ocram_size = resource_size(&res);
++ ocram_saved_in_ddr = kzalloc(ocram_size, GFP_KERNEL);
++ WARN_ON(!ocram_saved_in_ddr);
++
++ np = of_find_node_by_path(
++ "/soc/aips-bus@02000000/spba-bus@02000000/serial@02020000");
++ if (np)
++ console_base = of_iomap(np, 0);
++ if (imx_src_is_m4_enabled()) {
++ np = of_find_compatible_node(NULL, NULL,
++ "fsl,imx6sx-qspi-m4-restore");
++ if (np)
++ qspi_base = of_iomap(np, 0);
++ WARN_ON(!qspi_base);
++ }
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/pm-imx6q.c linux-3.14.72/arch/arm/mach-imx/pm-imx6q.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/pm-imx6q.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/pm-imx6q.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,241 +0,0 @@
+-/*
+- * Copyright 2011-2013 Freescale Semiconductor, Inc.
+- * Copyright 2011 Linaro Ltd.
+- *
+- * The code contained herein is licensed under the GNU General Public
+- * License. You may obtain a copy of the GNU General Public License
+- * Version 2 or later at the following locations:
+- *
+- * http://www.opensource.org/licenses/gpl-license.html
+- * http://www.gnu.org/copyleft/gpl.html
+- */
+-
+-#include <linux/delay.h>
+-#include <linux/init.h>
+-#include <linux/io.h>
+-#include <linux/irq.h>
+-#include <linux/mfd/syscon.h>
+-#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+-#include <linux/of.h>
+-#include <linux/of_address.h>
+-#include <linux/regmap.h>
+-#include <linux/suspend.h>
+-#include <asm/cacheflush.h>
+-#include <asm/proc-fns.h>
+-#include <asm/suspend.h>
+-#include <asm/hardware/cache-l2x0.h>
+-
+-#include "common.h"
+-#include "hardware.h"
+-
+-#define CCR 0x0
+-#define BM_CCR_WB_COUNT (0x7 << 16)
+-#define BM_CCR_RBC_BYPASS_COUNT (0x3f << 21)
+-#define BM_CCR_RBC_EN (0x1 << 27)
+-
+-#define CLPCR 0x54
+-#define BP_CLPCR_LPM 0
+-#define BM_CLPCR_LPM (0x3 << 0)
+-#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
+-#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+-#define BM_CLPCR_SBYOS (0x1 << 6)
+-#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
+-#define BM_CLPCR_VSTBY (0x1 << 8)
+-#define BP_CLPCR_STBY_COUNT 9
+-#define BM_CLPCR_STBY_COUNT (0x3 << 9)
+-#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+-#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
+-#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
+-#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
+-#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
+-#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
+-#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
+-#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
+-#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
+-#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
+-#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
+-
+-#define CGPR 0x64
+-#define BM_CGPR_CHICKEN_BIT (0x1 << 17)
+-
+-static void __iomem *ccm_base;
+-
+-void imx6q_set_chicken_bit(void)
+-{
+- u32 val = readl_relaxed(ccm_base + CGPR);
+-
+- val |= BM_CGPR_CHICKEN_BIT;
+- writel_relaxed(val, ccm_base + CGPR);
+-}
+-
+-static void imx6q_enable_rbc(bool enable)
+-{
+- u32 val;
+-
+- /*
+- * need to mask all interrupts in GPC before
+- * operating RBC configurations
+- */
+- imx_gpc_mask_all();
+-
+- /* configure RBC enable bit */
+- val = readl_relaxed(ccm_base + CCR);
+- val &= ~BM_CCR_RBC_EN;
+- val |= enable ? BM_CCR_RBC_EN : 0;
+- writel_relaxed(val, ccm_base + CCR);
+-
+- /* configure RBC count */
+- val = readl_relaxed(ccm_base + CCR);
+- val &= ~BM_CCR_RBC_BYPASS_COUNT;
+- val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+- writel(val, ccm_base + CCR);
+-
+- /*
+- * need to delay at least 2 cycles of CKIL(32K)
+- * due to hardware design requirement, which is
+- * ~61us, here we use 65us for safe
+- */
+- udelay(65);
+-
+- /* restore GPC interrupt mask settings */
+- imx_gpc_restore_all();
+-}
+-
+-static void imx6q_enable_wb(bool enable)
+-{
+- u32 val;
+-
+- /* configure well bias enable bit */
+- val = readl_relaxed(ccm_base + CLPCR);
+- val &= ~BM_CLPCR_WB_PER_AT_LPM;
+- val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+- writel_relaxed(val, ccm_base + CLPCR);
+-
+- /* configure well bias count */
+- val = readl_relaxed(ccm_base + CCR);
+- val &= ~BM_CCR_WB_COUNT;
+- val |= enable ? BM_CCR_WB_COUNT : 0;
+- writel_relaxed(val, ccm_base + CCR);
+-}
+-
+-int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
+-{
+- struct irq_desc *iomuxc_irq_desc;
+- u32 val = readl_relaxed(ccm_base + CLPCR);
+-
+- val &= ~BM_CLPCR_LPM;
+- switch (mode) {
+- case WAIT_CLOCKED:
+- break;
+- case WAIT_UNCLOCKED:
+- val |= 0x1 << BP_CLPCR_LPM;
+- val |= BM_CLPCR_ARM_CLK_DIS_ON_LPM;
+- break;
+- case STOP_POWER_ON:
+- val |= 0x2 << BP_CLPCR_LPM;
+- break;
+- case WAIT_UNCLOCKED_POWER_OFF:
+- val |= 0x1 << BP_CLPCR_LPM;
+- val &= ~BM_CLPCR_VSTBY;
+- val &= ~BM_CLPCR_SBYOS;
+- break;
+- case STOP_POWER_OFF:
+- val |= 0x2 << BP_CLPCR_LPM;
+- val |= 0x3 << BP_CLPCR_STBY_COUNT;
+- val |= BM_CLPCR_VSTBY;
+- val |= BM_CLPCR_SBYOS;
+- if (cpu_is_imx6sl()) {
+- val |= BM_CLPCR_BYPASS_PMIC_READY;
+- val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
+- } else {
+- val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+- }
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- /*
+- * ERR007265: CCM: When improper low-power sequence is used,
+- * the SoC enters low power mode before the ARM core executes WFI.
+- *
+- * Software workaround:
+- * 1) Software should trigger IRQ #32 (IOMUX) to be always pending
+- * by setting IOMUX_GPR1_GINT.
+- * 2) Software should then unmask IRQ #32 in GPC before setting CCM
+- * Low-Power mode.
+- * 3) Software should mask IRQ #32 right after CCM Low-Power mode
+- * is set (set bits 0-1 of CCM_CLPCR).
+- */
+- iomuxc_irq_desc = irq_to_desc(32);
+- imx_gpc_irq_unmask(&iomuxc_irq_desc->irq_data);
+- writel_relaxed(val, ccm_base + CLPCR);
+- imx_gpc_irq_mask(&iomuxc_irq_desc->irq_data);
+-
+- return 0;
+-}
+-
+-static int imx6q_suspend_finish(unsigned long val)
+-{
+- cpu_do_idle();
+- return 0;
+-}
+-
+-static int imx6q_pm_enter(suspend_state_t state)
+-{
+- switch (state) {
+- case PM_SUSPEND_MEM:
+- imx6q_set_lpm(STOP_POWER_OFF);
+- imx6q_enable_wb(true);
+- imx6q_enable_rbc(true);
+- imx_gpc_pre_suspend();
+- imx_anatop_pre_suspend();
+- imx_set_cpu_jump(0, v7_cpu_resume);
+- /* Zzz ... */
+- cpu_suspend(0, imx6q_suspend_finish);
+- if (cpu_is_imx6q() || cpu_is_imx6dl())
+- imx_smp_prepare();
+- imx_anatop_post_resume();
+- imx_gpc_post_resume();
+- imx6q_enable_rbc(false);
+- imx6q_enable_wb(false);
+- imx6q_set_lpm(WAIT_CLOCKED);
+- break;
+- default:
+- return -EINVAL;
+- }
+-
+- return 0;
+-}
+-
+-static const struct platform_suspend_ops imx6q_pm_ops = {
+- .enter = imx6q_pm_enter,
+- .valid = suspend_valid_only_mem,
+-};
+-
+-void __init imx6q_pm_set_ccm_base(void __iomem *base)
+-{
+- ccm_base = base;
+-}
+-
+-void __init imx6q_pm_init(void)
+-{
+- struct regmap *gpr;
+-
+- WARN_ON(!ccm_base);
+-
+- /*
+- * This is for SW workaround step #1 of ERR007265, see comments
+- * in imx6q_set_lpm for details of this errata.
+- * Force IOMUXC irq pending, so that the interrupt to GPC can be
+- * used to deassert dsm_request signal when the signal gets
+- * asserted unexpectedly.
+- */
+- gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+- if (!IS_ERR(gpr))
+- regmap_update_bits(gpr, IOMUXC_GPR1, IMX6Q_GPR1_GINT,
+- IMX6Q_GPR1_GINT);
+-
+-
+- suspend_set_ops(&imx6q_pm_ops);
+-}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/src.c linux-3.14.72/arch/arm/mach-imx/src.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/src.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/src.c 2016-06-19 22:11:55.057156252 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011-2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -18,6 +18,7 @@
+ #include <linux/smp.h>
+ #include <asm/smp_plat.h>
+ #include "common.h"
++#include "hardware.h"
+
+ #define SRC_SCR 0x000
+ #define SRC_GPR1 0x020
+@@ -32,6 +33,7 @@
+
+ static void __iomem *src_base;
+ static DEFINE_SPINLOCK(scr_lock);
++static bool m4_is_enabled;
+
+ static const int sw_reset_bits[5] = {
+ BP_SRC_SCR_SW_GPU_RST,
+@@ -41,6 +43,11 @@
+ BP_SRC_SCR_SW_IPU2_RST
+ };
+
++bool imx_src_is_m4_enabled(void)
++{
++ return m4_is_enabled;
++}
++
+ static int imx_src_reset_module(struct reset_controller_dev *rcdev,
+ unsigned long sw_reset_idx)
+ {
+@@ -136,6 +143,14 @@
+ */
+ spin_lock(&scr_lock);
+ val = readl_relaxed(src_base + SRC_SCR);
++
++ /* bit 4 is m4c_non_sclr_rst on i.MX6SX */
++ if (cpu_is_imx6sx() && ((val &
++ (1 << BP_SRC_SCR_SW_OPEN_VG_RST)) == 0))
++ m4_is_enabled = true;
++ else
++ m4_is_enabled = false;
++
+ val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
+ writel_relaxed(val, src_base + SRC_SCR);
+ spin_unlock(&scr_lock);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/suspend-imx6.S linux-3.14.72/arch/arm/mach-imx/suspend-imx6.S
+--- linux-3.14.72.orig/arch/arm/mach-imx/suspend-imx6.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mach-imx/suspend-imx6.S 2016-06-19 22:11:55.057156252 +0200
+@@ -0,0 +1,661 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/linkage.h>
++#include <asm/asm-offsets.h>
++#include <asm/hardware/cache-l2x0.h>
++#include "hardware.h"
++
++/*
++ * ==================== low level suspend ====================
++ *
++ * Better to follow below rules to use ARM registers:
++ * r0: pm_info structure address;
++ * r1 ~ r4: for saving pm_info members;
++ * r5 ~ r10: free registers;
++ * r11: io base address.
++ *
++ * suspend ocram space layout:
++ * ======================== high address ======================
++ * .
++ * .
++ * .
++ * ^
++ * ^
++ * ^
++ * imx6_suspend code
++ * PM_INFO structure(imx6_cpu_pm_info)
++ * ======================== low address =======================
++ */
++
++/*
++ * Below offsets are based on struct imx6_cpu_pm_info
++ * which defined in arch/arm/mach-imx/pm-imx6q.c, this
++ * structure contains necessary pm info for low level
++ * suspend related code.
++ */
++#define PM_INFO_PBASE_OFFSET 0x0
++#define PM_INFO_RESUME_ADDR_OFFSET 0x4
++#define PM_INFO_DDR_TYPE_OFFSET 0x8
++#define PM_INFO_PM_INFO_SIZE_OFFSET 0xC
++#define PM_INFO_MX6Q_MMDC_P_OFFSET 0x10
++#define PM_INFO_MX6Q_MMDC_V_OFFSET 0x14
++#define PM_INFO_MX6Q_SRC_P_OFFSET 0x18
++#define PM_INFO_MX6Q_SRC_V_OFFSET 0x1C
++#define PM_INFO_MX6Q_IOMUXC_P_OFFSET 0x20
++#define PM_INFO_MX6Q_IOMUXC_V_OFFSET 0x24
++#define PM_INFO_MX6Q_CCM_P_OFFSET 0x28
++#define PM_INFO_MX6Q_CCM_V_OFFSET 0x2C
++#define PM_INFO_MX6Q_GPC_P_OFFSET 0x30
++#define PM_INFO_MX6Q_GPC_V_OFFSET 0x34
++#define PM_INFO_MX6Q_L2_P_OFFSET 0x38
++#define PM_INFO_MX6Q_L2_V_OFFSET 0x3C
++#define PM_INFO_MX6Q_ANATOP_P_OFFSET 0x40
++#define PM_INFO_MX6Q_ANATOP_V_OFFSET 0x44
++#define PM_INFO_MX6Q_TTBR1_V_OFFSET 0x48
++#define PM_INFO_MMDC_IO_NUM_OFFSET 0x4c
++#define PM_INFO_MMDC_IO_VAL_OFFSET 0x50
++/* below offsets depends on MX6_MAX_MMDC_IO_NUM(33) definition */
++#define PM_INFO_MMDC_NUM_OFFSET 0x158
++#define PM_INFO_MMDC_VAL_OFFSET 0x15c
++
++#define MX6Q_SRC_GPR1 0x20
++#define MX6Q_SRC_GPR2 0x24
++#define MX6Q_MMDC_MAPSR 0x404
++#define MX6Q_MMDC_MPDGCTRL0 0x83c
++#define MX6Q_GPC_IMR1 0x08
++#define MX6Q_GPC_IMR2 0x0c
++#define MX6Q_GPC_IMR3 0x10
++#define MX6Q_GPC_IMR4 0x14
++#define MX6Q_CCM_CCR 0x0
++#define MX6Q_ANATOP_CORE 0x140
++
++#define MX6_MAX_MMDC_IO_NUM 33
++#define MX6_MAX_MMDC_NUM 34
++
++ .align 3
++
++ .macro sync_l2_cache
++
++ /* sync L2 cache to drain L2's buffers to DRAM. */
++#ifdef CONFIG_CACHE_L2X0
++ ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
++ mov r6, #0x0
++ str r6, [r11, #L2X0_CACHE_SYNC]
++1:
++ ldr r6, [r11, #L2X0_CACHE_SYNC]
++ ands r6, r6, #0x1
++ bne 1b
++#endif
++
++ .endm
++
++ /* r11 must be MMDC base address */
++ .macro reset_read_fifo
++
++ /* reset read FIFO, RST_RD_FIFO */
++ ldr r7, =MX6Q_MMDC_MPDGCTRL0
++ ldr r6, [r11, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r11, r7]
++2:
++ ldr r6, [r11, r7]
++ ands r6, r6, #(1 << 31)
++ bne 2b
++
++ /* reset FIFO a second time */
++ ldr r6, [r11, r7]
++ orr r6, r6, #(1 << 31)
++ str r6, [r11, r7]
++3:
++ ldr r6, [r11, r7]
++ ands r6, r6, #(1 << 31)
++ bne 3b
++
++ .endm
++
++ /* r11 must be MMDC base address */
++ .macro mmdc_out_and_auto_self_refresh
++
++ /* let DDR out of self-refresh */
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #(1 << 21)
++ str r7, [r11, #MX6Q_MMDC_MAPSR]
++4:
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ bne 4b
++
++ /* enable DDR auto power saving */
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #0x1
++ str r7, [r11, #MX6Q_MMDC_MAPSR]
++
++ .endm
++
++ /* r10 must be iomuxc base address */
++ .macro resume_iomuxc_gpr
++
++ add r10, r10, #0x4000
++ /* IOMUXC GPR DRAM_RESET_BYPASS */
++ ldr r4, [r10, #0x8]
++ bic r4, r4, #(0x1 << 27)
++ str r4, [r10, #0x8]
++ /* IOMUXC GPR DRAM_CKE_BYPASS */
++ ldr r4, [r10, #0x8]
++ bic r4, r4, #(0x1 << 31)
++ str r4, [r10, #0x8]
++
++ .endm
++
++ .macro resume_io
++
++ /* restore MMDC IO */
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
++
++ ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
++ ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
++ add r7, r7, r0
++5:
++ ldr r8, [r7], #0x4
++ ldr r9, [r7], #0x4
++ str r9, [r10, r8]
++ subs r6, r6, #0x1
++ bne 5b
++
++ cmp r5, #0x0
++ /* Here only MMDC0 is set */
++ ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
++ ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
++
++ cmp r3, #IMX_DDR_TYPE_LPDDR2
++ bne 6f
++
++ reset_read_fifo
++6:
++ mmdc_out_and_auto_self_refresh
++
++ .endm
++
++ .macro resume_mmdc_io
++
++ cmp r5, #0x0
++ ldreq r10, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
++ ldrne r10, [r0, #PM_INFO_MX6Q_IOMUXC_P_OFFSET]
++ ldreq r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
++ ldrne r11, [r0, #PM_INFO_MX6Q_MMDC_P_OFFSET]
++
++ /* resume mmdc iomuxc settings */
++ ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
++ ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
++ add r7, r7, r0
++7:
++ ldr r8, [r7], #0x4
++ ldr r9, [r7], #0x4
++ str r9, [r10, r8]
++ subs r6, r6, #0x1
++ bne 7b
++
++ /* check whether we need to restore MMDC */
++ cmp r5, #0x0
++ beq 8f
++
++ /* check whether last suspend is with M/F mix off */
++ ldr r9, [r0, #PM_INFO_MX6Q_GPC_P_OFFSET]
++ ldr r6, [r9, #0x220]
++ cmp r6, #0x0
++ bne 9f
++8:
++ resume_iomuxc_gpr
++
++ b 13f
++9:
++ /* restore MMDC settings */
++ ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET]
++ ldr r7, =PM_INFO_MMDC_VAL_OFFSET
++ add r7, r7, r0
++10:
++ ldr r8, [r7], #0x4
++ ldr r9, [r7], #0x4
++ str r9, [r11, r8]
++ subs r6, r6, #0x1
++ bne 10b
++
++ /* let DDR enter self-refresh */
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #(1 << 20)
++ str r7, [r11, #MX6Q_MMDC_MAPSR]
++11:
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 24)
++ beq 11b
++
++ resume_iomuxc_gpr
++
++ reset_read_fifo
++
++ /* let DDR out of self-refresh */
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ bic r7, r7, #(1 << 20)
++ str r7, [r11, #MX6Q_MMDC_MAPSR]
++12:
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 24)
++ bne 12b
++
++ /* kick off MMDC */
++ ldr r4, =0x0
++ str r4, [r11, #0x1c]
++13:
++ mmdc_out_and_auto_self_refresh
++
++ .endm
++
++ .macro store_ttbr1
++
++ /* Store TTBR1 to pm_info->ttbr1 */
++ mrc p15, 0, r7, c2, c0, 1
++ str r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET]
++
++ /* Disable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the BTAC. */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ ldr r6, =iram_tlb_phys_addr
++ ldr r6, [r6]
++ dsb
++ isb
++
++ /* Store the IRAM table in TTBR1 */
++ mcr p15, 0, r6, c2, c0, 1
++ /* Read TTBCR and set PD0=1, N = 1 */
++ mrc p15, 0, r6, c2, c0, 2
++ orr r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ /* Disable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ bic r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ dsb
++ isb
++
++#ifdef CONFIG_CACHE_L2X0
++ ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
++ mov r6, #0x0
++ str r6, [r8, #0x100]
++
++ dsb
++ isb
++#endif
++
++ .endm
++
++ .macro restore_ttbr1
++
++#ifdef CONFIG_CACHE_L2X0
++ /* Enable L2. */
++ ldr r8, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
++ ldr r7, =0x1
++ str r7, [r8, #0x100]
++#endif
++
++ /* Enable L1 data cache. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x4
++ mcr p15, 0, r6, c1, c0, 0
++
++ dsb
++ isb
++
++ /* Restore TTBCR */
++ /* Read TTBCR and set PD0=0, N = 0 */
++ mrc p15, 0, r6, c2, c0, 2
++ bic r6, r6, #0x11
++ mcr p15, 0, r6, c2, c0, 2
++ dsb
++ isb
++
++ /* flush the TLB */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c8, c3, 0
++
++ /* Enable Branch Prediction, Z bit in SCTLR. */
++ mrc p15, 0, r6, c1, c0, 0
++ orr r6, r6, #0x800
++ mcr p15, 0, r6, c1, c0, 0
++
++ /* Flush the Branch Target Address Cache (BTAC) */
++ ldr r6, =0x0
++ mcr p15, 0, r6, c7, c1, 6
++
++ /* Restore TTBR1, get the origin ttbr1 from pm info */
++ ldr r7, [r0, #PM_INFO_MX6Q_TTBR1_V_OFFSET]
++ mcr p15, 0, r7, c2, c0, 1
++
++ .endm
++
++ENTRY(imx6_suspend)
++ push {r4-r12}
++ /*
++ * The value of r0 is mapped the same in origin table and IRAM table,
++ * thus no need to care r0 here.
++ */
++ ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
++ ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
++ ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
++ ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
++
++ /*
++ * counting the resume address in iram
++ * to set it in SRC register.
++ */
++ ldr r6, =imx6_suspend
++ ldr r7, =resume
++ sub r7, r7, r6
++ add r8, r1, r4
++ add r9, r8, r7
++
++ /*
++ * make sure TLB contain the addr we want,
++ * as we will access them after MMDC IO floated.
++ */
++
++ ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
++ ldr r6, [r11, #0x0]
++ ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
++ ldr r6, [r11, #0x0]
++
++ ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
++ /* store physical resume addr and pm_info address. */
++ str r9, [r11, #MX6Q_SRC_GPR1]
++ str r1, [r11, #MX6Q_SRC_GPR2]
++
++ /* need to sync L2 cache before DSM. */
++ sync_l2_cache
++
++ store_ttbr1
++
++ ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
++ /*
++ * put DDR explicitly into self-refresh and
++ * disable automatic power savings.
++ */
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #0x1
++ str r7, [r11, #MX6Q_MMDC_MAPSR]
++
++ /* make the DDR explicitly enter self-refresh. */
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ orr r7, r7, #(1 << 21)
++ str r7, [r11, #MX6Q_MMDC_MAPSR]
++
++poll_dvfs_set:
++ ldr r7, [r11, #MX6Q_MMDC_MAPSR]
++ ands r7, r7, #(1 << 25)
++ beq poll_dvfs_set
++
++ /* use r11 to store the IO address */
++ ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
++ ldr r6, =0x0
++ ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
++ ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
++ add r8, r8, r0
++ /* LPDDR2's last 3 IOs need special setting */
++ cmp r3, #IMX_DDR_TYPE_LPDDR2
++ subeq r7, r7, #0x3
++set_mmdc_io_lpm:
++ ldr r9, [r8], #0x8
++ str r6, [r11, r9]
++ subs r7, r7, #0x1
++ bne set_mmdc_io_lpm
++
++ cmp r3, #IMX_DDR_TYPE_LPDDR2
++ bne set_mmdc_io_lpm_done
++ ldr r6, =0x1000
++ ldr r9, [r8], #0x8
++ str r6, [r11, r9]
++ ldr r9, [r8], #0x8
++ str r6, [r11, r9]
++ ldr r6, =0x80000
++ ldr r9, [r8]
++ str r6, [r11, r9]
++set_mmdc_io_lpm_done:
++
++ /* check whether it supports Mega/Fast off */
++ ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET]
++ cmp r6, #0x0
++ beq set_mmdc_lpm_done
++
++ /* IOMUXC GPR DRAM_RESET */
++ add r11, r11, #0x4000
++ ldr r6, [r11, #0x8]
++ orr r6, r6, #(0x1 << 28)
++ str r6, [r11, #0x8]
++
++ /* IOMUXC GPR DRAM_RESET_BYPASS */
++ ldr r6, [r11, #0x8]
++ orr r6, r6, #(0x1 << 27)
++ str r6, [r11, #0x8]
++
++ /* IOMUXC GPR DRAM_CKE_BYPASS */
++ ldr r6, [r11, #0x8]
++ orr r6, r6, #(0x1 << 31)
++ str r6, [r11, #0x8]
++set_mmdc_lpm_done:
++
++ /*
++ * mask all GPC interrupts before
++ * enabling the RBC counters to
++ * avoid the counter starting too
++ * early if an interupt is already
++ * pending.
++ */
++ ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
++ ldr r6, [r11, #MX6Q_GPC_IMR1]
++ ldr r7, [r11, #MX6Q_GPC_IMR2]
++ ldr r8, [r11, #MX6Q_GPC_IMR3]
++ ldr r9, [r11, #MX6Q_GPC_IMR4]
++
++ ldr r10, =0xffffffff
++ str r10, [r11, #MX6Q_GPC_IMR1]
++ str r10, [r11, #MX6Q_GPC_IMR2]
++ str r10, [r11, #MX6Q_GPC_IMR3]
++ str r10, [r11, #MX6Q_GPC_IMR4]
++
++ /*
++ * enable the RBC bypass counter here
++ * to hold off the interrupts. RBC counter
++ * = 32 (1ms), Minimum RBC delay should be
++ * 400us for the analog LDOs to power down.
++ */
++ ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
++ ldr r10, [r11, #MX6Q_CCM_CCR]
++ bic r10, r10, #(0x3f << 21)
++ orr r10, r10, #(0x20 << 21)
++ str r10, [r11, #MX6Q_CCM_CCR]
++
++ /* enable the counter. */
++ ldr r10, [r11, #MX6Q_CCM_CCR]
++ orr r10, r10, #(0x1 << 27)
++ str r10, [r11, #MX6Q_CCM_CCR]
++
++ /* unmask all the GPC interrupts. */
++ ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
++ str r6, [r11, #MX6Q_GPC_IMR1]
++ str r7, [r11, #MX6Q_GPC_IMR2]
++ str r8, [r11, #MX6Q_GPC_IMR3]
++ str r9, [r11, #MX6Q_GPC_IMR4]
++
++ /*
++ * now delay for a short while (3usec)
++ * ARM is at 1GHz at this point
++ * so a short loop should be enough.
++ * this delay is required to ensure that
++ * the RBC counter can start counting in
++ * case an interrupt is already pending
++ * or in case an interrupt arrives just
++ * as ARM is about to assert DSM_request.
++ */
++ ldr r6, =2000
++rbc_loop:
++ subs r6, r6, #0x1
++ bne rbc_loop
++
++ /*
++ * ERR005852 Analog: Transition from Deep Sleep Mode to
++ * LDO Bypass Mode may cause the slow response of the
++ * VDDARM_CAP output.
++ *
++ * Software workaround:
++ * if internal ldo(VDDARM) bypassed, switch to analog bypass
++ * mode (0x1E), prio to entering DSM, and then, revert to the
++ * normal bypass mode, when exiting from DSM.
++ */
++ ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_V_OFFSET]
++ ldr r10, [r11, #MX6Q_ANATOP_CORE]
++ and r10, r10, #0x1f
++ cmp r10, #0x1f
++ bne ldo_check_done1
++ldo_analog_bypass:
++ ldr r10, [r11, #MX6Q_ANATOP_CORE]
++ bic r10, r10, #0x1f
++ orr r10, r10, #0x1e
++ str r10, [r11, #MX6Q_ANATOP_CORE]
++ldo_check_done1:
++ /* Zzz, enter stop mode */
++ wfi
++ nop
++ nop
++ nop
++ nop
++
++ /*
++ * run to here means there is pending
++ * wakeup source, system should auto
++ * resume, we need to restore MMDC IO first
++ */
++ /* restore it with 0x1f if use ldo bypass mode.*/
++ ldr r10, [r11, #MX6Q_ANATOP_CORE]
++ and r10, r10, #0x1f
++ cmp r10, #0x1e
++ bne ldo_check_done2
++ldo_bypass_restore:
++ ldr r10, [r11, #MX6Q_ANATOP_CORE]
++ orr r10, r10, #0x1f
++ str r10, [r11, #MX6Q_ANATOP_CORE]
++ldo_check_done2:
++
++ mov r5, #0x0
++ /* check whether it supports Mega/Fast off */
++ ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET]
++ cmp r6, #0x0
++ beq only_resume_io
++ resume_mmdc_io
++ b resume_mmdc_done
++only_resume_io:
++ resume_io
++resume_mmdc_done:
++ restore_ttbr1
++
++ pop {r4-r12}
++ /* return to suspend finish */
++ mov pc, lr
++
++resume:
++ /* invalidate L1 I-cache first */
++ mov r6, #0x0
++ mcr p15, 0, r6, c7, c5, 0
++ mcr p15, 0, r6, c7, c5, 6
++ /* enable the Icache and branch prediction */
++ mov r6, #0x1800
++ mcr p15, 0, r6, c1, c0, 0
++ isb
++
++ /* restore it with 0x1f if use ldo bypass mode.*/
++ ldr r11, [r0, #PM_INFO_MX6Q_ANATOP_P_OFFSET]
++ ldr r7, [r11, #MX6Q_ANATOP_CORE]
++ and r7, r7, #0x1f
++ cmp r7, #0x1e
++ bne ldo_check_done3
++ ldr r7, [r11, #MX6Q_ANATOP_CORE]
++ orr r7, r7, #0x1f
++ str r7, [r11, #MX6Q_ANATOP_CORE]
++ldo_check_done3:
++ /* get physical resume address from pm_info. */
++ ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
++ /* clear core0's entry and parameter */
++ ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
++ mov r7, #0x0
++ str r7, [r11, #MX6Q_SRC_GPR1]
++ str r7, [r11, #MX6Q_SRC_GPR2]
++
++ mov r5, #0x1
++ /* check whether it supports Mega/Fast off */
++ ldr r6, [r0, #PM_INFO_MMDC_NUM_OFFSET]
++ cmp r6, #0x0
++ beq dsm_only_resume_io
++ resume_mmdc_io
++ b dsm_resume_mmdc_done
++dsm_only_resume_io:
++ ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
++ resume_io
++dsm_resume_mmdc_done:
++
++ mov pc, lr
++ENDPROC(imx6_suspend)
++
++/*
++ * The following code must assume it is running from physical address
++ * where absolute virtual addresses to the data section have to be
++ * turned into relative ones.
++ */
++
++#ifdef CONFIG_CACHE_L2X0
++ .macro pl310_resume
++ adr r0, l2x0_saved_regs_offset
++ ldr r2, [r0]
++ add r2, r2, r0
++ ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
++ ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
++ str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
++ mov r1, #0x1
++ str r1, [r0, #L2X0_CTRL] @ re-enable L2
++ .endm
++
++l2x0_saved_regs_offset:
++ .word l2x0_saved_regs - .
++
++#else
++ .macro pl310_resume
++ .endm
++#endif
++
++ENTRY(v7_cpu_resume)
++ bl v7_invalidate_l1
++ pl310_resume
++ b cpu_resume
++ENDPROC(v7_cpu_resume)
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/system.c linux-3.14.72/arch/arm/mach-imx/system.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/system.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/system.c 2016-06-19 22:11:55.057156252 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2006-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
+ *
+@@ -34,6 +34,7 @@
+
+ static void __iomem *wdog_base;
+ static struct clk *wdog_clk;
++static u32 wdog_source = 1; /* use WDOG1 default */
+
+ /*
+ * Reset the system. It is called by machine_restart().
+@@ -47,6 +48,17 @@
+
+ if (cpu_is_mx1())
+ wcr_enable = (1 << 0);
++ /*
++ * Some i.MX6 boards use WDOG2 to reset external pmic in bypass mode,
++ * so do WDOG2 reset here. Do not set SRS, since we will
++ * trigger external POR later. Use WDOG1 to reset in ldo-enable
++ * mode. You can set it by "fsl,wdog-reset" in dts.
++ * For i.MX6SX we have to trigger wdog-reset to reset QSPI-NOR flash to
++ * workaround qspi-nor reboot issue whatever ldo-bypass or not.
++ */
++ else if ((wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
++ cpu_is_imx6sl())) || cpu_is_imx6sx())
++ wcr_enable = 0x14;
+ else
+ wcr_enable = (1 << 2);
+
+@@ -90,12 +102,29 @@
+
+ void __init mxc_arch_reset_init_dt(void)
+ {
+- struct device_node *np;
++ struct device_node *np = NULL;
++
++ if (cpu_is_imx6q() || cpu_is_imx6dl())
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
++ else if (cpu_is_imx6sl())
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpc");
++
++ if (np)
++ of_property_read_u32(np, "fsl,wdog-reset", &wdog_source);
++ pr_info("Use WDOG%d as reset source\n", wdog_source);
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
+ wdog_base = of_iomap(np, 0);
+ WARN_ON(!wdog_base);
+
++ /* Some i.MX6 boards use WDOG2 to reset board in ldo-bypass mode */
++ if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() ||
++ cpu_is_imx6sl())) {
++ np = of_find_compatible_node(np, NULL, "fsl,imx21-wdt");
++ wdog_base = of_iomap(np, 0);
++ WARN_ON(!wdog_base);
++ }
++
+ wdog_clk = of_clk_get(np, 0);
+ if (IS_ERR(wdog_clk)) {
+ pr_warn("%s: failed to get wdog clock\n", __func__);
+@@ -124,7 +153,7 @@
+ }
+
+ /* Configure the L2 PREFETCH and POWER registers */
+- val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
++ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
+ val |= 0x70800000;
+ /*
+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+@@ -137,14 +166,14 @@
+ */
+ if (cpu_is_imx6q())
+ val &= ~(1 << 30 | 1 << 23);
+- writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
+- val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
+- writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
++ writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
++ val = L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN;
++ writel_relaxed(val, l2x0_base + L310_POWER_CTRL);
+
+ iounmap(l2x0_base);
+ of_node_put(np);
+
+ out:
+- l2x0_of_init(0, ~0UL);
++ l2x0_of_init(0, ~0);
+ }
+ #endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-imx/time.c linux-3.14.72/arch/arm/mach-imx/time.c
+--- linux-3.14.72.orig/arch/arm/mach-imx/time.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-imx/time.c 2016-06-19 22:11:55.057156252 +0200
+@@ -25,8 +25,12 @@
+ #include <linux/irq.h>
+ #include <linux/clockchips.h>
+ #include <linux/clk.h>
++#include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/sched_clock.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
+
+ #include <asm/mach/time.h>
+
+@@ -56,11 +60,15 @@
+ #define MX2_TSTAT_CAPT (1 << 1)
+ #define MX2_TSTAT_COMP (1 << 0)
+
+-/* MX31, MX35, MX25, MX5 */
++/* MX31, MX35, MX25, MX5, MX6 */
+ #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
+ #define V2_TCTL_CLK_IPG (1 << 6)
+ #define V2_TCTL_CLK_PER (2 << 6)
++#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
++#define V2_TCTL_CLK_OSC (7 << 6)
++#define V2_TCTL_24MEN (1 << 10)
+ #define V2_TCTL_FRR (1 << 9)
++#define V2_TPRER_PRE24M 12
+ #define V2_IR 0x0c
+ #define V2_TSTAT 0x08
+ #define V2_TSTAT_OF1 (1 << 0)
+@@ -116,11 +124,22 @@
+ return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
+ }
+
++static struct delay_timer imx_delay_timer;
++
++static unsigned long imx_read_current_timer(void)
++{
++ return __raw_readl(sched_clock_reg);
++}
++
+ static int __init mxc_clocksource_init(struct clk *timer_clk)
+ {
+ unsigned int c = clk_get_rate(timer_clk);
+ void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
+
++ imx_delay_timer.read_current_timer = &imx_read_current_timer;
++ imx_delay_timer.freq = c;
++ register_current_timer_delay(&imx_delay_timer);
++
+ sched_clock_reg = reg;
+
+ sched_clock_register(mxc_read_sched_clock, 32, c);
+@@ -277,11 +296,20 @@
+
+ void __init mxc_timer_init(void __iomem *base, int irq)
+ {
+- uint32_t tctl_val;
++ uint32_t tctl_val, tprer_val;
+ struct clk *timer_clk;
+ struct clk *timer_ipg_clk;
+
+- timer_clk = clk_get_sys("imx-gpt.0", "per");
++ /*
++ * gpt clk source from 24M OSC on imx6q > TO1.0 and
++ * imx6dl, others from per clk.
++ */
++ if ((cpu_is_imx6q() && imx_get_soc_revision() > IMX_CHIP_REVISION_1_0)
++ || cpu_is_imx6dl() || cpu_is_imx6sx())
++ timer_clk = clk_get_sys("imx-gpt.0", "gpt_3m");
++ else
++ timer_clk = clk_get_sys("imx-gpt.0", "per");
++
+ if (IS_ERR(timer_clk)) {
+ pr_err("i.MX timer: unable to get clk\n");
+ return;
+@@ -302,10 +330,25 @@
+ __raw_writel(0, timer_base + MXC_TCTL);
+ __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
+
+- if (timer_is_v2())
+- tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
+- else
++ if (timer_is_v2()) {
++ if ((cpu_is_imx6q() && imx_get_soc_revision() >
++ IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl() ||
++ cpu_is_imx6sx()) {
++ tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR |
++ V2_TCTL_WAITEN | MXC_TCTL_TEN;
++ if (cpu_is_imx6dl() || cpu_is_imx6sx()) {
++ /* 24 / 8 = 3 MHz */
++ tprer_val = 7 << V2_TPRER_PRE24M;
++ __raw_writel(tprer_val, timer_base + MXC_TPRER);
++ tctl_val |= V2_TCTL_24MEN;
++ }
++ } else {
++ tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR |
++ V2_TCTL_WAITEN | MXC_TCTL_TEN;
++ }
++ } else {
+ tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
++ }
+
+ __raw_writel(tctl_val, timer_base + MXC_TCTL);
+
+@@ -316,3 +359,15 @@
+ /* Make irqs happen */
+ setup_irq(irq, &mxc_timer_irq);
+ }
++
++void __init mxc_timer_init_dt(struct device_node *np)
++{
++ void __iomem *base;
++ int irq;
++
++ base = of_iomap(np, 0);
++ WARN_ON(!base);
++ irq = irq_of_parse_and_map(np, 0);
++
++ mxc_timer_init(base, irq);
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mach-nomadik/cpu-8815.c linux-3.14.72/arch/arm/mach-nomadik/cpu-8815.c
+--- linux-3.14.72.orig/arch/arm/mach-nomadik/cpu-8815.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-nomadik/cpu-8815.c 2016-06-19 22:11:55.057156252 +0200
+@@ -147,7 +147,7 @@
+ {
+ #ifdef CONFIG_CACHE_L2X0
+ /* At full speed latency must be >=2, so 0x249 in low bits */
+- l2x0_of_init(0x00730249, 0xfe000fff);
++ l2x0_of_init(0x00700249, 0xfe0fefff);
+ #endif
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-omap2/omap4-common.c linux-3.14.72/arch/arm/mach-omap2/omap4-common.c
+--- linux-3.14.72.orig/arch/arm/mach-omap2/omap4-common.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-omap2/omap4-common.c 2016-06-19 22:11:55.057156252 +0200
+@@ -166,22 +166,38 @@
+ return l2cache_base;
+ }
+
+-static void omap4_l2x0_disable(void)
++static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
+ {
+- outer_flush_all();
+- /* Disable PL310 L2 Cache controller */
+- omap_smc1(0x102, 0x0);
+-}
++ unsigned smc_op;
+
+-static void omap4_l2x0_set_debug(unsigned long val)
+-{
+- /* Program PL310 L2 Cache controller debug register */
+- omap_smc1(0x100, val);
++ switch (reg) {
++ case L2X0_CTRL:
++ smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
++ break;
++
++ case L2X0_AUX_CTRL:
++ smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
++ break;
++
++ case L2X0_DEBUG_CTRL:
++ smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
++ break;
++
++ case L310_PREFETCH_CTRL:
++ smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
++ break;
++
++ default:
++ WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
++ return;
++ }
++
++ omap_smc1(smc_op, val);
+ }
+
+ static int __init omap_l2_cache_init(void)
+ {
+- u32 aux_ctrl = 0;
++ u32 aux_ctrl;
+
+ /*
+ * To avoid code running on other OMAPs in
+@@ -195,42 +211,19 @@
+ if (WARN_ON(!l2cache_base))
+ return -ENOMEM;
+
+- /*
+- * 16-way associativity, parity disabled
+- * Way size - 32KB (es1.0)
+- * Way size - 64KB (es2.0 +)
+- */
+- aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
+- (0x1 << 25) |
+- (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
+- (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
+-
+- if (omap_rev() == OMAP4430_REV_ES1_0) {
+- aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
+- } else {
+- aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+- (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+- (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+- (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+- (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
+- }
+- if (omap_rev() != OMAP4430_REV_ES1_0)
+- omap_smc1(0x109, aux_ctrl);
+-
+- /* Enable PL310 L2 Cache controller */
+- omap_smc1(0x102, 0x1);
++ /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
++ aux_ctrl = L310_AUX_CTRL_CACHE_REPLACE_RR |
++ L310_AUX_CTRL_NS_LOCKDOWN |
++ L310_AUX_CTRL_NS_INT_CTRL |
++ L2C_AUX_CTRL_SHARED_OVERRIDE |
++ L310_AUX_CTRL_DATA_PREFETCH |
++ L310_AUX_CTRL_INSTR_PREFETCH;
+
++ outer_cache.write_sec = omap4_l2c310_write_sec;
+ if (of_have_populated_dt())
+- l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
++ l2x0_of_init(aux_ctrl, 0xc19fffff);
+ else
+- l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+-
+- /*
+- * Override default outer_cache.disable with a OMAP4
+- * specific one
+- */
+- outer_cache.disable = omap4_l2x0_disable;
+- outer_cache.set_debug = omap4_l2x0_set_debug;
++ l2x0_init(l2cache_base, aux_ctrl, 0xc19fffff);
+
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-omap2/omap-mpuss-lowpower.c linux-3.14.72/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+--- linux-3.14.72.orig/arch/arm/mach-omap2/omap-mpuss-lowpower.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-omap2/omap-mpuss-lowpower.c 2016-06-19 22:11:55.057156252 +0200
+@@ -194,7 +194,7 @@
+ if (l2x0_base) {
+ val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+ __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+- val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
++ val = __raw_readl(l2x0_base + L310_PREFETCH_CTRL);
+ __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+ }
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-prima2/l2x0.c linux-3.14.72/arch/arm/mach-prima2/l2x0.c
+--- linux-3.14.72.orig/arch/arm/mach-prima2/l2x0.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-prima2/l2x0.c 2016-06-19 22:11:55.057156252 +0200
+@@ -8,43 +8,10 @@
+
+ #include <linux/init.h>
+ #include <linux/kernel.h>
+-#include <linux/of.h>
+ #include <asm/hardware/cache-l2x0.h>
+
+-struct l2x0_aux
+-{
+- u32 val;
+- u32 mask;
+-};
+-
+-static struct l2x0_aux prima2_l2x0_aux __initconst = {
+- .val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT,
+- .mask = 0,
+-};
+-
+-static struct l2x0_aux marco_l2x0_aux __initconst = {
+- .val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+- (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT),
+- .mask = L2X0_AUX_CTRL_MASK,
+-};
+-
+-static struct of_device_id sirf_l2x0_ids[] __initconst = {
+- { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, },
+- { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, },
+- {},
+-};
+-
+ static int __init sirfsoc_l2x0_init(void)
+ {
+- struct device_node *np;
+- const struct l2x0_aux *aux;
+-
+- np = of_find_matching_node(NULL, sirf_l2x0_ids);
+- if (np) {
+- aux = of_match_node(sirf_l2x0_ids, np)->data;
+- return l2x0_of_init(aux->val, aux->mask);
+- }
+-
+- return 0;
++ return l2x0_of_init(0, ~0);
+ }
+ early_initcall(sirfsoc_l2x0_init);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-prima2/pm.c linux-3.14.72/arch/arm/mach-prima2/pm.c
+--- linux-3.14.72.orig/arch/arm/mach-prima2/pm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-prima2/pm.c 2016-06-19 22:11:55.057156252 +0200
+@@ -71,7 +71,6 @@
+ case PM_SUSPEND_MEM:
+ sirfsoc_pre_suspend_power_off();
+
+- outer_flush_all();
+ outer_disable();
+ /* go zzz */
+ cpu_suspend(0, sirfsoc_finish_suspend);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-realview/realview_eb.c linux-3.14.72/arch/arm/mach-realview/realview_eb.c
+--- linux-3.14.72.orig/arch/arm/mach-realview/realview_eb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-realview/realview_eb.c 2016-06-19 22:11:55.057156252 +0200
+@@ -442,8 +442,13 @@
+ realview_eb11mp_fixup();
+
+ #ifdef CONFIG_CACHE_L2X0
+- /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+- * Bits: .... ...0 0111 1001 0000 .... .... .... */
++ /*
++ * The PL220 needs to be manually configured as the hardware
++ * doesn't report the correct sizes.
++ * 1MB (128KB/way), 8-way associativity, event monitor and
++ * parity enabled, ignore share bit, no force write allocate
++ * Bits: .... ...0 0111 1001 0000 .... .... ....
++ */
+ l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
+ #endif
+ platform_device_register(&pmu_device);
+diff -Nur linux-3.14.72.orig/arch/arm/mach-realview/realview_pb1176.c linux-3.14.72/arch/arm/mach-realview/realview_pb1176.c
+--- linux-3.14.72.orig/arch/arm/mach-realview/realview_pb1176.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-realview/realview_pb1176.c 2016-06-19 22:11:55.057156252 +0200
+@@ -355,7 +355,13 @@
+ int i;
+
+ #ifdef CONFIG_CACHE_L2X0
+- /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
++ /*
++ * The PL220 needs to be manually configured as the hardware
++ * doesn't report the correct sizes.
++ * 128kB (16kB/way), 8-way associativity, event monitor and
++ * parity enabled, ignore share bit, no force write allocate
++ * Bits: .... ...0 0111 0011 0000 .... .... ....
++ */
+ l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
+ #endif
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-realview/realview_pb11mp.c linux-3.14.72/arch/arm/mach-realview/realview_pb11mp.c
+--- linux-3.14.72.orig/arch/arm/mach-realview/realview_pb11mp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-realview/realview_pb11mp.c 2016-06-19 22:11:55.057156252 +0200
+@@ -337,8 +337,13 @@
+ int i;
+
+ #ifdef CONFIG_CACHE_L2X0
+- /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+- * Bits: .... ...0 0111 1001 0000 .... .... .... */
++ /*
++ * The PL220 needs to be manually configured as the hardware
++ * doesn't report the correct sizes.
++ * 1MB (128KB/way), 8-way associativity, event monitor and
++ * parity enabled, ignore share bit, no force write allocate
++ * Bits: .... ...0 0111 1001 0000 .... .... ....
++ */
+ l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
+ #endif
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-realview/realview_pbx.c linux-3.14.72/arch/arm/mach-realview/realview_pbx.c
+--- linux-3.14.72.orig/arch/arm/mach-realview/realview_pbx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-realview/realview_pbx.c 2016-06-19 22:11:55.057156252 +0200
+@@ -370,8 +370,8 @@
+ __io_address(REALVIEW_PBX_TILE_L220_BASE);
+
+ /* set RAM latencies to 1 cycle for eASIC */
+- writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+- writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
++ writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
++ writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
+
+ /* 16KB way size, 8-way associativity, parity disabled
+ * Bits: .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
+diff -Nur linux-3.14.72.orig/arch/arm/mach-rockchip/rockchip.c linux-3.14.72/arch/arm/mach-rockchip/rockchip.c
+--- linux-3.14.72.orig/arch/arm/mach-rockchip/rockchip.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-rockchip/rockchip.c 2016-06-19 22:11:55.057156252 +0200
+@@ -25,7 +25,7 @@
+
+ static void __init rockchip_dt_init(void)
+ {
+- l2x0_of_init(0, ~0UL);
++ l2x0_of_init(0, ~0);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ }
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-shmobile/board-armadillo800eva.c linux-3.14.72/arch/arm/mach-shmobile/board-armadillo800eva.c
+--- linux-3.14.72.orig/arch/arm/mach-shmobile/board-armadillo800eva.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-shmobile/board-armadillo800eva.c 2016-06-19 22:11:55.057156252 +0200
+@@ -1270,8 +1270,8 @@
+
+
+ #ifdef CONFIG_CACHE_L2X0
+- /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+- l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
++ /* Shared attribute override enable, 32K*8way */
++ l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
+ #endif
+
+ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
+diff -Nur linux-3.14.72.orig/arch/arm/mach-shmobile/board-armadillo800eva-reference.c linux-3.14.72/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+--- linux-3.14.72.orig/arch/arm/mach-shmobile/board-armadillo800eva-reference.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-shmobile/board-armadillo800eva-reference.c 2016-06-19 22:11:55.057156252 +0200
+@@ -164,8 +164,8 @@
+ r8a7740_meram_workaround();
+
+ #ifdef CONFIG_CACHE_L2X0
+- /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+- l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
++ /* Shared attribute override enable, 32K*8way */
++ l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
+ #endif
+
+ r8a7740_add_standard_devices_dt();
+diff -Nur linux-3.14.72.orig/arch/arm/mach-shmobile/board-kzm9g.c linux-3.14.72/arch/arm/mach-shmobile/board-kzm9g.c
+--- linux-3.14.72.orig/arch/arm/mach-shmobile/board-kzm9g.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-shmobile/board-kzm9g.c 2016-06-19 22:11:55.057156252 +0200
+@@ -878,8 +878,8 @@
+ gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
+
+ #ifdef CONFIG_CACHE_L2X0
+- /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+- l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
++ /* Shared attribute override enable, 64K*8way */
++ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
+ #endif
+
+ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
+diff -Nur linux-3.14.72.orig/arch/arm/mach-shmobile/board-kzm9g-reference.c linux-3.14.72/arch/arm/mach-shmobile/board-kzm9g-reference.c
+--- linux-3.14.72.orig/arch/arm/mach-shmobile/board-kzm9g-reference.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-shmobile/board-kzm9g-reference.c 2016-06-19 22:11:55.057156252 +0200
+@@ -36,8 +36,8 @@
+ sh73a0_add_standard_devices_dt();
+
+ #ifdef CONFIG_CACHE_L2X0
+- /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+- l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
++ /* Shared attribute override enable, 64K*8way */
++ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
+ #endif
+ }
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-shmobile/setup-r8a7778.c linux-3.14.72/arch/arm/mach-shmobile/setup-r8a7778.c
+--- linux-3.14.72.orig/arch/arm/mach-shmobile/setup-r8a7778.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-shmobile/setup-r8a7778.c 2016-06-19 22:11:55.057156252 +0200
+@@ -298,10 +298,10 @@
+ void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
+ if (base) {
+ /*
+- * Early BRESP enable, Shared attribute override enable, 64K*16way
++ * Shared attribute override enable, 64K*16way
+ * don't call iounmap(base)
+ */
+- l2x0_init(base, 0x40470000, 0x82000fff);
++ l2x0_init(base, 0x00400000, 0xc20f0fff);
+ }
+ #endif
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-shmobile/setup-r8a7779.c linux-3.14.72/arch/arm/mach-shmobile/setup-r8a7779.c
+--- linux-3.14.72.orig/arch/arm/mach-shmobile/setup-r8a7779.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-shmobile/setup-r8a7779.c 2016-06-19 22:11:55.057156252 +0200
+@@ -700,8 +700,8 @@
+ void __init r8a7779_add_standard_devices(void)
+ {
+ #ifdef CONFIG_CACHE_L2X0
+- /* Early BRESP enable, Shared attribute override enable, 64K*16way */
+- l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
++ /* Shared attribute override enable, 64K*16way */
++ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
+ #endif
+ r8a7779_pm_init();
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-socfpga/socfpga.c linux-3.14.72/arch/arm/mach-socfpga/socfpga.c
+--- linux-3.14.72.orig/arch/arm/mach-socfpga/socfpga.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-socfpga/socfpga.c 2016-06-19 22:11:55.057156252 +0200
+@@ -104,7 +104,7 @@
+
+ static void __init socfpga_cyclone5_init(void)
+ {
+- l2x0_of_init(0, ~0UL);
++ l2x0_of_init(0, ~0);
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ socfpga_init_clocks();
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-spear/platsmp.c linux-3.14.72/arch/arm/mach-spear/platsmp.c
+--- linux-3.14.72.orig/arch/arm/mach-spear/platsmp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-spear/platsmp.c 2016-06-19 22:11:55.057156252 +0200
+@@ -20,6 +20,18 @@
+ #include <mach/spear.h>
+ #include "generic.h"
+
++/*
++ * Write pen_release in a way that is guaranteed to be visible to all
++ * observers, irrespective of whether they're taking part in coherency
++ * or not. This is necessary for the hotplug code to work reliably.
++ */
++static void write_pen_release(int val)
++{
++ pen_release = val;
++ smp_wmb();
++ sync_cache_w(&pen_release);
++}
++
+ static DEFINE_SPINLOCK(boot_lock);
+
+ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
+@@ -30,8 +42,7 @@
+ * let the primary processor know we're out of the
+ * pen, then head off into the C entry point
+ */
+- pen_release = -1;
+- smp_wmb();
++ write_pen_release(-1);
+
+ /*
+ * Synchronise with the boot thread.
+@@ -58,9 +69,7 @@
+ * Note that "pen_release" is the hardware CPU ID, whereas
+ * "cpu" is Linux's internal ID.
+ */
+- pen_release = cpu;
+- flush_cache_all();
+- outer_flush_all();
++ write_pen_release(cpu);
+
+ timeout = jiffies + (1 * HZ);
+ while (time_before(jiffies, timeout)) {
+diff -Nur linux-3.14.72.orig/arch/arm/mach-spear/spear13xx.c linux-3.14.72/arch/arm/mach-spear/spear13xx.c
+--- linux-3.14.72.orig/arch/arm/mach-spear/spear13xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-spear/spear13xx.c 2016-06-19 22:11:55.057156252 +0200
+@@ -38,15 +38,15 @@
+ if (!IS_ENABLED(CONFIG_CACHE_L2X0))
+ return;
+
+- writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
++ writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
+
+ /*
+ * Program following latencies in order to make
+ * SPEAr1340 work at 600 MHz
+ */
+- writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
+- writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
+- l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
++ writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
++ writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
++ l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
+ }
+
+ /*
+diff -Nur linux-3.14.72.orig/arch/arm/mach-sti/board-dt.c linux-3.14.72/arch/arm/mach-sti/board-dt.c
+--- linux-3.14.72.orig/arch/arm/mach-sti/board-dt.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-sti/board-dt.c 2016-06-19 22:11:55.057156252 +0200
+@@ -16,15 +16,9 @@
+
+ void __init stih41x_l2x0_init(void)
+ {
+- u32 way_size = 0x4;
+- u32 aux_ctrl;
+- /* may be this can be encoded in macros like BIT*() */
+- aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+- (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+- (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+- (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
+-
+- l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
++ l2x0_of_init(L2C_AUX_CTRL_SHARED_OVERRIDE |
++ L310_AUX_CTRL_DATA_PREFETCH |
++ L310_AUX_CTRL_INSTR_PREFETCH, 0xc00f0fff);
+ }
+
+ static void __init stih41x_machine_init(void)
+diff -Nur linux-3.14.72.orig/arch/arm/mach-tegra/sleep.h linux-3.14.72/arch/arm/mach-tegra/sleep.h
+--- linux-3.14.72.orig/arch/arm/mach-tegra/sleep.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-tegra/sleep.h 2016-06-19 22:11:55.061155987 +0200
+@@ -134,13 +134,13 @@
+ tst \tmp3, #L2X0_CTRL_EN
+ bne exit_l2_resume
+ ldr \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
+- str \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
++ str \tmp3, [\tmp2, #L310_TAG_LATENCY_CTRL]
+ ldr \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
+- str \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
++ str \tmp3, [\tmp2, #L310_DATA_LATENCY_CTRL]
+ ldr \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
+- str \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
++ str \tmp3, [\tmp2, #L310_PREFETCH_CTRL]
+ ldr \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
+- str \tmp3, [\tmp2, #L2X0_POWER_CTRL]
++ str \tmp3, [\tmp2, #L310_POWER_CTRL]
+ ldr \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
+ str \tmp3, [\tmp2, #L2X0_AUX_CTRL]
+ mov \tmp3, #L2X0_CTRL_EN
+diff -Nur linux-3.14.72.orig/arch/arm/mach-tegra/tegra.c linux-3.14.72/arch/arm/mach-tegra/tegra.c
+--- linux-3.14.72.orig/arch/arm/mach-tegra/tegra.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-tegra/tegra.c 2016-06-19 22:11:55.061155987 +0200
+@@ -73,25 +73,9 @@
+ static void __init tegra_init_cache(void)
+ {
+ #ifdef CONFIG_CACHE_L2X0
+- static const struct of_device_id pl310_ids[] __initconst = {
+- { .compatible = "arm,pl310-cache", },
+- {}
+- };
+-
+- struct device_node *np;
+ int ret;
+- void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+- u32 aux_ctrl, cache_type;
+-
+- np = of_find_matching_node(NULL, pl310_ids);
+- if (!np)
+- return;
+-
+- cache_type = readl(p + L2X0_CACHE_TYPE);
+- aux_ctrl = (cache_type & 0x700) << (17-8);
+- aux_ctrl |= 0x7C400001;
+
+- ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
++ ret = l2x0_of_init(0x3c400001, 0xc20fc3fe);
+ if (!ret)
+ l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
+ #endif
+diff -Nur linux-3.14.72.orig/arch/arm/mach-ux500/cache-l2x0.c linux-3.14.72/arch/arm/mach-ux500/cache-l2x0.c
+--- linux-3.14.72.orig/arch/arm/mach-ux500/cache-l2x0.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-ux500/cache-l2x0.c 2016-06-19 22:11:55.061155987 +0200
+@@ -35,10 +35,16 @@
+ return 0;
+ }
+
+-static int __init ux500_l2x0_init(void)
++static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
+ {
+- u32 aux_val = 0x3e000000;
++ /*
++ * We can't write to secure registers as we are in non-secure
++ * mode, until we have some SMI service available.
++ */
++}
+
++static int __init ux500_l2x0_init(void)
++{
+ if (cpu_is_u8500_family() || cpu_is_ux540_family())
+ l2x0_base = __io_address(U8500_L2CC_BASE);
+ else
+@@ -48,28 +54,12 @@
+ /* Unlock before init */
+ ux500_l2x0_unlock();
+
+- /* DBx540's L2 has 128KB way size */
+- if (cpu_is_ux540_family())
+- /* 128KB way size */
+- aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
+- else
+- /* 64KB way size */
+- aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
++ outer_cache.write_sec = ux500_l2c310_write_sec;
+
+- /* 64KB way size, 8 way associativity, force WA */
+ if (of_have_populated_dt())
+- l2x0_of_init(aux_val, 0xc0000fff);
++ l2x0_of_init(0, ~0);
+ else
+- l2x0_init(l2x0_base, aux_val, 0xc0000fff);
+-
+- /*
+- * We can't disable l2 as we are in non secure mode, currently
+- * this seems be called only during kexec path. So let's
+- * override outer.disable with nasty assignment until we have
+- * some SMI service available.
+- */
+- outer_cache.disable = NULL;
+- outer_cache.set_debug = NULL;
++ l2x0_init(l2x0_base, 0, ~0);
+
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mach-vexpress/ct-ca9x4.c linux-3.14.72/arch/arm/mach-vexpress/ct-ca9x4.c
+--- linux-3.14.72.orig/arch/arm/mach-vexpress/ct-ca9x4.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-vexpress/ct-ca9x4.c 2016-06-19 22:11:55.061155987 +0200
+@@ -45,6 +45,23 @@
+ iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
+ }
+
++static void __init ca9x4_l2_init(void)
++{
++#ifdef CONFIG_CACHE_L2X0
++ void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
++
++ if (l2x0_base) {
++ /* set RAM latencies to 1 cycle for this core tile. */
++ writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
++ writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
++
++ l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
++ } else {
++ pr_err("L2C: unable to map L2 cache controller\n");
++ }
++#endif
++}
++
+ #ifdef CONFIG_HAVE_ARM_TWD
+ static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
+
+@@ -63,6 +80,7 @@
+ gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
+ ioremap(A9_MPCORE_GIC_CPU, SZ_256));
+ ca9x4_twd_init();
++ ca9x4_l2_init();
+ }
+
+ static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
+@@ -141,16 +159,6 @@
+ {
+ int i;
+
+-#ifdef CONFIG_CACHE_L2X0
+- void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
+-
+- /* set RAM latencies to 1 cycle for this core tile. */
+- writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+- writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
+-
+- l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
+-#endif
+-
+ for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
+ amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
+
+diff -Nur linux-3.14.72.orig/arch/arm/mach-zynq/common.c linux-3.14.72/arch/arm/mach-zynq/common.c
+--- linux-3.14.72.orig/arch/arm/mach-zynq/common.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mach-zynq/common.c 2016-06-19 22:11:55.061155987 +0200
+@@ -67,7 +67,7 @@
+ /*
+ * 64KB way size, 8-way associativity, parity disabled
+ */
+- l2x0_of_init(0x02060000, 0xF0F0FFFF);
++ l2x0_of_init(0x02000000, 0xf0ffffff);
+
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+diff -Nur linux-3.14.72.orig/arch/arm/mm/cache-feroceon-l2.c linux-3.14.72/arch/arm/mm/cache-feroceon-l2.c
+--- linux-3.14.72.orig/arch/arm/mm/cache-feroceon-l2.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mm/cache-feroceon-l2.c 2016-06-19 22:11:55.061155987 +0200
+@@ -343,7 +343,6 @@
+ outer_cache.inv_range = feroceon_l2_inv_range;
+ outer_cache.clean_range = feroceon_l2_clean_range;
+ outer_cache.flush_range = feroceon_l2_flush_range;
+- outer_cache.inv_all = l2_inv_all;
+
+ enable_l2();
+
+diff -Nur linux-3.14.72.orig/arch/arm/mm/cache-l2x0.c linux-3.14.72/arch/arm/mm/cache-l2x0.c
+--- linux-3.14.72.orig/arch/arm/mm/cache-l2x0.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mm/cache-l2x0.c 2016-06-19 22:11:55.061155987 +0200
+@@ -24,10 +24,22 @@
+ #include <linux/of_address.h>
+
+ #include <asm/cacheflush.h>
++#include <asm/cputype.h>
+ #include <asm/hardware/cache-l2x0.h>
+ #include "cache-tauros3.h"
+ #include "cache-aurora-l2.h"
+
++struct l2c_init_data {
++ const char *type;
++ unsigned way_size_0;
++ unsigned num_lock;
++ void (*of_parse)(const struct device_node *, u32 *, u32 *);
++ void (*enable)(void __iomem *, u32, unsigned);
++ void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
++ void (*save)(void __iomem *);
++ struct outer_cache_fns outer_cache;
++};
++
+ #define CACHE_LINE_SIZE 32
+
+ static void __iomem *l2x0_base;
+@@ -36,96 +48,116 @@
+ static u32 l2x0_size;
+ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
+
+-/* Aurora don't have the cache ID register available, so we have to
+- * pass it though the device tree */
+-static u32 cache_id_part_number_from_dt;
+-
+ struct l2x0_regs l2x0_saved_regs;
+
+-struct l2x0_of_data {
+- void (*setup)(const struct device_node *, u32 *, u32 *);
+- void (*save)(void);
+- struct outer_cache_fns outer_cache;
+-};
+-
+-static bool of_init = false;
+-
+-static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
++/*
++ * Common code for all cache controllers.
++ */
++static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask)
+ {
+ /* wait for cache operation by line or way to complete */
+ while (readl_relaxed(reg) & mask)
+ cpu_relax();
+ }
+
+-#ifdef CONFIG_CACHE_PL310
+-static inline void cache_wait(void __iomem *reg, unsigned long mask)
++/*
++ * By default, we write directly to secure registers. Platforms must
++ * override this if they are running non-secure.
++ */
++static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg)
+ {
+- /* cache operations by line are atomic on PL310 */
++ if (val == readl_relaxed(base + reg))
++ return;
++ if (outer_cache.write_sec)
++ outer_cache.write_sec(val, reg);
++ else
++ writel_relaxed(val, base + reg);
+ }
+-#else
+-#define cache_wait cache_wait_way
+-#endif
+
+-static inline void cache_sync(void)
++/*
++ * This should only be called when we have a requirement that the
++ * register be written due to a work-around, as platforms running
++ * in non-secure mode may not be able to access this register.
++ */
++static inline void l2c_set_debug(void __iomem *base, unsigned long val)
+ {
+- void __iomem *base = l2x0_base;
+-
+- writel_relaxed(0, base + sync_reg_offset);
+- cache_wait(base + L2X0_CACHE_SYNC, 1);
++ l2c_write_sec(val, base, L2X0_DEBUG_CTRL);
+ }
+
+-static inline void l2x0_clean_line(unsigned long addr)
++static void __l2c_op_way(void __iomem *reg)
+ {
+- void __iomem *base = l2x0_base;
+- cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+- writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
++ writel_relaxed(l2x0_way_mask, reg);
++ l2c_wait_mask(reg, l2x0_way_mask);
+ }
+
+-static inline void l2x0_inv_line(unsigned long addr)
++static inline void l2c_unlock(void __iomem *base, unsigned num)
+ {
+- void __iomem *base = l2x0_base;
+- cache_wait(base + L2X0_INV_LINE_PA, 1);
+- writel_relaxed(addr, base + L2X0_INV_LINE_PA);
++ unsigned i;
++
++ for (i = 0; i < num; i++) {
++ writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
++ i * L2X0_LOCKDOWN_STRIDE);
++ writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
++ i * L2X0_LOCKDOWN_STRIDE);
++ }
+ }
+
+-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+-static inline void debug_writel(unsigned long val)
++/*
++ * Enable the L2 cache controller. This function must only be
++ * called when the cache controller is known to be disabled.
++ */
++static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
+ {
+- if (outer_cache.set_debug)
+- outer_cache.set_debug(val);
++ unsigned long flags;
++
++ l2c_write_sec(aux, base, L2X0_AUX_CTRL);
++
++ l2c_unlock(base, num_lock);
++
++ local_irq_save(flags);
++ __l2c_op_way(base + L2X0_INV_WAY);
++ writel_relaxed(0, base + sync_reg_offset);
++ l2c_wait_mask(base + sync_reg_offset, 1);
++ local_irq_restore(flags);
++
++ l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
+ }
+
+-static void pl310_set_debug(unsigned long val)
++static void l2c_disable(void)
+ {
+- writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
++ void __iomem *base = l2x0_base;
++
++ outer_cache.flush_all();
++ l2c_write_sec(0, base, L2X0_CTRL);
++ dsb(st);
+ }
+-#else
+-/* Optimised out for non-errata case */
+-static inline void debug_writel(unsigned long val)
++
++#ifdef CONFIG_CACHE_PL310
++static inline void cache_wait(void __iomem *reg, unsigned long mask)
+ {
++ /* cache operations by line are atomic on PL310 */
+ }
+-
+-#define pl310_set_debug NULL
++#else
++#define cache_wait l2c_wait_mask
+ #endif
+
+-#ifdef CONFIG_PL310_ERRATA_588369
+-static inline void l2x0_flush_line(unsigned long addr)
++static inline void cache_sync(void)
+ {
+ void __iomem *base = l2x0_base;
+
+- /* Clean by PA followed by Invalidate by PA */
+- cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+- writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
+- cache_wait(base + L2X0_INV_LINE_PA, 1);
+- writel_relaxed(addr, base + L2X0_INV_LINE_PA);
++ writel_relaxed(0, base + sync_reg_offset);
++ cache_wait(base + L2X0_CACHE_SYNC, 1);
+ }
+-#else
+
+-static inline void l2x0_flush_line(unsigned long addr)
++#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
++static inline void debug_writel(unsigned long val)
++{
++ l2c_set_debug(l2x0_base, val);
++}
++#else
++/* Optimised out for non-errata case */
++static inline void debug_writel(unsigned long val)
+ {
+- void __iomem *base = l2x0_base;
+- cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+- writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
+ }
+ #endif
+
+@@ -141,8 +173,7 @@
+ static void __l2x0_flush_all(void)
+ {
+ debug_writel(0x03);
+- writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
+- cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
++ __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY);
+ cache_sync();
+ debug_writel(0x00);
+ }
+@@ -157,250 +188,610 @@
+ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ }
+
+-static void l2x0_clean_all(void)
++static void l2x0_disable(void)
+ {
+ unsigned long flags;
+
+- /* clean all ways */
+ raw_spin_lock_irqsave(&l2x0_lock, flags);
+- writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
+- cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
+- cache_sync();
++ __l2x0_flush_all();
++ l2c_write_sec(0, l2x0_base, L2X0_CTRL);
++ dsb(st);
+ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ }
+
+-static void l2x0_inv_all(void)
++/*
++ * L2C-210 specific code.
++ *
++ * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
++ * ensure that no background operation is running. The way operations
++ * are all background tasks.
++ *
++ * While a background operation is in progress, any new operation is
++ * ignored (unspecified whether this causes an error.) Thankfully, not
++ * used on SMP.
++ *
++ * Never has a different sync register other than L2X0_CACHE_SYNC, but
++ * we use sync_reg_offset here so we can share some of this with L2C-310.
++ */
++static void __l2c210_cache_sync(void __iomem *base)
+ {
+- unsigned long flags;
++ writel_relaxed(0, base + sync_reg_offset);
++}
+
+- /* invalidate all ways */
+- raw_spin_lock_irqsave(&l2x0_lock, flags);
+- /* Invalidating when L2 is enabled is a nono */
+- BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
+- writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+- cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+- cache_sync();
+- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start,
++ unsigned long end)
++{
++ while (start < end) {
++ writel_relaxed(start, reg);
++ start += CACHE_LINE_SIZE;
++ }
+ }
+
+-static void l2x0_inv_range(unsigned long start, unsigned long end)
++static void l2c210_inv_range(unsigned long start, unsigned long end)
+ {
+ void __iomem *base = l2x0_base;
+- unsigned long flags;
+
+- raw_spin_lock_irqsave(&l2x0_lock, flags);
+ if (start & (CACHE_LINE_SIZE - 1)) {
+ start &= ~(CACHE_LINE_SIZE - 1);
+- debug_writel(0x03);
+- l2x0_flush_line(start);
+- debug_writel(0x00);
++ writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
+ start += CACHE_LINE_SIZE;
+ }
+
+ if (end & (CACHE_LINE_SIZE - 1)) {
+ end &= ~(CACHE_LINE_SIZE - 1);
+- debug_writel(0x03);
+- l2x0_flush_line(end);
+- debug_writel(0x00);
++ writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
+ }
+
++ __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
++ __l2c210_cache_sync(base);
++}
++
++static void l2c210_clean_range(unsigned long start, unsigned long end)
++{
++ void __iomem *base = l2x0_base;
++
++ start &= ~(CACHE_LINE_SIZE - 1);
++ __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end);
++ __l2c210_cache_sync(base);
++}
++
++static void l2c210_flush_range(unsigned long start, unsigned long end)
++{
++ void __iomem *base = l2x0_base;
++
++ start &= ~(CACHE_LINE_SIZE - 1);
++ __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end);
++ __l2c210_cache_sync(base);
++}
++
++static void l2c210_flush_all(void)
++{
++ void __iomem *base = l2x0_base;
++
++ BUG_ON(!irqs_disabled());
++
++ __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
++ __l2c210_cache_sync(base);
++}
++
++static void l2c210_sync(void)
++{
++ __l2c210_cache_sync(l2x0_base);
++}
++
++static void l2c210_resume(void)
++{
++ void __iomem *base = l2x0_base;
++
++ if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
++ l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
++}
++
++static const struct l2c_init_data l2c210_data __initconst = {
++ .type = "L2C-210",
++ .way_size_0 = SZ_8K,
++ .num_lock = 1,
++ .enable = l2c_enable,
++ .outer_cache = {
++ .inv_range = l2c210_inv_range,
++ .clean_range = l2c210_clean_range,
++ .flush_range = l2c210_flush_range,
++ .flush_all = l2c210_flush_all,
++ .disable = l2c_disable,
++ .sync = l2c210_sync,
++ .resume = l2c210_resume,
++ },
++};
++
++/*
++ * L2C-220 specific code.
++ *
++ * All operations are background operations: they have to be waited for.
++ * Conflicting requests generate a slave error (which will cause an
++ * imprecise abort.) Never uses sync_reg_offset, so we hard-code the
++ * sync register here.
++ *
++ * However, we can re-use the l2c210_resume call.
++ */
++static inline void __l2c220_cache_sync(void __iomem *base)
++{
++ writel_relaxed(0, base + L2X0_CACHE_SYNC);
++ l2c_wait_mask(base + L2X0_CACHE_SYNC, 1);
++}
++
++static void l2c220_op_way(void __iomem *base, unsigned reg)
++{
++ unsigned long flags;
++
++ raw_spin_lock_irqsave(&l2x0_lock, flags);
++ __l2c_op_way(base + reg);
++ __l2c220_cache_sync(base);
++ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++}
++
++static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
++ unsigned long end, unsigned long flags)
++{
++ raw_spinlock_t *lock = &l2x0_lock;
++
+ while (start < end) {
+ unsigned long blk_end = start + min(end - start, 4096UL);
+
+ while (start < blk_end) {
+- l2x0_inv_line(start);
++ l2c_wait_mask(reg, 1);
++ writel_relaxed(start, reg);
+ start += CACHE_LINE_SIZE;
+ }
+
+ if (blk_end < end) {
+- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+- raw_spin_lock_irqsave(&l2x0_lock, flags);
++ raw_spin_unlock_irqrestore(lock, flags);
++ raw_spin_lock_irqsave(lock, flags);
+ }
+ }
+- cache_wait(base + L2X0_INV_LINE_PA, 1);
+- cache_sync();
+- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++
++ return flags;
+ }
+
+-static void l2x0_clean_range(unsigned long start, unsigned long end)
++static void l2c220_inv_range(unsigned long start, unsigned long end)
+ {
+ void __iomem *base = l2x0_base;
+ unsigned long flags;
+
+- if ((end - start) >= l2x0_size) {
+- l2x0_clean_all();
+- return;
+- }
+-
+ raw_spin_lock_irqsave(&l2x0_lock, flags);
+- start &= ~(CACHE_LINE_SIZE - 1);
+- while (start < end) {
+- unsigned long blk_end = start + min(end - start, 4096UL);
+-
+- while (start < blk_end) {
+- l2x0_clean_line(start);
++ if ((start | end) & (CACHE_LINE_SIZE - 1)) {
++ if (start & (CACHE_LINE_SIZE - 1)) {
++ start &= ~(CACHE_LINE_SIZE - 1);
++ writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
+ start += CACHE_LINE_SIZE;
+ }
+
+- if (blk_end < end) {
+- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+- raw_spin_lock_irqsave(&l2x0_lock, flags);
++ if (end & (CACHE_LINE_SIZE - 1)) {
++ end &= ~(CACHE_LINE_SIZE - 1);
++ l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
++ writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
+ }
+ }
+- cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+- cache_sync();
++
++ flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA,
++ start, end, flags);
++ l2c_wait_mask(base + L2X0_INV_LINE_PA, 1);
++ __l2c220_cache_sync(base);
+ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ }
+
+-static void l2x0_flush_range(unsigned long start, unsigned long end)
++static void l2c220_clean_range(unsigned long start, unsigned long end)
+ {
+ void __iomem *base = l2x0_base;
+ unsigned long flags;
+
++ start &= ~(CACHE_LINE_SIZE - 1);
+ if ((end - start) >= l2x0_size) {
+- l2x0_flush_all();
++ l2c220_op_way(base, L2X0_CLEAN_WAY);
+ return;
+ }
+
+ raw_spin_lock_irqsave(&l2x0_lock, flags);
++ flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA,
++ start, end, flags);
++ l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
++ __l2c220_cache_sync(base);
++ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++}
++
++static void l2c220_flush_range(unsigned long start, unsigned long end)
++{
++ void __iomem *base = l2x0_base;
++ unsigned long flags;
++
+ start &= ~(CACHE_LINE_SIZE - 1);
++ if ((end - start) >= l2x0_size) {
++ l2c220_op_way(base, L2X0_CLEAN_INV_WAY);
++ return;
++ }
++
++ raw_spin_lock_irqsave(&l2x0_lock, flags);
++ flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA,
++ start, end, flags);
++ l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
++ __l2c220_cache_sync(base);
++ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++}
++
++static void l2c220_flush_all(void)
++{
++ l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY);
++}
++
++static void l2c220_sync(void)
++{
++ unsigned long flags;
++
++ raw_spin_lock_irqsave(&l2x0_lock, flags);
++ __l2c220_cache_sync(l2x0_base);
++ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++}
++
++static const struct l2c_init_data l2c220_data = {
++ .type = "L2C-220",
++ .way_size_0 = SZ_8K,
++ .num_lock = 1,
++ .enable = l2c_enable,
++ .outer_cache = {
++ .inv_range = l2c220_inv_range,
++ .clean_range = l2c220_clean_range,
++ .flush_range = l2c220_flush_range,
++ .flush_all = l2c220_flush_all,
++ .disable = l2c_disable,
++ .sync = l2c220_sync,
++ .resume = l2c210_resume,
++ },
++};
++
++/*
++ * L2C-310 specific code.
++ *
++ * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
++ * and the way operations are all background tasks. However, issuing an
++ * operation while a background operation is in progress results in a
++ * SLVERR response. We can reuse:
++ *
++ * __l2c210_cache_sync (using sync_reg_offset)
++ * l2c210_sync
++ * l2c210_inv_range (if 588369 is not applicable)
++ * l2c210_clean_range
++ * l2c210_flush_range (if 588369 is not applicable)
++ * l2c210_flush_all (if 727915 is not applicable)
++ *
++ * Errata:
++ * 588369: PL310 R0P0->R1P0, fixed R2P0.
++ * Affects: all clean+invalidate operations
++ * clean and invalidate skips the invalidate step, so we need to issue
++ * separate operations. We also require the above debug workaround
++ * enclosing this code fragment on affected parts. On unaffected parts,
++ * we must not use this workaround without the debug register writes
++ * to avoid exposing a problem similar to 727915.
++ *
++ * 727915: PL310 R2P0->R3P0, fixed R3P1.
++ * Affects: clean+invalidate by way
++ * clean and invalidate by way runs in the background, and a store can
++ * hit the line between the clean operation and invalidate operation,
++ * resulting in the store being lost.
++ *
++ * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
++ * Affects: 8x64-bit (double fill) line fetches
++ * double fill line fetches can fail to cause dirty data to be evicted
++ * from the cache before the new data overwrites the second line.
++ *
++ * 753970: PL310 R3P0, fixed R3P1.
++ * Affects: sync
++ * prevents merging writes after the sync operation, until another L2C
++ * operation is performed (or a number of other conditions.)
++ *
++ * 769419: PL310 R0P0->R3P1, fixed R3P2.
++ * Affects: store buffer
++ * store buffer is not automatically drained.
++ */
++static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
++{
++ void __iomem *base = l2x0_base;
++
++ if ((start | end) & (CACHE_LINE_SIZE - 1)) {
++ unsigned long flags;
++
++ /* Erratum 588369 for both clean+invalidate operations */
++ raw_spin_lock_irqsave(&l2x0_lock, flags);
++ l2c_set_debug(base, 0x03);
++
++ if (start & (CACHE_LINE_SIZE - 1)) {
++ start &= ~(CACHE_LINE_SIZE - 1);
++ writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
++ writel_relaxed(start, base + L2X0_INV_LINE_PA);
++ start += CACHE_LINE_SIZE;
++ }
++
++ if (end & (CACHE_LINE_SIZE - 1)) {
++ end &= ~(CACHE_LINE_SIZE - 1);
++ writel_relaxed(end, base + L2X0_CLEAN_LINE_PA);
++ writel_relaxed(end, base + L2X0_INV_LINE_PA);
++ }
++
++ l2c_set_debug(base, 0x00);
++ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++ }
++
++ __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
++ __l2c210_cache_sync(base);
++}
++
++static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
++{
++ raw_spinlock_t *lock = &l2x0_lock;
++ unsigned long flags;
++ void __iomem *base = l2x0_base;
++
++ raw_spin_lock_irqsave(lock, flags);
+ while (start < end) {
+ unsigned long blk_end = start + min(end - start, 4096UL);
+
+- debug_writel(0x03);
++ l2c_set_debug(base, 0x03);
+ while (start < blk_end) {
+- l2x0_flush_line(start);
++ writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
++ writel_relaxed(start, base + L2X0_INV_LINE_PA);
+ start += CACHE_LINE_SIZE;
+ }
+- debug_writel(0x00);
++ l2c_set_debug(base, 0x00);
+
+ if (blk_end < end) {
+- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+- raw_spin_lock_irqsave(&l2x0_lock, flags);
++ raw_spin_unlock_irqrestore(lock, flags);
++ raw_spin_lock_irqsave(lock, flags);
+ }
+ }
+- cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+- cache_sync();
+- raw_spin_unlock_irqrestore(&l2x0_lock, flags);
++ raw_spin_unlock_irqrestore(lock, flags);
++ __l2c210_cache_sync(base);
+ }
+
+-static void l2x0_disable(void)
++static void l2c310_flush_all_erratum(void)
+ {
++ void __iomem *base = l2x0_base;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&l2x0_lock, flags);
+- __l2x0_flush_all();
+- writel_relaxed(0, l2x0_base + L2X0_CTRL);
+- dsb(st);
++ l2c_set_debug(base, 0x03);
++ __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
++ l2c_set_debug(base, 0x00);
++ __l2c210_cache_sync(base);
+ raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ }
+
+-static void l2x0_unlock(u32 cache_id)
++static void __init l2c310_save(void __iomem *base)
+ {
+- int lockregs;
+- int i;
++ unsigned revision;
+
+- switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+- case L2X0_CACHE_ID_PART_L310:
+- lockregs = 8;
+- break;
+- case AURORA_CACHE_ID:
+- lockregs = 4;
+- break;
+- default:
+- /* L210 and unknown types */
+- lockregs = 1;
+- break;
++ l2x0_saved_regs.tag_latency = readl_relaxed(base +
++ L310_TAG_LATENCY_CTRL);
++ l2x0_saved_regs.data_latency = readl_relaxed(base +
++ L310_DATA_LATENCY_CTRL);
++ l2x0_saved_regs.filter_end = readl_relaxed(base +
++ L310_ADDR_FILTER_END);
++ l2x0_saved_regs.filter_start = readl_relaxed(base +
++ L310_ADDR_FILTER_START);
++
++ revision = readl_relaxed(base + L2X0_CACHE_ID) &
++ L2X0_CACHE_ID_RTL_MASK;
++
++ /* From r2p0, there is Prefetch offset/control register */
++ if (revision >= L310_CACHE_ID_RTL_R2P0)
++ l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
++ L310_PREFETCH_CTRL);
++
++ /* From r3p0, there is Power control register */
++ if (revision >= L310_CACHE_ID_RTL_R3P0)
++ l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
++ L310_POWER_CTRL);
++}
++
++static void l2c310_resume(void)
++{
++ void __iomem *base = l2x0_base;
++
++ if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
++ unsigned revision;
++
++ /* restore pl310 setup */
++ writel_relaxed(l2x0_saved_regs.tag_latency,
++ base + L310_TAG_LATENCY_CTRL);
++ writel_relaxed(l2x0_saved_regs.data_latency,
++ base + L310_DATA_LATENCY_CTRL);
++ writel_relaxed(l2x0_saved_regs.filter_end,
++ base + L310_ADDR_FILTER_END);
++ writel_relaxed(l2x0_saved_regs.filter_start,
++ base + L310_ADDR_FILTER_START);
++
++ revision = readl_relaxed(base + L2X0_CACHE_ID) &
++ L2X0_CACHE_ID_RTL_MASK;
++
++ if (revision >= L310_CACHE_ID_RTL_R2P0)
++ l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
++ L310_PREFETCH_CTRL);
++ if (revision >= L310_CACHE_ID_RTL_R3P0)
++ l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
++ L310_POWER_CTRL);
++
++ l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
+ }
++}
+
+- for (i = 0; i < lockregs; i++) {
+- writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
+- i * L2X0_LOCKDOWN_STRIDE);
+- writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
+- i * L2X0_LOCKDOWN_STRIDE);
++static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
++{
++ unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK;
++ bool cortex_a9 = read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
++
++ if (rev >= L310_CACHE_ID_RTL_R2P0) {
++ if (cortex_a9) {
++ aux |= L310_AUX_CTRL_EARLY_BRESP;
++ pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
++ } else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
++ pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n");
++ aux &= ~L310_AUX_CTRL_EARLY_BRESP;
++ }
+ }
++
++ l2c_enable(base, aux, num_lock);
+ }
+
+-void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
++static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
++ struct outer_cache_fns *fns)
+ {
+- u32 aux;
+- u32 cache_id;
+- u32 way_size = 0;
+- int ways;
+- int way_size_shift = L2X0_WAY_SIZE_SHIFT;
+- const char *type;
++ unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK;
++ const char *errata[8];
++ unsigned n = 0;
++
++ if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) &&
++ revision < L310_CACHE_ID_RTL_R2P0 &&
++ /* For bcm compatibility */
++ fns->inv_range == l2c210_inv_range) {
++ fns->inv_range = l2c310_inv_range_erratum;
++ fns->flush_range = l2c310_flush_range_erratum;
++ errata[n++] = "588369";
++ }
++
++ if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) &&
++ revision >= L310_CACHE_ID_RTL_R2P0 &&
++ revision < L310_CACHE_ID_RTL_R3P1) {
++ fns->flush_all = l2c310_flush_all_erratum;
++ errata[n++] = "727915";
++ }
++
++ if (revision >= L310_CACHE_ID_RTL_R3P0 &&
++ revision < L310_CACHE_ID_RTL_R3P2) {
++ u32 val = readl_relaxed(base + L310_PREFETCH_CTRL);
++ /* I don't think bit23 is required here... but iMX6 does so */
++ if (val & (BIT(30) | BIT(23))) {
++ val &= ~(BIT(30) | BIT(23));
++ l2c_write_sec(val, base, L310_PREFETCH_CTRL);
++ errata[n++] = "752271";
++ }
++ }
+
+- l2x0_base = base;
+- if (cache_id_part_number_from_dt)
+- cache_id = cache_id_part_number_from_dt;
+- else
+- cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+- aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
++ if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) &&
++ revision == L310_CACHE_ID_RTL_R3P0) {
++ sync_reg_offset = L2X0_DUMMY_REG;
++ errata[n++] = "753970";
++ }
++
++ if (IS_ENABLED(CONFIG_PL310_ERRATA_769419))
++ errata[n++] = "769419";
++
++ if (n) {
++ unsigned i;
++
++ pr_info("L2C-310 errat%s", n > 1 ? "a" : "um");
++ for (i = 0; i < n; i++)
++ pr_cont(" %s", errata[i]);
++ pr_cont(" enabled\n");
++ }
++}
++
++static const struct l2c_init_data l2c310_init_fns __initconst = {
++ .type = "L2C-310",
++ .way_size_0 = SZ_8K,
++ .num_lock = 8,
++ .enable = l2c310_enable,
++ .fixup = l2c310_fixup,
++ .save = l2c310_save,
++ .outer_cache = {
++ .inv_range = l2c210_inv_range,
++ .clean_range = l2c210_clean_range,
++ .flush_range = l2c210_flush_range,
++ .flush_all = l2c210_flush_all,
++ .disable = l2c_disable,
++ .sync = l2c210_sync,
++ .resume = l2c310_resume,
++ },
++};
++
++static void __init __l2c_init(const struct l2c_init_data *data,
++ u32 aux_val, u32 aux_mask, u32 cache_id)
++{
++ struct outer_cache_fns fns;
++ unsigned way_size_bits, ways;
++ u32 aux, old_aux;
++
++ /*
++ * Sanity check the aux values. aux_mask is the bits we preserve
++ * from reading the hardware register, and aux_val is the bits we
++ * set.
++ */
++ if (aux_val & aux_mask)
++ pr_alert("L2C: platform provided aux values permit register corruption.\n");
+
++ /*
++ * It is strange to save the register state before initialisation,
++ * but hey, this is what the DT implementations decided to do.
++ */
++ if (data->save)
++ data->save(l2x0_base);
++
++ old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+ aux &= aux_mask;
+ aux |= aux_val;
+
++ if (old_aux != aux)
++ pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n",
++ old_aux, aux);
++
+ /* Determine the number of ways */
+ switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+ case L2X0_CACHE_ID_PART_L310:
++ if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16))
++ pr_warn("L2C: DT/platform tries to modify or specify cache size\n");
+ if (aux & (1 << 16))
+ ways = 16;
+ else
+ ways = 8;
+- type = "L310";
+-#ifdef CONFIG_PL310_ERRATA_753970
+- /* Unmapped register. */
+- sync_reg_offset = L2X0_DUMMY_REG;
+-#endif
+- if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
+- outer_cache.set_debug = pl310_set_debug;
+ break;
++
+ case L2X0_CACHE_ID_PART_L210:
++ case L2X0_CACHE_ID_PART_L220:
+ ways = (aux >> 13) & 0xf;
+- type = "L210";
+ break;
+
+ case AURORA_CACHE_ID:
+- sync_reg_offset = AURORA_SYNC_REG;
+ ways = (aux >> 13) & 0xf;
+ ways = 2 << ((ways + 1) >> 2);
+- way_size_shift = AURORA_WAY_SIZE_SHIFT;
+- type = "Aurora";
+ break;
++
+ default:
+ /* Assume unknown chips have 8 ways */
+ ways = 8;
+- type = "L2x0 series";
+ break;
+ }
+
+ l2x0_way_mask = (1 << ways) - 1;
+
+ /*
+- * L2 cache Size = Way size * Number of ways
++ * way_size_0 is the size that a way_size value of zero would be
++ * given the calculation: way_size = way_size_0 << way_size_bits.
++ * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k,
++ * then way_size_0 would be 8k.
++ *
++ * L2 cache size = number of ways * way size.
+ */
+- way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
+- way_size = 1 << (way_size + way_size_shift);
+-
+- l2x0_size = ways * way_size * SZ_1K;
++ way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >>
++ L2C_AUX_CTRL_WAY_SIZE_SHIFT;
++ l2x0_size = ways * (data->way_size_0 << way_size_bits);
++
++ fns = data->outer_cache;
++ fns.write_sec = outer_cache.write_sec;
++ if (data->fixup)
++ data->fixup(l2x0_base, cache_id, &fns);
+
+ /*
+- * Check if l2x0 controller is already enabled.
+- * If you are booting from non-secure mode
+- * accessing the below registers will fault.
++ * Check if l2x0 controller is already enabled. If we are booting
++ * in non-secure mode accessing the below registers will fault.
+ */
+- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+- /* Make sure that I&D is not locked down when starting */
+- l2x0_unlock(cache_id);
+-
+- /* l2x0 controller is disabled */
+- writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
+-
+- l2x0_inv_all();
+-
+- /* enable L2X0 */
+- writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
+- }
++ if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
++ data->enable(l2x0_base, aux, data->num_lock);
+
+ /* Re-read it in case some bits are reserved. */
+ aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+@@ -408,23 +799,178 @@
+ /* Save the value for resuming. */
+ l2x0_saved_regs.aux_ctrl = aux;
+
+- if (!of_init) {
+- outer_cache.inv_range = l2x0_inv_range;
+- outer_cache.clean_range = l2x0_clean_range;
+- outer_cache.flush_range = l2x0_flush_range;
+- outer_cache.sync = l2x0_cache_sync;
+- outer_cache.flush_all = l2x0_flush_all;
+- outer_cache.inv_all = l2x0_inv_all;
+- outer_cache.disable = l2x0_disable;
++ outer_cache = fns;
++
++ pr_info("%s cache controller enabled, %d ways, %d kB\n",
++ data->type, ways, l2x0_size >> 10);
++ pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
++ data->type, cache_id, aux);
++}
++
++void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
++{
++ const struct l2c_init_data *data;
++ u32 cache_id;
++
++ l2x0_base = base;
++
++ cache_id = readl_relaxed(base + L2X0_CACHE_ID);
++
++ switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
++ default:
++ case L2X0_CACHE_ID_PART_L210:
++ data = &l2c210_data;
++ break;
++
++ case L2X0_CACHE_ID_PART_L220:
++ data = &l2c220_data;
++ break;
++
++ case L2X0_CACHE_ID_PART_L310:
++ data = &l2c310_init_fns;
++ break;
+ }
+
+- pr_info("%s cache controller enabled\n", type);
+- pr_info("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d kB\n",
+- ways, cache_id, aux, l2x0_size >> 10);
++ __l2c_init(data, aux_val, aux_mask, cache_id);
+ }
+
+-#ifdef CONFIG_OF
+-static int l2_wt_override;
++#ifdef CONFIG_OF
++static int l2_wt_override;
++
++/* Aurora don't have the cache ID register available, so we have to
++ * pass it though the device tree */
++static u32 cache_id_part_number_from_dt;
++
++static void __init l2x0_of_parse(const struct device_node *np,
++ u32 *aux_val, u32 *aux_mask)
++{
++ u32 data[2] = { 0, 0 };
++ u32 tag = 0;
++ u32 dirty = 0;
++ u32 val = 0, mask = 0;
++
++ of_property_read_u32(np, "arm,tag-latency", &tag);
++ if (tag) {
++ mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
++ val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
++ }
++
++ of_property_read_u32_array(np, "arm,data-latency",
++ data, ARRAY_SIZE(data));
++ if (data[0] && data[1]) {
++ mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
++ L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
++ val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
++ ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
++ }
++
++ of_property_read_u32(np, "arm,dirty-latency", &dirty);
++ if (dirty) {
++ mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
++ val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
++ }
++
++ *aux_val &= ~mask;
++ *aux_val |= val;
++ *aux_mask &= ~mask;
++}
++
++static const struct l2c_init_data of_l2c210_data __initconst = {
++ .type = "L2C-210",
++ .way_size_0 = SZ_8K,
++ .num_lock = 1,
++ .of_parse = l2x0_of_parse,
++ .enable = l2c_enable,
++ .outer_cache = {
++ .inv_range = l2c210_inv_range,
++ .clean_range = l2c210_clean_range,
++ .flush_range = l2c210_flush_range,
++ .flush_all = l2c210_flush_all,
++ .disable = l2c_disable,
++ .sync = l2c210_sync,
++ .resume = l2c210_resume,
++ },
++};
++
++static const struct l2c_init_data of_l2c220_data __initconst = {
++ .type = "L2C-220",
++ .way_size_0 = SZ_8K,
++ .num_lock = 1,
++ .of_parse = l2x0_of_parse,
++ .enable = l2c_enable,
++ .outer_cache = {
++ .inv_range = l2c220_inv_range,
++ .clean_range = l2c220_clean_range,
++ .flush_range = l2c220_flush_range,
++ .flush_all = l2c220_flush_all,
++ .disable = l2c_disable,
++ .sync = l2c220_sync,
++ .resume = l2c210_resume,
++ },
++};
++
++static void __init l2c310_of_parse(const struct device_node *np,
++ u32 *aux_val, u32 *aux_mask)
++{
++ u32 data[3] = { 0, 0, 0 };
++ u32 tag[3] = { 0, 0, 0 };
++ u32 filter[2] = { 0, 0 };
++ u32 val;
++
++ of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
++ if (tag[0] && tag[1] && tag[2])
++ writel_relaxed(
++ L310_LATENCY_CTRL_RD(tag[0] - 1) |
++ L310_LATENCY_CTRL_WR(tag[1] - 1) |
++ L310_LATENCY_CTRL_SETUP(tag[2] - 1),
++ l2x0_base + L310_TAG_LATENCY_CTRL);
++
++ of_property_read_u32_array(np, "arm,data-latency",
++ data, ARRAY_SIZE(data));
++ if (data[0] && data[1] && data[2])
++ writel_relaxed(
++ L310_LATENCY_CTRL_RD(data[0] - 1) |
++ L310_LATENCY_CTRL_WR(data[1] - 1) |
++ L310_LATENCY_CTRL_SETUP(data[2] - 1),
++ l2x0_base + L310_DATA_LATENCY_CTRL);
++
++ of_property_read_u32_array(np, "arm,filter-ranges",
++ filter, ARRAY_SIZE(filter));
++ if (filter[1]) {
++ writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
++ l2x0_base + L310_ADDR_FILTER_END);
++ writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
++ l2x0_base + L310_ADDR_FILTER_START);
++ }
++
++ val = 0;
++ if (of_property_read_bool(np, "arm,dynamic-clk-gating"))
++ val |= L310_DYNAMIC_CLK_GATING_EN;
++ if (of_property_read_bool(np, "arm,standby-mode"))
++ val |= L310_STNDBY_MODE_EN;
++
++ if (val)
++ l2c_write_sec(val, l2x0_base, L310_POWER_CTRL);
++}
++
++static const struct l2c_init_data of_l2c310_data __initconst = {
++ .type = "L2C-310",
++ .way_size_0 = SZ_8K,
++ .num_lock = 8,
++ .of_parse = l2c310_of_parse,
++ .enable = l2c310_enable,
++ .fixup = l2c310_fixup,
++ .save = l2c310_save,
++ .outer_cache = {
++ .inv_range = l2c210_inv_range,
++ .clean_range = l2c210_clean_range,
++ .flush_range = l2c210_flush_range,
++ .flush_all = l2c210_flush_all,
++ .disable = l2c_disable,
++ .sync = l2c210_sync,
++ .resume = l2c310_resume,
++ },
++};
+
+ /*
+ * Note that the end addresses passed to Linux primitives are
+@@ -524,6 +1070,100 @@
+ }
+ }
+
++static void aurora_save(void __iomem *base)
++{
++ l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
++ l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
++}
++
++static void aurora_resume(void)
++{
++ void __iomem *base = l2x0_base;
++
++ if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
++ writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL);
++ writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL);
++ }
++}
++
++/*
++ * For Aurora cache in no outer mode, enable via the CP15 coprocessor
++ * broadcasting of cache commands to L2.
++ */
++static void __init aurora_enable_no_outer(void __iomem *base, u32 aux,
++ unsigned num_lock)
++{
++ u32 u;
++
++ asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
++ u |= AURORA_CTRL_FW; /* Set the FW bit */
++ asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
++
++ isb();
++
++ l2c_enable(base, aux, num_lock);
++}
++
++static void __init aurora_fixup(void __iomem *base, u32 cache_id,
++ struct outer_cache_fns *fns)
++{
++ sync_reg_offset = AURORA_SYNC_REG;
++}
++
++static void __init aurora_of_parse(const struct device_node *np,
++ u32 *aux_val, u32 *aux_mask)
++{
++ u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
++ u32 mask = AURORA_ACR_REPLACEMENT_MASK;
++
++ of_property_read_u32(np, "cache-id-part",
++ &cache_id_part_number_from_dt);
++
++ /* Determine and save the write policy */
++ l2_wt_override = of_property_read_bool(np, "wt-override");
++
++ if (l2_wt_override) {
++ val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
++ mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
++ }
++
++ *aux_val &= ~mask;
++ *aux_val |= val;
++ *aux_mask &= ~mask;
++}
++
++static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
++ .type = "Aurora",
++ .way_size_0 = SZ_4K,
++ .num_lock = 4,
++ .of_parse = aurora_of_parse,
++ .enable = l2c_enable,
++ .fixup = aurora_fixup,
++ .save = aurora_save,
++ .outer_cache = {
++ .inv_range = aurora_inv_range,
++ .clean_range = aurora_clean_range,
++ .flush_range = aurora_flush_range,
++ .flush_all = l2x0_flush_all,
++ .disable = l2x0_disable,
++ .sync = l2x0_cache_sync,
++ .resume = aurora_resume,
++ },
++};
++
++static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
++ .type = "Aurora",
++ .way_size_0 = SZ_4K,
++ .num_lock = 4,
++ .of_parse = aurora_of_parse,
++ .enable = aurora_enable_no_outer,
++ .fixup = aurora_fixup,
++ .save = aurora_save,
++ .outer_cache = {
++ .resume = aurora_resume,
++ },
++};
++
+ /*
+ * For certain Broadcom SoCs, depending on the address range, different offsets
+ * need to be added to the address before passing it to L2 for
+@@ -588,16 +1228,16 @@
+
+ /* normal case, no cross section between start and end */
+ if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+- l2x0_inv_range(new_start, new_end);
++ l2c210_inv_range(new_start, new_end);
+ return;
+ }
+
+ /* They cross sections, so it can only be a cross from section
+ * 2 to section 3
+ */
+- l2x0_inv_range(new_start,
++ l2c210_inv_range(new_start,
+ bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+- l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
++ l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+ new_end);
+ }
+
+@@ -610,26 +1250,21 @@
+ if (unlikely(end <= start))
+ return;
+
+- if ((end - start) >= l2x0_size) {
+- l2x0_clean_all();
+- return;
+- }
+-
+ new_start = bcm_l2_phys_addr(start);
+ new_end = bcm_l2_phys_addr(end);
+
+ /* normal case, no cross section between start and end */
+ if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+- l2x0_clean_range(new_start, new_end);
++ l2c210_clean_range(new_start, new_end);
+ return;
+ }
+
+ /* They cross sections, so it can only be a cross from section
+ * 2 to section 3
+ */
+- l2x0_clean_range(new_start,
++ l2c210_clean_range(new_start,
+ bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+- l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
++ l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+ new_end);
+ }
+
+@@ -643,7 +1278,7 @@
+ return;
+
+ if ((end - start) >= l2x0_size) {
+- l2x0_flush_all();
++ outer_cache.flush_all();
+ return;
+ }
+
+@@ -652,283 +1287,65 @@
+
+ /* normal case, no cross section between start and end */
+ if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+- l2x0_flush_range(new_start, new_end);
++ l2c210_flush_range(new_start, new_end);
+ return;
+ }
+
+ /* They cross sections, so it can only be a cross from section
+ * 2 to section 3
+ */
+- l2x0_flush_range(new_start,
++ l2c210_flush_range(new_start,
+ bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+- l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
++ l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+ new_end);
+ }
+
+-static void __init l2x0_of_setup(const struct device_node *np,
+- u32 *aux_val, u32 *aux_mask)
+-{
+- u32 data[2] = { 0, 0 };
+- u32 tag = 0;
+- u32 dirty = 0;
+- u32 val = 0, mask = 0;
+-
+- of_property_read_u32(np, "arm,tag-latency", &tag);
+- if (tag) {
+- mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
+- val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
+- }
+-
+- of_property_read_u32_array(np, "arm,data-latency",
+- data, ARRAY_SIZE(data));
+- if (data[0] && data[1]) {
+- mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
+- L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
+- val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
+- ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
+- }
+-
+- of_property_read_u32(np, "arm,dirty-latency", &dirty);
+- if (dirty) {
+- mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
+- val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
+- }
+-
+- *aux_val &= ~mask;
+- *aux_val |= val;
+- *aux_mask &= ~mask;
+-}
+-
+-static void __init pl310_of_setup(const struct device_node *np,
+- u32 *aux_val, u32 *aux_mask)
+-{
+- u32 data[3] = { 0, 0, 0 };
+- u32 tag[3] = { 0, 0, 0 };
+- u32 filter[2] = { 0, 0 };
+-
+- of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
+- if (tag[0] && tag[1] && tag[2])
+- writel_relaxed(
+- ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
+- ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
+- ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
+- l2x0_base + L2X0_TAG_LATENCY_CTRL);
+-
+- of_property_read_u32_array(np, "arm,data-latency",
+- data, ARRAY_SIZE(data));
+- if (data[0] && data[1] && data[2])
+- writel_relaxed(
+- ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
+- ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
+- ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
+- l2x0_base + L2X0_DATA_LATENCY_CTRL);
+-
+- of_property_read_u32_array(np, "arm,filter-ranges",
+- filter, ARRAY_SIZE(filter));
+- if (filter[1]) {
+- writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
+- l2x0_base + L2X0_ADDR_FILTER_END);
+- writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
+- l2x0_base + L2X0_ADDR_FILTER_START);
+- }
+-}
+-
+-static void __init pl310_save(void)
+-{
+- u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
+- L2X0_CACHE_ID_RTL_MASK;
+-
+- l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
+- L2X0_TAG_LATENCY_CTRL);
+- l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
+- L2X0_DATA_LATENCY_CTRL);
+- l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
+- L2X0_ADDR_FILTER_END);
+- l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
+- L2X0_ADDR_FILTER_START);
+-
+- if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+- /*
+- * From r2p0, there is Prefetch offset/control register
+- */
+- l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
+- L2X0_PREFETCH_CTRL);
+- /*
+- * From r3p0, there is Power control register
+- */
+- if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+- l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
+- L2X0_POWER_CTRL);
+- }
+-}
+-
+-static void aurora_save(void)
+-{
+- l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+- l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+-}
++/* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */
++static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
++ .type = "BCM-L2C-310",
++ .way_size_0 = SZ_8K,
++ .num_lock = 8,
++ .of_parse = l2c310_of_parse,
++ .enable = l2c310_enable,
++ .save = l2c310_save,
++ .outer_cache = {
++ .inv_range = bcm_inv_range,
++ .clean_range = bcm_clean_range,
++ .flush_range = bcm_flush_range,
++ .flush_all = l2c210_flush_all,
++ .disable = l2c_disable,
++ .sync = l2c210_sync,
++ .resume = l2c310_resume,
++ },
++};
+
+-static void __init tauros3_save(void)
++static void __init tauros3_save(void __iomem *base)
+ {
+ l2x0_saved_regs.aux2_ctrl =
+- readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL);
++ readl_relaxed(base + TAUROS3_AUX2_CTRL);
+ l2x0_saved_regs.prefetch_ctrl =
+- readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+-}
+-
+-static void l2x0_resume(void)
+-{
+- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+- /* restore aux ctrl and enable l2 */
+- l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
+-
+- writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
+- L2X0_AUX_CTRL);
+-
+- l2x0_inv_all();
+-
+- writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
+- }
+-}
+-
+-static void pl310_resume(void)
+-{
+- u32 l2x0_revision;
+-
+- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+- /* restore pl310 setup */
+- writel_relaxed(l2x0_saved_regs.tag_latency,
+- l2x0_base + L2X0_TAG_LATENCY_CTRL);
+- writel_relaxed(l2x0_saved_regs.data_latency,
+- l2x0_base + L2X0_DATA_LATENCY_CTRL);
+- writel_relaxed(l2x0_saved_regs.filter_end,
+- l2x0_base + L2X0_ADDR_FILTER_END);
+- writel_relaxed(l2x0_saved_regs.filter_start,
+- l2x0_base + L2X0_ADDR_FILTER_START);
+-
+- l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
+- L2X0_CACHE_ID_RTL_MASK;
+-
+- if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
+- writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+- l2x0_base + L2X0_PREFETCH_CTRL);
+- if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
+- writel_relaxed(l2x0_saved_regs.pwr_ctrl,
+- l2x0_base + L2X0_POWER_CTRL);
+- }
+- }
+-
+- l2x0_resume();
+-}
+-
+-static void aurora_resume(void)
+-{
+- if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+- writel_relaxed(l2x0_saved_regs.aux_ctrl,
+- l2x0_base + L2X0_AUX_CTRL);
+- writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
+- }
++ readl_relaxed(base + L310_PREFETCH_CTRL);
+ }
+
+ static void tauros3_resume(void)
+ {
+- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
++ void __iomem *base = l2x0_base;
++
++ if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+ writel_relaxed(l2x0_saved_regs.aux2_ctrl,
+- l2x0_base + TAUROS3_AUX2_CTRL);
++ base + TAUROS3_AUX2_CTRL);
+ writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
+- l2x0_base + L2X0_PREFETCH_CTRL);
+- }
+-
+- l2x0_resume();
+-}
+-
+-static void __init aurora_broadcast_l2_commands(void)
+-{
+- __u32 u;
+- /* Enable Broadcasting of cache commands to L2*/
+- __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
+- u |= AURORA_CTRL_FW; /* Set the FW bit */
+- __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
+- isb();
+-}
+-
+-static void __init aurora_of_setup(const struct device_node *np,
+- u32 *aux_val, u32 *aux_mask)
+-{
+- u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+- u32 mask = AURORA_ACR_REPLACEMENT_MASK;
++ base + L310_PREFETCH_CTRL);
+
+- of_property_read_u32(np, "cache-id-part",
+- &cache_id_part_number_from_dt);
+-
+- /* Determine and save the write policy */
+- l2_wt_override = of_property_read_bool(np, "wt-override");
+-
+- if (l2_wt_override) {
+- val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+- mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
++ l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
+ }
+-
+- *aux_val &= ~mask;
+- *aux_val |= val;
+- *aux_mask &= ~mask;
+ }
+
+-static const struct l2x0_of_data pl310_data = {
+- .setup = pl310_of_setup,
+- .save = pl310_save,
+- .outer_cache = {
+- .resume = pl310_resume,
+- .inv_range = l2x0_inv_range,
+- .clean_range = l2x0_clean_range,
+- .flush_range = l2x0_flush_range,
+- .sync = l2x0_cache_sync,
+- .flush_all = l2x0_flush_all,
+- .inv_all = l2x0_inv_all,
+- .disable = l2x0_disable,
+- },
+-};
+-
+-static const struct l2x0_of_data l2x0_data = {
+- .setup = l2x0_of_setup,
+- .save = NULL,
+- .outer_cache = {
+- .resume = l2x0_resume,
+- .inv_range = l2x0_inv_range,
+- .clean_range = l2x0_clean_range,
+- .flush_range = l2x0_flush_range,
+- .sync = l2x0_cache_sync,
+- .flush_all = l2x0_flush_all,
+- .inv_all = l2x0_inv_all,
+- .disable = l2x0_disable,
+- },
+-};
+-
+-static const struct l2x0_of_data aurora_with_outer_data = {
+- .setup = aurora_of_setup,
+- .save = aurora_save,
+- .outer_cache = {
+- .resume = aurora_resume,
+- .inv_range = aurora_inv_range,
+- .clean_range = aurora_clean_range,
+- .flush_range = aurora_flush_range,
+- .sync = l2x0_cache_sync,
+- .flush_all = l2x0_flush_all,
+- .inv_all = l2x0_inv_all,
+- .disable = l2x0_disable,
+- },
+-};
+-
+-static const struct l2x0_of_data aurora_no_outer_data = {
+- .setup = aurora_of_setup,
+- .save = aurora_save,
+- .outer_cache = {
+- .resume = aurora_resume,
+- },
+-};
+-
+-static const struct l2x0_of_data tauros3_data = {
+- .setup = NULL,
++static const struct l2c_init_data of_tauros3_data __initconst = {
++ .type = "Tauros3",
++ .way_size_0 = SZ_8K,
++ .num_lock = 8,
++ .enable = l2c_enable,
+ .save = tauros3_save,
+ /* Tauros3 broadcasts L1 cache operations to L2 */
+ .outer_cache = {
+@@ -936,43 +1353,26 @@
+ },
+ };
+
+-static const struct l2x0_of_data bcm_l2x0_data = {
+- .setup = pl310_of_setup,
+- .save = pl310_save,
+- .outer_cache = {
+- .resume = pl310_resume,
+- .inv_range = bcm_inv_range,
+- .clean_range = bcm_clean_range,
+- .flush_range = bcm_flush_range,
+- .sync = l2x0_cache_sync,
+- .flush_all = l2x0_flush_all,
+- .inv_all = l2x0_inv_all,
+- .disable = l2x0_disable,
+- },
+-};
+-
++#define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
+ static const struct of_device_id l2x0_ids[] __initconst = {
+- { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+- { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
+- { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
+- { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
+- .data = (void *)&bcm_l2x0_data},
+- { .compatible = "brcm,bcm11351-a2-pl310-cache",
+- .data = (void *)&bcm_l2x0_data},
+- { .compatible = "marvell,aurora-outer-cache",
+- .data = (void *)&aurora_with_outer_data},
+- { .compatible = "marvell,aurora-system-cache",
+- .data = (void *)&aurora_no_outer_data},
+- { .compatible = "marvell,tauros3-cache",
+- .data = (void *)&tauros3_data },
++ L2C_ID("arm,l210-cache", of_l2c210_data),
++ L2C_ID("arm,l220-cache", of_l2c220_data),
++ L2C_ID("arm,pl310-cache", of_l2c310_data),
++ L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
++ L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data),
++ L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data),
++ L2C_ID("marvell,tauros3-cache", of_tauros3_data),
++ /* Deprecated IDs */
++ L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
+ {}
+ };
+
+ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
+ {
++ const struct l2c_init_data *data;
+ struct device_node *np;
+- const struct l2x0_of_data *data;
+ struct resource res;
++ u32 cache_id, old_aux;
+
+ np = of_find_matching_node(NULL, l2x0_ids);
+ if (!np)
+@@ -989,23 +1389,29 @@
+
+ data = of_match_node(l2x0_ids, np)->data;
+
+- /* L2 configuration can only be changed if the cache is disabled */
+- if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+- if (data->setup)
+- data->setup(np, &aux_val, &aux_mask);
+-
+- /* For aurora cache in no outer mode select the
+- * correct mode using the coprocessor*/
+- if (data == &aurora_no_outer_data)
+- aurora_broadcast_l2_commands();
++ old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
++ if (old_aux != ((old_aux & aux_mask) | aux_val)) {
++ pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n",
++ old_aux, (old_aux & aux_mask) | aux_val);
++ } else if (aux_mask != ~0U && aux_val != 0) {
++ pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n");
+ }
+
+- if (data->save)
+- data->save();
++ /* All L2 caches are unified, so this property should be specified */
++ if (!of_property_read_bool(np, "cache-unified"))
++ pr_err("L2C: device tree omits to specify unified cache\n");
++
++ /* L2 configuration can only be changed if the cache is disabled */
++ if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
++ if (data->of_parse)
++ data->of_parse(np, &aux_val, &aux_mask);
++
++ if (cache_id_part_number_from_dt)
++ cache_id = cache_id_part_number_from_dt;
++ else
++ cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+
+- of_init = true;
+- memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
+- l2x0_init(l2x0_base, aux_val, aux_mask);
++ __l2c_init(data, aux_val, aux_mask, cache_id);
+
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/arch/arm/mm/dma-mapping.c linux-3.14.72/arch/arm/mm/dma-mapping.c
+--- linux-3.14.72.orig/arch/arm/mm/dma-mapping.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mm/dma-mapping.c 2016-06-19 22:11:55.061155987 +0200
+@@ -26,6 +26,7 @@
+ #include <linux/io.h>
+ #include <linux/vmalloc.h>
+ #include <linux/sizes.h>
++#include <linux/cma.h>
+
+ #include <asm/memory.h>
+ #include <asm/highmem.h>
+diff -Nur linux-3.14.72.orig/arch/arm/mm/Kconfig linux-3.14.72/arch/arm/mm/Kconfig
+--- linux-3.14.72.orig/arch/arm/mm/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mm/Kconfig 2016-06-19 22:11:55.061155987 +0200
+@@ -898,6 +898,57 @@
+ This option enables optimisations for the PL310 cache
+ controller.
+
++config PL310_ERRATA_588369
++ bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
++ depends on CACHE_L2X0
++ help
++ The PL310 L2 cache controller implements three types of Clean &
++ Invalidate maintenance operations: by Physical Address
++ (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
++ They are architecturally defined to behave as the execution of a
++ clean operation followed immediately by an invalidate operation,
++ both performing to the same memory location. This functionality
++ is not correctly implemented in PL310 as clean lines are not
++ invalidated as a result of these operations.
++
++config PL310_ERRATA_727915
++ bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
++ depends on CACHE_L2X0
++ help
++ PL310 implements the Clean & Invalidate by Way L2 cache maintenance
++ operation (offset 0x7FC). This operation runs in background so that
++ PL310 can handle normal accesses while it is in progress. Under very
++ rare circumstances, due to this erratum, write data can be lost when
++ PL310 treats a cacheable write transaction during a Clean &
++ Invalidate by Way operation.
++
++config PL310_ERRATA_753970
++ bool "PL310 errata: cache sync operation may be faulty"
++ depends on CACHE_PL310
++ help
++ This option enables the workaround for the 753970 PL310 (r3p0) erratum.
++
++ Under some condition the effect of cache sync operation on
++ the store buffer still remains when the operation completes.
++ This means that the store buffer is always asked to drain and
++ this prevents it from merging any further writes. The workaround
++ is to replace the normal offset of cache sync operation (0x730)
++ by another offset targeting an unmapped PL310 register 0x740.
++ This has the same effect as the cache sync operation: store buffer
++ drain and waiting for all buffers empty.
++
++config PL310_ERRATA_769419
++ bool "PL310 errata: no automatic Store Buffer drain"
++ depends on CACHE_L2X0
++ help
++ On revisions of the PL310 prior to r3p2, the Store Buffer does
++ not automatically drain. This can cause normal, non-cacheable
++ writes to be retained when the memory system is idle, leading
++ to suboptimal I/O performance for drivers using coherent DMA.
++ This option adds a write barrier to the cpu_idle loop so that,
++ on systems with an outer cache, the store buffer is drained
++ explicitly.
++
+ config CACHE_TAUROS2
+ bool "Enable the Tauros2 L2 cache controller"
+ depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
+diff -Nur linux-3.14.72.orig/arch/arm/mm/l2c-common.c linux-3.14.72/arch/arm/mm/l2c-common.c
+--- linux-3.14.72.orig/arch/arm/mm/l2c-common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/arch/arm/mm/l2c-common.c 2016-06-19 22:11:55.061155987 +0200
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (C) 2010 ARM Ltd.
++ * Written by Catalin Marinas <catalin.marinas@arm.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++#include <linux/bug.h>
++#include <linux/smp.h>
++#include <asm/outercache.h>
++
++void outer_disable(void)
++{
++ WARN_ON(!irqs_disabled());
++ WARN_ON(num_online_cpus() > 1);
++
++ if (outer_cache.disable)
++ outer_cache.disable();
++}
+diff -Nur linux-3.14.72.orig/arch/arm/mm/Makefile linux-3.14.72/arch/arm/mm/Makefile
+--- linux-3.14.72.orig/arch/arm/mm/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mm/Makefile 2016-06-19 22:11:55.061155987 +0200
+@@ -95,6 +95,7 @@
+ AFLAGS_proc-v6.o :=-Wa,-march=armv6
+ AFLAGS_proc-v7.o :=-Wa,-march=armv7-a
+
++obj-$(CONFIG_OUTER_CACHE) += l2c-common.o
+ obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
+ obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
+ obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o
+diff -Nur linux-3.14.72.orig/arch/arm/mm/proc-v7.S linux-3.14.72/arch/arm/mm/proc-v7.S
+--- linux-3.14.72.orig/arch/arm/mm/proc-v7.S 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/arm/mm/proc-v7.S 2016-06-19 22:11:55.061155987 +0200
+@@ -152,6 +152,40 @@
+ ENDPROC(cpu_v7_do_resume)
+ #endif
+
++/*
++ * Cortex-A9 processor functions
++ */
++ globl_equ cpu_ca9mp_proc_init, cpu_v7_proc_init
++ globl_equ cpu_ca9mp_proc_fin, cpu_v7_proc_fin
++ globl_equ cpu_ca9mp_reset, cpu_v7_reset
++ globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
++ globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
++ globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
++ globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
++.globl cpu_ca9mp_suspend_size
++.equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
++#ifdef CONFIG_ARM_CPU_SUSPEND
++ENTRY(cpu_ca9mp_do_suspend)
++ stmfd sp!, {r4 - r5}
++ mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
++ mrc p15, 0, r5, c15, c0, 0 @ Power register
++ stmia r0!, {r4 - r5}
++ ldmfd sp!, {r4 - r5}
++ b cpu_v7_do_suspend
++ENDPROC(cpu_ca9mp_do_suspend)
++
++ENTRY(cpu_ca9mp_do_resume)
++ ldmia r0!, {r4 - r5}
++ mrc p15, 0, r10, c15, c0, 1 @ Read Diagnostic register
++ teq r4, r10 @ Already restored?
++ mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
++ mrc p15, 0, r10, c15, c0, 0 @ Read Power register
++ teq r5, r10 @ Already restored?
++ mcrne p15, 0, r5, c15, c0, 0 @ No, so restore it
++ b cpu_v7_do_resume
++ENDPROC(cpu_ca9mp_do_resume)
++#endif
++
+ #ifdef CONFIG_CPU_PJ4B
+ globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
+ globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
+@@ -392,6 +426,7 @@
+
+ @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
+ define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
++ define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
+ #ifdef CONFIG_CPU_PJ4B
+ define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
+ #endif
+@@ -444,7 +479,7 @@
+ __v7_ca9mp_proc_info:
+ .long 0x410fc090
+ .long 0xff0ffff0
+- __v7_proc __v7_ca9mp_setup
++ __v7_proc __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
+ .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
+
+ #endif /* CONFIG_ARM_LPAE */
+diff -Nur linux-3.14.72.orig/arch/x86/include/asm/idle.h linux-3.14.72/arch/x86/include/asm/idle.h
+--- linux-3.14.72.orig/arch/x86/include/asm/idle.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/x86/include/asm/idle.h 2016-06-19 22:11:55.061155987 +0200
+@@ -1,13 +1,6 @@
+ #ifndef _ASM_X86_IDLE_H
+ #define _ASM_X86_IDLE_H
+
+-#define IDLE_START 1
+-#define IDLE_END 2
+-
+-struct notifier_block;
+-void idle_notifier_register(struct notifier_block *n);
+-void idle_notifier_unregister(struct notifier_block *n);
+-
+ #ifdef CONFIG_X86_64
+ void enter_idle(void);
+ void exit_idle(void);
+diff -Nur linux-3.14.72.orig/arch/x86/kernel/process.c linux-3.14.72/arch/x86/kernel/process.c
+--- linux-3.14.72.orig/arch/x86/kernel/process.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/x86/kernel/process.c 2016-06-19 22:11:55.061155987 +0200
+@@ -41,19 +41,6 @@
+
+ #ifdef CONFIG_X86_64
+ static DEFINE_PER_CPU(unsigned char, is_idle);
+-static ATOMIC_NOTIFIER_HEAD(idle_notifier);
+-
+-void idle_notifier_register(struct notifier_block *n)
+-{
+- atomic_notifier_chain_register(&idle_notifier, n);
+-}
+-EXPORT_SYMBOL_GPL(idle_notifier_register);
+-
+-void idle_notifier_unregister(struct notifier_block *n)
+-{
+- atomic_notifier_chain_unregister(&idle_notifier, n);
+-}
+-EXPORT_SYMBOL_GPL(idle_notifier_unregister);
+ #endif
+
+ struct kmem_cache *task_xstate_cachep;
+@@ -258,14 +245,14 @@
+ void enter_idle(void)
+ {
+ this_cpu_write(is_idle, 1);
+- atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
++ idle_notifier_call_chain(IDLE_START);
+ }
+
+ static void __exit_idle(void)
+ {
+ if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
+ return;
+- atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
++ idle_notifier_call_chain(IDLE_END);
+ }
+
+ /* Called from interrupts to signify idle end */
+diff -Nur linux-3.14.72.orig/arch/x86/kernel/setup.c linux-3.14.72/arch/x86/kernel/setup.c
+--- linux-3.14.72.orig/arch/x86/kernel/setup.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/arch/x86/kernel/setup.c 2016-06-19 22:11:55.061155987 +0200
+@@ -1120,7 +1120,7 @@
+ setup_real_mode();
+
+ memblock_set_current_limit(get_max_mapped());
+- dma_contiguous_reserve(0);
++ dma_contiguous_reserve(max_pfn_mapped << PAGE_SHIFT);
+
+ /*
+ * NOTE: On x86-32, only from this point on, fixmaps are ready for use.
+diff -Nur linux-3.14.72.orig/block/bfq-cgroup.c linux-3.14.72/block/bfq-cgroup.c
+--- linux-3.14.72.orig/block/bfq-cgroup.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/block/bfq-cgroup.c 2016-06-19 22:11:55.061155987 +0200
+@@ -0,0 +1,938 @@
++/*
++ * BFQ: CGROUPS support.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ
++ * file.
++ */
++
++#ifdef CONFIG_CGROUP_BFQIO
++
++static DEFINE_MUTEX(bfqio_mutex);
++
++static bool bfqio_is_removed(struct bfqio_cgroup *bgrp)
++{
++ return bgrp ? !bgrp->online : false;
++}
++
++static struct bfqio_cgroup bfqio_root_cgroup = {
++ .weight = BFQ_DEFAULT_GRP_WEIGHT,
++ .ioprio = BFQ_DEFAULT_GRP_IOPRIO,
++ .ioprio_class = BFQ_DEFAULT_GRP_CLASS,
++};
++
++static inline void bfq_init_entity(struct bfq_entity *entity,
++ struct bfq_group *bfqg)
++{
++ entity->weight = entity->new_weight;
++ entity->orig_weight = entity->new_weight;
++ entity->ioprio = entity->new_ioprio;
++ entity->ioprio_class = entity->new_ioprio_class;
++ entity->parent = bfqg->my_entity;
++ entity->sched_data = &bfqg->sched_data;
++}
++
++static struct bfqio_cgroup *css_to_bfqio(struct cgroup_subsys_state *css)
++{
++ return css ? container_of(css, struct bfqio_cgroup, css) : NULL;
++}
++
++/*
++ * Search the bfq_group for bfqd into the hash table (by now only a list)
++ * of bgrp. Must be called under rcu_read_lock().
++ */
++static struct bfq_group *bfqio_lookup_group(struct bfqio_cgroup *bgrp,
++ struct bfq_data *bfqd)
++{
++ struct bfq_group *bfqg;
++ void *key;
++
++ hlist_for_each_entry_rcu(bfqg, &bgrp->group_data, group_node) {
++ key = rcu_dereference(bfqg->bfqd);
++ if (key == bfqd)
++ return bfqg;
++ }
++
++ return NULL;
++}
++
++static inline void bfq_group_init_entity(struct bfqio_cgroup *bgrp,
++ struct bfq_group *bfqg)
++{
++ struct bfq_entity *entity = &bfqg->entity;
++
++ /*
++ * If the weight of the entity has never been set via the sysfs
++ * interface, then bgrp->weight == 0. In this case we initialize
++ * the weight from the current ioprio value. Otherwise, the group
++ * weight, if set, has priority over the ioprio value.
++ */
++ if (bgrp->weight == 0) {
++ entity->new_weight = bfq_ioprio_to_weight(bgrp->ioprio);
++ entity->new_ioprio = bgrp->ioprio;
++ } else {
++ if (bgrp->weight < BFQ_MIN_WEIGHT ||
++ bgrp->weight > BFQ_MAX_WEIGHT) {
++ printk(KERN_CRIT "bfq_group_init_entity: "
++ "bgrp->weight %d\n", bgrp->weight);
++ BUG();
++ }
++ entity->new_weight = bgrp->weight;
++ entity->new_ioprio = bfq_weight_to_ioprio(bgrp->weight);
++ }
++ entity->orig_weight = entity->weight = entity->new_weight;
++ entity->ioprio = entity->new_ioprio;
++ entity->ioprio_class = entity->new_ioprio_class = bgrp->ioprio_class;
++ entity->my_sched_data = &bfqg->sched_data;
++ bfqg->active_entities = 0;
++}
++
++static inline void bfq_group_set_parent(struct bfq_group *bfqg,
++ struct bfq_group *parent)
++{
++ struct bfq_entity *entity;
++
++ BUG_ON(parent == NULL);
++ BUG_ON(bfqg == NULL);
++
++ entity = &bfqg->entity;
++ entity->parent = parent->my_entity;
++ entity->sched_data = &parent->sched_data;
++}
++
++/**
++ * bfq_group_chain_alloc - allocate a chain of groups.
++ * @bfqd: queue descriptor.
++ * @css: the leaf cgroup_subsys_state this chain starts from.
++ *
++ * Allocate a chain of groups starting from the one belonging to
++ * @cgroup up to the root cgroup. Stop if a cgroup on the chain
++ * to the root has already an allocated group on @bfqd.
++ */
++static struct bfq_group *bfq_group_chain_alloc(struct bfq_data *bfqd,
++ struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp;
++ struct bfq_group *bfqg, *prev = NULL, *leaf = NULL;
++
++ for (; css != NULL; css = css->parent) {
++ bgrp = css_to_bfqio(css);
++
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ if (bfqg != NULL) {
++ /*
++ * All the cgroups in the path from there to the
++ * root must have a bfq_group for bfqd, so we don't
++ * need any more allocations.
++ */
++ break;
++ }
++
++ bfqg = kzalloc(sizeof(*bfqg), GFP_ATOMIC);
++ if (bfqg == NULL)
++ goto cleanup;
++
++ bfq_group_init_entity(bgrp, bfqg);
++ bfqg->my_entity = &bfqg->entity;
++
++ if (leaf == NULL) {
++ leaf = bfqg;
++ prev = leaf;
++ } else {
++ bfq_group_set_parent(prev, bfqg);
++ /*
++ * Build a list of allocated nodes using the bfqd
++ * filed, that is still unused and will be
++ * initialized only after the node will be
++ * connected.
++ */
++ prev->bfqd = bfqg;
++ prev = bfqg;
++ }
++ }
++
++ return leaf;
++
++cleanup:
++ while (leaf != NULL) {
++ prev = leaf;
++ leaf = leaf->bfqd;
++ kfree(prev);
++ }
++
++ return NULL;
++}
++
++/**
++ * bfq_group_chain_link - link an allocated group chain to a cgroup
++ * hierarchy.
++ * @bfqd: the queue descriptor.
++ * @css: the leaf cgroup_subsys_state to start from.
++ * @leaf: the leaf group (to be associated to @cgroup).
++ *
++ * Try to link a chain of groups to a cgroup hierarchy, connecting the
++ * nodes bottom-up, so we can be sure that when we find a cgroup in the
++ * hierarchy that already as a group associated to @bfqd all the nodes
++ * in the path to the root cgroup have one too.
++ *
++ * On locking: the queue lock protects the hierarchy (there is a hierarchy
++ * per device) while the bfqio_cgroup lock protects the list of groups
++ * belonging to the same cgroup.
++ */
++static void bfq_group_chain_link(struct bfq_data *bfqd,
++ struct cgroup_subsys_state *css,
++ struct bfq_group *leaf)
++{
++ struct bfqio_cgroup *bgrp;
++ struct bfq_group *bfqg, *next, *prev = NULL;
++ unsigned long flags;
++
++ assert_spin_locked(bfqd->queue->queue_lock);
++
++ for (; css != NULL && leaf != NULL; css = css->parent) {
++ bgrp = css_to_bfqio(css);
++ next = leaf->bfqd;
++
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ BUG_ON(bfqg != NULL);
++
++ spin_lock_irqsave(&bgrp->lock, flags);
++
++ rcu_assign_pointer(leaf->bfqd, bfqd);
++ hlist_add_head_rcu(&leaf->group_node, &bgrp->group_data);
++ hlist_add_head(&leaf->bfqd_node, &bfqd->group_list);
++
++ spin_unlock_irqrestore(&bgrp->lock, flags);
++
++ prev = leaf;
++ leaf = next;
++ }
++
++ BUG_ON(css == NULL && leaf != NULL);
++ if (css != NULL && prev != NULL) {
++ bgrp = css_to_bfqio(css);
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ bfq_group_set_parent(prev, bfqg);
++ }
++}
++
++/**
++ * bfq_find_alloc_group - return the group associated to @bfqd in @cgroup.
++ * @bfqd: queue descriptor.
++ * @cgroup: cgroup being searched for.
++ *
++ * Return a group associated to @bfqd in @cgroup, allocating one if
++ * necessary. When a group is returned all the cgroups in the path
++ * to the root have a group associated to @bfqd.
++ *
++ * If the allocation fails, return the root group: this breaks guarantees
++ * but is a safe fallback. If this loss becomes a problem it can be
++ * mitigated using the equivalent weight (given by the product of the
++ * weights of the groups in the path from @group to the root) in the
++ * root scheduler.
++ *
++ * We allocate all the missing nodes in the path from the leaf cgroup
++ * to the root and we connect the nodes only after all the allocations
++ * have been successful.
++ */
++static struct bfq_group *bfq_find_alloc_group(struct bfq_data *bfqd,
++ struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++ struct bfq_group *bfqg;
++
++ bfqg = bfqio_lookup_group(bgrp, bfqd);
++ if (bfqg != NULL)
++ return bfqg;
++
++ bfqg = bfq_group_chain_alloc(bfqd, css);
++ if (bfqg != NULL)
++ bfq_group_chain_link(bfqd, css, bfqg);
++ else
++ bfqg = bfqd->root_group;
++
++ return bfqg;
++}
++
++/**
++ * bfq_bfqq_move - migrate @bfqq to @bfqg.
++ * @bfqd: queue descriptor.
++ * @bfqq: the queue to move.
++ * @entity: @bfqq's entity.
++ * @bfqg: the group to move to.
++ *
++ * Move @bfqq to @bfqg, deactivating it from its old group and reactivating
++ * it on the new one. Avoid putting the entity on the old group idle tree.
++ *
++ * Must be called under the queue lock; the cgroup owning @bfqg must
++ * not disappear (by now this just means that we are called under
++ * rcu_read_lock()).
++ */
++static void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ struct bfq_entity *entity, struct bfq_group *bfqg)
++{
++ int busy, resume;
++
++ busy = bfq_bfqq_busy(bfqq);
++ resume = !RB_EMPTY_ROOT(&bfqq->sort_list);
++
++ BUG_ON(resume && !entity->on_st);
++ BUG_ON(busy && !resume && entity->on_st &&
++ bfqq != bfqd->in_service_queue);
++
++ if (busy) {
++ BUG_ON(atomic_read(&bfqq->ref) < 2);
++
++ if (!resume)
++ bfq_del_bfqq_busy(bfqd, bfqq, 0);
++ else
++ bfq_deactivate_bfqq(bfqd, bfqq, 0);
++ } else if (entity->on_st)
++ bfq_put_idle_entity(bfq_entity_service_tree(entity), entity);
++
++ /*
++ * Here we use a reference to bfqg. We don't need a refcounter
++ * as the cgroup reference will not be dropped, so that its
++ * destroy() callback will not be invoked.
++ */
++ entity->parent = bfqg->my_entity;
++ entity->sched_data = &bfqg->sched_data;
++
++ if (busy && resume)
++ bfq_activate_bfqq(bfqd, bfqq);
++
++ if (bfqd->in_service_queue == NULL && !bfqd->rq_in_driver)
++ bfq_schedule_dispatch(bfqd);
++}
++
++/**
++ * __bfq_bic_change_cgroup - move @bic to @cgroup.
++ * @bfqd: the queue descriptor.
++ * @bic: the bic to move.
++ * @cgroup: the cgroup to move to.
++ *
++ * Move bic to cgroup, assuming that bfqd->queue is locked; the caller
++ * has to make sure that the reference to cgroup is valid across the call.
++ *
++ * NOTE: an alternative approach might have been to store the current
++ * cgroup in bfqq and getting a reference to it, reducing the lookup
++ * time here, at the price of slightly more complex code.
++ */
++static struct bfq_group *__bfq_bic_change_cgroup(struct bfq_data *bfqd,
++ struct bfq_io_cq *bic,
++ struct cgroup_subsys_state *css)
++{
++ struct bfq_queue *async_bfqq = bic_to_bfqq(bic, 0);
++ struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, 1);
++ struct bfq_entity *entity;
++ struct bfq_group *bfqg;
++ struct bfqio_cgroup *bgrp;
++
++ bgrp = css_to_bfqio(css);
++
++ bfqg = bfq_find_alloc_group(bfqd, css);
++ if (async_bfqq != NULL) {
++ entity = &async_bfqq->entity;
++
++ if (entity->sched_data != &bfqg->sched_data) {
++ bic_set_bfqq(bic, NULL, 0);
++ bfq_log_bfqq(bfqd, async_bfqq,
++ "bic_change_group: %p %d",
++ async_bfqq, atomic_read(&async_bfqq->ref));
++ bfq_put_queue(async_bfqq);
++ }
++ }
++
++ if (sync_bfqq != NULL) {
++ entity = &sync_bfqq->entity;
++ if (entity->sched_data != &bfqg->sched_data)
++ bfq_bfqq_move(bfqd, sync_bfqq, entity, bfqg);
++ }
++
++ return bfqg;
++}
++
++/**
++ * bfq_bic_change_cgroup - move @bic to @cgroup.
++ * @bic: the bic being migrated.
++ * @cgroup: the destination cgroup.
++ *
++ * When the task owning @bic is moved to @cgroup, @bic is immediately
++ * moved into its new parent group.
++ */
++static void bfq_bic_change_cgroup(struct bfq_io_cq *bic,
++ struct cgroup_subsys_state *css)
++{
++ struct bfq_data *bfqd;
++ unsigned long uninitialized_var(flags);
++
++ bfqd = bfq_get_bfqd_locked(&(bic->icq.q->elevator->elevator_data),
++ &flags);
++ if (bfqd != NULL) {
++ __bfq_bic_change_cgroup(bfqd, bic, css);
++ bfq_put_bfqd_unlock(bfqd, &flags);
++ }
++}
++
++/**
++ * bfq_bic_update_cgroup - update the cgroup of @bic.
++ * @bic: the @bic to update.
++ *
++ * Make sure that @bic is enqueued in the cgroup of the current task.
++ * We need this in addition to moving bics during the cgroup attach
++ * phase because the task owning @bic could be at its first disk
++ * access or we may end up in the root cgroup as the result of a
++ * memory allocation failure and here we try to move to the right
++ * group.
++ *
++ * Must be called under the queue lock. It is safe to use the returned
++ * value even after the rcu_read_unlock() as the migration/destruction
++ * paths act under the queue lock too. IOW it is impossible to race with
++ * group migration/destruction and end up with an invalid group as:
++ * a) here cgroup has not yet been destroyed, nor its destroy callback
++ * has started execution, as current holds a reference to it,
++ * b) if it is destroyed after rcu_read_unlock() [after current is
++ * migrated to a different cgroup] its attach() callback will have
++ * taken care of remove all the references to the old cgroup data.
++ */
++static struct bfq_group *bfq_bic_update_cgroup(struct bfq_io_cq *bic)
++{
++ struct bfq_data *bfqd = bic_to_bfqd(bic);
++ struct bfq_group *bfqg;
++ struct cgroup_subsys_state *css;
++
++ BUG_ON(bfqd == NULL);
++
++ rcu_read_lock();
++ css = task_css(current, bfqio_subsys_id);
++ bfqg = __bfq_bic_change_cgroup(bfqd, bic, css);
++ rcu_read_unlock();
++
++ return bfqg;
++}
++
++/**
++ * bfq_flush_idle_tree - deactivate any entity on the idle tree of @st.
++ * @st: the service tree being flushed.
++ */
++static inline void bfq_flush_idle_tree(struct bfq_service_tree *st)
++{
++ struct bfq_entity *entity = st->first_idle;
++
++ for (; entity != NULL; entity = st->first_idle)
++ __bfq_deactivate_entity(entity, 0);
++}
++
++/**
++ * bfq_reparent_leaf_entity - move leaf entity to the root_group.
++ * @bfqd: the device data structure with the root group.
++ * @entity: the entity to move.
++ */
++static inline void bfq_reparent_leaf_entity(struct bfq_data *bfqd,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++
++ BUG_ON(bfqq == NULL);
++ bfq_bfqq_move(bfqd, bfqq, entity, bfqd->root_group);
++ return;
++}
++
++/**
++ * bfq_reparent_active_entities - move to the root group all active
++ * entities.
++ * @bfqd: the device data structure with the root group.
++ * @bfqg: the group to move from.
++ * @st: the service tree with the entities.
++ *
++ * Needs queue_lock to be taken and reference to be valid over the call.
++ */
++static inline void bfq_reparent_active_entities(struct bfq_data *bfqd,
++ struct bfq_group *bfqg,
++ struct bfq_service_tree *st)
++{
++ struct rb_root *active = &st->active;
++ struct bfq_entity *entity = NULL;
++
++ if (!RB_EMPTY_ROOT(&st->active))
++ entity = bfq_entity_of(rb_first(active));
++
++ for (; entity != NULL; entity = bfq_entity_of(rb_first(active)))
++ bfq_reparent_leaf_entity(bfqd, entity);
++
++ if (bfqg->sched_data.in_service_entity != NULL)
++ bfq_reparent_leaf_entity(bfqd,
++ bfqg->sched_data.in_service_entity);
++
++ return;
++}
++
++/**
++ * bfq_destroy_group - destroy @bfqg.
++ * @bgrp: the bfqio_cgroup containing @bfqg.
++ * @bfqg: the group being destroyed.
++ *
++ * Destroy @bfqg, making sure that it is not referenced from its parent.
++ */
++static void bfq_destroy_group(struct bfqio_cgroup *bgrp, struct bfq_group *bfqg)
++{
++ struct bfq_data *bfqd;
++ struct bfq_service_tree *st;
++ struct bfq_entity *entity = bfqg->my_entity;
++ unsigned long uninitialized_var(flags);
++ int i;
++
++ hlist_del(&bfqg->group_node);
++
++ /*
++ * Empty all service_trees belonging to this group before
++ * deactivating the group itself.
++ */
++ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) {
++ st = bfqg->sched_data.service_tree + i;
++
++ /*
++ * The idle tree may still contain bfq_queues belonging
++ * to exited task because they never migrated to a different
++ * cgroup from the one being destroyed now. No one else
++ * can access them so it's safe to act without any lock.
++ */
++ bfq_flush_idle_tree(st);
++
++ /*
++ * It may happen that some queues are still active
++ * (busy) upon group destruction (if the corresponding
++ * processes have been forced to terminate). We move
++ * all the leaf entities corresponding to these queues
++ * to the root_group.
++ * Also, it may happen that the group has an entity
++ * in service, which is disconnected from the active
++ * tree: it must be moved, too.
++ * There is no need to put the sync queues, as the
++ * scheduler has taken no reference.
++ */
++ bfqd = bfq_get_bfqd_locked(&bfqg->bfqd, &flags);
++ if (bfqd != NULL) {
++ bfq_reparent_active_entities(bfqd, bfqg, st);
++ bfq_put_bfqd_unlock(bfqd, &flags);
++ }
++ BUG_ON(!RB_EMPTY_ROOT(&st->active));
++ BUG_ON(!RB_EMPTY_ROOT(&st->idle));
++ }
++ BUG_ON(bfqg->sched_data.next_in_service != NULL);
++ BUG_ON(bfqg->sched_data.in_service_entity != NULL);
++
++ /*
++ * We may race with device destruction, take extra care when
++ * dereferencing bfqg->bfqd.
++ */
++ bfqd = bfq_get_bfqd_locked(&bfqg->bfqd, &flags);
++ if (bfqd != NULL) {
++ hlist_del(&bfqg->bfqd_node);
++ __bfq_deactivate_entity(entity, 0);
++ bfq_put_async_queues(bfqd, bfqg);
++ bfq_put_bfqd_unlock(bfqd, &flags);
++ }
++ BUG_ON(entity->tree != NULL);
++
++ /*
++ * No need to defer the kfree() to the end of the RCU grace
++ * period: we are called from the destroy() callback of our
++ * cgroup, so we can be sure that no one is a) still using
++ * this cgroup or b) doing lookups in it.
++ */
++ kfree(bfqg);
++}
++
++static void bfq_end_wr_async(struct bfq_data *bfqd)
++{
++ struct hlist_node *tmp;
++ struct bfq_group *bfqg;
++
++ hlist_for_each_entry_safe(bfqg, tmp, &bfqd->group_list, bfqd_node)
++ bfq_end_wr_async_queues(bfqd, bfqg);
++ bfq_end_wr_async_queues(bfqd, bfqd->root_group);
++}
++
++/**
++ * bfq_disconnect_groups - disconnect @bfqd from all its groups.
++ * @bfqd: the device descriptor being exited.
++ *
++ * When the device exits we just make sure that no lookup can return
++ * the now unused group structures. They will be deallocated on cgroup
++ * destruction.
++ */
++static void bfq_disconnect_groups(struct bfq_data *bfqd)
++{
++ struct hlist_node *tmp;
++ struct bfq_group *bfqg;
++
++ bfq_log(bfqd, "disconnect_groups beginning");
++ hlist_for_each_entry_safe(bfqg, tmp, &bfqd->group_list, bfqd_node) {
++ hlist_del(&bfqg->bfqd_node);
++
++ __bfq_deactivate_entity(bfqg->my_entity, 0);
++
++ /*
++ * Don't remove from the group hash, just set an
++ * invalid key. No lookups can race with the
++ * assignment as bfqd is being destroyed; this
++ * implies also that new elements cannot be added
++ * to the list.
++ */
++ rcu_assign_pointer(bfqg->bfqd, NULL);
++
++ bfq_log(bfqd, "disconnect_groups: put async for group %p",
++ bfqg);
++ bfq_put_async_queues(bfqd, bfqg);
++ }
++}
++
++static inline void bfq_free_root_group(struct bfq_data *bfqd)
++{
++ struct bfqio_cgroup *bgrp = &bfqio_root_cgroup;
++ struct bfq_group *bfqg = bfqd->root_group;
++
++ bfq_put_async_queues(bfqd, bfqg);
++
++ spin_lock_irq(&bgrp->lock);
++ hlist_del_rcu(&bfqg->group_node);
++ spin_unlock_irq(&bgrp->lock);
++
++ /*
++ * No need to synchronize_rcu() here: since the device is gone
++ * there cannot be any read-side access to its root_group.
++ */
++ kfree(bfqg);
++}
++
++static struct bfq_group *bfq_alloc_root_group(struct bfq_data *bfqd, int node)
++{
++ struct bfq_group *bfqg;
++ struct bfqio_cgroup *bgrp;
++ int i;
++
++ bfqg = kzalloc_node(sizeof(*bfqg), GFP_KERNEL, node);
++ if (bfqg == NULL)
++ return NULL;
++
++ bfqg->entity.parent = NULL;
++ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++)
++ bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT;
++
++ bgrp = &bfqio_root_cgroup;
++ spin_lock_irq(&bgrp->lock);
++ rcu_assign_pointer(bfqg->bfqd, bfqd);
++ hlist_add_head_rcu(&bfqg->group_node, &bgrp->group_data);
++ spin_unlock_irq(&bgrp->lock);
++
++ return bfqg;
++}
++
++#define SHOW_FUNCTION(__VAR) \
++static u64 bfqio_cgroup_##__VAR##_read(struct cgroup_subsys_state *css, \
++ struct cftype *cftype) \
++{ \
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css); \
++ u64 ret = -ENODEV; \
++ \
++ mutex_lock(&bfqio_mutex); \
++ if (bfqio_is_removed(bgrp)) \
++ goto out_unlock; \
++ \
++ spin_lock_irq(&bgrp->lock); \
++ ret = bgrp->__VAR; \
++ spin_unlock_irq(&bgrp->lock); \
++ \
++out_unlock: \
++ mutex_unlock(&bfqio_mutex); \
++ return ret; \
++}
++
++SHOW_FUNCTION(weight);
++SHOW_FUNCTION(ioprio);
++SHOW_FUNCTION(ioprio_class);
++#undef SHOW_FUNCTION
++
++#define STORE_FUNCTION(__VAR, __MIN, __MAX) \
++static int bfqio_cgroup_##__VAR##_write(struct cgroup_subsys_state *css,\
++ struct cftype *cftype, \
++ u64 val) \
++{ \
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css); \
++ struct bfq_group *bfqg; \
++ int ret = -EINVAL; \
++ \
++ if (val < (__MIN) || val > (__MAX)) \
++ return ret; \
++ \
++ ret = -ENODEV; \
++ mutex_lock(&bfqio_mutex); \
++ if (bfqio_is_removed(bgrp)) \
++ goto out_unlock; \
++ ret = 0; \
++ \
++ spin_lock_irq(&bgrp->lock); \
++ bgrp->__VAR = (unsigned short)val; \
++ hlist_for_each_entry(bfqg, &bgrp->group_data, group_node) { \
++ /* \
++ * Setting the ioprio_changed flag of the entity \
++ * to 1 with new_##__VAR == ##__VAR would re-set \
++ * the value of the weight to its ioprio mapping. \
++ * Set the flag only if necessary. \
++ */ \
++ if ((unsigned short)val != bfqg->entity.new_##__VAR) { \
++ bfqg->entity.new_##__VAR = (unsigned short)val; \
++ /* \
++ * Make sure that the above new value has been \
++ * stored in bfqg->entity.new_##__VAR before \
++ * setting the ioprio_changed flag. In fact, \
++ * this flag may be read asynchronously (in \
++ * critical sections protected by a different \
++ * lock than that held here), and finding this \
++ * flag set may cause the execution of the code \
++ * for updating parameters whose value may \
++ * depend also on bfqg->entity.new_##__VAR (in \
++ * __bfq_entity_update_weight_prio). \
++ * This barrier makes sure that the new value \
++ * of bfqg->entity.new_##__VAR is correctly \
++ * seen in that code. \
++ */ \
++ smp_wmb(); \
++ bfqg->entity.ioprio_changed = 1; \
++ } \
++ } \
++ spin_unlock_irq(&bgrp->lock); \
++ \
++out_unlock: \
++ mutex_unlock(&bfqio_mutex); \
++ return ret; \
++}
++
++STORE_FUNCTION(weight, BFQ_MIN_WEIGHT, BFQ_MAX_WEIGHT);
++STORE_FUNCTION(ioprio, 0, IOPRIO_BE_NR - 1);
++STORE_FUNCTION(ioprio_class, IOPRIO_CLASS_RT, IOPRIO_CLASS_IDLE);
++#undef STORE_FUNCTION
++
++static struct cftype bfqio_files[] = {
++ {
++ .name = "weight",
++ .read_u64 = bfqio_cgroup_weight_read,
++ .write_u64 = bfqio_cgroup_weight_write,
++ },
++ {
++ .name = "ioprio",
++ .read_u64 = bfqio_cgroup_ioprio_read,
++ .write_u64 = bfqio_cgroup_ioprio_write,
++ },
++ {
++ .name = "ioprio_class",
++ .read_u64 = bfqio_cgroup_ioprio_class_read,
++ .write_u64 = bfqio_cgroup_ioprio_class_write,
++ },
++ { }, /* terminate */
++};
++
++static struct cgroup_subsys_state *bfqio_create(struct cgroup_subsys_state
++ *parent_css)
++{
++ struct bfqio_cgroup *bgrp;
++
++ if (parent_css != NULL) {
++ bgrp = kzalloc(sizeof(*bgrp), GFP_KERNEL);
++ if (bgrp == NULL)
++ return ERR_PTR(-ENOMEM);
++ } else
++ bgrp = &bfqio_root_cgroup;
++
++ spin_lock_init(&bgrp->lock);
++ INIT_HLIST_HEAD(&bgrp->group_data);
++ bgrp->ioprio = BFQ_DEFAULT_GRP_IOPRIO;
++ bgrp->ioprio_class = BFQ_DEFAULT_GRP_CLASS;
++
++ return &bgrp->css;
++}
++
++/*
++ * We cannot support shared io contexts, as we have no means to support
++ * two tasks with the same ioc in two different groups without major rework
++ * of the main bic/bfqq data structures. By now we allow a task to change
++ * its cgroup only if it's the only owner of its ioc; the drawback of this
++ * behavior is that a group containing a task that forked using CLONE_IO
++ * will not be destroyed until the tasks sharing the ioc die.
++ */
++static int bfqio_can_attach(struct cgroup_subsys_state *css,
++ struct cgroup_taskset *tset)
++{
++ struct task_struct *task;
++ struct io_context *ioc;
++ int ret = 0;
++
++ cgroup_taskset_for_each(task, css, tset) {
++ /*
++ * task_lock() is needed to avoid races with
++ * exit_io_context()
++ */
++ task_lock(task);
++ ioc = task->io_context;
++ if (ioc != NULL && atomic_read(&ioc->nr_tasks) > 1)
++ /*
++ * ioc == NULL means that the task is either too
++ * young or exiting: if it has still no ioc the
++ * ioc can't be shared, if the task is exiting the
++ * attach will fail anyway, no matter what we
++ * return here.
++ */
++ ret = -EINVAL;
++ task_unlock(task);
++ if (ret)
++ break;
++ }
++
++ return ret;
++}
++
++static void bfqio_attach(struct cgroup_subsys_state *css,
++ struct cgroup_taskset *tset)
++{
++ struct task_struct *task;
++ struct io_context *ioc;
++ struct io_cq *icq;
++
++ /*
++ * IMPORTANT NOTE: The move of more than one process at a time to a
++ * new group has not yet been tested.
++ */
++ cgroup_taskset_for_each(task, css, tset) {
++ ioc = get_task_io_context(task, GFP_ATOMIC, NUMA_NO_NODE);
++ if (ioc) {
++ /*
++ * Handle cgroup change here.
++ */
++ rcu_read_lock();
++ hlist_for_each_entry_rcu(icq, &ioc->icq_list, ioc_node)
++ if (!strncmp(
++ icq->q->elevator->type->elevator_name,
++ "bfq", ELV_NAME_MAX))
++ bfq_bic_change_cgroup(icq_to_bic(icq),
++ css);
++ rcu_read_unlock();
++ put_io_context(ioc);
++ }
++ }
++}
++
++static void bfqio_destroy(struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++ struct hlist_node *tmp;
++ struct bfq_group *bfqg;
++
++ /*
++ * Since we are destroying the cgroup, there are no more tasks
++ * referencing it, and all the RCU grace periods that may have
++ * referenced it are ended (as the destruction of the parent
++ * cgroup is RCU-safe); bgrp->group_data will not be accessed by
++ * anything else and we don't need any synchronization.
++ */
++ hlist_for_each_entry_safe(bfqg, tmp, &bgrp->group_data, group_node)
++ bfq_destroy_group(bgrp, bfqg);
++
++ BUG_ON(!hlist_empty(&bgrp->group_data));
++
++ kfree(bgrp);
++}
++
++static int bfqio_css_online(struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++
++ mutex_lock(&bfqio_mutex);
++ bgrp->online = true;
++ mutex_unlock(&bfqio_mutex);
++
++ return 0;
++}
++
++static void bfqio_css_offline(struct cgroup_subsys_state *css)
++{
++ struct bfqio_cgroup *bgrp = css_to_bfqio(css);
++
++ mutex_lock(&bfqio_mutex);
++ bgrp->online = false;
++ mutex_unlock(&bfqio_mutex);
++}
++
++struct cgroup_subsys bfqio_subsys = {
++ .name = "bfqio",
++ .css_alloc = bfqio_create,
++ .css_online = bfqio_css_online,
++ .css_offline = bfqio_css_offline,
++ .can_attach = bfqio_can_attach,
++ .attach = bfqio_attach,
++ .css_free = bfqio_destroy,
++ .subsys_id = bfqio_subsys_id,
++ .base_cftypes = bfqio_files,
++};
++#else
++static inline void bfq_init_entity(struct bfq_entity *entity,
++ struct bfq_group *bfqg)
++{
++ entity->weight = entity->new_weight;
++ entity->orig_weight = entity->new_weight;
++ entity->ioprio = entity->new_ioprio;
++ entity->ioprio_class = entity->new_ioprio_class;
++ entity->sched_data = &bfqg->sched_data;
++}
++
++static inline struct bfq_group *
++bfq_bic_update_cgroup(struct bfq_io_cq *bic)
++{
++ struct bfq_data *bfqd = bic_to_bfqd(bic);
++ return bfqd->root_group;
++}
++
++static inline void bfq_bfqq_move(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct bfq_entity *entity,
++ struct bfq_group *bfqg)
++{
++}
++
++static void bfq_end_wr_async(struct bfq_data *bfqd)
++{
++ bfq_end_wr_async_queues(bfqd, bfqd->root_group);
++}
++
++static inline void bfq_disconnect_groups(struct bfq_data *bfqd)
++{
++ bfq_put_async_queues(bfqd, bfqd->root_group);
++}
++
++static inline void bfq_free_root_group(struct bfq_data *bfqd)
++{
++ kfree(bfqd->root_group);
++}
++
++static struct bfq_group *bfq_alloc_root_group(struct bfq_data *bfqd, int node)
++{
++ struct bfq_group *bfqg;
++ int i;
++
++ bfqg = kmalloc_node(sizeof(*bfqg), GFP_KERNEL | __GFP_ZERO, node);
++ if (bfqg == NULL)
++ return NULL;
++
++ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++)
++ bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT;
++
++ return bfqg;
++}
++#endif
+diff -Nur linux-3.14.72.orig/block/bfq.h linux-3.14.72/block/bfq.h
+--- linux-3.14.72.orig/block/bfq.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/block/bfq.h 2016-06-19 22:11:55.065155743 +0200
+@@ -0,0 +1,807 @@
++/*
++ * BFQ-v7r8 for 3.14.0: data structures and common functions prototypes.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ */
++
++#ifndef _BFQ_H
++#define _BFQ_H
++
++#include <linux/blktrace_api.h>
++#include <linux/hrtimer.h>
++#include <linux/ioprio.h>
++#include <linux/rbtree.h>
++
++#define BFQ_IOPRIO_CLASSES 3
++#define BFQ_CL_IDLE_TIMEOUT (HZ/5)
++
++#define BFQ_MIN_WEIGHT 1
++#define BFQ_MAX_WEIGHT 1000
++
++#define BFQ_DEFAULT_QUEUE_IOPRIO 4
++
++#define BFQ_DEFAULT_GRP_WEIGHT 10
++#define BFQ_DEFAULT_GRP_IOPRIO 0
++#define BFQ_DEFAULT_GRP_CLASS IOPRIO_CLASS_BE
++
++struct bfq_entity;
++
++/**
++ * struct bfq_service_tree - per ioprio_class service tree.
++ * @active: tree for active entities (i.e., those backlogged).
++ * @idle: tree for idle entities (i.e., those not backlogged, with V <= F_i).
++ * @first_idle: idle entity with minimum F_i.
++ * @last_idle: idle entity with maximum F_i.
++ * @vtime: scheduler virtual time.
++ * @wsum: scheduler weight sum; active and idle entities contribute to it.
++ *
++ * Each service tree represents a B-WF2Q+ scheduler on its own. Each
++ * ioprio_class has its own independent scheduler, and so its own
++ * bfq_service_tree. All the fields are protected by the queue lock
++ * of the containing bfqd.
++ */
++struct bfq_service_tree {
++ struct rb_root active;
++ struct rb_root idle;
++
++ struct bfq_entity *first_idle;
++ struct bfq_entity *last_idle;
++
++ u64 vtime;
++ unsigned long wsum;
++};
++
++/**
++ * struct bfq_sched_data - multi-class scheduler.
++ * @in_service_entity: entity in service.
++ * @next_in_service: head-of-the-line entity in the scheduler.
++ * @service_tree: array of service trees, one per ioprio_class.
++ *
++ * bfq_sched_data is the basic scheduler queue. It supports three
++ * ioprio_classes, and can be used either as a toplevel queue or as
++ * an intermediate queue on a hierarchical setup.
++ * @next_in_service points to the active entity of the sched_data
++ * service trees that will be scheduled next.
++ *
++ * The supported ioprio_classes are the same as in CFQ, in descending
++ * priority order, IOPRIO_CLASS_RT, IOPRIO_CLASS_BE, IOPRIO_CLASS_IDLE.
++ * Requests from higher priority queues are served before all the
++ * requests from lower priority queues; among requests of the same
++ * queue requests are served according to B-WF2Q+.
++ * All the fields are protected by the queue lock of the containing bfqd.
++ */
++struct bfq_sched_data {
++ struct bfq_entity *in_service_entity;
++ struct bfq_entity *next_in_service;
++ struct bfq_service_tree service_tree[BFQ_IOPRIO_CLASSES];
++};
++
++/**
++ * struct bfq_weight_counter - counter of the number of all active entities
++ * with a given weight.
++ * @weight: weight of the entities that this counter refers to.
++ * @num_active: number of active entities with this weight.
++ * @weights_node: weights tree member (see bfq_data's @queue_weights_tree
++ * and @group_weights_tree).
++ */
++struct bfq_weight_counter {
++ short int weight;
++ unsigned int num_active;
++ struct rb_node weights_node;
++};
++
++/**
++ * struct bfq_entity - schedulable entity.
++ * @rb_node: service_tree member.
++ * @weight_counter: pointer to the weight counter associated with this entity.
++ * @on_st: flag, true if the entity is on a tree (either the active or
++ * the idle one of its service_tree).
++ * @finish: B-WF2Q+ finish timestamp (aka F_i).
++ * @start: B-WF2Q+ start timestamp (aka S_i).
++ * @tree: tree the entity is enqueued into; %NULL if not on a tree.
++ * @min_start: minimum start time of the (active) subtree rooted at
++ * this entity; used for O(log N) lookups into active trees.
++ * @service: service received during the last round of service.
++ * @budget: budget used to calculate F_i; F_i = S_i + @budget / @weight.
++ * @weight: weight of the queue
++ * @parent: parent entity, for hierarchical scheduling.
++ * @my_sched_data: for non-leaf nodes in the cgroup hierarchy, the
++ * associated scheduler queue, %NULL on leaf nodes.
++ * @sched_data: the scheduler queue this entity belongs to.
++ * @ioprio: the ioprio in use.
++ * @new_weight: when a weight change is requested, the new weight value.
++ * @orig_weight: original weight, used to implement weight boosting
++ * @new_ioprio: when an ioprio change is requested, the new ioprio value.
++ * @ioprio_class: the ioprio_class in use.
++ * @new_ioprio_class: when an ioprio_class change is requested, the new
++ * ioprio_class value.
++ * @ioprio_changed: flag, true when the user requested a weight, ioprio or
++ * ioprio_class change.
++ *
++ * A bfq_entity is used to represent either a bfq_queue (leaf node in the
++ * cgroup hierarchy) or a bfq_group into the upper level scheduler. Each
++ * entity belongs to the sched_data of the parent group in the cgroup
++ * hierarchy. Non-leaf entities have also their own sched_data, stored
++ * in @my_sched_data.
++ *
++ * Each entity stores independently its priority values; this would
++ * allow different weights on different devices, but this
++ * functionality is not exported to userspace by now. Priorities and
++ * weights are updated lazily, first storing the new values into the
++ * new_* fields, then setting the @ioprio_changed flag. As soon as
++ * there is a transition in the entity state that allows the priority
++ * update to take place the effective and the requested priority
++ * values are synchronized.
++ *
++ * Unless cgroups are used, the weight value is calculated from the
++ * ioprio to export the same interface as CFQ. When dealing with
++ * ``well-behaved'' queues (i.e., queues that do not spend too much
++ * time to consume their budget and have true sequential behavior, and
++ * when there are no external factors breaking anticipation) the
++ * relative weights at each level of the cgroups hierarchy should be
++ * guaranteed. All the fields are protected by the queue lock of the
++ * containing bfqd.
++ */
++struct bfq_entity {
++ struct rb_node rb_node;
++ struct bfq_weight_counter *weight_counter;
++
++ int on_st;
++
++ u64 finish;
++ u64 start;
++
++ struct rb_root *tree;
++
++ u64 min_start;
++
++ unsigned long service, budget;
++ unsigned short weight, new_weight;
++ unsigned short orig_weight;
++
++ struct bfq_entity *parent;
++
++ struct bfq_sched_data *my_sched_data;
++ struct bfq_sched_data *sched_data;
++
++ unsigned short ioprio, new_ioprio;
++ unsigned short ioprio_class, new_ioprio_class;
++
++ int ioprio_changed;
++};
++
++struct bfq_group;
++
++/**
++ * struct bfq_queue - leaf schedulable entity.
++ * @ref: reference counter.
++ * @bfqd: parent bfq_data.
++ * @new_bfqq: shared bfq_queue if queue is cooperating with
++ * one or more other queues.
++ * @pos_node: request-position tree member (see bfq_data's @rq_pos_tree).
++ * @pos_root: request-position tree root (see bfq_data's @rq_pos_tree).
++ * @sort_list: sorted list of pending requests.
++ * @next_rq: if fifo isn't expired, next request to serve.
++ * @queued: nr of requests queued in @sort_list.
++ * @allocated: currently allocated requests.
++ * @meta_pending: pending metadata requests.
++ * @fifo: fifo list of requests in sort_list.
++ * @entity: entity representing this queue in the scheduler.
++ * @max_budget: maximum budget allowed from the feedback mechanism.
++ * @budget_timeout: budget expiration (in jiffies).
++ * @dispatched: number of requests on the dispatch list or inside driver.
++ * @flags: status flags.
++ * @bfqq_list: node for active/idle bfqq list inside our bfqd.
++ * @burst_list_node: node for the device's burst list.
++ * @seek_samples: number of seeks sampled
++ * @seek_total: sum of the distances of the seeks sampled
++ * @seek_mean: mean seek distance
++ * @last_request_pos: position of the last request enqueued
++ * @requests_within_timer: number of consecutive pairs of request completion
++ * and arrival, such that the queue becomes idle
++ * after the completion, but the next request arrives
++ * within an idle time slice; used only if the queue's
++ * IO_bound has been cleared.
++ * @pid: pid of the process owning the queue, used for logging purposes.
++ * @last_wr_start_finish: start time of the current weight-raising period if
++ * the @bfq-queue is being weight-raised, otherwise
++ * finish time of the last weight-raising period
++ * @wr_cur_max_time: current max raising time for this queue
++ * @soft_rt_next_start: minimum time instant such that, only if a new
++ * request is enqueued after this time instant in an
++ * idle @bfq_queue with no outstanding requests, then
++ * the task associated with the queue it is deemed as
++ * soft real-time (see the comments to the function
++ * bfq_bfqq_softrt_next_start())
++ * @last_idle_bklogged: time of the last transition of the @bfq_queue from
++ * idle to backlogged
++ * @service_from_backlogged: cumulative service received from the @bfq_queue
++ * since the last transition from idle to
++ * backlogged
++ * @bic: pointer to the bfq_io_cq owning the bfq_queue, set to %NULL if the
++ * queue is shared
++ *
++ * A bfq_queue is a leaf request queue; it can be associated with an
++ * io_context or more, if it is async or shared between cooperating
++ * processes. @cgroup holds a reference to the cgroup, to be sure that it
++ * does not disappear while a bfqq still references it (mostly to avoid
++ * races between request issuing and task migration followed by cgroup
++ * destruction).
++ * All the fields are protected by the queue lock of the containing bfqd.
++ */
++struct bfq_queue {
++ atomic_t ref;
++ struct bfq_data *bfqd;
++
++ /* fields for cooperating queues handling */
++ struct bfq_queue *new_bfqq;
++ struct rb_node pos_node;
++ struct rb_root *pos_root;
++
++ struct rb_root sort_list;
++ struct request *next_rq;
++ int queued[2];
++ int allocated[2];
++ int meta_pending;
++ struct list_head fifo;
++
++ struct bfq_entity entity;
++
++ unsigned long max_budget;
++ unsigned long budget_timeout;
++
++ int dispatched;
++
++ unsigned int flags;
++
++ struct list_head bfqq_list;
++
++ struct hlist_node burst_list_node;
++
++ unsigned int seek_samples;
++ u64 seek_total;
++ sector_t seek_mean;
++ sector_t last_request_pos;
++
++ unsigned int requests_within_timer;
++
++ pid_t pid;
++ struct bfq_io_cq *bic;
++
++ /* weight-raising fields */
++ unsigned long wr_cur_max_time;
++ unsigned long soft_rt_next_start;
++ unsigned long last_wr_start_finish;
++ unsigned int wr_coeff;
++ unsigned long last_idle_bklogged;
++ unsigned long service_from_backlogged;
++};
++
++/**
++ * struct bfq_ttime - per process thinktime stats.
++ * @ttime_total: total process thinktime
++ * @ttime_samples: number of thinktime samples
++ * @ttime_mean: average process thinktime
++ */
++struct bfq_ttime {
++ unsigned long last_end_request;
++
++ unsigned long ttime_total;
++ unsigned long ttime_samples;
++ unsigned long ttime_mean;
++};
++
++/**
++ * struct bfq_io_cq - per (request_queue, io_context) structure.
++ * @icq: associated io_cq structure
++ * @bfqq: array of two process queues, the sync and the async
++ * @ttime: associated @bfq_ttime struct
++ * @wr_time_left: snapshot of the time left before weight raising ends
++ * for the sync queue associated to this process; this
++ * snapshot is taken to remember this value while the weight
++ * raising is suspended because the queue is merged with a
++ * shared queue, and is used to set @raising_cur_max_time
++ * when the queue is split from the shared queue and its
++ * weight is raised again
++ * @saved_idle_window: same purpose as the previous field for the idle
++ * window
++ * @saved_IO_bound: same purpose as the previous two fields for the I/O
++ * bound classification of a queue
++ * @saved_in_large_burst: same purpose as the previous fields for the
++ * value of the field keeping the queue's belonging
++ * to a large burst
++ * @was_in_burst_list: true if the queue belonged to a burst list
++ * before its merge with another cooperating queue
++ * @cooperations: counter of consecutive successful queue merges underwent
++ * by any of the process' @bfq_queues
++ * @failed_cooperations: counter of consecutive failed queue merges of any
++ * of the process' @bfq_queues
++ */
++struct bfq_io_cq {
++ struct io_cq icq; /* must be the first member */
++ struct bfq_queue *bfqq[2];
++ struct bfq_ttime ttime;
++ int ioprio;
++
++ unsigned int wr_time_left;
++ bool saved_idle_window;
++ bool saved_IO_bound;
++
++ bool saved_in_large_burst;
++ bool was_in_burst_list;
++
++ unsigned int cooperations;
++ unsigned int failed_cooperations;
++};
++
++enum bfq_device_speed {
++ BFQ_BFQD_FAST,
++ BFQ_BFQD_SLOW,
++};
++
++/**
++ * struct bfq_data - per device data structure.
++ * @queue: request queue for the managed device.
++ * @root_group: root bfq_group for the device.
++ * @rq_pos_tree: rbtree sorted by next_request position, used when
++ * determining if two or more queues have interleaving
++ * requests (see bfq_close_cooperator()).
++ * @active_numerous_groups: number of bfq_groups containing more than one
++ * active @bfq_entity.
++ * @queue_weights_tree: rbtree of weight counters of @bfq_queues, sorted by
++ * weight. Used to keep track of whether all @bfq_queues
++ * have the same weight. The tree contains one counter
++ * for each distinct weight associated to some active
++ * and not weight-raised @bfq_queue (see the comments to
++ * the functions bfq_weights_tree_[add|remove] for
++ * further details).
++ * @group_weights_tree: rbtree of non-queue @bfq_entity weight counters, sorted
++ * by weight. Used to keep track of whether all
++ * @bfq_groups have the same weight. The tree contains
++ * one counter for each distinct weight associated to
++ * some active @bfq_group (see the comments to the
++ * functions bfq_weights_tree_[add|remove] for further
++ * details).
++ * @busy_queues: number of bfq_queues containing requests (including the
++ * queue in service, even if it is idling).
++ * @busy_in_flight_queues: number of @bfq_queues containing pending or
++ * in-flight requests, plus the @bfq_queue in
++ * service, even if idle but waiting for the
++ * possible arrival of its next sync request. This
++ * field is updated only if the device is rotational,
++ * but used only if the device is also NCQ-capable.
++ * The reason why the field is updated also for non-
++ * NCQ-capable rotational devices is related to the
++ * fact that the value of @hw_tag may be set also
++ * later than when busy_in_flight_queues may need to
++ * be incremented for the first time(s). Taking also
++ * this possibility into account, to avoid unbalanced
++ * increments/decrements, would imply more overhead
++ * than just updating busy_in_flight_queues
++ * regardless of the value of @hw_tag.
++ * @const_seeky_busy_in_flight_queues: number of constantly-seeky @bfq_queues
++ * (that is, seeky queues that expired
++ * for budget timeout at least once)
++ * containing pending or in-flight
++ * requests, including the in-service
++ * @bfq_queue if constantly seeky. This
++ * field is updated only if the device
++ * is rotational, but used only if the
++ * device is also NCQ-capable (see the
++ * comments to @busy_in_flight_queues).
++ * @wr_busy_queues: number of weight-raised busy @bfq_queues.
++ * @queued: number of queued requests.
++ * @rq_in_driver: number of requests dispatched and waiting for completion.
++ * @sync_flight: number of sync requests in the driver.
++ * @max_rq_in_driver: max number of reqs in driver in the last
++ * @hw_tag_samples completed requests.
++ * @hw_tag_samples: nr of samples used to calculate hw_tag.
++ * @hw_tag: flag set to one if the driver is showing a queueing behavior.
++ * @budgets_assigned: number of budgets assigned.
++ * @idle_slice_timer: timer set when idling for the next sequential request
++ * from the queue in service.
++ * @unplug_work: delayed work to restart dispatching on the request queue.
++ * @in_service_queue: bfq_queue in service.
++ * @in_service_bic: bfq_io_cq (bic) associated with the @in_service_queue.
++ * @last_position: on-disk position of the last served request.
++ * @last_budget_start: beginning of the last budget.
++ * @last_idling_start: beginning of the last idle slice.
++ * @peak_rate: peak transfer rate observed for a budget.
++ * @peak_rate_samples: number of samples used to calculate @peak_rate.
++ * @bfq_max_budget: maximum budget allotted to a bfq_queue before
++ * rescheduling.
++ * @group_list: list of all the bfq_groups active on the device.
++ * @active_list: list of all the bfq_queues active on the device.
++ * @idle_list: list of all the bfq_queues idle on the device.
++ * @bfq_fifo_expire: timeout for async/sync requests; when it expires
++ * requests are served in fifo order.
++ * @bfq_back_penalty: weight of backward seeks wrt forward ones.
++ * @bfq_back_max: maximum allowed backward seek.
++ * @bfq_slice_idle: maximum idling time.
++ * @bfq_user_max_budget: user-configured max budget value
++ * (0 for auto-tuning).
++ * @bfq_max_budget_async_rq: maximum budget (in nr of requests) allotted to
++ * async queues.
++ * @bfq_timeout: timeout for bfq_queues to consume their budget; used to
++ * to prevent seeky queues to impose long latencies to well
++ * behaved ones (this also implies that seeky queues cannot
++ * receive guarantees in the service domain; after a timeout
++ * they are charged for the whole allocated budget, to try
++ * to preserve a behavior reasonably fair among them, but
++ * without service-domain guarantees).
++ * @bfq_coop_thresh: number of queue merges after which a @bfq_queue is
++ * no more granted any weight-raising.
++ * @bfq_failed_cooperations: number of consecutive failed cooperation
++ * chances after which weight-raising is restored
++ * to a queue subject to more than bfq_coop_thresh
++ * queue merges.
++ * @bfq_requests_within_timer: number of consecutive requests that must be
++ * issued within the idle time slice to set
++ * again idling to a queue which was marked as
++ * non-I/O-bound (see the definition of the
++ * IO_bound flag for further details).
++ * @last_ins_in_burst: last time at which a queue entered the current
++ * burst of queues being activated shortly after
++ * each other; for more details about this and the
++ * following parameters related to a burst of
++ * activations, see the comments to the function
++ * @bfq_handle_burst.
++ * @bfq_burst_interval: reference time interval used to decide whether a
++ * queue has been activated shortly after
++ * @last_ins_in_burst.
++ * @burst_size: number of queues in the current burst of queue activations.
++ * @bfq_large_burst_thresh: maximum burst size above which the current
++ * queue-activation burst is deemed as 'large'.
++ * @large_burst: true if a large queue-activation burst is in progress.
++ * @burst_list: head of the burst list (as for the above fields, more details
++ * in the comments to the function bfq_handle_burst).
++ * @low_latency: if set to true, low-latency heuristics are enabled.
++ * @bfq_wr_coeff: maximum factor by which the weight of a weight-raised
++ * queue is multiplied.
++ * @bfq_wr_max_time: maximum duration of a weight-raising period (jiffies).
++ * @bfq_wr_rt_max_time: maximum duration for soft real-time processes.
++ * @bfq_wr_min_idle_time: minimum idle period after which weight-raising
++ * may be reactivated for a queue (in jiffies).
++ * @bfq_wr_min_inter_arr_async: minimum period between request arrivals
++ * after which weight-raising may be
++ * reactivated for an already busy queue
++ * (in jiffies).
++ * @bfq_wr_max_softrt_rate: max service-rate for a soft real-time queue,
++ * sectors per seconds.
++ * @RT_prod: cached value of the product R*T used for computing the maximum
++ * duration of the weight raising automatically.
++ * @device_speed: device-speed class for the low-latency heuristic.
++ * @oom_bfqq: fallback dummy bfqq for extreme OOM conditions.
++ *
++ * All the fields are protected by the @queue lock.
++ */
++struct bfq_data {
++ struct request_queue *queue;
++
++ struct bfq_group *root_group;
++ struct rb_root rq_pos_tree;
++
++#ifdef CONFIG_CGROUP_BFQIO
++ int active_numerous_groups;
++#endif
++
++ struct rb_root queue_weights_tree;
++ struct rb_root group_weights_tree;
++
++ int busy_queues;
++ int busy_in_flight_queues;
++ int const_seeky_busy_in_flight_queues;
++ int wr_busy_queues;
++ int queued;
++ int rq_in_driver;
++ int sync_flight;
++
++ int max_rq_in_driver;
++ int hw_tag_samples;
++ int hw_tag;
++
++ int budgets_assigned;
++
++ struct timer_list idle_slice_timer;
++ struct work_struct unplug_work;
++
++ struct bfq_queue *in_service_queue;
++ struct bfq_io_cq *in_service_bic;
++
++ sector_t last_position;
++
++ ktime_t last_budget_start;
++ ktime_t last_idling_start;
++ int peak_rate_samples;
++ u64 peak_rate;
++ unsigned long bfq_max_budget;
++
++ struct hlist_head group_list;
++ struct list_head active_list;
++ struct list_head idle_list;
++
++ unsigned int bfq_fifo_expire[2];
++ unsigned int bfq_back_penalty;
++ unsigned int bfq_back_max;
++ unsigned int bfq_slice_idle;
++ u64 bfq_class_idle_last_service;
++
++ unsigned int bfq_user_max_budget;
++ unsigned int bfq_max_budget_async_rq;
++ unsigned int bfq_timeout[2];
++
++ unsigned int bfq_coop_thresh;
++ unsigned int bfq_failed_cooperations;
++ unsigned int bfq_requests_within_timer;
++
++ unsigned long last_ins_in_burst;
++ unsigned long bfq_burst_interval;
++ int burst_size;
++ unsigned long bfq_large_burst_thresh;
++ bool large_burst;
++ struct hlist_head burst_list;
++
++ bool low_latency;
++
++ /* parameters of the low_latency heuristics */
++ unsigned int bfq_wr_coeff;
++ unsigned int bfq_wr_max_time;
++ unsigned int bfq_wr_rt_max_time;
++ unsigned int bfq_wr_min_idle_time;
++ unsigned long bfq_wr_min_inter_arr_async;
++ unsigned int bfq_wr_max_softrt_rate;
++ u64 RT_prod;
++ enum bfq_device_speed device_speed;
++
++ struct bfq_queue oom_bfqq;
++};
++
++enum bfqq_state_flags {
++ BFQ_BFQQ_FLAG_busy = 0, /* has requests or is in service */
++ BFQ_BFQQ_FLAG_wait_request, /* waiting for a request */
++ BFQ_BFQQ_FLAG_must_alloc, /* must be allowed rq alloc */
++ BFQ_BFQQ_FLAG_fifo_expire, /* FIFO checked in this slice */
++ BFQ_BFQQ_FLAG_idle_window, /* slice idling enabled */
++ BFQ_BFQQ_FLAG_sync, /* synchronous queue */
++ BFQ_BFQQ_FLAG_budget_new, /* no completion with this budget */
++ BFQ_BFQQ_FLAG_IO_bound, /*
++ * bfqq has timed-out at least once
++ * having consumed at most 2/10 of
++ * its budget
++ */
++ BFQ_BFQQ_FLAG_in_large_burst, /*
++ * bfqq activated in a large burst,
++ * see comments to bfq_handle_burst.
++ */
++ BFQ_BFQQ_FLAG_constantly_seeky, /*
++ * bfqq has proved to be slow and
++ * seeky until budget timeout
++ */
++ BFQ_BFQQ_FLAG_softrt_update, /*
++ * may need softrt-next-start
++ * update
++ */
++ BFQ_BFQQ_FLAG_coop, /* bfqq is shared */
++ BFQ_BFQQ_FLAG_split_coop, /* shared bfqq will be split */
++ BFQ_BFQQ_FLAG_just_split, /* queue has just been split */
++};
++
++#define BFQ_BFQQ_FNS(name) \
++static inline void bfq_mark_bfqq_##name(struct bfq_queue *bfqq) \
++{ \
++ (bfqq)->flags |= (1 << BFQ_BFQQ_FLAG_##name); \
++} \
++static inline void bfq_clear_bfqq_##name(struct bfq_queue *bfqq) \
++{ \
++ (bfqq)->flags &= ~(1 << BFQ_BFQQ_FLAG_##name); \
++} \
++static inline int bfq_bfqq_##name(const struct bfq_queue *bfqq) \
++{ \
++ return ((bfqq)->flags & (1 << BFQ_BFQQ_FLAG_##name)) != 0; \
++}
++
++BFQ_BFQQ_FNS(busy);
++BFQ_BFQQ_FNS(wait_request);
++BFQ_BFQQ_FNS(must_alloc);
++BFQ_BFQQ_FNS(fifo_expire);
++BFQ_BFQQ_FNS(idle_window);
++BFQ_BFQQ_FNS(sync);
++BFQ_BFQQ_FNS(budget_new);
++BFQ_BFQQ_FNS(IO_bound);
++BFQ_BFQQ_FNS(in_large_burst);
++BFQ_BFQQ_FNS(constantly_seeky);
++BFQ_BFQQ_FNS(coop);
++BFQ_BFQQ_FNS(split_coop);
++BFQ_BFQQ_FNS(just_split);
++BFQ_BFQQ_FNS(softrt_update);
++#undef BFQ_BFQQ_FNS
++
++/* Logging facilities. */
++#define bfq_log_bfqq(bfqd, bfqq, fmt, args...) \
++ blk_add_trace_msg((bfqd)->queue, "bfq%d " fmt, (bfqq)->pid, ##args)
++
++#define bfq_log(bfqd, fmt, args...) \
++ blk_add_trace_msg((bfqd)->queue, "bfq " fmt, ##args)
++
++/* Expiration reasons. */
++enum bfqq_expiration {
++ BFQ_BFQQ_TOO_IDLE = 0, /*
++ * queue has been idling for
++ * too long
++ */
++ BFQ_BFQQ_BUDGET_TIMEOUT, /* budget took too long to be used */
++ BFQ_BFQQ_BUDGET_EXHAUSTED, /* budget consumed */
++ BFQ_BFQQ_NO_MORE_REQUESTS, /* the queue has no more requests */
++};
++
++#ifdef CONFIG_CGROUP_BFQIO
++/**
++ * struct bfq_group - per (device, cgroup) data structure.
++ * @entity: schedulable entity to insert into the parent group sched_data.
++ * @sched_data: own sched_data, to contain child entities (they may be
++ * both bfq_queues and bfq_groups).
++ * @group_node: node to be inserted into the bfqio_cgroup->group_data
++ * list of the containing cgroup's bfqio_cgroup.
++ * @bfqd_node: node to be inserted into the @bfqd->group_list list
++ * of the groups active on the same device; used for cleanup.
++ * @bfqd: the bfq_data for the device this group acts upon.
++ * @async_bfqq: array of async queues for all the tasks belonging to
++ * the group, one queue per ioprio value per ioprio_class,
++ * except for the idle class that has only one queue.
++ * @async_idle_bfqq: async queue for the idle class (ioprio is ignored).
++ * @my_entity: pointer to @entity, %NULL for the toplevel group; used
++ * to avoid too many special cases during group creation/
++ * migration.
++ * @active_entities: number of active entities belonging to the group;
++ * unused for the root group. Used to know whether there
++ * are groups with more than one active @bfq_entity
++ * (see the comments to the function
++ * bfq_bfqq_must_not_expire()).
++ *
++ * Each (device, cgroup) pair has its own bfq_group, i.e., for each cgroup
++ * there is a set of bfq_groups, each one collecting the lower-level
++ * entities belonging to the group that are acting on the same device.
++ *
++ * Locking works as follows:
++ * o @group_node is protected by the bfqio_cgroup lock, and is accessed
++ * via RCU from its readers.
++ * o @bfqd is protected by the queue lock, RCU is used to access it
++ * from the readers.
++ * o All the other fields are protected by the @bfqd queue lock.
++ */
++struct bfq_group {
++ struct bfq_entity entity;
++ struct bfq_sched_data sched_data;
++
++ struct hlist_node group_node;
++ struct hlist_node bfqd_node;
++
++ void *bfqd;
++
++ struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
++ struct bfq_queue *async_idle_bfqq;
++
++ struct bfq_entity *my_entity;
++
++ int active_entities;
++};
++
++/**
++ * struct bfqio_cgroup - bfq cgroup data structure.
++ * @css: subsystem state for bfq in the containing cgroup.
++ * @online: flag marked when the subsystem is inserted.
++ * @weight: cgroup weight.
++ * @ioprio: cgroup ioprio.
++ * @ioprio_class: cgroup ioprio_class.
++ * @lock: spinlock that protects @ioprio, @ioprio_class and @group_data.
++ * @group_data: list containing the bfq_group belonging to this cgroup.
++ *
++ * @group_data is accessed using RCU, with @lock protecting the updates,
++ * @ioprio and @ioprio_class are protected by @lock.
++ */
++struct bfqio_cgroup {
++ struct cgroup_subsys_state css;
++ bool online;
++
++ unsigned short weight, ioprio, ioprio_class;
++
++ spinlock_t lock;
++ struct hlist_head group_data;
++};
++#else
++struct bfq_group {
++ struct bfq_sched_data sched_data;
++
++ struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR];
++ struct bfq_queue *async_idle_bfqq;
++};
++#endif
++
++static inline struct bfq_service_tree *
++bfq_entity_service_tree(struct bfq_entity *entity)
++{
++ struct bfq_sched_data *sched_data = entity->sched_data;
++ unsigned int idx = entity->ioprio_class - 1;
++
++ BUG_ON(idx >= BFQ_IOPRIO_CLASSES);
++ BUG_ON(sched_data == NULL);
++
++ return sched_data->service_tree + idx;
++}
++
++static inline struct bfq_queue *bic_to_bfqq(struct bfq_io_cq *bic,
++ bool is_sync)
++{
++ return bic->bfqq[is_sync];
++}
++
++static inline void bic_set_bfqq(struct bfq_io_cq *bic,
++ struct bfq_queue *bfqq, bool is_sync)
++{
++ bic->bfqq[is_sync] = bfqq;
++}
++
++static inline struct bfq_data *bic_to_bfqd(struct bfq_io_cq *bic)
++{
++ return bic->icq.q->elevator->elevator_data;
++}
++
++/**
++ * bfq_get_bfqd_locked - get a lock to a bfqd using a RCU protected pointer.
++ * @ptr: a pointer to a bfqd.
++ * @flags: storage for the flags to be saved.
++ *
++ * This function allows bfqg->bfqd to be protected by the
++ * queue lock of the bfqd they reference; the pointer is dereferenced
++ * under RCU, so the storage for bfqd is assured to be safe as long
++ * as the RCU read side critical section does not end. After the
++ * bfqd->queue->queue_lock is taken the pointer is rechecked, to be
++ * sure that no other writer accessed it. If we raced with a writer,
++ * the function returns NULL, with the queue unlocked, otherwise it
++ * returns the dereferenced pointer, with the queue locked.
++ */
++static inline struct bfq_data *bfq_get_bfqd_locked(void **ptr,
++ unsigned long *flags)
++{
++ struct bfq_data *bfqd;
++
++ rcu_read_lock();
++ bfqd = rcu_dereference(*(struct bfq_data **)ptr);
++
++ if (bfqd != NULL) {
++ spin_lock_irqsave(bfqd->queue->queue_lock, *flags);
++ if (*ptr == bfqd)
++ goto out;
++ spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags);
++ }
++
++ bfqd = NULL;
++out:
++ rcu_read_unlock();
++ return bfqd;
++}
++
++static inline void bfq_put_bfqd_unlock(struct bfq_data *bfqd,
++ unsigned long *flags)
++{
++ spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags);
++}
++
++static void bfq_check_ioprio_change(struct bfq_io_cq *bic);
++static void bfq_put_queue(struct bfq_queue *bfqq);
++static void bfq_dispatch_insert(struct request_queue *q, struct request *rq);
++static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
++ struct bfq_group *bfqg, int is_sync,
++ struct bfq_io_cq *bic, gfp_t gfp_mask);
++static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
++ struct bfq_group *bfqg);
++static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg);
++static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq);
++
++#endif /* _BFQ_H */
+diff -Nur linux-3.14.72.orig/block/bfq-ioc.c linux-3.14.72/block/bfq-ioc.c
+--- linux-3.14.72.orig/block/bfq-ioc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/block/bfq-ioc.c 2016-06-19 22:11:55.065155743 +0200
+@@ -0,0 +1,36 @@
++/*
++ * BFQ: I/O context handling.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ */
++
++/**
++ * icq_to_bic - convert iocontext queue structure to bfq_io_cq.
++ * @icq: the iocontext queue.
++ */
++static inline struct bfq_io_cq *icq_to_bic(struct io_cq *icq)
++{
++ /* bic->icq is the first member, %NULL will convert to %NULL */
++ return container_of(icq, struct bfq_io_cq, icq);
++}
++
++/**
++ * bfq_bic_lookup - search into @ioc a bic associated to @bfqd.
++ * @bfqd: the lookup key.
++ * @ioc: the io_context of the process doing I/O.
++ *
++ * Queue lock must be held.
++ */
++static inline struct bfq_io_cq *bfq_bic_lookup(struct bfq_data *bfqd,
++ struct io_context *ioc)
++{
++ if (ioc)
++ return icq_to_bic(ioc_lookup_icq(ioc, bfqd->queue));
++ return NULL;
++}
+diff -Nur linux-3.14.72.orig/block/bfq-iosched.c linux-3.14.72/block/bfq-iosched.c
+--- linux-3.14.72.orig/block/bfq-iosched.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/block/bfq-iosched.c 2016-06-19 22:11:55.065155743 +0200
+@@ -0,0 +1,4218 @@
++/*
++ * Budget Fair Queueing (BFQ) disk scheduler.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ
++ * file.
++ *
++ * BFQ is a proportional-share storage-I/O scheduling algorithm based on
++ * the slice-by-slice service scheme of CFQ. But BFQ assigns budgets,
++ * measured in number of sectors, to processes instead of time slices. The
++ * device is not granted to the in-service process for a given time slice,
++ * but until it has exhausted its assigned budget. This change from the time
++ * to the service domain allows BFQ to distribute the device throughput
++ * among processes as desired, without any distortion due to ZBR, workload
++ * fluctuations or other factors. BFQ uses an ad hoc internal scheduler,
++ * called B-WF2Q+, to schedule processes according to their budgets. More
++ * precisely, BFQ schedules queues associated to processes. Thanks to the
++ * accurate policy of B-WF2Q+, BFQ can afford to assign high budgets to
++ * I/O-bound processes issuing sequential requests (to boost the
++ * throughput), and yet guarantee a low latency to interactive and soft
++ * real-time applications.
++ *
++ * BFQ is described in [1], where also a reference to the initial, more
++ * theoretical paper on BFQ can be found. The interested reader can find
++ * in the latter paper full details on the main algorithm, as well as
++ * formulas of the guarantees and formal proofs of all the properties.
++ * With respect to the version of BFQ presented in these papers, this
++ * implementation adds a few more heuristics, such as the one that
++ * guarantees a low latency to soft real-time applications, and a
++ * hierarchical extension based on H-WF2Q+.
++ *
++ * B-WF2Q+ is based on WF2Q+, that is described in [2], together with
++ * H-WF2Q+, while the augmented tree used to implement B-WF2Q+ with O(log N)
++ * complexity derives from the one introduced with EEVDF in [3].
++ *
++ * [1] P. Valente and M. Andreolini, ``Improving Application Responsiveness
++ * with the BFQ Disk I/O Scheduler'',
++ * Proceedings of the 5th Annual International Systems and Storage
++ * Conference (SYSTOR '12), June 2012.
++ *
++ * http://algogroup.unimo.it/people/paolo/disk_sched/bf1-v1-suite-results.pdf
++ *
++ * [2] Jon C.R. Bennett and H. Zhang, ``Hierarchical Packet Fair Queueing
++ * Algorithms,'' IEEE/ACM Transactions on Networking, 5(5):675-689,
++ * Oct 1997.
++ *
++ * http://www.cs.cmu.edu/~hzhang/papers/TON-97-Oct.ps.gz
++ *
++ * [3] I. Stoica and H. Abdel-Wahab, ``Earliest Eligible Virtual Deadline
++ * First: A Flexible and Accurate Mechanism for Proportional Share
++ * Resource Allocation,'' technical report.
++ *
++ * http://www.cs.berkeley.edu/~istoica/papers/eevdf-tr-95.pdf
++ */
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/blkdev.h>
++#include <linux/cgroup.h>
++#include <linux/elevator.h>
++#include <linux/jiffies.h>
++#include <linux/rbtree.h>
++#include <linux/ioprio.h>
++#include "bfq.h"
++#include "blk.h"
++
++/* Expiration time of sync (0) and async (1) requests, in jiffies. */
++static const int bfq_fifo_expire[2] = { HZ / 4, HZ / 8 };
++
++/* Maximum backwards seek, in KiB. */
++static const int bfq_back_max = 16 * 1024;
++
++/* Penalty of a backwards seek, in number of sectors. */
++static const int bfq_back_penalty = 2;
++
++/* Idling period duration, in jiffies. */
++static int bfq_slice_idle = HZ / 125;
++
++/* Default maximum budget values, in sectors and number of requests. */
++static const int bfq_default_max_budget = 16 * 1024;
++static const int bfq_max_budget_async_rq = 4;
++
++/*
++ * Async to sync throughput distribution is controlled as follows:
++ * when an async request is served, the entity is charged the number
++ * of sectors of the request, multiplied by the factor below
++ */
++static const int bfq_async_charge_factor = 10;
++
++/* Default timeout values, in jiffies, approximating CFQ defaults. */
++static const int bfq_timeout_sync = HZ / 8;
++static int bfq_timeout_async = HZ / 25;
++
++struct kmem_cache *bfq_pool;
++
++/* Below this threshold (in ms), we consider thinktime immediate. */
++#define BFQ_MIN_TT 2
++
++/* hw_tag detection: parallel requests threshold and min samples needed. */
++#define BFQ_HW_QUEUE_THRESHOLD 4
++#define BFQ_HW_QUEUE_SAMPLES 32
++
++#define BFQQ_SEEK_THR (sector_t)(8 * 1024)
++#define BFQQ_SEEKY(bfqq) ((bfqq)->seek_mean > BFQQ_SEEK_THR)
++
++/* Min samples used for peak rate estimation (for autotuning). */
++#define BFQ_PEAK_RATE_SAMPLES 32
++
++/* Shift used for peak rate fixed precision calculations. */
++#define BFQ_RATE_SHIFT 16
++
++/*
++ * By default, BFQ computes the duration of the weight raising for
++ * interactive applications automatically, using the following formula:
++ * duration = (R / r) * T, where r is the peak rate of the device, and
++ * R and T are two reference parameters.
++ * In particular, R is the peak rate of the reference device (see below),
++ * and T is a reference time: given the systems that are likely to be
++ * installed on the reference device according to its speed class, T is
++ * about the maximum time needed, under BFQ and while reading two files in
++ * parallel, to load typical large applications on these systems.
++ * In practice, the slower/faster the device at hand is, the more/less it
++ * takes to load applications with respect to the reference device.
++ * Accordingly, the longer/shorter BFQ grants weight raising to interactive
++ * applications.
++ *
++ * BFQ uses four different reference pairs (R, T), depending on:
++ * . whether the device is rotational or non-rotational;
++ * . whether the device is slow, such as old or portable HDDs, as well as
++ * SD cards, or fast, such as newer HDDs and SSDs.
++ *
++ * The device's speed class is dynamically (re)detected in
++ * bfq_update_peak_rate() every time the estimated peak rate is updated.
++ *
++ * In the following definitions, R_slow[0]/R_fast[0] and T_slow[0]/T_fast[0]
++ * are the reference values for a slow/fast rotational device, whereas
++ * R_slow[1]/R_fast[1] and T_slow[1]/T_fast[1] are the reference values for
++ * a slow/fast non-rotational device. Finally, device_speed_thresh are the
++ * thresholds used to switch between speed classes.
++ * Both the reference peak rates and the thresholds are measured in
++ * sectors/usec, left-shifted by BFQ_RATE_SHIFT.
++ */
++static int R_slow[2] = {1536, 10752};
++static int R_fast[2] = {17415, 34791};
++/*
++ * To improve readability, a conversion function is used to initialize the
++ * following arrays, which entails that they can be initialized only in a
++ * function.
++ */
++static int T_slow[2];
++static int T_fast[2];
++static int device_speed_thresh[2];
++
++#define BFQ_SERVICE_TREE_INIT ((struct bfq_service_tree) \
++ { RB_ROOT, RB_ROOT, NULL, NULL, 0, 0 })
++
++#define RQ_BIC(rq) ((struct bfq_io_cq *) (rq)->elv.priv[0])
++#define RQ_BFQQ(rq) ((rq)->elv.priv[1])
++
++static inline void bfq_schedule_dispatch(struct bfq_data *bfqd);
++
++#include "bfq-ioc.c"
++#include "bfq-sched.c"
++#include "bfq-cgroup.c"
++
++#define bfq_class_idle(bfqq) ((bfqq)->entity.ioprio_class ==\
++ IOPRIO_CLASS_IDLE)
++#define bfq_class_rt(bfqq) ((bfqq)->entity.ioprio_class ==\
++ IOPRIO_CLASS_RT)
++
++#define bfq_sample_valid(samples) ((samples) > 80)
++
++/*
++ * The following macro groups conditions that need to be evaluated when
++ * checking if existing queues and groups form a symmetric scenario
++ * and therefore idling can be reduced or disabled for some of the
++ * queues. See the comment to the function bfq_bfqq_must_not_expire()
++ * for further details.
++ */
++#ifdef CONFIG_CGROUP_BFQIO
++#define symmetric_scenario (!bfqd->active_numerous_groups && \
++ !bfq_differentiated_weights(bfqd))
++#else
++#define symmetric_scenario (!bfq_differentiated_weights(bfqd))
++#endif
++
++/*
++ * We regard a request as SYNC, if either it's a read or has the SYNC bit
++ * set (in which case it could also be a direct WRITE).
++ */
++static inline int bfq_bio_sync(struct bio *bio)
++{
++ if (bio_data_dir(bio) == READ || (bio->bi_rw & REQ_SYNC))
++ return 1;
++
++ return 0;
++}
++
++/*
++ * Scheduler run of queue, if there are requests pending and no one in the
++ * driver that will restart queueing.
++ */
++static inline void bfq_schedule_dispatch(struct bfq_data *bfqd)
++{
++ if (bfqd->queued != 0) {
++ bfq_log(bfqd, "schedule dispatch");
++ kblockd_schedule_work(bfqd->queue, &bfqd->unplug_work);
++ }
++}
++
++/*
++ * Lifted from AS - choose which of rq1 and rq2 that is best served now.
++ * We choose the request that is closesr to the head right now. Distance
++ * behind the head is penalized and only allowed to a certain extent.
++ */
++static struct request *bfq_choose_req(struct bfq_data *bfqd,
++ struct request *rq1,
++ struct request *rq2,
++ sector_t last)
++{
++ sector_t s1, s2, d1 = 0, d2 = 0;
++ unsigned long back_max;
++#define BFQ_RQ1_WRAP 0x01 /* request 1 wraps */
++#define BFQ_RQ2_WRAP 0x02 /* request 2 wraps */
++ unsigned wrap = 0; /* bit mask: requests behind the disk head? */
++
++ if (rq1 == NULL || rq1 == rq2)
++ return rq2;
++ if (rq2 == NULL)
++ return rq1;
++
++ if (rq_is_sync(rq1) && !rq_is_sync(rq2))
++ return rq1;
++ else if (rq_is_sync(rq2) && !rq_is_sync(rq1))
++ return rq2;
++ if ((rq1->cmd_flags & REQ_META) && !(rq2->cmd_flags & REQ_META))
++ return rq1;
++ else if ((rq2->cmd_flags & REQ_META) && !(rq1->cmd_flags & REQ_META))
++ return rq2;
++
++ s1 = blk_rq_pos(rq1);
++ s2 = blk_rq_pos(rq2);
++
++ /*
++ * By definition, 1KiB is 2 sectors.
++ */
++ back_max = bfqd->bfq_back_max * 2;
++
++ /*
++ * Strict one way elevator _except_ in the case where we allow
++ * short backward seeks which are biased as twice the cost of a
++ * similar forward seek.
++ */
++ if (s1 >= last)
++ d1 = s1 - last;
++ else if (s1 + back_max >= last)
++ d1 = (last - s1) * bfqd->bfq_back_penalty;
++ else
++ wrap |= BFQ_RQ1_WRAP;
++
++ if (s2 >= last)
++ d2 = s2 - last;
++ else if (s2 + back_max >= last)
++ d2 = (last - s2) * bfqd->bfq_back_penalty;
++ else
++ wrap |= BFQ_RQ2_WRAP;
++
++ /* Found required data */
++
++ /*
++ * By doing switch() on the bit mask "wrap" we avoid having to
++ * check two variables for all permutations: --> faster!
++ */
++ switch (wrap) {
++ case 0: /* common case for CFQ: rq1 and rq2 not wrapped */
++ if (d1 < d2)
++ return rq1;
++ else if (d2 < d1)
++ return rq2;
++ else {
++ if (s1 >= s2)
++ return rq1;
++ else
++ return rq2;
++ }
++
++ case BFQ_RQ2_WRAP:
++ return rq1;
++ case BFQ_RQ1_WRAP:
++ return rq2;
++ case (BFQ_RQ1_WRAP|BFQ_RQ2_WRAP): /* both rqs wrapped */
++ default:
++ /*
++ * Since both rqs are wrapped,
++ * start with the one that's further behind head
++ * (--> only *one* back seek required),
++ * since back seek takes more time than forward.
++ */
++ if (s1 <= s2)
++ return rq1;
++ else
++ return rq2;
++ }
++}
++
++static struct bfq_queue *
++bfq_rq_pos_tree_lookup(struct bfq_data *bfqd, struct rb_root *root,
++ sector_t sector, struct rb_node **ret_parent,
++ struct rb_node ***rb_link)
++{
++ struct rb_node **p, *parent;
++ struct bfq_queue *bfqq = NULL;
++
++ parent = NULL;
++ p = &root->rb_node;
++ while (*p) {
++ struct rb_node **n;
++
++ parent = *p;
++ bfqq = rb_entry(parent, struct bfq_queue, pos_node);
++
++ /*
++ * Sort strictly based on sector. Smallest to the left,
++ * largest to the right.
++ */
++ if (sector > blk_rq_pos(bfqq->next_rq))
++ n = &(*p)->rb_right;
++ else if (sector < blk_rq_pos(bfqq->next_rq))
++ n = &(*p)->rb_left;
++ else
++ break;
++ p = n;
++ bfqq = NULL;
++ }
++
++ *ret_parent = parent;
++ if (rb_link)
++ *rb_link = p;
++
++ bfq_log(bfqd, "rq_pos_tree_lookup %llu: returning %d",
++ (long long unsigned)sector,
++ bfqq != NULL ? bfqq->pid : 0);
++
++ return bfqq;
++}
++
++static void bfq_rq_pos_tree_add(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ struct rb_node **p, *parent;
++ struct bfq_queue *__bfqq;
++
++ if (bfqq->pos_root != NULL) {
++ rb_erase(&bfqq->pos_node, bfqq->pos_root);
++ bfqq->pos_root = NULL;
++ }
++
++ if (bfq_class_idle(bfqq))
++ return;
++ if (!bfqq->next_rq)
++ return;
++
++ bfqq->pos_root = &bfqd->rq_pos_tree;
++ __bfqq = bfq_rq_pos_tree_lookup(bfqd, bfqq->pos_root,
++ blk_rq_pos(bfqq->next_rq), &parent, &p);
++ if (__bfqq == NULL) {
++ rb_link_node(&bfqq->pos_node, parent, p);
++ rb_insert_color(&bfqq->pos_node, bfqq->pos_root);
++ } else
++ bfqq->pos_root = NULL;
++}
++
++/*
++ * Tell whether there are active queues or groups with differentiated weights.
++ */
++static inline bool bfq_differentiated_weights(struct bfq_data *bfqd)
++{
++ /*
++ * For weights to differ, at least one of the trees must contain
++ * at least two nodes.
++ */
++ return (!RB_EMPTY_ROOT(&bfqd->queue_weights_tree) &&
++ (bfqd->queue_weights_tree.rb_node->rb_left ||
++ bfqd->queue_weights_tree.rb_node->rb_right)
++#ifdef CONFIG_CGROUP_BFQIO
++ ) ||
++ (!RB_EMPTY_ROOT(&bfqd->group_weights_tree) &&
++ (bfqd->group_weights_tree.rb_node->rb_left ||
++ bfqd->group_weights_tree.rb_node->rb_right)
++#endif
++ );
++}
++
++/*
++ * If the weight-counter tree passed as input contains no counter for
++ * the weight of the input entity, then add that counter; otherwise just
++ * increment the existing counter.
++ *
++ * Note that weight-counter trees contain few nodes in mostly symmetric
++ * scenarios. For example, if all queues have the same weight, then the
++ * weight-counter tree for the queues may contain at most one node.
++ * This holds even if low_latency is on, because weight-raised queues
++ * are not inserted in the tree.
++ * In most scenarios, the rate at which nodes are created/destroyed
++ * should be low too.
++ */
++static void bfq_weights_tree_add(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root)
++{
++ struct rb_node **new = &(root->rb_node), *parent = NULL;
++
++ /*
++ * Do not insert if the entity is already associated with a
++ * counter, which happens if:
++ * 1) the entity is associated with a queue,
++ * 2) a request arrival has caused the queue to become both
++ * non-weight-raised, and hence change its weight, and
++ * backlogged; in this respect, each of the two events
++ * causes an invocation of this function,
++ * 3) this is the invocation of this function caused by the
++ * second event. This second invocation is actually useless,
++ * and we handle this fact by exiting immediately. More
++ * efficient or clearer solutions might possibly be adopted.
++ */
++ if (entity->weight_counter)
++ return;
++
++ while (*new) {
++ struct bfq_weight_counter *__counter = container_of(*new,
++ struct bfq_weight_counter,
++ weights_node);
++ parent = *new;
++
++ if (entity->weight == __counter->weight) {
++ entity->weight_counter = __counter;
++ goto inc_counter;
++ }
++ if (entity->weight < __counter->weight)
++ new = &((*new)->rb_left);
++ else
++ new = &((*new)->rb_right);
++ }
++
++ entity->weight_counter = kzalloc(sizeof(struct bfq_weight_counter),
++ GFP_ATOMIC);
++ entity->weight_counter->weight = entity->weight;
++ rb_link_node(&entity->weight_counter->weights_node, parent, new);
++ rb_insert_color(&entity->weight_counter->weights_node, root);
++
++inc_counter:
++ entity->weight_counter->num_active++;
++}
++
++/*
++ * Decrement the weight counter associated with the entity, and, if the
++ * counter reaches 0, remove the counter from the tree.
++ * See the comments to the function bfq_weights_tree_add() for considerations
++ * about overhead.
++ */
++static void bfq_weights_tree_remove(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root)
++{
++ if (!entity->weight_counter)
++ return;
++
++ BUG_ON(RB_EMPTY_ROOT(root));
++ BUG_ON(entity->weight_counter->weight != entity->weight);
++
++ BUG_ON(!entity->weight_counter->num_active);
++ entity->weight_counter->num_active--;
++ if (entity->weight_counter->num_active > 0)
++ goto reset_entity_pointer;
++
++ rb_erase(&entity->weight_counter->weights_node, root);
++ kfree(entity->weight_counter);
++
++reset_entity_pointer:
++ entity->weight_counter = NULL;
++}
++
++static struct request *bfq_find_next_rq(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct request *last)
++{
++ struct rb_node *rbnext = rb_next(&last->rb_node);
++ struct rb_node *rbprev = rb_prev(&last->rb_node);
++ struct request *next = NULL, *prev = NULL;
++
++ BUG_ON(RB_EMPTY_NODE(&last->rb_node));
++
++ if (rbprev != NULL)
++ prev = rb_entry_rq(rbprev);
++
++ if (rbnext != NULL)
++ next = rb_entry_rq(rbnext);
++ else {
++ rbnext = rb_first(&bfqq->sort_list);
++ if (rbnext && rbnext != &last->rb_node)
++ next = rb_entry_rq(rbnext);
++ }
++
++ return bfq_choose_req(bfqd, next, prev, blk_rq_pos(last));
++}
++
++/* see the definition of bfq_async_charge_factor for details */
++static inline unsigned long bfq_serv_to_charge(struct request *rq,
++ struct bfq_queue *bfqq)
++{
++ return blk_rq_sectors(rq) *
++ (1 + ((!bfq_bfqq_sync(bfqq)) * (bfqq->wr_coeff == 1) *
++ bfq_async_charge_factor));
++}
++
++/**
++ * bfq_updated_next_req - update the queue after a new next_rq selection.
++ * @bfqd: the device data the queue belongs to.
++ * @bfqq: the queue to update.
++ *
++ * If the first request of a queue changes we make sure that the queue
++ * has enough budget to serve at least its first request (if the
++ * request has grown). We do this because if the queue has not enough
++ * budget for its first request, it has to go through two dispatch
++ * rounds to actually get it dispatched.
++ */
++static void bfq_updated_next_req(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ struct bfq_service_tree *st = bfq_entity_service_tree(entity);
++ struct request *next_rq = bfqq->next_rq;
++ unsigned long new_budget;
++
++ if (next_rq == NULL)
++ return;
++
++ if (bfqq == bfqd->in_service_queue)
++ /*
++ * In order not to break guarantees, budgets cannot be
++ * changed after an entity has been selected.
++ */
++ return;
++
++ BUG_ON(entity->tree != &st->active);
++ BUG_ON(entity == entity->sched_data->in_service_entity);
++
++ new_budget = max_t(unsigned long, bfqq->max_budget,
++ bfq_serv_to_charge(next_rq, bfqq));
++ if (entity->budget != new_budget) {
++ entity->budget = new_budget;
++ bfq_log_bfqq(bfqd, bfqq, "updated next rq: new budget %lu",
++ new_budget);
++ bfq_activate_bfqq(bfqd, bfqq);
++ }
++}
++
++static inline unsigned int bfq_wr_duration(struct bfq_data *bfqd)
++{
++ u64 dur;
++
++ if (bfqd->bfq_wr_max_time > 0)
++ return bfqd->bfq_wr_max_time;
++
++ dur = bfqd->RT_prod;
++ do_div(dur, bfqd->peak_rate);
++
++ return dur;
++}
++
++static inline unsigned
++bfq_bfqq_cooperations(struct bfq_queue *bfqq)
++{
++ return bfqq->bic ? bfqq->bic->cooperations : 0;
++}
++
++static inline void
++bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct bfq_io_cq *bic)
++{
++ if (bic->saved_idle_window)
++ bfq_mark_bfqq_idle_window(bfqq);
++ else
++ bfq_clear_bfqq_idle_window(bfqq);
++ if (bic->saved_IO_bound)
++ bfq_mark_bfqq_IO_bound(bfqq);
++ else
++ bfq_clear_bfqq_IO_bound(bfqq);
++ /* Assuming that the flag in_large_burst is already correctly set */
++ if (bic->wr_time_left && bfqq->bfqd->low_latency &&
++ !bfq_bfqq_in_large_burst(bfqq) &&
++ bic->cooperations < bfqq->bfqd->bfq_coop_thresh) {
++ /*
++ * Start a weight raising period with the duration given by
++ * the raising_time_left snapshot.
++ */
++ if (bfq_bfqq_busy(bfqq))
++ bfqq->bfqd->wr_busy_queues++;
++ bfqq->wr_coeff = bfqq->bfqd->bfq_wr_coeff;
++ bfqq->wr_cur_max_time = bic->wr_time_left;
++ bfqq->last_wr_start_finish = jiffies;
++ bfqq->entity.ioprio_changed = 1;
++ }
++ /*
++ * Clear wr_time_left to prevent bfq_bfqq_save_state() from
++ * getting confused about the queue's need of a weight-raising
++ * period.
++ */
++ bic->wr_time_left = 0;
++}
++
++/* Must be called with the queue_lock held. */
++static int bfqq_process_refs(struct bfq_queue *bfqq)
++{
++ int process_refs, io_refs;
++
++ io_refs = bfqq->allocated[READ] + bfqq->allocated[WRITE];
++ process_refs = atomic_read(&bfqq->ref) - io_refs - bfqq->entity.on_st;
++ BUG_ON(process_refs < 0);
++ return process_refs;
++}
++
++/* Empty burst list and add just bfqq (see comments to bfq_handle_burst) */
++static inline void bfq_reset_burst_list(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ struct bfq_queue *item;
++ struct hlist_node *n;
++
++ hlist_for_each_entry_safe(item, n, &bfqd->burst_list, burst_list_node)
++ hlist_del_init(&item->burst_list_node);
++ hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
++ bfqd->burst_size = 1;
++}
++
++/* Add bfqq to the list of queues in current burst (see bfq_handle_burst) */
++static void bfq_add_to_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ /* Increment burst size to take into account also bfqq */
++ bfqd->burst_size++;
++
++ if (bfqd->burst_size == bfqd->bfq_large_burst_thresh) {
++ struct bfq_queue *pos, *bfqq_item;
++ struct hlist_node *n;
++
++ /*
++ * Enough queues have been activated shortly after each
++ * other to consider this burst as large.
++ */
++ bfqd->large_burst = true;
++
++ /*
++ * We can now mark all queues in the burst list as
++ * belonging to a large burst.
++ */
++ hlist_for_each_entry(bfqq_item, &bfqd->burst_list,
++ burst_list_node)
++ bfq_mark_bfqq_in_large_burst(bfqq_item);
++ bfq_mark_bfqq_in_large_burst(bfqq);
++
++ /*
++ * From now on, and until the current burst finishes, any
++ * new queue being activated shortly after the last queue
++ * was inserted in the burst can be immediately marked as
++ * belonging to a large burst. So the burst list is not
++ * needed any more. Remove it.
++ */
++ hlist_for_each_entry_safe(pos, n, &bfqd->burst_list,
++ burst_list_node)
++ hlist_del_init(&pos->burst_list_node);
++ } else /* burst not yet large: add bfqq to the burst list */
++ hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list);
++}
++
++/*
++ * If many queues happen to become active shortly after each other, then,
++ * to help the processes associated to these queues get their job done as
++ * soon as possible, it is usually better to not grant either weight-raising
++ * or device idling to these queues. In this comment we describe, firstly,
++ * the reasons why this fact holds, and, secondly, the next function, which
++ * implements the main steps needed to properly mark these queues so that
++ * they can then be treated in a different way.
++ *
++ * As for the terminology, we say that a queue becomes active, i.e.,
++ * switches from idle to backlogged, either when it is created (as a
++ * consequence of the arrival of an I/O request), or, if already existing,
++ * when a new request for the queue arrives while the queue is idle.
++ * Bursts of activations, i.e., activations of different queues occurring
++ * shortly after each other, are typically caused by services or applications
++ * that spawn or reactivate many parallel threads/processes. Examples are
++ * systemd during boot or git grep.
++ *
++ * These services or applications benefit mostly from a high throughput:
++ * the quicker the requests of the activated queues are cumulatively served,
++ * the sooner the target job of these queues gets completed. As a consequence,
++ * weight-raising any of these queues, which also implies idling the device
++ * for it, is almost always counterproductive: in most cases it just lowers
++ * throughput.
++ *
++ * On the other hand, a burst of activations may be also caused by the start
++ * of an application that does not consist in a lot of parallel I/O-bound
++ * threads. In fact, with a complex application, the burst may be just a
++ * consequence of the fact that several processes need to be executed to
++ * start-up the application. To start an application as quickly as possible,
++ * the best thing to do is to privilege the I/O related to the application
++ * with respect to all other I/O. Therefore, the best strategy to start as
++ * quickly as possible an application that causes a burst of activations is
++ * to weight-raise all the queues activated during the burst. This is the
++ * exact opposite of the best strategy for the other type of bursts.
++ *
++ * In the end, to take the best action for each of the two cases, the two
++ * types of bursts need to be distinguished. Fortunately, this seems
++ * relatively easy to do, by looking at the sizes of the bursts. In
++ * particular, we found a threshold such that bursts with a larger size
++ * than that threshold are apparently caused only by services or commands
++ * such as systemd or git grep. For brevity, hereafter we call just 'large'
++ * these bursts. BFQ *does not* weight-raise queues whose activations occur
++ * in a large burst. In addition, for each of these queues BFQ performs or
++ * does not perform idling depending on which choice boosts the throughput
++ * most. The exact choice depends on the device and request pattern at
++ * hand.
++ *
++ * Turning back to the next function, it implements all the steps needed
++ * to detect the occurrence of a large burst and to properly mark all the
++ * queues belonging to it (so that they can then be treated in a different
++ * way). This goal is achieved by maintaining a special "burst list" that
++ * holds, temporarily, the queues that belong to the burst in progress. The
++ * list is then used to mark these queues as belonging to a large burst if
++ * the burst does become large. The main steps are the following.
++ *
++ * . when the very first queue is activated, the queue is inserted into the
++ * list (as it could be the first queue in a possible burst)
++ *
++ * . if the current burst has not yet become large, and a queue Q that does
++ * not yet belong to the burst is activated shortly after the last time
++ * at which a new queue entered the burst list, then the function appends
++ * Q to the burst list
++ *
++ * . if, as a consequence of the previous step, the burst size reaches
++ * the large-burst threshold, then
++ *
++ * . all the queues in the burst list are marked as belonging to a
++ * large burst
++ *
++ * . the burst list is deleted; in fact, the burst list already served
++ * its purpose (keeping temporarily track of the queues in a burst,
++ * so as to be able to mark them as belonging to a large burst in the
++ * previous sub-step), and now is not needed any more
++ *
++ * . the device enters a large-burst mode
++ *
++ * . if a queue Q that does not belong to the burst is activated while
++ * the device is in large-burst mode and shortly after the last time
++ * at which a queue either entered the burst list or was marked as
++ * belonging to the current large burst, then Q is immediately marked
++ * as belonging to a large burst.
++ *
++ * . if a queue Q that does not belong to the burst is activated a while
++ * later, i.e., not shortly after, than the last time at which a queue
++ * either entered the burst list or was marked as belonging to the
++ * current large burst, then the current burst is deemed as finished and:
++ *
++ * . the large-burst mode is reset if set
++ *
++ * . the burst list is emptied
++ *
++ * . Q is inserted in the burst list, as Q may be the first queue
++ * in a possible new burst (then the burst list contains just Q
++ * after this step).
++ */
++static void bfq_handle_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ bool idle_for_long_time)
++{
++ /*
++ * If bfqq happened to be activated in a burst, but has been idle
++ * for at least as long as an interactive queue, then we assume
++ * that, in the overall I/O initiated in the burst, the I/O
++ * associated to bfqq is finished. So bfqq does not need to be
++ * treated as a queue belonging to a burst anymore. Accordingly,
++ * we reset bfqq's in_large_burst flag if set, and remove bfqq
++ * from the burst list if it's there. We do not decrement instead
++ * burst_size, because the fact that bfqq does not need to belong
++ * to the burst list any more does not invalidate the fact that
++ * bfqq may have been activated during the current burst.
++ */
++ if (idle_for_long_time) {
++ hlist_del_init(&bfqq->burst_list_node);
++ bfq_clear_bfqq_in_large_burst(bfqq);
++ }
++
++ /*
++ * If bfqq is already in the burst list or is part of a large
++ * burst, then there is nothing else to do.
++ */
++ if (!hlist_unhashed(&bfqq->burst_list_node) ||
++ bfq_bfqq_in_large_burst(bfqq))
++ return;
++
++ /*
++ * If bfqq's activation happens late enough, then the current
++ * burst is finished, and related data structures must be reset.
++ *
++ * In this respect, consider the special case where bfqq is the very
++ * first queue being activated. In this case, last_ins_in_burst is
++ * not yet significant when we get here. But it is easy to verify
++ * that, whether or not the following condition is true, bfqq will
++ * end up being inserted into the burst list. In particular the
++ * list will happen to contain only bfqq. And this is exactly what
++ * has to happen, as bfqq may be the first queue in a possible
++ * burst.
++ */
++ if (time_is_before_jiffies(bfqd->last_ins_in_burst +
++ bfqd->bfq_burst_interval)) {
++ bfqd->large_burst = false;
++ bfq_reset_burst_list(bfqd, bfqq);
++ return;
++ }
++
++ /*
++ * If we get here, then bfqq is being activated shortly after the
++ * last queue. So, if the current burst is also large, we can mark
++ * bfqq as belonging to this large burst immediately.
++ */
++ if (bfqd->large_burst) {
++ bfq_mark_bfqq_in_large_burst(bfqq);
++ return;
++ }
++
++ /*
++ * If we get here, then a large-burst state has not yet been
++ * reached, but bfqq is being activated shortly after the last
++ * queue. Then we add bfqq to the burst.
++ */
++ bfq_add_to_burst(bfqd, bfqq);
++}
++
++static void bfq_add_request(struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++ struct bfq_entity *entity = &bfqq->entity;
++ struct bfq_data *bfqd = bfqq->bfqd;
++ struct request *next_rq, *prev;
++ unsigned long old_wr_coeff = bfqq->wr_coeff;
++ bool interactive = false;
++
++ bfq_log_bfqq(bfqd, bfqq, "add_request %d", rq_is_sync(rq));
++ bfqq->queued[rq_is_sync(rq)]++;
++ bfqd->queued++;
++
++ elv_rb_add(&bfqq->sort_list, rq);
++
++ /*
++ * Check if this request is a better next-serve candidate.
++ */
++ prev = bfqq->next_rq;
++ next_rq = bfq_choose_req(bfqd, bfqq->next_rq, rq, bfqd->last_position);
++ BUG_ON(next_rq == NULL);
++ bfqq->next_rq = next_rq;
++
++ /*
++ * Adjust priority tree position, if next_rq changes.
++ */
++ if (prev != bfqq->next_rq)
++ bfq_rq_pos_tree_add(bfqd, bfqq);
++
++ if (!bfq_bfqq_busy(bfqq)) {
++ bool soft_rt, coop_or_in_burst,
++ idle_for_long_time = time_is_before_jiffies(
++ bfqq->budget_timeout +
++ bfqd->bfq_wr_min_idle_time);
++
++ if (bfq_bfqq_sync(bfqq)) {
++ bool already_in_burst =
++ !hlist_unhashed(&bfqq->burst_list_node) ||
++ bfq_bfqq_in_large_burst(bfqq);
++ bfq_handle_burst(bfqd, bfqq, idle_for_long_time);
++ /*
++ * If bfqq was not already in the current burst,
++ * then, at this point, bfqq either has been
++ * added to the current burst or has caused the
++ * current burst to terminate. In particular, in
++ * the second case, bfqq has become the first
++ * queue in a possible new burst.
++ * In both cases last_ins_in_burst needs to be
++ * moved forward.
++ */
++ if (!already_in_burst)
++ bfqd->last_ins_in_burst = jiffies;
++ }
++
++ coop_or_in_burst = bfq_bfqq_in_large_burst(bfqq) ||
++ bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh;
++ soft_rt = bfqd->bfq_wr_max_softrt_rate > 0 &&
++ !coop_or_in_burst &&
++ time_is_before_jiffies(bfqq->soft_rt_next_start);
++ interactive = !coop_or_in_burst && idle_for_long_time;
++ entity->budget = max_t(unsigned long, bfqq->max_budget,
++ bfq_serv_to_charge(next_rq, bfqq));
++
++ if (!bfq_bfqq_IO_bound(bfqq)) {
++ if (time_before(jiffies,
++ RQ_BIC(rq)->ttime.last_end_request +
++ bfqd->bfq_slice_idle)) {
++ bfqq->requests_within_timer++;
++ if (bfqq->requests_within_timer >=
++ bfqd->bfq_requests_within_timer)
++ bfq_mark_bfqq_IO_bound(bfqq);
++ } else
++ bfqq->requests_within_timer = 0;
++ }
++
++ if (!bfqd->low_latency)
++ goto add_bfqq_busy;
++
++ if (bfq_bfqq_just_split(bfqq))
++ goto set_ioprio_changed;
++
++ /*
++ * If the queue:
++ * - is not being boosted,
++ * - has been idle for enough time,
++ * - is not a sync queue or is linked to a bfq_io_cq (it is
++ * shared "for its nature" or it is not shared and its
++ * requests have not been redirected to a shared queue)
++ * start a weight-raising period.
++ */
++ if (old_wr_coeff == 1 && (interactive || soft_rt) &&
++ (!bfq_bfqq_sync(bfqq) || bfqq->bic != NULL)) {
++ bfqq->wr_coeff = bfqd->bfq_wr_coeff;
++ if (interactive)
++ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
++ else
++ bfqq->wr_cur_max_time =
++ bfqd->bfq_wr_rt_max_time;
++ bfq_log_bfqq(bfqd, bfqq,
++ "wrais starting at %lu, rais_max_time %u",
++ jiffies,
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ } else if (old_wr_coeff > 1) {
++ if (interactive)
++ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
++ else if (coop_or_in_burst ||
++ (bfqq->wr_cur_max_time ==
++ bfqd->bfq_wr_rt_max_time &&
++ !soft_rt)) {
++ bfqq->wr_coeff = 1;
++ bfq_log_bfqq(bfqd, bfqq,
++ "wrais ending at %lu, rais_max_time %u",
++ jiffies,
++ jiffies_to_msecs(bfqq->
++ wr_cur_max_time));
++ } else if (time_before(
++ bfqq->last_wr_start_finish +
++ bfqq->wr_cur_max_time,
++ jiffies +
++ bfqd->bfq_wr_rt_max_time) &&
++ soft_rt) {
++ /*
++ *
++ * The remaining weight-raising time is lower
++ * than bfqd->bfq_wr_rt_max_time, which means
++ * that the application is enjoying weight
++ * raising either because deemed soft-rt in
++ * the near past, or because deemed interactive
++ * a long ago.
++ * In both cases, resetting now the current
++ * remaining weight-raising time for the
++ * application to the weight-raising duration
++ * for soft rt applications would not cause any
++ * latency increase for the application (as the
++ * new duration would be higher than the
++ * remaining time).
++ *
++ * In addition, the application is now meeting
++ * the requirements for being deemed soft rt.
++ * In the end we can correctly and safely
++ * (re)charge the weight-raising duration for
++ * the application with the weight-raising
++ * duration for soft rt applications.
++ *
++ * In particular, doing this recharge now, i.e.,
++ * before the weight-raising period for the
++ * application finishes, reduces the probability
++ * of the following negative scenario:
++ * 1) the weight of a soft rt application is
++ * raised at startup (as for any newly
++ * created application),
++ * 2) since the application is not interactive,
++ * at a certain time weight-raising is
++ * stopped for the application,
++ * 3) at that time the application happens to
++ * still have pending requests, and hence
++ * is destined to not have a chance to be
++ * deemed soft rt before these requests are
++ * completed (see the comments to the
++ * function bfq_bfqq_softrt_next_start()
++ * for details on soft rt detection),
++ * 4) these pending requests experience a high
++ * latency because the application is not
++ * weight-raised while they are pending.
++ */
++ bfqq->last_wr_start_finish = jiffies;
++ bfqq->wr_cur_max_time =
++ bfqd->bfq_wr_rt_max_time;
++ }
++ }
++set_ioprio_changed:
++ if (old_wr_coeff != bfqq->wr_coeff)
++ entity->ioprio_changed = 1;
++add_bfqq_busy:
++ bfqq->last_idle_bklogged = jiffies;
++ bfqq->service_from_backlogged = 0;
++ bfq_clear_bfqq_softrt_update(bfqq);
++ bfq_add_bfqq_busy(bfqd, bfqq);
++ } else {
++ if (bfqd->low_latency && old_wr_coeff == 1 && !rq_is_sync(rq) &&
++ time_is_before_jiffies(
++ bfqq->last_wr_start_finish +
++ bfqd->bfq_wr_min_inter_arr_async)) {
++ bfqq->wr_coeff = bfqd->bfq_wr_coeff;
++ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd);
++
++ bfqd->wr_busy_queues++;
++ entity->ioprio_changed = 1;
++ bfq_log_bfqq(bfqd, bfqq,
++ "non-idle wrais starting at %lu, rais_max_time %u",
++ jiffies,
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ }
++ if (prev != bfqq->next_rq)
++ bfq_updated_next_req(bfqd, bfqq);
++ }
++
++ if (bfqd->low_latency &&
++ (old_wr_coeff == 1 || bfqq->wr_coeff == 1 || interactive))
++ bfqq->last_wr_start_finish = jiffies;
++}
++
++static struct request *bfq_find_rq_fmerge(struct bfq_data *bfqd,
++ struct bio *bio)
++{
++ struct task_struct *tsk = current;
++ struct bfq_io_cq *bic;
++ struct bfq_queue *bfqq;
++
++ bic = bfq_bic_lookup(bfqd, tsk->io_context);
++ if (bic == NULL)
++ return NULL;
++
++ bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio));
++ if (bfqq != NULL)
++ return elv_rb_find(&bfqq->sort_list, bio_end_sector(bio));
++
++ return NULL;
++}
++
++static void bfq_activate_request(struct request_queue *q, struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++
++ bfqd->rq_in_driver++;
++ bfqd->last_position = blk_rq_pos(rq) + blk_rq_sectors(rq);
++ bfq_log(bfqd, "activate_request: new bfqd->last_position %llu",
++ (long long unsigned)bfqd->last_position);
++}
++
++static inline void bfq_deactivate_request(struct request_queue *q,
++ struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++
++ BUG_ON(bfqd->rq_in_driver == 0);
++ bfqd->rq_in_driver--;
++}
++
++static void bfq_remove_request(struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++ struct bfq_data *bfqd = bfqq->bfqd;
++ const int sync = rq_is_sync(rq);
++
++ if (bfqq->next_rq == rq) {
++ bfqq->next_rq = bfq_find_next_rq(bfqd, bfqq, rq);
++ bfq_updated_next_req(bfqd, bfqq);
++ }
++
++ if (rq->queuelist.prev != &rq->queuelist)
++ list_del_init(&rq->queuelist);
++ BUG_ON(bfqq->queued[sync] == 0);
++ bfqq->queued[sync]--;
++ bfqd->queued--;
++ elv_rb_del(&bfqq->sort_list, rq);
++
++ if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
++ if (bfq_bfqq_busy(bfqq) && bfqq != bfqd->in_service_queue)
++ bfq_del_bfqq_busy(bfqd, bfqq, 1);
++ /*
++ * Remove queue from request-position tree as it is empty.
++ */
++ if (bfqq->pos_root != NULL) {
++ rb_erase(&bfqq->pos_node, bfqq->pos_root);
++ bfqq->pos_root = NULL;
++ }
++ }
++
++ if (rq->cmd_flags & REQ_META) {
++ BUG_ON(bfqq->meta_pending == 0);
++ bfqq->meta_pending--;
++ }
++}
++
++static int bfq_merge(struct request_queue *q, struct request **req,
++ struct bio *bio)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct request *__rq;
++
++ __rq = bfq_find_rq_fmerge(bfqd, bio);
++ if (__rq != NULL && elv_rq_merge_ok(__rq, bio)) {
++ *req = __rq;
++ return ELEVATOR_FRONT_MERGE;
++ }
++
++ return ELEVATOR_NO_MERGE;
++}
++
++static void bfq_merged_request(struct request_queue *q, struct request *req,
++ int type)
++{
++ if (type == ELEVATOR_FRONT_MERGE &&
++ rb_prev(&req->rb_node) &&
++ blk_rq_pos(req) <
++ blk_rq_pos(container_of(rb_prev(&req->rb_node),
++ struct request, rb_node))) {
++ struct bfq_queue *bfqq = RQ_BFQQ(req);
++ struct bfq_data *bfqd = bfqq->bfqd;
++ struct request *prev, *next_rq;
++
++ /* Reposition request in its sort_list */
++ elv_rb_del(&bfqq->sort_list, req);
++ elv_rb_add(&bfqq->sort_list, req);
++ /* Choose next request to be served for bfqq */
++ prev = bfqq->next_rq;
++ next_rq = bfq_choose_req(bfqd, bfqq->next_rq, req,
++ bfqd->last_position);
++ BUG_ON(next_rq == NULL);
++ bfqq->next_rq = next_rq;
++ /*
++ * If next_rq changes, update both the queue's budget to
++ * fit the new request and the queue's position in its
++ * rq_pos_tree.
++ */
++ if (prev != bfqq->next_rq) {
++ bfq_updated_next_req(bfqd, bfqq);
++ bfq_rq_pos_tree_add(bfqd, bfqq);
++ }
++ }
++}
++
++static void bfq_merged_requests(struct request_queue *q, struct request *rq,
++ struct request *next)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq), *next_bfqq = RQ_BFQQ(next);
++
++ /*
++ * If next and rq belong to the same bfq_queue and next is older
++ * than rq, then reposition rq in the fifo (by substituting next
++ * with rq). Otherwise, if next and rq belong to different
++ * bfq_queues, never reposition rq: in fact, we would have to
++ * reposition it with respect to next's position in its own fifo,
++ * which would most certainly be too expensive with respect to
++ * the benefits.
++ */
++ if (bfqq == next_bfqq &&
++ !list_empty(&rq->queuelist) && !list_empty(&next->queuelist) &&
++ time_before(rq_fifo_time(next), rq_fifo_time(rq))) {
++ list_del_init(&rq->queuelist);
++ list_replace_init(&next->queuelist, &rq->queuelist);
++ rq_set_fifo_time(rq, rq_fifo_time(next));
++ }
++
++ if (bfqq->next_rq == next)
++ bfqq->next_rq = rq;
++
++ bfq_remove_request(next);
++}
++
++/* Must be called with bfqq != NULL */
++static inline void bfq_bfqq_end_wr(struct bfq_queue *bfqq)
++{
++ BUG_ON(bfqq == NULL);
++ if (bfq_bfqq_busy(bfqq))
++ bfqq->bfqd->wr_busy_queues--;
++ bfqq->wr_coeff = 1;
++ bfqq->wr_cur_max_time = 0;
++ /* Trigger a weight change on the next activation of the queue */
++ bfqq->entity.ioprio_changed = 1;
++}
++
++static void bfq_end_wr_async_queues(struct bfq_data *bfqd,
++ struct bfq_group *bfqg)
++{
++ int i, j;
++
++ for (i = 0; i < 2; i++)
++ for (j = 0; j < IOPRIO_BE_NR; j++)
++ if (bfqg->async_bfqq[i][j] != NULL)
++ bfq_bfqq_end_wr(bfqg->async_bfqq[i][j]);
++ if (bfqg->async_idle_bfqq != NULL)
++ bfq_bfqq_end_wr(bfqg->async_idle_bfqq);
++}
++
++static void bfq_end_wr(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq;
++
++ spin_lock_irq(bfqd->queue->queue_lock);
++
++ list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list)
++ bfq_bfqq_end_wr(bfqq);
++ list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list)
++ bfq_bfqq_end_wr(bfqq);
++ bfq_end_wr_async(bfqd);
++
++ spin_unlock_irq(bfqd->queue->queue_lock);
++}
++
++static inline sector_t bfq_io_struct_pos(void *io_struct, bool request)
++{
++ if (request)
++ return blk_rq_pos(io_struct);
++ else
++ return ((struct bio *)io_struct)->bi_iter.bi_sector;
++}
++
++static inline sector_t bfq_dist_from(sector_t pos1,
++ sector_t pos2)
++{
++ if (pos1 >= pos2)
++ return pos1 - pos2;
++ else
++ return pos2 - pos1;
++}
++
++static inline int bfq_rq_close_to_sector(void *io_struct, bool request,
++ sector_t sector)
++{
++ return bfq_dist_from(bfq_io_struct_pos(io_struct, request), sector) <=
++ BFQQ_SEEK_THR;
++}
++
++static struct bfq_queue *bfqq_close(struct bfq_data *bfqd, sector_t sector)
++{
++ struct rb_root *root = &bfqd->rq_pos_tree;
++ struct rb_node *parent, *node;
++ struct bfq_queue *__bfqq;
++
++ if (RB_EMPTY_ROOT(root))
++ return NULL;
++
++ /*
++ * First, if we find a request starting at the end of the last
++ * request, choose it.
++ */
++ __bfqq = bfq_rq_pos_tree_lookup(bfqd, root, sector, &parent, NULL);
++ if (__bfqq != NULL)
++ return __bfqq;
++
++ /*
++ * If the exact sector wasn't found, the parent of the NULL leaf
++ * will contain the closest sector (rq_pos_tree sorted by
++ * next_request position).
++ */
++ __bfqq = rb_entry(parent, struct bfq_queue, pos_node);
++ if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
++ return __bfqq;
++
++ if (blk_rq_pos(__bfqq->next_rq) < sector)
++ node = rb_next(&__bfqq->pos_node);
++ else
++ node = rb_prev(&__bfqq->pos_node);
++ if (node == NULL)
++ return NULL;
++
++ __bfqq = rb_entry(node, struct bfq_queue, pos_node);
++ if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector))
++ return __bfqq;
++
++ return NULL;
++}
++
++/*
++ * bfqd - obvious
++ * cur_bfqq - passed in so that we don't decide that the current queue
++ * is closely cooperating with itself
++ * sector - used as a reference point to search for a close queue
++ */
++static struct bfq_queue *bfq_close_cooperator(struct bfq_data *bfqd,
++ struct bfq_queue *cur_bfqq,
++ sector_t sector)
++{
++ struct bfq_queue *bfqq;
++
++ if (bfq_class_idle(cur_bfqq))
++ return NULL;
++ if (!bfq_bfqq_sync(cur_bfqq))
++ return NULL;
++ if (BFQQ_SEEKY(cur_bfqq))
++ return NULL;
++
++ /* If device has only one backlogged bfq_queue, don't search. */
++ if (bfqd->busy_queues == 1)
++ return NULL;
++
++ /*
++ * We should notice if some of the queues are cooperating, e.g.
++ * working closely on the same area of the disk. In that case,
++ * we can group them together and don't waste time idling.
++ */
++ bfqq = bfqq_close(bfqd, sector);
++ if (bfqq == NULL || bfqq == cur_bfqq)
++ return NULL;
++
++ /*
++ * Do not merge queues from different bfq_groups.
++ */
++ if (bfqq->entity.parent != cur_bfqq->entity.parent)
++ return NULL;
++
++ /*
++ * It only makes sense to merge sync queues.
++ */
++ if (!bfq_bfqq_sync(bfqq))
++ return NULL;
++ if (BFQQ_SEEKY(bfqq))
++ return NULL;
++
++ /*
++ * Do not merge queues of different priority classes.
++ */
++ if (bfq_class_rt(bfqq) != bfq_class_rt(cur_bfqq))
++ return NULL;
++
++ return bfqq;
++}
++
++static struct bfq_queue *
++bfq_setup_merge(struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
++{
++ int process_refs, new_process_refs;
++ struct bfq_queue *__bfqq;
++
++ /*
++ * If there are no process references on the new_bfqq, then it is
++ * unsafe to follow the ->new_bfqq chain as other bfqq's in the chain
++ * may have dropped their last reference (not just their last process
++ * reference).
++ */
++ if (!bfqq_process_refs(new_bfqq))
++ return NULL;
++
++ /* Avoid a circular list and skip interim queue merges. */
++ while ((__bfqq = new_bfqq->new_bfqq)) {
++ if (__bfqq == bfqq)
++ return NULL;
++ new_bfqq = __bfqq;
++ }
++
++ process_refs = bfqq_process_refs(bfqq);
++ new_process_refs = bfqq_process_refs(new_bfqq);
++ /*
++ * If the process for the bfqq has gone away, there is no
++ * sense in merging the queues.
++ */
++ if (process_refs == 0 || new_process_refs == 0)
++ return NULL;
++
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "scheduling merge with queue %d",
++ new_bfqq->pid);
++
++ /*
++ * Merging is just a redirection: the requests of the process
++ * owning one of the two queues are redirected to the other queue.
++ * The latter queue, in its turn, is set as shared if this is the
++ * first time that the requests of some process are redirected to
++ * it.
++ *
++ * We redirect bfqq to new_bfqq and not the opposite, because we
++ * are in the context of the process owning bfqq, hence we have
++ * the io_cq of this process. So we can immediately configure this
++ * io_cq to redirect the requests of the process to new_bfqq.
++ *
++ * NOTE, even if new_bfqq coincides with the in-service queue, the
++ * io_cq of new_bfqq is not available, because, if the in-service
++ * queue is shared, bfqd->in_service_bic may not point to the
++ * io_cq of the in-service queue.
++ * Redirecting the requests of the process owning bfqq to the
++ * currently in-service queue is in any case the best option, as
++ * we feed the in-service queue with new requests close to the
++ * last request served and, by doing so, hopefully increase the
++ * throughput.
++ */
++ bfqq->new_bfqq = new_bfqq;
++ atomic_add(process_refs, &new_bfqq->ref);
++ return new_bfqq;
++}
++
++/*
++ * Attempt to schedule a merge of bfqq with the currently in-service queue
++ * or with a close queue among the scheduled queues.
++ * Return NULL if no merge was scheduled, a pointer to the shared bfq_queue
++ * structure otherwise.
++ *
++ * The OOM queue is not allowed to participate to cooperation: in fact, since
++ * the requests temporarily redirected to the OOM queue could be redirected
++ * again to dedicated queues at any time, the state needed to correctly
++ * handle merging with the OOM queue would be quite complex and expensive
++ * to maintain. Besides, in such a critical condition as an out of memory,
++ * the benefits of queue merging may be little relevant, or even negligible.
++ */
++static struct bfq_queue *
++bfq_setup_cooperator(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ void *io_struct, bool request)
++{
++ struct bfq_queue *in_service_bfqq, *new_bfqq;
++
++ if (bfqq->new_bfqq)
++ return bfqq->new_bfqq;
++
++ if (!io_struct || unlikely(bfqq == &bfqd->oom_bfqq))
++ return NULL;
++
++ in_service_bfqq = bfqd->in_service_queue;
++
++ if (in_service_bfqq == NULL || in_service_bfqq == bfqq ||
++ !bfqd->in_service_bic ||
++ unlikely(in_service_bfqq == &bfqd->oom_bfqq))
++ goto check_scheduled;
++
++ if (bfq_class_idle(in_service_bfqq) || bfq_class_idle(bfqq))
++ goto check_scheduled;
++
++ if (bfq_class_rt(in_service_bfqq) != bfq_class_rt(bfqq))
++ goto check_scheduled;
++
++ if (in_service_bfqq->entity.parent != bfqq->entity.parent)
++ goto check_scheduled;
++
++ if (bfq_rq_close_to_sector(io_struct, request, bfqd->last_position) &&
++ bfq_bfqq_sync(in_service_bfqq) && bfq_bfqq_sync(bfqq)) {
++ new_bfqq = bfq_setup_merge(bfqq, in_service_bfqq);
++ if (new_bfqq != NULL)
++ return new_bfqq; /* Merge with in-service queue */
++ }
++
++ /*
++ * Check whether there is a cooperator among currently scheduled
++ * queues. The only thing we need is that the bio/request is not
++ * NULL, as we need it to establish whether a cooperator exists.
++ */
++check_scheduled:
++ new_bfqq = bfq_close_cooperator(bfqd, bfqq,
++ bfq_io_struct_pos(io_struct, request));
++ if (new_bfqq && likely(new_bfqq != &bfqd->oom_bfqq))
++ return bfq_setup_merge(bfqq, new_bfqq);
++
++ return NULL;
++}
++
++static inline void
++bfq_bfqq_save_state(struct bfq_queue *bfqq)
++{
++ /*
++ * If bfqq->bic == NULL, the queue is already shared or its requests
++ * have already been redirected to a shared queue; both idle window
++ * and weight raising state have already been saved. Do nothing.
++ */
++ if (bfqq->bic == NULL)
++ return;
++ if (bfqq->bic->wr_time_left)
++ /*
++ * This is the queue of a just-started process, and would
++ * deserve weight raising: we set wr_time_left to the full
++ * weight-raising duration to trigger weight-raising when
++ * and if the queue is split and the first request of the
++ * queue is enqueued.
++ */
++ bfqq->bic->wr_time_left = bfq_wr_duration(bfqq->bfqd);
++ else if (bfqq->wr_coeff > 1) {
++ unsigned long wr_duration =
++ jiffies - bfqq->last_wr_start_finish;
++ /*
++ * It may happen that a queue's weight raising period lasts
++ * longer than its wr_cur_max_time, as weight raising is
++ * handled only when a request is enqueued or dispatched (it
++ * does not use any timer). If the weight raising period is
++ * about to end, don't save it.
++ */
++ if (bfqq->wr_cur_max_time <= wr_duration)
++ bfqq->bic->wr_time_left = 0;
++ else
++ bfqq->bic->wr_time_left =
++ bfqq->wr_cur_max_time - wr_duration;
++ /*
++ * The bfq_queue is becoming shared or the requests of the
++ * process owning the queue are being redirected to a shared
++ * queue. Stop the weight raising period of the queue, as in
++ * both cases it should not be owned by an interactive or
++ * soft real-time application.
++ */
++ bfq_bfqq_end_wr(bfqq);
++ } else
++ bfqq->bic->wr_time_left = 0;
++ bfqq->bic->saved_idle_window = bfq_bfqq_idle_window(bfqq);
++ bfqq->bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq);
++ bfqq->bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq);
++ bfqq->bic->was_in_burst_list = !hlist_unhashed(&bfqq->burst_list_node);
++ bfqq->bic->cooperations++;
++ bfqq->bic->failed_cooperations = 0;
++}
++
++static inline void
++bfq_get_bic_reference(struct bfq_queue *bfqq)
++{
++ /*
++ * If bfqq->bic has a non-NULL value, the bic to which it belongs
++ * is about to begin using a shared bfq_queue.
++ */
++ if (bfqq->bic)
++ atomic_long_inc(&bfqq->bic->icq.ioc->refcount);
++}
++
++static void
++bfq_merge_bfqqs(struct bfq_data *bfqd, struct bfq_io_cq *bic,
++ struct bfq_queue *bfqq, struct bfq_queue *new_bfqq)
++{
++ bfq_log_bfqq(bfqd, bfqq, "merging with queue %lu",
++ (long unsigned)new_bfqq->pid);
++ /* Save weight raising and idle window of the merged queues */
++ bfq_bfqq_save_state(bfqq);
++ bfq_bfqq_save_state(new_bfqq);
++ if (bfq_bfqq_IO_bound(bfqq))
++ bfq_mark_bfqq_IO_bound(new_bfqq);
++ bfq_clear_bfqq_IO_bound(bfqq);
++ /*
++ * Grab a reference to the bic, to prevent it from being destroyed
++ * before being possibly touched by a bfq_split_bfqq().
++ */
++ bfq_get_bic_reference(bfqq);
++ bfq_get_bic_reference(new_bfqq);
++ /*
++ * Merge queues (that is, let bic redirect its requests to new_bfqq)
++ */
++ bic_set_bfqq(bic, new_bfqq, 1);
++ bfq_mark_bfqq_coop(new_bfqq);
++ /*
++ * new_bfqq now belongs to at least two bics (it is a shared queue):
++ * set new_bfqq->bic to NULL. bfqq either:
++ * - does not belong to any bic any more, and hence bfqq->bic must
++ * be set to NULL, or
++ * - is a queue whose owning bics have already been redirected to a
++ * different queue, hence the queue is destined to not belong to
++ * any bic soon and bfqq->bic is already NULL (therefore the next
++ * assignment causes no harm).
++ */
++ new_bfqq->bic = NULL;
++ bfqq->bic = NULL;
++ bfq_put_queue(bfqq);
++}
++
++static inline void bfq_bfqq_increase_failed_cooperations(struct bfq_queue *bfqq)
++{
++ struct bfq_io_cq *bic = bfqq->bic;
++ struct bfq_data *bfqd = bfqq->bfqd;
++
++ if (bic && bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh) {
++ bic->failed_cooperations++;
++ if (bic->failed_cooperations >= bfqd->bfq_failed_cooperations)
++ bic->cooperations = 0;
++ }
++}
++
++static int bfq_allow_merge(struct request_queue *q, struct request *rq,
++ struct bio *bio)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_io_cq *bic;
++ struct bfq_queue *bfqq, *new_bfqq;
++
++ /*
++ * Disallow merge of a sync bio into an async request.
++ */
++ if (bfq_bio_sync(bio) && !rq_is_sync(rq))
++ return 0;
++
++ /*
++ * Lookup the bfqq that this bio will be queued with. Allow
++ * merge only if rq is queued there.
++ * Queue lock is held here.
++ */
++ bic = bfq_bic_lookup(bfqd, current->io_context);
++ if (bic == NULL)
++ return 0;
++
++ bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio));
++ /*
++ * We take advantage of this function to perform an early merge
++ * of the queues of possible cooperating processes.
++ */
++ if (bfqq != NULL) {
++ new_bfqq = bfq_setup_cooperator(bfqd, bfqq, bio, false);
++ if (new_bfqq != NULL) {
++ bfq_merge_bfqqs(bfqd, bic, bfqq, new_bfqq);
++ /*
++ * If we get here, the bio will be queued in the
++ * shared queue, i.e., new_bfqq, so use new_bfqq
++ * to decide whether bio and rq can be merged.
++ */
++ bfqq = new_bfqq;
++ } else
++ bfq_bfqq_increase_failed_cooperations(bfqq);
++ }
++
++ return bfqq == RQ_BFQQ(rq);
++}
++
++static void __bfq_set_in_service_queue(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ if (bfqq != NULL) {
++ bfq_mark_bfqq_must_alloc(bfqq);
++ bfq_mark_bfqq_budget_new(bfqq);
++ bfq_clear_bfqq_fifo_expire(bfqq);
++
++ bfqd->budgets_assigned = (bfqd->budgets_assigned*7 + 256) / 8;
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "set_in_service_queue, cur-budget = %lu",
++ bfqq->entity.budget);
++ }
++
++ bfqd->in_service_queue = bfqq;
++}
++
++/*
++ * Get and set a new queue for service.
++ */
++static struct bfq_queue *bfq_set_in_service_queue(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq = bfq_get_next_queue(bfqd);
++
++ __bfq_set_in_service_queue(bfqd, bfqq);
++ return bfqq;
++}
++
++/*
++ * If enough samples have been computed, return the current max budget
++ * stored in bfqd, which is dynamically updated according to the
++ * estimated disk peak rate; otherwise return the default max budget
++ */
++static inline unsigned long bfq_max_budget(struct bfq_data *bfqd)
++{
++ if (bfqd->budgets_assigned < 194)
++ return bfq_default_max_budget;
++ else
++ return bfqd->bfq_max_budget;
++}
++
++/*
++ * Return min budget, which is a fraction of the current or default
++ * max budget (trying with 1/32)
++ */
++static inline unsigned long bfq_min_budget(struct bfq_data *bfqd)
++{
++ if (bfqd->budgets_assigned < 194)
++ return bfq_default_max_budget / 32;
++ else
++ return bfqd->bfq_max_budget / 32;
++}
++
++static void bfq_arm_slice_timer(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq = bfqd->in_service_queue;
++ struct bfq_io_cq *bic;
++ unsigned long sl;
++
++ BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
++
++ /* Processes have exited, don't wait. */
++ bic = bfqd->in_service_bic;
++ if (bic == NULL || atomic_read(&bic->icq.ioc->active_ref) == 0)
++ return;
++
++ bfq_mark_bfqq_wait_request(bfqq);
++
++ /*
++ * We don't want to idle for seeks, but we do want to allow
++ * fair distribution of slice time for a process doing back-to-back
++ * seeks. So allow a little bit of time for him to submit a new rq.
++ *
++ * To prevent processes with (partly) seeky workloads from
++ * being too ill-treated, grant them a small fraction of the
++ * assigned budget before reducing the waiting time to
++ * BFQ_MIN_TT. This happened to help reduce latency.
++ */
++ sl = bfqd->bfq_slice_idle;
++ /*
++ * Unless the queue is being weight-raised or the scenario is
++ * asymmetric, grant only minimum idle time if the queue either
++ * has been seeky for long enough or has already proved to be
++ * constantly seeky.
++ */
++ if (bfq_sample_valid(bfqq->seek_samples) &&
++ ((BFQQ_SEEKY(bfqq) && bfqq->entity.service >
++ bfq_max_budget(bfqq->bfqd) / 8) ||
++ bfq_bfqq_constantly_seeky(bfqq)) && bfqq->wr_coeff == 1 &&
++ symmetric_scenario)
++ sl = min(sl, msecs_to_jiffies(BFQ_MIN_TT));
++ else if (bfqq->wr_coeff > 1)
++ sl = sl * 3;
++ bfqd->last_idling_start = ktime_get();
++ mod_timer(&bfqd->idle_slice_timer, jiffies + sl);
++ bfq_log(bfqd, "arm idle: %u/%u ms",
++ jiffies_to_msecs(sl), jiffies_to_msecs(bfqd->bfq_slice_idle));
++}
++
++/*
++ * Set the maximum time for the in-service queue to consume its
++ * budget. This prevents seeky processes from lowering the disk
++ * throughput (always guaranteed with a time slice scheme as in CFQ).
++ */
++static void bfq_set_budget_timeout(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq = bfqd->in_service_queue;
++ unsigned int timeout_coeff;
++ if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time)
++ timeout_coeff = 1;
++ else
++ timeout_coeff = bfqq->entity.weight / bfqq->entity.orig_weight;
++
++ bfqd->last_budget_start = ktime_get();
++
++ bfq_clear_bfqq_budget_new(bfqq);
++ bfqq->budget_timeout = jiffies +
++ bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] * timeout_coeff;
++
++ bfq_log_bfqq(bfqd, bfqq, "set budget_timeout %u",
++ jiffies_to_msecs(bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] *
++ timeout_coeff));
++}
++
++/*
++ * Move request from internal lists to the request queue dispatch list.
++ */
++static void bfq_dispatch_insert(struct request_queue *q, struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++
++ /*
++ * For consistency, the next instruction should have been executed
++ * after removing the request from the queue and dispatching it.
++ * We execute instead this instruction before bfq_remove_request()
++ * (and hence introduce a temporary inconsistency), for efficiency.
++ * In fact, in a forced_dispatch, this prevents two counters related
++ * to bfqq->dispatched to risk to be uselessly decremented if bfqq
++ * is not in service, and then to be incremented again after
++ * incrementing bfqq->dispatched.
++ */
++ bfqq->dispatched++;
++ bfq_remove_request(rq);
++ elv_dispatch_sort(q, rq);
++
++ if (bfq_bfqq_sync(bfqq))
++ bfqd->sync_flight++;
++}
++
++/*
++ * Return expired entry, or NULL to just start from scratch in rbtree.
++ */
++static struct request *bfq_check_fifo(struct bfq_queue *bfqq)
++{
++ struct request *rq = NULL;
++
++ if (bfq_bfqq_fifo_expire(bfqq))
++ return NULL;
++
++ bfq_mark_bfqq_fifo_expire(bfqq);
++
++ if (list_empty(&bfqq->fifo))
++ return NULL;
++
++ rq = rq_entry_fifo(bfqq->fifo.next);
++
++ if (time_before(jiffies, rq_fifo_time(rq)))
++ return NULL;
++
++ return rq;
++}
++
++static inline unsigned long bfq_bfqq_budget_left(struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ return entity->budget - entity->service;
++}
++
++static void __bfq_bfqq_expire(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ BUG_ON(bfqq != bfqd->in_service_queue);
++
++ __bfq_bfqd_reset_in_service(bfqd);
++
++ /*
++ * If this bfqq is shared between multiple processes, check
++ * to make sure that those processes are still issuing I/Os
++ * within the mean seek distance. If not, it may be time to
++ * break the queues apart again.
++ */
++ if (bfq_bfqq_coop(bfqq) && BFQQ_SEEKY(bfqq))
++ bfq_mark_bfqq_split_coop(bfqq);
++
++ if (RB_EMPTY_ROOT(&bfqq->sort_list)) {
++ /*
++ * Overloading budget_timeout field to store the time
++ * at which the queue remains with no backlog; used by
++ * the weight-raising mechanism.
++ */
++ bfqq->budget_timeout = jiffies;
++ bfq_del_bfqq_busy(bfqd, bfqq, 1);
++ } else {
++ bfq_activate_bfqq(bfqd, bfqq);
++ /*
++ * Resort priority tree of potential close cooperators.
++ */
++ bfq_rq_pos_tree_add(bfqd, bfqq);
++ }
++}
++
++/**
++ * __bfq_bfqq_recalc_budget - try to adapt the budget to the @bfqq behavior.
++ * @bfqd: device data.
++ * @bfqq: queue to update.
++ * @reason: reason for expiration.
++ *
++ * Handle the feedback on @bfqq budget. See the body for detailed
++ * comments.
++ */
++static void __bfq_bfqq_recalc_budget(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ enum bfqq_expiration reason)
++{
++ struct request *next_rq;
++ unsigned long budget, min_budget;
++
++ budget = bfqq->max_budget;
++ min_budget = bfq_min_budget(bfqd);
++
++ BUG_ON(bfqq != bfqd->in_service_queue);
++
++ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last budg %lu, budg left %lu",
++ bfqq->entity.budget, bfq_bfqq_budget_left(bfqq));
++ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last max_budg %lu, min budg %lu",
++ budget, bfq_min_budget(bfqd));
++ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: sync %d, seeky %d",
++ bfq_bfqq_sync(bfqq), BFQQ_SEEKY(bfqd->in_service_queue));
++
++ if (bfq_bfqq_sync(bfqq)) {
++ switch (reason) {
++ /*
++ * Caveat: in all the following cases we trade latency
++ * for throughput.
++ */
++ case BFQ_BFQQ_TOO_IDLE:
++ /*
++ * This is the only case where we may reduce
++ * the budget: if there is no request of the
++ * process still waiting for completion, then
++ * we assume (tentatively) that the timer has
++ * expired because the batch of requests of
++ * the process could have been served with a
++ * smaller budget. Hence, betting that
++ * process will behave in the same way when it
++ * becomes backlogged again, we reduce its
++ * next budget. As long as we guess right,
++ * this budget cut reduces the latency
++ * experienced by the process.
++ *
++ * However, if there are still outstanding
++ * requests, then the process may have not yet
++ * issued its next request just because it is
++ * still waiting for the completion of some of
++ * the still outstanding ones. So in this
++ * subcase we do not reduce its budget, on the
++ * contrary we increase it to possibly boost
++ * the throughput, as discussed in the
++ * comments to the BUDGET_TIMEOUT case.
++ */
++ if (bfqq->dispatched > 0) /* still outstanding reqs */
++ budget = min(budget * 2, bfqd->bfq_max_budget);
++ else {
++ if (budget > 5 * min_budget)
++ budget -= 4 * min_budget;
++ else
++ budget = min_budget;
++ }
++ break;
++ case BFQ_BFQQ_BUDGET_TIMEOUT:
++ /*
++ * We double the budget here because: 1) it
++ * gives the chance to boost the throughput if
++ * this is not a seeky process (which may have
++ * bumped into this timeout because of, e.g.,
++ * ZBR), 2) together with charge_full_budget
++ * it helps give seeky processes higher
++ * timestamps, and hence be served less
++ * frequently.
++ */
++ budget = min(budget * 2, bfqd->bfq_max_budget);
++ break;
++ case BFQ_BFQQ_BUDGET_EXHAUSTED:
++ /*
++ * The process still has backlog, and did not
++ * let either the budget timeout or the disk
++ * idling timeout expire. Hence it is not
++ * seeky, has a short thinktime and may be
++ * happy with a higher budget too. So
++ * definitely increase the budget of this good
++ * candidate to boost the disk throughput.
++ */
++ budget = min(budget * 4, bfqd->bfq_max_budget);
++ break;
++ case BFQ_BFQQ_NO_MORE_REQUESTS:
++ /*
++ * Leave the budget unchanged.
++ */
++ default:
++ return;
++ }
++ } else /* async queue */
++ /* async queues get always the maximum possible budget
++ * (their ability to dispatch is limited by
++ * @bfqd->bfq_max_budget_async_rq).
++ */
++ budget = bfqd->bfq_max_budget;
++
++ bfqq->max_budget = budget;
++
++ if (bfqd->budgets_assigned >= 194 && bfqd->bfq_user_max_budget == 0 &&
++ bfqq->max_budget > bfqd->bfq_max_budget)
++ bfqq->max_budget = bfqd->bfq_max_budget;
++
++ /*
++ * Make sure that we have enough budget for the next request.
++ * Since the finish time of the bfqq must be kept in sync with
++ * the budget, be sure to call __bfq_bfqq_expire() after the
++ * update.
++ */
++ next_rq = bfqq->next_rq;
++ if (next_rq != NULL)
++ bfqq->entity.budget = max_t(unsigned long, bfqq->max_budget,
++ bfq_serv_to_charge(next_rq, bfqq));
++ else
++ bfqq->entity.budget = bfqq->max_budget;
++
++ bfq_log_bfqq(bfqd, bfqq, "head sect: %u, new budget %lu",
++ next_rq != NULL ? blk_rq_sectors(next_rq) : 0,
++ bfqq->entity.budget);
++}
++
++static unsigned long bfq_calc_max_budget(u64 peak_rate, u64 timeout)
++{
++ unsigned long max_budget;
++
++ /*
++ * The max_budget calculated when autotuning is equal to the
++ * amount of sectors transfered in timeout_sync at the
++ * estimated peak rate.
++ */
++ max_budget = (unsigned long)(peak_rate * 1000 *
++ timeout >> BFQ_RATE_SHIFT);
++
++ return max_budget;
++}
++
++/*
++ * In addition to updating the peak rate, checks whether the process
++ * is "slow", and returns 1 if so. This slow flag is used, in addition
++ * to the budget timeout, to reduce the amount of service provided to
++ * seeky processes, and hence reduce their chances to lower the
++ * throughput. See the code for more details.
++ */
++static int bfq_update_peak_rate(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ int compensate, enum bfqq_expiration reason)
++{
++ u64 bw, usecs, expected, timeout;
++ ktime_t delta;
++ int update = 0;
++
++ if (!bfq_bfqq_sync(bfqq) || bfq_bfqq_budget_new(bfqq))
++ return 0;
++
++ if (compensate)
++ delta = bfqd->last_idling_start;
++ else
++ delta = ktime_get();
++ delta = ktime_sub(delta, bfqd->last_budget_start);
++ usecs = ktime_to_us(delta);
++
++ /* Don't trust short/unrealistic values. */
++ if (usecs < 100 || usecs >= LONG_MAX)
++ return 0;
++
++ /*
++ * Calculate the bandwidth for the last slice. We use a 64 bit
++ * value to store the peak rate, in sectors per usec in fixed
++ * point math. We do so to have enough precision in the estimate
++ * and to avoid overflows.
++ */
++ bw = (u64)bfqq->entity.service << BFQ_RATE_SHIFT;
++ do_div(bw, (unsigned long)usecs);
++
++ timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]);
++
++ /*
++ * Use only long (> 20ms) intervals to filter out spikes for
++ * the peak rate estimation.
++ */
++ if (usecs > 20000) {
++ if (bw > bfqd->peak_rate ||
++ (!BFQQ_SEEKY(bfqq) &&
++ reason == BFQ_BFQQ_BUDGET_TIMEOUT)) {
++ bfq_log(bfqd, "measured bw =%llu", bw);
++ /*
++ * To smooth oscillations use a low-pass filter with
++ * alpha=7/8, i.e.,
++ * new_rate = (7/8) * old_rate + (1/8) * bw
++ */
++ do_div(bw, 8);
++ if (bw == 0)
++ return 0;
++ bfqd->peak_rate *= 7;
++ do_div(bfqd->peak_rate, 8);
++ bfqd->peak_rate += bw;
++ update = 1;
++ bfq_log(bfqd, "new peak_rate=%llu", bfqd->peak_rate);
++ }
++
++ update |= bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES - 1;
++
++ if (bfqd->peak_rate_samples < BFQ_PEAK_RATE_SAMPLES)
++ bfqd->peak_rate_samples++;
++
++ if (bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES &&
++ update) {
++ int dev_type = blk_queue_nonrot(bfqd->queue);
++ if (bfqd->bfq_user_max_budget == 0) {
++ bfqd->bfq_max_budget =
++ bfq_calc_max_budget(bfqd->peak_rate,
++ timeout);
++ bfq_log(bfqd, "new max_budget=%lu",
++ bfqd->bfq_max_budget);
++ }
++ if (bfqd->device_speed == BFQ_BFQD_FAST &&
++ bfqd->peak_rate < device_speed_thresh[dev_type]) {
++ bfqd->device_speed = BFQ_BFQD_SLOW;
++ bfqd->RT_prod = R_slow[dev_type] *
++ T_slow[dev_type];
++ } else if (bfqd->device_speed == BFQ_BFQD_SLOW &&
++ bfqd->peak_rate > device_speed_thresh[dev_type]) {
++ bfqd->device_speed = BFQ_BFQD_FAST;
++ bfqd->RT_prod = R_fast[dev_type] *
++ T_fast[dev_type];
++ }
++ }
++ }
++
++ /*
++ * If the process has been served for a too short time
++ * interval to let its possible sequential accesses prevail on
++ * the initial seek time needed to move the disk head on the
++ * first sector it requested, then give the process a chance
++ * and for the moment return false.
++ */
++ if (bfqq->entity.budget <= bfq_max_budget(bfqd) / 8)
++ return 0;
++
++ /*
++ * A process is considered ``slow'' (i.e., seeky, so that we
++ * cannot treat it fairly in the service domain, as it would
++ * slow down too much the other processes) if, when a slice
++ * ends for whatever reason, it has received service at a
++ * rate that would not be high enough to complete the budget
++ * before the budget timeout expiration.
++ */
++ expected = bw * 1000 * timeout >> BFQ_RATE_SHIFT;
++
++ /*
++ * Caveat: processes doing IO in the slower disk zones will
++ * tend to be slow(er) even if not seeky. And the estimated
++ * peak rate will actually be an average over the disk
++ * surface. Hence, to not be too harsh with unlucky processes,
++ * we keep a budget/3 margin of safety before declaring a
++ * process slow.
++ */
++ return expected > (4 * bfqq->entity.budget) / 3;
++}
++
++/*
++ * To be deemed as soft real-time, an application must meet two
++ * requirements. First, the application must not require an average
++ * bandwidth higher than the approximate bandwidth required to playback or
++ * record a compressed high-definition video.
++ * The next function is invoked on the completion of the last request of a
++ * batch, to compute the next-start time instant, soft_rt_next_start, such
++ * that, if the next request of the application does not arrive before
++ * soft_rt_next_start, then the above requirement on the bandwidth is met.
++ *
++ * The second requirement is that the request pattern of the application is
++ * isochronous, i.e., that, after issuing a request or a batch of requests,
++ * the application stops issuing new requests until all its pending requests
++ * have been completed. After that, the application may issue a new batch,
++ * and so on.
++ * For this reason the next function is invoked to compute
++ * soft_rt_next_start only for applications that meet this requirement,
++ * whereas soft_rt_next_start is set to infinity for applications that do
++ * not.
++ *
++ * Unfortunately, even a greedy application may happen to behave in an
++ * isochronous way if the CPU load is high. In fact, the application may
++ * stop issuing requests while the CPUs are busy serving other processes,
++ * then restart, then stop again for a while, and so on. In addition, if
++ * the disk achieves a low enough throughput with the request pattern
++ * issued by the application (e.g., because the request pattern is random
++ * and/or the device is slow), then the application may meet the above
++ * bandwidth requirement too. To prevent such a greedy application to be
++ * deemed as soft real-time, a further rule is used in the computation of
++ * soft_rt_next_start: soft_rt_next_start must be higher than the current
++ * time plus the maximum time for which the arrival of a request is waited
++ * for when a sync queue becomes idle, namely bfqd->bfq_slice_idle.
++ * This filters out greedy applications, as the latter issue instead their
++ * next request as soon as possible after the last one has been completed
++ * (in contrast, when a batch of requests is completed, a soft real-time
++ * application spends some time processing data).
++ *
++ * Unfortunately, the last filter may easily generate false positives if
++ * only bfqd->bfq_slice_idle is used as a reference time interval and one
++ * or both the following cases occur:
++ * 1) HZ is so low that the duration of a jiffy is comparable to or higher
++ * than bfqd->bfq_slice_idle. This happens, e.g., on slow devices with
++ * HZ=100.
++ * 2) jiffies, instead of increasing at a constant rate, may stop increasing
++ * for a while, then suddenly 'jump' by several units to recover the lost
++ * increments. This seems to happen, e.g., inside virtual machines.
++ * To address this issue, we do not use as a reference time interval just
++ * bfqd->bfq_slice_idle, but bfqd->bfq_slice_idle plus a few jiffies. In
++ * particular we add the minimum number of jiffies for which the filter
++ * seems to be quite precise also in embedded systems and KVM/QEMU virtual
++ * machines.
++ */
++static inline unsigned long bfq_bfqq_softrt_next_start(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ return max(bfqq->last_idle_bklogged +
++ HZ * bfqq->service_from_backlogged /
++ bfqd->bfq_wr_max_softrt_rate,
++ jiffies + bfqq->bfqd->bfq_slice_idle + 4);
++}
++
++/*
++ * Return the largest-possible time instant such that, for as long as possible,
++ * the current time will be lower than this time instant according to the macro
++ * time_is_before_jiffies().
++ */
++static inline unsigned long bfq_infinity_from_now(unsigned long now)
++{
++ return now + ULONG_MAX / 2;
++}
++
++/**
++ * bfq_bfqq_expire - expire a queue.
++ * @bfqd: device owning the queue.
++ * @bfqq: the queue to expire.
++ * @compensate: if true, compensate for the time spent idling.
++ * @reason: the reason causing the expiration.
++ *
++ *
++ * If the process associated to the queue is slow (i.e., seeky), or in
++ * case of budget timeout, or, finally, if it is async, we
++ * artificially charge it an entire budget (independently of the
++ * actual service it received). As a consequence, the queue will get
++ * higher timestamps than the correct ones upon reactivation, and
++ * hence it will be rescheduled as if it had received more service
++ * than what it actually received. In the end, this class of processes
++ * will receive less service in proportion to how slowly they consume
++ * their budgets (and hence how seriously they tend to lower the
++ * throughput).
++ *
++ * In contrast, when a queue expires because it has been idling for
++ * too much or because it exhausted its budget, we do not touch the
++ * amount of service it has received. Hence when the queue will be
++ * reactivated and its timestamps updated, the latter will be in sync
++ * with the actual service received by the queue until expiration.
++ *
++ * Charging a full budget to the first type of queues and the exact
++ * service to the others has the effect of using the WF2Q+ policy to
++ * schedule the former on a timeslice basis, without violating the
++ * service domain guarantees of the latter.
++ */
++static void bfq_bfqq_expire(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ int compensate,
++ enum bfqq_expiration reason)
++{
++ int slow;
++ BUG_ON(bfqq != bfqd->in_service_queue);
++
++ /* Update disk peak rate for autotuning and check whether the
++ * process is slow (see bfq_update_peak_rate).
++ */
++ slow = bfq_update_peak_rate(bfqd, bfqq, compensate, reason);
++
++ /*
++ * As above explained, 'punish' slow (i.e., seeky), timed-out
++ * and async queues, to favor sequential sync workloads.
++ *
++ * Processes doing I/O in the slower disk zones will tend to be
++ * slow(er) even if not seeky. Hence, since the estimated peak
++ * rate is actually an average over the disk surface, these
++ * processes may timeout just for bad luck. To avoid punishing
++ * them we do not charge a full budget to a process that
++ * succeeded in consuming at least 2/3 of its budget.
++ */
++ if (slow || (reason == BFQ_BFQQ_BUDGET_TIMEOUT &&
++ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3))
++ bfq_bfqq_charge_full_budget(bfqq);
++
++ bfqq->service_from_backlogged += bfqq->entity.service;
++
++ if (BFQQ_SEEKY(bfqq) && reason == BFQ_BFQQ_BUDGET_TIMEOUT &&
++ !bfq_bfqq_constantly_seeky(bfqq)) {
++ bfq_mark_bfqq_constantly_seeky(bfqq);
++ if (!blk_queue_nonrot(bfqd->queue))
++ bfqd->const_seeky_busy_in_flight_queues++;
++ }
++
++ if (reason == BFQ_BFQQ_TOO_IDLE &&
++ bfqq->entity.service <= 2 * bfqq->entity.budget / 10 )
++ bfq_clear_bfqq_IO_bound(bfqq);
++
++ if (bfqd->low_latency && bfqq->wr_coeff == 1)
++ bfqq->last_wr_start_finish = jiffies;
++
++ if (bfqd->low_latency && bfqd->bfq_wr_max_softrt_rate > 0 &&
++ RB_EMPTY_ROOT(&bfqq->sort_list)) {
++ /*
++ * If we get here, and there are no outstanding requests,
++ * then the request pattern is isochronous (see the comments
++ * to the function bfq_bfqq_softrt_next_start()). Hence we
++ * can compute soft_rt_next_start. If, instead, the queue
++ * still has outstanding requests, then we have to wait
++ * for the completion of all the outstanding requests to
++ * discover whether the request pattern is actually
++ * isochronous.
++ */
++ if (bfqq->dispatched == 0)
++ bfqq->soft_rt_next_start =
++ bfq_bfqq_softrt_next_start(bfqd, bfqq);
++ else {
++ /*
++ * The application is still waiting for the
++ * completion of one or more requests:
++ * prevent it from possibly being incorrectly
++ * deemed as soft real-time by setting its
++ * soft_rt_next_start to infinity. In fact,
++ * without this assignment, the application
++ * would be incorrectly deemed as soft
++ * real-time if:
++ * 1) it issued a new request before the
++ * completion of all its in-flight
++ * requests, and
++ * 2) at that time, its soft_rt_next_start
++ * happened to be in the past.
++ */
++ bfqq->soft_rt_next_start =
++ bfq_infinity_from_now(jiffies);
++ /*
++ * Schedule an update of soft_rt_next_start to when
++ * the task may be discovered to be isochronous.
++ */
++ bfq_mark_bfqq_softrt_update(bfqq);
++ }
++ }
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "expire (%d, slow %d, num_disp %d, idle_win %d)", reason,
++ slow, bfqq->dispatched, bfq_bfqq_idle_window(bfqq));
++
++ /*
++ * Increase, decrease or leave budget unchanged according to
++ * reason.
++ */
++ __bfq_bfqq_recalc_budget(bfqd, bfqq, reason);
++ __bfq_bfqq_expire(bfqd, bfqq);
++}
++
++/*
++ * Budget timeout is not implemented through a dedicated timer, but
++ * just checked on request arrivals and completions, as well as on
++ * idle timer expirations.
++ */
++static int bfq_bfqq_budget_timeout(struct bfq_queue *bfqq)
++{
++ if (bfq_bfqq_budget_new(bfqq) ||
++ time_before(jiffies, bfqq->budget_timeout))
++ return 0;
++ return 1;
++}
++
++/*
++ * If we expire a queue that is waiting for the arrival of a new
++ * request, we may prevent the fictitious timestamp back-shifting that
++ * allows the guarantees of the queue to be preserved (see [1] for
++ * this tricky aspect). Hence we return true only if this condition
++ * does not hold, or if the queue is slow enough to deserve only to be
++ * kicked off for preserving a high throughput.
++*/
++static inline int bfq_may_expire_for_budg_timeout(struct bfq_queue *bfqq)
++{
++ bfq_log_bfqq(bfqq->bfqd, bfqq,
++ "may_budget_timeout: wait_request %d left %d timeout %d",
++ bfq_bfqq_wait_request(bfqq),
++ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3,
++ bfq_bfqq_budget_timeout(bfqq));
++
++ return (!bfq_bfqq_wait_request(bfqq) ||
++ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3)
++ &&
++ bfq_bfqq_budget_timeout(bfqq);
++}
++
++/*
++ * Device idling is allowed only for the queues for which this function
++ * returns true. For this reason, the return value of this function plays a
++ * critical role for both throughput boosting and service guarantees. The
++ * return value is computed through a logical expression. In this rather
++ * long comment, we try to briefly describe all the details and motivations
++ * behind the components of this logical expression.
++ *
++ * First, the expression is false if bfqq is not sync, or if: bfqq happened
++ * to become active during a large burst of queue activations, and the
++ * pattern of requests bfqq contains boosts the throughput if bfqq is
++ * expired. In fact, queues that became active during a large burst benefit
++ * only from throughput, as discussed in the comments to bfq_handle_burst.
++ * In this respect, expiring bfqq certainly boosts the throughput on NCQ-
++ * capable flash-based devices, whereas, on rotational devices, it boosts
++ * the throughput only if bfqq contains random requests.
++ *
++ * On the opposite end, if (a) bfqq is sync, (b) the above burst-related
++ * condition does not hold, and (c) bfqq is being weight-raised, then the
++ * expression always evaluates to true, as device idling is instrumental
++ * for preserving low-latency guarantees (see [1]). If, instead, conditions
++ * (a) and (b) do hold, but (c) does not, then the expression evaluates to
++ * true only if: (1) bfqq is I/O-bound and has a non-null idle window, and
++ * (2) at least one of the following two conditions holds.
++ * The first condition is that the device is not performing NCQ, because
++ * idling the device most certainly boosts the throughput if this condition
++ * holds and bfqq is I/O-bound and has been granted a non-null idle window.
++ * The second compound condition is made of the logical AND of two components.
++ *
++ * The first component is true only if there is no weight-raised busy
++ * queue. This guarantees that the device is not idled for a sync non-
++ * weight-raised queue when there are busy weight-raised queues. The former
++ * is then expired immediately if empty. Combined with the timestamping
++ * rules of BFQ (see [1] for details), this causes sync non-weight-raised
++ * queues to get a lower number of requests served, and hence to ask for a
++ * lower number of requests from the request pool, before the busy weight-
++ * raised queues get served again.
++ *
++ * This is beneficial for the processes associated with weight-raised
++ * queues, when the request pool is saturated (e.g., in the presence of
++ * write hogs). In fact, if the processes associated with the other queues
++ * ask for requests at a lower rate, then weight-raised processes have a
++ * higher probability to get a request from the pool immediately (or at
++ * least soon) when they need one. Hence they have a higher probability to
++ * actually get a fraction of the disk throughput proportional to their
++ * high weight. This is especially true with NCQ-capable drives, which
++ * enqueue several requests in advance and further reorder internally-
++ * queued requests.
++ *
++ * In the end, mistreating non-weight-raised queues when there are busy
++ * weight-raised queues seems to mitigate starvation problems in the
++ * presence of heavy write workloads and NCQ, and hence to guarantee a
++ * higher application and system responsiveness in these hostile scenarios.
++ *
++ * If the first component of the compound condition is instead true, i.e.,
++ * there is no weight-raised busy queue, then the second component of the
++ * compound condition takes into account service-guarantee and throughput
++ * issues related to NCQ (recall that the compound condition is evaluated
++ * only if the device is detected as supporting NCQ).
++ *
++ * As for service guarantees, allowing the drive to enqueue more than one
++ * request at a time, and hence delegating de facto final scheduling
++ * decisions to the drive's internal scheduler, causes loss of control on
++ * the actual request service order. In this respect, when the drive is
++ * allowed to enqueue more than one request at a time, the service
++ * distribution enforced by the drive's internal scheduler is likely to
++ * coincide with the desired device-throughput distribution only in the
++ * following, perfectly symmetric, scenario:
++ * 1) all active queues have the same weight,
++ * 2) all active groups at the same level in the groups tree have the same
++ * weight,
++ * 3) all active groups at the same level in the groups tree have the same
++ * number of children.
++ *
++ * Even in such a scenario, sequential I/O may still receive a preferential
++ * treatment, but this is not likely to be a big issue with flash-based
++ * devices, because of their non-dramatic loss of throughput with random
++ * I/O. Things do differ with HDDs, for which additional care is taken, as
++ * explained after completing the discussion for flash-based devices.
++ *
++ * Unfortunately, keeping the necessary state for evaluating exactly the
++ * above symmetry conditions would be quite complex and time-consuming.
++ * Therefore BFQ evaluates instead the following stronger sub-conditions,
++ * for which it is much easier to maintain the needed state:
++ * 1) all active queues have the same weight,
++ * 2) all active groups have the same weight,
++ * 3) all active groups have at most one active child each.
++ * In particular, the last two conditions are always true if hierarchical
++ * support and the cgroups interface are not enabled, hence no state needs
++ * to be maintained in this case.
++ *
++ * According to the above considerations, the second component of the
++ * compound condition evaluates to true if any of the above symmetry
++ * sub-condition does not hold, or the device is not flash-based. Therefore,
++ * if also the first component is true, then idling is allowed for a sync
++ * queue. These are the only sub-conditions considered if the device is
++ * flash-based, as, for such a device, it is sensible to force idling only
++ * for service-guarantee issues. In fact, as for throughput, idling
++ * NCQ-capable flash-based devices would not boost the throughput even
++ * with sequential I/O; rather it would lower the throughput in proportion
++ * to how fast the device is. In the end, (only) if all the three
++ * sub-conditions hold and the device is flash-based, the compound
++ * condition evaluates to false and therefore no idling is performed.
++ *
++ * As already said, things change with a rotational device, where idling
++ * boosts the throughput with sequential I/O (even with NCQ). Hence, for
++ * such a device the second component of the compound condition evaluates
++ * to true also if the following additional sub-condition does not hold:
++ * the queue is constantly seeky. Unfortunately, this different behavior
++ * with respect to flash-based devices causes an additional asymmetry: if
++ * some sync queues enjoy idling and some other sync queues do not, then
++ * the latter get a low share of the device throughput, simply because the
++ * former get many requests served after being set as in service, whereas
++ * the latter do not. As a consequence, to guarantee the desired throughput
++ * distribution, on HDDs the compound expression evaluates to true (and
++ * hence device idling is performed) also if the following last symmetry
++ * condition does not hold: no other queue is benefiting from idling. Also
++ * this last condition is actually replaced with a simpler-to-maintain and
++ * stronger condition: there is no busy queue which is not constantly seeky
++ * (and hence may also benefit from idling).
++ *
++ * To sum up, when all the required symmetry and throughput-boosting
++ * sub-conditions hold, the second component of the compound condition
++ * evaluates to false, and hence no idling is performed. This helps to
++ * keep the drives' internal queues full on NCQ-capable devices, and hence
++ * to boost the throughput, without causing 'almost' any loss of service
++ * guarantees. The 'almost' follows from the fact that, if the internal
++ * queue of one such device is filled while all the sub-conditions hold,
++ * but at some point in time some sub-condition stops to hold, then it may
++ * become impossible to let requests be served in the new desired order
++ * until all the requests already queued in the device have been served.
++ */
++static inline bool bfq_bfqq_must_not_expire(struct bfq_queue *bfqq)
++{
++ struct bfq_data *bfqd = bfqq->bfqd;
++#define cond_for_seeky_on_ncq_hdd (bfq_bfqq_constantly_seeky(bfqq) && \
++ bfqd->busy_in_flight_queues == \
++ bfqd->const_seeky_busy_in_flight_queues)
++
++#define cond_for_expiring_in_burst (bfq_bfqq_in_large_burst(bfqq) && \
++ bfqd->hw_tag && \
++ (blk_queue_nonrot(bfqd->queue) || \
++ bfq_bfqq_constantly_seeky(bfqq)))
++
++/*
++ * Condition for expiring a non-weight-raised queue (and hence not idling
++ * the device).
++ */
++#define cond_for_expiring_non_wr (bfqd->hw_tag && \
++ (bfqd->wr_busy_queues > 0 || \
++ (blk_queue_nonrot(bfqd->queue) || \
++ cond_for_seeky_on_ncq_hdd)))
++
++ return bfq_bfqq_sync(bfqq) &&
++ !cond_for_expiring_in_burst &&
++ (bfqq->wr_coeff > 1 || !symmetric_scenario ||
++ (bfq_bfqq_IO_bound(bfqq) && bfq_bfqq_idle_window(bfqq) &&
++ !cond_for_expiring_non_wr)
++ );
++}
++
++/*
++ * If the in-service queue is empty but sync, and the function
++ * bfq_bfqq_must_not_expire returns true, then:
++ * 1) the queue must remain in service and cannot be expired, and
++ * 2) the disk must be idled to wait for the possible arrival of a new
++ * request for the queue.
++ * See the comments to the function bfq_bfqq_must_not_expire for the reasons
++ * why performing device idling is the best choice to boost the throughput
++ * and preserve service guarantees when bfq_bfqq_must_not_expire itself
++ * returns true.
++ */
++static inline bool bfq_bfqq_must_idle(struct bfq_queue *bfqq)
++{
++ struct bfq_data *bfqd = bfqq->bfqd;
++
++ return RB_EMPTY_ROOT(&bfqq->sort_list) && bfqd->bfq_slice_idle != 0 &&
++ bfq_bfqq_must_not_expire(bfqq);
++}
++
++/*
++ * Select a queue for service. If we have a current queue in service,
++ * check whether to continue servicing it, or retrieve and set a new one.
++ */
++static struct bfq_queue *bfq_select_queue(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq;
++ struct request *next_rq;
++ enum bfqq_expiration reason = BFQ_BFQQ_BUDGET_TIMEOUT;
++
++ bfqq = bfqd->in_service_queue;
++ if (bfqq == NULL)
++ goto new_queue;
++
++ bfq_log_bfqq(bfqd, bfqq, "select_queue: already in-service queue");
++
++ if (bfq_may_expire_for_budg_timeout(bfqq) &&
++ !timer_pending(&bfqd->idle_slice_timer) &&
++ !bfq_bfqq_must_idle(bfqq))
++ goto expire;
++
++ next_rq = bfqq->next_rq;
++ /*
++ * If bfqq has requests queued and it has enough budget left to
++ * serve them, keep the queue, otherwise expire it.
++ */
++ if (next_rq != NULL) {
++ if (bfq_serv_to_charge(next_rq, bfqq) >
++ bfq_bfqq_budget_left(bfqq)) {
++ reason = BFQ_BFQQ_BUDGET_EXHAUSTED;
++ goto expire;
++ } else {
++ /*
++ * The idle timer may be pending because we may
++ * not disable disk idling even when a new request
++ * arrives.
++ */
++ if (timer_pending(&bfqd->idle_slice_timer)) {
++ /*
++ * If we get here: 1) at least a new request
++ * has arrived but we have not disabled the
++ * timer because the request was too small,
++ * 2) then the block layer has unplugged
++ * the device, causing the dispatch to be
++ * invoked.
++ *
++ * Since the device is unplugged, now the
++ * requests are probably large enough to
++ * provide a reasonable throughput.
++ * So we disable idling.
++ */
++ bfq_clear_bfqq_wait_request(bfqq);
++ del_timer(&bfqd->idle_slice_timer);
++ }
++ goto keep_queue;
++ }
++ }
++
++ /*
++ * No requests pending. However, if the in-service queue is idling
++ * for a new request, or has requests waiting for a completion and
++ * may idle after their completion, then keep it anyway.
++ */
++ if (timer_pending(&bfqd->idle_slice_timer) ||
++ (bfqq->dispatched != 0 && bfq_bfqq_must_not_expire(bfqq))) {
++ bfqq = NULL;
++ goto keep_queue;
++ }
++
++ reason = BFQ_BFQQ_NO_MORE_REQUESTS;
++expire:
++ bfq_bfqq_expire(bfqd, bfqq, 0, reason);
++new_queue:
++ bfqq = bfq_set_in_service_queue(bfqd);
++ bfq_log(bfqd, "select_queue: new queue %d returned",
++ bfqq != NULL ? bfqq->pid : 0);
++keep_queue:
++ return bfqq;
++}
++
++static void bfq_update_wr_data(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ if (bfqq->wr_coeff > 1) { /* queue is being weight-raised */
++ bfq_log_bfqq(bfqd, bfqq,
++ "raising period dur %u/%u msec, old coeff %u, w %d(%d)",
++ jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
++ jiffies_to_msecs(bfqq->wr_cur_max_time),
++ bfqq->wr_coeff,
++ bfqq->entity.weight, bfqq->entity.orig_weight);
++
++ BUG_ON(bfqq != bfqd->in_service_queue && entity->weight !=
++ entity->orig_weight * bfqq->wr_coeff);
++ if (entity->ioprio_changed)
++ bfq_log_bfqq(bfqd, bfqq, "WARN: pending prio change");
++
++ /*
++ * If the queue was activated in a burst, or
++ * too much time has elapsed from the beginning
++ * of this weight-raising period, or the queue has
++ * exceeded the acceptable number of cooperations,
++ * then end weight raising.
++ */
++ if (bfq_bfqq_in_large_burst(bfqq) ||
++ bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh ||
++ time_is_before_jiffies(bfqq->last_wr_start_finish +
++ bfqq->wr_cur_max_time)) {
++ bfqq->last_wr_start_finish = jiffies;
++ bfq_log_bfqq(bfqd, bfqq,
++ "wrais ending at %lu, rais_max_time %u",
++ bfqq->last_wr_start_finish,
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ bfq_bfqq_end_wr(bfqq);
++ }
++ }
++ /* Update weight both if it must be raised and if it must be lowered */
++ if ((entity->weight > entity->orig_weight) != (bfqq->wr_coeff > 1))
++ __bfq_entity_update_weight_prio(
++ bfq_entity_service_tree(entity),
++ entity);
++}
++
++/*
++ * Dispatch one request from bfqq, moving it to the request queue
++ * dispatch list.
++ */
++static int bfq_dispatch_request(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq)
++{
++ int dispatched = 0;
++ struct request *rq;
++ unsigned long service_to_charge;
++
++ BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list));
++
++ /* Follow expired path, else get first next available. */
++ rq = bfq_check_fifo(bfqq);
++ if (rq == NULL)
++ rq = bfqq->next_rq;
++ service_to_charge = bfq_serv_to_charge(rq, bfqq);
++
++ if (service_to_charge > bfq_bfqq_budget_left(bfqq)) {
++ /*
++ * This may happen if the next rq is chosen in fifo order
++ * instead of sector order. The budget is properly
++ * dimensioned to be always sufficient to serve the next
++ * request only if it is chosen in sector order. The reason
++ * is that it would be quite inefficient and little useful
++ * to always make sure that the budget is large enough to
++ * serve even the possible next rq in fifo order.
++ * In fact, requests are seldom served in fifo order.
++ *
++ * Expire the queue for budget exhaustion, and make sure
++ * that the next act_budget is enough to serve the next
++ * request, even if it comes from the fifo expired path.
++ */
++ bfqq->next_rq = rq;
++ /*
++ * Since this dispatch is failed, make sure that
++ * a new one will be performed
++ */
++ if (!bfqd->rq_in_driver)
++ bfq_schedule_dispatch(bfqd);
++ goto expire;
++ }
++
++ /* Finally, insert request into driver dispatch list. */
++ bfq_bfqq_served(bfqq, service_to_charge);
++ bfq_dispatch_insert(bfqd->queue, rq);
++
++ bfq_update_wr_data(bfqd, bfqq);
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "dispatched %u sec req (%llu), budg left %lu",
++ blk_rq_sectors(rq),
++ (long long unsigned)blk_rq_pos(rq),
++ bfq_bfqq_budget_left(bfqq));
++
++ dispatched++;
++
++ if (bfqd->in_service_bic == NULL) {
++ atomic_long_inc(&RQ_BIC(rq)->icq.ioc->refcount);
++ bfqd->in_service_bic = RQ_BIC(rq);
++ }
++
++ if (bfqd->busy_queues > 1 && ((!bfq_bfqq_sync(bfqq) &&
++ dispatched >= bfqd->bfq_max_budget_async_rq) ||
++ bfq_class_idle(bfqq)))
++ goto expire;
++
++ return dispatched;
++
++expire:
++ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_EXHAUSTED);
++ return dispatched;
++}
++
++static int __bfq_forced_dispatch_bfqq(struct bfq_queue *bfqq)
++{
++ int dispatched = 0;
++
++ while (bfqq->next_rq != NULL) {
++ bfq_dispatch_insert(bfqq->bfqd->queue, bfqq->next_rq);
++ dispatched++;
++ }
++
++ BUG_ON(!list_empty(&bfqq->fifo));
++ return dispatched;
++}
++
++/*
++ * Drain our current requests.
++ * Used for barriers and when switching io schedulers on-the-fly.
++ */
++static int bfq_forced_dispatch(struct bfq_data *bfqd)
++{
++ struct bfq_queue *bfqq, *n;
++ struct bfq_service_tree *st;
++ int dispatched = 0;
++
++ bfqq = bfqd->in_service_queue;
++ if (bfqq != NULL)
++ __bfq_bfqq_expire(bfqd, bfqq);
++
++ /*
++ * Loop through classes, and be careful to leave the scheduler
++ * in a consistent state, as feedback mechanisms and vtime
++ * updates cannot be disabled during the process.
++ */
++ list_for_each_entry_safe(bfqq, n, &bfqd->active_list, bfqq_list) {
++ st = bfq_entity_service_tree(&bfqq->entity);
++
++ dispatched += __bfq_forced_dispatch_bfqq(bfqq);
++ bfqq->max_budget = bfq_max_budget(bfqd);
++
++ bfq_forget_idle(st);
++ }
++
++ BUG_ON(bfqd->busy_queues != 0);
++
++ return dispatched;
++}
++
++static int bfq_dispatch_requests(struct request_queue *q, int force)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_queue *bfqq;
++ int max_dispatch;
++
++ bfq_log(bfqd, "dispatch requests: %d busy queues", bfqd->busy_queues);
++ if (bfqd->busy_queues == 0)
++ return 0;
++
++ if (unlikely(force))
++ return bfq_forced_dispatch(bfqd);
++
++ bfqq = bfq_select_queue(bfqd);
++ if (bfqq == NULL)
++ return 0;
++
++ if (bfq_class_idle(bfqq))
++ max_dispatch = 1;
++
++ if (!bfq_bfqq_sync(bfqq))
++ max_dispatch = bfqd->bfq_max_budget_async_rq;
++
++ if (!bfq_bfqq_sync(bfqq) && bfqq->dispatched >= max_dispatch) {
++ if (bfqd->busy_queues > 1)
++ return 0;
++ if (bfqq->dispatched >= 4 * max_dispatch)
++ return 0;
++ }
++
++ if (bfqd->sync_flight != 0 && !bfq_bfqq_sync(bfqq))
++ return 0;
++
++ bfq_clear_bfqq_wait_request(bfqq);
++ BUG_ON(timer_pending(&bfqd->idle_slice_timer));
++
++ if (!bfq_dispatch_request(bfqd, bfqq))
++ return 0;
++
++ bfq_log_bfqq(bfqd, bfqq, "dispatched %s request",
++ bfq_bfqq_sync(bfqq) ? "sync" : "async");
++
++ return 1;
++}
++
++/*
++ * Task holds one reference to the queue, dropped when task exits. Each rq
++ * in-flight on this queue also holds a reference, dropped when rq is freed.
++ *
++ * Queue lock must be held here.
++ */
++static void bfq_put_queue(struct bfq_queue *bfqq)
++{
++ struct bfq_data *bfqd = bfqq->bfqd;
++
++ BUG_ON(atomic_read(&bfqq->ref) <= 0);
++
++ bfq_log_bfqq(bfqd, bfqq, "put_queue: %p %d", bfqq,
++ atomic_read(&bfqq->ref));
++ if (!atomic_dec_and_test(&bfqq->ref))
++ return;
++
++ BUG_ON(rb_first(&bfqq->sort_list) != NULL);
++ BUG_ON(bfqq->allocated[READ] + bfqq->allocated[WRITE] != 0);
++ BUG_ON(bfqq->entity.tree != NULL);
++ BUG_ON(bfq_bfqq_busy(bfqq));
++ BUG_ON(bfqd->in_service_queue == bfqq);
++
++ if (bfq_bfqq_sync(bfqq))
++ /*
++ * The fact that this queue is being destroyed does not
++ * invalidate the fact that this queue may have been
++ * activated during the current burst. As a consequence,
++ * although the queue does not exist anymore, and hence
++ * needs to be removed from the burst list if there,
++ * the burst size has not to be decremented.
++ */
++ hlist_del_init(&bfqq->burst_list_node);
++
++ bfq_log_bfqq(bfqd, bfqq, "put_queue: %p freed", bfqq);
++
++ kmem_cache_free(bfq_pool, bfqq);
++}
++
++static void bfq_put_cooperator(struct bfq_queue *bfqq)
++{
++ struct bfq_queue *__bfqq, *next;
++
++ /*
++ * If this queue was scheduled to merge with another queue, be
++ * sure to drop the reference taken on that queue (and others in
++ * the merge chain). See bfq_setup_merge and bfq_merge_bfqqs.
++ */
++ __bfqq = bfqq->new_bfqq;
++ while (__bfqq) {
++ if (__bfqq == bfqq)
++ break;
++ next = __bfqq->new_bfqq;
++ bfq_put_queue(__bfqq);
++ __bfqq = next;
++ }
++}
++
++static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ if (bfqq == bfqd->in_service_queue) {
++ __bfq_bfqq_expire(bfqd, bfqq);
++ bfq_schedule_dispatch(bfqd);
++ }
++
++ bfq_log_bfqq(bfqd, bfqq, "exit_bfqq: %p, %d", bfqq,
++ atomic_read(&bfqq->ref));
++
++ bfq_put_cooperator(bfqq);
++
++ bfq_put_queue(bfqq);
++}
++
++static inline void bfq_init_icq(struct io_cq *icq)
++{
++ struct bfq_io_cq *bic = icq_to_bic(icq);
++
++ bic->ttime.last_end_request = jiffies;
++ /*
++ * A newly created bic indicates that the process has just
++ * started doing I/O, and is probably mapping into memory its
++ * executable and libraries: it definitely needs weight raising.
++ * There is however the possibility that the process performs,
++ * for a while, I/O close to some other process. EQM intercepts
++ * this behavior and may merge the queue corresponding to the
++ * process with some other queue, BEFORE the weight of the queue
++ * is raised. Merged queues are not weight-raised (they are assumed
++ * to belong to processes that benefit only from high throughput).
++ * If the merge is basically the consequence of an accident, then
++ * the queue will be split soon and will get back its old weight.
++ * It is then important to write down somewhere that this queue
++ * does need weight raising, even if it did not make it to get its
++ * weight raised before being merged. To this purpose, we overload
++ * the field raising_time_left and assign 1 to it, to mark the queue
++ * as needing weight raising.
++ */
++ bic->wr_time_left = 1;
++}
++
++static void bfq_exit_icq(struct io_cq *icq)
++{
++ struct bfq_io_cq *bic = icq_to_bic(icq);
++ struct bfq_data *bfqd = bic_to_bfqd(bic);
++
++ if (bic->bfqq[BLK_RW_ASYNC]) {
++ bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_ASYNC]);
++ bic->bfqq[BLK_RW_ASYNC] = NULL;
++ }
++
++ if (bic->bfqq[BLK_RW_SYNC]) {
++ /*
++ * If the bic is using a shared queue, put the reference
++ * taken on the io_context when the bic started using a
++ * shared bfq_queue.
++ */
++ if (bfq_bfqq_coop(bic->bfqq[BLK_RW_SYNC]))
++ put_io_context(icq->ioc);
++ bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_SYNC]);
++ bic->bfqq[BLK_RW_SYNC] = NULL;
++ }
++}
++
++/*
++ * Update the entity prio values; note that the new values will not
++ * be used until the next (re)activation.
++ */
++static void bfq_set_next_ioprio_data(struct bfq_queue *bfqq, struct bfq_io_cq *bic)
++{
++ struct task_struct *tsk = current;
++ int ioprio_class;
++
++ ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
++ switch (ioprio_class) {
++ default:
++ dev_err(bfqq->bfqd->queue->backing_dev_info.dev,
++ "bfq: bad prio class %d\n", ioprio_class);
++ case IOPRIO_CLASS_NONE:
++ /*
++ * No prio set, inherit CPU scheduling settings.
++ */
++ bfqq->entity.new_ioprio = task_nice_ioprio(tsk);
++ bfqq->entity.new_ioprio_class = task_nice_ioclass(tsk);
++ break;
++ case IOPRIO_CLASS_RT:
++ bfqq->entity.new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
++ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_RT;
++ break;
++ case IOPRIO_CLASS_BE:
++ bfqq->entity.new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
++ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_BE;
++ break;
++ case IOPRIO_CLASS_IDLE:
++ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_IDLE;
++ bfqq->entity.new_ioprio = 7;
++ bfq_clear_bfqq_idle_window(bfqq);
++ break;
++ }
++
++ if (bfqq->entity.new_ioprio < 0 ||
++ bfqq->entity.new_ioprio >= IOPRIO_BE_NR) {
++ printk(KERN_CRIT "bfq_set_next_ioprio_data: new_ioprio %d\n",
++ bfqq->entity.new_ioprio);
++ BUG();
++ }
++
++ bfqq->entity.new_weight = bfq_ioprio_to_weight(bfqq->entity.new_ioprio);
++ bfqq->entity.ioprio_changed = 1;
++}
++
++static void bfq_check_ioprio_change(struct bfq_io_cq *bic)
++{
++ struct bfq_data *bfqd;
++ struct bfq_queue *bfqq, *new_bfqq;
++ struct bfq_group *bfqg;
++ unsigned long uninitialized_var(flags);
++ int ioprio = bic->icq.ioc->ioprio;
++
++ bfqd = bfq_get_bfqd_locked(&(bic->icq.q->elevator->elevator_data),
++ &flags);
++ /*
++ * This condition may trigger on a newly created bic, be sure to
++ * drop the lock before returning.
++ */
++ if (unlikely(bfqd == NULL) || likely(bic->ioprio == ioprio))
++ goto out;
++
++ bic->ioprio = ioprio;
++
++ bfqq = bic->bfqq[BLK_RW_ASYNC];
++ if (bfqq != NULL) {
++ bfqg = container_of(bfqq->entity.sched_data, struct bfq_group,
++ sched_data);
++ new_bfqq = bfq_get_queue(bfqd, bfqg, BLK_RW_ASYNC, bic,
++ GFP_ATOMIC);
++ if (new_bfqq != NULL) {
++ bic->bfqq[BLK_RW_ASYNC] = new_bfqq;
++ bfq_log_bfqq(bfqd, bfqq,
++ "check_ioprio_change: bfqq %p %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ }
++ }
++
++ bfqq = bic->bfqq[BLK_RW_SYNC];
++ if (bfqq != NULL)
++ bfq_set_next_ioprio_data(bfqq, bic);
++
++out:
++ bfq_put_bfqd_unlock(bfqd, &flags);
++}
++
++static void bfq_init_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ struct bfq_io_cq *bic, pid_t pid, int is_sync)
++{
++ RB_CLEAR_NODE(&bfqq->entity.rb_node);
++ INIT_LIST_HEAD(&bfqq->fifo);
++ INIT_HLIST_NODE(&bfqq->burst_list_node);
++
++ atomic_set(&bfqq->ref, 0);
++ bfqq->bfqd = bfqd;
++
++ if (bic)
++ bfq_set_next_ioprio_data(bfqq, bic);
++
++ if (is_sync) {
++ if (!bfq_class_idle(bfqq))
++ bfq_mark_bfqq_idle_window(bfqq);
++ bfq_mark_bfqq_sync(bfqq);
++ }
++ bfq_mark_bfqq_IO_bound(bfqq);
++
++ /* Tentative initial value to trade off between thr and lat */
++ bfqq->max_budget = (2 * bfq_max_budget(bfqd)) / 3;
++ bfqq->pid = pid;
++
++ bfqq->wr_coeff = 1;
++ bfqq->last_wr_start_finish = 0;
++ /*
++ * Set to the value for which bfqq will not be deemed as
++ * soft rt when it becomes backlogged.
++ */
++ bfqq->soft_rt_next_start = bfq_infinity_from_now(jiffies);
++}
++
++static struct bfq_queue *bfq_find_alloc_queue(struct bfq_data *bfqd,
++ struct bfq_group *bfqg,
++ int is_sync,
++ struct bfq_io_cq *bic,
++ gfp_t gfp_mask)
++{
++ struct bfq_queue *bfqq, *new_bfqq = NULL;
++
++retry:
++ /* bic always exists here */
++ bfqq = bic_to_bfqq(bic, is_sync);
++
++ /*
++ * Always try a new alloc if we fall back to the OOM bfqq
++ * originally, since it should just be a temporary situation.
++ */
++ if (bfqq == NULL || bfqq == &bfqd->oom_bfqq) {
++ bfqq = NULL;
++ if (new_bfqq != NULL) {
++ bfqq = new_bfqq;
++ new_bfqq = NULL;
++ } else if (gfp_mask & __GFP_WAIT) {
++ spin_unlock_irq(bfqd->queue->queue_lock);
++ new_bfqq = kmem_cache_alloc_node(bfq_pool,
++ gfp_mask | __GFP_ZERO,
++ bfqd->queue->node);
++ spin_lock_irq(bfqd->queue->queue_lock);
++ if (new_bfqq != NULL)
++ goto retry;
++ } else {
++ bfqq = kmem_cache_alloc_node(bfq_pool,
++ gfp_mask | __GFP_ZERO,
++ bfqd->queue->node);
++ }
++
++ if (bfqq != NULL) {
++ bfq_init_bfqq(bfqd, bfqq, bic, current->pid,
++ is_sync);
++ bfq_init_entity(&bfqq->entity, bfqg);
++ bfq_log_bfqq(bfqd, bfqq, "allocated");
++ } else {
++ bfqq = &bfqd->oom_bfqq;
++ bfq_log_bfqq(bfqd, bfqq, "using oom bfqq");
++ }
++ }
++
++ if (new_bfqq != NULL)
++ kmem_cache_free(bfq_pool, new_bfqq);
++
++ return bfqq;
++}
++
++static struct bfq_queue **bfq_async_queue_prio(struct bfq_data *bfqd,
++ struct bfq_group *bfqg,
++ int ioprio_class, int ioprio)
++{
++ switch (ioprio_class) {
++ case IOPRIO_CLASS_RT:
++ return &bfqg->async_bfqq[0][ioprio];
++ case IOPRIO_CLASS_NONE:
++ ioprio = IOPRIO_NORM;
++ /* fall through */
++ case IOPRIO_CLASS_BE:
++ return &bfqg->async_bfqq[1][ioprio];
++ case IOPRIO_CLASS_IDLE:
++ return &bfqg->async_idle_bfqq;
++ default:
++ BUG();
++ }
++}
++
++static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd,
++ struct bfq_group *bfqg, int is_sync,
++ struct bfq_io_cq *bic, gfp_t gfp_mask)
++{
++ const int ioprio = IOPRIO_PRIO_DATA(bic->ioprio);
++ const int ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio);
++ struct bfq_queue **async_bfqq = NULL;
++ struct bfq_queue *bfqq = NULL;
++
++ if (!is_sync) {
++ async_bfqq = bfq_async_queue_prio(bfqd, bfqg, ioprio_class,
++ ioprio);
++ bfqq = *async_bfqq;
++ }
++
++ if (bfqq == NULL)
++ bfqq = bfq_find_alloc_queue(bfqd, bfqg, is_sync, bic, gfp_mask);
++
++ /*
++ * Pin the queue now that it's allocated, scheduler exit will
++ * prune it.
++ */
++ if (!is_sync && *async_bfqq == NULL) {
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqd, bfqq, "get_queue, bfqq not in async: %p, %d",
++ bfqq, atomic_read(&bfqq->ref));
++ *async_bfqq = bfqq;
++ }
++
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqd, bfqq, "get_queue, at end: %p, %d", bfqq,
++ atomic_read(&bfqq->ref));
++ return bfqq;
++}
++
++static void bfq_update_io_thinktime(struct bfq_data *bfqd,
++ struct bfq_io_cq *bic)
++{
++ unsigned long elapsed = jiffies - bic->ttime.last_end_request;
++ unsigned long ttime = min(elapsed, 2UL * bfqd->bfq_slice_idle);
++
++ bic->ttime.ttime_samples = (7*bic->ttime.ttime_samples + 256) / 8;
++ bic->ttime.ttime_total = (7*bic->ttime.ttime_total + 256*ttime) / 8;
++ bic->ttime.ttime_mean = (bic->ttime.ttime_total + 128) /
++ bic->ttime.ttime_samples;
++}
++
++static void bfq_update_io_seektime(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct request *rq)
++{
++ sector_t sdist;
++ u64 total;
++
++ if (bfqq->last_request_pos < blk_rq_pos(rq))
++ sdist = blk_rq_pos(rq) - bfqq->last_request_pos;
++ else
++ sdist = bfqq->last_request_pos - blk_rq_pos(rq);
++
++ /*
++ * Don't allow the seek distance to get too large from the
++ * odd fragment, pagein, etc.
++ */
++ if (bfqq->seek_samples == 0) /* first request, not really a seek */
++ sdist = 0;
++ else if (bfqq->seek_samples <= 60) /* second & third seek */
++ sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*1024);
++ else
++ sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*64);
++
++ bfqq->seek_samples = (7*bfqq->seek_samples + 256) / 8;
++ bfqq->seek_total = (7*bfqq->seek_total + (u64)256*sdist) / 8;
++ total = bfqq->seek_total + (bfqq->seek_samples/2);
++ do_div(total, bfqq->seek_samples);
++ bfqq->seek_mean = (sector_t)total;
++
++ bfq_log_bfqq(bfqd, bfqq, "dist=%llu mean=%llu", (u64)sdist,
++ (u64)bfqq->seek_mean);
++}
++
++/*
++ * Disable idle window if the process thinks too long or seeks so much that
++ * it doesn't matter.
++ */
++static void bfq_update_idle_window(struct bfq_data *bfqd,
++ struct bfq_queue *bfqq,
++ struct bfq_io_cq *bic)
++{
++ int enable_idle;
++
++ /* Don't idle for async or idle io prio class. */
++ if (!bfq_bfqq_sync(bfqq) || bfq_class_idle(bfqq))
++ return;
++
++ /* Idle window just restored, statistics are meaningless. */
++ if (bfq_bfqq_just_split(bfqq))
++ return;
++
++ enable_idle = bfq_bfqq_idle_window(bfqq);
++
++ if (atomic_read(&bic->icq.ioc->active_ref) == 0 ||
++ bfqd->bfq_slice_idle == 0 ||
++ (bfqd->hw_tag && BFQQ_SEEKY(bfqq) &&
++ bfqq->wr_coeff == 1))
++ enable_idle = 0;
++ else if (bfq_sample_valid(bic->ttime.ttime_samples)) {
++ if (bic->ttime.ttime_mean > bfqd->bfq_slice_idle &&
++ bfqq->wr_coeff == 1)
++ enable_idle = 0;
++ else
++ enable_idle = 1;
++ }
++ bfq_log_bfqq(bfqd, bfqq, "update_idle_window: enable_idle %d",
++ enable_idle);
++
++ if (enable_idle)
++ bfq_mark_bfqq_idle_window(bfqq);
++ else
++ bfq_clear_bfqq_idle_window(bfqq);
++}
++
++/*
++ * Called when a new fs request (rq) is added to bfqq. Check if there's
++ * something we should do about it.
++ */
++static void bfq_rq_enqueued(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ struct request *rq)
++{
++ struct bfq_io_cq *bic = RQ_BIC(rq);
++
++ if (rq->cmd_flags & REQ_META)
++ bfqq->meta_pending++;
++
++ bfq_update_io_thinktime(bfqd, bic);
++ bfq_update_io_seektime(bfqd, bfqq, rq);
++ if (!BFQQ_SEEKY(bfqq) && bfq_bfqq_constantly_seeky(bfqq)) {
++ bfq_clear_bfqq_constantly_seeky(bfqq);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ BUG_ON(!bfqd->const_seeky_busy_in_flight_queues);
++ bfqd->const_seeky_busy_in_flight_queues--;
++ }
++ }
++ if (bfqq->entity.service > bfq_max_budget(bfqd) / 8 ||
++ !BFQQ_SEEKY(bfqq))
++ bfq_update_idle_window(bfqd, bfqq, bic);
++ bfq_clear_bfqq_just_split(bfqq);
++
++ bfq_log_bfqq(bfqd, bfqq,
++ "rq_enqueued: idle_window=%d (seeky %d, mean %llu)",
++ bfq_bfqq_idle_window(bfqq), BFQQ_SEEKY(bfqq),
++ (long long unsigned)bfqq->seek_mean);
++
++ bfqq->last_request_pos = blk_rq_pos(rq) + blk_rq_sectors(rq);
++
++ if (bfqq == bfqd->in_service_queue && bfq_bfqq_wait_request(bfqq)) {
++ int small_req = bfqq->queued[rq_is_sync(rq)] == 1 &&
++ blk_rq_sectors(rq) < 32;
++ int budget_timeout = bfq_bfqq_budget_timeout(bfqq);
++
++ /*
++ * There is just this request queued: if the request
++ * is small and the queue is not to be expired, then
++ * just exit.
++ *
++ * In this way, if the disk is being idled to wait for
++ * a new request from the in-service queue, we avoid
++ * unplugging the device and committing the disk to serve
++ * just a small request. On the contrary, we wait for
++ * the block layer to decide when to unplug the device:
++ * hopefully, new requests will be merged to this one
++ * quickly, then the device will be unplugged and
++ * larger requests will be dispatched.
++ */
++ if (small_req && !budget_timeout)
++ return;
++
++ /*
++ * A large enough request arrived, or the queue is to
++ * be expired: in both cases disk idling is to be
++ * stopped, so clear wait_request flag and reset
++ * timer.
++ */
++ bfq_clear_bfqq_wait_request(bfqq);
++ del_timer(&bfqd->idle_slice_timer);
++
++ /*
++ * The queue is not empty, because a new request just
++ * arrived. Hence we can safely expire the queue, in
++ * case of budget timeout, without risking that the
++ * timestamps of the queue are not updated correctly.
++ * See [1] for more details.
++ */
++ if (budget_timeout)
++ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_TIMEOUT);
++
++ /*
++ * Let the request rip immediately, or let a new queue be
++ * selected if bfqq has just been expired.
++ */
++ __blk_run_queue(bfqd->queue);
++ }
++}
++
++static void bfq_insert_request(struct request_queue *q, struct request *rq)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_queue *bfqq = RQ_BFQQ(rq), *new_bfqq;
++
++ assert_spin_locked(bfqd->queue->queue_lock);
++
++ /*
++ * An unplug may trigger a requeue of a request from the device
++ * driver: make sure we are in process context while trying to
++ * merge two bfq_queues.
++ */
++ if (!in_interrupt()) {
++ new_bfqq = bfq_setup_cooperator(bfqd, bfqq, rq, true);
++ if (new_bfqq != NULL) {
++ if (bic_to_bfqq(RQ_BIC(rq), 1) != bfqq)
++ new_bfqq = bic_to_bfqq(RQ_BIC(rq), 1);
++ /*
++ * Release the request's reference to the old bfqq
++ * and make sure one is taken to the shared queue.
++ */
++ new_bfqq->allocated[rq_data_dir(rq)]++;
++ bfqq->allocated[rq_data_dir(rq)]--;
++ atomic_inc(&new_bfqq->ref);
++ bfq_put_queue(bfqq);
++ if (bic_to_bfqq(RQ_BIC(rq), 1) == bfqq)
++ bfq_merge_bfqqs(bfqd, RQ_BIC(rq),
++ bfqq, new_bfqq);
++ rq->elv.priv[1] = new_bfqq;
++ bfqq = new_bfqq;
++ } else
++ bfq_bfqq_increase_failed_cooperations(bfqq);
++ }
++
++ bfq_add_request(rq);
++
++ /*
++ * Here a newly-created bfq_queue has already started a weight-raising
++ * period: clear raising_time_left to prevent bfq_bfqq_save_state()
++ * from assigning it a full weight-raising period. See the detailed
++ * comments about this field in bfq_init_icq().
++ */
++ if (bfqq->bic != NULL)
++ bfqq->bic->wr_time_left = 0;
++ rq_set_fifo_time(rq, jiffies + bfqd->bfq_fifo_expire[rq_is_sync(rq)]);
++ list_add_tail(&rq->queuelist, &bfqq->fifo);
++
++ bfq_rq_enqueued(bfqd, bfqq, rq);
++}
++
++static void bfq_update_hw_tag(struct bfq_data *bfqd)
++{
++ bfqd->max_rq_in_driver = max(bfqd->max_rq_in_driver,
++ bfqd->rq_in_driver);
++
++ if (bfqd->hw_tag == 1)
++ return;
++
++ /*
++ * This sample is valid if the number of outstanding requests
++ * is large enough to allow a queueing behavior. Note that the
++ * sum is not exact, as it's not taking into account deactivated
++ * requests.
++ */
++ if (bfqd->rq_in_driver + bfqd->queued < BFQ_HW_QUEUE_THRESHOLD)
++ return;
++
++ if (bfqd->hw_tag_samples++ < BFQ_HW_QUEUE_SAMPLES)
++ return;
++
++ bfqd->hw_tag = bfqd->max_rq_in_driver > BFQ_HW_QUEUE_THRESHOLD;
++ bfqd->max_rq_in_driver = 0;
++ bfqd->hw_tag_samples = 0;
++}
++
++static void bfq_completed_request(struct request_queue *q, struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++ struct bfq_data *bfqd = bfqq->bfqd;
++ bool sync = bfq_bfqq_sync(bfqq);
++
++ bfq_log_bfqq(bfqd, bfqq, "completed one req with %u sects left (%d)",
++ blk_rq_sectors(rq), sync);
++
++ bfq_update_hw_tag(bfqd);
++
++ BUG_ON(!bfqd->rq_in_driver);
++ BUG_ON(!bfqq->dispatched);
++ bfqd->rq_in_driver--;
++ bfqq->dispatched--;
++
++ if (!bfqq->dispatched && !bfq_bfqq_busy(bfqq)) {
++ bfq_weights_tree_remove(bfqd, &bfqq->entity,
++ &bfqd->queue_weights_tree);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ BUG_ON(!bfqd->busy_in_flight_queues);
++ bfqd->busy_in_flight_queues--;
++ if (bfq_bfqq_constantly_seeky(bfqq)) {
++ BUG_ON(!bfqd->
++ const_seeky_busy_in_flight_queues);
++ bfqd->const_seeky_busy_in_flight_queues--;
++ }
++ }
++ }
++
++ if (sync) {
++ bfqd->sync_flight--;
++ RQ_BIC(rq)->ttime.last_end_request = jiffies;
++ }
++
++ /*
++ * If we are waiting to discover whether the request pattern of the
++ * task associated with the queue is actually isochronous, and
++ * both requisites for this condition to hold are satisfied, then
++ * compute soft_rt_next_start (see the comments to the function
++ * bfq_bfqq_softrt_next_start()).
++ */
++ if (bfq_bfqq_softrt_update(bfqq) && bfqq->dispatched == 0 &&
++ RB_EMPTY_ROOT(&bfqq->sort_list))
++ bfqq->soft_rt_next_start =
++ bfq_bfqq_softrt_next_start(bfqd, bfqq);
++
++ /*
++ * If this is the in-service queue, check if it needs to be expired,
++ * or if we want to idle in case it has no pending requests.
++ */
++ if (bfqd->in_service_queue == bfqq) {
++ if (bfq_bfqq_budget_new(bfqq))
++ bfq_set_budget_timeout(bfqd);
++
++ if (bfq_bfqq_must_idle(bfqq)) {
++ bfq_arm_slice_timer(bfqd);
++ goto out;
++ } else if (bfq_may_expire_for_budg_timeout(bfqq))
++ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_TIMEOUT);
++ else if (RB_EMPTY_ROOT(&bfqq->sort_list) &&
++ (bfqq->dispatched == 0 ||
++ !bfq_bfqq_must_not_expire(bfqq)))
++ bfq_bfqq_expire(bfqd, bfqq, 0,
++ BFQ_BFQQ_NO_MORE_REQUESTS);
++ }
++
++ if (!bfqd->rq_in_driver)
++ bfq_schedule_dispatch(bfqd);
++
++out:
++ return;
++}
++
++static inline int __bfq_may_queue(struct bfq_queue *bfqq)
++{
++ if (bfq_bfqq_wait_request(bfqq) && bfq_bfqq_must_alloc(bfqq)) {
++ bfq_clear_bfqq_must_alloc(bfqq);
++ return ELV_MQUEUE_MUST;
++ }
++
++ return ELV_MQUEUE_MAY;
++}
++
++static int bfq_may_queue(struct request_queue *q, int rw)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct task_struct *tsk = current;
++ struct bfq_io_cq *bic;
++ struct bfq_queue *bfqq;
++
++ /*
++ * Don't force setup of a queue from here, as a call to may_queue
++ * does not necessarily imply that a request actually will be
++ * queued. So just lookup a possibly existing queue, or return
++ * 'may queue' if that fails.
++ */
++ bic = bfq_bic_lookup(bfqd, tsk->io_context);
++ if (bic == NULL)
++ return ELV_MQUEUE_MAY;
++
++ bfqq = bic_to_bfqq(bic, rw_is_sync(rw));
++ if (bfqq != NULL)
++ return __bfq_may_queue(bfqq);
++
++ return ELV_MQUEUE_MAY;
++}
++
++/*
++ * Queue lock held here.
++ */
++static void bfq_put_request(struct request *rq)
++{
++ struct bfq_queue *bfqq = RQ_BFQQ(rq);
++
++ if (bfqq != NULL) {
++ const int rw = rq_data_dir(rq);
++
++ BUG_ON(!bfqq->allocated[rw]);
++ bfqq->allocated[rw]--;
++
++ rq->elv.priv[0] = NULL;
++ rq->elv.priv[1] = NULL;
++
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "put_request %p, %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ }
++}
++
++/*
++ * Returns NULL if a new bfqq should be allocated, or the old bfqq if this
++ * was the last process referring to said bfqq.
++ */
++static struct bfq_queue *
++bfq_split_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq)
++{
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "splitting queue");
++
++ put_io_context(bic->icq.ioc);
++
++ if (bfqq_process_refs(bfqq) == 1) {
++ bfqq->pid = current->pid;
++ bfq_clear_bfqq_coop(bfqq);
++ bfq_clear_bfqq_split_coop(bfqq);
++ return bfqq;
++ }
++
++ bic_set_bfqq(bic, NULL, 1);
++
++ bfq_put_cooperator(bfqq);
++
++ bfq_put_queue(bfqq);
++ return NULL;
++}
++
++/*
++ * Allocate bfq data structures associated with this request.
++ */
++static int bfq_set_request(struct request_queue *q, struct request *rq,
++ struct bio *bio, gfp_t gfp_mask)
++{
++ struct bfq_data *bfqd = q->elevator->elevator_data;
++ struct bfq_io_cq *bic = icq_to_bic(rq->elv.icq);
++ const int rw = rq_data_dir(rq);
++ const int is_sync = rq_is_sync(rq);
++ struct bfq_queue *bfqq;
++ struct bfq_group *bfqg;
++ unsigned long flags;
++ bool split = false;
++
++ might_sleep_if(gfp_mask & __GFP_WAIT);
++
++ bfq_check_ioprio_change(bic);
++
++ spin_lock_irqsave(q->queue_lock, flags);
++
++ if (bic == NULL)
++ goto queue_fail;
++
++ bfqg = bfq_bic_update_cgroup(bic);
++
++new_queue:
++ bfqq = bic_to_bfqq(bic, is_sync);
++ if (bfqq == NULL || bfqq == &bfqd->oom_bfqq) {
++ bfqq = bfq_get_queue(bfqd, bfqg, is_sync, bic, gfp_mask);
++ bic_set_bfqq(bic, bfqq, is_sync);
++ if (split && is_sync) {
++ if ((bic->was_in_burst_list && bfqd->large_burst) ||
++ bic->saved_in_large_burst)
++ bfq_mark_bfqq_in_large_burst(bfqq);
++ else {
++ bfq_clear_bfqq_in_large_burst(bfqq);
++ if (bic->was_in_burst_list)
++ hlist_add_head(&bfqq->burst_list_node,
++ &bfqd->burst_list);
++ }
++ }
++ } else {
++ /* If the queue was seeky for too long, break it apart. */
++ if (bfq_bfqq_coop(bfqq) && bfq_bfqq_split_coop(bfqq)) {
++ bfq_log_bfqq(bfqd, bfqq, "breaking apart bfqq");
++ bfqq = bfq_split_bfqq(bic, bfqq);
++ split = true;
++ if (!bfqq)
++ goto new_queue;
++ }
++ }
++
++ bfqq->allocated[rw]++;
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqd, bfqq, "set_request: bfqq %p, %d", bfqq,
++ atomic_read(&bfqq->ref));
++
++ rq->elv.priv[0] = bic;
++ rq->elv.priv[1] = bfqq;
++
++ /*
++ * If a bfq_queue has only one process reference, it is owned
++ * by only one bfq_io_cq: we can set the bic field of the
++ * bfq_queue to the address of that structure. Also, if the
++ * queue has just been split, mark a flag so that the
++ * information is available to the other scheduler hooks.
++ */
++ if (likely(bfqq != &bfqd->oom_bfqq) && bfqq_process_refs(bfqq) == 1) {
++ bfqq->bic = bic;
++ if (split) {
++ bfq_mark_bfqq_just_split(bfqq);
++ /*
++ * If the queue has just been split from a shared
++ * queue, restore the idle window and the possible
++ * weight raising period.
++ */
++ bfq_bfqq_resume_state(bfqq, bic);
++ }
++ }
++
++ spin_unlock_irqrestore(q->queue_lock, flags);
++
++ return 0;
++
++queue_fail:
++ bfq_schedule_dispatch(bfqd);
++ spin_unlock_irqrestore(q->queue_lock, flags);
++
++ return 1;
++}
++
++static void bfq_kick_queue(struct work_struct *work)
++{
++ struct bfq_data *bfqd =
++ container_of(work, struct bfq_data, unplug_work);
++ struct request_queue *q = bfqd->queue;
++
++ spin_lock_irq(q->queue_lock);
++ __blk_run_queue(q);
++ spin_unlock_irq(q->queue_lock);
++}
++
++/*
++ * Handler of the expiration of the timer running if the in-service queue
++ * is idling inside its time slice.
++ */
++static void bfq_idle_slice_timer(unsigned long data)
++{
++ struct bfq_data *bfqd = (struct bfq_data *)data;
++ struct bfq_queue *bfqq;
++ unsigned long flags;
++ enum bfqq_expiration reason;
++
++ spin_lock_irqsave(bfqd->queue->queue_lock, flags);
++
++ bfqq = bfqd->in_service_queue;
++ /*
++ * Theoretical race here: the in-service queue can be NULL or
++ * different from the queue that was idling if the timer handler
++ * spins on the queue_lock and a new request arrives for the
++ * current queue and there is a full dispatch cycle that changes
++ * the in-service queue. This can hardly happen, but in the worst
++ * case we just expire a queue too early.
++ */
++ if (bfqq != NULL) {
++ bfq_log_bfqq(bfqd, bfqq, "slice_timer expired");
++ if (bfq_bfqq_budget_timeout(bfqq))
++ /*
++ * Also here the queue can be safely expired
++ * for budget timeout without wasting
++ * guarantees
++ */
++ reason = BFQ_BFQQ_BUDGET_TIMEOUT;
++ else if (bfqq->queued[0] == 0 && bfqq->queued[1] == 0)
++ /*
++ * The queue may not be empty upon timer expiration,
++ * because we may not disable the timer when the
++ * first request of the in-service queue arrives
++ * during disk idling.
++ */
++ reason = BFQ_BFQQ_TOO_IDLE;
++ else
++ goto schedule_dispatch;
++
++ bfq_bfqq_expire(bfqd, bfqq, 1, reason);
++ }
++
++schedule_dispatch:
++ bfq_schedule_dispatch(bfqd);
++
++ spin_unlock_irqrestore(bfqd->queue->queue_lock, flags);
++}
++
++static void bfq_shutdown_timer_wq(struct bfq_data *bfqd)
++{
++ del_timer_sync(&bfqd->idle_slice_timer);
++ cancel_work_sync(&bfqd->unplug_work);
++}
++
++static inline void __bfq_put_async_bfqq(struct bfq_data *bfqd,
++ struct bfq_queue **bfqq_ptr)
++{
++ struct bfq_group *root_group = bfqd->root_group;
++ struct bfq_queue *bfqq = *bfqq_ptr;
++
++ bfq_log(bfqd, "put_async_bfqq: %p", bfqq);
++ if (bfqq != NULL) {
++ bfq_bfqq_move(bfqd, bfqq, &bfqq->entity, root_group);
++ bfq_log_bfqq(bfqd, bfqq, "put_async_bfqq: putting %p, %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ *bfqq_ptr = NULL;
++ }
++}
++
++/*
++ * Release all the bfqg references to its async queues. If we are
++ * deallocating the group these queues may still contain requests, so
++ * we reparent them to the root cgroup (i.e., the only one that will
++ * exist for sure until all the requests on a device are gone).
++ */
++static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg)
++{
++ int i, j;
++
++ for (i = 0; i < 2; i++)
++ for (j = 0; j < IOPRIO_BE_NR; j++)
++ __bfq_put_async_bfqq(bfqd, &bfqg->async_bfqq[i][j]);
++
++ __bfq_put_async_bfqq(bfqd, &bfqg->async_idle_bfqq);
++}
++
++static void bfq_exit_queue(struct elevator_queue *e)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ struct request_queue *q = bfqd->queue;
++ struct bfq_queue *bfqq, *n;
++
++ bfq_shutdown_timer_wq(bfqd);
++
++ spin_lock_irq(q->queue_lock);
++
++ BUG_ON(bfqd->in_service_queue != NULL);
++ list_for_each_entry_safe(bfqq, n, &bfqd->idle_list, bfqq_list)
++ bfq_deactivate_bfqq(bfqd, bfqq, 0);
++
++ bfq_disconnect_groups(bfqd);
++ spin_unlock_irq(q->queue_lock);
++
++ bfq_shutdown_timer_wq(bfqd);
++
++ synchronize_rcu();
++
++ BUG_ON(timer_pending(&bfqd->idle_slice_timer));
++
++ bfq_free_root_group(bfqd);
++ kfree(bfqd);
++}
++
++static int bfq_init_queue(struct request_queue *q, struct elevator_type *e)
++{
++ struct bfq_group *bfqg;
++ struct bfq_data *bfqd;
++ struct elevator_queue *eq;
++
++ eq = elevator_alloc(q, e);
++ if (eq == NULL)
++ return -ENOMEM;
++
++ bfqd = kzalloc_node(sizeof(*bfqd), GFP_KERNEL, q->node);
++ if (bfqd == NULL) {
++ kobject_put(&eq->kobj);
++ return -ENOMEM;
++ }
++ eq->elevator_data = bfqd;
++
++ /*
++ * Our fallback bfqq if bfq_find_alloc_queue() runs into OOM issues.
++ * Grab a permanent reference to it, so that the normal code flow
++ * will not attempt to free it.
++ */
++ bfq_init_bfqq(bfqd, &bfqd->oom_bfqq, NULL, 1, 0);
++ atomic_inc(&bfqd->oom_bfqq.ref);
++ bfqd->oom_bfqq.entity.new_ioprio = BFQ_DEFAULT_QUEUE_IOPRIO;
++ bfqd->oom_bfqq.entity.new_ioprio_class = IOPRIO_CLASS_BE;
++ bfqd->oom_bfqq.entity.new_weight =
++ bfq_ioprio_to_weight(bfqd->oom_bfqq.entity.new_ioprio);
++ /*
++ * Trigger weight initialization, according to ioprio, at the
++ * oom_bfqq's first activation. The oom_bfqq's ioprio and ioprio
++ * class won't be changed any more.
++ */
++ bfqd->oom_bfqq.entity.ioprio_changed = 1;
++
++ bfqd->queue = q;
++
++ spin_lock_irq(q->queue_lock);
++ q->elevator = eq;
++ spin_unlock_irq(q->queue_lock);
++
++ bfqg = bfq_alloc_root_group(bfqd, q->node);
++ if (bfqg == NULL) {
++ kfree(bfqd);
++ kobject_put(&eq->kobj);
++ return -ENOMEM;
++ }
++
++ bfqd->root_group = bfqg;
++ bfq_init_entity(&bfqd->oom_bfqq.entity, bfqd->root_group);
++#ifdef CONFIG_CGROUP_BFQIO
++ bfqd->active_numerous_groups = 0;
++#endif
++
++ init_timer(&bfqd->idle_slice_timer);
++ bfqd->idle_slice_timer.function = bfq_idle_slice_timer;
++ bfqd->idle_slice_timer.data = (unsigned long)bfqd;
++
++ bfqd->rq_pos_tree = RB_ROOT;
++ bfqd->queue_weights_tree = RB_ROOT;
++ bfqd->group_weights_tree = RB_ROOT;
++
++ INIT_WORK(&bfqd->unplug_work, bfq_kick_queue);
++
++ INIT_LIST_HEAD(&bfqd->active_list);
++ INIT_LIST_HEAD(&bfqd->idle_list);
++ INIT_HLIST_HEAD(&bfqd->burst_list);
++
++ bfqd->hw_tag = -1;
++
++ bfqd->bfq_max_budget = bfq_default_max_budget;
++
++ bfqd->bfq_fifo_expire[0] = bfq_fifo_expire[0];
++ bfqd->bfq_fifo_expire[1] = bfq_fifo_expire[1];
++ bfqd->bfq_back_max = bfq_back_max;
++ bfqd->bfq_back_penalty = bfq_back_penalty;
++ bfqd->bfq_slice_idle = bfq_slice_idle;
++ bfqd->bfq_class_idle_last_service = 0;
++ bfqd->bfq_max_budget_async_rq = bfq_max_budget_async_rq;
++ bfqd->bfq_timeout[BLK_RW_ASYNC] = bfq_timeout_async;
++ bfqd->bfq_timeout[BLK_RW_SYNC] = bfq_timeout_sync;
++
++ bfqd->bfq_coop_thresh = 2;
++ bfqd->bfq_failed_cooperations = 7000;
++ bfqd->bfq_requests_within_timer = 120;
++
++ bfqd->bfq_large_burst_thresh = 11;
++ bfqd->bfq_burst_interval = msecs_to_jiffies(500);
++
++ bfqd->low_latency = true;
++
++ bfqd->bfq_wr_coeff = 20;
++ bfqd->bfq_wr_rt_max_time = msecs_to_jiffies(300);
++ bfqd->bfq_wr_max_time = 0;
++ bfqd->bfq_wr_min_idle_time = msecs_to_jiffies(2000);
++ bfqd->bfq_wr_min_inter_arr_async = msecs_to_jiffies(500);
++ bfqd->bfq_wr_max_softrt_rate = 7000; /*
++ * Approximate rate required
++ * to playback or record a
++ * high-definition compressed
++ * video.
++ */
++ bfqd->wr_busy_queues = 0;
++ bfqd->busy_in_flight_queues = 0;
++ bfqd->const_seeky_busy_in_flight_queues = 0;
++
++ /*
++ * Begin by assuming, optimistically, that the device peak rate is
++ * equal to the highest reference rate.
++ */
++ bfqd->RT_prod = R_fast[blk_queue_nonrot(bfqd->queue)] *
++ T_fast[blk_queue_nonrot(bfqd->queue)];
++ bfqd->peak_rate = R_fast[blk_queue_nonrot(bfqd->queue)];
++ bfqd->device_speed = BFQ_BFQD_FAST;
++
++ return 0;
++}
++
++static void bfq_slab_kill(void)
++{
++ if (bfq_pool != NULL)
++ kmem_cache_destroy(bfq_pool);
++}
++
++static int __init bfq_slab_setup(void)
++{
++ bfq_pool = KMEM_CACHE(bfq_queue, 0);
++ if (bfq_pool == NULL)
++ return -ENOMEM;
++ return 0;
++}
++
++static ssize_t bfq_var_show(unsigned int var, char *page)
++{
++ return sprintf(page, "%d\n", var);
++}
++
++static ssize_t bfq_var_store(unsigned long *var, const char *page,
++ size_t count)
++{
++ unsigned long new_val;
++ int ret = kstrtoul(page, 10, &new_val);
++
++ if (ret == 0)
++ *var = new_val;
++
++ return count;
++}
++
++static ssize_t bfq_wr_max_time_show(struct elevator_queue *e, char *page)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ return sprintf(page, "%d\n", bfqd->bfq_wr_max_time > 0 ?
++ jiffies_to_msecs(bfqd->bfq_wr_max_time) :
++ jiffies_to_msecs(bfq_wr_duration(bfqd)));
++}
++
++static ssize_t bfq_weights_show(struct elevator_queue *e, char *page)
++{
++ struct bfq_queue *bfqq;
++ struct bfq_data *bfqd = e->elevator_data;
++ ssize_t num_char = 0;
++
++ num_char += sprintf(page + num_char, "Tot reqs queued %d\n\n",
++ bfqd->queued);
++
++ spin_lock_irq(bfqd->queue->queue_lock);
++
++ num_char += sprintf(page + num_char, "Active:\n");
++ list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) {
++ num_char += sprintf(page + num_char,
++ "pid%d: weight %hu, nr_queued %d %d, dur %d/%u\n",
++ bfqq->pid,
++ bfqq->entity.weight,
++ bfqq->queued[0],
++ bfqq->queued[1],
++ jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish),
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ }
++
++ num_char += sprintf(page + num_char, "Idle:\n");
++ list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) {
++ num_char += sprintf(page + num_char,
++ "pid%d: weight %hu, dur %d/%u\n",
++ bfqq->pid,
++ bfqq->entity.weight,
++ jiffies_to_msecs(jiffies -
++ bfqq->last_wr_start_finish),
++ jiffies_to_msecs(bfqq->wr_cur_max_time));
++ }
++
++ spin_unlock_irq(bfqd->queue->queue_lock);
++
++ return num_char;
++}
++
++#define SHOW_FUNCTION(__FUNC, __VAR, __CONV) \
++static ssize_t __FUNC(struct elevator_queue *e, char *page) \
++{ \
++ struct bfq_data *bfqd = e->elevator_data; \
++ unsigned int __data = __VAR; \
++ if (__CONV) \
++ __data = jiffies_to_msecs(__data); \
++ return bfq_var_show(__data, (page)); \
++}
++SHOW_FUNCTION(bfq_fifo_expire_sync_show, bfqd->bfq_fifo_expire[1], 1);
++SHOW_FUNCTION(bfq_fifo_expire_async_show, bfqd->bfq_fifo_expire[0], 1);
++SHOW_FUNCTION(bfq_back_seek_max_show, bfqd->bfq_back_max, 0);
++SHOW_FUNCTION(bfq_back_seek_penalty_show, bfqd->bfq_back_penalty, 0);
++SHOW_FUNCTION(bfq_slice_idle_show, bfqd->bfq_slice_idle, 1);
++SHOW_FUNCTION(bfq_max_budget_show, bfqd->bfq_user_max_budget, 0);
++SHOW_FUNCTION(bfq_max_budget_async_rq_show,
++ bfqd->bfq_max_budget_async_rq, 0);
++SHOW_FUNCTION(bfq_timeout_sync_show, bfqd->bfq_timeout[BLK_RW_SYNC], 1);
++SHOW_FUNCTION(bfq_timeout_async_show, bfqd->bfq_timeout[BLK_RW_ASYNC], 1);
++SHOW_FUNCTION(bfq_low_latency_show, bfqd->low_latency, 0);
++SHOW_FUNCTION(bfq_wr_coeff_show, bfqd->bfq_wr_coeff, 0);
++SHOW_FUNCTION(bfq_wr_rt_max_time_show, bfqd->bfq_wr_rt_max_time, 1);
++SHOW_FUNCTION(bfq_wr_min_idle_time_show, bfqd->bfq_wr_min_idle_time, 1);
++SHOW_FUNCTION(bfq_wr_min_inter_arr_async_show, bfqd->bfq_wr_min_inter_arr_async,
++ 1);
++SHOW_FUNCTION(bfq_wr_max_softrt_rate_show, bfqd->bfq_wr_max_softrt_rate, 0);
++#undef SHOW_FUNCTION
++
++#define STORE_FUNCTION(__FUNC, __PTR, MIN, MAX, __CONV) \
++static ssize_t \
++__FUNC(struct elevator_queue *e, const char *page, size_t count) \
++{ \
++ struct bfq_data *bfqd = e->elevator_data; \
++ unsigned long uninitialized_var(__data); \
++ int ret = bfq_var_store(&__data, (page), count); \
++ if (__data < (MIN)) \
++ __data = (MIN); \
++ else if (__data > (MAX)) \
++ __data = (MAX); \
++ if (__CONV) \
++ *(__PTR) = msecs_to_jiffies(__data); \
++ else \
++ *(__PTR) = __data; \
++ return ret; \
++}
++STORE_FUNCTION(bfq_fifo_expire_sync_store, &bfqd->bfq_fifo_expire[1], 1,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_fifo_expire_async_store, &bfqd->bfq_fifo_expire[0], 1,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_back_seek_max_store, &bfqd->bfq_back_max, 0, INT_MAX, 0);
++STORE_FUNCTION(bfq_back_seek_penalty_store, &bfqd->bfq_back_penalty, 1,
++ INT_MAX, 0);
++STORE_FUNCTION(bfq_slice_idle_store, &bfqd->bfq_slice_idle, 0, INT_MAX, 1);
++STORE_FUNCTION(bfq_max_budget_async_rq_store, &bfqd->bfq_max_budget_async_rq,
++ 1, INT_MAX, 0);
++STORE_FUNCTION(bfq_timeout_async_store, &bfqd->bfq_timeout[BLK_RW_ASYNC], 0,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_coeff_store, &bfqd->bfq_wr_coeff, 1, INT_MAX, 0);
++STORE_FUNCTION(bfq_wr_max_time_store, &bfqd->bfq_wr_max_time, 0, INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_rt_max_time_store, &bfqd->bfq_wr_rt_max_time, 0, INT_MAX,
++ 1);
++STORE_FUNCTION(bfq_wr_min_idle_time_store, &bfqd->bfq_wr_min_idle_time, 0,
++ INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_min_inter_arr_async_store,
++ &bfqd->bfq_wr_min_inter_arr_async, 0, INT_MAX, 1);
++STORE_FUNCTION(bfq_wr_max_softrt_rate_store, &bfqd->bfq_wr_max_softrt_rate, 0,
++ INT_MAX, 0);
++#undef STORE_FUNCTION
++
++/* do nothing for the moment */
++static ssize_t bfq_weights_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ return count;
++}
++
++static inline unsigned long bfq_estimated_max_budget(struct bfq_data *bfqd)
++{
++ u64 timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]);
++
++ if (bfqd->peak_rate_samples >= BFQ_PEAK_RATE_SAMPLES)
++ return bfq_calc_max_budget(bfqd->peak_rate, timeout);
++ else
++ return bfq_default_max_budget;
++}
++
++static ssize_t bfq_max_budget_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ unsigned long uninitialized_var(__data);
++ int ret = bfq_var_store(&__data, (page), count);
++
++ if (__data == 0)
++ bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd);
++ else {
++ if (__data > INT_MAX)
++ __data = INT_MAX;
++ bfqd->bfq_max_budget = __data;
++ }
++
++ bfqd->bfq_user_max_budget = __data;
++
++ return ret;
++}
++
++static ssize_t bfq_timeout_sync_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ unsigned long uninitialized_var(__data);
++ int ret = bfq_var_store(&__data, (page), count);
++
++ if (__data < 1)
++ __data = 1;
++ else if (__data > INT_MAX)
++ __data = INT_MAX;
++
++ bfqd->bfq_timeout[BLK_RW_SYNC] = msecs_to_jiffies(__data);
++ if (bfqd->bfq_user_max_budget == 0)
++ bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd);
++
++ return ret;
++}
++
++static ssize_t bfq_low_latency_store(struct elevator_queue *e,
++ const char *page, size_t count)
++{
++ struct bfq_data *bfqd = e->elevator_data;
++ unsigned long uninitialized_var(__data);
++ int ret = bfq_var_store(&__data, (page), count);
++
++ if (__data > 1)
++ __data = 1;
++ if (__data == 0 && bfqd->low_latency != 0)
++ bfq_end_wr(bfqd);
++ bfqd->low_latency = __data;
++
++ return ret;
++}
++
++#define BFQ_ATTR(name) \
++ __ATTR(name, S_IRUGO|S_IWUSR, bfq_##name##_show, bfq_##name##_store)
++
++static struct elv_fs_entry bfq_attrs[] = {
++ BFQ_ATTR(fifo_expire_sync),
++ BFQ_ATTR(fifo_expire_async),
++ BFQ_ATTR(back_seek_max),
++ BFQ_ATTR(back_seek_penalty),
++ BFQ_ATTR(slice_idle),
++ BFQ_ATTR(max_budget),
++ BFQ_ATTR(max_budget_async_rq),
++ BFQ_ATTR(timeout_sync),
++ BFQ_ATTR(timeout_async),
++ BFQ_ATTR(low_latency),
++ BFQ_ATTR(wr_coeff),
++ BFQ_ATTR(wr_max_time),
++ BFQ_ATTR(wr_rt_max_time),
++ BFQ_ATTR(wr_min_idle_time),
++ BFQ_ATTR(wr_min_inter_arr_async),
++ BFQ_ATTR(wr_max_softrt_rate),
++ BFQ_ATTR(weights),
++ __ATTR_NULL
++};
++
++static struct elevator_type iosched_bfq = {
++ .ops = {
++ .elevator_merge_fn = bfq_merge,
++ .elevator_merged_fn = bfq_merged_request,
++ .elevator_merge_req_fn = bfq_merged_requests,
++ .elevator_allow_merge_fn = bfq_allow_merge,
++ .elevator_dispatch_fn = bfq_dispatch_requests,
++ .elevator_add_req_fn = bfq_insert_request,
++ .elevator_activate_req_fn = bfq_activate_request,
++ .elevator_deactivate_req_fn = bfq_deactivate_request,
++ .elevator_completed_req_fn = bfq_completed_request,
++ .elevator_former_req_fn = elv_rb_former_request,
++ .elevator_latter_req_fn = elv_rb_latter_request,
++ .elevator_init_icq_fn = bfq_init_icq,
++ .elevator_exit_icq_fn = bfq_exit_icq,
++ .elevator_set_req_fn = bfq_set_request,
++ .elevator_put_req_fn = bfq_put_request,
++ .elevator_may_queue_fn = bfq_may_queue,
++ .elevator_init_fn = bfq_init_queue,
++ .elevator_exit_fn = bfq_exit_queue,
++ },
++ .icq_size = sizeof(struct bfq_io_cq),
++ .icq_align = __alignof__(struct bfq_io_cq),
++ .elevator_attrs = bfq_attrs,
++ .elevator_name = "bfq",
++ .elevator_owner = THIS_MODULE,
++};
++
++static int __init bfq_init(void)
++{
++ /*
++ * Can be 0 on HZ < 1000 setups.
++ */
++ if (bfq_slice_idle == 0)
++ bfq_slice_idle = 1;
++
++ if (bfq_timeout_async == 0)
++ bfq_timeout_async = 1;
++
++ if (bfq_slab_setup())
++ return -ENOMEM;
++
++ /*
++ * Times to load large popular applications for the typical systems
++ * installed on the reference devices (see the comments before the
++ * definitions of the two arrays).
++ */
++ T_slow[0] = msecs_to_jiffies(2600);
++ T_slow[1] = msecs_to_jiffies(1000);
++ T_fast[0] = msecs_to_jiffies(5500);
++ T_fast[1] = msecs_to_jiffies(2000);
++
++ /*
++ * Thresholds that determine the switch between speed classes (see
++ * the comments before the definition of the array).
++ */
++ device_speed_thresh[0] = (R_fast[0] + R_slow[0]) / 2;
++ device_speed_thresh[1] = (R_fast[1] + R_slow[1]) / 2;
++
++ elv_register(&iosched_bfq);
++ pr_info("BFQ I/O-scheduler: v7r8");
++
++ return 0;
++}
++
++static void __exit bfq_exit(void)
++{
++ elv_unregister(&iosched_bfq);
++ bfq_slab_kill();
++}
++
++module_init(bfq_init);
++module_exit(bfq_exit);
++
++MODULE_AUTHOR("Fabio Checconi, Paolo Valente");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/block/bfq-sched.c linux-3.14.72/block/bfq-sched.c
+--- linux-3.14.72.orig/block/bfq-sched.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/block/bfq-sched.c 2016-06-19 22:11:55.065155743 +0200
+@@ -0,0 +1,1180 @@
++/*
++ * BFQ: Hierarchical B-WF2Q+ scheduler.
++ *
++ * Based on ideas and code from CFQ:
++ * Copyright (C) 2003 Jens Axboe <axboe@kernel.dk>
++ *
++ * Copyright (C) 2008 Fabio Checconi <fabio@gandalf.sssup.it>
++ * Paolo Valente <paolo.valente@unimore.it>
++ *
++ * Copyright (C) 2010 Paolo Valente <paolo.valente@unimore.it>
++ */
++
++#ifdef CONFIG_CGROUP_BFQIO
++#define for_each_entity(entity) \
++ for (; entity != NULL; entity = entity->parent)
++
++#define for_each_entity_safe(entity, parent) \
++ for (; entity && ({ parent = entity->parent; 1; }); entity = parent)
++
++static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd,
++ int extract,
++ struct bfq_data *bfqd);
++
++static inline void bfq_update_budget(struct bfq_entity *next_in_service)
++{
++ struct bfq_entity *bfqg_entity;
++ struct bfq_group *bfqg;
++ struct bfq_sched_data *group_sd;
++
++ BUG_ON(next_in_service == NULL);
++
++ group_sd = next_in_service->sched_data;
++
++ bfqg = container_of(group_sd, struct bfq_group, sched_data);
++ /*
++ * bfq_group's my_entity field is not NULL only if the group
++ * is not the root group. We must not touch the root entity
++ * as it must never become an in-service entity.
++ */
++ bfqg_entity = bfqg->my_entity;
++ if (bfqg_entity != NULL)
++ bfqg_entity->budget = next_in_service->budget;
++}
++
++static int bfq_update_next_in_service(struct bfq_sched_data *sd)
++{
++ struct bfq_entity *next_in_service;
++
++ if (sd->in_service_entity != NULL)
++ /* will update/requeue at the end of service */
++ return 0;
++
++ /*
++ * NOTE: this can be improved in many ways, such as returning
++ * 1 (and thus propagating upwards the update) only when the
++ * budget changes, or caching the bfqq that will be scheduled
++ * next from this subtree. By now we worry more about
++ * correctness than about performance...
++ */
++ next_in_service = bfq_lookup_next_entity(sd, 0, NULL);
++ sd->next_in_service = next_in_service;
++
++ if (next_in_service != NULL)
++ bfq_update_budget(next_in_service);
++
++ return 1;
++}
++
++static inline void bfq_check_next_in_service(struct bfq_sched_data *sd,
++ struct bfq_entity *entity)
++{
++ BUG_ON(sd->next_in_service != entity);
++}
++#else
++#define for_each_entity(entity) \
++ for (; entity != NULL; entity = NULL)
++
++#define for_each_entity_safe(entity, parent) \
++ for (parent = NULL; entity != NULL; entity = parent)
++
++static inline int bfq_update_next_in_service(struct bfq_sched_data *sd)
++{
++ return 0;
++}
++
++static inline void bfq_check_next_in_service(struct bfq_sched_data *sd,
++ struct bfq_entity *entity)
++{
++}
++
++static inline void bfq_update_budget(struct bfq_entity *next_in_service)
++{
++}
++#endif
++
++/*
++ * Shift for timestamp calculations. This actually limits the maximum
++ * service allowed in one timestamp delta (small shift values increase it),
++ * the maximum total weight that can be used for the queues in the system
++ * (big shift values increase it), and the period of virtual time
++ * wraparounds.
++ */
++#define WFQ_SERVICE_SHIFT 22
++
++/**
++ * bfq_gt - compare two timestamps.
++ * @a: first ts.
++ * @b: second ts.
++ *
++ * Return @a > @b, dealing with wrapping correctly.
++ */
++static inline int bfq_gt(u64 a, u64 b)
++{
++ return (s64)(a - b) > 0;
++}
++
++static inline struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = NULL;
++
++ BUG_ON(entity == NULL);
++
++ if (entity->my_sched_data == NULL)
++ bfqq = container_of(entity, struct bfq_queue, entity);
++
++ return bfqq;
++}
++
++
++/**
++ * bfq_delta - map service into the virtual time domain.
++ * @service: amount of service.
++ * @weight: scale factor (weight of an entity or weight sum).
++ */
++static inline u64 bfq_delta(unsigned long service,
++ unsigned long weight)
++{
++ u64 d = (u64)service << WFQ_SERVICE_SHIFT;
++
++ do_div(d, weight);
++ return d;
++}
++
++/**
++ * bfq_calc_finish - assign the finish time to an entity.
++ * @entity: the entity to act upon.
++ * @service: the service to be charged to the entity.
++ */
++static inline void bfq_calc_finish(struct bfq_entity *entity,
++ unsigned long service)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++
++ BUG_ON(entity->weight == 0);
++
++ entity->finish = entity->start +
++ bfq_delta(service, entity->weight);
++
++ if (bfqq != NULL) {
++ bfq_log_bfqq(bfqq->bfqd, bfqq,
++ "calc_finish: serv %lu, w %d",
++ service, entity->weight);
++ bfq_log_bfqq(bfqq->bfqd, bfqq,
++ "calc_finish: start %llu, finish %llu, delta %llu",
++ entity->start, entity->finish,
++ bfq_delta(service, entity->weight));
++ }
++}
++
++/**
++ * bfq_entity_of - get an entity from a node.
++ * @node: the node field of the entity.
++ *
++ * Convert a node pointer to the relative entity. This is used only
++ * to simplify the logic of some functions and not as the generic
++ * conversion mechanism because, e.g., in the tree walking functions,
++ * the check for a %NULL value would be redundant.
++ */
++static inline struct bfq_entity *bfq_entity_of(struct rb_node *node)
++{
++ struct bfq_entity *entity = NULL;
++
++ if (node != NULL)
++ entity = rb_entry(node, struct bfq_entity, rb_node);
++
++ return entity;
++}
++
++/**
++ * bfq_extract - remove an entity from a tree.
++ * @root: the tree root.
++ * @entity: the entity to remove.
++ */
++static inline void bfq_extract(struct rb_root *root,
++ struct bfq_entity *entity)
++{
++ BUG_ON(entity->tree != root);
++
++ entity->tree = NULL;
++ rb_erase(&entity->rb_node, root);
++}
++
++/**
++ * bfq_idle_extract - extract an entity from the idle tree.
++ * @st: the service tree of the owning @entity.
++ * @entity: the entity being removed.
++ */
++static void bfq_idle_extract(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct rb_node *next;
++
++ BUG_ON(entity->tree != &st->idle);
++
++ if (entity == st->first_idle) {
++ next = rb_next(&entity->rb_node);
++ st->first_idle = bfq_entity_of(next);
++ }
++
++ if (entity == st->last_idle) {
++ next = rb_prev(&entity->rb_node);
++ st->last_idle = bfq_entity_of(next);
++ }
++
++ bfq_extract(&st->idle, entity);
++
++ if (bfqq != NULL)
++ list_del(&bfqq->bfqq_list);
++}
++
++/**
++ * bfq_insert - generic tree insertion.
++ * @root: tree root.
++ * @entity: entity to insert.
++ *
++ * This is used for the idle and the active tree, since they are both
++ * ordered by finish time.
++ */
++static void bfq_insert(struct rb_root *root, struct bfq_entity *entity)
++{
++ struct bfq_entity *entry;
++ struct rb_node **node = &root->rb_node;
++ struct rb_node *parent = NULL;
++
++ BUG_ON(entity->tree != NULL);
++
++ while (*node != NULL) {
++ parent = *node;
++ entry = rb_entry(parent, struct bfq_entity, rb_node);
++
++ if (bfq_gt(entry->finish, entity->finish))
++ node = &parent->rb_left;
++ else
++ node = &parent->rb_right;
++ }
++
++ rb_link_node(&entity->rb_node, parent, node);
++ rb_insert_color(&entity->rb_node, root);
++
++ entity->tree = root;
++}
++
++/**
++ * bfq_update_min - update the min_start field of a entity.
++ * @entity: the entity to update.
++ * @node: one of its children.
++ *
++ * This function is called when @entity may store an invalid value for
++ * min_start due to updates to the active tree. The function assumes
++ * that the subtree rooted at @node (which may be its left or its right
++ * child) has a valid min_start value.
++ */
++static inline void bfq_update_min(struct bfq_entity *entity,
++ struct rb_node *node)
++{
++ struct bfq_entity *child;
++
++ if (node != NULL) {
++ child = rb_entry(node, struct bfq_entity, rb_node);
++ if (bfq_gt(entity->min_start, child->min_start))
++ entity->min_start = child->min_start;
++ }
++}
++
++/**
++ * bfq_update_active_node - recalculate min_start.
++ * @node: the node to update.
++ *
++ * @node may have changed position or one of its children may have moved,
++ * this function updates its min_start value. The left and right subtrees
++ * are assumed to hold a correct min_start value.
++ */
++static inline void bfq_update_active_node(struct rb_node *node)
++{
++ struct bfq_entity *entity = rb_entry(node, struct bfq_entity, rb_node);
++
++ entity->min_start = entity->start;
++ bfq_update_min(entity, node->rb_right);
++ bfq_update_min(entity, node->rb_left);
++}
++
++/**
++ * bfq_update_active_tree - update min_start for the whole active tree.
++ * @node: the starting node.
++ *
++ * @node must be the deepest modified node after an update. This function
++ * updates its min_start using the values held by its children, assuming
++ * that they did not change, and then updates all the nodes that may have
++ * changed in the path to the root. The only nodes that may have changed
++ * are the ones in the path or their siblings.
++ */
++static void bfq_update_active_tree(struct rb_node *node)
++{
++ struct rb_node *parent;
++
++up:
++ bfq_update_active_node(node);
++
++ parent = rb_parent(node);
++ if (parent == NULL)
++ return;
++
++ if (node == parent->rb_left && parent->rb_right != NULL)
++ bfq_update_active_node(parent->rb_right);
++ else if (parent->rb_left != NULL)
++ bfq_update_active_node(parent->rb_left);
++
++ node = parent;
++ goto up;
++}
++
++static void bfq_weights_tree_add(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root);
++
++static void bfq_weights_tree_remove(struct bfq_data *bfqd,
++ struct bfq_entity *entity,
++ struct rb_root *root);
++
++
++/**
++ * bfq_active_insert - insert an entity in the active tree of its
++ * group/device.
++ * @st: the service tree of the entity.
++ * @entity: the entity being inserted.
++ *
++ * The active tree is ordered by finish time, but an extra key is kept
++ * per each node, containing the minimum value for the start times of
++ * its children (and the node itself), so it's possible to search for
++ * the eligible node with the lowest finish time in logarithmic time.
++ */
++static void bfq_active_insert(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct rb_node *node = &entity->rb_node;
++#ifdef CONFIG_CGROUP_BFQIO
++ struct bfq_sched_data *sd = NULL;
++ struct bfq_group *bfqg = NULL;
++ struct bfq_data *bfqd = NULL;
++#endif
++
++ bfq_insert(&st->active, entity);
++
++ if (node->rb_left != NULL)
++ node = node->rb_left;
++ else if (node->rb_right != NULL)
++ node = node->rb_right;
++
++ bfq_update_active_tree(node);
++
++#ifdef CONFIG_CGROUP_BFQIO
++ sd = entity->sched_data;
++ bfqg = container_of(sd, struct bfq_group, sched_data);
++ BUG_ON(!bfqg);
++ bfqd = (struct bfq_data *)bfqg->bfqd;
++#endif
++ if (bfqq != NULL)
++ list_add(&bfqq->bfqq_list, &bfqq->bfqd->active_list);
++#ifdef CONFIG_CGROUP_BFQIO
++ else { /* bfq_group */
++ BUG_ON(!bfqd);
++ bfq_weights_tree_add(bfqd, entity, &bfqd->group_weights_tree);
++ }
++ if (bfqg != bfqd->root_group) {
++ BUG_ON(!bfqg);
++ BUG_ON(!bfqd);
++ bfqg->active_entities++;
++ if (bfqg->active_entities == 2)
++ bfqd->active_numerous_groups++;
++ }
++#endif
++}
++
++/**
++ * bfq_ioprio_to_weight - calc a weight from an ioprio.
++ * @ioprio: the ioprio value to convert.
++ */
++static inline unsigned short bfq_ioprio_to_weight(int ioprio)
++{
++ BUG_ON(ioprio < 0 || ioprio >= IOPRIO_BE_NR);
++ return IOPRIO_BE_NR - ioprio;
++}
++
++/**
++ * bfq_weight_to_ioprio - calc an ioprio from a weight.
++ * @weight: the weight value to convert.
++ *
++ * To preserve as mush as possible the old only-ioprio user interface,
++ * 0 is used as an escape ioprio value for weights (numerically) equal or
++ * larger than IOPRIO_BE_NR
++ */
++static inline unsigned short bfq_weight_to_ioprio(int weight)
++{
++ BUG_ON(weight < BFQ_MIN_WEIGHT || weight > BFQ_MAX_WEIGHT);
++ return IOPRIO_BE_NR - weight < 0 ? 0 : IOPRIO_BE_NR - weight;
++}
++
++static inline void bfq_get_entity(struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++
++ if (bfqq != NULL) {
++ atomic_inc(&bfqq->ref);
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "get_entity: %p %d",
++ bfqq, atomic_read(&bfqq->ref));
++ }
++}
++
++/**
++ * bfq_find_deepest - find the deepest node that an extraction can modify.
++ * @node: the node being removed.
++ *
++ * Do the first step of an extraction in an rb tree, looking for the
++ * node that will replace @node, and returning the deepest node that
++ * the following modifications to the tree can touch. If @node is the
++ * last node in the tree return %NULL.
++ */
++static struct rb_node *bfq_find_deepest(struct rb_node *node)
++{
++ struct rb_node *deepest;
++
++ if (node->rb_right == NULL && node->rb_left == NULL)
++ deepest = rb_parent(node);
++ else if (node->rb_right == NULL)
++ deepest = node->rb_left;
++ else if (node->rb_left == NULL)
++ deepest = node->rb_right;
++ else {
++ deepest = rb_next(node);
++ if (deepest->rb_right != NULL)
++ deepest = deepest->rb_right;
++ else if (rb_parent(deepest) != node)
++ deepest = rb_parent(deepest);
++ }
++
++ return deepest;
++}
++
++/**
++ * bfq_active_extract - remove an entity from the active tree.
++ * @st: the service_tree containing the tree.
++ * @entity: the entity being removed.
++ */
++static void bfq_active_extract(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct rb_node *node;
++#ifdef CONFIG_CGROUP_BFQIO
++ struct bfq_sched_data *sd = NULL;
++ struct bfq_group *bfqg = NULL;
++ struct bfq_data *bfqd = NULL;
++#endif
++
++ node = bfq_find_deepest(&entity->rb_node);
++ bfq_extract(&st->active, entity);
++
++ if (node != NULL)
++ bfq_update_active_tree(node);
++
++#ifdef CONFIG_CGROUP_BFQIO
++ sd = entity->sched_data;
++ bfqg = container_of(sd, struct bfq_group, sched_data);
++ BUG_ON(!bfqg);
++ bfqd = (struct bfq_data *)bfqg->bfqd;
++#endif
++ if (bfqq != NULL)
++ list_del(&bfqq->bfqq_list);
++#ifdef CONFIG_CGROUP_BFQIO
++ else { /* bfq_group */
++ BUG_ON(!bfqd);
++ bfq_weights_tree_remove(bfqd, entity,
++ &bfqd->group_weights_tree);
++ }
++ if (bfqg != bfqd->root_group) {
++ BUG_ON(!bfqg);
++ BUG_ON(!bfqd);
++ BUG_ON(!bfqg->active_entities);
++ bfqg->active_entities--;
++ if (bfqg->active_entities == 1) {
++ BUG_ON(!bfqd->active_numerous_groups);
++ bfqd->active_numerous_groups--;
++ }
++ }
++#endif
++}
++
++/**
++ * bfq_idle_insert - insert an entity into the idle tree.
++ * @st: the service tree containing the tree.
++ * @entity: the entity to insert.
++ */
++static void bfq_idle_insert(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct bfq_entity *first_idle = st->first_idle;
++ struct bfq_entity *last_idle = st->last_idle;
++
++ if (first_idle == NULL || bfq_gt(first_idle->finish, entity->finish))
++ st->first_idle = entity;
++ if (last_idle == NULL || bfq_gt(entity->finish, last_idle->finish))
++ st->last_idle = entity;
++
++ bfq_insert(&st->idle, entity);
++
++ if (bfqq != NULL)
++ list_add(&bfqq->bfqq_list, &bfqq->bfqd->idle_list);
++}
++
++/**
++ * bfq_forget_entity - remove an entity from the wfq trees.
++ * @st: the service tree.
++ * @entity: the entity being removed.
++ *
++ * Update the device status and forget everything about @entity, putting
++ * the device reference to it, if it is a queue. Entities belonging to
++ * groups are not refcounted.
++ */
++static void bfq_forget_entity(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ struct bfq_sched_data *sd;
++
++ BUG_ON(!entity->on_st);
++
++ entity->on_st = 0;
++ st->wsum -= entity->weight;
++ if (bfqq != NULL) {
++ sd = entity->sched_data;
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "forget_entity: %p %d",
++ bfqq, atomic_read(&bfqq->ref));
++ bfq_put_queue(bfqq);
++ }
++}
++
++/**
++ * bfq_put_idle_entity - release the idle tree ref of an entity.
++ * @st: service tree for the entity.
++ * @entity: the entity being released.
++ */
++static void bfq_put_idle_entity(struct bfq_service_tree *st,
++ struct bfq_entity *entity)
++{
++ bfq_idle_extract(st, entity);
++ bfq_forget_entity(st, entity);
++}
++
++/**
++ * bfq_forget_idle - update the idle tree if necessary.
++ * @st: the service tree to act upon.
++ *
++ * To preserve the global O(log N) complexity we only remove one entry here;
++ * as the idle tree will not grow indefinitely this can be done safely.
++ */
++static void bfq_forget_idle(struct bfq_service_tree *st)
++{
++ struct bfq_entity *first_idle = st->first_idle;
++ struct bfq_entity *last_idle = st->last_idle;
++
++ if (RB_EMPTY_ROOT(&st->active) && last_idle != NULL &&
++ !bfq_gt(last_idle->finish, st->vtime)) {
++ /*
++ * Forget the whole idle tree, increasing the vtime past
++ * the last finish time of idle entities.
++ */
++ st->vtime = last_idle->finish;
++ }
++
++ if (first_idle != NULL && !bfq_gt(first_idle->finish, st->vtime))
++ bfq_put_idle_entity(st, first_idle);
++}
++
++static struct bfq_service_tree *
++__bfq_entity_update_weight_prio(struct bfq_service_tree *old_st,
++ struct bfq_entity *entity)
++{
++ struct bfq_service_tree *new_st = old_st;
++
++ if (entity->ioprio_changed) {
++ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity);
++ unsigned short prev_weight, new_weight;
++ struct bfq_data *bfqd = NULL;
++ struct rb_root *root;
++#ifdef CONFIG_CGROUP_BFQIO
++ struct bfq_sched_data *sd;
++ struct bfq_group *bfqg;
++#endif
++
++ if (bfqq != NULL)
++ bfqd = bfqq->bfqd;
++#ifdef CONFIG_CGROUP_BFQIO
++ else {
++ sd = entity->my_sched_data;
++ bfqg = container_of(sd, struct bfq_group, sched_data);
++ BUG_ON(!bfqg);
++ bfqd = (struct bfq_data *)bfqg->bfqd;
++ BUG_ON(!bfqd);
++ }
++#endif
++
++ BUG_ON(old_st->wsum < entity->weight);
++ old_st->wsum -= entity->weight;
++
++ if (entity->new_weight != entity->orig_weight) {
++ if (entity->new_weight < BFQ_MIN_WEIGHT ||
++ entity->new_weight > BFQ_MAX_WEIGHT) {
++ printk(KERN_CRIT "update_weight_prio: "
++ "new_weight %d\n",
++ entity->new_weight);
++ BUG();
++ }
++ entity->orig_weight = entity->new_weight;
++ entity->ioprio =
++ bfq_weight_to_ioprio(entity->orig_weight);
++ }
++
++ entity->ioprio_class = entity->new_ioprio_class;
++ entity->ioprio_changed = 0;
++
++ /*
++ * NOTE: here we may be changing the weight too early,
++ * this will cause unfairness. The correct approach
++ * would have required additional complexity to defer
++ * weight changes to the proper time instants (i.e.,
++ * when entity->finish <= old_st->vtime).
++ */
++ new_st = bfq_entity_service_tree(entity);
++
++ prev_weight = entity->weight;
++ new_weight = entity->orig_weight *
++ (bfqq != NULL ? bfqq->wr_coeff : 1);
++ /*
++ * If the weight of the entity changes, remove the entity
++ * from its old weight counter (if there is a counter
++ * associated with the entity), and add it to the counter
++ * associated with its new weight.
++ */
++ if (prev_weight != new_weight) {
++ root = bfqq ? &bfqd->queue_weights_tree :
++ &bfqd->group_weights_tree;
++ bfq_weights_tree_remove(bfqd, entity, root);
++ }
++ entity->weight = new_weight;
++ /*
++ * Add the entity to its weights tree only if it is
++ * not associated with a weight-raised queue.
++ */
++ if (prev_weight != new_weight &&
++ (bfqq ? bfqq->wr_coeff == 1 : 1))
++ /* If we get here, root has been initialized. */
++ bfq_weights_tree_add(bfqd, entity, root);
++
++ new_st->wsum += entity->weight;
++
++ if (new_st != old_st)
++ entity->start = new_st->vtime;
++ }
++
++ return new_st;
++}
++
++/**
++ * bfq_bfqq_served - update the scheduler status after selection for
++ * service.
++ * @bfqq: the queue being served.
++ * @served: bytes to transfer.
++ *
++ * NOTE: this can be optimized, as the timestamps of upper level entities
++ * are synchronized every time a new bfqq is selected for service. By now,
++ * we keep it to better check consistency.
++ */
++static void bfq_bfqq_served(struct bfq_queue *bfqq, unsigned long served)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++ struct bfq_service_tree *st;
++
++ for_each_entity(entity) {
++ st = bfq_entity_service_tree(entity);
++
++ entity->service += served;
++ BUG_ON(entity->service > entity->budget);
++ BUG_ON(st->wsum == 0);
++
++ st->vtime += bfq_delta(served, st->wsum);
++ bfq_forget_idle(st);
++ }
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "bfqq_served %lu secs", served);
++}
++
++/**
++ * bfq_bfqq_charge_full_budget - set the service to the entity budget.
++ * @bfqq: the queue that needs a service update.
++ *
++ * When it's not possible to be fair in the service domain, because
++ * a queue is not consuming its budget fast enough (the meaning of
++ * fast depends on the timeout parameter), we charge it a full
++ * budget. In this way we should obtain a sort of time-domain
++ * fairness among all the seeky/slow queues.
++ */
++static inline void bfq_bfqq_charge_full_budget(struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++
++ bfq_log_bfqq(bfqq->bfqd, bfqq, "charge_full_budget");
++
++ bfq_bfqq_served(bfqq, entity->budget - entity->service);
++}
++
++/**
++ * __bfq_activate_entity - activate an entity.
++ * @entity: the entity being activated.
++ *
++ * Called whenever an entity is activated, i.e., it is not active and one
++ * of its children receives a new request, or has to be reactivated due to
++ * budget exhaustion. It uses the current budget of the entity (and the
++ * service received if @entity is active) of the queue to calculate its
++ * timestamps.
++ */
++static void __bfq_activate_entity(struct bfq_entity *entity)
++{
++ struct bfq_sched_data *sd = entity->sched_data;
++ struct bfq_service_tree *st = bfq_entity_service_tree(entity);
++
++ if (entity == sd->in_service_entity) {
++ BUG_ON(entity->tree != NULL);
++ /*
++ * If we are requeueing the current entity we have
++ * to take care of not charging to it service it has
++ * not received.
++ */
++ bfq_calc_finish(entity, entity->service);
++ entity->start = entity->finish;
++ sd->in_service_entity = NULL;
++ } else if (entity->tree == &st->active) {
++ /*
++ * Requeueing an entity due to a change of some
++ * next_in_service entity below it. We reuse the
++ * old start time.
++ */
++ bfq_active_extract(st, entity);
++ } else if (entity->tree == &st->idle) {
++ /*
++ * Must be on the idle tree, bfq_idle_extract() will
++ * check for that.
++ */
++ bfq_idle_extract(st, entity);
++ entity->start = bfq_gt(st->vtime, entity->finish) ?
++ st->vtime : entity->finish;
++ } else {
++ /*
++ * The finish time of the entity may be invalid, and
++ * it is in the past for sure, otherwise the queue
++ * would have been on the idle tree.
++ */
++ entity->start = st->vtime;
++ st->wsum += entity->weight;
++ bfq_get_entity(entity);
++
++ BUG_ON(entity->on_st);
++ entity->on_st = 1;
++ }
++
++ st = __bfq_entity_update_weight_prio(st, entity);
++ bfq_calc_finish(entity, entity->budget);
++ bfq_active_insert(st, entity);
++}
++
++/**
++ * bfq_activate_entity - activate an entity and its ancestors if necessary.
++ * @entity: the entity to activate.
++ *
++ * Activate @entity and all the entities on the path from it to the root.
++ */
++static void bfq_activate_entity(struct bfq_entity *entity)
++{
++ struct bfq_sched_data *sd;
++
++ for_each_entity(entity) {
++ __bfq_activate_entity(entity);
++
++ sd = entity->sched_data;
++ if (!bfq_update_next_in_service(sd))
++ /*
++ * No need to propagate the activation to the
++ * upper entities, as they will be updated when
++ * the in-service entity is rescheduled.
++ */
++ break;
++ }
++}
++
++/**
++ * __bfq_deactivate_entity - deactivate an entity from its service tree.
++ * @entity: the entity to deactivate.
++ * @requeue: if false, the entity will not be put into the idle tree.
++ *
++ * Deactivate an entity, independently from its previous state. If the
++ * entity was not on a service tree just return, otherwise if it is on
++ * any scheduler tree, extract it from that tree, and if necessary
++ * and if the caller did not specify @requeue, put it on the idle tree.
++ *
++ * Return %1 if the caller should update the entity hierarchy, i.e.,
++ * if the entity was in service or if it was the next_in_service for
++ * its sched_data; return %0 otherwise.
++ */
++static int __bfq_deactivate_entity(struct bfq_entity *entity, int requeue)
++{
++ struct bfq_sched_data *sd = entity->sched_data;
++ struct bfq_service_tree *st = bfq_entity_service_tree(entity);
++ int was_in_service = entity == sd->in_service_entity;
++ int ret = 0;
++
++ if (!entity->on_st)
++ return 0;
++
++ BUG_ON(was_in_service && entity->tree != NULL);
++
++ if (was_in_service) {
++ bfq_calc_finish(entity, entity->service);
++ sd->in_service_entity = NULL;
++ } else if (entity->tree == &st->active)
++ bfq_active_extract(st, entity);
++ else if (entity->tree == &st->idle)
++ bfq_idle_extract(st, entity);
++ else if (entity->tree != NULL)
++ BUG();
++
++ if (was_in_service || sd->next_in_service == entity)
++ ret = bfq_update_next_in_service(sd);
++
++ if (!requeue || !bfq_gt(entity->finish, st->vtime))
++ bfq_forget_entity(st, entity);
++ else
++ bfq_idle_insert(st, entity);
++
++ BUG_ON(sd->in_service_entity == entity);
++ BUG_ON(sd->next_in_service == entity);
++
++ return ret;
++}
++
++/**
++ * bfq_deactivate_entity - deactivate an entity.
++ * @entity: the entity to deactivate.
++ * @requeue: true if the entity can be put on the idle tree
++ */
++static void bfq_deactivate_entity(struct bfq_entity *entity, int requeue)
++{
++ struct bfq_sched_data *sd;
++ struct bfq_entity *parent;
++
++ for_each_entity_safe(entity, parent) {
++ sd = entity->sched_data;
++
++ if (!__bfq_deactivate_entity(entity, requeue))
++ /*
++ * The parent entity is still backlogged, and
++ * we don't need to update it as it is still
++ * in service.
++ */
++ break;
++
++ if (sd->next_in_service != NULL)
++ /*
++ * The parent entity is still backlogged and
++ * the budgets on the path towards the root
++ * need to be updated.
++ */
++ goto update;
++
++ /*
++ * If we reach there the parent is no more backlogged and
++ * we want to propagate the dequeue upwards.
++ */
++ requeue = 1;
++ }
++
++ return;
++
++update:
++ entity = parent;
++ for_each_entity(entity) {
++ __bfq_activate_entity(entity);
++
++ sd = entity->sched_data;
++ if (!bfq_update_next_in_service(sd))
++ break;
++ }
++}
++
++/**
++ * bfq_update_vtime - update vtime if necessary.
++ * @st: the service tree to act upon.
++ *
++ * If necessary update the service tree vtime to have at least one
++ * eligible entity, skipping to its start time. Assumes that the
++ * active tree of the device is not empty.
++ *
++ * NOTE: this hierarchical implementation updates vtimes quite often,
++ * we may end up with reactivated processes getting timestamps after a
++ * vtime skip done because we needed a ->first_active entity on some
++ * intermediate node.
++ */
++static void bfq_update_vtime(struct bfq_service_tree *st)
++{
++ struct bfq_entity *entry;
++ struct rb_node *node = st->active.rb_node;
++
++ entry = rb_entry(node, struct bfq_entity, rb_node);
++ if (bfq_gt(entry->min_start, st->vtime)) {
++ st->vtime = entry->min_start;
++ bfq_forget_idle(st);
++ }
++}
++
++/**
++ * bfq_first_active_entity - find the eligible entity with
++ * the smallest finish time
++ * @st: the service tree to select from.
++ *
++ * This function searches the first schedulable entity, starting from the
++ * root of the tree and going on the left every time on this side there is
++ * a subtree with at least one eligible (start >= vtime) entity. The path on
++ * the right is followed only if a) the left subtree contains no eligible
++ * entities and b) no eligible entity has been found yet.
++ */
++static struct bfq_entity *bfq_first_active_entity(struct bfq_service_tree *st)
++{
++ struct bfq_entity *entry, *first = NULL;
++ struct rb_node *node = st->active.rb_node;
++
++ while (node != NULL) {
++ entry = rb_entry(node, struct bfq_entity, rb_node);
++left:
++ if (!bfq_gt(entry->start, st->vtime))
++ first = entry;
++
++ BUG_ON(bfq_gt(entry->min_start, st->vtime));
++
++ if (node->rb_left != NULL) {
++ entry = rb_entry(node->rb_left,
++ struct bfq_entity, rb_node);
++ if (!bfq_gt(entry->min_start, st->vtime)) {
++ node = node->rb_left;
++ goto left;
++ }
++ }
++ if (first != NULL)
++ break;
++ node = node->rb_right;
++ }
++
++ BUG_ON(first == NULL && !RB_EMPTY_ROOT(&st->active));
++ return first;
++}
++
++/**
++ * __bfq_lookup_next_entity - return the first eligible entity in @st.
++ * @st: the service tree.
++ *
++ * Update the virtual time in @st and return the first eligible entity
++ * it contains.
++ */
++static struct bfq_entity *__bfq_lookup_next_entity(struct bfq_service_tree *st,
++ bool force)
++{
++ struct bfq_entity *entity, *new_next_in_service = NULL;
++
++ if (RB_EMPTY_ROOT(&st->active))
++ return NULL;
++
++ bfq_update_vtime(st);
++ entity = bfq_first_active_entity(st);
++ BUG_ON(bfq_gt(entity->start, st->vtime));
++
++ /*
++ * If the chosen entity does not match with the sched_data's
++ * next_in_service and we are forcedly serving the IDLE priority
++ * class tree, bubble up budget update.
++ */
++ if (unlikely(force && entity != entity->sched_data->next_in_service)) {
++ new_next_in_service = entity;
++ for_each_entity(new_next_in_service)
++ bfq_update_budget(new_next_in_service);
++ }
++
++ return entity;
++}
++
++/**
++ * bfq_lookup_next_entity - return the first eligible entity in @sd.
++ * @sd: the sched_data.
++ * @extract: if true the returned entity will be also extracted from @sd.
++ *
++ * NOTE: since we cache the next_in_service entity at each level of the
++ * hierarchy, the complexity of the lookup can be decreased with
++ * absolutely no effort just returning the cached next_in_service value;
++ * we prefer to do full lookups to test the consistency of * the data
++ * structures.
++ */
++static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd,
++ int extract,
++ struct bfq_data *bfqd)
++{
++ struct bfq_service_tree *st = sd->service_tree;
++ struct bfq_entity *entity;
++ int i = 0;
++
++ BUG_ON(sd->in_service_entity != NULL);
++
++ if (bfqd != NULL &&
++ jiffies - bfqd->bfq_class_idle_last_service > BFQ_CL_IDLE_TIMEOUT) {
++ entity = __bfq_lookup_next_entity(st + BFQ_IOPRIO_CLASSES - 1,
++ true);
++ if (entity != NULL) {
++ i = BFQ_IOPRIO_CLASSES - 1;
++ bfqd->bfq_class_idle_last_service = jiffies;
++ sd->next_in_service = entity;
++ }
++ }
++ for (; i < BFQ_IOPRIO_CLASSES; i++) {
++ entity = __bfq_lookup_next_entity(st + i, false);
++ if (entity != NULL) {
++ if (extract) {
++ bfq_check_next_in_service(sd, entity);
++ bfq_active_extract(st + i, entity);
++ sd->in_service_entity = entity;
++ sd->next_in_service = NULL;
++ }
++ break;
++ }
++ }
++
++ return entity;
++}
++
++/*
++ * Get next queue for service.
++ */
++static struct bfq_queue *bfq_get_next_queue(struct bfq_data *bfqd)
++{
++ struct bfq_entity *entity = NULL;
++ struct bfq_sched_data *sd;
++ struct bfq_queue *bfqq;
++
++ BUG_ON(bfqd->in_service_queue != NULL);
++
++ if (bfqd->busy_queues == 0)
++ return NULL;
++
++ sd = &bfqd->root_group->sched_data;
++ for (; sd != NULL; sd = entity->my_sched_data) {
++ entity = bfq_lookup_next_entity(sd, 1, bfqd);
++ BUG_ON(entity == NULL);
++ entity->service = 0;
++ }
++
++ bfqq = bfq_entity_to_bfqq(entity);
++ BUG_ON(bfqq == NULL);
++
++ return bfqq;
++}
++
++static void __bfq_bfqd_reset_in_service(struct bfq_data *bfqd)
++{
++ if (bfqd->in_service_bic != NULL) {
++ put_io_context(bfqd->in_service_bic->icq.ioc);
++ bfqd->in_service_bic = NULL;
++ }
++
++ bfqd->in_service_queue = NULL;
++ del_timer(&bfqd->idle_slice_timer);
++}
++
++static void bfq_deactivate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ int requeue)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++
++ if (bfqq == bfqd->in_service_queue)
++ __bfq_bfqd_reset_in_service(bfqd);
++
++ bfq_deactivate_entity(entity, requeue);
++}
++
++static void bfq_activate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ struct bfq_entity *entity = &bfqq->entity;
++
++ bfq_activate_entity(entity);
++}
++
++/*
++ * Called when the bfqq no longer has requests pending, remove it from
++ * the service tree.
++ */
++static void bfq_del_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq,
++ int requeue)
++{
++ BUG_ON(!bfq_bfqq_busy(bfqq));
++ BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list));
++
++ bfq_log_bfqq(bfqd, bfqq, "del from busy");
++
++ bfq_clear_bfqq_busy(bfqq);
++
++ BUG_ON(bfqd->busy_queues == 0);
++ bfqd->busy_queues--;
++
++ if (!bfqq->dispatched) {
++ bfq_weights_tree_remove(bfqd, &bfqq->entity,
++ &bfqd->queue_weights_tree);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ BUG_ON(!bfqd->busy_in_flight_queues);
++ bfqd->busy_in_flight_queues--;
++ if (bfq_bfqq_constantly_seeky(bfqq)) {
++ BUG_ON(!bfqd->
++ const_seeky_busy_in_flight_queues);
++ bfqd->const_seeky_busy_in_flight_queues--;
++ }
++ }
++ }
++ if (bfqq->wr_coeff > 1)
++ bfqd->wr_busy_queues--;
++
++ bfq_deactivate_bfqq(bfqd, bfqq, requeue);
++}
++
++/*
++ * Called when an inactive queue receives a new request.
++ */
++static void bfq_add_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq)
++{
++ BUG_ON(bfq_bfqq_busy(bfqq));
++ BUG_ON(bfqq == bfqd->in_service_queue);
++
++ bfq_log_bfqq(bfqd, bfqq, "add to busy");
++
++ bfq_activate_bfqq(bfqd, bfqq);
++
++ bfq_mark_bfqq_busy(bfqq);
++ bfqd->busy_queues++;
++
++ if (!bfqq->dispatched) {
++ if (bfqq->wr_coeff == 1)
++ bfq_weights_tree_add(bfqd, &bfqq->entity,
++ &bfqd->queue_weights_tree);
++ if (!blk_queue_nonrot(bfqd->queue)) {
++ bfqd->busy_in_flight_queues++;
++ if (bfq_bfqq_constantly_seeky(bfqq))
++ bfqd->const_seeky_busy_in_flight_queues++;
++ }
++ }
++ if (bfqq->wr_coeff > 1)
++ bfqd->wr_busy_queues++;
++}
+diff -Nur linux-3.14.72.orig/block/Kconfig.iosched linux-3.14.72/block/Kconfig.iosched
+--- linux-3.14.72.orig/block/Kconfig.iosched 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/block/Kconfig.iosched 2016-06-19 22:11:55.065155743 +0200
+@@ -39,6 +39,27 @@
+ ---help---
+ Enable group IO scheduling in CFQ.
+
++config IOSCHED_BFQ
++ tristate "BFQ I/O scheduler"
++ default n
++ ---help---
++ The BFQ I/O scheduler tries to distribute bandwidth among
++ all processes according to their weights.
++ It aims at distributing the bandwidth as desired, independently of
++ the disk parameters and with any workload. It also tries to
++ guarantee low latency to interactive and soft real-time
++ applications. If compiled built-in (saying Y here), BFQ can
++ be configured to support hierarchical scheduling.
++
++config CGROUP_BFQIO
++ bool "BFQ hierarchical scheduling support"
++ depends on CGROUPS && IOSCHED_BFQ=y
++ default n
++ ---help---
++ Enable hierarchical scheduling in BFQ, using the cgroups
++ filesystem interface. The name of the subsystem will be
++ bfqio.
++
+ choice
+ prompt "Default I/O scheduler"
+ default DEFAULT_CFQ
+@@ -52,6 +73,16 @@
+ config DEFAULT_CFQ
+ bool "CFQ" if IOSCHED_CFQ=y
+
++ config DEFAULT_BFQ
++ bool "BFQ" if IOSCHED_BFQ=y
++ help
++ Selects BFQ as the default I/O scheduler which will be
++ used by default for all block devices.
++ The BFQ I/O scheduler aims at distributing the bandwidth
++ as desired, independently of the disk parameters and with
++ any workload. It also tries to guarantee low latency to
++ interactive and soft real-time applications.
++
+ config DEFAULT_NOOP
+ bool "No-op"
+
+@@ -61,6 +92,7 @@
+ string
+ default "deadline" if DEFAULT_DEADLINE
+ default "cfq" if DEFAULT_CFQ
++ default "bfq" if DEFAULT_BFQ
+ default "noop" if DEFAULT_NOOP
+
+ endmenu
+diff -Nur linux-3.14.72.orig/block/Makefile linux-3.14.72/block/Makefile
+--- linux-3.14.72.orig/block/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/block/Makefile 2016-06-19 22:11:55.065155743 +0200
+@@ -16,6 +16,7 @@
+ obj-$(CONFIG_IOSCHED_NOOP) += noop-iosched.o
+ obj-$(CONFIG_IOSCHED_DEADLINE) += deadline-iosched.o
+ obj-$(CONFIG_IOSCHED_CFQ) += cfq-iosched.o
++obj-$(CONFIG_IOSCHED_BFQ) += bfq-iosched.o
+
+ obj-$(CONFIG_BLOCK_COMPAT) += compat_ioctl.o
+ obj-$(CONFIG_BLK_DEV_INTEGRITY) += blk-integrity.o
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/authenc.c linux-3.14.72/crypto/cryptodev/authenc.c
+--- linux-3.14.72.orig/crypto/cryptodev/authenc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/authenc.c 2016-06-19 22:11:55.065155743 +0200
+@@ -0,0 +1,758 @@
++/*
++ * Driver for /dev/crypto device (aka CryptoDev)
++ *
++ * Copyright (c) 2011, 2012 OpenSSL Software Foundation, Inc.
++ *
++ * Author: Nikos Mavrogiannopoulos
++ *
++ * This file is part of linux cryptodev.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++/*
++ * This file handles the AEAD part of /dev/crypto.
++ *
++ */
++
++#include <crypto/hash.h>
++#include <linux/crypto.h>
++#include <linux/mm.h>
++#include <linux/highmem.h>
++#include <linux/ioctl.h>
++#include <linux/random.h>
++#include <linux/syscalls.h>
++#include <linux/pagemap.h>
++#include <linux/poll.h>
++#include <linux/uaccess.h>
++#include <crypto/cryptodev.h>
++#include <crypto/scatterwalk.h>
++#include <linux/scatterlist.h>
++#include "cryptodev_int.h"
++#include "zc.h"
++#include "util.h"
++#include "cryptlib.h"
++#include "version.h"
++
++
++/* make caop->dst available in scatterlist.
++ * (caop->src is assumed to be equal to caop->dst)
++ */
++static int get_userbuf_tls(struct csession *ses, struct kernel_crypt_auth_op *kcaop,
++ struct scatterlist **dst_sg)
++{
++ int pagecount = 0;
++ struct crypt_auth_op *caop = &kcaop->caop;
++ int rc;
++
++ if (caop->dst == NULL)
++ return -EINVAL;
++
++ if (ses->alignmask) {
++ if (!IS_ALIGNED((unsigned long)caop->dst, ses->alignmask))
++ dwarning(2, "careful - source address %p is not %d byte aligned",
++ caop->dst, ses->alignmask + 1);
++ }
++
++ if (kcaop->dst_len == 0) {
++ dwarning(1, "Destination length cannot be zero");
++ return -EINVAL;
++ }
++
++ pagecount = PAGECOUNT(caop->dst, kcaop->dst_len);
++
++ ses->used_pages = pagecount;
++ ses->readonly_pages = 0;
++
++ rc = adjust_sg_array(ses, pagecount);
++ if (rc)
++ return rc;
++
++ rc = __get_userbuf(caop->dst, kcaop->dst_len, 1, pagecount,
++ ses->pages, ses->sg, kcaop->task, kcaop->mm);
++ if (unlikely(rc)) {
++ derr(1, "failed to get user pages for data input");
++ return -EINVAL;
++ }
++
++ (*dst_sg) = ses->sg;
++
++ return 0;
++}
++
++
++#define MAX_SRTP_AUTH_DATA_DIFF 256
++
++/* Makes caop->auth_src available as scatterlist.
++ * It also provides a pointer to caop->dst, which however,
++ * is assumed to be within the caop->auth_src buffer. If not
++ * (if their difference exceeds MAX_SRTP_AUTH_DATA_DIFF) it
++ * returns error.
++ */
++static int get_userbuf_srtp(struct csession *ses, struct kernel_crypt_auth_op *kcaop,
++ struct scatterlist **auth_sg, struct scatterlist **dst_sg)
++{
++ int pagecount, diff;
++ int auth_pagecount = 0;
++ struct crypt_auth_op *caop = &kcaop->caop;
++ int rc;
++
++ if (caop->dst == NULL && caop->auth_src == NULL) {
++ derr(1, "dst and auth_src cannot be both null");
++ return -EINVAL;
++ }
++
++ if (ses->alignmask) {
++ if (!IS_ALIGNED((unsigned long)caop->dst, ses->alignmask))
++ dwarning(2, "careful - source address %p is not %d byte aligned",
++ caop->dst, ses->alignmask + 1);
++ if (!IS_ALIGNED((unsigned long)caop->auth_src, ses->alignmask))
++ dwarning(2, "careful - source address %p is not %d byte aligned",
++ caop->auth_src, ses->alignmask + 1);
++ }
++
++ if (unlikely(kcaop->dst_len == 0 || caop->auth_len == 0)) {
++ dwarning(1, "Destination length cannot be zero");
++ return -EINVAL;
++ }
++
++ /* Note that in SRTP auth data overlap with data to be encrypted (dst)
++ */
++
++ auth_pagecount = PAGECOUNT(caop->auth_src, caop->auth_len);
++ diff = (int)(caop->src - caop->auth_src);
++ if (diff > MAX_SRTP_AUTH_DATA_DIFF || diff < 0) {
++ dwarning(1, "auth_src must overlap with src (diff: %d).", diff);
++ return -EINVAL;
++ }
++
++ pagecount = auth_pagecount;
++
++ rc = adjust_sg_array(ses, pagecount*2); /* double pages to have pages for dst(=auth_src) */
++ if (rc) {
++ derr(1, "cannot adjust sg array");
++ return rc;
++ }
++
++ rc = __get_userbuf(caop->auth_src, caop->auth_len, 1, auth_pagecount,
++ ses->pages, ses->sg, kcaop->task, kcaop->mm);
++ if (unlikely(rc)) {
++ derr(1, "failed to get user pages for data input");
++ return -EINVAL;
++ }
++
++ ses->used_pages = pagecount;
++ ses->readonly_pages = 0;
++
++ (*auth_sg) = ses->sg;
++
++ (*dst_sg) = ses->sg + auth_pagecount;
++ sg_init_table(*dst_sg, auth_pagecount);
++ sg_copy(ses->sg, (*dst_sg), caop->auth_len);
++ (*dst_sg) = sg_advance(*dst_sg, diff);
++ if (*dst_sg == NULL) {
++ release_user_pages(ses);
++ derr(1, "failed to get enough pages for auth data");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * Return tag (digest) length for authenticated encryption
++ * If the cipher and digest are separate, hdata.init is set - just return
++ * digest length. Otherwise return digest length for aead ciphers
++ */
++static int cryptodev_get_tag_len(struct csession *ses_ptr)
++{
++ if (ses_ptr->hdata.init)
++ return ses_ptr->hdata.digestsize;
++ else
++ return cryptodev_cipher_get_tag_size(&ses_ptr->cdata);
++}
++
++/*
++ * Calculate destination buffer length for authenticated encryption. The
++ * expectation is that user-space code allocates exactly the same space for
++ * destination buffer before calling cryptodev. The result is cipher-dependent.
++ */
++static int cryptodev_get_dst_len(struct crypt_auth_op *caop, struct csession *ses_ptr)
++{
++ int dst_len = caop->len;
++ if (caop->op == COP_DECRYPT)
++ return dst_len;
++
++ dst_len += caop->tag_len;
++
++ /* for TLS always add some padding so the total length is rounded to
++ * cipher block size */
++ if (caop->flags & COP_FLAG_AEAD_TLS_TYPE) {
++ int bs = ses_ptr->cdata.blocksize;
++ dst_len += bs - (dst_len % bs);
++ }
++
++ return dst_len;
++}
++
++static int fill_kcaop_from_caop(struct kernel_crypt_auth_op *kcaop, struct fcrypt *fcr)
++{
++ struct crypt_auth_op *caop = &kcaop->caop;
++ struct csession *ses_ptr;
++ int ret;
++
++ /* this also enters ses_ptr->sem */
++ ses_ptr = crypto_get_session_by_sid(fcr, caop->ses);
++ if (unlikely(!ses_ptr)) {
++ derr(1, "invalid session ID=0x%08X", caop->ses);
++ return -EINVAL;
++ }
++
++ if (caop->flags & COP_FLAG_AEAD_TLS_TYPE || caop->flags & COP_FLAG_AEAD_SRTP_TYPE) {
++ if (caop->src != caop->dst) {
++ derr(1, "Non-inplace encryption and decryption is not efficient and not implemented");
++ ret = -EINVAL;
++ goto out_unlock;
++ }
++ }
++
++ if (caop->tag_len == 0)
++ caop->tag_len = cryptodev_get_tag_len(ses_ptr);
++
++ kcaop->ivlen = caop->iv ? ses_ptr->cdata.ivsize : 0;
++ kcaop->dst_len = cryptodev_get_dst_len(caop, ses_ptr);
++ kcaop->task = current;
++ kcaop->mm = current->mm;
++
++ if (caop->iv) {
++ ret = copy_from_user(kcaop->iv, caop->iv, kcaop->ivlen);
++ if (unlikely(ret)) {
++ derr(1, "error copying IV (%d bytes), copy_from_user returned %d for address %p",
++ kcaop->ivlen, ret, caop->iv);
++ ret = -EFAULT;
++ goto out_unlock;
++ }
++ }
++
++ ret = 0;
++
++out_unlock:
++ crypto_put_session(ses_ptr);
++ return ret;
++
++}
++
++static int fill_caop_from_kcaop(struct kernel_crypt_auth_op *kcaop, struct fcrypt *fcr)
++{
++ int ret;
++
++ kcaop->caop.len = kcaop->dst_len;
++
++ if (kcaop->ivlen && kcaop->caop.flags & COP_FLAG_WRITE_IV) {
++ ret = copy_to_user(kcaop->caop.iv,
++ kcaop->iv, kcaop->ivlen);
++ if (unlikely(ret)) {
++ derr(1, "Error in copying to userspace");
++ return -EFAULT;
++ }
++ }
++ return 0;
++}
++
++
++int kcaop_from_user(struct kernel_crypt_auth_op *kcaop,
++ struct fcrypt *fcr, void __user *arg)
++{
++ if (unlikely(copy_from_user(&kcaop->caop, arg, sizeof(kcaop->caop)))) {
++ derr(1, "Error in copying from userspace");
++ return -EFAULT;
++ }
++
++ return fill_kcaop_from_caop(kcaop, fcr);
++}
++
++int kcaop_to_user(struct kernel_crypt_auth_op *kcaop,
++ struct fcrypt *fcr, void __user *arg)
++{
++ int ret;
++
++ ret = fill_caop_from_kcaop(kcaop, fcr);
++ if (unlikely(ret)) {
++ derr(1, "fill_caop_from_kcaop");
++ return ret;
++ }
++
++ if (unlikely(copy_to_user(arg, &kcaop->caop, sizeof(kcaop->caop)))) {
++ derr(1, "Error in copying to userspace");
++ return -EFAULT;
++ }
++ return 0;
++}
++
++static void copy_tls_hash(struct scatterlist *dst_sg, int len, void *hash, int hash_len)
++{
++ scatterwalk_map_and_copy(hash, dst_sg, len, hash_len, 1);
++}
++
++static void read_tls_hash(struct scatterlist *dst_sg, int len, void *hash, int hash_len)
++{
++ scatterwalk_map_and_copy(hash, dst_sg, len - hash_len, hash_len, 0);
++}
++
++static int pad_record(struct scatterlist *dst_sg, int len, int block_size)
++{
++ uint8_t pad[block_size];
++ int pad_size = block_size - (len % block_size);
++
++ memset(pad, pad_size - 1, pad_size);
++
++ scatterwalk_map_and_copy(pad, dst_sg, len, pad_size, 1);
++
++ return pad_size;
++}
++
++static int verify_tls_record_pad(struct scatterlist *dst_sg, int len, int block_size)
++{
++ uint8_t pad[256]; /* the maximum allowed */
++ uint8_t pad_size;
++ int i;
++
++ scatterwalk_map_and_copy(&pad_size, dst_sg, len - 1, 1, 0);
++
++ if (pad_size + 1 > len) {
++ derr(1, "Pad size: %d", pad_size);
++ return -EBADMSG;
++ }
++
++ scatterwalk_map_and_copy(pad, dst_sg, len - pad_size - 1, pad_size + 1, 0);
++
++ for (i = 0; i < pad_size; i++)
++ if (pad[i] != pad_size) {
++ derr(1, "Pad size: %u, pad: %d", pad_size, pad[i]);
++ return -EBADMSG;
++ }
++
++ return pad_size + 1;
++}
++
++/* Authenticate and encrypt the TLS way (also perform padding).
++ * During decryption it verifies the pad and tag and returns -EBADMSG on error.
++ */
++static int
++tls_auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop,
++ struct scatterlist *auth_sg, uint32_t auth_len,
++ struct scatterlist *dst_sg, uint32_t len)
++{
++ int ret, fail = 0;
++ struct crypt_auth_op *caop = &kcaop->caop;
++ uint8_t vhash[AALG_MAX_RESULT_LEN];
++ uint8_t hash_output[AALG_MAX_RESULT_LEN];
++
++ /* TLS authenticates the plaintext except for the padding.
++ */
++ if (caop->op == COP_ENCRYPT) {
++ if (ses_ptr->hdata.init != 0) {
++ if (auth_len > 0) {
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ auth_sg, auth_len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_update: %d", ret);
++ return ret;
++ }
++ }
++
++ if (len > 0) {
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ dst_sg, len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_update: %d", ret);
++ return ret;
++ }
++ }
++
++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_final: %d", ret);
++ return ret;
++ }
++
++ copy_tls_hash(dst_sg, len, hash_output, caop->tag_len);
++ len += caop->tag_len;
++ }
++
++ if (ses_ptr->cdata.init != 0) {
++ if (ses_ptr->cdata.blocksize > 1) {
++ ret = pad_record(dst_sg, len, ses_ptr->cdata.blocksize);
++ len += ret;
++ }
++
++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata,
++ dst_sg, dst_sg, len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_cipher_encrypt: %d", ret);
++ return ret;
++ }
++ }
++ } else {
++ if (ses_ptr->cdata.init != 0) {
++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata,
++ dst_sg, dst_sg, len);
++
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_cipher_decrypt: %d", ret);
++ return ret;
++ }
++
++ if (ses_ptr->cdata.blocksize > 1) {
++ ret = verify_tls_record_pad(dst_sg, len, ses_ptr->cdata.blocksize);
++ if (unlikely(ret < 0)) {
++ derr(2, "verify_record_pad: %d", ret);
++ fail = 1;
++ } else {
++ len -= ret;
++ }
++ }
++ }
++
++ if (ses_ptr->hdata.init != 0) {
++ if (unlikely(caop->tag_len > sizeof(vhash) || caop->tag_len > len)) {
++ derr(1, "Illegal tag len size");
++ return -EINVAL;
++ }
++
++ read_tls_hash(dst_sg, len, vhash, caop->tag_len);
++ len -= caop->tag_len;
++
++ if (auth_len > 0) {
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ auth_sg, auth_len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_update: %d", ret);
++ return ret;
++ }
++ }
++
++ if (len > 0) {
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ dst_sg, len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_update: %d", ret);
++ return ret;
++ }
++ }
++
++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_final: %d", ret);
++ return ret;
++ }
++
++ if (memcmp(vhash, hash_output, caop->tag_len) != 0 || fail != 0) {
++ derr(2, "MAC verification failed (tag_len: %d)", caop->tag_len);
++ return -EBADMSG;
++ }
++ }
++ }
++ kcaop->dst_len = len;
++ return 0;
++}
++
++/* Authenticate and encrypt the SRTP way. During decryption
++ * it verifies the tag and returns -EBADMSG on error.
++ */
++static int
++srtp_auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop,
++ struct scatterlist *auth_sg, uint32_t auth_len,
++ struct scatterlist *dst_sg, uint32_t len)
++{
++ int ret, fail = 0;
++ struct crypt_auth_op *caop = &kcaop->caop;
++ uint8_t vhash[AALG_MAX_RESULT_LEN];
++ uint8_t hash_output[AALG_MAX_RESULT_LEN];
++
++ /* SRTP authenticates the encrypted data.
++ */
++ if (caop->op == COP_ENCRYPT) {
++ if (ses_ptr->cdata.init != 0) {
++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata,
++ dst_sg, dst_sg, len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_cipher_encrypt: %d", ret);
++ return ret;
++ }
++ }
++
++ if (ses_ptr->hdata.init != 0) {
++ if (auth_len > 0) {
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ auth_sg, auth_len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_update: %d", ret);
++ return ret;
++ }
++ }
++
++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_final: %d", ret);
++ return ret;
++ }
++
++ if (unlikely(copy_to_user(caop->tag, hash_output, caop->tag_len)))
++ return -EFAULT;
++ }
++
++ } else {
++ if (ses_ptr->hdata.init != 0) {
++ if (unlikely(caop->tag_len > sizeof(vhash) || caop->tag_len > len)) {
++ derr(1, "Illegal tag len size");
++ return -EINVAL;
++ }
++
++ if (unlikely(copy_from_user(vhash, caop->tag, caop->tag_len)))
++ return -EFAULT;
++
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ auth_sg, auth_len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_update: %d", ret);
++ return ret;
++ }
++
++ ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_hash_final: %d", ret);
++ return ret;
++ }
++
++ if (memcmp(vhash, hash_output, caop->tag_len) != 0 || fail != 0) {
++ derr(2, "MAC verification failed");
++ return -EBADMSG;
++ }
++ }
++
++ if (ses_ptr->cdata.init != 0) {
++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata,
++ dst_sg, dst_sg, len);
++
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_cipher_decrypt: %d", ret);
++ return ret;
++ }
++ }
++
++ }
++ kcaop->dst_len = len;
++ return 0;
++}
++
++/* Typical AEAD (i.e. GCM) encryption/decryption.
++ * During decryption the tag is verified.
++ */
++static int
++auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop,
++ struct scatterlist *auth_sg, uint32_t auth_len,
++ struct scatterlist *src_sg,
++ struct scatterlist *dst_sg, uint32_t len)
++{
++ int ret;
++ struct crypt_auth_op *caop = &kcaop->caop;
++ int max_tag_len;
++
++ max_tag_len = cryptodev_cipher_get_tag_size(&ses_ptr->cdata);
++ if (unlikely(caop->tag_len > max_tag_len)) {
++ derr(0, "Illegal tag length: %d", caop->tag_len);
++ return -EINVAL;
++ }
++
++ if (caop->tag_len)
++ cryptodev_cipher_set_tag_size(&ses_ptr->cdata, caop->tag_len);
++ else
++ caop->tag_len = max_tag_len;
++
++ cryptodev_cipher_auth(&ses_ptr->cdata, auth_sg, auth_len);
++
++ if (caop->op == COP_ENCRYPT) {
++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata,
++ src_sg, dst_sg, len);
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_cipher_encrypt: %d", ret);
++ return ret;
++ }
++ kcaop->dst_len = len + caop->tag_len;
++ caop->tag = caop->dst + len;
++ } else {
++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata,
++ src_sg, dst_sg, len);
++
++ if (unlikely(ret)) {
++ derr(0, "cryptodev_cipher_decrypt: %d", ret);
++ return ret;
++ }
++ kcaop->dst_len = len - caop->tag_len;
++ caop->tag = caop->dst + len - caop->tag_len;
++ }
++
++ return 0;
++}
++
++/* This is the main crypto function - zero-copy edition */
++static int
++__crypto_auth_run_zc(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop)
++{
++ struct scatterlist *dst_sg, *auth_sg, *src_sg;
++ struct crypt_auth_op *caop = &kcaop->caop;
++ int ret = 0;
++
++ if (caop->flags & COP_FLAG_AEAD_SRTP_TYPE) {
++ if (unlikely(ses_ptr->cdata.init != 0 &&
++ (ses_ptr->cdata.stream == 0 ||
++ ses_ptr->cdata.aead != 0))) {
++ derr(0, "Only stream modes are allowed in SRTP mode (but not AEAD)");
++ return -EINVAL;
++ }
++
++ ret = get_userbuf_srtp(ses_ptr, kcaop, &auth_sg, &dst_sg);
++ if (unlikely(ret)) {
++ derr(1, "get_userbuf_srtp(): Error getting user pages.");
++ return ret;
++ }
++
++ ret = srtp_auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len,
++ dst_sg, caop->len);
++
++ release_user_pages(ses_ptr);
++ } else { /* TLS and normal cases. Here auth data are usually small
++ * so we just copy them to a free page, instead of trying
++ * to map them.
++ */
++ unsigned char *auth_buf = NULL;
++ struct scatterlist tmp;
++
++ if (unlikely(caop->auth_len > PAGE_SIZE)) {
++ derr(1, "auth data len is excessive.");
++ return -EINVAL;
++ }
++
++ auth_buf = (char *)__get_free_page(GFP_KERNEL);
++ if (unlikely(!auth_buf)) {
++ derr(1, "unable to get a free page.");
++ return -ENOMEM;
++ }
++
++ if (caop->auth_src && caop->auth_len > 0) {
++ if (unlikely(copy_from_user(auth_buf, caop->auth_src, caop->auth_len))) {
++ derr(1, "unable to copy auth data from userspace.");
++ ret = -EFAULT;
++ goto free_auth_buf;
++ }
++
++ sg_init_one(&tmp, auth_buf, caop->auth_len);
++ auth_sg = &tmp;
++ } else {
++ auth_sg = NULL;
++ }
++
++ if (caop->flags & COP_FLAG_AEAD_TLS_TYPE && ses_ptr->cdata.aead == 0) {
++ ret = get_userbuf_tls(ses_ptr, kcaop, &dst_sg);
++ if (unlikely(ret)) {
++ derr(1, "get_userbuf_tls(): Error getting user pages.");
++ goto free_auth_buf;
++ }
++
++ ret = tls_auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len,
++ dst_sg, caop->len);
++ } else {
++ if (unlikely(ses_ptr->cdata.init == 0 ||
++ (ses_ptr->cdata.stream == 0 &&
++ ses_ptr->cdata.aead == 0))) {
++ derr(0, "Only stream and AEAD ciphers are allowed for authenc");
++ ret = -EINVAL;
++ goto free_auth_buf;
++ }
++
++ ret = get_userbuf(ses_ptr, caop->src, caop->len, caop->dst, kcaop->dst_len,
++ kcaop->task, kcaop->mm, &src_sg, &dst_sg);
++ if (unlikely(ret)) {
++ derr(1, "get_userbuf(): Error getting user pages.");
++ goto free_auth_buf;
++ }
++
++ ret = auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len,
++ src_sg, dst_sg, caop->len);
++ }
++
++ release_user_pages(ses_ptr);
++
++free_auth_buf:
++ free_page((unsigned long)auth_buf);
++ }
++
++ return ret;
++}
++
++
++int crypto_auth_run(struct fcrypt *fcr, struct kernel_crypt_auth_op *kcaop)
++{
++ struct csession *ses_ptr;
++ struct crypt_auth_op *caop = &kcaop->caop;
++ int ret;
++
++ if (unlikely(caop->op != COP_ENCRYPT && caop->op != COP_DECRYPT)) {
++ ddebug(1, "invalid operation op=%u", caop->op);
++ return -EINVAL;
++ }
++
++ /* this also enters ses_ptr->sem */
++ ses_ptr = crypto_get_session_by_sid(fcr, caop->ses);
++ if (unlikely(!ses_ptr)) {
++ derr(1, "invalid session ID=0x%08X", caop->ses);
++ return -EINVAL;
++ }
++
++ if (unlikely(ses_ptr->cdata.init == 0)) {
++ derr(1, "cipher context not initialized");
++ ret = -EINVAL;
++ goto out_unlock;
++ }
++
++ /* If we have a hash/mac handle reset its state */
++ if (ses_ptr->hdata.init != 0) {
++ ret = cryptodev_hash_reset(&ses_ptr->hdata);
++ if (unlikely(ret)) {
++ derr(1, "error in cryptodev_hash_reset()");
++ goto out_unlock;
++ }
++ }
++
++ cryptodev_cipher_set_iv(&ses_ptr->cdata, kcaop->iv,
++ min(ses_ptr->cdata.ivsize, kcaop->ivlen));
++
++ ret = __crypto_auth_run_zc(ses_ptr, kcaop);
++ if (unlikely(ret)) {
++ derr(1, "error in __crypto_auth_run_zc()");
++ goto out_unlock;
++ }
++
++ ret = 0;
++
++ cryptodev_cipher_get_iv(&ses_ptr->cdata, kcaop->iv,
++ min(ses_ptr->cdata.ivsize, kcaop->ivlen));
++
++out_unlock:
++ crypto_put_session(ses_ptr);
++ return ret;
++}
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/cryptlib.c linux-3.14.72/crypto/cryptodev/cryptlib.c
+--- linux-3.14.72.orig/crypto/cryptodev/cryptlib.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/cryptlib.c 2016-06-19 22:11:55.065155743 +0200
+@@ -0,0 +1,441 @@
++/*
++ * Driver for /dev/crypto device (aka CryptoDev)
++ *
++ * Copyright (c) 2010,2011 Nikos Mavrogiannopoulos <nmav@gnutls.org>
++ * Portions Copyright (c) 2010 Michael Weiser
++ * Portions Copyright (c) 2010 Phil Sutter
++ *
++ * This file is part of linux cryptodev.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++#include <linux/crypto.h>
++#include <linux/mm.h>
++#include <linux/highmem.h>
++#include <linux/ioctl.h>
++#include <linux/random.h>
++#include <linux/scatterlist.h>
++#include <linux/uaccess.h>
++#include <crypto/algapi.h>
++#include <crypto/hash.h>
++#include <crypto/cryptodev.h>
++#include <crypto/aead.h>
++#include <linux/rtnetlink.h>
++#include <crypto/authenc.h>
++#include "cryptodev_int.h"
++
++
++struct cryptodev_result {
++ struct completion completion;
++ int err;
++};
++
++static void cryptodev_complete(struct crypto_async_request *req, int err)
++{
++ struct cryptodev_result *res = req->data;
++
++ if (err == -EINPROGRESS)
++ return;
++
++ res->err = err;
++ complete(&res->completion);
++}
++
++int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop,
++ int aead)
++{
++ /*
++ * For blockciphers (AES-CBC) or non-composite aead ciphers (like AES-GCM),
++ * the key length is simply the cipher keylen obtained from userspace. If
++ * the cipher is composite aead, the keylen is the sum of cipher keylen,
++ * hmac keylen and a key header length. This key format is the one used in
++ * Linux kernel for composite aead ciphers (crypto/authenc.c)
++ */
++ unsigned int klen = sop->keylen;
++
++ if (unlikely(sop->keylen > CRYPTO_CIPHER_MAX_KEY_LEN))
++ return -EINVAL;
++
++ if (aead && sop->mackeylen) {
++ if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN))
++ return -EINVAL;
++ klen += sop->mackeylen;
++ klen += RTA_SPACE(sizeof(struct crypto_authenc_key_param));
++ }
++
++ *keylen = klen;
++ return 0;
++}
++
++int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead)
++{
++ /*
++ * Get cipher key from user-space. For blockciphers just copy it from
++ * user-space. For composite aead ciphers combine it with the hmac key in
++ * the format used by Linux kernel in crypto/authenc.c:
++ *
++ * [[AUTHENC_KEY_HEADER + CIPHER_KEYLEN] [AUTHENTICATION KEY] [CIPHER KEY]]
++ */
++ struct crypto_authenc_key_param *param;
++ struct rtattr *rta;
++ int ret = 0;
++
++ if (aead && sop->mackeylen) {
++ /*
++ * Composite aead ciphers. The first four bytes are the header type and
++ * header length for aead keys
++ */
++ rta = (void *)key;
++ rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM;
++ rta->rta_len = RTA_LENGTH(sizeof(*param));
++
++ /*
++ * The next four bytes hold the length of the encryption key
++ */
++ param = RTA_DATA(rta);
++ param->enckeylen = cpu_to_be32(sop->keylen);
++
++ /* Advance key pointer eight bytes and copy the hmac key */
++ key += RTA_SPACE(sizeof(*param));
++ if (unlikely(copy_from_user(key, sop->mackey, sop->mackeylen))) {
++ ret = -EFAULT;
++ goto error;
++ }
++ /* Advance key pointer past the hmac key */
++ key += sop->mackeylen;
++ }
++ /* now copy the blockcipher key */
++ if (unlikely(copy_from_user(key, sop->key, sop->keylen)))
++ ret = -EFAULT;
++
++error:
++ return ret;
++}
++
++
++int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name,
++ uint8_t *keyp, size_t keylen, int stream, int aead)
++{
++ int ret;
++
++ if (aead == 0) {
++ struct ablkcipher_alg *alg;
++
++ out->async.s = crypto_alloc_ablkcipher(alg_name, 0, 0);
++ if (unlikely(IS_ERR(out->async.s))) {
++ ddebug(1, "Failed to load cipher %s", alg_name);
++ return -EINVAL;
++ }
++
++ alg = crypto_ablkcipher_alg(out->async.s);
++ if (alg != NULL) {
++ /* Was correct key length supplied? */
++ if (alg->max_keysize > 0 &&
++ unlikely((keylen < alg->min_keysize) ||
++ (keylen > alg->max_keysize))) {
++ ddebug(1, "Wrong keylen '%zu' for algorithm '%s'. Use %u to %u.",
++ keylen, alg_name, alg->min_keysize, alg->max_keysize);
++ ret = -EINVAL;
++ goto error;
++ }
++ }
++
++ out->blocksize = crypto_ablkcipher_blocksize(out->async.s);
++ out->ivsize = crypto_ablkcipher_ivsize(out->async.s);
++ out->alignmask = crypto_ablkcipher_alignmask(out->async.s);
++
++ ret = crypto_ablkcipher_setkey(out->async.s, keyp, keylen);
++ } else {
++ out->async.as = crypto_alloc_aead(alg_name, 0, 0);
++ if (unlikely(IS_ERR(out->async.as))) {
++ ddebug(1, "Failed to load cipher %s", alg_name);
++ return -EINVAL;
++ }
++
++ out->blocksize = crypto_aead_blocksize(out->async.as);
++ out->ivsize = crypto_aead_ivsize(out->async.as);
++ out->alignmask = crypto_aead_alignmask(out->async.as);
++
++ ret = crypto_aead_setkey(out->async.as, keyp, keylen);
++ }
++
++ if (unlikely(ret)) {
++ ddebug(1, "Setting key failed for %s-%zu.", alg_name, keylen*8);
++ ret = -EINVAL;
++ goto error;
++ }
++
++ out->stream = stream;
++ out->aead = aead;
++
++ out->async.result = kzalloc(sizeof(*out->async.result), GFP_KERNEL);
++ if (unlikely(!out->async.result)) {
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ init_completion(&out->async.result->completion);
++
++ if (aead == 0) {
++ out->async.request = ablkcipher_request_alloc(out->async.s, GFP_KERNEL);
++ if (unlikely(!out->async.request)) {
++ derr(1, "error allocating async crypto request");
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ ablkcipher_request_set_callback(out->async.request,
++ CRYPTO_TFM_REQ_MAY_BACKLOG,
++ cryptodev_complete, out->async.result);
++ } else {
++ out->async.arequest = aead_request_alloc(out->async.as, GFP_KERNEL);
++ if (unlikely(!out->async.arequest)) {
++ derr(1, "error allocating async crypto request");
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ aead_request_set_callback(out->async.arequest,
++ CRYPTO_TFM_REQ_MAY_BACKLOG,
++ cryptodev_complete, out->async.result);
++ }
++
++ out->init = 1;
++ return 0;
++error:
++ if (aead == 0) {
++ if (out->async.request)
++ ablkcipher_request_free(out->async.request);
++ if (out->async.s)
++ crypto_free_ablkcipher(out->async.s);
++ } else {
++ if (out->async.arequest)
++ aead_request_free(out->async.arequest);
++ if (out->async.as)
++ crypto_free_aead(out->async.as);
++ }
++ kfree(out->async.result);
++
++ return ret;
++}
++
++void cryptodev_cipher_deinit(struct cipher_data *cdata)
++{
++ if (cdata->init) {
++ if (cdata->aead == 0) {
++ if (cdata->async.request)
++ ablkcipher_request_free(cdata->async.request);
++ if (cdata->async.s)
++ crypto_free_ablkcipher(cdata->async.s);
++ } else {
++ if (cdata->async.arequest)
++ aead_request_free(cdata->async.arequest);
++ if (cdata->async.as)
++ crypto_free_aead(cdata->async.as);
++ }
++
++ kfree(cdata->async.result);
++ cdata->init = 0;
++ }
++}
++
++static inline int waitfor(struct cryptodev_result *cr, ssize_t ret)
++{
++ switch (ret) {
++ case 0:
++ break;
++ case -EINPROGRESS:
++ case -EBUSY:
++ wait_for_completion(&cr->completion);
++ /* At this point we known for sure the request has finished,
++ * because wait_for_completion above was not interruptible.
++ * This is important because otherwise hardware or driver
++ * might try to access memory which will be freed or reused for
++ * another request. */
++
++ if (unlikely(cr->err)) {
++ derr(0, "error from async request: %d", cr->err);
++ return cr->err;
++ }
++
++ break;
++ default:
++ return ret;
++ }
++
++ return 0;
++}
++
++ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata,
++ const struct scatterlist *src, struct scatterlist *dst,
++ size_t len)
++{
++ int ret;
++
++ reinit_completion(&cdata->async.result->completion);
++
++ if (cdata->aead == 0) {
++ ablkcipher_request_set_crypt(cdata->async.request,
++ (struct scatterlist *)src, dst,
++ len, cdata->async.iv);
++ ret = crypto_ablkcipher_encrypt(cdata->async.request);
++ } else {
++ aead_request_set_crypt(cdata->async.arequest,
++ (struct scatterlist *)src, dst,
++ len, cdata->async.iv);
++ ret = crypto_aead_encrypt(cdata->async.arequest);
++ }
++
++ return waitfor(cdata->async.result, ret);
++}
++
++ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata,
++ const struct scatterlist *src, struct scatterlist *dst,
++ size_t len)
++{
++ int ret;
++
++ reinit_completion(&cdata->async.result->completion);
++ if (cdata->aead == 0) {
++ ablkcipher_request_set_crypt(cdata->async.request,
++ (struct scatterlist *)src, dst,
++ len, cdata->async.iv);
++ ret = crypto_ablkcipher_decrypt(cdata->async.request);
++ } else {
++ aead_request_set_crypt(cdata->async.arequest,
++ (struct scatterlist *)src, dst,
++ len, cdata->async.iv);
++ ret = crypto_aead_decrypt(cdata->async.arequest);
++ }
++
++ return waitfor(cdata->async.result, ret);
++}
++
++/* Hash functions */
++
++int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name,
++ int hmac_mode, void *mackey, size_t mackeylen)
++{
++ int ret;
++
++ hdata->async.s = crypto_alloc_ahash(alg_name, 0, 0);
++ if (unlikely(IS_ERR(hdata->async.s))) {
++ ddebug(1, "Failed to load transform for %s", alg_name);
++ return -EINVAL;
++ }
++
++ /* Copy the key from user and set to TFM. */
++ if (hmac_mode != 0) {
++ ret = crypto_ahash_setkey(hdata->async.s, mackey, mackeylen);
++ if (unlikely(ret)) {
++ ddebug(1, "Setting hmac key failed for %s-%zu.",
++ alg_name, mackeylen*8);
++ ret = -EINVAL;
++ goto error;
++ }
++ }
++
++ hdata->digestsize = crypto_ahash_digestsize(hdata->async.s);
++ hdata->alignmask = crypto_ahash_alignmask(hdata->async.s);
++
++ hdata->async.result = kzalloc(sizeof(*hdata->async.result), GFP_KERNEL);
++ if (unlikely(!hdata->async.result)) {
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ init_completion(&hdata->async.result->completion);
++
++ hdata->async.request = ahash_request_alloc(hdata->async.s, GFP_KERNEL);
++ if (unlikely(!hdata->async.request)) {
++ derr(0, "error allocating async crypto request");
++ ret = -ENOMEM;
++ goto error;
++ }
++
++ ahash_request_set_callback(hdata->async.request,
++ CRYPTO_TFM_REQ_MAY_BACKLOG,
++ cryptodev_complete, hdata->async.result);
++
++ ret = crypto_ahash_init(hdata->async.request);
++ if (unlikely(ret)) {
++ derr(0, "error in crypto_hash_init()");
++ goto error_request;
++ }
++
++ hdata->init = 1;
++ return 0;
++
++error_request:
++ ahash_request_free(hdata->async.request);
++error:
++ kfree(hdata->async.result);
++ crypto_free_ahash(hdata->async.s);
++ return ret;
++}
++
++void cryptodev_hash_deinit(struct hash_data *hdata)
++{
++ if (hdata->init) {
++ if (hdata->async.request)
++ ahash_request_free(hdata->async.request);
++ kfree(hdata->async.result);
++ if (hdata->async.s)
++ crypto_free_ahash(hdata->async.s);
++ hdata->init = 0;
++ }
++}
++
++int cryptodev_hash_reset(struct hash_data *hdata)
++{
++ int ret;
++
++ ret = crypto_ahash_init(hdata->async.request);
++ if (unlikely(ret)) {
++ derr(0, "error in crypto_hash_init()");
++ return ret;
++ }
++
++ return 0;
++
++}
++
++ssize_t cryptodev_hash_update(struct hash_data *hdata,
++ struct scatterlist *sg, size_t len)
++{
++ int ret;
++
++ reinit_completion(&hdata->async.result->completion);
++ ahash_request_set_crypt(hdata->async.request, sg, NULL, len);
++
++ ret = crypto_ahash_update(hdata->async.request);
++
++ return waitfor(hdata->async.result, ret);
++}
++
++int cryptodev_hash_final(struct hash_data *hdata, void *output)
++{
++ int ret;
++
++ reinit_completion(&hdata->async.result->completion);
++ ahash_request_set_crypt(hdata->async.request, NULL, output, 0);
++
++ ret = crypto_ahash_final(hdata->async.request);
++
++ return waitfor(hdata->async.result, ret);
++}
++
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/cryptlib.h linux-3.14.72/crypto/cryptodev/cryptlib.h
+--- linux-3.14.72.orig/crypto/cryptodev/cryptlib.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/cryptlib.h 2016-06-19 22:11:55.065155743 +0200
+@@ -0,0 +1,93 @@
++#ifndef CRYPTLIB_H
++# define CRYPTLIB_H
++
++struct cipher_data {
++ int init; /* 0 uninitialized */
++ int blocksize;
++ int aead;
++ int stream;
++ int ivsize;
++ int alignmask;
++ struct {
++ /* block ciphers */
++ struct crypto_ablkcipher *s;
++ struct ablkcipher_request *request;
++
++ /* AEAD ciphers */
++ struct crypto_aead *as;
++ struct aead_request *arequest;
++
++ struct cryptodev_result *result;
++ uint8_t iv[EALG_MAX_BLOCK_LEN];
++ } async;
++};
++
++int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name,
++ uint8_t *key, size_t keylen, int stream, int aead);
++void cryptodev_cipher_deinit(struct cipher_data *cdata);
++int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead);
++int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop,
++ int aead);
++ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata,
++ const struct scatterlist *sg1,
++ struct scatterlist *sg2, size_t len);
++ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata,
++ const struct scatterlist *sg1,
++ struct scatterlist *sg2, size_t len);
++
++/* AEAD */
++static inline void cryptodev_cipher_auth(struct cipher_data *cdata,
++ struct scatterlist *sg1, size_t len)
++{
++ /* for some reason we _have_ to call that even for zero length sgs */
++ aead_request_set_assoc(cdata->async.arequest, len ? sg1 : NULL, len);
++}
++
++static inline void cryptodev_cipher_set_tag_size(struct cipher_data *cdata, int size)
++{
++ if (likely(cdata->aead != 0))
++ crypto_aead_setauthsize(cdata->async.as, size);
++}
++
++static inline int cryptodev_cipher_get_tag_size(struct cipher_data *cdata)
++{
++ if (likely(cdata->init && cdata->aead != 0))
++ return crypto_aead_authsize(cdata->async.as);
++ else
++ return 0;
++}
++
++static inline void cryptodev_cipher_set_iv(struct cipher_data *cdata,
++ void *iv, size_t iv_size)
++{
++ memcpy(cdata->async.iv, iv, min(iv_size, sizeof(cdata->async.iv)));
++}
++
++static inline void cryptodev_cipher_get_iv(struct cipher_data *cdata,
++ void *iv, size_t iv_size)
++{
++ memcpy(iv, cdata->async.iv, min(iv_size, sizeof(cdata->async.iv)));
++}
++
++/* Hash */
++struct hash_data {
++ int init; /* 0 uninitialized */
++ int digestsize;
++ int alignmask;
++ struct {
++ struct crypto_ahash *s;
++ struct cryptodev_result *result;
++ struct ahash_request *request;
++ } async;
++};
++
++int cryptodev_hash_final(struct hash_data *hdata, void *output);
++ssize_t cryptodev_hash_update(struct hash_data *hdata,
++ struct scatterlist *sg, size_t len);
++int cryptodev_hash_reset(struct hash_data *hdata);
++void cryptodev_hash_deinit(struct hash_data *hdata);
++int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name,
++ int hmac_mode, void *mackey, size_t mackeylen);
++
++
++#endif
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/cryptodev_int.h linux-3.14.72/crypto/cryptodev/cryptodev_int.h
+--- linux-3.14.72.orig/crypto/cryptodev/cryptodev_int.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/cryptodev_int.h 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,145 @@
++/* cipher stuff */
++#ifndef CRYPTODEV_INT_H
++# define CRYPTODEV_INT_H
++
++#include <linux/version.h>
++
++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0))
++# define reinit_completion(x) INIT_COMPLETION(*(x))
++#endif
++
++#include <linux/init.h>
++#include <linux/sched.h>
++#include <linux/fs.h>
++#include <linux/file.h>
++#include <linux/fdtable.h>
++#include <linux/miscdevice.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/scatterlist.h>
++#include <crypto/cryptodev.h>
++#include <crypto/aead.h>
++
++#define PFX "cryptodev: "
++#define dprintk(level, severity, format, a...) \
++ do { \
++ if (level <= cryptodev_verbosity) \
++ printk(severity PFX "%s[%u] (%s:%u): " format "\n", \
++ current->comm, current->pid, \
++ __func__, __LINE__, \
++ ##a); \
++ } while (0)
++#define derr(level, format, a...) dprintk(level, KERN_ERR, format, ##a)
++#define dwarning(level, format, a...) dprintk(level, KERN_WARNING, format, ##a)
++#define dinfo(level, format, a...) dprintk(level, KERN_INFO, format, ##a)
++#define ddebug(level, format, a...) dprintk(level, KERN_DEBUG, format, ##a)
++
++
++extern int cryptodev_verbosity;
++
++struct fcrypt {
++ struct list_head list;
++ struct mutex sem;
++};
++
++/* compatibility stuff */
++#ifdef CONFIG_COMPAT
++#include <linux/compat.h>
++
++/* input of CIOCGSESSION */
++struct compat_session_op {
++ /* Specify either cipher or mac
++ */
++ uint32_t cipher; /* cryptodev_crypto_op_t */
++ uint32_t mac; /* cryptodev_crypto_op_t */
++
++ uint32_t keylen;
++ compat_uptr_t key; /* pointer to key data */
++ uint32_t mackeylen;
++ compat_uptr_t mackey; /* pointer to mac key data */
++
++ uint32_t ses; /* session identifier */
++};
++
++/* input of CIOCCRYPT */
++struct compat_crypt_op {
++ uint32_t ses; /* session identifier */
++ uint16_t op; /* COP_ENCRYPT or COP_DECRYPT */
++ uint16_t flags; /* see COP_FLAG_* */
++ uint32_t len; /* length of source data */
++ compat_uptr_t src; /* source data */
++ compat_uptr_t dst; /* pointer to output data */
++ compat_uptr_t mac;/* pointer to output data for hash/MAC operations */
++ compat_uptr_t iv;/* initialization vector for encryption operations */
++};
++
++/* compat ioctls, defined for the above structs */
++#define COMPAT_CIOCGSESSION _IOWR('c', 102, struct compat_session_op)
++#define COMPAT_CIOCCRYPT _IOWR('c', 104, struct compat_crypt_op)
++#define COMPAT_CIOCASYNCCRYPT _IOW('c', 107, struct compat_crypt_op)
++#define COMPAT_CIOCASYNCFETCH _IOR('c', 108, struct compat_crypt_op)
++
++#endif /* CONFIG_COMPAT */
++
++/* kernel-internal extension to struct crypt_op */
++struct kernel_crypt_op {
++ struct crypt_op cop;
++
++ int ivlen;
++ __u8 iv[EALG_MAX_BLOCK_LEN];
++
++ int digestsize;
++ uint8_t hash_output[AALG_MAX_RESULT_LEN];
++
++ struct task_struct *task;
++ struct mm_struct *mm;
++};
++
++struct kernel_crypt_auth_op {
++ struct crypt_auth_op caop;
++
++ int dst_len; /* based on src_len + pad + tag */
++ int ivlen;
++ __u8 iv[EALG_MAX_BLOCK_LEN];
++
++ struct task_struct *task;
++ struct mm_struct *mm;
++};
++
++/* auth */
++
++int kcaop_from_user(struct kernel_crypt_auth_op *kcop,
++ struct fcrypt *fcr, void __user *arg);
++int kcaop_to_user(struct kernel_crypt_auth_op *kcaop,
++ struct fcrypt *fcr, void __user *arg);
++int crypto_auth_run(struct fcrypt *fcr, struct kernel_crypt_auth_op *kcaop);
++int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop);
++
++#include <cryptlib.h>
++
++/* other internal structs */
++struct csession {
++ struct list_head entry;
++ struct mutex sem;
++ struct cipher_data cdata;
++ struct hash_data hdata;
++ uint32_t sid;
++ uint32_t alignmask;
++
++ unsigned int array_size;
++ unsigned int used_pages; /* the number of pages that are used */
++ /* the number of pages marked as NOT-writable; they preceed writeables */
++ unsigned int readonly_pages;
++ struct page **pages;
++ struct scatterlist *sg;
++};
++
++struct csession *crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid);
++
++static inline void crypto_put_session(struct csession *ses_ptr)
++{
++ mutex_unlock(&ses_ptr->sem);
++}
++int adjust_sg_array(struct csession *ses, int pagecount);
++
++#endif /* CRYPTODEV_INT_H */
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/ioctl.c linux-3.14.72/crypto/cryptodev/ioctl.c
+--- linux-3.14.72.orig/crypto/cryptodev/ioctl.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/ioctl.c 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,1169 @@
++/*
++ * Driver for /dev/crypto device (aka CryptoDev)
++ *
++ * Copyright (c) 2004 Michal Ludvig <mludvig@logix.net.nz>, SuSE Labs
++ * Copyright (c) 2009,2010,2011 Nikos Mavrogiannopoulos <nmav@gnutls.org>
++ * Copyright (c) 2010 Phil Sutter
++ *
++ * This file is part of linux cryptodev.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++/*
++ * Device /dev/crypto provides an interface for
++ * accessing kernel CryptoAPI algorithms (ciphers,
++ * hashes) from userspace programs.
++ *
++ * /dev/crypto interface was originally introduced in
++ * OpenBSD and this module attempts to keep the API.
++ *
++ */
++
++#include <crypto/hash.h>
++#include <linux/crypto.h>
++#include <linux/mm.h>
++#include <linux/highmem.h>
++#include <linux/ioctl.h>
++#include <linux/random.h>
++#include <linux/syscalls.h>
++#include <linux/pagemap.h>
++#include <linux/poll.h>
++#include <linux/uaccess.h>
++#include <crypto/cryptodev.h>
++#include <linux/scatterlist.h>
++#include <linux/rtnetlink.h>
++#include <crypto/authenc.h>
++
++#include <linux/sysctl.h>
++
++#include "cryptodev_int.h"
++#include "zc.h"
++#include "version.h"
++
++MODULE_AUTHOR("Nikos Mavrogiannopoulos <nmav@gnutls.org>");
++MODULE_DESCRIPTION("CryptoDev driver");
++MODULE_LICENSE("GPL");
++
++/* ====== Compile-time config ====== */
++
++/* Default (pre-allocated) and maximum size of the job queue.
++ * These are free, pending and done items all together. */
++#define DEF_COP_RINGSIZE 16
++#define MAX_COP_RINGSIZE 64
++
++/* ====== Module parameters ====== */
++
++int cryptodev_verbosity;
++module_param(cryptodev_verbosity, int, 0644);
++MODULE_PARM_DESC(cryptodev_verbosity, "0: normal, 1: verbose, 2: debug");
++
++/* ====== CryptoAPI ====== */
++struct todo_list_item {
++ struct list_head __hook;
++ struct kernel_crypt_op kcop;
++ int result;
++};
++
++struct locked_list {
++ struct list_head list;
++ struct mutex lock;
++};
++
++struct crypt_priv {
++ struct fcrypt fcrypt;
++ struct locked_list free, todo, done;
++ int itemcount;
++ struct work_struct cryptask;
++ wait_queue_head_t user_waiter;
++};
++
++#define FILL_SG(sg, ptr, len) \
++ do { \
++ (sg)->page = virt_to_page(ptr); \
++ (sg)->offset = offset_in_page(ptr); \
++ (sg)->length = len; \
++ (sg)->dma_address = 0; \
++ } while (0)
++
++/* cryptodev's own workqueue, keeps crypto tasks from disturbing the force */
++static struct workqueue_struct *cryptodev_wq;
++
++/* Prepare session for future use. */
++static int
++crypto_create_session(struct fcrypt *fcr, struct session_op *sop)
++{
++ struct csession *ses_new = NULL, *ses_ptr;
++ int ret = 0;
++ const char *alg_name = NULL;
++ const char *hash_name = NULL;
++ int hmac_mode = 1, stream = 0, aead = 0;
++ /*
++ * With composite aead ciphers, only ckey is used and it can cover all the
++ * structure space; otherwise both keys may be used simultaneously but they
++ * are confined to their spaces
++ */
++ struct {
++ uint8_t ckey[CRYPTO_CIPHER_MAX_KEY_LEN];
++ uint8_t mkey[CRYPTO_HMAC_MAX_KEY_LEN];
++ /* padding space for aead keys */
++ uint8_t pad[RTA_SPACE(sizeof(struct crypto_authenc_key_param))];
++ } keys;
++
++ /* Does the request make sense? */
++ if (unlikely(!sop->cipher && !sop->mac)) {
++ ddebug(1, "Both 'cipher' and 'mac' unset.");
++ return -EINVAL;
++ }
++
++ switch (sop->cipher) {
++ case 0:
++ break;
++ case CRYPTO_DES_CBC:
++ alg_name = "cbc(des)";
++ break;
++ case CRYPTO_3DES_CBC:
++ alg_name = "cbc(des3_ede)";
++ break;
++ case CRYPTO_BLF_CBC:
++ alg_name = "cbc(blowfish)";
++ break;
++ case CRYPTO_AES_CBC:
++ alg_name = "cbc(aes)";
++ break;
++ case CRYPTO_AES_ECB:
++ alg_name = "ecb(aes)";
++ break;
++ case CRYPTO_CAMELLIA_CBC:
++ alg_name = "cbc(camellia)";
++ break;
++ case CRYPTO_AES_CTR:
++ alg_name = "ctr(aes)";
++ stream = 1;
++ break;
++ case CRYPTO_AES_GCM:
++ alg_name = "gcm(aes)";
++ stream = 1;
++ aead = 1;
++ break;
++ case CRYPTO_NULL:
++ alg_name = "ecb(cipher_null)";
++ stream = 1;
++ break;
++ default:
++ ddebug(1, "bad cipher: %d", sop->cipher);
++ return -EINVAL;
++ }
++
++ switch (sop->mac) {
++ case 0:
++ break;
++ case CRYPTO_MD5_HMAC:
++ hash_name = "hmac(md5)";
++ break;
++ case CRYPTO_RIPEMD160_HMAC:
++ hash_name = "hmac(rmd160)";
++ break;
++ case CRYPTO_SHA1_HMAC:
++ hash_name = "hmac(sha1)";
++ break;
++ case CRYPTO_SHA2_224_HMAC:
++ hash_name = "hmac(sha224)";
++ break;
++
++ case CRYPTO_SHA2_256_HMAC:
++ hash_name = "hmac(sha256)";
++ break;
++ case CRYPTO_SHA2_384_HMAC:
++ hash_name = "hmac(sha384)";
++ break;
++ case CRYPTO_SHA2_512_HMAC:
++ hash_name = "hmac(sha512)";
++ break;
++
++ /* non-hmac cases */
++ case CRYPTO_MD5:
++ hash_name = "md5";
++ hmac_mode = 0;
++ break;
++ case CRYPTO_RIPEMD160:
++ hash_name = "rmd160";
++ hmac_mode = 0;
++ break;
++ case CRYPTO_SHA1:
++ hash_name = "sha1";
++ hmac_mode = 0;
++ break;
++ case CRYPTO_SHA2_224:
++ hash_name = "sha224";
++ hmac_mode = 0;
++ break;
++ case CRYPTO_SHA2_256:
++ hash_name = "sha256";
++ hmac_mode = 0;
++ break;
++ case CRYPTO_SHA2_384:
++ hash_name = "sha384";
++ hmac_mode = 0;
++ break;
++ case CRYPTO_SHA2_512:
++ hash_name = "sha512";
++ hmac_mode = 0;
++ break;
++ default:
++ ddebug(1, "bad mac: %d", sop->mac);
++ return -EINVAL;
++ }
++
++ /* Create a session and put it to the list. */
++ ses_new = kzalloc(sizeof(*ses_new), GFP_KERNEL);
++ if (!ses_new)
++ return -ENOMEM;
++
++ /* Set-up crypto transform. */
++ if (alg_name) {
++ unsigned int keylen;
++ ret = cryptodev_get_cipher_keylen(&keylen, sop, aead);
++ if (unlikely(ret < 0)) {
++ ddebug(1, "Setting key failed for %s-%zu.",
++ alg_name, (size_t)sop->keylen*8);
++ goto error_cipher;
++ }
++
++ ret = cryptodev_get_cipher_key(keys.ckey, sop, aead);
++ if (unlikely(ret < 0))
++ goto error_cipher;
++
++ ret = cryptodev_cipher_init(&ses_new->cdata, alg_name, keys.ckey,
++ keylen, stream, aead);
++ if (ret < 0) {
++ ddebug(1, "Failed to load cipher for %s", alg_name);
++ ret = -EINVAL;
++ goto error_cipher;
++ }
++ }
++
++ if (hash_name && aead == 0) {
++ if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN)) {
++ ddebug(1, "Setting key failed for %s-%zu.",
++ hash_name, (size_t)sop->mackeylen*8);
++ ret = -EINVAL;
++ goto error_hash;
++ }
++
++ if (sop->mackey && unlikely(copy_from_user(keys.mkey, sop->mackey,
++ sop->mackeylen))) {
++ ret = -EFAULT;
++ goto error_hash;
++ }
++
++ ret = cryptodev_hash_init(&ses_new->hdata, hash_name, hmac_mode,
++ keys.mkey, sop->mackeylen);
++ if (ret != 0) {
++ ddebug(1, "Failed to load hash for %s", hash_name);
++ ret = -EINVAL;
++ goto error_hash;
++ }
++ }
++
++ ses_new->alignmask = max(ses_new->cdata.alignmask,
++ ses_new->hdata.alignmask);
++ ddebug(2, "got alignmask %d", ses_new->alignmask);
++
++ ses_new->array_size = DEFAULT_PREALLOC_PAGES;
++ ddebug(2, "preallocating for %d user pages", ses_new->array_size);
++ ses_new->pages = kzalloc(ses_new->array_size *
++ sizeof(struct page *), GFP_KERNEL);
++ ses_new->sg = kzalloc(ses_new->array_size *
++ sizeof(struct scatterlist), GFP_KERNEL);
++ if (ses_new->sg == NULL || ses_new->pages == NULL) {
++ ddebug(0, "Memory error");
++ ret = -ENOMEM;
++ goto error_hash;
++ }
++
++ /* put the new session to the list */
++ get_random_bytes(&ses_new->sid, sizeof(ses_new->sid));
++ mutex_init(&ses_new->sem);
++
++ mutex_lock(&fcr->sem);
++restart:
++ list_for_each_entry(ses_ptr, &fcr->list, entry) {
++ /* Check for duplicate SID */
++ if (unlikely(ses_new->sid == ses_ptr->sid)) {
++ get_random_bytes(&ses_new->sid, sizeof(ses_new->sid));
++ /* Unless we have a broken RNG this
++ shouldn't loop forever... ;-) */
++ goto restart;
++ }
++ }
++
++ list_add(&ses_new->entry, &fcr->list);
++ mutex_unlock(&fcr->sem);
++
++ /* Fill in some values for the user. */
++ sop->ses = ses_new->sid;
++
++ return 0;
++
++error_hash:
++ cryptodev_cipher_deinit(&ses_new->cdata);
++ kfree(ses_new->sg);
++ kfree(ses_new->pages);
++error_cipher:
++ kfree(ses_new);
++
++ return ret;
++
++}
++
++/* Everything that needs to be done when remowing a session. */
++static inline void
++crypto_destroy_session(struct csession *ses_ptr)
++{
++ if (!mutex_trylock(&ses_ptr->sem)) {
++ ddebug(2, "Waiting for semaphore of sid=0x%08X", ses_ptr->sid);
++ mutex_lock(&ses_ptr->sem);
++ }
++ ddebug(2, "Removed session 0x%08X", ses_ptr->sid);
++ cryptodev_cipher_deinit(&ses_ptr->cdata);
++ cryptodev_hash_deinit(&ses_ptr->hdata);
++ ddebug(2, "freeing space for %d user pages", ses_ptr->array_size);
++ kfree(ses_ptr->pages);
++ kfree(ses_ptr->sg);
++ mutex_unlock(&ses_ptr->sem);
++ mutex_destroy(&ses_ptr->sem);
++ kfree(ses_ptr);
++}
++
++/* Look up a session by ID and remove. */
++static int
++crypto_finish_session(struct fcrypt *fcr, uint32_t sid)
++{
++ struct csession *tmp, *ses_ptr;
++ struct list_head *head;
++ int ret = 0;
++
++ mutex_lock(&fcr->sem);
++ head = &fcr->list;
++ list_for_each_entry_safe(ses_ptr, tmp, head, entry) {
++ if (ses_ptr->sid == sid) {
++ list_del(&ses_ptr->entry);
++ crypto_destroy_session(ses_ptr);
++ break;
++ }
++ }
++
++ if (unlikely(!ses_ptr)) {
++ derr(1, "Session with sid=0x%08X not found!", sid);
++ ret = -ENOENT;
++ }
++ mutex_unlock(&fcr->sem);
++
++ return ret;
++}
++
++/* Remove all sessions when closing the file */
++static int
++crypto_finish_all_sessions(struct fcrypt *fcr)
++{
++ struct csession *tmp, *ses_ptr;
++ struct list_head *head;
++
++ mutex_lock(&fcr->sem);
++
++ head = &fcr->list;
++ list_for_each_entry_safe(ses_ptr, tmp, head, entry) {
++ list_del(&ses_ptr->entry);
++ crypto_destroy_session(ses_ptr);
++ }
++ mutex_unlock(&fcr->sem);
++
++ return 0;
++}
++
++/* Look up session by session ID. The returned session is locked. */
++struct csession *
++crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid)
++{
++ struct csession *ses_ptr, *retval = NULL;
++
++ if (unlikely(fcr == NULL))
++ return NULL;
++
++ mutex_lock(&fcr->sem);
++ list_for_each_entry(ses_ptr, &fcr->list, entry) {
++ if (ses_ptr->sid == sid) {
++ mutex_lock(&ses_ptr->sem);
++ retval = ses_ptr;
++ break;
++ }
++ }
++ mutex_unlock(&fcr->sem);
++
++ return retval;
++}
++
++static void cryptask_routine(struct work_struct *work)
++{
++ struct crypt_priv *pcr = container_of(work, struct crypt_priv, cryptask);
++ struct todo_list_item *item;
++ LIST_HEAD(tmp);
++
++ /* fetch all pending jobs into the temporary list */
++ mutex_lock(&pcr->todo.lock);
++ list_cut_position(&tmp, &pcr->todo.list, pcr->todo.list.prev);
++ mutex_unlock(&pcr->todo.lock);
++
++ /* handle each job locklessly */
++ list_for_each_entry(item, &tmp, __hook) {
++ item->result = crypto_run(&pcr->fcrypt, &item->kcop);
++ if (unlikely(item->result))
++ derr(0, "crypto_run() failed: %d", item->result);
++ }
++
++ /* push all handled jobs to the done list at once */
++ mutex_lock(&pcr->done.lock);
++ list_splice_tail(&tmp, &pcr->done.list);
++ mutex_unlock(&pcr->done.lock);
++
++ /* wake for POLLIN */
++ wake_up_interruptible(&pcr->user_waiter);
++}
++
++/* ====== /dev/crypto ====== */
++
++static int
++cryptodev_open(struct inode *inode, struct file *filp)
++{
++ struct todo_list_item *tmp, *tmp_next;
++ struct crypt_priv *pcr;
++ int i;
++
++ pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
++ if (!pcr)
++ return -ENOMEM;
++ filp->private_data = pcr;
++
++ mutex_init(&pcr->fcrypt.sem);
++ mutex_init(&pcr->free.lock);
++ mutex_init(&pcr->todo.lock);
++ mutex_init(&pcr->done.lock);
++
++ INIT_LIST_HEAD(&pcr->fcrypt.list);
++ INIT_LIST_HEAD(&pcr->free.list);
++ INIT_LIST_HEAD(&pcr->todo.list);
++ INIT_LIST_HEAD(&pcr->done.list);
++
++ INIT_WORK(&pcr->cryptask, cryptask_routine);
++
++ init_waitqueue_head(&pcr->user_waiter);
++
++ for (i = 0; i < DEF_COP_RINGSIZE; i++) {
++ tmp = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL);
++ if (!tmp)
++ goto err_ringalloc;
++ pcr->itemcount++;
++ ddebug(2, "allocated new item at %p", tmp);
++ list_add(&tmp->__hook, &pcr->free.list);
++ }
++
++ ddebug(2, "Cryptodev handle initialised, %d elements in queue",
++ DEF_COP_RINGSIZE);
++ return 0;
++
++/* In case of errors, free any memory allocated so far */
++err_ringalloc:
++ list_for_each_entry_safe(tmp, tmp_next, &pcr->free.list, __hook) {
++ list_del(&tmp->__hook);
++ kfree(tmp);
++ }
++ mutex_destroy(&pcr->done.lock);
++ mutex_destroy(&pcr->todo.lock);
++ mutex_destroy(&pcr->free.lock);
++ mutex_destroy(&pcr->fcrypt.sem);
++ kfree(pcr);
++ filp->private_data = NULL;
++ return -ENOMEM;
++}
++
++static int
++cryptodev_release(struct inode *inode, struct file *filp)
++{
++ struct crypt_priv *pcr = filp->private_data;
++ struct todo_list_item *item, *item_safe;
++ int items_freed = 0;
++
++ if (!pcr)
++ return 0;
++
++ cancel_work_sync(&pcr->cryptask);
++
++ list_splice_tail(&pcr->todo.list, &pcr->free.list);
++ list_splice_tail(&pcr->done.list, &pcr->free.list);
++
++ list_for_each_entry_safe(item, item_safe, &pcr->free.list, __hook) {
++ ddebug(2, "freeing item at %p", item);
++ list_del(&item->__hook);
++ kfree(item);
++ items_freed++;
++ }
++
++ if (items_freed != pcr->itemcount) {
++ derr(0, "freed %d items, but %d should exist!",
++ items_freed, pcr->itemcount);
++ }
++
++ crypto_finish_all_sessions(&pcr->fcrypt);
++
++ mutex_destroy(&pcr->done.lock);
++ mutex_destroy(&pcr->todo.lock);
++ mutex_destroy(&pcr->free.lock);
++ mutex_destroy(&pcr->fcrypt.sem);
++
++ kfree(pcr);
++ filp->private_data = NULL;
++
++ ddebug(2, "Cryptodev handle deinitialised, %d elements freed",
++ items_freed);
++ return 0;
++}
++
++static int
++clonefd(struct file *filp)
++{
++ int ret;
++ ret = get_unused_fd_flags(0);
++ if (ret >= 0) {
++ get_file(filp);
++ fd_install(ret, filp);
++ }
++
++ return ret;
++}
++
++#ifdef ENABLE_ASYNC
++/* enqueue a job for asynchronous completion
++ *
++ * returns:
++ * -EBUSY when there are no free queue slots left
++ * (and the number of slots has reached it MAX_COP_RINGSIZE)
++ * -EFAULT when there was a memory allocation error
++ * 0 on success */
++static int crypto_async_run(struct crypt_priv *pcr, struct kernel_crypt_op *kcop)
++{
++ struct todo_list_item *item = NULL;
++
++ if (unlikely(kcop->cop.flags & COP_FLAG_NO_ZC))
++ return -EINVAL;
++
++ mutex_lock(&pcr->free.lock);
++ if (likely(!list_empty(&pcr->free.list))) {
++ item = list_first_entry(&pcr->free.list,
++ struct todo_list_item, __hook);
++ list_del(&item->__hook);
++ } else if (pcr->itemcount < MAX_COP_RINGSIZE) {
++ pcr->itemcount++;
++ } else {
++ mutex_unlock(&pcr->free.lock);
++ return -EBUSY;
++ }
++ mutex_unlock(&pcr->free.lock);
++
++ if (unlikely(!item)) {
++ item = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL);
++ if (unlikely(!item))
++ return -EFAULT;
++ dinfo(1, "increased item count to %d", pcr->itemcount);
++ }
++
++ memcpy(&item->kcop, kcop, sizeof(struct kernel_crypt_op));
++
++ mutex_lock(&pcr->todo.lock);
++ list_add_tail(&item->__hook, &pcr->todo.list);
++ mutex_unlock(&pcr->todo.lock);
++
++ queue_work(cryptodev_wq, &pcr->cryptask);
++ return 0;
++}
++
++/* get the first completed job from the "done" queue
++ *
++ * returns:
++ * -EBUSY if no completed jobs are ready (yet)
++ * the return value of crypto_run() otherwise */
++static int crypto_async_fetch(struct crypt_priv *pcr,
++ struct kernel_crypt_op *kcop)
++{
++ struct todo_list_item *item;
++ int retval;
++
++ mutex_lock(&pcr->done.lock);
++ if (list_empty(&pcr->done.list)) {
++ mutex_unlock(&pcr->done.lock);
++ return -EBUSY;
++ }
++ item = list_first_entry(&pcr->done.list, struct todo_list_item, __hook);
++ list_del(&item->__hook);
++ mutex_unlock(&pcr->done.lock);
++
++ memcpy(kcop, &item->kcop, sizeof(struct kernel_crypt_op));
++ retval = item->result;
++
++ mutex_lock(&pcr->free.lock);
++ list_add_tail(&item->__hook, &pcr->free.list);
++ mutex_unlock(&pcr->free.lock);
++
++ /* wake for POLLOUT */
++ wake_up_interruptible(&pcr->user_waiter);
++
++ return retval;
++}
++#endif
++
++/* this function has to be called from process context */
++static int fill_kcop_from_cop(struct kernel_crypt_op *kcop, struct fcrypt *fcr)
++{
++ struct crypt_op *cop = &kcop->cop;
++ struct csession *ses_ptr;
++ int rc;
++
++ /* this also enters ses_ptr->sem */
++ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses);
++ if (unlikely(!ses_ptr)) {
++ derr(1, "invalid session ID=0x%08X", cop->ses);
++ return -EINVAL;
++ }
++ kcop->ivlen = cop->iv ? ses_ptr->cdata.ivsize : 0;
++ kcop->digestsize = 0; /* will be updated during operation */
++
++ crypto_put_session(ses_ptr);
++
++ kcop->task = current;
++ kcop->mm = current->mm;
++
++ if (cop->iv) {
++ rc = copy_from_user(kcop->iv, cop->iv, kcop->ivlen);
++ if (unlikely(rc)) {
++ derr(1, "error copying IV (%d bytes), copy_from_user returned %d for address %p",
++ kcop->ivlen, rc, cop->iv);
++ return -EFAULT;
++ }
++ }
++
++ return 0;
++}
++
++/* this function has to be called from process context */
++static int fill_cop_from_kcop(struct kernel_crypt_op *kcop, struct fcrypt *fcr)
++{
++ int ret;
++
++ if (kcop->digestsize) {
++ ret = copy_to_user(kcop->cop.mac,
++ kcop->hash_output, kcop->digestsize);
++ if (unlikely(ret))
++ return -EFAULT;
++ }
++ if (kcop->ivlen && kcop->cop.flags & COP_FLAG_WRITE_IV) {
++ ret = copy_to_user(kcop->cop.iv,
++ kcop->iv, kcop->ivlen);
++ if (unlikely(ret))
++ return -EFAULT;
++ }
++ return 0;
++}
++
++static int kcop_from_user(struct kernel_crypt_op *kcop,
++ struct fcrypt *fcr, void __user *arg)
++{
++ if (unlikely(copy_from_user(&kcop->cop, arg, sizeof(kcop->cop))))
++ return -EFAULT;
++
++ return fill_kcop_from_cop(kcop, fcr);
++}
++
++static int kcop_to_user(struct kernel_crypt_op *kcop,
++ struct fcrypt *fcr, void __user *arg)
++{
++ int ret;
++
++ ret = fill_cop_from_kcop(kcop, fcr);
++ if (unlikely(ret)) {
++ derr(1, "Error in fill_cop_from_kcop");
++ return ret;
++ }
++
++ if (unlikely(copy_to_user(arg, &kcop->cop, sizeof(kcop->cop)))) {
++ derr(1, "Cannot copy to userspace");
++ return -EFAULT;
++ }
++ return 0;
++}
++
++static inline void tfm_info_to_alg_info(struct alg_info *dst, struct crypto_tfm *tfm)
++{
++ snprintf(dst->cra_name, CRYPTODEV_MAX_ALG_NAME,
++ "%s", crypto_tfm_alg_name(tfm));
++ snprintf(dst->cra_driver_name, CRYPTODEV_MAX_ALG_NAME,
++ "%s", crypto_tfm_alg_driver_name(tfm));
++}
++
++#ifndef CRYPTO_ALG_KERN_DRIVER_ONLY
++static unsigned int is_known_accelerated(struct crypto_tfm *tfm)
++{
++ const char *name = crypto_tfm_alg_driver_name(tfm);
++
++ if (name == NULL)
++ return 1; /* assume accelerated */
++
++ /* look for known crypto engine names */
++ if (strstr(name, "-talitos") ||
++ !strncmp(name, "mv-", 3) ||
++ !strncmp(name, "atmel-", 6) ||
++ strstr(name, "geode") ||
++ strstr(name, "hifn") ||
++ strstr(name, "-ixp4xx") ||
++ strstr(name, "-omap") ||
++ strstr(name, "-picoxcell") ||
++ strstr(name, "-s5p") ||
++ strstr(name, "-ppc4xx") ||
++ strstr(name, "-caam") ||
++ strstr(name, "-n2"))
++ return 1;
++
++ return 0;
++}
++#endif
++
++static int get_session_info(struct fcrypt *fcr, struct session_info_op *siop)
++{
++ struct csession *ses_ptr;
++ struct crypto_tfm *tfm;
++
++ /* this also enters ses_ptr->sem */
++ ses_ptr = crypto_get_session_by_sid(fcr, siop->ses);
++ if (unlikely(!ses_ptr)) {
++ derr(1, "invalid session ID=0x%08X", siop->ses);
++ return -EINVAL;
++ }
++
++ siop->flags = 0;
++
++ if (ses_ptr->cdata.init) {
++ if (ses_ptr->cdata.aead == 0)
++ tfm = crypto_ablkcipher_tfm(ses_ptr->cdata.async.s);
++ else
++ tfm = crypto_aead_tfm(ses_ptr->cdata.async.as);
++ tfm_info_to_alg_info(&siop->cipher_info, tfm);
++#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY
++ if (tfm->__crt_alg->cra_flags & CRYPTO_ALG_KERN_DRIVER_ONLY)
++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY;
++#else
++ if (is_known_accelerated(tfm))
++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY;
++#endif
++ }
++ if (ses_ptr->hdata.init) {
++ tfm = crypto_ahash_tfm(ses_ptr->hdata.async.s);
++ tfm_info_to_alg_info(&siop->hash_info, tfm);
++#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY
++ if (tfm->__crt_alg->cra_flags & CRYPTO_ALG_KERN_DRIVER_ONLY)
++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY;
++#else
++ if (is_known_accelerated(tfm))
++ siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY;
++#endif
++ }
++
++ siop->alignmask = ses_ptr->alignmask;
++
++ crypto_put_session(ses_ptr);
++ return 0;
++}
++
++static long
++cryptodev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg_)
++{
++ void __user *arg = (void __user *)arg_;
++ int __user *p = arg;
++ struct session_op sop;
++ struct kernel_crypt_op kcop;
++ struct kernel_crypt_auth_op kcaop;
++ struct crypt_priv *pcr = filp->private_data;
++ struct fcrypt *fcr;
++ struct session_info_op siop;
++ uint32_t ses;
++ int ret, fd;
++
++ if (unlikely(!pcr))
++ BUG();
++
++ fcr = &pcr->fcrypt;
++
++ switch (cmd) {
++ case CIOCASYMFEAT:
++ return put_user(0, p);
++ case CRIOGET:
++ fd = clonefd(filp);
++ ret = put_user(fd, p);
++ if (unlikely(ret)) {
++ sys_close(fd);
++ return ret;
++ }
++ return ret;
++ case CIOCGSESSION:
++ if (unlikely(copy_from_user(&sop, arg, sizeof(sop))))
++ return -EFAULT;
++
++ ret = crypto_create_session(fcr, &sop);
++ if (unlikely(ret))
++ return ret;
++ ret = copy_to_user(arg, &sop, sizeof(sop));
++ if (unlikely(ret)) {
++ crypto_finish_session(fcr, sop.ses);
++ return -EFAULT;
++ }
++ return ret;
++ case CIOCFSESSION:
++ ret = get_user(ses, (uint32_t __user *)arg);
++ if (unlikely(ret))
++ return ret;
++ ret = crypto_finish_session(fcr, ses);
++ return ret;
++ case CIOCGSESSINFO:
++ if (unlikely(copy_from_user(&siop, arg, sizeof(siop))))
++ return -EFAULT;
++
++ ret = get_session_info(fcr, &siop);
++ if (unlikely(ret))
++ return ret;
++ return copy_to_user(arg, &siop, sizeof(siop));
++ case CIOCCRYPT:
++ if (unlikely(ret = kcop_from_user(&kcop, fcr, arg))) {
++ dwarning(1, "Error copying from user");
++ return ret;
++ }
++
++ ret = crypto_run(fcr, &kcop);
++ if (unlikely(ret)) {
++ dwarning(1, "Error in crypto_run");
++ return ret;
++ }
++
++ return kcop_to_user(&kcop, fcr, arg);
++ case CIOCAUTHCRYPT:
++ if (unlikely(ret = kcaop_from_user(&kcaop, fcr, arg))) {
++ dwarning(1, "Error copying from user");
++ return ret;
++ }
++
++ ret = crypto_auth_run(fcr, &kcaop);
++ if (unlikely(ret)) {
++ dwarning(1, "Error in crypto_auth_run");
++ return ret;
++ }
++ return kcaop_to_user(&kcaop, fcr, arg);
++#ifdef ENABLE_ASYNC
++ case CIOCASYNCCRYPT:
++ if (unlikely(ret = kcop_from_user(&kcop, fcr, arg)))
++ return ret;
++
++ return crypto_async_run(pcr, &kcop);
++ case CIOCASYNCFETCH:
++ ret = crypto_async_fetch(pcr, &kcop);
++ if (unlikely(ret))
++ return ret;
++
++ return kcop_to_user(&kcop, fcr, arg);
++#endif
++ default:
++ return -EINVAL;
++ }
++}
++
++/* compatibility code for 32bit userlands */
++#ifdef CONFIG_COMPAT
++
++static inline void
++compat_to_session_op(struct compat_session_op *compat, struct session_op *sop)
++{
++ sop->cipher = compat->cipher;
++ sop->mac = compat->mac;
++ sop->keylen = compat->keylen;
++
++ sop->key = compat_ptr(compat->key);
++ sop->mackeylen = compat->mackeylen;
++ sop->mackey = compat_ptr(compat->mackey);
++ sop->ses = compat->ses;
++}
++
++static inline void
++session_op_to_compat(struct session_op *sop, struct compat_session_op *compat)
++{
++ compat->cipher = sop->cipher;
++ compat->mac = sop->mac;
++ compat->keylen = sop->keylen;
++
++ compat->key = ptr_to_compat(sop->key);
++ compat->mackeylen = sop->mackeylen;
++ compat->mackey = ptr_to_compat(sop->mackey);
++ compat->ses = sop->ses;
++}
++
++static inline void
++compat_to_crypt_op(struct compat_crypt_op *compat, struct crypt_op *cop)
++{
++ cop->ses = compat->ses;
++ cop->op = compat->op;
++ cop->flags = compat->flags;
++ cop->len = compat->len;
++
++ cop->src = compat_ptr(compat->src);
++ cop->dst = compat_ptr(compat->dst);
++ cop->mac = compat_ptr(compat->mac);
++ cop->iv = compat_ptr(compat->iv);
++}
++
++static inline void
++crypt_op_to_compat(struct crypt_op *cop, struct compat_crypt_op *compat)
++{
++ compat->ses = cop->ses;
++ compat->op = cop->op;
++ compat->flags = cop->flags;
++ compat->len = cop->len;
++
++ compat->src = ptr_to_compat(cop->src);
++ compat->dst = ptr_to_compat(cop->dst);
++ compat->mac = ptr_to_compat(cop->mac);
++ compat->iv = ptr_to_compat(cop->iv);
++}
++
++static int compat_kcop_from_user(struct kernel_crypt_op *kcop,
++ struct fcrypt *fcr, void __user *arg)
++{
++ struct compat_crypt_op compat_cop;
++
++ if (unlikely(copy_from_user(&compat_cop, arg, sizeof(compat_cop))))
++ return -EFAULT;
++ compat_to_crypt_op(&compat_cop, &kcop->cop);
++
++ return fill_kcop_from_cop(kcop, fcr);
++}
++
++static int compat_kcop_to_user(struct kernel_crypt_op *kcop,
++ struct fcrypt *fcr, void __user *arg)
++{
++ int ret;
++ struct compat_crypt_op compat_cop;
++
++ ret = fill_cop_from_kcop(kcop, fcr);
++ if (unlikely(ret)) {
++ dwarning(1, "Error in fill_cop_from_kcop");
++ return ret;
++ }
++ crypt_op_to_compat(&kcop->cop, &compat_cop);
++
++ if (unlikely(copy_to_user(arg, &compat_cop, sizeof(compat_cop)))) {
++ dwarning(1, "Error copying to user");
++ return -EFAULT;
++ }
++ return 0;
++}
++
++static long
++cryptodev_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg_)
++{
++ void __user *arg = (void __user *)arg_;
++ struct crypt_priv *pcr = file->private_data;
++ struct fcrypt *fcr;
++ struct session_op sop;
++ struct compat_session_op compat_sop;
++ struct kernel_crypt_op kcop;
++ int ret;
++
++ if (unlikely(!pcr))
++ BUG();
++
++ fcr = &pcr->fcrypt;
++
++ switch (cmd) {
++ case CIOCASYMFEAT:
++ case CRIOGET:
++ case CIOCFSESSION:
++ case CIOCGSESSINFO:
++ return cryptodev_ioctl(file, cmd, arg_);
++
++ case COMPAT_CIOCGSESSION:
++ if (unlikely(copy_from_user(&compat_sop, arg,
++ sizeof(compat_sop))))
++ return -EFAULT;
++ compat_to_session_op(&compat_sop, &sop);
++
++ ret = crypto_create_session(fcr, &sop);
++ if (unlikely(ret))
++ return ret;
++
++ session_op_to_compat(&sop, &compat_sop);
++ ret = copy_to_user(arg, &compat_sop, sizeof(compat_sop));
++ if (unlikely(ret)) {
++ crypto_finish_session(fcr, sop.ses);
++ return -EFAULT;
++ }
++ return ret;
++
++ case COMPAT_CIOCCRYPT:
++ ret = compat_kcop_from_user(&kcop, fcr, arg);
++ if (unlikely(ret))
++ return ret;
++
++ ret = crypto_run(fcr, &kcop);
++ if (unlikely(ret))
++ return ret;
++
++ return compat_kcop_to_user(&kcop, fcr, arg);
++#ifdef ENABLE_ASYNC
++ case COMPAT_CIOCASYNCCRYPT:
++ if (unlikely(ret = compat_kcop_from_user(&kcop, fcr, arg)))
++ return ret;
++
++ return crypto_async_run(pcr, &kcop);
++ case COMPAT_CIOCASYNCFETCH:
++ ret = crypto_async_fetch(pcr, &kcop);
++ if (unlikely(ret))
++ return ret;
++
++ return compat_kcop_to_user(&kcop, fcr, arg);
++#endif
++ default:
++ return -EINVAL;
++ }
++}
++
++#endif /* CONFIG_COMPAT */
++
++static unsigned int cryptodev_poll(struct file *file, poll_table *wait)
++{
++ struct crypt_priv *pcr = file->private_data;
++ int ret = 0;
++
++ poll_wait(file, &pcr->user_waiter, wait);
++
++ if (!list_empty_careful(&pcr->done.list))
++ ret |= POLLIN | POLLRDNORM;
++ if (!list_empty_careful(&pcr->free.list) || pcr->itemcount < MAX_COP_RINGSIZE)
++ ret |= POLLOUT | POLLWRNORM;
++
++ return ret;
++}
++
++static const struct file_operations cryptodev_fops = {
++ .owner = THIS_MODULE,
++ .open = cryptodev_open,
++ .release = cryptodev_release,
++ .unlocked_ioctl = cryptodev_ioctl,
++#ifdef CONFIG_COMPAT
++ .compat_ioctl = cryptodev_compat_ioctl,
++#endif /* CONFIG_COMPAT */
++ .poll = cryptodev_poll,
++};
++
++static struct miscdevice cryptodev = {
++ .minor = MISC_DYNAMIC_MINOR,
++ .name = "crypto",
++ .fops = &cryptodev_fops,
++ .mode = S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH,
++};
++
++static int __init
++cryptodev_register(void)
++{
++ int rc;
++
++ rc = misc_register(&cryptodev);
++ if (unlikely(rc)) {
++ pr_err(PFX "registration of /dev/crypto failed\n");
++ return rc;
++ }
++
++ return 0;
++}
++
++static void __exit
++cryptodev_deregister(void)
++{
++ misc_deregister(&cryptodev);
++}
++
++/* ====== Module init/exit ====== */
++static struct ctl_table verbosity_ctl_dir[] = {
++ {
++ .procname = "cryptodev_verbosity",
++ .data = &cryptodev_verbosity,
++ .maxlen = sizeof(int),
++ .mode = 0644,
++ .proc_handler = proc_dointvec,
++ },
++ {0, },
++};
++
++static struct ctl_table verbosity_ctl_root[] = {
++ {
++ .procname = "ioctl",
++ .mode = 0555,
++ .child = verbosity_ctl_dir,
++ },
++ {0, },
++};
++static struct ctl_table_header *verbosity_sysctl_header;
++static int __init init_cryptodev(void)
++{
++ int rc;
++
++ cryptodev_wq = create_workqueue("cryptodev_queue");
++ if (unlikely(!cryptodev_wq)) {
++ pr_err(PFX "failed to allocate the cryptodev workqueue\n");
++ return -EFAULT;
++ }
++
++ rc = cryptodev_register();
++ if (unlikely(rc)) {
++ destroy_workqueue(cryptodev_wq);
++ return rc;
++ }
++
++ verbosity_sysctl_header = register_sysctl_table(verbosity_ctl_root);
++
++ pr_info(PFX "driver %s loaded.\n", VERSION);
++
++ return 0;
++}
++
++static void __exit exit_cryptodev(void)
++{
++ flush_workqueue(cryptodev_wq);
++ destroy_workqueue(cryptodev_wq);
++
++ if (verbosity_sysctl_header)
++ unregister_sysctl_table(verbosity_sysctl_header);
++
++ cryptodev_deregister();
++ pr_info(PFX "driver unloaded.\n");
++}
++
++module_init(init_cryptodev);
++module_exit(exit_cryptodev);
++
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/main.c linux-3.14.72/crypto/cryptodev/main.c
+--- linux-3.14.72.orig/crypto/cryptodev/main.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/main.c 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,267 @@
++/*
++ * Driver for /dev/crypto device (aka CryptoDev)
++ *
++ * Copyright (c) 2004 Michal Ludvig <mludvig@logix.net.nz>, SuSE Labs
++ * Copyright (c) 2009-2013 Nikos Mavrogiannopoulos <nmav@gnutls.org>
++ *
++ * This file is part of linux cryptodev.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++/*
++ * Device /dev/crypto provides an interface for
++ * accessing kernel CryptoAPI algorithms (ciphers,
++ * hashes) from userspace programs.
++ *
++ * /dev/crypto interface was originally introduced in
++ * OpenBSD and this module attempts to keep the API.
++ *
++ */
++#include <crypto/hash.h>
++#include <linux/crypto.h>
++#include <linux/mm.h>
++#include <linux/highmem.h>
++#include <linux/ioctl.h>
++#include <linux/random.h>
++#include <linux/syscalls.h>
++#include <linux/pagemap.h>
++#include <linux/poll.h>
++#include <linux/uaccess.h>
++#include <crypto/cryptodev.h>
++#include <crypto/scatterwalk.h>
++#include <linux/scatterlist.h>
++#include "cryptodev_int.h"
++#include "zc.h"
++#include "cryptlib.h"
++#include "version.h"
++
++/* This file contains the traditional operations of encryption
++ * and hashing of /dev/crypto.
++ */
++
++static int
++hash_n_crypt(struct csession *ses_ptr, struct crypt_op *cop,
++ struct scatterlist *src_sg, struct scatterlist *dst_sg,
++ uint32_t len)
++{
++ int ret;
++
++ /* Always hash before encryption and after decryption. Maybe
++ * we should introduce a flag to switch... TBD later on.
++ */
++ if (cop->op == COP_ENCRYPT) {
++ if (ses_ptr->hdata.init != 0) {
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ src_sg, len);
++ if (unlikely(ret))
++ goto out_err;
++ }
++ if (ses_ptr->cdata.init != 0) {
++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata,
++ src_sg, dst_sg, len);
++
++ if (unlikely(ret))
++ goto out_err;
++ }
++ } else {
++ if (ses_ptr->cdata.init != 0) {
++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata,
++ src_sg, dst_sg, len);
++
++ if (unlikely(ret))
++ goto out_err;
++ }
++
++ if (ses_ptr->hdata.init != 0) {
++ ret = cryptodev_hash_update(&ses_ptr->hdata,
++ dst_sg, len);
++ if (unlikely(ret))
++ goto out_err;
++ }
++ }
++ return 0;
++out_err:
++ derr(0, "CryptoAPI failure: %d", ret);
++ return ret;
++}
++
++/* This is the main crypto function - feed it with plaintext
++ and get a ciphertext (or vice versa :-) */
++static int
++__crypto_run_std(struct csession *ses_ptr, struct crypt_op *cop)
++{
++ char *data;
++ char __user *src, *dst;
++ struct scatterlist sg;
++ size_t nbytes, bufsize;
++ int ret = 0;
++
++ nbytes = cop->len;
++ data = (char *)__get_free_page(GFP_KERNEL);
++
++ if (unlikely(!data)) {
++ derr(1, "Error getting free page.");
++ return -ENOMEM;
++ }
++
++ bufsize = PAGE_SIZE < nbytes ? PAGE_SIZE : nbytes;
++
++ src = cop->src;
++ dst = cop->dst;
++
++ while (nbytes > 0) {
++ size_t current_len = nbytes > bufsize ? bufsize : nbytes;
++
++ if (unlikely(copy_from_user(data, src, current_len))) {
++ derr(1, "Error copying %zu bytes from user address %p.", current_len, src);
++ ret = -EFAULT;
++ break;
++ }
++
++ sg_init_one(&sg, data, current_len);
++
++ ret = hash_n_crypt(ses_ptr, cop, &sg, &sg, current_len);
++
++ if (unlikely(ret)) {
++ derr(1, "hash_n_crypt failed.");
++ break;
++ }
++
++ if (ses_ptr->cdata.init != 0) {
++ if (unlikely(copy_to_user(dst, data, current_len))) {
++ derr(1, "could not copy to user.");
++ ret = -EFAULT;
++ break;
++ }
++ }
++
++ dst += current_len;
++ nbytes -= current_len;
++ src += current_len;
++ }
++
++ free_page((unsigned long)data);
++ return ret;
++}
++
++
++
++/* This is the main crypto function - zero-copy edition */
++static int
++__crypto_run_zc(struct csession *ses_ptr, struct kernel_crypt_op *kcop)
++{
++ struct scatterlist *src_sg, *dst_sg;
++ struct crypt_op *cop = &kcop->cop;
++ int ret = 0;
++
++ ret = get_userbuf(ses_ptr, cop->src, cop->len, cop->dst, cop->len,
++ kcop->task, kcop->mm, &src_sg, &dst_sg);
++ if (unlikely(ret)) {
++ derr(1, "Error getting user pages. Falling back to non zero copy.");
++ return __crypto_run_std(ses_ptr, cop);
++ }
++
++ ret = hash_n_crypt(ses_ptr, cop, src_sg, dst_sg, cop->len);
++
++ release_user_pages(ses_ptr);
++ return ret;
++}
++
++int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop)
++{
++ struct csession *ses_ptr;
++ struct crypt_op *cop = &kcop->cop;
++ int ret;
++
++ if (unlikely(cop->op != COP_ENCRYPT && cop->op != COP_DECRYPT)) {
++ ddebug(1, "invalid operation op=%u", cop->op);
++ return -EINVAL;
++ }
++
++ /* this also enters ses_ptr->sem */
++ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses);
++ if (unlikely(!ses_ptr)) {
++ derr(1, "invalid session ID=0x%08X", cop->ses);
++ return -EINVAL;
++ }
++
++ if (ses_ptr->hdata.init != 0 && (cop->flags == 0 || cop->flags & COP_FLAG_RESET)) {
++ ret = cryptodev_hash_reset(&ses_ptr->hdata);
++ if (unlikely(ret)) {
++ derr(1, "error in cryptodev_hash_reset()");
++ goto out_unlock;
++ }
++ }
++
++ if (ses_ptr->cdata.init != 0) {
++ int blocksize = ses_ptr->cdata.blocksize;
++
++ if (unlikely(cop->len % blocksize)) {
++ derr(1, "data size (%u) isn't a multiple of block size (%u)",
++ cop->len, blocksize);
++ ret = -EINVAL;
++ goto out_unlock;
++ }
++
++ cryptodev_cipher_set_iv(&ses_ptr->cdata, kcop->iv,
++ min(ses_ptr->cdata.ivsize, kcop->ivlen));
++ }
++
++ if (likely(cop->len)) {
++ if (cop->flags & COP_FLAG_NO_ZC) {
++ if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->src, ses_ptr->alignmask))) {
++ dwarning(2, "source address %p is not %d byte aligned - disabling zero copy",
++ cop->src, ses_ptr->alignmask + 1);
++ cop->flags &= ~COP_FLAG_NO_ZC;
++ }
++
++ if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->dst, ses_ptr->alignmask))) {
++ dwarning(2, "destination address %p is not %d byte aligned - disabling zero copy",
++ cop->dst, ses_ptr->alignmask + 1);
++ cop->flags &= ~COP_FLAG_NO_ZC;
++ }
++ }
++
++ if (cop->flags & COP_FLAG_NO_ZC)
++ ret = __crypto_run_std(ses_ptr, &kcop->cop);
++ else
++ ret = __crypto_run_zc(ses_ptr, kcop);
++ if (unlikely(ret))
++ goto out_unlock;
++ }
++
++ if (ses_ptr->cdata.init != 0) {
++ cryptodev_cipher_get_iv(&ses_ptr->cdata, kcop->iv,
++ min(ses_ptr->cdata.ivsize, kcop->ivlen));
++ }
++
++ if (ses_ptr->hdata.init != 0 &&
++ ((cop->flags & COP_FLAG_FINAL) ||
++ (!(cop->flags & COP_FLAG_UPDATE) || cop->len == 0))) {
++
++ ret = cryptodev_hash_final(&ses_ptr->hdata, kcop->hash_output);
++ if (unlikely(ret)) {
++ derr(0, "CryptoAPI failure: %d", ret);
++ goto out_unlock;
++ }
++ kcop->digestsize = ses_ptr->hdata.digestsize;
++ }
++
++out_unlock:
++ crypto_put_session(ses_ptr);
++ return ret;
++}
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/Makefile linux-3.14.72/crypto/cryptodev/Makefile
+--- linux-3.14.72.orig/crypto/cryptodev/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/Makefile 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,8 @@
++ccflags-y := -Icrypto/cryptodev -Iinclude/uapi/linux/
++obj-$(CONFIG_CRYPTO_CRYPTODEV) += cryptodev.o
++cryptodev-objs := ioctl.o \
++ main.o \
++ cryptlib.o \
++ authenc.o \
++ zc.o \
++ util.o
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/util.c linux-3.14.72/crypto/cryptodev/util.c
+--- linux-3.14.72.orig/crypto/cryptodev/util.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/util.c 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (c) 2011 Maxim Levitsky
++ *
++ * This file is part of linux cryptodev.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++#include <crypto/scatterwalk.h>
++#include <linux/scatterlist.h>
++#include "util.h"
++
++/* These were taken from Maxim Levitsky's patch to lkml.
++ */
++struct scatterlist *sg_advance(struct scatterlist *sg, int consumed)
++{
++ while (consumed >= sg->length) {
++ consumed -= sg->length;
++
++ sg = sg_next(sg);
++ if (!sg)
++ break;
++ }
++
++ WARN_ON(!sg && consumed);
++
++ if (!sg)
++ return NULL;
++
++ sg->offset += consumed;
++ sg->length -= consumed;
++
++ if (sg->offset >= PAGE_SIZE) {
++ struct page *page =
++ nth_page(sg_page(sg), sg->offset / PAGE_SIZE);
++ sg_set_page(sg, page, sg->length, sg->offset % PAGE_SIZE);
++ }
++
++ return sg;
++}
++
++/**
++ * sg_copy - copies sg entries from sg_from to sg_to, such
++ * as sg_to covers first 'len' bytes from sg_from.
++ */
++int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len)
++{
++ while (len > sg_from->length) {
++ len -= sg_from->length;
++
++ sg_set_page(sg_to, sg_page(sg_from),
++ sg_from->length, sg_from->offset);
++
++ sg_to = sg_next(sg_to);
++ sg_from = sg_next(sg_from);
++
++ if (len && (!sg_from || !sg_to))
++ return -ENOMEM;
++ }
++
++ if (len)
++ sg_set_page(sg_to, sg_page(sg_from),
++ len, sg_from->offset);
++ sg_mark_end(sg_to);
++ return 0;
++}
++
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/util.h linux-3.14.72/crypto/cryptodev/util.h
+--- linux-3.14.72.orig/crypto/cryptodev/util.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/util.h 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,2 @@
++int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len);
++struct scatterlist *sg_advance(struct scatterlist *sg, int consumed);
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/version.h linux-3.14.72/crypto/cryptodev/version.h
+--- linux-3.14.72.orig/crypto/cryptodev/version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/version.h 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1 @@
++#define VERSION "1.7"
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/zc.c linux-3.14.72/crypto/cryptodev/zc.c
+--- linux-3.14.72.orig/crypto/cryptodev/zc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/zc.c 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,208 @@
++/*
++ * Driver for /dev/crypto device (aka CryptoDev)
++ *
++ * Copyright (c) 2009-2013 Nikos Mavrogiannopoulos <nmav@gnutls.org>
++ * Copyright (c) 2010 Phil Sutter
++ * Copyright (c) 2011, 2012 OpenSSL Software Foundation, Inc.
++ *
++ * This file is part of linux cryptodev.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
++ * 02110-1301, USA.
++ */
++
++#include <crypto/hash.h>
++#include <linux/crypto.h>
++#include <linux/mm.h>
++#include <linux/highmem.h>
++#include <linux/ioctl.h>
++#include <linux/random.h>
++#include <linux/syscalls.h>
++#include <linux/pagemap.h>
++#include <linux/uaccess.h>
++#include <crypto/scatterwalk.h>
++#include <linux/scatterlist.h>
++#include "cryptodev_int.h"
++#include "zc.h"
++#include "version.h"
++
++/* Helper functions to assist zero copy.
++ * This needs to be redesigned and moved out of the session. --nmav
++ */
++
++/* offset of buf in it's first page */
++#define PAGEOFFSET(buf) ((unsigned long)buf & ~PAGE_MASK)
++
++/* fetch the pages addr resides in into pg and initialise sg with them */
++int __get_userbuf(uint8_t __user *addr, uint32_t len, int write,
++ unsigned int pgcount, struct page **pg, struct scatterlist *sg,
++ struct task_struct *task, struct mm_struct *mm)
++{
++ int ret, pglen, i = 0;
++ struct scatterlist *sgp;
++
++ if (unlikely(!pgcount || !len || !addr)) {
++ sg_mark_end(sg);
++ return 0;
++ }
++
++ down_read(&mm->mmap_sem);
++ ret = get_user_pages(task, mm,
++ (unsigned long)addr, pgcount, write, 0, pg, NULL);
++ up_read(&mm->mmap_sem);
++ if (ret != pgcount)
++ return -EINVAL;
++
++ sg_init_table(sg, pgcount);
++
++ pglen = min((ptrdiff_t)(PAGE_SIZE - PAGEOFFSET(addr)), (ptrdiff_t)len);
++ sg_set_page(sg, pg[i++], pglen, PAGEOFFSET(addr));
++
++ len -= pglen;
++ for (sgp = sg_next(sg); len; sgp = sg_next(sgp)) {
++ pglen = min((uint32_t)PAGE_SIZE, len);
++ sg_set_page(sgp, pg[i++], pglen, 0);
++ len -= pglen;
++ }
++ sg_mark_end(sg_last(sg, pgcount));
++ return 0;
++}
++
++int adjust_sg_array(struct csession *ses, int pagecount)
++{
++ struct scatterlist *sg;
++ struct page **pages;
++ int array_size;
++
++ for (array_size = ses->array_size; array_size < pagecount;
++ array_size *= 2)
++ ;
++ ddebug(0, "reallocating from %d to %d pages",
++ ses->array_size, array_size);
++ pages = krealloc(ses->pages, array_size * sizeof(struct page *),
++ GFP_KERNEL);
++ if (unlikely(!pages))
++ return -ENOMEM;
++ ses->pages = pages;
++ sg = krealloc(ses->sg, array_size * sizeof(struct scatterlist),
++ GFP_KERNEL);
++ if (unlikely(!sg))
++ return -ENOMEM;
++ ses->sg = sg;
++ ses->array_size = array_size;
++
++ return 0;
++}
++
++void release_user_pages(struct csession *ses)
++{
++ unsigned int i;
++
++ for (i = 0; i < ses->used_pages; i++) {
++ if (!PageReserved(ses->pages[i]))
++ SetPageDirty(ses->pages[i]);
++
++ if (ses->readonly_pages == 0)
++ flush_dcache_page(ses->pages[i]);
++ else
++ ses->readonly_pages--;
++
++ page_cache_release(ses->pages[i]);
++ }
++ ses->used_pages = 0;
++}
++
++/* make src and dst available in scatterlists.
++ * dst might be the same as src.
++ */
++int get_userbuf(struct csession *ses,
++ void *__user src, unsigned int src_len,
++ void *__user dst, unsigned int dst_len,
++ struct task_struct *task, struct mm_struct *mm,
++ struct scatterlist **src_sg,
++ struct scatterlist **dst_sg)
++{
++ int src_pagecount, dst_pagecount;
++ int rc;
++
++ /* Empty input is a valid option to many algorithms & is tested by NIST/FIPS */
++ /* Make sure NULL input has 0 length */
++ if (!src && src_len)
++ src_len = 0;
++
++ /* I don't know that null output is ever useful, but we can handle it gracefully */
++ /* Make sure NULL output has 0 length */
++ if (!dst && dst_len)
++ dst_len = 0;
++
++ src_pagecount = PAGECOUNT(src, src_len);
++ dst_pagecount = PAGECOUNT(dst, dst_len);
++
++ ses->used_pages = (src == dst) ? max(src_pagecount, dst_pagecount)
++ : src_pagecount + dst_pagecount;
++
++ ses->readonly_pages = (src == dst) ? 0 : src_pagecount;
++
++ if (ses->used_pages > ses->array_size) {
++ rc = adjust_sg_array(ses, ses->used_pages);
++ if (rc)
++ return rc;
++ }
++
++ if (src == dst) { /* inplace operation */
++ /* When we encrypt for authenc modes we need to write
++ * more data than the ones we read. */
++ if (src_len < dst_len)
++ src_len = dst_len;
++ rc = __get_userbuf(src, src_len, 1, ses->used_pages,
++ ses->pages, ses->sg, task, mm);
++ if (unlikely(rc)) {
++ derr(1, "failed to get user pages for data IO");
++ return rc;
++ }
++ (*src_sg) = (*dst_sg) = ses->sg;
++ return 0;
++ }
++
++ *src_sg = NULL; /* default to no input */
++ *dst_sg = NULL; /* default to ignore output */
++
++ if (likely(src)) {
++ rc = __get_userbuf(src, src_len, 0, ses->readonly_pages,
++ ses->pages, ses->sg, task, mm);
++ if (unlikely(rc)) {
++ derr(1, "failed to get user pages for data input");
++ return rc;
++ }
++ *src_sg = ses->sg;
++ }
++
++ if (likely(dst)) {
++ const unsigned int writable_pages =
++ ses->used_pages - ses->readonly_pages;
++ struct page **dst_pages = ses->pages + ses->readonly_pages;
++ *dst_sg = ses->sg + ses->readonly_pages;
++
++ rc = __get_userbuf(dst, dst_len, 1, writable_pages,
++ dst_pages, *dst_sg, task, mm);
++ if (unlikely(rc)) {
++ derr(1, "failed to get user pages for data output");
++ release_user_pages(ses); /* FIXME: use __release_userbuf(src, ...) */
++ return rc;
++ }
++ }
++ return 0;
++}
++
+diff -Nur linux-3.14.72.orig/crypto/cryptodev/zc.h linux-3.14.72/crypto/cryptodev/zc.h
+--- linux-3.14.72.orig/crypto/cryptodev/zc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/crypto/cryptodev/zc.h 2016-06-19 22:11:55.069155494 +0200
+@@ -0,0 +1,27 @@
++#ifndef ZC_H
++# define ZC_H
++
++#include "cryptodev_int.h"
++
++/* For zero copy */
++int __get_userbuf(uint8_t __user *addr, uint32_t len, int write,
++ unsigned int pgcount, struct page **pg, struct scatterlist *sg,
++ struct task_struct *task, struct mm_struct *mm);
++void release_user_pages(struct csession *ses);
++
++int get_userbuf(struct csession *ses,
++ void *__user src, unsigned int src_len,
++ void *__user dst, unsigned int dst_len,
++ struct task_struct *task, struct mm_struct *mm,
++ struct scatterlist **src_sg,
++ struct scatterlist **dst_sg);
++
++/* buflen ? (last page - first page + 1) : 0 */
++#define PAGECOUNT(buf, buflen) ((buflen) \
++ ? ((((unsigned long)(buf + buflen - 1)) >> PAGE_SHIFT) - \
++ (((unsigned long)(buf )) >> PAGE_SHIFT) + 1) \
++ : 0)
++
++#define DEFAULT_PREALLOC_PAGES 32
++
++#endif
+diff -Nur linux-3.14.72.orig/crypto/Kconfig linux-3.14.72/crypto/Kconfig
+--- linux-3.14.72.orig/crypto/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/crypto/Kconfig 2016-06-19 22:11:55.069155494 +0200
+@@ -86,6 +86,13 @@
+ tristate
+ select CRYPTO_ALGAPI2
+
++config CRYPTO_CRYPTODEV
++ tristate "Cryptodev (/dev/crypto) interface"
++ depends on CRYPTO
++ help
++ Device /dev/crypto gives userspace programs access to
++ kernel crypto algorithms.
++
+ config CRYPTO_MANAGER
+ tristate "Cryptographic algorithm manager"
+ select CRYPTO_MANAGER2
+diff -Nur linux-3.14.72.orig/crypto/Makefile linux-3.14.72/crypto/Makefile
+--- linux-3.14.72.orig/crypto/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/crypto/Makefile 2016-06-19 22:11:55.069155494 +0200
+@@ -30,6 +30,7 @@
+
+ cryptomgr-y := algboss.o testmgr.o
+
++obj-$(CONFIG_CRYPTO_CRYPTODEV) += cryptodev/
+ obj-$(CONFIG_CRYPTO_MANAGER2) += cryptomgr.o
+ obj-$(CONFIG_CRYPTO_USER) += crypto_user.o
+ obj-$(CONFIG_CRYPTO_CMAC) += cmac.o
+diff -Nur linux-3.14.72.orig/crypto/tcrypt.c linux-3.14.72/crypto/tcrypt.c
+--- linux-3.14.72.orig/crypto/tcrypt.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/crypto/tcrypt.c 2016-06-19 22:11:55.069155494 +0200
+@@ -917,21 +917,28 @@
+ struct tcrypt_result tresult;
+ struct ahash_request *req;
+ struct crypto_ahash *tfm;
+- static char output[1024];
++ const int output_size = 1024;
++ char *output = kmalloc(output_size, GFP_KERNEL);
+ int i, ret;
+
++ if (!output) {
++ printk(KERN_INFO "\nUnable to allocate output buffer memory\n");
++ return;
++ }
++
+ printk(KERN_INFO "\ntesting speed of async %s\n", algo);
+
+ tfm = crypto_alloc_ahash(algo, 0, 0);
+ if (IS_ERR(tfm)) {
+ pr_err("failed to load transform for %s: %ld\n",
+ algo, PTR_ERR(tfm));
++ kfree(output);
+ return;
+ }
+
+- if (crypto_ahash_digestsize(tfm) > sizeof(output)) {
++ if (crypto_ahash_digestsize(tfm) > output_size) {
+ pr_err("digestsize(%u) > outputbuffer(%zu)\n",
+- crypto_ahash_digestsize(tfm), sizeof(output));
++ crypto_ahash_digestsize(tfm), output_size);
+ goto out;
+ }
+
+@@ -975,6 +982,7 @@
+ ahash_request_free(req);
+
+ out:
++ kfree(output);
+ crypto_free_ahash(tfm);
+ }
+
+diff -Nur linux-3.14.72.orig/crypto/testmgr.c linux-3.14.72/crypto/testmgr.c
+--- linux-3.14.72.orig/crypto/testmgr.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/crypto/testmgr.c 2016-06-19 22:11:55.069155494 +0200
+@@ -191,13 +191,20 @@
+ const char *algo = crypto_tfm_alg_driver_name(crypto_ahash_tfm(tfm));
+ unsigned int i, j, k, temp;
+ struct scatterlist sg[8];
+- char result[64];
++ char *result;
++ char *key;
+ struct ahash_request *req;
+ struct tcrypt_result tresult;
+ void *hash_buff;
+ char *xbuf[XBUFSIZE];
+ int ret = -ENOMEM;
+
++ result = kmalloc(MAX_DIGEST_SIZE, GFP_KERNEL);
++ if (!result)
++ return ret;
++ key = kmalloc(MAX_KEYLEN, GFP_KERNEL);
++ if (!key)
++ goto out_nobuf;
+ if (testmgr_alloc_buf(xbuf))
+ goto out_nobuf;
+
+@@ -222,7 +229,7 @@
+ goto out;
+
+ j++;
+- memset(result, 0, 64);
++ memset(result, 0, MAX_DIGEST_SIZE);
+
+ hash_buff = xbuf[0];
+ hash_buff += align_offset;
+@@ -232,8 +239,14 @@
+
+ if (template[i].ksize) {
+ crypto_ahash_clear_flags(tfm, ~0);
+- ret = crypto_ahash_setkey(tfm, template[i].key,
+- template[i].ksize);
++ if (template[i].ksize > MAX_KEYLEN) {
++ pr_err("alg: hash: setkey failed on test %d for %s: key size %d > %d\n",
++ j, algo, template[i].ksize, MAX_KEYLEN);
++ ret = -EINVAL;
++ goto out;
++ }
++ memcpy(key, template[i].key, template[i].ksize);
++ ret = crypto_ahash_setkey(tfm, key, template[i].ksize);
+ if (ret) {
+ printk(KERN_ERR "alg: hash: setkey failed on "
+ "test %d for %s: ret=%d\n", j, algo,
+@@ -293,7 +306,7 @@
+
+ if (template[i].np) {
+ j++;
+- memset(result, 0, 64);
++ memset(result, 0, MAX_DIGEST_SIZE);
+
+ temp = 0;
+ sg_init_table(sg, template[i].np);
+@@ -312,8 +325,16 @@
+ }
+
+ if (template[i].ksize) {
++ if (template[i].ksize > MAX_KEYLEN) {
++ pr_err("alg: hash: setkey failed on test %d for %s: key size %d > %d\n",
++ j, algo, template[i].ksize,
++ MAX_KEYLEN);
++ ret = -EINVAL;
++ goto out;
++ }
+ crypto_ahash_clear_flags(tfm, ~0);
+- ret = crypto_ahash_setkey(tfm, template[i].key,
++ memcpy(key, template[i].key, template[i].ksize);
++ ret = crypto_ahash_setkey(tfm, key,
+ template[i].ksize);
+
+ if (ret) {
+@@ -365,6 +386,8 @@
+ out_noreq:
+ testmgr_free_buf(xbuf);
+ out_nobuf:
++ kfree(key);
++ kfree(result);
+ return ret;
+ }
+
+@@ -414,16 +437,21 @@
+ void *input;
+ void *output;
+ void *assoc;
+- char iv[MAX_IVLEN];
++ char *iv;
+ char *xbuf[XBUFSIZE];
+ char *xoutbuf[XBUFSIZE];
+ char *axbuf[XBUFSIZE];
+
++ iv = kzalloc(MAX_IVLEN, GFP_KERNEL);
++ if (!iv)
++ return ret;
++ key = kmalloc(MAX_KEYLEN, GFP_KERNEL);
++ if (!key)
++ goto out_noxbuf;
+ if (testmgr_alloc_buf(xbuf))
+ goto out_noxbuf;
+ if (testmgr_alloc_buf(axbuf))
+ goto out_noaxbuf;
+-
+ if (diff_dst && testmgr_alloc_buf(xoutbuf))
+ goto out_nooutbuf;
+
+@@ -484,7 +512,14 @@
+ crypto_aead_set_flags(
+ tfm, CRYPTO_TFM_REQ_WEAK_KEY);
+
+- key = template[i].key;
++ if (template[i].klen > MAX_KEYLEN) {
++ pr_err("alg: aead%s: setkey failed on test %d for %s: key size %d > %d\n",
++ d, j, algo, template[i].klen,
++ MAX_KEYLEN);
++ ret = -EINVAL;
++ goto out;
++ }
++ memcpy(key, template[i].key, template[i].klen);
+
+ ret = crypto_aead_setkey(tfm, key,
+ template[i].klen);
+@@ -585,7 +620,14 @@
+ if (template[i].wk)
+ crypto_aead_set_flags(
+ tfm, CRYPTO_TFM_REQ_WEAK_KEY);
+- key = template[i].key;
++ if (template[i].klen > MAX_KEYLEN) {
++ pr_err("alg: aead%s: setkey failed on test %d for %s: key size %d > %d\n",
++ d, j, algo, template[i].klen,
++ MAX_KEYLEN);
++ ret = -EINVAL;
++ goto out;
++ }
++ memcpy(key, template[i].key, template[i].klen);
+
+ ret = crypto_aead_setkey(tfm, key, template[i].klen);
+ if (!ret == template[i].fail) {
+@@ -767,6 +809,8 @@
+ out_noaxbuf:
+ testmgr_free_buf(xbuf);
+ out_noxbuf:
++ kfree(key);
++ kfree(iv);
+ return ret;
+ }
+
+@@ -1809,6 +1853,18 @@
+ }
+ }
+ }, {
++ .alg = "authenc(hmac(md5),cbc(aes))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_md5_aes_cbc_enc_tv_template,
++ .count = HMAC_MD5_AES_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
+ .alg = "authenc(hmac(sha1),cbc(aes))",
+ .test = alg_test_aead,
+ .fips_allowed = 1,
+@@ -1821,6 +1877,54 @@
+ }
+ }
+ }, {
++ .alg = "authenc(hmac(sha1),cbc(des))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha1_des_cbc_enc_tv_template,
++ .count = HMAC_SHA1_DES_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
++ .alg = "authenc(hmac(sha1),cbc(des3_ede))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha1_des3_ede_cbc_enc_tv_template,
++ .count = HMAC_SHA1_DES3_EDE_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
++ .alg = "authenc(hmac(sha224),cbc(des))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha224_des_cbc_enc_tv_template,
++ .count = HMAC_SHA224_DES_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
++ .alg = "authenc(hmac(sha224),cbc(des3_ede))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha224_des3_ede_cbc_enc_tv_template,
++ .count = HMAC_SHA224_DES3_EDE_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
+ .alg = "authenc(hmac(sha256),cbc(aes))",
+ .test = alg_test_aead,
+ .fips_allowed = 1,
+@@ -1833,6 +1937,54 @@
+ }
+ }
+ }, {
++ .alg = "authenc(hmac(sha256),cbc(des))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha256_des_cbc_enc_tv_template,
++ .count = HMAC_SHA256_DES_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
++ .alg = "authenc(hmac(sha256),cbc(des3_ede))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha256_des3_ede_cbc_enc_tv_template,
++ .count = HMAC_SHA256_DES3_EDE_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
++ .alg = "authenc(hmac(sha384),cbc(des))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha384_des_cbc_enc_tv_template,
++ .count = HMAC_SHA384_DES_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
++ .alg = "authenc(hmac(sha384),cbc(des3_ede))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha384_des3_ede_cbc_enc_tv_template,
++ .count = HMAC_SHA384_DES3_EDE_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
+ .alg = "authenc(hmac(sha512),cbc(aes))",
+ .test = alg_test_aead,
+ .fips_allowed = 1,
+@@ -1845,6 +1997,30 @@
+ }
+ }
+ }, {
++ .alg = "authenc(hmac(sha512),cbc(des))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha512_des_cbc_enc_tv_template,
++ .count = HMAC_SHA512_DES_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
++ .alg = "authenc(hmac(sha512),cbc(des3_ede))",
++ .test = alg_test_aead,
++ .fips_allowed = 1,
++ .suite = {
++ .aead = {
++ .enc = {
++ .vecs = hmac_sha512_des3_ede_cbc_enc_tv_template,
++ .count = HMAC_SHA512_DES3_EDE_CBC_ENC_TEST_VECTORS
++ }
++ }
++ }
++ }, {
+ .alg = "cbc(aes)",
+ .test = alg_test_skcipher,
+ .fips_allowed = 1,
+diff -Nur linux-3.14.72.orig/crypto/testmgr.h linux-3.14.72/crypto/testmgr.h
+--- linux-3.14.72.orig/crypto/testmgr.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/crypto/testmgr.h 2016-06-19 22:11:55.073155238 +0200
+@@ -32,7 +32,7 @@
+ #define MAX_DIGEST_SIZE 64
+ #define MAX_TAP 8
+
+-#define MAX_KEYLEN 56
++#define MAX_KEYLEN 160
+ #define MAX_IVLEN 32
+
+ struct hash_testvec {
+@@ -94,6 +94,684 @@
+
+ static char zeroed_string[48];
+
++#define HMAC_MD5_AES_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_md5_aes_cbc_enc_tv_template[] = {
++ {
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x10" /* enc key length */
++ "\x00\x00\x00\x00\x00\x00\x00\x00"
++ "\x00\x00\x00\x00\x00\x00\x00\x00"
++ "\x06\xa9\x21\x40\x36\xb8\xa1\x5b"
++ "\x51\x2e\x03\xd5\x34\x12\x00\x06",
++ .klen = 8 + 16 + 16,
++ .iv = "\x3d\xaf\xba\x42\x9d\x9e\xb4\x30"
++ "\xb4\x22\xda\x80\x2c\x9f\xac\x41",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "Single block msg",
++ .ilen = 16,
++ .result = "\xe3\x53\x77\x9c\x10\x79\xae\xb8"
++ "\x27\x08\x94\x2d\xbe\x77\x18\x1a"
++ "\x76\xa8\x43\x89\xbd\xfe\xf9\x79"
++ "\x96\x64\x77\x02\x95\x21\x08\x4c",
++ .rlen = 16 + 16,
++ },
++};
++
++#define HMAC_SHA1_DES_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha1_des_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x08" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
++ .klen = 8 + 20 + 8,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
++ "\x54\x31\x85\x37\xed\x6b\x01\x8d"
++ "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
++ "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
++ "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
++ "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
++ "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
++ "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
++ "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
++ "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
++ "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
++ "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
++ "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
++ "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
++ "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
++ "\x53\xba\xe1\x76\xe3\x82\x07\x86"
++ "\x95\x16\x20\x09\xf5\x95\x19\xfd"
++ "\x3c\xc7\xe0\x42\xc0\x14\x69\xfa"
++ "\x5c\x44\xa9\x37",
++ .rlen = 128 + 20,
++ },
++};
++
++#define HMAC_SHA224_DES_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha224_des_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x08" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
++ .klen = 8 + 24 + 8,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
++ "\x54\x31\x85\x37\xed\x6b\x01\x8d"
++ "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
++ "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
++ "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
++ "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
++ "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
++ "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
++ "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
++ "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
++ "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
++ "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
++ "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
++ "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
++ "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
++ "\x53\xba\xe1\x76\xe3\x82\x07\x86"
++ "\x9c\x2d\x7e\xee\x20\x34\x55\x0a"
++ "\xce\xb5\x4e\x64\x53\xe7\xbf\x91"
++ "\xab\xd4\xd9\xda\xc9\x12\xae\xf7",
++ .rlen = 128 + 24,
++ },
++};
++
++#define HMAC_SHA256_DES_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha256_des_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x08" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
++ .klen = 8 + 32 + 8,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
++ "\x54\x31\x85\x37\xed\x6b\x01\x8d"
++ "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
++ "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
++ "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
++ "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
++ "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
++ "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
++ "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
++ "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
++ "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
++ "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
++ "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
++ "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
++ "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
++ "\x53\xba\xe1\x76\xe3\x82\x07\x86"
++ "\xc6\x58\xa1\x60\x70\x91\x39\x36"
++ "\x50\xf6\x5d\xab\x4b\x51\x4e\x5e"
++ "\xde\x63\xde\x76\x52\xde\x9f\xba"
++ "\x90\xcf\x15\xf2\xbb\x6e\x84\x00",
++ .rlen = 128 + 32,
++ },
++};
++
++#define HMAC_SHA384_DES_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha384_des_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x08" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
++ "\x33\x44\x55\x66\x77\x88\x99\xaa"
++ "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
++ .klen = 8 + 48 + 8,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
++ "\x54\x31\x85\x37\xed\x6b\x01\x8d"
++ "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
++ "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
++ "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
++ "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
++ "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
++ "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
++ "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
++ "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
++ "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
++ "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
++ "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
++ "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
++ "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
++ "\x53\xba\xe1\x76\xe3\x82\x07\x86"
++ "\xa8\x8e\x9c\x74\x8c\x2b\x99\xa0"
++ "\xc8\x8c\xef\x25\x07\x83\x11\x3a"
++ "\x31\x8d\xbe\x3b\x6a\xd7\x96\xfe"
++ "\x5e\x67\xb5\x74\xe7\xe7\x85\x61"
++ "\x6a\x95\x26\x75\xcc\x53\x89\xf3"
++ "\x74\xc9\x2a\x76\x20\xa2\x64\x62",
++ .rlen = 128 + 48,
++ },
++};
++
++#define HMAC_SHA512_DES_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha512_des_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x08" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
++ "\x33\x44\x55\x66\x77\x88\x99\xaa"
++ "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
++ "\x44\x55\x66\x77\x88\x99\xaa\xbb"
++ "\xcc\xdd\xee\xff\x11\x22\x33\x44"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24",
++ .klen = 8 + 64 + 8,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x70\xd6\xde\x64\x87\x17\xf1\xe8"
++ "\x54\x31\x85\x37\xed\x6b\x01\x8d"
++ "\xe3\xcc\xe0\x1d\x5e\xf3\xfe\xf1"
++ "\x41\xaa\x33\x91\xa7\x7d\x99\x88"
++ "\x4d\x85\x6e\x2f\xa3\x69\xf5\x82"
++ "\x3a\x6f\x25\xcb\x7d\x58\x1f\x9b"
++ "\xaa\x9c\x11\xd5\x76\x67\xce\xde"
++ "\x56\xd7\x5a\x80\x69\xea\x3a\x02"
++ "\xf0\xc7\x7c\xe3\xcb\x40\xe5\x52"
++ "\xd1\x10\x92\x78\x0b\x8e\x5b\xf1"
++ "\xe3\x26\x1f\xe1\x15\x41\xc7\xba"
++ "\x99\xdb\x08\x51\x1c\xd3\x01\xf4"
++ "\x87\x47\x39\xb8\xd2\xdd\xbd\xfb"
++ "\x66\x13\xdf\x1c\x01\x44\xf0\x7a"
++ "\x1a\x6b\x13\xf5\xd5\x0b\xb8\xba"
++ "\x53\xba\xe1\x76\xe3\x82\x07\x86"
++ "\xc6\x2c\x73\x88\xb0\x9d\x5f\x3e"
++ "\x5b\x78\xca\x0e\xab\x8a\xa3\xbb"
++ "\xd9\x1d\xc3\xe3\x05\xac\x76\xfb"
++ "\x58\x83\xda\x67\xfb\x21\x24\xa2"
++ "\xb1\xa7\xd7\x66\xa6\x8d\xa6\x93"
++ "\x97\xe2\xe3\xb8\xaa\x48\x85\xee"
++ "\x8c\xf6\x07\x95\x1f\xa6\x6c\x96"
++ "\x99\xc7\x5c\x8d\xd8\xb5\x68\x7b",
++ .rlen = 128 + 64,
++ },
++};
++
++
++#define HMAC_SHA1_DES3_EDE_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha1_des3_ede_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x18" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
++ "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
++ "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
++ .klen = 8 + 20 + 24,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
++ "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
++ "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
++ "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
++ "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
++ "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
++ "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
++ "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
++ "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
++ "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
++ "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
++ "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
++ "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
++ "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
++ "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
++ "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
++ "\x67\x6d\xb1\xf5\xb8\x10\xdc\xc6"
++ "\x75\x86\x96\x6b\xb1\xc5\xe4\xcf"
++ "\xd1\x60\x91\xb3",
++ .rlen = 128 + 20,
++ },
++};
++
++#define HMAC_SHA224_DES3_EDE_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha224_des3_ede_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x18" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
++ "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
++ "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
++ .klen = 8 + 24 + 24,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
++ "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
++ "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
++ "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
++ "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
++ "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
++ "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
++ "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
++ "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
++ "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
++ "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
++ "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
++ "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
++ "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
++ "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
++ "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
++ "\x15\x24\x7f\x5a\x45\x4a\x66\xce"
++ "\x2b\x0b\x93\x99\x2f\x9d\x0c\x6c"
++ "\x56\x1f\xe1\xa6\x41\xb2\x4c\xd0",
++ .rlen = 128 + 24,
++ },
++};
++
++#define HMAC_SHA256_DES3_EDE_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha256_des3_ede_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x18" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
++ "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
++ "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
++ .klen = 8 + 32 + 24,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
++ "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
++ "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
++ "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
++ "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
++ "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
++ "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
++ "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
++ "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
++ "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
++ "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
++ "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
++ "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
++ "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
++ "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
++ "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
++ "\x73\xb0\xea\x9f\xe8\x18\x80\xd6"
++ "\x56\x38\x44\xc0\xdb\xe3\x4f\x71"
++ "\xf7\xce\xd1\xd3\xf8\xbd\x3e\x4f"
++ "\xca\x43\x95\xdf\x80\x61\x81\xa9",
++ .rlen = 128 + 32,
++ },
++};
++
++#define HMAC_SHA384_DES3_EDE_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha384_des3_ede_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x18" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
++ "\x33\x44\x55\x66\x77\x88\x99\xaa"
++ "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
++ "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
++ "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
++ .klen = 8 + 48 + 24,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
++ "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
++ "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
++ "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
++ "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
++ "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
++ "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
++ "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
++ "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
++ "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
++ "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
++ "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
++ "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
++ "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
++ "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
++ "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
++ "\x6d\x77\xfc\x80\x9d\x8a\x9c\xb7"
++ "\x70\xe7\x93\xbf\x73\xe6\x9f\x83"
++ "\x99\x62\x23\xe6\x5b\xd0\xda\x18"
++ "\xa4\x32\x8a\x0b\x46\xd7\xf0\x39"
++ "\x36\x5d\x13\x2f\x86\x10\x78\xd6"
++ "\xd6\xbe\x5c\xb9\x15\x89\xf9\x1b",
++ .rlen = 128 + 48,
++ },
++};
++
++#define HMAC_SHA512_DES3_EDE_CBC_ENC_TEST_VECTORS 1
++
++static struct aead_testvec hmac_sha512_des3_ede_cbc_enc_tv_template[] = {
++ { /*Generated with cryptopp*/
++#ifdef __LITTLE_ENDIAN
++ .key = "\x08\x00" /* rta length */
++ "\x01\x00" /* rta type */
++#else
++ .key = "\x00\x08" /* rta length */
++ "\x00\x01" /* rta type */
++#endif
++ "\x00\x00\x00\x18" /* enc key length */
++ "\x11\x22\x33\x44\x55\x66\x77\x88"
++ "\x99\xaa\xbb\xcc\xdd\xee\xff\x11"
++ "\x22\x33\x44\x55\x66\x77\x88\x99"
++ "\xaa\xbb\xcc\xdd\xee\xff\x11\x22"
++ "\x33\x44\x55\x66\x77\x88\x99\xaa"
++ "\xbb\xcc\xdd\xee\xff\x11\x22\x33"
++ "\x44\x55\x66\x77\x88\x99\xaa\xbb"
++ "\xcc\xdd\xee\xff\x11\x22\x33\x44"
++ "\xE9\xC0\xFF\x2E\x76\x0B\x64\x24"
++ "\x44\x4D\x99\x5A\x12\xD6\x40\xC0"
++ "\xEA\xC2\x84\xE8\x14\x95\xDB\xE8",
++ .klen = 8 + 64 + 24,
++ .iv = "\x7D\x33\x88\x93\x0F\x93\xB2\x42",
++ .assoc = "\x00\x00\x43\x21\x00\x00\x00\x01",
++ .alen = 8,
++ .input = "\x6f\x54\x20\x6f\x61\x4d\x79\x6e"
++ "\x53\x20\x63\x65\x65\x72\x73\x74"
++ "\x54\x20\x6f\x6f\x4d\x20\x6e\x61"
++ "\x20\x79\x65\x53\x72\x63\x74\x65"
++ "\x20\x73\x6f\x54\x20\x6f\x61\x4d"
++ "\x79\x6e\x53\x20\x63\x65\x65\x72"
++ "\x73\x74\x54\x20\x6f\x6f\x4d\x20"
++ "\x6e\x61\x20\x79\x65\x53\x72\x63"
++ "\x74\x65\x20\x73\x6f\x54\x20\x6f"
++ "\x61\x4d\x79\x6e\x53\x20\x63\x65"
++ "\x65\x72\x73\x74\x54\x20\x6f\x6f"
++ "\x4d\x20\x6e\x61\x20\x79\x65\x53"
++ "\x72\x63\x74\x65\x20\x73\x6f\x54"
++ "\x20\x6f\x61\x4d\x79\x6e\x53\x20"
++ "\x63\x65\x65\x72\x73\x74\x54\x20"
++ "\x6f\x6f\x4d\x20\x6e\x61\x0a\x79",
++ .ilen = 128,
++ .result = "\x0e\x2d\xb6\x97\x3c\x56\x33\xf4"
++ "\x67\x17\x21\xc7\x6e\x8a\xd5\x49"
++ "\x74\xb3\x49\x05\xc5\x1c\xd0\xed"
++ "\x12\x56\x5c\x53\x96\xb6\x00\x7d"
++ "\x90\x48\xfc\xf5\x8d\x29\x39\xcc"
++ "\x8a\xd5\x35\x18\x36\x23\x4e\xd7"
++ "\x76\xd1\xda\x0c\x94\x67\xbb\x04"
++ "\x8b\xf2\x03\x6c\xa8\xcf\xb6\xea"
++ "\x22\x64\x47\xaa\x8f\x75\x13\xbf"
++ "\x9f\xc2\xc3\xf0\xc9\x56\xc5\x7a"
++ "\x71\x63\x2e\x89\x7b\x1e\x12\xca"
++ "\xe2\x5f\xaf\xd8\xa4\xf8\xc9\x7a"
++ "\xd6\xf9\x21\x31\x62\x44\x45\xa6"
++ "\xd6\xbc\x5a\xd3\x2d\x54\x43\xcc"
++ "\x9d\xde\xa5\x70\xe9\x42\x45\x8a"
++ "\x6b\xfa\xb1\x91\x13\xb0\xd9\x19"
++ "\x41\xb5\x1f\xbb\xbd\x4e\xb8\x32"
++ "\x22\x86\x4e\x57\x1b\x2a\xd8\x6e"
++ "\xa9\xfb\xc8\xf3\xbf\x2d\xae\x2b"
++ "\x3b\xbc\x41\xe8\x38\xbb\xf1\x60"
++ "\x4c\x68\xa9\x4e\x8c\x73\xa7\xc0"
++ "\x2a\x74\xd4\x65\x12\xcb\x55\xf2"
++ "\xd5\x02\x6d\xe6\xaf\xc9\x2f\xf2"
++ "\x57\xaa\x85\xf7\xf3\x6a\xcb\xdb",
++ .rlen = 128 + 64,
++ },
++};
++
+ /*
+ * MD4 test vectors from RFC1320
+ */
+diff -Nur linux-3.14.72.orig/Documentation/ABI/testing/sysfs-platform-chipidea-usb-otg linux-3.14.72/Documentation/ABI/testing/sysfs-platform-chipidea-usb-otg
+--- linux-3.14.72.orig/Documentation/ABI/testing/sysfs-platform-chipidea-usb-otg 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/ABI/testing/sysfs-platform-chipidea-usb-otg 2016-06-19 22:11:55.073155238 +0200
+@@ -0,0 +1,56 @@
++What: /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
++Date: Feb 2014
++Contact: Li Jun <b47624@freescale.com>
++Description:
++ Can be set and read.
++ Set a_bus_req(A-device bus request) input to be 1 if
++ the application running on the A-device wants to use the bus,
++ and to be 0 when the application no longer wants to use
++ the bus(or wants to work as peripheral). a_bus_req can also
++ be set to 1 by kernel in response to remote wakeup signaling
++ from the B-device, the A-device should decide to resume the bus.
++
++ Valid values are "1" and "0".
++
++ Reading: returns 1 if the application running on the A-device
++ is using the bus as host role, otherwise 0.
++
++What: /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_drop
++Date: Feb 2014
++Contact: Li Jun <b47624@freescale.com>
++Description:
++ Can be set and read
++ The a_bus_drop(A-device bus drop) input is 1 when the
++ application running on the A-device wants to power down
++ the bus, and is 0 otherwise, When a_bus_drop is 1, then
++ the a_bus_req shall be 0.
++
++ Valid values are "1" and "0".
++
++ Reading: returns 1 if the bus is off(vbus is turned off) by
++ A-device, otherwise 0.
++
++What: /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
++Date: Feb 2014
++Contact: Li Jun <b47624@freescale.com>
++Description:
++ Can be set and read.
++ The b_bus_req(B-device bus request) input is 1 during the time
++ that the application running on the B-device wants to use the
++ bus as host, and is 0 when the application no longer wants to
++ work as host and decides to switch back to be peripheral.
++
++ Valid values are "1" and "0".
++
++ Reading: returns if the application running on the B device
++ is using the bus as host role, otherwise 0.
++
++What: /sys/bus/platform/devices/ci_hdrc.0/inputs/a_clr_err
++Date: Feb 2014
++Contact: Li Jun <b47624@freescale.com>
++Description:
++ Only can be set.
++ The a_clr_err(A-device Vbus error clear) input is used to clear
++ vbus error, then A-device will power down the bus.
++
++ Valid value is "1"
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt linux-3.14.72/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/arm/imx/busfreq-imx6.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -0,0 +1,64 @@
++Freescale Busfreq driver
++
++It is a generic driver that manages the frequency of the DDR, AHB and AXI buses in the iMX6x architecture.
++It works for both SMP and UP systems and for both DDR3 and LPDDR2 memory types.
++
++Required properties are listed below:
++- compatible: should be "fsl,imx6_busfreq"
++- clocks: Lists the various clocks used by the busfreq driver
++- interrupts - Lists the interrupts used by the busfreq driver. This is needed only for SMP architecutre.
++- fsl,max_ddr_freq - The max ddr freq for this chip
++
++Examples:
++For SOC imx6q.dtsi:
++ busfreq { /* BUSFREQ */
++ compatible = "fsl,imx6_busfreq";
++ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
++ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
++ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
++ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
++ interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
++ interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
++ fsl,max_ddr_freq = <528000000>;
++ };
++
++The Freescale Busfreq driver supports the following setpoints for the DDR freq:
++enum bus_freq_mode {
++ BUS_FREQ_HIGH, -> The max freq the SOC supports
++ BUS_FREQ_MED, -> Medium setpoint (ex 400MHz for DDR3 when the max is 528MHz)
++ BUS_FREQ_AUDIO, -> Audio playback freq (50MHz)
++ BUS_FREQ_LOW, -> Low power IDLE freq (24MHz)
++};
++
++Currently the Freescale Busfreq driver implementation requires drivers to call the following APIs:
++1. request_bus_freq(enum bus_freq_mode):
++ The driver is requesting the system and ddr freq to be set to the requested value. The driver should call this
++ API before it even enables its clocks.
++
++2. release_bus_freq(enum bus_freq_mode):
++ The driver no longer needs the system and ddr freq at the required value. The driver should call this API after
++ its work is done and it has disabled its clocks.
++
++Examples:
++In the IPU driver, the requesting and releasing of the required bus frequency is tied into the runtime PM implementation:
++
++int ipu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high release.\n");
++
++ return 0;
++}
++
++int ipu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high requst.\n");
++
++ return 0;
++}
++
++static const struct dev_pm_ops ipu_pm_ops = {
++ SET_RUNTIME_PM_OPS(ipu_runtime_suspend, ipu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(ipu_suspend, ipu_resume)
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/arm/l2cc.txt linux-3.14.72/Documentation/devicetree/bindings/arm/l2cc.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/arm/l2cc.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/arm/l2cc.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -40,6 +40,8 @@
+ - arm,filter-ranges : <start length> Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
++- arm,dynamic-clk-gating : Enables dynamic clock gating (PL310)
++- arm,standby-mode : Enables standby mode (PL310)
+ - interrupts : 1 combined interrupt.
+ - cache-id-part: cache id part number to be used if it is not present
+ on hardware
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/ata/ahci-platform.txt linux-3.14.72/Documentation/devicetree/bindings/ata/ahci-platform.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/ata/ahci-platform.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/ata/ahci-platform.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -4,17 +4,39 @@
+ Each SATA controller should have its own node.
+
+ Required properties:
+-- compatible : compatible list, contains "snps,spear-ahci"
++- compatible : compatible string, one of:
++ - "allwinner,sun4i-a10-ahci"
++ - "fsl,imx53-ahci"
++ - "fsl,imx6q-ahci"
++ - "hisilicon,hisi-ahci"
++ - "ibm,476gtr-ahci"
++ - "marvell,armada-380-ahci"
++ - "snps,dwc-ahci"
++ - "snps,exynos5440-ahci"
++ - "snps,spear-ahci"
+ - interrupts : <interrupt mapping for SATA IRQ>
+ - reg : <registers mapping>
+
+ Optional properties:
+ - dma-coherent : Present if dma operations are coherent
++- clocks : a list of phandle + clock specifier pairs
++- target-supply : regulator for SATA target power
+
+-Example:
++"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:
++- clocks : must contain the sata, sata_ref and ahb clocks
++- clock-names : must contain "ahb" for the ahb clock
++
++Examples:
+ sata@ffe08000 {
+ compatible = "snps,spear-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;
+-
+ };
++
++ ahci: sata@01c18000 {
++ compatible = "allwinner,sun4i-a10-ahci";
++ reg = <0x01c18000 0x1000>;
++ interrupts = <56>;
++ clocks = <&pll6 0>, <&ahb_gates 25>;
++ target-supply = <&reg_ahci_5v>;
++ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/clock/clock-bindings.txt linux-3.14.72/Documentation/devicetree/bindings/clock/clock-bindings.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/clock/clock-bindings.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/clock/clock-bindings.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -115,3 +115,39 @@
+ ("pll" and "pll-switched").
+ * The UART has its baud clock connected the external oscillator and its
+ register clock connected to the PLL clock (the "pll-switched" signal)
++
++==Assigned clock parents and rates==
++
++Some platforms may require initial configuration of default parent clocks
++and clock frequencies. Such a configuration can be specified in a device tree
++node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
++properties. The assigned-clock-parents property should contain a list of parent
++clocks in form of phandle and clock specifier pairs, the assigned-clock-parents
++property the list of assigned clock frequency values - corresponding to clocks
++listed in the assigned-clocks property.
++
++To skip setting parent or rate of a clock its corresponding entry should be
++set to 0, or can be omitted if it is not followed by any non-zero entry.
++
++ uart@a000 {
++ compatible = "fsl,imx-uart";
++ reg = <0xa000 0x1000>;
++ ...
++ clocks = <&osc 0>, <&pll 1>;
++ clock-names = "baud", "register";
++
++ assigned-clocks = <&clkcon 0>, <&pll 2>;
++ assigned-clock-parents = <&pll 2>;
++ assigned-clock-rates = <0>, <460800>;
++ };
++
++In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
++the <&pll 2> clock is assigned a frequency value of 460800 Hz.
++
++Configuring a clock's parent and rate through the device node that consumes
++the clock can be done only for clocks that have a single user. Specifying
++conflicting parent or rate configuration in multiple consumer nodes for
++a shared clock is forbidden.
++
++Configuration of common clocks, which affect multiple consumer devices can
++be similarly specified in the clock provider node.
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/clock/imx6q-clock.txt linux-3.14.72/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/clock/imx6q-clock.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/clock/imx6q-clock.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -7,222 +7,13 @@
+ - #clock-cells: Should be <1>
+
+ The clock consumer should specify the desired clock by having the clock
+-ID in its "clocks" phandle cell. The following is a full list of i.MX6Q
+-clocks and IDs.
+-
+- Clock ID
+- ---------------------------
+- dummy 0
+- ckil 1
+- ckih 2
+- osc 3
+- pll2_pfd0_352m 4
+- pll2_pfd1_594m 5
+- pll2_pfd2_396m 6
+- pll3_pfd0_720m 7
+- pll3_pfd1_540m 8
+- pll3_pfd2_508m 9
+- pll3_pfd3_454m 10
+- pll2_198m 11
+- pll3_120m 12
+- pll3_80m 13
+- pll3_60m 14
+- twd 15
+- step 16
+- pll1_sw 17
+- periph_pre 18
+- periph2_pre 19
+- periph_clk2_sel 20
+- periph2_clk2_sel 21
+- axi_sel 22
+- esai_sel 23
+- asrc_sel 24
+- spdif_sel 25
+- gpu2d_axi 26
+- gpu3d_axi 27
+- gpu2d_core_sel 28
+- gpu3d_core_sel 29
+- gpu3d_shader_sel 30
+- ipu1_sel 31
+- ipu2_sel 32
+- ldb_di0_sel 33
+- ldb_di1_sel 34
+- ipu1_di0_pre_sel 35
+- ipu1_di1_pre_sel 36
+- ipu2_di0_pre_sel 37
+- ipu2_di1_pre_sel 38
+- ipu1_di0_sel 39
+- ipu1_di1_sel 40
+- ipu2_di0_sel 41
+- ipu2_di1_sel 42
+- hsi_tx_sel 43
+- pcie_axi_sel 44
+- ssi1_sel 45
+- ssi2_sel 46
+- ssi3_sel 47
+- usdhc1_sel 48
+- usdhc2_sel 49
+- usdhc3_sel 50
+- usdhc4_sel 51
+- enfc_sel 52
+- emi_sel 53
+- emi_slow_sel 54
+- vdo_axi_sel 55
+- vpu_axi_sel 56
+- cko1_sel 57
+- periph 58
+- periph2 59
+- periph_clk2 60
+- periph2_clk2 61
+- ipg 62
+- ipg_per 63
+- esai_pred 64
+- esai_podf 65
+- asrc_pred 66
+- asrc_podf 67
+- spdif_pred 68
+- spdif_podf 69
+- can_root 70
+- ecspi_root 71
+- gpu2d_core_podf 72
+- gpu3d_core_podf 73
+- gpu3d_shader 74
+- ipu1_podf 75
+- ipu2_podf 76
+- ldb_di0_podf 77
+- ldb_di1_podf 78
+- ipu1_di0_pre 79
+- ipu1_di1_pre 80
+- ipu2_di0_pre 81
+- ipu2_di1_pre 82
+- hsi_tx_podf 83
+- ssi1_pred 84
+- ssi1_podf 85
+- ssi2_pred 86
+- ssi2_podf 87
+- ssi3_pred 88
+- ssi3_podf 89
+- uart_serial_podf 90
+- usdhc1_podf 91
+- usdhc2_podf 92
+- usdhc3_podf 93
+- usdhc4_podf 94
+- enfc_pred 95
+- enfc_podf 96
+- emi_podf 97
+- emi_slow_podf 98
+- vpu_axi_podf 99
+- cko1_podf 100
+- axi 101
+- mmdc_ch0_axi_podf 102
+- mmdc_ch1_axi_podf 103
+- arm 104
+- ahb 105
+- apbh_dma 106
+- asrc 107
+- can1_ipg 108
+- can1_serial 109
+- can2_ipg 110
+- can2_serial 111
+- ecspi1 112
+- ecspi2 113
+- ecspi3 114
+- ecspi4 115
+- ecspi5 116
+- enet 117
+- esai 118
+- gpt_ipg 119
+- gpt_ipg_per 120
+- gpu2d_core 121
+- gpu3d_core 122
+- hdmi_iahb 123
+- hdmi_isfr 124
+- i2c1 125
+- i2c2 126
+- i2c3 127
+- iim 128
+- enfc 129
+- ipu1 130
+- ipu1_di0 131
+- ipu1_di1 132
+- ipu2 133
+- ipu2_di0 134
+- ldb_di0 135
+- ldb_di1 136
+- ipu2_di1 137
+- hsi_tx 138
+- mlb 139
+- mmdc_ch0_axi 140
+- mmdc_ch1_axi 141
+- ocram 142
+- openvg_axi 143
+- pcie_axi 144
+- pwm1 145
+- pwm2 146
+- pwm3 147
+- pwm4 148
+- per1_bch 149
+- gpmi_bch_apb 150
+- gpmi_bch 151
+- gpmi_io 152
+- gpmi_apb 153
+- sata 154
+- sdma 155
+- spba 156
+- ssi1 157
+- ssi2 158
+- ssi3 159
+- uart_ipg 160
+- uart_serial 161
+- usboh3 162
+- usdhc1 163
+- usdhc2 164
+- usdhc3 165
+- usdhc4 166
+- vdo_axi 167
+- vpu_axi 168
+- cko1 169
+- pll1_sys 170
+- pll2_bus 171
+- pll3_usb_otg 172
+- pll4_audio 173
+- pll5_video 174
+- pll8_mlb 175
+- pll7_usb_host 176
+- pll6_enet 177
+- ssi1_ipg 178
+- ssi2_ipg 179
+- ssi3_ipg 180
+- rom 181
+- usbphy1 182
+- usbphy2 183
+- ldb_di0_div_3_5 184
+- ldb_di1_div_3_5 185
+- sata_ref 186
+- sata_ref_100m 187
+- pcie_ref 188
+- pcie_ref_125m 189
+- enet_ref 190
+- usbphy1_gate 191
+- usbphy2_gate 192
+- pll4_post_div 193
+- pll5_post_div 194
+- pll5_video_div 195
+- eim_slow 196
+- spdif 197
+- cko2_sel 198
+- cko2_podf 199
+- cko2 200
+- cko 201
+- vdoa 202
+- pll4_audio_div 203
+- lvds1_sel 204
+- lvds2_sel 205
+- lvds1_gate 206
+- lvds2_gate 207
++ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6qdl-clock.h
++for the full list of i.MX6 Quad and DualLite clock IDs.
+
+ Examples:
+
++#include <dt-bindings/clock/imx6qdl-clock.h>
++
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6q-ccm";
+ reg = <0x020c4000 0x4000>;
+@@ -234,7 +25,7 @@
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <0 26 0x04>;
+- clocks = <&clks 160>, <&clks 161>;
++ clocks = <&clks IMX6QDL_CLK_UART_IPG>, <&clks IMX6QDL_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/clock/imx6sx-clock.txt linux-3.14.72/Documentation/devicetree/bindings/clock/imx6sx-clock.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/clock/imx6sx-clock.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/clock/imx6sx-clock.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -0,0 +1,13 @@
++* Clock bindings for Freescale i.MX6 SoloX
++
++Required properties:
++- compatible: Should be "fsl,imx6sx-ccm"
++- reg: Address and length of the register set
++- #clock-cells: Should be <1>
++- clocks: list of clock specifiers, must contain an entry for each required
++ entry in clock-names
++- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
++
++The clock consumer should specify the desired clock by having the clock
++ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
++for the full list of i.MX6 SoloX clock IDs.
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt linux-3.14.72/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -16,6 +16,12 @@
+ - #dma-cells : Must be <3>.
+ The first cell specifies the DMA request/event ID. See details below
+ about the second and third cell.
++- gpr : The phandle to general purpose register node.
++- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
++ <reg shift val>.
++ reg is the gpr register offset.
++ shift is the bit offset of event remap.
++ val is the value of the bit to be set.
+ - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
+ scripts firmware
+
+@@ -47,6 +53,9 @@
+ 20 ASRC
+ 21 ESAI
+ 22 SSI Dual FIFO (needs firmware ver >= 2)
++ 23 Shared ASRC
++ 24 HDMI Audio
++ 25 SAI
+
+ The third cell specifies the transfer priority as below.
+
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt linux-3.14.72/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -0,0 +1,118 @@
++* FSL IPUv3 Display/FB
++
++The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics
++subsystem in an application processor. The goal of the IPU is to provide
++comprehensive support for the flow of data from an image sensor or/and to a
++display device.
++
++Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC.
++Each IPU unit has two display interfaces.
++
++Required properties for IPU:
++- bypass_reset :Bypass reset to avoid display channel being.
++ stopped by probe since it may start to work in bootloader: 0 or 1.
++- compatible : should be "fsl,imx6q-ipu".
++- reg : the register address range.
++- interrupts : the error and sync interrupts request.
++- clocks : the clock sources that it depends on.
++- clock-names: the related clock names.
++- resets : IPU reset specifier. See reset.txt and fsl,imx-src.txt in
++ Documentation/devicetree/bindings/reset/ for details.
++
++Required properties for fb:
++- compatible : should be "fsl,mxc_sdc_fb".
++- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi", "adv739x".
++- mode_str : video mode string: "LDB-XGA" or "LDB-1080P60" for ldb,
++ "CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel,
++ "1920x1080M@60" for hdmi, "BT656-NTSC" or "BT656-PAL" for adv739x.
++- default_bpp : default bits per pixel: 8/16/24/32
++- int_clk : use internal clock as pixel clock: 0 or 1
++- late_init : to avoid display channel being re-initialized
++ as we've probably setup the channel in bootloader: 0 or 1
++- interface_pix_fmt : display interface pixel format as below:
++ RGB666 IPU_PIX_FMT_RGB666
++ RGB565 IPU_PIX_FMT_RGB565
++ RGB24 IPU_PIX_FMT_RGB24
++ BGR24 IPU_PIX_FMT_BGR24
++ GBR24 IPU_PIX_FMT_GBR24
++ YUV444 IPU_PIX_FMT_YUV444
++ YUYV IPU_PIX_FMT_YUYV
++ UYVY IPU_PIX_FMT_UYVY
++ YVYV IPU_PIX_FMT_YVYU
++ VYUY IPU_PIX_FMT_VYUY
++
++Required properties for display:
++- compatible : should be "fsl,lcd" for lcd panel
++- reg : the register address range if necessary to have.
++- interrupts : the error and sync interrupts if necessary to have.
++- clocks : the clock sources that it depends on if necessary to have.
++- clock-names: the related clock names if necessary to have.
++- ipu_id : ipu id for the first display device: 0 or 1
++- disp_id : display interface id for the first display interface: 0 or 1
++- default_ifmt : save as above display interface pixel format for lcd
++- pinctrl-names : should be "default"
++- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the
++ IPU connected.
++- gpr : the mux controller for the display engine's display interfaces and the display encoder
++ (only valid for mipi dsi now).
++- disp-power-on-supply : the regulator to control display panel's power.
++ (only valid for mipi dsi now).
++- resets : the gpio pin to reset the display device(only valid for mipi display panel now).
++- lcd_panel : the video mode name for the display device(only valid for mipi display panel now).
++- dev_id : the display engine's identity within the system, which intends to replace ipu_id
++ (only valid for mipi dsi now).
++
++Example for IPU:
++ ipu1: ipu@02400000 {
++ compatible = "fsl,imx6q-ipu";
++ reg = <0x02400000 0x400000>;
++ interrupts = <0 6 0x4 0 5 0x4>;
++ clocks = <&clks 130>, <&clks 131>, <&clks 132>,
++ <&clks 39>, <&clks 40>,
++ <&clks 135>, <&clks 136>;
++ clock-names = "bus", "di0", "di1",
++ "di0_sel", "di1_sel",
++ "ldb_di0", "ldb_di1";
++ resets = <&src 2>;
++ bypass_reset = <0>;
++ };
++
++Example for fb:
++ fb0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "ldb";
++ interface_pix_fmt = "RGB666";
++ mode_str ="LDB-XGA";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++Example for mipi dsi display:
++ mipi_dsi: mipi@021e0000 {
++ compatible = "fsl,imx6q-mipi-dsi";
++ reg = <0x021e0000 0x4000>;
++ interrupts = <0 102 0x04>;
++ gpr = <&gpr>;
++ clocks = <&clks 138>, <&clks 204>;
++ clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
++ dev_id = <0>;
++ disp_id = <0>;
++ lcd_panel = "TRULY-WVGA";
++ disp-power-on-supply = <&reg_mipi_dsi_pwr_on>
++ resets = <&mipi_dsi_reset>;
++ status = "okay";
++ };
++
++Example for adv739x CVBS output:
++ fb0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "adv739x";
++ interface_pix_fmt = "BT656";
++ mode_str ="BT656-NTSC";
++ default_bpp = <16>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/fb/mxsfb.txt linux-3.14.72/Documentation/devicetree/bindings/fb/mxsfb.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/fb/mxsfb.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/fb/mxsfb.txt 2016-06-19 22:11:55.073155238 +0200
+@@ -3,6 +3,9 @@
+ Required properties:
+ - compatible: Should be "fsl,<chip>-lcdif". Supported chips include
+ imx23 and imx28.
++- pinctrl-names: Should be "default"
++- pinctrl-0: pinctrl setting for lcd
++- lcd-supply: lcd power supply, usually via GPIO
+ - reg: Address and length of the register set for lcdif
+ - interrupts: Should contain lcdif interrupts
+ - display : phandle to display node (see below for details)
+@@ -22,6 +25,10 @@
+ compatible = "fsl,imx28-lcdif";
+ reg = <0x80030000 2000>;
+ interrupts = <38 86>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&lcdif_24bit_pins_a
++ &lcdif_pins_evk>;
++ lcd-supply = <&reg_lcd_3v3>;
+
+ display: display {
+ bits-per-pixel = <32>;
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/input/snvs-pwrkey.txt linux-3.14.72/Documentation/devicetree/bindings/input/snvs-pwrkey.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/input/snvs-pwrkey.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/input/snvs-pwrkey.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,26 @@
++* Freescale i.MX SNVS powerkey device tree bindings
++
++The snvs-pwrkey is designed to enable POWER key function which controlled
++by SNVS ONOFF, the driver can report the status of POWER key and wakeup
++system if pressed after system suspend.
++
++Required SoC Specific Properties:
++- compatible: Should be "fsl,imx6sx-snvs-pwrkey".
++
++- reg: Physical base address of the SNVS and length of memory mapped
++ region.
++
++- interrupts: The SNVS interrupt number to the CPU(s).
++
++- fsl,keycode: Keycode to emit, KEY_POWER by default.
++
++- fsl,wakeup: Button can wake-up the system
++
++Example:
++snvs-pwrkey@0x020cc000 {
++ compatible = "fsl,imx6sx-snvs-pwrkey";
++ reg = <0x020cc000 0x4000>;
++ interrupts = <0 4 0x4>;
++ fsl,keycode = <116>; /* KEY_POWER */
++ fsl,wakeup;
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt linux-3.14.72/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,55 @@
++FocalTech EDT-FT5x06 Polytouch driver
++=====================================
++
++There are 3 variants of the chip for various touch panel sizes
++FT5206GE1 2.8" .. 3.8"
++FT5306DE4 4.3" .. 7"
++FT5406EE8 7" .. 8.9"
++
++The software interface is identical for all those chips, so that
++currently there is no need for the driver to distinguish between the
++different chips. Nevertheless distinct compatible strings are used so
++that a distinction can be added if necessary without changing the DT
++bindings.
++
++
++Required properties:
++ - compatible: "edt,edt-ft5206"
++ or: "edt,edt-ft5306"
++ or: "edt,edt-ft5406"
++
++ - reg: I2C slave address of the chip (0x38)
++ - interrupt-parent: a phandle pointing to the interrupt controller
++ serving the interrupt for this chip
++ - interrupts: interrupt specification for the touchdetect
++ interrupt
++
++Optional properties:
++ - reset-gpios: GPIO specification for the RESET input
++ - wake-gpios: GPIO specification for the WAKE input
++
++ - pinctrl-names: should be "default"
++ - pinctrl-0: a phandle pointing to the pin settings for the
++ control gpios
++
++ - threshold: allows setting the "click"-threshold in the range
++ from 20 to 80.
++
++ - gain: allows setting the sensitivity in the range from 0 to
++ 31. Note that lower values indicate higher
++ sensitivity.
++
++ - offset: allows setting the edge compensation in the range from
++ 0 to 31.
++
++Example:
++ polytouch: edt-ft5x06@38 {
++ compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
++ reg = <0x38>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&edt_ft5x06_pins>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <5 0>;
++ reset-gpios = <&gpio2 6 1>;
++ wake-gpios = <&gpio4 9 0>;
++ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/leds/leds-gpio.txt linux-3.14.72/Documentation/devicetree/bindings/leds/leds-gpio.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/leds/leds-gpio.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/leds/leds-gpio.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -21,6 +21,8 @@
+ on). The "keep" setting will keep the LED at whatever its current
+ state is, without producing a glitch. The default is off if this
+ property is not present.
++- retain-state-suspended: (optional) The suspend state can be retained.Such
++ as charge-led gpio.
+
+ Examples:
+
+@@ -50,3 +52,13 @@
+ default-state = "on";
+ };
+ };
++
++leds {
++ compatible = "gpio-leds";
++
++ charger-led {
++ gpios = <&gpio1 2 0>;
++ linux,default-trigger = "max8903-charger-charging";
++ retain-state-suspended;
++ };
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/leds/leds-pwm.txt linux-3.14.72/Documentation/devicetree/bindings/leds/leds-pwm.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/leds/leds-pwm.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/leds/leds-pwm.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -17,6 +17,8 @@
+ see Documentation/devicetree/bindings/leds/common.txt
+ - linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
++- active-low : (optional)
++ Inverts the duty cycle to reflect a low-active output pin
+
+ Example:
+
+@@ -38,6 +40,7 @@
+ label = "omap4::keypad";
+ pwms = <&twl_pwm 0 7812500>;
+ max-brightness = <127>;
++ active-low;
+ };
+
+ charging {
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/mfd/syscon.txt linux-3.14.72/Documentation/devicetree/bindings/mfd/syscon.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/mfd/syscon.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/mfd/syscon.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -13,6 +13,9 @@
+ - compatible: Should contain "syscon".
+ - reg: the register region can be accessed from syscon
+
++Optional properties:
++- clocks: clock used for accessing the regmap
++
+ Examples:
+ gpr: iomuxc-gpr@020e0000 {
+ compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/mmc/mmc.txt linux-3.14.72/Documentation/devicetree/bindings/mmc/mmc.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/mmc/mmc.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/mmc/mmc.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -5,6 +5,8 @@
+ Interpreted by the OF core:
+ - reg: Registers location and length.
+ - interrupts: Interrupts used by the MMC controller.
++- clocks: Clocks needed for the host controller, if any.
++- clock-names: Goes with clocks above.
+
+ Card detection:
+ If no property below is supplied, host native card detect is used.
+@@ -30,6 +32,15 @@
+ - cap-sdio-irq: enable SDIO IRQ signalling on this interface
+ - full-pwr-cycle: full power cycle of the card is supported
+
++Card power and reset control:
++The following properties can be specified for cases where the MMC
++peripheral needs additional reset, regulator and clock lines. It is for
++example common for WiFi/BT adapters to have these separate from the main
++MMC bus:
++ - card-reset-gpios: Specify GPIOs for card reset (reset active low)
++ - card-external-vcc-supply: Regulator to drive (independent) card VCC
++ - clock with name "card_ext_clock": External clock provided to the card
++
+ *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
+ polarity properties, we have to fix the meaning of the "normal" and "inverted"
+ line levels. We choose to follow the SDHCI standard, which specifies both those
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt linux-3.14.72/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/mtd/fsl-quadspi.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,52 @@
++* Freescale Quad Serial Peripheral Interface(QuadSPI)
++
++The QuadSPI controller acts as the SPI master. It is described with a node
++for the controller and a set of child nodes for each SPI NOR flash.
++
++Part I - The DT node for the controller:
++------------------------------
++
++Required properties:
++ - compatible : Should be "fsl,vf610-qspi"
++ - reg : the first contains the register location and length,
++ the second contains the memory mapping address and length
++ - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
++ - interrupts : Should contain the interrupt for the device
++ - clocks : The clocks needed by the QuadSPI controller
++ - clock-names : the name of the clocks
++
++Optional properties:
++ - fsl,qspi-has-second-chip: The controller has two buses, bus A and bus B.
++ Each bus can be connected with two NOR flashes.
++ Most of the time, each bus only has one NOR flash
++ connected, this is the default case.
++ But if there are two NOR flashes connected to the
++ bus, you should enable this property.
++ (Please check the board's schematic.)
++ - ddrsmp: The value for DDR internal sampling point, range is 0 - 7.
++
++Part II - The DT nodes for each SPI NOR flash
++------------------------------
++Required properties:
++- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
++
++Optional properties:
++ Please refer to the Documentation/devicetree/bindings/mtd/spi-nor-flash.txt
++ If you set the "spi-nor,ddr-quad-read-dummy", it means you enable the DDR
++ quad read feature for the driver.
++
++Example:
++
++qspi0: quadspi@40044000 {
++ compatible = "fsl,vf610-qspi";
++ reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
++ reg-names = "QuadSPI", "QuadSPI-memory";
++ interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks VF610_CLK_QSPI0_EN>,
++ <&clks VF610_CLK_QSPI0>;
++ clock-names = "qspi_en", "qspi";
++
++ flash0: s25fl128s@0 {
++ ....
++ };
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt linux-3.14.72/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/mtd/spi-nor-flash.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,7 @@
++This file defines some DT properties for specific SPI NOR flash features.
++The SPI NOR controller drivers may refer to this file, such as fsl-quadspi.txt
++
++Optional properties:
++ - spi-nor,ddr-quad-read-dummy: The dummy cycles used by the DDR Quad read.
++ Please refer to the chip's datasheet. This
++ property can be 4 or 6 which is less then 8.
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt linux-3.14.72/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -15,8 +15,18 @@
+ Optional properties:
+
+ - clock-frequency : The oscillator frequency driving the flexcan device
+-
+ - xceiver-supply: Regulator that powers the CAN transceiver
++- stop-mode: register bits of stop mode control, the format is
++ <&gpr req_gpr req_bit ack_gpr ack_bit>.
++ gpr is the phandle to general purpose register node.
++ req_gpr is the gpr register offset of CAN stop request.
++ req_bit is the bit offset of CAN stop request.
++ ack_gpr is the gpr register offset of CAN stop acknowledge.
++ ack_bit is the bit offset of CAN stop acknowledge.
++- trx_en_gpio : enable gpio
++- trx_stby_gpio : standby gpio
++- trx_nerr_gpio : NERR gpio
++- trx_wakeup_gpio : local wakeup gpio
+
+ Example:
+
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/net/can/m_can.txt linux-3.14.72/Documentation/devicetree/bindings/net/can/m_can.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/net/can/m_can.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/net/can/m_can.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,29 @@
++Bosch MCAN controller Device Tree Bindings
++-------------------------------------------------
++
++Required properties:
++- compatible : Should be "bosch,m_can" for M_CAN controllers
++- reg : physical base address and size of the M_CAN
++ registers map and message ram
++- interrupts : property with a value describing the interrupt
++ number
++- clocks : clocks used by controller
++- mram-cfg : message ram configuration data, the format is
++ <offset sidf_elems xidf_elems rxf1_elems rxb_elems txe_elems txb_elems>
++ The 'offset' is the address offset inside the message ram. This is usually set
++ if you're using the shared message ram while the other part is used by another
++ m_can controller.
++ The left cell are all the number of each elements inside the message ram.
++ Please refer to 2.4.1 Message RAM Con.guration in Bosch M_CAN user mannual
++ for each elements definition.
++
++Example:
++canfd1: canfd@020e8000 {
++ compatible = "bosch,m_can";
++ reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
++ reg-names = "canfd", "message_ram";
++ interrupts = <0 114 0x04>;
++ clocks = <&clks IMX6SX_CLK_CANFD>;
++ mram-cfg = <0x0 0 0 32 32 32 0 1>;
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/net/fixed-link.txt linux-3.14.72/Documentation/devicetree/bindings/net/fixed-link.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/net/fixed-link.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/net/fixed-link.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,30 @@
++Fixed link Device Tree binding
++------------------------------
++
++Some Ethernet MACs have a "fixed link", and are not connected to a
++normal MDIO-managed PHY device. For those situations, a Device Tree
++binding allows to describe a "fixed link".
++
++Such a fixed link situation is described by creating a 'fixed-link'
++sub-node of the Ethernet MAC device node, with the following
++properties:
++
++* 'speed' (integer, mandatory), to indicate the link speed. Accepted
++ values are 10, 100 and 1000
++* 'full-duplex' (boolean, optional), to indicate that full duplex is
++ used. When absent, half duplex is assumed.
++* 'pause' (boolean, optional), to indicate that pause should be
++ enabled.
++* 'asym-pause' (boolean, optional), to indicate that asym_pause should
++ be enabled.
++
++Example:
++
++ethernet@0 {
++ ...
++ fixed-link {
++ speed = <1000>;
++ full-duplex;
++ };
++ ...
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/net/fsl-fec.txt linux-3.14.72/Documentation/devicetree/bindings/net/fsl-fec.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/net/fsl-fec.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/net/fsl-fec.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -15,7 +15,22 @@
+ only if property "phy-reset-gpios" is available. Missing the property
+ will have the duration be 1 millisecond. Numbers greater than 1000 are
+ invalid and 1 millisecond will be used instead.
+-- phy-supply: regulator that powers the Ethernet PHY.
++- phy-supply : regulator that powers the Ethernet PHY.
++- phy-handle : phandle to the PHY device connected to this device.
++- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
++ Use instead of phy-handle.
++- fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
++ hw multi queues. Should specify the tx queue number, otherwise set tx queue
++ number to 1.
++- fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
++ hw multi queues. Should specify the rx queue number, otherwise set rx queue
++ number to 1.
++- fsl,magic-packet : If present, indicates that the hardware supports waking
++ up via magic packet.
++
++Optional subnodes:
++- mdio : specifies the mdio bus in the FEC, used as a container for phy nodes
++ according to phy.txt in the same directory
+
+ Example:
+
+@@ -28,3 +43,23 @@
+ local-mac-address = [00 04 9F 01 1B B9];
+ phy-supply = <&reg_fec_supply>;
+ };
++
++Example with phy specified:
++
++ethernet@83fec000 {
++ compatible = "fsl,imx51-fec", "fsl,imx27-fec";
++ reg = <0x83fec000 0x4000>;
++ interrupts = <87>;
++ phy-mode = "mii";
++ phy-reset-gpios = <&gpio2 14 0>; /* GPIO2_14 */
++ local-mac-address = [00 04 9F 01 1B B9];
++ phy-supply = <&reg_fec_supply>;
++ phy-handle = <&ethphy>;
++ mdio {
++ ethphy: ethernet-phy@6 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <6>;
++ max-speed = <100>;
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pci/designware-pcie.txt linux-3.14.72/Documentation/devicetree/bindings/pci/designware-pcie.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pci/designware-pcie.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/pci/designware-pcie.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -1,15 +1,11 @@
+ * Synopsys Designware PCIe interface
+
+ Required properties:
+-- compatible: should contain "snps,dw-pcie" to identify the
+- core, plus an identifier for the specific instance, such
+- as "samsung,exynos5440-pcie" or "fsl,imx6q-pcie".
+-- reg: base addresses and lengths of the pcie controller,
+- the phy controller, additional register for the phy controller.
+-- interrupts: interrupt values for level interrupt,
+- pulse interrupt, special interrupt.
+-- clocks: from common clock binding: handle to pci clock.
+-- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
++- compatible: should contain "snps,dw-pcie" to identify the core.
++- reg: Should contain the configuration address space.
++- reg-names: Must be "config" for the PCIe configuration space.
++ (The old way of getting the configuration address space from "ranges"
++ is deprecated and should be avoided.)
+ - #address-cells: set to <3>
+ - #size-cells: set to <2>
+ - device_type: set to "pci"
+@@ -19,65 +15,14 @@
+ to define the mapping of the PCIe interface to interrupt
+ numbers.
+ - num-lanes: number of lanes to use
++- clocks: Must contain an entry for each entry in clock-names.
++ See ../clocks/clock-bindings.txt for details.
++- clock-names: Must include the following entries:
++ - "pcie"
++ - "pcie_bus"
+
+ Optional properties:
+ - reset-gpio: gpio pin number of power good signal
+-
+-Optional properties for fsl,imx6q-pcie
+-- power-on-gpio: gpio pin number of power-enable signal
+-- wake-up-gpio: gpio pin number of incoming wakeup signal
+-- disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal
+-
+-Example:
+-
+-SoC specific DT Entry:
+-
+- pcie@290000 {
+- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+- reg = <0x290000 0x1000
+- 0x270000 0x1000
+- 0x271000 0x40>;
+- interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+- clocks = <&clock 28>, <&clock 27>;
+- clock-names = "pcie", "pcie_bus";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- device_type = "pci";
+- ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
+- 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
+- 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+- #interrupt-cells = <1>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0x0 0 &gic 53>;
+- num-lanes = <4>;
+- };
+-
+- pcie@2a0000 {
+- compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+- reg = <0x2a0000 0x1000
+- 0x272000 0x1000
+- 0x271040 0x40>;
+- interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+- clocks = <&clock 29>, <&clock 27>;
+- clock-names = "pcie", "pcie_bus";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- device_type = "pci";
+- ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
+- 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
+- 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+- #interrupt-cells = <1>;
+- interrupt-map-mask = <0 0 0 0>;
+- interrupt-map = <0x0 0 &gic 56>;
+- num-lanes = <4>;
+- };
+-
+-Board specific DT Entry:
+-
+- pcie@290000 {
+- reset-gpio = <&pin_ctrl 5 0>;
+- };
+-
+- pcie@2a0000 {
+- reset-gpio = <&pin_ctrl 22 0>;
+- };
++- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
++ specify this property, to keep backwards compatibility a range of 0x00-0xff
++ is assumed if not present)
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt linux-3.14.72/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,44 @@
++* Freescale i.MX6 PCIe interface
++
++This PCIe host controller is based on the Synopsis Designware PCIe IP
++and thus inherits all the common properties defined in designware-pcie.txt.
++
++Required properties:
++- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie"
++- reg: base addresse and length of the pcie controller
++- interrupts: A list of interrupt outputs of the controller. Must contain an
++ entry for each entry in the interrupt-names property.
++- interrupt-names: Must include the following entries:
++ - "msi": The interrupt that is asserted when an MSI is received
++- clock-names: Must include the following additional entries:
++ - "pcie_phy"
++
++Additional required properties for imx6sx-pcie:
++- clock names: Must include the following additional entries:
++ - "pcie_inbound_axi"
++- power supplies:
++ - pcie-phy-supply: regulator used to power the PCIe PHY
++
++Example:
++
++ pcie@0x01000000 {
++ compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
++ reg = <0x01ffc000 0x4000>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
++ 0x81000000 0 0 0x01f80000 0 0x00010000
++ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
++ num-lanes = <1>;
++ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++ <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks 144>, <&clks 206>, <&clks 189>;
++ clock-names = "pcie", "pcie_bus", "pcie_phy";
++ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pci/host-generic-pci.txt linux-3.14.72/Documentation/devicetree/bindings/pci/host-generic-pci.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pci/host-generic-pci.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/pci/host-generic-pci.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,100 @@
++* Generic PCI host controller
++
++Firmware-initialised PCI host controllers and PCI emulations, such as the
++virtio-pci implementations found in kvmtool and other para-virtualised
++systems, do not require driver support for complexities such as regulator
++and clock management. In fact, the controller may not even require the
++configuration of a control interface by the operating system, instead
++presenting a set of fixed windows describing a subset of IO, Memory and
++Configuration Spaces.
++
++Such a controller can be described purely in terms of the standardized device
++tree bindings communicated in pci.txt:
++
++
++Properties of the host controller node:
++
++- compatible : Must be "pci-host-cam-generic" or "pci-host-ecam-generic"
++ depending on the layout of configuration space (CAM vs
++ ECAM respectively).
++
++- device_type : Must be "pci".
++
++- ranges : As described in IEEE Std 1275-1994, but must provide
++ at least a definition of non-prefetchable memory. One
++ or both of prefetchable Memory and IO Space may also
++ be provided.
++
++- bus-range : Optional property (also described in IEEE Std 1275-1994)
++ to indicate the range of bus numbers for this controller.
++ If absent, defaults to <0 255> (i.e. all buses).
++
++- #address-cells : Must be 3.
++
++- #size-cells : Must be 2.
++
++- reg : The Configuration Space base address and size, as accessed
++ from the parent bus.
++
++
++Properties of the /chosen node:
++
++- linux,pci-probe-only
++ : Optional property which takes a single-cell argument.
++ If '0', then Linux will assign devices in its usual manner,
++ otherwise it will not try to assign devices and instead use
++ them as they are configured already.
++
++Configuration Space is assumed to be memory-mapped (as opposed to being
++accessed via an ioport) and laid out with a direct correspondence to the
++geography of a PCI bus address by concatenating the various components to
++form an offset.
++
++For CAM, this 24-bit offset is:
++
++ cfg_offset(bus, device, function, register) =
++ bus << 16 | device << 11 | function << 8 | register
++
++Whilst ECAM extends this by 4 bits to accomodate 4k of function space:
++
++ cfg_offset(bus, device, function, register) =
++ bus << 20 | device << 15 | function << 12 | register
++
++Interrupt mapping is exactly as described in `Open Firmware Recommended
++Practice: Interrupt Mapping' and requires the following properties:
++
++- #interrupt-cells : Must be 1
++
++- interrupt-map : <see aforementioned specification>
++
++- interrupt-map-mask : <see aforementioned specification>
++
++
++Example:
++
++pci {
++ compatible = "pci-host-cam-generic"
++ device_type = "pci";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ bus-range = <0x0 0x1>;
++
++ // CPU_PHYSICAL(2) SIZE(2)
++ reg = <0x0 0x40000000 0x0 0x1000000>;
++
++ // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
++ ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
++ <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
++
++
++ #interrupt-cells = <0x1>;
++
++ // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3)
++ interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1
++ 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1
++ 0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1
++ 0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
++
++ // PCI_DEVICE(3) INT#(1)
++ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
++}
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt linux-3.14.72/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,65 @@
++* Samsung Exynos 5440 PCIe interface
++
++This PCIe host controller is based on the Synopsis Designware PCIe IP
++and thus inherits all the common properties defined in designware-pcie.txt.
++
++Required properties:
++- compatible: "samsung,exynos5440-pcie"
++- reg: base addresses and lengths of the pcie controller,
++ the phy controller, additional register for the phy controller.
++- interrupts: A list of interrupt outputs for level interrupt,
++ pulse interrupt, special interrupt.
++
++Example:
++
++SoC specific DT Entry:
++
++ pcie@290000 {
++ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
++ reg = <0x290000 0x1000
++ 0x270000 0x1000
++ 0x271000 0x40>;
++ interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
++ clocks = <&clock 28>, <&clock 27>;
++ clock-names = "pcie", "pcie_bus";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
++ 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
++ num-lanes = <4>;
++ };
++
++ pcie@2a0000 {
++ compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
++ reg = <0x2a0000 0x1000
++ 0x272000 0x1000
++ 0x271040 0x40>;
++ interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
++ clocks = <&clock 29>, <&clock 27>;
++ clock-names = "pcie", "pcie_bus";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
++ 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
++ 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0>;
++ interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
++ num-lanes = <4>;
++ };
++
++Board specific DT Entry:
++
++ pcie@290000 {
++ reset-gpio = <&pin_ctrl 5 0>;
++ };
++
++ pcie@2a0000 {
++ reset-gpio = <&pin_ctrl 22 0>;
++ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt linux-3.14.72/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/pci/spear13xx-pcie.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,14 @@
++SPEAr13XX PCIe DT detail:
++================================
++
++SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
++controller.
++
++Required properties:
++- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
++- phys : phandle to phy node associated with pcie controller
++- phy-names : must be "pcie-phy"
++- All other definitions as per generic PCI bindings
++
++ Optional properties:
++- st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pci/ti-pci.txt linux-3.14.72/Documentation/devicetree/bindings/pci/ti-pci.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pci/ti-pci.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/pci/ti-pci.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,59 @@
++TI PCI Controllers
++
++PCIe Designware Controller
++ - compatible: Should be "ti,dra7-pcie""
++ - reg : Two register ranges as listed in the reg-names property
++ - reg-names : The first entry must be "ti-conf" for the TI specific registers
++ The second entry must be "rc-dbics" for the designware pcie
++ registers
++ The third entry must be "config" for the PCIe configuration space
++ - phys : list of PHY specifiers (used by generic PHY framework)
++ - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
++ number of PHYs as specified in *phys* property.
++ - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
++ where <X> is the instance number of the pcie from the HW spec.
++ - interrupts : Two interrupt entries must be specified. The first one is for
++ main interrupt line and the second for MSI interrupt line.
++ - #address-cells,
++ #size-cells,
++ #interrupt-cells,
++ device_type,
++ ranges,
++ num-lanes,
++ interrupt-map-mask,
++ interrupt-map : as specified in ../designware-pcie.txt
++
++Example:
++axi {
++ compatible = "simple-bus";
++ #size-cells = <1>;
++ #address-cells = <1>;
++ ranges = <0x51000000 0x51000000 0x3000
++ 0x0 0x20000000 0x10000000>;
++ pcie@51000000 {
++ compatible = "ti,dra7-pcie";
++ reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
++ reg-names = "rc_dbics", "ti_conf", "config";
++ interrupts = <0 232 0x4>, <0 233 0x4>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++ device_type = "pci";
++ ranges = <0x81000000 0 0 0x03000 0 0x00010000
++ 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
++ #interrupt-cells = <1>;
++ num-lanes = <1>;
++ ti,hwmods = "pcie1";
++ phys = <&pcie1_phy>;
++ phy-names = "pcie-phy0";
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc 1>,
++ <0 0 0 2 &pcie_intc 2>,
++ <0 0 0 3 &pcie_intc 3>,
++ <0 0 0 4 &pcie_intc 4>;
++ pcie_intc: interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ };
++ };
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt linux-3.14.72/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,36 @@
++* Freescale i.MX6 SoloX IOMUX Controller
++
++Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
++and usage.
++
++Required properties:
++- compatible: "fsl,imx6sx-iomuxc"
++- fsl,pins: each entry consists of 6 integers and represents the mux and config
++ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
++ input_val> are specified using a PIN_FUNC_ID macro, which can be found in
++ imx6sx-pinfunc.h under device tree source folder. The last integer CONFIG is
++ the pad setting value like pull-up on this pin. Please refer to i.MX6 SoloX
++ Reference Manual for detailed CONFIG settings.
++
++CONFIG bits definition:
++PAD_CTL_HYS (1 << 16)
++PAD_CTL_PUS_100K_DOWN (0 << 14)
++PAD_CTL_PUS_47K_UP (1 << 14)
++PAD_CTL_PUS_100K_UP (2 << 14)
++PAD_CTL_PUS_22K_UP (3 << 14)
++PAD_CTL_PUE (1 << 13)
++PAD_CTL_PKE (1 << 12)
++PAD_CTL_ODE (1 << 11)
++PAD_CTL_SPEED_LOW (0 << 6)
++PAD_CTL_SPEED_MED (1 << 6)
++PAD_CTL_SPEED_HIGH (3 << 6)
++PAD_CTL_DSE_DISABLE (0 << 3)
++PAD_CTL_DSE_260ohm (1 << 3)
++PAD_CTL_DSE_130ohm (2 << 3)
++PAD_CTL_DSE_87ohm (3 << 3)
++PAD_CTL_DSE_65ohm (4 << 3)
++PAD_CTL_DSE_52ohm (5 << 3)
++PAD_CTL_DSE_43ohm (6 << 3)
++PAD_CTL_DSE_37ohm (7 << 3)
++PAD_CTL_SRE_FAST (1 << 0)
++PAD_CTL_SRE_SLOW (0 << 0)
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt linux-3.14.72/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -71,6 +71,13 @@
+ name for integer state ID 0, list entry 1 for state ID 1, and
+ so on.
+
++pinctrl-assert-gpios:
++ List of phandles, each pointing at a GPIO which is used by some
++ board design to steer pins between two peripherals on the board.
++ It plays like a board level pin multiplexer to choose different
++ functions for given pins by pulling up/down the GPIOs. See
++ bindings/gpio/gpio.txt for details of how to specify GPIO.
++
+ For example:
+
+ /* For a client device requiring named states */
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt linux-3.14.72/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,54 @@
++Freescale i.MX General Power Controller
++=======================================
++
++The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
++counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
++domains.
++
++Required properties:
++- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
++- reg: should be register base and length as documented in the
++ datasheet
++- interrupts: Should contain GPC interrupt request 1
++- pu-supply: Link to the LDO regulator powering the PU power domain
++- clocks: Clock phandles to devices in the PU power domain that need
++ to be enabled during domain power-up for reset propagation.
++- #power-domain-cells: Should be 1, see below:
++
++The gpc node is a power-controller as documented by the generic power domain
++bindings in Documentation/devicetree/bindings/power/power_domain.txt.
++
++Example:
++
++ gpc: gpc@020dc000 {
++ compatible = "fsl,imx6q-gpc";
++ reg = <0x020dc000 0x4000>;
++ interrupts = <0 89 0x04 0 90 0x04>;
++ pu-supply = <&reg_pu>;
++ clocks = <&clks 122>, <&clks 74>, <&clks 121>,
++ <&clks 26>, <&clks 143>, <&clks 168>;
++ #power-domain-cells = <1>;
++ };
++
++
++Specifying power domain for IP modules
++======================================
++
++IP cores belonging to a power domain should contain a 'power-domains' property
++that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
++the power domain the device belongs to.
++
++Example of a device that is part of the PU power domain:
++
++ vpu: vpu@02040000 {
++ reg = <0x02040000 0x3c000>;
++ /* ... */
++ power-domains = <&gpc 1>;
++ /* ... */
++ };
++
++The following DOMAIN_INDEX values are valid for i.MX6Q:
++ARM_DOMAIN 0
++PU_DOMAIN 1
++The following additional DOMAIN_INDEX value is valid for i.MX6SL:
++DISPLAY_DOMAIN 2
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/power/power_domain.txt linux-3.14.72/Documentation/devicetree/bindings/power/power_domain.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/power/power_domain.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/power/power_domain.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,49 @@
++* Generic PM domains
++
++System on chip designs are often divided into multiple PM domains that can be
++used for power gating of selected IP blocks for power saving by reduced leakage
++current.
++
++This device tree binding can be used to bind PM domain consumer devices with
++their PM domains provided by PM domain providers. A PM domain provider can be
++represented by any node in the device tree and can provide one or more PM
++domains. A consumer node can refer to the provider by a phandle and a set of
++phandle arguments (so called PM domain specifiers) of length specified by the
++#power-domain-cells property in the PM domain provider node.
++
++==PM domain providers==
++
++Required properties:
++ - #power-domain-cells : Number of cells in a PM domain specifier;
++ Typically 0 for nodes representing a single PM domain and 1 for nodes
++ providing multiple PM domains (e.g. power controllers), but can be any value
++ as specified by device tree binding documentation of particular provider.
++
++Example:
++
++ power: power-controller@12340000 {
++ compatible = "foo,power-controller";
++ reg = <0x12340000 0x1000>;
++ #power-domain-cells = <1>;
++ };
++
++The node above defines a power controller that is a PM domain provider and
++expects one cell as its phandle argument.
++
++==PM domain consumers==
++
++Required properties:
++ - power-domains : A phandle and PM domain specifier as defined by bindings of
++ the power controller specified by phandle.
++
++Example:
++
++ leaky-device@12350000 {
++ compatible = "foo,i-leak-current";
++ reg = <0x12350000 0x1000>;
++ power-domains = <&power 0>;
++ };
++
++The node above defines a typical PM domain consumer device, which is located
++inside a PM domain with index 0 of a power controller represented by a node
++with the label "power".
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/regulator/ltc3676.txt linux-3.14.72/Documentation/devicetree/bindings/regulator/ltc3676.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/regulator/ltc3676.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/regulator/ltc3676.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,103 @@
++Linear Technology LTC3676 8-output regulators
++
++Required properties:
++- compatible: "lltc,ltc3676"
++- reg: I2C slave address
++
++Required child node:
++- regulators: Contains eight regulator child nodes sw1, sw2, sw3, sw4,
++ ldo1, ldo2, ldo3, and ldo4, specifying the initialization data as
++ documented in Documentation/devicetree/bindings/regulator/regulator.txt.
++
++Each regulator is defined using the standard binding for regulators. The
++nodes for sw1, sw2, sw3, sw4, ldo1, ldo2 and ldo4 additionally need to specify
++the resistor values of their external feedback voltage dividers:
++
++Required properties (not on ldo3):
++- lltc,fb-voltage-divider: An array of two integers containing the resistor
++ values R1 and R2 of the feedback voltage divider in ohms.
++
++Regulators sw1, sw2, sw3, sw4 can regulate the feedback reference from:
++412.5mV to 800mV in 12.5 mV steps. The output voltage thus ranges between
++0.4125 * (1 + R1/R2) V and 0.8 * (1 + R1/R2) V.
++
++Regulators ldo1, ldo2, and ldo4 have a fixed 0.725 V reference and thus output
++0.725 * (1 + R1/R2) V. The ldo3 regulator is fixed to 1.8 V. The ldo1 standby
++regulator can not be disabled and thus should have the regulator-always-on
++property set.
++
++Example:
++
++ ltc3676: pmic@3c {
++ compatible = "lltc,ltc3676";
++ reg = <0x3c>;
++
++ regulators {
++ sw1_reg: sw1 {
++ regulator-min-microvolt = <674400>;
++ regulator-max-microvolt = <1308000>;
++ lltc,fb-voltage-divider = <127000 200000>;
++ regulator-ramp-delay = <7000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <1033310>;
++ regulator-max-microvolt = <200400>;
++ lltc,fb-voltage-divider = <301000 200000>;
++ regulator-ramp-delay = <7000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3_reg: sw3 {
++ regulator-min-microvolt = <674400>;
++ regulator-max-microvolt = <130800>;
++ lltc,fb-voltage-divider = <127000 200000>;
++ regulator-ramp-delay = <7000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw4_reg: sw4 {
++ regulator-min-microvolt = <868310>;
++ regulator-max-microvolt = <168400>;
++ lltc,fb-voltage-divider = <221000 200000>;
++ regulator-ramp-delay = <7000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ /* unused */
++ ldo1_reg: ldo1 {
++ regulator-min-microvolt = <0>;
++ regulator-max-microvolt = <0>;
++ lltc,fb-voltage-divider = <0 0>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ ldo2_reg: ldo2 {
++ regulator-min-microvolt = <2490375>;
++ regulator-max-microvolt = <2490375>;
++ lltc,fb-voltage-divider = <487000 200000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ ldo3_reg: ldo3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-boot-on;
++ };
++
++ ldo4_reg: ldo4 {
++ regulator-min-microvolt = <3023250>;
++ regulator-max-microvolt = <3023250>;
++ lltc,fb-voltage-divider = <634000 200000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++ };
++ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/regulator/pfuze100.txt linux-3.14.72/Documentation/devicetree/bindings/regulator/pfuze100.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/regulator/pfuze100.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/regulator/pfuze100.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -1,7 +1,7 @@
+ PFUZE100 family of regulators
+
+ Required properties:
+-- compatible: "fsl,pfuze100"
++- compatible: "fsl,pfuze100" or "fsl,pfuze200"
+ - reg: I2C slave address
+
+ Required child node:
+@@ -10,11 +10,14 @@
+ Documentation/devicetree/bindings/regulator/regulator.txt.
+
+ The valid names for regulators are:
++ --PFUZE100
+ sw1ab,sw1c,sw2,sw3a,sw3b,sw4,swbst,vsnvs,vrefddr,vgen1~vgen6
++ --PFUZE200
++ sw1ab,sw2,sw3a,sw3b,swbst,vsnvs,vrefddr,vgen1~vgen6
+
+ Each regulator is defined using the standard binding for regulators.
+
+-Example:
++Example 1: PFUZE100
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+@@ -63,6 +66,95 @@
+ };
+
+ swbst_reg: swbst {
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5150000>;
++ };
++
++ snvs_reg: vsnvs {
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <3000000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vref_reg: vrefddr {
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ vgen1_reg: vgen1 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen2_reg: vgen2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1550000>;
++ };
++
++ vgen3_reg: vgen3 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
++
++ vgen4_reg: vgen4 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen5_reg: vgen5 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ vgen6_reg: vgen6 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++ };
++ };
++
++
++Example 2: PFUZE200
++
++ pmic: pfuze200@08 {
++ compatible = "fsl,pfuze200";
++ reg = <0x08>;
++
++ regulators {
++ sw1a_reg: sw1ab {
++ regulator-min-microvolt = <300000>;
++ regulator-max-microvolt = <1875000>;
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-ramp-delay = <6250>;
++ };
++
++ sw2_reg: sw2 {
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3a_reg: sw3a {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ sw3b_reg: sw3b {
++ regulator-min-microvolt = <400000>;
++ regulator-max-microvolt = <1975000>;
++ regulator-boot-on;
++ regulator-always-on;
++ };
++
++ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/reset/gpio-reset.txt linux-3.14.72/Documentation/devicetree/bindings/reset/gpio-reset.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/reset/gpio-reset.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/reset/gpio-reset.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,35 @@
++GPIO reset controller
++=====================
++
++A GPIO reset controller controls a single GPIO that is connected to the reset
++pin of a peripheral IC. Please also refer to reset.txt in this directory for
++common reset controller binding usage.
++
++Required properties:
++- compatible: Should be "gpio-reset"
++- reset-gpios: A gpio used as reset line. The gpio specifier for this property
++ depends on the gpio controller that provides the gpio.
++- #reset-cells: 0, see below
++
++Optional properties:
++- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for
++ this duration to reset.
++- initially-in-reset: boolean. If not set, the initial state should be a
++ deasserted reset line. If this property exists, the
++ reset line should be kept in reset.
++
++example:
++
++sii902x_reset: gpio-reset {
++ compatible = "gpio-reset";
++ reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
++ reset-delay-us = <10000>;
++ initially-in-reset;
++ #reset-cells = <0>;
++};
++
++/* Device with nRESET pin connected to GPIO5_0 */
++sii902x@39 {
++ /* ... */
++ resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt linux-3.14.72/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/rtc/nxp,pcf8523.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,14 @@
++NXP Semiconductors PCF8523 Real Time Clock
++
++Required properties:
++- compatible: should be: "nxp,pcf8523"
++- reg: i2c address
++- nxp,12p5_pf: force autodetection to start at 12.5 pf instead of 7pf
++
++Example:
++
++rtc: pcf8523@68 {
++ compatible = "nxp,pcf8523";
++ reg = <0x68>;
++ nxp,12p5_pf;
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/cs42xx8.txt linux-3.14.72/Documentation/devicetree/bindings/sound/cs42xx8.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/cs42xx8.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/cs42xx8.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,28 @@
++CS42448/CS42888 audio CODEC
++
++Required properties:
++
++ - compatible : must contain one of "cirrus,cs42448" and "cirrus,cs42888"
++
++ - reg : the I2C address of the device for I2C
++
++ - clocks : a list of phandles + clock-specifiers, one for each entry in
++ clock-names
++
++ - clock-names : must contain "mclk"
++
++ - VA-supply, VD-supply, VLS-supply, VLC-supply: power supplies for the device,
++ as covered in Documentation/devicetree/bindings/regulator/regulator.txt
++
++Example:
++
++codec: cs42888@48 {
++ compatible = "cirrus,cs42888";
++ reg = <0x48>;
++ clocks = <&codec_mclk 0>;
++ clock-names = "mclk";
++ VA-supply = <&reg_audio>;
++ VD-supply = <&reg_audio>;
++ VLS-supply = <&reg_audio>;
++ VLC-supply = <&reg_audio>;
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,asrc.txt linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,asrc.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,asrc.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,asrc.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,60 @@
++Freescale Asynchronous Sample Rate Converter (ASRC) Controller
++
++The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a
++signal associated with an input clock into a signal associated with a different
++output clock. The driver currently works as a Front End of DPCM with other Back
++Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support
++three substreams within totally 10 channels.
++
++Required properties:
++
++ - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc".
++
++ - reg : Offset and length of the register set for the device.
++
++ - interrupts : Contains the spdif interrupt.
++
++ - dmas : Generic dma devicetree binding as described in
++ Documentation/devicetree/bindings/dma/dma.txt.
++
++ - dma-names : Contains "rxa", "rxb", "rxc", "txa", "txb" and "txc".
++
++ - clocks : Contains an entry for each entry in clock-names.
++
++ - clock-names : Contains the following entries
++ "mem" Peripheral access clock to access registers.
++ "ipg" Peripheral clock to driver module.
++ "asrck_<0-f>" Clock sources for input and output clock.
++
++ - big-endian : If this property is absent, the little endian mode
++ will be in use as default. Otherwise, the big endian
++ mode will be in use for all the device registers.
++
++ - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends.
++
++ - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends.
++
++Example:
++
++asrc: asrc@02034000 {
++ compatible = "fsl,imx53-asrc";
++ reg = <0x02034000 0x4000>;
++ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks 107>, <&clks 107>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
++ <&clks 107>, <&clks 0>, <&clks 0>;
++ clock-names = "mem", "ipg", "asrck0",
++ "asrck_1", "asrck_2", "asrck_3", "asrck_4",
++ "asrck_5", "asrck_6", "asrck_7", "asrck_8",
++ "asrck_9", "asrck_a", "asrck_b", "asrck_c",
++ "asrck_d", "asrck_e", "asrck_f";
++ dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
++ <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
++ dma-names = "rxa", "rxb", "rxc",
++ "txa", "txb", "txc";
++ fsl,asrc-rate = <48000>;
++ fsl,asrc-width = <16>;
++ status = "okay";
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,esai.txt linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,esai.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,esai.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,esai.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -34,6 +34,10 @@
+ that ESAI would work in the synchronous mode, which means all the settings
+ for Receiving would be duplicated from Transmition related registers.
+
++ - big-endian : If this property is absent, the native endian mode will
++ be in use as default, or the big endian mode will be in use for all the
++ device registers.
++
+ Example:
+
+ esai: esai@02024000 {
+@@ -46,5 +50,6 @@
+ dma-names = "rx", "tx";
+ fsl,fifo-depth = <128>;
+ fsl,esai-synchronous;
++ big-endian;
+ status = "disabled";
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,mqs.txt linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,mqs.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,mqs.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,mqs.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,22 @@
++fsl,mqs audio CODEC
++
++Required properties:
++
++ - compatible : must contain one of "fsl,imx6sx-mqs" and "fsl,codec-mqs"
++
++ - clocks : a list of phandles + clock-specifiers, one for each entry in
++ clock-names
++
++ - clock-names : must contain "mclk"
++
++ - gpr : the gpr node.
++
++Example:
++
++mqs: mqs {
++ compatible = "fsl,imx6sx-mqs";
++ gpr = <&gpr>;
++ clocks = <&clks IMX6SX_CLK_SAI1>;
++ clock-names = "mclk";
++ status = "disabled";
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl-sai.txt linux-3.14.72/Documentation/devicetree/bindings/sound/fsl-sai.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl-sai.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/fsl-sai.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -7,22 +7,37 @@
+
+
+ Required properties:
+-- compatible: Compatible list, contains "fsl,vf610-sai".
++- compatible: Compatible list, contains "fsl,vf610-sai" or "fsl,imx6sx-sai".
+ - reg: Offset and length of the register set for the device.
+ - clocks: Must contain an entry for each entry in clock-names.
+-- clock-names : Must include the "sai" entry.
++- clock-names : Must include the "bus" for register access and "mclk1" "mclk2"
++ "mclk3" for bit clock and frame clock providing.
+ - dmas : Generic dma devicetree binding as described in
+ Documentation/devicetree/bindings/dma/dma.txt.
+ - dma-names : Two dmas have to be defined, "tx" and "rx".
+ - pinctrl-names: Must contain a "default" entry.
+ - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
+ See ../pinctrl/pinctrl-bindings.txt for details of the property values.
+-- big-endian-regs: If this property is absent, the little endian mode will
+- be in use as default, or the big endian mode will be in use for all the
+- device registers.
+-- big-endian-data: If this property is absent, the little endian mode will
+- be in use as default, or the big endian mode will be in use for all the
+- fifo data.
++- big-endian: Boolean property, required if all the FTM_PWM registers
++ are big-endian rather than little-endian.
++- lsb-first: Configures whether the LSB or the MSB is transmitted first for
++ the fifo data. If this property is absent, the MSB is transmitted first as
++ default, or the LSB is transmitted first.
++- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
++ that SAI will work in the synchronous mode (sync Tx with Rx) which means
++ both the transimitter and receiver will send and receive data by following
++ receiver's bit clocks and frame sync clocks.
++- fsl,sai-asynchronous: This is a boolean property. If present, indicating
++ that SAI will work in the asynchronous mode, which means both transimitter
++ and receiver will send and receive data by following their own bit clocks
++ and frame sync clocks separately.
++
++Note:
++- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
++ default synchronous mode (sync Rx with Tx) will be used, which means both
++ transimitter and receiver will send and receive data by following clocks
++ of transimitter.
++- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
+
+ Example:
+ sai2: sai@40031000 {
+@@ -30,11 +45,13 @@
+ reg = <0x40031000 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2_1>;
+- clocks = <&clks VF610_CLK_SAI2>;
+- clock-names = "sai";
++ clocks = <&clks VF610_CLK_PLATFORM_BUS>,
++ <&clks VF610_CLK_SAI2>,
++ <&clks 0>, <&clks 0>;
++ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dma-names = "tx", "rx";
+ dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
+ <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
+- big-endian-regs;
+- big-endian-data;
++ big-endian;
++ lsb-first;
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,spdif.txt linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,spdif.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/fsl,spdif.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/fsl,spdif.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -29,6 +29,10 @@
+ can also be referred to TxClk_Source
+ bit of register SPDIF_STC.
+
++ - big-endian : If this property is absent, the native endian mode will
++ be in use as default, or the big endian mode will be in use for all the
++ device registers.
++
+ Example:
+
+ spdif: spdif@02004000 {
+@@ -50,5 +54,6 @@
+ "rxtx5", "rxtx6",
+ "rxtx7";
+
++ big-endian;
+ status = "okay";
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,25 @@
++Freescale i.MX audio complex with CS42888 codec
++
++Required properties:
++- compatible : "fsl,imx-audio-cs42888"
++- model : The user-visible name of this sound complex
++- esai-controller : The phandle of the i.MX SSI controller
++- audio-codec : The phandle of the CS42888 audio codec
++
++Optional properties:
++- asrc-controller : The phandle of the i.MX ASRC controller
++- audio-routing : A list of the connections between audio components.
++ Each entry is a pair of strings, the first being the connection's sink,
++ the second being the connection's source. Valid names could be power
++ supplies, CS42888 pins, and the jacks on the board:
++
++Example:
++
++sound {
++ compatible = "fsl,imx6q-sabresd-wm8962",
++ "fsl,imx-audio-wm8962";
++ model = "cs42888-audio";
++ esai-controller = <&esai>;
++ asrc-controller = <&asrc_p2p>;
++ audio-codec = <&codec>;
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,18 @@
++Freescale i.MX audio complex with mqs codec
++
++Required properties:
++- compatible : "fsl,imx-audio-mqs"
++- model : The user-visible name of this sound complex
++- cpu-dai : The phandle of the i.MX sai controller
++- audio-codec : The phandle of the mqs audio codec
++
++Example:
++
++sound-mqs {
++ compatible = "fsl,imx6sx-sdb-mqs",
++ "fsl,imx-audio-mqs";
++ model = "mqs-audio";
++ cpu-dai = <&sai1>;
++ audio-codec = <&mqs>;
++};
++
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -3,7 +3,7 @@
+ Required properties:
+ - compatible : "fsl,imx-audio-sgtl5000"
+ - model : The user-visible name of this sound complex
+-- ssi-controller : The phandle of the i.MX SSI controller
++- cpu-dai : The phandle of CPU dai
+ - audio-codec : The phandle of the SGTL5000 audio codec
+ - audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+@@ -38,7 +38,7 @@
+ compatible = "fsl,imx51-babbage-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx51-babbage-sgtl5000";
+- ssi-controller = <&ssi1>;
++ cpu-dai = <&ssi1>;
+ audio-codec = <&sgtl5000>;
+ audio-routing =
+ "MIC_IN", "Mic Jack",
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -0,0 +1,24 @@
++Freescale i.MX audio complex with si476x codec
++
++Required properties:
++- compatible : "fsl,imx-audio-si476x"
++- model : The user-visible name of this sound complex
++- ssi-controller : The phandle of the i.MX SSI controller
++
++- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
++- mux-ext-port : The external port of the i.MX audio muxer
++
++Note: The AUDMUX port numbering should start at 1, which is consistent with
++hardware manual.
++
++Example:
++
++sound {
++ compatible = "fsl,imx-audio-si476x",
++ "fsl,imx-tuner-si476x";
++ model = "imx-radio-si476x";
++
++ ssi-controller = <&ssi1>;
++ mux-int-port = <2>;
++ mux-ext-port = <5>;
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt 2016-06-19 22:11:55.077154974 +0200
+@@ -3,7 +3,7 @@
+ Required properties:
+ - compatible : "fsl,imx-audio-wm8962"
+ - model : The user-visible name of this sound complex
+-- ssi-controller : The phandle of the i.MX SSI controller
++- cpu-dai : The phandle of CPU DAI
+ - audio-codec : The phandle of the WM8962 audio codec
+ - audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+@@ -24,13 +24,19 @@
+ Note: The AUDMUX port numbering should start at 1, which is consistent with
+ hardware manual.
+
++Optional properties:
++- hp-det-gpios : The gpio pin to detect plug in/out event that happens to
++ Headphone jack.
++- mic-det-gpios: The gpio pin to detect plug in/out event that happens to
++ Microphone jack.
++
+ Example:
+
+ sound {
+ compatible = "fsl,imx6q-sabresd-wm8962",
+ "fsl,imx-audio-wm8962";
+ model = "wm8962-audio";
+- ssi-controller = <&ssi2>;
++ cpu-dai = <&ssi2>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "Headphone Jack", "HPOUTL",
+@@ -43,4 +49,6 @@
+ "DMICDAT", "DMIC";
+ mux-int-port = <2>;
+ mux-ext-port = <3>;
++ hp-det-gpios = <&gpio7 8 1>;
++ mic-det-gpios = <&gpio1 9 1>;
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/wm8960.txt linux-3.14.72/Documentation/devicetree/bindings/sound/wm8960.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/wm8960.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/wm8960.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -0,0 +1,31 @@
++WM8960 audio CODEC
++
++This device supports I2C only.
++
++Required properties:
++
++ - compatible : "wlf,wm8960"
++
++ - reg : the I2C address of the device.
++
++Optional properties:
++ - wlf,shared-lrclk: This is a boolean property. If present, the LRCM bit of
++ R24 (Additional control 2) gets set, indicating that ADCLRC and DACLRC pins
++ will be disabled only when ADC (Left and Right) and DAC (Left and Right)
++ are disabled.
++ When wm8960 works on synchronize mode and DACLRC pin is used to supply
++ frame clock, it will no frame clock for captrue unless enable DAC to enable
++ DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue.
++
++ - wlf,capless: This is a boolean property. If present, OUT3 pin will be
++ enabled and disabled together with HP_L and HP_R pins in response to jack
++ detect events.
++
++Example:
++
++codec: wm8960@1a {
++ compatible = "wlf,wm8960";
++ reg = <0x1a>;
++
++ wlf,shared-lrclk;
++};
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/sound/wm8962.txt linux-3.14.72/Documentation/devicetree/bindings/sound/wm8962.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/sound/wm8962.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/sound/wm8962.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -13,6 +13,14 @@
+ of R51 (Class D Control 2) gets set, indicating that the speaker is
+ in mono mode.
+
++ - amic-mono: This is a boolean property. If present, indicating that the
++ analog micphone is hardware mono input, the driver would enable monomix
++ for it.
++
++ - dmic-mono: This is a boolean property. If present, indicating that the
++ digital micphone is hardware mono input, the driver would enable monomix
++ for it.
++
+ - mic-cfg : Default register value for R48 (Additional Control 4).
+ If absent, the default should be the register default.
+
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt linux-3.14.72/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -7,6 +7,9 @@
+ - interrupts : Should contain CSPI/eCSPI interrupt
+ - fsl,spi-num-chipselects : Contains the number of the chipselect
+ - cs-gpios : Specifies the gpio pins to be used for chipselects.
++- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
++ Documentation/devicetree/bindings/dma/dma.txt
++- dma-names: DMA request names should include "tx" and "rx" if present.
+
+ Example:
+
+@@ -19,4 +22,6 @@
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
+ <&gpio3 25 0>; /* GPIO3_25 */
++ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
++ dma-names = "rx", "tx";
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/spi/spi-bus.txt linux-3.14.72/Documentation/devicetree/bindings/spi/spi-bus.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/spi/spi-bus.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/spi/spi-bus.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -55,6 +55,8 @@
+ chip select active high
+ - spi-3wire - (optional) Empty property indicating device requires
+ 3-wire mode.
++- spi-lsb-first - (optional) Empty property indicating device requires
++ LSB first mode.
+ - spi-tx-bus-width - (optional) The bus width(number of data wires) that
+ used for MOSI. Defaults to 1 if not present.
+ - spi-rx-bus-width - (optional) The bus width(number of data wires) that
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt linux-3.14.72/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -4,6 +4,7 @@
+ - compatible: Should be "fsl,imx27-usb"
+ - reg: Should contain registers location and length
+ - interrupts: Should contain controller interrupt
++- fsl,usbphy: phandle of usb phy that connects to the port
+
+ Recommended properies:
+ - phy_type: the type of the phy connected to the core. Should be one
+@@ -12,12 +13,25 @@
+ - dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
+
+ Optional properties:
+-- fsl,usbphy: phandler of usb phy that connects to the only one port
+ - fsl,usbmisc: phandler of non-core register device, with one argument
+ that indicate usb controller index
+ - vbus-supply: regulator for vbus
+ - disable-over-current: disable over current detect
+ - external-vbus-divider: enables off-chip resistor divider for Vbus
++- imx6-usb-charger-detection: enable imx6 usb charger detect function,
++ only set it when the user wants SoC usb charger detection capabilities.
++ If the user wants to use charger IC's usb charger detection capabilities,
++ please do not set it.
++- fsl,anatop: phandle for anatop module, anatop module is only existed
++ at imx6 SoC series.
++- pinctrl-names: for names of hsic pin group
++- pinctrl-0: hsic "idle" pin group
++- pinctrl-1: hsic "active" pin group
++- osc-clkgate-delay: the delay between powering up the xtal 24MHz clock
++ and release the clock to the digital logic inside the analog block,
++ 0 <= osc-clkgate-delay <= 7.
++- maximum-speed: limit the maximum connection speed to "full-speed".
++- tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts
+
+ Examples:
+ usb@02184000 { /* USB OTG */
+@@ -28,4 +42,12 @@
+ fsl,usbmisc = <&usbmisc 0>;
+ disable-over-current;
+ external-vbus-divider;
++ imx6-usb-charger-detection;
++ fsl,anatop = <&anatop>;
++ pinctrl-names = "idle", "active";
++ pinctrl-0 = <&pinctrl_usbh2_1>;
++ pinctrl-1 = <&pinctrl_usbh2_2>;
++ osc-clkgate-delay = <0x3>;
++ maximum-speed = "full-speed";
++ tpl-support;
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/usb/mxs-phy.txt linux-3.14.72/Documentation/devicetree/bindings/usb/mxs-phy.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/usb/mxs-phy.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/usb/mxs-phy.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -1,13 +1,21 @@
+ * Freescale MXS USB Phy Device
+
+ Required properties:
+-- compatible: Should be "fsl,imx23-usbphy"
++- compatible: should contain:
++ * "fsl,imx23-usbphy" for imx23 and imx28
++ * "fsl,imx6q-usbphy" for imx6dq and imx6dl
++ * "fsl,imx6sl-usbphy" for imx6sl
++ * "fsl,vf610-usbphy" for Vybrid vf610
++ * "fsl,imx6sx-usbphy" for imx6sx
++ "fsl,imx23-usbphy" is still a fallback for other strings
+ - reg: Should contain registers location and length
+ - interrupts: Should contain phy interrupt
++- fsl,anatop: phandle for anatop register, it is only for imx6 SoC series
+
+ Example:
+ usbphy1: usbphy@020c9000 {
+ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
+ reg = <0x020c9000 0x1000>;
+ interrupts = <0 44 0x04>;
++ fsl,anatop = <&anatop>;
+ };
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/usb/usbmisc-imx.txt linux-3.14.72/Documentation/devicetree/bindings/usb/usbmisc-imx.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/usb/usbmisc-imx.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/usb/usbmisc-imx.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -4,6 +4,8 @@
+ - #index-cells: Cells used to descibe usb controller index. Should be <1>
+ - compatible: Should be one of below:
+ "fsl,imx6q-usbmisc" for imx6q
++ "fsl,vf610-usbmisc" for Vybrid vf610
++ "fsl,imx6sx-usbmisc" for imx6sx
+ - reg: Should contain registers location and length
+
+ Examples:
+diff -Nur linux-3.14.72.orig/Documentation/devicetree/bindings/vendor-prefixes.txt linux-3.14.72/Documentation/devicetree/bindings/vendor-prefixes.txt
+--- linux-3.14.72.orig/Documentation/devicetree/bindings/vendor-prefixes.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/devicetree/bindings/vendor-prefixes.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -22,6 +22,7 @@
+ capella Capella Microsystems, Inc
+ cavium Cavium, Inc.
+ cdns Cadence Design Systems Inc.
++chipidea Chipidea, Inc
+ chrp Common Hardware Reference Platform
+ chunghwa Chunghwa Picture Tubes Ltd.
+ cirrus Cirrus Logic, Inc.
+@@ -29,6 +30,7 @@
+ dallas Maxim Integrated Products (formerly Dallas Semiconductor)
+ davicom DAVICOM Semiconductor, Inc.
+ denx Denx Software Engineering
++eeti EGalax_eMPIA Technology, Inc.
+ edt Emerging Display Technologies
+ emmicro EM Microelectronic
+ epfl Ecole Polytechnique Fédérale de Lausanne
+diff -Nur linux-3.14.72.orig/Documentation/DocBook/media/v4l/subdev-formats.xml linux-3.14.72/Documentation/DocBook/media/v4l/subdev-formats.xml
+--- linux-3.14.72.orig/Documentation/DocBook/media/v4l/subdev-formats.xml 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/DocBook/media/v4l/subdev-formats.xml 2016-06-19 22:11:55.081154709 +0200
+@@ -1898,6 +1898,134 @@
+ <entry>y<subscript>1</subscript></entry>
+ <entry>y<subscript>0</subscript></entry>
+ </row>
++ <row id="V4L2-MBUS-FMT-UYVY10-2X10">
++ <entry>V4L2_MBUS_FMT_UYVY10_2X10</entry>
++ <entry>0x2018</entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-VYUY10-2X10">
++ <entry>V4L2_MBUS_FMT_VYUY10_2X10</entry>
++ <entry>0x2019</entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-22;
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
+ <row id="V4L2-MBUS-FMT-YUYV10-2X10">
+ <entry>V4L2_MBUS_FMT_YUYV10_2X10</entry>
+ <entry>0x200b</entry>
+@@ -2308,6 +2436,110 @@
+ <entry>v<subscript>1</subscript></entry>
+ <entry>v<subscript>0</subscript></entry>
+ </row>
++ <row id="V4L2-MBUS-FMT-UYVY10-1X20">
++ <entry>V4L2_MBUS_FMT_UYVY10_1X20</entry>
++ <entry>0x201a</entry>
++ <entry></entry>
++ &dash-ent-12;
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-12;
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-VYUY10-1X20">
++ <entry>V4L2_MBUS_FMT_VYUY10_1X20</entry>
++ <entry>0x201b</entry>
++ <entry></entry>
++ &dash-ent-12;
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-12;
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
+ <row id="V4L2-MBUS-FMT-YUYV10-1X20">
+ <entry>V4L2_MBUS_FMT_YUYV10_1X20</entry>
+ <entry>0x200d</entry>
+@@ -2486,6 +2718,534 @@
+ <entry>v<subscript>1</subscript></entry>
+ <entry>v<subscript>0</subscript></entry>
+ </row>
++ <row id="V4L2-MBUS-FMT-UYVY12-2X12">
++ <entry>V4L2_MBUS_FMT_UYVY12_2X12</entry>
++ <entry>0x201c</entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-VYUY12-2X12">
++ <entry>V4L2_MBUS_FMT_VYUY12_2X12</entry>
++ <entry>0x201d</entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-YUYV12-2X12">
++ <entry>V4L2_MBUS_FMT_YUYV12_2X12</entry>
++ <entry>0x201e</entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-YVYU12-2X12">
++ <entry>V4L2_MBUS_FMT_YVYU12_2X12</entry>
++ <entry>0x201f</entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-20;
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-UYVY12-1X24">
++ <entry>V4L2_MBUS_FMT_UYVY12_1X24</entry>
++ <entry>0x2020</entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-VYUY12-1X24">
++ <entry>V4L2_MBUS_FMT_VYUY12_1X24</entry>
++ <entry>0x2021</entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-YUYV12-1X24">
++ <entry>V4L2_MBUS_FMT_YUYV12_1X24</entry>
++ <entry>0x2022</entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row id="V4L2-MBUS-FMT-YVYU12-1X24">
++ <entry>V4L2_MBUS_FMT_YVYU12_1X24</entry>
++ <entry>0x2023</entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ <entry>v<subscript>11</subscript></entry>
++ <entry>v<subscript>10</subscript></entry>
++ <entry>v<subscript>9</subscript></entry>
++ <entry>v<subscript>8</subscript></entry>
++ <entry>v<subscript>7</subscript></entry>
++ <entry>v<subscript>6</subscript></entry>
++ <entry>v<subscript>5</subscript></entry>
++ <entry>v<subscript>4</subscript></entry>
++ <entry>v<subscript>3</subscript></entry>
++ <entry>v<subscript>2</subscript></entry>
++ <entry>v<subscript>1</subscript></entry>
++ <entry>v<subscript>0</subscript></entry>
++ </row>
++ <row>
++ <entry></entry>
++ <entry></entry>
++ <entry></entry>
++ &dash-ent-8;
++ <entry>y<subscript>11</subscript></entry>
++ <entry>y<subscript>10</subscript></entry>
++ <entry>y<subscript>9</subscript></entry>
++ <entry>y<subscript>8</subscript></entry>
++ <entry>y<subscript>7</subscript></entry>
++ <entry>y<subscript>6</subscript></entry>
++ <entry>y<subscript>5</subscript></entry>
++ <entry>y<subscript>4</subscript></entry>
++ <entry>y<subscript>3</subscript></entry>
++ <entry>y<subscript>2</subscript></entry>
++ <entry>y<subscript>1</subscript></entry>
++ <entry>y<subscript>0</subscript></entry>
++ <entry>u<subscript>11</subscript></entry>
++ <entry>u<subscript>10</subscript></entry>
++ <entry>u<subscript>9</subscript></entry>
++ <entry>u<subscript>8</subscript></entry>
++ <entry>u<subscript>7</subscript></entry>
++ <entry>u<subscript>6</subscript></entry>
++ <entry>u<subscript>5</subscript></entry>
++ <entry>u<subscript>4</subscript></entry>
++ <entry>u<subscript>3</subscript></entry>
++ <entry>u<subscript>2</subscript></entry>
++ <entry>u<subscript>1</subscript></entry>
++ <entry>u<subscript>0</subscript></entry>
++ </row>
+ </tbody>
+ </tgroup>
+ </table>
+diff -Nur linux-3.14.72.orig/Documentation/kernel-parameters.txt linux-3.14.72/Documentation/kernel-parameters.txt
+--- linux-3.14.72.orig/Documentation/kernel-parameters.txt 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/Documentation/kernel-parameters.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -603,8 +603,11 @@
+ Also note the kernel might malfunction if you disable
+ some critical bits.
+
+- cma=nn[MG] [ARM,KNL]
+- Sets the size of kernel global memory area for contiguous
++ cma=nn[MG]@[start[MG][-end[MG]]]
++ [ARM,X86,KNL]
++ Sets the size of kernel global memory area for
++ contiguous memory allocations and optionally the
++ placement constraint by the physical address range of
+ memory allocations. For more information, see
+ include/linux/dma-contiguous.h
+
+@@ -2538,6 +2541,13 @@
+
+ pcmv= [HW,PCMCIA] BadgePAD 4
+
++ pd_ignore_unused
++ [PM]
++ Keep all power-domains already enabled by bootloader on,
++ even if no driver has claimed them. This is useful
++ for debug and development, but should not be
++ needed on a platform with proper driver support.
++
+ pd. [PARIDE]
+ See Documentation/blockdev/paride.txt.
+
+diff -Nur linux-3.14.72.orig/Documentation/mtd/spi-nor.txt linux-3.14.72/Documentation/mtd/spi-nor.txt
+--- linux-3.14.72.orig/Documentation/mtd/spi-nor.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/mtd/spi-nor.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -0,0 +1,62 @@
++ SPI NOR framework
++ ============================================
++
++Part I - Why do we need this framework?
++---------------------------------------
++
++SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
++controller operates agnostic of the specific device attached. However, some
++controllers (such as Freescale's QuadSPI controller) cannot easily handle
++arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
++
++In particular, Freescale's QuadSPI controller must know the NOR commands to
++find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
++opcodes, addresses, or data payloads; a SPI controller simply knows to send or
++receive bytes (Tx and Rx). Therefore, we must define a new layering scheme under
++which the controller driver is aware of the opcodes, addressing, and other
++details of the SPI NOR protocol.
++
++Part II - How does the framework work?
++--------------------------------------
++
++This framework just adds a new layer between the MTD and the SPI bus driver.
++With this new layer, the SPI NOR controller driver does not depend on the
++m25p80 code anymore.
++
++ Before this framework, the layer is like:
++
++ MTD
++ ------------------------
++ m25p80
++ ------------------------
++ SPI bus driver
++ ------------------------
++ SPI NOR chip
++
++ After this framework, the layer is like:
++ MTD
++ ------------------------
++ SPI NOR framework
++ ------------------------
++ m25p80
++ ------------------------
++ SPI bus driver
++ ------------------------
++ SPI NOR chip
++
++ With the SPI NOR controller driver (Freescale QuadSPI), it looks like:
++ MTD
++ ------------------------
++ SPI NOR framework
++ ------------------------
++ fsl-quadSPI
++ ------------------------
++ SPI NOR chip
++
++Part III - How can drivers use the framework?
++---------------------------------------------
++
++The main API is spi_nor_scan(). Before you call the hook, a driver should
++initialize the necessary fields for spi_nor{}. Please see
++drivers/mtd/spi-nor/spi-nor.c for detail. Please also refer to fsl-quadspi.c
++when you want to write a new driver for a SPI NOR controller.
+diff -Nur linux-3.14.72.orig/Documentation/tda1997x linux-3.14.72/Documentation/tda1997x
+--- linux-3.14.72.orig/Documentation/tda1997x 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/tda1997x 2016-06-19 22:11:55.081154709 +0200
+@@ -0,0 +1,31 @@
++The NXP TDA19971/19972 are HDMI receiver devices that decode HDMI
++input signals and present a configurable parallel video output bus and
++audio output bus. The internal video bus is 36bits while the output bus
++differs per device. These devices offer High Definition (HD) video resolutions
++up to 1080p50/60 or WUXGA and HD audio formats up to 8 channels such as DTS HD
++and Dolby True HD. The chips optionally include an HDCP 1.4 engine with
++pre-programmed keys stored into an internal NV memory. Additionally the chips
++also supports several HDMI 1.4b options such as 3D formats up to 1080p50/60,
++Deep Colors up to 36bpp and extended colorimetry.
++
++The TDA19971 has one HDMI input (HDMI-A) and 24bit output bus and the TDA19972
++has two HDMI inputs (HDMI-A/B) and a 36bit video output bus.
++
++Driver Details:
++---------------
++
++The chips respond to two i2c slave addresses, the first allows access to
++HDMI input, audio, and video status and configuration and the second allows
++access to CEC.
++
++The tda1997x-core driver attaches to the i2c slave that controls the device.
++It also manages the 2nd i2c slave for CEC. The platform data structure
++provides details about the desired video output bus configuration and the
++desired audio output bus configuration. An ASoC codec driver is also provided
++however this is merely a skeleton driver as the audio output format cannot
++be changed and is dependent upon the HDMI input signal. A separate platform
++specific device video driver can interact with the core to obtain information
++about the video data format which is dependent upon the HDMI input signal. A
++separate platform specific ASoC SoC DAI driver can interact with the core
++to obtain information about the audio data format which is dependent upon
++the HDMI input signal.
+diff -Nur linux-3.14.72.orig/Documentation/usb/chipidea.txt linux-3.14.72/Documentation/usb/chipidea.txt
+--- linux-3.14.72.orig/Documentation/usb/chipidea.txt 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/Documentation/usb/chipidea.txt 2016-06-19 22:11:55.081154709 +0200
+@@ -0,0 +1,98 @@
++1. How to test OTG FSM(HNP and SRP)
++-----------------------------------
++To show how to demo OTG HNP and SRP functions via sys input files
++with 2 Freescale i.MX6Q sabre SD boards.
++
++1.1 How to enable OTG FSM in menuconfig
++---------------------------------------
++Select CONFIG_USB_OTG_FSM, rebuild kernel Image and modules.
++If you want to check some internal variables for otg fsm,
++select CONFIG_USB_CHIPIDEA_DEBUG, there are 2 files which
++can show otg fsm variables and some controller registers value:
++cat /sys/kernel/debug/ci_hdrc.0/otg
++cat /sys/kernel/debug/ci_hdrc.0/registers
++
++1.2 Test operations
++-------------------
++1) Power up 2 Freescale i.MX6Q sabre SD boards with gadget class driver loaded
++ (e.g. g_mass_storage).
++
++2) Connect 2 boards with usb cable with one end is micro A plug, the other end
++ is micro B plug.
++
++ The A-device(with micro A plug inserted) should enumrate B-device.
++
++3) Role switch
++ On B-device:
++ echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
++
++ B-device should take host role and enumrate A-device.
++
++4) A-device switch back to host.
++ On A-device:
++ echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
++
++ or, on B-device:
++ echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
++
++ A-device should switch back to host and enumrate B-device.
++
++5) Remove B-device(unplug micro B plug) and insert again in 10 seconds,
++ A-device should enumrate B-device again.
++
++6) Remove B-device(unplug micro B plug) and insert again after 10 seconds,
++ A-device should NOT enumrate B-device.
++
++ if A-device wants to use bus:
++ On A-device:
++ echo 0 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_drop
++ echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_req
++
++ if B-device wants to use bus:
++ On B-device:
++ echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
++
++7) A-device power down the bus.
++ On A-device:
++ echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/a_bus_drop
++
++ A-device should disconnect with B-device and power down the bus.
++
++8) B-device does data pulse for SRP.
++ On B-device:
++ echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
++
++ A-device should resume usb bus and enumrate B-device.
++
++1.3 Reference document
++----------------------
++"On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification
++July 27, 2012 Revision 2.0 version 1.1a"
++
++1.4 OTG compliance test
++----------------------
++Only below 3 popular gadget drivers are declared to be USB OTG and EH 2.0
++compliant(with otg descriptor comply with USB OTG and EH 2.0 as a peripheral):
++- mass storage
++- ether
++- serial
++
++2. How to enable USB as system wakeup source
++-----------------------------------
++Below is the example for how to enable USB as system wakeup source
++at imx6 platform.
++
++2.1 Enable core's wakeup
++echo enabled > /sys/bus/platform/devices/ci_hdrc.0/power/wakeup
++2.2 Enable glue layer's wakeup
++echo enabled > /sys/bus/platform/devices/2184000.usb/power/wakeup
++2.3 Enable PHY's wakeup (optional)
++echo enabled > /sys/bus/platform/devices/20c9000.usbphy/power/wakeup
++2.4 Enable roothub's wakeup
++echo enabled > /sys/bus/usb/devices/usb1/power/wakeup
++2.5 Enable related device's wakeup
++echo enabled > /sys/bus/usb/devices/1-1/power/wakeup
++
++If the system has only one usb port, and you want usb wakeup at this port, you
++can use below script to enable usb wakeup.
++for i in $(find /sys -name wakeup | grep usb);do echo enabled > $i;done;
+diff -Nur linux-3.14.72.orig/drivers/acpi/device_pm.c linux-3.14.72/drivers/acpi/device_pm.c
+--- linux-3.14.72.orig/drivers/acpi/device_pm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/acpi/device_pm.c 2016-06-19 22:11:55.081154709 +0200
+@@ -987,6 +987,8 @@
+ acpi_dev_pm_full_power(adev);
+ __acpi_device_run_wake(adev, false);
+ }
++
++ dev->pm_domain->detach = acpi_dev_pm_detach;
+ return 0;
+ }
+ EXPORT_SYMBOL_GPL(acpi_dev_pm_attach);
+diff -Nur linux-3.14.72.orig/drivers/ata/acard-ahci.c linux-3.14.72/drivers/ata/acard-ahci.c
+--- linux-3.14.72.orig/drivers/ata/acard-ahci.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/acard-ahci.c 2016-06-19 22:11:55.081154709 +0200
+@@ -36,7 +36,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -78,7 +77,7 @@
+ static int acard_ahci_port_start(struct ata_port *ap);
+ static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
+ static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
+ #endif
+@@ -119,13 +118,13 @@
+ .id_table = acard_ahci_pci_tbl,
+ .probe = acard_ahci_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = acard_ahci_pci_device_suspend,
+ .resume = acard_ahci_pci_device_resume,
+ #endif
+ };
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -442,7 +441,7 @@
+ hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
+
+ /* save initial config */
+- ahci_save_initial_config(&pdev->dev, hpriv, 0, 0);
++ ahci_save_initial_config(&pdev->dev, hpriv);
+
+ /* prepare host */
+ if (hpriv->cap & HOST_CAP_NCQ)
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci.c linux-3.14.72/drivers/ata/ahci.c
+--- linux-3.14.72.orig/drivers/ata/ahci.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/ahci.c 2016-06-19 22:11:55.081154709 +0200
+@@ -35,7 +35,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -574,8 +573,7 @@
+ "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
+ }
+
+- ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
+- mask_port_map);
++ ahci_save_initial_config(&pdev->dev, hpriv);
+ }
+
+ static int ahci_pci_reset_controller(struct ata_host *host)
+@@ -630,6 +628,7 @@
+ unsigned long deadline)
+ {
+ struct ata_port *ap = link->ap;
++ struct ahci_host_priv *hpriv = ap->host->private_data;
+ bool online;
+ int rc;
+
+@@ -640,7 +639,7 @@
+ rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
+ deadline, &online, NULL);
+
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+
+ DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
+
+@@ -655,6 +654,7 @@
+ {
+ struct ata_port *ap = link->ap;
+ struct ahci_port_priv *pp = ap->private_data;
++ struct ahci_host_priv *hpriv = ap->host->private_data;
+ u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+ struct ata_taskfile tf;
+ bool online;
+@@ -670,7 +670,7 @@
+ rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
+ deadline, &online, NULL);
+
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+
+ /* The pseudo configuration device on SIMG4726 attached to
+ * ASUS P5W-DH Deluxe doesn't send signature FIS after
+@@ -1243,6 +1243,13 @@
+
+ /* fallback to single MSI mode if the controller enforced MRSM mode */
+ if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
++ pci_disable_msi(pdev);
++ printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
++ goto single_msi;
++ }
++
++ /* fallback to single MSI mode if the controller enforced MRSM mode */
++ if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
+ pci_disable_msi(pdev);
+ printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
+ goto single_msi;
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_da850.c linux-3.14.72/drivers/ata/ahci_da850.c
+--- linux-3.14.72.orig/drivers/ata/ahci_da850.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/ata/ahci_da850.c 2016-06-19 22:11:55.081154709 +0200
+@@ -0,0 +1,114 @@
++/*
++ * DaVinci DA850 AHCI SATA platform driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2, or (at your option)
++ * any later version.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/pm.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/libata.h>
++#include <linux/ahci_platform.h>
++#include "ahci.h"
++
++/* SATA PHY Control Register offset from AHCI base */
++#define SATA_P0PHYCR_REG 0x178
++
++#define SATA_PHY_MPY(x) ((x) << 0)
++#define SATA_PHY_LOS(x) ((x) << 6)
++#define SATA_PHY_RXCDR(x) ((x) << 10)
++#define SATA_PHY_RXEQ(x) ((x) << 13)
++#define SATA_PHY_TXSWING(x) ((x) << 19)
++#define SATA_PHY_ENPLL(x) ((x) << 31)
++
++/*
++ * The multiplier needed for 1.5GHz PLL output.
++ *
++ * NOTE: This is currently hardcoded to be suitable for 100MHz crystal
++ * frequency (which is used by DA850 EVM board) and may need to be changed
++ * if you would like to use this driver on some other board.
++ */
++#define DA850_SATA_CLK_MULTIPLIER 7
++
++static void da850_sata_init(struct device *dev, void __iomem *pwrdn_reg,
++ void __iomem *ahci_base)
++{
++ unsigned int val;
++
++ /* Enable SATA clock receiver */
++ val = readl(pwrdn_reg);
++ val &= ~BIT(0);
++ writel(val, pwrdn_reg);
++
++ val = SATA_PHY_MPY(DA850_SATA_CLK_MULTIPLIER + 1) | SATA_PHY_LOS(1) |
++ SATA_PHY_RXCDR(4) | SATA_PHY_RXEQ(1) | SATA_PHY_TXSWING(3) |
++ SATA_PHY_ENPLL(1);
++
++ writel(val, ahci_base + SATA_P0PHYCR_REG);
++}
++
++static const struct ata_port_info ahci_da850_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_platform_ops,
++};
++
++static int ahci_da850_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct ahci_host_priv *hpriv;
++ struct resource *res;
++ void __iomem *pwrdn_reg;
++ int rc;
++
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
++
++ rc = ahci_platform_enable_resources(hpriv);
++ if (rc)
++ return rc;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ if (!res)
++ goto disable_resources;
++
++ pwrdn_reg = devm_ioremap(dev, res->start, resource_size(res));
++ if (!pwrdn_reg)
++ goto disable_resources;
++
++ da850_sata_init(dev, pwrdn_reg, hpriv->mmio);
++
++ rc = ahci_platform_init_host(pdev, hpriv, &ahci_da850_port_info);
++ if (rc)
++ goto disable_resources;
++
++ return 0;
++disable_resources:
++ ahci_platform_disable_resources(hpriv);
++ return rc;
++}
++
++static SIMPLE_DEV_PM_OPS(ahci_da850_pm_ops, ahci_platform_suspend,
++ ahci_platform_resume);
++
++static struct platform_driver ahci_da850_driver = {
++ .probe = ahci_da850_probe,
++ .remove = ata_platform_remove_one,
++ .driver = {
++ .name = "ahci_da850",
++ .owner = THIS_MODULE,
++ .pm = &ahci_da850_pm_ops,
++ },
++};
++module_platform_driver(ahci_da850_driver);
++
++MODULE_DESCRIPTION("DaVinci DA850 AHCI SATA platform driver");
++MODULE_AUTHOR("Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci.h linux-3.14.72/drivers/ata/ahci.h
+--- linux-3.14.72.orig/drivers/ata/ahci.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/ahci.h 2016-06-19 22:11:55.085154441 +0200
+@@ -37,6 +37,8 @@
+
+ #include <linux/clk.h>
+ #include <linux/libata.h>
++#include <linux/phy/phy.h>
++#include <linux/regulator/consumer.h>
+
+ /* Enclosure Management Control */
+ #define EM_CTRL_MSG_TYPE 0x000f0000
+@@ -51,6 +53,7 @@
+
+ enum {
+ AHCI_MAX_PORTS = 32,
++ AHCI_MAX_CLKS = 4,
+ AHCI_MAX_SG = 168, /* hardware max is 64K */
+ AHCI_DMA_BOUNDARY = 0xffffffff,
+ AHCI_MAX_CMDS = 32,
+@@ -233,6 +236,7 @@
+ port start (wait until
+ error-handling stage) */
+ AHCI_HFLAG_MULTI_MSI = (1 << 16), /* multiple PCI MSIs */
++ AHCI_HFLAG_NO_FBS = (1 << 17), /* no FBS */
+
+ /* ap->flags bits */
+
+@@ -311,8 +315,12 @@
+ };
+
+ struct ahci_host_priv {
+- void __iomem * mmio; /* bus-independent mem map */
++ /* Input fields */
+ unsigned int flags; /* AHCI_HFLAG_* */
++ u32 force_port_map; /* force port map */
++ u32 mask_port_map; /* mask out particular bits */
++
++ void __iomem * mmio; /* bus-independent mem map */
+ u32 cap; /* cap to use */
+ u32 cap2; /* cap2 to use */
+ u32 port_map; /* port map to use */
+@@ -322,8 +330,17 @@
+ u32 em_loc; /* enclosure management location */
+ u32 em_buf_sz; /* EM buffer size in byte */
+ u32 em_msg_type; /* EM message type */
+- struct clk *clk; /* Only for platforms supporting clk */
++ bool got_runtime_pm; /* Did we do pm_runtime_get? */
++ struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
++ struct regulator *target_pwr; /* Optional */
++ struct phy *phy; /* If platform uses phy */
+ void *plat_data; /* Other platform data */
++ /*
++ * Optional ahci_start_engine override, if not set this gets set to the
++ * default ahci_start_engine during ahci_save_initial_config, this can
++ * be overridden anytime before the host is activated.
++ */
++ void (*start_engine)(struct ata_port *ap);
+ };
+
+ extern int ahci_ignore_sss;
+@@ -347,9 +364,7 @@
+ void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
+ u32 opts);
+ void ahci_save_initial_config(struct device *dev,
+- struct ahci_host_priv *hpriv,
+- unsigned int force_port_map,
+- unsigned int mask_port_map);
++ struct ahci_host_priv *hpriv);
+ void ahci_init_controller(struct ata_host *host);
+ int ahci_reset_controller(struct ata_host *host);
+
+@@ -357,7 +372,9 @@
+ int pmp, unsigned long deadline,
+ int (*check_ready)(struct ata_link *link));
+
++unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
+ int ahci_stop_engine(struct ata_port *ap);
++void ahci_start_fis_rx(struct ata_port *ap);
+ void ahci_start_engine(struct ata_port *ap);
+ int ahci_check_ready(struct ata_link *link);
+ int ahci_kick_engine(struct ata_port *ap);
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_imx.c linux-3.14.72/drivers/ata/ahci_imx.c
+--- linux-3.14.72.orig/drivers/ata/ahci_imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/ahci_imx.c 2016-06-19 22:11:55.085154441 +0200
+@@ -29,9 +29,25 @@
+ #include "ahci.h"
+
+ enum {
+- PORT_PHY_CTL = 0x178, /* Port0 PHY Control */
+- PORT_PHY_CTL_PDDQ_LOC = 0x100000, /* PORT_PHY_CTL bits */
+- HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
++ /* Timer 1-ms Register */
++ IMX_TIMER1MS = 0x00e0,
++ /* Port0 PHY Control Register */
++ IMX_P0PHYCR = 0x0178,
++ IMX_P0PHYCR_TEST_PDDQ = 1 << 20,
++ IMX_P0PHYCR_CR_READ = 1 << 19,
++ IMX_P0PHYCR_CR_WRITE = 1 << 18,
++ IMX_P0PHYCR_CR_CAP_DATA = 1 << 17,
++ IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16,
++ /* Port0 PHY Status Register */
++ IMX_P0PHYSR = 0x017c,
++ IMX_P0PHYSR_CR_ACK = 1 << 18,
++ IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0,
++ /* Lane0 Output Status Register */
++ IMX_LANE0_OUT_STAT = 0x2003,
++ IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1,
++ /* Clock Reset Register */
++ IMX_CLOCK_RESET = 0x7f3f,
++ IMX_CLOCK_RESET_RESET = 1 << 0,
+ };
+
+ enum ahci_imx_type {
+@@ -42,62 +58,230 @@
+ struct imx_ahci_priv {
+ struct platform_device *ahci_pdev;
+ enum ahci_imx_type type;
+-
+- /* i.MX53 clock */
+- struct clk *sata_gate_clk;
+- /* Common clock */
++ struct clk *sata_clk;
+ struct clk *sata_ref_clk;
+ struct clk *ahb_clk;
+-
+ struct regmap *gpr;
+ bool no_device;
+ bool first_time;
++ u32 phy_params;
+ };
+
+ static int ahci_imx_hotplug;
+ module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
+ MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
+
+-static int imx_sata_clock_enable(struct device *dev)
++static void ahci_imx_host_stop(struct ata_host *host);
++
++static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
++{
++ int timeout = 10;
++ u32 crval;
++ u32 srval;
++
++ /* Assert or deassert the bit */
++ crval = readl(mmio + IMX_P0PHYCR);
++ if (assert)
++ crval |= bit;
++ else
++ crval &= ~bit;
++ writel(crval, mmio + IMX_P0PHYCR);
++
++ /* Wait for the cr_ack signal */
++ do {
++ srval = readl(mmio + IMX_P0PHYSR);
++ if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
++ break;
++ usleep_range(100, 200);
++ } while (--timeout);
++
++ return timeout ? 0 : -ETIMEDOUT;
++}
++
++static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
++{
++ u32 crval = addr;
++ int ret;
++
++ /* Supply the address on cr_data_in */
++ writel(crval, mmio + IMX_P0PHYCR);
++
++ /* Assert the cr_cap_addr signal */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
++ if (ret)
++ return ret;
++
++ /* Deassert cr_cap_addr */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int imx_phy_reg_write(u16 val, void __iomem *mmio)
++{
++ u32 crval = val;
++ int ret;
++
++ /* Supply the data on cr_data_in */
++ writel(crval, mmio + IMX_P0PHYCR);
++
++ /* Assert the cr_cap_data signal */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
++ if (ret)
++ return ret;
++
++ /* Deassert cr_cap_data */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
++ if (ret)
++ return ret;
++
++ if (val & IMX_CLOCK_RESET_RESET) {
++ /*
++ * In case we're resetting the phy, it's unable to acknowledge,
++ * so we return immediately here.
++ */
++ crval |= IMX_P0PHYCR_CR_WRITE;
++ writel(crval, mmio + IMX_P0PHYCR);
++ goto out;
++ }
++
++ /* Assert the cr_write signal */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
++ if (ret)
++ return ret;
++
++ /* Deassert cr_write */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
++ if (ret)
++ return ret;
++
++out:
++ return 0;
++}
++
++static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
++{
++ int ret;
++
++ /* Assert the cr_read signal */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
++ if (ret)
++ return ret;
++
++ /* Capture the data from cr_data_out[] */
++ *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
++
++ /* Deassert cr_read */
++ ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
++ if (ret)
++ return ret;
++
++ return 0;
++}
++
++static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
+ {
+- struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++ void __iomem *mmio = hpriv->mmio;
++ int timeout = 10;
++ u16 val;
+ int ret;
+
+- if (imxpriv->type == AHCI_IMX53) {
+- ret = clk_prepare_enable(imxpriv->sata_gate_clk);
+- if (ret < 0) {
+- dev_err(dev, "prepare-enable sata_gate clock err:%d\n",
+- ret);
++ /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
++ ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
++ if (ret)
++ return ret;
++ ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
++ if (ret)
++ return ret;
++
++ /* Wait for PHY RX_PLL to be stable */
++ do {
++ usleep_range(100, 200);
++ ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
++ if (ret)
++ return ret;
++ ret = imx_phy_reg_read(&val, mmio);
++ if (ret)
++ return ret;
++ if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
++ break;
++ } while (--timeout);
++
++ return timeout ? 0 : -ETIMEDOUT;
++}
++
++static int imx_sata_enable(struct ahci_host_priv *hpriv)
++{
++ struct imx_ahci_priv *imxpriv = hpriv->plat_data;
++ struct device *dev = &imxpriv->ahci_pdev->dev;
++ int ret;
++
++ if (imxpriv->no_device)
++ return 0;
++
++ if (hpriv->target_pwr) {
++ ret = regulator_enable(hpriv->target_pwr);
++ if (ret)
+ return ret;
+- }
+ }
+
+ ret = clk_prepare_enable(imxpriv->sata_ref_clk);
+- if (ret < 0) {
+- dev_err(dev, "prepare-enable sata_ref clock err:%d\n",
+- ret);
+- goto clk_err;
+- }
++ if (ret < 0)
++ goto disable_regulator;
+
+ if (imxpriv->type == AHCI_IMX6Q) {
++ /*
++ * set PHY Paremeters, two steps to configure the GPR13,
++ * one write for rest of parameters, mask of first write
++ * is 0x07ffffff, and the other one write for setting
++ * the mpll_clk_en.
++ */
++ regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
++ IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
++ IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
++ IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
++ IMX6Q_GPR13_SATA_SPD_MODE_MASK |
++ IMX6Q_GPR13_SATA_MPLL_SS_EN |
++ IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
++ IMX6Q_GPR13_SATA_TX_BOOST_MASK |
++ IMX6Q_GPR13_SATA_TX_LVL_MASK |
++ IMX6Q_GPR13_SATA_MPLL_CLK_EN |
++ IMX6Q_GPR13_SATA_TX_EDGE_RATE,
++ imxpriv->phy_params);
+ regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
+ IMX6Q_GPR13_SATA_MPLL_CLK_EN,
+ IMX6Q_GPR13_SATA_MPLL_CLK_EN);
++
++ usleep_range(100, 200);
++
++ ret = imx_sata_phy_reset(hpriv);
++ if (ret) {
++ dev_err(dev, "failed to reset phy: %d\n", ret);
++ goto disable_clk;
++ }
+ }
+
+ usleep_range(1000, 2000);
+
+ return 0;
+
+-clk_err:
+- if (imxpriv->type == AHCI_IMX53)
+- clk_disable_unprepare(imxpriv->sata_gate_clk);
++disable_clk:
++ clk_disable_unprepare(imxpriv->sata_ref_clk);
++disable_regulator:
++ if (hpriv->target_pwr)
++ regulator_disable(hpriv->target_pwr);
++
+ return ret;
+ }
+
+-static void imx_sata_clock_disable(struct device *dev)
++static void imx_sata_disable(struct ahci_host_priv *hpriv)
+ {
+- struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++ struct imx_ahci_priv *imxpriv = hpriv->plat_data;
++
++ if (imxpriv->no_device)
++ return;
+
+ if (imxpriv->type == AHCI_IMX6Q) {
+ regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
+@@ -107,8 +291,8 @@
+
+ clk_disable_unprepare(imxpriv->sata_ref_clk);
+
+- if (imxpriv->type == AHCI_IMX53)
+- clk_disable_unprepare(imxpriv->sata_gate_clk);
++ if (hpriv->target_pwr)
++ regulator_disable(hpriv->target_pwr);
+ }
+
+ static void ahci_imx_error_handler(struct ata_port *ap)
+@@ -118,7 +302,7 @@
+ struct ata_host *host = dev_get_drvdata(ap->dev);
+ struct ahci_host_priv *hpriv = host->private_data;
+ void __iomem *mmio = hpriv->mmio;
+- struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
++ struct imx_ahci_priv *imxpriv = hpriv->plat_data;
+
+ ahci_error_handler(ap);
+
+@@ -134,17 +318,22 @@
+ * without full reset once the pddq mode is enabled making it
+ * impossible to use as part of libata LPM.
+ */
+- reg_val = readl(mmio + PORT_PHY_CTL);
+- writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
+- imx_sata_clock_disable(ap->dev);
++ reg_val = readl(mmio + IMX_P0PHYCR);
++ writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
++ imx_sata_disable(hpriv);
+ imxpriv->no_device = true;
++
++ dev_info(ap->dev, "no device found, disabling link.\n");
++ dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
+ }
+
+ static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
+ unsigned long deadline)
+ {
+ struct ata_port *ap = link->ap;
+- struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
++ struct ata_host *host = dev_get_drvdata(ap->dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ struct imx_ahci_priv *imxpriv = hpriv->plat_data;
+ int ret = -EIO;
+
+ if (imxpriv->type == AHCI_IMX53)
+@@ -156,7 +345,8 @@
+ }
+
+ static struct ata_port_operations ahci_imx_ops = {
+- .inherits = &ahci_platform_ops,
++ .inherits = &ahci_ops,
++ .host_stop = ahci_imx_host_stop,
+ .error_handler = ahci_imx_error_handler,
+ .softreset = ahci_imx_softreset,
+ };
+@@ -168,234 +358,330 @@
+ .port_ops = &ahci_imx_ops,
+ };
+
+-static int imx_sata_init(struct device *dev, void __iomem *mmio)
+-{
+- int ret = 0;
+- unsigned int reg_val;
+- struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
+-
+- ret = imx_sata_clock_enable(dev);
+- if (ret < 0)
+- return ret;
++static const struct of_device_id imx_ahci_of_match[] = {
++ { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
++ { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
++ {},
++};
++MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
+
+- /*
+- * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
+- * and IP vendor specific register HOST_TIMER1MS.
+- * Configure CAP_SSS (support stagered spin up).
+- * Implement the port0.
+- * Get the ahb clock rate, and configure the TIMER1MS register.
+- */
+- reg_val = readl(mmio + HOST_CAP);
+- if (!(reg_val & HOST_CAP_SSS)) {
+- reg_val |= HOST_CAP_SSS;
+- writel(reg_val, mmio + HOST_CAP);
+- }
+- reg_val = readl(mmio + HOST_PORTS_IMPL);
+- if (!(reg_val & 0x1)) {
+- reg_val |= 0x1;
+- writel(reg_val, mmio + HOST_PORTS_IMPL);
+- }
++struct reg_value {
++ u32 of_value;
++ u32 reg_value;
++};
+
+- reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
+- writel(reg_val, mmio + HOST_TIMER1MS);
++struct reg_property {
++ const char *name;
++ const struct reg_value *values;
++ size_t num_values;
++ u32 def_value;
++ u32 set_value;
++};
+
+- return 0;
+-}
++static const struct reg_value gpr13_tx_level[] = {
++ { 937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
++ { 947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
++ { 957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
++ { 966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
++ { 976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
++ { 986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
++ { 996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
++ { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
++ { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
++ { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
++ { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
++ { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
++ { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
++ { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
++ { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
++ { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
++ { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
++ { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
++ { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
++ { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
++ { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
++ { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
++ { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
++ { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
++ { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
++ { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
++ { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
++ { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
++ { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
++ { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
++ { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
++ { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
++};
+
+-static void imx_sata_exit(struct device *dev)
+-{
+- imx_sata_clock_disable(dev);
+-}
++static const struct reg_value gpr13_tx_boost[] = {
++ { 0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
++ { 370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
++ { 740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
++ { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
++ { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
++ { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
++ { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
++ { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
++ { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
++ { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
++ { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
++ { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
++ { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
++ { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
++ { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
++ { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
++};
+
+-static int imx_ahci_suspend(struct device *dev)
+-{
+- struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
++static const struct reg_value gpr13_tx_atten[] = {
++ { 8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
++ { 9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
++ { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
++ { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
++ { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
++ { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
++};
+
+- /*
+- * If no_device is set, The CLKs had been gated off in the
+- * initialization so don't do it again here.
+- */
+- if (!imxpriv->no_device)
+- imx_sata_clock_disable(dev);
++static const struct reg_value gpr13_rx_eq[] = {
++ { 500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
++ { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
++ { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
++ { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
++ { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
++ { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
++ { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
++ { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
++};
+
+- return 0;
+-}
++static const struct reg_property gpr13_props[] = {
++ {
++ .name = "fsl,transmit-level-mV",
++ .values = gpr13_tx_level,
++ .num_values = ARRAY_SIZE(gpr13_tx_level),
++ .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
++ }, {
++ .name = "fsl,transmit-boost-mdB",
++ .values = gpr13_tx_boost,
++ .num_values = ARRAY_SIZE(gpr13_tx_boost),
++ .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
++ }, {
++ .name = "fsl,transmit-atten-16ths",
++ .values = gpr13_tx_atten,
++ .num_values = ARRAY_SIZE(gpr13_tx_atten),
++ .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
++ }, {
++ .name = "fsl,receive-eq-mdB",
++ .values = gpr13_rx_eq,
++ .num_values = ARRAY_SIZE(gpr13_rx_eq),
++ .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
++ }, {
++ .name = "fsl,no-spread-spectrum",
++ .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
++ .set_value = 0,
++ },
++};
+
+-static int imx_ahci_resume(struct device *dev)
++static u32 imx_ahci_parse_props(struct device *dev,
++ const struct reg_property *prop, size_t num)
+ {
+- struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
+- int ret = 0;
+-
+- if (!imxpriv->no_device)
+- ret = imx_sata_clock_enable(dev);
++ struct device_node *np = dev->of_node;
++ u32 reg_value = 0;
++ int i, j;
++
++ for (i = 0; i < num; i++, prop++) {
++ u32 of_val;
++
++ if (prop->num_values == 0) {
++ if (of_property_read_bool(np, prop->name))
++ reg_value |= prop->set_value;
++ else
++ reg_value |= prop->def_value;
++ continue;
++ }
+
+- return ret;
+-}
++ if (of_property_read_u32(np, prop->name, &of_val)) {
++ dev_info(dev, "%s not specified, using %08x\n",
++ prop->name, prop->def_value);
++ reg_value |= prop->def_value;
++ continue;
++ }
+
+-static struct ahci_platform_data imx_sata_pdata = {
+- .init = imx_sata_init,
+- .exit = imx_sata_exit,
+- .ata_port_info = &ahci_imx_port_info,
+- .suspend = imx_ahci_suspend,
+- .resume = imx_ahci_resume,
++ for (j = 0; j < prop->num_values; j++) {
++ if (prop->values[j].of_value == of_val) {
++ dev_info(dev, "%s value %u, using %08x\n",
++ prop->name, of_val, prop->values[j].reg_value);
++ reg_value |= prop->values[j].reg_value;
++ break;
++ }
++ }
+
+-};
++ if (j == prop->num_values) {
++ dev_err(dev, "DT property %s is not a valid value\n",
++ prop->name);
++ reg_value |= prop->def_value;
++ }
++ }
+
+-static const struct of_device_id imx_ahci_of_match[] = {
+- { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
+- { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
+- {},
+-};
+-MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
++ return reg_value;
++}
+
+ static int imx_ahci_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+- struct resource *mem, *irq, res[2];
+ const struct of_device_id *of_id;
+- enum ahci_imx_type type;
+- const struct ahci_platform_data *pdata = NULL;
++ struct ahci_host_priv *hpriv;
+ struct imx_ahci_priv *imxpriv;
+- struct device *ahci_dev;
+- struct platform_device *ahci_pdev;
++ unsigned int reg_val;
+ int ret;
+
+ of_id = of_match_device(imx_ahci_of_match, dev);
+ if (!of_id)
+ return -EINVAL;
+
+- type = (enum ahci_imx_type)of_id->data;
+- pdata = &imx_sata_pdata;
+-
+ imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
+- if (!imxpriv) {
+- dev_err(dev, "can't alloc ahci_host_priv\n");
++ if (!imxpriv)
+ return -ENOMEM;
+- }
+-
+- ahci_pdev = platform_device_alloc("ahci", -1);
+- if (!ahci_pdev)
+- return -ENODEV;
+-
+- ahci_dev = &ahci_pdev->dev;
+- ahci_dev->parent = dev;
+
++ imxpriv->ahci_pdev = pdev;
+ imxpriv->no_device = false;
+ imxpriv->first_time = true;
+- imxpriv->type = type;
+-
+- imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
+- if (IS_ERR(imxpriv->ahb_clk)) {
+- dev_err(dev, "can't get ahb clock.\n");
+- ret = PTR_ERR(imxpriv->ahb_clk);
+- goto err_out;
+- }
++ imxpriv->type = (enum ahci_imx_type)of_id->data;
+
+- if (type == AHCI_IMX53) {
+- imxpriv->sata_gate_clk = devm_clk_get(dev, "sata_gate");
+- if (IS_ERR(imxpriv->sata_gate_clk)) {
+- dev_err(dev, "can't get sata_gate clock.\n");
+- ret = PTR_ERR(imxpriv->sata_gate_clk);
+- goto err_out;
+- }
++ imxpriv->sata_clk = devm_clk_get(dev, "sata");
++ if (IS_ERR(imxpriv->sata_clk)) {
++ dev_err(dev, "can't get sata clock.\n");
++ return PTR_ERR(imxpriv->sata_clk);
+ }
+
+ imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
+ if (IS_ERR(imxpriv->sata_ref_clk)) {
+ dev_err(dev, "can't get sata_ref clock.\n");
+- ret = PTR_ERR(imxpriv->sata_ref_clk);
+- goto err_out;
++ return PTR_ERR(imxpriv->sata_ref_clk);
+ }
+
+- imxpriv->ahci_pdev = ahci_pdev;
+- platform_set_drvdata(pdev, imxpriv);
+-
+- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+- if (!mem || !irq) {
+- dev_err(dev, "no mmio/irq resource\n");
+- ret = -ENOMEM;
+- goto err_out;
++ imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
++ if (IS_ERR(imxpriv->ahb_clk)) {
++ dev_err(dev, "can't get ahb clock.\n");
++ return PTR_ERR(imxpriv->ahb_clk);
+ }
+
+- res[0] = *mem;
+- res[1] = *irq;
+-
+- ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
+- ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
+- ahci_dev->of_node = dev->of_node;
++ if (imxpriv->type == AHCI_IMX6Q) {
++ u32 reg_value;
+
+- if (type == AHCI_IMX6Q) {
+ imxpriv->gpr = syscon_regmap_lookup_by_compatible(
+ "fsl,imx6q-iomuxc-gpr");
+ if (IS_ERR(imxpriv->gpr)) {
+ dev_err(dev,
+ "failed to find fsl,imx6q-iomux-gpr regmap\n");
+- ret = PTR_ERR(imxpriv->gpr);
+- goto err_out;
++ return PTR_ERR(imxpriv->gpr);
+ }
+
+- /*
+- * Set PHY Paremeters, two steps to configure the GPR13,
+- * one write for rest of parameters, mask of first write
+- * is 0x07fffffe, and the other one write for setting
+- * the mpll_clk_en happens in imx_sata_clock_enable().
+- */
+- regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
+- IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
+- IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
+- IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
+- IMX6Q_GPR13_SATA_SPD_MODE_MASK |
+- IMX6Q_GPR13_SATA_MPLL_SS_EN |
+- IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
+- IMX6Q_GPR13_SATA_TX_BOOST_MASK |
+- IMX6Q_GPR13_SATA_TX_LVL_MASK |
+- IMX6Q_GPR13_SATA_MPLL_CLK_EN |
+- IMX6Q_GPR13_SATA_TX_EDGE_RATE,
+- IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
++ reg_value = imx_ahci_parse_props(dev, gpr13_props,
++ ARRAY_SIZE(gpr13_props));
++
++ imxpriv->phy_params =
+ IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
+ IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
+ IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
+- IMX6Q_GPR13_SATA_MPLL_SS_EN |
+- IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
+- IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
+- IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
++ reg_value;
+ }
+
+- ret = platform_device_add_resources(ahci_pdev, res, 2);
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
++
++ hpriv->plat_data = imxpriv;
++
++ ret = clk_prepare_enable(imxpriv->sata_clk);
+ if (ret)
+- goto err_out;
++ return ret;
+
+- ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
++ ret = imx_sata_enable(hpriv);
+ if (ret)
+- goto err_out;
++ goto disable_clk;
+
+- ret = platform_device_add(ahci_pdev);
+- if (ret) {
+-err_out:
+- platform_device_put(ahci_pdev);
+- return ret;
++ /*
++ * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
++ * and IP vendor specific register IMX_TIMER1MS.
++ * Configure CAP_SSS (support stagered spin up).
++ * Implement the port0.
++ * Get the ahb clock rate, and configure the TIMER1MS register.
++ */
++ reg_val = readl(hpriv->mmio + HOST_CAP);
++ if (!(reg_val & HOST_CAP_SSS)) {
++ reg_val |= HOST_CAP_SSS;
++ writel(reg_val, hpriv->mmio + HOST_CAP);
++ }
++ reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
++ if (!(reg_val & 0x1)) {
++ reg_val |= 0x1;
++ writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
+ }
+
++ reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
++ writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
++
++ ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info);
++ if (ret)
++ goto disable_sata;
++
+ return 0;
++
++disable_sata:
++ imx_sata_disable(hpriv);
++disable_clk:
++ clk_disable_unprepare(imxpriv->sata_clk);
++ return ret;
+ }
+
+-static int imx_ahci_remove(struct platform_device *pdev)
++static void ahci_imx_host_stop(struct ata_host *host)
+ {
+- struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
+- struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
++ struct ahci_host_priv *hpriv = host->private_data;
++ struct imx_ahci_priv *imxpriv = hpriv->plat_data;
++
++ imx_sata_disable(hpriv);
++ clk_disable_unprepare(imxpriv->sata_clk);
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int imx_ahci_suspend(struct device *dev)
++{
++ struct ata_host *host = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ int ret;
++
++ ret = ahci_platform_suspend_host(dev);
++ if (ret)
++ return ret;
++
++ imx_sata_disable(hpriv);
+
+- platform_device_unregister(ahci_pdev);
+ return 0;
+ }
+
++static int imx_ahci_resume(struct device *dev)
++{
++ struct ata_host *host = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ int ret;
++
++ ret = imx_sata_enable(hpriv);
++ if (ret)
++ return ret;
++
++ return ahci_platform_resume_host(dev);
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
++
+ static struct platform_driver imx_ahci_driver = {
+ .probe = imx_ahci_probe,
+- .remove = imx_ahci_remove,
++ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = "ahci-imx",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_ahci_of_match,
++ .pm = &ahci_imx_pm_ops,
+ },
+ };
+ module_platform_driver(imx_ahci_driver);
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_mvebu.c linux-3.14.72/drivers/ata/ahci_mvebu.c
+--- linux-3.14.72.orig/drivers/ata/ahci_mvebu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/ata/ahci_mvebu.c 2016-06-19 22:11:55.085154441 +0200
+@@ -0,0 +1,127 @@
++/*
++ * AHCI glue platform driver for Marvell EBU SOCs
++ *
++ * Copyright (C) 2014 Marvell
++ *
++ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
++ * Marcin Wojtas <mw@semihalf.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/ahci_platform.h>
++#include <linux/kernel.h>
++#include <linux/mbus.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include "ahci.h"
++
++#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
++#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
++
++#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
++#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
++#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
++
++static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv,
++ const struct mbus_dram_target_info *dram)
++{
++ int i;
++
++ for (i = 0; i < 4; i++) {
++ writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
++ writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
++ writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
++ }
++
++ for (i = 0; i < dram->num_cs; i++) {
++ const struct mbus_dram_window *cs = dram->cs + i;
++
++ writel((cs->mbus_attr << 8) |
++ (dram->mbus_dram_target_id << 4) | 1,
++ hpriv->mmio + AHCI_WINDOW_CTRL(i));
++ writel(cs->base, hpriv->mmio + AHCI_WINDOW_BASE(i));
++ writel(((cs->size - 1) & 0xffff0000),
++ hpriv->mmio + AHCI_WINDOW_SIZE(i));
++ }
++}
++
++static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
++{
++ /*
++ * Enable the regret bit to allow the SATA unit to regret a
++ * request that didn't receive an acknowlegde and avoid a
++ * deadlock
++ */
++ writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
++ writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
++}
++
++static const struct ata_port_info ahci_mvebu_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_platform_ops,
++};
++
++static int ahci_mvebu_probe(struct platform_device *pdev)
++{
++ struct ahci_host_priv *hpriv;
++ const struct mbus_dram_target_info *dram;
++ int rc;
++
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
++
++ rc = ahci_platform_enable_resources(hpriv);
++ if (rc)
++ return rc;
++
++ dram = mv_mbus_dram_info();
++ if (!dram)
++ return -ENODEV;
++
++ ahci_mvebu_mbus_config(hpriv, dram);
++ ahci_mvebu_regret_option(hpriv);
++
++ rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info);
++ if (rc)
++ goto disable_resources;
++
++ return 0;
++
++disable_resources:
++ ahci_platform_disable_resources(hpriv);
++ return rc;
++}
++
++static const struct of_device_id ahci_mvebu_of_match[] = {
++ { .compatible = "marvell,armada-380-ahci", },
++ { },
++};
++MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
++
++/*
++ * We currently don't provide power management related operations,
++ * since there is no suspend/resume support at the platform level for
++ * Armada 38x for the moment.
++ */
++static struct platform_driver ahci_mvebu_driver = {
++ .probe = ahci_mvebu_probe,
++ .remove = ata_platform_remove_one,
++ .driver = {
++ .name = "ahci-mvebu",
++ .owner = THIS_MODULE,
++ .of_match_table = ahci_mvebu_of_match,
++ },
++};
++module_platform_driver(ahci_mvebu_driver);
++
++MODULE_DESCRIPTION("Marvell EBU AHCI SATA driver");
++MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ahci_mvebu");
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_platform.c linux-3.14.72/drivers/ata/ahci_platform.c
+--- linux-3.14.72.orig/drivers/ata/ahci_platform.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/ahci_platform.c 2016-06-19 22:11:55.085154441 +0200
+@@ -12,135 +12,37 @@
+ * any later version.
+ */
+
+-#include <linux/clk.h>
+ #include <linux/kernel.h>
+-#include <linux/gfp.h>
+ #include <linux/module.h>
+ #include <linux/pm.h>
+-#include <linux/init.h>
+-#include <linux/interrupt.h>
+ #include <linux/device.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/libata.h>
+ #include <linux/ahci_platform.h>
+ #include "ahci.h"
+
+-static void ahci_host_stop(struct ata_host *host);
+-
+-enum ahci_type {
+- AHCI, /* standard platform ahci */
+- IMX53_AHCI, /* ahci on i.mx53 */
+- STRICT_AHCI, /* delayed DMA engine start */
+-};
+-
+-static struct platform_device_id ahci_devtype[] = {
+- {
+- .name = "ahci",
+- .driver_data = AHCI,
+- }, {
+- .name = "imx53-ahci",
+- .driver_data = IMX53_AHCI,
+- }, {
+- .name = "strict-ahci",
+- .driver_data = STRICT_AHCI,
+- }, {
+- /* sentinel */
+- }
+-};
+-MODULE_DEVICE_TABLE(platform, ahci_devtype);
+-
+-struct ata_port_operations ahci_platform_ops = {
+- .inherits = &ahci_ops,
+- .host_stop = ahci_host_stop,
+-};
+-EXPORT_SYMBOL_GPL(ahci_platform_ops);
+-
+-static struct ata_port_operations ahci_platform_retry_srst_ops = {
+- .inherits = &ahci_pmp_retry_srst_ops,
+- .host_stop = ahci_host_stop,
+-};
+-
+-static const struct ata_port_info ahci_port_info[] = {
+- /* by features */
+- [AHCI] = {
+- .flags = AHCI_FLAG_COMMON,
+- .pio_mask = ATA_PIO4,
+- .udma_mask = ATA_UDMA6,
+- .port_ops = &ahci_platform_ops,
+- },
+- [IMX53_AHCI] = {
+- .flags = AHCI_FLAG_COMMON,
+- .pio_mask = ATA_PIO4,
+- .udma_mask = ATA_UDMA6,
+- .port_ops = &ahci_platform_retry_srst_ops,
+- },
+- [STRICT_AHCI] = {
+- AHCI_HFLAGS (AHCI_HFLAG_DELAY_ENGINE),
+- .flags = AHCI_FLAG_COMMON,
+- .pio_mask = ATA_PIO4,
+- .udma_mask = ATA_UDMA6,
+- .port_ops = &ahci_platform_ops,
+- },
+-};
+-
+-static struct scsi_host_template ahci_platform_sht = {
+- AHCI_SHT("ahci_platform"),
++static const struct ata_port_info ahci_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_platform_ops,
+ };
+
+ static int ahci_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+ struct ahci_platform_data *pdata = dev_get_platdata(dev);
+- const struct platform_device_id *id = platform_get_device_id(pdev);
+- struct ata_port_info pi = ahci_port_info[id ? id->driver_data : 0];
+- const struct ata_port_info *ppi[] = { &pi, NULL };
+ struct ahci_host_priv *hpriv;
+- struct ata_host *host;
+- struct resource *mem;
+- int irq;
+- int n_ports;
+- int i;
+ int rc;
+
+- mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!mem) {
+- dev_err(dev, "no mmio space\n");
+- return -EINVAL;
+- }
+-
+- irq = platform_get_irq(pdev, 0);
+- if (irq <= 0) {
+- dev_err(dev, "no irq\n");
+- return -EINVAL;
+- }
+-
+- if (pdata && pdata->ata_port_info)
+- pi = *pdata->ata_port_info;
+-
+- hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
+- if (!hpriv) {
+- dev_err(dev, "can't alloc ahci_host_priv\n");
+- return -ENOMEM;
+- }
+-
+- hpriv->flags |= (unsigned long)pi.private_data;
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
+
+- hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
+- if (!hpriv->mmio) {
+- dev_err(dev, "can't map %pR\n", mem);
+- return -ENOMEM;
+- }
+-
+- hpriv->clk = clk_get(dev, NULL);
+- if (IS_ERR(hpriv->clk)) {
+- dev_err(dev, "can't get clock\n");
+- } else {
+- rc = clk_prepare_enable(hpriv->clk);
+- if (rc) {
+- dev_err(dev, "clock prepare enable failed");
+- goto free_clk;
+- }
+- }
++ rc = ahci_platform_enable_resources(hpriv);
++ if (rc)
++ return rc;
+
+ /*
+ * Some platforms might need to prepare for mmio region access,
+@@ -151,69 +53,13 @@
+ if (pdata && pdata->init) {
+ rc = pdata->init(dev, hpriv->mmio);
+ if (rc)
+- goto disable_unprepare_clk;
+- }
+-
+- ahci_save_initial_config(dev, hpriv,
+- pdata ? pdata->force_port_map : 0,
+- pdata ? pdata->mask_port_map : 0);
+-
+- /* prepare host */
+- if (hpriv->cap & HOST_CAP_NCQ)
+- pi.flags |= ATA_FLAG_NCQ;
+-
+- if (hpriv->cap & HOST_CAP_PMP)
+- pi.flags |= ATA_FLAG_PMP;
+-
+- ahci_set_em_messages(hpriv, &pi);
+-
+- /* CAP.NP sometimes indicate the index of the last enabled
+- * port, at other times, that of the last possible port, so
+- * determining the maximum port number requires looking at
+- * both CAP.NP and port_map.
+- */
+- n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
+-
+- host = ata_host_alloc_pinfo(dev, ppi, n_ports);
+- if (!host) {
+- rc = -ENOMEM;
+- goto pdata_exit;
+- }
+-
+- host->private_data = hpriv;
+-
+- if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
+- host->flags |= ATA_HOST_PARALLEL_SCAN;
+- else
+- dev_info(dev, "SSS flag set, parallel bus scan disabled\n");
+-
+- if (pi.flags & ATA_FLAG_EM)
+- ahci_reset_em(host);
+-
+- for (i = 0; i < host->n_ports; i++) {
+- struct ata_port *ap = host->ports[i];
+-
+- ata_port_desc(ap, "mmio %pR", mem);
+- ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
+-
+- /* set enclosure management message type */
+- if (ap->flags & ATA_FLAG_EM)
+- ap->em_message_type = hpriv->em_msg_type;
+-
+- /* disabled/not-implemented port */
+- if (!(hpriv->port_map & (1 << i)))
+- ap->ops = &ata_dummy_port_ops;
++ goto disable_resources;
+ }
+
+- rc = ahci_reset_controller(host);
+- if (rc)
+- goto pdata_exit;
++ if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
++ hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
+
+- ahci_init_controller(host);
+- ahci_print_info(host, "platform");
+-
+- rc = ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
+- &ahci_platform_sht);
++ rc = ahci_platform_init_host(pdev, hpriv, &ahci_port_info);
+ if (rc)
+ goto pdata_exit;
+
+@@ -221,115 +67,20 @@
+ pdata_exit:
+ if (pdata && pdata->exit)
+ pdata->exit(dev);
+-disable_unprepare_clk:
+- if (!IS_ERR(hpriv->clk))
+- clk_disable_unprepare(hpriv->clk);
+-free_clk:
+- if (!IS_ERR(hpriv->clk))
+- clk_put(hpriv->clk);
+- return rc;
+-}
+-
+-static void ahci_host_stop(struct ata_host *host)
+-{
+- struct device *dev = host->dev;
+- struct ahci_platform_data *pdata = dev_get_platdata(dev);
+- struct ahci_host_priv *hpriv = host->private_data;
+-
+- if (pdata && pdata->exit)
+- pdata->exit(dev);
+-
+- if (!IS_ERR(hpriv->clk)) {
+- clk_disable_unprepare(hpriv->clk);
+- clk_put(hpriv->clk);
+- }
+-}
+-
+-#ifdef CONFIG_PM_SLEEP
+-static int ahci_suspend(struct device *dev)
+-{
+- struct ahci_platform_data *pdata = dev_get_platdata(dev);
+- struct ata_host *host = dev_get_drvdata(dev);
+- struct ahci_host_priv *hpriv = host->private_data;
+- void __iomem *mmio = hpriv->mmio;
+- u32 ctl;
+- int rc;
+-
+- if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
+- dev_err(dev, "firmware update required for suspend/resume\n");
+- return -EIO;
+- }
+-
+- /*
+- * AHCI spec rev1.1 section 8.3.3:
+- * Software must disable interrupts prior to requesting a
+- * transition of the HBA to D3 state.
+- */
+- ctl = readl(mmio + HOST_CTL);
+- ctl &= ~HOST_IRQ_EN;
+- writel(ctl, mmio + HOST_CTL);
+- readl(mmio + HOST_CTL); /* flush */
+-
+- rc = ata_host_suspend(host, PMSG_SUSPEND);
+- if (rc)
+- return rc;
+-
+- if (pdata && pdata->suspend)
+- return pdata->suspend(dev);
+-
+- if (!IS_ERR(hpriv->clk))
+- clk_disable_unprepare(hpriv->clk);
+-
+- return 0;
+-}
+-
+-static int ahci_resume(struct device *dev)
+-{
+- struct ahci_platform_data *pdata = dev_get_platdata(dev);
+- struct ata_host *host = dev_get_drvdata(dev);
+- struct ahci_host_priv *hpriv = host->private_data;
+- int rc;
+-
+- if (!IS_ERR(hpriv->clk)) {
+- rc = clk_prepare_enable(hpriv->clk);
+- if (rc) {
+- dev_err(dev, "clock prepare enable failed");
+- return rc;
+- }
+- }
+-
+- if (pdata && pdata->resume) {
+- rc = pdata->resume(dev);
+- if (rc)
+- goto disable_unprepare_clk;
+- }
+-
+- if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
+- rc = ahci_reset_controller(host);
+- if (rc)
+- goto disable_unprepare_clk;
+-
+- ahci_init_controller(host);
+- }
+-
+- ata_host_resume(host);
+-
+- return 0;
+-
+-disable_unprepare_clk:
+- if (!IS_ERR(hpriv->clk))
+- clk_disable_unprepare(hpriv->clk);
+-
++disable_resources:
++ ahci_platform_disable_resources(hpriv);
+ return rc;
+ }
+-#endif
+
+-static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_suspend, ahci_resume);
++static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
++ ahci_platform_resume);
+
+ static const struct of_device_id ahci_of_match[] = {
+ { .compatible = "snps,spear-ahci", },
+ { .compatible = "snps,exynos5440-ahci", },
+ { .compatible = "ibm,476gtr-ahci", },
++ { .compatible = "snps,dwc-ahci", },
++ { .compatible = "hisilicon,hisi-ahci", },
+ {},
+ };
+ MODULE_DEVICE_TABLE(of, ahci_of_match);
+@@ -343,7 +94,6 @@
+ .of_match_table = ahci_of_match,
+ .pm = &ahci_pm_ops,
+ },
+- .id_table = ahci_devtype,
+ };
+ module_platform_driver(ahci_driver);
+
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_st.c linux-3.14.72/drivers/ata/ahci_st.c
+--- linux-3.14.72.orig/drivers/ata/ahci_st.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/ata/ahci_st.c 2016-06-19 22:11:55.085154441 +0200
+@@ -0,0 +1,245 @@
++/*
++ * Copyright (C) 2012 STMicroelectronics Limited
++ *
++ * Authors: Francesco Virlinzi <francesco.virlinzi@st.com>
++ * Alexandre Torgue <alexandre.torgue@st.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/export.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/of.h>
++#include <linux/ahci_platform.h>
++#include <linux/libata.h>
++#include <linux/reset.h>
++#include <linux/io.h>
++#include <linux/dma-mapping.h>
++
++#include "ahci.h"
++
++#define ST_AHCI_OOBR 0xbc
++#define ST_AHCI_OOBR_WE BIT(31)
++#define ST_AHCI_OOBR_CWMIN_SHIFT 24
++#define ST_AHCI_OOBR_CWMAX_SHIFT 16
++#define ST_AHCI_OOBR_CIMIN_SHIFT 8
++#define ST_AHCI_OOBR_CIMAX_SHIFT 0
++
++struct st_ahci_drv_data {
++ struct platform_device *ahci;
++ struct reset_control *pwr;
++ struct reset_control *sw_rst;
++ struct reset_control *pwr_rst;
++ struct ahci_host_priv *hpriv;
++};
++
++static void st_ahci_configure_oob(void __iomem *mmio)
++{
++ unsigned long old_val, new_val;
++
++ new_val = (0x02 << ST_AHCI_OOBR_CWMIN_SHIFT) |
++ (0x04 << ST_AHCI_OOBR_CWMAX_SHIFT) |
++ (0x08 << ST_AHCI_OOBR_CIMIN_SHIFT) |
++ (0x0C << ST_AHCI_OOBR_CIMAX_SHIFT);
++
++ old_val = readl(mmio + ST_AHCI_OOBR);
++ writel(old_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
++ writel(new_val | ST_AHCI_OOBR_WE, mmio + ST_AHCI_OOBR);
++ writel(new_val, mmio + ST_AHCI_OOBR);
++}
++
++static int st_ahci_deassert_resets(struct device *dev)
++{
++ struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev);
++ int err;
++
++ if (drv_data->pwr) {
++ err = reset_control_deassert(drv_data->pwr);
++ if (err) {
++ dev_err(dev, "unable to bring out of pwrdwn\n");
++ return err;
++ }
++ }
++
++ st_ahci_configure_oob(drv_data->hpriv->mmio);
++
++ if (drv_data->sw_rst) {
++ err = reset_control_deassert(drv_data->sw_rst);
++ if (err) {
++ dev_err(dev, "unable to bring out of sw-rst\n");
++ return err;
++ }
++ }
++
++ if (drv_data->pwr_rst) {
++ err = reset_control_deassert(drv_data->pwr_rst);
++ if (err) {
++ dev_err(dev, "unable to bring out of pwr-rst\n");
++ return err;
++ }
++ }
++
++ return 0;
++}
++
++static void st_ahci_host_stop(struct ata_host *host)
++{
++ struct ahci_host_priv *hpriv = host->private_data;
++ struct device *dev = host->dev;
++ struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev);
++ int err;
++
++ if (drv_data->pwr) {
++ err = reset_control_assert(drv_data->pwr);
++ if (err)
++ dev_err(dev, "unable to pwrdwn\n");
++ }
++
++ ahci_platform_disable_resources(hpriv);
++}
++
++static int st_ahci_probe_resets(struct platform_device *pdev)
++{
++ struct st_ahci_drv_data *drv_data = platform_get_drvdata(pdev);
++
++ drv_data->pwr = devm_reset_control_get(&pdev->dev, "pwr-dwn");
++ if (IS_ERR(drv_data->pwr)) {
++ dev_info(&pdev->dev, "power reset control not defined\n");
++ drv_data->pwr = NULL;
++ }
++
++ drv_data->sw_rst = devm_reset_control_get(&pdev->dev, "sw-rst");
++ if (IS_ERR(drv_data->sw_rst)) {
++ dev_info(&pdev->dev, "soft reset control not defined\n");
++ drv_data->sw_rst = NULL;
++ }
++
++ drv_data->pwr_rst = devm_reset_control_get(&pdev->dev, "pwr-rst");
++ if (IS_ERR(drv_data->pwr_rst)) {
++ dev_dbg(&pdev->dev, "power soft reset control not defined\n");
++ drv_data->pwr_rst = NULL;
++ }
++
++ return st_ahci_deassert_resets(&pdev->dev);
++}
++
++static struct ata_port_operations st_ahci_port_ops = {
++ .inherits = &ahci_platform_ops,
++ .host_stop = st_ahci_host_stop,
++};
++
++static const struct ata_port_info st_ahci_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &st_ahci_port_ops,
++};
++
++static int st_ahci_probe(struct platform_device *pdev)
++{
++ struct st_ahci_drv_data *drv_data;
++ struct ahci_host_priv *hpriv;
++ int err;
++
++ drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
++ if (!drv_data)
++ return -ENOMEM;
++
++ platform_set_drvdata(pdev, drv_data);
++
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
++
++ drv_data->hpriv = hpriv;
++
++ err = st_ahci_probe_resets(pdev);
++ if (err)
++ return err;
++
++ err = ahci_platform_enable_resources(hpriv);
++ if (err)
++ return err;
++
++ err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info);
++ if (err) {
++ ahci_platform_disable_resources(hpriv);
++ return err;
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int st_ahci_suspend(struct device *dev)
++{
++ struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = drv_data->hpriv;
++ int err;
++
++ err = ahci_platform_suspend_host(dev);
++ if (err)
++ return err;
++
++ if (drv_data->pwr) {
++ err = reset_control_assert(drv_data->pwr);
++ if (err) {
++ dev_err(dev, "unable to pwrdwn");
++ return err;
++ }
++ }
++
++ ahci_platform_disable_resources(hpriv);
++
++ return 0;
++}
++
++static int st_ahci_resume(struct device *dev)
++{
++ struct st_ahci_drv_data *drv_data = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = drv_data->hpriv;
++ int err;
++
++ err = ahci_platform_enable_resources(hpriv);
++ if (err)
++ return err;
++
++ err = st_ahci_deassert_resets(dev);
++ if (err) {
++ ahci_platform_disable_resources(hpriv);
++ return err;
++ }
++
++ return ahci_platform_resume_host(dev);
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(st_ahci_pm_ops, st_ahci_suspend, st_ahci_resume);
++
++static struct of_device_id st_ahci_match[] = {
++ { .compatible = "st,ahci", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, st_ahci_match);
++
++static struct platform_driver st_ahci_driver = {
++ .driver = {
++ .name = "st_ahci",
++ .owner = THIS_MODULE,
++ .pm = &st_ahci_pm_ops,
++ .of_match_table = of_match_ptr(st_ahci_match),
++ },
++ .probe = st_ahci_probe,
++ .remove = ata_platform_remove_one,
++};
++module_platform_driver(st_ahci_driver);
++
++MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
++MODULE_AUTHOR("Francesco Virlinzi <francesco.virlinzi@st.com>");
++MODULE_DESCRIPTION("STMicroelectronics SATA AHCI Driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_sunxi.c linux-3.14.72/drivers/ata/ahci_sunxi.c
+--- linux-3.14.72.orig/drivers/ata/ahci_sunxi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/ata/ahci_sunxi.c 2016-06-19 22:11:55.085154441 +0200
+@@ -0,0 +1,250 @@
++/*
++ * Allwinner sunxi AHCI SATA platform driver
++ * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
++ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
++ *
++ * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
++ * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
++ * Daniel Wang <danielwang@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ */
++
++#include <linux/ahci_platform.h>
++#include <linux/clk.h>
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include "ahci.h"
++
++#define AHCI_BISTAFR 0x00a0
++#define AHCI_BISTCR 0x00a4
++#define AHCI_BISTFCTR 0x00a8
++#define AHCI_BISTSR 0x00ac
++#define AHCI_BISTDECR 0x00b0
++#define AHCI_DIAGNR0 0x00b4
++#define AHCI_DIAGNR1 0x00b8
++#define AHCI_OOBR 0x00bc
++#define AHCI_PHYCS0R 0x00c0
++#define AHCI_PHYCS1R 0x00c4
++#define AHCI_PHYCS2R 0x00c8
++#define AHCI_TIMER1MS 0x00e0
++#define AHCI_GPARAM1R 0x00e8
++#define AHCI_GPARAM2R 0x00ec
++#define AHCI_PPARAMR 0x00f0
++#define AHCI_TESTR 0x00f4
++#define AHCI_VERSIONR 0x00f8
++#define AHCI_IDR 0x00fc
++#define AHCI_RWCR 0x00fc
++#define AHCI_P0DMACR 0x0170
++#define AHCI_P0PHYCR 0x0178
++#define AHCI_P0PHYSR 0x017c
++
++static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
++{
++ u32 reg_val;
++
++ reg_val = readl(reg);
++ reg_val &= ~(clr_val);
++ writel(reg_val, reg);
++}
++
++static void sunxi_setbits(void __iomem *reg, u32 set_val)
++{
++ u32 reg_val;
++
++ reg_val = readl(reg);
++ reg_val |= set_val;
++ writel(reg_val, reg);
++}
++
++static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
++{
++ u32 reg_val;
++
++ reg_val = readl(reg);
++ reg_val &= ~(clr_val);
++ reg_val |= set_val;
++ writel(reg_val, reg);
++}
++
++static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
++{
++ return (readl(reg) >> shift) & mask;
++}
++
++static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
++{
++ u32 reg_val;
++ int timeout;
++
++ /* This magic is from the original code */
++ writel(0, reg_base + AHCI_RWCR);
++ msleep(5);
++
++ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
++ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
++ (0x7 << 24),
++ (0x5 << 24) | BIT(23) | BIT(18));
++ sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
++ (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
++ (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
++ sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
++ sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
++ sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
++ (0x7 << 20), (0x3 << 20));
++ sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
++ (0x1f << 5), (0x19 << 5));
++ msleep(5);
++
++ sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
++
++ timeout = 250; /* Power up takes aprox 50 us */
++ do {
++ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
++ if (reg_val == 0x02)
++ break;
++
++ if (--timeout == 0) {
++ dev_err(dev, "PHY power up failed.\n");
++ return -EIO;
++ }
++ udelay(1);
++ } while (1);
++
++ sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
++
++ timeout = 100; /* Calibration takes aprox 10 us */
++ do {
++ reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
++ if (reg_val == 0x00)
++ break;
++
++ if (--timeout == 0) {
++ dev_err(dev, "PHY calibration failed.\n");
++ return -EIO;
++ }
++ udelay(1);
++ } while (1);
++
++ msleep(15);
++
++ writel(0x7, reg_base + AHCI_RWCR);
++
++ return 0;
++}
++
++static void ahci_sunxi_start_engine(struct ata_port *ap)
++{
++ void __iomem *port_mmio = ahci_port_base(ap);
++ struct ahci_host_priv *hpriv = ap->host->private_data;
++
++ /* Setup DMA before DMA start */
++ sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
++
++ /* Start DMA */
++ sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
++}
++
++static const struct ata_port_info ahci_sunxi_port_info = {
++ .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_platform_ops,
++};
++
++static int ahci_sunxi_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct ahci_host_priv *hpriv;
++ int rc;
++
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
++
++ hpriv->start_engine = ahci_sunxi_start_engine;
++
++ rc = ahci_platform_enable_resources(hpriv);
++ if (rc)
++ return rc;
++
++ rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
++ if (rc)
++ goto disable_resources;
++
++ hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
++ AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
++
++ rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info);
++ if (rc)
++ goto disable_resources;
++
++ return 0;
++
++disable_resources:
++ ahci_platform_disable_resources(hpriv);
++ return rc;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int ahci_sunxi_resume(struct device *dev)
++{
++ struct ata_host *host = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ int rc;
++
++ rc = ahci_platform_enable_resources(hpriv);
++ if (rc)
++ return rc;
++
++ rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
++ if (rc)
++ goto disable_resources;
++
++ rc = ahci_platform_resume_host(dev);
++ if (rc)
++ goto disable_resources;
++
++ return 0;
++
++disable_resources:
++ ahci_platform_disable_resources(hpriv);
++ return rc;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
++ ahci_sunxi_resume);
++
++static const struct of_device_id ahci_sunxi_of_match[] = {
++ { .compatible = "allwinner,sun4i-a10-ahci", },
++ { },
++};
++MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
++
++static struct platform_driver ahci_sunxi_driver = {
++ .probe = ahci_sunxi_probe,
++ .remove = ata_platform_remove_one,
++ .driver = {
++ .name = "ahci-sunxi",
++ .owner = THIS_MODULE,
++ .of_match_table = ahci_sunxi_of_match,
++ .pm = &ahci_sunxi_pm_ops,
++ },
++};
++module_platform_driver(ahci_sunxi_driver);
++
++MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
++MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_tegra.c linux-3.14.72/drivers/ata/ahci_tegra.c
+--- linux-3.14.72.orig/drivers/ata/ahci_tegra.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/ata/ahci_tegra.c 2016-06-19 22:11:55.085154441 +0200
+@@ -0,0 +1,376 @@
++/*
++ * drivers/ata/ahci_tegra.c
++ *
++ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
++ *
++ * Author:
++ * Mikko Perttunen <mperttunen@nvidia.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/ahci_platform.h>
++#include <linux/reset.h>
++#include <linux/errno.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/tegra-powergate.h>
++#include <linux/regulator/consumer.h>
++#include "ahci.h"
++
++#define SATA_CONFIGURATION_0 0x180
++#define SATA_CONFIGURATION_EN_FPCI BIT(0)
++
++#define SCFG_OFFSET 0x1000
++
++#define T_SATA0_CFG_1 0x04
++#define T_SATA0_CFG_1_IO_SPACE BIT(0)
++#define T_SATA0_CFG_1_MEMORY_SPACE BIT(1)
++#define T_SATA0_CFG_1_BUS_MASTER BIT(2)
++#define T_SATA0_CFG_1_SERR BIT(8)
++
++#define T_SATA0_CFG_9 0x24
++#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
++
++#define SATA_FPCI_BAR5 0x94
++#define SATA_FPCI_BAR5_START_SHIFT 4
++
++#define SATA_INTR_MASK 0x188
++#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
++
++#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
++
++#define T_SATA0_BKDOOR_CC 0x4a4
++
++#define T_SATA0_CFG_SATA 0x54c
++#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
++
++#define T_SATA0_CFG_MISC 0x550
++
++#define T_SATA0_INDEX 0x680
++
++#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
++#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
++#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
++#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
++#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
++
++#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
++#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
++#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
++#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
++#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
++
++#define T_SATA0_CHX_PHY_CTRL2 0x69c
++#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
++
++#define T_SATA0_CHX_PHY_CTRL11 0x6d0
++#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
++
++#define FUSE_SATA_CALIB 0x124
++#define FUSE_SATA_CALIB_MASK 0x3
++
++struct sata_pad_calibration {
++ u8 gen1_tx_amp;
++ u8 gen1_tx_peak;
++ u8 gen2_tx_amp;
++ u8 gen2_tx_peak;
++};
++
++static const struct sata_pad_calibration tegra124_pad_calibration[] = {
++ {0x18, 0x04, 0x18, 0x0a},
++ {0x0e, 0x04, 0x14, 0x0a},
++ {0x0e, 0x07, 0x1a, 0x0e},
++ {0x14, 0x0e, 0x1a, 0x0e},
++};
++
++struct tegra_ahci_priv {
++ struct platform_device *pdev;
++ void __iomem *sata_regs;
++ struct reset_control *sata_rst;
++ struct reset_control *sata_oob_rst;
++ struct reset_control *sata_cold_rst;
++ /* Needs special handling, cannot use ahci_platform */
++ struct clk *sata_clk;
++ struct regulator_bulk_data supplies[5];
++};
++
++static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
++{
++ struct tegra_ahci_priv *tegra = hpriv->plat_data;
++ int ret;
++
++ ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies),
++ tegra->supplies);
++ if (ret)
++ return ret;
++
++ ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA,
++ tegra->sata_clk,
++ tegra->sata_rst);
++ if (ret)
++ goto disable_regulators;
++
++ reset_control_assert(tegra->sata_oob_rst);
++ reset_control_assert(tegra->sata_cold_rst);
++
++ ret = ahci_platform_enable_resources(hpriv);
++ if (ret)
++ goto disable_power;
++
++ reset_control_deassert(tegra->sata_cold_rst);
++ reset_control_deassert(tegra->sata_oob_rst);
++
++ return 0;
++
++disable_power:
++ clk_disable_unprepare(tegra->sata_clk);
++
++ tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
++
++disable_regulators:
++ regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
++
++ return ret;
++}
++
++static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
++{
++ struct tegra_ahci_priv *tegra = hpriv->plat_data;
++
++ ahci_platform_disable_resources(hpriv);
++
++ reset_control_assert(tegra->sata_rst);
++ reset_control_assert(tegra->sata_oob_rst);
++ reset_control_assert(tegra->sata_cold_rst);
++
++ clk_disable_unprepare(tegra->sata_clk);
++ tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
++
++ regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies);
++}
++
++static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
++{
++ struct tegra_ahci_priv *tegra = hpriv->plat_data;
++ int ret;
++ unsigned int val;
++ struct sata_pad_calibration calib;
++
++ ret = tegra_ahci_power_on(hpriv);
++ if (ret) {
++ dev_err(&tegra->pdev->dev,
++ "failed to power on AHCI controller: %d\n", ret);
++ return ret;
++ }
++
++ val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
++ val |= SATA_CONFIGURATION_EN_FPCI;
++ writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
++
++ /* Pad calibration */
++
++ /* FIXME Always use calibration 0. Change this to read the calibration
++ * fuse once the fuse driver has landed. */
++ val = 0;
++
++ calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
++
++ writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
++
++ val = readl(tegra->sata_regs +
++ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
++ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
++ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
++ val |= calib.gen1_tx_amp <<
++ T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
++ val |= calib.gen1_tx_peak <<
++ T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
++ writel(val, tegra->sata_regs + SCFG_OFFSET +
++ T_SATA0_CHX_PHY_CTRL1_GEN1);
++
++ val = readl(tegra->sata_regs +
++ SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
++ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
++ val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
++ val |= calib.gen2_tx_amp <<
++ T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
++ val |= calib.gen2_tx_peak <<
++ T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
++ writel(val, tegra->sata_regs + SCFG_OFFSET +
++ T_SATA0_CHX_PHY_CTRL1_GEN2);
++
++ writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
++ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
++ writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
++ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
++
++ writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
++
++ /* Program controller device ID */
++
++ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
++ val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
++ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
++
++ writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
++
++ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
++ val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
++ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
++
++ /* Enable IO & memory access, bus master mode */
++
++ val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
++ val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
++ T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR;
++ writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
++
++ /* Program SATA MMIO */
++
++ writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT,
++ tegra->sata_regs + SATA_FPCI_BAR5);
++
++ writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT,
++ tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
++
++ /* Unmask SATA interrupts */
++
++ val = readl(tegra->sata_regs + SATA_INTR_MASK);
++ val |= SATA_INTR_MASK_IP_INT_MASK;
++ writel(val, tegra->sata_regs + SATA_INTR_MASK);
++
++ return 0;
++}
++
++static void tegra_ahci_controller_deinit(struct ahci_host_priv *hpriv)
++{
++ tegra_ahci_power_off(hpriv);
++}
++
++static void tegra_ahci_host_stop(struct ata_host *host)
++{
++ struct ahci_host_priv *hpriv = host->private_data;
++
++ tegra_ahci_controller_deinit(hpriv);
++}
++
++static struct ata_port_operations ahci_tegra_port_ops = {
++ .inherits = &ahci_ops,
++ .host_stop = tegra_ahci_host_stop,
++};
++
++static const struct ata_port_info ahci_tegra_port_info = {
++ .flags = AHCI_FLAG_COMMON,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &ahci_tegra_port_ops,
++};
++
++static const struct of_device_id tegra_ahci_of_match[] = {
++ { .compatible = "nvidia,tegra124-ahci" },
++ {}
++};
++MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
++
++static int tegra_ahci_probe(struct platform_device *pdev)
++{
++ struct ahci_host_priv *hpriv;
++ struct tegra_ahci_priv *tegra;
++ struct resource *res;
++ int ret;
++
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
++
++ tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
++ if (!tegra)
++ return -ENOMEM;
++
++ hpriv->plat_data = tegra;
++
++ tegra->pdev = pdev;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(tegra->sata_regs))
++ return PTR_ERR(tegra->sata_regs);
++
++ tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
++ if (IS_ERR(tegra->sata_rst)) {
++ dev_err(&pdev->dev, "Failed to get sata reset\n");
++ return PTR_ERR(tegra->sata_rst);
++ }
++
++ tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob");
++ if (IS_ERR(tegra->sata_oob_rst)) {
++ dev_err(&pdev->dev, "Failed to get sata-oob reset\n");
++ return PTR_ERR(tegra->sata_oob_rst);
++ }
++
++ tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");
++ if (IS_ERR(tegra->sata_cold_rst)) {
++ dev_err(&pdev->dev, "Failed to get sata-cold reset\n");
++ return PTR_ERR(tegra->sata_cold_rst);
++ }
++
++ tegra->sata_clk = devm_clk_get(&pdev->dev, "sata");
++ if (IS_ERR(tegra->sata_clk)) {
++ dev_err(&pdev->dev, "Failed to get sata clock\n");
++ return PTR_ERR(tegra->sata_clk);
++ }
++
++ tegra->supplies[0].supply = "avdd";
++ tegra->supplies[1].supply = "hvdd";
++ tegra->supplies[2].supply = "vddio";
++ tegra->supplies[3].supply = "target-5v";
++ tegra->supplies[4].supply = "target-12v";
++
++ ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies),
++ tegra->supplies);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to get regulators\n");
++ return ret;
++ }
++
++ ret = tegra_ahci_controller_init(hpriv);
++ if (ret)
++ return ret;
++
++ ret = ahci_platform_init_host(pdev, hpriv, &ahci_tegra_port_info);
++ if (ret)
++ goto deinit_controller;
++
++ return 0;
++
++deinit_controller:
++ tegra_ahci_controller_deinit(hpriv);
++
++ return ret;
++};
++
++static struct platform_driver tegra_ahci_driver = {
++ .probe = tegra_ahci_probe,
++ .remove = ata_platform_remove_one,
++ .driver = {
++ .name = "tegra-ahci",
++ .of_match_table = tegra_ahci_of_match,
++ },
++ /* LP0 suspend support not implemented */
++};
++module_platform_driver(tegra_ahci_driver);
++
++MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
++MODULE_DESCRIPTION("Tegra124 AHCI SATA driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/ata/ahci_xgene.c linux-3.14.72/drivers/ata/ahci_xgene.c
+--- linux-3.14.72.orig/drivers/ata/ahci_xgene.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/ata/ahci_xgene.c 2016-06-19 22:11:55.085154441 +0200
+@@ -0,0 +1,518 @@
++/*
++ * AppliedMicro X-Gene SoC SATA Host Controller Driver
++ *
++ * Copyright (c) 2014, Applied Micro Circuits Corporation
++ * Author: Loc Ho <lho@apm.com>
++ * Tuan Phan <tphan@apm.com>
++ * Suman Tripathi <stripathi@apm.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * NOTE: PM support is not currently available.
++ *
++ */
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/ahci_platform.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/phy/phy.h>
++#include "ahci.h"
++
++/* Max # of disk per a controller */
++#define MAX_AHCI_CHN_PERCTR 2
++
++/* MUX CSR */
++#define SATA_ENET_CONFIG_REG 0x00000000
++#define CFG_SATA_ENET_SELECT_MASK 0x00000001
++
++/* SATA core host controller CSR */
++#define SLVRDERRATTRIBUTES 0x00000000
++#define SLVWRERRATTRIBUTES 0x00000004
++#define MSTRDERRATTRIBUTES 0x00000008
++#define MSTWRERRATTRIBUTES 0x0000000c
++#define BUSCTLREG 0x00000014
++#define IOFMSTRWAUX 0x00000018
++#define INTSTATUSMASK 0x0000002c
++#define ERRINTSTATUS 0x00000030
++#define ERRINTSTATUSMASK 0x00000034
++
++/* SATA host AHCI CSR */
++#define PORTCFG 0x000000a4
++#define PORTADDR_SET(dst, src) \
++ (((dst) & ~0x0000003f) | (((u32)(src)) & 0x0000003f))
++#define PORTPHY1CFG 0x000000a8
++#define PORTPHY1CFG_FRCPHYRDY_SET(dst, src) \
++ (((dst) & ~0x00100000) | (((u32)(src) << 0x14) & 0x00100000))
++#define PORTPHY2CFG 0x000000ac
++#define PORTPHY3CFG 0x000000b0
++#define PORTPHY4CFG 0x000000b4
++#define PORTPHY5CFG 0x000000b8
++#define SCTL0 0x0000012C
++#define PORTPHY5CFG_RTCHG_SET(dst, src) \
++ (((dst) & ~0xfff00000) | (((u32)(src) << 0x14) & 0xfff00000))
++#define PORTAXICFG_EN_CONTEXT_SET(dst, src) \
++ (((dst) & ~0x01000000) | (((u32)(src) << 0x18) & 0x01000000))
++#define PORTAXICFG 0x000000bc
++#define PORTAXICFG_OUTTRANS_SET(dst, src) \
++ (((dst) & ~0x00f00000) | (((u32)(src) << 0x14) & 0x00f00000))
++#define PORTRANSCFG 0x000000c8
++#define PORTRANSCFG_RXWM_SET(dst, src) \
++ (((dst) & ~0x0000007f) | (((u32)(src)) & 0x0000007f))
++
++/* SATA host controller AXI CSR */
++#define INT_SLV_TMOMASK 0x00000010
++
++/* SATA diagnostic CSR */
++#define CFG_MEM_RAM_SHUTDOWN 0x00000070
++#define BLOCK_MEM_RDY 0x00000074
++
++struct xgene_ahci_context {
++ struct ahci_host_priv *hpriv;
++ struct device *dev;
++ u8 last_cmd[MAX_AHCI_CHN_PERCTR]; /* tracking the last command issued*/
++ void __iomem *csr_core; /* Core CSR address of IP */
++ void __iomem *csr_diag; /* Diag CSR address of IP */
++ void __iomem *csr_axi; /* AXI CSR address of IP */
++ void __iomem *csr_mux; /* MUX CSR address of IP */
++};
++
++static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
++{
++ dev_dbg(ctx->dev, "Release memory from shutdown\n");
++ writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
++ readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
++ msleep(1); /* reset may take up to 1ms */
++ if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
++ dev_err(ctx->dev, "failed to release memory from shutdown\n");
++ return -ENODEV;
++ }
++ return 0;
++}
++
++/**
++ * xgene_ahci_restart_engine - Restart the dma engine.
++ * @ap : ATA port of interest
++ *
++ * Restarts the dma engine inside the controller.
++ */
++static int xgene_ahci_restart_engine(struct ata_port *ap)
++{
++ struct ahci_host_priv *hpriv = ap->host->private_data;
++
++ ahci_stop_engine(ap);
++ ahci_start_fis_rx(ap);
++ hpriv->start_engine(ap);
++
++ return 0;
++}
++
++/**
++ * xgene_ahci_qc_issue - Issue commands to the device
++ * @qc: Command to issue
++ *
++ * Due to Hardware errata for IDENTIFY DEVICE command, the controller cannot
++ * clear the BSY bit after receiving the PIO setup FIS. This results in the dma
++ * state machine goes into the CMFatalErrorUpdate state and locks up. By
++ * restarting the dma engine, it removes the controller out of lock up state.
++ */
++static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
++{
++ struct ata_port *ap = qc->ap;
++ struct ahci_host_priv *hpriv = ap->host->private_data;
++ struct xgene_ahci_context *ctx = hpriv->plat_data;
++ int rc = 0;
++
++ if (unlikely(ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA))
++ xgene_ahci_restart_engine(ap);
++
++ rc = ahci_qc_issue(qc);
++
++ /* Save the last command issued */
++ ctx->last_cmd[ap->port_no] = qc->tf.command;
++
++ return rc;
++}
++
++/**
++ * xgene_ahci_read_id - Read ID data from the specified device
++ * @dev: device
++ * @tf: proposed taskfile
++ * @id: data buffer
++ *
++ * This custom read ID function is required due to the fact that the HW
++ * does not support DEVSLP.
++ */
++static unsigned int xgene_ahci_read_id(struct ata_device *dev,
++ struct ata_taskfile *tf, u16 *id)
++{
++ u32 err_mask;
++
++ err_mask = ata_do_dev_read_id(dev, tf, id);
++ if (err_mask)
++ return err_mask;
++
++ /*
++ * Mask reserved area. Word78 spec of Link Power Management
++ * bit15-8: reserved
++ * bit7: NCQ autosence
++ * bit6: Software settings preservation supported
++ * bit5: reserved
++ * bit4: In-order sata delivery supported
++ * bit3: DIPM requests supported
++ * bit2: DMA Setup FIS Auto-Activate optimization supported
++ * bit1: DMA Setup FIX non-Zero buffer offsets supported
++ * bit0: Reserved
++ *
++ * Clear reserved bit 8 (DEVSLP bit) as we don't support DEVSLP
++ */
++ id[ATA_ID_FEATURE_SUPP] &= ~(1 << 8);
++
++ return 0;
++}
++
++static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
++{
++ void __iomem *mmio = ctx->hpriv->mmio;
++ u32 val;
++
++ dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
++ mmio, channel);
++ val = readl(mmio + PORTCFG);
++ val = PORTADDR_SET(val, channel == 0 ? 2 : 3);
++ writel(val, mmio + PORTCFG);
++ readl(mmio + PORTCFG); /* Force a barrier */
++ /* Disable fix rate */
++ writel(0x0001fffe, mmio + PORTPHY1CFG);
++ readl(mmio + PORTPHY1CFG); /* Force a barrier */
++ writel(0x28183219, mmio + PORTPHY2CFG);
++ readl(mmio + PORTPHY2CFG); /* Force a barrier */
++ writel(0x13081008, mmio + PORTPHY3CFG);
++ readl(mmio + PORTPHY3CFG); /* Force a barrier */
++ writel(0x00480815, mmio + PORTPHY4CFG);
++ readl(mmio + PORTPHY4CFG); /* Force a barrier */
++ /* Set window negotiation */
++ val = readl(mmio + PORTPHY5CFG);
++ val = PORTPHY5CFG_RTCHG_SET(val, 0x300);
++ writel(val, mmio + PORTPHY5CFG);
++ readl(mmio + PORTPHY5CFG); /* Force a barrier */
++ val = readl(mmio + PORTAXICFG);
++ val = PORTAXICFG_EN_CONTEXT_SET(val, 0x1); /* Enable context mgmt */
++ val = PORTAXICFG_OUTTRANS_SET(val, 0xe); /* Set outstanding */
++ writel(val, mmio + PORTAXICFG);
++ readl(mmio + PORTAXICFG); /* Force a barrier */
++ /* Set the watermark threshold of the receive FIFO */
++ val = readl(mmio + PORTRANSCFG);
++ val = PORTRANSCFG_RXWM_SET(val, 0x30);
++ writel(val, mmio + PORTRANSCFG);
++}
++
++/**
++ * xgene_ahci_do_hardreset - Issue the actual COMRESET
++ * @link: link to reset
++ * @deadline: deadline jiffies for the operation
++ * @online: Return value to indicate if device online
++ *
++ * Due to the limitation of the hardware PHY, a difference set of setting is
++ * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps),
++ * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will
++ * report disparity error and etc. In addition, during COMRESET, there can
++ * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and
++ * SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following
++ * algorithm is followed to proper configure the hardware PHY during COMRESET:
++ *
++ * Alg Part 1:
++ * 1. Start the PHY at Gen3 speed (default setting)
++ * 2. Issue the COMRESET
++ * 3. If no link, go to Alg Part 3
++ * 4. If link up, determine if the negotiated speed matches the PHY
++ * configured speed
++ * 5. If they matched, go to Alg Part 2
++ * 6. If they do not matched and first time, configure the PHY for the linked
++ * up disk speed and repeat step 2
++ * 7. Go to Alg Part 2
++ *
++ * Alg Part 2:
++ * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error
++ * reported in the register PORT_SCR_ERR, then reset the PHY receiver line
++ * 2. Go to Alg Part 3
++ *
++ * Alg Part 3:
++ * 1. Clear any pending from register PORT_SCR_ERR.
++ *
++ * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition
++ * and until the underlying PHY supports an method to reset the receiver
++ * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors,
++ * an warning message will be printed.
++ */
++static int xgene_ahci_do_hardreset(struct ata_link *link,
++ unsigned long deadline, bool *online)
++{
++ const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
++ struct ata_port *ap = link->ap;
++ struct ahci_host_priv *hpriv = ap->host->private_data;
++ struct xgene_ahci_context *ctx = hpriv->plat_data;
++ struct ahci_port_priv *pp = ap->private_data;
++ u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
++ void __iomem *port_mmio = ahci_port_base(ap);
++ struct ata_taskfile tf;
++ int rc;
++ u32 val;
++
++ /* clear D2H reception area to properly wait for D2H FIS */
++ ata_tf_init(link->device, &tf);
++ tf.command = ATA_BUSY;
++ ata_tf_to_fis(&tf, 0, 0, d2h_fis);
++ rc = sata_link_hardreset(link, timing, deadline, online,
++ ahci_check_ready);
++
++ val = readl(port_mmio + PORT_SCR_ERR);
++ if (val & (SERR_DISPARITY | SERR_10B_8B_ERR))
++ dev_warn(ctx->dev, "link has error\n");
++
++ /* clear all errors if any pending */
++ val = readl(port_mmio + PORT_SCR_ERR);
++ writel(val, port_mmio + PORT_SCR_ERR);
++
++ return rc;
++}
++
++static int xgene_ahci_hardreset(struct ata_link *link, unsigned int *class,
++ unsigned long deadline)
++{
++ struct ata_port *ap = link->ap;
++ struct ahci_host_priv *hpriv = ap->host->private_data;
++ void __iomem *port_mmio = ahci_port_base(ap);
++ bool online;
++ int rc;
++ u32 portcmd_saved;
++ u32 portclb_saved;
++ u32 portclbhi_saved;
++ u32 portrxfis_saved;
++ u32 portrxfishi_saved;
++
++ /* As hardreset resets these CSR, save it to restore later */
++ portcmd_saved = readl(port_mmio + PORT_CMD);
++ portclb_saved = readl(port_mmio + PORT_LST_ADDR);
++ portclbhi_saved = readl(port_mmio + PORT_LST_ADDR_HI);
++ portrxfis_saved = readl(port_mmio + PORT_FIS_ADDR);
++ portrxfishi_saved = readl(port_mmio + PORT_FIS_ADDR_HI);
++
++ ahci_stop_engine(ap);
++
++ rc = xgene_ahci_do_hardreset(link, deadline, &online);
++
++ /* As controller hardreset clears them, restore them */
++ writel(portcmd_saved, port_mmio + PORT_CMD);
++ writel(portclb_saved, port_mmio + PORT_LST_ADDR);
++ writel(portclbhi_saved, port_mmio + PORT_LST_ADDR_HI);
++ writel(portrxfis_saved, port_mmio + PORT_FIS_ADDR);
++ writel(portrxfishi_saved, port_mmio + PORT_FIS_ADDR_HI);
++
++ hpriv->start_engine(ap);
++
++ if (online)
++ *class = ahci_dev_classify(ap);
++
++ return rc;
++}
++
++static void xgene_ahci_host_stop(struct ata_host *host)
++{
++ struct ahci_host_priv *hpriv = host->private_data;
++
++ ahci_platform_disable_resources(hpriv);
++}
++
++static struct ata_port_operations xgene_ahci_ops = {
++ .inherits = &ahci_ops,
++ .host_stop = xgene_ahci_host_stop,
++ .hardreset = xgene_ahci_hardreset,
++ .read_id = xgene_ahci_read_id,
++ .qc_issue = xgene_ahci_qc_issue,
++};
++
++static const struct ata_port_info xgene_ahci_port_info = {
++ .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
++ .pio_mask = ATA_PIO4,
++ .udma_mask = ATA_UDMA6,
++ .port_ops = &xgene_ahci_ops,
++};
++
++static int xgene_ahci_hw_init(struct ahci_host_priv *hpriv)
++{
++ struct xgene_ahci_context *ctx = hpriv->plat_data;
++ int i;
++ int rc;
++ u32 val;
++
++ /* Remove IP RAM out of shutdown */
++ rc = xgene_ahci_init_memram(ctx);
++ if (rc)
++ return rc;
++
++ for (i = 0; i < MAX_AHCI_CHN_PERCTR; i++)
++ xgene_ahci_set_phy_cfg(ctx, i);
++
++ /* AXI disable Mask */
++ writel(0xffffffff, hpriv->mmio + HOST_IRQ_STAT);
++ readl(hpriv->mmio + HOST_IRQ_STAT); /* Force a barrier */
++ writel(0, ctx->csr_core + INTSTATUSMASK);
++ val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
++ dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
++ INTSTATUSMASK, val);
++
++ writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
++ readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
++ writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
++ readl(ctx->csr_axi + INT_SLV_TMOMASK);
++
++ /* Enable AXI Interrupt */
++ writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
++ writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
++ writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
++ writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
++
++ /* Enable coherency */
++ val = readl(ctx->csr_core + BUSCTLREG);
++ val &= ~0x00000002; /* Enable write coherency */
++ val &= ~0x00000001; /* Enable read coherency */
++ writel(val, ctx->csr_core + BUSCTLREG);
++
++ val = readl(ctx->csr_core + IOFMSTRWAUX);
++ val |= (1 << 3); /* Enable read coherency */
++ val |= (1 << 9); /* Enable write coherency */
++ writel(val, ctx->csr_core + IOFMSTRWAUX);
++ val = readl(ctx->csr_core + IOFMSTRWAUX);
++ dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
++ IOFMSTRWAUX, val);
++
++ return rc;
++}
++
++static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
++{
++ u32 val;
++
++ /* Check for optional MUX resource */
++ if (IS_ERR(ctx->csr_mux))
++ return 0;
++
++ val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
++ val &= ~CFG_SATA_ENET_SELECT_MASK;
++ writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
++ val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
++ return val & CFG_SATA_ENET_SELECT_MASK ? -1 : 0;
++}
++
++static int xgene_ahci_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct ahci_host_priv *hpriv;
++ struct xgene_ahci_context *ctx;
++ struct resource *res;
++ int rc;
++
++ hpriv = ahci_platform_get_resources(pdev);
++ if (IS_ERR(hpriv))
++ return PTR_ERR(hpriv);
++
++ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
++ if (!ctx)
++ return -ENOMEM;
++
++ hpriv->plat_data = ctx;
++ ctx->hpriv = hpriv;
++ ctx->dev = dev;
++
++ /* Retrieve the IP core resource */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ ctx->csr_core = devm_ioremap_resource(dev, res);
++ if (IS_ERR(ctx->csr_core))
++ return PTR_ERR(ctx->csr_core);
++
++ /* Retrieve the IP diagnostic resource */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
++ ctx->csr_diag = devm_ioremap_resource(dev, res);
++ if (IS_ERR(ctx->csr_diag))
++ return PTR_ERR(ctx->csr_diag);
++
++ /* Retrieve the IP AXI resource */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
++ ctx->csr_axi = devm_ioremap_resource(dev, res);
++ if (IS_ERR(ctx->csr_axi))
++ return PTR_ERR(ctx->csr_axi);
++
++ /* Retrieve the optional IP mux resource */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 4);
++ ctx->csr_mux = devm_ioremap_resource(dev, res);
++
++ dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
++ hpriv->mmio);
++
++ /* Select ATA */
++ if ((rc = xgene_ahci_mux_select(ctx))) {
++ dev_err(dev, "SATA mux selection failed error %d\n", rc);
++ return -ENODEV;
++ }
++
++ /* Due to errata, HW requires full toggle transition */
++ rc = ahci_platform_enable_clks(hpriv);
++ if (rc)
++ goto disable_resources;
++ ahci_platform_disable_clks(hpriv);
++
++ rc = ahci_platform_enable_resources(hpriv);
++ if (rc)
++ goto disable_resources;
++
++ /* Configure the host controller */
++ xgene_ahci_hw_init(hpriv);
++
++ hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ;
++
++ rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
++ if (rc)
++ goto disable_resources;
++
++ dev_dbg(dev, "X-Gene SATA host controller initialized\n");
++ return 0;
++
++disable_resources:
++ ahci_platform_disable_resources(hpriv);
++ return rc;
++}
++
++static const struct of_device_id xgene_ahci_of_match[] = {
++ {.compatible = "apm,xgene-ahci"},
++ {},
++};
++MODULE_DEVICE_TABLE(of, xgene_ahci_of_match);
++
++static struct platform_driver xgene_ahci_driver = {
++ .probe = xgene_ahci_probe,
++ .remove = ata_platform_remove_one,
++ .driver = {
++ .name = "xgene-ahci",
++ .owner = THIS_MODULE,
++ .of_match_table = xgene_ahci_of_match,
++ },
++};
++
++module_platform_driver(xgene_ahci_driver);
++
++MODULE_DESCRIPTION("APM X-Gene AHCI SATA driver");
++MODULE_AUTHOR("Loc Ho <lho@apm.com>");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("0.4");
+diff -Nur linux-3.14.72.orig/drivers/ata/ata_generic.c linux-3.14.72/drivers/ata/ata_generic.c
+--- linux-3.14.72.orig/drivers/ata/ata_generic.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/ata_generic.c 2016-06-19 22:11:55.085154441 +0200
+@@ -19,7 +19,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -242,7 +241,7 @@
+ .id_table = ata_generic,
+ .probe = ata_generic_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/ata_piix.c linux-3.14.72/drivers/ata/ata_piix.c
+--- linux-3.14.72.orig/drivers/ata/ata_piix.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/ata_piix.c 2016-06-19 22:11:55.085154441 +0200
+@@ -838,7 +838,7 @@
+ return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int piix_broken_suspend(void)
+ {
+ static const struct dmi_system_id sysids[] = {
+@@ -1775,7 +1775,7 @@
+ .id_table = piix_pci_tbl,
+ .probe = piix_init_one,
+ .remove = piix_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = piix_pci_device_suspend,
+ .resume = piix_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/Kconfig linux-3.14.72/drivers/ata/Kconfig
+--- linux-3.14.72.orig/drivers/ata/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/Kconfig 2016-06-19 22:11:55.085154441 +0200
+@@ -60,7 +60,7 @@
+
+ config SATA_ZPODD
+ bool "SATA Zero Power Optical Disc Drive (ZPODD) support"
+- depends on ATA_ACPI
++ depends on ATA_ACPI && PM_RUNTIME
+ default n
+ help
+ This option adds support for SATA Zero Power Optical Disc
+@@ -97,15 +97,65 @@
+
+ If unsure, say N.
+
++config AHCI_DA850
++ tristate "DaVinci DA850 AHCI SATA support"
++ depends on ARCH_DAVINCI_DA850
++ help
++ This option enables support for the DaVinci DA850 SoC's
++ onboard AHCI SATA.
++
++ If unsure, say N.
++
++config AHCI_ST
++ tristate "ST AHCI SATA support"
++ depends on ARCH_STI
++ help
++ This option enables support for ST AHCI SATA controller.
++
++ If unsure, say N.
++
+ config AHCI_IMX
+ tristate "Freescale i.MX AHCI SATA support"
+- depends on SATA_AHCI_PLATFORM && MFD_SYSCON
++ depends on MFD_SYSCON && (ARCH_MXC || COMPILE_TEST)
+ help
+ This option enables support for the Freescale i.MX SoC's
+ onboard AHCI SATA.
+
+ If unsure, say N.
+
++config AHCI_MVEBU
++ tristate "Marvell EBU AHCI SATA support"
++ depends on ARCH_MVEBU
++ help
++ This option enables support for the Marvebu EBU SoC's
++ onboard AHCI SATA.
++
++ If unsure, say N.
++
++config AHCI_SUNXI
++ tristate "Allwinner sunxi AHCI SATA support"
++ depends on ARCH_SUNXI
++ help
++ This option enables support for the Allwinner sunxi SoC's
++ onboard AHCI SATA.
++
++ If unsure, say N.
++
++config AHCI_TEGRA
++ tristate "NVIDIA Tegra124 AHCI SATA support"
++ depends on ARCH_TEGRA
++ help
++ This option enables support for the NVIDIA Tegra124 SoC's
++ onboard AHCI SATA.
++
++ If unsure, say N.
++
++config AHCI_XGENE
++ tristate "APM X-Gene 6.0Gbps AHCI SATA host controller support"
++ depends on PHY_XGENE
++ help
++ This option enables support for APM X-Gene SoC SATA host controller.
++
+ config SATA_FSL
+ tristate "Freescale 3.0Gbps SATA support"
+ depends on FSL_SOC
+@@ -239,6 +289,7 @@
+
+ config SATA_HIGHBANK
+ tristate "Calxeda Highbank SATA support"
++ depends on ARCH_HIGHBANK || COMPILE_TEST
+ help
+ This option enables support for the Calxeda Highbank SoC's
+ onboard SATA.
+@@ -273,6 +324,7 @@
+
+ config SATA_RCAR
+ tristate "Renesas R-Car SATA support"
++ depends on ARCH_SHMOBILE || COMPILE_TEST
+ help
+ This option enables support for Renesas R-Car Serial ATA.
+
+@@ -352,6 +404,7 @@
+
+ config PATA_ARASAN_CF
+ tristate "ARASAN CompactFlash PATA Controller Support"
++ depends on ARCH_SPEAR13XX || COMPILE_TEST
+ depends on DMADEVICES
+ select DMA_ENGINE
+ help
+@@ -403,7 +456,7 @@
+
+ config PATA_CS5520
+ tristate "CS5510/5520 PATA support"
+- depends on PCI
++ depends on PCI && (X86_32 || COMPILE_TEST)
+ help
+ This option enables support for the Cyrix 5510/5520
+ companion chip used with the MediaGX/Geode processor family.
+@@ -412,7 +465,7 @@
+
+ config PATA_CS5530
+ tristate "CS5530 PATA support"
+- depends on PCI
++ depends on PCI && (X86_32 || COMPILE_TEST)
+ help
+ This option enables support for the Cyrix/NatSemi/AMD CS5530
+ companion chip used with the MediaGX/Geode processor family.
+@@ -421,7 +474,7 @@
+
+ config PATA_CS5535
+ tristate "CS5535 PATA support (Experimental)"
+- depends on PCI && X86 && !X86_64
++ depends on PCI && X86_32
+ help
+ This option enables support for the NatSemi/AMD CS5535
+ companion chip used with the Geode processor family.
+@@ -430,7 +483,7 @@
+
+ config PATA_CS5536
+ tristate "CS5536 PATA support"
+- depends on PCI
++ depends on PCI && (X86_32 || MIPS || COMPILE_TEST)
+ help
+ This option enables support for the AMD CS5536
+ companion chip used with the Geode LX processor family.
+@@ -666,7 +719,7 @@
+
+ config PATA_SC1200
+ tristate "SC1200 PATA support"
+- depends on PCI
++ depends on PCI && (X86_32 || COMPILE_TEST)
+ help
+ This option enables support for the NatSemi/AMD SC1200 SoC
+ companion chip used with the Geode processor family.
+@@ -778,7 +831,7 @@
+
+ config PATA_AT91
+ tristate "PATA support for AT91SAM9260"
+- depends on ARM && ARCH_AT91
++ depends on ARM && SOC_AT91SAM9
+ help
+ This option enables support for IDE devices on the Atmel AT91SAM9260 SoC.
+
+diff -Nur linux-3.14.72.orig/drivers/ata/libahci.c linux-3.14.72/drivers/ata/libahci.c
+--- linux-3.14.72.orig/drivers/ata/libahci.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/libahci.c 2016-06-19 22:11:55.085154441 +0200
+@@ -35,7 +35,6 @@
+ #include <linux/kernel.h>
+ #include <linux/gfp.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -69,7 +68,6 @@
+
+ static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
+ static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
+-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
+ static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
+ static int ahci_port_start(struct ata_port *ap);
+ static void ahci_port_stop(struct ata_port *ap);
+@@ -384,8 +382,6 @@
+ * ahci_save_initial_config - Save and fixup initial config values
+ * @dev: target AHCI device
+ * @hpriv: host private area to store config values
+- * @force_port_map: force port map to a specified value
+- * @mask_port_map: mask out particular bits from port map
+ *
+ * Some registers containing configuration info might be setup by
+ * BIOS and might be cleared on reset. This function saves the
+@@ -394,13 +390,13 @@
+ *
+ * If inconsistent, config values are fixed up by this function.
+ *
++ * If it is not set already this function sets hpriv->start_engine to
++ * ahci_start_engine.
++ *
+ * LOCKING:
+ * None.
+ */
+-void ahci_save_initial_config(struct device *dev,
+- struct ahci_host_priv *hpriv,
+- unsigned int force_port_map,
+- unsigned int mask_port_map)
++void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
+ {
+ void __iomem *mmio = hpriv->mmio;
+ u32 cap, cap2, vers, port_map;
+@@ -455,17 +451,22 @@
+ cap |= HOST_CAP_FBS;
+ }
+
+- if (force_port_map && port_map != force_port_map) {
++ if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
++ dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
++ cap &= ~HOST_CAP_FBS;
++ }
++
++ if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
+ dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
+- port_map, force_port_map);
+- port_map = force_port_map;
++ port_map, hpriv->force_port_map);
++ port_map = hpriv->force_port_map;
+ }
+
+- if (mask_port_map) {
++ if (hpriv->mask_port_map) {
+ dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
+ port_map,
+- port_map & mask_port_map);
+- port_map &= mask_port_map;
++ port_map & hpriv->mask_port_map);
++ port_map &= hpriv->mask_port_map;
+ }
+
+ /* cross check port_map and cap.n_ports */
+@@ -500,6 +501,9 @@
+ hpriv->cap = cap;
+ hpriv->cap2 = cap2;
+ hpriv->port_map = port_map;
++
++ if (!hpriv->start_engine)
++ hpriv->start_engine = ahci_start_engine;
+ }
+ EXPORT_SYMBOL_GPL(ahci_save_initial_config);
+
+@@ -603,7 +607,7 @@
+ }
+ EXPORT_SYMBOL_GPL(ahci_stop_engine);
+
+-static void ahci_start_fis_rx(struct ata_port *ap)
++void ahci_start_fis_rx(struct ata_port *ap)
+ {
+ void __iomem *port_mmio = ahci_port_base(ap);
+ struct ahci_host_priv *hpriv = ap->host->private_data;
+@@ -629,6 +633,7 @@
+ /* flush */
+ readl(port_mmio + PORT_CMD);
+ }
++EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
+
+ static int ahci_stop_fis_rx(struct ata_port *ap)
+ {
+@@ -766,7 +771,7 @@
+
+ /* enable DMA */
+ if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+
+ /* turn on LEDs */
+ if (ap->flags & ATA_FLAG_EM) {
+@@ -1234,7 +1239,7 @@
+
+ /* restart engine */
+ out_restart:
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+ return rc;
+ }
+ EXPORT_SYMBOL_GPL(ahci_kick_engine);
+@@ -1435,6 +1440,7 @@
+ const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
+ struct ata_port *ap = link->ap;
+ struct ahci_port_priv *pp = ap->private_data;
++ struct ahci_host_priv *hpriv = ap->host->private_data;
+ u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+ struct ata_taskfile tf;
+ bool online;
+@@ -1452,7 +1458,7 @@
+ rc = sata_link_hardreset(link, timing, deadline, &online,
+ ahci_check_ready);
+
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+
+ if (online)
+ *class = ahci_dev_classify(ap);
+@@ -1638,7 +1644,7 @@
+ }
+
+ if (irq_stat & PORT_IRQ_UNK_FIS) {
+- u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
++ u32 *unk = pp->rx_fis + RX_FIS_UNK;
+
+ active_ehi->err_mask |= AC_ERR_HSM;
+ active_ehi->action |= ATA_EH_RESET;
+@@ -1934,7 +1940,7 @@
+ }
+ EXPORT_SYMBOL_GPL(ahci_interrupt);
+
+-static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
++unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
+ {
+ struct ata_port *ap = qc->ap;
+ void __iomem *port_mmio = ahci_port_base(ap);
+@@ -1963,6 +1969,7 @@
+
+ return 0;
+ }
++EXPORT_SYMBOL_GPL(ahci_qc_issue);
+
+ static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
+ {
+@@ -2015,10 +2022,12 @@
+
+ void ahci_error_handler(struct ata_port *ap)
+ {
++ struct ahci_host_priv *hpriv = ap->host->private_data;
++
+ if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
+ /* restart engine */
+ ahci_stop_engine(ap);
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+ }
+
+ sata_pmp_error_handler(ap);
+@@ -2039,6 +2048,7 @@
+
+ static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
+ {
++ struct ahci_host_priv *hpriv = ap->host->private_data;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ struct ata_device *dev = ap->link.device;
+ u32 devslp, dm, dito, mdat, deto;
+@@ -2102,7 +2112,7 @@
+ PORT_DEVSLP_ADSE);
+ writel(devslp, port_mmio + PORT_DEVSLP);
+
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+
+ /* enable device sleep feature for the drive */
+ err_mask = ata_dev_set_feature(dev,
+@@ -2114,6 +2124,7 @@
+
+ static void ahci_enable_fbs(struct ata_port *ap)
+ {
++ struct ahci_host_priv *hpriv = ap->host->private_data;
+ struct ahci_port_priv *pp = ap->private_data;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ u32 fbs;
+@@ -2142,11 +2153,12 @@
+ } else
+ dev_err(ap->host->dev, "Failed to enable FBS\n");
+
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+ }
+
+ static void ahci_disable_fbs(struct ata_port *ap)
+ {
++ struct ahci_host_priv *hpriv = ap->host->private_data;
+ struct ahci_port_priv *pp = ap->private_data;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ u32 fbs;
+@@ -2174,7 +2186,7 @@
+ pp->fbs_enabled = false;
+ }
+
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+ }
+
+ static void ahci_pmp_attach(struct ata_port *ap)
+diff -Nur linux-3.14.72.orig/drivers/ata/libahci_platform.c linux-3.14.72/drivers/ata/libahci_platform.c
+--- linux-3.14.72.orig/drivers/ata/libahci_platform.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/ata/libahci_platform.c 2016-06-19 22:11:55.085154441 +0200
+@@ -0,0 +1,555 @@
++/*
++ * AHCI SATA platform library
++ *
++ * Copyright 2004-2005 Red Hat, Inc.
++ * Jeff Garzik <jgarzik@pobox.com>
++ * Copyright 2010 MontaVista Software, LLC.
++ * Anton Vorontsov <avorontsov@ru.mvista.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2, or (at your option)
++ * any later version.
++ */
++
++#include <linux/clk.h>
++#include <linux/kernel.h>
++#include <linux/gfp.h>
++#include <linux/module.h>
++#include <linux/pm.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/libata.h>
++#include <linux/ahci_platform.h>
++#include <linux/phy/phy.h>
++#include <linux/pm_runtime.h>
++#include "ahci.h"
++
++static void ahci_host_stop(struct ata_host *host);
++
++struct ata_port_operations ahci_platform_ops = {
++ .inherits = &ahci_ops,
++ .host_stop = ahci_host_stop,
++};
++EXPORT_SYMBOL_GPL(ahci_platform_ops);
++
++static struct scsi_host_template ahci_platform_sht = {
++ AHCI_SHT("ahci_platform"),
++};
++
++/**
++ * ahci_platform_enable_clks - Enable platform clocks
++ * @hpriv: host private area to store config values
++ *
++ * This function enables all the clks found in hpriv->clks, starting at
++ * index 0. If any clk fails to enable it disables all the clks already
++ * enabled in reverse order, and then returns an error.
++ *
++ * RETURNS:
++ * 0 on success otherwise a negative error code
++ */
++int ahci_platform_enable_clks(struct ahci_host_priv *hpriv)
++{
++ int c, rc;
++
++ for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++) {
++ rc = clk_prepare_enable(hpriv->clks[c]);
++ if (rc)
++ goto disable_unprepare_clk;
++ }
++ return 0;
++
++disable_unprepare_clk:
++ while (--c >= 0)
++ clk_disable_unprepare(hpriv->clks[c]);
++ return rc;
++}
++EXPORT_SYMBOL_GPL(ahci_platform_enable_clks);
++
++/**
++ * ahci_platform_disable_clks - Disable platform clocks
++ * @hpriv: host private area to store config values
++ *
++ * This function disables all the clks found in hpriv->clks, in reverse
++ * order of ahci_platform_enable_clks (starting at the end of the array).
++ */
++void ahci_platform_disable_clks(struct ahci_host_priv *hpriv)
++{
++ int c;
++
++ for (c = AHCI_MAX_CLKS - 1; c >= 0; c--)
++ if (hpriv->clks[c])
++ clk_disable_unprepare(hpriv->clks[c]);
++}
++EXPORT_SYMBOL_GPL(ahci_platform_disable_clks);
++
++/**
++ * ahci_platform_enable_resources - Enable platform resources
++ * @hpriv: host private area to store config values
++ *
++ * This function enables all ahci_platform managed resources in the
++ * following order:
++ * 1) Regulator
++ * 2) Clocks (through ahci_platform_enable_clks)
++ * 3) Phy
++ *
++ * If resource enabling fails at any point the previous enabled resources
++ * are disabled in reverse order.
++ *
++ * RETURNS:
++ * 0 on success otherwise a negative error code
++ */
++int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
++{
++ int rc;
++
++ if (hpriv->target_pwr) {
++ rc = regulator_enable(hpriv->target_pwr);
++ if (rc)
++ return rc;
++ }
++
++ rc = ahci_platform_enable_clks(hpriv);
++ if (rc)
++ goto disable_regulator;
++
++ if (hpriv->phy) {
++ rc = phy_init(hpriv->phy);
++ if (rc)
++ goto disable_clks;
++
++ rc = phy_power_on(hpriv->phy);
++ if (rc) {
++ phy_exit(hpriv->phy);
++ goto disable_clks;
++ }
++ }
++
++ return 0;
++
++disable_clks:
++ ahci_platform_disable_clks(hpriv);
++
++disable_regulator:
++ if (hpriv->target_pwr)
++ regulator_disable(hpriv->target_pwr);
++ return rc;
++}
++EXPORT_SYMBOL_GPL(ahci_platform_enable_resources);
++
++/**
++ * ahci_platform_disable_resources - Disable platform resources
++ * @hpriv: host private area to store config values
++ *
++ * This function disables all ahci_platform managed resources in the
++ * following order:
++ * 1) Phy
++ * 2) Clocks (through ahci_platform_disable_clks)
++ * 3) Regulator
++ */
++void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
++{
++ if (hpriv->phy) {
++ phy_power_off(hpriv->phy);
++ phy_exit(hpriv->phy);
++ }
++
++ ahci_platform_disable_clks(hpriv);
++
++ if (hpriv->target_pwr)
++ regulator_disable(hpriv->target_pwr);
++}
++EXPORT_SYMBOL_GPL(ahci_platform_disable_resources);
++
++static void ahci_platform_put_resources(struct device *dev, void *res)
++{
++ struct ahci_host_priv *hpriv = res;
++ int c;
++
++ if (hpriv->got_runtime_pm) {
++ pm_runtime_put_sync(dev);
++ pm_runtime_disable(dev);
++ }
++
++ for (c = 0; c < AHCI_MAX_CLKS && hpriv->clks[c]; c++)
++ clk_put(hpriv->clks[c]);
++}
++
++/**
++ * ahci_platform_get_resources - Get platform resources
++ * @pdev: platform device to get resources for
++ *
++ * This function allocates an ahci_host_priv struct, and gets the following
++ * resources, storing a reference to them inside the returned struct:
++ *
++ * 1) mmio registers (IORESOURCE_MEM 0, mandatory)
++ * 2) regulator for controlling the targets power (optional)
++ * 3) 0 - AHCI_MAX_CLKS clocks, as specified in the devs devicetree node,
++ * or for non devicetree enabled platforms a single clock
++ * 4) phy (optional)
++ *
++ * RETURNS:
++ * The allocated ahci_host_priv on success, otherwise an ERR_PTR value
++ */
++struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct ahci_host_priv *hpriv;
++ struct clk *clk;
++ int i, rc = -ENOMEM;
++
++ if (!devres_open_group(dev, NULL, GFP_KERNEL))
++ return ERR_PTR(-ENOMEM);
++
++ hpriv = devres_alloc(ahci_platform_put_resources, sizeof(*hpriv),
++ GFP_KERNEL);
++ if (!hpriv)
++ goto err_out;
++
++ devres_add(dev, hpriv);
++
++ hpriv->mmio = devm_ioremap_resource(dev,
++ platform_get_resource(pdev, IORESOURCE_MEM, 0));
++ if (IS_ERR(hpriv->mmio)) {
++ dev_err(dev, "no mmio space\n");
++ rc = PTR_ERR(hpriv->mmio);
++ goto err_out;
++ }
++
++ hpriv->target_pwr = devm_regulator_get_optional(dev, "target");
++ if (IS_ERR(hpriv->target_pwr)) {
++ rc = PTR_ERR(hpriv->target_pwr);
++ if (rc == -EPROBE_DEFER)
++ goto err_out;
++ hpriv->target_pwr = NULL;
++ }
++
++ for (i = 0; i < AHCI_MAX_CLKS; i++) {
++ /*
++ * For now we must use clk_get(dev, NULL) for the first clock,
++ * because some platforms (da850, spear13xx) are not yet
++ * converted to use devicetree for clocks. For new platforms
++ * this is equivalent to of_clk_get(dev->of_node, 0).
++ */
++ if (i == 0)
++ clk = clk_get(dev, NULL);
++ else
++ clk = of_clk_get(dev->of_node, i);
++
++ if (IS_ERR(clk)) {
++ rc = PTR_ERR(clk);
++ if (rc == -EPROBE_DEFER)
++ goto err_out;
++ break;
++ }
++ hpriv->clks[i] = clk;
++ }
++
++ hpriv->phy = devm_phy_get(dev, "sata-phy");
++ if (IS_ERR(hpriv->phy)) {
++ rc = PTR_ERR(hpriv->phy);
++ switch (rc) {
++ case -ENOSYS:
++ /* No PHY support. Check if PHY is required. */
++ if (of_find_property(dev->of_node, "phys", NULL)) {
++ dev_err(dev, "couldn't get sata-phy: ENOSYS\n");
++ goto err_out;
++ }
++ case -ENODEV:
++ /* continue normally */
++ hpriv->phy = NULL;
++ break;
++
++ case -EPROBE_DEFER:
++ goto err_out;
++
++ default:
++ dev_err(dev, "couldn't get sata-phy\n");
++ goto err_out;
++ }
++ }
++
++ pm_runtime_enable(dev);
++ pm_runtime_get_sync(dev);
++ hpriv->got_runtime_pm = true;
++
++ devres_remove_group(dev, NULL);
++ return hpriv;
++
++err_out:
++ devres_release_group(dev, NULL);
++ return ERR_PTR(rc);
++}
++EXPORT_SYMBOL_GPL(ahci_platform_get_resources);
++
++/**
++ * ahci_platform_init_host - Bring up an ahci-platform host
++ * @pdev: platform device pointer for the host
++ * @hpriv: ahci-host private data for the host
++ * @pi_template: template for the ata_port_info to use
++ *
++ * This function does all the usual steps needed to bring up an
++ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
++ * must be initialized / enabled before calling this.
++ *
++ * RETURNS:
++ * 0 on success otherwise a negative error code
++ */
++int ahci_platform_init_host(struct platform_device *pdev,
++ struct ahci_host_priv *hpriv,
++ const struct ata_port_info *pi_template)
++{
++ struct device *dev = &pdev->dev;
++ struct ata_port_info pi = *pi_template;
++ const struct ata_port_info *ppi[] = { &pi, NULL };
++ struct ata_host *host;
++ int i, irq, n_ports, rc;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq <= 0) {
++ dev_err(dev, "no irq\n");
++ return -EINVAL;
++ }
++
++ /* prepare host */
++ pi.private_data = (void *)hpriv->flags;
++
++ ahci_save_initial_config(dev, hpriv);
++
++ if (hpriv->cap & HOST_CAP_NCQ)
++ pi.flags |= ATA_FLAG_NCQ;
++
++ if (hpriv->cap & HOST_CAP_PMP)
++ pi.flags |= ATA_FLAG_PMP;
++
++ ahci_set_em_messages(hpriv, &pi);
++
++ /* CAP.NP sometimes indicate the index of the last enabled
++ * port, at other times, that of the last possible port, so
++ * determining the maximum port number requires looking at
++ * both CAP.NP and port_map.
++ */
++ n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
++
++ host = ata_host_alloc_pinfo(dev, ppi, n_ports);
++ if (!host)
++ return -ENOMEM;
++
++ host->private_data = hpriv;
++
++ if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
++ host->flags |= ATA_HOST_PARALLEL_SCAN;
++ else
++ dev_info(dev, "SSS flag set, parallel bus scan disabled\n");
++
++ if (pi.flags & ATA_FLAG_EM)
++ ahci_reset_em(host);
++
++ for (i = 0; i < host->n_ports; i++) {
++ struct ata_port *ap = host->ports[i];
++
++ ata_port_desc(ap, "mmio %pR",
++ platform_get_resource(pdev, IORESOURCE_MEM, 0));
++ ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
++
++ /* set enclosure management message type */
++ if (ap->flags & ATA_FLAG_EM)
++ ap->em_message_type = hpriv->em_msg_type;
++
++ /* disabled/not-implemented port */
++ if (!(hpriv->port_map & (1 << i)))
++ ap->ops = &ata_dummy_port_ops;
++ }
++
++ if (hpriv->cap & HOST_CAP_64) {
++ rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
++ if (rc) {
++ rc = dma_coerce_mask_and_coherent(dev,
++ DMA_BIT_MASK(32));
++ if (rc) {
++ dev_err(dev, "Failed to enable 64-bit DMA.\n");
++ return rc;
++ }
++ dev_warn(dev, "Enable 32-bit DMA instead of 64-bit.\n");
++ }
++ }
++
++ rc = ahci_reset_controller(host);
++ if (rc)
++ return rc;
++
++ ahci_init_controller(host);
++ ahci_print_info(host, "platform");
++
++ return ata_host_activate(host, irq, ahci_interrupt, IRQF_SHARED,
++ &ahci_platform_sht);
++}
++EXPORT_SYMBOL_GPL(ahci_platform_init_host);
++
++static void ahci_host_stop(struct ata_host *host)
++{
++ struct device *dev = host->dev;
++ struct ahci_platform_data *pdata = dev_get_platdata(dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++
++ if (pdata && pdata->exit)
++ pdata->exit(dev);
++
++ ahci_platform_disable_resources(hpriv);
++}
++
++#ifdef CONFIG_PM_SLEEP
++/**
++ * ahci_platform_suspend_host - Suspend an ahci-platform host
++ * @dev: device pointer for the host
++ *
++ * This function does all the usual steps needed to suspend an
++ * ahci-platform host, note any necessary resources (ie clks, phy, etc.)
++ * must be disabled after calling this.
++ *
++ * RETURNS:
++ * 0 on success otherwise a negative error code
++ */
++int ahci_platform_suspend_host(struct device *dev)
++{
++ struct ata_host *host = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ void __iomem *mmio = hpriv->mmio;
++ u32 ctl;
++
++ if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
++ dev_err(dev, "firmware update required for suspend/resume\n");
++ return -EIO;
++ }
++
++ /*
++ * AHCI spec rev1.1 section 8.3.3:
++ * Software must disable interrupts prior to requesting a
++ * transition of the HBA to D3 state.
++ */
++ ctl = readl(mmio + HOST_CTL);
++ ctl &= ~HOST_IRQ_EN;
++ writel(ctl, mmio + HOST_CTL);
++ readl(mmio + HOST_CTL); /* flush */
++
++ return ata_host_suspend(host, PMSG_SUSPEND);
++}
++EXPORT_SYMBOL_GPL(ahci_platform_suspend_host);
++
++/**
++ * ahci_platform_resume_host - Resume an ahci-platform host
++ * @dev: device pointer for the host
++ *
++ * This function does all the usual steps needed to resume an ahci-platform
++ * host, note any necessary resources (ie clks, phy, etc.) must be
++ * initialized / enabled before calling this.
++ *
++ * RETURNS:
++ * 0 on success otherwise a negative error code
++ */
++int ahci_platform_resume_host(struct device *dev)
++{
++ struct ata_host *host = dev_get_drvdata(dev);
++ int rc;
++
++ if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
++ rc = ahci_reset_controller(host);
++ if (rc)
++ return rc;
++
++ ahci_init_controller(host);
++ }
++
++ ata_host_resume(host);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(ahci_platform_resume_host);
++
++/**
++ * ahci_platform_suspend - Suspend an ahci-platform device
++ * @dev: the platform device to suspend
++ *
++ * This function suspends the host associated with the device, followed by
++ * disabling all the resources of the device.
++ *
++ * RETURNS:
++ * 0 on success otherwise a negative error code
++ */
++int ahci_platform_suspend(struct device *dev)
++{
++ struct ahci_platform_data *pdata = dev_get_platdata(dev);
++ struct ata_host *host = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ int rc;
++
++ rc = ahci_platform_suspend_host(dev);
++ if (rc)
++ return rc;
++
++ if (pdata && pdata->suspend) {
++ rc = pdata->suspend(dev);
++ if (rc)
++ goto resume_host;
++ }
++
++ ahci_platform_disable_resources(hpriv);
++
++ return 0;
++
++resume_host:
++ ahci_platform_resume_host(dev);
++ return rc;
++}
++EXPORT_SYMBOL_GPL(ahci_platform_suspend);
++
++/**
++ * ahci_platform_resume - Resume an ahci-platform device
++ * @dev: the platform device to resume
++ *
++ * This function enables all the resources of the device followed by
++ * resuming the host associated with the device.
++ *
++ * RETURNS:
++ * 0 on success otherwise a negative error code
++ */
++int ahci_platform_resume(struct device *dev)
++{
++ struct ahci_platform_data *pdata = dev_get_platdata(dev);
++ struct ata_host *host = dev_get_drvdata(dev);
++ struct ahci_host_priv *hpriv = host->private_data;
++ int rc;
++
++ rc = ahci_platform_enable_resources(hpriv);
++ if (rc)
++ return rc;
++
++ if (pdata && pdata->resume) {
++ rc = pdata->resume(dev);
++ if (rc)
++ goto disable_resources;
++ }
++
++ rc = ahci_platform_resume_host(dev);
++ if (rc)
++ goto disable_resources;
++
++ /* We resumed so update PM runtime state */
++ pm_runtime_disable(dev);
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++
++ return 0;
++
++disable_resources:
++ ahci_platform_disable_resources(hpriv);
++
++ return rc;
++}
++EXPORT_SYMBOL_GPL(ahci_platform_resume);
++#endif
++
++MODULE_DESCRIPTION("AHCI SATA platform library");
++MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/ata/libata-acpi.c linux-3.14.72/drivers/ata/libata-acpi.c
+--- linux-3.14.72.orig/drivers/ata/libata-acpi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/libata-acpi.c 2016-06-19 22:11:55.085154441 +0200
+@@ -835,6 +835,7 @@
+ ata_for_each_dev(dev, &ap->link, ALL) {
+ ata_acpi_clear_gtf(dev);
+ if (ata_dev_enabled(dev) &&
++ ata_dev_acpi_handle(dev) &&
+ ata_dev_get_GTF(dev, NULL) >= 0)
+ dev->flags |= ATA_DFLAG_ACPI_PENDING;
+ }
+diff -Nur linux-3.14.72.orig/drivers/ata/libata-core.c linux-3.14.72/drivers/ata/libata-core.c
+--- linux-3.14.72.orig/drivers/ata/libata-core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/libata-core.c 2016-06-19 22:11:55.089154177 +0200
+@@ -5369,22 +5369,17 @@
+ }
+
+ #ifdef CONFIG_PM
+-static int ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
+- unsigned int action, unsigned int ehi_flags,
+- int *async)
++static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
++ unsigned int action, unsigned int ehi_flags,
++ bool async)
+ {
+ struct ata_link *link;
+ unsigned long flags;
+- int rc = 0;
+
+ /* Previous resume operation might still be in
+ * progress. Wait for PM_PENDING to clear.
+ */
+ if (ap->pflags & ATA_PFLAG_PM_PENDING) {
+- if (async) {
+- *async = -EAGAIN;
+- return 0;
+- }
+ ata_port_wait_eh(ap);
+ WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
+ }
+@@ -5393,11 +5388,6 @@
+ spin_lock_irqsave(ap->lock, flags);
+
+ ap->pm_mesg = mesg;
+- if (async)
+- ap->pm_result = async;
+- else
+- ap->pm_result = &rc;
+-
+ ap->pflags |= ATA_PFLAG_PM_PENDING;
+ ata_for_each_link(link, ap, HOST_FIRST) {
+ link->eh_info.action |= action;
+@@ -5408,87 +5398,81 @@
+
+ spin_unlock_irqrestore(ap->lock, flags);
+
+- /* wait and check result */
+ if (!async) {
+ ata_port_wait_eh(ap);
+ WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
+ }
+-
+- return rc;
+ }
+
+-static int __ata_port_suspend_common(struct ata_port *ap, pm_message_t mesg, int *async)
++/*
++ * On some hardware, device fails to respond after spun down for suspend. As
++ * the device won't be used before being resumed, we don't need to touch the
++ * device. Ask EH to skip the usual stuff and proceed directly to suspend.
++ *
++ * http://thread.gmane.org/gmane.linux.ide/46764
++ */
++static const unsigned int ata_port_suspend_ehi = ATA_EHI_QUIET
++ | ATA_EHI_NO_AUTOPSY
++ | ATA_EHI_NO_RECOVERY;
++
++static void ata_port_suspend(struct ata_port *ap, pm_message_t mesg)
+ {
+- /*
+- * On some hardware, device fails to respond after spun down
+- * for suspend. As the device won't be used before being
+- * resumed, we don't need to touch the device. Ask EH to skip
+- * the usual stuff and proceed directly to suspend.
+- *
+- * http://thread.gmane.org/gmane.linux.ide/46764
+- */
+- unsigned int ehi_flags = ATA_EHI_QUIET | ATA_EHI_NO_AUTOPSY |
+- ATA_EHI_NO_RECOVERY;
+- return ata_port_request_pm(ap, mesg, 0, ehi_flags, async);
++ ata_port_request_pm(ap, mesg, 0, ata_port_suspend_ehi, false);
+ }
+
+-static int ata_port_suspend_common(struct device *dev, pm_message_t mesg)
++static void ata_port_suspend_async(struct ata_port *ap, pm_message_t mesg)
+ {
+- struct ata_port *ap = to_ata_port(dev);
+-
+- return __ata_port_suspend_common(ap, mesg, NULL);
++ ata_port_request_pm(ap, mesg, 0, ata_port_suspend_ehi, true);
+ }
+
+-static int ata_port_suspend(struct device *dev)
++static int ata_port_pm_suspend(struct device *dev)
+ {
++ struct ata_port *ap = to_ata_port(dev);
++
+ if (pm_runtime_suspended(dev))
+ return 0;
+
+- return ata_port_suspend_common(dev, PMSG_SUSPEND);
++ ata_port_suspend(ap, PMSG_SUSPEND);
++ return 0;
+ }
+
+-static int ata_port_do_freeze(struct device *dev)
++static int ata_port_pm_freeze(struct device *dev)
+ {
++ struct ata_port *ap = to_ata_port(dev);
++
+ if (pm_runtime_suspended(dev))
+ return 0;
+
+- return ata_port_suspend_common(dev, PMSG_FREEZE);
++ ata_port_suspend(ap, PMSG_FREEZE);
++ return 0;
+ }
+
+-static int ata_port_poweroff(struct device *dev)
++static int ata_port_pm_poweroff(struct device *dev)
+ {
+- return ata_port_suspend_common(dev, PMSG_HIBERNATE);
++ ata_port_suspend(to_ata_port(dev), PMSG_HIBERNATE);
++ return 0;
+ }
+
+-static int __ata_port_resume_common(struct ata_port *ap, pm_message_t mesg,
+- int *async)
+-{
+- int rc;
++static const unsigned int ata_port_resume_ehi = ATA_EHI_NO_AUTOPSY
++ | ATA_EHI_QUIET;
+
+- rc = ata_port_request_pm(ap, mesg, ATA_EH_RESET,
+- ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET, async);
+- return rc;
++static void ata_port_resume(struct ata_port *ap, pm_message_t mesg)
++{
++ ata_port_request_pm(ap, mesg, ATA_EH_RESET, ata_port_resume_ehi, false);
+ }
+
+-static int ata_port_resume_common(struct device *dev, pm_message_t mesg)
++static void ata_port_resume_async(struct ata_port *ap, pm_message_t mesg)
+ {
+- struct ata_port *ap = to_ata_port(dev);
+-
+- return __ata_port_resume_common(ap, mesg, NULL);
++ ata_port_request_pm(ap, mesg, ATA_EH_RESET, ata_port_resume_ehi, true);
+ }
+
+-static int ata_port_resume(struct device *dev)
++static int ata_port_pm_resume(struct device *dev)
+ {
+- int rc;
+-
+- rc = ata_port_resume_common(dev, PMSG_RESUME);
+- if (!rc) {
+- pm_runtime_disable(dev);
+- pm_runtime_set_active(dev);
+- pm_runtime_enable(dev);
+- }
+-
+- return rc;
++ ata_port_resume_async(to_ata_port(dev), PMSG_RESUME);
++ pm_runtime_disable(dev);
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ return 0;
+ }
+
+ /*
+@@ -5517,21 +5501,23 @@
+
+ static int ata_port_runtime_suspend(struct device *dev)
+ {
+- return ata_port_suspend_common(dev, PMSG_AUTO_SUSPEND);
++ ata_port_suspend(to_ata_port(dev), PMSG_AUTO_SUSPEND);
++ return 0;
+ }
+
+ static int ata_port_runtime_resume(struct device *dev)
+ {
+- return ata_port_resume_common(dev, PMSG_AUTO_RESUME);
++ ata_port_resume(to_ata_port(dev), PMSG_AUTO_RESUME);
++ return 0;
+ }
+
+ static const struct dev_pm_ops ata_port_pm_ops = {
+- .suspend = ata_port_suspend,
+- .resume = ata_port_resume,
+- .freeze = ata_port_do_freeze,
+- .thaw = ata_port_resume,
+- .poweroff = ata_port_poweroff,
+- .restore = ata_port_resume,
++ .suspend = ata_port_pm_suspend,
++ .resume = ata_port_pm_resume,
++ .freeze = ata_port_pm_freeze,
++ .thaw = ata_port_pm_resume,
++ .poweroff = ata_port_pm_poweroff,
++ .restore = ata_port_pm_resume,
+
+ .runtime_suspend = ata_port_runtime_suspend,
+ .runtime_resume = ata_port_runtime_resume,
+@@ -5543,18 +5529,17 @@
+ * level. sas suspend/resume is async to allow parallel port recovery
+ * since sas has multiple ata_port instances per Scsi_Host.
+ */
+-int ata_sas_port_async_suspend(struct ata_port *ap, int *async)
++void ata_sas_port_suspend(struct ata_port *ap)
+ {
+- return __ata_port_suspend_common(ap, PMSG_SUSPEND, async);
++ ata_port_suspend_async(ap, PMSG_SUSPEND);
+ }
+-EXPORT_SYMBOL_GPL(ata_sas_port_async_suspend);
++EXPORT_SYMBOL_GPL(ata_sas_port_suspend);
+
+-int ata_sas_port_async_resume(struct ata_port *ap, int *async)
++void ata_sas_port_resume(struct ata_port *ap)
+ {
+- return __ata_port_resume_common(ap, PMSG_RESUME, async);
++ ata_port_resume_async(ap, PMSG_RESUME);
+ }
+-EXPORT_SYMBOL_GPL(ata_sas_port_async_resume);
+-
++EXPORT_SYMBOL_GPL(ata_sas_port_resume);
+
+ /**
+ * ata_host_suspend - suspend host
+diff -Nur linux-3.14.72.orig/drivers/ata/libata-eh.c linux-3.14.72/drivers/ata/libata-eh.c
+--- linux-3.14.72.orig/drivers/ata/libata-eh.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/libata-eh.c 2016-06-19 22:11:55.089154177 +0200
+@@ -95,12 +95,13 @@
+ * represents timeout for that try. The first try can be soft or
+ * hardreset. All others are hardreset if available. In most cases
+ * the first reset w/ 10sec timeout should succeed. Following entries
+- * are mostly for error handling, hotplug and retarded devices.
++ * are mostly for error handling, hotplug and those outlier devices that
++ * take an exceptionally long time to recover from reset.
+ */
+ static const unsigned long ata_eh_reset_timeouts[] = {
+ 10000, /* most drives spin up by 10sec */
+ 10000, /* > 99% working drives spin up before 20sec */
+- 35000, /* give > 30 secs of idleness for retarded devices */
++ 35000, /* give > 30 secs of idleness for outlier devices */
+ 5000, /* and sweet one last chance */
+ ULONG_MAX, /* > 1 min has elapsed, give up */
+ };
+@@ -1810,7 +1811,7 @@
+ case ATA_DEV_ATA:
+ if (err & ATA_ICRC)
+ qc->err_mask |= AC_ERR_ATA_BUS;
+- if (err & ATA_UNC)
++ if (err & (ATA_UNC | ATA_AMNF))
+ qc->err_mask |= AC_ERR_MEDIA;
+ if (err & ATA_IDNF)
+ qc->err_mask |= AC_ERR_INVALID;
+@@ -2555,11 +2556,12 @@
+ }
+
+ if (cmd->command != ATA_CMD_PACKET &&
+- (res->feature & (ATA_ICRC | ATA_UNC | ATA_IDNF |
+- ATA_ABORTED)))
+- ata_dev_err(qc->dev, "error: { %s%s%s%s}\n",
++ (res->feature & (ATA_ICRC | ATA_UNC | ATA_AMNF |
++ ATA_IDNF | ATA_ABORTED)))
++ ata_dev_err(qc->dev, "error: { %s%s%s%s%s}\n",
+ res->feature & ATA_ICRC ? "ICRC " : "",
+ res->feature & ATA_UNC ? "UNC " : "",
++ res->feature & ATA_AMNF ? "AMNF " : "",
+ res->feature & ATA_IDNF ? "IDNF " : "",
+ res->feature & ATA_ABORTED ? "ABRT " : "");
+ #endif
+@@ -4072,7 +4074,7 @@
+
+ ata_acpi_set_state(ap, ap->pm_mesg);
+ out:
+- /* report result */
++ /* update the flags */
+ spin_lock_irqsave(ap->lock, flags);
+
+ ap->pflags &= ~ATA_PFLAG_PM_PENDING;
+@@ -4081,11 +4083,6 @@
+ else if (ap->pflags & ATA_PFLAG_FROZEN)
+ ata_port_schedule_eh(ap);
+
+- if (ap->pm_result) {
+- *ap->pm_result = rc;
+- ap->pm_result = NULL;
+- }
+-
+ spin_unlock_irqrestore(ap->lock, flags);
+
+ return;
+@@ -4137,13 +4134,9 @@
+ /* tell ACPI that we're resuming */
+ ata_acpi_on_resume(ap);
+
+- /* report result */
++ /* update the flags */
+ spin_lock_irqsave(ap->lock, flags);
+ ap->pflags &= ~(ATA_PFLAG_PM_PENDING | ATA_PFLAG_SUSPENDED);
+- if (ap->pm_result) {
+- *ap->pm_result = rc;
+- ap->pm_result = NULL;
+- }
+ spin_unlock_irqrestore(ap->lock, flags);
+ }
+ #endif /* CONFIG_PM */
+diff -Nur linux-3.14.72.orig/drivers/ata/libata-scsi.c linux-3.14.72/drivers/ata/libata-scsi.c
+--- linux-3.14.72.orig/drivers/ata/libata-scsi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/libata-scsi.c 2016-06-19 22:11:55.089154177 +0200
+@@ -1992,7 +1992,11 @@
+ memcpy(rbuf, hdr, sizeof(hdr));
+ memcpy(&rbuf[8], "ATA ", 8);
+ ata_id_string(args->id, &rbuf[16], ATA_ID_PROD, 16);
+- ata_id_string(args->id, &rbuf[32], ATA_ID_FW_REV, 4);
++
++ /* From SAT, use last 2 words from fw rev unless they are spaces */
++ ata_id_string(args->id, &rbuf[32], ATA_ID_FW_REV + 2, 4);
++ if (strncmp(&rbuf[32], " ", 4) == 0)
++ ata_id_string(args->id, &rbuf[32], ATA_ID_FW_REV, 4);
+
+ if (rbuf[32] == 0 || rbuf[32] == ' ')
+ memcpy(&rbuf[32], "n/a ", 4);
+diff -Nur linux-3.14.72.orig/drivers/ata/libata-sff.c linux-3.14.72/drivers/ata/libata-sff.c
+--- linux-3.14.72.orig/drivers/ata/libata-sff.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/libata-sff.c 2016-06-19 22:11:55.089154177 +0200
+@@ -2433,15 +2433,6 @@
+ mask = (1 << 2) | (1 << 0);
+ if ((tmp8 & mask) != mask)
+ legacy_mode = 1;
+-#if defined(CONFIG_NO_ATA_LEGACY)
+- /* Some platforms with PCI limits cannot address compat
+- port space. In that case we punt if their firmware has
+- left a device in compatibility mode */
+- if (legacy_mode) {
+- printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
+- return -EOPNOTSUPP;
+- }
+-#endif
+ }
+
+ if (!devres_open_group(dev, NULL, GFP_KERNEL))
+diff -Nur linux-3.14.72.orig/drivers/ata/libata-zpodd.c linux-3.14.72/drivers/ata/libata-zpodd.c
+--- linux-3.14.72.orig/drivers/ata/libata-zpodd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/libata-zpodd.c 2016-06-19 22:11:55.089154177 +0200
+@@ -85,21 +85,6 @@
+ return ODD_MECH_TYPE_UNSUPPORTED;
+ }
+
+-static bool odd_can_poweroff(struct ata_device *ata_dev)
+-{
+- acpi_handle handle;
+- struct acpi_device *acpi_dev;
+-
+- handle = ata_dev_acpi_handle(ata_dev);
+- if (!handle)
+- return false;
+-
+- if (acpi_bus_get_device(handle, &acpi_dev))
+- return false;
+-
+- return acpi_device_can_poweroff(acpi_dev);
+-}
+-
+ /* Test if ODD is zero power ready by sense code */
+ static bool zpready(struct ata_device *dev)
+ {
+@@ -267,13 +252,11 @@
+
+ void zpodd_init(struct ata_device *dev)
+ {
++ struct acpi_device *adev = ACPI_COMPANION(&dev->tdev);
+ enum odd_mech_type mech_type;
+ struct zpodd *zpodd;
+
+- if (dev->zpodd)
+- return;
+-
+- if (!odd_can_poweroff(dev))
++ if (dev->zpodd || !adev || !acpi_device_can_poweroff(adev))
+ return;
+
+ mech_type = zpodd_get_mech_type(dev);
+diff -Nur linux-3.14.72.orig/drivers/ata/Makefile linux-3.14.72/drivers/ata/Makefile
+--- linux-3.14.72.orig/drivers/ata/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/Makefile 2016-06-19 22:11:55.089154177 +0200
+@@ -4,13 +4,19 @@
+ # non-SFF interface
+ obj-$(CONFIG_SATA_AHCI) += ahci.o libahci.o
+ obj-$(CONFIG_SATA_ACARD_AHCI) += acard-ahci.o libahci.o
+-obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o
++obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o libahci_platform.o
+ obj-$(CONFIG_SATA_FSL) += sata_fsl.o
+ obj-$(CONFIG_SATA_INIC162X) += sata_inic162x.o
+ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
+ obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
+ obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
+-obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
++obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
++obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
++obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
++obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
++obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o libahci_platform.o
++obj-$(CONFIG_AHCI_TEGRA) += ahci_tegra.o libahci.o libahci_platform.o
++obj-$(CONFIG_AHCI_XGENE) += ahci_xgene.o libahci.o libahci_platform.o
+
+ # SFF w/ custom DMA
+ obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_acpi.c linux-3.14.72/drivers/ata/pata_acpi.c
+--- linux-3.14.72.orig/drivers/ata/pata_acpi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_acpi.c 2016-06-19 22:11:55.089154177 +0200
+@@ -7,7 +7,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -266,7 +265,7 @@
+ .id_table = pacpi_pci_tbl,
+ .probe = pacpi_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_ali.c linux-3.14.72/drivers/ata/pata_ali.c
+--- linux-3.14.72.orig/drivers/ata/pata_ali.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_ali.c 2016-06-19 22:11:55.089154177 +0200
+@@ -589,7 +589,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &ali_sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int ali_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -616,7 +616,7 @@
+ .id_table = ali,
+ .probe = ali_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ali_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_amd.c linux-3.14.72/drivers/ata/pata_amd.c
+--- linux-3.14.72.orig/drivers/ata/pata_amd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_amd.c 2016-06-19 22:11:55.089154177 +0200
+@@ -17,7 +17,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -575,7 +574,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int amd_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -626,7 +625,7 @@
+ .id_table = amd,
+ .probe = amd_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = amd_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_arasan_cf.c linux-3.14.72/drivers/ata/pata_arasan_cf.c
+--- linux-3.14.72.orig/drivers/ata/pata_arasan_cf.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_arasan_cf.c 2016-06-19 22:11:55.089154177 +0200
+@@ -356,7 +356,7 @@
+
+ static void dma_callback(void *dev)
+ {
+- struct arasan_cf_dev *acdev = (struct arasan_cf_dev *) dev;
++ struct arasan_cf_dev *acdev = dev;
+
+ complete(&acdev->dma_completion);
+ }
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_artop.c linux-3.14.72/drivers/ata/pata_artop.c
+--- linux-3.14.72.orig/drivers/ata/pata_artop.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_artop.c 2016-06-19 22:11:55.089154177 +0200
+@@ -19,7 +19,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -423,7 +422,7 @@
+ { } /* terminate list */
+ };
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int atp8xx_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -445,7 +444,7 @@
+ .id_table = artop_pci_tbl,
+ .probe = artop_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = atp8xx_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_at91.c linux-3.14.72/drivers/ata/pata_at91.c
+--- linux-3.14.72.orig/drivers/ata/pata_at91.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_at91.c 2016-06-19 22:11:55.089154177 +0200
+@@ -18,7 +18,6 @@
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/gfp.h>
+ #include <scsi/scsi_host.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_atiixp.c linux-3.14.72/drivers/ata/pata_atiixp.c
+--- linux-3.14.72.orig/drivers/ata/pata_atiixp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_atiixp.c 2016-06-19 22:11:55.093153915 +0200
+@@ -15,7 +15,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -299,7 +298,7 @@
+ .id_table = atiixp,
+ .probe = atiixp_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .resume = ata_pci_device_resume,
+ .suspend = ata_pci_device_suspend,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_atp867x.c linux-3.14.72/drivers/ata/pata_atp867x.c
+--- linux-3.14.72.orig/drivers/ata/pata_atp867x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_atp867x.c 2016-06-19 22:11:55.093153915 +0200
+@@ -29,7 +29,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -531,7 +530,7 @@
+ return rc;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int atp867x_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -559,7 +558,7 @@
+ .id_table = atp867x_pci_tbl,
+ .probe = atp867x_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = atp867x_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_bf54x.c linux-3.14.72/drivers/ata/pata_bf54x.c
+--- linux-3.14.72.orig/drivers/ata/pata_bf54x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_bf54x.c 2016-06-19 22:11:55.093153915 +0200
+@@ -1619,7 +1619,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int bfin_atapi_suspend(struct platform_device *pdev, pm_message_t state)
+ {
+ struct ata_host *host = platform_get_drvdata(pdev);
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_cmd640.c linux-3.14.72/drivers/ata/pata_cmd640.c
+--- linux-3.14.72.orig/drivers/ata/pata_cmd640.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_cmd640.c 2016-06-19 22:11:55.093153915 +0200
+@@ -15,7 +15,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/gfp.h>
+@@ -232,7 +231,7 @@
+ return ata_pci_sff_init_one(pdev, ppi, &cmd640_sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int cmd640_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -257,7 +256,7 @@
+ .id_table = cmd640,
+ .probe = cmd640_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = cmd640_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_cmd64x.c linux-3.14.72/drivers/ata/pata_cmd64x.c
+--- linux-3.14.72.orig/drivers/ata/pata_cmd64x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_cmd64x.c 2016-06-19 22:11:55.093153915 +0200
+@@ -26,7 +26,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -488,7 +487,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int cmd64x_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -519,7 +518,7 @@
+ .id_table = cmd64x,
+ .probe = cmd64x_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = cmd64x_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_cs5520.c linux-3.14.72/drivers/ata/pata_cs5520.c
+--- linux-3.14.72.orig/drivers/ata/pata_cs5520.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_cs5520.c 2016-06-19 22:11:55.093153915 +0200
+@@ -34,7 +34,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -230,7 +229,7 @@
+ return ata_host_register(host, &cs5520_sht);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ /**
+ * cs5520_reinit_one - device resume
+ * @pdev: PCI device
+@@ -279,7 +278,7 @@
+ pci_save_state(pdev);
+ return 0;
+ }
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
+
+ /* For now keep DMA off. We can set it for all but A rev CS5510 once the
+ core ATA code can handle it */
+@@ -296,7 +295,7 @@
+ .id_table = pata_cs5520,
+ .probe = cs5520_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = cs5520_pci_device_suspend,
+ .resume = cs5520_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_cs5530.c linux-3.14.72/drivers/ata/pata_cs5530.c
+--- linux-3.14.72.orig/drivers/ata/pata_cs5530.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_cs5530.c 2016-06-19 22:11:55.093153915 +0200
+@@ -26,7 +26,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -327,7 +326,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &cs5530_sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int cs5530_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -344,7 +343,7 @@
+ ata_host_resume(host);
+ return 0;
+ }
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
+
+ static const struct pci_device_id cs5530[] = {
+ { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), },
+@@ -357,7 +356,7 @@
+ .id_table = cs5530,
+ .probe = cs5530_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = cs5530_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_cs5535.c linux-3.14.72/drivers/ata/pata_cs5535.c
+--- linux-3.14.72.orig/drivers/ata/pata_cs5535.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_cs5535.c 2016-06-19 22:11:55.093153915 +0200
+@@ -31,7 +31,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -201,7 +200,7 @@
+ .id_table = cs5535,
+ .probe = cs5535_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_cs5536.c linux-3.14.72/drivers/ata/pata_cs5536.c
+--- linux-3.14.72.orig/drivers/ata/pata_cs5536.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_cs5536.c 2016-06-19 22:11:55.093153915 +0200
+@@ -33,7 +33,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/libata.h>
+@@ -298,7 +297,7 @@
+ .id_table = cs5536,
+ .probe = cs5536_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_cypress.c linux-3.14.72/drivers/ata/pata_cypress.c
+--- linux-3.14.72.orig/drivers/ata/pata_cypress.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_cypress.c 2016-06-19 22:11:55.093153915 +0200
+@@ -11,7 +11,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -152,7 +151,7 @@
+ .id_table = cy82c693,
+ .probe = cy82c693_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_efar.c linux-3.14.72/drivers/ata/pata_efar.c
+--- linux-3.14.72.orig/drivers/ata/pata_efar.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_efar.c 2016-06-19 22:11:55.093153915 +0200
+@@ -14,7 +14,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -289,7 +288,7 @@
+ .id_table = efar_pci_tbl,
+ .probe = efar_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_ep93xx.c linux-3.14.72/drivers/ata/pata_ep93xx.c
+--- linux-3.14.72.orig/drivers/ata/pata_ep93xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_ep93xx.c 2016-06-19 22:11:55.093153915 +0200
+@@ -34,7 +34,6 @@
+ #include <linux/err.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <scsi/scsi_host.h>
+ #include <linux/ata.h>
+@@ -709,8 +708,8 @@
+ struct dma_chan *channel = qc->dma_dir == DMA_TO_DEVICE
+ ? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
+
+- txd = channel->device->device_prep_slave_sg(channel, qc->sg,
+- qc->n_elem, qc->dma_dir, DMA_CTRL_ACK, NULL);
++ txd = dmaengine_prep_slave_sg(channel, qc->sg, qc->n_elem, qc->dma_dir,
++ DMA_CTRL_ACK);
+ if (!txd) {
+ dev_err(qc->ap->dev, "failed to prepare slave for sg dma\n");
+ return;
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_hpt366.c linux-3.14.72/drivers/ata/pata_hpt366.c
+--- linux-3.14.72.orig/drivers/ata/pata_hpt366.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_hpt366.c 2016-06-19 22:11:55.093153915 +0200
+@@ -19,7 +19,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -387,7 +386,7 @@
+ return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int hpt36x_reinit_one(struct pci_dev *dev)
+ {
+ struct ata_host *host = pci_get_drvdata(dev);
+@@ -412,7 +411,7 @@
+ .id_table = hpt36x,
+ .probe = hpt36x_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = hpt36x_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_hpt37x.c linux-3.14.72/drivers/ata/pata_hpt37x.c
+--- linux-3.14.72.orig/drivers/ata/pata_hpt37x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_hpt37x.c 2016-06-19 22:11:55.093153915 +0200
+@@ -19,7 +19,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_hpt3x2n.c linux-3.14.72/drivers/ata/pata_hpt3x2n.c
+--- linux-3.14.72.orig/drivers/ata/pata_hpt3x2n.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_hpt3x2n.c 2016-06-19 22:11:55.093153915 +0200
+@@ -20,7 +20,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_hpt3x3.c linux-3.14.72/drivers/ata/pata_hpt3x3.c
+--- linux-3.14.72.orig/drivers/ata/pata_hpt3x3.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_hpt3x3.c 2016-06-19 22:11:55.093153915 +0200
+@@ -16,7 +16,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -250,7 +249,7 @@
+ IRQF_SHARED, &hpt3x3_sht);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int hpt3x3_reinit_one(struct pci_dev *dev)
+ {
+ struct ata_host *host = pci_get_drvdata(dev);
+@@ -278,7 +277,7 @@
+ .id_table = hpt3x3,
+ .probe = hpt3x3_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = hpt3x3_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_imx.c linux-3.14.72/drivers/ata/pata_imx.c
+--- linux-3.14.72.orig/drivers/ata/pata_imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_imx.c 2016-06-19 22:11:55.093153915 +0200
+@@ -15,7 +15,6 @@
+ */
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <scsi/scsi_host.h>
+ #include <linux/ata.h>
+@@ -191,7 +190,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int pata_imx_suspend(struct device *dev)
+ {
+ struct ata_host *host = dev_get_drvdata(dev);
+@@ -250,7 +249,7 @@
+ .name = DRV_NAME,
+ .of_match_table = imx_pata_dt_ids,
+ .owner = THIS_MODULE,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .pm = &pata_imx_pm_ops,
+ #endif
+ },
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_it8213.c linux-3.14.72/drivers/ata/pata_it8213.c
+--- linux-3.14.72.orig/drivers/ata/pata_it8213.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_it8213.c 2016-06-19 22:11:55.093153915 +0200
+@@ -10,7 +10,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -284,7 +283,7 @@
+ .id_table = it8213_pci_tbl,
+ .probe = it8213_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_it821x.c linux-3.14.72/drivers/ata/pata_it821x.c
+--- linux-3.14.72.orig/drivers/ata/pata_it821x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_it821x.c 2016-06-19 22:11:55.093153915 +0200
+@@ -72,7 +72,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/slab.h>
+@@ -936,7 +935,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &it821x_sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int it821x_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -966,7 +965,7 @@
+ .id_table = it821x,
+ .probe = it821x_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = it821x_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_jmicron.c linux-3.14.72/drivers/ata/pata_jmicron.c
+--- linux-3.14.72.orig/drivers/ata/pata_jmicron.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_jmicron.c 2016-06-19 22:11:55.093153915 +0200
+@@ -10,7 +10,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -158,7 +157,7 @@
+ .id_table = jmicron_pci_tbl,
+ .probe = jmicron_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_legacy.c linux-3.14.72/drivers/ata/pata_legacy.c
+--- linux-3.14.72.orig/drivers/ata/pata_legacy.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_legacy.c 2016-06-19 22:11:55.093153915 +0200
+@@ -916,7 +916,6 @@
+ local_irq_restore(flags);
+ return BIOS;
+ }
+- local_irq_restore(flags);
+ }
+
+ if (ht6560a & mask)
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_macio.c linux-3.14.72/drivers/ata/pata_macio.c
+--- linux-3.14.72.orig/drivers/ata/pata_macio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_macio.c 2016-06-19 22:11:55.097153654 +0200
+@@ -845,8 +845,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
+-
++#ifdef CONFIG_PM_SLEEP
+ static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
+ {
+ int rc;
+@@ -907,8 +906,7 @@
+
+ return 0;
+ }
+-
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
+
+ static struct scsi_host_template pata_macio_sht = {
+ ATA_BASE_SHT(DRV_NAME),
+@@ -1208,8 +1206,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
+-
++#ifdef CONFIG_PM_SLEEP
+ static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
+ {
+ struct ata_host *host = macio_get_drvdata(mdev);
+@@ -1223,8 +1220,7 @@
+
+ return pata_macio_do_resume(host->private_data);
+ }
+-
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
+
+ #ifdef CONFIG_PMAC_MEDIABAY
+ static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
+@@ -1316,8 +1312,7 @@
+ ata_host_detach(host);
+ }
+
+-#ifdef CONFIG_PM
+-
++#ifdef CONFIG_PM_SLEEP
+ static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -1331,8 +1326,7 @@
+
+ return pata_macio_do_resume(host->private_data);
+ }
+-
+-#endif /* CONFIG_PM */
++#endif /* CONFIG_PM_SLEEP */
+
+ static struct of_device_id pata_macio_match[] =
+ {
+@@ -1360,7 +1354,7 @@
+ },
+ .probe = pata_macio_attach,
+ .remove = pata_macio_detach,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = pata_macio_suspend,
+ .resume = pata_macio_resume,
+ #endif
+@@ -1383,7 +1377,7 @@
+ .id_table = pata_macio_pci_match,
+ .probe = pata_macio_pci_attach,
+ .remove = pata_macio_pci_detach,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = pata_macio_pci_suspend,
+ .resume = pata_macio_pci_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_marvell.c linux-3.14.72/drivers/ata/pata_marvell.c
+--- linux-3.14.72.orig/drivers/ata/pata_marvell.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_marvell.c 2016-06-19 22:11:55.097153654 +0200
+@@ -11,7 +11,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -172,7 +171,7 @@
+ .id_table = marvell_pci_tbl,
+ .probe = marvell_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_mpc52xx.c linux-3.14.72/drivers/ata/pata_mpc52xx.c
+--- linux-3.14.72.orig/drivers/ata/pata_mpc52xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_mpc52xx.c 2016-06-19 22:11:55.097153654 +0200
+@@ -819,9 +819,7 @@
+ return 0;
+ }
+
+-
+-#ifdef CONFIG_PM
+-
++#ifdef CONFIG_PM_SLEEP
+ static int
+ mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state)
+ {
+@@ -847,10 +845,8 @@
+
+ return 0;
+ }
+-
+ #endif
+
+-
+ static struct of_device_id mpc52xx_ata_of_match[] = {
+ { .compatible = "fsl,mpc5200-ata", },
+ { .compatible = "mpc5200-ata", },
+@@ -861,7 +857,7 @@
+ static struct platform_driver mpc52xx_ata_of_platform_driver = {
+ .probe = mpc52xx_ata_probe,
+ .remove = mpc52xx_ata_remove,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = mpc52xx_ata_suspend,
+ .resume = mpc52xx_ata_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_mpiix.c linux-3.14.72/drivers/ata/pata_mpiix.c
+--- linux-3.14.72.orig/drivers/ata/pata_mpiix.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_mpiix.c 2016-06-19 22:11:55.097153654 +0200
+@@ -28,7 +28,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -224,7 +223,7 @@
+ .id_table = mpiix,
+ .probe = mpiix_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_netcell.c linux-3.14.72/drivers/ata/pata_netcell.c
+--- linux-3.14.72.orig/drivers/ata/pata_netcell.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_netcell.c 2016-06-19 22:11:55.097153654 +0200
+@@ -7,7 +7,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -93,7 +92,7 @@
+ .id_table = netcell_pci_tbl,
+ .probe = netcell_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_ninja32.c linux-3.14.72/drivers/ata/pata_ninja32.c
+--- linux-3.14.72.orig/drivers/ata/pata_ninja32.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_ninja32.c 2016-06-19 22:11:55.097153654 +0200
+@@ -37,7 +37,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -153,8 +152,7 @@
+ IRQF_SHARED, &ninja32_sht);
+ }
+
+-#ifdef CONFIG_PM
+-
++#ifdef CONFIG_PM_SLEEP
+ static int ninja32_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -184,7 +182,7 @@
+ .id_table = ninja32,
+ .probe = ninja32_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ninja32_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_ns87410.c linux-3.14.72/drivers/ata/pata_ns87410.c
+--- linux-3.14.72.orig/drivers/ata/pata_ns87410.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_ns87410.c 2016-06-19 22:11:55.097153654 +0200
+@@ -20,7 +20,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -162,7 +161,7 @@
+ .id_table = ns87410,
+ .probe = ns87410_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_ns87415.c linux-3.14.72/drivers/ata/pata_ns87415.c
+--- linux-3.14.72.orig/drivers/ata/pata_ns87415.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_ns87415.c 2016-06-19 22:11:55.097153654 +0200
+@@ -25,7 +25,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -386,7 +385,7 @@
+ { } /* terminate list */
+ };
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int ns87415_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -408,7 +407,7 @@
+ .id_table = ns87415_pci_tbl,
+ .probe = ns87415_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ns87415_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_oldpiix.c linux-3.14.72/drivers/ata/pata_oldpiix.c
+--- linux-3.14.72.orig/drivers/ata/pata_oldpiix.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_oldpiix.c 2016-06-19 22:11:55.097153654 +0200
+@@ -16,7 +16,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -259,7 +258,7 @@
+ .id_table = oldpiix_pci_tbl,
+ .probe = oldpiix_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_opti.c linux-3.14.72/drivers/ata/pata_opti.c
+--- linux-3.14.72.orig/drivers/ata/pata_opti.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_opti.c 2016-06-19 22:11:55.097153654 +0200
+@@ -26,7 +26,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -185,7 +184,7 @@
+ .id_table = opti,
+ .probe = opti_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_optidma.c linux-3.14.72/drivers/ata/pata_optidma.c
+--- linux-3.14.72.orig/drivers/ata/pata_optidma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_optidma.c 2016-06-19 22:11:55.097153654 +0200
+@@ -25,7 +25,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -441,7 +440,7 @@
+ .id_table = optidma,
+ .probe = optidma_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_pcmcia.c linux-3.14.72/drivers/ata/pata_pcmcia.c
+--- linux-3.14.72.orig/drivers/ata/pata_pcmcia.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_pcmcia.c 2016-06-19 22:11:55.097153654 +0200
+@@ -26,7 +26,6 @@
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/slab.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_pdc2027x.c linux-3.14.72/drivers/ata/pata_pdc2027x.c
+--- linux-3.14.72.orig/drivers/ata/pata_pdc2027x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_pdc2027x.c 2016-06-19 22:11:55.097153654 +0200
+@@ -25,7 +25,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -63,7 +62,7 @@
+ };
+
+ static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int pdc2027x_reinit_one(struct pci_dev *pdev);
+ #endif
+ static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
+@@ -129,7 +128,7 @@
+ .id_table = pdc2027x_pci_tbl,
+ .probe = pdc2027x_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = pdc2027x_reinit_one,
+ #endif
+@@ -762,7 +761,7 @@
+ IRQF_SHARED, &pdc2027x_sht);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int pdc2027x_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_pdc202xx_old.c linux-3.14.72/drivers/ata/pata_pdc202xx_old.c
+--- linux-3.14.72.orig/drivers/ata/pata_pdc202xx_old.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_pdc202xx_old.c 2016-06-19 22:11:55.097153654 +0200
+@@ -15,7 +15,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -378,7 +377,7 @@
+ .id_table = pdc202xx,
+ .probe = pdc202xx_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_piccolo.c linux-3.14.72/drivers/ata/pata_piccolo.c
+--- linux-3.14.72.orig/drivers/ata/pata_piccolo.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_piccolo.c 2016-06-19 22:11:55.097153654 +0200
+@@ -18,7 +18,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -111,7 +110,7 @@
+ .id_table = ata_tosh,
+ .probe = ata_tosh_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_platform.c linux-3.14.72/drivers/ata/pata_platform.c
+--- linux-3.14.72.orig/drivers/ata/pata_platform.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_platform.c 2016-06-19 22:11:55.097153654 +0200
+@@ -13,7 +13,6 @@
+ */
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <scsi/scsi_host.h>
+ #include <linux/ata.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_pxa.c linux-3.14.72/drivers/ata/pata_pxa.c
+--- linux-3.14.72.orig/drivers/ata/pata_pxa.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_pxa.c 2016-06-19 22:11:55.097153654 +0200
+@@ -20,7 +20,6 @@
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/ata.h>
+ #include <linux/libata.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_radisys.c linux-3.14.72/drivers/ata/pata_radisys.c
+--- linux-3.14.72.orig/drivers/ata/pata_radisys.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_radisys.c 2016-06-19 22:11:55.097153654 +0200
+@@ -15,7 +15,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -238,7 +237,7 @@
+ .id_table = radisys_pci_tbl,
+ .probe = radisys_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_rdc.c linux-3.14.72/drivers/ata/pata_rdc.c
+--- linux-3.14.72.orig/drivers/ata/pata_rdc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_rdc.c 2016-06-19 22:11:55.097153654 +0200
+@@ -24,7 +24,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -383,7 +382,7 @@
+ .id_table = rdc_pci_tbl,
+ .probe = rdc_init_one,
+ .remove = rdc_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_rz1000.c linux-3.14.72/drivers/ata/pata_rz1000.c
+--- linux-3.14.72.orig/drivers/ata/pata_rz1000.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_rz1000.c 2016-06-19 22:11:55.097153654 +0200
+@@ -14,7 +14,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -102,7 +101,7 @@
+ return -ENODEV;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int rz1000_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -134,7 +133,7 @@
+ .id_table = pata_rz1000,
+ .probe = rz1000_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = rz1000_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_samsung_cf.c linux-3.14.72/drivers/ata/pata_samsung_cf.c
+--- linux-3.14.72.orig/drivers/ata/pata_samsung_cf.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_samsung_cf.c 2016-06-19 22:11:55.097153654 +0200
+@@ -54,7 +54,6 @@
+
+ enum s3c_cpu_type {
+ TYPE_S3C64XX,
+- TYPE_S5PC100,
+ TYPE_S5PV210,
+ };
+
+@@ -476,10 +475,6 @@
+ writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
+ break;
+
+- case TYPE_S5PC100:
+- pata_s3c_cfg_mode(info->sfr_addr);
+- /* FALLTHROUGH */
+-
+ case TYPE_S5PV210:
+ /* Configure as little endian */
+ pata_s3c_set_endian(info->ide_addr, 0);
+@@ -549,11 +544,6 @@
+ info->sfr_addr = info->ide_addr + 0x1800;
+ info->ide_addr += 0x1900;
+ info->fifo_status_reg = 0x94;
+- } else if (cpu_type == TYPE_S5PC100) {
+- ap->ops = &pata_s5p_port_ops;
+- info->sfr_addr = info->ide_addr + 0x1800;
+- info->ide_addr += 0x1900;
+- info->fifo_status_reg = 0x84;
+ } else {
+ ap->ops = &pata_s5p_port_ops;
+ info->fifo_status_reg = 0x84;
+@@ -615,7 +605,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int pata_s3c_suspend(struct device *dev)
+ {
+ struct platform_device *pdev = to_platform_device(dev);
+@@ -649,9 +639,6 @@
+ .name = "s3c64xx-pata",
+ .driver_data = TYPE_S3C64XX,
+ }, {
+- .name = "s5pc100-pata",
+- .driver_data = TYPE_S5PC100,
+- }, {
+ .name = "s5pv210-pata",
+ .driver_data = TYPE_S5PV210,
+ },
+@@ -666,7 +653,7 @@
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .pm = &pata_s3c_pm_ops,
+ #endif
+ },
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_sc1200.c linux-3.14.72/drivers/ata/pata_sc1200.c
+--- linux-3.14.72.orig/drivers/ata/pata_sc1200.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_sc1200.c 2016-06-19 22:11:55.097153654 +0200
+@@ -32,7 +32,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -255,7 +254,7 @@
+ .id_table = sc1200,
+ .probe = sc1200_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_scc.c linux-3.14.72/drivers/ata/pata_scc.c
+--- linux-3.14.72.orig/drivers/ata/pata_scc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_scc.c 2016-06-19 22:11:55.097153654 +0200
+@@ -35,7 +35,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -1096,7 +1095,7 @@
+ .id_table = scc_pci_tbl,
+ .probe = scc_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_sch.c linux-3.14.72/drivers/ata/pata_sch.c
+--- linux-3.14.72.orig/drivers/ata/pata_sch.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_sch.c 2016-06-19 22:11:55.097153654 +0200
+@@ -27,7 +27,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -65,7 +64,7 @@
+ .id_table = sch_pci_tbl,
+ .probe = sch_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_serverworks.c linux-3.14.72/drivers/ata/pata_serverworks.c
+--- linux-3.14.72.orig/drivers/ata/pata_serverworks.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_serverworks.c 2016-06-19 22:11:55.097153654 +0200
+@@ -34,7 +34,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -446,7 +445,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int serverworks_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -478,7 +477,7 @@
+ .id_table = serverworks,
+ .probe = serverworks_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = serverworks_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_sil680.c linux-3.14.72/drivers/ata/pata_sil680.c
+--- linux-3.14.72.orig/drivers/ata/pata_sil680.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_sil680.c 2016-06-19 22:11:55.097153654 +0200
+@@ -25,7 +25,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -404,7 +403,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sil680_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -430,7 +429,7 @@
+ .id_table = sil680,
+ .probe = sil680_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = sil680_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_sis.c linux-3.14.72/drivers/ata/pata_sis.c
+--- linux-3.14.72.orig/drivers/ata/pata_sis.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_sis.c 2016-06-19 22:11:55.101153393 +0200
+@@ -26,7 +26,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -870,7 +869,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &sis_sht, chipset, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sis_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -900,7 +899,7 @@
+ .id_table = sis_pci_tbl,
+ .probe = sis_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = sis_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_sl82c105.c linux-3.14.72/drivers/ata/pata_sl82c105.c
+--- linux-3.14.72.orig/drivers/ata/pata_sl82c105.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_sl82c105.c 2016-06-19 22:11:55.101153393 +0200
+@@ -19,7 +19,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -338,7 +337,7 @@
+ return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sl82c105_reinit_one(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -366,7 +365,7 @@
+ .id_table = sl82c105,
+ .probe = sl82c105_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = sl82c105_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_triflex.c linux-3.14.72/drivers/ata/pata_triflex.c
+--- linux-3.14.72.orig/drivers/ata/pata_triflex.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_triflex.c 2016-06-19 22:11:55.101153393 +0200
+@@ -36,7 +36,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <scsi/scsi_host.h>
+@@ -208,7 +207,7 @@
+ { },
+ };
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int triflex_ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -234,7 +233,7 @@
+ .id_table = triflex,
+ .probe = triflex_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = triflex_ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pata_via.c linux-3.14.72/drivers/ata/pata_via.c
+--- linux-3.14.72.orig/drivers/ata/pata_via.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pata_via.c 2016-06-19 22:11:55.101153393 +0200
+@@ -55,7 +55,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/gfp.h>
+@@ -660,7 +659,7 @@
+ return ata_pci_bmdma_init_one(pdev, ppi, &via_sht, (void *)config, 0);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ /**
+ * via_reinit_one - reinit after resume
+ * @pdev; PCI device
+@@ -705,7 +704,7 @@
+ .id_table = via,
+ .probe = via_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = via_reinit_one,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/pdc_adma.c linux-3.14.72/drivers/ata/pdc_adma.c
+--- linux-3.14.72.orig/drivers/ata/pdc_adma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/pdc_adma.c 2016-06-19 22:11:55.101153393 +0200
+@@ -36,7 +36,6 @@
+ #include <linux/module.h>
+ #include <linux/gfp.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_dwc_460ex.c linux-3.14.72/drivers/ata/sata_dwc_460ex.c
+--- linux-3.14.72.orig/drivers/ata/sata_dwc_460ex.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_dwc_460ex.c 2016-06-19 22:11:55.101153393 +0200
+@@ -29,7 +29,6 @@
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/device.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+@@ -462,8 +461,7 @@
+ int chan;
+ u32 tfr_reg, err_reg;
+ unsigned long flags;
+- struct sata_dwc_device *hsdev =
+- (struct sata_dwc_device *)hsdev_instance;
++ struct sata_dwc_device *hsdev = hsdev_instance;
+ struct ata_host *host = (struct ata_host *)hsdev->host;
+ struct ata_port *ap;
+ struct sata_dwc_device_port *hsdevp;
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_fsl.c linux-3.14.72/drivers/ata/sata_fsl.c
+--- linux-3.14.72.orig/drivers/ata/sata_fsl.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_fsl.c 2016-06-19 22:11:55.101153393 +0200
+@@ -734,13 +734,12 @@
+ if (!pp)
+ return -ENOMEM;
+
+- mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
+- GFP_KERNEL);
++ mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
++ GFP_KERNEL);
+ if (!mem) {
+ kfree(pp);
+ return -ENOMEM;
+ }
+- memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ);
+
+ pp->cmdslot = mem;
+ pp->cmdslot_paddr = mem_dma;
+@@ -774,20 +773,6 @@
+ VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
+ VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
+
+-#ifdef CONFIG_MPC8315_DS
+- /*
+- * Workaround for 8315DS board 3gbps link-up issue,
+- * currently limit SATA port to GEN1 speed
+- */
+- sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
+- temp &= ~(0xF << 4);
+- temp |= (0x1 << 4);
+- sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp);
+-
+- sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp);
+- dev_warn(dev, "scr_control, speed limited to %x\n", temp);
+-#endif
+-
+ return 0;
+ }
+
+@@ -1588,7 +1573,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
+ {
+ struct ata_host *host = platform_get_drvdata(op);
+@@ -1644,7 +1629,7 @@
+ },
+ .probe = sata_fsl_probe,
+ .remove = sata_fsl_remove,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = sata_fsl_suspend,
+ .resume = sata_fsl_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_highbank.c linux-3.14.72/drivers/ata/sata_highbank.c
+--- linux-3.14.72.orig/drivers/ata/sata_highbank.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_highbank.c 2016-06-19 22:11:55.101153393 +0200
+@@ -19,7 +19,6 @@
+ #include <linux/kernel.h>
+ #include <linux/gfp.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/types.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
+@@ -403,6 +402,7 @@
+ static const unsigned long timing[] = { 5, 100, 500};
+ struct ata_port *ap = link->ap;
+ struct ahci_port_priv *pp = ap->private_data;
++ struct ahci_host_priv *hpriv = ap->host->private_data;
+ u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
+ struct ata_taskfile tf;
+ bool online;
+@@ -431,7 +431,7 @@
+ break;
+ } while (!online && retry--);
+
+- ahci_start_engine(ap);
++ hpriv->start_engine(ap);
+
+ if (online)
+ *class = ahci_dev_classify(ap);
+@@ -512,7 +512,7 @@
+ return rc;
+
+
+- ahci_save_initial_config(dev, hpriv, 0, 0);
++ ahci_save_initial_config(dev, hpriv);
+
+ /* prepare host */
+ if (hpriv->cap & HOST_CAP_NCQ)
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_inic162x.c linux-3.14.72/drivers/ata/sata_inic162x.c
+--- linux-3.14.72.orig/drivers/ata/sata_inic162x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_inic162x.c 2016-06-19 22:11:55.101153393 +0200
+@@ -785,7 +785,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int inic_pci_device_resume(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -898,7 +898,7 @@
+ static struct pci_driver inic_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = inic_pci_tbl,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = inic_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_mv.c linux-3.14.72/drivers/ata/sata_mv.c
+--- linux-3.14.72.orig/drivers/ata/sata_mv.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_mv.c 2016-06-19 22:11:55.101153393 +0200
+@@ -4222,7 +4222,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
+ {
+ struct ata_host *host = platform_get_drvdata(pdev);
+@@ -4289,7 +4289,7 @@
+ #ifdef CONFIG_PCI
+ static int mv_pci_init_one(struct pci_dev *pdev,
+ const struct pci_device_id *ent);
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int mv_pci_device_resume(struct pci_dev *pdev);
+ #endif
+
+@@ -4299,7 +4299,7 @@
+ .id_table = mv_pci_tbl,
+ .probe = mv_pci_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = mv_pci_device_resume,
+ #endif
+@@ -4457,7 +4457,7 @@
+ IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int mv_pci_device_resume(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_nv.c linux-3.14.72/drivers/ata/sata_nv.c
+--- linux-3.14.72.orig/drivers/ata/sata_nv.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_nv.c 2016-06-19 22:11:55.101153393 +0200
+@@ -40,7 +40,6 @@
+ #include <linux/module.h>
+ #include <linux/gfp.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -296,7 +295,7 @@
+ #define NV_ADMA_CHECK_INTR(GCTL, PORT) ((GCTL) & (1 << (19 + (12 * (PORT)))))
+
+ static int nv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int nv_pci_device_resume(struct pci_dev *pdev);
+ #endif
+ static void nv_ck804_host_stop(struct ata_host *host);
+@@ -380,7 +379,7 @@
+ .name = DRV_NAME,
+ .id_table = nv_pci_tbl,
+ .probe = nv_init_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = nv_pci_device_resume,
+ #endif
+@@ -2432,7 +2431,7 @@
+ return ata_pci_sff_activate_host(host, ipriv->irq_handler, ipriv->sht);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int nv_pci_device_resume(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_promise.c linux-3.14.72/drivers/ata/sata_promise.c
+--- linux-3.14.72.orig/drivers/ata/sata_promise.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_promise.c 2016-06-19 22:11:55.101153393 +0200
+@@ -35,7 +35,6 @@
+ #include <linux/module.h>
+ #include <linux/gfp.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_qstor.c linux-3.14.72/drivers/ata/sata_qstor.c
+--- linux-3.14.72.orig/drivers/ata/sata_qstor.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_qstor.c 2016-06-19 22:11:55.101153393 +0200
+@@ -31,7 +31,6 @@
+ #include <linux/module.h>
+ #include <linux/gfp.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_rcar.c linux-3.14.72/drivers/ata/sata_rcar.c
+--- linux-3.14.72.orig/drivers/ata/sata_rcar.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_rcar.c 2016-06-19 22:11:55.101153393 +0200
+@@ -947,7 +947,7 @@
+ return 0;
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sata_rcar_suspend(struct device *dev)
+ {
+ struct ata_host *host = dev_get_drvdata(dev);
+@@ -1001,7 +1001,7 @@
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = sata_rcar_match,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .pm = &sata_rcar_pm_ops,
+ #endif
+ },
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_sil24.c linux-3.14.72/drivers/ata/sata_sil24.c
+--- linux-3.14.72.orig/drivers/ata/sata_sil24.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_sil24.c 2016-06-19 22:11:55.105153131 +0200
+@@ -353,8 +353,10 @@
+ static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
+ static int sil24_port_start(struct ata_port *ap);
+ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sil24_pci_device_resume(struct pci_dev *pdev);
++#endif
++#ifdef CONFIG_PM
+ static int sil24_port_resume(struct ata_port *ap);
+ #endif
+
+@@ -375,7 +377,7 @@
+ .id_table = sil24_pci_tbl,
+ .probe = sil24_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = sil24_pci_device_resume,
+ #endif
+@@ -1350,7 +1352,7 @@
+ &sil24_sht);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sil24_pci_device_resume(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+@@ -1370,7 +1372,9 @@
+
+ return 0;
+ }
++#endif
+
++#ifdef CONFIG_PM
+ static int sil24_port_resume(struct ata_port *ap)
+ {
+ sil24_config_pmp(ap, ap->nr_pmp_links);
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_sil.c linux-3.14.72/drivers/ata/sata_sil.c
+--- linux-3.14.72.orig/drivers/ata/sata_sil.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_sil.c 2016-06-19 22:11:55.105153131 +0200
+@@ -37,7 +37,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -113,7 +112,7 @@
+ };
+
+ static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sil_pci_device_resume(struct pci_dev *pdev);
+ #endif
+ static void sil_dev_config(struct ata_device *dev);
+@@ -167,7 +166,7 @@
+ .id_table = sil_pci_tbl,
+ .probe = sil_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = sil_pci_device_resume,
+ #endif
+@@ -806,7 +805,7 @@
+ &sil_sht);
+ }
+
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ static int sil_pci_device_resume(struct pci_dev *pdev)
+ {
+ struct ata_host *host = pci_get_drvdata(pdev);
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_sis.c linux-3.14.72/drivers/ata/sata_sis.c
+--- linux-3.14.72.orig/drivers/ata/sata_sis.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_sis.c 2016-06-19 22:11:55.105153131 +0200
+@@ -33,7 +33,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -83,7 +82,7 @@
+ .id_table = sis_pci_tbl,
+ .probe = sis_init_one,
+ .remove = ata_pci_remove_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_svw.c linux-3.14.72/drivers/ata/sata_svw.c
+--- linux-3.14.72.orig/drivers/ata/sata_svw.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_svw.c 2016-06-19 22:11:55.105153131 +0200
+@@ -39,7 +39,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_sx4.c linux-3.14.72/drivers/ata/sata_sx4.c
+--- linux-3.14.72.orig/drivers/ata/sata_sx4.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_sx4.c 2016-06-19 22:11:55.105153131 +0200
+@@ -82,7 +82,6 @@
+ #include <linux/module.h>
+ #include <linux/pci.h>
+ #include <linux/slab.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+@@ -1021,8 +1020,7 @@
+ idx++;
+ dist = ((long) (window_size - (offset + size))) >= 0 ? size :
+ (long) (window_size - offset);
+- memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
+- dist);
++ memcpy_fromio(psource, dimm_mmio + offset / 4, dist);
+
+ psource += dist;
+ size -= dist;
+@@ -1031,8 +1029,7 @@
+ readl(mmio + PDC_GENERAL_CTLR);
+ writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
+ readl(mmio + PDC_DIMM_WINDOW_CTLR);
+- memcpy_fromio((char *) psource, (char *) (dimm_mmio),
+- window_size / 4);
++ memcpy_fromio(psource, dimm_mmio, window_size / 4);
+ psource += window_size;
+ size -= window_size;
+ idx++;
+@@ -1043,8 +1040,7 @@
+ readl(mmio + PDC_GENERAL_CTLR);
+ writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
+ readl(mmio + PDC_DIMM_WINDOW_CTLR);
+- memcpy_fromio((char *) psource, (char *) (dimm_mmio),
+- size / 4);
++ memcpy_fromio(psource, dimm_mmio, size / 4);
+ }
+ }
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_uli.c linux-3.14.72/drivers/ata/sata_uli.c
+--- linux-3.14.72.orig/drivers/ata/sata_uli.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_uli.c 2016-06-19 22:11:55.105153131 +0200
+@@ -28,7 +28,6 @@
+ #include <linux/module.h>
+ #include <linux/gfp.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_via.c linux-3.14.72/drivers/ata/sata_via.c
+--- linux-3.14.72.orig/drivers/ata/sata_via.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_via.c 2016-06-19 22:11:55.105153131 +0200
+@@ -36,7 +36,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+@@ -104,7 +103,7 @@
+ .name = DRV_NAME,
+ .id_table = svia_pci_tbl,
+ .probe = svia_init_one,
+-#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
+ .suspend = ata_pci_device_suspend,
+ .resume = ata_pci_device_resume,
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/ata/sata_vsc.c linux-3.14.72/drivers/ata/sata_vsc.c
+--- linux-3.14.72.orig/drivers/ata/sata_vsc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ata/sata_vsc.c 2016-06-19 22:11:55.105153131 +0200
+@@ -37,7 +37,6 @@
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+ #include <linux/pci.h>
+-#include <linux/init.h>
+ #include <linux/blkdev.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/base/attribute_container.c linux-3.14.72/drivers/base/attribute_container.c
+--- linux-3.14.72.orig/drivers/base/attribute_container.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/attribute_container.c 2016-06-19 22:11:55.105153131 +0200
+@@ -12,7 +12,6 @@
+ */
+
+ #include <linux/attribute_container.h>
+-#include <linux/init.h>
+ #include <linux/device.h>
+ #include <linux/kernel.h>
+ #include <linux/slab.h>
+diff -Nur linux-3.14.72.orig/drivers/base/dma-contiguous.c linux-3.14.72/drivers/base/dma-contiguous.c
+--- linux-3.14.72.orig/drivers/base/dma-contiguous.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/dma-contiguous.c 2016-06-19 22:11:55.105153131 +0200
+@@ -24,22 +24,9 @@
+
+ #include <linux/memblock.h>
+ #include <linux/err.h>
+-#include <linux/mm.h>
+-#include <linux/mutex.h>
+-#include <linux/page-isolation.h>
+ #include <linux/sizes.h>
+-#include <linux/slab.h>
+-#include <linux/swap.h>
+-#include <linux/mm_types.h>
+ #include <linux/dma-contiguous.h>
+-
+-struct cma {
+- unsigned long base_pfn;
+- unsigned long count;
+- unsigned long *bitmap;
+-};
+-
+-struct cma *dma_contiguous_default_area;
++#include <linux/cma.h>
+
+ #ifdef CONFIG_CMA_SIZE_MBYTES
+ #define CMA_SIZE_MBYTES CONFIG_CMA_SIZE_MBYTES
+@@ -47,6 +34,8 @@
+ #define CMA_SIZE_MBYTES 0
+ #endif
+
++struct cma *dma_contiguous_default_area;
++
+ /*
+ * Default global CMA area size can be defined in kernel's .config.
+ * This is useful mainly for distro maintainers to create a kernel
+@@ -59,11 +48,22 @@
+ */
+ static const phys_addr_t size_bytes = CMA_SIZE_MBYTES * SZ_1M;
+ static phys_addr_t size_cmdline = -1;
++static phys_addr_t base_cmdline;
++static phys_addr_t limit_cmdline;
+
+ static int __init early_cma(char *p)
+ {
+ pr_debug("%s(%s)\n", __func__, p);
+ size_cmdline = memparse(p, &p);
++ if (*p != '@')
++ return 0;
++ base_cmdline = memparse(p + 1, &p);
++ if (*p != '-') {
++ limit_cmdline = base_cmdline + size_cmdline;
++ return 0;
++ }
++ limit_cmdline = memparse(p + 1, &p);
++
+ return 0;
+ }
+ early_param("cma", early_cma);
+@@ -107,11 +107,18 @@
+ void __init dma_contiguous_reserve(phys_addr_t limit)
+ {
+ phys_addr_t selected_size = 0;
++ phys_addr_t selected_base = 0;
++ phys_addr_t selected_limit = limit;
++ bool fixed = false;
+
+ pr_debug("%s(limit %08lx)\n", __func__, (unsigned long)limit);
+
+ if (size_cmdline != -1) {
+ selected_size = size_cmdline;
++ selected_base = base_cmdline;
++ selected_limit = min_not_zero(limit_cmdline, limit);
++ if (base_cmdline + size_cmdline == limit_cmdline)
++ fixed = true;
+ } else {
+ #ifdef CONFIG_CMA_SIZE_SEL_MBYTES
+ selected_size = size_bytes;
+@@ -128,68 +135,12 @@
+ pr_debug("%s: reserving %ld MiB for global area\n", __func__,
+ (unsigned long)selected_size / SZ_1M);
+
+- dma_contiguous_reserve_area(selected_size, 0, limit,
+- &dma_contiguous_default_area);
+- }
+-};
+-
+-static DEFINE_MUTEX(cma_mutex);
+-
+-static int __init cma_activate_area(struct cma *cma)
+-{
+- int bitmap_size = BITS_TO_LONGS(cma->count) * sizeof(long);
+- unsigned long base_pfn = cma->base_pfn, pfn = base_pfn;
+- unsigned i = cma->count >> pageblock_order;
+- struct zone *zone;
+-
+- cma->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+-
+- if (!cma->bitmap)
+- return -ENOMEM;
+-
+- WARN_ON_ONCE(!pfn_valid(pfn));
+- zone = page_zone(pfn_to_page(pfn));
+-
+- do {
+- unsigned j;
+- base_pfn = pfn;
+- for (j = pageblock_nr_pages; j; --j, pfn++) {
+- WARN_ON_ONCE(!pfn_valid(pfn));
+- /*
+- * alloc_contig_range requires the pfn range
+- * specified to be in the same zone. Make this
+- * simple by forcing the entire CMA resv range
+- * to be in the same zone.
+- */
+- if (page_zone(pfn_to_page(pfn)) != zone)
+- goto err;
+- }
+- init_cma_reserved_pageblock(pfn_to_page(base_pfn));
+- } while (--i);
+-
+- return 0;
+-
+-err:
+- kfree(cma->bitmap);
+- return -EINVAL;
+-}
+-
+-static struct cma cma_areas[MAX_CMA_AREAS];
+-static unsigned cma_area_count;
+-
+-static int __init cma_init_reserved_areas(void)
+-{
+- int i;
+-
+- for (i = 0; i < cma_area_count; i++) {
+- int ret = cma_activate_area(&cma_areas[i]);
+- if (ret)
+- return ret;
++ dma_contiguous_reserve_area(selected_size, selected_base,
++ selected_limit,
++ &dma_contiguous_default_area,
++ fixed);
+ }
+-
+- return 0;
+ }
+-core_initcall(cma_init_reserved_areas);
+
+ /**
+ * dma_contiguous_reserve_area() - reserve custom contiguous area
+@@ -197,78 +148,32 @@
+ * @base: Base address of the reserved area optional, use 0 for any
+ * @limit: End address of the reserved memory (optional, 0 for any).
+ * @res_cma: Pointer to store the created cma region.
++ * @fixed: hint about where to place the reserved area
+ *
+ * This function reserves memory from early allocator. It should be
+ * called by arch specific code once the early allocator (memblock or bootmem)
+ * has been activated and all other subsystems have already allocated/reserved
+ * memory. This function allows to create custom reserved areas for specific
+ * devices.
++ *
++ * If @fixed is true, reserve contiguous area at exactly @base. If false,
++ * reserve in range from @base to @limit.
+ */
+ int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
+- phys_addr_t limit, struct cma **res_cma)
++ phys_addr_t limit, struct cma **res_cma,
++ bool fixed)
+ {
+- struct cma *cma = &cma_areas[cma_area_count];
+- phys_addr_t alignment;
+- int ret = 0;
+-
+- pr_debug("%s(size %lx, base %08lx, limit %08lx)\n", __func__,
+- (unsigned long)size, (unsigned long)base,
+- (unsigned long)limit);
+-
+- /* Sanity checks */
+- if (cma_area_count == ARRAY_SIZE(cma_areas)) {
+- pr_err("Not enough slots for CMA reserved regions!\n");
+- return -ENOSPC;
+- }
+-
+- if (!size)
+- return -EINVAL;
+-
+- /* Sanitise input arguments */
+- alignment = PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order);
+- base = ALIGN(base, alignment);
+- size = ALIGN(size, alignment);
+- limit &= ~(alignment - 1);
+-
+- /* Reserve memory */
+- if (base) {
+- if (memblock_is_region_reserved(base, size) ||
+- memblock_reserve(base, size) < 0) {
+- ret = -EBUSY;
+- goto err;
+- }
+- } else {
+- /*
+- * Use __memblock_alloc_base() since
+- * memblock_alloc_base() panic()s.
+- */
+- phys_addr_t addr = __memblock_alloc_base(size, alignment, limit);
+- if (!addr) {
+- ret = -ENOMEM;
+- goto err;
+- } else {
+- base = addr;
+- }
+- }
+-
+- /*
+- * Each reserved area must be initialised later, when more kernel
+- * subsystems (like slab allocator) are available.
+- */
+- cma->base_pfn = PFN_DOWN(base);
+- cma->count = size >> PAGE_SHIFT;
+- *res_cma = cma;
+- cma_area_count++;
++ int ret;
+
+- pr_info("CMA: reserved %ld MiB at %08lx\n", (unsigned long)size / SZ_1M,
+- (unsigned long)base);
++ ret = cma_declare_contiguous(base, size, limit, 0, 0, fixed, res_cma);
++ if (ret)
++ return ret;
+
+ /* Architecture specific contiguous memory fixup. */
+- dma_contiguous_early_fixup(base, size);
++ dma_contiguous_early_fixup(cma_get_base(*res_cma),
++ cma_get_size(*res_cma));
++
+ return 0;
+-err:
+- pr_err("CMA: failed to reserve %ld MiB\n", (unsigned long)size / SZ_1M);
+- return ret;
+ }
+
+ /**
+@@ -279,57 +184,16 @@
+ *
+ * This function allocates memory buffer for specified device. It uses
+ * device specific contiguous memory area if available or the default
+- * global one. Requires architecture specific get_dev_cma_area() helper
++ * global one. Requires architecture specific dev_get_cma_area() helper
+ * function.
+ */
+ struct page *dma_alloc_from_contiguous(struct device *dev, int count,
+ unsigned int align)
+ {
+- unsigned long mask, pfn, pageno, start = 0;
+- struct cma *cma = dev_get_cma_area(dev);
+- struct page *page = NULL;
+- int ret;
+-
+- if (!cma || !cma->count)
+- return NULL;
+-
+ if (align > CONFIG_CMA_ALIGNMENT)
+ align = CONFIG_CMA_ALIGNMENT;
+
+- pr_debug("%s(cma %p, count %d, align %d)\n", __func__, (void *)cma,
+- count, align);
+-
+- if (!count)
+- return NULL;
+-
+- mask = (1 << align) - 1;
+-
+- mutex_lock(&cma_mutex);
+-
+- for (;;) {
+- pageno = bitmap_find_next_zero_area(cma->bitmap, cma->count,
+- start, count, mask);
+- if (pageno >= cma->count)
+- break;
+-
+- pfn = cma->base_pfn + pageno;
+- ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
+- if (ret == 0) {
+- bitmap_set(cma->bitmap, pageno, count);
+- page = pfn_to_page(pfn);
+- break;
+- } else if (ret != -EBUSY) {
+- break;
+- }
+- pr_debug("%s(): memory range at %p is busy, retrying\n",
+- __func__, pfn_to_page(pfn));
+- /* try again with a bit different memory target */
+- start = pageno + mask + 1;
+- }
+-
+- mutex_unlock(&cma_mutex);
+- pr_debug("%s(): returned %p\n", __func__, page);
+- return page;
++ return cma_alloc(dev_get_cma_area(dev), count, align);
+ }
+
+ /**
+@@ -345,25 +209,5 @@
+ bool dma_release_from_contiguous(struct device *dev, struct page *pages,
+ int count)
+ {
+- struct cma *cma = dev_get_cma_area(dev);
+- unsigned long pfn;
+-
+- if (!cma || !pages)
+- return false;
+-
+- pr_debug("%s(page %p)\n", __func__, (void *)pages);
+-
+- pfn = page_to_pfn(pages);
+-
+- if (pfn < cma->base_pfn || pfn >= cma->base_pfn + cma->count)
+- return false;
+-
+- VM_BUG_ON(pfn + count > cma->base_pfn + cma->count);
+-
+- mutex_lock(&cma_mutex);
+- bitmap_clear(cma->bitmap, pfn - cma->base_pfn, count);
+- free_contig_range(pfn, count);
+- mutex_unlock(&cma_mutex);
+-
+- return true;
++ return cma_release(dev_get_cma_area(dev), pages, count);
+ }
+diff -Nur linux-3.14.72.orig/drivers/base/Kconfig linux-3.14.72/drivers/base/Kconfig
+--- linux-3.14.72.orig/drivers/base/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/Kconfig 2016-06-19 22:11:55.105153131 +0200
+@@ -266,16 +266,6 @@
+
+ If unsure, leave the default value "8".
+
+-config CMA_AREAS
+- int "Maximum count of the CMA device-private areas"
+- default 7
+- help
+- CMA allows to create CMA areas for particular devices. This parameter
+- sets the maximum number of such device private CMA areas in the
+- system.
+-
+- If unsure, leave the default value "7".
+-
+ endif
+
+ endmenu
+diff -Nur linux-3.14.72.orig/drivers/base/platform.c linux-3.14.72/drivers/base/platform.c
+--- linux-3.14.72.orig/drivers/base/platform.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/platform.c 2016-06-19 22:11:55.105153131 +0200
+@@ -23,6 +23,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/idr.h>
+ #include <linux/acpi.h>
++#include <linux/clk/clk-conf.h>
+
+ #include "base.h"
+ #include "power/power.h"
+@@ -487,12 +488,16 @@
+ struct platform_device *dev = to_platform_device(_dev);
+ int ret;
+
+- if (ACPI_HANDLE(_dev))
+- acpi_dev_pm_attach(_dev, true);
++ ret = of_clk_set_defaults(_dev->of_node, false);
++ if (ret < 0)
++ return ret;
+
+- ret = drv->probe(dev);
+- if (ret && ACPI_HANDLE(_dev))
+- acpi_dev_pm_detach(_dev, true);
++ ret = dev_pm_domain_attach(_dev, true);
++ if (ret != -EPROBE_DEFER) {
++ ret = drv->probe(dev);
++ if (ret)
++ dev_pm_domain_detach(_dev, true);
++ }
+
+ if (drv->prevent_deferred_probe && ret == -EPROBE_DEFER) {
+ dev_warn(_dev, "probe deferral not supported\n");
+@@ -514,8 +519,7 @@
+ int ret;
+
+ ret = drv->remove(dev);
+- if (ACPI_HANDLE(_dev))
+- acpi_dev_pm_detach(_dev, true);
++ dev_pm_domain_detach(_dev, true);
+
+ return ret;
+ }
+@@ -526,8 +530,7 @@
+ struct platform_device *dev = to_platform_device(_dev);
+
+ drv->shutdown(dev);
+- if (ACPI_HANDLE(_dev))
+- acpi_dev_pm_detach(_dev, true);
++ dev_pm_domain_detach(_dev, true);
+ }
+
+ /**
+diff -Nur linux-3.14.72.orig/drivers/base/power/clock_ops.c linux-3.14.72/drivers/base/power/clock_ops.c
+--- linux-3.14.72.orig/drivers/base/power/clock_ops.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/power/clock_ops.c 2016-06-19 22:11:55.105153131 +0200
+@@ -6,7 +6,6 @@
+ * This file is released under the GPLv2.
+ */
+
+-#include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/device.h>
+ #include <linux/io.h>
+diff -Nur linux-3.14.72.orig/drivers/base/power/common.c linux-3.14.72/drivers/base/power/common.c
+--- linux-3.14.72.orig/drivers/base/power/common.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/power/common.c 2016-06-19 22:11:55.105153131 +0200
+@@ -6,12 +6,13 @@
+ * This file is released under the GPLv2.
+ */
+
+-#include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/device.h>
+ #include <linux/export.h>
+ #include <linux/slab.h>
+ #include <linux/pm_clock.h>
++#include <linux/acpi.h>
++#include <linux/pm_domain.h>
+
+ /**
+ * dev_pm_get_subsys_data - Create or refcount power.subsys_data for device.
+@@ -83,3 +84,53 @@
+ return ret;
+ }
+ EXPORT_SYMBOL_GPL(dev_pm_put_subsys_data);
++
++/**
++ * dev_pm_domain_attach - Attach a device to its PM domain.
++ * @dev: Device to attach.
++ * @power_on: Used to indicate whether we should power on the device.
++ *
++ * The @dev may only be attached to a single PM domain. By iterating through
++ * the available alternatives we try to find a valid PM domain for the device.
++ * As attachment succeeds, the ->detach() callback in the struct dev_pm_domain
++ * should be assigned by the corresponding attach function.
++ *
++ * This function should typically be invoked from subsystem level code during
++ * the probe phase. Especially for those that holds devices which requires
++ * power management through PM domains.
++ *
++ * Callers must ensure proper synchronization of this function with power
++ * management callbacks.
++ *
++ * Returns 0 on successfully attached PM domain or negative error code.
++ */
++int dev_pm_domain_attach(struct device *dev, bool power_on)
++{
++ int ret;
++
++ ret = acpi_dev_pm_attach(dev, power_on);
++ if (ret)
++ ret = genpd_dev_pm_attach(dev);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(dev_pm_domain_attach);
++
++/**
++ * dev_pm_domain_detach - Detach a device from its PM domain.
++ * @dev: Device to attach.
++ * @power_off: Used to indicate whether we should power off the device.
++ *
++ * This functions will reverse the actions from dev_pm_domain_attach() and thus
++ * try to detach the @dev from its PM domain. Typically it should be invoked
++ * from subsystem level code during the remove phase.
++ *
++ * Callers must ensure proper synchronization of this function with power
++ * management callbacks.
++ */
++void dev_pm_domain_detach(struct device *dev, bool power_off)
++{
++ if (dev->pm_domain && dev->pm_domain->detach)
++ dev->pm_domain->detach(dev, power_off);
++}
++EXPORT_SYMBOL_GPL(dev_pm_domain_detach);
+diff -Nur linux-3.14.72.orig/drivers/base/power/domain.c linux-3.14.72/drivers/base/power/domain.c
+--- linux-3.14.72.orig/drivers/base/power/domain.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/power/domain.c 2016-06-19 22:11:55.105153131 +0200
+@@ -6,9 +6,9 @@
+ * This file is released under the GPLv2.
+ */
+
+-#include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/io.h>
++#include <linux/platform_device.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/pm_domain.h>
+ #include <linux/pm_qos.h>
+@@ -26,10 +26,6 @@
+ __routine = genpd->dev_ops.callback; \
+ if (__routine) { \
+ __ret = __routine(dev); \
+- } else { \
+- __routine = dev_gpd_data(dev)->ops.callback; \
+- if (__routine) \
+- __ret = __routine(dev); \
+ } \
+ __ret; \
+ })
+@@ -42,7 +38,7 @@
+ struct gpd_timing_data *__td = &dev_gpd_data(dev)->td; \
+ if (!__retval && __elapsed > __td->field) { \
+ __td->field = __elapsed; \
+- dev_warn(dev, name " latency exceeded, new value %lld ns\n", \
++ dev_dbg(dev, name " latency exceeded, new value %lld ns\n", \
+ __elapsed); \
+ genpd->max_off_time_changed = true; \
+ __td->constraint_changed = true; \
+@@ -71,8 +67,6 @@
+ return genpd;
+ }
+
+-#ifdef CONFIG_PM
+-
+ struct generic_pm_domain *dev_to_genpd(struct device *dev)
+ {
+ if (IS_ERR_OR_NULL(dev->pm_domain))
+@@ -286,8 +280,6 @@
+ return genpd ? pm_genpd_poweron(genpd) : -EINVAL;
+ }
+
+-#endif /* CONFIG_PM */
+-
+ #ifdef CONFIG_PM_RUNTIME
+
+ static int genpd_start_dev_no_timing(struct generic_pm_domain *genpd,
+@@ -431,7 +423,7 @@
+ * Queue up the execution of pm_genpd_poweroff() unless it's already been done
+ * before.
+ */
+-void genpd_queue_power_off_work(struct generic_pm_domain *genpd)
++static void genpd_queue_power_off_work(struct generic_pm_domain *genpd)
+ {
+ queue_work(pm_wq, &genpd->power_off_work);
+ }
+@@ -620,8 +612,6 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- might_sleep_if(!genpd->dev_irq_safe);
+-
+ stop_ok = genpd->gov ? genpd->gov->stop_ok : NULL;
+ if (stop_ok && !stop_ok(dev))
+ return -EBUSY;
+@@ -666,8 +656,6 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- might_sleep_if(!genpd->dev_irq_safe);
+-
+ /* If power.irq_safe, the PM domain is never powered off. */
+ if (dev->power.irq_safe)
+ return genpd_start_dev_no_timing(genpd, dev);
+@@ -706,6 +694,14 @@
+ return 0;
+ }
+
++static bool pd_ignore_unused;
++static int __init pd_ignore_unused_setup(char *__unused)
++{
++ pd_ignore_unused = true;
++ return 1;
++}
++__setup("pd_ignore_unused", pd_ignore_unused_setup);
++
+ /**
+ * pm_genpd_poweroff_unused - Power off all PM domains with no devices in use.
+ */
+@@ -713,6 +709,11 @@
+ {
+ struct generic_pm_domain *genpd;
+
++ if (pd_ignore_unused) {
++ pr_warn("genpd: Not disabling unused power domains\n");
++ return;
++ }
++
+ mutex_lock(&gpd_list_lock);
+
+ list_for_each_entry(genpd, &gpd_list, gpd_list_node)
+@@ -721,6 +722,13 @@
+ mutex_unlock(&gpd_list_lock);
+ }
+
++static int __init genpd_poweroff_unused(void)
++{
++ pm_genpd_poweroff_unused();
++ return 0;
++}
++late_initcall(genpd_poweroff_unused);
++
+ #else
+
+ static inline int genpd_dev_pm_qos_notifier(struct notifier_block *nb,
+@@ -729,6 +737,9 @@
+ return NOTIFY_DONE;
+ }
+
++static inline void
++genpd_queue_power_off_work(struct generic_pm_domain *genpd) {}
++
+ static inline void genpd_power_off_work_fn(struct work_struct *work) {}
+
+ #define pm_genpd_runtime_suspend NULL
+@@ -762,46 +773,6 @@
+ return GENPD_DEV_CALLBACK(genpd, bool, active_wakeup, dev);
+ }
+
+-static int genpd_suspend_dev(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, suspend, dev);
+-}
+-
+-static int genpd_suspend_late(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, suspend_late, dev);
+-}
+-
+-static int genpd_resume_early(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, resume_early, dev);
+-}
+-
+-static int genpd_resume_dev(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, resume, dev);
+-}
+-
+-static int genpd_freeze_dev(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, freeze, dev);
+-}
+-
+-static int genpd_freeze_late(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, freeze_late, dev);
+-}
+-
+-static int genpd_thaw_early(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, thaw_early, dev);
+-}
+-
+-static int genpd_thaw_dev(struct generic_pm_domain *genpd, struct device *dev)
+-{
+- return GENPD_DEV_CALLBACK(genpd, int, thaw, dev);
+-}
+-
+ /**
+ * pm_genpd_sync_poweroff - Synchronously power off a PM domain and its masters.
+ * @genpd: PM domain to power off, if possible.
+@@ -983,7 +954,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_suspend_dev(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_suspend(dev);
+ }
+
+ /**
+@@ -1004,7 +975,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_suspend_late(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_suspend_late(dev);
+ }
+
+ /**
+@@ -1028,6 +999,8 @@
+ || (dev->power.wakeup_path && genpd_dev_active_wakeup(genpd, dev)))
+ return 0;
+
++ pm_generic_suspend_noirq(dev);
++
+ genpd_stop_dev(genpd, dev);
+
+ /*
+@@ -1050,6 +1023,7 @@
+ static int pm_genpd_resume_noirq(struct device *dev)
+ {
+ struct generic_pm_domain *genpd;
++ int ret;
+
+ dev_dbg(dev, "%s()\n", __func__);
+
+@@ -1069,7 +1043,11 @@
+ pm_genpd_sync_poweron(genpd);
+ genpd->suspended_count--;
+
+- return genpd_start_dev(genpd, dev);
++ ret = genpd_start_dev(genpd, dev);
++
++ pm_generic_resume_noirq(dev);
++
++ return ret;
+ }
+
+ /**
+@@ -1091,7 +1069,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_resume_early(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_resume_early(dev);
+ }
+
+ /**
+@@ -1112,7 +1090,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_resume_dev(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_resume(dev);
+ }
+
+ /**
+@@ -1133,7 +1111,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_freeze_dev(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_freeze(dev);
+ }
+
+ /**
+@@ -1155,7 +1133,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_freeze_late(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_freeze_late(dev);
+ }
+
+ /**
+@@ -1219,7 +1197,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_thaw_early(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_thaw_early(dev);
+ }
+
+ /**
+@@ -1240,7 +1218,7 @@
+ if (IS_ERR(genpd))
+ return -EINVAL;
+
+- return genpd->suspend_power_off ? 0 : genpd_thaw_dev(genpd, dev);
++ return genpd->suspend_power_off ? 0 : pm_generic_thaw(dev);
+ }
+
+ /**
+@@ -1332,13 +1310,13 @@
+ }
+
+ /**
+- * pm_genpd_syscore_switch - Switch power during system core suspend or resume.
++ * genpd_syscore_switch - Switch power during system core suspend or resume.
+ * @dev: Device that normally is marked as "always on" to switch power for.
+ *
+ * This routine may only be called during the system core (syscore) suspend or
+ * resume phase for devices whose "always on" flags are set.
+ */
+-void pm_genpd_syscore_switch(struct device *dev, bool suspend)
++static void genpd_syscore_switch(struct device *dev, bool suspend)
+ {
+ struct generic_pm_domain *genpd;
+
+@@ -1354,7 +1332,18 @@
+ genpd->suspended_count--;
+ }
+ }
+-EXPORT_SYMBOL_GPL(pm_genpd_syscore_switch);
++
++void pm_genpd_syscore_poweroff(struct device *dev)
++{
++ genpd_syscore_switch(dev, true);
++}
++EXPORT_SYMBOL_GPL(pm_genpd_syscore_poweroff);
++
++void pm_genpd_syscore_poweron(struct device *dev)
++{
++ genpd_syscore_switch(dev, false);
++}
++EXPORT_SYMBOL_GPL(pm_genpd_syscore_poweron);
+
+ #else
+
+@@ -1732,112 +1721,6 @@
+ }
+
+ /**
+- * pm_genpd_add_callbacks - Add PM domain callbacks to a given device.
+- * @dev: Device to add the callbacks to.
+- * @ops: Set of callbacks to add.
+- * @td: Timing data to add to the device along with the callbacks (optional).
+- *
+- * Every call to this routine should be balanced with a call to
+- * __pm_genpd_remove_callbacks() and they must not be nested.
+- */
+-int pm_genpd_add_callbacks(struct device *dev, struct gpd_dev_ops *ops,
+- struct gpd_timing_data *td)
+-{
+- struct generic_pm_domain_data *gpd_data_new, *gpd_data = NULL;
+- int ret = 0;
+-
+- if (!(dev && ops))
+- return -EINVAL;
+-
+- gpd_data_new = __pm_genpd_alloc_dev_data(dev);
+- if (!gpd_data_new)
+- return -ENOMEM;
+-
+- pm_runtime_disable(dev);
+- device_pm_lock();
+-
+- ret = dev_pm_get_subsys_data(dev);
+- if (ret)
+- goto out;
+-
+- spin_lock_irq(&dev->power.lock);
+-
+- if (dev->power.subsys_data->domain_data) {
+- gpd_data = to_gpd_data(dev->power.subsys_data->domain_data);
+- } else {
+- gpd_data = gpd_data_new;
+- dev->power.subsys_data->domain_data = &gpd_data->base;
+- }
+- gpd_data->refcount++;
+- gpd_data->ops = *ops;
+- if (td)
+- gpd_data->td = *td;
+-
+- spin_unlock_irq(&dev->power.lock);
+-
+- out:
+- device_pm_unlock();
+- pm_runtime_enable(dev);
+-
+- if (gpd_data != gpd_data_new)
+- __pm_genpd_free_dev_data(dev, gpd_data_new);
+-
+- return ret;
+-}
+-EXPORT_SYMBOL_GPL(pm_genpd_add_callbacks);
+-
+-/**
+- * __pm_genpd_remove_callbacks - Remove PM domain callbacks from a given device.
+- * @dev: Device to remove the callbacks from.
+- * @clear_td: If set, clear the device's timing data too.
+- *
+- * This routine can only be called after pm_genpd_add_callbacks().
+- */
+-int __pm_genpd_remove_callbacks(struct device *dev, bool clear_td)
+-{
+- struct generic_pm_domain_data *gpd_data = NULL;
+- bool remove = false;
+- int ret = 0;
+-
+- if (!(dev && dev->power.subsys_data))
+- return -EINVAL;
+-
+- pm_runtime_disable(dev);
+- device_pm_lock();
+-
+- spin_lock_irq(&dev->power.lock);
+-
+- if (dev->power.subsys_data->domain_data) {
+- gpd_data = to_gpd_data(dev->power.subsys_data->domain_data);
+- gpd_data->ops = (struct gpd_dev_ops){ NULL };
+- if (clear_td)
+- gpd_data->td = (struct gpd_timing_data){ 0 };
+-
+- if (--gpd_data->refcount == 0) {
+- dev->power.subsys_data->domain_data = NULL;
+- remove = true;
+- }
+- } else {
+- ret = -EINVAL;
+- }
+-
+- spin_unlock_irq(&dev->power.lock);
+-
+- device_pm_unlock();
+- pm_runtime_enable(dev);
+-
+- if (ret)
+- return ret;
+-
+- dev_pm_put_subsys_data(dev);
+- if (remove)
+- __pm_genpd_free_dev_data(dev, gpd_data);
+-
+- return 0;
+-}
+-EXPORT_SYMBOL_GPL(__pm_genpd_remove_callbacks);
+-
+-/**
+ * pm_genpd_attach_cpuidle - Connect the given PM domain with cpuidle.
+ * @genpd: PM domain to be connected with cpuidle.
+ * @state: cpuidle state this domain can disable/enable.
+@@ -1958,17 +1841,13 @@
+ /* Default device callbacks for generic PM domains. */
+
+ /**
+- * pm_genpd_default_save_state - Default "save device state" for PM domians.
++ * pm_genpd_default_save_state - Default "save device state" for PM domains.
+ * @dev: Device to handle.
+ */
+ static int pm_genpd_default_save_state(struct device *dev)
+ {
+ int (*cb)(struct device *__dev);
+
+- cb = dev_gpd_data(dev)->ops.save_state;
+- if (cb)
+- return cb(dev);
+-
+ if (dev->type && dev->type->pm)
+ cb = dev->type->pm->runtime_suspend;
+ else if (dev->class && dev->class->pm)
+@@ -1985,17 +1864,13 @@
+ }
+
+ /**
+- * pm_genpd_default_restore_state - Default PM domians "restore device state".
++ * pm_genpd_default_restore_state - Default PM domains "restore device state".
+ * @dev: Device to handle.
+ */
+ static int pm_genpd_default_restore_state(struct device *dev)
+ {
+ int (*cb)(struct device *__dev);
+
+- cb = dev_gpd_data(dev)->ops.restore_state;
+- if (cb)
+- return cb(dev);
+-
+ if (dev->type && dev->type->pm)
+ cb = dev->type->pm->runtime_resume;
+ else if (dev->class && dev->class->pm)
+@@ -2011,109 +1886,6 @@
+ return cb ? cb(dev) : 0;
+ }
+
+-#ifdef CONFIG_PM_SLEEP
+-
+-/**
+- * pm_genpd_default_suspend - Default "device suspend" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_suspend(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.suspend;
+-
+- return cb ? cb(dev) : pm_generic_suspend(dev);
+-}
+-
+-/**
+- * pm_genpd_default_suspend_late - Default "late device suspend" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_suspend_late(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.suspend_late;
+-
+- return cb ? cb(dev) : pm_generic_suspend_late(dev);
+-}
+-
+-/**
+- * pm_genpd_default_resume_early - Default "early device resume" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_resume_early(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.resume_early;
+-
+- return cb ? cb(dev) : pm_generic_resume_early(dev);
+-}
+-
+-/**
+- * pm_genpd_default_resume - Default "device resume" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_resume(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.resume;
+-
+- return cb ? cb(dev) : pm_generic_resume(dev);
+-}
+-
+-/**
+- * pm_genpd_default_freeze - Default "device freeze" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_freeze(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.freeze;
+-
+- return cb ? cb(dev) : pm_generic_freeze(dev);
+-}
+-
+-/**
+- * pm_genpd_default_freeze_late - Default "late device freeze" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_freeze_late(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.freeze_late;
+-
+- return cb ? cb(dev) : pm_generic_freeze_late(dev);
+-}
+-
+-/**
+- * pm_genpd_default_thaw_early - Default "early device thaw" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_thaw_early(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.thaw_early;
+-
+- return cb ? cb(dev) : pm_generic_thaw_early(dev);
+-}
+-
+-/**
+- * pm_genpd_default_thaw - Default "device thaw" for PM domians.
+- * @dev: Device to handle.
+- */
+-static int pm_genpd_default_thaw(struct device *dev)
+-{
+- int (*cb)(struct device *__dev) = dev_gpd_data(dev)->ops.thaw;
+-
+- return cb ? cb(dev) : pm_generic_thaw(dev);
+-}
+-
+-#else /* !CONFIG_PM_SLEEP */
+-
+-#define pm_genpd_default_suspend NULL
+-#define pm_genpd_default_suspend_late NULL
+-#define pm_genpd_default_resume_early NULL
+-#define pm_genpd_default_resume NULL
+-#define pm_genpd_default_freeze NULL
+-#define pm_genpd_default_freeze_late NULL
+-#define pm_genpd_default_thaw_early NULL
+-#define pm_genpd_default_thaw NULL
+-
+-#endif /* !CONFIG_PM_SLEEP */
+-
+ /**
+ * pm_genpd_init - Initialize a generic I/O PM domain object.
+ * @genpd: PM domain object to initialize.
+@@ -2165,15 +1937,295 @@
+ genpd->domain.ops.complete = pm_genpd_complete;
+ genpd->dev_ops.save_state = pm_genpd_default_save_state;
+ genpd->dev_ops.restore_state = pm_genpd_default_restore_state;
+- genpd->dev_ops.suspend = pm_genpd_default_suspend;
+- genpd->dev_ops.suspend_late = pm_genpd_default_suspend_late;
+- genpd->dev_ops.resume_early = pm_genpd_default_resume_early;
+- genpd->dev_ops.resume = pm_genpd_default_resume;
+- genpd->dev_ops.freeze = pm_genpd_default_freeze;
+- genpd->dev_ops.freeze_late = pm_genpd_default_freeze_late;
+- genpd->dev_ops.thaw_early = pm_genpd_default_thaw_early;
+- genpd->dev_ops.thaw = pm_genpd_default_thaw;
+ mutex_lock(&gpd_list_lock);
+ list_add(&genpd->gpd_list_node, &gpd_list);
+ mutex_unlock(&gpd_list_lock);
+ }
++
++#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
++/*
++ * Device Tree based PM domain providers.
++ *
++ * The code below implements generic device tree based PM domain providers that
++ * bind device tree nodes with generic PM domains registered in the system.
++ *
++ * Any driver that registers generic PM domains and needs to support binding of
++ * devices to these domains is supposed to register a PM domain provider, which
++ * maps a PM domain specifier retrieved from the device tree to a PM domain.
++ *
++ * Two simple mapping functions have been provided for convenience:
++ * - __of_genpd_xlate_simple() for 1:1 device tree node to PM domain mapping.
++ * - __of_genpd_xlate_onecell() for mapping of multiple PM domains per node by
++ * index.
++ */
++
++/**
++ * struct of_genpd_provider - PM domain provider registration structure
++ * @link: Entry in global list of PM domain providers
++ * @node: Pointer to device tree node of PM domain provider
++ * @xlate: Provider-specific xlate callback mapping a set of specifier cells
++ * into a PM domain.
++ * @data: context pointer to be passed into @xlate callback
++ */
++struct of_genpd_provider {
++ struct list_head link;
++ struct device_node *node;
++ genpd_xlate_t xlate;
++ void *data;
++};
++
++/* List of registered PM domain providers. */
++static LIST_HEAD(of_genpd_providers);
++/* Mutex to protect the list above. */
++static DEFINE_MUTEX(of_genpd_mutex);
++
++/**
++ * __of_genpd_xlate_simple() - Xlate function for direct node-domain mapping
++ * @genpdspec: OF phandle args to map into a PM domain
++ * @data: xlate function private data - pointer to struct generic_pm_domain
++ *
++ * This is a generic xlate function that can be used to model PM domains that
++ * have their own device tree nodes. The private data of xlate function needs
++ * to be a valid pointer to struct generic_pm_domain.
++ */
++struct generic_pm_domain *__of_genpd_xlate_simple(
++ struct of_phandle_args *genpdspec,
++ void *data)
++{
++ if (genpdspec->args_count != 0)
++ return ERR_PTR(-EINVAL);
++ return data;
++}
++EXPORT_SYMBOL_GPL(__of_genpd_xlate_simple);
++
++/**
++ * __of_genpd_xlate_onecell() - Xlate function using a single index.
++ * @genpdspec: OF phandle args to map into a PM domain
++ * @data: xlate function private data - pointer to struct genpd_onecell_data
++ *
++ * This is a generic xlate function that can be used to model simple PM domain
++ * controllers that have one device tree node and provide multiple PM domains.
++ * A single cell is used as an index into an array of PM domains specified in
++ * the genpd_onecell_data struct when registering the provider.
++ */
++struct generic_pm_domain *__of_genpd_xlate_onecell(
++ struct of_phandle_args *genpdspec,
++ void *data)
++{
++ struct genpd_onecell_data *genpd_data = data;
++ unsigned int idx = genpdspec->args[0];
++
++ if (genpdspec->args_count != 1)
++ return ERR_PTR(-EINVAL);
++
++ if (idx >= genpd_data->num_domains) {
++ pr_err("%s: invalid domain index %u\n", __func__, idx);
++ return ERR_PTR(-EINVAL);
++ }
++
++ if (!genpd_data->domains[idx])
++ return ERR_PTR(-ENOENT);
++
++ return genpd_data->domains[idx];
++}
++EXPORT_SYMBOL_GPL(__of_genpd_xlate_onecell);
++
++/**
++ * __of_genpd_add_provider() - Register a PM domain provider for a node
++ * @np: Device node pointer associated with the PM domain provider.
++ * @xlate: Callback for decoding PM domain from phandle arguments.
++ * @data: Context pointer for @xlate callback.
++ */
++int __of_genpd_add_provider(struct device_node *np, genpd_xlate_t xlate,
++ void *data)
++{
++ struct of_genpd_provider *cp;
++
++ cp = kzalloc(sizeof(*cp), GFP_KERNEL);
++ if (!cp)
++ return -ENOMEM;
++
++ cp->node = of_node_get(np);
++ cp->data = data;
++ cp->xlate = xlate;
++
++ mutex_lock(&of_genpd_mutex);
++ list_add(&cp->link, &of_genpd_providers);
++ mutex_unlock(&of_genpd_mutex);
++ pr_debug("Added domain provider from %s\n", np->full_name);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(__of_genpd_add_provider);
++
++/**
++ * of_genpd_del_provider() - Remove a previously registered PM domain provider
++ * @np: Device node pointer associated with the PM domain provider
++ */
++void of_genpd_del_provider(struct device_node *np)
++{
++ struct of_genpd_provider *cp;
++
++ mutex_lock(&of_genpd_mutex);
++ list_for_each_entry(cp, &of_genpd_providers, link) {
++ if (cp->node == np) {
++ list_del(&cp->link);
++ of_node_put(cp->node);
++ kfree(cp);
++ break;
++ }
++ }
++ mutex_unlock(&of_genpd_mutex);
++}
++EXPORT_SYMBOL_GPL(of_genpd_del_provider);
++
++/**
++ * of_genpd_get_from_provider() - Look-up PM domain
++ * @genpdspec: OF phandle args to use for look-up
++ *
++ * Looks for a PM domain provider under the node specified by @genpdspec and if
++ * found, uses xlate function of the provider to map phandle args to a PM
++ * domain.
++ *
++ * Returns a valid pointer to struct generic_pm_domain on success or ERR_PTR()
++ * on failure.
++ */
++static struct generic_pm_domain *of_genpd_get_from_provider(
++ struct of_phandle_args *genpdspec)
++{
++ struct generic_pm_domain *genpd = ERR_PTR(-ENOENT);
++ struct of_genpd_provider *provider;
++
++ mutex_lock(&of_genpd_mutex);
++
++ /* Check if we have such a provider in our array */
++ list_for_each_entry(provider, &of_genpd_providers, link) {
++ if (provider->node == genpdspec->np)
++ genpd = provider->xlate(genpdspec, provider->data);
++ if (!IS_ERR(genpd))
++ break;
++ }
++
++ mutex_unlock(&of_genpd_mutex);
++
++ return genpd;
++}
++
++/**
++ * genpd_dev_pm_detach - Detach a device from its PM domain.
++ * @dev: Device to attach.
++ * @power_off: Currently not used
++ *
++ * Try to locate a corresponding generic PM domain, which the device was
++ * attached to previously. If such is found, the device is detached from it.
++ */
++static void genpd_dev_pm_detach(struct device *dev, bool power_off)
++{
++ struct generic_pm_domain *pd = NULL, *gpd;
++ int ret = 0;
++
++ if (!dev->pm_domain)
++ return;
++
++ mutex_lock(&gpd_list_lock);
++ list_for_each_entry(gpd, &gpd_list, gpd_list_node) {
++ if (&gpd->domain == dev->pm_domain) {
++ pd = gpd;
++ break;
++ }
++ }
++ mutex_unlock(&gpd_list_lock);
++
++ if (!pd)
++ return;
++
++ dev_dbg(dev, "removing from PM domain %s\n", pd->name);
++
++ while (1) {
++ ret = pm_genpd_remove_device(pd, dev);
++ if (ret != -EAGAIN)
++ break;
++ cond_resched();
++ }
++
++ if (ret < 0) {
++ dev_err(dev, "failed to remove from PM domain %s: %d",
++ pd->name, ret);
++ return;
++ }
++
++ /* Check if PM domain can be powered off after removing this device. */
++ genpd_queue_power_off_work(pd);
++}
++
++/**
++ * genpd_dev_pm_attach - Attach a device to its PM domain using DT.
++ * @dev: Device to attach.
++ *
++ * Parse device's OF node to find a PM domain specifier. If such is found,
++ * attaches the device to retrieved pm_domain ops.
++ *
++ * Both generic and legacy Samsung-specific DT bindings are supported to keep
++ * backwards compatibility with existing DTBs.
++ *
++ * Returns 0 on successfully attached PM domain or negative error code.
++ */
++int genpd_dev_pm_attach(struct device *dev)
++{
++ struct of_phandle_args pd_args;
++ struct generic_pm_domain *pd;
++ int ret;
++
++ if (!dev->of_node)
++ return -ENODEV;
++
++ if (dev->pm_domain)
++ return -EEXIST;
++
++ ret = of_parse_phandle_with_args(dev->of_node, "power-domains",
++ "#power-domain-cells", 0, &pd_args);
++ if (ret < 0) {
++ if (ret != -ENOENT)
++ return ret;
++
++ /*
++ * Try legacy Samsung-specific bindings
++ * (for backwards compatibility of DT ABI)
++ */
++ pd_args.args_count = 0;
++ pd_args.np = of_parse_phandle(dev->of_node,
++ "samsung,power-domain", 0);
++ if (!pd_args.np)
++ return -ENOENT;
++ }
++
++ pd = of_genpd_get_from_provider(&pd_args);
++ if (IS_ERR(pd)) {
++ dev_dbg(dev, "%s() failed to find PM domain: %ld\n",
++ __func__, PTR_ERR(pd));
++ of_node_put(dev->of_node);
++ return PTR_ERR(pd);
++ }
++
++ dev_dbg(dev, "adding to PM domain %s\n", pd->name);
++
++ while (1) {
++ ret = pm_genpd_add_device(pd, dev);
++ if (ret != -EAGAIN)
++ break;
++ cond_resched();
++ }
++
++ if (ret < 0) {
++ dev_err(dev, "failed to add to PM domain %s: %d",
++ pd->name, ret);
++ of_node_put(dev->of_node);
++ return ret;
++ }
++
++ dev->pm_domain->detach = genpd_dev_pm_detach;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(genpd_dev_pm_attach);
++#endif
+diff -Nur linux-3.14.72.orig/drivers/base/power/domain_governor.c linux-3.14.72/drivers/base/power/domain_governor.c
+--- linux-3.14.72.orig/drivers/base/power/domain_governor.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/power/domain_governor.c 2016-06-19 22:11:55.105153131 +0200
+@@ -6,7 +6,6 @@
+ * This file is released under the GPLv2.
+ */
+
+-#include <linux/init.h>
+ #include <linux/kernel.h>
+ #include <linux/pm_domain.h>
+ #include <linux/pm_qos.h>
+diff -Nur linux-3.14.72.orig/drivers/base/power/opp.c linux-3.14.72/drivers/base/power/opp.c
+--- linux-3.14.72.orig/drivers/base/power/opp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/power/opp.c 2016-06-19 22:11:55.105153131 +0200
+@@ -14,7 +14,6 @@
+ #include <linux/kernel.h>
+ #include <linux/errno.h>
+ #include <linux/err.h>
+-#include <linux/init.h>
+ #include <linux/slab.h>
+ #include <linux/cpufreq.h>
+ #include <linux/device.h>
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/Kconfig linux-3.14.72/drivers/base/regmap/Kconfig
+--- linux-3.14.72.orig/drivers/base/regmap/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/regmap/Kconfig 2016-06-19 22:11:55.105153131 +0200
+@@ -3,11 +3,14 @@
+ # subsystems should select the appropriate symbols.
+
+ config REGMAP
+- default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_MMIO || REGMAP_IRQ)
++ default y if (REGMAP_I2C || REGMAP_SPI || REGMAP_SPMI || REGMAP_MMIO || REGMAP_IRQ || REGMAP_AC97)
+ select LZO_COMPRESS
+ select LZO_DECOMPRESS
+ select IRQ_DOMAIN if REGMAP_IRQ
+ bool
++
++config REGMAP_AC97
++ tristate
+
+ config REGMAP_I2C
+ tristate
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/Makefile linux-3.14.72/drivers/base/regmap/Makefile
+--- linux-3.14.72.orig/drivers/base/regmap/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/regmap/Makefile 2016-06-19 22:11:55.105153131 +0200
+@@ -6,3 +6,4 @@
+ obj-$(CONFIG_REGMAP_SPMI) += regmap-spmi.o
+ obj-$(CONFIG_REGMAP_MMIO) += regmap-mmio.o
+ obj-$(CONFIG_REGMAP_IRQ) += regmap-irq.o
++obj-$(CONFIG_REGMAP_AC97) += regmap-ac97.o
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/regcache.c linux-3.14.72/drivers/base/regmap/regcache.c
+--- linux-3.14.72.orig/drivers/base/regmap/regcache.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/regmap/regcache.c 2016-06-19 22:11:55.109152867 +0200
+@@ -636,10 +636,10 @@
+ if (*data == NULL)
+ return 0;
+
+- count = cur - base;
++ count = (cur - base) / map->reg_stride;
+
+ dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
+- count * val_bytes, count, base, cur - 1);
++ count * val_bytes, count, base, cur - map->reg_stride);
+
+ map->cache_bypass = 1;
+
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/regmap-ac97.c linux-3.14.72/drivers/base/regmap/regmap-ac97.c
+--- linux-3.14.72.orig/drivers/base/regmap/regmap-ac97.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/base/regmap/regmap-ac97.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,113 @@
++/*
++ * Register map access API - AC'97 support
++ *
++ * Copyright 2013 Linaro Ltd. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms and conditions of the GNU General Public License,
++ * version 2, as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
++ * more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++
++#include <sound/ac97_codec.h>
++
++bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case AC97_RESET:
++ case AC97_POWERDOWN:
++ case AC97_INT_PAGING:
++ case AC97_EXTENDED_ID:
++ case AC97_EXTENDED_STATUS:
++ case AC97_EXTENDED_MID:
++ case AC97_EXTENDED_MSTATUS:
++ case AC97_GPIO_STATUS:
++ case AC97_MISC_AFE:
++ case AC97_VENDOR_ID1:
++ case AC97_VENDOR_ID2:
++ case AC97_CODEC_CLASS_REV:
++ case AC97_PCI_SVID:
++ case AC97_PCI_SID:
++ case AC97_FUNC_SELECT:
++ case AC97_FUNC_INFO:
++ case AC97_SENSE_INFO:
++ return true;
++ default:
++ return false;
++ }
++}
++EXPORT_SYMBOL_GPL(regmap_ac97_default_volatile);
++
++static int regmap_ac97_reg_read(void *context, unsigned int reg,
++ unsigned int *val)
++{
++ struct snd_ac97 *ac97 = context;
++ *val = ac97->bus->ops->read(ac97, reg);
++
++ return 0;
++}
++
++static int regmap_ac97_reg_write(void *context, unsigned int reg,
++ unsigned int val)
++{
++ struct snd_ac97 *ac97 = context;
++
++ ac97->bus->ops->write(ac97, reg, val);
++
++ return 0;
++}
++
++static const struct regmap_bus ac97_regmap_bus = {
++ .reg_write = regmap_ac97_reg_write,
++ .reg_read = regmap_ac97_reg_read,
++};
++
++/**
++ * regmap_init_ac97(): Initialise AC'97 register map
++ *
++ * @ac97: Device that will be interacted with
++ * @config: Configuration for register map
++ *
++ * The return value will be an ERR_PTR() on error or a valid pointer to
++ * a struct regmap.
++ */
++struct regmap *regmap_init_ac97(struct snd_ac97 *ac97,
++ const struct regmap_config *config)
++{
++ return regmap_init(&ac97->dev, &ac97_regmap_bus, ac97, config);
++}
++EXPORT_SYMBOL_GPL(regmap_init_ac97);
++
++/**
++ * devm_regmap_init_ac97(): Initialise AC'97 register map
++ *
++ * @ac97: Device that will be interacted with
++ * @config: Configuration for register map
++ *
++ * The return value will be an ERR_PTR() on error or a valid pointer
++ * to a struct regmap. The regmap will be automatically freed by the
++ * device management code.
++ */
++struct regmap *devm_regmap_init_ac97(struct snd_ac97 *ac97,
++ const struct regmap_config *config)
++{
++ return devm_regmap_init(&ac97->dev, &ac97_regmap_bus, ac97, config);
++}
++EXPORT_SYMBOL_GPL(devm_regmap_init_ac97);
++
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/regmap.c linux-3.14.72/drivers/base/regmap/regmap.c
+--- linux-3.14.72.orig/drivers/base/regmap/regmap.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/regmap/regmap.c 2016-06-19 22:11:55.109152867 +0200
+@@ -35,10 +35,14 @@
+ unsigned int mask, unsigned int val,
+ bool *change);
+
++static int _regmap_bus_reg_read(void *context, unsigned int reg,
++ unsigned int *val);
+ static int _regmap_bus_read(void *context, unsigned int reg,
+ unsigned int *val);
+ static int _regmap_bus_formatted_write(void *context, unsigned int reg,
+ unsigned int val);
++static int _regmap_bus_reg_write(void *context, unsigned int reg,
++ unsigned int val);
+ static int _regmap_bus_raw_write(void *context, unsigned int reg,
+ unsigned int val);
+
+@@ -472,6 +476,11 @@
+
+ map->defer_caching = false;
+ goto skip_format_initialization;
++ } else if (!bus->read || !bus->write) {
++ map->reg_read = _regmap_bus_reg_read;
++ map->reg_write = _regmap_bus_reg_write;
++ map->defer_caching = false;
++ goto skip_format_initialization;
+ } else {
+ map->reg_read = _regmap_bus_read;
+ }
+@@ -1266,6 +1275,14 @@
+ return ret;
+ }
+
++static int _regmap_bus_reg_write(void *context, unsigned int reg,
++ unsigned int val)
++{
++ struct regmap *map = context;
++
++ return map->bus->reg_write(map->bus_context, reg, val);
++}
++
+ static int _regmap_bus_raw_write(void *context, unsigned int reg,
+ unsigned int val)
+ {
+@@ -1707,6 +1724,14 @@
+ return ret;
+ }
+
++static int _regmap_bus_reg_read(void *context, unsigned int reg,
++ unsigned int *val)
++{
++ struct regmap *map = context;
++
++ return map->bus->reg_read(map->bus_context, reg, val);
++}
++
+ static int _regmap_bus_read(void *context, unsigned int reg,
+ unsigned int *val)
+ {
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/regmap-i2c.c linux-3.14.72/drivers/base/regmap/regmap-i2c.c
+--- linux-3.14.72.orig/drivers/base/regmap/regmap-i2c.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/regmap/regmap-i2c.c 2016-06-19 22:11:55.109152867 +0200
+@@ -13,7 +13,6 @@
+ #include <linux/regmap.h>
+ #include <linux/i2c.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+
+ static int regmap_i2c_write(void *context, const void *data, size_t count)
+ {
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/regmap-mmio.c linux-3.14.72/drivers/base/regmap/regmap-mmio.c
+--- linux-3.14.72.orig/drivers/base/regmap/regmap-mmio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/regmap/regmap-mmio.c 2016-06-19 22:11:55.109152867 +0200
+@@ -18,7 +18,6 @@
+
+ #include <linux/clk.h>
+ #include <linux/err.h>
+-#include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+ #include <linux/regmap.h>
+@@ -211,19 +210,15 @@
+ ctx->val_bytes = config->val_bits / 8;
+ ctx->clk = ERR_PTR(-ENODEV);
+
+- if (clk_id == NULL)
+- return ctx;
+-
+ ctx->clk = clk_get(dev, clk_id);
+- if (IS_ERR(ctx->clk)) {
+- ret = PTR_ERR(ctx->clk);
+- goto err_free;
+- }
+-
+- ret = clk_prepare(ctx->clk);
+- if (ret < 0) {
+- clk_put(ctx->clk);
+- goto err_free;
++ if (!IS_ERR(ctx->clk)) {
++ ret = clk_prepare(ctx->clk);
++ if (ret < 0) {
++ clk_put(ctx->clk);
++ goto err_free;
++ }
++ } else {
++ ctx->clk = NULL;
+ }
+
+ return ctx;
+diff -Nur linux-3.14.72.orig/drivers/base/regmap/regmap-spi.c linux-3.14.72/drivers/base/regmap/regmap-spi.c
+--- linux-3.14.72.orig/drivers/base/regmap/regmap-spi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/regmap/regmap-spi.c 2016-06-19 22:11:55.109152867 +0200
+@@ -12,7 +12,6 @@
+
+ #include <linux/regmap.h>
+ #include <linux/spi/spi.h>
+-#include <linux/init.h>
+ #include <linux/module.h>
+
+ #include "internal.h"
+diff -Nur linux-3.14.72.orig/drivers/base/topology.c linux-3.14.72/drivers/base/topology.c
+--- linux-3.14.72.orig/drivers/base/topology.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/base/topology.c 2016-06-19 22:11:55.109152867 +0200
+@@ -23,7 +23,6 @@
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+-#include <linux/init.h>
+ #include <linux/mm.h>
+ #include <linux/cpu.h>
+ #include <linux/module.h>
+diff -Nur linux-3.14.72.orig/drivers/bcma/driver_pcie2.c linux-3.14.72/drivers/bcma/driver_pcie2.c
+--- linux-3.14.72.orig/drivers/bcma/driver_pcie2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/bcma/driver_pcie2.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,175 @@
++/*
++ * Broadcom specific AMBA
++ * PCIe Gen 2 Core
++ *
++ * Copyright 2014, Broadcom Corporation
++ * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
++ *
++ * Licensed under the GNU/GPL. See COPYING for details.
++ */
++
++#include "bcma_private.h"
++#include <linux/bcma/bcma.h>
++
++/**************************************************
++ * R/W ops.
++ **************************************************/
++
++#if 0
++static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
++ pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
++ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
++}
++#endif
++
++static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
++ u32 val)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
++}
++
++/**************************************************
++ * Init.
++ **************************************************/
++
++static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
++ bool enable)
++{
++ u32 val;
++
++ /* restore back to default */
++ val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
++ val |= PCIE2_CLKC_DLYPERST;
++ val &= ~PCIE2_CLKC_DISSPROMLD;
++ if (enable) {
++ val &= ~PCIE2_CLKC_DLYPERST;
++ val |= PCIE2_CLKC_DISSPROMLD;
++ }
++ pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
++ /* flush */
++ return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
++}
++
++static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
++{
++ /* LTR0 */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
++ /* LTR1 */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
++ /* LTR2 */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
++}
++
++static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
++{
++ u8 core_rev = pcie2->core->id.rev;
++ u32 devstsctr2;
++
++ if (core_rev < 2 || core_rev == 10 || core_rev > 13)
++ return;
++
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIE2_CAP_DEVSTSCTRL2_OFFSET);
++ devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
++ if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
++ /* force the right LTR values */
++ bcma_core_pcie2_set_ltr_vals(pcie2);
++
++ /* TODO:
++ si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
++
++ /* enable the LTR */
++ devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIE2_CAP_DEVSTSCTRL2_OFFSET);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
++
++ /* set the LTR state to be active */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
++ PCIE2_LTR_ACTIVE);
++ usleep_range(1000, 2000);
++
++ /* set the LTR state to be sleep */
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
++ PCIE2_LTR_SLEEP);
++ usleep_range(1000, 2000);
++ }
++}
++
++static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
++{
++ u8 core_rev = pcie2->core->id.rev;
++ bool pciewar160, pciewar162;
++
++ pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
++ pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
++ core_rev == 9 || core_rev == 11;
++
++ if (!pciewar160 && !pciewar162)
++ return;
++
++/* TODO */
++#if 0
++ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
++ PCIE_DISABLE_L1CLK_GATING);
++#if 0
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIEGEN2_COE_PVT_TL_CTRL_0);
++ pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
++ ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
++#endif
++#endif
++}
++
++static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
++ pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
++}
++
++static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
++{
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
++}
++
++static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
++{
++ struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
++ u8 core_rev = pcie2->core->id.rev;
++ u32 alp_khz, pm_value;
++
++ if (core_rev <= 13) {
++ alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
++ pm_value = (1000000 * 2) / alp_khz;
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
++ PCIE2_PVT_REG_PM_CLK_PERIOD);
++ pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
++ }
++}
++
++void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
++{
++ struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
++ u32 tmp;
++
++ tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
++ if ((tmp & 0xe) >> 1 == 2)
++ bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
++
++ /* TODO: Do we need pcie_reqsize? */
++
++ if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
++ bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
++ bcma_core_pcie2_hw_ltr_war(pcie2);
++ pciedev_crwlpciegen2(pcie2);
++ pciedev_reg_pm_clk_period(pcie2);
++ pciedev_crwlpciegen2_180(pcie2);
++ pciedev_crwlpciegen2_182(pcie2);
++}
+diff -Nur linux-3.14.72.orig/drivers/bcma/main.c linux-3.14.72/drivers/bcma/main.c
+--- linux-3.14.72.orig/drivers/bcma/main.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/bcma/main.c 2016-06-19 22:11:55.109152867 +0200
+@@ -132,6 +132,7 @@
+ case BCMA_CORE_CHIPCOMMON:
+ case BCMA_CORE_PCI:
+ case BCMA_CORE_PCIE:
++ case BCMA_CORE_PCIE2:
+ case BCMA_CORE_MIPS_74K:
+ case BCMA_CORE_4706_MAC_GBIT_COMMON:
+ continue;
+@@ -281,6 +282,13 @@
+ bcma_core_pci_init(&bus->drv_pci[1]);
+ }
+
++ /* Init PCIe Gen 2 core */
++ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
++ if (core) {
++ bus->drv_pcie2.core = core;
++ bcma_core_pcie2_init(&bus->drv_pcie2);
++ }
++
+ /* Init GBIT MAC COMMON core */
+ core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
+ if (core) {
+diff -Nur linux-3.14.72.orig/drivers/bcma/Makefile linux-3.14.72/drivers/bcma/Makefile
+--- linux-3.14.72.orig/drivers/bcma/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/bcma/Makefile 2016-06-19 22:11:55.109152867 +0200
+@@ -3,6 +3,7 @@
+ bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
+ bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
+ bcma-y += driver_pci.o
++bcma-y += driver_pcie2.o
+ bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
+ bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
+ bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
+diff -Nur linux-3.14.72.orig/drivers/char/fsl_otp.c linux-3.14.72/drivers/char/fsl_otp.c
+--- linux-3.14.72.orig/drivers/char/fsl_otp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/char/fsl_otp.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,316 @@
++/*
++ * Freescale On-Chip OTP driver
++ *
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/kobject.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/sysfs.h>
++#include <linux/fsl_otp.h>
++
++#define HW_OCOTP_CTRL 0x00000000
++#define HW_OCOTP_CTRL_SET 0x00000004
++#define BP_OCOTP_CTRL_WR_UNLOCK 16
++#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
++#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00000400
++#define BM_OCOTP_CTRL_ERROR 0x00000200
++#define BM_OCOTP_CTRL_BUSY 0x00000100
++#define BP_OCOTP_CTRL_ADDR 0
++#define BM_OCOTP_CTRL_ADDR 0x0000007F
++
++#define HW_OCOTP_TIMING 0x00000010
++#define BP_OCOTP_TIMING_STROBE_READ 16
++#define BM_OCOTP_TIMING_STROBE_READ 0x003F0000
++#define BP_OCOTP_TIMING_RELAX 12
++#define BM_OCOTP_TIMING_RELAX 0x0000F000
++#define BP_OCOTP_TIMING_STROBE_PROG 0
++#define BM_OCOTP_TIMING_STROBE_PROG 0x00000FFF
++
++#define HW_OCOTP_DATA 0x00000020
++
++#define HW_OCOTP_CUST_N(n) (0x00000400 + (n) * 0x10)
++#define BF(value, field) (((value) << BP_##field) & BM_##field)
++
++#define DEF_RELAX 20 /* > 16.5ns */
++
++#define BANK(a, b, c, d, e, f, g, h) { \
++ "HW_OCOTP_"#a, "HW_OCOTP_"#b, "HW_OCOTP_"#c, "HW_OCOTP_"#d, \
++ "HW_OCOTP_"#e, "HW_OCOTP_"#f, "HW_OCOTP_"#g, "HW_OCOTP_"#h, \
++}
++
++static const char *imx6q_otp_desc[16][8] = {
++ BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6),
++ BANK(MEM0, MEM1, MEM2, MEM3, MEM4, ANA0, ANA1, ANA2),
++ BANK(OTPMK0, OTPMK1, OTPMK2, OTPMK3, OTPMK4, OTPMK5, OTPMK6, OTPMK7),
++ BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7),
++ BANK(RESP0, HSJC_RESP1, MAC0, MAC1, HDCP_KSV0, HDCP_KSV1, GP1, GP2),
++ BANK(DTCP_KEY0, DTCP_KEY1, DTCP_KEY2, DTCP_KEY3, DTCP_KEY4, MISC_CONF, FIELD_RETURN, SRK_REVOKE),
++ BANK(HDCP_KEY0, HDCP_KEY1, HDCP_KEY2, HDCP_KEY3, HDCP_KEY4, HDCP_KEY5, HDCP_KEY6, HDCP_KEY7),
++ BANK(HDCP_KEY8, HDCP_KEY9, HDCP_KEY10, HDCP_KEY11, HDCP_KEY12, HDCP_KEY13, HDCP_KEY14, HDCP_KEY15),
++ BANK(HDCP_KEY16, HDCP_KEY17, HDCP_KEY18, HDCP_KEY19, HDCP_KEY20, HDCP_KEY21, HDCP_KEY22, HDCP_KEY23),
++ BANK(HDCP_KEY24, HDCP_KEY25, HDCP_KEY26, HDCP_KEY27, HDCP_KEY28, HDCP_KEY29, HDCP_KEY30, HDCP_KEY31),
++ BANK(HDCP_KEY32, HDCP_KEY33, HDCP_KEY34, HDCP_KEY35, HDCP_KEY36, HDCP_KEY37, HDCP_KEY38, HDCP_KEY39),
++ BANK(HDCP_KEY40, HDCP_KEY41, HDCP_KEY42, HDCP_KEY43, HDCP_KEY44, HDCP_KEY45, HDCP_KEY46, HDCP_KEY47),
++ BANK(HDCP_KEY48, HDCP_KEY49, HDCP_KEY50, HDCP_KEY51, HDCP_KEY52, HDCP_KEY53, HDCP_KEY54, HDCP_KEY55),
++ BANK(HDCP_KEY56, HDCP_KEY57, HDCP_KEY58, HDCP_KEY59, HDCP_KEY60, HDCP_KEY61, HDCP_KEY62, HDCP_KEY63),
++ BANK(HDCP_KEY64, HDCP_KEY65, HDCP_KEY66, HDCP_KEY67, HDCP_KEY68, HDCP_KEY69, HDCP_KEY70, HDCP_KEY71),
++ BANK(CRC0, CRC1, CRC2, CRC3, CRC4, CRC5, CRC6, CRC7),
++};
++
++static DEFINE_MUTEX(otp_mutex);
++static void __iomem *otp_base;
++static struct clk *otp_clk;
++struct kobject *otp_kobj;
++struct kobj_attribute *otp_kattr;
++struct attribute_group *otp_attr_group;
++
++static void set_otp_timing(void)
++{
++ unsigned long clk_rate = 0;
++ unsigned long strobe_read, relex, strobe_prog;
++ u32 timing = 0;
++
++ clk_rate = clk_get_rate(otp_clk);
++
++ /* do optimization for too many zeros */
++ relex = clk_rate / (1000000000 / DEF_RELAX) - 1;
++ strobe_prog = clk_rate / (1000000000 / 10000) + 2 * (DEF_RELAX + 1) - 1;
++ strobe_read = clk_rate / (1000000000 / 40) + 2 * (DEF_RELAX + 1) - 1;
++
++ timing = BF(relex, OCOTP_TIMING_RELAX);
++ timing |= BF(strobe_read, OCOTP_TIMING_STROBE_READ);
++ timing |= BF(strobe_prog, OCOTP_TIMING_STROBE_PROG);
++
++ __raw_writel(timing, otp_base + HW_OCOTP_TIMING);
++}
++
++static int otp_wait_busy(u32 flags)
++{
++ int count;
++ u32 c;
++
++ for (count = 10000; count >= 0; count--) {
++ c = __raw_readl(otp_base + HW_OCOTP_CTRL);
++ if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags)))
++ break;
++ cpu_relax();
++ }
++
++ if (count < 0)
++ return -ETIMEDOUT;
++
++ return 0;
++}
++
++int fsl_otp_readl(unsigned long offset, u32 *value)
++{
++ int ret = 0;
++
++ ret = clk_prepare_enable(otp_clk);
++ if (ret)
++ return ret;
++
++ mutex_lock(&otp_mutex);
++
++ set_otp_timing();
++ ret = otp_wait_busy(0);
++ if (ret)
++ goto out;
++
++ *value = __raw_readl(otp_base + offset);
++
++out:
++ mutex_unlock(&otp_mutex);
++ clk_disable_unprepare(otp_clk);
++ return ret;
++}
++EXPORT_SYMBOL(fsl_otp_readl);
++
++static ssize_t fsl_otp_show(struct kobject *kobj, struct kobj_attribute *attr,
++ char *buf)
++{
++ unsigned int index = attr - otp_kattr;
++ u32 value = 0;
++ int ret;
++
++ ret = fsl_otp_readl(HW_OCOTP_CUST_N(index), &value);
++
++ return ret ? 0 : sprintf(buf, "0x%x\n", value);
++}
++
++#ifdef CONFIG_FSL_OTP_WRITE_ENABLE
++static int otp_write_bits(int addr, u32 data, u32 magic)
++{
++ u32 c; /* for control register */
++
++ /* init the control register */
++ c = __raw_readl(otp_base + HW_OCOTP_CTRL);
++ c &= ~BM_OCOTP_CTRL_ADDR;
++ c |= BF(addr, OCOTP_CTRL_ADDR);
++ c |= BF(magic, OCOTP_CTRL_WR_UNLOCK);
++ __raw_writel(c, otp_base + HW_OCOTP_CTRL);
++
++ /* init the data register */
++ __raw_writel(data, otp_base + HW_OCOTP_DATA);
++ otp_wait_busy(0);
++
++ mdelay(2); /* Write Postamble */
++
++ return 0;
++}
++
++static ssize_t fsl_otp_store(struct kobject *kobj, struct kobj_attribute *attr,
++ const char *buf, size_t count)
++{
++ unsigned int index = attr - otp_kattr;
++ u32 value;
++ int ret;
++
++ sscanf(buf, "0x%x", &value);
++
++ ret = clk_prepare_enable(otp_clk);
++ if (ret)
++ return 0;
++
++ mutex_lock(&otp_mutex);
++
++ set_otp_timing();
++ ret = otp_wait_busy(0);
++ if (ret)
++ goto out;
++
++ otp_write_bits(index, value, 0x3e77);
++
++ /* Reload all the shadow registers */
++ __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS,
++ otp_base + HW_OCOTP_CTRL_SET);
++ udelay(1);
++ otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS);
++
++out:
++ mutex_unlock(&otp_mutex);
++ clk_disable_unprepare(otp_clk);
++ return ret ? 0 : count;
++}
++#endif
++
++static int fsl_otp_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ struct attribute **attrs;
++ const char **desc;
++ int i, num;
++ int ret;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ otp_base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(otp_base)) {
++ ret = PTR_ERR(otp_base);
++ dev_err(&pdev->dev, "failed to ioremap resource: %d\n", ret);
++ return ret;
++ }
++
++ otp_clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(otp_clk)) {
++ ret = PTR_ERR(otp_clk);
++ dev_err(&pdev->dev, "failed to get clock: %d\n", ret);
++ return ret;
++ }
++
++ desc = (const char **) imx6q_otp_desc;
++ num = sizeof(imx6q_otp_desc) / sizeof(void *);
++
++ /* The last one is NULL, which is used to detect the end */
++ attrs = devm_kzalloc(&pdev->dev, (num + 1) * sizeof(*attrs),
++ GFP_KERNEL);
++ otp_kattr = devm_kzalloc(&pdev->dev, num * sizeof(*otp_kattr),
++ GFP_KERNEL);
++ otp_attr_group = devm_kzalloc(&pdev->dev, sizeof(*otp_attr_group),
++ GFP_KERNEL);
++ if (!attrs || !otp_kattr || !otp_attr_group)
++ return -ENOMEM;
++
++ for (i = 0; i < num; i++) {
++ sysfs_attr_init(&otp_kattr[i].attr);
++ otp_kattr[i].attr.name = desc[i];
++#ifdef CONFIG_FSL_OTP_WRITE_ENABLE
++ otp_kattr[i].attr.mode = 0600;
++ otp_kattr[i].store = fsl_otp_store;
++#else
++ otp_kattr[i].attr.mode = 0400;
++#endif
++ otp_kattr[i].show = fsl_otp_show;
++ attrs[i] = &otp_kattr[i].attr;
++ }
++ otp_attr_group->attrs = attrs;
++
++ otp_kobj = kobject_create_and_add("fsl_otp", NULL);
++ if (!otp_kobj) {
++ dev_err(&pdev->dev, "failed to add kobject\n");
++ return -ENOMEM;
++ }
++
++ ret = sysfs_create_group(otp_kobj, otp_attr_group);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to create sysfs group: %d\n", ret);
++ kobject_put(otp_kobj);
++ return ret;
++ }
++
++ mutex_init(&otp_mutex);
++
++ return 0;
++}
++
++static int fsl_otp_remove(struct platform_device *pdev)
++{
++ sysfs_remove_group(otp_kobj, otp_attr_group);
++ kobject_put(otp_kobj);
++
++ return 0;
++}
++
++static const struct of_device_id fsl_otp_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ocotp", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_otp_dt_ids);
++
++static struct platform_driver fsl_otp_driver = {
++ .driver = {
++ .name = "imx-ocotp",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_otp_dt_ids,
++ },
++ .probe = fsl_otp_probe,
++ .remove = fsl_otp_remove,
++};
++module_platform_driver(fsl_otp_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Huang Shijie <b32955@freescale.com>");
++MODULE_DESCRIPTION("Freescale i.MX OCOTP driver");
+diff -Nur linux-3.14.72.orig/drivers/char/hw_random/imx-rng.c linux-3.14.72/drivers/char/hw_random/imx-rng.c
+--- linux-3.14.72.orig/drivers/char/hw_random/imx-rng.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/char/hw_random/imx-rng.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,440 @@
++/*
++ * RNG driver for Freescale RNG B/C
++ *
++ * Copyright (C) 2008-2015 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
++ * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
++ *
++ * derived from
++ *
++ * Hardware driver for the AMD 768 Random Number Generator (RNG)
++ * (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
++ *
++ * derived from
++ *
++ * Hardware driver for Intel i810 Random Number Generator (RNG)
++ * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
++ * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/of_address.h>
++#include <linux/interrupt.h>
++#include <linux/hw_random.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++
++#define MODULE_NAME "imx-rng"
++
++#define RNGC_VERSION_MAJOR3 3
++
++#define RNGC_VERSION_ID 0x0000
++#define RNGC_COMMAND 0x0004
++#define RNGC_CONTROL 0x0008
++#define RNGC_STATUS 0x000C
++#define RNGC_ERROR 0x0010
++#define RNGC_FIFO 0x0014
++#define RNGC_VERIF_CTRL 0x0020
++#define RNGC_OSC_CTRL_COUNT 0x0028
++#define RNGC_OSC_COUNT 0x002C
++#define RNGC_OSC_COUNT_STATUS 0x0030
++
++#define RNGC_VERID_ZEROS_MASK 0x0f000000
++#define RNGC_VERID_RNG_TYPE_MASK 0xf0000000
++#define RNGC_VERID_RNG_TYPE_SHIFT 28
++#define RNGC_VERID_CHIP_VERSION_MASK 0x00ff0000
++#define RNGC_VERID_CHIP_VERSION_SHIFT 16
++#define RNGC_VERID_VERSION_MAJOR_MASK 0x0000ff00
++#define RNGC_VERID_VERSION_MAJOR_SHIFT 8
++#define RNGC_VERID_VERSION_MINOR_MASK 0x000000ff
++#define RNGC_VERID_VERSION_MINOR_SHIFT 0
++
++#define RNGC_CMD_ZEROS_MASK 0xffffff8c
++#define RNGC_CMD_SW_RST 0x00000040
++#define RNGC_CMD_CLR_ERR 0x00000020
++#define RNGC_CMD_CLR_INT 0x00000010
++#define RNGC_CMD_SEED 0x00000002
++#define RNGC_CMD_SELF_TEST 0x00000001
++
++#define RNGC_CTRL_ZEROS_MASK 0xfffffc8c
++#define RNGC_CTRL_CTL_ACC 0x00000200
++#define RNGC_CTRL_VERIF_MODE 0x00000100
++#define RNGC_CTRL_MASK_ERROR 0x00000040
++
++#define RNGC_CTRL_MASK_DONE 0x00000020
++#define RNGC_CTRL_AUTO_SEED 0x00000010
++#define RNGC_CTRL_FIFO_UFLOW_MASK 0x00000003
++#define RNGC_CTRL_FIFO_UFLOW_SHIFT 0
++
++#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR 0
++#define RNGC_CTRL_FIFO_UFLOW_ZEROS_ERROR2 1
++#define RNGC_CTRL_FIFO_UFLOW_BUS_XFR 2
++#define RNGC_CTRL_FIFO_UFLOW_ZEROS_INTR 3
++
++#define RNGC_STATUS_ST_PF_MASK 0x00c00000
++#define RNGC_STATUS_ST_PF_SHIFT 22
++#define RNGC_STATUS_ST_PF_TRNG 0x00800000
++#define RNGC_STATUS_ST_PF_PRNG 0x00400000
++#define RNGC_STATUS_ERROR 0x00010000
++#define RNGC_STATUS_FIFO_SIZE_MASK 0x0000f000
++#define RNGC_STATUS_FIFO_SIZE_SHIFT 12
++#define RNGC_STATUS_FIFO_LEVEL_MASK 0x00000f00
++#define RNGC_STATUS_FIFO_LEVEL_SHIFT 8
++#define RNGC_STATUS_NEXT_SEED_DONE 0x00000040
++#define RNGC_STATUS_SEED_DONE 0x00000020
++#define RNGC_STATUS_ST_DONE 0x00000010
++#define RNGC_STATUS_RESEED 0x00000008
++#define RNGC_STATUS_SLEEP 0x00000004
++#define RNGC_STATUS_BUSY 0x00000002
++#define RNGC_STATUS_SEC_STATE 0x00000001
++
++#define RNGC_ERROR_STATUS_ZEROS_MASK 0xffffffc0
++#define RNGC_ERROR_STATUS_BAD_KEY 0x00000040
++#define RNGC_ERROR_STATUS_RAND_ERR 0x00000020
++#define RNGC_ERROR_STATUS_FIFO_ERR 0x00000010
++#define RNGC_ERROR_STATUS_STAT_ERR 0x00000008
++#define RNGC_ERROR_STATUS_ST_ERR 0x00000004
++#define RNGC_ERROR_STATUS_OSC_ERR 0x00000002
++#define RNGC_ERROR_STATUS_LFSR_ERR 0x00000001
++
++#define RNG_ADDR_RANGE 0x34
++
++static DECLARE_COMPLETION(rng_self_testing);
++static DECLARE_COMPLETION(rng_seed_done);
++
++static struct platform_device *imx_rng_dev;
++
++struct imx_rng_priv_data {
++ void __iomem *reg_base;
++};
++
++int irq_rng;
++
++static int imx_rng_data_present(struct hwrng *rng, int wait)
++{
++ int level;
++ struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)rng->priv;
++
++ /* how many random numbers are in FIFO? [0-16] */
++ level = (readl(prv->reg_base + RNGC_STATUS) &
++ RNGC_STATUS_FIFO_LEVEL_MASK) >> RNGC_STATUS_FIFO_LEVEL_SHIFT;
++
++ return level > 0 ? 1 : 0;
++}
++
++static int imx_rng_data_read(struct hwrng *rng, u32 * data)
++{
++ int err;
++ struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)rng->priv;
++
++ /* retrieve a random number from FIFO */
++ *data = readl(prv->reg_base + RNGC_FIFO);
++
++ /* is there some error while reading this random number? */
++ err = readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ERROR;
++
++ /* if error happened doesn't return random number */
++ return err ? 0 : 4;
++}
++
++static irqreturn_t imx_rng_irq(int irq, void *dev)
++{
++ int handled = 0;
++ struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)dev;
++
++ /* is the seed creation done? */
++ if (readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_SEED_DONE) {
++ complete(&rng_seed_done);
++ writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
++ prv->reg_base + RNGC_COMMAND);
++ handled = 1;
++ }
++
++ /* is the self test done? */
++ if (readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ST_DONE) {
++ complete(&rng_self_testing);
++ writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
++ prv->reg_base + RNGC_COMMAND);
++ handled = 1;
++ }
++
++ /* is there any error? */
++ if (readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ERROR) {
++ /* clear interrupt */
++ writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
++ prv->reg_base + RNGC_COMMAND);
++ handled = 1;
++ }
++
++ return handled;
++}
++
++static int imx_rng_init(struct hwrng *rng)
++{
++ int err;
++ struct imx_rng_priv_data *prv = (struct imx_rng_priv_data *)rng->priv;
++ u32 cmd, ctrl, osc;
++
++ reinit_completion(&rng_self_testing);
++ reinit_completion(&rng_seed_done);
++
++ err = readl(prv->reg_base + RNGC_STATUS) & RNGC_STATUS_ERROR;
++ if (err) {
++ /* is this a bad keys error ? */
++ if (readl(prv->reg_base + RNGC_ERROR) &
++ RNGC_ERROR_STATUS_BAD_KEY) {
++ dev_err(&imx_rng_dev->dev, "Can't start, Bad Keys.\n");
++ return -EIO;
++ }
++ }
++
++ /* mask all interrupts, will be unmasked soon */
++ ctrl = readl(prv->reg_base + RNGC_CONTROL);
++ writel(ctrl | RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR,
++ prv->reg_base + RNGC_CONTROL);
++
++ /* verify if oscillator is working */
++ osc = readl(prv->reg_base + RNGC_ERROR);
++ if (osc & RNGC_ERROR_STATUS_OSC_ERR) {
++ dev_err(&imx_rng_dev->dev, "RNGC Oscillator is dead!\n");
++ return -EIO;
++ }
++
++ err = request_irq(irq_rng, imx_rng_irq,
++ 0, "imx-rng", (void *)rng->priv);
++ if (err) {
++ dev_err(&imx_rng_dev->dev, "Can't get interrupt working.\n");
++ return -EIO;
++ }
++
++ /* do self test, repeat until get success */
++ do {
++ /* clear error */
++ cmd = readl(prv->reg_base + RNGC_COMMAND);
++ writel(cmd | RNGC_CMD_CLR_ERR, prv->reg_base + RNGC_COMMAND);
++
++ /* unmask all interrupt */
++ ctrl = readl(prv->reg_base + RNGC_CONTROL);
++ writel(ctrl & ~(RNGC_CTRL_MASK_DONE | RNGC_CTRL_MASK_ERROR),
++ prv->reg_base + RNGC_CONTROL);
++
++ /* run self test */
++ cmd = readl(prv->reg_base + RNGC_COMMAND);
++ writel(cmd | RNGC_CMD_SELF_TEST,
++ prv->reg_base + RNGC_COMMAND);
++
++ wait_for_completion(&rng_self_testing);
++
++ } while (readl(prv->reg_base + RNGC_ERROR) &
++ RNGC_ERROR_STATUS_ST_ERR);
++
++ /* clear interrupt. Is it really necessary here? */
++ writel(RNGC_CMD_CLR_INT | RNGC_CMD_CLR_ERR,
++ prv->reg_base + RNGC_COMMAND);
++
++ /* create seed, repeat while there is some statistical error */
++ do {
++ /* clear error */
++ cmd = readl(prv->reg_base + RNGC_COMMAND);
++ writel(cmd | RNGC_CMD_CLR_ERR, prv->reg_base + RNGC_COMMAND);
++
++ /* seed creation */
++ cmd = readl(prv->reg_base + RNGC_COMMAND);
++ writel(cmd | RNGC_CMD_SEED, prv->reg_base + RNGC_COMMAND);
++
++ wait_for_completion(&rng_seed_done);
++
++ } while (readl(prv->reg_base + RNGC_ERROR) &
++ RNGC_ERROR_STATUS_STAT_ERR);
++
++ err = readl(prv->reg_base + RNGC_ERROR) &
++ (RNGC_ERROR_STATUS_STAT_ERR |
++ RNGC_ERROR_STATUS_RAND_ERR |
++ RNGC_ERROR_STATUS_FIFO_ERR |
++ RNGC_ERROR_STATUS_ST_ERR |
++ RNGC_ERROR_STATUS_OSC_ERR |
++ RNGC_ERROR_STATUS_LFSR_ERR);
++
++ if (err) {
++ dev_err(&imx_rng_dev->dev, "iMX RNG appears inoperable.\n");
++ return -EIO;
++ }
++
++ return 0;
++}
++
++static struct hwrng imx_rng = {
++ .name = "imx-rng",
++ .init = imx_rng_init,
++ .data_present = imx_rng_data_present,
++ .data_read = imx_rng_data_read
++};
++
++static int __init imx_rng_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct clk *clk;
++ struct imx_rng_priv_data *priv;
++ int err = -ENODEV;
++
++ if (imx_rng_dev)
++ return -EBUSY;
++
++ /* Enable the clock */
++ clk = of_clk_get(np, 0);
++ if (IS_ERR(clk)) {
++ dev_err(dev, "Can not get clock.\n");
++ return PTR_ERR(clk);
++ }
++ clk_enable(clk);
++
++ /* Allocate private data memory */
++ priv = kzalloc(sizeof(struct imx_rng_priv_data), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ imx_rng.priv = (unsigned long)priv;
++ dev_set_drvdata(dev, priv);
++
++ /* ioremap that register space */
++ priv->reg_base = of_iomap(np, 0);
++ if (!priv->reg_base) {
++ kfree(priv);
++ dev_err(dev, "Failed to remap register space.\n");
++ return -ENODEV;
++ }
++
++ irq_rng = platform_get_irq(pdev, 0);
++
++ err = hwrng_register(&imx_rng);
++ if (err) {
++ iounmap(priv->reg_base);
++ kfree(priv);
++ dev_err(dev, "failed to register hwrng (%d)\n", err);
++ return err;
++ }
++
++ imx_rng_dev = pdev;
++ dev_info(dev, "iMX RNG Registered.\n");
++
++ return 0;
++}
++
++static int __exit imx_rng_remove(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct clk *clk;
++ struct imx_rng_priv_data *priv = dev_get_drvdata(dev);
++
++ /* Disable the clock */
++ clk = of_clk_get(np, 0);
++
++ if (IS_ERR(clk))
++ dev_err(dev, "Can not get clock.\n");
++ else
++ clk_disable(clk);
++
++ hwrng_unregister(&imx_rng);
++
++ iounmap(priv->reg_base);
++
++ kfree(priv);
++
++ return 0;
++}
++
++static int imx_rng_suspend(struct platform_device *pdev, pm_message_t state)
++{
++#ifdef CONFIG_PM
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct clk *clk = of_clk_get(np, 0);
++
++ if (IS_ERR(clk)) {
++ dev_err(&pdev->dev, "Can not get rng_clk\n");
++ return PTR_ERR(clk);
++ }
++
++ clk_disable(clk);
++#endif
++
++ return 0;
++}
++
++static int imx_rng_resume(struct platform_device *pdev)
++{
++#ifdef CONFIG_PM
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct clk *clk = of_clk_get(np, 0);
++
++ if (IS_ERR(clk)) {
++ dev_err(&pdev->dev, "Can not get rng_clk\n");
++ return PTR_ERR(clk);
++ }
++
++ clk_enable(clk);
++#endif
++
++ return 0;
++}
++
++static struct of_device_id imx_rng_dt_ids[] = {
++ { .compatible = "imx-rng",},
++ { .compatible = "fsl,imx-rng",},
++ { .compatible = "fsl,imx6sl-rng",},
++ { },
++};
++
++MODULE_DEVICE_TABLE(of, imx_rng_dt_ids);
++
++static struct platform_driver imx_rng_driver = {
++ .driver = {
++ .name = MODULE_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = imx_rng_dt_ids,
++ },
++ .remove = __exit_p(imx_rng_remove),
++ .suspend = imx_rng_suspend,
++ .resume = imx_rng_resume,
++};
++
++static int __init mod_init(void)
++{
++ return platform_driver_probe(&imx_rng_driver, imx_rng_probe);
++}
++
++static void __exit mod_exit(void)
++{
++ platform_driver_unregister(&imx_rng_driver);
++}
++
++module_init(mod_init);
++module_exit(mod_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("H/W RNG(B/C) driver for i.MX");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/char/hw_random/Kconfig linux-3.14.72/drivers/char/hw_random/Kconfig
+--- linux-3.14.72.orig/drivers/char/hw_random/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/char/hw_random/Kconfig 2016-06-19 22:11:55.109152867 +0200
+@@ -239,6 +239,18 @@
+
+ If unsure, say Y.
+
++config HW_RANDOM_IMX_RNG
++ tristate "Freescale RNG B/C Random Number Generator"
++ depends on HW_RANDOM && ARCH_MXC && HAVE_IMX_RNG
++ ---help---
++ This driver provides kernel-side support for the Random Number
++ Generator (RNGBB and RNGC) hardware found on Freescale i.MX processors.
++
++ To compile this driver as a module, choose M here: the
++ module will be called fsl-rngc.
++
++ If unsure, say Y.
++
+ config HW_RANDOM_NOMADIK
+ tristate "ST-Ericsson Nomadik Random Number Generator support"
+ depends on HW_RANDOM && ARCH_NOMADIK
+diff -Nur linux-3.14.72.orig/drivers/char/hw_random/Makefile linux-3.14.72/drivers/char/hw_random/Makefile
+--- linux-3.14.72.orig/drivers/char/hw_random/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/char/hw_random/Makefile 2016-06-19 22:11:55.109152867 +0200
+@@ -20,6 +20,7 @@
+ obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o
+ obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o
+ obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o
++obj-$(CONFIG_HW_RANDOM_IMX_RNG) += imx-rng.o
+ obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o
+ obj-$(CONFIG_HW_RANDOM_NOMADIK) += nomadik-rng.o
+ obj-$(CONFIG_HW_RANDOM_PICOXCELL) += picoxcell-rng.o
+diff -Nur linux-3.14.72.orig/drivers/char/imx_amp/imx_mcc_test.c linux-3.14.72/drivers/char/imx_amp/imx_mcc_test.c
+--- linux-3.14.72.orig/drivers/char/imx_amp/imx_mcc_test.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/char/imx_amp/imx_mcc_test.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,314 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/suspend.h>
++
++#include <linux/imx_sema4.h>
++#include <linux/mcc_config_linux.h>
++#include <linux/mcc_common.h>
++#include <linux/mcc_api.h>
++#include <linux/mcc_linux.h>
++#include <linux/mcc_imx6sx.h>
++
++enum {
++ MCC_NODE_A9 = 0,
++ MCC_NODE_M4 = 0,
++
++ MCC_A9_PORT = 1,
++ MCC_M4_PORT = 2,
++};
++
++/* mcc pingpong test */
++MCC_ENDPOINT mcc_endpoint_a9_pingpong = {0, MCC_NODE_A9, MCC_A9_PORT};
++MCC_ENDPOINT mcc_endpoint_m4_pingpong = {1, MCC_NODE_M4, MCC_M4_PORT};
++/* mcc can test */
++MCC_ENDPOINT mcc_endpoint_a9_can = {0, MCC_NODE_A9, MCC_A9_PORT};
++MCC_ENDPOINT mcc_endpoint_m4_can = {1, MCC_NODE_A9, MCC_A9_PORT};
++
++struct mcc_pp_msg {
++ unsigned int data;
++};
++
++/* Set the max len of the can msg to be 1000 bytes */
++struct mcc_can_msg {
++ char data[MCC_ATTR_BUFFER_SIZE_IN_BYTES - 24];
++};
++
++static ssize_t imx_mcc_can_test_en(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ u32 can_test_en;
++ int i = 0, ret = 0;
++ struct mcc_can_msg msg;
++ MCC_MEM_SIZE num_of_received_bytes;
++ MCC_INFO_STRUCT mcc_info;
++
++ sscanf(buf, "%d\n", &can_test_en);
++
++ if (can_test_en) {
++ pr_info("imx mcc can communication test begin.\n");
++ ret = mcc_get_info(MCC_NODE_A9, &mcc_info);
++ if (ret) {
++ pr_err("failed to get mcc info.\n");
++ return -EINVAL;
++ }
++
++ ret = mcc_create_endpoint(&mcc_endpoint_a9_can, MCC_A9_PORT);
++ if (ret) {
++ pr_err("failed to create a9 mcc ep.\n");
++ return -EINVAL;
++ }
++
++ pr_info("\nA9 mcc prepares run, MCC version is %s\n",
++ mcc_info.version_string);
++
++ while (i < 0x10000) {
++ i++;
++ /*
++ * wait for the "sleep" msg from the remote ep.
++ */
++ ret = mcc_recv(&mcc_endpoint_m4_can,
++ &mcc_endpoint_a9_can, &msg,
++ sizeof(struct mcc_can_msg),
++ &num_of_received_bytes, 0xffffffff);
++ if (ret < 0) {
++ pr_err("A9 Main task recv error: %d\n", ret);
++ break;
++ }
++ pr_info("%s", msg.data);
++ }
++
++ ret = mcc_destroy_endpoint(&mcc_endpoint_a9_can);
++ if (ret) {
++ pr_err("failed to destory a9 mcc ep.\n");
++ return -EINVAL;
++ } else {
++ pr_info("destory a9 mcc ep.\n");
++ }
++ }
++
++ pr_info("imx mcc test end after %08d times recv tests.\n", i);
++ return count;
++}
++
++static ssize_t imx_mcc_pingpong_en(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ u32 pingpong_en;
++ int i = 0, ret = 0;
++ struct timeval tv1, tv2, tv3;
++ u32 tv_count1 = 0, tv_count2 = 0;
++ struct mcc_pp_msg msg;
++ MCC_MEM_SIZE num_of_received_bytes;
++ MCC_INFO_STRUCT mcc_info;
++
++ sscanf(buf, "%d\n", &pingpong_en);
++ if (pingpong_en) {
++ pr_info("imx mcc pingpong test begin.\n");
++ ret = mcc_get_info(MCC_NODE_A9, &mcc_info);
++ if (ret) {
++ pr_err("failed to get mcc info.\n");
++ return -EINVAL;
++ }
++
++ ret = mcc_create_endpoint(&mcc_endpoint_a9_pingpong,
++ MCC_A9_PORT);
++ if (ret) {
++ pr_err("failed to create a9 mcc ep.\n");
++ return -EINVAL;
++ }
++
++ pr_info("\nA9 mcc prepares run, MCC version is %s\n",
++ mcc_info.version_string);
++ msg.data = 1;
++ while (i < 0x50000) {
++ i++;
++ i++;
++ /*
++ * wait until the remote endpoint is created by
++ * the other core
++ */
++ if (pingpong_en > 1)
++ do_gettimeofday(&tv1);
++
++ ret = mcc_send(&mcc_endpoint_a9_pingpong,
++ &mcc_endpoint_m4_pingpong, &msg,
++ sizeof(struct mcc_pp_msg),
++ 0xffffffff);
++ if (ret < 0) {
++ pr_err("A9 Main task send error: %d\n", ret);
++ break;
++ }
++
++ if (pingpong_en > 1) {
++ do_gettimeofday(&tv2);
++ tv_count1 = (tv2.tv_sec - tv1.tv_sec)
++ * USEC_PER_SEC
++ + tv2.tv_usec - tv1.tv_usec;
++ }
++ while (MCC_ERR_ENDPOINT == ret) {
++ pr_err("\n send err ret %d, re-send\n", ret);
++ ret = mcc_send(&mcc_endpoint_a9_pingpong,
++ &mcc_endpoint_m4_pingpong, &msg,
++ sizeof(struct mcc_pp_msg),
++ 0xffffffff);
++ msleep(5000);
++ }
++
++ if (pingpong_en > 1)
++ do_gettimeofday(&tv2);
++
++ ret = mcc_recv(&mcc_endpoint_m4_pingpong,
++ &mcc_endpoint_a9_pingpong, &msg,
++ sizeof(struct mcc_pp_msg),
++ &num_of_received_bytes, 0xffffffff);
++
++ if (pingpong_en > 1) {
++ do_gettimeofday(&tv3);
++ tv_count2 = (tv3.tv_sec - tv2.tv_sec)
++ * USEC_PER_SEC
++ + tv3.tv_usec - tv2.tv_usec;
++ pr_info("imx mcc: Data transfer speed tests"
++ "in pingpong. a9 -> m4:%08dus."
++ "a9 <- m4:%08dus.\n",
++ tv_count1, tv_count2);
++ }
++
++ if (MCC_SUCCESS != ret) {
++ pr_err("A9 Main task receive error: %d\n", ret);
++ break;
++ } else {
++ pr_info("%08x Main task received a msg"
++ " from [%d, %d, %d] endpoint\n", i,
++ mcc_endpoint_m4_pingpong.core,
++ mcc_endpoint_m4_pingpong.node,
++ mcc_endpoint_m4_pingpong.port);
++ pr_info("Message: Size=0x%08x, data = 0x%08x\n",
++ num_of_received_bytes, msg.data);
++ msg.data++;
++ }
++ }
++ ret = mcc_destroy_endpoint(&mcc_endpoint_a9_pingpong);
++ if (ret) {
++ pr_err("failed to destory a9 mcc ep.\n");
++ return ret;
++ } else {
++ pr_info("destory a9 mcc ep.\n");
++ }
++ pr_info("imx mcc test end after %08d times tests.\n", i/2);
++ }
++
++ if (ret)
++ return ret;
++ else
++ return count;
++}
++
++static DEVICE_ATTR(pingpong_en, S_IWUGO, NULL, imx_mcc_pingpong_en);
++static DEVICE_ATTR(can_test_en, S_IWUGO, NULL, imx_mcc_can_test_en);
++
++static struct attribute *imx_mcc_attrs[] = {
++ &dev_attr_pingpong_en.attr,
++ &dev_attr_can_test_en.attr,
++ NULL
++};
++
++static struct attribute_group imx_mcc_attrgroup = {
++ .attrs = imx_mcc_attrs,
++};
++
++static int imx_mcc_test_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++ MCC_INFO_STRUCT mcc_info;
++
++ ret = mcc_initialize(MCC_NODE_A9);
++ if (ret) {
++ pr_err("failed to initialize mcc.\n");
++ ret = -EINVAL;
++ return ret;
++ }
++
++ ret = mcc_get_info(MCC_NODE_A9, &mcc_info);
++ if (ret) {
++ pr_err("failed to get mcc info.\n");
++ ret = -EINVAL;
++ goto out_node;
++ }
++ pr_info("\nA9 mcc prepares run, MCC version is %s\n",
++ mcc_info.version_string);
++
++ if (strcmp(mcc_info.version_string, MCC_VERSION_STRING) != 0) {
++ pr_err("\nError, different versions of the MCC library");
++ pr_err("is used on each core!\n");
++ pr_err("\nApplication is stopped now.\n");
++ ret = -EINVAL;
++ goto out_node;
++ }
++
++ /* add attributes for device. */
++ ret = sysfs_create_group(&pdev->dev.kobj, &imx_mcc_attrgroup);
++ if (ret)
++ goto out_node;
++
++ return ret;
++
++out_node:
++ mcc_destroy(MCC_NODE_A9);
++
++ return ret;
++}
++
++static int imx_mcc_test_remove(struct platform_device *pdev)
++{
++ return 0;
++}
++
++static const struct of_device_id imx_mcc_test_dt_ids[] = {
++ { .compatible = "fsl,imx6sx-mcc-test", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_mcc_test_dt_ids);
++
++static struct platform_driver imx_mcc_test_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "imx6sx-mcc-test",
++ .of_match_table = imx_mcc_test_dt_ids,
++ },
++ .probe = imx_mcc_test_probe,
++ .remove = imx_mcc_test_remove,
++};
++
++static int __init imx_mcc_test_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&imx_mcc_test_driver);
++ if (ret)
++ pr_err("failed to register imx mcc test driver.\n");
++ else
++ pr_info("imx mcc test is registered.\n");
++ return ret;
++}
++late_initcall(imx_mcc_test_init);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX MCC test driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/char/imx_amp/imx_mcc_tty.c linux-3.14.72/drivers/char/imx_amp/imx_mcc_tty.c
+--- linux-3.14.72.orig/drivers/char/imx_amp/imx_mcc_tty.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/char/imx_amp/imx_mcc_tty.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,282 @@
++/*
++ * imx_mcc_tty.c - tty demo driver used to test imx mcc
++ * posix tty interface.
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/tty.h>
++#include <linux/tty_driver.h>
++#include <linux/tty_flip.h>
++#include <linux/mcc_config_linux.h>
++#include <linux/mcc_common.h>
++#include <linux/mcc_api.h>
++
++/**
++ * struct mcctty_port - Wrapper struct for imx mcc tty port.
++ * @port: TTY port data
++ */
++struct mcctty_port {
++ struct delayed_work read;
++ struct tty_port port;
++ spinlock_t rx_lock;
++};
++
++static struct mcctty_port mcc_tty_port;
++
++enum {
++ MCC_NODE_A9 = 0,
++ MCC_NODE_M4 = 0,
++
++ MCC_A9_PORT = 1,
++ MCC_M4_PORT = 2,
++};
++
++/* mcc tty/pingpong demo */
++static MCC_ENDPOINT mcc_endpoint_a9_pingpong = {0, MCC_NODE_A9, MCC_A9_PORT};
++static MCC_ENDPOINT mcc_endpoint_m4_pingpong = {1, MCC_NODE_M4, MCC_M4_PORT};
++struct mcc_tty_msg {
++ char data[MCC_ATTR_BUFFER_SIZE_IN_BYTES - 24];
++};
++
++static struct tty_port_operations mcctty_port_ops = { };
++
++static int mcctty_install(struct tty_driver *driver, struct tty_struct *tty)
++{
++ return tty_port_install(&mcc_tty_port.port, driver, tty);
++}
++
++static int mcctty_open(struct tty_struct *tty, struct file *filp)
++{
++ return tty_port_open(tty->port, tty, filp);
++}
++
++static void mcctty_close(struct tty_struct *tty, struct file *filp)
++{
++ return tty_port_close(tty->port, tty, filp);
++}
++
++static int mcctty_write(struct tty_struct *tty, const unsigned char *buf,
++ int total)
++{
++ int i, count, ret = 0, space;
++ unsigned char *cbuf, *tmp;
++ MCC_MEM_SIZE num_of_received_bytes;
++ struct mcc_tty_msg tty_msg;
++ struct mcctty_port *cport = &mcc_tty_port;
++
++ if (NULL == buf) {
++ pr_err("buf shouldn't be null.\n");
++ return -ENOMEM;
++ }
++
++ count = total;
++ tmp = (unsigned char *)buf;
++ for (i = 0; i <= count / 999; i++) {
++ strlcpy(tty_msg.data, tmp, count >= 1000 ? 1000 : count + 1);
++ if (count >= 1000)
++ count -= 999;
++
++ /*
++ * wait until the remote endpoint is created by
++ * the other core
++ */
++ ret = mcc_send(&mcc_endpoint_a9_pingpong,
++ &mcc_endpoint_m4_pingpong, &tty_msg,
++ sizeof(struct mcc_tty_msg),
++ 0xffffffff);
++
++ while (MCC_ERR_ENDPOINT == ret) {
++ pr_err("\n send err ret %d, re-send\n", ret);
++ ret = mcc_send(&mcc_endpoint_a9_pingpong,
++ &mcc_endpoint_m4_pingpong, &tty_msg,
++ sizeof(struct mcc_tty_msg),
++ 0xffffffff);
++ msleep(5000);
++ }
++
++ ret = mcc_recv(&mcc_endpoint_m4_pingpong,
++ &mcc_endpoint_a9_pingpong, &tty_msg,
++ sizeof(struct mcc_tty_msg),
++ &num_of_received_bytes, 0xffffffff);
++
++ if (MCC_SUCCESS != ret) {
++ pr_err("A9 Main task receive error: %d\n", ret);
++ } else {
++ /* flush the recv-ed data to tty node */
++ spin_lock_bh(&cport->rx_lock);
++ space = tty_prepare_flip_string(&cport->port, &cbuf,
++ strlen(tty_msg.data));
++ if (space <= 0)
++ return -ENOMEM;
++
++ memcpy(cbuf, &tty_msg.data, strlen(tty_msg.data));
++ tty_flip_buffer_push(&cport->port);
++ spin_unlock_bh(&cport->rx_lock);
++ }
++ }
++ return total;
++}
++
++static int mcctty_write_room(struct tty_struct *tty)
++{
++ /* report the space in the mcc buffer */
++ return MCC_ATTR_BUFFER_SIZE_IN_BYTES;
++}
++
++static const struct tty_operations imxmcctty_ops = {
++ .install = mcctty_install,
++ .open = mcctty_open,
++ .close = mcctty_close,
++ .write = mcctty_write,
++ .write_room = mcctty_write_room,
++};
++
++static struct tty_driver *mcctty_driver;
++
++static int imx_mcc_tty_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct mcctty_port *cport = &mcc_tty_port;
++ MCC_INFO_STRUCT mcc_info;
++
++ mcctty_driver = tty_alloc_driver(1,
++ TTY_DRIVER_RESET_TERMIOS |
++ TTY_DRIVER_UNNUMBERED_NODE);
++ if (IS_ERR(mcctty_driver))
++ return PTR_ERR(mcctty_driver);
++
++ mcctty_driver->driver_name = "mcc_tty";
++ mcctty_driver->name = "ttyMCC";
++ mcctty_driver->major = TTYAUX_MAJOR;
++ mcctty_driver->minor_start = 3;
++ mcctty_driver->type = TTY_DRIVER_TYPE_CONSOLE;
++ mcctty_driver->init_termios = tty_std_termios;
++ mcctty_driver->init_termios.c_cflag |= CLOCAL;
++
++ tty_set_operations(mcctty_driver, &imxmcctty_ops);
++
++ tty_port_init(&cport->port);
++ cport->port.ops = &mcctty_port_ops;
++ spin_lock_init(&cport->rx_lock);
++ cport->port.low_latency = cport->port.flags | ASYNC_LOW_LATENCY;
++
++ ret = tty_register_driver(mcctty_driver);
++ if (ret < 0) {
++ pr_err("Couldn't install mcc tty driver: err %d\n", ret);
++ goto error;
++ } else
++ pr_info("Install mcc tty driver!\n");
++
++ ret = mcc_initialize(MCC_NODE_A9);
++ if (ret) {
++ pr_err("failed to initialize mcc.\n");
++ ret = -ENODEV;
++ goto error;
++ }
++
++ ret = mcc_get_info(MCC_NODE_A9, &mcc_info);
++ if (ret) {
++ pr_err("failed to get mcc info.\n");
++ ret = -ENODEV;
++ goto error;
++ } else {
++ pr_info("\nA9 mcc prepares run, MCC version is %s\n",
++ mcc_info.version_string);
++ pr_info("imx mcc tty/pingpong test begin.\n");
++ }
++
++ ret = mcc_create_endpoint(&mcc_endpoint_a9_pingpong,
++ MCC_A9_PORT);
++ if (ret) {
++ pr_err("failed to create a9 mcc ep.\n");
++ ret = -ENODEV;
++ goto error;
++ }
++
++ return 0;
++
++error:
++ tty_unregister_driver(mcctty_driver);
++ put_tty_driver(mcctty_driver);
++ tty_port_destroy(&cport->port);
++ mcctty_driver = NULL;
++
++ return ret;
++}
++
++static int imx_mcc_tty_remove(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct mcctty_port *cport = &mcc_tty_port;
++
++ /* destory the mcc tty endpoint here */
++ ret = mcc_destroy_endpoint(&mcc_endpoint_a9_pingpong);
++ if (ret)
++ pr_err("failed to destory a9 mcc ep.\n");
++ else
++ pr_info("destory a9 mcc ep.\n");
++
++ tty_unregister_driver(mcctty_driver);
++ tty_port_destroy(&cport->port);
++ put_tty_driver(mcctty_driver);
++
++ return ret;
++}
++
++static const struct of_device_id imx6sx_mcc_tty_ids[] = {
++ { .compatible = "fsl,imx6sx-mcc-tty", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver imxmcctty_driver = {
++ .driver = {
++ .name = "imx6sx-mcc-tty",
++ .owner = THIS_MODULE,
++ .of_match_table = imx6sx_mcc_tty_ids,
++ },
++ .probe = imx_mcc_tty_probe,
++ .remove = imx_mcc_tty_remove,
++};
++
++/*!
++ * Initialise the imxmcctty_driver.
++ *
++ * @return The function always returns 0.
++ */
++
++static int __init imxmcctty_init(void)
++{
++ if (platform_driver_register(&imxmcctty_driver) != 0)
++ return -ENODEV;
++
++ printk(KERN_INFO "IMX MCC TTY driver module loaded\n");
++ return 0;
++}
++
++static void __exit imxmcctty_exit(void)
++{
++ /* Unregister the device structure */
++ platform_driver_unregister(&imxmcctty_driver);
++}
++
++module_init(imxmcctty_init);
++module_exit(imxmcctty_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MCC TTY driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/char/imx_amp/imx_sema4.c linux-3.14.72/drivers/char/imx_amp/imx_sema4.c
+--- linux-3.14.72.orig/drivers/char/imx_amp/imx_sema4.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/char/imx_amp/imx_sema4.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,419 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/mcc_config_linux.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/wait.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/imx_sema4.h>
++
++static struct imx_sema4_mutex_device *imx6_sema4;
++
++/*!
++ * \brief mutex create function.
++ *
++ * This function allocates imx_sema4_mutex structure and returns a handle
++ * to it. The mutex to be created is identified by SEMA4 device number and mutex
++ * (gate) number. The handle is used to reference the created mutex in calls to
++ * other imx_sema4_mutex API functions. This function is to be called only
++ * once for each mutex.
++ *
++ * \param[in] dev_num SEMA4 device (module) number.
++ * \param[in] mutex_num Mutex (gate) number.
++ *
++ * \return NULL (Failure.)
++ * \return imx_sema4_mutex (Success.)
++ */
++struct imx_sema4_mutex *
++imx_sema4_mutex_create(u32 dev_num, u32 mutex_num)
++{
++ struct imx_sema4_mutex *mutex_ptr = NULL;
++
++ if ((mutex_num > SEMA4_NUM_GATES) || dev_num >= SEMA4_NUM_DEVICES)
++ goto out;
++
++ if (imx6_sema4->cpine_val & (1 < mutex_num)) {
++ pr_err("Error: requiring a allocated sema4.\n");
++ pr_err("mutex_num %d cpine_val 0x%08x.\n",
++ mutex_num, imx6_sema4->cpine_val);
++ }
++ mutex_ptr = kzalloc(sizeof(*mutex_ptr), GFP_KERNEL);
++ if (!mutex_ptr)
++ goto out;
++ imx6_sema4->mutex_ptr[mutex_num] = mutex_ptr;
++ imx6_sema4->alloced |= 1 < mutex_num;
++ imx6_sema4->cpine_val |= idx_sema4[mutex_num];
++ writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE);
++
++ mutex_ptr->valid = CORE_MUTEX_VALID;
++ mutex_ptr->gate_num = mutex_num;
++ init_waitqueue_head(&mutex_ptr->wait_q);
++
++out:
++ return mutex_ptr;
++}
++EXPORT_SYMBOL(imx_sema4_mutex_create);
++
++/*!
++ * \brief mutex destroy function.
++ *
++ * This function destroys a mutex.
++ *
++ * \param[in] mutex_ptr Pointer to mutex structure.
++ *
++ * \return MQX_COMPONENT_DOES_NOT_EXIST (mutex component not installed.)
++ * \return MQX_INVALID_PARAMETER (Wrong input parameter.)
++ * \return COREMUTEX_OK (Success.)
++ *
++ */
++int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr)
++{
++ u32 mutex_num;
++
++ if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID))
++ return -EINVAL;
++
++ mutex_num = mutex_ptr->gate_num;
++ if ((imx6_sema4->cpine_val & idx_sema4[mutex_num]) == 0) {
++ pr_err("Error: trying to destory a un-allocated sema4.\n");
++ pr_err("mutex_num %d cpine_val 0x%08x.\n",
++ mutex_num, imx6_sema4->cpine_val);
++ }
++ imx6_sema4->mutex_ptr[mutex_num] = NULL;
++ imx6_sema4->alloced &= ~(1 << mutex_num);
++ imx6_sema4->cpine_val &= ~(idx_sema4[mutex_num]);
++ writew(imx6_sema4->cpine_val, imx6_sema4->ioaddr + SEMA4_CP0INE);
++
++ kfree(mutex_ptr);
++
++ return 0;
++}
++EXPORT_SYMBOL(imx_sema4_mutex_destroy);
++
++/*!
++ * \brief Lock the mutex, shouldn't be interruted by INT.
++ *
++ * This function attempts to lock a mutex. If the mutex is already locked
++ * by another task the function return -EBUSY, and tell invoker wait until
++ * it is possible to lock the mutex.
++ *
++ * \param[in] mutex_ptr Pointer to mutex structure.
++ *
++ * \return MQX_INVALID_POINTER (Wrong pointer to the mutex structure provided.)
++ * \return COREMUTEX_OK (mutex successfully locked.)
++ *
++ * \see imx_sema4_mutex_unlock
++ */
++int _imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr)
++{
++ int ret = 0, i = mutex_ptr->gate_num;
++
++ if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID))
++ return -EINVAL;
++
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= SEMA4_GATE_MASK;
++ /* Check to see if this core already own it */
++ if (mutex_ptr->gate_val == SEMA4_A9_LOCK) {
++ /* return -EBUSY, invoker should be in sleep, and re-lock ag */
++ pr_err("%s -> %s %d already locked, wait! num %d val %d.\n",
++ __FILE__, __func__, __LINE__,
++ i, mutex_ptr->gate_val);
++ ret = -EBUSY;
++ goto out;
++ } else {
++ /* try to lock the mutex */
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= (~SEMA4_GATE_MASK);
++ mutex_ptr->gate_val |= SEMA4_A9_LOCK;
++ writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= SEMA4_GATE_MASK;
++ /* double check the mutex is locked, otherwise, return -EBUSY */
++ if (mutex_ptr->gate_val != SEMA4_A9_LOCK) {
++ pr_debug("wait-locked num %d val %d.\n",
++ i, mutex_ptr->gate_val);
++ ret = -EBUSY;
++ }
++ }
++out:
++ return ret;
++}
++
++/* !
++ * \brief Try to lock the core mutex.
++ *
++ * This function attempts to lock a mutex. If the mutex is successfully locked
++ * for the calling task, SEMA4_A9_LOCK is returned. If the mutex is already
++ * locked by another task, the function does not block but rather returns
++ * negative immediately.
++ *
++ * \param[in] mutex_ptr Pointer to core_mutex structure.
++ *
++ * \return SEMA4_A9_LOCK (mutex successfully locked.)
++ * \return negative (mutex not locked.)
++ *
++ */
++int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr)
++{
++ int ret = 0;
++
++ ret = _imx_sema4_mutex_lock(mutex_ptr);
++ if (ret == 0)
++ return SEMA4_A9_LOCK;
++ else
++ return ret;
++}
++EXPORT_SYMBOL(imx_sema4_mutex_trylock);
++
++/*!
++ * \brief Invoke _imx_sema4_mutex_lock to lock the mutex.
++ *
++ * This function attempts to lock a mutex. If the mutex is already locked
++ * by another task the function, sleep itself and schedule out.
++ * Wait until it is possible to lock the mutex.
++ *
++ * Invoker should add its own wait queue into the wait queue header of the
++ * required semaphore, set TASK_INTERRUPTIBLE and sleep on itself by
++ * schedule() when the lock is failed. Re-try to lock the semaphore when
++ * it is woke up by the sema4 isr.
++ *
++ * \param[in] mutex_ptr Pointer to mutex structure.
++ *
++ * \return SEMA4_A9_LOCK (mutex successfully locked.)
++ *
++ * \see imx_sema4_mutex_unlock
++ */
++int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr)
++{
++ int ret = 0;
++ unsigned long flags;
++ unsigned long timeout_j; /* jiffies */
++
++ spin_lock_irqsave(&imx6_sema4->lock, flags);
++ ret = _imx_sema4_mutex_lock(mutex_ptr);
++ spin_unlock_irqrestore(&imx6_sema4->lock, flags);
++ while (-EBUSY == ret) {
++ if (MCC_SHMEM_SEMAPHORE_NUMBER == mutex_ptr->gate_num) {
++ timeout_j = msecs_to_jiffies(1000);
++ wait_event_timeout(mutex_ptr->wait_q,
++ mutex_ptr->gate_val == 0, timeout_j);
++ pr_debug("wake up val %d.\n", mutex_ptr->gate_val);
++ }
++ spin_lock_irqsave(&imx6_sema4->lock, flags);
++ ret = _imx_sema4_mutex_lock(mutex_ptr);
++ spin_unlock_irqrestore(&imx6_sema4->lock, flags);
++ if (ret == 0)
++ break;
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL(imx_sema4_mutex_lock);
++
++/*!
++ * \brief Unlock the mutex.
++ *
++ * This function unlocks the specified mutex.
++ *
++ * \param[in] mutex_ptr Pointer to mutex structure.
++ *
++ * \return -EINVAL (Wrong pointer to the mutex structure provided.)
++ * \return -EINVAL (This mutex has not been locked by this core.)
++ * \return 0 (mutex successfully unlocked.)
++ *
++ * \see imx_sema4_mutex_lock
++ */
++int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr)
++{
++ int ret = 0, i = mutex_ptr->gate_num;
++
++ if ((mutex_ptr == NULL) || (mutex_ptr->valid != CORE_MUTEX_VALID))
++ return -EINVAL;
++
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= SEMA4_GATE_MASK;
++ /* make sure it is locked by this core */
++ if (mutex_ptr->gate_val != SEMA4_A9_LOCK) {
++ pr_err("%d Trying to unlock an unlock mutex.\n", __LINE__);
++ ret = -EINVAL;
++ goto out;
++ }
++ /* unlock it */
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= (~SEMA4_GATE_MASK);
++ writeb(mutex_ptr->gate_val | SEMA4_UNLOCK, imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= SEMA4_GATE_MASK;
++ /* make sure it is locked by this core */
++ if (mutex_ptr->gate_val == SEMA4_A9_LOCK)
++ pr_err("%d ERROR, failed to unlock the mutex.\n", __LINE__);
++
++out:
++ return ret;
++}
++EXPORT_SYMBOL(imx_sema4_mutex_unlock);
++
++/*
++ * isr used by SEMA4, wake up the sleep tasks if there are the tasks waiting
++ * for locking semaphore.
++ * FIXME the bits order of the gatn, cpnie, cpnntf are not exact identified yet!
++ */
++static irqreturn_t imx_sema4_isr(int irq, void *dev_id)
++{
++ int i;
++ struct imx_sema4_mutex *mutex_ptr;
++ u32 mask;
++ struct imx_sema4_mutex_device *imx6_sema4 = dev_id;
++
++ imx6_sema4->cpntf_val = readw(imx6_sema4->ioaddr + SEMA4_CP0NTF);
++ for (i = 0; i < SEMA4_NUM_GATES; i++) {
++ mask = idx_sema4[i];
++ if ((imx6_sema4->cpntf_val) & mask) {
++ mutex_ptr = imx6_sema4->mutex_ptr[i];
++ /*
++ * An interrupt is pending on this mutex, the only way
++ * to clear it is to lock it (either by this core or
++ * another).
++ */
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= (~SEMA4_GATE_MASK);
++ mutex_ptr->gate_val |= SEMA4_A9_LOCK;
++ writeb(mutex_ptr->gate_val, imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val = readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= SEMA4_GATE_MASK;
++ if (mutex_ptr->gate_val == SEMA4_A9_LOCK) {
++ /*
++ * wake up the wait queue, whatever there
++ * are wait task or not.
++ * NOTE: check gate is locted or not in
++ * sema4_lock func by wait task.
++ */
++ mutex_ptr->gate_val =
++ readb(imx6_sema4->ioaddr + i);
++ mutex_ptr->gate_val &= (~SEMA4_GATE_MASK);
++ mutex_ptr->gate_val |= SEMA4_UNLOCK;
++
++ writeb(mutex_ptr->gate_val,
++ imx6_sema4->ioaddr + i);
++ wake_up(&mutex_ptr->wait_q);
++ } else {
++ pr_debug("can't lock gate%d %s retry!\n", i,
++ mutex_ptr->gate_val ?
++ "locked by m4" : "");
++ }
++ }
++ }
++
++ return IRQ_HANDLED;
++}
++
++static const struct of_device_id imx_sema4_dt_ids[] = {
++ { .compatible = "fsl,imx6sx-sema4", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_sema4_dt_ids);
++
++static int imx_sema4_probe(struct platform_device *pdev)
++{
++ struct resource *res;
++ int ret;
++
++ imx6_sema4 = devm_kzalloc(&pdev->dev, sizeof(*imx6_sema4), GFP_KERNEL);
++ if (!imx6_sema4)
++ return -ENOMEM;
++
++ imx6_sema4->dev = &pdev->dev;
++ imx6_sema4->cpine_val = 0;
++ spin_lock_init(&imx6_sema4->lock);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (IS_ERR(res)) {
++ dev_err(&pdev->dev, "unable to get imx sema4 resource 0\n");
++ ret = -ENODEV;
++ goto err;
++ }
++
++ imx6_sema4->ioaddr = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(imx6_sema4->ioaddr)) {
++ ret = PTR_ERR(imx6_sema4->ioaddr);
++ goto err;
++ }
++
++ imx6_sema4->irq = platform_get_irq(pdev, 0);
++ if (!imx6_sema4->irq) {
++ dev_err(&pdev->dev, "failed to get irq\n");
++ ret = -ENODEV;
++ goto err;
++ }
++
++ ret = devm_request_irq(&pdev->dev, imx6_sema4->irq, imx_sema4_isr,
++ IRQF_SHARED, "imx6sx-sema4", imx6_sema4);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request imx sema4 irq\n");
++ ret = -ENODEV;
++ goto err;
++ }
++
++ platform_set_drvdata(pdev, imx6_sema4);
++
++err:
++ return ret;
++}
++
++static int imx_sema4_remove(struct platform_device *pdev)
++{
++ return 0;
++}
++
++static struct platform_driver imx_sema4_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "imx-sema4",
++ .of_match_table = imx_sema4_dt_ids,
++ },
++ .probe = imx_sema4_probe,
++ .remove = imx_sema4_remove,
++};
++
++static int __init imx_sema4_init(void)
++{
++ int ret;
++
++ ret = platform_driver_register(&imx_sema4_driver);
++ if (ret)
++ pr_err("Unable to initialize sema4 driver\n");
++ else
++ pr_info("imx sema4 driver is registered.\n");
++
++ return ret;
++}
++
++static void __exit imx_sema4_exit(void)
++{
++ pr_info("imx sema4 driver is unregistered.\n");
++ platform_driver_unregister(&imx_sema4_driver);
++}
++
++module_exit(imx_sema4_exit);
++module_init(imx_sema4_init);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX SEMA4 driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/char/imx_amp/Kconfig linux-3.14.72/drivers/char/imx_amp/Kconfig
+--- linux-3.14.72.orig/drivers/char/imx_amp/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/char/imx_amp/Kconfig 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,30 @@
++#
++# imx mcc
++#
++
++config IMX_SEMA4
++ bool "IMX SEMA4 driver"
++ depends on SOC_IMX6SX
++ help
++ Support for IMX SEMA4 driver, most people should say N here.
++
++config IMX_MCC_TEST
++ bool "IMX MCC test driver"
++ depends on SOC_IMX6SX && IMX_SEMA4
++ default y
++ help
++ If you say Y here, you will get support for IMX MCC ping pong
++ test and CAN test. Say N here, if the IMX_MCC_TTY interface is
++ mandatory required.
++
++ If unsure, it is safe to say Y.
++
++config IMX_MCC_TTY
++ bool "IMX PTY for MCC interface"
++ depends on SOC_IMX6SX && IMX_SEMA4 && !IMX_MCC_TEST
++ help
++ This enables a PTY node for IMX6SX MCC, used as interface
++ between kernel space and user space. Say N here, if the
++ interface is not required.
++
++#end imx mcc
+diff -Nur linux-3.14.72.orig/drivers/char/imx_amp/Makefile linux-3.14.72/drivers/char/imx_amp/Makefile
+--- linux-3.14.72.orig/drivers/char/imx_amp/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/char/imx_amp/Makefile 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,7 @@
++#
++# Makefile for imx mcc
++#
++#
++obj-$(CONFIG_IMX_SEMA4) += imx_sema4.o
++obj-$(CONFIG_IMX_MCC_TEST) += imx_mcc_test.o
++obj-$(CONFIG_IMX_MCC_TTY) += imx_mcc_tty.o
+diff -Nur linux-3.14.72.orig/drivers/char/Kconfig linux-3.14.72/drivers/char/Kconfig
+--- linux-3.14.72.orig/drivers/char/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/char/Kconfig 2016-06-19 22:11:55.109152867 +0200
+@@ -82,6 +82,33 @@
+
+ If unsure, say N.
+
++config FSL_OTP
++ tristate "Freescale On-Chip OTP Memory Support"
++ depends on HAS_IOMEM && OF
++ help
++ If you say Y here, you will get support for a character device
++ interface into the One Time Programmable memory pages that are
++ stored on the some Freescale i.MX processors. This will not get
++ you access to the secure memory pages however. You will need to
++ write your own secure code and reader for that.
++
++ To compile this driver as a module, choose M here: the module
++ will be called fsl_otp.
++
++ If unsure, it is safe to say Y.
++
++config FSL_OTP_WRITE_ENABLE
++ bool "Enable writing support of OTP pages on Freescale chips"
++ depends on FSL_OTP
++ default n
++ help
++ If you say Y here, you will enable support for writing of the
++ OTP pages. This is dangerous by nature as you can only program
++ the pages once, so only enable this option when you actually
++ need it so as to not inadvertently clobber data.
++
++ If unsure, say N.
++
+ config PRINTER
+ tristate "Parallel printer support"
+ depends on PARPORT
+@@ -600,5 +627,6 @@
+ device appear much like a simple EEPROM, and knows
+ how to partition a single ROM for multiple purposes.
+
++source "drivers/char/imx_amp/Kconfig"
+ endmenu
+
+diff -Nur linux-3.14.72.orig/drivers/char/Makefile linux-3.14.72/drivers/char/Makefile
+--- linux-3.14.72.orig/drivers/char/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/char/Makefile 2016-06-19 22:11:55.109152867 +0200
+@@ -16,6 +16,7 @@
+ obj-$(CONFIG_IBM_BSR) += bsr.o
+ obj-$(CONFIG_SGI_MBCS) += mbcs.o
+ obj-$(CONFIG_BFIN_OTP) += bfin-otp.o
++obj-$(CONFIG_FSL_OTP) += fsl_otp.o
+
+ obj-$(CONFIG_PRINTER) += lp.o
+
+@@ -61,3 +62,4 @@
+ js-rtc-y = rtc.o
+
+ obj-$(CONFIG_TILE_SROM) += tile-srom.o
++obj-$(CONFIG_HAVE_IMX_AMP) += imx_amp/
+diff -Nur linux-3.14.72.orig/drivers/clk/clk.c linux-3.14.72/drivers/clk/clk.c
+--- linux-3.14.72.orig/drivers/clk/clk.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/clk/clk.c 2016-06-19 22:11:55.109152867 +0200
+@@ -10,6 +10,7 @@
+ */
+
+ #include <linux/clk-private.h>
++#include <linux/clk/clk-conf.h>
+ #include <linux/module.h>
+ #include <linux/mutex.h>
+ #include <linux/spinlock.h>
+@@ -1707,6 +1708,7 @@
+ */
+ int clk_set_parent(struct clk *clk, struct clk *parent)
+ {
++ struct clk *child;
+ int ret = 0;
+ int p_index = 0;
+ unsigned long p_rate = 0;
+@@ -1733,6 +1735,18 @@
+ goto out;
+ }
+
++ /* check two consecutive basic mux clocks */
++ if (clk->flags & CLK_IS_BASIC_MUX) {
++ hlist_for_each_entry(child, &clk->children, child_node) {
++ if (child->flags & CLK_IS_BASIC_MUX) {
++ pr_err("%s: failed to switch parent of %s due to child mux %s\n",
++ __func__, clk->name, child->name);
++ ret = -EBUSY;
++ goto out;
++ }
++ }
++ }
++
+ /* try finding the new parent index */
+ if (parent) {
+ p_index = clk_fetch_parent_index(clk, parent);
+@@ -2429,6 +2443,7 @@
+ void *data)
+ {
+ struct of_clk_provider *cp;
++ int ret;
+
+ cp = kzalloc(sizeof(struct of_clk_provider), GFP_KERNEL);
+ if (!cp)
+@@ -2443,7 +2458,11 @@
+ mutex_unlock(&of_clk_mutex);
+ pr_debug("Added clock from %s\n", np->full_name);
+
+- return 0;
++ ret = of_clk_set_defaults(np, true);
++ if (ret < 0)
++ of_clk_del_provider(np);
++
++ return ret;
+ }
+ EXPORT_SYMBOL_GPL(of_clk_add_provider);
+
+@@ -2543,6 +2562,7 @@
+ for_each_matching_node_and_match(np, matches, &match) {
+ of_clk_init_cb_t clk_init_cb = match->data;
+ clk_init_cb(np);
++ of_clk_set_defaults(np, true);
+ }
+ }
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/clk/clk-conf.c linux-3.14.72/drivers/clk/clk-conf.c
+--- linux-3.14.72.orig/drivers/clk/clk-conf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/clk/clk-conf.c 2016-06-19 22:11:55.109152867 +0200
+@@ -0,0 +1,143 @@
++/*
++ * Copyright (C) 2014 Samsung Electronics Co., Ltd.
++ * Sylwester Nawrocki <s.nawrocki@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clk/clk-conf.h>
++#include <linux/device.h>
++#include <linux/of.h>
++#include <linux/printk.h>
++#include "clk.h"
++
++static int __set_clk_parents(struct device_node *node, bool clk_supplier)
++{
++ struct of_phandle_args clkspec;
++ int index, rc, num_parents;
++ struct clk *clk, *pclk;
++
++ num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
++ "#clock-cells");
++ if (num_parents == -EINVAL)
++ pr_err("clk: invalid value of clock-parents property at %s\n",
++ node->full_name);
++
++ for (index = 0; index < num_parents; index++) {
++ rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
++ "#clock-cells", index, &clkspec);
++ if (rc < 0) {
++ /* skip empty (null) phandles */
++ if (rc == -ENOENT)
++ continue;
++ else
++ return rc;
++ }
++ if (clkspec.np == node && !clk_supplier)
++ return 0;
++ pclk = of_clk_get_by_clkspec(&clkspec);
++ if (IS_ERR(pclk)) {
++ pr_warn("clk: couldn't get parent clock %d for %s\n",
++ index, node->full_name);
++ return PTR_ERR(pclk);
++ }
++
++ rc = of_parse_phandle_with_args(node, "assigned-clocks",
++ "#clock-cells", index, &clkspec);
++ if (rc < 0)
++ goto err;
++ if (clkspec.np == node && !clk_supplier) {
++ rc = 0;
++ goto err;
++ }
++ clk = of_clk_get_by_clkspec(&clkspec);
++ if (IS_ERR(pclk)) {
++ pr_warn("clk: couldn't get parent clock %d for %s\n",
++ index, node->full_name);
++ rc = PTR_ERR(pclk);
++ goto err;
++ }
++
++ rc = clk_set_parent(clk, pclk);
++ if (rc < 0)
++ pr_err("clk: failed to reparent %s to %s: %d\n",
++ __clk_get_name(clk), __clk_get_name(pclk), rc);
++ clk_put(clk);
++ clk_put(pclk);
++ }
++ return 0;
++err:
++ clk_put(pclk);
++ return rc;
++}
++
++static int __set_clk_rates(struct device_node *node, bool clk_supplier)
++{
++ struct of_phandle_args clkspec;
++ struct property *prop;
++ const __be32 *cur;
++ int rc, index = 0;
++ struct clk *clk;
++ u32 rate;
++
++ of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
++ if (rate) {
++ rc = of_parse_phandle_with_args(node, "assigned-clocks",
++ "#clock-cells", index, &clkspec);
++ if (rc < 0) {
++ /* skip empty (null) phandles */
++ if (rc == -ENOENT)
++ continue;
++ else
++ return rc;
++ }
++ if (clkspec.np == node && !clk_supplier)
++ return 0;
++
++ clk = of_clk_get_by_clkspec(&clkspec);
++ if (IS_ERR(clk)) {
++ pr_warn("clk: couldn't get clock %d for %s\n",
++ index, node->full_name);
++ return PTR_ERR(clk);
++ }
++
++ rc = clk_set_rate(clk, rate);
++ if (rc < 0)
++ pr_err("clk: couldn't set %s clock rate: %d\n",
++ __clk_get_name(clk), rc);
++ clk_put(clk);
++ }
++ index++;
++ }
++ return 0;
++}
++
++/**
++ * of_clk_set_defaults() - parse and set assigned clocks configuration
++ * @node: device node to apply clock settings for
++ * @clk_supplier: true if clocks supplied by @node should also be considered
++ *
++ * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
++ * and sets any specified clock parents and rates. The @clk_supplier argument
++ * should be set to true if @node may be also a clock supplier of any clock
++ * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
++ * If @clk_supplier is false the function exits returnning 0 as soon as it
++ * determines the @node is also a supplier of any of the clocks.
++ */
++int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
++{
++ int rc;
++
++ if (!node)
++ return 0;
++
++ rc = __set_clk_parents(node, clk_supplier);
++ if (rc < 0)
++ return rc;
++
++ return __set_clk_rates(node, clk_supplier);
++}
+diff -Nur linux-3.14.72.orig/drivers/clk/clkdev.c linux-3.14.72/drivers/clk/clkdev.c
+--- linux-3.14.72.orig/drivers/clk/clkdev.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/clk/clkdev.c 2016-06-19 22:11:55.109152867 +0200
+@@ -27,6 +27,32 @@
+ static DEFINE_MUTEX(clocks_mutex);
+
+ #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
++
++/**
++ * of_clk_get_by_clkspec() - Lookup a clock form a clock provider
++ * @clkspec: pointer to a clock specifier data structure
++ *
++ * This function looks up a struct clk from the registered list of clock
++ * providers, an input is a clock specifier data structure as returned
++ * from the of_parse_phandle_with_args() function call.
++ */
++struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec)
++{
++ struct clk *clk;
++
++ if (!clkspec)
++ return ERR_PTR(-EINVAL);
++
++ of_clk_lock();
++ clk = __of_clk_get_from_provider(clkspec);
++
++ if (!IS_ERR(clk) && !__clk_get(clk))
++ clk = ERR_PTR(-ENOENT);
++
++ of_clk_unlock();
++ return clk;
++}
++
+ struct clk *of_clk_get(struct device_node *np, int index)
+ {
+ struct of_phandle_args clkspec;
+@@ -41,13 +67,7 @@
+ if (rc)
+ return ERR_PTR(rc);
+
+- of_clk_lock();
+- clk = __of_clk_get_from_provider(&clkspec);
+-
+- if (!IS_ERR(clk) && !__clk_get(clk))
+- clk = ERR_PTR(-ENOENT);
+-
+- of_clk_unlock();
++ clk = of_clk_get_by_clkspec(&clkspec);
+ of_node_put(clkspec.np);
+ return clk;
+ }
+diff -Nur linux-3.14.72.orig/drivers/clk/clk.h linux-3.14.72/drivers/clk/clk.h
+--- linux-3.14.72.orig/drivers/clk/clk.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/clk/clk.h 2016-06-19 22:11:55.113152605 +0200
+@@ -10,6 +10,7 @@
+ */
+
+ #if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
++struct clk *of_clk_get_by_clkspec(struct of_phandle_args *clkspec);
+ struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec);
+ void of_clk_lock(void);
+ void of_clk_unlock(void);
+diff -Nur linux-3.14.72.orig/drivers/clk/clk-mux.c linux-3.14.72/drivers/clk/clk-mux.c
+--- linux-3.14.72.orig/drivers/clk/clk-mux.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/clk/clk-mux.c 2016-06-19 22:11:55.113152605 +0200
+@@ -143,7 +143,7 @@
+ init.ops = &clk_mux_ro_ops;
+ else
+ init.ops = &clk_mux_ops;
+- init.flags = flags | CLK_IS_BASIC;
++ init.flags = flags | CLK_IS_BASIC | CLK_IS_BASIC_MUX;
+ init.parent_names = parent_names;
+ init.num_parents = num_parents;
+
+diff -Nur linux-3.14.72.orig/drivers/clk/Makefile linux-3.14.72/drivers/clk/Makefile
+--- linux-3.14.72.orig/drivers/clk/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/clk/Makefile 2016-06-19 22:11:55.113152605 +0200
+@@ -8,6 +8,9 @@
+ obj-$(CONFIG_COMMON_CLK) += clk-gate.o
+ obj-$(CONFIG_COMMON_CLK) += clk-mux.o
+ obj-$(CONFIG_COMMON_CLK) += clk-composite.o
++ifeq ($(CONFIG_OF), y)
++obj-$(CONFIG_COMMON_CLK) += clk-conf.o
++endif
+
+ # hardware specific clock types
+ # please keep this section sorted lexicographically by file/directory path name
+diff -Nur linux-3.14.72.orig/drivers/cpufreq/cpufreq_interactive.c linux-3.14.72/drivers/cpufreq/cpufreq_interactive.c
+--- linux-3.14.72.orig/drivers/cpufreq/cpufreq_interactive.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/cpufreq/cpufreq_interactive.c 2016-06-19 22:11:55.113152605 +0200
+@@ -0,0 +1,1345 @@
++/*
++ * drivers/cpufreq/cpufreq_interactive.c
++ *
++ * Copyright (C) 2010 Google, Inc.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * Author: Mike Chan (mike@android.com)
++ *
++ */
++
++#include <linux/cpu.h>
++#include <linux/cpumask.h>
++#include <linux/cpufreq.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/rwsem.h>
++#include <linux/sched.h>
++#include <linux/sched/rt.h>
++#include <linux/tick.h>
++#include <linux/time.h>
++#include <linux/timer.h>
++#include <linux/workqueue.h>
++#include <linux/kthread.h>
++#include <linux/slab.h>
++
++#define CREATE_TRACE_POINTS
++#include <trace/events/cpufreq_interactive.h>
++
++struct cpufreq_interactive_cpuinfo {
++ struct timer_list cpu_timer;
++ struct timer_list cpu_slack_timer;
++ spinlock_t load_lock; /* protects the next 4 fields */
++ u64 time_in_idle;
++ u64 time_in_idle_timestamp;
++ u64 cputime_speedadj;
++ u64 cputime_speedadj_timestamp;
++ struct cpufreq_policy *policy;
++ struct cpufreq_frequency_table *freq_table;
++ unsigned int target_freq;
++ unsigned int floor_freq;
++ u64 floor_validate_time;
++ u64 hispeed_validate_time;
++ struct rw_semaphore enable_sem;
++ int governor_enabled;
++};
++
++static DEFINE_PER_CPU(struct cpufreq_interactive_cpuinfo, cpuinfo);
++
++/* realtime thread handles frequency scaling */
++static struct task_struct *speedchange_task;
++static cpumask_t speedchange_cpumask;
++static spinlock_t speedchange_cpumask_lock;
++static struct mutex gov_lock;
++
++/* Target load. Lower values result in higher CPU speeds. */
++#define DEFAULT_TARGET_LOAD 90
++static unsigned int default_target_loads[] = {DEFAULT_TARGET_LOAD};
++
++#define DEFAULT_TIMER_RATE (20 * USEC_PER_MSEC)
++#define DEFAULT_ABOVE_HISPEED_DELAY DEFAULT_TIMER_RATE
++static unsigned int default_above_hispeed_delay[] = {
++ DEFAULT_ABOVE_HISPEED_DELAY };
++
++struct cpufreq_interactive_tunables {
++ int usage_count;
++ /* Hi speed to bump to from lo speed when load burst (default max) */
++ unsigned int hispeed_freq;
++ /* Go to hi speed when CPU load at or above this value. */
++#define DEFAULT_GO_HISPEED_LOAD 99
++ unsigned long go_hispeed_load;
++ /* Target load. Lower values result in higher CPU speeds. */
++ spinlock_t target_loads_lock;
++ unsigned int *target_loads;
++ int ntarget_loads;
++ /*
++ * The minimum amount of time to spend at a frequency before we can ramp
++ * down.
++ */
++#define DEFAULT_MIN_SAMPLE_TIME (80 * USEC_PER_MSEC)
++ unsigned long min_sample_time;
++ /*
++ * The sample rate of the timer used to increase frequency
++ */
++ unsigned long timer_rate;
++ /*
++ * Wait this long before raising speed above hispeed, by default a
++ * single timer interval.
++ */
++ spinlock_t above_hispeed_delay_lock;
++ unsigned int *above_hispeed_delay;
++ int nabove_hispeed_delay;
++ /* Non-zero means indefinite speed boost active */
++ int boost_val;
++ /* Duration of a boot pulse in usecs */
++ int boostpulse_duration_val;
++ /* End time of boost pulse in ktime converted to usecs */
++ u64 boostpulse_endtime;
++ /*
++ * Max additional time to wait in idle, beyond timer_rate, at speeds
++ * above minimum before wakeup to reduce speed, or -1 if unnecessary.
++ */
++#define DEFAULT_TIMER_SLACK (4 * DEFAULT_TIMER_RATE)
++ int timer_slack_val;
++ bool io_is_busy;
++};
++
++/* For cases where we have single governor instance for system */
++struct cpufreq_interactive_tunables *common_tunables;
++
++static struct attribute_group *get_sysfs_attr(void);
++
++static void cpufreq_interactive_timer_resched(
++ struct cpufreq_interactive_cpuinfo *pcpu)
++{
++ struct cpufreq_interactive_tunables *tunables =
++ pcpu->policy->governor_data;
++ unsigned long expires;
++ unsigned long flags;
++
++ spin_lock_irqsave(&pcpu->load_lock, flags);
++ pcpu->time_in_idle =
++ get_cpu_idle_time(smp_processor_id(),
++ &pcpu->time_in_idle_timestamp,
++ tunables->io_is_busy);
++ pcpu->cputime_speedadj = 0;
++ pcpu->cputime_speedadj_timestamp = pcpu->time_in_idle_timestamp;
++ expires = jiffies + usecs_to_jiffies(tunables->timer_rate);
++ mod_timer_pinned(&pcpu->cpu_timer, expires);
++
++ if (tunables->timer_slack_val >= 0 &&
++ pcpu->target_freq > pcpu->policy->min) {
++ expires += usecs_to_jiffies(tunables->timer_slack_val);
++ mod_timer_pinned(&pcpu->cpu_slack_timer, expires);
++ }
++
++ spin_unlock_irqrestore(&pcpu->load_lock, flags);
++}
++
++/* The caller shall take enable_sem write semaphore to avoid any timer race.
++ * The cpu_timer and cpu_slack_timer must be deactivated when calling this
++ * function.
++ */
++static void cpufreq_interactive_timer_start(
++ struct cpufreq_interactive_tunables *tunables, int cpu)
++{
++ struct cpufreq_interactive_cpuinfo *pcpu = &per_cpu(cpuinfo, cpu);
++ unsigned long expires = jiffies +
++ usecs_to_jiffies(tunables->timer_rate);
++ unsigned long flags;
++
++ pcpu->cpu_timer.expires = expires;
++ add_timer_on(&pcpu->cpu_timer, cpu);
++ if (tunables->timer_slack_val >= 0 &&
++ pcpu->target_freq > pcpu->policy->min) {
++ expires += usecs_to_jiffies(tunables->timer_slack_val);
++ pcpu->cpu_slack_timer.expires = expires;
++ add_timer_on(&pcpu->cpu_slack_timer, cpu);
++ }
++
++ spin_lock_irqsave(&pcpu->load_lock, flags);
++ pcpu->time_in_idle =
++ get_cpu_idle_time(cpu, &pcpu->time_in_idle_timestamp,
++ tunables->io_is_busy);
++ pcpu->cputime_speedadj = 0;
++ pcpu->cputime_speedadj_timestamp = pcpu->time_in_idle_timestamp;
++ spin_unlock_irqrestore(&pcpu->load_lock, flags);
++}
++
++static unsigned int freq_to_above_hispeed_delay(
++ struct cpufreq_interactive_tunables *tunables,
++ unsigned int freq)
++{
++ int i;
++ unsigned int ret;
++ unsigned long flags;
++
++ spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags);
++
++ for (i = 0; i < tunables->nabove_hispeed_delay - 1 &&
++ freq >= tunables->above_hispeed_delay[i+1]; i += 2)
++ ;
++
++ ret = tunables->above_hispeed_delay[i];
++ spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags);
++ return ret;
++}
++
++static unsigned int freq_to_targetload(
++ struct cpufreq_interactive_tunables *tunables, unsigned int freq)
++{
++ int i;
++ unsigned int ret;
++ unsigned long flags;
++
++ spin_lock_irqsave(&tunables->target_loads_lock, flags);
++
++ for (i = 0; i < tunables->ntarget_loads - 1 &&
++ freq >= tunables->target_loads[i+1]; i += 2)
++ ;
++
++ ret = tunables->target_loads[i];
++ spin_unlock_irqrestore(&tunables->target_loads_lock, flags);
++ return ret;
++}
++
++/*
++ * If increasing frequencies never map to a lower target load then
++ * choose_freq() will find the minimum frequency that does not exceed its
++ * target load given the current load.
++ */
++static unsigned int choose_freq(struct cpufreq_interactive_cpuinfo *pcpu,
++ unsigned int loadadjfreq)
++{
++ unsigned int freq = pcpu->policy->cur;
++ unsigned int prevfreq, freqmin, freqmax;
++ unsigned int tl;
++ int index;
++
++ freqmin = 0;
++ freqmax = UINT_MAX;
++
++ do {
++ prevfreq = freq;
++ tl = freq_to_targetload(pcpu->policy->governor_data, freq);
++
++ /*
++ * Find the lowest frequency where the computed load is less
++ * than or equal to the target load.
++ */
++
++ if (cpufreq_frequency_table_target(
++ pcpu->policy, pcpu->freq_table, loadadjfreq / tl,
++ CPUFREQ_RELATION_L, &index))
++ break;
++ freq = pcpu->freq_table[index].frequency;
++
++ if (freq > prevfreq) {
++ /* The previous frequency is too low. */
++ freqmin = prevfreq;
++
++ if (freq >= freqmax) {
++ /*
++ * Find the highest frequency that is less
++ * than freqmax.
++ */
++ if (cpufreq_frequency_table_target(
++ pcpu->policy, pcpu->freq_table,
++ freqmax - 1, CPUFREQ_RELATION_H,
++ &index))
++ break;
++ freq = pcpu->freq_table[index].frequency;
++
++ if (freq == freqmin) {
++ /*
++ * The first frequency below freqmax
++ * has already been found to be too
++ * low. freqmax is the lowest speed
++ * we found that is fast enough.
++ */
++ freq = freqmax;
++ break;
++ }
++ }
++ } else if (freq < prevfreq) {
++ /* The previous frequency is high enough. */
++ freqmax = prevfreq;
++
++ if (freq <= freqmin) {
++ /*
++ * Find the lowest frequency that is higher
++ * than freqmin.
++ */
++ if (cpufreq_frequency_table_target(
++ pcpu->policy, pcpu->freq_table,
++ freqmin + 1, CPUFREQ_RELATION_L,
++ &index))
++ break;
++ freq = pcpu->freq_table[index].frequency;
++
++ /*
++ * If freqmax is the first frequency above
++ * freqmin then we have already found that
++ * this speed is fast enough.
++ */
++ if (freq == freqmax)
++ break;
++ }
++ }
++
++ /* If same frequency chosen as previous then done. */
++ } while (freq != prevfreq);
++
++ return freq;
++}
++
++static u64 update_load(int cpu)
++{
++ struct cpufreq_interactive_cpuinfo *pcpu = &per_cpu(cpuinfo, cpu);
++ struct cpufreq_interactive_tunables *tunables =
++ pcpu->policy->governor_data;
++ u64 now;
++ u64 now_idle;
++ unsigned int delta_idle;
++ unsigned int delta_time;
++ u64 active_time;
++
++ now_idle = get_cpu_idle_time(cpu, &now, tunables->io_is_busy);
++ delta_idle = (unsigned int)(now_idle - pcpu->time_in_idle);
++ delta_time = (unsigned int)(now - pcpu->time_in_idle_timestamp);
++
++ if (delta_time <= delta_idle)
++ active_time = 0;
++ else
++ active_time = delta_time - delta_idle;
++
++ pcpu->cputime_speedadj += active_time * pcpu->policy->cur;
++
++ pcpu->time_in_idle = now_idle;
++ pcpu->time_in_idle_timestamp = now;
++ return now;
++}
++
++static void cpufreq_interactive_timer(unsigned long data)
++{
++ u64 now;
++ unsigned int delta_time;
++ u64 cputime_speedadj;
++ int cpu_load;
++ struct cpufreq_interactive_cpuinfo *pcpu =
++ &per_cpu(cpuinfo, data);
++ struct cpufreq_interactive_tunables *tunables =
++ pcpu->policy->governor_data;
++ unsigned int new_freq;
++ unsigned int loadadjfreq;
++ unsigned int index;
++ unsigned long flags;
++ bool boosted;
++
++ if (!down_read_trylock(&pcpu->enable_sem))
++ return;
++ if (!pcpu->governor_enabled)
++ goto exit;
++
++ spin_lock_irqsave(&pcpu->load_lock, flags);
++ now = update_load(data);
++ delta_time = (unsigned int)(now - pcpu->cputime_speedadj_timestamp);
++ cputime_speedadj = pcpu->cputime_speedadj;
++ spin_unlock_irqrestore(&pcpu->load_lock, flags);
++
++ if (WARN_ON_ONCE(!delta_time))
++ goto rearm;
++
++ do_div(cputime_speedadj, delta_time);
++ loadadjfreq = (unsigned int)cputime_speedadj * 100;
++ cpu_load = loadadjfreq / pcpu->target_freq;
++ boosted = tunables->boost_val || now < tunables->boostpulse_endtime;
++
++ if (cpu_load >= tunables->go_hispeed_load || boosted) {
++ if (pcpu->target_freq < tunables->hispeed_freq) {
++ new_freq = tunables->hispeed_freq;
++ } else {
++ new_freq = choose_freq(pcpu, loadadjfreq);
++
++ if (new_freq < tunables->hispeed_freq)
++ new_freq = tunables->hispeed_freq;
++ }
++ } else {
++ new_freq = choose_freq(pcpu, loadadjfreq);
++ }
++
++ if (pcpu->target_freq >= tunables->hispeed_freq &&
++ new_freq > pcpu->target_freq &&
++ now - pcpu->hispeed_validate_time <
++ freq_to_above_hispeed_delay(tunables, pcpu->target_freq)) {
++ trace_cpufreq_interactive_notyet(
++ data, cpu_load, pcpu->target_freq,
++ pcpu->policy->cur, new_freq);
++ goto rearm;
++ }
++
++ pcpu->hispeed_validate_time = now;
++
++ if (cpufreq_frequency_table_target(pcpu->policy, pcpu->freq_table,
++ new_freq, CPUFREQ_RELATION_L,
++ &index))
++ goto rearm;
++
++ new_freq = pcpu->freq_table[index].frequency;
++
++ /*
++ * Do not scale below floor_freq unless we have been at or above the
++ * floor frequency for the minimum sample time since last validated.
++ */
++ if (new_freq < pcpu->floor_freq) {
++ if (now - pcpu->floor_validate_time <
++ tunables->min_sample_time) {
++ trace_cpufreq_interactive_notyet(
++ data, cpu_load, pcpu->target_freq,
++ pcpu->policy->cur, new_freq);
++ goto rearm;
++ }
++ }
++
++ /*
++ * Update the timestamp for checking whether speed has been held at
++ * or above the selected frequency for a minimum of min_sample_time,
++ * if not boosted to hispeed_freq. If boosted to hispeed_freq then we
++ * allow the speed to drop as soon as the boostpulse duration expires
++ * (or the indefinite boost is turned off).
++ */
++
++ if (!boosted || new_freq > tunables->hispeed_freq) {
++ pcpu->floor_freq = new_freq;
++ pcpu->floor_validate_time = now;
++ }
++
++ if (pcpu->target_freq == new_freq) {
++ trace_cpufreq_interactive_already(
++ data, cpu_load, pcpu->target_freq,
++ pcpu->policy->cur, new_freq);
++ goto rearm_if_notmax;
++ }
++
++ trace_cpufreq_interactive_target(data, cpu_load, pcpu->target_freq,
++ pcpu->policy->cur, new_freq);
++
++ pcpu->target_freq = new_freq;
++ spin_lock_irqsave(&speedchange_cpumask_lock, flags);
++ cpumask_set_cpu(data, &speedchange_cpumask);
++ spin_unlock_irqrestore(&speedchange_cpumask_lock, flags);
++ wake_up_process(speedchange_task);
++
++rearm_if_notmax:
++ /*
++ * Already set max speed and don't see a need to change that,
++ * wait until next idle to re-evaluate, don't need timer.
++ */
++ if (pcpu->target_freq == pcpu->policy->max)
++ goto exit;
++
++rearm:
++ if (!timer_pending(&pcpu->cpu_timer))
++ cpufreq_interactive_timer_resched(pcpu);
++
++exit:
++ up_read(&pcpu->enable_sem);
++ return;
++}
++
++static void cpufreq_interactive_idle_start(void)
++{
++ struct cpufreq_interactive_cpuinfo *pcpu =
++ &per_cpu(cpuinfo, smp_processor_id());
++ int pending;
++
++ if (!down_read_trylock(&pcpu->enable_sem))
++ return;
++ if (!pcpu->governor_enabled) {
++ up_read(&pcpu->enable_sem);
++ return;
++ }
++
++ pending = timer_pending(&pcpu->cpu_timer);
++
++ if (pcpu->target_freq != pcpu->policy->min) {
++ /*
++ * Entering idle while not at lowest speed. On some
++ * platforms this can hold the other CPU(s) at that speed
++ * even though the CPU is idle. Set a timer to re-evaluate
++ * speed so this idle CPU doesn't hold the other CPUs above
++ * min indefinitely. This should probably be a quirk of
++ * the CPUFreq driver.
++ */
++ if (!pending)
++ cpufreq_interactive_timer_resched(pcpu);
++ }
++
++ up_read(&pcpu->enable_sem);
++}
++
++static void cpufreq_interactive_idle_end(void)
++{
++ struct cpufreq_interactive_cpuinfo *pcpu =
++ &per_cpu(cpuinfo, smp_processor_id());
++
++ if (!down_read_trylock(&pcpu->enable_sem))
++ return;
++ if (!pcpu->governor_enabled) {
++ up_read(&pcpu->enable_sem);
++ return;
++ }
++
++ /* Arm the timer for 1-2 ticks later if not already. */
++ if (!timer_pending(&pcpu->cpu_timer)) {
++ cpufreq_interactive_timer_resched(pcpu);
++ } else if (time_after_eq(jiffies, pcpu->cpu_timer.expires)) {
++ del_timer(&pcpu->cpu_timer);
++ del_timer(&pcpu->cpu_slack_timer);
++ cpufreq_interactive_timer(smp_processor_id());
++ }
++
++ up_read(&pcpu->enable_sem);
++}
++
++static int cpufreq_interactive_speedchange_task(void *data)
++{
++ unsigned int cpu;
++ cpumask_t tmp_mask;
++ unsigned long flags;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++
++ while (1) {
++ set_current_state(TASK_INTERRUPTIBLE);
++ spin_lock_irqsave(&speedchange_cpumask_lock, flags);
++
++ if (cpumask_empty(&speedchange_cpumask)) {
++ spin_unlock_irqrestore(&speedchange_cpumask_lock,
++ flags);
++ schedule();
++
++ if (kthread_should_stop())
++ break;
++
++ spin_lock_irqsave(&speedchange_cpumask_lock, flags);
++ }
++
++ set_current_state(TASK_RUNNING);
++ tmp_mask = speedchange_cpumask;
++ cpumask_clear(&speedchange_cpumask);
++ spin_unlock_irqrestore(&speedchange_cpumask_lock, flags);
++
++ for_each_cpu(cpu, &tmp_mask) {
++ unsigned int j;
++ unsigned int max_freq = 0;
++
++ pcpu = &per_cpu(cpuinfo, cpu);
++ if (!down_read_trylock(&pcpu->enable_sem))
++ continue;
++ if (!pcpu->governor_enabled) {
++ up_read(&pcpu->enable_sem);
++ continue;
++ }
++
++ for_each_cpu(j, pcpu->policy->cpus) {
++ struct cpufreq_interactive_cpuinfo *pjcpu =
++ &per_cpu(cpuinfo, j);
++
++ if (pjcpu->target_freq > max_freq)
++ max_freq = pjcpu->target_freq;
++ }
++
++ if (max_freq != pcpu->policy->cur)
++ __cpufreq_driver_target(pcpu->policy,
++ max_freq,
++ CPUFREQ_RELATION_H);
++ trace_cpufreq_interactive_setspeed(cpu,
++ pcpu->target_freq,
++ pcpu->policy->cur);
++
++ up_read(&pcpu->enable_sem);
++ }
++ }
++
++ return 0;
++}
++
++static void cpufreq_interactive_boost(void)
++{
++ int i;
++ int anyboost = 0;
++ unsigned long flags;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++ struct cpufreq_interactive_tunables *tunables;
++
++ spin_lock_irqsave(&speedchange_cpumask_lock, flags);
++
++ for_each_online_cpu(i) {
++ pcpu = &per_cpu(cpuinfo, i);
++ tunables = pcpu->policy->governor_data;
++
++ if (pcpu->target_freq < tunables->hispeed_freq) {
++ pcpu->target_freq = tunables->hispeed_freq;
++ cpumask_set_cpu(i, &speedchange_cpumask);
++ pcpu->hispeed_validate_time =
++ ktime_to_us(ktime_get());
++ anyboost = 1;
++ }
++
++ /*
++ * Set floor freq and (re)start timer for when last
++ * validated.
++ */
++
++ pcpu->floor_freq = tunables->hispeed_freq;
++ pcpu->floor_validate_time = ktime_to_us(ktime_get());
++ }
++
++ spin_unlock_irqrestore(&speedchange_cpumask_lock, flags);
++
++ if (anyboost)
++ wake_up_process(speedchange_task);
++}
++
++static int cpufreq_interactive_notifier(
++ struct notifier_block *nb, unsigned long val, void *data)
++{
++ struct cpufreq_freqs *freq = data;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++ int cpu;
++ unsigned long flags;
++
++ if (val == CPUFREQ_POSTCHANGE) {
++ pcpu = &per_cpu(cpuinfo, freq->cpu);
++ if (!down_read_trylock(&pcpu->enable_sem))
++ return 0;
++ if (!pcpu->governor_enabled) {
++ up_read(&pcpu->enable_sem);
++ return 0;
++ }
++
++ for_each_cpu(cpu, pcpu->policy->cpus) {
++ struct cpufreq_interactive_cpuinfo *pjcpu =
++ &per_cpu(cpuinfo, cpu);
++ if (cpu != freq->cpu) {
++ if (!down_read_trylock(&pjcpu->enable_sem))
++ continue;
++ if (!pjcpu->governor_enabled) {
++ up_read(&pjcpu->enable_sem);
++ continue;
++ }
++ }
++ spin_lock_irqsave(&pjcpu->load_lock, flags);
++ update_load(cpu);
++ spin_unlock_irqrestore(&pjcpu->load_lock, flags);
++ if (cpu != freq->cpu)
++ up_read(&pjcpu->enable_sem);
++ }
++
++ up_read(&pcpu->enable_sem);
++ }
++ return 0;
++}
++
++static struct notifier_block cpufreq_notifier_block = {
++ .notifier_call = cpufreq_interactive_notifier,
++};
++
++static unsigned int *get_tokenized_data(const char *buf, int *num_tokens)
++{
++ const char *cp;
++ int i;
++ int ntokens = 1;
++ unsigned int *tokenized_data;
++ int err = -EINVAL;
++
++ cp = buf;
++ while ((cp = strpbrk(cp + 1, " :")))
++ ntokens++;
++
++ if (!(ntokens & 0x1))
++ goto err;
++
++ tokenized_data = kmalloc(ntokens * sizeof(unsigned int), GFP_KERNEL);
++ if (!tokenized_data) {
++ err = -ENOMEM;
++ goto err;
++ }
++
++ cp = buf;
++ i = 0;
++ while (i < ntokens) {
++ if (sscanf(cp, "%u", &tokenized_data[i++]) != 1)
++ goto err_kfree;
++
++ cp = strpbrk(cp, " :");
++ if (!cp)
++ break;
++ cp++;
++ }
++
++ if (i != ntokens)
++ goto err_kfree;
++
++ *num_tokens = ntokens;
++ return tokenized_data;
++
++err_kfree:
++ kfree(tokenized_data);
++err:
++ return ERR_PTR(err);
++}
++
++static ssize_t show_target_loads(
++ struct cpufreq_interactive_tunables *tunables,
++ char *buf)
++{
++ int i;
++ ssize_t ret = 0;
++ unsigned long flags;
++
++ spin_lock_irqsave(&tunables->target_loads_lock, flags);
++
++ for (i = 0; i < tunables->ntarget_loads; i++)
++ ret += sprintf(buf + ret, "%u%s", tunables->target_loads[i],
++ i & 0x1 ? ":" : " ");
++
++ sprintf(buf + ret - 1, "\n");
++ spin_unlock_irqrestore(&tunables->target_loads_lock, flags);
++ return ret;
++}
++
++static ssize_t store_target_loads(
++ struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ntokens;
++ unsigned int *new_target_loads = NULL;
++ unsigned long flags;
++
++ new_target_loads = get_tokenized_data(buf, &ntokens);
++ if (IS_ERR(new_target_loads))
++ return PTR_RET(new_target_loads);
++
++ spin_lock_irqsave(&tunables->target_loads_lock, flags);
++ if (tunables->target_loads != default_target_loads)
++ kfree(tunables->target_loads);
++ tunables->target_loads = new_target_loads;
++ tunables->ntarget_loads = ntokens;
++ spin_unlock_irqrestore(&tunables->target_loads_lock, flags);
++ return count;
++}
++
++static ssize_t show_above_hispeed_delay(
++ struct cpufreq_interactive_tunables *tunables, char *buf)
++{
++ int i;
++ ssize_t ret = 0;
++ unsigned long flags;
++
++ spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags);
++
++ for (i = 0; i < tunables->nabove_hispeed_delay; i++)
++ ret += sprintf(buf + ret, "%u%s",
++ tunables->above_hispeed_delay[i],
++ i & 0x1 ? ":" : " ");
++
++ sprintf(buf + ret - 1, "\n");
++ spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags);
++ return ret;
++}
++
++static ssize_t store_above_hispeed_delay(
++ struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ntokens;
++ unsigned int *new_above_hispeed_delay = NULL;
++ unsigned long flags;
++
++ new_above_hispeed_delay = get_tokenized_data(buf, &ntokens);
++ if (IS_ERR(new_above_hispeed_delay))
++ return PTR_RET(new_above_hispeed_delay);
++
++ spin_lock_irqsave(&tunables->above_hispeed_delay_lock, flags);
++ if (tunables->above_hispeed_delay != default_above_hispeed_delay)
++ kfree(tunables->above_hispeed_delay);
++ tunables->above_hispeed_delay = new_above_hispeed_delay;
++ tunables->nabove_hispeed_delay = ntokens;
++ spin_unlock_irqrestore(&tunables->above_hispeed_delay_lock, flags);
++ return count;
++
++}
++
++static ssize_t show_hispeed_freq(struct cpufreq_interactive_tunables *tunables,
++ char *buf)
++{
++ return sprintf(buf, "%u\n", tunables->hispeed_freq);
++}
++
++static ssize_t store_hispeed_freq(struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ret;
++ long unsigned int val;
++
++ ret = strict_strtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ tunables->hispeed_freq = val;
++ return count;
++}
++
++static ssize_t show_go_hispeed_load(struct cpufreq_interactive_tunables
++ *tunables, char *buf)
++{
++ return sprintf(buf, "%lu\n", tunables->go_hispeed_load);
++}
++
++static ssize_t store_go_hispeed_load(struct cpufreq_interactive_tunables
++ *tunables, const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = strict_strtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ tunables->go_hispeed_load = val;
++ return count;
++}
++
++static ssize_t show_min_sample_time(struct cpufreq_interactive_tunables
++ *tunables, char *buf)
++{
++ return sprintf(buf, "%lu\n", tunables->min_sample_time);
++}
++
++static ssize_t store_min_sample_time(struct cpufreq_interactive_tunables
++ *tunables, const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = strict_strtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ tunables->min_sample_time = val;
++ return count;
++}
++
++static ssize_t show_timer_rate(struct cpufreq_interactive_tunables *tunables,
++ char *buf)
++{
++ return sprintf(buf, "%lu\n", tunables->timer_rate);
++}
++
++static ssize_t store_timer_rate(struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = strict_strtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ tunables->timer_rate = val;
++ return count;
++}
++
++static ssize_t show_timer_slack(struct cpufreq_interactive_tunables *tunables,
++ char *buf)
++{
++ return sprintf(buf, "%d\n", tunables->timer_slack_val);
++}
++
++static ssize_t store_timer_slack(struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = kstrtol(buf, 10, &val);
++ if (ret < 0)
++ return ret;
++
++ tunables->timer_slack_val = val;
++ return count;
++}
++
++static ssize_t show_boost(struct cpufreq_interactive_tunables *tunables,
++ char *buf)
++{
++ return sprintf(buf, "%d\n", tunables->boost_val);
++}
++
++static ssize_t store_boost(struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = kstrtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++
++ tunables->boost_val = val;
++
++ if (tunables->boost_val) {
++ trace_cpufreq_interactive_boost("on");
++ cpufreq_interactive_boost();
++ } else {
++ trace_cpufreq_interactive_unboost("off");
++ }
++
++ return count;
++}
++
++static ssize_t store_boostpulse(struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = kstrtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++
++ tunables->boostpulse_endtime = ktime_to_us(ktime_get()) +
++ tunables->boostpulse_duration_val;
++ trace_cpufreq_interactive_boost("pulse");
++ cpufreq_interactive_boost();
++ return count;
++}
++
++static ssize_t show_boostpulse_duration(struct cpufreq_interactive_tunables
++ *tunables, char *buf)
++{
++ return sprintf(buf, "%d\n", tunables->boostpulse_duration_val);
++}
++
++static ssize_t store_boostpulse_duration(struct cpufreq_interactive_tunables
++ *tunables, const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = kstrtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++
++ tunables->boostpulse_duration_val = val;
++ return count;
++}
++
++static ssize_t show_io_is_busy(struct cpufreq_interactive_tunables *tunables,
++ char *buf)
++{
++ return sprintf(buf, "%u\n", tunables->io_is_busy);
++}
++
++static ssize_t store_io_is_busy(struct cpufreq_interactive_tunables *tunables,
++ const char *buf, size_t count)
++{
++ int ret;
++ unsigned long val;
++
++ ret = kstrtoul(buf, 0, &val);
++ if (ret < 0)
++ return ret;
++ tunables->io_is_busy = val;
++ return count;
++}
++
++/*
++ * Create show/store routines
++ * - sys: One governor instance for complete SYSTEM
++ * - pol: One governor instance per struct cpufreq_policy
++ */
++#define show_gov_pol_sys(file_name) \
++static ssize_t show_##file_name##_gov_sys \
++(struct kobject *kobj, struct attribute *attr, char *buf) \
++{ \
++ return show_##file_name(common_tunables, buf); \
++} \
++ \
++static ssize_t show_##file_name##_gov_pol \
++(struct cpufreq_policy *policy, char *buf) \
++{ \
++ return show_##file_name(policy->governor_data, buf); \
++}
++
++#define store_gov_pol_sys(file_name) \
++static ssize_t store_##file_name##_gov_sys \
++(struct kobject *kobj, struct attribute *attr, const char *buf, \
++ size_t count) \
++{ \
++ return store_##file_name(common_tunables, buf, count); \
++} \
++ \
++static ssize_t store_##file_name##_gov_pol \
++(struct cpufreq_policy *policy, const char *buf, size_t count) \
++{ \
++ return store_##file_name(policy->governor_data, buf, count); \
++}
++
++#define show_store_gov_pol_sys(file_name) \
++show_gov_pol_sys(file_name); \
++store_gov_pol_sys(file_name)
++
++show_store_gov_pol_sys(target_loads);
++show_store_gov_pol_sys(above_hispeed_delay);
++show_store_gov_pol_sys(hispeed_freq);
++show_store_gov_pol_sys(go_hispeed_load);
++show_store_gov_pol_sys(min_sample_time);
++show_store_gov_pol_sys(timer_rate);
++show_store_gov_pol_sys(timer_slack);
++show_store_gov_pol_sys(boost);
++store_gov_pol_sys(boostpulse);
++show_store_gov_pol_sys(boostpulse_duration);
++show_store_gov_pol_sys(io_is_busy);
++
++#define gov_sys_attr_rw(_name) \
++static struct global_attr _name##_gov_sys = \
++__ATTR(_name, 0644, show_##_name##_gov_sys, store_##_name##_gov_sys)
++
++#define gov_pol_attr_rw(_name) \
++static struct freq_attr _name##_gov_pol = \
++__ATTR(_name, 0644, show_##_name##_gov_pol, store_##_name##_gov_pol)
++
++#define gov_sys_pol_attr_rw(_name) \
++ gov_sys_attr_rw(_name); \
++ gov_pol_attr_rw(_name)
++
++gov_sys_pol_attr_rw(target_loads);
++gov_sys_pol_attr_rw(above_hispeed_delay);
++gov_sys_pol_attr_rw(hispeed_freq);
++gov_sys_pol_attr_rw(go_hispeed_load);
++gov_sys_pol_attr_rw(min_sample_time);
++gov_sys_pol_attr_rw(timer_rate);
++gov_sys_pol_attr_rw(timer_slack);
++gov_sys_pol_attr_rw(boost);
++gov_sys_pol_attr_rw(boostpulse_duration);
++gov_sys_pol_attr_rw(io_is_busy);
++
++static struct global_attr boostpulse_gov_sys =
++ __ATTR(boostpulse, 0200, NULL, store_boostpulse_gov_sys);
++
++static struct freq_attr boostpulse_gov_pol =
++ __ATTR(boostpulse, 0200, NULL, store_boostpulse_gov_pol);
++
++/* One Governor instance for entire system */
++static struct attribute *interactive_attributes_gov_sys[] = {
++ &target_loads_gov_sys.attr,
++ &above_hispeed_delay_gov_sys.attr,
++ &hispeed_freq_gov_sys.attr,
++ &go_hispeed_load_gov_sys.attr,
++ &min_sample_time_gov_sys.attr,
++ &timer_rate_gov_sys.attr,
++ &timer_slack_gov_sys.attr,
++ &boost_gov_sys.attr,
++ &boostpulse_gov_sys.attr,
++ &boostpulse_duration_gov_sys.attr,
++ &io_is_busy_gov_sys.attr,
++ NULL,
++};
++
++static struct attribute_group interactive_attr_group_gov_sys = {
++ .attrs = interactive_attributes_gov_sys,
++ .name = "interactive",
++};
++
++/* Per policy governor instance */
++static struct attribute *interactive_attributes_gov_pol[] = {
++ &target_loads_gov_pol.attr,
++ &above_hispeed_delay_gov_pol.attr,
++ &hispeed_freq_gov_pol.attr,
++ &go_hispeed_load_gov_pol.attr,
++ &min_sample_time_gov_pol.attr,
++ &timer_rate_gov_pol.attr,
++ &timer_slack_gov_pol.attr,
++ &boost_gov_pol.attr,
++ &boostpulse_gov_pol.attr,
++ &boostpulse_duration_gov_pol.attr,
++ &io_is_busy_gov_pol.attr,
++ NULL,
++};
++
++static struct attribute_group interactive_attr_group_gov_pol = {
++ .attrs = interactive_attributes_gov_pol,
++ .name = "interactive",
++};
++
++static struct attribute_group *get_sysfs_attr(void)
++{
++ if (have_governor_per_policy())
++ return &interactive_attr_group_gov_pol;
++ else
++ return &interactive_attr_group_gov_sys;
++}
++
++static int cpufreq_interactive_idle_notifier(struct notifier_block *nb,
++ unsigned long val,
++ void *data)
++{
++ switch (val) {
++ case IDLE_START:
++ cpufreq_interactive_idle_start();
++ break;
++ case IDLE_END:
++ cpufreq_interactive_idle_end();
++ break;
++ }
++
++ return 0;
++}
++
++static struct notifier_block cpufreq_interactive_idle_nb = {
++ .notifier_call = cpufreq_interactive_idle_notifier,
++};
++
++static int cpufreq_governor_interactive(struct cpufreq_policy *policy,
++ unsigned int event)
++{
++ int rc;
++ unsigned int j;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++ struct cpufreq_frequency_table *freq_table;
++ struct cpufreq_interactive_tunables *tunables;
++
++ if (have_governor_per_policy())
++ tunables = policy->governor_data;
++ else
++ tunables = common_tunables;
++
++ WARN_ON(!tunables && (event != CPUFREQ_GOV_POLICY_INIT));
++
++ switch (event) {
++ case CPUFREQ_GOV_POLICY_INIT:
++ if (have_governor_per_policy()) {
++ WARN_ON(tunables);
++ } else if (tunables) {
++ tunables->usage_count++;
++ policy->governor_data = tunables;
++ return 0;
++ }
++
++ tunables = kzalloc(sizeof(*tunables), GFP_KERNEL);
++ if (!tunables) {
++ pr_err("%s: POLICY_INIT: kzalloc failed\n", __func__);
++ return -ENOMEM;
++ }
++
++ tunables->usage_count = 1;
++ tunables->above_hispeed_delay = default_above_hispeed_delay;
++ tunables->nabove_hispeed_delay =
++ ARRAY_SIZE(default_above_hispeed_delay);
++ tunables->go_hispeed_load = DEFAULT_GO_HISPEED_LOAD;
++ tunables->target_loads = default_target_loads;
++ tunables->ntarget_loads = ARRAY_SIZE(default_target_loads);
++ tunables->min_sample_time = DEFAULT_MIN_SAMPLE_TIME;
++ tunables->timer_rate = DEFAULT_TIMER_RATE;
++ tunables->boostpulse_duration_val = DEFAULT_MIN_SAMPLE_TIME;
++ tunables->timer_slack_val = DEFAULT_TIMER_SLACK;
++
++ spin_lock_init(&tunables->target_loads_lock);
++ spin_lock_init(&tunables->above_hispeed_delay_lock);
++
++ policy->governor_data = tunables;
++ if (!have_governor_per_policy()) {
++ common_tunables = tunables;
++ WARN_ON(cpufreq_get_global_kobject());
++ }
++
++ rc = sysfs_create_group(get_governor_parent_kobj(policy),
++ get_sysfs_attr());
++ if (rc) {
++ kfree(tunables);
++ policy->governor_data = NULL;
++ if (!have_governor_per_policy())
++ common_tunables = NULL;
++ return rc;
++ }
++
++ if (!policy->governor->initialized) {
++ idle_notifier_register(&cpufreq_interactive_idle_nb);
++ cpufreq_register_notifier(&cpufreq_notifier_block,
++ CPUFREQ_TRANSITION_NOTIFIER);
++ }
++
++ break;
++
++ case CPUFREQ_GOV_POLICY_EXIT:
++ if (!--tunables->usage_count) {
++ if (policy->governor->initialized == 1) {
++ cpufreq_unregister_notifier(&cpufreq_notifier_block,
++ CPUFREQ_TRANSITION_NOTIFIER);
++ idle_notifier_unregister(&cpufreq_interactive_idle_nb);
++ }
++
++ sysfs_remove_group(get_governor_parent_kobj(policy),
++ get_sysfs_attr());
++ kfree(tunables);
++ common_tunables = NULL;
++ }
++
++ policy->governor_data = NULL;
++ break;
++
++ case CPUFREQ_GOV_START:
++ mutex_lock(&gov_lock);
++
++ freq_table = cpufreq_frequency_get_table(policy->cpu);
++ if (!tunables->hispeed_freq)
++ tunables->hispeed_freq = policy->max;
++
++ for_each_cpu(j, policy->cpus) {
++ pcpu = &per_cpu(cpuinfo, j);
++ pcpu->policy = policy;
++ pcpu->target_freq = policy->cur;
++ pcpu->freq_table = freq_table;
++ pcpu->floor_freq = pcpu->target_freq;
++ pcpu->floor_validate_time =
++ ktime_to_us(ktime_get());
++ pcpu->hispeed_validate_time =
++ pcpu->floor_validate_time;
++ down_write(&pcpu->enable_sem);
++ del_timer_sync(&pcpu->cpu_timer);
++ del_timer_sync(&pcpu->cpu_slack_timer);
++ cpufreq_interactive_timer_start(tunables, j);
++ pcpu->governor_enabled = 1;
++ up_write(&pcpu->enable_sem);
++ }
++
++ mutex_unlock(&gov_lock);
++ break;
++
++ case CPUFREQ_GOV_STOP:
++ mutex_lock(&gov_lock);
++ for_each_cpu(j, policy->cpus) {
++ pcpu = &per_cpu(cpuinfo, j);
++ down_write(&pcpu->enable_sem);
++ pcpu->governor_enabled = 0;
++ del_timer_sync(&pcpu->cpu_timer);
++ del_timer_sync(&pcpu->cpu_slack_timer);
++ up_write(&pcpu->enable_sem);
++ }
++
++ mutex_unlock(&gov_lock);
++ break;
++
++ case CPUFREQ_GOV_LIMITS:
++ if (policy->max < policy->cur)
++ __cpufreq_driver_target(policy,
++ policy->max, CPUFREQ_RELATION_H);
++ else if (policy->min > policy->cur)
++ __cpufreq_driver_target(policy,
++ policy->min, CPUFREQ_RELATION_L);
++ for_each_cpu(j, policy->cpus) {
++ pcpu = &per_cpu(cpuinfo, j);
++
++ /* hold write semaphore to avoid race */
++ down_write(&pcpu->enable_sem);
++ if (pcpu->governor_enabled == 0) {
++ up_write(&pcpu->enable_sem);
++ continue;
++ }
++
++ /* update target_freq firstly */
++ if (policy->max < pcpu->target_freq)
++ pcpu->target_freq = policy->max;
++ else if (policy->min > pcpu->target_freq)
++ pcpu->target_freq = policy->min;
++
++ /* Reschedule timer.
++ * Delete the timers, else the timer callback may
++ * return without re-arm the timer when failed
++ * acquire the semaphore. This race may cause timer
++ * stopped unexpectedly.
++ */
++ del_timer_sync(&pcpu->cpu_timer);
++ del_timer_sync(&pcpu->cpu_slack_timer);
++ cpufreq_interactive_timer_start(tunables, j);
++ up_write(&pcpu->enable_sem);
++ }
++ break;
++ }
++ return 0;
++}
++
++#ifndef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE
++static
++#endif
++struct cpufreq_governor cpufreq_gov_interactive = {
++ .name = "interactive",
++ .governor = cpufreq_governor_interactive,
++ .max_transition_latency = 10000000,
++ .owner = THIS_MODULE,
++};
++
++static void cpufreq_interactive_nop_timer(unsigned long data)
++{
++}
++
++static int __init cpufreq_interactive_init(void)
++{
++ unsigned int i;
++ struct cpufreq_interactive_cpuinfo *pcpu;
++ struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 };
++
++ /* Initalize per-cpu timers */
++ for_each_possible_cpu(i) {
++ pcpu = &per_cpu(cpuinfo, i);
++ init_timer_deferrable(&pcpu->cpu_timer);
++ pcpu->cpu_timer.function = cpufreq_interactive_timer;
++ pcpu->cpu_timer.data = i;
++ init_timer(&pcpu->cpu_slack_timer);
++ pcpu->cpu_slack_timer.function = cpufreq_interactive_nop_timer;
++ spin_lock_init(&pcpu->load_lock);
++ init_rwsem(&pcpu->enable_sem);
++ }
++
++ spin_lock_init(&speedchange_cpumask_lock);
++ mutex_init(&gov_lock);
++ speedchange_task =
++ kthread_create(cpufreq_interactive_speedchange_task, NULL,
++ "cfinteractive");
++ if (IS_ERR(speedchange_task))
++ return PTR_ERR(speedchange_task);
++
++ sched_setscheduler_nocheck(speedchange_task, SCHED_FIFO, &param);
++ get_task_struct(speedchange_task);
++
++ /* NB: wake up so the thread does not look hung to the freezer */
++ wake_up_process(speedchange_task);
++
++ return cpufreq_register_governor(&cpufreq_gov_interactive);
++}
++
++#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE
++fs_initcall(cpufreq_interactive_init);
++#else
++module_init(cpufreq_interactive_init);
++#endif
++
++static void __exit cpufreq_interactive_exit(void)
++{
++ cpufreq_unregister_governor(&cpufreq_gov_interactive);
++ kthread_stop(speedchange_task);
++ put_task_struct(speedchange_task);
++}
++
++module_exit(cpufreq_interactive_exit);
++
++MODULE_AUTHOR("Mike Chan <mike@android.com>");
++MODULE_DESCRIPTION("'cpufreq_interactive' - A cpufreq governor for "
++ "Latency sensitive workloads");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/cpufreq/cpufreq_ondemand.c linux-3.14.72/drivers/cpufreq/cpufreq_ondemand.c
+--- linux-3.14.72.orig/drivers/cpufreq/cpufreq_ondemand.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/cpufreq/cpufreq_ondemand.c 2016-06-19 22:11:55.113152605 +0200
+@@ -50,7 +50,8 @@
+ * efficient idling at a higher frequency/voltage is.
+ * Pavel Machek says this is not so for various generations of AMD and old
+ * Intel systems.
+- * Mike Chan (android.com) claims this is also not true for ARM.
++ * ARM systems v7 and later generally good idle power management as well, so
++ * treat them the same.
+ * Because of this, whitelist specific known (series) of CPUs by default, and
+ * leave all others up to the user.
+ */
+@@ -65,6 +66,9 @@
+ boot_cpu_data.x86_model >= 15)
+ return 1;
+ #endif
++#if defined(CONFIG_ARM) && defined(CPU_V7)
++ return 1;
++#endif
+ return 0;
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/cpufreq/imx6q-cpufreq.c linux-3.14.72/drivers/cpufreq/imx6q-cpufreq.c
+--- linux-3.14.72.orig/drivers/cpufreq/imx6q-cpufreq.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/cpufreq/imx6q-cpufreq.c 2016-06-19 22:11:55.113152605 +0200
+@@ -1,11 +1,12 @@
+ /*
+- * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
++#include <linux/busfreq-imx6.h>
+ #include <linux/clk.h>
+ #include <linux/cpu.h>
+ #include <linux/cpufreq.h>
+@@ -16,10 +17,12 @@
+ #include <linux/pm_opp.h>
+ #include <linux/platform_device.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/suspend.h>
+
+ #define PU_SOC_VOLTAGE_NORMAL 1250000
+ #define PU_SOC_VOLTAGE_HIGH 1275000
+ #define FREQ_1P2_GHZ 1200000000
++#define FREQ_396_MHZ 396000
+
+ static struct regulator *arm_reg;
+ static struct regulator *pu_reg;
+@@ -30,11 +33,14 @@
+ static struct clk *pll1_sw_clk;
+ static struct clk *step_clk;
+ static struct clk *pll2_pfd2_396m_clk;
++static struct clk *pll1_bypass;
++static struct clk *pll1_bypass_src;
++static struct clk *pll1;
+
+ static struct device *cpu_dev;
+ static struct cpufreq_frequency_table *freq_table;
+ static unsigned int transition_latency;
+-
++static struct mutex set_cpufreq_lock;
+ static u32 *imx6_soc_volt;
+ static u32 soc_opp_count;
+
+@@ -44,6 +50,9 @@
+ unsigned long freq_hz, volt, volt_old;
+ unsigned int old_freq, new_freq;
+ int ret;
++ int tol = 25000; /* 25mv tollerance */
++
++ mutex_lock(&set_cpufreq_lock);
+
+ new_freq = freq_table[index].frequency;
+ freq_hz = new_freq * 1000;
+@@ -54,6 +63,7 @@
+ if (IS_ERR(opp)) {
+ rcu_read_unlock();
+ dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
++ mutex_unlock(&set_cpufreq_lock);
+ return PTR_ERR(opp);
+ }
+
+@@ -61,26 +71,39 @@
+ rcu_read_unlock();
+ volt_old = regulator_get_voltage(arm_reg);
+
+- dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
++ dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld/%d mV\n",
+ old_freq / 1000, volt_old / 1000,
+- new_freq / 1000, volt / 1000);
++ new_freq / 1000, volt / 1000, imx6_soc_volt[index] / 1000);
++ /*
++ * CPU freq is increasing, so need to ensure
++ * that bus frequency is increased too.
++ */
++ if (old_freq <= FREQ_396_MHZ && new_freq > FREQ_396_MHZ)
++ request_bus_freq(BUS_FREQ_HIGH);
+
+ /* scaling up? scale voltage before frequency */
+ if (new_freq > old_freq) {
+- ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
+- if (ret) {
+- dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
+- return ret;
++ if (!IS_ERR(pu_reg) && regulator_is_enabled(pu_reg)) {
++ ret = regulator_set_voltage_tol(pu_reg,
++ imx6_soc_volt[index], tol);
++ if (ret) {
++ dev_err(cpu_dev,
++ "failed to scale vddpu up: %d\n", ret);
++ mutex_unlock(&set_cpufreq_lock);
++ return ret;
++ }
+ }
+- ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
++ ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], tol);
+ if (ret) {
+ dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
++ mutex_unlock(&set_cpufreq_lock);
+ return ret;
+ }
+- ret = regulator_set_voltage_tol(arm_reg, volt, 0);
++ ret = regulator_set_voltage_tol(arm_reg, volt, tol);
+ if (ret) {
+ dev_err(cpu_dev,
+ "failed to scale vddarm up: %d\n", ret);
++ mutex_unlock(&set_cpufreq_lock);
+ return ret;
+ }
+ }
+@@ -97,45 +120,79 @@
+ clk_set_parent(step_clk, pll2_pfd2_396m_clk);
+ clk_set_parent(pll1_sw_clk, step_clk);
+ if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
+- clk_set_rate(pll1_sys_clk, new_freq * 1000);
++ clk_set_rate(pll1, new_freq * 1000);
++ /*
++ * Ensure pll1_bypass is set back to pll1.
++ */
++ clk_set_parent(pll1_bypass, pll1);
+ clk_set_parent(pll1_sw_clk, pll1_sys_clk);
+- }
++ } else
++ /*
++ * Need to ensure that PLL1 is bypassed and enabled
++ * before ARM-PODF is set.
++ */
++ clk_set_parent(pll1_bypass, pll1_bypass_src);
++
+
+ /* Ensure the arm clock divider is what we expect */
+ ret = clk_set_rate(arm_clk, new_freq * 1000);
+ if (ret) {
+ dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
+- regulator_set_voltage_tol(arm_reg, volt_old, 0);
++ regulator_set_voltage_tol(arm_reg, volt_old, tol);
++ mutex_unlock(&set_cpufreq_lock);
+ return ret;
+ }
+
+ /* scaling down? scale voltage after frequency */
+ if (new_freq < old_freq) {
+- ret = regulator_set_voltage_tol(arm_reg, volt, 0);
++ ret = regulator_set_voltage_tol(arm_reg, volt, tol);
+ if (ret) {
+ dev_warn(cpu_dev,
+ "failed to scale vddarm down: %d\n", ret);
+ ret = 0;
+ }
+- ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
++ ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], tol);
+ if (ret) {
+ dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
+ ret = 0;
+ }
+- ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
+- if (ret) {
+- dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
+- ret = 0;
++ if (!IS_ERR(pu_reg) && regulator_is_enabled(pu_reg)) {
++ ret = regulator_set_voltage_tol(pu_reg,
++ imx6_soc_volt[index], tol);
++ if (ret) {
++ dev_warn(cpu_dev,
++ "failed to scale vddpu down: %d\n",
++ ret);
++ ret = 0;
++ }
+ }
+ }
++ /*
++ * If CPU is dropped to the lowest level, release the need
++ * for a high bus frequency.
++ */
++ if (old_freq > FREQ_396_MHZ && new_freq <= FREQ_396_MHZ)
++ release_bus_freq(BUS_FREQ_HIGH);
+
++ mutex_unlock(&set_cpufreq_lock);
+ return 0;
+ }
+
+ static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
+ {
++ int ret;
++
+ policy->clk = arm_clk;
+- return cpufreq_generic_init(policy, freq_table, transition_latency);
++ policy->cur = clk_get_rate(arm_clk) / 1000;
++
++ ret = cpufreq_generic_init(policy, freq_table, transition_latency);
++ if (ret) {
++ dev_err(cpu_dev, "imx6 cpufreq init failed!\n");
++ return ret;
++ }
++ if (policy->cur > FREQ_396_MHZ)
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
+ }
+
+ static struct cpufreq_driver imx6q_cpufreq_driver = {
+@@ -149,6 +206,40 @@
+ .attr = cpufreq_generic_attr,
+ };
+
++static int imx6_cpufreq_pm_notify(struct notifier_block *nb,
++ unsigned long event, void *dummy)
++{
++ struct cpufreq_policy *data = cpufreq_cpu_get(0);
++ static u32 cpufreq_policy_min_pre_suspend;
++
++ /*
++ * During suspend/resume, When cpufreq driver try to increase
++ * voltage/freq, it needs to control I2C/SPI to communicate
++ * with external PMIC to adjust voltage, but these I2C/SPI
++ * devices may be already suspended, to avoid such scenario,
++ * we just increase cpufreq to highest setpoint before suspend.
++ */
++ switch (event) {
++ case PM_SUSPEND_PREPARE:
++ cpufreq_policy_min_pre_suspend = data->user_policy.min;
++ data->user_policy.min = data->user_policy.max;
++ break;
++ case PM_POST_SUSPEND:
++ data->user_policy.min = cpufreq_policy_min_pre_suspend;
++ break;
++ default:
++ break;
++ }
++
++ cpufreq_update_policy(0);
++
++ return NOTIFY_OK;
++}
++
++static struct notifier_block imx6_cpufreq_pm_notifier = {
++ .notifier_call = imx6_cpufreq_pm_notify,
++};
++
+ static int imx6q_cpufreq_probe(struct platform_device *pdev)
+ {
+ struct device_node *np;
+@@ -157,7 +248,7 @@
+ int num, ret;
+ const struct property *prop;
+ const __be32 *val;
+- u32 nr, i, j;
++ u32 nr, j, i = 0;
+
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev) {
+@@ -176,23 +267,39 @@
+ pll1_sw_clk = devm_clk_get(cpu_dev, "pll1_sw");
+ step_clk = devm_clk_get(cpu_dev, "step");
+ pll2_pfd2_396m_clk = devm_clk_get(cpu_dev, "pll2_pfd2_396m");
++ pll1_bypass = devm_clk_get(cpu_dev, "pll1_bypass");
++ pll1 = devm_clk_get(cpu_dev, "pll1");
++ pll1_bypass_src = devm_clk_get(cpu_dev, "pll1_bypass_src");
++
+ if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
+- IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
++ IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk) ||
++ IS_ERR(pll1_bypass) || IS_ERR(pll1) ||
++ IS_ERR(pll1_bypass_src)) {
+ dev_err(cpu_dev, "failed to get clocks\n");
+ ret = -ENOENT;
+ goto put_node;
+ }
+
+- arm_reg = devm_regulator_get(cpu_dev, "arm");
+- pu_reg = devm_regulator_get(cpu_dev, "pu");
+- soc_reg = devm_regulator_get(cpu_dev, "soc");
+- if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) {
++ arm_reg = devm_regulator_get_optional(cpu_dev, "arm");
++ pu_reg = devm_regulator_get_optional(cpu_dev, "pu");
++ soc_reg = devm_regulator_get_optional(cpu_dev, "soc");
++ if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
+ dev_err(cpu_dev, "failed to get regulators\n");
+ ret = -ENOENT;
+ goto put_node;
+ }
+
+ /*
++ * soc_reg sync with arm_reg if arm shares the same regulator
++ * with soc. Otherwise, regulator common framework will refuse to update
++ * this consumer's voltage right now while another consumer voltage
++ * still keep in old one. For example, imx6sx-sdb with pfuze200 in
++ * ldo-bypass mode.
++ */
++ of_property_read_u32(np, "fsl,arm-soc-shared", &i);
++ if (i == 1)
++ soc_reg = arm_reg;
++ /*
+ * We expect an OPP table supplied by platform.
+ * Just, incase the platform did not supply the OPP
+ * table, it will try to get it.
+@@ -245,6 +352,12 @@
+ unsigned long volt = be32_to_cpup(val++);
+ if (freq_table[j].frequency == freq) {
+ imx6_soc_volt[soc_opp_count++] = volt;
++#ifdef CONFIG_MX6_VPU_352M
++ if (freq == 792000) {
++ pr_info("increase SOC/PU voltage for VPU352MHz\n");
++ imx6_soc_volt[soc_opp_count - 1] = 1250000;
++ }
++#endif
+ break;
+ }
+ }
+@@ -270,9 +383,12 @@
+ ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
+ if (ret > 0)
+ transition_latency += ret * 1000;
+- ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
+- if (ret > 0)
+- transition_latency += ret * 1000;
++ if (!IS_ERR(pu_reg)) {
++ ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0],
++ imx6_soc_volt[num - 1]);
++ if (ret > 0)
++ transition_latency += ret * 1000;
++ }
+
+ /*
+ * OPP is maintained in order of increasing frequency, and
+@@ -291,6 +407,9 @@
+ if (ret > 0)
+ transition_latency += ret * 1000;
+
++ mutex_init(&set_cpufreq_lock);
++ register_pm_notifier(&imx6_cpufreq_pm_notifier);
++
+ ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
+ if (ret) {
+ dev_err(cpu_dev, "failed register driver: %d\n", ret);
+diff -Nur linux-3.14.72.orig/drivers/cpufreq/Kconfig linux-3.14.72/drivers/cpufreq/Kconfig
+--- linux-3.14.72.orig/drivers/cpufreq/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/cpufreq/Kconfig 2016-06-19 22:11:55.113152605 +0200
+@@ -102,6 +102,16 @@
+ Be aware that not all cpufreq drivers support the conservative
+ governor. If unsure have a look at the help section of the
+ driver. Fallback governor will be the performance governor.
++
++config CPU_FREQ_DEFAULT_GOV_INTERACTIVE
++ bool "interactive"
++ select CPU_FREQ_GOV_INTERACTIVE
++ help
++ Use the CPUFreq governor 'interactive' as default. This allows
++ you to get a full dynamic cpu frequency capable system by simply
++ loading your cpufreq low-level hardware driver, using the
++ 'interactive' governor for latency-sensitive workloads.
++
+ endchoice
+
+ config CPU_FREQ_GOV_PERFORMANCE
+@@ -159,6 +169,19 @@
+
+ If in doubt, say N.
+
++config CPU_FREQ_GOV_INTERACTIVE
++ tristate "'interactive' cpufreq policy governor"
++ help
++ 'interactive' - This driver adds a dynamic cpufreq policy governor
++ designed for latency-sensitive workloads.
++ This governor attempts to reduce the latency of clock
++ increases so that the system is more responsive to
++ interactive workloads.
++ To compile this driver as a module, choose M here: the
++ module will be called cpufreq_interactive.
++ For details, take a look at linux/Documentation/cpu-freq.
++ If in doubt, say N.
++
+ config CPU_FREQ_GOV_CONSERVATIVE
+ tristate "'conservative' cpufreq governor"
+ depends on CPU_FREQ
+diff -Nur linux-3.14.72.orig/drivers/cpufreq/Makefile linux-3.14.72/drivers/cpufreq/Makefile
+--- linux-3.14.72.orig/drivers/cpufreq/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/cpufreq/Makefile 2016-06-19 22:11:55.113152605 +0200
+@@ -9,6 +9,7 @@
+ obj-$(CONFIG_CPU_FREQ_GOV_USERSPACE) += cpufreq_userspace.o
+ obj-$(CONFIG_CPU_FREQ_GOV_ONDEMAND) += cpufreq_ondemand.o
+ obj-$(CONFIG_CPU_FREQ_GOV_CONSERVATIVE) += cpufreq_conservative.o
++obj-$(CONFIG_CPU_FREQ_GOV_INTERACTIVE) += cpufreq_interactive.o
+ obj-$(CONFIG_CPU_FREQ_GOV_COMMON) += cpufreq_governor.o
+
+ obj-$(CONFIG_GENERIC_CPUFREQ_CPU0) += cpufreq-cpu0.o
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/caamalg.c linux-3.14.72/drivers/crypto/caam/caamalg.c
+--- linux-3.14.72.orig/drivers/crypto/caam/caamalg.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/caamalg.c 2016-06-19 22:11:55.113152605 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for crypto API
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2015 Freescale Semiconductor, Inc.
+ *
+ * Based on talitos crypto API driver.
+ *
+@@ -53,6 +53,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include <linux/string.h>
+
+ /*
+ * crypto alg
+@@ -287,6 +288,8 @@
+ desc_bytes(desc), 1);
+ #endif
+
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_enc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
+ /*
+ * Job Descriptor and Shared Descriptors
+ * must all fit into the 64-word Descriptor h/w Buffer
+@@ -354,6 +357,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_dec_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
+
+ /*
+ * Job Descriptor and Shared Descriptors
+@@ -437,6 +442,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_givenc_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return 0;
+ }
+@@ -505,11 +512,15 @@
+ dev_err(jrdev, "unable to map key i/o memory\n");
+ return -ENOMEM;
+ }
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+ ctx->split_key_pad_len + keys.enckeylen, 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->key_dma,
++ ctx->split_key_pad_len + keys.enckeylen,
++ DMA_TO_DEVICE);
+
+ ctx->enckeylen = keys.enckeylen;
+
+@@ -548,6 +559,7 @@
+ return -ENOMEM;
+ }
+ ctx->enckeylen = keylen;
++ dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE);
+
+ /* ablkcipher_encrypt shared descriptor */
+ desc = ctx->sh_desc_enc;
+@@ -566,10 +578,15 @@
+ /* Propagate errors from shared to job descriptor */
+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+
+- /* Load iv */
+- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+- LDST_CLASS_1_CCB | tfm->ivsize);
+-
++ /* load IV */
++ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize |
++ (16 << LDST_OFFSET_SHIFT));
++ } else {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize);
++ }
+ /* Load operation */
+ append_operation(desc, ctx->class1_alg_type |
+ OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
+@@ -590,6 +607,9 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
+ /* ablkcipher_decrypt shared descriptor */
+ desc = ctx->sh_desc_dec;
+
+@@ -610,11 +630,20 @@
+ set_jump_tgt_here(desc, jump_cmd);
+
+ /* load IV */
+- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
+- LDST_CLASS_1_CCB | tfm->ivsize);
++ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize |
++ (16 << LDST_OFFSET_SHIFT));
+
+- /* Choose operation */
+- append_dec_op1(desc, ctx->class1_alg_type);
++ append_operation(desc, ctx->class1_alg_type |
++ OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT);
++ } else {
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | tfm->ivsize);
++
++ /* Choose operation */
++ append_dec_op1(desc, ctx->class1_alg_type);
++ }
+
+ /* Perform operation */
+ ablkcipher_append_src_dst(desc);
+@@ -636,6 +665,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return ret;
+ }
+@@ -1153,7 +1184,7 @@
+ }
+
+ sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
+- DMA_TO_DEVICE, assoc_chained);
++ DMA_BIDIRECTIONAL, assoc_chained);
+ if (likely(req->src == req->dst)) {
+ sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+ DMA_BIDIRECTIONAL, src_chained);
+@@ -1177,9 +1208,10 @@
+ sec4_sg_len += dst_nents;
+
+ sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1220,6 +1252,8 @@
+ sg_to_sec4_sg_last(req->dst, dst_nents,
+ edesc->sec4_sg + sec4_sg_index, 0);
+ }
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ return edesc;
+ }
+@@ -1334,7 +1368,7 @@
+ &dst_chained);
+
+ sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
+- DMA_TO_DEVICE, assoc_chained);
++ DMA_BIDIRECTIONAL, assoc_chained);
+ if (likely(req->src == req->dst)) {
+ sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
+ DMA_BIDIRECTIONAL, src_chained);
+@@ -1367,8 +1401,10 @@
+
+ sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
+
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
++
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1410,6 +1446,8 @@
+ sg_to_sec4_sg_last(req->dst, dst_nents,
+ edesc->sec4_sg + sec4_sg_index, 0);
+ }
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
+
+ return edesc;
+ }
+@@ -1501,6 +1539,7 @@
+ * If so, include it. If not, create scatterlist.
+ */
+ iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE);
+ if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
+ iv_contig = true;
+ else
+@@ -1509,7 +1548,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
++ edesc = kzalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1539,8 +1578,12 @@
+
+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+ sec4_sg_bytes, DMA_TO_DEVICE);
++
+ edesc->iv_dma = iv_dma;
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
+@@ -2004,6 +2047,70 @@
+ },
+ /* ablkcipher descriptor */
+ {
++ .name = "ecb(des)",
++ .driver_name = "ecb-des-caam",
++ .blocksize = DES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = DES_KEY_SIZE,
++ .max_keysize = DES_KEY_SIZE,
++ .ivsize = DES_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_ECB,
++ },
++ {
++ .name = "ecb(arc4)",
++ .driver_name = "ecb-arc4-caam",
++ .blocksize = ARC4_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = ARC4_MIN_KEY_SIZE,
++ .max_keysize = ARC4_MAX_KEY_SIZE,
++ .ivsize = ARC4_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_ARC4 | OP_ALG_AAI_ECB
++ },
++ {
++ .name = "ecb(aes)",
++ .driver_name = "ecb-aes-caam",
++ .blocksize = AES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB,
++ },
++ {
++ .name = "ctr(aes)",
++ .driver_name = "ctr-aes-caam",
++ .blocksize = AES_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128,
++ },
++ {
+ .name = "cbc(aes)",
+ .driver_name = "cbc-aes-caam",
+ .blocksize = AES_BLOCK_SIZE,
+@@ -2020,6 +2127,22 @@
+ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
+ },
+ {
++ .name = "ecb(des3_ede)",
++ .driver_name = "ecb-des3-caam",
++ .blocksize = DES3_EDE_BLOCK_SIZE,
++ .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
++ .template_ablkcipher = {
++ .setkey = ablkcipher_setkey,
++ .encrypt = ablkcipher_encrypt,
++ .decrypt = ablkcipher_decrypt,
++ .geniv = "eseqiv",
++ .min_keysize = DES3_EDE_KEY_SIZE,
++ .max_keysize = DES3_EDE_KEY_SIZE,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ },
++ .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_ECB,
++ },
++ {
+ .name = "cbc(des3_ede)",
+ .driver_name = "cbc-3des-caam",
+ .blocksize = DES3_EDE_BLOCK_SIZE,
+@@ -2142,8 +2265,12 @@
+ alg->cra_blocksize = template->blocksize;
+ alg->cra_alignmask = 0;
+ alg->cra_ctxsize = sizeof(struct caam_ctx);
+- alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
+- template->type;
++ alg->cra_flags = CRYPTO_ALG_ASYNC | template->type;
++
++#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY
++ alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
++#endif
++
+ switch (template->type) {
+ case CRYPTO_ALG_TYPE_ABLKCIPHER:
+ alg->cra_type = &crypto_ablkcipher_type;
+@@ -2164,14 +2291,83 @@
+
+ static int __init caam_algapi_init(void)
+ {
+- int i = 0, err = 0;
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++ struct device *ctrldev;
++ struct caam_drv_private *priv;
++ int i = 0, err = 0, md_limit = 0;
++ int des_inst, aes_inst, md_inst;
++ u64 cha_inst;
++
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev) {
++ of_node_put(dev_node);
++ return -ENODEV;
++ }
++
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++
++ /*
++ * If priv is NULL, it's probably because the caam driver wasn't
++ * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
++ */
++ if (!priv) {
++ of_node_put(dev_node);
++ return -ENODEV;
++ }
+
+ INIT_LIST_HEAD(&alg_list);
+
+- /* register crypto algorithms the device supports */
++ /*
++ * register crypto algorithms the device supports
++ * first, detect presence of DES, AES, and MD blocks. If MD present,
++ * determine limit of supported digest size
++ */
++ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num);
++ des_inst = (cha_inst & CHA_ID_DES_MASK) >> CHA_ID_DES_SHIFT;
++ aes_inst = (cha_inst & CHA_ID_AES_MASK) >> CHA_ID_AES_SHIFT;
++ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT;
++ if (md_inst) {
++ md_limit = SHA512_DIGEST_SIZE;
++ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK)
++ == CHA_ID_MD_LP256) /* LP256 limits digest size */
++ md_limit = SHA256_DIGEST_SIZE;
++ }
++
+ for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
+- /* TODO: check if h/w supports alg */
+ struct caam_crypto_alg *t_alg;
++ bool done = false;
++
++authencesn:
++ /*
++ * All registrable algs in this module require a blockcipher
++ * All aead algs require message digests, so check them for
++ * instantiation and size.
++ */
++ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD) {
++ /* If no MD instantiated, or MD too small, skip */
++ if ((!md_inst) ||
++ (driver_algs[i].template_aead.maxauthsize >
++ md_limit))
++ continue;
++ }
++ /* If DES alg, and CHA not instantiated, skip */
++ if ((driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_3DES) ||
++ (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_DES))
++ if (!des_inst)
++ continue;
++ /* If AES alg, and CHA not instantiated, skip */
++ if (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_AES)
++ if (!aes_inst)
++ continue;
+
+ t_alg = caam_alg_alloc(&driver_algs[i]);
+ if (IS_ERR(t_alg)) {
+@@ -2186,12 +2382,36 @@
+ pr_warn("%s alg registration failed\n",
+ t_alg->crypto_alg.cra_driver_name);
+ kfree(t_alg);
+- } else
++ } else {
+ list_add_tail(&t_alg->entry, &alg_list);
++#ifdef DEBUG
++ dev_info(ctrldev, "%s\n",
++ t_alg->crypto_alg.cra_driver_name);
++#endif
++
++ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD &&
++ !memcmp(driver_algs[i].name, "authenc", 7) &&
++ !done) {
++ char *name;
++
++ name = driver_algs[i].name;
++ memmove(name + 10, name + 7, strlen(name) - 7);
++ memcpy(name + 7, "esn", 3);
++
++ name = driver_algs[i].driver_name;
++ memmove(name + 10, name + 7, strlen(name) - 7);
++ memcpy(name + 7, "esn", 3);
++
++ done = true;
++ goto authencesn;
++ }
++ }
+ }
++
+ if (!list_empty(&alg_list))
+ pr_info("caam algorithms registered in /proc/crypto\n");
+
++ of_node_put(dev_node);
+ return err;
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/caamhash.c linux-3.14.72/drivers/crypto/caam/caamhash.c
+--- linux-3.14.72.orig/drivers/crypto/caam/caamhash.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/caamhash.c 2016-06-19 22:11:55.113152605 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for ahash functions of crypto API
+ *
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright 2011-2015 Freescale Semiconductor, Inc.
+ *
+ * Based on caamalg.c crypto API driver.
+ *
+@@ -62,6 +62,7 @@
+ #include "error.h"
+ #include "sg_sw_sec4.h"
+ #include "key_gen.h"
++#include <linux/string.h>
+
+ #define CAAM_CRA_PRIORITY 3000
+
+@@ -115,6 +116,7 @@
+ u8 key[CAAM_MAX_HASH_KEY_SIZE];
+ dma_addr_t key_dma;
+ int ctx_len;
++ unsigned int key_len;
+ unsigned int split_key_len;
+ unsigned int split_key_pad_len;
+ };
+@@ -127,13 +129,22 @@
+ int buflen_0;
+ u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
+ int buflen_1;
+- u8 caam_ctx[MAX_CTX_LEN];
++ u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
+ int (*update)(struct ahash_request *req);
+ int (*final)(struct ahash_request *req);
+ int (*finup)(struct ahash_request *req);
+ int current_buf;
+ };
+
++struct caam_export_state {
++ u8 buf[CAAM_MAX_HASH_BLOCK_SIZE];
++ u8 caam_ctx[MAX_CTX_LEN];
++ int buflen;
++ int (*update)(struct ahash_request *req);
++ int (*final)(struct ahash_request *req);
++ int (*finup)(struct ahash_request *req);
++};
++
+ /* Common job descriptor seq in/out ptr routines */
+
+ /* Map state->caam_ctx, and append seq_out_ptr command that points to it */
+@@ -166,6 +177,7 @@
+ dma_addr_t buf_dma;
+
+ buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, buf_dma, buflen, DMA_TO_DEVICE);
+ dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0);
+
+ return buf_dma;
+@@ -208,6 +220,9 @@
+ u32 flag)
+ {
+ state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag);
++ if ((flag == DMA_TO_DEVICE) || (flag == DMA_BIDIRECTIONAL))
++ dma_sync_single_for_device(jrdev, state->ctx_dma, ctx_len,
++ flag);
+ dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0);
+ }
+
+@@ -219,6 +234,13 @@
+ KEY_DEST_MDHA_SPLIT | KEY_ENC);
+ }
+
++static inline void append_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
++{
++ append_key_as_imm(desc, ctx->key, ctx->key_len,
++ ctx->key_len, CLASS_1 |
++ KEY_DEST_CLASS_REG);
++}
++
+ /* Append key if it has been set */
+ static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
+ {
+@@ -240,6 +262,25 @@
+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
+ }
+
++static inline void init_sh_desc_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx)
++{
++ u32 *key_jump_cmd;
++
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++ if (ctx->key_len) {
++ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
++ JUMP_COND_SHRD);
++
++ append_key_axcbc(desc, ctx);
++
++ set_jump_tgt_here(desc, key_jump_cmd);
++ }
++
++ /* Propagate errors from shared to job descriptor */
++ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
++
++}
+ /*
+ * For ahash read data from seqin following state->caam_ctx,
+ * and write resulting class2 context to seqout, which may be state->caam_ctx
+@@ -259,6 +300,20 @@
+ LDST_SRCDST_BYTE_CONTEXT);
+ }
+
++static inline void axcbc_append_load_str(u32 *desc, int digestsize)
++{
++ /* Calculate remaining bytes to read */
++ append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
++
++ /* Read remaining bytes */
++ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_LAST1 |
++ FIFOLD_TYPE_MSG | KEY_VLF);
++
++ /* Store class1 context bytes */
++ append_seq_store(desc, digestsize, LDST_CLASS_1_CCB |
++ LDST_SRCDST_BYTE_CONTEXT);
++}
++
+ /*
+ * For ahash update, final and finup, import context, read and write to seqout
+ */
+@@ -281,6 +336,27 @@
+ ahash_append_load_str(desc, digestsize);
+ }
+
++/*
++ * For ahash update, final and finup, import context, read and write to seqout
++ */
++static inline void axcbc_ctx_data_to_out(u32 *desc, u32 op, u32 state,
++ int digestsize,
++ struct caam_hash_ctx *ctx)
++{
++ init_sh_desc_key_axcbc(desc, ctx);
++
++ /* Import context from software */
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | ctx->ctx_len);
++
++ /* Class 1 operation */
++ append_operation(desc, op | state | OP_ALG_ENCRYPT);
++
++ /*
++ * Load from buf and/or src and write to req->result or state->context
++ */
++ axcbc_append_load_str(desc, digestsize);
++}
+ /* For ahash firsts and digest, read and write to seqout */
+ static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state,
+ int digestsize, struct caam_hash_ctx *ctx)
+@@ -296,6 +372,21 @@
+ ahash_append_load_str(desc, digestsize);
+ }
+
++/* For ahash firsts and digest, read and write to seqout */
++static inline void axcbc_data_to_out(u32 *desc, u32 op, u32 state,
++ int digestsize, struct caam_hash_ctx *ctx)
++{
++ init_sh_desc_key_axcbc(desc, ctx);
++
++ /* Class 1 operation */
++ append_operation(desc, op | state | OP_ALG_ENCRYPT);
++
++ /*
++ * Load from buf and/or src and write to req->result or state->context
++ */
++ axcbc_append_load_str(desc, digestsize);
++}
++
+ static int ahash_set_sh_desc(struct crypto_ahash *ahash)
+ {
+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+@@ -353,6 +444,8 @@
+ "ahash update first shdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_final shared descriptor */
+ desc = ctx->sh_desc_fin;
+@@ -371,6 +464,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_finup shared descriptor */
+ desc = ctx->sh_desc_finup;
+@@ -389,6 +484,8 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ /* ahash_digest shared descriptor */
+ desc = ctx->sh_desc_digest;
+@@ -409,10 +506,130 @@
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+ desc_bytes(desc), 1);
+ #endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
+
+ return 0;
+ }
+
++static int axcbc_set_sh_desc(struct crypto_ahash *ahash)
++{
++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++ int digestsize = crypto_ahash_digestsize(ahash);
++ struct device *jrdev = ctx->jrdev;
++ u32 have_key = 0;
++ u32 *desc;
++
++ /* ahash_update shared descriptor */
++ desc = ctx->sh_desc_update;
++
++ init_sh_desc(desc, HDR_SHARE_SERIAL);
++
++ /* Import context from software */
++ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
++ LDST_CLASS_1_CCB | ctx->ctx_len);
++
++ /* Class 1 operation */
++ append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE |
++ OP_ALG_ENCRYPT);
++
++ /* Load data and write to result or context */
++ axcbc_append_load_str(desc, ctx->ctx_len);
++
++ ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash update shdesc@"__stringify(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++
++ /* ahash_update_first shared descriptor */
++ desc = ctx->sh_desc_update_first;
++
++ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT,
++ ctx->ctx_len, ctx);
++
++ ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
++ desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash update first shdesc@"__stringify(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_final shared descriptor */
++ desc = ctx->sh_desc_fin;
++
++ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type,
++ OP_ALG_AS_FINALIZE, digestsize, ctx);
++
++ ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_finup shared descriptor */
++ desc = ctx->sh_desc_finup;
++
++ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type,
++ OP_ALG_AS_FINALIZE, digestsize, ctx);
++
++ ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ /* ahash_digest shared descriptor */
++ desc = ctx->sh_desc_digest;
++
++ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL,
++ digestsize, ctx);
++
++ ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
++ desc_bytes(desc),
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
++ dev_err(jrdev, "unable to map shared descriptor\n");
++ return -ENOMEM;
++ }
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ahash digest shdesc@"__stringify(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, desc,
++ desc_bytes(desc), 1);
++#endif
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma,
++ desc_bytes(desc), DMA_TO_DEVICE);
++
++ return 0;
++}
+ static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
+ u32 keylen)
+ {
+@@ -446,6 +663,8 @@
+ kfree(desc);
+ return -ENOMEM;
+ }
++ dma_sync_single_for_device(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
++
+ dst_dma = dma_map_single(jrdev, (void *)key_out, digestsize,
+ DMA_FROM_DEVICE);
+ if (dma_mapping_error(jrdev, dst_dma)) {
+@@ -490,6 +709,7 @@
+ *keylen = digestsize;
+
+ dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
++ dma_sync_single_for_cpu(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
+
+ kfree(desc);
+@@ -547,6 +767,10 @@
+ dev_err(jrdev, "unable to map key i/o memory\n");
+ return -ENOMEM;
+ }
++
++ dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->split_key_pad_len,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
+@@ -567,6 +791,25 @@
+ return -EINVAL;
+ }
+
++static int axcbc_setkey(struct crypto_ahash *ahash,
++ const u8 *key, unsigned int keylen)
++{
++ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
++ int ret = 0;
++
++ ctx->key_len = keylen;
++ memcpy(ctx->key, key, keylen);
++
++#ifdef DEBUG
++ print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
++ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
++ ctx->key_len, 1);
++#endif
++
++ ret = axcbc_set_sh_desc(ahash);
++
++ return ret;
++}
+ /*
+ * ahash_edesc - s/w-extended ahash descriptor
+ * @dst_dma: physical mapped address of req->result
+@@ -594,8 +837,11 @@
+ if (edesc->src_nents)
+ dma_unmap_sg_chained(dev, req->src, edesc->src_nents,
+ DMA_TO_DEVICE, edesc->chained);
+- if (edesc->dst_dma)
++ if (edesc->dst_dma) {
++ dma_sync_single_for_cpu(dev, edesc->dst_dma, dst_len,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
++ }
+
+ if (edesc->sec4_sg_bytes)
+ dma_unmap_single(dev, edesc->sec4_sg_dma,
+@@ -610,8 +856,12 @@
+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ struct caam_hash_state *state = ahash_request_ctx(req);
+
+- if (state->ctx_dma)
++ if (state->ctx_dma) {
++ if ((flag == DMA_FROM_DEVICE) || (flag == DMA_BIDIRECTIONAL))
++ dma_sync_single_for_cpu(dev, state->ctx_dma,
++ ctx->ctx_len, flag);
+ dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
++ }
+ ahash_unmap(dev, edesc, req, dst_len);
+ }
+
+@@ -805,7 +1055,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -855,6 +1105,9 @@
+
+ append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+@@ -910,7 +1163,7 @@
+ sec4_sg_bytes = sec4_sg_src_index * sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -942,6 +1195,9 @@
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -986,7 +1242,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1021,6 +1277,9 @@
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -1061,7 +1320,7 @@
+ sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes +
+ DESC_JOB_IO_LEN, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1071,6 +1330,7 @@
+ DESC_JOB_IO_LEN;
+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
+ sec4_sg_bytes, DMA_TO_DEVICE);
++ edesc->sec4_sg_bytes = sec4_sg_bytes;
+ edesc->src_nents = src_nents;
+ edesc->chained = chained;
+
+@@ -1088,6 +1348,9 @@
+ }
+ append_seq_in_ptr(desc, src_dma, req->nbytes, options);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ edesc->sec4_sg_bytes, DMA_TO_DEVICE);
++
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
+@@ -1126,7 +1389,7 @@
+ int sh_len;
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN,
+ GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1145,6 +1408,8 @@
+ digestsize);
+ edesc->src_nents = 0;
+
++ dma_sync_single_for_device(jrdev, state->buf_dma, buflen,
++ DMA_TO_DEVICE);
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -1197,7 +1462,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -1234,6 +1499,8 @@
+
+ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+@@ -1296,7 +1563,7 @@
+ sizeof(struct sec4_sg_entry);
+
+ /* allocate space for base edesc and hw desc commands, link tables */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev, "could not allocate extended descriptor\n");
+@@ -1328,6 +1595,9 @@
+ edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
+ digestsize);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes,
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
+@@ -1382,7 +1652,7 @@
+ * allocate space for base edesc and hw desc commands,
+ * link tables
+ */
+- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
++ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN +
+ sec4_sg_bytes, GFP_DMA | flags);
+ if (!edesc) {
+ dev_err(jrdev,
+@@ -1422,6 +1692,8 @@
+
+ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
+
++ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma,
++ sec4_sg_bytes, DMA_TO_DEVICE);
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
+ DUMP_PREFIX_ADDRESS, 16, 4, desc,
+@@ -1470,6 +1742,9 @@
+ state->final = ahash_final_no_ctx;
+
+ state->current_buf = 0;
++ state->buf_dma = 0;
++ state->buflen_0 = 0;
++ state->buflen_1 = 0;
+
+ return 0;
+ }
+@@ -1497,25 +1772,42 @@
+
+ static int ahash_export(struct ahash_request *req, void *out)
+ {
+- struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
+- struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ struct caam_hash_state *state = ahash_request_ctx(req);
++ struct caam_export_state *export = out;
++ int len;
++ u8 *buf;
++
++ if (state->current_buf) {
++ buf = state->buf_1;
++ len = state->buflen_1;
++ } else {
++ buf = state->buf_0;
++ len = state->buflen_1;
++ }
++
++ memcpy(export->buf, buf, len);
++ memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx));
++ export->buflen = len;
++ export->update = state->update;
++ export->final = state->final;
++ export->finup = state->finup;
+
+- memcpy(out, ctx, sizeof(struct caam_hash_ctx));
+- memcpy(out + sizeof(struct caam_hash_ctx), state,
+- sizeof(struct caam_hash_state));
+ return 0;
+ }
+
+ static int ahash_import(struct ahash_request *req, const void *in)
+ {
+- struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
+- struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
+ struct caam_hash_state *state = ahash_request_ctx(req);
++ const struct caam_export_state *export = in;
++
++ memset(state, 0, sizeof(*state));
++ memcpy(state->buf_0, export->buf, export->buflen);
++ memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx));
++ state->buflen_0 = export->buflen;
++ state->update = export->update;
++ state->final = export->final;
++ state->finup = export->finup;
+
+- memcpy(ctx, in, sizeof(struct caam_hash_ctx));
+- memcpy(state, in + sizeof(struct caam_hash_ctx),
+- sizeof(struct caam_hash_state));
+ return 0;
+ }
+
+@@ -1533,6 +1825,28 @@
+ /* ahash descriptors */
+ static struct caam_hash_template driver_hash[] = {
+ {
++ .name = "md5",
++ .driver_name = "md5-caam",
++ .hmac_name = "hmac(md5)",
++ .hmac_driver_name = "hmac-md5-caam",
++ .blocksize = MD5_BLOCK_WORDS * 4,
++ .template_ahash = {
++ .init = ahash_init,
++ .update = ahash_update,
++ .final = ahash_final,
++ .finup = ahash_finup,
++ .digest = ahash_digest,
++ .export = ahash_export,
++ .import = ahash_import,
++ .setkey = ahash_setkey,
++ .halg = {
++ .digestsize = MD5_DIGEST_SIZE,
++ .statesize = sizeof(struct caam_export_state),
++ },
++ },
++ .alg_type = OP_ALG_ALGSEL_MD5,
++ .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
++ }, {
+ .name = "sha1",
+ .driver_name = "sha1-caam",
+ .hmac_name = "hmac(sha1)",
+@@ -1549,8 +1863,9 @@
+ .setkey = ahash_setkey,
+ .halg = {
+ .digestsize = SHA1_DIGEST_SIZE,
+- },
++ .statesize = sizeof(struct caam_export_state),
+ },
++ },
+ .alg_type = OP_ALG_ALGSEL_SHA1,
+ .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
+ }, {
+@@ -1570,8 +1885,9 @@
+ .setkey = ahash_setkey,
+ .halg = {
+ .digestsize = SHA224_DIGEST_SIZE,
+- },
++ .statesize = sizeof(struct caam_export_state),
+ },
++ },
+ .alg_type = OP_ALG_ALGSEL_SHA224,
+ .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
+ }, {
+@@ -1591,8 +1907,9 @@
+ .setkey = ahash_setkey,
+ .halg = {
+ .digestsize = SHA256_DIGEST_SIZE,
+- },
++ .statesize = sizeof(struct caam_export_state),
+ },
++ },
+ .alg_type = OP_ALG_ALGSEL_SHA256,
+ .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
+ }, {
+@@ -1612,8 +1929,9 @@
+ .setkey = ahash_setkey,
+ .halg = {
+ .digestsize = SHA384_DIGEST_SIZE,
+- },
++ .statesize = sizeof(struct caam_export_state),
+ },
++ },
+ .alg_type = OP_ALG_ALGSEL_SHA384,
+ .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
+ }, {
+@@ -1633,16 +1951,17 @@
+ .setkey = ahash_setkey,
+ .halg = {
+ .digestsize = SHA512_DIGEST_SIZE,
+- },
++ .statesize = sizeof(struct caam_export_state),
+ },
++ },
+ .alg_type = OP_ALG_ALGSEL_SHA512,
+ .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
+ }, {
+- .name = "md5",
+- .driver_name = "md5-caam",
+- .hmac_name = "hmac(md5)",
+- .hmac_driver_name = "hmac-md5-caam",
+- .blocksize = MD5_BLOCK_WORDS * 4,
++ .name = "xcbc(aes)",
++ .driver_name = "xcbc-aes-caam",
++ .hmac_name = "xcbc(aes)",
++ .hmac_driver_name = "xcbc-aes-caam",
++ .blocksize = XCBC_MAC_BLOCK_WORDS * 4,
+ .template_ahash = {
+ .init = ahash_init,
+ .update = ahash_update,
+@@ -1651,13 +1970,14 @@
+ .digest = ahash_digest,
+ .export = ahash_export,
+ .import = ahash_import,
+- .setkey = ahash_setkey,
++ .setkey = axcbc_setkey,
+ .halg = {
+- .digestsize = MD5_DIGEST_SIZE,
+- },
++ .digestsize = XCBC_MAC_DIGEST_SIZE,
++ .statesize = sizeof(struct caam_export_state),
+ },
+- .alg_type = OP_ALG_ALGSEL_MD5,
+- .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
++ },
++ .alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XCBC_MAC,
++ .alg_op = OP_ALG_ALGSEL_AES,
+ },
+ };
+
+@@ -1712,6 +2032,41 @@
+ return ret;
+ }
+
++static int caam_axcbc_cra_init(struct crypto_tfm *tfm)
++{
++ struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
++ struct crypto_alg *base = tfm->__crt_alg;
++ struct hash_alg_common *halg =
++ container_of(base, struct hash_alg_common, base);
++ struct ahash_alg *alg =
++ container_of(halg, struct ahash_alg, halg);
++ struct caam_hash_alg *caam_hash =
++ container_of(alg, struct caam_hash_alg, ahash_alg);
++ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
++ int ret = 0;
++
++ /*
++ * Get a Job ring from Job Ring driver to ensure in-order
++ * crypto request processing per tfm
++ */
++ ctx->jrdev = caam_jr_alloc();
++ if (IS_ERR(ctx->jrdev)) {
++ pr_err("Job Ring Device allocation for transform failed\n");
++ return PTR_ERR(ctx->jrdev);
++ }
++
++ /* copy descriptor header template value */
++ ctx->alg_type = OP_TYPE_CLASS1_ALG | caam_hash->alg_type;
++ ctx->alg_op = OP_TYPE_CLASS1_ALG | caam_hash->alg_op;
++
++ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
++ sizeof(struct caam_hash_state));
++
++ ret = axcbc_set_sh_desc(ahash);
++
++ return ret;
++}
++
+ static void caam_hash_cra_exit(struct crypto_tfm *tfm)
+ {
+ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
+@@ -1787,7 +2142,11 @@
+ template->driver_name);
+ }
+ alg->cra_module = THIS_MODULE;
+- alg->cra_init = caam_hash_cra_init;
++
++ if (strstr(alg->cra_name, "xcbc") > 0)
++ alg->cra_init = caam_axcbc_cra_init;
++ else
++ alg->cra_init = caam_hash_cra_init;
+ alg->cra_exit = caam_hash_cra_exit;
+ alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
+ alg->cra_priority = CAAM_CRA_PRIORITY;
+@@ -1804,15 +2163,56 @@
+
+ static int __init caam_algapi_hash_init(void)
+ {
+- int i = 0, err = 0;
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++ struct device *ctrldev;
++ struct caam_drv_private *priv;
++ int i = 0, err = 0, md_limit = 0, md_inst;
++ u64 cha_inst;
++
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ of_node_put(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++
++ /*
++ * If priv is NULL, it's probably because the caam driver wasn't
++ * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
++ */
++ if (!priv)
++ return -ENODEV;
+
+ INIT_LIST_HEAD(&hash_list);
+
+- /* register crypto algorithms the device supports */
++ /* register algorithms the device supports */
++ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num);
++ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT;
++ if (md_inst) {
++ md_limit = SHA512_DIGEST_SIZE;
++ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK)
++ == CHA_ID_MD_LP256) /* LP256 limits digest size */
++ md_limit = SHA256_DIGEST_SIZE;
++ }
++
+ for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
+- /* TODO: check if h/w supports alg */
+ struct caam_hash_alg *t_alg;
+
++ /* If no MD instantiated, or MD too small, skip */
++ if ((!md_inst) ||
++ (driver_hash[i].template_ahash.halg.digestsize >
++ md_limit))
++ continue;
++
+ /* register hmac version */
+ t_alg = caam_hash_alloc(&driver_hash[i], true);
+ if (IS_ERR(t_alg)) {
+@@ -1824,8 +2224,9 @@
+
+ err = crypto_register_ahash(&t_alg->ahash_alg);
+ if (err) {
+- pr_warn("%s alg registration failed\n",
+- t_alg->ahash_alg.halg.base.cra_driver_name);
++ pr_warn("%s alg registration failed: %d\n",
++ t_alg->ahash_alg.halg.base.cra_driver_name,
++ err);
+ kfree(t_alg);
+ } else
+ list_add_tail(&t_alg->entry, &hash_list);
+@@ -1841,8 +2242,9 @@
+
+ err = crypto_register_ahash(&t_alg->ahash_alg);
+ if (err) {
+- pr_warn("%s alg registration failed\n",
+- t_alg->ahash_alg.halg.base.cra_driver_name);
++ pr_warn("%s alg registration failed: %d\n",
++ t_alg->ahash_alg.halg.base.cra_driver_name,
++ err);
+ kfree(t_alg);
+ } else
+ list_add_tail(&t_alg->entry, &hash_list);
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/caamrng.c linux-3.14.72/drivers/crypto/caam/caamrng.c
+--- linux-3.14.72.orig/drivers/crypto/caam/caamrng.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/caamrng.c 2016-06-19 22:11:55.113152605 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * caam - Freescale FSL CAAM support for hw_random
+ *
+- * Copyright 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
+ *
+ * Based on caamalg.c crypto API driver.
+ *
+@@ -76,13 +76,16 @@
+ struct buf_data bufs[2];
+ };
+
+-static struct caam_rng_ctx rng_ctx;
++static struct caam_rng_ctx *rng_ctx;
+
+ static inline void rng_unmap_buf(struct device *jrdev, struct buf_data *bd)
+ {
+- if (bd->addr)
++ if (bd->addr) {
++ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, bd->addr, RN_BUF_SIZE,
+ DMA_FROM_DEVICE);
++ }
+ }
+
+ static inline void rng_unmap_ctx(struct caam_rng_ctx *ctx)
+@@ -111,6 +114,10 @@
+
+ atomic_set(&bd->empty, BUF_NOT_EMPTY);
+ complete(&bd->filled);
++
++ /* Buffer refilled, invalidate cache */
++ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "rng refreshed buf@: ",
+ DUMP_PREFIX_ADDRESS, 16, 4, bd->buf, RN_BUF_SIZE, 1);
+@@ -137,7 +144,7 @@
+
+ static int caam_read(struct hwrng *rng, void *data, size_t max, bool wait)
+ {
+- struct caam_rng_ctx *ctx = &rng_ctx;
++ struct caam_rng_ctx *ctx = rng_ctx;
+ struct buf_data *bd = &ctx->bufs[ctx->current_buf];
+ int next_buf_idx, copied_idx;
+ int err;
+@@ -206,6 +213,9 @@
+
+ ctx->sh_desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
+ DMA_TO_DEVICE);
++ dma_sync_single_for_device(jrdev, ctx->sh_desc_dma, desc_bytes(desc),
++ DMA_TO_DEVICE);
++
+ #ifdef DEBUG
+ print_hex_dump(KERN_ERR, "rng shdesc@: ", DUMP_PREFIX_ADDRESS, 16, 4,
+ desc, desc_bytes(desc), 1);
+@@ -237,14 +247,57 @@
+ struct buf_data *bd;
+
+ for (i = 0; i < 2; i++) {
+- bd = &rng_ctx.bufs[i];
++ bd = &rng_ctx->bufs[i];
+ if (atomic_read(&bd->empty) == BUF_PENDING)
+ wait_for_completion(&bd->filled);
+ }
+
+- rng_unmap_ctx(&rng_ctx);
++ rng_unmap_ctx(rng_ctx);
++}
++
++#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST
++static inline void test_len(struct hwrng *rng, size_t len, bool wait)
++{
++ u8 *buf;
++ int real_len;
++
++ buf = kzalloc(sizeof(u8) * len, GFP_KERNEL);
++ real_len = rng->read(rng, buf, len, wait);
++ if (real_len == 0 && wait)
++ pr_err("WAITING FAILED\n");
++ pr_info("wanted %d bytes, got %d\n", len, real_len);
++ print_hex_dump(KERN_INFO, "random bytes@: ", DUMP_PREFIX_ADDRESS,
++ 16, 4, buf, real_len, 1);
++ kfree(buf);
++}
++
++static inline void test_mode_once(struct hwrng *rng, bool wait)
++{
++#define TEST_CHUNK (RN_BUF_SIZE / 4)
++
++ test_len(rng, TEST_CHUNK, wait);
++ test_len(rng, RN_BUF_SIZE * 2, wait);
++ test_len(rng, RN_BUF_SIZE * 2 - TEST_CHUNK, wait);
+ }
+
++static inline void test_mode(struct hwrng *rng, bool wait)
++{
++#define TEST_PASS 1
++ int i;
++
++ for (i = 0; i < TEST_PASS; i++)
++ test_mode_once(rng, wait);
++}
++
++static void self_test(struct hwrng *rng)
++{
++ pr_info("testing without waiting\n");
++ test_mode(rng, false);
++ pr_info("testing with waiting\n");
++ test_mode(rng, true);
++}
++#endif
++
+ static void caam_init_buf(struct caam_rng_ctx *ctx, int buf_id)
+ {
+ struct buf_data *bd = &ctx->bufs[buf_id];
+@@ -273,13 +326,14 @@
+
+ static void __exit caam_rng_exit(void)
+ {
+- caam_jr_free(rng_ctx.jrdev);
++ caam_jr_free(rng_ctx->jrdev);
+ hwrng_unregister(&caam_rng);
+ }
+
+ static int __init caam_rng_init(void)
+ {
+ struct device *dev;
++ rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_KERNEL | GFP_DMA);
+
+ dev = caam_jr_alloc();
+ if (IS_ERR(dev)) {
+@@ -287,7 +341,11 @@
+ return PTR_ERR(dev);
+ }
+
+- caam_init_rng(&rng_ctx, dev);
++ caam_init_rng(rng_ctx, dev);
++
++#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST
++ self_test(&caam_rng);
++#endif
+
+ dev_info(dev, "registering rng-caam\n");
+ return hwrng_register(&caam_rng);
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/compat.h linux-3.14.72/drivers/crypto/caam/compat.h
+--- linux-3.14.72.orig/drivers/crypto/caam/compat.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/compat.h 2016-06-19 22:11:55.113152605 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef CAAM_COMPAT_H
+@@ -23,6 +23,10 @@
+ #include <linux/types.h>
+ #include <linux/debugfs.h>
+ #include <linux/circ_buf.h>
++
++#ifdef CONFIG_ARM /* needs the clock control subsystem */
++#include <linux/clk.h>
++#endif
+ #include <net/xfrm.h>
+
+ #include <crypto/algapi.h>
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/ctrl.c linux-3.14.72/drivers/crypto/caam/ctrl.c
+--- linux-3.14.72.orig/drivers/crypto/caam/ctrl.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/ctrl.c 2016-06-19 22:11:55.113152605 +0200
+@@ -2,7 +2,7 @@
+ * CAAM control-plane driver backend
+ * Controller-level driver, kernel property detection, initialization
+ *
+- * Copyright 2008-2012 Freescale Semiconductor, Inc.
++ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ */
+
+ #include <linux/of_address.h>
+@@ -15,6 +15,7 @@
+ #include "desc_constr.h"
+ #include "error.h"
+ #include "ctrl.h"
++#include "sm.h"
+
+ /*
+ * Descriptor to instantiate RNG State Handle 0 in normal mode and
+@@ -296,6 +297,14 @@
+ /* Unmap controller region */
+ iounmap(&topregs->ctrl);
+
++#ifdef CONFIG_ARM
++ /* shut clocks off before finalizing shutdown */
++ clk_disable(ctrlpriv->caam_ipg);
++ clk_disable(ctrlpriv->caam_mem);
++ clk_disable(ctrlpriv->caam_aclk);
++ clk_disable(ctrlpriv->caam_emi_slow);
++#endif
++
+ kfree(ctrlpriv->jrpdev);
+ kfree(ctrlpriv);
+
+@@ -344,8 +353,8 @@
+ wr_reg32(&r4tst->rtsdctl, val);
+ /* min. freq. count, equal to 1/4 of the entropy sample length */
+ wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
+- /* max. freq. count, equal to 8 times the entropy sample length */
+- wr_reg32(&r4tst->rtfrqmax, ent_delay << 3);
++ /* max. freq. count, equal to 16 times the entropy sample length */
++ wr_reg32(&r4tst->rtfrqmax, ent_delay << 4);
+ /* put RNG4 into run mode */
+ clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+ }
+@@ -356,9 +365,9 @@
+ * Returns the ERA number (1..4) or -ENOTSUPP if the ERA is unknown.
+ * @caam_id - the value of the SEC_VID register
+ **/
+-int caam_get_era(u64 caam_id)
++int caam_get_era(u32 caam_id)
+ {
+- struct sec_vid *sec_vid = (struct sec_vid *)&caam_id;
++ struct sec_vid sec_vid;
+ static const struct {
+ u16 ip_id;
+ u8 maj_rev;
+@@ -368,16 +377,38 @@
+ {0x0A10, 2, 2},
+ {0x0A12, 1, 3},
+ {0x0A14, 1, 3},
++ {0x0A10, 3, 4},
++ {0x0A11, 1, 4},
+ {0x0A14, 2, 4},
+ {0x0A16, 1, 4},
+- {0x0A11, 1, 4}
++ {0x0A18, 1, 4},
++ {0x0A11, 2, 5},
++ {0x0A12, 2, 5},
++ {0x0A13, 1, 5},
++ {0x0A1C, 1, 5},
++ {0x0A12, 4, 6},
++ {0x0A13, 2, 6},
++ {0x0A16, 2, 6},
++ {0x0A17, 1, 6},
++ {0x0A18, 2, 6},
++ {0x0A1A, 1, 6},
++ {0x0A1C, 2, 6},
++ {0x0A14, 3, 7},
++ {0x0A10, 4, 8},
++ {0x0A11, 3, 8},
++ {0x0A11, 4, 8},
++ {0x0A12, 5, 8},
++ {0x0A16, 3, 8},
+ };
+ int i;
+
++ sec_vid.ip_id = caam_id >> SEC_VID_IPID_SHIFT;
++ sec_vid.maj_rev = (caam_id & SEC_VID_MAJ_MASK) >> SEC_VID_MAJ_SHIFT;
++
+ for (i = 0; i < ARRAY_SIZE(caam_eras); i++)
+- if (caam_eras[i].ip_id == sec_vid->ip_id &&
+- caam_eras[i].maj_rev == sec_vid->maj_rev)
+- return caam_eras[i].era;
++ if (caam_eras[i].ip_id == sec_vid.ip_id &&
++ caam_eras[i].maj_rev == sec_vid.maj_rev)
++ return caam_eras[i].era;
+
+ return -ENOTSUPP;
+ }
+@@ -387,7 +418,7 @@
+ static int caam_probe(struct platform_device *pdev)
+ {
+ int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
+- u64 caam_id;
++ u32 caam_id;
+ struct device *dev;
+ struct device_node *nprop, *np;
+ struct caam_ctrl __iomem *ctrl;
+@@ -419,8 +450,92 @@
+ /* topregs used to derive pointers to CAAM sub-blocks only */
+ topregs = (struct caam_full __iomem *)ctrl;
+
+- /* Get the IRQ of the controller (for security violations only) */
+- ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
++ /* Get CAAM-SM node and of_iomap() and save */
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm");
++
++ if (!np)
++ return -ENODEV;
++
++ ctrlpriv->sm_base = of_iomap(np, 0);
++ ctrlpriv->sm_size = 0x3fff;
++
++/*
++ * ARM targets tend to have clock control subsystems that can
++ * enable/disable clocking to our device. Turn clocking on to proceed
++ */
++#ifdef CONFIG_ARM
++ ctrlpriv->caam_ipg = devm_clk_get(&ctrlpriv->pdev->dev, "caam_ipg");
++ if (IS_ERR(ctrlpriv->caam_ipg)) {
++ ret = PTR_ERR(ctrlpriv->caam_ipg);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM ipg clk: %d\n", ret);
++ return -ENODEV;
++ }
++ ctrlpriv->caam_mem = devm_clk_get(&ctrlpriv->pdev->dev, "caam_mem");
++ if (IS_ERR(ctrlpriv->caam_mem)) {
++ ret = PTR_ERR(ctrlpriv->caam_mem);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM secure mem clk: %d\n", ret);
++ return -ENODEV;
++ }
++ ctrlpriv->caam_aclk = devm_clk_get(&ctrlpriv->pdev->dev, "caam_aclk");
++ if (IS_ERR(ctrlpriv->caam_aclk)) {
++ ret = PTR_ERR(ctrlpriv->caam_aclk);
++ dev_err(&ctrlpriv->pdev->dev,
++ "can't identify CAAM aclk clk: %d\n", ret);
++ return -ENODEV;
++ }
++
++ ctrlpriv->caam_emi_slow = devm_clk_get(&ctrlpriv->pdev->dev,
++ "caam_emi_slow");
++ ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM emi"
++ " slow clock: %d\n", ret);
++ return -ENODEV;
++ }
++
++ ret = clk_prepare(ctrlpriv->caam_ipg);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM ipg clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_prepare(ctrlpriv->caam_mem);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM secure mem clock: %d\n",
++ ret);
++ return -ENODEV;
++ }
++ ret = clk_prepare(ctrlpriv->caam_aclk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't prepare CAAM aclk clock: %d\n", ret);
++ return -ENODEV;
++ }
++
++ ret = clk_enable(ctrlpriv->caam_ipg);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
++ return -ENODEV;
++ }
++ ret = clk_enable(ctrlpriv->caam_mem);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
++ ret);
++ return -ENODEV;
++ }
++ ret = clk_enable(ctrlpriv->caam_aclk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
++ return -ENODEV;
++ }
++
++ pr_debug("%s caam_ipg clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_ipg));
++ pr_debug("%s caam_mem clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_mem));
++ pr_debug("%s caam_aclk clock:%d\n", __func__,
++ (int)clk_get_rate(ctrlpriv->caam_aclk));
++#endif
+
+ /*
+ * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
+@@ -429,6 +544,22 @@
+ setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE |
+ (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
+
++#ifdef CONFIG_ARCH_MX6
++ /*
++ * ERRATA: mx6 devices have an issue wherein AXI bus transactions
++ * may not occur in the correct order. This isn't a problem running
++ * single descriptors, but can be if running multiple concurrent
++ * descriptors. Reworking the driver to throttle to single requests
++ * is impractical, thus the workaround is to limit the AXI pipeline
++ * to a depth of 1 (from it's default of 4) to preclude this situation
++ * from occurring.
++ */
++ wr_reg32(&topregs->ctrl.mcr,
++ (rd_reg32(&topregs->ctrl.mcr) & ~(MCFGR_AXIPIPE_MASK)) |
++ ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK));
++#endif
++
++ /* Set DMA masks according to platform ranging */
+ if (sizeof(dma_addr_t) == sizeof(u64))
+ if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
+ dma_set_mask(dev, DMA_BIT_MASK(40));
+@@ -560,10 +691,10 @@
+
+ /* NOTE: RTIC detection ought to go here, around Si time */
+
+- caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id);
++ caam_id = rd_reg32(&topregs->ctrl.perfmon.caam_id);
+
+ /* Report "alive" for developer to see */
+- dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
++ dev_info(dev, "device ID = 0x%08x (Era %d)\n", caam_id,
+ caam_get_era(caam_id));
+ dev_info(dev, "job rings = %d, qi = %d\n",
+ ctrlpriv->total_jobrs, ctrlpriv->qi_present);
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/ctrl.h linux-3.14.72/drivers/crypto/caam/ctrl.h
+--- linux-3.14.72.orig/drivers/crypto/caam/ctrl.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/ctrl.h 2016-06-19 22:11:55.117152342 +0200
+@@ -1,13 +1,13 @@
+ /*
+ * CAAM control-plane driver backend public-level include definitions
+ *
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef CTRL_H
+ #define CTRL_H
+
+ /* Prototypes for backend-level services exposed to APIs */
+-int caam_get_era(u64 caam_id);
++int caam_get_era(u32 caam_id);
+
+ #endif /* CTRL_H */
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/desc.h linux-3.14.72/drivers/crypto/caam/desc.h
+--- linux-3.14.72.orig/drivers/crypto/caam/desc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/desc.h 2016-06-19 22:11:55.117152342 +0200
+@@ -2,19 +2,35 @@
+ * CAAM descriptor composition header
+ * Definitions to support CAAM descriptor instruction generation
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2015 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef DESC_H
+ #define DESC_H
+
++/*
++ * 16-byte hardware scatter/gather table
++ * An 8-byte table exists in the hardware spec, but has never been
++ * implemented to date. The 8/16 option is selected at RTL-compile-time.
++ * and this selection is visible in the Compile Time Parameters Register
++ */
++
++#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */
++#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */
++#define SEC4_SG_BPID_MASK 0x000000ff
++#define SEC4_SG_BPID_SHIFT 16
++#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */
++#define SEC4_SG_OFFS_MASK 0x00001fff
++
+ struct sec4_sg_entry {
++#ifdef CONFIG_64BIT
+ u64 ptr;
+-#define SEC4_SG_LEN_FIN 0x40000000
+-#define SEC4_SG_LEN_EXT 0x80000000
++#else
++ u32 reserved;
++ u32 ptr;
++#endif
+ u32 len;
+- u8 reserved;
+- u8 buf_pool_id;
++ u16 buf_pool_id;
+ u16 offset;
+ };
+
+@@ -391,7 +407,10 @@
+ #define FIFOST_TYPE_PKHA_N (0x08 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_A (0x0c << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_B (0x0d << FIFOST_TYPE_SHIFT)
+-#define FIFOST_TYPE_AF_SBOX_JKEK (0x10 << FIFOST_TYPE_SHIFT)
++#define FIFOST_TYPE_AF_SBOX_CCM_JKEK (0x10 << FIFOST_TYPE_SHIFT)
++#define FIFOST_TYPE_AF_SBOX_CCM_TKEK (0x11 << FIFOST_TYPE_SHIFT)
++#define FIFOST_TYPE_KEY_CCM_JKEK (0x14 << FIFOST_TYPE_SHIFT)
++#define FIFOST_TYPE_KEY_CCM_TKEK (0x15 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_E_JKEK (0x22 << FIFOST_TYPE_SHIFT)
+ #define FIFOST_TYPE_PKHA_E_TKEK (0x23 << FIFOST_TYPE_SHIFT)
+@@ -1093,6 +1112,23 @@
+ #define OP_PCL_PKPROT_ECC 0x0002
+ #define OP_PCL_PKPROT_F2M 0x0001
+
++/* Blob protocol protinfo bits */
++#define OP_PCL_BLOB_TK 0x0200
++#define OP_PCL_BLOB_EKT 0x0100
++
++#define OP_PCL_BLOB_K2KR_MEM 0x0000
++#define OP_PCL_BLOB_K2KR_C1KR 0x0010
++#define OP_PCL_BLOB_K2KR_C2KR 0x0030
++#define OP_PCL_BLOB_K2KR_AFHAS 0x0050
++#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070
++
++#define OP_PCL_BLOB_PTXT_SECMEM 0x0008
++#define OP_PCL_BLOB_BLACK 0x0004
++
++#define OP_PCL_BLOB_FMT_NORMAL 0x0000
++#define OP_PCL_BLOB_FMT_MSTR 0x0002
++#define OP_PCL_BLOB_FMT_TEST 0x0003
++
+ /* For non-protocol/alg-only op commands */
+ #define OP_ALG_TYPE_SHIFT 24
+ #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT)
+@@ -1619,4 +1655,12 @@
+ /* Frame Descriptor Command for Replacement Job Descriptor */
+ #define FD_CMD_REPLACE_JOB_DESC 0x20000000
+
++#define ARC4_BLOCK_SIZE 1
++#define ARC4_MAX_KEY_SIZE 256
++#define ARC4_MIN_KEY_SIZE 1
++
++#define XCBC_MAC_DIGEST_SIZE 16
++#define XCBC_MAC_BLOCK_WORDS 16
++
++
+ #endif /* DESC_H */
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/intern.h linux-3.14.72/drivers/crypto/caam/intern.h
+--- linux-3.14.72.orig/drivers/crypto/caam/intern.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/intern.h 2016-06-19 22:11:55.117152342 +0200
+@@ -2,7 +2,7 @@
+ * CAAM/SEC 4.x driver backend
+ * Private/internal definitions between modules
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ *
+ */
+
+@@ -66,6 +66,7 @@
+ struct caam_drv_private {
+
+ struct device *dev;
++ struct device *smdev;
+ struct platform_device **jrpdev; /* Alloc'ed array per sub-device */
+ struct platform_device *pdev;
+
+@@ -74,6 +75,8 @@
+ struct caam_deco **deco; /* DECO/CCB views */
+ struct caam_assurance *ac;
+ struct caam_queue_if *qi; /* QI control region */
++ dma_addr_t __iomem *sm_base; /* Secure memory storage base */
++ u32 sm_size;
+
+ /*
+ * Detected geometry block. Filled in from device tree if powerpc,
+@@ -81,7 +84,6 @@
+ */
+ u8 total_jobrs; /* Total Job Rings in device */
+ u8 qi_present; /* Nonzero if QI present in device */
+- int secvio_irq; /* Security violation interrupt number */
+
+ #define RNG4_MAX_HANDLES 2
+ /* RNG4 block */
+@@ -89,6 +91,13 @@
+ Handles of the RNG4 block are initialized
+ by this driver */
+
++#ifdef CONFIG_ARM
++ struct clk *caam_ipg;
++ struct clk *caam_mem;
++ struct clk *caam_aclk;
++ struct clk *caam_emi_slow;
++#endif
++
+ /*
+ * debugfs entries for developer view into driver/device
+ * variables at runtime.
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/jr.c linux-3.14.72/drivers/crypto/caam/jr.c
+--- linux-3.14.72.orig/drivers/crypto/caam/jr.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/jr.c 2016-06-19 22:11:55.117152342 +0200
+@@ -2,7 +2,7 @@
+ * CAAM/SEC 4.x transport/backend driver
+ * JobR backend functionality
+ *
+- * Copyright 2008-2012 Freescale Semiconductor, Inc.
++ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ */
+
+ #include <linux/of_irq.h>
+@@ -168,6 +168,9 @@
+ void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg);
+ u32 *userdesc, userstatus;
+ void *userarg;
++ dma_addr_t outbusaddr;
++
++ outbusaddr = rd_reg64(&jrp->rregs->outring_base);
+
+ while (rd_reg32(&jrp->rregs->outring_used)) {
+
+@@ -177,6 +180,9 @@
+
+ sw_idx = tail = jrp->tail;
+ hw_idx = jrp->out_ring_read_index;
++ dma_sync_single_for_cpu(dev, outbusaddr,
++ sizeof(struct jr_outentry) * JOBR_DEPTH,
++ DMA_FROM_DEVICE);
+
+ for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) {
+ sw_idx = (tail + i) & (JOBR_DEPTH - 1);
+@@ -204,6 +210,8 @@
+ userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
+ userstatus = jrp->outring[hw_idx].jrstatus;
+
++ smp_mb();
++
+ /* set done */
+ wr_reg32(&jrp->rregs->outring_rmvd, 1);
+
+@@ -292,8 +300,7 @@
+ * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK,
+ * -EBUSY if the queue is full, -EIO if it cannot map the caller's
+ * descriptor.
+- * @dev: device of the job ring to be used. This device should have
+- * been assigned prior by caam_jr_register().
++ * @dev: device of the job ring to be used.
+ * @desc: points to a job descriptor that execute our request. All
+ * descriptors (and all referenced data) must be in a DMAable
+ * region, and all data references must be physical addresses
+@@ -324,7 +331,7 @@
+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev);
+ struct caam_jrentry_info *head_entry;
+ int head, tail, desc_size;
+- dma_addr_t desc_dma;
++ dma_addr_t desc_dma, inpbusaddr;
+
+ desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32);
+ desc_dma = dma_map_single(dev, desc, desc_size, DMA_TO_DEVICE);
+@@ -333,6 +340,13 @@
+ return -EIO;
+ }
+
++ dma_sync_single_for_device(dev, desc_dma, desc_size, DMA_TO_DEVICE);
++
++ inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
++ dma_sync_single_for_device(dev, inpbusaddr,
++ sizeof(dma_addr_t) * JOBR_DEPTH,
++ DMA_TO_DEVICE);
++
+ spin_lock_bh(&jrp->inplock);
+
+ head = jrp->head;
+@@ -354,12 +368,18 @@
+
+ jrp->inpring[jrp->inp_ring_write_index] = desc_dma;
+
++ dma_sync_single_for_device(dev, inpbusaddr,
++ sizeof(dma_addr_t) * JOBR_DEPTH,
++ DMA_TO_DEVICE);
++
+ smp_wmb();
+
+ jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) &
+ (JOBR_DEPTH - 1);
+ jrp->head = (head + 1) & (JOBR_DEPTH - 1);
+
++ wmb();
++
+ wr_reg32(&jrp->rregs->inpring_jobadd, 1);
+
+ spin_unlock_bh(&jrp->inplock);
+@@ -484,6 +504,10 @@
+
+ /* Identify the interrupt */
+ jrpriv->irq = irq_of_parse_and_map(nprop, 0);
++ if (jrpriv->irq <= 0) {
++ kfree(jrpriv);
++ return -EINVAL;
++ }
+
+ /* Now do the platform independent part */
+ error = caam_jr_init(jrdev); /* now turn on hardware */
+@@ -497,9 +521,39 @@
+
+ atomic_set(&jrpriv->tfm_count, 0);
+
++ device_init_wakeup(&pdev->dev, 1);
++ device_set_wakeup_enable(&pdev->dev, false);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int caam_jr_suspend(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev);
++
++ if (device_may_wakeup(&pdev->dev))
++ enable_irq_wake(jrpriv->irq);
++
++ return 0;
++}
++
++static int caam_jr_resume(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct caam_drv_private_jr *jrpriv = platform_get_drvdata(pdev);
++
++ if (device_may_wakeup(&pdev->dev))
++ disable_irq_wake(jrpriv->irq);
++
+ return 0;
+ }
+
++static SIMPLE_DEV_PM_OPS(caam_jr_pm_ops, caam_jr_suspend,
++ caam_jr_resume);
++#endif
++
+ static struct of_device_id caam_jr_match[] = {
+ {
+ .compatible = "fsl,sec-v4.0-job-ring",
+@@ -516,6 +570,9 @@
+ .name = "caam_jr",
+ .owner = THIS_MODULE,
+ .of_match_table = caam_jr_match,
++#ifdef CONFIG_PM
++ .pm = &caam_jr_pm_ops,
++#endif
+ },
+ .probe = caam_jr_probe,
+ .remove = caam_jr_remove,
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/Kconfig linux-3.14.72/drivers/crypto/caam/Kconfig
+--- linux-3.14.72.orig/drivers/crypto/caam/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/Kconfig 2016-06-19 22:11:55.117152342 +0200
+@@ -1,6 +1,6 @@
+ config CRYPTO_DEV_FSL_CAAM
+ tristate "Freescale CAAM-Multicore driver backend"
+- depends on FSL_SOC
++ depends on FSL_SOC || ARCH_MXC
+ help
+ Enables the driver module for Freescale's Cryptographic Accelerator
+ and Assurance Module (CAAM), also known as the SEC version 4 (SEC4).
+@@ -112,6 +112,56 @@
+ To compile this as a module, choose M here: the module
+ will be called caamrng.
+
++config CRYPTO_DEV_FSL_CAAM_RNG_TEST
++ boolean "Test caam rng"
++ depends on CRYPTO_DEV_FSL_CAAM_RNG_API
++ default n
++ help
++ Selecting this will enable a self-test to run for the
++ caam RNG. This test is several minutes long and executes
++ just before the RNG is registered with the hw_random API.
++
++config CRYPTO_DEV_FSL_CAAM_SM
++ tristate "CAAM Secure Memory / Keystore API (EXPERIMENTAL)"
++ default n
++ help
++ Enables use of a prototype kernel-level Keystore API with CAAM
++ Secure Memory for insertion/extraction of bus-protected secrets.
++
++config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE
++ int "Size of each keystore slot in Secure Memory"
++ depends on CRYPTO_DEV_FSL_CAAM_SM
++ range 5 9
++ default 7
++ help
++ Select size of allocation units to divide Secure Memory pages into
++ (the size of a "slot" as referenced inside the API code).
++ Established as powers of two.
++ Examples:
++ 5 => 32 bytes
++ 6 => 64 bytes
++ 7 => 128 bytes
++ 8 => 256 bytes
++ 9 => 512 bytes
++
++config CRYPTO_DEV_FSL_CAAM_SM_TEST
++ tristate "CAAM Secure Memory - Keystore Test/Example (EXPERIMENTAL)"
++ depends on CRYPTO_DEV_FSL_CAAM_SM
++ default n
++ help
++ Example thread to exercise the Keystore API and to verify that
++ stored and recovered secrets can be used for general purpose
++ encryption/decryption.
++
++config CRYPTO_DEV_FSL_CAAM_SECVIO
++ tristate "CAAM/SNVS Security Violation Handler (EXPERIMENTAL)"
++ depends on CRYPTO_DEV_FSL_CAAM
++ default n
++ help
++ Enables installation of an interrupt handler with registrable
++ handler functions which can be specified to act on the consequences
++ of a security violation.
++
+ config CRYPTO_DEV_FSL_CAAM_DEBUG
+ bool "Enable debug output in CAAM driver"
+ depends on CRYPTO_DEV_FSL_CAAM
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/key_gen.c linux-3.14.72/drivers/crypto/caam/key_gen.c
+--- linux-3.14.72.orig/drivers/crypto/caam/key_gen.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/key_gen.c 2016-06-19 22:11:55.117152342 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM/SEC 4.x functions for handling key-generation jobs
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ *
+ */
+ #include "compat.h"
+@@ -74,6 +74,9 @@
+ }
+
+ init_job_desc(desc, 0);
++
++ dma_sync_single_for_device(jrdev, dma_addr_in, keylen, DMA_TO_DEVICE);
++
+ append_key(desc, dma_addr_in, keylen, CLASS_2 | KEY_DEST_CLASS_REG);
+
+ /* Sets MDHA up into an HMAC-INIT */
+@@ -114,7 +117,8 @@
+ split_key_pad_len, 1);
+ #endif
+ }
+-
++ dma_sync_single_for_cpu(jrdev, dma_addr_out, split_key_pad_len,
++ DMA_FROM_DEVICE);
+ dma_unmap_single(jrdev, dma_addr_out, split_key_pad_len,
+ DMA_FROM_DEVICE);
+ out_unmap_in:
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/Makefile linux-3.14.72/drivers/crypto/caam/Makefile
+--- linux-3.14.72.orig/drivers/crypto/caam/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/Makefile 2016-06-19 22:11:55.117152342 +0200
+@@ -10,6 +10,9 @@
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
+ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o
+
+ caam-objs := ctrl.o
+ caam_jr-objs := jr.o key_gen.o error.o
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/regs.h linux-3.14.72/drivers/crypto/caam/regs.h
+--- linux-3.14.72.orig/drivers/crypto/caam/regs.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/regs.h 2016-06-19 22:11:55.117152342 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM hardware register-level view
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2008-2015 Freescale Semiconductor, Inc.
+ */
+
+ #ifndef REGS_H
+@@ -74,15 +74,21 @@
+ #endif
+ #else
+ #ifdef __LITTLE_ENDIAN
+-#define wr_reg32(reg, data) __raw_writel(reg, data)
+-#define rd_reg32(reg) __raw_readl(reg)
++#define wr_reg32(reg, data) writel(data, reg)
++#define rd_reg32(reg) readl(reg)
+ #ifdef CONFIG_64BIT
+-#define wr_reg64(reg, data) __raw_writeq(reg, data)
+-#define rd_reg64(reg) __raw_readq(reg)
++#define wr_reg64(reg, data) writeq(data, reg)
++#define rd_reg64(reg) readq(reg)
+ #endif
+ #endif
+ #endif
+
++#ifdef CONFIG_ARM
++/* These are common macros for Power, put here for ARMs */
++#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
++#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
++#endif
++
+ #ifndef CONFIG_64BIT
+ static inline void wr_reg64(u64 __iomem *reg, u64 data)
+ {
+@@ -107,52 +113,107 @@
+ } __packed;
+
+ /*
+- * caam_perfmon - Performance Monitor/Secure Memory Status/
+- * CAAM Global Status/Component Version IDs
+- *
+- * Spans f00-fff wherever instantiated
++ * CHA version ID / instantiation bitfields
++ * Defined for use within cha_id in perfmon
++ * Note that the same shift/mask selectors can be used to pull out number
++ * of instantiated blocks within cha_num in perfmon, the locations are
++ * the same.
+ */
+
+-/* Number of DECOs */
+-#define CHA_NUM_DECONUM_SHIFT 56
++/* Job Ring */
++#define CHA_ID_JR_SHIFT 60
++#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT)
++
++/* DEscriptor COntroller */
++#define CHA_ID_DECO_SHIFT 56
++#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT)
++#define CHA_NUM_DECONUM_SHIFT 56 /* legacy definition */
+ #define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+
+-/* CHA Version IDs */
+-#define CHA_ID_AES_SHIFT 0
+-#define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT)
++/* ZUC-Authentication */
++#define CHA_ID_ZA_SHIFT 44
++#define CHA_ID_ZA_MASK (0xfull << CHA_ID_ZA_SHIFT)
++
++/* ZUC-Encryption */
++#define CHA_ID_ZE_SHIFT 40
++#define CHA_ID_ZE_MASK (0xfull << CHA_ID_ZE_SHIFT)
+
+-#define CHA_ID_DES_SHIFT 4
+-#define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT)
++/* SNOW f9 */
++#define CHA_ID_SNW9_SHIFT 36
++#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT)
+
+-#define CHA_ID_ARC4_SHIFT 8
+-#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
++/* CRC */
++#define CHA_ID_CRC_SHIFT 32
++#define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT)
+
+-#define CHA_ID_MD_SHIFT 12
+-#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
++/* Public Key */
++#define CHA_ID_PK_SHIFT 28
++#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT)
+
+-#define CHA_ID_RNG_SHIFT 16
+-#define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT)
++/* Kasumi */
++#define CHA_ID_KAS_SHIFT 24
++#define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT)
+
++/* SNOW f8 */
+ #define CHA_ID_SNW8_SHIFT 20
+ #define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT)
+
+-#define CHA_ID_KAS_SHIFT 24
+-#define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT)
++/*
++ * Random Generator
++ * RNG4 = FIPS-verification-compliant, requires init kickstart for use
++ */
++#define CHA_ID_RNG_SHIFT 16
++#define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_A (0x1ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_B (0x2ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_C (0x3ull << CHA_ID_RNG_SHIFT)
++#define CHA_ID_RNG_4 (0x4ull << CHA_ID_RNG_SHIFT)
+
+-#define CHA_ID_PK_SHIFT 28
+-#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT)
++/*
++ * Message Digest
++ * LP256 = Low Power (MD5/SHA1/SHA224/SHA256 + HMAC)
++ * LP512 = Low Power (LP256 + SHA384/SHA512)
++ * HP = High Power (LP512 + SMAC)
++ */
++#define CHA_ID_MD_SHIFT 12
++#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_LP256 (0x0ull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_LP512 (0x1ull << CHA_ID_MD_SHIFT)
++#define CHA_ID_MD_HP (0x2ull << CHA_ID_MD_SHIFT)
+
+-#define CHA_ID_CRC_SHIFT 32
+-#define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT)
++/* ARC4 Streamcipher */
++#define CHA_ID_ARC4_SHIFT 8
++#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT)
++#define CHA_ID_ARC4_LP (0x0ull << CHA_ID_ARC4_SHIFT)
++#define CHA_ID_ARC4_HP (0x1ull << CHA_ID_ARC4_SHIFT)
+
+-#define CHA_ID_SNW9_SHIFT 36
+-#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT)
++/* DES Blockcipher Accelerator */
++#define CHA_ID_DES_SHIFT 4
++#define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT)
+
+-#define CHA_ID_DECO_SHIFT 56
+-#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT)
++/*
++ * AES Blockcipher + Combo Mode Accelerator
++ * LP = Low Power (includes ECB/CBC/CFB128/OFB/CTR/CCM/CMAC/XCBC-MAC)
++ * HP = High Power (LP + CBCXCBC/CTRXCBC/XTS/GCM)
++ * DIFFPWR = ORed in if differential-power-analysis resistance implemented
++ */
++#define CHA_ID_AES_SHIFT 0
++#define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_LP (0x3ull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_HP (0x4ull << CHA_ID_AES_SHIFT)
++#define CHA_ID_AES_DIFFPWR (0x1ull << CHA_ID_AES_SHIFT)
+
+-#define CHA_ID_JR_SHIFT 60
+-#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT)
++
++/*
++ * caam_perfmon - Performance Monitor/Secure Memory Status/
++ * CAAM Global Status/Component Version IDs
++ *
++ * Spans f00-fff wherever instantiated
++ */
++
++/* Number of DECOs */
++#define CHA_NUM_DECONUM_SHIFT 56
++#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT)
+
+ struct sec_vid {
+ u16 ip_id;
+@@ -160,6 +221,10 @@
+ u8 min_rev;
+ };
+
++#define SEC_VID_IPID_SHIFT 16
++#define SEC_VID_MAJ_SHIFT 8
++#define SEC_VID_MAJ_MASK 0xFF00
++
+ struct caam_perfmon {
+ /* Performance Monitor Registers f00-f9f */
+ u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
+@@ -176,15 +241,21 @@
+ #define CTPR_QI_SHIFT 57
+ #define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT)
+ u64 comp_parms; /* CTPR - Compile Parameters Register */
+- u64 rsvd1[2];
++
++ /* Secure Memory State Visibility */
++ u32 rsvd1;
++ u32 smstatus; /* Secure memory status */
++ u32 rsvd2;
++ u32 smpartown; /* Secure memory partition owner */
+
+ /* CAAM Global Status fc0-fdf */
+ u64 faultaddr; /* FAR - Fault Address */
+ u32 faultliodn; /* FALR - Fault Address LIODN */
+ u32 faultdetail; /* FADR - Fault Addr Detail */
+- u32 rsvd2;
++ u32 rsvd3;
+ u32 status; /* CSTA - CAAM Status */
+- u64 rsvd3;
++ u32 smpart; /* Secure Memory Partition Parameters */
++ u32 smvid; /* Secure Memory Version ID */
+
+ /* Component Instantiation Parameters fe0-fff */
+ u32 rtic_id; /* RVID - RTIC Version ID */
+@@ -194,6 +265,62 @@
+ u64 caam_id; /* CAAMVID - CAAM Version ID */
+ };
+
++#define SMSTATUS_PART_SHIFT 28
++#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT)
++#define SMSTATUS_PAGE_SHIFT 16
++#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT)
++#define SMSTATUS_MID_SHIFT 8
++#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT)
++#define SMSTATUS_ACCERR_SHIFT 4
++#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT)
++#define SMSTATUS_ACCERR_NONE 0
++#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */
++#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */
++#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */
++#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */
++#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */
++#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */
++#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */
++#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */
++#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */
++#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */
++#define SMSTATUS_STATE_SHIFT 0
++#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT)
++#define SMSTATUS_STATE_RESET 0
++#define SMSTATUS_STATE_INIT 1
++#define SMSTATUS_STATE_NORMAL 2
++#define SMSTATUS_STATE_FAIL 3
++
++/* up to 15 rings, 2 bits shifted by ring number */
++#define SMPARTOWN_RING_SHIFT 2
++#define SMPARTOWN_RING_MASK 3
++#define SMPARTOWN_AVAILABLE 0
++#define SMPARTOWN_NOEXIST 1
++#define SMPARTOWN_UNAVAILABLE 2
++#define SMPARTOWN_OURS 3
++
++/* Maximum number of pages possible */
++#define SMPART_MAX_NUMPG_SHIFT 16
++#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT)
++
++/* Maximum partition number */
++#define SMPART_MAX_PNUM_SHIFT 12
++#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT)
++
++/* Highest possible page number */
++#define SMPART_MAX_PG_SHIFT 0
++#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT)
++
++/* Max size of a page */
++#define SMVID_PG_SIZE_SHIFT 16
++#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT)
++
++/* Major/Minor Version ID */
++#define SMVID_MAJ_VERS_SHIFT 8
++#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT)
++#define SMVID_MIN_VERS_SHIFT 0
++#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT)
++
+ /* LIODN programming for DMA configuration */
+ #define MSTRID_LOCK_LIODN 0x80000000
+ #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
+@@ -255,7 +382,7 @@
+ };
+ #define RTSDCTL_ENT_DLY_SHIFT 16
+ #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
+-#define RTSDCTL_ENT_DLY_MIN 1200
++#define RTSDCTL_ENT_DLY_MIN 3200
+ #define RTSDCTL_ENT_DLY_MAX 12800
+ u32 rtsdctl; /* seed control register */
+ union {
+@@ -407,7 +534,18 @@
+ u32 rsvd11;
+ u32 jrcommand; /* JRCRx - JobR command */
+
+- u32 rsvd12[932];
++ u32 rsvd12[33];
++
++ /* Secure Memory Configuration - if you have it */
++ u32 sm_cmd; /* SMCJRx - Secure memory command */
++ u32 rsvd13;
++ u32 sm_status; /* SMCSJRx - Secure memory status */
++ u32 rsvd14;
++ u32 sm_perm; /* SMAPJRx - Secure memory access perms */
++ u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */
++ u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */
++
++ u32 rsvd15[891];
+
+ /* Performance Monitor f00-fff */
+ struct caam_perfmon perfmon;
+@@ -530,6 +668,62 @@
+
+ #define JRCR_RESET 0x01
+
++/* secure memory command */
++#define SMC_PAGE_SHIFT 16
++#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT)
++#define SMC_PART_SHIFT 8
++#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT)
++#define SMC_CMD_SHIFT 0
++#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT)
++
++#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */
++#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */
++#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */
++#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */
++
++/* secure memory (command) status */
++#define SMCS_PAGE_SHIFT 16
++#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT)
++#define SMCS_CMDERR_SHIFT 14
++#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT)
++#define SMCS_ALCERR_SHIFT 12
++#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT)
++#define SMCS_PGOWN_SHIFT 6
++#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT)
++#define SMCS_PART_SHIFT 0
++#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT)
++
++#define SMCS_CMDERR_NONE 0
++#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */
++#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */
++#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */
++
++#define SMCS_ALCERR_NONE 0
++#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */
++#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */
++#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */
++
++#define SMCS_PGOWN_AVAIL 0 /* Page is available */
++#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */
++#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */
++#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */
++
++/* secure memory access permissions */
++#define SMCS_PERM_KEYMOD_SHIFT 16
++#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT)
++#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */
++#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */
++#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */
++#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */
++#define SMCA_PERM_RINGID_SHIFT 10
++#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT)
++#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */
++#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */
++#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */
++#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */
++#define SMCA_PERM_G1_WRITE 0x0002
++#define SMCA_PERM_G1_READ 0x0001
++
+ /*
+ * caam_assurance - Assurance Controller View
+ * base + 0x6000 padded out to 0x1000
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/secvio.c linux-3.14.72/drivers/crypto/caam/secvio.c
+--- linux-3.14.72.orig/drivers/crypto/caam/secvio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/crypto/caam/secvio.c 2016-06-19 22:11:55.117152342 +0200
+@@ -0,0 +1,292 @@
++
++/*
++ * SNVS Security Violation Handler
++ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include "compat.h"
++#include "intern.h"
++#include "secvio.h"
++#include "regs.h"
++
++/*
++ * These names are associated with each violation handler.
++ * The source names were taken from MX6, and are based on recommendations
++ * for most common SoCs.
++ */
++static const u8 *violation_src_name[] = {
++ "CAAM Internal Security Violation",
++ "JTAG Alarm",
++ "Watchdog",
++ "(reserved)",
++ "External Boot",
++ "External Tamper Detect",
++};
++
++/* These names help describe security monitor state for the console */
++static const u8 *snvs_ssm_state_name[] = {
++ "init",
++ "hard fail",
++ "(undef:2)",
++ "soft fail",
++ "(undef:4)",
++ "(undef:5)",
++ "(undef:6)",
++ "(undef:7)",
++ "transition",
++ "check",
++ "(undef:10)",
++ "non-secure",
++ "(undef:12)",
++ "trusted",
++ "(undef:14)",
++ "secure",
++};
++
++/* Top-level security violation interrupt */
++static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev)
++{
++ struct device *dev = snvsdev;
++ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
++
++ /* Check the HP secvio status register */
++ svpriv->irqcause = rd_reg32(&svpriv->svregs->hp.secvio_status) &
++ HP_SECVIOST_SECVIOMASK;
++
++ if (!svpriv->irqcause)
++ return IRQ_NONE;
++
++ /* Now ACK cause */
++ setbits32(&svpriv->svregs->hp.secvio_status, svpriv->irqcause);
++
++ /* And run deferred service */
++ preempt_disable();
++ tasklet_schedule(&svpriv->irqtask[smp_processor_id()]);
++ preempt_enable();
++
++ return IRQ_HANDLED;
++}
++
++/* Deferred service handler. Tasklet arg is simply the SNVS dev */
++static void snvs_secvio_dispatch(unsigned long indev)
++{
++ struct device *dev = (struct device *)indev;
++ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
++ unsigned long flags;
++ int i;
++
++
++ /* Look through stored causes, call each handler if exists */
++ for (i = 0; i < MAX_SECVIO_SOURCES; i++)
++ if (svpriv->irqcause & (1 << i)) {
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[i].handler(dev, i,
++ svpriv->intsrc[i].ext);
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++ };
++
++ /* Re-enable now-serviced interrupts */
++ setbits32(&svpriv->svregs->hp.secvio_intcfg, svpriv->irqcause);
++}
++
++/*
++ * Default cause handler, used in lieu of an application-defined handler.
++ * All it does at this time is print a console message. It could force a halt.
++ */
++static void snvs_secvio_default(struct device *dev, u32 cause, void *ext)
++{
++ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev);
++
++ dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n",
++ cause, svpriv->intsrc[cause].intname);
++}
++
++/*
++ * Install an application-defined handler for a specified cause
++ * Arguments:
++ * - dev points to SNVS-owning device
++ * - cause interrupt source cause
++ * - handler application-defined handler, gets called with dev
++ * source cause, and locally-defined handler argument
++ * - cause_description points to a string to override the default cause
++ * name, this can be used as an alternate for error
++ * messages and such. If left NULL, the default
++ * description string is used.
++ * - ext pointer to any extra data needed by the handler.
++ */
++int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause,
++ void (*handler)(struct device *dev, u32 cause,
++ void *ext),
++ u8 *cause_description, void *ext)
++{
++ unsigned long flags;
++ struct snvs_secvio_drv_private *svpriv;
++
++ svpriv = dev_get_drvdata(dev);
++
++ if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5))
++ return -EINVAL;
++
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[cause].handler = handler;
++ if (cause_description != NULL)
++ svpriv->intsrc[cause].intname = cause_description;
++ if (ext != NULL)
++ svpriv->intsrc[cause].ext = ext;
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(snvs_secvio_install_handler);
++
++/*
++ * Remove an application-defined handler for a specified cause (and, by
++ * implication, restore the "default".
++ * Arguments:
++ * - dev points to SNVS-owning device
++ * - cause interrupt source cause
++ */
++int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause)
++{
++ unsigned long flags;
++ struct snvs_secvio_drv_private *svpriv;
++
++ svpriv = dev_get_drvdata(dev);
++
++ if (cause > SECVIO_CAUSE_SOURCE_5)
++ return -EINVAL;
++
++ spin_lock_irqsave(&svpriv->svlock, flags);
++ svpriv->intsrc[cause].intname = violation_src_name[cause];
++ svpriv->intsrc[cause].handler = snvs_secvio_default;
++ svpriv->intsrc[cause].ext = NULL;
++ spin_unlock_irqrestore(&svpriv->svlock, flags);
++ return 0;
++}
++EXPORT_SYMBOL(snvs_secvio_remove_handler);
++
++static int snvs_secvio_remove(struct platform_device *pdev)
++{
++ struct device *svdev;
++ struct snvs_secvio_drv_private *svpriv;
++ int i;
++
++ svdev = &pdev->dev;
++ svpriv = dev_get_drvdata(svdev);
++
++ /* Set all sources to nonfatal */
++ wr_reg32(&svpriv->svregs->hp.secvio_intcfg, 0);
++
++ /* Remove tasklets and release interrupt */
++ for_each_possible_cpu(i)
++ tasklet_kill(&svpriv->irqtask[i]);
++
++ free_irq(svpriv->irq, svdev);
++ iounmap(svpriv->svregs);
++ kfree(svpriv);
++
++ return 0;
++}
++
++static int snvs_secvio_probe(struct platform_device *pdev)
++{
++ struct device *svdev;
++ struct snvs_secvio_drv_private *svpriv;
++ struct device_node *np, *npirq;
++ struct snvs_full __iomem *snvsregs;
++ int i, error;
++ u32 hpstate;
++
++ svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL);
++ if (!svpriv)
++ return -ENOMEM;
++
++ svdev = &pdev->dev;
++ dev_set_drvdata(svdev, svpriv);
++ svpriv->pdev = pdev;
++ np = pdev->dev.of_node;
++
++ npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio");
++ if (!npirq) {
++ dev_err(svdev, "can't identify secvio interrupt\n");
++ kfree(svpriv);
++ return -EINVAL;
++ }
++ svpriv->irq = irq_of_parse_and_map(npirq, 0);
++ if (svpriv->irq <= 0) {
++ kfree(svpriv);
++ return -EINVAL;
++ }
++
++ snvsregs = of_iomap(np, 0);
++ if (!snvsregs) {
++ dev_err(svdev, "register mapping failed\n");
++ return -ENOMEM;
++ }
++ svpriv->svregs = (struct snvs_full __force *)snvsregs;
++
++ /* Device data set up. Now init interrupt source descriptions */
++ for (i = 0; i < MAX_SECVIO_SOURCES; i++) {
++ svpriv->intsrc[i].intname = violation_src_name[i];
++ svpriv->intsrc[i].handler = snvs_secvio_default;
++ }
++ /* Connect main handler */
++ for_each_possible_cpu(i)
++ tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch,
++ (unsigned long)svdev);
++
++ error = request_irq(svpriv->irq, snvs_secvio_interrupt,
++ IRQF_SHARED, "snvs-secvio", svdev);
++ if (error) {
++ dev_err(svdev, "can't connect secvio interrupt\n");
++ irq_dispose_mapping(svpriv->irq);
++ svpriv->irq = 0;
++ iounmap(svpriv->svregs);
++ kfree(svpriv);
++ return -EINVAL;
++ }
++
++ /*
++ * Configure all sources as fatal violations except LP section,
++ * source #5 (typically used as an external tamper detect), and
++ * source #3 (typically unused). Whenever the transition to
++ * secure mode has occurred, these will now be "fatal" violations
++ */
++ wr_reg32(&svpriv->svregs->hp.secvio_intcfg,
++ HP_SECVIO_INTEN_SRC4 | HP_SECVIO_INTEN_SRC2 |
++ HP_SECVIO_INTEN_SRC1 | HP_SECVIO_INTEN_SRC0);
++
++ hpstate = (rd_reg32(&svpriv->svregs->hp.status) &
++ HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT;
++ dev_info(svdev, "violation handlers armed - %s state\n",
++ snvs_ssm_state_name[hpstate]);
++
++ return 0;
++}
++
++static struct of_device_id snvs_secvio_match[] = {
++ {
++ .compatible = "fsl,imx6q-caam-snvs",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, snvs_secvio_match);
++
++static struct platform_driver snvs_secvio_driver = {
++ .driver = {
++ .name = "snvs-secvio",
++ .owner = THIS_MODULE,
++ .of_match_table = snvs_secvio_match,
++ },
++ .probe = snvs_secvio_probe,
++ .remove = snvs_secvio_remove,
++};
++
++module_platform_driver(snvs_secvio_driver);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL SNVS Security Violation Handler");
++MODULE_AUTHOR("Freescale Semiconductor - MCU");
++
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/secvio.h linux-3.14.72/drivers/crypto/caam/secvio.h
+--- linux-3.14.72.orig/drivers/crypto/caam/secvio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/crypto/caam/secvio.h 2016-06-19 22:11:55.117152342 +0200
+@@ -0,0 +1,66 @@
++
++/*
++ * CAAM Security Violation Handler
++ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#ifndef SECVIO_H
++#define SECVIO_H
++
++#include "snvsregs.h"
++
++
++/*
++ * Defines the published interfaces to install/remove application-specified
++ * handlers for catching violations
++ */
++
++#define MAX_SECVIO_SOURCES 6
++
++/* these are the untranslated causes */
++enum secvio_cause {
++ SECVIO_CAUSE_SOURCE_0,
++ SECVIO_CAUSE_SOURCE_1,
++ SECVIO_CAUSE_SOURCE_2,
++ SECVIO_CAUSE_SOURCE_3,
++ SECVIO_CAUSE_SOURCE_4,
++ SECVIO_CAUSE_SOURCE_5
++};
++
++/* These are common "recommended" cause definitions for most devices */
++#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0
++#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1
++#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2
++#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4
++#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5
++
++int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause,
++ void (*handler)(struct device *dev, u32 cause,
++ void *ext),
++ u8 *cause_description, void *ext);
++int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause);
++
++/*
++ * Private data definitions for the secvio "driver"
++ */
++
++struct secvio_int_src {
++ const u8 *intname; /* Points to a descriptive name for source */
++ void *ext; /* Extended data to pass to the handler */
++ void (*handler)(struct device *dev, u32 cause, void *ext);
++};
++
++struct snvs_secvio_drv_private {
++ struct platform_device *pdev;
++ spinlock_t svlock ____cacheline_aligned;
++ struct tasklet_struct irqtask[NR_CPUS];
++ struct snvs_full __iomem *svregs; /* both HP and LP domains */
++ int irq;
++ u32 irqcause; /* stashed cause of violation interrupt */
++
++ /* Registered handlers for each violation */
++ struct secvio_int_src intsrc[MAX_SECVIO_SOURCES];
++
++};
++
++#endif /* SECVIO_H */
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/sg_sw_sec4.h linux-3.14.72/drivers/crypto/caam/sg_sw_sec4.h
+--- linux-3.14.72.orig/drivers/crypto/caam/sg_sw_sec4.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/crypto/caam/sg_sw_sec4.h 2016-06-19 22:11:55.117152342 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * CAAM/SEC 4.x functions for using scatterlists in caam driver
+ *
+- * Copyright 2008-2011 Freescale Semiconductor, Inc.
++ * Copyright 2008-2015 Freescale Semiconductor, Inc.
+ *
+ */
+
+@@ -91,13 +91,22 @@
+ {
+ if (unlikely(chained)) {
+ int i;
++ struct scatterlist *tsg = sg;
++
++ /* We use a local copy of the sg pointer to avoid moving the
++ * head of the list pointed to by sg as we wall the list.
++ */
+ for (i = 0; i < nents; i++) {
+- dma_map_sg(dev, sg, 1, dir);
+- sg = scatterwalk_sg_next(sg);
++ dma_map_sg(dev, tsg, 1, dir);
++ tsg = scatterwalk_sg_next(tsg);
+ }
+ } else {
+ dma_map_sg(dev, sg, nents, dir);
+ }
++
++ if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL))
++ dma_sync_sg_for_device(dev, sg, nents, dir);
++
+ return nents;
+ }
+
+@@ -105,6 +114,9 @@
+ unsigned int nents, enum dma_data_direction dir,
+ bool chained)
+ {
++ if ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))
++ dma_sync_sg_for_cpu(dev, sg, nents, dir);
++
+ if (unlikely(chained)) {
+ int i;
+ for (i = 0; i < nents; i++) {
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/sm.h linux-3.14.72/drivers/crypto/caam/sm.h
+--- linux-3.14.72.orig/drivers/crypto/caam/sm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/crypto/caam/sm.h 2016-06-19 22:11:55.117152342 +0200
+@@ -0,0 +1,122 @@
++
++/*
++ * CAAM Secure Memory/Keywrap API Definitions
++ * Copyright (C) 2008-2015 Freescale Semiconductor, Inc.
++ */
++
++#ifndef SM_H
++#define SM_H
++
++
++/* Storage access permissions */
++#define SM_PERM_READ 0x01
++#define SM_PERM_WRITE 0x02
++#define SM_PERM_BLOB 0x03
++
++/* Define treatment of secure memory vs. general memory blobs */
++#define SM_SECMEM 0
++#define SM_GENMEM 1
++
++/* Define treatment of red/black keys */
++#define RED_KEY 0
++#define BLACK_KEY 1
++
++/* Define key encryption/covering options */
++#define KEY_COVER_ECB 0 /* cover key in AES-ECB */
++#define KEY_COVER_CCM 1 /* cover key with AES-CCM */
++
++/*
++ * Round a key size up to an AES blocksize boundary so to allow for
++ * padding out to a full block
++ */
++#define AES_BLOCK_PAD(x) ((x % 16) ? ((x >> 4) + 1) << 4 : x)
++
++/* Define space required for BKEK + MAC tag storage in any blob */
++#define BLOB_OVERHEAD (32 + 16)
++
++/* Keystore maintenance functions */
++void sm_init_keystore(struct device *dev);
++u32 sm_detect_keystore_units(struct device *dev);
++int sm_establish_keystore(struct device *dev, u32 unit);
++void sm_release_keystore(struct device *dev, u32 unit);
++void caam_sm_shutdown(struct platform_device *pdev);
++int caam_sm_example_init(struct platform_device *pdev);
++
++/* Keystore accessor functions */
++extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size,
++ u32 *slot);
++extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot);
++extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot,
++ const u8 *key_data, u32 key_length);
++extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot,
++ u32 key_length, u8 *key_data);
++extern int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot,
++ u16 key_length, u8 keyauth);
++extern int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot,
++ u8 keycolor, u8 keyauth, u8 *outbuf,
++ u16 keylen, u8 *keymod);
++extern int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot,
++ u8 keycolor, u8 keyauth, u8 *inbuf,
++ u16 keylen, u8 *keymod);
++
++/* Prior functions from legacy API, deprecated */
++extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit,
++ u32 inslot, u32 outslot, u16 secretlen,
++ u8 *keymod, u16 keymodlen);
++extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit,
++ u32 inslot, u32 outslot, u16 secretlen,
++ u8 *keymod, u16 keymodlen);
++
++/* Data structure to hold per-slot information */
++struct keystore_data_slot_info {
++ u8 allocated; /* Track slot assignments */
++ u32 key_length; /* Size of the key */
++};
++
++/* Data structure to hold keystore information */
++struct keystore_data {
++ void *base_address; /* Virtual base of secure memory pages */
++ void *phys_address; /* Physical base of secure memory pages */
++ u32 slot_count; /* Number of slots in the keystore */
++ struct keystore_data_slot_info *slot; /* Per-slot information */
++};
++
++/* store the detected attributes of a secure memory page */
++struct sm_page_descriptor {
++ u16 phys_pagenum; /* may be discontiguous */
++ u16 own_part; /* Owning partition */
++ void *pg_base; /* Calculated virtual address */
++ void *pg_phys; /* Calculated physical address */
++ struct keystore_data *ksdata;
++};
++
++struct caam_drv_private_sm {
++ struct device *parentdev; /* this ends up as the controller */
++ struct device *smringdev; /* ring that owns this instance */
++ struct platform_device *sm_pdev; /* Secure Memory platform device */
++ spinlock_t kslock ____cacheline_aligned;
++
++ /* Default parameters for geometry */
++ u32 max_pages; /* maximum pages this instance can support */
++ u32 top_partition; /* highest partition number in this instance */
++ u32 top_page; /* highest page number in this instance */
++ u32 page_size; /* page size */
++ u32 slot_size; /* selected size of each storage block */
++
++ /* Partition/Page Allocation Map */
++ u32 localpages; /* Number of pages we can access */
++ struct sm_page_descriptor *pagedesc; /* Allocated per-page */
++
++ /* Installed handlers for keystore access */
++ int (*data_init)(struct device *dev, u32 unit);
++ void (*data_cleanup)(struct device *dev, u32 unit);
++ int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot);
++ int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot);
++ void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle);
++ void *(*slot_get_physical)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle);
++ u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle);
++};
++
++#endif /* SM_H */
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/sm_store.c linux-3.14.72/drivers/crypto/caam/sm_store.c
+--- linux-3.14.72.orig/drivers/crypto/caam/sm_store.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/crypto/caam/sm_store.c 2016-06-19 22:11:55.117152342 +0200
+@@ -0,0 +1,1169 @@
++
++/*
++ * CAAM Secure Memory Storage Interface
++ * Copyright (C) 2008-2015 Freescale Semiconductor, Inc.
++ *
++ * Loosely based on the SHW Keystore API for SCC/SCC2
++ * Experimental implementation and NOT intended for upstream use. Expect
++ * this interface to be amended significantly in the future once it becomes
++ * integrated into live applications.
++ *
++ * Known issues:
++ *
++ * - Executes one instance of an secure memory "driver". This is tied to the
++ * fact that job rings can't run as standalone instances in the present
++ * configuration.
++ *
++ * - It does not expose a userspace interface. The value of a userspace
++ * interface for access to secrets is a point for further architectural
++ * discussion.
++ *
++ * - Partition/permission management is not part of this interface. It
++ * depends on some level of "knowledge" agreed upon between bootloader,
++ * provisioning applications, and OS-hosted software (which uses this
++ * driver).
++ *
++ * - No means of identifying the location or purpose of secrets managed by
++ * this interface exists; "slot location" and format of a given secret
++ * needs to be agreed upon between bootloader, provisioner, and OS-hosted
++ * application.
++ */
++
++#include "compat.h"
++#include "regs.h"
++#include "jr.h"
++#include "desc.h"
++#include "intern.h"
++#include "error.h"
++#include "sm.h"
++
++#define SECMEM_KEYMOD_LEN 8
++#define GENMEM_KEYMOD_LEN 16
++
++#ifdef SM_DEBUG_CONT
++void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ u32 i, *smdata;
++
++ dev_info(dev, "physical page %d content at 0x%08x\n",
++ pgdesc->phys_pagenum, pgdesc->pg_base);
++ smdata = pgdesc->pg_base;
++ for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4)
++ dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
++ (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2],
++ smdata[i+3]);
++}
++#endif
++
++#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */
++
++/*
++ * Construct a black key conversion job descriptor
++ *
++ * This function constructs a job descriptor capable of performing
++ * a key blackening operation on a plaintext secure memory resident object.
++ *
++ * - desc pointer to a pointer to the descriptor generated by this
++ * function. Caller will be responsible to kfree() this
++ * descriptor after execution.
++ * - key physical pointer to the plaintext, which will also hold
++ * the result. Since encryption occurs in place, caller must
++ * ensure that the space is large enough to accommodate the
++ * blackened key
++ * - keysz size of the plaintext
++ * - auth if a CCM-covered key is required, use KEY_COVER_CCM, else
++ * use KEY_COVER_ECB.
++ *
++ * KEY to key1 from @key_addr LENGTH 16 BYTES;
++ * FIFO STORE from key1[ecb] TO @key_addr LENGTH 16 BYTES;
++ *
++ * Note that this variant uses the JDKEK only; it does not accommodate the
++ * trusted key encryption key at this time.
++ *
++ */
++static int blacken_key_jobdesc(u32 **desc, void *key, u16 keysz, bool auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /* Load key to class 1 key register */
++ tmpdesc[idx++] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK);
++ tmpdesc[idx++] = (u32)key;
++
++ /* ...and write back out via FIFO store*/
++ tmpdesc[idx] = CMD_FIFO_STORE | CLASS_1 | (keysz & KEY_LENGTH_MASK);
++
++ /* plus account for ECB/CCM option in FIFO_STORE */
++ if (auth == KEY_COVER_ECB)
++ tmpdesc[idx] |= FIFOST_TYPE_KEY_KEK;
++ else
++ tmpdesc[idx] |= FIFOST_TYPE_KEY_CCM_JKEK;
++
++ idx++;
++ tmpdesc[idx++] = (u32)key;
++
++ /* finish off the job header */
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ /* now allocate execution buffer and coat it with executable */
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++
++ return dsize;
++}
++
++/*
++ * Construct a blob encapsulation job descriptor
++ *
++ * This function dynamically constructs a blob encapsulation job descriptor
++ * from the following arguments:
++ *
++ * - desc pointer to a pointer to the descriptor generated by this
++ * function. Caller will be responsible to kfree() this
++ * descriptor after execution.
++ * - keymod Physical pointer to a key modifier, which must reside in a
++ * contiguous piece of memory. Modifier will be assumed to be
++ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long
++ * for a blob of type SM_GENMEM (see blobtype argument).
++ * - secretbuf Physical pointer to a secret, normally a black or red key,
++ * possibly residing within an accessible secure memory page,
++ * of the secret to be encapsulated to an output blob.
++ * - outbuf Physical pointer to the destination buffer to receive the
++ * encapsulated output. This buffer will need to be 48 bytes
++ * larger than the input because of the added encapsulation data.
++ * The generated descriptor will account for the increase in size,
++ * but the caller must also account for this increase in the
++ * buffer allocator.
++ * - secretsz Size of input secret, in bytes. This is limited to 65536
++ * less the size of blob overhead, since the length embeds into
++ * DECO pointer in/out instructions.
++ * - keycolor Determines if the source data is covered (black key) or
++ * plaintext (red key). RED_KEY or BLACK_KEY are defined in
++ * for this purpose.
++ * - blobtype Determine if encapsulated blob should be a secure memory
++ * blob (SM_SECMEM), with partition data embedded with key
++ * material, or a general memory blob (SM_GENMEM).
++ * - auth If BLACK_KEY source is covered via AES-CCM, specify
++ * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB).
++ *
++ * Upon completion, desc points to a buffer containing a CAAM job
++ * descriptor which encapsulates data into an externally-storable blob
++ * suitable for use across power cycles.
++ *
++ * This is an example of a black key encapsulation job into a general memory
++ * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note
++ * the output 48 bytes longer than the input:
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400010 ld: ccb2-key len=16 offs=0
++ * [02] 08144891 ptr->@0x08144891
++ * [03] F800003A seqoutptr: len=58
++ * [04] 01000000 out_ptr->@0x01000000
++ * [05] F000000A seqinptr: len=10
++ * [06] 09745090 in_ptr->@0x09745090
++ * [07] 870D0004 operation: encap blob reg=memory, black, format=normal
++ *
++ * This is an example of a red key encapsulation job for storing a red key
++ * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset
++ * in the LOAD instruction; this accounts for blob permission storage:
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400C08 ld: ccb2-key len=8 offs=12
++ * [02] 087D0784 ptr->@0x087d0784
++ * [03] F8000050 seqoutptr: len=80
++ * [04] 09251BB2 out_ptr->@0x09251bb2
++ * [05] F0000020 seqinptr: len=32
++ * [06] 40000F31 in_ptr->@0x40000f31
++ * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem,
++ * format=normal
++ *
++ * Note: this function only generates 32-bit pointers at present, and should
++ * be refactored using a scheme that allows both 32 and 64 bit addressing
++ */
++
++static int blob_encap_jobdesc(u32 **desc, dma_addr_t keymod,
++ void *secretbuf, dma_addr_t outbuf,
++ u16 secretsz, u8 keycolor, u8 blobtype, u8 auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /*
++ * Key modifier works differently for secure/general memory blobs
++ * This accounts for the permission/protection data encapsulated
++ * within the blob if a secure memory blob is requested
++ */
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK)
++ | (8 & LDST_LEN_MASK);
++ else /* is general memory blob */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /*
++ * Encapsulation output must include space for blob key encryption
++ * key and MAC tag
++ */
++ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (secretsz + BLOB_OVERHEAD);
++ tmpdesc[idx++] = (u32)outbuf;
++
++ /* Input data, should be somewhere in secure memory */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz;
++ tmpdesc[idx++] = (u32)secretbuf;
++
++ /* Set blob encap, then color */
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB;
++
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM;
++
++ if (auth == KEY_COVER_CCM)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ if (keycolor == BLACK_KEY)
++ tmpdesc[idx] |= OP_PCL_BLOB_BLACK;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++/*
++ * Construct a blob decapsulation job descriptor
++ *
++ * This function dynamically constructs a blob decapsulation job descriptor
++ * from the following arguments:
++ *
++ * - desc pointer to a pointer to the descriptor generated by this
++ * function. Caller will be responsible to kfree() this
++ * descriptor after execution.
++ * - keymod Physical pointer to a key modifier, which must reside in a
++ * contiguous piece of memory. Modifier will be assumed to be
++ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long
++ * for a blob of type SM_GENMEM (see blobtype argument).
++ * - blobbuf Physical pointer (into external memory) of the blob to
++ * be decapsulated. Blob must reside in a contiguous memory
++ * segment.
++ * - outbuf Physical pointer of the decapsulated output, possibly into
++ * a location within a secure memory page. Must be contiguous.
++ * - secretsz Size of encapsulated secret in bytes (not the size of the
++ * input blob).
++ * - keycolor Determines if decapsulated content is encrypted (BLACK_KEY)
++ * or left as plaintext (RED_KEY).
++ * - blobtype Determine if encapsulated blob should be a secure memory
++ * blob (SM_SECMEM), with partition data embedded with key
++ * material, or a general memory blob (SM_GENMEM).
++ * - auth If decapsulation path is specified by BLACK_KEY, then if
++ * AES-CCM is requested for key covering use KEY_COVER_CCM, else
++ * use AES-ECB (KEY_COVER_ECB).
++ *
++ * Upon completion, desc points to a buffer containing a CAAM job descriptor
++ * that decapsulates a key blob from external memory into a black (encrypted)
++ * key or red (plaintext) content.
++ *
++ * This is an example of a black key decapsulation job from a general memory
++ * blob. Notice the 16-byte key modifier in the LOAD instruction.
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400010 ld: ccb2-key len=16 offs=0
++ * [02] 08A63B7F ptr->@0x08a63b7f
++ * [03] F8000010 seqoutptr: len=16
++ * [04] 01000000 out_ptr->@0x01000000
++ * [05] F000003A seqinptr: len=58
++ * [06] 01000010 in_ptr->@0x01000010
++ * [07] 860D0004 operation: decap blob reg=memory, black, format=normal
++ *
++ * This is an example of a red key decapsulation job for restoring a red key
++ * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset
++ * in the LOAD instruction:
++ *
++ * [00] B0800008 jobhdr: stidx=0 len=8
++ * [01] 14400C08 ld: ccb2-key len=8 offs=12
++ * [02] 01000000 ptr->@0x01000000
++ * [03] F8000020 seqoutptr: len=32
++ * [04] 400000E6 out_ptr->@0x400000e6
++ * [05] F0000050 seqinptr: len=80
++ * [06] 08F0C0EA in_ptr->@0x08f0c0ea
++ * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem,
++ * format=normal
++ *
++ * Note: this function only generates 32-bit pointers at present, and should
++ * be refactored using a scheme that allows both 32 and 64 bit addressing
++ */
++
++static int blob_decap_jobdesc(u32 **desc, dma_addr_t keymod, dma_addr_t blobbuf,
++ u8 *outbuf, u16 secretsz, u8 keycolor,
++ u8 blobtype, u8 auth)
++{
++ u32 *tdesc, tmpdesc[INITIAL_DESCSZ];
++ u16 dsize, idx;
++
++ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32));
++ idx = 1;
++
++ /* Load key modifier */
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY |
++ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK)
++ | (8 & LDST_LEN_MASK);
++ else /* is general memory blob */
++ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB |
++ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK);
++
++ tmpdesc[idx++] = (u32)keymod;
++
++ /* Compensate BKEK + MAC tag over size of encapsulated secret */
++ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + BLOB_OVERHEAD);
++ tmpdesc[idx++] = (u32)blobbuf;
++ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | secretsz;
++ tmpdesc[idx++] = (u32)outbuf;
++
++ /* Decapsulate from secure memory partition to black blob */
++ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB;
++
++ if (blobtype == SM_SECMEM)
++ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM;
++
++ if (auth == KEY_COVER_CCM)
++ tmpdesc[idx] |= OP_PCL_BLOB_EKT;
++
++ if (keycolor == BLACK_KEY)
++ tmpdesc[idx] |= OP_PCL_BLOB_BLACK;
++
++ idx++;
++ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK);
++ dsize = idx * sizeof(u32);
++
++ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA);
++ if (tdesc == NULL)
++ return 0;
++
++ memcpy(tdesc, tmpdesc, dsize);
++ *desc = tdesc;
++ return dsize;
++}
++
++/*
++ * Pseudo-synchronous ring access functions for carrying out key
++ * encapsulation and decapsulation
++ */
++
++struct sm_key_job_result {
++ int error;
++ struct completion completion;
++};
++
++void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context)
++{
++ struct sm_key_job_result *res = context;
++
++ res->error = err; /* save off the error for postprocessing */
++ complete(&res->completion); /* mark us complete */
++}
++
++static int sm_key_job(struct device *ksdev, u32 *jobdesc)
++{
++ struct sm_key_job_result testres;
++ struct caam_drv_private_sm *kspriv;
++ int rtn = 0;
++
++ kspriv = dev_get_drvdata(ksdev);
++
++ init_completion(&testres.completion);
++
++ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done,
++ &testres);
++ if (!rtn) {
++ wait_for_completion_interruptible(&testres.completion);
++ rtn = testres.error;
++ }
++ return rtn;
++}
++
++/*
++ * Following section establishes the default methods for keystore access
++ * They are NOT intended for use external to this module
++ *
++ * In the present version, these are the only means for the higher-level
++ * interface to deal with the mechanics of accessing the phyiscal keystore
++ */
++
++
++int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++ u32 i;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size);
++#endif
++
++ if (size > smpriv->slot_size)
++ return -EKEYREJECTED;
++
++ for (i = 0; i < ksdata->slot_count; i++) {
++ if (ksdata->slot[i].allocated == 0) {
++ ksdata->slot[i].allocated = 1;
++ (*slot) = i;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_alloc(): new slot %d allocated\n",
++ *slot);
++#endif
++ return 0;
++ }
++ }
++
++ return -ENOSPC;
++}
++EXPORT_SYMBOL(slot_alloc);
++
++int slot_dealloc(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++ u8 __iomem *slotdata;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot);
++#endif
++ if (slot >= ksdata->slot_count)
++ return -EINVAL;
++ slotdata = ksdata->base_address + slot * smpriv->slot_size;
++
++ if (ksdata->slot[slot].allocated == 1) {
++ /* Forcibly overwrite the data from the keystore */
++ memset(ksdata->base_address + slot * smpriv->slot_size, 0,
++ smpriv->slot_size);
++
++ ksdata->slot[slot].allocated = 0;
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_dealloc(): slot %d released\n", slot);
++#endif
++ return 0;
++ }
++
++ return -EINVAL;
++}
++EXPORT_SYMBOL(slot_dealloc);
++
++void *slot_get_address(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ if (slot >= ksdata->slot_count)
++ return NULL;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot,
++ (u32)ksdata->base_address + slot * smpriv->slot_size);
++#endif
++
++ return ksdata->base_address + slot * smpriv->slot_size;
++}
++
++void *slot_get_physical(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ if (slot >= ksdata->slot_count)
++ return NULL;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_physical(): slot %d is 0x%08x\n", slot,
++ (u32)ksdata->phys_address + slot * smpriv->slot_size);
++#endif
++
++ return ksdata->phys_address + slot * smpriv->slot_size;
++}
++
++u32 slot_get_base(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ /*
++ * There could potentially be more than one secure partition object
++ * associated with this keystore. For now, there is just one.
++ */
++
++ (void)slot;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n",
++ slot, (u32)ksdata->base_address);
++#endif
++
++ return (u32)(ksdata->base_address);
++}
++
++u32 slot_get_offset(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata;
++
++ if (slot >= ksdata->slot_count)
++ return -EINVAL;
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot,
++ slot * smpriv->slot_size);
++#endif
++
++ return slot * smpriv->slot_size;
++}
++
++u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++
++#ifdef SM_DEBUG
++ dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot,
++ smpriv->slot_size);
++#endif
++ /* All slots are the same size in the default implementation */
++ return smpriv->slot_size;
++}
++
++
++
++int kso_init_data(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ struct keystore_data *keystore_data = NULL;
++ u32 slot_count;
++ u32 keystore_data_size;
++
++ /*
++ * Calculate the required size of the keystore data structure, based
++ * on the number of keys that can fit in the partition.
++ */
++ slot_count = smpriv->page_size / smpriv->slot_size;
++#ifdef SM_DEBUG
++ dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count);
++#endif
++
++ keystore_data_size = sizeof(struct keystore_data) +
++ slot_count *
++ sizeof(struct keystore_data_slot_info);
++
++ keystore_data = kzalloc(keystore_data_size, GFP_KERNEL);
++
++ if (keystore_data == NULL) {
++ retval = -ENOSPC;
++ goto out;
++ }
++
++#ifdef SM_DEBUG
++ dev_info(dev, "kso_init_data: keystore data size = %d\n",
++ keystore_data_size);
++#endif
++
++ /*
++ * Place the slot information structure directly after the keystore data
++ * structure.
++ */
++ keystore_data->slot = (struct keystore_data_slot_info *)
++ (keystore_data + 1);
++ keystore_data->slot_count = slot_count;
++
++ smpriv->pagedesc[unit].ksdata = keystore_data;
++ smpriv->pagedesc[unit].ksdata->base_address =
++ smpriv->pagedesc[unit].pg_base;
++ smpriv->pagedesc[unit].ksdata->phys_address =
++ smpriv->pagedesc[unit].pg_phys;
++
++ retval = 0;
++
++out:
++ if (retval != 0)
++ if (keystore_data != NULL)
++ kfree(keystore_data);
++
++
++ return retval;
++}
++
++void kso_cleanup_data(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ struct keystore_data *keystore_data = NULL;
++
++ if (smpriv->pagedesc[unit].ksdata != NULL)
++ keystore_data = smpriv->pagedesc[unit].ksdata;
++
++ /* Release the allocated keystore management data */
++ kfree(smpriv->pagedesc[unit].ksdata);
++
++ return;
++}
++
++
++
++/*
++ * Keystore management section
++ */
++
++void sm_init_keystore(struct device *dev)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++ smpriv->data_init = kso_init_data;
++ smpriv->data_cleanup = kso_cleanup_data;
++ smpriv->slot_alloc = slot_alloc;
++ smpriv->slot_dealloc = slot_dealloc;
++ smpriv->slot_get_address = slot_get_address;
++ smpriv->slot_get_physical = slot_get_physical;
++ smpriv->slot_get_base = slot_get_base;
++ smpriv->slot_get_offset = slot_get_offset;
++ smpriv->slot_get_slot_size = slot_get_slot_size;
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_init_keystore(): handlers installed\n");
++#endif
++}
++EXPORT_SYMBOL(sm_init_keystore);
++
++/* Return available pages/units */
++u32 sm_detect_keystore_units(struct device *dev)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++ return smpriv->localpages;
++}
++EXPORT_SYMBOL(sm_detect_keystore_units);
++
++/*
++ * Do any keystore specific initializations
++ */
++int sm_establish_keystore(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit);
++#endif
++
++ if (smpriv->data_init == NULL)
++ return -EINVAL;
++
++ /* Call the data_init function for any user setup */
++ return smpriv->data_init(dev, unit);
++}
++EXPORT_SYMBOL(sm_establish_keystore);
++
++void sm_release_keystore(struct device *dev, u32 unit)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++
++#ifdef SM_DEBUG
++ dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit);
++#endif
++ if ((smpriv != NULL) && (smpriv->data_cleanup != NULL))
++ smpriv->data_cleanup(dev, unit);
++
++ return;
++}
++EXPORT_SYMBOL(sm_release_keystore);
++
++/*
++ * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to
++ * the keystore
++ */
++int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++
++ spin_lock(&smpriv->kslock);
++
++ if ((smpriv->slot_alloc == NULL) ||
++ (smpriv->pagedesc[unit].ksdata == NULL))
++ goto out;
++
++ retval = smpriv->slot_alloc(dev, unit, size, slot);
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_alloc);
++
++int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++
++ spin_lock(&smpriv->kslock);
++
++ if ((smpriv->slot_alloc == NULL) ||
++ (smpriv->pagedesc[unit].ksdata == NULL))
++ goto out;
++
++ retval = smpriv->slot_dealloc(dev, unit, slot);
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_dealloc);
++
++int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot,
++ const u8 *key_data, u32 key_length)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ u32 slot_size;
++ u32 i;
++ u8 __iomem *slot_location;
++
++ spin_lock(&smpriv->kslock);
++
++ slot_size = smpriv->slot_get_slot_size(dev, unit, slot);
++
++ if (key_length > slot_size) {
++ retval = -EFBIG;
++ goto out;
++ }
++
++ slot_location = smpriv->slot_get_address(dev, unit, slot);
++
++ for (i = 0; i < key_length; i++)
++ slot_location[i] = key_data[i];
++
++ retval = 0;
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_load);
++
++int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot,
++ u32 key_length, u8 *key_data)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = -EINVAL;
++ u8 __iomem *slot_addr;
++ u32 slot_size;
++
++ spin_lock(&smpriv->kslock);
++
++ slot_addr = smpriv->slot_get_address(dev, unit, slot);
++ slot_size = smpriv->slot_get_slot_size(dev, unit, slot);
++
++ if (key_length > slot_size) {
++ retval = -EKEYREJECTED;
++ goto out;
++ }
++
++ memcpy(key_data, slot_addr, key_length);
++ retval = 0;
++
++out:
++ spin_unlock(&smpriv->kslock);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_read);
++
++/*
++ * Blacken a clear key in a slot. Operates "in place".
++ * Limited to class 1 keys at the present time
++ */
++int sm_keystore_cover_key(struct device *dev, u32 unit, u32 slot,
++ u16 key_length, u8 keyauth)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = 0;
++ u8 __iomem *slotaddr;
++ void *slotphys;
++ u32 dsize, jstat;
++ u32 __iomem *coverdesc = NULL;
++
++ /* Get the address of the object in the slot */
++ slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot);
++ slotphys = (u8 *)smpriv->slot_get_physical(dev, unit, slot);
++
++ dsize = blacken_key_jobdesc(&coverdesc, slotphys, key_length, keyauth);
++ if (!dsize)
++ return -ENOMEM;
++ jstat = sm_key_job(dev, coverdesc);
++ if (jstat)
++ retval = -EIO;
++
++ kfree(coverdesc);
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_cover_key);
++
++/* Export a black/red key to a blob in external memory */
++int sm_keystore_slot_export(struct device *dev, u32 unit, u32 slot, u8 keycolor,
++ u8 keyauth, u8 *outbuf, u16 keylen, u8 *keymod)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = 0;
++ u8 __iomem *slotaddr, *lkeymod;
++ u8 __iomem *slotphys;
++ dma_addr_t keymod_dma, outbuf_dma;
++ u32 dsize, jstat;
++ u32 __iomem *encapdesc = NULL;
++
++ /* Get the base address(es) of the specified slot */
++ slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot);
++ slotphys = smpriv->slot_get_physical(dev, unit, slot);
++
++ /* Build/map/flush the key modifier */
++ lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA);
++ memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN);
++ keymod_dma = dma_map_single(dev, lkeymod, SECMEM_KEYMOD_LEN,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(dev, keymod_dma, SECMEM_KEYMOD_LEN,
++ DMA_TO_DEVICE);
++
++ outbuf_dma = dma_map_single(dev, outbuf, keylen + BLOB_OVERHEAD,
++ DMA_FROM_DEVICE);
++
++ /* Build the encapsulation job descriptor */
++ dsize = blob_encap_jobdesc(&encapdesc, keymod_dma, slotphys, outbuf_dma,
++ keylen, keycolor, SM_SECMEM, keyauth);
++ if (!dsize) {
++ dev_err(dev, "can't alloc an encapsulation descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++ jstat = sm_key_job(dev, encapdesc);
++ dma_sync_single_for_cpu(dev, outbuf_dma, keylen + BLOB_OVERHEAD,
++ DMA_FROM_DEVICE);
++ if (jstat)
++ retval = -EIO;
++
++out:
++ dma_unmap_single(dev, outbuf_dma, keylen + BLOB_OVERHEAD,
++ DMA_FROM_DEVICE);
++ dma_unmap_single(dev, keymod_dma, SECMEM_KEYMOD_LEN, DMA_TO_DEVICE);
++ kfree(encapdesc);
++
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_export);
++
++/* Import a black/red key from a blob residing in external memory */
++int sm_keystore_slot_import(struct device *dev, u32 unit, u32 slot, u8 keycolor,
++ u8 keyauth, u8 *inbuf, u16 keylen, u8 *keymod)
++{
++ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev);
++ int retval = 0;
++ u8 __iomem *slotaddr, *lkeymod;
++ u8 __iomem *slotphys;
++ dma_addr_t keymod_dma, inbuf_dma;
++ u32 dsize, jstat;
++ u32 __iomem *decapdesc = NULL;
++
++ /* Get the base address(es) of the specified slot */
++ slotaddr = (u8 *)smpriv->slot_get_address(dev, unit, slot);
++ slotphys = smpriv->slot_get_physical(dev, unit, slot);
++
++ /* Build/map/flush the key modifier */
++ lkeymod = kmalloc(SECMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA);
++ memcpy(lkeymod, keymod, SECMEM_KEYMOD_LEN);
++ keymod_dma = dma_map_single(dev, lkeymod, SECMEM_KEYMOD_LEN,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(dev, keymod_dma, SECMEM_KEYMOD_LEN,
++ DMA_TO_DEVICE);
++
++ inbuf_dma = dma_map_single(dev, inbuf, keylen + BLOB_OVERHEAD,
++ DMA_TO_DEVICE);
++ dma_sync_single_for_device(dev, inbuf_dma, keylen + BLOB_OVERHEAD,
++ DMA_TO_DEVICE);
++
++ /* Build the encapsulation job descriptor */
++ dsize = blob_decap_jobdesc(&decapdesc, keymod_dma, inbuf_dma, slotphys,
++ keylen, keycolor, SM_SECMEM, keyauth);
++ if (!dsize) {
++ dev_err(dev, "can't alloc a decapsulation descriptor\n");
++ retval = -ENOMEM;
++ goto out;
++ }
++
++ jstat = sm_key_job(dev, decapdesc);
++
++ /*
++ * May want to expand upon error meanings a bit. Any CAAM status
++ * is reported as EIO, but we might want to look for something more
++ * meaningful for something like an ICV error on restore, otherwise
++ * the caller is left guessing.
++ */
++ if (jstat)
++ retval = -EIO;
++
++out:
++ dma_unmap_single(dev, inbuf_dma, keylen + BLOB_OVERHEAD,
++ DMA_TO_DEVICE);
++ dma_unmap_single(dev, keymod_dma, SECMEM_KEYMOD_LEN, DMA_TO_DEVICE);
++ kfree(decapdesc);
++
++ return retval;
++}
++EXPORT_SYMBOL(sm_keystore_slot_import);
++
++/*
++ * Initialization/shutdown subsystem
++ * Assumes statically-invoked startup/shutdown from the controller driver
++ * for the present time, to be reworked when a device tree becomes
++ * available. This code will not modularize in present form.
++ *
++ * Also, simply uses ring 0 for execution at the present
++ */
++
++int caam_sm_startup(struct platform_device *pdev)
++{
++ struct device *ctrldev, *smdev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_sm *smpriv;
++ struct caam_drv_private_jr *jrpriv; /* need this for reg page */
++ struct platform_device *sm_pdev;
++ struct sm_page_descriptor *lpagedesc;
++ u32 page, pgstat, lpagect, detectedpage;
++
++ struct device_node *np;
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++
++ /*
++ * Set up the private block for secure memory
++ * Only one instance is possible
++ */
++ smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL);
++ if (smpriv == NULL) {
++ dev_err(ctrldev, "can't alloc private mem for secure memory\n");
++ return -ENOMEM;
++ }
++ smpriv->parentdev = ctrldev; /* copy of parent dev is handy */
++
++ /* Create the dev */
++#ifdef CONFIG_OF
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm");
++ sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev);
++#else
++ sm_pdev = platform_device_register_data(ctrldev, "caam_sm", 0,
++ smpriv,
++ sizeof(struct caam_drv_private_sm));
++#endif
++ if (sm_pdev == NULL) {
++ kfree(smpriv);
++ return -EINVAL;
++ }
++
++ /* Save a pointer to the platform device for Secure Memory */
++ smpriv->sm_pdev = sm_pdev;
++ smdev = &sm_pdev->dev;
++ dev_set_drvdata(smdev, smpriv);
++ ctrlpriv->smdev = smdev;
++
++ /*
++ * Collect configuration limit data for reference
++ * This batch comes from the partition data/vid registers in perfmon
++ */
++ smpriv->max_pages = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_NUMPG_MASK) >>
++ SMPART_MAX_NUMPG_SHIFT) + 1;
++ smpriv->top_partition = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_PNUM_MASK) >>
++ SMPART_MAX_PNUM_SHIFT) + 1;
++ smpriv->top_page = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart)
++ & SMPART_MAX_PG_MASK) >> SMPART_MAX_PG_SHIFT) + 1;
++ smpriv->page_size = 1024 << ((rd_reg32(&ctrlpriv->ctrl->perfmon.smvid)
++ & SMVID_PG_SIZE_MASK) >> SMVID_PG_SIZE_SHIFT);
++ smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE;
++
++#ifdef SM_DEBUG
++ dev_info(smdev, "max pages = %d, top partition = %d\n",
++ smpriv->max_pages, smpriv->top_partition);
++ dev_info(smdev, "top page = %d, page size = %d (total = %d)\n",
++ smpriv->top_page, smpriv->page_size,
++ smpriv->top_page * smpriv->page_size);
++ dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size);
++#endif
++
++ /*
++ * Now probe for partitions/pages to which we have access. Note that
++ * these have likely been set up by a bootloader or platform
++ * provisioning application, so we have to assume that we "inherit"
++ * a configuration and work within the constraints of what it might be.
++ *
++ * Assume use of the zeroth ring in the present iteration (until
++ * we can divorce the controller and ring drivers, and then assign
++ * an SM instance to any ring instance).
++ */
++ smpriv->smringdev = &ctrlpriv->jrpdev[0]->dev;
++ jrpriv = dev_get_drvdata(smpriv->smringdev);
++ lpagect = 0;
++ lpagedesc = kzalloc(sizeof(struct sm_page_descriptor)
++ * smpriv->max_pages, GFP_KERNEL);
++ if (lpagedesc == NULL) {
++ kfree(smpriv);
++ return -ENOMEM;
++ }
++
++ for (page = 0; page < smpriv->max_pages; page++) {
++ wr_reg32(&jrpriv->rregs->sm_cmd,
++ ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) |
++ (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK));
++ pgstat = rd_reg32(&jrpriv->rregs->sm_status);
++ if (((pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT)
++ == SMCS_PGOWN_OWNED) { /* our page? */
++ lpagedesc[page].phys_pagenum =
++ (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT;
++ lpagedesc[page].own_part =
++ (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK;
++ lpagedesc[page].pg_base = ctrlpriv->sm_base +
++ ((smpriv->page_size * page) / sizeof(u32));
++ /* FIXME: get base address from platform property... */
++ lpagedesc[page].pg_phys = (u32 *)0x00100000 +
++ ((smpriv->page_size * page) / sizeof(u32));
++ lpagect++;
++#ifdef SM_DEBUG
++ dev_info(smdev,
++ "physical page %d, owning partition = %d\n",
++ lpagedesc[page].phys_pagenum,
++ lpagedesc[page].own_part);
++#endif
++ }
++ }
++
++ smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect,
++ GFP_KERNEL);
++ if (smpriv->pagedesc == NULL) {
++ kfree(lpagedesc);
++ kfree(smpriv);
++ return -ENOMEM;
++ }
++ smpriv->localpages = lpagect;
++
++ detectedpage = 0;
++ for (page = 0; page < smpriv->max_pages; page++) {
++ if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */
++ memcpy(&smpriv->pagedesc[detectedpage],
++ &lpagedesc[page],
++ sizeof(struct sm_page_descriptor));
++#ifdef SM_DEBUG_CONT
++ sm_show_page(smdev, &smpriv->pagedesc[detectedpage]);
++#endif
++ detectedpage++;
++ }
++ }
++
++ kfree(lpagedesc);
++
++ sm_init_keystore(smdev);
++
++ return 0;
++}
++
++void caam_sm_shutdown(struct platform_device *pdev)
++{
++ struct device *ctrldev, *smdev;
++ struct caam_drv_private *priv;
++ struct caam_drv_private_sm *smpriv;
++
++ ctrldev = &pdev->dev;
++ priv = dev_get_drvdata(ctrldev);
++ smdev = priv->smdev;
++
++ /* Return if resource not initialized by startup */
++ if (smdev == NULL)
++ return;
++
++ smpriv = dev_get_drvdata(smdev);
++
++ /* Remove Secure Memory Platform Device */
++ of_device_unregister(smpriv->sm_pdev);
++
++ kfree(smpriv->pagedesc);
++ kfree(smpriv);
++}
++EXPORT_SYMBOL(caam_sm_shutdown);
++#ifdef CONFIG_OF
++static void __exit caam_sm_exit(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return;
++
++ of_node_put(dev_node);
++
++ caam_sm_shutdown(pdev);
++
++ return;
++}
++
++static int __init caam_sm_init(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ of_node_get(dev_node);
++
++ caam_sm_startup(pdev);
++
++ return 0;
++}
++
++module_init(caam_sm_init);
++module_exit(caam_sm_exit);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM Secure Memory / Keystore");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
++#endif
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/sm_test.c linux-3.14.72/drivers/crypto/caam/sm_test.c
+--- linux-3.14.72.orig/drivers/crypto/caam/sm_test.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/crypto/caam/sm_test.c 2016-06-19 22:11:55.117152342 +0200
+@@ -0,0 +1,517 @@
++
++/*
++ * Secure Memory / Keystore Exemplification Module
++ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved
++ *
++ * This module has been overloaded as an example to show:
++ * - Secure memory subsystem initialization/shutdown
++ * - Allocation/deallocation of "slots" in a secure memory page
++ * - Loading and unloading of key material into slots
++ * - Covering of secure memory objects into "black keys" (ECB only at present)
++ * - Verification of key covering (by differentiation only)
++ * - Exportation of keys into secure memory blobs (with display of result)
++ * - Importation of keys from secure memory blobs (with display of result)
++ * - Verification of re-imported keys where possible.
++ *
++ * The module does not show the use of key objects as working key register
++ * source material at this time.
++ *
++ * This module can use a substantial amount of refactoring, which may occur
++ * after the API gets some mileage. Furthermore, expect this module to
++ * eventually disappear once the API is integrated into "real" software.
++ */
++
++#include "compat.h"
++#include "intern.h"
++#include "desc.h"
++#include "error.h"
++#include "jr.h"
++#include "sm.h"
++
++/* Fixed known pattern for a key modifier */
++static u8 skeymod[] = {
++ 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
++ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00
++};
++
++/* Fixed known pattern for a key */
++static u8 clrkey[] = {
++ 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07,
++ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
++ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
++ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
++ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
++ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
++ 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
++ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
++ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
++ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
++ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
++ 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
++ 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
++ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
++ 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
++ 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
++ 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
++ 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
++ 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
++ 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
++ 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
++ 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
++ 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
++ 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
++ 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
++ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
++ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
++ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
++ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
++ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
++ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
++ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff
++};
++
++static void key_display(struct device *dev, u8 *label, u16 size, u8 *key)
++{
++ unsigned i;
++
++ dev_info(dev, label);
++ for (i = 0; i < size; i += 8)
++ dev_info(dev,
++ "[%04d] %02x %02x %02x %02x %02x %02x %02x %02x\n",
++ i, key[i], key[i + 1], key[i + 2], key[i + 3],
++ key[i + 4], key[i + 5], key[i + 6], key[i + 7]);
++}
++
++int caam_sm_example_init(struct platform_device *pdev)
++{
++ struct device *ctrldev, *ksdev;
++ struct caam_drv_private *ctrlpriv;
++ struct caam_drv_private_sm *kspriv;
++ u32 unit, units;
++ int rtnval = 0;
++ u8 clrkey8[8], clrkey16[16], clrkey24[24], clrkey32[32];
++ u8 blkkey8[AES_BLOCK_PAD(8)], blkkey16[AES_BLOCK_PAD(16)];
++ u8 blkkey24[AES_BLOCK_PAD(24)], blkkey32[AES_BLOCK_PAD(32)];
++ u8 rstkey8[AES_BLOCK_PAD(8)], rstkey16[AES_BLOCK_PAD(16)];
++ u8 rstkey24[AES_BLOCK_PAD(24)], rstkey32[AES_BLOCK_PAD(32)];
++ u8 __iomem *blob8, *blob16, *blob24, *blob32;
++ u32 keyslot8, keyslot16, keyslot24, keyslot32 = 0;
++
++ blob8 = blob16 = blob24 = blob32 = NULL;
++
++ /*
++ * 3.5.x and later revs for MX6 should be able to ditch this
++ * and detect via dts property
++ */
++ ctrldev = &pdev->dev;
++ ctrlpriv = dev_get_drvdata(ctrldev);
++ ksdev = ctrlpriv->smdev;
++ kspriv = dev_get_drvdata(ksdev);
++ if (kspriv == NULL)
++ return -ENODEV;
++
++ /* What keystores are available ? */
++ units = sm_detect_keystore_units(ksdev);
++ if (!units)
++ dev_err(ksdev, "blkkey_ex: no keystore units available\n");
++
++ /*
++ * MX6 bootloader stores some stuff in unit 0, so let's
++ * use 1 or above
++ */
++ if (units < 2) {
++ dev_err(ksdev, "blkkey_ex: insufficient keystore units\n");
++ return -ENODEV;
++ }
++ unit = 1;
++
++ dev_info(ksdev, "blkkey_ex: %d keystore units available\n", units);
++
++ /* Initialize/Establish Keystore */
++ sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */
++
++ /*
++ * Now let's set up buffers for blobs in DMA-able memory. All are
++ * larger than need to be so that blob size can be seen.
++ */
++ blob8 = kzalloc(128, GFP_KERNEL | GFP_DMA);
++ blob16 = kzalloc(128, GFP_KERNEL | GFP_DMA);
++ blob24 = kzalloc(128, GFP_KERNEL | GFP_DMA);
++ blob32 = kzalloc(128, GFP_KERNEL | GFP_DMA);
++
++ if ((blob8 == NULL) || (blob16 == NULL) || (blob24 == NULL) ||
++ (blob32 == NULL)) {
++ rtnval = -ENOMEM;
++ dev_err(ksdev, "blkkey_ex: can't get blob buffers\n");
++ goto freemem;
++ }
++
++ /* Initialize clear keys with a known and recognizable pattern */
++ memcpy(clrkey8, clrkey, 8);
++ memcpy(clrkey16, clrkey, 16);
++ memcpy(clrkey24, clrkey, 24);
++ memcpy(clrkey32, clrkey, 32);
++
++ memset(blkkey8, 0, AES_BLOCK_PAD(8));
++ memset(blkkey16, 0, AES_BLOCK_PAD(16));
++ memset(blkkey24, 0, AES_BLOCK_PAD(24));
++ memset(blkkey32, 0, AES_BLOCK_PAD(32));
++
++ memset(rstkey8, 0, AES_BLOCK_PAD(8));
++ memset(rstkey16, 0, AES_BLOCK_PAD(16));
++ memset(rstkey24, 0, AES_BLOCK_PAD(24));
++ memset(rstkey32, 0, AES_BLOCK_PAD(32));
++
++ /*
++ * Allocate keyslots. Since we're going to blacken keys in-place,
++ * we want slots big enough to pad out to the next larger AES blocksize
++ * so pad them out.
++ */
++ if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(8), &keyslot8))
++ goto dealloc;
++
++ if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(16), &keyslot16))
++ goto dealloc;
++
++ if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(24), &keyslot24))
++ goto dealloc;
++
++ if (sm_keystore_slot_alloc(ksdev, unit, AES_BLOCK_PAD(32), &keyslot32))
++ goto dealloc;
++
++
++ /* Now load clear key data into the newly allocated slots */
++ if (sm_keystore_slot_load(ksdev, unit, keyslot8, clrkey8, 8))
++ goto dealloc;
++
++ if (sm_keystore_slot_load(ksdev, unit, keyslot16, clrkey16, 16))
++ goto dealloc;
++
++ if (sm_keystore_slot_load(ksdev, unit, keyslot24, clrkey24, 24))
++ goto dealloc;
++
++ if (sm_keystore_slot_load(ksdev, unit, keyslot32, clrkey32, 32))
++ goto dealloc;
++
++ /*
++ * All cleartext keys are loaded into slots (in an unprotected
++ * partition at this time)
++ *
++ * Cover keys in-place
++ */
++ if (sm_keystore_cover_key(ksdev, unit, keyslot8, 8, KEY_COVER_ECB)) {
++ dev_info(ksdev, "blkkey_ex: can't cover 64-bit key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_cover_key(ksdev, unit, keyslot16, 16, KEY_COVER_ECB)) {
++ dev_info(ksdev, "blkkey_ex: can't cover 128-bit key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_cover_key(ksdev, unit, keyslot24, 24, KEY_COVER_ECB)) {
++ dev_info(ksdev, "blkkey_ex: can't cover 192-bit key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_cover_key(ksdev, unit, keyslot32, 32, KEY_COVER_ECB)) {
++ dev_info(ksdev, "blkkey_ex: can't cover 256-bit key\n");
++ goto dealloc;
++ }
++
++ /*
++ * Keys should be covered and appear sufficiently "random"
++ * as a result of the covering (blackening) process. Assuming
++ * non-secure mode, read them back out for examination; they should
++ * appear as random data, completely differing from the clear
++ * inputs. So, this will read them back from secure memory and
++ * compare them. If they match the clear key, then the covering
++ * operation didn't occur.
++ */
++
++ if (sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8),
++ blkkey8)) {
++ dev_info(ksdev, "blkkey_ex: can't read 64-bit black key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_read(ksdev, unit, keyslot16, AES_BLOCK_PAD(16),
++ blkkey16)) {
++ dev_info(ksdev, "blkkey_ex: can't read 128-bit black key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_read(ksdev, unit, keyslot24, AES_BLOCK_PAD(24),
++ blkkey24)) {
++ dev_info(ksdev, "blkkey_ex: can't read 192-bit black key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_read(ksdev, unit, keyslot32, AES_BLOCK_PAD(32),
++ blkkey32)) {
++ dev_info(ksdev, "blkkey_ex: can't read 256-bit black key\n");
++ goto dealloc;
++ }
++
++
++ if (!memcmp(blkkey8, clrkey8, 8)) {
++ dev_info(ksdev, "blkkey_ex: 64-bit key cover failed\n");
++ goto dealloc;
++ }
++
++ if (!memcmp(blkkey16, clrkey16, 16)) {
++ dev_info(ksdev, "blkkey_ex: 128-bit key cover failed\n");
++ goto dealloc;
++ }
++
++ if (!memcmp(blkkey24, clrkey24, 24)) {
++ dev_info(ksdev, "blkkey_ex: 192-bit key cover failed\n");
++ goto dealloc;
++ }
++
++ if (!memcmp(blkkey32, clrkey32, 32)) {
++ dev_info(ksdev, "blkkey_ex: 256-bit key cover failed\n");
++ goto dealloc;
++ }
++
++
++ key_display(ksdev, "64-bit clear key:", 8, clrkey8);
++ key_display(ksdev, "64-bit black key:", AES_BLOCK_PAD(8), blkkey8);
++
++ key_display(ksdev, "128-bit clear key:", 16, clrkey16);
++ key_display(ksdev, "128-bit black key:", AES_BLOCK_PAD(16), blkkey16);
++
++ key_display(ksdev, "192-bit clear key:", 24, clrkey24);
++ key_display(ksdev, "192-bit black key:", AES_BLOCK_PAD(24), blkkey24);
++
++ key_display(ksdev, "256-bit clear key:", 32, clrkey32);
++ key_display(ksdev, "256-bit black key:", AES_BLOCK_PAD(32), blkkey32);
++
++ /*
++ * Now encapsulate all keys as SM blobs out to external memory
++ * Blobs will appear as random-looking blocks of data different
++ * from the original source key, and 48 bytes longer than the
++ * original key, to account for the extra data encapsulated within.
++ */
++ key_display(ksdev, "64-bit unwritten blob:", 96, blob8);
++ key_display(ksdev, "128-bit unwritten blob:", 96, blob16);
++ key_display(ksdev, "196-bit unwritten blob:", 96, blob24);
++ key_display(ksdev, "256-bit unwritten blob:", 96, blob32);
++
++ if (sm_keystore_slot_export(ksdev, unit, keyslot8, BLACK_KEY,
++ KEY_COVER_ECB, blob8, 8, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't encapsulate 64-bit key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_export(ksdev, unit, keyslot16, BLACK_KEY,
++ KEY_COVER_ECB, blob16, 16, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't encapsulate 128-bit key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_export(ksdev, unit, keyslot24, BLACK_KEY,
++ KEY_COVER_ECB, blob24, 24, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't encapsulate 192-bit key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_export(ksdev, unit, keyslot32, BLACK_KEY,
++ KEY_COVER_ECB, blob32, 32, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't encapsulate 256-bit key\n");
++ goto dealloc;
++ }
++
++ key_display(ksdev, "64-bit black key in blob:", 96, blob8);
++ key_display(ksdev, "128-bit black key in blob:", 96, blob16);
++ key_display(ksdev, "192-bit black key in blob:", 96, blob24);
++ key_display(ksdev, "256-bit black key in blob:", 96, blob32);
++
++ /*
++ * Now re-import black keys from secure-memory blobs stored
++ * in general memory from the previous operation. Since we are
++ * working with black keys, and since power has not cycled, the
++ * restored black keys should match the original blackened keys
++ * (this would not be true if the blobs were save in some non-volatile
++ * store, and power was cycled between the save and restore)
++ */
++ if (sm_keystore_slot_import(ksdev, unit, keyslot8, BLACK_KEY,
++ KEY_COVER_ECB, blob8, 8, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't decapsulate 64-bit blob\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_import(ksdev, unit, keyslot16, BLACK_KEY,
++ KEY_COVER_ECB, blob16, 16, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't decapsulate 128-bit blob\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_import(ksdev, unit, keyslot24, BLACK_KEY,
++ KEY_COVER_ECB, blob24, 24, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't decapsulate 196-bit blob\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_import(ksdev, unit, keyslot32, BLACK_KEY,
++ KEY_COVER_ECB, blob32, 32, skeymod)) {
++ dev_info(ksdev, "blkkey_ex: can't decapsulate 256-bit blob\n");
++ goto dealloc;
++ }
++
++
++ /*
++ * Blobs are now restored as black keys. Read those black keys back
++ * for a comparison with the original black key, they should match
++ */
++ if (sm_keystore_slot_read(ksdev, unit, keyslot8, AES_BLOCK_PAD(8),
++ rstkey8)) {
++ dev_info(ksdev,
++ "blkkey_ex: can't read restored 64-bit black key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_read(ksdev, unit, keyslot16, AES_BLOCK_PAD(16),
++ rstkey16)) {
++ dev_info(ksdev,
++ "blkkey_ex: can't read restored 128-bit black key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_read(ksdev, unit, keyslot24, AES_BLOCK_PAD(24),
++ rstkey24)) {
++ dev_info(ksdev,
++ "blkkey_ex: can't read restored 196-bit black key\n");
++ goto dealloc;
++ }
++
++ if (sm_keystore_slot_read(ksdev, unit, keyslot32, AES_BLOCK_PAD(32),
++ rstkey32)) {
++ dev_info(ksdev,
++ "blkkey_ex: can't read restored 256-bit black key\n");
++ goto dealloc;
++ }
++
++ key_display(ksdev, "restored 64-bit black key:", AES_BLOCK_PAD(8),
++ rstkey8);
++ key_display(ksdev, "restored 128-bit black key:", AES_BLOCK_PAD(16),
++ rstkey16);
++ key_display(ksdev, "restored 192-bit black key:", AES_BLOCK_PAD(24),
++ rstkey24);
++ key_display(ksdev, "restored 256-bit black key:", AES_BLOCK_PAD(32),
++ rstkey32);
++
++ /*
++ * Compare the restored black keys with the original blackened keys
++ * As long as we're operating within the same power cycle, a black key
++ * restored from a blob should match the original black key IF the
++ * key happens to be of a size that matches a multiple of the AES
++ * blocksize. Any key that is padded to fill the block size will not
++ * match, excepting a key that exceeds a block; only the first full
++ * blocks will match (assuming ECB).
++ *
++ * Therefore, compare the 16 and 32 bit keys, they should match.
++ * The 24 bit key can only match within the first 16 byte block.
++ */
++
++ if (memcmp(rstkey16, blkkey16, AES_BLOCK_PAD(16))) {
++ dev_info(ksdev, "blkkey_ex: 128-bit restored key mismatch\n");
++ rtnval--;
++ }
++
++ /* Only first AES block will match, remainder subject to padding */
++ if (memcmp(rstkey24, blkkey24, 16)) {
++ dev_info(ksdev, "blkkey_ex: 192-bit restored key mismatch\n");
++ rtnval--;
++ }
++
++ if (memcmp(rstkey32, blkkey32, AES_BLOCK_PAD(32))) {
++ dev_info(ksdev, "blkkey_ex: 256-bit restored key mismatch\n");
++ rtnval--;
++ }
++
++
++ /* Remove keys from keystore */
++dealloc:
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot8);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot16);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot24);
++ sm_keystore_slot_dealloc(ksdev, unit, keyslot32);
++
++
++ /* Free resources */
++freemem:
++ kfree(blob8);
++ kfree(blob16);
++ kfree(blob24);
++ kfree(blob32);
++
++ /* Disconnect from keystore and leave */
++ sm_release_keystore(ksdev, unit);
++
++ return rtnval;
++}
++EXPORT_SYMBOL(caam_sm_example_init);
++
++void caam_sm_example_shutdown(void)
++{
++ /* unused in present version */
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return;
++
++ of_node_get(dev_node);
++
++}
++
++static int __init caam_sm_test_init(void)
++{
++ struct device_node *dev_node;
++ struct platform_device *pdev;
++
++ /*
++ * Do of_find_compatible_node() then of_find_device_by_node()
++ * once a functional device tree is available
++ */
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
++ if (!dev_node) {
++ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
++ if (!dev_node)
++ return -ENODEV;
++ }
++
++ pdev = of_find_device_by_node(dev_node);
++ if (!pdev)
++ return -ENODEV;
++
++ of_node_put(dev_node);
++
++ caam_sm_example_init(pdev);
++
++ return 0;
++}
++
++
++/* Module-based initialization needs to wait for dev tree */
++#ifdef CONFIG_OF
++module_init(caam_sm_test_init);
++module_exit(caam_sm_example_shutdown);
++
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_DESCRIPTION("FSL CAAM Black Key Usage Example");
++MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD");
++#endif
+diff -Nur linux-3.14.72.orig/drivers/crypto/caam/snvsregs.h linux-3.14.72/drivers/crypto/caam/snvsregs.h
+--- linux-3.14.72.orig/drivers/crypto/caam/snvsregs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/crypto/caam/snvsregs.h 2016-06-19 22:11:55.117152342 +0200
+@@ -0,0 +1,237 @@
++/*
++ * SNVS hardware register-level view
++ *
++ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc., All Rights Reserved
++ */
++
++#ifndef SNVSREGS_H
++#define SNVSREGS_H
++
++#include <linux/types.h>
++#include <linux/io.h>
++
++/*
++ * SNVS High Power Domain
++ * Includes security violations, HA counter, RTC, alarm
++ */
++struct snvs_hp {
++ u32 lock; /* HPLR - HP Lock */
++ u32 cmd; /* HPCOMR - HP Command */
++ u32 ctl; /* HPCR - HP Control */
++ u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */
++ u32 secvio_ctl; /* HPSVCR - Security Violation Control */
++ u32 status; /* HPSR - HP Status */
++ u32 secvio_status; /* HPSVSR - Security Violation Status */
++ u32 ha_counteriv; /* High Assurance Counter IV */
++ u32 ha_counter; /* High Assurance Counter */
++ u32 rtc_msb; /* Real Time Clock/Counter MSB */
++ u32 rtc_lsb; /* Real Time Counter LSB */
++ u32 time_alarm_msb; /* Time Alarm MSB */
++ u32 time_alarm_lsb; /* Time Alarm LSB */
++};
++
++#define HP_LOCK_HAC_LCK 0x00040000
++#define HP_LOCK_HPSICR_LCK 0x00020000
++#define HP_LOCK_HPSVCR_LCK 0x00010000
++#define HP_LOCK_MKEYSEL_LCK 0x00000200
++#define HP_LOCK_TAMPCFG_LCK 0x00000100
++#define HP_LOCK_TAMPFLT_LCK 0x00000080
++#define HP_LOCK_SECVIO_LCK 0x00000040
++#define HP_LOCK_GENP_LCK 0x00000020
++#define HP_LOCK_MONOCTR_LCK 0x00000010
++#define HP_LOCK_CALIB_LCK 0x00000008
++#define HP_LOCK_SRTC_LCK 0x00000004
++#define HP_LOCK_ZMK_RD_LCK 0x00000002
++#define HP_LOCK_ZMK_WT_LCK 0x00000001
++
++#define HP_CMD_NONPRIV_AXS 0x80000000
++#define HP_CMD_HAC_STOP 0x00080000
++#define HP_CMD_HAC_CLEAR 0x00040000
++#define HP_CMD_HAC_LOAD 0x00020000
++#define HP_CMD_HAC_CFG_EN 0x00010000
++#define HP_CMD_SNVS_MSTR_KEY 0x00002000
++#define HP_CMD_PROG_ZMK 0x00001000
++#define HP_CMD_SW_LPSV 0x00000400
++#define HP_CMD_SW_FSV 0x00000200
++#define HP_CMD_SW_SV 0x00000100
++#define HP_CMD_LP_SWR_DIS 0x00000020
++#define HP_CMD_LP_SWR 0x00000010
++#define HP_CMD_SSM_SFNS_DIS 0x00000004
++#define HP_CMD_SSM_ST_DIS 0x00000002
++#define HP_CMD_SMM_ST 0x00000001
++
++#define HP_CTL_TIME_SYNC 0x00010000
++#define HP_CTL_CAL_VAL_SHIFT 10
++#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT)
++#define HP_CTL_CALIB_EN 0x00000100
++#define HP_CTL_PI_FREQ_SHIFT 4
++#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT)
++#define HP_CTL_PI_EN 0x00000008
++#define HP_CTL_TIMEALARM_EN 0x00000002
++#define HP_CTL_RTC_EN 0x00000001
++
++#define HP_SECVIO_INTEN_EN 0x10000000
++#define HP_SECVIO_INTEN_SRC5 0x00000020
++#define HP_SECVIO_INTEN_SRC4 0x00000010
++#define HP_SECVIO_INTEN_SRC3 0x00000008
++#define HP_SECVIO_INTEN_SRC2 0x00000004
++#define HP_SECVIO_INTEN_SRC1 0x00000002
++#define HP_SECVIO_INTEN_SRC0 0x00000001
++#define HP_SECVIO_INTEN_ALL 0x8000003f
++
++#define HP_SECVIO_ICTL_CFG_SHIFT 30
++#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT)
++#define HP_SECVIO_ICTL_CFG5_SHIFT 5
++#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT)
++#define HP_SECVIO_ICTL_CFG_DISABLE 0
++#define HP_SECVIO_ICTL_CFG_NONFATAL 1
++#define HP_SECVIO_ICTL_CFG_FATAL 2
++#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010
++#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008
++#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004
++#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002
++#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001
++
++#define HP_STATUS_ZMK_ZERO 0x80000000
++#define HP_STATUS_OTPMK_ZERO 0x08000000
++#define HP_STATUS_OTPMK_SYN_SHIFT 16
++#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT)
++#define HP_STATUS_SSM_ST_SHIFT 8
++#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT)
++#define HP_STATUS_SSM_ST_INIT 0
++#define HP_STATUS_SSM_ST_HARDFAIL 1
++#define HP_STATUS_SSM_ST_SOFTFAIL 3
++#define HP_STATUS_SSM_ST_INITINT 8
++#define HP_STATUS_SSM_ST_CHECK 9
++#define HP_STATUS_SSM_ST_NONSECURE 11
++#define HP_STATUS_SSM_ST_TRUSTED 13
++#define HP_STATUS_SSM_ST_SECURE 15
++
++#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */
++#define HP_SECVIOST_ZMK_SYN_SHIFT 16
++#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT)
++#define HP_SECVIOST_SECVIO5 0x00000020
++#define HP_SECVIOST_SECVIO4 0x00000010
++#define HP_SECVIOST_SECVIO3 0x00000008
++#define HP_SECVIOST_SECVIO2 0x00000004
++#define HP_SECVIOST_SECVIO1 0x00000002
++#define HP_SECVIOST_SECVIO0 0x00000001
++#define HP_SECVIOST_SECVIOMASK 0x0000003f
++
++/*
++ * SNVS Low Power Domain
++ * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK
++ */
++struct snvs_lp {
++ u32 lock;
++ u32 ctl;
++ u32 mstr_key_ctl; /* Master Key Control */
++ u32 secvio_ctl; /* Security Violation Control */
++ u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */
++ u32 tamper_det_cfg; /* Tamper Detectors Configuration */
++ u32 status;
++ u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */
++ u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */
++ u32 time_alarm; /* Time Alarm */
++ u32 smc_msb; /* Secure Monotonic Counter MSB */
++ u32 smc_lsb; /* Secure Monotonic Counter LSB */
++ u32 pwr_glitch_det; /* Power Glitch Detector */
++ u32 gen_purpose;
++ u32 zmk[8]; /* Zeroizable Master Key */
++};
++
++#define LP_LOCK_MKEYSEL_LCK 0x00000200
++#define LP_LOCK_TAMPDET_LCK 0x00000100
++#define LP_LOCK_TAMPFLT_LCK 0x00000080
++#define LP_LOCK_SECVIO_LCK 0x00000040
++#define LP_LOCK_GENP_LCK 0x00000020
++#define LP_LOCK_MONOCTR_LCK 0x00000010
++#define LP_LOCK_CALIB_LCK 0x00000008
++#define LP_LOCK_SRTC_LCK 0x00000004
++#define LP_LOCK_ZMK_RD_LCK 0x00000002
++#define LP_LOCK_ZMK_WT_LCK 0x00000001
++
++#define LP_CTL_CAL_VAL_SHIFT 10
++#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT)
++#define LP_CTL_CALIB_EN 0x00000100
++#define LP_CTL_SRTC_INVAL_EN 0x00000010
++#define LP_CTL_WAKE_INT_EN 0x00000008
++#define LP_CTL_MONOCTR_EN 0x00000004
++#define LP_CTL_TIMEALARM_EN 0x00000002
++#define LP_CTL_SRTC_EN 0x00000001
++
++#define LP_MKEYCTL_ZMKECC_SHIFT 8
++#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT)
++#define LP_MKEYCTL_ZMKECC_EN 0x00000010
++#define LP_MKEYCTL_ZMKECC_VAL 0x00000008
++#define LP_MKEYCTL_ZMKECC_PROG 0x00000004
++#define LP_MKEYCTL_MKSEL_SHIFT 0
++#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT)
++#define LP_MKEYCTL_MK_OTP 0
++#define LP_MKEYCTL_MK_ZMK 2
++#define LP_MKEYCTL_MK_COMB 3
++
++#define LP_SECVIO_CTL_SRC5 0x20
++#define LP_SECVIO_CTL_SRC4 0x10
++#define LP_SECVIO_CTL_SRC3 0x08
++#define LP_SECVIO_CTL_SRC2 0x04
++#define LP_SECVIO_CTL_SRC1 0x02
++#define LP_SECVIO_CTL_SRC0 0x01
++
++#define LP_TAMPFILT_EXT2_EN 0x80000000
++#define LP_TAMPFILT_EXT2_SHIFT 24
++#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT)
++#define LP_TAMPFILT_EXT1_EN 0x00800000
++#define LP_TAMPFILT_EXT1_SHIFT 16
++#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT)
++#define LP_TAMPFILT_WM_EN 0x00000080
++#define LP_TAMPFILT_WM_SHIFT 0
++#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT)
++
++#define LP_TAMPDET_OSC_BPS 0x10000000
++#define LP_TAMPDET_VRC_SHIFT 24
++#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT)
++#define LP_TAMPDET_HTDC_SHIFT 20
++#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT)
++#define LP_TAMPDET_LTDC_SHIFT 16
++#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT)
++#define LP_TAMPDET_POR_OBS 0x00008000
++#define LP_TAMPDET_PFD_OBS 0x00004000
++#define LP_TAMPDET_ET2_EN 0x00000400
++#define LP_TAMPDET_ET1_EN 0x00000200
++#define LP_TAMPDET_WMT2_EN 0x00000100
++#define LP_TAMPDET_WMT1_EN 0x00000080
++#define LP_TAMPDET_VT_EN 0x00000040
++#define LP_TAMPDET_TT_EN 0x00000020
++#define LP_TAMPDET_CT_EN 0x00000010
++#define LP_TAMPDET_MCR_EN 0x00000004
++#define LP_TAMPDET_SRTCR_EN 0x00000002
++
++#define LP_STATUS_SECURE
++#define LP_STATUS_NONSECURE
++#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */
++#define LP_STATUS_EXT_SECVIO 0x00010000
++#define LP_STATUS_ET2 0x00000400
++#define LP_STATUS_ET1 0x00000200
++#define LP_STATUS_WMT2 0x00000100
++#define LP_STATUS_WMT1 0x00000080
++#define LP_STATUS_VTD 0x00000040
++#define LP_STATUS_TTD 0x00000020
++#define LP_STATUS_CTD 0x00000010
++#define LP_STATUS_PGD 0x00000008
++#define LP_STATUS_MCR 0x00000004
++#define LP_STATUS_SRTCR 0x00000002
++#define LP_STATUS_LPTA 0x00000001
++
++/* Full SNVS register page, including version/options */
++struct snvs_full {
++ struct snvs_hp hp;
++ struct snvs_lp lp;
++ u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */
++
++ /* Version / Revision / Option ID space - end of register page */
++ u32 vid; /* 0xbf8 HP Version ID (VID 1) */
++ u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */
++};
++
++#endif /* SNVSREGS_H */
+diff -Nur linux-3.14.72.orig/drivers/dma/imx-sdma.c linux-3.14.72/drivers/dma/imx-sdma.c
+--- linux-3.14.72.orig/drivers/dma/imx-sdma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/dma/imx-sdma.c 2016-06-19 22:11:55.121152080 +0200
+@@ -7,7 +7,7 @@
+ *
+ * Based on code from Freescale:
+ *
+- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -25,10 +25,12 @@
+ #include <linux/interrupt.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
++#include <linux/regmap.h>
+ #include <linux/sched.h>
+ #include <linux/semaphore.h>
+ #include <linux/spinlock.h>
+ #include <linux/device.h>
++#include <linux/genalloc.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/firmware.h>
+ #include <linux/slab.h>
+@@ -39,6 +41,8 @@
+ #include <linux/of_dma.h>
+
+ #include <asm/irq.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+ #include <linux/platform_data/dma-imx-sdma.h>
+ #include <linux/platform_data/dma-imx.h>
+
+@@ -229,6 +233,7 @@
+ } __attribute__ ((packed));
+
+ #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
++#define SDMA_BD_MAX_CNT 0xfffc /* align with 4 bytes */
+
+ struct sdma_engine;
+
+@@ -244,6 +249,7 @@
+ * @word_size peripheral access size
+ * @buf_tail ID of the buffer that was processed
+ * @num_bd max NUM_BD. number of descriptors currently handling
++ * @bd_iram flag indicating the memory location of buffer descriptor
+ */
+ struct sdma_channel {
+ struct sdma_engine *sdma;
+@@ -255,11 +261,15 @@
+ enum dma_slave_buswidth word_size;
+ unsigned int buf_tail;
+ unsigned int num_bd;
++ unsigned int period_len;
+ struct sdma_buffer_descriptor *bd;
+ dma_addr_t bd_phys;
++ bool bd_iram;
+ unsigned int pc_from_device, pc_to_device;
++ unsigned int device_to_device;
++ unsigned int pc_to_pc;
+ unsigned long flags;
+- dma_addr_t per_address;
++ dma_addr_t per_address, per_address2;
+ unsigned long event_mask[2];
+ unsigned long watermark_level;
+ u32 shp_addr, per_addr;
+@@ -270,6 +280,7 @@
+ unsigned int chn_count;
+ unsigned int chn_real_count;
+ struct tasklet_struct tasklet;
++ struct imx_dma_data data;
+ };
+
+ #define IMX_DMA_SG_LOOP BIT(0)
+@@ -278,6 +289,14 @@
+ #define MXC_SDMA_DEFAULT_PRIORITY 1
+ #define MXC_SDMA_MIN_PRIORITY 1
+ #define MXC_SDMA_MAX_PRIORITY 7
++/*
++ * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are reserved and
++ * can't be accessed. Skip these register touch in suspend/resume. Also below
++ * two macros are only used on i.mx6sx.
++ */
++#define MXC_SDMA_RESERVED_REG (SDMA_CHNPRI_0 - SDMA_XTRIG_CONF2 - 4)
++#define MXC_SDMA_SAVED_REG_NUM (((SDMA_CHNENBL0_IMX35 + 4 * 48) - \
++ MXC_SDMA_RESERVED_REG) / 4)
+
+ #define SDMA_FIRMWARE_MAGIC 0x414d4453
+
+@@ -316,6 +335,8 @@
+ struct device_dma_parameters dma_parms;
+ struct sdma_channel channel[MAX_DMA_CHANNELS];
+ struct sdma_channel_control *channel_control;
++ u32 save_regs[MXC_SDMA_SAVED_REG_NUM];
++ const char *fw_name;
+ void __iomem *regs;
+ struct sdma_context_data *context;
+ dma_addr_t context_phys;
+@@ -326,6 +347,7 @@
+ u32 script_number;
+ struct sdma_script_start_addrs *script_addrs;
+ const struct sdma_driver_data *drvdata;
++ struct gen_pool *iram_pool;
+ };
+
+ static struct sdma_driver_data sdma_imx31 = {
+@@ -403,7 +425,6 @@
+ .ap_2_ap_addr = 642,
+ .uart_2_mcu_addr = 817,
+ .mcu_2_app_addr = 747,
+- .per_2_per_addr = 6331,
+ .uartsh_2_mcu_addr = 1032,
+ .mcu_2_shp_addr = 960,
+ .app_2_mcu_addr = 683,
+@@ -418,6 +439,24 @@
+ .script_addrs = &sdma_script_imx6q,
+ };
+
++static struct sdma_script_start_addrs sdma_script_imx6sx = {
++ .ap_2_ap_addr = 642,
++ .uart_2_mcu_addr = 817,
++ .mcu_2_app_addr = 747,
++ .uartsh_2_mcu_addr = 1032,
++ .mcu_2_shp_addr = 960,
++ .app_2_mcu_addr = 683,
++ .shp_2_mcu_addr = 891,
++ .spdif_2_mcu_addr = 1100,
++ .mcu_2_spdif_addr = 1134,
++};
++
++static struct sdma_driver_data sdma_imx6sx = {
++ .chnenbl0 = SDMA_CHNENBL0_IMX35,
++ .num_events = 48,
++ .script_addrs = &sdma_script_imx6sx,
++};
++
+ static struct platform_device_id sdma_devtypes[] = {
+ {
+ .name = "imx25-sdma",
+@@ -438,12 +477,16 @@
+ .name = "imx6q-sdma",
+ .driver_data = (unsigned long)&sdma_imx6q,
+ }, {
++ .name = "imx6sx-sdma",
++ .driver_data = (unsigned long)&sdma_imx6sx,
++ }, {
+ /* sentinel */
+ }
+ };
+ MODULE_DEVICE_TABLE(platform, sdma_devtypes);
+
+ static const struct of_device_id sdma_dt_ids[] = {
++ { .compatible = "fsl,imx6sx-sdma", .data = &sdma_imx6sx, },
+ { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
+ { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
+ { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
+@@ -540,12 +583,14 @@
+ dma_addr_t buf_phys;
+ int ret;
+ unsigned long flags;
++ bool use_iram = true;
+
+- buf_virt = dma_alloc_coherent(NULL,
+- size,
+- &buf_phys, GFP_KERNEL);
++ buf_virt = gen_pool_dma_alloc(sdma->iram_pool, size, &buf_phys);
+ if (!buf_virt) {
+- return -ENOMEM;
++ use_iram = false;
++ buf_virt = dma_alloc_coherent(NULL, size, &buf_phys, GFP_KERNEL);
++ if (!buf_virt)
++ return -ENOMEM;
+ }
+
+ spin_lock_irqsave(&sdma->channel_0_lock, flags);
+@@ -562,7 +607,10 @@
+
+ spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
+
+- dma_free_coherent(NULL, size, buf_virt, buf_phys);
++ if (use_iram)
++ gen_pool_free(sdma->iram_pool, (unsigned long)buf_virt, size);
++ else
++ dma_free_coherent(NULL, size, buf_virt, buf_phys);
+
+ return ret;
+ }
+@@ -593,6 +641,12 @@
+
+ static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
+ {
++ if (sdmac->desc.callback)
++ sdmac->desc.callback(sdmac->desc.callback_param);
++}
++
++static void sdma_update_channel_loop(struct sdma_channel *sdmac)
++{
+ struct sdma_buffer_descriptor *bd;
+
+ /*
+@@ -607,15 +661,15 @@
+
+ if (bd->mode.status & BD_RROR)
+ sdmac->status = DMA_ERROR;
+- else
+- sdmac->status = DMA_IN_PROGRESS;
+
+ bd->mode.status |= BD_DONE;
+ sdmac->buf_tail++;
+ sdmac->buf_tail %= sdmac->num_bd;
+-
+- if (sdmac->desc.callback)
+- sdmac->desc.callback(sdmac->desc.callback_param);
++ if (sdmac->peripheral_type == IMX_DMATYPE_UART) {
++ /* restore mode.count after counter readed */
++ sdmac->chn_real_count = bd->mode.count;
++ bd->mode.count = sdmac->chn_count;
++ }
+ }
+ }
+
+@@ -650,6 +704,14 @@
+ static void sdma_tasklet(unsigned long data)
+ {
+ struct sdma_channel *sdmac = (struct sdma_channel *) data;
++ unsigned long flags;
++
++ spin_lock_irqsave(&sdmac->lock, flags);
++ if (sdmac->status != DMA_IN_PROGRESS && !(sdmac->flags & IMX_DMA_SG_LOOP)) {
++ spin_unlock_irqrestore(&sdmac->lock, flags);
++ return;
++ }
++ spin_unlock_irqrestore(&sdmac->lock, flags);
+
+ if (sdmac->flags & IMX_DMA_SG_LOOP)
+ sdma_handle_channel_loop(sdmac);
+@@ -660,7 +722,7 @@
+ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
+ {
+ struct sdma_engine *sdma = dev_id;
+- unsigned long stat;
++ unsigned long stat, flags;
+
+ stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
+ /* not interested in channel 0 interrupts */
+@@ -671,7 +733,14 @@
+ int channel = fls(stat) - 1;
+ struct sdma_channel *sdmac = &sdma->channel[channel];
+
+- tasklet_schedule(&sdmac->tasklet);
++ if ((sdmac->flags & IMX_DMA_SG_LOOP) &&
++ (sdmac->peripheral_type != IMX_DMATYPE_HDMI))
++ sdma_update_channel_loop(sdmac);
++
++ spin_lock_irqsave(&sdmac->lock, flags);
++ if (sdmac->status == DMA_IN_PROGRESS || (sdmac->flags & IMX_DMA_SG_LOOP))
++ tasklet_schedule(&sdmac->tasklet);
++ spin_unlock_irqrestore(&sdmac->lock, flags);
+
+ __clear_bit(channel, &stat);
+ }
+@@ -695,6 +764,8 @@
+
+ sdmac->pc_from_device = 0;
+ sdmac->pc_to_device = 0;
++ sdmac->device_to_device = 0;
++ sdmac->pc_to_pc = 0;
+
+ switch (peripheral_type) {
+ case IMX_DMATYPE_MEMORY:
+@@ -721,8 +792,12 @@
+ emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
+ break;
+ case IMX_DMATYPE_CSPI:
++ per_2_emi = sdma->script_addrs->app_2_mcu_addr;
++ emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr;
++ break;
+ case IMX_DMATYPE_EXT:
+ case IMX_DMATYPE_SSI:
++ case IMX_DMATYPE_SAI:
+ per_2_emi = sdma->script_addrs->app_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_app_addr;
+ break;
+@@ -744,6 +819,11 @@
+ emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
+ per_2_per = sdma->script_addrs->per_2_per_addr;
+ break;
++ case IMX_DMATYPE_ASRC_SP:
++ per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
++ emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
++ per_2_per = sdma->script_addrs->per_2_per_addr;
++ break;
+ case IMX_DMATYPE_MSHC:
+ per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
+@@ -758,12 +838,17 @@
+ case IMX_DMATYPE_IPU_MEMORY:
+ emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
+ break;
++ case IMX_DMATYPE_HDMI:
++ emi_2_per = sdma->script_addrs->hdmi_dma_addr;
++ break;
+ default:
+ break;
+ }
+
+ sdmac->pc_from_device = per_2_emi;
+ sdmac->pc_to_device = emi_2_per;
++ sdmac->device_to_device = per_2_per;
++ sdmac->pc_to_pc = emi_2_emi;
+ }
+
+ static int sdma_load_context(struct sdma_channel *sdmac)
+@@ -776,11 +861,14 @@
+ int ret;
+ unsigned long flags;
+
+- if (sdmac->direction == DMA_DEV_TO_MEM) {
++ if (sdmac->direction == DMA_DEV_TO_MEM)
+ load_address = sdmac->pc_from_device;
+- } else {
++ else if (sdmac->direction == DMA_DEV_TO_DEV)
++ load_address = sdmac->device_to_device;
++ else if (sdmac->direction == DMA_MEM_TO_MEM)
++ load_address = sdmac->pc_to_pc;
++ else
+ load_address = sdmac->pc_to_device;
+- }
+
+ if (load_address < 0)
+ return load_address;
+@@ -800,11 +888,16 @@
+ /* Send by context the event mask,base address for peripheral
+ * and watermark level
+ */
+- context->gReg[0] = sdmac->event_mask[1];
+- context->gReg[1] = sdmac->event_mask[0];
+- context->gReg[2] = sdmac->per_addr;
+- context->gReg[6] = sdmac->shp_addr;
+- context->gReg[7] = sdmac->watermark_level;
++ if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
++ context->gReg[4] = sdmac->per_addr;
++ context->gReg[6] = sdmac->shp_addr;
++ } else {
++ context->gReg[0] = sdmac->event_mask[1];
++ context->gReg[1] = sdmac->event_mask[0];
++ context->gReg[2] = sdmac->per_addr;
++ context->gReg[6] = sdmac->shp_addr;
++ context->gReg[7] = sdmac->watermark_level;
++ }
+
+ bd0->mode.command = C0_SETDM;
+ bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
+@@ -822,9 +915,75 @@
+ {
+ struct sdma_engine *sdma = sdmac->sdma;
+ int channel = sdmac->channel;
++ unsigned long flags;
+
+- writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
++ spin_lock_irqsave(&sdmac->lock, flags);
+ sdmac->status = DMA_ERROR;
++ spin_unlock_irqrestore(&sdmac->lock, flags);
++
++ writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
++}
++
++static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
++{
++ int lwml = sdmac->watermark_level & 0xff;
++ int hwml = (sdmac->watermark_level >> 16) & 0xff;
++
++ if (sdmac->event_id0 > 31) {
++ sdmac->event_mask[0] |= 0;
++ __set_bit(28, &sdmac->watermark_level);
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id0 % 32);
++ } else {
++ sdmac->event_mask[0] |= 0;
++ sdmac->event_mask[1] |=
++ BIT(sdmac->event_id0 % 32);
++ }
++ if (sdmac->event_id1 > 31) {
++ sdmac->event_mask[1] |= 0;
++ __set_bit(29, &sdmac->watermark_level);
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id1 % 32);
++ } else {
++ sdmac->event_mask[1] |= 0;
++ sdmac->event_mask[0] |=
++ BIT(sdmac->event_id1 % 32);
++ }
++
++ /*
++ * If LWML(src_maxburst) > HWML(dst_maxburst), we need
++ * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
++ * r0(event_mask[1]) and r1(event_mask[0]).
++ */
++ if (lwml > hwml) {
++ sdmac->watermark_level &= ~0xff00ff;
++ sdmac->watermark_level |= hwml;
++ sdmac->watermark_level |= lwml << 16;
++ swap(sdmac->event_mask[0], sdmac->event_mask[1]);
++ }
++ /* BIT 11:
++ * 1 : Source on SPBA
++ * 0 : Source on AIPS
++ */
++ __set_bit(11, &sdmac->watermark_level);
++ /* BIT 12:
++ * 1 : Destination on SPBA
++ * 0 : Destination on AIPS
++ */
++ __set_bit(12, &sdmac->watermark_level);
++ __set_bit(31, &sdmac->watermark_level);
++ /* BIT 31:
++ * 1 : Amount of samples to be transferred is
++ * unknown and script will keep on transferring
++ * samples as long as both events are detected
++ * and script must be manually stopped by the
++ * application.
++ * 0 : The amount of samples to be is equal to
++ * the count field of mode word
++ *
++ */
++ __set_bit(25, &sdmac->watermark_level);
++ __clear_bit(24, &sdmac->watermark_level);
+ }
+
+ static int sdma_config_channel(struct sdma_channel *sdmac)
+@@ -844,6 +1003,12 @@
+ sdma_event_enable(sdmac, sdmac->event_id0);
+ }
+
++ if (sdmac->event_id1) {
++ if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
++ return -EINVAL;
++ sdma_event_enable(sdmac, sdmac->event_id1);
++ }
++
+ switch (sdmac->peripheral_type) {
+ case IMX_DMATYPE_DSP:
+ sdma_config_ownership(sdmac, false, true, true);
+@@ -862,19 +1027,22 @@
+ (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
+ /* Handle multiple event channels differently */
+ if (sdmac->event_id1) {
+- sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32);
+- if (sdmac->event_id1 > 31)
+- __set_bit(31, &sdmac->watermark_level);
+- sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32);
+- if (sdmac->event_id0 > 31)
+- __set_bit(30, &sdmac->watermark_level);
+- } else {
++ if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
++ sdmac->peripheral_type == IMX_DMATYPE_ASRC)
++ sdma_set_watermarklevel_for_p2p(sdmac);
++ } else
+ __set_bit(sdmac->event_id0, sdmac->event_mask);
+- }
++
+ /* Watermark Level */
+ sdmac->watermark_level |= sdmac->watermark_level;
+ /* Address */
+- sdmac->shp_addr = sdmac->per_address;
++ if (sdmac->direction == DMA_DEV_TO_DEV ||
++ (sdmac->peripheral_type == IMX_DMATYPE_HDMI)) {
++ sdmac->shp_addr = sdmac->per_address2;
++ sdmac->per_addr = sdmac->per_address;
++ } else {
++ sdmac->shp_addr = sdmac->per_address;
++ }
+ } else {
+ sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
+ }
+@@ -906,10 +1074,15 @@
+ int channel = sdmac->channel;
+ int ret = -EBUSY;
+
+- sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
++ sdmac->bd_iram = true;
++ sdmac->bd = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, &sdmac->bd_phys);
+ if (!sdmac->bd) {
+- ret = -ENOMEM;
+- goto out;
++ sdmac->bd_iram = false;
++ sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL);
++ if (!sdmac->bd) {
++ ret = -ENOMEM;
++ goto out;
++ }
+ }
+
+ memset(sdmac->bd, 0, PAGE_SIZE);
+@@ -968,6 +1141,7 @@
+
+ sdmac->peripheral_type = data->peripheral_type;
+ sdmac->event_id0 = data->dma_request;
++ sdmac->event_id1 = data->dma_request2;
+
+ clk_enable(sdmac->sdma->clk_ipg);
+ clk_enable(sdmac->sdma->clk_ahb);
+@@ -1005,58 +1179,177 @@
+
+ sdma_set_channel_priority(sdmac, 0);
+
+- dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
++ if (sdmac->bd_iram)
++ gen_pool_free(sdma->iram_pool, (unsigned long)sdmac->bd, PAGE_SIZE);
++ else
++ dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
+
+ clk_disable(sdma->clk_ipg);
+ clk_disable(sdma->clk_ahb);
+ }
+
+-static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
+- struct dma_chan *chan, struct scatterlist *sgl,
+- unsigned int sg_len, enum dma_transfer_direction direction,
+- unsigned long flags, void *context)
++static int sdma_transfer_init(struct sdma_channel *sdmac,
++ enum dma_transfer_direction direction)
++{
++ int ret = 0;
++
++ sdmac->status = DMA_IN_PROGRESS;
++ sdmac->buf_tail = 0;
++ sdmac->flags = 0;
++ sdmac->direction = direction;
++
++ ret = sdma_load_context(sdmac);
++ if (ret)
++ return ret;
++
++ sdmac->chn_count = 0;
++
++ return ret;
++}
++
++static int check_bd_buswidth(struct sdma_buffer_descriptor *bd,
++ struct sdma_channel *sdmac, int count,
++ dma_addr_t dma_dst, dma_addr_t dma_src)
++{
++ int ret = 0;
++
++ switch (sdmac->word_size) {
++ case DMA_SLAVE_BUSWIDTH_4_BYTES:
++ bd->mode.command = 0;
++ if ((count | dma_dst | dma_src) & 3)
++ ret = -EINVAL;
++ break;
++ case DMA_SLAVE_BUSWIDTH_2_BYTES:
++ bd->mode.command = 2;
++ if ((count | dma_dst | dma_src) & 1)
++ ret = -EINVAL;
++ break;
++ case DMA_SLAVE_BUSWIDTH_1_BYTE:
++ bd->mode.command = 1;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return ret;
++}
++
++static struct dma_async_tx_descriptor *sdma_prep_memcpy(
++ struct dma_chan *chan, dma_addr_t dma_dst,
++ dma_addr_t dma_src, size_t len, unsigned long flags)
+ {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct sdma_engine *sdma = sdmac->sdma;
+- int ret, i, count;
+ int channel = sdmac->channel;
+- struct scatterlist *sg;
++ size_t count;
++ int i = 0, param;
++ struct sdma_buffer_descriptor *bd;
+
+- if (sdmac->status == DMA_IN_PROGRESS)
++ if (!chan || !len || sdmac->status == DMA_IN_PROGRESS)
+ return NULL;
+- sdmac->status = DMA_IN_PROGRESS;
+
+- sdmac->flags = 0;
+-
+- sdmac->buf_tail = 0;
++ if (len >= NUM_BD * SDMA_BD_MAX_CNT) {
++ dev_err(sdma->dev, "channel%d: maximum bytes exceeded:%zu > %d\n",
++ channel, len, NUM_BD * SDMA_BD_MAX_CNT);
++ goto err_out;
++ }
+
+- dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
+- sg_len, channel);
++ dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
++ &dma_src, &dma_dst, len, channel);
+
+- sdmac->direction = direction;
+- ret = sdma_load_context(sdmac);
+- if (ret)
++ if (sdma_transfer_init(sdmac, DMA_MEM_TO_MEM))
+ goto err_out;
+
+- if (sg_len > NUM_BD) {
++ do {
++ count = min_t(size_t, len, SDMA_BD_MAX_CNT);
++ bd = &sdmac->bd[i];
++ bd->buffer_addr = dma_src;
++ bd->ext_buffer_addr = dma_dst;
++ bd->mode.count = count;
++
++ if (check_bd_buswidth(bd, sdmac, count, dma_dst, dma_src))
++ goto err_out;
++
++ dma_src += count;
++ dma_dst += count;
++ len -= count;
++ i++;
++
++ param = BD_DONE | BD_EXTD | BD_CONT;
++ /* last bd */
++ if (!len) {
++ param |= BD_INTR;
++ param |= BD_LAST;
++ param &= ~BD_CONT;
++ }
++
++ dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%u %s%s\n",
++ i, count, bd->buffer_addr,
++ param & BD_WRAP ? "wrap" : "",
++ param & BD_INTR ? " intr" : "");
++
++ bd->mode.status = param;
++ sdmac->chn_count += count;
++ } while (len);
++
++ sdmac->num_bd = i;
++ sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
++
++ return &sdmac->desc;
++err_out:
++ sdmac->status = DMA_ERROR;
++ return NULL;
++}
++
++/*
++ * Please ensure dst_nents no smaller than src_nents , also every sg_len of
++ * dst_sg node no smaller than src_sg. To simply things, please use the same
++ * size of dst_sg as src_sg.
++ */
++static struct dma_async_tx_descriptor *sdma_prep_sg(
++ struct dma_chan *chan,
++ struct scatterlist *dst_sg, unsigned int dst_nents,
++ struct scatterlist *src_sg, unsigned int src_nents,
++ enum dma_transfer_direction direction)
++{
++ struct sdma_channel *sdmac = to_sdma_chan(chan);
++ struct sdma_engine *sdma = sdmac->sdma;
++ int ret, i, count;
++ int channel = sdmac->channel;
++ struct scatterlist *sg_src = src_sg, *sg_dst = dst_sg;
++
++ if (sdmac->status == DMA_IN_PROGRESS)
++ return NULL;
++
++ dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
++ src_nents, channel);
++
++ if (src_nents > NUM_BD) {
+ dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+- channel, sg_len, NUM_BD);
++ channel, src_nents, NUM_BD);
+ ret = -EINVAL;
+ goto err_out;
+ }
+
+- sdmac->chn_count = 0;
+- for_each_sg(sgl, sg, sg_len, i) {
++ if (sdma_transfer_init(sdmac, direction))
++ goto err_out;
++
++ for_each_sg(src_sg, sg_src, src_nents, i) {
+ struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
+ int param;
+
+- bd->buffer_addr = sg->dma_address;
++ bd->buffer_addr = sg_src->dma_address;
++
++ if (direction == DMA_MEM_TO_MEM) {
++ BUG_ON(!sg_dst);
++ bd->ext_buffer_addr = sg_dst->dma_address;
++ }
+
+- count = sg_dma_len(sg);
++ count = sg_dma_len(sg_src);
+
+- if (count > 0xffff) {
++ if (count > SDMA_BD_MAX_CNT) {
+ dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
+- channel, count, 0xffff);
++ channel, count, SDMA_BD_MAX_CNT);
+ ret = -EINVAL;
+ goto err_out;
+ }
+@@ -1064,46 +1357,35 @@
+ bd->mode.count = count;
+ sdmac->chn_count += count;
+
+- if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
+- ret = -EINVAL;
++ if (direction == DMA_MEM_TO_MEM)
++ ret = check_bd_buswidth(bd, sdmac, count,
++ sg_dst->dma_address,
++ sg_src->dma_address);
++ else
++ ret = check_bd_buswidth(bd, sdmac, count, 0,
++ sg_src->dma_address);
++ if (ret)
+ goto err_out;
+- }
+-
+- switch (sdmac->word_size) {
+- case DMA_SLAVE_BUSWIDTH_4_BYTES:
+- bd->mode.command = 0;
+- if (count & 3 || sg->dma_address & 3)
+- return NULL;
+- break;
+- case DMA_SLAVE_BUSWIDTH_2_BYTES:
+- bd->mode.command = 2;
+- if (count & 1 || sg->dma_address & 1)
+- return NULL;
+- break;
+- case DMA_SLAVE_BUSWIDTH_1_BYTE:
+- bd->mode.command = 1;
+- break;
+- default:
+- return NULL;
+- }
+
+ param = BD_DONE | BD_EXTD | BD_CONT;
+
+- if (i + 1 == sg_len) {
++ if (i + 1 == src_nents) {
+ param |= BD_INTR;
+ param |= BD_LAST;
+ param &= ~BD_CONT;
+ }
+
+- dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
+- i, count, (u64)sg->dma_address,
++ dev_dbg(sdma->dev, "entry %d: count: %d dma: 0x%pad %s%s\n",
++ i, count, &sg_src->dma_address,
+ param & BD_WRAP ? "wrap" : "",
+ param & BD_INTR ? " intr" : "");
+
+ bd->mode.status = param;
++ if (direction == DMA_MEM_TO_MEM)
++ sg_dst = sg_next(sg_dst);
+ }
+
+- sdmac->num_bd = sg_len;
++ sdmac->num_bd = src_nents;
+ sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
+
+ return &sdmac->desc;
+@@ -1112,6 +1394,24 @@
+ return NULL;
+ }
+
++static struct dma_async_tx_descriptor *sdma_prep_memcpy_sg(
++ struct dma_chan *chan,
++ struct scatterlist *dst_sg, unsigned int dst_nents,
++ struct scatterlist *src_sg, unsigned int src_nents,
++ unsigned long flags)
++{
++ return sdma_prep_sg(chan, dst_sg, dst_nents, src_sg, src_nents,
++ DMA_MEM_TO_MEM);
++}
++
++static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
++ struct dma_chan *chan, struct scatterlist *sgl,
++ unsigned int sg_len, enum dma_transfer_direction direction,
++ unsigned long flags, void *context)
++{
++ return sdma_prep_sg(chan, NULL, 0, sgl, sg_len, direction);
++}
++
+ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
+ struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+@@ -1119,9 +1419,9 @@
+ {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct sdma_engine *sdma = sdmac->sdma;
+- int num_periods = buf_len / period_len;
+ int channel = sdmac->channel;
+ int ret, i = 0, buf = 0;
++ int num_periods;
+
+ dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
+
+@@ -1131,6 +1431,7 @@
+ sdmac->status = DMA_IN_PROGRESS;
+
+ sdmac->buf_tail = 0;
++ sdmac->period_len = period_len;
+
+ sdmac->flags |= IMX_DMA_SG_LOOP;
+ sdmac->direction = direction;
+@@ -1138,18 +1439,26 @@
+ if (ret)
+ goto err_out;
+
++ if (sdmac->peripheral_type == IMX_DMATYPE_HDMI)
++ return &sdmac->desc;
++ else
++ num_periods = buf_len / period_len;
++
+ if (num_periods > NUM_BD) {
+ dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
+ channel, num_periods, NUM_BD);
+ goto err_out;
+ }
+
+- if (period_len > 0xffff) {
+- dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
+- channel, period_len, 0xffff);
++ if (period_len > SDMA_BD_MAX_CNT) {
++ dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
++ channel, period_len, SDMA_BD_MAX_CNT);
+ goto err_out;
+ }
+
++ if (sdmac->peripheral_type == IMX_DMATYPE_UART)
++ sdmac->chn_count = period_len;
++
+ while (buf < buf_len) {
+ struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
+ int param;
+@@ -1169,8 +1478,8 @@
+ if (i + 1 == num_periods)
+ param |= BD_WRAP;
+
+- dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
+- i, period_len, (u64)dma_addr,
++ dev_dbg(sdma->dev, "entry %d: count: %d dma: %pad %s%s\n",
++ i, period_len, &dma_addr,
+ param & BD_WRAP ? "wrap" : "",
+ param & BD_INTR ? " intr" : "");
+
+@@ -1207,12 +1516,27 @@
+ sdmac->watermark_level = dmaengine_cfg->src_maxburst *
+ dmaengine_cfg->src_addr_width;
+ sdmac->word_size = dmaengine_cfg->src_addr_width;
+- } else {
++ } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
++ sdmac->per_address = dmaengine_cfg->src_addr;
++ sdmac->per_address2 = dmaengine_cfg->dst_addr;
++ sdmac->watermark_level =
++ dmaengine_cfg->src_maxburst & 0xff;
++ sdmac->watermark_level |=
++ (dmaengine_cfg->dst_maxburst & 0xff) << 16;
++ sdmac->word_size = dmaengine_cfg->dst_addr_width;
++ } else if (dmaengine_cfg->direction == DMA_MEM_TO_DEV) {
+ sdmac->per_address = dmaengine_cfg->dst_addr;
+ sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
+ dmaengine_cfg->dst_addr_width;
+ sdmac->word_size = dmaengine_cfg->dst_addr_width;
++ } else if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) {
++ sdmac->per_address = dmaengine_cfg->src_addr;
++ sdmac->per_address2 = dmaengine_cfg->dst_addr;
++ sdmac->watermark_level = 0;
++ } else if (dmaengine_cfg->direction == DMA_MEM_TO_MEM) {
++ sdmac->word_size = dmaengine_cfg->dst_addr_width;
+ }
++
+ sdmac->direction = dmaengine_cfg->direction;
+ return sdma_config_channel(sdmac);
+ default:
+@@ -1227,9 +1551,20 @@
+ struct dma_tx_state *txstate)
+ {
+ struct sdma_channel *sdmac = to_sdma_chan(chan);
++ u32 residue;
++
++ /*
++ * For uart rx data may not receive fully, use old chn_real_count to
++ * know the real rx count.
++ */
++ if ((sdmac->flags & IMX_DMA_SG_LOOP) &&
++ (sdmac->peripheral_type != IMX_DMATYPE_UART))
++ residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
++ else
++ residue = sdmac->chn_count - sdmac->chn_real_count;
+
+ dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
+- sdmac->chn_count - sdmac->chn_real_count);
++ residue);
+
+ return sdmac->status;
+ }
+@@ -1245,6 +1580,7 @@
+
+ #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
+ #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
++#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
+
+ static void sdma_add_scripts(struct sdma_engine *sdma,
+ const struct sdma_script_start_addrs *addr)
+@@ -1290,6 +1626,9 @@
+ case 2:
+ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
+ break;
++ case 3:
++ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
++ break;
+ default:
+ dev_err(sdma->dev, "unknown firmware version\n");
+ goto err_firmware;
+@@ -1317,7 +1656,73 @@
+ release_firmware(fw);
+ }
+
+-static int __init sdma_get_firmware(struct sdma_engine *sdma,
++#define EVENT_REMAP_CELLS 3
++
++static int __init sdma_event_remap(struct sdma_engine *sdma)
++{
++ struct device_node *np = sdma->dev->of_node;
++ struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
++ struct property *event_remap;
++ struct regmap *gpr;
++ char propname[] = "fsl,sdma-event-remap";
++ u32 reg, val, shift, num_map, i;
++ int ret = 0;
++
++ if (IS_ERR(np) || IS_ERR(gpr_np))
++ goto out;
++
++ event_remap = of_find_property(np, propname, NULL);
++ num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
++ if (!num_map) {
++ dev_warn(sdma->dev, "no event needs to be remapped\n");
++ goto out;
++ } else if (num_map % EVENT_REMAP_CELLS) {
++ dev_err(sdma->dev, "the property %s must modulo %d\n",
++ propname, EVENT_REMAP_CELLS);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ gpr = syscon_node_to_regmap(gpr_np);
++ if (IS_ERR(gpr)) {
++ dev_err(sdma->dev, "failed to get gpr regmap\n");
++ ret = PTR_ERR(gpr);
++ goto out;
++ }
++
++ for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
++ ret = of_property_read_u32_index(np, propname, i, &reg);
++ if (ret) {
++ dev_err(sdma->dev, "failed to read property %s index %d\n",
++ propname, i);
++ goto out;
++ }
++
++ ret = of_property_read_u32_index(np, propname, i + 1, &shift);
++ if (ret) {
++ dev_err(sdma->dev, "failed to read property %s index %d\n",
++ propname, i + 1);
++ goto out;
++ }
++
++ ret = of_property_read_u32_index(np, propname, i + 2, &val);
++ if (ret) {
++ dev_err(sdma->dev, "failed to read property %s index %d\n",
++ propname, i + 2);
++ goto out;
++ }
++
++ regmap_update_bits(gpr, reg, BIT(shift), val << shift);
++ }
++
++out:
++ if (!IS_ERR(gpr_np))
++ of_node_put(gpr_np);
++
++ return ret;
++}
++
++static int sdma_get_firmware(struct sdma_engine *sdma,
+ const char *fw_name)
+ {
+ int ret;
+@@ -1331,7 +1736,7 @@
+
+ static int __init sdma_init(struct sdma_engine *sdma)
+ {
+- int i, ret;
++ int i, ret, ccbsize;
+ dma_addr_t ccb_phys;
+
+ clk_enable(sdma->clk_ipg);
+@@ -1340,14 +1745,17 @@
+ /* Be sure SDMA has not started yet */
+ writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
+
+- sdma->channel_control = dma_alloc_coherent(NULL,
+- MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
+- sizeof(struct sdma_context_data),
+- &ccb_phys, GFP_KERNEL);
++ ccbsize = MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control)
++ + sizeof(struct sdma_context_data);
+
++ sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, ccbsize, &ccb_phys);
+ if (!sdma->channel_control) {
+- ret = -ENOMEM;
+- goto err_dma_alloc;
++ sdma->channel_control = dma_alloc_coherent(NULL, ccbsize,
++ &ccb_phys, GFP_KERNEL);
++ if (!sdma->channel_control) {
++ ret = -ENOMEM;
++ goto err_dma_alloc;
++ }
+ }
+
+ sdma->context = (void *)sdma->channel_control +
+@@ -1402,12 +1810,14 @@
+
+ static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
+ {
++ struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct imx_dma_data *data = fn_param;
+
+ if (!imx_dma_is_general_purpose(chan))
+ return false;
+
+- chan->private = data;
++ sdmac->data = *data;
++ chan->private = &sdmac->data;
+
+ return true;
+ }
+@@ -1426,6 +1836,15 @@
+ data.peripheral_type = dma_spec->args[1];
+ data.priority = dma_spec->args[2];
+
++ /*
++ * init dma_request2 to zero, which is not used by the dts.
++ * For P2P, dma_request2 is init from dma_request_channel(),
++ * chan->private will point to the imx_dma_data, and in
++ * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
++ * be set to sdmac->event_id1.
++ */
++ data.dma_request2 = 0;
++
+ return dma_request_channel(mask, sdma_filter_fn, &data);
+ }
+
+@@ -1517,6 +1936,7 @@
+
+ dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
+ dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
++ dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
+
+ INIT_LIST_HEAD(&sdma->dma_device.channels);
+ /* Initialize channel parameters */
+@@ -1542,10 +1962,19 @@
+ &sdma->dma_device.channels);
+ }
+
++ if (np)
++ sdma->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!sdma->iram_pool)
++ dev_warn(&pdev->dev, "no iram assigned, using external mem\n");
++
+ ret = sdma_init(sdma);
+ if (ret)
+ goto err_init;
+
++ ret = sdma_event_remap(sdma);
++ if (ret)
++ goto err_init;
++
+ if (sdma->drvdata->script_addrs)
+ sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
+ if (pdata && pdata->script_addrs)
+@@ -1571,6 +2000,7 @@
+ dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
+ }
+ }
++ sdma->fw_name = fw_name;
+
+ sdma->dma_device.dev = &pdev->dev;
+
+@@ -1579,6 +2009,8 @@
+ sdma->dma_device.device_tx_status = sdma_tx_status;
+ sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
+ sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
++ sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
++ sdma->dma_device.device_prep_dma_sg = sdma_prep_memcpy_sg;
+ sdma->dma_device.device_control = sdma_control;
+ sdma->dma_device.device_issue_pending = sdma_issue_pending;
+ sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
+@@ -1598,6 +2030,7 @@
+ }
+ }
+
++ platform_set_drvdata(pdev, sdma);
+ dev_info(sdma->dev, "initialized\n");
+
+ return 0;
+@@ -1624,10 +2057,94 @@
+ return -EBUSY;
+ }
+
++#ifdef CONFIG_PM_SLEEP
++static int sdma_suspend(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct sdma_engine *sdma = platform_get_drvdata(pdev);
++ int i;
++
++ /* Do nothing if not i.MX6SX */
++ if (sdma->drvdata != &sdma_imx6sx)
++ return 0;
++
++ clk_enable(sdma->clk_ipg);
++ clk_enable(sdma->clk_ahb);
++ /* save regs */
++ for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) {
++ /*
++ * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are
++ * reserved and can't be touched. Skip these regs.
++ */
++ if (i > SDMA_XTRIG_CONF2 / 4)
++ sdma->save_regs[i] = readl_relaxed(sdma->regs +
++ MXC_SDMA_RESERVED_REG
++ + 4 * i);
++ else
++ sdma->save_regs[i] = readl_relaxed(sdma->regs + 4 * i);
++ }
++
++ clk_disable(sdma->clk_ipg);
++ clk_disable(sdma->clk_ahb);
++
++ return 0;
++}
++
++static int sdma_resume(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct sdma_engine *sdma = platform_get_drvdata(pdev);
++ int i, ret;
++
++ /* Do nothing if not i.MX6SX */
++ if (sdma->drvdata != &sdma_imx6sx)
++ return 0;
++
++ clk_enable(sdma->clk_ipg);
++ clk_enable(sdma->clk_ahb);
++ /* Do nothing if mega/fast mix not turned off */
++ if (readl_relaxed(sdma->regs + SDMA_H_C0PTR)) {
++ clk_disable(sdma->clk_ipg);
++ clk_disable(sdma->clk_ahb);
++ return 0;
++ }
++ /* restore regs and load firmware */
++ for (i = 0; i < MXC_SDMA_SAVED_REG_NUM; i++) {
++ /*
++ * 0x78(SDMA_XTRIG_CONF2+4)~0x100(SDMA_CHNPRI_O) registers are
++ * reserved and can't be touched. Skip these regs.
++ */
++ if (i > SDMA_XTRIG_CONF2 / 4)
++ writel_relaxed(sdma->save_regs[i], sdma->regs +
++ MXC_SDMA_RESERVED_REG + 4 * i);
++ else
++ writel_relaxed(sdma->save_regs[i] , sdma->regs + 4 * i);
++ }
++
++ /* prepare priority for channel0 to start */
++ sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
++ clk_disable(sdma->clk_ipg);
++ clk_disable(sdma->clk_ahb);
++
++ ret = sdma_get_firmware(sdma, sdma->fw_name);
++ if (ret) {
++ dev_warn(&pdev->dev, "failed to get firware\n");
++ return ret;
++ }
++
++ return 0;
++}
++#endif
++
++static const struct dev_pm_ops sdma_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(sdma_suspend, sdma_resume)
++};
++
+ static struct platform_driver sdma_driver = {
+ .driver = {
+ .name = "imx-sdma",
+ .of_match_table = sdma_dt_ids,
++ .pm = &sdma_pm_ops,
+ },
+ .id_table = sdma_devtypes,
+ .remove = sdma_remove,
+diff -Nur linux-3.14.72.orig/drivers/dma/Kconfig linux-3.14.72/drivers/dma/Kconfig
+--- linux-3.14.72.orig/drivers/dma/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/dma/Kconfig 2016-06-19 22:11:55.121152080 +0200
+@@ -137,6 +137,19 @@
+ To avoid bloating the irq_desc[] array we allocate a sufficient
+ number of IRQ slots and map them dynamically to specific sources.
+
++config MXC_PXP_V2
++ bool "MXC PxP V2 support"
++ depends on ARM
++ select DMA_ENGINE
++ help
++ Support the PxP (Pixel Pipeline) on i.MX6 DualLite and i.MX6 SoloLite.
++ If unsure, select N.
++
++config MXC_PXP_CLIENT_DEVICE
++ bool "MXC PxP Client Device"
++ default y
++ depends on MXC_PXP_V2
++
+ config TXX9_DMAC
+ tristate "Toshiba TXx9 SoC DMA support"
+ depends on MACH_TX49XX || MACH_TX39XX
+diff -Nur linux-3.14.72.orig/drivers/dma/Makefile linux-3.14.72/drivers/dma/Makefile
+--- linux-3.14.72.orig/drivers/dma/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/dma/Makefile 2016-06-19 22:11:55.121152080 +0200
+@@ -18,6 +18,7 @@
+ obj-$(CONFIG_DW_DMAC_CORE) += dw/
+ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
+ obj-$(CONFIG_MX3_IPU) += ipu/
++obj-$(CONFIG_MXC_PXP_V2) += pxp/
+ obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
+ obj-$(CONFIG_SH_DMAE_BASE) += sh/
+ obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
+diff -Nur linux-3.14.72.orig/drivers/dma/mxs-dma.c linux-3.14.72/drivers/dma/mxs-dma.c
+--- linux-3.14.72.orig/drivers/dma/mxs-dma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/dma/mxs-dma.c 2016-06-19 22:11:55.121152080 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Refer to drivers/dma/imx-sdma.c
+ *
+@@ -28,7 +28,7 @@
+ #include <linux/of_device.h>
+ #include <linux/of_dma.h>
+ #include <linux/list.h>
+-
++#include <linux/pm_runtime.h>
+ #include <asm/irq.h>
+
+ #include "dmaengine.h"
+@@ -710,7 +710,7 @@
+ mxs_dma_enable_chan(mxs_chan);
+ }
+
+-static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
++static int mxs_dma_init(struct mxs_dma_engine *mxs_dma)
+ {
+ int ret;
+
+@@ -852,6 +852,7 @@
+
+ mxs_dma->pdev = pdev;
+ mxs_dma->dma_device.dev = &pdev->dev;
++ dev_set_drvdata(&pdev->dev, mxs_dma);
+
+ /* mxs_dma gets 65535 bytes maximum sg size */
+ mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
+@@ -883,9 +884,56 @@
+ return 0;
+ }
+
++static int mxs_dma_runtime_suspend(struct device *dev)
++{
++ struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev);
++
++ clk_disable(mxs_dma->clk);
++ return 0;
++}
++
++static int mxs_dma_runtime_resume(struct device *dev)
++{
++ struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev);
++ int ret;
++
++ ret = clk_enable(mxs_dma->clk);
++ if (ret < 0) {
++ dev_err(dev, "clk_enable failed: %d\n", ret);
++ return ret;
++ }
++ return 0;
++}
++
++static int mxs_dma_pm_suspend(struct device *dev)
++{
++ /*
++ * We do not save any registers here, since the gpmi will release its
++ * DMA channel.
++ */
++ return 0;
++}
++
++static int mxs_dma_pm_resume(struct device *dev)
++{
++ struct mxs_dma_engine *mxs_dma = dev_get_drvdata(dev);
++ int ret;
++
++ ret = mxs_dma_init(mxs_dma);
++ if (ret)
++ return ret;
++ return 0;
++}
++
++static const struct dev_pm_ops mxs_dma_pm_ops = {
++ SET_RUNTIME_PM_OPS(mxs_dma_runtime_suspend, mxs_dma_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(mxs_dma_pm_suspend, mxs_dma_pm_resume)
++};
++
+ static struct platform_driver mxs_dma_driver = {
+ .driver = {
+ .name = "mxs-dma",
++ .pm = &mxs_dma_pm_ops,
+ .of_match_table = mxs_dma_dt_ids,
+ },
+ .id_table = mxs_dma_ids,
+diff -Nur linux-3.14.72.orig/drivers/dma/pxp/Makefile linux-3.14.72/drivers/dma/pxp/Makefile
+--- linux-3.14.72.orig/drivers/dma/pxp/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/dma/pxp/Makefile 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_MXC_PXP_V2) += pxp_dma_v2.o
++obj-$(CONFIG_MXC_PXP_CLIENT_DEVICE) += pxp_device.o
+diff -Nur linux-3.14.72.orig/drivers/dma/pxp/pxp_device.c linux-3.14.72/drivers/dma/pxp/pxp_device.c
+--- linux-3.14.72.orig/drivers/dma/pxp/pxp_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/dma/pxp/pxp_device.c 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,762 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#include <linux/interrupt.h>
++#include <linux/miscdevice.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/uaccess.h>
++#include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/pxp_device.h>
++#include <linux/atomic.h>
++#include <linux/platform_data/dma-imx.h>
++
++#define BUFFER_HASH_ORDER 4
++
++static struct pxp_buffer_hash bufhash;
++static struct pxp_irq_info irq_info[NR_PXP_VIRT_CHANNEL];
++
++static int pxp_ht_create(struct pxp_buffer_hash *hash, int order)
++{
++ unsigned long i;
++ unsigned long table_size;
++
++ table_size = 1U << order;
++
++ hash->order = order;
++ hash->hash_table = kmalloc(sizeof(*hash->hash_table) * table_size, GFP_KERNEL);
++
++ if (!hash->hash_table) {
++ pr_err("%s: Out of memory for hash table\n", __func__);
++ return -ENOMEM;
++ }
++
++ for (i = 0; i < table_size; i++)
++ INIT_HLIST_HEAD(&hash->hash_table[i]);
++
++ return 0;
++}
++
++static int pxp_ht_insert_item(struct pxp_buffer_hash *hash,
++ struct pxp_buf_obj *new)
++{
++ unsigned long hashkey;
++ struct hlist_head *h_list;
++
++ hashkey = hash_long(new->offset >> PAGE_SHIFT, hash->order);
++ h_list = &hash->hash_table[hashkey];
++
++ spin_lock(&hash->hash_lock);
++ hlist_add_head_rcu(&new->item, h_list);
++ spin_unlock(&hash->hash_lock);
++
++ return 0;
++}
++
++static int pxp_ht_remove_item(struct pxp_buffer_hash *hash,
++ struct pxp_buf_obj *obj)
++{
++ spin_lock(&hash->hash_lock);
++ hlist_del_init_rcu(&obj->item);
++ spin_unlock(&hash->hash_lock);
++ return 0;
++}
++
++static struct hlist_node *pxp_ht_find_key(struct pxp_buffer_hash *hash,
++ unsigned long key)
++{
++ struct pxp_buf_obj *entry;
++ struct hlist_head *h_list;
++ unsigned long hashkey;
++
++ hashkey = hash_long(key, hash->order);
++ h_list = &hash->hash_table[hashkey];
++
++ hlist_for_each_entry_rcu(entry, h_list, item) {
++ if (entry->offset >> PAGE_SHIFT == key)
++ return &entry->item;
++ }
++
++ return NULL;
++}
++
++static void pxp_ht_destroy(struct pxp_buffer_hash *hash)
++{
++ kfree(hash->hash_table);
++ hash->hash_table = NULL;
++}
++
++static int pxp_buffer_handle_create(struct pxp_file *file_priv,
++ struct pxp_buf_obj *obj,
++ uint32_t *handlep)
++{
++ int ret;
++
++ idr_preload(GFP_KERNEL);
++ spin_lock(&file_priv->buffer_lock);
++
++ ret = idr_alloc(&file_priv->buffer_idr, obj, 1, 0, GFP_NOWAIT);
++
++ spin_unlock(&file_priv->buffer_lock);
++ idr_preload_end();
++
++ if (ret < 0)
++ return ret;
++
++ *handlep = ret;
++
++ return 0;
++}
++
++static struct pxp_buf_obj *
++pxp_buffer_object_lookup(struct pxp_file *file_priv,
++ uint32_t handle)
++{
++ struct pxp_buf_obj *obj;
++
++ spin_lock(&file_priv->buffer_lock);
++
++ obj = idr_find(&file_priv->buffer_idr, handle);
++ if (!obj) {
++ spin_unlock(&file_priv->buffer_lock);
++ return NULL;
++ }
++
++ spin_unlock(&file_priv->buffer_lock);
++
++ return obj;
++}
++
++static int pxp_buffer_handle_delete(struct pxp_file *file_priv,
++ uint32_t handle)
++{
++ struct pxp_buf_obj *obj;
++
++ spin_lock(&file_priv->buffer_lock);
++
++ obj = idr_find(&file_priv->buffer_idr, handle);
++ if (!obj) {
++ spin_unlock(&file_priv->buffer_lock);
++ return -EINVAL;
++ }
++
++ idr_remove(&file_priv->buffer_idr, handle);
++ spin_unlock(&file_priv->buffer_lock);
++
++ return 0;
++}
++
++static int pxp_channel_handle_create(struct pxp_file *file_priv,
++ struct pxp_chan_obj *obj,
++ uint32_t *handlep)
++{
++ int ret;
++
++ idr_preload(GFP_KERNEL);
++ spin_lock(&file_priv->channel_lock);
++
++ ret = idr_alloc(&file_priv->channel_idr, obj, 0, 0, GFP_NOWAIT);
++
++ spin_unlock(&file_priv->channel_lock);
++ idr_preload_end();
++
++ if (ret < 0)
++ return ret;
++
++ *handlep = ret;
++
++ return 0;
++}
++
++static struct pxp_chan_obj *
++pxp_channel_object_lookup(struct pxp_file *file_priv,
++ uint32_t handle)
++{
++ struct pxp_chan_obj *obj;
++
++ spin_lock(&file_priv->channel_lock);
++
++ obj = idr_find(&file_priv->channel_idr, handle);
++ if (!obj) {
++ spin_unlock(&file_priv->channel_lock);
++ return NULL;
++ }
++
++ spin_unlock(&file_priv->channel_lock);
++
++ return obj;
++}
++
++static int pxp_channel_handle_delete(struct pxp_file *file_priv,
++ uint32_t handle)
++{
++ struct pxp_chan_obj *obj;
++
++ spin_lock(&file_priv->channel_lock);
++
++ obj = idr_find(&file_priv->channel_idr, handle);
++ if (!obj) {
++ spin_unlock(&file_priv->channel_lock);
++ return -EINVAL;
++ }
++
++ idr_remove(&file_priv->channel_idr, handle);
++ spin_unlock(&file_priv->channel_lock);
++
++ return 0;
++}
++
++static int pxp_alloc_dma_buffer(struct pxp_buf_obj *obj)
++{
++ obj->virtual = dma_alloc_coherent(NULL, PAGE_ALIGN(obj->size),
++ (dma_addr_t *) (&obj->offset),
++ GFP_DMA | GFP_KERNEL);
++ pr_debug("[ALLOC] mem alloc phys_addr = 0x%lx\n", obj->offset);
++
++ if (obj->virtual == NULL) {
++ printk(KERN_ERR "Physical memory allocation error!\n");
++ return -1;
++ }
++
++ return 0;
++}
++
++static void pxp_free_dma_buffer(struct pxp_buf_obj *obj)
++{
++ if (obj->virtual != NULL) {
++ dma_free_coherent(0, PAGE_ALIGN(obj->size),
++ obj->virtual, (dma_addr_t)obj->offset);
++ }
++}
++
++static int
++pxp_buffer_object_free(int id, void *ptr, void *data)
++{
++ struct pxp_file *file_priv = data;
++ struct pxp_buf_obj *obj = ptr;
++ int ret;
++
++ ret = pxp_buffer_handle_delete(file_priv, obj->handle);
++ if (ret < 0)
++ return ret;
++
++ pxp_ht_remove_item(&bufhash, obj);
++ pxp_free_dma_buffer(obj);
++ kfree(obj);
++
++ return 0;
++}
++
++static int
++pxp_channel_object_free(int id, void *ptr, void *data)
++{
++ struct pxp_file *file_priv = data;
++ struct pxp_chan_obj *obj = ptr;
++ int chan_id;
++
++ chan_id = obj->chan->chan_id;
++ wait_event(irq_info[chan_id].waitq,
++ atomic_read(&irq_info[chan_id].irq_pending) == 0);
++
++ pxp_channel_handle_delete(file_priv, obj->handle);
++ dma_release_channel(obj->chan);
++ kfree(obj);
++
++ return 0;
++}
++
++static void pxp_free_buffers(struct pxp_file *file_priv)
++{
++ idr_for_each(&file_priv->buffer_idr,
++ &pxp_buffer_object_free, file_priv);
++ idr_destroy(&file_priv->buffer_idr);
++}
++
++static void pxp_free_channels(struct pxp_file *file_priv)
++{
++ idr_for_each(&file_priv->channel_idr,
++ &pxp_channel_object_free, file_priv);
++ idr_destroy(&file_priv->channel_idr);
++}
++
++/* Callback function triggered after PxP receives an EOF interrupt */
++static void pxp_dma_done(void *arg)
++{
++ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
++ struct dma_chan *chan = tx_desc->txd.chan;
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ int chan_id = pxp_chan->dma_chan.chan_id;
++
++ pr_debug("DMA Done ISR, chan_id %d\n", chan_id);
++
++ atomic_dec(&irq_info[chan_id].irq_pending);
++ irq_info[chan_id].hist_status = tx_desc->hist_status;
++
++ wake_up(&(irq_info[chan_id].waitq));
++}
++
++static int pxp_ioc_config_chan(struct pxp_file *priv, unsigned long arg)
++{
++ struct scatterlist sg[3];
++ struct pxp_tx_desc *desc;
++ struct dma_async_tx_descriptor *txd;
++ struct pxp_config_data pxp_conf;
++ dma_cookie_t cookie;
++ int handle, chan_id;
++ int i, length, ret;
++ struct dma_chan *chan;
++ struct pxp_chan_obj *obj;
++
++ ret = copy_from_user(&pxp_conf,
++ (struct pxp_config_data *)arg,
++ sizeof(struct pxp_config_data));
++ if (ret)
++ return -EFAULT;
++
++ handle = pxp_conf.handle;
++ obj = pxp_channel_object_lookup(priv, handle);
++ if (!obj)
++ return -EINVAL;
++ chan = obj->chan;
++ chan_id = chan->chan_id;
++
++ sg_init_table(sg, 3);
++
++ txd = chan->device->device_prep_slave_sg(chan,
++ sg, 3,
++ DMA_TO_DEVICE,
++ DMA_PREP_INTERRUPT,
++ NULL);
++ if (!txd) {
++ pr_err("Error preparing a DMA transaction descriptor.\n");
++ return -EIO;
++ }
++
++ txd->callback_param = txd;
++ txd->callback = pxp_dma_done;
++
++ desc = to_tx_desc(txd);
++
++ length = desc->len;
++ for (i = 0; i < length; i++) {
++ if (i == 0) { /* S0 */
++ memcpy(&desc->proc_data,
++ &pxp_conf.proc_data,
++ sizeof(struct pxp_proc_data));
++ memcpy(&desc->layer_param.s0_param,
++ &pxp_conf.s0_param,
++ sizeof(struct pxp_layer_param));
++ } else if (i == 1) { /* Output */
++ memcpy(&desc->layer_param.out_param,
++ &pxp_conf.out_param,
++ sizeof(struct pxp_layer_param));
++ } else {
++ /* OverLay */
++ memcpy(&desc->layer_param.ol_param,
++ &pxp_conf.ol_param,
++ sizeof(struct pxp_layer_param));
++ }
++
++ desc = desc->next;
++ }
++
++ cookie = txd->tx_submit(txd);
++ if (cookie < 0) {
++ pr_err("Error tx_submit\n");
++ return -EIO;
++ }
++
++ atomic_inc(&irq_info[chan_id].irq_pending);
++
++ return 0;
++}
++
++static int pxp_device_open(struct inode *inode, struct file *filp)
++{
++ struct pxp_file *priv;
++
++ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
++
++ if (!priv)
++ return -ENOMEM;
++
++ filp->private_data = priv;
++ priv->filp = filp;
++
++ idr_init(&priv->buffer_idr);
++ spin_lock_init(&priv->buffer_lock);
++
++ idr_init(&priv->channel_idr);
++ spin_lock_init(&priv->channel_lock);
++
++ return 0;
++}
++
++static int pxp_device_release(struct inode *inode, struct file *filp)
++{
++ struct pxp_file *priv = filp->private_data;
++
++ if (priv) {
++ pxp_free_channels(priv);
++ pxp_free_buffers(priv);
++ kfree(priv);
++ filp->private_data = NULL;
++ }
++
++ return 0;
++}
++
++static int pxp_device_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ int request_size;
++ struct hlist_node *node;
++ struct pxp_buf_obj *obj;
++
++ request_size = vma->vm_end - vma->vm_start;
++
++ pr_debug("start=0x%x, pgoff=0x%x, size=0x%x\n",
++ (unsigned int)(vma->vm_start), (unsigned int)(vma->vm_pgoff),
++ request_size);
++
++ node = pxp_ht_find_key(&bufhash, vma->vm_pgoff);
++ if (!node)
++ return -EINVAL;
++
++ obj = list_entry(node, struct pxp_buf_obj, item);
++ if (obj->offset + (obj->size >> PAGE_SHIFT) <
++ (vma->vm_pgoff + vma_pages(vma)))
++ return -ENOMEM;
++
++ switch (obj->mem_type) {
++ case MEMORY_TYPE_UNCACHED:
++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++ break;
++ case MEMORY_TYPE_WC:
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++ break;
++ case MEMORY_TYPE_CACHED:
++ break;
++ default:
++ pr_err("%s: invalid memory type!\n", __func__);
++ return -EINVAL;
++ }
++
++ return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ request_size, vma->vm_page_prot) ? -EAGAIN : 0;
++}
++
++static bool chan_filter(struct dma_chan *chan, void *arg)
++{
++ if (imx_dma_is_pxp(chan))
++ return true;
++ else
++ return false;
++}
++
++static long pxp_device_ioctl(struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ int ret = 0;
++ struct pxp_file *file_priv = filp->private_data;
++
++ switch (cmd) {
++ case PXP_IOC_GET_CHAN:
++ {
++ int ret;
++ struct dma_chan *chan = NULL;
++ dma_cap_mask_t mask;
++ struct pxp_chan_obj *obj = NULL;
++
++ pr_debug("drv: PXP_IOC_GET_CHAN Line %d\n", __LINE__);
++
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_PRIVATE, mask);
++
++ chan = dma_request_channel(mask, chan_filter, NULL);
++ if (!chan) {
++ pr_err("Unsccessfully received channel!\n");
++ return -EBUSY;
++ }
++
++ pr_debug("Successfully received channel."
++ "chan_id %d\n", chan->chan_id);
++
++ obj = kzalloc(sizeof(*obj), GFP_KERNEL);
++ if (!obj) {
++ dma_release_channel(chan);
++ return -ENOMEM;
++ }
++ obj->chan = chan;
++
++ ret = pxp_channel_handle_create(file_priv, obj,
++ &obj->handle);
++ if (ret) {
++ dma_release_channel(chan);
++ kfree(obj);
++ return ret;
++ }
++
++ init_waitqueue_head(&(irq_info[chan->chan_id].waitq));
++ if (put_user(obj->handle, (u32 __user *) arg)) {
++ pxp_channel_handle_delete(file_priv, obj->handle);
++ dma_release_channel(chan);
++ kfree(obj);
++ return -EFAULT;
++ }
++
++ break;
++ }
++ case PXP_IOC_PUT_CHAN:
++ {
++ int handle;
++ struct pxp_chan_obj *obj;
++
++ if (get_user(handle, (u32 __user *) arg))
++ return -EFAULT;
++
++ pr_debug("%d release handle %d\n", __LINE__, handle);
++
++ obj = pxp_channel_object_lookup(file_priv, handle);
++ if (!obj)
++ return -EINVAL;
++
++ pxp_channel_handle_delete(file_priv, obj->handle);
++ dma_release_channel(obj->chan);
++ kfree(obj);
++
++ break;
++ }
++ case PXP_IOC_CONFIG_CHAN:
++ {
++ int ret;
++
++ ret = pxp_ioc_config_chan(file_priv, arg);
++ if (ret)
++ return ret;
++
++ break;
++ }
++ case PXP_IOC_START_CHAN:
++ {
++ int handle;
++ struct pxp_chan_obj *obj = NULL;
++
++ if (get_user(handle, (u32 __user *) arg))
++ return -EFAULT;
++
++ obj = pxp_channel_object_lookup(file_priv, handle);
++ if (!obj)
++ return -EINVAL;
++
++ dma_async_issue_pending(obj->chan);
++
++ break;
++ }
++ case PXP_IOC_GET_PHYMEM:
++ {
++ struct pxp_mem_desc buffer;
++ struct pxp_buf_obj *obj;
++
++ ret = copy_from_user(&buffer,
++ (struct pxp_mem_desc *)arg,
++ sizeof(struct pxp_mem_desc));
++ if (ret)
++ return -EFAULT;
++
++ pr_debug("[ALLOC] mem alloc size = 0x%x\n",
++ buffer.size);
++
++ obj = kzalloc(sizeof(*obj), GFP_KERNEL);
++ if (!obj)
++ return -ENOMEM;
++ obj->size = buffer.size;
++ obj->mem_type = buffer.mtype;
++
++ ret = pxp_alloc_dma_buffer(obj);
++ if (ret == -1) {
++ printk(KERN_ERR
++ "Physical memory allocation error!\n");
++ kfree(obj);
++ return ret;
++ }
++
++ ret = pxp_buffer_handle_create(file_priv, obj, &obj->handle);
++ if (ret) {
++ pxp_free_dma_buffer(obj);
++ kfree(obj);
++ return ret;
++ }
++ buffer.handle = obj->handle;
++ buffer.phys_addr = obj->offset;
++
++ ret = copy_to_user((void __user *)arg, &buffer,
++ sizeof(struct pxp_mem_desc));
++ if (ret) {
++ pxp_buffer_handle_delete(file_priv, buffer.handle);
++ pxp_free_dma_buffer(obj);
++ kfree(obj);
++ return -EFAULT;
++ }
++
++ pxp_ht_insert_item(&bufhash, obj);
++
++ break;
++ }
++ case PXP_IOC_PUT_PHYMEM:
++ {
++ struct pxp_mem_desc pxp_mem;
++ struct pxp_buf_obj *obj;
++
++ ret = copy_from_user(&pxp_mem,
++ (struct pxp_mem_desc *)arg,
++ sizeof(struct pxp_mem_desc));
++ if (ret)
++ return -EACCES;
++
++ obj = pxp_buffer_object_lookup(file_priv, pxp_mem.handle);
++ if (!obj)
++ return -EINVAL;
++
++ ret = pxp_buffer_handle_delete(file_priv, obj->handle);
++ if (ret)
++ return ret;
++
++ pxp_ht_remove_item(&bufhash, obj);
++ pxp_free_dma_buffer(obj);
++ kfree(obj);
++
++ break;
++ }
++ case PXP_IOC_FLUSH_PHYMEM:
++ {
++ int ret;
++ struct pxp_mem_flush flush;
++ struct pxp_buf_obj *obj;
++
++ ret = copy_from_user(&flush,
++ (struct pxp_mem_flush *)arg,
++ sizeof(struct pxp_mem_flush));
++ if (ret)
++ return -EACCES;
++
++ obj = pxp_buffer_object_lookup(file_priv, flush.handle);
++ if (!obj)
++ return -EINVAL;
++
++ switch (flush.type) {
++ case CACHE_CLEAN:
++ dma_sync_single_for_device(NULL, obj->offset,
++ obj->size, DMA_TO_DEVICE);
++ break;
++ case CACHE_INVALIDATE:
++ dma_sync_single_for_device(NULL, obj->offset,
++ obj->size, DMA_FROM_DEVICE);
++ break;
++ case CACHE_FLUSH:
++ dma_sync_single_for_device(NULL, obj->offset,
++ obj->size, DMA_TO_DEVICE);
++ dma_sync_single_for_device(NULL, obj->offset,
++ obj->size, DMA_FROM_DEVICE);
++ break;
++ default:
++ pr_err("%s: invalid cache flush type\n", __func__);
++ return -EINVAL;
++ }
++
++ break;
++ }
++ case PXP_IOC_WAIT4CMPLT:
++ {
++ struct pxp_chan_handle chan_handle;
++ int ret, chan_id, handle;
++ struct pxp_chan_obj *obj = NULL;
++
++ ret = copy_from_user(&chan_handle,
++ (struct pxp_chan_handle *)arg,
++ sizeof(struct pxp_chan_handle));
++ if (ret)
++ return -EFAULT;
++
++ handle = chan_handle.handle;
++ obj = pxp_channel_object_lookup(file_priv, handle);
++ if (!obj)
++ return -EINVAL;
++ chan_id = obj->chan->chan_id;
++
++ ret = wait_event_interruptible
++ (irq_info[chan_id].waitq,
++ (atomic_read(&irq_info[chan_id].irq_pending) == 0));
++ if (ret < 0)
++ return -ERESTARTSYS;
++
++ chan_handle.hist_status = irq_info[chan_id].hist_status;
++ ret = copy_to_user((struct pxp_chan_handle *)arg,
++ &chan_handle,
++ sizeof(struct pxp_chan_handle));
++ if (ret)
++ return -EFAULT;
++ break;
++ }
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++static const struct file_operations pxp_device_fops = {
++ .open = pxp_device_open,
++ .release = pxp_device_release,
++ .unlocked_ioctl = pxp_device_ioctl,
++ .mmap = pxp_device_mmap,
++};
++
++static struct miscdevice pxp_device_miscdev = {
++ .minor = MISC_DYNAMIC_MINOR,
++ .name = "pxp_device",
++ .fops = &pxp_device_fops,
++};
++
++int register_pxp_device(void)
++{
++ int ret;
++
++ ret = misc_register(&pxp_device_miscdev);
++ if (ret)
++ return ret;
++
++ ret = pxp_ht_create(&bufhash, BUFFER_HASH_ORDER);
++ if (ret)
++ return ret;
++ spin_lock_init(&(bufhash.hash_lock));
++
++ pr_debug("PxP_Device registered Successfully\n");
++ return 0;
++}
++
++void unregister_pxp_device(void)
++{
++ pxp_ht_destroy(&bufhash);
++ misc_deregister(&pxp_device_miscdev);
++}
+diff -Nur linux-3.14.72.orig/drivers/dma/pxp/pxp_dma_v2.c linux-3.14.72/drivers/dma/pxp/pxp_dma_v2.c
+--- linux-3.14.72.orig/drivers/dma/pxp/pxp_dma_v2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/dma/pxp/pxp_dma_v2.c 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,1844 @@
++/*
++ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X PxP driver
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmaengine.h>
++#include <linux/freezer.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/pxp_dma.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/timer.h>
++#include <linux/vmalloc.h>
++#include <linux/workqueue.h>
++
++#include "regs-pxp_v2.h"
++
++#define PXP_DOWNSCALE_THRESHOLD 0x4000
++
++static LIST_HEAD(head);
++static int timeout_in_ms = 600;
++static unsigned int block_size;
++static struct kmem_cache *tx_desc_cache;
++
++struct pxp_dma {
++ struct dma_device dma;
++};
++
++struct pxps {
++ struct platform_device *pdev;
++ struct clk *clk;
++ struct clk *clk_disp_axi; /* may exist on some SoC for gating */
++ void __iomem *base;
++ int irq; /* PXP IRQ to the CPU */
++
++ spinlock_t lock;
++ struct mutex clk_mutex;
++ int clk_stat;
++#define CLK_STAT_OFF 0
++#define CLK_STAT_ON 1
++ int pxp_ongoing;
++ int lut_state;
++
++ struct device *dev;
++ struct pxp_dma pxp_dma;
++ struct pxp_channel channel[NR_PXP_VIRT_CHANNEL];
++ struct work_struct work;
++
++ /* describes most recent processing configuration */
++ struct pxp_config_data pxp_conf_state;
++
++ /* to turn clock off when pxp is inactive */
++ struct timer_list clk_timer;
++
++ /* for pxp config dispatch asynchronously*/
++ struct task_struct *dispatch;
++ wait_queue_head_t thread_waitq;
++ struct completion complete;
++};
++
++#define to_pxp_dma(d) container_of(d, struct pxp_dma, dma)
++#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
++#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
++#define to_pxp(id) container_of(id, struct pxps, pxp_dma)
++
++#define PXP_DEF_BUFS 2
++#define PXP_MIN_PIX 8
++
++/*
++ * PXP common functions
++ */
++static void dump_pxp_reg(struct pxps *pxp)
++{
++ dev_dbg(pxp->dev, "PXP_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CTRL));
++ dev_dbg(pxp->dev, "PXP_STAT 0x%x",
++ __raw_readl(pxp->base + HW_PXP_STAT));
++ dev_dbg(pxp->dev, "PXP_OUT_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_CTRL));
++ dev_dbg(pxp->dev, "PXP_OUT_BUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_BUF));
++ dev_dbg(pxp->dev, "PXP_OUT_BUF2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_BUF2));
++ dev_dbg(pxp->dev, "PXP_OUT_PITCH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_PITCH));
++ dev_dbg(pxp->dev, "PXP_OUT_LRC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_LRC));
++ dev_dbg(pxp->dev, "PXP_OUT_PS_ULC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_PS_ULC));
++ dev_dbg(pxp->dev, "PXP_OUT_PS_LRC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_PS_LRC));
++ dev_dbg(pxp->dev, "PXP_OUT_AS_ULC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_AS_ULC));
++ dev_dbg(pxp->dev, "PXP_OUT_AS_LRC 0x%x",
++ __raw_readl(pxp->base + HW_PXP_OUT_AS_LRC));
++ dev_dbg(pxp->dev, "PXP_PS_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_CTRL));
++ dev_dbg(pxp->dev, "PXP_PS_BUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_BUF));
++ dev_dbg(pxp->dev, "PXP_PS_UBUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_UBUF));
++ dev_dbg(pxp->dev, "PXP_PS_VBUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_VBUF));
++ dev_dbg(pxp->dev, "PXP_PS_PITCH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_PITCH));
++ dev_dbg(pxp->dev, "PXP_PS_BACKGROUND 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_BACKGROUND));
++ dev_dbg(pxp->dev, "PXP_PS_SCALE 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_SCALE));
++ dev_dbg(pxp->dev, "PXP_PS_OFFSET 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_OFFSET));
++ dev_dbg(pxp->dev, "PXP_PS_CLRKEYLOW 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYLOW));
++ dev_dbg(pxp->dev, "PXP_PS_CLRKEYHIGH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_PS_CLRKEYHIGH));
++ dev_dbg(pxp->dev, "PXP_AS_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_CTRL));
++ dev_dbg(pxp->dev, "PXP_AS_BUF 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_BUF));
++ dev_dbg(pxp->dev, "PXP_AS_PITCH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_PITCH));
++ dev_dbg(pxp->dev, "PXP_AS_CLRKEYLOW 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYLOW));
++ dev_dbg(pxp->dev, "PXP_AS_CLRKEYHIGH 0x%x",
++ __raw_readl(pxp->base + HW_PXP_AS_CLRKEYHIGH));
++ dev_dbg(pxp->dev, "PXP_CSC1_COEF0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC1_COEF0));
++ dev_dbg(pxp->dev, "PXP_CSC1_COEF1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC1_COEF1));
++ dev_dbg(pxp->dev, "PXP_CSC1_COEF2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC1_COEF2));
++ dev_dbg(pxp->dev, "PXP_CSC2_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_CTRL));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF0));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF1));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF2));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF3 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF3));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF4 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF4));
++ dev_dbg(pxp->dev, "PXP_CSC2_COEF5 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CSC2_COEF5));
++ dev_dbg(pxp->dev, "PXP_LUT_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_CTRL));
++ dev_dbg(pxp->dev, "PXP_LUT_ADDR 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_ADDR));
++ dev_dbg(pxp->dev, "PXP_LUT_DATA 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_DATA));
++ dev_dbg(pxp->dev, "PXP_LUT_EXTMEM 0x%x",
++ __raw_readl(pxp->base + HW_PXP_LUT_EXTMEM));
++ dev_dbg(pxp->dev, "PXP_CFA 0x%x",
++ __raw_readl(pxp->base + HW_PXP_CFA));
++ dev_dbg(pxp->dev, "PXP_HIST_CTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST_CTRL));
++ dev_dbg(pxp->dev, "PXP_HIST2_PARAM 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST2_PARAM));
++ dev_dbg(pxp->dev, "PXP_HIST4_PARAM 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST4_PARAM));
++ dev_dbg(pxp->dev, "PXP_HIST8_PARAM0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST8_PARAM0));
++ dev_dbg(pxp->dev, "PXP_HIST8_PARAM1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST8_PARAM1));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM0 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM0));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM1 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM1));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM2 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM2));
++ dev_dbg(pxp->dev, "PXP_HIST16_PARAM3 0x%x",
++ __raw_readl(pxp->base + HW_PXP_HIST16_PARAM3));
++ dev_dbg(pxp->dev, "PXP_POWER 0x%x",
++ __raw_readl(pxp->base + HW_PXP_POWER));
++ dev_dbg(pxp->dev, "PXP_NEXT 0x%x",
++ __raw_readl(pxp->base + HW_PXP_NEXT));
++ dev_dbg(pxp->dev, "PXP_DEBUGCTRL 0x%x",
++ __raw_readl(pxp->base + HW_PXP_DEBUGCTRL));
++ dev_dbg(pxp->dev, "PXP_DEBUG 0x%x",
++ __raw_readl(pxp->base + HW_PXP_DEBUG));
++ dev_dbg(pxp->dev, "PXP_VERSION 0x%x",
++ __raw_readl(pxp->base + HW_PXP_VERSION));
++}
++
++static bool is_yuv(u32 pix_fmt)
++{
++ if ((pix_fmt == PXP_PIX_FMT_YUYV) |
++ (pix_fmt == PXP_PIX_FMT_UYVY) |
++ (pix_fmt == PXP_PIX_FMT_YVYU) |
++ (pix_fmt == PXP_PIX_FMT_VYUY) |
++ (pix_fmt == PXP_PIX_FMT_Y41P) |
++ (pix_fmt == PXP_PIX_FMT_VUY444) |
++ (pix_fmt == PXP_PIX_FMT_NV12) |
++ (pix_fmt == PXP_PIX_FMT_NV16) |
++ (pix_fmt == PXP_PIX_FMT_NV61) |
++ (pix_fmt == PXP_PIX_FMT_GREY) |
++ (pix_fmt == PXP_PIX_FMT_GY04) |
++ (pix_fmt == PXP_PIX_FMT_YVU410P) |
++ (pix_fmt == PXP_PIX_FMT_YUV410P) |
++ (pix_fmt == PXP_PIX_FMT_YVU420P) |
++ (pix_fmt == PXP_PIX_FMT_YUV420P) |
++ (pix_fmt == PXP_PIX_FMT_YUV420P2) |
++ (pix_fmt == PXP_PIX_FMT_YVU422P) |
++ (pix_fmt == PXP_PIX_FMT_YUV422P)) {
++ return true;
++ } else {
++ return false;
++ }
++}
++
++static void pxp_soft_reset(struct pxps *pxp)
++{
++ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR);
++ __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR);
++
++ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_SET);
++ while (!(__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_CLKGATE))
++ dev_dbg(pxp->dev, "%s: wait for clock gate off", __func__);
++
++ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL_CLR);
++ __raw_writel(BM_PXP_CTRL_CLKGATE, pxp->base + HW_PXP_CTRL_CLR);
++}
++
++static void pxp_set_ctrl(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ u32 ctrl;
++ u32 fmt_ctrl;
++ int need_swap = 0; /* to support YUYV and YVYU formats */
++
++ /* Configure S0 input format */
++ switch (pxp_conf->s0_param.pixel_fmt) {
++ case PXP_PIX_FMT_RGB32:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB888;
++ break;
++ case PXP_PIX_FMT_RGB565:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB565;
++ break;
++ case PXP_PIX_FMT_RGB555:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__RGB555;
++ break;
++ case PXP_PIX_FMT_YUV420P:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420;
++ break;
++ case PXP_PIX_FMT_YVU420P:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV420;
++ break;
++ case PXP_PIX_FMT_GREY:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8;
++ break;
++ case PXP_PIX_FMT_GY04:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4;
++ break;
++ case PXP_PIX_FMT_VUY444:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444;
++ break;
++ case PXP_PIX_FMT_YUV422P:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422;
++ break;
++ case PXP_PIX_FMT_UYVY:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
++ break;
++ case PXP_PIX_FMT_YUYV:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422;
++ need_swap = 1;
++ break;
++ case PXP_PIX_FMT_VYUY:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
++ break;
++ case PXP_PIX_FMT_YVYU:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__VYUY1P422;
++ need_swap = 1;
++ break;
++ case PXP_PIX_FMT_NV12:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P420;
++ break;
++ case PXP_PIX_FMT_NV21:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P420;
++ break;
++ case PXP_PIX_FMT_NV16:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV2P422;
++ break;
++ case PXP_PIX_FMT_NV61:
++ fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YVU2P422;
++ break;
++ default:
++ fmt_ctrl = 0;
++ }
++
++ ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap);
++ __raw_writel(ctrl, pxp->base + HW_PXP_PS_CTRL_SET);
++
++ /* Configure output format based on out_channel format */
++ switch (pxp_conf->out_param.pixel_fmt) {
++ case PXP_PIX_FMT_RGB32:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888;
++ break;
++ case PXP_PIX_FMT_BGRA32:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__ARGB8888;
++ break;
++ case PXP_PIX_FMT_RGB24:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888P;
++ break;
++ case PXP_PIX_FMT_RGB565:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565;
++ break;
++ case PXP_PIX_FMT_RGB555:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB555;
++ break;
++ case PXP_PIX_FMT_GREY:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8;
++ break;
++ case PXP_PIX_FMT_GY04:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4;
++ break;
++ case PXP_PIX_FMT_UYVY:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__UYVY1P422;
++ break;
++ case PXP_PIX_FMT_VYUY:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__VYUY1P422;
++ break;
++ case PXP_PIX_FMT_NV12:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P420;
++ break;
++ case PXP_PIX_FMT_NV21:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P420;
++ break;
++ case PXP_PIX_FMT_NV16:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YUV2P422;
++ break;
++ case PXP_PIX_FMT_NV61:
++ fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__YVU2P422;
++ break;
++ default:
++ fmt_ctrl = 0;
++ }
++
++ ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl);
++ __raw_writel(ctrl, pxp->base + HW_PXP_OUT_CTRL);
++
++ ctrl = 0;
++ if (proc_data->scaling)
++ ;
++ if (proc_data->vflip)
++ ctrl |= BM_PXP_CTRL_VFLIP;
++ if (proc_data->hflip)
++ ctrl |= BM_PXP_CTRL_HFLIP;
++ if (proc_data->rotate)
++ ctrl |= BF_PXP_CTRL_ROTATE(proc_data->rotate / 90);
++
++ /* In default, the block size is set to 8x8
++ * But block size can be set to 16x16 due to
++ * blocksize variable modification
++ */
++ ctrl |= block_size << 23;
++
++ __raw_writel(ctrl, pxp->base + HW_PXP_CTRL);
++}
++
++static int pxp_start(struct pxps *pxp)
++{
++ __raw_writel(BM_PXP_CTRL_IRQ_ENABLE, pxp->base + HW_PXP_CTRL_SET);
++ __raw_writel(BM_PXP_CTRL_ENABLE, pxp->base + HW_PXP_CTRL_SET);
++ dump_pxp_reg(pxp);
++
++ return 0;
++}
++
++static void pxp_set_outbuf(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *out_params = &pxp_conf->out_param;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++
++ __raw_writel(out_params->paddr, pxp->base + HW_PXP_OUT_BUF);
++
++ if (proc_data->rotate == 90 || proc_data->rotate == 270)
++ __raw_writel(BF_PXP_OUT_LRC_X(out_params->height - 1) |
++ BF_PXP_OUT_LRC_Y(out_params->width - 1),
++ pxp->base + HW_PXP_OUT_LRC);
++ else
++ __raw_writel(BF_PXP_OUT_LRC_X(out_params->width - 1) |
++ BF_PXP_OUT_LRC_Y(out_params->height - 1),
++ pxp->base + HW_PXP_OUT_LRC);
++
++ if (out_params->pixel_fmt == PXP_PIX_FMT_RGB24) {
++ __raw_writel(out_params->stride * 3,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_BGRA32 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_RGB32) {
++ __raw_writel(out_params->stride << 2,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_RGB565) {
++ __raw_writel(out_params->stride << 1,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_UYVY ||
++ (out_params->pixel_fmt == PXP_PIX_FMT_VYUY)) {
++ __raw_writel(out_params->stride << 1,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_GREY ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV12 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV21 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV16 ||
++ out_params->pixel_fmt == PXP_PIX_FMT_NV61) {
++ __raw_writel(out_params->stride,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else if (out_params->pixel_fmt == PXP_PIX_FMT_GY04) {
++ __raw_writel(out_params->stride >> 1,
++ pxp->base + HW_PXP_OUT_PITCH);
++ } else {
++ __raw_writel(0, pxp->base + HW_PXP_OUT_PITCH);
++ }
++
++ /* set global alpha if necessary */
++ if (out_params->global_alpha_enable) {
++ __raw_writel(out_params->global_alpha << 24,
++ pxp->base + HW_PXP_OUT_CTRL_SET);
++ __raw_writel(BM_PXP_OUT_CTRL_ALPHA_OUTPUT,
++ pxp->base + HW_PXP_OUT_CTRL_SET);
++ }
++}
++
++static void pxp_set_s0colorkey(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
++
++ /* Low and high are set equal. V4L does not allow a chromakey range */
++ if (s0_params->color_key_enable == 0 || s0_params->color_key == -1) {
++ /* disable color key */
++ __raw_writel(0xFFFFFF, pxp->base + HW_PXP_PS_CLRKEYLOW);
++ __raw_writel(0, pxp->base + HW_PXP_PS_CLRKEYHIGH);
++ } else {
++ __raw_writel(s0_params->color_key,
++ pxp->base + HW_PXP_PS_CLRKEYLOW);
++ __raw_writel(s0_params->color_key,
++ pxp->base + HW_PXP_PS_CLRKEYHIGH);
++ }
++}
++
++static void pxp_set_olcolorkey(int layer_no, struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *ol_params = &pxp_conf->ol_param[layer_no];
++
++ /* Low and high are set equal. V4L does not allow a chromakey range */
++ if (ol_params->color_key_enable != 0 && ol_params->color_key != -1) {
++ __raw_writel(ol_params->color_key,
++ pxp->base + HW_PXP_AS_CLRKEYLOW);
++ __raw_writel(ol_params->color_key,
++ pxp->base + HW_PXP_AS_CLRKEYHIGH);
++ } else {
++ /* disable color key */
++ __raw_writel(0xFFFFFF, pxp->base + HW_PXP_AS_CLRKEYLOW);
++ __raw_writel(0, pxp->base + HW_PXP_AS_CLRKEYHIGH);
++ }
++}
++
++static void pxp_set_oln(int layer_no, struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
++ dma_addr_t phys_addr = olparams_data->paddr;
++ u32 pitch = olparams_data->stride ? olparams_data->stride :
++ olparams_data->width;
++
++ __raw_writel(phys_addr, pxp->base + HW_PXP_AS_BUF);
++
++ /* Fixme */
++ if (olparams_data->width == 0 && olparams_data->height == 0) {
++ __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_AS_ULC);
++ __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_LRC);
++ } else {
++ __raw_writel(0x0, pxp->base + HW_PXP_OUT_AS_ULC);
++ __raw_writel(BF_PXP_OUT_AS_LRC_X(olparams_data->width - 1) |
++ BF_PXP_OUT_AS_LRC_Y(olparams_data->height - 1),
++ pxp->base + HW_PXP_OUT_AS_LRC);
++ }
++
++ if ((olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) |
++ (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB32)) {
++ __raw_writel(pitch << 2,
++ pxp->base + HW_PXP_AS_PITCH);
++ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) {
++ __raw_writel(pitch << 1,
++ pxp->base + HW_PXP_AS_PITCH);
++ } else {
++ __raw_writel(0, pxp->base + HW_PXP_AS_PITCH);
++ }
++}
++
++static void pxp_set_olparam(int layer_no, struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *olparams_data = &pxp_conf->ol_param[layer_no];
++ u32 olparam;
++
++ olparam = BF_PXP_AS_CTRL_ALPHA(olparams_data->global_alpha);
++ if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB32) {
++ olparam |=
++ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB888);
++ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_BGRA32) {
++ olparam |=
++ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__ARGB8888);
++ if (!olparams_data->combine_enable) {
++ olparam |=
++ BF_PXP_AS_CTRL_ALPHA_CTRL
++ (BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs);
++ olparam |= 0x3 << 16;
++ }
++ } else if (olparams_data->pixel_fmt == PXP_PIX_FMT_RGB565) {
++ olparam |=
++ BF_PXP_AS_CTRL_FORMAT(BV_PXP_AS_CTRL_FORMAT__RGB565);
++ }
++ if (olparams_data->global_alpha_enable) {
++ if (olparams_data->global_override) {
++ olparam |=
++ BF_PXP_AS_CTRL_ALPHA_CTRL
++ (BV_PXP_AS_CTRL_ALPHA_CTRL__Override);
++ } else {
++ olparam |=
++ BF_PXP_AS_CTRL_ALPHA_CTRL
++ (BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply);
++ }
++ if (olparams_data->alpha_invert)
++ olparam |= BM_PXP_AS_CTRL_ALPHA_INVERT;
++ }
++ if (olparams_data->color_key_enable)
++ olparam |= BM_PXP_AS_CTRL_ENABLE_COLORKEY;
++
++ __raw_writel(olparam, pxp->base + HW_PXP_AS_CTRL);
++}
++
++static void pxp_set_s0param(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ struct pxp_layer_param *out_params = &pxp_conf->out_param;
++ u32 s0param_ulc, s0param_lrc;
++
++ /* contains the coordinate for the PS in the OUTPUT buffer. */
++ if ((pxp_conf->s0_param).width == 0 &&
++ (pxp_conf->s0_param).height == 0) {
++ __raw_writel(0xffffffff, pxp->base + HW_PXP_OUT_PS_ULC);
++ __raw_writel(0x0, pxp->base + HW_PXP_OUT_PS_LRC);
++ } else {
++ switch (proc_data->rotate) {
++ case 0:
++ s0param_ulc = BF_PXP_OUT_PS_ULC_X(proc_data->drect.left);
++ s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.top);
++ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1);
++ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1);
++ break;
++ case 90:
++ s0param_ulc = BF_PXP_OUT_PS_ULC_Y(out_params->width - (proc_data->drect.left + proc_data->drect.width));
++ s0param_ulc |= BF_PXP_OUT_PS_ULC_X(proc_data->drect.top);
++ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1);
++ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1);
++ break;
++ case 180:
++ s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->width - (proc_data->drect.left + proc_data->drect.width));
++ s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(out_params->height - (proc_data->drect.top + proc_data->drect.height));
++ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.width - 1);
++ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.height - 1);
++ break;
++ case 270:
++ s0param_ulc = BF_PXP_OUT_PS_ULC_X(out_params->height - (proc_data->drect.top + proc_data->drect.height));
++ s0param_ulc |= BF_PXP_OUT_PS_ULC_Y(proc_data->drect.left);
++ s0param_lrc = BF_PXP_OUT_PS_LRC_X(((s0param_ulc & BM_PXP_OUT_PS_ULC_X) >> 16) + proc_data->drect.height - 1);
++ s0param_lrc |= BF_PXP_OUT_PS_LRC_Y((s0param_ulc & BM_PXP_OUT_PS_ULC_Y) + proc_data->drect.width - 1);
++ break;
++ default:
++ return;
++ }
++ __raw_writel(s0param_ulc, pxp->base + HW_PXP_OUT_PS_ULC);
++ __raw_writel(s0param_lrc, pxp->base + HW_PXP_OUT_PS_LRC);
++ }
++
++ /* Since user apps always pass the rotated drect
++ * to this driver, we need to first swap the width
++ * and height which is used to calculate the scale
++ * factors later.
++ */
++ if (proc_data->rotate == 90 || proc_data->rotate == 270) {
++ int temp;
++ temp = proc_data->drect.width;
++ proc_data->drect.width = proc_data->drect.height;
++ proc_data->drect.height = temp;
++ }
++}
++
++/* crop behavior is re-designed in h/w. */
++static void pxp_set_s0crop(struct pxps *pxp)
++{
++ /*
++ * place-holder, it's implemented in other functions in this driver.
++ * Refer to "Clipping source images" section in RM for detail.
++ */
++}
++
++static int pxp_set_scaling(struct pxps *pxp)
++{
++ int ret = 0;
++ u32 xscale, yscale, s0scale;
++ u32 decx, decy, xdec = 0, ydec = 0;
++ struct pxp_proc_data *proc_data = &pxp->pxp_conf_state.proc_data;
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
++
++ proc_data->scaling = 1;
++ decx = proc_data->srect.width / proc_data->drect.width;
++ decy = proc_data->srect.height / proc_data->drect.height;
++ if (decx > 1) {
++ if (decx >= 2 && decx < 4) {
++ decx = 2;
++ xdec = 1;
++ } else if (decx >= 4 && decx < 8) {
++ decx = 4;
++ xdec = 2;
++ } else if (decx >= 8) {
++ decx = 8;
++ xdec = 3;
++ }
++ xscale = proc_data->srect.width * 0x1000 /
++ (proc_data->drect.width * decx);
++ } else {
++ if (!is_yuv(s0_params->pixel_fmt) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_VUY444)) {
++ if ((proc_data->srect.width > 1) &&
++ (proc_data->drect.width > 1))
++ xscale = (proc_data->srect.width - 1) * 0x1000 /
++ (proc_data->drect.width - 1);
++ else
++ xscale = proc_data->srect.width * 0x1000 /
++ proc_data->drect.width;
++ } else {
++ if ((proc_data->srect.width > 2) &&
++ (proc_data->drect.width > 1))
++ xscale = (proc_data->srect.width - 2) * 0x1000 /
++ (proc_data->drect.width - 1);
++ else
++ xscale = proc_data->srect.width * 0x1000 /
++ proc_data->drect.width;
++ }
++ }
++ if (decy > 1) {
++ if (decy >= 2 && decy < 4) {
++ decy = 2;
++ ydec = 1;
++ } else if (decy >= 4 && decy < 8) {
++ decy = 4;
++ ydec = 2;
++ } else if (decy >= 8) {
++ decy = 8;
++ ydec = 3;
++ }
++ yscale = proc_data->srect.height * 0x1000 /
++ (proc_data->drect.height * decy);
++ } else {
++ if ((proc_data->srect.height > 1) &&
++ (proc_data->drect.height > 1))
++ yscale = (proc_data->srect.height - 1) * 0x1000 /
++ (proc_data->drect.height - 1);
++ else
++ yscale = proc_data->srect.height * 0x1000 /
++ proc_data->drect.height;
++ }
++
++ __raw_writel((xdec << 10) | (ydec << 8), pxp->base + HW_PXP_PS_CTRL);
++
++ if (xscale > PXP_DOWNSCALE_THRESHOLD)
++ xscale = PXP_DOWNSCALE_THRESHOLD;
++ if (yscale > PXP_DOWNSCALE_THRESHOLD)
++ yscale = PXP_DOWNSCALE_THRESHOLD;
++ s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) |
++ BF_PXP_PS_SCALE_XSCALE(xscale);
++ __raw_writel(s0scale, pxp->base + HW_PXP_PS_SCALE);
++
++ pxp_set_ctrl(pxp);
++
++ return ret;
++}
++
++static void pxp_set_bg(struct pxps *pxp)
++{
++ __raw_writel(pxp->pxp_conf_state.proc_data.bgcolor,
++ pxp->base + HW_PXP_PS_BACKGROUND);
++}
++
++static void pxp_set_lut(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ int lut_op = pxp_conf->proc_data.lut_transform;
++ u32 reg_val;
++ int i;
++ bool use_cmap = (lut_op & PXP_LUT_USE_CMAP) ? true : false;
++ u8 *cmap = pxp_conf->proc_data.lut_map;
++ u32 entry_src;
++ u32 pix_val;
++ u8 entry[4];
++
++ /*
++ * If LUT already configured as needed, return...
++ * Unless CMAP is needed and it has been updated.
++ */
++ if ((pxp->lut_state == lut_op) &&
++ !(use_cmap && pxp_conf->proc_data.lut_map_updated))
++ return;
++
++ if (lut_op == PXP_LUT_NONE) {
++ __raw_writel(BM_PXP_LUT_CTRL_BYPASS,
++ pxp->base + HW_PXP_LUT_CTRL);
++ } else if (((lut_op & PXP_LUT_INVERT) != 0)
++ && ((lut_op & PXP_LUT_BLACK_WHITE) != 0)) {
++ /* Fill out LUT table with inverted monochromized values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++) {
++ entry_src = use_cmap ?
++ cmap[pix_val + i] : pix_val + i;
++ entry[i] = (entry_src < 0x80) ? 0xFF : 0x00;
++ }
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ } else if ((lut_op & PXP_LUT_INVERT) != 0) {
++ /* Fill out LUT table with 8-bit inverted values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++) {
++ entry_src = use_cmap ?
++ cmap[pix_val + i] : pix_val + i;
++ entry[i] = ~entry_src & 0xFF;
++ }
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ } else if ((lut_op & PXP_LUT_BLACK_WHITE) != 0) {
++ /* Fill out LUT table with 8-bit monochromized values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++) {
++ entry_src = use_cmap ?
++ cmap[pix_val + i] : pix_val + i;
++ entry[i] = (entry_src < 0x80) ? 0x00 : 0xFF;
++ }
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ } else if (use_cmap) {
++ /* Fill out LUT table using colormap values */
++
++ /* clear bypass bit, set lookup mode & out mode */
++ __raw_writel(BF_PXP_LUT_CTRL_LOOKUP_MODE
++ (BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8) |
++ BF_PXP_LUT_CTRL_OUT_MODE
++ (BV_PXP_LUT_CTRL_OUT_MODE__Y8),
++ pxp->base + HW_PXP_LUT_CTRL);
++
++ /* Initialize LUT address to 0 and set NUM_BYTES to 0 */
++ __raw_writel(0, pxp->base + HW_PXP_LUT_ADDR);
++
++ /* LUT address pointer auto-increments after each data write */
++ for (pix_val = 0; pix_val < 256; pix_val += 4) {
++ for (i = 0; i < 4; i++)
++ entry[i] = cmap[pix_val + i];
++ reg_val = (entry[3] << 24) | (entry[2] << 16) |
++ (entry[1] << 8) | entry[0];
++ __raw_writel(reg_val, pxp->base + HW_PXP_LUT_DATA);
++ }
++ }
++
++ pxp->lut_state = lut_op;
++}
++
++static void pxp_set_csc(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
++ struct pxp_layer_param *ol_params = &pxp_conf->ol_param[0];
++ struct pxp_layer_param *out_params = &pxp_conf->out_param;
++
++ bool input_is_YUV = is_yuv(s0_params->pixel_fmt);
++ bool output_is_YUV = is_yuv(out_params->pixel_fmt);
++
++ if (input_is_YUV && output_is_YUV) {
++ /*
++ * Input = YUV, Output = YUV
++ * No CSC unless we need to do combining
++ */
++ if (ol_params->combine_enable) {
++ /* Must convert to RGB for combining with RGB overlay */
++
++ /* CSC1 - YUV->RGB */
++ __raw_writel(0x04030000, pxp->base + HW_PXP_CSC1_COEF0);
++ __raw_writel(0x01230208, pxp->base + HW_PXP_CSC1_COEF1);
++ __raw_writel(0x076b079c, pxp->base + HW_PXP_CSC1_COEF2);
++
++ /* CSC2 - RGB->YUV */
++ __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL);
++ __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0);
++ __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1);
++ __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2);
++ __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3);
++ __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4);
++ __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5);
++ } else {
++ /* Input & Output both YUV, so bypass both CSCs */
++
++ /* CSC1 - Bypass */
++ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
++
++ /* CSC2 - Bypass */
++ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
++ }
++ } else if (input_is_YUV && !output_is_YUV) {
++ /*
++ * Input = YUV, Output = RGB
++ * Use CSC1 to convert to RGB
++ */
++
++ /* CSC1 - YUV->RGB */
++ __raw_writel(0x84ab01f0, pxp->base + HW_PXP_CSC1_COEF0);
++ __raw_writel(0x01980204, pxp->base + HW_PXP_CSC1_COEF1);
++ __raw_writel(0x0730079c, pxp->base + HW_PXP_CSC1_COEF2);
++
++ /* CSC2 - Bypass */
++ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
++ } else if (!input_is_YUV && output_is_YUV) {
++ /*
++ * Input = RGB, Output = YUV
++ * Use CSC2 to convert to YUV
++ */
++
++ /* CSC1 - Bypass */
++ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
++
++ /* CSC2 - RGB->YUV */
++ __raw_writel(0x4, pxp->base + HW_PXP_CSC2_CTRL);
++ __raw_writel(0x0096004D, pxp->base + HW_PXP_CSC2_COEF0);
++ __raw_writel(0x05DA001D, pxp->base + HW_PXP_CSC2_COEF1);
++ __raw_writel(0x007005B6, pxp->base + HW_PXP_CSC2_COEF2);
++ __raw_writel(0x057C009E, pxp->base + HW_PXP_CSC2_COEF3);
++ __raw_writel(0x000005E6, pxp->base + HW_PXP_CSC2_COEF4);
++ __raw_writel(0x00000000, pxp->base + HW_PXP_CSC2_COEF5);
++ } else {
++ /*
++ * Input = RGB, Output = RGB
++ * Input & Output both RGB, so bypass both CSCs
++ */
++
++ /* CSC1 - Bypass */
++ __raw_writel(0x40000000, pxp->base + HW_PXP_CSC1_COEF0);
++
++ /* CSC2 - Bypass */
++ __raw_writel(0x1, pxp->base + HW_PXP_CSC2_CTRL);
++ }
++
++ /* YCrCb colorspace */
++ /* Not sure when we use this...no YCrCb formats are defined for PxP */
++ /*
++ __raw_writel(0x84ab01f0, HW_PXP_CSCCOEFF0_ADDR);
++ __raw_writel(0x01230204, HW_PXP_CSCCOEFF1_ADDR);
++ __raw_writel(0x0730079c, HW_PXP_CSCCOEFF2_ADDR);
++ */
++
++}
++
++static void pxp_set_s0buf(struct pxps *pxp)
++{
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf_state;
++ struct pxp_layer_param *s0_params = &pxp_conf->s0_param;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ dma_addr_t Y, U, V;
++ dma_addr_t Y1, U1, V1;
++ u32 offset, bpp = 1;
++ u32 pitch = s0_params->stride ? s0_params->stride :
++ s0_params->width;
++
++ Y = s0_params->paddr;
++
++ if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB565)
++ bpp = 2;
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB32)
++ bpp = 4;
++ offset = (proc_data->srect.top * s0_params->width +
++ proc_data->srect.left) * bpp;
++ /* clipping or cropping */
++ Y1 = Y + offset;
++ __raw_writel(Y1, pxp->base + HW_PXP_PS_BUF);
++ if ((s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)) {
++ /* Set to 1 if YUV format is 4:2:2 rather than 4:2:0 */
++ int s = 2;
++ if (s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P)
++ s = 1;
++
++ offset = proc_data->srect.top * s0_params->width / 4 +
++ proc_data->srect.left / 2;
++ U = Y + (s0_params->width * s0_params->height);
++ U1 = U + offset;
++ V = U + ((s0_params->width * s0_params->height) >> s);
++ V1 = V + offset;
++ if (s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P) {
++ __raw_writel(V1, pxp->base + HW_PXP_PS_UBUF);
++ __raw_writel(U1, pxp->base + HW_PXP_PS_VBUF);
++ } else {
++ __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF);
++ __raw_writel(V1, pxp->base + HW_PXP_PS_VBUF);
++ }
++ } else if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV12) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV21) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV16) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV61)) {
++ int s = 2;
++ if ((s0_params->pixel_fmt == PXP_PIX_FMT_NV16) ||
++ (s0_params->pixel_fmt == PXP_PIX_FMT_NV61))
++ s = 1;
++
++ offset = (proc_data->srect.top * s0_params->width +
++ proc_data->srect.left) / s;
++ U = Y + (s0_params->width * s0_params->height);
++ U1 = U + offset;
++
++ __raw_writel(U1, pxp->base + HW_PXP_PS_UBUF);
++ }
++
++ /* TODO: only support RGB565, Y8, Y4, YUV420 */
++ if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YUV420P ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YVU420P ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV12 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV21 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV16 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_NV61 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YUV422P) {
++ __raw_writel(pitch, pxp->base + HW_PXP_PS_PITCH);
++ }
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04)
++ __raw_writel(pitch >> 1,
++ pxp->base + HW_PXP_PS_PITCH);
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB32 ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_VUY444)
++ __raw_writel(pitch << 2,
++ pxp->base + HW_PXP_PS_PITCH);
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_UYVY ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YUYV ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_VYUY ||
++ s0_params->pixel_fmt == PXP_PIX_FMT_YVYU)
++ __raw_writel(pitch << 1,
++ pxp->base + HW_PXP_PS_PITCH);
++ else if (s0_params->pixel_fmt == PXP_PIX_FMT_RGB565)
++ __raw_writel(pitch << 1,
++ pxp->base + HW_PXP_PS_PITCH);
++ else
++ __raw_writel(0, pxp->base + HW_PXP_PS_PITCH);
++}
++
++/**
++ * pxp_config() - configure PxP for a processing task
++ * @pxps: PXP context.
++ * @pxp_chan: PXP channel.
++ * @return: 0 on success or negative error code on failure.
++ */
++static int pxp_config(struct pxps *pxp, struct pxp_channel *pxp_chan)
++{
++ struct pxp_config_data *pxp_conf_data = &pxp->pxp_conf_state;
++ int ol_nr;
++ int i;
++
++ /* Configure PxP regs */
++ pxp_set_ctrl(pxp);
++ pxp_set_s0param(pxp);
++ pxp_set_s0crop(pxp);
++ pxp_set_scaling(pxp);
++ ol_nr = pxp_conf_data->layer_nr - 2;
++ while (ol_nr > 0) {
++ i = pxp_conf_data->layer_nr - 2 - ol_nr;
++ pxp_set_oln(i, pxp);
++ pxp_set_olparam(i, pxp);
++ /* only the color key in higher overlay will take effect. */
++ pxp_set_olcolorkey(i, pxp);
++ ol_nr--;
++ }
++ pxp_set_s0colorkey(pxp);
++ pxp_set_csc(pxp);
++ pxp_set_bg(pxp);
++ pxp_set_lut(pxp);
++
++ pxp_set_s0buf(pxp);
++ pxp_set_outbuf(pxp);
++
++ return 0;
++}
++
++static void pxp_clk_enable(struct pxps *pxp)
++{
++ mutex_lock(&pxp->clk_mutex);
++
++ if (pxp->clk_stat == CLK_STAT_ON) {
++ mutex_unlock(&pxp->clk_mutex);
++ return;
++ }
++
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ pm_runtime_get_sync(pxp->dev);
++
++ if (pxp->clk_disp_axi)
++ clk_prepare_enable(pxp->clk_disp_axi);
++ clk_prepare_enable(pxp->clk);
++ pxp->clk_stat = CLK_STAT_ON;
++
++ mutex_unlock(&pxp->clk_mutex);
++}
++
++static void pxp_clk_disable(struct pxps *pxp)
++{
++ unsigned long flags;
++
++ mutex_lock(&pxp->clk_mutex);
++
++ if (pxp->clk_stat == CLK_STAT_OFF) {
++ mutex_unlock(&pxp->clk_mutex);
++ return;
++ }
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ if ((pxp->pxp_ongoing == 0) && list_empty(&head)) {
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ clk_disable_unprepare(pxp->clk);
++ if (pxp->clk_disp_axi)
++ clk_disable_unprepare(pxp->clk_disp_axi);
++ pxp->clk_stat = CLK_STAT_OFF;
++ } else
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ pm_runtime_put_sync_suspend(pxp->dev);
++
++ mutex_unlock(&pxp->clk_mutex);
++
++ release_bus_freq(BUS_FREQ_HIGH);
++}
++
++static inline void clkoff_callback(struct work_struct *w)
++{
++ struct pxps *pxp = container_of(w, struct pxps, work);
++
++ pxp_clk_disable(pxp);
++}
++
++static void pxp_clkoff_timer(unsigned long arg)
++{
++ struct pxps *pxp = (struct pxps *)arg;
++
++ if ((pxp->pxp_ongoing == 0) && list_empty(&head))
++ schedule_work(&pxp->work);
++ else
++ mod_timer(&pxp->clk_timer,
++ jiffies + msecs_to_jiffies(timeout_in_ms));
++}
++
++static struct pxp_tx_desc *pxpdma_first_queued(struct pxp_channel *pxp_chan)
++{
++ return list_entry(pxp_chan->queue.next, struct pxp_tx_desc, list);
++}
++
++/* called with pxp_chan->lock held */
++static void __pxpdma_dostart(struct pxp_channel *pxp_chan)
++{
++ struct pxp_dma *pxp_dma = to_pxp_dma(pxp_chan->dma_chan.device);
++ struct pxps *pxp = to_pxp(pxp_dma);
++ struct pxp_tx_desc *desc;
++ struct pxp_tx_desc *child;
++ int i = 0;
++
++ memset(&pxp->pxp_conf_state.s0_param, 0, sizeof(struct pxp_layer_param));
++ memset(&pxp->pxp_conf_state.out_param, 0, sizeof(struct pxp_layer_param));
++ memset(pxp->pxp_conf_state.ol_param, 0, sizeof(struct pxp_layer_param) * 8);
++ memset(&pxp->pxp_conf_state.proc_data, 0, sizeof(struct pxp_proc_data));
++ /* S0 */
++ desc = list_first_entry(&head, struct pxp_tx_desc, list);
++ memcpy(&pxp->pxp_conf_state.s0_param,
++ &desc->layer_param.s0_param, sizeof(struct pxp_layer_param));
++ memcpy(&pxp->pxp_conf_state.proc_data,
++ &desc->proc_data, sizeof(struct pxp_proc_data));
++
++ /* Save PxP configuration */
++ list_for_each_entry(child, &desc->tx_list, list) {
++ if (i == 0) { /* Output */
++ memcpy(&pxp->pxp_conf_state.out_param,
++ &child->layer_param.out_param,
++ sizeof(struct pxp_layer_param));
++ } else { /* Overlay */
++ memcpy(&pxp->pxp_conf_state.ol_param[i - 1],
++ &child->layer_param.ol_param,
++ sizeof(struct pxp_layer_param));
++ }
++
++ i++;
++ }
++ pr_debug("%s:%d S0 w/h %d/%d paddr %08x\n", __func__, __LINE__,
++ pxp->pxp_conf_state.s0_param.width,
++ pxp->pxp_conf_state.s0_param.height,
++ pxp->pxp_conf_state.s0_param.paddr);
++ pr_debug("%s:%d OUT w/h %d/%d paddr %08x\n", __func__, __LINE__,
++ pxp->pxp_conf_state.out_param.width,
++ pxp->pxp_conf_state.out_param.height,
++ pxp->pxp_conf_state.out_param.paddr);
++}
++
++static void pxpdma_dostart_work(struct pxps *pxp)
++{
++ struct pxp_channel *pxp_chan = NULL;
++ unsigned long flags;
++ struct pxp_tx_desc *desc = NULL;
++
++ spin_lock_irqsave(&pxp->lock, flags);
++
++ desc = list_entry(head.next, struct pxp_tx_desc, list);
++ pxp_chan = to_pxp_channel(desc->txd.chan);
++
++ __pxpdma_dostart(pxp_chan);
++
++ /* Configure PxP */
++ pxp_config(pxp, pxp_chan);
++
++ pxp_start(pxp);
++
++ spin_unlock_irqrestore(&pxp->lock, flags);
++}
++
++static void pxpdma_dequeue(struct pxp_channel *pxp_chan, struct pxps *pxp)
++{
++ unsigned long flags;
++ struct pxp_tx_desc *desc = NULL;
++
++ do {
++ desc = pxpdma_first_queued(pxp_chan);
++ spin_lock_irqsave(&pxp->lock, flags);
++ list_move_tail(&desc->list, &head);
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ } while (!list_empty(&pxp_chan->queue));
++}
++
++static dma_cookie_t pxp_tx_submit(struct dma_async_tx_descriptor *tx)
++{
++ struct pxp_tx_desc *desc = to_tx_desc(tx);
++ struct pxp_channel *pxp_chan = to_pxp_channel(tx->chan);
++ dma_cookie_t cookie;
++
++ dev_dbg(&pxp_chan->dma_chan.dev->device, "received TX\n");
++
++ /* pxp_chan->lock can be taken under ichan->lock, but not v.v. */
++ spin_lock(&pxp_chan->lock);
++
++ cookie = pxp_chan->dma_chan.cookie;
++
++ if (++cookie < 0)
++ cookie = 1;
++
++ /* from dmaengine.h: "last cookie value returned to client" */
++ pxp_chan->dma_chan.cookie = cookie;
++ tx->cookie = cookie;
++
++ /* Here we add the tx descriptor to our PxP task queue. */
++ list_add_tail(&desc->list, &pxp_chan->queue);
++
++ spin_unlock(&pxp_chan->lock);
++
++ dev_dbg(&pxp_chan->dma_chan.dev->device, "done TX\n");
++
++ return cookie;
++}
++
++/**
++ * pxp_init_channel() - initialize a PXP channel.
++ * @pxp_dma: PXP DMA context.
++ * @pchan: pointer to the channel object.
++ * @return 0 on success or negative error code on failure.
++ */
++static int pxp_init_channel(struct pxp_dma *pxp_dma,
++ struct pxp_channel *pxp_chan)
++{
++ int ret = 0;
++
++ /*
++ * We are using _virtual_ channel here.
++ * Each channel contains all parameters of corresponding layers
++ * for one transaction; each layer is represented as one descriptor
++ * (i.e., pxp_tx_desc) here.
++ */
++
++ INIT_LIST_HEAD(&pxp_chan->queue);
++
++ return ret;
++}
++
++static irqreturn_t pxp_irq(int irq, void *dev_id)
++{
++ struct pxps *pxp = dev_id;
++ struct pxp_channel *pxp_chan;
++ struct pxp_tx_desc *desc;
++ struct pxp_tx_desc *child, *_child;
++ dma_async_tx_callback callback;
++ void *callback_param;
++ unsigned long flags;
++ u32 hist_status;
++
++ dump_pxp_reg(pxp);
++
++ hist_status =
++ __raw_readl(pxp->base + HW_PXP_HIST_CTRL) & BM_PXP_HIST_CTRL_STATUS;
++
++ __raw_writel(BM_PXP_STAT_IRQ, pxp->base + HW_PXP_STAT_CLR);
++
++ /* set the SFTRST bit to be 1 to reset
++ * the PXP block to its default state.
++ */
++ pxp_soft_reset(pxp);
++
++ spin_lock_irqsave(&pxp->lock, flags);
++
++ if (list_empty(&head)) {
++ pxp->pxp_ongoing = 0;
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ return IRQ_NONE;
++ }
++
++ /* Get descriptor and call callback */
++ desc = list_entry(head.next, struct pxp_tx_desc, list);
++ pxp_chan = to_pxp_channel(desc->txd.chan);
++
++ pxp_chan->completed = desc->txd.cookie;
++
++ callback = desc->txd.callback;
++ callback_param = desc->txd.callback_param;
++
++ /* Send histogram status back to caller */
++ desc->hist_status = hist_status;
++
++ if ((desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
++ callback(callback_param);
++
++ pxp_chan->status = PXP_CHANNEL_INITIALIZED;
++
++ list_for_each_entry_safe(child, _child, &desc->tx_list, list) {
++ list_del_init(&child->list);
++ kmem_cache_free(tx_desc_cache, (void *)child);
++ }
++ list_del_init(&desc->list);
++ kmem_cache_free(tx_desc_cache, (void *)desc);
++
++ complete(&pxp->complete);
++ pxp->pxp_ongoing = 0;
++ mod_timer(&pxp->clk_timer, jiffies + msecs_to_jiffies(timeout_in_ms));
++
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ return IRQ_HANDLED;
++}
++
++/* allocate/free dma tx descriptor dynamically*/
++static struct pxp_tx_desc *pxpdma_desc_alloc(struct pxp_channel *pxp_chan)
++{
++ struct pxp_tx_desc *desc = NULL;
++ struct dma_async_tx_descriptor *txd = NULL;
++
++ desc = kmem_cache_alloc(tx_desc_cache, GFP_KERNEL | __GFP_ZERO);
++ if (desc == NULL)
++ return NULL;
++
++ INIT_LIST_HEAD(&desc->list);
++ INIT_LIST_HEAD(&desc->tx_list);
++ txd = &desc->txd;
++ dma_async_tx_descriptor_init(txd, &pxp_chan->dma_chan);
++ txd->tx_submit = pxp_tx_submit;
++
++ return desc;
++}
++
++/* Allocate and initialise a transfer descriptor. */
++static struct dma_async_tx_descriptor *pxp_prep_slave_sg(struct dma_chan *chan,
++ struct scatterlist
++ *sgl,
++ unsigned int sg_len,
++ enum
++ dma_transfer_direction
++ direction,
++ unsigned long tx_flags,
++ void *context)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
++ struct pxps *pxp = to_pxp(pxp_dma);
++ struct pxp_tx_desc *desc = NULL;
++ struct pxp_tx_desc *first = NULL, *prev = NULL;
++ struct scatterlist *sg;
++ dma_addr_t phys_addr;
++ int i;
++
++ if (direction != DMA_DEV_TO_MEM && direction != DMA_MEM_TO_DEV) {
++ dev_err(chan->device->dev, "Invalid DMA direction %d!\n",
++ direction);
++ return NULL;
++ }
++
++ if (unlikely(sg_len < 2))
++ return NULL;
++
++ for_each_sg(sgl, sg, sg_len, i) {
++ desc = pxpdma_desc_alloc(pxp_chan);
++ if (!desc) {
++ dev_err(chan->device->dev, "no enough memory to allocate tx descriptor\n");
++ return NULL;
++ }
++
++ phys_addr = sg_dma_address(sg);
++
++ if (!first) {
++ first = desc;
++
++ desc->layer_param.s0_param.paddr = phys_addr;
++ } else {
++ list_add_tail(&desc->list, &first->tx_list);
++ prev->next = desc;
++ desc->next = NULL;
++
++ if (i == 1)
++ desc->layer_param.out_param.paddr = phys_addr;
++ else
++ desc->layer_param.ol_param.paddr = phys_addr;
++ }
++
++ prev = desc;
++ }
++
++ pxp->pxp_conf_state.layer_nr = sg_len;
++ first->txd.flags = tx_flags;
++ first->len = sg_len;
++ pr_debug("%s:%d first %p, first->len %d, flags %08x\n",
++ __func__, __LINE__, first, first->len, first->txd.flags);
++
++ return &first->txd;
++}
++
++static void pxp_issue_pending(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
++ struct pxps *pxp = to_pxp(pxp_dma);
++
++ spin_lock(&pxp_chan->lock);
++
++ if (list_empty(&pxp_chan->queue)) {
++ spin_unlock(&pxp_chan->lock);
++ return;
++ }
++
++ pxpdma_dequeue(pxp_chan, pxp);
++ pxp_chan->status = PXP_CHANNEL_READY;
++
++ spin_unlock(&pxp_chan->lock);
++
++ pxp_clk_enable(pxp);
++ wake_up_interruptible(&pxp->thread_waitq);
++}
++
++static void __pxp_terminate_all(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++
++ pxp_chan->status = PXP_CHANNEL_INITIALIZED;
++}
++
++static int pxp_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
++ unsigned long arg)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++
++ /* Only supports DMA_TERMINATE_ALL */
++ if (cmd != DMA_TERMINATE_ALL)
++ return -ENXIO;
++
++ spin_lock(&pxp_chan->lock);
++ __pxp_terminate_all(chan);
++ spin_unlock(&pxp_chan->lock);
++
++ return 0;
++}
++
++static int pxp_alloc_chan_resources(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxp_dma *pxp_dma = to_pxp_dma(chan->device);
++ int ret;
++
++ /* dmaengine.c now guarantees to only offer free channels */
++ BUG_ON(chan->client_count > 1);
++ WARN_ON(pxp_chan->status != PXP_CHANNEL_FREE);
++
++ chan->cookie = 1;
++ pxp_chan->completed = -ENXIO;
++
++ pr_debug("%s dma_chan.chan_id %d\n", __func__, chan->chan_id);
++ ret = pxp_init_channel(pxp_dma, pxp_chan);
++ if (ret < 0)
++ goto err_chan;
++
++ pxp_chan->status = PXP_CHANNEL_INITIALIZED;
++
++ dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
++ chan->chan_id, pxp_chan->eof_irq);
++
++ return ret;
++
++err_chan:
++ return ret;
++}
++
++static void pxp_free_chan_resources(struct dma_chan *chan)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++
++ spin_lock(&pxp_chan->lock);
++
++ __pxp_terminate_all(chan);
++
++ pxp_chan->status = PXP_CHANNEL_FREE;
++
++ spin_unlock(&pxp_chan->lock);
++}
++
++static enum dma_status pxp_tx_status(struct dma_chan *chan,
++ dma_cookie_t cookie,
++ struct dma_tx_state *txstate)
++{
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++
++ if (cookie != chan->cookie)
++ return DMA_ERROR;
++
++ if (txstate) {
++ txstate->last = pxp_chan->completed;
++ txstate->used = chan->cookie;
++ txstate->residue = 0;
++ }
++ return DMA_COMPLETE;
++}
++
++static int pxp_dma_init(struct pxps *pxp)
++{
++ struct pxp_dma *pxp_dma = &pxp->pxp_dma;
++ struct dma_device *dma = &pxp_dma->dma;
++ int i;
++
++ dma_cap_set(DMA_SLAVE, dma->cap_mask);
++ dma_cap_set(DMA_PRIVATE, dma->cap_mask);
++
++ /* Compulsory common fields */
++ dma->dev = pxp->dev;
++ dma->device_alloc_chan_resources = pxp_alloc_chan_resources;
++ dma->device_free_chan_resources = pxp_free_chan_resources;
++ dma->device_tx_status = pxp_tx_status;
++ dma->device_issue_pending = pxp_issue_pending;
++
++ /* Compulsory for DMA_SLAVE fields */
++ dma->device_prep_slave_sg = pxp_prep_slave_sg;
++ dma->device_control = pxp_control;
++
++ /* Initialize PxP Channels */
++ INIT_LIST_HEAD(&dma->channels);
++ for (i = 0; i < NR_PXP_VIRT_CHANNEL; i++) {
++ struct pxp_channel *pxp_chan = pxp->channel + i;
++ struct dma_chan *dma_chan = &pxp_chan->dma_chan;
++
++ spin_lock_init(&pxp_chan->lock);
++
++ /* Only one EOF IRQ for PxP, shared by all channels */
++ pxp_chan->eof_irq = pxp->irq;
++ pxp_chan->status = PXP_CHANNEL_FREE;
++ pxp_chan->completed = -ENXIO;
++ snprintf(pxp_chan->eof_name, sizeof(pxp_chan->eof_name),
++ "PXP EOF %d", i);
++
++ dma_chan->device = &pxp_dma->dma;
++ dma_chan->cookie = 1;
++ dma_chan->chan_id = i;
++ list_add_tail(&dma_chan->device_node, &dma->channels);
++ }
++
++ return dma_async_device_register(&pxp_dma->dma);
++}
++
++static ssize_t clk_off_timeout_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "%d\n", timeout_in_ms);
++}
++
++static ssize_t clk_off_timeout_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int val;
++ if (sscanf(buf, "%d", &val) > 0) {
++ timeout_in_ms = val;
++ return count;
++ }
++ return -EINVAL;
++}
++
++static DEVICE_ATTR(clk_off_timeout, 0644, clk_off_timeout_show,
++ clk_off_timeout_store);
++
++static ssize_t block_size_show(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ return sprintf(buf, "%d\n", block_size);
++}
++
++static ssize_t block_size_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ char **last = NULL;
++
++ block_size = simple_strtoul(buf, last, 0);
++ if (block_size > 1)
++ block_size = 1;
++
++ return count;
++}
++static DEVICE_ATTR(block_size, S_IWUSR | S_IRUGO,
++ block_size_show, block_size_store);
++
++static const struct of_device_id imx_pxpdma_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-pxp-dma", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_pxpdma_dt_ids);
++
++static int has_pending_task(struct pxps *pxp, struct pxp_channel *task)
++{
++ int found;
++ unsigned long flags;
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ found = !list_empty(&head);
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ return found;
++}
++
++static int pxp_dispatch_thread(void *argv)
++{
++ struct pxps *pxp = (struct pxps *)argv;
++ struct pxp_channel *pending = NULL;
++ unsigned long flags;
++
++ set_freezable();
++
++ while (!kthread_should_stop()) {
++ int ret;
++ ret = wait_event_freezable(pxp->thread_waitq,
++ has_pending_task(pxp, pending) ||
++ kthread_should_stop());
++ if (ret < 0)
++ continue;
++
++ if (kthread_should_stop())
++ break;
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ pxp->pxp_ongoing = 1;
++ spin_unlock_irqrestore(&pxp->lock, flags);
++ init_completion(&pxp->complete);
++ pxpdma_dostart_work(pxp);
++ ret = wait_for_completion_timeout(&pxp->complete, 2 * HZ);
++ if (ret == 0) {
++ printk(KERN_EMERG "%s: task is timeout\n\n", __func__);
++ break;
++ }
++ }
++
++ return 0;
++}
++
++static int pxp_probe(struct platform_device *pdev)
++{
++ struct pxps *pxp;
++ struct resource *res;
++ int irq;
++ int err = 0;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ irq = platform_get_irq(pdev, 0);
++ if (!res || irq < 0) {
++ err = -ENODEV;
++ goto exit;
++ }
++
++ pxp = devm_kzalloc(&pdev->dev, sizeof(*pxp), GFP_KERNEL);
++ if (!pxp) {
++ dev_err(&pdev->dev, "failed to allocate control object\n");
++ err = -ENOMEM;
++ goto exit;
++ }
++
++ pxp->dev = &pdev->dev;
++
++ platform_set_drvdata(pdev, pxp);
++ pxp->irq = irq;
++
++ pxp->pxp_ongoing = 0;
++ pxp->lut_state = 0;
++
++ spin_lock_init(&pxp->lock);
++ mutex_init(&pxp->clk_mutex);
++
++ pxp->base = devm_request_and_ioremap(&pdev->dev, res);
++ if (pxp->base == NULL) {
++ dev_err(&pdev->dev, "Couldn't ioremap regs\n");
++ err = -ENODEV;
++ goto exit;
++ }
++
++ pxp->pdev = pdev;
++
++ pxp->clk_disp_axi = devm_clk_get(&pdev->dev, "disp-axi");
++ if (IS_ERR(pxp->clk_disp_axi))
++ pxp->clk_disp_axi = NULL;
++ pxp->clk = devm_clk_get(&pdev->dev, "pxp-axi");
++
++ err = devm_request_irq(&pdev->dev, pxp->irq, pxp_irq, 0,
++ "pxp-dmaengine", pxp);
++ if (err)
++ goto exit;
++ /* Initialize DMA engine */
++ err = pxp_dma_init(pxp);
++ if (err < 0)
++ goto exit;
++
++ if (device_create_file(&pdev->dev, &dev_attr_clk_off_timeout)) {
++ dev_err(&pdev->dev,
++ "Unable to create file from clk_off_timeout\n");
++ goto exit;
++ }
++
++ device_create_file(&pdev->dev, &dev_attr_block_size);
++ pxp_clk_enable(pxp);
++ dump_pxp_reg(pxp);
++ pxp_clk_disable(pxp);
++
++ INIT_WORK(&pxp->work, clkoff_callback);
++ init_timer(&pxp->clk_timer);
++ pxp->clk_timer.function = pxp_clkoff_timer;
++ pxp->clk_timer.data = (unsigned long)pxp;
++
++ init_waitqueue_head(&pxp->thread_waitq);
++ /* allocate a kernel thread to dispatch pxp conf */
++ pxp->dispatch = kthread_run(pxp_dispatch_thread, pxp, "pxp_dispatch");
++ if (IS_ERR(pxp->dispatch)) {
++ err = PTR_ERR(pxp->dispatch);
++ goto exit;
++ }
++ tx_desc_cache = kmem_cache_create("tx_desc", sizeof(struct pxp_tx_desc),
++ 0, SLAB_HWCACHE_ALIGN, NULL);
++ if (!tx_desc_cache) {
++ err = -ENOMEM;
++ goto exit;
++ }
++
++ register_pxp_device();
++
++ pm_runtime_enable(pxp->dev);
++
++exit:
++ if (err)
++ dev_err(&pdev->dev, "Exiting (unsuccessfully) pxp_probe()\n");
++ return err;
++}
++
++static int pxp_remove(struct platform_device *pdev)
++{
++ struct pxps *pxp = platform_get_drvdata(pdev);
++
++ unregister_pxp_device();
++ kmem_cache_destroy(tx_desc_cache);
++ kthread_stop(pxp->dispatch);
++ cancel_work_sync(&pxp->work);
++ del_timer_sync(&pxp->clk_timer);
++ clk_disable_unprepare(pxp->clk);
++ if (pxp->clk_disp_axi)
++ clk_disable_unprepare(pxp->clk_disp_axi);
++ device_remove_file(&pdev->dev, &dev_attr_clk_off_timeout);
++ device_remove_file(&pdev->dev, &dev_attr_block_size);
++ dma_async_device_unregister(&(pxp->pxp_dma.dma));
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int pxp_suspend(struct device *dev)
++{
++ struct pxps *pxp = dev_get_drvdata(dev);
++
++ pxp_clk_enable(pxp);
++ while (__raw_readl(pxp->base + HW_PXP_CTRL) & BM_PXP_CTRL_ENABLE)
++ ;
++
++ __raw_writel(BM_PXP_CTRL_SFTRST, pxp->base + HW_PXP_CTRL);
++ pxp_clk_disable(pxp);
++
++ return 0;
++}
++
++static int pxp_resume(struct device *dev)
++{
++ struct pxps *pxp = dev_get_drvdata(dev);
++
++ pxp_clk_enable(pxp);
++ /* Pull PxP out of reset */
++ __raw_writel(0, pxp->base + HW_PXP_CTRL);
++ pxp_clk_disable(pxp);
++
++ return 0;
++}
++#else
++#define pxp_suspend NULL
++#define pxp_resume NULL
++#endif
++
++#ifdef CONFIG_PM_RUNTIME
++static int pxp_runtime_suspend(struct device *dev)
++{
++ dev_dbg(dev, "pxp busfreq high release.\n");
++ return 0;
++}
++
++static int pxp_runtime_resume(struct device *dev)
++{
++ dev_dbg(dev, "pxp busfreq high request.\n");
++ return 0;
++}
++#else
++#define pxp_runtime_suspend NULL
++#define pxp_runtime_resume NULL
++#endif
++
++static const struct dev_pm_ops pxp_pm_ops = {
++ SET_RUNTIME_PM_OPS(pxp_runtime_suspend, pxp_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(pxp_suspend, pxp_resume)
++};
++
++static struct platform_driver pxp_driver = {
++ .driver = {
++ .name = "imx-pxp",
++ .of_match_table = of_match_ptr(imx_pxpdma_dt_ids),
++ .pm = &pxp_pm_ops,
++ },
++ .probe = pxp_probe,
++ .remove = pxp_remove,
++};
++
++module_platform_driver(pxp_driver);
++
++
++MODULE_DESCRIPTION("i.MX PxP driver");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/dma/pxp/regs-pxp_v2.h linux-3.14.72/drivers/dma/pxp/regs-pxp_v2.h
+--- linux-3.14.72.orig/drivers/dma/pxp/regs-pxp_v2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/dma/pxp/regs-pxp_v2.h 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,1152 @@
++/*
++ * Freescale PXP Register Definitions
++ *
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * This file is created by xml file. Don't Edit it.
++ *
++ * Xml Revision: 1.29
++ * Template revision: 1.3
++ */
++
++#ifndef __ARCH_ARM___PXP_H
++#define __ARCH_ARM___PXP_H
++
++#define HW_PXP_CTRL (0x00000000)
++#define HW_PXP_CTRL_SET (0x00000004)
++#define HW_PXP_CTRL_CLR (0x00000008)
++#define HW_PXP_CTRL_TOG (0x0000000c)
++
++#define BM_PXP_CTRL_SFTRST 0x80000000
++#define BM_PXP_CTRL_CLKGATE 0x40000000
++#define BM_PXP_CTRL_RSVD4 0x20000000
++#define BM_PXP_CTRL_EN_REPEAT 0x10000000
++#define BP_PXP_CTRL_RSVD3 26
++#define BM_PXP_CTRL_RSVD3 0x0C000000
++#define BF_PXP_CTRL_RSVD3(v) \
++ (((v) << 26) & BM_PXP_CTRL_RSVD3)
++#define BP_PXP_CTRL_INTERLACED_INPUT 24
++#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000
++#define BF_PXP_CTRL_INTERLACED_INPUT(v) \
++ (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT)
++#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0
++#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2
++#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3
++#define BM_PXP_CTRL_BLOCK_SIZE 0x00800000
++#define BV_PXP_CTRL_BLOCK_SIZE__8X8 0x0
++#define BV_PXP_CTRL_BLOCK_SIZE__16X16 0x1
++#define BM_PXP_CTRL_ROT_POS 0x00400000
++#define BM_PXP_CTRL_IN_PLACE 0x00200000
++#define BP_PXP_CTRL_RSVD1 12
++#define BM_PXP_CTRL_RSVD1 0x001FF000
++#define BF_PXP_CTRL_RSVD1(v) \
++ (((v) << 12) & BM_PXP_CTRL_RSVD1)
++#define BM_PXP_CTRL_VFLIP 0x00000800
++#define BM_PXP_CTRL_HFLIP 0x00000400
++#define BP_PXP_CTRL_ROTATE 8
++#define BM_PXP_CTRL_ROTATE 0x00000300
++#define BF_PXP_CTRL_ROTATE(v) \
++ (((v) << 8) & BM_PXP_CTRL_ROTATE)
++#define BV_PXP_CTRL_ROTATE__ROT_0 0x0
++#define BV_PXP_CTRL_ROTATE__ROT_90 0x1
++#define BV_PXP_CTRL_ROTATE__ROT_180 0x2
++#define BV_PXP_CTRL_ROTATE__ROT_270 0x3
++#define BP_PXP_CTRL_RSVD0 5
++#define BM_PXP_CTRL_RSVD0 0x000000E0
++#define BF_PXP_CTRL_RSVD0(v) \
++ (((v) << 5) & BM_PXP_CTRL_RSVD0)
++#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000010
++#define BM_PXP_CTRL_LUT_DMA_IRQ_ENABLE 0x00000008
++#define BM_PXP_CTRL_NEXT_IRQ_ENABLE 0x00000004
++#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
++#define BM_PXP_CTRL_ENABLE 0x00000001
++
++#define HW_PXP_STAT (0x00000010)
++#define HW_PXP_STAT_SET (0x00000014)
++#define HW_PXP_STAT_CLR (0x00000018)
++#define HW_PXP_STAT_TOG (0x0000001c)
++
++#define BP_PXP_STAT_BLOCKX 24
++#define BM_PXP_STAT_BLOCKX 0xFF000000
++#define BF_PXP_STAT_BLOCKX(v) \
++ (((v) << 24) & BM_PXP_STAT_BLOCKX)
++#define BP_PXP_STAT_BLOCKY 16
++#define BM_PXP_STAT_BLOCKY 0x00FF0000
++#define BF_PXP_STAT_BLOCKY(v) \
++ (((v) << 16) & BM_PXP_STAT_BLOCKY)
++#define BP_PXP_STAT_RSVD2 9
++#define BM_PXP_STAT_RSVD2 0x0000FE00
++#define BF_PXP_STAT_RSVD2(v) \
++ (((v) << 9) & BM_PXP_STAT_RSVD2)
++#define BM_PXP_STAT_LUT_DMA_LOAD_DONE_IRQ 0x00000100
++#define BP_PXP_STAT_AXI_ERROR_ID 4
++#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0
++#define BF_PXP_STAT_AXI_ERROR_ID(v) \
++ (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID)
++#define BM_PXP_STAT_NEXT_IRQ 0x00000008
++#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004
++#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002
++#define BM_PXP_STAT_IRQ 0x00000001
++
++#define HW_PXP_OUT_CTRL (0x00000020)
++#define HW_PXP_OUT_CTRL_SET (0x00000024)
++#define HW_PXP_OUT_CTRL_CLR (0x00000028)
++#define HW_PXP_OUT_CTRL_TOG (0x0000002c)
++
++#define BP_PXP_OUT_CTRL_ALPHA 24
++#define BM_PXP_OUT_CTRL_ALPHA 0xFF000000
++#define BF_PXP_OUT_CTRL_ALPHA(v) \
++ (((v) << 24) & BM_PXP_OUT_CTRL_ALPHA)
++#define BM_PXP_OUT_CTRL_ALPHA_OUTPUT 0x00800000
++#define BP_PXP_OUT_CTRL_RSVD1 10
++#define BM_PXP_OUT_CTRL_RSVD1 0x007FFC00
++#define BF_PXP_OUT_CTRL_RSVD1(v) \
++ (((v) << 10) & BM_PXP_OUT_CTRL_RSVD1)
++#define BP_PXP_OUT_CTRL_INTERLACED_OUTPUT 8
++#define BM_PXP_OUT_CTRL_INTERLACED_OUTPUT 0x00000300
++#define BF_PXP_OUT_CTRL_INTERLACED_OUTPUT(v) \
++ (((v) << 8) & BM_PXP_OUT_CTRL_INTERLACED_OUTPUT)
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD0 0x1
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__FIELD1 0x2
++#define BV_PXP_OUT_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3
++#define BP_PXP_OUT_CTRL_RSVD0 5
++#define BM_PXP_OUT_CTRL_RSVD0 0x000000E0
++#define BF_PXP_OUT_CTRL_RSVD0(v) \
++ (((v) << 5) & BM_PXP_OUT_CTRL_RSVD0)
++#define BP_PXP_OUT_CTRL_FORMAT 0
++#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F
++#define BF_PXP_OUT_CTRL_FORMAT(v) \
++ (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT)
++#define BV_PXP_OUT_CTRL_FORMAT__ARGB8888 0x0
++#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4
++#define BV_PXP_OUT_CTRL_FORMAT__RGB888P 0x5
++#define BV_PXP_OUT_CTRL_FORMAT__ARGB1555 0x8
++#define BV_PXP_OUT_CTRL_FORMAT__ARGB4444 0x9
++#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC
++#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD
++#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE
++#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10
++#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12
++#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13
++#define BV_PXP_OUT_CTRL_FORMAT__Y8 0x14
++#define BV_PXP_OUT_CTRL_FORMAT__Y4 0x15
++#define BV_PXP_OUT_CTRL_FORMAT__YUV2P422 0x18
++#define BV_PXP_OUT_CTRL_FORMAT__YUV2P420 0x19
++#define BV_PXP_OUT_CTRL_FORMAT__YVU2P422 0x1A
++#define BV_PXP_OUT_CTRL_FORMAT__YVU2P420 0x1B
++
++#define HW_PXP_OUT_BUF (0x00000030)
++
++#define BP_PXP_OUT_BUF_ADDR 0
++#define BM_PXP_OUT_BUF_ADDR 0xFFFFFFFF
++#define BF_PXP_OUT_BUF_ADDR(v) (v)
++
++#define HW_PXP_OUT_BUF2 (0x00000040)
++
++#define BP_PXP_OUT_BUF2_ADDR 0
++#define BM_PXP_OUT_BUF2_ADDR 0xFFFFFFFF
++#define BF_PXP_OUT_BUF2_ADDR(v) (v)
++
++#define HW_PXP_OUT_PITCH (0x00000050)
++
++#define BP_PXP_OUT_PITCH_RSVD 16
++#define BM_PXP_OUT_PITCH_RSVD 0xFFFF0000
++#define BF_PXP_OUT_PITCH_RSVD(v) \
++ (((v) << 16) & BM_PXP_OUT_PITCH_RSVD)
++#define BP_PXP_OUT_PITCH_PITCH 0
++#define BM_PXP_OUT_PITCH_PITCH 0x0000FFFF
++#define BF_PXP_OUT_PITCH_PITCH(v) \
++ (((v) << 0) & BM_PXP_OUT_PITCH_PITCH)
++
++#define HW_PXP_OUT_LRC (0x00000060)
++
++#define BP_PXP_OUT_LRC_RSVD1 30
++#define BM_PXP_OUT_LRC_RSVD1 0xC0000000
++#define BF_PXP_OUT_LRC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_LRC_RSVD1)
++#define BP_PXP_OUT_LRC_X 16
++#define BM_PXP_OUT_LRC_X 0x3FFF0000
++#define BF_PXP_OUT_LRC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_LRC_X)
++#define BP_PXP_OUT_LRC_RSVD0 14
++#define BM_PXP_OUT_LRC_RSVD0 0x0000C000
++#define BF_PXP_OUT_LRC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_LRC_RSVD0)
++#define BP_PXP_OUT_LRC_Y 0
++#define BM_PXP_OUT_LRC_Y 0x00003FFF
++#define BF_PXP_OUT_LRC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_LRC_Y)
++
++#define HW_PXP_OUT_PS_ULC (0x00000070)
++
++#define BP_PXP_OUT_PS_ULC_RSVD1 30
++#define BM_PXP_OUT_PS_ULC_RSVD1 0xC0000000
++#define BF_PXP_OUT_PS_ULC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_PS_ULC_RSVD1)
++#define BP_PXP_OUT_PS_ULC_X 16
++#define BM_PXP_OUT_PS_ULC_X 0x3FFF0000
++#define BF_PXP_OUT_PS_ULC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_PS_ULC_X)
++#define BP_PXP_OUT_PS_ULC_RSVD0 14
++#define BM_PXP_OUT_PS_ULC_RSVD0 0x0000C000
++#define BF_PXP_OUT_PS_ULC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_PS_ULC_RSVD0)
++#define BP_PXP_OUT_PS_ULC_Y 0
++#define BM_PXP_OUT_PS_ULC_Y 0x00003FFF
++#define BF_PXP_OUT_PS_ULC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_PS_ULC_Y)
++
++#define HW_PXP_OUT_PS_LRC (0x00000080)
++
++#define BP_PXP_OUT_PS_LRC_RSVD1 30
++#define BM_PXP_OUT_PS_LRC_RSVD1 0xC0000000
++#define BF_PXP_OUT_PS_LRC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_PS_LRC_RSVD1)
++#define BP_PXP_OUT_PS_LRC_X 16
++#define BM_PXP_OUT_PS_LRC_X 0x3FFF0000
++#define BF_PXP_OUT_PS_LRC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_PS_LRC_X)
++#define BP_PXP_OUT_PS_LRC_RSVD0 14
++#define BM_PXP_OUT_PS_LRC_RSVD0 0x0000C000
++#define BF_PXP_OUT_PS_LRC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_PS_LRC_RSVD0)
++#define BP_PXP_OUT_PS_LRC_Y 0
++#define BM_PXP_OUT_PS_LRC_Y 0x00003FFF
++#define BF_PXP_OUT_PS_LRC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_PS_LRC_Y)
++
++#define HW_PXP_OUT_AS_ULC (0x00000090)
++
++#define BP_PXP_OUT_AS_ULC_RSVD1 30
++#define BM_PXP_OUT_AS_ULC_RSVD1 0xC0000000
++#define BF_PXP_OUT_AS_ULC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_AS_ULC_RSVD1)
++#define BP_PXP_OUT_AS_ULC_X 16
++#define BM_PXP_OUT_AS_ULC_X 0x3FFF0000
++#define BF_PXP_OUT_AS_ULC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_AS_ULC_X)
++#define BP_PXP_OUT_AS_ULC_RSVD0 14
++#define BM_PXP_OUT_AS_ULC_RSVD0 0x0000C000
++#define BF_PXP_OUT_AS_ULC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_AS_ULC_RSVD0)
++#define BP_PXP_OUT_AS_ULC_Y 0
++#define BM_PXP_OUT_AS_ULC_Y 0x00003FFF
++#define BF_PXP_OUT_AS_ULC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_AS_ULC_Y)
++
++#define HW_PXP_OUT_AS_LRC (0x000000a0)
++
++#define BP_PXP_OUT_AS_LRC_RSVD1 30
++#define BM_PXP_OUT_AS_LRC_RSVD1 0xC0000000
++#define BF_PXP_OUT_AS_LRC_RSVD1(v) \
++ (((v) << 30) & BM_PXP_OUT_AS_LRC_RSVD1)
++#define BP_PXP_OUT_AS_LRC_X 16
++#define BM_PXP_OUT_AS_LRC_X 0x3FFF0000
++#define BF_PXP_OUT_AS_LRC_X(v) \
++ (((v) << 16) & BM_PXP_OUT_AS_LRC_X)
++#define BP_PXP_OUT_AS_LRC_RSVD0 14
++#define BM_PXP_OUT_AS_LRC_RSVD0 0x0000C000
++#define BF_PXP_OUT_AS_LRC_RSVD0(v) \
++ (((v) << 14) & BM_PXP_OUT_AS_LRC_RSVD0)
++#define BP_PXP_OUT_AS_LRC_Y 0
++#define BM_PXP_OUT_AS_LRC_Y 0x00003FFF
++#define BF_PXP_OUT_AS_LRC_Y(v) \
++ (((v) << 0) & BM_PXP_OUT_AS_LRC_Y)
++
++#define HW_PXP_PS_CTRL (0x000000b0)
++#define HW_PXP_PS_CTRL_SET (0x000000b4)
++#define HW_PXP_PS_CTRL_CLR (0x000000b8)
++#define HW_PXP_PS_CTRL_TOG (0x000000bc)
++
++#define BP_PXP_PS_CTRL_RSVD1 12
++#define BM_PXP_PS_CTRL_RSVD1 0xFFFFF000
++#define BF_PXP_PS_CTRL_RSVD1(v) \
++ (((v) << 12) & BM_PXP_PS_CTRL_RSVD1)
++#define BP_PXP_PS_CTRL_DECX 10
++#define BM_PXP_PS_CTRL_DECX 0x00000C00
++#define BF_PXP_PS_CTRL_DECX(v) \
++ (((v) << 10) & BM_PXP_PS_CTRL_DECX)
++#define BV_PXP_PS_CTRL_DECX__DISABLE 0x0
++#define BV_PXP_PS_CTRL_DECX__DECX2 0x1
++#define BV_PXP_PS_CTRL_DECX__DECX4 0x2
++#define BV_PXP_PS_CTRL_DECX__DECX8 0x3
++#define BP_PXP_PS_CTRL_DECY 8
++#define BM_PXP_PS_CTRL_DECY 0x00000300
++#define BF_PXP_PS_CTRL_DECY(v) \
++ (((v) << 8) & BM_PXP_PS_CTRL_DECY)
++#define BV_PXP_PS_CTRL_DECY__DISABLE 0x0
++#define BV_PXP_PS_CTRL_DECY__DECY2 0x1
++#define BV_PXP_PS_CTRL_DECY__DECY4 0x2
++#define BV_PXP_PS_CTRL_DECY__DECY8 0x3
++#define BP_PXP_PS_CTRL_SWAP 5
++#define BM_PXP_PS_CTRL_SWAP 0x000000E0
++#define BF_PXP_PS_CTRL_SWAP(v) \
++ (((v) << 5) & BM_PXP_PS_CTRL_SWAP)
++#define BP_PXP_PS_CTRL_FORMAT 0
++#define BM_PXP_PS_CTRL_FORMAT 0x0000001F
++#define BF_PXP_PS_CTRL_FORMAT(v) \
++ (((v) << 0) & BM_PXP_PS_CTRL_FORMAT)
++#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4
++#define BV_PXP_PS_CTRL_FORMAT__RGB555 0xC
++#define BV_PXP_PS_CTRL_FORMAT__RGB444 0xD
++#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE
++#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10
++#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12
++#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13
++#define BV_PXP_PS_CTRL_FORMAT__Y8 0x14
++#define BV_PXP_PS_CTRL_FORMAT__Y4 0x15
++#define BV_PXP_PS_CTRL_FORMAT__YUV2P422 0x18
++#define BV_PXP_PS_CTRL_FORMAT__YUV2P420 0x19
++#define BV_PXP_PS_CTRL_FORMAT__YVU2P422 0x1A
++#define BV_PXP_PS_CTRL_FORMAT__YVU2P420 0x1B
++#define BV_PXP_PS_CTRL_FORMAT__YUV422 0x1E
++#define BV_PXP_PS_CTRL_FORMAT__YUV420 0x1F
++
++#define HW_PXP_PS_BUF (0x000000c0)
++
++#define BP_PXP_PS_BUF_ADDR 0
++#define BM_PXP_PS_BUF_ADDR 0xFFFFFFFF
++#define BF_PXP_PS_BUF_ADDR(v) (v)
++
++#define HW_PXP_PS_UBUF (0x000000d0)
++
++#define BP_PXP_PS_UBUF_ADDR 0
++#define BM_PXP_PS_UBUF_ADDR 0xFFFFFFFF
++#define BF_PXP_PS_UBUF_ADDR(v) (v)
++
++#define HW_PXP_PS_VBUF (0x000000e0)
++
++#define BP_PXP_PS_VBUF_ADDR 0
++#define BM_PXP_PS_VBUF_ADDR 0xFFFFFFFF
++#define BF_PXP_PS_VBUF_ADDR(v) (v)
++
++#define HW_PXP_PS_PITCH (0x000000f0)
++
++#define BP_PXP_PS_PITCH_RSVD 16
++#define BM_PXP_PS_PITCH_RSVD 0xFFFF0000
++#define BF_PXP_PS_PITCH_RSVD(v) \
++ (((v) << 16) & BM_PXP_PS_PITCH_RSVD)
++#define BP_PXP_PS_PITCH_PITCH 0
++#define BM_PXP_PS_PITCH_PITCH 0x0000FFFF
++#define BF_PXP_PS_PITCH_PITCH(v) \
++ (((v) << 0) & BM_PXP_PS_PITCH_PITCH)
++
++#define HW_PXP_PS_BACKGROUND (0x00000100)
++
++#define BP_PXP_PS_BACKGROUND_RSVD 24
++#define BM_PXP_PS_BACKGROUND_RSVD 0xFF000000
++#define BF_PXP_PS_BACKGROUND_RSVD(v) \
++ (((v) << 24) & BM_PXP_PS_BACKGROUND_RSVD)
++#define BP_PXP_PS_BACKGROUND_COLOR 0
++#define BM_PXP_PS_BACKGROUND_COLOR 0x00FFFFFF
++#define BF_PXP_PS_BACKGROUND_COLOR(v) \
++ (((v) << 0) & BM_PXP_PS_BACKGROUND_COLOR)
++
++#define HW_PXP_PS_SCALE (0x00000110)
++
++#define BM_PXP_PS_SCALE_RSVD2 0x80000000
++#define BP_PXP_PS_SCALE_YSCALE 16
++#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000
++#define BF_PXP_PS_SCALE_YSCALE(v) \
++ (((v) << 16) & BM_PXP_PS_SCALE_YSCALE)
++#define BM_PXP_PS_SCALE_RSVD1 0x00008000
++#define BP_PXP_PS_SCALE_XSCALE 0
++#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF
++#define BF_PXP_PS_SCALE_XSCALE(v) \
++ (((v) << 0) & BM_PXP_PS_SCALE_XSCALE)
++
++#define HW_PXP_PS_OFFSET (0x00000120)
++
++#define BP_PXP_PS_OFFSET_RSVD2 28
++#define BM_PXP_PS_OFFSET_RSVD2 0xF0000000
++#define BF_PXP_PS_OFFSET_RSVD2(v) \
++ (((v) << 28) & BM_PXP_PS_OFFSET_RSVD2)
++#define BP_PXP_PS_OFFSET_YOFFSET 16
++#define BM_PXP_PS_OFFSET_YOFFSET 0x0FFF0000
++#define BF_PXP_PS_OFFSET_YOFFSET(v) \
++ (((v) << 16) & BM_PXP_PS_OFFSET_YOFFSET)
++#define BP_PXP_PS_OFFSET_RSVD1 12
++#define BM_PXP_PS_OFFSET_RSVD1 0x0000F000
++#define BF_PXP_PS_OFFSET_RSVD1(v) \
++ (((v) << 12) & BM_PXP_PS_OFFSET_RSVD1)
++#define BP_PXP_PS_OFFSET_XOFFSET 0
++#define BM_PXP_PS_OFFSET_XOFFSET 0x00000FFF
++#define BF_PXP_PS_OFFSET_XOFFSET(v) \
++ (((v) << 0) & BM_PXP_PS_OFFSET_XOFFSET)
++
++#define HW_PXP_PS_CLRKEYLOW (0x00000130)
++
++#define BP_PXP_PS_CLRKEYLOW_RSVD1 24
++#define BM_PXP_PS_CLRKEYLOW_RSVD1 0xFF000000
++#define BF_PXP_PS_CLRKEYLOW_RSVD1(v) \
++ (((v) << 24) & BM_PXP_PS_CLRKEYLOW_RSVD1)
++#define BP_PXP_PS_CLRKEYLOW_PIXEL 0
++#define BM_PXP_PS_CLRKEYLOW_PIXEL 0x00FFFFFF
++#define BF_PXP_PS_CLRKEYLOW_PIXEL(v) \
++ (((v) << 0) & BM_PXP_PS_CLRKEYLOW_PIXEL)
++
++#define HW_PXP_PS_CLRKEYHIGH (0x00000140)
++
++#define BP_PXP_PS_CLRKEYHIGH_RSVD1 24
++#define BM_PXP_PS_CLRKEYHIGH_RSVD1 0xFF000000
++#define BF_PXP_PS_CLRKEYHIGH_RSVD1(v) \
++ (((v) << 24) & BM_PXP_PS_CLRKEYHIGH_RSVD1)
++#define BP_PXP_PS_CLRKEYHIGH_PIXEL 0
++#define BM_PXP_PS_CLRKEYHIGH_PIXEL 0x00FFFFFF
++#define BF_PXP_PS_CLRKEYHIGH_PIXEL(v) \
++ (((v) << 0) & BM_PXP_PS_CLRKEYHIGH_PIXEL)
++
++#define HW_PXP_AS_CTRL (0x00000150)
++
++#define BP_PXP_AS_CTRL_RSVD1 21
++#define BM_PXP_AS_CTRL_RSVD1 0xFFE00000
++#define BF_PXP_AS_CTRL_RSVD1(v) \
++ (((v) << 21) & BM_PXP_AS_CTRL_RSVD1)
++#define BM_PXP_AS_CTRL_ALPHA_INVERT 0x00100000
++#define BP_PXP_AS_CTRL_ROP 16
++#define BM_PXP_AS_CTRL_ROP 0x000F0000
++#define BF_PXP_AS_CTRL_ROP(v) \
++ (((v) << 16) & BM_PXP_AS_CTRL_ROP)
++#define BV_PXP_AS_CTRL_ROP__MASKAS 0x0
++#define BV_PXP_AS_CTRL_ROP__MASKNOTAS 0x1
++#define BV_PXP_AS_CTRL_ROP__MASKASNOT 0x2
++#define BV_PXP_AS_CTRL_ROP__MERGEAS 0x3
++#define BV_PXP_AS_CTRL_ROP__MERGENOTAS 0x4
++#define BV_PXP_AS_CTRL_ROP__MERGEASNOT 0x5
++#define BV_PXP_AS_CTRL_ROP__NOTCOPYAS 0x6
++#define BV_PXP_AS_CTRL_ROP__NOT 0x7
++#define BV_PXP_AS_CTRL_ROP__NOTMASKAS 0x8
++#define BV_PXP_AS_CTRL_ROP__NOTMERGEAS 0x9
++#define BV_PXP_AS_CTRL_ROP__XORAS 0xA
++#define BV_PXP_AS_CTRL_ROP__NOTXORAS 0xB
++#define BP_PXP_AS_CTRL_ALPHA 8
++#define BM_PXP_AS_CTRL_ALPHA 0x0000FF00
++#define BF_PXP_AS_CTRL_ALPHA(v) \
++ (((v) << 8) & BM_PXP_AS_CTRL_ALPHA)
++#define BP_PXP_AS_CTRL_FORMAT 4
++#define BM_PXP_AS_CTRL_FORMAT 0x000000F0
++#define BF_PXP_AS_CTRL_FORMAT(v) \
++ (((v) << 4) & BM_PXP_AS_CTRL_FORMAT)
++#define BV_PXP_AS_CTRL_FORMAT__ARGB8888 0x0
++#define BV_PXP_AS_CTRL_FORMAT__RGB888 0x4
++#define BV_PXP_AS_CTRL_FORMAT__ARGB1555 0x8
++#define BV_PXP_AS_CTRL_FORMAT__ARGB4444 0x9
++#define BV_PXP_AS_CTRL_FORMAT__RGB555 0xC
++#define BV_PXP_AS_CTRL_FORMAT__RGB444 0xD
++#define BV_PXP_AS_CTRL_FORMAT__RGB565 0xE
++#define BM_PXP_AS_CTRL_ENABLE_COLORKEY 0x00000008
++#define BP_PXP_AS_CTRL_ALPHA_CTRL 1
++#define BM_PXP_AS_CTRL_ALPHA_CTRL 0x00000006
++#define BF_PXP_AS_CTRL_ALPHA_CTRL(v) \
++ (((v) << 1) & BM_PXP_AS_CTRL_ALPHA_CTRL)
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__Embedded 0x0
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__Override 0x1
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__Multiply 0x2
++#define BV_PXP_AS_CTRL_ALPHA_CTRL__ROPs 0x3
++#define BM_PXP_AS_CTRL_RSVD0 0x00000001
++
++#define HW_PXP_AS_BUF (0x00000160)
++
++#define BP_PXP_AS_BUF_ADDR 0
++#define BM_PXP_AS_BUF_ADDR 0xFFFFFFFF
++#define BF_PXP_AS_BUF_ADDR(v) (v)
++
++#define HW_PXP_AS_PITCH (0x00000170)
++
++#define BP_PXP_AS_PITCH_RSVD 16
++#define BM_PXP_AS_PITCH_RSVD 0xFFFF0000
++#define BF_PXP_AS_PITCH_RSVD(v) \
++ (((v) << 16) & BM_PXP_AS_PITCH_RSVD)
++#define BP_PXP_AS_PITCH_PITCH 0
++#define BM_PXP_AS_PITCH_PITCH 0x0000FFFF
++#define BF_PXP_AS_PITCH_PITCH(v) \
++ (((v) << 0) & BM_PXP_AS_PITCH_PITCH)
++
++#define HW_PXP_AS_CLRKEYLOW (0x00000180)
++
++#define BP_PXP_AS_CLRKEYLOW_RSVD1 24
++#define BM_PXP_AS_CLRKEYLOW_RSVD1 0xFF000000
++#define BF_PXP_AS_CLRKEYLOW_RSVD1(v) \
++ (((v) << 24) & BM_PXP_AS_CLRKEYLOW_RSVD1)
++#define BP_PXP_AS_CLRKEYLOW_PIXEL 0
++#define BM_PXP_AS_CLRKEYLOW_PIXEL 0x00FFFFFF
++#define BF_PXP_AS_CLRKEYLOW_PIXEL(v) \
++ (((v) << 0) & BM_PXP_AS_CLRKEYLOW_PIXEL)
++
++#define HW_PXP_AS_CLRKEYHIGH (0x00000190)
++
++#define BP_PXP_AS_CLRKEYHIGH_RSVD1 24
++#define BM_PXP_AS_CLRKEYHIGH_RSVD1 0xFF000000
++#define BF_PXP_AS_CLRKEYHIGH_RSVD1(v) \
++ (((v) << 24) & BM_PXP_AS_CLRKEYHIGH_RSVD1)
++#define BP_PXP_AS_CLRKEYHIGH_PIXEL 0
++#define BM_PXP_AS_CLRKEYHIGH_PIXEL 0x00FFFFFF
++#define BF_PXP_AS_CLRKEYHIGH_PIXEL(v) \
++ (((v) << 0) & BM_PXP_AS_CLRKEYHIGH_PIXEL)
++
++#define HW_PXP_CSC1_COEF0 (0x000001a0)
++
++#define BM_PXP_CSC1_COEF0_YCBCR_MODE 0x80000000
++#define BM_PXP_CSC1_COEF0_BYPASS 0x40000000
++#define BM_PXP_CSC1_COEF0_RSVD1 0x20000000
++#define BP_PXP_CSC1_COEF0_C0 18
++#define BM_PXP_CSC1_COEF0_C0 0x1FFC0000
++#define BF_PXP_CSC1_COEF0_C0(v) \
++ (((v) << 18) & BM_PXP_CSC1_COEF0_C0)
++#define BP_PXP_CSC1_COEF0_UV_OFFSET 9
++#define BM_PXP_CSC1_COEF0_UV_OFFSET 0x0003FE00
++#define BF_PXP_CSC1_COEF0_UV_OFFSET(v) \
++ (((v) << 9) & BM_PXP_CSC1_COEF0_UV_OFFSET)
++#define BP_PXP_CSC1_COEF0_Y_OFFSET 0
++#define BM_PXP_CSC1_COEF0_Y_OFFSET 0x000001FF
++#define BF_PXP_CSC1_COEF0_Y_OFFSET(v) \
++ (((v) << 0) & BM_PXP_CSC1_COEF0_Y_OFFSET)
++
++#define HW_PXP_CSC1_COEF1 (0x000001b0)
++
++#define BP_PXP_CSC1_COEF1_RSVD1 27
++#define BM_PXP_CSC1_COEF1_RSVD1 0xF8000000
++#define BF_PXP_CSC1_COEF1_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC1_COEF1_RSVD1)
++#define BP_PXP_CSC1_COEF1_C1 16
++#define BM_PXP_CSC1_COEF1_C1 0x07FF0000
++#define BF_PXP_CSC1_COEF1_C1(v) \
++ (((v) << 16) & BM_PXP_CSC1_COEF1_C1)
++#define BP_PXP_CSC1_COEF1_RSVD0 11
++#define BM_PXP_CSC1_COEF1_RSVD0 0x0000F800
++#define BF_PXP_CSC1_COEF1_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC1_COEF1_RSVD0)
++#define BP_PXP_CSC1_COEF1_C4 0
++#define BM_PXP_CSC1_COEF1_C4 0x000007FF
++#define BF_PXP_CSC1_COEF1_C4(v) \
++ (((v) << 0) & BM_PXP_CSC1_COEF1_C4)
++
++#define HW_PXP_CSC1_COEF2 (0x000001c0)
++
++#define BP_PXP_CSC1_COEF2_RSVD1 27
++#define BM_PXP_CSC1_COEF2_RSVD1 0xF8000000
++#define BF_PXP_CSC1_COEF2_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC1_COEF2_RSVD1)
++#define BP_PXP_CSC1_COEF2_C2 16
++#define BM_PXP_CSC1_COEF2_C2 0x07FF0000
++#define BF_PXP_CSC1_COEF2_C2(v) \
++ (((v) << 16) & BM_PXP_CSC1_COEF2_C2)
++#define BP_PXP_CSC1_COEF2_RSVD0 11
++#define BM_PXP_CSC1_COEF2_RSVD0 0x0000F800
++#define BF_PXP_CSC1_COEF2_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC1_COEF2_RSVD0)
++#define BP_PXP_CSC1_COEF2_C3 0
++#define BM_PXP_CSC1_COEF2_C3 0x000007FF
++#define BF_PXP_CSC1_COEF2_C3(v) \
++ (((v) << 0) & BM_PXP_CSC1_COEF2_C3)
++
++#define HW_PXP_CSC2_CTRL (0x000001d0)
++
++#define BP_PXP_CSC2_CTRL_RSVD 3
++#define BM_PXP_CSC2_CTRL_RSVD 0xFFFFFFF8
++#define BF_PXP_CSC2_CTRL_RSVD(v) \
++ (((v) << 3) & BM_PXP_CSC2_CTRL_RSVD)
++#define BP_PXP_CSC2_CTRL_CSC_MODE 1
++#define BM_PXP_CSC2_CTRL_CSC_MODE 0x00000006
++#define BF_PXP_CSC2_CTRL_CSC_MODE(v) \
++ (((v) << 1) & BM_PXP_CSC2_CTRL_CSC_MODE)
++#define BV_PXP_CSC2_CTRL_CSC_MODE__YUV2RGB 0x0
++#define BV_PXP_CSC2_CTRL_CSC_MODE__YCbCr2RGB 0x1
++#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YUV 0x2
++#define BV_PXP_CSC2_CTRL_CSC_MODE__RGB2YCbCr 0x3
++#define BM_PXP_CSC2_CTRL_BYPASS 0x00000001
++
++#define HW_PXP_CSC2_COEF0 (0x000001e0)
++
++#define BP_PXP_CSC2_COEF0_RSVD1 27
++#define BM_PXP_CSC2_COEF0_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF0_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF0_RSVD1)
++#define BP_PXP_CSC2_COEF0_A2 16
++#define BM_PXP_CSC2_COEF0_A2 0x07FF0000
++#define BF_PXP_CSC2_COEF0_A2(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF0_A2)
++#define BP_PXP_CSC2_COEF0_RSVD0 11
++#define BM_PXP_CSC2_COEF0_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF0_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF0_RSVD0)
++#define BP_PXP_CSC2_COEF0_A1 0
++#define BM_PXP_CSC2_COEF0_A1 0x000007FF
++#define BF_PXP_CSC2_COEF0_A1(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF0_A1)
++
++#define HW_PXP_CSC2_COEF1 (0x000001f0)
++
++#define BP_PXP_CSC2_COEF1_RSVD1 27
++#define BM_PXP_CSC2_COEF1_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF1_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF1_RSVD1)
++#define BP_PXP_CSC2_COEF1_B1 16
++#define BM_PXP_CSC2_COEF1_B1 0x07FF0000
++#define BF_PXP_CSC2_COEF1_B1(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF1_B1)
++#define BP_PXP_CSC2_COEF1_RSVD0 11
++#define BM_PXP_CSC2_COEF1_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF1_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF1_RSVD0)
++#define BP_PXP_CSC2_COEF1_A3 0
++#define BM_PXP_CSC2_COEF1_A3 0x000007FF
++#define BF_PXP_CSC2_COEF1_A3(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF1_A3)
++
++#define HW_PXP_CSC2_COEF2 (0x00000200)
++
++#define BP_PXP_CSC2_COEF2_RSVD1 27
++#define BM_PXP_CSC2_COEF2_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF2_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF2_RSVD1)
++#define BP_PXP_CSC2_COEF2_B3 16
++#define BM_PXP_CSC2_COEF2_B3 0x07FF0000
++#define BF_PXP_CSC2_COEF2_B3(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF2_B3)
++#define BP_PXP_CSC2_COEF2_RSVD0 11
++#define BM_PXP_CSC2_COEF2_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF2_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF2_RSVD0)
++#define BP_PXP_CSC2_COEF2_B2 0
++#define BM_PXP_CSC2_COEF2_B2 0x000007FF
++#define BF_PXP_CSC2_COEF2_B2(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF2_B2)
++
++#define HW_PXP_CSC2_COEF3 (0x00000210)
++
++#define BP_PXP_CSC2_COEF3_RSVD1 27
++#define BM_PXP_CSC2_COEF3_RSVD1 0xF8000000
++#define BF_PXP_CSC2_COEF3_RSVD1(v) \
++ (((v) << 27) & BM_PXP_CSC2_COEF3_RSVD1)
++#define BP_PXP_CSC2_COEF3_C2 16
++#define BM_PXP_CSC2_COEF3_C2 0x07FF0000
++#define BF_PXP_CSC2_COEF3_C2(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF3_C2)
++#define BP_PXP_CSC2_COEF3_RSVD0 11
++#define BM_PXP_CSC2_COEF3_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF3_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF3_RSVD0)
++#define BP_PXP_CSC2_COEF3_C1 0
++#define BM_PXP_CSC2_COEF3_C1 0x000007FF
++#define BF_PXP_CSC2_COEF3_C1(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF3_C1)
++
++#define HW_PXP_CSC2_COEF4 (0x00000220)
++
++#define BP_PXP_CSC2_COEF4_RSVD1 25
++#define BM_PXP_CSC2_COEF4_RSVD1 0xFE000000
++#define BF_PXP_CSC2_COEF4_RSVD1(v) \
++ (((v) << 25) & BM_PXP_CSC2_COEF4_RSVD1)
++#define BP_PXP_CSC2_COEF4_D1 16
++#define BM_PXP_CSC2_COEF4_D1 0x01FF0000
++#define BF_PXP_CSC2_COEF4_D1(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF4_D1)
++#define BP_PXP_CSC2_COEF4_RSVD0 11
++#define BM_PXP_CSC2_COEF4_RSVD0 0x0000F800
++#define BF_PXP_CSC2_COEF4_RSVD0(v) \
++ (((v) << 11) & BM_PXP_CSC2_COEF4_RSVD0)
++#define BP_PXP_CSC2_COEF4_C3 0
++#define BM_PXP_CSC2_COEF4_C3 0x000007FF
++#define BF_PXP_CSC2_COEF4_C3(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF4_C3)
++
++#define HW_PXP_CSC2_COEF5 (0x00000230)
++
++#define BP_PXP_CSC2_COEF5_RSVD1 25
++#define BM_PXP_CSC2_COEF5_RSVD1 0xFE000000
++#define BF_PXP_CSC2_COEF5_RSVD1(v) \
++ (((v) << 25) & BM_PXP_CSC2_COEF5_RSVD1)
++#define BP_PXP_CSC2_COEF5_D3 16
++#define BM_PXP_CSC2_COEF5_D3 0x01FF0000
++#define BF_PXP_CSC2_COEF5_D3(v) \
++ (((v) << 16) & BM_PXP_CSC2_COEF5_D3)
++#define BP_PXP_CSC2_COEF5_RSVD0 9
++#define BM_PXP_CSC2_COEF5_RSVD0 0x0000FE00
++#define BF_PXP_CSC2_COEF5_RSVD0(v) \
++ (((v) << 9) & BM_PXP_CSC2_COEF5_RSVD0)
++#define BP_PXP_CSC2_COEF5_D2 0
++#define BM_PXP_CSC2_COEF5_D2 0x000001FF
++#define BF_PXP_CSC2_COEF5_D2(v) \
++ (((v) << 0) & BM_PXP_CSC2_COEF5_D2)
++
++#define HW_PXP_LUT_CTRL (0x00000240)
++
++#define BM_PXP_LUT_CTRL_BYPASS 0x80000000
++#define BP_PXP_LUT_CTRL_RSVD3 26
++#define BM_PXP_LUT_CTRL_RSVD3 0x7C000000
++#define BF_PXP_LUT_CTRL_RSVD3(v) \
++ (((v) << 26) & BM_PXP_LUT_CTRL_RSVD3)
++#define BP_PXP_LUT_CTRL_LOOKUP_MODE 24
++#define BM_PXP_LUT_CTRL_LOOKUP_MODE 0x03000000
++#define BF_PXP_LUT_CTRL_LOOKUP_MODE(v) \
++ (((v) << 24) & BM_PXP_LUT_CTRL_LOOKUP_MODE)
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__CACHE_RGB565 0x0
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_Y8 0x1
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB444 0x2
++#define BV_PXP_LUT_CTRL_LOOKUP_MODE__DIRECT_RGB454 0x3
++#define BP_PXP_LUT_CTRL_RSVD2 18
++#define BM_PXP_LUT_CTRL_RSVD2 0x00FC0000
++#define BF_PXP_LUT_CTRL_RSVD2(v) \
++ (((v) << 18) & BM_PXP_LUT_CTRL_RSVD2)
++#define BP_PXP_LUT_CTRL_OUT_MODE 16
++#define BM_PXP_LUT_CTRL_OUT_MODE 0x00030000
++#define BF_PXP_LUT_CTRL_OUT_MODE(v) \
++ (((v) << 16) & BM_PXP_LUT_CTRL_OUT_MODE)
++#define BV_PXP_LUT_CTRL_OUT_MODE__RESERVED 0x0
++#define BV_PXP_LUT_CTRL_OUT_MODE__Y8 0x1
++#define BV_PXP_LUT_CTRL_OUT_MODE__RGBW4444CFA 0x2
++#define BV_PXP_LUT_CTRL_OUT_MODE__RGB888 0x3
++#define BP_PXP_LUT_CTRL_RSVD1 11
++#define BM_PXP_LUT_CTRL_RSVD1 0x0000F800
++#define BF_PXP_LUT_CTRL_RSVD1(v) \
++ (((v) << 11) & BM_PXP_LUT_CTRL_RSVD1)
++#define BM_PXP_LUT_CTRL_SEL_8KB 0x00000400
++#define BM_PXP_LUT_CTRL_LRU_UPD 0x00000200
++#define BM_PXP_LUT_CTRL_INVALID 0x00000100
++#define BP_PXP_LUT_CTRL_RSVD0 1
++#define BM_PXP_LUT_CTRL_RSVD0 0x000000FE
++#define BF_PXP_LUT_CTRL_RSVD0(v) \
++ (((v) << 1) & BM_PXP_LUT_CTRL_RSVD0)
++#define BM_PXP_LUT_CTRL_DMA_START 0x00000001
++
++#define HW_PXP_LUT_ADDR (0x00000250)
++
++#define BM_PXP_LUT_ADDR_RSVD2 0x80000000
++#define BP_PXP_LUT_ADDR_NUM_BYTES 16
++#define BM_PXP_LUT_ADDR_NUM_BYTES 0x7FFF0000
++#define BF_PXP_LUT_ADDR_NUM_BYTES(v) \
++ (((v) << 16) & BM_PXP_LUT_ADDR_NUM_BYTES)
++#define BP_PXP_LUT_ADDR_RSVD1 14
++#define BM_PXP_LUT_ADDR_RSVD1 0x0000C000
++#define BF_PXP_LUT_ADDR_RSVD1(v) \
++ (((v) << 14) & BM_PXP_LUT_ADDR_RSVD1)
++#define BP_PXP_LUT_ADDR_ADDR 0
++#define BM_PXP_LUT_ADDR_ADDR 0x00003FFF
++#define BF_PXP_LUT_ADDR_ADDR(v) \
++ (((v) << 0) & BM_PXP_LUT_ADDR_ADDR)
++
++#define HW_PXP_LUT_DATA (0x00000260)
++
++#define BP_PXP_LUT_DATA_DATA 0
++#define BM_PXP_LUT_DATA_DATA 0xFFFFFFFF
++#define BF_PXP_LUT_DATA_DATA(v) (v)
++
++#define HW_PXP_LUT_EXTMEM (0x00000270)
++
++#define BP_PXP_LUT_EXTMEM_ADDR 0
++#define BM_PXP_LUT_EXTMEM_ADDR 0xFFFFFFFF
++#define BF_PXP_LUT_EXTMEM_ADDR(v) (v)
++
++#define HW_PXP_CFA (0x00000280)
++
++#define BP_PXP_CFA_DATA 0
++#define BM_PXP_CFA_DATA 0xFFFFFFFF
++#define BF_PXP_CFA_DATA(v) (v)
++
++#define HW_PXP_HIST_CTRL (0x00000290)
++
++#define BP_PXP_HIST_CTRL_RSVD 6
++#define BM_PXP_HIST_CTRL_RSVD 0xFFFFFFC0
++#define BF_PXP_HIST_CTRL_RSVD(v) \
++ (((v) << 6) & BM_PXP_HIST_CTRL_RSVD)
++#define BP_PXP_HIST_CTRL_PANEL_MODE 4
++#define BM_PXP_HIST_CTRL_PANEL_MODE 0x00000030
++#define BF_PXP_HIST_CTRL_PANEL_MODE(v) \
++ (((v) << 4) & BM_PXP_HIST_CTRL_PANEL_MODE)
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY4 0x0
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY8 0x1
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY16 0x2
++#define BV_PXP_HIST_CTRL_PANEL_MODE__GRAY32 0x3
++#define BP_PXP_HIST_CTRL_STATUS 0
++#define BM_PXP_HIST_CTRL_STATUS 0x0000000F
++#define BF_PXP_HIST_CTRL_STATUS(v) \
++ (((v) << 0) & BM_PXP_HIST_CTRL_STATUS)
++
++#define HW_PXP_HIST2_PARAM (0x000002a0)
++
++#define BP_PXP_HIST2_PARAM_RSVD 16
++#define BM_PXP_HIST2_PARAM_RSVD 0xFFFF0000
++#define BF_PXP_HIST2_PARAM_RSVD(v) \
++ (((v) << 16) & BM_PXP_HIST2_PARAM_RSVD)
++#define BP_PXP_HIST2_PARAM_RSVD1 13
++#define BM_PXP_HIST2_PARAM_RSVD1 0x0000E000
++#define BF_PXP_HIST2_PARAM_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST2_PARAM_RSVD1)
++#define BP_PXP_HIST2_PARAM_VALUE1 8
++#define BM_PXP_HIST2_PARAM_VALUE1 0x00001F00
++#define BF_PXP_HIST2_PARAM_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST2_PARAM_VALUE1)
++#define BP_PXP_HIST2_PARAM_RSVD0 5
++#define BM_PXP_HIST2_PARAM_RSVD0 0x000000E0
++#define BF_PXP_HIST2_PARAM_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST2_PARAM_RSVD0)
++#define BP_PXP_HIST2_PARAM_VALUE0 0
++#define BM_PXP_HIST2_PARAM_VALUE0 0x0000001F
++#define BF_PXP_HIST2_PARAM_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST2_PARAM_VALUE0)
++
++#define HW_PXP_HIST4_PARAM (0x000002b0)
++
++#define BP_PXP_HIST4_PARAM_RSVD3 29
++#define BM_PXP_HIST4_PARAM_RSVD3 0xE0000000
++#define BF_PXP_HIST4_PARAM_RSVD3(v) \
++ (((v) << 29) & BM_PXP_HIST4_PARAM_RSVD3)
++#define BP_PXP_HIST4_PARAM_VALUE3 24
++#define BM_PXP_HIST4_PARAM_VALUE3 0x1F000000
++#define BF_PXP_HIST4_PARAM_VALUE3(v) \
++ (((v) << 24) & BM_PXP_HIST4_PARAM_VALUE3)
++#define BP_PXP_HIST4_PARAM_RSVD2 21
++#define BM_PXP_HIST4_PARAM_RSVD2 0x00E00000
++#define BF_PXP_HIST4_PARAM_RSVD2(v) \
++ (((v) << 21) & BM_PXP_HIST4_PARAM_RSVD2)
++#define BP_PXP_HIST4_PARAM_VALUE2 16
++#define BM_PXP_HIST4_PARAM_VALUE2 0x001F0000
++#define BF_PXP_HIST4_PARAM_VALUE2(v) \
++ (((v) << 16) & BM_PXP_HIST4_PARAM_VALUE2)
++#define BP_PXP_HIST4_PARAM_RSVD1 13
++#define BM_PXP_HIST4_PARAM_RSVD1 0x0000E000
++#define BF_PXP_HIST4_PARAM_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST4_PARAM_RSVD1)
++#define BP_PXP_HIST4_PARAM_VALUE1 8
++#define BM_PXP_HIST4_PARAM_VALUE1 0x00001F00
++#define BF_PXP_HIST4_PARAM_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST4_PARAM_VALUE1)
++#define BP_PXP_HIST4_PARAM_RSVD0 5
++#define BM_PXP_HIST4_PARAM_RSVD0 0x000000E0
++#define BF_PXP_HIST4_PARAM_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST4_PARAM_RSVD0)
++#define BP_PXP_HIST4_PARAM_VALUE0 0
++#define BM_PXP_HIST4_PARAM_VALUE0 0x0000001F
++#define BF_PXP_HIST4_PARAM_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST4_PARAM_VALUE0)
++
++#define HW_PXP_HIST8_PARAM0 (0x000002c0)
++
++#define BP_PXP_HIST8_PARAM0_RSVD3 29
++#define BM_PXP_HIST8_PARAM0_RSVD3 0xE0000000
++#define BF_PXP_HIST8_PARAM0_RSVD3(v) \
++ (((v) << 29) & BM_PXP_HIST8_PARAM0_RSVD3)
++#define BP_PXP_HIST8_PARAM0_VALUE3 24
++#define BM_PXP_HIST8_PARAM0_VALUE3 0x1F000000
++#define BF_PXP_HIST8_PARAM0_VALUE3(v) \
++ (((v) << 24) & BM_PXP_HIST8_PARAM0_VALUE3)
++#define BP_PXP_HIST8_PARAM0_RSVD2 21
++#define BM_PXP_HIST8_PARAM0_RSVD2 0x00E00000
++#define BF_PXP_HIST8_PARAM0_RSVD2(v) \
++ (((v) << 21) & BM_PXP_HIST8_PARAM0_RSVD2)
++#define BP_PXP_HIST8_PARAM0_VALUE2 16
++#define BM_PXP_HIST8_PARAM0_VALUE2 0x001F0000
++#define BF_PXP_HIST8_PARAM0_VALUE2(v) \
++ (((v) << 16) & BM_PXP_HIST8_PARAM0_VALUE2)
++#define BP_PXP_HIST8_PARAM0_RSVD1 13
++#define BM_PXP_HIST8_PARAM0_RSVD1 0x0000E000
++#define BF_PXP_HIST8_PARAM0_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST8_PARAM0_RSVD1)
++#define BP_PXP_HIST8_PARAM0_VALUE1 8
++#define BM_PXP_HIST8_PARAM0_VALUE1 0x00001F00
++#define BF_PXP_HIST8_PARAM0_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST8_PARAM0_VALUE1)
++#define BP_PXP_HIST8_PARAM0_RSVD0 5
++#define BM_PXP_HIST8_PARAM0_RSVD0 0x000000E0
++#define BF_PXP_HIST8_PARAM0_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST8_PARAM0_RSVD0)
++#define BP_PXP_HIST8_PARAM0_VALUE0 0
++#define BM_PXP_HIST8_PARAM0_VALUE0 0x0000001F
++#define BF_PXP_HIST8_PARAM0_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST8_PARAM0_VALUE0)
++
++#define HW_PXP_HIST8_PARAM1 (0x000002d0)
++
++#define BP_PXP_HIST8_PARAM1_RSVD7 29
++#define BM_PXP_HIST8_PARAM1_RSVD7 0xE0000000
++#define BF_PXP_HIST8_PARAM1_RSVD7(v) \
++ (((v) << 29) & BM_PXP_HIST8_PARAM1_RSVD7)
++#define BP_PXP_HIST8_PARAM1_VALUE7 24
++#define BM_PXP_HIST8_PARAM1_VALUE7 0x1F000000
++#define BF_PXP_HIST8_PARAM1_VALUE7(v) \
++ (((v) << 24) & BM_PXP_HIST8_PARAM1_VALUE7)
++#define BP_PXP_HIST8_PARAM1_RSVD6 21
++#define BM_PXP_HIST8_PARAM1_RSVD6 0x00E00000
++#define BF_PXP_HIST8_PARAM1_RSVD6(v) \
++ (((v) << 21) & BM_PXP_HIST8_PARAM1_RSVD6)
++#define BP_PXP_HIST8_PARAM1_VALUE6 16
++#define BM_PXP_HIST8_PARAM1_VALUE6 0x001F0000
++#define BF_PXP_HIST8_PARAM1_VALUE6(v) \
++ (((v) << 16) & BM_PXP_HIST8_PARAM1_VALUE6)
++#define BP_PXP_HIST8_PARAM1_RSVD5 13
++#define BM_PXP_HIST8_PARAM1_RSVD5 0x0000E000
++#define BF_PXP_HIST8_PARAM1_RSVD5(v) \
++ (((v) << 13) & BM_PXP_HIST8_PARAM1_RSVD5)
++#define BP_PXP_HIST8_PARAM1_VALUE5 8
++#define BM_PXP_HIST8_PARAM1_VALUE5 0x00001F00
++#define BF_PXP_HIST8_PARAM1_VALUE5(v) \
++ (((v) << 8) & BM_PXP_HIST8_PARAM1_VALUE5)
++#define BP_PXP_HIST8_PARAM1_RSVD4 5
++#define BM_PXP_HIST8_PARAM1_RSVD4 0x000000E0
++#define BF_PXP_HIST8_PARAM1_RSVD4(v) \
++ (((v) << 5) & BM_PXP_HIST8_PARAM1_RSVD4)
++#define BP_PXP_HIST8_PARAM1_VALUE4 0
++#define BM_PXP_HIST8_PARAM1_VALUE4 0x0000001F
++#define BF_PXP_HIST8_PARAM1_VALUE4(v) \
++ (((v) << 0) & BM_PXP_HIST8_PARAM1_VALUE4)
++
++#define HW_PXP_HIST16_PARAM0 (0x000002e0)
++
++#define BP_PXP_HIST16_PARAM0_RSVD3 29
++#define BM_PXP_HIST16_PARAM0_RSVD3 0xE0000000
++#define BF_PXP_HIST16_PARAM0_RSVD3(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM0_RSVD3)
++#define BP_PXP_HIST16_PARAM0_VALUE3 24
++#define BM_PXP_HIST16_PARAM0_VALUE3 0x1F000000
++#define BF_PXP_HIST16_PARAM0_VALUE3(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM0_VALUE3)
++#define BP_PXP_HIST16_PARAM0_RSVD2 21
++#define BM_PXP_HIST16_PARAM0_RSVD2 0x00E00000
++#define BF_PXP_HIST16_PARAM0_RSVD2(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM0_RSVD2)
++#define BP_PXP_HIST16_PARAM0_VALUE2 16
++#define BM_PXP_HIST16_PARAM0_VALUE2 0x001F0000
++#define BF_PXP_HIST16_PARAM0_VALUE2(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM0_VALUE2)
++#define BP_PXP_HIST16_PARAM0_RSVD1 13
++#define BM_PXP_HIST16_PARAM0_RSVD1 0x0000E000
++#define BF_PXP_HIST16_PARAM0_RSVD1(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM0_RSVD1)
++#define BP_PXP_HIST16_PARAM0_VALUE1 8
++#define BM_PXP_HIST16_PARAM0_VALUE1 0x00001F00
++#define BF_PXP_HIST16_PARAM0_VALUE1(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM0_VALUE1)
++#define BP_PXP_HIST16_PARAM0_RSVD0 5
++#define BM_PXP_HIST16_PARAM0_RSVD0 0x000000E0
++#define BF_PXP_HIST16_PARAM0_RSVD0(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM0_RSVD0)
++#define BP_PXP_HIST16_PARAM0_VALUE0 0
++#define BM_PXP_HIST16_PARAM0_VALUE0 0x0000001F
++#define BF_PXP_HIST16_PARAM0_VALUE0(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM0_VALUE0)
++
++#define HW_PXP_HIST16_PARAM1 (0x000002f0)
++
++#define BP_PXP_HIST16_PARAM1_RSVD7 29
++#define BM_PXP_HIST16_PARAM1_RSVD7 0xE0000000
++#define BF_PXP_HIST16_PARAM1_RSVD7(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM1_RSVD7)
++#define BP_PXP_HIST16_PARAM1_VALUE7 24
++#define BM_PXP_HIST16_PARAM1_VALUE7 0x1F000000
++#define BF_PXP_HIST16_PARAM1_VALUE7(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM1_VALUE7)
++#define BP_PXP_HIST16_PARAM1_RSVD6 21
++#define BM_PXP_HIST16_PARAM1_RSVD6 0x00E00000
++#define BF_PXP_HIST16_PARAM1_RSVD6(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM1_RSVD6)
++#define BP_PXP_HIST16_PARAM1_VALUE6 16
++#define BM_PXP_HIST16_PARAM1_VALUE6 0x001F0000
++#define BF_PXP_HIST16_PARAM1_VALUE6(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM1_VALUE6)
++#define BP_PXP_HIST16_PARAM1_RSVD5 13
++#define BM_PXP_HIST16_PARAM1_RSVD5 0x0000E000
++#define BF_PXP_HIST16_PARAM1_RSVD5(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM1_RSVD5)
++#define BP_PXP_HIST16_PARAM1_VALUE5 8
++#define BM_PXP_HIST16_PARAM1_VALUE5 0x00001F00
++#define BF_PXP_HIST16_PARAM1_VALUE5(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM1_VALUE5)
++#define BP_PXP_HIST16_PARAM1_RSVD4 5
++#define BM_PXP_HIST16_PARAM1_RSVD4 0x000000E0
++#define BF_PXP_HIST16_PARAM1_RSVD4(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM1_RSVD4)
++#define BP_PXP_HIST16_PARAM1_VALUE4 0
++#define BM_PXP_HIST16_PARAM1_VALUE4 0x0000001F
++#define BF_PXP_HIST16_PARAM1_VALUE4(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM1_VALUE4)
++
++#define HW_PXP_HIST16_PARAM2 (0x00000300)
++
++#define BP_PXP_HIST16_PARAM2_RSVD11 29
++#define BM_PXP_HIST16_PARAM2_RSVD11 0xE0000000
++#define BF_PXP_HIST16_PARAM2_RSVD11(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM2_RSVD11)
++#define BP_PXP_HIST16_PARAM2_VALUE11 24
++#define BM_PXP_HIST16_PARAM2_VALUE11 0x1F000000
++#define BF_PXP_HIST16_PARAM2_VALUE11(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM2_VALUE11)
++#define BP_PXP_HIST16_PARAM2_RSVD10 21
++#define BM_PXP_HIST16_PARAM2_RSVD10 0x00E00000
++#define BF_PXP_HIST16_PARAM2_RSVD10(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM2_RSVD10)
++#define BP_PXP_HIST16_PARAM2_VALUE10 16
++#define BM_PXP_HIST16_PARAM2_VALUE10 0x001F0000
++#define BF_PXP_HIST16_PARAM2_VALUE10(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM2_VALUE10)
++#define BP_PXP_HIST16_PARAM2_RSVD9 13
++#define BM_PXP_HIST16_PARAM2_RSVD9 0x0000E000
++#define BF_PXP_HIST16_PARAM2_RSVD9(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM2_RSVD9)
++#define BP_PXP_HIST16_PARAM2_VALUE9 8
++#define BM_PXP_HIST16_PARAM2_VALUE9 0x00001F00
++#define BF_PXP_HIST16_PARAM2_VALUE9(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM2_VALUE9)
++#define BP_PXP_HIST16_PARAM2_RSVD8 5
++#define BM_PXP_HIST16_PARAM2_RSVD8 0x000000E0
++#define BF_PXP_HIST16_PARAM2_RSVD8(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM2_RSVD8)
++#define BP_PXP_HIST16_PARAM2_VALUE8 0
++#define BM_PXP_HIST16_PARAM2_VALUE8 0x0000001F
++#define BF_PXP_HIST16_PARAM2_VALUE8(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM2_VALUE8)
++
++#define HW_PXP_HIST16_PARAM3 (0x00000310)
++
++#define BP_PXP_HIST16_PARAM3_RSVD15 29
++#define BM_PXP_HIST16_PARAM3_RSVD15 0xE0000000
++#define BF_PXP_HIST16_PARAM3_RSVD15(v) \
++ (((v) << 29) & BM_PXP_HIST16_PARAM3_RSVD15)
++#define BP_PXP_HIST16_PARAM3_VALUE15 24
++#define BM_PXP_HIST16_PARAM3_VALUE15 0x1F000000
++#define BF_PXP_HIST16_PARAM3_VALUE15(v) \
++ (((v) << 24) & BM_PXP_HIST16_PARAM3_VALUE15)
++#define BP_PXP_HIST16_PARAM3_RSVD14 21
++#define BM_PXP_HIST16_PARAM3_RSVD14 0x00E00000
++#define BF_PXP_HIST16_PARAM3_RSVD14(v) \
++ (((v) << 21) & BM_PXP_HIST16_PARAM3_RSVD14)
++#define BP_PXP_HIST16_PARAM3_VALUE14 16
++#define BM_PXP_HIST16_PARAM3_VALUE14 0x001F0000
++#define BF_PXP_HIST16_PARAM3_VALUE14(v) \
++ (((v) << 16) & BM_PXP_HIST16_PARAM3_VALUE14)
++#define BP_PXP_HIST16_PARAM3_RSVD13 13
++#define BM_PXP_HIST16_PARAM3_RSVD13 0x0000E000
++#define BF_PXP_HIST16_PARAM3_RSVD13(v) \
++ (((v) << 13) & BM_PXP_HIST16_PARAM3_RSVD13)
++#define BP_PXP_HIST16_PARAM3_VALUE13 8
++#define BM_PXP_HIST16_PARAM3_VALUE13 0x00001F00
++#define BF_PXP_HIST16_PARAM3_VALUE13(v) \
++ (((v) << 8) & BM_PXP_HIST16_PARAM3_VALUE13)
++#define BP_PXP_HIST16_PARAM3_RSVD12 5
++#define BM_PXP_HIST16_PARAM3_RSVD12 0x000000E0
++#define BF_PXP_HIST16_PARAM3_RSVD12(v) \
++ (((v) << 5) & BM_PXP_HIST16_PARAM3_RSVD12)
++#define BP_PXP_HIST16_PARAM3_VALUE12 0
++#define BM_PXP_HIST16_PARAM3_VALUE12 0x0000001F
++#define BF_PXP_HIST16_PARAM3_VALUE12(v) \
++ (((v) << 0) & BM_PXP_HIST16_PARAM3_VALUE12)
++
++#define HW_PXP_POWER (0x00000320)
++
++#define BP_PXP_POWER_CTRL 12
++#define BM_PXP_POWER_CTRL 0xFFFFF000
++#define BF_PXP_POWER_CTRL(v) \
++ (((v) << 12) & BM_PXP_POWER_CTRL)
++#define BP_PXP_POWER_ROT_MEM_LP_STATE 9
++#define BM_PXP_POWER_ROT_MEM_LP_STATE 0x00000E00
++#define BF_PXP_POWER_ROT_MEM_LP_STATE(v) \
++ (((v) << 9) & BM_PXP_POWER_ROT_MEM_LP_STATE)
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__NONE 0x0
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__LS 0x1
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__DS 0x2
++#define BV_PXP_POWER_ROT_MEM_LP_STATE__SD 0x4
++#define BP_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 6
++#define BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN 0x000001C0
++#define BF_PXP_POWER_LUT_LP_STATE_WAY1_BANKN(v) \
++ (((v) << 6) & BM_PXP_POWER_LUT_LP_STATE_WAY1_BANKN)
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__NONE 0x0
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__LS 0x1
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__DS 0x2
++#define BV_PXP_POWER_LUT_LP_STATE_WAY1_BANKN__SD 0x4
++#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 3
++#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN 0x00000038
++#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANKN(v) \
++ (((v) << 3) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANKN)
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__NONE 0x0
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__LS 0x1
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__DS 0x2
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANKN__SD 0x4
++#define BP_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0
++#define BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0 0x00000007
++#define BF_PXP_POWER_LUT_LP_STATE_WAY0_BANK0(v) \
++ (((v) << 0) & BM_PXP_POWER_LUT_LP_STATE_WAY0_BANK0)
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__NONE 0x0
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__LS 0x1
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__DS 0x2
++#define BV_PXP_POWER_LUT_LP_STATE_WAY0_BANK0__SD 0x4
++
++#define HW_PXP_NEXT (0x00000400)
++
++#define BP_PXP_NEXT_POINTER 2
++#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
++#define BF_PXP_NEXT_POINTER(v) \
++ (((v) << 2) & BM_PXP_NEXT_POINTER)
++#define BM_PXP_NEXT_RSVD 0x00000002
++#define BM_PXP_NEXT_ENABLED 0x00000001
++
++#define HW_PXP_DEBUGCTRL (0x00000410)
++
++#define BP_PXP_DEBUGCTRL_RSVD 12
++#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFF000
++#define BF_PXP_DEBUGCTRL_RSVD(v) \
++ (((v) << 12) & BM_PXP_DEBUGCTRL_RSVD)
++#define BP_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 8
++#define BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT 0x00000F00
++#define BF_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT(v) \
++ (((v) << 8) & BM_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT)
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__NONE 0x0
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MISS_CNT 0x1
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__HIT_CNT 0x2
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__LAT_CNT 0x4
++#define BV_PXP_DEBUGCTRL_LUT_CLR_STAT_CNT__MAX_LAT 0x8
++#define BP_PXP_DEBUGCTRL_SELECT 0
++#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
++#define BF_PXP_DEBUGCTRL_SELECT(v) \
++ (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
++#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0
++#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1
++#define BV_PXP_DEBUGCTRL_SELECT__PSBUF 0x2
++#define BV_PXP_DEBUGCTRL_SELECT__PSBAX 0x3
++#define BV_PXP_DEBUGCTRL_SELECT__PSBAY 0x4
++#define BV_PXP_DEBUGCTRL_SELECT__ASBUF 0x5
++#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
++#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF0 0x7
++#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF1 0x8
++#define BV_PXP_DEBUGCTRL_SELECT__OUTBUF2 0x9
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_STAT 0x10
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_MISS 0x11
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_HIT 0x12
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_LAT 0x13
++#define BV_PXP_DEBUGCTRL_SELECT__LUT_MAX_LAT 0x14
++
++#define HW_PXP_DEBUG (0x00000420)
++
++#define BP_PXP_DEBUG_DATA 0
++#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
++#define BF_PXP_DEBUG_DATA(v) (v)
++
++#define HW_PXP_VERSION (0x00000430)
++
++#define BP_PXP_VERSION_MAJOR 24
++#define BM_PXP_VERSION_MAJOR 0xFF000000
++#define BF_PXP_VERSION_MAJOR(v) \
++ (((v) << 24) & BM_PXP_VERSION_MAJOR)
++#define BP_PXP_VERSION_MINOR 16
++#define BM_PXP_VERSION_MINOR 0x00FF0000
++#define BF_PXP_VERSION_MINOR(v) \
++ (((v) << 16) & BM_PXP_VERSION_MINOR)
++#define BP_PXP_VERSION_STEP 0
++#define BM_PXP_VERSION_STEP 0x0000FFFF
++#define BF_PXP_VERSION_STEP(v) \
++ (((v) << 0) & BM_PXP_VERSION_STEP)
++#endif /* __ARCH_ARM___PXP_H */
+diff -Nur linux-3.14.72.orig/drivers/gpio/gpio-generic.c linux-3.14.72/drivers/gpio/gpio-generic.c
+--- linux-3.14.72.orig/drivers/gpio/gpio-generic.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/gpio/gpio-generic.c 2016-06-19 22:11:55.121152080 +0200
+@@ -139,7 +139,7 @@
+ {
+ struct bgpio_chip *bgc = to_bgpio_chip(gc);
+
+- return bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio);
++ return !!(bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio));
+ }
+
+ static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+diff -Nur linux-3.14.72.orig/drivers/gpio/gpio-pca953x.c linux-3.14.72/drivers/gpio/gpio-pca953x.c
+--- linux-3.14.72.orig/drivers/gpio/gpio-pca953x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/gpio/gpio-pca953x.c 2016-06-19 22:11:55.121152080 +0200
+@@ -19,6 +19,7 @@
+ #include <linux/irqdomain.h>
+ #include <linux/i2c.h>
+ #include <linux/platform_data/pca953x.h>
++#include <linux/reset.h>
+ #include <linux/slab.h>
+ #ifdef CONFIG_OF_GPIO
+ #include <linux/of_platform.h>
+@@ -741,6 +742,10 @@
+
+ mutex_init(&chip->i2c_lock);
+
++ ret = device_reset(&client->dev);
++ if (ret == -ENODEV)
++ return -EPROBE_DEFER;
++
+ /* initialize cached registers from their original values.
+ * we can't share this chip with another i2c master.
+ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/drm/drm_platform.c linux-3.14.72/drivers/gpu/drm/drm_platform.c
+--- linux-3.14.72.orig/drivers/gpu/drm/drm_platform.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/gpu/drm/drm_platform.c 2016-06-19 22:11:55.121152080 +0200
+@@ -53,6 +53,14 @@
+
+ dev->platformdev = platdev;
+
++ /*
++ * If drvdata is not used by platform driver, let's set drm_device
++ * pointer into it. We take this as the default usage of drvdata,
++ * and platform driver is free to overwrite it later as needed.
++ */
++ if (platform_get_drvdata(platdev) == NULL)
++ platform_set_drvdata(platdev, dev);
++
+ ret = drm_dev_register(dev, 0);
+ if (ret)
+ goto err_free;
+diff -Nur linux-3.14.72.orig/drivers/gpu/drm/Kconfig linux-3.14.72/drivers/gpu/drm/Kconfig
+--- linux-3.14.72.orig/drivers/gpu/drm/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/gpu/drm/Kconfig 2016-06-19 22:11:55.121152080 +0200
+@@ -166,6 +166,13 @@
+ Choose this option if you have a Savage3D/4/SuperSavage/Pro/Twister
+ chipset. If M is selected the module will be called savage.
+
++config DRM_VIVANTE
++ tristate "Vivante GCCore"
++ depends on DRM
++ help
++ Choose this option if you have a Vivante graphics card.
++ If M is selected, the module will be called vivante.
++
+ source "drivers/gpu/drm/exynos/Kconfig"
+
+ source "drivers/gpu/drm/vmwgfx/Kconfig"
+diff -Nur linux-3.14.72.orig/drivers/gpu/drm/Makefile linux-3.14.72/drivers/gpu/drm/Makefile
+--- linux-3.14.72.orig/drivers/gpu/drm/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/gpu/drm/Makefile 2016-06-19 22:11:55.121152080 +0200
+@@ -35,6 +35,7 @@
+ obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
+ obj-$(CONFIG_DRM_USB) += drm_usb.o
+ obj-$(CONFIG_DRM_TTM) += ttm/
++obj-$(CONFIG_DRM_VIVANTE) += vivante/
+ obj-$(CONFIG_DRM_TDFX) += tdfx/
+ obj-$(CONFIG_DRM_R128) += r128/
+ obj-$(CONFIG_DRM_RADEON)+= radeon/
+diff -Nur linux-3.14.72.orig/drivers/gpu/drm/vivante/Makefile linux-3.14.72/drivers/gpu/drm/vivante/Makefile
+--- linux-3.14.72.orig/drivers/gpu/drm/vivante/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/drm/vivante/Makefile 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,29 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2013 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++#
++# Makefile for the drm device driver. This driver provides support for the
++# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
++
++ccflags-y := -Iinclude/drm
++vivante-y := vivante_drv.o
++
++obj-$(CONFIG_DRM_VIVANTE) += vivante.o
+diff -Nur linux-3.14.72.orig/drivers/gpu/drm/vivante/vivante_drv.c linux-3.14.72/drivers/gpu/drm/vivante/vivante_drv.c
+--- linux-3.14.72.orig/drivers/gpu/drm/vivante/vivante_drv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/drm/vivante/vivante_drv.c 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,110 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/* vivante_drv.c -- vivante driver -*- linux-c -*-
++ *
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
++ * DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Rickard E. (Rik) Faith <faith@valinux.com>
++ * Daryll Strauss <daryll@valinux.com>
++ * Gareth Hughes <gareth@valinux.com>
++ */
++
++#include <linux/version.h>
++#include <linux/module.h>
++
++#include "drmP.h"
++#include "vivante_drv.h"
++
++#include "drm_pciids.h"
++
++static char platformdevicename[] = "Vivante GCCore";
++static struct platform_device *pplatformdev;
++
++static const struct file_operations viv_driver_fops = {
++ .owner = THIS_MODULE,
++ .open = drm_open,
++ .release = drm_release,
++ .unlocked_ioctl = drm_ioctl,
++ .mmap = drm_mmap,
++ .poll = drm_poll,
++ .llseek = noop_llseek,
++};
++
++static struct drm_driver driver = {
++ .fops = &viv_driver_fops,
++ .name = DRIVER_NAME,
++ .desc = DRIVER_DESC,
++ .date = DRIVER_DATE,
++ .major = DRIVER_MAJOR,
++ .minor = DRIVER_MINOR,
++ .patchlevel = DRIVER_PATCHLEVEL,
++};
++
++static int __init vivante_init(void)
++{
++ int retcode;
++
++ pplatformdev = platform_device_register_simple(platformdevicename,
++ -1, NULL, 0);
++ if (pplatformdev == NULL)
++ printk(KERN_ERR"Platform device is null\n");
++
++ retcode = drm_platform_init(&driver, pplatformdev);
++
++ return retcode;
++}
++
++static void __exit vivante_exit(void)
++{
++ if (pplatformdev) {
++ /* The drvdata is set in drm_get_platform_dev() */
++ drm_put_dev(platform_get_drvdata(pplatformdev));
++ platform_device_unregister(pplatformdev);
++ pplatformdev = NULL;
++ }
++}
++
++module_init(vivante_init);
++module_exit(vivante_exit);
++
++MODULE_AUTHOR(DRIVER_AUTHOR);
++MODULE_DESCRIPTION(DRIVER_DESC);
++MODULE_LICENSE("GPL and additional rights");
+diff -Nur linux-3.14.72.orig/drivers/gpu/drm/vivante/vivante_drv.h linux-3.14.72/drivers/gpu/drm/vivante/vivante_drv.h
+--- linux-3.14.72.orig/drivers/gpu/drm/vivante/vivante_drv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/drm/vivante/vivante_drv.h 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,66 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2013 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/* vivante_drv.h -- Vivante DRM template customization -*- linux-c -*-
++ * Created: Wed Feb 14 12:32:32 2012 by John Zhao
++ */
++/*
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ * Authors:
++ * Gareth Hughes <gareth@valinux.com>
++ */
++
++#ifndef __VIVANTE_DRV_H__
++#define __VIVANTE_DRV_H__
++
++/* General customization:
++ */
++
++#define DRIVER_AUTHOR "Vivante Inc."
++
++#define DRIVER_NAME "vivante"
++#define DRIVER_DESC "Vivante GCCore"
++#define DRIVER_DATE "20120216"
++
++#define DRIVER_MAJOR 1
++#define DRIVER_MINOR 0
++#define DRIVER_PATCHLEVEL 0
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h linux-3.14.72/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,34 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++extern gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++
++gcsALLOCATOR_DESC allocatorArray[] =
++{
++ /* Default allocator. */
++ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit),
++};
++
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h linux-3.14.72/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h 2016-06-19 22:11:55.121152080 +0200
+@@ -0,0 +1,45 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++extern gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++
++#if LINUX_CMA_FSL
++gceSTATUS
++_CMAFSLAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++#endif
++
++gcsALLOCATOR_DESC allocatorArray[] =
++{
++#if LINUX_CMA_FSL
++ gcmkDEFINE_ALLOCATOR_DESC("cmafsl", _CMAFSLAlloctorInit),
++#endif
++ /* Default allocator. */
++ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit),
++};
++
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c linux-3.14.72/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c 2016-06-19 22:11:55.125151817 +0200
+@@ -0,0 +1,386 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_allocator.h"
++
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsCMA_PRIV * gcsCMA_PRIV_PTR;
++typedef struct _gcsCMA_PRIV {
++ gctUINT32 cmasize;
++}
++gcsCMA_PRIV;
++
++struct mdl_cma_priv {
++ gctPOINTER kvaddr;
++ dma_addr_t physical;
++};
++
++int gc_cma_usage_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckALLOCATOR Allocator = node->device;
++ gcsCMA_PRIV_PTR priv = Allocator->privateData;
++
++ seq_printf(m, "cma: %u bytes\n", priv->cmasize);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"cmausage", gc_cma_usage_show},
++};
++
++static void
++_DefaultAllocatorDebugfsInit(
++ IN gckALLOCATOR Allocator,
++ IN gckDEBUGFS_DIR Root
++ )
++{
++ gcmkVERIFY_OK(
++ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "cma"));
++
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList),
++ Allocator
++ ));
++}
++
++static void
++_DefaultAllocatorDebugfsCleanup(
++ IN gckALLOCATOR Allocator
++ )
++{
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList)
++ ));
++
++ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir);
++}
++
++static gceSTATUS
++_CMAFSLAlloc(
++ IN gckALLOCATOR Allocator,
++ INOUT PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flags
++ )
++{
++ gceSTATUS status;
++ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData;
++
++ struct mdl_cma_priv *mdl_priv=gcvNULL;
++ gckOS os = Allocator->os;
++
++ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages);
++
++ gcmkONERROR(gckOS_Allocate(os, sizeof(struct mdl_cma_priv), (gctPOINTER *)&mdl_priv));
++ mdl_priv->kvaddr = gcvNULL;
++
++ mdl_priv->kvaddr = dma_alloc_writecombine(gcvNULL,
++ NumPages * PAGE_SIZE,
++ &mdl_priv->physical,
++ GFP_KERNEL | gcdNOWARN);
++
++ if (mdl_priv->kvaddr == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ Mdl->priv = mdl_priv;
++ priv->cmasize += NumPages * PAGE_SIZE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if(mdl_priv)
++ gckOS_Free(os, mdl_priv);
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_CMAFSLFree(
++ IN gckALLOCATOR Allocator,
++ IN OUT PLINUX_MDL Mdl
++ )
++{
++ gckOS os = Allocator->os;
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData;
++ dma_free_writecombine(gcvNULL,
++ Mdl->numPages * PAGE_SIZE,
++ mdl_priv->kvaddr,
++ mdl_priv->physical);
++ gckOS_Free(os, mdl_priv);
++ priv->cmasize -= Mdl->numPages * PAGE_SIZE;
++}
++
++gctINT
++_CMAFSLMapUser(
++ gckALLOCATOR Allocator,
++ PLINUX_MDL Mdl,
++ PLINUX_MDL_MAP MdlMap,
++ gctBOOL Cacheable
++ )
++{
++
++ PLINUX_MDL mdl = Mdl;
++ PLINUX_MDL_MAP mdlMap = MdlMap;
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++
++ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable);
++
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (dma_mmap_writecombine(gcvNULL,
++ mdlMap->vma,
++ mdl_priv->kvaddr,
++ mdl_priv->physical,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): dma_mmap_attrs error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ gckOS_Print("incorrect mdl:conti%d\n",mdl->contiguous);
++ }
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_CMAUnmapUser(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ )
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++}
++
++gceSTATUS
++_CMAMapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ )
++{
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ *Logical =mdl_priv->kvaddr;
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_CMAUnmapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++extern gceSTATUS
++_DefaultLogicalToPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ );
++
++extern gceSTATUS
++_DefaultCache(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++gceSTATUS
++_CMAPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ gcmkASSERT(!Offset);
++ *Physical = mdl_priv->physical;
++
++ return gcvSTATUS_OK;
++}
++
++
++extern void
++_DefaultAllocatorDestructor(
++ IN void* PrivateData
++ );
++
++/* Default allocator operations. */
++gcsALLOCATOR_OPERATIONS CMAFSLAllocatorOperations = {
++ .Alloc = _CMAFSLAlloc,
++ .Free = _CMAFSLFree,
++ .MapUser = _CMAFSLMapUser,
++ .UnmapUser = _CMAUnmapUser,
++ .MapKernel = _CMAMapKernel,
++ .UnmapKernel = _CMAUnmapKernel,
++ .LogicalToPhysical = _DefaultLogicalToPhysical,
++ .Cache = _DefaultCache,
++ .Physical = _CMAPhysical,
++};
++
++/* Default allocator entry. */
++gceSTATUS
++_CMAFSLAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++ gcsCMA_PRIV_PTR priv = gcvNULL;
++
++ gcmkONERROR(
++ gckALLOCATOR_Construct(Os, &CMAFSLAllocatorOperations, &allocator));
++
++ priv = kzalloc(gcmSIZEOF(gcsCMA_PRIV), GFP_KERNEL | gcdNOWARN);
++
++ if (!priv)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Register private data. */
++ allocator->privateData = priv;
++ allocator->privateDataDestructor = _DefaultAllocatorDestructor;
++
++ allocator->debugfsInit = _DefaultAllocatorDebugfsInit;
++ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup;
++
++ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS;
++
++ *Allocator = allocator;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.c linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_context.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_context.c 2016-06-19 22:11:55.125151817 +0200
+@@ -0,0 +1,2252 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++#include "gc_hal_kernel_buffer.h"
++
++/******************************************************************************\
++******************************** Debugging Macro *******************************
++\******************************************************************************/
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++
++/******************************************************************************\
++************************** Context State Buffer Helpers ************************
++\******************************************************************************/
++
++#define _STATE(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT(reg, count) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT_OFFSET(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_MIRROR_COUNT(reg, mirror, count) \
++ _StateMirror(\
++ Context, \
++ reg ## _Address >> 2, \
++ count, \
++ mirror ## _Address >> 2 \
++ )
++
++#define _STATE_HINT(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_HINT_BLOCK(reg, block, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + (block << reg ## _BLK), \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_COUNT_OFFSET_HINT(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_X(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvTRUE, gcvFALSE \
++ )
++
++#define _STATE_INIT_VALUE(reg, value) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ value, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _CLOSE_RANGE() \
++ _TerminateStateBlock(Context, index)
++
++#define _ENABLE(reg, field) \
++ do \
++ { \
++ if (gcmVERIFYFIELDVALUE(data, reg, MASK_ ## field, ENABLED)) \
++ { \
++ enable |= gcmFIELDMASK(reg, field); \
++ } \
++ } \
++ while (gcvFALSE)
++
++#define _BLOCK_COUNT(reg) \
++ ((reg ## _Count) >> (reg ## _BLK))
++
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++#define gcdSTATE_MASK \
++ (((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 | 0xC0FFEE & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))))
++
++#if gcdENABLE_3D
++static gctUINT32
++_TerminateStateBlock(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 align;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ /* Flush the current state block; make sure no pairing with the states
++ to follow happens. */
++ if (align && (buffer != gcvNULL))
++ {
++ buffer[Index] = 0xDEADDEAD;
++ }
++
++ /* Reset last address. */
++ Context->lastAddress = ~0U;
++
++ /* Return alignment requirement. */
++ return align;
++}
++#endif
++
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gctUINT32
++_FlushPipe(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ gctBOOL fcFlushStall;
++ gctUINT32 flushSlots;
++ gctBOOL iCacheInvalidate;
++
++ fcFlushStall
++ = gckHARDWARE_IsFeatureAvailable(Context->hardware, gcvFEATURE_FC_FLUSH_STALL);
++
++ iCacheInvalidate
++ = ((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ flushSlots = 6;
++
++ if (fcFlushStall)
++ {
++ /* Flush tile status cache. */
++ flushSlots += 6;
++ }
++
++ if (iCacheInvalidate)
++ {
++ flushSlots += 12;
++ }
++
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Flush the current pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ if (fcFlushStall)
++ {
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ if (iCacheInvalidate)
++ {
++ /* Invalidate I$ after pipe is stalled */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ }
++
++ /* Number of slots taken by flushing pipe. */
++ return flushSlots;
++}
++#endif
++
++#if gcdENABLE_3D
++static gctUINT32
++_SemaphoreStall(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ /* Semaphore/stall takes 4 slots. */
++ return 4;
++}
++#endif
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gctUINT32
++_SwitchPipe(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ gctUINT32 slots = 6;
++
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ Context->pipeSelectBytes = slots * gcmSIZEOF(gctUINT32);
++
++ return slots;
++}
++#endif
++
++#if gcdENABLE_3D
++static gctUINT32
++_State(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gctUINT32 Address,
++ IN gctUINT32 Value,
++ IN gctUINT32 Size,
++ IN gctBOOL FixedPoint,
++ IN gctBOOL Hinted
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 align;
++ gctUINT32 i;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ if ((buffer == gcvNULL) && (Address + Size > Context->stateCount))
++ {
++ /* Determine maximum state. */
++ Context->stateCount = Address + Size;
++ }
++
++ /* Do we need a new entry? */
++ if ((Address != Context->lastAddress) || (FixedPoint != Context->lastFixed))
++ {
++ if (buffer != gcvNULL)
++ {
++ if (align)
++ {
++ /* Add filler. */
++ buffer[Index++] = 0xDEADDEAD;
++ }
++
++ /* LoadState(Address, Count). */
++ gcmkASSERT((Index & 1) == 0);
++
++ if (FixedPoint)
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++ else
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ /* Walk all the states. */
++ for (i = 0; i < (gctUINT32)Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + 1 + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = (gctUINT)Index + 1 + i;
++ }
++ }
++
++ /* Save information for this LoadState. */
++ Context->lastIndex = (gctUINT)Index;
++ Context->lastAddress = Address + (gctUINT32)Size;
++ Context->lastSize = Size;
++ Context->lastFixed = FixedPoint;
++
++ /* Return size for load state. */
++ return align + 1 + Size;
++ }
++
++ /* Append this state to the previous one. */
++ if (buffer != gcvNULL)
++ {
++ /* Update last load state. */
++ buffer[Context->lastIndex] =
++ ((((gctUINT32) (buffer[Context->lastIndex])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Context->lastSize + Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Walk all the states. */
++ for (i = 0; i < (gctUINT32)Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = (gctUINT)Index + i;
++ }
++ }
++
++ /* Update last address and size. */
++ Context->lastAddress += (gctUINT32)Size;
++ Context->lastSize += Size;
++
++ /* Return number of slots required. */
++ return Size;
++}
++
++static gctUINT32
++_StateMirror(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Address,
++ IN gctUINT32 Size,
++ IN gctUINT32 AddressMirror
++ )
++{
++ gctUINT32 i;
++
++ /* Process when buffer is set. */
++ if (Context->buffer != gcvNULL)
++ {
++ /* Walk all states. */
++ for (i = 0; i < Size; i++)
++ {
++ /* Copy the mapping address. */
++ Context->map[Address + i].index =
++ Context->map[AddressMirror + i].index;
++ }
++ }
++
++ /* Return the number of required maps. */
++ return Size;
++}
++#endif
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gceSTATUS
++_InitializeContextBuffer(
++ IN gckCONTEXT Context
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 index;
++
++#if gcdENABLE_3D
++ gctBOOL halti0, halti1, halti2, halti3;
++ gctUINT i;
++ gctUINT vertexUniforms, fragmentUniforms, vsConstBase, psConstBase, constMax;
++ gctBOOL unifiedUniform;
++ gctUINT fe2vsCount;
++#endif
++
++ /* Reset the buffer index. */
++ index = 0;
++
++ /* Reset the last state address. */
++ Context->lastAddress = ~0U;
++
++ /* Get the buffer pointer. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++
++ /**************************************************************************/
++ /* Build 2D states. *******************************************************/
++
++
++#if gcdENABLE_3D
++ /**************************************************************************/
++ /* Build 3D states. *******************************************************/
++
++ halti0 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) );
++ halti1 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) );
++ halti2 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) );
++ halti3 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures5)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) );
++
++ /* Query how many uniforms can support for non-unified uniform mode. */
++ {if (Context->hardware->identity.numConstants > 256){ unifiedUniform = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; constMax = Context->hardware->identity.numConstants; vertexUniforms = 256; fragmentUniforms = constMax - vertexUniforms;}else if (Context->hardware->identity.numConstants == 256){ if (Context->hardware->identity.chipModel == gcv2000 && Context->hardware->identity.chipRevision == 0x5118) { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 64; constMax = 320; } else { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 256; constMax = 512; }}else{ unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 168; fragmentUniforms = 64; constMax = 232;}};
++
++#if !gcdENABLE_UNIFIED_CONSTANT
++ if (Context->hardware->identity.numConstants > 256)
++ {
++ unifiedUniform = gcvTRUE;
++ }
++ else
++ {
++ unifiedUniform = gcvFALSE;
++ }
++#endif
++
++ /* Store the 3D entry index. */
++ Context->entryOffset3D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Current context pointer. */
++#if DEBUG
++ index += _State(Context, index, 0x03850 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ index += _FlushPipe(Context, index, gcvPIPE_3D);
++
++ /* Global states. */
++ index += _State(Context, index, 0x03814 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03818 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0381C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03820 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03828 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0382C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03834 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03854 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0384C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Front End states. */
++ fe2vsCount = 12;
++ if (halti0)
++ {
++ fe2vsCount = 16;
++ }
++ index += _State(Context, index, 0x00600 >> 2, 0x00000000, fe2vsCount, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x00644 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00648 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0064C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00650 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00680 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x006A0 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0067C >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x006C0 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00700 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00740 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00780 >> 2, 0x3F800000, 16, gcvFALSE, gcvFALSE);
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x14600 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14640 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14680 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ }
++
++ /* This register is programed by all chips, which program all DECODE_SELECT as VS
++ ** except SAMPLER_DECODE_SELECT.
++ */
++ index += _State(Context, index, 0x00860 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ /* I-Cache states. */
++ index += _State(Context, index, 0x00868 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0086C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0304C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01028 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x00890 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0104C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++ }
++ }
++
++ /* Vertex Shader states. */
++ index += _State(Context, index, 0x00804 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00808 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0080C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00810 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00820 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00830 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++
++ /* Primitive Assembly states. */
++ index += _State(Context, index, 0x00A00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A0C >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A10 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A1C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A28 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A2C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A30 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A40 >> 2, 0x00000000, Context->hardware->identity.varyingsCount, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A34 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A38 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A3C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A80 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A8C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A88 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Setup states. */
++ index += _State(Context, index, 0x00C00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C08 >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C0C >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C10 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C1C >> 2, 0x42000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C20 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C24 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++
++ /* Raster states. */
++ index += _State(Context, index, 0x00E00 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E10 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E40 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E08 >> 2, 0x00000031, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E24 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E20 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x00E0C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ /* Pixel Shader states. */
++ index += _State(Context, index, 0x01004 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0100C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01010 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++
++ /* Texture states. */
++ index += _State(Context, index, 0x02000 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02040 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02080 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x020C0 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02100 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02140 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02180 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x021C0 >> 2, 0x00321000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02200 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02240 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x02400 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02440 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02480 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x024C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02500 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02540 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02580 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x025C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02600 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02640 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02680 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x026C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02700 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02740 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 22:22)) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) ))
++ {
++ /*
++ * Linear stride LODn will overwrite LOD0 on GC880,GC2000.
++ * And only LOD0 is valid for this register.
++ */
++ gctUINT count = halti1 ? 14 : 1;
++
++ for (i = 0; i < 12; i += 1)
++ {
++ index += _State(Context, index, (0x02C00 >> 2) + i * 16, 0x00000000, count, gcvFALSE, gcvFALSE);
++ }
++ }
++
++ if (halti1)
++ {
++ gctUINT texBlockCount;
++ gctUINT gcregTXLogSizeResetValue;
++
++ /* Enable the integer filter pipe for all texture samplers
++ so that the floating point filter clock will shut off until
++ we start using the floating point filter.
++ */
++ gcregTXLogSizeResetValue = ((((gctUINT32) (0x00000000)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29)));
++
++ /* New texture block. */
++ index += _State(Context, index, 0x10000 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10080 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10100 >> 2, gcregTXLogSizeResetValue, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10180 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10200 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10280 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10300 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10380 >> 2, 0x00321000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10400 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10480 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 15:15)) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x12000 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x12400 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ }
++
++ texBlockCount = ((512) >> (4));
++
++ for (i = 0; i < texBlockCount; i += 1)
++ {
++ index += _State(Context, index, (0x10800 >> 2) + (i << 4), 0x00000000, 14, gcvFALSE, gcvTRUE);
++ }
++ }
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x10700 >> 2, 0x00000F00, 32, gcvFALSE, gcvFALSE);
++ }
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x10780 >> 2, 0x00030000, 32, gcvFALSE, gcvFALSE);
++ }
++
++ /* ASTC */
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 13:13)) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x10500 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10580 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10600 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10680 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ }
++
++ /* YUV. */
++ index += _State(Context, index, 0x01678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0167C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01680 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01684 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01688 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0168C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01690 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01694 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01698 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0169C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* Thread walker states. */
++ index += _State(Context, index, 0x00900 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00904 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00908 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0090C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00910 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00914 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00918 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0091C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00924 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ index += _State(Context, index, 0x00940 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00944 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00948 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0094C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00950 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00954 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++
++ if (!halti3)
++ {
++ if (Context->hardware->identity.instructionCount > 1024)
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x20000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ else if (Context->hardware->identity.instructionCount > 256)
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* VX instruction memory. */
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x0C000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ _StateMirror(Context, 0x08000 >> 2, Context->hardware->identity.instructionCount << 2 , 0x0C000 >> 2);
++ }
++ else /* if (Context->hardware->identity.instructionCount <= 256) */
++ {
++ /* old shader instruction PC registers */
++ index += _State(Context, index, 0x00800 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x01000 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01018 >> 2, 0x01000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x04000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x06000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ /* I cache use the new instruction PC registers */
++ else
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ if (unifiedUniform)
++ {
++ gctINT numConstants = Context->hardware->identity.numConstants;
++
++ index += _State(Context, index, 0x01024 >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00864 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ numConstants > 0;
++ i += 256 << 2,
++ numConstants -= 256
++ )
++ {
++ if (numConstants >= 256)
++ {
++ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, numConstants << 2, gcvFALSE, gcvFALSE);
++ }
++ index += _CLOSE_RANGE();
++ }
++ }
++#if gcdENABLE_UNIFIED_CONSTANT
++ else
++#endif
++ {
++ index += _State(Context, index, 0x05000 >> 2, 0x00000000, vertexUniforms * 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x07000 >> 2, 0x00000000, fragmentUniforms * 4, gcvFALSE, gcvFALSE);
++ }
++
++ /* Store the index of the "XD" entry. */
++ Context->entryOffsetXDFrom3D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++
++ /* Pixel Engine states. */
++ index += _State(Context, index, 0x01400 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01404 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01408 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0140C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01414 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01418 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0141C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01420 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01424 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01428 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0142C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01434 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01454 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01458 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0145C >> 2, 0x00000010, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A8 >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014AC >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A4 >> 2, 0x000E400C, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01580 >> 2, 0x00000000, 3, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Composition states. */
++ index += _State(Context, index, 0x03008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (Context->hardware->identity.pixelPipes == 1)
++ {
++ index += _State(Context, index, 0x01460 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01430 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01410 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x01460 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ if (Context->hardware->identity.pixelPipes > 1 || halti0)
++ {
++ index += _State(Context, index, (0x01480 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ for (i = 0; i < 3; i++)
++ {
++ index += _State(Context, index, (0x01500 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ if (halti2)
++ {
++ for (i = 0; i < 7; i++)
++ {
++ index += _State(Context, index, (0x14800 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++ index += _State(Context, index, 0x14900 >> 2, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ }
++
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x014BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ /* Resolve states. */
++ index += _State(Context, index, 0x01604 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01608 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0160C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01610 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01614 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01620 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01630 >> 2, 0x00000000, 2, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01640 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0163C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if ((Context->hardware->identity.pixelPipes > 1) || halti1)
++ {
++ index += _State(Context, index, (0x016C0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, (0x016E0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01700 >> 2, 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvFALSE);
++ }
++
++#if gcd3DBLIT
++ index += _State(Context, index, (0x14000 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1400C >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14010 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14014 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x14018 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14020 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14024 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14028 >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1402C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14034 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14038 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1403C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14040 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14044 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14048 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1404C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14050 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14058 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1405C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14054 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14100 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14200 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14064 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14068 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _State(Context, index, 0x1406C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14070 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14074 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14078 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1407C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14080 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14084 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14088 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1408C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14090 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _State(Context, index, 0x14094 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14098 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ /* Tile status. */
++ index += _State(Context, index, 0x01654 >> 2, 0x00200000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x01658 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0165C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01660 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01664 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01668 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0166C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A4 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x016AC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01720 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01740 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01760 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x01780 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x017A0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x017C0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x017E0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x01A00 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x01A20 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x01A40 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++
++ if(((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 25:25) & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1))))))))
++ {
++ index += _State(Context, index, 0x03860 >> 2, 0x6, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x01A80 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++ }
++
++ /* Semaphore/stall. */
++ index += _SemaphoreStall(Context, index);
++#endif
++
++ /**************************************************************************/
++ /* Link to another address. ***********************************************/
++
++ Context->linkIndex3D = (gctUINT)index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++ /* Store the end of the context buffer. */
++ Context->bufferSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /**************************************************************************/
++ /* Pipe switch for the case where neither 2D nor 3D are used. *************/
++
++ /* Store the 3D entry index. */
++ Context->entryOffsetXDFrom2D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++ /* Flush 2D pipe. */
++ index += _FlushPipe(Context, index, gcvPIPE_2D);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Store the location of the link. */
++ Context->linkIndexXD = (gctUINT)index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++
++ /**************************************************************************/
++ /* Save size for buffer. **************************************************/
++
++ Context->totalSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++static gceSTATUS
++_DestroyContext(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ if (Context != gcvNULL)
++ {
++ gcsCONTEXT_PTR bufferHead;
++
++ /* Free context buffers. */
++ for (bufferHead = Context->buffer; Context->buffer != gcvNULL;)
++ {
++ /* Get a shortcut to the current buffer. */
++ gcsCONTEXT_PTR buffer = Context->buffer;
++
++ /* Get the next buffer. */
++ gcsCONTEXT_PTR next = buffer->next;
++
++ /* Last item? */
++ if (next == bufferHead)
++ {
++ next = gcvNULL;
++ }
++
++ /* Destroy the signal. */
++ if (buffer->signal != gcvNULL)
++ {
++ gcmkONERROR(gckOS_DestroySignal(
++ Context->os, buffer->signal
++ ));
++
++ buffer->signal = gcvNULL;
++ }
++
++ /* Free state delta map. */
++ if (buffer->logical != gcvNULL)
++ {
++ if (Context->hardware->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckEVENT_DestroyVirtualCommandBuffer(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckEVENT_FreeContiguousMemory(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++ }
++
++ buffer->logical = gcvNULL;
++ }
++
++ /* Free context buffer. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, buffer));
++
++ /* Remove from the list. */
++ Context->buffer = next;
++ }
++
++ /* Free record array copy. */
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (Context->recordArrayMap != gcvNULL)
++ {
++ gcsRECORD_ARRAY_MAP_PTR map = Context->recordArrayMap;
++
++ do
++ {
++ /* Free record array. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, map->kData));
++ map = map->next;
++ }
++ while (map != Context->recordArrayMap);
++
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArrayMap));
++ }
++#else
++ if (Context->recordArray != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArray));
++ }
++#endif
++
++ /* Free the state mapping. */
++ if (Context->map != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->map));
++ }
++
++ /* Mark the gckCONTEXT object as unknown. */
++ Context->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCONTEXT object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context));
++ }
++
++OnError:
++ return status;
++}
++
++
++/******************************************************************************\
++**************************** Context Management API ****************************
++\******************************************************************************/
++
++/******************************************************************************\
++**
++** gckCONTEXT_Construct
++**
++** Construct a new gckCONTEXT object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gckHARDWARE Hardware
++** Pointer to gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable thet will receive the gckCONTEXT object
++** pointer.
++*/
++#if (gcdENABLE_3D || gcdENABLE_2D)
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gctUINT32 allocationSize;
++ gctUINT i;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Os=0x%08X Hardware=0x%08X", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++
++
++ /**************************************************************************/
++ /* Allocate and initialize basic fields of gckCONTEXT. ********************/
++
++ /* The context object size. */
++ allocationSize = gcmSIZEOF(struct _gckCONTEXT);
++
++ /* Allocate the object. */
++ gcmkONERROR(gckOS_Allocate(
++ Os, allocationSize, &pointer
++ ));
++
++ context = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(context, allocationSize));
++
++ /* Initialize the gckCONTEXT object. */
++ context->object.type = gcvOBJ_CONTEXT;
++ context->os = Os;
++ context->hardware = Hardware;
++
++
++#if !gcdENABLE_3D
++ context->entryPipe = gcvPIPE_2D;
++ context->exitPipe = gcvPIPE_2D;
++#elif gcdCMD_NO_2D_CONTEXT
++ context->entryPipe = gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#else
++ context->entryPipe
++ = (((((gctUINT32) (context->hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) )
++ ? gcvPIPE_2D
++ : gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#endif
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Hardware,
++ &context->alignment,
++ &context->reservedHead,
++ &context->reservedTail
++ ));
++
++ /* Mark the context as dirty to force loading of the entire state table
++ the first time. */
++ context->dirty = gcvTRUE;
++
++
++ /**************************************************************************/
++ /* Get the size of the context buffer. ************************************/
++
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++
++ /**************************************************************************/
++ /* Compute the size of the record array. **********************************/
++
++ context->recordArraySize
++ = gcmSIZEOF(gcsSTATE_DELTA_RECORD) * (gctUINT)context->stateCount;
++
++
++ if (context->stateCount > 0)
++ {
++ /**************************************************************************/
++ /* Allocate and reset the state mapping table. ****************************/
++
++ /* Allocate the state mapping table. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsSTATE_MAP) * context->stateCount,
++ &pointer
++ ));
++
++ context->map = pointer;
++
++ /* Zero the state mapping table. */
++ gcmkONERROR(gckOS_ZeroMemory(
++ context->map, gcmSIZEOF(gcsSTATE_MAP) * context->stateCount
++ ));
++ }
++
++ /**************************************************************************/
++ /* Allocate the context and state delta buffers. **************************/
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i += 1)
++ {
++ /* Allocate a context buffer. */
++ gcsCONTEXT_PTR buffer;
++
++ gctSIZE_T totalSize = context->totalSize;
++
++ /* Allocate the context buffer structure. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsCONTEXT),
++ &pointer
++ ));
++
++ buffer = pointer;
++
++ /* Reset the context buffer structure. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ buffer, gcmSIZEOF(gcsCONTEXT)
++ ));
++
++ /* Append to the list. */
++ if (context->buffer == gcvNULL)
++ {
++ buffer->next = buffer;
++ context->buffer = buffer;
++ }
++ else
++ {
++ buffer->next = context->buffer->next;
++ context->buffer->next = buffer;
++ }
++
++ /* Set the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ buffer->num = i;
++#endif
++
++ /* Create the busy signal. */
++ gcmkONERROR(gckOS_CreateSignal(
++ Os, gcvFALSE, &buffer->signal
++ ));
++
++ /* Set the signal, buffer is currently not busy. */
++ gcmkONERROR(gckOS_Signal(
++ Os, buffer->signal, gcvTRUE
++ ));
++
++ /* Create a new physical context buffer. */
++ if (context->hardware->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckKERNEL_AllocateVirtualCommandBuffer(
++ context->hardware->kernel,
++ gcvFALSE,
++ &totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++ gcmkONERROR(gckKERNEL_GetGPUAddress(
++ context->hardware->kernel,
++ pointer,
++ gcvFALSE,
++ &address
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Os,
++ gcvFALSE,
++ &totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ context->hardware,
++ pointer,
++ gcvFALSE,
++ &address
++ ));
++ }
++
++ buffer->logical = pointer;
++ buffer->address = address;
++
++ /* Set gckEVENT object pointer. */
++ buffer->eventObj = Hardware->kernel->eventObj;
++
++ /* Set the pointers to the LINK commands. */
++ if (context->linkIndex2D != 0)
++ {
++ buffer->link2D = &buffer->logical[context->linkIndex2D];
++ }
++
++ if (context->linkIndex3D != 0)
++ {
++ buffer->link3D = &buffer->logical[context->linkIndex3D];
++ }
++
++ if (context->linkIndexXD != 0)
++ {
++ gctPOINTER xdLink;
++ gctUINT32 xdEntryAddress;
++ gctUINT32 xdEntrySize;
++ gctUINT32 linkBytes;
++
++ /* Determine LINK parameters. */
++ xdLink
++ = &buffer->logical[context->linkIndexXD];
++
++ xdEntryAddress
++ = buffer->address
++ + context->entryOffsetXDFrom3D;
++
++ xdEntrySize
++ = context->bufferSize
++ - context->entryOffsetXDFrom3D;
++
++ /* Query LINK size. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware, gcvNULL, 0, 0, &linkBytes
++ ));
++
++ /* Generate a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware,
++ xdLink,
++ xdEntryAddress,
++ xdEntrySize,
++ &linkBytes
++ ));
++ }
++ }
++
++
++ /**************************************************************************/
++ /* Initialize the context buffers. ****************************************/
++
++ /* Initialize the current context buffer. */
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++ /* Make all created contexts equal. */
++ {
++ gcsCONTEXT_PTR currContext, tempContext;
++
++ /* Set the current context buffer. */
++ currContext = context->buffer;
++
++ /* Get the next context buffer. */
++ tempContext = currContext->next;
++
++ /* Loop through all buffers. */
++ while (tempContext != currContext)
++ {
++ if (tempContext == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ /* Copy the current context. */
++ gckOS_MemCopy(
++ tempContext->logical,
++ currContext->logical,
++ context->totalSize
++ );
++
++ /* Get the next context buffer. */
++ tempContext = tempContext->next;
++ }
++ }
++
++ /* Return pointer to the gckCONTEXT object. */
++ *Context = context;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%08X", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back on error. */
++ gcmkVERIFY_OK(_DestroyContext(context));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/******************************************************************************\
++**
++** gckCONTEXT_Destroy
++**
++** Destroy a gckCONTEXT object.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Context=0x%08X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Destroy the context and all related objects. */
++ status = _DestroyContext(Context);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/******************************************************************************\
++**
++** gckCONTEXT_Update
++**
++** Merge all pending state delta buffers into the current context buffer.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ )
++{
++#if gcdENABLE_3D
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSTATE_DELTA _stateDelta;
++ gckKERNEL kernel;
++ gcsCONTEXT_PTR buffer;
++ gcsSTATE_MAP_PTR map;
++ gctBOOL needCopy = gcvFALSE;
++ gcsSTATE_DELTA_PTR nDelta;
++ gcsSTATE_DELTA_PTR uDelta = gcvNULL;
++ gcsSTATE_DELTA_PTR kDelta = gcvNULL;
++ gcsSTATE_DELTA_RECORD_PTR record;
++ gcsSTATE_DELTA_RECORD_PTR recordArray = gcvNULL;
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ gcsRECORD_ARRAY_MAP_PTR recordArrayMap = gcvNULL;
++#endif
++ gctUINT elementCount;
++ gctUINT address;
++ gctUINT32 mask;
++ gctUINT32 data;
++ gctUINT index;
++ gctUINT i, j;
++
++ gcmkHEADER_ARG(
++ "Context=0x%08X ProcessID=%d StateDelta=0x%08X",
++ Context, ProcessID, StateDelta
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Get a shortcut to the kernel object. */
++ kernel = Context->hardware->kernel;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Context->os, ProcessID, &needCopy));
++
++ /* Allocate the copy buffer for the user record array. */
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy && (Context->recordArrayMap == gcvNULL))
++ {
++ /* Allocate enough maps. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ gcmSIZEOF(gcsRECORD_ARRAY_MAP_PTR) * gcdCONTEXT_BUFFER_COUNT,
++ (gctPOINTER *) &Context->recordArrayMap
++ ));
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++)
++ {
++ /* Next mapping id. */
++ gctUINT n = (i + 1) % gcdCONTEXT_BUFFER_COUNT;
++
++ recordArrayMap = &Context->recordArrayMap[i];
++
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &recordArrayMap->kData
++ ));
++
++ /* Initialize fields. */
++ recordArrayMap->key = 0;
++ recordArrayMap->next = &Context->recordArrayMap[n];
++ }
++ }
++#else
++ if (needCopy && (Context->recordArray == gcvNULL))
++ {
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &Context->recordArray
++ ));
++ }
++#endif
++
++ /* Get the current context buffer. */
++ buffer = Context->buffer;
++
++ /* Wait until the context buffer becomes available; this will
++ also reset the signal and mark the buffer as busy. */
++ gcmkONERROR(gckOS_WaitSignal(
++ Context->os, buffer->signal, gcvINFINITE
++ ));
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE) && 1 && gcdENABLE_3D
++ /* Update current context token. */
++ buffer->logical[Context->map[0x0E14].index]
++ = (gctUINT32)gcmPTR2INT32(Context);
++#endif
++
++ /* Are there any pending deltas? */
++ if (buffer->deltaCount != 0)
++ {
++ /* Get the state map. */
++ map = Context->map;
++
++ /* Get the first delta item. */
++ uDelta = buffer->delta;
++
++ /* Reset the vertex stream count. */
++ elementCount = 0;
++
++ /* Merge all pending deltas. */
++ for (i = 0; i < buffer->deltaCount; i += 1)
++ {
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy)
++ {
++ recordArray = gcvNULL;
++ recordArrayMap = Context->recordArrayMap;
++
++ do
++ {
++ /* Check if recordArray is alreay opened. */
++ if (recordArrayMap->key == kDelta->recordArray)
++ {
++ /* Found. */
++ recordArray = recordArrayMap->kData;
++ break;
++ }
++
++ recordArrayMap = recordArrayMap->next;
++ }
++ while (recordArrayMap != Context->recordArrayMap);
++
++ if (recordArray == gcvNULL)
++ {
++ while (recordArrayMap->key != 0)
++ {
++ /* Found an empty slot. */
++ recordArrayMap = recordArrayMap->next;
++ }
++
++ /* Get access to the state records. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ kernel->os,
++ recordArrayMap->kData,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize
++ ));
++
++ /* Save user pointer as key. */
++ recordArrayMap->key = kDelta->recordArray;
++ recordArray = recordArrayMap->kData;
++ }
++ }
++ else
++ {
++ /* Get access to the state records. */
++ gcmkONERROR(gckOS_MapUserPointer(
++ kernel->os,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++#else
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ Context->recordArray,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++#endif
++
++ /* Merge all pending states. */
++ for (j = 0; j < kDelta->recordCount; j += 1)
++ {
++ if (j >= Context->stateCount)
++ {
++ break;
++ }
++
++ /* Get the current state record. */
++ record = &recordArray[j];
++
++ /* Get the state address. */
++ address = record->address;
++
++ /* Make sure the state is a part of the mapping table. */
++ if (address >= Context->stateCount)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): State 0x%04X is not mapped.\n",
++ __FUNCTION__, __LINE__,
++ address
++ );
++
++ continue;
++ }
++
++ /* Get the state index. */
++ index = map[address].index;
++
++ /* Skip the state if not mapped. */
++ if (index == 0)
++ {
++ continue;
++ }
++
++ /* Get the data mask. */
++ mask = record->mask;
++
++ /* Masked states that are being completly reset or regular states. */
++ if ((mask == 0) || (mask == ~0U))
++ {
++ /* Get the new data value. */
++ data = record->data;
++
++ /* Process special states. */
++ if (address == 0x0595)
++ {
++ /* Force auto-disable to be disabled. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13)));
++ }
++
++ /* Set new data. */
++ buffer->logical[index] = data;
++ }
++
++ /* Masked states that are being set partially. */
++ else
++ {
++ buffer->logical[index]
++ = (~mask & buffer->logical[index])
++ | (mask & record->data);
++ }
++ }
++
++ /* Get the element count. */
++ if (kDelta->elementCount != 0)
++ {
++ elementCount = kDelta->elementCount;
++ }
++
++ /* Dereference delta. */
++ kDelta->refCount -= 1;
++ gcmkASSERT(kDelta->refCount >= 0);
++
++ /* Get the next state delta. */
++ nDelta = gcmUINT64_TO_PTR(kDelta->next);
++
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy)
++ {
++ if (kDelta->refCount == 0)
++ {
++ /* No other reference, reset the mapping. */
++ recordArrayMap->key = 0;
++ }
++ }
++ else
++ {
++ /* Close access to the state records. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ kernel->os,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize,
++ (gctPOINTER *) recordArray
++ ));
++
++ recordArray = gcvNULL;
++ }
++#else
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++#endif
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Update the user delta pointer. */
++ uDelta = nDelta;
++ }
++
++ /* Hardware disables all input streams when the stream 0 is programmed,
++ it then reenables those streams that were explicitely programmed by
++ the software. Because of this we cannot program the entire array of
++ values, otherwise we'll get all streams reenabled, but rather program
++ only those that are actully needed by the software. */
++ if (elementCount != 0)
++ {
++ gctUINT base;
++ gctUINT nopCount;
++ gctUINT32_PTR nop;
++ gctUINT fe2vsCount = 12;
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ))
++ {
++ fe2vsCount = 16;
++ }
++
++ /* Determine the base index of the vertex stream array. */
++ base = map[0x0180].index;
++
++ /* Set the proper state count. */
++ buffer->logical[base - 1]
++ = ((((gctUINT32) (buffer->logical[base - 1])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (elementCount ) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine the number of NOP commands. */
++ nopCount
++ = (fe2vsCount / 2)
++ - (elementCount / 2);
++
++ /* Determine the location of the first NOP. */
++ nop = &buffer->logical[base + (elementCount | 1)];
++
++ if ((nop + (nopCount * 2)) >= buffer->logical + Context->totalSize)
++ nopCount = (buffer->logical + Context->totalSize - nop) / 2;
++
++ /* Fill the unused space with NOPs. */
++ for (i = 0; i < nopCount; i += 1)
++ {
++ /* Generate a NOP command. */
++ *nop = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ /* Advance. */
++ nop += 2;
++ }
++ }
++
++ /* Reset pending deltas. */
++ buffer->deltaCount = 0;
++ buffer->delta = gcvNULL;
++ }
++
++ /* Set state delta user pointer. */
++ uDelta = StateDelta;
++
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* State delta cannot be attached to anything yet. */
++ if (kDelta->refCount != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): kDelta->refCount = %d (has to be 0).\n",
++ __FUNCTION__, __LINE__,
++ kDelta->refCount
++ );
++ }
++
++ /* Attach to all contexts. */
++ buffer = Context->buffer;
++
++ do
++ {
++ /* Attach to the context if nothing is attached yet. If a delta
++ is allready attached, all we need to do is to increment
++ the number of deltas in the context. */
++ if (buffer->delta == gcvNULL)
++ {
++ buffer->delta = uDelta;
++ }
++
++ /* Update reference count. */
++ kDelta->refCount += 1;
++
++ /* Update counters. */
++ buffer->deltaCount += 1;
++
++ /* Get the next context buffer. */
++ buffer = buffer->next;
++
++ if (buffer == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++ }
++ while (Context->buffer != buffer);
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Schedule an event to mark the context buffer as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ buffer->eventObj, buffer->signal, gcvKERNEL_PIXEL
++ ));
++
++ /* Advance to the next context buffer. */
++ Context->buffer = buffer->next;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Get access to the state records. */
++ if (kDelta != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++
++ /* Close access to the current state delta. */
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++gceSTATUS
++gckCONTEXT_MapBuffer(
++ IN gckCONTEXT Context,
++ OUT gctUINT32 *Physicals,
++ OUT gctUINT64 *Logicals,
++ OUT gctUINT32 *Bytes
++ )
++{
++ gceSTATUS status;
++ int i = 0;
++ gctSIZE_T pageCount;
++ gckVIRTUAL_COMMAND_BUFFER_PTR commandBuffer;
++ gckKERNEL kernel = Context->hardware->kernel;
++ gctPOINTER logical;
++ gctPHYS_ADDR physical;
++
++ gcsCONTEXT_PTR buffer;
++
++ gcmkHEADER();
++
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ buffer = Context->buffer;
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++)
++ {
++ if (kernel->virtualCommandBuffer)
++ {
++ commandBuffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)buffer->physical;
++ physical = commandBuffer->physical;
++
++ gcmkONERROR(gckOS_CreateUserVirtualMapping(
++ kernel->os,
++ physical,
++ Context->totalSize,
++ &logical,
++ &pageCount));
++ }
++ else
++ {
++ physical = buffer->physical;
++
++ gcmkONERROR(gckOS_MapMemory(
++ kernel->os,
++ physical,
++ Context->totalSize,
++ &logical));
++ }
++
++ Physicals[i] = gcmPTR_TO_NAME(physical);
++
++ Logicals[i] = gcmPTR_TO_UINT64(logical);
++
++ buffer = buffer->next;
++ }
++
++ *Bytes = (gctUINT)Context->totalSize;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.h linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_context.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_context.h 2016-06-19 22:11:55.125151817 +0200
+@@ -0,0 +1,178 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_context_h_
++#define __gc_hal_kernel_context_h_
++
++#include "gc_hal_kernel_buffer.h"
++
++/* Exprimental optimization. */
++#define REMOVE_DUPLICATED_COPY_FROM_USER 1
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Maps state locations within the context buffer. */
++typedef struct _gcsSTATE_MAP * gcsSTATE_MAP_PTR;
++typedef struct _gcsSTATE_MAP
++{
++ /* Index of the state in the context buffer. */
++ gctUINT index;
++
++ /* State mask. */
++ gctUINT32 mask;
++}
++gcsSTATE_MAP;
++
++/* Context buffer. */
++typedef struct _gcsCONTEXT * gcsCONTEXT_PTR;
++typedef struct _gcsCONTEXT
++{
++ /* For debugging: the number of context buffer in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Context busy signal. */
++ gctSIGNAL signal;
++
++ /* Physical address of the context buffer. */
++ gctPHYS_ADDR physical;
++
++ /* Logical address of the context buffer. */
++ gctUINT32_PTR logical;
++
++ /* Hardware address of the context buffer. */
++ gctUINT32 address;
++
++ /* Pointer to the LINK commands. */
++ gctPOINTER link2D;
++ gctPOINTER link3D;
++
++ /* The number of pending state deltas. */
++ gctUINT deltaCount;
++
++ /* Pointer to the first delta to be applied. */
++ gcsSTATE_DELTA_PTR delta;
++
++ /* Next context buffer. */
++ gcsCONTEXT_PTR next;
++}
++gcsCONTEXT;
++
++typedef struct _gcsRECORD_ARRAY_MAP * gcsRECORD_ARRAY_MAP_PTR;
++struct _gcsRECORD_ARRAY_MAP
++{
++ /* User pointer key. */
++ gctUINT64 key;
++
++ /* Kernel memory buffer. */
++ gcsSTATE_DELTA_RECORD_PTR kData;
++
++ /* Next map. */
++ gcsRECORD_ARRAY_MAP_PTR next;
++
++};
++
++/* gckCONTEXT structure that hold the current context. */
++struct _gckCONTEXT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Command buffer alignment. */
++ gctUINT32 alignment;
++ gctUINT32 reservedHead;
++ gctUINT32 reservedTail;
++
++ /* Context buffer metrics. */
++ gctSIZE_T stateCount;
++ gctUINT32 totalSize;
++ gctUINT32 bufferSize;
++ gctUINT32 linkIndex2D;
++ gctUINT32 linkIndex3D;
++ gctUINT32 linkIndexXD;
++ gctUINT32 entryOffset3D;
++ gctUINT32 entryOffsetXDFrom2D;
++ gctUINT32 entryOffsetXDFrom3D;
++
++ /* Dirty flags. */
++ gctBOOL dirty;
++ gctBOOL dirty2D;
++ gctBOOL dirty3D;
++ gcsCONTEXT_PTR dirtyBuffer;
++
++ /* State mapping. */
++ gcsSTATE_MAP_PTR map;
++
++ /* List of context buffers. */
++ gcsCONTEXT_PTR buffer;
++
++ /* A copy of the user record array. */
++ gctUINT recordArraySize;
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ gcsRECORD_ARRAY_MAP_PTR recordArrayMap;
++#else
++ gcsSTATE_DELTA_RECORD_PTR recordArray;
++#endif
++
++ /* Requested pipe select for context. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Variables used for building state buffer. */
++ gctUINT32 lastAddress;
++ gctSIZE_T lastSize;
++ gctUINT32 lastIndex;
++ gctBOOL lastFixed;
++
++ gctUINT32 pipeSelectBytes;
++
++#if VIVANTE_PROFILER_CONTEXT
++ gcsPROFILER_COUNTERS latestProfiler;
++ gcsPROFILER_COUNTERS histroyProfiler;
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++#endif
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_context_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c 2016-06-19 22:11:55.129151555 +0200
+@@ -0,0 +1,7719 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#if VIVANTE_PROFILER_CONTEXT
++#include "gc_hal_kernel_context.h"
++#endif
++
++#define gcdDISABLE_FE_L2 1
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++#define gcmSEMAPHORESTALL(buffer) \
++ do \
++ { \
++ /* Arm the PE-FE Semaphore. */ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, 1) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, 0x0E02); \
++ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END) \
++ | gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE);\
++ \
++ /* STALL FE until PE is done flushing. */ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \
++ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, STALL_STALL, SOURCE, FRONT_END) \
++ | gcmSETFIELDVALUE(0, STALL_STALL, DESTINATION, PIXEL_ENGINE); \
++ } while(0)
++
++typedef struct _gcsiDEBUG_REGISTERS * gcsiDEBUG_REGISTERS_PTR;
++typedef struct _gcsiDEBUG_REGISTERS
++{
++ gctSTRING module;
++ gctUINT index;
++ gctUINT shift;
++ gctUINT data;
++ gctUINT count;
++ gctUINT32 signature;
++}
++gcsiDEBUG_REGISTERS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gctBOOL
++_IsHardwareMatch(
++ IN gckHARDWARE Hardware,
++ IN gctINT32 ChipModel,
++ IN gctUINT32 ChipRevision
++ )
++{
++ return ((Hardware->identity.chipModel == ChipModel) &&
++ (Hardware->identity.chipRevision == ChipRevision));
++}
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gceSTATUS status;
++
++ gctUINT32 chipIdentity;
++
++ gctUINT32 streamCount = 0;
++ gctUINT32 registerMax = 0;
++ gctUINT32 threadCount = 0;
++ gctUINT32 shaderCoreCount = 0;
++ gctUINT32 vertexCacheSize = 0;
++ gctUINT32 vertexOutputBufferSize = 0;
++ gctUINT32 pixelPipes = 0;
++ gctUINT32 instructionCount = 0;
++ gctUINT32 numConstants = 0;
++ gctUINT32 bufferSize = 0;
++ gctUINT32 varyingsCount = 0;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /***************************************************************************
++ ** Get chip ID and revision.
++ */
++
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00018,
++ &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ Identity->chipModel = gcv500;
++ Identity->chipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00020,
++ (gctUINT32_PTR) &Identity->chipModel));
++
++ if (((Identity->chipModel & 0xFF00) == 0x0400)
++ && (Identity->chipModel != 0x0420)
++ && (Identity->chipModel != 0x0428))
++ {
++ Identity->chipModel = (gceCHIPMODEL) (Identity->chipModel & 0x0400);
++ }
++
++ /* Read CHIP_REV register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00024,
++ &Identity->chipRevision));
++
++ if ((Identity->chipModel == gcv300)
++ && (Identity->chipRevision == 0x2201)
++ )
++ {
++ gctUINT32 chipDate;
++ gctUINT32 chipTime;
++
++ /* Read date and time registers. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00028,
++ &chipDate));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0002C,
++ &chipTime));
++
++ if ((chipDate == 0x20080814) && (chipTime == 0x12051100))
++ {
++ /* This IP has an ECO; put the correct revision in it. */
++ Identity->chipRevision = 0x1051;
++ }
++ }
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x000A8,
++ &Identity->productID));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipModel=%X",
++ Identity->chipModel);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipRevision=%X",
++ Identity->chipRevision);
++
++
++ /***************************************************************************
++ ** Get chip features.
++ */
++
++ /* Read chip feature register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0001C,
++ &Identity->chipFeatures));
++
++#if gcdENABLE_3D
++ /* Disable fast clear on GC700. */
++ if (Identity->chipModel == gcv700)
++ {
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++#endif
++
++ if (((Identity->chipModel == gcv500) && (Identity->chipRevision < 2))
++ || ((Identity->chipModel == gcv300) && (Identity->chipRevision < 0x2000))
++ )
++ {
++ /* GC500 rev 1.x and GC300 rev < 2.0 doesn't have these registers. */
++ Identity->chipMinorFeatures = 0;
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ Identity->chipMinorFeatures5 = 0;
++ }
++ else
++ {
++ /* Read chip minor feature register #0. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00034,
++ &Identity->chipMinorFeatures));
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))
++ )
++ {
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00074,
++ &Identity->chipMinorFeatures1));
++
++ /* Read chip minor featuress register #2. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00084,
++ &Identity->chipMinorFeatures2));
++
++ /*Identity->chipMinorFeatures2 &= ~(0x1 << 3);*/
++
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00088,
++ &Identity->chipMinorFeatures3));
++
++
++ /* Read chip minor featuress register #4. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00094,
++ &Identity->chipMinorFeatures4));
++
++ /* Read chip minor featuress register #5. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x000A0,
++ &Identity->chipMinorFeatures5));
++ }
++ else
++ {
++ /* Chip doesn't has minor features register #1 or 2 or 3 or 4. */
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ Identity->chipMinorFeatures5 = 0;
++ }
++ }
++
++ /* Get the Supertile layout in the hardware. */
++ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
++ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))))
++ {
++ Identity->superTileMode = 2;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))))
++ {
++ Identity->superTileMode = 1;
++ }
++ else
++ {
++ Identity->superTileMode = 0;
++ }
++
++ /* Exception for GC1000, revision 5035 & GC800, revision 4612 */
++ if (((Identity->chipModel == gcv1000) && ((Identity->chipRevision == 0x5035)
++ || (Identity->chipRevision == 0x5036)
++ || (Identity->chipRevision == 0x5037)
++ || (Identity->chipRevision == 0x5039)
++ || (Identity->chipRevision >= 0x5040)))
++ || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612))
++ || ((Identity->chipModel == gcv600) && (Identity->chipRevision >= 0x4650))
++ || ((Identity->chipModel == gcv860) && (Identity->chipRevision == 0x4647))
++ || ((Identity->chipModel == gcv400) && (Identity->chipRevision >= 0x4633)))
++ {
++ Identity->superTileMode = 1;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipFeatures=0x%08X",
++ Identity->chipFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures=0x%08X",
++ Identity->chipMinorFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures1=0x%08X",
++ Identity->chipMinorFeatures1);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures2=0x%08X",
++ Identity->chipMinorFeatures2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures3=0x%08X",
++ Identity->chipMinorFeatures3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures4=0x%08X",
++ Identity->chipMinorFeatures4);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures5=0x%08X",
++ Identity->chipMinorFeatures5);
++
++ /***************************************************************************
++ ** Get chip specs.
++ */
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ gctUINT32 specs, specs2, specs3, specs4;
++
++ /* Read gcChipSpecs register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00048,
++ &specs));
++
++ /* Extract the fields. */
++ registerMax = (((((gctUINT32) (specs)) >> (0 ? 7:4)) & ((gctUINT32) ((((1 ? 7:4) - (0 ? 7:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:4) - (0 ? 7:4) + 1)))))) );
++ threadCount = (((((gctUINT32) (specs)) >> (0 ? 11:8)) & ((gctUINT32) ((((1 ? 11:8) - (0 ? 11:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:8) - (0 ? 11:8) + 1)))))) );
++ shaderCoreCount = (((((gctUINT32) (specs)) >> (0 ? 24:20)) & ((gctUINT32) ((((1 ? 24:20) - (0 ? 24:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:20) - (0 ? 24:20) + 1)))))) );
++ vertexCacheSize = (((((gctUINT32) (specs)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ vertexOutputBufferSize = (((((gctUINT32) (specs)) >> (0 ? 31:28)) & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1)))))) );
++ pixelPipes = (((((gctUINT32) (specs)) >> (0 ? 27:25)) & ((gctUINT32) ((((1 ? 27:25) - (0 ? 27:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:25) - (0 ? 27:25) + 1)))))) );
++
++ /* Read gcChipSpecs2 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00080,
++ &specs2));
++
++ instructionCount = (((((gctUINT32) (specs2)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ numConstants = (((((gctUINT32) (specs2)) >> (0 ? 31:16)) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1)))))) );
++ bufferSize = (((((gctUINT32) (specs2)) >> (0 ? 7:0)) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1)))))) );
++
++ /* Read gcChipSpecs3 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0008C,
++ &specs3));
++
++ varyingsCount = (((((gctUINT32) (specs3)) >> (0 ? 8:4)) & ((gctUINT32) ((((1 ? 8:4) - (0 ? 8:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:4) - (0 ? 8:4) + 1)))))) );
++
++ /* Read gcChipSpecs4 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0009C,
++ &specs4));
++
++
++ streamCount = (((((gctUINT32) (specs4)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ if (streamCount == 0)
++ {
++ /* Extract stream count from older register. */
++ streamCount = (((((gctUINT32) (specs)) >> (0 ? 3:0)) & ((gctUINT32) ((((1 ? 3:0) - (0 ? 3:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:0) - (0 ? 3:0) + 1)))))) );
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs1=0x%08X",
++ specs);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs2=0x%08X",
++ specs2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs3=0x%08X",
++ specs3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs4=0x%08X",
++ specs4);
++ }
++
++ /* Get the number of pixel pipes. */
++ Identity->pixelPipes = gcmMAX(pixelPipes, 1);
++
++ /* Get the stream count. */
++ Identity->streamCount = (streamCount != 0)
++ ? streamCount
++ : (Identity->chipModel >= gcv1000) ? 4 : 1;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: streamCount=%u%s",
++ Identity->streamCount,
++ (streamCount == 0) ? " (default)" : "");
++
++ /* Get the vertex output buffer size. */
++ Identity->vertexOutputBufferSize = (vertexOutputBufferSize != 0)
++ ? 1 << vertexOutputBufferSize
++ : (Identity->chipModel == gcv400)
++ ? (Identity->chipRevision < 0x4000) ? 512
++ : (Identity->chipRevision < 0x4200) ? 256
++ : 128
++ : (Identity->chipModel == gcv530)
++ ? (Identity->chipRevision < 0x4200) ? 512
++ : 128
++ : 512;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexOutputBufferSize=%u%s",
++ Identity->vertexOutputBufferSize,
++ (vertexOutputBufferSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of threads. */
++ Identity->threadCount = (threadCount != 0)
++ ? 1 << threadCount
++ : (Identity->chipModel == gcv400) ? 64
++ : (Identity->chipModel == gcv500) ? 128
++ : (Identity->chipModel == gcv530) ? 128
++ : 256;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: threadCount=%u%s",
++ Identity->threadCount,
++ (threadCount == 0) ? " (default)" : "");
++
++ /* Get the number of shader cores. */
++ Identity->shaderCoreCount = (shaderCoreCount != 0)
++ ? shaderCoreCount
++ : (Identity->chipModel >= gcv1000) ? 2
++ : 1;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: shaderCoreCount=%u%s",
++ Identity->shaderCoreCount,
++ (shaderCoreCount == 0) ? " (default)" : "");
++
++ /* Get the vertex cache size. */
++ Identity->vertexCacheSize = (vertexCacheSize != 0)
++ ? vertexCacheSize
++ : 8;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexCacheSize=%u%s",
++ Identity->vertexCacheSize,
++ (vertexCacheSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of temporary registers. */
++ Identity->registerMax = (registerMax != 0)
++ /* Maximum of registerMax/4 registers are accessible to 1 shader */
++ ? 1 << registerMax
++ : (Identity->chipModel == gcv400) ? 32
++ : 64;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: registerMax=%u%s",
++ Identity->registerMax,
++ (registerMax == 0) ? " (default)" : "");
++
++ /* Get the instruction count. */
++ Identity->instructionCount = (instructionCount == 0) ? 256
++ : (instructionCount == 1) ? 1024
++ : (instructionCount == 2) ? 2048
++ : (instructionCount == 0xFF) ? 512
++ : 256;
++
++ if (Identity->instructionCount == 256)
++ {
++ if ((Identity->chipModel == gcv2000 && Identity->chipRevision == 0x5108)
++ || Identity->chipModel == gcv880)
++ {
++ Identity->instructionCount = 512;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ Identity->instructionCount = 512;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: instructionCount=%u%s",
++ Identity->instructionCount,
++ (instructionCount == 0) ? " (default)" : "");
++
++ /* Get the number of constants. */
++ Identity->numConstants = (numConstants == 0) ? 168 : numConstants;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: numConstants=%u%s",
++ Identity->numConstants,
++ (numConstants == 0) ? " (default)" : "");
++
++ /* Get the buffer size. */
++ Identity->bufferSize = bufferSize;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: bufferSize=%u%s",
++ Identity->bufferSize,
++ (bufferSize == 0) ? " (default)" : "");
++
++
++ if (varyingsCount != 0)
++ {
++ Identity->varyingsCount = varyingsCount;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures1)) >> (0 ? 23:23) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))))
++ {
++ Identity->varyingsCount = 12;
++ }
++ else
++ {
++ Identity->varyingsCount = 8;
++ }
++
++ /* For some cores, it consumes two varying for position, so the max varying vectors should minus one. */
++ if ((Identity->chipModel == gcv5000 && Identity->chipRevision == 0x5434) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5222) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5208) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5245) ||
++ (Identity->chipModel == gcv3000 && Identity->chipRevision == 0x5435) ||
++ (Identity->chipModel == gcv2200 && Identity->chipRevision == 0x5244) ||
++ (Identity->chipModel == gcv1500 && Identity->chipRevision == 0x5246) ||
++ ((Identity->chipModel == gcv2100 || Identity->chipModel == gcv2000) && Identity->chipRevision == 0x5108) ||
++ (Identity->chipModel == gcv880 && (Identity->chipRevision == 0x5107 || Identity->chipRevision == 0x5106)))
++ {
++ Identity->varyingsCount -= 1;
++ }
++
++ Identity->chip2DControl = 0;
++ if (Identity->chipModel == gcv320)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x0002C,
++ &data));
++
++ if ((data != 33956864) &&
++ ((Identity->chipRevision == 0x5007) ||
++ (Identity->chipRevision == 0x5220)))
++ {
++ Identity->chip2DControl |= 0xFF &
++ (Identity->chipRevision == 0x5220 ? 8 :
++ (Identity->chipRevision == 0x5007 ? 12 : 0));
++ }
++
++ if (Identity->chipRevision == 0x5007)
++ {
++ /* Disable splitting rectangle. */
++ Identity->chip2DControl |= 0x100;
++
++ /* Enable 2D Flush. */
++ Identity->chip2DControl |= 0x200;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#define gcdDEBUG_MODULE_CLOCK_GATING 0
++#define gcdDISABLE_MODULE_CLOCK_GATING 0
++#define gcdDISABLE_FE_CLOCK_GATING 0
++#define gcdDISABLE_PE_CLOCK_GATING 0
++#define gcdDISABLE_SH_CLOCK_GATING 0
++#define gcdDISABLE_PA_CLOCK_GATING 0
++#define gcdDISABLE_SE_CLOCK_GATING 0
++#define gcdDISABLE_RA_CLOCK_GATING 0
++#define gcdDISABLE_RA_EZ_CLOCK_GATING 0
++#define gcdDISABLE_RA_HZ_CLOCK_GATING 0
++#define gcdDISABLE_TX_CLOCK_GATING 0
++
++#if gcdDEBUG_MODULE_CLOCK_GATING
++gceSTATUS
++_ConfigureModuleLevelClockGating(
++ gckHARDWARE Hardware
++ )
++{
++ gctUINT32 data;
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++#if gcdDISABLE_FE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++#endif
++
++#if gcdDISABLE_PE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++#endif
++
++#if gcdDISABLE_SH_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++#endif
++
++#if gcdDISABLE_PA_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++#endif
++
++#if gcdDISABLE_SE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++#endif
++
++#if gcdDISABLE_RA_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++#endif
++
++#if gcdDISABLE_TX_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++#endif
++
++#if gcdDISABLE_RA_EZ_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++#endif
++
++#if gcdDISABLE_RA_HZ_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++#endif
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++
++#if gcdDISABLE_MODULE_CLOCK_GATING
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++#endif
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_PowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckHARDWARE hardware = (gckHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++static gceSTATUS
++_VerifyDMA(
++ IN gckOS Os,
++ IN gceCORE Core,
++ gctUINT32_PTR Address1,
++ gctUINT32_PTR Address2,
++ gctUINT32_PTR State1,
++ gctUINT32_PTR State2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State1));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address1));
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State2));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address2));
++
++ if (*Address1 != *Address2)
++ {
++ break;
++ }
++
++ if (*State1 != *State2)
++ {
++ break;
++ }
++ }
++
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_DumpDebugRegisters(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gcsiDEBUG_REGISTERS_PTR Descriptor
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 select;
++ gctUINT32 data = 0;
++ gctUINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Descriptor=0x%X", Os, Descriptor);
++
++ gcmkPRINT_N(4, " %s debug registers:\n", Descriptor->module);
++
++ for (i = 0; i < Descriptor->count; i += 1)
++ {
++ select = i << Descriptor->shift;
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ gcmkPRINT_N(12, " [0x%02X] 0x%08X\n", i, data);
++ }
++
++ select = 0xF << Descriptor->shift;
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ if (data == Descriptor->signature)
++ {
++ break;
++ }
++ }
++
++ if (i == 500)
++ {
++ gcmkPRINT_N(4, " failed to obtain the signature (read 0x%08X).\n", data);
++ }
++ else
++ {
++ gcmkPRINT_N(8, " signature = 0x%08X (%d read attempt(s))\n", data, i + 1);
++ }
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IsGPUPresent(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ control));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++_FlushCache(
++ gckHARDWARE Hardware,
++ gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 bytes, requested;
++ gctPOINTER buffer;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(Command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(Command, requested));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++gctBOOL
++_IsGPUIdle(
++ IN gctUINT32 Idle
++ )
++{
++ return (((((gctUINT32) (Idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) )
++ ;
++}
++
++/******************************************************************************\
++****************************** gckHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHARDWARE_Construct
++**
++** Construct a new gckHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** OUTPUT:
++**
++** gckHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckHARDWARE
++** object.
++*/
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware = gcvNULL;
++ gctUINT16 data = 0xff00;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ /* Enable the GPU. */
++ gcmkONERROR(gckOS_SetGPUPower(Os, Core, gcvTRUE, gcvTRUE));
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Allocate the gckHARDWARE object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckHARDWARE),
++ &pointer));
++
++ hardware = (gckHARDWARE) pointer;
++
++ /* Initialize the gckHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++ hardware->core = Core;
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Os, Core, &hardware->identity));
++
++ /* Determine the hardware type */
++ switch (hardware->identity.chipModel)
++ {
++ case gcv350:
++ case gcv355:
++ hardware->type = gcvHARDWARE_VG;
++ break;
++
++ case gcv200:
++ case gcv300:
++ case gcv320:
++ case gcv328:
++ case gcv420:
++ case gcv428:
++ hardware->type = gcvHARDWARE_2D;
++ break;
++
++ default:
++ hardware->type = gcvHARDWARE_3D;
++
++ if(hardware->identity.chipModel == gcv880 && hardware->identity.chipRevision == 0x5107)
++ {
++ /*set outstanding limit*/
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x00010;
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot));
++ }
++
++
++ if ((((((gctUINT32) (hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ))
++ {
++ hardware->type = (gceHARDWARE_TYPE) (hardware->type | gcvHARDWARE_2D);
++ }
++ }
++
++ hardware->powerBaseAddress
++ = ((hardware->identity.chipModel == gcv300)
++ && (hardware->identity.chipRevision < 0x2000))
++ ? 0x0100
++ : 0x0000;
++
++ /* _ResetGPU need powerBaseAddress. */
++ status = _ResetGPU(hardware, Os, Core);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ hardware->powerMutex = gcvNULL;
++
++ hardware->mmuVersion
++ = (((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 28:28)) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) );
++
++ /* Determine whether bug fixes #1 are present. */
++ hardware->extraEventStates = ((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ /* Check if big endian */
++ hardware->bigEndian = (*(gctUINT8 *)&data == 0xff);
++
++ /* Initialize the fast clear. */
++ gcmkONERROR(gckHARDWARE_SetFastClear(hardware, -1, -1));
++
++#if !gcdENABLE_128B_MERGE
++
++ if (((((gctUINT32) (hardware->identity.chipMinorFeatures2)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ /* 128B merge is turned on by default. Disable it. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00558, 0));
++ }
++
++#endif
++
++ /* Set power state to ON. */
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++ hardware->lastWaitLink = ~0U;
++ hardware->lastEnd = ~0U;
++ hardware->globalSemaphore = gcvNULL;
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ hardware->powerOnFscaleVal = 64;
++#endif
++
++ gcmkONERROR(gckOS_CreateMutex(Os, &hardware->powerMutex));
++ gcmkONERROR(gckOS_CreateSemaphore(Os, &hardware->globalSemaphore));
++ hardware->startIsr = gcvNULL;
++ hardware->stopIsr = gcvNULL;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _PowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pendingEvent));
++
++#if gcdLINK_QUEUE_SIZE
++ hardware->linkQueue.front = 0;
++ hardware->linkQueue.rear = 0;
++ hardware->linkQueue.count = 0;
++#endif
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Disable profiler by default */
++ hardware->gpuProfiler = gcvFALSE;
++
++ if (hardware->mmuVersion)
++ {
++ hardware->endAfterFlushMmuCache = gcvTRUE;
++ }
++ else
++ {
++ hardware->endAfterFlushMmuCache = gcvFALSE;
++ }
++
++ gcmkONERROR(gckOS_QueryOption(Os, "mmu", (gctUINT32_PTR)&hardware->enableMMU));
++
++ hardware->minFscaleValue = 1;
++
++ /* Return pointer to the gckHARDWARE object. */
++ *Hardware = hardware;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Hardware=0x%x", *Hardware);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, Core, gcvFALSE, gcvFALSE));
++
++ if (hardware->globalSemaphore != gcvNULL)
++ {
++ /* Destroy the global semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Os,
++ hardware->globalSemaphore));
++ }
++
++ if (hardware->powerMutex != gcvNULL)
++ {
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ if (hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware->pendingEvent != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pendingEvent));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, hardware));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Destroy
++**
++** Destroy an gckHARDWARE object.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Destroy the power semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Hardware->os, Hardware->powerMutex));
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pendingEvent));
++
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ Hardware->os,
++ Hardware->functionBytes,
++ Hardware->functionPhysical,
++ Hardware->functionLogical
++ ));
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Hardware->os, Hardware));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_GetType
++**
++** Get the hardware type.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gceHARDWARE_TYPE * Type
++** Pointer to a variable that receives the type of hardware object.
++*/
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkVERIFY_ARGUMENT(Type != gcvNULL);
++
++ *Type = Hardware->type;
++
++ gcmkFOOTER_ARG("*Type=%d", *Type);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_InitializeHardware
++**
++** Initialize the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++ gctUINT32 chipRev;
++ gctUINT32 control;
++ gctUINT32 data;
++ gctUINT32 regPMC = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the chip revision register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00024,
++ &chipRev));
++
++ if (chipRev != Hardware->identity.chipRevision)
++ {
++ /* Chip is not there! */
++ gcmkONERROR(gcvSTATUS_CONTEXT_LOSSED);
++ }
++
++ /* Disable isolate GPU bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)))));
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ /* Reset memory counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ ~0U));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++
++ /* Get the system's physical base address. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Program the base addesses. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0041C,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00418,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00428,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00420,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00424,
++ baseAddress));
++
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ /* Enable clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ if ((Hardware->identity.chipRevision == 0x4301)
++ || (Hardware->identity.chipRevision == 0x4302)
++ )
++ {
++ /* Disable stall module level clock gating for 4.3.0.1 and 4.3.0.2
++ ** revisions. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++
++#if gcdENABLE_3D
++ /* Disable PE clock gating on revs < 5.0 when HZ is present without a
++ ** bug fix. */
++ if ((Hardware->identity.chipRevision < 0x5000)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HZ)
++ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))))
++ )
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable PE clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ }
++
++#endif
++ }
++
++ if (Hardware->identity.chipModel == gcv4000 &&
++ ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222)))
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)))));
++ }
++
++ if (Hardware->identity.chipModel == gcv1000 &&
++ (Hardware->identity.chipRevision == 0x5039 ||
++ Hardware->identity.chipRevision == 0x5040))
++ {
++ gctUINT32 pulseEater;
++
++ pulseEater = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (pulseEater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)))));
++ }
++
++ if ((gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) == gcvSTATUS_FALSE)
++ || (Hardware->identity.chipRevision < 0x5422)
++ )
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15)));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108))
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ &data));
++
++ /* Set FE bus to one, TX bus to zero */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ data));
++ }
++
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(Hardware,
++ Hardware->kernel->mmu->pageTableLogical));
++
++ if (Hardware->identity.chipModel >= gcv400
++ && Hardware->identity.chipModel != gcv420)
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable PA clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++
++ /* Limit 2D outstanding request. */
++ if (_IsHardwareMatch(Hardware, gcv880, 0x5107))
++ {
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x00010;
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00414, axi_ot));
++ }
++
++ if (Hardware->identity.chip2DControl & 0xFF)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (Hardware->identity.chip2DControl & 0xFF) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv1000, 0x5035))
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ /* Disable HZ-L2. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv4000, 0x5222))
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable TX clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv880, 0x5106))
++ {
++ Hardware->kernel->timeOut = 140 * 1000;
++ }
++
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable RA HZ clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable RA EZ clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++
++ if (regPMC != 0)
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ regPMC));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108)
++ || _IsHardwareMatch(Hardware, gcv320, 0x5007)
++ || _IsHardwareMatch(Hardware, gcv880, 0x5106)
++ || _IsHardwareMatch(Hardware, gcv400, 0x4645)
++ )
++ {
++ /* Update GPU AXI cache atttribute. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00008,
++ 0x00002200));
++ }
++
++
++ if ((Hardware->identity.chipRevision > 0x5420)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D))
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ /* Disable internal DFS. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++ }
++
++#if gcdDEBUG_MODULE_CLOCK_GATING
++ _ConfigureModuleLevelClockGating(Hardware);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*InternalSize=%lu *InternalBaseAddress=0x%08x "
++ "*InternalAlignment=0x%08x *ExternalSize=%lu "
++ "*ExternalBaseAddress=0x%08x *ExtenalAlignment=0x%08x "
++ "*HorizontalTileSize=%u *VerticalTileSize=%u",
++ gcmOPT_VALUE(InternalSize),
++ gcmOPT_VALUE(InternalBaseAddress),
++ gcmOPT_VALUE(InternalAlignment),
++ gcmOPT_VALUE(ExternalSize),
++ gcmOPT_VALUE(ExternalBaseAddress),
++ gcmOPT_VALUE(ExternalAlignment),
++ gcmOPT_VALUE(HorizontalTileSize),
++ gcmOPT_VALUE(VerticalTileSize));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++** Pointer to the identity structure.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gctUINT32 features;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Identity != gcvNULL);
++
++ /* Return chip model and revision. */
++ Identity->chipModel = Hardware->identity.chipModel;
++ Identity->chipRevision = Hardware->identity.chipRevision;
++
++ /* Return feature set. */
++ features = Hardware->identity.chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* Override fast clear by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ if ((((((gctUINT32) (features)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ))
++ {
++ /* Override compression by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (Hardware->allowCompression) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 through GC500.2 and GC300,
++ ** since they did not have this bit. */
++ if (((Hardware->identity.chipModel == gcv500) && (Hardware->identity.chipRevision <= 2))
++ || (Hardware->identity.chipModel == gcv300)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ Identity->chipFeatures = features;
++
++ /* Return minor features. */
++ Identity->chipMinorFeatures = Hardware->identity.chipMinorFeatures;
++ Identity->chipMinorFeatures1 = Hardware->identity.chipMinorFeatures1;
++ Identity->chipMinorFeatures2 = Hardware->identity.chipMinorFeatures2;
++ Identity->chipMinorFeatures3 = Hardware->identity.chipMinorFeatures3;
++ Identity->chipMinorFeatures4 = Hardware->identity.chipMinorFeatures4;
++ Identity->chipMinorFeatures5 = Hardware->identity.chipMinorFeatures5;
++
++ /* Return chip specs. */
++ Identity->streamCount = Hardware->identity.streamCount;
++ Identity->registerMax = Hardware->identity.registerMax;
++ Identity->threadCount = Hardware->identity.threadCount;
++ Identity->shaderCoreCount = Hardware->identity.shaderCoreCount;
++ Identity->vertexCacheSize = Hardware->identity.vertexCacheSize;
++ Identity->vertexOutputBufferSize = Hardware->identity.vertexOutputBufferSize;
++ Identity->pixelPipes = Hardware->identity.pixelPipes;
++ Identity->instructionCount = Hardware->identity.instructionCount;
++ Identity->numConstants = Hardware->identity.numConstants;
++ Identity->bufferSize = Hardware->identity.bufferSize;
++ Identity->varyingsCount = Hardware->identity.varyingsCount;
++ Identity->superTileMode = Hardware->identity.superTileMode;
++ Identity->chip2DControl = Hardware->identity.chip2DControl;
++
++ Identity->productID = Hardware->identity.productID;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Addres=0x%08x", Hardware, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 31:31)) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x1:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = (((((gctUINT32) (Address)) >> (0 ? 30:0)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1)))))) );
++ }
++ else
++ {
++ *Pool = gcvPOOL_SYSTEM;
++ *Offset = Address;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Pool=%d *Offset=0x%08x", *Pool, *Offset);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Hardware address of command buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes for the prefetch unit (until after the first LINK).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Bytes=%lu",
++ Hardware, Address, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Enable all events. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00014, ~0U));
++
++ /* Write address register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00654, Address));
++
++ /* Build control register. */
++ control = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) ((Bytes + 7) >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ /* Set big endian */
++ if (Hardware->bigEndian)
++ {
++ control |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20)));
++ }
++
++ /* Write control register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00658, control));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Started command buffer @ 0x%08x",
++ Address);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_WaitLink
++**
++** Append a WAIT/LINK command sequence at the specified location in the command
++** queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** WAIT/LINK command sequence at or gcvNULL just to query the size of the
++** WAIT/LINK command sequence.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the WAIT/LINK command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the WAIT/LINK command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitOffset
++** Pointer to a variable that will receive the offset of the WAIT command
++** from the specified logcial pointer.
++** If 'WaitOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitSize
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command. If 'LinkSize' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctUINT32 * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctUINT32 * WaitSize
++ )
++{
++ static const gctUINT waitCount = 200;
++
++ gceSTATUS status;
++ gctUINT32 address;
++ gctUINT32_PTR logical;
++ gctUINT32 bytes;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x *Bytes=%lu",
++ Hardware, Logical, Offset, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical != gcvNULL) || (Bytes != gcvNULL));
++
++ /* Compute number of bytes required. */
++ bytes = gcmALIGN(Offset + 16, 8) - Offset;
++ /* Cast the input pointer. */
++ logical = (gctUINT32_PTR) Logical;
++
++ if (logical != gcvNULL)
++ {
++ /* Not enough space? */
++ if (*Bytes < bytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address));
++
++ /* Store the WAIT/LINK address. */
++ Hardware->lastWaitLink = address;
++
++ /* Append WAIT(count). */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (waitCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ /* Append LINK(2, address). */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3] = address;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, waitCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: LINK 0x%08x, #%lu",
++ address + 8, address, bytes
++ );
++ if (WaitOffset != gcvNULL)
++ {
++ /* Return the offset pointer to WAIT command. */
++ *WaitOffset = 0;
++ }
++
++ if (WaitSize != gcvNULL)
++ {
++ /* Return number of bytes used by the WAIT command. */
++ *WaitSize = 8;
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the WAIT/LINK command
++ ** sequence. */
++ *Bytes = bytes;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *WaitOffset=0x%x *WaitSize=%lu",
++ gcmOPT_VALUE(Bytes), gcmOPT_VALUE(WaitOffset),
++ gcmOPT_VALUE(WaitSize));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_End
++**
++** Append an END command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** END command at or gcvNULL just to query the size of the END command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append END. */
++ logical[0] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: END", Logical);
++
++ /* Make sure the CPU writes out the data to memory. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address));
++
++ Hardware->lastEnd = address;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Nop
++**
++** Append a NOP command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** NOP command at or gcvNULL just to query the size of the NOP command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the NOP command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append NOP. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: NOP", Logical);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the NOP command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Event
++**
++** Append an EVENT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the EVENT command at or gcvNULL just to query the size of the EVENT
++** command.
++**
++** gctUINT8 Event
++** Event ID to program.
++**
++** gceKERNEL_WHERE FromWhere
++** Location of the pipe to send the event.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the EVENT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT size;
++ gctUINT32 destination = 0;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Event=%u FromWhere=%d *Bytes=%lu",
++ Hardware, Logical, Event, FromWhere, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++ gcmkVERIFY_ARGUMENT(Event < 32);
++
++ /* Determine the size of the command. */
++
++ size = (Hardware->extraEventStates && (FromWhere == gcvKERNEL_PIXEL))
++ ? gcmALIGN(8 + (1 + 5) * 4, 8) /* EVENT + 5 STATES */
++ : 8;
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < size)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ switch (FromWhere)
++ {
++ case gcvKERNEL_COMMAND:
++ /* From command processor. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ break;
++
++ case gcvKERNEL_PIXEL:
++ /* From pixel engine. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Append EVENT(Event, destiantion). */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1] = ((((gctUINT32) (destination)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (Event) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ /* Make sure the event ID gets written out before GPU can access it. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ {
++ gctUINT32 phys;
++ gckOS_GetPhysicalAddress(Hardware->os, Logical, &phys);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: EVENT %d", phys, Event);
++ }
++#endif
++
++ /* Append the extra states. These are needed for the chips that do not
++ ** support back-to-back events due to the async interface. The extra
++ ** states add the necessary delay to ensure that event IDs do not
++ ** collide. */
++ if (size > 8)
++ {
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0100) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++ logical[3] = 0;
++ logical[4] = 0;
++ logical[5] = 0;
++ logical[6] = 0;
++ logical[7] = 0;
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ if (Event < gcmCOUNTOF(Hardware->kernel->eventObj->queues))
++ {
++ gckOS_AtomSetMask(Hardware->pendingEvent, 1 << Event);
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT command. */
++ *Bytes = size;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_PipeSelect
++**
++** Append a PIPESELECT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the PIPESELECT command at or gcvNULL just to query the size of the
++** PIPESELECT command.
++**
++** gcePIPE_SELECT Pipe
++** Pipe value to select.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the PIPESELECT command.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the PIPESELECT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Pipe=%d *Bytes=%lu",
++ Hardware, Logical, Pipe, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ /* Append a PipeSelect. */
++ if (Logical != gcvNULL)
++ {
++ gctUINT32 flush, stall;
++
++ if (*Bytes < 32)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ flush = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++
++ stall = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1]
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical, flush);
++
++ /* LoadState(AQSempahore, 1), stall. */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3]
++ = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: SEMAPHORE 0x%x", logical + 2, stall);
++
++ /* Stall, stall. */
++ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ logical[5] = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: STALL 0x%x", logical + 4, stall);
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ logical[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[7] = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: PIPE %d", logical + 6, Pipe);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the PIPESELECT command. */
++ *Bytes = 32;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Link
++**
++** Append a LINK command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the LINK command at or gcvNULL just to query the size of the LINK
++** command.
++**
++** gctUINT32 FetchAddress
++** Hardware address of destination of LINK.
++**
++** gctSIZE_T FetchSize
++** Number of bytes in destination of LINK.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the LINK command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the LINK command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT32 FetchSize,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gctUINT32 link;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x FetchAddress=0x%x FetchSize=%lu "
++ "*Bytes=%lu",
++ Hardware, Logical, FetchAddress, FetchSize,
++ gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical + 1, FetchAddress));
++
++ /* Make sure the address got written before the LINK command. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++ /* Compute number of 64-byte aligned bytes to fetch. */
++ bytes = gcmALIGN(FetchAddress + FetchSize, 8) - FetchAddress;
++
++ /* Append LINK(bytes / 8), FetchAddress. */
++ link = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical, link));
++
++ /* Memory barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical));
++
++#if gcdLINK_QUEUE_SIZE && !gcdPROCESS_ADDRESS_SPACE
++ if ((Hardware->kernel->virtualCommandBuffer)
++ && (Hardware->kernel->stuckDump > 2)
++ )
++ {
++ gctBOOL in;
++
++ gcmkVERIFY_OK(gckCOMMAND_AddressInKernelCommandBuffer(
++ Hardware->kernel->command, FetchAddress, &in));
++
++ if (in == gcvFALSE)
++ {
++ /* Record user command buffer and context buffer link
++ ** information for stuck dump.
++ **/
++ gckLINKQUEUE_Enqueue(
++ &Hardware->linkQueue, FetchAddress, FetchAddress + (gctUINT)bytes);
++ }
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_UpdateQueueTail
++**
++** Update the tail of the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the start of the command queue.
++**
++** gctUINT32 Offset
++** Offset into the command queue of the tail (last command).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x",
++ Hardware, Logical, Offset);
++
++ /* Verify the hardware. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Force a barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ /* Notify gckKERNEL object of change. */
++ gcmkONERROR(
++ gckKERNEL_Notify(Hardware->kernel,
++ gcvNOTIFY_COMMAND_QUEUE,
++ gcvFALSE));
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ gcmkONERROR(gcvSTATUS_DEVICE);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the memory in user space.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d",
++ Hardware, Logical, InUserSpace);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Convert logical address into a physical address. */
++ if (InUserSpace)
++ {
++ gcmkONERROR(gckOS_UserLogicalToPhysical(Hardware->os, Logical, &address));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++ }
++
++ /* For old MMU, get GPU address according to baseAddress. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Subtract base address to get a GPU address. */
++ gcmkASSERT(address >= baseAddress);
++ address -= baseAddress;
++ }
++
++ /* Return hardware specific address. */
++ *Address = (Hardware->mmuVersion == 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)))
++ : address;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Interrupt
++**
++** Process an interrupt.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL InterruptValid
++** If gcvTRUE, this function will read the interrupt acknowledge
++** register, stores the data, and return whether or not the interrupt
++** is ours or not. If gcvFALSE, this functions will read the interrupt
++** acknowledge register and combine it with any stored value to handle
++** the event notifications.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL InterruptValid
++ )
++{
++ gckEVENT eventObj;
++ gctUINT32 data = 0;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x InterruptValid=%d", Hardware, InterruptValid);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Extract gckEVENT object. */
++ eventObj = Hardware->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ if (InterruptValid)
++ {
++ /* Read AQIntrAcknowledge register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00010,
++ &data));
++
++ if (data == 0)
++ {
++ /* Not our interrupt. */
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ }
++ else
++ {
++
++#if gcdINTERRUPT_STATISTIC
++ gckOS_AtomClearMask(Hardware->pendingEvent, data);
++#endif
++
++ /* Inform gckEVENT of the interrupt. */
++ status = gckEVENT_Interrupt(eventObj,
++ data);
++ }
++ }
++ else
++ {
++ /* Handle events. */
++ status = gckEVENT_Notify(eventObj, 0);
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryCommandBuffer
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Alignment
++** Pointer to a variable receiving the alignment for each command.
++**
++** gctSIZE_T * ReservedHead
++** Pointer to a variable receiving the number of reserved bytes at the
++** head of each command buffer.
++**
++** gctSIZE_T * ReservedTail
++** Pointer to a variable receiving the number of bytes reserved at the
++** tail of each command buffer.
++*/
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Alignment,
++ OUT gctUINT32 * ReservedHead,
++ OUT gctUINT32 * ReservedTail
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Alignment != gcvNULL)
++ {
++ /* Align every 8 bytes. */
++ *Alignment = 8;
++ }
++
++ if (ReservedHead != gcvNULL)
++ {
++ /* Reserve space for SelectPipe(). */
++ *ReservedHead = 32;
++ }
++
++ if (ReservedTail != gcvNULL)
++ {
++ /* Reserve space for Link(). */
++ *ReservedTail = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Alignment=%lu *ReservedHead=%lu *ReservedTail=%lu",
++ gcmOPT_VALUE(Alignment), gcmOPT_VALUE(ReservedHead),
++ gcmOPT_VALUE(ReservedTail));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = 1U << 31;
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*SystemSize=%lu *SystemBaseAddress=%lu",
++ gcmOPT_VALUE(SystemSize), gcmOPT_VALUE(SystemBaseAddress));
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_3D
++/*******************************************************************************
++**
++** gckHARDWARE_QueryShaderCaps
++**
++** Query the shader capabilities.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT * VertexUniforms
++** Pointer to a variable receiving the number of uniforms in the vertex
++** shader.
++**
++** gctUINT * FragmentUniforms
++** Pointer to a variable receiving the number of uniforms in the
++** fragment shader.
++**
++** gctBOOL * UnifiedUnforms
++** Pointer to a variable receiving whether the uniformas are unified.
++*/
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctBOOL * UnifiedUnforms
++ )
++{
++ gctBOOL unifiedConst;
++ gctUINT32 vsConstMax;
++ gctUINT32 psConstMax;
++ gctUINT32 vsConstBase;
++ gctUINT32 psConstBase;
++ gctUINT32 ConstMax;
++
++ gcmkHEADER_ARG("Hardware=0x%x VertexUniforms=0x%x "
++ "FragmentUniforms=0x%x UnifiedUnforms=0x%x",
++ Hardware, VertexUniforms,
++ FragmentUniforms, UnifiedUnforms);
++
++ {if (Hardware->identity.numConstants > 256){ unifiedConst = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; ConstMax = Hardware->identity.numConstants; vsConstMax = 256; psConstMax = ConstMax - vsConstMax;}else if (Hardware->identity.numConstants == 256){ if (Hardware->identity.chipModel == gcv2000 && Hardware->identity.chipRevision == 0x5118) { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 64; ConstMax = 320; } else { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 256; ConstMax = 512; }}else{ unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 168; psConstMax = 64; ConstMax = 232;}};
++
++ if (VertexUniforms != gcvNULL)
++ {
++ /* Return the vs shader const count. */
++ *VertexUniforms = vsConstMax;
++ }
++
++ if (FragmentUniforms != gcvNULL)
++ {
++ /* Return the ps shader const count. */
++ *FragmentUniforms = psConstMax;
++ }
++
++ if (UnifiedUnforms != gcvNULL)
++ {
++ /* Return whether the uniformas are unified. */
++ *UnifiedUnforms = unifiedConst;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++ gctUINT32 idle;
++ gctUINT32 timer = 0, delay = 1;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert the logical address into physical address. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Setting page table to 0x%08X",
++ address);
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00400,
++ address));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00410,
++ address));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00404,
++ address));
++
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00408,
++ address));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0040C,
++ address));
++ }
++ else if (Hardware->enableMMU == gcvTRUE)
++ {
++ /* Execute prepared command sequence. */
++ gcmkONERROR(gckHARDWARE_Execute(
++ Hardware,
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address,
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes
++ ));
++
++ /* Wait until MMU configure finishes. */
++ do
++ {
++ gckOS_Delay(Hardware->os, delay);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(
++ Hardware->os,
++ Hardware->core,
++ 0x00004,
++ &idle));
++
++ timer += delay;
++ delay *= 2;
++
++#if gcdGPU_TIMEOUT
++ if (timer >= Hardware->kernel->timeOut)
++ {
++ /* Even if hardware is not reset correctly, let software
++ ** continue to avoid software stuck. Software will timeout again
++ ** and try to recover GPU in next timeout.
++ */
++ gcmkONERROR(gcvSTATUS_DEVICE);
++ }
++#endif
++ }
++ while (!(((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ));
++
++ /* Enable MMU. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os,
++ Hardware->core,
++ 0x0018C,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (gcvTRUE) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command;
++ gctUINT32_PTR buffer;
++ gctUINT32 bufferSize;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 flushSize;
++ gctUINT32 count;
++ gctUINT32 physical;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Hardware->kernel->command;
++
++ /* Flush the memory controller. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, 8, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ gcmkONERROR(gckCOMMAND_Execute(command, 8));
++ }
++ else
++ {
++ flushSize = 16 * 4;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, flushSize, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ count = ((gctUINT)bufferSize - flushSize + 7) >> 3;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(command->os, buffer, &physical));
++
++ /* Flush cache. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[3]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[5]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[7]
++ = physical + 8 * gcmSIZEOF(gctUINT32);
++
++ /* Flush MMU cache. */
++ buffer[8]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[9]
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[10]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[11]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[12]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[13]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[14]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[15]
++ = physical + flushSize;
++
++ gcmkONERROR(gckCOMMAND_Execute(command, flushSize));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetMMUStates(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 config, address;
++ gctUINT32_PTR buffer;
++ gctBOOL ace;
++ gctUINT32 reserveBytes = 16 + 4 * 4;
++
++ gctBOOL config2D;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Hardware->mmuVersion != 0);
++
++ ace = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_ACE);
++
++ if (ace)
++ {
++ reserveBytes += 8;
++ }
++
++ config2D = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_2D);
++
++ if (config2D)
++ {
++ reserveBytes +=
++ /* Pipe Select. */
++ 4 * 4
++ /* Configure MMU States. */
++ + 4 * 4
++ /* Semaphore stall */
++ + 4 * 8;
++ }
++
++ /* Convert logical address into physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, MtlbAddress, &config));
++
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, SafeAddress, &address));
++
++ if (address & 0x3F)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ switch (Mode)
++ {
++ case gcvMMU_MODE_1K:
++ if (config & 0x3FF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ case gcvMMU_MODE_4K:
++ if (config & 0xFFF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (Logical != gcvNULL)
++ {
++ buffer = Logical;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = config;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = address;
++
++ if (ace)
++ {
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0068) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0;
++ }
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++
++ if (config2D)
++ {
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0x1;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = config;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = address;
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0x0;
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++ }
++
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ *Bytes = reserveBytes;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++/*******************************************************************************
++**
++** gckHARDWARE_ConfigMMU
++**
++** Append a MMU Configuration command sequence at the specified location in the command
++** queue. That command sequence consists of mmu configuration, LINK and WAIT/LINK.
++** LINK is fetched and paresed with new mmu configuration.
++**
++** If MMU Configuration is not changed between commit, change last WAIT/LINK to
++** link to ENTRY.
++**
++** -+-----------+-----------+-----------------------------------------
++** | WAIT/LINK | WAIT/LINK |
++** -+-----------+-----------+-----------------------------------------
++** | /|\
++** \|/ |
++** +--------------------+
++** | ENTRY | ... | LINK |
++** +--------------------+
++**
++** If MMU Configuration is changed between commit, change last WAIT/LINK to
++** link to MMU CONFIGURATION command sequence, and there are an EVNET and
++** an END at the end of this command sequence, when interrupt handler
++** receives this event, it will start FE at ENTRY to continue the command
++** buffer execution.
++**
++** -+-----------+-------------------+---------+---------+-----------+--
++** | WAIT/LINK | MMU CONFIGURATION | EVENT | END | WAIT/LINK |
++** -+-----------+-------------------+---------+---------+-----------+--
++** | /|\ /|\
++** +-------------+ |
++** +--------------------+
++** | ENTRY | ... | LINK |
++** +--------------------+
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** command sequence at or gcvNULL just to query the size of the
++** command sequence.
++**
++** gctPOINTER MtlbLogical
++** Pointer to the current Master TLB.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitLinkOffset
++** Pointer to a variable that will receive the offset of the WAIT/LINK command
++** from the specified logcial pointer.
++** If 'WaitLinkOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitLinkBytes
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command.
++** If 'WaitLinkBytes' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_ConfigMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER MtlbLogical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctSIZE_T * WaitLinkOffset,
++ OUT gctSIZE_T * WaitLinkBytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes, bytesAligned;
++ gctUINT32 config;
++ gctUINT32_PTR buffer = (gctUINT32_PTR) Logical;
++ gctUINT32 physical;
++ gctUINT32 event;
++
++ gcmkHEADER_ARG("Hardware=0x%08X Logical=0x%08x MtlbLogical=0x%08X",
++ Hardware, Logical, MtlbLogical);
++
++ bytes
++ /* Flush cache states. */
++ = 18 * 4
++ /* MMU configuration states. */
++ + 6 * 4
++ /* EVENT. */
++ + 2 * 4
++ /* END. */
++ + 2 * 4
++ /* WAIT/LINK. */
++ + 4 * 4;
++
++ /* Compute number of bytes required. */
++ bytesAligned = gcmALIGN(Offset + bytes, 8) - Offset;
++
++ if (buffer != gcvNULL)
++ {
++ if (MtlbLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get physical address of this command buffer segment. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, buffer, &physical));
++
++ /* Get physical address of Master TLB. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, MtlbLogical, &config));
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ /* Flush cache. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Flush tile status cache. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = physical + 10 * gcmSIZEOF(gctUINT32);
++
++ /* Configure MMU. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = physical + 18 * 4;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = config;
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Event 29. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ event = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ event = ((((gctUINT32) (event)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (29) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ *buffer++
++ = event;
++
++ /* Append END. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ *Bytes = bytesAligned;
++ }
++
++ if (WaitLinkOffset != gcvNULL)
++ {
++ *WaitLinkOffset = bytes - 4 * 4;
++ }
++
++ if (WaitLinkBytes != gcvNULL)
++ {
++ *WaitLinkBytes = 4 * 4;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Index=%u Offset=%u", Hardware, Index, Offset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ *Address = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (Offset | (Index << 12)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle = 0;
++ gctINT retry, poll, pollCount;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Wait=%d", Hardware, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++
++ /* If we have to wait, try 100 polls per millisecond. */
++ pollCount = Wait ? 100 : 1;
++
++ /* At most, try for 1 second. */
++ for (retry = 0; retry < 1000; ++retry)
++ {
++ /* If we have to wait, try 100 polls per millisecond. */
++ for (poll = pollCount; poll > 0; --poll)
++ {
++ /* Read register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++
++ /* See if we have to wait for FE idle. */
++ if (_IsGPUIdle(idle)
++ && (address == Hardware->lastEnd + 8)
++ )
++ {
++ /* FE is idle. */
++ break;
++ }
++ }
++
++ /* Check if we need to wait for FE and FE is busy. */
++ if (Wait && !_IsGPUIdle(idle))
++ {
++ /* Wait a little. */
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HARDWARE,
++ "%s: Waiting for idle: 0x%08X",
++ __FUNCTION__, idle);
++
++ gcmkVERIFY_OK(gckOS_Delay(Hardware->os, 1));
++ }
++ else
++ {
++ break;
++ }
++ }
++
++ /* Return idle to caller. */
++ *Data = idle;
++
++#if defined(EMULATOR)
++ /* Wait a little while until CModel FE gets END.
++ * END is supposed to be appended by caller.
++ */
++ gckOS_Delay(gcvNULL, 100);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32 pipe;
++ gctUINT32 flush = 0;
++ gctBOOL flushTileStatus;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++ gctUINT32 reserveBytes
++ /* Semaphore/Stall */
++ = 4 * gcmSIZEOF(gctUINT32);
++
++ gcmkHEADER_ARG("Hardware=0x%x Flush=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Flush, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get current pipe. */
++ pipe = Hardware->kernel->command->pipeSelect;
++
++ /* Flush tile status cache. */
++ flushTileStatus = Flush & gcvFLUSH_TILE_STATUS;
++
++ /* Flush 3D color cache. */
++ if ((Flush & gcvFLUSH_COLOR) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ /* Flush 3D depth cache. */
++ if ((Flush & gcvFLUSH_DEPTH) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Flush 3D texture cache. */
++ if ((Flush & gcvFLUSH_TEXTURE) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ }
++
++ /* Flush 2D cache. */
++ if ((Flush & gcvFLUSH_2D) && (pipe == 0x1))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ }
++
++ /* Determine reserve bytes. */
++ if (flush)
++ {
++ reserveBytes += 2 * gcmSIZEOF(gctUINT32);
++ }
++
++ if (flushTileStatus)
++ {
++ reserveBytes += 2 * gcmSIZEOF(gctUINT32);
++ }
++
++ /* See if there is a valid flush. */
++ if ((flush == 0) && (flushTileStatus == gcvFALSE))
++ {
++ if (Bytes != gcvNULL)
++ {
++ /* No bytes required. */
++ *Bytes = 0;
++ }
++ }
++
++ else
++ {
++ /* Copy to command queue. */
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < reserveBytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ if (flush)
++ {
++ /* Append LOAD_STATE to AQFlush. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *logical++
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical - 1, flush);
++ }
++
++ if (flushTileStatus)
++ {
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH TILE STATUS 0x%x", logical - 1, logical[-1]);
++ }
++
++ /* Semaphore. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x05 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* bytes required. */
++ *Bytes = reserveBytes;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ )
++{
++#if gcdENABLE_3D
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Enable=%d Compression=%d",
++ Hardware, Enable, Compression);
++
++ /* Only process if fast clear is available. */
++ if ((((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ if (Enable == -1)
++ {
++ /* Determine automatic value for fast clear. */
++ Enable = ((Hardware->identity.chipModel != gcv500)
++ || (Hardware->identity.chipRevision >= 3)
++ ) ? 1 : 0;
++ }
++
++ if (Compression == -1)
++ {
++ /* Determine automatic value for compression. */
++ Compression = Enable
++ & (((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) );
++ }
++
++ /* Read AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &debug));
++
++ /* Set fast clear bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++ if (
++ ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) ||
++ (Hardware->identity.chipModel >= gcv4000))
++ {
++ /* Set compression bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21))) | (((gctUINT32) ((gctUINT32) (Compression == 0) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21)));
++ }
++
++ /* Write back AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ debug));
++
++ /* Store fast clear and comprersison flags. */
++ Hardware->allowFastClear = Enable;
++ Hardware->allowCompression = Compression;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "FastClear=%d Compression=%d", Enable, Compression);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++}
++gcePOWER_FLAGS;
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++static gctCONST_STRING
++_PowerEnum(gceCHIPPOWERSTATE State)
++{
++ const gctCONST_STRING states[] =
++ {
++ gcmSTRING(gcvPOWER_ON),
++ gcmSTRING(gcvPOWER_OFF),
++ gcmSTRING(gcvPOWER_IDLE),
++ gcmSTRING(gcvPOWER_SUSPEND),
++ gcmSTRING(gcvPOWER_SUSPEND_ATPOWERON),
++ gcmSTRING(gcvPOWER_OFF_ATPOWERON),
++ gcmSTRING(gcvPOWER_IDLE_BROADCAST),
++ gcmSTRING(gcvPOWER_SUSPEND_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_RECOVERY),
++ gcmSTRING(gcvPOWER_OFF_TIMEOUT),
++ gcmSTRING(gcvPOWER_ON_AUTO)
++ };
++
++ if ((State >= gcvPOWER_ON) && (State <= gcvPOWER_ON_AUTO))
++ {
++ return states[State - gcvPOWER_ON];
++ }
++
++ return "unknown";
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag, clock;
++ gctPOINTER buffer;
++ gctUINT32 bytes, requested;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL broadcast = gcvFALSE;
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++ gctUINT32 process, thread;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL commandStarted = gcvFALSE;
++ gctBOOL isrStarted = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++ gctBOOL global = gcvFALSE;
++ gctBOOL globalAcquired = gcvFALSE;
++ gctBOOL configMmu = gcvFALSE;
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_RELEASE,
++ /* OFF */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ /* Clocks. */
++ static const gctUINT clocks[4] =
++ {
++ /* gcvPOWER_ON */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (64) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_OFF */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_IDLE */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_SUSPEND */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d(%s)",
++ State, _PowerEnum(State));
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ if (Hardware->powerManagement == gcvFALSE
++ && State != gcvPOWER_ON
++ )
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 3);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State != gcvPOWER_ON)
++ {
++ /* Called from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONWARNING(gcvSTATUS_INVALID_REQUEST);
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Before we grab locks see if this is actually a needed change */
++ if (State == Hardware->chipPowerState)
++ {
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Get time until mutex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ clock = clocks[State];
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if (State == gcvPOWER_ON)
++ {
++ clock = ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (Hardware->powerOnFscaleVal) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)));
++ }
++#endif
++
++ if (State == gcvPOWER_SUSPEND && Hardware->chipPowerState == gcvPOWER_OFF && broadcast)
++ {
++#if gcdPOWER_SUSPEND_WHEN_IDLE
++ /* Do nothing */
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++#else
++ /* Clock should be on when switch power from off to suspend */
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) ;
++#endif
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE or SUSPEND. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Power Off GPU[%d] at %u [supposed to be at %u]",
++ Hardware->core, currentTime, Hardware->powerOffTime);
++ }
++
++ if (State == gcvPOWER_ON || State == gcvPOWER_OFF)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* If this is an internal power management, we have to check if we can grab
++ ** the global power semaphore. If we cannot, we have to wait until the
++ ** external world changes power management. */
++ if (!global)
++ {
++ /* Try to acquire the global semaphore. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Called from thread routine which should NEVER sleep.*/
++ gcmkONWARNING(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Release the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Releasing the power mutex.");
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ /* Wait for the semaphore. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Waiting for global semaphore.");
++ gcmkONERROR(gckOS_AcquireSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvTRUE;
++
++ /* Acquire the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Reacquiring the power mutex.");
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ mutexAcquired = gcvTRUE;
++
++ /* chipPowerState may be changed by external world during the time
++ ** we give up powerMutex, so updating flag now is necessary. */
++ flag = flags[Hardware->chipPowerState][State];
++
++ if (flag == 0)
++ {
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Error. */
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore again. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ else
++ {
++ if (State == gcvPOWER_OFF || State == gcvPOWER_SUSPEND || State == gcvPOWER_IDLE)
++ {
++ gctBOOL idle;
++ /* Check for idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle));
++
++ if (!idle)
++ {
++ gcmkONWARNING(gcvSTATUS_CHIP_NOT_READY);
++ }
++
++ /* Acquire the global semaphore if it has not been acquired. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_OK)
++ {
++ globalAcquired = gcvTRUE;
++ }
++ else if (status != gcvSTATUS_TIMEOUT)
++ {
++ /* Other errors. */
++ gcmkONERROR(status);
++ }
++ /* Ignore gcvSTATUS_TIMEOUT and leave globalAcquired as gcvFALSE.
++ ** gcvSTATUS_TIMEOUT means global semaphore has already
++ ** been acquired before this operation, so even if we fail,
++ ** we should not release it in our error handling. It should be
++ ** released by the next successful global gcvPOWER_ON. */
++ }
++
++ /* Global power management can't be aborted, so sync with
++ ** proceeding last commit. */
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ for (;;)
++ {
++ /* Check if GPU is present and awake. */
++ status = _IsGPUPresent(Hardware);
++
++ /* Check if the GPU is not responding. */
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Turn off the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvFALSE, gcvFALSE));
++
++ Hardware->clockState = gcvFALSE;
++ Hardware->powerState = gcvFALSE;
++
++ /* Wait a little. */
++ gckOS_Delay(os, 1);
++
++ /* Turn on the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ /* We need to initialize the hardware and start the command
++ * processor. */
++ flag |= gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_START;
++ }
++ else
++ {
++ /* Test for error. */
++ gcmkONERROR(status);
++
++ /* Break out of loop. */
++ break;
++ }
++ }
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ gctBOOL idle;
++ gctINT32 atomValue;
++
++ /* For global operation, all pending commits have already been
++ ** blocked by globalSemaphore or powerSemaphore.*/
++ if (!global)
++ {
++ /* Check commit atom. */
++ gcmkONERROR(gckOS_AtomGet(os, command->atomCommit, &atomValue));
++
++ if (atomValue > 0)
++ {
++ /* Commits are pending - abort power management. */
++ status = broadcast ? gcvSTATUS_CHIP_NOT_READY
++ : gcvSTATUS_MORE_DATA;
++ goto OnError;
++ }
++ }
++
++ if (broadcast)
++ {
++ /* Check for idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle));
++
++ if (!idle)
++ {
++ status = gcvSTATUS_CHIP_NOT_READY;
++ goto OnError;
++ }
++ }
++
++ else
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvTRUE));
++ commitEntered = gcvTRUE;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(command, requested));
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ commitEntered = gcvFALSE;
++
++ /* Wait to finish all commands. */
++ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE));
++ }
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++ }
++
++ if (flag & gcvPOWER_FLAG_STOP)
++ {
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ /* Stop the Isr. */
++ if (Hardware->stopIsr)
++ {
++ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++ }
++
++ /* Flush Cache before Power Off. */
++ if (flag & gcvPOWER_FLAG_POWER_OFF)
++ {
++ if (Hardware->clockState == gcvFALSE)
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ gcvTRUE,
++ gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++
++ if (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE)
++ {
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clocks[0]));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clocks[0])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++ }
++
++ gcmkONERROR(gckCOMMAND_Start(command));
++
++ gcmkONERROR(_FlushCache(Hardware, command));
++
++ gckOS_Delay(gcvNULL, 1);
++
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ flag |= gcvPOWER_FLAG_CLOCK_OFF;
++ }
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++ /* Only process this when hardware is enabled. */
++ if (Hardware->clockState && Hardware->powerState
++ /* Don't touch clock control if dynamic frequency scaling is available. */
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE
++ )
++ {
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ if (Hardware->identity.chipModel == gcv4000
++ && ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222)))
++ {
++ clock &= ~2U;
++ }
++ }
++
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(Hardware,
++ Hardware->allowFastClear,
++ Hardware->allowCompression));
++
++ /* Force the command queue to reload the next context. */
++ command->currContext = gcvNULL;
++
++ /* Need to config mmu after command start. */
++ configMmu = gcvTRUE;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++ if (flag & gcvPOWER_FLAG_START)
++ {
++ /* Start the command processor. */
++ gcmkONERROR(gckCOMMAND_Start(command));
++ commandStarted = gcvTRUE;
++
++ if (Hardware->startIsr)
++ {
++ /* Start the Isr. */
++ gcmkONERROR(Hardware->startIsr(Hardware->isrContext, Hardware->core));
++ isrStarted = gcvTRUE;
++ }
++ }
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++
++ if (global)
++ {
++ /* Verify global semaphore has been acquired already before
++ ** we release it.
++ ** If it was acquired, gckOS_TryAcquireSemaphore will return
++ ** gcvSTATUS_TIMEOUT and we release it. Otherwise, global
++ ** semaphore will be acquried now, but it still is released
++ ** immediately. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status != gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++#if gcdDVFS
++ if (State == gcvPOWER_ON && Hardware->kernel->dvfs)
++ {
++ gckDVFS_Start(Hardware->kernel->dvfs);
++ }
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commandStarted)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Stop(command, gcvFALSE));
++ }
++
++ if (isrStarted)
++ {
++ gcmkVERIFY_OK(Hardware->stopIsr(Hardware->isrContext, Hardware->core));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ }
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (globalAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ if(!Hardware->powerManagementLock)
++ {
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++
++ Hardware->powerManagement = PowerManagement;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementLock
++**
++** Disable dynamic GPU power management switch.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL Lock
++** Power Mangement Lock State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementLock(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Lock
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagementLock = Lock;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++/*******************************************************************************
++**
++** gckHARDWARE_SetGpuProfiler
++**
++** Configure GPU profiler function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL GpuProfiler
++** GOU Profiler State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (GpuProfiler == gcvTRUE)
++ {
++ gctUINT32 data = 0;
++
++ /* Need to disable clock gating when doing profiling. */
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++ }
++
++ Hardware->gpuProfiler = GpuProfiler;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ )
++{
++ gceSTATUS status;
++ gctUINT32 clock;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x FscaleValue=%d", Hardware, FscaleValue);
++
++ gcmkVERIFY_ARGUMENT(FscaleValue > 0 && FscaleValue <= 64);
++
++ gcmkONERROR(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ Hardware->powerOnFscaleVal = FscaleValue;
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (FscaleValue) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ /* Restore all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ )
++{
++ *FscaleValue = Hardware->powerOnFscaleVal;
++ *MinFscaleValue = Hardware->minFscaleValue;
++ *MaxFscaleValue = 64;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetMinFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT MinFscaleValue
++ )
++{
++ if (MinFscaleValue >= 1 && MinFscaleValue <= 64)
++ {
++ Hardware->minFscaleValue = MinFscaleValue;
++ }
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle, address;
++ gctBOOL isIdle;
++
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 pendingInterrupt;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ isIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ isIdle = gcvFALSE;
++ }
++
++ else
++ {
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++ /* Test if address is inside the last WAIT/LINK sequence. */
++ if ((address >= Hardware->lastWaitLink)
++ && (address <= Hardware->lastWaitLink + 16)
++ )
++ {
++ /* FE is in last WAIT/LINK and the pipe is idle. */
++ isIdle = gcvTRUE;
++ }
++ else
++ {
++ /* FE is not in WAIT/LINK yet. */
++ isIdle = gcvFALSE;
++ }
++ }
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkONERROR(gckOS_AtomGet(
++ Hardware->os,
++ Hardware->kernel->eventObj->interruptCount,
++ &pendingInterrupt
++ ));
++
++ if (pendingInterrupt)
++ {
++ isIdle = gcvFALSE;
++ }
++#endif
++
++ *IsIdle = isIdle;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** Handy macros that will help in reading those debug registers.
++*/
++
++#define gcmkREAD_DEBUG_REGISTER(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &profiler->data))
++
++#define gcmkREAD_DEBUG_REGISTER_N(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &data))
++
++#define gcmkRESET_DEBUG_REGISTER(control, block) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 15))); \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 0)))
++
++/*******************************************************************************
++**
++** gckHARDWARE_ProfileEngine2D
++**
++** Read the profile registers available in the 2D engine and sets them in the
++** profile. The function will also reset the pixelsRendered counter every time.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** OPTIONAL gcs2D_PROFILE_PTR Profile
++** Pointer to a gcs2D_Profile structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ )
++{
++ gceSTATUS status;
++ gcs2D_PROFILE_PTR profiler = Profile;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Profile != gcvNULL)
++ {
++ /* Read the cycle count. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &Profile->cycleCount));
++
++ /* Read pixels rendered by 2D engine. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &profiler->pixelsRendered));
++
++ /* Reset counter. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++ gctUINT i, clock;
++ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
++ gctUINT32 totalRead, totalWrite;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
++#if VIVANTE_PROFILER_CONTEXT
++#define gcmkUPDATE_PROFILE_DATA(data) \
++ profilerHistroy->data += profiler->data
++
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = Hardware->kernel->command;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os, command->mutexContextSeq, gcvINFINITE
++ ));
++
++ /* Read the counters. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ profiler, &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ /* Reset counters. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os, command->mutexContextSeq
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gctUINT32
++CalcDelta(
++ IN gctUINT32 new,
++ IN gctUINT32 old
++ )
++{
++ if (new >= old)
++ {
++ return new - old;
++ }
++ else
++ {
++ return (gctUINT32)((gctUINT64)new + 0x100000000ll - old);
++ }
++}
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = &Context->latestProfiler;
++ gcsPROFILER_COUNTERS * profilerHistroy = &Context->histroyProfiler;
++ gctUINT i, clock;
++ gctUINT32 colorKilled = 0, colorDrawn = 0, depthKilled = 0, depthDrawn = 0;
++ gctUINT32 totalRead, totalWrite;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 temp;
++ gctBOOL needResetShader = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x Context=0x%x", Hardware, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ chipModel = Hardware->identity.chipModel;
++ chipRevision = Hardware->identity.chipRevision;
++ if (chipModel == gcv2000 || (chipModel == gcv2100 && chipRevision == 0x5118))
++ {
++ needResetShader = gcvTRUE;
++ }
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuTotalCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuIdleCyclesCounter);
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++ gcmkUPDATE_PROFILE_DATA(gpuTotalRead64BytesPerFrame);
++ gcmkUPDATE_PROFILE_DATA(gpuTotalWrite64BytesPerFrame);
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_depth_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_depth_pipe);
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->ps_inst_counter;
++ profiler->ps_inst_counter = CalcDelta(temp, Context->prevPSInstCount);
++ Context->prevPSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(ps_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_pixel_counter;
++ profiler->rendered_pixel_counter = CalcDelta(temp, Context->prevPSPixelCount);
++ Context->prevPSPixelCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_pixel_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vs_inst_counter;
++ profiler->vs_inst_counter = CalcDelta(temp, Context->prevVSInstCount);
++ Context->prevVSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vs_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_vertice_counter;
++ profiler->rendered_vertice_counter = CalcDelta(temp, Context->prevVSVertexCount);
++ Context->prevVSVertexCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_vertice_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_branch_inst_counter;
++ profiler->vtx_branch_inst_counter = CalcDelta(temp, Context->prevVSBranchInstCount);
++ Context->prevVSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_texld_inst_counter;
++ profiler->vtx_texld_inst_counter = CalcDelta(temp, Context->prevVSTexInstCount);
++ Context->prevVSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_branch_inst_counter;
++ profiler->pxl_branch_inst_counter = CalcDelta(temp, Context->prevPSBranchInstCount);
++ Context->prevPSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_texld_inst_counter;
++ profiler->pxl_texld_inst_counter = CalcDelta(temp, Context->prevPSTexInstCount);
++ Context->prevPSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_vtx_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_output_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_depth_clipped_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_trivial_rejected_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_culled_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_triangle_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_lines_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_pixel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_quad_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_quad_count_after_early_z);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_primitive_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_pipe_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_prefetch_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_bilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_trilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_discarded_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_in_8B_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_hit_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_IP);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_write_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_read_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_data_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
++#if VIVANTE_PROFILER_NEW
++gceSTATUS
++gckHARDWARE_InitProfiler(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ Hardware->powerBaseAddress +
++ 0x00104,
++ 0x00000000));
++
++ control = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable pulse-eater. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++
++ /* Hardware reset. */
++ status = gckOS_ResetGPU(Hardware->os, Hardware->core);
++
++ if (gcmIS_ERROR(status))
++ {
++ if (Hardware->identity.chipRevision < 0x4600)
++ {
++ /* Not supported - we need the isolation bit. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ /* Soft reset. */
++ gcmkONERROR(_ResetGPU(Hardware, Hardware->os, Hardware->core));
++ }
++
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ /* Jump to address into which GPU should run if it doesn't stuck. */
++ gcmkONERROR(gckHARDWARE_Execute(Hardware, Hardware->kernel->restoreAddress, 16));
++
++ gcmkPRINT("[galcore]: recovery done");
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkPRINT("[galcore]: Hardware not reset successfully, give up");
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Test if we have a new Memory Controller. */
++ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))))
++ {
++ /* No base address required. */
++ *BaseAddress = 0;
++ }
++ else
++ {
++ /* Get the base address from the OS. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, BaseAddress));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ )
++{
++ gctBOOL need = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x State=0x%08x", Hardware, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(NeedBase != gcvNULL);
++
++ /* Make sure this is a load state. */
++ if (((((gctUINT32) (State)) >> (0 ? 31:27) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))))
++ {
++#if gcdENABLE_3D
++ /* Get the state address. */
++ switch ((((((gctUINT32) (State)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) ))
++ {
++ case 0x0596:
++ case 0x0597:
++ case 0x0599:
++ case 0x059A:
++ case 0x05A9:
++ /* These states need a TRUE physical address. */
++ need = gcvTRUE;
++ break;
++ }
++#else
++ /* 2D addresses don't need a base address. */
++#endif
++ }
++
++ /* Return the flag. */
++ *NeedBase = need;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedBase=%d", *NeedBase);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Hardware=0x%x, StartIsr=0x%x, StopIsr=0x%x, Context=0x%x",
++ Hardware, StartIsr, StopIsr, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (StartIsr == gcvNULL ||
++ StopIsr == gcvNULL ||
++ Context == gcvNULL)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ Hardware->startIsr = StartIsr;
++ Hardware->stopIsr = StopIsr;
++ Hardware->isrContext = Context;
++
++ /* Success. */
++ gcmkFOOTER();
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Compose
++**
++** Start a composition.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ )
++{
++#if gcdENABLE_3D
++ gceSTATUS status;
++ gctUINT32_PTR triggerState;
++
++ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x Logical=0x%x"
++ " Offset=%d Size=%d EventID=%d",
++ Hardware, Physical, Logical, Offset, Size, EventID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(((Size + 8) & 63) == 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Program the trigger state. */
++ triggerState = (gctUINT32_PTR) ((gctUINT8_PTR) Logical + Offset + Size);
++ triggerState[0] = 0x0C03;
++ triggerState[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16))) | (((gctUINT32) ((gctUINT32) (EventID) & ((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16)))
++ ;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Hardware->os, ProcessID, gcvNULL,
++ (gctUINT32)Physical, Logical, Offset + Size
++ ));
++#endif
++
++ /* Start composition. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os, Hardware->core, 0x00554,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ /* Return the status. */
++ return gcvSTATUS_NOT_SUPPORTED;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_IsFeatureAvailable
++**
++** Verifies whether the specified feature is available in hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gceFEATURE Feature
++** Feature to be verified.
++*/
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ )
++{
++ gctBOOL available;
++
++ gcmkHEADER_ARG("Hardware=0x%x Feature=%d", Hardware, Feature);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Only features needed by common kernel logic added here. */
++ switch (Feature)
++ {
++ case gcvFEATURE_END_EVENT:
++ /*available = gcmVERIFYFIELDVALUE(Hardware->identity.chipMinorFeatures2,
++ GC_MINOR_FEATURES2, END_EVENT, AVAILABLE
++ );*/
++ available = gcvFALSE;
++ break;
++
++ case gcvFEATURE_MC20:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))));
++ break;
++
++ case gcvFEATURE_EARLY_Z:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ case gcvFEATURE_HZ:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))));
++ break;
++
++ case gcvFEATURE_NEW_HZ:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))));
++ break;
++
++ case gcvFEATURE_FAST_MSAA:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))));
++ break;
++
++ case gcvFEATURE_SMALL_MSAA:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++ break;
++
++ case gcvFEATURE_DYNAMIC_FREQUENCY_SCALING:
++ /* This feature doesn't apply for 2D cores. */
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 14:14) & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))))
++ && ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++
++ if (Hardware->identity.chipModel == gcv1000 &&
++ (Hardware->identity.chipRevision == 0x5039 ||
++ Hardware->identity.chipRevision == 0x5040))
++ {
++ available = gcvFALSE;
++ }
++ break;
++
++ case gcvFEATURE_ACE:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++ break;
++
++ case gcvFEATURE_HALTI2:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_2D:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_3D:
++#if gcdENABLE_3D
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++#else
++ available = gcvFALSE;
++#endif
++ break;
++
++ case gcvFEATURE_FC_FLUSH_STALL:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 31:31) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))));
++ break;
++
++ default:
++ gcmkFATAL("Invalid feature has been requested.");
++ available = gcvFALSE;
++ }
++
++ /* Return result. */
++ gcmkFOOTER_ARG("%d", available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE);
++ return available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpMMUException
++**
++** Dump the MMU debug info on an MMU exception.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ )
++{
++ gctUINT32 mmu = 0;
++ gctUINT32 mmuStatus = 0;
++ gctUINT32 address = 0;
++ gctUINT32 i = 0;
++ gctUINT32 mtlb = 0;
++ gctUINT32 stlb = 0;
++ gctUINT32 offset = 0;
++#if gcdPROCESS_ADDRESS_SPACE
++ gcsDATABASE_PTR database;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkPRINT("GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ Hardware->core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** MMU ERROR DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00188,
++ &mmuStatus));
++
++ gcmkPRINT(" MMU status = 0x%08X\n", mmuStatus);
++
++ for (i = 0; i < 4; i += 1)
++ {
++ mmu = mmuStatus & 0xF;
++ mmuStatus >>= 4;
++
++ if (mmu == 0)
++ {
++ continue;
++ }
++
++ switch (mmu)
++ {
++ case 1:
++ gcmkPRINT(" MMU%d: slave not present\n", i);
++ break;
++
++ case 2:
++ gcmkPRINT(" MMU%d: page not present\n", i);
++ break;
++
++ case 3:
++ gcmkPRINT(" MMU%d: write violation\n", i);
++ break;
++
++ default:
++ gcmkPRINT(" MMU%d: unknown state\n", i);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00190 + i * 4,
++ &address));
++
++ mtlb = (address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ stlb = (address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++ offset = address & gcdMMU_OFFSET_4K_MASK;
++
++ gcmkPRINT(" MMU%d: exception address = 0x%08X\n", i, address);
++
++ gcmkPRINT(" MTLB entry = %d\n", mtlb);
++
++ gcmkPRINT(" STLB entry = %d\n", stlb);
++
++ gcmkPRINT(" Offset = 0x%08X (%d)\n", offset, offset);
++
++ gckMMU_DumpPageTableEntry(Hardware->kernel->mmu, address);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ for (i = 0; i < gcmCOUNTOF(Hardware->kernel->db->db); ++i)
++ {
++ for (database = Hardware->kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ gcmkPRINT(" database [%d] :", database->processID);
++ gckMMU_DumpPageTableEntry(database->mmu, address);
++ }
++ }
++#endif
++ }
++
++ gckHARDWARE_DumpGPUState(Hardware);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpGPUState
++**
++** Dump the GPU debug registers.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ )
++{
++ static gctCONST_STRING _cmdState[] =
++ {
++ "PAR_IDLE_ST", "PAR_DEC_ST", "PAR_ADR0_ST", "PAR_LOAD0_ST",
++ "PAR_ADR1_ST", "PAR_LOAD1_ST", "PAR_3DADR_ST", "PAR_3DCMD_ST",
++ "PAR_3DCNTL_ST", "PAR_3DIDXCNTL_ST", "PAR_INITREQDMA_ST",
++ "PAR_DRAWIDX_ST", "PAR_DRAW_ST", "PAR_2DRECT0_ST", "PAR_2DRECT1_ST",
++ "PAR_2DDATA0_ST", "PAR_2DDATA1_ST", "PAR_WAITFIFO_ST", "PAR_WAIT_ST",
++ "PAR_LINK_ST", "PAR_END_ST", "PAR_STALL_ST"
++ };
++
++ static gctCONST_STRING _cmdDmaState[] =
++ {
++ "CMD_IDLE_ST", "CMD_START_ST", "CMD_REQ_ST", "CMD_END_ST"
++ };
++
++ static gctCONST_STRING _cmdFetState[] =
++ {
++ "FET_IDLE_ST", "FET_RAMVALID_ST", "FET_VALID_ST"
++ };
++
++ static gctCONST_STRING _reqDmaState[] =
++ {
++ "REQ_IDLE_ST", "REQ_WAITIDX_ST", "REQ_CAL_ST"
++ };
++
++ static gctCONST_STRING _calState[] =
++ {
++ "CAL_IDLE_ST", "CAL_LDADR_ST", "CAL_IDXCALC_ST"
++ };
++
++ static gctCONST_STRING _veReqState[] =
++ {
++ "VER_IDLE_ST", "VER_CKCACHE_ST", "VER_MISS_ST"
++ };
++
++ static gcsiDEBUG_REGISTERS _dbgRegs[] =
++ {
++ { "RA", 0x474, 16, 0x448, 16, 0x12344321 },
++ { "TX", 0x474, 24, 0x44C, 16, 0x12211221 },
++ { "FE", 0x470, 0, 0x450, 16, 0xBABEF00D },
++ { "PE", 0x470, 16, 0x454, 16, 0xBABEF00D },
++ { "DE", 0x470, 8, 0x458, 16, 0xBABEF00D },
++ { "SH", 0x470, 24, 0x45C, 16, 0xDEADBEEF },
++ { "PA", 0x474, 0, 0x460, 16, 0x0000AAAA },
++ { "SE", 0x474, 8, 0x464, 16, 0x5E5E5E5E },
++ { "MC", 0x478, 0, 0x468, 16, 0x12345678 },
++ { "HI", 0x478, 8, 0x46C, 16, 0xAAAAAAAA }
++ };
++
++ static gctUINT32 _otherRegs[] =
++ {
++ 0x040, 0x044, 0x04C, 0x050, 0x054, 0x058, 0x05C, 0x060,
++ 0x43c, 0x440, 0x444, 0x414,
++ };
++
++ gceSTATUS status;
++ gckKERNEL kernel = gcvNULL;
++ gctUINT32 idle = 0, axi = 0;
++ gctUINT32 dmaAddress1 = 0, dmaAddress2 = 0;
++ gctUINT32 dmaState1 = 0, dmaState2 = 0;
++ gctUINT32 dmaLow = 0, dmaHigh = 0;
++ gctUINT32 cmdState = 0, cmdDmaState = 0, cmdFetState = 0;
++ gctUINT32 dmaReqState = 0, calState = 0, veReqState = 0;
++ gctUINT i;
++ gctUINT pipe = 0, pixelPipes = 0;
++ gctUINT32 control = 0, oldControl = 0;
++ gckOS os = Hardware->os;
++ gceCORE core = Hardware->core;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ kernel = Hardware->kernel;
++
++ gcmkPRINT_N(12, "GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ pixelPipes = Hardware->identity.pixelPipes
++ ? Hardware->identity.pixelPipes
++ : 1;
++
++ /* Reset register values. */
++ idle = axi =
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 =
++ dmaLow = dmaHigh = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkONERROR(_VerifyDMA(
++ os, core, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++ cmdState = dmaState2 & 0x1F;
++ cmdDmaState = (dmaState2 >> 8) & 0x03;
++ cmdFetState = (dmaState2 >> 10) & 0x03;
++ dmaReqState = (dmaState2 >> 12) & 0x03;
++ calState = (dmaState2 >> 14) & 0x03;
++ veReqState = (dmaState2 >> 16) & 0x03;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x004, &idle));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x00C, &axi));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x668, &dmaLow));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x66C, &dmaHigh));
++
++ gcmkPRINT_N(0, "**************************\n");
++ gcmkPRINT_N(0, "*** GPU STATE DUMP ***\n");
++ gcmkPRINT_N(0, "**************************\n");
++
++ gcmkPRINT_N(4, " axi = 0x%08X\n", axi);
++
++ gcmkPRINT_N(4, " idle = 0x%08X\n", idle);
++ if ((idle & 0x00000001) == 0) gcmkPRINT_N(0, " FE not idle\n");
++ if ((idle & 0x00000002) == 0) gcmkPRINT_N(0, " DE not idle\n");
++ if ((idle & 0x00000004) == 0) gcmkPRINT_N(0, " PE not idle\n");
++ if ((idle & 0x00000008) == 0) gcmkPRINT_N(0, " SH not idle\n");
++ if ((idle & 0x00000010) == 0) gcmkPRINT_N(0, " PA not idle\n");
++ if ((idle & 0x00000020) == 0) gcmkPRINT_N(0, " SE not idle\n");
++ if ((idle & 0x00000040) == 0) gcmkPRINT_N(0, " RA not idle\n");
++ if ((idle & 0x00000080) == 0) gcmkPRINT_N(0, " TX not idle\n");
++ if ((idle & 0x00000100) == 0) gcmkPRINT_N(0, " VG not idle\n");
++ if ((idle & 0x00000200) == 0) gcmkPRINT_N(0, " IM not idle\n");
++ if ((idle & 0x00000400) == 0) gcmkPRINT_N(0, " FP not idle\n");
++ if ((idle & 0x00000800) == 0) gcmkPRINT_N(0, " TS not idle\n");
++ if ((idle & 0x80000000) != 0) gcmkPRINT_N(0, " AXI low power mode\n");
++
++ if (
++ (dmaAddress1 == dmaAddress2)
++ && (dmaState1 == dmaState2)
++ )
++ {
++ gcmkPRINT_N(0, " DMA appears to be stuck at this address:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ }
++ else
++ {
++ if (dmaAddress1 == dmaAddress2)
++ {
++ gcmkPRINT_N(0, " DMA address is constant, but state is changing:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState2);
++ }
++ else
++ {
++ gcmkPRINT_N(0, " DMA is running; known addresses are:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress2);
++ }
++ }
++
++ gcmkPRINT_N(4, " dmaLow = 0x%08X\n", dmaLow);
++ gcmkPRINT_N(4, " dmaHigh = 0x%08X\n", dmaHigh);
++ gcmkPRINT_N(4, " dmaState = 0x%08X\n", dmaState2);
++ gcmkPRINT_N(8, " command state = %d (%s)\n", cmdState, _cmdState [cmdState]);
++ gcmkPRINT_N(8, " command DMA state = %d (%s)\n", cmdDmaState, _cmdDmaState[cmdDmaState]);
++ gcmkPRINT_N(8, " command fetch state = %d (%s)\n", cmdFetState, _cmdFetState[cmdFetState]);
++ gcmkPRINT_N(8, " DMA request state = %d (%s)\n", dmaReqState, _reqDmaState[dmaReqState]);
++ gcmkPRINT_N(8, " cal state = %d (%s)\n", calState, _calState [calState]);
++ gcmkPRINT_N(8, " VE request state = %d (%s)\n", veReqState, _veReqState [veReqState]);
++
++ /* Record control. */
++ gckOS_ReadRegisterEx(os, core, 0x0, &oldControl);
++
++ for (pipe = 0; pipe < pixelPipes; pipe++)
++ {
++ gcmkPRINT_N(4, " Debug registers of pipe[%d]:\n", pipe);
++
++ /* Switch pipe. */
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x0, &control));
++ control &= ~(0xF << 20);
++ control |= (pipe << 20);
++ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, control));
++
++ for (i = 0; i < gcmCOUNTOF(_dbgRegs); i += 1)
++ {
++ gcmkONERROR(_DumpDebugRegisters(os, core, &_dbgRegs[i]));
++ }
++
++ gcmkPRINT_N(0, " Other Registers:\n");
++ for (i = 0; i < gcmCOUNTOF(_otherRegs); i += 1)
++ {
++ gctUINT32 read;
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, _otherRegs[i], &read));
++ gcmkPRINT_N(12, " [0x%04X] 0x%08X\n", _otherRegs[i], read);
++ }
++ }
++
++ if (kernel->hardware->identity.chipFeatures & (1 << 4))
++ {
++ gctUINT32 read0, read1, write;
++
++ read0 = read1 = write = 0;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x43C, &read0));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x440, &read1));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x444, &write));
++
++ gcmkPRINT_N(4, " read0 = 0x%08X\n", read0);
++ gcmkPRINT_N(4, " read1 = 0x%08X\n", read1);
++ gcmkPRINT_N(4, " write = 0x%08X\n", write);
++ }
++
++ /* Restore control. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, oldControl));
++
++ /* dump stack. */
++ gckOS_DumpCallStack(os);
++
++OnError:
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckHARDWARE_ReadPerformanceRegister(
++ IN gckHARDWARE Hardware,
++ IN gctUINT PerformanceAddress,
++ IN gctUINT IndexAddress,
++ IN gctUINT IndexShift,
++ IN gctUINT Index,
++ OUT gctUINT32_PTR Value
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x PerformanceAddress=0x%x IndexAddress=0x%x "
++ "IndexShift=%u Index=%u",
++ Hardware, PerformanceAddress, IndexAddress, IndexShift,
++ Index);
++
++ /* Write the index. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ IndexAddress,
++ Index << IndexShift));
++
++ /* Read the register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ PerformanceAddress,
++ Value));
++
++ /* Test for reset. */
++ if (Index == 15)
++ {
++ /* Index another register to get out of reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, IndexAddress, 0));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=0x%x", *Value);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ )
++{
++ gceSTATUS status;
++ gctUINT i, clock;
++ gcsHAL_FRAME_INFO info;
++#if gcdFRAME_DB_RESET
++ gctUINT reset;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Get profile tick. */
++ gcmkONERROR(gckOS_GetProfileTick(&info.ticks));
++
++ /* Read SH counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 4,
++ &info.shaderCycles));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 9,
++ &info.vsInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 12,
++ &info.vsTextureCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 7,
++ &info.psInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 14,
++ &info.psTextureCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read PA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 3,
++ &info.vertexCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 4,
++ &info.primitiveCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 7,
++ &info.rejectedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 8,
++ &info.culledPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 6,
++ &info.clippedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 5,
++ &info.outPrimitives));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 15,
++ &reset));
++#endif
++
++ /* Read RA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 3,
++ &info.inPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 11,
++ &info.culledQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 1,
++ &info.totalQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 2,
++ &info.quadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 0,
++ &info.totalPixelCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Read TX counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 0,
++ &info.bilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 1,
++ &info.trilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 8,
++ &info.txHitCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 9,
++ &info.txMissCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 6,
++ &info.txBytes8));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* Read cycle registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &info.cycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &info.idleCycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &info.mcCycles[i]));
++
++ /* Read bandwidth registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0005C,
++ &info.readRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &info.readBytes8[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00050,
++ &info.writeRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &info.writeBytes8[i]));
++
++ /* Read PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 0,
++ &info.colorKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 2,
++ &info.colorDrawn[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 1,
++ &info.depthKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 3,
++ &info.depthDrawn[i]));
++ }
++
++ /* Zero out remaning reserved counters. */
++ for (; i < 8; ++i)
++ {
++ info.readBytes8[i] = 0;
++ info.writeBytes8[i] = 0;
++ info.cycles[i] = 0;
++ info.idleCycles[i] = 0;
++ info.mcCycles[i] = 0;
++ info.readRequests[i] = 0;
++ info.writeRequests[i] = 0;
++ info.colorKilled[i] = 0;
++ info.colorDrawn[i] = 0;
++ info.depthKilled[i] = 0;
++ info.depthDrawn[i] = 0;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset cycle and bandwidth counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 1));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ 0));
++
++#if gcdFRAME_DB_RESET
++ /* Reset PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Copy to user. */
++ gcmkONERROR(gckOS_CopyToUserData(Hardware->os,
++ &info,
++ FrameInfo,
++ gcmSIZEOF(info)));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdDVFS
++#define READ_FROM_EATER1 0
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ )
++{
++ gctUINT32 debug1;
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Load != gcvNULL);
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00110,
++ Load));
++#if READ_FROM_EATER1
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00134,
++ Load));
++#endif
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00114,
++ &debug1));
++
++ /* Patch result of 0x110 with result of 0x114. */
++ if ((debug1 & 0xFF) == 1)
++ {
++ *Load &= ~0xFF;
++ *Load |= 1;
++ }
++
++ if (((debug1 & 0xFF00) >> 8) == 1)
++ {
++ *Load &= ~(0xFF << 8);
++ *Load |= 1 << 8;
++ }
++
++ if (((debug1 & 0xFF0000) >> 16) == 1)
++ {
++ *Load &= ~(0xFF << 16);
++ *Load |= 1 << 16;
++ }
++
++ if (((debug1 & 0xFF000000) >> 24) == 1)
++ {
++ *Load &= ~(0xFF << 24);
++ *Load |= 1 << 24;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 Frequency
++ )
++{
++ gceSTATUS status;
++ gctUINT32 period;
++ gctUINT32 eater;
++
++#if READ_FROM_EATER1
++ gctUINT32 period1;
++ gctUINT32 eater1;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%X Frequency=%d", Hardware, Frequency);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ period = 0;
++
++ while((64 << period) < (gcdDVFS_ANAYLSE_WINDOW * Frequency * 1000) )
++ {
++ period++;
++ }
++
++#if READ_FROM_EATER1
++ /*
++ * Peroid = F * 1000 * 1000 / (60 * 16 * 1024);
++ */
++ period1 = Frequency * 6250 / 6114;
++#endif
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ /* Get current configure. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &eater));
++
++ /* Change peroid. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (eater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (period) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))));
++
++#if READ_FROM_EATER1
++ /* Config eater1. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ &eater1));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ ((((gctUINT32) (eater1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16))) | (((gctUINT32) ((gctUINT32) (period1) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16)))));
++#endif
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 data;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "DVFS Configure=0x%X",
++ data);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_PrepareFunctions
++**
++** Generate command buffer snippets which will be used by gckHARDWARE, by which
++** gckHARDWARE can manipulate GPU by FE command without using gckCOMMAND to avoid
++** race condition and deadlock.
++**
++** Notice:
++** 1. Each snippet can only be executed when GPU is idle.
++** 2. Execution is triggered by AHB (0x658)
++** 3. Each snippet followed by END so software can sync with GPU by checking GPU
++** idle
++** 4. It is transparent to gckCOMMAND command buffer.
++**
++** Existing Snippets:
++** 1. MMU Configure
++** For new MMU, after GPU is reset, FE execute this command sequence to enble MMU.
++*/
++gceSTATUS
++gckHARDWARE_PrepareFunctions(
++ gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckOS os;
++ gctUINT32 offset = 0;
++ gctUINT32 mmuBytes;
++ gctUINT32 endBytes;
++ gctUINT8_PTR logical;
++
++ gcmkHEADER_ARG("%x", Hardware);
++
++ os = Hardware->os;
++
++ gcmkVERIFY_OK(gckOS_GetPageSize(os, &Hardware->functionBytes));
++
++ /* Allocate a command buffer. */
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ os,
++ gcvFALSE,
++ &Hardware->functionBytes,
++ &Hardware->functionPhysical,
++ &Hardware->functionLogical
++ ));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ os,
++ Hardware->functionLogical,
++ &Hardware->functionAddress
++ ));
++
++ if (Hardware->mmuVersion > 0)
++ {
++ /* MMU configure command sequence. */
++ logical = (gctUINT8_PTR)Hardware->functionLogical + offset;
++
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address
++ = Hardware->functionAddress + offset;
++
++ gcmkONERROR(gckHARDWARE_SetMMUStates(
++ Hardware,
++ Hardware->kernel->mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Hardware->kernel->mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ logical,
++ &mmuBytes
++ ));
++
++ offset += mmuBytes;
++
++ logical = (gctUINT8_PTR)Hardware->functionLogical + offset;
++
++ gcmkONERROR(gckHARDWARE_End(
++ Hardware,
++ gcvNULL,
++ &endBytes
++ ));
++
++ gcmkONERROR(gckHARDWARE_End(
++ Hardware,
++ logical,
++ &endBytes
++ ));
++
++ offset += endBytes;
++
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes = mmuBytes + endBytes;
++ }
++
++ gcmkASSERT(offset < Hardware->functionBytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h 2016-06-19 22:11:55.129151555 +0200
+@@ -0,0 +1,160 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_h_
++#define __gc_hal_kernel_hardware_h_
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_hardware_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++typedef enum {
++ gcvHARDWARE_FUNCTION_MMU,
++ gcvHARDWARE_FUNCTION_FLUSH,
++
++ gcvHARDWARE_FUNCTION_NUM,
++}
++gceHARDWARE_FUNCTION;
++
++
++typedef struct _gcsHARWARE_FUNCTION
++{
++ /* Entry of the function. */
++ gctUINT32 address;
++
++ /* Bytes of the function. */
++ gctUINT32 bytes;
++}
++gcsHARDWARE_FUNCTION;
++
++/* gckHARDWARE object. */
++struct _gckHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gctKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Pointer to gctOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Chip characteristics. */
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctBOOL allowFastClear;
++ gctBOOL allowCompression;
++ gctUINT32 powerBaseAddress;
++ gctBOOL extraEventStates;
++
++ /* Big endian */
++ gctBOOL bigEndian;
++
++ /* Chip status */
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gctUINT32 lastWaitLink;
++ gctUINT32 lastEnd;
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER globalSemaphore;
++
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++
++ gctUINT32 mmuVersion;
++
++ /* Whether use new MMU. It is meaningless
++ ** for old MMU since old MMU is always enabled.
++ */
++ gctBOOL enableMMU;
++
++ /* Type */
++ gceHARDWARE_TYPE type;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gctUINT32 powerOnFscaleVal;
++#endif
++ gctPOINTER pageTableDirty;
++
++#if gcdLINK_QUEUE_SIZE
++ struct _gckLINKQUEUE linkQueue;
++#endif
++
++ gctBOOL powerManagement;
++ gctBOOL powerManagementLock;
++ gctBOOL gpuProfiler;
++
++ gctBOOL endAfterFlushMmuCache;
++
++ gctUINT32 minFscaleValue;
++
++ gctPOINTER pendingEvent;
++
++ /* Function used by gckHARDWARE. */
++ gctPHYS_ADDR functionPhysical;
++ gctPOINTER functionLogical;
++ gctUINT32 functionAddress;
++ gctSIZE_T functionBytes;
++
++ gcsHARDWARE_FUNCTION functions[gcvHARDWARE_FUNCTION_NUM];
++};
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ );
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c 2016-06-19 22:11:55.129151555 +0200
+@@ -0,0 +1,679 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++
++/*
++ * -----------------------
++ * HARDWARE STATE RECORDER
++ * -----------------------
++ *
++ * State mirror buffer is used to 'mirror' hardware states since hardware
++ * states can't be dumpped. It is a context buffer which stores 'global'
++ * context.
++ *
++ * For each commit, state recorder
++ * 1) Records context buffer (if there is) and command buffers in this commit.
++ * 2) Parse those buffers to estimate the state changed.
++ * 3) Stores result to a mirror buffer.
++ *
++ * == Commit 0 ====================================================================
++ *
++ * Context Buffer 0
++ *
++ * Command Buffer 0
++ *
++ * Mirror Buffer 0 <- Context Buffer 0 + Command Buffer 0
++ *
++ * == Commit 1 ====================================================================
++ *
++ * Command Buffer 1
++ *
++ * Mirror Buffer 1 <- Command buffer 1 + Mirror Buffer 0
++ *
++ * == Commit 2 ====================================================================
++ *
++ * Context Buffer 2 (optional)
++ *
++ * Command Buffer 2
++ *
++ * Mirror Buffer 2 <- Command buffer 2 + Context Buffer 2 + Mirror Buffer 1
++ *
++ * == Commit N ====================================================================
++ *
++ * For Commit N, these buffers are needed to reproduce hardware's behavior in
++ * this commit.
++ *
++ * Mirror Buffer [N - 1] : State Mirror accumlated by past commits,
++ * which is used to restore hardware state.
++ * Context Buffer [N] :
++ * Command Buffer [N] : Command buffer executed by hardware in this commit.
++ *
++ * If sequence of states programming matters, hardware's behavior can't be reproduced,
++ * but the state values stored in mirror buffer are assuring.
++ */
++
++/* Queue size. */
++#define gcdNUM_RECORDS 6
++
++typedef struct _gcsPARSER_HANDLER * gckPARSER_HANDLER;
++
++typedef void
++(*HandlerFunction)(
++ IN gckPARSER_HANDLER Handler,
++ IN gctUINT32 Addr,
++ IN gctUINT32 Data
++ );
++
++typedef struct _gcsPARSER_HANDLER
++{
++ gctUINT32 type;
++ gctUINT32 cmd;
++ gctPOINTER private;
++ HandlerFunction function;
++}
++gcsPARSER_HANDLER;
++
++typedef struct _gcsPARSER * gckPARSER;
++typedef struct _gcsPARSER
++{
++ gctUINT8_PTR currentCmdBufferAddr;
++
++ /* Current command. */
++ gctUINT32 lo;
++ gctUINT32 hi;
++
++ gctUINT8 cmdOpcode;
++ gctUINT16 cmdAddr;
++ gctUINT32 cmdSize;
++ gctUINT32 cmdRectCount;
++ gctUINT8 skip;
++ gctUINT32 skipCount;
++
++ gctBOOL allow;
++
++ /* Callback used by parser to handle a command. */
++ gckPARSER_HANDLER commandHandler;
++}
++gcsPARSER;
++
++typedef struct _gcsMIRROR
++{
++ gctUINT32_PTR logical[gcdNUM_RECORDS];
++ gctUINT32 bytes;
++ gcsSTATE_MAP_PTR map;
++ gctUINT32 stateCount;
++}
++gcsMIRROR;
++
++typedef struct _gcsDELTA
++{
++ gctUINT64 commitStamp;
++ gctUINT32_PTR command;
++ gctUINT32 commandBytes;
++ gctUINT32_PTR context;
++ gctUINT32 contextBytes;
++}
++gcsDELTA;
++
++typedef struct _gcsRECORDER
++{
++ gckOS os;
++ gcsMIRROR mirror;
++ gcsDELTA deltas[gcdNUM_RECORDS];
++
++ /* Index of current record. */
++ gctUINT index;
++
++ /* Number of records. */
++ gctUINT num;
++
++ /* Plugin used by gckPARSER. */
++ gcsPARSER_HANDLER recorderHandler;
++ gckPARSER parser;
++}
++gcsRECORDER;
++
++
++/******************************************************************************\
++***************************** Command Buffer Parser ****************************
++\******************************************************************************/
++
++/*
++** Command buffer parser checks command buffer in FE's view to make sure there
++** is no format error.
++**
++** Parser provide a callback mechnisam, so plug-in can be added to implement
++** other functions.
++*/
++
++static void
++_HandleLoadState(
++ IN OUT gckPARSER Parser
++ )
++{
++ gctUINT i;
++ gctUINT32_PTR data = (gctUINT32_PTR)Parser->currentCmdBufferAddr;
++ gctUINT32 cmdAddr = Parser->cmdAddr;
++
++ if (Parser->commandHandler == gcvNULL
++ || Parser->commandHandler->cmd != 0x01
++ )
++ {
++ /* No handler for this command. */
++ return;
++ }
++
++ for (i = 0; i < Parser->cmdSize; i++)
++ {
++ Parser->commandHandler->function(Parser->commandHandler, cmdAddr, *data);
++
++ /* Advance to next state. */
++ cmdAddr++;
++ data++;
++ }
++}
++
++static void
++_GetCommand(
++ IN OUT gckPARSER Parser
++ )
++{
++ gctUINT32 * buffer = (gctUINT32 *)Parser->currentCmdBufferAddr;
++
++ gctUINT16 cmdRectCount;
++ gctUINT16 cmdDataCount;
++
++ Parser->hi = buffer[0];
++ Parser->lo = buffer[1];
++
++ Parser->cmdOpcode = (((((gctUINT32) (Parser->hi)) >> (0 ? 31:27)) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) );
++ Parser->cmdRectCount = 1;
++
++ switch (Parser->cmdOpcode)
++ {
++ case 0x01:
++ /* Extract count. */
++ Parser->cmdSize = (((((gctUINT32) (Parser->hi)) >> (0 ? 25:16)) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1)))))) );
++ if (Parser->cmdSize == 0)
++ {
++ /* 0 means 1024. */
++ Parser->cmdSize = 1024;
++ }
++ Parser->skip = (Parser->cmdSize & 0x1) ? 0 : 1;
++
++ /* Extract address. */
++ Parser->cmdAddr = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) );
++
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 4;
++ Parser->skipCount = Parser->cmdSize + Parser->skip;
++ break;
++
++ case 0x05:
++ Parser->cmdSize = 4;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x06:
++ Parser->cmdSize = 5;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x0C:
++ Parser->cmdSize = 3;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x09:
++ Parser->cmdSize = 2;
++ Parser->cmdAddr = 0x0F16;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x04:
++ Parser->cmdSize = 1;
++ Parser->cmdAddr = 0x0F06;
++
++ cmdRectCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ cmdDataCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 26:16)) & ((gctUINT32) ((((1 ? 26:16) - (0 ? 26:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:16) - (0 ? 26:16) + 1)))))) );
++
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2)
++ + cmdRectCount * 2
++ + gcmALIGN(cmdDataCount, 2);
++
++ Parser->cmdRectCount = cmdRectCount;
++ break;
++
++ case 0x03:
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8;
++ Parser->skipCount = 0;
++ break;
++
++ case 0x02:
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8;
++ Parser->skipCount = 0;
++ break;
++
++ default:
++ /* Unknown command is a risk. */
++ Parser->allow = gcvFALSE;
++ break;
++ }
++}
++
++static void
++_ParseCommand(
++ IN OUT gckPARSER Parser
++ )
++{
++ switch(Parser->cmdOpcode)
++ {
++ case 0x01:
++ _HandleLoadState(Parser);
++ break;
++ case 0x05:
++ case 0x06:
++ case 0x0C:
++ break;
++ case 0x04:
++ break;
++ default:
++ break;
++ }
++
++ /* Advance to next command. */
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr
++ + (Parser->skipCount << 2);
++}
++
++gceSTATUS
++gckPARSER_Parse(
++ IN gckPARSER Parser,
++ IN gctUINT8_PTR Buffer,
++ IN gctUINT32 Bytes
++ )
++{
++ gckPARSER parser = Parser;
++ gctUINT8_PTR end = (gctUINT8_PTR)Buffer + Bytes;
++
++ /* Initialize parser. */
++ parser->currentCmdBufferAddr = (gctUINT8_PTR)Buffer;
++ parser->skip = 0;
++ parser->allow = gcvTRUE;
++
++ /* Go through command buffer until reaching the end
++ ** or meeting an error. */
++ do
++ {
++ _GetCommand(parser);
++
++ _ParseCommand(parser);
++ }
++ while ((parser->currentCmdBufferAddr < end) && (parser->allow == gcvTRUE));
++
++ if (parser->allow == gcvFALSE)
++ {
++ /* Error detected. */
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckPARSER_RegisterCommandHandler
++**
++** Register a command handler which will be called when parser get a command.
++**
++*/
++gceSTATUS
++gckPARSER_RegisterCommandHandler(
++ IN gckPARSER Parser,
++ IN gckPARSER_HANDLER Handler
++ )
++{
++ Parser->commandHandler = Handler;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckPARSER_Construct(
++ IN gckOS Os,
++ IN gckPARSER_HANDLER Handler,
++ OUT gckPARSER * Parser
++ )
++{
++ gceSTATUS status;
++ gckPARSER pointer;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsPARSER), (gctPOINTER *)&pointer));
++
++ /* Put it here temp, should have a more general plug-in mechnisam. */
++ pointer->commandHandler = Handler;
++
++ *Parser = pointer;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++void
++gckPARSER_Destroy(
++ IN gckOS Os,
++ IN gckPARSER Parser
++ )
++{
++ gcmkOS_SAFE_FREE(Os, Parser);
++}
++
++/******************************************************************************\
++**************************** Hardware States Recorder **************************
++\******************************************************************************/
++
++static void
++_RecodeState(
++ IN gckPARSER_HANDLER Handler,
++ IN gctUINT32 Addr,
++ IN gctUINT32 Data
++ )
++{
++ gcmkVERIFY_OK(gckRECORDER_UpdateMirror(Handler->private, Addr, Data));
++}
++
++static gctUINT
++_Previous(
++ IN gctUINT Index
++ )
++{
++ if (Index == 0)
++ {
++ return gcdNUM_RECORDS - 1;
++ }
++
++ return Index - 1;
++}
++
++static gctUINT
++_Next(
++ IN gctUINT Index
++ )
++{
++ return (Index + 1) % gcdNUM_RECORDS;
++}
++
++gceSTATUS
++gckRECORDER_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ OUT gckRECORDER * Recorder
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gckRECORDER recorder = gcvNULL;
++ gctUINT32 mapSize;
++ gctUINT i;
++ gctBOOL virtualCommandBuffer = Hardware->kernel->virtualCommandBuffer;
++
++ /* TODO: We only need context buffer and state map, it should be able to get without construct a
++ ** new context.
++ ** Now it is leaked, since we can't free it when command buffer is gone.
++ */
++
++ /* MMU is not ready now. */
++ Hardware->kernel->virtualCommandBuffer = gcvFALSE;
++
++ gcmkONERROR(gckCONTEXT_Construct(Os, Hardware, 0, &context));
++
++ /* Restore. */
++ Hardware->kernel->virtualCommandBuffer = virtualCommandBuffer;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsRECORDER), (gctPOINTER *)&recorder));
++
++ gckOS_ZeroMemory(recorder, gcmSIZEOF(gcsRECORDER));
++
++ /* Copy state map. */
++ recorder->mirror.stateCount = context->stateCount;
++
++ mapSize = context->stateCount * gcmSIZEOF(gcsSTATE_MAP);
++
++ gcmkONERROR(gckOS_Allocate(Os, mapSize, (gctPOINTER *)&recorder->mirror.map));
++
++ gckOS_MemCopy(recorder->mirror.map, context->map, mapSize);
++
++ /* Copy context buffer. */
++ recorder->mirror.bytes = context->totalSize;
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->mirror.logical[i]));
++ gckOS_MemCopy(recorder->mirror.logical[i], context->buffer->logical, context->totalSize);
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ /* TODO : Optimize size. */
++ gcmkONERROR(gckOS_Allocate(Os, gcdCMD_BUFFER_SIZE, (gctPOINTER *)&recorder->deltas[i].command));
++ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->deltas[i].context));
++ }
++
++ recorder->index = 0;
++ recorder->num = 0;
++
++ /* Initialize Parser plugin. */
++ recorder->recorderHandler.cmd = 0x01;
++ recorder->recorderHandler.private = recorder;
++ recorder->recorderHandler.function = _RecodeState;
++
++ gcmkONERROR(gckPARSER_Construct(Os, &recorder->recorderHandler, &recorder->parser));
++
++ recorder->os = Os;
++
++ *Recorder = recorder;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (recorder)
++ {
++ gckRECORDER_Destory(Os, recorder);
++ }
++
++ return status;
++}
++
++gceSTATUS
++gckRECORDER_Destory(
++ IN gckOS Os,
++ IN gckRECORDER Recorder
++ )
++{
++ gctUINT i;
++
++ if (Recorder->mirror.map)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->mirror.map);
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ if (Recorder->mirror.logical[i])
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->mirror.logical[i]);
++ }
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ if (Recorder->deltas[i].command)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].command);
++ }
++
++ if (Recorder->deltas[i].context)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].context);
++ }
++ }
++
++ if (Recorder->parser)
++ {
++ gckPARSER_Destroy(Os, Recorder->parser);
++ }
++
++ gcmkOS_SAFE_FREE(Os, Recorder);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckRECORDER_UpdateMirror(
++ IN gckRECORDER Recorder,
++ IN gctUINT32 State,
++ IN gctUINT32 Data
++ )
++{
++ gctUINT32 index;
++ gcsSTATE_MAP_PTR map = Recorder->mirror.map;
++ gctUINT32_PTR buffer = Recorder->mirror.logical[Recorder->index];
++
++ if (State >= Recorder->mirror.stateCount)
++ {
++ /* Ignore them just like HW does. */
++ return gcvSTATUS_OK;
++ }
++
++ index = map[State].index;
++
++ if (index)
++ {
++ buffer[index] = Data;
++ }
++
++ return gcvSTATUS_OK;
++}
++
++void
++gckRECORDER_AdvanceIndex(
++ IN gckRECORDER Recorder,
++ IN gctUINT64 CommitStamp
++ )
++{
++ /* Get next record. */
++ gctUINT next = (Recorder->index + 1) % gcdNUM_RECORDS;
++
++ /* Record stamp of this commit. */
++ Recorder->deltas[Recorder->index].commitStamp = CommitStamp;
++
++ /* Mirror of next record is mirror of this record and delta in next record. */
++ gckOS_MemCopy(Recorder->mirror.logical[next],
++ Recorder->mirror.logical[Recorder->index], Recorder->mirror.bytes);
++
++ /* Advance to next record. */
++ Recorder->index = next;
++
++ Recorder->num = gcmMIN(Recorder->num + 1, gcdNUM_RECORDS - 1);
++
++
++ /* Reset delta. */
++ Recorder->deltas[Recorder->index].commandBytes = 0;
++ Recorder->deltas[Recorder->index].contextBytes = 0;
++}
++
++void
++gckRECORDER_Record(
++ IN gckRECORDER Recorder,
++ IN gctUINT8_PTR CommandBuffer,
++ IN gctUINT32 CommandBytes,
++ IN gctUINT8_PTR ContextBuffer,
++ IN gctUINT32 ContextBytes
++ )
++{
++ gcsDELTA * delta = &Recorder->deltas[Recorder->index];
++
++ if (CommandBytes != 0xFFFFFFFF)
++ {
++ gckPARSER_Parse(Recorder->parser, CommandBuffer, CommandBytes);
++ gckOS_MemCopy(delta->command, CommandBuffer, CommandBytes);
++ delta->commandBytes = CommandBytes;
++ }
++
++ if (ContextBytes != 0xFFFFFFFF)
++ {
++ gckPARSER_Parse(Recorder->parser, ContextBuffer, ContextBytes);
++ gckOS_MemCopy(delta->context, ContextBuffer, ContextBytes);
++ delta->contextBytes = ContextBytes;
++ }
++}
++
++void
++gckRECORDER_Dump(
++ IN gckRECORDER Recorder
++ )
++{
++ gctUINT last = Recorder->index;
++ gctUINT previous;
++ gctUINT i;
++ gcsMIRROR *mirror = &Recorder->mirror;
++ gcsDELTA *delta;
++ gckOS os = Recorder->os;
++
++ for (i = 0; i < Recorder->num; i++)
++ {
++ last = _Previous(last);
++ }
++
++ for (i = 0; i < Recorder->num; i++)
++ {
++ delta = &Recorder->deltas[last];
++
++ /* Dump record */
++ gcmkPRINT("#[commit %llu]", delta->commitStamp);
++
++ if (delta->commitStamp)
++ {
++ previous = _Previous(last);
++
++ gcmkPRINT("#[mirror]");
++ gckOS_DumpBuffer(os, mirror->logical[previous], mirror->bytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++ }
++
++ if (delta->contextBytes)
++ {
++ gckOS_DumpBuffer(os, delta->context, delta->contextBytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++ }
++
++ gckOS_DumpBuffer(os, delta->command, delta->commandBytes, gceDUMP_BUFFER_USER, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++
++ last = _Next(last);
++ }
++}
++
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c 2016-06-19 22:11:55.129151555 +0200
+@@ -0,0 +1,932 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_InitializeInfo
++**
++** Initialize architecture dependent command buffer information.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ /* Reset interrupts. */
++ Command->info.feBufferInt = -1;
++ Command->info.tsOverflowInt = -1;
++
++ /* Set command buffer attributes. */
++ Command->info.addressAlignment = 64;
++ Command->info.commandAlignment = 8;
++
++ /* Determine command alignment address mask. */
++ Command->info.addressMask = ((((gctUINT32) (Command->info.addressAlignment - 1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0 ) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Query the number of bytes needed by the STATE command. */
++ gcmkERR_BREAK(gckVGCOMMAND_StateCommand(
++ Command, 0x0, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.stateCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RESTART command. */
++ gcmkERR_BREAK(gckVGCOMMAND_RestartCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.restartCommandSize
++ ));
++
++ /* Query the number of bytes needed by the FETCH command. */
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.fetchCommandSize
++ ));
++
++ /* Query the number of bytes needed by the CALL command. */
++ gcmkERR_BREAK(gckVGCOMMAND_CallCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.callCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RETURN command. */
++ gcmkERR_BREAK(gckVGCOMMAND_ReturnCommand(
++ Command, gcvNULL,
++ &Command->info.returnCommandSize
++ ));
++
++ /* Query the number of bytes needed by the EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, gcvNULL, gcvBLOCK_PIXEL, -1,
++ &Command->info.eventCommandSize
++ ));
++
++ /* Query the number of bytes needed by the END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command, gcvNULL, -1,
++ &Command->info.endCommandSize
++ ));
++
++ /* Determine the tail reserve size. */
++ Command->info.staticTailSize = gcmMAX(
++ Command->info.fetchCommandSize,
++ gcmMAX(
++ Command->info.returnCommandSize,
++ Command->info.endCommandSize
++ )
++ );
++
++ /* Determine the maximum tail size. */
++ Command->info.dynamicTailSize
++ = Command->info.staticTailSize
++ + Command->info.eventCommandSize * gcvBLOCK_COUNT;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_StateCommand
++**
++** Append a STATE command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctUINT32 Pipe
++** Harwdare destination pipe.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** STATE command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 Address
++** Starting register address of the state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT32 Count
++** Number of states in state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the STATE command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the STATE command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Pipe=0x%x Logical=0x%x Address=0x%x Count=0x%x Bytes = 0x%x",
++ Command, Pipe, Logical, Address, Count, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) ((gctUINT32) (Pipe) & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LOAD_STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_RestartCommand
++**
++** Form a RESTART command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RESTART command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this RESTART
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this RESTART command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RESTART command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RESTART command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++ gctUINT32 beginEndMark;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Determine Begin/End flag. */
++ beginEndMark = (FetchCount > 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)));
++
++ /* Append RESTART. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x9 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)))
++ | beginEndMark;
++
++ buffer[1]
++ = FetchAddress;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RESTART command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_FetchCommand
++**
++** Form a FETCH command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** FETCH command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this FETCH
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this FETCH command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the FETCH command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the FETCH command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append FETCH. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x5 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the FETCH command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LINK. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_CallCommand
++**
++** Append a CALL command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** CALL command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this CALL
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this CALL command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the CALL command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the CALL command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append CALL. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x6 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the CALL command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_ReturnCommand
++**
++** Append a RETURN command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RETURN command at or gcvNULL to query the size of the command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RETURN command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RETURN command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Bytes = 0x%x",
++ Command, Logical, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append RETURN. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x7 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RETURN command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EventCommand
++**
++** Form an EVENT command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** EVENT command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gceBLOCK Block
++** Block that will generate the interrupt.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Block=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, Block, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ typedef struct _gcsEVENTSTATES
++ {
++ /* Chips before VG21 use these values. */
++ gctUINT eventFromFE;
++ gctUINT eventFromPE;
++
++ /* VG21 chips and later use SOURCE field. */
++ gctUINT eventSource;
++ }
++ gcsEVENTSTATES;
++
++ static gcsEVENTSTATES states[] =
++ {
++ /* gcvBLOCK_COMMAND */
++ {
++ (gctUINT)~0,
++ (gctUINT)~0,
++ (gctUINT)~0
++ },
++
++ /* gcvBLOCK_TESSELLATOR */
++ {
++ 0x0,
++ 0x1,
++ 0x10
++ },
++
++ /* gcvBLOCK_TESSELLATOR2 */
++ {
++ 0x0,
++ 0x1,
++ 0x12
++ },
++
++ /* gcvBLOCK_TESSELLATOR3 */
++ {
++ 0x0,
++ 0x1,
++ 0x14
++ },
++
++ /* gcvBLOCK_RASTER */
++ {
++ 0x0,
++ 0x1,
++ 0x07,
++ },
++
++ /* gcvBLOCK_VG */
++ {
++ 0x0,
++ 0x1,
++ 0x0F
++ },
++
++ /* gcvBLOCK_VG2 */
++ {
++ 0x0,
++ 0x1,
++ 0x11
++ },
++
++ /* gcvBLOCK_VG3 */
++ {
++ 0x0,
++ 0x1,
++ 0x13
++ },
++
++ /* gcvBLOCK_PIXEL */
++ {
++ 0x0,
++ 0x1,
++ 0x07
++ },
++ };
++
++ /* Verify block ID. */
++ gcmkVERIFY_ARGUMENT(gcmIS_VALID_INDEX(Block, states));
++
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++
++ /* Determine chip version. */
++ if (Command->vg21)
++ {
++ /* Get the event source for the block. */
++ gctUINT eventSource = states[Block].eventSource;
++
++ /* Supported? */
++ if (eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) ((gctUINT32) (eventSource) & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ else
++ {
++ /* Get the event source for the block. */
++ gctUINT eventFromFE = states[Block].eventFromFE;
++ gctUINT eventFromPE = states[Block].eventFromPE;
++
++ /* Supported? */
++ if (eventFromFE == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (eventFromFE) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (eventFromPE) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Make sure the events are directly supported for the block. */
++ if (states[Block].eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine event source. */
++ if (Block == gcvBLOCK_COMMAND)
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++ else
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EndCommand
++**
++** Form an END command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** END command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append END. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR memory;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ memory = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ memory[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ memory[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Append END. */
++ memory[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 16;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h 2016-06-19 22:11:55.129151555 +0200
+@@ -0,0 +1,319 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_command_vg_h_
++#define __gc_hal_kernel_hardware_command_vg_h_
++
++/******************************************************************************\
++******************* Task and Interrupt Management Structures. ******************
++\******************************************************************************/
++
++/* Task storage header. */
++typedef struct _gcsTASK_STORAGE * gcsTASK_STORAGE_PTR;
++typedef struct _gcsTASK_STORAGE
++{
++ /* Next allocated storage buffer. */
++ gcsTASK_STORAGE_PTR next;
++}
++gcsTASK_STORAGE;
++
++/* Task container header. */
++typedef struct _gcsTASK_CONTAINER * gcsTASK_CONTAINER_PTR;
++typedef struct _gcsTASK_CONTAINER
++{
++ /* The number of tasks left to be processed in the container. */
++ gctINT referenceCount;
++
++ /* Size of the buffer. */
++ gctUINT size;
++
++ /* Link to the previous and the next allocated containers. */
++ gcsTASK_CONTAINER_PTR allocPrev;
++ gcsTASK_CONTAINER_PTR allocNext;
++
++ /* Link to the previous and the next containers in the free list. */
++ gcsTASK_CONTAINER_PTR freePrev;
++ gcsTASK_CONTAINER_PTR freeNext;
++}
++gcsTASK_CONTAINER;
++
++/* Kernel space task master table entry. */
++typedef struct _gcsBLOCK_TASK_ENTRY * gcsBLOCK_TASK_ENTRY_PTR;
++typedef struct _gcsBLOCK_TASK_ENTRY
++{
++ /* Pointer to the current task container for the block. */
++ gcsTASK_CONTAINER_PTR container;
++
++ /* Pointer to the current task data within the container. */
++ gcsTASK_HEADER_PTR task;
++
++ /* Pointer to the last link task within the container. */
++ gcsTASK_LINK_PTR link;
++
++ /* Number of interrupts allocated for this block. */
++ gctUINT interruptCount;
++
++ /* The index of the current interrupt. */
++ gctUINT interruptIndex;
++
++ /* Interrupt semaphore. */
++ gctSEMAPHORE interruptSemaphore;
++
++ /* Interrupt value array. */
++ gctINT32 interruptArray[32];
++}
++gcsBLOCK_TASK_ENTRY;
++
++
++/******************************************************************************\
++********************* Command Queue Management Structures. *********************
++\******************************************************************************/
++
++/* Command queue kernel element pointer. */
++typedef struct _gcsKERNEL_CMDQUEUE * gcsKERNEL_CMDQUEUE_PTR;
++
++/* Command queue object handler function type. */
++typedef gceSTATUS (* gctOBJECT_HANDLER) (
++ gckVGKERNEL Kernel,
++ gcsKERNEL_CMDQUEUE_PTR Entry
++ );
++
++/* Command queue kernel element. */
++typedef struct _gcsKERNEL_CMDQUEUE
++{
++ /* The number of buffers in the queue. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Pointer to the object handler function. */
++ gctOBJECT_HANDLER handler;
++}
++gcsKERNEL_CMDQUEUE;
++
++/* Command queue header. */
++typedef struct _gcsKERNEL_QUEUE_HEADER * gcsKERNEL_QUEUE_HEADER_PTR;
++typedef struct _gcsKERNEL_QUEUE_HEADER
++{
++ /* The size of the buffer in bytes. */
++ gctUINT size;
++
++ /* The number of pending entries to be processed. */
++ volatile gctUINT pending;
++
++ /* The current command queue entry. */
++ gcsKERNEL_CMDQUEUE_PTR currentEntry;
++
++ /* Next buffer. */
++ gcsKERNEL_QUEUE_HEADER_PTR next;
++}
++gcsKERNEL_QUEUE_HEADER;
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++/* gckVGCOMMAND object. */
++struct _gckVGCOMMAND
++{
++ /***************************************************************************
++ ** Object data and pointers.
++ */
++
++ gcsOBJECT object;
++ gckVGKERNEL kernel;
++ gckOS os;
++ gckVGHARDWARE hardware;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++
++ /***************************************************************************
++ ** Enable command queue dumping.
++ */
++
++ gctBOOL enableDumping;
++
++
++ /***************************************************************************
++ ** Bus Error interrupt.
++ */
++
++ gctINT32 busErrorInt;
++
++
++ /***************************************************************************
++ ** Command buffer information.
++ */
++
++ gcsCOMMAND_BUFFER_INFO info;
++
++
++ /***************************************************************************
++ ** Synchronization objects.
++ */
++
++ gctPOINTER queueMutex;
++ gctPOINTER taskMutex;
++ gctPOINTER commitMutex;
++
++
++ /***************************************************************************
++ ** Task management.
++ */
++
++ /* The head of the storage buffer linked list. */
++ gcsTASK_STORAGE_PTR taskStorage;
++
++ /* Allocation size. */
++ gctUINT taskStorageGranularity;
++ gctUINT taskStorageUsable;
++
++ /* The free container list. */
++ gcsTASK_CONTAINER_PTR taskFreeHead;
++ gcsTASK_CONTAINER_PTR taskFreeTail;
++
++ /* Task table */
++ gcsBLOCK_TASK_ENTRY taskTable[gcvBLOCK_COUNT];
++
++
++ /***************************************************************************
++ ** Command queue.
++ */
++
++ /* Pointer to the allocated queue memory. */
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++
++ /* Pointer to the current available queue from which new queue entries
++ will be allocated. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* If different from queueHead, points to the command queue which is
++ currently being executed by the hardware. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++
++ /* Points to the queue to merge the tail with when the tail is processed. */
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++
++ /* Queue overflow counter. */
++ gctUINT queueOverflow;
++
++
++ /***************************************************************************
++ ** Context.
++ */
++
++ /* Context counter used for unique ID. */
++ gctUINT64 contextCounter;
++
++ /* Current context ID. */
++ gctUINT64 currentContext;
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++ gctINT32 powerStallInt;
++ gcsCMDBUFFER_PTR powerStallBuffer;
++ gctSIGNAL powerStallSignal;
++
++};
++
++/******************************************************************************\
++************************ gckVGCOMMAND Object Internal API. ***********************
++\******************************************************************************/
++
++/* Initialize architecture dependent command buffer information. */
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ );
++
++/* Form a STATE command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a RESTART command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a FETCH command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a CALL command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a RETURN command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form an EVENT command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form an END command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ );
++
++#endif /* __gc_hal_kernel_hardware_command_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c 2016-06-19 22:11:55.133151292 +0200
+@@ -0,0 +1,2119 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++ gcvPOWER_FLAG_NOP = 1 << 11,
++}
++gcePOWER_FLAGS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_ResetGPU(
++ IN gckOS Os
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ /* Read register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00104,
++ 0x00000000));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32 * ChipFeatures,
++ OUT gctUINT32 * ChipMinorFeatures,
++ OUT gctUINT32 * ChipMinorFeatures2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 chipIdentity;
++
++ do
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, 0x00018, &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ *ChipModel = gcv500;
++ *ChipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00020,
++ (gctUINT32 *) ChipModel));
++
++ /* Read CHIP_REV register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00024,
++ ChipRevision));
++ }
++
++ /* Read chip feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x0001C, ChipFeatures
++ ));
++
++ /* Read chip minor feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00034, ChipMinorFeatures
++ ));
++
++ /* Read chip minor feature register #2. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00074, ChipMinorFeatures2
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_VERBOSE,
++ "ChipModel=0x%08X\n"
++ "ChipRevision=0x%08X\n"
++ "ChipFeatures=0x%08X\n"
++ "ChipMinorFeatures=0x%08X\n"
++ "ChipMinorFeatures2=0x%08X\n",
++ *ChipModel,
++ *ChipRevision,
++ *ChipFeatures,
++ *ChipMinorFeatures,
++ *ChipMinorFeatures2
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_VGPowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckVGHARDWARE hardware = (gckVGHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++/******************************************************************************\
++****************************** gckVGHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Construct
++**
++** Construct a new gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** OUTPUT:
++**
++** gckVGHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckVGHARDWARE
++** object.
++*/
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ )
++{
++ gckVGHARDWARE hardware = gcvNULL;
++ gceSTATUS status;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x ", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ status = _ResetGPU(Os);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ /* Identify the hardware. */
++ gcmkERR_BREAK(_IdentifyHardware(Os,
++ &chipModel, &chipRevision,
++ &chipFeatures, &chipMinorFeatures, &chipMinorFeatures2
++ ));
++
++ /* Allocate the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckVGHARDWARE), (gctPOINTER *) &hardware
++ ));
++
++ /* Initialize the gckVGHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++
++ /* Set chip identity. */
++ hardware->chipModel = chipModel;
++ hardware->chipRevision = chipRevision;
++ hardware->chipFeatures = chipFeatures;
++ hardware->chipMinorFeatures = chipMinorFeatures;
++ hardware->chipMinorFeatures2 = chipMinorFeatures2;
++
++ hardware->powerMutex = gcvNULL;
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->chipPowerStateGlobal = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTime = 0;
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _VGPowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ /* Determine whether FE 2.0 is present. */
++ hardware->fe20 = ((((gctUINT32) (hardware->chipFeatures)) >> (0 ? 28:28) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))));
++
++ /* Determine whether VG 2.0 is present. */
++ hardware->vg20 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 13:13) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))));
++
++ /* Determine whether VG 2.1 is present. */
++ hardware->vg21 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++
++ /* Set default event mask. */
++ hardware->eventMask = 0xFFFFFFFF;
++
++ gcmkERR_BREAK(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++
++ /* Set fast clear to auto. */
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(hardware, -1));
++
++ gcmkERR_BREAK(gckOS_CreateMutex(Os, &hardware->powerMutex));
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Return pointer to the gckVGHARDWARE object. */
++ *Hardware = hardware;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvFALSE, gcvFALSE));
++
++ if (hardware != gcvNULL && hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Free(Os, hardware));
++ }
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Destroy
++**
++** Destroy an gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ if (Hardware->powerMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(
++ Hardware->os, Hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ if (Hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++ }
++
++ /* Free the object. */
++ status = gckOS_Free(Hardware->os, Hardware);
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x InternalSize=0x%x InternalBaseAddress=0x%x InternalAlignment=0x%x"
++ "ExternalSize=0x%x ExternalBaseAddress=0x%x ExternalAlignment=0x%x HorizontalTileSize=0x%x VerticalTileSize=0x%x",
++ Hardware, InternalSize, InternalBaseAddress, InternalAlignment,
++ ExternalSize, ExternalBaseAddress, ExternalAlignment, HorizontalTileSize, VerticalTileSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gceCHIPMODEL * ChipModel
++** If 'ChipModel' is not gcvNULL, the variable it points to will
++** receive the model of the chip.
++**
++** gctUINT32 * ChipRevision
++** If 'ChipRevision' is not gcvNULL, the variable it points to will
++** receive the revision of the chip.
++**
++** gctUINT32 * ChipFeatures
++** If 'ChipFeatures' is not gcvNULL, the variable it points to will
++** receive the feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures
++** If 'ChipMinorFeatures' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures2
++** If 'ChipMinorFeatures2' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures2
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x ChipModel=0x%x ChipRevision=0x%x ChipFeatures = 0x%x ChipMinorFeatures = 0x%x ChipMinorFeatures2 = 0x%x",
++ Hardware, ChipModel, ChipRevision, ChipFeatures, ChipMinorFeatures, ChipMinorFeatures2);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Return chip model. */
++ if (ChipModel != gcvNULL)
++ {
++ *ChipModel = Hardware->chipModel;
++ }
++
++ /* Return revision number. */
++ if (ChipRevision != gcvNULL)
++ {
++ *ChipRevision = Hardware->chipRevision;
++ }
++
++ /* Return feature set. */
++ if (ChipFeatures != gcvNULL)
++ {
++ gctUINT32 features = Hardware->chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 since it did not have this *\
++ \* bit. */
++ if ((Hardware->chipModel == gcv500)
++ && (Hardware->chipRevision == 0)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ /* Mark 2D pipe as available for GC300 since it did not have this *\
++ \* bit. */
++ if (Hardware->chipModel == gcv300)
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ *ChipFeatures = features;
++ }
++
++ /* Return minor feature set. */
++ if (ChipMinorFeatures != gcvNULL)
++ {
++ *ChipMinorFeatures = Hardware->chipMinorFeatures;
++ }
++
++ /* Return minor feature set #2. */
++ if (ChipMinorFeatures2 != gcvNULL)
++ {
++ *ChipMinorFeatures2 = Hardware->chipMinorFeatures2;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertFormat
++**
++** Convert an API format to hardware parameters.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gceSURF_FORMAT Format
++** API format to convert.
++**
++** OUTPUT:
++**
++** gctUINT32 * BitsPerPixel
++** Pointer to a variable that will hold the number of bits per pixel.
++**
++** gctUINT32 * BytesPerTile
++** Pointer to a variable that will hold the number of bytes per tile.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ )
++{
++ gctUINT32 bitsPerPixel;
++ gctUINT32 bytesPerTile;
++
++ gcmkHEADER_ARG("Hardware=0x%x Format=0x%x BitsPerPixel=0x%x BytesPerTile = 0x%x",
++ Hardware, Format, BitsPerPixel, BytesPerTile);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Dispatch on format. */
++ switch (Format)
++ {
++ case gcvSURF_A1:
++ case gcvSURF_L1:
++ /* 1-bpp format. */
++ bitsPerPixel = 1;
++ bytesPerTile = (1 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_A4:
++ /* 4-bpp format. */
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_INDEX8:
++ case gcvSURF_A8:
++ case gcvSURF_L8:
++ /* 8-bpp format. */
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_YV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_NV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ /* 4444 variations. */
++ case gcvSURF_X4R4G4B4:
++ case gcvSURF_A4R4G4B4:
++ case gcvSURF_R4G4B4X4:
++ case gcvSURF_R4G4B4A4:
++ case gcvSURF_B4G4R4X4:
++ case gcvSURF_B4G4R4A4:
++ case gcvSURF_X4B4G4R4:
++ case gcvSURF_A4B4G4R4:
++
++ /* 1555 variations. */
++ case gcvSURF_X1R5G5B5:
++ case gcvSURF_A1R5G5B5:
++ case gcvSURF_R5G5B5X1:
++ case gcvSURF_R5G5B5A1:
++ case gcvSURF_X1B5G5R5:
++ case gcvSURF_A1B5G5R5:
++ case gcvSURF_B5G5R5X1:
++ case gcvSURF_B5G5R5A1:
++
++ /* 565 variations. */
++ case gcvSURF_R5G6B5:
++ case gcvSURF_B5G6R5:
++
++ case gcvSURF_A8L8:
++ case gcvSURF_YUY2:
++ case gcvSURF_UYVY:
++ case gcvSURF_D16:
++ /* 16-bpp format. */
++ bitsPerPixel = 16;
++ bytesPerTile = (16 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_X8R8G8B8:
++ case gcvSURF_A8R8G8B8:
++ case gcvSURF_X8B8G8R8:
++ case gcvSURF_A8B8G8R8:
++ case gcvSURF_R8G8B8X8:
++ case gcvSURF_R8G8B8A8:
++ case gcvSURF_B8G8R8X8:
++ case gcvSURF_B8G8R8A8:
++ case gcvSURF_D32:
++ /* 32-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_D24S8:
++ /* 24-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT1:
++ case gcvSURF_ETC1:
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT2:
++ case gcvSURF_DXT3:
++ case gcvSURF_DXT4:
++ case gcvSURF_DXT5:
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ default:
++ /* Invalid format. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Set the result. */
++ if (BitsPerPixel != gcvNULL)
++ {
++ * BitsPerPixel = bitsPerPixel;
++ }
++
++ if (BytesPerTile != gcvNULL)
++ {
++ * BytesPerTile = bytesPerTile;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Pool=0x%x Offset = 0x%x",
++ Hardware, Address, Pool, Offset);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 1:0)) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x2:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = ((((gctUINT32) (Address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address of the command buffer.
++**
++** gctSIZE_T Count
++** Number of command-sized data units to be executed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Count=0x%x",
++ Hardware, Address, Count);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ /* Enable all events. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00014,
++ Hardware->eventMask
++ ));
++
++ if (Hardware->fe20)
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00500,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00504,
++ Count
++ ));
++ }
++ else
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00654,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00658,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_AlignToTile
++**
++** Align the specified width and height to tile boundaries.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gceSURF_TYPE Type
++** Type of alignment.
++**
++** gctUINT32 * Width
++** Pointer to the width to be aligned. If 'Width' is gcvNULL, no width
++** will be aligned.
++**
++** gctUINT32 * Height
++** Pointer to the height to be aligned. If 'Height' is gcvNULL, no height
++** will be aligned.
++**
++** OUTPUT:
++**
++** gctUINT32 * Width
++** Pointer to a variable that will receive the aligned width.
++**
++** gctUINT32 * Height
++** Pointer to a variable that will receive the aligned height.
++*/
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32 * Width,
++ IN OUT gctUINT32 * Height
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Type=0x%x Width=0x%x Height=0x%x",
++ Hardware, Type, Width, Height);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Width != gcvNULL)
++ {
++ /* Align the width. */
++ *Width = gcmALIGN(*Width, (Type == gcvSURF_TEXTURE) ? 4 : 16);
++ }
++
++ if (Height != gcvNULL)
++ {
++ /* Special case for VG images. */
++ if ((*Height == 0) && (Type == gcvSURF_IMAGE))
++ {
++ *Height = 4;
++ }
++ else
++ {
++ /* Align the height. */
++ *Height = gcmALIGN(*Height, 4);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the memory in user space.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d Address=0x%x",
++ Hardware, Logical, InUserSpace, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ /* Convert logical address into a physical address. */
++ if (InUserSpace)
++ {
++ gcmkERR_BREAK(gckOS_UserLogicalToPhysical(
++ Hardware->os, Logical, &address
++ ));
++ }
++ else
++ {
++ gcmkERR_BREAK(gckOS_GetPhysicalAddress(
++ Hardware->os, Logical, &address
++ ));
++ }
++
++ /* Return hardware specific address. */
++ *Address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x SystemSize=0x%x SystemBaseAddress=0x%x",
++ Hardware, SystemSize, SystemBaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = (gctSIZE_T)(1 << 31);
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x",
++ Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ do
++ {
++ /* Convert the logical address into an hardware address. */
++ gcmkERR_BREAK(gckVGHARDWARE_ConvertLogical(Hardware, Logical,
++ gcvFALSE, &address));
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00400,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00404,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00408,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x0040C,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00410,
++ gcmkFIXADDRESS(address)));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++ gctUINT32_PTR buffer;
++
++ /* Create a shortcut to the command buffer object. */
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &commandBuffer, (gctPOINTER *) &buffer
++ ));
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Index=0x%x Offset=0x%x Address=0x%x",
++ Hardware, Index, Offset, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ address = (Index << 12) | Offset;
++
++ /* Set virtual type. */
++ address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Set the result. */
++ *Address = address;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x Data=0x%x", Hardware, Data);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ /* Read register and return. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, Data);
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ )
++{
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ if (!(((((gctUINT32) (Hardware->chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ return gcvSTATUS_OK;
++ }
++
++ do
++ {
++ if (Enable == -1)
++ {
++ Enable = (Hardware->chipModel > gcv500) ||
++ ((Hardware->chipModel == gcv500) && (Hardware->chipRevision >= 3));
++ }
++
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ &debug));
++
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++#ifdef AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION)));
++#endif
++
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ debug));
++
++ Hardware->allowFastClear = Enable;
++
++ status = gcvFALSE;
++ }
++ while (gcvFALSE);
++
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x IDs=0x%x", Hardware, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IDs != gcvNULL);
++
++ /* Read AQIntrAcknowledge register. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00010,
++ IDs);
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS _CommandStall(
++ gckVGHARDWARE Hardware)
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gctUINT32_PTR buffer;
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &command->powerStallBuffer,
++ (gctPOINTER *) &buffer
++ ));
++
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ command, buffer, gcvBLOCK_PIXEL,
++ command->powerStallInt, gcvNULL));
++
++ gcmkERR_BREAK(gckVGCOMMAND_Execute(
++ command,
++ command->powerStallBuffer
++ ));
++
++ /* Wait the signal. */
++ gcmkERR_BREAK(gckOS_WaitSignal(
++ command->os,
++ command->powerStallSignal,
++ command->kernel->kernel->timeOut));
++
++
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag/*, clock*/;
++
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL commitMutex = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++
++ gctBOOL broadcast = gcvFALSE;
++ gctUINT32 process, thread;
++ gctBOOL global = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_NOP,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_NOP,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d",
++ State);
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->powerManagement == gcvFALSE)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Acquire the power mutex. */
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 1);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State == gcvPOWER_IDLE)
++ {
++ /* gcvPOWER_IDLE_BROADCAST is from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ /*clock = clocks[State];*/
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* internal power control */
++ if (!global)
++ {
++ if (Hardware->chipPowerStateGlobal == gcvPOWER_OFF)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os,
++ command->commitMutex,
++ gcvINFINITE
++ ));
++
++ commitMutex = gcvTRUE;
++
++ gcmkONERROR(_CommandStall(Hardware));
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++
++ acquired = gcvTRUE;
++ }
++
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++
++ /* Initialize GPU here, replaced by InitializeHardware later */
++ gcmkONERROR(gckVGHARDWARE_SetMMU(Hardware, Hardware->kernel->mmu->pageTableLogical));
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(Hardware, -1));
++
++ /* Force the command queue to reload the next context. */
++ command->currentContext = 0;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ gcvCORE_VG,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++ if (global)
++ {
++ /* Save the new power state. */
++ Hardware->chipPowerStateGlobal = State;
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ /* Reset power off time */
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++
++ if (State == gcvPOWER_IDLE)
++ {
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagement = PowerManagement;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ *IsIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 8:8)) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 10:10)) & ((gctUINT32) ((((1 ? 10:10) - (0 ? 10:10) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 10:10) - (0 ? 10:10) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ *IsIdle = gcvFALSE;
++ }
++
++ else
++ {
++ *IsIdle = gcvTRUE;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h 2016-06-19 22:11:55.133151292 +0200
+@@ -0,0 +1,74 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_vg_h_
++#define __gc_hal_kernel_hardware_vg_h_
++
++/* gckHARDWARE object. */
++struct _gckVGHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckKERNEL object. */
++ gckVGKERNEL kernel;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Chip characteristics. */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++ gctBOOL allowFastClear;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++ /* Event mask. */
++ gctUINT32 eventMask;
++
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gceCHIPPOWERSTATE chipPowerStateGlobal;
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++ gctPOINTER pageTableDirty;
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++ gctBOOL powerManagement;
++};
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/config linux-3.14.72/drivers/gpu/galcore/config
+--- linux-3.14.72.orig/drivers/gpu/galcore/config 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/config 2016-06-19 22:11:55.133151292 +0200
+@@ -0,0 +1,35 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2014 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++ARCH_TYPE ?= arm
++SDK_DIR ?= $(AQROOT)/build/sdk
++VIVANTE_ENABLE_3D ?= 1
++VIVANTE_ENABLE_2D ?= 1
++VIVANTE_ENABLE_VG ?= 1
++FORCE_ALL_VIDEO_MEMORY_CACHED ?= 0
++NONPAGED_MEMORY_CACHEABLE ?= 0
++NONPAGED_MEMORY_BUFFERABLE ?= 1
++USE_BANK_ALIGNMENT ?= 1
++BANK_BIT_START ?= 13
++BANK_BIT_END ?= 15
++BANK_CHANNEL_BIT ?= 12
++PLATFORM ?= freescale/gc_hal_kernel_platform_imx6q14
++DEBUG ?= 0
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_allocator.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_allocator.c 2016-06-19 22:11:55.133151292 +0200
+@@ -0,0 +1,884 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_allocator.h"
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++
++#include "gc_hal_kernel_allocator_array.h"
++#include "gc_hal_kernel_platform.h"
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsDEFAULT_PRIV * gcsDEFAULT_PRIV_PTR;
++typedef struct _gcsDEFAULT_PRIV {
++ gctUINT32 low;
++ gctUINT32 high;
++}
++gcsDEFAULT_PRIV;
++
++/******************************************************************************\
++************************** Default Allocator Debugfs ***************************
++\******************************************************************************/
++
++int gc_usage_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckALLOCATOR Allocator = node->device;
++ gcsDEFAULT_PRIV_PTR priv = Allocator->privateData;
++
++ seq_printf(m, "low: %u bytes\n", priv->low);
++ seq_printf(m, "high: %u bytes\n", priv->high);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"lowHighUsage", gc_usage_show},
++};
++
++static void
++_DefaultAllocatorDebugfsInit(
++ IN gckALLOCATOR Allocator,
++ IN gckDEBUGFS_DIR Root
++ )
++{
++ gcmkVERIFY_OK(
++ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "default"));
++
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList),
++ Allocator
++ ));
++}
++
++static void
++_DefaultAllocatorDebugfsCleanup(
++ IN gckALLOCATOR Allocator
++ )
++{
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList)
++ ));
++
++ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir);
++}
++
++
++static void
++_NonContiguousFree(
++ IN struct page ** Pages,
++ IN gctUINT32 NumPages
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Pages=0x%X, NumPages=%d", Pages, NumPages);
++
++ gcmkASSERT(Pages != gcvNULL);
++
++ for (i = 0; i < NumPages; i++)
++ {
++ __free_page(Pages[i]);
++ }
++
++ if (is_vmalloc_addr(Pages))
++ {
++ vfree(Pages);
++ }
++ else
++ {
++ kfree(Pages);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++static struct page **
++_NonContiguousAlloc(
++ IN gctUINT32 NumPages
++ )
++{
++ struct page ** pages;
++ struct page *p;
++ gctINT i, size;
++
++ gcmkHEADER_ARG("NumPages=%lu", NumPages);
++
++ if (NumPages > totalram_pages)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ size = NumPages * sizeof(struct page *);
++
++ pages = kmalloc(size, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ pages = vmalloc(size);
++
++ if (!pages)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ }
++
++ for (i = 0; i < NumPages; i++)
++ {
++ p = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN);
++
++ if (!p)
++ {
++ _NonContiguousFree(pages, i);
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ pages[i] = p;
++ }
++
++ gcmkFOOTER_ARG("pages=0x%X", pages);
++ return pages;
++}
++
++gctSTRING
++_CreateKernelVirtualMapping(
++ IN PLINUX_MDL Mdl
++ )
++{
++ gctSTRING addr = 0;
++ gctINT numPages = Mdl->numPages;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ if (Mdl->contiguous)
++ {
++ addr = page_address(Mdl->u.contiguousPages);
++ }
++ else
++ {
++ addr = vmap(Mdl->u.nonContiguousPages,
++ numPages,
++ 0,
++ PAGE_KERNEL);
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++ }
++#else
++ struct page ** pages;
++ gctBOOL free = gcvFALSE;
++ gctINT i;
++
++ if (Mdl->contiguous)
++ {
++ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ return gcvNULL;
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ pages[i] = nth_page(Mdl->u.contiguousPages, i);
++ }
++
++ free = gcvTRUE;
++ }
++ else
++ {
++ pages = Mdl->u.nonContiguousPages;
++ }
++
++ /* ioremap() can't work on system memory since 2.6.38. */
++ addr = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL));
++
++ if (free)
++ {
++ kfree(pages);
++ }
++
++#endif
++
++ return addr;
++}
++
++void
++_DestoryKernelVirtualMapping(
++ IN gctSTRING Addr
++ )
++{
++#if !gcdNONPAGED_MEMORY_CACHEABLE
++ vunmap(Addr);
++#endif
++}
++
++void
++_UnmapUserLogical(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++)
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++}
++
++/***************************************************************************\
++************************ Default Allocator **********************************
++\***************************************************************************/
++#define C_MAX_PAGENUM (50*1024)
++static gceSTATUS
++_DefaultAlloc(
++ IN gckALLOCATOR Allocator,
++ INOUT PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flags
++ )
++{
++ gceSTATUS status;
++ gctUINT32 order;
++ gctSIZE_T bytes;
++ gctPOINTER addr = gcvNULL;
++ gctUINT32 numPages;
++ gctUINT i = 0;
++ gctBOOL contiguous = Flags & gcvALLOC_FLAG_CONTIGUOUS;
++ struct sysinfo temsysinfo;
++ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData;
++
++ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages);
++
++ numPages = NumPages;
++ bytes = NumPages * PAGE_SIZE;
++ order = get_order(bytes);
++
++ si_meminfo(&temsysinfo);
++
++ if (Flags & gcvALLOC_FLAG_MEMLIMIT)
++ {
++ if ( (temsysinfo.freeram < NumPages) || ((temsysinfo.freeram-NumPages) < C_MAX_PAGENUM) )
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ if (contiguous)
++ {
++ if (order >= MAX_ORDER)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ addr =
++ alloc_pages_exact(bytes, GFP_KERNEL | gcdNOWARN | __GFP_NORETRY);
++
++ Mdl->u.contiguousPages = addr
++ ? virt_to_page(addr)
++ : gcvNULL;
++
++ Mdl->exact = gcvTRUE;
++
++ if (Mdl->u.contiguousPages == gcvNULL)
++ {
++ Mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, order);
++
++ Mdl->exact = gcvFALSE;
++ }
++ }
++ else
++ {
++ Mdl->u.nonContiguousPages = _NonContiguousAlloc(numPages);
++ }
++
++ if (Mdl->u.contiguousPages == gcvNULL && Mdl->u.nonContiguousPages == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ struct page *page;
++
++ if (contiguous)
++ {
++ page = nth_page(Mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i);
++ }
++
++ SetPageReserved(page);
++
++ if (!PageHighMem(page) && page_to_phys(page))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CacheFlush(Allocator->os, _GetProcessID(), gcvNULL,
++ page_to_phys(page),
++ page_address(page),
++ PAGE_SIZE));
++
++ priv->low += PAGE_SIZE;
++ }
++ else
++ {
++ flush_dcache_page(page);
++
++ priv->high += PAGE_SIZE;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_DefaultFree(
++ IN gckALLOCATOR Allocator,
++ IN OUT PLINUX_MDL Mdl
++ )
++{
++ gctINT i;
++ struct page * page;
++ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData;
++
++ for (i = 0; i < Mdl->numPages; i++)
++ {
++ if (Mdl->contiguous)
++ {
++ page = nth_page(Mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i);
++ }
++
++ ClearPageReserved(page);
++
++ if (PageHighMem(page))
++ {
++ priv->high -= PAGE_SIZE;
++ }
++ else
++ {
++ priv->low -= PAGE_SIZE;
++ }
++ }
++
++ if (Mdl->contiguous)
++ {
++ if (Mdl->exact == gcvTRUE)
++ {
++ free_pages_exact(page_address(Mdl->u.contiguousPages), Mdl->numPages * PAGE_SIZE);
++ }
++ else
++ {
++ __free_pages(Mdl->u.contiguousPages, get_order(Mdl->numPages * PAGE_SIZE));
++ }
++ }
++ else
++ {
++ _NonContiguousFree(Mdl->u.nonContiguousPages, Mdl->numPages);
++ }
++}
++
++gctINT
++_DefaultMapUser(
++ gckALLOCATOR Allocator,
++ PLINUX_MDL Mdl,
++ PLINUX_MDL_MAP MdlMap,
++ gctBOOL Cacheable
++ )
++{
++
++ gctSTRING addr;
++ unsigned long start;
++ unsigned long pfn;
++ gctINT i;
++ gckOS os = Allocator->os;
++ gcsPLATFORM * platform = os->device->platform;
++
++ PLINUX_MDL mdl = Mdl;
++ PLINUX_MDL_MAP mdlMap = MdlMap;
++
++ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable);
++
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++
++ if (Cacheable == gcvFALSE)
++ {
++ /* Make this mapping non-cached. */
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ }
++
++ if (platform && platform->ops->adjustProt)
++ {
++ platform->ops->adjustProt(mdlMap->vma);
++ }
++
++ addr = mdl->addr;
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ page_to_pfn(mdl->u.contiguousPages),
++ mdlMap->vma->vm_end - mdlMap->vma->vm_start,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): unable to mmap ret",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ start = mdlMap->vma->vm_start;
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ pfn = _NonContiguousToPfn(mdl->u.nonContiguousPages, i);
++
++ if (remap_pfn_range(mdlMap->vma,
++ start,
++ pfn,
++ PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ start += PAGE_SIZE;
++ addr += PAGE_SIZE;
++ }
++ }
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_DefaultUnmapUser(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ )
++{
++ _UnmapUserLogical(Logical, Size);
++}
++
++gceSTATUS
++_DefaultMapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ )
++{
++ *Logical = _CreateKernelVirtualMapping(Mdl);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultUnmapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ )
++{
++ _DestoryKernelVirtualMapping(Logical);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultLogicalToPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ return _ConvertLogical2Physical(
++ Allocator->os, Logical, ProcessID, Mdl, Physical);
++}
++
++gceSTATUS
++_DefaultCache(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ gcmkASSERT(Mdl->pagedMem && !Mdl->contiguous);
++ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, Offset);
++
++ return gcvSTATUS_OK;
++}
++
++void
++_DefaultAllocatorDestructor(
++ IN void* PrivateData
++ )
++{
++ kfree(PrivateData);
++}
++
++/* Default allocator operations. */
++gcsALLOCATOR_OPERATIONS DefaultAllocatorOperations = {
++ .Alloc = _DefaultAlloc,
++ .Free = _DefaultFree,
++ .MapUser = _DefaultMapUser,
++ .UnmapUser = _DefaultUnmapUser,
++ .MapKernel = _DefaultMapKernel,
++ .UnmapKernel = _DefaultUnmapKernel,
++ .LogicalToPhysical = _DefaultLogicalToPhysical,
++ .Cache = _DefaultCache,
++ .Physical = _DefaultPhysical,
++};
++
++/* Default allocator entry. */
++gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++ gcsDEFAULT_PRIV_PTR priv = gcvNULL;
++
++ gcmkONERROR(
++ gckALLOCATOR_Construct(Os, &DefaultAllocatorOperations, &allocator));
++
++ priv = kzalloc(gcmSIZEOF(gcsDEFAULT_PRIV), GFP_KERNEL | gcdNOWARN);
++
++ if (!priv)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Register private data. */
++ allocator->privateData = priv;
++ allocator->privateDataDestructor = _DefaultAllocatorDestructor;
++
++ allocator->debugfsInit = _DefaultAllocatorDebugfsInit;
++ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup;
++
++ *Allocator = allocator;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++/***************************************************************************\
++************************ Allocator helper ***********************************
++\***************************************************************************/
++
++gceSTATUS
++gckALLOCATOR_Construct(
++ IN gckOS Os,
++ IN gcsALLOCATOR_OPERATIONS * Operations,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=%p, Operations=%p, Allocator=%p",
++ Os, Operations, Allocator);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Allocator != gcvNULL);
++ gcmkVERIFY_ARGUMENT
++ ( Operations
++ && Operations->Alloc
++ && Operations->Free
++ && Operations->MapUser
++ && Operations->UnmapUser
++ && Operations->MapKernel
++ && Operations->UnmapKernel
++ && Operations->LogicalToPhysical
++ && Operations->Cache
++ && Operations->Physical
++ );
++
++ gcmkONERROR(
++ gckOS_Allocate(Os, gcmSIZEOF(gcsALLOCATOR), (gctPOINTER *)&allocator));
++
++ gckOS_ZeroMemory(allocator, gcmSIZEOF(gcsALLOCATOR));
++
++ /* Record os. */
++ allocator->os = Os;
++
++ /* Set operations. */
++ allocator->ops = Operations;
++
++ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS
++ | gcvALLOC_FLAG_NON_CONTIGUOUS
++ | gcvALLOC_FLAG_CACHEABLE
++ | gcvALLOC_FLAG_MEMLIMIT;
++ ;
++
++ *Allocator = allocator;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/******************************************************************************\
++******************************** Debugfs Support *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_AllocatorDebugfsInit(
++ IN gckOS Os
++ )
++{
++ gceSTATUS status;
++ gckGALDEVICE device = Os->device;
++
++ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir;
++
++ gcmkONERROR(gckDEBUGFS_DIR_Init(dir, device->debugfsDir.root, "allocators"));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++static void
++_AllocatorDebugfsCleanup(
++ IN gckOS Os
++ )
++{
++ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir;
++
++ gckDEBUGFS_DIR_Deinit(dir);
++}
++
++/***************************************************************************\
++************************ Allocator management *******************************
++\***************************************************************************/
++
++gceSTATUS
++gckOS_ImportAllocators(
++ gckOS Os
++ )
++{
++ gceSTATUS status;
++ gctUINT i;
++ gckALLOCATOR allocator;
++
++ _AllocatorDebugfsInit(Os);
++
++ INIT_LIST_HEAD(&Os->allocatorList);
++
++ for (i = 0; i < gcmCOUNTOF(allocatorArray); i++)
++ {
++ if (allocatorArray[i].construct)
++ {
++ /* Construct allocator. */
++ status = allocatorArray[i].construct(Os, &allocator);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkPRINT("["DEVICE_NAME"]: Can't construct allocator(%s)",
++ allocatorArray[i].name);
++
++ continue;
++ }
++
++ allocator->name = allocatorArray[i].name;
++
++ if (allocator->debugfsInit)
++ {
++ /* Init allocator's debugfs. */
++ allocator->debugfsInit(allocator, &Os->allocatorDebugfsDir);
++ }
++
++ list_add_tail(&allocator->head, &Os->allocatorList);
++ }
++ }
++
++#if DEBUG
++ list_for_each_entry(allocator, &Os->allocatorList, head)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d) Allocator: %s",
++ __FUNCTION__, __LINE__,
++ allocator->name
++ );
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_FreeAllocators(
++ gckOS Os
++ )
++{
++ gckALLOCATOR allocator;
++ gckALLOCATOR temp;
++
++ list_for_each_entry_safe(allocator, temp, &Os->allocatorList, head)
++ {
++ list_del(&allocator->head);
++
++ if (allocator->debugfsCleanup)
++ {
++ /* Clean up allocator's debugfs. */
++ allocator->debugfsCleanup(allocator);
++ }
++
++ /* Free private data. */
++ if (allocator->privateDataDestructor && allocator->privateData)
++ {
++ allocator->privateDataDestructor(allocator->privateData);
++ }
++
++ gckOS_Free(Os, allocator);
++ }
++
++ _AllocatorDebugfsCleanup(Os);
++
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_allocator.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_allocator.h 2016-06-19 22:11:55.133151292 +0200
+@@ -0,0 +1,400 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_allocator_h_
++#define __gc_hal_kernel_allocator_h_
++
++#include "gc_hal_kernel_linux.h"
++
++typedef struct _gcsALLOCATOR * gckALLOCATOR;
++
++typedef struct _gcsALLOCATOR_OPERATIONS
++{
++ /**************************************************************************
++ **
++ ** Alloc
++ **
++ ** Allocte memory, request size is page aligned.
++ **
++ ** INPUT:
++ **
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_Mdl
++ ** Pointer to Mdl whichs stores information
++ ** about allocated memory.
++ **
++ ** gctSIZE_T NumPages
++ ** Number of pages need to allocate.
++ **
++ ** gctUINT32 Flag
++ ** Allocation option.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS
++ (*Alloc)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flag
++ );
++
++ /**************************************************************************
++ **
++ ** Free
++ **
++ ** Free memory.
++ **
++ ** INPUT:
++ **
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Mdl which stores information.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ void
++ (*Free)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl
++ );
++
++ /**************************************************************************
++ **
++ ** MapUser
++ **
++ ** Map memory to user space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl.
++ **
++ ** PLINUX_MDL_MAP MdlMap
++ ** Pointer to a MdlMap, mapped address is stored
++ ** in MdlMap->vmaAddr
++ **
++ ** gctBOOL Cacheable
++ ** Whether this mapping is cacheable.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gctINT
++ (*MapUser)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap,
++ IN gctBOOL Cacheable
++ );
++
++ /**************************************************************************
++ **
++ ** UnmapUser
++ **
++ ** Unmap address from user address space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** gctPOINTER Logical
++ ** Address to be unmap
++ **
++ ** gctUINT32 Size
++ ** Size of address space
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ void
++ (*UnmapUser)(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ );
++
++ /**************************************************************************
++ **
++ ** MapKernel
++ **
++ ** Map memory to kernel space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** OUTPUT:
++ ** gctPOINTER * Logical
++ ** Mapped kernel address.
++ */
++ gceSTATUS
++ (*MapKernel)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ );
++
++ /**************************************************************************
++ **
++ ** UnmapKernel
++ **
++ ** Unmap memory from kernel space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Mapped kernel address.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS
++ (*UnmapKernel)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ );
++
++ /**************************************************************************
++ **
++ ** LogicalToPhysical
++ **
++ ** Get physical address from logical address, logical
++ ** address could be user virtual address or kernel
++ ** virtual address.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Mapped kernel address.
++ **
++ ** gctUINT32 ProcessID
++ ** pid of current process.
++ ** OUTPUT:
++ **
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ */
++ gceSTATUS
++ (*LogicalToPhysical)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ );
++
++ /**************************************************************************
++ **
++ ** Cache
++ **
++ ** Maintain cache coherency.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Logical address, could be user address or kernel address
++ **
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ ** gctUINT32 Bytes
++ ** Size of memory region.
++ **
++ ** gceCACHEOPERATION Opertaion
++ ** Cache operation.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS (*Cache)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++ /**************************************************************************
++ **
++ ** Physical
++ **
++ ** Get physical address from a offset in memory region.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctUINT32 Offset
++ ** Offset in this memory region.
++ **
++ ** OUTPUT:
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ */
++ gceSTATUS (*Physical)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ );
++}
++gcsALLOCATOR_OPERATIONS;
++
++typedef struct _gcsALLOCATOR
++{
++ /* Pointer to gckOS Object. */
++ gckOS os;
++
++ /* Name. */
++ gctSTRING name;
++
++ /* Operations. */
++ gcsALLOCATOR_OPERATIONS* ops;
++
++ /* Capability of this allocator. */
++ gctUINT32 capability;
++
++ struct list_head head;
++
++ /* Debugfs entry of this allocator. */
++ gcsDEBUGFS_DIR debugfsDir;
++
++ /* Init allocator debugfs. */
++ void (*debugfsInit)(gckALLOCATOR, gckDEBUGFS_DIR);
++
++ /* Cleanup allocator debugfs. */
++ void (*debugfsCleanup)(gckALLOCATOR);
++
++ /* Private data used by customer allocator. */
++ void * privateData;
++
++ /* Private data destructor. */
++ void (*privateDataDestructor)(void *);
++}
++gcsALLOCATOR;
++
++typedef struct _gcsALLOCATOR_DESC
++{
++ /* Name of a allocator. */
++ char * name;
++
++ /* Entry function to construct a allocator. */
++ gceSTATUS (*construct)(gckOS, gckALLOCATOR *);
++}
++gcsALLOCATOR_DESC;
++
++/*
++* Helpers
++*/
++
++/* Fill a gcsALLOCATOR_DESC structure. */
++#define gcmkDEFINE_ALLOCATOR_DESC(Name, Construct) \
++ { \
++ .name = Name, \
++ .construct = Construct, \
++ }
++
++/* Construct a allocator. */
++gceSTATUS
++gckALLOCATOR_Construct(
++ IN gckOS Os,
++ IN gcsALLOCATOR_OPERATIONS * Operations,
++ OUT gckALLOCATOR * Allocator
++ );
++
++/*
++ How to implement customer allocator
++
++ Build in customer alloctor
++
++ It is recommanded that customer allocator is implmented in independent
++ source file(s) which is specified by CUSOMTER_ALLOCATOR_OBJS in Kbuld.
++
++ Register gcsALLOCATOR
++
++ For each customer specified allocator, a desciption entry must be added
++ to allocatorArray defined in gc_hal_kernel_allocator_array.h.
++
++ An entry in allocatorArray is a gcsALLOCATOR_DESC structure which describes
++ name and constructor of a gckALLOCATOR object.
++
++
++ Implement gcsALLOCATOR_DESC.init()
++
++ In gcsALLOCATOR_DESC.init(), gckALLOCATOR_Construct should be called
++ to create a gckALLOCATOR object, customer specified private data can
++ be put in gcsALLOCATOR.privateData.
++
++
++ Implement gcsALLOCATOR_OPERATIONS
++
++ When call gckALLOCATOR_Construct to create a gckALLOCATOR object, a
++ gcsALLOCATOR_OPERATIONS structure must be provided whose all members
++ implemented.
++
++*/
++#endif
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel.c 2016-06-19 22:11:55.133151292 +0200
+@@ -0,0 +1,4244 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <linux/utsname.h>
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/*******************************************************************************
++***** Version Signature *******************************************************/
++
++#define _gcmTXT2STR(t) #t
++#define gcmTXT2STR(t) _gcmTXT2STR(t)
++const char * _VERSION = "\n\0$VERSION$"
++ gcmTXT2STR(gcvVERSION_MAJOR) "."
++ gcmTXT2STR(gcvVERSION_MINOR) "."
++ gcmTXT2STR(gcvVERSION_PATCH) ":"
++ gcmTXT2STR(gcvVERSION_BUILD) "$\n";
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define gcmDEFINE2TEXT(d) #d
++gctCONST_STRING _DispatchText[] =
++{
++ gcmDEFINE2TEXT(gcvHAL_QUERY_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_CHIP_IDENTITY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_RELEASE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_LOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNLOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_EVENT_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_USER_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_DATA),
++ gcmDEFINE2TEXT(gcvHAL_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_STALL),
++ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_GET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_SET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_READ_ALL_PROFILE_REGISTERS),
++ gcmDEFINE2TEXT(gcvHAL_PROFILE_REGISTERS_2D),
++#if VIVANTE_PROFILER_PERDRAW
++ gcvHAL_READ_PROFILER_REGISTER_SETTING,
++#endif
++ gcmDEFINE2TEXT(gcvHAL_SET_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_GET_BASE_ADDRESS),
++ gcmDEFINE2TEXT(gcvHAL_SET_IDLE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_KERNEL_SETTINGS),
++ gcmDEFINE2TEXT(gcvHAL_RESET),
++ gcmDEFINE2TEXT(gcvHAL_MAP_PHYSICAL),
++ gcmDEFINE2TEXT(gcvHAL_DEBUG),
++ gcmDEFINE2TEXT(gcvHAL_CACHE),
++ gcmDEFINE2TEXT(gcvHAL_TIMESTAMP),
++ gcmDEFINE2TEXT(gcvHAL_DATABASE),
++ gcmDEFINE2TEXT(gcvHAL_VERSION),
++ gcmDEFINE2TEXT(gcvHAL_CHIP_INFO),
++ gcmDEFINE2TEXT(gcvHAL_ATTACH),
++ gcmDEFINE2TEXT(gcvHAL_DETACH),
++ gcmDEFINE2TEXT(gcvHAL_COMPOSE),
++ gcmDEFINE2TEXT(gcvHAL_SET_TIMEOUT),
++ gcmDEFINE2TEXT(gcvHAL_GET_FRAME_INFO),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_COMMAND_BUFFER),
++ gcmDEFINE2TEXT(gcvHAL_COMMIT_DONE),
++ gcmDEFINE2TEXT(gcvHAL_DUMP_GPU_STATE),
++ gcmDEFINE2TEXT(gcvHAL_DUMP_EVENT),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER),
++ gcmDEFINE2TEXT(gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER),
++ gcmDEFINE2TEXT(gcvHAL_SET_FSCALE_VALUE),
++ gcmDEFINE2TEXT(gcvHAL_GET_FSCALE_VALUE),
++ gcmDEFINE2TEXT(gcvHAL_NAME_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_IMPORT_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_RESET_TIME_STAMP),
++ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER_EX),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER_EX),
++ gcmDEFINE2TEXT(gcvHAL_SYNC_POINT),
++ gcmDEFINE2TEXT(gcvHAL_CREATE_NATIVE_FENCE),
++ gcmDEFINE2TEXT(gcvHAL_DESTROY_MMU),
++ gcmDEFINE2TEXT(gcvHAL_SHBUF),
++};
++#endif
++
++#if gcdGPU_TIMEOUT && gcdINTERRUPT_STATISTIC
++void
++_MonitorTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckKERNEL kernel = (gckKERNEL)Data;
++ gctUINT32 pendingInterrupt;
++ gctBOOL reset = gcvFALSE;
++ gctUINT32 mask;
++ gctUINT32 advance = kernel->timeOut/2;
++
++#if gcdENABLE_VG
++ if (kernel->core == gcvCORE_VG)
++ {
++ return;
++ }
++#endif
++
++ if (kernel->monitorTimerStop)
++ {
++ /* Stop. */
++ return;
++ }
++
++ gckOS_AtomGet(kernel->os, kernel->eventObj->interruptCount, &pendingInterrupt);
++
++ if (kernel->monitoring == gcvFALSE)
++ {
++ if (pendingInterrupt)
++ {
++ /* Begin to mointor GPU state. */
++ kernel->monitoring = gcvTRUE;
++
++ /* Record current state. */
++ kernel->lastCommitStamp = kernel->eventObj->lastCommitStamp;
++ kernel->restoreAddress = kernel->hardware->lastWaitLink;
++ gcmkVERIFY_OK(gckOS_AtomGet(
++ kernel->os,
++ kernel->hardware->pendingEvent,
++ &kernel->restoreMask
++ ));
++
++ /* Clear timeout. */
++ kernel->timer = 0;
++ }
++ }
++ else
++ {
++ if (pendingInterrupt)
++ {
++ gcmkVERIFY_OK(gckOS_AtomGet(
++ kernel->os,
++ kernel->hardware->pendingEvent,
++ &mask
++ ));
++
++ if (kernel->eventObj->lastCommitStamp == kernel->lastCommitStamp
++ && kernel->hardware->lastWaitLink == kernel->restoreAddress
++ && mask == kernel->restoreMask
++ )
++ {
++ /* GPU state is not changed, accumlate timeout. */
++ kernel->timer += advance;
++
++ if (kernel->timer >= kernel->timeOut)
++ {
++ /* GPU stuck, trigger reset. */
++ reset = gcvTRUE;
++ }
++ }
++ else
++ {
++ /* GPU state changed, cancel current timeout.*/
++ kernel->monitoring = gcvFALSE;
++ }
++ }
++ else
++ {
++ /* GPU finish all jobs, cancel current timeout*/
++ kernel->monitoring = gcvFALSE;
++ }
++ }
++
++ if (reset)
++ {
++ gckKERNEL_Recovery(kernel);
++
++ /* Work in this timeout is done. */
++ kernel->monitoring = gcvFALSE;
++ }
++
++ gcmkVERIFY_OK(gckOS_StartTimer(kernel->os, kernel->monitorTimer, advance));
++}
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++_MapCommandBuffer(
++ IN gckKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i;
++ gctUINT32 physical;
++ gckMMU mmu;
++
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu));
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Kernel->os,
++ Kernel->command->queues[i].logical,
++ &physical
++ ));
++
++ gcmkONERROR(gckMMU_FlatMapping(mmu, physical));
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++#endif
++
++void
++_DumpDriverConfigure(
++ IN gckKERNEL Kernel
++ )
++{
++ gcmkPRINT_N(0, "**************************\n");
++ gcmkPRINT_N(0, "*** GPU DRV CONFIG ***\n");
++ gcmkPRINT_N(0, "**************************\n");
++
++ gcmkPRINT("Galcore version %d.%d.%d.%d\n",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
++
++ gckOS_DumpParam();
++}
++
++void
++_DumpState(
++ IN gckKERNEL Kernel
++ )
++{
++ /* Dump GPU Debug registers. */
++ gcmkVERIFY_OK(gckHARDWARE_DumpGPUState(Kernel->hardware));
++
++ if (Kernel->virtualCommandBuffer)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_DumpExecutingBuffer(Kernel->command));
++ }
++
++ /* Dump Pending event. */
++ gcmkVERIFY_OK(gckEVENT_Dump(Kernel->eventObj));
++
++ /* Dump Process DB. */
++ gcmkVERIFY_OK(gckKERNEL_DumpProcessDB(Kernel));
++
++#if gcdRECORD_COMMAND
++ /* Dump record. */
++ gckRECORDER_Dump(Kernel->command->recorder);
++#endif
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** IN gckDB SharedDB,
++** Pointer to a shared DB.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ )
++{
++ gckKERNEL kernel = gcvNULL;
++ gceSTATUS status;
++ gctSIZE_T i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ /* Allocate the gckKERNEL object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckKERNEL),
++ &pointer));
++
++ kernel = pointer;
++
++ /* Zero the object pointers. */
++ kernel->hardware = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->eventObj = gcvNULL;
++ kernel->mmu = gcvNULL;
++#if gcdDVFS
++ kernel->dvfs = gcvNULL;
++#endif
++ kernel->monitorTimer = gcvNULL;
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->core = Core;
++
++ if (SharedDB == gcvNULL)
++ {
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckDB),
++ &pointer));
++
++ kernel->db = pointer;
++ kernel->dbCreated = gcvTRUE;
++ kernel->db->freeDatabase = gcvNULL;
++ kernel->db->freeRecord = gcvNULL;
++ kernel->db->dbMutex = gcvNULL;
++ kernel->db->lastDatabase = gcvNULL;
++ kernel->db->idleTime = 0;
++ kernel->db->lastIdle = 0;
++ kernel->db->lastSlowdown = 0;
++
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ kernel->db->db[i] = gcvNULL;
++ }
++
++ /* Construct a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->dbMutex));
++
++ /* Construct a video memory name database. */
++ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->nameDatabase));
++
++ /* Construct a video memory name database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->nameDatabaseMutex));
++
++ /* Construct a pointer name database. */
++ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->pointerDatabase));
++
++ /* Construct a pointer name database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->pointerDatabaseMutex));
++ }
++ else
++ {
++ kernel->db = SharedDB;
++ kernel->dbCreated = gcvFALSE;
++ }
++
++ for (i = 0; i < gcmCOUNTOF(kernel->timers); ++i)
++ {
++ kernel->timers[i].startTime = 0;
++ kernel->timers[i].stopTime = 0;
++ }
++
++ /* Save context. */
++ kernel->context = Context;
++
++ /* Construct atom holding number of clients. */
++ kernel->atomClients = gcvNULL;
++ gcmkONERROR(gckOS_AtomConstruct(Os, &kernel->atomClients));
++
++#if gcdENABLE_VG
++ kernel->vg = gcvNULL;
++
++ if (Core == gcvCORE_VG)
++ {
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckVGKERNEL_Construct(Os, Context, kernel, &kernel->vg));
++
++ kernel->timeOut = gcdGPU_TIMEOUT;
++ }
++ else
++#endif
++ {
++ /* Construct the gckHARDWARE object. */
++ gcmkONERROR(
++ gckHARDWARE_Construct(Os, kernel->core, &kernel->hardware));
++
++ /* Set pointer to gckKERNEL object in gckHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ kernel->timeOut = kernel->hardware->type == gcvHARDWARE_2D
++ ? gcdGPU_2D_TIMEOUT
++ : gcdGPU_TIMEOUT
++ ;
++
++ /* Initialize virtual command buffer. */
++ kernel->virtualCommandBuffer = gcvTRUE;
++
++ /* Construct the gckCOMMAND object. */
++ gcmkONERROR(
++ gckCOMMAND_Construct(kernel, &kernel->command));
++
++ /* Construct the gckEVENT object. */
++ gcmkONERROR(
++ gckEVENT_Construct(kernel, &kernel->eventObj));
++
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckMMU_Construct(kernel, gcdMMU_SIZE, &kernel->mmu));
++
++ gcmkVERIFY_OK(gckOS_GetTime(&kernel->resetTimeStamp));
++
++ gcmkONERROR(gckHARDWARE_PrepareFunctions(kernel->hardware));
++
++ /* Initialize the hardware. */
++ gcmkONERROR(
++ gckHARDWARE_InitializeHardware(kernel->hardware));
++
++#if gcdDVFS
++ if (gckHARDWARE_IsFeatureAvailable(kernel->hardware,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING))
++ {
++ gcmkONERROR(gckDVFS_Construct(kernel->hardware, &kernel->dvfs));
++ gcmkONERROR(gckDVFS_Start(kernel->dvfs));
++ }
++#endif
++ }
++
++ spin_lock_init(&kernel->irq_lock);
++
++#if VIVANTE_PROFILER
++ /* Initialize profile setting */
++ kernel->profileEnable = gcvFALSE;
++ kernel->profileCleanRegister = gcvTRUE;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkONERROR(gckOS_CreateSyncTimeline(Os, &kernel->timeline));
++#endif
++
++ kernel->recovery = gcvTRUE;
++ kernel->stuckDump = 1;
++
++ kernel->virtualBufferHead =
++ kernel->virtualBufferTail = gcvNULL;
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Os, (gctPOINTER)&kernel->virtualBufferLock));
++
++#if gcdGPU_TIMEOUT && gcdINTERRUPT_STATISTIC
++ if (kernel->timeOut)
++ {
++ gcmkVERIFY_OK(gckOS_CreateTimer(
++ Os,
++ (gctTIMERFUNCTION)_MonitorTimerFunction,
++ (gctPOINTER)kernel,
++ &kernel->monitorTimer
++ ));
++
++ kernel->monitoring = gcvFALSE;
++
++ kernel->monitorTimerStop = gcvFALSE;
++
++ gcmkVERIFY_OK(gckOS_StartTimer(
++ Os,
++ kernel->monitorTimer,
++ 100
++ ));
++ }
++#endif
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (kernel != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Core != gcvCORE_VG)
++#endif
++ {
++ if (kernel->eventObj != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_Destroy(kernel->eventObj));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(kernel->hardware->os,
++ kernel->hardware->core,
++ gcvFALSE,
++ gcvFALSE));
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(kernel->hardware));
++ }
++ }
++
++ if (kernel->atomClients != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, kernel->atomClients));
++ }
++
++ if (kernel->dbCreated && kernel->db != gcvNULL)
++ {
++ if (kernel->db->dbMutex != gcvNULL)
++ {
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->db->dbMutex));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel->db));
++ }
++
++ if (kernel->virtualBufferLock != gcvNULL)
++ {
++ /* Destroy the virtual command buffer mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->virtualBufferLock));
++ }
++
++#if gcdDVFS
++ if (kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (kernel->timeline)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Os, kernel->timeline));
++ }
++#endif
++
++ if (kernel->monitorTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, kernel->monitorTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, kernel->monitorTimer));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel));
++ }
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ )
++{
++ gctSIZE_T i;
++ gcsDATABASE_PTR database, databaseNext;
++ gcsDATABASE_RECORD_PTR record, recordNext;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Destroy the database. */
++ if (Kernel->dbCreated)
++ {
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ if (Kernel->db->db[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyProcessDB(Kernel, Kernel->db->db[i]->processID));
++ }
++ }
++
++ /* Free all databases. */
++ for (database = Kernel->db->freeDatabase;
++ database != gcvNULL;
++ database = databaseNext)
++ {
++ databaseNext = database->next;
++
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->counterMutex));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, database));
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->lastDatabase->counterMutex));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db->lastDatabase));
++ }
++
++ /* Free all database records. */
++ for (record = Kernel->db->freeRecord; record != gcvNULL; record = recordNext)
++ {
++ recordNext = record->next;
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Destroy video memory name database. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->nameDatabase));
++
++ /* Destroy video memory name database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->nameDatabaseMutex));
++
++
++ /* Destroy id-pointer database. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->pointerDatabase));
++
++ /* Destroy id-pointer database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++
++ /* Destroy the database. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db));
++
++ /* Notify stuck timer to quit. */
++ Kernel->monitorTimerStop = gcvTRUE;
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg)
++ {
++ gcmkVERIFY_OK(gckVGKERNEL_Destroy(Kernel->vg));
++ }
++ else
++#endif
++ {
++ /* Destroy the gckMMU object. */
++ gcmkVERIFY_OK(gckMMU_Destroy(Kernel->mmu));
++
++ /* Destroy the gckCOMMNAND object. */
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(Kernel->command));
++
++ /* Destroy the gckEVENT object. */
++ gcmkVERIFY_OK(gckEVENT_Destroy(Kernel->eventObj));
++
++ /* Destroy the gckHARDWARE object. */
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(Kernel->hardware));
++ }
++
++ /* Detsroy the client atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Kernel->atomClients));
++
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->virtualBufferLock));
++
++#if gcdDVFS
++ if (Kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(Kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(Kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Kernel->os, Kernel->timeline));
++#endif
++
++ if (Kernel->monitorTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Kernel->os, Kernel->monitorTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Kernel->os, Kernel->monitorTimer));
++ }
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** _AllocateMemory
++**
++** Private function to walk all required memory pools to allocate the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 Flag,
++ OUT gctUINT32 * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++ gctINT loopCount;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctBOOL tileStatusInVirtual;
++ gctBOOL contiguous = gcvFALSE;
++ gctBOOL cacheable = gcvFALSE;
++ gctSIZE_T bytes = Bytes;
++ gctUINT32 handle = 0;
++ gceDATABASE_TYPE type;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=%d Bytes=%lu Alignment=%lu Type=%d",
++ Kernel, *Pool, Bytes, Alignment, Type);
++
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes != 0);
++
++ /* Get basic type. */
++ Type &= 0xFF;
++
++ /* Check flags. */
++ contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS;
++ cacheable = Flag & gcvALLOC_FLAG_CACHEABLE;
++
++AllocateMemory:
++
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_CONTIGUOUS:
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ default:
++ loopCount = 1;
++ break;
++ }
++
++ while (loopCount-- > 0)
++ {
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkONERROR(
++ gckVIDMEM_ConstructVirtual(Kernel, Flag | gcvALLOC_FLAG_NON_CONTIGUOUS, Bytes, &node));
++
++ bytes = node->Virtual.bytes;
++ node->Virtual.type = Type;
++
++ /* Success. */
++ break;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++#if gcdCONTIGUOUS_SIZE_LIMIT
++ if (Bytes > gcdCONTIGUOUS_SIZE_LIMIT && contiguous == gcvFALSE)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ }
++ else
++#endif
++ {
++ /* Create a gcuVIDMEM_NODE from contiguous memory. */
++ status = gckVIDMEM_ConstructVirtual(
++ Kernel,
++ Flag | gcvALLOC_FLAG_CONTIGUOUS,
++ Bytes,
++ &node);
++ }
++
++ if (gcmIS_SUCCESS(status))
++ {
++ bytes = node->Virtual.bytes;
++ node->Virtual.type = Type;
++
++ /* Memory allocated. */
++ break;
++ }
++ }
++
++ else
++ /* gcvPOOL_SYSTEM can't be cacheable. */
++ if (cacheable == gcvFALSE)
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Allocate memory. */
++#if defined(gcdLINEAR_SIZE_LIMIT)
++ /* 512 KB */
++ if (Bytes > gcdLINEAR_SIZE_LIMIT)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ }
++ else
++#endif
++ {
++ status = gckVIDMEM_AllocateLinear(Kernel,
++ videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ (*Pool == gcvPOOL_SYSTEM),
++ &node);
++ }
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Memory allocated. */
++ node->VidMem.pool = pool;
++ bytes = node->VidMem.bytes;
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++
++ else
++ if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++
++ else
++ if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to contiguous memory. */
++ pool = gcvPOOL_CONTIGUOUS;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg)
++ {
++ tileStatusInVirtual = gcvFALSE;
++ }
++ else
++#endif
++ {
++ tileStatusInVirtual =
++ gckHARDWARE_IsFeatureAvailable(Kernel->hardware,
++ gcvFEATURE_MC20);
++ }
++
++ if (Type == gcvSURF_TILE_STATUS && tileStatusInVirtual != gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (contiguous)
++ {
++ break;
++ }
++
++ /* Advance to virtual memory. */
++ pool = gcvPOOL_VIRTUAL;
++ }
++
++ else
++ {
++ /* Out of pools. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ if (contiguous)
++ {
++ /* Broadcast OOM message. */
++ status = gckOS_Broadcast(Kernel->os, Kernel->hardware, gcvBROADCAST_OUT_OF_MEMORY);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Get some memory. */
++ gckOS_Delay(gcvNULL, 1);
++ goto AllocateMemory;
++ }
++ }
++
++ /* Nothing allocated. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Allocate handle for this video memory. */
++ gcmkONERROR(
++ gckVIDMEM_NODE_Allocate(Kernel, node, Type, pool, &handle));
++
++ /* Return node and pool used for allocation. */
++ *Node = handle;
++ *Pool = pool;
++
++ /* Encode surface type and pool to database type. */
++ type = gcvDB_VIDEO_MEMORY
++ | (Type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT)
++ | (pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT);
++
++ /* Record in process db. */
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ ProcessID,
++ type,
++ gcmINT2PTR(handle),
++ gcvNULL,
++ bytes));
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Pool=%d *Node=0x%x", *Pool, *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (handle)
++ {
++ /* Destroy handle allocated. */
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(Kernel, ProcessID, handle));
++ }
++
++ if (node)
++ {
++ /* Free video memory allocated. */
++ gcmkVERIFY_OK(gckVIDMEM_Free(Kernel, node));
++ }
++
++ /* For some case like chrome with webgl test, it needs too much memory so that it invokes oom_killer
++ * And the case is killed by oom_killer, the user wants not to see the crash and hope the case iteself handles the condition
++ * So the patch reports the out_of_memory to the case */
++ if ( status == gcvSTATUS_OUT_OF_MEMORY && (Flag & gcvALLOC_FLAG_MEMLIMIT) )
++ gcmkPRINT("The running case is out_of_memory");
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_ReleaseVideoMemory
++**
++** Release handle of a video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID of current process.
++**
++** gctUINT32 Handle
++** Handle of video memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_ReleaseVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject;
++ gceDATABASE_TYPE type;
++
++ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d Handle=%d",
++ Kernel, ProcessID, Handle);
++
++ gcmkONERROR(
++ gckVIDMEM_HANDLE_Lookup(Kernel, ProcessID, Handle, &nodeObject));
++
++ type = gcvDB_VIDEO_MEMORY
++ | (nodeObject->type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT)
++ | (nodeObject->pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT);
++
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ ProcessID,
++ type,
++ gcmINT2PTR(Handle)));
++
++ gckVIDMEM_HANDLE_Dereference(Kernel, ProcessID, Handle);
++
++ gckVIDMEM_NODE_Dereference(Kernel, nodeObject);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_LockVideoMemory
++**
++** Lock a video memory node. It will generate a cpu virtual address used
++** by software and a GPU address used by GPU.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gceCORE Core
++** GPU to which video memory is locked.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_LockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject = gcvNULL;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctBOOL locked = gcvFALSE;
++ gctBOOL asynchronous = gcvFALSE;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d",
++ Kernel, ProcessID);
++
++ gcmkONERROR(
++ gckVIDMEM_HANDLE_LookupAndReference(Kernel,
++ Interface->u.LockVideoMemory.node,
++ &nodeObject));
++
++ node = nodeObject->node;
++
++ Interface->u.LockVideoMemory.gid = 0;
++
++ /* Lock video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Lock(Kernel,
++ nodeObject,
++ Interface->u.LockVideoMemory.cacheable,
++ &Interface->u.LockVideoMemory.address,
++ &Interface->u.LockVideoMemory.gid,
++ &Interface->u.LockVideoMemory.physicalAddress));
++
++ locked = gcvTRUE;
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Map video memory address into user space. */
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemoryEx(Kernel,
++ Core,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ &pointer));
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(pointer);
++ }
++ else
++ {
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->Virtual.logical);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckVIDMEM_Node_Lock(
++ Kernel,
++ nodeObject,
++ &Interface->u.LockVideoMemory.address
++ ));
++#endif
++
++
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ ProcessID, gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmINT2PTR(Interface->u.LockVideoMemory.node),
++ gcvNULL,
++ 0));
++
++ gckVIDMEM_HANDLE_Reference(
++ Kernel, ProcessID, (gctUINT32)Interface->u.LockVideoMemory.node);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (locked)
++ {
++ /* Roll back the lock. */
++ gcmkVERIFY_OK(gckVIDMEM_Unlock(Kernel,
++ nodeObject,
++ gcvSURF_TYPE_UNKNOWN,
++ &asynchronous));
++
++ if (gcvTRUE == asynchronous)
++ {
++ /* Bottom Half */
++ gcmkVERIFY_OK(gckVIDMEM_Unlock(Kernel,
++ nodeObject,
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++ }
++ }
++
++ if (nodeObject != gcvNULL)
++ {
++ gckVIDMEM_NODE_Dereference(Kernel, nodeObject);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_UnlockVideoMemory
++**
++** Unlock a video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID of current process.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_UnlockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject;
++ gcuVIDMEM_NODE_PTR node;
++
++ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d",
++ Kernel, ProcessID);
++
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(
++ Kernel,
++ ProcessID,
++ (gctUINT32)Interface->u.UnlockVideoMemory.node,
++ &nodeObject));
++
++ node = nodeObject->node;
++
++ /* Unlock video memory. */
++ gcmkONERROR(gckVIDMEM_Unlock(
++ Kernel,
++ nodeObject,
++ Interface->u.UnlockVideoMemory.type,
++ &Interface->u.UnlockVideoMemory.asynchroneous));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gctINT i;
++ gcuDATABASE_INFO tmp;
++
++ gceDATABASE_TYPE type[3] = {
++ gcvDB_VIDEO_MEMORY | (gcvPOOL_SYSTEM << gcdDB_VIDEO_MEMORY_POOL_SHIFT),
++ gcvDB_VIDEO_MEMORY | (gcvPOOL_CONTIGUOUS << gcdDB_VIDEO_MEMORY_POOL_SHIFT),
++ gcvDB_VIDEO_MEMORY | (gcvPOOL_VIRTUAL << gcdDB_VIDEO_MEMORY_POOL_SHIFT),
++ };
++
++ gcmkHEADER();
++
++ /* Query video memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_VIDEO_MEMORY,
++ &Interface->u.Database.vidMem));
++
++ /* Query non-paged memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_NON_PAGED,
++ &Interface->u.Database.nonPaged));
++
++ /* Query contiguous memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_CONTIGUOUS,
++ &Interface->u.Database.contiguous));
++
++ /* Query GPU idle time. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_IDLE,
++ &Interface->u.Database.gpuIdle));
++ for (i = 0; i < 3; i++)
++ {
++ /* Query each video memory pool. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ type[i],
++ &Interface->u.Database.vidMemPool[i]));
++ }
++
++ /* Query virtual command buffer pool. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_COMMAND_BUFFER,
++ &tmp));
++
++ Interface->u.Database.vidMemPool[2].counters.bytes += tmp.counters.bytes;
++ Interface->u.Database.vidMemPool[2].counters.maxBytes += tmp.counters.maxBytes;
++ Interface->u.Database.vidMemPool[2].counters.totalBytes += tmp.counters.totalBytes;
++
++ Interface->u.Database.vidMem.counters.bytes += tmp.counters.bytes;
++ Interface->u.Database.vidMem.counters.maxBytes += tmp.counters.maxBytes;
++ Interface->u.Database.vidMem.counters.totalBytes += tmp.counters.totalBytes;
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gckKERNEL_DumpVidMemUsage(Kernel, Interface->u.Database.processID);
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_ConfigPowerManagement(
++ IN gckKERNEL Kernel,
++ IN OUT gcsHAL_INTERFACE * Interface
++)
++{
++ gceSTATUS status;
++ gctBOOL enable = Interface->u.ConfigPowerManagement.enable;
++
++ gcmkHEADER();
++
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(Kernel->hardware, enable));
++
++ if (enable == gcvTRUE)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Kernel->hardware, gcvPOWER_ON));
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL FromUser
++** whether the call is from the user space.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctSIZE_T bytes;
++ gctPOINTER logical = gcvNULL;
++ gctPOINTER info = gcvNULL;
++#if (gcdENABLE_3D || gcdENABLE_2D)
++ gckCONTEXT context = gcvNULL;
++#endif
++ gckKERNEL kernel = Kernel;
++ gctUINT32 address;
++ gctUINT32 processID;
++ gctUINT32 paddr = gcvINVALID_ADDRESS;
++ gctSIGNAL signal;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++
++ gckVIDMEM_NODE nodeObject;
++ gctBOOL powerMutexAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x FromUser=%d Interface=0x%x",
++ Kernel, FromUser, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "Dispatching command %d (%s)",
++ Interface->command, _DispatchText[Interface->command]);
++#endif
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkONERROR(
++ gckOS_GetBaseAddress(Kernel->os,
++ &Interface->u.GetBaseAddress.baseAddress));
++ break;
++
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkONERROR(gckKERNEL_QueryVideoMemory(Kernel, Interface));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkONERROR(
++ gckHARDWARE_QueryChipIdentity(
++ Kernel->hardware,
++ &Interface->u.QueryChipIdentity));
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.MapMemory.physical);
++
++ /* Map memory. */
++ gcmkONERROR(
++ gckKERNEL_MapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes,
++ &logical));
++
++ Interface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ logical,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes));
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.UnmapMemory.physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++
++ /* Unmap memory. */
++ gcmkONERROR(
++ gckKERNEL_UnmapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.UnmapMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++ break;
++
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateNonPagedMemory.bytes;
++
++ /* Allocate non-paged memory. */
++ gcmkONERROR(
++ gckOS_AllocateNonPagedMemory(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateNonPagedMemory.bytes = bytes;
++ Interface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateNonPagedMemory.physical),
++ bytes));
++ break;
++
++ case gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER:
++ bytes = (gctSIZE_T) Interface->u.AllocateVirtualCommandBuffer.bytes;
++
++ gcmkONERROR(
++ gckKERNEL_AllocateVirtualCommandBuffer(
++ Kernel,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateVirtualCommandBuffer.bytes = bytes;
++ Interface->u.AllocateVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateVirtualCommandBuffer.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_COMMAND_BUFFER,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateVirtualCommandBuffer.physical),
++ bytes));
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Free non-paged memory. */
++ gcmkONERROR(
++ gckOS_FreeNonPagedMemory(Kernel->os,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ gcmRELEASE_NAME(Interface->u.FreeNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateContiguousMemory.bytes;
++
++ /* Allocate contiguous memory. */
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateContiguousMemory.bytes = bytes;
++ Interface->u.AllocateContiguousMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateContiguousMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ logical,
++ gcvTRUE,
++ &Interface->u.AllocateContiguousMemory.address));
++
++ gcmkVERIFY_OK(gckKERNEL_AddProcessDB(
++ Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateContiguousMemory.physical),
++ bytes));
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++
++ /* Free contiguous memory. */
++ gcmkONERROR(
++ gckOS_FreeContiguous(Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes));
++
++ gcmRELEASE_NAME(Interface->u.FreeContiguousMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ /* Allocate memory. */
++ gcmkONERROR(
++ gckKERNEL_AllocateLinearMemory(Kernel, processID,
++ &Interface->u.AllocateLinearVideoMemory.pool,
++ Interface->u.AllocateLinearVideoMemory.bytes,
++ Interface->u.AllocateLinearVideoMemory.alignment,
++ Interface->u.AllocateLinearVideoMemory.type,
++ Interface->u.AllocateLinearVideoMemory.flag,
++ &Interface->u.AllocateLinearVideoMemory.node));
++ break;
++
++ case gcvHAL_RELEASE_VIDEO_MEMORY:
++ /* Release video memory. */
++ gcmkONERROR(gckKERNEL_ReleaseVideoMemory(
++ Kernel, processID,
++ (gctUINT32)Interface->u.ReleaseVideoMemory.node
++ ));
++ break;
++
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ /* Lock video memory. */
++ gcmkONERROR(gckKERNEL_LockVideoMemory(Kernel, Kernel->core, processID, FromUser, Interface));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ /* Unlock video memory. */
++ gcmkONERROR(gckKERNEL_UnlockVideoMemory(Kernel, processID, Interface));
++ break;
++
++ case gcvHAL_EVENT_COMMIT:
++ /* Commit an event queue. */
++ gcmkONERROR(
++ gckEVENT_Commit(Kernel->eventObj,
++ gcmUINT64_TO_PTR(Interface->u.Event.queue)));
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++ gcmkONERROR(
++ gckCOMMAND_Commit(Kernel->command,
++ Interface->u.Commit.context ?
++ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL,
++ gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer),
++ gcmUINT64_TO_PTR(Interface->u.Commit.delta),
++ gcmUINT64_TO_PTR(Interface->u.Commit.queue),
++ processID));
++
++ break;
++
++ case gcvHAL_STALL:
++ /* Stall the command queue. */
++ gcmkONERROR(gckCOMMAND_Stall(Kernel->command, gcvFALSE));
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkONERROR(
++ gckOS_MapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ Interface->u.MapUserMemory.physical,
++ (gctSIZE_T) Interface->u.MapUserMemory.size,
++ &info,
++ &Interface->u.MapUserMemory.address));
++
++ Interface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.MapUserMemory.info),
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ (gctSIZE_T) Interface->u.MapUserMemory.size));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ address = Interface->u.UnmapUserMemory.address;
++ info = gcmNAME_TO_PTR(Interface->u.UnmapUserMemory.info);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.UnmapUserMemory.info)));
++ /* Unmap user memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) Interface->u.UnmapUserMemory.size,
++ info,
++ address));
++
++ gcmRELEASE_NAME(Interface->u.UnmapUserMemory.info);
++ break;
++
++ case gcvHAL_USER_SIGNAL:
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkONERROR(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkONERROR(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++
++ break;
++
++ case gcvUSER_SIGNAL_MAP:
++ gcmkONERROR(
++ gckOS_MapSignal(Kernel->os,
++ (gctSIGNAL)(gctUINTPTR_T)Interface->u.UserSignal.id,
++ (gctHANDLE)(gctUINTPTR_T)processID,
++ &signal));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_UNMAP:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ break;
++
++ case gcvHAL_SET_POWER_MANAGEMENT_STATE:
++ /* Set the power management state. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(
++ Kernel->hardware,
++ Interface->u.SetPowerManagement.state));
++ break;
++
++ case gcvHAL_QUERY_POWER_MANAGEMENT_STATE:
++ /* Chip is not idle. */
++ Interface->u.QueryPowerManagement.isIdle = gcvFALSE;
++
++ /* Query the power management state. */
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(
++ Kernel->hardware,
++ &Interface->u.QueryPowerManagement.state));
++
++ /* Query the idle state. */
++ gcmkONERROR(
++ gckHARDWARE_QueryIdle(Kernel->hardware,
++ &Interface->u.QueryPowerManagement.isIdle));
++ break;
++
++ case gcvHAL_READ_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE));
++ powerMutexAcquired = gcvTRUE;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Read a register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(
++ Kernel->os,
++ Kernel->core,
++ Interface->u.ReadRegisterData.address,
++ &Interface->u.ReadRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ powerMutexAcquired = gcvFALSE;
++ }
++#else
++ /* No access from user land to read registers. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_WRITE_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE));
++ powerMutexAcquired = gcvTRUE;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Write a register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Kernel->os,
++ Kernel->core,
++ Interface->u.WriteRegisterData.address,
++ Interface->u.WriteRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.WriteRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ powerMutexAcquired = gcvFALSE;
++ }
++#else
++ /* No access from user land to write registers. */
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_READ_ALL_PROFILE_REGISTERS:
++#if VIVANTE_PROFILER && VIVANTE_PROFILER_CONTEXT
++ /* Read profile data according to the context. */
++ gcmkONERROR(
++ gckHARDWARE_QueryContextProfile(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ gcmNAME_TO_PTR(Interface->u.RegisterProfileData.context),
++ &Interface->u.RegisterProfileData.counters));
++#elif VIVANTE_PROFILER
++ /* Read all 3D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_QueryProfileRegisters(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ &Interface->u.RegisterProfileData.counters));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_PROFILE_REGISTERS_2D:
++#if VIVANTE_PROFILER
++ /* Read all 2D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_ProfileEngine2D(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.RegisterProfileData2D.hwProfile2D)));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_GET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Get profile setting */
++ Interface->u.GetProfileSetting.enable = Kernel->profileEnable;
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_SET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Set profile setting */
++ if(Kernel->hardware->gpuProfiler)
++ {
++ Kernel->profileEnable = Interface->u.SetProfileSetting.enable;
++#if VIVANTE_PROFILER_NEW
++ if (Kernel->profileEnable)
++ gckHARDWARE_InitProfiler(Kernel->hardware);
++#endif
++ }
++ else
++ {
++ status = gcvSTATUS_NOT_SUPPORTED;
++ break;
++ }
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++
++#if VIVANTE_PROFILER_PERDRAW
++ case gcvHAL_READ_PROFILER_REGISTER_SETTING:
++ #if VIVANTE_PROFILER
++ Kernel->profileCleanRegister = Interface->u.SetProfilerRegisterClear.bclear;
++ #endif
++ status = gcvSTATUS_OK;
++ break;
++#endif
++
++ case gcvHAL_QUERY_KERNEL_SETTINGS:
++ /* Get kernel settings. */
++ gcmkONERROR(
++ gckKERNEL_QuerySettings(Kernel,
++ &Interface->u.QueryKernelSettings.settings));
++ break;
++
++ case gcvHAL_RESET:
++ /* Reset the hardware. */
++ gcmkONERROR(
++ gckHARDWARE_Reset(Kernel->hardware));
++ break;
++
++ case gcvHAL_DEBUG:
++ /* Set debug level and zones. */
++ if (Interface->u.Debug.set)
++ {
++ gckOS_SetDebugLevel(Interface->u.Debug.level);
++ gckOS_SetDebugZones(Interface->u.Debug.zones,
++ Interface->u.Debug.enable);
++ }
++
++ if (Interface->u.Debug.message[0] != '\0')
++ {
++ /* Print a message to the debugger. */
++ if (Interface->u.Debug.type == gcvMESSAGE_TEXT)
++ {
++ gckOS_CopyPrint(Interface->u.Debug.message);
++ }
++ else
++ {
++ gckOS_DumpBuffer(Kernel->os,
++ Interface->u.Debug.message,
++ Interface->u.Debug.messageSize,
++ gceDUMP_BUFFER_FROM_USER,
++ gcvTRUE);
++ }
++ }
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_DUMP_GPU_STATE:
++ {
++ gceCHIPPOWERSTATE power;
++
++ _DumpDriverConfigure(Kernel);
++
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(
++ Kernel->hardware,
++ &power
++ ));
++
++ if (power == gcvPOWER_ON)
++ {
++ Interface->u.ReadRegisterData.data = 1;
++
++ _DumpState(Kernel);
++ }
++ else
++ {
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++
++ gcmkPRINT("[galcore]: Can't dump state if GPU isn't POWER ON.");
++ }
++ }
++ break;
++
++ case gcvHAL_DUMP_EVENT:
++ break;
++
++ case gcvHAL_CACHE:
++
++ logical = gcmUINT64_TO_PTR(Interface->u.Cache.logical);
++
++ if (Interface->u.Cache.node)
++ {
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(
++ Kernel,
++ processID,
++ Interface->u.Cache.node,
++ &nodeObject));
++
++ if (nodeObject->node->VidMem.memory->object.type == gcvOBJ_VIDMEM
++ || nodeObject->node->Virtual.contiguous
++ )
++ {
++ /* If memory is contiguous, get physical address. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Kernel->os, logical, (gctUINT32*)&paddr));
++ }
++ }
++
++ bytes = (gctSIZE_T) Interface->u.Cache.bytes;
++ switch(Interface->u.Cache.operation)
++ {
++ case gcvCACHE_FLUSH:
++ /* Clean and invalidate the cache. */
++ status = gckOS_CacheFlush(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_CLEAN:
++ /* Clean the cache. */
++ status = gckOS_CacheClean(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_INVALIDATE:
++ /* Invalidate the cache. */
++ status = gckOS_CacheInvalidate(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++
++ case gcvCACHE_MEMORY_BARRIER:
++ status = gckOS_MemoryBarrier(Kernel->os,
++ logical);
++ break;
++ default:
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ /* Check for invalid timer. */
++ if ((Interface->u.TimeStamp.timer >= gcmCOUNTOF(Kernel->timers))
++ || (Interface->u.TimeStamp.request != 2))
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Return timer results and reset timer. */
++ {
++ gcsTIMER_PTR timer = &(Kernel->timers[Interface->u.TimeStamp.timer]);
++ gctUINT64 timeDelta = 0;
++
++ if (timer->stopTime < timer->startTime )
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ timeDelta = timer->stopTime - timer->startTime;
++
++ /* Check truncation overflow. */
++ Interface->u.TimeStamp.timeDelta = (gctINT32) timeDelta;
++ /*bit0~bit30 is available*/
++ if (timeDelta>>31)
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ break;
++
++ case gcvHAL_DATABASE:
++ gcmkONERROR(gckKERNEL_QueryDatabase(Kernel, processID, Interface));
++ break;
++
++ case gcvHAL_VERSION:
++ Interface->u.Version.major = gcvVERSION_MAJOR;
++ Interface->u.Version.minor = gcvVERSION_MINOR;
++ Interface->u.Version.patch = gcvVERSION_PATCH;
++ Interface->u.Version.build = gcvVERSION_BUILD;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "KERNEL version %d.%d.%d build %u %s",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH,
++ gcvVERSION_BUILD, utsname()->version);
++#endif
++ break;
++
++ case gcvHAL_CHIP_INFO:
++ /* Only if not support multi-core */
++ Interface->u.ChipInfo.count = 1;
++ Interface->u.ChipInfo.types[0] = Kernel->hardware->type;
++ break;
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++ case gcvHAL_ATTACH:
++ /* Attach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Attach(Kernel->command,
++ &context,
++ &bytes,
++ processID));
++
++ Interface->u.Attach.stateCount = bytes;
++ Interface->u.Attach.context = gcmPTR_TO_NAME(context);
++
++ if (Interface->u.Attach.map == gcvTRUE)
++ {
++ gcmkVERIFY_OK(
++ gckCONTEXT_MapBuffer(context,
++ Interface->u.Attach.physicals,
++ Interface->u.Attach.logicals,
++ &Interface->u.Attach.bytes));
++ }
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Attach.context),
++ gcvNULL,
++ 0));
++ break;
++#endif
++
++ case gcvHAL_DETACH:
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Detach.context)));
++
++ /* Detach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Detach(Kernel->command,
++ gcmNAME_TO_PTR(Interface->u.Detach.context)));
++
++ gcmRELEASE_NAME(Interface->u.Detach.context);
++ break;
++
++ case gcvHAL_COMPOSE:
++ Interface->u.Compose.physical = gcmPTR_TO_UINT64(gcmNAME_TO_PTR(Interface->u.Compose.physical));
++ /* Start composition. */
++ gcmkONERROR(
++ gckEVENT_Compose(Kernel->eventObj,
++ &Interface->u.Compose));
++ break;
++
++ case gcvHAL_SET_TIMEOUT:
++ /* set timeOut value from user */
++ gckKERNEL_SetTimeOut(Kernel, Interface->u.SetTimeOut.timeOut);
++ break;
++
++ case gcvHAL_GET_FRAME_INFO:
++ gcmkONERROR(gckHARDWARE_GetFrameInfo(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.GetFrameInfo.frameInfo)));
++ break;
++
++ case gcvHAL_SET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_SetFscaleValue(Kernel->hardware,
++ Interface->u.SetFscaleValue.value);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++ case gcvHAL_GET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_GetFscaleValue(Kernel->hardware,
++ &Interface->u.GetFscaleValue.value,
++ &Interface->u.GetFscaleValue.minValue,
++ &Interface->u.GetFscaleValue.maxValue);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_NAME_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Name(Kernel,
++ Interface->u.NameVideoMemory.handle,
++ &Interface->u.NameVideoMemory.name));
++ break;
++
++ case gcvHAL_IMPORT_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Import(Kernel,
++ Interface->u.ImportVideoMemory.name,
++ &Interface->u.ImportVideoMemory.handle));
++
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ gcmINT2PTR(Interface->u.ImportVideoMemory.handle),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_GET_VIDEO_MEMORY_FD:
++ gcmkONERROR(gckVIDMEM_NODE_GetFd(
++ Kernel,
++ Interface->u.GetVideoMemoryFd.handle,
++ &Interface->u.GetVideoMemoryFd.fd
++ ));
++
++ /* No need to add it to processDB because OS will release all fds when
++ ** process quits.
++ */
++ break;
++
++ case gcvHAL_QUERY_RESET_TIME_STAMP:
++ Interface->u.QueryResetTimeStamp.timeStamp = Kernel->resetTimeStamp;
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)gcmNAME_TO_PTR(Interface->u.FreeVirtualCommandBuffer.physical);
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID,
++ gcvDB_COMMAND_BUFFER,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++
++ gcmkONERROR(gckOS_DestroyUserVirtualMapping(
++ Kernel->os,
++ buffer->physical,
++ (gctSIZE_T)Interface->u.FreeVirtualCommandBuffer.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++
++ gcmkONERROR(gckKERNEL_DestroyVirtualCommandBuffer(
++ Kernel,
++ (gctSIZE_T)Interface->u.FreeVirtualCommandBuffer.bytes,
++ (gctPHYS_ADDR)buffer,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++
++ gcmRELEASE_NAME(Interface->u.FreeVirtualCommandBuffer.physical);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ switch (Interface->u.SyncPoint.command)
++ {
++ case gcvSYNC_POINT_CREATE:
++ gcmkONERROR(gckOS_CreateSyncPoint(Kernel->os, &syncPoint));
++
++ Interface->u.SyncPoint.syncPoint = gcmPTR_TO_UINT64(syncPoint);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSYNC_POINT_DESTROY:
++ syncPoint = gcmUINT64_TO_PTR(Interface->u.SyncPoint.syncPoint);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint));
++
++ gcmkONERROR(gckOS_DestroySyncPoint(Kernel->os, syncPoint));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++
++ case gcvHAL_CREATE_NATIVE_FENCE:
++ {
++ gctINT fenceFD;
++ gctSYNC_POINT syncPoint =
++ gcmUINT64_TO_PTR(Interface->u.CreateNativeFence.syncPoint);
++
++ gcmkONERROR(
++ gckOS_CreateNativeFence(Kernel->os,
++ Kernel->timeline,
++ syncPoint,
++ &fenceFD));
++
++ Interface->u.CreateNativeFence.fenceFD = fenceFD;
++ }
++ break;
++#endif
++
++ case gcvHAL_SHBUF:
++ {
++ gctSHBUF shBuf;
++ gctPOINTER uData;
++ gctUINT32 bytes;
++
++ switch (Interface->u.ShBuf.command)
++ {
++ case gcvSHBUF_CREATE:
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Create. */
++ gcmkONERROR(gckKERNEL_CreateShBuffer(Kernel, bytes, &shBuf));
++
++ Interface->u.ShBuf.id = gcmPTR_TO_UINT64(shBuf);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_DESTROY:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Check db first to avoid illegal destroy in the process. */
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf));
++
++ gcmkONERROR(gckKERNEL_DestroyShBuffer(Kernel, shBuf));
++ break;
++
++ case gcvSHBUF_MAP:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Map for current process access. */
++ gcmkONERROR(gckKERNEL_MapShBuffer(Kernel, shBuf));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_WRITE:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Write. */
++ gcmkONERROR(
++ gckKERNEL_WriteShBuffer(Kernel, shBuf, uData, bytes));
++ break;
++
++ case gcvSHBUF_READ:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Read. */
++ gcmkONERROR(
++ gckKERNEL_ReadShBuffer(Kernel,
++ shBuf,
++ uData,
++ bytes,
++ &bytes));
++
++ /* Return copied size. */
++ Interface->u.ShBuf.bytes = bytes;
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++
++ case gcvHAL_CONFIG_POWER_MANAGEMENT:
++ gcmkONERROR(gckKERNEL_ConfigPowerManagement(Kernel, Interface));
++ break;
++
++ default:
++ /* Invalid command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++OnError:
++ /* Save status. */
++ Interface->status = status;
++
++ if (powerMutexAcquired == gcvTRUE)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcess
++**
++** Attach or detach a process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d", Kernel, Attach);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_AttachProcessEx(Kernel, Attach, processID));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcessEx
++**
++** Attach or detach a process with the given PID. Can be paired with gckKERNEL_AttachProcess
++** provided the programmer is aware of the consequences.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** gctUINT32 PID
++** PID of the process to attach or detach.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ )
++{
++ gceSTATUS status;
++ gctINT32 old;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d PID=%d", Kernel, Attach, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (Attach)
++ {
++ /* Increment the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomIncrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 0)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_FIRST_PROCESS));
++ }
++ }
++
++ if (Kernel->dbCreated)
++ {
++ /* Create the process database. */
++ gcmkONERROR(gckKERNEL_CreateProcessDB(Kernel, PID));
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Map kernel command buffer in the process's own MMU. */
++ gcmkONERROR(_MapCommandBuffer(Kernel));
++#endif
++ }
++ else
++ {
++ if (Kernel->dbCreated)
++ {
++ /* Clean up the process database. */
++ gcmkONERROR(gckKERNEL_DestroyProcessDB(Kernel, PID));
++
++ /* Save the last know process ID. */
++ Kernel->db->lastProcessID = PID;
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ status = gckEVENT_Submit(Kernel->eventObj, gcvTRUE, gcvFALSE, gcvFALSE);
++
++ if (status == gcvSTATUS_INTERRUPTED && Kernel->eventObj->submitTimer)
++ {
++ gcmkONERROR(gckOS_StartTimer(Kernel->os,
++ Kernel->eventObj->submitTimer,
++ 1));
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++ }
++
++ /* Decrement the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomDecrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 1)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ /* Last client detached, switch to SUSPEND power state. */
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_LAST_PROCESS));
++ }
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++ gckEVENT eventObj;
++ gckHARDWARE hardware;
++ gctUINT32 mask = 0;
++ gckCOMMAND command;
++ gckENTRYDATA data;
++ gctUINT32 i = 0, count = 0;
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 oldValue;
++#endif
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Grab gckEVENT object. */
++ eventObj = Kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Grab gckCOMMAND object. */
++ command = Kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Kernel->stuckDump == gcdSTUCK_DUMP_MINIMAL)
++ {
++ gcmkPRINT("[galcore]: GPU[%d] hang, automatic recovery.", Kernel->core);
++ }
++ else
++ {
++ _DumpDriverConfigure(Kernel);
++ _DumpState(Kernel);
++ }
++
++ if (Kernel->recovery == gcvFALSE)
++ {
++ gcmkPRINT("[galcore]: Stop driver to keep scene.");
++
++ for (;;)
++ {
++ gckOS_Delay(Kernel->os, 10000);
++ }
++ }
++
++ /* Clear queue. */
++ do
++ {
++ status = gckENTRYQUEUE_Dequeue(&command->queue, &data);
++ }
++ while (status == gcvSTATUS_OK);
++
++ /* Issuing a soft reset for the GPU. */
++ gcmkONERROR(gckHARDWARE_Reset(hardware));
++
++ mask = Kernel->restoreMask;
++
++ for (i = 0; i < 32; i++)
++ {
++ if (mask & (1 << i))
++ {
++ count++;
++ }
++ }
++
++ /* Handle all outstanding events now. */
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, mask));
++#else
++ eventObj->pending = mask;
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ while (count--)
++ {
++ gcmkONERROR(gckOS_AtomDecrement(
++ Kernel->os,
++ eventObj->interruptCount,
++ &oldValue
++ ));
++ }
++
++ gckOS_AtomClearMask(Kernel->hardware->pendingEvent, mask);
++#endif
++
++ gcmkONERROR(gckEVENT_Notify(eventObj, 1));
++
++ gcmkVERIFY_OK(gckOS_GetTime(&Kernel->resetTimeStamp));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_OpenUserData
++**
++** Get access to the user data.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctPOINTER StaticStorage
++** Pointer to the kernel storage where the data is to be copied if
++** NeedCopy is gcvTRUE.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to the kernel pointer that will be pointing to the data.
++*/
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d StaticStorage=0x%08X "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, StaticStorage, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(!NeedCopy || (StaticStorage != gcvNULL));
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ if (NeedCopy)
++ {
++ /* Copy the user data to the static storage. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Kernel->os, StaticStorage, UserPointer, Size
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = StaticStorage;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map the user pointer. */
++ gcmkONERROR(gckOS_MapUserPointer(
++ Kernel->os, UserPointer, Size, &pointer
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = pointer;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_CloseUserData
++**
++** Release resources associated with the user data connection opened by
++** gckKERNEL_OpenUserData.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctBOOL FlushData
++** If gcvTRUE, the data is written back to the user.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Kernel pointer to the data.
++*/
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d FlushData=%d "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, FlushData, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Get a shortcut to the kernel pointer. */
++ pointer = * KernelPointer;
++
++ if (pointer != gcvNULL)
++ {
++ if (NeedCopy)
++ {
++ if (FlushData)
++ {
++ gcmkONERROR(gckOS_CopyToUserData(
++ Kernel->os, * KernelPointer, UserPointer, Size
++ ));
++ }
++ }
++ else
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Kernel->os,
++ UserPointer,
++ Size,
++ * KernelPointer
++ ));
++ }
++
++ /* Reset the kernel pointer. */
++ * KernelPointer = gcvNULL;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ )
++{
++ gcmkHEADER_ARG("Kernel=0x%x timeOut=%d", Kernel, timeOut);
++#if gcdGPU_TIMEOUT
++ Kernel->timeOut = timeOut;
++#endif
++ gcmkFOOTER_NO();
++}
++
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckOS os = Kernel->os;
++ gceSTATUS status;
++ gctPOINTER logical = gcvNULL;
++ gctSIZE_T pageCount;
++ gctSIZE_T bytes = *Bytes;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = gcvNULL;
++ gckMMU mmu;
++ gctUINT32 flag = gcvALLOC_FLAG_NON_CONTIGUOUS;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(os,
++ sizeof(gckVIRTUAL_COMMAND_BUFFER),
++ (gctPOINTER)&buffer));
++
++ gcmkONERROR(gckOS_ZeroMemory(buffer, sizeof(gckVIRTUAL_COMMAND_BUFFER)));
++
++ buffer->bytes = bytes;
++
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(os,
++ flag,
++ bytes,
++ gcvNULL,
++ &buffer->physical));
++
++ if (InUserSpace)
++ {
++ gcmkONERROR(gckOS_CreateUserVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ &logical,
++ &pageCount));
++
++ *Logical =
++ buffer->userLogical = logical;
++ }
++ else
++ {
++ gcmkONERROR(gckOS_CreateKernelVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ &logical,
++ &pageCount));
++
++ *Logical =
++ buffer->kernelLogical = logical;
++ }
++
++ buffer->pageCount = pageCount;
++ buffer->kernel = Kernel;
++
++ gcmkONERROR(gckOS_GetProcessID(&buffer->pid));
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu));
++ buffer->mmu = mmu;
++#else
++ mmu = Kernel->mmu;
++#endif
++
++ gcmkONERROR(gckMMU_AllocatePages(mmu,
++ pageCount,
++ &buffer->pageTable,
++ &buffer->gpuAddress));
++
++
++ gcmkONERROR(gckOS_MapPagesEx(os,
++ Kernel->core,
++ buffer->physical,
++ pageCount,
++ buffer->gpuAddress,
++ buffer->pageTable));
++
++ gcmkONERROR(gckMMU_Flush(mmu, gcvSURF_INDEX));
++
++ *Physical = buffer;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "gpuAddress = %x pageCount = %d kernelLogical = %x userLogical=%x",
++ buffer->gpuAddress, buffer->pageCount,
++ buffer->kernelLogical, buffer->userLogical);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ if (Kernel->virtualBufferHead == gcvNULL)
++ {
++ Kernel->virtualBufferHead =
++ Kernel->virtualBufferTail = buffer;
++ }
++ else
++ {
++ buffer->prev = Kernel->virtualBufferTail;
++ Kernel->virtualBufferTail->next = buffer;
++ Kernel->virtualBufferTail = buffer;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (buffer->gpuAddress)
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(mmu, buffer->pageTable, buffer->pageCount));
++#else
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu, buffer->pageTable, buffer->pageCount));
++#endif
++ }
++
++ if (buffer->userLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyUserVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ buffer->userLogical));
++ }
++
++ if (buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ buffer->kernelLogical));
++ }
++
++ if (buffer->physical)
++ {
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, bytes));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ gckOS os;
++ gckKERNEL kernel;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)Physical;
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(buffer != gcvNULL);
++
++ kernel = buffer->kernel;
++ os = kernel->os;
++
++ if (!buffer->userLogical)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ Bytes,
++ Logical));
++ }
++
++#if !gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(kernel->mmu, buffer->pageTable, buffer->pageCount));
++#endif
++
++ gcmkVERIFY_OK(gckOS_UnmapPages(os, buffer->pageCount, buffer->gpuAddress));
++
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, Bytes));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, kernel->virtualBufferLock, gcvINFINITE));
++
++ if (buffer == kernel->virtualBufferHead)
++ {
++ if ((kernel->virtualBufferHead = buffer->next) == gcvNULL)
++ {
++ kernel->virtualBufferTail = gcvNULL;
++ }
++ }
++ else
++ {
++ buffer->prev->next = buffer->next;
++
++ if (buffer == kernel->virtualBufferTail)
++ {
++ kernel->virtualBufferTail = buffer->prev;
++ }
++ else
++ {
++ buffer->next->prev = buffer->prev;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, kernel->virtualBufferLock));
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctPOINTER start;
++ gctUINT32 pid;
++
++ gcmkHEADER_ARG("Logical = %x InUserSpace=%d.", Logical, InUserSpace);
++
++ gcmkVERIFY_OK(gckOS_GetProcessID(&pid));
++
++ status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffer. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ if (InUserSpace)
++ {
++ start = buffer->userLogical;
++ }
++ else
++ {
++ start = buffer->kernelLogical;
++ }
++
++ if (start == gcvNULL)
++ {
++ continue;
++ }
++
++ if (Logical >= start
++ && (Logical < (gctPOINTER)((gctUINT8_PTR)start + buffer->pageCount * 4096))
++ && pid == buffer->pid
++ )
++ {
++ * Address = buffer->gpuAddress + (gctUINT32)((gctUINT8_PTR)Logical - (gctUINT8_PTR)start);
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ )
++{
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 start;
++ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffers. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ start = (gctUINT32)buffer->gpuAddress;
++
++ if (GpuAddress >= start && GpuAddress < (start + buffer->pageCount * 4096))
++ {
++ /* Find a range matched. */
++ *Buffer = buffer;
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ return status;
++}
++
++#if gcdLINK_QUEUE_SIZE
++static void
++gckLINKQUEUE_Dequeue(
++ IN gckLINKQUEUE LinkQueue
++ )
++{
++ gcmkASSERT(LinkQueue->count == gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count--;
++ LinkQueue->front = (LinkQueue->front + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ )
++{
++ if (LinkQueue->count == gcdLINK_QUEUE_SIZE)
++ {
++ gckLINKQUEUE_Dequeue(LinkQueue);
++ }
++
++ gcmkASSERT(LinkQueue->count < gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count++;
++
++ LinkQueue->data[LinkQueue->rear].start = start;
++ LinkQueue->data[LinkQueue->rear].end = end;
++
++ gcmkVERIFY_OK(
++ gckOS_GetProcessID(&LinkQueue->data[LinkQueue->rear].pid));
++
++ LinkQueue->rear = (LinkQueue->rear + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ )
++{
++ gcmkASSERT(Index >= 0 && Index < gcdLINK_QUEUE_SIZE);
++
++ *Data = &LinkQueue->data[(Index + LinkQueue->front) % gcdLINK_QUEUE_SIZE];
++}
++#endif
++
++/*
++* gckENTRYQUEUE_Enqueue is called with Command->mutexQueue acquired.
++*/
++gceSTATUS
++gckENTRYQUEUE_Enqueue(
++ IN gckKERNEL Kernel,
++ IN gckENTRYQUEUE Queue,
++ IN gctUINT32 physical,
++ IN gctUINT32 bytes
++ )
++{
++ gctUINT32 next = (Queue->rear + 1) % gcdENTRY_QUEUE_SIZE;
++
++ if (next == Queue->front)
++ {
++ /* Queue is full. */
++ return gcvSTATUS_INVALID_REQUEST;
++ }
++
++ /* Copy data. */
++ Queue->data[Queue->rear].physical = physical;
++ Queue->data[Queue->rear].bytes = bytes;
++
++ gcmkVERIFY_OK(gckOS_MemoryBarrier(Kernel->os, &Queue->rear));
++
++ /* Update rear. */
++ Queue->rear = next;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckENTRYQUEUE_Dequeue(
++ IN gckENTRYQUEUE Queue,
++ OUT gckENTRYDATA * Data
++ )
++{
++ if (Queue->front == Queue->rear)
++ {
++ /* Queue is empty. */
++ return gcvSTATUS_INVALID_REQUEST;
++ }
++
++ /* Copy data. */
++ *Data = &Queue->data[Queue->front];
++
++ /* Update front. */
++ Queue->front = (Queue->front + 1) % gcdENTRY_QUEUE_SIZE;
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++*************************** Pointer - ID translation ***************************
++\******************************************************************************/
++#define gcdID_TABLE_LENGTH 1024
++typedef struct _gcsINTEGERDB * gckINTEGERDB;
++typedef struct _gcsINTEGERDB
++{
++ gckOS os;
++ gctPOINTER* table;
++ gctPOINTER mutex;
++ gctUINT32 tableLen;
++ gctUINT32 currentID;
++ gctUINT32 unused;
++}
++gcsINTEGERDB;
++
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Allocate a database. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gcsINTEGERDB), (gctPOINTER *)&database));
++
++ gcmkONERROR(gckOS_ZeroMemory(database, gcmSIZEOF(gcsINTEGERDB)));
++
++ /* Allocate a pointer table. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH, (gctPOINTER *)&database->table));
++
++ gcmkONERROR(gckOS_ZeroMemory(database->table, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH));
++
++ /* Allocate a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->mutex));
++
++ /* Initialize. */
++ database->currentID = 0;
++ database->unused = gcdID_TABLE_LENGTH;
++ database->os = Kernel->os;
++ database->tableLen = gcdID_TABLE_LENGTH;
++
++ *Database = database;
++
++ gcmkFOOTER_ARG("*Database=0x%08X", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Rollback. */
++ if (database)
++ {
++ if (database->table)
++ {
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++ }
++
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ )
++{
++ gckINTEGERDB database = Database;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Destroy pointer table. */
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++
++ /* Destroy database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->mutex));
++
++ /* Destroy database. */
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctUINT32 i, unused, currentID, tableLen;
++ gctPOINTER * table;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Pointer=0x%08X", Database, Pointer);
++
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (database->unused < 1)
++ {
++ /* Extend table. */
++ gcmkONERROR(
++ gckOS_Allocate(os,
++ gcmSIZEOF(gctPOINTER) * (database->tableLen + gcdID_TABLE_LENGTH),
++ (gctPOINTER *)&table));
++
++ gcmkONERROR(gckOS_ZeroMemory(table + database->tableLen,
++ gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH));
++
++ /* Copy data from old table. */
++ gckOS_MemCopy(table,
++ database->table,
++ database->tableLen * gcmSIZEOF(gctPOINTER));
++
++ gcmkOS_SAFE_FREE(os, database->table);
++
++ /* Update databse with new allocated table. */
++ database->table = table;
++ database->currentID = database->tableLen;
++ database->tableLen += gcdID_TABLE_LENGTH;
++ database->unused += gcdID_TABLE_LENGTH;
++ }
++
++ table = database->table;
++ currentID = database->currentID;
++ tableLen = database->tableLen;
++ unused = database->unused;
++
++ /* Connect id with pointer. */
++ table[currentID] = Pointer;
++
++ *Id = currentID + 1;
++
++ /* Update the currentID. */
++ if (--unused > 0)
++ {
++ for (i = 0; i < tableLen; i++)
++ {
++ if (++currentID >= tableLen)
++ {
++ /* Wrap to the begin. */
++ currentID = 0;
++ }
++
++ if (table[currentID] == gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ database->table = table;
++ database->currentID = currentID;
++ database->tableLen = tableLen;
++ database->unused = unused;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_ARG("*Id=%d", *Id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ database->table[Id] = gcvNULL;
++
++ if (database->unused++ == 0)
++ {
++ database->currentID = Id;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctPOINTER pointer;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ pointer = database->table[Id];
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ if (pointer)
++ {
++ *Pointer = pointer;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ gcmkFOOTER_ARG("*Pointer=0x%08X", *Pointer);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gctUINT32 name;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Pointer=0x%X", Kernel, Pointer);
++
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(database, Pointer, &name));
++
++ gcmkFOOTER_ARG("name=%d", name);
++ return name;
++
++OnError:
++ gcmkFOOTER();
++ return 0;
++}
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer = gcvNULL;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name);
++
++ /* Lookup in database to get pointer. */
++ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, &pointer));
++
++ gcmkFOOTER_ARG("pointer=0x%X", pointer);
++ return pointer;
++
++OnError:
++ gcmkFOOTER();
++ return gcvNULL;
++}
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=0x%X", Kernel, Name);
++
++ /* Free name if exists. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Name));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_SetRecovery(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Recovery,
++ IN gctUINT32 StuckDump
++ )
++{
++ Kernel->recovery = Recovery;
++
++ if (Recovery == gcvFALSE)
++ {
++ /* Dump stuck information if Recovery is disabled. */
++ Kernel->stuckDump = gcmMAX(StuckDump, gcdSTUCK_DUMP_MIDDLE);
++ }
++
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++***** Shared Buffer ************************************************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_CreateShBuffer
++**
++** Create shared buffer.
++** The shared buffer can be used across processes. Other process needs call
++** gckKERNEL_MapShBuffer before use it.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Size
++** Specify the shared buffer size.
++**
++** OUTPUT:
++**
++** gctSHBUF * ShBuf
++** Pointer to hold return shared buffer handle.
++*/
++gceSTATUS
++gckKERNEL_CreateShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Size,
++ OUT gctSHBUF * ShBuf
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%X, Size=%u", Kernel, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (Size == 0)
++ {
++ /* Invalid size. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ else if (Size > 1024)
++ {
++ /* Limite shared buffer size. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Create a shared buffer structure. */
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof (gcsSHBUF),
++ (gctPOINTER *)&shBuf));
++
++ /* Initialize shared buffer. */
++ shBuf->id = 0;
++ shBuf->reference = gcvNULL;
++ shBuf->size = Size;
++ shBuf->data = gcvNULL;
++
++ /* Allocate integer id for this shared buffer. */
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(Kernel->db->pointerDatabase,
++ shBuf,
++ &shBuf->id));
++
++ /* Allocate atom. */
++ gcmkONERROR(gckOS_AtomConstruct(Kernel->os, &shBuf->reference));
++
++ /* Set default reference count to 1. */
++ gcmkVERIFY_OK(gckOS_AtomSet(Kernel->os, shBuf->reference, 1));
++
++ /* Return integer id. */
++ *ShBuf = (gctSHBUF)(gctUINTPTR_T)shBuf->id;
++
++ gcmkFOOTER_ARG("*ShBuf=%u", shBuf->id);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Error roll back. */
++ if (shBuf != gcvNULL)
++ {
++ if (shBuf->id != 0)
++ {
++ gcmkVERIFY_OK(
++ gckKERNEL_FreeIntegerId(Kernel->db->pointerDatabase,
++ shBuf->id));
++ }
++
++ gcmkOS_SAFE_FREE(Kernel->os, shBuf);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_DestroyShBuffer
++**
++** Destroy shared buffer.
++** This will decrease reference of specified shared buffer and do actual
++** destroy when no reference on it.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_DestroyShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctINT32 oldValue = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ /* Decrease the reference count. */
++ gckOS_AtomDecrement(Kernel->os, shBuf->reference, &oldValue);
++
++ if (oldValue == 1)
++ {
++ /* Free integer id. */
++ gcmkVERIFY_OK(
++ gckKERNEL_FreeIntegerId(Kernel->db->pointerDatabase,
++ shBuf->id));
++
++ /* Free atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, shBuf->reference));
++
++ if (shBuf->data)
++ {
++ gcmkOS_SAFE_FREE(Kernel->os, shBuf->data);
++ shBuf->data = gcvNULL;
++ }
++
++ /* Free the shared buffer. */
++ gcmkOS_SAFE_FREE(Kernel->os, shBuf);
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapShBuffer
++**
++** Map shared buffer into this process so that it can be used in this process.
++** This will increase reference count on the specified shared buffer.
++** Call gckKERNEL_DestroyShBuffer to dereference.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be mapped.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_MapShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctINT32 oldValue = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ /* Increase the reference count. */
++ gckOS_AtomIncrement(Kernel->os, shBuf->reference, &oldValue);
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_WriteShBuffer
++**
++** Write user data into shared buffer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be written to.
++**
++** gctPOINTER UserData
++** User mode pointer to hold the source data.
++**
++** gctUINT32 ByteCount
++** Specify number of bytes to write. If this is larger than
++** shared buffer size, gcvSTATUS_INVALID_ARGUMENT is returned.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_WriteShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u UserData=0x%X ByteCount=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf, UserData, ByteCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ if ((ByteCount > shBuf->size) ||
++ (ByteCount == 0) ||
++ (UserData == gcvNULL))
++ {
++ /* Exceeds buffer max size or invalid. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (shBuf->data == gcvNULL)
++ {
++ /* Allocate buffer data when first time write. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os, ByteCount, &shBuf->data));
++ }
++
++ /* Copy data from user. */
++ gcmkONERROR(
++ gckOS_CopyFromUserData(Kernel->os,
++ shBuf->data,
++ UserData,
++ ByteCount));
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_ReadShBuffer
++**
++** Read data from shared buffer and copy to user pointer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be read from.
++**
++** gctPOINTER UserData
++** User mode pointer to save output data.
++**
++** gctUINT32 ByteCount
++** Specify number of bytes to read.
++** If this is larger than shared buffer size, only avaiable bytes are
++** copied. If smaller, copy requested size.
++**
++** OUTPUT:
++**
++** gctUINT32 * BytesRead
++** Pointer to hold how many bytes actually read from shared buffer.
++*/
++gceSTATUS
++gckKERNEL_ReadShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount,
++ OUT gctUINT32 * BytesRead
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctUINT32 bytes;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u UserData=0x%X ByteCount=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf, UserData, ByteCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ if (shBuf->data == gcvNULL)
++ {
++ *BytesRead = 0;
++
++ /* No data in shared buffer, skip copy. */
++ status = gcvSTATUS_SKIP;
++ goto OnError;
++ }
++ else if (ByteCount == 0)
++ {
++ /* Invalid size to read. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Determine bytes to copy. */
++ bytes = (ByteCount < shBuf->size) ? ByteCount : shBuf->size;
++
++ /* Copy data to user. */
++ gcmkONERROR(
++ gckOS_CopyToUserData(Kernel->os,
++ shBuf->data,
++ UserData,
++ bytes));
++
++ /* Return copied size. */
++ *BytesRead = bytes;
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_ARG("*BytesRead=%u", bytes);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++/*******************************************************************************
++***** Test Code ****************************************************************
++*******************************************************************************/
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_command.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_command.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_command.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_command.c 2016-06-19 22:11:55.137151030 +0200
+@@ -0,0 +1,3075 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_context.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _NewQueue
++**
++** Allocate a new command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** OUTPUT:
++**
++** gckCOMMAND Command
++** gckCOMMAND object has been updated with a new command queue.
++*/
++static gceSTATUS
++_NewQueue(
++ IN OUT gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctINT currentIndex, newIndex;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Switch to the next command buffer. */
++ currentIndex = Command->index;
++ newIndex = (currentIndex + 1) % gcdCOMMAND_QUEUES;
++
++ /* Wait for availability. */
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.waitsignal]");
++#endif
++
++ gcmkONERROR(gckOS_WaitSignal(
++ Command->os,
++ Command->queues[newIndex].signal,
++ gcvINFINITE
++ ));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ if (newIndex < currentIndex)
++ {
++ Command->wrapCount += 1;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 2 * 4,
++ "%s(%d): queue array wrapped around.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): total queue wrap arounds %d.\n",
++ __FUNCTION__, __LINE__, Command->wrapCount
++ );
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): switched to queue %d.\n",
++ __FUNCTION__, __LINE__, newIndex
++ );
++#endif
++
++ /* Update gckCOMMAND object with new command queue. */
++ Command->index = newIndex;
++ Command->newQueue = gcvTRUE;
++ Command->logical = Command->queues[newIndex].logical;
++ Command->address = Command->queues[newIndex].address;
++ Command->offset = 0;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Command->os,
++ Command->logical,
++ (gctUINT32 *) &Command->physical
++ ));
++
++ if (currentIndex != -1)
++ {
++ /* Mark the command queue as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ Command->kernel->eventObj,
++ Command->queues[currentIndex].signal,
++ gcvKERNEL_COMMAND
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("Command->index=%d", Command->index);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IncrementCommitAtom(
++ IN gckCOMMAND Command,
++ IN gctBOOL Increment
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctINT32 atomValue;
++ gctBOOL powerAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Increment the commit atom. */
++ if (Increment)
++ {
++ /* Grab the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, hardware->powerMutex, gcvINFINITE
++ ));
++ powerAcquired = gcvTRUE;
++
++ gcmkONERROR(gckOS_AtomIncrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ powerAcquired = gcvFALSE;
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AtomDecrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (powerAcquired)
++ {
++ /* Release the power mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_FlushMMU(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckHARDWARE hardware = Command->kernel->hardware;
++ gctBOOL pause = gcvFALSE;
++
++ gctUINT8_PTR pointer;
++ gctUINT32 eventBytes;
++ gctUINT32 endBytes;
++ gctUINT32 bufferSize;
++ gctUINT32 executeBytes;
++ gctUINT32 waitLinkBytes;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckHARDWARE_FlushMMU(hardware));
++
++ if ((oldValue & gcvPAGE_TABLE_DIRTY_BIT_FE)
++ && (hardware->endAfterFlushMmuCache)
++ )
++ {
++ pause = gcvTRUE;
++ }
++ }
++
++ if (pause)
++ {
++ /* Query size. */
++ gcmkONERROR(gckHARDWARE_Event(hardware, gcvNULL, 0, gcvKERNEL_PIXEL, &eventBytes));
++ gcmkONERROR(gckHARDWARE_End(hardware, gcvNULL, &endBytes));
++
++ executeBytes = eventBytes + endBytes;
++
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ gcvNULL,
++ Command->offset + executeBytes,
++ &waitLinkBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Reserve space. */
++ gcmkONERROR(gckCOMMAND_Reserve(
++ Command,
++ executeBytes,
++ (gctPOINTER *)&pointer,
++ &bufferSize
++ ));
++
++ /* Append EVENT(29). */
++ gcmkONERROR(gckHARDWARE_Event(
++ hardware,
++ pointer,
++ 29,
++ gcvKERNEL_PIXEL,
++ &eventBytes
++ ));
++
++ /* Append END. */
++ pointer += eventBytes;
++ gcmkONERROR(gckHARDWARE_End(hardware, pointer, &endBytes));
++
++ /* Store address to queue. */
++ gcmkONERROR(gckENTRYQUEUE_Enqueue(
++ Command->kernel,
++ &Command->queue,
++ Command->address + Command->offset + executeBytes,
++ waitLinkBytes
++ ));
++
++ gcmkONERROR(gckCOMMAND_Execute(Command, executeBytes));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++static void
++_DumpBuffer(
++ IN gctPOINTER Buffer,
++ IN gctUINT32 GpuAddress,
++ IN gctSIZE_T Size
++ )
++{
++ gctSIZE_T i, line, left;
++ gctUINT32_PTR data = Buffer;
++
++ line = Size / 32;
++ left = Size % 32;
++
++ for (i = 0; i < line; i++)
++ {
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]);
++ data += 8;
++ GpuAddress += 8 * 4;
++ }
++
++ switch(left)
++ {
++ case 28:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6]);
++ break;
++ case 24:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5]);
++ break;
++ case 20:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4]);
++ break;
++ case 16:
++ gcmkPRINT("%X : %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3]);
++ break;
++ case 12:
++ gcmkPRINT("%X : %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2]);
++ break;
++ case 8:
++ gcmkPRINT("%X : %08X %08X ",
++ GpuAddress, data[0], data[1]);
++ break;
++ case 4:
++ gcmkPRINT("%X : %08X ",
++ GpuAddress, data[0]);
++ break;
++ default:
++ break;
++ }
++}
++
++static void
++_DumpKernelCommandBuffer(
++ IN gckCOMMAND Command
++ )
++{
++ gctINT i;
++ gctUINT32 physical = 0;
++ gctPOINTER entry = gcvNULL;
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ entry = Command->queues[i].logical;
++
++ gckOS_GetPhysicalAddress(Command->os, entry, &physical);
++
++ gcmkPRINT("Kernel command buffer %d\n", i);
++
++ _DumpBuffer(entry, physical, Command->pageSize);
++ }
++}
++
++/******************************************************************************\
++****************************** gckCOMMAND API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckCOMMAND_Construct
++**
++** Construct a new gckCOMMAND object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckCOMMAND * Command
++** Pointer to a variable that will hold the pointer to the gckCOMMAND
++** object.
++*/
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ )
++{
++ gckOS os;
++ gckCOMMAND command = gcvNULL;
++ gceSTATUS status;
++ gctINT i;
++ gctPOINTER pointer = gcvNULL;
++ gctSIZE_T pageSize;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ /* Extract the gckOS object. */
++ os = Kernel->os;
++
++ /* Allocate the gckCOMMAND structure. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckCOMMAND), &pointer));
++ command = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(command, gcmSIZEOF(struct _gckCOMMAND)));
++
++ /* Initialize the gckCOMMAND object.*/
++ command->object.type = gcvOBJ_COMMAND;
++ command->kernel = Kernel;
++ command->os = os;
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Kernel->hardware,
++ &command->alignment,
++ &command->reservedHead,
++ &command->reservedTail
++ ));
++
++ /* Create the command queue mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexQueue));
++
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContextSeq));
++#endif
++
++ /* Create the power management semaphore. */
++ gcmkONERROR(gckOS_CreateSemaphore(os, &command->powerSemaphore));
++
++ /* Create the commit atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &command->atomCommit));
++
++ /* Get the page size from teh OS. */
++ gcmkONERROR(gckOS_GetPageSize(os, &pageSize));
++
++ gcmkSAFECASTSIZET(command->pageSize, pageSize);
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&command->kernelProcessID));
++
++ /* Set hardware to pipe 0. */
++ command->pipeSelect = gcvPIPE_INVALID;
++
++ /* Pre-allocate the command queues. */
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ os,
++ gcvFALSE,
++ &pageSize,
++ &command->queues[i].physical,
++ &command->queues[i].logical
++ ));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ command->queues[i].logical,
++ gcvFALSE,
++ &command->queues[i].address
++ ));
++
++ gcmkONERROR(gckOS_CreateSignal(
++ os, gcvFALSE, &command->queues[i].signal
++ ));
++
++ gcmkONERROR(gckOS_Signal(
++ os, command->queues[i].signal, gcvTRUE
++ ));
++ }
++
++#if gcdRECORD_COMMAND
++ gcmkONERROR(gckRECORDER_Construct(os, Kernel->hardware, &command->recorder));
++#endif
++
++ /* No command queue in use yet. */
++ command->index = -1;
++ command->logical = gcvNULL;
++ command->newQueue = gcvFALSE;
++
++ /* Command is not yet running. */
++ command->running = gcvFALSE;
++
++ /* Command queue is idle. */
++ command->idle = gcvTRUE;
++
++ /* Commit stamp is zero. */
++ command->commitStamp = 0;
++
++ /* END event signal not created. */
++ command->endEventSignal = gcvNULL;
++
++ command->queue.front = 0;
++ command->queue.rear = 0;
++ command->queue.count = 0;
++
++ /* Return pointer to the gckCOMMAND object. */
++ *Command = command;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Command=0x%x", *Command);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ if (command->atomCommit != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, command->atomCommit));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(os, command->powerSemaphore));
++ }
++
++ if (command->mutexContext != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContext));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (command->mutexContextSeq != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContextSeq));
++ }
++#endif
++
++ if (command->mutexQueue != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexQueue));
++ }
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ if (command->queues[i].signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ os, command->queues[i].signal
++ ));
++ }
++
++ if (command->queues[i].logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ os,
++ command->pageSize,
++ command->queues[i].physical,
++ command->queues[i].logical
++ ));
++ }
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, command));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Destroy
++**
++** Destroy an gckCOMMAND object.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Stop the command queue. */
++ gcmkVERIFY_OK(gckCOMMAND_Stop(Command, gcvFALSE));
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkASSERT(Command->queues[i].signal != gcvNULL);
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->queues[i].signal
++ ));
++
++ gcmkASSERT(Command->queues[i].logical != gcvNULL);
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ Command->os,
++ Command->pageSize,
++ Command->queues[i].physical,
++ Command->queues[i].logical
++ ));
++ }
++
++ /* END event signal. */
++ if (Command->endEventSignal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->endEventSignal
++ ));
++ }
++
++ /* Delete the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (Command->mutexContextSeq != gcvNULL)
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContextSeq));
++#endif
++
++ /* Delete the command queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexQueue));
++
++ /* Destroy the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Command->os, Command->powerSemaphore));
++
++ /* Destroy the commit atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Command->os, Command->atomCommit));
++
++#if gcdRECORD_COMMAND
++ gckRECORDER_Destory(Command->os, Command->recorder);
++#endif
++
++ /* Mark object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCOMMAND object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, Command));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_EnterCommit
++**
++** Acquire command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctBOOL atomIncremented = gcvFALSE;
++ gctBOOL semaAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (!FromPower)
++ {
++ /* Increment COMMIT atom to let power management know that a commit is
++ ** in progress. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvTRUE));
++ atomIncremented = gcvTRUE;
++
++ /* Notify the system the GPU has a commit. */
++ gcmkONERROR(gckOS_Broadcast(Command->os,
++ hardware,
++ gcvBROADCAST_GPU_COMMIT));
++
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(Command->os,
++ Command->powerSemaphore));
++ semaAcquired = gcvTRUE;
++ }
++
++ /* Grab the conmmand queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Command->os,
++ Command->mutexQueue,
++ gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (semaAcquired)
++ {
++ /* Release the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++ }
++
++ if (atomIncremented)
++ {
++ /* Decrement the commit atom. */
++ gcmkVERIFY_OK(_IncrementCommitAtom(
++ Command, gcvFALSE
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_ExitCommit
++**
++** Release command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexQueue));
++
++ if (!FromPower)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(Command->os,
++ Command->powerSemaphore));
++
++ /* Decrement the commit atom. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvFALSE));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Start
++**
++** Start up the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to start.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctUINT32 waitOffset = 0;
++ gctUINT32 waitLinkBytes;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->running)
++ {
++ /* Command queue already running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (Command->logical == gcvNULL)
++ {
++ /* Start at beginning of a new queue. */
++ gcmkONERROR(_NewQueue(Command));
++ }
++
++ /* Start at beginning of page. */
++ Command->offset = 0;
++
++ /* Set abvailable number of bytes for WAIT/LINK command sequence. */
++ waitLinkBytes = Command->pageSize;
++
++ /* Append WAIT/LINK. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ Command->logical,
++ 0,
++ &waitLinkBytes,
++ &waitOffset,
++ &Command->waitSize
++ ));
++
++ Command->waitLogical = (gctUINT8_PTR) Command->logical + waitOffset;
++ Command->waitPhysical = (gctUINT8_PTR) Command->physical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->physical,
++ Command->logical,
++ waitLinkBytes
++ ));
++#endif
++
++ /* Adjust offset. */
++ Command->offset = waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Enable command processor. */
++ gcmkONERROR(gckHARDWARE_Execute(
++ hardware,
++ Command->address,
++ waitLinkBytes
++ ));
++
++ /* Command queue is running. */
++ Command->running = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stop
++**
++** Stop the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to stop.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ )
++{
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (!Command->running)
++ {
++ /* Command queue is not running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (gckHARDWARE_IsFeatureAvailable(hardware,
++ gcvFEATURE_END_EVENT) == gcvSTATUS_TRUE)
++ {
++ /* Allocate the signal. */
++ if (Command->endEventSignal == gcvNULL)
++ {
++ gcmkONERROR(gckOS_CreateSignal(Command->os,
++ gcvTRUE,
++ &Command->endEventSignal));
++ }
++
++ /* Append the END EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Stop(Command->kernel->eventObj,
++ Command->kernelProcessID,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->endEventSignal,
++ &Command->waitSize));
++ }
++ else
++ {
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ hardware, Command->waitLogical, &Command->waitSize
++ ));
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(Command->kernel->hardware,
++ Command->logical,
++ Command->offset));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ /* Wait for idle. */
++ gcmkONERROR(gckHARDWARE_GetIdle(hardware, !FromRecovery, &idle));
++ }
++
++ /* Command queue is no longer running. */
++ Command->running = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Commit
++**
++** Commit a command buffer to the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object.
++**
++** gcoCMDBUF CommandBuffer
++** Pointer to a gcoCMDBUF object.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL contextAcquired = gcvFALSE;
++ gckHARDWARE hardware;
++ gctBOOL needCopy = gcvFALSE;
++ gcsQUEUE_PTR eventRecord = gcvNULL;
++ gcsQUEUE _eventRecord;
++ gcsQUEUE_PTR nextEventRecord;
++ gctBOOL commandBufferMapped = gcvFALSE;
++ gcoCMDBUF commandBufferObject = gcvNULL;
++
++#if !gcdNULL_DRIVER
++ gcsCONTEXT_PTR contextBuffer;
++ struct _gcoCMDBUF _commandBufferObject;
++ gctPHYS_ADDR commandBufferPhysical;
++ gctUINT8_PTR commandBufferLogical = gcvNULL;
++ gctUINT32 commandBufferAddress = 0;
++ gctUINT8_PTR commandBufferLink = gcvNULL;
++ gctUINT commandBufferSize;
++ gctSIZE_T nopBytes;
++ gctUINT32 pipeBytes;
++ gctUINT32 linkBytes;
++ gctSIZE_T bytes;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR entryPhysical;
++#endif
++ gctPOINTER entryLogical;
++ gctUINT32 entryAddress;
++ gctUINT32 entryBytes;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR exitPhysical;
++#endif
++ gctPOINTER exitLogical;
++ gctUINT32 exitAddress;
++ gctUINT32 exitBytes;
++ gctPHYS_ADDR waitLinkPhysical;
++ gctPOINTER waitLinkLogical;
++ gctUINT32 waitLinkAddress;
++ gctUINT32 waitLinkBytes;
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctUINT32 waitSize;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gctSIZE_T mmuConfigureBytes;
++ gctPOINTER mmuConfigureLogical = gcvNULL;
++ gctUINT32 mmuConfigureAddress;
++ gctPOINTER mmuConfigurePhysical = 0;
++ gctSIZE_T mmuConfigureWaitLinkOffset;
++ gckMMU mmu;
++ gctSIZE_T reservedBytes;
++ gctUINT32 oldValue;
++#endif
++
++#if gcdDUMP_COMMAND
++ gctPOINTER contextDumpLogical = gcvNULL;
++ gctSIZE_T contextDumpBytes = 0;
++ gctPOINTER bufferDumpLogical = gcvNULL;
++ gctSIZE_T bufferDumpBytes = 0;
++# endif
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gctBOOL sequenceAcquired = gcvFALSE;
++#endif
++
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG(
++ "Command=0x%x CommandBuffer=0x%x ProcessID=%d",
++ Command, CommandBuffer, ProcessID
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->kernel->hardware->type== gcvHARDWARE_2D)
++ {
++ /* There is no context for 2D. */
++ Context = gcvNULL;
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Command->kernel, &mmu));
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ mmu->pageTableDirty[Command->kernel->core],
++ 0,
++ &oldValue));
++#else
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ if((Command->kernel->hardware->gpuProfiler) && (Command->kernel->profileEnable))
++ {
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContextSeq, gcvINFINITE
++ ));
++ sequenceAcquired = gcvTRUE;
++ }
++#endif
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(Command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ contextAcquired = gcvTRUE;
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
++
++#if gcdNULL_DRIVER
++ /* Context switch required? */
++ if ((Context != gcvNULL) && (Command->currContext != Context))
++ {
++ /* Yes, merge in the deltas. */
++ gckCONTEXT_Update(Context, ProcessID, StateDelta);
++
++ /* Update the current context. */
++ Command->currContext = Context;
++ }
++#else
++ if (needCopy)
++ {
++ commandBufferObject = &_commandBufferObject;
++
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os,
++ commandBufferObject,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF)
++ ));
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ }
++ else
++ {
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ &pointer
++ ));
++
++ commandBufferObject = pointer;
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ commandBufferMapped = gcvTRUE;
++ }
++
++ /* Query the size of NOP command. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware, gcvNULL, &nopBytes
++ ));
++
++ /* Query the size of pipe select command sequence. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ hardware, gcvNULL, gcvPIPE_3D, &pipeBytes
++ ));
++
++ /* Query the size of LINK command. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware, gcvNULL, 0, 0, &linkBytes
++ ));
++
++ /* Compute the command buffer entry and the size. */
++ commandBufferLogical
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->startOffset;
++
++ /* Get the hardware address. */
++ if (Command->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckKERNEL_GetGPUAddress(
++ Command->kernel,
++ commandBufferLogical,
++ gcvTRUE,
++ &commandBufferAddress
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ hardware,
++ commandBufferLogical,
++ gcvTRUE,
++ &commandBufferAddress
++ ));
++ }
++
++ /* Get the physical address. */
++ gcmkONERROR(gckOS_UserLogicalToPhysical(
++ Command->os,
++ commandBufferLogical,
++ (gctUINT32_PTR)&commandBufferPhysical
++ ));
++
++ commandBufferSize
++ = commandBufferObject->offset
++ + Command->reservedTail
++ - commandBufferObject->startOffset;
++
++ gcmkONERROR(_FlushMMU(Command));
++
++ /* Get the current offset. */
++ offset = Command->offset;
++
++ /* Compute number of bytes left in current kernel command queue. */
++ bytes = Command->pageSize - offset;
++
++ /* Query the size of WAIT/LINK command sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ gcvNULL,
++ offset,
++ &waitLinkBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < waitLinkBytes)
++ {
++ /* No, create a new one. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Get the new current offset. */
++ offset = Command->offset;
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - offset;
++ gcmkASSERT(bytes >= waitLinkBytes);
++ }
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + offset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + offset;
++ waitLinkAddress = Command->address + offset;
++
++ /* Context switch required? */
++ if (Context == gcvNULL)
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryAddress = commandBufferAddress + offset;
++ entryBytes = commandBufferSize - offset;
++
++ Command->currContext = gcvNULL;
++ }
++ else if (Command->currContext != Context)
++ {
++ /* Temporary disable context length oprimization. */
++ Context->dirty = gcvTRUE;
++
++ /* Get the current context buffer. */
++ contextBuffer = Context->buffer;
++
++ /* Yes, merge in the deltas. */
++ gcmkONERROR(gckCONTEXT_Update(Context, ProcessID, StateDelta));
++
++ /* Determine context entry and exit points. */
++ if (0)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D and 3D are used.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++
++ /* Mark context as not dirty. */
++ Context->dirty = gcvFALSE;
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D only command buffer.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++ /* Not using 2D. */
++ else
++ {
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 3D only command buffer.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + Context->pipeSelectBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryAddress = contextBuffer->address + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: "XD" command buffer - neither 2D nor 3D.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_3D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom3D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom3D;
++
++ entryAddress
++ = contextBuffer->address
++ + Context->entryOffsetXDFrom3D;
++
++ entryBytes
++ = Context->bufferSize
++ - Context->entryOffsetXDFrom3D;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom2D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom2D;
++
++ entryAddress
++ = contextBuffer->address
++ + Context->entryOffsetXDFrom2D;
++
++ entryBytes
++ = Context->totalSize
++ - Context->entryOffsetXDFrom2D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the context buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)entryPhysical,
++ entryLogical,
++ entryBytes
++ ));
++#endif
++
++ /* Update the current context. */
++ Command->currContext = Context;
++
++#if gcdDUMP_COMMAND
++ contextDumpLogical = entryLogical;
++ contextDumpBytes = entryBytes;
++#endif
++
++#if gcdRECORD_COMMAND
++ gckRECORDER_Record(
++ Command->recorder,
++ gcvNULL,
++ 0xFFFFFFFF,
++ entryLogical,
++ entryBytes - 8
++ );
++#endif
++ }
++
++ /* Same context. */
++ else
++ {
++ /* Determine context entry and exit points. */
++ if (commandBufferObject->using2D && Context->dirty2D)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++ else
++ {
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + pipeBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryAddress = contextBuffer->address + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryAddress = commandBufferAddress + offset;
++ entryBytes = commandBufferSize - offset;
++ }
++ }
++ }
++
++#if gcdDUMP_COMMAND
++ bufferDumpLogical = commandBufferLogical + offset;
++ bufferDumpBytes = commandBufferSize - offset;
++#endif
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = Command->physical;
++#endif
++
++ exitLogical = Command->logical;
++ exitAddress = Command->address;
++ exitBytes = Command->offset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump to the new
++ WAIT/LINK command sequence. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = waitLinkPhysical;
++#endif
++ exitLogical = waitLinkLogical;
++ exitAddress = waitLinkAddress;
++ exitBytes = waitLinkBytes;
++ }
++
++ /* Add a new WAIT/LINK command sequence. When the command buffer which is
++ currently being scheduled is fully executed by the GPU, the FE will
++ jump to this WAIT/LINK sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ waitLinkLogical,
++ offset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitSize
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = (gctUINT8_PTR) waitLinkLogical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command queue cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)exitPhysical,
++ exitLogical,
++ exitBytes
++ ));
++#endif
++
++ /* Determine the location of the LINK command in the command buffer. */
++ commandBufferLink
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->offset;
++
++ /* Generate a LINK from the end of the command buffer being scheduled
++ back to the kernel command queue. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ commandBufferLink,
++ exitAddress,
++ exitBytes,
++ &linkBytes
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ ProcessID,
++ gcvNULL,
++ (gctUINT32)commandBufferPhysical,
++ commandBufferLogical,
++ commandBufferSize
++ ));
++#endif
++
++#if gcdRECORD_COMMAND
++ gckRECORDER_Record(
++ Command->recorder,
++ commandBufferLogical + offset,
++ commandBufferSize - offset - 8,
++ gcvNULL,
++ 0xFFFFFFFF
++ );
++
++ gckRECORDER_AdvanceIndex(Command->recorder, Command->commitStamp);
++
++ Command->commitStamp++;
++#endif
++
++ /* Generate a LINK from the previous WAIT/LINK command sequence to the
++ entry determined above (either the context or the command buffer).
++ This LINK replaces the WAIT instruction from the previous WAIT/LINK
++ pair, therefore we use WAIT metrics for generation of this LINK.
++ This action will execute the entire sequence. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ Command->waitLogical,
++ entryAddress,
++ entryBytes,
++ &Command->waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ contextDumpLogical,
++ contextDumpBytes,
++ gceDUMP_BUFFER_CONTEXT,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ bufferDumpLogical,
++ bufferDumpBytes,
++ gceDUMP_BUFFER_USER,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ waitLinkLogical,
++ waitLinkBytes,
++ gceDUMP_BUFFER_WAITLINK,
++ gcvFALSE
++ );
++
++ /* Update the current pipe. */
++ Command->pipeSelect = commandBufferObject->exitPipe;
++
++ /* Update command queue offset. */
++ Command->offset += waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update address of last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitSize;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.commit]");
++#endif
++#endif /* gcdNULL_DRIVER */
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ contextAcquired = gcvFALSE;
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ commitEntered = gcvFALSE;
++
++#if VIVANTE_PROFILER_CONTEXT
++ if(sequenceAcquired)
++ {
++ gcmkONERROR(gckCOMMAND_Stall(Command, gcvTRUE));
++ if (Command->currContext)
++ {
++ gcmkONERROR(gckHARDWARE_UpdateContextProfile(
++ hardware,
++ Command->currContext));
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ sequenceAcquired = gcvFALSE;
++ }
++#endif
++
++ /* Loop while there are records in the queue. */
++ while (EventQueue != gcvNULL)
++ {
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ eventRecord = &_eventRecord;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os, eventRecord, EventQueue, gcmSIZEOF(gcsQUEUE)
++ ));
++ }
++ else
++ {
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ eventRecord = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(gckEVENT_AddList(
++ Command->kernel->eventObj, &eventRecord->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE
++ ));
++
++ /* Next record in the queue. */
++ nextEventRecord = gcmUINT64_TO_PTR(eventRecord->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os, EventQueue, gcmSIZEOF(gcsQUEUE), (gctPOINTER *) eventRecord
++ ));
++
++ eventRecord = gcvNULL;
++ }
++
++ EventQueue = nextEventRecord;
++ }
++
++ if (Command->kernel->eventObj->queueHead == gcvNULL
++ && Command->kernel->hardware->powerManagement == gcvTRUE
++ )
++ {
++ /* Commit done event by which work thread knows all jobs done. */
++ gcmkVERIFY_OK(
++ gckEVENT_CommitDone(Command->kernel->eventObj, gcvKERNEL_PIXEL));
++ }
++
++ /* Submit events. */
++ status = gckEVENT_Submit(Command->kernel->eventObj, gcvTRUE, gcvFALSE, gcvTRUE);
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkTRACE(
++ gcvLEVEL_INFO,
++ "%s(%d): Intterupted in gckEVENT_Submit",
++ __FUNCTION__, __LINE__
++ );
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++
++ commandBufferMapped = gcvFALSE;
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((eventRecord != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) eventRecord
++ ));
++ }
++
++ if (contextAcquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (sequenceAcquired)
++ {
++ /* Release the context sequence mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ }
++#endif
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Reserve
++**
++** Reserve space in the command queue. Also acquire the command queue mutex.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** gctPOINTER * Buffer
++** Pointer to a variable that will receive the address of the reserved
++** space.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable that will receive the number of bytes
++** available in the command queue.
++*/
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctUINT32 * BufferSize
++ )
++{
++ gceSTATUS status;
++ gctUINT32 bytes;
++ gctUINT32 requiredBytes;
++ gctUINT32 requestedAligned;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute aligned number of reuested bytes. */
++ requestedAligned = gcmALIGN(RequestedBytes, Command->alignment);
++
++ /* Another WAIT/LINK command sequence will have to be appended after
++ the requested area being reserved. Compute the number of bytes
++ required for WAIT/LINK at the location after the reserved area. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ gcvNULL,
++ Command->offset + requestedAligned,
++ &requiredBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Compute total number of bytes required. */
++ requiredBytes += requestedAligned;
++
++ /* Compute number of bytes available in command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < requiredBytes)
++ {
++ /* Create a new command queue. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Still not enough space? */
++ if (bytes < requiredBytes)
++ {
++ /* Rare case, not enough room in command queue. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++ }
++
++ /* Return pointer to empty slot command queue. */
++ *Buffer = (gctUINT8 *) Command->logical + Command->offset;
++
++ /* Return number of bytes left in command queue. */
++ *BufferSize = bytes;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Buffer=0x%x *BufferSize=%lu", *Buffer, *BufferSize);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Execute
++**
++** Execute a previously reserved command queue by appending a WAIT/LINK command
++** sequence after it and modifying the last WAIT into a LINK command. The
++** command FIFO mutex will be released whether this function succeeds or not.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequestedBytes
++ )
++{
++ gceSTATUS status;
++
++ gctPHYS_ADDR waitLinkPhysical;
++ gctUINT8_PTR waitLinkLogical;
++ gctUINT32 waitLinkOffset;
++ gctUINT32 waitLinkBytes;
++
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctUINT32 waitBytes;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR execPhysical;
++#endif
++ gctPOINTER execLogical;
++ gctUINT32 execAddress;
++ gctUINT32 execBytes;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute offset for WAIT/LINK. */
++ waitLinkOffset = Command->offset + RequestedBytes;
++
++ /* Compute number of bytes left in command queue. */
++ waitLinkBytes = Command->pageSize - waitLinkOffset;
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + waitLinkOffset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + waitLinkOffset;
++
++ /* Append WAIT/LINK in command queue. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ waitLinkLogical,
++ waitLinkOffset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitBytes
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = waitLinkLogical + waitOffset;
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = Command->physical;
++#endif
++ execLogical = Command->logical;
++ execAddress = Command->address;
++ execBytes = waitLinkOffset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump directly to the
++ reserved area. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = (gctUINT8 *) Command->physical + Command->offset;
++#endif
++ execLogical = (gctUINT8 *) Command->logical + Command->offset;
++ execAddress = Command->address + Command->offset;
++ execBytes = RequestedBytes + waitLinkBytes;
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)execPhysical,
++ execLogical,
++ execBytes
++ ));
++#endif
++
++ /* Convert the last WAIT into a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Command->kernel->hardware,
++ Command->waitLogical,
++ execAddress,
++ execBytes,
++ &Command->waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ execLogical,
++ execBytes,
++ gceDUMP_BUFFER_KERNEL,
++ gcvFALSE
++ );
++
++ /* Update the pointer to the last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitBytes;
++
++ /* Update the command queue. */
++ Command->offset += RequestedBytes + waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ Command->kernel->hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.execute]");
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stall
++**
++** The calling thread will be suspended until the command queue has been
++** completed.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++#if gcdNULL_DRIVER
++ /* Do nothing with infinite hardware. */
++ return gcvSTATUS_OK;
++#else
++ gckOS os;
++ gckHARDWARE hardware;
++ gckEVENT eventObject;
++ gceSTATUS status;
++ gctSIGNAL signal = gcvNULL;
++ gctUINT timer = 0;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Extract the gckOS object pointer. */
++ os = Command->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Extract the gckEVENT object pointer. */
++ eventObject = Command->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObject, gcvOBJ_EVENT);
++
++ /* Allocate the signal. */
++ gcmkONERROR(gckOS_CreateSignal(os, gcvTRUE, &signal));
++
++ /* Append the EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Signal(eventObject, signal, gcvKERNEL_PIXEL));
++
++ /* Submit the event queue. */
++ gcmkONERROR(gckEVENT_Submit(eventObject, gcvTRUE, FromPower, gcvFALSE));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.stall]");
++#endif
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ /* Error. */
++ goto OnError;
++ }
++
++ do
++ {
++ /* Wait for the signal. */
++ status = gckOS_WaitSignal(os, signal, gcdGPU_ADVANCETIMER);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT32 idle;
++
++ /* Read idle register. */
++ gcmkVERIFY_OK(gckHARDWARE_GetIdle(
++ hardware, gcvFALSE, &idle
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): idle=%08x",
++ __FUNCTION__, __LINE__, idle
++ );
++
++ gcmkVERIFY_OK(gckOS_MemoryBarrier(os, gcvNULL));
++#endif
++
++ /* Advance timer. */
++ timer += gcdGPU_ADVANCETIMER;
++ }
++ else if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkONERROR(gcvSTATUS_INTERRUPTED);
++ }
++
++ }
++ while (gcmIS_ERROR(status));
++
++ /* Bail out on timeout. */
++ if (gcmIS_ERROR(status))
++ {
++ /* Broadcast the stuck GPU. */
++ gcmkONERROR(gckOS_Broadcast(
++ os, hardware, gcvBROADCAST_GPU_STUCK
++ ));
++ }
++
++ /* Delete the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ /* Free the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Attach
++**
++** Attach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable that will receive a pointer to a new
++** gckCONTEXT object.
++**
++** gctSIZE_T * StateCount
++** Pointer to a variable that will receive the number of states
++** in the context buffer.
++*/
++#if (gcdENABLE_3D || gcdENABLE_2D)
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Construct(
++ Command->os,
++ Command->kernel->hardware,
++ ProcessID,
++ Context
++ ));
++
++ /* Return the number of states in the context. */
++ * StateCount = (* Context)->stateCount;
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%x", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckCOMMAND_Detach
++**
++** Detach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x", Command, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Destroy(Context));
++
++ if (Command->currContext == Context)
++ {
++ /* Detach from gckCOMMAND object if the destoryed context is current context. */
++ Command->currContext = gcvNULL;
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_DumpExecutingBuffer
++**
++** Dump the command buffer which GPU is executing.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 gpuAddress;
++ gctSIZE_T pageCount;
++ gctPOINTER entry;
++ gckOS os = Command->os;
++ gckKERNEL kernel = Command->kernel;
++ gctINT pid;
++ gctUINT32 i, rear;
++ gctUINT32 start, end;
++ gctUINT32 dumpFront, dumpRear;
++ gckLINKQUEUE queue = &kernel->hardware->linkQueue;
++ gckLINKQUEUE queueMirror;
++ gctUINT32 bytes;
++ gckLINKDATA linkData;
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("**** COMMAND BUF DUMP ****\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(os, kernel->core, 0x664, &gpuAddress));
++
++ gcmkPRINT("DMA Address 0x%08X", gpuAddress);
++
++ if (Command->kernel->stuckDump > gcdSTUCK_DUMP_MIDDLE)
++ {
++ gcmkPRINT("Dump Level is %d", Command->kernel->stuckDump);
++
++ /* Duplicate queue because it will be changed.*/
++ gcmkONERROR(gckOS_AllocateMemory(os,
++ sizeof(struct _gckLINKQUEUE),
++ (gctPOINTER *)&queueMirror));
++
++ gckOS_MemCopy(queueMirror,
++ queue,
++ sizeof(struct _gckLINKQUEUE));
++
++ /* If kernel command buffer link to a context buffer, then link to a user command
++ ** buffer, the second link will be in queue first, so we must fix this.
++ ** In Queue: C1 U1 U2 C2 U3 U4 U5 C3
++ ** Real: C1 X1 U1 C2 U2 U3 U4 C3 U5
++ ** Command buffer X1 which is after C1 is out of queue, so C1 is meaningless.
++ */
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Can't find it in virtual command buffer list, ignore it. */
++ continue;
++ }
++
++ if (buffer->kernelLogical)
++ {
++ /* It is a context buffer. */
++ if (i == 0)
++ {
++ /* The real command buffer is out, so clear this slot. */
++ linkData->start = 0;
++ linkData->end = 0;
++ linkData->pid = 0;
++ }
++ else
++ {
++ /* switch context buffer and command buffer. */
++ struct _gckLINKDATA tmp = *linkData;
++ gckLINKDATA linkDataPrevious;
++
++ gckLINKQUEUE_GetData(queueMirror, i - 1, &linkDataPrevious);
++ *linkData = *linkDataPrevious;
++ *linkDataPrevious = tmp;
++ }
++ }
++ }
++
++ /* Clear search result. */
++ dumpFront = dumpRear = gcvINFINITE;
++
++ gcmkPRINT("Link Stack:");
++
++ /* Search stuck address in link queue from rear. */
++ rear = gcdLINK_QUEUE_SIZE - 1;
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ start = linkData->start;
++ end = linkData->end;
++ pid = linkData->pid;
++
++ if (gpuAddress >= start && gpuAddress < end)
++ {
++ /* Find latest matched command buffer. */
++ gcmkPRINT(" %d, [%08X - %08X]", pid, start, end);
++
++ /* Initiliaze dump information. */
++ dumpFront = dumpRear = rear;
++ }
++
++ /* Advance to previous one. */
++ rear--;
++
++ if (dumpFront != gcvINFINITE)
++ {
++ break;
++ }
++ }
++
++ if (dumpFront == gcvINFINITE)
++ {
++ /* Can't find matched record in link queue, dump kernel command buffer. */
++ _DumpKernelCommandBuffer(Command);
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++ }
++
++ /* Search the last context buffer linked. */
++ while (rear > 0)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ gcmkPRINT(" %d, [%08X - %08X]",
++ linkData->pid,
++ linkData->start,
++ linkData->end);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_SUCCESS(status) && buffer->kernelLogical)
++ {
++ /* Find a context buffer. */
++ dumpFront = rear;
++ break;
++ }
++
++ rear--;
++ }
++
++ if (dumpFront == dumpRear)
++ {
++ /* No context buffer is found, dump all we got.*/
++ dumpFront = 0;
++ }
++
++ /* Dump from last context buffer to last command buffer where hang happens. */
++ for (i = dumpFront; i <= dumpRear; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ /* Get gpu address of this command buffer. */
++ gpuAddress = linkData->start;
++ bytes = linkData->end - gpuAddress;
++
++ /* Get the whole buffer. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkPRINT("Buffer [%08X - %08X] is lost or not belong to current process",
++ linkData->start,
++ linkData->end);
++ continue;
++ }
++
++ /* Get kernel logical for dump. */
++ if (buffer->kernelLogical)
++ {
++ /* Get kernel logical directly if it is a context buffer. */
++ entry = buffer->kernelLogical;
++ gcmkPRINT("Context Buffer:");
++ }
++ else
++ {
++ /* Make it accessiable by kernel if it is a user command buffer. */
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ &entry,
++ &pageCount));
++ gcmkPRINT("User Command Buffer:");
++ }
++
++ /* Dump from the entry. */
++ _DumpBuffer((gctUINT8_PTR)entry + (gpuAddress - buffer->gpuAddress), gpuAddress, bytes);
++
++ /* Release kernel logical address if neccessary. */
++ if (!buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ entry));
++ }
++ }
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++ OnError:
++ return status;
++ }
++ else
++ {
++ gcmkPRINT("Dump Level is %d, dump memory near the stuck address",
++ Command->kernel->stuckDump);
++
++ /* Without link queue information, we don't know the entry of last command
++ ** buffer, just dump the page where GPU stuck. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ &entry,
++ &pageCount));
++
++ if (entry)
++ {
++ gctUINT32 offset = gpuAddress - buffer->gpuAddress;
++ gctPOINTER entryDump = entry;
++
++ /* Dump one pages. */
++ gctUINT32 bytes = 4096;
++
++ /* Align to page. */
++ offset &= 0xfffff000;
++
++ /* Kernel address of page where stall point stay. */
++ entryDump = (gctUINT8_PTR)entryDump + offset;
++
++ /* Align to page. */
++ gpuAddress &= 0xfffff000;
++
++ gcmkPRINT("User Command Buffer:\n");
++ _DumpBuffer(entryDump, gpuAddress, bytes);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ entry));
++ }
++ else
++ {
++ _DumpKernelCommandBuffer(Command);
++ }
++
++ return gcvSTATUS_OK;
++ }
++}
++
++gceSTATUS
++gckCOMMAND_AddressInKernelCommandBuffer(
++ IN gckCOMMAND Command,
++ IN gctUINT32 Address,
++ OUT gctBOOL *In
++ )
++{
++ gctBOOL in = gcvFALSE;
++ gctINT i;
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ if ((Address >= Command->queues[i].address)
++ && (Address < (Command->queues[i].address + Command->pageSize))
++ )
++ {
++ in = gcvTRUE;
++ break;
++ }
++ }
++
++ *In = in;
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_command_vg.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_command_vg.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_command_vg.c 2016-06-19 22:11:55.137151030 +0200
+@@ -0,0 +1,3678 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++*********************************** Debugging **********************************
++\******************************************************************************/
++
++#define gcvDISABLE_TIMEOUT 1
++#define gcvDUMP_COMMAND_BUFFER 0
++#define gcvDUMP_COMMAND_LINES 0
++
++
++#if gcvDEBUG || defined(EMULATOR) || gcvDISABLE_TIMEOUT
++# define gcvQUEUE_TIMEOUT ~0
++#else
++# define gcvQUEUE_TIMEOUT 10
++#endif
++
++
++/******************************************************************************\
++********************************** Definitions *********************************
++\******************************************************************************/
++
++/* Minimum buffer size. */
++#define gcvMINUMUM_BUFFER \
++ gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) + \
++ gcmSIZEOF(gcsKERNEL_CMDQUEUE) * 2
++
++#define gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ static gceSTATUS \
++ _EventHandler_##Block##_##Number( \
++ IN gckVGKERNEL Kernel \
++ )
++
++#define gcmDEFINE_INTERRUPT_HANDLER(Block, Number) \
++ gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ { \
++ return _EventHandler_Block( \
++ Kernel, \
++ &Kernel->command->taskTable[gcvBLOCK_##Block], \
++ gcvFALSE \
++ ); \
++ }
++
++#define gcmDEFINE_INTERRUPT_HANDLER_ENTRY(Block, Number) \
++ { gcvBLOCK_##Block, _EventHandler_##Block##_##Number }
++
++/* Block interrupt handling table entry. */
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER * gcsBLOCK_INTERRUPT_HANDLER_PTR;
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER
++{
++ gceBLOCK block;
++ gctINTERRUPT_HANDLER handler;
++}
++gcsBLOCK_INTERRUPT_HANDLER;
++
++/* Queue control functions. */
++typedef struct _gcsQUEUE_UPDATE_CONTROL * gcsQUEUE_UPDATE_CONTROL_PTR;
++typedef struct _gcsQUEUE_UPDATE_CONTROL
++{
++ gctOBJECT_HANDLER execute;
++ gctOBJECT_HANDLER update;
++ gctOBJECT_HANDLER lastExecute;
++ gctOBJECT_HANDLER lastUpdate;
++}
++gcsQUEUE_UPDATE_CONTROL;
++
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_FlushMMU(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckVGHARDWARE hardware = Command->hardware;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckVGHARDWARE_FlushMMU(hardware));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_WaitForIdle(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 idle;
++ gctUINT timeout = 0;
++
++ /* Loop while not idle. */
++ while (Queue->pending)
++ {
++ /* Did we reach the timeout limit? */
++ if (timeout == gcvQUEUE_TIMEOUT)
++ {
++ /* Hardware is probably dead... */
++ return gcvSTATUS_TIMEOUT;
++ }
++
++ /* Sleep for 100ms. */
++ gcmkERR_BREAK(gckOS_Delay(Command->os, 100));
++
++ /* Not the first loop? */
++ if (timeout > 0)
++ {
++ /* Read IDLE register. */
++ gcmkVERIFY_OK(gckVGHARDWARE_GetIdle(Command->hardware, &idle));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_COMMAND,
++ "%s: timeout, IDLE=%08X\n",
++ __FUNCTION__, idle
++ );
++ }
++
++ /* Increment the timeout counter. */
++ timeout += 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gctINT32
++_GetNextInterrupt(
++ IN gckVGCOMMAND Command,
++ IN gceBLOCK Block
++ )
++{
++ gctUINT index;
++ gcsBLOCK_TASK_ENTRY_PTR entry;
++ gctINT32 interrupt;
++
++ /* Get the block entry. */
++ entry = &Command->taskTable[Block];
++
++ /* Make sure we have initialized interrupts. */
++ gcmkASSERT(entry->interruptCount > 0);
++
++ /* Decrement the interrupt usage semaphore. */
++ gcmkVERIFY_OK(gckOS_DecrementSemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++
++ /* Get the value index. */
++ index = entry->interruptIndex;
++
++ /* Get the interrupt value. */
++ interrupt = entry->interruptArray[index];
++
++ /* Must be a valid value. */
++ gcmkASSERT((interrupt >= 0) && (interrupt <= 31));
++
++ /* Advance the index to the next value. */
++ index += 1;
++
++ /* Set the new index. */
++ entry->interruptIndex = (index == entry->interruptCount)
++ ? 0
++ : index;
++
++ /* Return interrupt value. */
++ return interrupt;
++}
++
++
++/******************************************************************************\
++***************************** Task Storage Management **************************
++\******************************************************************************/
++
++/* Minimum task buffer size. */
++#define gcvMIN_TASK_BUFFER \
++( \
++ gcmSIZEOF(gcsTASK_CONTAINER) + 128 \
++)
++
++/* Free list terminator. */
++#define gcvFREE_TASK_TERMINATOR \
++( \
++ (gcsTASK_CONTAINER_PTR) gcmINT2PTR(~0) \
++)
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------- Allocated Task Buffer List Management ------------------*/
++
++static void
++_InsertTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR AddAfter,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR addBefore;
++
++ /* Cannot add before the first buffer. */
++ gcmkASSERT(AddAfter != gcvNULL);
++
++ /* Create a shortcut to the next buffer. */
++ addBefore = AddAfter->allocNext;
++
++ /* Initialize the links. */
++ Buffer->allocPrev = AddAfter;
++ Buffer->allocNext = addBefore;
++
++ /* Link to the previous buffer. */
++ AddAfter->allocNext = Buffer;
++
++ /* Link to the next buffer. */
++ if (addBefore != gcvNULL)
++ {
++ addBefore->allocPrev = Buffer;
++ }
++}
++
++static void
++_RemoveTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++
++ /* Cannot remove the first buffer. */
++ gcmkASSERT(Buffer->allocPrev != gcvNULL);
++
++ /* Create shortcuts to the previous and next buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Tail buffer? */
++ if (next == gcvNULL)
++ {
++ /* Remove from the list. */
++ prev->allocNext = gcvNULL;
++ }
++
++ /* Buffer from the middle. */
++ else
++ {
++ prev->allocNext = next;
++ next->allocPrev = prev;
++ }
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*--------------------- Free Task Buffer List Management ---------------------*/
++
++static void
++_AppendToFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Cannot be a part of the free list already. */
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* First buffer to add? */
++ if (Command->taskFreeHead == gcvNULL)
++ {
++ /* Terminate the links. */
++ Buffer->freePrev = gcvFREE_TASK_TERMINATOR;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Initialize the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = Buffer;
++ }
++
++ /* Not the first, add after the tail. */
++ else
++ {
++ /* Initialize the new tail buffer. */
++ Buffer->freePrev = Command->taskFreeTail;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Add after the tail. */
++ Command->taskFreeTail->freeNext = Buffer;
++ Command->taskFreeTail = Buffer;
++ }
++}
++
++static void
++_RemoveFromFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Has to be a part of the free list. */
++ gcmkASSERT(Buffer->freePrev != gcvNULL);
++ gcmkASSERT(Buffer->freeNext != gcvNULL);
++
++ /* Head buffer? */
++ if (Buffer->freePrev == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Tail buffer as well? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Reset the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = gcvNULL;
++ }
++
++ /* No, just the head. */
++ else
++ {
++ /* Update the head. */
++ Command->taskFreeHead = Buffer->freeNext;
++
++ /* Terminate the next buffer. */
++ Command->taskFreeHead->freePrev = gcvFREE_TASK_TERMINATOR;
++ }
++ }
++
++ /* Not the head. */
++ else
++ {
++ /* Tail buffer? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Update the tail. */
++ Command->taskFreeTail = Buffer->freePrev;
++
++ /* Terminate the previous buffer. */
++ Command->taskFreeTail->freeNext = gcvFREE_TASK_TERMINATOR;
++ }
++
++ /* A buffer in the middle. */
++ else
++ {
++ /* Remove the buffer from the list. */
++ Buffer->freePrev->freeNext = Buffer->freeNext;
++ Buffer->freeNext->freePrev = Buffer->freePrev;
++ }
++ }
++
++ /* Reset free list pointers. */
++ Buffer->freePrev = gcvNULL;
++ Buffer->freeNext = gcvNULL;
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- Task Buffer Allocation --------------------------*/
++
++static void
++_SplitTaskBuffer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer,
++ IN gctUINT Size
++ )
++{
++ /* Determine the size of the new buffer. */
++ gctINT splitBufferSize = Buffer->size - Size;
++ gcmkASSERT(splitBufferSize >= 0);
++
++ /* Is the split buffer big enough to become a separate buffer? */
++ if (splitBufferSize >= gcvMIN_TASK_BUFFER)
++ {
++ /* Place the new path data. */
++ gcsTASK_CONTAINER_PTR splitBuffer = (gcsTASK_CONTAINER_PTR)
++ (
++ (gctUINT8_PTR) Buffer + Size
++ );
++
++ /* Set the trimmed buffer size. */
++ Buffer->size = Size;
++
++ /* Initialize the split buffer. */
++ splitBuffer->referenceCount = 0;
++ splitBuffer->size = splitBufferSize;
++ splitBuffer->freePrev = gcvNULL;
++ splitBuffer->freeNext = gcvNULL;
++
++ /* Link in. */
++ _InsertTaskBuffer(Buffer, splitBuffer);
++ _AppendToFreeList(Command, splitBuffer);
++ }
++}
++
++static gceSTATUS
++_AllocateTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ OUT gcsTASK_CONTAINER_PTR * Buffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x, Buffer ==0x%x", Command, Size, Buffer);
++
++ /* Verify arguments. */
++ gcmkVERIFY_ARGUMENT(Buffer != gcvNULL);
++
++ do
++ {
++ gcsTASK_STORAGE_PTR storage;
++ gcsTASK_CONTAINER_PTR buffer;
++
++ /* Adjust the size. */
++ Size += gcmSIZEOF(gcsTASK_CONTAINER);
++
++ /* Adjust the allocation size if not big enough. */
++ if (Size > Command->taskStorageUsable)
++ {
++ Command->taskStorageGranularity
++ = gcmALIGN(Size + gcmSIZEOF(gcsTASK_STORAGE), 1024);
++
++ Command->taskStorageUsable
++ = Command->taskStorageGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++ }
++
++ /* Is there a free buffer available? */
++ else if (Command->taskFreeHead != gcvNULL)
++ {
++ /* Set the initial free buffer. */
++ gcsTASK_CONTAINER_PTR buffer = Command->taskFreeHead;
++
++ do
++ {
++ /* Is the buffer big enough? */
++ if (buffer->size >= Size)
++ {
++ /* Remove the buffer from the free list. */
++ _RemoveFromFreeList(Command, buffer);
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++
++ /* Get the next free buffer. */
++ buffer = buffer->freeNext;
++ }
++ while (buffer != gcvFREE_TASK_TERMINATOR);
++ }
++
++ /* Allocate a container. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Command->os,
++ Command->taskStorageGranularity,
++ (gctPOINTER *) &storage
++ ));
++
++ /* Link in the storage buffer. */
++ storage->next = Command->taskStorage;
++ Command->taskStorage = storage;
++
++ /* Place the task buffer. */
++ buffer = (gcsTASK_CONTAINER_PTR) (storage + 1);
++
++ /* Determine the size of the buffer. */
++ buffer->size
++ = Command->taskStorageGranularity
++ - gcmSIZEOF(gcsTASK_STORAGE);
++
++ /* Initialize the task buffer. */
++ buffer->referenceCount = 0;
++ buffer->allocPrev = gcvNULL;
++ buffer->allocNext = gcvNULL;
++ buffer->freePrev = gcvNULL;
++ buffer->freeNext = gcvNULL;
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++static void
++_FreeTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++ gcsTASK_CONTAINER_PTR merged;
++
++ gctUINT32 mergedSize;
++
++ /* Verify arguments. */
++ gcmkASSERT(Buffer != gcvNULL);
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* Get shortcuts to the previous and next path data buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Is the previous path data buffer already free? */
++ if (prev && prev->freeNext)
++ {
++ /* The previous path data buffer is the one that remains. */
++ merged = prev;
++
++ /* Is the next path data buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge all three path data buffers into the previous. */
++ mergedSize = prev->size + Buffer->size + next->size;
++
++ /* Remove the next path data buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++ }
++ else
++ {
++ /* Merge the current path data buffer into the previous. */
++ mergedSize = prev->size + Buffer->size;
++ }
++
++ /* Delete the current path data buffer. */
++ _RemoveTaskBuffer(Buffer);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++ else
++ {
++ /* The current path data buffer is the one that remains. */
++ merged = Buffer;
++
++ /* Is the next buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge the next into the current. */
++ mergedSize = Buffer->size + next->size;
++
++ /* Remove the next buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++
++ /* Add the current buffer into the free list. */
++ _AppendToFreeList(Command, merged);
++ }
++}
++
++gceSTATUS
++_RemoveRecordFromProcesDB(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_HEADER_PTR Task
++ )
++{
++ gceSTATUS status;
++ gcsTASK_PTR task = (gcsTASK_PTR)((gctUINT8_PTR)Task - sizeof(gcsTASK));
++ gcsTASK_FREE_VIDEO_MEMORY_PTR freeVideoMemory;
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR unlockVideoMemory;
++ gctINT pid;
++ gctUINT32 size;
++ gctUINT32 handle;
++ gckKERNEL kernel = Command->kernel->kernel;
++ gckVIDMEM_NODE unlockNode = gcvNULL;
++ gckVIDMEM_NODE nodeObject = gcvNULL;
++ gceDATABASE_TYPE type;
++
++ /* Get the total size of all tasks. */
++ size = task->size;
++
++ gcmkVERIFY_OK(gckOS_GetProcessID((gctUINT32_PTR)&pid));
++
++ do
++ {
++ switch (Task->id)
++ {
++ case gcvTASK_FREE_VIDEO_MEMORY:
++ freeVideoMemory = (gcsTASK_FREE_VIDEO_MEMORY_PTR)Task;
++
++ handle = (gctUINT32)freeVideoMemory->node;
++
++ status = gckVIDMEM_HANDLE_Lookup(
++ Command->kernel->kernel,
++ pid,
++ handle,
++ &nodeObject);
++
++ if (gcmIS_ERROR(status))
++ {
++ return status;
++ }
++
++ gckVIDMEM_HANDLE_Dereference(kernel, pid, handle);
++ freeVideoMemory->node = gcmALL_TO_UINT32(nodeObject);
++
++ type = gcvDB_VIDEO_MEMORY
++ | (nodeObject->type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT)
++ | (nodeObject->pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT);
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ type,
++ gcmINT2PTR(handle)));
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_FREE_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(freeVideoMemory + 1);
++
++ break;
++ case gcvTASK_UNLOCK_VIDEO_MEMORY:
++ unlockVideoMemory = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR)Task;
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(unlockVideoMemory->node)));
++
++ handle = (gctUINT32)unlockVideoMemory->node;
++
++ status = gckVIDMEM_HANDLE_Lookup(
++ Command->kernel->kernel,
++ pid,
++ handle,
++ &unlockNode);
++
++ if (gcmIS_ERROR(status))
++ {
++ return status;
++ }
++
++ gckVIDMEM_HANDLE_Dereference(kernel, pid, handle);
++ unlockVideoMemory->node = gcmPTR_TO_UINT64(unlockNode);
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_UNLOCK_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(unlockVideoMemory + 1);
++
++ break;
++ default:
++ /* Skip the whole task. */
++ size = 0;
++ break;
++ }
++ }
++ while(size);
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++********************************* Task Scheduling ******************************
++\******************************************************************************/
++
++static gceSTATUS
++_ScheduleTasks(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable,
++ IN gctUINT8_PTR PreviousEnd
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gctINT block;
++ gcsTASK_CONTAINER_PTR container;
++ gcsTASK_MASTER_ENTRY_PTR userTaskEntry;
++ gcsBLOCK_TASK_ENTRY_PTR kernelTaskEntry;
++ gcsTASK_PTR userTask;
++ gctUINT8_PTR kernelTask;
++ gctINT32 interrupt;
++ gctUINT8_PTR eventCommand;
++
++ /* Nothing to schedule? */
++ if (TaskTable->size == 0)
++ {
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->taskMutex,
++ gcvINFINITE
++ ));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ do
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " number of tasks scheduled = %d\n"
++ " size of event data in bytes = %d\n",
++ TaskTable->count,
++ TaskTable->size
++ );
++
++ /* Allocate task buffer. */
++ gcmkERR_BREAK(_AllocateTaskContainer(
++ Command,
++ TaskTable->size,
++ &container
++ ));
++
++ /* Determine the task data pointer. */
++ kernelTask = (gctUINT8_PTR) (container + 1);
++
++ /* Initialize the reference count. */
++ container->referenceCount = TaskTable->count;
++
++ /* Process tasks. */
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " processing tasks for block %d\n",
++ block
++ );
++
++ /* Get the current kernel table entry. */
++ kernelTaskEntry = &Command->taskTable[block];
++
++ /* Are there tasks for the current block scheduled? */
++ if (kernelTaskEntry->container == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " first task container for the block added\n",
++ block
++ );
++
++ /* Nothing yet, set the container buffer pointer. */
++ kernelTaskEntry->container = container;
++ kernelTaskEntry->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Yes, append to the end. */
++ else
++ {
++ kernelTaskEntry->link->cotainer = container;
++ kernelTaskEntry->link->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Set initial task. */
++ userTask = userTaskEntry->head;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " copying user tasks over to the kernel\n"
++ );
++
++ /* Copy tasks. */
++ do
++ {
++ gcsTASK_HEADER_PTR taskHeader;
++
++ taskHeader = (gcsTASK_HEADER_PTR) (userTask + 1);
++
++ gcmkVERIFY_OK(_RemoveRecordFromProcesDB(Command, taskHeader));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " task ID = %d, size = %d\n",
++ ((gcsTASK_HEADER_PTR) (userTask + 1))->id,
++ userTask->size
++ );
++
++ /* Copy the task data. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ kernelTask, taskHeader, userTask->size
++ ));
++
++ /* Advance to the next task. */
++ kernelTask += userTask->size;
++ userTask = userTask->next;
++ }
++ while (userTask != gcvNULL);
++
++ /* Update link pointer in the header. */
++ kernelTaskEntry->link = (gcsTASK_LINK_PTR) kernelTask;
++
++ /* Initialize link task. */
++ kernelTaskEntry->link->id = gcvTASK_LINK;
++ kernelTaskEntry->link->cotainer = gcvNULL;
++ kernelTaskEntry->link->task = gcvNULL;
++
++ /* Advance the task data pointer. */
++ kernelTask += gcmSIZEOF(gcsTASK_LINK);
++ }
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->taskMutex
++ ));
++
++ /* Assign interrupts to the blocks. */
++ eventCommand = PreviousEnd;
++
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ /* Get the interrupt number. */
++ interrupt = _GetNextInterrupt(Command, block);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): block = %d interrupt = %d\n",
++ __FUNCTION__, __LINE__,
++ block, interrupt
++ );
++
++ /* Determine the command position. */
++ eventCommand -= Command->info.eventCommandSize;
++
++ /* Append an EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, eventCommand, block, interrupt, gcvNULL
++ ));
++ }
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************** Memory Management *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_HardwareToKernel(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM memory;
++ gctUINT32 offset;
++ gctUINT32 nodePhysical;
++ gctPOINTER *logical;
++ gctSIZE_T bytes;
++ status = gcvSTATUS_OK;
++
++ memory = Node->VidMem.memory;
++
++ if (memory->object.type == gcvOBJ_VIDMEM)
++ {
++ nodePhysical = memory->baseAddress
++ + (gctUINT32)Node->VidMem.offset
++ + Node->VidMem.alignment;
++ bytes = Node->VidMem.bytes;
++ logical = &Node->VidMem.kernelVirtual;
++ }
++ else
++ {
++ nodePhysical = Node->Virtual.physicalAddress;
++ bytes = Node->Virtual.bytes;
++ logical = &Node->Virtual.kernelVirtual;
++ }
++
++ if (*logical == gcvNULL)
++ {
++ status = gckOS_MapPhysical(Os, nodePhysical, bytes, logical);
++
++ if (gcmkIS_ERROR(status))
++ {
++ return status;
++ }
++ }
++
++ offset = Address - nodePhysical;
++ *KernelPointer = (gctPOINTER)((gctUINT8_PTR)(*logical) + offset);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_ConvertUserCommandBufferPointer(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR UserCommandBuffer,
++ OUT gcsCMDBUFFER_PTR * KernelCommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcsCMDBUFFER_PTR mappedUserCommandBuffer = gcvNULL;
++ gckKERNEL kernel = Command->kernel->kernel;
++ gctUINT32 pid;
++ gckVIDMEM_NODE node;
++
++ gckOS_GetProcessID(&pid);
++
++ do
++ {
++ gctUINT32 headerAddress;
++
++ /* Map the command buffer structure into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ (gctPOINTER *) &mappedUserCommandBuffer
++ ));
++
++ /* Determine the address of the header. */
++ headerAddress
++ = mappedUserCommandBuffer->address
++ - mappedUserCommandBuffer->bufferOffset;
++
++ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(
++ kernel,
++ pid,
++ gcmPTR2INT32(mappedUserCommandBuffer->node),
++ &node));
++
++ /* Translate the logical address to the kernel space. */
++ gcmkERR_BREAK(_HardwareToKernel(
++ Command->os,
++ node->node,
++ headerAddress,
++ (gctPOINTER *) KernelCommandBuffer
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Unmap the user command buffer. */
++ if (mappedUserCommandBuffer != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_UnmapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ mappedUserCommandBuffer
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_AllocateLinear(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gcuVIDMEM_NODE_PTR * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status, last;
++ gctPOINTER logical;
++ gctPHYS_ADDR physical;
++ gctUINT32 address;
++ gctSIZE_T size = Size;
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Command->os,
++ gcvFALSE,
++ &size,
++ &physical,
++ &logical
++ ));
++
++ gcmkERR_BREAK(gckOS_GetPhysicalAddress(Command->os, logical, &address));
++
++ /* Set return values. */
++ * Node = physical;
++ * Address = address;
++ * Logical = logical;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (physical != gcvNULL)
++ {
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(gckOS_FreeContiguous(Command->os, physical, logical, size));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeLinear(
++ IN gckVGKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_FreeContiguous(Kernel->os, Node, Logical, 1));
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++_AllocateCommandBuffer(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gcsCMDBUFFER_PTR commandBuffer = gcvNULL;
++
++ do
++ {
++ gctUINT alignedHeaderSize;
++ gctUINT requestedSize;
++ gctUINT allocationSize;
++ gctUINT32 address = 0;
++ gctUINT8_PTR endCommand;
++
++ /* Determine the aligned header size. */
++ alignedHeaderSize
++ = (gctUINT32)gcmALIGN(gcmSIZEOF(gcsCMDBUFFER), Command->info.addressAlignment);
++
++ /* Align the requested size. */
++ requestedSize
++ = (gctUINT32)gcmALIGN(Size, Command->info.commandAlignment);
++
++ /* Determine the size of the buffer to allocate. */
++ allocationSize
++ = alignedHeaderSize
++ + requestedSize
++ + (gctUINT32)Command->info.staticTailSize;
++
++ /* Allocate the command buffer. */
++ gcmkERR_BREAK(_AllocateLinear(
++ Command,
++ allocationSize,
++ Command->info.addressAlignment,
++ &node,
++ &address,
++ (gctPOINTER *) &commandBuffer
++ ));
++
++ /* Initialize the structure. */
++ commandBuffer->completion = gcvVACANT_BUFFER;
++ commandBuffer->node = node;
++ commandBuffer->address = address + alignedHeaderSize;
++ commandBuffer->bufferOffset = alignedHeaderSize;
++ commandBuffer->size = requestedSize;
++ commandBuffer->offset = requestedSize;
++ commandBuffer->nextAllocated = gcvNULL;
++ commandBuffer->nextSubBuffer = gcvNULL;
++
++ /* Determine the data count. */
++ commandBuffer->dataCount
++ = (requestedSize + Command->info.staticTailSize)
++ / Command->info.commandAlignment;
++
++ /* Determine the location of the END command. */
++ endCommand
++ = (gctUINT8_PTR) commandBuffer
++ + alignedHeaderSize
++ + requestedSize;
++
++ /* Append an END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ endCommand,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++
++ /* Set the return pointer. */
++ * CommandBuffer = commandBuffer;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(_FreeLinear(Command->kernel, node, commandBuffer));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ /* Free the buffer. */
++ status = _FreeLinear(Kernel, CommandBuffer->node, CommandBuffer);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++****************************** TS Overflow Handler *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_TSOverflow(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** TS OVERFLOW ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++
++/******************************************************************************\
++****************************** Bus Error Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_BusError(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** BUS ERROR ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++****************************** Power Stall Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_PowerStall(
++ IN gckVGKERNEL Kernel
++ )
++{
++ /* Signal. */
++ return gckOS_Signal(
++ Kernel->os,
++ Kernel->command->powerStallSignal,
++ gcvTRUE);
++}
++
++/******************************************************************************\
++******************************** Task Routines *********************************
++\******************************************************************************/
++
++typedef gceSTATUS (* gctTASKROUTINE) (
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gctTASKROUTINE _taskRoutine[] =
++{
++ _TaskLink, /* gcvTASK_LINK */
++ _TaskCluster, /* gcvTASK_CLUSTER */
++ _TaskIncrement, /* gcvTASK_INCREMENT */
++ _TaskDecrement, /* gcvTASK_DECREMENT */
++ _TaskSignal, /* gcvTASK_SIGNAL */
++ _TaskLockdown, /* gcvTASK_LOCKDOWN */
++ _TaskUnlockVideoMemory, /* gcvTASK_UNLOCK_VIDEO_MEMORY */
++ _TaskFreeVideoMemory, /* gcvTASK_FREE_VIDEO_MEMORY */
++ _TaskFreeContiguousMemory, /* gcvTASK_FREE_CONTIGUOUS_MEMORY */
++ _TaskUnmapUserMemory, /* gcvTASK_UNMAP_USER_MEMORY */
++};
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ /* Cast the task pointer. */
++ gcsTASK_LINK_PTR task = (gcsTASK_LINK_PTR) TaskHeader->task;
++
++ /* Save the pointer to the container. */
++ gcsTASK_CONTAINER_PTR container = TaskHeader->container;
++
++ /* No more tasks in the list? */
++ if (task->task == gcvNULL)
++ {
++ /* Reset the entry. */
++ TaskHeader->container = gcvNULL;
++ TaskHeader->task = gcvNULL;
++ TaskHeader->link = gcvNULL;
++ }
++ else
++ {
++ /* Update the entry. */
++ TaskHeader->container = task->cotainer;
++ TaskHeader->task = task->task;
++ }
++
++ /* Decrement the task buffer reference. */
++ gcmkASSERT(container->referenceCount >= 0);
++ if (container->referenceCount == 0)
++ {
++ /* Free the container. */
++ _FreeTaskContainer(Command, container);
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ /* Cast the task pointer. */
++ gcsTASK_CLUSTER_PTR cluster = (gcsTASK_CLUSTER_PTR) TaskHeader->task;
++
++ /* Get the number of tasks. */
++ gctUINT taskCount = cluster->taskCount;
++
++ /* Advance to the next task. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (cluster + 1);
++
++ /* Perform all tasks in the cluster. */
++ while (taskCount)
++ {
++ /* Perform the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ Command,
++ TaskHeader
++ ));
++
++ /* Update the task count. */
++ taskCount -= 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_INCREMENT_PTR task = (gcsTASK_INCREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Increment data. */
++ (* logical) += 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_DECREMENT_PTR task = (gcsTASK_DECREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Decrement data. */
++ (* logical) -= 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_SIGNAL_PTR task = (gcsTASK_SIGNAL_PTR) TaskHeader->task;
++
++
++ /* Map the signal into kernel space. */
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, task->signal, task->process
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR userCounter = gcvNULL;
++ gctUINT32_PTR kernelCounter = gcvNULL;
++ gctSIGNAL signal = gcvNULL;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_LOCKDOWN_PTR task = (gcsTASK_LOCKDOWN_PTR) TaskHeader->task;
++
++ /* Convert physical addresses into logical. */
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->userCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &userCounter
++ ));
++
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->kernelCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &kernelCounter
++ ));
++
++ /* Update the kernel counter. */
++ (* kernelCounter) += 1;
++
++ /* Are the counters equal? */
++ if ((* userCounter) == (* kernelCounter))
++ {
++ /* Map the signal into kernel space. */
++ gcmkERR_BREAK(gckOS_MapSignal(
++ Command->os, task->signal, task->process, &signal
++ ));
++
++ if (signal == gcvNULL)
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, task->signal, gcvTRUE
++ ));
++ }
++ else
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, signal, gcvTRUE
++ ));
++ }
++ }
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Destroy the mapped signal. */
++ if (signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, signal
++ ));
++ }
++
++ /* Unmap the physical memory. */
++ if (kernelCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ kernelCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ if (userCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ userCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR task
++ = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Unlock video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Unlock(
++ Command->kernel->kernel,
++ (gckVIDMEM_NODE)gcmUINT64_TO_PTR(task->node),
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++
++ gcmkERR_BREAK(gckVIDMEM_NODE_Dereference(
++ Command->kernel->kernel,
++ gcmUINT64_TO_PTR(task->node)));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_VIDEO_MEMORY_PTR task
++ = (gcsTASK_FREE_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Free video memory. */
++ gcmkERR_BREAK(gckVIDMEM_NODE_Dereference(
++ Command->kernel->kernel,
++ gcmINT2PTR(task->node)));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR task
++ = (gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR) TaskHeader->task;
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Command->os, task->physical, task->logical, task->bytes
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++ gctPOINTER info;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNMAP_USER_MEMORY_PTR task
++ = (gcsTASK_UNMAP_USER_MEMORY_PTR) TaskHeader->task;
++
++ info = gckKERNEL_QueryPointerFromName(
++ Command->kernel->kernel, gcmALL_TO_UINT32(task->info));
++
++ /* Unmap the user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Command->os, gcvCORE_VG, task->memory, task->size, info, task->address
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++************ Hardware Block Interrupt Handlers For Scheduled Events ************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_Block(
++ IN gckVGKERNEL Kernel,
++ IN gcsBLOCK_TASK_ENTRY_PTR TaskHeader,
++ IN gctBOOL ProcessAll
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskHeader=0x%x ProcessAll=0x%x", Kernel, TaskHeader, ProcessAll);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (TaskHeader->task == gcvNULL)
++ {
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++
++ do
++ {
++ gckVGCOMMAND command;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Increment the interrupt usage semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, TaskHeader->interruptSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->taskMutex,
++ gcvINFINITE
++ ));
++
++ /* Verify inputs. */
++ gcmkASSERT(TaskHeader != gcvNULL);
++ gcmkASSERT(TaskHeader->container != gcvNULL);
++ gcmkASSERT(TaskHeader->task != gcvNULL);
++ gcmkASSERT(TaskHeader->link != gcvNULL);
++
++ /* Process tasks. */
++ do
++ {
++ /* Process the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Is the next task is LINK? */
++ if (TaskHeader->task->id == gcvTASK_LINK)
++ {
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Done. */
++ break;
++ }
++ }
++ while (ProcessAll);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->taskMutex
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gcmDECLARE_INTERRUPT_HANDLER(COMMAND, 0)
++{
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x ", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++
++ do
++ {
++ gckVGCOMMAND command;
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT entryCount;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Get the current queue. */
++ queueTail = command->queueTail;
++
++ /* Get the current queue entry. */
++ entry = queueTail->currentEntry;
++
++ /* Get the number of entries in the queue. */
++ entryCount = queueTail->pending;
++
++ /* Process all entries. */
++ while (gcvTRUE)
++ {
++ /* Call post-execution function. */
++ status = entry->handler(Kernel, entry);
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: post action failed.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Executed the next buffer? */
++ if (status == gcvSTATUS_EXECUTED)
++ {
++ /* Update the queue. */
++ queueTail->pending = entryCount;
++ queueTail->currentEntry = entry;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++
++ /* Break out of the loop. */
++ break;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ entryCount -= 1;
++
++ /* Last entry? */
++ if (entryCount == 0)
++ {
++ /* Reset the queue to idle. */
++ queueTail->pending = 0;
++
++ /* Get a shortcut to the queue to merge with. */
++ mergeQueue = command->mergeQueue;
++
++ /* Merge the queues if necessary. */
++ if (mergeQueue != queueTail)
++ {
++ gcmkASSERT(mergeQueue < queueTail);
++ gcmkASSERT(mergeQueue->next == queueTail);
++
++ mergeQueue->size
++ += gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + queueTail->size;
++
++ mergeQueue->next = queueTail->next;
++ }
++
++ /* Advance to the next queue. */
++ queueTail = queueTail->next;
++
++ /* Did it wrap around? */
++ if (command->queue == queueTail)
++ {
++ /* Reset merge queue. */
++ command->mergeQueue = queueTail;
++ }
++
++ /* Set new queue. */
++ command->queueTail = queueTail;
++
++ /* Is the next queue scheduled? */
++ if (queueTail->pending > 0)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ status = gckVGHARDWARE_Execute(
++ command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: failed to start the next queue.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ }
++ else
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(
++ Kernel->command->hardware, gcvPOWER_IDLE_BROADCAST
++ );
++ }
++
++ /* Break out of the loop. */
++ break;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->queueMutex
++ ));
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/* Define standard block interrupt handlers. */
++gcmDEFINE_INTERRUPT_HANDLER(TESSELLATOR, 0)
++gcmDEFINE_INTERRUPT_HANDLER(VG, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 1)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 2)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 3)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 4)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 5)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 6)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 7)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 8)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 9)
++
++/* The entries in the array are arranged by event priority. */
++static gcsBLOCK_INTERRUPT_HANDLER _blockHandlers[] =
++{
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(TESSELLATOR, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(VG, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 1),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 2),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 3),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 4),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 5),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 6),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 7),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 8),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 9),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(COMMAND, 0),
++};
++
++
++/******************************************************************************\
++************************* Static Command Buffer Handlers ***********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Cast the command buffer header. */
++ commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++************************* Dynamic Command Buffer Handlers **********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++********************************* Other Handlers *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_FreeKernelCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ /* Free the command buffer. */
++ status = _FreeCommandBuffer(Kernel, Entry->commandBuffer);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************* Queue Management *******************************
++\******************************************************************************/
++
++#if gcvDUMP_COMMAND_BUFFER
++static void
++_DumpCommandQueue(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR QueueHeader,
++ IN gctUINT EntryCount
++ )
++{
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT queueIndex;
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ static gctUINT arrayCount = 0;
++#endif
++
++ /* Is dumpinng enabled? */
++ if (!Commad->enableDumping)
++ {
++ return;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "COMMAND QUEUE DUMP: %d entries\n", EntryCount
++ );
++#endif
++
++ /* Get the pointer to the first entry. */
++ entry = QueueHeader->currentEntry;
++
++ /* Iterate through the queue. */
++ for (queueIndex = 0; queueIndex < EntryCount; queueIndex += 1)
++ {
++ gcsCMDBUFFER_PTR buffer;
++ gctUINT bufferCount;
++ gctUINT bufferIndex;
++ gctUINT i, count;
++ gctUINT size;
++ gctUINT32_PTR data;
++
++#if gcvDUMP_COMMAND_LINES
++ gctUINT lineNumber;
++#endif
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "ENTRY %d\n", queueIndex
++ );
++#endif
++
++ /* Reset the count. */
++ bufferCount = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Update the count. */
++ bufferCount += 1;
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ if (bufferCount > 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER SET: %d buffers.\n",
++ bufferCount
++ );
++ }
++#endif
++
++ /* Reset the buffer index. */
++ bufferIndex = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Determine the size of the buffer. */
++ size = buffer->dataCount * Command->info.commandAlignment;
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ /* A single buffer? */
++ if (bufferCount == 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER: count=%d (0x%X), size=%d bytes @ %08X.\n",
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER %d: count=%d (0x%X), size=%d bytes @ %08X\n",
++ bufferIndex,
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++#endif
++
++ /* Determine the number of double words to print. */
++ count = size / 4;
++
++ /* Determine the buffer location. */
++ data = (gctUINT32_PTR)
++ (
++ (gctUINT8_PTR) buffer + buffer->bufferOffset
++ );
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "unsigned int _" gcvCOMMAND_BUFFER_NAME "_%d[] =\n",
++ arrayCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "{\n"
++ );
++
++ arrayCount += 1;
++#endif
++
++#if gcvDUMP_COMMAND_LINES
++ /* Reset the line number. */
++ lineNumber = 0;
++#endif
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ count -= 2;
++#endif
++
++ for (i = 0; i < count; i += 1)
++ {
++ if ((i % 8) == 0)
++ {
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\t");
++#else
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " ");
++#endif
++ }
++
++#if gcvDUMP_COMMAND_LINES
++ if (lineNumber == gcvDUMP_COMMAND_LINES)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " . . . . . . . . .\n");
++ break;
++ }
++#endif
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "0x%08X", data[i]);
++
++ if (i + 1 == count)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ if (((i + 1) % 8) == 0)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ",\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ", ");
++ }
++ }
++ }
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "};\n\n"
++ );
++#endif
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ bufferIndex += 1;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ }
++}
++#endif
++
++static gceSTATUS
++_LockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ OUT gcsKERNEL_CMDQUEUE_PTR * Entries,
++ OUT gctUINT_PTR EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* Get a shortcut to the head of the queue. */
++ queueHead = Command->queueHead;
++
++ /* Is the head buffer still being worked on? */
++ if (queueHead->pending)
++ {
++ /* Increment overflow count. */
++ Command->queueOverflow += 1;
++
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, queueHead));
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Determine the first queue entry. */
++ queueHead->currentEntry = (gcsKERNEL_CMDQUEUE_PTR)
++ (
++ (gctUINT8_PTR) queueHead + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ );
++
++ /* Set the pointer to the first entry. */
++ * Entries = queueHead->currentEntry;
++
++ /* Determine the number of available entries. */
++ * EntryCount = queueHead->size / gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UnlockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ IN gctUINT EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++#if !gcdENABLE_INFINITE_SPEED_HW
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++ gcsKERNEL_QUEUE_HEADER_PTR queueNext;
++ gctUINT queueSize;
++ gctUINT newSize;
++ gctUINT unusedSize;
++
++ /* Get shortcut to the head and to the tail of the queue. */
++ queueTail = Command->queueTail;
++ queueHead = Command->queueHead;
++
++ /* Dump the command buffer. */
++#if gcvDUMP_COMMAND_BUFFER
++ _DumpCommandQueue(Command, queueHead, EntryCount);
++#endif
++
++ /* Get a shortcut to the current queue size. */
++ queueSize = queueHead->size;
++
++ /* Determine the new queue size. */
++ newSize = EntryCount * gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++ gcmkASSERT(newSize <= queueSize);
++
++ /* Determine the size of the unused area. */
++ unusedSize = queueSize - newSize;
++
++ /* Is the unused area big enough to become a buffer? */
++ if (unusedSize >= gcvMINUMUM_BUFFER)
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR nextHead;
++
++ /* Place the new header. */
++ nextHead = (gcsKERNEL_QUEUE_HEADER_PTR)
++ (
++ (gctUINT8_PTR) queueHead
++ + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + newSize
++ );
++
++ /* Initialize the buffer. */
++ nextHead->size = unusedSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ nextHead->pending = 0;
++
++ /* Link the buffer in. */
++ nextHead->next = queueHead->next;
++ queueHead->next = nextHead;
++ queueNext = nextHead;
++
++ /* Update the size of the current buffer. */
++ queueHead->size = newSize;
++ }
++
++ /* Not big enough. */
++ else
++ {
++ /* Determine the next queue. */
++ queueNext = queueHead->next;
++ }
++
++ /* Mark the buffer as busy. */
++ queueHead->pending = EntryCount;
++
++ /* Advance to the next buffer. */
++ Command->queueHead = queueNext;
++
++ /* Start the command processor if the queue was empty. */
++ if (queueTail == queueHead)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++ }
++
++ /* The queue was not empty. */
++ else
++ {
++ /* Advance the merge buffer if needed. */
++ if (queueHead == Command->mergeQueue)
++ {
++ Command->mergeQueue = queueNext;
++ }
++ }
++#endif
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API Code *****************************
++\******************************************************************************/
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ )
++{
++ gceSTATUS status, last;
++ gckVGCOMMAND command = gcvNULL;
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++ gctUINT i, j;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskGranularity=0x%x QueueSize=0x%x Command=0x%x",
++ Kernel, TaskGranularity, QueueSize, Command);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(QueueSize >= gcvMINUMUM_BUFFER);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ do
++ {
++ /***********************************************************************
++ ** Generic object initialization.
++ */
++
++ /* Allocate the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGCOMMAND),
++ (gctPOINTER *) &command
++ ));
++
++ /* Initialize the object. */
++ command->object.type = gcvOBJ_COMMAND;
++
++ /* Set the object pointers. */
++ command->kernel = Kernel;
++ command->os = Kernel->os;
++ command->hardware = Kernel->hardware;
++
++ /* Reset pointers. */
++ command->queue = gcvNULL;
++ command->queueMutex = gcvNULL;
++ command->taskMutex = gcvNULL;
++ command->commitMutex = gcvNULL;
++
++ command->powerStallBuffer = gcvNULL;
++ command->powerStallSignal = gcvNULL;
++ command->powerSemaphore = gcvNULL;
++
++ /* Reset context states. */
++ command->contextCounter = 0;
++ command->currentContext = 0;
++
++ /* Enable command buffer dumping. */
++ command->enableDumping = gcvTRUE;
++
++ /* Set features. */
++ command->fe20 = Kernel->hardware->fe20;
++ command->vg20 = Kernel->hardware->vg20;
++ command->vg21 = Kernel->hardware->vg21;
++
++ /* Reset task table .*/
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ command->taskTable, gcmSIZEOF(command->taskTable)
++ ));
++
++ /* Query command buffer attributes. */
++ gcmkERR_BREAK(gckVGCOMMAND_InitializeInfo(command));
++
++ /* Create the control mutexes. */
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->queueMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->taskMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->commitMutex));
++
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphore(Kernel->os,
++ &command->powerSemaphore));
++
++ gcmkERR_BREAK(gckOS_CreateSignal(Kernel->os,
++ gcvFALSE, &command->powerStallSignal));
++
++ /***********************************************************************
++ ** Command queue initialization.
++ */
++
++ /* Allocate the command queue. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ QueueSize,
++ (gctPOINTER *) &command->queue
++ ));
++
++ /* Initialize the command queue. */
++ queue = command->queue;
++
++ queue->size = QueueSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ queue->pending = 0;
++ queue->next = queue;
++
++ command->queueHead =
++ command->queueTail =
++ command->mergeQueue = command->queue;
++
++ command->queueOverflow = 0;
++
++
++ /***********************************************************************
++ ** Enable TS overflow interrupt.
++ */
++
++ command->info.tsOverflowInt = 0;
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->info.tsOverflowInt,
++ _EventHandler_TSOverflow
++ ));
++
++ /* Mask out the interrupt. */
++ Kernel->hardware->eventMask &= ~(1 << command->info.tsOverflowInt);
++
++
++ /***********************************************************************
++ ** Enable Bus Error interrupt.
++ */
++
++ /* Hardwired to bit 31. */
++ command->busErrorInt = 31;
++
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->busErrorInt,
++ _EventHandler_BusError
++ ));
++
++
++ command->powerStallInt = 30;
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->powerStallInt,
++ _EventHandler_PowerStall
++ ));
++
++ /***********************************************************************
++ ** Task management initialization.
++ */
++
++ command->taskStorage = gcvNULL;
++ command->taskStorageGranularity = TaskGranularity;
++ command->taskStorageUsable = TaskGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++
++ command->taskFreeHead = gcvNULL;
++ command->taskFreeTail = gcvNULL;
++
++ /* Enable block handlers. */
++ for (i = 0; i < gcmCOUNTOF(_blockHandlers); i += 1)
++ {
++ /* Get the target hardware block. */
++ gceBLOCK block = _blockHandlers[i].block;
++
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[block];
++
++ /* Determine the interrupt value index. */
++ gctUINT index = entry->interruptCount;
++
++ /* Create the block semaphore. */
++ if (entry->interruptSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ command->os, &entry->interruptSemaphore
++ ));
++ }
++
++ /* Enable auto-detection. */
++ entry->interruptArray[index] = -1;
++
++ /* Enable interrupt for the block. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &entry->interruptArray[index],
++ _blockHandlers[i].handler
++ ));
++
++ /* Update the number of registered interrupts. */
++ entry->interruptCount += 1;
++
++ /* Inrement the semaphore to allow the usage of the registered
++ interrupt. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Get the FE interrupt. */
++ command->info.feBufferInt
++ = command->taskTable[gcvBLOCK_COMMAND].interruptArray[0];
++
++ /* Return gckVGCOMMAND object pointer. */
++ *Command = command;
++
++ gcmkFOOTER_ARG("*Command=0x%x",*Command);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the task table entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[i];
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ for (j = 0; j < entry->interruptCount; j += 1)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[j] >= 0);
++ gcmkASSERT(entry->interruptArray[j] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ entry->interruptArray[j]
++ ));
++ }
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (command->info.tsOverflowInt != -1)
++ {
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->info.tsOverflowInt
++ ));
++ }
++
++ /* Delete the commit mutex. */
++ if (command->commitMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->commitMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->taskMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->taskMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->queueMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->queueMutex
++ ));
++ }
++
++ /* Delete the command queue. */
++ if (command->queue != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command->queue
++ ));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(
++ Kernel->os, command->powerSemaphore));
++ }
++
++ if (command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Kernel->os,
++ command->powerStallSignal));
++ }
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command
++ ));
++ }
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ OUT gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ gctUINT i;
++ gcsTASK_STORAGE_PTR nextStorage;
++
++ if (Command->queueHead != gcvNULL)
++ {
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, Command->queueHead));
++ }
++
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &Command->taskTable[i];
++
++ /* Determine the index of the last interrupt in the array. */
++ gctINT index = entry->interruptCount - 1;
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ while (index >= 0)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[index] >= 0);
++ gcmkASSERT(entry->interruptArray[index] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ entry->interruptArray[index]
++ ));
++
++ /* Update to the next interrupt. */
++ index -= 1;
++ entry->interruptCount -= 1;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (Command->info.tsOverflowInt != -1)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->info.tsOverflowInt
++ ));
++
++ Command->info.tsOverflowInt = -1;
++ }
++
++ /* Delete the commit mutex. */
++ if (Command->commitMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->commitMutex
++ ));
++
++ Command->commitMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->taskMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->taskMutex
++ ));
++
++ Command->taskMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->queueMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->queueMutex
++ ));
++
++ Command->queueMutex = gcvNULL;
++ }
++
++ if (Command->powerSemaphore != gcvNULL)
++ {
++ /* Destroy the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++
++ if (Command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySignal(
++ Command->os,
++ Command->powerStallSignal));
++ }
++
++ if (Command->queue != gcvNULL)
++ {
++ /* Delete the command queue. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->queue
++ ));
++ }
++
++ /* Destroy all allocated buffers. */
++ while (Command->taskStorage)
++ {
++ /* Copy the buffer pointer. */
++ nextStorage = Command->taskStorage->next;
++
++ /* Free the current container. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->taskStorage
++ ));
++
++ /* Advance to the next one. */
++ Command->taskStorage = nextStorage;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Mark the object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Free(Command->os, Command));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Restore the object type if failed. */
++ Command->object.type = gcvOBJ_COMMAND;
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Information=0x%x", Command, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Information != gcvNULL);
++
++ /* Copy the information. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ Information, &Command->info, sizeof(gcsCOMMAND_BUFFER_INFO)
++ ));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x CommandBuffer=0x%x Data=0x%x",
++ Command, Size, CommandBuffer, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ do
++ {
++ /* Allocate the buffer. */
++ gcmkERR_BREAK(_AllocateCommandBuffer(Command, Size, CommandBuffer));
++
++ /* Determine the data pointer. */
++ * Data = (gctUINT8_PTR) (*CommandBuffer) + (* CommandBuffer)->bufferOffset;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ /* Free command buffer. */
++ status = _FreeCommandBuffer(Command->kernel, CommandBuffer);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ do
++ {
++ gctUINT queueLength;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Set the buffer. */
++ kernelEntry->commandBuffer = CommandBuffer;
++ kernelEntry->handler = _FreeKernelCommandBuffer;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, 1
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ )
++{
++ /*
++ The first buffer is executed through a direct gckVGHARDWARE_Execute call,
++ therefore only an update is needed after the execution is over. All
++ consequent buffers need to be executed upon the first update call from
++ the FE interrupt handler.
++ */
++
++ static gcsQUEUE_UPDATE_CONTROL _dynamicBuffer[] =
++ {
++ {
++ _UpdateDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ },
++ {
++ _ExecuteDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _ExecuteLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ }
++ };
++
++ static gcsQUEUE_UPDATE_CONTROL _staticBuffer[] =
++ {
++ {
++ _UpdateStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ },
++ {
++ _ExecuteStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _ExecuteLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ }
++ };
++
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x Queue=0x%x EntryCount=0x%x TaskTable=0x%x",
++ Command, Context, Queue, EntryCount, TaskTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++ gcmkVERIFY_ARGUMENT(EntryCount > 1);
++
++ do
++ {
++ gctBOOL haveFETasks;
++ gctUINT queueSize;
++ gcsVGCMDQUEUE_PTR mappedQueue;
++ gcsVGCMDQUEUE_PTR userEntry;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++ gcsQUEUE_UPDATE_CONTROL_PTR queueControl;
++ gctUINT currentLength;
++ gctUINT queueLength;
++ gctUINT entriesQueued;
++ gctUINT8_PTR previousEnd;
++ gctBOOL previousDynamic;
++ gctBOOL previousExecuted;
++ gctUINT controlIndex;
++
++ gcmkERR_BREAK(gckVGHARDWARE_SetPowerManagementState(
++ Command->hardware, gcvPOWER_ON_AUTO
++ ));
++
++ /* Acquire the power semaphore. */
++ gcmkERR_BREAK(gckOS_AcquireSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ status = gckOS_AcquireMutex(
++ Command->os,
++ Command->commitMutex,
++ gcvINFINITE
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ break;
++ }
++
++ do
++ {
++ gcmkERR_BREAK(_FlushMMU(Command));
++
++ /* Assign a context ID if not yet assigned. */
++ if (Context->id == 0)
++ {
++ /* Assign the next context number. */
++ Context->id = ++ Command->contextCounter;
++
++ /* See if we overflowed. */
++ if (Command->contextCounter == 0)
++ {
++ /* We actually did overflow, wow... */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++ }
++
++ /* The first entry in the queue is always the context buffer.
++ Verify whether the user context is the same as the current
++ context and if that's the case, skip the first entry. */
++ if (Context->id == Command->currentContext)
++ {
++ /* Same context as before, skip the first entry. */
++ EntryCount -= 1;
++ Queue += 1;
++
++ /* Set the signal to avoid user waiting. */
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, Context->signal, Context->process
++ ));
++ }
++ else
++ {
++ /* Different user context - keep the first entry.
++ Set the user context as the current one. */
++ Command->currentContext = Context->id;
++ }
++
++ /* Reset pointers. */
++ queueControl = gcvNULL;
++ previousEnd = gcvNULL;
++
++ /* Determine whether there are FE tasks to be performed. */
++ haveFETasks = (TaskTable->table[gcvBLOCK_COMMAND].head != gcvNULL);
++
++ /* Determine the size of the queue. */
++ queueSize = EntryCount * gcmSIZEOF(gcsVGCMDQUEUE);
++
++ /* Map the command queue into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ (gctPOINTER *) &mappedQueue
++ ));
++
++ /* Set the first entry. */
++ userEntry = mappedQueue;
++
++ /* Process the command queue. */
++ while (EntryCount)
++ {
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Determine the number of entries to process. */
++ currentLength = (queueLength < EntryCount)
++ ? queueLength
++ : EntryCount;
++
++ /* Update the number of the entries left to process. */
++ EntryCount -= currentLength;
++
++ /* Reset previous flags. */
++ previousDynamic = gcvFALSE;
++ previousExecuted = gcvFALSE;
++
++ /* Set the initial control index. */
++ controlIndex = 0;
++
++ /* Process entries. */
++ for (entriesQueued = 0; entriesQueued < currentLength; entriesQueued += 1)
++ {
++ /* Get the kernel pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = gcvNULL;
++ gcmkERR_BREAK(_ConvertUserCommandBufferPointer(
++ Command,
++ userEntry->commandBuffer,
++ &commandBuffer
++ ));
++
++ /* Is it a dynamic command buffer? */
++ if (userEntry->dynamic)
++ {
++ /* Select dynamic buffer control functions. */
++ queueControl = &_dynamicBuffer[controlIndex];
++ }
++
++ /* No, a static command buffer. */
++ else
++ {
++ /* Select static buffer control functions. */
++ queueControl = &_staticBuffer[controlIndex];
++ }
++
++ /* Set the command buffer pointer to the entry. */
++ kernelEntry->commandBuffer = commandBuffer;
++
++ /* If the previous entry was a dynamic command buffer,
++ link it to the current. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command,
++ previousEnd,
++ commandBuffer->address,
++ commandBuffer->dataCount,
++ gcvNULL
++ ));
++
++ /* The buffer will be auto-executed, only need to
++ update it after it has been executed. */
++ kernelEntry->handler = queueControl->update;
++
++ /* The buffer is only being updated. */
++ previousExecuted = gcvFALSE;
++ }
++ else
++ {
++ /* Set the buffer up for execution. */
++ kernelEntry->handler = queueControl->execute;
++
++ /* The buffer is being updated. */
++ previousExecuted = gcvTRUE;
++ }
++
++ /* The current buffer's END command becomes the last END. */
++ previousEnd
++ = ((gctUINT8_PTR) commandBuffer)
++ + commandBuffer->bufferOffset
++ + commandBuffer->dataCount * Command->info.commandAlignment
++ - Command->info.staticTailSize;
++
++ /* Update the last entry info. */
++ previousDynamic = userEntry->dynamic;
++
++ /* Advance entries. */
++ userEntry += 1;
++ kernelEntry += 1;
++
++ /* Update the control index. */
++ controlIndex = 1;
++ }
++
++ /* If the previous entry was a dynamic command buffer,
++ terminate it with an END. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ previousEnd,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++ }
++
++ /* Last buffer? */
++ if (EntryCount == 0)
++ {
++ /* Modify the last command buffer's routines to handle
++ tasks if any.*/
++ if (haveFETasks)
++ {
++ if (previousExecuted)
++ {
++ kernelEntry[-1].handler = queueControl->lastExecute;
++ }
++ else
++ {
++ kernelEntry[-1].handler = queueControl->lastUpdate;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++ /* Schedule tasks. */
++ gcmkERR_BREAK(_ScheduleTasks(Command, TaskTable, previousEnd));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++ }
++
++ /* Unkock and schedule the current queue for execution. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, currentLength
++ ));
++ }
++
++
++ /* Unmap the user command buffer. */
++ gcmkERR_BREAK(gckOS_UnmapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ mappedQueue
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ Command->os,
++ Command->commitMutex
++ ));
++
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_db.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_db.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_db.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_db.c 2016-06-19 22:11:55.137151030 +0200
+@@ -0,0 +1,1758 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_DATABASE
++
++/*******************************************************************************
++***** Private fuctions ********************************************************/
++
++#define _GetSlot(database, x) \
++ (gctUINT32)(gcmPTR_TO_UINT64(x) % gcmCOUNTOF(database->list))
++
++/*******************************************************************************
++** gckKERNEL_NewDatabase
++**
++** Create a new database structure and insert it to the head of the hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++static gceSTATUS
++gckKERNEL_NewDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctBOOL acquired = gcvFALSE;
++ gctSIZE_T slot;
++ gcsDATABASE_PTR existingDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Walk the hash list. */
++ for (existingDatabase = Kernel->db->db[slot];
++ existingDatabase != gcvNULL;
++ existingDatabase = existingDatabase->next)
++ {
++ if (existingDatabase->processID == ProcessID)
++ {
++ /* One process can't be added twice. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++ }
++
++ if (Kernel->db->freeDatabase != gcvNULL)
++ {
++ /* Allocate a database from the free list. */
++ database = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = database->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate a new database from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE),
++ &pointer));
++
++ gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsDATABASE));
++
++ database = pointer;
++
++ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->counterMutex));
++ }
++
++ /* Insert the database into the hash. */
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++
++ /* Save the hash slot. */
++ database->slot = slot;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindDatabase
++**
++** Find a database identified by a process ID and move it to the head of the
++** hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++gceSTATUS
++gckKERNEL_FindDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database, previous;
++ gctSIZE_T slot;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d LastProcessID=%d",
++ Kernel, ProcessID, LastProcessID);
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Check whether we are getting the last known database. */
++ if (LastProcessID)
++ {
++ /* Use last database. */
++ database = Kernel->db->lastDatabase;
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ else
++ {
++ /* Walk the hash list. */
++ for (previous = gcvNULL, database = Kernel->db->db[slot];
++ database != gcvNULL;
++ database = database->next)
++ {
++ if (database->processID == ProcessID)
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = database;
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (previous != gcvNULL)
++ {
++ /* Move database to the head of the hash list. */
++ previous->next = database->next;
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteDatabase
++**
++** Remove a database from the hash list and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to the database structure to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++static gceSTATUS
++gckKERNEL_DeleteDatabase(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Check slot value. */
++ gcmkVERIFY_ARGUMENT(Database->slot < gcmCOUNTOF(Kernel->db->db));
++
++ if (Database->slot < gcmCOUNTOF(Kernel->db->db))
++ {
++ /* Check if database if the head of the hash list. */
++ if (Kernel->db->db[Database->slot] == Database)
++ {
++ /* Remove the database from the hash list. */
++ Kernel->db->db[Database->slot] = Database->next;
++ }
++ else
++ {
++ /* Walk the has list to find the database. */
++ for (database = Kernel->db->db[Database->slot];
++ database != gcvNULL;
++ database = database->next
++ )
++ {
++ /* Check if the next list entry is this database. */
++ if (database->next == Database)
++ {
++ /* Remove the database from the hash list. */
++ database->next = Database->next;
++ break;
++ }
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Ouch! Something got corrupted. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ /* Insert database to the free list. */
++ Kernel->db->lastDatabase->next = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = Kernel->db->lastDatabase;
++ }
++
++ /* Keep database as the last database. */
++ Kernel->db->lastDatabase = Database;
++
++ /* Destory handle db. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Database->handleDatabase));
++ Database->handleDatabase = gcvNULL;
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Database->handleDatabaseMutex));
++ Database->handleDatabaseMutex = gcvNULL;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Destory process MMU. */
++ gcmkVERIFY_OK(gckEVENT_DestroyMmu(Kernel->eventObj, Database->mmu, gcvKERNEL_PIXEL));
++ Database->mmu = gcvNULL;
++#endif
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_NewRecord
++**
++** Create a new database record structure and insert it to the head of the
++** database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR * Record
++** Pointer to a variable receiving the database record structure
++** pointer on success.
++*/
++static gceSTATUS
++gckKERNEL_NewRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gctUINT32 Slot,
++ OUT gcsDATABASE_RECORD_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (Kernel->db->freeRecord != gcvNULL)
++ {
++ /* Allocate the record from the free list. */
++ record = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate the record from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE_RECORD),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Insert the record in the database. */
++ record->next = Database->list[Slot];
++ Database->list[Slot] = record;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the record. */
++ *Record = record;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", *Record);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteRecord
++**
++** Remove a database record from the database and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_DeleteRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T_PTR Bytes OPTIONAL
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record, previous;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot], previous = gcvNULL;
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = record;
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return size of record. */
++ *Bytes = record->bytes;
++ }
++
++ /* Remove record from database. */
++ if (previous == gcvNULL)
++ {
++ Database->list[slot] = record->next;
++ }
++ else
++ {
++ previous->next = record->next;
++ }
++
++ /* Insert record in free list. */
++ record->next = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindRecord
++**
++** Find a database record from the database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_FindRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot];
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Record != gcvNULL)
++ {
++ /* Return information of record. */
++ gcmkONERROR(
++ gckOS_MemCopy(Record, record, sizeof(gcsDATABASE_RECORD)));
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("Record=0x%x", Record);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++***** Public API **************************************************************/
++
++/*******************************************************************************
++** gckKERNEL_CreateProcessDB
++**
++** Create a new process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database = gcvNULL;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Create a new database. */
++ gcmkONERROR(gckKERNEL_NewDatabase(Kernel, ProcessID, &database));
++
++ /* Initialize the database. */
++ database->processID = ProcessID;
++ database->vidMem.bytes = 0;
++ database->vidMem.maxBytes = 0;
++ database->vidMem.totalBytes = 0;
++ database->nonPaged.bytes = 0;
++ database->nonPaged.maxBytes = 0;
++ database->nonPaged.totalBytes = 0;
++ database->contiguous.bytes = 0;
++ database->contiguous.maxBytes = 0;
++ database->contiguous.totalBytes = 0;
++ database->mapMemory.bytes = 0;
++ database->mapMemory.maxBytes = 0;
++ database->mapMemory.totalBytes = 0;
++ database->mapUserMemory.bytes = 0;
++ database->mapUserMemory.maxBytes = 0;
++ database->mapUserMemory.totalBytes = 0;
++ database->virtualCommandBuffer.bytes = 0;
++ database->virtualCommandBuffer.maxBytes = 0;
++ database->virtualCommandBuffer.totalBytes = 0;
++
++ for (i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++ database->list[i] = gcvNULL;
++ }
++
++ for (i = 0; i < gcvSURF_NUM_TYPES; i++)
++ {
++ database->vidMemType[i].bytes = 0;
++ database->vidMemType[i].maxBytes = 0;
++ database->vidMemType[i].totalBytes = 0;
++ }
++
++ for (i = 0; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ database->vidMemPool[i].bytes = 0;
++ database->vidMemPool[i].maxBytes = 0;
++ database->vidMemPool[i].totalBytes = 0;
++ }
++
++ gcmkASSERT(database->handleDatabase == gcvNULL);
++ gcmkONERROR(
++ gckKERNEL_CreateIntegerDatabase(Kernel, &database->handleDatabase));
++
++ gcmkASSERT(database->handleDatabaseMutex == gcvNULL);
++ gcmkONERROR(
++ gckOS_CreateMutex(Kernel->os, &database->handleDatabaseMutex));
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkASSERT(database->mmu == gcvNULL);
++ gcmkONERROR(
++ gckMMU_Construct(Kernel, gcdMMU_SIZE, &database->mmu));
++#endif
++
++ /* Reset idle timer. */
++ Kernel->db->lastIdle = 0;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AddProcessDB
++**
++** Add a record to a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to add.
++**
++** gctPOINTER Pointer
++** Data of the record to add.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the record to add.
++**
++** gctSIZE_T Size
++** Size of the record to add.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++ gcsDATABASE_COUNTERS * count;
++ gctUINT32 vidMemType;
++ gcePOOL vidMemPool;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x "
++ "Physical=0x%x Size=%lu",
++ Kernel, ProcessID, Type, Pointer, Physical, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Decode type. */
++ vidMemType = (Type & gcdDB_VIDEO_MEMORY_TYPE_MASK) >> gcdDB_VIDEO_MEMORY_TYPE_SHIFT;
++ vidMemPool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT;
++
++ Type &= gcdDATABASE_TYPE_MASK;
++
++ /* Special case the idle record. */
++ if (Type == gcvDB_IDLE)
++ {
++ gctUINT64 time;
++
++ /* Get the current profile time. */
++ gcmkONERROR(gckOS_GetProfileTick(&time));
++
++ if ((ProcessID == 0) && (Kernel->db->lastIdle != 0))
++ {
++ /* Out of idle, adjust time it was idle. */
++ Kernel->db->idleTime += time - Kernel->db->lastIdle;
++ Kernel->db->lastIdle = 0;
++ }
++ else if (ProcessID == 1)
++ {
++ /* Save current idle time. */
++ Kernel->db->lastIdle = time;
++ }
++
++#if gcdDYNAMIC_SPEED
++ {
++ /* Test for first call. */
++ if (Kernel->db->lastSlowdown == 0)
++ {
++ /* Save milliseconds. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ else
++ {
++ /* Compute ellapsed time in milliseconds. */
++ gctUINT delta = gckOS_ProfileToMS(time - Kernel->db->lastSlowdown);
++
++ /* Test for end of period. */
++ if (delta >= gcdDYNAMIC_SPEED)
++ {
++ /* Compute number of idle milliseconds. */
++ gctUINT idle = gckOS_ProfileToMS(
++ Kernel->db->idleTime - Kernel->db->lastSlowdownIdle);
++
++ /* Broadcast to slow down the GPU. */
++ gcmkONERROR(gckOS_BroadcastCalibrateSpeed(Kernel->os,
++ Kernel->hardware,
++ idle,
++ delta));
++
++ /* Save current time. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ }
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Create a new record in the database. */
++ gcmkONERROR(gckKERNEL_NewRecord(Kernel, database, _GetSlot(database, Pointer), &record));
++
++ /* Initialize the record. */
++ record->kernel = Kernel;
++ record->type = Type;
++ record->data = Pointer;
++ record->physical = Physical;
++ record->bytes = Size;
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ count = &database->vidMem;
++ break;
++
++ case gcvDB_NON_PAGED:
++ count = &database->nonPaged;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ count = &database->contiguous;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ count = &database->mapMemory;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ count = &database->mapUserMemory;
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ count = &database->virtualCommandBuffer;
++ break;
++
++ default:
++ count = gcvNULL;
++ break;
++ }
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE));
++
++ if (count != gcvNULL)
++ {
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++ }
++
++ if (Type == gcvDB_VIDEO_MEMORY)
++ {
++ count = &database->vidMemType[vidMemType];
++
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++
++ count = &database->vidMemPool[vidMemPool];
++
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_RemoveProcessDB
++**
++** Remove a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctSIZE_T bytes = 0;
++ gctUINT32 vidMemType;
++ gcePOOL vidMempool;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Decode type. */
++ vidMemType = (Type & gcdDB_VIDEO_MEMORY_TYPE_MASK) >> gcdDB_VIDEO_MEMORY_TYPE_SHIFT;
++ vidMempool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT;
++
++ Type &= gcdDATABASE_TYPE_MASK;
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Delete the record. */
++ gcmkONERROR(
++ gckKERNEL_DeleteRecord(Kernel, database, Type, Pointer, &bytes));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE));
++
++ /* Update counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ database->vidMem.bytes -= bytes;
++ database->vidMemType[vidMemType].bytes -= bytes;
++ database->vidMemPool[vidMempool].bytes -= bytes;
++ break;
++
++ case gcvDB_NON_PAGED:
++ database->nonPaged.bytes -= bytes;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ database->contiguous.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ database->mapMemory.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ database->mapUserMemory.bytes -= bytes;
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ database->virtualCommandBuffer.bytes -= bytes;
++ break;
++
++ default:
++ break;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindProcessDB
++**
++** Find a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR Record
++** Copy of record.
++*/
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, ThreadID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Find the record. */
++ gcmkONERROR(
++ gckKERNEL_FindRecord(Kernel, database, Type, Pointer, Record));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DestroyProcessDB
++**
++** Destroy a process database. If the database contains any records, the data
++** inside those records will be deleted as well. This aids in the cleanup if
++** a process has died unexpectedly or has memory leaks.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record, next;
++ gctBOOL asynchronous = gcvTRUE;
++ gckVIDMEM_NODE nodeObject;
++ gctPHYS_ADDR physical;
++ gckKERNEL kernel = Kernel;
++ gctUINT32 handle;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): VidMem: total=%lu max=%lu",
++ ProcessID, database->vidMem.totalBytes,
++ database->vidMem.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): NonPaged: total=%lu max=%lu",
++ ProcessID, database->nonPaged.totalBytes,
++ database->nonPaged.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Contiguous: total=%lu max=%lu",
++ ProcessID, database->contiguous.totalBytes,
++ database->contiguous.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Idle time=%llu",
++ ProcessID, Kernel->db->idleTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapMemory.totalBytes,
++ database->mapMemory.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapUserMemory.totalBytes,
++ database->mapUserMemory.maxBytes);
++
++ if (database->list != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "Process %d has entries in its database:",
++ ProcessID);
++ }
++
++ for(i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++
++ /* Walk all records. */
++ for (record = database->list[i]; record != gcvNULL; record = next)
++ {
++ /* Next next record. */
++ next = record->next;
++
++ /* Dispatch on record type. */
++ switch (record->type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(record->kernel,
++ ProcessID,
++ gcmPTR2INT32(record->data),
++ &nodeObject));
++
++ /* Free the video memory. */
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel,
++ ProcessID,
++ gcmPTR2INT32(record->data)));
++
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel,
++ nodeObject));
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_NON_PAGED:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the non paged memory. */
++ status = gckEVENT_FreeNonPagedMemory(Kernel->eventObj,
++ record->bytes,
++ physical,
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: NON_PAGED 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ /* Free the command buffer. */
++ status = gckEVENT_DestroyVirtualCommandBuffer(record->kernel->eventObj,
++ record->bytes,
++ gcmNAME_TO_PTR(record->physical),
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: COMMAND_BUFFER 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the contiguous memory. */
++ status = gckEVENT_FreeContiguousMemory(Kernel->eventObj,
++ record->bytes,
++ physical,
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTIGUOUS 0x%x bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_SIGNAL:
++ /* Free the user signal. */
++ status = gckOS_DestroyUserSignal(Kernel->os,
++ gcmPTR2INT32(record->data));
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SIGNAL %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++
++ case gcvDB_VIDEO_MEMORY_LOCKED:
++ handle = gcmPTR2INT32(record->data);
++
++ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(record->kernel,
++ ProcessID,
++ handle,
++ &nodeObject));
++
++ /* Unlock what we still locked */
++ status = gckVIDMEM_Unlock(record->kernel,
++ nodeObject,
++ nodeObject->type,
++ &asynchronous);
++
++#if gcdENABLE_VG
++ if (record->kernel->core == gcvCORE_VG)
++ {
++ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous))
++ {
++ /* TODO: we maybe need to schedule a event here */
++ status = gckVIDMEM_Unlock(record->kernel,
++ nodeObject,
++ nodeObject->type,
++ gcvNULL);
++ }
++
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel,
++ ProcessID,
++ handle));
++
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel,
++ nodeObject));
++ }
++ else
++#endif
++ {
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel,
++ ProcessID,
++ handle));
++
++ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous))
++ {
++ status = gckEVENT_Unlock(record->kernel->eventObj,
++ gcvKERNEL_PIXEL,
++ nodeObject,
++ nodeObject->type);
++ }
++ else
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel,
++ nodeObject));
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY_LOCKED 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_CONTEXT:
++ /* TODO: Free the context */
++ status = gckCOMMAND_Detach(Kernel->command, gcmNAME_TO_PTR(record->data));
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTEXT 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ /* Unmap memory. */
++ status = gckKERNEL_UnmapMemory(Kernel,
++ record->physical,
++ record->bytes,
++ record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP MEMORY %d (status=%d)",
++ gcmPTR2INT32(record->data), status);
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ /* TODO: Unmap user memory. */
++ status = gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ record->physical,
++ record->bytes,
++ gcmNAME_TO_PTR(record->data),
++ 0);
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP USER MEMORY %d (status=%d)",
++ gcmPTR2INT32(record->data), status);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvDB_SYNC_POINT:
++ /* Free the user signal. */
++ status = gckOS_DestroySyncPoint(Kernel->os,
++ (gctSYNC_POINT) record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SYNC POINT %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++#endif
++
++ case gcvDB_SHBUF:
++ /* Free shared buffer. */
++ status = gckKERNEL_DestroyShBuffer(Kernel,
++ (gctSHBUF) record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SHBUF %u (status=%d)",
++ (gctUINT32)(gctUINTPTR_T) record->data, status);
++ break;
++
++ default:
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DATABASE,
++ "DB: Correcupted record=0x%08x type=%d",
++ record, record->type);
++ break;
++ }
++
++ /* Delete the record. */
++ gcmkONERROR(gckKERNEL_DeleteRecord(Kernel,
++ database,
++ record->type,
++ record->data,
++ gcvNULL));
++ }
++
++ }
++
++ /* Delete the database. */
++ gcmkONERROR(gckKERNEL_DeleteDatabase(Kernel, database));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_QueryProcessDB
++**
++** Query a process database for the current usage of a particular record type.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to query.
++**
++** OUTPUT:
++**
++** gcuDATABASE_INFO * Info
++** Pointer to a variable that receives the requested information.
++*/
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcePOOL vidMemPool;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Info=0x%x",
++ Kernel, ProcessID, Type, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Deocde pool. */
++ vidMemPool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT;
++
++ Type &= gcdDATABASE_TYPE_MASK;
++
++ /* Find the database. */
++ if(Type != gcvDB_IDLE)
++ {
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(Kernel, ProcessID, LastProcessID, &database));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE));
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ if (vidMemPool != gcvPOOL_UNKNOWN)
++ {
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMemPool[vidMemPool],
++ gcmSIZEOF(database->vidMemPool[vidMemPool]));
++ }
++ else
++ {
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMem,
++ gcmSIZEOF(database->vidMem));
++ }
++ break;
++
++ case gcvDB_NON_PAGED:
++ gckOS_MemCopy(&Info->counters,
++ &database->nonPaged,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ gckOS_MemCopy(&Info->counters,
++ &database->contiguous,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapMemory,
++ gcmSIZEOF(database->mapMemory));
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapUserMemory,
++ gcmSIZEOF(database->mapUserMemory));
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ gckOS_MemCopy(&Info->counters,
++ &database->virtualCommandBuffer,
++ gcmSIZEOF(database->virtualCommandBuffer));
++ break;
++
++ default:
++ break;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex));
++ }
++ else
++ {
++ Info->time = Kernel->db->idleTime;
++ Kernel->db->idleTime = 0;
++ }
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FindHandleDatbase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gctPOINTER * HandleDatabase,
++ OUT gctPOINTER * HandleDatabaseMutex
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d",
++ Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ *HandleDatabase = database->handleDatabase;
++ *HandleDatabaseMutex = database->handleDatabaseMutex;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckKERNEL_GetProcessMMU(
++ IN gckKERNEL Kernel,
++ OUT gckMMU * Mmu
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctUINT32 processID;
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, processID, gcvFALSE, &database));
++
++ *Mmu = database->mmu;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++#endif
++
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ )
++{
++ gcsDATABASE_PTR database;
++ gctINT i, pid;
++ gctUINT8 name[24];
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** PROCESS DB DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkPRINT_N(8, "%-8s%s\n", "PID", "NAME");
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ for (database = Kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ pid = database->processID;
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ gcmkPRINT_N(8, "%-8d%s\n", pid, name);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_DumpCounter(
++ IN gcsDATABASE_COUNTERS * Counter,
++ IN gctCONST_STRING Name
++ )
++{
++ gcmkPRINT("%s:", Name);
++ gcmkPRINT(" Currently allocated : %10lld", Counter->bytes);
++ gcmkPRINT(" Maximum allocated : %10lld", Counter->maxBytes);
++ gcmkPRINT(" Total allocated : %10lld", Counter->totalBytes);
++}
++
++gceSTATUS
++gckKERNEL_DumpVidMemUsage(
++ IN gckKERNEL Kernel,
++ IN gctINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_COUNTERS * counter;
++ gctUINT32 i = 0;
++
++ static gctCONST_STRING surfaceTypes[] = {
++ "UNKNOWN",
++ "INDEX",
++ "VERTEX",
++ "TEXTURE",
++ "RENDER_TARGET",
++ "DEPTH",
++ "BITMAP",
++ "TILE_STATUS",
++ "IMAGE",
++ "MASK",
++ "SCISSOR",
++ "HIERARCHICAL_DEPTH",
++ };
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d",
++ Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Find the database. */
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ gcmkPRINT("VidMem Usage (Process %d):", ProcessID);
++
++ /* Get pointer to counters. */
++ counter = &database->vidMem;
++
++ _DumpCounter(counter, "Total Video Memory");
++
++ for (i = 0; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ _DumpCounter(counter, surfaceTypes[i]);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debug.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debug.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debug.c 2016-06-19 22:11:55.137151030 +0200
+@@ -0,0 +1,2766 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include <gc_hal_kernel_debug.h>
++
++/******************************************************************************\
++******************************** Debug Variables *******************************
++\******************************************************************************/
++
++static gceSTATUS _lastError = gcvSTATUS_OK;
++static gctUINT32 _debugLevel = gcvLEVEL_ERROR;
++/*
++_debugZones config value
++Please Reference define in gc_hal_base.h
++*/
++static gctUINT32 _debugZones = gcvZONE_ALL;
++
++/******************************************************************************\
++********************************* Debug Switches *******************************
++\******************************************************************************/
++
++/*
++ gcdBUFFERED_OUTPUT
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console. gcdBUFFERED_SIZE determines the size of the buffer.
++*/
++#define gcdBUFFERED_OUTPUT 0
++
++/*
++ gcdBUFFERED_SIZE
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console.
++*/
++#define gcdBUFFERED_SIZE (1024 * 1024 * 2)
++
++/*
++ gcdDMA_BUFFER_COUNT
++
++ If greater then zero, the debugger will attempt to find the command buffer
++ where DMA is currently executing and then print this buffer and
++ (gcdDMA_BUFFER_COUNT - 1) buffers before the current one. If set to zero
++ or the current buffer is not found, all buffers are printed.
++*/
++#define gcdDMA_BUFFER_COUNT 0
++
++/*
++ gcdTHREAD_BUFFERS
++
++ When greater then one, will accumulate messages from the specified number
++ of threads in separate output buffers.
++*/
++#define gcdTHREAD_BUFFERS 1
++
++/*
++ gcdENABLE_OVERFLOW
++
++ When set to non-zero, and the output buffer gets full, instead of being
++ printed, it will be allowed to overflow removing the oldest messages.
++*/
++#define gcdENABLE_OVERFLOW 1
++
++/*
++ gcdSHOW_LINE_NUMBER
++
++ When enabledm each print statement will be preceeded with the current
++ line number.
++*/
++#define gcdSHOW_LINE_NUMBER 0
++
++/*
++ gcdSHOW_PROCESS_ID
++
++ When enabledm each print statement will be preceeded with the current
++ process ID.
++*/
++#define gcdSHOW_PROCESS_ID 0
++
++/*
++ gcdSHOW_THREAD_ID
++
++ When enabledm each print statement will be preceeded with the current
++ thread ID.
++*/
++#define gcdSHOW_THREAD_ID 0
++
++/*
++ gcdSHOW_TIME
++
++ When enabled each print statement will be preceeded with the current
++ high-resolution time.
++*/
++#define gcdSHOW_TIME 0
++
++
++/******************************************************************************\
++****************************** Miscellaneous Macros ****************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmDBGASSERT(Expression, Format, Value) \
++ if (!(Expression)) \
++ { \
++ _DirectPrint( \
++ "*** gcmDBGASSERT ***************************\n" \
++ " function : %s\n" \
++ " line : %d\n" \
++ " expression : " #Expression "\n" \
++ " actual value : " Format "\n", \
++ __FUNCTION__, __LINE__, Value \
++ ); \
++ }
++#else
++# define gcmDBGASSERT(Expression, Format, Value)
++#endif
++
++#define gcmPTRALIGNMENT(Pointer, Alignemnt) \
++( \
++ gcmALIGN(gcmPTR2INT32(Pointer), Alignemnt) - gcmPTR2INT32(Pointer) \
++)
++
++#if gcdALIGNBYSIZE
++# define gcmISALIGNED(Offset, Alignment) \
++ (((Offset) & ((Alignment) - 1)) == 0)
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment) \
++ Pointer = (Type) gcmINT2PTR(gcmALIGN(gcmPTR2INT32(Pointer), Alignment))
++#else
++# define gcmISALIGNED(Offset, Alignment) \
++ gcvTRUE
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment)
++#endif
++
++#define gcmALIGNSIZE(Offset, Size) \
++ ((Size - Offset) + Size)
++
++#define gcdHAVEPREFIX \
++( \
++ gcdSHOW_TIME \
++ || gcdSHOW_LINE_NUMBER \
++ || gcdSHOW_PROCESS_ID \
++ || gcdSHOW_THREAD_ID \
++)
++
++#if gcdHAVEPREFIX
++
++# define gcdOFFSET 0
++
++#if gcdSHOW_TIME
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdTIMESIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdTIMESIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdTIMEFORMAT "0x%016llX"
++# else
++# define gcdTIMEFORMAT ", 0x%016llX"
++# endif
++# else
++# define gcdTIMESIZE 0
++# define gcdTIMEFORMAT
++# endif
++
++#if gcdSHOW_LINE_NUMBER
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdNUMSIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdNUMSIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdNUMFORMAT "%8llu"
++# else
++# define gcdNUMFORMAT ", %8llu"
++# endif
++# else
++# define gcdNUMSIZE 0
++# define gcdNUMFORMAT
++# endif
++
++#if gcdSHOW_PROCESS_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdPIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPIDFORMAT "pid=%5d"
++# else
++# define gcdPIDFORMAT ", pid=%5d"
++# endif
++# else
++# define gcdPIDSIZE 0
++# define gcdPIDFORMAT
++# endif
++
++#if gcdSHOW_THREAD_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdTIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdTIDFORMAT "tid=%5d"
++# else
++# define gcdTIDFORMAT ", tid=%5d"
++# endif
++# else
++# define gcdTIDSIZE 0
++# define gcdTIDFORMAT
++# endif
++
++# define gcdPREFIX_SIZE \
++ ( \
++ gcdTIMESIZE \
++ + gcdNUMSIZE \
++ + gcdPIDSIZE \
++ + gcdTIDSIZE \
++ )
++
++ static const char * _prefixFormat =
++ "["
++ gcdTIMEFORMAT
++ gcdNUMFORMAT
++ gcdPIDFORMAT
++ gcdTIDFORMAT
++ "] ";
++
++#else
++
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPREFIX_SIZE 0
++
++#endif
++
++/* Assumed largest variable argument leader size. */
++#define gcdVARARG_LEADER gcmSIZEOF(gctUINT64)
++
++/* Alignnments. */
++#if gcdALIGNBYSIZE
++# define gcdPREFIX_ALIGNMENT gcdPREFIX_LEADER
++# define gcdVARARG_ALIGNMENT gcdVARARG_LEADER
++#else
++# define gcdPREFIX_ALIGNMENT 0
++# define gcdVARARG_ALIGNMENT 0
++#endif
++
++#if gcdBUFFERED_OUTPUT
++# define gcdOUTPUTPREFIX _AppendPrefix
++# define gcdOUTPUTSTRING _AppendString
++# define gcdOUTPUTCOPY _AppendCopy
++# define gcdOUTPUTBUFFER _AppendBuffer
++#else
++# define gcdOUTPUTPREFIX _PrintPrefix
++# define gcdOUTPUTSTRING _PrintString
++# define gcdOUTPUTCOPY _PrintString
++# define gcdOUTPUTBUFFER _PrintBuffer
++#endif
++
++/******************************************************************************\
++****************************** Private Structures ******************************
++\******************************************************************************/
++
++typedef enum _gceBUFITEM
++{
++ gceBUFITEM_NONE,
++ gcvBUFITEM_PREFIX,
++ gcvBUFITEM_STRING,
++ gcvBUFITEM_COPY,
++ gcvBUFITEM_BUFFER
++}
++gceBUFITEM;
++
++/* Common item head/buffer terminator. */
++typedef struct _gcsBUFITEM_HEAD * gcsBUFITEM_HEAD_PTR;
++typedef struct _gcsBUFITEM_HEAD
++{
++ gceBUFITEM type;
++}
++gcsBUFITEM_HEAD;
++
++/* String prefix (for ex. [ 1,tid=0x019A]) */
++typedef struct _gcsBUFITEM_PREFIX * gcsBUFITEM_PREFIX_PTR;
++typedef struct _gcsBUFITEM_PREFIX
++{
++ gceBUFITEM type;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_PREFIX;
++
++/* Buffered string. */
++typedef struct _gcsBUFITEM_STRING * gcsBUFITEM_STRING_PTR;
++typedef struct _gcsBUFITEM_STRING
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctCONST_STRING message;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_STRING;
++
++/* Buffered string (copy of the string is included with the record). */
++typedef struct _gcsBUFITEM_COPY * gcsBUFITEM_COPY_PTR;
++typedef struct _gcsBUFITEM_COPY
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_COPY;
++
++/* Memory buffer. */
++typedef struct _gcsBUFITEM_BUFFER * gcsBUFITEM_BUFFER_PTR;
++typedef struct _gcsBUFITEM_BUFFER
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gceDUMP_BUFFER bufferType;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ gctUINT32 dmaAddress;
++#endif
++
++ gctUINT dataSize;
++ gctUINT32 address;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_BUFFER;
++
++typedef struct _gcsBUFFERED_OUTPUT * gcsBUFFERED_OUTPUT_PTR;
++typedef struct _gcsBUFFERED_OUTPUT
++{
++#if gcdTHREAD_BUFFERS > 1
++ gctUINT32 threadID;
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ gctUINT64 lineNumber;
++#endif
++
++ gctINT indent;
++
++#if gcdBUFFERED_OUTPUT
++ gctINT start;
++ gctINT index;
++ gctINT count;
++ gctUINT8 buffer[gcdBUFFERED_SIZE];
++#endif
++
++ gcsBUFFERED_OUTPUT_PTR prev;
++ gcsBUFFERED_OUTPUT_PTR next;
++}
++gcsBUFFERED_OUTPUT;
++
++typedef gctUINT (* gcfPRINTSTRING) (
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++typedef gctINT (* gcfGETITEMSIZE) (
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++/******************************************************************************\
++******************************* Private Variables ******************************
++\******************************************************************************/
++
++static gcsBUFFERED_OUTPUT _outputBuffer[gcdTHREAD_BUFFERS];
++static gcsBUFFERED_OUTPUT_PTR _outputBufferHead = gcvNULL;
++static gcsBUFFERED_OUTPUT_PTR _outputBufferTail = gcvNULL;
++
++/******************************************************************************\
++****************************** Item Size Functions *****************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++static gctINT
++_GetTerminatorItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctINT
++_GetPrefixItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item = (gcsBUFITEM_PREFIX_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctINT
++_GetStringItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item = (gcsBUFITEM_STRING_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetCopyItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item = (gcsBUFITEM_COPY_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetBufferItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfGETITEMSIZE _itemSize[] =
++{
++ _GetTerminatorItemSize,
++ _GetPrefixItemSize,
++ _GetStringItemSize,
++ _GetCopyItemSize,
++ _GetBufferItemSize
++};
++#endif
++
++/******************************************************************************\
++******************************* Printing Functions *****************************
++\******************************************************************************/
++
++#if gcdDEBUG || gcdBUFFERED_OUTPUT
++static void
++_DirectPrint(
++ gctCONST_STRING Message,
++ ...
++ )
++{
++ gctINT len;
++ char buffer[768];
++ gctARGUMENTS arguments;
++
++ gcmkARGUMENTS_START(arguments, Message);
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), Message, &arguments);
++ gcmkARGUMENTS_END(arguments);
++
++ buffer[len] = '\0';
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static int
++_AppendIndent(
++ IN gctINT Indent,
++ IN char * Buffer,
++ IN int BufferSize
++ )
++{
++ gctINT i;
++
++ gctINT len = 0;
++ gctINT indent = Indent % 40;
++
++ for (i = 0; i < indent; i += 1)
++ {
++ Buffer[len++] = ' ';
++ }
++
++ if (indent != Indent)
++ {
++ len += gcmkSPRINTF(
++ Buffer + len, BufferSize - len, " <%d> ", Indent
++ );
++
++ Buffer[len] = '\0';
++ }
++
++ return len;
++}
++
++#if gcdHAVEPREFIX
++static void
++_PrintPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Format the string. */
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, Data);
++ buffer[len] = '\0';
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static void
++_PrintString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Append the indent string. */
++ len = _AppendIndent(Indent, buffer, gcmSIZEOF(buffer));
++
++ /* Format the string. */
++ len += gcmkVSPRINTF(buffer + len, gcmSIZEOF(buffer) - len, Message, Data);
++ buffer[len] = '\0';
++
++ /* Add end-of-line if missing. */
++ if (buffer[len - 1] != '\n')
++ {
++ buffer[len++] = '\n';
++ buffer[len] = '\0';
++ }
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++
++static void
++_PrintBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++ static gctCONST_STRING _titleString[] =
++ {
++ "CONTEXT BUFFER",
++ "USER COMMAND BUFFER",
++ "KERNEL COMMAND BUFFER",
++ "LINK BUFFER",
++ "WAIT LINK BUFFER",
++ ""
++ };
++
++ static const gctINT COLUMN_COUNT = 8;
++
++ gctUINT i, count, column, address;
++ gctUINT32_PTR data;
++ gctCHAR buffer[768];
++ gctUINT indent, len;
++ gctBOOL command;
++
++ /* Append space for the prefix. */
++#if gcdHAVEPREFIX
++ indent = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, PrefixData);
++ buffer[indent] = '\0';
++#else
++ indent = 0;
++#endif
++
++ /* Append the indent string. */
++ indent += _AppendIndent(
++ Indent, buffer + indent, gcmSIZEOF(buffer) - indent
++ );
++
++ switch (Type)
++ {
++ case gceDUMP_BUFFER_CONTEXT:
++ case gceDUMP_BUFFER_USER:
++ case gceDUMP_BUFFER_KERNEL:
++ case gceDUMP_BUFFER_LINK:
++ case gceDUMP_BUFFER_WAITLINK:
++ /* Form and print the title string. */
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "%s%s\n", _titleString[Type],
++ ((DmaAddress >= Address) && (DmaAddress < Address + DataSize))
++ ? " (CURRENT)" : ""
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++
++ /* This is a command buffer. */
++ command = gcvTRUE;
++ break;
++
++ case gceDUMP_BUFFER_FROM_USER:
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++
++ /* No title. */
++ break;
++
++ default:
++ gcmDBGASSERT(gcvFALSE, "%s", "invalid buffer type");
++
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++ }
++
++ /* Overwrite the prefix with spaces. */
++ for (i = 0; i < indent; i += 1)
++ {
++ buffer[i] = ' ';
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "@[kernel.command %08X %08X\n", Address, DataSize
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++ }
++
++ /* Get initial address. */
++ address = Address;
++
++ /* Cast the data pointer. */
++ data = (gctUINT32_PTR) Data;
++
++ /* Compute the number of double words. */
++ count = DataSize / gcmSIZEOF(gctUINT32);
++
++ /* Print the buffer. */
++ for (i = 0, len = indent, column = 0; i < count; i += 1)
++ {
++ /* Append the address. */
++ if (column == 0)
++ {
++ len += gcmkSPRINTF(
++ buffer + len, gcmSIZEOF(buffer) - len, "0x%08X:", address
++ );
++ }
++
++ /* Append the data value. */
++ len += gcmkSPRINTF2(
++ buffer + len, gcmSIZEOF(buffer) - len, "%c%08X",
++ (address == DmaAddress)? '>' : ' ', data[i]
++ );
++
++ buffer[len] = '\0';
++
++ /* Update the address. */
++ address += gcmSIZEOF(gctUINT32);
++
++ /* Advance column count. */
++ column += 1;
++
++ /* End of line? */
++ if ((column % COLUMN_COUNT) == 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Reset. */
++ len = indent;
++ column = 0;
++ }
++ }
++
++ /* Print the last partial string. */
++ if (column != 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ buffer[indent] = '\0';
++ gcmkSTRCAT(buffer, gcmSIZEOF(buffer), "] -- command\n");
++ gcmkOUTPUT_STRING(buffer);
++ }
++}
++
++#if gcdBUFFERED_OUTPUT
++static gctUINT
++_PrintNone(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctUINT
++_PrintPrefixWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_PREFIX_PTR) Item;
++
++ /* Print the message. */
++ _PrintPrefix(OutputBuffer, item->prefixData);
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctUINT
++_PrintStringWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_STRING_PTR) Item;
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, item->message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintCopyWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item;
++ gctCONST_STRING message;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_COPY_PTR) Item;
++
++ /* Determine the string pointer. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintBufferWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctPOINTER data;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Compute the data address. */
++ data = ((gctUINT8_PTR) item->prefixData) + gcdPREFIX_SIZE;
++
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, item->prefixData,
++ data, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, gcvNULL,
++ item + 1, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfPRINTSTRING _printArray[] =
++{
++ _PrintNone,
++ _PrintPrefixWrapper,
++ _PrintStringWrapper,
++ _PrintCopyWrapper,
++ _PrintBufferWrapper
++};
++#endif
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++static gcsBUFITEM_BUFFER_PTR
++_FindCurrentDMABuffer(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR dmaCurrent;
++
++ /* Reset the current buffer. */
++ dmaCurrent = gcvNULL;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ if ((DmaAddress >= buffer->address) &&
++ (DmaAddress < buffer->address + buffer->dataSize))
++ {
++ dmaCurrent = buffer;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Return result. */
++ return dmaCurrent;
++}
++
++static void
++_EnableAllDMABuffers(
++ void
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Enable the buffer. */
++ buffer->dmaAddress = ~0U;
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++}
++
++static void
++_EnableDMABuffers(
++ gctUINT32 DmaAddress,
++ gcsBUFITEM_BUFFER_PTR CurrentDMABuffer
++ )
++{
++ gctINT i, skip, index;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR buffers[gcdDMA_BUFFER_COUNT];
++
++ /* Reset buffer pointers. */
++ gckOS_ZeroMemory(buffers, gcmSIZEOF(buffers));
++
++ /* Set the current buffer index. */
++ index = -1;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items until the current DMA buffer is found. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ /* Advance the index. */
++ index = (index + 1) % gcdDMA_BUFFER_COUNT;
++
++ /* Add to the buffer array. */
++ buffers[index] = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Stop if this is the current DMA buffer. */
++ if ((gcsBUFITEM_BUFFER_PTR) item == CurrentDMABuffer)
++ {
++ break;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Enable the found buffers. */
++ gcmDBGASSERT(index != -1, "%d", index);
++
++ for (i = 0; i < gcdDMA_BUFFER_COUNT; i += 1)
++ {
++ if (buffers[index] == gcvNULL)
++ {
++ break;
++ }
++
++ buffers[index]->dmaAddress = DmaAddress;
++
++ index -= 1;
++
++ if (index == -1)
++ {
++ index = gcdDMA_BUFFER_COUNT - 1;
++ }
++ }
++}
++#endif
++
++static void
++_Flush(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ gcsBUFFERED_OUTPUT_PTR outputBuffer = _outputBufferHead;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ if ((outputBuffer != gcvNULL) && (outputBuffer->count != 0))
++ {
++ /* Find the current DMA buffer. */
++ gcsBUFITEM_BUFFER_PTR dmaCurrent = _FindCurrentDMABuffer(DmaAddress);
++
++ /* Was the current buffer found? */
++ if (dmaCurrent == gcvNULL)
++ {
++ /* No, print all buffers. */
++ _EnableAllDMABuffers();
++ }
++ else
++ {
++ /* Yes, enable only specified number of buffers. */
++ _EnableDMABuffers(DmaAddress, dmaCurrent);
++ }
++ }
++#endif
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->count != 0)
++ {
++ _DirectPrint("********************************************************************************\n");
++ _DirectPrint("FLUSHING DEBUG OUTPUT BUFFER (%d elements).\n", outputBuffer->count);
++ _DirectPrint("********************************************************************************\n");
++
++ item = (gcsBUFITEM_HEAD_PTR) &outputBuffer->buffer[outputBuffer->start];
++
++ for (i = 0; i < outputBuffer->count; i += 1)
++ {
++ skip = (* _printArray[item->type]) (outputBuffer, item);
++
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) outputBuffer->buffer;
++ }
++ }
++
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++}
++
++static gcsBUFITEM_HEAD_PTR
++_AllocateItem(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Size
++ )
++{
++ gctINT skip;
++ gcsBUFITEM_HEAD_PTR item, next;
++
++#if gcdENABLE_OVERFLOW
++ if (
++ (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ ||
++ (
++ (OutputBuffer->index < OutputBuffer->start) &&
++ (OutputBuffer->index + Size >= OutputBuffer->start)
++ )
++ )
++ {
++ if (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ if (OutputBuffer->index < OutputBuffer->start)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (item->type != gceBUFITEM_NONE)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++ }
++
++ OutputBuffer->start = 0;
++ }
++
++ OutputBuffer->index = 0;
++ }
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (OutputBuffer->start - OutputBuffer->index <= Size)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ OutputBuffer->start = 0;
++ break;
++ }
++ }
++ }
++#else
++ if (OutputBuffer->index + Size > gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ _DirectPrint("\nMessage buffer full; forcing message flush.\n\n");
++ _Flush(~0U);
++ }
++#endif
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->index];
++
++ OutputBuffer->index += Size;
++ OutputBuffer->count += 1;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + Size);
++ next->type = gceBUFITEM_NONE;
++
++ return item;
++}
++
++#if gcdALIGNBYSIZE
++static void
++_FreeExtraSpace(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Item,
++ IN gctINT ItemSize,
++ IN gctINT FreeSize
++ )
++{
++ gcsBUFITEM_HEAD_PTR next;
++
++ OutputBuffer->index -= FreeSize;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) Item + ItemSize);
++ next->type = gceBUFITEM_NONE;
++}
++#endif
++
++#if gcdHAVEPREFIX
++static void
++_AppendPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_PREFIX_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_PREFIX)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_PREFIX_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_PREFIX;
++ item->prefixData = prefixData;
++
++ /* Copy argument value. */
++ memcpy(prefixData, Data, gcdPREFIX_SIZE);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_PREFIX) + gcdPREFIX_SIZE + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++#endif
++
++static void
++_AppendString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_STRING_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_STRING)
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_STRING_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_STRING;
++ item->indent = Indent;
++ item->message = Message;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_STRING) + ArgumentSize + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendCopy(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_COPY_PTR item;
++ gctINT allocSize;
++ gctINT messageLength;
++ gctCONST_STRING message;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Get the length of the string. */
++ messageLength = strlen(Message) + 1;
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_COPY_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Determine the message placement. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) message + messageLength;
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ if (ArgumentSize == 0)
++ {
++ alignment = 0;
++ }
++ else
++ {
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++ }
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_COPY;
++ item->indent = Indent;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy the message. */
++ memcpy((gctPOINTER) message, Message, messageLength);
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT allocSize;
++ gctPOINTER data;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT
++ + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++#if gcdALIGNBYSIZE
++ /* Align the data pointer as necessary. */
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->bufferType = Type;
++ item->dataSize = DataSize;
++ item->address = Address;
++ item->prefixData = prefixData;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ item->dmaAddress = DmaAddress;
++#endif
++
++ /* Copy prefix data. */
++ memcpy(prefixData, PrefixData, gcdPREFIX_SIZE);
++
++ /* Compute the data pointer. */
++ data = prefixData + gcdPREFIX_SIZE;
++
++ /* Copy argument value. */
++ memcpy(data, Data, DataSize);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + alignment
++ + DataSize;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++#else
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT size;
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ size = gcmSIZEOF(gcsBUFITEM_BUFFER) + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, size);
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->dataSize = DataSize;
++ item->address = Address;
++
++ /* Copy argument value. */
++ memcpy(item + 1, Data, DataSize);
++#endif
++}
++#endif
++
++static gcmINLINE void
++_InitBuffers(
++ void
++ )
++{
++ int i;
++
++ if (_outputBufferHead == gcvNULL)
++ {
++ for (i = 0; i < gcdTHREAD_BUFFERS; i += 1)
++ {
++ if (_outputBufferTail == gcvNULL)
++ {
++ _outputBufferHead = &_outputBuffer[i];
++ }
++ else
++ {
++ _outputBufferTail->next = &_outputBuffer[i];
++ }
++
++#if gcdTHREAD_BUFFERS > 1
++ _outputBuffer[i].threadID = ~0U;
++#endif
++
++ _outputBuffer[i].prev = _outputBufferTail;
++ _outputBuffer[i].next = gcvNULL;
++
++ _outputBufferTail = &_outputBuffer[i];
++ }
++ }
++}
++
++static gcmINLINE gcsBUFFERED_OUTPUT_PTR
++_GetOutputBuffer(
++ void
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++
++#if gcdTHREAD_BUFFERS > 1
++ /* Get the current thread ID. */
++ gctUINT32 ThreadID = gcmkGETTHREADID();
++
++ /* Locate the output buffer for the thread. */
++ outputBuffer = _outputBufferHead;
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->threadID == ThreadID)
++ {
++ break;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++
++ /* No matching buffer found? */
++ if (outputBuffer == gcvNULL)
++ {
++ /* Get the tail for the buffer. */
++ outputBuffer = _outputBufferTail;
++
++ /* Move it to the head. */
++ _outputBufferTail = _outputBufferTail->prev;
++ _outputBufferTail->next = gcvNULL;
++
++ outputBuffer->prev = gcvNULL;
++ outputBuffer->next = _outputBufferHead;
++
++ _outputBufferHead->prev = outputBuffer;
++ _outputBufferHead = outputBuffer;
++
++ /* Reset the buffer. */
++ outputBuffer->threadID = ThreadID;
++#if gcdBUFFERED_OUTPUT
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++#endif
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber = 0;
++#endif
++ }
++#else
++ outputBuffer = _outputBufferHead;
++#endif
++
++ return outputBuffer;
++}
++
++static gcmINLINE int _GetArgumentSize(
++ IN gctCONST_STRING Message
++ )
++{
++ int i, count;
++
++ gcmDBGASSERT(Message != gcvNULL, "%p", Message);
++
++ for (i = 0, count = 0; Message[i]; i += 1)
++ {
++ if (Message[i] == '%')
++ {
++ count += 1;
++ }
++ }
++
++ return count * gcmSIZEOF(gctUINT32);
++}
++
++#if gcdHAVEPREFIX
++static void
++_InitPrefixData(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR data = (gctUINT8_PTR) Data;
++
++#if gcdSHOW_TIME
++ {
++ gctUINT64 time;
++ gckOS_GetProfileTick(&time);
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = time;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = OutputBuffer->lineNumber;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_PROCESS_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETPROCESSID();
++ data += gcmSIZEOF(gctUINT32);
++ }
++#endif
++
++#if gcdSHOW_THREAD_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETTHREADID();
++ }
++#endif
++}
++#endif
++
++static void
++_Print(
++ IN gctUINT ArgumentSize,
++ IN gctBOOL CopyMessage,
++ IN gctCONST_STRING Message,
++ IN gctARGUMENTS * Arguments
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++ gcmkDECLARE_LOCK(lockHandle);
++
++ gcmkLOCKSECTION(lockHandle);
++
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Print prefix. */
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print the prefix. */
++ gcdOUTPUTPREFIX(outputBuffer, alignedPrefixData);
++ }
++#endif
++
++ /* Form the indent string. */
++ if (strncmp(Message, "--", 2) == 0)
++ {
++ outputBuffer->indent -= 2;
++ }
++
++ /* Print the message. */
++ if (CopyMessage)
++ {
++ gcdOUTPUTCOPY(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, (gctPOINTER) Arguments
++ );
++ }
++ else
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, ((gctPOINTER) Arguments)
++ );
++ }
++
++ /* Check increasing indent. */
++ if (strncmp(Message, "++", 2) == 0)
++ {
++ outputBuffer->indent += 2;
++ }
++
++ gcmkUNLOCKSECTION(lockHandle);
++}
++
++
++/******************************************************************************\
++********************************* Debug Macros *********************************
++\******************************************************************************/
++
++#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \
++{ \
++ gctARGUMENTS __arguments__; \
++ gcmkARGUMENTS_START(__arguments__, Message); \
++ _Print(ArgumentSize, CopyMessage, Message, &__arguments__); \
++ gcmkARGUMENTS_END(__arguments__); \
++}
++
++
++/******************************************************************************\
++********************************** Debug Code **********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Print
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_PrintN
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyPrint
++**
++** Send a message to the debugger. If in buffered output mode, the entire
++** message will be copied into the buffer instead of using the pointer to
++** the string.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvTRUE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DumpBuffer
++**
++** Print the contents of the specified buffer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Buffer
++** Pointer to the buffer to print.
++**
++** gctUINT Size
++** Size of the buffer.
++**
++** gceDUMP_BUFFER Type
++** Buffer type.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ )
++{
++ gctUINT32 address = 0;
++ gcsBUFFERED_OUTPUT_PTR outputBuffer = gcvNULL;
++ static gctBOOL userLocked;
++ gctCHAR *buffer = (gctCHAR*)Buffer;
++
++ gcmkDECLARE_LOCK(lockHandle);
++
++ /* Request lock when not coming from user,
++ or coming from user and not yet locked
++ and message is starting with @[. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ if ((Size > 2)
++ && (buffer[0] == '@')
++ && (buffer[1] == '['))
++ {
++ /* Beginning of a user dump. */
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvTRUE;
++ }
++ /* Else, let it pass through. */
++ }
++ else
++ {
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++
++ if (Buffer != gcvNULL)
++ {
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Get the physical address of the buffer. */
++ if (Type != gceDUMP_BUFFER_FROM_USER)
++ {
++ gcmkVERIFY_OK(gckOS_GetPhysicalAddress(Os, Buffer, &address));
++ }
++ else
++ {
++ address = 0;
++ }
++
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print/schedule the buffer. */
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ alignedPrefixData, Buffer, address, Size, Type, 0
++ );
++ }
++#else
++ /* Print/schedule the buffer. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Buffer, 0, gcvNULL
++ );
++ }
++ else
++ {
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ gcvNULL, Buffer, address, Size, Type, 0
++ );
++ }
++#endif
++ }
++
++ /* Unlock when not coming from user,
++ or coming from user and not yet locked. */
++ if (userLocked)
++ {
++ if ((Size > 4)
++ && (buffer[0] == ']')
++ && (buffer[1] == ' ')
++ && (buffer[2] == '-')
++ && (buffer[3] == '-'))
++ {
++ /* End of a user dump. */
++ gcmkUNLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++ /* Else, let it pass through, don't unlock. */
++ }
++ else
++ {
++ gcmkUNLOCKSECTION(lockHandle);
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTrace
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceN
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZone
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZoneN
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugBreak
++**
++** Break into the debugger.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugBreak(
++ void
++ )
++{
++ gckOS_DebugTrace(gcvLEVEL_ERROR, "%s(%d)", __FUNCTION__, __LINE__);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFatal
++**
++** Send a message to the debugger and break into the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmkPRINT_VERSION();
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++
++ /* Break into the debugger. */
++ gckOS_DebugBreak();
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevel
++**
++** Set the debug level.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ )
++{
++ _debugLevel = Level;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZone
++**
++** Set the debug zone.
++**
++** INPUT:
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ )
++{
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevelZone
++**
++** Set the debug level and zone.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ )
++{
++ _debugLevel = Level;
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZones
++**
++** Enable or disable debug zones.
++**
++** INPUT:
++**
++** gctUINT32 Zones
++** Debug zones to enable or disable.
++**
++** gctBOOL Enable
++** Set to gcvTRUE to enable the zones (or the Zones with the current
++** zones) or gcvFALSE to disable the specified Zones.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ )
++{
++ if (Enable)
++ {
++ /* Enable the zones. */
++ _debugZones |= Zones;
++ }
++ else
++ {
++ /* Disable the zones. */
++ _debugZones &= ~Zones;
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_Verify
++**
++** Called to verify the result of a function call.
++**
++** INPUT:
++**
++** gceSTATUS Status
++** Function call result.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Verify(
++ IN gceSTATUS status
++ )
++{
++ _lastError = status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFlush
++**
++** Force messages to be flushed out.
++**
++** INPUT:
++**
++** gctCONST_STRING CallerName
++** Name of the caller function.
++**
++** gctUINT LineNumber
++** Line number of the caller.
++**
++** gctUINT32 DmaAddress
++** The current DMA address or ~0U to ignore.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ )
++{
++#if gcdBUFFERED_OUTPUT
++ _DirectPrint("\nFlush requested by %s(%d).\n\n", CallerName, LineNumber);
++ _Flush(DmaAddress);
++#endif
++}
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ )
++{
++ switch (status)
++ {
++ case gcvSTATUS_OK:
++ return "gcvSTATUS_OK";
++ case gcvSTATUS_TRUE:
++ return "gcvSTATUS_TRUE";
++ case gcvSTATUS_NO_MORE_DATA:
++ return "gcvSTATUS_NO_MORE_DATA";
++ case gcvSTATUS_CACHED:
++ return "gcvSTATUS_CACHED";
++ case gcvSTATUS_MIPMAP_TOO_LARGE:
++ return "gcvSTATUS_MIPMAP_TOO_LARGE";
++ case gcvSTATUS_NAME_NOT_FOUND:
++ return "gcvSTATUS_NAME_NOT_FOUND";
++ case gcvSTATUS_NOT_OUR_INTERRUPT:
++ return "gcvSTATUS_NOT_OUR_INTERRUPT";
++ case gcvSTATUS_MISMATCH:
++ return "gcvSTATUS_MISMATCH";
++ case gcvSTATUS_MIPMAP_TOO_SMALL:
++ return "gcvSTATUS_MIPMAP_TOO_SMALL";
++ case gcvSTATUS_LARGER:
++ return "gcvSTATUS_LARGER";
++ case gcvSTATUS_SMALLER:
++ return "gcvSTATUS_SMALLER";
++ case gcvSTATUS_CHIP_NOT_READY:
++ return "gcvSTATUS_CHIP_NOT_READY";
++ case gcvSTATUS_NEED_CONVERSION:
++ return "gcvSTATUS_NEED_CONVERSION";
++ case gcvSTATUS_SKIP:
++ return "gcvSTATUS_SKIP";
++ case gcvSTATUS_DATA_TOO_LARGE:
++ return "gcvSTATUS_DATA_TOO_LARGE";
++ case gcvSTATUS_INVALID_CONFIG:
++ return "gcvSTATUS_INVALID_CONFIG";
++ case gcvSTATUS_CHANGED:
++ return "gcvSTATUS_CHANGED";
++ case gcvSTATUS_NOT_SUPPORT_DITHER:
++ return "gcvSTATUS_NOT_SUPPORT_DITHER";
++
++ case gcvSTATUS_INVALID_ARGUMENT:
++ return "gcvSTATUS_INVALID_ARGUMENT";
++ case gcvSTATUS_INVALID_OBJECT:
++ return "gcvSTATUS_INVALID_OBJECT";
++ case gcvSTATUS_OUT_OF_MEMORY:
++ return "gcvSTATUS_OUT_OF_MEMORY";
++ case gcvSTATUS_MEMORY_LOCKED:
++ return "gcvSTATUS_MEMORY_LOCKED";
++ case gcvSTATUS_MEMORY_UNLOCKED:
++ return "gcvSTATUS_MEMORY_UNLOCKED";
++ case gcvSTATUS_HEAP_CORRUPTED:
++ return "gcvSTATUS_HEAP_CORRUPTED";
++ case gcvSTATUS_GENERIC_IO:
++ return "gcvSTATUS_GENERIC_IO";
++ case gcvSTATUS_INVALID_ADDRESS:
++ return "gcvSTATUS_INVALID_ADDRESS";
++ case gcvSTATUS_CONTEXT_LOSSED:
++ return "gcvSTATUS_CONTEXT_LOSSED";
++ case gcvSTATUS_TOO_COMPLEX:
++ return "gcvSTATUS_TOO_COMPLEX";
++ case gcvSTATUS_BUFFER_TOO_SMALL:
++ return "gcvSTATUS_BUFFER_TOO_SMALL";
++ case gcvSTATUS_INTERFACE_ERROR:
++ return "gcvSTATUS_INTERFACE_ERROR";
++ case gcvSTATUS_NOT_SUPPORTED:
++ return "gcvSTATUS_NOT_SUPPORTED";
++ case gcvSTATUS_MORE_DATA:
++ return "gcvSTATUS_MORE_DATA";
++ case gcvSTATUS_TIMEOUT:
++ return "gcvSTATUS_TIMEOUT";
++ case gcvSTATUS_OUT_OF_RESOURCES:
++ return "gcvSTATUS_OUT_OF_RESOURCES";
++ case gcvSTATUS_INVALID_DATA:
++ return "gcvSTATUS_INVALID_DATA";
++ case gcvSTATUS_INVALID_MIPMAP:
++ return "gcvSTATUS_INVALID_MIPMAP";
++ case gcvSTATUS_NOT_FOUND:
++ return "gcvSTATUS_NOT_FOUND";
++ case gcvSTATUS_NOT_ALIGNED:
++ return "gcvSTATUS_NOT_ALIGNED";
++ case gcvSTATUS_INVALID_REQUEST:
++ return "gcvSTATUS_INVALID_REQUEST";
++ case gcvSTATUS_GPU_NOT_RESPONDING:
++ return "gcvSTATUS_GPU_NOT_RESPONDING";
++ case gcvSTATUS_TIMER_OVERFLOW:
++ return "gcvSTATUS_TIMER_OVERFLOW";
++ case gcvSTATUS_VERSION_MISMATCH:
++ return "gcvSTATUS_VERSION_MISMATCH";
++ case gcvSTATUS_LOCKED:
++ return "gcvSTATUS_LOCKED";
++ case gcvSTATUS_INTERRUPTED:
++ return "gcvSTATUS_INTERRUPTED";
++ case gcvSTATUS_DEVICE:
++ return "gcvSTATUS_DEVICE";
++ case gcvSTATUS_NOT_MULTI_PIPE_ALIGNED:
++ return "gcvSTATUS_NOT_MULTI_PIPE_ALIGNED";
++
++ /* Linker errors. */
++ case gcvSTATUS_GLOBAL_TYPE_MISMATCH:
++ return "gcvSTATUS_GLOBAL_TYPE_MISMATCH";
++ case gcvSTATUS_TOO_MANY_ATTRIBUTES:
++ return "gcvSTATUS_TOO_MANY_ATTRIBUTES";
++ case gcvSTATUS_TOO_MANY_UNIFORMS:
++ return "gcvSTATUS_TOO_MANY_UNIFORMS";
++ case gcvSTATUS_TOO_MANY_SAMPLER:
++ return "gcvSTATUS_TOO_MANY_SAMPLER";
++ case gcvSTATUS_TOO_MANY_VARYINGS:
++ return "gcvSTATUS_TOO_MANY_VARYINGS";
++ case gcvSTATUS_UNDECLARED_VARYING:
++ return "gcvSTATUS_UNDECLARED_VARYING";
++ case gcvSTATUS_VARYING_TYPE_MISMATCH:
++ return "gcvSTATUS_VARYING_TYPE_MISMATCH";
++ case gcvSTATUS_MISSING_MAIN:
++ return "gcvSTATUS_MISSING_MAIN";
++ case gcvSTATUS_NAME_MISMATCH:
++ return "gcvSTATUS_NAME_MISMATCH";
++ case gcvSTATUS_INVALID_INDEX:
++ return "gcvSTATUS_INVALID_INDEX";
++ case gcvSTATUS_UNIFORM_MISMATCH:
++ return "gcvSTATUS_UNIFORM_MISMATCH";
++ case gcvSTATUS_UNSAT_LIB_SYMBOL:
++ return "gcvSTATUS_UNSAT_LIB_SYMBOL";
++ case gcvSTATUS_TOO_MANY_SHADERS:
++ return "gcvSTATUS_TOO_MANY_SHADERS";
++ case gcvSTATUS_LINK_INVALID_SHADERS:
++ return "gcvSTATUS_LINK_INVALID_SHADERS";
++ case gcvSTATUS_CS_NO_WORKGROUP_SIZE:
++ return "gcvSTATUS_CS_NO_WORKGROUP_SIZE";
++ case gcvSTATUS_LINK_LIB_ERROR:
++ return "gcvSTATUS_LINK_LIB_ERROR";
++ case gcvSTATUS_SHADER_VERSION_MISMATCH:
++ return "gcvSTATUS_SHADER_VERSION_MISMATCH";
++ case gcvSTATUS_TOO_MANY_INSTRUCTION:
++ return "gcvSTATUS_TOO_MANY_INSTRUCTION";
++ case gcvSTATUS_SSBO_MISMATCH:
++ return "gcvSTATUS_SSBO_MISMATCH";
++ case gcvSTATUS_TOO_MANY_OUTPUT:
++ return "gcvSTATUS_TOO_MANY_OUTPUT";
++ case gcvSTATUS_TOO_MANY_INPUT:
++ return "gcvSTATUS_TOO_MANY_INPUT";
++ case gcvSTATUS_NOT_SUPPORT_CL:
++ return "gcvSTATUS_NOT_SUPPORT_CL";
++ case gcvSTATUS_NOT_SUPPORT_INTEGER:
++ return "gcvSTATUS_NOT_SUPPORT_INTEGER";
++
++ /* Compiler errors. */
++ case gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR:
++ return "gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR";
++ case gcvSTATUS_COMPILER_FE_PARSER_ERROR:
++ return "gcvSTATUS_COMPILER_FE_PARSER_ERROR";
++
++ default:
++ return "nil";
++ }
++}
++
++/*******************************************************************************
++***** Binary Trace *************************************************************
++*******************************************************************************/
++
++/*******************************************************************************
++** _VerifyMessage
++**
++** Verify a binary trace message, decode it to human readable string and print
++** it.
++**
++** ARGUMENTS:
++**
++** gctCONST_STRING Buffer
++** Pointer to buffer to store.
++**
++** gctSIZE_T Bytes
++** Buffer length.
++*/
++void
++_VerifyMessage(
++ IN gctCONST_STRING Buffer,
++ IN gctSIZE_T Bytes
++ )
++{
++ char arguments[150] = {0};
++ char format[100] = {0};
++
++ gctSTRING function;
++ gctPOINTER args;
++ gctUINT32 numArguments;
++ int i = 0;
++ gctUINT32 functionBytes;
++
++ gcsBINARY_TRACE_MESSAGE_PTR message = (gcsBINARY_TRACE_MESSAGE_PTR)Buffer;
++
++ /* Check signature. */
++ if (message->signature != 0x7FFFFFFF)
++ {
++ gcmkPRINT("Signature error");
++ return;
++ }
++
++ /* Get function name. */
++ function = (gctSTRING)&message->payload;
++ functionBytes = (gctUINT32)strlen(function) + 1;
++
++ /* Get arguments number. */
++ numArguments = message->numArguments;
++
++ /* Get arguments . */
++ args = function + functionBytes;
++
++ /* Prepare format string. */
++ while (numArguments--)
++ {
++ format[i++] = '%';
++ format[i++] = 'x';
++ format[i++] = ' ';
++ }
++
++ format[i] = '\0';
++
++ if (numArguments)
++ {
++ gcmkVSPRINTF(arguments, 150, format, (gctARGUMENTS *) &args);
++ }
++
++ gcmkPRINT("[%d](%d): %s(%d) %s",
++ message->pid,
++ message->tid,
++ function,
++ message->line,
++ arguments);
++}
++
++
++/*******************************************************************************
++** gckOS_WriteToRingBuffer
++**
++** Store a buffer to ring buffer.
++**
++** ARGUMENTS:
++**
++** gctCONST_STRING Buffer
++** Pointer to buffer to store.
++**
++** gctSIZE_T Bytes
++** Buffer length.
++*/
++void
++gckOS_WriteToRingBuffer(
++ IN gctCONST_STRING Buffer,
++ IN gctSIZE_T Bytes
++ )
++{
++
++}
++
++/*******************************************************************************
++** gckOS_BinaryTrace
++**
++** Output a binary trace message.
++**
++** ARGUMENTS:
++**
++** gctCONST_STRING Function
++** Pointer to function name.
++**
++** gctINT Line
++** Line number.
++**
++** gctCONST_STRING Text OPTIONAL
++** Optional pointer to a descriptive text.
++**
++** ...
++** Optional arguments to the descriptive text.
++*/
++void
++gckOS_BinaryTrace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text OPTIONAL,
++ ...
++ )
++{
++ static gctUINT32 messageSignature = 0x7FFFFFFF;
++ char buffer[gcdBINARY_TRACE_MESSAGE_SIZE];
++ gctUINT32 numArguments = 0;
++ gctUINT32 functionBytes;
++ gctUINT32 i = 0;
++ gctSTRING payload;
++ gcsBINARY_TRACE_MESSAGE_PTR message = (gcsBINARY_TRACE_MESSAGE_PTR)buffer;
++
++ /* Calculate arguments number. */
++ if (Text)
++ {
++ while (Text[i] != '\0')
++ {
++ if (Text[i] == '%')
++ {
++ numArguments++;
++ }
++ i++;
++ }
++ }
++
++ message->signature = messageSignature;
++ message->pid = gcmkGETPROCESSID();
++ message->tid = gcmkGETTHREADID();
++ message->line = Line;
++ message->numArguments = numArguments;
++
++ payload = (gctSTRING)&message->payload;
++
++ /* Function name. */
++ functionBytes = (gctUINT32)gcmkSTRLEN(Function) + 1;
++ gcmkMEMCPY(payload, Function, functionBytes);
++
++ /* Advance to next payload. */
++ payload += functionBytes;
++
++ /* Arguments value. */
++ if (numArguments)
++ {
++ gctARGUMENTS p;
++ gcmkARGUMENTS_START(p, Text);
++
++ for (i = 0; i < numArguments; ++i)
++ {
++ gctPOINTER value = gcmkARGUMENTS_ARG(p, gctPOINTER);
++ gcmkMEMCPY(payload, &value, gcmSIZEOF(gctPOINTER));
++ payload += gcmSIZEOF(gctPOINTER);
++ }
++
++ gcmkARGUMENTS_END(p);
++ }
++
++ gcmkASSERT(payload - buffer <= gcdBINARY_TRACE_MESSAGE_SIZE);
++
++
++ /* Send buffer to ring buffer. */
++ gckOS_WriteToRingBuffer(buffer, (gctUINT32)(payload - buffer));
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debugfs.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debugfs.c 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,1137 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifdef MODULE
++#include <linux/module.h>
++#endif
++#include <linux/init.h>
++#include <linux/debugfs.h>
++#include <linux/slab.h>
++#ifdef MODVERSIONS
++#include <linux/modversions.h>
++#endif
++#include <linux/stddef.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/mutex.h>
++#include <linux/vmalloc.h>
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/poll.h>
++#include <asm/uaccess.h>
++#include <linux/completion.h>
++#include <linux/seq_file.h>
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel.h"
++
++/*
++ Prequsite:
++
++ 1) Debugfs feature must be enabled in the kernel.
++ 1.a) You can enable this, in the compilation of the uImage, all you have to do is, In the "make menuconfig" part,
++ you have to enable the debugfs in the kernel hacking part of the menu.
++
++ HOW TO USE:
++ 1) insert the driver with the following option logFileSize, Ex: insmod galcore.ko ...... logFileSize=10240
++ This gives a circular buffer of 10 MB
++
++ 2)Usually after inserting the driver, the debug file system is mounted under /sys/kernel/debug/
++
++ 2.a)If the debugfs is not mounted, you must do "mount -t debugfs none /sys/kernel/debug"
++
++ 3) To read what is being printed in the debugfs file system:
++ Ex : cat /sys/kernel/debug/gc/galcore_trace
++
++ 4)To write into the debug file system from user side :
++ Ex: echo "hello" > cat /sys/kernel/debug/gc/galcore_trace
++
++ 5)To write into debugfs from kernel side, Use the function called gckDEBUGFS_Print
++
++ How to Get Video Memory Usage:
++ 1) Select a process whose video memory usage can be dump, no need to reset it until <pid> is needed to be change.
++ echo <pid> > /sys/kernel/debug/gc/vidmem
++
++ 2) Get video memory usage.
++ cat /sys/kernel/debug/gc/vidmem
++
++ USECASE Kernel Dump:
++
++ 1) Go to /hal/inc/gc_hal_options.h, and enable the following flags:
++ - # define gcdDUMP 1
++ - # define gcdDUMP_IN_KERNEL 1
++ - # define gcdDUMP_COMMAND 1
++
++ 2) Go to /hal/kernel/gc_hal_kernel_command.c and disable the following flag
++ -#define gcdSIMPLE_COMMAND_DUMP 0
++
++ 3) Compile the driver
++ 4) insmod it with the logFileSize option
++ 5) Run an application
++ 6) You can get the dump by cat /sys/kernel/debug/gpu/galcore_trace
++
++ */
++
++/**/
++typedef va_list gctDBGARGS ;
++#define gcmkARGS_START(argument, pointer) va_start(argument, pointer)
++#define gcmkARGS_END(argument) va_end(argument)
++
++#define gcmkDEBUGFS_PRINT(ArgumentSize, Message) \
++ { \
++ gctDBGARGS __arguments__; \
++ gcmkARGS_START(__arguments__, Message); \
++ _debugfs_res = _DebugFSPrint(ArgumentSize, Message, &__arguments__);\
++ gcmkARGS_END(__arguments__); \
++ }
++
++/* Debug File System Node Struct. */
++struct _gcsDEBUGFS_Node
++{
++ /*wait queues for read and write operations*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ wait_queue_head_t read_q , write_q ;
++#else
++ struct wait_queue *read_q , *write_q ;
++#endif
++ struct dentry *parent ; /*parent directory*/
++ struct dentry *filen ; /*filename*/
++ struct dentry *vidmem;
++ struct semaphore sem ; /* mutual exclusion semaphore */
++ char *data ; /* The circular buffer data */
++ int size ; /* Size of the buffer pointed to by 'data' */
++ int refcount ; /* Files that have this buffer open */
++ int read_point ; /* Offset in circ. buffer of oldest data */
++ int write_point ; /* Offset in circ. buffer of newest data */
++ int offset ; /* Byte number of read_point in the stream */
++ struct _gcsDEBUGFS_Node *next ;
++};
++
++/* amount of data in the queue */
++#define gcmkNODE_QLEN(node) ( (node)->write_point >= (node)->read_point ? \
++ (node)->write_point - (node)->read_point : \
++ (node)->size - (node)->read_point + (node)->write_point)
++
++/* byte number of the last byte in the queue */
++#define gcmkNODE_FIRST_EMPTY_BYTE(node) ((node)->offset + gcmkNODE_QLEN(node))
++
++/*Synchronization primitives*/
++#define gcmkNODE_READQ(node) (&((node)->read_q))
++#define gcmkNODE_WRITEQ(node) (&((node)->write_q))
++
++/*Utilities*/
++#define gcmkMIN(x, y) ((x) < (y) ? (x) : y)
++
++/*Debug File System Struct*/
++typedef struct _gcsDEBUGFS_
++{
++ gcsDEBUGFS_Node* linkedlist ;
++ gcsDEBUGFS_Node* currentNode ;
++ int isInited ;
++} gcsDEBUGFS_ ;
++
++/*debug file system*/
++static gcsDEBUGFS_ gc_dbgfs ;
++
++static int gc_debugfs_open(struct inode *inode, struct file *file)
++{
++ gcsINFO_NODE *node = inode->i_private;
++
++ return single_open(file, node->info->show, node);
++}
++
++static const struct file_operations gc_debugfs_operations = {
++ .owner = THIS_MODULE,
++ .open = gc_debugfs_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++gceSTATUS
++gckDEBUGFS_DIR_Init(
++ IN gckDEBUGFS_DIR Dir,
++ IN struct dentry *root,
++ IN gctCONST_STRING Name
++ )
++{
++ Dir->root = debugfs_create_dir(Name, root);
++
++ if (!Dir->root)
++ {
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ INIT_LIST_HEAD(&Dir->nodeList);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDEBUGFS_DIR_CreateFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count,
++ IN gctPOINTER Data
++ )
++{
++ int i;
++ gcsINFO_NODE * node;
++ gceSTATUS status;
++
++ for (i = 0; i < count; i++)
++ {
++ /* Create a node. */
++ node = (gcsINFO_NODE *)kzalloc(sizeof(gcsINFO_NODE), GFP_KERNEL);
++
++ node->info = &List[i];
++ node->device = Data;
++
++ /* Bind to a file. TODO: clean up when fail. */
++ node->entry = debugfs_create_file(
++ List[i].name, S_IRUGO|S_IWUSR, Dir->root, node, &gc_debugfs_operations);
++
++ if (!node->entry)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ list_add(&(node->head), &(Dir->nodeList));
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(Dir, List, count));
++ return status;
++}
++
++gceSTATUS
++gckDEBUGFS_DIR_RemoveFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count
++ )
++{
++ int i;
++ gcsINFO_NODE * node;
++ gcsINFO_NODE * temp;
++
++ for (i = 0; i < count; i++)
++ {
++ list_for_each_entry_safe(node, temp, &Dir->nodeList, head)
++ {
++ if (node->info == &List[i])
++ {
++ debugfs_remove(node->entry);
++ list_del(&node->head);
++ kfree(node);
++ }
++ }
++ }
++
++ return gcvSTATUS_OK;
++}
++
++void
++gckDEBUGFS_DIR_Deinit(
++ IN gckDEBUGFS_DIR Dir
++ )
++{
++ if (Dir->root != NULL)
++ {
++ debugfs_remove(Dir->root);
++ Dir->root = NULL;
++ }
++}
++
++/*******************************************************************************
++ **
++ ** READ & WRITE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _ReadFromNode
++ **
++ ** 1) reading bytes out of a circular buffer with wraparound.
++ ** 2)returns caddr_t, pointer to data read, which the caller must free.
++ ** 3) length is (a pointer to) the number of bytes to be read, which will be set by this function to
++ ** be the number of bytes actually returned
++ **
++ *******************************************************************************/
++static caddr_t
++_ReadFromNode (
++ gcsDEBUGFS_Node* Node ,
++ size_t *Length ,
++ loff_t *Offset
++ )
++{
++ caddr_t retval ;
++ int bytes_copied = 0 , n , start_point , remaining ;
++
++ /* is the user trying to read data that has already scrolled off? */
++ if ( *Offset < Node->offset )
++ {
++ *Offset = Node->offset ;
++ }
++
++ /* is the user trying to read past EOF? */
++ if ( *Offset >= gcmkNODE_FIRST_EMPTY_BYTE ( Node ) )
++ {
++ return NULL ;
++ }
++
++ /* find the smaller of the total bytes we have available and what
++ * the user is asking for */
++
++ *Length = gcmkMIN ( *Length , gcmkNODE_FIRST_EMPTY_BYTE ( Node ) - *Offset ) ;
++
++ remaining = * Length ;
++
++ /* figure out where to start based on user's Offset */
++ start_point = Node->read_point + ( *Offset - Node->offset ) ;
++
++ start_point = start_point % Node->size ;
++
++ /* allocate memory to return */
++ if ( ( retval = kmalloc ( sizeof (char ) * remaining , GFP_KERNEL ) ) == NULL )
++ return NULL ;
++
++ /* copy the (possibly noncontiguous) data to our buffer */
++ while ( remaining )
++ {
++ n = gcmkMIN ( remaining , Node->size - start_point ) ;
++ memcpy ( retval + bytes_copied , Node->data + start_point , n ) ;
++ bytes_copied += n ;
++ remaining -= n ;
++ start_point = ( start_point + n ) % Node->size ;
++ }
++
++ /* advance user's file pointer */
++ *Offset += * Length ;
++
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ ** _WriteToNode
++ **
++ ** 1) writes to a circular buffer with wraparound.
++ ** 2)in case of an overflow, it overwrites the oldest unread data.
++ **
++ *********************************************************************************/
++static void
++_WriteToNode (
++ gcsDEBUGFS_Node* Node ,
++ caddr_t Buf ,
++ int Length
++ )
++{
++ int bytes_copied = 0 ;
++ int overflow = 0 ;
++ int n ;
++
++ if ( Length + gcmkNODE_QLEN ( Node ) >= ( Node->size - 1 ) )
++ {
++ overflow = 1 ;
++
++ /* in case of overflow, figure out where the new buffer will
++ * begin. we start by figuring out where the current buffer ENDS:
++ * node->parent->offset + gcmkNODE_QLEN. we then advance the end-offset
++ * by the Length of the current write, and work backwards to
++ * figure out what the oldest unoverwritten data will be (i.e.,
++ * size of the buffer). */
++ Node->offset = Node->offset + gcmkNODE_QLEN ( Node ) + Length
++ - Node->size + 1 ;
++ }
++
++ while ( Length )
++ {
++ /* how many contiguous bytes are available from the write point to
++ * the end of the circular buffer? */
++ n = gcmkMIN ( Length , Node->size - Node->write_point ) ;
++ memcpy ( Node->data + Node->write_point , Buf + bytes_copied , n ) ;
++ bytes_copied += n ;
++ Length -= n ;
++ Node->write_point = ( Node->write_point + n ) % Node->size ;
++ }
++
++ /* if there is an overflow, reset the read point to read whatever is
++ * the oldest data that we have, that has not yet been
++ * overwritten. */
++ if ( overflow )
++ {
++ Node->read_point = ( Node->write_point + 1 ) % Node->size ;
++ }
++}
++
++/*******************************************************************************
++ **
++ ** PRINTING UTILITY (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _GetArgumentSize
++ **
++ **
++ *******************************************************************************/
++static gctINT
++_GetArgumentSize (
++ IN gctCONST_STRING Message
++ )
++{
++ gctINT i , count ;
++
++ for ( i = 0 , count = 0 ; Message[i] ; i += 1 )
++ {
++ if ( Message[i] == '%' )
++ {
++ count += 1 ;
++ }
++ }
++ return count * sizeof (unsigned int ) ;
++}
++
++/*******************************************************************************
++ **
++ ** _AppendString
++ **
++ **
++ *******************************************************************************/
++static ssize_t
++_AppendString (
++ IN gcsDEBUGFS_Node* Node ,
++ IN gctCONST_STRING String ,
++ IN int Length
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( Length , Node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_ATOMIC ) ) == NULL )
++ return - ENOMEM ;
++
++ /* copy into our temp buffer */
++ memcpy ( message , String , n ) ;
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( Node , message , n ) ;
++ kfree ( message ) ;
++ return n ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSPrint
++ **
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSPrint (
++ IN unsigned int ArgumentSize ,
++ IN const char* Message ,
++ IN gctDBGARGS * Arguments
++
++ )
++{
++ char buffer[MAX_LINE_SIZE] ;
++ int len ;
++ ssize_t res=0;
++
++ if(in_interrupt())
++ {
++ return - ERESTARTSYS ;
++ }
++
++ len = vsnprintf ( buffer , sizeof (buffer ) , Message , *( va_list * ) Arguments ) ;
++ buffer[len] = '\0' ;
++
++ /* Add end-of-line if missing. */
++ if ( buffer[len - 1] != '\n' )
++ {
++ buffer[len ++] = '\n' ;
++ buffer[len] = '\0' ;
++ }
++ res = _AppendString ( gc_dbgfs.currentNode , buffer , len ) ;
++ wake_up ( gcmkNODE_READQ ( gc_dbgfs.currentNode ) ) ; /* blocked in read*/
++ return res;
++}
++
++/*******************************************************************************
++ **
++ ** LINUX SYSTEM FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** find the vivlog structure associated with an inode.
++ ** returns a pointer to the structure if found, NULL if not found
++ **
++ *******************************************************************************/
++static gcsDEBUGFS_Node*
++_GetNodeInfo (
++ IN struct inode *Inode
++ )
++{
++ gcsDEBUGFS_Node* node ;
++
++ if ( Inode == NULL )
++ return NULL ;
++
++ for ( node = gc_dbgfs.linkedlist ; node != NULL ; node = node->next )
++ if ( node->filen->d_inode->i_ino == Inode->i_ino )
++ return node ;
++
++ return NULL ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSRead
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSRead (
++ struct file *file ,
++ char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ int retval ;
++ caddr_t data_to_return ;
++ gcsDEBUGFS_Node* node ;
++ /* get the metadata about this emlog */
++ if ( ( node = _GetNodeInfo ( file->f_path.dentry->d_inode ) ) == NULL )
++ {
++ printk ( "debugfs_read: record not found\n" ) ;
++ return - EIO ;
++ }
++
++ /* wait until there's data available (unless we do nonblocking reads) */
++ while ( *offset >= gcmkNODE_FIRST_EMPTY_BYTE ( node ) )
++ {
++ if ( file->f_flags & O_NONBLOCK )
++ {
++ return - EAGAIN ;
++ }
++ if ( wait_event_interruptible ( ( *( gcmkNODE_READQ ( node ) ) ) , ( *offset < gcmkNODE_FIRST_EMPTY_BYTE ( node ) ) ) )
++ {
++ return - ERESTARTSYS ; /* signal: tell the fs layer to handle it */
++ }
++ }
++ data_to_return = _ReadFromNode ( node , &length , offset ) ;
++ if ( data_to_return == NULL )
++ {
++ retval = 0 ;
++ goto unlock ;
++ }
++ if ( copy_to_user ( buffer , data_to_return , length ) > 0 )
++ {
++ retval = - EFAULT ;
++ }
++ else
++ {
++ retval = length ;
++ }
++ kfree ( data_to_return ) ;
++unlock:
++ wake_up_interruptible ( gcmkNODE_WRITEQ ( node ) ) ;
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ **_DebugFSWrite
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSWrite (
++ struct file *file ,
++ const char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++ gcsDEBUGFS_Node*node ;
++
++ /* get the metadata about this log */
++ if ( ( node = _GetNodeInfo ( file->f_path.dentry->d_inode ) ) == NULL )
++ {
++ return - EIO ;
++ }
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( length , node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL )
++ {
++ return - ENOMEM ;
++ }
++
++
++ /* copy into our temp buffer */
++ if ( copy_from_user ( message , buffer , n ) > 0 )
++ {
++ kfree ( message ) ;
++ return - EFAULT ;
++ }
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( node , message , n ) ;
++
++ kfree ( message ) ;
++
++ /* wake up any readers that might be waiting for the data. we call
++ * schedule in the vague hope that a reader will run before the
++ * writer's next write, to avoid losing data. */
++ wake_up_interruptible ( gcmkNODE_READQ ( node ) ) ;
++
++ return n ;
++}
++
++int dumpProcess = 0;
++
++void
++_PrintCounter(
++ struct seq_file *file,
++ gcsDATABASE_COUNTERS * counter,
++ gctCONST_STRING Name
++ )
++{
++ seq_printf(file,"Counter: %s\n", Name);
++
++ seq_printf(file,"%-9s%10s","", "All");
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Current");
++
++ seq_printf(file,"%10lld", counter->bytes);
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Maximum");
++
++ seq_printf(file,"%10lld", counter->maxBytes);
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Total");
++
++ seq_printf(file,"%10lld", counter->totalBytes);
++
++ seq_printf(file, "\n");
++}
++
++void
++_ShowCounters(
++ struct seq_file *file,
++ gcsDATABASE_PTR database
++ )
++{
++ gctUINT i = 0;
++ gcsDATABASE_COUNTERS * counter;
++ gcsDATABASE_COUNTERS * nonPaged;
++
++ static gctCONST_STRING surfaceTypes[] = {
++ "UNKNOWN",
++ "Index",
++ "Vertex",
++ "Texture",
++ "RT",
++ "Depth",
++ "Bitmap",
++ "TS",
++ "Image",
++ "Mask",
++ "Scissor",
++ "HZDepth",
++ };
++
++ /* Get pointer to counters. */
++ counter = &database->vidMem;
++
++ nonPaged = &database->nonPaged;
++
++ seq_printf(file,"Counter: vidMem (for each surface type)\n");
++
++ seq_printf(file,"%-9s%10s","", "All");
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file, "%10s",surfaceTypes[i]);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Current");
++
++ seq_printf(file,"%10lld", database->vidMem.bytes);
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file,"%10lld", counter->bytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Maximum");
++
++ seq_printf(file,"%10lld", database->vidMem.maxBytes);
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file,"%10lld", counter->maxBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Total");
++
++ seq_printf(file,"%10lld", database->vidMem.totalBytes);
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file,"%10lld", counter->totalBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"Counter: vidMem (for each pool)\n");
++
++ seq_printf(file,"%-9s%10s","", "All");
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ seq_printf(file, "%10d", i);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Current");
++
++ seq_printf(file,"%10lld", database->vidMem.bytes);
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ counter = &database->vidMemPool[i];
++
++ seq_printf(file,"%10lld", counter->bytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Maximum");
++
++ seq_printf(file,"%10lld", database->vidMem.maxBytes);
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ counter = &database->vidMemPool[i];
++
++ seq_printf(file,"%10lld", counter->maxBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Total");
++
++ seq_printf(file,"%10lld", database->vidMem.totalBytes);
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ counter = &database->vidMemPool[i];
++
++ seq_printf(file,"%10lld", counter->totalBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ /* Print nonPaged. */
++ _PrintCounter(file, &database->nonPaged, "nonPaged");
++ _PrintCounter(file, &database->contiguous, "contiguous");
++ _PrintCounter(file, &database->mapUserMemory, "mapUserMemory");
++ _PrintCounter(file, &database->mapMemory, "mapMemory");
++}
++
++gckKERNEL
++_GetValidKernel(
++ gckGALDEVICE Device
++);
++static int vidmem_show(struct seq_file *file, void *unused)
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gckGALDEVICE device = file->private;
++
++ gckKERNEL kernel = _GetValidKernel(device);
++ if(kernel == gcvNULL)
++ {
++ return 0;
++ }
++
++ /* Find the database. */
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(kernel, dumpProcess, gcvFALSE, &database));
++
++ seq_printf(file, "VidMem Usage (Process %d):\n", dumpProcess);
++
++ _ShowCounters(file, database);
++
++ return 0;
++
++OnError:
++ return 0;
++}
++
++static int
++vidmem_open(
++ struct inode *inode,
++ struct file *file
++ )
++{
++ return single_open(file, vidmem_show, inode->i_private);
++}
++
++static ssize_t
++vidmem_write(
++ struct file *file,
++ const char __user *buf,
++ size_t count,
++ loff_t *pos
++ )
++{
++ dumpProcess = simple_strtol(buf, NULL, 0);
++ return count;
++}
++
++/*******************************************************************************
++ **
++ ** File Operations Table
++ **
++ *******************************************************************************/
++static const struct file_operations debugfs_operations = {
++ .owner = THIS_MODULE ,
++ .read = _DebugFSRead ,
++ .write = _DebugFSWrite ,
++} ;
++
++static const struct file_operations vidmem_operations = {
++ .owner = THIS_MODULE ,
++ .open = vidmem_open,
++ .read = seq_read,
++ .write = vidmem_write,
++ .llseek = seq_lseek,
++} ;
++
++/*******************************************************************************
++ **
++ ** INTERFACE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_IsEnabled
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++
++gctINT
++gckDEBUGFS_IsEnabled ( void )
++{
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_Initialize
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDEBUGFS_Initialize ( void )
++{
++ if ( ! gc_dbgfs.isInited )
++ {
++ gc_dbgfs.linkedlist = gcvNULL ;
++ gc_dbgfs.currentNode = gcvNULL ;
++ gc_dbgfs.isInited = 1 ;
++ }
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_Terminate
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDEBUGFS_Terminate ( void )
++{
++ gcsDEBUGFS_Node * next = gcvNULL ;
++ gcsDEBUGFS_Node * temp = gcvNULL ;
++ if ( gc_dbgfs.isInited )
++ {
++ temp = gc_dbgfs.linkedlist ;
++ while ( temp != gcvNULL )
++ {
++ next = temp->next ;
++ gckDEBUGFS_FreeNode ( temp ) ;
++ kfree ( temp ) ;
++ temp = next ;
++ }
++ gc_dbgfs.isInited = 0 ;
++ }
++ return 0 ;
++}
++
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_CreateNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ ** gckDEBUGFS_FreeNode * Device
++ ** Pointer to a variable receiving the gcsDEBUGFS_Node object pointer on
++ ** success.
++ *********************************************************************************/
++
++gctINT
++gckDEBUGFS_CreateNode (
++ IN gctPOINTER Device,
++ IN gctINT SizeInKB ,
++ IN struct dentry * Root ,
++ IN gctCONST_STRING NodeName ,
++ OUT gcsDEBUGFS_Node **Node
++ )
++{
++ gcsDEBUGFS_Node*node ;
++ /* allocate space for our metadata and initialize it */
++ if ( ( node = kmalloc ( sizeof (gcsDEBUGFS_Node ) , GFP_KERNEL ) ) == NULL )
++ goto struct_malloc_failed ;
++
++ /*Zero it out*/
++ memset ( node , 0 , sizeof (gcsDEBUGFS_Node ) ) ;
++
++ /*Init the sync primitives*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_READQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_READQ ( node ) ) ;
++#endif
++
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_WRITEQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_WRITEQ ( node ) ) ;
++#endif
++ /*End the sync primitives*/
++
++ /*creating the debug file system*/
++ node->parent = Root;
++
++ if (SizeInKB)
++ {
++ /* figure out how much of a buffer this should be and allocate the buffer */
++ node->size = 1024 * SizeInKB ;
++ if ( ( node->data = ( char * ) vmalloc ( sizeof (char ) * node->size ) ) == NULL )
++ goto data_malloc_failed ;
++
++ /*creating the file*/
++ node->filen = debugfs_create_file(NodeName, S_IRUGO|S_IWUSR, node->parent, NULL,
++ &debugfs_operations);
++ }
++
++ node->vidmem
++ = debugfs_create_file("vidmem", S_IRUGO|S_IWUSR, node->parent, Device, &vidmem_operations);
++
++ /* add it to our linked list */
++ node->next = gc_dbgfs.linkedlist ;
++ gc_dbgfs.linkedlist = node ;
++
++
++ /* pass the struct back */
++ *Node = node ;
++ return 0 ;
++
++
++data_malloc_failed:
++ kfree ( node ) ;
++struct_malloc_failed:
++ return - ENOMEM ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_FreeNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDEBUGFS_FreeNode (
++ IN gcsDEBUGFS_Node * Node
++ )
++{
++
++ gcsDEBUGFS_Node **ptr ;
++
++ if ( Node == NULL )
++ {
++ printk ( "null passed to free_vinfo\n" ) ;
++ return ;
++ }
++
++ /*free data*/
++ vfree ( Node->data ) ;
++
++ /*Close Debug fs*/
++ if (Node->vidmem)
++ {
++ debugfs_remove(Node->vidmem);
++ }
++
++ if ( Node->filen )
++ {
++ debugfs_remove ( Node->filen ) ;
++ }
++
++ /* now delete the node from the linked list */
++ ptr = & ( gc_dbgfs.linkedlist ) ;
++ while ( *ptr != Node )
++ {
++ if ( ! *ptr )
++ {
++ printk ( "corrupt info list!\n" ) ;
++ break ;
++ }
++ else
++ ptr = & ( ( **ptr ).next ) ;
++ }
++ *ptr = Node->next ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_SetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDEBUGFS_SetCurrentNode (
++ IN gcsDEBUGFS_Node * Node
++ )
++{
++ gc_dbgfs.currentNode = Node ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_GetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDEBUGFS_GetCurrentNode (
++ OUT gcsDEBUGFS_Node ** Node
++ )
++{
++ *Node = gc_dbgfs.currentNode ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_Print
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++ssize_t
++gckDEBUGFS_Print (
++ IN gctCONST_STRING Message ,
++ ...
++ )
++{
++ ssize_t _debugfs_res;
++ gcmkDEBUGFS_PRINT ( _GetArgumentSize ( Message ) , Message ) ;
++ return _debugfs_res;
++}
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debugfs.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debugfs.h 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,135 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <stdarg.h>
++
++#ifndef __gc_hal_kernel_debugfs_h_
++#define __gc_hal_kernel_debugfs_h_
++
++ #define MAX_LINE_SIZE 768 /* Max bytes for a line of debug info */
++
++
++ typedef struct _gcsDEBUGFS_Node gcsDEBUGFS_Node;
++
++typedef struct _gcsDEBUGFS_DIR *gckDEBUGFS_DIR;
++typedef struct _gcsDEBUGFS_DIR
++{
++ struct dentry * root;
++ struct list_head nodeList;
++}
++gcsDEBUGFS_DIR;
++
++typedef struct _gcsINFO
++{
++ const char * name;
++ int (*show)(struct seq_file*, void*);
++}
++gcsINFO;
++
++typedef struct _gcsINFO_NODE
++{
++ gcsINFO * info;
++ gctPOINTER device;
++ struct dentry * entry;
++ struct list_head head;
++}
++gcsINFO_NODE;
++
++gceSTATUS
++gckDEBUGFS_DIR_Init(
++ IN gckDEBUGFS_DIR Dir,
++ IN struct dentry *root,
++ IN gctCONST_STRING Name
++ );
++
++gceSTATUS
++gckDEBUGFS_DIR_CreateFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count,
++ IN gctPOINTER Data
++ );
++
++gceSTATUS
++gckDEBUGFS_DIR_RemoveFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count
++ );
++
++void
++gckDEBUGFS_DIR_Deinit(
++ IN gckDEBUGFS_DIR Dir
++ );
++
++/*******************************************************************************
++ **
++ ** System Related
++ **
++ *******************************************************************************/
++
++gctINT gckDEBUGFS_IsEnabled(void);
++
++gctINT gckDEBUGFS_Initialize(void);
++
++gctINT gckDEBUGFS_Terminate(void);
++
++
++/*******************************************************************************
++ **
++ ** Node Related
++ **
++ *******************************************************************************/
++
++gctINT
++gckDEBUGFS_CreateNode(
++ IN gctPOINTER Device,
++ IN gctINT SizeInKB,
++ IN struct dentry * Root,
++ IN gctCONST_STRING NodeName,
++ OUT gcsDEBUGFS_Node **Node
++ );
++
++void gckDEBUGFS_FreeNode(
++ IN gcsDEBUGFS_Node * Node
++ );
++
++
++
++void gckDEBUGFS_SetCurrentNode(
++ IN gcsDEBUGFS_Node * Node
++ );
++
++
++
++void gckDEBUGFS_GetCurrentNode(
++ OUT gcsDEBUGFS_Node ** Node
++ );
++
++
++ssize_t gckDEBUGFS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#endif
++
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debug.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debug.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_debug.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_debug.h 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,103 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_debug_h_
++#define __gc_hal_kernel_debug_h_
++
++#include <gc_hal_kernel_linux.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <stdarg.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** OS-dependent Macros *****************************
++\******************************************************************************/
++
++typedef va_list gctARGUMENTS;
++
++#define gcmkARGUMENTS_START(Arguments, Pointer) \
++ va_start(Arguments, Pointer)
++
++#define gcmkARGUMENTS_END(Arguments) \
++ va_end(Arguments)
++
++#define gcmkARGUMENTS_ARG(Arguments, Type) \
++ va_arg(Arguments, Type)
++
++#define gcmkDECLARE_LOCK(__spinLock__) \
++ static DEFINE_SPINLOCK(__spinLock__); \
++ unsigned long __spinLock__##flags = 0;
++
++#define gcmkLOCKSECTION(__spinLock__) \
++ spin_lock_irqsave(&__spinLock__, __spinLock__##flags)
++
++#define gcmkUNLOCKSECTION(__spinLock__) \
++ spin_unlock_irqrestore(&__spinLock__, __spinLock__##flags)
++
++# define gcmkGETPROCESSID() \
++ task_tgid_vnr(current)
++
++# define gcmkGETTHREADID() \
++ task_pid_vnr(current)
++
++#define gcmkOUTPUT_STRING(String) \
++ if(gckDEBUGFS_IsEnabled()) {\
++ while(-ERESTARTSYS == gckDEBUGFS_Print(String));\
++ }else{\
++ printk(String); \
++ }\
++ touch_softlockup_watchdog()
++
++
++#define gcmkSPRINTF(Destination, Size, Message, Value) \
++ snprintf(Destination, Size, Message, Value)
++
++#define gcmkSPRINTF2(Destination, Size, Message, Value1, Value2) \
++ snprintf(Destination, Size, Message, Value1, Value2)
++
++#define gcmkSPRINTF3(Destination, Size, Message, Value1, Value2, Value3) \
++ snprintf(Destination, Size, Message, Value1, Value2, Value3)
++
++#define gcmkVSPRINTF(Destination, Size, Message, Arguments) \
++ vsnprintf(Destination, Size, Message, *((va_list*)Arguments))
++
++#define gcmkSTRCAT(Destination, Size, String) \
++ strncat(Destination, String, Size)
++
++#define gcmkMEMCPY(Destination, Source, Size) \
++ memcpy(Destination, Source, Size)
++
++#define gcmkSTRLEN(String) \
++ strlen(String)
++
++/* If not zero, forces data alignment in the variable argument list
++ by its individual size. */
++#define gcdALIGNBYSIZE 1
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_debug_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_device.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_device.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_device.c 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,1941 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <linux/slab.h>
++
++#define _GC_OBJ_ZONE gcvZONE_DEVICE
++
++#define DEBUG_FILE "galcore_trace"
++#define PARENT_FILE "gpu"
++
++gckKERNEL
++_GetValidKernel(
++ gckGALDEVICE Device
++ )
++{
++ if (Device->kernels[gcvCORE_MAJOR])
++ {
++ return Device->kernels[gcvCORE_MAJOR];
++ }
++ else
++ if (Device->kernels[gcvCORE_2D])
++ {
++ return Device->kernels[gcvCORE_2D];
++ }
++ else
++ if (Device->kernels[gcvCORE_VG])
++ {
++ return Device->kernels[gcvCORE_VG];
++ }
++ else
++ {
++ return gcvNULL;
++ }
++}
++
++/******************************************************************************\
++******************************** Debugfs Support *******************************
++\******************************************************************************/
++
++/******************************************************************************\
++***************************** DEBUG SHOW FUNCTIONS *****************************
++\******************************************************************************/
++
++int gc_info_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ int i = 0;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ chipModel = device->kernels[i]->vg->hardware->chipModel;
++ chipRevision = device->kernels[i]->vg->hardware->chipRevision;
++ }
++ else
++#endif
++ {
++ chipModel = device->kernels[i]->hardware->identity.chipModel;
++ chipRevision = device->kernels[i]->hardware->identity.chipRevision;
++ }
++
++ seq_printf(m, "gpu : %d\n", i);
++ seq_printf(m, "model : %4x\n", chipModel);
++ seq_printf(m, "revision : %4x\n", chipRevision);
++ seq_printf(m, "\n");
++ }
++ }
++
++ return 0;
++}
++
++int gc_clients_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++
++ gckKERNEL kernel = _GetValidKernel(device);
++
++ gcsDATABASE_PTR database;
++ gctINT i, pid;
++ gctUINT8 name[24];
++
++ seq_printf(m, "%-8s%s\n", "PID", "NAME");
++ seq_printf(m, "------------------------\n");
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(kernel->os, kernel->db->dbMutex, gcvINFINITE));
++
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ for (database = kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ pid = database->processID;
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ seq_printf(m, "%-8d%s\n", pid, name);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(kernel->os, kernel->db->dbMutex));
++
++ /* Success. */
++ return 0;
++}
++
++static void
++_CounterAdd(
++ gcsDATABASE_COUNTERS * Dest,
++ gcsDATABASE_COUNTERS * Src
++ )
++{
++ Dest->bytes += Src->bytes;
++ Dest->maxBytes += Src->maxBytes;
++ Dest->totalBytes += Src->totalBytes;
++}
++
++static void
++_CounterPrint(
++ gcsDATABASE_COUNTERS * Counter,
++ gctCONST_STRING Name,
++ struct seq_file* m
++ )
++{
++ seq_printf(m, " %s:\n", Name);
++ seq_printf(m, " Used : %10llu B\n", Counter->bytes);
++}
++
++int gc_meminfo_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ gckKERNEL kernel = _GetValidKernel(device);
++ gckVIDMEM memory;
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctUINT32 i;
++
++ gctUINT32 free = 0, used = 0, total = 0;
++
++ gcsDATABASE_COUNTERS contiguousCounter = {0, 0, 0};
++ gcsDATABASE_COUNTERS virtualCounter = {0, 0, 0};
++ gcsDATABASE_COUNTERS nonPagedCounter = {0, 0, 0};
++
++ status = gckKERNEL_GetVideoMemoryPool(kernel, gcvPOOL_SYSTEM, &memory);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(memory->os, memory->mutex, gcvINFINITE));
++
++ free = memory->freeBytes;
++ used = memory->bytes - memory->freeBytes;
++ total = memory->bytes;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(memory->os, memory->mutex));
++ }
++
++ seq_printf(m, "VIDEO MEMORY:\n");
++ seq_printf(m, " gcvPOOL_SYSTEM:\n");
++ seq_printf(m, " Free : %10u B\n", free);
++ seq_printf(m, " Used : %10u B\n", used);
++ seq_printf(m, " Total : %10u B\n", total);
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(kernel->os, kernel->db->dbMutex, gcvINFINITE));
++
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ for (database = kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ gcsDATABASE_COUNTERS * counter = &database->vidMemPool[gcvPOOL_CONTIGUOUS];
++ _CounterAdd(&contiguousCounter, counter);
++
++ counter = &database->vidMemPool[gcvPOOL_VIRTUAL];
++ _CounterAdd(&virtualCounter, counter);
++
++
++ counter = &database->nonPaged;
++ _CounterAdd(&nonPagedCounter, counter);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(kernel->os, kernel->db->dbMutex));
++
++ _CounterPrint(&contiguousCounter, "gcvPOOL_CONTIGUOUS", m);
++ _CounterPrint(&virtualCounter, "gcvPOOL_VIRTUAL", m);
++
++ seq_printf(m, "\n");
++
++ seq_printf(m, "NON PAGED MEMORY:\n");
++ seq_printf(m, " Used : %10llu B\n", nonPagedCounter.bytes);
++
++ return 0;
++}
++
++static int
++_ShowRecord(
++ IN struct seq_file *file,
++ IN gcsDATABASE_RECORD_PTR record
++ )
++{
++ seq_printf(file, "%4d%8d%16p%16p%16zu\n",
++ record->type,
++ record->kernel->core,
++ record->data,
++ record->physical,
++ record->bytes
++ );
++
++ return 0;
++}
++
++static int
++_ShowRecords(
++ IN struct seq_file *File,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gctUINT i;
++
++ seq_printf(File, "Records:\n");
++
++ seq_printf(File, "%s%8s%16s%16s%16s\n",
++ "Type", "GPU", "Data", "Physical", "Bytes");
++
++ for (i = 0; i < gcmCOUNTOF(Database->list); i++)
++ {
++ gcsDATABASE_RECORD_PTR record = Database->list[i];
++
++ while (record != NULL)
++ {
++ _ShowRecord(File, record);
++ record = record->next;
++ }
++ }
++
++ return 0;
++}
++
++void
++_ShowCounters(
++ struct seq_file *File,
++ gcsDATABASE_PTR Database
++ );
++
++static void
++_ShowProcess(
++ IN struct seq_file *File,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gctINT pid;
++ gctUINT8 name[24];
++
++ /* Process ID and name */
++ pid = Database->processID;
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ seq_printf(File, "--------------------------------------------------------------------------------\n");
++ seq_printf(File, "Process: %-8d %s\n", pid, name);
++
++ /* Detailed records */
++ _ShowRecords(File, Database);
++
++ seq_printf(File, "Counters:\n");
++
++ _ShowCounters(File, Database);
++}
++
++static void
++_ShowProcesses(
++ IN struct seq_file * file,
++ IN gckKERNEL Kernel
++ )
++{
++ gcsDATABASE_PTR database;
++ gctINT i;
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++
++ /* Idle time since last call */
++ seq_printf(file, "GPU Idle: %llu ns\n", Kernel->db->idleTime);
++ Kernel->db->idleTime = 0;
++
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ for (database = Kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ _ShowProcess(file, database);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++}
++
++static int
++gc_db_show(struct seq_file *m, void *data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ gckKERNEL kernel = _GetValidKernel(device);
++ _ShowProcesses(m, kernel);
++ return 0 ;
++}
++
++static int
++gc_version_show(struct seq_file *m, void *data)
++{
++ seq_printf(m, "%s\n", gcvVERSION_STRING);
++
++ return 0 ;
++}
++
++int gc_idle_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ gckKERNEL kernel = _GetValidKernel(device);
++ gcuDATABASE_INFO info;
++
++ gckKERNEL_QueryProcessDB(kernel, 0, gcvFALSE, gcvDB_IDLE, &info);
++
++ seq_printf(m, "GPU idle time since last query: %llu ns\n", info.time);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"info", gc_info_show},
++ {"clients", gc_clients_show},
++ {"meminfo", gc_meminfo_show},
++ {"idle", gc_idle_show},
++ {"database", gc_db_show},
++ {"version", gc_version_show},
++};
++
++static gceSTATUS
++_DebugfsInit(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gckDEBUGFS_DIR dir = &Device->debugfsDir;
++
++ gcmkONERROR(gckDEBUGFS_DIR_Init(dir, gcvNULL, "gc"));
++
++ gcmkONERROR(gckDEBUGFS_DIR_CreateFiles(dir, InfoList, gcmCOUNTOF(InfoList), Device));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++static void
++_DebugfsCleanup(
++ IN gckGALDEVICE Device
++ )
++{
++ gckDEBUGFS_DIR dir = &Device->debugfsDir;
++
++ if (Device->debugfsDir.root)
++ {
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(dir, InfoList, gcmCOUNTOF(InfoList)));
++
++ gckDEBUGFS_DIR_Deinit(dir);
++ }
++}
++
++
++/******************************************************************************\
++*************************** Memory Allocation Wrappers *************************
++\******************************************************************************/
++
++static gceSTATUS
++_AllocateMemory(
++ IN gckGALDEVICE Device,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER *Logical,
++ OUT gctPHYS_ADDR *Physical,
++ OUT gctUINT32 *PhysAddr
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Bytes=%lu", Device, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++ gcmkVERIFY_ARGUMENT(Physical != NULL);
++ gcmkVERIFY_ARGUMENT(PhysAddr != NULL);
++
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Device->os, gcvFALSE, &Bytes, Physical, Logical
++ ));
++
++ *PhysAddr = ((PLINUX_MDL)*Physical)->dmaHandle;
++
++ /* Success. */
++ gcmkFOOTER_ARG(
++ "*Logical=0x%x *Physical=0x%x *PhysAddr=0x%08x",
++ *Logical, *Physical, *PhysAddr
++ );
++
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_FreeMemory(
++ IN gckGALDEVICE Device,
++ IN gctPOINTER Logical,
++ IN gctPHYS_ADDR Physical)
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Logical=0x%x Physical=0x%x",
++ Device, Logical, Physical);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ status = gckOS_FreeContiguous(
++ Device->os, Physical, Logical,
++ ((PLINUX_MDL) Physical)->numPages * PAGE_SIZE
++ );
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++
++/******************************************************************************\
++******************************* Interrupt Handler ******************************
++\******************************************************************************/
++static irqreturn_t isrRoutine(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ up(&device->semas[gcvCORE_MAJOR]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_MAJOR]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR],
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutine2D(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_2D],
++ gcvNOTIFY_INTERRUPT,
++ gcvTRUE);
++ if (gcmIS_SUCCESS(status))
++ {
++ up(&device->semas[gcvCORE_2D]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine2D(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_2D]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++ gckKERNEL_Notify(device->kernels[gcvCORE_2D],
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutineVG(int irq, void *ctxt)
++{
++#if gcdENABLE_VG
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Serve the interrupt. */
++ status = gckVGINTERRUPT_Enque(device->kernels[gcvCORE_VG]->vg->interrupt);
++
++ /* Determine the return value. */
++ return (status == gcvSTATUS_NOT_OUR_INTERRUPT)
++ ? IRQ_RETVAL(0)
++ : IRQ_RETVAL(1);
++#else
++ return IRQ_NONE;
++#endif
++}
++
++static int threadRoutineVG(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_VG]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++ gckKERNEL_Notify(device->kernels[gcvCORE_VG],
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++
++/******************************************************************************\
++******************************* gckGALDEVICE Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Construct
++**
++** Constructor.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gckGALDEVICE * Device
++** Pointer to a variable receiving the gckGALDEVICE object pointer on
++** success.
++*/
++gceSTATUS
++gckGALDEVICE_Construct(
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ IN gcsDEVICE_CONSTRUCT_ARGS * Args,
++ IN struct device *dev,
++ OUT gckGALDEVICE *Device
++ )
++{
++ gctUINT32 internalBaseAddress = 0, internalAlignment = 0;
++ gctUINT32 externalBaseAddress = 0, externalAlignment = 0;
++ gctUINT32 horizontalTileSize, verticalTileSize;
++ struct resource* mem_region;
++ gctUINT32 physAddr;
++ gctUINT32 physical;
++ gckGALDEVICE device;
++ gceSTATUS status;
++ gctINT32 i;
++ gceHARDWARE_TYPE type;
++ gckDB sharedDB = gcvNULL;
++ gckKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("IrqLine=%d RegisterMemBase=0x%08x RegisterMemSize=%u "
++ "IrqLine2D=%d RegisterMemBase2D=0x%08x RegisterMemSize2D=%u "
++ "IrqLineVG=%d RegisterMemBaseVG=0x%08x RegisterMemSizeVG=%u "
++ "ContiguousBase=0x%08x ContiguousSize=%lu BankSize=%lu "
++ "FastClear=%d Compression=%d PhysBaseAddr=0x%x PhysSize=%d Signal=%d",
++ IrqLine, RegisterMemBase, RegisterMemSize,
++ IrqLine2D, RegisterMemBase2D, RegisterMemSize2D,
++ IrqLineVG, RegisterMemBaseVG, RegisterMemSizeVG,
++ ContiguousBase, ContiguousSize, BankSize, FastClear, Compression,
++ PhysBaseAddr, PhysSize, Signal);
++
++#if gcdDISABLE_CORES_2D3D
++ IrqLine = -1;
++ IrqLine2D = -1;
++#endif
++
++ /* Allocate device structure. */
++ device = kmalloc(sizeof(struct _gckGALDEVICE), GFP_KERNEL | __GFP_NOWARN);
++
++ if (!device)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ memset(device, 0, sizeof(struct _gckGALDEVICE));
++
++ device->dbgNode = gcvNULL;
++
++ device->platform = Args->platform;
++
++ device->dev = dev;
++
++ gcmkONERROR(_DebugfsInit(device));
++
++ if (gckDEBUGFS_CreateNode(
++ device, LogFileSize, device->debugfsDir.root ,DEBUG_FILE, &(device->dbgNode)))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the debug file system %s/%s \n",
++ __FUNCTION__, __LINE__,
++ PARENT_FILE, DEBUG_FILE
++ );
++ }
++ else if (LogFileSize)
++ {
++ gckDEBUGFS_SetCurrentNode(device->dbgNode);
++ }
++
++ if (IrqLine != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_MAJOR] = RegisterMemBase;
++ device->requestedRegisterMemSizes[gcvCORE_MAJOR] = RegisterMemSize;
++ }
++
++ if (IrqLine2D != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_2D] = RegisterMemBase2D;
++ device->requestedRegisterMemSizes[gcvCORE_2D] = RegisterMemSize2D;
++ }
++
++ if (IrqLineVG != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_VG] = RegisterMemBaseVG;
++ device->requestedRegisterMemSizes[gcvCORE_VG] = RegisterMemSizeVG;
++ }
++
++ device->requestedContiguousBase = 0;
++ device->requestedContiguousSize = 0;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ physical = device->requestedRegisterMemBases[i];
++
++ /* Set up register memory region. */
++ if (physical != 0)
++ {
++ mem_region = request_mem_region(physical,
++ device->requestedRegisterMemSizes[i],
++ "galcore register region");
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %lu bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->registerBases[i] = (gctPOINTER) ioremap_nocache(
++ physical, device->requestedRegisterMemSizes[i]);
++
++ if (device->registerBases[i] == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unable to map %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ physical += device->requestedRegisterMemSizes[i];
++ }
++ }
++
++ /* Set the base address */
++ device->baseAddress = device->physBase = PhysBaseAddr;
++ device->physSize = PhysSize;
++ device->mmu = Args->mmu;
++
++ /* Construct the gckOS object. */
++ gcmkONERROR(gckOS_Construct(device, &device->os));
++
++ if (IrqLine != -1)
++ {
++ /* Construct the gckKERNEL object. */
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_MAJOR, device,
++ gcvNULL, &device->kernels[gcvCORE_MAJOR]));
++
++ sharedDB = device->kernels[gcvCORE_MAJOR]->db;
++
++ /* Initialize core mapping */
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_MAJOR;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_MAJOR]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR,
++ device
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(
++ device->kernels[gcvCORE_MAJOR]->hardware, FastClear, Compression
++ ));
++
++ if(PowerManagement != -1)
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_MAJOR]->hardware, PowerManagement
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvTRUE
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvTRUE
++ ));
++ }
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gcmkONERROR(gckHARDWARE_SetMinFscaleValue(
++ device->kernels[gcvCORE_MAJOR]->hardware, Args->gpu3DMinClock
++ ));
++#endif
++
++ gcmkONERROR(gckHARDWARE_SetGpuProfiler(
++ device->kernels[gcvCORE_MAJOR]->hardware, GpuProfiler
++ ));
++
++ gcmkVERIFY_OK(gckKERNEL_SetRecovery(
++ device->kernels[gcvCORE_MAJOR], Args->recovery, Args->stuckDump
++ ));
++
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_MAJOR]->command));
++ }
++ else
++ {
++ device->kernels[gcvCORE_MAJOR] = gcvNULL;
++ }
++
++ if (IrqLine2D != -1)
++ {
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_2D, device,
++ sharedDB, &device->kernels[gcvCORE_2D]));
++
++ if (sharedDB == gcvNULL) sharedDB = device->kernels[gcvCORE_2D]->db;
++
++ /* Verify the hardware type */
++ gcmkONERROR(gckHARDWARE_GetType(device->kernels[gcvCORE_2D]->hardware, &type));
++
++ if (type != gcvHARDWARE_2D)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unexpected hardware type: %d\n",
++ __FUNCTION__, __LINE__,
++ type
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL)
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_2D;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_2D] = gcvCORE_2D;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_2D]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR,
++ device
++ ));
++
++ if(PowerManagement != -1)
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_2D]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_2D]->hardware, PowerManagement
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_2D]->hardware, gcvTRUE
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_2D]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_2D]->hardware, gcvTRUE
++ ));
++ }
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gcmkONERROR(gckHARDWARE_SetMinFscaleValue(
++ device->kernels[gcvCORE_2D]->hardware, 1
++ ));
++#endif
++
++ gcmkVERIFY_OK(gckKERNEL_SetRecovery(
++ device->kernels[gcvCORE_2D], Args->recovery, Args->stuckDump
++ ));
++
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_2D]->command));
++ }
++ else
++ {
++ device->kernels[gcvCORE_2D] = gcvNULL;
++ }
++
++ if (IrqLineVG != -1)
++ {
++#if gcdENABLE_VG
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_VG, device,
++ sharedDB, &device->kernels[gcvCORE_VG]));
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL
++ && device->kernels[gcvCORE_2D] == gcvNULL
++ )
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_VG;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_VG] = gcvCORE_VG;
++ }
++
++ if(PowerManagement != -1)
++ {
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_VG]->vg->hardware,
++ PowerManagement
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_VG]->vg->hardware,
++ gcvTRUE
++ ));
++ }
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_VG] = gcvNULL;
++ }
++
++ /* Initialize the ISR. */
++ device->irqLines[gcvCORE_MAJOR] = IrqLine;
++ device->irqLines[gcvCORE_2D] = IrqLine2D;
++ device->irqLines[gcvCORE_VG] = IrqLineVG;
++
++ /* Initialize the kernel thread semaphores. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1) sema_init(&device->semas[i], 0);
++ }
++
++ device->signal = Signal;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL) break;
++ }
++
++ if (i == gcdMAX_GPU_COUNT)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckVGHARDWARE_QuerySystemMemory(
++ device->kernels[i]->vg->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++ /* query the amount of video memory */
++ gcmkONERROR(gckVGHARDWARE_QueryMemory(
++ device->kernels[i]->vg->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++ else
++#endif
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckHARDWARE_QuerySystemMemory(
++ device->kernels[i]->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++
++ /* query the amount of video memory */
++ gcmkONERROR(gckHARDWARE_QueryMemory(
++ device->kernels[i]->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++
++
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1)
++ {
++ kernel = device->kernels[i];
++ break;
++ }
++ }
++
++ /* Set up the internal memory region. */
++ if (device->internalSize > 0)
++ {
++ status = gckVIDMEM_Construct(
++ device->os,
++ internalBaseAddress, device->internalSize, internalAlignment,
++ 0, &device->internalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->internalSize = 0;
++ }
++ else
++ {
++ /* Map internal memory. */
++ device->internalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->internalSize);
++
++ if (device->internalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->internalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->internalPhysicalName = gcmPTR_TO_NAME(device->internalPhysical);
++ physical += device->internalSize;
++ }
++ }
++
++ if (device->externalSize > 0)
++ {
++ /* create the external memory heap */
++ status = gckVIDMEM_Construct(
++ device->os,
++ externalBaseAddress, device->externalSize, externalAlignment,
++ 0, &device->externalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->externalSize = 0;
++ }
++ else
++ {
++ /* Map external memory. */
++ device->externalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->externalSize);
++
++ if (device->externalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->externalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->externalPhysicalName = gcmPTR_TO_NAME(device->externalPhysical);
++ physical += device->externalSize;
++ }
++ }
++
++ /* set up the contiguous memory */
++ device->contiguousSize = ContiguousSize;
++
++ if (ContiguousSize > 0)
++ {
++ if (ContiguousBase == 0)
++ {
++ while (device->contiguousSize > 0)
++ {
++ /* Allocate contiguous memory. */
++ status = _AllocateMemory(
++ device,
++ device->contiguousSize,
++ &device->contiguousBase,
++ &device->contiguousPhysical,
++ &physAddr
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->contiguousPhysicalName = gcmPTR_TO_NAME(device->contiguousPhysical);
++ status = gckVIDMEM_Construct(
++ device->os,
++ physAddr | device->systemMemoryBaseAddress,
++ device->contiguousSize,
++ 64,
++ BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++
++ gcmkONERROR(_FreeMemory(
++ device,
++ device->contiguousBase,
++ device->contiguousPhysical
++ ));
++
++ gcmRELEASE_NAME(device->contiguousPhysicalName);
++ device->contiguousBase = gcvNULL;
++ device->contiguousPhysical = gcvNULL;
++ }
++
++ if (device->contiguousSize <= (4 << 20))
++ {
++ device->contiguousSize = 0;
++ }
++ else
++ {
++ device->contiguousSize -= (4 << 20);
++ }
++ }
++ }
++ else
++ {
++ /* Create the contiguous memory heap. */
++ status = gckVIDMEM_Construct(
++ device->os,
++ ContiguousBase | device->systemMemoryBaseAddress,
++ ContiguousSize,
++ 64, BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable contiguous memory pool. */
++ device->contiguousVidMem = gcvNULL;
++ device->contiguousSize = 0;
++ }
++ else
++ {
++ if (Args->contiguousRequested == gcvFALSE)
++ {
++ mem_region = request_mem_region(
++ ContiguousBase, ContiguousSize, "galcore managed memory"
++ );
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ ContiguousSize, ContiguousBase
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ device->requestedContiguousBase = ContiguousBase;
++ device->requestedContiguousSize = ContiguousSize;
++ device->contiguousRequested = Args->contiguousRequested;
++
++ device->contiguousPhysical = gcvNULL;
++ device->contiguousPhysicalName = 0;
++ device->contiguousSize = ContiguousSize;
++ device->contiguousMapped = gcvTRUE;
++ }
++ }
++ }
++
++ /* Return pointer to the device. */
++ *Device = device;
++
++ gcmkFOOTER_ARG("*Device=0x%x", * Device);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Destroy
++**
++** Class destructor.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Destroy(
++ gckGALDEVICE Device)
++{
++ gctINT i;
++ gckKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ if (Device != gcvNULL)
++ {
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->irqLines[i] != -1)
++ {
++ kernel = Device->kernels[i];
++ break;
++ }
++ }
++
++ if (Device->internalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->internalPhysicalName);
++ Device->internalPhysicalName = 0;
++ }
++ if (Device->externalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->externalPhysicalName);
++ Device->externalPhysicalName = 0;
++ }
++ if (Device->contiguousPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->contiguousPhysicalName);
++ Device->contiguousPhysicalName = 0;
++ }
++
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->kernels[i] != gcvNULL)
++ {
++ /* Destroy the gckKERNEL object. */
++ gcmkVERIFY_OK(gckKERNEL_Destroy(Device->kernels[i]));
++ Device->kernels[i] = gcvNULL;
++ }
++ }
++
++ if (Device->internalLogical != gcvNULL)
++ {
++ /* Unmap the internal memory. */
++ iounmap(Device->internalLogical);
++ Device->internalLogical = gcvNULL;
++ }
++
++ if (Device->internalVidMem != gcvNULL)
++ {
++ /* Destroy the internal heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->internalVidMem));
++ Device->internalVidMem = gcvNULL;
++ }
++
++ if (Device->externalLogical != gcvNULL)
++ {
++ /* Unmap the external memory. */
++ iounmap(Device->externalLogical);
++ Device->externalLogical = gcvNULL;
++ }
++
++ if (Device->externalVidMem != gcvNULL)
++ {
++ /* destroy the external heap */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->externalVidMem));
++ Device->externalVidMem = gcvNULL;
++ }
++
++ if (Device->contiguousBase != gcvNULL)
++ {
++ if (Device->contiguousMapped == gcvFALSE)
++ {
++ gcmkVERIFY_OK(_FreeMemory(
++ Device,
++ Device->contiguousBase,
++ Device->contiguousPhysical
++ ));
++ }
++
++ Device->contiguousBase = gcvNULL;
++ Device->contiguousPhysical = gcvNULL;
++ }
++
++ if (Device->requestedContiguousBase != 0
++ && Device->contiguousRequested == gcvFALSE
++ )
++ {
++ release_mem_region(Device->requestedContiguousBase, Device->requestedContiguousSize);
++ Device->requestedContiguousBase = 0;
++ Device->requestedContiguousSize = 0;
++ }
++
++ if (Device->contiguousVidMem != gcvNULL)
++ {
++ /* Destroy the contiguous heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->contiguousVidMem));
++ Device->contiguousVidMem = gcvNULL;
++ }
++
++ if (Device->dbgNode)
++ {
++ gckDEBUGFS_FreeNode(Device->dbgNode);
++
++ if(Device->dbgNode != gcvNULL)
++ {
++ kfree(Device->dbgNode);
++ Device->dbgNode = gcvNULL;
++ }
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->registerBases[i] != gcvNULL)
++ {
++ /* Unmap register memory. */
++ iounmap(Device->registerBases[i]);
++ if (Device->requestedRegisterMemBases[i] != 0)
++ {
++ release_mem_region(Device->requestedRegisterMemBases[i],
++ Device->requestedRegisterMemSizes[i]);
++ }
++
++ Device->registerBases[i] = gcvNULL;
++ Device->requestedRegisterMemBases[i] = 0;
++ Device->requestedRegisterMemSizes[i] = 0;
++ }
++ }
++
++ /* Destroy the gckOS object. */
++ if (Device->os != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Destroy(Device->os));
++ Device->os = gcvNULL;
++ }
++
++ _DebugfsCleanup(Device);
++
++ /* Free the device. */
++ kfree(Device);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Setup_ISR
++**
++** Start the ISR routine.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Setup successfully.
++** gcvSTATUS_GENERIC_IO
++** Setup failed.
++*/
++gceSTATUS
++gckGALDEVICE_Setup_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status;
++ gctINT ret = 0;
++
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[Core] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Hook up the isr based on the irq line. */
++ switch (Core) {
++ case gcvCORE_MAJOR:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutine, 0,
++ "galcore interrupt service", Device
++ );
++ break;
++ case gcvCORE_2D:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutine2D, 0,
++ "galcore 2D interrupt service", Device
++ );
++ break;
++ case gcvCORE_VG:
++ ret = request_irq(
++ Device->irqLines[Core], isrRoutineVG, 0,
++ "galcore VG interrupt service", Device
++ );
++ break;
++ default:
++ break;
++ }
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[gcvCORE_MAJOR], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->isrEnabled[Core] = 1;
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[Core] = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckGALDEVICE_Enable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[Core] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ spin_lock(&Device->kernels[Core]->irq_lock);
++ if (Device->isrEnabled[Core] == 0)
++ {
++ enable_irq(Device->irqLines[Core]);
++ /* Mark ISR as initialized. */
++ Device->isrEnabled[Core] = gcvTRUE;
++ }
++ Device->isrEnabled[Core]++;
++ spin_unlock(&Device->kernels[Core]->irq_lock);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Release_ISR
++**
++** Release the irq line.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Release_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* release the irq */
++ if (Device->isrInitializeds[Core])
++ {
++ free_irq(Device->irqLines[Core], Device);
++ Device->isrInitializeds[Core] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckGALDEVICE_Disable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* disable the irq */
++ spin_lock(&Device->kernels[Core]->irq_lock);
++ if (Device->isrEnabled[Core] > 0)
++ {
++ Device->isrEnabled[Core]--;
++ if (Device->isrEnabled[Core] == 0)
++ disable_irq(Device->irqLines[Core]);
++ }
++ spin_unlock(&Device->kernels[Core]->irq_lock);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start_Threads
++**
++** Start the daemon threads.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++** gcvSTATUS_GENERIC_IO
++** Start failed.
++*/
++gceSTATUS
++gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++ struct task_struct * task;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine, Device, "galcore daemon thread");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_MAJOR] = task;
++ Device->threadInitializeds[gcvCORE_MAJOR] = gcvTRUE;
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine2D, Device, "galcore daemon thread for 2D");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_2D] = task;
++ Device->threadInitializeds[gcvCORE_2D] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_2D] = gcvFALSE;
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutineVG, Device, "galcore daemon thread for VG");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_VG] = task;
++ Device->threadInitializeds[gcvCORE_VG] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_VG] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop_Threads
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ /* Stop the kernel threads. */
++ if (Device->threadInitializeds[i])
++ {
++ Device->killThread = gcvTRUE;
++ up(&Device->semas[i]);
++
++ kthread_stop(Device->threadCtxts[i]);
++ Device->threadCtxts[i] = gcvNULL;
++ Device->threadInitializeds[i] = gcvFALSE;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start
++**
++** Start the gal device, including the following actions: setup the isr routine
++** and start the daemoni thread.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++*/
++gceSTATUS
++gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ /* Start the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Start_Threads(Device));
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_MAJOR));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF_ATPOWERON
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_2D));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF_ATPOWERON
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_VG));
++
++#if gcdENABLE_VG
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF_ATPOWERON
++ ));
++#endif
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF
++ ));
++
++ /* Remove the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_MAJOR));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_2D));
++
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_VG));
++
++#if gcdENABLE_VG
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF
++ ));
++#endif
++ }
++
++ /* Stop the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Stop_Threads(Device));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_device.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_device.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_device.h 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,188 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_device_h_
++#define __gc_hal_kernel_device_h_
++
++#include "gc_hal_kernel_debugfs.h"
++
++/******************************************************************************\
++******************************* gckGALDEVICE Structure *******************************
++\******************************************************************************/
++
++typedef struct _gckGALDEVICE
++{
++ struct device *dev;
++
++ /* Objects. */
++ gckOS os;
++ gckKERNEL kernels[gcdMAX_GPU_COUNT];
++
++ gcsPLATFORM* platform;
++
++ /* Attributes. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctUINT32 internalPhysicalName;
++ gctPOINTER internalLogical;
++ gckVIDMEM internalVidMem;
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctUINT32 externalPhysicalName;
++ gctPOINTER externalLogical;
++ gckVIDMEM externalVidMem;
++ gckVIDMEM contiguousVidMem;
++ gctPOINTER contiguousBase;
++ gctPHYS_ADDR contiguousPhysical;
++ gctUINT32 contiguousPhysicalName;
++ gctSIZE_T contiguousSize;
++ gctBOOL contiguousMapped;
++ gctPOINTER contiguousMappedUser;
++ gctBOOL contiguousRequested;
++ gctSIZE_T systemMemorySize;
++ gctUINT32 systemMemoryBaseAddress;
++ gctPOINTER registerBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T registerSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 baseAddress;
++ gctUINT32 physBase;
++ gctUINT32 physSize;
++ gctBOOL mmu;
++ gctUINT32 requestedRegisterMemBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T requestedRegisterMemSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 requestedContiguousBase;
++ gctSIZE_T requestedContiguousSize;
++
++ /* IRQ management. */
++ gctINT irqLines[gcdMAX_GPU_COUNT];
++ gctBOOL isrInitializeds[gcdMAX_GPU_COUNT];
++ gctINT isrEnabled[gcdMAX_GPU_COUNT];
++
++ /* Thread management. */
++ struct task_struct *threadCtxts[gcdMAX_GPU_COUNT];
++ struct semaphore semas[gcdMAX_GPU_COUNT];
++ gctBOOL threadInitializeds[gcdMAX_GPU_COUNT];
++ gctBOOL killThread;
++
++ /* Signal management. */
++ gctINT signal;
++
++ /* Core mapping */
++ gceCORE coreMapping[8];
++
++ /* States before suspend. */
++ gceCHIPPOWERSTATE statesStored[gcdMAX_GPU_COUNT];
++
++ /* Device Debug File System Entry in kernel. */
++ struct _gcsDEBUGFS_Node * dbgNode;
++
++ gcsDEBUGFS_DIR debugfsDir;
++}
++* gckGALDEVICE;
++
++typedef struct _gcsHAL_PRIVATE_DATA
++{
++ gckGALDEVICE device;
++ gctPOINTER mappedMemory;
++ gctPOINTER contiguousLogical;
++ /* The process opening the device may not be the same as the one that closes it. */
++ gctUINT32 pidOpen;
++}
++gcsHAL_PRIVATE_DATA, * gcsHAL_PRIVATE_DATA_PTR;
++
++typedef struct _gcsDEVICE_CONSTRUCT_ARGS
++{
++ gctBOOL recovery;
++ gctUINT stuckDump;
++ gctUINT gpu3DMinClock;
++
++ gctBOOL contiguousRequested;
++ gcsPLATFORM* platform;
++ gctBOOL mmu;
++}
++gcsDEVICE_CONSTRUCT_ARGS;
++
++gceSTATUS gckGALDEVICE_Enable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Disable_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Setup_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Release_ISR(
++ IN gckGALDEVICE Device,
++ IN gceCORE Core
++ );
++
++gceSTATUS gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Construct(
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ IN gcsDEVICE_CONSTRUCT_ARGS * Args,
++ IN struct device *dev,
++ OUT gckGALDEVICE *Device
++ );
++
++gceSTATUS gckGALDEVICE_Destroy(
++ IN gckGALDEVICE Device
++ );
++
++#endif /* __gc_hal_kernel_device_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_event.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_event.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_event.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_event.c 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,2847 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_buffer.h"
++
++#define _GC_OBJ_ZONE gcvZONE_EVENT
++
++#define gcdEVENT_ALLOCATION_COUNT (4096 / gcmSIZEOF(gcsHAL_INTERFACE))
++#define gcdEVENT_MIN_THRESHOLD 4
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++static gceSTATUS
++gckEVENT_AllocateQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR * Queue
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Do we have free queues? */
++ if (Event->freeList == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Move one free queue from the free list. */
++ * Queue = Event->freeList;
++ Event->freeList = Event->freeList->next;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Queue=0x%x", gcmOPT_POINTER(Queue));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Move one free queue from the free list. */
++ Queue->next = Event->freeList;
++ Event->freeList = Queue;
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeRecord(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->freeEventMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Push the record on the free list. */
++ Record->next = Event->freeEventList;
++ Event->freeEventList = Record;
++ Event->freeEventCount += 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++gckEVENT_IsEmpty(
++ IN gckEVENT Event,
++ OUT gctBOOL_PTR IsEmpty
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T i;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(IsEmpty != gcvNULL);
++
++ /* Assume the event queue is empty. */
++ *IsEmpty = gcvTRUE;
++
++ /* Try acquiring the mutex. */
++ status = gckOS_AcquireMutex(Event->os, Event->eventQueueMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Timeout - queue is no longer empty. */
++ *IsEmpty = gcvFALSE;
++ }
++ else
++ {
++ /* Bail out on error. */
++ gcmkONERROR(status);
++
++ /* Walk the event queue. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ /* Check whether this event is in use. */
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* The event is in use, hence the queue is not empty. */
++ *IsEmpty = gcvFALSE;
++ break;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*IsEmpty=%d", gcmOPT_VALUE(IsEmpty));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_TryToIdleGPU(
++ IN gckEVENT Event
++)
++{
++ gceSTATUS status;
++ gctBOOL empty = gcvFALSE;
++ gckHARDWARE hardware;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Event->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Check whether the event queue is empty. */
++ gcmkONERROR(gckEVENT_IsEmpty(Event, &empty));
++
++ if (empty)
++ {
++ /* Inform the system of idle GPU. */
++ gcmkONERROR(gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_IDLE));
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++__RemoveRecordFromProcessDB(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ while (Record != gcvNULL)
++ {
++ if (Record->info.command == gcvHAL_SIGNAL)
++ {
++ /* TODO: Find a better place to bind signal to hardware.*/
++ gcmkVERIFY_OK(gckOS_SignalSetHardware(Event->os,
++ gcmUINT64_TO_PTR(Record->info.u.Signal.signal),
++ Event->kernel->hardware));
++ }
++
++ if (Record->fromKernel)
++ {
++ /* No need to check db if event is from kernel. */
++ Record = Record->next;
++ continue;
++ }
++
++ switch (Record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Record->info.u.FreeNonPagedMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Record->info.u.FreeContiguousMemory.logical)));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(Record->info.u.UnlockVideoMemory.node)));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Record->info.u.UnmapUserMemory.info)));
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_COMMAND_BUFFER,
++ gcmUINT64_TO_PTR(Record->info.u.FreeVirtualCommandBuffer.logical)));
++ break;
++
++ default:
++ break;
++ }
++
++ Record = Record->next;
++ }
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_ReleaseVideoMemoryHandle(
++ IN gckKERNEL Kernel,
++ IN OUT gcsEVENT_PTR Record,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject;
++ gctUINT32 handle;
++
++ switch(Interface->command)
++ {
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ handle = (gctUINT32)Interface->u.UnlockVideoMemory.node;
++
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(
++ Kernel, Record->processID, handle, &nodeObject));
++
++ Record->info.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(nodeObject);
++
++ gckVIDMEM_HANDLE_Dereference(Kernel, Record->processID, handle);
++ break;
++
++ default:
++ break;
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++/*******************************************************************************
++**
++** _QueryFlush
++**
++** Check the type of surfaces which will be released by current event and
++** determine the cache needed to flush.
++**
++*/
++static gceSTATUS
++_QueryFlush(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record,
++ OUT gceKERNEL_FLUSH *Flush
++ )
++{
++ gceKERNEL_FLUSH flush = 0;
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ while (Record != gcvNULL)
++ {
++ switch (Record->info.command)
++ {
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ switch(Record->info.u.UnlockVideoMemory.type)
++ {
++ case gcvSURF_TILE_STATUS:
++ flush |= gcvFLUSH_TILE_STATUS;
++ break;
++ case gcvSURF_RENDER_TARGET:
++ flush |= gcvFLUSH_COLOR;
++ break;
++ case gcvSURF_DEPTH:
++ flush |= gcvFLUSH_DEPTH;
++ break;
++ case gcvSURF_TEXTURE:
++ flush |= gcvFLUSH_TEXTURE;
++ break;
++ case gcvSURF_TYPE_UNKNOWN:
++ gcmkASSERT(0);
++ break;
++ default:
++ break;
++ }
++ break;
++ case gcvHAL_UNMAP_USER_MEMORY:
++ *Flush = gcvFLUSH_ALL;
++ return gcvSTATUS_OK;
++
++ default:
++ break;
++ }
++
++ Record = Record->next;
++ }
++
++ *Flush = flush;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_SubmitTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckEVENT event = (gckEVENT)Data;
++ gcmkVERIFY_OK(gckEVENT_Submit(event, gcvTRUE, gcvFALSE, gcvFALSE));
++}
++
++/******************************************************************************\
++******************************* gckEVENT API Code *******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckEVENT_Construct
++**
++** Construct a new gckEVENT object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckEVENT * Event
++** Pointer to a variable that receives the gckEVENT object pointer.
++*/
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gckEVENT eventObj = gcvNULL;
++ int i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Event != gcvNULL);
++
++ /* Extract the pointer to the gckOS object. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate the gckEVENT object. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckEVENT), &pointer));
++
++ eventObj = pointer;
++
++ /* Reset the object. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(eventObj, gcmSIZEOF(struct _gckEVENT)));
++
++ /* Initialize the gckEVENT object. */
++ eventObj->object.type = gcvOBJ_EVENT;
++ eventObj->kernel = Kernel;
++ eventObj->os = os;
++
++ /* Create the mutexes. */
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventQueueMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->freeEventMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventListMutex));
++
++ /* Create a bunch of event reccords. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsEVENT), &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = eventObj->freeEventList;
++ eventObj->freeEventList = record;
++ eventObj->freeEventCount += 1;
++ }
++
++ /* Initialize the free list of event queues. */
++ for (i = 0; i < gcdREPO_LIST_COUNT; i += 1)
++ {
++ eventObj->repoList[i].next = eventObj->freeList;
++ eventObj->freeList = &eventObj->repoList[i];
++ }
++
++ /* Construct the atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->freeAtom));
++ gcmkONERROR(gckOS_AtomSet(os,
++ eventObj->freeAtom,
++ gcmCOUNTOF(eventObj->queues)));
++
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pending));
++#endif
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(os,
++ _SubmitTimerFunction,
++ (gctPOINTER)eventObj,
++ &eventObj->submitTimer));
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->interruptCount));
++ gcmkONERROR(gckOS_AtomSet(os,eventObj->interruptCount, 0));
++#endif
++
++ /* Return pointer to the gckEVENT object. */
++ *Event = eventObj;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Event=0x%x", *Event);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (eventObj != gcvNULL)
++ {
++ if (eventObj->eventQueueMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventQueueMutex));
++ }
++
++ if (eventObj->freeEventMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->freeEventMutex));
++ }
++
++ if (eventObj->eventListMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventListMutex));
++ }
++
++ while (eventObj->freeEventList != gcvNULL)
++ {
++ record = eventObj->freeEventList;
++ eventObj->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, record));
++ }
++
++ if (eventObj->freeAtom != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->freeAtom));
++ }
++
++#if gcdSMP
++ if (eventObj->pending != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->pending));
++ }
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ if (eventObj->interruptCount)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->interruptCount));
++ }
++#endif
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, eventObj));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Destroy
++**
++** Destroy an gckEVENT object.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_PTR record;
++ gcsEVENT_QUEUE_PTR queue;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ if (Event->submitTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Event->os, Event->submitTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Event->os, Event->submitTimer));
++ }
++
++ /* Delete the queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventQueueMutex));
++
++ /* Free all free events. */
++ while (Event->freeEventList != gcvNULL)
++ {
++ record = Event->freeEventList;
++ Event->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Delete the free mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->freeEventMutex));
++
++ /* Free all pending queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Free all pending events. */
++ while (queue->head != gcvNULL)
++ {
++ record = queue->head;
++ queue->head = record->next;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(record) + gcmSIZEOF(queue->source),
++ "Event record 0x%x is still pending for %d.",
++ record, queue->source
++ );
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead =
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkVERIFY_OK(gckEVENT_FreeQueue(Event, queue));
++ }
++
++ /* Delete the list mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventListMutex));
++
++ /* Delete the atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->freeAtom));
++
++#if gcdSMP
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->pending));
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->interruptCount));
++#endif
++
++ /* Mark the gckEVENT object as unknown. */
++ Event->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckEVENT object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_GetEvent
++**
++** Reserve the next available hardware event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Set to gcvTRUE to force the function to wait if no events are
++** immediately available.
++**
++** gceKERNEL_WHERE Source
++** Source of the event.
++**
++** OUTPUT:
++**
++** gctUINT8 * EventID
++** Reserved event ID.
++*/
++#define gcdINVALID_EVENT_PTR ((gcsEVENT_PTR)gcvMAXUINTPTR_T)
++
++static gceSTATUS
++gckEVENT_GetEvent(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ OUT gctUINT8 * EventID,
++ IN gcsEVENT_PTR Head,
++ IN gceKERNEL_WHERE Source
++ )
++{
++ gctINT i, id;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT32 free;
++
++ gcmkHEADER_ARG("Event=0x%x Head=%p Source=%d", Event, Head, Source);
++
++ while (gcvTRUE)
++ {
++ /* Grab the queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Walk through all events. */
++ id = Event->lastID;
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ gctINT nextID = gckMATH_ModuloInt((id + 1),
++ gcmCOUNTOF(Event->queues));
++
++ if (Event->queues[id].head == gcvNULL)
++ {
++ *EventID = (gctUINT8) id;
++
++ Event->lastID = (gctUINT8) nextID;
++
++ /* Save time stamp of event. */
++ Event->queues[id].head = gcdINVALID_EVENT_PTR;
++ Event->queues[id].stamp = ++(Event->stamp);
++ Event->queues[id].head = Head;
++ Event->queues[id].source = Source;
++
++ gcmkONERROR(gckOS_AtomDecrement(Event->os,
++ Event->freeAtom,
++ &free));
++#if gcdDYNAMIC_SPEED
++ if (free <= gcdDYNAMIC_EVENT_THRESHOLD)
++ {
++ gcmkONERROR(gckOS_BroadcastHurry(
++ Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD - free));
++ }
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os,
++ Event->eventQueueMutex));
++
++ /* Success. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(id),
++ "Using id=%d",
++ id
++ );
++
++ gcmkFOOTER_ARG("*EventID=%u", *EventID);
++ return gcvSTATUS_OK;
++ }
++
++ id = nextID;
++ }
++
++#if gcdDYNAMIC_SPEED
++ /* No free events, speed up the GPU right now! */
++ gcmkONERROR(gckOS_BroadcastHurry(Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD));
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Fail if wait is not requested. */
++ if (!Wait)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Delay a while. */
++ gcmkONERROR(gckOS_Delay(Event->os, 1));
++ }
++
++OnError:
++ if (acquired)
++ {
++ /* Release the queue mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AllocateRecord
++**
++** Allocate a record for the new event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** gcsEVENT_PTR * Record
++** Allocated event record.
++*/
++gceSTATUS
++gckEVENT_AllocateRecord(
++ IN gckEVENT Event,
++ IN gctBOOL AllocateAllowed,
++ OUT gcsEVENT_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Event=0x%x AllocateAllowed=%d", Event, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->freeEventMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Test if we are below the allocation threshold. */
++ if ( (AllocateAllowed && (Event->freeEventCount < gcdEVENT_MIN_THRESHOLD)) ||
++ (Event->freeEventCount == 0) )
++ {
++ /* Allocate a bunch of records. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(Event->os,
++ gcmSIZEOF(gcsEVENT),
++ &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = Event->freeEventList;
++ Event->freeEventList = record;
++ Event->freeEventCount += 1;
++ }
++ }
++
++ *Record = Event->freeEventList;
++ Event->freeEventList = Event->freeEventList->next;
++ Event->freeEventCount -= 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", gcmOPT_POINTER(Record));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AddList
++**
++** Add a new event to the list of events.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_INTERFACE_PTR Interface
++** Pointer to the interface for the event to be added.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record = gcvNULL;
++ gcsEVENT_QUEUE_PTR queue;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Interface=0x%x",
++ Event, Interface);
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, _GC_OBJ_ZONE,
++ "FromWhere=%d AllocateAllowed=%d",
++ FromWhere, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ /* Verify the event command. */
++ gcmkASSERT
++ ( (Interface->command == gcvHAL_FREE_NON_PAGED_MEMORY)
++ || (Interface->command == gcvHAL_FREE_CONTIGUOUS_MEMORY)
++ || (Interface->command == gcvHAL_WRITE_DATA)
++ || (Interface->command == gcvHAL_UNLOCK_VIDEO_MEMORY)
++ || (Interface->command == gcvHAL_SIGNAL)
++ || (Interface->command == gcvHAL_UNMAP_USER_MEMORY)
++ || (Interface->command == gcvHAL_TIMESTAMP)
++ || (Interface->command == gcvHAL_COMMIT_DONE)
++ || (Interface->command == gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER)
++ || (Interface->command == gcvHAL_SYNC_POINT)
++ || (Interface->command == gcvHAL_DESTROY_MMU)
++ );
++
++ /* Validate the source. */
++ if ((FromWhere != gcvKERNEL_COMMAND) && (FromWhere != gcvKERNEL_PIXEL))
++ {
++ /* Invalid argument. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Allocate a free record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, AllocateAllowed, &record));
++
++ /* Termninate the record. */
++ record->next = gcvNULL;
++
++ /* Record the committer. */
++ record->fromKernel = FromKernel;
++
++ /* Copy the event interface into the record. */
++ gckOS_MemCopy(&record->info, Interface, gcmSIZEOF(record->info));
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&record->processID));
++
++ gcmkONERROR(__RemoveRecordFromProcessDB(Event, record));
++
++ /* Handle is belonged to current process, it must be released now. */
++ if (FromKernel == gcvFALSE)
++ {
++ status = _ReleaseVideoMemoryHandle(Event->kernel, record, Interface);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Ingore error because there are other events in the queue. */
++ status = gcvSTATUS_OK;
++ goto OnError;
++ }
++ }
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->eventListMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Do we need to allocate a new queue? */
++ if ((Event->queueTail == gcvNULL) || (Event->queueTail->source < FromWhere))
++ {
++ /* Allocate a new queue. */
++ gcmkONERROR(gckEVENT_AllocateQueue(Event, &queue));
++
++ /* Initialize the queue. */
++ queue->source = FromWhere;
++ queue->head = gcvNULL;
++ queue->next = gcvNULL;
++
++ /* Attach it to the list of allocated queues. */
++ if (Event->queueTail == gcvNULL)
++ {
++ Event->queueHead =
++ Event->queueTail = queue;
++ }
++ else
++ {
++ Event->queueTail->next = queue;
++ Event->queueTail = queue;
++ }
++ }
++ else
++ {
++ queue = Event->queueTail;
++ }
++
++ /* Attach the record to the queue. */
++ if (queue->head == gcvNULL)
++ {
++ queue->head = record;
++ queue->tail = record;
++ }
++ else
++ {
++ queue->tail->next = record;
++ queue->tail = record;
++ }
++
++ /* Unmap user space logical address.
++ * Linux kernel does not support unmap the memory of other process any more since 3.5.
++ * Let's unmap memory of self process before submit the event to gpu.
++ * */
++ switch(Interface->command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical),
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++ break;
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)gcmNAME_TO_PTR(Interface->u.FreeVirtualCommandBuffer.physical);
++ if (buffer->userLogical)
++ {
++ gcmkONERROR(gckOS_DestroyUserVirtualMapping(
++ Event->os,
++ buffer->physical,
++ (gctSIZE_T) Interface->u.FreeVirtualCommandBuffer.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Unlock
++**
++** Schedule an event to unlock virtual memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union that specifies the virtual memory
++** to unlock.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctPOINTER Node,
++ IN gceSURF_TYPE Type
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d Node=0x%x Type=%d",
++ Event, FromWhere, Node, Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Mark the event as an unlock. */
++ iface.command = gcvHAL_UNLOCK_VIDEO_MEMORY;
++ iface.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(Node);
++ iface.u.UnlockVideoMemory.type = Type;
++ iface.u.UnlockVideoMemory.asynchroneous = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeNonPagedMemory
++**
++** Schedule an event to free non-paged memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of non-paged memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of non-paged memory to free.
++**
++** gctPOINTER Logical
++** Logical address of non-paged memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_NON_PAGED_MEMORY;
++ iface.u.FreeNonPagedMemory.bytes = Bytes;
++ iface.u.FreeNonPagedMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeNonPagedMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER;
++ iface.u.FreeVirtualCommandBuffer.bytes = Bytes;
++ iface.u.FreeVirtualCommandBuffer.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeContigiuousMemory
++**
++** Schedule an event to free contiguous memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of contiguous memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of contiguous memory to free.
++**
++** gctPOINTER Logical
++** Logical address of contiguous memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_CONTIGUOUS_MEMORY;
++ iface.u.FreeContiguousMemory.bytes = Bytes;
++ iface.u.FreeContiguousMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeContiguousMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Signal
++**
++** Schedule an event to trigger a signal.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x Signal=0x%x FromWhere=%d",
++ Event, Signal, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Mark the event as a signal. */
++ iface.command = gcvHAL_SIGNAL;
++ iface.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++ iface.u.Signal.auxSignal = 0;
++ iface.u.Signal.process = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_CommitDone
++**
++** Schedule an event to wake up work thread when commit is done by GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ iface.command = gcvHAL_COMMIT_DONE;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckEVENT_DestroyMmu(
++ IN gckEVENT Event,
++ IN gckMMU Mmu,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ iface.command = gcvHAL_DESTROY_MMU;
++ iface.u.DestroyMmu.mmu = gcmPTR_TO_UINT64(Mmu);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckEVENT_Submit
++**
++** Submit the current event queue to the GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Submit requires one vacant event; if Wait is set to not zero,
++** and there are no vacant events at this time, the function will
++** wait until an event becomes vacant so that submission of the
++** queue is successful.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower,
++ IN gctBOOL FromCommand
++ )
++{
++ gceSTATUS status;
++ gctUINT8 id = 0xFF;
++ gcsEVENT_QUEUE_PTR queue;
++ gctBOOL acquired = gcvFALSE;
++ gckCOMMAND command = gcvNULL;
++ gctBOOL commitEntered = gcvFALSE;
++#if !gcdNULL_DRIVER
++ gctUINT32 bytes;
++ gctPOINTER buffer;
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 oldValue;
++#endif
++
++ gctUINT32 flushBytes;
++ gctUINT32 executeBytes;
++ gckHARDWARE hardware;
++
++ gceKERNEL_FLUSH flush = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Wait=%d", Event, Wait);
++
++ /* Get gckCOMMAND object. */
++ command = Event->kernel->command;
++ hardware = Event->kernel->hardware;
++
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ gckOS_GetTicks(&Event->lastCommitStamp);
++
++ /* Are there event queues? */
++ if (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, FromPower));
++ commitEntered = gcvTRUE;
++
++ /* Process all queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the list mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventListMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Allocate an event ID. */
++ gcmkONERROR(gckEVENT_GetEvent(Event, Wait, &id, queue->head, queue->source));
++
++ /* Copy event list to event ID queue. */
++ Event->queues[id].head = queue->head;
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead = gcvNULL;
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkONERROR(gckEVENT_FreeQueue(Event, queue));
++
++ /* Release the list mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ acquired = gcvFALSE;
++
++ /* Determine cache needed to flush. */
++ gcmkVERIFY_OK(_QueryFlush(Event, Event->queues[id].head, &flush));
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkVERIFY_OK(gckOS_AtomIncrement(
++ Event->os,
++ Event->interruptCount,
++ &oldValue
++ ));
++#endif
++
++#if gcdNULL_DRIVER
++ /* Notify immediately on infinite hardware. */
++ gcmkONERROR(gckEVENT_Interrupt(Event, 1 << id));
++
++ gcmkONERROR(gckEVENT_Notify(Event, 0));
++#else
++ /* Get the size of the hardware event. */
++ gcmkONERROR(gckHARDWARE_Event(
++ hardware,
++ gcvNULL,
++ id,
++ Event->queues[id].source,
++ &bytes
++ ));
++
++ /* Get the size of flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ hardware,
++ flush,
++ gcvNULL,
++ &flushBytes
++ ));
++
++ bytes += flushBytes;
++
++ /* Total bytes need to execute. */
++ executeBytes = bytes;
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command, bytes, &buffer, &bytes));
++
++ /* Set the flush in the command queue. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ hardware,
++ flush,
++ buffer,
++ &flushBytes
++ ));
++
++ /* Advance to next command. */
++ buffer = (gctUINT8_PTR)buffer + flushBytes;
++
++ /* Set the hardware event in the command queue. */
++ gcmkONERROR(gckHARDWARE_Event(
++ hardware,
++ buffer,
++ id,
++ Event->queues[id].source,
++ &bytes
++ ));
++
++ /* Advance to next command. */
++ buffer = (gctUINT8_PTR)buffer + bytes;
++
++ /* Execute the hardware event. */
++ gcmkONERROR(gckCOMMAND_Execute(command, executeBytes));
++#endif
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, FromPower));
++
++#if !gcdNULL_DRIVER
++ if (!FromCommand)
++ gcmkVERIFY_OK(_TryToIdleGPU(Event));
++#endif
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Need to unroll the mutex acquire. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, FromPower));
++ }
++
++ if (id != 0xFF)
++ {
++ /* Need to unroll the event allocation. */
++ Event->queues[id].head = gcvNULL;
++ }
++
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Broadcast GPU stuck. */
++ status = gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_STUCK);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Commit
++**
++** Commit an event queue from the user.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsQUEUE_PTR Queue
++** User event queue.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ )
++{
++ gceSTATUS status;
++ gcsQUEUE_PTR record = gcvNULL, next;
++ gctUINT32 processID;
++ gctBOOL needCopy = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Queue=0x%x", Event, Queue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Query if we need to copy the client data. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Event->os, processID, &needCopy));
++
++ /* Loop while there are records in the queue. */
++ while (Queue != gcvNULL)
++ {
++ gcsQUEUE queue;
++
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ record = &queue;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(Event->os,
++ record,
++ Queue,
++ gcmSIZEOF(gcsQUEUE)));
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(
++ gckEVENT_AddList(Event, &record->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE));
++
++ /* Next record in the queue. */
++ next = gcmUINT64_TO_PTR(record->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ record = gcvNULL;
++ }
++
++ Queue = next;
++ }
++
++ /* Submit the event list. */
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE, gcvFALSE));
++
++ /* Success */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((record != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Compose
++**
++** Schedule a composition event and start a composition.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_COMPOSE_PTR Info
++** Pointer to the composition structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ )
++{
++ gceSTATUS status;
++ gcsEVENT_PTR headRecord;
++ gcsEVENT_PTR tailRecord;
++ gcsEVENT_PTR tempRecord;
++ gctUINT8 id = 0xFF;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Event=0x%x Info=0x%x", Event, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ headRecord = tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->process;
++ tempRecord->info.u.Signal.signal = Info->signal;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++
++ /* Allocate another record for user signal #1. */
++ if (gcmUINT64_TO_PTR(Info->userSignal1) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++ tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++ tempRecord->info.u.Signal.signal = Info->userSignal1;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Allocate another record for user signal #2. */
++ if (gcmUINT64_TO_PTR(Info->userSignal2) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++ tempRecord->info.u.Signal.signal = Info->userSignal2;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Allocate an event ID. */
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, headRecord, gcvKERNEL_PIXEL));
++
++ /* Start composition. */
++ gcmkONERROR(gckHARDWARE_Compose(
++ Event->kernel->hardware, processID,
++ gcmUINT64_TO_PTR(Info->physical), gcmUINT64_TO_PTR(Info->logical), Info->offset, Info->size, id
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Interrupt
++**
++** Called by the interrupt service routine to store the triggered interrupt
++** mask to be later processed by gckEVENT_Notify.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 Data
++** Mask for the 32 interrupts.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++ IN gctUINT32 Data
++ )
++{
++ unsigned long flags;
++ gcmkHEADER_ARG("Event=0x%x Data=0x%x", Event, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ if (Data & 0x20000000)
++ {
++ gckENTRYDATA data;
++ gctUINT32 idle;
++ Data &= ~0x20000000;
++
++ /* Get first entry information. */
++ gcmkVERIFY_OK(
++ gckENTRYQUEUE_Dequeue(&Event->kernel->command->queue, &data));
++
++ /* Make sure FE is idle. */
++ do
++ {
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(
++ Event->os,
++ Event->kernel->core,
++ 0x4,
++ &idle));
++ }
++ while (idle != 0x7FFFFFFF);
++
++ /* Start Command Parser. */
++ gcmkVERIFY_OK(gckHARDWARE_Execute(
++ Event->kernel->hardware,
++ data->physical,
++ data->bytes
++ ));
++ }
++
++ /* Combine current interrupt status with pending flags. */
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ gckOS_AtomSetMask(Event->pending, Data);
++#else
++ Event->pending |= Data;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++#if gcdINTERRUPT_STATISTIC
++ {
++ gctINT j = 0;
++ gctINT32 oldValue;
++
++ for (j = 0; j < gcmCOUNTOF(Event->queues); j++)
++ {
++ if ((Data & (1 << j)))
++ {
++ gcmkVERIFY_OK(gckOS_AtomDecrement(Event->os,
++ Event->interruptCount,
++ &oldValue));
++ }
++ }
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Notify
++**
++** Process all triggered interrupts.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctINT i;
++ gcsEVENT_QUEUE * queue;
++ gctUINT mask = 0;
++ gctBOOL acquired = gcvFALSE;
++ gctPOINTER info;
++ gctSIGNAL signal;
++ gctUINT pending = 0;
++ gckKERNEL kernel = Event->kernel;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctINT eventNumber = 0;
++#endif
++ gctINT32 free;
++ gckVIDMEM_NODE nodeObject;
++ gcuVIDMEM_NODE_PTR node;
++ unsigned long flags;
++
++ gcmkHEADER_ARG("Event=0x%x IDs=0x%x", Event, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ gcmDEBUG_ONLY(
++ if (IDs != 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++ for (;;)
++ {
++ gcsEVENT_PTR record;
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ gckOS_AtomGet(Event->os, Event->pending, (gctINT32_PTR)&pending);
++#else
++ pending = Event->pending;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ if (pending & 0x80000000)
++ {
++ gctUINT32 AQAxiStatus = 0;
++ gckOS_ReadRegisterEx(Event->os, Event->kernel->hardware->core, 0xC, &AQAxiStatus);
++
++ gcmkPRINT("GPU[%d]: AXI BUS ERROR, AQAxiStatus=0x%x\n", Event->kernel->hardware->core, AQAxiStatus);
++ pending &= 0x7FFFFFFF;
++ }
++
++ if (pending & 0x40000000)
++ {
++ gckHARDWARE_DumpMMUException(Event->kernel->hardware);
++
++ pending &= 0xBFFFFFFF;
++ }
++
++ if (pending == 0)
++ {
++ /* No more pending interrupts - done. */
++ break;
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Pending interrupts 0x%x",
++ pending
++ );
++
++ queue = gcvNULL;
++
++ /* Grab the mutex queue. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmDEBUG_ONLY(
++ if (IDs == 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++ /* Find the oldest pending interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (pending & (1 << i))
++ )
++ {
++ if ((queue == gcvNULL)
++ || (Event->queues[i].stamp < queue->stamp)
++ )
++ {
++ queue = &Event->queues[i];
++ mask = 1 << i;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ eventNumber = i;
++#endif
++ }
++ }
++ }
++
++ if (queue == gcvNULL)
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Interrupts 0x%x are not pending.",
++ pending
++ );
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ gckOS_AtomClearMask(Event->pending, pending);
++#else
++ Event->pending &= ~pending;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++ break;
++ }
++
++ /* Check whether there is a missed interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (Event->queues[i].stamp < queue->stamp)
++ && (Event->queues[i].source <= queue->source)
++ )
++ {
++ gcmkTRACE_N(
++ gcvLEVEL_ERROR,
++ gcmSIZEOF(i) + gcmSIZEOF(Event->queues[i].stamp),
++ "Event %d lost (stamp %llu)",
++ i, Event->queues[i].stamp
++ );
++
++ /* Use this event instead. */
++ queue = &Event->queues[i];
++ mask = 0;
++ }
++ }
++
++ if (mask != 0)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(eventNumber),
++ "Processing interrupt %d",
++ eventNumber
++ );
++#endif
++ }
++
++ spin_lock_irqsave(&Event->kernel->irq_lock, flags);
++#if gcdSMP
++ gckOS_AtomClearMask(Event->pending, mask);
++#else
++ Event->pending &= ~mask;
++#endif
++ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags);
++
++ /* Grab the event head. */
++ record = queue->head;
++
++ /* Now quickly clear its event list. */
++ queue->head = gcvNULL;
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Increase the number of free events. */
++ gcmkONERROR(gckOS_AtomIncrement(Event->os, Event->freeAtom, &free));
++
++ /* Walk all events for this interrupt. */
++ while (record != gcvNULL)
++ {
++ gcsEVENT_PTR recordNext;
++ gctPOINTER logical;
++
++ /* Grab next record. */
++ recordNext = record->next;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Processing event type: %d",
++ record->info.command
++ );
++
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_NON_PAGED_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical));
++
++ /* Free non-paged memory. */
++ status = gckOS_FreeNonPagedMemory(
++ Event->os,
++ (gctSIZE_T) record->info.u.FreeNonPagedMemory.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeNonPagedMemory.logical));
++
++ gcmRELEASE_NAME(record->info.u.FreeNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_CONTIGUOUS_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical));
++
++ /* Unmap the user memory. */
++ status = gckOS_FreeContiguous(
++ Event->os,
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeContiguousMemory.logical),
++ (gctSIZE_T) record->info.u.FreeContiguousMemory.bytes);
++
++ gcmRELEASE_NAME(record->info.u.FreeContiguousMemory.physical);
++ break;
++
++ case gcvHAL_WRITE_DATA:
++ /* Convert physical into logical address. */
++ gcmkERR_BREAK(
++ gckOS_MapPhysical(Event->os,
++ record->info.u.WriteData.address,
++ gcmSIZEOF(gctUINT32),
++ &logical));
++
++ /* Write data. */
++ gcmkERR_BREAK(
++ gckOS_WriteMemory(Event->os,
++ logical,
++ record->info.u.WriteData.data));
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(
++ gckOS_UnmapPhysical(Event->os,
++ logical,
++ gcmSIZEOF(gctUINT32)));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNLOCK_VIDEO_MEMORY: 0x%x",
++ record->info.u.UnlockVideoMemory.node);
++
++ nodeObject = gcmUINT64_TO_PTR(record->info.u.UnlockVideoMemory.node);
++
++ node = nodeObject->node;
++
++ /* Unlock. */
++ status = gckVIDMEM_Unlock(
++ Event->kernel,
++ nodeObject,
++ record->info.u.UnlockVideoMemory.type,
++ gcvNULL);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Unlock(
++ Event->kernel,
++ nodeObject,
++ record->processID
++ ));
++#endif
++
++ status = gckVIDMEM_NODE_Dereference(Event->kernel, nodeObject);
++ break;
++
++ case gcvHAL_SIGNAL:
++ signal = gcmUINT64_TO_PTR(record->info.u.Signal.signal);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_SIGNAL: 0x%x",
++ signal);
++
++ /* User signal. */
++ gcmkERR_BREAK(
++ gckOS_UserSignal(Event->os,
++ signal,
++ gcmUINT64_TO_PTR(record->info.u.Signal.process)));
++
++ gcmkASSERT(record->info.u.Signal.auxSignal == 0);
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ info = gcmNAME_TO_PTR(record->info.u.UnmapUserMemory.info);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNMAP_USER_MEMORY: 0x%x",
++ info);
++
++ /* Unmap the user memory. */
++ status = gckOS_UnmapUserMemory(
++ Event->os,
++ Event->kernel->core,
++ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory),
++ (gctSIZE_T) record->info.u.UnmapUserMemory.size,
++ info,
++ record->info.u.UnmapUserMemory.address);
++
++ gcmRELEASE_NAME(record->info.u.UnmapUserMemory.info);
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_TIMESTAMP: %d %d",
++ record->info.u.TimeStamp.timer,
++ record->info.u.TimeStamp.request);
++
++ /* Process the timestamp. */
++ switch (record->info.u.TimeStamp.request)
++ {
++ case 0:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ stopTime);
++ break;
++
++ case 1:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ startTime);
++ break;
++
++ default:
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.u.TimeStamp.request),
++ "Invalid timestamp request: %d",
++ record->info.u.TimeStamp.request
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyVirtualCommandBuffer(Event->kernel,
++ (gctSIZE_T) record->info.u.FreeVirtualCommandBuffer.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeVirtualCommandBuffer.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeVirtualCommandBuffer.logical)
++ ));
++ gcmRELEASE_NAME(record->info.u.FreeVirtualCommandBuffer.physical);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ syncPoint = gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint);
++ status = gckOS_SignalSyncPoint(Event->os, syncPoint);
++ }
++ break;
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++ case gcvHAL_DESTROY_MMU:
++ status = gckMMU_Destroy(gcmUINT64_TO_PTR(record->info.u.DestroyMmu.mmu));
++ break;
++#endif
++
++ case gcvHAL_COMMIT_DONE:
++ break;
++
++ default:
++ /* Invalid argument. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Unknown event type: %d",
++ record->info.command
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Make sure there are no errors generated. */
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(status),
++ "Event produced status: %d(%s)",
++ status, gckOS_DebugStatus2Name(status));
++ }
++
++ /* Free the event. */
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++
++ /* Advance to next record. */
++ record = recordNext;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Handled interrupt 0x%x", mask);
++ }
++
++ if (IDs == 0)
++ {
++ gcmkONERROR(_TryToIdleGPU(Event));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_FreeProcess
++**
++** Free all events owned by a particular process ID.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID of the process to be freed up.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ )
++{
++ gctSIZE_T i;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record, next;
++ gceSTATUS status;
++ gcsEVENT_PTR deleteHead, deleteTail;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%d", Event, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Walk through all queues. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* Grab the event queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Grab the mutex head. */
++ record = Event->queues[i].head;
++ Event->queues[i].head = gcvNULL;
++ Event->queues[i].tail = gcvNULL;
++ deleteHead = gcvNULL;
++ deleteTail = gcvNULL;
++
++ while (record != gcvNULL)
++ {
++ next = record->next;
++ if (record->processID == ProcessID)
++ {
++ if (deleteHead == gcvNULL)
++ {
++ deleteHead = record;
++ }
++ else
++ {
++ deleteTail->next = record;
++ }
++
++ deleteTail = record;
++ }
++ else
++ {
++ if (Event->queues[i].head == gcvNULL)
++ {
++ Event->queues[i].head = record;
++ }
++ else
++ {
++ Event->queues[i].tail->next = record;
++ }
++
++ Event->queues[i].tail = record;
++ }
++
++ record->next = gcvNULL;
++ record = next;
++ }
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Loop through the entire list of events. */
++ for (record = deleteHead; record != gcvNULL; record = next)
++ {
++ /* Get the next event record. */
++ next = record->next;
++
++ /* Free the event record. */
++ gcmkONERROR(gckEVENT_FreeRecord(Event, record));
++ }
++ }
++ }
++
++ gcmkONERROR(_TryToIdleGPU(Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release the event queue mutex. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_Stop
++**
++** Stop the hardware using the End event mechanism.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctUINT32 * waitSize
++ )
++{
++ gceSTATUS status;
++ /* gctSIZE_T waitSize;*/
++ gcsEVENT_PTR record;
++ gctUINT8 id = 0xFF;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%u Handle=0x%x Logical=0x%x "
++ "Signal=0x%x",
++ Event, ProcessID, Handle, Logical, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Submit the current event queue. */
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE, gcvFALSE));
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &record));
++
++ /* Initialize the record. */
++ record->next = gcvNULL;
++ record->processID = ProcessID;
++ record->info.command = gcvHAL_SIGNAL;
++ record->info.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++ record->info.u.Signal.auxSignal = 0;
++ record->info.u.Signal.process = 0;
++
++
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, record, gcvKERNEL_PIXEL));
++
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ Event->kernel->hardware, Logical, waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Event->os,
++ ProcessID,
++ gcvNULL,
++ (gctUINT32)Handle,
++ Logical,
++ *waitSize
++ ));
++#endif
++
++ /* Wait for the signal. */
++ gcmkONERROR(gckOS_WaitSignal(Event->os, Signal, gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_PrintRecord(
++ gcsEVENT_PTR record
++ )
++{
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_NON_PAGED_MEMORY");
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_CONTIGUOUS_MEMORY");
++ break;
++
++ case gcvHAL_WRITE_DATA:
++ gcmkPRINT(" gcvHAL_WRITE_DATA");
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkPRINT(" gcvHAL_UNLOCK_VIDEO_MEMORY");
++ break;
++
++ case gcvHAL_SIGNAL:
++ gcmkPRINT(" gcvHAL_SIGNAL process=%d signal=0x%x",
++ record->info.u.Signal.process,
++ record->info.u.Signal.signal);
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkPRINT(" gcvHAL_UNMAP_USER_MEMORY");
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkPRINT(" gcvHAL_TIMESTAMP");
++ break;
++
++ case gcvHAL_COMMIT_DONE:
++ gcmkPRINT(" gcvHAL_COMMIT_DONE");
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkPRINT(" gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER logical=0x%08x",
++ record->info.u.FreeVirtualCommandBuffer.logical);
++ break;
++
++ case gcvHAL_SYNC_POINT:
++ gcmkPRINT(" gcvHAL_SYNC_POINT syncPoint=0x%08x",
++ gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint));
++
++ break;
++
++ case gcvHAL_DESTROY_MMU:
++ gcmkPRINT(" gcvHAL_DESTORY_MMU mmu=0x%08x",
++ gcmUINT64_TO_PTR(record->info.u.DestroyMmu.mmu));
++
++ break;
++ default:
++ gcmkPRINT(" Illegal Event %d", record->info.command);
++ break;
++ }
++}
++
++/*******************************************************************************
++** gckEVENT_Dump
++**
++** Dump record in event queue when stuck happens.
++** No protection for the event queue.
++**/
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_QUEUE_PTR queueHead = Event->queueHead;
++ gcsEVENT_QUEUE_PTR queue;
++ gcsEVENT_PTR record = gcvNULL;
++ gctINT i;
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 pendingInterrupt;
++ gctUINT32 intrAcknowledge;
++#endif
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** EVENT STATE DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkPRINT(" Unsumbitted Event:");
++ while(queueHead)
++ {
++ queue = queueHead;
++ record = queueHead->head;
++
++ gcmkPRINT(" [%x]:", queue);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++
++ if (queueHead == Event->queueTail)
++ {
++ queueHead = gcvNULL;
++ }
++ else
++ {
++ queueHead = queueHead->next;
++ }
++ }
++
++ gcmkPRINT(" Untriggered Event:");
++ for (i = 0; i < gcmCOUNTOF(Event->queues); i++)
++ {
++ queue = &Event->queues[i];
++ record = queue->head;
++
++ gcmkPRINT(" [%d]:", i);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ gckOS_AtomGet(Event->os, Event->interruptCount, &pendingInterrupt);
++ gcmkPRINT(" Number of Pending Interrupt: %d", pendingInterrupt);
++
++ if (Event->kernel->recovery == 0)
++ {
++ gckOS_ReadRegisterEx(
++ Event->os,
++ Event->kernel->core,
++ 0x10,
++ &intrAcknowledge
++ );
++
++ gcmkPRINT(" INTR_ACKNOWLEDGE=0x%x", intrAcknowledge);
++ }
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel.h 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,1353 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_h_
++#define __gc_hal_kernel_h_
++
++#include <linux/spinlock.h>
++
++#include "gc_hal.h"
++#include "gc_hal_kernel_hardware.h"
++#include "gc_hal_driver.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++/*******************************************************************************
++***** New MMU Defination *******************************************************/
++#define gcdMMU_MTLB_SHIFT 22
++#define gcdMMU_STLB_4K_SHIFT 12
++#define gcdMMU_STLB_64K_SHIFT 16
++
++#define gcdMMU_MTLB_BITS (32 - gcdMMU_MTLB_SHIFT)
++#define gcdMMU_PAGE_4K_BITS gcdMMU_STLB_4K_SHIFT
++#define gcdMMU_STLB_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_4K_BITS)
++#define gcdMMU_PAGE_64K_BITS gcdMMU_STLB_64K_SHIFT
++#define gcdMMU_STLB_64K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_64K_BITS)
++
++#define gcdMMU_MTLB_ENTRY_NUM (1 << gcdMMU_MTLB_BITS)
++#define gcdMMU_MTLB_SIZE (gcdMMU_MTLB_ENTRY_NUM << 2)
++#define gcdMMU_STLB_4K_ENTRY_NUM (1 << gcdMMU_STLB_4K_BITS)
++#define gcdMMU_STLB_4K_SIZE (gcdMMU_STLB_4K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_4K_SIZE (1 << gcdMMU_STLB_4K_SHIFT)
++#define gcdMMU_STLB_64K_ENTRY_NUM (1 << gcdMMU_STLB_64K_BITS)
++#define gcdMMU_STLB_64K_SIZE (gcdMMU_STLB_64K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_64K_SIZE (1 << gcdMMU_STLB_64K_SHIFT)
++
++#define gcdMMU_MTLB_MASK (~((1U << gcdMMU_MTLB_SHIFT)-1))
++#define gcdMMU_STLB_4K_MASK ((~0U << gcdMMU_STLB_4K_SHIFT) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_4K_MASK (gcdMMU_PAGE_4K_SIZE - 1)
++#define gcdMMU_STLB_64K_MASK ((~((1U << gcdMMU_STLB_64K_SHIFT)-1)) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_64K_MASK (gcdMMU_PAGE_64K_SIZE - 1)
++
++/* Page offset definitions. */
++#define gcdMMU_OFFSET_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_4K_BITS)
++#define gcdMMU_OFFSET_4K_MASK ((1U << gcdMMU_OFFSET_4K_BITS) - 1)
++#define gcdMMU_OFFSET_16K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_16K_BITS)
++#define gcdMMU_OFFSET_16K_MASK ((1U << gcdMMU_OFFSET_16K_BITS) - 1)
++
++#define gcdMMU_MTLB_PRESENT 0x00000001
++#define gcdMMU_MTLB_EXCEPTION 0x00000002
++#define gcdMMU_MTLB_4K_PAGE 0x00000000
++
++#define gcdMMU_STLB_PRESENT 0x00000001
++#define gcdMMU_STLB_EXCEPTION 0x00000002
++#define gcdMMU_STLB_4K_PAGE 0x00000000
++
++/*******************************************************************************
++***** Stuck Dump Level ********************************************************/
++
++#define gcdSTUCK_DUMP_MINIMAL 1
++#define gcdSTUCK_DUMP_MIDDLE 2
++#define gcdSTUCK_DUMP_MAXIMAL 3
++
++/*******************************************************************************
++***** Process Secure Cache ****************************************************/
++
++#define gcdSECURE_CACHE_LRU 1
++#define gcdSECURE_CACHE_LINEAR 2
++#define gcdSECURE_CACHE_HASH 3
++#define gcdSECURE_CACHE_TABLE 4
++
++#define gcvPAGE_TABLE_DIRTY_BIT_OTHER (1 << 0)
++#define gcvPAGE_TABLE_DIRTY_BIT_FE (1 << 1)
++
++typedef struct _gcskLOGICAL_CACHE * gcskLOGICAL_CACHE_PTR;
++typedef struct _gcskLOGICAL_CACHE gcskLOGICAL_CACHE;
++struct _gcskLOGICAL_CACHE
++{
++ /* Logical address. */
++ gctPOINTER logical;
++
++ /* DMAable address. */
++ gctUINT32 dma;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Pointer to the previous and next hash tables. */
++ gcskLOGICAL_CACHE_PTR nextHash;
++ gcskLOGICAL_CACHE_PTR prevHash;
++#endif
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ /* Pointer to the previous and next slot. */
++ gcskLOGICAL_CACHE_PTR next;
++ gcskLOGICAL_CACHE_PTR prev;
++#endif
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ /* Time stamp. */
++ gctUINT64 stamp;
++#endif
++};
++
++typedef struct _gcskSECURE_CACHE * gcskSECURE_CACHE_PTR;
++typedef struct _gcskSECURE_CACHE
++{
++ /* Cache memory. */
++ gcskLOGICAL_CACHE cache[1 + gcdSECURE_CACHE_SLOTS];
++
++ /* Last known index for LINEAR mode. */
++ gcskLOGICAL_CACHE_PTR cacheIndex;
++
++ /* Current free slot for LINEAR mode. */
++ gctUINT32 cacheFree;
++
++ /* Time stamp for LINEAR mode. */
++ gctUINT64 cacheStamp;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Hash table for HASH mode. */
++ gcskLOGICAL_CACHE hash[256];
++#endif
++}
++gcskSECURE_CACHE;
++
++/*******************************************************************************
++***** Process Database Management *********************************************/
++
++typedef enum _gceDATABASE_TYPE
++{
++ gcvDB_VIDEO_MEMORY = 1, /* Video memory created. */
++ gcvDB_COMMAND_BUFFER, /* Command Buffer. */
++ gcvDB_NON_PAGED, /* Non paged memory. */
++ gcvDB_CONTIGUOUS, /* Contiguous memory. */
++ gcvDB_SIGNAL, /* Signal. */
++ gcvDB_VIDEO_MEMORY_LOCKED, /* Video memory locked. */
++ gcvDB_CONTEXT, /* Context */
++ gcvDB_IDLE, /* GPU idle. */
++ gcvDB_MAP_MEMORY, /* Map memory */
++ gcvDB_MAP_USER_MEMORY, /* Map user memory */
++ gcvDB_SYNC_POINT, /* Sync point. */
++ gcvDB_SHBUF, /* Shared buffer. */
++}
++gceDATABASE_TYPE;
++
++#define gcdDATABASE_TYPE_MASK 0x000000FF
++#define gcdDB_VIDEO_MEMORY_TYPE_MASK 0x0000FF00
++#define gcdDB_VIDEO_MEMORY_TYPE_SHIFT 8
++
++#define gcdDB_VIDEO_MEMORY_POOL_MASK 0x00FF0000
++#define gcdDB_VIDEO_MEMORY_POOL_SHIFT 16
++
++typedef struct _gcsDATABASE_RECORD * gcsDATABASE_RECORD_PTR;
++typedef struct _gcsDATABASE_RECORD
++{
++ /* Pointer to kernel. */
++ gckKERNEL kernel;
++
++ /* Pointer to next database record. */
++ gcsDATABASE_RECORD_PTR next;
++
++ /* Type of record. */
++ gceDATABASE_TYPE type;
++
++ /* Data for record. */
++ gctPOINTER data;
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++}
++gcsDATABASE_RECORD;
++
++typedef struct _gcsDATABASE * gcsDATABASE_PTR;
++typedef struct _gcsDATABASE
++{
++ /* Pointer to next entry is hash list. */
++ gcsDATABASE_PTR next;
++ gctSIZE_T slot;
++
++ /* Process ID. */
++ gctUINT32 processID;
++
++ /* Sizes to query. */
++ gcsDATABASE_COUNTERS vidMem;
++ gcsDATABASE_COUNTERS nonPaged;
++ gcsDATABASE_COUNTERS contiguous;
++ gcsDATABASE_COUNTERS mapUserMemory;
++ gcsDATABASE_COUNTERS mapMemory;
++ gcsDATABASE_COUNTERS virtualCommandBuffer;
++
++ gcsDATABASE_COUNTERS vidMemType[gcvSURF_NUM_TYPES];
++ /* Counter for each video memory pool. */
++ gcsDATABASE_COUNTERS vidMemPool[gcvPOOL_NUMBER_OF_POOLS];
++ gctPOINTER counterMutex;
++
++ /* Idle time management. */
++ gctUINT64 lastIdle;
++ gctUINT64 idle;
++
++ /* Pointer to database. */
++ gcsDATABASE_RECORD_PTR list[48];
++
++ gctPOINTER handleDatabase;
++ gctPOINTER handleDatabaseMutex;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++}
++gcsDATABASE;
++
++typedef struct _gcsRECORDER * gckRECORDER;
++
++typedef struct _gcsFDPRIVATE * gcsFDPRIVATE_PTR;
++typedef struct _gcsFDPRIVATE
++{
++ gctINT (* release) (gcsFDPRIVATE_PTR Private);
++}
++gcsFDPRIVATE;
++
++/* Create a process database that will contain all its allocations. */
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Add a record to the process database. */
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ );
++
++/* Remove a record to the process database. */
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ );
++
++/* Destroy the process database. */
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Find a record to the process database. */
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ );
++
++/* Query the process database. */
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ );
++
++/* Dump the process database. */
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ );
++
++/* Dump the video memory usage for process specified. */
++gceSTATUS
++gckKERNEL_DumpVidMemUsage(
++ IN gckKERNEL Kernel,
++ IN gctINT32 ProcessID
++ );
++
++gceSTATUS
++gckKERNEL_FindDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ OUT gcsDATABASE_PTR * Database
++ );
++
++gceSTATUS
++gckKERNEL_FindHandleDatbase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gctPOINTER * HandleDatabase,
++ OUT gctPOINTER * HandleDatabaseMutex
++ );
++
++gceSTATUS
++gckKERNEL_GetProcessMMU(
++ IN gckKERNEL Kernel,
++ OUT gckMMU * Mmu
++ );
++
++gceSTATUS
++gckKERNEL_SetRecovery(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Recovery,
++ IN gctUINT32 StuckDump
++ );
++
++gceSTATUS
++gckMMU_FlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 Physical
++ );
++
++gceSTATUS
++gckMMU_GetPageEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctUINT32_PTR *PageTable
++ );
++
++gceSTATUS
++gckMMU_FreePagesEx(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctSIZE_T PageCount
++ );
++
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ );
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ );
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ );
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ );
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ );
++
++/* Pointer rename */
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ );
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++/*******************************************************************************
++********* Timer Management ****************************************************/
++typedef struct _gcsTIMER * gcsTIMER_PTR;
++typedef struct _gcsTIMER
++{
++ /* Start and Stop time holders. */
++ gctUINT64 startTime;
++ gctUINT64 stopTime;
++}
++gcsTIMER;
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckDB object. */
++struct _gckDB
++{
++ /* Database management. */
++ gcsDATABASE_PTR db[16];
++ gctPOINTER dbMutex;
++ gcsDATABASE_PTR freeDatabase;
++ gcsDATABASE_RECORD_PTR freeRecord;
++ gcsDATABASE_PTR lastDatabase;
++ gctUINT32 lastProcessID;
++ gctUINT64 lastIdle;
++ gctUINT64 idleTime;
++ gctUINT64 lastSlowdown;
++ gctUINT64 lastSlowdownIdle;
++ gctPOINTER nameDatabase;
++ gctPOINTER nameDatabaseMutex;
++
++ gctPOINTER pointerDatabase;
++ gctPOINTER pointerDatabaseMutex;
++};
++
++typedef struct _gckVIRTUAL_COMMAND_BUFFER * gckVIRTUAL_COMMAND_BUFFER_PTR;
++typedef struct _gckVIRTUAL_COMMAND_BUFFER
++{
++ gctPHYS_ADDR physical;
++ gctPOINTER userLogical;
++ gctPOINTER kernelLogical;
++ gctSIZE_T bytes;
++ gctSIZE_T pageCount;
++ gctPOINTER pageTable;
++ gctUINT32 gpuAddress;
++ gctUINT pid;
++ gckVIRTUAL_COMMAND_BUFFER_PTR next;
++ gckVIRTUAL_COMMAND_BUFFER_PTR prev;
++ gckKERNEL kernel;
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++}
++gckVIRTUAL_COMMAND_BUFFER;
++
++/* gckKERNEL object. */
++struct _gckKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Pointer to gckCOMMAND object. */
++ gckCOMMAND command;
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckMMU mmu;
++
++ /* Arom holding number of clients. */
++ gctPOINTER atomClients;
++
++#if VIVANTE_PROFILER
++ /* Enable profiling */
++ gctBOOL profileEnable;
++ /* Clear profile register or not*/
++ gctBOOL profileCleanRegister;
++#endif
++
++ /* Database management. */
++ gckDB db;
++ gctBOOL dbCreated;
++
++ gctUINT64 resetTimeStamp;
++
++ /* Pointer to gckEVENT object. */
++ gcsTIMER timers[8];
++ gctUINT32 timeOut;
++
++#if gcdENABLE_VG
++ gckVGKERNEL vg;
++#endif
++
++ /* Virtual command buffer list. */
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferHead;
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferTail;
++ gctPOINTER virtualBufferLock;
++
++ /* Enable virtual command buffer. */
++ gctBOOL virtualCommandBuffer;
++
++#if gcdDVFS
++ gckDVFS dvfs;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gctHANDLE timeline;
++#endif
++
++ /* Enable recovery. */
++ gctBOOL recovery;
++
++ /* Level of dump information after stuck. */
++ gctUINT stuckDump;
++
++ /* Timer to monitor GPU stuck. */
++ gctPOINTER monitorTimer;
++
++ /* Flag to quit monitor timer. */
++ gctBOOL monitorTimerStop;
++
++ /* Monitor states. */
++ gctBOOL monitoring;
++ gctUINT32 lastCommitStamp;
++ gctUINT32 timer;
++ gctUINT32 restoreAddress;
++ gctUINT32 restoreMask;
++
++ spinlock_t irq_lock;
++};
++
++struct _FrequencyHistory
++{
++ gctUINT32 frequency;
++ gctUINT32 count;
++};
++
++/* gckDVFS object. */
++struct _gckDVFS
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gctPOINTER timer;
++ gctUINT32 pollingTime;
++ gctBOOL stop;
++ gctUINT32 totalConfig;
++ gctUINT32 loads[8];
++ gctUINT8 currentScale;
++ struct _FrequencyHistory frequencyHistory[16];
++};
++
++/* gckCOMMAND object. */
++struct _gckCOMMAND
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to required object. */
++ gckKERNEL kernel;
++ gckOS os;
++
++ /* Number of bytes per page. */
++ gctUINT32 pageSize;
++
++ /* Current pipe select. */
++ gcePIPE_SELECT pipeSelect;
++
++ /* Command queue running flag. */
++ gctBOOL running;
++
++ /* Idle flag and commit stamp. */
++ gctBOOL idle;
++ gctUINT64 commitStamp;
++
++ /* Command queue mutex. */
++ gctPOINTER mutexQueue;
++
++ /* Context switching mutex. */
++ gctPOINTER mutexContext;
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context sequence mutex. */
++ gctPOINTER mutexContextSeq;
++#endif
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++
++ /* Current command queue. */
++ struct _gcskCOMMAND_QUEUE
++ {
++ gctSIGNAL signal;
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ gctUINT32 address;
++ }
++ queues[gcdCOMMAND_QUEUES];
++
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ gctUINT32 address;
++ gctUINT32 offset;
++ gctINT index;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctUINT wrapCount;
++#endif
++
++ /* The command queue is new. */
++ gctBOOL newQueue;
++
++ /* Context management. */
++ gckCONTEXT currContext;
++
++ /* Pointer to last WAIT command. */
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitSize;
++
++ /* Command buffer alignment. */
++ gctUINT32 alignment;
++ gctUINT32 reservedHead;
++ gctUINT32 reservedTail;
++
++ /* Commit counter. */
++ gctPOINTER atomCommit;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* End Event signal. */
++ gctSIGNAL endEventSignal;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU currentMmu;
++#endif
++ struct _gckENTRYQUEUE queue;
++};
++
++typedef struct _gcsEVENT * gcsEVENT_PTR;
++
++/* Structure holding one event to be processed. */
++typedef struct _gcsEVENT
++{
++ /* Pointer to next event in queue. */
++ gcsEVENT_PTR next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE info;
++
++ /* Process ID owning the event. */
++ gctUINT32 processID;
++
++ gctBOOL fromKernel;
++}
++gcsEVENT;
++
++/* Structure holding a list of events to be processed by an interrupt. */
++typedef struct _gcsEVENT_QUEUE * gcsEVENT_QUEUE_PTR;
++typedef struct _gcsEVENT_QUEUE
++{
++ /* Time stamp. */
++ gctUINT64 stamp;
++
++ /* Source of the event. */
++ gceKERNEL_WHERE source;
++
++ /* Pointer to head of event queue. */
++ gcsEVENT_PTR head;
++
++ /* Pointer to tail of event queue. */
++ gcsEVENT_PTR tail;
++
++ /* Next list of events. */
++ gcsEVENT_QUEUE_PTR next;
++}
++gcsEVENT_QUEUE;
++
++/*
++ gcdREPO_LIST_COUNT defines the maximum number of event queues with different
++ hardware module sources that may coexist at the same time. Only two sources
++ are supported - gcvKERNEL_COMMAND and gcvKERNEL_PIXEL. gcvKERNEL_COMMAND
++ source is used only for managing the kernel command queue and is only issued
++ when the current command queue gets full. Since we commit event queues every
++ time we commit command buffers, in the worst case we can have up to three
++ pending event queues:
++ - gcvKERNEL_PIXEL
++ - gcvKERNEL_COMMAND (queue overflow)
++ - gcvKERNEL_PIXEL
++*/
++#define gcdREPO_LIST_COUNT 3
++
++/* gckEVENT object. */
++struct _gckEVENT
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to required objects. */
++ gckOS os;
++ gckKERNEL kernel;
++
++ /* Time stamp. */
++ gctUINT64 stamp;
++ gctUINT32 lastCommitStamp;
++
++ /* Queue mutex. */
++ gctPOINTER eventQueueMutex;
++
++ /* Array of event queues. */
++ gcsEVENT_QUEUE queues[29];
++ gctUINT8 lastID;
++ gctPOINTER freeAtom;
++
++ /* Pending events. */
++#if gcdSMP
++ gctPOINTER pending;
++#else
++ volatile gctUINT pending;
++#endif
++
++ /* List of free event structures and its mutex. */
++ gcsEVENT_PTR freeEventList;
++ gctSIZE_T freeEventCount;
++ gctPOINTER freeEventMutex;
++
++ /* Event queues. */
++ gcsEVENT_QUEUE_PTR queueHead;
++ gcsEVENT_QUEUE_PTR queueTail;
++ gcsEVENT_QUEUE_PTR freeList;
++ gcsEVENT_QUEUE repoList[gcdREPO_LIST_COUNT];
++ gctPOINTER eventListMutex;
++
++ gctPOINTER submitTimer;
++
++#if gcdINTERRUPT_STATISTIC
++ gctPOINTER interruptCount;
++#endif
++
++#if gcdRECORD_COMMAND
++ gckRECORDER recorder;
++#endif
++};
++
++/* Free all events belonging to a process. */
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ );
++
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctUINT32 * waitSize
++ );
++
++typedef struct _gcsLOCK_INFO * gcsLOCK_INFO_PTR;
++typedef struct _gcsLOCK_INFO
++{
++ gctUINT32 GPUAddresses[gcdMAX_GPU_COUNT];
++ gctPOINTER pageTables[gcdMAX_GPU_COUNT];
++ gctUINT32 lockeds[gcdMAX_GPU_COUNT];
++ gckKERNEL lockKernels[gcdMAX_GPU_COUNT];
++ gckMMU lockMmus[gcdMAX_GPU_COUNT];
++}
++gcsLOCK_INFO;
++
++typedef struct _gcsGPU_MAP * gcsGPU_MAP_PTR;
++typedef struct _gcsGPU_MAP
++{
++ gctINT pid;
++ gcsLOCK_INFO lockInfo;
++ gcsGPU_MAP_PTR prev;
++ gcsGPU_MAP_PTR next;
++}
++gcsGPU_MAP;
++
++/* gcuVIDMEM_NODE structure. */
++typedef union _gcuVIDMEM_NODE
++{
++ /* Allocated from gckVIDMEM. */
++ struct _gcsVIDMEM_NODE_VIDMEM
++ {
++ /* Owner of this node. */
++ gckVIDMEM memory;
++
++ /* Dual-linked list of nodes. */
++ gcuVIDMEM_NODE_PTR next;
++ gcuVIDMEM_NODE_PTR prev;
++
++ /* Dual linked list of free nodes. */
++ gcuVIDMEM_NODE_PTR nextFree;
++ gcuVIDMEM_NODE_PTR prevFree;
++
++ /* Information for this node. */
++ gctSIZE_T offset;
++ gctSIZE_T bytes;
++ gctUINT32 alignment;
++
++ /* Locked counter. */
++ gctINT32 locked;
++
++ /* Memory pool. */
++ gcePOOL pool;
++ gctUINT32 physical;
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++#if gcdENABLE_VG
++ gctPOINTER kernelVirtual;
++#endif
++ }
++ VidMem;
++
++ /* Allocated from gckOS. */
++ struct _gcsVIDMEM_NODE_VIRTUAL
++ {
++ /* Pointer to gckKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Information for this node. */
++ /* Contiguously allocated? */
++ gctBOOL contiguous;
++ /* mdl record pointer... a kmalloc address. Process agnostic. */
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++ /* do_mmap_pgoff address... mapped per-process. */
++ gctPOINTER logical;
++
++#if gcdENABLE_VG
++ /* Physical address of this node, only meaningful when it is contiguous. */
++ gctUINT32 physicalAddress;
++
++ /* Kernel logical of this node. */
++ gctPOINTER kernelVirtual;
++#endif
++
++ /* Customer private handle */
++ gctUINT32 gid;
++
++ /* Page table information. */
++ /* Used only when node is not contiguous */
++ gctSIZE_T pageCount;
++
++ /* Used only when node is not contiguous */
++ gctPOINTER pageTables[gcdMAX_GPU_COUNT];
++ /* Pointer to gckKERNEL object who lock this. */
++ gckKERNEL lockKernels[gcdMAX_GPU_COUNT];
++ /* Actual physical address */
++ gctUINT32 addresses[gcdMAX_GPU_COUNT];
++
++ /* Locked counter. */
++ gctINT32 lockeds[gcdMAX_GPU_COUNT];
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++ /* Surface type. */
++ gceSURF_TYPE type;
++ }
++ Virtual;
++}
++gcuVIDMEM_NODE;
++
++/* gckVIDMEM object. */
++struct _gckVIDMEM
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Information for this video memory heap. */
++ gctUINT32 baseAddress;
++ gctSIZE_T bytes;
++ gctSIZE_T freeBytes;
++
++ /* Mapping for each type of surface. */
++ gctINT mapping[gcvSURF_NUM_TYPES];
++
++ /* Sentinel nodes for up to 8 banks. */
++ gcuVIDMEM_NODE sentinel[8];
++
++ /* Allocation threshold. */
++ gctSIZE_T threshold;
++
++ /* The heap mutex. */
++ gctPOINTER mutex;
++};
++
++typedef struct _gcsVIDMEM_NODE
++{
++ /* Pointer to gcuVIDMEM_NODE. */
++ gcuVIDMEM_NODE_PTR node;
++
++ /* Mutex to protect node. */
++ gctPOINTER mutex;
++
++ /* Reference count. */
++ gctPOINTER reference;
++
++ /* Name for client to import. */
++ gctUINT32 name;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Head of mapping list. */
++ gcsGPU_MAP_PTR mapHead;
++
++ /* Tail of mapping list. */
++ gcsGPU_MAP_PTR mapTail;
++
++ gctPOINTER mapMutex;
++#endif
++
++ /* Surface Type. */
++ gceSURF_TYPE type;
++
++ /* Pool from which node is allocated. */
++ gcePOOL pool;
++}
++gcsVIDMEM_NODE;
++
++typedef struct _gcsVIDMEM_HANDLE * gckVIDMEM_HANDLE;
++typedef struct _gcsVIDMEM_HANDLE
++{
++ /* Pointer to gckVIDMEM_NODE. */
++ gckVIDMEM_NODE node;
++
++ /* Handle for current process. */
++ gctUINT32 handle;
++
++ /* Reference count for this handle. */
++ gctPOINTER reference;
++}
++gcsVIDMEM_HANDLE;
++
++typedef struct _gcsSHBUF * gcsSHBUF_PTR;
++typedef struct _gcsSHBUF
++{
++ /* ID. */
++ gctUINT32 id;
++
++ /* Reference count. */
++ gctPOINTER reference;
++
++ /* Data size. */
++ gctUINT32 size;
++
++ /* Data. */
++ gctPOINTER data;
++}
++gcsSHBUF;
++
++gceSTATUS
++gckVIDMEM_HANDLE_Reference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ );
++
++gceSTATUS
++gckVIDMEM_HANDLE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Allocate(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR VideoNode,
++ IN gceSURF_TYPE Type,
++ IN gcePOOL Pool,
++ IN gctUINT32 * Handle
++ );
++
++gceSTATUS
++gckVIDMEM_Node_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ OUT gctUINT32 *Address
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctUINT32 ProcessID
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Name(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ IN gctUINT32 * Name
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Import(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name,
++ IN gctUINT32 * Handle
++ );
++
++gceSTATUS
++gckVIDMEM_HANDLE_LookupAndReference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ );
++
++gceSTATUS
++gckVIDMEM_HANDLE_Lookup(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_GetFd(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gctINT * Fd
++ );
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckEVENT_DestroyMmu(
++ IN gckEVENT Event,
++ IN gckMMU Mmu,
++ IN gceKERNEL_WHERE FromWhere
++ );
++#endif
++
++/* gckMMU object. */
++struct _gckMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER pageTableMutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctUINT32_PTR pageTableLogical;
++ gctUINT32 pageTableEntries;
++
++ /* Master TLB information. */
++ gctSIZE_T mtlbSize;
++ gctPHYS_ADDR mtlbPhysical;
++ gctUINT32_PTR mtlbLogical;
++ gctUINT32 mtlbEntries;
++
++ /* Free entries. */
++ gctUINT32 heapList;
++ gctBOOL freeNodes;
++
++ gctPOINTER staticSTLB;
++ gctBOOL enabled;
++
++ gctUINT32 dynamicMappingStart;
++
++ gctUINT32_PTR mapLogical;
++#if gcdPROCESS_ADDRESS_SPACE
++ gctPOINTER pageTableDirty[gcdMAX_GPU_COUNT];
++ gctPOINTER stlbs;
++#endif
++};
++
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckOS_CreateUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++gceSTATUS
++gckOS_DestroyUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckOS_GetFd(
++ IN gctSTRING Name,
++ IN gcsFDPRIVATE_PTR Private,
++ OUT gctINT *Fd
++ );
++
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ );
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ );
++
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ );
++
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ );
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++
++gceSTATUS
++gckKERNEL_CreateShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Size,
++ OUT gctSHBUF * ShBuf
++ );
++
++gceSTATUS
++gckKERNEL_DestroyShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ );
++
++gceSTATUS
++gckKERNEL_MapShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ );
++
++gceSTATUS
++gckKERNEL_WriteShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount
++ );
++
++gceSTATUS
++gckKERNEL_ReadShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount,
++ OUT gctUINT32 * BytesRead
++ );
++
++
++/******************************************************************************\
++******************************* gckCONTEXT Object *******************************
++\******************************************************************************/
++
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ );
++
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ );
++
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ );
++
++gceSTATUS
++gckCONTEXT_MapBuffer(
++ IN gckCONTEXT Context,
++ OUT gctUINT32 *Physicals,
++ OUT gctUINT64 *Logicals,
++ OUT gctUINT32 *Bytes
++ );
++
++#if gcdLINK_QUEUE_SIZE
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ );
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ );
++#endif
++
++gceSTATUS
++gckENTRYQUEUE_Enqueue(
++ IN gckKERNEL Kernel,
++ IN gckENTRYQUEUE Queue,
++ IN gctUINT32 physical,
++ IN gctUINT32 bytes
++ );
++
++gceSTATUS
++gckENTRYQUEUE_Dequeue(
++ IN gckENTRYQUEUE Queue,
++ OUT gckENTRYDATA * Data
++ );
++
++/******************************************************************************\
++****************************** gckRECORDER Object ******************************
++\******************************************************************************/
++gceSTATUS
++gckRECORDER_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ OUT gckRECORDER * Recorder
++ );
++
++gceSTATUS
++gckRECORDER_Destory(
++ IN gckOS Os,
++ IN gckRECORDER Recorder
++ );
++
++void
++gckRECORDER_AdvanceIndex(
++ gckRECORDER Recorder,
++ gctUINT64 CommitStamp
++ );
++
++void
++gckRECORDER_Record(
++ gckRECORDER Recorder,
++ gctUINT8_PTR CommandBuffer,
++ gctUINT32 CommandBytes,
++ gctUINT8_PTR ContextBuffer,
++ gctUINT32 ContextBytes
++ );
++
++void
++gckRECORDER_Dump(
++ gckRECORDER Recorder
++ );
++
++gceSTATUS
++gckRECORDER_UpdateMirror(
++ gckRECORDER Recorder,
++ gctUINT32 State,
++ gctUINT32 Data
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,858 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++/* Interruot statistics will be accumulated if not zero. */
++#define gcmENABLE_INTERRUPT_STATISTICS 0
++
++#define _GC_OBJ_ZONE gcvZONE_INTERRUPT
++
++/* Object structure. */
++struct _gckVGINTERRUPT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* gckVGKERNEL pointer. */
++ gckVGKERNEL kernel;
++
++ /* gckOS pointer. */
++ gckOS os;
++
++ /* Interrupt handlers. */
++ gctINTERRUPT_HANDLER handlers[32];
++
++ /* Main interrupt handler thread. */
++ gctTHREAD handler;
++ gctBOOL terminate;
++
++ /* Interrupt FIFO. */
++ gctSEMAPHORE fifoValid;
++ gctUINT32 fifo[256];
++ gctUINT fifoItems;
++ gctUINT8 head;
++ gctUINT8 tail;
++
++ /* Interrupt statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT maxFifoItems;
++ gctUINT fifoOverflow;
++ gctUINT maxSimultaneous;
++ gctUINT multipleCount;
++#endif
++};
++
++
++/*******************************************************************************
++**
++** _ProcessInterrupt
++**
++** The interrupt processor.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt,
++ gctUINT_PTR TriggeredCount
++ )
++#else
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++ gctUINT i;
++
++ /* Advance to the next entry. */
++ Interrupt->tail += 1;
++ Interrupt->fifoItems -= 1;
++
++ /* Get the interrupt value. */
++ triggered = Interrupt->fifo[Interrupt->tail];
++ gcmkASSERT(triggered != 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: triggered=0x%08X\n",
++ __FUNCTION__,
++ triggered
++ );
++
++ /* Walk through all possible interrupts. */
++ for (i = 0; i < gcmSIZEOF(Interrupt->handlers); i += 1)
++ {
++ /* Test if interrupt happened. */
++ if ((triggered & 1) == 1)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (TriggeredCount != gcvNULL)
++ {
++ (* TriggeredCount) += 1;
++ }
++#endif
++
++ /* Make sure we have valid handler. */
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Interrupt %d isn't registered.\n",
++ __FUNCTION__, i
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: interrupt=%d\n",
++ __FUNCTION__,
++ i
++ );
++
++ /* Call the handler. */
++ status = Interrupt->handlers[i] (Interrupt->kernel);
++
++ if (gcmkIS_ERROR(status))
++ {
++ /* Failed to signal the semaphore. */
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Error %d incrementing the semaphore #%d.\n",
++ __FUNCTION__, status, i
++ );
++ }
++ }
++ }
++
++ /* Next interrupt. */
++ triggered >>= 1;
++
++ /* No more interrupts to handle? */
++ if (triggered == 0)
++ {
++ break;
++ }
++ }
++}
++
++
++/*******************************************************************************
++**
++** _MainInterruptHandler
++**
++** The main interrupt thread serves the interrupt FIFO and calls registered
++** handlers for the interrupts that occured. The handlers are called in the
++** sequence interrupts occured with the exception when multiple interrupts
++** occured at the same time. In that case the handler calls are "sorted" by
++** the interrupt number therefore giving the interrupts with lower numbers
++** higher priority.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gctTHREADFUNCRESULT gctTHREADFUNCTYPE
++_MainInterruptHandler(
++ gctTHREADFUNCPARAMETER ThreadParameter
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT count;
++#endif
++
++ /* Cast the object. */
++ interrupt = (gckVGINTERRUPT) ThreadParameter;
++
++ /* Enter the loop. */
++ while (gcvTRUE)
++ {
++ /* Wait for an interrupt. */
++ status = gckOS_DecrementSemaphore(interrupt->os, interrupt->fifoValid);
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* System termination request? */
++ if (status == gcvSTATUS_TERMINATE)
++ {
++ break;
++ }
++
++ /* Driver is shutting down? */
++ if (interrupt->terminate)
++ {
++ break;
++ }
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Reset triggered count. */
++ count = 0;
++
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt, &count);
++
++ /* Update conters. */
++ if (count > interrupt->maxSimultaneous)
++ {
++ interrupt->maxSimultaneous = count;
++ }
++
++ if (count > 1)
++ {
++ interrupt->multipleCount += 1;
++ }
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt);
++#endif
++ }
++
++ return 0;
++}
++
++
++/*******************************************************************************
++**
++** _StartInterruptHandler / _StopInterruptHandler
++**
++** Main interrupt handler routine control.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gceSTATUS
++_StartInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status, last;
++
++ do
++ {
++ /* Objects must not be already created. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++ gcmkASSERT(Interrupt->handler == gcvNULL);
++
++ /* Reset the termination request. */
++ Interrupt->terminate = gcvFALSE;
++
++#if !gcdENABLE_INFINITE_SPEED_HW
++ /* Construct the fifo semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ Interrupt->os, &Interrupt->fifoValid
++ ));
++
++ /* Start the interrupt handler thread. */
++ gcmkERR_BREAK(gckOS_StartThread(
++ Interrupt->os,
++ _MainInterruptHandler,
++ Interrupt,
++ &Interrupt->handler
++ ));
++#endif
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (Interrupt->fifoValid != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ Interrupt->fifoValid = gcvNULL;
++ }
++
++ /* Return the status. */
++ return status;
++}
++
++static gceSTATUS
++_StopInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Does the thread exist? */
++ if (Interrupt->handler == gcvNULL)
++ {
++ /* The semaphore must be NULL as well. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* The semaphore must exist as well. */
++ gcmkASSERT(Interrupt->fifoValid != gcvNULL);
++
++ /* Set the termination request. */
++ Interrupt->terminate = gcvTRUE;
++
++ /* Unlock the thread. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Wait until the thread quits. */
++ gcmkERR_BREAK(gckOS_StopThread(
++ Interrupt->os,
++ Interrupt->handler
++ ));
++
++ /* Destroy the semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Reset handles. */
++ Interrupt->handler = gcvNULL;
++ Interrupt->fifoValid = gcvNULL;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++
++/******************************************************************************\
++***************************** Interrupt Object API *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Construct
++**
++** Construct an interrupt object.
++**
++** INPUT:
++**
++** Kernel
++** Pointer to the gckVGKERNEL object.
++**
++** OUTPUT:
++**
++** Interrupt
++** Pointer to the new gckVGINTERRUPT object.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interrupt=0x%x", Kernel, Interrupt);
++
++ /* Verify argeuments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interrupt != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGINTERRUPT),
++ (gctPOINTER *) &interrupt
++ ));
++
++ /* Reset the object data. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ interrupt, gcmSIZEOF(struct _gckVGINTERRUPT)
++ ));
++
++ /* Initialize the object. */
++ interrupt->object.type = gcvOBJ_INTERRUPT;
++
++ /* Initialize the object pointers. */
++ interrupt->kernel = Kernel;
++ interrupt->os = Kernel->os;
++
++ /* Initialize the current FIFO position. */
++ interrupt->head = (gctUINT8)~0;
++ interrupt->tail = (gctUINT8)~0;
++
++ /* Start the thread. */
++ gcmkERR_BREAK(_StartInterruptHandler(interrupt));
++
++ /* Return interrupt object. */
++ *Interrupt = interrupt;
++
++ gcmkFOOTER_ARG("*Interrup=0x%x", *Interrupt);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (interrupt != gcvNULL)
++ {
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkVERIFY_OK(gckOS_Free(interrupt->os, interrupt));
++ }
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Destroy
++**
++** Destroy an interrupt object.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to the gckVGINTERRUPT object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ do
++ {
++ /* Stop the interrupt thread. */
++ gcmkERR_BREAK(_StopInterruptHandler(Interrupt));
++
++ /* Mark the object as unknown. */
++ Interrupt->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Free(Interrupt->os, Interrupt));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_DumpState
++**
++** Print the current state of the interrupt manager.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcvDEBUG
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ /* Print the header. */
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: INTERRUPT OBJECT STATUS\n",
++ __FUNCTION__
++ );
++
++ /* Print statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of FIFO items accumulated at a single time: %d\n",
++ Interrupt->maxFifoItems
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Interrupt FIFO overflow happened times: %d\n",
++ Interrupt->fifoOverflow
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of interrupts simultaneously generated: %d\n",
++ Interrupt->maxSimultaneous
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Number of times when there were multiple interrupts generated: %d\n",
++ Interrupt->multipleCount
++ );
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " The current number of entries in the FIFO: %d\n",
++ Interrupt->fifoItems
++ );
++
++ /* Print the FIFO contents. */
++ if (Interrupt->fifoItems != 0)
++ {
++ gctUINT8 index;
++ gctUINT8 last;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " FIFO current contents:\n"
++ );
++
++ /* Get the current pointers. */
++ index = Interrupt->tail;
++ last = Interrupt->head;
++
++ while (index != last)
++ {
++ /* Advance to the next entry. */
++ index += 1;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " %d: 0x%08X\n",
++ index, Interrupt->fifo[index]
++ );
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enable
++**
++** Enable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Pointer to the variable that holds the interrupt number to be
++** registered in range 0..31.
++** If the value is less then 0, gckVGINTERRUPT_Enable will attempt
++** to find an unused interrupt. If such interrupt is found, the number
++** will be assigned to the variable if the functuion call succeedes.
++**
++** Handler
++** Pointer to the handler to register for the interrupt.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ )
++{
++ gceSTATUS status;
++ gctINT32 i;
++
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x Handler=0x%x", Interrupt, Id, Handler);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Handler != gcvNULL);
++
++ do
++ {
++ /* See if we need to allocate an ID. */
++ if (*Id < 0)
++ {
++ /* Find the first unused interrupt handler. */
++ for (i = 0; i < gcmCOUNTOF(Interrupt->handlers); ++i)
++ {
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ break;
++ }
++ }
++
++ /* No unused innterrupts? */
++ if (i == gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++
++ /* Update the interrupt ID. */
++ *Id = i;
++ }
++
++ /* Make sure the ID is in range. */
++ else if (*Id >= gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Set interrupt handler. */
++ Interrupt->handlers[*Id] = Handler;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Disable
++**
++** Disable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Interrupt number to be disabled in range 0..31.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x", Interrupt, Id);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT((Id >= 0) && (Id < gcmCOUNTOF(Interrupt->handlers)));
++
++ /* Reset interrupt handler. */
++ Interrupt->handlers[Id] = gcvNULL;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enque
++**
++** Read the interrupt status register and put the value in the interrupt FIFO.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ do
++ {
++ /* Read interrupt status register. */
++ gcmkERR_BREAK(gckVGHARDWARE_ReadInterrupt(
++ Interrupt->kernel->hardware, &triggered
++ ));
++
++ /* Mask out TS overflow interrupt */
++ triggered &= 0xfffffffe;
++
++ /* No interrupts to process? */
++ if (triggered == 0)
++ {
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ break;
++ }
++
++ /* FIFO overflow? */
++ if (Interrupt->fifoItems == gcmCOUNTOF(Interrupt->fifo))
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ Interrupt->fifoOverflow += 1;
++#endif
++
++ /* OR the interrupt with the last value in the FIFO. */
++ Interrupt->fifo[Interrupt->head] |= triggered;
++
++ /* Success (kind of). */
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ /* Advance to the next entry. */
++ Interrupt->head += 1;
++ Interrupt->fifoItems += 1;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (Interrupt->fifoItems > Interrupt->maxFifoItems)
++ {
++ Interrupt->maxFifoItems = Interrupt->fifoItems;
++ }
++#endif
++
++ /* Set the new value. */
++ Interrupt->fifo[Interrupt->head] = triggered;
++
++ /* Increment the FIFO semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Windows kills our threads prematurely when the application
++ exists. Verify here that the thread is still alive. */
++ status = gckOS_VerifyThread(Interrupt->os, Interrupt->handler);
++
++ /* Has the thread been prematurely terminated? */
++ if (status != gcvSTATUS_OK)
++ {
++ /* Process all accumulated interrupts. */
++ while (Interrupt->head != Interrupt->tail)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt, gcvNULL);
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt);
++#endif
++ }
++
++ /* Set success. */
++ status = gcvSTATUS_OK;
++ }
++ }
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_iommu.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_iommu.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_iommu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_iommu.c 2016-06-19 22:11:55.141150767 +0200
+@@ -0,0 +1,202 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_device.h"
++
++#include <linux/iommu.h>
++#include <linux/platform_device.h>
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsIOMMU
++{
++ struct iommu_domain * domain;
++ struct device * device;
++}
++gcsIOMMU;
++
++static int
++_IOMMU_Fault_Handler(
++ struct iommu_domain * Domain,
++ struct device * Dev,
++ unsigned long DomainAddress,
++ int flags,
++ void * args
++ )
++{
++ return 0;
++}
++
++static int
++_FlatMapping(
++ IN gckIOMMU Iommu
++ )
++{
++ gceSTATUS status;
++ gctUINT32 physical;
++
++ for (physical = 0; physical < 0x80000000; physical += PAGE_SIZE)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "Map %x => %x bytes = %d",
++ physical, physical, PAGE_SIZE
++ );
++
++ gcmkONERROR(gckIOMMU_Map(Iommu, physical, physical, PAGE_SIZE));
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++void
++gckIOMMU_Destory(
++ IN gckOS Os,
++ IN gckIOMMU Iommu
++ )
++{
++ gcmkHEADER();
++
++ if (Iommu->domain && Iommu->device)
++ {
++ iommu_attach_device(Iommu->domain, Iommu->device);
++ }
++
++ if (Iommu->domain)
++ {
++ iommu_domain_free(Iommu->domain);
++ }
++
++ if (Iommu)
++ {
++ gcmkOS_SAFE_FREE(Os, Iommu);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++gceSTATUS
++gckIOMMU_Construct(
++ IN gckOS Os,
++ OUT gckIOMMU * Iommu
++ )
++{
++ gceSTATUS status;
++ gckIOMMU iommu = gcvNULL;
++ struct device *dev;
++ int ret;
++
++ gcmkHEADER();
++
++ dev = &Os->device->platform->device->dev;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsIOMMU), (gctPOINTER *)&iommu));
++
++ gckOS_ZeroMemory(iommu, gcmSIZEOF(gcsIOMMU));
++
++ iommu->domain = iommu_domain_alloc(&platform_bus_type);
++
++ if (!iommu->domain)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "iommu_domain_alloc() fail");
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ iommu_set_fault_handler(iommu->domain, _IOMMU_Fault_Handler, dev);
++
++ ret = iommu_attach_device(iommu->domain, dev);
++
++ if (ret)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS, "iommu_attach_device() fail %d", ret);
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ iommu->device = dev;
++
++ _FlatMapping(iommu);
++
++ *Iommu = iommu;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ gckIOMMU_Destory(Os, iommu);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckIOMMU_Map(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes
++ )
++{
++ gceSTATUS status;
++ int ret;
++
++ gcmkHEADER_ARG("DomainAddress=%#X, Physical=%#X, Bytes=%d",
++ DomainAddress, Physical, Bytes);
++
++ ret = iommu_map(Iommu->domain, DomainAddress, Physical, Bytes, 0);
++
++ if (ret)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ gcmkFOOTER();
++ return status;
++
++}
++
++gceSTATUS
++gckIOMMU_Unmap(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Bytes
++ )
++{
++ gcmkHEADER();
++
++ iommu_unmap(Iommu->domain, DomainAddress, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_linux.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_linux.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_linux.c 2016-06-19 22:11:55.145150505 +0200
+@@ -0,0 +1,487 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryVideoMemory
++**
++** Query the amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to an gcsHAL_INTERFACE structure that will be filled in with
++** the memory information.
++*/
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Get internal memory size and physical address. */
++ Interface->u.QueryVideoMemory.internalSize = device->internalSize;
++ Interface->u.QueryVideoMemory.internalPhysical = device->internalPhysicalName;
++
++ /* Get external memory size and physical address. */
++ Interface->u.QueryVideoMemory.externalSize = device->externalSize;
++ Interface->u.QueryVideoMemory.externalPhysical = device->externalPhysicalName;
++
++ /* Get contiguous memory size and physical address. */
++ Interface->u.QueryVideoMemory.contiguousSize = device->contiguousSize;
++ Interface->u.QueryVideoMemory.contiguousPhysical = device->contiguousPhysicalName;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_GetVideoMemoryPool
++**
++** Get the gckVIDMEM object belonging to the specified pool.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL Pool
++** Pool to query gckVIDMEM object for.
++**
++** OUTPUT:
++**
++** gckVIDMEM * VideoMemory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object belonging to the requested pool.
++*/
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ )
++{
++ gckGALDEVICE device;
++ gckVIDMEM videoMemory;
++
++ gcmkHEADER_ARG("Kernel=%p Pool=%d", Kernel, Pool);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(VideoMemory != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Dispatch on pool. */
++ switch (Pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ videoMemory = device->internalVidMem;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ videoMemory = device->externalVidMem;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ videoMemory = device->contiguousVidMem;
++ break;
++
++ default:
++ /* Unknown pool. */
++ videoMemory = NULL;
++ }
++
++ /* Return pointer to the gckVIDMEM object. */
++ *VideoMemory = videoMemory;
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*VideoMemory=%p", *VideoMemory);
++ return (videoMemory == NULL) ? gcvSTATUS_OUT_OF_MEMORY : gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapMemory
++**
++** Map video memory into the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the base address of the mapped
++** memory region.
++*/
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_MapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_UnmapMemory
++**
++** Unmap video memory from the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** gctPOINTER Logical
++** Base address of the mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_UnmapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckGALDEVICE device = gcvNULL;
++ PLINUX_MDL mdl = gcvNULL;
++ PLINUX_MDL_MAP mdlMap = gcvNULL;
++ gcePOOL pool = gcvPOOL_UNKNOWN;
++ gctUINT32 offset = 0;
++ gctUINT32 base = 0;
++ gceSTATUS status;
++ gctPOINTER logical = gcvNULL;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Kernel=%p InUserSpace=%d Address=%08x",
++ Kernel, InUserSpace, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware, Address, &pool, &offset));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckHARDWARE_SplitMemory(Kernel->hardware, Address, &pool, &offset));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ if (device->contiguousMapped)
++ {
++ logical = device->contiguousBase;
++ }
++ else
++ {
++ gctINT processID;
++ gckOS_GetProcessID(&processID);
++
++ mdl = (PLINUX_MDL) device->contiguousPhysical;
++
++ mdlMap = FindMdlMap(mdl, processID);
++ gcmkASSERT(mdlMap);
++
++ logical = (gctPOINTER) mdlMap->vmaAddr;
++ }
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware,
++ device->contiguousVidMem->baseAddress,
++ &pool,
++ &base));
++ }
++ else
++#endif
++ {
++ gctUINT32 systemBaseAddress = 0;
++
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &systemBaseAddress));
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_CPUPhysicalToGPUPhysical(
++ Kernel->os,
++ device->contiguousVidMem->baseAddress - systemBaseAddress,
++ &baseAddress
++ ));
++
++ gcmkVERIFY_OK(
++ gckHARDWARE_SplitMemory(Kernel->hardware,
++ baseAddress,
++ &pool,
++ &base));
++ }
++ offset -= base;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Build logical address of specified address. */
++ *Logical = (gctPOINTER) ((gctUINT8_PTR) logical + offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=%p", *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Retunn the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ return gckKERNEL_MapVideoMemoryEx(Kernel, gcvCORE_MAJOR, InUserSpace, Address, Logical);
++}
++/*******************************************************************************
++**
++** gckKERNEL_Notify
++**
++** This function iscalled by clients to notify the gckKERNRL object of an event.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gceNOTIFY Notification
++** Notification event.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++ IN gceNOTIFY Notification,
++ IN gctBOOL Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=%p Notification=%d Data=%d",
++ Kernel, Notification, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Dispatch on notifcation. */
++ switch (Notification)
++ {
++ case gcvNOTIFY_INTERRUPT:
++ /* Process the interrupt. */
++ status = gckHARDWARE_Interrupt(Kernel->hardware,
++ Data);
++ break;
++
++ default:
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Settings != gcvNULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Fill in signal. */
++ Settings->signal = device->signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("Settings->signal=%d", Settings->signal);
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_linux.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_linux.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_linux.h 2016-06-19 22:11:55.145150505 +0200
+@@ -0,0 +1,364 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_linux_h_
++#define __gc_hal_kernel_linux_h_
++
++#include <linux/version.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#include <linux/interrupt.h>
++#include <linux/vmalloc.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++
++#include <linux/idr.h>
++
++#ifdef MODVERSIONS
++# include <linux/modversions.h>
++#endif
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#include <linux/clk.h>
++
++#define NTSTRSAFE_NO_CCH_FUNCTIONS
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_platform.h"
++#include "gc_hal_kernel_device.h"
++#include "gc_hal_kernel_os.h"
++#include "gc_hal_kernel_debugfs.h"
++
++
++#define FIND_TASK_BY_PID(x) pid_task(find_vpid(x), PIDTYPE_PID)
++
++#define _WIDE(string) L##string
++#define WIDE(string) _WIDE(string)
++
++#define countof(a) (sizeof(a) / sizeof(a[0]))
++
++#ifndef DEVICE_NAME
++# define DEVICE_NAME "galcore"
++#endif
++
++#define GetPageCount(size, offset) ((((size) + ((offset) & ~PAGE_CACHE_MASK)) + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT)
++
++#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP)
++
++/* Protection bit when mapping memroy to user sapce */
++#define gcmkPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++
++#if gcdNONPAGED_MEMORY_BUFFERABLE
++#define gcmkIOREMAP ioremap_wc
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++#elif !gcdNONPAGED_MEMORY_CACHEABLE
++#define gcmkIOREMAP ioremap_nocache
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_noncached(x)
++#endif
++
++#define gcdSUPPRESS_OOM_MESSAGE 1
++
++#if gcdSUPPRESS_OOM_MESSAGE
++#define gcdNOWARN __GFP_NOWARN
++#else
++#define gcdNOWARN 0
++#endif
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++typedef struct _gcsIOMMU * gckIOMMU;
++
++typedef struct _gcsUSER_MAPPING * gcsUSER_MAPPING_PTR;
++typedef struct _gcsUSER_MAPPING
++{
++ /* Pointer to next mapping structure. */
++ gcsUSER_MAPPING_PTR next;
++
++ /* Physical address of this mapping. */
++ gctUINT32 physical;
++
++ /* Logical address of this mapping. */
++ gctPOINTER logical;
++
++ /* Number of bytes of this mapping. */
++ gctSIZE_T bytes;
++
++ /* Starting address of this mapping. */
++ gctINT8_PTR start;
++
++ /* Ending address of this mapping. */
++ gctINT8_PTR end;
++}
++gcsUSER_MAPPING;
++
++typedef struct _gcsINTEGER_DB * gcsINTEGER_DB_PTR;
++typedef struct _gcsINTEGER_DB
++{
++ struct idr idr;
++ spinlock_t lock;
++ gctINT curr;
++}
++gcsINTEGER_DB;
++
++struct _gckOS
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to device */
++ gckGALDEVICE device;
++
++ /* Memory management */
++ gctPOINTER memoryLock;
++ gctPOINTER memoryMapLock;
++
++ struct _LINUX_MDL *mdlHead;
++ struct _LINUX_MDL *mdlTail;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* Signal management. */
++
++ /* Lock. */
++ gctPOINTER signalMutex;
++
++ /* signal id database. */
++ gcsINTEGER_DB signalDB;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /* Lock. */
++ gctPOINTER syncPointMutex;
++
++ /* sync point id database. */
++ gcsINTEGER_DB syncPointDB;
++#endif
++
++ gcsUSER_MAPPING_PTR userMap;
++ gctPOINTER debugLock;
++
++ /* workqueue for os timer. */
++ struct workqueue_struct * workqueue;
++
++ /* Allocate extra page to avoid cache overflow */
++ struct page* paddingPage;
++
++ /* Detect unfreed allocation. */
++ atomic_t allocateCount;
++
++ struct list_head allocatorList;
++
++ gcsDEBUGFS_DIR allocatorDebugfsDir;
++
++ /* Lock for register access check. */
++ struct mutex registerAccessLocks[gcdMAX_GPU_COUNT];
++
++ /* External power states. */
++ gctBOOL powerStates[gcdMAX_GPU_COUNT];
++
++ /* External clock states. */
++ gctBOOL clockStates[gcdMAX_GPU_COUNT];
++
++ /* IOMMU. */
++ gckIOMMU iommu;
++};
++
++typedef struct _gcsSIGNAL * gcsSIGNAL_PTR;
++typedef struct _gcsSIGNAL
++{
++ /* Kernel sync primitive. */
++ struct completion obj;
++
++ /* Manual reset flag. */
++ gctBOOL manualReset;
++
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* The owner of the signal. */
++ gctHANDLE process;
++
++ gckHARDWARE hardware;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSIGNAL;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++typedef struct _gcsSYNC_POINT * gcsSYNC_POINT_PTR;
++typedef struct _gcsSYNC_POINT
++{
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* State. */
++ atomic_t state;
++
++ /* timeline. */
++ struct sync_timeline * timeline;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSYNC_POINT;
++#endif
++
++typedef struct _gcsPageInfo * gcsPageInfo_PTR;
++typedef struct _gcsPageInfo
++{
++ struct page **pages;
++ gctUINT32_PTR pageTable;
++ gctUINT32 extraPage;
++ gctUINT32 address;
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++}
++gcsPageInfo;
++
++typedef struct _gcsOSTIMER * gcsOSTIMER_PTR;
++typedef struct _gcsOSTIMER
++{
++ struct delayed_work work;
++ gctTIMERFUNCTION function;
++ gctPOINTER data;
++} gcsOSTIMER;
++
++gceSTATUS
++gckOS_ImportAllocators(
++ gckOS Os
++ );
++
++gceSTATUS
++gckOS_FreeAllocators(
++ gckOS Os
++ );
++
++gceSTATUS
++_HandleOuterCache(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Type
++ );
++
++gceSTATUS
++_ConvertLogical2Physical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ IN PLINUX_MDL Mdl,
++ OUT gctUINT32_PTR Physical
++ );
++
++gctSTRING
++_CreateKernelVirtualMapping(
++ IN PLINUX_MDL Mdl
++ );
++
++void
++_DestoryKernelVirtualMapping(
++ IN gctSTRING Addr
++ );
++
++void
++_UnmapUserLogical(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ );
++
++static inline gctINT
++_GetProcessID(
++ void
++ )
++{
++ return task_tgid_vnr(current);
++}
++
++static inline struct page *
++_NonContiguousToPage(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return Pages[Index];
++}
++
++static inline unsigned long
++_NonContiguousToPfn(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_pfn(_NonContiguousToPage(Pages, Index));
++}
++
++static inline unsigned long
++_NonContiguousToPhys(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_phys(_NonContiguousToPage(Pages, Index));
++}
++
++#ifdef CONFIG_IOMMU_SUPPORT
++void
++gckIOMMU_Destory(
++ IN gckOS Os,
++ IN gckIOMMU Iommu
++ );
++
++gceSTATUS
++gckIOMMU_Construct(
++ IN gckOS Os,
++ OUT gckIOMMU * Iommu
++ );
++
++gceSTATUS
++gckIOMMU_Map(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes
++ );
++
++gceSTATUS
++gckIOMMU_Unmap(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Bytes
++ );
++#endif
++
++#endif /* __gc_hal_kernel_linux_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_math.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_math.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_math.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_math.c 2016-06-19 22:11:55.145150505 +0200
+@@ -0,0 +1,32 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ )
++{
++ if(Y ==0) {return 0;}
++ else {return X % Y;}
++}
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_mmu.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_mmu.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_mmu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_mmu.c 2016-06-19 22:11:55.145150505 +0200
+@@ -0,0 +1,2260 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++typedef enum _gceMMU_TYPE
++{
++ gcvMMU_USED = (0 << 4),
++ gcvMMU_SINGLE = (1 << 4),
++ gcvMMU_FREE = (2 << 4),
++}
++gceMMU_TYPE;
++
++#define gcmENTRY_TYPE(x) (x & 0xF0)
++
++#define gcdMMU_TABLE_DUMP 0
++
++#define gcdUSE_MMU_EXCEPTION 1
++
++/*
++ gcdMMU_CLEAR_VALUE
++
++ The clear value for the entry of the old MMU.
++*/
++#ifndef gcdMMU_CLEAR_VALUE
++# define gcdMMU_CLEAR_VALUE 0x00000ABC
++#endif
++
++#define gcdVERTEX_START (128 << 10)
++
++typedef struct _gcsMMU_STLB *gcsMMU_STLB_PTR;
++
++typedef struct _gcsMMU_STLB
++{
++ gctPHYS_ADDR physical;
++ gctUINT32_PTR logical;
++ gctSIZE_T size;
++ gctUINT32 physBase;
++ gctSIZE_T pageCount;
++ gctUINT32 mtlbIndex;
++ gctUINT32 mtlbEntryNum;
++ gcsMMU_STLB_PTR next;
++} gcsMMU_STLB;
++
++#if gcdSHARED_PAGETABLE
++typedef struct _gcsSharedPageTable * gcsSharedPageTable_PTR;
++typedef struct _gcsSharedPageTable
++{
++ /* Shared gckMMU object. */
++ gckMMU mmu;
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsSharedPageTable;
++
++static gcsSharedPageTable_PTR sharedPageTable = gcvNULL;
++#endif
++
++#if gcdMIRROR_PAGETABLE
++typedef struct _gcsMirrorPageTable * gcsMirrorPageTable_PTR;
++typedef struct _gcsMirrorPageTable
++{
++ /* gckMMU objects. */
++ gckMMU mmus[gcdMAX_GPU_COUNT];
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsMirrorPageTable;
++
++static gcsMirrorPageTable_PTR mirrorPageTable = gcvNULL;
++static gctPOINTER mirrorPageTableMutex = gcvNULL;
++#endif
++
++typedef struct _gcsDynamicSpaceNode * gcsDynamicSpaceNode_PTR;
++typedef struct _gcsDynamicSpaceNode
++{
++ gctUINT32 start;
++ gctINT32 entries;
++}
++gcsDynamicSpaceNode;
++
++static void
++_WritePageEntry(
++ IN gctUINT32_PTR PageEntry,
++ IN gctUINT32 EntryValue
++ )
++{
++ static gctUINT16 data = 0xff00;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ *PageEntry = gcmSWAB32(EntryValue);
++ }
++ else
++ {
++ *PageEntry = EntryValue;
++ }
++}
++
++static gctUINT32
++_ReadPageEntry(
++ IN gctUINT32_PTR PageEntry
++ )
++{
++ static gctUINT16 data = 0xff00;
++ gctUINT32 entryValue;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ entryValue = *PageEntry;
++ return gcmSWAB32(entryValue);
++ }
++ else
++ {
++ return *PageEntry;
++ }
++}
++
++static gceSTATUS
++_FillPageTable(
++ IN gctUINT32_PTR PageTable,
++ IN gctUINT32 PageCount,
++ IN gctUINT32 EntryValue
++)
++{
++ gctUINT i;
++
++ for (i = 0; i < PageCount; i++)
++ {
++ _WritePageEntry(PageTable + i, EntryValue);
++ }
++
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_Link(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Next
++ )
++{
++ if (Index >= Mmu->pageTableEntries)
++ {
++ /* Just move heap pointer. */
++ Mmu->heapList = Next;
++ }
++ else
++ {
++ /* Address page table. */
++ gctUINT32_PTR map = Mmu->mapLogical;
++
++ /* Dispatch on node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[Index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Set single index. */
++ _WritePageEntry(&map[Index], (Next << 8) | gcvMMU_SINGLE);
++ break;
++
++ case gcvMMU_FREE:
++ /* Set index. */
++ _WritePageEntry(&map[Index + 1], Next);
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", Index);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_AddFree(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Node,
++ IN gctUINT32 Count
++ )
++{
++ gctUINT32_PTR map = Mmu->mapLogical;
++
++ if (Count == 1)
++ {
++ /* Initialize a single page node. */
++ _WritePageEntry(map + Node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++ }
++ else
++ {
++ /* Initialize the node. */
++ _WritePageEntry(map + Node + 0, (Count << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + Node + 1, ~0U);
++ }
++
++ /* Append the node. */
++ return _Link(Mmu, Index, Node);
++}
++
++static gceSTATUS
++_Collect(
++ IN gckMMU Mmu
++ )
++{
++ gctUINT32_PTR map = Mmu->mapLogical;
++ gceSTATUS status;
++ gctUINT32 i, previous, start = 0, count = 0;
++
++ previous = Mmu->heapList = ~0U;
++ Mmu->freeNodes = gcvFALSE;
++
++ /* Walk the entire page table. */
++ for (i = 0; i < Mmu->pageTableEntries; ++i)
++ {
++ /* Dispatch based on type of page. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i])))
++ {
++ case gcvMMU_USED:
++ /* Used page, so close any open node. */
++ if (count > 0)
++ {
++ /* Add the node. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++
++ /* Reset the node. */
++ previous = start;
++ count = 0;
++ }
++ break;
++
++ case gcvMMU_SINGLE:
++ /* Single free node. */
++ if (count++ == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* A free node. */
++ if (count == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++
++ /* Advance the count. */
++ count += _ReadPageEntry(&map[i]) >> 8;
++
++ /* Advance the index into the page table. */
++ i += (_ReadPageEntry(&map[i]) >> 8) - 1;
++ break;
++
++ default:
++ gcmkFATAL("MMU page table correcupted at index %u!", i);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* See if we have an open node left. */
++ if (count > 0)
++ {
++ /* Add the node to the list. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_MMU,
++ "Performed a garbage collection of the MMU heap.");
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the staus. */
++ return status;
++}
++
++static gctUINT32
++_SetPage(gctUINT32 PageAddress)
++{
++ return PageAddress
++ /* writable */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gctUINT32
++_AddressToIndex(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ )
++{
++ gctUINT32 mtlbOffset = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 stlbOffset = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++
++ return (mtlbOffset - Mmu->dynamicMappingStart) * gcdMMU_STLB_4K_ENTRY_NUM + stlbOffset;
++}
++
++gctUINT32
++_MtlbOffset(
++ gctUINT32 Address
++ )
++{
++ return (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++}
++
++gctUINT32
++_StlbOffset(
++ gctUINT32 Address
++ )
++{
++ return (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++}
++
++static gceSTATUS
++_AllocateStlb(
++ IN gckOS Os,
++ OUT gcsMMU_STLB_PTR *Stlb
++ )
++{
++ gceSTATUS status;
++ gcsMMU_STLB_PTR stlb;
++ gctPOINTER pointer;
++
++ /* Allocate slave TLB record. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsMMU_STLB), &pointer));
++ stlb = pointer;
++
++ stlb->size = gcdMMU_STLB_4K_SIZE;
++
++ /* Allocate slave TLB entries. */
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Os,
++ gcvFALSE,
++ &stlb->size,
++ &stlb->physical,
++ (gctPOINTER)&stlb->logical
++ ));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(Os, stlb->logical, &stlb->physBase));
++
++#if gcdUSE_MMU_EXCEPTION
++ _FillPageTable(stlb->logical, stlb->size / 4, gcdMMU_STLB_EXCEPTION);
++#else
++ gckOS_ZeroMemory(stlb->logical, stlb->size);
++#endif
++
++ *Stlb = stlb;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++gceSTATUS
++_SetupProcessAddressSpace(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gctINT numEntries = 0;
++ gctUINT32_PTR map;
++
++ numEntries = gcdPROCESS_ADDRESS_SPACE_SIZE
++ /* Address space mapped by one MTLB entry. */
++ / (1 << gcdMMU_MTLB_SHIFT);
++
++ Mmu->dynamicMappingStart = 0;
++
++ Mmu->pageTableSize = numEntries * 4096;
++
++ Mmu->pageTableEntries = Mmu->pageTableSize / gcmSIZEOF(gctUINT32);
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ Mmu->pageTableSize,
++ (void **)&Mmu->mapLogical));
++
++ /* Initilization. */
++ map = Mmu->mapLogical;
++ _WritePageEntry(map, (Mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + 1, ~0U);
++ Mmu->heapList = 0;
++ Mmu->freeNodes = gcvFALSE;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++#else
++static gceSTATUS
++_FillFlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBase,
++ OUT gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcsMMU_STLB_PTR head = gcvNULL, pre = gcvNULL;
++ gctUINT32 start = PhysBase & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 end = (PhysBase + Size - 1) & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 mStart = start >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 mEnd = end >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 sStart = (start & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++ gctUINT32 sEnd = (end & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE);
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ while (mStart <= mEnd)
++ {
++ gcmkASSERT(mStart < gcdMMU_MTLB_ENTRY_NUM);
++ if (*(Mmu->mtlbLogical + mStart) == 0)
++ {
++ gcsMMU_STLB_PTR stlb;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 last = (mStart == mEnd) ? sEnd : (gcdMMU_STLB_64K_ENTRY_NUM - 1);
++ gctUINT32 mtlbEntry;
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os, sizeof(struct _gcsMMU_STLB), &pointer));
++ stlb = pointer;
++
++ stlb->mtlbEntryNum = 0;
++ stlb->next = gcvNULL;
++ stlb->physical = gcvNULL;
++ stlb->logical = gcvNULL;
++ stlb->size = gcdMMU_STLB_64K_SIZE;
++ stlb->pageCount = 0;
++
++ if (pre == gcvNULL)
++ {
++ pre = head = stlb;
++ }
++ else
++ {
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = stlb;
++ pre = stlb;
++ }
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &stlb->size,
++ &stlb->physical,
++ (gctPOINTER)&stlb->logical));
++
++ gcmkONERROR(gckOS_ZeroMemory(stlb->logical, stlb->size));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Mmu->os,
++ stlb->logical,
++ &stlb->physBase));
++
++ if (stlb->physBase & (gcdMMU_STLB_64K_SIZE - 1))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ mtlbEntry = stlb->physBase
++ /* 64KB page size */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++
++ if (ace)
++ {
++ mtlbEntry = mtlbEntry
++ /* Secure */
++ | (1 << 4);
++ }
++
++ _WritePageEntry(Mmu->mtlbLogical + mStart, mtlbEntry);
++
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ mStart,
++ _ReadPageEntry(Mmu->mtlbLogical + mStart));
++#endif
++
++ stlb->mtlbIndex = mStart;
++ stlb->mtlbEntryNum = 1;
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): STLB: logical:%08x -> physical:%08x\n",
++ __FUNCTION__, __LINE__,
++ stlb->logical,
++ stlb->physBase);
++#endif
++
++ while (sStart <= last)
++ {
++ gcmkASSERT(!(start & gcdMMU_PAGE_64K_MASK));
++ _WritePageEntry(stlb->logical + sStart, _SetPage(start));
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert STLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ sStart,
++ _ReadPageEntry(stlb->logical + sStart));
++#endif
++ /* next page. */
++ start += gcdMMU_PAGE_64K_SIZE;
++ sStart++;
++ stlb->pageCount++;
++ }
++
++ sStart = 0;
++ ++mStart;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ }
++
++ /* Insert the stlb into staticSTLB. */
++ if (Mmu->staticSTLB == gcvNULL)
++ {
++ Mmu->staticSTLB = head;
++ }
++ else
++ {
++ gcmkASSERT(pre == gcvNULL);
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = Mmu->staticSTLB;
++ Mmu->staticSTLB = head;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Roll back. */
++ while (head != gcvNULL)
++ {
++ pre = head;
++ head = head->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_FindDynamicSpace(
++ IN gckMMU Mmu,
++ OUT gcsDynamicSpaceNode_PTR *Array,
++ OUT gctINT * Size
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer = gcvNULL;
++ gcsDynamicSpaceNode_PTR array = gcvNULL;
++ gctINT size = 0;
++ gctINT i = 0, nodeStart = -1, nodeEntries = 0;
++
++ /* Allocate memory for the array. */
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ gcmSIZEOF(*array) * (gcdMMU_MTLB_ENTRY_NUM / 2),
++ &pointer));
++
++ array = (gcsDynamicSpaceNode_PTR)pointer;
++
++ /* Loop all the entries. */
++ while (i < gcdMMU_MTLB_ENTRY_NUM)
++ {
++ if (!Mmu->mtlbLogical[i])
++ {
++ if (nodeStart < 0)
++ {
++ /* This is the first entry of the dynamic space. */
++ nodeStart = i;
++ nodeEntries = 1;
++ }
++ else
++ {
++ /* Other entries of the dynamic space. */
++ nodeEntries++;
++ }
++ }
++ else if (nodeStart >= 0)
++ {
++ /* Save the previous node. */
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++
++ /* Reset the start. */
++ nodeStart = -1;
++ nodeEntries = 0;
++ }
++
++ i++;
++ }
++
++ /* Save the previous node. */
++ if (nodeStart >= 0)
++ {
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++ }
++
++#if gcdMMU_TABLE_DUMP
++ for (i = 0; i < size; i++)
++ {
++ gckOS_Print("%s(%d): [%d]: start=%d, entries=%d.\n",
++ __FUNCTION__, __LINE__,
++ i,
++ array[i].start,
++ array[i].entries);
++ }
++#endif
++
++ *Array = array;
++ *Size = size;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (pointer != gcvNULL)
++ {
++ gckOS_Free(Mmu->os, pointer);
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_SetupDynamicSpace(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gcsDynamicSpaceNode_PTR nodeArray = gcvNULL;
++ gctINT i, nodeArraySize = 0;
++ gctUINT32 physical;
++ gctINT numEntries = 0;
++ gctUINT32_PTR map;
++ gctBOOL acquired = gcvFALSE;
++ gctUINT32 mtlbEntry;
++ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE);
++
++ /* Find all the dynamic address space. */
++ gcmkONERROR(_FindDynamicSpace(Mmu, &nodeArray, &nodeArraySize));
++
++ /* TODO: We only use the largest one for now. */
++ for (i = 0; i < nodeArraySize; i++)
++ {
++ if (nodeArray[i].entries > numEntries)
++ {
++ Mmu->dynamicMappingStart = nodeArray[i].start;
++ numEntries = nodeArray[i].entries;
++ }
++ }
++
++ gckOS_Free(Mmu->os, (gctPOINTER)nodeArray);
++
++ Mmu->pageTableSize = numEntries * 4096;
++
++ gcmkSAFECASTSIZET(Mmu->pageTableEntries, Mmu->pageTableSize / gcmSIZEOF(gctUINT32));
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ Mmu->pageTableSize,
++ (void **)&Mmu->mapLogical));
++
++ /* Construct Slave TLB. */
++ gcmkONERROR(gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &Mmu->pageTableSize,
++ &Mmu->pageTablePhysical,
++ (gctPOINTER)&Mmu->pageTableLogical));
++
++#if gcdUSE_MMU_EXCEPTION
++ gcmkONERROR(_FillPageTable(Mmu->pageTableLogical,
++ Mmu->pageTableEntries,
++ /* Enable exception */
++ 1 << 1));
++#else
++ /* Invalidate all entries. */
++ gcmkONERROR(gckOS_ZeroMemory(Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++#endif
++
++ /* Initilization. */
++ map = Mmu->mapLogical;
++ _WritePageEntry(map, (Mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + 1, ~0U);
++ Mmu->heapList = 0;
++ Mmu->freeNodes = gcvFALSE;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(Mmu->os,
++ Mmu->pageTableLogical,
++ &physical));
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Map to Master TLB. */
++ for (i = (gctINT)Mmu->dynamicMappingStart;
++ i < (gctINT)Mmu->dynamicMappingStart + numEntries;
++ i++)
++ {
++ mtlbEntry = physical
++ /* 4KB page size */
++ | (0 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++
++ if (ace)
++ {
++ mtlbEntry = mtlbEntry
++ /* Secure */
++ | (1 << 4);
++ }
++
++ _WritePageEntry(Mmu->mtlbLogical + i, mtlbEntry);
++
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ i,
++ _ReadPageEntry(Mmu->mtlbLogical + i));
++#endif
++ physical += gcdMMU_STLB_4K_SIZE;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (Mmu->mapLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_Free(Mmu->os, (gctPOINTER) Mmu->mapLogical));
++
++
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** _Construct
++**
++** Construct a new gckMMU object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckMMU * Mmu
++** Pointer to a variable that receives the gckMMU object pointer.
++*/
++gceSTATUS
++_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gckMMU mmu = gcvNULL;
++ gctUINT32_PTR map;
++ gctPOINTER pointer = gcvNULL;
++#if gcdPROCESS_ADDRESS_SPACE
++ gctUINT32 i;
++ gctUINT32 physical;
++#endif
++ gctUINT32 physBase;
++ gctUINT32 physSize;
++ gctUINT32 gpuAddress;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=%lu", Kernel, MmuSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckMMU object. */
++ gcmkONERROR(gckOS_Allocate(os, sizeof(struct _gckMMU), &pointer));
++
++ mmu = pointer;
++
++ /* Initialize the gckMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++ mmu->pageTableMutex = gcvNULL;
++ mmu->pageTableLogical = gcvNULL;
++ mmu->mtlbLogical = gcvNULL;
++ mmu->staticSTLB = gcvNULL;
++ mmu->enabled = gcvFALSE;
++ mmu->mapLogical = gcvNULL;
++
++ /* Create the page table mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &mmu->pageTableMutex));
++
++ if (hardware->mmuVersion == 0)
++ {
++ mmu->pageTableSize = MmuSize;
++
++ /* Construct address space management table. */
++ gcmkONERROR(gckOS_Allocate(mmu->os,
++ mmu->pageTableSize,
++ &pointer));
++
++ mmu->mapLogical = pointer;
++
++ /* Construct page table read by GPU. */
++ gcmkONERROR(gckOS_AllocateContiguous(mmu->os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ (gctPOINTER)&mmu->pageTableLogical));
++
++
++ /* Compute number of entries in page table. */
++ gcmkSAFECASTSIZET(mmu->pageTableEntries, mmu->pageTableSize / sizeof(gctUINT32));
++
++ /* Mark all pages as free. */
++ map = mmu->mapLogical;
++
++#if gcdMMU_CLEAR_VALUE
++ _FillPageTable(mmu->pageTableLogical, mmu->pageTableEntries, gcdMMU_CLEAR_VALUE);
++#endif
++
++ _WritePageEntry(map, (mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + 1, ~0U);
++ mmu->heapList = 0;
++ mmu->freeNodes = gcvFALSE;
++ }
++ else
++ {
++ /* Allocate the 4K mode MTLB table. */
++ mmu->mtlbSize = gcdMMU_MTLB_SIZE + 64;
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->mtlbSize,
++ &mmu->mtlbPhysical,
++ &pointer));
++
++ mmu->mtlbLogical = pointer;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ _FillPageTable(pointer, mmu->mtlbSize / 4, gcdMMU_MTLB_EXCEPTION);
++
++ /* Allocate a array to store stlbs. */
++ gcmkONERROR(gckOS_Allocate(os, mmu->mtlbSize, &mmu->stlbs));
++
++ gckOS_ZeroMemory(mmu->stlbs, mmu->mtlbSize);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ gcmkONERROR(gckOS_AtomConstruct(os, &mmu->pageTableDirty[i]));
++ }
++
++ _SetupProcessAddressSpace(mmu);
++
++ /* Map kernel command buffer in MMU. */
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ mmu->os,
++ Kernel->command->queues[i].logical,
++ &physical
++ ));
++
++ gcmkONERROR(gckMMU_FlatMapping(mmu, physical));
++ }
++#else
++ /* Invalid all the entries. */
++ gcmkONERROR(
++ gckOS_ZeroMemory(pointer, mmu->mtlbSize));
++
++ gcmkONERROR(
++ gckOS_QueryOption(mmu->os, "physBase", &physBase));
++
++ gcmkONERROR(
++ gckOS_QueryOption(mmu->os, "physSize", &physSize));
++
++ gcmkONERROR(
++ gckOS_CPUPhysicalToGPUPhysical(mmu->os, physBase, &gpuAddress));
++
++ /* Setup [physBase - physSize) flat mapping. */
++ gcmkONERROR(_FillFlatMapping(
++ mmu,
++ gpuAddress,
++ physSize
++ ));
++
++ gcmkONERROR(_SetupDynamicSpace(mmu));
++#endif
++ }
++
++ /* Return the gckMMU object pointer. */
++ *Mmu = mmu;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Mmu=0x%x", *Mmu);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (mmu != gcvNULL)
++ {
++ if (mmu->mapLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_Free(os, (gctPOINTER) mmu->mapLogical));
++
++
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->pageTablePhysical,
++ (gctPOINTER) mmu->pageTableLogical,
++ mmu->pageTableSize));
++ }
++
++ if (mmu->mtlbLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->mtlbPhysical,
++ (gctPOINTER) mmu->mtlbLogical,
++ mmu->mtlbSize));
++ }
++
++ if (mmu->pageTableMutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, mmu->pageTableMutex));
++ }
++
++ /* Mark the gckMMU object as unknown. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the allocates memory. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, mmu));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** _Destroy
++**
++** Destroy a gckMMU object.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#if gcdPROCESS_ADDRESS_SPACE
++ gctUINT32 i;
++#endif
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ while (Mmu->staticSTLB != gcvNULL)
++ {
++ gcsMMU_STLB_PTR pre = Mmu->staticSTLB;
++ Mmu->staticSTLB = pre->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): clean MTLB[%d]\n",
++ __FUNCTION__, __LINE__,
++ pre->mtlbIndex);
++#endif
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (Mmu->hardware->mmuVersion != 0)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->mtlbPhysical,
++ (gctPOINTER) Mmu->mtlbLogical,
++ Mmu->mtlbSize));
++ }
++
++ /* Free address space management table. */
++ if (Mmu->mapLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_Free(Mmu->os, (gctPOINTER) Mmu->mapLogical));
++ }
++
++ if (Mmu->pageTableLogical != gcvNULL)
++ {
++ /* Free page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++ }
++
++ /* Delete the page table mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->pageTableMutex));
++
++#if gcdPROCESS_ADDRESS_SPACE
++ for (i = 0; i < Mmu->mtlbSize / 4; i++)
++ {
++ struct _gcsMMU_STLB *stlb = ((struct _gcsMMU_STLB **)Mmu->stlbs)[i];
++
++ if (stlb)
++ {
++ gcmkVERIFY_OK(gckOS_FreeContiguous(
++ Mmu->os,
++ stlb->physical,
++ stlb->logical,
++ stlb->size));
++
++ gcmkOS_SAFE_FREE(Mmu->os, stlb);
++ }
++ }
++
++ gcmkOS_SAFE_FREE(Mmu->os, Mmu->stlbs);
++#endif
++
++ /* Mark the gckMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckMMU object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, Mmu));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** _AdjstIndex
++**
++** Adjust the index from which we search for a usable node to make sure
++** index allocated is greater than Start.
++*/
++gceSTATUS
++_AdjustIndex(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 PageCount,
++ IN gctUINT32 Start,
++ OUT gctUINT32 * IndexAdjusted
++ )
++{
++ gceSTATUS status;
++ gctUINT32 index = Index;
++ gctUINT32_PTR map = Mmu->mapLogical;
++
++ gcmkHEADER();
++
++ for (; index < Mmu->pageTableEntries;)
++ {
++ gctUINT32 result = 0;
++ gctUINT32 nodeSize = 0;
++
++ if (index >= Start)
++ {
++ break;
++ }
++
++ switch (gcmENTRY_TYPE(map[index]))
++ {
++ case gcvMMU_SINGLE:
++ nodeSize = 1;
++ break;
++
++ case gcvMMU_FREE:
++ nodeSize = map[index] >> 8;
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ if (nodeSize > PageCount)
++ {
++ result = index + (nodeSize - PageCount);
++
++ if (result >= Start)
++ {
++ break;
++ }
++ }
++
++ switch (gcmENTRY_TYPE(map[index]))
++ {
++ case gcvMMU_SINGLE:
++ index = map[index] >> 8;
++ break;
++
++ case gcvMMU_FREE:
++ index = map[index + 1];
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ *IndexAdjusted = index;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (sharedPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsSharedPageTable),
++ &pointer));
++ sharedPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(sharedPageTable,
++ sizeof(struct _gcsSharedPageTable)));
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, &sharedPageTable->mmu));
++ }
++
++ *Mmu = sharedPageTable->mmu;
++
++ sharedPageTable->hardwares[sharedPageTable->reference] = Kernel->hardware;
++
++ sharedPageTable->reference++;
++
++ gcmkFOOTER_ARG("sharedPageTable->reference=%lu", sharedPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (sharedPageTable)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(gckMMU_Destroy(sharedPageTable->mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, sharedPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#elif gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (mirrorPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsMirrorPageTable),
++ &pointer));
++ mirrorPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(mirrorPageTable,
++ sizeof(struct _gcsMirrorPageTable)));
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Kernel->os, &mirrorPageTableMutex));
++ }
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, Mmu));
++
++ mirrorPageTable->mmus[mirrorPageTable->reference] = *Mmu;
++
++ mirrorPageTable->hardwares[mirrorPageTable->reference] = Kernel->hardware;
++
++ mirrorPageTable->reference++;
++
++ gcmkFOOTER_ARG("mirrorPageTable->reference=%lu", mirrorPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mirrorPageTable && mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, mirrorPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#else
++ return _Construct(Kernel, MmuSize, Mmu);
++#endif
++}
++
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ gckOS os = Mmu->os;
++
++ sharedPageTable->reference--;
++
++ if (sharedPageTable->reference == 0)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(_Destroy(Mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, sharedPageTable));
++ }
++
++ return gcvSTATUS_OK;
++#elif gcdMIRROR_PAGETABLE
++ mirrorPageTable->reference--;
++
++ if (mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTable));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTableMutex));
++ }
++
++ return _Destroy(Mmu);
++#else
++ return _Destroy(Mmu);
++#endif
++}
++
++/*******************************************************************************
++**
++** gckMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS
++_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gctUINT32 index = 0, previous = ~0U, left;
++ gctUINT32_PTR map;
++ gctBOOL gotIt;
++ gctUINT32 address;
++ gctUINT32 pageCount;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=%lu", Mmu, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ if (PageCount > Mmu->pageTableEntries)
++ {
++ /* Not enough pages avaiable. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ gcmkSAFECASTSIZET(pageCount, PageCount);
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ /* Cast pointer to page table. */
++ for (map = Mmu->mapLogical, gotIt = gcvFALSE; !gotIt;)
++ {
++ index = Mmu->heapList;
++
++ if ((Mmu->hardware->mmuVersion == 0) && (Type == gcvSURF_VERTEX))
++ {
++ gcmkONERROR(_AdjustIndex(
++ Mmu,
++ index,
++ pageCount,
++ gcdVERTEX_START / gcmSIZEOF(gctUINT32),
++ &index
++ ));
++ }
++
++ /* Walk the heap list. */
++ for (; !gotIt && (index < Mmu->pageTableEntries);)
++ {
++ /* Check the node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Single odes are valid if we only need 1 page. */
++ if (pageCount == 1)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&map[index]) >> 8;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* Test if the node has enough space. */
++ if (pageCount <= (_ReadPageEntry(&map[index]) >> 8))
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&map[index + 1]);
++ }
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ /* Test if we are out of memory. */
++ if (index >= Mmu->pageTableEntries)
++ {
++ if (Mmu->freeNodes)
++ {
++ /* Time to move out the trash! */
++ gcmkONERROR(_Collect(Mmu));
++ }
++ else
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ }
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Unlink single node from free list. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&map[index]) >> 8));
++ break;
++
++ case gcvMMU_FREE:
++ /* Check how many pages will be left. */
++ left = (_ReadPageEntry(&map[index]) >> 8) - pageCount;
++ switch (left)
++ {
++ case 0:
++ /* The entire node is consumed, just unlink it. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&map[index + 1])));
++ break;
++
++ case 1:
++ /* One page will remain. Convert the node to a single node and
++ ** advance the index. */
++ _WritePageEntry(&map[index], (_ReadPageEntry(&map[index + 1]) << 8) | gcvMMU_SINGLE);
++ index ++;
++ break;
++
++ default:
++ /* Enough pages remain for a new node. However, we will just adjust
++ ** the size of the current node and advance the index. */
++ _WritePageEntry(&map[index], (left << 8) | gcvMMU_FREE);
++ index += left;
++ break;
++ }
++ break;
++ }
++
++ /* Mark node as used. */
++ gcmkONERROR(_FillPageTable(&map[index], pageCount, gcvMMU_USED));
++
++ /* Return pointer to page table. */
++ *PageTable = &Mmu->pageTableLogical[index];
++
++ /* Build virtual address. */
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(
++ gckHARDWARE_BuildVirtualAddress(Mmu->hardware, index, 0, &address));
++ }
++ else
++ {
++ gctUINT32 masterOffset = index / gcdMMU_STLB_4K_ENTRY_NUM
++ + Mmu->dynamicMappingStart;
++ gctUINT32 slaveOffset = index % gcdMMU_STLB_4K_ENTRY_NUM;
++
++ address = (masterOffset << gcdMMU_MTLB_SHIFT)
++ | (slaveOffset << gcdMMU_STLB_4K_SHIFT);
++ }
++
++ if (Address != gcvNULL)
++ {
++ *Address = address;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageTable=0x%x *Address=%08x",
++ *PageTable, gcmOPT_VALUE(Address));
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32_PTR node;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctUINT32 pageCount;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=%lu",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ gcmkSAFECASTSIZET(pageCount, PageCount);
++
++ /* Get the node by index. */
++ node = Mmu->mapLogical + ((gctUINT32_PTR)PageTable - Mmu->pageTableLogical);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++#if gcdMMU_CLEAR_VALUE
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ _FillPageTable(PageTable, pageCount, gcdMMU_CLEAR_VALUE);
++ }
++#endif
++
++ if (PageCount == 1)
++ {
++ /* Single page node. */
++ _WritePageEntry(node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ _WritePageEntry(PageTable, (1 << 1));
++#endif
++ }
++ else
++ {
++ /* Mark the node as free. */
++ _WritePageEntry(node, (pageCount << 8) | gcvMMU_FREE);
++ _WritePageEntry(node + 1, ~0U);
++
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ gcmkVERIFY_OK(_FillPageTable(PageTable, pageCount, 1 << 1));
++#endif
++ }
++
++ /* We have free nodes. */
++ Mmu->freeNodes = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ return gckMMU_AllocatePagesEx(
++ Mmu, PageCount, gcvSURF_TYPE_UNKNOWN, PageTable, Address);
++}
++
++gceSTATUS
++gckMMU_AllocatePagesEx(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pageTable;
++ gctUINT32 address;
++ gctINT i;
++ gckMMU mmu;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL allocated = gcvFALSE;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++ acquired = gcvTRUE;
++
++ /* Allocate page table for current MMU. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ if (Mmu == mirrorPageTable->mmus[i])
++ {
++ gcmkONERROR(_AllocatePages(Mmu, PageCount, Type, PageTable, Address));
++ allocated = gcvTRUE;
++ }
++ }
++
++ /* Allocate page table for other MMUs. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (Mmu != mmu)
++ {
++ gcmkONERROR(_AllocatePages(mmu, PageCount, Type, &pageTable, &address));
++ gcmkASSERT(address == *Address);
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ acquired = gcvFALSE;
++
++ return gcvSTATUS_OK;
++OnError:
++
++ if (allocated)
++ {
++ /* Page tables for multiple GPU always keep the same. So it is impossible
++ * the fist one allocates successfully but others fail.
++ */
++ gcmkASSERT(0);
++ }
++
++ if (acquired)
++ {
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ }
++
++ return status;
++#else
++ return _AllocatePages(Mmu, PageCount, Type, PageTable, Address);
++#endif
++}
++
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctINT i;
++ gctUINT32 offset;
++ gckMMU mmu;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++
++ gcmkVERIFY_OK(_FreePages(Mmu, PageTable, PageCount));
++
++ offset = (gctUINT32)PageTable - (gctUINT32)Mmu->pageTableLogical;
++
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ gcmkVERIFY_OK(_FreePages(mmu, mmu->pageTableLogical + offset/4, PageCount));
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++
++ return gcvSTATUS_OK;
++#else
++ return _FreePages(Mmu, PageTable, PageCount);
++#endif
++}
++
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctUINT32_PTR pageEntry;
++ gctINT i;
++ gckMMU mmu;
++ gctUINT32 offset = (gctUINT32)PageEntry - (gctUINT32)Mmu->pageTableLogical;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ _WritePageEntry(PageEntry, PageAddress);
++ }
++ else
++ {
++ _WritePageEntry(PageEntry, _SetPage(PageAddress));
++ }
++
++#if gcdMIRROR_PAGETABLE
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ pageEntry = mmu->pageTableLogical + offset / 4;
++
++ if (mmu->hardware->mmuVersion == 0)
++ {
++ _WritePageEntry(pageEntry, PageAddress);
++ }
++ else
++ {
++ _WritePageEntry(pageEntry, _SetPage(PageAddress));
++ }
++ }
++
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckMMU_GetPageEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctUINT32_PTR *PageTable
++ )
++{
++ gceSTATUS status;
++ struct _gcsMMU_STLB *stlb;
++ struct _gcsMMU_STLB **stlbs = Mmu->stlbs;
++ gctUINT32 offset = _MtlbOffset(Address);
++ gctUINT32 mtlbEntry;
++ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE);
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT((Address & 0xFFF) == 0);
++
++ stlb = stlbs[offset];
++
++ if (stlb == gcvNULL)
++ {
++ gcmkONERROR(_AllocateStlb(Mmu->os, &stlb));
++
++ mtlbEntry = stlb->physBase
++ | gcdMMU_MTLB_4K_PAGE
++ | gcdMMU_MTLB_PRESENT
++ ;
++
++ if (ace)
++ {
++ mtlbEntry = mtlbEntry
++ /* Secure */
++ | (1 << 4);
++ }
++
++ /* Insert Slave TLB address to Master TLB entry.*/
++ _WritePageEntry(Mmu->mtlbLogical + offset, mtlbEntry);
++
++ /* Record stlb. */
++ stlbs[offset] = stlb;
++ }
++
++ *PageTable = &stlb->logical[_StlbOffset(Address)];
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++_CheckMap(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR map = Mmu->mapLogical;
++ gctUINT32 index;
++
++ for (index = Mmu->heapList; index < Mmu->pageTableEntries;)
++ {
++ /* Check the node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Move to next node. */
++ index = _ReadPageEntry(&map[index]) >> 8;
++ break;
++
++ case gcvMMU_FREE:
++ /* Move to next node. */
++ index = _ReadPageEntry(&map[index + 1]);
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index [%u] = %x!", index, map[index]);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++gceSTATUS
++gckMMU_FlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 Physical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 index = _AddressToIndex(Mmu, Physical);
++ gctUINT32 i;
++ gctBOOL gotIt = gcvFALSE;
++ gctUINT32_PTR map = Mmu->mapLogical;
++ gctUINT32 previous = ~0U;
++ gctUINT32_PTR pageTable;
++
++ gckMMU_GetPageEntry(Mmu, Physical, &pageTable);
++
++ _WritePageEntry(pageTable, _SetPage(Physical));
++
++ if (map)
++ {
++ /* Find node which contains index. */
++ for (i = 0; !gotIt && (i < Mmu->pageTableEntries);)
++ {
++ gctUINT32 numPages;
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i])))
++ {
++ case gcvMMU_SINGLE:
++ if (i == index)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ previous = i;
++ i = _ReadPageEntry(&map[i]) >> 8;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ numPages = _ReadPageEntry(&map[i]) >> 8;
++ if (index >= i && index < i + numPages)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ previous = i;
++ i = _ReadPageEntry(&map[i + 1]);
++ }
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i])))
++ {
++ case gcvMMU_SINGLE:
++ /* Unlink single node from free list. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&map[i]) >> 8));
++ break;
++
++ case gcvMMU_FREE:
++ /* Split the node. */
++ {
++ gctUINT32 start;
++ gctUINT32 next = _ReadPageEntry(&map[i+1]);
++ gctUINT32 total = _ReadPageEntry(&map[i]) >> 8;
++ gctUINT32 countLeft = index - i;
++ gctUINT32 countRight = total - countLeft - 1;
++
++ if (countLeft)
++ {
++ start = i;
++ _AddFree(Mmu, previous, start, countLeft);
++ previous = start;
++ }
++
++ if (countRight)
++ {
++ start = index + 1;
++ _AddFree(Mmu, previous, start, countRight);
++ previous = start;
++ }
++
++ _Link(Mmu, previous, next);
++ }
++ break;
++ }
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Roll back. */
++ return status;
++}
++
++
++
++gceSTATUS
++gckMMU_FreePagesEx(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32_PTR node;
++ gceSTATUS status;
++
++#if gcdUSE_MMU_EXCEPTION
++ gctUINT32 i;
++ struct _gcsMMU_STLB *stlb;
++ struct _gcsMMU_STLB **stlbs = Mmu->stlbs;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x Address=0x%x PageCount=%lu",
++ Mmu, Address, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ /* Get the node by index. */
++ node = Mmu->mapLogical + _AddressToIndex(Mmu, Address);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++
++ if (PageCount == 1)
++ {
++ /* Single page node. */
++ _WritePageEntry(node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++ }
++ else
++ {
++ /* Mark the node as free. */
++ _WritePageEntry(node, (PageCount << 8) | gcvMMU_FREE);
++ _WritePageEntry(node + 1, ~0U);
++ }
++
++ /* We have free nodes. */
++ Mmu->freeNodes = gcvTRUE;
++
++#if gcdUSE_MMU_EXCEPTION
++ for (i = 0; i < PageCount; i++)
++ {
++ /* Get */
++ stlb = stlbs[_MtlbOffset(Address)];
++
++ /* Enable exception */
++ stlb->logical[_StlbOffset(Address)] = gcdMMU_STLB_EXCEPTION;
++ }
++#endif
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu,
++ IN gceSURF_TYPE Type
++ )
++{
++ gckHARDWARE hardware;
++ gctUINT32 mask;
++ gctINT i;
++
++ if (Type == gcvSURF_VERTEX || Type == gcvSURF_INDEX)
++ {
++ mask = gcvPAGE_TABLE_DIRTY_BIT_FE;
++ }
++ else
++ {
++ mask = gcvPAGE_TABLE_DIRTY_BIT_OTHER;
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ gcmkVERIFY_OK(
++ gckOS_AtomSetMask(Mmu->pageTableDirty[i], mask));
++ }
++#else
++#if gcdSHARED_PAGETABLE
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ hardware = sharedPageTable->hardwares[i];
++ if (hardware)
++ {
++ gcmkVERIFY_OK(gckOS_AtomSetMask(hardware->pageTableDirty, mask));
++ }
++ }
++#elif gcdMIRROR_PAGETABLE
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ hardware = mirrorPageTable->hardwares[i];
++
++ /* Notify cores who use this page table. */
++ gcmkVERIFY_OK(
++ gckOS_AtomSetMask(hardware->pageTableDirty, mask));
++ }
++#else
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSetMask(hardware->pageTableDirty, mask));
++#endif
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ )
++{
++#if gcdPROCESS_ADDRESS_SPACE
++ gcsMMU_STLB_PTR *stlbs = Mmu->stlbs;
++ gcsMMU_STLB_PTR stlbDesc = stlbs[_MtlbOffset(Address)];
++#else
++ gctUINT32_PTR pageTable;
++ gctUINT32 index;
++ gctUINT32 mtlb, stlb;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%08X Address=0x%08X", Mmu, Address);
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkASSERT(Mmu->hardware->mmuVersion > 0);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ if (stlbDesc)
++ {
++ gcmkPRINT(" STLB entry = 0x%08X",
++ _ReadPageEntry(&stlbDesc->logical[_StlbOffset(Address)]));
++ }
++ else
++ {
++ gcmkPRINT(" MTLB entry is empty.");
++ }
++#else
++ mtlb = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++
++ if (mtlb >= Mmu->dynamicMappingStart)
++ {
++ stlb = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++
++ pageTable = Mmu->pageTableLogical;
++
++ index = (mtlb - Mmu->dynamicMappingStart)
++ * gcdMMU_STLB_4K_ENTRY_NUM
++ + stlb;
++
++ gcmkPRINT(" Page table entry = 0x%08X", _ReadPageEntry(pageTable + index));
++ }
++ else
++ {
++ gcsMMU_STLB_PTR stlbObj = Mmu->staticSTLB;
++ gctUINT32 entry = Mmu->mtlbLogical[mtlb];
++
++ stlb = (Address & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++
++ entry &= 0xFFFFFFF0;
++
++ while (stlbObj)
++ {
++
++ if (entry == stlbObj->physBase)
++ {
++ gcmkPRINT(" Page table entry = 0x%08X", stlbObj->logical[stlb]);
++ break;
++ }
++
++ stlbObj = stlbObj->next;
++ }
++ }
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************
++****************************** T E S T C O D E ******************************
++******************************************************************************/
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c 2016-06-19 22:11:55.145150505 +0200
+@@ -0,0 +1,522 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++/*******************************************************************************
++**
++** gckVGMMU_Construct
++**
++** Construct a new gckVGMMU object.
++**
++** INPUT:
++**
++** gckVGKERNEL Kernel
++** Pointer to an gckVGKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckVGMMU * Mmu
++** Pointer to a variable that receives the gckVGMMU object pointer.
++*/
++gceSTATUS gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT32 MmuSize,
++ OUT gckVGMMU * Mmu
++ )
++{
++ gckOS os;
++ gckVGHARDWARE hardware;
++ gceSTATUS status;
++ gckVGMMU mmu;
++ gctUINT32 * pageTable;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=0x%x Mmu=0x%x", Kernel, MmuSize, Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckVGHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckVGMMU object. */
++ status = gckOS_Allocate(os, sizeof(struct _gckVGMMU), (gctPOINTER *) &mmu);
++
++ if (status < 0)
++ {
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate gckVGMMU object.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Initialize the gckVGMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++
++ /* Create the mutex. */
++ status = gckOS_CreateMutex(os, &mmu->mutex);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Allocate the page table. */
++ mmu->pageTableSize = (gctUINT32)MmuSize;
++ status = gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ &mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Compute number of entries in page table. */
++ mmu->entryCount = (gctUINT32)mmu->pageTableSize / sizeof(gctUINT32);
++ mmu->entry = 0;
++
++ /* Mark the entire page table as available. */
++ pageTable = (gctUINT32 *) mmu->pageTableLogical;
++ for (i = 0; i < mmu->entryCount; i++)
++ {
++ pageTable[i] = (gctUINT32)~0;
++ }
++
++ /* Set page table address. */
++ status = gckVGHARDWARE_SetMMU(hardware, mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(mmu->os,
++ mmu->pageTablePhysical,
++ mmu->pageTableLogical,
++ mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not program page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Return the gckVGMMU object pointer. */
++ *Mmu = mmu;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u entries at %p.(0x%08X)\n",
++ __FUNCTION__, __LINE__,
++ mmu->entryCount,
++ mmu->pageTableLogical,
++ mmu->pageTablePhysical
++ );
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_Destroy
++**
++** Destroy a nAQMMU object.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->mutex));
++
++ /* Mark the gckVGMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGMMU object. */
++ gcmkVERIFY_OK(gckOS_Free(Mmu->os, Mmu));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 tail, index, i;
++ gctUINT32 * table;
++ gctBOOL allocated = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=0x%x PageTable=0x%x Address=0x%x",
++ Mmu, PageCount, PageTable, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ if (PageCount > Mmu->entryCount)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): page table too small for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ gcmkFOOTER_NO();
++ /* Not enough pages avaiable. */
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Grab the mutex. */
++ status = gckOS_AcquireMutex(Mmu->os, Mmu->mutex, gcvINFINITE);
++
++ if (status < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): could not acquire mutex.\n"
++ ,__FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Compute the tail for this allocation. */
++ tail = Mmu->entryCount - (gctUINT32)PageCount;
++
++ /* Walk all entries until we find enough slots. */
++ for (index = Mmu->entry; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++
++ if (!allocated)
++ {
++ if (status >= 0)
++ {
++ /* Walk all entries until we find enough slots. */
++ for (index = 0; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++ }
++ }
++
++ if (!allocated && (status >= 0))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): not enough free pages for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ /* Not enough empty slots available. */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ if (status >= 0)
++ {
++ /* Build virtual address. */
++ status = gckVGHARDWARE_BuildVirtualAddress(Mmu->hardware,
++ index,
++ 0,
++ Address);
++
++ if (status >= 0)
++ {
++ /* Update current entry into page table. */
++ Mmu->entry = index + (gctUINT32)PageCount;
++
++ /* Return pointer to page table. */
++ *PageTable = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): allocated %u pages at index %u (0x%08X) @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ index,
++ *Address,
++ *PageTable
++ );
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->mutex));
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32 * table;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=0x%x",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): freeing %u pages at index %u @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ ((gctUINT32 *) PageTable - (gctUINT32 *) Mmu->pageTableLogical),
++ PageTable
++ );
++
++ /* Convert pointer. */
++ table = (gctUINT32 *) PageTable;
++
++ /* Mark the page table entries as available. */
++ while (PageCount-- > 0)
++ {
++ *table++ = (gctUINT32)~0;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ *PageEntry = PageAddress;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ )
++{
++ gckVGHARDWARE hardware;
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_os.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_os.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_os.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_os.c 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,8133 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/workqueue.h>
++#include <linux/irqflags.h>
++#include <linux/math64.h>
++#include <linux/delay.h>
++#include <linux/anon_inodes.h>
++#include <linux/lockdep.h>
++
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++#include <linux/file.h>
++#include "gc_hal_kernel_sync.h"
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++#include "gc_hal_kernel_allocator.h"
++
++#define MEMORY_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryLock, \
++ gcvINFINITE))
++
++#define MEMORY_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryLock))
++
++#define MEMORY_MAP_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryMapLock, \
++ gcvINFINITE))
++
++#define MEMORY_MAP_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryMapLock))
++
++
++/* Create a new mutex. */
++static gceSTATUS
++gckOS_CreateNamedMutex(
++ IN gckOS Os,
++ IN struct lock_class_key *key,
++ IN const char *name,
++ OUT gctPOINTER * Mutex
++ );
++
++static struct lock_class_key gckOS_key;
++static struct lock_class_key gckOS_MM_key;
++static struct lock_class_key gckOS_Signal_key;
++#if gcdANDROID_NATIVE_FENCE_SYNC
++static struct lock_class_key gckOS_SyncPoint_key;
++#endif
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++static gctINT
++_GetThreadID(
++ void
++ )
++{
++ return task_pid_vnr(current);
++}
++
++static PLINUX_MDL
++_CreateMdl(
++ void
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER();
++
++ mdl = (PLINUX_MDL)kzalloc(sizeof(struct _LINUX_MDL), GFP_KERNEL | gcdNOWARN);
++
++ gcmkFOOTER_ARG("0x%X", mdl);
++ return mdl;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ );
++
++static gceSTATUS
++_DestroyMdl(
++ IN PLINUX_MDL Mdl
++ )
++{
++ PLINUX_MDL_MAP mdlMap, next;
++
++ gcmkHEADER_ARG("Mdl=0x%X", Mdl);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Mdl != gcvNULL);
++
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ next = mdlMap->next;
++
++ gcmkVERIFY_OK(_DestroyMdlMap(Mdl, mdlMap));
++
++ mdlMap = next;
++ }
++
++ kfree(Mdl);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++static PLINUX_MDL_MAP
++_CreateMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++
++ mdlMap = (PLINUX_MDL_MAP)kmalloc(sizeof(struct _LINUX_MDL_MAP), GFP_KERNEL | gcdNOWARN);
++ if (mdlMap == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ mdlMap->pid = ProcessID;
++ mdlMap->vmaAddr = gcvNULL;
++ mdlMap->vma = gcvNULL;
++ mdlMap->count = 0;
++
++ mdlMap->next = Mdl->maps;
++ Mdl->maps = mdlMap;
++
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ )
++{
++ PLINUX_MDL_MAP prevMdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X MdlMap=0x%X", Mdl, MdlMap);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(MdlMap != gcvNULL);
++ gcmkASSERT(Mdl->maps != gcvNULL);
++
++ if (Mdl->maps == MdlMap)
++ {
++ Mdl->maps = MdlMap->next;
++ }
++ else
++ {
++ prevMdlMap = Mdl->maps;
++
++ while (prevMdlMap->next != MdlMap)
++ {
++ prevMdlMap = prevMdlMap->next;
++
++ gcmkASSERT(prevMdlMap != gcvNULL);
++ }
++
++ prevMdlMap->next = MdlMap->next;
++ }
++
++ kfree(MdlMap);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++ if(Mdl == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if (mdlMap->pid == ProcessID)
++ {
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvNULL;
++}
++
++/*******************************************************************************
++** Integer Id Management.
++*/
++gceSTATUS
++_AllocateIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctPOINTER KernelPointer,
++ OUT gctUINT32 *Id
++ )
++{
++ int result;
++ gctINT next;
++
++ idr_preload(GFP_KERNEL | gcdNOWARN);
++
++ spin_lock(&Database->lock);
++
++ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
++
++ result = idr_alloc(&Database->idr, KernelPointer, next, 0, GFP_ATOMIC);
++
++ /* ID allocated should not be 0. */
++ gcmkASSERT(result != 0);
++
++ if (result > 0)
++ {
++ Database->curr = *Id = result;
++ }
++
++ spin_unlock(&Database->lock);
++
++ idr_preload_end();
++
++ if (result < 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_QueryIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER pointer;
++
++ spin_lock(&Database->lock);
++
++ pointer = idr_find(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ if(pointer)
++ {
++ *KernelPointer = pointer;
++ return gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_OS,
++ "%s(%d) Id = %d is not found",
++ __FUNCTION__, __LINE__, Id);
++
++ return gcvSTATUS_NOT_FOUND;
++ }
++}
++
++gceSTATUS
++_DestroyIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id
++ )
++{
++ spin_lock(&Database->lock);
++
++ idr_remove(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_QueryProcessPageTable(
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINTPTR_T logical = (gctUINTPTR_T)Logical;
++ pgd_t *pgd;
++ pud_t *pud;
++ pmd_t *pmd;
++ pte_t *pte;
++
++ if (!current->mm)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pgd = pgd_offset(current->mm, logical);
++ if (pgd_none(*pgd) || pgd_bad(*pgd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pud = pud_offset(pgd, logical);
++ if (pud_none(*pud) || pud_bad(*pud))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pmd = pmd_offset(pud, logical);
++ if (pmd_none(*pmd) || pmd_bad(*pmd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pte = pte_offset_map(pmd, logical);
++ if (!pte)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ if (!pte_present(*pte))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ *Address = (pte_pfn(*pte) << PAGE_SHIFT) | (logical & ~PAGE_MASK);
++
++ return gcvSTATUS_OK;
++}
++
++gctBOOL
++_AllowAccess(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address
++ )
++{
++ gctUINT32 data;
++
++ /* Check external clock state. */
++ if (Os->clockStates[Core] == gcvFALSE)
++ {
++ gcmkPRINT("[galcore]: %s(%d) External clock off", __FUNCTION__, __LINE__);
++ return gcvFALSE;
++ }
++
++ /* Check internal clock state. */
++ if (Address == 0)
++ {
++ return gcvTRUE;
++ }
++
++ data = readl((gctUINT8 *)Os->device->registerBases[Core] + 0x0);
++
++ if ((data & 0x3) == 0x3)
++ {
++ gcmkPRINT("[galcore]: %s(%d) Internal clock off", __FUNCTION__, __LINE__);
++ return gcvFALSE;
++ }
++
++ return gcvTRUE;
++}
++
++static gceSTATUS
++_ShrinkMemory(
++ IN gckOS Os
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->shrinkMemory)
++ {
++ platform->ops->shrinkMemory(platform);
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Construct
++**
++** Construct a new gckOS object.
++**
++** INPUT:
++**
++** gctPOINTER Context
++** Pointer to the gckGALDEVICE class.
++**
++** OUTPUT:
++**
++** gckOS * Os
++** Pointer to a variable that will hold the pointer to the gckOS object.
++*/
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gctINT i;
++
++ gcmkHEADER_ARG("Context=0x%X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Os != gcvNULL);
++
++ /* Allocate the gckOS object. */
++ os = (gckOS) kmalloc(gcmSIZEOF(struct _gckOS), GFP_KERNEL | gcdNOWARN);
++
++ if (os == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ /* Zero the memory. */
++ gckOS_ZeroMemory(os, gcmSIZEOF(struct _gckOS));
++
++ /* Initialize the gckOS object. */
++ os->object.type = gcvOBJ_OS;
++
++ /* Set device device. */
++ os->device = Context;
++
++ /* Set allocateCount to 0, gckOS_Allocate has not been used yet. */
++ atomic_set(&os->allocateCount, 0);
++
++ /* Initialize the memory lock. */
++ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_key, "memoryLock", &os->memoryLock));
++ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_MM_key, "memoryMapLock", &os->memoryMapLock));
++
++ /* Create debug lock mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->debugLock));
++
++ os->mdlHead = os->mdlTail = gcvNULL;
++
++ /* Get the kernel process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&os->kernelProcessID));
++
++ /*
++ * Initialize the signal manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_Signal_key, "signalMutex", &os->signalMutex));
++
++ /* Initialize signal id database lock. */
++ spin_lock_init(&os->signalDB.lock);
++
++ /* Initialize signal id database. */
++ idr_init(&os->signalDB.idr);
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Initialize the sync point manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_SyncPoint_key, "syncPointMutex", &os->syncPointMutex));
++
++ /* Initialize sync point id database lock. */
++ spin_lock_init(&os->syncPointDB.lock);
++
++ /* Initialize sync point id database. */
++ idr_init(&os->syncPointDB.idr);
++#endif
++
++ /* Create a workqueue for os timer. */
++ os->workqueue = create_singlethread_workqueue("galcore workqueue");
++
++ if (os->workqueue == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ os->paddingPage = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN);
++ if (os->paddingPage == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ else
++ {
++ SetPageReserved(os->paddingPage);
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ mutex_init(&os->registerAccessLocks[i]);
++ }
++
++ gckOS_ImportAllocators(os);
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (((gckGALDEVICE)(os->device))->mmu == gcvFALSE)
++ {
++ /* Only use IOMMU when internal MMU is not enabled. */
++ status = gckIOMMU_Construct(os, &os->iommu);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Fail to setup IOMMU",
++ __FUNCTION__, __LINE__
++ );
++ }
++ }
++#endif
++
++ /* Return pointer to the gckOS object. */
++ *Os = os;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Os=0x%X", *Os);
++ return gcvSTATUS_OK;
++
++OnError:
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (os->syncPointMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->syncPointMutex));
++ }
++#endif
++
++ if (os->signalMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->signalMutex));
++ }
++
++ if (os->memoryMapLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryMapLock));
++ }
++
++ if (os->memoryLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryLock));
++ }
++
++ if (os->debugLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->debugLock));
++ }
++
++ if (os->workqueue != gcvNULL)
++ {
++ destroy_workqueue(os->workqueue);
++ }
++
++ kfree(os);
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Destroy
++**
++** Destroy an gckOS object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ if (Os->paddingPage != gcvNULL)
++ {
++ ClearPageReserved(Os->paddingPage);
++ __free_page(Os->paddingPage);
++ Os->paddingPage = gcvNULL;
++ }
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Destroy the sync point manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->syncPointMutex));
++#endif
++
++ /*
++ * Destroy the signal manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->signalMutex));
++
++ /* Destroy the memory lock. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryMapLock));
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryLock));
++
++ /* Destroy debug lock mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->debugLock));
++
++ /* Wait for all works done. */
++ flush_workqueue(Os->workqueue);
++
++ /* Destory work queue. */
++ destroy_workqueue(Os->workqueue);
++
++ gckOS_FreeAllocators(Os);
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gckIOMMU_Destory(Os, Os->iommu);
++ }
++#endif
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++
++ /* Mark the gckOS object as unknown. */
++ Os->object.type = gcvOBJ_UNKNOWN;
++
++
++ /* Free the gckOS object. */
++ kfree(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ gceSTATUS status;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ gcmkHEADER();
++
++ *PageCount = mdl->numPages;
++
++ gcmkONERROR(allocator->ops->MapKernel(allocator, mdl, Logical));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ gcmkHEADER();
++
++ allocator->ops->UnmapKernel(allocator, mdl, Logical);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ return gckOS_LockPages(Os, Physical, Bytes, gcvFALSE, Logical, PageCount);
++}
++
++gceSTATUS
++gckOS_DestroyUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ return gckOS_UnlockPages(Os, Physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckOS_Allocate
++**
++** Allocate memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ gcmkONERROR(gckOS_AllocateMemory(Os, Bytes, Memory));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Free
++**
++** Free allocated memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Memory=0x%X", Os, Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ gcmkONERROR(gckOS_FreeMemory(Os, Memory));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateMemory
++**
++** Allocate memory wrapper.
++**
++** INPUT:
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gctPOINTER memory;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ if (Bytes > PAGE_SIZE)
++ {
++ memory = (gctPOINTER) vmalloc(Bytes);
++ }
++ else
++ {
++ memory = (gctPOINTER) kmalloc(Bytes, GFP_KERNEL | gcdNOWARN);
++ }
++
++ if (memory == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Increase count. */
++ atomic_inc(&Os->allocateCount);
++
++ /* Return pointer to the memory allocation. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeMemory
++**
++** Free allocated memory wrapper.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Free the memory from the OS pool. */
++ if (is_vmalloc_addr(Memory))
++ {
++ vfree(Memory);
++ }
++ else
++ {
++ kfree(Memory);
++ }
++
++ /* Decrease count. */
++ atomic_dec(&Os->allocateCount);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapMemory
++**
++** Map physical memory into the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the logical address of the
++** mapped memory.
++*/
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++ mdlMap->vmaAddr = (char *)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): mdl->numPages: %d mdl->vmaAddr: 0x%X",
++ __FUNCTION__, __LINE__,
++ mdl->numPages,
++ mdlMap->vmaAddr
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (!mdlMap->vma)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): find_vma error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ up_write(&current->mm->mmap_sem);
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_writecombine(Os->device->dev,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): dma_mmap_coherent error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#else
++#if !gcdPAGED_MEMORY_CACHEABLE
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++# endif
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages*PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): remap_pfn_range error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#endif
++
++ up_write(&current->mm->mmap_sem);
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ *Logical = mdlMap->vmaAddr;
++
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemory
++**
++** Unmap physical memory out of the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemoryEx(Os, Physical, Bytes, Logical, _GetProcessID());
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemoryEx
++**
++** Unmap physical memory in the specified process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** gctUINT32 PID
++** Pid of the process that opened the device and mapped this memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X PID=%d",
++ Os, Physical, Bytes, Logical, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PID != 0);
++
++ MEMORY_LOCK(Os);
++
++ if (Logical)
++ {
++ mdlMap = FindMdlMap(mdl, PID);
++
++ if (mdlMap == gcvNULL || mdlMap->vmaAddr == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ _UnmapUserLogical(mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE);
++
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserLogical
++**
++** Unmap user logical memory out of physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemory(Os, Physical, Bytes, Logical);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateNonPagedMemory
++**
++** Allocate a number of pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that holds the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that hold the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that will hold the physical address of the
++** allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** allocation.
++*/
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctSIZE_T bytes;
++ gctINT numPages;
++ PLINUX_MDL mdl = gcvNULL;
++ PLINUX_MDL_MAP mdlMap = gcvNULL;
++ gctSTRING addr;
++ gckKERNEL kernel;
++#ifdef NO_DMA_COHERENT
++ struct page * page;
++ long size, order;
++ gctPOINTER vaddr;
++#endif
++ gctBOOL locked = gcvFALSE;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Align number of bytes to page size. */
++ bytes = gcmALIGN(*Bytes, PAGE_SIZE);
++
++ /* Get total number of pages.. */
++ numPages = GetPageCount(bytes, 0);
++
++ /* Allocate mdl+vector structure */
++ mdl = _CreateMdl();
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->pagedMem = 0;
++ mdl->numPages = numPages;
++
++ MEMORY_LOCK(Os);
++ locked = gcvTRUE;
++
++#ifndef NO_DMA_COHERENT
++#ifdef CONFIG_ARM64
++ addr = dma_alloc_coherent(Os->device->dev,
++#else
++ addr = dma_alloc_writecombine(Os->device->dev,
++#endif
++ mdl->numPages * PAGE_SIZE,
++ &mdl->dmaHandle,
++ GFP_KERNEL | gcdNOWARN);
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ order = get_order(size);
++
++ page = alloc_pages(GFP_KERNEL | gcdNOWARN, order);
++
++ if (page == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ vaddr = (gctPOINTER)page_address(page);
++ mdl->contiguous = gcvTRUE;
++ mdl->u.contiguousPages = page;
++ addr = _CreateKernelVirtualMapping(mdl);
++ mdl->dmaHandle = virt_to_phys(vaddr);
++ mdl->kaddr = vaddr;
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++
++#if !defined(CONFIG_PPC)
++ /* Cache invalidate. */
++ dma_sync_single_for_device(
++ Os->device->dev,
++ page_to_phys(page),
++ bytes,
++ DMA_FROM_DEVICE);
++#endif
++
++ while (size > 0)
++ {
++ SetPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++#endif
++
++ if (addr == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ kernel = Os->device->kernels[gcvCORE_MAJOR] != gcvNULL ?
++ Os->device->kernels[gcvCORE_MAJOR] : Os->device->kernels[gcvCORE_2D];
++ if (((Os->device->baseAddress & 0x80000000) != (mdl->dmaHandle & 0x80000000)) &&
++ kernel->hardware->mmuVersion == 0)
++ {
++ mdl->dmaHandle = (mdl->dmaHandle & ~0x80000000)
++ | (Os->device->baseAddress & 0x80000000);
++ }
++
++ mdl->addr = addr;
++
++ if (InUserSpace)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Only after mmap this will be valid. */
++
++ /* We need to map this to user space. */
++ mdlMap->vmaAddr = (gctSTRING) vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_coherent(Os->device->dev,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): dma_mmap_coherent error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#else
++ mdlMap->vma->vm_page_prot = gcmkNONPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages * PAGE_SIZE,
++ mdlMap->vma->vm_page_prot))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): remap_pfn_range error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#endif /* NO_DMA_COHERENT */
++
++ up_write(&current->mm->mmap_sem);
++
++ *Logical = mdlMap->vmaAddr;
++ }
++ else
++ {
++ *Logical = (gctPOINTER)mdl->addr;
++ }
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to the tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Return allocated memory. */
++ *Bytes = bytes;
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdlMap != gcvNULL)
++ {
++ /* Free LINUX_MDL_MAP. */
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ if (mdl != gcvNULL)
++ {
++ /* Free LINUX_MDL. */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++ }
++ *Physical = gcvNULL;
++ *Bytes = 0;
++
++ if (locked)
++ {
++ /* Unlock memory. */
++ MEMORY_UNLOCK(Os);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeNonPagedMemory
++**
++** Free previously allocated and mapped pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes allocated.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocated memory.
++**
++** gctPOINTER Logical
++** Logical address of the allocated memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++#ifdef NO_DMA_COHERENT
++ unsigned size;
++ gctPOINTER vaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu Physical=0x%X Logical=0x%X",
++ Os, Bytes, Physical, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert physical address into a pointer to a MDL. */
++ mdl = (PLINUX_MDL) Physical;
++
++ MEMORY_LOCK(Os);
++
++#ifndef NO_DMA_COHERENT
++#ifdef CONFIG_ARM64
++ dma_free_coherent(Os->device->dev,
++#else
++ dma_free_writecombine(Os->device->dev,
++#endif
++ mdl->numPages * PAGE_SIZE,
++ mdl->addr,
++ mdl->dmaHandle);
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ vaddr = mdl->kaddr;
++
++ while (size > 0)
++ {
++ ClearPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++
++ free_pages((unsigned long)mdl->kaddr, get_order(mdl->numPages * PAGE_SIZE));
++
++ _DestoryKernelVirtualMapping(mdl->addr);
++#endif /* NO_DMA_COHERENT */
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ /* No mapped memory exists when free nonpaged memory */
++ gcmkASSERT(mdlMap->vmaAddr == gcvNULL);
++
++ mdlMap = mdlMap->next;
++ }
++
++ /* Remove the node from global list.. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReadRegister
++**
++** Read data from a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** OUTPUT:
++**
++** gctUINT32 * Data
++** Pointer to a variable that receives the data read from the register.
++*/
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ return gckOS_ReadRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X", Os, Core, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ if (!in_interrupt())
++ {
++ mutex_lock(&Os->registerAccessLocks[Core]);
++ }
++
++ BUG_ON(!_AllowAccess(Os, Core, Address));
++
++ *Data = readl((gctUINT8 *)Os->device->registerBases[Core] + Address);
++
++ if (!in_interrupt())
++ {
++ mutex_unlock(&Os->registerAccessLocks[Core]);
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_WriteRegister
++**
++** Write data to a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ return gckOS_WriteRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X Data=0x%08x", Os, Core, Address, Data);
++
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++
++ if (!in_interrupt())
++ {
++ mutex_lock(&Os->registerAccessLocks[Core]);
++ }
++
++ BUG_ON(!_AllowAccess(Os, Core, Address));
++
++ writel(Data, (gctUINT8 *)Os->device->registerBases[Core] + Address);
++
++ if (!in_interrupt())
++ {
++ mutex_unlock(&Os->registerAccessLocks[Core]);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPageSize
++**
++** Get the system's page size.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * PageSize
++** Pointer to a variable that will receive the system's page size.
++*/
++gceSTATUS gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(PageSize != gcvNULL);
++
++ /* Return the page size. */
++ *PageSize = (gctSIZE_T) PAGE_SIZE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageSize", *PageSize);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddress
++**
++** Get the physical system address of a corresponding virtual address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X", Os, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Query page table of current process first. */
++ status = _QueryProcessPageTable(Logical, Address);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Get current process ID. */
++ processID = _GetProcessID();
++
++ /* Route through other function. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddressProcess(Os, Logical, processID, Address));
++ }
++
++ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(Os, *Address, Address));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UserLogicalToPhysical
++**
++** Get the physical system address of a corresponding user virtual address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the 32-bit physical address.
++*/
++gceSTATUS gckOS_UserLogicalToPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ return gckOS_GetPhysicalAddress(Os, Logical, Address);
++}
++
++gceSTATUS
++_ConvertLogical2Physical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ IN PLINUX_MDL Mdl,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ gctINT8_PTR base, vBase;
++ gctUINT32 offset;
++ PLINUX_MDL_MAP map;
++ gcsUSER_MAPPING_PTR userMap;
++
++ base = (Mdl == gcvNULL) ? gcvNULL : (gctINT8_PTR) Mdl->addr;
++
++ /* Check for the logical address match. */
++ if ((base != gcvNULL)
++ && ((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - base;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ /* paged memory is not mapped to kernel space. */
++ return gcvSTATUS_INVALID_ADDRESS;
++ }
++ else
++ {
++ *Physical = gcmPTR2INT32(virt_to_phys(base)) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++
++ /* Walk user maps. */
++ for (userMap = Os->userMap; userMap != gcvNULL; userMap = userMap->next)
++ {
++ if (((gctINT8_PTR) Logical >= userMap->start)
++ && ((gctINT8_PTR) Logical < userMap->end)
++ )
++ {
++ *Physical = userMap->physical
++ + (gctUINT32) ((gctINT8_PTR) Logical - userMap->start);
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ if (ProcessID != Os->kernelProcessID)
++ {
++ map = FindMdlMap(Mdl, (gctINT) ProcessID);
++ vBase = (map == gcvNULL) ? gcvNULL : (gctINT8_PTR) map->vmaAddr;
++
++ /* Is the given address within that range. */
++ if ((vBase != gcvNULL)
++ && ((gctINT8_PTR) Logical >= vBase)
++ && ((gctINT8_PTR) Logical < vBase + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - vBase;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, offset/PAGE_SIZE);
++ }
++ else
++ {
++ *Physical = page_to_phys(Mdl->u.contiguousPages) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ /* Address not yet found. */
++ return gcvSTATUS_INVALID_ADDRESS;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddressProcess
++**
++** Get the physical system address of a corresponding virtual address for a
++** given process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** gctUINT32 ProcessID
++** Process ID.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ )
++{
++ PLINUX_MDL mdl;
++ gctINT8_PTR base;
++ gckALLOCATOR allocator = gcvNULL;
++ gceSTATUS status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X ProcessID=%d", Os, Logical, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* First try the contiguous memory pool. */
++ if (Os->device->contiguousMapped)
++ {
++ base = (gctINT8_PTR) Os->device->contiguousBase;
++
++ if (((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Os->device->contiguousSize)
++ )
++ {
++ /* Convert logical address into physical. */
++ *Address = Os->device->contiguousVidMem->baseAddress
++ + (gctINT8_PTR) Logical - base;
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Try the contiguous memory pool. */
++ mdl = (PLINUX_MDL) Os->device->contiguousPhysical;
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Walk all MDLs. */
++ for (mdl = Os->mdlHead; mdl != gcvNULL; mdl = mdl->next)
++ {
++ /* Try this MDL. */
++ allocator = mdl->allocator;
++
++ if (allocator)
++ {
++ status = allocator->ops->LogicalToPhysical(
++ allocator,
++ mdl,
++ Logical,
++ ProcessID,
++ Address
++ );
++ }
++ else
++ {
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ }
++
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkONERROR(status);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPhysical
++**
++** Map a physical address into kernel space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Physical
++** Physical address of the memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the base address of the mapped
++** memory.
++*/
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctPOINTER logical;
++ PLINUX_MDL mdl;
++ gctUINT32 physical = Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* Go through our mapping to see if we know this physical address already. */
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->dmaHandle != 0)
++ {
++ if ((physical >= mdl->dmaHandle)
++ && (physical < mdl->dmaHandle + mdl->numPages * PAGE_SIZE)
++ )
++ {
++ *Logical = mdl->addr + (physical - mdl->dmaHandle);
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ if (mdl == gcvNULL)
++ {
++ struct page * page = pfn_to_page(physical >> PAGE_SHIFT);
++
++ if (pfn_valid(page_to_pfn(page)))
++ {
++ gctUINT32 offset = physical & ~PAGE_MASK;
++ struct page ** pages;
++ gctUINT numPages;
++ gctINT i;
++
++ numPages = GetPageCount(PAGE_ALIGN(offset + Bytes), 0);
++
++ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ pages[i] = nth_page(page, i);
++ }
++
++ logical = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL));
++
++ kfree(pages);
++
++ if (logical == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Failed to vmap",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Out of resources. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ logical += offset;
++ }
++ else
++ {
++ /* Map memory as cached memory. */
++ request_mem_region(physical, Bytes, "MapRegion");
++ logical = (gctPOINTER) ioremap_nocache(physical, Bytes);
++
++ if (logical == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Failed to ioremap",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Out of resources. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++ }
++
++ /* Return pointer to mapped memory. */
++ *Logical = logical;
++ }
++
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapPhysical
++**
++** Unmap a previously mapped memory region from kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Pointer to the base address of the memory to unmap.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ MEMORY_LOCK(Os);
++
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->addr != gcvNULL)
++ {
++ if (Logical >= (gctPOINTER)mdl->addr
++ && Logical < (gctPOINTER)((gctSTRING)mdl->addr + mdl->numPages * PAGE_SIZE))
++ {
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ if (mdl == gcvNULL)
++ {
++ /* Unmap the memory. */
++ vunmap((void *)((unsigned long)Logical & PAGE_MASK));
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateMutex
++**
++** Create a new mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Mutex
++** Pointer to a variable that will hold a pointer to the mutex.
++*/
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Allocate the mutex structure. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct mutex), Mutex));
++
++ /* Initialize the mutex. */
++ mutex_init(*Mutex);
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Mutex=0x%X", *Mutex);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckOS_CreateNamedMutex(
++ IN gckOS Os,
++ IN struct lock_class_key *key,
++ IN const char *name,
++ OUT gctPOINTER * Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Allocate the mutex structure. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct mutex), Mutex));
++
++ /* Initialize the mutex. */
++ mutex_init(*Mutex);
++ lockdep_set_class_and_name((struct mutex *)Mutex, key, name);
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Mutex=0x%X", *Mutex);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DeleteMutex
++**
++** Delete a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mute to be deleted.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%X", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Destroy the mutex. */
++ mutex_destroy((struct mutex *)Mutex);
++
++ /* Free the mutex structure. */
++ gcmkONERROR(gckOS_Free(Os, Mutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireMutex
++**
++** Acquire a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be acquired.
++**
++** gctUINT32 Timeout
++** Timeout value specified in milliseconds.
++** Specify the value of gcvINFINITE to keep the thread suspended
++** until the mutex has been acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x Timeout=%u", Os, Mutex, Timeout);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ if (Timeout == gcvINFINITE)
++ {
++ /* Lock the mutex. */
++ mutex_lock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ for (;;)
++ {
++ /* Try to acquire the mutex. */
++ if (mutex_trylock(Mutex))
++ {
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ if (Timeout-- == 0)
++ {
++ break;
++ }
++
++ /* Wait for 1 millisecond. */
++ gcmkVERIFY_OK(gckOS_Delay(Os, 1));
++ }
++
++ /* Timeout. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_TIMEOUT);
++ return gcvSTATUS_TIMEOUT;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseMutex
++**
++** Release an acquired mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Release the mutex. */
++ mutex_unlock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchange
++**
++** Atomically exchange a pair of 32-bit values.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctINT32_PTR Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctINT32 NewValue
++** Specifies a new value for the 32-bit value pointed to by Target.
++**
++** OUT gctINT32_PTR OldValue
++** The old value of the 32-bit value pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=%u", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(OldValue != gcvNULL);
++
++ /* Exchange the pair of 32-bit values. */
++ *OldValue = (gctUINT32) atomic_xchg((atomic_t *) Target, (int) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=%u", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchangePtr
++**
++** Atomically exchange a pair of pointers.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctPOINTER * Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctPOINTER NewValue
++** Specifies a new value for the pointer pointed to by Target.
++**
++** OUT gctPOINTER * OldValue
++** The old value of the pointer pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=0x%X", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(OldValue != gcvNULL);
++
++ /* Exchange the pair of pointers. */
++ *OldValue = (gctPOINTER)(gctUINTPTR_T) atomic_xchg((atomic_t *) Target, (int)(gctUINTPTR_T) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=0x%X", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicSetMask
++**
++** Atomically set mask to Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to set.
++**
++** IN gctUINT32 Mask
++** Mask to set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval | Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomClearMask
++**
++** Atomically clear mask from Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to clear.
++**
++** IN gctUINT32 Mask
++** Mask to clear.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval & ~Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Allocate the atom. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(atomic_t), Atom));
++
++ /* Initialize the atom. */
++ atomic_set((atomic_t *) *Atom, 0);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Atom=0x%X", *Atom);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Free the atom. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Os, Atom));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Return the current value of atom. */
++ *Value = atomic_read((atomic_t *) Atom);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x Value=%d", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Set the current value of atom. */
++ atomic_set((atomic_t *) Atom, Value);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Increment the atom. */
++ *Value = atomic_inc_return((atomic_t *) Atom) - 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Decrement the atom. */
++ *Value = atomic_dec_return((atomic_t *) Atom) + 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Delay
++**
++** Delay execution of the current thread for a number of milliseconds.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Delay
++** Delay to sleep, specified in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Delay=%u", Os, Delay);
++
++ if (Delay > 0)
++ {
++ ktime_t delay = ktime_set((Delay / MSEC_PER_SEC), (Delay % MSEC_PER_SEC) * NSEC_PER_MSEC);
++ __set_current_state(TASK_UNINTERRUPTIBLE);
++ schedule_hrtimeout(&delay, HRTIMER_MODE_REL);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTicks
++**
++** Get the number of milliseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT32_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ )
++{
++ gcmkHEADER();
++
++ *Time = jiffies_to_msecs(jiffies);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_TicksAfter
++**
++** Compare time values got from gckOS_GetTicks.
++**
++** INPUT:
++** gctUINT32 Time1
++** First time value to be compared.
++**
++** gctUINT32 Time2
++** Second time value to be compared.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR IsAfter
++** Pointer to a variable to result.
++**
++*/
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ )
++{
++ gcmkHEADER();
++
++ *IsAfter = time_after((unsigned long)Time1, (unsigned long)Time2);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTime
++**
++** Get the number of microseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT64_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ )
++{
++ struct timeval tv;
++ gcmkHEADER();
++
++ /* Return the time of day in microseconds. */
++ do_gettimeofday(&tv);
++ *Time = (tv.tv_sec * 1000000ULL) + tv.tv_usec;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MemoryBarrier
++**
++** Make sure the CPU has executed everything up to this point and the data got
++** written to the specified pointer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of memory that needs to be barriered.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X", Os, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ mb();
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemory
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ /* Allocate the memory. */
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(Os, gcvALLOC_FLAG_NONE, Bytes, gcvNULL, Physical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemoryEx
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Flag
++** Allocation attribute.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctUINT32 * Gid
++** Save the global ID for the piece of allocated memory.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gctUINT32 * Gid,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gctINT numPages;
++ PLINUX_MDL mdl = gcvNULL;
++ gctSIZE_T bytes;
++ gceSTATUS status = gcvSTATUS_OUT_OF_MEMORY;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Flag=%x Bytes=%lu", Os, Flag, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ bytes = gcmALIGN(Bytes, PAGE_SIZE);
++
++ numPages = GetPageCount(bytes, 0);
++
++ mdl = _CreateMdl();
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Walk all allocators. */
++ list_for_each_entry(allocator, &Os->allocatorList, head)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d) flag = %x allocator->capability = %x",
++ __FUNCTION__, __LINE__, Flag, allocator->capability);
++
++ if ((Flag & allocator->capability) != Flag)
++ {
++ continue;
++ }
++
++ status = allocator->ops->Alloc(allocator, mdl, numPages, Flag);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ mdl->allocator = allocator;
++ break;
++ }
++ }
++
++ /* Check status. */
++ gcmkONERROR(status);
++
++ mdl->dmaHandle = 0;
++ mdl->addr = 0;
++ mdl->numPages = numPages;
++ mdl->pagedMem = 1;
++ mdl->contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS;
++
++ if (Gid != gcvNULL)
++ {
++ *Gid = mdl->gid;
++ }
++
++ MEMORY_LOCK(Os);
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Return physical address. */
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdl != gcvNULL)
++ {
++ /* Free the memory. */
++ _DestroyMdl(mdl);
++ }
++ *Physical = gcvNULL;
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("Os=0x%X Flag=%x Bytes=%lu", Os, Flag, Bytes);
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreePagedMemory
++**
++** Free memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL) Physical;
++ gckALLOCATOR allocator = (gckALLOCATOR)mdl->allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ MEMORY_LOCK(Os);
++
++ /* Remove the node from global list. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ allocator->ops->Free(allocator, mdl);
++
++ /* Free the structure... */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_LockPages
++**
++** Lock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctBOOL Cacheable
++** Cache mode of mapping.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the address of the mapped
++** memory.
++**
++** gctSIZE_T * PageCount
++** Pointer to a variable that receives the number of pages required for
++** the page table according to the GPU page size.
++*/
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ gceSTATUS status;
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount != gcvNULL);
++
++ mdl = (PLINUX_MDL) Physical;
++ allocator = mdl->allocator;
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++ status = allocator->ops->MapUser(allocator, mdl, mdlMap, Cacheable);
++
++ if (gcmIS_ERROR(status))
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", status);
++ return status;
++ }
++ }
++
++ mdlMap->count++;
++
++ /* Convert pointer to MDL. */
++ *Logical = mdlMap->vmaAddr;
++
++ /* Return the page number according to the GPU page size. */
++ gcmkASSERT((PAGE_SIZE / 4096) >= 1);
++
++ *PageCount = mdl->numPages * (PAGE_SIZE / 4096);
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(gckOS_CacheFlush(
++ Os,
++ _GetProcessID(),
++ Physical,
++ gcvINVALID_ADDRESS,
++ (gctPOINTER)mdlMap->vmaAddr,
++ mdl->numPages * PAGE_SIZE
++ ));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X *PageCount=%lu", *Logical, *PageCount);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPages
++**
++** Map paged memory into a page table.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T PageCount
++** Number of pages required for the physical address.
++**
++** gctPOINTER PageTable
++** Pointer to the page table to fill in.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ )
++{
++ return gckOS_MapPagesEx(Os,
++ gcvCORE_MAJOR,
++ Physical,
++ PageCount,
++ 0,
++ PageTable);
++}
++
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address,
++ IN gctPOINTER PageTable
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ PLINUX_MDL mdl;
++ gctUINT32* table;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gckMMU mmu;
++ PLINUX_MDL mmuMdl;
++ gctUINT32 bytes;
++ gctPHYS_ADDR pageTablePhysical;
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckKERNEL kernel = Os->device->kernels[Core];
++ gckMMU mmu;
++#endif
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Physical=0x%X PageCount=%u PageTable=0x%X",
++ Os, Core, Physical, PageCount, PageTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ /* Convert pointer to MDL. */
++ mdl = (PLINUX_MDL)Physical;
++
++ allocator = mdl->allocator;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Physical->0x%X PageCount->0x%X PagedMemory->?%d",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)Physical,
++ (gctUINT32)(gctUINTPTR_T)PageCount,
++ mdl->pagedMem
++ );
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(kernel, &mmu));
++#endif
++
++ table = (gctUINT32 *)PageTable;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ mmu = Os->device->kernels[Core]->mmu;
++ bytes = PageCount * sizeof(*table);
++ mmuMdl = (PLINUX_MDL)mmu->pageTablePhysical;
++#endif
++
++ /* Get all the physical addresses and store them in the page table. */
++
++ offset = 0;
++ PageCount = PageCount / (PAGE_SIZE / 4096);
++
++ /* Try to get the user pages so DMA can happen. */
++ while (PageCount-- > 0)
++ {
++ gctUINT i;
++ gctUINT32 phys = ~0;
++
++ if (mdl->pagedMem && !mdl->contiguous)
++ {
++ allocator->ops->Physical(allocator, mdl, offset, &phys);
++ }
++ else
++ {
++ if (!mdl->pagedMem)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): we should not get this call for Non Paged Memory!",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ phys = page_to_phys(nth_page(mdl->u.contiguousPages, offset));
++ }
++
++ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(Os, phys, &phys));
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Setup mapping in IOMMU %x => %x",
++ __FUNCTION__, __LINE__,
++ Address + (offset * PAGE_SIZE), phys
++ );
++
++ /* When use IOMMU, GPU use system PAGE_SIZE. */
++ gcmkONERROR(gckIOMMU_Map(
++ Os->iommu, Address + (offset * PAGE_SIZE), phys, PAGE_SIZE));
++ }
++ else
++#endif
++ {
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ for (i = 0; i < (PAGE_SIZE / 4096); i++)
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ phys + (i * 4096),
++ table++));
++ }
++ }
++ else
++#endif
++ {
++ for (i = 0; i < (PAGE_SIZE / 4096); i++)
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ gctUINT32_PTR pageTableEntry;
++ gckMMU_GetPageEntry(mmu, Address + (offset * 4096), &pageTableEntry);
++ gcmkONERROR(
++ gckMMU_SetPage(mmu,
++ phys + (i * 4096),
++ pageTableEntry));
++#else
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ phys + (i * 4096),
++ table++));
++#endif
++ }
++ }
++ }
++
++ offset += 1;
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Get physical address of pageTable */
++ pageTablePhysical = (gctPHYS_ADDR)(mmuMdl->dmaHandle +
++ ((gctUINT32 *)PageTable - mmu->pageTableLogical));
++
++ /* Flush the mmu page table cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Os,
++ _GetProcessID(),
++ gcvNULL,
++ pageTablePhysical,
++ PageTable,
++ bytes
++ ));
++#endif
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_UnmapPages(
++ IN gckOS Os,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address
++ )
++{
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gcmkVERIFY_OK(gckIOMMU_Unmap(
++ Os->iommu, Address, PageCount * PAGE_SIZE));
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnlockPages
++**
++** Unlock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctPOINTER Logical
++** Address of the mapped memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if ((mdlMap->vmaAddr != gcvNULL) && (_GetProcessID() == mdlMap->pid))
++ {
++ if (--mdlMap->count == 0)
++ {
++ allocator->ops->UnmapUser(
++ allocator,
++ mdlMap->vmaAddr,
++ mdl->numPages * PAGE_SIZE);
++
++ mdlMap->vmaAddr = gcvNULL;
++ }
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_AllocateContiguous
++**
++** Allocate memory from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that receives the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the logical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Same as non-paged memory for now. */
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(Os,
++ InUserSpace,
++ Bytes,
++ Physical,
++ Logical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeContiguous
++**
++** Free memory allocated from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctPOINTER Logical
++** Logicval address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu",
++ Os, Physical, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Same of non-paged memory for now. */
++ gcmkONERROR(gckOS_FreeNonPagedMemory(Os, Bytes, Physical, Logical));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++/******************************************************************************
++**
++** gckOS_GetKernelLogical
++**
++** Return the kernel logical pointer that corresponods to the specified
++** hardware address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Hardware physical address.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the pointer in kernel address space.
++*/
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ return gckOS_GetKernelLogicalEx(Os, gcvCORE_MAJOR, Address, KernelPointer);
++}
++
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%08x", Os, Core, Address);
++
++ do
++ {
++ gckGALDEVICE device;
++ gckKERNEL kernel;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctPOINTER logical;
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Os->device;
++
++ /* Kernel shortcut. */
++ kernel = device->kernels[Core];
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_SplitMemory(
++ kernel->vg->hardware, Address, &pool, &offset
++ ));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkERR_BREAK(gckHARDWARE_SplitMemory(
++ kernel->hardware, Address, &pool, &offset
++ ));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ logical = device->contiguousBase;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkFOOTER();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Build logical address of specified address. */
++ * KernelPointer = ((gctUINT8_PTR) logical) + offset;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_MapUserPointer
++**
++** Map a pointer from the user process into the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be mapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be mapped.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the mapped pointer in kernel address
++** space.
++*/
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER buf = gcvNULL;
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu", Os, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ buf = kmalloc(Size, GFP_KERNEL | gcdNOWARN);
++ if (buf == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to allocate memory.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ len = copy_from_user(buf, Pointer, Size);
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data from user.",
++ __FUNCTION__, __LINE__
++ );
++
++ if (buf != gcvNULL)
++ {
++ kfree(buf);
++ }
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ *KernelPointer = buf;
++
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserPointer
++**
++** Unmap a user process pointer from the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be unmapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be unmapped.
++**
++** gctPOINTER KernelPointer
++** Pointer in kernel address space that needs to be unmapped.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ )
++{
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu KernelPointer=0x%X",
++ Os, Pointer, Size, KernelPointer);
++
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ len = copy_to_user(Pointer, KernelPointer, Size);
++
++ kfree(KernelPointer);
++
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data to user.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d", Os, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(NeedCopy != gcvNULL);
++
++ /* We need to copy data. */
++ *NeedCopy = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedCopy=%d", *NeedCopy);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data from user. */
++ if (copy_from_user(KernelPointer, Pointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data to user. */
++ if (copy_to_user(Pointer, KernelPointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WriteMemory
++**
++** Write data to a memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of the memory to write to.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X Data=%u", Os, Address, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Write memory. */
++ if (access_ok(VERIFY_WRITE, Address, 4))
++ {
++ /* User address. */
++ if(put_user(Data, (gctUINT32*)Address))
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS);
++ }
++ }
++ else
++ {
++ /* Kernel address. */
++ *(gctUINT32 *)Address = Data;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapUserMemory
++**
++** Lock down a user buffer and return an DMA'able address to be used by the
++** hardware to access it.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to lock down.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to lock down.
++**
++** OUTPUT:
++**
++** gctPOINTER * Info
++** Pointer to variable receiving the information record required by
++** gckOS_UnmapUserMemory.
++**
++** gctUINT32_PTR Address
++** Pointer to a variable that will receive the address DMA'able by the
++** hardware.
++*/
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T pageCount, i, j;
++ gctUINT32_PTR pageTable;
++ gctUINT32 address = 0, physical = ~0U;
++ gctUINTPTR_T start, end, memory;
++ gctUINT32 offset;
++ gctINT result = 0;
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++
++ gcsPageInfo_PTR info = gcvNULL;
++ struct page **pages = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Core=%d Memory=0x%x Size=%lu", Os, Core, Memory, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL || Physical != ~0U);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ gctSIZE_T extraPage;
++
++ memory = (gctUINTPTR_T) Memory;
++
++ /* Get the number of required pages. */
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ /* Allocate extra 64 bytes to avoid cache overflow */
++ extraPage = (((memory + gcmALIGN(Size + 64, 64) + PAGE_SIZE - 1) >> PAGE_SHIFT) > end) ? 1 : 0;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageCount: %d.",
++ __FUNCTION__, __LINE__,
++ pageCount
++ );
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ MEMORY_MAP_LOCK(Os);
++
++ /* Allocate the Info struct. */
++ info = (gcsPageInfo_PTR)kmalloc(sizeof(gcsPageInfo), GFP_KERNEL | gcdNOWARN);
++
++ if (info == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ info->extraPage = 0;
++
++ /* Allocate the array of page addresses. */
++ pages = (struct page **)kmalloc((pageCount + extraPage) * sizeof(struct page *), GFP_KERNEL | gcdNOWARN);
++
++ if (pages == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ if (Physical != ~0U)
++ {
++ unsigned long pfn = Physical >> PAGE_SHIFT;
++ for (i = 0; i < pageCount; i++)
++ {
++ if (!pfn_valid(pfn + i))
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ }
++
++ for (i = 0; i < pageCount; i++)
++ {
++ pages[i] = pfn_to_page(pfn + i);
++ get_page(pages[i]);
++ }
++ }
++ else
++ {
++ /* Get the user pages. */
++ down_read(&current->mm->mmap_sem);
++
++ result = get_user_pages(current,
++ current->mm,
++ memory & PAGE_MASK,
++ pageCount,
++ 1,
++ 0,
++ pages,
++ gcvNULL
++ );
++
++ up_read(&current->mm->mmap_sem);
++
++ if (result <=0 || result < pageCount)
++ {
++ struct vm_area_struct *vma;
++
++ /* Release the pages if any. */
++ if (result > 0)
++ {
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] != gcvNULL)
++ {
++ page_cache_release(pages[i]);
++ pages[i] = gcvNULL;
++ }
++ }
++
++ result = 0;
++ }
++
++ vma = find_vma(current->mm, memory);
++
++ if (vma && (vma->vm_flags & VM_PFNMAP))
++ {
++ pte_t * pte;
++ spinlock_t * ptl;
++ gctUINTPTR_T logical = memory;
++
++ for (i = 0; i < pageCount; i++)
++ {
++ pgd_t * pgd = pgd_offset(current->mm, logical);
++ pud_t * pud = pud_offset(pgd, logical);
++ unsigned long pfn;
++
++ if (pud)
++ {
++ pmd_t * pmd = pmd_offset(pud, logical);
++ pte = pte_offset_map_lock(current->mm, pmd, logical, &ptl);
++ if (!pte)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ if (pte_present(*pte))
++ pfn = pte_pfn(*pte);
++ else
++ pfn = ~0UL;
++ pte_unmap_unlock(pte, ptl);
++
++ if (pfn == ~0UL || !pfn_valid(pfn))
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++
++ pages[i] = pfn_to_page(pfn);
++
++ /* Advance to next. */
++ logical += PAGE_SIZE;
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Check if this memory is contiguous for old mmu. */
++ if (Os->device->kernels[Core]->hardware->mmuVersion == 0)
++ {
++ for (i = 1; i < pageCount; i++)
++ {
++ if (pages[i] != nth_page(pages[0], i))
++ {
++ /* Non-contiguous. */
++ break;
++ }
++ }
++
++ if (i == pageCount)
++ {
++ /* Contiguous memory. */
++ physical = page_to_phys(pages[0]) | (memory & ~PAGE_MASK);
++
++ if (!((physical - Os->device->baseAddress) & 0x80000000))
++ {
++ kfree(pages);
++ pages = gcvNULL;
++
++ info->pages = gcvNULL;
++ info->pageTable = gcvNULL;
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ *Address = physical - Os->device->baseAddress;
++ *Info = info;
++
++ gcmkVERIFY_OK(
++ gckOS_CPUPhysicalToGPUPhysical(Os, *Address, Address));
++
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x",
++ *Info, *Address);
++
++ return gcvSTATUS_OK;
++ }
++ }
++ }
++
++ /* Reference pages. */
++ for (i = 0; i < pageCount; i++)
++ {
++ if (pfn_valid(page_to_pfn(pages[i])))
++ {
++ get_page(pages[i]);
++ }
++ }
++ }
++ }
++
++ for (i = 0; i < pageCount; i++)
++ {
++#ifdef CONFIG_ARM
++ gctUINT32 data;
++ get_user(data, (gctUINT32*)((memory & PAGE_MASK) + i * PAGE_SIZE));
++#endif
++
++ /* Flush(clean) the data cache. */
++ gcmkONERROR(gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
++ page_to_phys(pages[i]),
++ (gctPOINTER)(memory & PAGE_MASK) + i*PAGE_SIZE,
++ PAGE_SIZE));
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Os->device->kernels[Core], &mmu));
++#endif
++
++ if (extraPage)
++ {
++ pages[pageCount++] = Os->paddingPage;
++ info->extraPage = 1;
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckVGMMU_AllocatePages(Os->device->kernels[Core]->vg->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++ }
++ else
++#endif
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckMMU_AllocatePages(mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++#else
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckMMU_AllocatePages(Os->device->kernels[Core]->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++#endif
++ }
++
++ /* Fill the page table. */
++ for (i = 0; i < pageCount; i++)
++ {
++ gctUINT32 phys;
++ gctUINT32_PTR tab = pageTable + i * (PAGE_SIZE/4096);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU_GetPageEntry(mmu, address + i * 4096, &tab);
++#endif
++ phys = page_to_phys(pages[i]);
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Setup mapping in IOMMU %x => %x",
++ __FUNCTION__, __LINE__,
++ Address + (i * PAGE_SIZE), phys
++ );
++
++ gcmkONERROR(gckIOMMU_Map(
++ Os->iommu, address + i * PAGE_SIZE, phys, PAGE_SIZE));
++ }
++ else
++#endif
++ {
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkVERIFY_OK(
++ gckOS_CPUPhysicalToGPUPhysical(Os, phys, &phys));
++
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ phys,
++ tab));
++ }
++ else
++#endif
++ {
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ phys,
++ tab));
++ }
++
++ for (j = 1; j < (PAGE_SIZE/4096); j++)
++ {
++ pageTable[i * (PAGE_SIZE/4096) + j] = pageTable[i * (PAGE_SIZE/4096)] + 4096 * j;
++ }
++ }
++
++#if !gcdPROCESS_ADDRESS_SPACE
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageTable[%d]: 0x%X 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, phys, pageTable[i]);
++#endif
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Os->device->kernels[Core]->vg->mmu));
++ }
++ else
++#endif
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ info->mmu = mmu;
++ gcmkONERROR(gckMMU_Flush(mmu));
++#else
++ gcmkONERROR(gckMMU_Flush(Os->device->kernels[Core]->mmu, gcvSURF_TYPE_UNKNOWN));
++#endif
++ }
++ info->address = address;
++
++ /* Save pointer to page table. */
++ info->pageTable = pageTable;
++ info->pages = pages;
++
++ *Info = (gctPOINTER) info;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info->pages: 0x%X, info->pageTable: 0x%X, info: 0x%X.",
++ __FUNCTION__, __LINE__,
++ info->pages,
++ info->pageTable,
++ info
++ );
++
++ offset = (Physical != ~0U)
++ ? (Physical & ~PAGE_MASK)
++ : (memory & ~PAGE_MASK);
++
++ /* Return address. */
++ *Address = address + offset;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Address: 0x%X.",
++ __FUNCTION__, __LINE__,
++ *Address
++ );
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++OnError:
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error occured: %d.",
++ __FUNCTION__, __LINE__,
++ status
++ );
++
++ /* Release page array. */
++ if (result > 0 && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: page table is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] == gcvNULL)
++ {
++ break;
++ }
++ page_cache_release(pages[i]);
++ }
++ }
++
++ if (info!= gcvNULL && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: pages is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page table. */
++ kfree(pages);
++ info->pages = gcvNULL;
++ }
++
++ /* Release page info struct. */
++ if (info != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: info is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page info struct. */
++ kfree(info);
++ *Info = gcvNULL;
++ }
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x", *Info, *Address);
++ }
++ else
++ {
++ gcmkFOOTER();
++ }
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserMemory
++**
++** Unlock a user buffer and that was previously locked down by
++** gckOS_MapUserMemory.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to unlock.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to unlock.
++**
++** gctPOINTER Info
++** Information record returned by gckOS_MapUserMemory.
++**
++** gctUINT32_PTR Address
++** The address returned by gckOS_MapUserMemory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ )
++{
++ gceSTATUS status;
++ gctUINTPTR_T memory, start, end;
++ gcsPageInfo_PTR info;
++ gctSIZE_T pageCount, i;
++ struct page **pages;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Memory=0x%X Size=%lu Info=0x%X Address0x%08x",
++ Os, Core, Memory, Size, Info, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ do
++ {
++ info = (gcsPageInfo_PTR) Info;
++
++ pages = info->pages;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info=0x%X, pages=0x%X.",
++ __FUNCTION__, __LINE__,
++ info, pages
++ );
++
++ /* Invalid page array. */
++ if (pages == gcvNULL && info->pageTable == gcvNULL)
++ {
++ kfree(info);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ memory = (gctUINTPTR_T)Memory;
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): memory: 0x%X, pageCount: %d, pageTable: 0x%X.",
++ __FUNCTION__, __LINE__,
++ memory, pageCount, info->pageTable
++ );
++
++ MEMORY_MAP_LOCK(Os);
++
++ gcmkASSERT(info->pageTable != gcvNULL);
++
++ if (info->extraPage)
++ {
++ pageCount += 1;
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Free the pages from the MMU. */
++ gcmkERR_BREAK(gckVGMMU_FreePages(Os->device->kernels[Core]->vg->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkERR_BREAK(gckMMU_FreePagesEx(info->mmu,
++ info->address,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++
++#else
++ gcmkERR_BREAK(gckMMU_FreePages(Os->device->kernels[Core]->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++#endif
++
++ gcmkERR_BREAK(gckOS_UnmapPages(
++ Os,
++ pageCount * (PAGE_SIZE/4096),
++ info->address
++ ));
++ }
++
++ if (info->extraPage)
++ {
++ pageCount -= 1;
++ info->extraPage = 0;
++ }
++
++ /* Release the page cache. */
++ if (pages)
++ {
++ for (i = 0; i < pageCount; i++)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pages[%d]: 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, pages[i]
++ );
++
++ if (!PageReserved(pages[i]))
++ {
++ SetPageDirty(pages[i]);
++ }
++
++ if (pfn_valid(page_to_pfn(pages[i])))
++ {
++ page_cache_release(pages[i]);
++ }
++ }
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ if (info != gcvNULL)
++ {
++ /* Free the page array. */
++ if (info->pages != gcvNULL)
++ {
++ kfree(info->pages);
++ }
++
++ kfree(info);
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetBaseAddress
++**
++** Get the base address for the physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR BaseAddress
++** Pointer to a variable that will receive the base address.
++*/
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Return base address. */
++ *BaseAddress = Os->device->baseAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_SuspendInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ disable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_ResumeInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ enable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Destination=0x%X Source=0x%X Bytes=%lu",
++ Destination, Source, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Destination != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Source != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memcpy(Destination, Source, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X Bytes=%lu", Memory, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memset(Memory, 0, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Cache Control ********************************
++*******************************************************************************/
++
++/*******************************************************************************
++** gckOS_CacheClean
++**
++** Clean the cache for the specified addresses. The GPU is going to need the
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Physical
++** Physical address to flush.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheClean(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->cache)
++ {
++ platform->ops->cache(
++ platform,
++ ProcessID,
++ Handle,
++ Physical,
++ Logical,
++ Bytes,
++ gcvCACHE_CLEAN
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ dma_sync_single_for_device(
++ Os->device->dev,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_TO_DEVICE);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheInvalidate
++**
++** Invalidate the cache for the specified addresses. The GPU is going to need
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheInvalidate(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->cache)
++ {
++ platform->ops->cache(
++ platform,
++ ProcessID,
++ Handle,
++ Physical,
++ Logical,
++ Bytes,
++ gcvCACHE_INVALIDATE
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ dma_sync_single_for_device(
++ Os->device->dev,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_FROM_DEVICE);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheFlush
++**
++** Clean the cache for the specified addresses and invalidate the lines as
++** well. The GPU is going to need and modify the data. If the system is
++** allocating memory as non-cachable, this function can be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheFlush(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->cache)
++ {
++ platform->ops->cache(
++ platform,
++ ProcessID,
++ Handle,
++ Physical,
++ Logical,
++ Bytes,
++ gcvCACHE_FLUSH
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ if (Physical != gcvINVALID_ADDRESS)
++ {
++ dma_sync_single_for_device(
++ Os->device->dev,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_BIDIRECTIONAL);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Broadcasting *********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Broadcast
++**
++** System hook for broadcast events from the kernel driver.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gceBROADCAST Reason
++** Reason for the broadcast. Can be one of the following values:
++**
++** gcvBROADCAST_GPU_IDLE
++** Broadcasted when the kernel driver thinks the GPU might be
++** idle. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_COMMIT
++** Broadcasted when any client process commits a command
++** buffer. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_STUCK
++** Broadcasted when the kernel driver hits the timeout waiting
++** for the GPU.
++**
++** gcvBROADCAST_FIRST_PROCESS
++** First process is trying to connect to the kernel.
++**
++** gcvBROADCAST_LAST_PROCESS
++** Last process has detached from the kernel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Hardware=0x%X Reason=%d", Os, Hardware, Reason);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ switch (Reason)
++ {
++ case gcvBROADCAST_FIRST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "First process has attached");
++ break;
++
++ case gcvBROADCAST_LAST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "Last process has detached");
++
++ /* Put GPU OFF. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++ gcvPOWER_OFF_BROADCAST));
++ break;
++
++ case gcvBROADCAST_GPU_IDLE:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "GPU idle.");
++
++ /* Put GPU IDLE. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++#if gcdPOWER_SUSPEND_WHEN_IDLE
++ gcvPOWER_SUSPEND_BROADCAST));
++#else
++ gcvPOWER_IDLE_BROADCAST));
++#endif
++
++ /* Add idle process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 1,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++ break;
++
++ case gcvBROADCAST_GPU_COMMIT:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "COMMIT has arrived.");
++
++ /* Add busy process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 0,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++
++ /* Put GPU ON. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware, gcvPOWER_ON_AUTO));
++ break;
++
++ case gcvBROADCAST_GPU_STUCK:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_GPU_STUCK\n");
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++
++ case gcvBROADCAST_AXI_BUS_ERROR:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_AXI_BUS_ERROR\n");
++ gcmkONERROR(gckHARDWARE_DumpGPUState(Hardware));
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++
++ case gcvBROADCAST_OUT_OF_MEMORY:
++ gcmkTRACE_N(gcvLEVEL_INFO, 0, "gcvBROADCAST_OUT_OF_MEMORY\n");
++
++ status = _ShrinkMemory(Os);
++
++ if (status == gcvSTATUS_NOT_SUPPORTED)
++ {
++ goto OnError;
++ }
++
++ gcmkONERROR(status);
++
++ break;
++
++ default:
++ /* Skip unimplemented broadcast. */
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastHurry
++**
++** The GPU is running too slow.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Urgency
++** The higher the number, the higher the urgency to speed up the GPU.
++** The maximum value is defined by the gcdDYNAMIC_EVENT_THRESHOLD.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Urgency=%u", Os, Hardware, Urgency);
++
++ /* Do whatever you need to do to speed up the GPU now. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastCalibrateSpeed
++**
++** Calibrate the speed of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Idle, Time
++** Idle/Time will give the percentage the GPU is idle, so you can use
++** this to calibrate the working point of the GPU.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Idle=%u Time=%u",
++ Os, Hardware, Idle, Time);
++
++ /* Do whatever you need to do to callibrate the GPU speed. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************** Semaphores **********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_CreateSemaphore
++**
++** Create a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Semaphore
++** Pointer to the variable that will receive the created semaphore.
++*/
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore *sem = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Allocate the semaphore structure. */
++ sem = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (sem == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(sem, 1);
++
++ /* Return to caller. */
++ *Semaphore = (gctPOINTER) sem;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireSemaphore
++**
++** Acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%08X Semaphore=0x%08X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_interruptible((struct semaphore *) Semaphore))
++ {
++ gcmkONWARNING(gcvSTATUS_INTERRUPTED);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_TryAcquireSemaphore
++**
++** Try to acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_trylock((struct semaphore *) Semaphore))
++ {
++ /* Timeout. */
++ status = gcvSTATUS_TIMEOUT;
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseSemaphore
++**
++** Release a previously acquired semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Release the semaphore. */
++ up((struct semaphore *) Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySemaphore
++**
++** Destroy a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Free the sempahore structure. */
++ kfree(Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ )
++{
++ /* Get process ID. */
++ if (ProcessID != gcvNULL)
++ {
++ *ProcessID = _GetProcessID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ )
++{
++ /* Get thread ID. */
++ if (ThreadID != gcvNULL)
++ {
++ *ThreadID = _GetThreadID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gceCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ )
++{
++ gcsPLATFORM * platform;
++
++ gctBOOL powerChange = gcvFALSE;
++ gctBOOL clockChange = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Clock=%d Power=%d", Os, Core, Clock, Power);
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ platform = Os->device->platform;
++
++ powerChange = (Power != Os->powerStates[Core]);
++
++ clockChange = (Clock != Os->clockStates[Core]);
++
++ if (powerChange && (Power == gcvTRUE))
++ {
++ if (platform && platform->ops->setPower)
++ {
++ gcmkVERIFY_OK(platform->ops->setPower(platform, Core, Power));
++ }
++
++ Os->powerStates[Core] = Power;
++ }
++
++ if (clockChange)
++ {
++ mutex_lock(&Os->registerAccessLocks[Core]);
++
++ if (platform && platform->ops->setClock)
++ {
++ gcmkVERIFY_OK(platform->ops->setClock(platform, Core, Clock));
++ }
++
++ Os->clockStates[Core] = Clock;
++
++ mutex_unlock(&Os->registerAccessLocks[Core]);
++ }
++
++ if (powerChange && (Power == gcvFALSE))
++ {
++ if (platform && platform->ops->setPower)
++ {
++ gcmkVERIFY_OK(platform->ops->setPower(platform, Core, Power));
++ }
++
++ Os->powerStates[Core] = Power;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ResetGPU
++**
++** Reset the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED;
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->reset)
++ {
++ status = platform->ops->reset(platform, Core);
++ }
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_PrepareGPUFrequency
++**
++** Prepare to set GPU frequency and voltage.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage will be set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_FinishGPUFrequency
++**
++** Finish GPU frequency setting.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryGPUFrequency
++**
++** Query the current frequency of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT32 * Frequency
++** Pointer to a gctUINT32 to obtain current frequency, in MHz.
++**
++** gctUINT8 * Scale
++** Pointer to a gctUINT8 to obtain current scale(1 - 64).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUFrequency
++**
++** Set frequency and voltage of the GPU.
++**
++** 1. DVFS manager gives the target scale of full frequency, BSP must find
++** a real frequency according to this scale and board's configure.
++**
++** 2. BSP should find a suitable voltage for this frequency.
++**
++** 3. BSP must make sure setting take effect before this function returns.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT8 Scale
++** Target scale of full frequency, range is [1, 64]. 1 means 1/64 of
++** full frequency and 64 means 64/64 of full frequency.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ )
++{
++ struct timespec time;
++
++ ktime_get_ts(&time);
++
++ *Tick = time.tv_nsec + time.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ )
++{
++ struct timespec res;
++
++ hrtimer_get_res(CLOCK_MONOTONIC, &res);
++
++ *TickRate = res.tv_nsec + res.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ )
++{
++ return div_u64(Ticks, 1000000);
++}
++
++/******************************************************************************\
++******************************* Signal Management ******************************
++\******************************************************************************/
++
++#undef _GC_OBJ_ZONE
++#define _GC_OBJ_ZONE gcvZONE_SIGNAL
++
++/*******************************************************************************
++**
++** gckOS_CreateSignal
++**
++** Create a new signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctSIGNAL * Signal
++** Pointer to a variable receiving the created gctSIGNAL.
++*/
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X ManualReset=%d", Os, ManualReset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Create an event structure. */
++ signal = (gcsSIGNAL_PTR) kmalloc(sizeof(gcsSIGNAL), GFP_KERNEL | gcdNOWARN);
++
++ if (signal == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Save the process ID. */
++ signal->process = (gctHANDLE)(gctUINTPTR_T) _GetProcessID();
++ signal->manualReset = ManualReset;
++ signal->hardware = gcvNULL;
++ init_completion(&signal->obj);
++ atomic_set(&signal->ref, 1);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->signalDB, signal, &signal->id));
++
++ *Signal = (gctSIGNAL)(gctUINTPTR_T)signal->id;
++
++ gcmkFOOTER_ARG("*Signal=0x%X", *Signal);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ kfree(signal);
++ }
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ *Hardware = signal->hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ signal->hardware = Hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySignal
++**
++** Destroy a signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++static gceSTATUS
++gckOS_DestroySignalEx(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X", Os, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (atomic_dec_and_test(&signal->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->signalDB, signal->id));
++
++ /* Free the sgianl. */
++ kfree(signal);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X", Os, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(gckOS_DestroySignalEx(Os, Signal));
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Signal
++**
++** Set a state of the specified signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++static gceSTATUS
++gckOS_SignalEx(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X State=%d", Os, Signal, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (State)
++ {
++ /* unbind the signal from hardware. */
++ signal->hardware = gcvNULL;
++
++ /* Set the event to a signaled state. */
++ complete(&signal->obj);
++ }
++ else
++ {
++ /* Set the event to an unsignaled state. */
++ reinit_completion(&signal->obj);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X State=%d", Os, Signal, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(gckOS_SignalEx(Os, Signal, State));
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_SetSignalVG(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ printk("gckOS_SetSignalVG:0x%x\n", result);
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_UserSignal
++**
++** Set the specified signal which is owned by a process to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ )
++{
++ gceSTATUS status;
++ gctSIGNAL signal;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL user = (Process != gcvNULL);
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=%d",
++ Os, Signal, (gctINT32)(gctUINTPTR_T)Process);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (user)
++ {
++ /* Map the signal into kernel space. */
++ gcmkONERROR(gckOS_MapSignal(Os, Signal, Process, &signal));
++
++ /* Signal. */
++ gcmkONERROR(gckOS_SignalEx(Os, signal, gcvTRUE));
++
++ /* Unmap the signal */
++ gcmkVERIFY_OK(gckOS_UnmapSignal(Os, Signal));
++ } else {
++ /* Signal. */
++ gcmkONERROR(gckOS_SignalEx(Os, Signal, gcvTRUE));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER();
++ return status;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitSignal
++**
++** Wait for a signal to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Wait=0x%08X", Os, Signal, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ might_sleep();
++
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ else if (Wait == 0)
++ {
++ status = gcvSTATUS_TIMEOUT;
++ }
++ else
++ {
++ /* Convert wait to milliseconds. */
++ long timeout = (Wait == gcvINFINITE)
++ ? MAX_SCHEDULE_TIMEOUT
++ : Wait * HZ / 1000;
++
++ DECLARE_WAITQUEUE(wait, current);
++ wait.flags |= WQ_FLAG_EXCLUSIVE;
++ __add_wait_queue_tail(&signal->obj.wait, &wait);
++
++ while (gcvTRUE)
++ {
++ if (signal_pending(current))
++ {
++ /* Interrupt received. */
++ status = gcvSTATUS_INTERRUPTED;
++ break;
++ }
++
++ __set_current_state(TASK_INTERRUPTIBLE);
++ spin_unlock_irq(&signal->obj.wait.lock);
++ timeout = schedule_timeout(timeout);
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ if (timeout == 0)
++ {
++
++ status = gcvSTATUS_TIMEOUT;
++ break;
++ }
++ }
++
++ __remove_wait_queue(&signal->obj.wait, &wait);
++ }
++
++ spin_unlock_irq(&signal->obj.wait.lock);
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER_ARG("Signal=0x%X status=%d", Signal, status);
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapSignal
++**
++** Map a signal in to the current process space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to tha gctSIGNAL to map.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** gctSIGNAL * MappedSignal
++** Pointer to a variable receiving the mapped gctSIGNAL.
++*/
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=0x%X", Os, Signal, Process);
++
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(MappedSignal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ if(atomic_inc_return(&signal->ref) <= 1)
++ {
++ /* The previous value is 0, it has been deleted. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ *MappedSignal = (gctSIGNAL) Signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*MappedSignal=0x%X", *MappedSignal);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapSignal
++**
++** Unmap a signal .
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to that gctSIGNAL mapped.
++*/
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ return gckOS_DestroySignalEx(Os, Signal);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateUserSignal
++**
++** Create a new signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctINT * SignalID
++** Pointer to a variable receiving the created signal's ID.
++*/
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T signal;
++
++ /* Create a new signal. */
++ gcmkONERROR(gckOS_CreateSignal(Os, ManualReset, (gctSIGNAL *) &signal));
++ *SignalID = (gctINT) signal;
++
++OnError:
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyUserSignal
++**
++** Destroy a signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** The signal's ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ )
++{
++ return gckOS_DestroySignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID);
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitUserSignal
++**
++** Wait for a signal used in the user mode to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** Signal ID.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ )
++{
++ return gckOS_WaitSignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, Wait);
++}
++
++/*******************************************************************************
++**
++** gckOS_SignalUserSignal
++**
++** Set a state of the specified signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** SignalID.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ )
++{
++ return gckOS_Signal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, State);
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctSEMAPHORE * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore * newSemaphore;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Allocate the semaphore structure. */
++ newSemaphore = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (newSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(newSemaphore, 0);
++
++ /* Set the handle. */
++ * Semaphore = (gctSEMAPHORE) newSemaphore;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Increment the semaphore's count. */
++ up((struct semaphore *) Semaphore);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Decrement the semaphore's count. If the count is zero, wait
++ until it gets incremented. */
++ result = down_interruptible((struct semaphore *) Semaphore);
++
++ /* Signal received? */
++ if (result != 0)
++ {
++ status = gcvSTATUS_TERMINATE;
++ break;
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetSignal
++**
++** Set the specified signal to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++******************************** Thread Object *********************************
++\******************************************************************************/
++
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ )
++{
++ gceSTATUS status;
++ struct task_struct * thread;
++
++ gcmkHEADER_ARG("Os=0x%X ", Os);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(ThreadFunction != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ do
++ {
++ /* Create the thread. */
++ thread = kthread_create(
++ ThreadFunction,
++ ThreadParameter,
++ "Vivante Kernel Thread"
++ );
++
++ /* Failed? */
++ if (IS_ERR(thread))
++ {
++ status = gcvSTATUS_GENERIC_IO;
++ break;
++ }
++
++ /* Start the thread. */
++ wake_up_process(thread);
++
++ /* Set the thread handle. */
++ * Thread = (gctTHREAD) thread;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ /* Thread should have already been enabled to terminate. */
++ kthread_stop((struct task_struct *) Thread);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++/******************************************************************************\
++******************************** Software Timer ********************************
++\******************************************************************************/
++
++void
++_TimerFunction(
++ struct work_struct * work
++ )
++{
++ gcsOSTIMER_PTR timer = (gcsOSTIMER_PTR)work;
++
++ gctTIMERFUNCTION function = timer->function;
++
++ function(timer->data);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateTimer
++**
++** Create a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctTIMERFUNCTION Function.
++** Pointer to a call back function which will be called when timer is
++** expired.
++**
++** gctPOINTER Data.
++** Private data which will be passed to call back function.
++**
++** OUTPUT:
++**
++** gctPOINTER * Timer
++** Pointer to a variable receiving the created timer.
++*/
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ )
++{
++ gceSTATUS status;
++ gcsOSTIMER_PTR pointer;
++ gcmkHEADER_ARG("Os=0x%X Function=0x%X Data=0x%X", Os, Function, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(Os, sizeof(gcsOSTIMER), (gctPOINTER)&pointer));
++
++ pointer->function = Function;
++ pointer->data = Data;
++
++ INIT_DELAYED_WORK(&pointer->work, _TimerFunction);
++
++ *Timer = pointer;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyTimer
++**
++** Destory a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be destoryed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ cancel_delayed_work_sync(&timer->work);
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, Timer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StartTimer
++**
++** Schedule a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be scheduled.
++**
++** gctUINT32 Delay
++** Delay in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ )
++{
++ gcsOSTIMER_PTR timer;
++
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X Delay=%u", Os, Timer, Delay);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Delay != 0);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ mod_delayed_work(Os->workqueue, &timer->work, msecs_to_jiffies(Delay));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StopTimer
++**
++** Cancel a unscheduled timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be cancel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ cancel_delayed_work(&timer->work);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ )
++{
++ struct task_struct *task;
++
++ /* Get the task_struct of the task with pid. */
++ rcu_read_lock();
++
++ task = FIND_TASK_BY_PID(Pid);
++
++ if (task == gcvNULL)
++ {
++ rcu_read_unlock();
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ /* Get name of process. */
++ strncpy(String, task->comm, Length);
++
++ rcu_read_unlock();
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ dump_stack();
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_DetectProcessByName
++**
++** task->comm maybe part of process name, so this function
++** can only be used for debugging.
++**
++** INPUT:
++**
++** gctCONST_POINTER Name
++** Pointer to a string to hold name to be check. If the length
++** of name is longer than TASK_COMM_LEN (16), use part of name
++** to detect.
++**
++** OUTPUT:
++**
++** gcvSTATUS_TRUE if name of current process matches Name.
++**
++*/
++gceSTATUS
++gckOS_DetectProcessByName(
++ IN gctCONST_POINTER Name
++ )
++{
++ char comm[sizeof(current->comm)];
++
++ memset(comm, 0, sizeof(comm));
++
++ gcmkVERIFY_OK(
++ gckOS_GetProcessNameByPid(_GetProcessID(), sizeof(current->comm), comm));
++
++ return strstr(comm, Name) ? gcvSTATUS_TRUE
++ : gcvSTATUS_FALSE;
++}
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Create an sync point structure. */
++ syncPoint = (gcsSYNC_POINT_PTR) kmalloc(
++ sizeof(gcsSYNC_POINT), GFP_KERNEL | gcdNOWARN);
++
++ if (syncPoint == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the sync point. */
++ atomic_set(&syncPoint->ref, 1);
++ atomic_set(&syncPoint->state, 0);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->syncPointDB, syncPoint, &syncPoint->id));
++
++ *SyncPoint = (gctSYNC_POINT)(gctUINTPTR_T)syncPoint->id;
++
++ gcmkFOOTER_ARG("*SyncPonint=%d", syncPoint->id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (syncPoint != gcvNULL)
++ {
++ kfree(syncPoint);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Initialize the sync point. */
++ atomic_inc(&syncPoint->ref);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ if (atomic_dec_and_test(&syncPoint->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->syncPointDB, syncPoint->id));
++
++ /* Free the sgianl. */
++ syncPoint->timeline = gcvNULL;
++ kfree(syncPoint);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ struct sync_timeline * timeline;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Set signaled state. */
++ atomic_set(&syncPoint->state, 1);
++
++ /* Get parent timeline. */
++ timeline = syncPoint->timeline;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Signal timeline. */
++ if (timeline)
++ {
++ sync_timeline_signal(timeline);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Get state. */
++ *State = atomic_read(&syncPoint->state);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++
++ /* Create viv sync timeline. */
++ timeline = viv_sync_timeline_create("viv timeline", Os);
++
++ if (timeline == gcvNULL)
++ {
++ /* Out of memory. */
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ *Timeline = (gctHANDLE) timeline;
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++ gcmkASSERT(Timeline != gcvNULL);
++
++ /* Destroy timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++ sync_timeline_destroy(&timeline->obj);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ )
++{
++ int fd = -1;
++ struct viv_sync_timeline *timeline;
++ struct sync_pt * pt = gcvNULL;
++ struct sync_fence * fence;
++ char name[32];
++ gcsSYNC_POINT_PTR syncPoint;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Timeline=0x%X SyncPoint=%d",
++ Os, Timeline, (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Cast timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++
++ fd = get_unused_fd();
++
++ if (fd < 0)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Create viv_sync_pt. */
++ pt = viv_sync_pt_create(timeline, SyncPoint);
++
++ if (pt == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Reference sync_timeline. */
++ syncPoint->timeline = &timeline->obj;
++
++ /* Build fence name. */
++ snprintf(name, 32, "viv sync_fence-%u", (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ /* Create sync_fence. */
++ fence = sync_fence_create(name, pt);
++
++ if (fence == NULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Install fence to fd. */
++ sync_fence_install(fence, fd);
++
++ *FenceFD = fd;
++ gcmkFOOTER_ARG("*FenceFD=%d", fd);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Error roll back. */
++ if (pt)
++ {
++ sync_pt_free(pt);
++ }
++
++ if (fd > 0)
++ {
++ put_unused_fd(fd);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckOS_CPUPhysicalToGPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 CPUPhysical,
++ IN gctUINT32_PTR GPUPhysical
++ )
++{
++ gcsPLATFORM * platform;
++ gcmkHEADER_ARG("CPUPhysical=0x%X", CPUPhysical);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->getGPUPhysical)
++ {
++ gcmkVERIFY_OK(
++ platform->ops->getGPUPhysical(platform, CPUPhysical, GPUPhysical));
++ }
++ else
++ {
++ *GPUPhysical = CPUPhysical;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_GPUPhysicalToCPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 GPUPhysical,
++ IN gctUINT32_PTR CPUPhysical
++ )
++{
++ gcmkHEADER_ARG("GPUPhysical=0x%X", GPUPhysical);
++
++ *CPUPhysical = GPUPhysical;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_PhysicalToPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Physical,
++ OUT gctUINT32 * PhysicalAddress
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ if (allocator)
++ {
++ return allocator->ops->Physical(allocator, mdl, 0, PhysicalAddress);
++ }
++
++ return gcvSTATUS_NOT_SUPPORTED;
++}
++
++gceSTATUS
++gckOS_QueryOption(
++ IN gckOS Os,
++ IN gctCONST_STRING Option,
++ OUT gctUINT32 * Value
++ )
++{
++ gckGALDEVICE device = Os->device;
++
++ if (!strcmp(Option, "physBase"))
++ {
++ *Value = device->physBase;
++ return gcvSTATUS_OK;
++ }
++ else if (!strcmp(Option, "physSize"))
++ {
++ *Value = device->physSize;
++ return gcvSTATUS_OK;
++ }
++ else if (!strcmp(Option, "mmu"))
++ {
++ *Value = device->mmu;
++ return gcvSTATUS_OK;
++ }
++
++ return gcvSTATUS_NOT_SUPPORTED;
++}
++
++static int
++fd_release(
++ struct inode *inode,
++ struct file *file
++ )
++{
++ gcsFDPRIVATE_PTR private = (gcsFDPRIVATE_PTR)file->private_data;
++
++ if (private && private->release)
++ {
++ return private->release(private);
++ }
++
++ return 0;
++}
++
++static const struct file_operations fd_fops = {
++ .release = fd_release,
++};
++
++gceSTATUS
++gckOS_GetFd(
++ IN gctSTRING Name,
++ IN gcsFDPRIVATE_PTR Private,
++ OUT gctINT *Fd
++ )
++{
++ *Fd = anon_inode_getfd(Name, &fd_fops, Private, O_RDWR);
++
++ if (*Fd < 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_os.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_os.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_os.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_os.h 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,88 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_os_h_
++#define __gc_hal_kernel_os_h_
++
++typedef struct _LINUX_MDL_MAP
++{
++ gctINT pid;
++ gctPOINTER vmaAddr;
++ gctUINT32 count;
++ struct vm_area_struct * vma;
++ struct _LINUX_MDL_MAP * next;
++}
++LINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL_MAP * PLINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL
++{
++ char * addr;
++
++ union _pages
++ {
++ /* Pointer to a array of pages. */
++ struct page * contiguousPages;
++ /* Pointer to a array of pointers to page. */
++ struct page ** nonContiguousPages;
++ }
++ u;
++
++#ifdef NO_DMA_COHERENT
++ gctPOINTER kaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gctINT numPages;
++ gctINT pagedMem;
++ gctBOOL contiguous;
++ gctBOOL exact;
++ dma_addr_t dmaHandle;
++ PLINUX_MDL_MAP maps;
++ struct _LINUX_MDL * prev;
++ struct _LINUX_MDL * next;
++
++ /* Pointer to allocator which allocates memory for this mdl. */
++ void * allocator;
++
++ /* Private data used by allocator. */
++ void * priv;
++
++ uint gid;
++}
++LINUX_MDL, *PLINUX_MDL;
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT PID
++ );
++
++typedef struct _DRIVER_ARGS
++{
++ gctUINT64 InputBuffer;
++ gctUINT64 InputBufferSize;
++ gctUINT64 OutputBuffer;
++ gctUINT64 OutputBufferSize;
++}
++DRIVER_ARGS;
++
++#endif /* __gc_hal_kernel_os_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_platform.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_platform.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_platform.h 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,270 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef _gc_hal_kernel_platform_h_
++#define _gc_hal_kernel_platform_h_
++#include <linux/mm.h>
++
++typedef struct _gcsMODULE_PARAMETERS
++{
++ gctINT irqLine;
++ gctUINT registerMemBase;
++ gctUINT registerMemSize;
++ gctINT irqLine2D;
++ gctUINT registerMemBase2D;
++ gctUINT registerMemSize2D;
++ gctINT irqLineVG;
++ gctUINT registerMemBaseVG;
++ gctUINT registerMemSizeVG;
++ gctUINT contiguousSize;
++ gctUINT contiguousBase;
++ gctUINT contiguousRequested;
++ gctUINT bankSize;
++ gctINT fastClear;
++ gctINT compression;
++ gctINT powerManagement;
++ gctINT gpuProfiler;
++ gctINT signal;
++ gctUINT baseAddress;
++ gctUINT physSize;
++ gctUINT logFileSize;
++ gctUINT recovery;
++ gctUINT stuckDump;
++ gctUINT showArgs;
++ gctUINT gpu3DMinClock;
++}
++gcsMODULE_PARAMETERS;
++
++typedef struct _gcsPLATFORM * gckPLATFORM;
++
++typedef struct _gcsPLATFORM_OPERATIONS
++{
++ /*******************************************************************************
++ **
++ ** needAddDevice
++ **
++ ** Determine whether platform_device is created by initialization code.
++ ** If platform_device is created by BSP, return gcvFLASE here.
++ */
++ gctBOOL
++ (*needAddDevice)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustParam
++ **
++ ** Override content of arguments, if a argument is not changed here, it will
++ ** keep as default value or value set by insmod command line.
++ */
++ gceSTATUS
++ (*adjustParam)(
++ IN gckPLATFORM Platform,
++ OUT gcsMODULE_PARAMETERS *Args
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustDriver
++ **
++ ** Override content of platform_driver which will be registered.
++ */
++ gceSTATUS
++ (*adjustDriver)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** getPower
++ **
++ ** Prepare power and clock operation.
++ */
++ gceSTATUS
++ (*getPower)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** putPower
++ **
++ ** Finish power and clock operation.
++ */
++ gceSTATUS
++ (*putPower)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** allocPriv
++ **
++ ** Construct platform private data.
++ */
++ gceSTATUS
++ (*allocPriv)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** freePriv
++ **
++ ** free platform private data.
++ */
++ gceSTATUS
++ (*freePriv)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** setPower
++ **
++ ** Set power state of specified GPU.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to config.
++ **
++ ** gceBOOL Enable
++ ** Enable or disable power.
++ */
++ gceSTATUS
++ (*setPower)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ );
++
++ /*******************************************************************************
++ **
++ ** setClock
++ **
++ ** Set clock state of specified GPU.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to config.
++ **
++ ** gceBOOL Enable
++ ** Enable or disable clock.
++ */
++ gceSTATUS
++ (*setClock)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ );
++
++ /*******************************************************************************
++ **
++ ** reset
++ **
++ ** Reset GPU outside.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to reset.
++ */
++ gceSTATUS
++ (*reset)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU
++ );
++
++ /*******************************************************************************
++ **
++ ** getGPUPhysical
++ **
++ ** Convert CPU physical address to GPU physical address if they are
++ ** different.
++ */
++ gceSTATUS
++ (*getGPUPhysical)(
++ IN gckPLATFORM Platform,
++ IN gctUINT32 CPUPhysical,
++ OUT gctUINT32_PTR GPUPhysical
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustProt
++ **
++ ** Override Prot flag when mapping paged memory to userspace.
++ */
++ gceSTATUS
++ (*adjustProt)(
++ IN struct vm_area_struct * vma
++ );
++
++ /*******************************************************************************
++ **
++ ** shrinkMemory
++ **
++ ** Do something to collect memory, eg, act as oom killer.
++ */
++ gceSTATUS
++ (*shrinkMemory)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** cache
++ **
++ ** Cache operation.
++ */
++ gceSTATUS
++ (*cache)(
++ IN gckPLATFORM Platform,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++}
++gcsPLATFORM_OPERATIONS;
++
++typedef struct _gcsPLATFORM
++{
++ struct platform_device* device;
++ struct platform_driver* driver;
++
++ gcsPLATFORM_OPERATIONS* ops;
++
++ void* priv;
++}
++gcsPLATFORM;
++
++void
++gckPLATFORM_QueryOperations(
++ IN gcsPLATFORM_OPERATIONS ** Operations
++ );
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_power.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_power.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_power.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_power.c 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,347 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_POWER
++
++/******************************************************************************\
++************************ Dynamic Voltage Frequency Setting *********************
++\******************************************************************************/
++#if gcdDVFS
++static gctUINT32
++_GetLoadHistory(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Select,
++ IN gctUINT32 Index
++)
++{
++ return Dvfs->loads[Index];
++}
++
++static void
++_IncreaseScale(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ if (Dvfs->currentScale < 32)
++ {
++ *Scale = Dvfs->currentScale + 8;
++ }
++ else
++ {
++ *Scale = Dvfs->currentScale + 8;
++ *Scale = gcmMIN(64, *Scale);
++ }
++}
++
++static void
++_RecordFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory *history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ if (history->frequency == 0)
++ {
++ history->frequency = Frequency;
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ history->count++;
++ }
++}
++
++static gctUINT32
++_GetFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory * history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ return history->count;
++ }
++
++ return 0;
++}
++
++static void
++_Policy(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ gctUINT8 load[4], nextLoad;
++ gctUINT8 scale;
++
++ /* Last 4 history. */
++ load[0] = (Load & 0xFF);
++ load[1] = (Load & 0xFF00) >> 8;
++ load[2] = (Load & 0xFF0000) >> 16;
++ load[3] = (Load & 0xFF000000) >> 24;
++
++ /* Determine target scale. */
++ if (load[0] > 54)
++ {
++ _IncreaseScale(Dvfs, Load, &scale);
++ }
++ else
++ {
++ nextLoad = (load[0] + load[1] + load[2] + load[3])/4;
++
++ scale = Dvfs->currentScale * (nextLoad) / 54;
++
++ scale = gcmMAX(1, scale);
++ scale = gcmMIN(64, scale);
++ }
++
++ Dvfs->totalConfig++;
++
++ Dvfs->loads[(load[0]-1)/8]++;
++
++ *Scale = scale;
++
++
++ if (Dvfs->totalConfig % 100 == 0)
++ {
++ gcmkPRINT("=======================================================");
++ gcmkPRINT("GPU Load: %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ 8, 16, 24, 32, 40, 48, 56, 64);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ _GetLoadHistory(Dvfs,2, 0),
++ _GetLoadHistory(Dvfs,2, 1),
++ _GetLoadHistory(Dvfs,2, 2),
++ _GetLoadHistory(Dvfs,2, 3),
++ _GetLoadHistory(Dvfs,2, 4),
++ _GetLoadHistory(Dvfs,2, 5),
++ _GetLoadHistory(Dvfs,2, 6),
++ _GetLoadHistory(Dvfs,2, 7)
++ );
++
++ gcmkPRINT("Frequency(MHz) %-8d %-8d %-8d %-8d %-8d",
++ 58, 120, 240, 360, 480);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d",
++ _GetFrequencyHistory(Dvfs, 58),
++ _GetFrequencyHistory(Dvfs,120),
++ _GetFrequencyHistory(Dvfs,240),
++ _GetFrequencyHistory(Dvfs,360),
++ _GetFrequencyHistory(Dvfs,480)
++ );
++ }
++}
++
++static void
++_TimerFunction(
++ gctPOINTER Data
++ )
++{
++ gceSTATUS status;
++ gckDVFS dvfs = (gckDVFS) Data;
++ gckHARDWARE hardware = dvfs->hardware;
++ gctUINT32 value;
++ gctUINT32 frequency;
++ gctUINT8 scale;
++ gctUINT32 t1, t2, consumed;
++
++ gckOS_GetTicks(&t1);
++
++ gcmkONERROR(gckHARDWARE_QueryLoad(hardware, &value));
++
++ /* determine target sacle. */
++ _Policy(dvfs, value, &scale);
++
++ /* Set frequency and voltage. */
++ gcmkONERROR(gckOS_SetGPUFrequency(hardware->os, hardware->core, scale));
++
++ /* Query real frequency. */
++ gcmkONERROR(
++ gckOS_QueryGPUFrequency(hardware->os,
++ hardware->core,
++ &frequency,
++ &dvfs->currentScale));
++
++ _RecordFrequencyHistory(dvfs, frequency);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_POWER,
++ "Current frequency = %d",
++ frequency);
++
++ /* Set period. */
++ gcmkONERROR(gckHARDWARE_SetDVFSPeroid(hardware, frequency));
++
++OnError:
++ /* Determine next querying time. */
++ gckOS_GetTicks(&t2);
++
++ consumed = gcmMIN(((long)t2 - (long)t1), 5);
++
++ if (dvfs->stop == gcvFALSE)
++ {
++ gcmkVERIFY_OK(gckOS_StartTimer(hardware->os,
++ dvfs->timer,
++ dvfs->pollingTime - consumed));
++ }
++
++ return;
++}
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Dvfs
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer;
++ gckDVFS dvfs = gcvNULL;
++ gckOS os = Hardware->os;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Allocate a gckDVFS manager. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckDVFS), &pointer));
++
++ gckOS_ZeroMemory(pointer, gcmSIZEOF(struct _gckDVFS));
++
++ dvfs = pointer;
++
++ /* Initialization. */
++ dvfs->hardware = Hardware;
++ dvfs->pollingTime = gcdDVFS_POLLING_TIME;
++ dvfs->os = Hardware->os;
++ dvfs->currentScale = 64;
++
++ /* Create a polling timer. */
++ gcmkONERROR(gckOS_CreateTimer(os, _TimerFunction, pointer, &dvfs->timer));
++
++ /* Initialize frequency and voltage adjustment helper. */
++ gcmkONERROR(gckOS_PrepareGPUFrequency(os, Hardware->core));
++
++ /* Return result. */
++ *Dvfs = dvfs;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (dvfs)
++ {
++ if (dvfs->timer)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyTimer(os, dvfs->timer));
++ }
++
++ gcmkOS_SAFE_FREE(os, dvfs);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Deinitialize helper fuunction. */
++ gcmkVERIFY_OK(gckOS_FinishGPUFrequency(Dvfs->os, Dvfs->hardware->core));
++
++ /* DestroyTimer. */
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Dvfs->os, Dvfs->timer));
++
++ gcmkOS_SAFE_FREE(Dvfs->os, Dvfs);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ gckHARDWARE_InitDVFS(Dvfs->hardware);
++
++ Dvfs->stop = gcvFALSE;
++
++ gckOS_StartTimer(Dvfs->os, Dvfs->timer, Dvfs->pollingTime);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ Dvfs->stop = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_precomp.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_precomp.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_precomp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_precomp.h 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,29 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_precomp_h_
++#define __gc_hal_kernel_precomp_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++
++#endif /* __gc_hal_kernel_precomp_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_probe.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_probe.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_probe.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_probe.c 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,1253 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <linux/device.h>
++#include <linux/slab.h>
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_driver.h"
++
++#include <linux/platform_device.h>
++
++#ifdef CONFIG_PXA_DVFM
++# include <mach/dvfm.h>
++# include <mach/pxa3xx_dvfm.h>
++#endif
++
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_DRIVER
++
++MODULE_DESCRIPTION("Vivante Graphics Driver");
++MODULE_LICENSE("GPL");
++
++static struct class* gpuClass;
++
++static gcsPLATFORM platform;
++
++static gckGALDEVICE galDevice;
++
++static uint major = 199;
++module_param(major, uint, 0644);
++
++static int irqLine = -1;
++module_param(irqLine, int, 0644);
++
++static ulong registerMemBase = 0x80000000;
++module_param(registerMemBase, ulong, 0644);
++
++static ulong registerMemSize = 2 << 10;
++module_param(registerMemSize, ulong, 0644);
++
++static int irqLine2D = -1;
++module_param(irqLine2D, int, 0644);
++
++static ulong registerMemBase2D = 0x00000000;
++module_param(registerMemBase2D, ulong, 0644);
++
++static ulong registerMemSize2D = 2 << 10;
++module_param(registerMemSize2D, ulong, 0644);
++
++static int irqLineVG = -1;
++module_param(irqLineVG, int, 0644);
++
++static ulong registerMemBaseVG = 0x00000000;
++module_param(registerMemBaseVG, ulong, 0644);
++
++static ulong registerMemSizeVG = 2 << 10;
++module_param(registerMemSizeVG, ulong, 0644);
++
++#ifndef gcdDEFAULT_CONTIGUOUS_SIZE
++#define gcdDEFAULT_CONTIGUOUS_SIZE (4 << 20)
++#endif
++static ulong contiguousSize = gcdDEFAULT_CONTIGUOUS_SIZE;
++module_param(contiguousSize, ulong, 0644);
++
++static ulong contiguousBase = 0;
++module_param(contiguousBase, ulong, 0644);
++
++static ulong bankSize = 0;
++module_param(bankSize, ulong, 0644);
++
++static int fastClear = -1;
++module_param(fastClear, int, 0644);
++
++static int compression = -1;
++module_param(compression, int, 0644);
++
++static int powerManagement = -1;
++module_param(powerManagement, int, 0644);
++
++static int gpuProfiler = 0;
++module_param(gpuProfiler, int, 0644);
++
++static int signal = 48;
++module_param(signal, int, 0644);
++
++static ulong baseAddress = 0;
++module_param(baseAddress, ulong, 0644);
++
++static ulong physSize = 0;
++module_param(physSize, ulong, 0644);
++
++static uint logFileSize = 0;
++module_param(logFileSize,uint, 0644);
++
++static uint recovery = 1;
++module_param(recovery, uint, 0644);
++MODULE_PARM_DESC(recovery, "Recover GPU from stuck (1: Enable, 0: Disable)");
++
++/* Middle needs about 40KB buffer, Maximal may need more than 200KB buffer. */
++static uint stuckDump = 1;
++module_param(stuckDump, uint, 0644);
++MODULE_PARM_DESC(stuckDump, "Level of stuck dump content (1: Minimal, 2: Middle, 3: Maximal)");
++
++static int showArgs = 0;
++module_param(showArgs, int, 0644);
++
++static int mmu = 1;
++module_param(mmu, int, 0644);
++
++static int gpu3DMinClock = 1;
++
++static int contiguousRequested = 0;
++
++static int drv_open(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static int drv_release(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ );
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ );
++
++static struct file_operations driver_fops =
++{
++ .owner = THIS_MODULE,
++ .open = drv_open,
++ .release = drv_release,
++ .unlocked_ioctl = drv_ioctl,
++#ifdef HAVE_COMPAT_IOCTL
++ .compat_ioctl = drv_ioctl,
++#endif
++ .mmap = drv_mmap,
++};
++
++void
++_UpdateModuleParam(
++ gcsMODULE_PARAMETERS *Param
++ )
++{
++ irqLine = Param->irqLine ;
++ registerMemBase = Param->registerMemBase;
++ registerMemSize = Param->registerMemSize;
++ irqLine2D = Param->irqLine2D ;
++ registerMemBase2D = Param->registerMemBase2D;
++ registerMemSize2D = Param->registerMemSize2D;
++ irqLineVG = Param->irqLineVG;
++ registerMemBaseVG = Param->registerMemBaseVG;
++ registerMemSizeVG = Param->registerMemSizeVG;
++ contiguousSize = Param->contiguousSize;
++ contiguousBase = Param->contiguousBase;
++ bankSize = Param->bankSize;
++ fastClear = Param->fastClear;
++ compression = Param->compression;
++ powerManagement = Param->powerManagement;
++ gpuProfiler = Param->gpuProfiler;
++ signal = Param->signal;
++ baseAddress = Param->baseAddress;
++ physSize = Param->physSize;
++ logFileSize = Param->logFileSize;
++ recovery = Param->recovery;
++ stuckDump = Param->stuckDump;
++ showArgs = Param->showArgs;
++ contiguousRequested = Param->contiguousRequested;
++ gpu3DMinClock = Param->gpu3DMinClock;
++}
++
++void
++gckOS_DumpParam(
++ void
++ )
++{
++ printk("Galcore options:\n");
++ printk(" irqLine = %d\n", irqLine);
++ printk(" registerMemBase = 0x%08lX\n", registerMemBase);
++ printk(" registerMemSize = 0x%08lX\n", registerMemSize);
++
++ if (irqLine2D != -1)
++ {
++ printk(" irqLine2D = %d\n", irqLine2D);
++ printk(" registerMemBase2D = 0x%08lX\n", registerMemBase2D);
++ printk(" registerMemSize2D = 0x%08lX\n", registerMemSize2D);
++ }
++
++ if (irqLineVG != -1)
++ {
++ printk(" irqLineVG = %d\n", irqLineVG);
++ printk(" registerMemBaseVG = 0x%08lX\n", registerMemBaseVG);
++ printk(" registerMemSizeVG = 0x%08lX\n", registerMemSizeVG);
++ }
++
++ printk(" contiguousSize = %ld\n", contiguousSize);
++ printk(" contiguousBase = 0x%08lX\n", contiguousBase);
++ printk(" bankSize = 0x%08lX\n", bankSize);
++ printk(" fastClear = %d\n", fastClear);
++ printk(" compression = %d\n", compression);
++ printk(" signal = %d\n", signal);
++ printk(" powerManagement = %d\n", powerManagement);
++ printk(" baseAddress = 0x%08lX\n", baseAddress);
++ printk(" physSize = 0x%08lX\n", physSize);
++ printk(" logFileSize = %d KB \n", logFileSize);
++ printk(" recovery = %d\n", recovery);
++ printk(" stuckDump = %d\n", stuckDump);
++ printk(" gpuProfiler = %d\n", gpuProfiler);
++}
++
++int drv_open(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gctBOOL attached = gcvFALSE;
++ gcsHAL_PRIVATE_DATA_PTR data = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = kmalloc(sizeof(gcsHAL_PRIVATE_DATA), GFP_KERNEL | __GFP_NOWARN);
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ data->device = galDevice;
++ data->mappedMemory = gcvNULL;
++ data->contiguousLogical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&data->pidOpen));
++
++ /* Attached the process. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvTRUE));
++ }
++ }
++ attached = gcvTRUE;
++
++ if (!galDevice->contiguousMapped)
++ {
++ if (galDevice->contiguousPhysical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_MapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ &data->contiguousLogical
++ ));
++ }
++ }
++
++ filp->private_data = data;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ if (data != gcvNULL)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical
++ ));
++ }
++
++ kfree(data);
++ }
++
++ if (attached)
++ {
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvFALSE));
++ }
++ }
++ }
++
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++int drv_release(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (!device->contiguousMapped)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_UnmapMemoryEx(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical,
++ data->pidOpen
++ ));
++
++ data->contiguousLogical = gcvNULL;
++ }
++ }
++
++ /* A process gets detached. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcessEx(galDevice->kernels[i], gcvFALSE, data->pidOpen));
++ }
++ }
++
++ kfree(data);
++ filp->private_data = NULL;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gctUINT32 copyLen;
++ DRIVER_ARGS drvArgs;
++ gckGALDEVICE device;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gctINT32 i, count;
++ gckVIDMEM_NODE nodeObject;
++
++ gcmkHEADER_ARG(
++ "filp=0x%08X ioctlCode=0x%08X arg=0x%08X",
++ filp, ioctlCode, arg
++ );
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if ((ioctlCode != IOCTL_GCHAL_INTERFACE)
++ && (ioctlCode != IOCTL_GCHAL_KERNEL_INTERFACE)
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown command %d\n",
++ __FUNCTION__, __LINE__,
++ ioctlCode
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get the drvArgs. */
++ copyLen = copy_from_user(
++ &drvArgs, (void *) arg, sizeof(DRIVER_ARGS)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of the input arguments.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Now bring in the gcsHAL_INTERFACE structure. */
++ if ((drvArgs.InputBufferSize != sizeof(gcsHAL_INTERFACE))
++ || (drvArgs.OutputBufferSize != sizeof(gcsHAL_INTERFACE))
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): input or/and output structures are invalid.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ copyLen = copy_from_user(
++ &iface, gcmUINT64_TO_PTR(drvArgs.InputBuffer), sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of input HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (iface.command == gcvHAL_CHIP_INFO)
++ {
++ count = 0;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ iface.u.ChipInfo.types[count] = gcvHARDWARE_VG;
++ }
++ else
++#endif
++ {
++ gcmkVERIFY_OK(gckHARDWARE_GetType(device->kernels[i]->hardware,
++ &iface.u.ChipInfo.types[count]));
++ }
++ count++;
++ }
++ }
++
++ iface.u.ChipInfo.count = count;
++ iface.status = status = gcvSTATUS_OK;
++ }
++ else
++ {
++ if (iface.hardwareType > 7)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown hardwareType %d\n",
++ __FUNCTION__, __LINE__,
++ iface.hardwareType
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (device->coreMapping[iface.hardwareType] == gcvCORE_VG)
++ {
++ status = gckVGKERNEL_Dispatch(device->kernels[gcvCORE_VG],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ else
++#endif
++ {
++ status = gckKERNEL_Dispatch(device->kernels[device->coreMapping[iface.hardwareType]],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ }
++
++ /* Redo system call after pending signal is handled. */
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkFOOTER();
++ return -ERESTARTSYS;
++ }
++
++ if (gcmIS_SUCCESS(status) && (iface.command == gcvHAL_LOCK_VIDEO_MEMORY))
++ {
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 processID;
++
++ gckOS_GetProcessID(&processID);
++
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(device->kernels[device->coreMapping[iface.hardwareType]],
++ processID,
++ (gctUINT32)iface.u.LockVideoMemory.node,
++ &nodeObject));
++ node = nodeObject->node;
++
++ /* Special case for mapped memory. */
++ if ((data->mappedMemory != gcvNULL)
++ && (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ )
++ {
++ /* Compute offset into mapped memory. */
++ gctUINT32 offset
++ = (gctUINT8 *) gcmUINT64_TO_PTR(iface.u.LockVideoMemory.memory)
++ - (gctUINT8 *) device->contiguousBase;
++
++ /* Compute offset into user-mapped region. */
++ iface.u.LockVideoMemory.memory =
++ gcmPTR_TO_UINT64((gctUINT8 *) data->mappedMemory + offset);
++ }
++ }
++
++ /* Copy data back to the user. */
++ copyLen = copy_to_user(
++ gcmUINT64_TO_PTR(drvArgs.OutputBuffer), &iface, sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of output HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("filp=0x%08X vma=0x%08X", filp, vma);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if !gcdPAGED_MEMORY_CACHEABLE
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++ vma->vm_flags |= gcdVM_FLAGS;
++#endif
++ vma->vm_pgoff = 0;
++
++ if (device->contiguousMapped)
++ {
++ unsigned long size = vma->vm_end - vma->vm_start;
++ int ret = 0;
++
++ if (size > device->contiguousSize)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Invalid mapping size.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ ret = io_remap_pfn_range(
++ vma,
++ vma->vm_start,
++ device->requestedContiguousBase >> PAGE_SHIFT,
++ size,
++ vma->vm_page_prot
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): io_remap_pfn_range failed %d\n",
++ __FUNCTION__, __LINE__,
++ ret
++ );
++
++ data->mappedMemory = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ data->mappedMemory = (gctPOINTER) vma->vm_start;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++ }
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++
++static int drv_init(struct platform_device *pdev)
++{
++ int ret;
++ int result = -EINVAL;
++ gceSTATUS status;
++ gckGALDEVICE device = gcvNULL;
++ struct class* device_class = gcvNULL;
++
++ gcsDEVICE_CONSTRUCT_ARGS args = {
++ .recovery = recovery,
++ .stuckDump = stuckDump,
++ .gpu3DMinClock = gpu3DMinClock,
++ .contiguousRequested = contiguousRequested,
++ .platform = &platform,
++ .mmu = mmu,
++ };
++
++ gcmkHEADER();
++
++ printk(KERN_INFO "Galcore version %d.%d.%d.%d\n",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
++
++#if !VIVANTE_PROFILER_PM
++ /* when enable gpu profiler, we need to turn off gpu powerMangement */
++ if (gpuProfiler)
++ {
++ powerManagement = 0;
++ }
++#endif
++
++ if (showArgs)
++ {
++ gckOS_DumpParam();
++ }
++
++ if (logFileSize != 0)
++ {
++ gckDEBUGFS_Initialize();
++ }
++
++ /* Create the GAL device. */
++ status = gckGALDEVICE_Construct(
++ irqLine,
++ registerMemBase, registerMemSize,
++ irqLine2D,
++ registerMemBase2D, registerMemSize2D,
++ irqLineVG,
++ registerMemBaseVG, registerMemSizeVG,
++ contiguousBase, contiguousSize,
++ bankSize, fastClear, compression, baseAddress, physSize, signal,
++ logFileSize,
++ powerManagement,
++ gpuProfiler,
++ &args,
++ &pdev->dev,
++ &device
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the GAL device: status=%d\n",
++ __FUNCTION__, __LINE__, status);
++
++ goto OnError;
++ }
++
++ /* Start the GAL device. */
++ gcmkONERROR(gckGALDEVICE_Start(device));
++
++ if ((physSize != 0)
++ && (device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ && (device->kernels[gcvCORE_MAJOR]->hardware->mmuVersion != 0))
++ {
++ /* Reset the base address */
++ device->baseAddress = 0;
++ }
++
++ /* Register the character device. */
++ ret = register_chrdev(major, DEVICE_NAME, &driver_fops);
++
++ if (ret < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not allocate major number for mmap.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (major == 0)
++ {
++ major = ret;
++ }
++
++ /* Create the device class. */
++ device_class = class_create(THIS_MODULE, "graphics_class");
++
++ if (IS_ERR(device_class))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the class.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device_create(device_class, NULL, MKDEV(major, 0), NULL, DEVICE_NAME);
++
++ galDevice = device;
++ gpuClass = device_class;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "%s(%d): irqLine=%d, contiguousSize=%lu, memBase=0x%lX\n",
++ __FUNCTION__, __LINE__,
++ irqLine, contiguousSize, registerMemBase
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ /* Roll back. */
++ if (device_class != gcvNULL)
++ {
++ device_destroy(device_class, MKDEV(major, 0));
++ class_destroy(device_class);
++ }
++
++ if (device != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(device));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++ }
++
++ gcmkFOOTER();
++ return result;
++}
++
++static void drv_exit(void)
++{
++ gcmkHEADER();
++
++ gcmkASSERT(gpuClass != gcvNULL);
++ device_destroy(gpuClass, MKDEV(major, 0));
++ class_destroy(gpuClass);
++
++ unregister_chrdev(major, DEVICE_NAME);
++
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(galDevice));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(galDevice));
++
++ if(gckDEBUGFS_IsEnabled())
++ {
++ gckDEBUGFS_Terminate();
++ }
++
++ gcmkFOOTER_NO();
++}
++
++static int gpu_probe(struct platform_device *pdev)
++{
++ int ret = -ENODEV;
++ gcsMODULE_PARAMETERS moduleParam = {
++ .irqLine = irqLine,
++ .registerMemBase = registerMemBase,
++ .registerMemSize = registerMemSize,
++ .irqLine2D = irqLine2D,
++ .registerMemBase2D = registerMemBase2D,
++ .registerMemSize2D = registerMemSize2D,
++ .irqLineVG = irqLineVG,
++ .registerMemBaseVG = registerMemBaseVG,
++ .registerMemSizeVG = registerMemSizeVG,
++ .contiguousSize = contiguousSize,
++ .contiguousBase = contiguousBase,
++ .bankSize = bankSize,
++ .fastClear = fastClear,
++ .compression = compression,
++ .powerManagement = powerManagement,
++ .gpuProfiler = gpuProfiler,
++ .signal = signal,
++ .baseAddress = baseAddress,
++ .physSize = physSize,
++ .logFileSize = logFileSize,
++ .recovery = recovery,
++ .stuckDump = stuckDump,
++ .showArgs = showArgs,
++ .gpu3DMinClock = gpu3DMinClock,
++ };
++
++ gcmkHEADER();
++
++ platform.device = pdev;
++
++ if (platform.ops->getPower)
++ {
++ if (gcmIS_ERROR(platform.ops->getPower(&platform)))
++ {
++ gcmkFOOTER_NO();
++ return ret;
++ }
++ }
++
++ if (platform.ops->adjustParam)
++ {
++ /* Override default module param. */
++ platform.ops->adjustParam(&platform, &moduleParam);
++
++ /* Update module param because drv_init() uses them directly. */
++ _UpdateModuleParam(&moduleParam);
++ }
++
++ ret = drv_init(pdev);
++
++ if (!ret)
++ {
++ platform_set_drvdata(pdev, galDevice);
++
++ gcmkFOOTER_NO();
++ return ret;
++ }
++
++ gcmkFOOTER_ARG(KERN_INFO "Failed to register gpu driver: %d\n", ret);
++ return ret;
++}
++
++static int gpu_remove(struct platform_device *pdev)
++{
++ gcmkHEADER();
++
++ drv_exit();
++
++ if (platform.ops->putPower)
++ {
++ platform.ops->putPower(&platform);
++ }
++
++ gcmkFOOTER_NO();
++ return 0;
++}
++
++static int gpu_suspend(struct platform_device *dev, pm_message_t state)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++
++ device = platform_get_drvdata(dev);
++
++ if (!device)
++ {
++ return -1;
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++ /* Store states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_QueryPowerManagementState(device->kernels[i]->vg->hardware, &device->statesStored[i]);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_QueryPowerManagementState(device->kernels[i]->hardware, &device->statesStored[i]);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_OFF);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_OFF);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ }
++ }
++
++ return 0;
++}
++
++static int gpu_resume(struct platform_device *dev)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++ gceCHIPPOWERSTATE statesStored;
++
++ device = platform_get_drvdata(dev);
++
++ if (!device)
++ {
++ return -1;
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_ON);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_ON);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ /* Convert global state to crossponding internal state. */
++ switch(device->statesStored[i])
++ {
++ case gcvPOWER_OFF:
++ statesStored = gcvPOWER_OFF_BROADCAST;
++ break;
++ case gcvPOWER_IDLE:
++ statesStored = gcvPOWER_IDLE_BROADCAST;
++ break;
++ case gcvPOWER_SUSPEND:
++ statesStored = gcvPOWER_SUSPEND_BROADCAST;
++ break;
++ case gcvPOWER_ON:
++ statesStored = gcvPOWER_ON_AUTO;
++ break;
++ default:
++ statesStored = device->statesStored[i];
++ break;
++ }
++
++ /* Restore states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, statesStored);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, statesStored);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++ }
++ }
++
++ return 0;
++}
++
++#if defined(CONFIG_PM)
++static int gpu_runtime_suspend(struct device *dev)
++{
++ pm_message_t state={0};
++ return gpu_suspend(to_platform_device(dev), state);
++}
++
++static int gpu_runtime_resume(struct device *dev)
++{
++ return gpu_resume(to_platform_device(dev));
++}
++
++static const struct dev_pm_ops gpu_pm_ops = {
++ SET_RUNTIME_PM_OPS(gpu_runtime_suspend, gpu_runtime_resume, NULL)
++};
++#endif
++
++static struct platform_driver gpu_driver = {
++ .probe = gpu_probe,
++ .remove = gpu_remove,
++
++ .driver = {
++ .name = DEVICE_NAME,
++ .pm = &gpu_pm_ops,
++ }
++};
++
++static int __init gpu_init(void)
++{
++ int ret = 0;
++
++ memset(&platform, 0, sizeof(gcsPLATFORM));
++
++ gckPLATFORM_QueryOperations(&platform.ops);
++
++ if (platform.ops == gcvNULL)
++ {
++ printk(KERN_ERR "galcore: No platform specific operations.\n");
++ ret = -ENODEV;
++ goto out;
++ }
++
++ if (platform.ops->allocPriv)
++ {
++ /* Allocate platform private data. */
++ if (gcmIS_ERROR(platform.ops->allocPriv(&platform)))
++ {
++ ret = -ENOMEM;
++ goto out;
++ }
++ }
++
++ if (platform.ops->needAddDevice
++ && platform.ops->needAddDevice(&platform))
++ {
++ /* Allocate device */
++ platform.device = platform_device_alloc(DEVICE_NAME, -1);
++ if (!platform.device)
++ {
++ printk(KERN_ERR "galcore: platform_device_alloc failed.\n");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Add device */
++ ret = platform_device_add(platform.device);
++ if (ret)
++ {
++ printk(KERN_ERR "galcore: platform_device_add failed.\n");
++ goto put_dev;
++ }
++ }
++
++ platform.driver = &gpu_driver;
++
++ if (platform.ops->adjustDriver)
++ {
++ /* Override default platform_driver struct. */
++ platform.ops->adjustDriver(&platform);
++ }
++
++ ret = platform_driver_register(&gpu_driver);
++ if (!ret)
++ {
++ goto out;
++ }
++
++ platform_device_del(platform.device);
++put_dev:
++ platform_device_put(platform.device);
++
++out:
++ return ret;
++}
++
++static void __exit gpu_exit(void)
++{
++ platform_driver_unregister(&gpu_driver);
++
++ if (platform.ops->needAddDevice
++ && platform.ops->needAddDevice(&platform))
++ {
++ platform_device_unregister(platform.device);
++ }
++
++ if (platform.priv)
++ {
++ /* Free platform private data. */
++ platform.ops->freePriv(&platform);
++ }
++}
++
++module_init(gpu_init);
++module_exit(gpu_exit);
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_sync.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_sync.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_sync.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_sync.c 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,177 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <gc_hal.h>
++#include <gc_hal_base.h>
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++#include <linux/kernel.h>
++#include <linux/file.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/module.h>
++#include <linux/syscalls.h>
++#include <linux/uaccess.h>
++
++#include "gc_hal_kernel_sync.h"
++
++static struct sync_pt *
++viv_sync_pt_dup(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt *pt;
++ struct viv_sync_pt *src;
++ struct viv_sync_timeline *obj;
++
++ src = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ /* Create the new sync_pt. */
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = src->stamp;
++ pt->sync = src->sync;
++
++ /* Reference sync point. */
++ status = gckOS_ReferenceSyncPoint(obj->os, pt->sync);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *)pt;
++}
++
++static int
++viv_sync_pt_has_signaled(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ gctBOOL state;
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *)sync_pt;
++ obj = (struct viv_sync_timeline *)sync_pt->parent;
++
++ status = gckOS_QuerySyncPoint(obj->os, pt->sync, &state);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error. */
++ return -1;
++ }
++
++ return state;
++}
++
++static int
++viv_sync_pt_compare(
++ struct sync_pt * a,
++ struct sync_pt * b
++ )
++{
++ int ret;
++ struct viv_sync_pt * pt1 = (struct viv_sync_pt *) a;
++ struct viv_sync_pt * pt2 = (struct viv_sync_pt *) b;
++
++ ret = (pt1->stamp < pt2->stamp) ? -1
++ : (pt1->stamp == pt2->stamp) ? 0
++ : 1;
++
++ return ret;
++}
++
++static void
++viv_sync_pt_free(
++ struct sync_pt * sync_pt
++ )
++{
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ gckOS_DestroySyncPoint(obj->os, pt->sync);
++}
++
++static struct sync_timeline_ops viv_timeline_ops =
++{
++ .driver_name = "viv_sync",
++ .dup = viv_sync_pt_dup,
++ .has_signaled = viv_sync_pt_has_signaled,
++ .compare = viv_sync_pt_compare,
++ .free_pt = viv_sync_pt_free,
++};
++
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * name,
++ gckOS os
++ )
++{
++ struct viv_sync_timeline * obj;
++
++ obj = (struct viv_sync_timeline *)
++ sync_timeline_create(&viv_timeline_ops, sizeof(struct viv_sync_timeline), name);
++
++ obj->os = os;
++ obj->stamp = 0;
++
++ return obj;
++}
++
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * obj,
++ gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt * pt;
++
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = obj->stamp++;
++ pt->sync = SyncPoint;
++
++ /* Dup signal. */
++ status = gckOS_ReferenceSyncPoint(obj->os, SyncPoint);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *) pt;
++}
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_sync.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_sync.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_sync.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_sync.h 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,72 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_sync_h_
++#define __gc_hal_kernel_sync_h_
++
++#include <linux/types.h>
++
++/* sync.h is in drivers/staging/android/ for now. */
++#include <sync.h>
++
++#include <gc_hal.h>
++#include <gc_hal_base.h>
++
++struct viv_sync_timeline
++{
++ /* Parent object. */
++ struct sync_timeline obj;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++
++ /* Pointer to os struct. */
++ gckOS os;
++};
++
++
++struct viv_sync_pt
++{
++ /* Parent object. */
++ struct sync_pt pt;
++
++ /* Reference sync point*/
++ gctSYNC_POINT sync;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++};
++
++/* Create viv_sync_timeline object. */
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * Name,
++ gckOS Os
++ );
++
++/* Create viv_sync_pt object. */
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * Obj,
++ gctSYNC_POINT SyncPoint
++ );
++
++#endif /* __gc_hal_kernel_sync_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_vg.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_vg.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_vg.c 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,831 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_VG
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++gceSTATUS gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ )
++{
++ gceSTATUS status;
++ gckVGKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Os,
++ sizeof(struct _gckVGKERNEL),
++ (gctPOINTER *) &kernel
++ ));
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->context = Context;
++ kernel->hardware = gcvNULL;
++ kernel->interrupt = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->mmu = gcvNULL;
++ kernel->kernel = inKernel;
++
++ /* Construct the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckVGHARDWARE_Construct(
++ Os, &kernel->hardware
++ ));
++
++ /* Set pointer to gckKERNEL object in gckVGHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ /* Construct the gckVGINTERRUPT object. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Construct(
++ kernel, &kernel->interrupt
++ ));
++
++ /* Construct the gckVGCOMMAND object. */
++ gcmkERR_BREAK(gckVGCOMMAND_Construct(
++ kernel, gcmKB2BYTES(8), gcmKB2BYTES(2), &kernel->command
++ ));
++
++ /* Construct the gckVGMMU object. */
++ gcmkERR_BREAK(gckVGMMU_Construct(
++ kernel, gcmKB2BYTES(32), &kernel->mmu
++ ));
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (kernel != gcvNULL)
++ {
++ if (kernel->mmu != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGMMU_Destroy(kernel->mmu));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->interrupt != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGINTERRUPT_Destroy(kernel->interrupt));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGHARDWARE_Destroy(kernel->hardware));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(Os, kernel));
++ }
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ do
++ {
++ /* Destroy the gckVGMMU object. */
++ if (Kernel->mmu != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGMMU_Destroy(Kernel->mmu));
++ Kernel->mmu = gcvNULL;
++ }
++
++ /* Destroy the gckVGCOMMAND object. */
++ if (Kernel->command != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_Destroy(Kernel->command));
++ Kernel->command = gcvNULL;
++ }
++
++ /* Destroy the gckVGINTERRUPT object. */
++ if (Kernel->interrupt != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Destroy(Kernel->interrupt));
++ Kernel->interrupt = gcvNULL;
++ }
++
++ /* Destroy the gckVGHARDWARE object. */
++ if (Kernel->hardware != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_Destroy(Kernel->hardware));
++ Kernel->hardware = gcvNULL;
++ }
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Free(Kernel->os, Kernel));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_AllocateLinearMemory
++**
++** Function walks all required memory pools and allocates the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL * Pool
++** Pointer the desired memory pool.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctSIZE_T Alignment
++** Required buffer alignment.
++**
++** gceSURF_TYPE Type
++** Surface type.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to the actual pool where the memory was allocated.
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Allocated node.
++*/
++gceSTATUS
++gckVGKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ break;
++
++ default:
++ break;
++ }
++
++ do
++ {
++ /* Verify the number of bytes to allocate. */
++ if (Bytes == 0)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkERR_BREAK(gckVIDMEM_ConstructVirtual(Kernel, gcvFALSE, Bytes, Node));
++
++ /* Success. */
++ break;
++ }
++
++ else
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++
++ if (status == gcvSTATUS_OK)
++ {
++ /* Allocate memory. */
++ status = gckVIDMEM_AllocateLinear(Kernel,
++ videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ (*Pool == gcvPOOL_SYSTEM),
++ Node);
++
++ if (status == gcvSTATUS_OK)
++ {
++ /* Memory allocated. */
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++ else if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++ else if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to virtual memory. */
++ pool = gcvPOOL_VIRTUAL;
++ }
++ else
++ {
++ /* Out of pools. */
++ break;
++ }
++ }
++ /* Loop only for multiple selection pools. */
++ while ((*Pool == gcvPOOL_DEFAULT)
++ || (*Pool == gcvPOOL_LOCAL)
++ || (*Pool == gcvPOOL_UNIFIED)
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Return pool used for allocation. */
++ *Pool = pool;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE * kernelInterface = Interface;
++ gctUINT32 processID;
++ gckKERNEL kernel = Kernel;
++ gctPOINTER info = gcvNULL;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctPOINTER logical = gcvNULL;
++ gctSIZE_T bytes = 0;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interface=0x%x ", Kernel, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkERR_BREAK(gckKERNEL_QueryVideoMemory(
++ Kernel, kernelInterface
++ ));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkERR_BREAK(gckVGHARDWARE_QueryChipIdentity(
++ Kernel->vg->hardware,
++ &kernelInterface->u.QueryChipIdentity.chipModel,
++ &kernelInterface->u.QueryChipIdentity.chipRevision,
++ &kernelInterface->u.QueryChipIdentity.chipFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures2
++ ));
++ break;
++
++ case gcvHAL_QUERY_COMMAND_BUFFER:
++ /* Query command buffer information. */
++ gcmkERR_BREAK(gckKERNEL_QueryCommandBuffer(
++ Kernel,
++ &kernelInterface->u.QueryCommandBuffer.information
++ ));
++ break;
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate non-paged memory. */
++ gcmkERR_BREAK(gckOS_AllocateNonPagedMemory(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free non-paged memory. */
++ gcmkERR_BREAK(gckOS_FreeNonPagedMemory(
++ Kernel->os,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate contiguous memory. */
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical),
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++ gcmkERR_BREAK(gcvSTATUS_NOT_SUPPORTED);
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Kernel, processID,
++ &kernelInterface->u.AllocateLinearVideoMemory.pool,
++ kernelInterface->u.AllocateLinearVideoMemory.bytes,
++ kernelInterface->u.AllocateLinearVideoMemory.alignment,
++ kernelInterface->u.AllocateLinearVideoMemory.type,
++ kernelInterface->u.AllocateLinearVideoMemory.flag,
++ &kernelInterface->u.AllocateLinearVideoMemory.node
++ ));
++
++ break;
++
++ case gcvHAL_RELEASE_VIDEO_MEMORY:
++ /* Free video memory. */
++ gcmkERR_BREAK(gckKERNEL_ReleaseVideoMemory(
++ Kernel, processID,
++ (gctUINT32)kernelInterface->u.ReleaseVideoMemory.node
++ ));
++
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ /* Map memory. */
++ gcmkERR_BREAK(gckKERNEL_MapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ &logical
++ ));
++ kernelInterface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ /* Unmap memory. */
++ gcmkERR_BREAK(gckKERNEL_UnmapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapMemory.logical)
++ ));
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkERR_BREAK(gckOS_MapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapUserMemory.memory),
++ kernelInterface->u.MapUserMemory.physical,
++ (gctSIZE_T) kernelInterface->u.MapUserMemory.size,
++ &info,
++ &kernelInterface->u.MapUserMemory.address
++ ));
++
++ kernelInterface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++
++ /* Clear temp storage. */
++ info = gcvNULL;
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ /* Unmap user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) kernelInterface->u.UnmapUserMemory.size,
++ gcmNAME_TO_PTR(kernelInterface->u.UnmapUserMemory.info),
++ kernelInterface->u.UnmapUserMemory.address
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.UnmapUserMemory.info);
++ break;
++
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ gcmkONERROR(gckKERNEL_LockVideoMemory(Kernel, gcvCORE_VG, processID, FromUser, Interface));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkONERROR(gckKERNEL_UnlockVideoMemory(Kernel, processID, Interface));
++ break;
++
++ case gcvHAL_USER_SIGNAL:
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkERR_BREAK(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++
++ /* Destroy the signal. */
++ gcmkERR_BREAK(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkERR_BREAK(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkERR_BREAK(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++ gcmkERR_BREAK(gckVGCOMMAND_Commit(
++ Kernel->vg->command,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.context),
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.queue),
++ kernelInterface->u.VGCommit.entryCount,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.taskTable)
++ ));
++ break;
++ case gcvHAL_VERSION:
++ kernelInterface->u.Version.major = gcvVERSION_MAJOR;
++ kernelInterface->u.Version.minor = gcvVERSION_MINOR;
++ kernelInterface->u.Version.patch = gcvVERSION_PATCH;
++ kernelInterface->u.Version.build = gcvVERSION_BUILD;
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkERR_BREAK(
++ gckOS_GetBaseAddress(Kernel->os,
++ &kernelInterface->u.GetBaseAddress.baseAddress));
++ break;
++ case gcvHAL_IMPORT_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Import(Kernel,
++ Interface->u.ImportVideoMemory.name,
++ &Interface->u.ImportVideoMemory.handle));
++ gcmkONERROR(gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ gcmINT2PTR(Interface->u.ImportVideoMemory.handle),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_NAME_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Name(Kernel,
++ Interface->u.NameVideoMemory.handle,
++ &Interface->u.NameVideoMemory.name));
++ break;
++
++ case gcvHAL_DATABASE:
++ gcmkONERROR(gckKERNEL_QueryDatabase(Kernel, processID, Interface));
++ break;
++ case gcvHAL_SHBUF:
++ {
++ gctSHBUF shBuf;
++ gctPOINTER uData;
++ gctUINT32 bytes;
++
++ switch (Interface->u.ShBuf.command)
++ {
++ case gcvSHBUF_CREATE:
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Create. */
++ gcmkONERROR(gckKERNEL_CreateShBuffer(Kernel, bytes, &shBuf));
++
++ Interface->u.ShBuf.id = gcmPTR_TO_UINT64(shBuf);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_DESTROY:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Check db first to avoid illegal destroy in the process. */
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf));
++
++ gcmkONERROR(gckKERNEL_DestroyShBuffer(Kernel, shBuf));
++ break;
++
++ case gcvSHBUF_MAP:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Map for current process access. */
++ gcmkONERROR(gckKERNEL_MapShBuffer(Kernel, shBuf));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_WRITE:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Write. */
++ gcmkONERROR(
++ gckKERNEL_WriteShBuffer(Kernel, shBuf, uData, bytes));
++ break;
++
++ case gcvSHBUF_READ:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Read. */
++ gcmkONERROR(
++ gckKERNEL_ReadShBuffer(Kernel,
++ shBuf,
++ uData,
++ bytes,
++ &bytes));
++
++ /* Return copied size. */
++ Interface->u.ShBuf.bytes = bytes;
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++ default:
++ /* Invalid command. */
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++OnError:
++ /* Save status. */
++ kernelInterface->status = status;
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryCommandBuffer
++**
++** Query command buffer attributes.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsCOMMAND_BUFFER_INFO_PTR Information
++** Pointer to the information structure to receive buffer attributes.
++*/
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=0x%x",
++ Kernel, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get the information. */
++ status = gckVGCOMMAND_QueryCommandBuffer(Kernel->vg->command, Information);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_vg.h linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_vg.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_vg.h 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,85 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_vg_h_
++#define __gc_hal_kernel_vg_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel_hardware.h"
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckKERNEL object. */
++struct _gckVGKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* Pointer to gckINTERRUPT object. */
++ gckVGINTERRUPT interrupt;
++
++ /* Pointer to gckCOMMAND object. */
++ gckVGCOMMAND command;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckVGMMU mmu;
++
++ gckKERNEL kernel;
++};
++
++/* gckMMU object. */
++struct _gckVGMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER mutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctPOINTER pageTableLogical;
++
++ /* Allocation index. */
++ gctUINT32 entryCount;
++ gctUINT32 entry;
++};
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_video_memory.c linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_video_memory.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/gc_hal_kernel_video_memory.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/gc_hal_kernel_video_memory.c 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1,2734 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_VIDMEM
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _Split
++**
++** Split a node on the required byte boundary.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the node to split.
++**
++** gctSIZE_T Bytes
++** Number of bytes to keep in the node.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gctBOOL
++** gcvTRUE if the node was split successfully, or gcvFALSE if there is an
++** error.
++**
++*/
++static gctBOOL
++_Split(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctPOINTER pointer = gcvNULL;
++
++ /* Make sure the byte boundary makes sense. */
++ if ((Bytes <= 0) || (Bytes > Node->VidMem.bytes))
++ {
++ return gcvFALSE;
++ }
++
++ /* Allocate a new gcuVIDMEM_NODE object. */
++ if (gcmIS_ERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(gcuVIDMEM_NODE),
++ &pointer)))
++ {
++ /* Error. */
++ return gcvFALSE;
++ }
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE structure. */
++ node->VidMem.offset = Node->VidMem.offset + Bytes;
++ node->VidMem.bytes = Node->VidMem.bytes - Bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.locked = 0;
++ node->VidMem.memory = Node->VidMem.memory;
++ node->VidMem.pool = Node->VidMem.pool;
++ node->VidMem.physical = Node->VidMem.physical;
++
++ /* Insert node behind specified node. */
++ node->VidMem.next = Node->VidMem.next;
++ node->VidMem.prev = Node;
++ Node->VidMem.next = node->VidMem.next->VidMem.prev = node;
++
++ /* Insert free node behind specified node. */
++ node->VidMem.nextFree = Node->VidMem.nextFree;
++ node->VidMem.prevFree = Node;
++ Node->VidMem.nextFree = node->VidMem.nextFree->VidMem.prevFree = node;
++
++ /* Adjust size of specified node. */
++ Node->VidMem.bytes = Bytes;
++
++ /* Success. */
++ return gcvTRUE;
++}
++
++/*******************************************************************************
++**
++** _Merge
++**
++** Merge two adjacent nodes together.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the first of the two nodes to merge.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++*/
++static gceSTATUS
++_Merge(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gceSTATUS status;
++
++ /* Save pointer to next node. */
++ node = Node->VidMem.next;
++
++ /* This is a good time to make sure the heap is not corrupted. */
++ if (Node->VidMem.offset + Node->VidMem.bytes != node->VidMem.offset)
++ {
++ /* Corrupted heap. */
++ gcmkASSERT(
++ Node->VidMem.offset + Node->VidMem.bytes == node->VidMem.offset);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++
++ /* Adjust byte count. */
++ Node->VidMem.bytes += node->VidMem.bytes;
++
++ /* Unlink next node from linked list. */
++ Node->VidMem.next = node->VidMem.next;
++ Node->VidMem.nextFree = node->VidMem.nextFree;
++
++ Node->VidMem.next->VidMem.prev =
++ Node->VidMem.nextFree->VidMem.prevFree = Node;
++
++ /* Free next node. */
++ status = gcmkOS_SAFE_FREE(Os, node);
++ return status;
++}
++
++/******************************************************************************\
++******************************* gckVIDMEM API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVIDMEM_ConstructVirtual
++**
++** Construct a new gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T Bytes
++** Number of byte to allocate.
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that receives the gcuVIDMEM_NODE union pointer.
++*/
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("Kernel=0x%x Flag=%x Bytes=%lu", Kernel, Flag, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate an gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union for virtual memory. */
++ node->Virtual.kernel = Kernel;
++ node->Virtual.contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS;
++ node->Virtual.logical = gcvNULL;
++#if gcdENABLE_VG
++ node->Virtual.kernelVirtual = gcvNULL;
++#endif
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ node->Virtual.lockeds[i] = 0;
++ node->Virtual.pageTables[i] = gcvNULL;
++ node->Virtual.lockKernels[i] = gcvNULL;
++ }
++
++ gcmkONERROR(gckOS_GetProcessID(&node->Virtual.processID));
++
++ /* Allocate the virtual memory. */
++ gcmkONERROR(
++ gckOS_AllocatePagedMemoryEx(os,
++ Flag,
++ node->Virtual.bytes = Bytes,
++ &node->Virtual.gid,
++ &node->Virtual.physical));
++
++ /* Return pointer to the gcuVIDMEM_NODE union. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Created virtual node 0x%x for %u bytes @ 0x%x",
++ node, Bytes, node->Virtual.physical);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Free the structure. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_DestroyVirtual
++**
++** Destroy an gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gckOS os;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Node->Virtual.kernel, gcvOBJ_KERNEL);
++
++ /* Extact the gckOS object pointer. */
++ os = Node->Virtual.kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Delete the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, Node));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Construct
++**
++** Construct a new gckVIDMEM object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 BaseAddress
++** Base address for the video memory heap.
++**
++** gctSIZE_T Bytes
++** Number of bytes in the video memory heap.
++**
++** gctSIZE_T Threshold
++** Minimum number of bytes beyond am allocation before the node is
++** split. Can be used as a minimum alignment requirement.
++**
++** gctSIZE_T BankSize
++** Number of bytes per physical memory bank. Used by bank
++** optimization.
++**
++** OUTPUT:
++**
++** gckVIDMEM * Memory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object.
++*/
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T BankSize,
++ OUT gckVIDMEM * Memory
++ )
++{
++ gckVIDMEM memory = gcvNULL;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctINT i, banks = 0;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 heapBytes;
++ gctUINT32 bankSize;
++
++ gcmkHEADER_ARG("Os=0x%x BaseAddress=%08x Bytes=%lu Threshold=%lu "
++ "BankSize=%lu",
++ Os, BaseAddress, Bytes, Threshold, BankSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ gcmkSAFECASTSIZET(heapBytes, Bytes);
++ gcmkSAFECASTSIZET(bankSize, BankSize);
++
++ /* Allocate the gckVIDMEM object. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct _gckVIDMEM), &pointer));
++
++ memory = pointer;
++
++ /* Initialize the gckVIDMEM object. */
++ memory->object.type = gcvOBJ_VIDMEM;
++ memory->os = Os;
++
++ /* Set video memory heap information. */
++ memory->baseAddress = BaseAddress;
++ memory->bytes = heapBytes;
++ memory->freeBytes = heapBytes;
++ memory->threshold = Threshold;
++ memory->mutex = gcvNULL;
++
++ BaseAddress = 0;
++
++ /* Walk all possible banks. */
++ for (i = 0; i < gcmCOUNTOF(memory->sentinel); ++i)
++ {
++ gctUINT32 bytes;
++
++ if (BankSize == 0)
++ {
++ /* Use all bytes for the first bank. */
++ bytes = heapBytes;
++ }
++ else
++ {
++ /* Compute number of bytes for this bank. */
++ bytes = gcmALIGN(BaseAddress + 1, bankSize) - BaseAddress;
++
++ if (bytes > heapBytes)
++ {
++ /* Make sure we don't exceed the total number of bytes. */
++ bytes = heapBytes;
++ }
++ }
++
++ if (bytes == 0)
++ {
++ /* Mark heap is not used. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = gcvNULL;
++ continue;
++ }
++
++ /* Allocate one gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union. */
++ node->VidMem.memory = memory;
++
++ node->VidMem.next =
++ node->VidMem.prev =
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = &memory->sentinel[i];
++
++ node->VidMem.offset = BaseAddress;
++ node->VidMem.bytes = bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.physical = 0;
++ node->VidMem.pool = gcvPOOL_UNKNOWN;
++
++ node->VidMem.locked = 0;
++
++#if gcdENABLE_VG
++ node->VidMem.kernelVirtual = gcvNULL;
++#endif
++
++ /* Initialize the linked list of nodes. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = node;
++
++ /* Mark sentinel. */
++ memory->sentinel[i].VidMem.bytes = 0;
++
++ /* Adjust address for next bank. */
++ BaseAddress += bytes;
++ heapBytes -= bytes;
++ banks ++;
++ }
++
++ /* Assign all the bank mappings. */
++ memory->mapping[gcvSURF_RENDER_TARGET] = banks - 1;
++ memory->mapping[gcvSURF_BITMAP] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_DEPTH] = banks - 1;
++ memory->mapping[gcvSURF_HIERARCHICAL_DEPTH] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TEXTURE] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_VERTEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_INDEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TILE_STATUS] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TYPE_UNKNOWN] = 0;
++
++#if gcdENABLE_VG
++ memory->mapping[gcvSURF_IMAGE] = 0;
++ memory->mapping[gcvSURF_MASK] = 0;
++ memory->mapping[gcvSURF_SCISSOR] = 0;
++#endif
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] INDEX: bank %d",
++ memory->mapping[gcvSURF_INDEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] VERTEX: bank %d",
++ memory->mapping[gcvSURF_VERTEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TEXTURE: bank %d",
++ memory->mapping[gcvSURF_TEXTURE]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] RENDER_TARGET: bank %d",
++ memory->mapping[gcvSURF_RENDER_TARGET]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] DEPTH: bank %d",
++ memory->mapping[gcvSURF_DEPTH]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TILE_STATUS: bank %d",
++ memory->mapping[gcvSURF_TILE_STATUS]);
++
++ /* Allocate the mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &memory->mutex));
++
++ /* Return pointer to the gckVIDMEM object. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%x", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (memory != gcvNULL)
++ {
++ if (memory->mutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, memory->mutex));
++ }
++
++ for (i = 0; i < banks; ++i)
++ {
++ /* Free the heap. */
++ gcmkASSERT(memory->sentinel[i].VidMem.next != gcvNULL);
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory->sentinel[i].VidMem.next));
++ }
++
++ /* Free the object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Destroy
++**
++** Destroy an gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ )
++{
++ gcuVIDMEM_NODE_PTR node, next;
++ gctINT i;
++
++ gcmkHEADER_ARG("Memory=0x%x", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++
++ /* Walk all sentinels. */
++ for (i = 0; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ /* Bail out of the heap is not used. */
++ if (Memory->sentinel[i].VidMem.next == gcvNULL)
++ {
++ break;
++ }
++
++ /* Walk all the nodes until we reach the sentinel. */
++ for (node = Memory->sentinel[i].VidMem.next;
++ node->VidMem.bytes != 0;
++ node = next)
++ {
++ /* Save pointer to the next node. */
++ next = node->VidMem.next;
++
++ /* Free the node. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, node));
++ }
++ }
++
++ /* Free the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Memory->os, Memory->mutex));
++
++ /* Mark the object as unknown. */
++ Memory->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVIDMEM object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, Memory));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_BANK_ALIGNMENT
++
++#if !gcdBANK_BIT_START
++#error gcdBANK_BIT_START not defined.
++#endif
++
++#if !gcdBANK_BIT_END
++#error gcdBANK_BIT_END not defined.
++#endif
++/*******************************************************************************
++** _GetSurfaceBankAlignment
++**
++** Return the required offset alignment required to the make BaseAddress
++** aligned properly.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gcoOS object.
++**
++** gceSURF_TYPE Type
++** Type of allocation.
++**
++** gctUINT32 BaseAddress
++** Base address of current video memory node.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR AlignmentOffset
++** Pointer to a variable that will hold the number of bytes to skip in
++** the current video memory node in order to make the alignment bank
++** aligned.
++*/
++static gceSTATUS
++_GetSurfaceBankAlignment(
++ IN gckKERNEL Kernel,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 BaseAddress,
++ OUT gctUINT32_PTR AlignmentOffset
++ )
++{
++ gctUINT32 bank;
++ /* To retrieve the bank. */
++ static const gctUINT32 bankMask = (0xFFFFFFFF << gcdBANK_BIT_START)
++ ^ (0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ /* To retrieve the bank and all the lower bytes. */
++ static const gctUINT32 byteMask = ~(0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ gcmkHEADER_ARG("Type=%d BaseAddress=0x%x ", Type, BaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(AlignmentOffset != gcvNULL);
++
++ switch (Type)
++ {
++ case gcvSURF_RENDER_TARGET:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the first bank. */
++ *AlignmentOffset = (bank == 0) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + 0) - (BaseAddress & byteMask);
++ break;
++
++ case gcvSURF_DEPTH:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the third bank. */
++ *AlignmentOffset = (bank == 2) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + (2 << gcdBANK_BIT_START)) - (BaseAddress & byteMask);
++
++ /* Minimum 256 byte alignment needed for fast_msaa. */
++ if ((gcdBANK_CHANNEL_BIT > 7) ||
++ ((gckHARDWARE_IsFeatureAvailable(Kernel->hardware, gcvFEATURE_FAST_MSAA) != gcvSTATUS_TRUE) &&
++ (gckHARDWARE_IsFeatureAvailable(Kernel->hardware, gcvFEATURE_SMALL_MSAA) != gcvSTATUS_TRUE)))
++ {
++ /* Add a channel offset at the channel bit. */
++ *AlignmentOffset += (1 << gcdBANK_CHANNEL_BIT);
++ }
++ break;
++
++ default:
++ /* no alignment needed. */
++ *AlignmentOffset = 0;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("*AlignmentOffset=%u", *AlignmentOffset);
++ return gcvSTATUS_OK;
++}
++#endif
++
++static gcuVIDMEM_NODE_PTR
++_FindNode(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctINT Bank,
++ IN gctSIZE_T Bytes,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Alignment
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++
++#if gcdENABLE_BANK_ALIGNMENT
++ gctUINT32 bankAlignment;
++ gceSTATUS status;
++#endif
++
++ if (Memory->sentinel[Bank].VidMem.nextFree == gcvNULL)
++ {
++ /* No free nodes left. */
++ return gcvNULL;
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++ /* Walk all free nodes until we have one that is big enough or we have
++ ** reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++ if (node->VidMem.bytes < Bytes)
++ {
++ continue;
++ }
++
++ gcmkONERROR(_GetSurfaceBankAlignment(
++ Kernel,
++ Type,
++ node->VidMem.memory->baseAddress + node->VidMem.offset,
++ &bankAlignment));
++
++ bankAlignment = gcmALIGN(bankAlignment, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0)
++ ? 0
++ : (*Alignment - (node->VidMem.offset % *Alignment));
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment + bankAlignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment + bankAlignment;
++ return node;
++ }
++ }
++#endif
++
++ /* Walk all free nodes until we have one that is big enough or we have
++ reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++ gctUINT offset;
++
++ gctINT modulo;
++
++ gcmkSAFECASTSIZET(offset, node->VidMem.offset);
++
++ modulo = gckMATH_ModuloInt(offset, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0) ? 0 : (*Alignment - modulo);
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment;
++ return node;
++ }
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++OnError:
++#endif
++ /* Not enough memory. */
++ return gcvNULL;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_AllocateLinear
++**
++** Allocate linear memory from the gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctUINT32 Alignment
++** Byte alignment for allocation.
++**
++** gceSURF_TYPE Type
++** Type of surface to allocate (use by bank optimization).
++**
++** gctBOOL Specified
++** If user must use this pool, it should set Specified to gcvTRUE,
++** otherwise allocator may reserve some memory for other usage, such
++** as small block size allocation request.
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that will hold the allocated memory node.
++*/
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctBOOL Specified,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++ gctINT bank, i;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Memory=0x%x Bytes=%lu Alignment=%u Type=%d",
++ Memory, Bytes, Alignment, Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Type < gcvSURF_NUM_TYPES);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Memory->os, Memory->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ if (Bytes > Memory->freeBytes)
++ {
++ /* Not enough memory. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++
++#if gcdSMALL_BLOCK_SIZE
++ if ((Memory->freeBytes < (Memory->bytes/gcdRATIO_FOR_SMALL_MEMORY))
++ && (Bytes >= gcdSMALL_BLOCK_SIZE)
++ && (Specified == gcvFALSE)
++ )
++ {
++ /* The left memory is for small memory.*/
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++#endif
++
++ /* Find the default bank for this surface type. */
++ gcmkASSERT((gctINT) Type < gcmCOUNTOF(Memory->mapping));
++ bank = Memory->mapping[Type];
++ alignment = Alignment;
++
++ /* Find a free node in the default bank. */
++ node = _FindNode(Kernel, Memory, bank, Bytes, Type, &alignment);
++
++ /* Out of memory? */
++ if (node == gcvNULL)
++ {
++ /* Walk all lower banks. */
++ for (i = bank - 1; i >= 0; --i)
++ {
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Kernel, Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ /* Walk all upper banks. */
++ for (i = bank + 1; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ if (Memory->sentinel[i].VidMem.nextFree == gcvNULL)
++ {
++ /* Abort when we reach unused banks. */
++ break;
++ }
++
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Kernel, Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ /* Out of memory. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++
++ /* Do we have an alignment? */
++ if (alignment > 0)
++ {
++ /* Split the node so it is aligned. */
++ if (_Split(Memory->os, node, alignment))
++ {
++ /* Successful split, move to aligned node. */
++ node = node->VidMem.next;
++
++ /* Remove alignment. */
++ alignment = 0;
++ }
++ }
++
++ /* Do we have enough memory after the allocation to split it? */
++ if (node->VidMem.bytes - Bytes > Memory->threshold)
++ {
++ /* Adjust the node size. */
++ _Split(Memory->os, node, Bytes);
++ }
++
++ /* Remove the node from the free list. */
++ node->VidMem.prevFree->VidMem.nextFree = node->VidMem.nextFree;
++ node->VidMem.nextFree->VidMem.prevFree = node->VidMem.prevFree;
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = gcvNULL;
++
++ /* Fill in the information. */
++ node->VidMem.alignment = alignment;
++ node->VidMem.memory = Memory;
++
++ /* Adjust the number of free bytes. */
++ Memory->freeBytes -= node->VidMem.bytes;
++
++#if gcdENABLE_VG
++ node->VidMem.kernelVirtual = gcvNULL;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++
++ /* Return the pointer to the node. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Allocated %u bytes @ 0x%x [0x%08X]",
++ node->VidMem.bytes, node, node->VidMem.offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Free
++**
++** Free an allocated video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Free(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gceSTATUS status;
++ gckKERNEL kernel = gcvNULL;
++ gckVIDMEM memory = gcvNULL;
++ gcuVIDMEM_NODE_PTR node;
++ gctBOOL mutexAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Extract pointer to gckVIDMEM object owning the node. */
++ memory = Node->VidMem.memory;
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(memory->os, memory->mutex, gcvINFINITE));
++
++ mutexAcquired = gcvTRUE;
++
++#if gcdENABLE_VG
++ if (Node->VidMem.kernelVirtual)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "%s(%d) Unmap %x from kernel space.",
++ __FUNCTION__, __LINE__,
++ Node->VidMem.kernelVirtual);
++
++ gcmkVERIFY_OK(
++ gckOS_UnmapPhysical(memory->os,
++ Node->VidMem.kernelVirtual,
++ Node->VidMem.bytes));
++
++ Node->VidMem.kernelVirtual = gcvNULL;
++ }
++#endif
++
++ /* Check if Node is already freed. */
++ if (Node->VidMem.nextFree)
++ {
++ /* Node is alread freed. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ /* Update the number of free bytes. */
++ memory->freeBytes += Node->VidMem.bytes;
++
++ /* Find the next free node. */
++ for (node = Node->VidMem.next;
++ node != gcvNULL && node->VidMem.nextFree == gcvNULL;
++ node = node->VidMem.next) ;
++
++ /* Insert this node in the free list. */
++ Node->VidMem.nextFree = node;
++ Node->VidMem.prevFree = node->VidMem.prevFree;
++
++ Node->VidMem.prevFree->VidMem.nextFree =
++ node->VidMem.prevFree = Node;
++
++ /* Is the next node a free node and not the sentinel? */
++ if ((Node->VidMem.next == Node->VidMem.nextFree)
++ && (Node->VidMem.next->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the next node. */
++ gcmkONERROR(_Merge(memory->os, node = Node));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++
++ /* Is the previous node a free node and not the sentinel? */
++ if ((Node->VidMem.prev == Node->VidMem.prevFree)
++ && (Node->VidMem.prev->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the previous node. */
++ gcmkONERROR(_Merge(memory->os, node = Node->VidMem.prev));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(memory->os, memory->mutex));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Node 0x%x is freed.",
++ Node);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ /* Get gckKERNEL object. */
++ kernel = Node->Virtual.kernel;
++
++ /* Verify the gckKERNEL object pointer. */
++ gcmkVERIFY_OBJECT(kernel, gcvOBJ_KERNEL);
++
++#if gcdENABLE_VG
++ if (Node->Virtual.kernelVirtual)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "%s(%d) Unmap %x from kernel space.",
++ __FUNCTION__, __LINE__,
++ Node->Virtual.kernelVirtual);
++
++ gcmkVERIFY_OK(
++ gckOS_UnmapPhysical(kernel->os,
++ Node->Virtual.kernelVirtual,
++ Node->Virtual.bytes));
++
++ Node->Virtual.kernelVirtual = gcvNULL;
++ }
++#endif
++
++ /* Free the virtual memory. */
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(kernel->os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes));
++
++ /* Destroy the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gckVIDMEM_DestroyVirtual(Node));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutexAcquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ memory->os, memory->mutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if !gcdPROCESS_ADDRESS_SPACE
++/*******************************************************************************
++**
++** _NeedVirtualMapping
++**
++** Whether setup GPU page table for video node.
++**
++** INPUT:
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** gceCORE Core
++** Id of current GPU.
++**
++** OUTPUT:
++** gctBOOL * NeedMapping
++** A pointer hold the result whether Node should be mapping.
++*/
++static gceSTATUS
++_NeedVirtualMapping(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gcuVIDMEM_NODE_PTR Node,
++ OUT gctBOOL * NeedMapping
++)
++{
++ gceSTATUS status;
++ gctUINT32 phys;
++ gctUINT32 end;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctUINT32 baseAddress;
++ gctUINT32 bytes;
++
++ gcmkHEADER_ARG("Node=0x%X", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(NeedMapping != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Core < gcdMAX_GPU_COUNT);
++
++ if (Node->Virtual.contiguous)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ *NeedMapping = gcvFALSE;
++ }
++ else
++#endif
++ {
++ /* Convert logical address into a physical address. */
++ gcmkONERROR(gckOS_UserLogicalToPhysical(
++ Kernel->os, Node->Virtual.logical, &phys
++ ));
++
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++
++ gcmkASSERT(phys >= baseAddress);
++
++ /* Subtract baseAddress to get a GPU address used for programming. */
++ phys -= baseAddress;
++
++ /* If part of region is belong to gcvPOOL_VIRTUAL,
++ ** whole region has to be mapped. */
++ gcmkSAFECASTSIZET(bytes, Node->Virtual.bytes);
++ end = phys + bytes - 1;
++
++ gcmkONERROR(gckHARDWARE_SplitMemory(
++ Kernel->hardware, end, &pool, &offset
++ ));
++
++ *NeedMapping = (pool == gcvPOOL_VIRTUAL);
++ }
++ }
++ else
++ {
++ *NeedMapping = gcvTRUE;
++ }
++
++ gcmkFOOTER_ARG("*NeedMapping=%d", *NeedMapping);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++gcsGPU_MAP_PTR
++_FindGPUMap(
++ IN gcsGPU_MAP_PTR Head,
++ IN gctINT ProcessID
++ )
++{
++ gcsGPU_MAP_PTR map = Head;
++
++ while (map)
++ {
++ if (map->pid == ProcessID)
++ {
++ return map;
++ }
++
++ map = map->next;
++ }
++
++ return gcvNULL;
++}
++
++gcsGPU_MAP_PTR
++_CreateGPUMap(
++ IN gckOS Os,
++ IN gcsGPU_MAP_PTR *Head,
++ IN gcsGPU_MAP_PTR *Tail,
++ IN gctINT ProcessID
++ )
++{
++ gcsGPU_MAP_PTR gpuMap;
++ gctPOINTER pointer = gcvNULL;
++
++ gckOS_Allocate(Os, sizeof(gcsGPU_MAP), &pointer);
++
++ if (pointer == gcvNULL)
++ {
++ return gcvNULL;
++ }
++
++ gpuMap = pointer;
++
++ gckOS_ZeroMemory(pointer, sizeof(gcsGPU_MAP));
++
++ gpuMap->pid = ProcessID;
++
++ if (!*Head)
++ {
++ *Head = *Tail = gpuMap;
++ }
++ else
++ {
++ gpuMap->prev = *Tail;
++ (*Tail)->next = gpuMap;
++ *Tail = gpuMap;
++ }
++
++ return gpuMap;
++}
++
++void
++_DestroyGPUMap(
++ IN gckOS Os,
++ IN gcsGPU_MAP_PTR *Head,
++ IN gcsGPU_MAP_PTR *Tail,
++ IN gcsGPU_MAP_PTR gpuMap
++ )
++{
++
++ if (gpuMap == *Head)
++ {
++ if ((*Head = gpuMap->next) == gcvNULL)
++ {
++ *Tail = gcvNULL;
++ }
++ }
++ else
++ {
++ gpuMap->prev->next = gpuMap->next;
++ if (gpuMap == *Tail)
++ {
++ *Tail = gpuMap->prev;
++ }
++ else
++ {
++ gpuMap->next->prev = gpuMap->prev;
++ }
++ }
++
++ gcmkOS_SAFE_FREE(Os, gpuMap);
++}
++#endif
++
++/*******************************************************************************
++**
++** gckVIDMEM_Lock
++**
++** Lock a video memory node and return its hardware specific address.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable that will hold the hardware specific address.
++**
++** gctUINT32 * PhysicalAddress
++** Pointer to a variable that will hold the bus address of a contiguous
++** video node.
++*/
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address,
++ OUT gctUINT32 * Gid,
++ OUT gctUINT64 * PhysicalAddress
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL locked = gcvFALSE;
++ gckOS os = gcvNULL;
++#if !gcdPROCESS_ADDRESS_SPACE
++ gctBOOL needMapping = gcvFALSE;
++#endif
++ gctUINT32 baseAddress;
++ gctUINT32 physicalAddress;
++ gcuVIDMEM_NODE_PTR node = Node->node;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ if ((node == gcvNULL)
++ || (node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Node->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /**************************** Video Memory ********************************/
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ gctUINT32 offset;
++
++ if (Cacheable == gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Increment the lock count. */
++ node->VidMem.locked ++;
++
++ /* Return the physical address of the node. */
++ gcmkSAFECASTSIZET(offset, node->VidMem.offset);
++
++ *Address = node->VidMem.memory->baseAddress
++ + offset
++ + node->VidMem.alignment;
++
++ physicalAddress = *Address;
++
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ /* Convert physical to GPU address for old mmu. */
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++ gcmkASSERT(*Address > baseAddress);
++ *Address -= baseAddress;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(
++ Kernel->os,
++ *Address,
++ Address
++ ));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Locked node 0x%x (%d) @ 0x%08X",
++ node,
++ node->VidMem.locked,
++ *Address);
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++
++ *Gid = node->Virtual.gid;
++
++#if gcdPAGED_MEMORY_CACHEABLE
++ /* Force video memory cacheable. */
++ Cacheable = gcvTRUE;
++#endif
++
++ gcmkONERROR(
++ gckOS_LockPages(os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ Cacheable,
++ &node->Virtual.logical,
++ &node->Virtual.pageCount));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ os,
++ node->Virtual.logical,
++ &physicalAddress
++ ));
++
++#if gcdENABLE_VG
++ node->Virtual.physicalAddress = physicalAddress;
++#endif
++
++#if !gcdPROCESS_ADDRESS_SPACE
++ /* Increment the lock count. */
++ if (node->Virtual.lockeds[Kernel->core] ++ == 0)
++ {
++ locked = gcvTRUE;
++
++ gcmkONERROR(_NeedVirtualMapping(Kernel, Kernel->core, node, &needMapping));
++
++ if (needMapping == gcvFALSE)
++ {
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(gckVGHARDWARE_ConvertLogical(
++ Kernel->vg->hardware,
++ node->Virtual.logical,
++ gcvTRUE,
++ &node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ node->Virtual.logical,
++ gcvTRUE,
++ &node->Virtual.addresses[Kernel->core]));
++ }
++ }
++ else
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckVGMMU_AllocatePages(Kernel->vg->mmu,
++ node->Virtual.pageCount,
++ &node->Virtual.pageTables[Kernel->core],
++ &node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckMMU_AllocatePagesEx(Kernel->mmu,
++ node->Virtual.pageCount,
++ node->Virtual.type,
++ &node->Virtual.pageTables[Kernel->core],
++ &node->Virtual.addresses[Kernel->core]));
++ }
++
++ node->Virtual.lockKernels[Kernel->core] = Kernel;
++
++ /* Map the pages. */
++ gcmkONERROR(
++ gckOS_MapPagesEx(os,
++ Kernel->core,
++ node->Virtual.physical,
++ node->Virtual.pageCount,
++ node->Virtual.addresses[Kernel->core],
++ node->Virtual.pageTables[Kernel->core]));
++
++#if gcdENABLE_VG
++ if (Kernel->core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Kernel->vg->mmu));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckMMU_Flush(Kernel->mmu, node->Virtual.type));
++ }
++ }
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Mapped virtual node 0x%x to 0x%08X",
++ node,
++ node->Virtual.addresses[Kernel->core]);
++ }
++
++ /* Return hardware address. */
++ *Address = node->Virtual.addresses[Kernel->core];
++#endif
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++
++ *PhysicalAddress = (gctUINT64)physicalAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (locked)
++ {
++ if (node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++ node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++
++ /* Unlock the pages. */
++ gcmkVERIFY_OK(
++ gckOS_UnlockPages(os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ node->Virtual.logical
++ ));
++
++ node->Virtual.lockeds[Kernel->core]--;
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Unlock
++**
++** Unlock a video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a locked gcuVIDMEM_NODE union.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable specifying whether the surface should be
++** unlocked asynchroneously or not.
++**
++** OUTPUT:
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable receiving the number of bytes used in the
++** command buffer specified by 'Commands'. If gcvNULL, there is no
++** command buffer.
++*/
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ )
++{
++ gceSTATUS status;
++ gckOS os = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gcuVIDMEM_NODE_PTR node = Node->node;
++
++ gcmkHEADER_ARG("Node=0x%x Type=%d *Asynchroneous=%d",
++ Node, Type, gcmOPT_VALUE(Asynchroneous));
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Verify the arguments. */
++ if ((node == gcvNULL)
++ || (node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Node->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /**************************** Video Memory ********************************/
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (node->VidMem.locked <= 0)
++ {
++ /* The surface was not locked. */
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ if (Asynchroneous != gcvNULL)
++ {
++ /* Schedule an event to sync with GPU. */
++ *Asynchroneous = gcvTRUE;
++ }
++ else
++ {
++ /* Decrement the lock count. */
++ node->VidMem.locked --;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unlocked node 0x%x (%d)",
++ node,
++ node->VidMem.locked);
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++
++
++ if (Asynchroneous == gcvNULL)
++ {
++#if !gcdPROCESS_ADDRESS_SPACE
++ if (node->Virtual.lockeds[Kernel->core] == 0)
++ {
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ /* Decrement lock count. */
++ -- node->Virtual.lockeds[Kernel->core];
++
++ /* See if we can unlock the resources. */
++ if (node->Virtual.lockeds[Kernel->core] == 0)
++ {
++ /* Free the page table. */
++ if (node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(
++ gckMMU_FreePages(Kernel->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++
++ gcmkONERROR(gckOS_UnmapPages(
++ Kernel->os,
++ node->Virtual.pageCount,
++ node->Virtual.addresses[Kernel->core]
++ ));
++
++ /* Mark page table as freed. */
++ node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unmapped virtual node 0x%x from 0x%08X",
++ node, node->Virtual.addresses[Kernel->core]);
++#endif
++
++ }
++
++ else
++ {
++ gcmkONERROR(
++ gckOS_UnlockPages(os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ node->Virtual.logical));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Scheduled unlock for virtual node 0x%x",
++ node);
++
++ /* Schedule the surface to be unlocked. */
++ *Asynchroneous = gcvTRUE;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Asynchroneous=%d", gcmOPT_VALUE(Asynchroneous));
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckVIDMEM_Node_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ OUT gctUINT32 *Address
++ )
++{
++ gceSTATUS status;
++ gckOS os;
++ gcuVIDMEM_NODE_PTR node = Node->node;
++ gcsGPU_MAP_PTR gpuMap;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctUINT32 phys = gcvINVALID_ADDRESS;
++ gctUINT32 processID;
++ gcsLOCK_INFO_PTR lockInfo;
++ gctUINT32 pageCount;
++ gckMMU mmu;
++ gctUINT32 i;
++ gctUINT32_PTR pageTableEntry;
++ gctUINT32 offset = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Node = %x", Node);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu));
++
++ gcmkONERROR(gckOS_AcquireMutex(os, Node->mapMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get map information for current process. */
++ gpuMap = _FindGPUMap(Node->mapHead, processID);
++
++ if (gpuMap == gcvNULL)
++ {
++ gpuMap = _CreateGPUMap(os, &Node->mapHead, &Node->mapTail, processID);
++
++ if (gpuMap == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ lockInfo = &gpuMap->lockInfo;
++
++ if (lockInfo->lockeds[Kernel->core] ++ == 0)
++ {
++ /* Get necessary information. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ phys = node->VidMem.memory->baseAddress
++ + node->VidMem.offset
++ + node->VidMem.alignment;
++
++ /* GPU page table use 4K page. */
++ pageCount = ((phys + node->VidMem.bytes + 4096 - 1) >> 12)
++ - (phys >> 12);
++
++ offset = phys & 0xFFF;
++ }
++ else
++ {
++ pageCount = node->Virtual.pageCount;
++ physical = node->Virtual.physical;
++ }
++
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(gckMMU_AllocatePages(
++ mmu,
++ pageCount,
++ &lockInfo->pageTables[Kernel->core],
++ &lockInfo->GPUAddresses[Kernel->core]));
++
++ /* Record MMU from which pages are allocated. */
++ lockInfo->lockMmus[Kernel->core] = mmu;
++
++ pageTableEntry = lockInfo->pageTables[Kernel->core];
++
++ /* Fill page table entries. */
++ if (phys != gcvINVALID_ADDRESS)
++ {
++ gctUINT32 address = lockInfo->GPUAddresses[Kernel->core];
++ for (i = 0; i < pageCount; i++)
++ {
++ gckMMU_GetPageEntry(mmu, address, &pageTableEntry);
++ gckMMU_SetPage(mmu, phys & 0xFFFFF000, pageTableEntry);
++ phys += 4096;
++ address += 4096;
++ pageTableEntry += 1;
++ }
++ }
++ else
++ {
++ gctUINT32 address = lockInfo->GPUAddresses[Kernel->core];
++ gcmkASSERT(physical != gcvNULL);
++ gcmkONERROR(gckOS_MapPagesEx(os,
++ Kernel->core,
++ physical,
++ pageCount,
++ address,
++ pageTableEntry));
++ }
++
++ gcmkONERROR(gckMMU_Flush(mmu));
++ }
++
++ *Address = lockInfo->GPUAddresses[Kernel->core] + offset;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mapMutex));
++ acquired = gcvFALSE;
++
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mapMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_NODE_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsGPU_MAP_PTR gpuMap;
++ gcsLOCK_INFO_PTR lockInfo;
++ gckMMU mmu;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 pageCount;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%08X, Node = %x, ProcessID=%d",
++ Kernel, Node, ProcessID);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Node->mapMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get map information for current process. */
++ gpuMap = _FindGPUMap(Node->mapHead, ProcessID);
++
++ if (gpuMap == gcvNULL)
++ {
++ /* No mapping for this process. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ lockInfo = &gpuMap->lockInfo;
++
++ if (--lockInfo->lockeds[Kernel->core] == 0)
++ {
++ node = Node->node;
++
++ /* Get necessary information. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ gctUINT32 phys = node->VidMem.memory->baseAddress
++ + node->VidMem.offset
++ + node->VidMem.alignment;
++
++ /* GPU page table use 4K page. */
++ pageCount = ((phys + node->VidMem.bytes + 4096 - 1) >> 12)
++ - (phys >> 12);
++ }
++ else
++ {
++ pageCount = node->Virtual.pageCount;
++ }
++
++ /* Get MMU which allocates pages. */
++ mmu = lockInfo->lockMmus[Kernel->core];
++
++ /* Free virtual spaces in page table. */
++ gcmkVERIFY_OK(gckMMU_FreePagesEx(
++ mmu,
++ lockInfo->GPUAddresses[Kernel->core],
++ pageCount
++ ));
++
++ _DestroyGPUMap(Kernel->os, &Node->mapHead, &Node->mapTail, gpuMap);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Node->mapMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Node->mapMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckVIDMEM_HANDLE_Allocate
++**
++** Allocate a handle for a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gckVIDMEM_NODE Node
++** Pointer to a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Handle
++** Pointer to a variable receiving a handle represent this
++** gckVIDMEM_NODE in userspace.
++*/
++static gceSTATUS
++gckVIDMEM_HANDLE_Allocate(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ OUT gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID = 0;
++ gctPOINTER pointer = gcvNULL;
++ gctPOINTER handleDatabase = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctUINT32 handle = 0;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gckOS os = Kernel->os;
++
++ gcmkHEADER_ARG("Kernel=0x%X, Node=0x%X", Kernel, Node);
++
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate a gckVIDMEM_HANDLE object. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsVIDMEM_HANDLE), &pointer));
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsVIDMEM_HANDLE)));
++
++ handleObject = pointer;
++
++ gcmkONERROR(gckOS_AtomConstruct(os, &handleObject->reference));
++
++ /* Set default reference count to 1. */
++ gckOS_AtomSet(os, handleObject->reference, 1);
++
++ gcmkVERIFY_OK(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel,
++ processID,
++ &handleDatabase,
++ &mutex));
++
++ /* Allocate a handle for this object. */
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(handleDatabase, handleObject, &handle));
++
++ handleObject->node = Node;
++ handleObject->handle = handle;
++
++ *Handle = handle;
++
++ gcmkFOOTER_ARG("*Handle=%d", *Handle);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (handleObject != gcvNULL)
++ {
++ if (handleObject->reference != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, handleObject->reference));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, handleObject));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckVIDMEM_NODE_Reference(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node
++ )
++{
++ gctINT32 oldValue;
++ gcmkHEADER_ARG("Kernel=0x%X Node=0x%X", Kernel, Node);
++
++ gckOS_AtomIncrement(Kernel->os, Node->reference, &oldValue);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_Reference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gctPOINTER database = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctINT32 oldValue = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Handle=%d ProcessID=%d", Handle, ProcessID);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel, ProcessID, &database, &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Translate handle to gckVIDMEM_HANDLE object. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject));
++
++ /* Increase the reference count. */
++ gckOS_AtomIncrement(Kernel->os, handleObject->reference, &oldValue);
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ )
++{
++ gceSTATUS status;
++ gctPOINTER handleDatabase = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctINT32 oldValue = 0;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Handle=%d ProcessID=%d", Handle, ProcessID);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel,
++ ProcessID,
++ &handleDatabase,
++ &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Translate handle to gckVIDMEM_HANDLE. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(handleDatabase, Handle, (gctPOINTER *)&handleObject));
++
++ gckOS_AtomDecrement(Kernel->os, handleObject->reference, &oldValue);
++
++ if (oldValue == 1)
++ {
++ /* Remove handle from database if this is the last reference. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(handleDatabase, Handle));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ if (oldValue == 1)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, handleObject->reference));
++ gcmkOS_SAFE_FREE(Kernel->os, handleObject);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_LookupAndReference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER database = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctUINT32 processID = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle);
++
++ gckOS_GetProcessID(&processID);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel, processID, &database, &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Translate handle to gckVIDMEM_HANDLE object. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject));
++
++ /* Get gckVIDMEM_NODE object. */
++ node = handleObject->node;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ /* Reference this gckVIDMEM_NODE object. */
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Reference(Kernel, node));
++
++ /* Return result. */
++ *Node = node;
++
++ gcmkFOOTER_ARG("*Node=%X", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_Lookup(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER database = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ProcessID=%d Handle=%d",
++ Kernel, ProcessID, Handle);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel, ProcessID, &database, &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject));
++
++ node = handleObject->node;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ *Node = node;
++
++ gcmkFOOTER_ARG("*Node=%X", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_Allocate
++**
++** Allocate a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** gctUINT32 * Handle
++** Pointer to a variable receiving a handle represent this
++** gckVIDMEM_NODE in userspace.
++*/
++gceSTATUS
++gckVIDMEM_NODE_Allocate(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR VideoNode,
++ IN gceSURF_TYPE Type,
++ IN gcePOOL Pool,
++ IN gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 handle = 0;
++ gckOS os = Kernel->os;
++
++ gcmkHEADER_ARG("Kernel=0x%X VideoNode=0x%X", Kernel, VideoNode);
++
++ /* Construct a node. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsVIDMEM_NODE), &pointer));
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsVIDMEM_NODE)));
++
++ node = pointer;
++
++ node->node = VideoNode;
++ node->type = Type;
++ node->pool = Pool;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckOS_CreateMutex(os, &node->mapMutex));
++#endif
++
++ gcmkONERROR(gckOS_AtomConstruct(os, &node->reference));
++
++ gcmkONERROR(gckOS_CreateMutex(os, &node->mutex));
++
++ /* Reference is 1 by default . */
++ gckVIDMEM_NODE_Reference(Kernel, node);
++
++ /* Create a handle to represent this node. */
++ gcmkONERROR(gckVIDMEM_HANDLE_Allocate(Kernel, node, &handle));
++
++ *Handle = handle;
++
++ gcmkFOOTER_ARG("*Handle=%d", *Handle);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (node != gcvNULL)
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ if (node->mapMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, node->mapMutex));
++ }
++#endif
++
++ if (node->mutex)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, node->mutex));
++ }
++
++ if (node->reference != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, node->reference));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_NODE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node
++ )
++{
++ gctINT32 oldValue = 0;
++ gctPOINTER database = Kernel->db->nameDatabase;
++ gctPOINTER mutex = Kernel->db->nameDatabaseMutex;
++
++ gcmkHEADER_ARG("Kernel=0x%X Node=0x%X", Kernel, Node);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++
++ gcmkVERIFY_OK(gckOS_AtomDecrement(Kernel->os, Node->reference, &oldValue));
++
++ if (oldValue == 1 && Node->name)
++ {
++ /* Free name if exists. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Node->name));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++
++ if (oldValue == 1)
++ {
++ /* Free gcuVIDMEM_NODE. */
++ gcmkVERIFY_OK(gckVIDMEM_Free(Kernel, Node->node));
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Node->reference));
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Node->mapMutex));
++#endif
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Node->mutex));
++ gcmkOS_SAFE_FREE(Kernel->os, Node);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_Name
++**
++** Naming a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Handle
++** Handle to a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Name
++** Pointer to a variable receiving a name which can be pass to another
++** process.
++*/
++gceSTATUS
++gckVIDMEM_NODE_Name(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ IN gctUINT32 * Name
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctUINT32 name = 0;
++ gctUINT32 processID = 0;
++ gctPOINTER database = Kernel->db->nameDatabase;
++ gctPOINTER mutex = Kernel->db->nameDatabaseMutex;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL referenced = gcvFALSE;
++ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(gckVIDMEM_HANDLE_LookupAndReference(Kernel, Handle, &node));
++ referenced = gcvTRUE;
++
++ if (node->name == 0)
++ {
++ /* Name this node. */
++ gcmkONERROR(gckKERNEL_AllocateIntegerId(database, node, &name));
++ node->name = name;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++
++ if(node)
++ {
++ *Name = node->name;
++ }
++
++ gcmkFOOTER_ARG("*Name=%d", *Name);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (referenced)
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++ }
++
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_Import
++**
++** Import a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Name
++** Name of a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Handle
++** Pointer to a variable receiving a handle represent this
++** gckVIDMEM_NODE in userspace.
++*/
++gceSTATUS
++gckVIDMEM_NODE_Import(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name,
++ IN gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER database = Kernel->db->nameDatabase;
++ gctPOINTER mutex = Kernel->db->nameDatabaseMutex;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL referenced = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name);
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Lookup in database to get the node. */
++ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, (gctPOINTER *)&node));
++
++ /* Reference the node. */
++ gcmkONERROR(gckVIDMEM_NODE_Reference(Kernel, node));
++ referenced = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ /* Allocate a handle for current process. */
++ gcmkONERROR(gckVIDMEM_HANDLE_Allocate(Kernel, node, Handle));
++
++ gcmkFOOTER_ARG("*Handle=%d", *Handle);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (referenced)
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++ }
++
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++typedef struct _gcsVIDMEM_NODE_FDPRIVATE
++{
++ gcsFDPRIVATE base;
++ gckKERNEL kernel;
++ gckVIDMEM_NODE node;
++}
++gcsVIDMEM_NODE_FDPRIVATE;
++
++
++static gctINT
++_ReleaseFdPrivate(
++ gcsFDPRIVATE_PTR FdPrivate
++ )
++{
++ /* Cast private info. */
++ gcsVIDMEM_NODE_FDPRIVATE * private = (gcsVIDMEM_NODE_FDPRIVATE *) FdPrivate;
++
++ gckVIDMEM_NODE_Dereference(private->kernel, private->node);
++ gckOS_Free(private->kernel->os, private);
++
++ return 0;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_GetFd
++**
++** Attach a gckVIDMEM_NODE object to a native fd.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Handle
++** Handle to a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Fd
++** Pointer to a variable receiving a native fd from os.
++*/
++gceSTATUS
++gckVIDMEM_NODE_GetFd(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gctINT * Fd
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctBOOL referenced = gcvFALSE;
++ gcsVIDMEM_NODE_FDPRIVATE * fdPrivate = gcvNULL;
++ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle);
++
++ /* Query and reference handle. */
++ gcmkONERROR(gckVIDMEM_HANDLE_LookupAndReference(Kernel, Handle, &node));
++ referenced = gcvTRUE;
++
++ /* Allocate memory for private info. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(gcsVIDMEM_NODE_FDPRIVATE),
++ (gctPOINTER *)&fdPrivate
++ ));
++
++ fdPrivate->base.release = _ReleaseFdPrivate;
++ fdPrivate->kernel = Kernel;
++ fdPrivate->node = node;
++
++ /* Allocated fd owns a reference. */
++ gcmkONERROR(gckOS_GetFd("vidmem", &fdPrivate->base, Fd));
++
++ gcmkFOOTER_ARG("*Fd=%d", *Fd);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (referenced)
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++ }
++
++ if (fdPrivate)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, fdPrivate));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/aqHal.h linux-3.14.72/drivers/gpu/galcore/inc/aqHal.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/aqHal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/aqHal.h 2016-06-19 22:11:55.149150242 +0200
+@@ -0,0 +1 @@
++#include "HAL/gc_hal.h"
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_base.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_base.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_base.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_base.h 2016-06-19 22:11:55.153149980 +0200
+@@ -0,0 +1,5538 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_base_h_
++#define __gc_hal_base_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++#include "gc_hal_dump.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckOS * gckOS;
++typedef struct _gcoHAL * gcoHAL;
++typedef struct _gcoOS * gcoOS;
++typedef struct _gco2D * gco2D;
++typedef struct gcsATOM * gcsATOM_PTR;
++
++#if gcdENABLE_3D
++typedef struct _gco3D * gco3D;
++typedef struct _gcoCL * gcoCL;
++typedef struct _gcsFAST_FLUSH * gcsFAST_FLUSH_PTR;
++#endif
++
++typedef struct _gcoSURF * gcoSURF;
++typedef struct _gcsSURF_INFO * gcsSURF_INFO_PTR;
++typedef struct _gcsSURF_NODE * gcsSURF_NODE_PTR;
++typedef struct _gcsSURF_FORMAT_INFO * gcsSURF_FORMAT_INFO_PTR;
++typedef struct _gcsPOINT * gcsPOINT_PTR;
++typedef struct _gcsSIZE * gcsSIZE_PTR;
++typedef struct _gcsRECT * gcsRECT_PTR;
++typedef struct _gcsBOUNDARY * gcsBOUNDARY_PTR;
++typedef struct _gcoDUMP * gcoDUMP;
++typedef struct _gcoHARDWARE * gcoHARDWARE;
++typedef union _gcuVIDMEM_NODE * gcuVIDMEM_NODE_PTR;
++typedef struct _gcsVIDMEM_NODE * gckVIDMEM_NODE;
++
++#if gcdENABLE_VG
++typedef struct _gcoVG * gcoVG;
++typedef struct _gcsCOMPLETION_SIGNAL * gcsCOMPLETION_SIGNAL_PTR;
++typedef struct _gcsCONTEXT_MAP * gcsCONTEXT_MAP_PTR;
++#else
++typedef void * gcoVG;
++#endif
++
++#if gcdSYNC
++typedef struct _gcoFENCE * gcoFENCE;
++typedef struct _gcsSYNC_CONTEXT * gcsSYNC_CONTEXT_PTR;
++#endif
++
++#if defined(ANDROID)
++typedef struct _gcoOS_SymbolsList gcoOS_SymbolsList;
++#endif
++
++/******************************************************************************\
++******************************* Process local storage *************************
++\******************************************************************************/
++
++typedef struct _gcsPLS * gcsPLS_PTR;
++
++#if gcdENABLE_3D
++/******************************************************************************
++**
++** Patch defines which should be moved to dedicate file later
++**
++** !!! ALWAYS ADD new ID in the TAIL, otherwise will break exising TRACE FILE
++*******************************************************************************/
++typedef enum _gcePATCH_ID
++{
++ gcvPATCH_NOTINIT = -1,
++ gcvPATCH_INVALID = 0,
++
++#if gcdDEBUG_OPTION
++ gcvPATCH_DEBUG,
++#endif
++
++ gcvPATCH_GTFES30,
++ gcvPATCH_CTGL11,
++ gcvPATCH_CTGL20,
++ gcvPATCH_GLBM11,
++ gcvPATCH_GLBM21,
++ gcvPATCH_GLBM25,
++ gcvPATCH_GLBM27,
++ gcvPATCH_GLBMGUI,
++ gcvPATCH_GFXBENCH,
++ gcvPATCH_ANTUTU, /* Antutu 3.x */
++ gcvPATCH_ANTUTU4X, /* Antutu 4.x */
++ gcvPATCH_QUADRANT,
++ gcvPATCH_GPUBENCH,
++ gcvPATCH_DUOKAN,
++ gcvPATCH_GLOFTSXHM,
++ gcvPATCH_XRUNNER,
++ gcvPATCH_BUSPARKING3D,
++ gcvPATCH_SIEGECRAFT,
++ gcvPATCH_PREMIUM,
++ gcvPATCH_RACEILLEGAL,
++ gcvPATCH_MEGARUN,
++ gcvPATCH_BMGUI,
++ gcvPATCH_NENAMARK,
++ gcvPATCH_NENAMARK2,
++ gcvPATCH_FISHNOODLE,
++ gcvPATCH_MM06,
++ gcvPATCH_MM07,
++ gcvPATCH_BM21,
++ gcvPATCH_SMARTBENCH,
++ gcvPATCH_JPCT,
++ gcvPATCH_NEOCORE,
++ gcvPATCH_RTESTVA,
++ gcvPATCH_NBA2013,
++ gcvPATCH_BARDTALE,
++ gcvPATCH_F18,
++ gcvPATCH_CARPARK,
++ gcvPATCH_CARCHALLENGE,
++ gcvPATCH_HEROESCALL,
++ gcvPATCH_GLOFTF3HM,
++ gcvPATCH_CRAZYRACING,
++ gcvPATCH_FIREFOX,
++ gcvPATCH_CHROME,
++ gcvPATCH_MONOPOLY,
++ gcvPATCH_SNOWCOLD,
++ gcvPATCH_BM3,
++ gcvPATCH_BASEMARKX,
++ gcvPATCH_DEQP,
++ gcvPATCH_SF4,
++ gcePATCH_MGOHEAVEN2,
++ gcePATCH_SILIBILI,
++ gcePATCH_ELEMENTSDEF,
++ gcePATCH_GLOFTKRHM,
++ gcvPATCH_OCLCTS,
++ gcvPATCH_A8HP,
++ gcvPATCH_A8CN,
++ gcvPATCH_WISTONESG,
++ gcvPATCH_SPEEDRACE,
++ gcvPATCH_FSBHAWAIIF,
++ gcvPATCH_AIRNAVY,
++ gcvPATCH_F18NEW,
++ gcvPATCH_CKZOMBIES2,
++ gcvPATCH_EADGKEEPER,
++ gcvPATCH_BASEMARK2V2,
++ gcvPATCH_RIPTIDEGP2,
++ gcvPATCH_OESCTS,
++ gcvPATCH_GANGSTAR,
++ gcvPATCH_WHRKYZIXOVAN,
++ gcvPATCH_NAMESGAS,
++ gcvPATCH_AFTERBURNER,
++ gcvPATCH_UIMARK,
++ gcvPATCH_FM_OES_PLAYER,
++ gcvPATCH_SUMSUNG_BENCH,
++ gcvPATCH_ROCKSTAR_MAXPAYNE,
++ gcvPATCH_TITANPACKING,
++ gcvPATCH_BASEMARKOSIICN,
++ gcvPATCH_FRUITNINJA,
++#if defined(ANDROID)
++ gcePATCH_ANDROID_CTS_MEDIA_PRESENTATIONTIME,
++#endif
++ gcvPATCH_ANDROID_COMPOSITOR,
++ gcvPATCH_CTS_TEXTUREVIEW,
++ gcvPATCH_WATER2_CHUKONG,
++
++ gcvPATCH_COUNT
++} gcePATCH_ID;
++#endif /* gcdENABLE_3D */
++
++typedef void (* gctPLS_DESTRUCTOR) (
++ gcsPLS_PTR
++ );
++
++typedef struct _gcsPLS
++{
++ /* Global objects. */
++ gcoOS os;
++ gcoHAL hal;
++
++ /* Internal memory pool. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctPOINTER internalLogical;
++
++ /* External memory pool. */
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctPOINTER externalLogical;
++
++ /* Contiguous memory pool. */
++ gctSIZE_T contiguousSize;
++ gctPHYS_ADDR contiguousPhysical;
++ gctPOINTER contiguousLogical;
++
++ /* EGL-specific process-wide objects. */
++ gctPOINTER eglDisplayInfo;
++ gctPOINTER eglSurfaceInfo;
++ gceSURF_FORMAT eglConfigFormat;
++
++ /* PLS reference count */
++ gcsATOM_PTR reference;
++
++ /* PorcessID of the constrcutor process */
++ gctUINT32 processID;
++
++ /* ThreadID of the constrcutor process. */
++ gctSIZE_T threadID;
++ /* Flag for calling module destructor. */
++ gctBOOL exiting;
++
++ gctBOOL bNeedSupportNP2Texture;
++
++ gctPLS_DESTRUCTOR destructor;
++ /* Mutex to guard PLS access. currently it's for EGL.
++ ** We can use this mutex for every PLS access.
++ */
++ gctPOINTER accessLock;
++#if gcdENABLE_3D
++ /* Global patchID to overwrite the detection */
++ gcePATCH_ID patchID;
++#endif
++}
++gcsPLS;
++
++extern gcsPLS gcPLS;
++
++#if gcdENABLE_3D
++#define gcPLS_INITIALIZER \
++{ \
++ gcvNULL, /* gcoOS object. */ \
++ gcvNULL, /* gcoHAL object. */ \
++ 0, /* internalSize */ \
++ gcvNULL, /* internalPhysical */ \
++ gcvNULL, /* internalLogical */ \
++ 0, /* externalSize */ \
++ gcvNULL, /* externalPhysical */ \
++ gcvNULL, /* externalLogical */ \
++ 0, /* contiguousSize */ \
++ gcvNULL, /* contiguousPhysical */ \
++ gcvNULL, /* contiguousLogical */ \
++ gcvNULL, /* eglDisplayInfo */ \
++ gcvNULL, /* eglSurfaceInfo */ \
++ gcvSURF_A8R8G8B8,/* eglConfigFormat */ \
++ gcvNULL, /* reference */ \
++ 0, /* processID */ \
++ 0, /* threadID */ \
++ gcvFALSE, /* exiting */ \
++ gcvFALSE, /* Special flag for NP2 texture. */ \
++ gcvNULL, /* destructor */ \
++ gcvNULL, /* accessLock */ \
++ gcvPATCH_NOTINIT,/* global patchID */ \
++}
++#else
++#define gcPLS_INITIALIZER \
++{ \
++ gcvNULL, /* gcoOS object. */ \
++ gcvNULL, /* gcoHAL object. */ \
++ 0, /* internalSize */ \
++ gcvNULL, /* internalPhysical */ \
++ gcvNULL, /* internalLogical */ \
++ 0, /* externalSize */ \
++ gcvNULL, /* externalPhysical */ \
++ gcvNULL, /* externalLogical */ \
++ 0, /* contiguousSize */ \
++ gcvNULL, /* contiguousPhysical */ \
++ gcvNULL, /* contiguousLogical */ \
++ gcvNULL, /* eglDisplayInfo */ \
++ gcvNULL, /* eglSurfaceInfo */ \
++ gcvSURF_A8R8G8B8,/* eglConfigFormat */ \
++ gcvNULL, /* reference */ \
++ 0, /* processID */ \
++ 0, /* threadID */ \
++ gcvFALSE, /* exiting */ \
++ gcvFALSE, /* Special flag for NP2 texture. */ \
++ gcvNULL, /* destructor */ \
++ gcvNULL, /* accessLock */ \
++}
++#endif
++
++/******************************************************************************\
++******************************* Thread local storage *************************
++\******************************************************************************/
++
++typedef struct _gcsTLS * gcsTLS_PTR;
++
++typedef void (* gctTLS_DESTRUCTOR) (
++ gcsTLS_PTR
++ );
++
++typedef struct _gcsTLS
++{
++ gceHARDWARE_TYPE currentType;
++
++ /* Current 3D hardwre of this thread */
++ gcoHARDWARE currentHardware;
++
++ /* Default 3D hardware of this thread */
++ gcoHARDWARE defaultHardware;
++
++ /* Only for separated 3D and 2D */
++ gcoHARDWARE hardware2D;
++#if gcdENABLE_VG
++ gcoVGHARDWARE vg;
++ gcoVG engineVG;
++#endif /* gcdENABLE_VG */
++#if gcdENABLE_3D
++ gco3D engine3D;
++#endif
++#if gcdENABLE_2D
++ gco2D engine2D;
++#endif
++
++ /*thread data */
++ gctPOINTER context;
++ /* ES(including es1 and es2) client driver context which is current state */
++ gctPOINTER esClientCtx;
++ gctTLS_DESTRUCTOR destructor;
++
++ gctBOOL copied;
++
++ /* libGAL.so handle */
++ gctHANDLE handle;
++
++ /* If true, do not releas 2d engine and hardware in hal layer */
++ gctBOOL release2DUpper;
++}
++gcsTLS;
++
++/******************************************************************************\
++********************************* Enumerations *********************************
++\******************************************************************************/
++
++typedef enum _gcePLS_VALUE
++{
++ gcePLS_VALUE_EGL_DISPLAY_INFO,
++ gcePLS_VALUE_EGL_SURFACE_INFO,
++ gcePLS_VALUE_EGL_CONFIG_FORMAT_INFO,
++ gcePLS_VALUE_EGL_DESTRUCTOR_INFO,
++}
++gcePLS_VALUE;
++
++/* Video memory pool type. */
++typedef enum _gcePOOL
++{
++ gcvPOOL_UNKNOWN = 0,
++ gcvPOOL_DEFAULT,
++ gcvPOOL_LOCAL,
++ gcvPOOL_LOCAL_INTERNAL,
++ gcvPOOL_LOCAL_EXTERNAL,
++ gcvPOOL_UNIFIED,
++ gcvPOOL_SYSTEM,
++ gcvPOOL_VIRTUAL,
++ gcvPOOL_USER,
++ gcvPOOL_CONTIGUOUS,
++
++ gcvPOOL_NUMBER_OF_POOLS
++}
++gcePOOL;
++
++#if gcdENABLE_3D
++/* Blending functions. */
++typedef enum _gceBLEND_FUNCTION
++{
++ gcvBLEND_ZERO,
++ gcvBLEND_ONE,
++ gcvBLEND_SOURCE_COLOR,
++ gcvBLEND_INV_SOURCE_COLOR,
++ gcvBLEND_SOURCE_ALPHA,
++ gcvBLEND_INV_SOURCE_ALPHA,
++ gcvBLEND_TARGET_COLOR,
++ gcvBLEND_INV_TARGET_COLOR,
++ gcvBLEND_TARGET_ALPHA,
++ gcvBLEND_INV_TARGET_ALPHA,
++ gcvBLEND_SOURCE_ALPHA_SATURATE,
++ gcvBLEND_CONST_COLOR,
++ gcvBLEND_INV_CONST_COLOR,
++ gcvBLEND_CONST_ALPHA,
++ gcvBLEND_INV_CONST_ALPHA,
++}
++gceBLEND_FUNCTION;
++
++/* Blending modes. */
++typedef enum _gceBLEND_MODE
++{
++ gcvBLEND_ADD,
++ gcvBLEND_SUBTRACT,
++ gcvBLEND_REVERSE_SUBTRACT,
++ gcvBLEND_MIN,
++ gcvBLEND_MAX,
++}
++gceBLEND_MODE;
++
++/* Depth modes. */
++typedef enum _gceDEPTH_MODE
++{
++ gcvDEPTH_NONE,
++ gcvDEPTH_Z,
++ gcvDEPTH_W,
++}
++gceDEPTH_MODE;
++#endif /* gcdENABLE_3D */
++
++#if (gcdENABLE_3D || gcdENABLE_VG)
++/* API flags. */
++typedef enum _gceAPI
++{
++ gcvAPI_D3D = 1,
++ gcvAPI_OPENGL_ES11,
++ gcvAPI_OPENGL_ES20,
++ gcvAPI_OPENGL_ES30,
++ gcvAPI_OPENGL,
++ gcvAPI_OPENVG,
++ gcvAPI_OPENCL,
++}
++gceAPI;
++#endif
++
++
++typedef enum _gceWHERE
++{
++ gcvWHERE_COMMAND,
++ gcvWHERE_RASTER,
++ gcvWHERE_PIXEL,
++}
++gceWHERE;
++
++typedef enum _gceHOW
++{
++ gcvHOW_SEMAPHORE = 0x1,
++ gcvHOW_STALL = 0x2,
++ gcvHOW_SEMAPHORE_STALL = 0x3,
++}
++gceHOW;
++
++typedef enum _gceSignalHandlerType
++{
++ gcvHANDLE_SIGFPE_WHEN_SIGNAL_CODE_IS_0 = 0x1,
++}
++gceSignalHandlerType;
++
++/* gcsHAL_Limits*/
++typedef struct _gcsHAL_LIMITS
++{
++ /* chip info */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 featureCount;
++ gctUINT32 *chipFeatures;
++
++ /* target caps */
++ gctUINT32 maxWidth;
++ gctUINT32 maxHeight;
++ gctUINT32 multiTargetCount;
++ gctUINT32 maxSamples;
++
++}gcsHAL_LIMITS;
++
++/******************************************************************************\
++*********** Generic Memory Allocation Optimization Using Containers ************
++\******************************************************************************/
++
++/* Generic container definition. */
++typedef struct _gcsCONTAINER_LINK * gcsCONTAINER_LINK_PTR;
++typedef struct _gcsCONTAINER_LINK
++{
++ /* Points to the next container. */
++ gcsCONTAINER_LINK_PTR next;
++}
++gcsCONTAINER_LINK;
++
++typedef struct _gcsCONTAINER_RECORD * gcsCONTAINER_RECORD_PTR;
++typedef struct _gcsCONTAINER_RECORD
++{
++ gcsCONTAINER_RECORD_PTR prev;
++ gcsCONTAINER_RECORD_PTR next;
++}
++gcsCONTAINER_RECORD;
++
++typedef struct _gcsCONTAINER * gcsCONTAINER_PTR;
++typedef struct _gcsCONTAINER
++{
++ gctUINT containerSize;
++ gctUINT recordSize;
++ gctUINT recordCount;
++ gcsCONTAINER_LINK_PTR containers;
++ gcsCONTAINER_RECORD freeList;
++ gcsCONTAINER_RECORD allocList;
++}
++gcsCONTAINER;
++
++gceSTATUS
++gcsCONTAINER_Construct(
++ IN gcsCONTAINER_PTR Container,
++ gctUINT RecordsPerContainer,
++ gctUINT RecordSize
++ );
++
++gceSTATUS
++gcsCONTAINER_Destroy(
++ IN gcsCONTAINER_PTR Container
++ );
++
++gceSTATUS
++gcsCONTAINER_AllocateRecord(
++ IN gcsCONTAINER_PTR Container,
++ OUT gctPOINTER * Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeRecord(
++ IN gcsCONTAINER_PTR Container,
++ IN gctPOINTER Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeAll(
++ IN gcsCONTAINER_PTR Container
++ );
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++/* Construct a new gcoHAL object. */
++gceSTATUS
++gcoHAL_ConstructEx(
++ IN gctPOINTER Context,
++ IN gcoOS Os,
++ OUT gcoHAL * Hal
++ );
++
++/* Destroy an gcoHAL object. */
++gceSTATUS
++gcoHAL_DestroyEx(
++ IN gcoHAL Hal
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoHAL_Construct(
++ IN gctPOINTER Context,
++ IN gcoOS Os,
++ OUT gcoHAL * Hal
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoHAL_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Get HAL options */
++gceSTATUS
++gcoHAL_GetOption(
++ IN gcoHAL Hal,
++ IN gceOPTION Option
++ );
++
++gceSTATUS
++gcoHAL_FrameInfoOps(
++ IN gcoHAL Hal,
++ IN gceFRAMEINFO FrameInfo,
++ IN gceFRAMEINFO_OP Op,
++ IN OUT gctUINT * Val
++ );
++
++
++gceSTATUS
++gcoHAL_GetHardware(
++ IN gcoHAL Hal,
++ OUT gcoHARDWARE* Hw
++ );
++
++#if gcdENABLE_2D
++/* Get pointer to gco2D object. */
++gceSTATUS
++gcoHAL_Get2DEngine(
++ IN gcoHAL Hal,
++ OUT gco2D * Engine
++ );
++#endif
++
++#if gcdENABLE_3D
++gceSTATUS
++gcoHAL_GetSpecialHintData(
++ IN gcoHAL Hal,
++ OUT gctINT * Hint
++ );
++/*
++** Deprecated(Don't use it), keep it here for external library(libgcu.so)
++*/
++gceSTATUS
++gcoHAL_Get3DEngine(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++#endif /* gcdEANBLE_3D */
++
++
++gceSTATUS
++gcoHAL_GetProductName(
++ IN gcoHAL Hal,
++ OUT gctSTRING *ProductName
++ );
++
++gceSTATUS
++gcoHAL_SetFscaleValue(
++ IN gctUINT FscaleValue
++ );
++
++gceSTATUS
++gcoHAL_GetFscaleValue(
++ OUT gctUINT * FscaleValue,
++ OUT gctUINT * MinFscaleValue,
++ OUT gctUINT * MaxFscaleValue
++ );
++
++gceSTATUS
++gcoHAL_SetBltNP2Texture(
++ gctBOOL enable
++ );
++
++gceSTATUS
++gcoHAL_NameVideoMemory(
++ IN gctUINT32 Handle,
++ OUT gctUINT32 * Name
++ );
++
++gceSTATUS
++gcoHAL_ImportVideoMemory(
++ IN gctUINT32 Name,
++ OUT gctUINT32 * Handle
++ );
++
++gceSTATUS
++gcoHAL_GetVideoMemoryFd(
++ IN gctUINT32 Handle,
++ OUT gctINT * Fd
++ );
++
++/* Verify whether the specified feature is available in hardware. */
++gceSTATUS
++gcoHAL_IsFeatureAvailable(
++ IN gcoHAL Hal,
++ IN gceFEATURE Feature
++ );
++
++gceSTATUS
++gcoHAL_IsSwwaNeeded(
++ IN gcoHAL Hal,
++ IN gceSWWA Swwa
++ );
++
++gceSTATUS
++gcoHAL_IsFeatureAvailable1(
++ IN gcoHAL Hal,
++ IN gceFEATURE Feature
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gcoHAL_QueryChipIdentity(
++ IN gcoHAL Hal,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++/* Query the minor features of the hardware. */
++gceSTATUS gcoHAL_QueryChipMinorFeatures(
++ IN gcoHAL Hal,
++ OUT gctUINT32* NumFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++gctINT32
++gcoOS_EndRecordAllocation(void);
++void
++gcoOS_RecordAllocation(void);
++void
++gcoOS_AddRecordAllocation(gctSIZE_T Size);
++
++/* Query the amount of video memory. */
++gceSTATUS
++gcoHAL_QueryVideoMemory(
++ IN gcoHAL Hal,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Map video memory. */
++gceSTATUS
++gcoHAL_MapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap video memory. */
++gceSTATUS
++gcoHAL_UnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Schedule an unmap of a buffer mapped through its physical address. */
++gceSTATUS
++gcoHAL_ScheduleUnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Allocate video memory. */
++gceSTATUS
++gcoOS_AllocateVideoMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN gctBOOL InCacheable,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * Physical,
++ OUT gctPOINTER * Logical,
++ OUT gctPOINTER * Handle
++ );
++
++/* Free video memory. */
++gceSTATUS
++gcoOS_FreeVideoMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Handle
++ );
++
++/* Lock video memory. */
++gceSTATUS
++gcoOS_LockVideoMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Handle,
++ IN gctBOOL InUserSpace,
++ IN gctBOOL InCacheable,
++ OUT gctUINT32 * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoHAL_MapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR GPUAddress
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoHAL_UnmapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 GPUAddress
++ );
++
++/* Schedule an unmap of a user buffer using event mechanism. */
++gceSTATUS
++gcoHAL_ScheduleUnmapUserMemory(
++ IN gcoHAL Hal,
++ IN gctPOINTER Info,
++ IN gctSIZE_T Size,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory
++ );
++
++/* Commit the current command buffer. */
++gceSTATUS
++gcoHAL_Commit(
++ IN gcoHAL Hal,
++ IN gctBOOL Stall
++ );
++
++#if gcdENABLE_3D
++/* Sencd fence command. */
++gceSTATUS
++gcoHAL_SendFence(
++ IN gcoHAL Hal
++ );
++#endif /* gcdENABLE_3D */
++
++/* Query the tile capabilities. */
++gceSTATUS
++gcoHAL_QueryTiled(
++ IN gcoHAL Hal,
++ OUT gctINT32 * TileWidth2D,
++ OUT gctINT32 * TileHeight2D,
++ OUT gctINT32 * TileWidth3D,
++ OUT gctINT32 * TileHeight3D
++ );
++
++gceSTATUS
++gcoHAL_Compact(
++ IN gcoHAL Hal
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoHAL_ProfileStart(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_ProfileEnd(
++ IN gcoHAL Hal,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++/* Power Management */
++gceSTATUS
++gcoHAL_SetPowerManagementState(
++ IN gcoHAL Hal,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gcoHAL_QueryPowerManagementState(
++ IN gcoHAL Hal,
++ OUT gceCHIPPOWERSTATE *State
++ );
++
++/* Set the filter type for filter blit. */
++gceSTATUS
++gcoHAL_SetFilterType(
++ IN gcoHAL Hal,
++ IN gceFILTER_TYPE FilterType
++ );
++
++gceSTATUS
++gcoHAL_GetDump(
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++#if gcdENABLE_3D
++gceSTATUS
++gcoHAL_SetPatchID(
++ IN gcoHAL Hal,
++ IN gcePATCH_ID PatchID
++ );
++
++/* Get Patch ID based on process name */
++gceSTATUS
++gcoHAL_GetPatchID(
++ IN gcoHAL Hal,
++ OUT gcePATCH_ID * PatchID
++ );
++
++gceSTATUS
++gcoHAL_SetGlobalPatchID(
++ IN gcoHAL Hal,
++ IN gcePATCH_ID PatchID
++ );
++#endif /* gcdENABLE_3D */
++/* Call the kernel HAL layer. */
++gceSTATUS
++gcoHAL_Call(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++/* Schedule an event. */
++gceSTATUS
++gcoHAL_ScheduleEvent(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++/* Destroy a surface. */
++gceSTATUS
++gcoHAL_DestroySurface(
++ IN gcoHAL Hal,
++ IN gcoSURF Surface
++ );
++
++/* Request a start/stop timestamp. */
++gceSTATUS
++gcoHAL_SetTimer(
++ IN gcoHAL Hal,
++ IN gctUINT32 Index,
++ IN gctBOOL Start
++ );
++
++/* Get Time delta from a Timer in microseconds. */
++gceSTATUS
++gcoHAL_GetTimerTime(
++ IN gcoHAL Hal,
++ IN gctUINT32 Timer,
++ OUT gctINT32_PTR TimeDelta
++ );
++
++/* set timeout value. */
++gceSTATUS
++gcoHAL_SetTimeOut(
++ IN gcoHAL Hal,
++ IN gctUINT32 timeOut
++ );
++
++gceSTATUS
++gcoHAL_SetHardwareType(
++ IN gcoHAL Hal,
++ IN gceHARDWARE_TYPE HardwardType
++ );
++
++gceSTATUS
++gcoHAL_GetHardwareType(
++ IN gcoHAL Hal,
++ OUT gceHARDWARE_TYPE * HardwardType
++ );
++
++gceSTATUS
++gcoHAL_QueryChipCount(
++ IN gcoHAL Hal,
++ OUT gctINT32 * Count
++ );
++
++gceSTATUS
++gcoHAL_Query3DCoreCount(
++ IN gcoHAL Hal,
++ OUT gctUINT32 *Count
++ );
++
++gceSTATUS
++gcoHAL_QuerySeparated2D(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_Is3DAvailable(
++ IN gcoHAL Hal
++ );
++
++/* Get pointer to gcoVG object. */
++gceSTATUS
++gcoHAL_GetVGEngine(
++ IN gcoHAL Hal,
++ OUT gcoVG * Engine
++ );
++
++gceSTATUS
++gcoHAL_QueryChipLimits(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ IN gctINT32 Mask,
++ OUT gcsHAL_LIMITS *Limits);
++
++gceSTATUS
++gcoHAL_QueryChipFeature(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ IN gctINT32 Mask,
++ IN gceFEATURE Feature);
++
++/*----------------------------------------------------------------------------*/
++/*----- Shared Buffer --------------------------------------------------------*/
++
++/* Create shared buffer. */
++gceSTATUS
++gcoHAL_CreateShBuffer(
++ IN gctUINT32 Size,
++ OUT gctSHBUF * ShBuf
++ );
++
++/* Destroy shared buffer. */
++gceSTATUS
++gcoHAL_DestroyShBuffer(
++ IN gctSHBUF ShBuf
++ );
++
++/* Map shared buffer to current process. */
++gceSTATUS
++gcoHAL_MapShBuffer(
++ IN gctSHBUF ShBuf
++ );
++
++/* Write user data to shared buffer. */
++gceSTATUS
++gcoHAL_WriteShBuffer(
++ IN gctSHBUF ShBuf,
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 ByteCount
++ );
++
++/* Read user data from shared buffer. */
++gceSTATUS
++gcoHAL_ReadShBuffer(
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER Data,
++ IN gctUINT32 BytesCount,
++ OUT gctUINT32 * BytesRead
++ );
++
++/* Config power management to be enabled or disabled. */
++gceSTATUS
++gcoHAL_ConfigPowerManagement(
++ IN gctBOOL Enable
++ );
++
++#if gcdENABLE_3D || gcdENABLE_VG
++/* Query the target capabilities. */
++gceSTATUS
++gcoHAL_QueryTargetCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MultiTargetCount,
++ OUT gctUINT * MaxSamples
++ );
++#endif
++
++/******************************************************************************\
++********************************** gcoOS Object *********************************
++\******************************************************************************/
++/* Lock PLS access */
++gceSTATUS
++gcoOS_LockPLS(
++ void
++ );
++
++/* Unlock PLS access */
++gceSTATUS
++gcoOS_UnLockPLS(
++ void
++ );
++
++/* Get PLS value for given key */
++gctPOINTER
++gcoOS_GetPLSValue(
++ IN gcePLS_VALUE key
++ );
++
++/* Set PLS value of a given key */
++void
++gcoOS_SetPLSValue(
++ IN gcePLS_VALUE key,
++ OUT gctPOINTER value
++ );
++
++/* Get access to the thread local storage. */
++gceSTATUS
++gcoOS_GetTLS(
++ OUT gcsTLS_PTR * TLS
++ );
++
++ /* Copy the TLS from a source thread. */
++ gceSTATUS gcoOS_CopyTLS(IN gcsTLS_PTR Source);
++
++/* Destroy the objects associated with the current thread. */
++void
++gcoOS_FreeThreadData(
++ void
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoOS_Construct(
++ IN gctPOINTER Context,
++ OUT gcoOS * Os
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoOS_Destroy(
++ IN gcoOS Os
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gcoOS_GetBaseAddress(
++ IN gcoOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gcoOS_Allocate(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Get allocated memory size. */
++gceSTATUS
++gcoOS_GetMemorySize(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gcoOS_Free(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoOS_AllocateSharedMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoOS_FreeSharedMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoOS_AllocateMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoOS_FreeMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gcoOS_AllocateContiguous(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gcoOS_FreeContiguous(
++ IN gcoOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemoryEx(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoOS_UnmapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/* Device I/O Control call to the kernel HAL layer. */
++gceSTATUS
++gcoOS_DeviceControl(
++ IN gcoOS Os,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ IN gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/* Allocate non paged memory. */
++gceSTATUS
++gcoOS_AllocateNonPagedMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non paged memory. */
++gceSTATUS
++gcoOS_FreeNonPagedMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++#define gcmOS_SAFE_FREE(os, mem) \
++ gcoOS_Free(os, mem); \
++ mem = gcvNULL
++
++#define gcmOS_SAFE_FREE_SHARED_MEMORY(os, mem) \
++ gcoOS_FreeSharedMemory(os, mem); \
++ mem = gcvNULL
++
++#define gcmkOS_SAFE_FREE(os, mem) \
++ gckOS_Free(os, mem); \
++ mem = gcvNULL
++
++typedef enum _gceFILE_MODE
++{
++ gcvFILE_CREATE = 0,
++ gcvFILE_APPEND,
++ gcvFILE_READ,
++ gcvFILE_CREATETEXT,
++ gcvFILE_APPENDTEXT,
++ gcvFILE_READTEXT,
++}
++gceFILE_MODE;
++
++/* Open a file. */
++gceSTATUS
++gcoOS_Open(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ IN gceFILE_MODE Mode,
++ OUT gctFILE * File
++ );
++
++/* Close a file. */
++gceSTATUS
++gcoOS_Close(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Read data from a file. */
++gceSTATUS
++gcoOS_Read(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T * ByteRead
++ );
++
++/* Write data to a file. */
++gceSTATUS
++gcoOS_Write(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data to a file. */
++gceSTATUS
++gcoOS_Flush(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Close a file descriptor. */
++gceSTATUS
++gcoOS_CloseFD(
++ IN gcoOS Os,
++ IN gctINT FD
++ );
++
++/* Dup file descriptor to another. */
++gceSTATUS
++gcoOS_DupFD(
++ IN gcoOS Os,
++ IN gctINT FD,
++ OUT gctINT * FD2
++ );
++
++/* Create an endpoint for communication. */
++gceSTATUS
++gcoOS_Socket(
++ IN gcoOS Os,
++ IN gctINT Domain,
++ IN gctINT Type,
++ IN gctINT Protocol,
++ OUT gctINT *SockFd
++ );
++
++/* Close a socket. */
++gceSTATUS
++gcoOS_CloseSocket(
++ IN gcoOS Os,
++ IN gctINT SockFd
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_Connect(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctCONST_POINTER HostName,
++ IN gctUINT Port);
++
++/* Shut down part of connection on a socket. */
++gceSTATUS
++gcoOS_Shutdown(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT How
++ );
++
++/* Send a message on a socket. */
++gceSTATUS
++gcoOS_Send(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data,
++ IN gctINT Flags
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_WaitForSend(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT Seconds,
++ IN gctINT MicroSeconds);
++
++/* Get environment variable value. */
++gceSTATUS
++gcoOS_GetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ OUT gctSTRING * Value
++ );
++
++/* Set environment variable value. */
++gceSTATUS
++gcoOS_SetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ IN gctSTRING Value
++ );
++
++/* Get current working directory. */
++gceSTATUS
++gcoOS_GetCwd(
++ IN gcoOS Os,
++ IN gctINT SizeInBytes,
++ OUT gctSTRING Buffer
++ );
++
++/* Get file status info. */
++gceSTATUS
++gcoOS_Stat(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ OUT gctPOINTER Buffer
++ );
++
++typedef enum _gceFILE_WHENCE
++{
++ gcvFILE_SEEK_SET,
++ gcvFILE_SEEK_CUR,
++ gcvFILE_SEEK_END
++}
++gceFILE_WHENCE;
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_Seek(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Offset,
++ IN gceFILE_WHENCE Whence
++ );
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_SetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Position
++ );
++
++/* Get the current position of a file. */
++gceSTATUS
++gcoOS_GetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ OUT gctUINT32 * Position
++ );
++
++/* Same as strstr. */
++gceSTATUS
++gcoOS_StrStr(
++ IN gctCONST_STRING String,
++ IN gctCONST_STRING SubString,
++ OUT gctSTRING * Output
++ );
++
++/* Find the last occurance of a character inside a string. */
++gceSTATUS
++gcoOS_StrFindReverse(
++ IN gctCONST_STRING String,
++ IN gctINT8 Character,
++ OUT gctSTRING * Output
++ );
++
++gceSTATUS
++gcoOS_StrDup(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ OUT gctSTRING * Target
++ );
++
++/* Copy a string. */
++gceSTATUS
++gcoOS_StrCopySafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Append a string. */
++gceSTATUS
++gcoOS_StrCatSafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Compare two strings. */
++gceSTATUS
++gcoOS_StrCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2
++ );
++
++/* Compare characters of two strings. */
++gceSTATUS
++gcoOS_StrNCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2,
++ IN gctSIZE_T Count
++ );
++
++/* Convert string to float. */
++gceSTATUS
++gcoOS_StrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert hex string to integer. */
++gceSTATUS gcoOS_HexStrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++/* Convert hex string to float. */
++gceSTATUS
++gcoOS_HexStrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert string to integer. */
++gceSTATUS
++gcoOS_StrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++gceSTATUS
++gcoOS_MemCmp(
++ IN gctCONST_POINTER Memory1,
++ IN gctCONST_POINTER Memory2,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_PrintStrSafe(
++ OUT gctSTRING String,
++ IN gctSIZE_T StringSize,
++ IN OUT gctUINT * Offset,
++ IN gctCONST_STRING Format,
++ ...
++ );
++
++gceSTATUS
++gcoOS_LoadLibrary(
++ IN gcoOS Os,
++ IN gctCONST_STRING Library,
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeLibrary(
++ IN gcoOS Os,
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_GetProcAddress(
++ IN gcoOS Os,
++ IN gctHANDLE Handle,
++ IN gctCONST_STRING Name,
++ OUT gctPOINTER * Function
++ );
++
++gceSTATUS
++gcoOS_Compact(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_AddSignalHandler (
++ IN gceSignalHandlerType SignalHandlerType
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoOS_ProfileStart(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_ProfileEnd(
++ IN gcoOS Os,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_SetProfileSetting(
++ IN gcoOS Os,
++ IN gctBOOL Enable,
++ IN gctCONST_STRING FileName
++ );
++#endif
++
++/* Query the video memory. */
++gceSTATUS
++gcoOS_QueryVideoMemory(
++ IN gcoOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Detect if the process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByNamePid(
++ IN gctCONST_STRING Name,
++ IN gctHANDLE Pid
++ );
++
++/* Detect if the current process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByName(
++ IN gctCONST_STRING Name
++ );
++
++gceSTATUS
++gcoOS_DetectProcessByEncryptedName(
++ IN gctCONST_STRING Name
++ );
++
++#if defined(ANDROID)
++gceSTATUS
++gcoOS_DetectProgrameByEncryptedSymbols(
++ IN gcoOS_SymbolsList Symbols
++ );
++#endif
++
++/*----------------------------------------------------------------------------*/
++/*----- Atoms ----------------------------------------------------------------*/
++
++/* Construct an atom. */
++gceSTATUS
++gcoOS_AtomConstruct(
++ IN gcoOS Os,
++ OUT gcsATOM_PTR * Atom
++ );
++
++/* Destroy an atom. */
++gceSTATUS
++gcoOS_AtomDestroy(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom
++ );
++
++/* Get the 32-bit value protected by an atom. */
++gceSTATUS
++gcoOS_AtomGet(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/* Set the 32-bit value protected by an atom. */
++gceSTATUS
++gcoOS_AtomSet(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ IN gctINT32 Value
++ );
++
++/* Increment an atom. */
++gceSTATUS
++gcoOS_AtomIncrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++/* Decrement an atom. */
++gceSTATUS
++gcoOS_AtomDecrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++gctHANDLE
++gcoOS_GetCurrentProcessID(
++ void
++ );
++
++gctHANDLE
++gcoOS_GetCurrentThreadID(
++ void
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Time -----------------------------------------------------------------*/
++
++/* Get the number of milliseconds since the system started. */
++gctUINT32
++gcoOS_GetTicks(
++ void
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gcoOS_GetTime(
++ gctUINT64_PTR Time
++ );
++
++/* Get CPU usage in microseconds. */
++gceSTATUS
++gcoOS_GetCPUTime(
++ gctUINT64_PTR CPUTime
++ );
++
++/* Get memory usage. */
++gceSTATUS
++gcoOS_GetMemoryUsage(
++ gctUINT32_PTR MaxRSS,
++ gctUINT32_PTR IxRSS,
++ gctUINT32_PTR IdRSS,
++ gctUINT32_PTR IsRSS
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gcoOS_Delay(
++ IN gcoOS Os,
++ IN gctUINT32 Delay
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Threads --------------------------------------------------------------*/
++
++typedef void * gctTHREAD_RETURN;
++typedef void * (* gcTHREAD_ROUTINE)(void *);
++
++/* Create a new thread. */
++gceSTATUS
++gcoOS_CreateThread(
++ IN gcoOS Os,
++ IN gcTHREAD_ROUTINE Worker,
++ IN gctPOINTER Argument,
++ OUT gctPOINTER * Thread
++ );
++
++/* Close a thread. */
++gceSTATUS
++gcoOS_CloseThread(
++ IN gcoOS Os,
++ IN gctPOINTER Thread
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Mutexes --------------------------------------------------------------*/
++
++/* Create a new mutex. */
++gceSTATUS
++gcoOS_CreateMutex(
++ IN gcoOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gcoOS_DeleteMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gcoOS_AcquireMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gcoOS_ReleaseMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Signals --------------------------------------------------------------*/
++
++/* Create a signal. */
++gceSTATUS
++gcoOS_CreateSignal(
++ IN gcoOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gcoOS_DestroySignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gcoOS_Signal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gcoOS_WaitSignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a signal from another process */
++gceSTATUS
++gcoOS_MapSignal(
++ IN gctSIGNAL RemoteSignal,
++ OUT gctSIGNAL * LocalSignal
++ );
++
++/* Unmap a signal mapped from another process */
++gceSTATUS
++gcoOS_UnmapSignal(
++ IN gctSIGNAL Signal
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Android Native Fence -------------------------------------------------*/
++
++/* Create sync point. */
++gceSTATUS
++gcoOS_CreateSyncPoint(
++ IN gcoOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++/* Destroy sync point. */
++gceSTATUS
++gcoOS_DestroySyncPoint(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++/* Create native fence. */
++gceSTATUS
++gcoOS_CreateNativeFence(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++/* Wait on native fence. */
++gceSTATUS
++gcoOS_WaitNativeFence(
++ IN gcoOS Os,
++ IN gctINT FenceFD,
++ IN gctUINT32 Timeout
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Memory Access and Cache ----------------------------------------------*/
++
++/* Write a register. */
++gceSTATUS
++gcoOS_WriteRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Read a register. */
++gceSTATUS
++gcoOS_ReadRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++gceSTATUS
++gcoOS_CacheClean(
++ IN gcoOS Os,
++ IN gctUINT32 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheFlush(
++ IN gcoOS Os,
++ IN gctUINT32 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheInvalidate(
++ IN gcoOS Os,
++ IN gctUINT32 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_MemoryBarrier(
++ IN gcoOS Os,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gcoOS_CPUPhysicalToGPUPhysical(
++ IN gctUINT32 CPUPhysical,
++ OUT gctUINT32_PTR GPUPhysical
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ );
++
++gceSTATUS
++gcoOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gcoOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++#define _gcmPROFILE_INIT(prefix, freq, start) \
++ do { \
++ prefix ## OS_QueryProfileTickRate(&(freq)); \
++ prefix ## OS_GetProfileTick(&(start)); \
++ } while (gcvFALSE)
++
++#define _gcmPROFILE_QUERY(prefix, start, ticks) \
++ do { \
++ prefix ## OS_GetProfileTick(&(ticks)); \
++ (ticks) = ((ticks) > (start)) ? ((ticks) - (start)) \
++ : (~0ull - (start) + (ticks) + 1); \
++ } while (gcvFALSE)
++
++#if gcdENABLE_PROFILING
++# define gcmkPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gck, freq, start)
++# define gcmkPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gck, start, ticks)
++# define gcmPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gco, freq, start)
++# define gcmPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gco, start, ticks)
++# define gcmPROFILE_ONLY(x) x
++# define gcmPROFILE_ELSE(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ONLY(x) x
++# define gcmPROFILE_DECLARE_ELSE(x) typedef x
++#else
++# define gcmkPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmkPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_ELSE(x) x
++# define gcmPROFILE_DECLARE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ELSE(x) x
++#endif
++
++/*******************************************************************************
++** gcoMATH object
++*/
++
++#define gcdPI 3.14159265358979323846f
++
++/* Kernel. */
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++/* User. */
++gctUINT32
++gcoMATH_Log2in5dot5(
++ IN gctINT X
++ );
++
++
++gctFLOAT
++gcoMATH_UIntAsFloat(
++ IN gctUINT32 X
++ );
++
++gctUINT32
++gcoMATH_FloatAsUInt(
++ IN gctFLOAT X
++ );
++
++gctBOOL
++gcoMATH_CompareEqualF(
++ IN gctFLOAT X,
++ IN gctFLOAT Y
++ );
++
++gctUINT16
++gcoMATH_UInt8AsFloat16(
++ IN gctUINT8 X
++ );
++
++gctUINT32
++gcoMATH_Float16ToFloat(
++ IN gctUINT16 In
++ );
++
++gctUINT16
++gcoMATH_FloatToFloat16(
++ IN gctUINT32 In
++ );
++
++gctUINT32
++gcoMATH_Float11ToFloat(
++ IN gctUINT32 In
++ );
++
++gctUINT16
++gcoMATH_FloatToFloat11(
++ IN gctUINT32 In
++ );
++
++gctUINT32
++gcoMATH_Float10ToFloat(
++ IN gctUINT32 In
++ );
++
++gctUINT16
++gcoMATH_FloatToFloat10(
++ IN gctUINT32 In
++ );
++
++gctUINT32
++gcoMATH_Float14ToFloat(
++ IN gctUINT16 In
++ );
++
++/******************************************************************************\
++**************************** Coordinate Structures *****************************
++\******************************************************************************/
++
++typedef struct _gcsPOINT
++{
++ gctINT32 x;
++ gctINT32 y;
++}
++gcsPOINT;
++
++typedef struct _gcsSIZE
++{
++ gctINT32 width;
++ gctINT32 height;
++}
++gcsSIZE;
++
++typedef struct _gcsRECT
++{
++ gctINT32 left;
++ gctINT32 top;
++ gctINT32 right;
++ gctINT32 bottom;
++}
++gcsRECT;
++
++typedef union _gcsPIXEL
++{
++ struct
++ {
++ gctFLOAT r, g, b, a;
++ gctFLOAT d, s;
++ } pf;
++
++ struct
++ {
++ gctINT32 r, g, b, a;
++ gctINT32 d, s;
++ } pi;
++
++ struct
++ {
++ gctUINT32 r, g, b, a;
++ gctUINT32 d, s;
++ } pui;
++
++} gcsPIXEL;
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- gcoSURF Common ------------------------------*/
++
++/* Color format classes. */
++typedef enum _gceFORMAT_CLASS
++{
++ gcvFORMAT_CLASS_RGBA = 4500,
++ gcvFORMAT_CLASS_YUV,
++ gcvFORMAT_CLASS_INDEX,
++ gcvFORMAT_CLASS_LUMINANCE,
++ gcvFORMAT_CLASS_BUMP,
++ gcvFORMAT_CLASS_DEPTH,
++ gcvFORMAT_CLASS_ASTC,
++ gcvFORMAT_CLASS_OTHER
++}
++gceFORMAT_CLASS;
++
++/* Color format data type */
++typedef enum _gceFORMAT_DATATYPE
++{
++ gcvFORMAT_DATATYPE_UNSIGNED_NORMALIZED,
++ gcvFORMAT_DATATYPE_SIGNED_NORMALIZED,
++ gcvFORMAT_DATATYPE_UNSIGNED_INTEGER,
++ gcvFORMAT_DATATYPE_SIGNED_INTEGER,
++ gcvFORMAT_DATATYPE_FLOAT16,
++ gcvFORMAT_DATATYPE_FLOAT32,
++ gcvFORMAT_DATATYPE_FLOAT_E5B9G9R9,
++ gcvFORMAT_DATATYPE_FLOAT_B10G11R11F,
++ gcvFORMAT_DATATYPE_INDEX,
++ gcvFORMAT_DATATYPE_SRGB,
++ gcvFORMAT_DATATYPE_FLOAT32_UINT,
++}
++gceFORMAT_DATATYPE;
++
++/* Special enums for width field in gcsFORMAT_COMPONENT. */
++typedef enum _gceCOMPONENT_CONTROL
++{
++ gcvCOMPONENT_NOTPRESENT = 0x00,
++ gcvCOMPONENT_DONTCARE = 0x80,
++ gcvCOMPONENT_WIDTHMASK = 0x7F,
++ gcvCOMPONENT_ODD = 0x80
++}
++gceCOMPONENT_CONTROL;
++
++/* Color format component parameters. */
++typedef struct _gcsFORMAT_COMPONENT
++{
++ gctUINT8 start;
++ gctUINT8 width;
++}
++gcsFORMAT_COMPONENT;
++
++/* RGBA color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_RGBA
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT red;
++ gcsFORMAT_COMPONENT green;
++ gcsFORMAT_COMPONENT blue;
++}
++gcsFORMAT_CLASS_TYPE_RGBA;
++
++/* YUV color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_YUV
++{
++ gcsFORMAT_COMPONENT y;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT v;
++}
++gcsFORMAT_CLASS_TYPE_YUV;
++
++/* Index color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_INDEX
++{
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_INDEX;
++
++/* Luminance color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_LUMINANCE
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_LUMINANCE;
++
++/* Bump map color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_BUMP
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT l;
++ gcsFORMAT_COMPONENT v;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT q;
++ gcsFORMAT_COMPONENT w;
++}
++gcsFORMAT_CLASS_TYPE_BUMP;
++
++/* Depth and stencil format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_DEPTH
++{
++ gcsFORMAT_COMPONENT depth;
++ gcsFORMAT_COMPONENT stencil;
++}
++gcsFORMAT_CLASS_TYPE_DEPTH;
++
++typedef union _gcuPIXEL_FORMAT_CLASS
++{
++ gcsFORMAT_CLASS_TYPE_BUMP bump;
++ gcsFORMAT_CLASS_TYPE_RGBA rgba;
++ gcsFORMAT_CLASS_TYPE_YUV yuv;
++ gcsFORMAT_CLASS_TYPE_LUMINANCE lum;
++ gcsFORMAT_CLASS_TYPE_INDEX index;
++ gcsFORMAT_CLASS_TYPE_DEPTH depth;
++}
++gcuPIXEL_FORMAT_CLASS;
++
++/* Format parameters. */
++typedef struct _gcsSURF_FORMAT_INFO
++{
++ /* Name of the format */
++ gctCONST_STRING formatName;
++
++ /* Format code and class. */
++ gceSURF_FORMAT format;
++ gceFORMAT_CLASS fmtClass;
++
++ /* Format data type */
++ gceFORMAT_DATATYPE fmtDataType;
++
++ /* The size of one pixel in bits. */
++ gctUINT8 bitsPerPixel;
++
++ /* Pixel block dimensions. */
++ gctUINT blockWidth;
++ gctUINT blockHeight;
++
++ /* Pixel block size in bits. */
++ gctUINT blockSize;
++
++ /* Some formats are larger than what the GPU can support. */
++ /* These formats are read in the number of layers specified. */
++ gctUINT8 layers;
++
++ /* The format is faked and software will interpret it differently
++ ** with HW. Most of them can't be blendable(PE) or filterable(TX).
++ */
++ gctBOOL fakedFormat;
++
++ /* Some formats have two neighbour pixels interleaved together. */
++ /* To describe such format, set the flag to 1 and add another */
++ /* like this one describing the odd pixel format. */
++ gctBOOL interleaved;
++
++ /* sRGB format. */
++ gctBOOL sRGB;
++
++ /* Format components. */
++ gcuPIXEL_FORMAT_CLASS u;
++
++ /* Format components. */
++ gcuPIXEL_FORMAT_CLASS uOdd;
++
++ /* Render format. */
++ gceSURF_FORMAT closestRenderFormat;
++ /*gctCLOSEST_FORMAT dynamicClosestRenderFormat;*/
++ gctUINT renderFormat;
++ const gceTEXTURE_SWIZZLE * pixelSwizzle;
++
++ /* Texture format. */
++ gceSURF_FORMAT closestTXFormat;
++ gctUINT txFormat;
++ const gceTEXTURE_SWIZZLE * txSwizzle;
++ gctBOOL txIntFilter;
++}
++gcsSURF_FORMAT_INFO;
++
++/* Frame buffer information. */
++typedef struct _gcsSURF_FRAMEBUFFER
++{
++ gctPOINTER logical;
++ gctUINT width, height;
++ gctINT stride;
++ gceSURF_FORMAT format;
++}
++gcsSURF_FRAMEBUFFER;
++
++/* Generic pixel component descriptors. */
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XXX8;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XX8X;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_X8XX;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_8XXX;
++
++typedef enum _gceORIENTATION
++{
++ gcvORIENTATION_TOP_BOTTOM,
++ gcvORIENTATION_BOTTOM_TOP,
++}
++gceORIENTATION;
++
++
++/* Construct a new gcoSURF object. */
++gceSTATUS
++gcoSURF_Construct(
++ IN gcoHAL Hal,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++/* Destroy an gcoSURF object. */
++gceSTATUS
++gcoSURF_Destroy(
++ IN gcoSURF Surface
++ );
++
++/* Map user-allocated surface. */
++gceSTATUS
++gcoSURF_MapUserSurface(
++ IN gcoSURF Surface,
++ IN gctUINT Alignment,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Wrapp surface with known logical/GPU address */
++gceSTATUS
++gcoSURF_WrapSurface(
++ IN gcoSURF Surface,
++ IN gctUINT Alignment,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++
++/* Query vid mem node info. */
++gceSTATUS
++gcoSURF_QueryVidMemNode(
++ IN gcoSURF Surface,
++ OUT gctUINT32 * Node,
++ OUT gcePOOL * Pool,
++ OUT gctSIZE_T_PTR Bytes
++ );
++
++/* Set the color type of the surface. */
++gceSTATUS
++gcoSURF_SetColorType(
++ IN gcoSURF Surface,
++ IN gceSURF_COLOR_TYPE ColorType
++ );
++
++/* Get the color type of the surface. */
++gceSTATUS
++gcoSURF_GetColorType(
++ IN gcoSURF Surface,
++ OUT gceSURF_COLOR_TYPE *ColorType
++ );
++
++/* Set the color space of the surface. */
++gceSTATUS
++gcoSURF_SetColorSpace(
++ IN gcoSURF Surface,
++ IN gceSURF_COLOR_SPACE ColorSpace
++ );
++
++/* Get the color space of the surface. */
++gceSTATUS
++gcoSURF_GetColorSpace(
++ IN gcoSURF Surface,
++ OUT gceSURF_COLOR_SPACE *ColorSpace
++ );
++
++
++/* Set the surface ration angle. */
++gceSTATUS
++gcoSURF_SetRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_IsValid(
++ IN gcoSURF Surface
++ );
++
++#if gcdENABLE_3D
++/* Verify and return the state of the tile status mechanism. */
++gceSTATUS
++gcoSURF_IsTileStatusSupported(
++ IN gcoSURF Surface
++ );
++
++/* Verify if surface has tile status enabled. */
++gceSTATUS
++gcoSURF_IsTileStatusEnabled(
++ IN gcoSURF Surface
++ );
++
++/* Verify if surface is compressed. */
++gceSTATUS
++gcoSURF_IsCompressed(
++ IN gcoSURF Surface
++ );
++
++/* Enable tile status for the specified surface on zero slot. */
++gceSTATUS
++gcoSURF_EnableTileStatus(
++ IN gcoSURF Surface
++ );
++
++/* Enable tile status for the specified surface on specified slot. */
++gceSTATUS
++gcoSURF_EnableTileStatusEx(
++ IN gcoSURF Surface,
++ IN gctUINT RtIndex
++ );
++
++/* Disable tile status for the specified surface. */
++gceSTATUS
++gcoSURF_DisableTileStatus(
++ IN gcoSURF Surface,
++ IN gctBOOL Decompress
++ );
++
++/* Flush tile status cache for the specified surface. */
++gceSTATUS
++gcoSURF_FlushTileStatus(
++ IN gcoSURF Surface,
++ IN gctBOOL Decompress
++ );
++#endif /* gcdENABLE_3D */
++
++/* Get surface size. */
++gceSTATUS
++gcoSURF_GetSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctUINT * Depth
++ );
++
++/* Get surface aligned sizes. */
++gceSTATUS
++gcoSURF_GetAlignedSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctINT * Stride
++ );
++
++/* Get alignments. */
++gceSTATUS
++gcoSURF_GetAlignment(
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT * AddressAlignment,
++ OUT gctUINT * XAlignment,
++ OUT gctUINT * YAlignment
++ );
++
++gceSTATUS
++gcoSURF_AlignResolveRect(
++ IN gcoSURF Surf,
++ IN gcsPOINT_PTR RectOrigin,
++ IN gcsPOINT_PTR RectSize,
++ OUT gcsPOINT_PTR AlignedOrigin,
++ OUT gcsPOINT_PTR AlignedSize
++ );
++
++/* Get surface type and format. */
++gceSTATUS
++gcoSURF_GetFormat(
++ IN gcoSURF Surface,
++ OUT OPTIONAL gceSURF_TYPE * Type,
++ OUT OPTIONAL gceSURF_FORMAT * Format
++ );
++
++/* Get surface information */
++gceSTATUS
++gcoSURF_GetFormatInfo(
++ IN gcoSURF Surface,
++ OUT gcsSURF_FORMAT_INFO_PTR * formatInfo
++ );
++
++/* Get Surface pack format */
++gceSTATUS
++gcoSURF_GetPackedFormat(
++ IN gcoSURF Surface,
++ OUT gceSURF_FORMAT * Format
++ );
++
++/* Get surface tiling. */
++gceSTATUS
++gcoSURF_GetTiling(
++ IN gcoSURF Surface,
++ OUT gceTILING * Tiling
++ );
++
++/* Get flip bitmap offset bytes. */
++gceSTATUS
++gcoSURF_GetFlipBitmapOffset(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR FlipBitmapOffset
++ );
++
++/* Get bottom buffer offset bytes. */
++gceSTATUS
++gcoSURF_GetBottomBufferOffset(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR BottomBufferOffset
++ );
++
++/* Lock the surface. */
++gceSTATUS
++gcoSURF_Lock(
++ IN gcoSURF Surface,
++ IN OUT gctUINT32 * Address,
++ IN OUT gctPOINTER * Memory
++ );
++
++/* Unlock the surface. */
++gceSTATUS
++gcoSURF_Unlock(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory
++ );
++
++/*. Query surface flags.*/
++gceSTATUS
++gcoSURF_QueryFlags(
++ IN gcoSURF Surface,
++ IN gceSURF_FLAG Flag
++ );
++
++/* Return pixel format parameters; Info is required to be a pointer to an
++ * array of at least two items because some formats have up to two records
++ * of description. */
++gceSTATUS
++gcoSURF_QueryFormat(
++ IN gceSURF_FORMAT Format,
++ OUT gcsSURF_FORMAT_INFO_PTR * Info
++ );
++
++/* Compute the color pixel mask. */
++gceSTATUS
++gcoSURF_ComputeColorMask(
++ IN gcsSURF_FORMAT_INFO_PTR Format,
++ OUT gctUINT32_PTR ColorMask
++ );
++
++/* Flush the surface. */
++gceSTATUS
++gcoSURF_Flush(
++ IN gcoSURF Surface
++ );
++
++/* Fill surface from it's tile status buffer. */
++gceSTATUS
++gcoSURF_FillFromTile(
++ IN gcoSURF Surface
++ );
++
++/* Fill surface with a value. */
++gceSTATUS
++gcoSURF_Fill(
++ IN gcoSURF Surface,
++ IN gcsPOINT_PTR Origin,
++ IN gcsSIZE_PTR Size,
++ IN gctUINT32 Value,
++ IN gctUINT32 Mask
++ );
++
++/* Alpha blend two surfaces together. */
++gceSTATUS
++gcoSURF_Blend(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrig,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsSIZE_PTR Size,
++ IN gceSURF_BLEND_MODE Mode
++ );
++
++/* Create a new gcoSURF wrapper object. */
++gceSTATUS
++gcoSURF_ConstructWrapper(
++ IN gcoHAL Hal,
++ OUT gcoSURF * Surface
++ );
++
++/* Set surface flags.*/
++gceSTATUS
++gcoSURF_SetFlags(
++ IN gcoSURF Surface,
++ IN gceSURF_FLAG Flag,
++ IN gctBOOL Value
++ );
++
++/* Set the underlying buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Stride,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Set the underlying video buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetVideoBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Stride,
++ IN gctPOINTER *LogicalPlane1,
++ IN gctUINT32 *PhysicalPlane1
++ );
++
++/* Set the size of the surface in pixels and map the underlying buffer. */
++gceSTATUS
++gcoSURF_SetWindow(
++ IN gcoSURF Surface,
++ IN gctUINT X,
++ IN gctUINT Y,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Set width/height alignment of the surface directly and calculate stride/size. This is only for dri backend now. Please be careful before use. */
++gceSTATUS
++gcoSURF_SetAlignment(
++ IN gcoSURF Surface,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Increase reference count of the surface. */
++gceSTATUS
++gcoSURF_ReferenceSurface(
++ IN gcoSURF Surface
++ );
++
++/* Get surface reference count. */
++gceSTATUS
++gcoSURF_QueryReferenceCount(
++ IN gcoSURF Surface,
++ OUT gctINT32 * ReferenceCount
++ );
++
++/* Set surface orientation. */
++gceSTATUS
++gcoSURF_SetOrientation(
++ IN gcoSURF Surface,
++ IN gceORIENTATION Orientation
++ );
++
++/* Query surface orientation. */
++gceSTATUS
++gcoSURF_QueryOrientation(
++ IN gcoSURF Surface,
++ OUT gceORIENTATION * Orientation
++ );
++
++gceSTATUS
++gcoSURF_SetOffset(
++ IN gcoSURF Surface,
++ IN gctSIZE_T Offset
++ );
++
++gceSTATUS
++gcoSURF_NODE_Cache(
++ IN gcsSURF_NODE_PTR Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Lock and unlock surface node */
++gceSTATUS
++gcoSURF_LockNode(
++ IN gcsSURF_NODE_PTR Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++gceSTATUS
++gcoSURF_UnLockNode(
++ IN gcsSURF_NODE_PTR Node,
++ IN gceSURF_TYPE Type
++ );
++
++/* Perform CPU cache operation on surface node */
++gceSTATUS
++gcoSURF_NODE_CPUCacheOperation(
++ IN gcsSURF_NODE_PTR Node,
++ IN gceSURF_TYPE Type,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Length,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Perform CPU cache operation on surface */
++gceSTATUS
++gcoSURF_CPUCacheOperation(
++ IN gcoSURF Surface,
++ IN gceCACHEOPERATION Operation
++ );
++
++
++gceSTATUS
++gcoSURF_Swap(
++ IN gcoSURF Surface1,
++ IN gcoSURF Surface2
++ );
++
++gceSTATUS
++gcoSURF_ResetSurWH(
++ IN gcoSURF Surface,
++ IN gctUINT oriw,
++ IN gctUINT orih,
++ IN gctUINT alignw,
++ IN gctUINT alignh,
++ IN gceSURF_FORMAT fmt
++);
++
++/* Update surface timestamp. */
++gceSTATUS
++gcoSURF_UpdateTimeStamp(
++ IN gcoSURF Surface
++ );
++
++/* Query surface current timestamp. */
++gceSTATUS
++gcoSURF_QueryTimeStamp(
++ IN gcoSURF Surface,
++ OUT gctUINT64 * TimeStamp
++ );
++
++/*
++ * Allocate shared buffer for this surface, so that
++ * surface states can be shared across processes.
++ */
++gceSTATUS
++gcoSURF_AllocShBuffer(
++ IN gcoSURF Surface,
++ OUT gctSHBUF * ShBuf
++ );
++
++/* Bind shared buffer to this surface */
++gceSTATUS
++gcoSURF_BindShBuffer(
++ IN gcoSURF Surface,
++ IN gctSHBUF ShBuf
++ );
++
++/* Push surface shared states to shared buffer. */
++gceSTATUS
++gcoSURF_PushSharedInfo(
++ IN gcoSURF Surface
++ );
++
++/* Pop shared states from shared buffer. */
++gceSTATUS
++gcoSURF_PopSharedInfo(
++ IN gcoSURF Surface
++ );
++
++#if (gcdENABLE_3D || gcdENABLE_VG)
++/* Copy surface. */
++gceSTATUS
++gcoSURF_Copy(
++ IN gcoSURF Surface,
++ IN gcoSURF Source
++ );
++
++/* Set number of samples for a gcoSURF object. */
++gceSTATUS
++gcoSURF_SetSamples(
++ IN gcoSURF Surface,
++ IN gctUINT Samples
++ );
++
++/* Get the number of samples per pixel. */
++gceSTATUS
++gcoSURF_GetSamples(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR Samples
++ );
++#endif
++
++/******************************************************************************\
++********************************* gcoDUMP Object ********************************
++\******************************************************************************/
++
++/* Construct a new gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Construct(
++ IN gcoOS Os,
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++/* Destroy a gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Destroy(
++ IN gcoDUMP Dump
++ );
++
++/* Enable/disable dumping. */
++gceSTATUS
++gcoDUMP_Control(
++ IN gcoDUMP Dump,
++ IN gctSTRING FileName
++ );
++
++gceSTATUS
++gcoDUMP_IsEnabled(
++ IN gcoDUMP Dump,
++ OUT gctBOOL * Enabled
++ );
++
++/* Add surface. */
++gceSTATUS
++gcoDUMP_AddSurface(
++ IN gcoDUMP Dump,
++ IN gctINT32 Width,
++ IN gctINT32 Height,
++ IN gceSURF_FORMAT PixelFormat,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount
++ );
++
++/* Mark the beginning of a frame. */
++gceSTATUS
++gcoDUMP_FrameBegin(
++ IN gcoDUMP Dump
++ );
++
++/* Mark the end of a frame. */
++gceSTATUS
++gcoDUMP_FrameEnd(
++ IN gcoDUMP Dump
++ );
++
++/* Dump data. */
++gceSTATUS
++gcoDUMP_DumpData(
++ IN gcoDUMP Dump,
++ IN gceDUMP_TAG Type,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Delete an address. */
++gceSTATUS
++gcoDUMP_Delete(
++ IN gcoDUMP Dump,
++ IN gctUINT32 Address
++ );
++
++/* Enable dump or not. */
++gceSTATUS
++gcoDUMP_SetDumpFlag(
++ IN gctBOOL DumpState
++ );
++
++/******************************************************************************\
++******************************* gcsRECT Structure ******************************
++\******************************************************************************/
++
++/* Initialize rectangle structure. */
++gceSTATUS
++gcsRECT_Set(
++ OUT gcsRECT_PTR Rect,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Return the width of the rectangle. */
++gceSTATUS
++gcsRECT_Width(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Width
++ );
++
++/* Return the height of the rectangle. */
++gceSTATUS
++gcsRECT_Height(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Height
++ );
++
++/* Ensure that top left corner is to the left and above the right bottom. */
++gceSTATUS
++gcsRECT_Normalize(
++ IN OUT gcsRECT_PTR Rect
++ );
++
++/* Compare two rectangles. */
++gceSTATUS
++gcsRECT_IsEqual(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * Equal
++ );
++
++/* Compare the sizes of two rectangles. */
++gceSTATUS
++gcsRECT_IsOfEqualSize(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * EqualSize
++ );
++
++gceSTATUS
++gcsRECT_RelativeRotation(
++ IN gceSURF_ROTATION Orientation,
++ IN OUT gceSURF_ROTATION *Relation);
++
++gceSTATUS
++
++gcsRECT_Rotate(
++
++ IN OUT gcsRECT_PTR Rect,
++
++ IN gceSURF_ROTATION Rotation,
++
++ IN gceSURF_ROTATION toRotation,
++
++ IN gctINT32 SurfaceWidth,
++
++ IN gctINT32 SurfaceHeight
++
++ );
++
++/******************************************************************************\
++**************************** gcsBOUNDARY Structure *****************************
++\******************************************************************************/
++
++typedef struct _gcsBOUNDARY
++{
++ gctINT x;
++ gctINT y;
++ gctINT width;
++ gctINT height;
++}
++gcsBOUNDARY;
++
++/******************************************************************************\
++********************************* gcoHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gcoHEAP * gcoHEAP;
++
++/* Construct a new gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Construct(
++ IN gcoOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gcoHEAP * Heap
++ );
++
++/* Destroy an gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Destroy(
++ IN gcoHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoHEAP_Allocate(
++ IN gcoHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcoHEAP_GetMemorySize(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoHEAP_Free(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++#if (VIVANTE_PROFILER || gcdDEBUG)
++/* Profile the heap. */
++gceSTATUS
++gcoHEAP_ProfileStart(
++ IN gcoHEAP Heap
++ );
++
++gceSTATUS
++gcoHEAP_ProfileEnd(
++ IN gcoHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++
++/******************************************************************************\
++******************************* Debugging Macros *******************************
++\******************************************************************************/
++
++void
++gcoOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gcoOS_GetDebugLevel(
++ OUT gctUINT32_PTR DebugLevel
++ );
++
++void
++gcoOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_GetDebugZone(
++ IN gctUINT32 Zone,
++ OUT gctUINT32_PTR DebugZone
++ );
++
++void
++gcoOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gcoOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++gctFILE
++gcoOS_ReplaceDebugFile(
++ IN gctFILE fp
++ );
++
++void
++gcoOS_SysTraceBegin(
++ IN gctCONST_STRING FuncName
++ );
++
++void
++gcoOS_SysTraceEnd(
++ IN void);
++
++/*******************************************************************************
++**
++** gcmFATAL
++**
++** Print a message to the debugger and execute a break point.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_FATAL)
++# define gcmFATAL gcoOS_DebugFatal
++# define gcmkFATAL gckOS_DebugFatal
++#elif gcdHAS_ELLIPSIS
++# define gcmFATAL(...)
++# define gcmkFATAL(...)
++#else
++ gcmINLINE static void
++ __dummy_fatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmFATAL __dummy_fatal
++# define gcmkFATAL __dummy_fatal
++#endif
++
++#define gcmENUM2TEXT(e) case e: return #e
++
++/*******************************************************************************
++**
++** gcmTRACE
++**
++** Print a message to the debugfer if the correct level has been set. In
++** retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** level Level of message.
++** message Message.
++** ... Optional arguments.
++*/
++#define gcvLEVEL_NONE -1
++#define gcvLEVEL_ERROR 0
++#define gcvLEVEL_WARNING 1
++#define gcvLEVEL_INFO 2
++#define gcvLEVEL_VERBOSE 3
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE gcoOS_DebugTrace
++# define gcmkTRACE gckOS_DebugTrace
++# define gcmkTRACE_N gckOS_DebugTraceN
++#elif gcdHAS_ELLIPSIS
++# define gcmTRACE(...)
++# define gcmkTRACE(...)
++# define gcmkTRACE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_n(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE __dummy_trace
++# define gcmkTRACE __dummy_trace
++# define gcmkTRACE_N __dummy_trace_n
++#endif
++
++/* Zones common for kernel and user. */
++#define gcvZONE_OS (1 << 0)
++#define gcvZONE_HARDWARE (1 << 1)
++#define gcvZONE_HEAP (1 << 2)
++#define gcvZONE_SIGNAL (1 << 27)
++
++/* Kernel zones. */
++#define gcvZONE_KERNEL (1 << 3)
++#define gcvZONE_VIDMEM (1 << 4)
++#define gcvZONE_COMMAND (1 << 5)
++#define gcvZONE_DRIVER (1 << 6)
++#define gcvZONE_CMODEL (1 << 7)
++#define gcvZONE_MMU (1 << 8)
++#define gcvZONE_EVENT (1 << 9)
++#define gcvZONE_DEVICE (1 << 10)
++#define gcvZONE_DATABASE (1 << 11)
++#define gcvZONE_INTERRUPT (1 << 12)
++#define gcvZONE_POWER (1 << 13)
++
++/* User zones. */
++#define gcvZONE_HAL (1 << 3)
++#define gcvZONE_BUFFER (1 << 4)
++#define gcvZONE_CONTEXT (1 << 5)
++#define gcvZONE_SURFACE (1 << 6)
++#define gcvZONE_INDEX (1 << 7)
++#define gcvZONE_STREAM (1 << 8)
++#define gcvZONE_TEXTURE (1 << 9)
++#define gcvZONE_2D (1 << 10)
++#define gcvZONE_3D (1 << 11)
++#define gcvZONE_COMPILER (1 << 12)
++#define gcvZONE_MEMORY (1 << 13)
++#define gcvZONE_STATE (1 << 14)
++#define gcvZONE_AUX (1 << 15)
++#define gcvZONE_VERTEX (1 << 16)
++#define gcvZONE_CL (1 << 17)
++#define gcvZONE_COMPOSITION (1 << 17)
++#define gcvZONE_VG (1 << 18)
++#define gcvZONE_IMAGE (1 << 19)
++#define gcvZONE_UTILITY (1 << 20)
++#define gcvZONE_PARAMETERS (1 << 21)
++#define gcvZONE_BUFOBJ (1 << 22)
++#define gcvZONE_SHADER (1 << 23)
++#define gcvZONE_STREAM_OUT (1 << 24)
++
++/* API definitions. */
++#define gcvZONE_API_HAL (1 << 28)
++#define gcvZONE_API_EGL (2 << 28)
++#define gcvZONE_API_ES11 (3 << 28)
++#define gcvZONE_API_ES20 (4 << 28)
++#define gcvZONE_API_VG11 (5 << 28)
++#define gcvZONE_API_GL (6 << 28)
++#define gcvZONE_API_DFB (7 << 28)
++#define gcvZONE_API_GDI ((gctUINT32)8 << 28)
++#define gcvZONE_API_D3D ((gctUINT32)9 << 28)
++#define gcvZONE_API_ES30 ((gctUINT32)10 << 28)
++
++
++#define gcmZONE_GET_API(zone) ((zone) >> 28)
++/*Set gcdZONE_MASE like 0x0 | gcvZONE_API_EGL
++will enable print EGL module debug info*/
++#define gcdZONE_MASK 0x0FFFFFFF
++
++/* Handy zones. */
++#define gcvZONE_NONE 0
++#define gcvZONE_ALL 0x0FFFFFFF
++
++/*Dump API depth set 1 for API, 2 for API and API behavior*/
++#define gcvDUMP_API_DEPTH 1
++
++/*******************************************************************************
++**
++** gcmTRACE_ZONE
++**
++** Print a message to the debugger if the correct level and zone has been
++** set. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** Level Level of message.
++** Zone Zone of message.
++** Message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE_ZONE gcoOS_DebugTraceZone
++# define gcmkTRACE_ZONE gckOS_DebugTraceZone
++# define gcmkTRACE_ZONE_N gckOS_DebugTraceZoneN
++#elif gcdHAS_ELLIPSIS
++# define gcmTRACE_ZONE(...)
++# define gcmkTRACE_ZONE(...)
++# define gcmkTRACE_ZONE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace_zone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_zone_n(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE_N __dummy_trace_zone_n
++#endif
++
++/*******************************************************************************
++**
++** gcmDEBUG_ONLY
++**
++** Execute a statement or function only in DEBUG mode.
++**
++** ARGUMENTS:
++**
++** f Statement or function to execute.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++# define gcmDEBUG_ONLY(f) f
++#else
++# define gcmDEBUG_ONLY(f)
++#endif
++
++/*******************************************************************************
++**
++** gcmSTACK_PUSH
++** gcmSTACK_POP
++** gcmSTACK_DUMP
++**
++** Push or pop a function with entry arguments on the trace stack.
++**
++** ARGUMENTS:
++**
++** Function Name of function.
++** Line Line number.
++** Text Optional text.
++** ... Optional arguments for text.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_STACK)
++ void gcoOS_StackPush(IN gctINT8_PTR Identity, IN gctCONST_STRING Function, IN gctINT Line, IN gctCONST_STRING Text, ...);
++ void gcoOS_StackPop(IN gctINT8_PTR Identity, IN gctCONST_STRING Function);
++ void gcoOS_StackDump(void);
++ void gcoOS_StackRemove(IN gctHANDLE Thread);
++
++# define gcmSTACK_PUSH gcoOS_StackPush
++# define gcmSTACK_POP gcoOS_StackPop
++# define gcmSTACK_DUMP gcoOS_StackDump
++# define gcmSTACK_REMOVE gcoOS_StackRemove
++#elif gcdHAS_ELLIPSIS
++# define gcmSTACK_PUSH(...) do { } while (0)
++# define gcmSTACK_POP(...) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++# define gcmSTACK_REMOVE(...) do { } while (0)
++#else
++ gcmINLINE static void
++ __dummy_stack_push(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text, ...
++ )
++ {
++ }
++# define gcmSTACK_PUSH __dummy_stack_push
++# define gcmSTACK_POP(a,b) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++# define gcmSTACK_REMOVE(a) do { } while (0)
++#endif
++
++/******************************************************************************\
++******************************** Binary Trace **********************************
++\******************************************************************************/
++typedef struct _gcsBINARY_TRACE_MESSAGE * gcsBINARY_TRACE_MESSAGE_PTR;
++typedef struct _gcsBINARY_TRACE_MESSAGE
++{
++ gctUINT32 signature;
++ gctUINT32 pid;
++ gctUINT32 tid;
++ gctUINT32 line;
++ gctUINT32 numArguments;
++ gctUINT8 payload;
++}
++gcsBINARY_TRACE_MESSAGE;
++
++#define gcdBINARY_TRACE_MESSAGE_SIZE 240
++
++#if gcdBINARY_TRACE
++ void
++ gcoOS_BinaryTrace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text OPTIONAL,
++ ...
++ );
++
++ void
++ gckOS_BinaryTrace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text OPTIONAL,
++ ...
++ );
++
++# define gcmBINARY_TRACE gcoOS_BinaryTrace
++# define gcmkBINARY_TRACE gckOS_BinaryTrace
++#elif gcdHAS_ELLIPSIS
++# define gcmBINARY_TRACE(Function, Line, Text, ...)
++# define gcmkBINARY_TRACE(Function, Line, Text, ...)
++#else
++ gcmINLINE static void
++ __dummy_binary_trace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text,
++ )
++ {
++ }
++
++# define gcmBINARY_TRACE __dummy_binary_trace
++# define gcmkBINARY_TRACE __dummy_binary_trace
++#endif
++
++/******************************************************************************\
++******************************** Logging Macros ********************************
++\******************************************************************************/
++
++#define gcdHEADER_LEVEL gcvLEVEL_VERBOSE
++
++#ifndef gcdEMPTY_HEADER_FOOTER
++#define gcdEMPTY_HEADER_FOOTER 0
++#endif
++
++#if gcdENABLE_PROFILING
++void
++gcoOS_ProfileDB(
++ IN gctCONST_STRING Function,
++ IN OUT gctBOOL_PTR Initialized
++ );
++
++#define gcmHEADER() \
++ gctINT8 __user__ = 1; \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(&__user__, __FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmHEADER_ARG(...) \
++ gctINT8 __user__ = 1; \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(&__user__, __FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmFOOTER() \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_ARG(...) \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(gcvNULL, gcvNULL)
++
++#else /* gcdENABLE_PROFILING */
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmHEADER()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmHEADER()
++#elif gcdHAS_ELLIPSIS
++#define gcmHEADER() \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__user_ptr__, __FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_header(void)
++ {
++ }
++# define gcmHEADER __dummy_header
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmHEADER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++#if gcdEMPTY_HEADER_FOOTER
++# define gcmHEADER_ARG(Text, ...)
++#else
++# define gcmHEADER_ARG(Text, ...) \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__user_ptr__, __FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#endif
++#else
++ gcmINLINE static void
++ __dummy_header_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmHEADER_ARG __dummy_header_arg
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmFOOTER()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER()
++#elif gcdHAS_ELLIPSIS
++# define gcmFOOTER() \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, \
++ status, gcoOS_DebugStatus2Name(status)); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer(void)
++ {
++ }
++# define gcmFOOTER __dummy_footer
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmFOOTER_NO()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER_NO()
++#elif gcdHAS_ELLIPSIS
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_no(void)
++ {
++ }
++# define gcmFOOTER_NO __dummy_footer_no
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmFOOTER_KILL()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER_KILL()
++#elif gcdHAS_ELLIPSIS
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_kill(void)
++ {
++ }
++# define gcmFOOTER_KILL __dummy_footer_kill
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmFOOTER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++#if gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER_ARG(Text, ...)
++#else
++# define gcmFOOTER_ARG(Text, ...) \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__user_ptr__ -= 1
++#endif
++#else
++ gcmINLINE static void
++ __dummy_footer_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmFOOTER_ARG __dummy_footer_arg
++#endif
++
++#endif /* gcdENABLE_PROFILING */
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmkHEADER()
++#elif gcdHAS_ELLIPSIS
++#define gcmkHEADER() \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_kheader(void)
++ {
++ }
++# define gcmkHEADER __dummy_kheader
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmkHEADER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++# define gcmkHEADER_ARG(Text, ...) \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#else
++ gcmINLINE static void
++ __dummy_kheader_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkHEADER_ARG __dummy_kheader_arg
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmkFOOTER()
++#elif gcdHAS_ELLIPSIS
++#define gcmkFOOTER() \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, status); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, status, gckOS_DebugStatus2Name(status)); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter(void)
++ {
++ }
++# define gcmkFOOTER __dummy_kfooter
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmkFOOTER_NO()
++#elif gcdHAS_ELLIPSIS
++#define gcmkFOOTER_NO() \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_no(void)
++ {
++ }
++# define gcmkFOOTER_NO __dummy_kfooter_no
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmkFOOTER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++# define gcmkFOOTER_ARG(Text, ...) \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, \
++ __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkFOOTER_ARG __dummy_kfooter_arg
++#endif
++
++#define gcmOPT_VALUE(ptr) (((ptr) == gcvNULL) ? 0 : *(ptr))
++#define gcmOPT_VALUE_INDEX(ptr, index) (((ptr) == gcvNULL) ? 0 : ptr[index])
++#define gcmOPT_POINTER(ptr) (((ptr) == gcvNULL) ? gcvNULL : *(ptr))
++#define gcmOPT_STRING(ptr) (((ptr) == gcvNULL) ? "(nil)" : (ptr))
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#define gcmPRINT gcoOS_Print
++#define gcmkPRINT gckOS_Print
++#define gcmkPRINT_N gckOS_PrintN
++
++#if gcdPRINT_VERSION
++# define gcmPRINT_VERSION() do { \
++ _gcmPRINT_VERSION(gcm); \
++ gcmSTACK_DUMP(); \
++ } while (0)
++# define gcmkPRINT_VERSION() _gcmPRINT_VERSION(gcmk)
++# define _gcmPRINT_VERSION(prefix) \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "Vivante HAL version %d.%d.%d build %d %s %s", \
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, \
++ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME )
++#else
++# define gcmPRINT_VERSION() do { gcmSTACK_DUMP(); } while (gcvFALSE)
++# define gcmkPRINT_VERSION() do { } while (gcvFALSE)
++#endif
++
++typedef enum _gceDUMP_BUFFER
++{
++ gceDUMP_BUFFER_CONTEXT,
++ gceDUMP_BUFFER_USER,
++ gceDUMP_BUFFER_KERNEL,
++ gceDUMP_BUFFER_LINK,
++ gceDUMP_BUFFER_WAITLINK,
++ gceDUMP_BUFFER_FROM_USER,
++}
++gceDUMP_BUFFER;
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ );
++
++#define gcmkDUMPBUFFER gckOS_DumpBuffer
++
++#if gcdDUMP_COMMAND
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage) \
++ gcmkDUMPBUFFER(Os, Buffer, Size, Type, CopyMessage)
++#else
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage)
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ );
++
++# define gcmkDEBUGFLUSH(DmaAddress) \
++ gckOS_DebugFlush(__FUNCTION__, __LINE__, DmaAddress)
++#else
++# define gcmkDEBUGFLUSH(DmaAddress)
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_FRAMERATE
++**
++** Print average frame rate
++**
++*/
++#if gcdDUMP_FRAMERATE
++ gceSTATUS
++ gcfDumpFrameRate(
++ void
++ );
++# define gcmDUMP_FRAMERATE gcfDumpFrameRate
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_FRAMERATE(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_frame_rate(
++ void
++ )
++ {
++ }
++# define gcmDUMP_FRAMERATE __dummy_dump_frame_rate
++#endif
++
++
++/*******************************************************************************
++**
++** gcmDUMP
++**
++** Print a dump message.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++#if gcdDUMP
++ gceSTATUS
++ gcfDump(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ ...
++ );
++# define gcmDUMP gcfDump
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP(...)
++#else
++ gcmINLINE static void
++ __dummy_dump(
++ IN gcoOS Os,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP __dummy_dump
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_DATA
++**
++** Add data to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++ gceSTATUS
++ gcfDumpData(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_DATA gcfDumpData
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_data(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_DATA __dummy_dump_data
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_BUFFER
++**
++** Print a buffer to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctUINT32 Physical
++** Physical address of buffer.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctUINT32 Offset
++** Offset into buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++gceSTATUS
++gcfDumpBuffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_BUFFER gcfDumpBuffer
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_BUFFER(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_buffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_BUFFER __dummy_dump_buffer
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API
++**
++** Print a dump message for a high level API prefixed by the function name.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++gceSTATUS gcfDumpApi(IN gctCONST_STRING String, ...);
++#if gcdDUMP_API
++# define gcmDUMP_API gcfDumpApi
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP_API __dummy_dump_api
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY
++**
++** Print an array of data.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Size.
++*/
++gceSTATUS gcfDumpArray(IN gctCONST_POINTER Data, IN gctUINT32 Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY gcfDumpArray
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API_ARRAY(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY __dummy_dump_api_array
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY_TOKEN
++**
++** Print an array of data terminated by a token.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Termination.
++*/
++gceSTATUS gcfDumpArrayToken(IN gctCONST_POINTER Data, IN gctUINT32 Termination);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY_TOKEN gcfDumpArrayToken
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API_ARRAY_TOKEN(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array_token(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Termination
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY_TOKEN __dummy_dump_api_array_token
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_DATA
++**
++** Print an array of bytes.
++**
++** ARGUMENTS:
++**
++** gctCONST_POINTER Pointer to array.
++** gctSIZE_T Size.
++*/
++gceSTATUS gcfDumpApiData(IN gctCONST_POINTER Data, IN gctSIZE_T Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_DATA gcfDumpApiData
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_data(
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Size
++ )
++ {
++ }
++# define gcmDUMP_API_DATA __dummy_dump_api_data
++#endif
++
++/*******************************************************************************
++** gcmDUMP_2D_COMMAND
++**
++** Print the 2D command buffer.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to the command buffer.
++** gctUINT32 Command buffer size.
++*/
++gceSTATUS gcfDump2DCommand(IN gctUINT32_PTR Command, IN gctUINT32 Size);
++#if gcdDUMP_2D
++# define gcmDUMP_2D_COMMAND gcfDump2DCommand
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_2D_COMMAND(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_2d_command(
++ IN gctUINT32_PTR Command,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_2D_COMMAND __dummy_dump_2d_command
++#endif
++
++/*******************************************************************************
++** gcmDUMP_2D_SURFACE
++**
++** Print the 2D surface memory.
++**
++** ARGUMENTS:
++**
++** gctBOOL Src.
++** gctUINT32 Address.
++*/
++gceSTATUS gcfDump2DSurface(IN gctBOOL Src, IN gctUINT32 Address);
++#if gcdDUMP_2D
++# define gcmDUMP_2D_SURFACE gcfDump2DSurface
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_2D_SURFACE(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_2d_surface(
++ IN gctBOOL Src,
++ IN gctUINT32 Address
++ )
++ {
++ }
++# define gcmDUMP_2D_SURFACE __dummy_dump_2d_surface
++#endif
++
++/*******************************************************************************
++** gcmDUMP_ADD_MEMORY_INFO
++**
++** Record the memory info.
++**
++** ARGUMENTS:
++**
++** gctUINT32 Address.
++** gctSIZE_T Size.
++*/
++gceSTATUS gcfAddMemoryInfo(IN gctUINT32 GPUAddress, IN gctPOINTER Logical, IN gctUINT32 Physical, IN gctUINT32 Size);
++#if gcdDUMP_2D
++# define gcmDUMP_ADD_MEMORY_INFO gcfAddMemoryInfo
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_ADD_MEMORY_INFO(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_add_memory_info(
++ IN gctUINT32 GPUAddress,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_ADD_MEMORY_INFO __dummy_dump_add_memory_info
++#endif
++
++/*******************************************************************************
++** gcmDUMP_DEL_MEMORY_INFO
++**
++** Record the memory info.
++**
++** ARGUMENTS:
++**
++** gctUINT32 Address.
++*/
++gceSTATUS gcfDelMemoryInfo(IN gctUINT32 Address);
++#if gcdDUMP_2D
++# define gcmDUMP_DEL_MEMORY_INFO gcfDelMemoryInfo
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_DEL_MEMORY_INFO(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_del_memory_info(
++ IN gctUINT32 Address
++ )
++ {
++ }
++# define gcmDUMP_DEL_MEMORY_INFO __dummy_dump_del_memory_info
++#endif
++
++#if gcdDUMP_2D
++extern gctPOINTER dumpMemInfoListMutex;
++extern gctBOOL dump2DFlag;
++#endif
++
++/*******************************************************************************
++**
++** gcmTRACE_RELEASE
++**
++** Print a message to the shader debugger.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++#define gcmTRACE_RELEASE gcoOS_DebugShaderTrace
++
++void
++gcoOS_DebugShaderTrace(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_SetDebugShaderFiles(
++ IN gctCONST_STRING VSFileName,
++ IN gctCONST_STRING FSFileName
++ );
++
++void
++gcoOS_SetDebugShaderFileType(
++ IN gctUINT32 ShaderType
++ );
++
++void
++gcoOS_EnableDebugBuffer(
++ IN gctBOOL Enable
++ );
++
++/*******************************************************************************
++**
++** gcmBREAK
++**
++** Break into the debugger. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** None.
++*/
++
++void
++gcoOS_DebugBreak(
++ void
++ );
++
++void
++gckOS_DebugBreak(
++ void
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_BREAK)
++# define gcmBREAK gcoOS_DebugBreak
++# define gcmkBREAK gckOS_DebugBreak
++#else
++# define gcmBREAK()
++# define gcmkBREAK()
++#endif
++
++/*******************************************************************************
++**
++** gcmASSERT
++**
++** Evaluate an expression and break into the debugger if the expression
++** evaluates to false. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define _gcmASSERT(prefix, exp) \
++ do \
++ { \
++ if (!(exp)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ASSERT at %s(%d)", \
++ __FUNCTION__, __LINE__); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "(%s)", #exp); \
++ prefix##BREAK(); \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmASSERT(exp) _gcmASSERT(gcm, exp)
++# define gcmkASSERT(exp) _gcmASSERT(gcmk, exp)
++#else
++# define gcmASSERT(exp)
++# define gcmkASSERT(exp)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY
++**
++** Verify if an expression returns true. If the expression does not
++** evaluates to true, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY(exp) gcmASSERT(exp)
++# define gcmkVERIFY(exp) gcmkASSERT(exp)
++#else
++# define gcmVERIFY(exp) exp
++# define gcmkVERIFY(exp) exp
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_OK
++**
++** Verify a fucntion returns gcvSTATUS_OK. If the function does not return
++** gcvSTATUS_OK, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++
++void
++gcoOS_Verify(
++ IN gceSTATUS status
++ );
++
++void
++gckOS_Verify(
++ IN gceSTATUS status
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ gcoOS_Verify(verifyStatus); \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gcmASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++# define gcmkVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmkTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmkVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gckOS_Verify(verifyStatus); \
++ gcmkASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++#else
++# define gcmVERIFY_OK(func) func
++# define gcmkVERIFY_OK(func) func
++#endif
++
++gctCONST_STRING
++gcoOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++/*******************************************************************************
++**
++** gcmERR_BREAK
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_BREAK(func) _gcmERR_BREAK(gcm, func)
++#define gcmkERR_BREAK(func) _gcmkERR_BREAK(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmERR_RETURN
++**
++** Executes a return on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_RETURN(func) _gcmERR_RETURN(gcm, func)
++#define gcmkERR_RETURN(func) _gcmkERR_RETURN(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmONWARNING
++**
++** Jump to the error handler in case there is an error, but only report at
++** the WARNING debug level. This is for non fatal errors.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmONWARNING(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_WARNING, \
++ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ status = gcvSTATUS_WARNING; \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkONWARNING(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_WARNING(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_WARNING, \
++ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ status = gcvSTATUS_WARNING; \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmONWARNING(func) _gcmONWARNING(gcm, func)
++#define gcmkONWARNING(func) _gcmkONWARNING(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmONERROR
++**
++** Jump to the error handler in case there is an error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_WARNING(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_WARNING, \
++ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ else if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_WARNING(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_WARNING, \
++ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ else if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmONERROR(func) _gcmONERROR(gcm, func)
++#define gcmkONERROR(func) _gcmkONERROR(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmkSAFECASTSIZET
++**
++** Check wether value of a gctSIZE_T varible beyond the capability
++** of 32bits GPU hardware.
++**
++** ASSUMPTIONS:
++**
++**
++**
++** ARGUMENTS:
++**
++** x A gctUINT32 variable
++** y A gctSIZE_T variable
++*/
++#define gcmkSAFECASTSIZET(x, y) \
++ do \
++ { \
++ gctUINT32 tmp = (gctUINT32)(y); \
++ if (gcmSIZEOF(gctSIZE_T) > gcmSIZEOF(gctUINT32)) \
++ { \
++ gcmkASSERT(tmp <= gcvMAXUINT32); \
++ } \
++ (x) = tmp; \
++ } \
++ while (gcvFALSE)
++
++#define gcmSAFECASTSIZET(x, y) \
++ do \
++ { \
++ gctUINT32 tmp = (gctUINT32)(y); \
++ if (gcmSIZEOF(gctSIZE_T) > gcmSIZEOF(gctUINT32)) \
++ { \
++ gcmASSERT(tmp <= gcvMAXUINT32); \
++ } \
++ (x) = tmp; \
++ } \
++ while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmVERIFY_LOCK
++**
++** Verifies whether the surface is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_LOCK(surfaceInfo) \
++ if (!surfaceInfo->node.valid) \
++ { \
++ gcmONERROR(gcvSTATUS_MEMORY_UNLOCKED); \
++ } \
++
++/*******************************************************************************
++**
++** gcmVERIFY_NODE_LOCK
++**
++** Verifies whether the surface node is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_NODE_LOCK(surfaceNode) \
++ if (!(surfaceNode)->valid) \
++ { \
++ status = gcvSTATUS_MEMORY_UNLOCKED; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmBADOBJECT_BREAK
++**
++** Executes a break statement on bad object.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#define gcmBADOBJECT_BREAK(obj, t) \
++ if ((obj == gcvNULL) \
++ || (((gcsOBJECT *)(obj))->type != t) \
++ ) \
++ { \
++ status = gcvSTATUS_INVALID_OBJECT; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmCHECK_STATUS
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gcoOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gckOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmCHECK_STATUS(func) _gcmCHECK_STATUS(gcm, func)
++#define gcmkCHECK_STATUS(func) _gcmkCHECK_STATUS(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT(prefix, arg) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, #prefix "VERIFY_ARGUMENT failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); \
++ return gcvSTATUS_INVALID_ARGUMENT; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcmk, arg)
++
++/*******************************************************************************
++**
++** gcmDEBUG_VERIFY_ARGUMENT
++**
++** Works just like gcmVERIFY_ARGUMENT, but is only valid in debug mode.
++** Use this to verify arguments inside non-public API functions.
++*/
++#if gcdDEBUG
++# define gcmDEBUG_VERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg) _gcmkVERIFY_ARGUMENT(gcm, arg)
++#else
++# define gcmDEBUG_VERIFY_ARGUMENT(arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT_RETURN
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT_RETURN(prefix, arg, value) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "gcmVERIFY_ARGUMENT_RETURN failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("value=%d", value); \
++ return value; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcm, arg, value)
++# define gcmkVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcmk, arg, value)
++
++#define MAX_LOOP_COUNT 0x7FFFFFFF
++
++/******************************************************************************\
++****************************** User Debug Option ******************************
++\******************************************************************************/
++
++/* User option. */
++typedef enum _gceDEBUG_MSG
++{
++ gcvDEBUG_MSG_NONE,
++ gcvDEBUG_MSG_ERROR,
++ gcvDEBUG_MSG_WARNING
++}
++gceDEBUG_MSG;
++
++typedef struct _gcsUSER_DEBUG_OPTION
++{
++ gceDEBUG_MSG debugMsg;
++}
++gcsUSER_DEBUG_OPTION;
++
++gcsUSER_DEBUG_OPTION *
++gcGetUserDebugOption(
++ void
++ );
++
++#if defined(ANDROID)
++struct _gcoOS_SymbolsList
++{
++#if gcdENABLE_3D
++ gcePATCH_ID patchId;
++#endif
++ const char * symList[10];
++};
++#endif
++
++#if gcdHAS_ELLIPSIS
++#define gcmUSER_DEBUG_MSG(level, ...) \
++ do \
++ { \
++ if (level <= gcGetUserDebugOption()->debugMsg) \
++ { \
++ gcoOS_Print(__VA_ARGS__); \
++ } \
++ } while (gcvFALSE)
++
++#define gcmUSER_DEBUG_ERROR_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_ERROR, "Error: " __VA_ARGS__)
++#define gcmUSER_DEBUG_WARNING_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_WARNING, "Warring: " __VA_ARGS__)
++#else
++#define gcmUSER_DEBUG_MSG
++#define gcmUSER_DEBUG_ERROR_MSG
++#define gcmUSER_DEBUG_WARNING_MSG
++#endif
++
++/*******************************************************************************
++**
++** A set of macros to aid state loading.
++**
++** ARGUMENTS:
++**
++** CommandBuffer Pointer to a gcoCMDBUF object.
++** StateDelta Pointer to a gcsSTATE_DELTA state delta structure.
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** PartOfContext Whether or not the state is a part of the context.
++** FixedPoint Whether or not the state is of the fixed point format.
++** Count Number of consecutive states to be loaded.
++** Address State address.
++** Data Data to be set to the state.
++*/
++
++/*----------------------------------------------------------------------------*/
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count) \
++ CommandBuffer->lastLoadStatePtr = gcmPTR_TO_UINT64(Memory); \
++ CommandBuffer->lastLoadStateAddress = Address; \
++ CommandBuffer->lastLoadStateCount = Count
++
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address) \
++ gcmASSERT( \
++ (gctUINT) (Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastLoadStatePtr, gctUINT32_PTR) - 1) \
++ == \
++ (gctUINT) (Address - CommandBuffer->lastLoadStateAddress) \
++ ); \
++ \
++ gcmASSERT(CommandBuffer->lastLoadStateCount > 0); \
++ \
++ CommandBuffer->lastLoadStateCount -= 1
++
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer) \
++ gcmASSERT(CommandBuffer->lastLoadStateCount == 0);
++
++# define gcmDEFINELOADSTATEBASE() \
++ gctUINT32_PTR LoadStateBase;
++
++# define gcmSETLOADSTATEBASE(CommandBuffer, OutSide) \
++ if (OutSide) \
++ {\
++ LoadStateBase = (gctUINT32_PTR)*OutSide; \
++ }\
++ else\
++ {\
++ LoadStateBase = (gctUINT_PTR)CommandBuffer->buffer;\
++ }
++
++
++# define gcmVERIFYLOADSTATEALIGNED(CommandBuffer, Memory) \
++ gcmASSERT(((Memory - LoadStateBase) & 1) == 0);
++
++# define gcmUNSETLOADSTATEBASE() \
++ LoadStateBase = LoadStateBase;
++
++#else
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count)
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address)
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer)
++
++# define gcmDEFINELOADSTATEBASE()
++# define gcmSETLOADSTATEBASE(CommandBuffer, OutSide)
++# define gcmVERIFYLOADSTATEALIGNED(CommandBuffer, Memory)
++# define gcmUNSETLOADSTATEBASE()
++
++#endif
++
++/*----------------------------------------------------------------------------*/
++
++#if gcdDUMP
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data) \
++ if (FixedPoint) \
++ { \
++ gcmDUMP(gcvNULL, "#[state.x 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ } \
++ else \
++ { \
++ gcmDUMP(gcvNULL, "#[state 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ }
++#else
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data)
++#endif
++
++#define gcmDEFINESTATEBUFFER(CommandBuffer, StateDelta, Memory, ReserveSize) \
++ gcmDEFINESECUREUSER() \
++ gctSIZE_T ReserveSize; \
++ gcoCMDBUF CommandBuffer; \
++ gctUINT32_PTR Memory; \
++ gcsSTATE_DELTA_PTR StateDelta
++
++#define gcmBEGINSTATEBUFFER(Hardware, CommandBuffer, StateDelta, Memory, ReserveSize) \
++{ \
++ gcmONERROR(gcoBUFFER_Reserve( \
++ Hardware->buffer, ReserveSize, gcvTRUE, gcvCOMMAND_3D, &CommandBuffer \
++ )); \
++ \
++ Memory = (gctUINT32_PTR) gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \
++ \
++ StateDelta = Hardware->delta; \
++ \
++ gcmBEGINSECUREUSER(); \
++}
++
++#define gcmENDSTATEBUFFER(Hardware, CommandBuffer, Memory, ReserveSize) \
++{ \
++ gcmENDSECUREUSER(); \
++ \
++ gcmASSERT( \
++ gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT8_PTR) + ReserveSize \
++ == \
++ (gctUINT8_PTR) Memory \
++ ); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, Count) \
++{ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++ gcmASSERT((gctUINT32)Count <= 1024); \
++ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count); \
++ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmENDSTATEBATCH(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ gcmSAFECASTSIZET(__temp_data32__, Data); \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, 0, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, Mask, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++
++#define gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETFILLER(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ Memory += 1; \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++
++#define gcmSETSINGLECTRLSTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++
++
++#define gcmSETSEMASTALLPIPE(StateDelta, CommandBuffer, Memory, Data) \
++{ \
++ gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, gcvFALSE, AQSemaphoreRegAddrs, Data); \
++ \
++ *Memory++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \
++ \
++ *Memory++ = Data; \
++ \
++ gcmDUMP(gcvNULL, "#[stall 0x%08X 0x%08X]", \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END), \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE)); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*******************************************************************************
++**
++** gcmSETSTARTDECOMMAND
++**
++** Form a START_DE command.
++**
++** ARGUMENTS:
++**
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** Count Number of the rectangles.
++*/
++
++#define gcmSETSTARTDECOMMAND(Memory, Count) \
++{ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \
++ \
++ *Memory++ = 0xDEADDEED; \
++}
++
++/*****************************************
++** Temp command buffer macro
++*/
++#define gcmDEFINESTATEBUFFER_NEW(CommandBuffer, StateDelta, Memory) \
++ gcmDEFINESECUREUSER() \
++ gcmDEFINELOADSTATEBASE() \
++ gcsTEMPCMDBUF CommandBuffer = gcvNULL; \
++ gctUINT32_PTR Memory; \
++ gcsSTATE_DELTA_PTR StateDelta
++
++
++#define gcmBEGINSTATEBUFFER_NEW(Hardware, CommandBuffer, StateDelta, Memory, OutSide) \
++{ \
++ if (OutSide) \
++ {\
++ Memory = (gctUINT32_PTR)*OutSide; \
++ }\
++ else \
++ {\
++ gcmONERROR(gcoBUFFER_StartTEMPCMDBUF( \
++ Hardware->buffer, &CommandBuffer \
++ ));\
++ \
++ Memory = (gctUINT32_PTR)(CommandBuffer->buffer); \
++ \
++ }\
++ StateDelta = Hardware->delta; \
++ \
++ gcmBEGINSECUREUSER(); \
++ gcmSETLOADSTATEBASE(CommandBuffer,OutSide);\
++}
++
++#define gcmENDSTATEBUFFER_NEW(Hardware, CommandBuffer, Memory, OutSide) \
++{ \
++ gcmENDSECUREUSER(); \
++ \
++ if (OutSide) \
++ {\
++ *OutSide = Memory; \
++ }\
++ else \
++ {\
++ CommandBuffer->currentByteSize = (gctUINT32)((gctUINT8_PTR)Memory - \
++ (gctUINT8_PTR)CommandBuffer->buffer); \
++ \
++ gcmONERROR(gcoBUFFER_EndTEMPCMDBUF(Hardware->buffer));\
++ }\
++ gcmUNSETLOADSTATEBASE()\
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, Count) \
++{ \
++ gcmVERIFYLOADSTATEALIGNED(CommandBuffer,Memory);\
++ gcmASSERT((gctUINT32)Count <= 1024); \
++ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmENDSTATEBATCH_NEW(CommandBuffer, Memory) \
++ gcmVERIFYLOADSTATEALIGNED(CommandBuffer,Memory);
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSTATEDATA_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, 0, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, Mask, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++
++#define gcmSETCTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETFILLER_NEW(CommandBuffer, Memory) \
++{ \
++ Memory += 1; \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSINGLESTATE_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++
++#define gcmSETSINGLECTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETCTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, Address, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++
++
++#define gcmSETSEMASTALLPIPE_NEW(StateDelta, CommandBuffer, Memory, Data) \
++{ \
++ gcmSETSINGLESTATE_NEW(StateDelta, CommandBuffer, Memory, gcvFALSE, AQSemaphoreRegAddrs, Data); \
++ \
++ *Memory++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \
++ \
++ *Memory++ = Data; \
++ \
++ gcmDUMP(gcvNULL, "#[stall 0x%08X 0x%08X]", \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END), \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE)); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETSTARTDECOMMAND_NEW(CommandBuffer, Memory, Count) \
++{ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \
++ \
++ *Memory++ = 0xDEADDEED; \
++ \
++}
++
++#define gcmSETSTATEDATA_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSINGLESTATE_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++#define gcmSETSTATEDATA_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ gcmSAFECASTSIZET(__temp_data32__, Data); \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSINGLESTATE_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmDEFINESTATEBUFFER_NEW_FAST(CommandBuffer, Memory) \
++ gcmDEFINESECUREUSER() \
++ gcmDEFINELOADSTATEBASE() \
++ gcsTEMPCMDBUF CommandBuffer = gcvNULL; \
++ gctUINT32_PTR Memory;
++
++#define gcmDEFINESTATEBUFFER_FAST(CommandBuffer, Memory, ReserveSize) \
++ gcmDEFINESECUREUSER() \
++ gctSIZE_T ReserveSize; \
++ gcoCMDBUF CommandBuffer; \
++ gctUINT32_PTR Memory;
++
++#define gcmBEGINSTATEBUFFER_FAST(Hardware, CommandBuffer, Memory, ReserveSize) \
++{ \
++ gcmONERROR(gcoBUFFER_Reserve( \
++ Hardware->buffer, ReserveSize, gcvTRUE, &CommandBuffer \
++ )); \
++ \
++ Memory = (gctUINT32_PTR) gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \
++ \
++ gcmBEGINSECUREUSER(); \
++}
++
++#define gcmBEGINSTATEBUFFER_NEW_FAST(Hardware, CommandBuffer, Memory, OutSide) \
++{ \
++ if (OutSide) \
++ {\
++ Memory = (gctUINT32_PTR)*OutSide; \
++ }\
++ else \
++ {\
++ gcmONERROR(gcoBUFFER_StartTEMPCMDBUF( \
++ Hardware->buffer, &CommandBuffer \
++ ));\
++ \
++ Memory = (gctUINT32_PTR)(CommandBuffer->buffer); \
++ \
++ }\
++ \
++ gcmBEGINSECUREUSER(); \
++ gcmSETLOADSTATEBASE(CommandBuffer,OutSide);\
++}
++/*******************************************************************************
++**
++** gcmCONFIGUREUNIFORMS
++**
++** Configure uniforms according to chip and numConstants.
++*/
++#if !gcdENABLE_UNIFIED_CONSTANT
++#define gcmCONFIGUREUNIFORMS(ChipModel, ChipRevision, NumConstants, \
++ UnifiedConst, VsConstBase, PsConstBase, VsConstMax, PsConstMax, ConstMax) \
++{ \
++ if (ChipModel == gcv2000 && ChipRevision == 0x5118) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ else if (NumConstants == 320) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */ \
++ else if (NumConstants > 256 && ChipModel == gcv1000) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ else if (NumConstants > 256) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 256; \
++ ConstMax = 512; \
++ } \
++ else if (NumConstants == 256) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 256; \
++ ConstMax = 512; \
++ } \
++ else \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 168; \
++ PsConstMax = 64; \
++ ConstMax = 232; \
++ } \
++}
++#else
++#define gcmCONFIGUREUNIFORMS(ChipModel, ChipRevision, NumConstants, \
++ UnifiedConst, VsConstBase, PsConstBase, VsConstMax, PsConstMax, ConstMax) \
++{ \
++ if (NumConstants > 256) \
++ { \
++ UnifiedConst = gcvTRUE; \
++ VsConstBase = gcregSHUniformsRegAddrs; \
++ PsConstBase = gcregSHUniformsRegAddrs; \
++ ConstMax = NumConstants; \
++ VsConstMax = 256; \
++ PsConstMax = ConstMax - VsConstMax; \
++ } \
++ else if (NumConstants == 256) \
++ { \
++ if (ChipModel == gcv2000 && ChipRevision == 0x5118) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ else \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 256; \
++ ConstMax = 512; \
++ } \
++ } \
++ else \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 168; \
++ PsConstMax = 64; \
++ ConstMax = 232; \
++ } \
++}
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_base_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_driver.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_driver.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_driver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_driver.h 2016-06-19 22:11:55.153149980 +0200
+@@ -0,0 +1,1064 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_driver_h_
++#define __gc_hal_driver_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_driver_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++#define IOCTL_GCHAL_KERNEL_INTERFACE 30001
++#define IOCTL_GCHAL_TERMINATE 30002
++
++#undef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++typedef enum _gceHAL_COMMAND_CODES
++{
++ /* Generic query. */
++ gcvHAL_QUERY_VIDEO_MEMORY,
++ gcvHAL_QUERY_CHIP_IDENTITY,
++
++ /* Contiguous memory. */
++ gcvHAL_ALLOCATE_NON_PAGED_MEMORY,
++ gcvHAL_FREE_NON_PAGED_MEMORY,
++ gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY,
++ gcvHAL_FREE_CONTIGUOUS_MEMORY,
++
++ /* Video memory allocation. */
++ gcvHAL_ALLOCATE_VIDEO_MEMORY, /* Enforced alignment. */
++ gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY, /* No alignment. */
++ gcvHAL_RELEASE_VIDEO_MEMORY,
++
++ /* Physical-to-logical mapping. */
++ gcvHAL_MAP_MEMORY,
++ gcvHAL_UNMAP_MEMORY,
++
++ /* Logical-to-physical mapping. */
++ gcvHAL_MAP_USER_MEMORY,
++ gcvHAL_UNMAP_USER_MEMORY,
++
++ /* Surface lock/unlock. */
++ gcvHAL_LOCK_VIDEO_MEMORY,
++ gcvHAL_UNLOCK_VIDEO_MEMORY,
++
++ /* Event queue. */
++ gcvHAL_EVENT_COMMIT,
++
++ gcvHAL_USER_SIGNAL,
++ gcvHAL_SIGNAL,
++ gcvHAL_WRITE_DATA,
++
++ gcvHAL_COMMIT,
++ gcvHAL_STALL,
++
++ gcvHAL_READ_REGISTER,
++ gcvHAL_WRITE_REGISTER,
++
++ gcvHAL_GET_PROFILE_SETTING,
++ gcvHAL_SET_PROFILE_SETTING,
++
++ gcvHAL_READ_ALL_PROFILE_REGISTERS,
++ gcvHAL_PROFILE_REGISTERS_2D,
++#if VIVANTE_PROFILER_PERDRAW
++ gcvHAL_READ_PROFILER_REGISTER_SETTING,
++#endif
++
++ /* Power management. */
++ gcvHAL_SET_POWER_MANAGEMENT_STATE,
++ gcvHAL_QUERY_POWER_MANAGEMENT_STATE,
++
++ gcvHAL_GET_BASE_ADDRESS,
++
++ gcvHAL_SET_IDLE, /* reserved */
++
++ /* Queries. */
++ gcvHAL_QUERY_KERNEL_SETTINGS,
++
++ /* Reset. */
++ gcvHAL_RESET,
++
++ /* Map physical address into handle. */
++ gcvHAL_MAP_PHYSICAL,
++
++ /* Debugger stuff. */
++ gcvHAL_DEBUG,
++
++ /* Cache stuff. */
++ gcvHAL_CACHE,
++
++ /* TimeStamp */
++ gcvHAL_TIMESTAMP,
++
++ /* Database. */
++ gcvHAL_DATABASE,
++
++ /* Version. */
++ gcvHAL_VERSION,
++
++ /* Chip info */
++ gcvHAL_CHIP_INFO,
++
++ /* Process attaching/detaching. */
++ gcvHAL_ATTACH,
++ gcvHAL_DETACH,
++
++ /* Composition. */
++ gcvHAL_COMPOSE,
++
++ /* Set timeOut value */
++ gcvHAL_SET_TIMEOUT,
++
++ /* Frame database. */
++ gcvHAL_GET_FRAME_INFO,
++
++ gcvHAL_QUERY_COMMAND_BUFFER,
++
++ gcvHAL_COMMIT_DONE,
++
++ /* GPU and event dump */
++ gcvHAL_DUMP_GPU_STATE,
++ gcvHAL_DUMP_EVENT,
++
++ /* Virtual command buffer. */
++ gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER,
++ gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER,
++
++ /* FSCALE_VAL. */
++ gcvHAL_SET_FSCALE_VALUE,
++ gcvHAL_GET_FSCALE_VALUE,
++
++ gcvHAL_NAME_VIDEO_MEMORY,
++ gcvHAL_IMPORT_VIDEO_MEMORY,
++
++ /* Reset time stamp. */
++ gcvHAL_QUERY_RESET_TIME_STAMP,
++
++ /* Multi-GPU read/write. */
++ gcvHAL_READ_REGISTER_EX,
++ gcvHAL_WRITE_REGISTER_EX,
++
++ /* Sync point operations. */
++ gcvHAL_SYNC_POINT,
++
++ /* Create native fence and return its fd. */
++ gcvHAL_CREATE_NATIVE_FENCE,
++
++ /* Destory MMU. */
++ gcvHAL_DESTROY_MMU,
++
++ /* Shared buffer. */
++ gcvHAL_SHBUF,
++
++ /* Config power management. */
++ gcvHAL_CONFIG_POWER_MANAGEMENT,
++
++ /* Connect a video node to an OS native fd. */
++ gcvHAL_GET_VIDEO_MEMORY_FD,
++}
++gceHAL_COMMAND_CODES;
++
++/******************************************************************************\
++****************************** Interface Structure *****************************
++\******************************************************************************/
++
++#define gcdMAX_PROFILE_FILE_NAME 128
++
++/* Kernel settings. */
++typedef struct _gcsKERNEL_SETTINGS
++{
++ /* Used RealTime signal between kernel and user. */
++ gctINT signal;
++}
++gcsKERNEL_SETTINGS;
++
++
++/* gcvHAL_QUERY_CHIP_IDENTITY */
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY * gcsHAL_QUERY_CHIP_IDENTITY_PTR;
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY
++{
++
++ /* Chip model. */
++ gceCHIPMODEL chipModel;
++
++ /* Revision value.*/
++ gctUINT32 chipRevision;
++
++ /* Supported feature fields. */
++ gctUINT32 chipFeatures;
++
++ /* Supported minor feature fields. */
++ gctUINT32 chipMinorFeatures;
++
++ /* Supported minor feature 1 fields. */
++ gctUINT32 chipMinorFeatures1;
++
++ /* Supported minor feature 2 fields. */
++ gctUINT32 chipMinorFeatures2;
++
++ /* Supported minor feature 3 fields. */
++ gctUINT32 chipMinorFeatures3;
++
++ /* Supported minor feature 4 fields. */
++ gctUINT32 chipMinorFeatures4;
++
++ /* Supported minor feature 5 fields. */
++ gctUINT32 chipMinorFeatures5;
++
++ /* Number of streams supported. */
++ gctUINT32 streamCount;
++
++ /* Total number of temporary registers per thread. */
++ gctUINT32 registerMax;
++
++ /* Maximum number of threads. */
++ gctUINT32 threadCount;
++
++ /* Number of shader cores. */
++ gctUINT32 shaderCoreCount;
++
++ /* Size of the vertex cache. */
++ gctUINT32 vertexCacheSize;
++
++ /* Number of entries in the vertex output buffer. */
++ gctUINT32 vertexOutputBufferSize;
++
++ /* Number of pixel pipes. */
++ gctUINT32 pixelPipes;
++
++ /* Number of instructions. */
++ gctUINT32 instructionCount;
++
++ /* Number of constants. */
++ gctUINT32 numConstants;
++
++ /* Buffer size */
++ gctUINT32 bufferSize;
++
++ /* Number of varyings */
++ gctUINT32 varyingsCount;
++
++ /* Supertile layout style in hardware */
++ gctUINT32 superTileMode;
++
++ /* Special control bits for 2D chip. */
++ gctUINT32 chip2DControl;
++
++ /* Product ID */
++ gctUINT32 productID;
++}
++gcsHAL_QUERY_CHIP_IDENTITY;
++
++/* gcvHAL_COMPOSE. */
++typedef struct _gcsHAL_COMPOSE * gcsHAL_COMPOSE_PTR;
++typedef struct _gcsHAL_COMPOSE
++{
++ /* Composition state buffer. */
++ gctUINT64 physical;
++ gctUINT64 logical;
++ gctUINT offset;
++ gctUINT size;
++
++ /* Composition end signal. */
++ gctUINT64 process;
++ gctUINT64 signal;
++
++ /* User signals. */
++ gctUINT64 userProcess;
++ gctUINT64 userSignal1;
++ gctUINT64 userSignal2;
++}
++gcsHAL_COMPOSE;
++
++
++typedef struct _gcsHAL_INTERFACE
++{
++ /* Command code. */
++ gceHAL_COMMAND_CODES command;
++
++ /* Hardware type. */
++ gceHARDWARE_TYPE hardwareType;
++
++ /* Status value. */
++ gceSTATUS status;
++
++ /* Handle to this interface channel. */
++ gctUINT64 handle;
++
++ /* Pid of the client. */
++ gctUINT32 pid;
++
++ /* Union of command structures. */
++ union _u
++ {
++ /* gcvHAL_GET_BASE_ADDRESS */
++ struct _gcsHAL_GET_BASE_ADDRESS
++ {
++ /* Physical memory address of internal memory. */
++ OUT gctUINT32 baseAddress;
++ }
++ GetBaseAddress;
++
++ /* gcvHAL_QUERY_VIDEO_MEMORY */
++ struct _gcsHAL_QUERY_VIDEO_MEMORY
++ {
++ /* Physical memory address of internal memory. Just a name. */
++ OUT gctUINT32 internalPhysical;
++
++ /* Size in bytes of internal memory. */
++ OUT gctUINT64 internalSize;
++
++ /* Physical memory address of external memory. Just a name. */
++ OUT gctUINT32 externalPhysical;
++
++ /* Size in bytes of external memory.*/
++ OUT gctUINT64 externalSize;
++
++ /* Physical memory address of contiguous memory. Just a name. */
++ OUT gctUINT32 contiguousPhysical;
++
++ /* Size in bytes of contiguous memory.*/
++ OUT gctUINT64 contiguousSize;
++ }
++ QueryVideoMemory;
++
++ /* gcvHAL_QUERY_CHIP_IDENTITY */
++ gcsHAL_QUERY_CHIP_IDENTITY QueryChipIdentity;
++
++ /* gcvHAL_MAP_MEMORY */
++ struct _gcsHAL_MAP_MEMORY
++ {
++ /* Physical memory address to map. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to map. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory. */
++ OUT gctUINT64 logical;
++ }
++ MapMemory;
++
++ /* gcvHAL_UNMAP_MEMORY */
++ struct _gcsHAL_UNMAP_MEMORY
++ {
++ /* Physical memory address to unmap. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to unmap. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory to unmap. */
++ IN gctUINT64 logical;
++ }
++ UnmapMemory;
++
++ /* gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_LINEAR_VIDEO_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT bytes;
++
++ /* Buffer alignment. */
++ IN gctUINT alignment;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Flag of allocation. */
++ IN gctUINT32 flag;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory. */
++ OUT gctUINT32 node;
++ }
++ AllocateLinearVideoMemory;
++
++ /* gcvHAL_ALLOCATE_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIDEO_MEMORY
++ {
++ /* Width of rectangle to allocate. */
++ IN OUT gctUINT width;
++
++ /* Height of rectangle to allocate. */
++ IN OUT gctUINT height;
++
++ /* Depth of rectangle to allocate. */
++ IN gctUINT depth;
++
++ /* Format rectangle to allocate in gceSURF_FORMAT. */
++ IN gceSURF_FORMAT format;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory. */
++ OUT gctUINT32 node;
++ }
++ AllocateVideoMemory;
++
++ /* gcvHAL_RELEASE_VIDEO_MEMORY */
++ struct _gcsHAL_RELEASE_VIDEO_MEMORY
++ {
++ /* Allocated video memory. */
++ IN gctUINT32 node;
++ }
++ ReleaseVideoMemory;
++
++ /* gcvHAL_LOCK_VIDEO_MEMORY */
++ struct _gcsHAL_LOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory. */
++ IN gctUINT32 node;
++
++ /* Cache configuration. */
++ /* Only gcvPOOL_CONTIGUOUS and gcvPOOL_VIRUTAL
++ ** can be configured */
++ IN gctBOOL cacheable;
++
++ /* Hardware specific address. */
++ OUT gctUINT32 address;
++
++ /* Mapped logical address. */
++ OUT gctUINT64 memory;
++
++ /* Customer priviate handle*/
++ OUT gctUINT32 gid;
++
++ /* Bus address of a contiguous video node. */
++ OUT gctUINT64 physicalAddress;
++ }
++ LockVideoMemory;
++
++ /* gcvHAL_UNLOCK_VIDEO_MEMORY */
++ struct _gcsHAL_UNLOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++
++ /* Type of surface. */
++ IN gceSURF_TYPE type;
++
++ /* Flag to unlock surface asynchroneously. */
++ IN OUT gctBOOL asynchroneous;
++ }
++ UnlockVideoMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateNonPagedMemory;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeNonPagedMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateVirtualCommandBuffer;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeVirtualCommandBuffer;
++
++ /* gcvHAL_EVENT_COMMIT. */
++ struct _gcsHAL_EVENT_COMMIT
++ {
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++ }
++ Event;
++
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_COMMIT
++ {
++ /* Context buffer object gckCONTEXT. */
++ IN gctUINT64 context;
++
++ /* Command buffer gcoCMDBUF. */
++ IN gctUINT64 commandBuffer;
++
++ /* State delta buffer in gcsSTATE_DELTA. */
++ gctUINT64 delta;
++
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++ }
++ Commit;
++
++ /* gcvHAL_MAP_USER_MEMORY */
++ struct _gcsHAL_MAP_USER_MEMORY
++ {
++ /* Base address of user memory to map. */
++ IN gctUINT64 memory;
++
++ /* Physical address of user memory to map. */
++ IN gctUINT32 physical;
++
++ /* Size of user memory in bytes to map. */
++ IN gctUINT64 size;
++
++ /* Info record required by gcvHAL_UNMAP_USER_MEMORY. Just a name. */
++ OUT gctUINT32 info;
++
++ /* Physical address of mapped memory. */
++ OUT gctUINT32 address;
++ }
++ MapUserMemory;
++
++ /* gcvHAL_UNMAP_USER_MEMORY */
++ struct _gcsHAL_UNMAP_USER_MEMORY
++ {
++ /* Base address of user memory to unmap. */
++ IN gctUINT64 memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctUINT64 size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. Just a name. */
++ IN gctUINT32 info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++ }
++ UnmapUserMemory;
++ /* gcsHAL_USER_SIGNAL */
++ struct _gcsHAL_USER_SIGNAL
++ {
++ /* Command. */
++ gceUSER_SIGNAL_COMMAND_CODES command;
++
++ /* Signal ID. */
++ IN OUT gctINT id;
++
++ /* Reset mode. */
++ IN gctBOOL manualReset;
++
++ /* Wait timedout. */
++ IN gctUINT32 wait;
++
++ /* State. */
++ IN gctBOOL state;
++ }
++ UserSignal;
++
++ /* gcvHAL_SIGNAL. */
++ struct _gcsHAL_SIGNAL
++ {
++ /* Signal handle to signal gctSIGNAL. */
++ IN gctUINT64 signal;
++
++ /* Reserved gctSIGNAL. */
++ IN gctUINT64 auxSignal;
++
++ /* Process owning the signal gctHANDLE. */
++ IN gctUINT64 process;
++ /* Event generated from where of pipeline */
++ IN gceKERNEL_WHERE fromWhere;
++ }
++ Signal;
++
++ /* gcvHAL_WRITE_DATA. */
++ struct _gcsHAL_WRITE_DATA
++ {
++ /* Address to write data to. */
++ IN gctUINT32 address;
++
++ /* Data to write. */
++ IN gctUINT32 data;
++ }
++ WriteData;
++
++ /* gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_ALLOCATE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Hardware address of allocation. */
++ OUT gctUINT32 address;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateContiguousMemory;
++
++ /* gcvHAL_FREE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_FREE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeContiguousMemory;
++
++ /* gcvHAL_READ_REGISTER */
++ struct _gcsHAL_READ_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ OUT gctUINT32 data;
++ }
++ ReadRegisterData;
++
++ /* gcvHAL_WRITE_REGISTER */
++ struct _gcsHAL_WRITE_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ IN gctUINT32 data;
++ }
++ WriteRegisterData;
++
++#if VIVANTE_PROFILER
++ /* gcvHAL_GET_PROFILE_SETTING */
++ struct _gcsHAL_GET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ OUT gctBOOL enable;
++ }
++ GetProfileSetting;
++
++ /* gcvHAL_SET_PROFILE_SETTING */
++ struct _gcsHAL_SET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ IN gctBOOL enable;
++ }
++ SetProfileSetting;
++
++#if VIVANTE_PROFILER_PERDRAW
++ /* gcvHAL_READ_PROFILER_REGISTER_SETTING */
++ struct _gcsHAL_READ_PROFILER_REGISTER_SETTING
++ {
++ /*Should Clear Register*/
++ IN gctBOOL bclear;
++ }
++ SetProfilerRegisterClear;
++#endif
++
++ /* gcvHAL_READ_ALL_PROFILE_REGISTERS */
++ struct _gcsHAL_READ_ALL_PROFILE_REGISTERS
++ {
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++#endif
++
++ /* Data read. */
++ OUT gcsPROFILER_COUNTERS counters;
++ }
++ RegisterProfileData;
++
++ /* gcvHAL_PROFILE_REGISTERS_2D */
++ struct _gcsHAL_PROFILE_REGISTERS_2D
++ {
++ /* Data read in gcs2D_PROFILE. */
++ OUT gctUINT64 hwProfile2D;
++ }
++ RegisterProfileData2D;
++#endif
++
++ /* Power management. */
++ /* gcvHAL_SET_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_SET_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ IN gceCHIPPOWERSTATE state;
++ }
++ SetPowerManagement;
++
++ /* gcvHAL_QUERY_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_QUERY_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ OUT gceCHIPPOWERSTATE state;
++
++ /* Idle query. */
++ OUT gctBOOL isIdle;
++ }
++ QueryPowerManagement;
++
++ /* gcvHAL_QUERY_KERNEL_SETTINGS */
++ struct _gcsHAL_QUERY_KERNEL_SETTINGS
++ {
++ /* Settings.*/
++ OUT gcsKERNEL_SETTINGS settings;
++ }
++ QueryKernelSettings;
++
++ /* gcvHAL_MAP_PHYSICAL */
++ struct _gcsHAL_MAP_PHYSICAL
++ {
++ /* gcvTRUE to map, gcvFALSE to unmap. */
++ IN gctBOOL map;
++
++ /* Physical address. */
++ IN OUT gctUINT64 physical;
++ }
++ MapPhysical;
++
++ /* gcvHAL_DEBUG */
++ struct _gcsHAL_DEBUG
++ {
++ /* If gcvTRUE, set the debug information. */
++ IN gctBOOL set;
++ IN gctUINT32 level;
++ IN gctUINT32 zones;
++ IN gctBOOL enable;
++
++ IN gceDEBUG_MESSAGE_TYPE type;
++ IN gctUINT32 messageSize;
++
++ /* Message to print if not empty. */
++ IN gctCHAR message[80];
++ }
++ Debug;
++
++ /* gcvHAL_CACHE */
++ struct _gcsHAL_CACHE
++ {
++ IN gceCACHEOPERATION operation;
++ IN gctUINT64 process;
++ IN gctUINT64 logical;
++ IN gctUINT64 bytes;
++ IN gctUINT32 node;
++ }
++ Cache;
++
++ /* gcvHAL_TIMESTAMP */
++ struct _gcsHAL_TIMESTAMP
++ {
++ /* Timer select. */
++ IN gctUINT32 timer;
++
++ /* Timer request type (0-stop, 1-start, 2-send delta). */
++ IN gctUINT32 request;
++
++ /* Result of delta time in microseconds. */
++ OUT gctINT32 timeDelta;
++ }
++ TimeStamp;
++
++ /* gcvHAL_DATABASE */
++ struct _gcsHAL_DATABASE
++ {
++ /* Set to gcvTRUE if you want to query a particular process ID.
++ ** Set to gcvFALSE to query the last detached process. */
++ IN gctBOOL validProcessID;
++
++ /* Process ID to query. */
++ IN gctUINT32 processID;
++
++ /* Information. */
++ OUT gcuDATABASE_INFO vidMem;
++ OUT gcuDATABASE_INFO nonPaged;
++ OUT gcuDATABASE_INFO contiguous;
++ OUT gcuDATABASE_INFO gpuIdle;
++
++ /* Detail information about video memory. */
++ OUT gcuDATABASE_INFO vidMemPool[3];
++ }
++ Database;
++
++ /* gcvHAL_VERSION */
++ struct _gcsHAL_VERSION
++ {
++ /* Major version: N.n.n. */
++ OUT gctINT32 major;
++
++ /* Minor version: n.N.n. */
++ OUT gctINT32 minor;
++
++ /* Patch version: n.n.N. */
++ OUT gctINT32 patch;
++
++ /* Build version. */
++ OUT gctUINT32 build;
++ }
++ Version;
++
++ /* gcvHAL_CHIP_INFO */
++ struct _gcsHAL_CHIP_INFO
++ {
++ /* Chip count. */
++ OUT gctINT32 count;
++
++ /* Chip types. */
++ OUT gceHARDWARE_TYPE types[gcdCHIP_COUNT];
++ }
++ ChipInfo;
++
++ /* gcvHAL_ATTACH */
++ struct _gcsHAL_ATTACH
++ {
++ /* Handle of context buffer object. */
++ OUT gctUINT32 context;
++
++ /* Number of states in the buffer. */
++ OUT gctUINT64 stateCount;
++
++ /* Map context buffer to user or not. */
++ IN gctBOOL map;
++
++ /* Physical of context buffer. */
++ OUT gctUINT32 physicals[2];
++
++ /* Physical of context buffer. */
++ OUT gctUINT64 logicals[2];
++
++ /* Bytes of context buffer. */
++ OUT gctUINT32 bytes;
++ }
++ Attach;
++
++ /* gcvHAL_DETACH */
++ struct _gcsHAL_DETACH
++ {
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++ }
++ Detach;
++
++ /* gcvHAL_COMPOSE. */
++ gcsHAL_COMPOSE Compose;
++
++ /* gcvHAL_GET_FRAME_INFO. */
++ struct _gcsHAL_GET_FRAME_INFO
++ {
++ /* gcsHAL_FRAME_INFO* */
++ OUT gctUINT64 frameInfo;
++ }
++ GetFrameInfo;
++
++ /* gcvHAL_SET_TIME_OUT. */
++ struct _gcsHAL_SET_TIMEOUT
++ {
++ gctUINT32 timeOut;
++ }
++ SetTimeOut;
++
++#if gcdENABLE_VG
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_VGCOMMIT
++ {
++ /* Context buffer. gcsVGCONTEXT_PTR */
++ IN gctUINT64 context;
++
++ /* Command queue. gcsVGCMDQUEUE_PTR */
++ IN gctUINT64 queue;
++
++ /* Number of entries in the queue. */
++ IN gctUINT entryCount;
++
++ /* Task table. gcsTASK_MASTER_TABLE_PTR */
++ IN gctUINT64 taskTable;
++ }
++ VGCommit;
++
++ /* gcvHAL_QUERY_COMMAND_BUFFER */
++ struct _gcsHAL_QUERY_COMMAND_BUFFER
++ {
++ /* Command buffer attributes. */
++ OUT gcsCOMMAND_BUFFER_INFO information;
++ }
++ QueryCommandBuffer;
++
++#endif
++
++ struct _gcsHAL_SET_FSCALE_VALUE
++ {
++ IN gctUINT value;
++ }
++ SetFscaleValue;
++
++ struct _gcsHAL_GET_FSCALE_VALUE
++ {
++ OUT gctUINT value;
++ OUT gctUINT minValue;
++ OUT gctUINT maxValue;
++ }
++ GetFscaleValue;
++
++ struct _gcsHAL_NAME_VIDEO_MEMORY
++ {
++ IN gctUINT32 handle;
++ OUT gctUINT32 name;
++ }
++ NameVideoMemory;
++
++ struct _gcsHAL_IMPORT_VIDEO_MEMORY
++ {
++ IN gctUINT32 name;
++ OUT gctUINT32 handle;
++ }
++ ImportVideoMemory;
++
++ struct _gcsHAL_QUERY_RESET_TIME_STAMP
++ {
++ OUT gctUINT64 timeStamp;
++ }
++ QueryResetTimeStamp;
++
++ struct _gcsHAL_SYNC_POINT
++ {
++ /* Command. */
++ gceSYNC_POINT_COMMAND_CODES command;
++
++ /* Sync point. */
++ IN OUT gctUINT64 syncPoint;
++
++ /* From where. */
++ IN gceKERNEL_WHERE fromWhere;
++
++ /* Signaled state. */
++ OUT gctBOOL state;
++ }
++ SyncPoint;
++
++ struct _gcsHAL_CREATE_NATIVE_FENCE
++ {
++ /* Signal id to dup. */
++ IN gctUINT64 syncPoint;
++
++ /* Native fence file descriptor. */
++ OUT gctINT fenceFD;
++
++ }
++ CreateNativeFence;
++
++ struct _gcsHAL_DESTROY_MMU
++ {
++ /* Mmu object. */
++ IN gctUINT64 mmu;
++ }
++ DestroyMmu;
++
++ struct _gcsHAL_SHBUF
++ {
++ gceSHBUF_COMMAND_CODES command;
++
++ /* Shared buffer. */
++ IN OUT gctUINT64 id;
++
++ /* User data to be shared. */
++ IN gctUINT64 data;
++
++ /* Data size. */
++ IN OUT gctUINT32 bytes;
++ }
++ ShBuf;
++
++ struct _gcsHAL_CONFIG_POWER_MANAGEMENT
++ {
++ IN gctBOOL enable;
++ }
++ ConfigPowerManagement;
++
++ struct _gcsHAL_GET_VIDEO_MEMORY_FD
++ {
++ IN gctUINT32 handle;
++ OUT gctINT fd;
++ }
++ GetVideoMemoryFd;
++ }
++ u;
++}
++gcsHAL_INTERFACE;
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_driver_vg.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_driver_vg.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_driver_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_driver_vg.h 2016-06-19 22:11:55.153149980 +0200
+@@ -0,0 +1,265 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_driver_vg_h_
++#define __gc_hal_driver_vg_h_
++
++
++
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++/******************************************************************************\
++********************* Command buffer information structure. ********************
++\******************************************************************************/
++
++typedef struct _gcsCOMMAND_BUFFER_INFO * gcsCOMMAND_BUFFER_INFO_PTR;
++typedef struct _gcsCOMMAND_BUFFER_INFO
++{
++ /* FE command buffer interrupt ID. */
++ gctINT32 feBufferInt;
++
++ /* TS overflow interrupt ID. */
++ gctINT32 tsOverflowInt;
++
++ /* Alignment and mask for the buffer address. */
++ gctUINT addressMask;
++ gctUINT32 addressAlignment;
++
++ /* Alignment for each command. */
++ gctUINT32 commandAlignment;
++
++ /* Number of bytes required by the STATE command. */
++ gctUINT32 stateCommandSize;
++
++ /* Number of bytes required by the RESTART command. */
++ gctUINT32 restartCommandSize;
++
++ /* Number of bytes required by the FETCH command. */
++ gctUINT32 fetchCommandSize;
++
++ /* Number of bytes required by the CALL command. */
++ gctUINT32 callCommandSize;
++
++ /* Number of bytes required by the RETURN command. */
++ gctUINT32 returnCommandSize;
++
++ /* Number of bytes required by the EVENT command. */
++ gctUINT32 eventCommandSize;
++
++ /* Number of bytes required by the END command. */
++ gctUINT32 endCommandSize;
++
++ /* Number of bytes reserved at the tail of a static command buffer. */
++ gctUINT32 staticTailSize;
++
++ /* Number of bytes reserved at the tail of a dynamic command buffer. */
++ gctUINT32 dynamicTailSize;
++}
++gcsCOMMAND_BUFFER_INFO;
++
++/******************************************************************************\
++******************************** Task Structures *******************************
++\******************************************************************************/
++
++typedef enum _gceTASK
++{
++ gcvTASK_LINK,
++ gcvTASK_CLUSTER,
++ gcvTASK_INCREMENT,
++ gcvTASK_DECREMENT,
++ gcvTASK_SIGNAL,
++ gcvTASK_LOCKDOWN,
++ gcvTASK_UNLOCK_VIDEO_MEMORY,
++ gcvTASK_FREE_VIDEO_MEMORY,
++ gcvTASK_FREE_CONTIGUOUS_MEMORY,
++ gcvTASK_UNMAP_USER_MEMORY
++}
++gceTASK;
++
++typedef struct _gcsTASK_HEADER * gcsTASK_HEADER_PTR;
++typedef struct _gcsTASK_HEADER
++{
++ /* Task ID. */
++ IN gceTASK id;
++}
++gcsTASK_HEADER;
++
++typedef struct _gcsTASK_LINK * gcsTASK_LINK_PTR;
++typedef struct _gcsTASK_LINK
++{
++ /* Task ID (gcvTASK_LINK). */
++ IN gceTASK id;
++
++ /* Pointer to the next task container. */
++ IN gctPOINTER cotainer;
++
++ /* Pointer to the next task from the next task container. */
++ IN gcsTASK_HEADER_PTR task;
++}
++gcsTASK_LINK;
++
++typedef struct _gcsTASK_CLUSTER * gcsTASK_CLUSTER_PTR;
++typedef struct _gcsTASK_CLUSTER
++{
++ /* Task ID (gcvTASK_CLUSTER). */
++ IN gceTASK id;
++
++ /* Number of tasks in the cluster. */
++ IN gctUINT taskCount;
++}
++gcsTASK_CLUSTER;
++
++typedef struct _gcsTASK_INCREMENT * gcsTASK_INCREMENT_PTR;
++typedef struct _gcsTASK_INCREMENT
++{
++ /* Task ID (gcvTASK_INCREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to increment. */
++ IN gctUINT32 address;
++}
++gcsTASK_INCREMENT;
++
++typedef struct _gcsTASK_DECREMENT * gcsTASK_DECREMENT_PTR;
++typedef struct _gcsTASK_DECREMENT
++{
++ /* Task ID (gcvTASK_DECREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to decrement. */
++ IN gctUINT32 address;
++}
++gcsTASK_DECREMENT;
++
++typedef struct _gcsTASK_SIGNAL * gcsTASK_SIGNAL_PTR;
++typedef struct _gcsTASK_SIGNAL
++{
++ /* Task ID (gcvTASK_SIGNAL). */
++ IN gceTASK id;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++}
++gcsTASK_SIGNAL;
++
++typedef struct _gcsTASK_LOCKDOWN * gcsTASK_LOCKDOWN_PTR;
++typedef struct _gcsTASK_LOCKDOWN
++{
++ /* Task ID (gcvTASK_LOCKDOWN). */
++ IN gceTASK id;
++
++ /* Address of the user space counter. */
++ IN gctUINT32 userCounter;
++
++ /* Address of the kernel space counter. */
++ IN gctUINT32 kernelCounter;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++}
++gcsTASK_LOCKDOWN;
++
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY * gcsTASK_UNLOCK_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_UNLOCK_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++}
++gcsTASK_UNLOCK_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY * gcsTASK_FREE_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT32 node;
++}
++gcsTASK_FREE_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY * gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_CONTIGUOUS_MEMORY). */
++ IN gceTASK id;
++
++ /* Number of bytes allocated. */
++ IN gctSIZE_T bytes;
++
++ /* Physical address of allocation. */
++ IN gctPHYS_ADDR physical;
++
++ /* Logical address of allocation. */
++ IN gctPOINTER logical;
++}
++gcsTASK_FREE_CONTIGUOUS_MEMORY;
++
++typedef struct _gcsTASK_UNMAP_USER_MEMORY * gcsTASK_UNMAP_USER_MEMORY_PTR;
++typedef struct _gcsTASK_UNMAP_USER_MEMORY
++{
++ /* Task ID (gcvTASK_UNMAP_USER_MEMORY). */
++ IN gceTASK id;
++
++ /* Base address of user memory to unmap. */
++ IN gctPOINTER memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctSIZE_T size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. */
++ IN gctPOINTER info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++}
++gcsTASK_UNMAP_USER_MEMORY;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_dump.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_dump.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_dump.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_dump.h 2016-06-19 22:11:55.153149980 +0200
+@@ -0,0 +1,89 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_dump_h_
++#define __gc_hal_dump_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++** FILE LAYOUT:
++**
++** gcsDUMP_FILE structure
++**
++** gcsDUMP_DATA frame
++** gcsDUMP_DATA or gcDUMP_DATA_SIZE records rendingring the frame
++** gctUINT8 data[length]
++*/
++
++#define gcvDUMP_FILE_SIGNATURE gcmCC('g','c','D','B')
++
++typedef struct _gcsDUMP_FILE
++{
++ gctUINT32 signature; /* File signature */
++ gctSIZE_T length; /* Length of file */
++ gctUINT32 frames; /* Number of frames in file */
++}
++gcsDUMP_FILE;
++
++typedef enum _gceDUMP_TAG
++{
++ gcvTAG_SURFACE = gcmCC('s','u','r','f'),
++ gcvTAG_FRAME = gcmCC('f','r','m',' '),
++ gcvTAG_COMMAND = gcmCC('c','m','d',' '),
++ gcvTAG_INDEX = gcmCC('i','n','d','x'),
++ gcvTAG_STREAM = gcmCC('s','t','r','m'),
++ gcvTAG_TEXTURE = gcmCC('t','e','x','t'),
++ gcvTAG_RENDER_TARGET = gcmCC('r','n','d','r'),
++ gcvTAG_DEPTH = gcmCC('z','b','u','f'),
++ gcvTAG_RESOLVE = gcmCC('r','s','l','v'),
++ gcvTAG_DELETE = gcmCC('d','e','l',' '),
++ gcvTAG_BUFOBJ = gcmCC('b','u','f','o'),
++}
++gceDUMP_TAG;
++
++typedef struct _gcsDUMP_SURFACE
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctUINT32 address; /* Address of the surface. */
++ gctINT16 width; /* Width of surface. */
++ gctINT16 height; /* Height of surface. */
++ gceSURF_FORMAT format; /* Surface pixel format. */
++ gctSIZE_T length; /* Number of bytes inside the surface. */
++}
++gcsDUMP_SURFACE;
++
++typedef struct _gcsDUMP_DATA
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctSIZE_T length; /* Number of bytes of data. */
++ gctUINT32 address; /* Address for the data. */
++}
++gcsDUMP_DATA;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_dump_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_eglplatform.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_eglplatform.h 2016-06-19 22:11:55.153149980 +0200
+@@ -0,0 +1,651 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_eglplatform_h_
++#define __gc_hal_eglplatform_h_
++
++/* Include VDK types. */
++#include "gc_hal_types.h"
++#include "gc_hal_base.h"
++#include "gc_hal_eglplatform_type.h"
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#if defined(LINUX) && defined(EGL_API_DFB)
++#include <directfb.h>
++typedef struct _DFBDisplay * HALNativeDisplayType;
++typedef struct _DFBWindow * HALNativeWindowType;
++typedef struct _DFBPixmap * HALNativePixmapType;
++
++#elif defined(LINUX) && defined(EGL_API_FB)
++
++#if defined(EGL_API_WL)
++
++#if defined(__GNUC__)
++# define inline __inline__ /* GNU keyword. */
++#endif
++
++/* Wayland platform. */
++#include <wayland-egl.h>
++
++#define WL_EGL_NUM_BACKBUFFERS 3
++
++typedef struct _gcsWL_VIV_BUFFER
++{
++ struct wl_resource *wl_buffer;
++ gcoSURF surface;
++ gctINT32 width, height;
++} gcsWL_VIV_BUFFER;
++
++typedef struct _gcsWL_EGL_DISPLAY
++{
++ struct wl_display* wl_display;
++ struct wl_viv* wl_viv;
++ struct wl_registry *registry;
++ struct wl_event_queue *wl_queue;
++ gctINT swapInterval;
++} gcsWL_EGL_DISPLAY;
++
++typedef struct _gcsWL_EGL_BUFFER_INFO
++{
++ gctINT32 width;
++ gctINT32 height;
++ gctINT32 stride;
++ gceSURF_FORMAT format;
++ gcuVIDMEM_NODE_PTR node;
++ gcePOOL pool;
++ gctUINT bytes;
++ gcoSURF surface;
++ gcoSURF attached_surface;
++ gctINT32 invalidate;
++ gctBOOL locked;
++} gcsWL_EGL_BUFFER_INFO;
++
++typedef struct _gcsWL_EGL_BUFFER
++{
++ struct wl_buffer* wl_buffer;
++ gcsWL_EGL_BUFFER_INFO info;
++} gcsWL_EGL_BUFFER;
++
++typedef struct _gcsWL_EGL_WINDOW_INFO
++{
++ gctINT32 dx;
++ gctINT32 dy;
++ gctUINT width;
++ gctUINT height;
++ gctINT32 attached_width;
++ gctINT32 attached_height;
++ gceSURF_FORMAT format;
++ gctUINT bpp;
++} gcsWL_EGL_WINDOW_INFO;
++
++struct wl_egl_window
++{
++ gcsWL_EGL_DISPLAY* display;
++ gcsWL_EGL_BUFFER backbuffers[WL_EGL_NUM_BACKBUFFERS];
++ gcsWL_EGL_WINDOW_INFO info;
++ gctUINT current;
++ struct wl_surface* surface;
++ struct wl_callback* frame_callback;
++};
++
++typedef void* HALNativeDisplayType;
++typedef void* HALNativeWindowType;
++typedef void* HALNativePixmapType;
++#else
++/* Linux platform for FBDEV. */
++typedef struct _FBDisplay * HALNativeDisplayType;
++typedef struct _FBWindow * HALNativeWindowType;
++typedef struct _FBPixmap * HALNativePixmapType;
++#endif
++#elif defined(__ANDROID__) || defined(ANDROID)
++
++struct egl_native_pixmap_t;
++
++#if ANDROID_SDK_VERSION >= 9
++ #include <android/native_window.h>
++
++ typedef struct ANativeWindow* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t* HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#else
++ struct android_native_window_t;
++ typedef struct android_native_window_t* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t * HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#endif
++
++#elif defined(LINUX)
++/* X11 platform. */
++#include <X11/Xlib.h>
++#include <X11/Xutil.h>
++
++typedef Display * HALNativeDisplayType;
++typedef Window HALNativeWindowType;
++
++#ifdef CUSTOM_PIXMAP
++typedef void * HALNativePixmapType;
++#else
++typedef Pixmap HALNativePixmapType;
++#endif /* CUSTOM_PIXMAP */
++
++/* Rename some badly named X defines. */
++#ifdef Status
++# define XStatus int
++# undef Status
++#endif
++#ifdef Always
++# define XAlways 2
++# undef Always
++#endif
++#ifdef CurrentTime
++# undef CurrentTime
++# define XCurrentTime 0
++#endif
++
++#else
++
++#error "Platform not recognized"
++
++/* VOID */
++typedef void * HALNativeDisplayType;
++typedef void * HALNativeWindowType;
++typedef void * HALNativePixmapType;
++
++#endif
++
++/* define DUMMY according to the system */
++#if defined(EGL_API_WL)
++# define WL_DUMMY (31415926)
++# define EGL_DUMMY WL_DUMMY
++#elif defined(__ANDROID__) || defined(ANDROID)
++# define ANDROID_DUMMY (31415926)
++# define EGL_DUMMY ANDROID_DUMMY
++#else
++# define EGL_DUMMY (31415926)
++#endif
++
++/*******************************************************************************
++** Display. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_GetDisplay(
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayByIndex(
++ IN gctINT DisplayIndex,
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfo(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctSIZE_T * Physical,
++ OUT gctINT * Stride,
++ OUT gctINT * BitsPerPixel
++ );
++
++
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetNextDisplayInfoExByIndex(
++ IN gctINT Index,
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbuffer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtualEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER Context,
++ IN gcoSURF Surface,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT Interval
++);
++
++gceSTATUS
++gcoOS_SetSwapIntervalEx(
++ IN HALNativeDisplayType Display,
++ IN gctINT Interval,
++ IN gctPOINTER localDisplay);
++
++gceSTATUS
++gcoOS_GetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT_PTR Min,
++ IN gctINT_PTR Max
++);
++
++gceSTATUS
++gcoOS_DisplayBufferRegions(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT NumRects,
++ IN gctINT_PTR Rects
++ );
++
++gceSTATUS
++gcoOS_DestroyDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_InitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_DeinitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx2(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbufferEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_IsValidDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_GetNativeVisualId(
++ IN HALNativeDisplayType Display,
++ OUT gctINT* nativeVisualId
++ );
++
++gctBOOL
++gcoOS_SynchronousFlip(
++ IN HALNativeDisplayType Display
++ );
++
++/*******************************************************************************
++** Windows. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreateWindow(
++ IN HALNativeDisplayType Display,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height,
++ OUT HALNativeWindowType * Window
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset
++ );
++
++gceSTATUS
++gcoOS_DestroyWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_DrawImage(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_GetImage(
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ OUT gctINT * BitsPerPixel,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_DrawImageEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits,
++ IN gceSURF_FORMAT Format
++ );
++
++/*******************************************************************************
++** Pixmaps. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreatePixmap(
++ IN HALNativeDisplayType Display,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ OUT HALNativePixmapType * Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DrawPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_CopyPixmapBits(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctUINT DstWidth,
++ IN gctUINT DstHeight,
++ IN gctINT DstStride,
++ IN gceSURF_FORMAT DstFormat,
++ OUT gctPOINTER DstBits
++ );
++
++/*******************************************************************************
++** OS relative. ****************************************************************
++*/
++gceSTATUS
++gcoOS_LoadEGLLibrary(
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeEGLLibrary(
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_ShowWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_HideWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_SetWindowTitle(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_CapturePointer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_GetEvent(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT halEvent * Event
++ );
++
++gceSTATUS
++gcoOS_CreateClientBuffer(
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT Format,
++ IN gctINT Type,
++ OUT gctPOINTER * ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_GetClientBufferInfo(
++ IN gctPOINTER ClientBuffer,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyClientBuffer(
++ IN gctPOINTER ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_DestroyContext(
++ IN gctPOINTER Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_CreateContext(
++ IN gctPOINTER LocalDisplay,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_MakeCurrent(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType DrawDrawable,
++ IN HALNativeWindowType ReadDrawable,
++ IN gctPOINTER Context,
++ IN gcoSURF ResolveTarget
++ );
++
++gceSTATUS
++gcoOS_CreateDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++
++gceSTATUS
++gcoOS_DestroyDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++gceSTATUS
++gcoOS_SwapBuffers(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gcoSURF RenderTarget,
++ IN gcoSURF ResolveTarget,
++ IN gctPOINTER ResolveBits,
++ OUT gctUINT *Width,
++ OUT gctUINT *Height
++ );
++
++#ifdef EGL_API_DRI
++gceSTATUS
++gcoOS_ResizeWindow(
++ IN gctPOINTER localDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gctUINT Width,
++ IN gctUINT Height)
++ ;
++
++#ifdef USE_FREESCALE_EGL_ACCEL
++gceSTATUS
++gcoOS_SwapBuffersGeneric_Async(
++ IN gctPOINTER localDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gcoSURF RenderTarget,
++ IN gcoSURF ResolveTarget,
++ IN gctPOINTER ResolveBits,
++ OUT gctUINT *Width,
++ OUT gctUINT *Height,
++ IN void * resolveRect
++ );
++
++gceSTATUS
++gcoOS_DrawSurface(
++ IN gctPOINTER localDisplay,
++ IN HALNativeWindowType Drawable
++ );
++#endif
++
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h 2016-06-19 22:11:55.153149980 +0200
+@@ -0,0 +1,280 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_eglplatform_type_h_
++#define __gc_hal_eglplatform_type_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Events. *********************************************************************
++*/
++
++typedef enum _halEventType
++{
++ /* Keyboard event. */
++ HAL_KEYBOARD,
++
++ /* Mouse move event. */
++ HAL_POINTER,
++
++ /* Mouse button event. */
++ HAL_BUTTON,
++
++ /* Application close event. */
++ HAL_CLOSE,
++
++ /* Application window has been updated. */
++ HAL_WINDOW_UPDATE
++}
++halEventType;
++
++/* Scancodes for keyboard. */
++typedef enum _halKeys
++{
++ HAL_UNKNOWN = -1,
++
++ HAL_BACKSPACE = 0x08,
++ HAL_TAB,
++ HAL_ENTER = 0x0D,
++ HAL_ESCAPE = 0x1B,
++
++ HAL_SPACE = 0x20,
++ HAL_SINGLEQUOTE = 0x27,
++ HAL_PAD_ASTERISK = 0x2A,
++ HAL_COMMA = 0x2C,
++ HAL_HYPHEN,
++ HAL_PERIOD,
++ HAL_SLASH,
++ HAL_0,
++ HAL_1,
++ HAL_2,
++ HAL_3,
++ HAL_4,
++ HAL_5,
++ HAL_6,
++ HAL_7,
++ HAL_8,
++ HAL_9,
++ HAL_SEMICOLON = 0x3B,
++ HAL_EQUAL = 0x3D,
++ HAL_A = 0x41,
++ HAL_B,
++ HAL_C,
++ HAL_D,
++ HAL_E,
++ HAL_F,
++ HAL_G,
++ HAL_H,
++ HAL_I,
++ HAL_J,
++ HAL_K,
++ HAL_L,
++ HAL_M,
++ HAL_N,
++ HAL_O,
++ HAL_P,
++ HAL_Q,
++ HAL_R,
++ HAL_S,
++ HAL_T,
++ HAL_U,
++ HAL_V,
++ HAL_W,
++ HAL_X,
++ HAL_Y,
++ HAL_Z,
++ HAL_LBRACKET,
++ HAL_BACKSLASH,
++ HAL_RBRACKET,
++ HAL_BACKQUOTE = 0x60,
++
++ HAL_F1 = 0x80,
++ HAL_F2,
++ HAL_F3,
++ HAL_F4,
++ HAL_F5,
++ HAL_F6,
++ HAL_F7,
++ HAL_F8,
++ HAL_F9,
++ HAL_F10,
++ HAL_F11,
++ HAL_F12,
++
++ HAL_LCTRL,
++ HAL_RCTRL,
++ HAL_LSHIFT,
++ HAL_RSHIFT,
++ HAL_LALT,
++ HAL_RALT,
++ HAL_CAPSLOCK,
++ HAL_NUMLOCK,
++ HAL_SCROLLLOCK,
++ HAL_PAD_0,
++ HAL_PAD_1,
++ HAL_PAD_2,
++ HAL_PAD_3,
++ HAL_PAD_4,
++ HAL_PAD_5,
++ HAL_PAD_6,
++ HAL_PAD_7,
++ HAL_PAD_8,
++ HAL_PAD_9,
++ HAL_PAD_HYPHEN,
++ HAL_PAD_PLUS,
++ HAL_PAD_SLASH,
++ HAL_PAD_PERIOD,
++ HAL_PAD_ENTER,
++ HAL_SYSRQ,
++ HAL_PRNTSCRN,
++ HAL_BREAK,
++ HAL_UP,
++ HAL_LEFT,
++ HAL_RIGHT,
++ HAL_DOWN,
++ HAL_HOME,
++ HAL_END,
++ HAL_PGUP,
++ HAL_PGDN,
++ HAL_INSERT,
++ HAL_DELETE,
++ HAL_LWINDOW,
++ HAL_RWINDOW,
++ HAL_MENU,
++ HAL_POWER,
++ HAL_SLEEP,
++ HAL_WAKE
++}
++halKeys;
++
++/* Structure that defined keyboard mapping. */
++typedef struct _halKeyMap
++{
++ /* Normal key. */
++ halKeys normal;
++
++ /* Extended key. */
++ halKeys extended;
++}
++halKeyMap;
++
++/* Event structure. */
++typedef struct _halEvent
++{
++ /* Event type. */
++ halEventType type;
++
++ /* Event data union. */
++ union _halEventData
++ {
++ /* Event data for keyboard. */
++ struct _halKeyboard
++ {
++ /* Scancode. */
++ halKeys scancode;
++
++ /* ASCII characte of the key pressed. */
++ char key;
++
++ /* Flag whether the key was pressed (1) or released (0). */
++ char pressed;
++ }
++ keyboard;
++
++ /* Event data for pointer. */
++ struct _halPointer
++ {
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ pointer;
++
++ /* Event data for mouse buttons. */
++ struct _halButton
++ {
++ /* Left button state. */
++ int left;
++
++ /* Middle button state. */
++ int middle;
++
++ /* Right button state. */
++ int right;
++
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ button;
++ }
++ data;
++}
++halEvent;
++
++/* VFK_DISPLAY_INFO structure defining information returned by
++ vdkGetDisplayInfoEx. */
++typedef struct _halDISPLAY_INFO
++{
++ /* The size of the display in pixels. */
++ int width;
++ int height;
++
++ /* The stride of the dispay. -1 is returned if the stride is not known
++ ** for the specified display.*/
++ int stride;
++
++ /* The color depth of the display in bits per pixel. */
++ int bitsPerPixel;
++
++ /* The logical pointer to the display memory buffer. NULL is returned
++ ** if the pointer is not known for the specified display. */
++ void * logical;
++
++ /* The physical address of the display memory buffer. ~0 is returned
++ ** if the address is not known for the specified display. */
++ unsigned long physical;
++
++ int wrapFB; /* true if compositor, false otherwise. */
++
++ /* The color info of the display. */
++ unsigned int alphaLength;
++ unsigned int alphaOffset;
++ unsigned int redLength;
++ unsigned int redOffset;
++ unsigned int greenLength;
++ unsigned int greenOffset;
++ unsigned int blueLength;
++ unsigned int blueOffset;
++
++ /* Display flip support. */
++ int flip;
++}
++halDISPLAY_INFO;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_type_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_engine.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_engine.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_engine.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_engine.h 2016-06-19 22:11:55.153149980 +0200
+@@ -0,0 +1,2587 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_h_
++#define __gc_hal_engine_h_
++
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++
++#if gcdENABLE_3D
++#if gcdENABLE_VG
++#include "gc_hal_engine_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoSTREAM * gcoSTREAM;
++typedef struct _gcoVERTEX * gcoVERTEX;
++typedef struct _gcoTEXTURE * gcoTEXTURE;
++typedef struct _gcoINDEX * gcoINDEX;
++typedef struct _gcsVERTEX_ATTRIBUTES * gcsVERTEX_ATTRIBUTES_PTR;
++typedef struct _gcoVERTEXARRAY * gcoVERTEXARRAY;
++typedef struct _gcoBUFOBJ * gcoBUFOBJ;
++
++#define gcdATTRIBUTE_COUNT 16
++
++typedef enum _gcePROGRAM_STAGE
++{
++ gcvPROGRAM_STAGE_VERTEX = 0x0,
++ gcvPROGRAM_STAGE_TES = 0x1,
++ gcvPROGRAM_STAGE_TCS = 0x2,
++ gcvPROGRAM_STAGE_GEOMETRY = 0x3,
++ gcvPROGRAM_STAGE_FRAGMENT = 0x4,
++ gcvPROGRAM_STAGE_COMPUTE = 0x5,
++ gcvPROGRAM_STAGE_OPENCL = 0x6,
++ gcvPROGRAM_STAGE_LAST
++}
++gcePROGRAM_STAGE;
++
++typedef enum _gcePROGRAM_STAGE_BIT
++{
++ gcvPROGRAM_STAGE_VERTEX_BIT = 1 << gcvPROGRAM_STAGE_VERTEX,
++ gcvPROGRAM_STAGE_TES_BIT = 1 << gcvPROGRAM_STAGE_TES,
++ gcvPROGRAM_STAGE_TCS_BIT = 1 << gcvPROGRAM_STAGE_TCS,
++ gcvPROGRAM_STAGE_GEOMETRY_BIT = 1 << gcvPROGRAM_STAGE_GEOMETRY,
++ gcvPROGRAM_STAGE_FRAGMENT_BIT = 1 << gcvPROGRAM_STAGE_FRAGMENT,
++ gcvPROGRAM_STAGE_COMPUTE_BIT = 1 << gcvPROGRAM_STAGE_COMPUTE,
++ gcvPROGRAM_STAGE_OPENCL_BIT = 1 << gcvPROGRAM_STAGE_OPENCL,
++}
++gcePROGRAM_STAGE_BIT;
++
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++gceSTATUS
++gcoHAL_QueryShaderCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ );
++
++gceSTATUS
++gcoHAL_QueryShaderCapsEx(
++ IN gcoHAL Hal,
++ OUT gctUINT * ShaderCoreCount,
++ OUT gctUINT * ThreadCount,
++ OUT gctUINT * VertexInstructionCount,
++ OUT gctUINT * FragmentInstructionCount
++ );
++
++gceSTATUS
++gcoHAL_QuerySamplerBase(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * VertexCount,
++ OUT gctINT_PTR VertexBase,
++ OUT gctUINT32 * FragmentCount,
++ OUT gctINT_PTR FragmentBase
++ );
++
++gceSTATUS
++gcoHAL_QueryUniformBase(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * VertexBase,
++ OUT gctUINT32 * FragmentBase
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureMaxAniso(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxAnisoValue
++ );
++
++gceSTATUS
++gcoHAL_QueryStreamCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * MaxAttributes,
++ OUT gctUINT32 * MaxStreamSize,
++ OUT gctUINT32 * NumberOfStreams,
++ OUT gctUINT32 * Alignment
++ );
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*--------------------------------- gcoSURF 3D --------------------------------*/
++typedef enum _gceBLIT_FLAG
++{
++ gcvBLIT_FLAG_SKIP_DEPTH_WRITE = 0x1,
++ gcvBLIT_FLAG_SKIP_STENCIL_WRITE = 0x2,
++} gceBLIT_FLAG;
++
++typedef struct _gcsSURF_BLIT_ARGS
++{
++ gcoSURF srcSurface;
++ gctINT srcX, srcY, srcZ;
++ gctINT srcWidth, srcHeight, srcDepth;
++ gcoSURF dstSurface;
++ gctINT dstX, dstY, dstZ;
++ gctINT dstWidth, dstHeight, dstDepth;
++ gctBOOL xReverse;
++ gctBOOL yReverse;
++ gctBOOL scissorTest;
++ gcsRECT scissor;
++ gctUINT flags;
++}
++gcsSURF_BLIT_ARGS;
++
++
++
++
++/* Clear flags. */
++typedef enum _gceCLEAR
++{
++ gcvCLEAR_COLOR = 0x1,
++ gcvCLEAR_DEPTH = 0x2,
++ gcvCLEAR_STENCIL = 0x4,
++ gcvCLEAR_HZ = 0x8,
++ gcvCLEAR_HAS_VAA = 0x10,
++ gcvCLEAR_WITH_GPU_ONLY = 0x100,
++ gcvCLEAR_WITH_CPU_ONLY = 0x200,
++}
++gceCLEAR;
++
++typedef struct _gcsSURF_CLEAR_ARGS
++{
++ /*
++ ** Color to fill the color portion of the framebuffer when clear
++ ** is called.
++ */
++ struct {
++ gcuVALUE r;
++ gcuVALUE g;
++ gcuVALUE b;
++ gcuVALUE a;
++ /*
++ ** Color has multiple value type so we must specify it.
++ */
++ gceVALUE_TYPE valueType;
++ } color;
++
++ gcuVALUE depth;
++
++ gctUINT stencil;
++
++
++
++ /*
++ ** stencil bit-wise mask
++ */
++ gctUINT8 stencilMask;
++ /*
++ ** Depth Write Mask
++ */
++ gctBOOL depthMask;
++ /*
++ ** 4-bit channel Mask: ABGR:MSB->LSB
++ */
++ gctUINT8 colorMask;
++ /*
++ ** If ClearRect is NULL, it means full clear
++ */
++ gcsRECT_PTR clearRect;
++ /*
++ ** clear flags
++ */
++ gceCLEAR flags;
++
++ /*
++ ** Offset in surface to cube/array/3D
++ */
++ gctUINT32 offset;
++
++} gcsSURF_CLEAR_ARGS;
++
++
++typedef gcsSURF_CLEAR_ARGS* gcsSURF_CLEAR_ARGS_PTR;
++
++typedef struct _gscSURF_BLITDRAW_BLIT
++{
++ gcoSURF srcSurface;
++ gcoSURF dstSurface;
++ gcsRECT srcRect;
++ gcsRECT dstRect;
++ gceTEXTURE_FILTER filterMode;
++ gctBOOL xReverse;
++ gctBOOL yReverse;
++ gctBOOL scissorEnabled;
++ gcsRECT scissor;
++}gscSURF_BLITDRAW_BLIT;
++
++
++typedef enum _gceBLITDRAW_TYPE
++{
++ gcvBLITDRAW_CLEAR = 0,
++ gcvBLITDRAW_BLIT = 1,
++
++ /* last number, not a real type */
++ gcvBLITDRAW_NUM_TYPE
++ }
++gceBLITDRAW_TYPE;
++
++
++typedef struct _gscSURF_BLITDRAW_ARGS
++{
++ /* always the fist member */
++ gceHAL_ARG_VERSION version;
++
++ union _gcsSURF_BLITDRAW_ARGS_UNION
++ {
++ struct _gscSURF_BLITDRAW_ARG_v1
++ {
++ /* Whether it's clear or blit operation, can be extended. */
++ gceBLITDRAW_TYPE type;
++
++ union _gscSURF_BLITDRAW_UNION
++ {
++ gscSURF_BLITDRAW_BLIT blit;
++
++ struct _gscSURF_BLITDRAW_CLEAR
++ {
++ gcsSURF_CLEAR_ARGS clearArgs;
++ gcoSURF rtSurface;
++ gcoSURF dsSurface;
++ } clear;
++ } u;
++ } v1;
++ } uArgs;
++}
++gcsSURF_BLITDRAW_ARGS;
++
++
++typedef struct _gcsSURF_RESOLVE_ARGS
++{
++ gceHAL_ARG_VERSION version;
++ union _gcsSURF_RESOLVE_ARGS_UNION
++ {
++ struct _gcsSURF_RESOLVE_ARG_v1
++ {
++ gctBOOL yInverted;
++ }v1;
++ } uArgs;
++}
++gcsSURF_RESOLVE_ARGS;
++
++
++/* CPU Blit with format (including linear <-> tile) conversion*/
++gceSTATUS
++gcoSURF_BlitCPU(
++ gcsSURF_BLIT_ARGS* args
++ );
++
++
++gceSTATUS
++gcoSURF_BlitDraw(
++ IN gcsSURF_BLITDRAW_ARGS *args
++ );
++#endif /* gcdENABLE_3D */
++
++
++
++#if gcdENABLE_3D
++/* Clear surface function. */
++gceSTATUS
++gcoSURF_Clear(
++ IN gcoSURF Surface,
++ IN gcsSURF_CLEAR_ARGS_PTR clearArg
++ );
++
++/* Preserve pixels from source. */
++gceSTATUS
++gcoSURF_Preserve(
++ IN gcoSURF Source,
++ IN gcoSURF Dest,
++ IN gcsRECT_PTR MaskRect
++ );
++
++
++/* TO BE REMOVED */
++ gceSTATUS
++ depr_gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight
++ );
++
++ gceSTATUS
++ depr_gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resample surface. */
++gceSTATUS
++gcoSURF_Resample(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++/* Resolve surface. */
++gceSTATUS
++gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++gceSTATUS
++gcoSURF_ResolveEx(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsSURF_RESOLVE_ARGS *args
++ );
++
++
++/* Resolve rectangular area of a surface. */
++gceSTATUS
++gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resolve rectangular area of a surface. */
++gceSTATUS
++gcoSURF_ResolveRectEx(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize,
++ IN gcsSURF_RESOLVE_ARGS *args
++ );
++
++
++gceSTATUS
++gcoSURF_GetResolveAlignment(
++ IN gcoSURF Surface,
++ OUT gctUINT *originX,
++ OUT gctUINT *originY,
++ OUT gctUINT *sizeX,
++ OUT gctUINT *sizeY
++ );
++
++gceSTATUS
++gcoSURF_IsHWResolveable(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Set surface resolvability. */
++gceSTATUS
++gcoSURF_SetResolvability(
++ IN gcoSURF Surface,
++ IN gctBOOL Resolvable
++ );
++
++gceSTATUS
++gcoSURF_IsRenderable(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSURF_IsFormatRenderableAsRT(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSURF_GetFence(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoBUFOBJ_GetFence(
++ IN gcoBUFOBJ bufObj
++ );
++
++gceSTATUS
++gcoBUFOBJ_WaitFence(
++ IN gcoBUFOBJ bufObj
++ );
++
++gceSTATUS
++gcoBUFOBJ_IsFenceEnabled(
++ IN gcoBUFOBJ bufObj
++ );
++
++gceSTATUS
++gcoSURF_WaitFence(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSTREAM_GetFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoSTREAM_WaitFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoINDEX_GetFence(
++ IN gcoINDEX index
++ );
++
++gceSTATUS
++gcoINDEX_WaitFence(
++ IN gcoINDEX index
++ );
++
++gceSTATUS
++gcoSURF_3DBlitClearRect(
++ IN gcoSURF Surface,
++ IN gcsSURF_CLEAR_ARGS_PTR ClearArgs
++ );
++
++
++gceSTATUS
++gcoSURF_3DBlitBltRect(
++ IN gcoSURF SrcSurf,
++ IN gcoSURF DestSurf,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++gceSTATUS
++gcoSURF_3DBlitCopy(
++ IN gctUINT32 SrcAddress,
++ IN gctUINT32 DestAddress,
++ IN gctUINT32 Bytes
++ );
++
++
++/******************************************************************************\
++******************************** gcoINDEX Object *******************************
++\******************************************************************************/
++
++/* Construct a new gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoINDEX * Index
++ );
++
++/* Destroy a gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Destroy(
++ IN gcoINDEX Index
++ );
++
++/* Lock index in memory. */
++gceSTATUS
++gcoINDEX_Lock(
++ IN gcoINDEX Index,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Unlock index that was previously locked with gcoINDEX_Lock. */
++gceSTATUS
++gcoINDEX_Unlock(
++ IN gcoINDEX Index
++ );
++
++/* Upload index data into the memory. */
++gceSTATUS
++gcoINDEX_Load(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE IndexType,
++ IN gctUINT32 IndexCount,
++ IN gctPOINTER IndexBuffer
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_Bind(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_BindOffset(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset
++ );
++
++/* Free existing index buffer. */
++gceSTATUS
++gcoINDEX_Free(
++ IN gcoINDEX Index
++ );
++
++/* Upload data into an index buffer. */
++gceSTATUS
++gcoINDEX_Upload(
++ IN gcoINDEX Index,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload data into an index buffer starting at an offset. */
++gceSTATUS
++gcoINDEX_UploadOffset(
++ IN gcoINDEX Index,
++ IN gctSIZE_T Offset,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/*Merge index2 to index1 from 0, index2 must subset of inex1*/
++gceSTATUS
++gcoINDEX_Merge(
++ IN gcoINDEX Index1,
++ IN gcoINDEX Index2
++ );
++
++/*check if index buffer is enough for this draw*/
++gctBOOL
++gcoINDEX_CheckRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctINT Count,
++ IN gctUINT32 Indices
++ );
++
++/* Query the index capabilities. */
++gceSTATUS
++gcoINDEX_QueryCaps(
++ OUT gctBOOL * Index8,
++ OUT gctBOOL * Index16,
++ OUT gctBOOL * Index32,
++ OUT gctUINT * MaxIndex
++ );
++
++/* Determine the index range in the current index buffer. */
++gceSTATUS
++gcoINDEX_GetIndexRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Count,
++ OUT gctUINT32 * MinimumIndex,
++ OUT gctUINT32 * MaximumIndex
++ );
++
++/* Dynamic buffer management. */
++gceSTATUS
++gcoINDEX_SetDynamic(
++ IN gcoINDEX Index,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++/******************************************************************************\
++********************************** gco3D Object *********************************
++\******************************************************************************/
++
++/* Blending targets. */
++typedef enum _gceBLEND_UNIT
++{
++ gcvBLEND_SOURCE,
++ gcvBLEND_TARGET,
++}
++gceBLEND_UNIT;
++
++/* Construct a new gco3D object. */
++gceSTATUS
++gco3D_Construct(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++/* Destroy an gco3D object. */
++gceSTATUS
++gco3D_Destroy(
++ IN gco3D Engine
++ );
++
++/* Set 3D API type. */
++gceSTATUS
++gco3D_SetAPI(
++ IN gco3D Engine,
++ IN gceAPI ApiType
++ );
++
++/* Get 3D API type. */
++gceSTATUS
++gco3D_GetAPI(
++ IN gco3D Engine,
++ OUT gceAPI * ApiType
++ );
++
++/* Set render target. */
++gceSTATUS
++gco3D_SetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Unset render target. */
++gceSTATUS
++gco3D_UnsetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gco3D_SetTargetEx(
++ IN gco3D Engine,
++ IN gctUINT32 TargetIndex,
++ IN gcoSURF Surface,
++ IN gctUINT32 LayerIndex
++ );
++
++gceSTATUS
++gco3D_UnsetTargetEx(
++ IN gco3D Engine,
++ IN gctUINT32 TargetIndex,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gco3D_SetTargetOffsetEx(
++ IN gco3D Engine,
++ IN gctUINT32 TargetIndex,
++ IN gctSIZE_T Offset
++ );
++
++
++gceSTATUS
++gco3D_SetPSOutputMapping(
++ IN gco3D Engine,
++ IN gctINT32 * psOutputMapping
++ );
++
++
++/* Set depth buffer. */
++gceSTATUS
++gco3D_SetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gco3D_SetDepthBufferOffset(
++ IN gco3D Engine,
++ IN gctSIZE_T Offset
++ );
++
++/* Unset depth buffer. */
++gceSTATUS
++gco3D_UnsetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Set viewport. */
++gceSTATUS
++gco3D_SetViewport(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set scissors. */
++gceSTATUS
++gco3D_SetScissors(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set clear color. */
++gceSTATUS
++gco3D_SetClearColor(
++ IN gco3D Engine,
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++/* Set fixed point clear color. */
++gceSTATUS
++gco3D_SetClearColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point clear color. */
++gceSTATUS
++gco3D_SetClearColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set fixed point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Depth
++ );
++
++/* Set floating point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthF(
++ IN gco3D Engine,
++ IN gctFLOAT Depth
++ );
++
++/* Set clear stencil. */
++gceSTATUS
++gco3D_SetClearStencil(
++ IN gco3D Engine,
++ IN gctUINT32 Stencil
++ );
++
++/* Set shading mode. */
++gceSTATUS
++gco3D_SetShading(
++ IN gco3D Engine,
++ IN gceSHADING Shading
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_EnableBlending(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set blending function. */
++gceSTATUS
++gco3D_SetBlendFunction(
++ IN gco3D Engine,
++ IN gceBLEND_UNIT Unit,
++ IN gceBLEND_FUNCTION FunctionRGB,
++ IN gceBLEND_FUNCTION FunctionAlpha
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_SetBlendMode(
++ IN gco3D Engine,
++ IN gceBLEND_MODE ModeRGB,
++ IN gceBLEND_MODE ModeAlpha
++ );
++
++/* Set blending color. */
++gceSTATUS
++gco3D_SetBlendColor(
++ IN gco3D Engine,
++ IN gctUINT Red,
++ IN gctUINT Green,
++ IN gctUINT Blue,
++ IN gctUINT Alpha
++ );
++
++/* Set fixed point blending color. */
++gceSTATUS
++gco3D_SetBlendColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point blending color. */
++gceSTATUS
++gco3D_SetBlendColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set culling mode. */
++gceSTATUS
++gco3D_SetCulling(
++ IN gco3D Engine,
++ IN gceCULL Mode
++ );
++
++/* Enable point size */
++gceSTATUS
++gco3D_SetPointSizeEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set point sprite */
++gceSTATUS
++gco3D_SetPointSprite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set fill mode. */
++gceSTATUS
++gco3D_SetFill(
++ IN gco3D Engine,
++ IN gceFILL Mode
++ );
++
++/* Set depth compare mode. */
++gceSTATUS
++gco3D_SetDepthCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Enable depth writing. */
++gceSTATUS
++gco3D_EnableDepthWrite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth mode. */
++gceSTATUS
++gco3D_SetDepthMode(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeX(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFIXED_POINT Near,
++ IN gctFIXED_POINT Far
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeF(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Set last pixel enable */
++gceSTATUS
++gco3D_SetLastPixelEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth Bias and Scale */
++gceSTATUS
++gco3D_SetDepthScaleBiasX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT DepthScale,
++ IN gctFIXED_POINT DepthBias
++ );
++
++gceSTATUS
++gco3D_SetDepthScaleBiasF(
++ IN gco3D Engine,
++ IN gctFLOAT DepthScale,
++ IN gctFLOAT DepthBias
++ );
++
++/* Set depth near and far clipping plane. */
++gceSTATUS
++gco3D_SetDepthPlaneF(
++ IN gco3D Engine,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Enable or disable dithering. */
++gceSTATUS
++gco3D_EnableDither(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set color write enable bits. */
++gceSTATUS
++gco3D_SetColorWrite(
++ IN gco3D Engine,
++ IN gctUINT8 Enable
++ );
++
++/* Enable or disable early depth. */
++gceSTATUS
++gco3D_SetEarlyDepth(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Deprecated: Enable or disable all early depth operations. */
++gceSTATUS
++gco3D_SetAllEarlyDepthModes(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Enable or disable all early depth operations. */
++gceSTATUS
++gco3D_SetAllEarlyDepthModesEx(
++ IN gco3D Engine,
++ IN gctBOOL Disable,
++ IN gctBOOL DisableModify,
++ IN gctBOOL DisablePassZ
++ );
++
++/* Switch dynamic early mode */
++gceSTATUS
++gco3D_SwitchDynamicEarlyDepthMode(
++ IN gco3D Engine
++ );
++
++/* Set dynamic early mode */
++gceSTATUS
++gco3D_DisableDynamicEarlyDepthMode(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Enable or disable depth-only mode. */
++gceSTATUS
++gco3D_SetDepthOnly(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++typedef struct _gcsSTENCIL_INFO * gcsSTENCIL_INFO_PTR;
++typedef struct _gcsSTENCIL_INFO
++{
++ gceSTENCIL_MODE mode;
++
++ gctUINT8 maskFront;
++ gctUINT8 maskBack;
++ gctUINT8 writeMaskFront;
++ gctUINT8 writeMaskBack;
++
++ gctUINT8 referenceFront;
++
++ gceCOMPARE compareFront;
++ gceSTENCIL_OPERATION passFront;
++ gceSTENCIL_OPERATION failFront;
++ gceSTENCIL_OPERATION depthFailFront;
++
++ gctUINT8 referenceBack;
++ gceCOMPARE compareBack;
++ gceSTENCIL_OPERATION passBack;
++ gceSTENCIL_OPERATION failBack;
++ gceSTENCIL_OPERATION depthFailBack;
++}
++gcsSTENCIL_INFO;
++
++/* Set stencil mode. */
++gceSTATUS
++gco3D_SetStencilMode(
++ IN gco3D Engine,
++ IN gceSTENCIL_MODE Mode
++ );
++
++/* Set stencil mask. */
++gceSTATUS
++gco3D_SetStencilMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back mask. */
++gceSTATUS
++gco3D_SetStencilMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil reference. */
++gceSTATUS
++gco3D_SetStencilReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctBOOL Front
++ );
++
++/* Set stencil compare. */
++gceSTATUS
++gco3D_SetStencilCompare(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceCOMPARE Compare
++ );
++
++/* Set stencil operation on pass. */
++gceSTATUS
++gco3D_SetStencilPass(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on fail. */
++gceSTATUS
++gco3D_SetStencilFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on depth fail. */
++gceSTATUS
++gco3D_SetStencilDepthFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set all stencil states in one blow. */
++gceSTATUS
++gco3D_SetStencilAll(
++ IN gco3D Engine,
++ IN gcsSTENCIL_INFO_PTR Info
++ );
++
++typedef struct _gcsALPHA_INFO * gcsALPHA_INFO_PTR;
++typedef struct _gcsALPHA_INFO
++{
++ /* Alpha test states. */
++ gctBOOL test;
++ gceCOMPARE compare;
++ gctUINT8 reference;
++ gctFLOAT floatReference;
++
++ /* Alpha blending states. */
++ gctBOOL blend;
++
++ gceBLEND_FUNCTION srcFuncColor;
++ gceBLEND_FUNCTION srcFuncAlpha;
++ gceBLEND_FUNCTION trgFuncColor;
++ gceBLEND_FUNCTION trgFuncAlpha;
++
++ gceBLEND_MODE modeColor;
++ gceBLEND_MODE modeAlpha;
++
++ gctUINT32 color;
++}
++gcsALPHA_INFO;
++
++/* Enable or disable alpha test. */
++gceSTATUS
++gco3D_SetAlphaTest(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set alpha test compare. */
++gceSTATUS
++gco3D_SetAlphaCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Set alpha test reference in unsigned integer. */
++gceSTATUS
++gco3D_SetAlphaReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctFLOAT FloatReference
++ );
++
++/* Set alpha test reference in fixed point. */
++gceSTATUS
++gco3D_SetAlphaReferenceX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Reference
++ );
++
++/* Set alpha test reference in floating point. */
++gceSTATUS
++gco3D_SetAlphaReferenceF(
++ IN gco3D Engine,
++ IN gctFLOAT Reference
++ );
++
++/* Enable/Disable anti-alias line. */
++gceSTATUS
++gco3D_SetAntiAliasLine(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set texture slot for anti-alias line. */
++gceSTATUS
++gco3D_SetAALineTexSlot(
++ IN gco3D Engine,
++ IN gctUINT TexSlot
++ );
++
++/* Set anti-alias line width scale. */
++gceSTATUS
++gco3D_SetAALineWidth(
++ IN gco3D Engine,
++ IN gctFLOAT Width
++ );
++
++/* Draw a number of primitives. */
++gceSTATUS
++gco3D_DrawPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctSIZE_T StartVertex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++gceSTATUS
++gco3D_DrawInstancedPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctBOOL DrawIndex,
++ IN gctSIZE_T StartVertex,
++ IN gctSIZE_T StartIndex,
++ IN gctSIZE_T PrimitiveCount,
++ IN gctSIZE_T VertexCount,
++ IN gctSIZE_T InstanceCount
++ );
++
++gceSTATUS
++gco3D_DrawPrimitivesCount(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT* StartVertex,
++ IN gctSIZE_T* VertexCount,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++
++/* Draw a number of primitives using offsets. */
++gceSTATUS
++gco3D_DrawPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives. */
++gceSTATUS
++gco3D_DrawIndexedPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctSIZE_T BaseVertex,
++ IN gctSIZE_T StartIndex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives using offsets. */
++gceSTATUS
++gco3D_DrawIndexedPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 BaseOffset,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a element from pattern */
++gceSTATUS
++gco3D_DrawPattern(
++ IN gco3D Engine,
++ IN gcsFAST_FLUSH_PTR FastFlushInfo
++ );
++
++/* Enable or disable anti-aliasing. */
++gceSTATUS
++gco3D_SetAntiAlias(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Write data into the command buffer. */
++gceSTATUS
++gco3D_WriteBuffer(
++ IN gco3D Engine,
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Aligned
++ );
++
++/* Send sempahore and stall until sempahore is signalled. */
++gceSTATUS
++gco3D_Semaphore(
++ IN gco3D Engine,
++ IN gceWHERE From,
++ IN gceWHERE To,
++ IN gceHOW How);
++
++/* Explicitly flush shader L1 cache */
++gceSTATUS
++gco3D_FlushSHL1Cache(
++ IN gco3D Engine
++ );
++
++/* Set the subpixels center. */
++gceSTATUS
++gco3D_SetCentroids(
++ IN gco3D Engine,
++ IN gctUINT32 Index,
++ IN gctPOINTER Centroids
++ );
++
++gceSTATUS
++gco3D_SetLogicOp(
++ IN gco3D Engine,
++ IN gctUINT8 Rop
++ );
++
++gceSTATUS
++gco3D_SetOQ(
++ IN gco3D Engine,
++ INOUT gctPOINTER * Result,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco3D_GetOQ(
++ IN gco3D Engine,
++ IN gctPOINTER Result,
++ OUT gctINT64 * Logical
++ );
++
++gceSTATUS
++gco3D_DeleteOQ(
++ IN gco3D Engine,
++ INOUT gctPOINTER Result
++ );
++
++gceSTATUS
++gco3D_SetColorOutCount(
++ IN gco3D Engine,
++ IN gctUINT32 ColorOutCount
++ );
++
++gceSTATUS
++gco3D_Set3DEngine(
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gco3D_UnSet3DEngine(
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gco3D_Get3DEngine(
++ OUT gco3D * Engine
++ );
++
++
++/* OCL thread walker information. */
++typedef struct _gcsTHREAD_WALKER_INFO * gcsTHREAD_WALKER_INFO_PTR;
++typedef struct _gcsTHREAD_WALKER_INFO
++{
++ gctUINT32 dimensions;
++ gctUINT32 traverseOrder;
++ gctUINT32 enableSwathX;
++ gctUINT32 enableSwathY;
++ gctUINT32 enableSwathZ;
++ gctUINT32 swathSizeX;
++ gctUINT32 swathSizeY;
++ gctUINT32 swathSizeZ;
++ gctUINT32 valueOrder;
++
++ gctUINT32 globalSizeX;
++ gctUINT32 globalOffsetX;
++ gctUINT32 globalSizeY;
++ gctUINT32 globalOffsetY;
++ gctUINT32 globalSizeZ;
++ gctUINT32 globalOffsetZ;
++
++ gctUINT32 workGroupSizeX;
++ gctUINT32 workGroupCountX;
++ gctUINT32 workGroupSizeY;
++ gctUINT32 workGroupCountY;
++ gctUINT32 workGroupSizeZ;
++ gctUINT32 workGroupCountZ;
++
++ gctUINT32 threadAllocation;
++}
++gcsTHREAD_WALKER_INFO;
++
++/* Start OCL thread walker. */
++gceSTATUS
++gco3D_InvokeThreadWalker(
++ IN gco3D Engine,
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++gceSTATUS
++gco3D_GetClosestRenderFormat(
++ IN gco3D Engine,
++ IN gceSURF_FORMAT InFormat,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++/* Set w clip and w plane limit value. */
++gceSTATUS
++gco3D_SetWClipEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco3D_GetWClipEnable(
++ IN gco3D Engine,
++ OUT gctBOOL * Enable
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitF(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Value
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimit(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++gceSTATUS
++gco3D_PrimitiveRestart(
++ IN gco3D Engine,
++ IN gctBOOL PrimitiveRestart);
++
++#if gcdSTREAM_OUT_BUFFER
++
++gceSTATUS
++gco3D_QueryStreamOut(
++ IN gco3D Engine,
++ IN gctUINT32 OriginalIndexAddress,
++ IN gctUINT32 OriginalIndexOffset,
++ IN gctUINT32 OriginalIndexCount,
++ OUT gctBOOL_PTR Found
++ );
++
++gceSTATUS
++gco3D_StartStreamOut(
++ IN gco3D Engine,
++ IN gctINT StreamOutStatus,
++ IN gctUINT32 IndexAddress,
++ IN gctUINT32 IndexOffset,
++ IN gctUINT32 IndexCount
++ );
++
++gceSTATUS
++gco3D_StopStreamOut(
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gco3D_ReplayStreamOut(
++ IN gco3D Engine,
++ IN gctUINT32 IndexAddress,
++ IN gctUINT32 IndexOffset,
++ IN gctUINT32 IndexCount
++ );
++
++gceSTATUS
++gco3D_EndStreamOut(
++ IN gco3D Engine
++ );
++
++#endif
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- gco3D Fragment Processor ------------------------*/
++
++/* Set the fragment processor configuration. */
++gceSTATUS
++gco3D_SetFragmentConfiguration(
++ IN gco3D Engine,
++ IN gctBOOL ColorFromStream,
++ IN gctBOOL EnableFog,
++ IN gctBOOL EnableSmoothPoint,
++ IN gctUINT32 ClipPlanes
++ );
++
++/* Enable/disable texture stage operation. */
++gceSTATUS
++gco3D_EnableTextureStage(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL Enable
++ );
++
++/* Program the channel enable masks for the color texture function. */
++gceSTATUS
++gco3D_SetTextureColorMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the channel enable masks for the alpha texture function. */
++gceSTATUS
++gco3D_SetTextureAlphaMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the constant fragment color. */
++gceSTATUS
++gco3D_SetFragmentColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFragmentColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant fog color. */
++gceSTATUS
++gco3D_SetFogColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFogColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant texture color. */
++gceSTATUS
++gco3D_SetTetxureColorX(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetTetxureColorF(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Configure color texture function. */
++gceSTATUS
++gco3D_SetColorTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/* Configure alpha texture function. */
++gceSTATUS
++gco3D_SetAlphaTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/******************************************************************************\
++******************************* gcoTEXTURE Object *******************************
++\******************************************************************************/
++
++/* Cube faces. */
++typedef enum _gceTEXTURE_FACE
++{
++ gcvFACE_NONE,
++ gcvFACE_POSITIVE_X,
++ gcvFACE_NEGATIVE_X,
++ gcvFACE_POSITIVE_Y,
++ gcvFACE_NEGATIVE_Y,
++ gcvFACE_POSITIVE_Z,
++ gcvFACE_NEGATIVE_Z,
++}
++gceTEXTURE_FACE;
++
++typedef struct _gcsTEXTURE
++{
++ /* Addressing modes. */
++ gceTEXTURE_ADDRESSING s;
++ gceTEXTURE_ADDRESSING t;
++ gceTEXTURE_ADDRESSING r;
++
++ gceTEXTURE_SWIZZLE swizzle[gcvTEXTURE_COMPONENT_NUM];
++
++ /* Border color. */
++ gctUINT8 border[gcvTEXTURE_COMPONENT_NUM];
++
++ /* Filters. */
++ gceTEXTURE_FILTER minFilter;
++ gceTEXTURE_FILTER magFilter;
++ gceTEXTURE_FILTER mipFilter;
++ gctUINT anisoFilter;
++
++ /* Level of detail. */
++ gctFLOAT lodBias;
++ gctFLOAT lodMin;
++ gctFLOAT lodMax;
++
++ /* base/max level */
++ gctINT32 baseLevel;
++ gctINT32 maxLevel;
++
++ /* depth texture comparison */
++ gceTEXTURE_COMPARE_MODE compareMode;
++ gceCOMPARE compareFunc;
++
++}
++gcsTEXTURE, * gcsTEXTURE_PTR;
++
++/* Construct a new gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Construct(
++ IN gcoHAL Hal,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Construct a new gcoTEXTURE object with type information. */
++gceSTATUS
++gcoTEXTURE_ConstructEx(
++ IN gcoHAL Hal,
++ IN gceTEXTURE_TYPE Type,
++ OUT gcoTEXTURE * Texture
++ );
++
++
++/* Construct a new sized gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_ConstructSized(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gctUINT MipMapCount,
++ IN gcePOOL Pool,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Destroy an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Destroy(
++ IN gcoTEXTURE Texture
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Upload(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_COLOR_SPACE SrcColorSpace
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadSub(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T X,
++ IN gctSIZE_T Y,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_COLOR_SPACE SrcColorSpace,
++ IN gctUINT32 PhysicalAddress
++ );
++
++
++/* Upload YUV data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadYUV(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctPOINTER Memory[3],
++ IN gctINT Stride[3],
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload compressed data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressed(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload compressed sub data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressedSub(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T XOffset,
++ IN gctSIZE_T YOffset,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Size
++ );
++
++/* Get gcoSURF object for a mipmap level. */
++gceSTATUS
++gcoTEXTURE_GetMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ OUT gcoSURF * Surface
++ );
++
++/* Get gcoSURF object for a mipmap level and face offset. */
++gceSTATUS
++gcoTEXTURE_GetMipMapFace(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ OUT gcoSURF * Surface,
++ OUT gctSIZE_T_PTR Offset
++ );
++
++gceSTATUS
++gcoTEXTURE_GetMipMapSlice(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gctUINT Slice,
++ OUT gcoSURF * Surface,
++ OUT gctSIZE_T_PTR Offset
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctINT InternalFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctSIZE_T Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapWithFlag(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctINT InternalFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctSIZE_T Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool,
++ IN gctBOOL Protected,
++ OUT gcoSURF * Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromClient(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromSurface(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_SetEndianHint(
++ IN gcoTEXTURE Texture,
++ IN gceENDIAN_HINT EndianHint
++ );
++
++gceSTATUS
++gcoTEXTURE_Disable(
++ IN gcoHAL Hal,
++ IN gctINT Sampler
++ );
++
++gceSTATUS
++gcoTEXTURE_Flush(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_FlushVS(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_QueryCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoTEXTURE_GetClosestFormat(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT InFormat,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++gceSTATUS
++gcoTEXTURE_GetClosestFormatEx(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT InFormat,
++ IN gceTEXTURE_TYPE TextureType,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++gceSTATUS
++gcoTEXTURE_GetFormatInfo(
++ IN gcoTEXTURE Texture,
++ IN gctINT preferLevel,
++ OUT gcsSURF_FORMAT_INFO_PTR * TxFormatInfo
++ );
++
++gceSTATUS
++gcoTEXTURE_GetTextureFormatName(
++ IN gcsSURF_FORMAT_INFO_PTR TxFormatInfo,
++ OUT gctCONST_STRING * TxName
++ );
++
++gceSTATUS
++gcoTEXTURE_RenderIntoMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_RenderIntoMipMap2(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctBOOL Sync
++ );
++
++gceSTATUS
++gcoTEXTURE_IsRenderable(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsComplete(
++ IN gcoTEXTURE Texture,
++ IN gcsTEXTURE_PTR Info,
++ IN gctINT BaseLevel,
++ IN gctINT MaxLevel
++ );
++
++gceSTATUS
++gcoTEXTURE_BindTexture(
++ IN gcoTEXTURE Texture,
++ IN gctINT Target,
++ IN gctINT Sampler,
++ IN gcsTEXTURE_PTR Info
++ );
++
++gceSTATUS
++gcoTEXTURE_BindTextureEx(
++ IN gcoTEXTURE Texture,
++ IN gctINT Target,
++ IN gctINT Sampler,
++ IN gcsTEXTURE_PTR Info,
++ IN gctINT textureLayer
++ );
++
++gceSTATUS
++gcoTEXTURE_InitParams(
++ IN gcoHAL Hal,
++ IN gcsTEXTURE_PTR TexParams
++ );
++
++gceSTATUS
++gcoTEXTURE_SetDepthTextureFlag(
++ IN gcoTEXTURE Texture,
++ IN gctBOOL unsized
++ );
++
++
++/******************************************************************************\
++******************************* gcoSTREAM Object ******************************
++\******************************************************************************/
++
++typedef enum _gceVERTEX_FORMAT
++{
++ gcvVERTEX_BYTE,
++ gcvVERTEX_UNSIGNED_BYTE,
++ gcvVERTEX_SHORT,
++ gcvVERTEX_UNSIGNED_SHORT,
++ gcvVERTEX_INT,
++ gcvVERTEX_UNSIGNED_INT,
++ gcvVERTEX_FIXED,
++ gcvVERTEX_HALF,
++ gcvVERTEX_FLOAT,
++ gcvVERTEX_UNSIGNED_INT_10_10_10_2,
++ gcvVERTEX_INT_10_10_10_2,
++ gcvVERTEX_UNSIGNED_INT_2_10_10_10_REV,
++ gcvVERTEX_INT_2_10_10_10_REV,
++ /* integer format */
++ gcvVERTEX_INT8,
++ gcvVERTEX_INT16,
++ gcvVERTEX_INT32,
++}
++gceVERTEX_FORMAT;
++
++/* What the SW converting scheme to create temp attrib */
++typedef enum _gceATTRIB_SCHEME
++{
++ gcvATTRIB_SCHEME_KEEP = 0,
++ gcvATTRIB_SCHEME_2_10_10_10_REV_TO_FLOAT,
++ gcvATTRIB_SCHEME_BYTE_TO_INT,
++ gcvATTRIB_SCHEME_SHORT_TO_INT,
++ gcvATTRIB_SCHEME_UBYTE_TO_UINT,
++ gcvATTRIB_SCHEME_USHORT_TO_UINT,
++} gceATTRIB_SCHEME;
++
++gceSTATUS
++gcoSTREAM_Construct(
++ IN gcoHAL Hal,
++ OUT gcoSTREAM * Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Destroy(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Upload(
++ IN gcoSTREAM Stream,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Dynamic
++ );
++
++gceSTATUS
++gcoSTREAM_SetStride(
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoSTREAM_Size(
++ IN gcoSTREAM Stream,
++ OUT gctSIZE_T *Size
++ );
++
++gceSTATUS
++gcoSTREAM_Node(
++ IN gcoSTREAM Stream,
++ OUT gcsSURF_NODE_PTR * Node
++ );
++
++gceSTATUS
++gcoSTREAM_Lock(
++ IN gcoSTREAM Stream,
++ OUT gctPOINTER * Logical,
++ OUT gctUINT32 * Physical
++ );
++
++gceSTATUS
++gcoSTREAM_Unlock(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Reserve(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoSTREAM_Flush(
++ IN gcoSTREAM Stream
++ );
++
++/* Dynamic buffer API. */
++gceSTATUS
++gcoSTREAM_SetDynamic(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++typedef struct _gcsSTREAM_INFO
++{
++ gctUINT index;
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT components;
++ gctSIZE_T size;
++ gctCONST_POINTER data;
++ gctUINT stride;
++}
++gcsSTREAM_INFO, * gcsSTREAM_INFO_PTR;
++
++gceSTATUS
++gcoSTREAM_UploadDynamic(
++ IN gcoSTREAM Stream,
++ IN gctUINT VertexCount,
++ IN gctUINT InfoCount,
++ IN gcsSTREAM_INFO_PTR Info,
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoSTREAM_CPUCacheOperation(
++ IN gcoSTREAM Stream,
++ IN gceCACHEOPERATION Operation
++ );
++
++gceSTATUS
++gcoSTREAM_CPUCacheOperation_Range(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Length,
++ IN gceCACHEOPERATION Operation
++ );
++
++/******************************************************************************\
++******************************** gcoVERTEX Object ******************************
++\******************************************************************************/
++
++typedef struct _gcsVERTEX_ATTRIBUTES
++{
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT32 components;
++ gctSIZE_T size;
++ gctUINT32 stream;
++ gctUINT32 offset;
++ gctUINT32 stride;
++}
++gcsVERTEX_ATTRIBUTES;
++
++gceSTATUS
++gcoVERTEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEX * Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Destroy(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Reset(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_EnableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index,
++ IN gceVERTEX_FORMAT Format,
++ IN gctBOOL Normalized,
++ IN gctUINT32 Components,
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoVERTEX_DisableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index
++ );
++
++gceSTATUS
++gcoVERTEX_Bind(
++ IN gcoVERTEX Vertex
++ );
++
++/*******************************************************************************
++***** gcoVERTEXARRAY Object ***************************************************/
++
++typedef struct _gcsATTRIBUTE
++{
++ /* Enabled. */
++ gctBOOL enable;
++
++ /* Number of components. */
++ gctINT size;
++
++ /* Attribute format. */
++ gceVERTEX_FORMAT format;
++
++ /* Flag whether the attribute is normalized or not. */
++ gctBOOL normalized;
++
++ /* Stride of the component. */
++ gctSIZE_T stride;
++
++ /* Divisor of the attribute */
++ gctUINT divisor;
++
++ /* Pointer to the attribute data. */
++ gctCONST_POINTER pointer;
++
++ /* Stream object owning the attribute data. */
++ gcoBUFOBJ stream;
++
++ /* Generic values for attribute. */
++ gctFLOAT genericValue[4];
++
++ /* Generic size for attribute. */
++ gctINT genericSize;
++
++ /* Vertex shader linkage. */
++ gctUINT linkage;
++
++#if gcdUSE_WCLIP_PATCH
++ /* Does it hold positions? */
++ gctBOOL isPosition;
++#endif
++
++ /* Index to vertex array */
++ gctINT arrayIdx;
++
++ gceATTRIB_SCHEME convertScheme;
++
++ /* Pointer to the temporary buffer to be freed */
++ gcoBUFOBJ tempStream;
++
++ /* Pointer to the temporary memory to be freed */
++ gctCONST_POINTER tempMemory;
++}
++gcsATTRIBUTE,
++* gcsATTRIBUTE_PTR;
++
++
++typedef struct _gcsVERTEXARRAY
++{
++ /* Enabled. */
++ gctBOOL enable;
++
++ /* Number of components. */
++ gctINT size;
++
++ /* Attribute format. */
++ gceVERTEX_FORMAT format;
++
++ /* Flag whether the attribute is normalized or not. */
++ gctBOOL normalized;
++
++ /* Stride of the component. */
++ gctUINT stride;
++
++ /* Divisor of the attribute */
++ gctUINT divisor;
++
++ /* Pointer to the attribute data. */
++ gctCONST_POINTER pointer;
++
++ /* Stream object owning the attribute data. */
++ gcoSTREAM stream;
++
++ /* Generic values for attribute. */
++ gctFLOAT genericValue[4];
++
++ /* Generic size for attribute. */
++ gctINT genericSize;
++
++ /* Vertex shader linkage. */
++ gctUINT linkage;
++
++ gctBOOL isPosition;
++}
++gcsVERTEXARRAY,
++* gcsVERTEXARRAY_PTR;
++
++gceSTATUS
++gcoVERTEXARRAY_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEXARRAY * Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Destroy(
++ IN gcoVERTEXARRAY Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind_Ex(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsVERTEXARRAY_PTR VertexArray,
++ IN gctUINT First,
++ IN gctSIZE_T Count,
++ IN gctBOOL DrawArraysInstanced,
++ IN gctSIZE_T InstanceCount,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoINDEX IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctUINT * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty
++#else
++ IN OUT gctUINT * PrimitiveCount
++#endif
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind_Ex2(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsATTRIBUTE_PTR VertexArray,
++ IN gctSIZE_T First,
++ IN gctSIZE_T Count,
++ IN gctBOOL DrawArraysInstanced,
++ IN gctSIZE_T InstanceCount,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoBUFOBJ IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctSIZE_T * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty,
++#else
++ IN OUT gctUINT * PrimitiveCount,
++#endif
++ IN gctINT VertexInstanceIdLinkage
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsVERTEXARRAY_PTR VertexArray,
++ IN gctUINT First,
++ IN gctSIZE_T Count,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoINDEX IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctUINT * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty
++#else
++ IN OUT gctUINT * PrimitiveCount
++#endif
++ );
++
++/*******************************************************************************
++***** Composition *************************************************************/
++
++typedef enum _gceCOMPOSITION
++{
++ gcvCOMPOSE_CLEAR = 1,
++ gcvCOMPOSE_BLUR,
++ gcvCOMPOSE_DIM,
++ gcvCOMPOSE_LAYER
++}
++gceCOMPOSITION;
++
++typedef struct _gcsCOMPOSITION * gcsCOMPOSITION_PTR;
++typedef struct _gcsCOMPOSITION
++{
++ /* Structure size. */
++ gctUINT structSize;
++
++ /* Composition operation. */
++ gceCOMPOSITION operation;
++
++ /* Layer to be composed. */
++ gcoSURF layer;
++
++ /* Source and target coordinates. */
++ gcsRECT srcRect;
++ gcsRECT trgRect;
++
++ /* Target rectangle */
++ gcsPOINT v0;
++ gcsPOINT v1;
++ gcsPOINT v2;
++
++ /* Blending parameters. */
++ gctBOOL enableBlending;
++ gctBOOL premultiplied;
++ gctUINT8 alphaValue;
++
++ /* Clear color. */
++ gctFLOAT r;
++ gctFLOAT g;
++ gctFLOAT b;
++ gctFLOAT a;
++}
++gcsCOMPOSITION;
++
++gceSTATUS
++gco3D_ProbeComposition(
++ IN gcoHARDWARE Hardware,
++ IN gctBOOL ResetIfEmpty
++ );
++
++gceSTATUS
++gco3D_CompositionBegin(
++ IN gcoHARDWARE Hardware
++ );
++
++gceSTATUS
++gco3D_ComposeLayer(
++ IN gcoHARDWARE Hardware,
++ IN gcsCOMPOSITION_PTR Layer
++ );
++
++gceSTATUS
++gco3D_CompositionSignals(
++ IN gcoHARDWARE Hardware,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal1,
++ IN gctSIGNAL Signal2
++ );
++
++gceSTATUS
++gco3D_CompositionEnd(
++ IN gcoHARDWARE Hardware,
++ IN gcoSURF Target,
++ IN gctBOOL Synchronous
++ );
++
++/* Frame Database */
++gceSTATUS
++gcoHAL_AddFrameDB(
++ void
++ );
++
++gceSTATUS
++gcoHAL_DumpFrameDB(
++ gctCONST_STRING Filename OPTIONAL
++ );
++
++/******************************************************************************
++**********************gcoBUFOBJ object*****************************************
++*******************************************************************************/
++typedef enum _gceBUFOBJ_TYPE
++{
++ gcvBUFOBJ_TYPE_ARRAY_BUFFER = 1,
++ gcvBUFOBJ_TYPE_ELEMENT_ARRAY_BUFFER = 2,
++ gcvBUFOBJ_TYPE_GENERIC_BUFFER = 100
++
++} gceBUFOBJ_TYPE;
++
++typedef enum _gceBUFOBJ_USAGE
++{
++ gcvBUFOBJ_USAGE_STREAM_DRAW = 1,
++ gcvBUFOBJ_USAGE_STREAM_READ,
++ gcvBUFOBJ_USAGE_STREAM_COPY,
++ gcvBUFOBJ_USAGE_STATIC_DRAW,
++ gcvBUFOBJ_USAGE_STATIC_READ,
++ gcvBUFOBJ_USAGE_STATIC_COPY,
++ gcvBUFOBJ_USAGE_DYNAMIC_DRAW,
++ gcvBUFOBJ_USAGE_DYNAMIC_READ,
++ gcvBUFOBJ_USAGE_DYNAMIC_COPY,
++
++} gceBUFOBJ_USAGE;
++
++/* Construct a new gcoBUFOBJ object. */
++gceSTATUS
++gcoBUFOBJ_Construct(
++ IN gcoHAL Hal,
++ IN gceBUFOBJ_TYPE Type,
++ OUT gcoBUFOBJ * BufObj
++ );
++
++/* Destroy a gcoBUFOBJ object. */
++gceSTATUS
++gcoBUFOBJ_Destroy(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Lock pbo in memory. */
++gceSTATUS
++gcoBUFOBJ_Lock(
++ IN gcoBUFOBJ BufObj,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Lock pbo in memory. */
++gceSTATUS
++gcoBUFOBJ_FastLock(
++ IN gcoBUFOBJ BufObj,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Unlock pbo that was previously locked with gcoBUFOBJ_Lock. */
++gceSTATUS
++gcoBUFOBJ_Unlock(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Free existing pbo buffer. */
++gceSTATUS
++gcoBUFOBJ_Free(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Upload data into an pbo buffer. */
++gceSTATUS
++gcoBUFOBJ_Upload(
++ IN gcoBUFOBJ BufObj,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Bytes,
++ IN gceBUFOBJ_USAGE Usage
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoBUFOBJ_IndexBind (
++ IN gcoBUFOBJ Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Count
++ );
++
++/* Find min and max index for the index buffer */
++gceSTATUS
++gcoBUFOBJ_IndexGetRange(
++ IN gcoBUFOBJ Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Count,
++ OUT gctUINT32 * MinimumIndex,
++ OUT gctUINT32 * MaximumIndex
++ );
++
++/* Sets a buffer object as dirty */
++gceSTATUS
++gcoBUFOBJ_SetDirty(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Creates a new buffer if needed */
++gceSTATUS
++gcoBUFOBJ_AlignIndexBufferWhenNeeded(
++ IN gcoBUFOBJ BufObj,
++ IN gctSIZE_T Offset,
++ OUT gcoBUFOBJ * AlignedBufObj
++ );
++
++/* Cache operations on whole range */
++gceSTATUS
++gcoBUFOBJ_CPUCacheOperation(
++ IN gcoBUFOBJ BufObj,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Cache operations on a specified range */
++gceSTATUS
++gcoBUFOBJ_CPUCacheOperation_Range(
++ IN gcoBUFOBJ BufObj,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Length,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Return size of the bufobj */
++gceSTATUS
++gcoBUFOBJ_GetSize(
++ IN gcoBUFOBJ BufObj,
++ OUT gctSIZE_T_PTR Size
++ );
++
++/* Return memory node of the bufobj */
++gceSTATUS
++gcoBUFOBJ_GetNode(
++ IN gcoBUFOBJ BufObj,
++ OUT gcsSURF_NODE_PTR * Node
++ );
++
++/* Handle GPU cache operations */
++gceSTATUS
++gcoBUFOBJ_GPUCacheOperation(
++ gcoBUFOBJ BufObj
++ );
++
++/* Dump buffer. */
++void
++gcoBUFOBJ_Dump(
++ IN gcoBUFOBJ BufObj
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* gcdENABLE_3D */
++#endif /* __gc_hal_engine_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_engine_vg.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_engine_vg.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_engine_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_engine_vg.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,1215 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_vg_h_
++#define __gc_hal_engine_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "gc_hal_types.h"
++
++/******************************************************************************\
++******************************** VG Enumerations *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Tiling mode for painting and imagig.
++**
++** This enumeration defines the tiling modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 tile modes.
++*/
++typedef enum _gceTILE_MODE
++{
++ gcvTILE_FILL,
++ gcvTILE_PAD,
++ gcvTILE_REPEAT,
++ gcvTILE_REFLECT
++}
++gceTILE_MODE;
++
++/******************************************************************************/
++/** @ingroup gcoVG
++**
++** @brief The different paint modes.
++**
++** This enumeration lists the available paint modes.
++*/
++typedef enum _gcePAINT_TYPE
++{
++ /** Solid color. */
++ gcvPAINT_MODE_SOLID,
++
++ /** Linear gradient. */
++ gcvPAINT_MODE_LINEAR,
++
++ /** Radial gradient. */
++ gcvPAINT_MODE_RADIAL,
++
++ /** Pattern. */
++ gcvPAINT_MODE_PATTERN,
++
++ /** Mode count. */
++ gcvPAINT_MODE_COUNT
++}
++gcePAINT_TYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Types of path data supported by HAL.
++**
++** This enumeration defines the types of path data supported by the HAL.
++** This is in fact a one-to-one mapping of the OpenVG 1.1 path types.
++*/
++typedef enum _gcePATHTYPE
++{
++ gcePATHTYPE_UNKNOWN = -1,
++ gcePATHTYPE_INT8,
++ gcePATHTYPE_INT16,
++ gcePATHTYPE_INT32,
++ gcePATHTYPE_FLOAT
++}
++gcePATHTYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Supported path segment commands.
++**
++** This enumeration defines the path segment commands supported by the HAL.
++*/
++typedef enum _gceVGCMD
++{
++ gcvVGCMD_END, /* 0: GCCMD_TS_OPCODE_END */
++ gcvVGCMD_CLOSE, /* 1: GCCMD_TS_OPCODE_CLOSE */
++ gcvVGCMD_MOVE, /* 2: GCCMD_TS_OPCODE_MOVE */
++ gcvVGCMD_MOVE_REL, /* 3: GCCMD_TS_OPCODE_MOVE_REL */
++ gcvVGCMD_LINE, /* 4: GCCMD_TS_OPCODE_LINE */
++ gcvVGCMD_LINE_REL, /* 5: GCCMD_TS_OPCODE_LINE_REL */
++ gcvVGCMD_QUAD, /* 6: GCCMD_TS_OPCODE_QUADRATIC */
++ gcvVGCMD_QUAD_REL, /* 7: GCCMD_TS_OPCODE_QUADRATIC_REL */
++ gcvVGCMD_CUBIC, /* 8: GCCMD_TS_OPCODE_CUBIC */
++ gcvVGCMD_CUBIC_REL, /* 9: GCCMD_TS_OPCODE_CUBIC_REL */
++ gcvVGCMD_BREAK, /* 10: GCCMD_TS_OPCODE_BREAK */
++ gcvVGCMD_HLINE, /* 11: ******* R E S E R V E D *******/
++ gcvVGCMD_HLINE_REL, /* 12: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE, /* 13: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE_REL, /* 14: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD, /* 15: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD_REL, /* 16: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC, /* 17: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC_REL, /* 18: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC, /* 19: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC_REL, /* 20: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC, /* 21: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC_REL, /* 22: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC, /* 23: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC_REL, /* 24: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC, /* 25: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC_REL, /* 26: ******* R E S E R V E D *******/
++
++ /* The width of the command recognized by the hardware on bits. */
++ gcvVGCMD_WIDTH = 5,
++
++ /* Hardware command mask. */
++ gcvVGCMD_MASK = (1 << gcvVGCMD_WIDTH) - 1,
++
++ /* Command modifiers. */
++ gcvVGCMD_H_MOD = 1 << gcvVGCMD_WIDTH, /* = 32 */
++ gcvVGCMD_V_MOD = 2 << gcvVGCMD_WIDTH, /* = 64 */
++ gcvVGCMD_S_MOD = 3 << gcvVGCMD_WIDTH, /* = 96 */
++ gcvVGCMD_ARC_MOD = 4 << gcvVGCMD_WIDTH, /* = 128 */
++
++ /* Emulated LINE commands. */
++ gcvVGCMD_HLINE_EMUL = gcvVGCMD_H_MOD | gcvVGCMD_LINE, /* = 36 */
++ gcvVGCMD_HLINE_EMUL_REL = gcvVGCMD_H_MOD | gcvVGCMD_LINE_REL, /* = 37 */
++ gcvVGCMD_VLINE_EMUL = gcvVGCMD_V_MOD | gcvVGCMD_LINE, /* = 68 */
++ gcvVGCMD_VLINE_EMUL_REL = gcvVGCMD_V_MOD | gcvVGCMD_LINE_REL, /* = 69 */
++
++ /* Emulated SMOOTH commands. */
++ gcvVGCMD_SQUAD_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD, /* = 102 */
++ gcvVGCMD_SQUAD_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD_REL, /* = 103 */
++ gcvVGCMD_SCUBIC_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC, /* = 104 */
++ gcvVGCMD_SCUBIC_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC_REL, /* = 105 */
++
++ /* Emulation ARC commands. */
++ gcvVGCMD_ARC_LINE = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE, /* = 132 */
++ gcvVGCMD_ARC_LINE_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE_REL, /* = 133 */
++ gcvVGCMD_ARC_QUAD = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD, /* = 134 */
++ gcvVGCMD_ARC_QUAD_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD_REL /* = 135 */
++}
++gceVGCMD;
++typedef enum _gceVGCMD * gceVGCMD_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Blending modes supported by the HAL.
++**
++** This enumeration defines the blending modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 blending modes.
++*/
++typedef enum _gceVG_BLEND
++{
++ gcvVG_BLEND_SRC,
++ gcvVG_BLEND_SRC_OVER,
++ gcvVG_BLEND_DST_OVER,
++ gcvVG_BLEND_SRC_IN,
++ gcvVG_BLEND_DST_IN,
++ gcvVG_BLEND_MULTIPLY,
++ gcvVG_BLEND_SCREEN,
++ gcvVG_BLEND_DARKEN,
++ gcvVG_BLEND_LIGHTEN,
++ gcvVG_BLEND_ADDITIVE,
++ gcvVG_BLEND_SUBTRACT,
++ gcvVG_BLEND_FILTER
++}
++gceVG_BLEND;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Image modes supported by the HAL.
++**
++** This enumeration defines the image modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 image modes with the addition
++** of NO IMAGE.
++*/
++typedef enum _gceVG_IMAGE
++{
++ gcvVG_IMAGE_NONE,
++ gcvVG_IMAGE_NORMAL,
++ gcvVG_IMAGE_MULTIPLY,
++ gcvVG_IMAGE_STENCIL,
++ gcvVG_IMAGE_FILTER
++}
++gceVG_IMAGE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Filter mode patterns and imaging.
++**
++** This enumeration defines the filter modes supported by the HAL.
++*/
++typedef enum _gceIMAGE_FILTER
++{
++ gcvFILTER_POINT,
++ gcvFILTER_LINEAR,
++ gcvFILTER_BI_LINEAR
++}
++gceIMAGE_FILTER;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Primitive modes supported by the HAL.
++**
++** This enumeration defines the primitive modes supported by the HAL.
++*/
++typedef enum _gceVG_PRIMITIVE
++{
++ gcvVG_SCANLINE,
++ gcvVG_RECTANGLE,
++ gcvVG_TESSELLATED,
++ gcvVG_TESSELLATED_TILED
++}
++gceVG_PRIMITIVE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rendering quality modes supported by the HAL.
++**
++** This enumeration defines the rendering quality modes supported by the HAL.
++*/
++typedef enum _gceRENDER_QUALITY
++{
++ gcvVG_NONANTIALIASED,
++ gcvVG_2X2_MSAA,
++ gcvVG_2X4_MSAA,
++ gcvVG_4X4_MSAA
++}
++gceRENDER_QUALITY;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Fill rules supported by the HAL.
++**
++** This enumeration defines the fill rules supported by the HAL.
++*/
++typedef enum _gceFILL_RULE
++{
++ gcvVG_EVEN_ODD,
++ gcvVG_NON_ZERO
++}
++gceFILL_RULE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Cap styles supported by the HAL.
++**
++** This enumeration defines the cap styles supported by the HAL.
++*/
++typedef enum _gceCAP_STYLE
++{
++ gcvCAP_BUTT,
++ gcvCAP_ROUND,
++ gcvCAP_SQUARE
++}
++gceCAP_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Join styles supported by the HAL.
++**
++** This enumeration defines the join styles supported by the HAL.
++*/
++typedef enum _gceJOIN_STYLE
++{
++ gcvJOIN_MITER,
++ gcvJOIN_ROUND,
++ gcvJOIN_BEVEL
++}
++gceJOIN_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Channel mask values.
++**
++** This enumeration defines the values for channel mask used in image
++** filtering.
++*/
++
++/* Base values for channel mask definitions. */
++#define gcvCHANNEL_X (0)
++#define gcvCHANNEL_R (1 << 0)
++#define gcvCHANNEL_G (1 << 1)
++#define gcvCHANNEL_B (1 << 2)
++#define gcvCHANNEL_A (1 << 3)
++
++typedef enum _gceCHANNEL
++{
++ gcvCHANNEL_XXXX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XXXA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XXBX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XXBA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_XGXX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XGXA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XGBX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XGBA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RXXX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RXXA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RXBX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RXBA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RGXX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RGXA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RGBX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RGBA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++}
++gceCHANNEL;
++
++/******************************************************************************\
++******************************** VG Structures *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsCOLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFLOAT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFLOAT red;
++
++ /** Green color channel value for the color stop. */
++ gctFLOAT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFLOAT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFLOAT alpha;
++}
++gcsCOLOR_RAMP, * gcsCOLOR_RAMP_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints in fixed form.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsFIXED_COLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFIXED_POINT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFIXED_POINT red;
++
++ /** Green color channel value for the color stop. */
++ gctFIXED_POINT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFIXED_POINT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFIXED_POINT alpha;
++}
++gcsFIXED_COLOR_RAMP, * gcsFIXED_COLOR_RAMP_PTR;
++
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rectangle structure used by the gcoVG object.
++**
++** This structure defines the layout of a rectangle. Make sure width and
++** height are larger than 0.
++*/
++typedef struct _gcsVG_RECT * gcsVG_RECT_PTR;
++typedef struct _gcsVG_RECT
++{
++ /** Left location of the rectangle. */
++ gctINT x;
++
++ /** Top location of the rectangle. */
++ gctINT y;
++
++ /** Width of the rectangle. */
++ gctINT width;
++
++ /** Height of the rectangle. */
++ gctINT height;
++}
++gcsVG_RECT;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Path command buffer attribute structure.
++**
++** The gcsPATH_BUFFER_INFO structure contains the specifics about
++** the layout of the path data command buffer.
++*/
++typedef struct _gcsPATH_BUFFER_INFO * gcsPATH_BUFFER_INFO_PTR;
++typedef struct _gcsPATH_BUFFER_INFO
++{
++ gctUINT reservedForHead;
++ gctUINT reservedForTail;
++}
++gcsPATH_BUFFER_INFO;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the path data container structure.
++**
++** The gcsPATH structure defines the layout of the path data container.
++*/
++typedef struct _gcsPATH_DATA * gcsPATH_DATA_PTR;
++typedef struct _gcsPATH_DATA
++{
++ /* Data container in command buffer format. */
++ gcsCMDBUFFER data;
++
++ /* Path data type. */
++ gcePATHTYPE dataType;
++}
++gcsPATH_DATA;
++
++
++/******************************************************************************\
++********************************* gcoHAL Object ********************************
++\******************************************************************************/
++
++/* Query path data storage attributes. */
++gceSTATUS
++gcoHAL_QueryPathStorage(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ OUT gcsPATH_BUFFER_INFO_PTR Information
++ );
++
++/* Associate a completion signal with the command buffer. */
++gceSTATUS
++gcoHAL_AssociateCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Release the current command buffer completion signal. */
++gceSTATUS
++gcoHAL_DeassociateCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Verify whether the command buffer is still in use. */
++gceSTATUS
++gcoHAL_CheckCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Wait until the command buffer is no longer in use. */
++gceSTATUS
++gcoHAL_WaitCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Flush the pixel cache. */
++gceSTATUS
++gcoHAL_Flush(
++ IN gcoHAL Hal
++#if GC355_PROFILER
++ ,
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++#endif
++ );
++
++/* Split a harwdare address into pool and offset. */
++gceSTATUS
++gcoHAL_SplitAddress(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Combine pool and offset into a harwdare address. */
++gceSTATUS
++gcoHAL_CombineAddress(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcePOOL Pool,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Schedule to free linear video memory allocated. */
++gceSTATUS
++gcoHAL_ScheduleVideoMemory(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT32 Node
++ );
++
++/* Free linear video memory allocated with gcoHAL_AllocateLinearVideoMemory. */
++gceSTATUS
++gcoHAL_FreeVideoMemory(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT32 Node
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gcoHAL_QueryCommandBuffer(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++/* Allocate and lock linear video memory. */
++gceSTATUS
++gcoHAL_AllocateLinearVideoMemory(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ IN gcePOOL Pool,
++ OUT gctUINT32 * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Align the specified size accordingly to the hardware requirements. */
++gceSTATUS
++gcoHAL_GetAlignedSurfaceSize(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++gceSTATUS
++gcoHAL_ReserveTask(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceBLOCK Block,
++ IN gctUINT TaskCount,
++ IN gctUINT32 Bytes,
++ OUT gctPOINTER * Memory
++ );
++/******************************************************************************\
++********************************** gcoVG Object ********************************
++\******************************************************************************/
++
++/** @defgroup gcoVG gcoVG
++**
++** The gcoVG object abstracts the VG hardware pipe.
++*/
++#if GC355_PROFILER
++void
++gcoVG_ProfilerEnableDisable(
++ IN gcoVG Vg,
++ IN gctUINT enableGetAPITimes,
++ IN gctFILE apiTimeFile
++ );
++
++void
++gcoVG_ProfilerTreeDepth(
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth
++ );
++
++void
++gcoVG_ProfilerSetStates(
++ IN gcoVG Vg,
++ IN gctUINT treeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++ );
++#endif
++
++gctBOOL
++gcoVG_IsMaskSupported(
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsTargetSupported(
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsImageSupported(
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_FORMAT Format
++ );
++
++gctUINT8 gcoVG_PackColorComponent(
++#if GC355_PROFILER
++ gcoVG Vg,
++ gctUINT TreeDepth,
++ gctUINT saveLayerTreeDepth,
++ gctUINT varTreeDepth,
++#endif
++ gctFLOAT Value
++ );
++
++gceSTATUS
++gcoVG_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVG * Vg
++ );
++
++gceSTATUS
++gcoVG_Destroy(
++ IN gcoVG Vg
++#if GC355_PROFILER
++ ,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++#endif
++ );
++
++gceSTATUS
++gcoVG_SetTarget(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Target
++ );
++
++gceSTATUS
++gcoVG_UnsetTarget(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_SetUserToSurface(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT UserToSurface[9]
++ );
++
++gceSTATUS
++gcoVG_SetSurfaceToImage(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT SurfaceToImage[9]
++ );
++
++gceSTATUS
++gcoVG_EnableMask(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetMask(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Mask
++ );
++
++gceSTATUS
++gcoVG_UnsetMask(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_FlushMask(
++ IN gcoVG Vg
++#if GC355_PROFILER
++ ,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++#endif
++ );
++
++gceSTATUS
++gcoVG_EnableScissor(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetScissor(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctSIZE_T RectangleCount,
++ IN gcsVG_RECT_PTR Rectangles
++ );
++
++gceSTATUS
++gcoVG_EnableColorTransform(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetColorTransform(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT ColorTransform[8]
++ );
++
++gceSTATUS
++gcoVG_SetTileFillColor(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++gceSTATUS
++gcoVG_SetSolidPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++gceSTATUS
++gcoVG_SetLinearPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT Constant,
++ IN gctFLOAT StepX,
++ IN gctFLOAT StepY
++ );
++
++gceSTATUS
++gcoVG_SetRadialPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT LinConstant,
++ IN gctFLOAT LinStepX,
++ IN gctFLOAT LinStepY,
++ IN gctFLOAT RadConstant,
++ IN gctFLOAT RadStepX,
++ IN gctFLOAT RadStepY,
++ IN gctFLOAT RadStepXX,
++ IN gctFLOAT RadStepYY,
++ IN gctFLOAT RadStepXY
++ );
++
++gceSTATUS
++gcoVG_SetPatternPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT UConstant,
++ IN gctFLOAT UStepX,
++ IN gctFLOAT UStepY,
++ IN gctFLOAT VConstant,
++ IN gctFLOAT VStepX,
++ IN gctFLOAT VStepY,
++ IN gctBOOL Linear
++ );
++
++gceSTATUS
++gcoVG_SetColorRamp(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF ColorRamp,
++ IN gceTILE_MODE ColorRampSpreadMode
++ );
++
++gceSTATUS
++gcoVG_SetPattern(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctINT32 width,
++ IN gctINT32 height,
++ IN gcoSURF Pattern,
++ IN gceTILE_MODE TileMode,
++ IN gceIMAGE_FILTER Filter
++ );
++
++gceSTATUS
++gcoVG_SetImageMode(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceVG_IMAGE Mode
++ );
++
++gceSTATUS
++gcoVG_SetBlendMode(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_SetRenderingQuality(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceRENDER_QUALITY Quality
++ );
++
++gceSTATUS
++gcoVG_SetFillRule(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceFILL_RULE FillRule
++ );
++
++gceSTATUS
++gcoVG_FinalizePath(
++ IN gcoVG Vg,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++gceSTATUS
++gcoVG_Clear(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_DrawPath(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++#if gcdMOVG
++ IN gctUINT32 Width,
++ IN gctUINT32 Height,
++ IN gctFLOAT *Bounds,
++#endif
++ IN gctBOOL SoftwareTesselation
++ );
++
++gceSTATUS
++gcoVG_DrawImage(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctBOOL Mask,
++ IN gctBOOL isDrawImage
++ );
++
++gceSTATUS
++gcoVG_TesselateImage(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Image,
++ IN gcsVG_RECT_PTR Rectangle,
++ IN gceIMAGE_FILTER Filter,
++ IN gctBOOL Mask,
++#if gcdMOVG
++ IN gctBOOL SoftwareTesselation,
++ IN gceVG_BLEND BlendMode
++#else
++ IN gctBOOL SoftwareTesselation
++#endif
++ );
++
++gceSTATUS
++gcoVG_Blit(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gcsVG_RECT_PTR SrcRect,
++ IN gcsVG_RECT_PTR TrgRect,
++ IN gceIMAGE_FILTER Filter,
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_ColorMatrix(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN const gctFLOAT * Matrix,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_SeparableConvolve(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT KernelWidth,
++ IN gctINT KernelHeight,
++ IN gctINT ShiftX,
++ IN gctINT ShiftY,
++ IN const gctINT16 * KernelX,
++ IN const gctINT16 * KernelY,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_GaussianBlur(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctFLOAT StdDeviationX,
++ IN gctFLOAT StdDeviationY,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_EnableDither(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_vg_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_enum.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_enum.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_enum.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_enum.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,1605 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_enum_h_
++#define __gc_hal_enum_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Chip models. */
++typedef enum _gceCHIPMODEL
++{
++ gcv200 = 0x0200,
++ gcv300 = 0x0300,
++ gcv320 = 0x0320,
++ gcv328 = 0x0328,
++ gcv350 = 0x0350,
++ gcv355 = 0x0355,
++ gcv400 = 0x0400,
++ gcv410 = 0x0410,
++ gcv420 = 0x0420,
++ gcv428 = 0x0428,
++ gcv450 = 0x0450,
++ gcv500 = 0x0500,
++ gcv520 = 0x0520,
++ gcv530 = 0x0530,
++ gcv600 = 0x0600,
++ gcv700 = 0x0700,
++ gcv800 = 0x0800,
++ gcv860 = 0x0860,
++ gcv880 = 0x0880,
++ gcv1000 = 0x1000,
++ gcv1500 = 0x1500,
++ gcv2000 = 0x2000,
++ gcv2100 = 0x2100,
++ gcv2200 = 0x2200,
++ gcv2500 = 0x2500,
++ gcv3000 = 0x3000,
++ gcv4000 = 0x4000,
++ gcv5000 = 0x5000,
++ gcv5200 = 0x5200,
++ gcv6400 = 0x6400,
++}
++gceCHIPMODEL;
++
++/* Chip features. */
++typedef enum _gceFEATURE
++{
++ gcvFEATURE_PIPE_2D = 0,
++ gcvFEATURE_PIPE_3D,
++ gcvFEATURE_PIPE_VG,
++ gcvFEATURE_DC,
++ gcvFEATURE_HIGH_DYNAMIC_RANGE,
++ gcvFEATURE_MODULE_CG,
++ gcvFEATURE_MIN_AREA,
++ gcvFEATURE_BUFFER_INTERLEAVING,
++ gcvFEATURE_BYTE_WRITE_2D,
++ gcvFEATURE_ENDIANNESS_CONFIG,
++ gcvFEATURE_DUAL_RETURN_BUS,
++ gcvFEATURE_DEBUG_MODE,
++ gcvFEATURE_YUY2_RENDER_TARGET,
++ gcvFEATURE_FRAGMENT_PROCESSOR,
++ gcvFEATURE_2DPE20,
++ gcvFEATURE_FAST_CLEAR,
++ gcvFEATURE_YUV420_TILER,
++ gcvFEATURE_YUY2_AVERAGING,
++ gcvFEATURE_FLIP_Y,
++ gcvFEATURE_EARLY_Z,
++ gcvFEATURE_COMPRESSION,
++ gcvFEATURE_MSAA,
++ gcvFEATURE_SPECIAL_ANTI_ALIASING,
++ gcvFEATURE_SPECIAL_MSAA_LOD,
++ gcvFEATURE_422_TEXTURE_COMPRESSION,
++ gcvFEATURE_DXT_TEXTURE_COMPRESSION,
++ gcvFEATURE_ETC1_TEXTURE_COMPRESSION,
++ gcvFEATURE_CORRECT_TEXTURE_CONVERTER,
++ gcvFEATURE_TEXTURE_8K,
++ gcvFEATURE_SCALER,
++ gcvFEATURE_YUV420_SCALER,
++ gcvFEATURE_SHADER_HAS_W,
++ gcvFEATURE_SHADER_HAS_SIGN,
++ gcvFEATURE_SHADER_HAS_FLOOR,
++ gcvFEATURE_SHADER_HAS_CEIL,
++ gcvFEATURE_SHADER_HAS_SQRT,
++ gcvFEATURE_SHADER_HAS_TRIG,
++ gcvFEATURE_VAA,
++ gcvFEATURE_HZ,
++ gcvFEATURE_CORRECT_STENCIL,
++ gcvFEATURE_VG20,
++ gcvFEATURE_VG_FILTER,
++ gcvFEATURE_VG21,
++ gcvFEATURE_VG_DOUBLE_BUFFER,
++ gcvFEATURE_MC20,
++ gcvFEATURE_SUPER_TILED,
++ gcvFEATURE_FAST_CLEAR_FLUSH,
++ gcvFEATURE_2D_FILTERBLIT_PLUS_ALPHABLEND,
++ gcvFEATURE_2D_DITHER,
++ gcvFEATURE_2D_A8_TARGET,
++ gcvFEATURE_2D_A8_NO_ALPHA,
++ gcvFEATURE_2D_FILTERBLIT_FULLROTATION,
++ gcvFEATURE_2D_BITBLIT_FULLROTATION,
++ gcvFEATURE_WIDE_LINE,
++ gcvFEATURE_FC_FLUSH_STALL,
++ gcvFEATURE_FULL_DIRECTFB,
++ gcvFEATURE_HALF_FLOAT_PIPE,
++ gcvFEATURE_LINE_LOOP,
++ gcvFEATURE_2D_YUV_BLIT,
++ gcvFEATURE_2D_TILING,
++ gcvFEATURE_NON_POWER_OF_TWO,
++ gcvFEATURE_3D_TEXTURE,
++ gcvFEATURE_TEXTURE_ARRAY,
++ gcvFEATURE_TILE_FILLER,
++ gcvFEATURE_LOGIC_OP,
++ gcvFEATURE_COMPOSITION,
++ gcvFEATURE_MIXED_STREAMS,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT,
++ gcvFEATURE_END_EVENT,
++ gcvFEATURE_VERTEX_10_10_10_2,
++ gcvFEATURE_TEXTURE_10_10_10_2,
++ gcvFEATURE_TEXTURE_ANISOTROPIC_FILTERING,
++ gcvFEATURE_TEXTURE_FLOAT_HALF_FLOAT,
++ gcvFEATURE_2D_ROTATION_STALL_FIX,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX,
++ gcvFEATURE_BUG_FIXES10,
++ gcvFEATURE_2D_MINOR_TILING,
++ /* Supertiled compressed textures are supported. */
++ gcvFEATURE_TEX_COMPRRESSION_SUPERTILED,
++ gcvFEATURE_FAST_MSAA,
++ gcvFEATURE_BUG_FIXED_INDEXED_TRIANGLE_STRIP,
++ gcvFEATURE_TEXTURE_TILE_STATUS_READ,
++ gcvFEATURE_DEPTH_BIAS_FIX,
++ gcvFEATURE_RECT_PRIMITIVE,
++ gcvFEATURE_BUG_FIXES11,
++ gcvFEATURE_SUPERTILED_TEXTURE,
++ gcvFEATURE_2D_NO_COLORBRUSH_INDEX8,
++ gcvFEATURE_RS_YUV_TARGET,
++ gcvFEATURE_2D_FC_SOURCE,
++ gcvFEATURE_2D_CC_NOAA_SOURCE,
++ gcvFEATURE_PE_DITHER_FIX,
++ gcvFEATURE_2D_YUV_SEPARATE_STRIDE,
++ gcvFEATURE_FRUSTUM_CLIP_FIX,
++ gcvFEATURE_TEXTURE_SWIZZLE,
++ gcvFEATURE_PRIMITIVE_RESTART,
++ gcvFEATURE_TEXTURE_LINEAR,
++ gcvFEATURE_TEXTURE_YUV_ASSEMBLER,
++ gcvFEATURE_LINEAR_RENDER_TARGET,
++ gcvFEATURE_SHADER_HAS_ATOMIC,
++ gcvFEATURE_SHADER_HAS_INSTRUCTION_CACHE,
++ gcvFEATURE_SHADER_ENHANCEMENTS2,
++ gcvFEATURE_BUG_FIXES7,
++ gcvFEATURE_SHADER_HAS_RTNE,
++ gcvFEATURE_SHADER_HAS_EXTRA_INSTRUCTIONS2,
++ gcvFEATURE_SHADER_ENHANCEMENTS3,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING,
++ gcvFEATURE_SINGLE_BUFFER,
++ gcvFEATURE_OCCLUSION_QUERY,
++ gcvFEATURE_2D_GAMMA,
++ gcvFEATURE_2D_COLOR_SPACE_CONVERSION,
++ gcvFEATURE_2D_SUPER_TILE_VERSION,
++ gcvFEATURE_HALTI0,
++ gcvFEATURE_HALTI1,
++ gcvFEATURE_HALTI2,
++ gcvFEATURE_2D_MIRROR_EXTENSION,
++ gcvFEATURE_TEXTURE_ASTC,
++ gcvFEATURE_2D_SUPER_TILE_V1,
++ gcvFEATURE_2D_SUPER_TILE_V2,
++ gcvFEATURE_2D_SUPER_TILE_V3,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX2,
++ gcvFEATURE_NEW_RA,
++ gcvFEATURE_BUG_FIXED_IMPLICIT_PRIMITIVE_RESTART,
++ gcvFEATURE_PE_MULTI_RT_BLEND_ENABLE_CONTROL,
++ gcvFEATURE_SMALL_MSAA, /* An upgraded version of Fast MSAA */
++ gcvFEATURE_VERTEX_INST_ID_AS_ATTRIBUTE,
++ gcvFEATURE_DUAL_16,
++ gcvFEATURE_BRANCH_ON_IMMEDIATE_REG,
++ gcvFEATURE_2D_COMPRESSION,
++ gcvFEATURE_TPC_COMPRESSION,
++ gcvFEATURE_2D_OPF_YUV_OUTPUT,
++ gcvFEATURE_2D_FILTERBLIT_A8_ALPHA,
++ gcvFEATURE_2D_MULTI_SRC_BLT_TO_UNIFIED_DST_RECT,
++ gcvFEATURE_V2_COMPRESSION_Z16_FIX,
++
++ gcvFEATURE_VERTEX_INST_ID_AS_INTEGER,
++ gcvFEATURE_2D_YUV_MODE,
++ gcvFEATURE_ACE,
++ gcvFEATURE_COLOR_COMPRESSION,
++
++ gcvFEATURE_32BPP_COMPONENT_TEXTURE_CHANNEL_SWIZZLE,
++ gcvFEATURE_64BPP_HW_CLEAR_SUPPORT,
++ gcvFEATURE_TX_LERP_PRECISION_FIX,
++ gcvFEATURE_COMPRESSION_V2,
++ gcvFEATURE_MMU,
++ gcvFEATURE_COMPRESSION_V3,
++ gcvFEATURE_TX_DECOMPRESSOR,
++ gcvFEATURE_MRT_TILE_STATUS_BUFFER,
++ gcvFEATURE_COMPRESSION_V1,
++ gcvFEATURE_V1_COMPRESSION_Z16_DECOMPRESS_FIX,
++ gcvFEATURE_RTT,
++ gcvFEATURE_GENERICS,
++ gcvFEATURE_2D_ONE_PASS_FILTER,
++ gcvFEATURE_2D_ONE_PASS_FILTER_TAP,
++ gcvFEATURE_2D_POST_FLIP,
++ gcvFEATURE_2D_PIXEL_ALIGNMENT,
++ gcvFEATURE_CORRECT_AUTO_DISABLE_COUNT,
++ gcvFEATURE_CORRECT_AUTO_DISABLE_COUNT_WIDTH,
++
++ gcvFEATURE_HALTI3,
++ gcvFEATURE_EEZ,
++ gcvFEATURE_INTEGER_PIPE_FIX,
++ gcvFEATURE_PSOUTPUT_MAPPING,
++ gcvFEATURE_8K_RT_FIX,
++ gcvFEATURE_TX_TILE_STATUS_MAPPING,
++ gcvFEATURE_SRGB_RT_SUPPORT,
++ gcvFEATURE_UNIFORM_APERTURE,
++ gcvFEATURE_TEXTURE_16K,
++ gcvFEATURE_PA_FARZCLIPPING_FIX,
++ gcvFEATURE_PE_DITHER_COLORMASK_FIX,
++ gcvFEATURE_ZSCALE_FIX,
++
++ gcvFEATURE_MULTI_PIXELPIPES,
++ gcvFEATURE_PIPE_CL,
++
++ gcvFEATURE_BUG_FIXES18,
++
++ gcvFEATURE_UNIFIED_SAMPLERS,
++ gcvFEATURE_CL_PS_WALKER,
++ gcvFEATURE_NEW_HZ,
++
++ gcvFEATURE_TX_FRAC_PRECISION_6BIT,
++ gcvFEATURE_SH_INSTRUCTION_PREFETCH,
++ gcvFEATURE_PROBE,
++
++ gcvFEATURE_BUG_FIXES8,
++ gcvFEATURE_2D_ALL_QUAD,
++
++ gcvFEATURE_SINGLE_PIPE_HALTI1,
++
++ gcvFEATURE_BLOCK_SIZE_16x16,
++
++ gcvFEATURE_NO_USER_CSC,
++ gcvFEATURE_ANDROID_ONLY,
++ gcvFEATURE_HAS_PRODUCTID,
++
++ gcvFEATURE_V2_MSAA_COMP_FIX,
++
++ gcvFEATURE_S8_ONLY_RENDERING,
++
++ gcvFEATURE_SEPARATE_SRC_DST,
++
++ gcvFEATURE_FE_START_VERTEX_SUPPORT,
++ gcvFEATURE_RS_DEPTHSTENCIL_NATIVE_SUPPORT,
++
++ /* Insert features above this comment only. */
++ gcvFEATURE_COUNT /* Not a feature. */
++}
++gceFEATURE;
++
++/* Chip SWWA. */
++typedef enum _gceSWWA
++{
++ gcvSWWA_601 = 0,
++ gcvSWWA_706,
++ gcvSWWA_1163,
++ gcvSWWA_1165,
++ /* Insert SWWA above this comment only. */
++ gcvSWWA_COUNT /* Not a SWWA. */
++}
++gceSWWA;
++
++
++/* Option Set*/
++typedef enum _gceOPITON
++{
++ /* HW setting we take PREFER */
++ gcvOPTION_PREFER_MULTIPIPE_RS = 0,
++ gcvOPTION_PREFER_ZCONVERT_BYPASS =1,
++
++
++ gcvOPTION_HW_NULL = 50,
++ gcvOPTION_PRINT_OPTION = 51,
++
++ gcvOPTION_FBO_PREFER_MEM = 80,
++
++ /* Insert option above this comment only */
++ gcvOPTION_COUNT /* Not a OPTION*/
++}
++gceOPTION;
++
++typedef enum _gceFRAMEINFO
++{
++ gcvFRAMEINFO_FRAME_NUM = 0,
++ gcvFRAMEINFO_DRAW_NUM = 1,
++ gcvFRAMEINFO_DRAW_DUAL16_NUM = 2,
++ gcvFRAMEINFO_DRAW_FL32_NUM = 3,
++
++
++ gcvFRAMEINFO_COUNT,
++}
++gceFRAMEINFO;
++
++typedef enum _gceFRAMEINFO_OP
++{
++ gcvFRAMEINFO_OP_INC = 0,
++ gcvFRAMEINFO_OP_DEC = 1,
++ gcvFRAMEINFO_OP_ZERO = 2,
++ gcvFRAMEINFO_OP_GET = 3,
++
++
++ gcvFRAMEINFO_OP_COUNT,
++}
++gceFRAMEINFO_OP;
++
++
++/* Chip Power Status. */
++typedef enum _gceCHIPPOWERSTATE
++{
++ gcvPOWER_ON = 0,
++ gcvPOWER_OFF,
++ gcvPOWER_IDLE,
++ gcvPOWER_SUSPEND,
++ gcvPOWER_SUSPEND_ATPOWERON,
++ gcvPOWER_OFF_ATPOWERON,
++ gcvPOWER_IDLE_BROADCAST,
++ gcvPOWER_SUSPEND_BROADCAST,
++ gcvPOWER_OFF_BROADCAST,
++ gcvPOWER_OFF_RECOVERY,
++ gcvPOWER_OFF_TIMEOUT,
++ gcvPOWER_ON_AUTO
++}
++gceCHIPPOWERSTATE;
++
++/* CPU cache operations */
++typedef enum _gceCACHEOPERATION
++{
++ gcvCACHE_CLEAN = 0x01,
++ gcvCACHE_INVALIDATE = 0x02,
++ gcvCACHE_FLUSH = gcvCACHE_CLEAN | gcvCACHE_INVALIDATE,
++ gcvCACHE_MEMORY_BARRIER = 0x04
++}
++gceCACHEOPERATION;
++
++/* Surface types. */
++typedef enum _gceSURF_TYPE
++{
++ gcvSURF_TYPE_UNKNOWN = 0,
++ gcvSURF_INDEX,
++ gcvSURF_VERTEX,
++ gcvSURF_TEXTURE,
++ gcvSURF_RENDER_TARGET,
++ gcvSURF_DEPTH,
++ gcvSURF_BITMAP,
++ gcvSURF_TILE_STATUS,
++ gcvSURF_IMAGE,
++ gcvSURF_MASK,
++ gcvSURF_SCISSOR,
++ gcvSURF_HIERARCHICAL_DEPTH,
++ gcvSURF_NUM_TYPES, /* Make sure this is the last one! */
++
++ /* Combinations. */
++ gcvSURF_NO_TILE_STATUS = 0x100,
++ gcvSURF_NO_VIDMEM = 0x200, /* Used to allocate surfaces with no underlying vidmem node.
++ In Android, vidmem node is allocated by another process. */
++ gcvSURF_CACHEABLE = 0x400, /* Used to allocate a cacheable surface */
++
++ gcvSURF_FLIP = 0x800, /* The Resolve Target the will been flip resolve from RT */
++
++ gcvSURF_TILE_STATUS_DIRTY = 0x1000, /* Init tile status to all dirty */
++
++ gcvSURF_LINEAR = 0x2000,
++
++ gcvSURF_CREATE_AS_TEXTURE = 0x4000, /* create it as a texture */
++
++ gcvSURF_PROTECTED_CONTENT = 0x8000, /* create it as content protected */
++
++ /* Create it as no compression, valid on when it has tile status. */
++ gcvSURF_NO_COMPRESSION = 0x40000,
++
++ gcvSURF_CONTIGUOUS = 0x20000, /*create it as contiguous */
++
++ gcvSURF_TEXTURE_LINEAR = gcvSURF_TEXTURE
++ | gcvSURF_LINEAR,
++
++ gcvSURF_RENDER_TARGET_LINEAR = gcvSURF_RENDER_TARGET
++ | gcvSURF_LINEAR,
++
++ gcvSURF_RENDER_TARGET_NO_TILE_STATUS = gcvSURF_RENDER_TARGET
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_RENDER_TARGET_TS_DIRTY = gcvSURF_RENDER_TARGET
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ gcvSURF_DEPTH_NO_TILE_STATUS = gcvSURF_DEPTH
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_DEPTH_TS_DIRTY = gcvSURF_DEPTH
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ /* Supported surface types with no vidmem node. */
++ gcvSURF_BITMAP_NO_VIDMEM = gcvSURF_BITMAP
++ | gcvSURF_NO_VIDMEM,
++
++ gcvSURF_TEXTURE_NO_VIDMEM = gcvSURF_TEXTURE
++ | gcvSURF_NO_VIDMEM,
++
++ /* Cacheable surface types with no vidmem node. */
++ gcvSURF_CACHEABLE_BITMAP_NO_VIDMEM = gcvSURF_BITMAP_NO_VIDMEM
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_CACHEABLE_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_FLIP_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_FLIP,
++}
++gceSURF_TYPE;
++
++typedef enum _gceSURF_USAGE
++{
++ gcvSURF_USAGE_UNKNOWN,
++ gcvSURF_USAGE_RESOLVE_AFTER_CPU,
++ gcvSURF_USAGE_RESOLVE_AFTER_3D
++}
++gceSURF_USAGE;
++
++typedef enum _gceSURF_COLOR_SPACE
++{
++ gcvSURF_COLOR_SPACE_UNKNOWN,
++ gcvSURF_COLOR_SPACE_LINEAR,
++ gcvSURF_COLOR_SPACE_NONLINEAR,
++}
++gceSURF_COLOR_SPACE;
++
++typedef enum _gceSURF_COLOR_TYPE
++{
++ gcvSURF_COLOR_UNKNOWN = 0,
++ gcvSURF_COLOR_LINEAR = 0x01,
++ gcvSURF_COLOR_ALPHA_PRE = 0x02,
++}
++gceSURF_COLOR_TYPE;
++
++/* Rotation. */
++typedef enum _gceSURF_ROTATION
++{
++ gcvSURF_0_DEGREE = 0,
++ gcvSURF_90_DEGREE,
++ gcvSURF_180_DEGREE,
++ gcvSURF_270_DEGREE,
++ gcvSURF_FLIP_X,
++ gcvSURF_FLIP_Y,
++
++ gcvSURF_POST_FLIP_X = 0x40000000,
++ gcvSURF_POST_FLIP_Y = 0x80000000,
++}
++gceSURF_ROTATION;
++
++/* Surface flag */
++typedef enum _gceSURF_FLAG
++{
++ /* None flag */
++ gcvSURF_FLAG_NONE = 0x0,
++ /* content is preserved after swap */
++ gcvSURF_FLAG_CONTENT_PRESERVED = 0x1,
++ /* content is updated after swap*/
++ gcvSURF_FLAG_CONTENT_UPDATED = 0x2,
++ /* content is y inverted */
++ gcvSURF_FLAG_CONTENT_YINVERTED = 0x4,
++ /* content is protected */
++ gcvSURF_FLAG_CONTENT_PROTECTED = 0x8,
++ /* surface is contiguous. */
++ gcvSURF_FLAG_CONTIGUOUS = (1 << 4),
++}
++gceSURF_FLAG;
++
++typedef enum _gceMIPMAP_IMAGE_FORMAT
++{
++ gcvUNKNOWN_MIPMAP_IMAGE_FORMAT = -2
++}
++gceMIPMAP_IMAGE_FORMAT;
++
++/* Surface formats. */
++typedef enum _gceSURF_FORMAT
++{
++ /* Unknown format. */
++ gcvSURF_UNKNOWN = 0,
++
++ /* Palettized formats. */
++ gcvSURF_INDEX1 = 100,
++ gcvSURF_INDEX4,
++ gcvSURF_INDEX8,
++
++ /* RGB formats. */
++ gcvSURF_A2R2G2B2 = 200,
++ gcvSURF_R3G3B2,
++ gcvSURF_A8R3G3B2,
++ gcvSURF_X4R4G4B4,
++ gcvSURF_A4R4G4B4,
++ gcvSURF_R4G4B4A4,
++ gcvSURF_X1R5G5B5,
++ gcvSURF_A1R5G5B5,
++ gcvSURF_R5G5B5A1,
++ gcvSURF_R5G6B5,
++ gcvSURF_R8G8B8,
++ gcvSURF_X8R8G8B8,
++ gcvSURF_A8R8G8B8,
++ gcvSURF_R8G8B8A8,
++ gcvSURF_G8R8G8B8,
++ gcvSURF_R8G8B8G8,
++ gcvSURF_X2R10G10B10,
++ gcvSURF_A2R10G10B10,
++ gcvSURF_X12R12G12B12,
++ gcvSURF_A12R12G12B12,
++ gcvSURF_X16R16G16B16,
++ gcvSURF_A16R16G16B16,
++ gcvSURF_A32R32G32B32,
++ gcvSURF_R8G8B8X8,
++ gcvSURF_R5G5B5X1,
++ gcvSURF_R4G4B4X4,
++ gcvSURF_X16R16G16B16_2_A8R8G8B8,
++ gcvSURF_A16R16G16B16_2_A8R8G8B8,
++ gcvSURF_A32R32G32B32_2_G32R32F,
++ gcvSURF_A32R32G32B32_4_A8R8G8B8,
++
++ /* BGR formats. */
++ gcvSURF_A4B4G4R4 = 300,
++ gcvSURF_A1B5G5R5,
++ gcvSURF_B5G6R5,
++ gcvSURF_B8G8R8,
++ gcvSURF_B16G16R16,
++ gcvSURF_X8B8G8R8,
++ gcvSURF_A8B8G8R8,
++ gcvSURF_A2B10G10R10,
++ gcvSURF_X16B16G16R16,
++ gcvSURF_A16B16G16R16,
++ gcvSURF_B32G32R32,
++ gcvSURF_X32B32G32R32,
++ gcvSURF_A32B32G32R32,
++ gcvSURF_B4G4R4A4,
++ gcvSURF_B5G5R5A1,
++ gcvSURF_B8G8R8X8,
++ gcvSURF_B8G8R8A8,
++ gcvSURF_X4B4G4R4,
++ gcvSURF_X1B5G5R5,
++ gcvSURF_B4G4R4X4,
++ gcvSURF_B5G5R5X1,
++ gcvSURF_X2B10G10R10,
++ gcvSURF_B8G8R8_SNORM,
++ gcvSURF_X8B8G8R8_SNORM,
++ gcvSURF_A8B8G8R8_SNORM,
++ gcvSURF_A8B12G12R12_2_A8R8G8B8,
++
++ /* Compressed formats. */
++ gcvSURF_DXT1 = 400,
++ gcvSURF_DXT2,
++ gcvSURF_DXT3,
++ gcvSURF_DXT4,
++ gcvSURF_DXT5,
++ gcvSURF_CXV8U8,
++ gcvSURF_ETC1,
++ gcvSURF_R11_EAC,
++ gcvSURF_SIGNED_R11_EAC,
++ gcvSURF_RG11_EAC,
++ gcvSURF_SIGNED_RG11_EAC,
++ gcvSURF_RGB8_ETC2,
++ gcvSURF_SRGB8_ETC2,
++ gcvSURF_RGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_RGBA8_ETC2_EAC,
++ gcvSURF_SRGB8_ALPHA8_ETC2_EAC,
++
++ /* YUV formats. */
++ gcvSURF_YUY2 = 500,
++ gcvSURF_UYVY,
++ gcvSURF_YV12,
++ gcvSURF_I420,
++ gcvSURF_NV12,
++ gcvSURF_NV21,
++ gcvSURF_NV16,
++ gcvSURF_NV61,
++ gcvSURF_YVYU,
++ gcvSURF_VYUY,
++
++ /* Depth formats. */
++ gcvSURF_D16 = 600,
++ gcvSURF_D24S8,
++ gcvSURF_D32,
++ gcvSURF_D24X8,
++ gcvSURF_D32F,
++ gcvSURF_S8D32F,
++ gcvSURF_S8D32F_1_G32R32F,
++ gcvSURF_S8D32F_2_A8R8G8B8,
++ gcvSURF_D24S8_1_A8R8G8B8,
++ gcvSURF_S8,
++
++ /* Alpha formats. */
++ gcvSURF_A4 = 700,
++ gcvSURF_A8,
++ gcvSURF_A12,
++ gcvSURF_A16,
++ gcvSURF_A32,
++ gcvSURF_A1,
++
++ /* Luminance formats. */
++ gcvSURF_L4 = 800,
++ gcvSURF_L8,
++ gcvSURF_L12,
++ gcvSURF_L16,
++ gcvSURF_L32,
++ gcvSURF_L1,
++
++ /* Alpha/Luminance formats. */
++ gcvSURF_A4L4 = 900,
++ gcvSURF_A2L6,
++ gcvSURF_A8L8,
++ gcvSURF_A4L12,
++ gcvSURF_A12L12,
++ gcvSURF_A16L16,
++
++ /* Bump formats. */
++ gcvSURF_L6V5U5 = 1000,
++ gcvSURF_V8U8,
++ gcvSURF_X8L8V8U8,
++ gcvSURF_Q8W8V8U8,
++ gcvSURF_A2W10V10U10,
++ gcvSURF_V16U16,
++ gcvSURF_Q16W16V16U16,
++
++ /* R/RG/RA formats. */
++ gcvSURF_R8 = 1100,
++ gcvSURF_X8R8,
++ gcvSURF_G8R8,
++ gcvSURF_X8G8R8,
++ gcvSURF_A8R8,
++ gcvSURF_R16,
++ gcvSURF_X16R16,
++ gcvSURF_G16R16,
++ gcvSURF_X16G16R16,
++ gcvSURF_A16R16,
++ gcvSURF_R32,
++ gcvSURF_X32R32,
++ gcvSURF_G32R32,
++ gcvSURF_X32G32R32,
++ gcvSURF_A32R32,
++ gcvSURF_RG16,
++ gcvSURF_R8_SNORM,
++ gcvSURF_G8R8_SNORM,
++
++ gcvSURF_R8_1_X8R8G8B8,
++ gcvSURF_G8R8_1_X8R8G8B8,
++
++ /* Floating point formats. */
++ gcvSURF_R16F = 1200,
++ gcvSURF_X16R16F,
++ gcvSURF_G16R16F,
++ gcvSURF_X16G16R16F,
++ gcvSURF_B16G16R16F,
++ gcvSURF_X16B16G16R16F,
++ gcvSURF_A16B16G16R16F,
++ gcvSURF_R32F,
++ gcvSURF_X32R32F,
++ gcvSURF_G32R32F,
++ gcvSURF_X32G32R32F,
++ gcvSURF_B32G32R32F,
++ gcvSURF_X32B32G32R32F,
++ gcvSURF_A32B32G32R32F,
++ gcvSURF_A16F,
++ gcvSURF_L16F,
++ gcvSURF_A16L16F,
++ gcvSURF_A16R16F,
++ gcvSURF_A32F,
++ gcvSURF_L32F,
++ gcvSURF_A32L32F,
++ gcvSURF_A32R32F,
++ gcvSURF_E5B9G9R9,
++ gcvSURF_B10G11R11F,
++
++ gcvSURF_X16B16G16R16F_2_A8R8G8B8,
++ gcvSURF_A16B16G16R16F_2_A8R8G8B8,
++ gcvSURF_G32R32F_2_A8R8G8B8,
++ gcvSURF_X32B32G32R32F_2_G32R32F,
++ gcvSURF_A32B32G32R32F_2_G32R32F,
++ gcvSURF_X32B32G32R32F_4_A8R8G8B8,
++ gcvSURF_A32B32G32R32F_4_A8R8G8B8,
++
++ gcvSURF_R16F_1_A4R4G4B4,
++ gcvSURF_G16R16F_1_A8R8G8B8,
++ gcvSURF_B16G16R16F_2_A8R8G8B8,
++
++ gcvSURF_R32F_1_A8R8G8B8,
++ gcvSURF_B32G32R32F_3_A8R8G8B8,
++
++ gcvSURF_B10G11R11F_1_A8R8G8B8,
++
++
++ /* sRGB format. */
++ gcvSURF_SBGR8 = 1400,
++ gcvSURF_A8_SBGR8,
++ gcvSURF_X8_SBGR8,
++
++ /* Integer formats. */
++ gcvSURF_R8I = 1500,
++ gcvSURF_R8UI,
++ gcvSURF_R16I,
++ gcvSURF_R16UI,
++ gcvSURF_R32I,
++ gcvSURF_R32UI,
++ gcvSURF_X8R8I,
++ gcvSURF_G8R8I,
++ gcvSURF_X8R8UI,
++ gcvSURF_G8R8UI,
++ gcvSURF_X16R16I,
++ gcvSURF_G16R16I,
++ gcvSURF_X16R16UI,
++ gcvSURF_G16R16UI,
++ gcvSURF_X32R32I,
++ gcvSURF_G32R32I,
++ gcvSURF_X32R32UI,
++ gcvSURF_G32R32UI,
++ gcvSURF_X8G8R8I,
++ gcvSURF_B8G8R8I,
++ gcvSURF_X8G8R8UI,
++ gcvSURF_B8G8R8UI,
++ gcvSURF_X16G16R16I,
++ gcvSURF_B16G16R16I,
++ gcvSURF_X16G16R16UI,
++ gcvSURF_B16G16R16UI,
++ gcvSURF_X32G32R32I,
++ gcvSURF_B32G32R32I,
++ gcvSURF_X32G32R32UI,
++ gcvSURF_B32G32R32UI,
++ gcvSURF_X8B8G8R8I,
++ gcvSURF_A8B8G8R8I,
++ gcvSURF_X8B8G8R8UI,
++ gcvSURF_A8B8G8R8UI,
++ gcvSURF_X16B16G16R16I,
++ gcvSURF_A16B16G16R16I,
++ gcvSURF_X16B16G16R16UI,
++ gcvSURF_A16B16G16R16UI,
++ gcvSURF_X32B32G32R32I,
++ gcvSURF_A32B32G32R32I,
++ gcvSURF_X32B32G32R32UI,
++ gcvSURF_A32B32G32R32UI,
++ gcvSURF_A2B10G10R10UI,
++ gcvSURF_G32R32I_2_A8R8G8B8,
++ gcvSURF_G32R32UI_2_A8R8G8B8,
++ gcvSURF_X16B16G16R16I_2_A8R8G8B8,
++ gcvSURF_A16B16G16R16I_2_A8R8G8B8,
++ gcvSURF_X16B16G16R16UI_2_A8R8G8B8,
++ gcvSURF_A16B16G16R16UI_2_A8R8G8B8,
++ gcvSURF_X32B32G32R32I_2_G32R32I,
++ gcvSURF_A32B32G32R32I_2_G32R32I,
++ gcvSURF_X32B32G32R32I_3_A8R8G8B8,
++ gcvSURF_A32B32G32R32I_4_A8R8G8B8,
++ gcvSURF_X32B32G32R32UI_2_G32R32UI,
++ gcvSURF_A32B32G32R32UI_2_G32R32UI,
++ gcvSURF_X32B32G32R32UI_3_A8R8G8B8,
++ gcvSURF_A32B32G32R32UI_4_A8R8G8B8,
++ gcvSURF_A2B10G10R10UI_1_A8R8G8B8,
++ gcvSURF_A8B8G8R8I_1_A8R8G8B8,
++ gcvSURF_A8B8G8R8UI_1_A8R8G8B8,
++ gcvSURF_R8I_1_A4R4G4B4,
++ gcvSURF_R8UI_1_A4R4G4B4,
++ gcvSURF_R16I_1_A4R4G4B4,
++ gcvSURF_R16UI_1_A4R4G4B4,
++ gcvSURF_R32I_1_A8R8G8B8,
++ gcvSURF_R32UI_1_A8R8G8B8,
++ gcvSURF_X8R8I_1_A4R4G4B4,
++ gcvSURF_X8R8UI_1_A4R4G4B4,
++ gcvSURF_G8R8I_1_A4R4G4B4,
++ gcvSURF_G8R8UI_1_A4R4G4B4,
++ gcvSURF_X16R16I_1_A4R4G4B4,
++ gcvSURF_X16R16UI_1_A4R4G4B4,
++ gcvSURF_G16R16I_1_A8R8G8B8,
++ gcvSURF_G16R16UI_1_A8R8G8B8,
++ gcvSURF_X32R32I_1_A8R8G8B8,
++ gcvSURF_X32R32UI_1_A8R8G8B8,
++ gcvSURF_X8G8R8I_1_A4R4G4B4,
++ gcvSURF_X8G8R8UI_1_A4R4G4B4,
++ gcvSURF_B8G8R8I_1_A8R8G8B8,
++ gcvSURF_B8G8R8UI_1_A8R8G8B8,
++ gcvSURF_B16G16R16I_2_A8R8G8B8,
++ gcvSURF_B16G16R16UI_2_A8R8G8B8,
++ gcvSURF_B32G32R32I_3_A8R8G8B8,
++ gcvSURF_B32G32R32UI_3_A8R8G8B8,
++
++ /* ASTC formats. */
++ gcvSURF_ASTC4x4 = 1600,
++ gcvSURF_ASTC5x4,
++ gcvSURF_ASTC5x5,
++ gcvSURF_ASTC6x5,
++ gcvSURF_ASTC6x6,
++ gcvSURF_ASTC8x5,
++ gcvSURF_ASTC8x6,
++ gcvSURF_ASTC8x8,
++ gcvSURF_ASTC10x5,
++ gcvSURF_ASTC10x6,
++ gcvSURF_ASTC10x8,
++ gcvSURF_ASTC10x10,
++ gcvSURF_ASTC12x10,
++ gcvSURF_ASTC12x12,
++ gcvSURF_ASTC4x4_SRGB,
++ gcvSURF_ASTC5x4_SRGB,
++ gcvSURF_ASTC5x5_SRGB,
++ gcvSURF_ASTC6x5_SRGB,
++ gcvSURF_ASTC6x6_SRGB,
++ gcvSURF_ASTC8x5_SRGB,
++ gcvSURF_ASTC8x6_SRGB,
++ gcvSURF_ASTC8x8_SRGB,
++ gcvSURF_ASTC10x5_SRGB,
++ gcvSURF_ASTC10x6_SRGB,
++ gcvSURF_ASTC10x8_SRGB,
++ gcvSURF_ASTC10x10_SRGB,
++ gcvSURF_ASTC12x10_SRGB,
++ gcvSURF_ASTC12x12_SRGB,
++
++ gcvSURF_FORMAT_COUNT
++}
++gceSURF_FORMAT;
++
++/* Format modifiers. */
++typedef enum _gceSURF_FORMAT_MODE
++{
++ gcvSURF_FORMAT_OCL = 0x80000000
++}
++gceSURF_FORMAT_MODE;
++
++/* Pixel swizzle modes. */
++typedef enum _gceSURF_SWIZZLE
++{
++ gcvSURF_NOSWIZZLE = 0,
++ gcvSURF_ARGB,
++ gcvSURF_ABGR,
++ gcvSURF_RGBA,
++ gcvSURF_BGRA
++}
++gceSURF_SWIZZLE;
++
++/* Transparency modes. */
++typedef enum _gceSURF_TRANSPARENCY
++{
++ /* Valid only for PE 1.0 */
++ gcvSURF_OPAQUE = 0,
++ gcvSURF_SOURCE_MATCH,
++ gcvSURF_SOURCE_MASK,
++ gcvSURF_PATTERN_MASK,
++}
++gceSURF_TRANSPARENCY;
++
++/* Surface Alignment. */
++typedef enum _gceSURF_ALIGNMENT
++{
++ gcvSURF_FOUR = 0,
++ gcvSURF_SIXTEEN,
++ gcvSURF_SUPER_TILED,
++ gcvSURF_SPLIT_TILED,
++ gcvSURF_SPLIT_SUPER_TILED
++}
++gceSURF_ALIGNMENT;
++
++/* Surface Addressing. */
++typedef enum _gceSURF_ADDRESSING
++{
++ gcvSURF_NO_STRIDE_TILED = 0,
++ gcvSURF_NO_STRIDE_LINEAR,
++ gcvSURF_STRIDE_TILED,
++ gcvSURF_STRIDE_LINEAR
++}
++gceSURF_ADDRESSING;
++
++/* Transparency modes. */
++typedef enum _gce2D_TRANSPARENCY
++{
++ /* Valid only for PE 2.0 */
++ gcv2D_OPAQUE = 0,
++ gcv2D_KEYED,
++ gcv2D_MASKED
++}
++gce2D_TRANSPARENCY;
++
++/* Mono packing modes. */
++typedef enum _gceSURF_MONOPACK
++{
++ gcvSURF_PACKED8 = 0,
++ gcvSURF_PACKED16,
++ gcvSURF_PACKED32,
++ gcvSURF_UNPACKED,
++}
++gceSURF_MONOPACK;
++
++/* Blending modes. */
++typedef enum _gceSURF_BLEND_MODE
++{
++ /* Porter-Duff blending modes. */
++ /* Fsrc Fdst */
++ gcvBLEND_CLEAR = 0, /* 0 0 */
++ gcvBLEND_SRC, /* 1 0 */
++ gcvBLEND_DST, /* 0 1 */
++ gcvBLEND_SRC_OVER_DST, /* 1 1 - Asrc */
++ gcvBLEND_DST_OVER_SRC, /* 1 - Adst 1 */
++ gcvBLEND_SRC_IN_DST, /* Adst 0 */
++ gcvBLEND_DST_IN_SRC, /* 0 Asrc */
++ gcvBLEND_SRC_OUT_DST, /* 1 - Adst 0 */
++ gcvBLEND_DST_OUT_SRC, /* 0 1 - Asrc */
++ gcvBLEND_SRC_ATOP_DST, /* Adst 1 - Asrc */
++ gcvBLEND_DST_ATOP_SRC, /* 1 - Adst Asrc */
++ gcvBLEND_SRC_XOR_DST, /* 1 - Adst 1 - Asrc */
++
++ /* Special blending modes. */
++ gcvBLEND_SET, /* DST = 1 */
++ gcvBLEND_SUB /* DST = DST * (1 - SRC) */
++}
++gceSURF_BLEND_MODE;
++
++/* Per-pixel alpha modes. */
++typedef enum _gceSURF_PIXEL_ALPHA_MODE
++{
++ gcvSURF_PIXEL_ALPHA_STRAIGHT = 0,
++ gcvSURF_PIXEL_ALPHA_INVERSED
++}
++gceSURF_PIXEL_ALPHA_MODE;
++
++/* Global alpha modes. */
++typedef enum _gceSURF_GLOBAL_ALPHA_MODE
++{
++ gcvSURF_GLOBAL_ALPHA_OFF = 0,
++ gcvSURF_GLOBAL_ALPHA_ON,
++ gcvSURF_GLOBAL_ALPHA_SCALE
++}
++gceSURF_GLOBAL_ALPHA_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gceSURF_PIXEL_COLOR_MODE
++{
++ gcvSURF_COLOR_STRAIGHT = 0,
++ gcvSURF_COLOR_MULTIPLY
++}
++gceSURF_PIXEL_COLOR_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_PIXEL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_COLOR_MULTIPLY_ENABLE
++}
++gce2D_PIXEL_COLOR_MULTIPLY_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_GLOBAL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_GLOBAL_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_ALPHA,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_COLOR
++}
++gce2D_GLOBAL_COLOR_MULTIPLY_MODE;
++
++/* Alpha blending factor modes. */
++typedef enum _gceSURF_BLEND_FACTOR_MODE
++{
++ gcvSURF_BLEND_ZERO = 0,
++ gcvSURF_BLEND_ONE,
++ gcvSURF_BLEND_STRAIGHT,
++ gcvSURF_BLEND_INVERSED,
++ gcvSURF_BLEND_COLOR,
++ gcvSURF_BLEND_COLOR_INVERSED,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED,
++ gcvSURF_BLEND_STRAIGHT_NO_CROSS,
++ gcvSURF_BLEND_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_COLOR_NO_CROSS,
++ gcvSURF_BLEND_COLOR_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED_CROSS
++}
++gceSURF_BLEND_FACTOR_MODE;
++
++/* Alpha blending porter duff rules. */
++typedef enum _gce2D_PORTER_DUFF_RULE
++{
++ gcvPD_CLEAR = 0,
++ gcvPD_SRC,
++ gcvPD_SRC_OVER,
++ gcvPD_DST_OVER,
++ gcvPD_SRC_IN,
++ gcvPD_DST_IN,
++ gcvPD_SRC_OUT,
++ gcvPD_DST_OUT,
++ gcvPD_SRC_ATOP,
++ gcvPD_DST_ATOP,
++ gcvPD_ADD,
++ gcvPD_XOR,
++ gcvPD_DST
++}
++gce2D_PORTER_DUFF_RULE;
++
++/* Alpha blending factor modes. */
++typedef enum _gce2D_YUV_COLOR_MODE
++{
++ gcv2D_YUV_601= 0,
++ gcv2D_YUV_709,
++ gcv2D_YUV_USER_DEFINED,
++ gcv2D_YUV_USER_DEFINED_CLAMP,
++
++ /* Default setting is for src. gcv2D_YUV_DST
++ can be ORed to set dst.
++ */
++ gcv2D_YUV_DST = 0x80000000,
++}
++gce2D_YUV_COLOR_MODE;
++
++typedef enum _gce2D_COMMAND
++{
++ gcv2D_CLEAR = 0,
++ gcv2D_LINE,
++ gcv2D_BLT,
++ gcv2D_STRETCH,
++ gcv2D_HOR_FILTER,
++ gcv2D_VER_FILTER,
++ gcv2D_MULTI_SOURCE_BLT,
++ gcv2D_FILTER_BLT,
++}
++gce2D_COMMAND;
++
++typedef enum _gce2D_TILE_STATUS_CONFIG
++{
++ gcv2D_TSC_DISABLE = 0,
++ gcv2D_TSC_ENABLE = 0x00000001,
++ gcv2D_TSC_COMPRESSED = 0x00000002,
++ gcv2D_TSC_DOWN_SAMPLER = 0x00000004,
++ gcv2D_TSC_2D_COMPRESSED = 0x00000008,
++ gcv2D_TSC_TPC_COMPRESSED = 0x00000010,
++}
++gce2D_TILE_STATUS_CONFIG;
++
++typedef enum _gce2D_QUERY
++{
++ gcv2D_QUERY_RGB_ADDRESS_MIN_ALIGN = 0,
++ gcv2D_QUERY_RGB_STRIDE_MIN_ALIGN,
++ gcv2D_QUERY_YUV_ADDRESS_MIN_ALIGN,
++ gcv2D_QUERY_YUV_STRIDE_MIN_ALIGN,
++}
++gce2D_QUERY;
++
++typedef enum _gce2D_SUPER_TILE_VERSION
++{
++ gcv2D_SUPER_TILE_VERSION_V1 = 1,
++ gcv2D_SUPER_TILE_VERSION_V2 = 2,
++ gcv2D_SUPER_TILE_VERSION_V3 = 3,
++}
++gce2D_SUPER_TILE_VERSION;
++
++typedef enum _gce2D_STATE
++{
++ gcv2D_STATE_SPECIAL_FILTER_MIRROR_MODE = 1,
++ gcv2D_STATE_SUPER_TILE_VERSION,
++ gcv2D_STATE_EN_GAMMA,
++ gcv2D_STATE_DE_GAMMA,
++ gcv2D_STATE_MULTI_SRC_BLIT_UNIFIED_DST_RECT,
++ gcv2D_STATE_PROFILE_ENABLE,
++ gcv2D_STATE_XRGB_ENABLE,
++
++ gcv2D_STATE_ARRAY_EN_GAMMA = 0x10001,
++ gcv2D_STATE_ARRAY_DE_GAMMA,
++ gcv2D_STATE_ARRAY_CSC_YUV_TO_RGB,
++ gcv2D_STATE_ARRAY_CSC_RGB_TO_YUV,
++}
++gce2D_STATE;
++
++typedef enum _gce2D_STATE_PROFILE
++{
++ gcv2D_STATE_PROFILE_NONE = 0x0,
++ gcv2D_STATE_PROFILE_COMMAND = 0x1,
++ gcv2D_STATE_PROFILE_SURFACE = 0x2,
++ gcv2D_STATE_PROFILE_ALL = 0xFFFF,
++}
++gce2D_STATE_PROFILE;
++
++/* Texture object types */
++typedef enum _gceTEXTURE_TYPE
++{
++ gcvTEXTURE_UNKNOWN = 0,
++ gcvTEXTURE_1D,
++ gcvTEXTURE_2D,
++ gcvTEXTURE_3D,
++ gcvTEXTURE_CUBEMAP,
++ gcvTEXTURE_1D_ARRAY,
++ gcvTEXTURE_2D_ARRAY,
++ gcvTEXTURE_EXTERNAL
++}
++gceTEXTURE_TYPE;
++
++#if gcdENABLE_3D
++/* Texture functions. */
++typedef enum _gceTEXTURE_FUNCTION
++{
++ gcvTEXTURE_DUMMY = 0,
++ gcvTEXTURE_REPLACE = 0,
++ gcvTEXTURE_MODULATE,
++ gcvTEXTURE_ADD,
++ gcvTEXTURE_ADD_SIGNED,
++ gcvTEXTURE_INTERPOLATE,
++ gcvTEXTURE_SUBTRACT,
++ gcvTEXTURE_DOT3
++}
++gceTEXTURE_FUNCTION;
++
++/* Texture sources. */
++typedef enum _gceTEXTURE_SOURCE
++{
++ gcvCOLOR_FROM_TEXTURE = 0,
++ gcvCOLOR_FROM_CONSTANT_COLOR,
++ gcvCOLOR_FROM_PRIMARY_COLOR,
++ gcvCOLOR_FROM_PREVIOUS_COLOR
++}
++gceTEXTURE_SOURCE;
++
++/* Texture source channels. */
++typedef enum _gceTEXTURE_CHANNEL
++{
++ gcvFROM_COLOR = 0,
++ gcvFROM_ONE_MINUS_COLOR,
++ gcvFROM_ALPHA,
++ gcvFROM_ONE_MINUS_ALPHA
++}
++gceTEXTURE_CHANNEL;
++#endif /* gcdENABLE_3D */
++
++/* Filter types. */
++typedef enum _gceFILTER_TYPE
++{
++ gcvFILTER_SYNC = 0,
++ gcvFILTER_BLUR,
++ gcvFILTER_USER
++}
++gceFILTER_TYPE;
++
++/* Filter pass types. */
++typedef enum _gceFILTER_PASS_TYPE
++{
++ gcvFILTER_HOR_PASS = 0,
++ gcvFILTER_VER_PASS
++}
++gceFILTER_PASS_TYPE;
++
++/* Endian hints. */
++typedef enum _gceENDIAN_HINT
++{
++ gcvENDIAN_NO_SWAP = 0,
++ gcvENDIAN_SWAP_WORD,
++ gcvENDIAN_SWAP_DWORD
++}
++gceENDIAN_HINT;
++
++/* Tiling modes. */
++typedef enum _gceTILING
++{
++ gcvINVALIDTILED = 0x0, /* Invalid tiling */
++ /* Tiling basic modes enum'ed in power of 2. */
++ gcvLINEAR = 0x1, /* No tiling. */
++ gcvTILED = 0x2, /* 4x4 tiling. */
++ gcvSUPERTILED = 0x4, /* 64x64 tiling. */
++ gcvMINORTILED = 0x8, /* 2x2 tiling. */
++
++ /* Tiling special layouts. */
++ gcvTILING_SPLIT_BUFFER = 0x100,
++
++ /* Tiling combination layouts. */
++ gcvMULTI_TILED = gcvTILED
++ | gcvTILING_SPLIT_BUFFER,
++
++ gcvMULTI_SUPERTILED = gcvSUPERTILED
++ | gcvTILING_SPLIT_BUFFER,
++}
++gceTILING;
++
++/* 2D pattern type. */
++typedef enum _gce2D_PATTERN
++{
++ gcv2D_PATTERN_SOLID = 0,
++ gcv2D_PATTERN_MONO,
++ gcv2D_PATTERN_COLOR,
++ gcv2D_PATTERN_INVALID
++}
++gce2D_PATTERN;
++
++/* 2D source type. */
++typedef enum _gce2D_SOURCE
++{
++ gcv2D_SOURCE_MASKED = 0,
++ gcv2D_SOURCE_MONO,
++ gcv2D_SOURCE_COLOR,
++ gcv2D_SOURCE_INVALID
++}
++gce2D_SOURCE;
++
++/* Pipes. */
++typedef enum _gcePIPE_SELECT
++{
++ gcvPIPE_INVALID = ~0,
++ gcvPIPE_3D = 0,
++ gcvPIPE_2D
++}
++gcePIPE_SELECT;
++
++/* Hardware type. */
++typedef enum _gceHARDWARE_TYPE
++{
++ gcvHARDWARE_INVALID = 0x00,
++ gcvHARDWARE_3D = 0x01,
++ gcvHARDWARE_2D = 0x02,
++ gcvHARDWARE_VG = 0x04,
++ gcvHARDWARE_3D2D = gcvHARDWARE_3D | gcvHARDWARE_2D
++}
++gceHARDWARE_TYPE;
++
++#define gcdCHIP_COUNT 3
++
++typedef enum _gceMMU_MODE
++{
++ gcvMMU_MODE_1K,
++ gcvMMU_MODE_4K,
++} gceMMU_MODE;
++
++/* User signal command codes. */
++typedef enum _gceUSER_SIGNAL_COMMAND_CODES
++{
++ gcvUSER_SIGNAL_CREATE,
++ gcvUSER_SIGNAL_DESTROY,
++ gcvUSER_SIGNAL_SIGNAL,
++ gcvUSER_SIGNAL_WAIT,
++ gcvUSER_SIGNAL_MAP,
++ gcvUSER_SIGNAL_UNMAP,
++}
++gceUSER_SIGNAL_COMMAND_CODES;
++
++/* Sync point command codes. */
++typedef enum _gceSYNC_POINT_COMMAND_CODES
++{
++ gcvSYNC_POINT_CREATE,
++ gcvSYNC_POINT_DESTROY,
++ gcvSYNC_POINT_SIGNAL,
++}
++gceSYNC_POINT_COMMAND_CODES;
++
++/* Shared buffer command codes. */
++typedef enum _gceSHBUF_COMMAND_CODES
++{
++ gcvSHBUF_CREATE,
++ gcvSHBUF_DESTROY,
++ gcvSHBUF_MAP,
++ gcvSHBUF_WRITE,
++ gcvSHBUF_READ,
++}
++gceSHBUF_COMMAND_CODES;
++
++/* Event locations. */
++typedef enum _gceKERNEL_WHERE
++{
++ gcvKERNEL_COMMAND,
++ gcvKERNEL_VERTEX,
++ gcvKERNEL_TRIANGLE,
++ gcvKERNEL_TEXTURE,
++ gcvKERNEL_PIXEL,
++}
++gceKERNEL_WHERE;
++
++#if gcdENABLE_VG
++/* Hardware blocks. */
++typedef enum _gceBLOCK
++{
++ gcvBLOCK_COMMAND,
++ gcvBLOCK_TESSELLATOR,
++ gcvBLOCK_TESSELLATOR2,
++ gcvBLOCK_TESSELLATOR3,
++ gcvBLOCK_RASTER,
++ gcvBLOCK_VG,
++ gcvBLOCK_VG2,
++ gcvBLOCK_VG3,
++ gcvBLOCK_PIXEL,
++
++ /* Number of defined blocks. */
++ gcvBLOCK_COUNT
++}
++gceBLOCK;
++#endif
++
++/* gcdDUMP message type. */
++typedef enum _gceDEBUG_MESSAGE_TYPE
++{
++ gcvMESSAGE_TEXT,
++ gcvMESSAGE_DUMP
++}
++gceDEBUG_MESSAGE_TYPE;
++
++/* Shading format. */
++typedef enum _gceSHADING
++{
++ gcvSHADING_SMOOTH,
++ gcvSHADING_FLAT_D3D,
++ gcvSHADING_FLAT_OPENGL,
++}
++gceSHADING;
++
++/* Culling modes. */
++typedef enum _gceCULL
++{
++ gcvCULL_NONE,
++ gcvCULL_CCW,
++ gcvCULL_CW,
++}
++gceCULL;
++
++/* Fill modes. */
++typedef enum _gceFILL
++{
++ gcvFILL_POINT,
++ gcvFILL_WIRE_FRAME,
++ gcvFILL_SOLID,
++}
++gceFILL;
++
++/* Compare modes. */
++typedef enum _gceCOMPARE
++{
++ gcvCOMPARE_INVALID = 0,
++ gcvCOMPARE_NEVER,
++ gcvCOMPARE_NOT_EQUAL,
++ gcvCOMPARE_LESS,
++ gcvCOMPARE_LESS_OR_EQUAL,
++ gcvCOMPARE_EQUAL,
++ gcvCOMPARE_GREATER,
++ gcvCOMPARE_GREATER_OR_EQUAL,
++ gcvCOMPARE_ALWAYS,
++}
++gceCOMPARE;
++
++/* Stencil modes. */
++typedef enum _gceSTENCIL_MODE
++{
++ gcvSTENCIL_NONE,
++ gcvSTENCIL_SINGLE_SIDED,
++ gcvSTENCIL_DOUBLE_SIDED,
++}
++gceSTENCIL_MODE;
++
++/* Stencil operations. */
++typedef enum _gceSTENCIL_OPERATION
++{
++ gcvSTENCIL_KEEP,
++ gcvSTENCIL_REPLACE,
++ gcvSTENCIL_ZERO,
++ gcvSTENCIL_INVERT,
++ gcvSTENCIL_INCREMENT,
++ gcvSTENCIL_DECREMENT,
++ gcvSTENCIL_INCREMENT_SATURATE,
++ gcvSTENCIL_DECREMENT_SATURATE,
++ gcvSTENCIL_OPERATION_INVALID = -1
++}
++gceSTENCIL_OPERATION;
++
++/* Stencil selection. */
++typedef enum _gceSTENCIL_WHERE
++{
++ gcvSTENCIL_FRONT,
++ gcvSTENCIL_BACK,
++}
++gceSTENCIL_WHERE;
++
++/* Texture addressing selection. */
++typedef enum _gceTEXTURE_WHICH
++{
++ gcvTEXTURE_S,
++ gcvTEXTURE_T,
++ gcvTEXTURE_R,
++}
++gceTEXTURE_WHICH;
++
++/* Texture addressing modes. */
++typedef enum _gceTEXTURE_ADDRESSING
++{
++ gcvTEXTURE_INVALID = 0,
++ gcvTEXTURE_CLAMP,
++ gcvTEXTURE_WRAP,
++ gcvTEXTURE_MIRROR,
++ gcvTEXTURE_BORDER,
++ gcvTEXTURE_MIRROR_ONCE,
++}
++gceTEXTURE_ADDRESSING;
++
++/* Texture filters. */
++typedef enum _gceTEXTURE_FILTER
++{
++ gcvTEXTURE_NONE,
++ gcvTEXTURE_POINT,
++ gcvTEXTURE_LINEAR,
++ gcvTEXTURE_ANISOTROPIC,
++}
++gceTEXTURE_FILTER;
++
++typedef enum _gceTEXTURE_COMPONENT
++{
++ gcvTEXTURE_COMPONENT_R,
++ gcvTEXTURE_COMPONENT_G,
++ gcvTEXTURE_COMPONENT_B,
++ gcvTEXTURE_COMPONENT_A,
++
++ gcvTEXTURE_COMPONENT_NUM,
++} gceTEXTURE_COMPONENT;
++
++/* Texture swizzle modes. */
++typedef enum _gceTEXTURE_SWIZZLE
++{
++ gcvTEXTURE_SWIZZLE_R = 0,
++ gcvTEXTURE_SWIZZLE_G,
++ gcvTEXTURE_SWIZZLE_B,
++ gcvTEXTURE_SWIZZLE_A,
++ gcvTEXTURE_SWIZZLE_0,
++ gcvTEXTURE_SWIZZLE_1,
++
++ gcvTEXTURE_SWIZZLE_INVALID,
++} gceTEXTURE_SWIZZLE;
++
++typedef enum _gceTEXTURE_COMPARE_MODE
++{
++ gcvTEXTURE_COMPARE_MODE_INVALID = 0,
++ gcvTEXTURE_COMPARE_MODE_NONE,
++ gcvTEXTURE_COMPARE_MODE_REF,
++} gceTEXTURE_COMPARE_MODE;
++
++/* Pixel output swizzle modes. */
++typedef enum _gcePIXEL_SWIZZLE
++{
++ gcvPIXEL_SWIZZLE_R = gcvTEXTURE_SWIZZLE_R,
++ gcvPIXEL_SWIZZLE_G = gcvTEXTURE_SWIZZLE_G,
++ gcvPIXEL_SWIZZLE_B = gcvTEXTURE_SWIZZLE_B,
++ gcvPIXEL_SWIZZLE_A = gcvTEXTURE_SWIZZLE_A,
++
++ gcvPIXEL_SWIZZLE_INVALID,
++} gcePIXEL_SWIZZLE;
++
++/* Primitive types. */
++typedef enum _gcePRIMITIVE
++{
++ gcvPRIMITIVE_POINT_LIST,
++ gcvPRIMITIVE_LINE_LIST,
++ gcvPRIMITIVE_LINE_STRIP,
++ gcvPRIMITIVE_LINE_LOOP,
++ gcvPRIMITIVE_TRIANGLE_LIST,
++ gcvPRIMITIVE_TRIANGLE_STRIP,
++ gcvPRIMITIVE_TRIANGLE_FAN,
++ gcvPRIMITIVE_RECTANGLE,
++}
++gcePRIMITIVE;
++
++/* Index types. */
++typedef enum _gceINDEX_TYPE
++{
++ gcvINDEX_8,
++ gcvINDEX_16,
++ gcvINDEX_32,
++}
++gceINDEX_TYPE;
++
++/* Multi GPU rendering modes. */
++typedef enum _gceMULTI_GPU_RENDERING_MODE
++{
++ gcvMULTI_GPU_RENDERING_MODE_OFF,
++ gcvMULTI_GPU_RENDERING_MODE_SPLIT_WIDTH,
++ gcvMULTI_GPU_RENDERING_MODE_SPLIT_HEIGHT,
++ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_64x64,
++ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_128x64,
++ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_128x128
++}
++gceMULTI_GPU_RENDERING_MODE;
++
++typedef enum _gceCORE_3D_MASK
++{
++ gcvCORE_3D_0_MASK = (1 << 0),
++ gcvCORE_3D_1_MASK = (1 << 1),
++
++ gcvCORE_3D_ALL_MASK = (0xFFFF)
++}
++gceCORE_3D_MASK;
++
++typedef enum _gceCORE_3D_ID
++{
++ gcvCORE_3D_0_ID = 0,
++ gcvCORE_3D_1_ID = 1,
++
++ gcvCORE_3D_ID_INVALID = ~0UL
++}
++gceCORE_3D_ID;
++
++typedef enum _gceMULTI_GPU_MODE
++{
++ gcvMULTI_GPU_MODE_COMBINED = 0,
++ gcvMULTI_GPU_MODE_INDEPENDENT = 1
++}
++gceMULTI_GPU_MODE;
++
++typedef enum _gceMACHINECODE
++{
++ gcvMACHINECODE_ANTUTU0 = 0x0,
++
++ gcvMACHINECODE_GLB27_RELEASE_0,
++
++ gcvMACHINECODE_GLB25_RELEASE_0,
++ gcvMACHINECODE_GLB25_RELEASE_1,
++ gcvMACHINECODE_GLB25_RELEASE_2,
++
++ /* keep it as the last enum */
++ gcvMACHINECODE_COUNT
++}
++gceMACHINECODE;
++
++typedef enum _gceUNIFORMCVT
++{
++ gcvUNIFORMCVT_NONE = 0,
++ gcvUNIFORMCVT_TO_BOOL,
++ gcvUNIFORMCVT_TO_FLOAT,
++} gceUNIFORMCVT;
++
++typedef enum _gceHAL_ARG_VERSION
++{
++ gcvHAL_ARG_VERSION_V1 = 0x0,
++}
++gceHAL_ARG_VERSION;
++
++
++/*
++* Bit of a requirment is 1 means requirement is a must, 0 means requirement can
++* be ignored.
++*/
++#define gcvALLOC_FLAG_CONTIGUOUS_BIT 0
++#define gcvALLOC_FLAG_CACHEABLE_BIT 1
++#define gcvALLOC_FLAG_SECURITY_BIT 2
++#define gcvALLOC_FLAG_NON_CONTIGUOUS_BIT 3
++#define gcvALLOC_FLAG_MEMLIMIT_BIT 4
++
++/* No special needs. */
++#define gcvALLOC_FLAG_NONE (0)
++/* Physical contiguous. */
++#define gcvALLOC_FLAG_CONTIGUOUS (1 << gcvALLOC_FLAG_CONTIGUOUS_BIT)
++/* Can be remapped as cacheable. */
++#define gcvALLOC_FLAG_CACHEABLE (1 << gcvALLOC_FLAG_CACHEABLE_BIT)
++/* Secure buffer. */
++#define gcvALLOC_FLAG_SECURITY (1 << gcvALLOC_FLAG_SECURITY_BIT)
++/* Physical non contiguous. */
++#define gcvALLOC_FLAG_NON_CONTIGUOUS (1 << gcvALLOC_FLAG_NON_CONTIGUOUS_BIT)
++#define gcvALLOC_FLAG_MEMLIMIT (1 << gcvALLOC_FLAG_MEMLIMIT_BIT)
++
++/* GL_VIV internal usage */
++#ifndef GL_MAP_BUFFER_OBJ_VIV
++#define GL_MAP_BUFFER_OBJ_VIV 0x10000
++#endif
++
++/* Command buffer usage. */
++#define gcvCOMMAND_2D (1 << 0)
++#define gcvCOMMAND_3D (1 << 1)
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckCONTEXT * gckCONTEXT;
++typedef struct _gcoCMDBUF * gcoCMDBUF;
++
++typedef struct _gcsSTATE_DELTA * gcsSTATE_DELTA_PTR;
++typedef struct _gcsQUEUE * gcsQUEUE_PTR;
++typedef struct _gcoQUEUE * gcoQUEUE;
++typedef struct _gcsHAL_INTERFACE * gcsHAL_INTERFACE_PTR;
++typedef struct _gcs2D_PROFILE * gcs2D_PROFILE_PTR;
++
++#if gcdENABLE_VG
++typedef struct _gcoVGHARDWARE * gcoVGHARDWARE;
++typedef struct _gcoVGBUFFER * gcoVGBUFFER;
++typedef struct _gckVGHARDWARE * gckVGHARDWARE;
++typedef struct _gcsVGCONTEXT * gcsVGCONTEXT_PTR;
++typedef struct _gcsVGCONTEXT_MAP * gcsVGCONTEXT_MAP_PTR;
++typedef struct _gcsVGCMDQUEUE * gcsVGCMDQUEUE_PTR;
++typedef struct _gcsTASK_MASTER_TABLE * gcsTASK_MASTER_TABLE_PTR;
++typedef struct _gckVGKERNEL * gckVGKERNEL;
++typedef void * gctTHREAD;
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_enum_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,2677 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_h_
++#define __gc_hal_h_
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++#include "gc_hal_profiler.h"
++#include "gc_hal_driver.h"
++#if gcdENABLE_3D
++#include "gc_hal_statistics.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* Alignment Macros *******************************
++\******************************************************************************/
++
++/* Alignment with a non-power of two value. */
++#define gcmALIGN_NP2(n, align) \
++( \
++ ((n) + (align) - 1) - (((n) + (align) - 1) % (align)) \
++)
++
++/* Alignment with a power of two value. */
++#define gcmALIGN(n, align) \
++( \
++ ((n) + ((align) - 1)) & ~((align) - 1) \
++)
++
++#define gcmALIGN_BASE(n, align) \
++( \
++ ((n) & ~((align) - 1)) \
++)
++
++/******************************************************************************\
++***************************** Element Count Macro *****************************
++\******************************************************************************/
++
++#define gcmSIZEOF(a) \
++( \
++ (gctSIZE_T) (sizeof(a)) \
++)
++
++#define gcmCOUNTOF(a) \
++( \
++ sizeof(a) / sizeof(a[0]) \
++)
++
++/******************************************************************************\
++********************************* Cast Macro **********************************
++\******************************************************************************/
++#define gcmNAME_TO_PTR(na) \
++ gckKERNEL_QueryPointerFromName(kernel, gcmALL_TO_UINT32(na))
++
++#define gcmPTR_TO_NAME(ptr) \
++ gckKERNEL_AllocateNameFromPointer(kernel, ptr)
++
++#define gcmRELEASE_NAME(na) \
++ gckKERNEL_DeleteName(kernel, gcmALL_TO_UINT32(na))
++
++#define gcmALL_TO_UINT32(t) \
++( \
++ (gctUINT32) (gctUINTPTR_T) (t)\
++)
++
++#define gcmPTR_TO_UINT64(p) \
++( \
++ (gctUINT64) (gctUINTPTR_T) (p)\
++)
++
++#define gcmUINT64_TO_PTR(u) \
++( \
++ (gctPOINTER) (gctUINTPTR_T) (u)\
++)
++
++#define gcmUINT64_TO_TYPE(u, t) \
++( \
++ (t) (gctUINTPTR_T) (u)\
++)
++
++/******************************************************************************\
++******************************** Useful Macro *********************************
++\******************************************************************************/
++
++#define gcvINVALID_ADDRESS ~0U
++
++#define gcmGET_PRE_ROTATION(rotate) \
++ ((rotate) & (~(gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y)))
++
++#define gcmGET_POST_ROTATION(rotate) \
++ ((rotate) & (gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y))
++
++/******************************************************************************\
++******************************** gcsOBJECT Object *******************************
++\******************************************************************************/
++
++/* Type of objects. */
++typedef enum _gceOBJECT_TYPE
++{
++ gcvOBJ_UNKNOWN = 0,
++ gcvOBJ_2D = gcmCC('2','D',' ',' '),
++ gcvOBJ_3D = gcmCC('3','D',' ',' '),
++ gcvOBJ_ATTRIBUTE = gcmCC('A','T','T','R'),
++ gcvOBJ_BRUSHCACHE = gcmCC('B','R','U','$'),
++ gcvOBJ_BRUSHNODE = gcmCC('B','R','U','n'),
++ gcvOBJ_BRUSH = gcmCC('B','R','U','o'),
++ gcvOBJ_BUFFER = gcmCC('B','U','F','R'),
++ gcvOBJ_COMMAND = gcmCC('C','M','D',' '),
++ gcvOBJ_COMMANDBUFFER = gcmCC('C','M','D','B'),
++ gcvOBJ_CONTEXT = gcmCC('C','T','X','T'),
++ gcvOBJ_DEVICE = gcmCC('D','E','V',' '),
++ gcvOBJ_DUMP = gcmCC('D','U','M','P'),
++ gcvOBJ_EVENT = gcmCC('E','V','N','T'),
++ gcvOBJ_FUNCTION = gcmCC('F','U','N','C'),
++ gcvOBJ_HAL = gcmCC('H','A','L',' '),
++ gcvOBJ_HARDWARE = gcmCC('H','A','R','D'),
++ gcvOBJ_HEAP = gcmCC('H','E','A','P'),
++ gcvOBJ_INDEX = gcmCC('I','N','D','X'),
++ gcvOBJ_INTERRUPT = gcmCC('I','N','T','R'),
++ gcvOBJ_KERNEL = gcmCC('K','E','R','N'),
++ gcvOBJ_KERNEL_FUNCTION = gcmCC('K','F','C','N'),
++ gcvOBJ_MEMORYBUFFER = gcmCC('M','E','M','B'),
++ gcvOBJ_MMU = gcmCC('M','M','U',' '),
++ gcvOBJ_OS = gcmCC('O','S',' ',' '),
++ gcvOBJ_OUTPUT = gcmCC('O','U','T','P'),
++ gcvOBJ_PAINT = gcmCC('P','N','T',' '),
++ gcvOBJ_PATH = gcmCC('P','A','T','H'),
++ gcvOBJ_QUEUE = gcmCC('Q','U','E',' '),
++ gcvOBJ_SAMPLER = gcmCC('S','A','M','P'),
++ gcvOBJ_SHADER = gcmCC('S','H','D','R'),
++ gcvOBJ_STREAM = gcmCC('S','T','R','M'),
++ gcvOBJ_SURF = gcmCC('S','U','R','F'),
++ gcvOBJ_TEXTURE = gcmCC('T','X','T','R'),
++ gcvOBJ_UNIFORM = gcmCC('U','N','I','F'),
++ gcvOBJ_VARIABLE = gcmCC('V','A','R','I'),
++ gcvOBJ_VERTEX = gcmCC('V','R','T','X'),
++ gcvOBJ_VIDMEM = gcmCC('V','M','E','M'),
++ gcvOBJ_VG = gcmCC('V','G',' ',' '),
++ gcvOBJ_BUFOBJ = gcmCC('B','U','F','O'),
++ gcvOBJ_UNIFORM_BLOCK = gcmCC('U','B','L','K'),
++ gcvOBJ_CL = gcmCC('C','L',' ',' '),
++}
++gceOBJECT_TYPE;
++
++/* gcsOBJECT object defintinon. */
++typedef struct _gcsOBJECT
++{
++ /* Type of an object. */
++ gceOBJECT_TYPE type;
++}
++gcsOBJECT;
++
++typedef struct _gckHARDWARE * gckHARDWARE;
++
++/* CORE flags. */
++typedef enum _gceCORE
++{
++ gcvCORE_MAJOR = 0x0,
++ gcvCORE_2D = 0x1,
++ gcvCORE_VG = 0x2,
++}
++gceCORE;
++
++#define gcdMAX_GPU_COUNT 3
++
++#define gcdMAX_SURF_LAYER 4
++
++#define gcdMAX_DRAW_BUFFERS 4
++
++/*******************************************************************************
++**
++** gcmVERIFY_OBJECT
++**
++** Assert if an object is invalid or is not of the specified type. If the
++** object is invalid or not of the specified type, gcvSTATUS_INVALID_OBJECT
++** will be returned from the current function. In retail mode this macro
++** does nothing.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define _gcmVERIFY_OBJECT(prefix, obj, t) \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ }
++
++# define gcmVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcm, obj, t)
++# define gcmkVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcmk, obj, t)
++#else
++# define gcmVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++# define gcmkVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************/
++/*VERIFY_OBJECT if special return expected*/
++/******************************************************************************/
++#ifndef EGL_API_ANDROID
++# define _gcmVERIFY_OBJECT_RETURN(prefix, obj, t, retVal) \
++ do \
++ { \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcm, obj, t, retVal)
++# define gcmkVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcmk, obj, t, retVal)
++#else
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************\
++********************************** gckOS Object *********************************
++\******************************************************************************/
++
++/* Construct a new gckOS object. */
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ );
++
++/* Destroy an gckOS object. */
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckOS_QueryVideoMemory(
++ IN gckOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Wrapper for allocation memory.. */
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Wrapper for freeing memory. */
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gctUINT32 * Gid,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Lock pages. */
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address,
++ IN gctPOINTER PageTable
++ );
++
++gceSTATUS
++gckOS_UnmapPages(
++ IN gckOS Os,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address
++ );
++
++/* Unlock pages. */
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Free paged memory. */
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Allocate non-paged memory. */
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non-paged memory. */
++gceSTATUS
++gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Get the number fo bytes per page. */
++gceSTATUS
++gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Get the physical address of a corresponding user logical address. */
++gceSTATUS
++gckOS_UserLogicalToPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ );
++
++/* Map physical memory. */
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap previously mapped physical memory. */
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Get real physical address from descriptor. */
++gceSTATUS
++gckOS_PhysicalToPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Physical,
++ OUT gctUINT32 * PhysicalAddress
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Write data to a 32-bit memory location. */
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ );
++
++/* Map physical memory into the process space. */
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap physical memory from the specified process space. */
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ );
++
++/* Unmap physical memory from the process space. */
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Unmap user logical memory out of physical memory.
++ * This function is only supported in Linux currently.
++ */
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Create a new mutex. */
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Atomically exchange a pair of 32-bit values. */
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ );
++
++/* Atomically exchange a pair of pointers. */
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ );
++
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ );
++
++/* Get time in milliseconds. */
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ );
++
++/* Compare time value. */
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ );
++
++/* Memory barrier. */
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ );
++
++/* Map user pointer. */
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Unmap user pointer. */
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ );
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Perform a memory copy. */
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ );
++
++/* Zero memory. */
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Device I/O control to the kernel HAL layer. */
++gceSTATUS
++gckOS_DeviceControl(
++ IN gckOS Os,
++ IN gctBOOL FromUser,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ OUT gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++gceSTATUS
++gckOS_GetCurrentProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ );
++
++/******************************************************************************\
++********************************** Signal Object *********************************
++\******************************************************************************/
++
++/* Create a signal. */
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a user signal to the kernel space. */
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ );
++
++/* Unmap a user signal */
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Map user memory. */
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/******************************************************************************\
++************************** Android Native Fence Sync ***************************
++\******************************************************************************/
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ );
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ );
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ );
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++/* Create signal to be used in the user space. */
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ );
++
++/* Destroy signal used in the user space. */
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ );
++
++/* Wait for signal used in the user space. */
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ );
++
++/* Signal a signal used in the user space. */
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ );
++
++/* Set a signal owned by a process. */
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ );
++
++/******************************************************************************\
++** Cache Support
++*/
++
++gceSTATUS
++gckOS_CacheClean(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctUINT32 Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheFlush(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctUINT32 Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheInvalidate(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctUINT32 Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CPUPhysicalToGPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 CPUPhysical,
++ IN gctUINT32_PTR GPUPhysical
++ );
++
++gceSTATUS
++gckOS_GPUPhysicalToCPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 GPUPhysical,
++ IN gctUINT32_PTR CPUPhysical
++ );
++
++gceSTATUS
++gckOS_QueryOption(
++ IN gckOS Os,
++ IN gctCONST_STRING Option,
++ OUT gctUINT32 * Value
++ );
++
++/******************************************************************************\
++** Debug Support
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gckOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++/*******************************************************************************
++** Broadcast interface.
++*/
++
++typedef enum _gceBROADCAST
++{
++ /* GPU might be idle. */
++ gcvBROADCAST_GPU_IDLE,
++
++ /* A commit is going to happen. */
++ gcvBROADCAST_GPU_COMMIT,
++
++ /* GPU seems to be stuck. */
++ gcvBROADCAST_GPU_STUCK,
++
++ /* First process gets attached. */
++ gcvBROADCAST_FIRST_PROCESS,
++
++ /* Last process gets detached. */
++ gcvBROADCAST_LAST_PROCESS,
++
++ /* AXI bus error. */
++ gcvBROADCAST_AXI_BUS_ERROR,
++
++ /* Out of memory. */
++ gcvBROADCAST_OUT_OF_MEMORY,
++}
++gceBROADCAST;
++
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ );
++
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ );
++
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ );
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gceCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ );
++
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ );
++
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ );
++
++/*******************************************************************************
++** Semaphores.
++*/
++
++/* Create a new semaphore. */
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++#endif
++
++/* Delete a semahore. */
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Acquire a semahore. */
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Try to acquire a semahore. */
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Release a semahore. */
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/*******************************************************************************
++** Timer API.
++*/
++
++typedef void (*gctTIMERFUNCTION)(gctPOINTER);
++
++/* Create a timer. */
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ );
++
++/* Destory a timer. */
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/* Start a timer. */
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ );
++
++/* Stop a timer. */
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/******************************************************************************\
++********************************* gckHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gckHEAP * gckHEAP;
++
++/* Construct a new gckHEAP object. */
++gceSTATUS
++gckHEAP_Construct(
++ IN gckOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gckHEAP * Heap
++ );
++
++/* Destroy an gckHEAP object. */
++gceSTATUS
++gckHEAP_Destroy(
++ IN gckHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gckHEAP_Allocate(
++ IN gckHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckHEAP_Free(
++ IN gckHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++/* Profile the heap. */
++gceSTATUS
++gckHEAP_ProfileStart(
++ IN gckHEAP Heap
++ );
++
++gceSTATUS
++gckHEAP_ProfileEnd(
++ IN gckHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++
++
++/******************************************************************************\
++******************************** gckVIDMEM Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVIDMEM * gckVIDMEM;
++typedef struct _gckKERNEL * gckKERNEL;
++typedef struct _gckDB * gckDB;
++typedef struct _gckDVFS * gckDVFS;
++
++/* Construct a new gckVIDMEM object. */
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T Banking,
++ OUT gckVIDMEM * Memory
++ );
++
++/* Destroy an gckVDIMEM object. */
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ );
++
++/* Allocate linear memory. */
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctBOOL Specified,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckVIDMEM_Free(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/* Lock memory. */
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address,
++ OUT gctUINT32 * Gid,
++ OUT gctUINT64 * PhysicalAddress
++ );
++
++/* Unlock memory. */
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ );
++
++/* Construct a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Destroy a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/******************************************************************************\
++******************************** gckKERNEL Object ******************************
++\******************************************************************************/
++
++struct _gcsHAL_INTERFACE;
++
++/* Notifications. */
++typedef enum _gceNOTIFY
++{
++ gcvNOTIFY_INTERRUPT,
++ gcvNOTIFY_COMMAND_QUEUE,
++}
++gceNOTIFY;
++
++/* Flush flags. */
++typedef enum _gceKERNEL_FLUSH
++{
++ gcvFLUSH_COLOR = 0x01,
++ gcvFLUSH_DEPTH = 0x02,
++ gcvFLUSH_TEXTURE = 0x04,
++ gcvFLUSH_2D = 0x08,
++ gcvFLUSH_TILE_STATUS = 0x20,
++ gcvFLUSH_ALL = gcvFLUSH_COLOR
++ | gcvFLUSH_DEPTH
++ | gcvFLUSH_TEXTURE
++ | gcvFLUSH_2D
++ | gcvFLUSH_TILE_STATUS
++}
++gceKERNEL_FLUSH;
++
++/* Construct a new gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ );
++
++/* Destroy an gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query Database requirements. */
++gceSTATUS
++ gckKERNEL_QueryDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Lookup the gckVIDMEM object for a pool. */
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 Flag,
++ OUT gctUINT32 * Node
++ );
++
++gceSTATUS
++gckKERNEL_ReleaseVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ );
++
++gceSTATUS
++gckKERNEL_LockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ );
++
++gceSTATUS
++gckKERNEL_UnlockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ );
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ );
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ );
++
++/* Map memory. */
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Notification of events. */
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++ IN gceNOTIFY Notifcation,
++ IN gctBOOL Data
++ );
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ );
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ );
++
++/* Set the value of timeout on HW operation. */
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ );
++
++/* Get access to the user data. */
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Release resources associated with the user data connection. */
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Frequency
++ );
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ );
++
++/******************************************************************************\
++******************************* gckHARDWARE Object *****************************
++\******************************************************************************/
++
++/* Construct a new gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ );
++
++/* Destroy an gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ );
++
++/* Get hardware type. */
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Alignment,
++ OUT gctUINT32 * ReservedHead,
++ OUT gctUINT32 * ReservedTail
++ );
++
++/* Add a WAIT/LINK pair in the command queue. */
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctUINT32 * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctUINT32 * WaitBytes
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Bytes
++ );
++
++/* Add an END command in the command queue. */
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Add a NOP command in the command queue. */
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a PIPESELECT command in the command queue. */
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Add a LINK command in the command queue. */
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT32 FetchSize,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Add an EVENT command in the command queue. */
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ );
++
++/* Query the shader uniforms support. */
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctBOOL * UnifiedUnforms
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Update command queue tail pointer. */
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ );
++
++/* Interrupt manager. */
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL InterruptValid
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ );
++
++/* Set the page table base address. */
++gceSTATUS
++gckHARDWARE_SetMMUv2(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Enable,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctBOOL FromPower
++ );
++
++#if gcdPROCESS_ADDRESS_SPACE
++/* Configure mmu configuration. */
++gceSTATUS
++gckHARDWARE_ConfigMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER MtlbLogical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctSIZE_T * WaitLinkOffset,
++ OUT gctSIZE_T * WaitLinkBytes
++ );
++#endif
++
++/* Get idle register. */
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ );
++
++gceSTATUS
++gckHARDWARE_ReadInterrupt(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckHARDWARE_SetPowerManagementLock(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Lock
++ );
++
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ );
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_SetMinFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT MinFscaleValue
++ );
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++);
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++);
++#endif
++
++/* Profile 2D Engine. */
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OUT gcs2D_PROFILE_PTR Profile
++ );
++
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ );
++
++typedef gceSTATUS (*gctISRMANAGERFUNC)(gctPOINTER Context, gceCORE Core);
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ );
++
++/* Start a composition. */
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ );
++
++/* Check for Hardware features. */
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ );
++
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ );
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Frequency
++ );
++
++gceSTATUS
++gckHARDWARE_PrepareFunctions(
++ gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_SetMMUStates(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++#if !gcdENABLE_VG
++/******************************************************************************\
++***************************** gckINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckINTERRUPT * gckINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckKERNEL Kernel
++ );
++
++gceSTATUS
++gckINTERRUPT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_Destroy(
++ IN gckINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_SetHandler(
++ IN gckINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckINTERRUPT_Notify(
++ IN gckINTERRUPT Interrupt,
++ IN gctBOOL Valid
++ );
++#endif
++/******************************************************************************\
++******************************** gckEVENT Object *******************************
++\******************************************************************************/
++
++typedef struct _gckEVENT * gckEVENT;
++
++/* Construct a new gckEVENT object. */
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ );
++
++/* Destroy an gckEVENT object. */
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ );
++
++/* Add a new event to the list of events. */
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ );
++
++/* Schedule a FreeNonPagedMemory event. */
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeContiguousMemory event. */
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeVideoMemory event. */
++gceSTATUS
++gckEVENT_FreeVideoMemory(
++ IN gckEVENT Event,
++ IN gcuVIDMEM_NODE_PTR VideoMemory,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a signal event. */
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule an Unlock event. */
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctPOINTER Node,
++ IN gceSURF_TYPE Type
++ );
++
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeVirtualCommandBuffer event. */
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower,
++ IN gctBOOL FromCommand
++ );
++
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ );
++
++/* Schedule a composition event. */
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ );
++
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ );
++/******************************************************************************\
++******************************* gckCOMMAND Object ******************************
++\******************************************************************************/
++
++typedef struct _gckCOMMAND * gckCOMMAND;
++
++/* Construct a new gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ );
++
++/* Destroy an gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ );
++
++/* Acquire command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Release command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Start the command queue. */
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ );
++
++/* Stop the command queue. */
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ );
++
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ );
++
++/* Reserve space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctUINT32 * BufferSize
++ );
++
++/* Execute reserved space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequstedBytes
++ );
++
++/* Stall the command queue. */
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Attach user process. */
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ );
++
++/* Detach user process. */
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ );
++
++/* Dump command buffer being executed by GPU. */
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ );
++
++/* Whether a kernel command buffer address. */
++gceSTATUS
++gckCOMMAND_AddressInKernelCommandBuffer(
++ IN gckCOMMAND Command,
++ IN gctUINT32 Address,
++ OUT gctBOOL *In
++ );
++
++/******************************************************************************\
++********************************* gckMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckMMU * gckMMU;
++
++/* Construct a new gckMMU object. */
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ );
++
++/* Destroy an gckMMU object. */
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++gceSTATUS
++gckMMU_AllocatePagesEx(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu,
++ IN gceSURF_TYPE Type
++ );
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ );
++
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ );
++#endif
++
++#if VIVANTE_PROFILER_NEW
++gceSTATUS
++gckHARDWARE_InitProfiler(
++ IN gckHARDWARE Hardware
++ );
++#endif
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ );
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckOS_DetectProcessByName(
++ IN gctCONST_POINTER Name
++ );
++
++void
++gckOS_DumpParam(
++ void
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#if gcdENABLE_VG
++#include "gc_hal_vg.h"
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,218 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_buffer_h_
++#define __gc_hal_kernel_buffer_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++************************ Command Buffer and Event Objects **********************
++\******************************************************************************/
++
++/* The number of context buffers per user. */
++#define gcdCONTEXT_BUFFER_COUNT 2
++
++/* State delta record. */
++typedef struct _gcsSTATE_DELTA_RECORD * gcsSTATE_DELTA_RECORD_PTR;
++typedef struct _gcsSTATE_DELTA_RECORD
++{
++ /* State address. */
++ gctUINT address;
++
++ /* State mask. */
++ gctUINT32 mask;
++
++ /* State data. */
++ gctUINT32 data;
++}
++gcsSTATE_DELTA_RECORD;
++
++/* State delta. */
++typedef struct _gcsSTATE_DELTA
++{
++ /* For debugging: the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Main state delta ID. Every time state delta structure gets reinitialized,
++ main ID is incremented. If main state ID overflows, all map entry IDs get
++ reinitialized to make sure there is no potential erroneous match after
++ the overflow.*/
++ gctUINT id;
++
++ /* The number of contexts pending modification by the delta. */
++ gctINT refCount;
++
++ /* Vertex element count for the delta buffer. */
++ gctUINT elementCount;
++
++ /* Number of states currently stored in the record array. */
++ gctUINT recordCount;
++
++ /* Record array; holds all modified states in gcsSTATE_DELTA_RECORD. */
++ gctUINT64 recordArray;
++
++ /* Map entry ID is used for map entry validation. If map entry ID does not
++ match the main state delta ID, the entry and the corresponding state are
++ considered not in use. */
++ gctUINT64 mapEntryID;
++ gctUINT mapEntryIDSize;
++
++ /* If the map entry ID matches the main state delta ID, index points to
++ the state record in the record array. */
++ gctUINT64 mapEntryIndex;
++
++ /* Previous and next state deltas in gcsSTATE_DELTA. */
++ gctUINT64 prev;
++ gctUINT64 next;
++}
++gcsSTATE_DELTA;
++
++/* Command buffer patch record. */
++struct _gcsPATCH
++{
++ /* Pointer within the buffer. */
++ gctUINT32_PTR pointer;
++
++ /* 32-bit data to write at the specified offset. */
++ gctUINT32 data;
++};
++
++/* List of patches for the command buffer. */
++struct _gcsPATCH_LIST
++{
++ /* Array of patch records. */
++ struct _gcsPATCH patch[1024];
++
++ /* Number of patches in the array. */
++ gctUINT count;
++
++ /* Next item in the list. */
++ struct _gcsPATCH_LIST *next;
++};
++
++/* Command buffer object. */
++struct _gcoCMDBUF
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Commit count. */
++ gctUINT count;
++
++ /* Command buffer entry and exit pipes. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Feature usage flags. */
++ gctBOOL using2D;
++ gctBOOL using3D;
++ gctBOOL usingFilterBlit;
++ gctBOOL usingPalette;
++
++ /* Physical address of command buffer. Just a name. */
++ gctUINT32 physical;
++
++ /* Logical address of command buffer. */
++ gctUINT64 logical;
++
++ /* Number of bytes in command buffer. */
++ gctUINT32 bytes;
++
++ /* Start offset into the command buffer. */
++ gctUINT32 startOffset;
++
++ /* Current offset into the command buffer. */
++ gctUINT32 offset;
++
++ /* Number of free bytes in command buffer. */
++ gctUINT32 free;
++
++ /* Location of the last reserved area. */
++ gctUINT64 lastReserve;
++ gctUINT32 lastOffset;
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Last load state command location and hardware address. */
++ gctUINT64 lastLoadStatePtr;
++ gctUINT32 lastLoadStateAddress;
++ gctUINT32 lastLoadStateCount;
++#endif
++
++ /* Completion signal. */
++ gctSIGNAL signal;
++
++ /* List of patches. */
++ struct _gcsPATCH_LIST *patchHead;
++ struct _gcsPATCH_LIST *patchTail;
++
++ /* Link to the siblings. */
++ gcoCMDBUF prev;
++ gcoCMDBUF next;
++};
++
++typedef struct _gcsQUEUE
++{
++ /* Pointer to next gcsQUEUE structure in gcsQUEUE. */
++ gctUINT64 next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE iface;
++}
++gcsQUEUE;
++
++/* Event queue. */
++struct _gcoQUEUE
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to current event queue. */
++ gcsQUEUE_PTR head;
++ gcsQUEUE_PTR tail;
++
++ /* chunks of the records. */
++ gctPOINTER chunks;
++
++ /* List of free records. */
++ gcsQUEUE_PTR freeList;
++
++ #define gcdIN_QUEUE_RECORD_LIMIT 16
++ /* Number of records currently in queue */
++ gctUINT32 recordCount;
++};
++
++struct _gcsTEMPCMDBUF
++{
++ gctUINT32 currentByteSize;
++ gctPOINTER buffer;
++ gctBOOL inUse;
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_buffer_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_mem.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_mem.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_mem.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,530 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/*
++** Include file for the local memory management.
++*/
++
++#ifndef __gc_hal_mem_h_
++#define __gc_hal_mem_h_
++#if (gcdENABLE_3D || gcdENABLE_VG)
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Usage:
++
++ The macros to declare MemPool type and functions are
++ gcmMEM_DeclareFSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareVSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix)
++
++ The data structures for MemPool are
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++
++ The MemPool constructor and destructor functions are
++ gcfMEM_InitFSMemPool(gcsMEM_FS_MEM_POOL *, gcoOS, gctUINT, gctUINT);
++ gcfMEM_FreeFSMemPool(gcsMEM_FS_MEM_POOL *);
++ gcfMEM_InitVSMemPool(gcsMEM_VS_MEM_POOL *, gcoOS, gctUINT, gctBOOL);
++ gcfMEM_FreeVSMemPool(gcsMEM_VS_MEM_POOL *);
++ gcfMEM_InitAFSMemPool(gcsMEM_AFS_MEM_POOL *, gcoOS, gctUINT);
++ gcfMEM_FreeAFSMemPool(gcsMEM_AFS_MEM_POOL *);
++
++ FS: for Fixed-Size data structures
++ VS: for Variable-size data structures
++ AFS: for Array of Fixed-Size data structures
++
++
++ // Example 1: For a fixed-size data structure, struct gcsNode.
++ // It is used locally in a file, so the functions are static without prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type.
++ // The second armument is the short name used in the fuctions.
++ gcmMEM_DeclareFSMemPool(struct gcsNode, Node, );
++
++ // The previous macro creates two inline functions,
++ // _AllocateNode and _FreeNode.
++
++ // In function or struct
++ gcsMEM_FS_MEM_POOL nodeMemPool;
++
++ // In function,
++ struct gcsNode * node;
++ gceSTATUS status;
++
++ // Before using the memory pool, initialize it.
++ // The second argument is the gcoOS object.
++ // The third argument is the number of data structures to allocate for each chunk.
++ status = gcfMEM_InitFSMemPool(&nodeMemPool, os, 100, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node.
++ status = _AllocateNode(nodeMemPool, &node);
++ ...
++ // Free a node.
++ _FreeNode(nodeMemPool, node);
++
++ // After using the memory pool, free it.
++ gcfMEM_FreeFSMemPool(&nodeMemPool);
++
++
++ // Example 2: For array of fixed-size data structures, struct gcsNode.
++ // It is used in several files, so the functions are extern with prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type, and the second one is the short name
++ // used in the fuctions.
++ gcmMEM_DeclareAFSMemPool(struct gcsNode, NodeArray, gcfOpt);
++
++ // The previous macro creates two inline functions,
++ // gcfOpt_AllocateNodeArray and gcfOpt_FreeNodeArray.
++
++ // In function or struct
++ gcsMEM_AFS_MEM_POOL nodeArrayMemPool;
++
++ // In function,
++ struct gcsNode * nodeArray;
++ gceSTATUS status;
++
++ // Before using the array memory pool, initialize it.
++ // The second argument is the gcoOS object, the third is the number of data
++ // structures to allocate for each chunk.
++ status = gcfMEM_InitAFSMemPool(&nodeArrayMemPool, os, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node array of size 100.
++ status = gcfOpt_AllocateNodeArray(nodeArrayMemPool, &nodeArray, 100);
++ ...
++ // Free a node array.
++ gcfOpt_FreeNodeArray(&nodeArrayMemPool, nodeArray);
++
++ // After using the array memory pool, free it.
++ gcfMEM_FreeAFSMemPool(&nodeArrayMemPool);
++
++*******************************************************************************/
++
++/*******************************************************************************
++** To switch back to use gcoOS_Allocate and gcoOS_Free, add
++** #define USE_LOCAL_MEMORY_POOL 0
++** before including this file.
++*******************************************************************************/
++#ifndef USE_LOCAL_MEMORY_POOL
++/*
++ USE_LOCAL_MEMORY_POOL
++
++ This define enables the local memory management to improve performance.
++*/
++#define USE_LOCAL_MEMORY_POOL 1
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Structures
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++#else
++ typedef gcoOS gcsMEM_FS_MEM_POOL;
++ typedef gcoOS gcsMEM_VS_MEM_POOL;
++ typedef gcoOS gcsMEM_AFS_MEM_POOL;
++#endif
++
++/*******************************************************************************
++** Memory Pool Macros
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ return(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_FSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName##List( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * FirstPointer, \
++ Type * LastPointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x FirstPointer=0x%x LastPointer=0x%x", MemPool, FirstPointer, LastPointer); \
++ status = gcfMEM_FSMemPoolFreeAList(MemPool, (gctPOINTER) FirstPointer, (gctPOINTER) LastPointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status;\
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++ Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pinter); \
++ status = gcfMEM_VSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_AFSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#else
++
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Functions
++*******************************************************************************/
++gceSTATUS
++gcfMEM_InitFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolGetANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeAList(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER FirstNode,
++ IN gctPOINTER LastNode
++ );
++
++gceSTATUS
++gcfMEM_InitVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT BlockSize,
++ IN gctBOOL RecycleFreeNode
++ );
++
++gceSTATUS
++gcfMEM_FreeVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolGetANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolFreeANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_InitAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolGetANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctUINT Count,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolFreeANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* (gcdENABLE_3D || gcdENABLE_VG) */
++#endif /* __gc_hal_mem_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_options.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_options.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_options.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_options.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,1194 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_options_h_
++#define __gc_hal_options_h_
++
++/*
++ gcdPRINT_VERSION
++
++ Print HAL version.
++*/
++#ifndef gcdPRINT_VERSION
++# define gcdPRINT_VERSION 0
++#endif
++
++/*
++ VIVANTE_PROFILER
++
++ This define enables the profiler.
++*/
++#ifndef VIVANTE_PROFILER
++# define VIVANTE_PROFILER 1
++#endif
++
++/*
++ VIVANTE_PROFILER_CONTEXT
++
++ This define enables the profiler according each context.
++*/
++#ifndef VIVANTE_PROFILER_CONTEXT
++# define VIVANTE_PROFILER_CONTEXT 1
++#endif
++
++#ifndef VIVANTE_PROFILER_PERDRAW
++# define VIVANTE_PROFILER_PERDRAW 0
++#endif
++
++#ifndef VIVANTE_PROFILER_NEW
++# define VIVANTE_PROFILER_NEW 0
++#endif
++
++#ifndef VIVANTE_PROFILER_PM
++# define VIVANTE_PROFILER_PM 1
++#endif
++/*
++ gcdUSE_VG
++
++ Enable VG HAL layer (only for GC350).
++*/
++#ifndef gcdUSE_VG
++# define gcdUSE_VG 0
++#endif
++
++/*
++ USE_SW_FB
++
++ Set to 1 if the frame buffer memory cannot be accessed by the GPU.
++*/
++#ifndef USE_SW_FB
++# define USE_SW_FB 0
++#endif
++
++/*
++ PROFILE_HAL_COUNTERS
++
++ This define enables HAL counter profiling support. HW and SHADER
++ counter profiling depends on this.
++*/
++#ifndef PROFILE_HAL_COUNTERS
++# define PROFILE_HAL_COUNTERS 1
++#endif
++
++/*
++ PROFILE_HW_COUNTERS
++
++ This define enables HW counter profiling support.
++*/
++#ifndef PROFILE_HW_COUNTERS
++# define PROFILE_HW_COUNTERS 1
++#endif
++
++/*
++ PROFILE_SHADER_COUNTERS
++
++ This define enables SHADER counter profiling support.
++*/
++#ifndef PROFILE_SHADER_COUNTERS
++# define PROFILE_SHADER_COUNTERS 1
++#endif
++
++/*
++ gcdDUMP_KEY
++
++ Set this to a string that appears in 'cat /proc/<pid>/cmdline'. E.g. 'camera'.
++ HAL will create dumps for the processes matching this key.
++*/
++#ifndef gcdDUMP_KEY
++# define gcdDUMP_KEY "process"
++#endif
++
++/*
++ gcdDUMP_PATH
++
++ The dump file location. Some processes cannot write to the sdcard.
++ Try apps' data dir, e.g. /data/data/com.android.launcher
++*/
++#ifndef gcdDUMP_PATH
++#if defined(ANDROID)
++# define gcdDUMP_PATH "/mnt/sdcard/"
++#else
++# define gcdDUMP_PATH "./"
++#endif
++#endif
++
++/*
++ gcdDUMP
++
++ When set to 1, a dump of all states and memory uploads, as well as other
++ hardware related execution will be printed to the debug console. This
++ data can be used for playing back applications.
++*/
++#ifndef gcdDUMP
++# define gcdDUMP 0
++#endif
++
++/*
++ gcdDUMP_API
++
++ When set to 1, a high level dump of the EGL and GL/VG APs's are
++ captured.
++*/
++#ifndef gcdDUMP_API
++# define gcdDUMP_API 0
++#endif
++
++
++
++/*
++ gcdDEBUG_OPTION
++ When set to 1, the debug options are enabled. We must set other MACRO to enable
++ sub case.
++*/
++#ifndef gcdDEBUG_OPTION
++# define gcdDEBUG_OPTION 0
++
++#if gcdDEBUG_OPTION
++/*
++ gcdDEBUG_OPTION_KEY
++ The process name of debug application.
++*/
++#ifndef gcdDEBUG_OPTION_KEY
++# define gcdDEBUG_OPTION_KEY "process"
++# endif
++/*
++ gcdDEBUG_OPTION_NO_GL_DRAWS
++ When set to 1, all glDrawArrays and glDrawElements will be skip.
++*/
++#ifndef gcdDEBUG_OPTION_NO_GL_DRAWS
++# define gcdDEBUG_OPTION_NO_GL_DRAWS 0
++# endif
++/*
++ gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES
++ When set to 1, all DrawPrimitives will be skip.
++*/
++#ifndef gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES
++# define gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES 0
++# endif
++/*
++ gcdDEBUG_OPTION_SKIP_SWAP
++ When set to 1, just one out of gcdDEBUG_OPTION_SKIP_FRAMES(such as 1/10) eglSwapBuffers will be resolve,
++ others skip.
++*/
++#ifndef gcdDEBUG_OPTION_SKIP_SWAP
++# define gcdDEBUG_OPTION_SKIP_SWAP 0
++# define gcdDEBUG_OPTION_SKIP_FRAMES 10
++# endif
++/*
++ gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET
++ When set to 1, the format of render target will force to RGB565.
++*/
++#ifndef gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET
++# define gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET 0
++# endif
++/*
++ gcdDEBUG_OPTION_NONE_TEXTURE
++ When set to 1, the type of texture will be set to AQ_TEXTURE_SAMPLE_MODE_TYPE_NONE.
++*/
++#ifndef gcdDEBUG_OPTION_NONE_TEXTURE
++# define gcdDEBUG_OPTION_NONE_TEXTURE 0
++# endif
++/*
++ gcdDEBUG_OPTION_NONE_DEPTH
++ When set to 1, the depth format of surface will be set to gcvSURF_UNKNOWN.
++*/
++#ifndef gcdDEBUG_OPTION_NONE_DEPTH
++# define gcdDEBUG_OPTION_NONE_DEPTH 0
++# endif
++
++# endif
++#endif
++
++/*
++ gcdDUMP_SWAP_PER_DRAW
++
++ When set to 1, dump swap command for every single draw to make simulation comparison happy.
++ Only valid for ES3 driver for now.
++*/
++#ifndef gcdDUMP_SWAP_PER_DRAW
++# define gcdDUMP_SWAP_PER_DRAW 0
++#endif
++
++/*
++ gcdDUMP_FRAMERATE
++ When set to a value other than zero, averaqe frame rate will be dumped.
++ The value set is the starting frame that the average will be calculated.
++ This is needed because sometimes first few frames are too slow to be included
++ in the average. Frame count starts from 1.
++*/
++#ifndef gcdDUMP_FRAMERATE
++# define gcdDUMP_FRAMERATE 0
++#endif
++
++/*
++ gcdENABLE_FSCALE_VAL_ADJUST
++ When non-zero, FSCALE_VAL when gcvPOWER_ON can be adjusted externally.
++ */
++#ifndef gcdENABLE_FSCALE_VAL_ADJUST
++# define gcdENABLE_FSCALE_VAL_ADJUST 1
++#endif
++
++/*
++ gcdDUMP_IN_KERNEL
++
++ When set to 1, all dumps will happen in the kernel. This is handy if
++ you want the kernel to dump its command buffers as well and the data
++ needs to be in sync.
++*/
++#ifndef gcdDUMP_IN_KERNEL
++# define gcdDUMP_IN_KERNEL 0
++#endif
++
++/*
++ gcdDUMP_COMMAND
++
++ When set to non-zero, the command queue will dump all incoming command
++ and context buffers as well as all other modifications to the command
++ queue.
++*/
++#ifndef gcdDUMP_COMMAND
++# define gcdDUMP_COMMAND 0
++#endif
++
++/*
++ gcdDUMP_2D
++
++ When set to non-zero, it will dump the 2D command and surface.
++*/
++#ifndef gcdDUMP_2D
++# define gcdDUMP_2D 0
++#endif
++
++/*
++ gcdDUMP_FRAME_TGA
++
++ When set to a value other than 0, a dump of the frame specified by the value,
++ will be done into frame.tga. Frame count starts from 1.
++ */
++#ifndef gcdDUMP_FRAME_TGA
++# define gcdDUMP_FRAME_TGA 0
++#endif
++/*
++ gcdNULL_DRIVER
++
++ Set to 1 for infinite speed hardware.
++ Set to 2 for bypassing the HAL.
++ Set to 3 for bypassing the drivers.
++*/
++#ifndef gcdNULL_DRIVER
++# define gcdNULL_DRIVER 0
++#endif
++
++/*
++ gcdENABLE_TIMEOUT_DETECTION
++
++ Enable timeout detection.
++*/
++#ifndef gcdENABLE_TIMEOUT_DETECTION
++# define gcdENABLE_TIMEOUT_DETECTION 0
++#endif
++
++/*
++ gcdCMD_BUFFER_SIZE
++
++ Number of bytes in a command buffer.
++*/
++#ifndef gcdCMD_BUFFER_SIZE
++# define gcdCMD_BUFFER_SIZE (128 << 10)
++#endif
++
++/*
++ gcdCMD_BUFFERS
++
++ Number of command buffers to use per client.
++*/
++#ifndef gcdCMD_BUFFERS
++# define gcdCMD_BUFFERS 2
++#endif
++
++/*
++ gcdMAX_CMD_BUFFERS
++
++ Maximum number of command buffers to use per client.
++*/
++#ifndef gcdMAX_CMD_BUFFERS
++# define gcdMAX_CMD_BUFFERS 8
++#endif
++
++/*
++ gcdCOMMAND_QUEUES
++
++ Number of command queues in the kernel.
++*/
++#ifndef gcdCOMMAND_QUEUES
++# define gcdCOMMAND_QUEUES 2
++#endif
++
++/*
++ gcdPOWER_CONTROL_DELAY
++
++ The delay in milliseconds required to wait until the GPU has woke up
++ from a suspend or power-down state. This is system dependent because
++ the bus clock also needs to stabalize.
++*/
++#ifndef gcdPOWER_CONTROL_DELAY
++# define gcdPOWER_CONTROL_DELAY 0
++#endif
++
++/*
++ gcdMIRROR_PAGETABLE
++
++ Enable it when GPUs with old MMU and new MMU exist at same SoC. It makes
++ each GPU use same virtual address to access same physical memory.
++*/
++#ifndef gcdMIRROR_PAGETABLE
++# define gcdMIRROR_PAGETABLE 0
++#endif
++
++/*
++ gcdMMU_SIZE
++
++ Size of the MMU page table in bytes. Each 4 bytes can hold 4kB worth of
++ virtual data.
++*/
++#ifndef gcdMMU_SIZE
++#if gcdMIRROR_PAGETABLE
++# define gcdMMU_SIZE 0x200000
++#else
++# define gcdMMU_SIZE (2048 << 10)
++#endif
++#endif
++
++/*
++ gcdSECURE_CACHE_SLOTS
++
++ Number of slots in the logical to DMA address cache table. Each time a
++ logical address needs to be translated into a DMA address for the GPU,
++ this cache will be walked. The replacement scheme is LRU.
++*/
++#ifndef gcdSECURE_CACHE_SLOTS
++# define gcdSECURE_CACHE_SLOTS 1024
++#endif
++
++/*
++ gcdSECURE_CACHE_METHOD
++
++ Replacement scheme used for Secure Cache. The following options are
++ available:
++
++ gcdSECURE_CACHE_LRU
++ A standard LRU cache.
++
++ gcdSECURE_CACHE_LINEAR
++ A linear walker with the idea that an application will always
++ render the scene in a similar way, so the next entry in the
++ cache should be a hit most of the time.
++
++ gcdSECURE_CACHE_HASH
++ A 256-entry hash table.
++
++ gcdSECURE_CACHE_TABLE
++ A simple cache but with potential of a lot of cache replacement.
++*/
++#ifndef gcdSECURE_CACHE_METHOD
++# define gcdSECURE_CACHE_METHOD gcdSECURE_CACHE_HASH
++#endif
++
++/*
++ gcdREGISTER_ACCESS_FROM_USER
++
++ Set to 1 to allow IOCTL calls to get through from user land. This
++ should only be in debug or development drops.
++*/
++#ifndef gcdREGISTER_ACCESS_FROM_USER
++# define gcdREGISTER_ACCESS_FROM_USER 1
++#endif
++
++/*
++ gcdHEAP_SIZE
++
++ Set the allocation size for the internal heaps. Each time a heap is
++ full, a new heap will be allocated with this minmimum amount of bytes.
++ The bigger this size, the fewer heaps there are to allocate, the better
++ the performance. However, heaps won't be freed until they are
++ completely free, so there might be some more memory waste if the size is
++ too big.
++*/
++#ifndef gcdHEAP_SIZE
++# define gcdHEAP_SIZE (64 << 10)
++#endif
++
++/*
++ gcdPOWER_SUSPEND_WHEN_IDLE
++
++ Set to 1 to make GPU enter gcvPOWER_SUSPEND when idle detected,
++ otherwise GPU will enter gcvPOWER_IDLE.
++*/
++#ifndef gcdPOWER_SUSPEND_WHEN_IDLE
++# define gcdPOWER_SUSPEND_WHEN_IDLE 0
++#endif
++
++#ifndef gcdFPGA_BUILD
++# define gcdFPGA_BUILD 0
++#endif
++
++/*
++ gcdGPU_TIMEOUT
++
++ This define specified the number of milliseconds the system will wait
++ before it broadcasts the GPU is stuck. In other words, it will define
++ the timeout of any operation that needs to wait for the GPU.
++
++ If the value is 0, no timeout will be checked for.
++*/
++#ifndef gcdGPU_TIMEOUT
++#if gcdFPGA_BUILD
++# define gcdGPU_TIMEOUT 0
++# define gcdGPU_2D_TIMEOUT 0
++# else
++# define gcdGPU_TIMEOUT 20000
++# define gcdGPU_2D_TIMEOUT 4000
++# endif
++#endif
++
++/*
++ gcdGPU_ADVANCETIMER
++
++ it is advance timer.
++*/
++#ifndef gcdGPU_ADVANCETIMER
++# define gcdGPU_ADVANCETIMER 250
++#endif
++
++/*
++ gcdSTATIC_LINK
++
++ This define disalbes static linking;
++*/
++#ifndef gcdSTATIC_LINK
++# define gcdSTATIC_LINK 0
++#endif
++
++/*
++ gcdUSE_NEW_HEAP
++
++ Setting this define to 1 enables new heap.
++*/
++#ifndef gcdUSE_NEW_HEAP
++# define gcdUSE_NEW_HEAP 0
++#endif
++
++/*
++ gcdCMD_NO_2D_CONTEXT
++
++ This define enables no-context 2D command buffer.
++*/
++#ifndef gcdCMD_NO_2D_CONTEXT
++# define gcdCMD_NO_2D_CONTEXT 1
++#endif
++
++/*
++ gcdENABLE_BUFFER_ALIGNMENT
++
++ When enabled, video memory is allocated with atleast 16KB aligment
++ between multiple sub-buffers.
++*/
++#ifndef gcdENABLE_BUFFER_ALIGNMENT
++# define gcdENABLE_BUFFER_ALIGNMENT 1
++#endif
++
++/*
++ gcdENABLE_BANK_ALIGNMENT
++
++ When enabled, video memory is allocated bank aligned. The vendor can modify
++ _GetSurfaceBankAlignment() and _GetBankOffsetBytes() to define how
++ different types of allocations are bank and channel aligned.
++ When disabled (default), no bank alignment is done.
++*/
++#ifndef gcdENABLE_BANK_ALIGNMENT
++# define gcdENABLE_BANK_ALIGNMENT 0
++#endif
++
++/*
++ gcdBANK_BIT_START
++
++ Specifies the start bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_START
++# define gcdBANK_BIT_START 12
++#endif
++
++/*
++ gcdBANK_BIT_END
++
++ Specifies the end bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_END
++# define gcdBANK_BIT_END 14
++#endif
++
++/*
++ gcdBANK_CHANNEL_BIT
++
++ When set, video memory when allocated bank aligned is allocated such that
++ render and depth buffer addresses alternate on the channel bit specified.
++ This option has an effect only when gcdENABLE_BANK_ALIGNMENT is enabled.
++ When disabled (default), no alteration is done.
++*/
++#ifndef gcdBANK_CHANNEL_BIT
++# define gcdBANK_CHANNEL_BIT 7
++#endif
++
++/*
++ gcdDYNAMIC_SPEED
++
++ When non-zero, it informs the kernel driver to use the speed throttling
++ broadcasting functions to inform the system the GPU should be spet up or
++ slowed down. It will send a broadcast for slowdown each "interval"
++ specified by this define in milliseconds
++ (gckOS_BroadcastCalibrateSpeed).
++*/
++#ifndef gcdDYNAMIC_SPEED
++# define gcdDYNAMIC_SPEED 2000
++#endif
++
++/*
++ gcdDYNAMIC_EVENT_THRESHOLD
++
++ When non-zero, it specifies the maximum number of available events at
++ which the kernel driver will issue a broadcast to speed up the GPU
++ (gckOS_BroadcastHurry).
++*/
++#ifndef gcdDYNAMIC_EVENT_THRESHOLD
++# define gcdDYNAMIC_EVENT_THRESHOLD 5
++#endif
++
++/*
++ gcdENABLE_PROFILING
++
++ Enable profiling macros.
++*/
++#ifndef gcdENABLE_PROFILING
++# define gcdENABLE_PROFILING 0
++#endif
++
++/*
++ gcdENABLE_128B_MERGE
++
++ Enable 128B merge for the BUS control.
++*/
++#ifndef gcdENABLE_128B_MERGE
++# define gcdENABLE_128B_MERGE 0
++#endif
++
++/*
++ gcdFRAME_DB
++
++ When non-zero, it specified the number of frames inside the frame
++ database. The frame DB will collect per-frame timestamps and hardware
++ counters.
++*/
++#ifndef gcdFRAME_DB
++# define gcdFRAME_DB 0
++# define gcdFRAME_DB_RESET 0
++# define gcdFRAME_DB_NAME "/var/log/frameDB.log"
++#endif
++
++/*
++ gcdDISABLE_CORES_2D3D
++ disable the 2D3D cores for 2D openVG
++*/
++#ifndef gcdDISABLE_CORES_2D3D
++# define gcdDISABLE_CORES_2D3D 0
++#endif
++
++/*
++ gcdPAGED_MEMORY_CACHEABLE
++
++ When non-zero, paged memory will be cacheable.
++
++ Normally, driver will detemines whether a video memory
++ is cacheable or not. When cacheable is not neccessary,
++ it will be writecombine.
++
++ This option is only for those SOC which can't enable
++ writecombine without enabling cacheable.
++*/
++#ifndef gcdPAGED_MEMORY_CACHEABLE
++# define gcdPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_CACHEABLE
++
++ When non-zero, non paged memory will be cacheable.
++*/
++#ifndef gcdNONPAGED_MEMORY_CACHEABLE
++# define gcdNONPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_BUFFERABLE
++
++ When non-zero, non paged memory will be bufferable.
++ gcdNONPAGED_MEMORY_BUFFERABLE and gcdNONPAGED_MEMORY_CACHEABLE
++ can't be set 1 at same time
++*/
++#ifndef gcdNONPAGED_MEMORY_BUFFERABLE
++# define gcdNONPAGED_MEMORY_BUFFERABLE 1
++#endif
++
++/*
++ gcdENABLE_INFINITE_SPEED_HW
++ enable the Infinte HW , this is for 2D openVG
++*/
++#ifndef gcdENABLE_INFINITE_SPEED_HW
++# define gcdENABLE_INFINITE_SPEED_HW 0
++#endif
++
++/*
++ gcdPOWEROFF_TIMEOUT
++
++ When non-zero, GPU will power off automatically from
++ idle state, and gcdPOWEROFF_TIMEOUT is also the default
++ timeout in milliseconds.
++ */
++#ifndef gcdPOWEROFF_TIMEOUT
++# define gcdPOWEROFF_TIMEOUT 300
++#endif
++
++/*
++ gcdRENDER_THREADS
++
++ Number of render threads. Make it zero, and there will be no render
++ threads.
++*/
++#ifndef gcdRENDER_THREADS
++# define gcdRENDER_THREADS 0
++#endif
++
++/*
++ gcdSMP
++
++ This define enables SMP support.
++
++ Currently, it only works on Linux/Android,
++ Kbuild will config it according to whether
++ CONFIG_SMP is set.
++
++*/
++#ifndef gcdSMP
++# define gcdSMP 0
++#endif
++
++/*
++ gcdSHARED_RESOLVE_BUFFER_ENABLED
++
++ Use shared resolve buffer for all app buffers.
++*/
++#ifndef gcdSHARED_RESOLVE_BUFFER_ENABLED
++# define gcdSHARED_RESOLVE_BUFFER_ENABLED 0
++#endif
++
++/*
++ gcdUSE_TRIANGLE_STRIP_PATCH
++ */
++#ifndef gcdUSE_TRIANGLE_STRIP_PATCH
++# define gcdUSE_TRIANGLE_STRIP_PATCH 1
++#endif
++
++/*
++ gcdPROCESS_ADDRESS_SPACE
++
++ When non-zero, every process which attaches to galcore has its own GPU
++ address space, size of which is gcdPROCESS_ADDRESS_SPACE_SIZE.
++*/
++#ifndef gcdPROCESS_ADDRESS_SPACE
++# define gcdPROCESS_ADDRESS_SPACE 0
++# define gcdPROCESS_ADDRESS_SPACE_SIZE 0x80000000
++#endif
++
++/*
++ gcdSHARED_PAGETABLE
++
++ When non-zero, multiple GPUs in one chip with same MMU use
++ one shared pagetable. So that when accessing same surface,
++ they can use same GPU virtual address.
++*/
++#ifndef gcdSHARED_PAGETABLE
++# define gcdSHARED_PAGETABLE !gcdPROCESS_ADDRESS_SPACE
++#endif
++
++#ifndef gcdUSE_PVR
++# define gcdUSE_PVR 1
++#endif
++
++/*
++ gcdSMALL_BLOCK_SIZE
++
++ When non-zero, a part of VIDMEM will be reserved for requests
++ whose requesting size is less than gcdSMALL_BLOCK_SIZE.
++
++ For Linux, it's the size of a page. If this requeset fallbacks
++ to gcvPOOL_CONTIGUOUS or gcvPOOL_VIRTUAL, memory will be wasted
++ because they allocate a page at least.
++*/
++#ifndef gcdSMALL_BLOCK_SIZE
++# define gcdSMALL_BLOCK_SIZE 4096
++# define gcdRATIO_FOR_SMALL_MEMORY 32
++#endif
++
++/*
++ gcdCONTIGUOUS_SIZE_LIMIT
++ When non-zero, size of video node from gcvPOOL_CONTIGUOUS is
++ limited by gcdCONTIGUOUS_SIZE_LIMIT.
++*/
++#ifndef gcdCONTIGUOUS_SIZE_LIMIT
++# define gcdCONTIGUOUS_SIZE_LIMIT 0
++#endif
++
++/*
++ gcdLINK_QUEUE_SIZE
++
++ When non-zero, driver maintains a queue to record information of
++ latest lined context buffer and command buffer. Data in this queue
++ is be used to debug.
++*/
++#ifndef gcdLINK_QUEUE_SIZE
++# define gcdLINK_QUEUE_SIZE 5
++#endif
++
++/* gcdALPHA_KILL_IN_SHADER
++
++ Enable alpha kill inside the shader. This will be set automatically by the
++ HAL if certain states match a criteria.
++*/
++#ifndef gcdALPHA_KILL_IN_SHADER
++# define gcdALPHA_KILL_IN_SHADER 1
++#endif
++
++
++
++/*
++ gcdDVFS
++
++ When non-zero, software will make use of dynamic voltage and
++ frequency feature.
++ */
++#ifndef gcdDVFS
++# define gcdDVFS 0
++# define gcdDVFS_ANAYLSE_WINDOW 4
++# define gcdDVFS_POLLING_TIME (gcdDVFS_ANAYLSE_WINDOW * 4)
++#endif
++
++#ifndef gcdSYNC
++# define gcdSYNC 1
++#endif
++
++#ifndef gcdSHADER_SRC_BY_MACHINECODE
++# define gcdSHADER_SRC_BY_MACHINECODE 1
++#endif
++
++#ifndef gcdGLB27_SHADER_REPLACE_OPTIMIZATION
++# define gcdGLB27_SHADER_REPLACE_OPTIMIZATION 1
++#endif
++
++/*
++ gcdSTREAM_OUT_BUFFER
++
++ Enable suppport for the secondary stream out buffer.
++*/
++#ifndef gcdSTREAM_OUT_BUFFER
++# define gcdSTREAM_OUT_BUFFER 0
++# define gcdSTREAM_OUT_NAIVE_SYNC 0
++#endif
++
++/*
++ gcdUSE_HARDWARE_CONFIGURATION_TABLES
++
++ Enable the use of hardware configuration tables,
++ instead of query hardware and determine the features.
++*/
++#ifndef gcdUSE_HARDWARE_CONFIGURATION_TABLES
++# define gcdUSE_HARDWARE_CONFIGURATION_TABLES 0
++#endif
++
++/*
++ gcdSUPPORT_SWAP_RECTANGLE
++
++ Support swap with a specific rectangle.
++
++ Set the rectangle with eglSetSwapRectangleVIV api.
++ Android only.
++*/
++#ifndef gcdSUPPORT_SWAP_RECTANGLE
++# define gcdSUPPORT_SWAP_RECTANGLE 1
++#endif
++
++/*
++ gcdGPU_LINEAR_BUFFER_ENABLED
++
++ Use linear buffer for GPU apps so HWC can do 2D composition.
++ Android only.
++*/
++#ifndef gcdGPU_LINEAR_BUFFER_ENABLED
++# define gcdGPU_LINEAR_BUFFER_ENABLED 1
++#endif
++
++/*
++ gcdENABLE_RENDER_INTO_WINDOW
++
++ Enable Render-Into-Window (ie, No-Resolve) feature on android.
++ NOTE that even if enabled, it still depends on hardware feature and
++ android application behavior. When hardware feature or application
++ behavior can not support render into window mode, it will fail back
++ to normal mode.
++ When Render-Into-Window is finally used, window back buffer of android
++ applications will be allocated matching render target tiling format.
++ Otherwise buffer tiling is decided by the above option
++ 'gcdGPU_LINEAR_BUFFER_ENABLED'.
++ Android only for now.
++*/
++#ifndef gcdENABLE_RENDER_INTO_WINDOW
++# define gcdENABLE_RENDER_INTO_WINDOW 1
++#endif
++
++/*
++ gcdENABLE_RENDER_INTO_WINDOW_WITH_FC
++
++ Enable Direct-rendering (ie, No-Resolve) with tile status.
++ This is expremental and in development stage.
++ This will dynamically check if color compression is available.
++*/
++#ifndef gcdENABLE_RENDER_INTO_WINDOW_WITH_FC
++# define gcdENABLE_RENDER_INTO_WINDOW_WITH_FC 1
++#endif
++
++/*
++ gcdENABLE_BLIT_BUFFER_PRESERVE
++
++ Render-Into-Window (ie, No-Resolve) does not include preserved swap
++ behavior. This feature can enable buffer preserve in No-Resolve mode.
++ When enabled, previous buffer (may be part of ) will be resolve-blitted
++ to current buffer.
++*/
++#ifndef gcdENABLE_BLIT_BUFFER_PRESERVE
++# define gcdENABLE_BLIT_BUFFER_PRESERVE 1
++#endif
++
++/*
++ gcdANDROID_NATIVE_FENCE_SYNC
++
++ Enable android native fence sync. It is introduced since jellybean-4.2.
++ Depends on linux kernel option: CONFIG_SYNC.
++
++ 0: Disabled
++ 1: Build framework for native fence sync feature, and EGL extension
++ 2: Enable async swap buffers for client
++ * Native fence sync for client 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for layer in compositor side.
++ 3. Enable async hwcomposer composition.
++ * 'releaseFenceFd' for layer in compositor side, which is native
++ fence sync when client 'dequeueBuffer'
++ * Native fence sync for compositor 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for framebuffer target for DC
++ */
++#ifndef gcdANDROID_NATIVE_FENCE_SYNC
++# define gcdANDROID_NATIVE_FENCE_SYNC 0
++#endif
++
++/*
++ gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC
++
++ Enable implicit android native buffer sync.
++
++ For non-HW_RENDER buffer, CPU (or other hardware) and GPU can access
++ the buffer at the same time. This is to add implicit synchronization
++ between CPU (or the hardware) and GPU.
++
++ Eventually, please do not use implicit native buffer sync, but use
++ "fence sync" or "android native fence sync" instead in libgui, which
++ can be enabled in frameworks/native/libs/gui/Android.mk. This kind
++ of synchronization should be done by app but not driver itself.
++
++ Please disable this option when either "fence sync" or
++ "android native fence sync" is enabled.
++ */
++#ifndef gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC
++# define gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC 1
++#endif
++
++/*
++ * Implicit native buffer sync is not needed when ANDROID_native_fence_sync
++ * is available.
++ */
++#if gcdANDROID_NATIVE_FENCE_SYNC
++# undef gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC
++# define gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC 0
++#endif
++
++/*
++ gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++
++ Enable source surface address adjust when composition on android.
++ Android only.
++*/
++#ifndef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 1
++#endif
++
++/*
++ gcdUSE_WCLIP_PATCH
++
++ Enable wclipping patch.
++*/
++#ifndef gcdUSE_WCLIP_PATCH
++# define gcdUSE_WCLIP_PATCH 1
++#endif
++
++#ifndef gcdUSE_NPOT_PATCH
++# define gcdUSE_NPOT_PATCH 1
++#endif
++
++/*
++ gcd3DBLIT
++
++ TODO: Should be replaced by feature bit if available.
++*/
++#ifndef gcd3DBLIT
++# define gcd3DBLIT 0
++#endif
++
++/*
++ gcdINTERNAL_COMMENT
++
++ Wrap internal comment, content wrapped by it and the macor itself
++ will be removed in release driver.
++*/
++#ifndef gcdINTERNAL_COMMENT
++# define gcdINTERNAL_COMMENT 1
++#endif
++
++/*
++ gcdRTT_DISABLE_FC
++
++ Disable RTT FC support. For test only.
++*/
++#ifndef gcdRTT_DISABLE_FC
++# define gcdRTT_DISABLE_FC 0
++#endif
++
++/*
++ gcdFORCE_MIPMAP
++
++ Force generate mipmap for texture.
++*/
++#ifndef gcdFORCE_MIPMAP
++# define gcdFORCE_MIPMAP 0
++#endif
++
++/*
++ gcdFORCE_BILINEAR
++
++ Force bilinear for mipfilter.
++*/
++#ifndef gcdFORCE_BILINEAR
++# define gcdFORCE_BILINEAR 1
++#endif
++
++/*
++ gcdBINARY_TRACE
++
++ When non-zero, binary trace will be generated.
++
++ When gcdBINARY_TRACE_FILE_SIZE is non-zero, binary trace buffer will
++ be written to a file which size is limited to
++ gcdBINARY_TRACE_FILE_SIZE.
++*/
++#ifndef gcdBINARY_TRACE
++# define gcdBINARY_TRACE 0
++# define gcdBINARY_TRACE_FILE_SIZE 0
++#endif
++
++#ifndef gcdMOVG
++# define gcdMOVG 0
++#if gcdMOVG
++# define GC355_PROFILER 1
++# endif
++# define gcdENABLE_TS_DOUBLE_BUFFER 1
++#else
++#if gcdMOVG
++# define GC355_PROFILER 1
++# define gcdENABLE_TS_DOUBLE_BUFFER 0
++#else
++# define gcdENABLE_TS_DOUBLE_BUFFER 1
++#endif
++#endif
++
++/* gcdINTERRUPT_STATISTIC
++ *
++ * Monitor the event send to GPU and interrupt issued by GPU.
++ */
++
++#ifndef gcdINTERRUPT_STATISTIC
++#if defined(LINUX)
++# define gcdINTERRUPT_STATISTIC 1
++#else
++# define gcdINTERRUPT_STATISTIC 0
++#endif
++#endif
++
++/*
++ gcdYINVERTED_RENDERING
++ When it's not zero, we will rendering display buffer
++ with top-bottom direction. All other offscreen rendering
++ will be bottom-top, which follow OpenGL ES spec.
++*/
++#ifndef gcdYINVERTED_RENDERING
++# define gcdYINVERTED_RENDERING 1
++#endif
++
++#if gcdYINVERTED_RENDERING
++/* disable unaligned linear composition adjust in Y-inverted rendering mode. */
++# undef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 0
++#endif
++
++/*
++ gcdFENCE_WAIT_LOOP_COUNT
++ Wait fence, loop count.
++*/
++#ifndef gcdFENCE_WAIT_LOOP_COUNT
++# define gcdFENCE_WAIT_LOOP_COUNT 100
++#endif
++
++/*
++ gcdHAL_3D_DRAWBLIT
++ When it's not zero, we will enable HAL 3D drawblit
++ to replace client 3dblit.
++*/
++#ifndef gcdHAL_3D_DRAWBLIT
++# define gcdHAL_3D_DRAWBLIT 1
++#endif
++
++/*
++ gcdPARTIAL_FAST_CLEAR
++ When it's not zero, partial fast clear is enabled.
++ Depends on gcdHAL_3D_DRAWBLIT, if gcdHAL_3D_DRAWBLIT is not enabled,
++ only available when scissor box is completely aligned.
++ Expremental, under test.
++*/
++#ifndef gcdPARTIAL_FAST_CLEAR
++# define gcdPARTIAL_FAST_CLEAR 1
++#endif
++
++/*
++ gcdREMOVE_SURF_ORIENTATION
++ When it's not zero, we will remove surface orientation function.
++ It wil become to a parameter of resolve function.
++*/
++#ifndef gcdREMOVE_SURF_ORIENTATION
++# define gcdREMOVE_SURF_ORIENTATION 0
++#endif
++
++/*
++ gcdPATTERN_FAST_PATH
++ For pattern match
++*/
++#ifndef gcdPATTERN_FAST_PATH
++# define gcdPATTERN_FAST_PATH 1
++#endif
++
++/*
++ gcdUSE_INPUT_DEVICE
++ disable input devices usage under fb mode to support fb+vdk multi-process
++*/
++#ifndef gcdUSE_INPUT_DEVICE
++# define gcdUSE_INPUT_DEVICE 1
++#endif
++
++
++/*
++ gcdFRAMEINFO_STATISTIC
++ When enable, collect frame information.
++*/
++#ifndef gcdFRAMEINFO_STATISTIC
++
++#if (defined(DBG) && DBG) || defined(DEBUG) || defined(_DEBUG) || gcdDUMP
++# define gcdFRAMEINFO_STATISTIC 1
++#else
++# define gcdFRAMEINFO_STATISTIC 0
++#endif
++
++#endif
++
++/*
++ gcdPACKED_OUTPUT_ADDRESS
++ When it's not zero, ps output is already packed after linked
++*/
++#ifndef gcdPACKED_OUTPUT_ADDRESS
++# define gcdPACKED_OUTPUT_ADDRESS 1
++#endif
++
++/*
++ gcdENABLE_THIRD_PARTY_OPERATION
++ Enable third party operation like tpc or not.
++*/
++#ifndef gcdENABLE_THIRD_PARTY_OPERATION
++# define gcdENABLE_THIRD_PARTY_OPERATION 1
++#endif
++
++
++/*
++ Core configurations. By default enable all cores.
++*/
++#ifndef gcdENABLE_3D
++# define gcdENABLE_3D 1
++#endif
++
++#ifndef gcdENABLE_2D
++# define gcdENABLE_2D 1
++#endif
++
++#ifndef gcdENABLE_VG
++# define gcdENABLE_VG 0
++#endif
++
++#ifndef gcdGC355_MEM_PRINT
++# define gcdGC355_MEM_PRINT 0
++#else
++#if (!((gcdENABLE_3D == 0) && (gcdENABLE_2D == 0) && (gcdENABLE_VG == 1)))
++# undef gcdGC355_MEM_PRINT
++# define gcdGC355_MEM_PRINT 0
++# endif
++#endif
++
++#ifndef gcdENABLE_UNIFIED_CONSTANT
++# define gcdENABLE_UNIFIED_CONSTANT 1
++#endif
++
++/*
++ gcdRECORD_COMMAND
++*/
++#ifndef gcdRECORD_COMMAND
++# define gcdRECORD_COMMAND 0
++#endif
++
++#endif /* __gc_hal_options_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_profiler.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_profiler.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_profiler.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_profiler.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,585 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_profiler_h_
++#define __gc_hal_profiler_h_
++
++#if VIVANTE_PROFILER_NEW
++#include "gc_hal_engine.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define GLVERTEX_OBJECT 10
++#define GLVERTEX_OBJECT_BYTES 11
++
++#define GLINDEX_OBJECT 20
++#define GLINDEX_OBJECT_BYTES 21
++
++#define GLTEXTURE_OBJECT 30
++#define GLTEXTURE_OBJECT_BYTES 31
++
++#define GLBUFOBJ_OBJECT 40
++#define GLBUFOBJ_OBJECT_BYTES 41
++
++#if VIVANTE_PROFILER
++#define gcmPROFILE_GC(Enum, Value) gcoPROFILER_Count(gcvNULL, Enum, Value)
++#else
++#define gcmPROFILE_GC(Enum, Value) do { } while (gcvFALSE)
++#endif
++
++#ifndef gcdNEW_PROFILER_FILE
++#define gcdNEW_PROFILER_FILE 1
++#endif
++
++#define ES11_CALLS 151
++#define ES11_DRAWCALLS (ES11_CALLS + 1)
++#define ES11_STATECHANGECALLS (ES11_DRAWCALLS + 1)
++#define ES11_POINTCOUNT (ES11_STATECHANGECALLS + 1)
++#define ES11_LINECOUNT (ES11_POINTCOUNT + 1)
++#define ES11_TRIANGLECOUNT (ES11_LINECOUNT + 1)
++
++#define ES30_CALLS 159
++#define ES30_DRAWCALLS (ES30_CALLS + 1)
++#define ES30_STATECHANGECALLS (ES30_DRAWCALLS + 1)
++#define ES30_POINTCOUNT (ES30_STATECHANGECALLS + 1)
++#define ES30_LINECOUNT (ES30_POINTCOUNT + 1)
++#define ES30_TRIANGLECOUNT (ES30_LINECOUNT + 1)
++
++#define VG11_CALLS 88
++#define VG11_DRAWCALLS (VG11_CALLS + 1)
++#define VG11_STATECHANGECALLS (VG11_DRAWCALLS + 1)
++#define VG11_FILLCOUNT (VG11_STATECHANGECALLS + 1)
++#define VG11_STROKECOUNT (VG11_FILLCOUNT + 1)
++/* End of Driver API ID Definitions. */
++
++/* HAL & MISC IDs. */
++#define HAL_VERTBUFNEWBYTEALLOC 1
++#define HAL_VERTBUFTOTALBYTEALLOC (HAL_VERTBUFNEWBYTEALLOC + 1)
++#define HAL_VERTBUFNEWOBJALLOC (HAL_VERTBUFTOTALBYTEALLOC + 1)
++#define HAL_VERTBUFTOTALOBJALLOC (HAL_VERTBUFNEWOBJALLOC + 1)
++#define HAL_INDBUFNEWBYTEALLOC (HAL_VERTBUFTOTALOBJALLOC + 1)
++#define HAL_INDBUFTOTALBYTEALLOC (HAL_INDBUFNEWBYTEALLOC + 1)
++#define HAL_INDBUFNEWOBJALLOC (HAL_INDBUFTOTALBYTEALLOC + 1)
++#define HAL_INDBUFTOTALOBJALLOC (HAL_INDBUFNEWOBJALLOC + 1)
++#define HAL_TEXBUFNEWBYTEALLOC (HAL_INDBUFTOTALOBJALLOC + 1)
++#define HAL_TEXBUFTOTALBYTEALLOC (HAL_TEXBUFNEWBYTEALLOC + 1)
++#define HAL_TEXBUFNEWOBJALLOC (HAL_TEXBUFTOTALBYTEALLOC + 1)
++#define HAL_TEXBUFTOTALOBJALLOC (HAL_TEXBUFNEWOBJALLOC + 1)
++
++#define GPU_CYCLES 1
++#define GPU_READ64BYTE (GPU_CYCLES + 1)
++#define GPU_WRITE64BYTE (GPU_READ64BYTE + 1)
++#define GPU_TOTALCYCLES (GPU_WRITE64BYTE + 1)
++#define GPU_IDLECYCLES (GPU_TOTALCYCLES + 1)
++
++#define VS_INSTCOUNT 1
++#define VS_BRANCHINSTCOUNT (VS_INSTCOUNT + 1)
++#define VS_TEXLDINSTCOUNT (VS_BRANCHINSTCOUNT + 1)
++#define VS_RENDEREDVERTCOUNT (VS_TEXLDINSTCOUNT + 1)
++#define VS_SOURCE (VS_RENDEREDVERTCOUNT + 1)
++
++#define PS_INSTCOUNT 1
++#define PS_BRANCHINSTCOUNT (PS_INSTCOUNT + 1)
++#define PS_TEXLDINSTCOUNT (PS_BRANCHINSTCOUNT + 1)
++#define PS_RENDEREDPIXCOUNT (PS_TEXLDINSTCOUNT + 1)
++#define PS_SOURCE (PS_RENDEREDPIXCOUNT + 1)
++
++#define PA_INVERTCOUNT 1
++#define PA_INPRIMCOUNT (PA_INVERTCOUNT + 1)
++#define PA_OUTPRIMCOUNT (PA_INPRIMCOUNT + 1)
++#define PA_DEPTHCLIPCOUNT (PA_OUTPRIMCOUNT + 1)
++#define PA_TRIVIALREJCOUNT (PA_DEPTHCLIPCOUNT + 1)
++#define PA_CULLCOUNT (PA_TRIVIALREJCOUNT + 1)
++
++#define SE_TRIANGLECOUNT 1
++#define SE_LINECOUNT (SE_TRIANGLECOUNT + 1)
++
++#define RA_VALIDPIXCOUNT 1
++#define RA_TOTALQUADCOUNT (RA_VALIDPIXCOUNT + 1)
++#define RA_VALIDQUADCOUNTEZ (RA_TOTALQUADCOUNT + 1)
++#define RA_TOTALPRIMCOUNT (RA_VALIDQUADCOUNTEZ + 1)
++#define RA_PIPECACHEMISSCOUNT (RA_TOTALPRIMCOUNT + 1)
++#define RA_PREFCACHEMISSCOUNT (RA_PIPECACHEMISSCOUNT + 1)
++#define RA_EEZCULLCOUNT (RA_PREFCACHEMISSCOUNT + 1)
++
++#define TX_TOTBILINEARREQ 1
++#define TX_TOTTRILINEARREQ (TX_TOTBILINEARREQ + 1)
++#define TX_TOTDISCARDTEXREQ (TX_TOTTRILINEARREQ + 1)
++#define TX_TOTTEXREQ (TX_TOTDISCARDTEXREQ + 1)
++#define TX_MEMREADCOUNT (TX_TOTTEXREQ + 1)
++#define TX_MEMREADIN8BCOUNT (TX_MEMREADCOUNT + 1)
++#define TX_CACHEMISSCOUNT (TX_MEMREADIN8BCOUNT + 1)
++#define TX_CACHEHITTEXELCOUNT (TX_CACHEMISSCOUNT + 1)
++#define TX_CACHEMISSTEXELCOUNT (TX_CACHEHITTEXELCOUNT + 1)
++
++#define PE_KILLEDBYCOLOR 1
++#define PE_KILLEDBYDEPTH (PE_KILLEDBYCOLOR + 1)
++#define PE_DRAWNBYCOLOR (PE_KILLEDBYDEPTH + 1)
++#define PE_DRAWNBYDEPTH (PE_DRAWNBYCOLOR + 1)
++
++#define MC_READREQ8BPIPE 1
++#define MC_READREQ8BIP (MC_READREQ8BPIPE + 1)
++#define MC_WRITEREQ8BPIPE (MC_READREQ8BIP + 1)
++
++#define AXI_READREQSTALLED 1
++#define AXI_WRITEREQSTALLED (AXI_READREQSTALLED + 1)
++#define AXI_WRITEDATASTALLED (AXI_WRITEREQSTALLED + 1)
++
++#define PVS_INSTRCOUNT 1
++#define PVS_ALUINSTRCOUNT (PVS_INSTRCOUNT + 1)
++#define PVS_TEXINSTRCOUNT (PVS_ALUINSTRCOUNT + 1)
++#define PVS_ATTRIBCOUNT (PVS_TEXINSTRCOUNT + 1)
++#define PVS_UNIFORMCOUNT (PVS_ATTRIBCOUNT + 1)
++#define PVS_FUNCTIONCOUNT (PVS_UNIFORMCOUNT + 1)
++#define PVS_SOURCE (PVS_FUNCTIONCOUNT + 1)
++
++#define PPS_INSTRCOUNT 1
++#define PPS_ALUINSTRCOUNT (PPS_INSTRCOUNT + 1)
++#define PPS_TEXINSTRCOUNT (PPS_ALUINSTRCOUNT + 1)
++#define PPS_ATTRIBCOUNT (PPS_TEXINSTRCOUNT + 1)
++#define PPS_UNIFORMCOUNT (PPS_ATTRIBCOUNT + 1)
++#define PPS_FUNCTIONCOUNT (PPS_UNIFORMCOUNT + 1)
++#define PPS_SOURCE (PPS_FUNCTIONCOUNT + 1)
++/* End of MISC Counter IDs. */
++
++#ifdef gcdNEW_PROFILER_FILE
++
++/* Category Constants. */
++#define VPHEADER 0x010000
++#define VPG_INFO 0x020000
++#define VPG_TIME 0x030000
++#define VPG_MEM 0x040000
++#define VPG_ES11 0x050000
++#define VPG_ES30 0x060000
++#define VPG_VG11 0x070000
++#define VPG_HAL 0x080000
++#define VPG_HW 0x090000
++#define VPG_GPU 0x0a0000
++#define VPG_VS 0x0b0000
++#define VPG_PS 0x0c0000
++#define VPG_PA 0x0d0000
++#define VPG_SETUP 0x0e0000
++#define VPG_RA 0x0f0000
++#define VPG_TX 0x100000
++#define VPG_PE 0x110000
++#define VPG_MC 0x120000
++#define VPG_AXI 0x130000
++#define VPG_PROG 0x140000
++#define VPG_PVS 0x150000
++#define VPG_PPS 0x160000
++#define VPG_ES11_TIME 0x170000
++#define VPG_ES30_TIME 0x180000
++#define VPG_FRAME 0x190000
++#define VPG_ES11_DRAW 0x200000
++#define VPG_ES30_DRAW 0x210000
++#define VPG_VG11_TIME 0x220000
++#define VPG_END 0xff0000
++
++/* Info. */
++#define VPC_INFOCOMPANY (VPG_INFO + 1)
++#define VPC_INFOVERSION (VPC_INFOCOMPANY + 1)
++#define VPC_INFORENDERER (VPC_INFOVERSION + 1)
++#define VPC_INFOREVISION (VPC_INFORENDERER + 1)
++#define VPC_INFODRIVER (VPC_INFOREVISION + 1)
++#define VPC_INFODRIVERMODE (VPC_INFODRIVER + 1)
++#define VPC_INFOSCREENSIZE (VPC_INFODRIVERMODE + 1)
++
++/* Counter Constants. */
++#define VPC_ELAPSETIME (VPG_TIME + 1)
++#define VPC_CPUTIME (VPC_ELAPSETIME + 1)
++
++#define VPC_MEMMAXRES (VPG_MEM + 1)
++#define VPC_MEMSHARED (VPC_MEMMAXRES + 1)
++#define VPC_MEMUNSHAREDDATA (VPC_MEMSHARED + 1)
++#define VPC_MEMUNSHAREDSTACK (VPC_MEMUNSHAREDDATA + 1)
++
++/* OpenGL ES11 Statics Counter IDs. */
++#define VPC_ES11CALLS (VPG_ES11 + ES11_CALLS)
++#define VPC_ES11DRAWCALLS (VPG_ES11 + ES11_DRAWCALLS)
++#define VPC_ES11STATECHANGECALLS (VPG_ES11 + ES11_STATECHANGECALLS)
++#define VPC_ES11POINTCOUNT (VPG_ES11 + ES11_POINTCOUNT)
++#define VPC_ES11LINECOUNT (VPG_ES11 + ES11_LINECOUNT)
++#define VPC_ES11TRIANGLECOUNT (VPG_ES11 + ES11_TRIANGLECOUNT)
++
++/* OpenGL ES30 Statistics Counter IDs. */
++#define VPC_ES30CALLS (VPG_ES30 + ES30_CALLS)
++#define VPC_ES30DRAWCALLS (VPG_ES30 + ES30_DRAWCALLS)
++#define VPC_ES30STATECHANGECALLS (VPG_ES30 + ES30_STATECHANGECALLS)
++#define VPC_ES30POINTCOUNT (VPG_ES30 + ES30_POINTCOUNT)
++#define VPC_ES30LINECOUNT (VPG_ES30 + ES30_LINECOUNT)
++#define VPC_ES30TRIANGLECOUNT (VPG_ES30 + ES30_TRIANGLECOUNT)
++
++/* OpenVG Statistics Counter IDs. */
++#define VPC_VG11CALLS (VPG_VG11 + VG11_CALLS)
++#define VPC_VG11DRAWCALLS (VPG_VG11 + VG11_DRAWCALLS)
++#define VPC_VG11STATECHANGECALLS (VPG_VG11 + VG11_STATECHANGECALLS)
++#define VPC_VG11FILLCOUNT (VPG_VG11 + VG11_FILLCOUNT)
++#define VPC_VG11STROKECOUNT (VPG_VG11 + VG11_STROKECOUNT)
++
++/* HAL Counters. */
++#define VPC_HALVERTBUFNEWBYTEALLOC (VPG_HAL + HAL_VERTBUFNEWBYTEALLOC)
++#define VPC_HALVERTBUFTOTALBYTEALLOC (VPG_HAL + HAL_VERTBUFTOTALBYTEALLOC)
++#define VPC_HALVERTBUFNEWOBJALLOC (VPG_HAL + HAL_VERTBUFNEWOBJALLOC)
++#define VPC_HALVERTBUFTOTALOBJALLOC (VPG_HAL + HAL_VERTBUFTOTALOBJALLOC)
++#define VPC_HALINDBUFNEWBYTEALLOC (VPG_HAL + HAL_INDBUFNEWBYTEALLOC)
++#define VPC_HALINDBUFTOTALBYTEALLOC (VPG_HAL + HAL_INDBUFTOTALBYTEALLOC)
++#define VPC_HALINDBUFNEWOBJALLOC (VPG_HAL + HAL_INDBUFNEWOBJALLOC)
++#define VPC_HALINDBUFTOTALOBJALLOC (VPG_HAL + HAL_INDBUFTOTALOBJALLOC)
++#define VPC_HALTEXBUFNEWBYTEALLOC (VPG_HAL + HAL_TEXBUFNEWBYTEALLOC)
++#define VPC_HALTEXBUFTOTALBYTEALLOC (VPG_HAL + HAL_TEXBUFTOTALBYTEALLOC)
++#define VPC_HALTEXBUFNEWOBJALLOC (VPG_HAL + HAL_TEXBUFNEWOBJALLOC)
++#define VPC_HALTEXBUFTOTALOBJALLOC (VPG_HAL + HAL_TEXBUFTOTALOBJALLOC)
++
++/* HW: GPU Counters. */
++#define VPC_GPUCYCLES (VPG_GPU + GPU_CYCLES)
++#define VPC_GPUREAD64BYTE (VPG_GPU + GPU_READ64BYTE)
++#define VPC_GPUWRITE64BYTE (VPG_GPU + GPU_WRITE64BYTE)
++#define VPC_GPUTOTALCYCLES (VPG_GPU + GPU_TOTALCYCLES)
++#define VPC_GPUIDLECYCLES (VPG_GPU + GPU_IDLECYCLES)
++
++/* HW: Shader Counters. */
++#define VPC_VSINSTCOUNT (VPG_VS + VS_INSTCOUNT)
++#define VPC_VSBRANCHINSTCOUNT (VPG_VS + VS_BRANCHINSTCOUNT)
++#define VPC_VSTEXLDINSTCOUNT (VPG_VS + VS_TEXLDINSTCOUNT)
++#define VPC_VSRENDEREDVERTCOUNT (VPG_VS + VS_RENDEREDVERTCOUNT)
++/* HW: PS Count. */
++#define VPC_PSINSTCOUNT (VPG_PS + PS_INSTCOUNT)
++#define VPC_PSBRANCHINSTCOUNT (VPG_PS + PS_BRANCHINSTCOUNT)
++#define VPC_PSTEXLDINSTCOUNT (VPG_PS + PS_TEXLDINSTCOUNT)
++#define VPC_PSRENDEREDPIXCOUNT (VPG_PS + PS_RENDEREDPIXCOUNT)
++
++
++/* HW: PA Counters. */
++#define VPC_PAINVERTCOUNT (VPG_PA + PA_INVERTCOUNT)
++#define VPC_PAINPRIMCOUNT (VPG_PA + PA_INPRIMCOUNT)
++#define VPC_PAOUTPRIMCOUNT (VPG_PA + PA_OUTPRIMCOUNT)
++#define VPC_PADEPTHCLIPCOUNT (VPG_PA + PA_DEPTHCLIPCOUNT)
++#define VPC_PATRIVIALREJCOUNT (VPG_PA + PA_TRIVIALREJCOUNT)
++#define VPC_PACULLCOUNT (VPG_PA + PA_CULLCOUNT)
++
++/* HW: Setup Counters. */
++#define VPC_SETRIANGLECOUNT (VPG_SETUP + SE_TRIANGLECOUNT)
++#define VPC_SELINECOUNT (VPG_SETUP + SE_LINECOUNT)
++
++/* HW: RA Counters. */
++#define VPC_RAVALIDPIXCOUNT (VPG_RA + RA_VALIDPIXCOUNT)
++#define VPC_RATOTALQUADCOUNT (VPG_RA + RA_TOTALQUADCOUNT)
++#define VPC_RAVALIDQUADCOUNTEZ (VPG_RA + RA_VALIDQUADCOUNTEZ)
++#define VPC_RATOTALPRIMCOUNT (VPG_RA + RA_TOTALPRIMCOUNT)
++#define VPC_RAPIPECACHEMISSCOUNT (VPG_RA + RA_PIPECACHEMISSCOUNT)
++#define VPC_RAPREFCACHEMISSCOUNT (VPG_RA + RA_PREFCACHEMISSCOUNT)
++#define VPC_RAEEZCULLCOUNT (VPG_RA + RA_EEZCULLCOUNT)
++
++/* HW: TEX Counters. */
++#define VPC_TXTOTBILINEARREQ (VPG_TX + TX_TOTBILINEARREQ)
++#define VPC_TXTOTTRILINEARREQ (VPG_TX + TX_TOTTRILINEARREQ)
++#define VPC_TXTOTDISCARDTEXREQ (VPG_TX + TX_TOTDISCARDTEXREQ)
++#define VPC_TXTOTTEXREQ (VPG_TX + TX_TOTTEXREQ)
++#define VPC_TXMEMREADCOUNT (VPG_TX + TX_MEMREADCOUNT)
++#define VPC_TXMEMREADIN8BCOUNT (VPG_TX + TX_MEMREADIN8BCOUNT)
++#define VPC_TXCACHEMISSCOUNT (VPG_TX + TX_CACHEMISSCOUNT)
++#define VPC_TXCACHEHITTEXELCOUNT (VPG_TX + TX_CACHEHITTEXELCOUNT)
++#define VPC_TXCACHEMISSTEXELCOUNT (VPG_TX + TX_CACHEMISSTEXELCOUNT)
++
++/* HW: PE Counters. */
++#define VPC_PEKILLEDBYCOLOR (VPG_PE + PE_KILLEDBYCOLOR)
++#define VPC_PEKILLEDBYDEPTH (VPG_PE + PE_KILLEDBYDEPTH)
++#define VPC_PEDRAWNBYCOLOR (VPG_PE + PE_DRAWNBYCOLOR)
++#define VPC_PEDRAWNBYDEPTH (VPG_PE + PE_DRAWNBYDEPTH)
++
++/* HW: MC Counters. */
++#define VPC_MCREADREQ8BPIPE (VPG_MC + MC_READREQ8BPIPE)
++#define VPC_MCREADREQ8BIP (VPG_MC + MC_READREQ8BIP)
++#define VPC_MCWRITEREQ8BPIPE (VPG_MC + MC_WRITEREQ8BPIPE)
++
++/* HW: AXI Counters. */
++#define VPC_AXIREADREQSTALLED (VPG_AXI + AXI_READREQSTALLED)
++#define VPC_AXIWRITEREQSTALLED (VPG_AXI + AXI_WRITEREQSTALLED)
++#define VPC_AXIWRITEDATASTALLED (VPG_AXI + AXI_WRITEDATASTALLED)
++
++/* PROGRAM: Shader program counters. */
++#define VPC_PVSINSTRCOUNT (VPG_PVS + PVS_INSTRCOUNT)
++#define VPC_PVSALUINSTRCOUNT (VPG_PVS + PVS_ALUINSTRCOUNT)
++#define VPC_PVSTEXINSTRCOUNT (VPG_PVS + PVS_TEXINSTRCOUNT)
++#define VPC_PVSATTRIBCOUNT (VPG_PVS + PVS_ATTRIBCOUNT)
++#define VPC_PVSUNIFORMCOUNT (VPG_PVS + PVS_UNIFORMCOUNT)
++#define VPC_PVSFUNCTIONCOUNT (VPG_PVS + PVS_FUNCTIONCOUNT)
++#define VPC_PVSSOURCE (VPG_PVS + PVS_SOURCE)
++
++#define VPC_PPSINSTRCOUNT (VPG_PPS + PPS_INSTRCOUNT)
++#define VPC_PPSALUINSTRCOUNT (VPG_PPS + PPS_ALUINSTRCOUNT)
++#define VPC_PPSTEXINSTRCOUNT (VPG_PPS + PPS_TEXINSTRCOUNT)
++#define VPC_PPSATTRIBCOUNT (VPG_PPS + PPS_ATTRIBCOUNT)
++#define VPC_PPSUNIFORMCOUNT (VPG_PPS + PPS_UNIFORMCOUNT)
++#define VPC_PPSFUNCTIONCOUNT (VPG_PPS + PPS_FUNCTIONCOUNT)
++#define VPC_PPSSOURCE (VPG_PPS + PPS_SOURCE)
++
++#define VPC_PROGRAMHANDLE (VPG_PROG + 1)
++
++#define VPC_ES30_DRAW_NO (VPG_ES30_DRAW + 1)
++#define VPC_ES11_DRAW_NO (VPG_ES11_DRAW + 1)
++#endif
++
++
++/* HW profile information. */
++typedef struct _gcsPROFILER_COUNTERS
++{
++ /* HW static counters. */
++ gctUINT32 gpuClock;
++ gctUINT32 axiClock;
++ gctUINT32 shaderClock;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuClockStart;
++ gctUINT32 gpuClockEnd;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuCyclesCounter;
++ gctUINT32 gpuTotalCyclesCounter;
++ gctUINT32 gpuIdleCyclesCounter;
++ gctUINT32 gpuTotalRead64BytesPerFrame;
++ gctUINT32 gpuTotalWrite64BytesPerFrame;
++
++ /* PE */
++ gctUINT32 pe_pixel_count_killed_by_color_pipe;
++ gctUINT32 pe_pixel_count_killed_by_depth_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_color_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_depth_pipe;
++
++ /* SH */
++ gctUINT32 ps_inst_counter;
++ gctUINT32 rendered_pixel_counter;
++ gctUINT32 vs_inst_counter;
++ gctUINT32 rendered_vertice_counter;
++ gctUINT32 vtx_branch_inst_counter;
++ gctUINT32 vtx_texld_inst_counter;
++ gctUINT32 pxl_branch_inst_counter;
++ gctUINT32 pxl_texld_inst_counter;
++
++ /* PA */
++ gctUINT32 pa_input_vtx_counter;
++ gctUINT32 pa_input_prim_counter;
++ gctUINT32 pa_output_prim_counter;
++ gctUINT32 pa_depth_clipped_counter;
++ gctUINT32 pa_trivial_rejected_counter;
++ gctUINT32 pa_culled_counter;
++
++ /* SE */
++ gctUINT32 se_culled_triangle_count;
++ gctUINT32 se_culled_lines_count;
++
++ /* RA */
++ gctUINT32 ra_valid_pixel_count;
++ gctUINT32 ra_total_quad_count;
++ gctUINT32 ra_valid_quad_count_after_early_z;
++ gctUINT32 ra_total_primitive_count;
++ gctUINT32 ra_pipe_cache_miss_counter;
++ gctUINT32 ra_prefetch_cache_miss_counter;
++ gctUINT32 ra_eez_culled_counter;
++
++ /* TX */
++ gctUINT32 tx_total_bilinear_requests;
++ gctUINT32 tx_total_trilinear_requests;
++ gctUINT32 tx_total_discarded_texture_requests;
++ gctUINT32 tx_total_texture_requests;
++ gctUINT32 tx_mem_read_count;
++ gctUINT32 tx_mem_read_in_8B_count;
++ gctUINT32 tx_cache_miss_count;
++ gctUINT32 tx_cache_hit_texel_count;
++ gctUINT32 tx_cache_miss_texel_count;
++
++ /* MC */
++ gctUINT32 mc_total_read_req_8B_from_pipeline;
++ gctUINT32 mc_total_read_req_8B_from_IP;
++ gctUINT32 mc_total_write_req_8B_from_pipeline;
++
++ /* HI */
++ gctUINT32 hi_axi_cycles_read_request_stalled;
++ gctUINT32 hi_axi_cycles_write_request_stalled;
++ gctUINT32 hi_axi_cycles_write_data_stalled;
++}
++gcsPROFILER_COUNTERS;
++
++#if VIVANTE_PROFILER_NEW
++#define NumOfDrawBuf 64
++#endif
++
++/* HAL profile information. */
++typedef struct _gcsPROFILER
++{
++ gctUINT32 enable;
++ gctBOOL enableHal;
++ gctBOOL enableHW;
++ gctBOOL enableSH;
++ gctBOOL isSyncMode;
++ gctBOOL disableOutputCounter;
++
++ gctBOOL useSocket;
++ gctINT sockFd;
++
++ gctFILE file;
++
++ /* Aggregate Information */
++
++ /* Clock Info */
++ gctUINT64 frameStart;
++ gctUINT64 frameEnd;
++
++ /* Current frame information */
++ gctUINT32 frameNumber;
++ gctUINT64 frameStartTimeusec;
++ gctUINT64 frameEndTimeusec;
++ gctUINT64 frameStartCPUTimeusec;
++ gctUINT64 frameEndCPUTimeusec;
++
++#if PROFILE_HAL_COUNTERS
++ gctUINT32 vertexBufferTotalBytesAlloc;
++ gctUINT32 vertexBufferNewBytesAlloc;
++ int vertexBufferTotalObjectsAlloc;
++ int vertexBufferNewObjectsAlloc;
++
++ gctUINT32 indexBufferTotalBytesAlloc;
++ gctUINT32 indexBufferNewBytesAlloc;
++ int indexBufferTotalObjectsAlloc;
++ int indexBufferNewObjectsAlloc;
++
++ gctUINT32 textureBufferTotalBytesAlloc;
++ gctUINT32 textureBufferNewBytesAlloc;
++ int textureBufferTotalObjectsAlloc;
++ int textureBufferNewObjectsAlloc;
++
++ gctUINT32 numCommits;
++ gctUINT32 drawPointCount;
++ gctUINT32 drawLineCount;
++ gctUINT32 drawTriangleCount;
++ gctUINT32 drawVertexCount;
++ gctUINT32 redundantStateChangeCalls;
++#endif
++
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++
++#if VIVANTE_PROFILER_NEW
++ gcoBUFOBJ newCounterBuf[NumOfDrawBuf];
++ gctUINT32 curBufId;
++#endif
++
++}
++gcsPROFILER;
++
++/* Memory profile information. */
++struct _gcsMemProfile
++{
++ /* Memory Usage */
++ gctUINT32 videoMemUsed;
++ gctUINT32 systemMemUsed;
++ gctUINT32 commitBufferSize;
++ gctUINT32 contextBufferCopyBytes;
++};
++
++/* Shader profile information. */
++struct _gcsSHADER_PROFILER
++{
++ gctUINT32 shaderLength;
++ gctUINT32 shaderALUCycles;
++ gctUINT32 shaderTexLoadCycles;
++ gctUINT32 shaderTempRegCount;
++ gctUINT32 shaderSamplerRegCount;
++ gctUINT32 shaderInputRegCount;
++ gctUINT32 shaderOutputRegCount;
++};
++
++/* Initialize the gcsProfiler. */
++gceSTATUS
++gcoPROFILER_Initialize(
++ IN gcoHAL Hal,
++ IN gctBOOL Enable
++ );
++
++/* Destroy the gcProfiler. */
++gceSTATUS
++gcoPROFILER_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Write data to profiler. */
++gceSTATUS
++gcoPROFILER_Write(
++ IN gcoHAL Hal,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data out. */
++gceSTATUS
++gcoPROFILER_Flush(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of frame. */
++gceSTATUS
++gcoPROFILER_EndFrame(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of draw. */
++gceSTATUS
++gcoPROFILER_EndDraw(
++ IN gcoHAL Hal,
++ IN gctBOOL FirstDraw
++ );
++
++/* Increase profile counter Enum by Value. */
++gceSTATUS
++gcoPROFILER_Count(
++ IN gcoHAL Hal,
++ IN gctUINT32 Enum,
++ IN gctINT Value
++ );
++
++/* Profile input vertex shader. */
++gceSTATUS
++gcoPROFILER_ShaderVS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Vs
++ );
++
++/* Profile input fragment shader. */
++gceSTATUS
++gcoPROFILER_ShaderFS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Fs
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_profiler_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_raster.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_raster.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_raster.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_raster.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,1038 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_raster_h_
++#define __gc_hal_raster_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoBRUSH * gcoBRUSH;
++typedef struct _gcoBRUSH_CACHE * gcoBRUSH_CACHE;
++
++/******************************************************************************\
++******************************** gcoBRUSH Object *******************************
++\******************************************************************************/
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructSingleColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructMonochrome(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Destroy an gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_Destroy(
++ IN gcoBRUSH Brush
++ );
++
++/******************************************************************************\
++******************************** gcoSURF Object *******************************
++\******************************************************************************/
++
++/* Set cipping rectangle. */
++gceSTATUS
++gcoSURF_SetClipping(
++ IN gcoSURF Surface
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gcoSURF_Clear2D(
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 LoColor,
++ IN gctUINT32 HiColor
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gcoSURF_Line(
++ IN gcoSURF Surface,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Generic rectangular blit. */
++gceSTATUS
++gcoSURF_Blit(
++ IN OPTIONAL gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN OPTIONAL gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN OPTIONAL gceSURF_TRANSPARENCY Transparency,
++ IN OPTIONAL gctUINT32 TransparencyColor,
++ IN OPTIONAL gctPOINTER Mask,
++ IN OPTIONAL gceSURF_MONOPACK MaskPack
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gcoSURF_MonoBlit(
++ IN gcoSURF DestSurface,
++ IN gctPOINTER Source,
++ IN gceSURF_MONOPACK SourcePack,
++ IN gcsPOINT_PTR SourceSize,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Filter blit. */
++gceSTATUS
++gcoSURF_FilterBlit(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gcoSURF_EnableAlphaBlend(
++ IN gcoSURF Surface,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gcoSURF_DisableAlphaBlend(
++ IN gcoSURF Surface
++ );
++
++/* Copy a rectangular area with format conversion. */
++gceSTATUS
++gcoSURF_CopyPixels(
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++/* Read surface pixel. */
++gceSTATUS
++gcoSURF_ReadPixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ OUT gctPOINTER PixelValue
++ );
++
++/* Write surface pixel. */
++gceSTATUS
++gcoSURF_WritePixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ IN gctPOINTER PixelValue
++ );
++
++gceSTATUS
++gcoSURF_SetDither(
++ IN gcoSURF Surface,
++ IN gctBOOL Dither
++ );
++
++gceSTATUS
++gcoSURF_Set2DSource(
++ gcoSURF Surface,
++ gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_Set2DTarget(
++ gcoSURF Surface,
++ gceSURF_ROTATION Rotation
++ );
++
++/******************************************************************************\
++********************************** gco2D Object *********************************
++\******************************************************************************/
++
++/* Construct a new gco2D object. */
++gceSTATUS
++gco2D_Construct(
++ IN gcoHAL Hal,
++ OUT gco2D * Hardware
++ );
++
++/* Destroy an gco2D object. */
++gceSTATUS
++gco2D_Destroy(
++ IN gco2D Hardware
++ );
++
++/* Sets the maximum number of brushes in the brush cache. */
++gceSTATUS
++gco2D_SetBrushLimit(
++ IN gco2D Hardware,
++ IN gctUINT MaxCount
++ );
++
++/* Flush the brush. */
++gceSTATUS
++gco2D_FlushBrush(
++ IN gco2D Engine,
++ IN gcoBRUSH Brush,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Program the specified solid color brush. */
++gceSTATUS
++gco2D_LoadSolidBrush(
++ IN gco2D Engine,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask
++ );
++
++/* Configure monochrome source. */
++gceSTATUS
++gco2D_SetMonochromeSource(
++ IN gco2D Engine,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_MONOPACK DataPack,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source extension for full rotation. */
++gceSTATUS
++gco2D_SetColorSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSourceAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative
++ );
++
++gceSTATUS
++gco2D_SetColorSourceN(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctUINT32 SurfaceNumber
++ );
++
++/* Configure masked color source. */
++gceSTATUS
++gco2D_SetMaskedSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack
++ );
++
++/* Configure masked color source extension for full rotation. */
++gceSTATUS
++gco2D_SetMaskedSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Setup the source rectangle. */
++gceSTATUS
++gco2D_SetSource(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect
++ );
++
++/* Set clipping rectangle. */
++gceSTATUS
++gco2D_SetClipping(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++/* Configure destination. */
++gceSTATUS
++gco2D_SetTarget(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth
++ );
++
++/* Configure destination extension for full rotation. */
++gceSTATUS
++gco2D_SetTargetEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Calculate and program the stretch factors. */
++gceSTATUS
++gco2D_CalcStretchFactor(
++ IN gco2D Engine,
++ IN gctINT32 SrcSize,
++ IN gctINT32 DestSize,
++ OUT gctUINT32_PTR Factor
++ );
++
++gceSTATUS
++gco2D_SetStretchFactors(
++ IN gco2D Engine,
++ IN gctUINT32 HorFactor,
++ IN gctUINT32 VerFactor
++ );
++
++/* Calculate and program the stretch factors based on the rectangles. */
++gceSTATUS
++gco2D_SetStretchRectFactors(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect
++ );
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructSingleColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gco2D_Clear(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gco2D_Line(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines based on the 32-bit color. */
++gceSTATUS
++gco2D_ColorLine(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Generic blit. */
++gceSTATUS
++gco2D_Blit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_Blend(
++ IN gco2D Engine,
++ IN gctUINT32 SrcCount,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Batch blit. */
++gceSTATUS
++gco2D_BatchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Stretch blit. */
++gceSTATUS
++gco2D_StretchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gco2D_MonoBlit(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gcsPOINT_PTR StreamSize,
++ IN gcsRECT_PTR StreamRect,
++ IN gceSURF_MONOPACK SrcStreamPack,
++ IN gceSURF_MONOPACK DestStreamPack,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 FgRop,
++ IN gctUINT32 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_MonoBlitEx(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gctINT32 StreamStride,
++ IN gctINT32 StreamWidth,
++ IN gctINT32 StreamHeight,
++ IN gctINT32 StreamX,
++ IN gctINT32 StreamY,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DstRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Set kernel size. */
++gceSTATUS
++gco2D_SetKernelSize(
++ IN gco2D Engine,
++ IN gctUINT8 HorKernelSize,
++ IN gctUINT8 VerKernelSize
++ );
++
++/* Set filter type. */
++gceSTATUS
++gco2D_SetFilterType(
++ IN gco2D Engine,
++ IN gceFILTER_TYPE FilterType
++ );
++
++/* Set the filter kernel by user. */
++gceSTATUS
++gco2D_SetUserFilterKernel(
++ IN gco2D Engine,
++ IN gceFILTER_PASS_TYPE PassType,
++ IN gctUINT16_PTR KernelArray
++ );
++
++/* Select the pass(es) to be done for user defined filter. */
++gceSTATUS
++gco2D_EnableUserFilterPasses(
++ IN gco2D Engine,
++ IN gctBOOL HorPass,
++ IN gctBOOL VerPass
++ );
++
++/* Frees the temporary buffer allocated by filter blit operation. */
++gceSTATUS
++gco2D_FreeFilterBuffer(
++ IN gco2D Engine
++ );
++
++/* Filter blit. */
++gceSTATUS
++gco2D_FilterBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Filter blit extension for full rotation. */
++gceSTATUS
++gco2D_FilterBlitEx(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++gceSTATUS
++gco2D_FilterBlitEx2(
++ IN gco2D Engine,
++ IN gctUINT32_PTR SrcAddresses,
++ IN gctUINT32 SrcAddressNum,
++ IN gctUINT32_PTR SrcStrides,
++ IN gctUINT32 SrcStrideNum,
++ IN gceTILING SrcTiling,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32_PTR DestAddresses,
++ IN gctUINT32 DestAddressNum,
++ IN gctUINT32_PTR DestStrides,
++ IN gctUINT32 DestStrideNum,
++ IN gceTILING DestTiling,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gco2D_EnableAlphaBlend(
++ IN gco2D Engine,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Enable alpha blending engine in the hardware. */
++gceSTATUS
++gco2D_EnableAlphaBlendAdvanced(
++ IN gco2D Engine,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode
++ );
++
++/* Enable alpha blending engine with Porter Duff rule. */
++gceSTATUS
++gco2D_SetPorterDuffBlending(
++ IN gco2D Engine,
++ IN gce2D_PORTER_DUFF_RULE Rule
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gco2D_DisableAlphaBlend(
++ IN gco2D Engine
++ );
++
++/* Retrieve the maximum number of 32-bit data chunks for a single DE command. */
++gctUINT32
++gco2D_GetMaximumDataCount(
++ void
++ );
++
++/* Retrieve the maximum number of rectangles, that can be passed in a single DE command. */
++gctUINT32
++gco2D_GetMaximumRectCount(
++ void
++ );
++
++/* Returns the pixel alignment of the surface. */
++gceSTATUS
++gco2D_GetPixelAlignment(
++ gceSURF_FORMAT Format,
++ gcsPOINT_PTR Alignment
++ );
++
++/* Retrieve monochrome stream pack size. */
++gceSTATUS
++gco2D_GetPackSize(
++ IN gceSURF_MONOPACK StreamPack,
++ OUT gctUINT32 * PackWidth,
++ OUT gctUINT32 * PackHeight
++ );
++
++/* Flush the 2D pipeline. */
++gceSTATUS
++gco2D_Flush(
++ IN gco2D Engine
++ );
++
++/* Load 256-entry color table for INDEX8 source surfaces. */
++gceSTATUS
++gco2D_LoadPalette(
++ IN gco2D Engine,
++ IN gctUINT FirstIndex,
++ IN gctUINT IndexCount,
++ IN gctPOINTER ColorTable,
++ IN gctBOOL ColorConvert
++ );
++
++/* Enable/disable 2D BitBlt mirrorring. */
++gceSTATUS
++gco2D_SetBitBlitMirror(
++ IN gco2D Engine,
++ IN gctBOOL HorizontalMirror,
++ IN gctBOOL VerticalMirror
++ );
++
++/*
++ * Set the transparency for source, destination and pattern.
++ * It also enable or disable the DFB color key mode.
++ */
++gceSTATUS
++gco2D_SetTransparencyAdvancedEx(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency,
++ IN gctBOOL EnableDFBColorKeyMode
++ );
++
++/* Set the transparency for source, destination and pattern. */
++gceSTATUS
++gco2D_SetTransparencyAdvanced(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency
++ );
++
++/* Set the source color key. */
++gceSTATUS
++gco2D_SetSourceColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the source color key range. */
++gceSTATUS
++gco2D_SetSourceColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the target color key. */
++gceSTATUS
++gco2D_SetTargetColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the target color key range. */
++gceSTATUS
++gco2D_SetTargetColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the YUV color space mode. */
++gceSTATUS
++gco2D_SetYUVColorMode(
++ IN gco2D Engine,
++ IN gce2D_YUV_COLOR_MODE Mode
++ );
++
++/* Setup the source global color value in ARGB8 format. */
++gceSTATUS gco2D_SetSourceGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the target global color value in ARGB8 format. */
++gceSTATUS gco2D_SetTargetGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the source and target pixel multiply modes. */
++gceSTATUS
++gco2D_SetPixelMultiplyModeAdvanced(
++ IN gco2D Engine,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE SrcPremultiplySrcAlpha,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstPremultiplyDstAlpha,
++ IN gce2D_GLOBAL_COLOR_MULTIPLY_MODE SrcPremultiplyGlobalMode,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstDemultiplyDstAlpha
++ );
++
++/* Set the GPU clock cycles after which the idle engine will keep auto-flushing. */
++gceSTATUS
++gco2D_SetAutoFlushCycles(
++ IN gco2D Engine,
++ IN gctUINT32 Cycles
++ );
++
++#if VIVANTE_PROFILER
++/* Read the profile registers available in the 2D engine and sets them in the profile.
++ The function will also reset the pixelsRendered counter every time.
++*/
++gceSTATUS
++gco2D_ProfileEngine(
++ IN gco2D Engine,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ );
++#endif
++
++/* Enable or disable 2D dithering. */
++gceSTATUS
++gco2D_EnableDither(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetGenericSource(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetGenericTarget(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetCurrentSourceIndex(
++ IN gco2D Engine,
++ IN gctUINT32 SrcIndex
++ );
++
++gceSTATUS
++gco2D_MultiSourceBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SourceMask,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 RectCount
++ );
++
++gceSTATUS
++gco2D_SetROP(
++ IN gco2D Engine,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++gceSTATUS
++gco2D_SetGdiStretchMode(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetSourceTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TSControl,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_SetTargetTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TileStatusConfig,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_QueryU32(
++ IN gco2D Engine,
++ IN gce2D_QUERY Item,
++ OUT gctUINT32_PTR Value
++ );
++
++gceSTATUS
++gco2D_SetStateU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32 Value
++ );
++
++gceSTATUS
++gco2D_SetStateArrayI32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetStateArrayU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetTargetRect(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++gceSTATUS
++gco2D_Set2DEngine(
++ IN gco2D Engine
++ );
++
++gceSTATUS
++gco2D_UnSet2DEngine(
++ IN gco2D Engine
++ );
++
++gceSTATUS
++gco2D_Get2DEngine(
++ OUT gco2D * Engine
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_raster_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_rename.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_rename.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_rename.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_rename.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,243 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_rename_h_
++#define __gc_hal_rename_h_
++
++
++#if defined(_HAL2D_APPENDIX)
++
++#define _HAL2D_RENAME_2(api, appendix) api ## appendix
++#define _HAL2D_RENAME_1(api, appendix) _HAL2D_RENAME_2(api, appendix)
++#define gcmHAL2D(api) _HAL2D_RENAME_1(api, _HAL2D_APPENDIX)
++
++
++#define gckOS_Construct gcmHAL2D(gckOS_Construct)
++#define gckOS_Destroy gcmHAL2D(gckOS_Destroy)
++#define gckOS_QueryVideoMemory gcmHAL2D(gckOS_QueryVideoMemory)
++#define gckOS_Allocate gcmHAL2D(gckOS_Allocate)
++#define gckOS_Free gcmHAL2D(gckOS_Free)
++#define gckOS_AllocateMemory gcmHAL2D(gckOS_AllocateMemory)
++#define gckOS_FreeMemory gcmHAL2D(gckOS_FreeMemory)
++#define gckOS_AllocatePagedMemory gcmHAL2D(gckOS_AllocatePagedMemory)
++#define gckOS_AllocatePagedMemoryEx gcmHAL2D(gckOS_AllocatePagedMemoryEx)
++#define gckOS_LockPages gcmHAL2D(gckOS_LockPages)
++#define gckOS_MapPages gcmHAL2D(gckOS_MapPages)
++#define gckOS_UnlockPages gcmHAL2D(gckOS_UnlockPages)
++#define gckOS_FreePagedMemory gcmHAL2D(gckOS_FreePagedMemory)
++#define gckOS_AllocateNonPagedMemory gcmHAL2D(gckOS_AllocateNonPagedMemory)
++#define gckOS_FreeNonPagedMemory gcmHAL2D(gckOS_FreeNonPagedMemory)
++#define gckOS_AllocateContiguous gcmHAL2D(gckOS_AllocateContiguous)
++#define gckOS_FreeContiguous gcmHAL2D(gckOS_FreeContiguous)
++#define gckOS_GetPageSize gcmHAL2D(gckOS_GetPageSize)
++#define gckOS_GetPhysicalAddress gcmHAL2D(gckOS_GetPhysicalAddress)
++#define gckOS_UserLogicalToPhysical gcmHAL2D(gckOS_UserLogicalToPhysical)
++#define gckOS_GetPhysicalAddressProcess gcmHAL2D(gckOS_GetPhysicalAddressProcess)
++#define gckOS_MapPhysical gcmHAL2D(gckOS_MapPhysical)
++#define gckOS_UnmapPhysical gcmHAL2D(gckOS_UnmapPhysical)
++#define gckOS_ReadRegister gcmHAL2D(gckOS_ReadRegister)
++#define gckOS_WriteRegister gcmHAL2D(gckOS_WriteRegister)
++#define gckOS_WriteMemory gcmHAL2D(gckOS_WriteMemory)
++#define gckOS_MapMemory gcmHAL2D(gckOS_MapMemory)
++#define gckOS_UnmapMemory gcmHAL2D(gckOS_UnmapMemory)
++#define gckOS_UnmapMemoryEx gcmHAL2D(gckOS_UnmapMemoryEx)
++#define gckOS_CreateMutex gcmHAL2D(gckOS_CreateMutex)
++#define gckOS_DeleteMutex gcmHAL2D(gckOS_DeleteMutex)
++#define gckOS_AcquireMutex gcmHAL2D(gckOS_AcquireMutex)
++#define gckOS_ReleaseMutex gcmHAL2D(gckOS_ReleaseMutex)
++#define gckOS_AtomicExchange gcmHAL2D(gckOS_AtomicExchange)
++#define gckOS_AtomicExchangePtr gcmHAL2D(gckOS_AtomicExchangePtr)
++#define gckOS_AtomConstruct gcmHAL2D(gckOS_AtomConstruct)
++#define gckOS_AtomDestroy gcmHAL2D(gckOS_AtomDestroy)
++#define gckOS_AtomGet gcmHAL2D(gckOS_AtomGet)
++#define gckOS_AtomIncrement gcmHAL2D(gckOS_AtomIncrement)
++#define gckOS_AtomDecrement gcmHAL2D(gckOS_AtomDecrement)
++#define gckOS_Delay gcmHAL2D(gckOS_Delay)
++#define gckOS_GetTime gcmHAL2D(gckOS_GetTime)
++#define gckOS_MemoryBarrier gcmHAL2D(gckOS_MemoryBarrier)
++#define gckOS_MapUserPointer gcmHAL2D(gckOS_MapUserPointer)
++#define gckOS_UnmapUserPointer gcmHAL2D(gckOS_UnmapUserPointer)
++#define gckOS_QueryNeedCopy gcmHAL2D(gckOS_QueryNeedCopy)
++#define gckOS_CopyFromUserData gcmHAL2D(gckOS_CopyFromUserData)
++#define gckOS_CopyToUserData gcmHAL2D(gckOS_CopyToUserData)
++#define gckOS_SuspendInterrupt gcmHAL2D(gckOS_SuspendInterrupt)
++#define gckOS_ResumeInterrupt gcmHAL2D(gckOS_ResumeInterrupt)
++#define gckOS_GetBaseAddress gcmHAL2D(gckOS_GetBaseAddress)
++#define gckOS_MemCopy gcmHAL2D(gckOS_MemCopy)
++#define gckOS_ZeroMemory gcmHAL2D(gckOS_ZeroMemory)
++#define gckOS_DeviceControl gcmHAL2D(gckOS_DeviceControl)
++#define gckOS_GetProcessID gcmHAL2D(gckOS_GetProcessID)
++#define gckOS_GetThreadID gcmHAL2D(gckOS_GetThreadID)
++#define gckOS_CreateSignal gcmHAL2D(gckOS_CreateSignal)
++#define gckOS_DestroySignal gcmHAL2D(gckOS_DestroySignal)
++#define gckOS_Signal gcmHAL2D(gckOS_Signal)
++#define gckOS_WaitSignal gcmHAL2D(gckOS_WaitSignal)
++#define gckOS_MapSignal gcmHAL2D(gckOS_MapSignal)
++#define gckOS_MapUserMemory gcmHAL2D(gckOS_MapUserMemory)
++#define gckOS_UnmapUserMemory gcmHAL2D(gckOS_UnmapUserMemory)
++#define gckOS_CreateUserSignal gcmHAL2D(gckOS_CreateUserSignal)
++#define gckOS_DestroyUserSignal gcmHAL2D(gckOS_DestroyUserSignal)
++#define gckOS_WaitUserSignal gcmHAL2D(gckOS_WaitUserSignal)
++#define gckOS_SignalUserSignal gcmHAL2D(gckOS_SignalUserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_CacheClean gcmHAL2D(gckOS_CacheClean)
++#define gckOS_CacheFlush gcmHAL2D(gckOS_CacheFlush)
++#define gckOS_SetDebugLevel gcmHAL2D(gckOS_SetDebugLevel)
++#define gckOS_SetDebugZone gcmHAL2D(gckOS_SetDebugZone)
++#define gckOS_SetDebugLevelZone gcmHAL2D(gckOS_SetDebugLevelZone)
++#define gckOS_SetDebugZones gcmHAL2D(gckOS_SetDebugZones)
++#define gckOS_SetDebugFile gcmHAL2D(gckOS_SetDebugFile)
++#define gckOS_Broadcast gcmHAL2D(gckOS_Broadcast)
++#define gckOS_SetGPUPower gcmHAL2D(gckOS_SetGPUPower)
++#define gckOS_CreateSemaphore gcmHAL2D(gckOS_CreateSemaphore)
++#define gckOS_DestroySemaphore gcmHAL2D(gckOS_DestroySemaphore)
++#define gckOS_AcquireSemaphore gcmHAL2D(gckOS_AcquireSemaphore)
++#define gckOS_ReleaseSemaphore gcmHAL2D(gckOS_ReleaseSemaphore)
++#define gckHEAP_Construct gcmHAL2D(gckHEAP_Construct)
++#define gckHEAP_Destroy gcmHAL2D(gckHEAP_Destroy)
++#define gckHEAP_Allocate gcmHAL2D(gckHEAP_Allocate)
++#define gckHEAP_Free gcmHAL2D(gckHEAP_Free)
++#define gckHEAP_ProfileStart gcmHAL2D(gckHEAP_ProfileStart)
++#define gckHEAP_ProfileEnd gcmHAL2D(gckHEAP_ProfileEnd)
++#define gckHEAP_Test gcmHAL2D(gckHEAP_Test)
++#define gckVIDMEM_Construct gcmHAL2D(gckVIDMEM_Construct)
++#define gckVIDMEM_Destroy gcmHAL2D(gckVIDMEM_Destroy)
++#define gckVIDMEM_Allocate gcmHAL2D(gckVIDMEM_Allocate)
++#define gckVIDMEM_AllocateLinear gcmHAL2D(gckVIDMEM_AllocateLinear)
++#define gckVIDMEM_Free gcmHAL2D(gckVIDMEM_Free)
++#define gckVIDMEM_Lock gcmHAL2D(gckVIDMEM_Lock)
++#define gckVIDMEM_Unlock gcmHAL2D(gckVIDMEM_Unlock)
++#define gckVIDMEM_ConstructVirtual gcmHAL2D(gckVIDMEM_ConstructVirtual)
++#define gckVIDMEM_DestroyVirtual gcmHAL2D(gckVIDMEM_DestroyVirtual)
++#define gckKERNEL_Construct gcmHAL2D(gckKERNEL_Construct)
++#define gckKERNEL_Destroy gcmHAL2D(gckKERNEL_Destroy)
++#define gckKERNEL_Dispatch gcmHAL2D(gckKERNEL_Dispatch)
++#define gckKERNEL_QueryVideoMemory gcmHAL2D(gckKERNEL_QueryVideoMemory)
++#define gckKERNEL_GetVideoMemoryPool gcmHAL2D(gckKERNEL_GetVideoMemoryPool)
++#define gckKERNEL_MapVideoMemory gcmHAL2D(gckKERNEL_MapVideoMemory)
++#define gckKERNEL_UnmapVideoMemory gcmHAL2D(gckKERNEL_UnmapVideoMemory)
++#define gckKERNEL_MapMemory gcmHAL2D(gckKERNEL_MapMemory)
++#define gckKERNEL_UnmapMemory gcmHAL2D(gckKERNEL_UnmapMemory)
++#define gckKERNEL_Notify gcmHAL2D(gckKERNEL_Notify)
++#define gckKERNEL_QuerySettings gcmHAL2D(gckKERNEL_QuerySettings)
++#define gckKERNEL_Recovery gcmHAL2D(gckKERNEL_Recovery)
++#define gckKERNEL_OpenUserData gcmHAL2D(gckKERNEL_OpenUserData)
++#define gckKERNEL_CloseUserData gcmHAL2D(gckKERNEL_CloseUserData)
++#define gckHARDWARE_Construct gcmHAL2D(gckHARDWARE_Construct)
++#define gckHARDWARE_Destroy gcmHAL2D(gckHARDWARE_Destroy)
++#define gckHARDWARE_QuerySystemMemory gcmHAL2D(gckHARDWARE_QuerySystemMemory)
++#define gckHARDWARE_BuildVirtualAddress gcmHAL2D(gckHARDWARE_BuildVirtualAddress)
++#define gckHARDWARE_QueryCommandBuffer gcmHAL2D(gckHARDWARE_QueryCommandBuffer)
++#define gckHARDWARE_WaitLink gcmHAL2D(gckHARDWARE_WaitLink)
++#define gckHARDWARE_Execute gcmHAL2D(gckHARDWARE_Execute)
++#define gckHARDWARE_End gcmHAL2D(gckHARDWARE_End)
++#define gckHARDWARE_Nop gcmHAL2D(gckHARDWARE_Nop)
++#define gckHARDWARE_PipeSelect gcmHAL2D(gckHARDWARE_PipeSelect)
++#define gckHARDWARE_Link gcmHAL2D(gckHARDWARE_Link)
++#define gckHARDWARE_Event gcmHAL2D(gckHARDWARE_Event)
++#define gckHARDWARE_QueryMemory gcmHAL2D(gckHARDWARE_QueryMemory)
++#define gckHARDWARE_QueryChipIdentity gcmHAL2D(gckHARDWARE_QueryChipIdentity)
++#define gckHARDWARE_QueryChipSpecs gcmHAL2D(gckHARDWARE_QueryChipSpecs)
++#define gckHARDWARE_QueryShaderCaps gcmHAL2D(gckHARDWARE_QueryShaderCaps)
++#define gckHARDWARE_ConvertFormat gcmHAL2D(gckHARDWARE_ConvertFormat)
++#define gckHARDWARE_SplitMemory gcmHAL2D(gckHARDWARE_SplitMemory)
++#define gckHARDWARE_AlignToTile gcmHAL2D(gckHARDWARE_AlignToTile)
++#define gckHARDWARE_UpdateQueueTail gcmHAL2D(gckHARDWARE_UpdateQueueTail)
++#define gckHARDWARE_ConvertLogical gcmHAL2D(gckHARDWARE_ConvertLogical)
++#define gckHARDWARE_Interrupt gcmHAL2D(gckHARDWARE_Interrupt)
++#define gckHARDWARE_SetMMU gcmHAL2D(gckHARDWARE_SetMMU)
++#define gckHARDWARE_FlushMMU gcmHAL2D(gckHARDWARE_FlushMMU)
++#define gckHARDWARE_GetIdle gcmHAL2D(gckHARDWARE_GetIdle)
++#define gckHARDWARE_Flush gcmHAL2D(gckHARDWARE_Flush)
++#define gckHARDWARE_SetFastClear gcmHAL2D(gckHARDWARE_SetFastClear)
++#define gckHARDWARE_ReadInterrupt gcmHAL2D(gckHARDWARE_ReadInterrupt)
++#define gckHARDWARE_SetPowerManagementState gcmHAL2D(gckHARDWARE_SetPowerManagementState)
++#define gckHARDWARE_QueryPowerManagementState gcmHAL2D(gckHARDWARE_QueryPowerManagementState)
++#define gckHARDWARE_ProfileEngine2D gcmHAL2D(gckHARDWARE_ProfileEngine2D)
++#define gckHARDWARE_InitializeHardware gcmHAL2D(gckHARDWARE_InitializeHardware)
++#define gckHARDWARE_Reset gcmHAL2D(gckHARDWARE_Reset)
++#define gckINTERRUPT_Construct gcmHAL2D(gckINTERRUPT_Construct)
++#define gckINTERRUPT_Destroy gcmHAL2D(gckINTERRUPT_Destroy)
++#define gckINTERRUPT_SetHandler gcmHAL2D(gckINTERRUPT_SetHandler)
++#define gckINTERRUPT_Notify gcmHAL2D(gckINTERRUPT_Notify)
++#define gckEVENT_Construct gcmHAL2D(gckEVENT_Construct)
++#define gckEVENT_Destroy gcmHAL2D(gckEVENT_Destroy)
++#define gckEVENT_AddList gcmHAL2D(gckEVENT_AddList)
++#define gckEVENT_FreeNonPagedMemory gcmHAL2D(gckEVENT_FreeNonPagedMemory)
++#define gckEVENT_FreeContiguousMemory gcmHAL2D(gckEVENT_FreeContiguousMemory)
++#define gckEVENT_FreeVideoMemory gcmHAL2D(gckEVENT_FreeVideoMemory)
++#define gckEVENT_Signal gcmHAL2D(gckEVENT_Signal)
++#define gckEVENT_Unlock gcmHAL2D(gckEVENT_Unlock)
++#define gckEVENT_Submit gcmHAL2D(gckEVENT_Submit)
++#define gckEVENT_Commit gcmHAL2D(gckEVENT_Commit)
++#define gckEVENT_Notify gcmHAL2D(gckEVENT_Notify)
++#define gckEVENT_Interrupt gcmHAL2D(gckEVENT_Interrupt)
++#define gckCOMMAND_Construct gcmHAL2D(gckCOMMAND_Construct)
++#define gckCOMMAND_Destroy gcmHAL2D(gckCOMMAND_Destroy)
++#define gckCOMMAND_EnterCommit gcmHAL2D(gckCOMMAND_EnterCommit)
++#define gckCOMMAND_ExitCommit gcmHAL2D(gckCOMMAND_ExitCommit)
++#define gckCOMMAND_Start gcmHAL2D(gckCOMMAND_Start)
++#define gckCOMMAND_Stop gcmHAL2D(gckCOMMAND_Stop)
++#define gckCOMMAND_Commit gcmHAL2D(gckCOMMAND_Commit)
++#define gckCOMMAND_Reserve gcmHAL2D(gckCOMMAND_Reserve)
++#define gckCOMMAND_Execute gcmHAL2D(gckCOMMAND_Execute)
++#define gckCOMMAND_Stall gcmHAL2D(gckCOMMAND_Stall)
++#define gckCOMMAND_Attach gcmHAL2D(gckCOMMAND_Attach)
++#define gckCOMMAND_Detach gcmHAL2D(gckCOMMAND_Detach)
++#define gckMMU_Construct gcmHAL2D(gckMMU_Construct)
++#define gckMMU_Destroy gcmHAL2D(gckMMU_Destroy)
++#define gckMMU_AllocatePages gcmHAL2D(gckMMU_AllocatePages)
++#define gckMMU_FreePages gcmHAL2D(gckMMU_FreePages)
++#define gckMMU_Test gcmHAL2D(gckMMU_Test)
++#define gckHARDWARE_QueryProfileRegisters gcmHAL2D(gckHARDWARE_QueryProfileRegisters)
++
++
++#define FindMdlMap gcmHAL2D(FindMdlMap)
++#define OnProcessExit gcmHAL2D(OnProcessExit)
++
++#define gckGALDEVICE_Destroy gcmHAL2D(gckGALDEVICE_Destroy)
++#define gckOS_Print gcmHAL2D(gckOS_Print)
++#define gckGALDEVICE_FreeMemory gcmHAL2D(gckGALDEVICE_FreeMemory)
++#define gckGALDEVICE_AllocateMemory gcmHAL2D(gckGALDEVICE_AllocateMemory)
++#define gckOS_DebugBreak gcmHAL2D(gckOS_DebugBreak)
++#define gckGALDEVICE_Release_ISR gcmHAL2D(gckGALDEVICE_Release_ISR)
++#define gckOS_Verify gcmHAL2D(gckOS_Verify)
++#define gckCOMMAND_Release gcmHAL2D(gckCOMMAND_Release)
++#define gckGALDEVICE_Stop gcmHAL2D(gckGALDEVICE_Stop)
++#define gckGALDEVICE_Construct gcmHAL2D(gckGALDEVICE_Construct)
++#define gckOS_DebugFatal gcmHAL2D(gckOS_DebugFatal)
++#define gckOS_DebugTrace gcmHAL2D(gckOS_DebugTrace)
++#define gckHARDWARE_GetBaseAddress gcmHAL2D(gckHARDWARE_GetBaseAddress)
++#define gckGALDEVICE_Setup_ISR gcmHAL2D(gckGALDEVICE_Setup_ISR)
++#define gckKERNEL_AttachProcess gcmHAL2D(gckKERNEL_AttachProcess)
++#define gckKERNEL_AttachProcessEx gcmHAL2D(gckKERNEL_AttachProcessEx)
++#define gckGALDEVICE_Start_Thread gcmHAL2D(gckGALDEVICE_Start_Thread)
++#define gckHARDWARE_QueryIdle gcmHAL2D(gckHARDWARE_QueryIdle)
++#define gckGALDEVICE_Start gcmHAL2D(gckGALDEVICE_Start)
++#define gckOS_GetKernelLogical gcmHAL2D(gckOS_GetKernelLogical)
++#define gckOS_DebugTraceZone gcmHAL2D(gckOS_DebugTraceZone)
++#define gckGALDEVICE_Stop_Thread gcmHAL2D(gckGALDEVICE_Stop_Thread)
++#define gckHARDWARE_NeedBaseAddress gcmHAL2D(gckHARDWARE_NeedBaseAddress)
++
++#endif
++
++#endif /* __gc_hal_rename_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_statistics.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_statistics.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_statistics.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_statistics.h 2016-06-19 22:11:55.157149718 +0200
+@@ -0,0 +1,99 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_statistics_h_
++#define __gc_hal_statistics_h_
++
++
++#define VIV_STAT_ENABLE_STATISTICS 0
++
++/* Toal number of frames for which the frame time is accounted. We have storage
++ to keep frame times for last this many frames.
++*/
++#define VIV_STAT_FRAME_BUFFER_SIZE 30
++
++
++/*
++ Total number of frames sampled for a mode. This means
++
++ # of frames for HZ Current : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ # of frames for HZ Switched : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ +
++ --------------------------------------------------------
++ : (2 * VIV_STAT_EARLY_Z_SAMPLE_FRAMES) frames needed
++
++ IMPORTANT: This total must be smaller than VIV_STAT_FRAME_BUFFER_SIZE
++*/
++#define VIV_STAT_EARLY_Z_SAMPLE_FRAMES 7
++#define VIV_STAT_EARLY_Z_LATENCY_FRAMES 2
++
++/* Multiplication factor for previous Hz off mode. Make it more than 1.0 to advertise HZ on.*/
++#define VIV_STAT_EARLY_Z_FACTOR (1.05f)
++
++/* Defines the statistical data keys monitored by the statistics module */
++typedef enum _gceSTATISTICS
++{
++ gcvFRAME_FPS = 1,
++}
++gceSTATISTICS;
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS_EARLYZ
++{
++ gctUINT switchBackCount;
++ gctUINT nextCheckPoint;
++ gctBOOL disabled;
++}
++gcsSTATISTICS_EARLYZ;
++
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS
++{
++ gctUINT64 frameTime[VIV_STAT_FRAME_BUFFER_SIZE];
++ gctUINT64 previousFrameTime;
++ gctUINT frame;
++ gcsSTATISTICS_EARLYZ earlyZ;
++}
++gcsSTATISTICS;
++
++
++/* Add a frame based data into current statistics. */
++void
++gcfSTATISTICS_AddData(
++ IN gceSTATISTICS Key,
++ IN gctUINT Value
++ );
++
++/* Marks the frame end and triggers statistical calculations and decisions.*/
++void
++gcfSTATISTICS_MarkFrameEnd (
++ void
++ );
++
++/* Sets whether the dynmaic HZ is disabled or not .*/
++void
++gcfSTATISTICS_DisableDynamicEarlyZ (
++ IN gctBOOL Disabled
++ );
++
++#endif /*__gc_hal_statistics_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_types.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_types.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_types.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_types.h 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,911 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_types_h_
++#define __gc_hal_types_h_
++
++#include "gc_hal_version.h"
++#include "gc_hal_options.h"
++
++#if !defined(VIV_KMD)
++#if defined(__KERNEL__)
++#include "linux/version.h"
++#include "linux/types.h"
++#else
++#include <stdlib.h>
++#include <stddef.h>
++#include <stdint.h>
++#endif
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++** Platform macros.
++*/
++
++#if defined(__GNUC__)
++# define gcdHAS_ELLIPSIS 1 /* GCC always has it. */
++#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)
++# define gcdHAS_ELLIPSIS 1 /* C99 has it. */
++#elif defined(_MSC_VER) && (_MSC_VER >= 1500)
++# define gcdHAS_ELLIPSIS 1 /* MSVC 2007+ has it. */
++#elif defined(UNDER_CE)
++#if UNDER_CE >= 600
++# define gcdHAS_ELLIPSIS 1
++# else
++# define gcdHAS_ELLIPSIS 0
++# endif
++#else
++# error "gcdHAS_ELLIPSIS: Platform could not be determined"
++#endif
++
++/******************************************************************************\
++************************************ Keyword ***********************************
++\******************************************************************************/
++#if defined(ANDROID) && defined(__BIONIC_FORTIFY)
++# define gcmINLINE __inline__ __attribute__ ((always_inline)) __attribute__ ((gnu_inline)) __attribute__ ((artificial))
++#elif ((defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)))
++# define gcmINLINE inline /* C99 keyword. */
++#elif defined(__GNUC__)
++# define gcmINLINE __inline__ /* GNU keyword. */
++#elif defined(_MSC_VER) || defined(UNDER_CE)
++# define gcmINLINE __inline /* Internal keyword. */
++#else
++# error "gcmINLINE: Platform could not be determined"
++#endif
++
++/* Possible debug flags. */
++#define gcdDEBUG_NONE 0
++#define gcdDEBUG_ALL (1 << 0)
++#define gcdDEBUG_FATAL (1 << 1)
++#define gcdDEBUG_TRACE (1 << 2)
++#define gcdDEBUG_BREAK (1 << 3)
++#define gcdDEBUG_ASSERT (1 << 4)
++#define gcdDEBUG_CODE (1 << 5)
++#define gcdDEBUG_STACK (1 << 6)
++
++#define gcmIS_DEBUG(flag) ( gcdDEBUG & (flag | gcdDEBUG_ALL) )
++
++#ifndef gcdDEBUG
++#if defined(DEBUG)
++# define gcdDEBUG ( gcdDEBUG_FATAL | gcdDEBUG_TRACE | gcdDEBUG_BREAK | gcdDEBUG_ASSERT )
++# else
++# define gcdDEBUG gcdDEBUG_NONE
++# endif
++#endif
++
++#ifdef _USRDLL
++#ifdef _MSC_VER
++#ifdef HAL_EXPORTS
++# define HALAPI __declspec(dllexport)
++# else
++# define HALAPI __declspec(dllimport)
++# endif
++# define HALDECL __cdecl
++# else
++#ifdef HAL_EXPORTS
++# define HALAPI
++# else
++# define HALAPI extern
++# endif
++# endif
++#else
++# define HALAPI
++# define HALDECL
++#endif
++
++/******************************************************************************\
++********************************** Common Types ********************************
++\******************************************************************************/
++
++#define gcvFALSE 0
++#define gcvTRUE 1
++
++#define gcvINFINITE ((gctUINT32) ~0U)
++
++#define gcvINVALID_HANDLE ((gctHANDLE) ~0U)
++
++typedef int gctBOOL;
++typedef gctBOOL * gctBOOL_PTR;
++
++typedef int gctINT;
++typedef signed char gctINT8;
++typedef signed short gctINT16;
++typedef signed int gctINT32;
++typedef signed long long gctINT64;
++
++typedef gctINT * gctINT_PTR;
++typedef gctINT8 * gctINT8_PTR;
++typedef gctINT16 * gctINT16_PTR;
++typedef gctINT32 * gctINT32_PTR;
++typedef gctINT64 * gctINT64_PTR;
++
++typedef unsigned int gctUINT;
++typedef unsigned char gctUINT8;
++typedef unsigned short gctUINT16;
++typedef unsigned int gctUINT32;
++typedef unsigned long long gctUINT64;
++typedef uintptr_t gctUINTPTR_T;
++
++typedef gctUINT * gctUINT_PTR;
++typedef gctUINT8 * gctUINT8_PTR;
++typedef gctUINT16 * gctUINT16_PTR;
++typedef gctUINT32 * gctUINT32_PTR;
++typedef gctUINT64 * gctUINT64_PTR;
++
++typedef size_t gctSIZE_T;
++typedef gctSIZE_T * gctSIZE_T_PTR;
++typedef gctUINT32 gctTRACE;
++
++#ifdef __cplusplus
++# define gcvNULL 0
++#else
++# define gcvNULL ((void *) 0)
++#endif
++
++#define gcvMAXINT8 0x7f
++#define gcvMININT8 0x80
++#define gcvMAXINT16 0x7fff
++#define gcvMININT16 0x8000
++#define gcvMAXINT32 0x7fffffff
++#define gcvMININT32 0x80000000
++#define gcvMAXINT64 0x7fffffffffffffff
++#define gcvMININT64 0x8000000000000000
++#define gcvMAXUINT8 0xff
++#define gcvMINUINT8 0x0
++#define gcvMAXUINT16 0xffff
++#define gcvMINUINT16 0x8000
++#define gcvMAXUINT32 0xffffffff
++#define gcvMINUINT32 0x80000000
++#define gcvMAXUINT64 0xffffffffffffffff
++#define gcvMINUINT64 0x8000000000000000
++#define gcvMAXUINTPTR_T (~(gctUINTPTR_T)0)
++
++typedef float gctFLOAT;
++typedef signed int gctFIXED_POINT;
++typedef float * gctFLOAT_PTR;
++
++typedef void * gctPHYS_ADDR;
++typedef void * gctHANDLE;
++typedef void * gctFILE;
++typedef void * gctSIGNAL;
++typedef void * gctWINDOW;
++typedef void * gctIMAGE;
++typedef void * gctSYNC_POINT;
++typedef void * gctSHBUF;
++
++typedef void * gctSEMAPHORE;
++
++typedef void * gctPOINTER;
++typedef const void * gctCONST_POINTER;
++
++typedef char gctCHAR;
++typedef char * gctSTRING;
++typedef const char * gctCONST_STRING;
++
++typedef struct _gcsCOUNT_STRING
++{
++ gctSIZE_T Length;
++ gctCONST_STRING String;
++}
++gcsCOUNT_STRING;
++
++typedef union _gcuFLOAT_UINT32
++{
++ gctFLOAT f;
++ gctUINT32 u;
++}
++gcuFLOAT_UINT32;
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++
++
++#define gcmFIXEDCLAMP_NEG1_TO_1(_x) \
++ (((_x) < gcvNEGONE_X) \
++ ? gcvNEGONE_X \
++ : (((_x) > gcvONE_X) \
++ ? gcvONE_X \
++ : (_x)))
++
++#define gcmFLOATCLAMP_NEG1_TO_1(_f) \
++ (((_f) < -1.0f) \
++ ? -1.0f \
++ : (((_f) > 1.0f) \
++ ? 1.0f \
++ : (_f)))
++
++
++#define gcmFIXEDCLAMP_0_TO_1(_x) \
++ (((_x) < 0) \
++ ? 0 \
++ : (((_x) > gcvONE_X) \
++ ? gcvONE_X \
++ : (_x)))
++
++#define gcmFLOATCLAMP_0_TO_1(_f) \
++ (((_f) < 0.0f) \
++ ? 0.0f \
++ : (((_f) > 1.0f) \
++ ? 1.0f \
++ : (_f)))
++
++
++/******************************************************************************\
++******************************* Multicast Values *******************************
++\******************************************************************************/
++
++/* Value types. */
++typedef enum _gceVALUE_TYPE
++{
++ gcvVALUE_UINT = 0x0,
++ gcvVALUE_FIXED,
++ gcvVALUE_FLOAT,
++ gcvVALUE_INT,
++
++ /*
++ ** The value need be unsigned denormalized. clamp (0.0-1.0) should be done first.
++ */
++ gcvVALUE_FLAG_UNSIGNED_DENORM = 0x00010000,
++
++ /*
++ ** The value need be signed denormalized. clamp (-1.0-1.0) should be done first.
++ */
++ gcvVALUE_FLAG_SIGNED_DENORM = 0x00020000,
++
++ /*
++ ** The value need to gammar
++ */
++ gcvVALUE_FLAG_GAMMAR = 0x00040000,
++
++ /*
++ ** The value need to convert from float to float16
++ */
++ gcvVALUE_FLAG_FLOAT_TO_FLOAT16 = 0x0080000,
++
++ /*
++ ** Mask for flag field.
++ */
++ gcvVALUE_FLAG_MASK = 0xFFFF0000,
++}
++gceVALUE_TYPE;
++
++/* Value unions. */
++typedef union _gcuVALUE
++{
++ gctUINT uintValue;
++ gctFIXED_POINT fixedValue;
++ gctFLOAT floatValue;
++ gctINT intValue;
++}
++gcuVALUE;
++
++
++
++
++/* Stringizing macro. */
++#define gcmSTRING(Value) #Value
++
++/******************************************************************************\
++******************************* Fixed Point Math *******************************
++\******************************************************************************/
++
++#define gcmXMultiply(x1, x2) gcoMATH_MultiplyFixed(x1, x2)
++#define gcmXDivide(x1, x2) gcoMATH_DivideFixed(x1, x2)
++#define gcmXMultiplyDivide(x1, x2, x3) gcoMATH_MultiplyDivideFixed(x1, x2, x3)
++
++/* 2D Engine profile. */
++typedef struct _gcs2D_PROFILE
++{
++ /* Cycle count.
++ 32bit counter incremented every 2D clock cycle.
++ Wraps back to 0 when the counter overflows.
++ */
++ gctUINT32 cycleCount;
++
++ /* Pixels rendered by the 2D engine.
++ Resets to 0 every time it is read. */
++ gctUINT32 pixelsRendered;
++}
++gcs2D_PROFILE;
++
++/* Macro to combine four characters into a Charcater Code. */
++#define gcmCC(c1, c2, c3, c4) \
++( \
++ (char) (c1) \
++ | \
++ ((char) (c2) << 8) \
++ | \
++ ((char) (c3) << 16) \
++ | \
++ ((char) (c4) << 24) \
++)
++
++#define gcmPRINTABLE(c) ((((c) >= ' ') && ((c) <= '}')) ? ((c) != '%' ? (c) : ' ') : ' ')
++
++#define gcmCC_PRINT(cc) \
++ gcmPRINTABLE((char) ( (cc) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 8) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 16) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 24) & 0xFF))
++
++/******************************************************************************\
++****************************** Function Parameters *****************************
++\******************************************************************************/
++
++#define IN
++#define OUT
++#define INOUT
++#define OPTIONAL
++
++/******************************************************************************\
++********************************* Status Codes *********************************
++\******************************************************************************/
++
++typedef enum _gceSTATUS
++{
++ gcvSTATUS_OK = 0,
++ gcvSTATUS_FALSE = 0,
++ gcvSTATUS_TRUE = 1,
++ gcvSTATUS_NO_MORE_DATA = 2,
++ gcvSTATUS_CACHED = 3,
++ gcvSTATUS_MIPMAP_TOO_LARGE = 4,
++ gcvSTATUS_NAME_NOT_FOUND = 5,
++ gcvSTATUS_NOT_OUR_INTERRUPT = 6,
++ gcvSTATUS_MISMATCH = 7,
++ gcvSTATUS_MIPMAP_TOO_SMALL = 8,
++ gcvSTATUS_LARGER = 9,
++ gcvSTATUS_SMALLER = 10,
++ gcvSTATUS_CHIP_NOT_READY = 11,
++ gcvSTATUS_NEED_CONVERSION = 12,
++ gcvSTATUS_SKIP = 13,
++ gcvSTATUS_DATA_TOO_LARGE = 14,
++ gcvSTATUS_INVALID_CONFIG = 15,
++ gcvSTATUS_CHANGED = 16,
++ gcvSTATUS_NOT_SUPPORT_DITHER = 17,
++ gcvSTATUS_EXECUTED = 18,
++ gcvSTATUS_TERMINATE = 19,
++
++ gcvSTATUS_INVALID_ARGUMENT = -1,
++ gcvSTATUS_INVALID_OBJECT = -2,
++ gcvSTATUS_OUT_OF_MEMORY = -3,
++ gcvSTATUS_MEMORY_LOCKED = -4,
++ gcvSTATUS_MEMORY_UNLOCKED = -5,
++ gcvSTATUS_HEAP_CORRUPTED = -6,
++ gcvSTATUS_GENERIC_IO = -7,
++ gcvSTATUS_INVALID_ADDRESS = -8,
++ gcvSTATUS_CONTEXT_LOSSED = -9,
++ gcvSTATUS_TOO_COMPLEX = -10,
++ gcvSTATUS_BUFFER_TOO_SMALL = -11,
++ gcvSTATUS_INTERFACE_ERROR = -12,
++ gcvSTATUS_NOT_SUPPORTED = -13,
++ gcvSTATUS_MORE_DATA = -14,
++ gcvSTATUS_TIMEOUT = -15,
++ gcvSTATUS_OUT_OF_RESOURCES = -16,
++ gcvSTATUS_INVALID_DATA = -17,
++ gcvSTATUS_INVALID_MIPMAP = -18,
++ gcvSTATUS_NOT_FOUND = -19,
++ gcvSTATUS_NOT_ALIGNED = -20,
++ gcvSTATUS_INVALID_REQUEST = -21,
++ gcvSTATUS_GPU_NOT_RESPONDING = -22,
++ gcvSTATUS_TIMER_OVERFLOW = -23,
++ gcvSTATUS_VERSION_MISMATCH = -24,
++ gcvSTATUS_LOCKED = -25,
++ gcvSTATUS_INTERRUPTED = -26,
++ gcvSTATUS_DEVICE = -27,
++ gcvSTATUS_NOT_MULTI_PIPE_ALIGNED = -28,
++
++ /* Linker errors. */
++ gcvSTATUS_GLOBAL_TYPE_MISMATCH = -1000,
++ gcvSTATUS_TOO_MANY_ATTRIBUTES = -1001,
++ gcvSTATUS_TOO_MANY_UNIFORMS = -1002,
++ gcvSTATUS_TOO_MANY_VARYINGS = -1003,
++ gcvSTATUS_UNDECLARED_VARYING = -1004,
++ gcvSTATUS_VARYING_TYPE_MISMATCH = -1005,
++ gcvSTATUS_MISSING_MAIN = -1006,
++ gcvSTATUS_NAME_MISMATCH = -1007,
++ gcvSTATUS_INVALID_INDEX = -1008,
++ gcvSTATUS_UNIFORM_MISMATCH = -1009,
++ gcvSTATUS_UNSAT_LIB_SYMBOL = -1010,
++ gcvSTATUS_TOO_MANY_SHADERS = -1011,
++ gcvSTATUS_LINK_INVALID_SHADERS = -1012,
++ gcvSTATUS_CS_NO_WORKGROUP_SIZE = -1013,
++ gcvSTATUS_LINK_LIB_ERROR = -1014,
++ gcvSTATUS_SHADER_VERSION_MISMATCH = -1015,
++ gcvSTATUS_TOO_MANY_INSTRUCTION = -1016,
++ gcvSTATUS_SSBO_MISMATCH = -1017,
++ gcvSTATUS_TOO_MANY_OUTPUT = -1018,
++ gcvSTATUS_TOO_MANY_INPUT = -1019,
++ gcvSTATUS_NOT_SUPPORT_CL = -1020,
++ gcvSTATUS_NOT_SUPPORT_INTEGER = -1021,
++ gcvSTATUS_UNIFORM_TYPE_MISMATCH = -1022,
++ gcvSTATUS_TOO_MANY_SAMPLER = -1023,
++
++ /* Compiler errors. */
++ gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR = -2000,
++ gcvSTATUS_COMPILER_FE_PARSER_ERROR = -2001,
++
++ /* Recompilation Errors */
++ gcvSTATUS_RECOMPILER_CONVERT_UNIMPLEMENTED = -3000,
++
++ gcvSTATUS_WARNING = -9999,
++}
++gceSTATUS;
++
++/******************************************************************************\
++********************************* Status Macros ********************************
++\******************************************************************************/
++
++#define gcmIS_ERROR(status) (status < 0)
++#define gcmNO_ERROR(status) (status >= 0)
++#define gcmIS_SUCCESS(status) (status == gcvSTATUS_OK)
++#define gcmIS_WARNING(status) (status == gcvSTATUS_WARNING)
++
++/******************************************************************************\
++********************************* Field Macros *********************************
++\******************************************************************************/
++
++#define __gcmSTART(reg_field) \
++ (0 ? reg_field)
++
++#define __gcmEND(reg_field) \
++ (1 ? reg_field)
++
++#define __gcmGETSIZE(reg_field) \
++ (__gcmEND(reg_field) - __gcmSTART(reg_field) + 1)
++
++#define __gcmALIGN(data, reg_field) \
++ (((gctUINT32) (data)) << __gcmSTART(reg_field))
++
++#define __gcmMASK(reg_field) \
++ ((gctUINT32) ((__gcmGETSIZE(reg_field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg_field)))))
++
++/*******************************************************************************
++**
++** gcmFIELDMASK
++**
++** Get aligned field mask.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMASK(reg, field) \
++( \
++ __gcmALIGN(__gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETFIELD
++**
++** Extract the value of a field from specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETFIELD(data, reg, field) \
++( \
++ ((((gctUINT32) (data)) >> __gcmSTART(reg##_##field)) \
++ & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELD
++**
++** Set the value of a field within specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETFIELD(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN((gctUINT32) (value) \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELDVALUE
++**
++** Set the value of a field within specified data with a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmSETFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN(reg##_##field##_##value \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETMASKEDFIELDMASK
++**
++** Determine field mask of a masked field.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETMASKEDFIELDMASK(reg, field) \
++( \
++ gcmSETFIELD(0, reg, field, ~0) | \
++ gcmSETFIELD(0, reg, MASK_ ## field, ~0) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELD
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELD(reg, field, value) \
++( \
++ gcmSETFIELD (~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELDVALUE
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELDVALUE(reg, field, value) \
++( \
++ gcmSETFIELDVALUE(~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDVALUE
++**
++** Verify if the value of a field within specified data equals a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmVERIFYFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) >> __gcmSTART(reg##_##field) & \
++ __gcmMASK(reg##_##field)) \
++ == \
++ (reg##_##field##_##value & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++** Bit field macros.
++*/
++
++#define __gcmSTARTBIT(Field) \
++ ( 1 ? Field )
++
++#define __gcmBITSIZE(Field) \
++ ( 0 ? Field )
++
++#define __gcmBITMASK(Field) \
++( \
++ (1 << __gcmBITSIZE(Field)) - 1 \
++)
++
++#define gcmGETBITS(Value, Type, Field) \
++( \
++ ( ((Type) (Value)) >> __gcmSTARTBIT(Field) ) \
++ & \
++ __gcmBITMASK(Field) \
++)
++
++#define gcmSETBITS(Value, Type, Field, NewValue) \
++( \
++ ( ((Type) (Value)) \
++ & ~(__gcmBITMASK(Field) << __gcmSTARTBIT(Field)) \
++ ) \
++ | \
++ ( ( ((Type) (NewValue)) \
++ & __gcmBITMASK(Field) \
++ ) << __gcmSTARTBIT(Field) \
++ ) \
++)
++
++/*******************************************************************************
++**
++** gcmISINREGRANGE
++**
++** Verify whether the specified address is in the register range.
++**
++** ARGUMENTS:
++**
++** Address Address to be verified.
++** Name Name of a register.
++*/
++
++#define gcmISINREGRANGE(Address, Name) \
++( \
++ ((Address & (~0U << Name ## _LSB)) == (Name ## _Address >> 2)) \
++)
++
++/******************************************************************************\
++******************************** Ceiling Macro ********************************
++\******************************************************************************/
++#define gcmCEIL(x) ((x - (gctUINT32)x) == 0 ? (gctUINT32)x : (gctUINT32)x + 1)
++
++/******************************************************************************\
++******************************** Min/Max Macros ********************************
++\******************************************************************************/
++
++#define gcmMIN(x, y) (((x) <= (y)) ? (x) : (y))
++#define gcmMAX(x, y) (((x) >= (y)) ? (x) : (y))
++#define gcmCLAMP(x, min, max) (((x) < (min)) ? (min) : \
++ ((x) > (max)) ? (max) : (x))
++#define gcmABS(x) (((x) < 0) ? -(x) : (x))
++#define gcmNEG(x) (((x) < 0) ? (x) : -(x))
++
++/******************************************************************************\
++******************************** Bit Macro ********************************
++\******************************************************************************/
++#define gcmBITSET(x, y) ((x) & (y))
++/*******************************************************************************
++**
++** gcmPTR2INT
++**
++** Convert a pointer to an integer value.
++**
++** ARGUMENTS:
++**
++** p Pointer value.
++*/
++#define gcmPTR2INT(p) \
++( \
++ (gctUINTPTR_T) (p) \
++)
++
++#define gcmPTR2INT32(p) \
++( \
++ (gctUINT32)(gctUINTPTR_T) (p) \
++)
++
++/*******************************************************************************
++**
++** gcmINT2PTR
++**
++** Convert an integer value into a pointer.
++**
++** ARGUMENTS:
++**
++** v Integer value.
++*/
++
++#define gcmINT2PTR(i) \
++( \
++ (gctPOINTER) (gctUINTPTR_T)(i) \
++)
++
++/*******************************************************************************
++**
++** gcmOFFSETOF
++**
++** Compute the byte offset of a field inside a structure.
++**
++** ARGUMENTS:
++**
++** s Structure name.
++** field Field name.
++*/
++#define gcmOFFSETOF(s, field) \
++( \
++ gcmPTR2INT32(& (((struct s *) 0)->field)) \
++)
++
++/*******************************************************************************
++**
++** gcmSWAB32
++**
++** Return a value with all bytes in the 32 bit argument swapped.
++*/
++#define gcmSWAB32(x) ((gctUINT32)( \
++ (((gctUINT32)(x) & (gctUINT32)0x000000FFUL) << 24) | \
++ (((gctUINT32)(x) & (gctUINT32)0x0000FF00UL) << 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0x00FF0000UL) >> 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0xFF000000UL) >> 24)))
++
++/*******************************************************************************
++***** Database ****************************************************************/
++
++typedef struct _gcsDATABASE_COUNTERS
++{
++ /* Number of currently allocated bytes. */
++ gctUINT64 bytes;
++
++ /* Maximum number of bytes allocated (memory footprint). */
++ gctUINT64 maxBytes;
++
++ /* Total number of bytes allocated. */
++ gctUINT64 totalBytes;
++}
++gcsDATABASE_COUNTERS;
++
++typedef struct _gcuDATABASE_INFO
++{
++ /* Counters. */
++ gcsDATABASE_COUNTERS counters;
++
++ /* Time value. */
++ gctUINT64 time;
++}
++gcuDATABASE_INFO;
++
++/*******************************************************************************
++***** Frame database **********************************************************/
++
++/* gcsHAL_FRAME_INFO */
++typedef struct _gcsHAL_FRAME_INFO
++{
++ /* Current timer tick. */
++ OUT gctUINT64 ticks;
++
++ /* Bandwidth counters. */
++ OUT gctUINT readBytes8[8];
++ OUT gctUINT writeBytes8[8];
++
++ /* Counters. */
++ OUT gctUINT cycles[8];
++ OUT gctUINT idleCycles[8];
++ OUT gctUINT mcCycles[8];
++ OUT gctUINT readRequests[8];
++ OUT gctUINT writeRequests[8];
++
++ /* 3D counters. */
++ OUT gctUINT vertexCount;
++ OUT gctUINT primitiveCount;
++ OUT gctUINT rejectedPrimitives;
++ OUT gctUINT culledPrimitives;
++ OUT gctUINT clippedPrimitives;
++ OUT gctUINT outPrimitives;
++ OUT gctUINT inPrimitives;
++ OUT gctUINT culledQuadCount;
++ OUT gctUINT totalQuadCount;
++ OUT gctUINT quadCount;
++ OUT gctUINT totalPixelCount;
++
++ /* PE counters. */
++ OUT gctUINT colorKilled[8];
++ OUT gctUINT colorDrawn[8];
++ OUT gctUINT depthKilled[8];
++ OUT gctUINT depthDrawn[8];
++
++ /* Shader counters. */
++ OUT gctUINT shaderCycles;
++ OUT gctUINT vsInstructionCount;
++ OUT gctUINT vsTextureCount;
++ OUT gctUINT psInstructionCount;
++ OUT gctUINT psTextureCount;
++
++ /* Texture counters. */
++ OUT gctUINT bilinearRequests;
++ OUT gctUINT trilinearRequests;
++ OUT gctUINT txBytes8;
++ OUT gctUINT txHitCount;
++ OUT gctUINT txMissCount;
++}
++gcsHAL_FRAME_INFO;
++
++#if gcdLINK_QUEUE_SIZE
++typedef struct _gckLINKDATA * gckLINKDATA;
++struct _gckLINKDATA
++{
++ gctUINT32 start;
++ gctUINT32 end;
++ gctUINT32 pid;
++};
++
++typedef struct _gckLINKQUEUE * gckLINKQUEUE;
++struct _gckLINKQUEUE
++{
++ struct _gckLINKDATA data[gcdLINK_QUEUE_SIZE];
++ gctUINT32 rear;
++ gctUINT32 front;
++ gctUINT32 count;
++};
++#endif
++
++#define gcdENTRY_QUEUE_SIZE 256
++typedef struct _gckENTRYDATA * gckENTRYDATA;
++struct _gckENTRYDATA
++{
++ gctUINT32 physical;
++ gctUINT32 bytes;
++};
++
++typedef struct _gckENTRYQUEUE * gckENTRYQUEUE;
++struct _gckENTRYQUEUE
++{
++ struct _gckENTRYDATA data[gcdENTRY_QUEUE_SIZE];
++ gctUINT32 rear;
++ gctUINT32 front;
++ gctUINT32 count;
++};
++
++typedef enum _gceTRACEMODE
++{
++ gcvTRACEMODE_NONE = 0,
++ gcvTRACEMODE_FULL = 1,
++ gcvTRACEMODE_LOGGER = 2,
++ gcvTRACEMODE_PRE = 3,
++ gcvTRACEMODE_POST = 4,
++ gcvTRACEMODE_SYSTRACE = 5,
++
++} gceTRACEMODE;
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_types_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_version.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_version.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_version.h 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,39 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_version_h_
++#define __gc_hal_version_h_
++
++#define gcvVERSION_MAJOR 5
++
++#define gcvVERSION_MINOR 0
++
++#define gcvVERSION_PATCH 11
++
++#define gcvVERSION_BUILD 25762
++
++#define gcvVERSION_STRING "5.0.11.p4.25762"
++
++#define gcvVERSION_DATE __DATE__
++
++#define gcvVERSION_TIME __TIME__
++
++#endif /* __gc_hal_version_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_vg.h linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_vg.h
+--- linux-3.14.72.orig/drivers/gpu/galcore/inc/gc_hal_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/inc/gc_hal_vg.h 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,863 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_vg_h_
++#define __gc_hal_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++
++#if gcdENABLE_VG
++
++/* Thread routine type. */
++typedef gctINT gctTHREADFUNCRESULT;
++typedef gctPOINTER gctTHREADFUNCPARAMETER;
++#define gctTHREADFUNCTYPE
++
++typedef gctTHREADFUNCRESULT (gctTHREADFUNCTYPE * gctTHREADFUNC) (
++ gctTHREADFUNCPARAMETER ThreadParameter
++ );
++
++
++#if defined(gcvDEBUG)
++# undef gcvDEBUG
++#endif
++
++#define gcdFORCE_DEBUG 0
++#define gcdFORCE_MESSAGES 0
++
++
++#if defined(DEBUG)
++# define gcvDEBUG 1
++#else
++# define gcvDEBUG 0
++#endif
++
++#define _gcmERROR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++
++#define gcmERROR_RETURN(func) _gcmERROR_RETURN(gcm, func)
++
++#define gcmLOG_LOCATION()
++
++#define gcmkIS_ERROR(status) (status < 0)
++
++#define gcmALIGNDOWN(n, align) \
++( \
++ (n) & ~((align) - 1) \
++)
++
++#define gcmIS_VALID_INDEX(Index, Array) \
++ (((gctUINT) (Index)) < gcmCOUNTOF(Array))
++
++
++#define gcmIS_NAN(x) \
++( \
++ ((* (gctUINT32_PTR) &(x)) & 0x7FFFFFFF) == 0x7FFFFFFF \
++)
++
++#define gcmLERP(v1, v2, w) \
++ ((v1) * (w) + (v2) * (1.0f - (w)))
++
++#define gcmINTERSECT(Start1, Start2, Length) \
++ (gcmABS((Start1) - (Start2)) < (Length))
++
++/*******************************************************************************
++**
++** gcmERR_GOTO
++**
++** Prints a message and terminates the current loop on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** Function
++** Function to evaluate.
++*/
++
++#define gcmERR_GOTO(Function) \
++ status = Function; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmERR_GOTO: status=%d @ line=%d in function %s.\n", \
++ status, __LINE__, __FUNCTION__ \
++ ); \
++ goto ErrorHandler; \
++ }
++
++#if gcvDEBUG || gcdFORCE_MESSAGES
++# define gcmVERIFY_BOOLEAN(Expression) \
++ gcmASSERT( \
++ ( (Expression) == gcvFALSE ) || \
++ ( (Expression) == gcvTRUE ) \
++ )
++#else
++# define gcmVERIFY_BOOLEAN(Expression)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDFIT
++**
++** Verify whether the value fits in the field.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmVERIFYFIELDFIT(reg, field, value) \
++ gcmASSERT( \
++ (value) <= gcmFIELDMAX(reg, field) \
++ )
++/*******************************************************************************
++**
++** gcmFIELDMAX
++**
++** Get field maximum value.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMAX(reg, field) \
++( \
++ (gctUINT32) \
++ ( \
++ (__gcmGETSIZE(reg##_##field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg##_##field))) \
++ ) \
++)
++
++
++/* ANSI C does not have the 'f' functions, define replacements here. */
++#define gcmSINF(x) ((gctFLOAT) sin(x))
++#define gcmCOSF(x) ((gctFLOAT) cos(x))
++#define gcmASINF(x) ((gctFLOAT) asin(x))
++#define gcmACOSF(x) ((gctFLOAT) acos(x))
++#define gcmSQRTF(x) ((gctFLOAT) sqrt(x))
++#define gcmFABSF(x) ((gctFLOAT) fabs(x))
++#define gcmFMODF(x, y) ((gctFLOAT) fmod((x), (y)))
++#define gcmCEILF(x) ((gctFLOAT) ceil(x))
++#define gcmFLOORF(x) ((gctFLOAT) floor(x))
++
++
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++/* Integer constants. */
++#define gcvMAX_POS_INT ((gctINT) 0x7FFFFFFF)
++#define gcvMAX_NEG_INT ((gctINT) 0x80000000)
++
++/* Float constants. */
++#define gcvMAX_POS_FLOAT ((gctFLOAT) 3.4028235e+038)
++#define gcvMAX_NEG_FLOAT ((gctFLOAT) -3.4028235e+038)
++
++/******************************************************************************\
++***************************** Miscellaneous Macro ******************************
++\******************************************************************************/
++
++#define gcmKB2BYTES(Kilobyte) \
++( \
++ (Kilobyte) << 10 \
++)
++
++#define gcmMB2BYTES(Megabyte) \
++( \
++ (Megabyte) << 20 \
++)
++
++#define gcmMAT(Matrix, Row, Column) \
++( \
++ (Matrix) [(Row) * 3 + (Column)] \
++)
++
++#define gcmMAKE2CHAR(Char1, Char2) \
++( \
++ ((gctUINT16) (gctUINT8) (Char1) << 0) | \
++ ((gctUINT16) (gctUINT8) (Char2) << 8) \
++)
++
++#define gcmMAKE4CHAR(Char1, Char2, Char3, Char4) \
++( \
++ ((gctUINT32)(gctUINT8) (Char1) << 0) | \
++ ((gctUINT32)(gctUINT8) (Char2) << 8) | \
++ ((gctUINT32)(gctUINT8) (Char3) << 16) | \
++ ((gctUINT32)(gctUINT8) (Char4) << 24) \
++)
++
++/* some platforms need to fix the physical address for HW to access*/
++#define gcmFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++#define gcmkFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++/******************************************************************************\
++****************************** Kernel Debug Macro ******************************
++\******************************************************************************/
++
++/* Set signal to signaled state for specified process. */
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----------------------------- Semaphore Object -----------------------------*/
++
++/* Increment the value of a semaphore. */
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++/* Decrement the value of a semaphore (waiting might occur). */
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- Thread Object ------------------------------*/
++
++/* Start a thread. */
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ );
++
++/* Stop a thread. */
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++/* Verify whether the thread is still running. */
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++
++/* Construct a new gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ );
++
++/* Destroy an gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ );
++
++/* Allocate linear video memory. */
++gceSTATUS
++gckVGKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++/******************************************************************************\
++******************************* gckVGHARDWARE Object ******************************
++\******************************************************************************/
++
++/* Construct a new gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ );
++
++/* Destroy an gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures1
++ );
++
++/* Convert an API format. */
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Align size to tile boundary. */
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Get idle register. */
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckVGHARDWARE_Flush(
++ IN gckVGHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ );
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++/******************************************************************************\
++*************************** Command Buffer Structures **************************
++\******************************************************************************/
++
++/* Vacant command buffer marker. */
++#define gcvVACANT_BUFFER ((gcsCOMPLETION_SIGNAL_PTR) ((gctSIZE_T)1))
++
++/* Command buffer header. */
++typedef struct _gcsCMDBUFFER * gcsCMDBUFFER_PTR;
++typedef struct _gcsCMDBUFFER
++{
++ /* Pointer to the completion signal. */
++ gcsCOMPLETION_SIGNAL_PTR completion;
++
++ /* The user sets this to the node of the container buffer whitin which
++ this particular command buffer resides. The kernel sets this to the
++ node of the internally allocated buffer. */
++ gcuVIDMEM_NODE_PTR node;
++
++ /* Command buffer hardware address. */
++ gctUINT32 address;
++
++ /* The offset of the buffer from the beginning of the header. */
++ gctUINT32 bufferOffset;
++
++ /* Size of the area allocated for the data portion of this particular
++ command buffer (headers and tail reserves are excluded). */
++ gctUINT32 size;
++
++ /* Offset into the buffer [0..size]; reflects exactly how much data has
++ been put into the command buffer. */
++ gctUINT offset;
++
++ /* The number of command units in the buffer for the hardware to
++ execute. */
++ gctUINT32 dataCount;
++
++ /* MANAGED BY : user HAL (gcoBUFFER object).
++ USED BY : user HAL (gcoBUFFER object).
++ Points to the immediate next allocated command buffer. */
++ gcsCMDBUFFER_PTR nextAllocated;
++
++ /* MANAGED BY : user layers (HAL and drivers).
++ USED BY : kernel HAL (gcoBUFFER object).
++ Points to the next subbuffer if any. A family of subbuffers are chained
++ together and are meant to be executed inseparably as a unit. Meaning
++ that context switching cannot occur while a chain of subbuffers is being
++ executed. */
++ gcsCMDBUFFER_PTR nextSubBuffer;
++}
++gcsCMDBUFFER;
++
++/* Command queue element. */
++typedef struct _gcsVGCMDQUEUE
++{
++ /* Pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Dynamic vs. static command buffer state. */
++ gctBOOL dynamic;
++}
++gcsVGCMDQUEUE;
++
++/* Context map entry. */
++typedef struct _gcsVGCONTEXT_MAP
++{
++ /* State index. */
++ gctUINT32 index;
++
++ /* New state value. */
++ gctUINT32 data;
++
++ /* Points to the next entry in the mod list. */
++ gcsVGCONTEXT_MAP_PTR next;
++}
++gcsVGCONTEXT_MAP;
++
++/* gcsVGCONTEXT structure that holds the current context. */
++typedef struct _gcsVGCONTEXT
++{
++ /* Context ID. */
++ gctUINT64 id;
++
++ /* State caching ebable flag. */
++ gctBOOL stateCachingEnabled;
++
++ /* Current pipe. */
++ gctUINT32 currentPipe;
++
++ /* State map/mod buffer. */
++ gctUINT32 mapFirst;
++ gctUINT32 mapLast;
++ gcsVGCONTEXT_MAP_PTR mapContainer;
++ gcsVGCONTEXT_MAP_PTR mapPrev;
++ gcsVGCONTEXT_MAP_PTR mapCurr;
++ gcsVGCONTEXT_MAP_PTR firstPrevMap;
++ gcsVGCONTEXT_MAP_PTR firstCurrMap;
++
++ /* Main context buffer. */
++ gcsCMDBUFFER_PTR header;
++ gctUINT32_PTR buffer;
++
++ /* Completion signal. */
++ gctHANDLE process;
++ gctSIGNAL signal;
++}
++gcsVGCONTEXT;
++
++/* User space task header. */
++typedef struct _gcsTASK * gcsTASK_PTR;
++typedef struct _gcsTASK
++{
++ /* Pointer to the next task for the same interrupt in user space. */
++ gcsTASK_PTR next;
++
++ /* Size of the task data that immediately follows the structure. */
++ gctUINT size;
++
++ /* Task data starts here. */
++ /* ... */
++}
++gcsTASK;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_ENTRY * gcsTASK_MASTER_ENTRY_PTR;
++typedef struct _gcsTASK_MASTER_ENTRY
++{
++ /* Pointers to the head and to the tail of the task chain. */
++ gcsTASK_PTR head;
++ gcsTASK_PTR tail;
++}
++gcsTASK_MASTER_ENTRY;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_TABLE
++{
++ /* Table with one entry per block. */
++ gcsTASK_MASTER_ENTRY table[gcvBLOCK_COUNT];
++
++ /* The total number of tasks sckeduled. */
++ gctUINT count;
++
++ /* The total size of event data in bytes. */
++ gctUINT size;
++}
++gcsTASK_MASTER_TABLE;
++
++/******************************************************************************\
++***************************** gckVGINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVGINTERRUPT * gckVGINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckVGKERNEL Kernel
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++typedef struct _gckVGCOMMAND * gckVGCOMMAND;
++
++/* Construct a new gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ );
++
++/* Destroy an gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ IN gckVGCOMMAND Command
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++/* Allocate a command queue. */
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ );
++
++/* Release memory held by the command queue. */
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Schedule the command queue for execution. */
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Commit a buffer to the command queue. */
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ );
++
++/******************************************************************************\
++********************************* gckVGMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckVGMMU * gckVGMMU;
++
++/* Construct a new gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT32 MmuSize,
++ OUT gckVGMMU * Mmu
++ );
++
++/* Destroy an gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++/* Flush MMU */
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ );
++
++#endif /* gcdENABLE_VG */
++
++#ifdef __cplusplus
++} /* extern "C" */
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/Kbuild linux-3.14.72/drivers/gpu/galcore/Kbuild
+--- linux-3.14.72.orig/drivers/gpu/galcore/Kbuild 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/Kbuild 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,233 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2014 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++#
++# Linux build file for kernel HAL driver.
++#
++
++AQROOT := $(srctree)/drivers/gpu/galcore
++
++include $(AQROOT)/config
++
++KERNEL_DIR ?= $(TOOL_DIR)/kernel
++
++# Check and include platform config.
++ifneq ($(PLATFORM),)
++
++# Get platform config path.
++PLATFORM_CONFIG ?= $(AQROOT)/platform/$(PLATFORM).config
++
++# Check whether it exists.
++PLATFORM_CONFIG := $(wildcard $(PLATFORM_CONFIG))
++
++# Include it if exists.
++ifneq ($(PLATFORM_CONFIG),)
++include $(PLATFORM_CONFIG)
++endif
++
++endif
++
++MODULE_NAME ?= galcore
++CUSTOMER_ALLOCATOR_OBJS ?=
++ALLOCATOR_ARRAY_H_LOCATION ?= allocator/default/
++
++#EXTRA_CFLAGS += -Werror
++
++OBJS := gc_hal_kernel_device.o \
++ gc_hal_kernel_linux.o \
++ gc_hal_kernel_math.o \
++ gc_hal_kernel_os.o \
++ gc_hal_kernel_debugfs.o \
++ gc_hal_kernel_allocator.o \
++
++ifneq ($(CONFIG_IOMMU_SUPPORT),)
++OBJS += gc_hal_kernel_iommu.o
++endif
++
++OBJS += gc_hal_kernel_probe.o
++ifneq ($(PLATFORM),)
++OBJS += platform/$(PLATFORM).o
++endif
++
++OBJS += gc_hal_kernel.o \
++ gc_hal_kernel_command.o \
++ gc_hal_kernel_db.o \
++ gc_hal_kernel_debug.o \
++ gc_hal_kernel_event.o \
++ gc_hal_kernel_mmu.o \
++ gc_hal_kernel_video_memory.o \
++ gc_hal_kernel_power.o \
++
++OBJS += arch/gc_hal_kernel_context.o \
++ arch/gc_hal_kernel_hardware.o
++
++ifeq ($(VIVANTE_ENABLE_3D), 1)
++OBJS += arch/gc_hal_kernel_recorder.o
++endif
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++OBJS +=\
++ gc_hal_kernel_vg.o \
++ gc_hal_kernel_command_vg.o \
++ gc_hal_kernel_interrupt_vg.o \
++ gc_hal_kernel_mmu_vg.o \
++ archvg/gc_hal_kernel_hardware_command_vg.o \
++ archvg/gc_hal_kernel_hardware_vg.o
++endif
++
++ifneq ($(CONFIG_SYNC),)
++EXTRA_CFLAGS += -Idrivers/staging/android
++
++OBJS += gc_hal_kernel_sync.o
++endif
++
++ifneq ($(CUSTOMER_ALLOCATOR_OBJS),)
++OBJS += $(CUSTOMER_ALLOCATOR_OBJS)
++endif
++
++ifeq ($(KERNELRELEASE), )
++
++.PHONY: all clean install
++
++# Define targets.
++all:
++ @make V=$(V) ARCH=$(ARCH_TYPE) -C $(KERNEL_DIR) SUBDIRS=`pwd` modules
++
++clean:
++ @rm -rf $(OBJS)
++ @rm -rf modules.order Module.symvers
++ @find $(AQROOT) -name ".gc_*.cmd" | xargs rm -f
++
++install: all
++ @mkdir -p $(SDK_DIR)/drivers
++
++else
++
++
++EXTRA_CFLAGS += -DLINUX -DDRIVER
++
++ifeq ($(DEBUG), 1)
++EXTRA_CFLAGS += -DDEBUG=1
++else
++EXTRA_CFLAGS += -DDEBUG=0
++endif
++
++ifeq ($(NO_DMA_COHERENT), 1)
++EXTRA_CFLAGS += -DNO_DMA_COHERENT
++endif
++
++ifneq ($(USE_PLATFORM_DRIVER), 0)
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1
++else
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0
++endif
++
++EXTRA_CFLAGS += -DVIVANTE_PROFILER=1
++EXTRA_CFLAGS += -DVIVANTE_PROFILER_CONTEXT=1
++
++ifeq ($(ENABLE_GPU_CLOCK_BY_DRIVER), 1)
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=1
++else
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=0
++endif
++
++ifeq ($(FORCE_ALL_VIDEO_MEMORY_CACHED), 1)
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_CACHEABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_BUFFERABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=0
++endif
++
++ifeq ($(CACHE_FUNCTION_UNIMPLEMENTED), 1)
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=1
++else
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=0
++endif
++
++ifeq ($(CONFIG_SMP), y)
++EXTRA_CFLAGS += -DgcdSMP=1
++else
++EXTRA_CFLAGS += -DgcdSMP=0
++endif
++
++ifeq ($(VIVANTE_ENABLE_3D),0)
++EXTRA_CFLAGS += -DgcdENABLE_3D=0
++else
++EXTRA_CFLAGS += -DgcdENABLE_3D=1
++endif
++
++ifeq ($(VIVANTE_ENABLE_2D),0)
++EXTRA_CFLAGS += -DgcdENABLE_2D=0
++else
++EXTRA_CFLAGS += -DgcdENABLE_2D=1
++endif
++
++ifeq ($(VIVANTE_ENABLE_VG),0)
++EXTRA_CFLAGS += -DgcdENABLE_VG=0
++else
++EXTRA_CFLAGS += -DgcdENABLE_VG=1
++endif
++
++ifeq ($(USE_BANK_ALIGNMENT), 1)
++ EXTRA_CFLAGS += -DgcdENABLE_BANK_ALIGNMENT=1
++ ifneq ($(BANK_BIT_START), 0)
++ ifneq ($(BANK_BIT_END), 0)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_START=$(BANK_BIT_START)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_END=$(BANK_BIT_END)
++ endif
++ endif
++
++ ifneq ($(BANK_CHANNEL_BIT), 0)
++ EXTRA_CFLAGS += -DgcdBANK_CHANNEL_BIT=$(BANK_CHANNEL_BIT)
++ endif
++endif
++
++ifeq ($(gcdFPGA_BUILD), 1)
++EXTRA_CFLAGS += -DgcdFPGA_BUILD=1
++else
++EXTRA_CFLAGS += -DgcdFPGA_BUILD=0
++endif
++
++EXTRA_CFLAGS += -I$(AQROOT)
++EXTRA_CFLAGS += -I$(AQROOT)/arch
++EXTRA_CFLAGS += -I$(AQROOT)/inc
++EXTRA_CFLAGS += -I$(AQROOT)/$(ALLOCATOR_ARRAY_H_LOCATION)
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++EXTRA_CFLAGS += -I$(AQROOT)/archvg
++endif
++
++obj-$(CONFIG_VIVANTE_GALCORE) += galcore.o
++
++galcore-objs := $(OBJS)
++
++endif
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/Kconfig linux-3.14.72/drivers/gpu/galcore/Kconfig
+--- linux-3.14.72.orig/drivers/gpu/galcore/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/Kconfig 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,8 @@
++menu "Vivante GPU support"
++
++config VIVANTE_GALCORE
++ tristate "Vivante GPU support"
++ ---help---
++ Say Y to get the GPU driver support.
++
++endmenu
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c linux-3.14.72/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c
+--- linux-3.14.72.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,692 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_platform.h"
++#include "gc_hal_kernel_device.h"
++#include "gc_hal_driver.h"
++#include <linux/slab.h>
++
++#if USE_PLATFORM_DRIVER
++# include <linux/platform_device.h>
++#endif
++
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/clk.h>
++#include <linux/regulator/consumer.h>
++
++#include <linux/busfreq-imx6.h>
++
++#ifdef CONFIG_DEVICE_THERMAL
++#include <linux/device_cooling.h>
++#define REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_devfreq_cooling_notifier(a);
++#else
++#define REG_THERMAL_NOTIFIER(a);
++#define UNREG_THERMAL_NOTIFIER(a);
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++static int initgpu3DMinClock = 1;
++module_param(initgpu3DMinClock, int, 0644);
++#endif
++
++struct platform_device *pdevice;
++
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++# include <linux/kernel.h>
++# include <linux/mm.h>
++# include <linux/oom.h>
++# include <linux/sched.h>
++
++struct task_struct *lowmem_deathpending;
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data);
++
++static struct notifier_block task_nb = {
++ .notifier_call = task_notify_func,
++};
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data)
++{
++ struct task_struct *task = data;
++
++ if (task == lowmem_deathpending)
++ lowmem_deathpending = NULL;
++
++ return NOTIFY_OK;
++}
++
++extern struct task_struct *lowmem_deathpending;
++static unsigned long lowmem_deathpending_timeout;
++
++static int force_contiguous_lowmem_shrink(IN gckKERNEL Kernel)
++{
++ struct task_struct *p;
++ struct task_struct *selected = NULL;
++ int tasksize;
++ int ret = -1;
++ int min_adj = 0;
++ int selected_tasksize = 0;
++ int selected_oom_adj;
++ /*
++ * If we already have a death outstanding, then
++ * bail out right away; indicating to vmscan
++ * that we have nothing further to offer on
++ * this pass.
++ *
++ */
++ if (lowmem_deathpending &&
++ time_before_eq(jiffies, lowmem_deathpending_timeout))
++ return 0;
++ selected_oom_adj = min_adj;
++
++ rcu_read_lock();
++ for_each_process(p) {
++ struct mm_struct *mm;
++ struct signal_struct *sig;
++ gcuDATABASE_INFO info;
++ int oom_adj;
++
++ task_lock(p);
++ mm = p->mm;
++ sig = p->signal;
++ if (!mm || !sig) {
++ task_unlock(p);
++ continue;
++ }
++ oom_adj = sig->oom_score_adj;
++ if (oom_adj < min_adj) {
++ task_unlock(p);
++ continue;
++ }
++
++ tasksize = 0;
++ task_unlock(p);
++ rcu_read_unlock();
++
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_VIDEO_MEMORY, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_CONTIGUOUS, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++
++ rcu_read_lock();
++
++ if (tasksize <= 0)
++ continue;
++
++ gckOS_Print("<gpu> pid %d (%s), adj %d, size %d \n", p->pid, p->comm, oom_adj, tasksize);
++
++ if (selected) {
++ if (oom_adj < selected_oom_adj)
++ continue;
++ if (oom_adj == selected_oom_adj &&
++ tasksize <= selected_tasksize)
++ continue;
++ }
++ selected = p;
++ selected_tasksize = tasksize;
++ selected_oom_adj = oom_adj;
++ }
++ if (selected) {
++ gckOS_Print("<gpu> send sigkill to %d (%s), adj %d, size %d\n",
++ selected->pid, selected->comm,
++ selected_oom_adj, selected_tasksize);
++ lowmem_deathpending = selected;
++ lowmem_deathpending_timeout = jiffies + HZ;
++ force_sig(SIGKILL, selected);
++ ret = 0;
++ }
++ rcu_read_unlock();
++ return ret;
++}
++
++
++gceSTATUS
++_ShrinkMemory(
++ IN gckPLATFORM Platform
++ )
++{
++ struct platform_device *pdev;
++ gckGALDEVICE galDevice;
++ gckKERNEL kernel;
++
++ pdev = Platform->device;
++
++ galDevice = platform_get_drvdata(pdev);
++
++ kernel = galDevice->kernels[gcvCORE_MAJOR];
++
++ if (kernel != gcvNULL)
++ {
++ force_contiguous_lowmem_shrink(kernel);
++ }
++ else
++ {
++ gcmkPRINT("%s(%d) can't find kernel! ", __FUNCTION__, __LINE__);
++ }
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++#ifdef CONFIG_DEVICE_THERMAL
++static int thermal_hot_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ static gctUINT orgFscale, minFscale, maxFscale;
++ static gctBOOL critical;
++ gckHARDWARE hardware;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if (!galDevice)
++ {
++ /* GPU is not ready, so it is meaningless to change GPU freq. */
++ return NOTIFY_OK;
++ }
++
++ if (!galDevice->kernels[gcvCORE_MAJOR])
++ {
++ return NOTIFY_OK;
++ }
++
++ hardware = galDevice->kernels[gcvCORE_MAJOR]->hardware;
++
++ if (!hardware)
++ {
++ return NOTIFY_OK;
++ }
++
++ if (event > 4) {
++ critical = gcvTRUE;
++ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
++ gckHARDWARE_SetFscaleValue(hardware, minFscale);
++ gckOS_Print("System is too hot. GPU3D will work at %d/64 clock.\n", minFscale);
++ } else if (event > 1) {
++ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
++ gckHARDWARE_SetFscaleValue(hardware, maxFscale - (8 * event));
++ } else if (orgFscale) {
++ gckHARDWARE_SetFscaleValue(hardware, orgFscale);
++ if (critical) {
++ gckOS_Print("Hot alarm is canceled. GPU3D clock will return to %d/64\n", orgFscale);
++ critical = gcvFALSE;
++ }
++ }
++ return NOTIFY_OK;
++}
++
++static struct notifier_block thermal_hot_pm_notifier = {
++ .notifier_call = thermal_hot_pm_notify,
++ };
++#endif
++
++static ssize_t show_gpu3DMinClock(struct device_driver *dev, char *buf)
++{
++ gctUINT currentf,minf,maxf;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ {
++ gckHARDWARE_GetFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware,
++ &currentf, &minf, &maxf);
++ }
++ snprintf(buf, PAGE_SIZE, "%d\n", minf);
++ return strlen(buf);
++}
++
++static ssize_t update_gpu3DMinClock(struct device_driver *dev, const char *buf, size_t count)
++{
++
++ gctINT fields;
++ gctUINT MinFscaleValue;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ {
++ fields = sscanf(buf, "%d", &MinFscaleValue);
++ if (fields < 1)
++ return -EINVAL;
++
++ gckHARDWARE_SetMinFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware,MinFscaleValue);
++ }
++
++ return count;
++}
++
++static DRIVER_ATTR(gpu3DMinClock, S_IRUGO | S_IWUSR, show_gpu3DMinClock, update_gpu3DMinClock);
++#endif
++
++
++
++
++static const struct of_device_id mxs_gpu_dt_ids[] = {
++ { .compatible = "fsl,imx6q-gpu", },
++ { .compatible = "fsl,imx-gpu-subsystem", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, mxs_gpu_dt_ids);
++
++
++struct contiguous_mem_pool {
++ struct dma_attrs attrs;
++ dma_addr_t phys;
++ void *virt;
++ size_t size;
++};
++
++struct imx_priv {
++ /* Clock management.*/
++ struct clk *clk_3d_core;
++ struct clk *clk_3d_shader;
++ struct clk *clk_3d_axi;
++ struct clk *clk_2d_core;
++ struct clk *clk_2d_axi;
++ struct clk *clk_vg_axi;
++
++ /*Run time pm*/
++ struct device *pmdev;
++ struct contiguous_mem_pool *pool;
++ struct reset_control *rstc[gcdMAX_GPU_COUNT];
++};
++
++static struct imx_priv imxPriv;
++
++gceSTATUS
++gckPLATFORM_AdjustParam(
++ IN gckPLATFORM Platform,
++ OUT gcsMODULE_PARAMETERS *Args
++ )
++{
++ struct resource* res;
++ struct platform_device* pdev = Platform->device;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phys_baseaddr");
++ if (res)
++ Args->baseAddress = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_3d");
++ if (res)
++ Args->irqLine = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_3d");
++ if (res)
++ {
++ Args->registerMemBase = res->start;
++ Args->registerMemSize = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_2d");
++ if (res)
++ Args->irqLine2D = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_2d");
++ if (res)
++ {
++ Args->registerMemBase2D = res->start;
++ Args->registerMemSize2D = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_vg");
++ if (res)
++ Args->irqLineVG = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_vg");
++ if (res)
++ {
++ Args->registerMemBaseVG = res->start;
++ Args->registerMemSizeVG = res->end - res->start + 1;
++ }
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ Args->gpu3DMinClock = initgpu3DMinClock;
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_AllocPriv(
++ IN gckPLATFORM Platform
++ )
++{
++ Platform->priv = &imxPriv;
++
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ task_free_register(&task_nb);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_FreePriv(
++ IN gckPLATFORM Platform
++ )
++{
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ task_free_unregister(&task_nb);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_GetPower(
++ IN gckPLATFORM Platform
++ )
++{
++ struct device* pdev = &Platform->device->dev;
++ struct imx_priv *priv = Platform->priv;
++ struct reset_control *rstc;
++
++#ifdef CONFIG_PM
++ /*Init runtime pm for gpu*/
++ pm_runtime_use_autosuspend(pdev);
++ pm_runtime_set_autosuspend_delay(pdev, 200);
++ pm_runtime_enable(pdev);
++ priv->pmdev = pdev;
++#endif
++
++
++ rstc = devm_reset_control_get(pdev, "gpu3d");
++ priv->rstc[gcvCORE_MAJOR] = IS_ERR(rstc) ? NULL : rstc;
++ rstc = devm_reset_control_get(pdev, "gpu2d");
++ priv->rstc[gcvCORE_2D] = IS_ERR(rstc) ? NULL : rstc;
++ rstc = devm_reset_control_get(pdev, "gpuvg");
++ priv->rstc[gcvCORE_VG] = IS_ERR(rstc) ? NULL : rstc;
++
++ /*Initialize the clock structure*/
++ priv->clk_3d_core = clk_get(pdev, "gpu3d_clk");
++ if (!IS_ERR(priv->clk_3d_core)) {
++ priv->clk_3d_axi = clk_get(pdev, "gpu3d_axi_clk");
++ priv->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(priv->clk_3d_shader)) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ priv->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++ } else {
++ priv->clk_3d_core = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_clk failed, disable 3d!\n");
++ }
++
++ priv->clk_2d_core = clk_get(pdev, "gpu2d_clk");
++ if (IS_ERR(priv->clk_2d_core)) {
++ priv->clk_2d_core = NULL;
++ gckOS_Print("galcore: clk_get 2d core clock failed, disable 2d/vg!\n");
++ } else {
++ priv->clk_2d_axi = clk_get(pdev, "gpu2d_axi_clk");
++ if (IS_ERR(priv->clk_2d_axi)) {
++ priv->clk_2d_axi = NULL;
++ gckOS_Print("galcore: clk_get 2d axi clock failed, disable 2d\n");
++ }
++
++ priv->clk_vg_axi = clk_get(pdev, "openvg_axi_clk");
++ if (IS_ERR(priv->clk_vg_axi)) {
++ priv->clk_vg_axi = NULL;
++ gckOS_Print("galcore: clk_get vg clock failed, disable vg!\n");
++ }
++ }
++
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ pdevice = Platform->device;
++ REG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++ {
++ int ret = 0;
++ ret = driver_create_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock);
++ if(ret)
++ dev_err(&pdevice->dev, "create gpu3DMinClock attr failed (%d)\n", ret);
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_PutPower(
++ IN gckPLATFORM Platform
++ )
++{
++ struct imx_priv *priv = Platform->priv;
++
++ /*Disable clock*/
++ if (priv->clk_3d_axi) {
++ clk_put(priv->clk_3d_axi);
++ priv->clk_3d_axi = NULL;
++ }
++ if (priv->clk_3d_core) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ }
++ if (priv->clk_3d_shader) {
++ clk_put(priv->clk_3d_shader);
++ priv->clk_3d_shader = NULL;
++ }
++ if (priv->clk_2d_core) {
++ clk_put(priv->clk_2d_core);
++ priv->clk_2d_core = NULL;
++ }
++ if (priv->clk_2d_axi) {
++ clk_put(priv->clk_2d_axi);
++ priv->clk_2d_axi = NULL;
++ }
++ if (priv->clk_vg_axi) {
++ clk_put(priv->clk_vg_axi);
++ priv->clk_vg_axi = NULL;
++ }
++
++#ifdef CONFIG_PM
++ if(priv->pmdev)
++ pm_runtime_disable(priv->pmdev);
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++
++ driver_remove_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_SetPower(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ )
++{
++ struct imx_priv* priv = Platform->priv;
++
++ if (Enable)
++ {
++#ifdef CONFIG_PM
++ pm_runtime_get_sync(priv->pmdev);
++#endif
++ }
++ else
++ {
++#ifdef CONFIG_PM
++ pm_runtime_put_sync(priv->pmdev);
++#endif
++ }
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_SetClock(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ )
++{
++ struct imx_priv* priv = Platform->priv;
++ struct clk *clk_3dcore = priv->clk_3d_core;
++ struct clk *clk_3dshader = priv->clk_3d_shader;
++ struct clk *clk_3d_axi = priv->clk_3d_axi;
++ struct clk *clk_2dcore = priv->clk_2d_core;
++ struct clk *clk_2d_axi = priv->clk_2d_axi;
++ struct clk *clk_vg_axi = priv->clk_vg_axi;
++
++
++ if (Enable) {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_prepare(clk_3dcore);
++ clk_enable(clk_3dcore);
++ clk_prepare(clk_3dshader);
++ clk_enable(clk_3dshader);
++ clk_prepare(clk_3d_axi);
++ clk_enable(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_2d_axi);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_vg_axi);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ } else {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_disable(clk_3dshader);
++ clk_unprepare(clk_3dshader);
++ clk_disable(clk_3dcore);
++ clk_unprepare(clk_3dcore);
++ clk_disable(clk_3d_axi);
++ clk_unprepare(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ clk_unprepare(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ clk_unprepare(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++
++ return gcvSTATUS_OK;
++}
++
++#ifdef CONFIG_PM
++static int gpu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int gpu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static struct dev_pm_ops gpu_pm_ops;
++#endif
++
++gceSTATUS
++_AdjustDriver(
++ IN gckPLATFORM Platform
++ )
++{
++ struct platform_driver * driver = Platform->driver;
++ driver->driver.of_match_table = mxs_gpu_dt_ids;
++
++ /* Fill local structure with original value. */
++ memcpy(&gpu_pm_ops, driver->driver.pm, sizeof(struct dev_pm_ops));
++
++ /* Add runtime PM callback. */
++#ifdef CONFIG_PM
++ gpu_pm_ops.runtime_suspend = gpu_runtime_suspend;
++ gpu_pm_ops.runtime_resume = gpu_runtime_resume;
++ gpu_pm_ops.runtime_idle = NULL;
++
++ /* Replace callbacks. */
++ driver->driver.pm = &gpu_pm_ops;
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_Reset(
++ IN gckPLATFORM Platform,
++ gceCORE GPU
++ )
++{
++ struct imx_priv* priv = Platform->priv;
++ struct reset_control *rstc = priv->rstc[GPU];
++ if (rstc)
++ reset_control_reset(rstc);
++ return gcvSTATUS_OK;
++}
++
++gcsPLATFORM_OPERATIONS platformOperations = {
++ .adjustParam = gckPLATFORM_AdjustParam,
++ .allocPriv = _AllocPriv,
++ .freePriv = _FreePriv,
++ .getPower = _GetPower,
++ .putPower = _PutPower,
++ .setPower = _SetPower,
++ .setClock = _SetClock,
++ .adjustDriver = _AdjustDriver,
++ .reset = _Reset,
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ .shrinkMemory = _ShrinkMemory,
++#endif
++};
++
++void
++gckPLATFORM_QueryOperations(
++ IN gcsPLATFORM_OPERATIONS ** Operations
++ )
++{
++ *Operations = &platformOperations;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config linux-3.14.72/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config
+--- linux-3.14.72.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,15 @@
++EXTRA_CFLAGS += -DgcdDEFAULT_CONTIGUOUS_SIZE=134217728
++
++ifneq ($(CONFIG_ANDROID),)
++# build for android
++EXTRA_CFLAGS += -DgcdANDROID_NATIVE_FENCE_SYNC=3
++
++ifeq ($(CONFIG_SYNC),)
++$(warn CONFIG_SYNC is not set in kernel config)
++$(warn Android native fence sync needs CONFIG_SYNC)
++endif
++endif
++
++EXTRA_CFLAGS += -DLINUX_CMA_FSL=1
++ALLOCATOR_ARRAY_H_LOCATION := $(OS_KERNEL_DIR)/allocator/freescale
++CUSTOMER_ALLOCATOR_OBJS := $(ALLOCATOR_ARRAY_H_LOCATION)/gc_hal_kernel_allocator_cma.o
+diff -Nur linux-3.14.72.orig/drivers/gpu/Makefile linux-3.14.72/drivers/gpu/Makefile
+--- linux-3.14.72.orig/drivers/gpu/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/gpu/Makefile 2016-06-19 22:11:55.161149455 +0200
+@@ -1,2 +1,3 @@
+ obj-y += drm/ vga/
+ obj-$(CONFIG_TEGRA_HOST1X) += host1x/
++obj-$(CONFIG_VIVANTE_GALCORE) += galcore/
+diff -Nur linux-3.14.72.orig/drivers/hwmon/Kconfig linux-3.14.72/drivers/hwmon/Kconfig
+--- linux-3.14.72.orig/drivers/hwmon/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/hwmon/Kconfig 2016-06-19 22:11:55.161149455 +0200
+@@ -894,6 +894,15 @@
+ This driver can also be built as a module. If so, the module
+ will be called max1668.
+
++config SENSORS_MAX17135
++ tristate "Maxim MAX17135 EPD temperature sensor"
++ depends on I2C
++ help
++ If you say yes here you get support for MAX17135 PMIC sensor.
++
++ This driver can also be built as a module. If so, the module
++ will be called max17135_sensor.
++
+ config SENSORS_MAX197
+ tristate "Maxim MAX197 and compatibles"
+ help
+@@ -1584,4 +1593,18 @@
+
+ endif # ACPI
+
++config SENSORS_MAG3110
++ tristate "Freescale MAG3110 e-compass sensor"
++ depends on I2C && SYSFS
++ help
++ If you say yes here you get support for the Freescale MAG3110
++ e-compass sensor.
++ This driver can also be built as a module. If so, the module
++ will be called mag3110.
++
++config MXC_MMA8451
++ tristate "MMA8451 device driver"
++ depends on I2C
++ default y
++
+ endif # HWMON
+diff -Nur linux-3.14.72.orig/drivers/hwmon/mag3110.c linux-3.14.72/drivers/hwmon/mag3110.c
+--- linux-3.14.72.orig/drivers/hwmon/mag3110.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/hwmon/mag3110.c 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,644 @@
++/*
++ *
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/irq.h>
++#include <linux/platform_device.h>
++#include <linux/input-polldev.h>
++#include <linux/hwmon.h>
++#include <linux/input.h>
++#include <linux/wait.h>
++#include <linux/workqueue.h>
++#include <linux/of.h>
++#include <linux/regulator/consumer.h>
++
++#define MAG3110_DRV_NAME "mag3110"
++#define MAG3110_ID (0xC4)
++#define MAG3110_XYZ_DATA_LEN (6)
++#define MAG3110_STATUS_ZYXDR (0x08)
++#define MAG3110_IRQ_USED (1)
++#define MAG3110_AC_MASK (0x01)
++#define MAG3110_AC_OFFSET (0)
++#define MAG3110_DR_MODE_MASK (0x7 << 5)
++#define MAG3110_DR_MODE_OFFSET (5)
++
++#define POLL_INTERVAL_MAX (500)
++#define POLL_INTERVAL (100)
++#define INT_TIMEOUT (1000)
++#define DEFAULT_POSITION (2)
++
++/* register enum for mag3110 registers */
++enum {
++ MAG3110_DR_STATUS = 0x00,
++ MAG3110_OUT_X_MSB,
++ MAG3110_OUT_X_LSB,
++ MAG3110_OUT_Y_MSB,
++ MAG3110_OUT_Y_LSB,
++ MAG3110_OUT_Z_MSB,
++ MAG3110_OUT_Z_LSB,
++ MAG3110_WHO_AM_I,
++
++ MAG3110_OFF_X_MSB,
++ MAG3110_OFF_X_LSB,
++ MAG3110_OFF_Y_MSB,
++ MAG3110_OFF_Y_LSB,
++ MAG3110_OFF_Z_MSB,
++ MAG3110_OFF_Z_LSB,
++
++ MAG3110_DIE_TEMP,
++
++ MAG3110_CTRL_REG1 = 0x10,
++ MAG3110_CTRL_REG2,
++};
++
++enum {
++ MAG_STANDBY,
++ MAG_ACTIVED
++};
++
++struct mag3110_data {
++ struct i2c_client *client;
++ struct input_polled_dev *poll_dev;
++ struct device *hwmon_dev;
++ wait_queue_head_t waitq;
++ bool data_ready;
++ u8 ctl_reg1;
++ int active;
++ int position;
++};
++
++static short MAGHAL[8][3][3] = {
++ { {0, 1, 0}, {-1, 0, 0}, {0, 0, 1} },
++ { {1, 0, 0}, {0, 1, 0}, {0, 0, 1} },
++ { {0, -1, 0}, {1, 0, 0}, {0, 0, 1} },
++ { {-1, 0, 0}, {0, -1, 0}, {0, 0, 1} },
++
++ { {0, 1, 0}, {1, 0, 0}, {0, 0, -1} },
++ { {1, 0, 0}, {0, -1, 0}, {0, 0, -1} },
++ { {0, -1, 0}, {-1, 0, 0}, {0, 0, -1} },
++ { {-1, 0, 0}, {0, 1, 0}, {0, 0, -1} },
++};
++
++static struct mag3110_data *mag3110_pdata;
++static DEFINE_MUTEX(mag3110_lock);
++
++/*
++ * This function do one mag3110 register read.
++ */
++static int mag3110_adjust_position(short *x, short *y, short *z)
++{
++ short rawdata[3], data[3];
++ int i, j;
++ int position = mag3110_pdata->position;
++ if (position < 0 || position > 7)
++ position = 0;
++ rawdata[0] = *x;
++ rawdata[1] = *y;
++ rawdata[2] = *z;
++ for (i = 0; i < 3; i++) {
++ data[i] = 0;
++ for (j = 0; j < 3; j++)
++ data[i] += rawdata[j] * MAGHAL[position][i][j];
++ }
++ *x = data[0];
++ *y = data[1];
++ *z = data[2];
++ return 0;
++}
++
++static int mag3110_read_reg(struct i2c_client *client, u8 reg)
++{
++ return i2c_smbus_read_byte_data(client, reg);
++}
++
++/*
++ * This function do one mag3110 register write.
++ */
++static int mag3110_write_reg(struct i2c_client *client, u8 reg, char value)
++{
++ int ret;
++
++ ret = i2c_smbus_write_byte_data(client, reg, value);
++ if (ret < 0)
++ dev_err(&client->dev, "i2c write failed\n");
++ return ret;
++}
++
++/*
++ * This function do multiple mag3110 registers read.
++ */
++static int mag3110_read_block_data(struct i2c_client *client, u8 reg,
++ int count, u8 *addr)
++{
++ if (i2c_smbus_read_i2c_block_data(client, reg, count, addr) < count) {
++ dev_err(&client->dev, "i2c block read failed\n");
++ return -1;
++ }
++
++ return count;
++}
++
++/*
++ * Initialization function
++ */
++static int mag3110_init_client(struct i2c_client *client)
++{
++ int val, ret;
++
++ /* enable automatic resets */
++ val = 0x80;
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG2, val);
++
++ /* set default data rate to 10HZ */
++ val = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ val |= (0x0 << MAG3110_DR_MODE_OFFSET);
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, val);
++
++ return ret;
++}
++
++/*
++ * read sensor data from mag3110
++ */
++static int mag3110_read_data(short *x, short *y, short *z)
++{
++ struct mag3110_data *data;
++ u8 tmp_data[MAG3110_XYZ_DATA_LEN];
++#if !MAG3110_IRQ_USED
++ int retry = 3;
++ int result;
++#endif
++ if (!mag3110_pdata || mag3110_pdata->active == MAG_STANDBY)
++ return -EINVAL;
++
++ data = mag3110_pdata;
++#if MAG3110_IRQ_USED
++ if (!wait_event_interruptible_timeout
++ (data->waitq, data->data_ready != 0,
++ msecs_to_jiffies(INT_TIMEOUT))) {
++ dev_dbg(&data->client->dev, "interrupt not received\n");
++ return -ETIME;
++ }
++#else
++ do {
++ msleep(1);
++ result = i2c_smbus_read_byte_data(data->client,
++ MAG3110_DR_STATUS);
++ retry--;
++ } while (!(result & MAG3110_STATUS_ZYXDR) && retry > 0);
++ /* Clear data_ready flag after data is read out */
++ if (retry == 0)
++ return -EINVAL;
++#endif
++
++ data->data_ready = 0;
++
++ while (i2c_smbus_read_byte_data(data->client, MAG3110_DR_STATUS)) {
++ if (mag3110_read_block_data(data->client,
++ MAG3110_OUT_X_MSB, MAG3110_XYZ_DATA_LEN,
++ tmp_data) < 0)
++ return -1;
++ }
++
++ *x = ((tmp_data[0] << 8) & 0xff00) | tmp_data[1];
++ *y = ((tmp_data[2] << 8) & 0xff00) | tmp_data[3];
++ *z = ((tmp_data[4] << 8) & 0xff00) | tmp_data[5];
++
++ return 0;
++}
++
++static void report_abs(void)
++{
++ struct input_dev *idev;
++ short x, y, z;
++
++ mutex_lock(&mag3110_lock);
++ if (mag3110_read_data(&x, &y, &z) != 0)
++ goto out;
++ mag3110_adjust_position(&x, &y, &z);
++ idev = mag3110_pdata->poll_dev->input;
++ input_report_abs(idev, ABS_X, x);
++ input_report_abs(idev, ABS_Y, y);
++ input_report_abs(idev, ABS_Z, z);
++ input_sync(idev);
++out:
++ mutex_unlock(&mag3110_lock);
++}
++
++static void mag3110_dev_poll(struct input_polled_dev *dev)
++{
++ report_abs();
++}
++
++#if MAG3110_IRQ_USED
++static irqreturn_t mag3110_irq_handler(int irq, void *dev_id)
++{
++ int result;
++ u8 tmp_data[MAG3110_XYZ_DATA_LEN];
++ result = i2c_smbus_read_byte_data(mag3110_pdata->client,
++ MAG3110_DR_STATUS);
++ if (!(result & MAG3110_STATUS_ZYXDR))
++ return IRQ_NONE;
++
++ mag3110_pdata->data_ready = 1;
++
++ if (mag3110_pdata->active == MAG_STANDBY)
++ /*
++ * Since the mode will be changed, sometimes irq will
++ * be handled in StandBy mode because of interrupt latency.
++ * So just clear the interrutp flag via reading block data.
++ */
++ mag3110_read_block_data(mag3110_pdata->client,
++ MAG3110_OUT_X_MSB,
++ MAG3110_XYZ_DATA_LEN, tmp_data);
++ else
++ wake_up_interruptible(&mag3110_pdata->waitq);
++
++ return IRQ_HANDLED;
++}
++#endif
++
++static ssize_t mag3110_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client;
++ int val;
++ mutex_lock(&mag3110_lock);
++ client = mag3110_pdata->client;
++ val = mag3110_read_reg(client, MAG3110_CTRL_REG1) & MAG3110_AC_MASK;
++
++ mutex_unlock(&mag3110_lock);
++ return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t mag3110_enable_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client;
++ int reg, ret;
++ long enable;
++ u8 tmp_data[MAG3110_XYZ_DATA_LEN];
++
++ ret = strict_strtol(buf, 10, &enable);
++ if (ret) {
++ dev_err(dev, "string to long error\n");
++ return ret;
++ }
++
++ mutex_lock(&mag3110_lock);
++ client = mag3110_pdata->client;
++
++ reg = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ if (enable && mag3110_pdata->active == MAG_STANDBY) {
++ reg |= MAG3110_AC_MASK;
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg);
++ if (!ret)
++ mag3110_pdata->active = MAG_ACTIVED;
++ } else if (!enable && mag3110_pdata->active == MAG_ACTIVED) {
++ reg &= ~MAG3110_AC_MASK;
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg);
++ if (!ret)
++ mag3110_pdata->active = MAG_STANDBY;
++ }
++
++ /* Read out MSB data to clear interrupt flag */
++ msleep(100);
++ mag3110_read_block_data(mag3110_pdata->client, MAG3110_OUT_X_MSB,
++ MAG3110_XYZ_DATA_LEN, tmp_data);
++ mutex_unlock(&mag3110_lock);
++ return count;
++}
++
++static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO,
++ mag3110_enable_show, mag3110_enable_store);
++
++static ssize_t mag3110_dr_mode_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client;
++ int val;
++
++ client = mag3110_pdata->client;
++ val = (mag3110_read_reg(client, MAG3110_CTRL_REG1)
++ & MAG3110_DR_MODE_MASK) >> MAG3110_DR_MODE_OFFSET;
++
++ return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t mag3110_dr_mode_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client;
++ int reg, ret;
++ unsigned long val;
++
++ /* This must be done when mag3110 is disabled */
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > 7))
++ return -EINVAL;
++
++ client = mag3110_pdata->client;
++ reg = mag3110_read_reg(client, MAG3110_CTRL_REG1) &
++ ~MAG3110_DR_MODE_MASK;
++ reg |= (val << MAG3110_DR_MODE_OFFSET);
++ /* MAG3110_CTRL_REG1 bit 5-7: data rate mode */
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1, reg);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(dr_mode, S_IWUSR | S_IRUGO,
++ mag3110_dr_mode_show, mag3110_dr_mode_store);
++
++static ssize_t mag3110_position_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int val;
++ mutex_lock(&mag3110_lock);
++ val = mag3110_pdata->position;
++ mutex_unlock(&mag3110_lock);
++ return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t mag3110_position_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ long position;
++ int ret;
++ ret = strict_strtol(buf, 10, &position);
++ if (ret) {
++ dev_err(dev, "string to long error\n");
++ return ret;
++ }
++
++ mutex_lock(&mag3110_lock);
++ mag3110_pdata->position = (int)position;
++ mutex_unlock(&mag3110_lock);
++ return count;
++}
++
++static DEVICE_ATTR(position, S_IWUSR | S_IRUGO,
++ mag3110_position_show, mag3110_position_store);
++
++static struct attribute *mag3110_attributes[] = {
++ &dev_attr_enable.attr,
++ &dev_attr_dr_mode.attr,
++ &dev_attr_position.attr,
++ NULL
++};
++
++static const struct attribute_group mag3110_attr_group = {
++ .attrs = mag3110_attributes,
++};
++
++static int mag3110_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct i2c_adapter *adapter;
++ struct input_dev *idev;
++ struct mag3110_data *data;
++ int ret = 0;
++ struct regulator *vdd, *vdd_io;
++ u32 pos = 0;
++ struct device_node *of_node = client->dev.of_node;
++#if MAG3110_IRQ_USED
++ struct irq_data *irq_data = irq_get_irq_data(client->irq);
++ u32 irq_flag;
++ bool shared_irq = of_property_read_bool(of_node, "shared-interrupt");
++#endif
++ vdd = NULL;
++ vdd_io = NULL;
++
++ vdd = devm_regulator_get(&client->dev, "vdd");
++ if (!IS_ERR(vdd)) {
++ ret = regulator_enable(vdd);
++ if (ret) {
++ dev_err(&client->dev, "vdd set voltage error\n");
++ return ret;
++ }
++ }
++
++ vdd_io = devm_regulator_get(&client->dev, "vddio");
++ if (!IS_ERR(vdd_io)) {
++ ret = regulator_enable(vdd_io);
++ if (ret) {
++ dev_err(&client->dev, "vddio set voltage error\n");
++ return ret;
++ }
++ }
++
++ adapter = to_i2c_adapter(client->dev.parent);
++ if (!i2c_check_functionality(adapter,
++ I2C_FUNC_SMBUS_BYTE |
++ I2C_FUNC_SMBUS_BYTE_DATA |
++ I2C_FUNC_SMBUS_I2C_BLOCK))
++ return -EIO;
++
++ dev_info(&client->dev, "check mag3110 chip ID\n");
++ ret = mag3110_read_reg(client, MAG3110_WHO_AM_I);
++
++ if (MAG3110_ID != ret) {
++ dev_err(&client->dev,
++ "read chip ID 0x%x is not equal to 0x%x!\n", ret,
++ MAG3110_ID);
++ return -EINVAL;
++ }
++ data = kzalloc(sizeof(struct mag3110_data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++ data->client = client;
++ i2c_set_clientdata(client, data);
++ /* Init queue */
++ init_waitqueue_head(&data->waitq);
++
++ data->hwmon_dev = hwmon_device_register(&client->dev);
++ if (IS_ERR(data->hwmon_dev)) {
++ dev_err(&client->dev, "hwmon register failed!\n");
++ ret = PTR_ERR(data->hwmon_dev);
++ goto error_rm_dev_sysfs;
++ }
++
++ /*input poll device register */
++ data->poll_dev = input_allocate_polled_device();
++ if (!data->poll_dev) {
++ dev_err(&client->dev, "alloc poll device failed!\n");
++ ret = -ENOMEM;
++ goto error_rm_hwmon_dev;
++ }
++ data->poll_dev->poll = mag3110_dev_poll;
++ data->poll_dev->poll_interval = POLL_INTERVAL;
++ data->poll_dev->poll_interval_max = POLL_INTERVAL_MAX;
++ idev = data->poll_dev->input;
++ idev->name = MAG3110_DRV_NAME;
++ idev->id.bustype = BUS_I2C;
++ idev->evbit[0] = BIT_MASK(EV_ABS);
++ input_set_abs_params(idev, ABS_X, -15000, 15000, 0, 0);
++ input_set_abs_params(idev, ABS_Y, -15000, 15000, 0, 0);
++ input_set_abs_params(idev, ABS_Z, -15000, 15000, 0, 0);
++ ret = input_register_polled_device(data->poll_dev);
++ if (ret) {
++ dev_err(&client->dev, "register poll device failed!\n");
++ goto error_free_poll_dev;
++ }
++
++ /*create device group in sysfs as user interface */
++ ret = sysfs_create_group(&idev->dev.kobj, &mag3110_attr_group);
++ if (ret) {
++ dev_err(&client->dev, "create device file failed!\n");
++ ret = -EINVAL;
++ goto error_rm_poll_dev;
++ }
++
++#if MAG3110_IRQ_USED
++ irq_flag = irqd_get_trigger_type(irq_data);
++ irq_flag |= IRQF_ONESHOT;
++ if (shared_irq)
++ irq_flag |= IRQF_SHARED;
++ ret = request_threaded_irq(client->irq, NULL, mag3110_irq_handler,
++ irq_flag, client->dev.driver->name, idev);
++ if (ret < 0) {
++ dev_err(&client->dev, "failed to register irq %d!\n",
++ client->irq);
++ goto error_rm_dev_sysfs;
++ }
++#endif
++ /* Initialize mag3110 chip */
++ mag3110_init_client(client);
++ mag3110_pdata = data;
++ mag3110_pdata->active = MAG_STANDBY;
++ ret = of_property_read_u32(of_node, "position", &pos);
++ if (ret)
++ pos = DEFAULT_POSITION;
++ mag3110_pdata->position = (int)pos;
++ dev_info(&client->dev, "mag3110 is probed\n");
++ return 0;
++error_rm_dev_sysfs:
++ sysfs_remove_group(&client->dev.kobj, &mag3110_attr_group);
++error_rm_poll_dev:
++ input_unregister_polled_device(data->poll_dev);
++error_free_poll_dev:
++ input_free_polled_device(data->poll_dev);
++error_rm_hwmon_dev:
++ hwmon_device_unregister(data->hwmon_dev);
++
++ kfree(data);
++ mag3110_pdata = NULL;
++
++ return ret;
++}
++
++static int mag3110_remove(struct i2c_client *client)
++{
++ struct mag3110_data *data;
++ int ret;
++
++ data = i2c_get_clientdata(client);
++
++ data->ctl_reg1 = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1,
++ data->ctl_reg1 & ~MAG3110_AC_MASK);
++
++ free_irq(client->irq, data);
++ input_unregister_polled_device(data->poll_dev);
++ input_free_polled_device(data->poll_dev);
++ hwmon_device_unregister(data->hwmon_dev);
++ sysfs_remove_group(&client->dev.kobj, &mag3110_attr_group);
++ kfree(data);
++ mag3110_pdata = NULL;
++
++ return ret;
++}
++
++#ifdef CONFIG_PM
++static int mag3110_suspend(struct i2c_client *client, pm_message_t mesg)
++{
++ int ret = 0;
++ struct mag3110_data *data = i2c_get_clientdata(client);
++ if (data->active == MAG_ACTIVED) {
++ data->ctl_reg1 = mag3110_read_reg(client, MAG3110_CTRL_REG1);
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1,
++ data->ctl_reg1 & ~MAG3110_AC_MASK);
++ }
++ return ret;
++}
++
++static int mag3110_resume(struct i2c_client *client)
++{
++ int ret = 0;
++ u8 tmp_data[MAG3110_XYZ_DATA_LEN];
++ struct mag3110_data *data = i2c_get_clientdata(client);
++ if (data->active == MAG_ACTIVED) {
++ ret = mag3110_write_reg(client, MAG3110_CTRL_REG1,
++ data->ctl_reg1);
++
++ if (data->ctl_reg1 & MAG3110_AC_MASK) {
++ /* Read out MSB data to clear interrupt
++ flag automatically */
++ mag3110_read_block_data(client, MAG3110_OUT_X_MSB,
++ MAG3110_XYZ_DATA_LEN, tmp_data);
++ }
++ }
++ return ret;
++}
++
++#else
++#define mag3110_suspend NULL
++#define mag3110_resume NULL
++#endif /* CONFIG_PM */
++
++static const struct i2c_device_id mag3110_id[] = {
++ {MAG3110_DRV_NAME, 0},
++ {}
++};
++
++MODULE_DEVICE_TABLE(i2c, mag3110_id);
++static struct i2c_driver mag3110_driver = {
++ .driver = {.name = MAG3110_DRV_NAME,
++ .owner = THIS_MODULE,},
++ .suspend = mag3110_suspend,
++ .resume = mag3110_resume,
++ .probe = mag3110_probe,
++ .remove = mag3110_remove,
++ .id_table = mag3110_id,
++};
++
++static int __init mag3110_init(void)
++{
++ return i2c_add_driver(&mag3110_driver);
++}
++
++static void __exit mag3110_exit(void)
++{
++ i2c_del_driver(&mag3110_driver);
++}
++
++module_init(mag3110_init);
++module_exit(mag3110_exit);
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Freescale mag3110 3-axis magnetometer driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/hwmon/Makefile linux-3.14.72/drivers/hwmon/Makefile
+--- linux-3.14.72.orig/drivers/hwmon/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/hwmon/Makefile 2016-06-19 22:11:55.161149455 +0200
+@@ -103,6 +103,7 @@
+ obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
+ obj-$(CONFIG_SENSORS_MAX1619) += max1619.o
+ obj-$(CONFIG_SENSORS_MAX1668) += max1668.o
++obj-$(CONFIG_SENSORS_MAX17135) += max17135-hwmon.o
+ obj-$(CONFIG_SENSORS_MAX197) += max197.o
+ obj-$(CONFIG_SENSORS_MAX6639) += max6639.o
+ obj-$(CONFIG_SENSORS_MAX6642) += max6642.o
+@@ -142,6 +143,8 @@
+ obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o
+ obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o
+ obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o
++obj-$(CONFIG_SENSORS_MAG3110) += mag3110.o
++obj-$(CONFIG_MXC_MMA8451) += mxc_mma8451.o
+
+ obj-$(CONFIG_PMBUS) += pmbus/
+
+diff -Nur linux-3.14.72.orig/drivers/hwmon/max17135-hwmon.c linux-3.14.72/drivers/hwmon/max17135-hwmon.c
+--- linux-3.14.72.orig/drivers/hwmon/max17135-hwmon.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/hwmon/max17135-hwmon.c 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,176 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * max17135.c
++ *
++ * Based on the MAX1619 driver.
++ * Copyright (C) 2003-2004 Alexey Fisher <fishor@mail.ru>
++ * Jean Delvare <khali@linux-fr.org>
++ *
++ * The MAX17135 is a sensor chip made by Maxim.
++ * It reports up to two temperatures (its own plus up to
++ * one external one).
++ */
++
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/jiffies.h>
++#include <linux/hwmon.h>
++#include <linux/hwmon-sysfs.h>
++#include <linux/err.h>
++#include <linux/sysfs.h>
++#include <linux/platform_device.h>
++#include <linux/mfd/max17135.h>
++
++/*
++ * Conversions
++ */
++static int temp_from_reg(int val)
++{
++ return val >> 8;
++}
++
++/*
++ * Functions declaration
++ */
++static int max17135_sensor_probe(struct platform_device *pdev);
++static int max17135_sensor_remove(struct platform_device *pdev);
++
++static const struct platform_device_id max17135_sns_id[] = {
++ { "max17135-sns", 0},
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(platform, max17135_sns_id);
++
++/*
++ * Driver data (common to all clients)
++ */
++static struct platform_driver max17135_sensor_driver = {
++ .probe = max17135_sensor_probe,
++ .remove = max17135_sensor_remove,
++ .id_table = max17135_sns_id,
++ .driver = {
++ .name = "max17135_sensor",
++ },
++};
++
++/*
++ * Client data (each client gets its own)
++ */
++struct max17135_data {
++ struct device *hwmon_dev;
++};
++
++/*
++ * Sysfs stuff
++ */
++static ssize_t show_temp_input1(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ unsigned int reg_val;
++ max17135_reg_read(REG_MAX17135_INT_TEMP, &reg_val);
++ return snprintf(buf, PAGE_SIZE, "%d\n", temp_from_reg(reg_val));
++}
++
++static ssize_t show_temp_input2(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ unsigned int reg_val;
++ max17135_reg_read(REG_MAX17135_EXT_TEMP, &reg_val);
++ return snprintf(buf, PAGE_SIZE, "%d\n", temp_from_reg(reg_val));
++}
++
++static DEVICE_ATTR(temp1_input, S_IRUGO, show_temp_input1, NULL);
++static DEVICE_ATTR(temp2_input, S_IRUGO, show_temp_input2, NULL);
++
++static struct attribute *max17135_attributes[] = {
++ &dev_attr_temp1_input.attr,
++ &dev_attr_temp2_input.attr,
++ NULL
++};
++
++static const struct attribute_group max17135_group = {
++ .attrs = max17135_attributes,
++};
++
++/*
++ * Real code
++ */
++static int max17135_sensor_probe(struct platform_device *pdev)
++{
++ struct max17135_data *data;
++ int err;
++
++ data = kzalloc(sizeof(struct max17135_data), GFP_KERNEL);
++ if (!data) {
++ err = -ENOMEM;
++ goto exit;
++ }
++
++ /* Register sysfs hooks */
++ err = sysfs_create_group(&pdev->dev.kobj, &max17135_group);
++ if (err)
++ goto exit_free;
++
++ data->hwmon_dev = hwmon_device_register(&pdev->dev);
++ if (IS_ERR(data->hwmon_dev)) {
++ err = PTR_ERR(data->hwmon_dev);
++ goto exit_remove_files;
++ }
++
++ platform_set_drvdata(pdev, data);
++
++ return 0;
++
++exit_remove_files:
++ sysfs_remove_group(&pdev->dev.kobj, &max17135_group);
++exit_free:
++ kfree(data);
++exit:
++ return err;
++}
++
++static int max17135_sensor_remove(struct platform_device *pdev)
++{
++ struct max17135_data *data = platform_get_drvdata(pdev);
++
++ hwmon_device_unregister(data->hwmon_dev);
++ sysfs_remove_group(&pdev->dev.kobj, &max17135_group);
++
++ kfree(data);
++ return 0;
++}
++
++static int __init sensors_max17135_init(void)
++{
++ return platform_driver_register(&max17135_sensor_driver);
++}
++module_init(sensors_max17135_init);
++
++static void __exit sensors_max17135_exit(void)
++{
++ platform_driver_unregister(&max17135_sensor_driver);
++}
++module_exit(sensors_max17135_exit);
++
++MODULE_DESCRIPTION("MAX17135 sensor driver");
++MODULE_LICENSE("GPL");
++
+diff -Nur linux-3.14.72.orig/drivers/hwmon/mxc_mma8451.c linux-3.14.72/drivers/hwmon/mxc_mma8451.c
+--- linux-3.14.72.orig/drivers/hwmon/mxc_mma8451.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/hwmon/mxc_mma8451.c 2016-06-19 22:11:55.161149455 +0200
+@@ -0,0 +1,730 @@
++/*
++ * mma8451.c - Linux kernel modules for 3-Axis Orientation/Motion
++ * Detection Sensor
++ *
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/pm.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/hwmon-sysfs.h>
++#include <linux/err.h>
++#include <linux/hwmon.h>
++#include <linux/input-polldev.h>
++#include <linux/of.h>
++#include <linux/regulator/consumer.h>
++
++#define MMA8451_I2C_ADDR 0x1C
++#define MMA8451_ID 0x1A
++#define MMA8452_ID 0x2A
++#define MMA8453_ID 0x3A
++#define FXOS8700_ID 0xC7
++
++#define POLL_INTERVAL_MIN 1
++#define POLL_INTERVAL_MAX 500
++#define POLL_INTERVAL 100 /* msecs */
++#define INPUT_FUZZ 32
++#define INPUT_FLAT 32
++#define MODE_CHANGE_DELAY_MS 100
++
++#define MMA8451_STATUS_ZYXDR 0x08
++#define MMA8451_BUF_SIZE 7
++#define DEFAULT_POSITION 0
++
++/* register enum for mma8451 registers */
++enum {
++ MMA8451_STATUS = 0x00,
++ MMA8451_OUT_X_MSB,
++ MMA8451_OUT_X_LSB,
++ MMA8451_OUT_Y_MSB,
++ MMA8451_OUT_Y_LSB,
++ MMA8451_OUT_Z_MSB,
++ MMA8451_OUT_Z_LSB,
++
++ MMA8451_F_SETUP = 0x09,
++ MMA8451_TRIG_CFG,
++ MMA8451_SYSMOD,
++ MMA8451_INT_SOURCE,
++ MMA8451_WHO_AM_I,
++ MMA8451_XYZ_DATA_CFG,
++ MMA8451_HP_FILTER_CUTOFF,
++
++ MMA8451_PL_STATUS,
++ MMA8451_PL_CFG,
++ MMA8451_PL_COUNT,
++ MMA8451_PL_BF_ZCOMP,
++ MMA8451_P_L_THS_REG,
++
++ MMA8451_FF_MT_CFG,
++ MMA8451_FF_MT_SRC,
++ MMA8451_FF_MT_THS,
++ MMA8451_FF_MT_COUNT,
++
++ MMA8451_TRANSIENT_CFG = 0x1D,
++ MMA8451_TRANSIENT_SRC,
++ MMA8451_TRANSIENT_THS,
++ MMA8451_TRANSIENT_COUNT,
++
++ MMA8451_PULSE_CFG,
++ MMA8451_PULSE_SRC,
++ MMA8451_PULSE_THSX,
++ MMA8451_PULSE_THSY,
++ MMA8451_PULSE_THSZ,
++ MMA8451_PULSE_TMLT,
++ MMA8451_PULSE_LTCY,
++ MMA8451_PULSE_WIND,
++
++ MMA8451_ASLP_COUNT,
++ MMA8451_CTRL_REG1,
++ MMA8451_CTRL_REG2,
++ MMA8451_CTRL_REG3,
++ MMA8451_CTRL_REG4,
++ MMA8451_CTRL_REG5,
++
++ MMA8451_OFF_X,
++ MMA8451_OFF_Y,
++ MMA8451_OFF_Z,
++
++ FXOS8700_M_DR_STATUS,
++ FXOS8700_M_OUT_X_MSB,
++ FXOS8700_M_OUT_X_LSB,
++ FXOS8700_M_OUT_Y_MSB,
++ FXOS8700_M_OUT_Y_LSB,
++ FXOS8700_M_OUT_Z_MSB,
++ FXOS8700_M_OUT_Z_LSB,
++
++ FXOS8700_M_CTRL_REG1 = 0x5B,
++
++ MMA8451_REG_END,
++};
++
++/* The sensitivity is represented in counts/g. In 2g mode the
++sensitivity is 1024 counts/g. In 4g mode the sensitivity is 512
++counts/g and in 8g mode the sensitivity is 256 counts/g.
++ */
++enum {
++ MODE_2G = 0,
++ MODE_4G,
++ MODE_8G,
++};
++
++enum {
++ MMA_STANDBY = 0,
++ MMA_ACTIVED,
++};
++
++enum {
++ FXOS_ACCEL_ONLY = 0,
++ FXOS_MAG_ONLY,
++ FXOS_NONE,
++ FXOS_HYBRID,
++};
++
++/* mma8451 status */
++struct mma8451_status {
++ u8 mode;
++ u8 ctl_reg1;
++ int active;
++ int position;
++ int hybrid_mode;
++};
++
++static struct mma8451_status mma_status;
++static struct input_polled_dev *mma8451_idev;
++static struct input_polled_dev *fxos8700_m_idev;
++static struct device *hwmon_dev;
++static struct i2c_client *mma8451_i2c_client;
++static int client_id;
++
++static int senstive_mode = MODE_2G;
++static int ACCHAL[8][3][3] = {
++ { {0, -1, 0}, {1, 0, 0}, {0, 0, 1} },
++ { {-1, 0, 0}, {0, -1, 0}, {0, 0, 1} },
++ { {0, 1, 0}, {-1, 0, 0}, {0, 0, 1} },
++ { {1, 0, 0}, {0, 1, 0}, {0, 0, 1} },
++
++ { {0, -1, 0}, {-1, 0, 0}, {0, 0, -1} },
++ { {-1, 0, 0}, {0, 1, 0}, {0, 0, -1} },
++ { {0, 1, 0}, {1, 0, 0}, {0, 0, -1} },
++ { {1, 0, 0}, {0, -1, 0}, {0, 0, -1} },
++};
++
++static DEFINE_MUTEX(mma8451_lock);
++static int mma8451_adjust_position(short *x, short *y, short *z)
++{
++ short rawdata[3], data[3];
++ int i, j;
++ int position = mma_status.position;
++ if (position < 0 || position > 7)
++ position = 0;
++ rawdata[0] = *x;
++ rawdata[1] = *y;
++ rawdata[2] = *z;
++ for (i = 0; i < 3; i++) {
++ data[i] = 0;
++ for (j = 0; j < 3; j++)
++ data[i] += rawdata[j] * ACCHAL[position][i][j];
++ }
++ *x = data[0];
++ *y = data[1];
++ *z = data[2];
++ return 0;
++}
++
++static int mma8451_change_mode(struct i2c_client *client, int mode)
++{
++ int result;
++
++ mma_status.ctl_reg1 = 0;
++ result = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, 0);
++ if (result < 0)
++ goto out;
++ mma_status.active = MMA_STANDBY;
++
++ if (client_id == FXOS8700_ID) {
++ mma_status.hybrid_mode = FXOS_HYBRID;
++ result = i2c_smbus_write_byte_data(client, FXOS8700_M_CTRL_REG1, FXOS_HYBRID);
++ if (result < 0)
++ goto out;
++ }
++
++ mma_status.mode = mode;
++ result = i2c_smbus_write_byte_data(client, MMA8451_XYZ_DATA_CFG,
++ mode);
++ if (result < 0)
++ goto out;
++ mdelay(MODE_CHANGE_DELAY_MS);
++ mma_status.mode = mode;
++
++ return 0;
++out:
++ dev_err(&client->dev, "error when init mma8451:(%d)", result);
++ return result;
++}
++
++static int mma8451_read_data(struct input_polled_dev *idev,
++ short *x, short *y, short *z)
++{
++ u8 tmp_data[MMA8451_BUF_SIZE];
++ char reg = (idev == mma8451_idev)?MMA8451_OUT_X_MSB:FXOS8700_M_OUT_X_MSB;
++ int ret;
++
++ ret = i2c_smbus_read_i2c_block_data(mma8451_i2c_client,
++ reg, 7, tmp_data);
++ if (ret < MMA8451_BUF_SIZE) {
++ dev_err(&mma8451_i2c_client->dev, "i2c block read failed\n");
++ return -EIO;
++ }
++
++ *x = ((tmp_data[0] << 8) & 0xff00) | tmp_data[1];
++ *y = ((tmp_data[2] << 8) & 0xff00) | tmp_data[3];
++ *z = ((tmp_data[4] << 8) & 0xff00) | tmp_data[5];
++ return 0;
++}
++
++static void report_abs(struct input_polled_dev *idev)
++{
++ short x, y, z;
++ int result;
++ int retry = 3;
++ char reg = (idev == mma8451_idev)?MMA8451_STATUS:FXOS8700_M_DR_STATUS;
++
++ mutex_lock(&mma8451_lock);
++ if (mma_status.active == MMA_STANDBY)
++ goto out;
++ /* wait for the data ready */
++ do {
++ result = i2c_smbus_read_byte_data(mma8451_i2c_client, reg);
++ retry--;
++ msleep(1);
++ } while (!(result & MMA8451_STATUS_ZYXDR) && retry > 0);
++ if (retry == 0)
++ goto out;
++ if (mma8451_read_data(idev, &x, &y, &z) != 0)
++ goto out;
++ mma8451_adjust_position(&x, &y, &z);
++ input_report_abs(idev->input, ABS_X, x);
++ input_report_abs(idev->input, ABS_Y, y);
++ input_report_abs(idev->input, ABS_Z, z);
++ input_sync(idev->input);
++out:
++ mutex_unlock(&mma8451_lock);
++}
++
++static void mma8451_dev_poll(struct input_polled_dev *dev)
++{
++ report_abs(dev);
++}
++
++static ssize_t mma8451_enable_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct input_polled_dev *idev = dev_get_drvdata(dev);
++ struct i2c_client *client;
++ u8 val;
++ int enable = 0;
++
++ mutex_lock(&mma8451_lock);
++ client = mma8451_i2c_client;
++ val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1);
++ if ((val & 0x01) && mma_status.active == MMA_ACTIVED) {
++ if (client_id == FXOS8700_ID) {
++ if (mma_status.hybrid_mode == FXOS_HYBRID)
++ enable = 1;
++ else if (mma_status.hybrid_mode == FXOS_ACCEL_ONLY
++ && idev == mma8451_idev)
++ enable = 1;
++ else if (mma_status.hybrid_mode == FXOS_MAG_ONLY)
++ enable = 1;
++ }
++ else
++ enable = 1;
++ }
++ mutex_unlock(&mma8451_lock);
++ return sprintf(buf, "%d\n", enable);
++}
++
++static ssize_t mma8451_enable_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct input_polled_dev *idev = dev_get_drvdata(dev);
++ struct i2c_client *client;
++ int ret;
++ unsigned long enable;
++ u8 val = 0;
++
++ ret = strict_strtoul(buf, 10, &enable);
++ if (ret) {
++ dev_err(dev, "string transform error\n");
++ return ret;
++ }
++
++ mutex_lock(&mma8451_lock);
++ client = mma8451_i2c_client;
++ enable = (enable > 0) ? 1 : 0;
++ if (client_id == FXOS8700_ID) {
++ val = mma_status.hybrid_mode;
++ if (idev == mma8451_idev) {
++ if (enable) {
++ if (val == FXOS_NONE)
++ val = FXOS_ACCEL_ONLY;
++ else if (val == FXOS_MAG_ONLY)
++ val = FXOS_HYBRID;
++ } else {
++ if (val == FXOS_HYBRID)
++ val = FXOS_MAG_ONLY;
++ else if (val == FXOS_ACCEL_ONLY)
++ val = FXOS_NONE;
++ }
++ } else {
++ if (enable) {
++ if (val == FXOS_NONE)
++ val = FXOS_MAG_ONLY;
++ else if (val == FXOS_ACCEL_ONLY)
++ val = FXOS_HYBRID;
++ } else {
++ if (val == FXOS_HYBRID)
++ val = FXOS_ACCEL_ONLY;
++ else if (val == FXOS_MAG_ONLY)
++ val = FXOS_NONE;
++ }
++ }
++/*
++ if (val != FXOS_NONE) {
++ ret = i2c_smbus_write_byte_data(client,
++ FXOS8700_M_CTRL_REG1, val & 0x03);
++ }
++*/
++ mma_status.hybrid_mode = val;
++ if (mma_status.hybrid_mode == FXOS_NONE)
++ enable = 0;
++ else
++ enable = 1;
++ }
++ if (enable && mma_status.active == MMA_STANDBY) {
++ val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1);
++ ret =
++ i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ val | 0x01);
++ if (!ret)
++ mma_status.active = MMA_ACTIVED;
++
++ } else if (enable == 0 && mma_status.active == MMA_ACTIVED) {
++ val = i2c_smbus_read_byte_data(client, MMA8451_CTRL_REG1);
++ ret =
++ i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ val & 0xFE);
++ if (!ret)
++ mma_status.active = MMA_STANDBY;
++
++ }
++ mutex_unlock(&mma8451_lock);
++ return count;
++}
++
++static ssize_t mma8451_position_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int position = 0;
++ mutex_lock(&mma8451_lock);
++ position = mma_status.position;
++ mutex_unlock(&mma8451_lock);
++ return sprintf(buf, "%d\n", position);
++}
++
++static ssize_t mma8451_position_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ unsigned long position;
++ int ret;
++ ret = strict_strtoul(buf, 10, &position);
++ if (ret) {
++ dev_err(dev, "string transform error\n");
++ return ret;
++ }
++
++ mutex_lock(&mma8451_lock);
++ mma_status.position = (int)position;
++ mutex_unlock(&mma8451_lock);
++ return count;
++}
++
++static ssize_t mma8451_scalemode_show(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ int mode = 0;
++ mutex_lock(&mma8451_lock);
++ mode = (int)mma_status.mode;
++ mutex_unlock(&mma8451_lock);
++
++ return sprintf(buf, "%d\n", mode);
++}
++
++static ssize_t mma8451_scalemode_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ unsigned long mode;
++ int ret, active_save;
++ struct i2c_client *client = mma8451_i2c_client;
++
++ ret = strict_strtoul(buf, 10, &mode);
++ if (ret) {
++ dev_err(dev, "string transform error\n");
++ goto out;
++ }
++
++ if (mode > MODE_8G) {
++ dev_warn(dev, "not supported mode\n");
++ ret = count;
++ goto out;
++ }
++
++ mutex_lock(&mma8451_lock);
++ if (mode == mma_status.mode) {
++ ret = count;
++ goto out_unlock;
++ }
++
++ active_save = mma_status.active;
++ ret = mma8451_change_mode(client, mode);
++ if (ret)
++ goto out_unlock;
++
++ if (active_save == MMA_ACTIVED) {
++ ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1, 1);
++
++ if (ret)
++ goto out_unlock;
++ mma_status.active = active_save;
++ }
++
++out_unlock:
++ mutex_unlock(&mma8451_lock);
++out:
++ return ret;
++}
++
++static DEVICE_ATTR(enable, S_IWUSR | S_IRUGO,
++ mma8451_enable_show, mma8451_enable_store);
++static DEVICE_ATTR(position, S_IWUSR | S_IRUGO,
++ mma8451_position_show, mma8451_position_store);
++static DEVICE_ATTR(scalemode, S_IWUSR | S_IRUGO,
++ mma8451_scalemode_show, mma8451_scalemode_store);
++
++static struct attribute *mma8451_attributes[] = {
++ &dev_attr_enable.attr,
++ &dev_attr_position.attr,
++ &dev_attr_scalemode.attr,
++ NULL
++};
++
++static const struct attribute_group mma8451_attr_group = {
++ .attrs = mma8451_attributes,
++};
++
++static int mma8451_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ int result;
++ struct input_dev *idev;
++ struct i2c_adapter *adapter;
++ u32 pos;
++ struct device_node *of_node = client->dev.of_node;
++ struct regulator *vdd, *vdd_io;
++
++ mma8451_i2c_client = client;
++
++ vdd = devm_regulator_get(&client->dev, "vdd");
++ if (!IS_ERR(vdd)) {
++ result = regulator_enable(vdd);
++ if (result) {
++ dev_err(&client->dev, "vdd set voltage error\n");
++ return result;
++ }
++ }
++
++ vdd_io = devm_regulator_get(&client->dev, "vddio");
++ if (!IS_ERR(vdd_io)) {
++ result = regulator_enable(vdd_io);
++ if (result) {
++ dev_err(&client->dev, "vddio set voltage error\n");
++ return result;
++ }
++ }
++
++ adapter = to_i2c_adapter(client->dev.parent);
++ result = i2c_check_functionality(adapter,
++ I2C_FUNC_SMBUS_BYTE |
++ I2C_FUNC_SMBUS_BYTE_DATA);
++ if (!result)
++ goto err_out;
++
++ client_id = i2c_smbus_read_byte_data(client, MMA8451_WHO_AM_I);
++ if (client_id != MMA8451_ID && client_id != MMA8452_ID
++ && client_id != MMA8453_ID && client_id != FXOS8700_ID) {
++ dev_err(&client->dev,
++ "read chip ID 0x%x is not equal to 0x%x,0x%x,0x%x!\n",
++ result, MMA8451_ID, MMA8452_ID, FXOS8700_ID);
++ result = -EINVAL;
++ goto err_out;
++ }
++
++ /* Initialize the MMA8451 chip */
++ result = mma8451_change_mode(client, senstive_mode);
++ if (result) {
++ dev_err(&client->dev,
++ "error when init mma8451 chip:(%d)\n", result);
++ goto err_out;
++ }
++
++ hwmon_dev = hwmon_device_register(&client->dev);
++ if (!hwmon_dev) {
++ result = -ENOMEM;
++ dev_err(&client->dev, "error when register hwmon device\n");
++ goto err_out;
++ }
++
++ /* create a polled input device for accelerometer */
++ mma8451_idev = input_allocate_polled_device();
++ if (!mma8451_idev) {
++ result = -ENOMEM;
++ dev_err(&client->dev, "alloc poll device failed!\n");
++ goto err_register_polled_device;
++ }
++ mma8451_idev->poll = mma8451_dev_poll;
++ mma8451_idev->poll_interval = POLL_INTERVAL;
++ mma8451_idev->poll_interval_min = POLL_INTERVAL_MIN;
++ mma8451_idev->poll_interval_max = POLL_INTERVAL_MAX;
++ idev = mma8451_idev->input;
++ if (client_id == FXOS8700_ID)
++ idev->name = "mma845x_a";
++ else
++ idev->name = "mma845x";
++ idev->id.bustype = BUS_I2C;
++ idev->evbit[0] = BIT_MASK(EV_ABS);
++
++ input_set_abs_params(idev, ABS_X, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++ input_set_abs_params(idev, ABS_Y, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++ input_set_abs_params(idev, ABS_Z, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++
++ result = input_register_polled_device(mma8451_idev);
++ if (result) {
++ dev_err(&client->dev, "register poll device failed!\n");
++ goto err_register_polled_device;
++ }
++ result = sysfs_create_group(&idev->dev.kobj, &mma8451_attr_group);
++ if (result) {
++ dev_err(&client->dev, "create device file failed!\n");
++ result = -EINVAL;
++ goto err_register_polled_device;
++ }
++
++ /* create a polled input device for magnetometer */
++ if (client_id == FXOS8700_ID) {
++ fxos8700_m_idev = input_allocate_polled_device();
++ if (!fxos8700_m_idev) {
++ result = -ENOMEM;
++ dev_err(&client->dev, "alloc poll device failed!\n");
++ goto err_alloc_poll_device;
++ }
++ fxos8700_m_idev->poll = mma8451_dev_poll;
++ fxos8700_m_idev->poll_interval = POLL_INTERVAL;
++ fxos8700_m_idev->poll_interval_min = POLL_INTERVAL_MIN;
++ fxos8700_m_idev->poll_interval_max = POLL_INTERVAL_MAX;
++ idev = fxos8700_m_idev->input;
++ idev->name = "fxos8700_m";
++ idev->id.bustype = BUS_I2C;
++ idev->evbit[0] = BIT_MASK(EV_ABS);
++
++ input_set_abs_params(idev, ABS_X, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++ input_set_abs_params(idev, ABS_Y, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++ input_set_abs_params(idev, ABS_Z, -8192, 8191, INPUT_FUZZ, INPUT_FLAT);
++
++ result = input_register_polled_device(fxos8700_m_idev);
++ if (result) {
++ dev_err(&client->dev, "register poll device failed!\n");
++ goto err_register_polled_device1;
++ }
++ result = sysfs_create_group(&idev->dev.kobj, &mma8451_attr_group);
++ if (result) {
++ dev_err(&client->dev, "create device file failed!\n");
++ result = -EINVAL;
++ goto err_create_sysfs1;
++ }
++ }
++
++ result = of_property_read_u32(of_node, "position", &pos);
++ if (result)
++ pos = DEFAULT_POSITION;
++ mma_status.position = (int)pos;
++
++ return 0;
++
++err_create_sysfs1:
++ input_unregister_polled_device(fxos8700_m_idev);
++err_register_polled_device1:
++ input_free_polled_device(fxos8700_m_idev);
++err_register_polled_device:
++ input_free_polled_device(mma8451_idev);
++err_alloc_poll_device:
++ hwmon_device_unregister(&client->dev);
++err_out:
++ return result;
++}
++
++static int mma8451_stop_chip(struct i2c_client *client)
++{
++ int ret = 0;
++ if (mma_status.active == MMA_ACTIVED) {
++ mma_status.ctl_reg1 = i2c_smbus_read_byte_data(client,
++ MMA8451_CTRL_REG1);
++ ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ mma_status.ctl_reg1 & 0xFE);
++ }
++ return ret;
++}
++
++static int mma8451_remove(struct i2c_client *client)
++{
++ int ret;
++ ret = mma8451_stop_chip(client);
++
++ if (client_id == FXOS8700_ID) {
++ input_unregister_polled_device(fxos8700_m_idev);
++ input_free_polled_device(fxos8700_m_idev);
++ }
++ input_unregister_polled_device(mma8451_idev);
++ input_free_polled_device(mma8451_idev);
++ hwmon_device_unregister(hwmon_dev);
++
++ return ret;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int mma8451_suspend(struct device *dev)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ return mma8451_stop_chip(client);
++}
++
++static int mma8451_resume(struct device *dev)
++{
++ int ret = 0;
++ struct i2c_client *client = to_i2c_client(dev);
++ if (mma_status.active == MMA_ACTIVED)
++ ret = i2c_smbus_write_byte_data(client, MMA8451_CTRL_REG1,
++ mma_status.ctl_reg1);
++ return ret;
++
++}
++#endif
++
++static const struct i2c_device_id mma8451_id[] = {
++ {"mma8451", 0},
++ { }
++};
++
++MODULE_DEVICE_TABLE(i2c, mma8451_id);
++
++static SIMPLE_DEV_PM_OPS(mma8451_pm_ops, mma8451_suspend, mma8451_resume);
++static struct i2c_driver mma8451_driver = {
++ .driver = {
++ .name = "mma8451",
++ .owner = THIS_MODULE,
++ .pm = &mma8451_pm_ops,
++ },
++ .probe = mma8451_probe,
++ .remove = mma8451_remove,
++ .id_table = mma8451_id,
++};
++
++static int __init mma8451_init(void)
++{
++ /* register driver */
++ int res;
++
++ res = i2c_add_driver(&mma8451_driver);
++ if (res < 0) {
++ printk(KERN_INFO "add mma8451 i2c driver failed\n");
++ return -ENODEV;
++ }
++ return res;
++}
++
++static void __exit mma8451_exit(void)
++{
++ i2c_del_driver(&mma8451_driver);
++}
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MMA8451 3-Axis Orientation/Motion Detection Sensor driver");
++MODULE_LICENSE("GPL");
++
++module_init(mma8451_init);
++module_exit(mma8451_exit);
+diff -Nur linux-3.14.72.orig/drivers/i2c/busses/i2c-imx.c linux-3.14.72/drivers/i2c/busses/i2c-imx.c
+--- linux-3.14.72.orig/drivers/i2c/busses/i2c-imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/i2c/busses/i2c-imx.c 2016-06-19 22:11:55.161149455 +0200
+@@ -261,15 +261,34 @@
+ {
+ unsigned long orig_jiffies = jiffies;
+ unsigned int temp;
++ int successes = 0;
+
+ dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
+
+ while (1) {
+ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
+- if (for_busy && (temp & I2SR_IBB))
+- break;
+- if (!for_busy && !(temp & I2SR_IBB))
+- break;
++
++ /* check for arbitration lost */
++ if (temp & I2SR_IAL) {
++ temp &= ~I2SR_IAL;
++ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
++ return -EAGAIN;
++ }
++
++ if (for_busy) {
++ if (temp & I2SR_IBB) {
++ if (successes++ > 2)
++ break;
++ } else
++ successes = 0 ;
++ }
++ if (!for_busy) {
++ if (!(temp & I2SR_IBB)) {
++ if (successes++ > 2)
++ break;
++ } else
++ successes = 0 ;
++ }
+ if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
+ dev_dbg(&i2c_imx->adapter.dev,
+ "<%s> I2C bus is busy\n", __func__);
+@@ -458,7 +477,7 @@
+ return 0;
+ }
+
+-static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
++static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bool is_lastmsg)
+ {
+ int i, result;
+ unsigned int temp;
+@@ -494,15 +513,30 @@
+ if (result)
+ return result;
+ if (i == (msgs->len - 1)) {
+- /* It must generate STOP before read I2DR to prevent
+- controller from generating another clock cycle */
+- dev_dbg(&i2c_imx->adapter.dev,
+- "<%s> clear MSTA\n", __func__);
+- temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
+- temp &= ~(I2CR_MSTA | I2CR_MTX);
+- imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
+- i2c_imx_bus_busy(i2c_imx, 0);
+- i2c_imx->stopped = 1;
++ if (is_lastmsg) {
++ /*
++ * It must generate STOP before read I2DR to prevent
++ * controller from generating another clock cycle
++ */
++ dev_dbg(&i2c_imx->adapter.dev,
++ "<%s> clear MSTA\n", __func__);
++ temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
++ temp &= ~(I2CR_MSTA | I2CR_MTX);
++ imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
++ i2c_imx_bus_busy(i2c_imx, 0);
++ i2c_imx->stopped = 1;
++ } else {
++ /*
++ * For i2c master receiver repeat restart operation like:
++ * read -> repeat MSTA -> read/write
++ * The controller must set MTX before read the last byte in
++ * the first read operation, otherwise the first read cost
++ * one extra clock cycle.
++ */
++ temp = readb(i2c_imx->base + IMX_I2C_I2CR);
++ temp |= I2CR_MTX;
++ writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
++ }
+ } else if (i == (msgs->len - 2)) {
+ dev_dbg(&i2c_imx->adapter.dev,
+ "<%s> set TXAK\n", __func__);
+@@ -523,6 +557,7 @@
+ {
+ unsigned int i, temp;
+ int result;
++ bool is_lastmsg = false;
+ struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
+
+ dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
+@@ -534,6 +569,9 @@
+
+ /* read/write data */
+ for (i = 0; i < num; i++) {
++ if (i == num - 1)
++ is_lastmsg = true;
++
+ if (i) {
+ dev_dbg(&i2c_imx->adapter.dev,
+ "<%s> repeated start\n", __func__);
+@@ -564,7 +602,7 @@
+ (temp & I2SR_RXAK ? 1 : 0));
+ #endif
+ if (msgs[i].flags & I2C_M_RD)
+- result = i2c_imx_read(i2c_imx, &msgs[i]);
++ result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
+ else
+ result = i2c_imx_write(i2c_imx, &msgs[i]);
+ if (result)
+@@ -634,6 +672,8 @@
+ i2c_imx->adapter.algo = &i2c_imx_algo;
+ i2c_imx->adapter.dev.parent = &pdev->dev;
+ i2c_imx->adapter.nr = pdev->id;
++ i2c_imx->adapter.retries = 500;
++ i2c_imx->adapter.timeout = msecs_to_jiffies(2000);
+ i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
+ i2c_imx->base = base;
+
+diff -Nur linux-3.14.72.orig/drivers/i2c/i2c-core.c linux-3.14.72/drivers/i2c/i2c-core.c
+--- linux-3.14.72.orig/drivers/i2c/i2c-core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/i2c/i2c-core.c 2016-06-19 22:11:55.161149455 +0200
+@@ -42,6 +42,7 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/of_irq.h>
++#include <linux/clk/clk-conf.h>
+ #include <linux/completion.h>
+ #include <linux/hardirq.h>
+ #include <linux/irqflags.h>
+@@ -262,6 +263,10 @@
+ client->flags & I2C_CLIENT_WAKE);
+ dev_dbg(dev, "probe\n");
+
++ status = of_clk_set_defaults(dev->of_node, false);
++ if (status < 0)
++ return status;
++
+ acpi_dev_pm_attach(&client->dev, true);
+ status = driver->probe(client, i2c_match_id(driver->id_table, client));
+ if (status)
+diff -Nur linux-3.14.72.orig/drivers/iio/adc/Kconfig linux-3.14.72/drivers/iio/adc/Kconfig
+--- linux-3.14.72.orig/drivers/iio/adc/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/iio/adc/Kconfig 2016-06-19 22:11:55.161149455 +0200
+@@ -196,6 +196,15 @@
+
+ This driver can also be built as a module. If so, the module will be
+ called twl6030-gpadc.
++config VF610_ADC
++ tristate "Freescale vf610 ADC driver"
++ depends on OF
++ help
++ Say yes here to support for Vybrid board analog-to-digital converter.
++ Since the IP is used for i.MX6SLX, the driver also support i.MX6SLX.
++
++ This driver can also be built as a module. If so, the module will be
++ called vf610_adc.
+
+ config VIPERBOARD_ADC
+ tristate "Viperboard ADC support"
+diff -Nur linux-3.14.72.orig/drivers/iio/adc/Makefile linux-3.14.72/drivers/iio/adc/Makefile
+--- linux-3.14.72.orig/drivers/iio/adc/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/iio/adc/Makefile 2016-06-19 22:11:55.161149455 +0200
+@@ -21,4 +21,5 @@
+ obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
+ obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o
+ obj-$(CONFIG_TWL6030_GPADC) += twl6030-gpadc.o
++obj-$(CONFIG_VF610_ADC) += vf610_adc.o
+ obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o
+diff -Nur linux-3.14.72.orig/drivers/iio/adc/vf610_adc.c linux-3.14.72/drivers/iio/adc/vf610_adc.c
+--- linux-3.14.72.orig/drivers/iio/adc/vf610_adc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/iio/adc/vf610_adc.c 2016-06-19 22:11:55.165149193 +0200
+@@ -0,0 +1,717 @@
++/*
++ * Freescale Vybrid vf610 ADC driver
++ *
++ * Copyright 2013-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/completion.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of_platform.h>
++#include <linux/err.h>
++
++#include <linux/iio/iio.h>
++#include <linux/iio/sysfs.h>
++#include <linux/iio/driver.h>
++
++/* This will be the driver name the kernel reports */
++#define DRIVER_NAME "vf610-adc"
++
++/* Vybrid/IMX ADC registers */
++#define VF610_REG_ADC_HC0 0x00
++#define VF610_REG_ADC_HC1 0x04
++#define VF610_REG_ADC_HS 0x08
++#define VF610_REG_ADC_R0 0x0c
++#define VF610_REG_ADC_R1 0x10
++#define VF610_REG_ADC_CFG 0x14
++#define VF610_REG_ADC_GC 0x18
++#define VF610_REG_ADC_GS 0x1c
++#define VF610_REG_ADC_CV 0x20
++#define VF610_REG_ADC_OFS 0x24
++#define VF610_REG_ADC_CAL 0x28
++#define VF610_REG_ADC_PCTL 0x30
++
++/* Configuration register field define */
++#define VF610_ADC_MODE_BIT8 0x00
++#define VF610_ADC_MODE_BIT10 0x04
++#define VF610_ADC_MODE_BIT12 0x08
++#define VF610_ADC_MODE_MASK 0x0c
++#define VF610_ADC_BUSCLK2_SEL 0x01
++#define VF610_ADC_ALTCLK_SEL 0x02
++#define VF610_ADC_ADACK_SEL 0x03
++#define VF610_ADC_ADCCLK_MASK 0x03
++#define VF610_ADC_CLK_DIV2 0x20
++#define VF610_ADC_CLK_DIV4 0x40
++#define VF610_ADC_CLK_DIV8 0x60
++#define VF610_ADC_CLK_MASK 0x60
++#define VF610_ADC_ADLSMP_LONG 0x10
++#define VF610_ADC_ADSTS_MASK 0x300
++#define VF610_ADC_ADLPC_EN 0x80
++#define VF610_ADC_ADHSC_EN 0x400
++#define VF610_ADC_REFSEL_VALT 0x100
++#define VF610_ADC_REFSEL_VBG 0x1000
++#define VF610_ADC_ADTRG_HARD 0x2000
++#define VF610_ADC_AVGS_8 0x4000
++#define VF610_ADC_AVGS_16 0x8000
++#define VF610_ADC_AVGS_32 0xC000
++#define VF610_ADC_AVGS_MASK 0xC000
++#define VF610_ADC_OVWREN 0x10000
++
++/* General control register field define */
++#define VF610_ADC_ADACKEN 0x1
++#define VF610_ADC_DMAEN 0x2
++#define VF610_ADC_ACREN 0x4
++#define VF610_ADC_ACFGT 0x8
++#define VF610_ADC_ACFE 0x10
++#define VF610_ADC_AVGEN 0x20
++#define VF610_ADC_ADCON 0x40
++#define VF610_ADC_CAL 0x80
++
++/* Other field define */
++#define VF610_ADC_ADCHC(x) ((x) & 0xF)
++#define VF610_ADC_AIEN (0x1 << 7)
++#define VF610_ADC_CONV_DISABLE 0x1F
++#define VF610_ADC_HS_COCO0 0x1
++#define VF610_ADC_CALF 0x2
++#define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
++
++enum clk_sel {
++ VF610_ADCIOC_BUSCLK_SET,
++ VF610_ADCIOC_ALTCLK_SET,
++ VF610_ADCIOC_ADACK_SET,
++};
++
++enum vol_ref {
++ VF610_ADCIOC_VR_VREF_SET,
++ VF610_ADCIOC_VR_VALT_SET,
++ VF610_ADCIOC_VR_VBG_SET,
++};
++
++enum average_sel {
++ VF610_ADC_SAMPLE_1,
++ VF610_ADC_SAMPLE_4,
++ VF610_ADC_SAMPLE_8,
++ VF610_ADC_SAMPLE_16,
++ VF610_ADC_SAMPLE_32,
++};
++
++struct vf610_adc_feature {
++ enum clk_sel clk_sel;
++ enum vol_ref vol_ref;
++
++ int clk_div;
++ int sample_rate;
++ int res_mode;
++
++ bool lpm;
++ bool calibration;
++ bool ovwren;
++};
++
++struct vf610_adc {
++ struct device *dev;
++ void __iomem *regs;
++ struct clk *clk;
++
++ u32 vref_uv;
++ u32 value;
++ struct regulator *vref;
++ struct vf610_adc_feature adc_feature;
++
++ struct completion completion;
++};
++
++#define VF610_ADC_CHAN(_idx, _chan_type) { \
++ .type = (_chan_type), \
++ .indexed = 1, \
++ .channel = (_idx), \
++ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
++ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
++ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
++}
++
++static const struct iio_chan_spec vf610_adc_iio_channels[] = {
++ VF610_ADC_CHAN(0, IIO_VOLTAGE),
++ VF610_ADC_CHAN(1, IIO_VOLTAGE),
++ VF610_ADC_CHAN(2, IIO_VOLTAGE),
++ VF610_ADC_CHAN(3, IIO_VOLTAGE),
++ VF610_ADC_CHAN(4, IIO_VOLTAGE),
++ VF610_ADC_CHAN(5, IIO_VOLTAGE),
++ VF610_ADC_CHAN(6, IIO_VOLTAGE),
++ VF610_ADC_CHAN(7, IIO_VOLTAGE),
++ VF610_ADC_CHAN(8, IIO_VOLTAGE),
++ VF610_ADC_CHAN(9, IIO_VOLTAGE),
++ VF610_ADC_CHAN(10, IIO_VOLTAGE),
++ VF610_ADC_CHAN(11, IIO_VOLTAGE),
++ VF610_ADC_CHAN(12, IIO_VOLTAGE),
++ VF610_ADC_CHAN(13, IIO_VOLTAGE),
++ VF610_ADC_CHAN(14, IIO_VOLTAGE),
++ VF610_ADC_CHAN(15, IIO_VOLTAGE),
++ /* sentinel */
++};
++
++/*
++ * ADC sample frequency, unit is ADCK cycles.
++ * ADC clk source is ipg clock, which is the same as bus clock.
++ *
++ * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
++ * SFCAdder: fixed to 6 ADCK cycles
++ * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
++ * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
++ * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles
++ *
++ * By default, enable 12 bit resolution mode, clock source
++ * set to ipg clock, So get below frequency group:
++ */
++static const u32 vf610_sample_freq_avail[5] =
++{1941176, 559332, 286957, 145374, 73171};
++
++static inline void vf610_adc_cfg_init(struct vf610_adc *info)
++{
++ /* set default Configuration for ADC controller */
++ info->adc_feature.clk_sel = VF610_ADCIOC_BUSCLK_SET;
++ info->adc_feature.vol_ref = VF610_ADCIOC_VR_VREF_SET;
++
++ info->adc_feature.calibration = true;
++ info->adc_feature.ovwren = true;
++
++ info->adc_feature.clk_div = 1;
++ info->adc_feature.res_mode = 12;
++ info->adc_feature.sample_rate = 1;
++ info->adc_feature.lpm = true;
++}
++
++static void vf610_adc_cfg_post_set(struct vf610_adc *info)
++{
++ struct vf610_adc_feature *adc_feature = &info->adc_feature;
++ int cfg_data = 0;
++ int gc_data = 0;
++
++ switch (adc_feature->clk_sel) {
++ case VF610_ADCIOC_ALTCLK_SET:
++ cfg_data |= VF610_ADC_ALTCLK_SEL;
++ break;
++ case VF610_ADCIOC_ADACK_SET:
++ cfg_data |= VF610_ADC_ADACK_SEL;
++ break;
++ default:
++ break;
++ }
++
++ /* low power set for calibration */
++ cfg_data |= VF610_ADC_ADLPC_EN;
++
++ /* enable high speed for calibration */
++ cfg_data |= VF610_ADC_ADHSC_EN;
++
++ /* voltage reference */
++ switch (adc_feature->vol_ref) {
++ case VF610_ADCIOC_VR_VREF_SET:
++ break;
++ case VF610_ADCIOC_VR_VALT_SET:
++ cfg_data |= VF610_ADC_REFSEL_VALT;
++ break;
++ case VF610_ADCIOC_VR_VBG_SET:
++ cfg_data |= VF610_ADC_REFSEL_VBG;
++ break;
++ default:
++ dev_err(info->dev, "error voltage reference\n");
++ }
++
++ /* data overwrite enable */
++ if (adc_feature->ovwren)
++ cfg_data |= VF610_ADC_OVWREN;
++
++ writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
++ writel(gc_data, info->regs + VF610_REG_ADC_GC);
++}
++
++static void vf610_adc_calibration(struct vf610_adc *info)
++{
++ int adc_gc, hc_cfg;
++ int timeout;
++
++ if (!info->adc_feature.calibration)
++ return;
++
++ /* enable calibration interrupt */
++ hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
++ writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
++
++ adc_gc = readl(info->regs + VF610_REG_ADC_GC);
++ writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
++
++ timeout = wait_for_completion_timeout
++ (&info->completion, VF610_ADC_TIMEOUT);
++ if (timeout == 0)
++ dev_err(info->dev, "Timeout for adc calibration\n");
++
++ adc_gc = readl(info->regs + VF610_REG_ADC_GS);
++ if (adc_gc & VF610_ADC_CALF)
++ dev_err(info->dev, "ADC calibration failed\n");
++
++ info->adc_feature.calibration = false;
++}
++
++static void vf610_adc_cfg_set(struct vf610_adc *info)
++{
++ struct vf610_adc_feature *adc_feature = &(info->adc_feature);
++ int cfg_data;
++
++ cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
++
++ /* low power configuration */
++ cfg_data &= ~VF610_ADC_ADLPC_EN;
++ if (adc_feature->lpm)
++ cfg_data |= VF610_ADC_ADLPC_EN;
++
++ /* disable high speed */
++ cfg_data &= ~VF610_ADC_ADHSC_EN;
++
++ writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
++}
++
++static void vf610_adc_sample_set(struct vf610_adc *info)
++{
++ struct vf610_adc_feature *adc_feature = &(info->adc_feature);
++ int cfg_data, gc_data;
++
++ cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
++ gc_data = readl(info->regs + VF610_REG_ADC_GC);
++
++ /* resolution mode */
++ cfg_data &= ~VF610_ADC_MODE_MASK;
++ switch (adc_feature->res_mode) {
++ case 8:
++ cfg_data |= VF610_ADC_MODE_BIT8;
++ break;
++ case 10:
++ cfg_data |= VF610_ADC_MODE_BIT10;
++ break;
++ case 12:
++ cfg_data |= VF610_ADC_MODE_BIT12;
++ break;
++ default:
++ dev_err(info->dev, "error resolution mode\n");
++ break;
++ }
++
++ /* clock select and clock divider */
++ cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
++ switch (adc_feature->clk_div) {
++ case 1:
++ break;
++ case 2:
++ cfg_data |= VF610_ADC_CLK_DIV2;
++ break;
++ case 4:
++ cfg_data |= VF610_ADC_CLK_DIV4;
++ break;
++ case 8:
++ cfg_data |= VF610_ADC_CLK_DIV8;
++ break;
++ case 16:
++ switch (adc_feature->clk_sel) {
++ case VF610_ADCIOC_BUSCLK_SET:
++ cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
++ break;
++ default:
++ dev_err(info->dev, "error clk divider\n");
++ break;
++ }
++ break;
++ }
++
++ /* Use the short sample mode */
++ cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK);
++
++ /* update hardware average selection */
++ cfg_data &= ~VF610_ADC_AVGS_MASK;
++ gc_data &= ~VF610_ADC_AVGEN;
++ switch (adc_feature->sample_rate) {
++ case VF610_ADC_SAMPLE_1:
++ break;
++ case VF610_ADC_SAMPLE_4:
++ gc_data |= VF610_ADC_AVGEN;
++ break;
++ case VF610_ADC_SAMPLE_8:
++ gc_data |= VF610_ADC_AVGEN;
++ cfg_data |= VF610_ADC_AVGS_8;
++ break;
++ case VF610_ADC_SAMPLE_16:
++ gc_data |= VF610_ADC_AVGEN;
++ cfg_data |= VF610_ADC_AVGS_16;
++ break;
++ case VF610_ADC_SAMPLE_32:
++ gc_data |= VF610_ADC_AVGEN;
++ cfg_data |= VF610_ADC_AVGS_32;
++ break;
++ default:
++ dev_err(info->dev,
++ "error hardware sample average select\n");
++ }
++
++ writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
++ writel(gc_data, info->regs + VF610_REG_ADC_GC);
++}
++
++static void vf610_adc_hw_init(struct vf610_adc *info)
++{
++ /* CFG: Feature set */
++ vf610_adc_cfg_post_set(info);
++ vf610_adc_sample_set(info);
++
++ /* adc calibration */
++ vf610_adc_calibration(info);
++
++ /* CFG: power and speed set */
++ vf610_adc_cfg_set(info);
++}
++
++static int vf610_adc_read_data(struct vf610_adc *info)
++{
++ int result;
++
++ result = readl(info->regs + VF610_REG_ADC_R0);
++
++ switch (info->adc_feature.res_mode) {
++ case 8:
++ result &= 0xFF;
++ break;
++ case 10:
++ result &= 0x3FF;
++ break;
++ case 12:
++ result &= 0xFFF;
++ break;
++ default:
++ break;
++ }
++
++ return result;
++}
++
++static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
++{
++ struct vf610_adc *info = (struct vf610_adc *)dev_id;
++ int coco;
++
++ coco = readl(info->regs + VF610_REG_ADC_HS);
++ if (coco & VF610_ADC_HS_COCO0) {
++ info->value = vf610_adc_read_data(info);
++ complete(&info->completion);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1941176, 559332, 286957, 145374, 73171");
++
++static struct attribute *vf610_attributes[] = {
++ &iio_const_attr_sampling_frequency_available.dev_attr.attr,
++ NULL
++};
++
++static const struct attribute_group vf610_attribute_group = {
++ .attrs = vf610_attributes,
++};
++
++static int vf610_read_raw(struct iio_dev *indio_dev,
++ struct iio_chan_spec const *chan,
++ int *val,
++ int *val2,
++ long mask)
++{
++ struct vf610_adc *info = iio_priv(indio_dev);
++ unsigned int hc_cfg;
++ unsigned long ret;
++
++ switch (mask) {
++ case IIO_CHAN_INFO_RAW:
++ mutex_lock(&indio_dev->mlock);
++ reinit_completion(&info->completion);
++
++ hc_cfg = VF610_ADC_ADCHC(chan->channel);
++ hc_cfg |= VF610_ADC_AIEN;
++ writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
++ ret = wait_for_completion_interruptible_timeout
++ (&info->completion, VF610_ADC_TIMEOUT);
++ if (ret == 0) {
++ mutex_unlock(&indio_dev->mlock);
++ return -ETIMEDOUT;
++ }
++ if (ret < 0) {
++ mutex_unlock(&indio_dev->mlock);
++ return ret;
++ }
++
++ *val = info->value;
++ mutex_unlock(&indio_dev->mlock);
++ return IIO_VAL_INT;
++
++ case IIO_CHAN_INFO_SCALE:
++ *val = info->vref_uv / 1000;
++ *val2 = info->adc_feature.res_mode;
++ return IIO_VAL_FRACTIONAL_LOG2;
++
++ case IIO_CHAN_INFO_SAMP_FREQ:
++ *val = vf610_sample_freq_avail[info->adc_feature.sample_rate];
++ *val2 = 0;
++ return IIO_VAL_INT;
++
++ default:
++ break;
++ }
++
++ return -EINVAL;
++}
++
++static int vf610_write_raw(struct iio_dev *indio_dev,
++ struct iio_chan_spec const *chan,
++ int val,
++ int val2,
++ long mask)
++{
++ struct vf610_adc *info = iio_priv(indio_dev);
++ int i;
++
++ switch (mask) {
++ case IIO_CHAN_INFO_SAMP_FREQ:
++ for (i = 0;
++ i < ARRAY_SIZE(vf610_sample_freq_avail);
++ i++)
++ if (val == vf610_sample_freq_avail[i]) {
++ info->adc_feature.sample_rate = i;
++ vf610_adc_sample_set(info);
++ return 0;
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ return -EINVAL;
++}
++
++static int vf610_adc_reg_access(struct iio_dev *indio_dev,
++ unsigned reg, unsigned writeval,
++ unsigned *readval)
++{
++ struct vf610_adc *info = iio_priv(indio_dev);
++
++ if ((readval == NULL) ||
++ (!(reg % 4) || (reg > VF610_REG_ADC_PCTL)))
++ return -EINVAL;
++
++ *readval = readl(info->regs + reg);
++
++ return 0;
++}
++
++static const struct iio_info vf610_adc_iio_info = {
++ .driver_module = THIS_MODULE,
++ .read_raw = &vf610_read_raw,
++ .write_raw = &vf610_write_raw,
++ .debugfs_reg_access = &vf610_adc_reg_access,
++ .attrs = &vf610_attribute_group,
++};
++
++static const struct of_device_id vf610_adc_match[] = {
++ { .compatible = "fsl,vf610-adc", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, vf610_adc_match);
++
++static int vf610_adc_probe(struct platform_device *pdev)
++{
++ struct vf610_adc *info;
++ struct iio_dev *indio_dev;
++ struct resource *mem;
++ int irq;
++ int ret;
++ u32 channels;
++
++ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
++ if (!indio_dev) {
++ dev_err(&pdev->dev, "Failed allocating iio device\n");
++ return -ENOMEM;
++ }
++
++ info = iio_priv(indio_dev);
++ info->dev = &pdev->dev;
++
++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ info->regs = devm_ioremap_resource(&pdev->dev, mem);
++ if (IS_ERR(info->regs))
++ return PTR_ERR(info->regs);
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq <= 0) {
++ dev_err(&pdev->dev, "no irq resource?\n");
++ return -EINVAL;
++ }
++
++ ret = devm_request_irq(info->dev, irq,
++ vf610_adc_isr, 0,
++ dev_name(&pdev->dev), info);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
++ return ret;
++ }
++
++ info->clk = devm_clk_get(&pdev->dev, "adc");
++ if (IS_ERR(info->clk)) {
++ dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
++ PTR_ERR(info->clk));
++ ret = PTR_ERR(info->clk);
++ return ret;
++ }
++
++ info->vref = devm_regulator_get(&pdev->dev, "vref");
++ if (IS_ERR(info->vref))
++ return PTR_ERR(info->vref);
++
++ ret = regulator_enable(info->vref);
++ if (ret)
++ return ret;
++
++ info->vref_uv = regulator_get_voltage(info->vref);
++
++ platform_set_drvdata(pdev, indio_dev);
++
++ init_completion(&info->completion);
++
++ ret = of_property_read_u32(pdev->dev.of_node,
++ "num-channels", &channels);
++ if (ret)
++ channels = ARRAY_SIZE(vf610_adc_iio_channels);
++
++ indio_dev->name = dev_name(&pdev->dev);
++ indio_dev->dev.parent = &pdev->dev;
++ indio_dev->dev.of_node = pdev->dev.of_node;
++ indio_dev->info = &vf610_adc_iio_info;
++ indio_dev->modes = INDIO_DIRECT_MODE;
++ indio_dev->channels = vf610_adc_iio_channels;
++ indio_dev->num_channels = (int)channels;
++
++ ret = clk_prepare_enable(info->clk);
++ if (ret) {
++ dev_err(&pdev->dev,
++ "Could not prepare or enable the clock.\n");
++ goto error_adc_clk_enable;
++ }
++
++ vf610_adc_cfg_init(info);
++ vf610_adc_hw_init(info);
++
++ ret = iio_device_register(indio_dev);
++ if (ret) {
++ dev_err(&pdev->dev, "Couldn't register the device.\n");
++ goto error_iio_device_register;
++ }
++
++ return 0;
++
++
++error_iio_device_register:
++ clk_disable_unprepare(info->clk);
++error_adc_clk_enable:
++ regulator_disable(info->vref);
++
++ return ret;
++}
++
++static int vf610_adc_remove(struct platform_device *pdev)
++{
++ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
++ struct vf610_adc *info = iio_priv(indio_dev);
++
++ iio_device_unregister(indio_dev);
++ regulator_disable(info->vref);
++ clk_disable_unprepare(info->clk);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int vf610_adc_suspend(struct device *dev)
++{
++ struct iio_dev *indio_dev = dev_get_drvdata(dev);
++ struct vf610_adc *info = iio_priv(indio_dev);
++ int hc_cfg;
++
++ /* ADC controller enters to stop mode */
++ hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
++ hc_cfg |= VF610_ADC_CONV_DISABLE;
++ writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
++
++ clk_disable_unprepare(info->clk);
++ regulator_disable(info->vref);
++
++ return 0;
++}
++
++static int vf610_adc_resume(struct device *dev)
++{
++ struct iio_dev *indio_dev = dev_get_drvdata(dev);
++ struct vf610_adc *info = iio_priv(indio_dev);
++ int ret;
++
++ ret = regulator_enable(info->vref);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(info->clk);
++ if (ret)
++ return ret;
++
++ vf610_adc_hw_init(info);
++
++ return 0;
++}
++#endif
++
++static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops,
++ vf610_adc_suspend,
++ vf610_adc_resume);
++
++static struct platform_driver vf610_adc_driver = {
++ .probe = vf610_adc_probe,
++ .remove = vf610_adc_remove,
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = vf610_adc_match,
++ .pm = &vf610_adc_pm_ops,
++ },
++};
++
++module_platform_driver(vf610_adc_driver);
++
++MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
++MODULE_DESCRIPTION("Freescale VF610 ADC driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/iio/gyro/Kconfig linux-3.14.72/drivers/iio/gyro/Kconfig
+--- linux-3.14.72.orig/drivers/iio/gyro/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/iio/gyro/Kconfig 2016-06-19 22:11:55.165149193 +0200
+@@ -93,7 +93,8 @@
+ config ITG3200
+ tristate "InvenSense ITG3200 Digital 3-Axis Gyroscope I2C driver"
+ depends on I2C
+- select IIO_TRIGGERED_BUFFER if IIO_BUFFER
++ select IIO_BUFFER
++ select IIO_TRIGGERED_BUFFER
+ help
+ Say yes here to add support for the InvenSense ITG3200 digital
+ 3-axis gyroscope sensor.
+diff -Nur linux-3.14.72.orig/drivers/input/keyboard/gpio_keys.c linux-3.14.72/drivers/input/keyboard/gpio_keys.c
+--- linux-3.14.72.orig/drivers/input/keyboard/gpio_keys.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/keyboard/gpio_keys.c 2016-06-19 22:11:55.165149193 +0200
+@@ -3,6 +3,7 @@
+ *
+ * Copyright 2005 Phil Blundell
+ * Copyright 2010, 2011 David Jander <david@protonic.nl>
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -473,6 +474,8 @@
+
+ isr = gpio_keys_gpio_isr;
+ irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
++ if (bdata->button->wakeup)
++ irqflags |= IRQF_NO_SUSPEND;
+
+ } else {
+ if (!button->irq) {
+diff -Nur linux-3.14.72.orig/drivers/input/keyboard/imx_keypad.c linux-3.14.72/drivers/input/keyboard/imx_keypad.c
+--- linux-3.14.72.orig/drivers/input/keyboard/imx_keypad.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/keyboard/imx_keypad.c 2016-06-19 22:11:55.165149193 +0200
+@@ -1,6 +1,7 @@
+ /*
+ * Driver for the IMX keypad port.
+ * Copyright (C) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -269,6 +270,7 @@
+ reg_val |= KBD_STAT_KDIE;
+ reg_val &= ~KBD_STAT_KRIE;
+ writew(reg_val, keypad->mmio_base + KPSR);
++ pm_relax(keypad->input_dev->dev.parent);
+ } else {
+ /*
+ * Some keys are still pressed. Schedule a rescan in
+@@ -282,11 +284,6 @@
+ reg_val = readw(keypad->mmio_base + KPSR);
+ reg_val |= KBD_STAT_KPKR | KBD_STAT_KRSS;
+ writew(reg_val, keypad->mmio_base + KPSR);
+-
+- reg_val = readw(keypad->mmio_base + KPSR);
+- reg_val |= KBD_STAT_KRIE;
+- reg_val &= ~KBD_STAT_KDIE;
+- writew(reg_val, keypad->mmio_base + KPSR);
+ }
+ }
+
+@@ -304,6 +301,7 @@
+ writew(reg_val, keypad->mmio_base + KPSR);
+
+ if (keypad->enabled) {
++ pm_stay_awake(keypad->input_dev->dev.parent);
+ /* The matrix is supposed to be changed */
+ keypad->stable_count = 0;
+
+@@ -537,6 +535,7 @@
+ struct platform_device *pdev = to_platform_device(dev);
+ struct imx_keypad *kbd = platform_get_drvdata(pdev);
+ struct input_dev *input_dev = kbd->input_dev;
++ unsigned short reg_val = readw(kbd->mmio_base + KPSR);
+
+ /* imx kbd can wake up system even clock is disabled */
+ mutex_lock(&input_dev->mutex);
+@@ -546,8 +545,15 @@
+
+ mutex_unlock(&input_dev->mutex);
+
+- if (device_may_wakeup(&pdev->dev))
++ if (device_may_wakeup(&pdev->dev)) {
++ if (reg_val & KBD_STAT_KPKD)
++ reg_val |= KBD_STAT_KRIE;
++ if (reg_val & KBD_STAT_KPKR)
++ reg_val |= KBD_STAT_KDIE;
++ writew(reg_val, kbd->mmio_base + KPSR);
++
+ enable_irq_wake(kbd->irq);
++ }
+
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/drivers/input/keyboard/Kconfig linux-3.14.72/drivers/input/keyboard/Kconfig
+--- linux-3.14.72.orig/drivers/input/keyboard/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/keyboard/Kconfig 2016-06-19 22:11:55.165149193 +0200
+@@ -388,6 +388,13 @@
+ To compile this driver as a module, choose M here: the
+ module will be called mpr121_touchkey.
+
++config KEYBOARD_SNVS_PWRKEY
++ tristate "IMX6SX SNVS Power Key Driver"
++ depends on SOC_IMX6SX
++ help
++ This is the snvs powerkey driver for the Freescale i.MX6SX application
++ processors.
++
+ config KEYBOARD_IMX
+ tristate "IMX keypad support"
+ depends on ARCH_MXC
+diff -Nur linux-3.14.72.orig/drivers/input/keyboard/Makefile linux-3.14.72/drivers/input/keyboard/Makefile
+--- linux-3.14.72.orig/drivers/input/keyboard/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/keyboard/Makefile 2016-06-19 22:11:55.165149193 +0200
+@@ -47,6 +47,7 @@
+ obj-$(CONFIG_KEYBOARD_QT2160) += qt2160.o
+ obj-$(CONFIG_KEYBOARD_SAMSUNG) += samsung-keypad.o
+ obj-$(CONFIG_KEYBOARD_SH_KEYSC) += sh_keysc.o
++obj-$(CONFIG_KEYBOARD_SNVS_PWRKEY) += snvs_pwrkey.o
+ obj-$(CONFIG_KEYBOARD_SPEAR) += spear-keyboard.o
+ obj-$(CONFIG_KEYBOARD_STMPE) += stmpe-keypad.o
+ obj-$(CONFIG_KEYBOARD_STOWAWAY) += stowaway.o
+diff -Nur linux-3.14.72.orig/drivers/input/keyboard/snvs_pwrkey.c linux-3.14.72/drivers/input/keyboard/snvs_pwrkey.c
+--- linux-3.14.72.orig/drivers/input/keyboard/snvs_pwrkey.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/input/keyboard/snvs_pwrkey.c 2016-06-19 22:11:55.165149193 +0200
+@@ -0,0 +1,224 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/jiffies.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/platform_device.h>
++
++#define SNVS_LPSR_REG 0x4C /* LP Status Register */
++#define SNVS_LPCR_REG 0x38 /* LP Control Register */
++#define SNVS_HPSR_REG 0x14
++#define SNVS_HPSR_BTN (0x1 << 6)
++#define SNVS_LPSR_SPO (0x1 << 18)
++#define SNVS_LPCR_DEP_EN (0x1 << 5)
++
++struct pwrkey_drv_data {
++ void __iomem *ioaddr;
++ int irq;
++ int keycode;
++ int keystate; /* 1:pressed */
++ int wakeup;
++ struct timer_list check_timer;
++ struct input_dev *input;
++};
++
++static void imx_imx_snvs_check_for_events(unsigned long data)
++{
++ struct pwrkey_drv_data *pdata = (struct pwrkey_drv_data *) data;
++ struct input_dev *input = pdata->input;
++ void __iomem *ioaddr = pdata->ioaddr;
++ u32 state;
++
++ state = ((readl_relaxed(ioaddr + SNVS_HPSR_REG) & SNVS_HPSR_BTN) ?
++ 1 : 0);
++
++ /* only report new event if status changed */
++ if (state ^ pdata->keystate) {
++ pdata->keystate = state;
++ input_event(input, EV_KEY, pdata->keycode, state);
++ input_sync(input);
++ }
++
++ /* repeat check if pressed long */
++ if (state) {
++ mod_timer(&pdata->check_timer,
++ jiffies + msecs_to_jiffies(60));
++ }
++}
++
++static irqreturn_t imx_snvs_pwrkey_interrupt(int irq, void *dev_id)
++{
++ struct platform_device *pdev = dev_id;
++ struct pwrkey_drv_data *pdata = platform_get_drvdata(pdev);
++ void __iomem *ioaddr = pdata->ioaddr;
++ u32 lp_status;
++
++ lp_status = readl_relaxed(ioaddr + SNVS_LPSR_REG);
++ if (lp_status & SNVS_LPSR_SPO)
++ mod_timer(&pdata->check_timer, jiffies + msecs_to_jiffies(2));
++
++ /* clear SPO status */
++ writel_relaxed(lp_status, ioaddr + SNVS_LPSR_REG);
++
++ return IRQ_HANDLED;
++}
++
++static int imx_snvs_pwrkey_probe(struct platform_device *pdev)
++{
++ struct pwrkey_drv_data *pdata = NULL;
++ struct input_dev *input = NULL;
++ struct device_node *np;
++ void __iomem *ioaddr;
++ u32 val;
++ int ret = 0;
++
++ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
++ if (!pdata)
++ return -ENOMEM;
++
++ /* Get SNVS register Page */
++ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-snvs-pwrkey");
++ if (!np)
++ return -ENODEV;
++ pdata->ioaddr = of_iomap(np, 0);
++ if (IS_ERR(pdata->ioaddr))
++ return PTR_ERR(pdata->ioaddr);
++
++ if (of_property_read_u32(np, "fsl,keycode", &pdata->keycode)) {
++ pdata->keycode = KEY_POWER;
++ dev_warn(&pdev->dev, "KEY_POWER without setting in dts\n");
++ }
++
++ pdata->wakeup = !!of_get_property(np, "fsl,wakeup", NULL);
++
++ pdata->irq = platform_get_irq(pdev, 0);
++ if (pdata->irq < 0) {
++ dev_err(&pdev->dev, "no irq defined in platform data\n");
++ return -EINVAL;
++ }
++
++ ioaddr = pdata->ioaddr;
++ val = readl_relaxed(ioaddr + SNVS_LPCR_REG);
++ val |= SNVS_LPCR_DEP_EN,
++ writel_relaxed(val, ioaddr + SNVS_LPCR_REG);
++ /* clear the unexpected interrupt before driver ready */
++ val = readl_relaxed(ioaddr + SNVS_LPSR_REG);
++ if (val & SNVS_LPSR_SPO)
++ writel_relaxed(val | SNVS_LPSR_SPO, ioaddr + SNVS_LPSR_REG);
++
++ setup_timer(&pdata->check_timer,
++ imx_imx_snvs_check_for_events, (unsigned long) pdata);
++
++ if (pdata->irq >= 0) {
++ ret = devm_request_irq(&pdev->dev, pdata->irq,
++ imx_snvs_pwrkey_interrupt,
++ IRQF_TRIGGER_HIGH, pdev->name, pdev);
++ if (ret) {
++ dev_err(&pdev->dev, "interrupt not available.\n");
++ return ret;
++ }
++ }
++
++ input = devm_input_allocate_device(&pdev->dev);
++ if (!input) {
++ dev_err(&pdev->dev, "failed to allocate the input device\n");
++ return -ENOMEM;
++ }
++
++ input->name = pdev->name;
++ input->phys = "snvs-pwrkey/input0";
++ input->id.bustype = BUS_HOST;
++ input->evbit[0] = BIT_MASK(EV_KEY);
++
++ input_set_capability(input, EV_KEY, pdata->keycode);
++
++ ret = input_register_device(input);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to register input device\n");
++ input_free_device(input);
++ return ret;
++ }
++
++ pdata->input = input;
++ platform_set_drvdata(pdev, pdata);
++
++ device_init_wakeup(&pdev->dev, pdata->wakeup);
++
++ dev_info(&pdev->dev, "i.MX snvs powerkey probed\n");
++
++ return 0;
++}
++
++static int imx_snvs_pwrkey_remove(struct platform_device *pdev)
++{
++ struct pwrkey_drv_data *pdata = platform_get_drvdata(pdev);
++
++ input_unregister_device(pdata->input);
++ del_timer_sync(&pdata->check_timer);
++
++ return 0;
++}
++
++static int imx_snvs_pwrkey_suspend(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct pwrkey_drv_data *pdata = platform_get_drvdata(pdev);
++
++ if (device_may_wakeup(&pdev->dev))
++ enable_irq_wake(pdata->irq);
++
++ return 0;
++}
++
++static int imx_snvs_pwrkey_resume(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct pwrkey_drv_data *pdata = platform_get_drvdata(pdev);
++
++ if (device_may_wakeup(&pdev->dev))
++ disable_irq_wake(pdata->irq);
++
++ return 0;
++}
++
++static const struct of_device_id imx_snvs_pwrkey_ids[] = {
++ { .compatible = "fsl,imx6sx-snvs-pwrkey" },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_snvs_pwrkey_ids);
++
++static SIMPLE_DEV_PM_OPS(imx_snvs_pwrkey_pm_ops, imx_snvs_pwrkey_suspend,
++ imx_snvs_pwrkey_resume);
++
++static struct platform_driver imx_snvs_pwrkey_driver = {
++ .driver = {
++ .name = "snvs_pwrkey",
++ .owner = THIS_MODULE,
++ .pm = &imx_snvs_pwrkey_pm_ops,
++ .of_match_table = imx_snvs_pwrkey_ids,
++ },
++ .probe = imx_snvs_pwrkey_probe,
++ .remove = imx_snvs_pwrkey_remove,
++};
++module_platform_driver(imx_snvs_pwrkey_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor");
++MODULE_DESCRIPTION("i.MX snvs power key Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/input/misc/isl29023.c linux-3.14.72/drivers/input/misc/isl29023.c
+--- linux-3.14.72.orig/drivers/input/misc/isl29023.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/input/misc/isl29023.c 2016-06-19 22:11:55.165149193 +0200
+@@ -0,0 +1,1076 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/of.h>
++#include <linux/regulator/consumer.h>
++#include <linux/isl29023.h>
++
++#define ISL29023_DRV_NAME "isl29023"
++#define DRIVER_VERSION "1.0"
++
++#define ISL29023_COMMAND1 (0x00)
++#define ISL29023_MODE_SHIFT (5)
++#define ISL29023_MODE_MASK (0x7 << ISL29023_MODE_SHIFT)
++#define ISL29023_INT_FLAG_SHIFT (2)
++#define ISL29023_INT_FLAG_MASK (0x1 << ISL29023_INT_FLAG_SHIFT)
++#define ISL29023_INT_PERSISTS_SHIFT (0)
++#define ISL29023_INT_PERSISTS_MASK (0x3 << ISL29023_INT_PERSISTS_SHIFT)
++
++#define ISL29023_COMMAND2 (0x01)
++#define ISL29023_RES_SHIFT (2)
++#define ISL29023_RES_MASK (0x3 << ISL29023_RES_SHIFT)
++#define ISL29023_RANGE_SHIFT (0)
++#define ISL29023_RANGE_MASK (0x3 << ISL29023_RANGE_SHIFT)
++
++#define ISL29023_REG_LSB_SENSOR (0x02)
++#define ISL29023_REG_MSB_SENSOR (0x03)
++#define ISL29023_REG_IRQ_TH_LO_LSB (0x04)
++#define ISL29023_REG_IRQ_TH_LO_MSB (0x05)
++#define ISL29023_REG_IRQ_TH_HI_LSB (0x06)
++#define ISL29023_REG_IRQ_TH_HI_MSB (0x07)
++
++#define ISL29023_NUM_CACHABLE_REGS 8
++#define DEF_RANGE 2
++#define DEFAULT_REGISTOR_VAL 499
++
++struct isl29023_data {
++ struct i2c_client *client;
++ struct mutex lock;
++ struct input_dev *input;
++ struct work_struct work;
++ struct workqueue_struct *workqueue;
++ char phys[32];
++ u8 reg_cache[ISL29023_NUM_CACHABLE_REGS];
++ u8 mode_before_suspend;
++ u8 mode_before_interrupt;
++ u16 rext;
++};
++
++static int gain_range[] = {
++ 1000, 4000, 16000, 64000
++};
++
++/*
++ * register access helpers
++ */
++static int __isl29023_read_reg(struct i2c_client *client,
++ u32 reg, u8 mask, u8 shift)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ return (data->reg_cache[reg] & mask) >> shift;
++}
++
++static int __isl29023_write_reg(struct i2c_client *client,
++ u32 reg, u8 mask, u8 shift, u8 val)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int ret = 0;
++ u8 tmp;
++
++ if (reg >= ISL29023_NUM_CACHABLE_REGS)
++ return -EINVAL;
++
++ mutex_lock(&data->lock);
++
++ tmp = data->reg_cache[reg];
++ tmp &= ~mask;
++ tmp |= val << shift;
++
++ ret = i2c_smbus_write_byte_data(client, reg, tmp);
++ if (!ret)
++ data->reg_cache[reg] = tmp;
++
++ mutex_unlock(&data->lock);
++ return ret;
++}
++
++/*
++ * internally used functions
++ */
++static int isl29023_get_int_persists(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_PERSISTS_MASK, ISL29023_INT_PERSISTS_SHIFT);
++}
++
++static int isl29023_set_int_persists(struct i2c_client *client,
++ int int_persists)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_PERSISTS_MASK, ISL29023_INT_PERSISTS_SHIFT,
++ int_persists);
++}
++
++/*
++ * interrupt flag
++ */
++static int isl29023_get_int_flag(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_FLAG_MASK, ISL29023_INT_FLAG_SHIFT);
++}
++
++static int isl29023_set_int_flag(struct i2c_client *client, int flag)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_INT_FLAG_MASK, ISL29023_INT_FLAG_SHIFT, flag);
++}
++
++/*
++ * interrupt lt
++ */
++static int isl29023_get_int_lt(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, lt;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ lt = ((msb << 8) | lsb);
++
++ return lt;
++}
++
++static int isl29023_set_int_lt(struct i2c_client *client, int lt)
++{
++ int ret = 0;
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB,
++ lt & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB,
++ (lt >> 8) & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_MSB] = (lt >> 8) & 0xff;
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_LSB] = lt & 0xff;
++ mutex_unlock(&data->lock);
++
++ return ret;
++}
++
++/*
++ * interrupt ht
++ */
++static int isl29023_get_int_ht(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, ht;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ ht = ((msb << 8) | lsb);
++
++ return ht;
++}
++
++static int isl29023_set_int_ht(struct i2c_client *client, int ht)
++{
++ int ret = 0;
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB,
++ ht & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB,
++ (ht >> 8) & 0xff);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_MSB] = (ht >> 8) & 0xff;
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_LSB] = ht & 0xff;
++ mutex_unlock(&data->lock);
++
++ return ret;
++}
++
++/*
++ * range
++ */
++static int isl29023_get_range(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND2,
++ ISL29023_RANGE_MASK, ISL29023_RANGE_SHIFT);
++}
++
++static int isl29023_set_range(struct i2c_client *client, int range)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND2,
++ ISL29023_RANGE_MASK, ISL29023_RANGE_SHIFT, range);
++}
++
++/*
++ * resolution
++ */
++static int isl29023_get_resolution(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND2,
++ ISL29023_RES_MASK, ISL29023_RES_SHIFT);
++}
++
++static int isl29023_set_resolution(struct i2c_client *client, int res)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND2,
++ ISL29023_RES_MASK, ISL29023_RES_SHIFT, res);
++}
++
++/*
++ * mode
++ */
++static int isl29023_get_mode(struct i2c_client *client)
++{
++ return __isl29023_read_reg(client, ISL29023_COMMAND1,
++ ISL29023_MODE_MASK, ISL29023_MODE_SHIFT);
++}
++
++static int isl29023_set_mode(struct i2c_client *client, int mode)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_MODE_MASK, ISL29023_MODE_SHIFT, mode);
++}
++
++/*
++ * power_state
++ */
++static int isl29023_set_power_state(struct i2c_client *client, int state)
++{
++ return __isl29023_write_reg(client, ISL29023_COMMAND1,
++ ISL29023_MODE_MASK, ISL29023_MODE_SHIFT,
++ state ?
++ ISL29023_ALS_ONCE_MODE : ISL29023_PD_MODE);
++}
++
++static int isl29023_get_power_state(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ u8 cmdreg = data->reg_cache[ISL29023_COMMAND1];
++
++ if (cmdreg & ISL29023_MODE_MASK)
++ return 1;
++ else
++ return 0;
++}
++
++static int isl29023_get_adc_value(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, range, bitdepth;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_LSB_SENSOR);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_MSB_SENSOR);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ return (((msb << 8) | lsb) * ((gain_range[range] * 499) / data->rext))
++ >> bitdepth;
++}
++
++static int isl29023_get_int_lt_value(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, range, bitdepth;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ return (((msb << 8) | lsb) * ((gain_range[range] * 499) / data->rext))
++ >> bitdepth;
++}
++
++static int isl29023_get_int_ht_value(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int lsb, msb, range, bitdepth;
++
++ mutex_lock(&data->lock);
++ lsb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB);
++
++ if (lsb < 0) {
++ mutex_unlock(&data->lock);
++ return lsb;
++ }
++
++ msb = i2c_smbus_read_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB);
++ mutex_unlock(&data->lock);
++
++ if (msb < 0)
++ return msb;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ return (((msb << 8) | lsb) * ((gain_range[range] * 499) / data->rext))
++ >> bitdepth;
++}
++
++/*
++ * sysfs layer
++ */
++
++/*
++ * interrupt persists
++ */
++static ssize_t isl29023_show_int_persists(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_persists(client));
++}
++
++static ssize_t isl29023_store_int_persists(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) ||
++ (val > ISL29023_INT_PERSISTS_16))
++ return -EINVAL;
++
++ ret = isl29023_set_int_persists(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_persists, S_IWUSR | S_IRUGO,
++ isl29023_show_int_persists, isl29023_store_int_persists);
++
++/*
++ *interrupt flag
++ */
++static ssize_t isl29023_show_int_flag(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_flag(client));
++}
++
++static ssize_t isl29023_store_int_flag(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > 1))
++ return -EINVAL;
++
++ ret = isl29023_set_int_flag(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_flag, S_IWUSR | S_IRUGO,
++ isl29023_show_int_flag, isl29023_store_int_flag);
++
++/*
++ * interrupt lt
++ */
++static ssize_t isl29023_show_int_lt(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_lt(client));
++}
++
++static ssize_t isl29023_store_int_lt(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 16, &val) < 0) || (val > 0xffff))
++ return -EINVAL;
++
++ ret = isl29023_set_int_lt(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_lt, S_IWUSR | S_IRUGO,
++ isl29023_show_int_lt, isl29023_store_int_lt);
++
++/*
++ *interrupt ht
++ */
++static ssize_t isl29023_show_int_ht(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_int_ht(client));
++}
++
++static ssize_t isl29023_store_int_ht(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 16, &val) < 0) || (val > 0xffff))
++ return -EINVAL;
++
++ ret = isl29023_set_int_ht(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(int_ht, S_IWUSR | S_IRUGO,
++ isl29023_show_int_ht, isl29023_store_int_ht);
++
++/*
++ * range
++ */
++static ssize_t isl29023_show_range(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%i\n", isl29023_get_range(client));
++}
++
++static ssize_t isl29023_store_range(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > ISL29023_RANGE_64K))
++ return -EINVAL;
++
++ ret = isl29023_set_range(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(range, S_IWUSR | S_IRUGO,
++ isl29023_show_range, isl29023_store_range);
++
++
++/*
++ * resolution
++ */
++static ssize_t isl29023_show_resolution(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%d\n", isl29023_get_resolution(client));
++}
++
++static ssize_t isl29023_store_resolution(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > ISL29023_RES_4))
++ return -EINVAL;
++
++ ret = isl29023_set_resolution(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(resolution, S_IWUSR | S_IRUGO,
++ isl29023_show_resolution, isl29023_store_resolution);
++
++/*
++ *mode
++ */
++static ssize_t isl29023_show_mode(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%d\n", isl29023_get_mode(client));
++}
++
++static ssize_t isl29023_store_mode(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) ||
++ (val > ISL29023_IR_CONT_MODE))
++ return -EINVAL;
++
++ /* clear the interrupt flag */
++ i2c_smbus_read_byte_data(client, ISL29023_COMMAND1);
++ ret = isl29023_set_mode(client, val);
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++
++static DEVICE_ATTR(mode, S_IWUSR | S_IRUGO,
++ isl29023_show_mode, isl29023_store_mode);
++
++
++/*
++ *power state
++ */
++static ssize_t isl29023_show_power_state(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ return sprintf(buf, "%d\n", isl29023_get_power_state(client));
++}
++
++static ssize_t isl29023_store_power_state(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ unsigned long val;
++ int ret;
++
++ if ((strict_strtoul(buf, 10, &val) < 0) || (val > 1))
++ return -EINVAL;
++
++ ret = isl29023_set_power_state(client, val);
++ return ret ? ret : count;
++}
++
++static DEVICE_ATTR(power_state, S_IWUSR | S_IRUGO,
++ isl29023_show_power_state, isl29023_store_power_state);
++
++/*
++ * lux
++ */
++static ssize_t isl29023_show_lux(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ /* No LUX data if not operational */
++ if (!isl29023_get_power_state(client))
++ return -EBUSY;
++
++ return sprintf(buf, "%d\n", isl29023_get_adc_value(client));
++}
++
++static DEVICE_ATTR(lux, S_IRUGO, isl29023_show_lux, NULL);
++
++/*
++ * lux interrupt low threshold
++ */
++static ssize_t isl29023_show_int_lt_lux(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ return sprintf(buf, "%d\n", isl29023_get_int_lt_value(client));
++}
++
++static ssize_t isl29023_store_int_lt_lux(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ unsigned long val, lux_data;
++ int range, bitdepth, ret;
++ u8 lsb, msb;
++
++ if ((strict_strtoul(buf, 10, &val) < 0))
++ return -EINVAL;
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ if (val > (gain_range[isl29023_get_range(client)]*499/data->rext))
++ return -EINVAL;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ lux_data = ((unsigned long)(val << bitdepth)) /
++ ((gain_range[range] * 499) / data->rext);
++ lux_data &= 0xffff;
++
++ msb = lux_data >> 8;
++ lsb = lux_data & 0xff;
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_LSB,
++ lsb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_LO_MSB,
++ msb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_MSB] = msb;
++ data->reg_cache[ISL29023_REG_IRQ_TH_LO_LSB] = lsb;
++ mutex_unlock(&data->lock);
++
++ return count;
++}
++
++static DEVICE_ATTR(int_lt_lux, S_IWUSR | S_IRUGO,
++ isl29023_show_int_lt_lux, isl29023_store_int_lt_lux);
++
++/*
++ * lux interrupt high threshold
++ */
++static ssize_t isl29023_show_int_ht_lux(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ return sprintf(buf, "%d\n", isl29023_get_int_ht_value(client));
++}
++
++static ssize_t isl29023_store_int_ht_lux(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct i2c_client *client = to_i2c_client(dev);
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ unsigned long val, lux_data;
++ int range, bitdepth, ret;
++ u8 lsb, msb;
++
++ if ((strict_strtoul(buf, 10, &val) < 0))
++ return -EINVAL;
++
++ /* No LUX data if not operational */
++ if (isl29023_get_mode(client) != ISL29023_ALS_ONCE_MODE &&
++ isl29023_get_mode(client) != ISL29023_ALS_CONT_MODE)
++ return -EIO;
++
++ if (val > (gain_range[isl29023_get_range(client)]*499/data->rext))
++ return -EINVAL;
++
++ range = isl29023_get_range(client);
++ bitdepth = (4 - isl29023_get_resolution(client)) * 4;
++ lux_data = ((unsigned long)(val << bitdepth)) /
++ ((gain_range[range] * 499) / data->rext);
++ lux_data &= 0xffff;
++
++ msb = lux_data >> 8;
++ lsb = lux_data & 0xff;
++
++ mutex_lock(&data->lock);
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_LSB,
++ lsb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ ret = i2c_smbus_write_byte_data(client, ISL29023_REG_IRQ_TH_HI_MSB,
++ msb);
++ if (ret < 0) {
++ mutex_unlock(&data->lock);
++ return ret;
++ }
++
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_MSB] = msb;
++ data->reg_cache[ISL29023_REG_IRQ_TH_HI_LSB] = lsb;
++ mutex_unlock(&data->lock);
++
++ return count;
++}
++
++static DEVICE_ATTR(int_ht_lux, S_IWUSR | S_IRUGO,
++ isl29023_show_int_ht_lux, isl29023_store_int_ht_lux);
++
++static struct attribute *isl29023_attributes[] = {
++ &dev_attr_int_persists.attr,
++ &dev_attr_range.attr,
++ &dev_attr_resolution.attr,
++ &dev_attr_mode.attr,
++ &dev_attr_power_state.attr,
++ &dev_attr_lux.attr,
++ &dev_attr_int_lt_lux.attr,
++ &dev_attr_int_ht_lux.attr,
++ &dev_attr_int_lt.attr,
++ &dev_attr_int_ht.attr,
++ &dev_attr_int_flag.attr,
++ NULL
++};
++
++static const struct attribute_group isl29023_attr_group = {
++ .attrs = isl29023_attributes,
++};
++
++static int isl29023_init_client(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++ int i;
++
++ /* read all the registers once to fill the cache.
++ * if one of the reads fails, we consider the init failed */
++ for (i = 0; i < ARRAY_SIZE(data->reg_cache); i++) {
++ int v = i2c_smbus_read_byte_data(client, i);
++ if (v < 0)
++ return -ENODEV;
++
++ data->reg_cache[i] = v;
++ }
++
++ /* set defaults */
++ isl29023_set_int_persists(client, ISL29023_INT_PERSISTS_8);
++ isl29023_set_int_ht(client, 0xffff);
++ isl29023_set_int_lt(client, 0x0);
++ isl29023_set_range(client, ISL29023_RANGE_16K);
++ isl29023_set_resolution(client, ISL29023_RES_16);
++ isl29023_set_mode(client, ISL29023_ALS_ONCE_MODE);
++ isl29023_set_int_flag(client, 0);
++ isl29023_set_power_state(client, 0);
++
++ return 0;
++}
++
++static void isl29023_work(struct work_struct *work)
++{
++ struct isl29023_data *data =
++ container_of(work, struct isl29023_data, work);
++ struct i2c_client *client = data->client;
++ int lux;
++
++ /* Clear interrupt flag */
++ isl29023_set_int_flag(client, 0);
++
++ data->mode_before_interrupt = isl29023_get_mode(client);
++ lux = isl29023_get_adc_value(client);
++
++ /* To clear the interrpt status */
++ isl29023_set_power_state(client, ISL29023_PD_MODE);
++ isl29023_set_mode(client, data->mode_before_interrupt);
++
++ msleep(100);
++
++ input_report_abs(data->input, ABS_MISC, lux);
++ input_sync(data->input);
++}
++
++static irqreturn_t isl29023_irq_handler(int irq, void *handle)
++{
++ struct isl29023_data *data = handle;
++ int cmd_1;
++ cmd_1 = i2c_smbus_read_byte_data(data->client, ISL29023_COMMAND1);
++ if (!(cmd_1 & ISL29023_INT_FLAG_MASK))
++ return IRQ_NONE;
++
++ queue_work(data->workqueue, &data->work);
++ return IRQ_HANDLED;
++}
++
++/*
++ * I2C layer
++ */
++static int isl29023_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
++ struct isl29023_data *data;
++ struct input_dev *input_dev;
++ int err = 0;
++ struct regulator *vdd = NULL;
++ u32 rext = 0;
++ struct device_node *of_node = client->dev.of_node;
++ struct irq_data *irq_data = irq_get_irq_data(client->irq);
++ u32 irq_flag;
++ bool shared_irq;
++
++ vdd = devm_regulator_get(&client->dev, "vdd");
++ if (!IS_ERR(vdd)) {
++ err = regulator_enable(vdd);
++ if (err) {
++ dev_err(&client->dev, "vdd set voltage error\n");
++ return err;
++ }
++ }
++
++ err = of_property_read_u32(of_node, "rext", &rext);
++ if (err)
++ rext = DEFAULT_REGISTOR_VAL;
++ shared_irq = of_property_read_bool(of_node, "shared-interrupt");
++
++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE))
++ return -EIO;
++
++ data = kzalloc(sizeof(struct isl29023_data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ data->client = client;
++ data->rext = (u16)rext;
++ snprintf(data->phys, sizeof(data->phys),
++ "%s", dev_name(&client->dev));
++ i2c_set_clientdata(client, data);
++ mutex_init(&data->lock);
++
++ /* initialize the ISL29023 chip */
++ err = isl29023_init_client(client);
++ if (err)
++ goto exit_kfree;
++
++ /* register sysfs hooks */
++ err = sysfs_create_group(&client->dev.kobj, &isl29023_attr_group);
++ if (err)
++ goto exit_kfree;
++
++ input_dev = input_allocate_device();
++ if (!input_dev) {
++ err = -ENOMEM;
++ goto exit_kfree;
++ }
++
++ data->input = input_dev;
++ input_dev->name = "isl29023 light sensor";
++ input_dev->id.bustype = BUS_I2C;
++ input_dev->phys = data->phys;
++
++ __set_bit(EV_ABS, input_dev->evbit);
++ input_set_abs_params(input_dev, ABS_MISC, 0,
++ gain_range[DEF_RANGE]*499/data->rext, 0, 0);
++
++ err = input_register_device(input_dev);
++ if (err)
++ goto exit_free_input;
++
++ irq_flag = irqd_get_trigger_type(irq_data);
++ irq_flag |= IRQF_ONESHOT;
++ if (shared_irq)
++ irq_flag |= IRQF_SHARED;
++ err = request_threaded_irq(client->irq, NULL,
++ isl29023_irq_handler, irq_flag,
++ client->dev.driver->name, data);
++ if (err < 0) {
++ dev_err(&client->dev, "failed to register irq %d!\n",
++ client->irq);
++ goto exit_free_input;
++ }
++
++ data->workqueue = create_singlethread_workqueue("isl29023");
++ INIT_WORK(&data->work, isl29023_work);
++ if (data->workqueue == NULL) {
++ dev_err(&client->dev, "couldn't create workqueue\n");
++ err = -ENOMEM;
++ goto exit_free_interrupt;
++ }
++
++ dev_info(&client->dev, "driver version %s enabled\n", DRIVER_VERSION);
++ return 0;
++
++exit_free_interrupt:
++ free_irq(client->irq, data);
++exit_free_input:
++ input_free_device(input_dev);
++exit_kfree:
++ kfree(data);
++ return err;
++}
++
++static int isl29023_remove(struct i2c_client *client)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ cancel_work_sync(&data->work);
++ destroy_workqueue(data->workqueue);
++ free_irq(client->irq, data);
++ input_unregister_device(data->input);
++ input_free_device(data->input);
++ sysfs_remove_group(&client->dev.kobj, &isl29023_attr_group);
++ isl29023_set_power_state(client, 0);
++ kfree(i2c_get_clientdata(client));
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int isl29023_suspend(struct i2c_client *client, pm_message_t mesg)
++{
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ data->mode_before_suspend = isl29023_get_mode(client);
++ return isl29023_set_power_state(client, ISL29023_PD_MODE);
++}
++
++static int isl29023_resume(struct i2c_client *client)
++{
++ int i;
++ struct isl29023_data *data = i2c_get_clientdata(client);
++
++ /* restore registers from cache */
++ for (i = 0; i < ARRAY_SIZE(data->reg_cache); i++)
++ if (i2c_smbus_write_byte_data(client, i, data->reg_cache[i]))
++ return -EIO;
++
++ return isl29023_set_mode(client, data->mode_before_suspend);
++}
++
++#else
++#define isl29023_suspend NULL
++#define isl29023_resume NULL
++#endif /* CONFIG_PM */
++
++static const struct i2c_device_id isl29023_id[] = {
++ { ISL29023_DRV_NAME, 0 },
++ {}
++};
++MODULE_DEVICE_TABLE(i2c, isl29023_id);
++
++static struct i2c_driver isl29023_driver = {
++ .driver = {
++ .name = ISL29023_DRV_NAME,
++ .owner = THIS_MODULE,
++ },
++ .suspend = isl29023_suspend,
++ .resume = isl29023_resume,
++ .probe = isl29023_probe,
++ .remove = isl29023_remove,
++ .id_table = isl29023_id,
++};
++
++static int __init isl29023_init(void)
++{
++ return i2c_add_driver(&isl29023_driver);
++}
++
++static void __exit isl29023_exit(void)
++{
++ i2c_del_driver(&isl29023_driver);
++}
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("ISL29023 ambient light sensor driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION(DRIVER_VERSION);
++
++module_init(isl29023_init);
++module_exit(isl29023_exit);
+diff -Nur linux-3.14.72.orig/drivers/input/misc/Kconfig linux-3.14.72/drivers/input/misc/Kconfig
+--- linux-3.14.72.orig/drivers/input/misc/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/misc/Kconfig 2016-06-19 22:11:55.165149193 +0200
+@@ -666,4 +666,14 @@
+ To compile this driver as a module, choose M here: the
+ module will be called ideapad_slidebar.
+
++config INPUT_ISL29023
++ tristate "Intersil ISL29023 ambient light sensor"
++ depends on I2C && SYSFS
++ help
++ If you say yes here you get support for the Intersil ISL29023
++ ambient light sensor.
++
++ This driver can also be built as a module. If so, the module
++ will be called isl29023.
++
+ endif
+diff -Nur linux-3.14.72.orig/drivers/input/misc/Makefile linux-3.14.72/drivers/input/misc/Makefile
+--- linux-3.14.72.orig/drivers/input/misc/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/misc/Makefile 2016-06-19 22:11:55.165149193 +0200
+@@ -63,3 +63,4 @@
+ obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o
+ obj-$(CONFIG_INPUT_YEALINK) += yealink.o
+ obj-$(CONFIG_INPUT_IDEAPAD_SLIDEBAR) += ideapad_slidebar.o
++obj-$(CONFIG_INPUT_ISL29023) += isl29023.o
+diff -Nur linux-3.14.72.orig/drivers/input/misc/mma8450.c linux-3.14.72/drivers/input/misc/mma8450.c
+--- linux-3.14.72.orig/drivers/input/misc/mma8450.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/misc/mma8450.c 2016-06-19 22:11:55.165149193 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Driver for Freescale's 3-Axis Accelerometer MMA8450
+ *
+- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+@@ -25,6 +25,7 @@
+ #include <linux/i2c.h>
+ #include <linux/input-polldev.h>
+ #include <linux/of_device.h>
++#include <linux/mutex.h>
+
+ #define MMA8450_DRV_NAME "mma8450"
+
+@@ -51,11 +52,22 @@
+
+ #define MMA8450_CTRL_REG1 0x38
+ #define MMA8450_CTRL_REG2 0x39
++#define MMA8450_ID 0xC6
++#define MMA8450_WHO_AM_I 0x0F
++
++enum {
++ MODE_STANDBY = 0,
++ MODE_2G,
++ MODE_4G,
++ MODE_8G,
++};
+
+ /* mma8450 status */
+ struct mma8450 {
+ struct i2c_client *client;
+ struct input_polled_dev *idev;
++ struct mutex mma8450_lock;
++ u8 mode;
+ };
+
+ static int mma8450_read(struct mma8450 *m, unsigned off)
+@@ -112,16 +124,19 @@
+ int ret;
+ u8 buf[6];
+
+- ret = mma8450_read(m, MMA8450_STATUS);
+- if (ret < 0)
+- return;
++ mutex_lock(&m->mma8450_lock);
+
+- if (!(ret & MMA8450_STATUS_ZXYDR))
++ ret = mma8450_read(m, MMA8450_STATUS);
++ if (ret < 0 || !(ret & MMA8450_STATUS_ZXYDR)) {
++ mutex_unlock(&m->mma8450_lock);
+ return;
++ }
+
+ ret = mma8450_read_block(m, MMA8450_OUT_X_LSB, buf, sizeof(buf));
+- if (ret < 0)
++ if (ret < 0) {
++ mutex_unlock(&m->mma8450_lock);
+ return;
++ }
+
+ x = ((int)(s8)buf[1] << 4) | (buf[0] & 0xf);
+ y = ((int)(s8)buf[3] << 4) | (buf[2] & 0xf);
+@@ -131,10 +146,12 @@
+ input_report_abs(dev->input, ABS_Y, y);
+ input_report_abs(dev->input, ABS_Z, z);
+ input_sync(dev->input);
++
++ mutex_unlock(&m->mma8450_lock);
+ }
+
+ /* Initialize the MMA8450 chip */
+-static void mma8450_open(struct input_polled_dev *dev)
++static s32 mma8450_open(struct input_polled_dev *dev)
+ {
+ struct mma8450 *m = dev->private;
+ int err;
+@@ -142,18 +159,20 @@
+ /* enable all events from X/Y/Z, no FIFO */
+ err = mma8450_write(m, MMA8450_XYZ_DATA_CFG, 0x07);
+ if (err)
+- return;
++ return err;
+
+ /*
+ * Sleep mode poll rate - 50Hz
+ * System output data rate - 400Hz
+- * Full scale selection - Active, +/- 2G
++ * Standby mode
+ */
+- err = mma8450_write(m, MMA8450_CTRL_REG1, 0x01);
+- if (err < 0)
+- return;
+-
++ err = mma8450_write(m, MMA8450_CTRL_REG1, MODE_STANDBY);
++ if (err)
++ return err;
++ m->mode = MODE_STANDBY;
+ msleep(MODE_CHANGE_DELAY_MS);
++
++ return 0;
+ }
+
+ static void mma8450_close(struct input_polled_dev *dev)
+@@ -164,6 +183,76 @@
+ mma8450_write(m, MMA8450_CTRL_REG2, 0x01);
+ }
+
++static ssize_t mma8450_scalemode_show(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ int mode = 0;
++ struct mma8450 *m;
++ struct i2c_client *client = to_i2c_client(dev);
++
++ m = i2c_get_clientdata(client);
++
++ mutex_lock(&m->mma8450_lock);
++ mode = (int)m->mode;
++ mutex_unlock(&m->mma8450_lock);
++
++ return sprintf(buf, "%d\n", mode);
++}
++
++static ssize_t mma8450_scalemode_store(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ unsigned long mode;
++ int ret;
++ struct mma8450 *m = NULL;
++ struct i2c_client *client = to_i2c_client(dev);
++
++ ret = strict_strtoul(buf, 10, &mode);
++ if (ret) {
++ dev_err(dev, "string transform error\n");
++ return ret;
++ }
++
++ if (mode > MODE_8G) {
++ dev_warn(dev, "not supported mode %d\n", (int)mode);
++ return count;
++ }
++
++ m = i2c_get_clientdata(client);
++
++ mutex_lock(&m->mma8450_lock);
++ if (mode == m->mode) {
++ mutex_unlock(&m->mma8450_lock);
++ return count;
++ }
++
++ ret = mma8450_write(m, MMA8450_CTRL_REG1, mode);
++ if (ret < 0) {
++ mutex_unlock(&m->mma8450_lock);
++ return ret;
++ }
++
++ msleep(MODE_CHANGE_DELAY_MS);
++ m->mode = (u8)mode;
++ mutex_unlock(&m->mma8450_lock);
++
++ return count;
++}
++
++static DEVICE_ATTR(scalemode, S_IWUSR | S_IRUGO,
++ mma8450_scalemode_show, mma8450_scalemode_store);
++
++static struct attribute *mma8450_attributes[] = {
++ &dev_attr_scalemode.attr,
++ NULL
++};
++
++static const struct attribute_group mma8450_attr_group = {
++ .attrs = mma8450_attributes,
++};
++
+ /*
+ * I2C init/probing/exit functions
+ */
+@@ -172,7 +261,25 @@
+ {
+ struct input_polled_dev *idev;
+ struct mma8450 *m;
+- int err;
++ int err, client_id;
++ struct i2c_adapter *adapter = NULL;
++
++ adapter = to_i2c_adapter(c->dev.parent);
++ err = i2c_check_functionality(adapter,
++ I2C_FUNC_SMBUS_BYTE |
++ I2C_FUNC_SMBUS_BYTE_DATA);
++ if (!err)
++ goto err_out;
++
++ client_id = i2c_smbus_read_byte_data(c, MMA8450_WHO_AM_I);
++
++ if (MMA8450_ID != client_id) {
++ dev_err(&c->dev,
++ "read chip ID 0x%x is not equal to 0x%x!\n", client_id,
++ MMA8450_ID);
++ err = -EINVAL;
++ goto err_out;
++ }
+
+ m = kzalloc(sizeof(struct mma8450), GFP_KERNEL);
+ idev = input_allocate_polled_device();
+@@ -183,6 +290,7 @@
+
+ m->client = c;
+ m->idev = idev;
++ i2c_set_clientdata(c, m);
+
+ idev->private = m;
+ idev->input->name = MMA8450_DRV_NAME;
+@@ -190,8 +298,6 @@
+ idev->poll = mma8450_poll;
+ idev->poll_interval = POLL_INTERVAL;
+ idev->poll_interval_max = POLL_INTERVAL_MAX;
+- idev->open = mma8450_open;
+- idev->close = mma8450_close;
+
+ __set_bit(EV_ABS, idev->input->evbit);
+ input_set_abs_params(idev->input, ABS_X, -2048, 2047, 32, 32);
+@@ -204,13 +310,32 @@
+ goto err_free_mem;
+ }
+
+- i2c_set_clientdata(c, m);
++ mutex_init(&m->mma8450_lock);
++
++ err = mma8450_open(idev);
++ if (err) {
++ dev_err(&c->dev, "failed to initialize mma8450\n");
++ goto err_unreg_dev;
++ }
++
++ err = sysfs_create_group(&c->dev.kobj, &mma8450_attr_group);
++ if (err) {
++ dev_err(&c->dev, "create device file failed!\n");
++ err = -EINVAL;
++ goto err_close;
++ }
+
+ return 0;
+
++err_close:
++ mma8450_close(idev);
++err_unreg_dev:
++ mutex_destroy(&m->mma8450_lock);
++ input_unregister_polled_device(idev);
+ err_free_mem:
+ input_free_polled_device(idev);
+ kfree(m);
++err_out:
+ return err;
+ }
+
+@@ -219,6 +344,9 @@
+ struct mma8450 *m = i2c_get_clientdata(c);
+ struct input_polled_dev *idev = m->idev;
+
++ sysfs_remove_group(&c->dev.kobj, &mma8450_attr_group);
++ mma8450_close(idev);
++ mutex_destroy(&m->mma8450_lock);
+ input_unregister_polled_device(idev);
+ input_free_polled_device(idev);
+ kfree(m);
+diff -Nur linux-3.14.72.orig/drivers/input/touchscreen/edt-ft5x06.c linux-3.14.72/drivers/input/touchscreen/edt-ft5x06.c
+--- linux-3.14.72.orig/drivers/input/touchscreen/edt-ft5x06.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/touchscreen/edt-ft5x06.c 2016-06-19 22:11:55.165149193 +0200
+@@ -1,5 +1,7 @@
+ /*
+ * Copyright (C) 2012 Simon Budig, <simon.budig@kernelconcepts.de>
++ * Daniel Wagener <daniel.wagener@kernelconcepts.de> (M09 firmware support)
++ * Lothar Waßmann <LW@KARO-electronics.de> (DT support)
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+@@ -33,6 +35,7 @@
+ #include <linux/debugfs.h>
+ #include <linux/slab.h>
+ #include <linux/gpio.h>
++#include <linux/of_gpio.h>
+ #include <linux/input/mt.h>
+ #include <linux/input/edt-ft5x06.h>
+
+@@ -45,6 +48,14 @@
+ #define WORK_REGISTER_NUM_X 0x33
+ #define WORK_REGISTER_NUM_Y 0x34
+
++#define M09_REGISTER_THRESHOLD 0x80
++#define M09_REGISTER_GAIN 0x92
++#define M09_REGISTER_OFFSET 0x93
++#define M09_REGISTER_NUM_X 0x94
++#define M09_REGISTER_NUM_Y 0x95
++
++#define NO_REGISTER 0xff
++
+ #define WORK_REGISTER_OPMODE 0x3c
+ #define FACTORY_REGISTER_OPMODE 0x01
+
+@@ -59,12 +70,30 @@
+ #define EDT_RAW_DATA_RETRIES 100
+ #define EDT_RAW_DATA_DELAY 1 /* msec */
+
++enum edt_ver {
++ M06,
++ M09,
++};
++
++struct edt_reg_addr {
++ int reg_threshold;
++ int reg_report_rate;
++ int reg_gain;
++ int reg_offset;
++ int reg_num_x;
++ int reg_num_y;
++};
++
+ struct edt_ft5x06_ts_data {
+ struct i2c_client *client;
+ struct input_dev *input;
+ u16 num_x;
+ u16 num_y;
+
++ int reset_pin;
++ int irq_pin;
++ int wake_pin;
++
+ #if defined(CONFIG_DEBUG_FS)
+ struct dentry *debug_dir;
+ u8 *raw_buffer;
+@@ -79,6 +108,13 @@
+ int report_rate;
+
+ char name[EDT_NAME_LEN];
++
++ struct edt_reg_addr reg_addr;
++ enum edt_ver version;
++
++ bool invert;
++ int screen_x;
++ int screen_y;
+ };
+
+ static int edt_ft5x06_ts_readwrite(struct i2c_client *client,
+@@ -136,33 +172,58 @@
+ {
+ struct edt_ft5x06_ts_data *tsdata = dev_id;
+ struct device *dev = &tsdata->client->dev;
+- u8 cmd = 0xf9;
+- u8 rdbuf[26];
++ u8 cmd;
++ u8 rdbuf[29];
+ int i, type, x, y, id;
++ int offset, tplen, datalen;
+ int error;
+
++ switch (tsdata->version) {
++ case M06:
++ cmd = 0xf9; /* tell the controller to send touch data */
++ offset = 5; /* where the actual touch data starts */
++ tplen = 4; /* data comes in so called frames */
++ datalen = 26; /* how much bytes to listen for */
++ break;
++
++ case M09:
++ cmd = 0x02;
++ offset = 1;
++ tplen = 6;
++ datalen = 29;
++ break;
++
++ default:
++ goto out;
++ }
++
+ memset(rdbuf, 0, sizeof(rdbuf));
+
+ error = edt_ft5x06_ts_readwrite(tsdata->client,
+ sizeof(cmd), &cmd,
+- sizeof(rdbuf), rdbuf);
++ datalen, rdbuf);
+ if (error) {
+ dev_err_ratelimited(dev, "Unable to fetch data, error: %d\n",
+ error);
+ goto out;
+ }
+
+- if (rdbuf[0] != 0xaa || rdbuf[1] != 0xaa || rdbuf[2] != 26) {
+- dev_err_ratelimited(dev, "Unexpected header: %02x%02x%02x!\n",
+- rdbuf[0], rdbuf[1], rdbuf[2]);
+- goto out;
+- }
++ /* M09 does not send header or CRC */
++ if (tsdata->version == M06) {
++ if (rdbuf[0] != 0xaa || rdbuf[1] != 0xaa ||
++ rdbuf[2] != datalen) {
++ dev_err_ratelimited(dev,
++ "Unexpected header: %02x%02x%02x!\n",
++ rdbuf[0], rdbuf[1], rdbuf[2]);
++ goto out;
++ }
+
+- if (!edt_ft5x06_ts_check_crc(tsdata, rdbuf, 26))
+- goto out;
++ if (!edt_ft5x06_ts_check_crc(tsdata, rdbuf, datalen))
++ goto out;
++ }
+
+ for (i = 0; i < MAX_SUPPORT_POINTS; i++) {
+- u8 *buf = &rdbuf[i * 4 + 5];
++ u8 *buf = &rdbuf[i * tplen + offset];
+ bool down;
+
+ type = buf[0] >> 6;
+@@ -170,11 +231,22 @@
+ if (type == TOUCH_EVENT_RESERVED)
+ continue;
+
++ /* M06 sometimes sends bogus coordinates in TOUCH_DOWN */
++ if (tsdata->version == M06 && type == TOUCH_EVENT_DOWN)
++ continue;
++
+ x = ((buf[0] << 8) | buf[1]) & 0x0fff;
+ y = ((buf[2] << 8) | buf[3]) & 0x0fff;
+ id = (buf[2] >> 4) & 0x0f;
+ down = (type != TOUCH_EVENT_UP);
+
++ /* invert axis */
++ if (tsdata->invert) {
++ x = tsdata->screen_x - x;
++ y = tsdata->screen_y - y;
++ }
++ dev_dbg(dev, "%d: %dx%d %s\n", id, x, y, down ? "UP" : "DOWN");
++
+ input_mt_slot(tsdata->input, id);
+ input_mt_report_slot_state(tsdata->input, MT_TOOL_FINGER, down);
+
+@@ -197,12 +269,25 @@
+ {
+ u8 wrbuf[4];
+
+- wrbuf[0] = tsdata->factory_mode ? 0xf3 : 0xfc;
+- wrbuf[1] = tsdata->factory_mode ? addr & 0x7f : addr & 0x3f;
+- wrbuf[2] = value;
+- wrbuf[3] = wrbuf[0] ^ wrbuf[1] ^ wrbuf[2];
++ switch (tsdata->version) {
++ case M06:
++ wrbuf[0] = tsdata->factory_mode ? 0xf3 : 0xfc;
++ wrbuf[1] = tsdata->factory_mode ? addr & 0x7f : addr & 0x3f;
++ wrbuf[1] = tsdata->factory_mode ? addr & 0x7f : addr & 0x3f;
++ wrbuf[2] = value;
++ wrbuf[3] = wrbuf[0] ^ wrbuf[1] ^ wrbuf[2];
++ return edt_ft5x06_ts_readwrite(tsdata->client, 4,
++ wrbuf, 0, NULL);
++ case M09:
++ wrbuf[0] = addr;
++ wrbuf[1] = value;
+
+- return edt_ft5x06_ts_readwrite(tsdata->client, 4, wrbuf, 0, NULL);
++ return edt_ft5x06_ts_readwrite(tsdata->client, 2,
++ wrbuf, 0, NULL);
++
++ default:
++ return -EINVAL;
++ }
+ }
+
+ static int edt_ft5x06_register_read(struct edt_ft5x06_ts_data *tsdata,
+@@ -211,19 +296,36 @@
+ u8 wrbuf[2], rdbuf[2];
+ int error;
+
+- wrbuf[0] = tsdata->factory_mode ? 0xf3 : 0xfc;
+- wrbuf[1] = tsdata->factory_mode ? addr & 0x7f : addr & 0x3f;
+- wrbuf[1] |= tsdata->factory_mode ? 0x80 : 0x40;
++ switch (tsdata->version) {
++ case M06:
++ wrbuf[0] = tsdata->factory_mode ? 0xf3 : 0xfc;
++ wrbuf[1] = tsdata->factory_mode ? addr & 0x7f : addr & 0x3f;
++ wrbuf[1] |= tsdata->factory_mode ? 0x80 : 0x40;
+
+- error = edt_ft5x06_ts_readwrite(tsdata->client, 2, wrbuf, 2, rdbuf);
+- if (error)
+- return error;
++ error = edt_ft5x06_ts_readwrite(tsdata->client, 2, wrbuf, 2,
++ rdbuf);
++ if (error)
++ return error;
+
+- if ((wrbuf[0] ^ wrbuf[1] ^ rdbuf[0]) != rdbuf[1]) {
+- dev_err(&tsdata->client->dev,
+- "crc error: 0x%02x expected, got 0x%02x\n",
+- wrbuf[0] ^ wrbuf[1] ^ rdbuf[0], rdbuf[1]);
+- return -EIO;
++ if ((wrbuf[0] ^ wrbuf[1] ^ rdbuf[0]) != rdbuf[1]) {
++ dev_err(&tsdata->client->dev,
++ "crc error: 0x%02x expected, got 0x%02x\n",
++ wrbuf[0] ^ wrbuf[1] ^ rdbuf[0],
++ rdbuf[1]);
++ return -EIO;
++ }
++ break;
++
++ case M09:
++ wrbuf[0] = addr;
++ error = edt_ft5x06_ts_readwrite(tsdata->client, 1,
++ wrbuf, 1, rdbuf);
++ if (error)
++ return error;
++ break;
++
++ default:
++ return -EINVAL;
+ }
+
+ return rdbuf[0];
+@@ -234,19 +336,21 @@
+ size_t field_offset;
+ u8 limit_low;
+ u8 limit_high;
+- u8 addr;
++ u8 addr_m06;
++ u8 addr_m09;
+ };
+
+-#define EDT_ATTR(_field, _mode, _addr, _limit_low, _limit_high) \
++#define EDT_ATTR(_field, _mode, _addr_m06, _addr_m09, \
++ _limit_low, _limit_high) \
+ struct edt_ft5x06_attribute edt_ft5x06_attr_##_field = { \
+ .dattr = __ATTR(_field, _mode, \
+ edt_ft5x06_setting_show, \
+ edt_ft5x06_setting_store), \
+- .field_offset = \
+- offsetof(struct edt_ft5x06_ts_data, _field), \
++ .field_offset = offsetof(struct edt_ft5x06_ts_data, _field), \
++ .addr_m06 = _addr_m06, \
++ .addr_m09 = _addr_m09, \
+ .limit_low = _limit_low, \
+ .limit_high = _limit_high, \
+- .addr = _addr, \
+ }
+
+ static ssize_t edt_ft5x06_setting_show(struct device *dev,
+@@ -261,6 +365,7 @@
+ int val;
+ size_t count = 0;
+ int error = 0;
++ u8 addr;
+
+ mutex_lock(&tsdata->mutex);
+
+@@ -269,15 +374,33 @@
+ goto out;
+ }
+
+- val = edt_ft5x06_register_read(tsdata, attr->addr);
+- if (val < 0) {
+- error = val;
+- dev_err(&tsdata->client->dev,
+- "Failed to fetch attribute %s, error %d\n",
+- dattr->attr.name, error);
++ switch (tsdata->version) {
++ case M06:
++ addr = attr->addr_m06;
++ break;
++
++ case M09:
++ addr = attr->addr_m09;
++ break;
++
++ default:
++ error = -ENODEV;
+ goto out;
+ }
+
++ if (addr != NO_REGISTER) {
++ val = edt_ft5x06_register_read(tsdata, addr);
++ if (val < 0) {
++ error = val;
++ dev_err(&tsdata->client->dev,
++ "Failed to fetch attribute %s, error %d\n",
++ dattr->attr.name, error);
++ goto out;
++ }
++ } else {
++ val = *field;
++ }
++
+ if (val != *field) {
+ dev_warn(&tsdata->client->dev,
+ "%s: read (%d) and stored value (%d) differ\n",
+@@ -302,6 +425,7 @@
+ u8 *field = (u8 *)((char *)tsdata + attr->field_offset);
+ unsigned int val;
+ int error;
++ u8 addr;
+
+ mutex_lock(&tsdata->mutex);
+
+@@ -319,14 +443,29 @@
+ goto out;
+ }
+
+- error = edt_ft5x06_register_write(tsdata, attr->addr, val);
+- if (error) {
+- dev_err(&tsdata->client->dev,
+- "Failed to update attribute %s, error: %d\n",
+- dattr->attr.name, error);
++ switch (tsdata->version) {
++ case M06:
++ addr = attr->addr_m06;
++ break;
++
++ case M09:
++ addr = attr->addr_m09;
++ break;
++
++ default:
++ error = -ENODEV;
+ goto out;
+ }
+
++ if (addr != NO_REGISTER) {
++ error = edt_ft5x06_register_write(tsdata, addr, val);
++ if (error) {
++ dev_err(&tsdata->client->dev,
++ "Failed to update attribute %s, error: %d\n",
++ dattr->attr.name, error);
++ goto out;
++ }
++ }
+ *field = val;
+
+ out:
+@@ -334,12 +473,14 @@
+ return error ?: count;
+ }
+
+-static EDT_ATTR(gain, S_IWUSR | S_IRUGO, WORK_REGISTER_GAIN, 0, 31);
+-static EDT_ATTR(offset, S_IWUSR | S_IRUGO, WORK_REGISTER_OFFSET, 0, 31);
+-static EDT_ATTR(threshold, S_IWUSR | S_IRUGO,
+- WORK_REGISTER_THRESHOLD, 20, 80);
+-static EDT_ATTR(report_rate, S_IWUSR | S_IRUGO,
+- WORK_REGISTER_REPORT_RATE, 3, 14);
++static EDT_ATTR(gain, S_IWUSR | S_IRUGO, WORK_REGISTER_GAIN,
++ M09_REGISTER_GAIN, 0, 31);
++static EDT_ATTR(offset, S_IWUSR | S_IRUGO, WORK_REGISTER_OFFSET,
++ M09_REGISTER_OFFSET, 0, 31);
++static EDT_ATTR(threshold, S_IWUSR | S_IRUGO, WORK_REGISTER_THRESHOLD,
++ M09_REGISTER_THRESHOLD, 20, 80);
++static EDT_ATTR(report_rate, S_IWUSR | S_IRUGO, WORK_REGISTER_REPORT_RATE,
++ NO_REGISTER, 3, 14);
+
+ static struct attribute *edt_ft5x06_attrs[] = {
+ &edt_ft5x06_attr_gain.dattr.attr,
+@@ -374,6 +515,9 @@
+ }
+
+ /* mode register is 0x3c when in the work mode */
++ if (tsdata->version == M09)
++ goto m09_out;
++
+ error = edt_ft5x06_register_write(tsdata, WORK_REGISTER_OPMODE, 0x03);
+ if (error) {
+ dev_err(&client->dev,
+@@ -406,12 +550,18 @@
+ enable_irq(client->irq);
+
+ return error;
++
++m09_out:
++ dev_err(&client->dev, "No factory mode support for M09\n");
++ return -EINVAL;
++
+ }
+
+ static int edt_ft5x06_work_mode(struct edt_ft5x06_ts_data *tsdata)
+ {
+ struct i2c_client *client = tsdata->client;
+ int retries = EDT_SWITCH_MODE_RETRIES;
++ struct edt_reg_addr *reg_addr = &tsdata->reg_addr;
+ int ret;
+ int error;
+
+@@ -444,13 +594,14 @@
+ tsdata->raw_buffer = NULL;
+
+ /* restore parameters */
+- edt_ft5x06_register_write(tsdata, WORK_REGISTER_THRESHOLD,
++ edt_ft5x06_register_write(tsdata, reg_addr->reg_threshold,
+ tsdata->threshold);
+- edt_ft5x06_register_write(tsdata, WORK_REGISTER_GAIN,
++ edt_ft5x06_register_write(tsdata, reg_addr->reg_gain,
+ tsdata->gain);
+- edt_ft5x06_register_write(tsdata, WORK_REGISTER_OFFSET,
++ edt_ft5x06_register_write(tsdata, reg_addr->reg_offset,
+ tsdata->offset);
+- edt_ft5x06_register_write(tsdata, WORK_REGISTER_REPORT_RATE,
++ if (reg_addr->reg_report_rate)
++ edt_ft5x06_register_write(tsdata, reg_addr->reg_report_rate,
+ tsdata->report_rate);
+
+ enable_irq(client->irq);
+@@ -617,55 +768,99 @@
+
+
+ static int edt_ft5x06_ts_reset(struct i2c_client *client,
+- int reset_pin)
++ struct edt_ft5x06_ts_data *tsdata)
+ {
+ int error;
+
+- if (gpio_is_valid(reset_pin)) {
++ if (gpio_is_valid(tsdata->wake_pin)) {
++ error = devm_gpio_request_one(&client->dev,
++ tsdata->wake_pin, GPIOF_OUT_INIT_LOW,
++ "edt-ft5x06 wake");
++ if (error) {
++ dev_err(&client->dev,
++ "Failed to request GPIO %d as wake pin, error %d\n",
++ tsdata->wake_pin, error);
++ return error;
++ }
++
++ msleep(5);
++ gpio_set_value(tsdata->wake_pin, 1);
++ }
++ if (gpio_is_valid(tsdata->reset_pin)) {
+ /* this pulls reset down, enabling the low active reset */
+- error = devm_gpio_request_one(&client->dev, reset_pin,
+- GPIOF_OUT_INIT_LOW,
+- "edt-ft5x06 reset");
++ error = devm_gpio_request_one(&client->dev,
++ tsdata->reset_pin, GPIOF_OUT_INIT_LOW,
++ "edt-ft5x06 reset");
+ if (error) {
+ dev_err(&client->dev,
+ "Failed to request GPIO %d as reset pin, error %d\n",
+- reset_pin, error);
++ tsdata->reset_pin, error);
+ return error;
+ }
+
+- mdelay(50);
+- gpio_set_value(reset_pin, 1);
+- mdelay(100);
++ msleep(5);
++ gpio_set_value(tsdata->reset_pin, 1);
++ msleep(300);
+ }
+
+ return 0;
+ }
+
+ static int edt_ft5x06_ts_identify(struct i2c_client *client,
+- char *model_name,
+- char *fw_version)
++ struct edt_ft5x06_ts_data *tsdata,
++ char *fw_version)
+ {
+ u8 rdbuf[EDT_NAME_LEN];
+ char *p;
+ int error;
++ char *model_name = tsdata->name;
+
++ /* see what we find if we assume it is a M06 *
++ * if we get less than EDT_NAME_LEN, we don't want
++ * to have garbage in there
++ */
++ memset(rdbuf, 0, sizeof(rdbuf));
+ error = edt_ft5x06_ts_readwrite(client, 1, "\xbb",
+ EDT_NAME_LEN - 1, rdbuf);
+ if (error)
+ return error;
+
+- /* remove last '$' end marker */
+- rdbuf[EDT_NAME_LEN - 1] = '\0';
+- if (rdbuf[EDT_NAME_LEN - 2] == '$')
+- rdbuf[EDT_NAME_LEN - 2] = '\0';
+-
+- /* look for Model/Version separator */
+- p = strchr(rdbuf, '*');
+- if (p)
+- *p++ = '\0';
++ /* if we find something consistent, stay with that assumption
++ * at least M09 won't send 3 bytes here
++ */
++ if (!(strnicmp(rdbuf + 1, "EP0", 3))) {
++ tsdata->version = M06;
++
++ /* remove last '$' end marker */
++ rdbuf[EDT_NAME_LEN - 1] = '\0';
++ if (rdbuf[EDT_NAME_LEN - 2] == '$')
++ rdbuf[EDT_NAME_LEN - 2] = '\0';
++
++ /* look for Model/Version separator */
++ p = strchr(rdbuf, '*');
++ if (p)
++ *p++ = '\0';
++ strlcpy(model_name, rdbuf + 1, EDT_NAME_LEN);
++ strlcpy(fw_version, p ? p : "", EDT_NAME_LEN);
++ } else {
++ /* since there are only two versions around (M06, M09) */
++ tsdata->version = M09;
++
++ error = edt_ft5x06_ts_readwrite(client, 1, "\xA6",
++ 2, rdbuf);
++ if (error)
++ return error;
++
++ strlcpy(fw_version, rdbuf, 2);
++
++ error = edt_ft5x06_ts_readwrite(client, 1, "\xA8",
++ 1, rdbuf);
++ if (error)
++ return error;
+
+- strlcpy(model_name, rdbuf + 1, EDT_NAME_LEN);
+- strlcpy(fw_version, p ? p : "", EDT_NAME_LEN);
++ snprintf(model_name, EDT_NAME_LEN, "EP0%i%i0M09",
++ rdbuf[0] >> 4, rdbuf[0] & 0x0F);
++ }
+
+ return 0;
+ }
+@@ -675,32 +870,108 @@
+ pdata->name <= edt_ft5x06_attr_##name.limit_high) \
+ edt_ft5x06_register_write(tsdata, reg, pdata->name)
+
++#define EDT_GET_PROP(name, reg) { \
++ u32 val; \
++ if (of_property_read_u32(np, #name, &val) == 0) \
++ edt_ft5x06_register_write(tsdata, reg, val); \
++}
++
++static void edt_ft5x06_ts_get_dt_defaults(struct device_node *np,
++ struct edt_ft5x06_ts_data *tsdata)
++{
++ struct edt_reg_addr *reg_addr = &tsdata->reg_addr;
++
++ EDT_GET_PROP(threshold, reg_addr->reg_threshold);
++ EDT_GET_PROP(gain, reg_addr->reg_gain);
++ EDT_GET_PROP(offset, reg_addr->reg_offset);
++
++ if (of_property_read_bool(np, "invert"))
++ tsdata->invert = true;
++ of_property_read_u32(np, "screen-x", &tsdata->screen_x);
++ of_property_read_u32(np, "screen-y", &tsdata->screen_y);
++}
++
+ static void
+ edt_ft5x06_ts_get_defaults(struct edt_ft5x06_ts_data *tsdata,
+ const struct edt_ft5x06_platform_data *pdata)
+ {
++ struct edt_reg_addr *reg_addr = &tsdata->reg_addr;
++
+ if (!pdata->use_parameters)
+ return;
+
+ /* pick up defaults from the platform data */
+- EDT_ATTR_CHECKSET(threshold, WORK_REGISTER_THRESHOLD);
+- EDT_ATTR_CHECKSET(gain, WORK_REGISTER_GAIN);
+- EDT_ATTR_CHECKSET(offset, WORK_REGISTER_OFFSET);
+- EDT_ATTR_CHECKSET(report_rate, WORK_REGISTER_REPORT_RATE);
++ EDT_ATTR_CHECKSET(threshold, reg_addr->reg_threshold);
++ EDT_ATTR_CHECKSET(gain, reg_addr->reg_gain);
++ EDT_ATTR_CHECKSET(offset, reg_addr->reg_offset);
++ if (reg_addr->reg_report_rate != NO_REGISTER)
++ EDT_ATTR_CHECKSET(report_rate, reg_addr->reg_report_rate);
+ }
+
+ static void
+ edt_ft5x06_ts_get_parameters(struct edt_ft5x06_ts_data *tsdata)
+ {
++ struct edt_reg_addr *reg_addr = &tsdata->reg_addr;
++
+ tsdata->threshold = edt_ft5x06_register_read(tsdata,
+- WORK_REGISTER_THRESHOLD);
+- tsdata->gain = edt_ft5x06_register_read(tsdata, WORK_REGISTER_GAIN);
+- tsdata->offset = edt_ft5x06_register_read(tsdata, WORK_REGISTER_OFFSET);
+- tsdata->report_rate = edt_ft5x06_register_read(tsdata,
+- WORK_REGISTER_REPORT_RATE);
+- tsdata->num_x = edt_ft5x06_register_read(tsdata, WORK_REGISTER_NUM_X);
+- tsdata->num_y = edt_ft5x06_register_read(tsdata, WORK_REGISTER_NUM_Y);
++ reg_addr->reg_threshold);
++ tsdata->gain = edt_ft5x06_register_read(tsdata, reg_addr->reg_gain);
++ tsdata->offset = edt_ft5x06_register_read(tsdata, reg_addr->reg_offset);
++ if (reg_addr->reg_report_rate != NO_REGISTER)
++ tsdata->report_rate = edt_ft5x06_register_read(tsdata,
++ reg_addr->reg_report_rate);
++ tsdata->num_x = edt_ft5x06_register_read(tsdata, reg_addr->reg_num_x);
++ tsdata->num_y = edt_ft5x06_register_read(tsdata, reg_addr->reg_num_y);
++}
++
++static void
++edt_ft5x06_ts_set_regs(struct edt_ft5x06_ts_data *tsdata)
++{
++ struct edt_reg_addr *reg_addr = &tsdata->reg_addr;
++
++ switch (tsdata->version) {
++ case M06:
++ reg_addr->reg_threshold = WORK_REGISTER_THRESHOLD;
++ reg_addr->reg_report_rate = WORK_REGISTER_REPORT_RATE;
++ reg_addr->reg_gain = WORK_REGISTER_GAIN;
++ reg_addr->reg_offset = WORK_REGISTER_OFFSET;
++ reg_addr->reg_num_x = WORK_REGISTER_NUM_X;
++ reg_addr->reg_num_y = WORK_REGISTER_NUM_Y;
++ break;
++
++ case M09:
++ reg_addr->reg_threshold = M09_REGISTER_THRESHOLD;
++ reg_addr->reg_gain = M09_REGISTER_GAIN;
++ reg_addr->reg_offset = M09_REGISTER_OFFSET;
++ reg_addr->reg_num_x = M09_REGISTER_NUM_X;
++ reg_addr->reg_num_y = M09_REGISTER_NUM_Y;
++ break;
++ }
++}
++
++#ifdef CONFIG_OF
++static int edt_ft5x06_i2c_ts_probe_dt(struct device *dev,
++ struct edt_ft5x06_ts_data *tsdata)
++{
++ struct device_node *np = dev->of_node;
++
++ /*
++ * irq_pin is not needed for DT setup.
++ * irq is associated via 'interrupts' property in DT
++ */
++ tsdata->irq_pin = -EINVAL;
++ tsdata->reset_pin = of_get_named_gpio(np, "reset-gpios", 0);
++ tsdata->wake_pin = of_get_named_gpio(np, "wake-gpios", 0);
++
++ return 0;
++}
++#else
++static inline int edt_ft5x06_i2c_ts_probe_dt(struct device *dev,
++ struct edt_ft5x06_ts_data *tsdata)
++{
++ return -ENODEV;
+ }
++#endif
+
+ static int edt_ft5x06_ts_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+@@ -714,32 +985,40 @@
+
+ dev_dbg(&client->dev, "probing for EDT FT5x06 I2C\n");
+
++ tsdata = devm_kzalloc(&client->dev, sizeof(*tsdata), GFP_KERNEL);
++ if (!tsdata) {
++ dev_err(&client->dev, "failed to allocate driver data.\n");
++ return -ENOMEM;
++ }
++
+ if (!pdata) {
+- dev_err(&client->dev, "no platform data?\n");
+- return -EINVAL;
++ error = edt_ft5x06_i2c_ts_probe_dt(&client->dev, tsdata);
++ if (error) {
++ dev_err(&client->dev,
++ "DT probe failed and no platform data present\n");
++ return error;
++ }
++ } else {
++ tsdata->reset_pin = pdata->reset_pin;
++ tsdata->irq_pin = pdata->irq_pin;
++ tsdata->wake_pin = -EINVAL;
+ }
+
+- error = edt_ft5x06_ts_reset(client, pdata->reset_pin);
++ error = edt_ft5x06_ts_reset(client, tsdata);
+ if (error)
+ return error;
+
+- if (gpio_is_valid(pdata->irq_pin)) {
+- error = devm_gpio_request_one(&client->dev, pdata->irq_pin,
+- GPIOF_IN, "edt-ft5x06 irq");
++ if (gpio_is_valid(tsdata->irq_pin)) {
++ error = devm_gpio_request_one(&client->dev, tsdata->irq_pin,
++ GPIOF_IN, "edt-ft5x06 irq");
+ if (error) {
+ dev_err(&client->dev,
+ "Failed to request GPIO %d, error %d\n",
+- pdata->irq_pin, error);
++ tsdata->irq_pin, error);
+ return error;
+ }
+ }
+
+- tsdata = devm_kzalloc(&client->dev, sizeof(*tsdata), GFP_KERNEL);
+- if (!tsdata) {
+- dev_err(&client->dev, "failed to allocate driver data.\n");
+- return -ENOMEM;
+- }
+-
+ input = devm_input_allocate_device(&client->dev);
+ if (!input) {
+ dev_err(&client->dev, "failed to allocate input device.\n");
+@@ -751,18 +1030,30 @@
+ tsdata->input = input;
+ tsdata->factory_mode = false;
+
+- error = edt_ft5x06_ts_identify(client, tsdata->name, fw_version);
++ error = edt_ft5x06_ts_identify(client, tsdata, fw_version);
+ if (error) {
+ dev_err(&client->dev, "touchscreen probe failed\n");
+ return error;
+ }
+
+- edt_ft5x06_ts_get_defaults(tsdata, pdata);
++ edt_ft5x06_ts_set_regs(tsdata);
++
++ if (!pdata)
++ edt_ft5x06_ts_get_dt_defaults(client->dev.of_node, tsdata);
++ else
++ edt_ft5x06_ts_get_defaults(tsdata, pdata);
++
+ edt_ft5x06_ts_get_parameters(tsdata);
++ if (!tsdata->screen_x || !tsdata->screen_y) {
++ tsdata->screen_x = tsdata->num_x * 64 - 1;
++ tsdata->screen_y = tsdata->num_y * 64 - 1;
++ }
+
+ dev_dbg(&client->dev,
+- "Model \"%s\", Rev. \"%s\", %dx%d sensors\n",
+- tsdata->name, fw_version, tsdata->num_x, tsdata->num_y);
++ "Model \"%s\", Rev. \"%s\", %dx%d sensors (%dx%d) %sinverted\n",
++ tsdata->name, fw_version, tsdata->num_x, tsdata->num_y,
++ tsdata->screen_x, tsdata->screen_y,
++ tsdata->invert ? "" : "non");
+
+ input->name = tsdata->name;
+ input->id.bustype = BUS_I2C;
+@@ -772,12 +1063,12 @@
+ __set_bit(EV_KEY, input->evbit);
+ __set_bit(EV_ABS, input->evbit);
+ __set_bit(BTN_TOUCH, input->keybit);
+- input_set_abs_params(input, ABS_X, 0, tsdata->num_x * 64 - 1, 0, 0);
+- input_set_abs_params(input, ABS_Y, 0, tsdata->num_y * 64 - 1, 0, 0);
++ input_set_abs_params(input, ABS_X, 0, tsdata->screen_x - 1, 0, 0);
++ input_set_abs_params(input, ABS_Y, 0, tsdata->screen_y - 1, 0, 0);
+ input_set_abs_params(input, ABS_MT_POSITION_X,
+- 0, tsdata->num_x * 64 - 1, 0, 0);
++ 0, tsdata->screen_x - 1, 0, 0);
+ input_set_abs_params(input, ABS_MT_POSITION_Y,
+- 0, tsdata->num_y * 64 - 1, 0, 0);
++ 0, tsdata->screen_y - 1, 0, 0);
+ error = input_mt_init_slots(input, MAX_SUPPORT_POINTS, 0);
+ if (error) {
+ dev_err(&client->dev, "Unable to init MT slots.\n");
+@@ -787,10 +1078,10 @@
+ input_set_drvdata(input, tsdata);
+ i2c_set_clientdata(client, tsdata);
+
+- error = devm_request_threaded_irq(&client->dev, client->irq,
+- NULL, edt_ft5x06_ts_isr,
+- IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+- client->name, tsdata);
++ error = devm_request_threaded_irq(&client->dev, client->irq, NULL,
++ edt_ft5x06_ts_isr,
++ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
++ client->name, tsdata);
+ if (error) {
+ dev_err(&client->dev, "Unable to request touchscreen IRQ.\n");
+ return error;
+@@ -801,19 +1092,21 @@
+ return error;
+
+ error = input_register_device(input);
+- if (error) {
+- sysfs_remove_group(&client->dev.kobj, &edt_ft5x06_attr_group);
+- return error;
+- }
++ if (error)
++ goto err_remove_attrs;
+
+ edt_ft5x06_ts_prepare_debugfs(tsdata, dev_driver_string(&client->dev));
+ device_init_wakeup(&client->dev, 1);
+
+ dev_dbg(&client->dev,
+- "EDT FT5x06 initialized: IRQ pin %d, Reset pin %d.\n",
+- pdata->irq_pin, pdata->reset_pin);
++ "EDT FT5x06 initialized: IRQ %d, WAKE pin %d, Reset pin %d.\n",
++ client->irq, tsdata->wake_pin, tsdata->reset_pin);
+
+ return 0;
++
++err_remove_attrs:
++ sysfs_remove_group(&client->dev.kobj, &edt_ft5x06_attr_group);
++ return error;
+ }
+
+ static int edt_ft5x06_ts_remove(struct i2c_client *client)
+@@ -857,10 +1150,21 @@
+ };
+ MODULE_DEVICE_TABLE(i2c, edt_ft5x06_ts_id);
+
++#ifdef CONFIG_OF
++static const struct of_device_id edt_ft5x06_of_match[] = {
++ { .compatible = "edt,edt-ft5206", },
++ { .compatible = "edt,edt-ft5306", },
++ { .compatible = "edt,edt-ft5406", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, edt_ft5x06_of_match);
++#endif
++
+ static struct i2c_driver edt_ft5x06_ts_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "edt_ft5x06",
++ .of_match_table = of_match_ptr(edt_ft5x06_of_match),
+ .pm = &edt_ft5x06_ts_pm_ops,
+ },
+ .id_table = edt_ft5x06_ts_id,
+diff -Nur linux-3.14.72.orig/drivers/input/touchscreen/elan_ts.c linux-3.14.72/drivers/input/touchscreen/elan_ts.c
+--- linux-3.14.72.orig/drivers/input/touchscreen/elan_ts.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/input/touchscreen/elan_ts.c 2016-06-19 22:11:55.165149193 +0200
+@@ -0,0 +1,472 @@
++/*
++ * Copyright (C) 2007-2008 HTC Corporation.
++ *
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
++ *
++ * This driver is adapted from elan8232_i2c.c written by Shan-Fu Chiou
++ * <sfchiou@gmail.com> and Jay Tu <jay_tu@htc.com>.
++ * This driver is also adapted from the ELAN Touch Screen driver
++ * written by Stanley Zeng <stanley.zeng@emc.com.tw>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/input.h>
++#include <linux/device.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/jiffies.h>
++#include <linux/interrupt.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/hrtimer.h>
++#include <linux/of_gpio.h>
++#include <linux/regulator/consumer.h>
++#include <linux/gpio.h>
++
++static const char ELAN_TS_NAME[] = "elan-touch";
++
++#define ELAN_TS_X_MAX 1088
++#define ELAN_TS_Y_MAX 768
++#define ELAN_USER_X_MAX 800
++#define ELAN_USER_Y_MAX 600
++#define IDX_PACKET_SIZE 8
++
++enum {
++ hello_packet = 0x55,
++ idx_coordinate_packet = 0x5a,
++};
++
++enum {
++ idx_finger_state = 7,
++};
++
++static struct workqueue_struct *elan_wq;
++
++static struct elan_data {
++ int intr_gpio;
++ int use_irq;
++ struct hrtimer timer;
++ struct work_struct work;
++ struct i2c_client *client;
++ struct input_dev *input;
++ wait_queue_head_t wait;
++} elan_touch_data;
++
++/*--------------------------------------------------------------*/
++static int elan_touch_detect_int_level(void)
++{
++ int v;
++ v = gpio_get_value(elan_touch_data.intr_gpio);
++
++ return v;
++}
++
++static int __elan_touch_poll(struct i2c_client *client)
++{
++ int status = 0, retry = 20;
++
++ do {
++ status = elan_touch_detect_int_level();
++ retry--;
++ mdelay(20);
++ } while (status == 1 && retry > 0);
++
++ return (status == 0 ? 0 : -ETIMEDOUT);
++}
++
++static int elan_touch_poll(struct i2c_client *client)
++{
++ return __elan_touch_poll(client);
++}
++
++static int __hello_packet_handler(struct i2c_client *client)
++{
++ int rc;
++ uint8_t buf_recv[4] = { 0 };
++
++ rc = elan_touch_poll(client);
++
++ if (rc < 0)
++ return -EINVAL;
++
++ rc = i2c_master_recv(client, buf_recv, 4);
++
++ if (rc != 4) {
++ return rc;
++ } else {
++ int i;
++ pr_info("hello packet: [0x%02x 0x%02x 0x%02x 0x%02x]\n",
++ buf_recv[0], buf_recv[1], buf_recv[2], buf_recv[3]);
++
++ for (i = 0; i < 4; i++)
++ if (buf_recv[i] != hello_packet)
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static inline int elan_touch_parse_xy(uint8_t *data, uint16_t *x,
++ uint16_t *y)
++{
++ *x = (data[0] & 0xf0);
++ *x <<= 4;
++ *x |= data[1];
++ if (*x >= ELAN_TS_X_MAX)
++ *x = ELAN_TS_X_MAX;
++ *x = ((((ELAN_TS_X_MAX -
++ *x) * 1000) / ELAN_TS_X_MAX) * ELAN_USER_X_MAX) / 1000;
++
++ *y = (data[0] & 0x0f);
++ *y <<= 8;
++ *y |= data[2];
++ if (*y >= ELAN_TS_Y_MAX)
++ *y = ELAN_TS_Y_MAX;
++ *y = ((((ELAN_TS_Y_MAX -
++ *y) * 1000) / ELAN_TS_Y_MAX) * ELAN_USER_Y_MAX) / 1000;
++
++ return 0;
++}
++
++/* __elan_touch_init -- hand shaking with touch panel
++ *
++ * 1.recv hello packet
++ */
++static int __elan_touch_init(struct i2c_client *client)
++{
++ int rc;
++ rc = __hello_packet_handler(client);
++ if (rc < 0)
++ goto hand_shake_failed;
++
++hand_shake_failed:
++ return rc;
++}
++
++static int elan_touch_recv_data(struct i2c_client *client, uint8_t * buf)
++{
++ int rc, bytes_to_recv = IDX_PACKET_SIZE;
++
++ if (buf == NULL)
++ return -EINVAL;
++
++ memset(buf, 0, bytes_to_recv);
++ rc = i2c_master_recv(client, buf, bytes_to_recv);
++ if (rc != bytes_to_recv)
++ return -EINVAL;
++
++ return rc;
++}
++
++static void elan_touch_report_data(struct i2c_client *client, uint8_t * buf)
++{
++ switch (buf[0]) {
++ case idx_coordinate_packet:
++ {
++ uint16_t x1, x2, y1, y2;
++ uint8_t finger_stat;
++
++ finger_stat = (buf[idx_finger_state] & 0x06) >> 1;
++
++ if (finger_stat == 0) {
++ input_report_key(elan_touch_data.input, BTN_TOUCH, 0);
++ input_report_key(elan_touch_data.input, BTN_2, 0);
++ } else if (finger_stat == 1) {
++ elan_touch_parse_xy(&buf[1], &x1, &y1);
++ input_report_abs(elan_touch_data.input, ABS_X, x1);
++ input_report_abs(elan_touch_data.input, ABS_Y, y1);
++ input_report_key(elan_touch_data.input, BTN_TOUCH, 1);
++ input_report_key(elan_touch_data.input, BTN_2, 0);
++ } else if (finger_stat == 2) {
++ elan_touch_parse_xy(&buf[1], &x1, &y1);
++ input_report_abs(elan_touch_data.input, ABS_X, x1);
++ input_report_abs(elan_touch_data.input, ABS_Y, y1);
++ input_report_key(elan_touch_data.input, BTN_TOUCH, 1);
++ elan_touch_parse_xy(&buf[4], &x2, &y2);
++ input_report_abs(elan_touch_data.input, ABS_HAT0X, x2);
++ input_report_abs(elan_touch_data.input, ABS_HAT0Y, y2);
++ input_report_key(elan_touch_data.input, BTN_2, 1);
++ }
++ input_sync(elan_touch_data.input);
++ break;
++ }
++
++ default:
++ break;
++ }
++}
++
++static void elan_touch_work_func(struct work_struct *work)
++{
++ int rc;
++ uint8_t buf[IDX_PACKET_SIZE] = { 0 };
++ struct i2c_client *client = elan_touch_data.client;
++
++ if (elan_touch_detect_int_level())
++ return;
++
++ rc = elan_touch_recv_data(client, buf);
++ if (rc < 0)
++ return;
++
++ elan_touch_report_data(client, buf);
++}
++
++static irqreturn_t elan_touch_ts_interrupt(int irq, void *dev_id)
++{
++ queue_work(elan_wq, &elan_touch_data.work);
++
++ return IRQ_HANDLED;
++}
++
++static enum hrtimer_restart elan_touch_timer_func(struct hrtimer *timer)
++{
++ queue_work(elan_wq, &elan_touch_data.work);
++ hrtimer_start(&elan_touch_data.timer, ktime_set(0, 12500000),
++ HRTIMER_MODE_REL);
++
++ return HRTIMER_NORESTART;
++}
++
++static int elan_touch_register_interrupt(struct i2c_client *client)
++{
++ int err = 0;
++
++ if (client->irq) {
++ elan_touch_data.use_irq = 1;
++ err =
++ request_irq(client->irq, elan_touch_ts_interrupt,
++ IRQF_TRIGGER_FALLING, ELAN_TS_NAME,
++ &elan_touch_data);
++
++ if (err < 0) {
++ pr_info("%s(%s): Can't allocate irq %d\n", __FILE__,
++ __func__, client->irq);
++ elan_touch_data.use_irq = 0;
++ }
++ }
++
++ if (!elan_touch_data.use_irq) {
++ hrtimer_init(&elan_touch_data.timer, CLOCK_MONOTONIC,
++ HRTIMER_MODE_REL);
++ elan_touch_data.timer.function = elan_touch_timer_func;
++ hrtimer_start(&elan_touch_data.timer, ktime_set(1, 0),
++ HRTIMER_MODE_REL);
++ }
++
++ pr_info("elan ts starts in %s mode.\n",
++ elan_touch_data.use_irq == 1 ? "interrupt" : "polling");
++
++ return 0;
++}
++
++static int elan_touch_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct device_node *np = client->dev.of_node;
++ int gpio_elan_cs, gpio_elan_rst, err = 0;
++
++ if (!np)
++ return -ENODEV;
++
++ elan_touch_data.intr_gpio = of_get_named_gpio(np, "gpio_intr", 0);
++ if (!gpio_is_valid(elan_touch_data.intr_gpio))
++ return -ENODEV;
++
++ err = devm_gpio_request_one(&client->dev, elan_touch_data.intr_gpio,
++ GPIOF_IN, "gpio_elan_intr");
++ if (err < 0) {
++ dev_err(&client->dev,
++ "request gpio failed: %d\n", err);
++ return err;
++ }
++
++ /* elan touch init */
++ gpio_elan_cs = of_get_named_gpio(np, "gpio_elan_cs", 0);
++ if (!gpio_is_valid(gpio_elan_cs))
++ return -ENODEV;
++
++ err = devm_gpio_request_one(&client->dev, gpio_elan_cs,
++ GPIOF_OUT_INIT_HIGH, "gpio_elan_cs");
++ if (err < 0) {
++ dev_err(&client->dev,
++ "request gpio failed: %d\n", err);
++ return err;
++ }
++ gpio_set_value(gpio_elan_cs, 0);
++
++ gpio_elan_rst = of_get_named_gpio(np, "gpio_elan_rst", 0);
++ if (!gpio_is_valid(gpio_elan_rst))
++ return -ENODEV;
++
++ err = devm_gpio_request_one(&client->dev, gpio_elan_rst,
++ GPIOF_OUT_INIT_HIGH, "gpio_elan_rst");
++ if (err < 0) {
++ dev_err(&client->dev,
++ "request gpio failed: %d\n", err);
++ return err;
++ }
++ gpio_set_value(gpio_elan_rst, 0);
++ msleep(10);
++ gpio_set_value(gpio_elan_rst, 1);
++
++ gpio_set_value(gpio_elan_cs, 1);
++ msleep(100);
++
++ elan_wq = create_singlethread_workqueue("elan_wq");
++ if (!elan_wq) {
++ err = -ENOMEM;
++ goto fail;
++ }
++
++ elan_touch_data.client = client;
++ strlcpy(client->name, ELAN_TS_NAME, I2C_NAME_SIZE);
++
++ INIT_WORK(&elan_touch_data.work, elan_touch_work_func);
++
++ elan_touch_data.input = input_allocate_device();
++ if (elan_touch_data.input == NULL) {
++ err = -ENOMEM;
++ goto fail;
++ }
++
++ err = __elan_touch_init(client);
++ if (err < 0) {
++ dev_err(&client->dev, "elan - Read Hello Packet Failed\n");
++ goto fail;
++ }
++
++ elan_touch_data.input->name = ELAN_TS_NAME;
++ elan_touch_data.input->id.bustype = BUS_I2C;
++
++ set_bit(EV_SYN, elan_touch_data.input->evbit);
++
++ set_bit(EV_KEY, elan_touch_data.input->evbit);
++ set_bit(BTN_TOUCH, elan_touch_data.input->keybit);
++ set_bit(BTN_2, elan_touch_data.input->keybit);
++
++ set_bit(EV_ABS, elan_touch_data.input->evbit);
++ set_bit(ABS_X, elan_touch_data.input->absbit);
++ set_bit(ABS_Y, elan_touch_data.input->absbit);
++ set_bit(ABS_HAT0X, elan_touch_data.input->absbit);
++ set_bit(ABS_HAT0Y, elan_touch_data.input->absbit);
++
++ input_set_abs_params(elan_touch_data.input, ABS_X, 0, ELAN_USER_X_MAX,
++ 0, 0);
++ input_set_abs_params(elan_touch_data.input, ABS_Y, 0, ELAN_USER_Y_MAX,
++ 0, 0);
++ input_set_abs_params(elan_touch_data.input, ABS_HAT0X, 0,
++ ELAN_USER_X_MAX, 0, 0);
++ input_set_abs_params(elan_touch_data.input, ABS_HAT0Y, 0,
++ ELAN_USER_Y_MAX, 0, 0);
++
++ err = input_register_device(elan_touch_data.input);
++ if (err < 0)
++ goto fail;
++
++ elan_touch_register_interrupt(elan_touch_data.client);
++
++ return 0;
++
++fail:
++ input_free_device(elan_touch_data.input);
++ if (elan_wq)
++ destroy_workqueue(elan_wq);
++ return err;
++}
++
++static int elan_touch_remove(struct i2c_client *client)
++{
++ if (elan_wq)
++ destroy_workqueue(elan_wq);
++
++ input_unregister_device(elan_touch_data.input);
++
++ if (elan_touch_data.use_irq)
++ free_irq(client->irq, client);
++ else
++ hrtimer_cancel(&elan_touch_data.timer);
++ return 0;
++}
++
++/* -------------------------------------------------------------------- */
++static const struct i2c_device_id elan_touch_id[] = {
++ {"elan-touch", 0},
++ {}
++};
++
++static const struct of_device_id elan_dt_ids[] = {
++ {
++ .compatible = "elan,elan-touch",
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, elan_dt_ids);
++
++static int elan_suspend(struct device *dev)
++{
++ return 0;
++}
++
++static int elan_resume(struct device *dev)
++{
++ uint8_t buf[IDX_PACKET_SIZE] = { 0 };
++
++ if (0 == elan_touch_detect_int_level()) {
++ dev_dbg(dev, "Got touch during suspend period.\n");
++ /*
++ * if touch screen during suspend, recv and drop the
++ * data, then touch interrupt pin will return high after
++ * receving data.
++ */
++ elan_touch_recv_data(elan_touch_data.client, buf);
++ }
++
++ return 0;
++}
++
++static const struct dev_pm_ops elan_dev_pm_ops = {
++ .suspend = elan_suspend,
++ .resume = elan_resume,
++};
++
++static struct i2c_driver elan_touch_driver = {
++ .probe = elan_touch_probe,
++ .remove = elan_touch_remove,
++ .id_table = elan_touch_id,
++ .driver = {
++ .name = "elan-touch",
++ .owner = THIS_MODULE,
++ .of_match_table = elan_dt_ids,
++#ifdef CONFIG_PM
++ .pm = &elan_dev_pm_ops,
++#endif
++ },
++};
++
++static int __init elan_touch_init(void)
++{
++ return i2c_add_driver(&elan_touch_driver);
++}
++
++static void __exit elan_touch_exit(void)
++{
++ i2c_del_driver(&elan_touch_driver);
++}
++
++module_init(elan_touch_init);
++module_exit(elan_touch_exit);
++
++MODULE_AUTHOR("Stanley Zeng <stanley.zeng@emc.com.tw>");
++MODULE_DESCRIPTION("ELAN Touch Screen driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/input/touchscreen/goodix.c linux-3.14.72/drivers/input/touchscreen/goodix.c
+--- linux-3.14.72.orig/drivers/input/touchscreen/goodix.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/input/touchscreen/goodix.c 2016-06-19 22:11:55.165149193 +0200
+@@ -0,0 +1,482 @@
++/*
++ * Driver for Goodix Touchscreens
++ *
++ * Copyright (c) 2014 Red Hat Inc.
++ *
++ * This code is based on gt9xx.c authored by andrew@goodix.com:
++ *
++ * 2010 - 2012 Goodix Technology.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the Free
++ * Software Foundation; version 2 of the License.
++ */
++
++#include <linux/kernel.h>
++#include <linux/gpio.h>
++#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/input/mt.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <linux/of_gpio.h>
++#include <asm/unaligned.h>
++
++struct goodix_ts_data {
++ struct i2c_client *client;
++ struct input_dev *input_dev;
++ int abs_x_max;
++ int abs_y_max;
++ unsigned int max_touch_num;
++ unsigned int int_trigger_type;
++ bool invert;
++ bool rotate;
++};
++
++#define GOODIX_MAX_HEIGHT 4096
++#define GOODIX_MAX_WIDTH 4096
++#define GOODIX_INT_TRIGGER 1
++#define GOODIX_CONTACT_SIZE 8
++#define GOODIX_MAX_CONTACTS 10
++
++#define GOODIX_CONFIG_MAX_LENGTH 240
++
++/* Register defines */
++#define GOODIX_READ_COOR_ADDR 0x814E
++#define GOODIX_REG_CONFIG_DATA 0x8047
++#define GOODIX_REG_VERSION 0x8140
++
++#define RESOLUTION_LOC 1
++#define TRIGGER_LOC 6
++
++static const unsigned long goodix_irq_flags[] = {
++ IRQ_TYPE_EDGE_RISING,
++ IRQ_TYPE_EDGE_FALLING,
++ IRQ_TYPE_LEVEL_LOW,
++ IRQ_TYPE_LEVEL_HIGH,
++};
++
++/**
++ * goodix_i2c_read - read data from a register of the i2c slave device.
++ *
++ * @client: i2c device.
++ * @reg: the register to read from.
++ * @buf: raw write data buffer.
++ * @len: length of the buffer to write
++ */
++static int goodix_i2c_read(struct i2c_client *client,
++ u16 reg, u8 *buf, int len)
++{
++ struct i2c_msg msgs[2];
++ u16 wbuf = cpu_to_be16(reg);
++ int ret;
++
++ msgs[0].flags = 0;
++ msgs[0].addr = client->addr;
++ msgs[0].len = 2;
++ msgs[0].buf = (u8 *) &wbuf;
++
++ msgs[1].flags = I2C_M_RD;
++ msgs[1].addr = client->addr;
++ msgs[1].len = len;
++ msgs[1].buf = buf;
++
++ ret = i2c_transfer(client->adapter, msgs, 2);
++ return ret < 0 ? ret : (ret != ARRAY_SIZE(msgs) ? -EIO : 0);
++}
++
++static int goodix_ts_read_input_report(struct goodix_ts_data *ts, u8 *data)
++{
++ int touch_num;
++ int error;
++
++ error = goodix_i2c_read(ts->client, GOODIX_READ_COOR_ADDR, data,
++ GOODIX_CONTACT_SIZE + 1);
++ if (error) {
++ dev_err(&ts->client->dev, "I2C transfer error: %d\n", error);
++ return error;
++ }
++
++ touch_num = data[0] & 0x0f;
++ if (touch_num > GOODIX_MAX_CONTACTS)
++ return -EPROTO;
++
++ if (touch_num > 1) {
++ data += 1 + GOODIX_CONTACT_SIZE;
++ error = goodix_i2c_read(ts->client,
++ GOODIX_READ_COOR_ADDR +
++ 1 + GOODIX_CONTACT_SIZE,
++ data,
++ GOODIX_CONTACT_SIZE * (touch_num - 1));
++ if (error)
++ return error;
++ }
++
++ return touch_num;
++}
++
++static void goodix_ts_report_touch(struct goodix_ts_data *ts, u8 *coor_data)
++{
++ int id = coor_data[0] & 0x0F;
++ int input_x = get_unaligned_le16(&coor_data[1]);
++ int input_y = get_unaligned_le16(&coor_data[3]);
++ int input_w = get_unaligned_le16(&coor_data[5]);
++
++ input_mt_slot(ts->input_dev, id);
++ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, true);
++ if (ts->invert) {
++ input_x = ts->abs_x_max - input_x;
++ input_y = ts->abs_y_max - input_y;
++ }
++ if (ts->rotate) {
++ input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, input_x);
++ input_report_abs(ts->input_dev, ABS_MT_POSITION_X, input_y);
++ } else {
++ input_report_abs(ts->input_dev, ABS_MT_POSITION_X, input_x);
++ input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, input_y);
++ }
++ input_report_abs(ts->input_dev, ABS_MT_TOUCH_MAJOR, input_w);
++ input_report_abs(ts->input_dev, ABS_MT_WIDTH_MAJOR, input_w);
++}
++
++/**
++ * goodix_process_events - Process incoming events
++ *
++ * @ts: our goodix_ts_data pointer
++ *
++ * Called when the IRQ is triggered. Read the current device state, and push
++ * the input events to the user space.
++ */
++static void goodix_process_events(struct goodix_ts_data *ts)
++{
++ u8 point_data[1 + GOODIX_CONTACT_SIZE * GOODIX_MAX_CONTACTS];
++ int touch_num;
++ int i;
++
++ touch_num = goodix_ts_read_input_report(ts, point_data);
++ if (touch_num < 0)
++ return;
++
++ for (i = 0; i < touch_num; i++)
++ goodix_ts_report_touch(ts,
++ &point_data[1 + GOODIX_CONTACT_SIZE * i]);
++
++ input_mt_sync_frame(ts->input_dev);
++ input_sync(ts->input_dev);
++}
++
++/**
++ * goodix_ts_irq_handler - The IRQ handler
++ *
++ * @irq: interrupt number.
++ * @dev_id: private data pointer.
++ */
++static irqreturn_t goodix_ts_irq_handler(int irq, void *dev_id)
++{
++ static const u8 end_cmd[] = {
++ GOODIX_READ_COOR_ADDR >> 8,
++ GOODIX_READ_COOR_ADDR & 0xff,
++ 0
++ };
++ struct goodix_ts_data *ts = dev_id;
++
++ goodix_process_events(ts);
++
++ if (i2c_master_send(ts->client, end_cmd, sizeof(end_cmd)) < 0)
++ dev_err(&ts->client->dev, "I2C write end_cmd error\n");
++
++ return IRQ_HANDLED;
++}
++
++/**
++ * goodix_read_config - Read the embedded configuration of the panel
++ *
++ * @ts: our goodix_ts_data pointer
++ *
++ * Must be called during probe
++ */
++static void goodix_read_config(struct goodix_ts_data *ts)
++{
++ u8 config[GOODIX_CONFIG_MAX_LENGTH];
++ int error;
++
++ error = goodix_i2c_read(ts->client, GOODIX_REG_CONFIG_DATA,
++ config,
++ GOODIX_CONFIG_MAX_LENGTH);
++ if (error) {
++ dev_warn(&ts->client->dev,
++ "Error reading config (%d), using defaults\n",
++ error);
++ ts->abs_x_max = GOODIX_MAX_WIDTH;
++ ts->abs_y_max = GOODIX_MAX_HEIGHT;
++ ts->int_trigger_type = GOODIX_INT_TRIGGER;
++ return;
++ }
++
++ if (ts->rotate) {
++ ts->abs_x_max = get_unaligned_le16(&config[RESOLUTION_LOC + 2]);
++ ts->abs_y_max = get_unaligned_le16(&config[RESOLUTION_LOC]);
++ } else {
++ ts->abs_x_max = get_unaligned_le16(&config[RESOLUTION_LOC]);
++ ts->abs_y_max = get_unaligned_le16(&config[RESOLUTION_LOC + 2]);
++ }
++ ts->int_trigger_type = (config[TRIGGER_LOC]) & 0x03;
++ if (!ts->abs_x_max || !ts->abs_y_max) {
++ dev_err(&ts->client->dev,
++ "Invalid config, using defaults\n");
++ ts->abs_x_max = GOODIX_MAX_WIDTH;
++ ts->abs_y_max = GOODIX_MAX_HEIGHT;
++ }
++}
++
++
++/**
++ * goodix_read_version - Read goodix touchscreen version
++ *
++ * @client: the i2c client
++ * @version: output buffer containing the version on success
++ */
++static int goodix_read_version(struct i2c_client *client, u16 *version)
++{
++ int error;
++ u8 buf[6];
++
++ error = goodix_i2c_read(client, GOODIX_REG_VERSION, buf, sizeof(buf));
++ if (error) {
++ dev_err(&client->dev, "read version failed: %d\n", error);
++ return error;
++ }
++
++ if (version)
++ *version = get_unaligned_le16(&buf[4]);
++
++ dev_info(&client->dev, "IC VERSION: %6ph\n", buf);
++
++ return 0;
++}
++
++/**
++ * goodix_i2c_test - I2C test function to check if the device answers.
++ *
++ * @client: the i2c client
++ */
++static int goodix_i2c_test(struct i2c_client *client)
++{
++ int retry = 0;
++ int error;
++ u8 test;
++
++ while (retry++ < 2) {
++ error = goodix_i2c_read(client, GOODIX_REG_CONFIG_DATA,
++ &test, 1);
++ if (!error)
++ return 0;
++
++ dev_err(&client->dev, "i2c test failed attempt %d: %d\n",
++ retry, error);
++ msleep(20);
++ }
++
++ return error;
++}
++
++/**
++ * goodix_request_input_dev - Allocate, populate and register the input device
++ *
++ * @ts: our goodix_ts_data pointer
++ *
++ * Must be called during probe
++ */
++static int goodix_request_input_dev(struct goodix_ts_data *ts)
++{
++ int error;
++
++ ts->input_dev = devm_input_allocate_device(&ts->client->dev);
++ if (!ts->input_dev) {
++ dev_err(&ts->client->dev, "Failed to allocate input device.");
++ return -ENOMEM;
++ }
++
++ ts->input_dev->evbit[0] = BIT_MASK(EV_SYN) |
++ BIT_MASK(EV_KEY) |
++ BIT_MASK(EV_ABS);
++
++ input_set_abs_params(ts->input_dev, ABS_MT_POSITION_X, 0,
++ ts->abs_x_max, 0, 0);
++ input_set_abs_params(ts->input_dev, ABS_MT_POSITION_Y, 0,
++ ts->abs_y_max, 0, 0);
++ input_set_abs_params(ts->input_dev, ABS_MT_WIDTH_MAJOR, 0, 255, 0, 0);
++ input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
++
++ input_mt_init_slots(ts->input_dev, GOODIX_MAX_CONTACTS,
++ INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED);
++
++ ts->input_dev->name = "Goodix Capacitive TouchScreen";
++ ts->input_dev->phys = "input/ts";
++ ts->input_dev->id.bustype = BUS_I2C;
++ ts->input_dev->id.vendor = 0x0416;
++ ts->input_dev->id.product = 0x1001;
++ ts->input_dev->id.version = 10427;
++
++ error = input_register_device(ts->input_dev);
++ if (error) {
++ dev_err(&ts->client->dev,
++ "Failed to register input device: %d", error);
++ return error;
++ }
++
++ return 0;
++}
++
++static int goodix_ts_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct goodix_ts_data *ts;
++ unsigned long irq_flags;
++ int error;
++ u16 version_info;
++#ifdef CONFIG_OF
++ int reset_pin;
++ int int_pin;
++ struct device_node *np = client->dev.of_node;
++#endif
++
++ dev_dbg(&client->dev, "I2C Address: 0x%02x\n", client->addr);
++
++ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++ dev_err(&client->dev, "I2C check functionality failed.\n");
++ return -ENXIO;
++ }
++
++ ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
++ if (!ts)
++ return -ENOMEM;
++
++#ifdef CONFIG_OF
++ /*
++ * The GT9110 requires that INT be driven low by the host for 50ms
++ * after sampling the state of INT to determine its slave address.
++ * If reset-gpio and int-gpio are provided in the device-tree, perform
++ * this init sequence.
++ */
++ reset_pin = of_get_named_gpio(np, "reset-gpio", 0);
++ int_pin = of_get_named_gpio(np, "int-gpio", 0);
++ if (gpio_is_valid(reset_pin) && gpio_is_valid(int_pin)) {
++ int int_val = (client->addr == 0x14) ?
++ GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++
++ error = devm_gpio_request_one(&client->dev,
++ reset_pin, GPIOF_OUT_INIT_LOW,
++ "gtxx reset");
++ if (error) {
++ dev_err(&client->dev,
++ "Failed to request gpio%d reset pin: %d\n",
++ reset_pin, error);
++ return error;
++ }
++ error = devm_gpio_request_one(&client->dev,
++ int_pin, int_val, "gtxx int");
++ if (error) {
++ dev_err(&client->dev,
++ "Failed to request gpio%d int pin: %d\n",
++ int_pin, error);
++ return error;
++ }
++
++ msleep(5);
++ gpio_set_value(reset_pin, 1);
++ msleep(5);
++ gpio_set_value(int_pin, 0);
++ msleep(50);
++ gpio_direction_input(int_pin);
++
++ dev_info(&client->dev, "Performed init sequence using "
++ "gpio%d/gpio%d as RST#/INT\n", reset_pin, int_pin);
++ }
++
++ if (of_property_read_bool(np, "invert"))
++ ts->invert = true;
++ if (of_property_read_bool(np, "rotate"))
++ ts->rotate = true;
++#endif
++
++ ts->client = client;
++ i2c_set_clientdata(client, ts);
++
++ error = goodix_i2c_test(client);
++ if (error) {
++ dev_err(&client->dev, "I2C communication failure: %d\n", error);
++ return error;
++ }
++
++ error = goodix_read_version(client, &version_info);
++ if (error) {
++ dev_err(&client->dev, "Read version failed.\n");
++ return error;
++ }
++
++ goodix_read_config(ts);
++
++ error = goodix_request_input_dev(ts);
++ if (error)
++ return error;
++
++ irq_flags = goodix_irq_flags[ts->int_trigger_type] | IRQF_ONESHOT;
++ error = devm_request_threaded_irq(&ts->client->dev, client->irq,
++ NULL, goodix_ts_irq_handler,
++ irq_flags, client->name, ts);
++ if (error) {
++ dev_err(&client->dev, "request IRQ failed: %d\n", error);
++ return error;
++ }
++
++ return 0;
++}
++
++static const struct i2c_device_id goodix_ts_id[] = {
++ { "GDIX1001:00", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, goodix_ts_id);
++
++#ifdef CONFIG_ACPI
++static const struct acpi_device_id goodix_acpi_match[] = {
++ { "GDIX1001", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(acpi, goodix_acpi_match);
++#endif
++
++#ifdef CONFIG_OF
++static const struct of_device_id goodix_of_match[] = {
++ { .compatible = "gdx,gt9xx", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, goodix_of_match);
++#endif
++
++static struct i2c_driver goodix_ts_driver = {
++ .probe = goodix_ts_probe,
++ .id_table = goodix_ts_id,
++ .driver = {
++ .name = "Goodix-TS",
++ .owner = THIS_MODULE,
++#ifdef CONFIG_ACPI
++ .acpi_match_table = goodix_acpi_match,
++#endif
++#ifdef CONFIG_OF
++ .of_match_table = of_match_ptr(goodix_of_match),
++#endif
++ },
++};
++module_i2c_driver(goodix_ts_driver);
++
++MODULE_AUTHOR("Benjamin Tissoires <benjamin.tissoires@gmail.com>");
++MODULE_AUTHOR("Bastien Nocera <hadess@hadess.net>");
++MODULE_DESCRIPTION("Goodix touchscreen driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/input/touchscreen/Kconfig linux-3.14.72/drivers/input/touchscreen/Kconfig
+--- linux-3.14.72.orig/drivers/input/touchscreen/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/touchscreen/Kconfig 2016-06-19 22:11:55.165149193 +0200
+@@ -265,6 +265,18 @@
+ To compile this driver as a module, choose M here: the
+ module will be called egalax_ts.
+
++config TOUCHSCREEN_ELAN
++ tristate "ELAN touchscreen input driver"
++ depends on I2C
++ help
++ Say Y here if you have an I2C ELAN touchscreen
++ attached.
++
++ If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ module will be called elan-touch.
++
+ config TOUCHSCREEN_FUJITSU
+ tristate "Fujitsu serial touchscreen"
+ select SERIO
+@@ -278,6 +290,19 @@
+ To compile this driver as a module, choose M here: the
+ module will be called fujitsu-ts.
+
++config TOUCHSCREEN_GOODIX
++ tristate "Goodix I2C touchscreen"
++ depends on I2C
++ help
++ Say Y here if you have the Goodix touchscreen (such as one
++ installed in Onda v975w tablets) connected to your
++ system.
++
++ If unsure, say N.
++
++ To compile this driver as a module, choose M here: the
++ module will be called goodix.
++
+ config TOUCHSCREEN_ILI210X
+ tristate "Ilitek ILI210X based touchscreen"
+ depends on I2C
+diff -Nur linux-3.14.72.orig/drivers/input/touchscreen/Makefile linux-3.14.72/drivers/input/touchscreen/Makefile
+--- linux-3.14.72.orig/drivers/input/touchscreen/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/touchscreen/Makefile 2016-06-19 22:11:55.165149193 +0200
+@@ -31,6 +31,7 @@
+ obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o
+ obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o
++obj-$(CONFIG_TOUCHSCREEN_ELAN) += elan_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o
+diff -Nur linux-3.14.72.orig/drivers/input/touchscreen/max11801_ts.c linux-3.14.72/drivers/input/touchscreen/max11801_ts.c
+--- linux-3.14.72.orig/drivers/input/touchscreen/max11801_ts.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/input/touchscreen/max11801_ts.c 2016-06-19 22:11:55.165149193 +0200
+@@ -2,7 +2,7 @@
+ * Driver for MAXI MAX11801 - A Resistive touch screen controller with
+ * i2c interface
+ *
+- * Copyright (C) 2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ * Author: Zhang Jiejing <jiejing.zhang@freescale.com>
+ *
+ * Based on mcs5000_ts.c
+@@ -38,6 +38,10 @@
+ #include <linux/input.h>
+ #include <linux/slab.h>
+ #include <linux/bitops.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
+
+ /* Register Address define */
+ #define GENERNAL_STATUS_REG 0x00
+@@ -53,13 +57,30 @@
+ #define AUX_MESURE_CONF_REG 0x0a
+ #define OP_MODE_CONF_REG 0x0b
+
++#define Panel_Setup_X (0x69 << 1)
++#define Panel_Setup_Y (0x6b << 1)
++
++#define XY_combined_measurement (0x70 << 1)
++#define X_measurement (0x78 << 1)
++#define Y_measurement (0x7a << 1)
++#define AUX_measurement (0x76 << 1)
++
+ /* FIFO is found only in max11800 and max11801 */
+ #define FIFO_RD_CMD (0x50 << 1)
+ #define MAX11801_FIFO_INT (1 << 2)
+ #define MAX11801_FIFO_OVERFLOW (1 << 3)
++#define MAX11801_EDGE_INT (1 << 1)
++
++#define FIFO_RD_X_MSB (0x52 << 1)
++#define FIFO_RD_X_LSB (0x53 << 1)
++#define FIFO_RD_Y_MSB (0x54 << 1)
++#define FIFO_RD_Y_LSB (0x55 << 1)
++#define FIFO_RD_AUX_MSB (0x5a << 1)
++#define FIFO_RD_AUX_LSB (0x5b << 1)
+
+ #define XY_BUFSIZE 4
+ #define XY_BUF_OFFSET 4
++#define AUX_BUFSIZE 2
+
+ #define MAX11801_MAX_X 0xfff
+ #define MAX11801_MAX_Y 0xfff
+@@ -84,6 +105,64 @@
+ struct input_dev *input_dev;
+ };
+
++static struct i2c_client *max11801_client;
++static unsigned int max11801_workmode;
++static u8 aux_buf[AUX_BUFSIZE];
++
++static int max11801_dcm_write_command(struct i2c_client *client, int command)
++{
++ return i2c_smbus_write_byte(client, command);
++}
++
++static u32 max11801_dcm_sample_aux(struct i2c_client *client)
++{
++ int ret;
++ int aux = 0;
++ u32 sample_data;
++
++ /* AUX_measurement */
++ max11801_dcm_write_command(client, AUX_measurement);
++ mdelay(5);
++ ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_AUX_MSB,
++ 1, &aux_buf[0]);
++ if (ret < 1) {
++ dev_err(&client->dev, "FIFO_RD_AUX_MSB read fails\n");
++ return ret;
++ }
++ mdelay(5);
++ ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_AUX_LSB,
++ 1, &aux_buf[1]);
++ if (ret < 1) {
++ dev_err(&client->dev, "FIFO_RD_AUX_LSB read fails\n");
++ return ret;
++ }
++
++ aux = (aux_buf[0] << 4) + (aux_buf[1] >> 4);
++ /*
++ * voltage = (9170*aux)/7371;
++ * voltage is (26.2*3150*aux)/(16.2*0xFFF)
++ * V(aux)=3150*sample/0xFFF,V(battery)=212*V(aux)/81
++ * sample_data = (14840*aux)/7371-1541;
++ */
++ sample_data = (14840 * aux) / 7371;
++
++ return sample_data;
++}
++
++u32 max11801_read_adc(void)
++{
++ u32 adc_data;
++
++ if (!max11801_client) {
++ pr_err("FAIL max11801_client not initialize\n");
++ return -1;
++ }
++ adc_data = max11801_dcm_sample_aux(max11801_client);
++
++ return adc_data;
++}
++EXPORT_SYMBOL_GPL(max11801_read_adc);
++
+ static u8 read_register(struct i2c_client *client, int addr)
+ {
+ /* XXX: The chip ignores LSB of register address */
+@@ -104,29 +183,62 @@
+ u8 buf[XY_BUFSIZE];
+ int x = -1;
+ int y = -1;
++ u8 command = FIFO_RD_X_MSB;
+
+ status = read_register(data->client, GENERNAL_STATUS_REG);
+-
+- if (status & (MAX11801_FIFO_INT | MAX11801_FIFO_OVERFLOW)) {
++ if ((!max11801_workmode && (status & (MAX11801_FIFO_INT |
++ MAX11801_FIFO_OVERFLOW))) || (max11801_workmode && (status &
++ MAX11801_EDGE_INT))) {
+ status = read_register(data->client, GENERNAL_STATUS_REG);
++ if (!max11801_workmode) {
++ /* ACM mode */
++ ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD,
++ XY_BUFSIZE, buf);
++ /*
++ * We should get 4 bytes buffer that contains X,Y
++ * and event tag
++ */
++ if (ret < XY_BUFSIZE)
++ goto out;
++ } else {
++ /* DCM mode */
++ /* X = panel setup */
++ max11801_dcm_write_command(client, Panel_Setup_X);
++ /* X_measurement */
++ max11801_dcm_write_command(client, X_measurement);
++ for (i = 0; i < 2; i++) {
++ ret = i2c_smbus_read_i2c_block_data(client,
++ command, 1, &buf[i]);
++ if (ret < 1)
++ goto out;
++
++ command = FIFO_RD_X_LSB;
++ }
++
++ /* Y = panel setup */
++ max11801_dcm_write_command(client, Panel_Setup_Y);
++ /* Y_measurement */
++ max11801_dcm_write_command(client, Y_measurement);
++ command = FIFO_RD_Y_MSB;
++ for (i = 2; i < XY_BUFSIZE; i++) {
++ ret = i2c_smbus_read_i2c_block_data(client,
++ command, 1, &buf[i]);
++ if (ret < 1)
++ goto out;
+
+- ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD,
+- XY_BUFSIZE, buf);
+-
+- /*
+- * We should get 4 bytes buffer that contains X,Y
+- * and event tag
+- */
+- if (ret < XY_BUFSIZE)
+- goto out;
++ command = FIFO_RD_Y_LSB;
++ }
++ }
+
+ for (i = 0; i < XY_BUFSIZE; i += XY_BUFSIZE / 2) {
+- if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_X_TAG)
++ if ((buf[i + 1] & MEASURE_TAG_MASK) ==
++ MEASURE_X_TAG)
+ x = (buf[i] << XY_BUF_OFFSET) +
+- (buf[i + 1] >> XY_BUF_OFFSET);
+- else if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_Y_TAG)
++ (buf[i + 1] >> XY_BUF_OFFSET);
++ else if ((buf[i + 1] & MEASURE_TAG_MASK) ==
++ MEASURE_Y_TAG)
+ y = (buf[i] << XY_BUF_OFFSET) +
+- (buf[i + 1] >> XY_BUF_OFFSET);
++ (buf[i + 1] >> XY_BUF_OFFSET);
+ }
+
+ if ((buf[1] & EVENT_TAG_MASK) != (buf[3] & EVENT_TAG_MASK))
+@@ -137,18 +249,17 @@
+ /* fall through */
+ case EVENT_MIDDLE:
+ input_report_abs(data->input_dev, ABS_X, x);
++ y = MAX11801_MAX_Y - y; /* Calibration */
+ input_report_abs(data->input_dev, ABS_Y, y);
+ input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1);
+ input_sync(data->input_dev);
+ break;
+-
+ case EVENT_RELEASE:
+ input_event(data->input_dev, EV_KEY, BTN_TOUCH, 0);
+ input_sync(data->input_dev);
+ break;
+-
+ case EVENT_FIFO_END:
+- break;
++ break;
+ }
+ }
+ out:
+@@ -159,18 +270,37 @@
+ {
+ struct i2c_client *client = data->client;
+
+- /* Average X,Y, take 16 samples, average eight media sample */
++ max11801_client = client;
++ /* Average X,Y, take 16 samples average eight media sample */
+ max11801_write_reg(client, MESURE_AVER_CONF_REG, 0xff);
+ /* X,Y panel setup time set to 20us */
+ max11801_write_reg(client, PANEL_SETUPTIME_CONF_REG, 0x11);
+- /* Rough pullup time (2uS), Fine pullup time (10us) */
++ /* Rough pullup time (2uS), Fine pullup time (10us) */
+ max11801_write_reg(client, TOUCH_DETECT_PULLUP_CONF_REG, 0x10);
+- /* Auto mode init period = 5ms , scan period = 5ms*/
++ /* Auto mode init period = 5ms, scan period = 5ms */
+ max11801_write_reg(client, AUTO_MODE_TIME_CONF_REG, 0xaa);
+ /* Aperture X,Y set to +- 4LSB */
+ max11801_write_reg(client, APERTURE_CONF_REG, 0x33);
+- /* Enable Power, enable Automode, enable Aperture, enable Average X,Y */
+- max11801_write_reg(client, OP_MODE_CONF_REG, 0x36);
++ /*
++ * Enable Power, enable Automode, enable Aperture,
++ * enable Average X,Y
++ */
++ if (!max11801_workmode)
++ max11801_write_reg(client, OP_MODE_CONF_REG, 0x36);
++ else {
++ max11801_write_reg(client, OP_MODE_CONF_REG, 0x16);
++ /*
++ * Delay initial=1ms, Sampling time 2us
++ * Averaging sample depth 2
++ * samples, Resolution 12bit
++ */
++ max11801_write_reg(client, AUX_MESURE_CONF_REG, 0x76);
++ /*
++ * Use edge interrupt with
++ * direct conversion mode
++ */
++ max11801_write_reg(client, GENERNAL_CONF_REG, 0xf3);
++ }
+ }
+
+ static int max11801_ts_probe(struct i2c_client *client,
+@@ -179,6 +309,7 @@
+ struct max11801_data *data;
+ struct input_dev *input_dev;
+ int error;
++ struct device_node *of_node = client->dev.of_node;
+
+ data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
+ input_dev = devm_input_allocate_device(&client->dev);
+@@ -201,6 +332,9 @@
+ input_set_abs_params(input_dev, ABS_Y, 0, MAX11801_MAX_Y, 0, 0);
+ input_set_drvdata(input_dev, data);
+
++ if (of_property_read_u32(of_node, "work-mode", &max11801_workmode))
++ max11801_workmode = *(int *)(client->dev).platform_data;
++
+ max11801_ts_phy_init(data);
+
+ error = devm_request_threaded_irq(&client->dev, client->irq, NULL,
+@@ -226,10 +360,17 @@
+ };
+ MODULE_DEVICE_TABLE(i2c, max11801_ts_id);
+
++static const struct of_device_id max11801_ts_dt_ids[] = {
++ { .compatible = "maxim,max11801", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, max11801_ts_dt_ids);
++
+ static struct i2c_driver max11801_ts_driver = {
+ .driver = {
+ .name = "max11801_ts",
+ .owner = THIS_MODULE,
++ .of_match_table = max11801_ts_dt_ids,
+ },
+ .id_table = max11801_ts_id,
+ .probe = max11801_ts_probe,
+diff -Nur linux-3.14.72.orig/drivers/irqchip/irq-gic.c linux-3.14.72/drivers/irqchip/irq-gic.c
+--- linux-3.14.72.orig/drivers/irqchip/irq-gic.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/irqchip/irq-gic.c 2016-06-19 22:11:55.169148931 +0200
+@@ -74,6 +74,27 @@
+ static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+
+ /*
++ * This lock is used by the big.LITTLE migration code to ensure no IPIs
++ * can be pended on the old core after the map has been updated.
++ */
++#ifdef CONFIG_BL_SWITCHER
++static DEFINE_RAW_SPINLOCK(cpu_map_migration_lock);
++
++static inline void gic_migration_lock(unsigned long *flags)
++{
++ raw_spin_lock_irqsave(&cpu_map_migration_lock, *flags);
++}
++
++static inline void gic_migration_unlock(unsigned long flags)
++{
++ raw_spin_unlock_irqrestore(&cpu_map_migration_lock, flags);
++}
++#else
++static inline void gic_migration_lock(unsigned long *flags) {}
++static inline void gic_migration_unlock(unsigned long flags) {}
++#endif
++
++/*
+ * The GIC mapping of CPU interfaces does not necessarily match
+ * the logical CPU numbering. Let's use a mapping as returned
+ * by the GIC itself.
+@@ -658,7 +679,7 @@
+ int cpu;
+ unsigned long flags, map = 0;
+
+- raw_spin_lock_irqsave(&irq_controller_lock, flags);
++ gic_migration_lock(&flags);
+
+ /* Convert our logical CPU mask into a physical one. */
+ for_each_cpu(cpu, mask)
+@@ -673,7 +694,7 @@
+ /* this always happens on GIC0 */
+ writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
+
+- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
++ gic_migration_unlock(flags);
+ }
+ #endif
+
+@@ -744,8 +765,17 @@
+
+ raw_spin_lock(&irq_controller_lock);
+
+- /* Update the target interface for this logical CPU */
++ /*
++ * Update the target interface for this logical CPU
++ *
++ * From the point we release the cpu_map_migration_lock any new
++ * SGIs will be pended on the new cpu which makes the set of SGIs
++ * pending on the old cpu static. That means we can defer the
++ * migration until after we have released the irq_controller_lock.
++ */
++ raw_spin_lock(&cpu_map_migration_lock);
+ gic_cpu_map[cpu] = 1 << new_cpu_id;
++ raw_spin_unlock(&cpu_map_migration_lock);
+
+ /*
+ * Find all the peripheral interrupts targetting the current
+diff -Nur linux-3.14.72.orig/drivers/Kconfig linux-3.14.72/drivers/Kconfig
+--- linux-3.14.72.orig/drivers/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/Kconfig 2016-06-19 22:11:55.169148931 +0200
+@@ -96,6 +96,8 @@
+
+ source "drivers/memstick/Kconfig"
+
++source "drivers/mxc/Kconfig"
++
+ source "drivers/leds/Kconfig"
+
+ source "drivers/accessibility/Kconfig"
+diff -Nur linux-3.14.72.orig/drivers/leds/leds-gpio.c linux-3.14.72/drivers/leds/leds-gpio.c
+--- linux-3.14.72.orig/drivers/leds/leds-gpio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/leds/leds-gpio.c 2016-06-19 22:11:55.169148931 +0200
+@@ -204,6 +204,9 @@
+ led.default_state = LEDS_GPIO_DEFSTATE_OFF;
+ }
+
++ if (of_get_property(child, "retain-state-suspended", NULL))
++ led.retain_state_suspended = 1;
++
+ ret = create_gpio_led(&led, &priv->leds[priv->num_leds++],
+ &pdev->dev, NULL);
+ if (ret < 0) {
+diff -Nur linux-3.14.72.orig/drivers/leds/leds-pwm.c linux-3.14.72/drivers/leds/leds-pwm.c
+--- linux-3.14.72.orig/drivers/leds/leds-pwm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/leds/leds-pwm.c 2016-06-19 22:11:55.169148931 +0200
+@@ -70,6 +70,10 @@
+
+ duty *= brightness;
+ do_div(duty, max);
++
++ if (led_dat->active_low)
++ duty = led_dat->period - duty;
++
+ led_dat->duty = duty;
+
+ if (led_dat->can_sleep)
+@@ -117,6 +121,7 @@
+
+ led_dat->cdev.default_trigger = of_get_property(child,
+ "linux,default-trigger", NULL);
++ led_dat->active_low = of_property_read_bool(child, "active-low");
+ of_property_read_u32(child, "max-brightness",
+ &led_dat->cdev.max_brightness);
+
+diff -Nur linux-3.14.72.orig/drivers/Makefile linux-3.14.72/drivers/Makefile
+--- linux-3.14.72.orig/drivers/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/Makefile 2016-06-19 22:11:55.169148931 +0200
+@@ -111,6 +111,7 @@
+ obj-$(CONFIG_CPU_FREQ) += cpufreq/
+ obj-$(CONFIG_CPU_IDLE) += cpuidle/
+ obj-y += mmc/
++obj-$(CONFIG_ARCH_MXC) += mxc/
+ obj-$(CONFIG_MEMSTICK) += memstick/
+ obj-y += leds/
+ obj-$(CONFIG_INFINIBAND) += infiniband/
+diff -Nur linux-3.14.72.orig/drivers/media/i2c/Kconfig linux-3.14.72/drivers/media/i2c/Kconfig
+--- linux-3.14.72.orig/drivers/media/i2c/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/i2c/Kconfig 2016-06-19 22:11:55.169148931 +0200
+@@ -293,6 +293,19 @@
+ To compile this driver as a module, choose M here: the
+ module will be called saa7191.
+
++config VIDEO_TC358743
++ tristate "Toshiba TC358743 decoder"
++ depends on VIDEO_V4L2 && I2C
++ select MEDIA_CONTROLLER
++ ---help---
++ Support for the Toshiba TC358743 HDMI to MIPI CSI-2 bridge
++
++ This is a Analog Devices Component/Graphics Digitizer
++ with 4:1 Multiplexed HDMI Receiver.
++
++ To compile this driver as a module, choose M here: the
++ module will be called tc358743.
++
+ config VIDEO_TVP514X
+ tristate "Texas Instruments TVP514x video decoder"
+ depends on VIDEO_V4L2 && I2C
+diff -Nur linux-3.14.72.orig/drivers/media/i2c/Makefile linux-3.14.72/drivers/media/i2c/Makefile
+--- linux-3.14.72.orig/drivers/media/i2c/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/i2c/Makefile 2016-06-19 22:11:55.169148931 +0200
+@@ -76,3 +76,4 @@
+ obj-$(CONFIG_VIDEO_AK881X) += ak881x.o
+ obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
+ obj-$(CONFIG_VIDEO_ML86V7667) += ml86v7667.o
++obj-$(CONFIG_VIDEO_TC358743) += tc358743.o
+diff -Nur linux-3.14.72.orig/drivers/media/i2c/tc358743.c linux-3.14.72/drivers/media/i2c/tc358743.c
+--- linux-3.14.72.orig/drivers/media/i2c/tc358743.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/i2c/tc358743.c 2016-06-19 22:11:55.169148931 +0200
+@@ -0,0 +1,1972 @@
++/*
++ * tc358743 - Toshiba HDMI to CSI-2 bridge
++ *
++ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
++ * reserved.
++ *
++ * This program is free software; you may redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ *
++ */
++
++/*
++ * References (c = chapter, p = page):
++ * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
++ * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/gpio/consumer.h>
++#include <linux/interrupt.h>
++#include <linux/videodev2.h>
++#include <linux/workqueue.h>
++#include <linux/v4l2-dv-timings.h>
++#include <media/v4l2-dv-timings.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/v4l2-of.h>
++#include <media/tc358743.h>
++
++#include "tc358743_regs.h"
++
++static int debug;
++module_param(debug, int, 0644);
++MODULE_PARM_DESC(debug, "debug level (0-3)");
++
++MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
++MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
++MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
++MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
++MODULE_LICENSE("GPL");
++
++static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
++ .type = V4L2_DV_BT_656_1120,
++ /* keep this initialization for compatibility with GCC < 4.4.6 */
++ .reserved = { 0 },
++ /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
++ V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 165000000,
++ V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
++ V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
++ V4L2_DV_BT_CAP_PROGRESSIVE |
++ V4L2_DV_BT_CAP_REDUCED_BLANKING |
++ V4L2_DV_BT_CAP_CUSTOM)
++};
++
++struct tc358743_state {
++ struct tc358743_platform_data pdata;
++ struct v4l2_of_bus_mipi_csi2 bus;
++ struct v4l2_subdev sd;
++ struct media_pad pad;
++ struct v4l2_ctrl_handler hdl;
++ struct i2c_client *i2c_client;
++
++ /* controls */
++ struct v4l2_ctrl *detect_tx_5v_ctrl;
++ struct v4l2_ctrl *audio_sampling_rate_ctrl;
++ struct v4l2_ctrl *audio_present_ctrl;
++
++ /* work queues */
++ struct workqueue_struct *work_queues;
++ struct delayed_work delayed_work_enable_hotplug;
++
++ /* edid */
++ bool edid_written;
++
++ struct v4l2_dv_timings timings;
++ u32 mbus_fmt_code;
++
++ struct gpio_desc *reset_gpio;
++};
++
++static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
++{
++ return container_of(sd, struct tc358743_state, sd);
++}
++
++/* --------------- I2C --------------- */
++
++static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct i2c_client *client = state->i2c_client;
++ int err;
++ u8 buf[2] = { reg >> 8, reg & 0xff };
++ struct i2c_msg msgs[] = {
++ {
++ .addr = client->addr,
++ .flags = 0,
++ .len = 2,
++ .buf = buf,
++ },
++ {
++ .addr = client->addr,
++ .flags = I2C_M_RD,
++ .len = n,
++ .buf = values,
++ },
++ };
++
++ err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
++ if (err != ARRAY_SIZE(msgs)) {
++ v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
++ __func__, reg, client->addr);
++ }
++}
++
++static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct i2c_client *client = state->i2c_client;
++ int err, i;
++ struct i2c_msg msg;
++ u8 data[2 + n];
++
++ msg.addr = client->addr;
++ msg.buf = data;
++ msg.len = 2 + n;
++ msg.flags = 0;
++
++ data[0] = reg >> 8;
++ data[1] = reg & 0xff;
++
++ for (i = 0; i < n; i++)
++ data[2 + i] = values[i];
++
++ err = i2c_transfer(client->adapter, &msg, 1);
++ if (err != 1) {
++ v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
++ __func__, reg, client->addr);
++ return;
++ }
++
++ if (debug < 3)
++ return;
++
++ switch (n) {
++ case 1:
++ v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
++ reg, data[2]);
++ break;
++ case 2:
++ v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
++ reg, data[3], data[2]);
++ break;
++ case 4:
++ v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
++ reg, data[5], data[4], data[3], data[2]);
++ break;
++ default:
++ v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
++ n, reg);
++ }
++}
++
++static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
++{
++ u8 val;
++
++ i2c_rd(sd, reg, &val, 1);
++
++ return val;
++}
++
++static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
++{
++ i2c_wr(sd, reg, &val, 1);
++}
++
++static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
++ u8 mask, u8 val)
++{
++ i2c_wr8(sd, reg, (i2c_rd8(sd, reg) & mask) | val);
++}
++
++static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
++{
++ u16 val;
++
++ i2c_rd(sd, reg, (u8 *)&val, 2);
++
++ return val;
++}
++
++static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
++{
++ i2c_wr(sd, reg, (u8 *)&val, 2);
++}
++
++static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
++{
++ i2c_wr16(sd, reg, (i2c_rd16(sd, reg) & mask) | val);
++}
++
++static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
++{
++ u32 val;
++
++ i2c_rd(sd, reg, (u8 *)&val, 4);
++
++ return val;
++}
++
++static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
++{
++ i2c_wr(sd, reg, (u8 *)&val, 4);
++}
++
++/* --------------- STATUS --------------- */
++
++static inline bool is_hdmi(struct v4l2_subdev *sd)
++{
++ return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
++}
++
++static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
++{
++ return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
++}
++
++static inline bool no_signal(struct v4l2_subdev *sd)
++{
++ return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
++}
++
++static inline bool no_sync(struct v4l2_subdev *sd)
++{
++ return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
++}
++
++static inline bool audio_present(struct v4l2_subdev *sd)
++{
++ return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
++}
++
++static int get_audio_sampling_rate(struct v4l2_subdev *sd)
++{
++ static const int code_to_rate[] = {
++ 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
++ 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
++ };
++
++ /* Register FS_SET is not cleared when the cable is disconnected */
++ if (no_signal(sd))
++ return 0;
++
++ return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
++}
++
++static unsigned tc358743_num_csi_lanes_in_use(struct v4l2_subdev *sd)
++{
++ return ((i2c_rd32(sd, CSI_CONTROL) & MASK_NOL) >> 1) + 1;
++}
++
++/* --------------- TIMINGS --------------- */
++
++static inline unsigned fps(const struct v4l2_bt_timings *t)
++{
++ if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
++ return 0;
++
++ return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
++ V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
++}
++
++static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
++ struct v4l2_dv_timings *timings)
++{
++ struct v4l2_bt_timings *bt = &timings->bt;
++ unsigned width, height, frame_width, frame_height, frame_interval, fps;
++
++ memset(timings, 0, sizeof(struct v4l2_dv_timings));
++
++ if (no_signal(sd)) {
++ v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
++ return -ENOLINK;
++ }
++ if (no_sync(sd))
++ v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
++
++ timings->type = V4L2_DV_BT_656_1120;
++ bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
++ V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
++
++ width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
++ i2c_rd8(sd, DE_WIDTH_H_LO);
++ height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
++ i2c_rd8(sd, DE_WIDTH_V_LO);
++ frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
++ i2c_rd8(sd, H_SIZE_LO);
++ frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
++ i2c_rd8(sd, V_SIZE_LO)) / 2;
++ /* frame interval in milliseconds * 10
++ * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
++ frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
++ i2c_rd8(sd, FV_CNT_LO);
++ fps = (frame_interval > 0) ?
++ DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
++
++ bt->width = width;
++ bt->height = height;
++ bt->vsync = frame_height - height;
++ bt->hsync = frame_width - width;
++ bt->pixelclock = frame_width * frame_height * fps;
++
++ return 0;
++}
++
++/* --------------- HOTPLUG / HDCP / EDID --------------- */
++
++static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
++{
++ struct delayed_work *dwork = to_delayed_work(work);
++ struct tc358743_state *state = container_of(dwork,
++ struct tc358743_state, delayed_work_enable_hotplug);
++ struct v4l2_subdev *sd = &state->sd;
++
++ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
++
++ i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
++}
++
++static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
++{
++ v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
++ "enable" : "disable");
++
++ i2c_wr8_and_or(sd, HDCP_REG1,
++ ~(MASK_AUTH_UNAUTH_SEL | MASK_AUTH_UNAUTH),
++ MASK_AUTH_UNAUTH_SEL_16_FRAMES | MASK_AUTH_UNAUTH_AUTO);
++
++ i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
++ SET_AUTO_P3_RESET_FRAMES(0x0f));
++
++ /* HDCP is disabled by configuring the receiver as HDCP repeater.
++ * The repeater mode require software support to work, so
++ * HDCP authentication will fail. Set Ready and MAX_EXCED bits
++ * to avoid problems on MacBook Pro gen.8.
++ */
++ i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, enable ? KEY_RD_CMD : 0);
++
++ i2c_wr8_and_or(sd, HDCP_MODE, ~(MASK_AUTO_CLR | MASK_MODE_RST_TN),
++ enable ? (MASK_AUTO_CLR | MASK_MODE_RST_TN) : 0);
++
++ i2c_wr8_and_or(sd, BSTATUS1, ~MASK_MAX_EXCED,
++ enable ? 0 : MASK_MAX_EXCED);
++
++ i2c_wr8_and_or(sd, BCAPS, ~(MASK_REPEATER | MASK_READY),
++ enable ? 0 : MASK_REPEATER | MASK_READY);
++}
++
++static void tc358743_disable_edid(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
++
++ cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
++
++ /* DDC access to EDID is also disabled when hotplug is disabled. See
++ * register DDC_CTL */
++ i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
++}
++
++static void tc358743_enable_edid(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ if (!state->edid_written) {
++ v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
++ return;
++ }
++
++ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
++
++ /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
++ * hotplug is enabled. See register DDC_CTL */
++ queue_delayed_work(state->work_queues,
++ &state->delayed_work_enable_hotplug, HZ / 10);
++}
++
++/* --------------- AVI --------------- */
++/* TODO move to common library */
++
++struct aviInfoFrame {
++ u8 f17;
++ u8 y10;
++ u8 a0;
++ u8 b10;
++ u8 s10;
++ u8 c10;
++ u8 m10;
++ u8 r3210;
++ u8 itc;
++ u8 ec210;
++ u8 q10;
++ u8 sc10;
++ u8 f47;
++ u8 vic;
++ u8 yq10;
++ u8 cn10;
++ u8 pr3210;
++ u16 etb;
++ u16 sbb;
++ u16 elb;
++ u16 srb;
++};
++
++static const char *y10Text[4] = {
++ "RGB",
++ "YCbCr 4:2:2",
++ "YCbCr 4:4:4",
++ "Future",
++};
++
++static const char *c10Text[4] = {
++ "No Data",
++ "SMPTE 170M",
++ "ITU-R 709",
++ "Extended Colorimetry information valied",
++};
++
++static const char *itcText[2] = {
++ "No Data",
++ "IT content",
++};
++
++static const char *ec210Text[8] = {
++ "xvYCC601",
++ "xvYCC709",
++ "sYCC601",
++ "AdobeYCC601",
++ "AdobeRGB",
++ "5 reserved",
++ "6 reserved",
++ "7 reserved",
++};
++
++static const char *q10Text[4] = {
++ "Default",
++ "Limited Range",
++ "Full Range",
++ "Reserved",
++};
++
++static void parse_avi_infoframe(struct v4l2_subdev *sd, u8 *buf,
++ struct aviInfoFrame *avi)
++{
++ avi->f17 = (buf[1] >> 7) & 0x1;
++ avi->y10 = (buf[1] >> 5) & 0x3;
++ avi->a0 = (buf[1] >> 4) & 0x1;
++ avi->b10 = (buf[1] >> 2) & 0x3;
++ avi->s10 = buf[1] & 0x3;
++ avi->c10 = (buf[2] >> 6) & 0x3;
++ avi->m10 = (buf[2] >> 4) & 0x3;
++ avi->r3210 = buf[2] & 0xf;
++ avi->itc = (buf[3] >> 7) & 0x1;
++ avi->ec210 = (buf[3] >> 4) & 0x7;
++ avi->q10 = (buf[3] >> 2) & 0x3;
++ avi->sc10 = buf[3] & 0x3;
++ avi->f47 = (buf[4] >> 7) & 0x1;
++ avi->vic = buf[4] & 0x7f;
++ avi->yq10 = (buf[5] >> 6) & 0x3;
++ avi->cn10 = (buf[5] >> 4) & 0x3;
++ avi->pr3210 = buf[5] & 0xf;
++ avi->etb = buf[6] + 256 * buf[7];
++ avi->sbb = buf[8] + 256 * buf[9];
++ avi->elb = buf[10] + 256 * buf[11];
++ avi->srb = buf[12] + 256 * buf[13];
++}
++
++static void print_avi_infoframe(struct v4l2_subdev *sd)
++{
++ u8 buf[14];
++ u8 avi_len;
++ u8 avi_ver;
++ struct aviInfoFrame avi;
++
++ if (!is_hdmi(sd)) {
++ v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
++ return;
++ }
++
++ avi_ver = i2c_rd8(sd, PK_AVI_1HEAD);
++ avi_len = i2c_rd8(sd, PK_AVI_2HEAD);
++ v4l2_info(sd, "AVI infoframe version %d (%d byte)\n", avi_ver, avi_len);
++
++ if (avi_ver != 0x02)
++ return;
++
++ i2c_rd(sd, PK_AVI_0BYTE, buf, ARRAY_SIZE(buf));
++
++ v4l2_info(sd, "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
++ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
++ buf[7], buf[8], buf[9], buf[10], buf[11], buf[12],
++ buf[13]);
++
++ parse_avi_infoframe(sd, buf, &avi);
++
++ if (avi.vic)
++ v4l2_info(sd, "\tVIC: %d\n", avi.vic);
++ if (avi.itc)
++ v4l2_info(sd, "\t%s\n", itcText[avi.itc]);
++
++ if (avi.y10)
++ v4l2_info(sd, "\t%s %s\n", y10Text[avi.y10],
++ !avi.c10 ? "" :
++ (avi.c10 == 0x3 ? ec210Text[avi.ec210] :
++ c10Text[avi.c10]));
++ else
++ v4l2_info(sd, "\t%s %s\n", y10Text[avi.y10], q10Text[avi.q10]);
++}
++
++/* --------------- CTRLS --------------- */
++
++static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
++ tx_5v_power_present(sd));
++}
++
++static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
++ get_audio_sampling_rate(sd));
++}
++
++static int tc358743_s_audio_present_ctrl(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
++ audio_present(sd));
++}
++
++static int tc358743_update_controls(struct v4l2_subdev *sd)
++{
++ int ret = 0;
++
++ ret |= tc358743_s_ctrl_detect_tx_5v(sd);
++ ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
++ ret |= tc358743_s_audio_present_ctrl(sd);
++
++ return ret;
++}
++
++/* --------------- INIT --------------- */
++
++static void tc358743_reset_phy(struct v4l2_subdev *sd)
++{
++ v4l2_dbg(1, debug, sd, "%s:\n", __func__);
++
++ i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
++ i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
++}
++
++static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
++{
++ u16 sysctl = i2c_rd16(sd, SYSCTL);
++
++ i2c_wr16(sd, SYSCTL, sysctl | mask);
++ i2c_wr16(sd, SYSCTL, sysctl & ~mask);
++}
++
++static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
++{
++ i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
++ enable ? MASK_SLEEP : 0);
++}
++
++static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
++{
++ v4l2_dbg(3, debug, sd, "%s: %sable\n",
++ __func__, enable ? "en" : "dis");
++
++ i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
++ enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
++}
++
++static void tc358743_set_pll(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct tc358743_platform_data *pdata = &state->pdata;
++ u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
++ u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
++ u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
++ SET_PLL_FBD(pdata->pll_fbd);
++
++ v4l2_dbg(2, debug, sd, "%s:\n", __func__);
++
++ /* Only rewrite when needed, since rewriting triggers another format
++ * change event. */
++ if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
++ u32 hsck = (pdata->refclk_hz * pdata->pll_fbd) / pdata->pll_prd;
++ u16 pll_frs;
++
++ if (hsck > 500000000)
++ pll_frs = 0x0;
++ else if (hsck > 250000000)
++ pll_frs = 0x1;
++ else if (hsck > 125000000)
++ pll_frs = 0x2;
++ else
++ pll_frs = 0x3;
++
++ v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
++ tc358743_sleep_mode(sd, true);
++ i2c_wr16(sd, PLLCTL0, pllctl0_new);
++ i2c_wr16_and_or(sd, PLLCTL1,
++ ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
++ (SET_PLL_FRS(pll_frs) | MASK_RESETB |
++ MASK_PLL_EN));
++ udelay(10); /* REF_02, Sheet "Source HDMI" */
++ i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
++ tc358743_sleep_mode(sd, false);
++ }
++}
++
++static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct tc358743_platform_data *pdata = &state->pdata;
++ u32 sys_freq;
++ u32 lockdet_ref;
++ u16 fh_min;
++ u16 fh_max;
++
++ BUG_ON(!(pdata->refclk_hz == 26000000 ||
++ pdata->refclk_hz == 27000000 ||
++ pdata->refclk_hz == 42000000));
++
++ sys_freq = pdata->refclk_hz / 10000;
++ i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
++ i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
++
++ i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
++ (pdata->refclk_hz == 42000000) ?
++ MASK_PHY_SYSCLK_IND : 0x0);
++
++ fh_min = pdata->refclk_hz / 100000;
++ i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
++ i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
++
++ fh_max = (fh_min * 66) / 10;
++ i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
++ i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
++
++ lockdet_ref = pdata->refclk_hz / 100;
++ i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
++ i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
++ i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
++
++ i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
++ (pdata->refclk_hz == 27000000) ?
++ MASK_NCO_F0_MOD_27MHZ : 0x0);
++}
++
++static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ switch (state->mbus_fmt_code) {
++ case MEDIA_BUS_FMT_UYVY8_1X16:
++ v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
++ i2c_wr8_and_or(sd, VOUT_SET2,
++ ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
++ MASK_SEL422 | MASK_VOUT_422FIL_100);
++ i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
++ MASK_VOUT_COLOR_601_YCBCR_LIMITED);
++ i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
++ MASK_YCBCRFMT_422_8_BIT);
++ break;
++ case MEDIA_BUS_FMT_RGB888_1X24:
++ v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
++ i2c_wr8_and_or(sd, VOUT_SET2,
++ ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
++ 0x00);
++ i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
++ MASK_VOUT_COLOR_RGB_FULL);
++ i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
++ break;
++ default:
++ v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
++ __func__, state->mbus_fmt_code);
++ }
++}
++
++static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct v4l2_bt_timings *bt = &state->timings.bt;
++ u32 htotal = bt->width + bt->hfrontporch + bt->hsync + bt->hbackporch;
++ u32 vtotal = bt->height + bt->vfrontporch + bt->vsync + bt->vbackporch;
++ u32 bits_pr_pixel =
++ (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
++ u32 bps = htotal * vtotal * fps(bt) * bits_pr_pixel;
++
++ return DIV_ROUND_UP(bps, state->pdata.bps_pr_lane);
++}
++
++static void tc358743_set_csi(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct tc358743_platform_data *pdata = &state->pdata;
++ unsigned lanes = tc358743_num_csi_lanes_needed(sd);
++
++ v4l2_dbg(3, debug, sd, "%s:\n", __func__);
++
++ tc358743_reset(sd, MASK_CTXRST);
++
++ if (lanes < 1)
++ i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
++ if (lanes < 1)
++ i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
++ if (lanes < 2)
++ i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
++ if (lanes < 3)
++ i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
++ if (lanes < 4)
++ i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
++
++ i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
++ i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
++ i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
++ i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
++ i2c_wr32(sd, TWAKEUP, pdata->twakeup);
++ i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
++ i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
++ i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
++ i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
++
++ i2c_wr32(sd, HSTXVREGEN,
++ ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
++ ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
++ ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
++ ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
++ ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
++
++ i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
++ V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
++}
++
++static void tc358743_start_csi(struct v4l2_subdev *sd)
++{
++ unsigned lanes = tc358743_num_csi_lanes_needed(sd);
++
++ v4l2_dbg(3, debug, sd, "%s:\n", __func__);
++
++ i2c_wr32(sd, STARTCNTRL, MASK_START);
++ i2c_wr32(sd, CSI_START, MASK_STRT);
++
++ i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
++ MASK_ADDRESS_CSI_CONTROL |
++ MASK_CSI_MODE |
++ MASK_TXHSMD |
++ ((lanes == 4) ? MASK_NOL_4 :
++ (lanes == 3) ? MASK_NOL_3 :
++ (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
++
++ i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
++ MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
++ MASK_WCER | MASK_INER);
++
++ i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
++ MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
++
++ i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
++ MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
++}
++
++static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct tc358743_platform_data *pdata = &state->pdata;
++
++ /* Default settings from REF_02, sheet "Source HDMI"
++ * and custom settings as platform data */
++ i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
++ i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
++ SET_FREQ_RANGE_MODE_CYCLES(1));
++ i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn, pdata->phy_auto_rst);
++ i2c_wr8(sd, PHY_BIAS, 0x40);
++ i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
++ i2c_wr8(sd, AVM_CTL, 45);
++ i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
++ pdata->hdmi_det_v);
++ i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
++ (pdata->h_pi_rst ? MASK_H_PI_RST : 0) |
++ (pdata->v_pi_rst ? MASK_V_PI_RST : 0));
++ i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
++}
++
++static void tc358743_erase_bksv(struct v4l2_subdev *sd)
++{
++ int i;
++
++ for (i = 0; i < 5; i++)
++ i2c_wr8(sd, BKSV + i, 0);
++}
++
++static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
++{
++ /* Default settings from REF_02, sheet "Source HDMI" */
++ i2c_wr8(sd, FORCE_MUTE, 0x00);
++ i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
++ MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
++ MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
++ i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
++ i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
++ i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
++ i2c_wr8(sd, FS_MUTE, 0x00);
++ i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
++ i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
++ i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
++ i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
++ i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
++ i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
++ i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
++ MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
++}
++
++static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
++{
++ /* Default settings from REF_02, sheet "Source HDMI" */
++ i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
++ MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
++ MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
++ MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
++ i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
++ i2c_wr8(sd, NO_PKT_CLR, 0x53);
++ i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
++ i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
++ i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
++}
++
++static void tc358743_initial_setup(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct tc358743_platform_data *pdata = &state->pdata;
++
++ /* Keep CEC and IR in reset since driver support is missing */
++ i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST),
++ (MASK_CECRST | MASK_IRRST));
++
++ tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
++ tc358743_sleep_mode(sd, false);
++
++ i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
++
++ tc358743_set_ref_clk(sd);
++
++ i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
++ pdata->ddc5v_delay & MASK_DDC5V_MODE);
++ i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
++
++ tc358743_set_hdmi_phy(sd);
++ tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
++ tc358743_set_hdmi_audio(sd);
++ tc358743_set_hdmi_info_frame_mode(sd);
++
++ i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
++ MASK_VOUTCOLORMODE_AUTO);
++ i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
++}
++
++/* --------------- IRQ --------------- */
++
++static void tc358743_clear_interrupt_status(struct v4l2_subdev *sd)
++{
++ u16 i;
++
++ /* clear interrupt status registers */
++ for (i = SYS_INT; i <= KEY_INT; i++)
++ i2c_wr8(sd, i, 0xff);
++
++ i2c_wr16(sd, INTSTATUS, 0xffff);
++}
++
++static void tc358743_enable_interrupts(struct v4l2_subdev *sd)
++{
++ tc358743_clear_interrupt_status(sd);
++
++ /* enable interrupts */
++ i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_HDMI_DET) & 0xff);
++
++ i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
++
++ i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
++
++ i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
++ MASK_M_AF_UNLOCK) & 0xff);
++
++ i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
++}
++
++static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
++{
++ v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
++
++ i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
++}
++
++static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
++ bool *handled)
++{
++ u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
++ u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
++
++ i2c_wr8(sd, MISC_INT, misc_int);
++
++ v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
++
++ if (misc_int & MASK_I_SYNC_CHG) {
++
++ v4l2_dbg(1, debug, sd, "%s: Format changed\n", __func__);
++
++ if (no_sync(sd) || no_signal(sd)) {
++ tc358743_reset_phy(sd);
++ tc358743_erase_bksv(sd);
++ }
++
++ v4l2_subdev_notify(sd, TC358743_FMT_CHANGE, NULL);
++
++ misc_int &= ~MASK_I_SYNC_CHG;
++ if (handled)
++ *handled = true;
++ }
++
++ if (misc_int) {
++ v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
++ __func__, misc_int);
++ }
++}
++
++static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
++ bool *handled)
++{
++ u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
++ u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
++
++ i2c_wr8(sd, CBIT_INT, cbit_int);
++
++ v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
++
++ if (cbit_int & MASK_I_CBIT_FS) {
++
++ v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
++ __func__);
++ tc358743_s_ctrl_audio_sampling_rate(sd);
++
++ cbit_int &= ~MASK_I_CBIT_FS;
++ if (handled)
++ *handled = true;
++ }
++
++ if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
++
++ v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
++ __func__);
++ tc358743_s_audio_present_ctrl(sd);
++
++ cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
++ if (handled)
++ *handled = true;
++ }
++
++ if (cbit_int) {
++ v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
++ __func__, cbit_int);
++ }
++}
++
++static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
++{
++ u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
++ u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
++
++ /* Bit 7 and bit 6 are set even when they are masked */
++ i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
++
++ v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
++
++ if (clk_int & (MASK_I_IN_DE_CHG)) {
++
++ v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
++ __func__);
++
++ /* If the source switch to a new resolution with the same pixel
++ * frequency as the existing (ie. 1080p25 -> 720p50), the
++ * I_SYNC_CHG interrupt is not always triggered, while the
++ * I_IN_DE_CHG interrupt seems to work fine. FMT_CHANGE
++ * notifications are only sent when the signal is stable to
++ * reduce the number of notifications. */
++ if (!no_signal(sd) && !no_sync(sd))
++ v4l2_subdev_notify(sd, TC358743_FMT_CHANGE, NULL);
++
++ clk_int &= ~(MASK_I_IN_DE_CHG);
++ if (handled)
++ *handled = true;
++ }
++
++ if (clk_int) {
++ v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
++ __func__, clk_int);
++ }
++}
++
++static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
++{
++ struct tc358743_state *state = to_state(sd);
++ u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
++ u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
++
++ i2c_wr8(sd, SYS_INT, sys_int);
++
++ v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
++
++ if (sys_int & MASK_I_DDC) {
++ bool tx_5v = tx_5v_power_present(sd);
++
++ v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
++ __func__, tx_5v ? "yes" : "no");
++
++ if (tx_5v) {
++ tc358743_enable_edid(sd);
++ } else {
++ tc358743_disable_edid(sd);
++ memset(&state->timings, 0, sizeof(state->timings));
++ tc358743_erase_bksv(sd);
++ }
++
++ tc358743_update_controls(sd);
++
++ sys_int &= ~MASK_I_DDC;
++ if (handled)
++ *handled = true;
++ }
++
++ if (sys_int & MASK_I_HDMI) {
++ v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
++ __func__);
++
++ /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
++ i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
++
++ sys_int &= ~MASK_I_HDMI;
++ if (handled)
++ *handled = true;
++ }
++
++ if (sys_int) {
++ v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
++ __func__, sys_int);
++ }
++}
++
++/* --------------- CORE OPS --------------- */
++
++static int tc358743_log_status(struct v4l2_subdev *sd)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct v4l2_dv_timings timings;
++ uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
++ uint16_t sysctl = i2c_rd16(sd, SYSCTL);
++ u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
++ const int deep_color_mode[4] = { 8, 10, 12, 16 };
++ static const char * const input_color_space[] = {
++ "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
++ "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
++ "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
++
++ v4l2_info(sd, "-----Chip status-----\n");
++ v4l2_info(sd, "Chip ID: %d\n", i2c_rd16(sd, CHIPID) &
++ MASK_CHIPID);
++ v4l2_info(sd, "Chip revision: %d\n",
++ i2c_rd16(sd, CHIPID) & MASK_REVID);
++ v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
++ !!(sysctl & MASK_IRRST),
++ !!(sysctl & MASK_CECRST),
++ !!(sysctl & MASK_CTXRST),
++ !!(sysctl & MASK_HDMIRST));
++ v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
++ v4l2_info(sd, "Cable detected (+5V power): %s\n",
++ hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
++ v4l2_info(sd, "DDC lines enabled: %s\n",
++ (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
++ "yes" : "no");
++ v4l2_info(sd, "Hotplug enabled: %s\n",
++ (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
++ "yes" : "no");
++ v4l2_info(sd, "CEC enabled: %s\n",
++ (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
++ v4l2_info(sd, "-----Signal status-----\n");
++ v4l2_info(sd, "TMDS signal detected: %s\n",
++ hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
++ v4l2_info(sd, "Stable sync signal: %s\n",
++ hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
++ v4l2_info(sd, "PHY PLL locked: %s\n",
++ hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
++ v4l2_info(sd, "PHY DE detected: %s\n",
++ hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
++
++ if (tc358743_get_detected_timings(sd, &timings)) {
++ v4l2_info(sd, "No video detected\n");
++ } else {
++ v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
++ true);
++ }
++ v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
++ true);
++
++ v4l2_info(sd, "-----CSI-TX status-----\n");
++ v4l2_info(sd, "Lanes needed: %d\n",
++ tc358743_num_csi_lanes_needed(sd));
++ v4l2_info(sd, "Lanes in use: %d\n",
++ tc358743_num_csi_lanes_in_use(sd));
++ v4l2_info(sd, "Waiting for particular sync signal: %s\n",
++ (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
++ "yes" : "no");
++ v4l2_info(sd, "Transmit mode: %s\n",
++ (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
++ "yes" : "no");
++ v4l2_info(sd, "Receive mode: %s\n",
++ (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
++ "yes" : "no");
++ v4l2_info(sd, "Stopped: %s\n",
++ (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
++ "yes" : "no");
++ v4l2_info(sd, "Color space: %s\n",
++ state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
++ "YCbCr 422 16-bit" :
++ state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
++ "RGB 888 24-bit" : "Unsupported");
++
++ v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
++ v4l2_info(sd, "HDCP encrypted content: %s\n",
++ hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
++ v4l2_info(sd, "Input color space: %s %s range\n",
++ input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
++ (vi_status3 & MASK_LIMITED) ? "limited" : "full");
++ if (!is_hdmi(sd))
++ return 0;
++ v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
++ "off");
++ v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
++ deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
++ MASK_S_DEEPCOLOR) >> 2]);
++ print_avi_infoframe(sd);
++
++ return 0;
++}
++
++static long tc358743_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
++{
++ switch (cmd) {
++ case TC358743_CSI_RESET:
++ {
++ /*
++ * This function is called often with CSI overflow. It should
++ * run as fast as possible for quick recovery. I2C operations
++ * are slow. This function takes about 20 ms. Stop stream first,
++ * reset CSI and enable stream. Avoid calling enable_stream
++ * twice which add an extra I2C read.
++ */
++ unsigned short confctl = i2c_rd16(sd, CONFCTL);
++
++ v4l2_dbg(3, debug, sd, "%s: TC358743_CSI_RESET\n", __func__);
++
++ i2c_wr16(sd, CONFCTL, confctl &
++ (~(MASK_VBUFEN | MASK_ABUFEN)));
++ tc358743_set_csi(sd);
++ tc358743_start_csi(sd);
++ i2c_wr16(sd, CONFCTL, confctl |
++ (MASK_VBUFEN | MASK_ABUFEN));
++ return 0;
++ }
++ }
++
++ v4l2_dbg(1, debug, sd, "%s: unknown ioctl %08x\n", __func__, cmd);
++
++ return -ENOTTY;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static void tc358743_print_register_map(struct v4l2_subdev *sd)
++{
++ v4l2_info(sd, "0x0000–0x00FF: Global Control Register\n");
++ v4l2_info(sd, "0x0100–0x01FF: CSI2-TX PHY Register\n");
++ v4l2_info(sd, "0x0200–0x03FF: CSI2-TX PPI Register\n");
++ v4l2_info(sd, "0x0400–0x05FF: Reserved\n");
++ v4l2_info(sd, "0x0600–0x06FF: CEC Register\n");
++ v4l2_info(sd, "0x0700–0x84FF: Reserved\n");
++ v4l2_info(sd, "0x8500–0x85FF: HDMIRX System Control Register\n");
++ v4l2_info(sd, "0x8600–0x86FF: HDMIRX Audio Control Register\n");
++ v4l2_info(sd, "0x8700–0x87FF: HDMIRX InfoFrame packet data Register\n");
++ v4l2_info(sd, "0x8800–0x88FF: HDMIRX HDCP Port Register\n");
++ v4l2_info(sd, "0x8900–0x89FF: HDMIRX Video Output Port & 3D Register\n");
++ v4l2_info(sd, "0x8A00–0x8BFF: Reserved\n");
++ v4l2_info(sd, "0x8C00–0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
++ v4l2_info(sd, "0x9000–0x90FF: HDMIRX GBD Extraction Control\n");
++ v4l2_info(sd, "0x9100–0x92FF: HDMIRX GBD RAM read\n");
++ v4l2_info(sd, "0x9300- : Reserved\n");
++}
++
++static int tc358743_get_reg_size(u16 address)
++{
++ /* REF_01 p. 66-72 */
++ if (address <= 0x00ff)
++ return 2;
++ else if ((address >= 0x0100) && (address <= 0x06FF))
++ return 4;
++ else if ((address >= 0x0700) && (address <= 0x84ff))
++ return 2;
++ else
++ return 1;
++}
++
++static int tc358743_g_register(struct v4l2_subdev *sd,
++ struct v4l2_dbg_register *reg)
++{
++ if (reg->reg > 0xffff) {
++ tc358743_print_register_map(sd);
++ return -EINVAL;
++ }
++
++ reg->size = tc358743_get_reg_size(reg->reg);
++
++ i2c_rd(sd, reg->reg, (u8 *)&reg->val, reg->size);
++
++ return 0;
++}
++
++static int tc358743_s_register(struct v4l2_subdev *sd,
++ const struct v4l2_dbg_register *reg)
++{
++ if (reg->reg > 0xffff) {
++ tc358743_print_register_map(sd);
++ return -EINVAL;
++ }
++
++ /* It should not be possible for the user to enable HDCP with a simple
++ * v4l2-dbg command.
++ *
++ * DO NOT REMOVE THIS unless all other issues with HDCP have been
++ * resolved.
++ */
++ if (reg->reg == HDCP_MODE ||
++ reg->reg == HDCP_REG1 ||
++ reg->reg == HDCP_REG2 ||
++ reg->reg == HDCP_REG3 ||
++ reg->reg == BCAPS)
++ return 0;
++
++ i2c_wr(sd, (u16)reg->reg, (u8 *)&reg->val,
++ tc358743_get_reg_size(reg->reg));
++
++ return 0;
++}
++#endif
++
++static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
++{
++ u16 intstatus = i2c_rd16(sd, INTSTATUS);
++
++ v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
++
++ if (intstatus & MASK_HDMI_INT) {
++ u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
++ u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
++
++ if (hdmi_int0 & MASK_I_MISC)
++ tc358743_hdmi_misc_int_handler(sd, handled);
++ if (hdmi_int1 & MASK_I_CBIT)
++ tc358743_hdmi_cbit_int_handler(sd, handled);
++ if (hdmi_int1 & MASK_I_CLK)
++ tc358743_hdmi_clk_int_handler(sd, handled);
++ if (hdmi_int1 & MASK_I_SYS)
++ tc358743_hdmi_sys_int_handler(sd, handled);
++
++ i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
++ intstatus &= ~MASK_HDMI_INT;
++ }
++
++ if (intstatus & MASK_CSI_INT) {
++ u32 csi_int = i2c_rd32(sd, CSI_INT);
++
++ if (csi_int & MASK_INTER)
++ tc358743_csi_err_int_handler(sd, handled);
++
++ i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
++ intstatus &= ~MASK_CSI_INT;
++ }
++
++ intstatus = i2c_rd16(sd, INTSTATUS);
++ if (intstatus) {
++ v4l2_dbg(1, debug, sd,
++ "%s: Unhandled IntStatus interrupts: 0x%02x\n",
++ __func__, intstatus);
++ }
++
++ return 0;
++}
++
++static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
++{
++ struct tc358743_state *state = dev_id;
++ bool handled;
++
++ tc358743_isr(&state->sd, 0, &handled);
++
++ return handled ? IRQ_HANDLED : IRQ_NONE;
++}
++
++/* --------------- VIDEO OPS --------------- */
++
++static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
++{
++ *status = 0;
++ *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
++ *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
++
++ v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
++
++ return 0;
++}
++
++static int tc358743_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
++ struct v4l2_subdev_format *format)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ if (format->pad != 0)
++ return -EINVAL;
++
++ switch (format->format.code) {
++ case MEDIA_BUS_FMT_RGB888_1X24:
++ case MEDIA_BUS_FMT_UYVY8_1X16:
++ state->mbus_fmt_code = format->format.code;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ enable_stream(sd, false);
++ tc358743_set_pll(sd);
++ tc358743_set_csi(sd);
++ tc358743_set_csi_color_space(sd);
++
++ return 0;
++}
++
++static int tc358743_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
++ struct v4l2_subdev_format *format)
++{
++ struct tc358743_state *state = to_state(sd);
++ u8 vi_rep = i2c_rd8(sd, VI_REP);
++
++ if (format->pad != 0)
++ return -EINVAL;
++
++ format->format.code = state->mbus_fmt_code;
++ format->format.width = state->timings.bt.width;
++ format->format.height = state->timings.bt.height;
++ format->format.field = V4L2_FIELD_NONE;
++
++ switch (vi_rep & MASK_VOUT_COLOR_SEL) {
++ case MASK_VOUT_COLOR_RGB_FULL:
++ case MASK_VOUT_COLOR_RGB_LIMITED:
++ format->format.colorspace = V4L2_COLORSPACE_SRGB;
++ break;
++ case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
++ case MASK_VOUT_COLOR_601_YCBCR_FULL:
++ format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
++ break;
++ case MASK_VOUT_COLOR_709_YCBCR_FULL:
++ case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
++ format->format.colorspace = V4L2_COLORSPACE_REC709;
++ break;
++ default:
++ format->format.colorspace = 0;
++ break;
++ }
++
++ return 0;
++}
++
++static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
++ struct v4l2_dv_timings *timings)
++{
++ struct tc358743_state *state = to_state(sd);
++ struct v4l2_bt_timings *bt;
++
++ if (!timings)
++ return -EINVAL;
++
++ if (debug)
++ v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
++ timings, false);
++
++ if (!memcmp(&state->timings, timings, sizeof(struct v4l2_dv_timings))) {
++ v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
++ return 0;
++ }
++
++ bt = &timings->bt;
++
++ if (!v4l2_valid_dv_timings(timings,
++ &tc358743_timings_cap, NULL, NULL)) {
++ v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
++ return -ERANGE;
++ }
++
++ /* Fill the optional fields .standards and .flags in struct
++ * v4l2_dv_timings if the format is one of the CEA or DMT timings */
++ v4l2_find_dv_timings_cap(timings,
++ &tc358743_timings_cap, 250000, NULL, NULL);
++
++ state->timings = *timings;
++
++ enable_stream(sd, false);
++ tc358743_set_pll(sd);
++ tc358743_set_csi(sd);
++
++ return 0;
++}
++
++static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
++ struct v4l2_dv_timings *timings)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ *timings = state->timings;
++
++ return 0;
++}
++
++static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
++ struct v4l2_enum_dv_timings *timings)
++{
++ return v4l2_enum_dv_timings_cap(timings,
++ &tc358743_timings_cap, NULL, NULL);
++}
++
++static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
++ struct v4l2_dv_timings *timings)
++{
++ int ret;
++
++ ret = tc358743_get_detected_timings(sd, timings);
++ if (ret)
++ return ret;
++
++ if (debug)
++ v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
++ timings, false);
++
++ if (!v4l2_valid_dv_timings(timings,
++ &tc358743_timings_cap, NULL, NULL)) {
++ v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
++ return -ERANGE;
++ }
++
++ return 0;
++}
++
++static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
++ struct v4l2_dv_timings_cap *cap)
++{
++ *cap = tc358743_timings_cap;
++
++ return 0;
++}
++
++static int tc358743_g_mbus_config(struct v4l2_subdev *sd,
++ struct v4l2_mbus_config *cfg)
++{
++ cfg->type = V4L2_MBUS_CSI2;
++
++ cfg->flags = i2c_rd16(sd, TXOPTIONCNTRL) & MASK_CONTCLKMODE ?
++ V4L2_MBUS_CSI2_CONTINUOUS_CLOCK :
++ V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK;
++
++ switch (tc358743_num_csi_lanes_in_use(sd)) {
++ case 1:
++ cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
++ break;
++ case 2:
++ cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
++ break;
++ case 3:
++ cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
++ break;
++ case 4:
++ cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
++{
++ if (enable)
++ tc358743_start_csi(sd);
++ enable_stream(sd, enable);
++ if (!enable)
++ tc358743_set_csi(sd);
++
++ return 0;
++}
++
++/* --------------- PAD OPS --------------- */
++
++static int tc358743_g_edid(struct v4l2_subdev *sd,
++ struct v4l2_subdev_edid *edid)
++{
++ struct tc358743_state *state = to_state(sd);
++
++ if (edid->pad != 0)
++ return -EINVAL;
++
++ if (!state->edid_written)
++ return -ENODATA;
++
++ if (edid->blocks == 0)
++ return -EINVAL;
++
++ if (edid->start_block >= 8)
++ return -EINVAL;
++
++ if (edid->start_block + edid->blocks > 8)
++ edid->blocks = 8 - edid->start_block;
++
++ if (!edid->edid)
++ return -EINVAL;
++
++ i2c_rd(sd, EDID_RAM + (edid->start_block * 128), edid->edid,
++ edid->blocks * 128);
++
++ return 0;
++}
++
++static int tc358743_s_edid(struct v4l2_subdev *sd,
++ struct v4l2_subdev_edid *edid)
++{
++ struct tc358743_state *state = to_state(sd);
++ u16 edid_len = edid->blocks * 128;
++
++ v4l2_dbg(2, debug, sd, "%s\n", __func__);
++
++ if (edid->pad != 0)
++ return -EINVAL;
++
++ if (edid->start_block != 0)
++ return -EINVAL;
++
++ if (edid->blocks > 8) {
++ edid->blocks = 8;
++ return -E2BIG;
++ }
++
++ if (edid->blocks != 0 && !edid->edid)
++ return -EINVAL;
++
++ tc358743_disable_edid(sd);
++
++ i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
++ i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
++
++ if (edid->blocks == 0) {
++ state->edid_written = false;
++ return 0;
++ }
++
++ i2c_wr(sd, EDID_RAM, edid->edid, edid_len);
++
++ state->edid_written = true;
++
++ if (tx_5v_power_present(sd))
++ tc358743_enable_edid(sd);
++
++ return 0;
++}
++
++/* -------------------------------------------------------------------------- */
++
++static const struct v4l2_subdev_core_ops tc358743_core_ops = {
++ .log_status = tc358743_log_status,
++ .ioctl = tc358743_ioctl,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++ .g_register = tc358743_g_register,
++ .s_register = tc358743_s_register,
++#endif
++ .interrupt_service_routine = tc358743_isr,
++ .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
++ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
++};
++
++static const struct v4l2_subdev_video_ops tc358743_video_ops = {
++ .g_input_status = tc358743_g_input_status,
++ .s_dv_timings = tc358743_s_dv_timings,
++ .g_dv_timings = tc358743_g_dv_timings,
++ .query_dv_timings = tc358743_query_dv_timings,
++ .g_mbus_config = tc358743_g_mbus_config,
++ .s_stream = tc358743_s_stream,
++ .enum_dv_timings = tc358743_enum_dv_timings,
++ .dv_timings_cap = tc358743_dv_timings_cap,
++};
++
++static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
++ .set_fmt = tc358743_set_fmt,
++ .get_fmt = tc358743_get_fmt,
++ .get_edid = tc358743_g_edid,
++ .set_edid = tc358743_s_edid,
++};
++
++static const struct v4l2_subdev_ops tc358743_ops = {
++ .core = &tc358743_core_ops,
++ .video = &tc358743_video_ops,
++ .pad = &tc358743_pad_ops,
++};
++
++/* --------------- CUSTOM CTRLS --------------- */
++
++static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
++ .id = TC358743_CID_AUDIO_SAMPLING_RATE,
++ .name = "Audio sampling rate",
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .min = 0,
++ .max = 768000,
++ .step = 1,
++ .def = 0,
++ .flags = V4L2_CTRL_FLAG_READ_ONLY,
++};
++
++static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
++ .id = TC358743_CID_AUDIO_PRESENT,
++ .name = "Audio present",
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ .min = 0,
++ .max = 1,
++ .step = 1,
++ .def = 0,
++ .flags = V4L2_CTRL_FLAG_READ_ONLY,
++};
++
++/* --------------- PROBE / REMOVE --------------- */
++
++#if CONFIG_OF
++static void tc358743_gpio_reset(struct tc358743_state *state)
++{
++ gpiod_set_value(state->reset_gpio, 0);
++ usleep_range(5000, 10000);
++ gpiod_set_value(state->reset_gpio, 1);
++ usleep_range(1000, 2000);
++ gpiod_set_value(state->reset_gpio, 0);
++ msleep(20);
++}
++
++static int tc358743_probe_of(struct tc358743_state *state)
++{
++ struct device *dev = &state->i2c_client->dev;
++ struct device_node *np = dev->of_node;
++ struct device_node *ep;
++ struct clk *refclk;
++ u32 bps_pr_lane;
++
++ refclk = devm_clk_get(dev, "refclk");
++ if (IS_ERR(refclk)) {
++ if (PTR_ERR(refclk) != -EPROBE_DEFER)
++ dev_err(dev, "failed to get refclk: %ld\n",
++ PTR_ERR(refclk));
++ return PTR_ERR(refclk);
++ }
++
++ ep = v4l2_of_get_next_endpoint(dev->of_node, NULL);
++ if (ep) {
++ struct v4l2_of_endpoint endpoint;
++
++ v4l2_of_parse_endpoint(ep, &endpoint);
++ if (endpoint.bus_type != V4L2_MBUS_CSI2 ||
++ endpoint.bus.mipi_csi2.num_data_lanes == 0) {
++ dev_err(dev, "missing CSI-2 properties in endpoint\n");
++ return -EINVAL;
++ }
++
++ state->bus = endpoint.bus.mipi_csi2;
++ } else {
++ dev_err(dev, "missing endpoint node\n");
++ return -EINVAL;
++ }
++
++ clk_prepare_enable(refclk);
++
++ state->pdata.refclk_hz = clk_get_rate(refclk);
++ state->pdata.ddc5v_delay = DDC5V_DELAY_100MS;
++ state->pdata.enable_hdcp = false;
++ /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
++ state->pdata.fifo_level = 16;
++ /*
++ * The PLL input clock is obtained by dividing refclk by pll_prd.
++ * It must be between 6 MHz and 40 MHz, lower frequency is better.
++ */
++ switch (state->pdata.refclk_hz) {
++ case 26000000:
++ case 27000000:
++ case 42000000:
++ state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
++ break;
++ default:
++ dev_err(dev, "unsupported refclk rate: %u Hz\n",
++ state->pdata.refclk_hz);
++ clk_disable_unprepare(refclk);
++ return -EINVAL;
++ }
++
++ /*
++ * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
++ * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
++ */
++ bps_pr_lane = 594000000U;
++ of_property_read_u32(np, "toshiba,bps-per-lane", &bps_pr_lane);
++ if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
++ dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
++ clk_disable_unprepare(refclk);
++ return -EINVAL;
++ }
++ state->pdata.bps_pr_lane = bps_pr_lane;
++
++ /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
++ state->pdata.pll_fbd = state->pdata.bps_pr_lane /
++ state->pdata.refclk_hz * state->pdata.pll_prd;
++ bps_pr_lane = state->pdata.refclk_hz / state->pdata.pll_prd *
++ state->pdata.pll_fbd;
++ if (bps_pr_lane != state->pdata.bps_pr_lane) {
++ dev_warn(dev, "bps per lane corrected to %u bps\n",
++ bps_pr_lane);
++ state->pdata.bps_pr_lane = bps_pr_lane;
++ }
++
++ /* FIXME: These timings are from REF_02 for 594 Mbps per lane */
++ state->pdata.lineinitcnt = 0xe80;
++ state->pdata.lptxtimecnt = 0x003;
++ /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
++ state->pdata.tclk_headercnt = 0x1403;
++ state->pdata.tclk_trailcnt = 0x00;
++ /* ths-preparecnt: 3, ths-zerocnt: 1 */
++ state->pdata.ths_headercnt = 0x0103;
++ state->pdata.twakeup = 0x4882;
++ state->pdata.tclk_postcnt = 0x008;
++ state->pdata.ths_trailcnt = 0x2;
++ state->pdata.hstxvregcnt = 0;
++
++ /* HDMI PHY */
++ state->pdata.phy_auto_rst = 0;
++ state->pdata.hdmi_det_v = 0;
++ state->pdata.h_pi_rst = 0;
++ state->pdata.v_pi_rst = 0;
++
++ state->reset_gpio = devm_gpiod_get(dev, "reset");
++ if (!IS_ERR(state->reset_gpio)) {
++ tc358743_gpio_reset(state);
++ } else {
++ dev_warn(dev, "failed to get reset gpio\n");
++ }
++
++
++ return 0;
++}
++#else
++static inline int tc358743_probe_of(struct tc358743_state *state)
++{
++ return -ENODEV;
++}
++#endif
++
++static int tc358743_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ static struct v4l2_dv_timings default_timing =
++ V4L2_DV_BT_CEA_640X480P59_94;
++ struct tc358743_state *state;
++ struct tc358743_platform_data *pdata = client->dev.platform_data;
++ struct v4l2_subdev *sd;
++ int err;
++
++ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
++ return -EIO;
++ v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
++ client->addr << 1, client->adapter->name);
++
++ state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
++ GFP_KERNEL);
++ if (!state) {
++ v4l_err(client, "Could not allocate tc358743_state memory!\n");
++ return -ENOMEM;
++ }
++
++ state->i2c_client = client;
++
++ /* platform data */
++ if (pdata) {
++ state->pdata = *pdata;
++ } else {
++ err = tc358743_probe_of(state);
++ if (err == -ENODEV)
++ v4l_err(client, "No platform data!\n");
++ if (err)
++ return err;
++ }
++
++ sd = &state->sd;
++ v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
++ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
++
++ /* i2c access */
++ if (i2c_rd16(sd, CHIPID) != 0x0000) {
++ v4l2_info(sd, "not a TC358743 on address 0x%x\n",
++ client->addr << 1);
++ return -ENODEV;
++ }
++ /* read the interrupt mask register, it should carry the
++ * default values, as it hasn't been touched at this point.
++ */
++ if (i2c_rd16(sd, INTMASK) != 0x0400) {
++ v4l2_warn(sd, "initial interrupt mask: 0x%04x\n",
++ i2c_rd16(sd, INTMASK));
++ i2c_wr16(sd, INTMASK, 0x0400);
++ }
++
++ tc358743_clear_interrupt_status(sd);
++
++ if (state->i2c_client->irq) {
++ err = devm_request_threaded_irq(&client->dev,
++ state->i2c_client->irq,
++ NULL, tc358743_irq_handler,
++ IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
++ "tc358743", state);
++ if (err)
++ return err;
++ }
++
++ /* control handlers */
++ v4l2_ctrl_handler_init(&state->hdl, 3);
++
++ /* private controls */
++ state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
++ V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
++
++ /* custom controls */
++ state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
++ &tc358743_ctrl_audio_sampling_rate, NULL);
++
++ state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
++ &tc358743_ctrl_audio_present, NULL);
++
++ sd->ctrl_handler = &state->hdl;
++ if (state->hdl.error) {
++ err = state->hdl.error;
++ goto err_hdl;
++ }
++
++ if (tc358743_update_controls(sd)) {
++ err = -ENODEV;
++ goto err_hdl;
++ }
++
++ /* work queues */
++ state->work_queues = create_singlethread_workqueue(client->name);
++ if (!state->work_queues) {
++ v4l2_err(sd, "Could not create work queue\n");
++ err = -ENOMEM;
++ goto err_hdl;
++ }
++
++ state->pad.flags = MEDIA_PAD_FL_SOURCE;
++ err = media_entity_init(&sd->entity, 1, &state->pad, 0);
++ if (err < 0)
++ goto err_hdl;
++
++ sd->dev = &client->dev;
++ err = v4l2_async_register_subdev(sd);
++ if (err < 0)
++ goto err_hdl;
++
++ INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
++ tc358743_delayed_work_enable_hotplug);
++
++ tc358743_initial_setup(sd);
++
++ tc358743_s_dv_timings(sd, &default_timing);
++
++ state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
++ tc358743_set_csi_color_space(sd);
++
++ tc358743_enable_interrupts(sd);
++
++ v4l2_ctrl_handler_setup(sd->ctrl_handler);
++
++ v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
++ client->addr << 1, client->adapter->name);
++
++ return 0;
++
++err_hdl:
++ media_entity_cleanup(&sd->entity);
++ v4l2_ctrl_handler_free(&state->hdl);
++ return err;
++}
++
++static int tc358743_remove(struct i2c_client *client)
++{
++ struct v4l2_subdev *sd = i2c_get_clientdata(client);
++ struct tc358743_state *state = to_state(sd);
++
++ cancel_delayed_work(&state->delayed_work_enable_hotplug);
++ destroy_workqueue(state->work_queues);
++ v4l2_async_unregister_subdev(sd);
++ v4l2_device_unregister_subdev(sd);
++ v4l2_ctrl_handler_free(&state->hdl);
++
++ return 0;
++}
++
++static struct i2c_device_id tc358743_id[] = {
++ {"tc358743", 0},
++ {}
++};
++
++MODULE_DEVICE_TABLE(i2c, tc358743_id);
++
++static struct i2c_driver tc358743_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "tc358743",
++ },
++ .probe = tc358743_probe,
++ .remove = tc358743_remove,
++ .id_table = tc358743_id,
++};
++
++module_i2c_driver(tc358743_driver);
+diff -Nur linux-3.14.72.orig/drivers/media/i2c/tc358743_regs.h linux-3.14.72/drivers/media/i2c/tc358743_regs.h
+--- linux-3.14.72.orig/drivers/media/i2c/tc358743_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/i2c/tc358743_regs.h 2016-06-19 22:11:55.169148931 +0200
+@@ -0,0 +1,670 @@
++/*
++ * tc358743 - Toshiba HDMI to CSI-2 bridge - register names and bit masks
++ *
++ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
++ * reserved.
++ *
++ * This program is free software; you may redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ *
++ */
++
++/*
++ * References (c = chapter, p = page):
++ * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
++ */
++
++/* Bit masks has prefix 'MASK_' and options after '_'. */
++
++#ifndef __TC358743_REGS_H
++#define __TC358743_REGS_H
++
++#define CHIPID 0x0000
++#define MASK_CHIPID 0xff00
++#define MASK_REVID 0x00ff
++
++#define SYSCTL 0x0002
++#define MASK_IRRST 0x0800
++#define MASK_CECRST 0x0400
++#define MASK_CTXRST 0x0200
++#define MASK_HDMIRST 0x0100
++#define MASK_SLEEP 0x0001
++
++#define CONFCTL 0x0004
++#define MASK_PWRISO 0x8000
++#define MASK_ACLKOPT 0x1000
++#define MASK_AUDCHNUM 0x0c00
++#define MASK_AUDCHNUM_8 0x0000
++#define MASK_AUDCHNUM_6 0x0400
++#define MASK_AUDCHNUM_4 0x0800
++#define MASK_AUDCHNUM_2 0x0c00
++#define MASK_AUDCHSEL 0x0200
++#define MASK_I2SDLYOPT 0x0100
++#define MASK_YCBCRFMT 0x00c0
++#define MASK_YCBCRFMT_444 0x0000
++#define MASK_YCBCRFMT_422_12_BIT 0x0040
++#define MASK_YCBCRFMT_COLORBAR 0x0080
++#define MASK_YCBCRFMT_422_8_BIT 0x00c0
++#define MASK_INFRMEN 0x0020
++#define MASK_AUDOUTSEL 0x0018
++#define MASK_AUDOUTSEL_CSI 0x0000
++#define MASK_AUDOUTSEL_I2S 0x0010
++#define MASK_AUDOUTSEL_TDM 0x0018
++#define MASK_AUTOINDEX 0x0004
++#define MASK_ABUFEN 0x0002
++#define MASK_VBUFEN 0x0001
++
++#define FIFOCTL 0x0006
++
++#define INTSTATUS 0x0014
++#define MASK_AMUTE_INT 0x0400
++#define MASK_HDMI_INT 0x0200
++#define MASK_CSI_INT 0x0100
++#define MASK_SYS_INT 0x0020
++#define MASK_CEC_EINT 0x0010
++#define MASK_CEC_TINT 0x0008
++#define MASK_CEC_RINT 0x0004
++#define MASK_IR_EINT 0x0002
++#define MASK_IR_DINT 0x0001
++
++#define INTMASK 0x0016
++#define MASK_AMUTE_MSK 0x0400
++#define MASK_HDMI_MSK 0x0200
++#define MASK_CSI_MSK 0x0100
++#define MASK_SYS_MSK 0x0020
++#define MASK_CEC_EMSK 0x0010
++#define MASK_CEC_TMSK 0x0008
++#define MASK_CEC_RMSK 0x0004
++#define MASK_IR_EMSK 0x0002
++#define MASK_IR_DMSK 0x0001
++
++#define INTFLAG 0x0018
++#define INTSYSSTATUS 0x001A
++
++#define PLLCTL0 0x0020
++#define MASK_PLL_PRD 0xf000
++#define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\
++ MASK_PLL_PRD)
++#define MASK_PLL_FBD 0x01ff
++#define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD)
++
++#define PLLCTL1 0x0022
++#define MASK_PLL_FRS 0x0c00
++#define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_PRD)
++#define MASK_PLL_LBWS 0x0300
++#define MASK_LFBREN 0x0040
++#define MASK_BYPCKEN 0x0020
++#define MASK_CKEN 0x0010
++#define MASK_RESETB 0x0002
++#define MASK_PLL_EN 0x0001
++
++#define CLW_CNTRL 0x0140
++#define MASK_CLW_LANEDISABLE 0x0001
++
++#define D0W_CNTRL 0x0144
++#define MASK_D0W_LANEDISABLE 0x0001
++
++#define D1W_CNTRL 0x0148
++#define MASK_D1W_LANEDISABLE 0x0001
++
++#define D2W_CNTRL 0x014C
++#define MASK_D2W_LANEDISABLE 0x0001
++
++#define D3W_CNTRL 0x0150
++#define MASK_D3W_LANEDISABLE 0x0001
++
++#define STARTCNTRL 0x0204
++#define MASK_START 0x00000001
++
++#define LINEINITCNT 0x0210
++#define LPTXTIMECNT 0x0214
++#define TCLK_HEADERCNT 0x0218
++#define TCLK_TRAILCNT 0x021C
++#define THS_HEADERCNT 0x0220
++#define TWAKEUP 0x0224
++#define TCLK_POSTCNT 0x0228
++#define THS_TRAILCNT 0x022C
++#define HSTXVREGCNT 0x0230
++
++#define HSTXVREGEN 0x0234
++#define MASK_D3M_HSTXVREGEN 0x0010
++#define MASK_D2M_HSTXVREGEN 0x0008
++#define MASK_D1M_HSTXVREGEN 0x0004
++#define MASK_D0M_HSTXVREGEN 0x0002
++#define MASK_CLM_HSTXVREGEN 0x0001
++
++
++#define TXOPTIONCNTRL 0x0238
++#define MASK_CONTCLKMODE 0x00000001
++
++#define CSI_CONTROL 0x040C
++#define MASK_CSI_MODE 0x8000
++#define MASK_HTXTOEN 0x0400
++#define MASK_TXHSMD 0x0080
++#define MASK_HSCKMD 0x0020
++#define MASK_NOL 0x0006
++#define MASK_NOL_1 0x0000
++#define MASK_NOL_2 0x0002
++#define MASK_NOL_3 0x0004
++#define MASK_NOL_4 0x0006
++#define MASK_EOTDIS 0x0001
++
++#define CSI_INT 0x0414
++#define MASK_INTHLT 0x00000008
++#define MASK_INTER 0x00000004
++
++#define CSI_INT_ENA 0x0418
++#define MASK_IENHLT 0x00000008
++#define MASK_IENER 0x00000004
++
++#define CSI_ERR 0x044C
++#define MASK_INER 0x00000200
++#define MASK_WCER 0x00000100
++#define MASK_QUNK 0x00000010
++#define MASK_TXBRK 0x00000002
++
++#define CSI_ERR_INTENA 0x0450
++#define CSI_ERR_HALT 0x0454
++
++#define CSI_CONFW 0x0500
++#define MASK_MODE 0xe0000000
++#define MASK_MODE_SET 0xa0000000
++#define MASK_MODE_CLEAR 0xc0000000
++#define MASK_ADDRESS 0x1f000000
++#define MASK_ADDRESS_CSI_CONTROL 0x03000000
++#define MASK_ADDRESS_CSI_INT_ENA 0x06000000
++#define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000
++#define MASK_ADDRESS_CSI_ERR_HALT 0x15000000
++#define MASK_DATA 0x0000ffff
++
++#define CSI_INT_CLR 0x050C
++#define MASK_ICRER 0x00000004
++
++#define CSI_START 0x0518
++#define MASK_STRT 0x00000001
++
++#define CECEN 0x0600
++#define MASK_CECEN 0x0001
++
++#define HDMI_INT0 0x8500
++#define MASK_I_KEY 0x80
++#define MASK_I_MISC 0x02
++#define MASK_I_PHYERR 0x01
++
++#define HDMI_INT1 0x8501
++#define MASK_I_GBD 0x80
++#define MASK_I_HDCP 0x40
++#define MASK_I_ERR 0x20
++#define MASK_I_AUD 0x10
++#define MASK_I_CBIT 0x08
++#define MASK_I_PACKET 0x04
++#define MASK_I_CLK 0x02
++#define MASK_I_SYS 0x01
++
++#define SYS_INT 0x8502
++#define MASK_I_ACR_CTS 0x80
++#define MASK_I_ACRN 0x40
++#define MASK_I_DVI 0x20
++#define MASK_I_HDMI 0x10
++#define MASK_I_NOPMBDET 0x08
++#define MASK_I_DPMBDET 0x04
++#define MASK_I_TMDS 0x02
++#define MASK_I_DDC 0x01
++
++#define CLK_INT 0x8503
++#define MASK_I_OUT_H_CHG 0x40
++#define MASK_I_IN_DE_CHG 0x20
++#define MASK_I_IN_HV_CHG 0x10
++#define MASK_I_DC_CHG 0x08
++#define MASK_I_PXCLK_CHG 0x04
++#define MASK_I_PHYCLK_CHG 0x02
++#define MASK_I_TMDSCLK_CHG 0x01
++
++#define CBIT_INT 0x8505
++#define MASK_I_AF_LOCK 0x80
++#define MASK_I_AF_UNLOCK 0x40
++#define MASK_I_CBIT_FS 0x02
++
++#define ERR_INT 0x8507
++#define MASK_I_EESS_ERR 0x80
++
++#define HDCP_INT 0x8508
++#define MASK_I_AVM_SET 0x80
++#define MASK_I_AVM_CLR 0x40
++#define MASK_I_LINKERR 0x20
++#define MASK_I_SHA_END 0x10
++#define MASK_I_R0_END 0x08
++#define MASK_I_KM_END 0x04
++#define MASK_I_AKSV_END 0x02
++#define MASK_I_AN_END 0x01
++
++#define MISC_INT 0x850B
++#define MASK_I_AS_LAYOUT 0x10
++#define MASK_I_NO_SPD 0x08
++#define MASK_I_NO_VS 0x03
++#define MASK_I_SYNC_CHG 0x02
++#define MASK_I_AUDIO_MUTE 0x01
++
++#define KEY_INT 0x850F
++
++#define SYS_INTM 0x8512
++#define MASK_M_ACR_CTS 0x80
++#define MASK_M_ACR_N 0x40
++#define MASK_M_DVI_DET 0x20
++#define MASK_M_HDMI_DET 0x10
++#define MASK_M_NOPMBDET 0x08
++#define MASK_M_BPMBDET 0x04
++#define MASK_M_TMDS 0x02
++#define MASK_M_DDC 0x01
++
++#define CLK_INTM 0x8513
++#define MASK_M_OUT_H_CHG 0x40
++#define MASK_M_IN_DE_CHG 0x20
++#define MASK_M_IN_HV_CHG 0x10
++#define MASK_M_DC_CHG 0x08
++#define MASK_M_PXCLK_CHG 0x04
++#define MASK_M_PHYCLK_CHG 0x02
++#define MASK_M_TMDS_CHG 0x01
++
++#define PACKET_INTM 0x8514
++
++#define CBIT_INTM 0x8515
++#define MASK_M_AF_LOCK 0x80
++#define MASK_M_AF_UNLOCK 0x40
++#define MASK_M_CBIT_FS 0x02
++
++#define AUDIO_INTM 0x8516
++
++#define ERR_INTM 0x8517
++#define MASK_M_EESS_ERR 0x80
++
++#define HDCP_INTM 0x8518
++#define MASK_M_AVM_SET 0x80
++#define MASK_M_AVM_CLR 0x40
++#define MASK_M_LINKERR 0x20
++#define MASK_M_SHA_END 0x10
++#define MASK_M_R0_END 0x08
++#define MASK_M_KM_END 0x04
++#define MASK_M_AKSV_END 0x02
++#define MASK_M_AN_END 0x01
++
++#define MISC_INTM 0x851B
++#define MASK_M_AS_LAYOUT 0x10
++#define MASK_M_NO_SPD 0x08
++#define MASK_M_NO_VS 0x03
++#define MASK_M_SYNC_CHG 0x02
++#define MASK_M_AUDIO_MUTE 0x01
++
++#define KEY_INTM 0x851F
++
++#define SYS_STATUS 0x8520
++#define MASK_S_SYNC 0x80
++#define MASK_S_AVMUTE 0x40
++#define MASK_S_HDCP 0x20
++#define MASK_S_HDMI 0x10
++#define MASK_S_PHY_SCDT 0x08
++#define MASK_S_PHY_PLL 0x04
++#define MASK_S_TMDS 0x02
++#define MASK_S_DDC5V 0x01
++
++#define CSI_STATUS 0x0410
++#define MASK_S_WSYNC 0x0400
++#define MASK_S_TXACT 0x0200
++#define MASK_S_RXACT 0x0100
++#define MASK_S_HLT 0x0001
++
++#define VI_STATUS1 0x8522
++#define MASK_S_V_GBD 0x08
++#define MASK_S_DEEPCOLOR 0x0c
++#define MASK_S_V_422 0x02
++#define MASK_S_V_INTERLACE 0x01
++
++#define AU_STATUS0 0x8523
++#define MASK_S_A_SAMPLE 0x01
++
++#define VI_STATUS3 0x8528
++#define MASK_S_V_COLOR 0x1e
++#define MASK_LIMITED 0x01
++
++#define PHY_CTL0 0x8531
++#define MASK_PHY_SYSCLK_IND 0x02
++#define MASK_PHY_CTL 0x01
++
++
++#define PHY_CTL1 0x8532 /* Not in REF_01 */
++#define MASK_PHY_AUTO_RST1 0xf0
++#define MASK_PHY_AUTO_RST1_OFF 0x00
++#define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \
++ MASK_PHY_AUTO_RST1)
++#define MASK_FREQ_RANGE_MODE 0x0f
++#define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \
++ MASK_FREQ_RANGE_MODE)
++
++#define PHY_CTL2 0x8533 /* Not in REF_01 */
++#define MASK_PHY_AUTO_RST4 0x04
++#define MASK_PHY_AUTO_RST3 0x02
++#define MASK_PHY_AUTO_RST2 0x01
++#define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \
++ MASK_PHY_AUTO_RST3 | \
++ MASK_PHY_AUTO_RST2)
++
++#define PHY_EN 0x8534
++#define MASK_ENABLE_PHY 0x01
++
++#define PHY_RST 0x8535
++#define MASK_RESET_CTRL 0x01 /* Reset active low */
++
++#define PHY_BIAS 0x8536 /* Not in REF_01 */
++
++#define PHY_CSQ 0x853F /* Not in REF_01 */
++#define MASK_CSQ_CNT 0x0f
++#define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT)
++
++#define SYS_FREQ0 0x8540
++#define SYS_FREQ1 0x8541
++
++#define SYS_CLK 0x8542 /* Not in REF_01 */
++#define MASK_CLK_DIFF 0x0C
++#define MASK_CLK_DIV 0x03
++
++#define DDC_CTL 0x8543
++#define MASK_DDC_ACK_POL 0x08
++#define MASK_DDC_ACTION 0x04
++#define MASK_DDC5V_MODE 0x03
++#define MASK_DDC5V_MODE_0MS 0x00
++#define MASK_DDC5V_MODE_50MS 0x01
++#define MASK_DDC5V_MODE_100MS 0x02
++#define MASK_DDC5V_MODE_200MS 0x03
++
++#define HPD_CTL 0x8544
++#define MASK_HPD_CTL0 0x10
++#define MASK_HPD_OUT0 0x01
++
++#define ANA_CTL 0x8545
++#define MASK_APPL_PCSX 0x30
++#define MASK_APPL_PCSX_HIZ 0x00
++#define MASK_APPL_PCSX_L_FIX 0x10
++#define MASK_APPL_PCSX_H_FIX 0x20
++#define MASK_APPL_PCSX_NORMAL 0x30
++#define MASK_ANALOG_ON 0x01
++
++#define AVM_CTL 0x8546
++
++#define INIT_END 0x854A
++#define MASK_INIT_END 0x01
++
++#define HDMI_DET 0x8552
++#define MASK_HDMI_DET_MOD1 0x80
++#define MASK_HDMI_DET_MOD0 0x40
++#define MASK_HDMI_DET_V 0x30
++#define MASK_HDMI_DET_V_SYNC 0x00
++#define MASK_HDMI_DET_V_ASYNC_25MS 0x10
++#define MASK_HDMI_DET_V_ASYNC_50MS 0x20
++#define MASK_HDMI_DET_V_ASYNC_100MS 0x30
++#define MASK_HDMI_DET_NUM 0x0f
++
++#define HDCP_MODE 0x8560
++#define MASK_MODE_RST_TN 0x20
++#define MASK_LINE_REKEY 0x10
++#define MASK_AUTO_CLR 0x04
++
++#define HDCP_REG1 0x8563 /* Not in REF_01 */
++#define MASK_AUTH_UNAUTH_SEL 0x70
++#define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70
++#define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60
++#define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50
++#define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40
++#define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30
++#define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20
++#define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10
++#define MASK_AUTH_UNAUTH_SEL_ONCE 0x00
++#define MASK_AUTH_UNAUTH 0x01
++#define MASK_AUTH_UNAUTH_AUTO 0x01
++
++#define HDCP_REG2 0x8564 /* Not in REF_01 */
++#define MASK_AUTO_P3_RESET 0x0F
++#define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET)
++#define MASK_AUTO_P3_RESET_OFF 0x00
++
++#define VOUT_SET2 0x8573
++#define MASK_SEL422 0x80
++#define MASK_VOUT_422FIL_100 0x40
++#define MASK_VOUTCOLORMODE 0x03
++#define MASK_VOUTCOLORMODE_THROUGH 0x00
++#define MASK_VOUTCOLORMODE_AUTO 0x01
++#define MASK_VOUTCOLORMODE_MANUAL 0x03
++
++#define VOUT_SET3 0x8574
++#define MASK_VOUT_EXTCNT 0x08
++
++#define VI_REP 0x8576
++#define MASK_VOUT_COLOR_SEL 0xe0
++#define MASK_VOUT_COLOR_RGB_FULL 0x00
++#define MASK_VOUT_COLOR_RGB_LIMITED 0x20
++#define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40
++#define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60
++#define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80
++#define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0
++#define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0
++#define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0
++#define MASK_IN_REP_HEN 0x10
++#define MASK_IN_REP 0x0f
++
++#define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */
++#define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */
++#define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */
++#define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */
++#define H_SIZE_LO 0x858A /* Not in REF_01 */
++#define H_SIZE_HI 0x858B /* Not in REF_01 */
++#define V_SIZE_LO 0x858C /* Not in REF_01 */
++#define V_SIZE_HI 0x858D /* Not in REF_01 */
++#define FV_CNT_LO 0x85A1 /* Not in REF_01 */
++#define FV_CNT_HI 0x85A2 /* Not in REF_01 */
++
++#define FH_MIN0 0x85AA /* Not in REF_01 */
++#define FH_MIN1 0x85AB /* Not in REF_01 */
++#define FH_MAX0 0x85AC /* Not in REF_01 */
++#define FH_MAX1 0x85AD /* Not in REF_01 */
++#define HV_RST 0x85AF /* Not in REF_01 */
++#define MASK_H_PI_RST 0x20
++#define MASK_V_PI_RST 0x10
++
++#define EDID_MODE 0x85C7
++#define MASK_EDID_SPEED 0x40
++#define MASK_EDID_MODE 0x03
++#define MASK_EDID_MODE_DISABLE 0x00
++#define MASK_EDID_MODE_DDC2B 0x01
++#define MASK_EDID_MODE_E_DDC 0x02
++
++#define EDID_LEN1 0x85CA
++#define EDID_LEN2 0x85CB
++
++#define HDCP_REG3 0x85D1 /* Not in REF_01 */
++#define KEY_RD_CMD 0x01
++
++#define FORCE_MUTE 0x8600
++#define MASK_FORCE_AMUTE 0x10
++#define MASK_FORCE_DMUTE 0x01
++
++#define CMD_AUD 0x8601
++#define MASK_CMD_BUFINIT 0x04
++#define MASK_CMD_LOCKDET 0x02
++#define MASK_CMD_MUTE 0x01
++
++#define AUTO_CMD0 0x8602
++#define MASK_AUTO_MUTE7 0x80
++#define MASK_AUTO_MUTE6 0x40
++#define MASK_AUTO_MUTE5 0x20
++#define MASK_AUTO_MUTE4 0x10
++#define MASK_AUTO_MUTE3 0x08
++#define MASK_AUTO_MUTE2 0x04
++#define MASK_AUTO_MUTE1 0x02
++#define MASK_AUTO_MUTE0 0x01
++
++#define AUTO_CMD1 0x8603
++#define MASK_AUTO_MUTE10 0x04
++#define MASK_AUTO_MUTE9 0x02
++#define MASK_AUTO_MUTE8 0x01
++
++#define AUTO_CMD2 0x8604
++#define MASK_AUTO_PLAY3 0x08
++#define MASK_AUTO_PLAY2 0x04
++
++#define BUFINIT_START 0x8606
++#define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100)
++
++#define FS_MUTE 0x8607
++#define MASK_FS_ELSE_MUTE 0x80
++#define MASK_FS22_MUTE 0x40
++#define MASK_FS24_MUTE 0x20
++#define MASK_FS88_MUTE 0x10
++#define MASK_FS96_MUTE 0x08
++#define MASK_FS176_MUTE 0x04
++#define MASK_FS192_MUTE 0x02
++#define MASK_FS_NO_MUTE 0x01
++
++#define FS_IMODE 0x8620
++#define MASK_NLPCM_HMODE 0x40
++#define MASK_NLPCM_SMODE 0x20
++#define MASK_NLPCM_IMODE 0x10
++#define MASK_FS_HMODE 0x08
++#define MASK_FS_AMODE 0x04
++#define MASK_FS_SMODE 0x02
++#define MASK_FS_IMODE 0x01
++
++#define FS_SET 0x8621
++#define MASK_FS 0x0f
++
++#define LOCKDET_REF0 0x8630
++#define LOCKDET_REF1 0x8631
++#define LOCKDET_REF2 0x8632
++
++#define ACR_MODE 0x8640
++#define MASK_ACR_LOAD 0x10
++#define MASK_N_MODE 0x04
++#define MASK_CTS_MODE 0x01
++
++#define ACR_MDF0 0x8641
++#define MASK_ACR_L2MDF 0x70
++#define MASK_ACR_L2MDF_0_PPM 0x00
++#define MASK_ACR_L2MDF_61_PPM 0x10
++#define MASK_ACR_L2MDF_122_PPM 0x20
++#define MASK_ACR_L2MDF_244_PPM 0x30
++#define MASK_ACR_L2MDF_488_PPM 0x40
++#define MASK_ACR_L2MDF_976_PPM 0x50
++#define MASK_ACR_L2MDF_1976_PPM 0x60
++#define MASK_ACR_L2MDF_3906_PPM 0x70
++#define MASK_ACR_L1MDF 0x07
++#define MASK_ACR_L1MDF_0_PPM 0x00
++#define MASK_ACR_L1MDF_61_PPM 0x01
++#define MASK_ACR_L1MDF_122_PPM 0x02
++#define MASK_ACR_L1MDF_244_PPM 0x03
++#define MASK_ACR_L1MDF_488_PPM 0x04
++#define MASK_ACR_L1MDF_976_PPM 0x05
++#define MASK_ACR_L1MDF_1976_PPM 0x06
++#define MASK_ACR_L1MDF_3906_PPM 0x07
++
++#define ACR_MDF1 0x8642
++#define MASK_ACR_L3MDF 0x07
++#define MASK_ACR_L3MDF_0_PPM 0x00
++#define MASK_ACR_L3MDF_61_PPM 0x01
++#define MASK_ACR_L3MDF_122_PPM 0x02
++#define MASK_ACR_L3MDF_244_PPM 0x03
++#define MASK_ACR_L3MDF_488_PPM 0x04
++#define MASK_ACR_L3MDF_976_PPM 0x05
++#define MASK_ACR_L3MDF_1976_PPM 0x06
++#define MASK_ACR_L3MDF_3906_PPM 0x07
++
++#define SDO_MODE1 0x8652
++#define MASK_SDO_BIT_LENG 0x70
++#define MASK_SDO_FMT 0x03
++#define MASK_SDO_FMT_RIGHT 0x00
++#define MASK_SDO_FMT_LEFT 0x01
++#define MASK_SDO_FMT_I2S 0x02
++
++#define DIV_MODE 0x8665 /* Not in REF_01 */
++#define MASK_DIV_DLY 0xf0
++#define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \
++ MASK_DIV_DLY)
++#define MASK_DIV_MODE 0x01
++
++#define NCO_F0_MOD 0x8670
++#define MASK_NCO_F0_MOD 0x03
++#define MASK_NCO_F0_MOD_42MHZ 0x00
++#define MASK_NCO_F0_MOD_27MHZ 0x01
++
++#define PK_INT_MODE 0x8709
++#define MASK_ISRC2_INT_MODE 0x80
++#define MASK_ISRC_INT_MODE 0x40
++#define MASK_ACP_INT_MODE 0x20
++#define MASK_VS_INT_MODE 0x10
++#define MASK_SPD_INT_MODE 0x08
++#define MASK_MS_INT_MODE 0x04
++#define MASK_AUD_INT_MODE 0x02
++#define MASK_AVI_INT_MODE 0x01
++
++#define NO_PKT_LIMIT 0x870B
++#define MASK_NO_ACP_LIMIT 0xf0
++#define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \
++ MASK_NO_ACP_LIMIT)
++#define MASK_NO_AVI_LIMIT 0x0f
++#define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \
++ MASK_NO_AVI_LIMIT)
++
++#define NO_PKT_CLR 0x870C
++#define MASK_NO_VS_CLR 0x40
++#define MASK_NO_SPD_CLR 0x20
++#define MASK_NO_ACP_CLR 0x10
++#define MASK_NO_AVI_CLR1 0x02
++#define MASK_NO_AVI_CLR0 0x01
++
++#define ERR_PK_LIMIT 0x870D
++#define NO_PKT_LIMIT2 0x870E
++#define PK_AVI_0HEAD 0x8710
++#define PK_AVI_1HEAD 0x8711
++#define PK_AVI_2HEAD 0x8712
++#define PK_AVI_0BYTE 0x8713
++#define PK_AVI_1BYTE 0x8714
++#define PK_AVI_2BYTE 0x8715
++#define PK_AVI_3BYTE 0x8716
++#define PK_AVI_4BYTE 0x8717
++#define PK_AVI_5BYTE 0x8718
++#define PK_AVI_6BYTE 0x8719
++#define PK_AVI_7BYTE 0x871A
++#define PK_AVI_8BYTE 0x871B
++#define PK_AVI_9BYTE 0x871C
++#define PK_AVI_10BYTE 0x871D
++#define PK_AVI_11BYTE 0x871E
++#define PK_AVI_12BYTE 0x871F
++#define PK_AVI_13BYTE 0x8720
++#define PK_AVI_14BYTE 0x8721
++#define PK_AVI_15BYTE 0x8722
++#define PK_AVI_16BYTE 0x8723
++
++#define BKSV 0x8800
++
++#define BCAPS 0x8840
++#define MASK_HDMI_RSVD 0x80
++#define MASK_REPEATER 0x40
++#define MASK_READY 0x20
++#define MASK_FASTI2C 0x10
++#define MASK_1_1_FEA 0x02
++#define MASK_FAST_REAU 0x01
++
++#define BSTATUS1 0x8842
++#define MASK_MAX_EXCED 0x08
++
++#define EDID_RAM 0x8C00
++#define NO_GDB_LIMIT 0x9007
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/media/pci/cx88/cx88-core.c linux-3.14.72/drivers/media/pci/cx88/cx88-core.c
+--- linux-3.14.72.orig/drivers/media/pci/cx88/cx88-core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/pci/cx88/cx88-core.c 2016-06-19 22:11:55.169148931 +0200
+@@ -1034,14 +1034,7 @@
+ if (NULL == vfd)
+ return NULL;
+ *vfd = *template_;
+- /*
+- * The dev pointer of v4l2_device is NULL, instead we set the
+- * video_device dev_parent pointer to the correct PCI bus device.
+- * This driver is a rare example where there is one v4l2_device,
+- * but the video nodes have different parent (PCI) devices.
+- */
+ vfd->v4l2_dev = &core->v4l2_dev;
+- vfd->dev_parent = &pci->dev;
+ vfd->release = video_device_release;
+ snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)",
+ core->name, type, core->board.name);
+diff -Nur linux-3.14.72.orig/drivers/media/pci/Kconfig linux-3.14.72/drivers/media/pci/Kconfig
+--- linux-3.14.72.orig/drivers/media/pci/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/pci/Kconfig 2016-06-19 22:11:55.169148931 +0200
+@@ -12,6 +12,7 @@
+ comment "Media capture support"
+ source "drivers/media/pci/meye/Kconfig"
+ source "drivers/media/pci/sta2x11/Kconfig"
++source "drivers/media/pci/tw6869/Kconfig"
+ endif
+
+ if MEDIA_ANALOG_TV_SUPPORT
+diff -Nur linux-3.14.72.orig/drivers/media/pci/Makefile linux-3.14.72/drivers/media/pci/Makefile
+--- linux-3.14.72.orig/drivers/media/pci/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/pci/Makefile 2016-06-19 22:11:55.169148931 +0200
+@@ -24,3 +24,4 @@
+ obj-$(CONFIG_VIDEO_SAA7164) += saa7164/
+ obj-$(CONFIG_VIDEO_MEYE) += meye/
+ obj-$(CONFIG_STA2X11_VIP) += sta2x11/
++obj-$(CONFIG_VIDEO_TW6869) += tw6869/
+diff -Nur linux-3.14.72.orig/drivers/media/pci/tw6869/Kconfig linux-3.14.72/drivers/media/pci/tw6869/Kconfig
+--- linux-3.14.72.orig/drivers/media/pci/tw6869/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/pci/tw6869/Kconfig 2016-06-19 22:11:55.169148931 +0200
+@@ -0,0 +1,9 @@
++config VIDEO_TW6869
++ tristate "Techwell tw6869 Video For Linux"
++ depends on VIDEO_DEV && PCI && VIDEO_V4L2
++ select VIDEOBUF2_DMA_CONTIG
++ ---help---
++ Support for Techwell tw6869 based frame grabber boards.
++
++ To compile this driver as a module, choose M here: the
++ module will be called tw6869.
+diff -Nur linux-3.14.72.orig/drivers/media/pci/tw6869/Makefile linux-3.14.72/drivers/media/pci/tw6869/Makefile
+--- linux-3.14.72.orig/drivers/media/pci/tw6869/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/pci/tw6869/Makefile 2016-06-19 22:11:55.169148931 +0200
+@@ -0,0 +1 @@
++obj-$(CONFIG_VIDEO_TW6869) += tw6869.o
+diff -Nur linux-3.14.72.orig/drivers/media/pci/tw6869/tw6869.c linux-3.14.72/drivers/media/pci/tw6869/tw6869.c
+--- linux-3.14.72.orig/drivers/media/pci/tw6869/tw6869.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/pci/tw6869/tw6869.c 2016-06-19 22:11:55.169148931 +0200
+@@ -0,0 +1,1439 @@
++/*
++ * Copyright 2015 www.starterkit.ru <info@starterkit.ru>
++ *
++ * Based on:
++ * Driver for Intersil|Techwell TW6869 based DVR cards
++ * (c) 2011-12 liran <jli11@intersil.com> [Intersil|Techwell China]
++ *
++ * V4L2 PCI Skeleton Driver
++ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates.
++ * All rights reserved.
++ *
++ * This program is free software; you may redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ */
++
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/kmod.h>
++#include <linux/mutex.h>
++#include <linux/pci.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/videodev2.h>
++
++#include <media/v4l2-device.h>
++#include <media/v4l2-dev.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-event.h>
++#include <media/videobuf2-dma-contig.h>
++
++#include <sound/core.h>
++#include <sound/initval.h>
++#include <sound/pcm.h>
++#include <sound/control.h>
++
++#include "tw6869.h"
++
++MODULE_DESCRIPTION("tw6869/65 media bridge driver");
++MODULE_AUTHOR("starterkit <info@starterkit.ru>");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("0.3.2");
++
++static const struct pci_device_id tw6869_pci_tbl[] = {
++ {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6869)},
++ { 0, }
++};
++
++struct tw6869_buf {
++ struct vb2_buffer vb;
++ struct list_head list;
++ dma_addr_t dma;
++};
++
++/**
++ * struct tw6869_vch - instance of one video channel
++ * @dev: parent device
++ * @vdev: video channel (v4l2 video device)
++ * @id: DMA id (0...7)
++ * @p_buf: DMA P-buffer
++ * @b_buf: DMA B-buffer
++ * @pb: P-buffer | B-buffer ping-pong state
++ * @mlock: the main serialization lock
++ * @queue: queue maintained by videobuf2 layer
++ * @buf_list: list of buffer in use
++ * @lock: spinlock controlling access to channel
++ * @hdl: handler for control framework
++ * @format: pixel format
++ * @std: video standard (e.g. PAL/NTSC)
++ * @input: input line for video signal
++ * @sequence: sequence number of acquired buffer
++ * @dcount: number of dropped frames
++ * @fps: current frame rate
++ */
++struct tw6869_vch {
++ struct tw6869_dev *dev;
++ struct video_device vdev;
++
++ unsigned int id;
++ struct tw6869_buf *p_buf;
++ struct tw6869_buf *b_buf;
++ unsigned int pb;
++
++ struct mutex mlock;
++ struct vb2_queue queue;
++ struct list_head buf_list;
++ spinlock_t lock;
++
++ struct v4l2_ctrl_handler hdl;
++ struct v4l2_pix_format format;
++ v4l2_std_id std;
++ unsigned int input;
++
++ unsigned int sequence;
++ unsigned int dcount;
++ unsigned int fps;
++};
++
++/**
++ * struct tw6869_ach - instance of one audio channel
++ * @dev: parent device
++ * @ss: audio channel (pcm substream)
++ * @id: DMA id (8...15)
++ * @p_buf: DMA P-buffer
++ * @b_buf: DMA B-buffer
++ * @pb: P-buffer | B-buffer ping-pong state
++ * @buf: split an contiguous buffer into chunks
++ * @buf_list: chunk list
++ * @lock: spinlock controlling access to channel
++ * @ptr: PCM buffer pointer
++ */
++struct tw6869_ach {
++ struct tw6869_dev *dev;
++ struct snd_pcm_substream *ss;
++
++ unsigned int id;
++ struct tw6869_buf *p_buf;
++ struct tw6869_buf *b_buf;
++ unsigned int pb;
++
++ struct tw6869_buf buf[TW_APAGE_MAX];
++ struct list_head buf_list;
++ spinlock_t lock;
++
++ dma_addr_t ptr;
++};
++
++/**
++ * struct tw6869_dev - instance of device
++ * @pdev: PCI device
++ * @mmio: hardware base address
++ * @rlock: spinlock controlling access to registers
++ * @ch_max: channels used
++ * @id_err: DMA error counters
++ * @v4l2_dev: device registered in v4l2 layer
++ * @alloc_ctx: context for videobuf2
++ * @vch: array of video channel instance
++ * @snd_card: device registered in ALSA layer
++ * @ach: array of audio channel instance
++ */
++struct tw6869_dev {
++ struct pci_dev *pdev;
++ unsigned char __iomem *mmio;
++ spinlock_t rlock;
++
++ unsigned int ch_max;
++ unsigned int id_err[2 * TW_CH_MAX];
++
++ struct v4l2_device v4l2_dev;
++ struct vb2_alloc_ctx *alloc_ctx;
++ struct tw6869_vch vch[TW_CH_MAX];
++
++ struct snd_card *snd_card;
++ struct tw6869_ach ach[TW_CH_MAX];
++};
++
++/**********************************************************************/
++
++static inline void tw_write(struct tw6869_dev *dev, unsigned int reg,
++ unsigned int val)
++{
++ iowrite32(val, dev->mmio + reg);
++}
++
++static inline unsigned int tw_read(struct tw6869_dev *dev,
++ unsigned int reg)
++{
++ return ioread32(dev->mmio + reg);
++}
++
++static inline void tw_write_mask(struct tw6869_dev *dev,
++ unsigned int reg, unsigned int val, unsigned int mask)
++{
++ unsigned int v = tw_read(dev, reg);
++
++ v = (v & ~mask) | (val & mask);
++ tw_write(dev, reg, v);
++}
++
++static inline void tw_clear(struct tw6869_dev *dev,
++ unsigned int reg, unsigned int val)
++{
++ tw_write_mask(dev, reg, 0, val);
++}
++
++static inline void tw_set(struct tw6869_dev *dev,
++ unsigned int reg, unsigned int val)
++{
++ tw_write_mask(dev, reg, val, val);
++}
++
++static inline unsigned int tw_id_is_on(struct tw6869_dev *dev,
++ unsigned int id)
++{
++ unsigned int e = tw_read(dev, R32_DMA_CHANNEL_ENABLE);
++ unsigned int c = tw_read(dev, R32_DMA_CMD);
++
++ return (c & BIT(31)) && (c & e & BIT_ID(id));
++}
++
++static inline unsigned int tw_id_is_off(struct tw6869_dev *dev,
++ unsigned int id)
++{
++ unsigned int e = tw_read(dev, R32_DMA_CHANNEL_ENABLE);
++ unsigned int c = tw_read(dev, R32_DMA_CMD);
++
++ return !((c | e) & BIT_ID(id));
++}
++
++static inline void tw_id_on(struct tw6869_dev *dev, unsigned int id)
++{
++ int c = 3;
++
++ while (!tw_id_is_on(dev, id) && c--) {
++ tw_set(dev, R32_DMA_CMD, BIT(31) | BIT_ID(id));
++ tw_set(dev, R32_DMA_CHANNEL_ENABLE, BIT_ID(id));
++ }
++}
++
++static inline void tw_id_off(struct tw6869_dev *dev, unsigned int id)
++{
++ int c = 3;
++
++ while (!tw_id_is_off(dev, id) && c--) {
++ tw_clear(dev, R32_DMA_CMD, BIT_ID(id));
++ tw_clear(dev, R32_DMA_CHANNEL_ENABLE, BIT_ID(id));
++ }
++
++ if (!tw_read(dev, R32_DMA_CHANNEL_ENABLE))
++ tw_write(dev, R32_DMA_CMD, 0);
++}
++
++static void tw6869_id_dma_cmd(struct tw6869_dev *dev,
++ unsigned int id,
++ unsigned int cmd)
++{
++ switch (cmd) {
++ case TW_DMA_ON:
++ dev->id_err[ID2ID(id)] = 0;
++ tw_id_on(dev, id);
++ dev_info(&dev->pdev->dev, "DMA %u ON\n", id);
++ break;
++ case TW_DMA_OFF:
++ tw_id_off(dev, id);
++ dev_info(&dev->pdev->dev, "DMA %u OFF\n", id);
++ break;
++ case TW_DMA_RST:
++ if (tw_id_is_on(dev, id)) {
++ tw_id_off(dev, id);
++ if (++dev->id_err[ID2ID(id)] > TW_DMA_ERR_MAX) {
++ dev_err(&dev->pdev->dev, "DMA %u forced OFF\n", id);
++ break;
++ }
++ tw_id_on(dev, id);
++ dev_info(&dev->pdev->dev, "DMA %u RST\n", id);
++ } else {
++ dev_info(&dev->pdev->dev, "DMA %u spurious RST\n", id);
++ }
++ break;
++ default:
++ dev_err(&dev->pdev->dev, "DMA %u unknown cmd %u\n", id, cmd);
++ }
++}
++
++static unsigned int tw6869_virq(struct tw6869_dev *dev,
++ unsigned int id,
++ unsigned int pb,
++ unsigned int err)
++{
++ struct tw6869_vch *vch = &dev->vch[ID2CH(id)];
++ struct tw6869_buf *done = NULL;
++ struct tw6869_buf *next = NULL;
++
++ spin_lock(&vch->lock);
++ if (!vb2_is_streaming(&vch->queue) || !vch->p_buf || !vch->b_buf) {
++ spin_unlock(&vch->lock);
++ return TW_DMA_OFF;
++ }
++
++ if (err || (vch->pb != pb)) {
++ vch->pb = 0;
++ spin_unlock(&vch->lock);
++ return TW_DMA_RST;
++ }
++
++ if (!list_empty(&vch->buf_list)) {
++ next = list_first_entry(&vch->buf_list, struct tw6869_buf, list);
++ list_del(&next->list);
++ if (pb) {
++ done = vch->b_buf;
++ vch->b_buf = next;
++ } else {
++ done = vch->p_buf;
++ vch->p_buf = next;
++ }
++ }
++ vch->pb = !pb;
++ spin_unlock(&vch->lock);
++
++ if (done && next) {
++ tw_write(dev, pb ? R32_DMA_B_ADDR(id) : R32_DMA_P_ADDR(id), next->dma);
++ v4l2_get_timestamp(&done->vb.v4l2_buf.timestamp);
++ done->vb.v4l2_buf.sequence = vch->sequence++;
++ vb2_buffer_done(&done->vb, VB2_BUF_STATE_DONE);
++ } else {
++ dev_info(&dev->pdev->dev, "vch%u NOBUF seq=%u dcount=%u\n",
++ ID2CH(id), vch->sequence, ++vch->dcount);
++ }
++ return 0;
++}
++
++static unsigned int tw6869_airq(struct tw6869_dev *dev,
++ unsigned int id,
++ unsigned int pb)
++{
++ struct tw6869_ach *ach = &dev->ach[ID2CH(id)];
++ struct tw6869_buf *done = NULL;
++ struct tw6869_buf *next = NULL;
++
++ spin_lock(&ach->lock);
++ if (!ach->ss || !ach->p_buf || !ach->b_buf) {
++ spin_unlock(&ach->lock);
++ return TW_DMA_OFF;
++ }
++
++ if (ach->pb != pb) {
++ ach->pb = 0;
++ spin_unlock(&ach->lock);
++ return TW_DMA_RST;
++ }
++
++ if (!list_empty(&ach->buf_list)) {
++ next = list_first_entry(&ach->buf_list, struct tw6869_buf, list);
++ list_move_tail(&next->list, &ach->buf_list);
++ if (pb) {
++ done = ach->p_buf;
++ ach->b_buf = next;
++ } else {
++ done = ach->b_buf;
++ ach->p_buf = next;
++ }
++ }
++ ach->pb = !pb;
++ spin_unlock(&ach->lock);
++
++ if (done && next) {
++ tw_write(dev, pb ? R32_DMA_B_ADDR(id) : R32_DMA_P_ADDR(id), next->dma);
++ ach->ptr = done->dma - ach->buf[0].dma;
++ snd_pcm_period_elapsed(ach->ss);
++ } else {
++ return TW_DMA_OFF;
++ }
++ return 0;
++}
++
++static irqreturn_t tw6869_irq(int irq, void *dev_id)
++{
++ struct tw6869_dev *dev = dev_id;
++ unsigned int int_sts, fifo_sts, pb_sts, dma_en, id;
++
++ int_sts = tw_read(dev, R32_INT_STATUS);
++ fifo_sts = tw_read(dev, R32_FIFO_STATUS);
++ pb_sts = tw_read(dev, R32_PB_STATUS);
++ dma_en = tw_read(dev, R32_DMA_CHANNEL_ENABLE);
++ dma_en &= tw_read(dev, R32_DMA_CMD);
++
++ for (id = 0; id < (2 * TW_CH_MAX); id++) {
++ unsigned int verr = fifo_sts & TW_VERR(id);
++
++ if ((dma_en & BIT(id)) && ((int_sts & BIT(id)) || verr)) {
++ unsigned int pb = !!(pb_sts & BIT(id));
++ unsigned int cmd = (BIT(id) & TW_VID) ?
++ tw6869_virq(dev, id, pb, verr) :
++ tw6869_airq(dev, id, pb);
++
++ if (cmd) {
++ spin_lock(&dev->rlock);
++ tw6869_id_dma_cmd(dev, id, cmd);
++ spin_unlock(&dev->rlock);
++ } else {
++ dev->id_err[id] = 0;
++ }
++ }
++ }
++ return IRQ_HANDLED;
++}
++
++/**********************************************************************/
++
++static inline struct tw6869_buf *to_tw6869_buf(struct vb2_buffer *vb2)
++{
++ return container_of(vb2, struct tw6869_buf, vb);
++}
++
++static int to_tw6869_pixformat(unsigned int pixelformat)
++{
++ int ret;
++
++ switch (pixelformat) {
++ case V4L2_PIX_FMT_YUYV:
++ ret = TW_FMT_YUYV;
++ break;
++ case V4L2_PIX_FMT_UYVY:
++ ret = TW_FMT_UYVY;
++ break;
++ case V4L2_PIX_FMT_RGB565:
++ ret = TW_FMT_RGB565;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static unsigned int tw6869_fields_map(v4l2_std_id std, unsigned int rate)
++{
++ unsigned int map[15] = {
++ 0x00000000, 0x00000001, 0x00004001, 0x00104001, 0x00404041,
++ 0x01041041, 0x01104411, 0x01111111, 0x04444445, 0x04511445,
++ 0x05145145, 0x05151515, 0x05515455, 0x05551555, 0x05555555
++ };
++ unsigned int std_625_50[26] = {
++ 0, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7,
++ 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 0
++ };
++ unsigned int std_525_60[31] = {
++ 0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
++ 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 0, 0
++ };
++ unsigned int i = (std & V4L2_STD_625_50) ?
++ std_625_50[(rate > 25) ? 25 : rate] :
++ std_525_60[(rate > 30) ? 30 : rate];
++
++ return map[i];
++}
++
++static void tw6869_fill_pix_format(struct tw6869_vch *vch,
++ struct v4l2_pix_format *pix)
++{
++ pix->width = 720;
++ pix->height = (vch->std & V4L2_STD_625_50) ? 576 : 480;
++ pix->field = V4L2_FIELD_INTERLACED_BT;
++ pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
++ pix->bytesperline = pix->width * 2;
++ pix->sizeimage = pix->bytesperline * pix->height;
++ pix->priv = 0;
++}
++
++static void tw6869_vch_hw_cfg(struct tw6869_vch *vch)
++{
++ struct tw6869_dev *dev = vch->dev;
++ struct v4l2_pix_format *pix = &vch->format;
++ unsigned int cfg;
++
++ if (vch->std & V4L2_STD_625_50)
++ tw_set(dev, R32_VIDEO_CONTROL1, BIT_CH(vch->id) << 13);
++ else
++ tw_clear(dev, R32_VIDEO_CONTROL1, BIT_CH(vch->id) << 13);
++
++ cfg = tw6869_fields_map(vch->std, vch->fps) << 1;
++ cfg |= cfg << 1;
++ if (cfg > 0)
++ cfg |= BIT(31);
++ tw_write(dev, R32_VIDEO_FIELD_CTRL(vch->id), cfg);
++
++ /* Analog mux input0, no drop, enable master */
++ cfg = ((vch->input & 0x0) << 30) |
++ BIT(27) | (ID2SC(vch->id) << 25) |
++ ((to_tw6869_pixformat(pix->pixelformat) & 0x7) << 20);
++ tw_write(dev, R32_DMA_CHANNEL_CONFIG(vch->id), cfg);
++
++ cfg = (((pix->height >> 1) & 0x3FF) << 22) |
++ ((pix->bytesperline & 0x7FF) << 11) |
++ (pix->bytesperline & 0x7FF);
++ tw_write(dev, R32_DMA_WHP(vch->id), cfg);
++
++ tw_write(dev, R32_DMA_P_ADDR(vch->id), vch->p_buf->dma);
++ tw_write(dev, R32_DMA_B_ADDR(vch->id), vch->b_buf->dma);
++}
++
++/*
++ * Videobuf2 Operations
++ */
++static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
++ unsigned int *nbuffers, unsigned int *nplanes,
++ unsigned int sizes[], void *alloc_ctxs[])
++{
++ struct tw6869_vch *vch = vb2_get_drv_priv(vq);
++ struct tw6869_dev *dev = vch->dev;
++
++ if (vq->num_buffers + *nbuffers < TW_FRAME_MAX)
++ *nbuffers = TW_FRAME_MAX - vq->num_buffers;
++
++ if (fmt && fmt->fmt.pix.sizeimage < vch->format.sizeimage)
++ return -EINVAL;
++
++ *nplanes = 1;
++ sizes[0] = fmt ? fmt->fmt.pix.sizeimage : vch->format.sizeimage;
++ alloc_ctxs[0] = dev->alloc_ctx;
++ return 0;
++}
++
++static int buffer_init(struct vb2_buffer *vb)
++{
++ struct tw6869_buf *buf = to_tw6869_buf(vb);
++
++ buf->dma = vb2_dma_contig_plane_dma_addr(vb, 0);
++ INIT_LIST_HEAD(&buf->list);
++ { /* pass the buffer physical address */
++ unsigned int *cpu = vb2_plane_vaddr(vb, 0);
++ *cpu = buf->dma;
++ }
++ return 0;
++}
++
++static int buffer_prepare(struct vb2_buffer *vb)
++{
++ struct tw6869_vch *vch = vb2_get_drv_priv(vb->vb2_queue);
++ unsigned long size = vch->format.sizeimage;
++
++ if (vb2_plane_size(vb, 0) < size) {
++ v4l2_err(&vch->dev->v4l2_dev, "buffer too small (%lu < %lu)\n",
++ vb2_plane_size(vb, 0), size);
++ return -EINVAL;
++ }
++
++ vb2_set_plane_payload(vb, 0, size);
++ return 0;
++}
++
++static void buffer_queue(struct vb2_buffer *vb)
++{
++ struct tw6869_vch *vch = vb2_get_drv_priv(vb->vb2_queue);
++ struct tw6869_buf *buf = to_tw6869_buf(vb);
++ unsigned long flags;
++
++ spin_lock_irqsave(&vch->lock, flags);
++ list_add_tail(&buf->list, &vch->buf_list);
++ spin_unlock_irqrestore(&vch->lock, flags);
++}
++
++static int start_streaming(struct vb2_queue *vq, unsigned int count)
++{
++ struct tw6869_vch *vch = vb2_get_drv_priv(vq);
++ struct tw6869_dev *dev = vch->dev;
++ unsigned long flags;
++
++ if (count < 2)
++ return -ENOBUFS;
++
++ spin_lock_irqsave(&vch->lock, flags);
++ vch->p_buf = list_first_entry(&vch->buf_list, struct tw6869_buf, list);
++ list_del(&vch->p_buf->list);
++
++ vch->b_buf = list_first_entry(&vch->buf_list, struct tw6869_buf, list);
++ list_del(&vch->b_buf->list);
++
++ vch->sequence = 0;
++ vch->dcount = 0;
++ vch->pb = 0;
++ spin_unlock_irqrestore(&vch->lock, flags);
++
++ spin_lock_irqsave(&dev->rlock, flags);
++ tw6869_vch_hw_cfg(vch);
++ tw6869_id_dma_cmd(dev, vch->id, TW_DMA_ON);
++ spin_unlock_irqrestore(&dev->rlock, flags);
++
++ return 0;
++}
++
++static int stop_streaming(struct vb2_queue *vq)
++{
++ struct tw6869_vch *vch = vb2_get_drv_priv(vq);
++ struct tw6869_dev *dev = vch->dev;
++ struct tw6869_buf *buf, *node;
++ unsigned long flags;
++
++ spin_lock_irqsave(&dev->rlock, flags);
++ tw6869_id_dma_cmd(dev, vch->id, TW_DMA_OFF);
++ spin_unlock_irqrestore(&dev->rlock, flags);
++
++ spin_lock_irqsave(&vch->lock, flags);
++ if (vch->p_buf) {
++ buf = vch->p_buf;
++ vch->p_buf = NULL;
++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
++ }
++
++ if (vch->b_buf) {
++ buf = vch->b_buf;
++ vch->b_buf = NULL;
++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
++ }
++
++ list_for_each_entry_safe(buf, node, &vch->buf_list, list) {
++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
++ list_del(&buf->list);
++ }
++ spin_unlock_irqrestore(&vch->lock, flags);
++
++ return 0;
++}
++
++static struct vb2_ops tw6869_qops = {
++ .queue_setup = queue_setup,
++ .buf_init = buffer_init,
++ .buf_prepare = buffer_prepare,
++ .buf_queue = buffer_queue,
++ .start_streaming = start_streaming,
++ .stop_streaming = stop_streaming,
++ .wait_prepare = vb2_ops_wait_prepare,
++ .wait_finish = vb2_ops_wait_finish,
++};
++
++static int tw6869_querycap(struct file *file, void *priv,
++ struct v4l2_capability *cap)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ struct tw6869_dev *dev = vch->dev;
++
++ strlcpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
++ snprintf(cap->card, sizeof(cap->card), "tw6869 vch%u", ID2CH(vch->id));
++ snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s",
++ pci_name(dev->pdev));
++ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
++ V4L2_CAP_STREAMING;
++ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
++ return 0;
++}
++
++static int tw6869_try_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ struct v4l2_pix_format *pix = &f->fmt.pix;
++ int ret;
++
++ ret = to_tw6869_pixformat(pix->pixelformat);
++ if (ret < 0)
++ return ret;
++
++ tw6869_fill_pix_format(vch, pix);
++ return 0;
++}
++
++static int tw6869_s_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ int ret;
++
++ ret = tw6869_try_fmt_vid_cap(file, priv, f);
++ if (ret)
++ return ret;
++
++ if (vb2_is_busy(&vch->queue))
++ return -EBUSY;
++
++ vch->format = f->fmt.pix;
++ return 0;
++}
++
++static int tw6869_g_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++
++ f->fmt.pix = vch->format;
++ return 0;
++}
++
++static int tw6869_enum_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_fmtdesc *f)
++{
++ if (f->index > 2)
++ return -EINVAL;
++
++ switch (f->index) {
++ case 1:
++ strcpy(f->description, "4:2:2, packed, YUYV");
++ f->pixelformat = V4L2_PIX_FMT_YUYV;
++ break;
++ case 2:
++ strcpy(f->description, "16 bpp RGB, le");
++ f->pixelformat = V4L2_PIX_FMT_RGB565;
++ break;
++ default:
++ strcpy(f->description, "4:2:2, packed, UYVY");
++ f->pixelformat = V4L2_PIX_FMT_UYVY;
++ }
++ f->flags = 0;
++ return 0;
++}
++
++static int tw6869_enum_framesizes(struct file *file, void *priv,
++ struct v4l2_frmsizeenum *fsize)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++
++ if (fsize->index != 0)
++ return -EINVAL;
++
++ fsize->discrete.width = vch->format.width;
++ fsize->discrete.height = vch->format.height;
++
++ return 0;
++}
++
++static int tw6869_querystd(struct file *file, void *priv, v4l2_std_id *std)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ struct tw6869_dev *dev = vch->dev;
++ unsigned int std_now;
++ char *std_str;
++
++ std_now = (tw_read(dev, R8_STANDARD_SEL(vch->id)) & 0x70) >> 4;
++
++ switch (std_now) {
++ case TW_STD_PAL_M:
++ std_str = "PAL (M)";
++ *std = V4L2_STD_525_60;
++ break;
++ case TW_STD_PAL_60:
++ std_str = "PAL 60";
++ *std = V4L2_STD_525_60;
++ break;
++ case TW_STD_NTSC_M:
++ std_str = "NTSC (M)";
++ *std = V4L2_STD_525_60;
++ break;
++ case TW_STD_NTSC_443:
++ std_str = "NTSC 4.43";
++ *std = V4L2_STD_525_60;
++ break;
++ case TW_STD_PAL:
++ std_str = "PAL (B,D,G,H,I)";
++ *std = V4L2_STD_625_50;
++ break;
++ case TW_STD_PAL_CN:
++ std_str = "PAL (CN)";
++ *std = V4L2_STD_625_50;
++ break;
++ case TW_STD_SECAM:
++ std_str = "SECAM";
++ *std = V4L2_STD_625_50;
++ break;
++ default:
++ std_str = "Not valid";
++ *std = 0;
++ }
++ v4l2_info(&dev->v4l2_dev, "vch%u std %s\n", ID2CH(vch->id), std_str);
++ return 0;
++}
++
++static int tw6869_s_std(struct file *file, void *priv, v4l2_std_id std)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ v4l2_std_id new_std = (std & V4L2_STD_625_50) ?
++ V4L2_STD_625_50 : V4L2_STD_525_60;
++
++ if (new_std == vch->std)
++ return 0;
++
++ if (vb2_is_busy(&vch->queue))
++ return -EBUSY;
++
++ vch->std = new_std;
++ vch->fps = (new_std & V4L2_STD_625_50) ? 25 : 30;
++ tw6869_fill_pix_format(vch, &vch->format);
++ return 0;
++}
++
++static int tw6869_g_std(struct file *file, void *priv, v4l2_std_id *std)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ v4l2_std_id new_std = 0;
++
++ tw6869_querystd(file, priv, &new_std);
++ if (new_std)
++ tw6869_s_std(file, priv, new_std);
++
++ vch->fps = (vch->std & V4L2_STD_625_50) ? 25 : 30;
++ *std = vch->std;
++ return 0;
++}
++
++/* SK-TW6869: only input0 is available */
++static int tw6869_enum_input(struct file *file, void *priv,
++ struct v4l2_input *i)
++{
++ if (i->index >= TW_VIN_MAX)
++ return -EINVAL;
++
++ i->type = V4L2_INPUT_TYPE_CAMERA;
++ i->std = V4L2_STD_ALL;
++ sprintf(i->name, "Camera %d", i->index);
++ return 0;
++}
++
++static int tw6869_s_input(struct file *file, void *priv, unsigned int i)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++
++ vch->input = i;
++ return 0;
++}
++
++static int tw6869_g_input(struct file *file, void *priv, unsigned int *i)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++
++ *i = vch->input;
++ return 0;
++}
++
++static int tw6869_g_parm(struct file *file, void *priv,
++ struct v4l2_streamparm *sp)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ struct v4l2_captureparm *cp = &sp->parm.capture;
++
++ cp->capability = V4L2_CAP_TIMEPERFRAME;
++ cp->timeperframe.numerator = 1;
++ cp->timeperframe.denominator = vch->fps;
++ return 0;
++}
++
++static int tw6869_s_parm(struct file *file, void *priv,
++ struct v4l2_streamparm *sp)
++{
++ struct tw6869_vch *vch = video_drvdata(file);
++ unsigned int denominator = sp->parm.capture.timeperframe.denominator;
++ unsigned int numerator = sp->parm.capture.timeperframe.numerator;
++ unsigned int fps;
++
++ fps = (!numerator || !denominator) ? 0 : denominator / numerator;
++ if (vch->std & V4L2_STD_625_50)
++ fps = (!fps || fps > 25) ? 25 : fps;
++ else
++ fps = (!fps || fps > 30) ? 30 : fps;
++
++ vch->fps = fps;
++ v4l2_info(&vch->dev->v4l2_dev,
++ "vch%u fps %u\n", ID2CH(vch->id), vch->fps);
++
++ return tw6869_g_parm(file, priv, sp);
++}
++
++/* The control handler */
++static int tw6869_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++ struct tw6869_vch *vch =
++ container_of(ctrl->handler, struct tw6869_vch, hdl);
++ struct tw6869_dev *dev = vch->dev;
++ unsigned int id = vch->id;
++ int ret = 0;
++
++ switch (ctrl->id) {
++ case V4L2_CID_BRIGHTNESS:
++ tw_write(dev, R8_BRIGHT_CTRL(id), ctrl->val);
++ break;
++ case V4L2_CID_CONTRAST:
++ tw_write(dev, R8_CONTRAST_CTRL(id), ctrl->val);
++ break;
++ case V4L2_CID_SATURATION:
++ tw_write(dev, R8_SAT_U_CTRL(id), ctrl->val);
++ tw_write(dev, R8_SAT_V_CTRL(id), ctrl->val);
++ break;
++ case V4L2_CID_HUE:
++ tw_write(dev, R8_HUE_CTRL(id), ctrl->val);
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++/*
++ * File operations for the device
++ */
++static const struct v4l2_ctrl_ops tw6869_ctrl_ops = {
++ .s_ctrl = tw6869_s_ctrl,
++};
++
++static const struct v4l2_ioctl_ops tw6869_ioctl_ops = {
++ .vidioc_querycap = tw6869_querycap,
++ .vidioc_try_fmt_vid_cap = tw6869_try_fmt_vid_cap,
++ .vidioc_s_fmt_vid_cap = tw6869_s_fmt_vid_cap,
++ .vidioc_g_fmt_vid_cap = tw6869_g_fmt_vid_cap,
++ .vidioc_enum_fmt_vid_cap = tw6869_enum_fmt_vid_cap,
++ .vidioc_enum_framesizes = tw6869_enum_framesizes,
++
++ .vidioc_querystd = tw6869_querystd,
++ .vidioc_s_std = tw6869_s_std,
++ .vidioc_g_std = tw6869_g_std,
++
++ .vidioc_enum_input = tw6869_enum_input,
++ .vidioc_s_input = tw6869_s_input,
++ .vidioc_g_input = tw6869_g_input,
++
++ .vidioc_g_parm = tw6869_g_parm,
++ .vidioc_s_parm = tw6869_s_parm,
++
++ .vidioc_reqbufs = vb2_ioctl_reqbufs,
++ .vidioc_create_bufs = vb2_ioctl_create_bufs,
++ .vidioc_querybuf = vb2_ioctl_querybuf,
++ .vidioc_qbuf = vb2_ioctl_qbuf,
++ .vidioc_dqbuf = vb2_ioctl_dqbuf,
++ .vidioc_expbuf = vb2_ioctl_expbuf,
++ .vidioc_streamon = vb2_ioctl_streamon,
++ .vidioc_streamoff = vb2_ioctl_streamoff,
++
++ .vidioc_log_status = v4l2_ctrl_log_status,
++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
++};
++
++static const struct v4l2_file_operations tw6869_fops = {
++ .owner = THIS_MODULE,
++ .open = v4l2_fh_open,
++ .release = vb2_fop_release,
++ .unlocked_ioctl = video_ioctl2,
++ .read = vb2_fop_read,
++ .mmap = vb2_fop_mmap,
++ .poll = vb2_fop_poll,
++};
++
++static int tw6869_vch_register(struct tw6869_vch *vch)
++{
++ struct tw6869_dev *dev = vch->dev;
++ struct v4l2_ctrl_handler *hdl = &vch->hdl;
++ struct vb2_queue *q = &vch->queue;
++ struct video_device *vdev = &vch->vdev;
++ int ret = 0;
++
++ /* Add the controls */
++ v4l2_ctrl_handler_init(hdl, 4);
++ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops,
++ V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
++ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops,
++ V4L2_CID_CONTRAST, 0, 255, 1, 100);
++ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops,
++ V4L2_CID_SATURATION, 0, 255, 1, 128);
++ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops,
++ V4L2_CID_HUE, -128, 127, 1, 0);
++ if (hdl->error) {
++ ret = hdl->error;
++ return ret;
++ }
++
++ /* Fill in the initial format-related settings */
++ vch->std = V4L2_STD_525_60;
++ vch->fps = 30;
++ vch->format.pixelformat = V4L2_PIX_FMT_UYVY;
++ tw6869_fill_pix_format(vch, &vch->format);
++
++ mutex_init(&vch->mlock);
++
++ /* Initialize the vb2 queue */
++ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
++ q->drv_priv = vch;
++ q->buf_struct_size = sizeof(struct tw6869_buf);
++ q->ops = &tw6869_qops;
++ q->mem_ops = &vb2_dma_contig_memops;
++ q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++ q->lock = &vch->mlock;
++ q->gfp_flags = __GFP_DMA32;
++ ret = vb2_queue_init(q);
++ if (ret)
++ goto free_hdl;
++
++ spin_lock_init(&vch->lock);
++ INIT_LIST_HEAD(&vch->buf_list);
++
++ /* Initialize the video_device structure */
++ strlcpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
++ vdev->release = video_device_release_empty;
++ vdev->fops = &tw6869_fops,
++ vdev->ioctl_ops = &tw6869_ioctl_ops,
++ vdev->lock = &vch->mlock;
++ vdev->queue = q;
++ vdev->v4l2_dev = &dev->v4l2_dev;
++ vdev->ctrl_handler = hdl;
++ vdev->tvnorms = V4L2_STD_ALL;
++ video_set_drvdata(vdev, vch);
++ ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
++ if (!ret)
++ return 0;
++
++free_hdl:
++ v4l2_ctrl_handler_free(hdl);
++ return ret;
++}
++
++static void tw6869_video_unregister(struct tw6869_dev *dev)
++{
++ unsigned int i;
++
++ /* Reset and disable all DMA channels */
++ tw_write(dev, R32_DMA_CMD, 0);
++ tw_write(dev, R32_DMA_CHANNEL_ENABLE, 0);
++
++ if (!dev->alloc_ctx)
++ return;
++
++ if (dev->ch_max > TW_CH_MAX)
++ dev->ch_max = TW_CH_MAX;
++
++ for (i = 0; i < dev->ch_max; i++) {
++ struct tw6869_vch *vch = &dev->vch[ID2CH(i)];
++ video_unregister_device(&vch->vdev);
++ v4l2_ctrl_handler_free(&vch->hdl);
++ }
++
++ v4l2_device_unregister(&dev->v4l2_dev);
++ vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
++ dev->alloc_ctx = NULL;
++}
++
++static int tw6869_video_register(struct tw6869_dev *dev)
++{
++ struct pci_dev *pdev = dev->pdev;
++ unsigned int i;
++ int ret;
++
++ /* Initialize the top-level structure */
++ ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
++ if (ret)
++ return ret;
++
++ dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
++ if (IS_ERR(dev->alloc_ctx)) {
++ ret = PTR_ERR(dev->alloc_ctx);
++ v4l2_err(&dev->v4l2_dev, "can't allocate buffer context\n");
++ v4l2_device_unregister(&dev->v4l2_dev);
++ dev->alloc_ctx = NULL;
++ return ret;
++ }
++
++ for (i = 0; i < TW_CH_MAX; i++) {
++ struct tw6869_vch *vch = &dev->vch[ID2CH(i)];
++ vch->dev = dev;
++ vch->id = i;
++ ret = tw6869_vch_register(vch);
++ if (ret) {
++ dev->ch_max = i;
++ tw6869_video_unregister(dev);
++ return ret;
++ }
++ dev_info(&pdev->dev, "vch%i registered as %s\n",
++ vch->id,
++ video_device_node_name(&vch->vdev));
++ }
++ return 0;
++}
++
++/**********************************************************************/
++
++static int tw6869_pcm_hw_params(struct snd_pcm_substream *ss,
++ struct snd_pcm_hw_params *hw_params)
++{
++ return snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(hw_params));
++}
++
++static int tw6869_pcm_hw_free(struct snd_pcm_substream *ss)
++{
++ return snd_pcm_lib_free_pages(ss);
++}
++
++static const struct snd_pcm_hardware tw6869_capture_hw = {
++ .info = (SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP_VALID),
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ .rates = SNDRV_PCM_RATE_48000,
++ .rate_min = 48000,
++ .rate_max = 48000,
++ .channels_min = 1,
++ .channels_max = 1,
++ .buffer_bytes_max = TW_PAGE_SIZE * TW_APAGE_MAX,
++ .period_bytes_min = TW_PAGE_SIZE,
++ .period_bytes_max = TW_PAGE_SIZE,
++ .periods_min = 2,
++ .periods_max = TW_APAGE_MAX,
++};
++
++static int tw6869_pcm_open(struct snd_pcm_substream *ss)
++{
++ struct tw6869_dev *dev = snd_pcm_substream_chip(ss);
++ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)];
++ struct snd_pcm_runtime *rt = ss->runtime;
++ int ret;
++
++ rt->hw = tw6869_capture_hw;
++ ret = snd_pcm_hw_constraint_integer(rt, SNDRV_PCM_HW_PARAM_PERIODS);
++ if (ret < 0)
++ return ret;
++
++ ach->ss = ss;
++ return 0;
++}
++
++static int tw6869_pcm_close(struct snd_pcm_substream *ss)
++{
++ struct tw6869_dev *dev = snd_pcm_substream_chip(ss);
++ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)];
++
++ ach->ss = NULL;
++ return 0;
++}
++
++static int tw6869_pcm_prepare(struct snd_pcm_substream *ss)
++{
++ struct tw6869_dev *dev = snd_pcm_substream_chip(ss);
++ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)];
++ struct snd_pcm_runtime *rt = ss->runtime;
++ unsigned int period = snd_pcm_lib_period_bytes(ss);
++ unsigned long flags;
++ unsigned int i;
++
++ spin_lock_irqsave(&ach->lock, flags);
++ ach->p_buf = NULL;
++ ach->b_buf = NULL;
++
++ if ((period != TW_PAGE_SIZE) ||
++ (rt->periods < 2) ||
++ (rt->periods > TW_APAGE_MAX)) {
++ spin_unlock_irqrestore(&ach->lock, flags);
++ return -EINVAL;
++ }
++
++ INIT_LIST_HEAD(&ach->buf_list);
++ for (i = 0; i < rt->periods; i++) {
++ ach->buf[i].dma = rt->dma_addr + period * i;
++ INIT_LIST_HEAD(&ach->buf[i].list);
++ list_add_tail(&ach->buf[i].list, &ach->buf_list);
++ }
++
++ ach->p_buf = list_first_entry(&ach->buf_list, struct tw6869_buf, list);
++ list_move_tail(&ach->p_buf->list, &ach->buf_list);
++
++ ach->b_buf = list_first_entry(&ach->buf_list, struct tw6869_buf, list);
++ list_move_tail(&ach->b_buf->list, &ach->buf_list);
++
++ ach->ptr = 0;
++ ach->pb = 0;
++ spin_unlock_irqrestore(&ach->lock, flags);
++
++ return 0;
++}
++
++static void tw6869_ach_hw_cfg(struct tw6869_ach *ach)
++{
++ struct tw6869_dev *dev = ach->dev;
++
++ tw_write(dev, R32_DMA_P_ADDR(ach->id), ach->p_buf->dma);
++ tw_write(dev, R32_DMA_B_ADDR(ach->id), ach->b_buf->dma);
++}
++
++static int tw6869_pcm_trigger(struct snd_pcm_substream *ss, int cmd)
++{
++ struct tw6869_dev *dev = snd_pcm_substream_chip(ss);
++ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)];
++ unsigned long flags;
++ int ret = 0;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ if (ach->p_buf && ach->b_buf) {
++ spin_lock_irqsave(&dev->rlock, flags);
++ tw6869_ach_hw_cfg(ach);
++ tw6869_id_dma_cmd(dev, ach->id, TW_DMA_ON);
++ spin_unlock_irqrestore(&dev->rlock, flags);
++ } else {
++ ret = -EIO;
++ }
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ spin_lock_irqsave(&dev->rlock, flags);
++ tw6869_id_dma_cmd(dev, ach->id, TW_DMA_OFF);
++ spin_unlock_irqrestore(&dev->rlock, flags);
++
++ spin_lock_irqsave(&ach->lock, flags);
++ ach->p_buf = NULL;
++ ach->b_buf = NULL;
++ spin_unlock_irqrestore(&ach->lock, flags);
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static snd_pcm_uframes_t tw6869_pcm_pointer(struct snd_pcm_substream *ss)
++{
++ struct tw6869_dev *dev = snd_pcm_substream_chip(ss);
++ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)];
++
++ return bytes_to_frames(ss->runtime, ach->ptr);
++}
++
++static struct snd_pcm_ops tw6869_pcm_ops = {
++ .open = tw6869_pcm_open,
++ .close = tw6869_pcm_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = tw6869_pcm_hw_params,
++ .hw_free = tw6869_pcm_hw_free,
++ .prepare = tw6869_pcm_prepare,
++ .trigger = tw6869_pcm_trigger,
++ .pointer = tw6869_pcm_pointer,
++};
++
++static int tw6869_snd_pcm_init(struct tw6869_dev *dev)
++{
++ struct snd_card *card = dev->snd_card;
++ struct snd_pcm *pcm;
++ struct snd_pcm_substream *ss;
++ int ret;
++
++ ret = snd_pcm_new(card, card->driver, 0, 0, TW_CH_MAX, &pcm);
++ if (ret < 0)
++ return ret;
++
++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &tw6869_pcm_ops);
++ snd_pcm_chip(pcm) = dev;
++ pcm->info_flags = 0;
++ strcpy(pcm->name, card->shortname);
++
++ ss = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
++ while (ss && (ss->next != ss)) {
++ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)];
++ ach->dev = dev;
++ ach->id = ID2CH(ss->number) + TW_CH_MAX;
++ spin_lock_init(&ach->lock);
++ sprintf(ss->name, "vch%u audio", ID2CH(ss->number));
++ ss = ss->next;
++ }
++
++ return snd_pcm_lib_preallocate_pages_for_all(pcm,
++ SNDRV_DMA_TYPE_DEV,
++ snd_dma_pci_data(dev->pdev),
++ TW_APAGE_MAX * TW_PAGE_SIZE,
++ TW_APAGE_MAX * TW_PAGE_SIZE);
++}
++
++static void tw6869_audio_unregister(struct tw6869_dev *dev)
++{
++ /* Reset and disable audio DMA */
++ tw_clear(dev, R32_DMA_CMD, TW_AID);
++ tw_clear(dev, R32_DMA_CHANNEL_ENABLE, TW_AID);
++
++ if (!dev->snd_card)
++ return;
++
++ snd_card_free(dev->snd_card);
++ dev->snd_card = NULL;
++}
++
++/* TODO: mixer controls */
++static int tw6869_audio_register(struct tw6869_dev *dev)
++{
++ struct pci_dev *pdev = dev->pdev;
++ static struct snd_device_ops ops = { NULL };
++ struct snd_card *card;
++ int ret;
++
++ ret = snd_card_create(SNDRV_DEFAULT_IDX1, KBUILD_MODNAME,
++ THIS_MODULE, 0, &card);
++ if (ret < 0)
++ return ret;
++
++ dev->snd_card = card;
++
++ strcpy(card->driver, KBUILD_MODNAME);
++ strcpy(card->shortname, KBUILD_MODNAME);
++ sprintf(card->longname, "%s on %s IRQ %d", card->shortname,
++ pci_name(pdev), pdev->irq);
++
++ ret = snd_device_new(card, SNDRV_DEV_LOWLEVEL, dev, &ops);
++ if (ret < 0)
++ goto snd_error;
++
++ snd_card_set_dev(card, &pdev->dev);
++
++ ret = tw6869_snd_pcm_init(dev);
++ if (ret < 0)
++ goto snd_error;
++
++ ret = snd_card_register(card);
++ if (!ret)
++ return 0;
++
++snd_error:
++ snd_card_free(card);
++ dev->snd_card = NULL;
++ return ret;
++}
++
++/**********************************************************************/
++
++static void tw6869_reset(struct tw6869_dev *dev)
++{
++ /* Software Reset */
++ tw_write(dev, R32_SYS_SOFT_RST, 0x01);
++ tw_write(dev, R32_SYS_SOFT_RST, 0x0F);
++
++ /* Reset Internal audio and video decoders */
++ tw_write(dev, R8_AVSRST(0), 0x1F);
++ tw_write(dev, R8_AVSRST(4), 0x1F);
++
++ /* Reset all DMA channels */
++ tw_write(dev, R32_DMA_CMD, 0);
++
++ /* Disable all DMA channels */
++ tw_write(dev, R32_DMA_CHANNEL_ENABLE, 0);
++
++ /* Enable DMA FIFO overflow and pointer check */
++ tw_write(dev, R32_DMA_CONFIG, 0x00FFFF04);
++
++ /* Minimum time span for DMA interrupting host (default: 0x00098968) */
++ tw_write(dev, R32_DMA_TIMER_INTERVAL, 0x00098968);
++
++ /* DMA timeout (default: 0x140C8584) */
++ tw_write(dev, R32_DMA_CHANNEL_TIMEOUT, 0x140C8584);
++
++ /* Frame mode DMA */
++ tw_write(dev, R32_PHASE_REF, 0xAAAA144D);
++
++ /* Show blue background if no signal */
++ tw_write(dev, R8_MISC_CONTROL1(0), 0xE7);
++ tw_write(dev, R8_MISC_CONTROL1(4), 0xE7);
++
++ /* Audio DMA 4096 bytes, sampling frequency reference 48 kHz */
++ tw_write(dev, R32_AUDIO_CONTROL1, 0x80000001 | (0x0A2C << 5));
++ tw_write(dev, R32_AUDIO_CONTROL2, 0x0A2C2AAA);
++}
++
++static int tw6869_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
++{
++ struct tw6869_dev *dev;
++ int ret;
++
++ /* Allocate a new instance */
++ dev = devm_kzalloc(&pdev->dev, sizeof(struct tw6869_dev), GFP_KERNEL);
++ if (!dev)
++ return -ENOMEM;
++
++ ret = pci_enable_device(pdev);
++ if (ret)
++ return ret;
++
++ pci_set_master(pdev);
++ ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
++ if (ret) {
++ dev_err(&pdev->dev, "no suitable DMA available\n");
++ goto disable_pci;
++ }
++
++ ret = pci_request_regions(pdev, KBUILD_MODNAME);
++ if (ret)
++ goto disable_pci;
++
++ dev->mmio = pci_iomap(pdev, 0, 0);
++ if (!dev->mmio) {
++ ret = -EIO;
++ goto release_regs;
++ }
++
++ tw6869_reset(dev);
++
++ ret = devm_request_irq(&pdev->dev, pdev->irq,
++ tw6869_irq, IRQF_SHARED, KBUILD_MODNAME, dev);
++ if (ret) {
++ dev_err(&pdev->dev, "request_irq failed\n");
++ goto unmap_regs;
++ }
++
++ dev->pdev = pdev;
++ dev->ch_max = TW_CH_MAX;
++ spin_lock_init(&dev->rlock);
++
++ ret = tw6869_video_register(dev);
++ if (ret)
++ goto unmap_regs;
++
++ ret = tw6869_audio_register(dev);
++ if (ret)
++ goto video_unreg;
++
++ dev_info(&pdev->dev, "driver loaded\n");
++ return 0;
++
++video_unreg:
++ tw6869_video_unregister(dev);
++unmap_regs:
++ pci_iounmap(pdev, dev->mmio);
++release_regs:
++ pci_release_regions(pdev);
++disable_pci:
++ pci_disable_device(pdev);
++ return ret;
++}
++
++static void tw6869_remove(struct pci_dev *pdev)
++{
++ struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
++ struct tw6869_dev *dev =
++ container_of(v4l2_dev, struct tw6869_dev, v4l2_dev);
++
++ tw6869_audio_unregister(dev);
++ tw6869_video_unregister(dev);
++ pci_iounmap(pdev, dev->mmio);
++ pci_release_regions(pdev);
++ pci_disable_device(pdev);
++}
++
++/* TODO: PM */
++static struct pci_driver tw6869_driver = {
++ .name = KBUILD_MODNAME,
++ .probe = tw6869_probe,
++ .remove = tw6869_remove,
++ .id_table = tw6869_pci_tbl,
++};
++
++module_pci_driver(tw6869_driver);
+diff -Nur linux-3.14.72.orig/drivers/media/pci/tw6869/tw6869.h linux-3.14.72/drivers/media/pci/tw6869/tw6869.h
+--- linux-3.14.72.orig/drivers/media/pci/tw6869/tw6869.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/pci/tw6869/tw6869.h 2016-06-19 22:11:55.169148931 +0200
+@@ -0,0 +1,119 @@
++/*
++ * Copyright 2015 www.starterkit.ru <info@starterkit.ru>
++ *
++ * Based on:
++ * tw686x common header file
++ * Copyright 2009-10 liran <jlee@techwellinc.com.cn> [Techwell China]
++ *
++ * This program is free software; you may redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ */
++
++#ifndef __TW6869_H
++#define __TW6869_H
++
++#define PCI_VENDOR_ID_TECHWELL 0x1797
++#define PCI_DEVICE_ID_6869 0x6869
++
++#define TW_CH_MAX 8
++#define TW_VIN_MAX 4
++#define TW_FRAME_MAX 4
++#define TW_APAGE_MAX 16
++#define TW_DMA_ERR_MAX 5
++#define TW_PAGE_SIZE 4096
++
++#define TW_VID 0x00FF
++#define TW_AID 0xFF00
++#define TW_CH_0to3 0x0F
++#define TW_CH_4to7 0xF0
++
++#define ID2ID(id) ((id) & 0xF)
++#define ID2CH(id) ((id) & 0x7)
++#define ID2SC(id) ((id) & 0x3)
++
++#define BIT_ID(id) BIT((id) & 0xF)
++#define BIT_CH(id) BIT((id) & 0x7)
++#define BIT_SC(id) BIT((id) & 0x3)
++
++#define IS_VID(id) (BIT_ID(id) & TW_VID)
++#define IS_CH03(id) (BIT_CH(id) & TW_CH_0to3)
++
++#define TW_FIFO_ERR(id) ((BIT(24) | BIT(16)) << ID2CH(id))
++#define TW_PARS_ERR(id) ((BIT(8) | BIT(0)) << ID2CH(id))
++#define TW_VERR(id) (IS_VID(id) ? TW_FIFO_ERR(id) : 0)
++
++#define TW_DMA_ON 1
++#define TW_DMA_OFF 2
++#define TW_DMA_RST 3
++
++#define TW_STD_NTSC_M 0
++#define TW_STD_PAL 1
++#define TW_STD_SECAM 2
++#define TW_STD_NTSC_443 3
++#define TW_STD_PAL_M 4
++#define TW_STD_PAL_CN 5
++#define TW_STD_PAL_60 6
++
++#define TW_FMT_UYVY 0
++#define TW_FMT_RGB565 5
++#define TW_FMT_YUYV 6
++
++/**
++ * Register definitions
++ */
++#define R32_INT_STATUS 0x000 /* 0x00 */
++#define R32_PB_STATUS 0x004 /* 0x01 */
++#define R32_DMA_CMD 0x008 /* 0x02 */
++#define R32_FIFO_STATUS 0x00C /* 0x03 */
++#define R32_VIDEO_CHANNEL_ID 0x010 /* 0x04 */
++#define R32_VIDEO_PARSER_STATUS 0x014 /* 0x05 */
++#define R32_SYS_SOFT_RST 0x018 /* 0x06 */
++#define R32_DMA_CHANNEL_ENABLE 0x028 /* 0x0a */
++#define R32_DMA_CONFIG 0x02C /* 0x0b */
++#define R32_DMA_TIMER_INTERVAL 0x030 /* 0x0c */
++#define R32_DMA_CHANNEL_TIMEOUT 0x034 /* 0x0d */
++#define R32_DMA_CHANNEL_CONFIG(id) (0x040 + ID2CH(id) * 0x04) /* 0x10 */
++#define R32_VIDEO_CONTROL1 0x0A8 /* 0x2A */
++#define R32_VIDEO_CONTROL2 0x0AC /* 0x2B */
++#define R32_AUDIO_CONTROL1 0x0B0 /* 0x2C */
++#define R32_AUDIO_CONTROL2 0x0B4 /* 0x2D */
++#define R32_PHASE_REF 0x0B8 /* 0x2E */
++#define R32_VIDEO_FIELD_CTRL(id) (0x0E4 + ID2CH(id) * 0x04) /* 0x39 */
++#define R32_DMA_P_ADDR(id) (IS_VID(id) ? (0x200 + ID2CH(id) * 0x20) : (0x060 + ID2CH(id) * 0x08))
++#define R32_DMA_B_ADDR(id) (IS_VID(id) ? (0x208 + ID2CH(id) * 0x20) : (0x064 + ID2CH(id) * 0x08))
++#define R32_DMA_WHP(id) (0x204 + ID2CH(id) * 0x20) /* 0x81 */
++
++/* 0x100, 0x200 */
++#define R8_VIDEO_STATUS(id) ((IS_CH03(id) ? 0x400 : 0x800) + ID2SC(id) * 0x40)
++/* 0x101, 0x201 */
++#define R8_BRIGHT_CTRL(id) ((IS_CH03(id) ? 0x404 : 0x804) + ID2SC(id) * 0x40)
++/* 0x102, 0x202 */
++#define R8_CONTRAST_CTRL(id) ((IS_CH03(id) ? 0x408 : 0x808) + ID2SC(id) * 0x40)
++/* 0x104, 0x204 */
++#define R8_SAT_U_CTRL(id) ((IS_CH03(id) ? 0x410 : 0x810) + ID2SC(id) * 0x40)
++/* 0x105, 0x205 */
++#define R8_SAT_V_CTRL(id) ((IS_CH03(id) ? 0x414 : 0x814) + ID2SC(id) * 0x40)
++/* 0x106, 0x206 */
++#define R8_HUE_CTRL(id) ((IS_CH03(id) ? 0x418 : 0x818) + ID2SC(id) * 0x40)
++/* 0x10E, 0x20E */
++#define R8_STANDARD_SEL(id) ((IS_CH03(id) ? 0x438 : 0x838) + ID2SC(id) * 0x40)
++/* 0x180, 0x280 */
++#define R8_AVSRST(id) (IS_CH03(id) ? 0x600 : 0xA00)
++/* 0x18F, 0x28F */
++#define R8_VERTICAL_CONTROL1(id) (IS_CH03(id) ? 0x63C : 0xA3C)
++/* 0x196, 0x296 */
++#define R8_MISC_CONTROL1(id) (IS_CH03(id) ? 0x658 : 0xA58)
++/* 0x1D0, 0x2D0 */
++#define R8_AIGAIN_CTRL(id) ((IS_CH03(id) ? 0x740 : 0xB40) + ID2SC(id) * 0x04)
++
++#endif /* __TW6869_H */
+diff -Nur linux-3.14.72.orig/drivers/media/platform/Kconfig linux-3.14.72/drivers/media/platform/Kconfig
+--- linux-3.14.72.orig/drivers/media/platform/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/platform/Kconfig 2016-06-19 22:11:55.169148931 +0200
+@@ -115,6 +115,22 @@
+ To compile this driver as a module, choose M here: the module
+ will be called s3c-camif.
+
++config VIDEO_MXC_OUTPUT
++ tristate "MXC Video For Linux Video Output"
++ depends on VIDEO_DEV && ARCH_MXC && FB_MXC
++ select VIDEOBUF_DMA_CONTIG
++ ---help---
++ This is the video4linux2 output driver based on MXC module.
++
++config VIDEO_MXC_CAPTURE
++ tristate "MXC Video For Linux Video Capture"
++ depends on VIDEO_V4L2
++ ---help---
++ This is the video4linux2 capture driver based on i.MX video-in module.
++
++source "drivers/media/platform/mxc/capture/Kconfig"
++source "drivers/media/platform/mxc/output/Kconfig"
++source "drivers/media/platform/mxc/subdev/Kconfig"
+ source "drivers/media/platform/soc_camera/Kconfig"
+ source "drivers/media/platform/exynos4-is/Kconfig"
+ source "drivers/media/platform/s5p-tv/Kconfig"
+diff -Nur linux-3.14.72.orig/drivers/media/platform/Makefile linux-3.14.72/drivers/media/platform/Makefile
+--- linux-3.14.72.orig/drivers/media/platform/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/platform/Makefile 2016-06-19 22:11:55.169148931 +0200
+@@ -51,4 +51,8 @@
+
+ obj-$(CONFIG_ARCH_OMAP) += omap/
+
++obj-$(CONFIG_VIDEO_MXC_CAPTURE) += mxc/capture/
++obj-$(CONFIG_VIDEO_MXC_CAPTURE) += mxc/subdev/
++obj-$(CONFIG_VIDEO_MXC_OUTPUT) += mxc/output/
++
+ ccflags-y += -I$(srctree)/drivers/media/i2c
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/adv7180.c linux-3.14.72/drivers/media/platform/mxc/capture/adv7180.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/adv7180.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/adv7180.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,1380 @@
++/*
++ * Copyright 2005-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file adv7180.c
++ *
++ * @brief Analog Device ADV7180 video decoder functions
++ *
++ * @ingroup Camera
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-chip-ident.h>
++#include "v4l2-int-device.h"
++#include "mxc_v4l2_capture.h"
++
++#define ADV7180_VOLTAGE_ANALOG 1800000
++#define ADV7180_VOLTAGE_DIGITAL_CORE 1800000
++#define ADV7180_VOLTAGE_DIGITAL_IO 3300000
++#define ADV7180_VOLTAGE_PLL 1800000
++
++static struct regulator *dvddio_regulator;
++static struct regulator *dvdd_regulator;
++static struct regulator *avdd_regulator;
++static struct regulator *pvdd_regulator;
++static int pwn_gpio;
++
++static int adv7180_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *id);
++static int adv7180_detach(struct i2c_client *client);
++
++static const struct i2c_device_id adv7180_id[] = {
++ {"adv7180", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, adv7180_id);
++
++static struct i2c_driver adv7180_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "adv7180",
++ },
++ .probe = adv7180_probe,
++ .remove = adv7180_detach,
++ .id_table = adv7180_id,
++};
++
++/*!
++ * Maintains the information on the current state of the sensor.
++ */
++struct sensor {
++ struct sensor_data sen;
++ v4l2_std_id std_id;
++} adv7180_data;
++
++
++/*! List of input video formats supported. The video formats is corresponding
++ * with v4l2 id in video_fmt_t
++ */
++typedef enum {
++ ADV7180_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
++ ADV7180_PAL, /*!< (B, G, H, I, N)PAL video signal. */
++ ADV7180_NOT_LOCKED, /*!< Not locked on a signal. */
++} video_fmt_idx;
++
++/*! Number of video standards supported (including 'not locked' signal). */
++#define ADV7180_STD_MAX (ADV7180_PAL + 1)
++
++/*! Video format structure. */
++typedef struct {
++ int v4l2_id; /*!< Video for linux ID. */
++ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */
++ u16 raw_width; /*!< Raw width. */
++ u16 raw_height; /*!< Raw height. */
++ u16 active_width; /*!< Active width. */
++ u16 active_height; /*!< Active height. */
++ int frame_rate; /*!< Frame rate. */
++} video_fmt_t;
++
++/*! Description of video formats supported.
++ *
++ * PAL: raw=720x625, active=720x576.
++ * NTSC: raw=720x525, active=720x480.
++ */
++static video_fmt_t video_fmts[] = {
++ { /*! NTSC */
++ .v4l2_id = V4L2_STD_NTSC,
++ .name = "NTSC",
++ .raw_width = 720, /* SENS_FRM_WIDTH */
++ .raw_height = 525, /* SENS_FRM_HEIGHT */
++ .active_width = 720, /* ACT_FRM_WIDTH plus 1 */
++ .active_height = 480, /* ACT_FRM_WIDTH plus 1 */
++ .frame_rate = 30,
++ },
++ { /*! (B, G, H, I, N) PAL */
++ .v4l2_id = V4L2_STD_PAL,
++ .name = "PAL",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ .frame_rate = 25,
++ },
++ { /*! Unlocked standard */
++ .v4l2_id = V4L2_STD_ALL,
++ .name = "Autodetect",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ .frame_rate = 0,
++ },
++};
++
++/*!* Standard index of ADV7180. */
++static video_fmt_idx video_idx = ADV7180_PAL;
++
++/*! @brief This mutex is used to provide mutual exclusion.
++ *
++ * Create a mutex that can be used to provide mutually exclusive
++ * read/write access to the globally accessible data structures
++ * and variables that were defined above.
++ */
++static DEFINE_MUTEX(mutex);
++
++#define IF_NAME "adv7180"
++#define ADV7180_INPUT_CTL 0x00 /* Input Control */
++#define ADV7180_STATUS_1 0x10 /* Status #1 */
++#define ADV7180_BRIGHTNESS 0x0a /* Brightness */
++#define ADV7180_IDENT 0x11 /* IDENT */
++#define ADV7180_VSYNC_FIELD_CTL_1 0x31 /* VSYNC Field Control #1 */
++#define ADV7180_MANUAL_WIN_CTL 0x3d /* Manual Window Control */
++#define ADV7180_SD_SATURATION_CB 0xe3 /* SD Saturation Cb */
++#define ADV7180_SD_SATURATION_CR 0xe4 /* SD Saturation Cr */
++#define ADV7180_PWR_MNG 0x0f /* Power Management */
++
++/* supported controls */
++/* This hasn't been fully implemented yet.
++ * This is how it should work, though. */
++static struct v4l2_queryctrl adv7180_qctrl[] = {
++ {
++ .id = V4L2_CID_BRIGHTNESS,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .name = "Brightness",
++ .minimum = 0, /* check this value */
++ .maximum = 255, /* check this value */
++ .step = 1, /* check this value */
++ .default_value = 127, /* check this value */
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_SATURATION,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .name = "Saturation",
++ .minimum = 0, /* check this value */
++ .maximum = 255, /* check this value */
++ .step = 0x1, /* check this value */
++ .default_value = 127, /* check this value */
++ .flags = 0,
++ }
++};
++
++static inline void adv7180_power_down(int enable)
++{
++ gpio_set_value_cansleep(pwn_gpio, !enable);
++ msleep(2);
++}
++
++static int adv7180_regulator_enable(struct device *dev)
++{
++ int ret = 0;
++
++ dvddio_regulator = devm_regulator_get(dev, "DOVDD");
++
++ if (!IS_ERR(dvddio_regulator)) {
++ regulator_set_voltage(dvddio_regulator,
++ ADV7180_VOLTAGE_DIGITAL_IO,
++ ADV7180_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(dvddio_regulator);
++ if (ret) {
++ dev_err(dev, "set io voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set io voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get io voltage\n");
++ }
++
++ dvdd_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(dvdd_regulator)) {
++ regulator_set_voltage(dvdd_regulator,
++ ADV7180_VOLTAGE_DIGITAL_CORE,
++ ADV7180_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(dvdd_regulator);
++ if (ret) {
++ dev_err(dev, "set core voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set core voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get core voltage\n");
++ }
++
++ avdd_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(avdd_regulator)) {
++ regulator_set_voltage(avdd_regulator,
++ ADV7180_VOLTAGE_ANALOG,
++ ADV7180_VOLTAGE_ANALOG);
++ ret = regulator_enable(avdd_regulator);
++ if (ret) {
++ dev_err(dev, "set analog voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set analog voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get analog voltage\n");
++ }
++
++ pvdd_regulator = devm_regulator_get(dev, "PVDD");
++ if (!IS_ERR(pvdd_regulator)) {
++ regulator_set_voltage(pvdd_regulator,
++ ADV7180_VOLTAGE_PLL,
++ ADV7180_VOLTAGE_PLL);
++ ret = regulator_enable(pvdd_regulator);
++ if (ret) {
++ dev_err(dev, "set pll voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set pll voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get pll voltage\n");
++ }
++
++ return ret;
++}
++
++
++/***********************************************************************
++ * I2C transfert.
++ ***********************************************************************/
++
++/*! Read one register from a ADV7180 i2c slave device.
++ *
++ * @param *reg register in the device we wish to access.
++ *
++ * @return 0 if success, an error code otherwise.
++ */
++static inline int adv7180_read(u8 reg)
++{
++ int val;
++
++ val = i2c_smbus_read_byte_data(adv7180_data.sen.i2c_client, reg);
++ if (val < 0) {
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:read reg error: reg=%2x\n", __func__, reg);
++ return -1;
++ }
++ return val;
++}
++
++/*! Write one register of a ADV7180 i2c slave device.
++ *
++ * @param *reg register in the device we wish to access.
++ *
++ * @return 0 if success, an error code otherwise.
++ */
++static int adv7180_write_reg(u8 reg, u8 val)
++{
++ s32 ret;
++
++ ret = i2c_smbus_write_byte_data(adv7180_data.sen.i2c_client, reg, val);
++ if (ret < 0) {
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
++ reg, val);
++ return -1;
++ }
++ return 0;
++}
++
++/***********************************************************************
++ * mxc_v4l2_capture interface.
++ ***********************************************************************/
++
++/*!
++ * Return attributes of current video standard.
++ * Since this device autodetects the current standard, this function also
++ * sets the values that need to be changed if the standard changes.
++ * There is no set std equivalent function.
++ *
++ * @return None.
++ */
++static void adv7180_get_std(v4l2_std_id *std)
++{
++ int status_1, standard, idx;
++ bool locked;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180_get_std\n");
++
++ status_1 = adv7180_read(ADV7180_STATUS_1);
++ locked = status_1 & 0x1;
++ standard = status_1 & 0x70;
++
++ mutex_lock(&mutex);
++ *std = V4L2_STD_ALL;
++ idx = ADV7180_NOT_LOCKED;
++ if (locked) {
++ if (standard == 0x40) {
++ *std = V4L2_STD_PAL;
++ idx = ADV7180_PAL;
++ } else if (standard == 0) {
++ *std = V4L2_STD_NTSC;
++ idx = ADV7180_NTSC;
++ }
++ }
++ mutex_unlock(&mutex);
++
++ /* This assumes autodetect which this device uses. */
++ if (*std != adv7180_data.std_id) {
++ video_idx = idx;
++ adv7180_data.std_id = *std;
++ adv7180_data.sen.pix.width = video_fmts[video_idx].raw_width;
++ adv7180_data.sen.pix.height = video_fmts[video_idx].raw_height;
++ }
++}
++
++/***********************************************************************
++ * IOCTL Functions from v4l2_int_ioctl_desc.
++ ***********************************************************************/
++
++/*!
++ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
++ * s: pointer to standard V4L2 device structure
++ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
++ *
++ * Gets slave interface parameters.
++ * Calculates the required xclk value to support the requested
++ * clock parameters in p. This value is returned in the p
++ * parameter.
++ *
++ * vidioc_int_g_ifparm returns platform-specific information about the
++ * interface settings used by the sensor.
++ *
++ * Called on open.
++ */
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_g_ifparm\n");
++
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ /* Initialize structure to 0s then set any non-0 values. */
++ memset(p, 0, sizeof(*p));
++ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.nobt_hs_inv = 1;
++ p->u.bt656.bt_sync_correct = 1;
++
++ /* ADV7180 has a dedicated clock so no clock settings needed. */
++
++ return 0;
++}
++
++/*!
++ * Sets the camera power.
++ *
++ * s pointer to the camera device
++ * on if 1, power is to be turned on. 0 means power is to be turned off
++ *
++ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
++ * @s: pointer to standard V4L2 device structure
++ * @on: power state to which device is to be set
++ *
++ * Sets devices power state to requrested state, if possible.
++ * This is called on open, close, suspend and resume.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor *sensor = s->priv;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_s_power\n");
++
++ if (on && !sensor->sen.on) {
++ if (adv7180_write_reg(ADV7180_PWR_MNG, 0x04) != 0)
++ return -EIO;
++
++ /*
++ * FIXME:Additional 400ms to wait the chip to be stable?
++ * This is a workaround for preview scrolling issue.
++ */
++ msleep(400);
++ } else if (!on && sensor->sen.on) {
++ if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0)
++ return -EIO;
++ }
++
++ sensor->sen.on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_g_parm\n");
++
++ switch (a->type) {
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->sen.streamcap.capability;
++ cparm->timeperframe = sensor->sen.streamcap.timeperframe;
++ cparm->capturemode = sensor->sen.streamcap.capturemode;
++ break;
++
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ break;
++
++ default:
++ pr_debug("ioctl_g_parm:type is unknown %d\n", a->type);
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ *
++ * This driver cannot change these settings.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_s_parm\n");
++
++ switch (a->type) {
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor *sensor = s->priv;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_g_fmt_cap\n");
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" Returning size of %dx%d\n",
++ sensor->sen.pix.width, sensor->sen.pix.height);
++ f->fmt.pix = sensor->sen.pix;
++ break;
++
++ case V4L2_BUF_TYPE_PRIVATE: {
++ v4l2_std_id std;
++ adv7180_get_std(&std);
++ f->fmt.pix.pixelformat = (u32)std;
++ }
++ break;
++
++ default:
++ f->fmt.pix = sensor->sen.pix;
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control information
++ * from the video_control[] array. Otherwise, returns -EINVAL if the
++ * control is not supported.
++ */
++static int ioctl_queryctrl(struct v4l2_int_device *s,
++ struct v4l2_queryctrl *qc)
++{
++ int i;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_queryctrl\n");
++
++ for (i = 0; i < ARRAY_SIZE(adv7180_qctrl); i++)
++ if (qc->id && qc->id == adv7180_qctrl[i].id) {
++ memcpy(qc, &(adv7180_qctrl[i]),
++ sizeof(*qc));
++ return 0;
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++ int sat = 0;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_g_ctrl\n");
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BRIGHTNESS\n");
++ adv7180_data.sen.brightness = adv7180_read(ADV7180_BRIGHTNESS);
++ vc->value = adv7180_data.sen.brightness;
++ break;
++ case V4L2_CID_CONTRAST:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_CONTRAST\n");
++ vc->value = adv7180_data.sen.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_SATURATION\n");
++ sat = adv7180_read(ADV7180_SD_SATURATION_CB);
++ adv7180_data.sen.saturation = sat;
++ vc->value = adv7180_data.sen.saturation;
++ break;
++ case V4L2_CID_HUE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HUE\n");
++ vc->value = adv7180_data.sen.hue;
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_DO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_RED_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_RED_BALANCE\n");
++ vc->value = adv7180_data.sen.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BLUE_BALANCE\n");
++ vc->value = adv7180_data.sen.blue;
++ break;
++ case V4L2_CID_GAMMA:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAMMA\n");
++ break;
++ case V4L2_CID_EXPOSURE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_EXPOSURE\n");
++ vc->value = adv7180_data.sen.ae_mode;
++ break;
++ case V4L2_CID_AUTOGAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTOGAIN\n");
++ break;
++ case V4L2_CID_GAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAIN\n");
++ break;
++ case V4L2_CID_HFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HFLIP\n");
++ break;
++ case V4L2_CID_VFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_VFLIP\n");
++ break;
++ default:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " Default case\n");
++ vc->value = 0;
++ ret = -EPERM;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++ u8 tmp;
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_s_ctrl\n");
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BRIGHTNESS\n");
++ tmp = vc->value;
++ adv7180_write_reg(ADV7180_BRIGHTNESS, tmp);
++ adv7180_data.sen.brightness = vc->value;
++ break;
++ case V4L2_CID_CONTRAST:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_CONTRAST\n");
++ break;
++ case V4L2_CID_SATURATION:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_SATURATION\n");
++ tmp = vc->value;
++ adv7180_write_reg(ADV7180_SD_SATURATION_CB, tmp);
++ adv7180_write_reg(ADV7180_SD_SATURATION_CR, tmp);
++ adv7180_data.sen.saturation = vc->value;
++ break;
++ case V4L2_CID_HUE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HUE\n");
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_DO_WHITE_BALANCE\n");
++ break;
++ case V4L2_CID_RED_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_RED_BALANCE\n");
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_BLUE_BALANCE\n");
++ break;
++ case V4L2_CID_GAMMA:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAMMA\n");
++ break;
++ case V4L2_CID_EXPOSURE:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_EXPOSURE\n");
++ break;
++ case V4L2_CID_AUTOGAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_AUTOGAIN\n");
++ break;
++ case V4L2_CID_GAIN:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_GAIN\n");
++ break;
++ case V4L2_CID_HFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_HFLIP\n");
++ break;
++ case V4L2_CID_VFLIP:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " V4L2_CID_VFLIP\n");
++ break;
++ default:
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ " Default case\n");
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index >= 1)
++ return -EINVAL;
++
++ fsize->discrete.width = video_fmts[video_idx].active_width;
++ fsize->discrete.height = video_fmts[video_idx].active_height;
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_frameintervals - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMEINTERVALS ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
++ struct v4l2_frmivalenum *fival)
++{
++ video_fmt_t fmt;
++ int i;
++
++ if (fival->index != 0)
++ return -EINVAL;
++
++ for (i = 0; i < ARRAY_SIZE(video_fmts) - 1; i++) {
++ fmt = video_fmts[i];
++ if (fival->width == fmt.active_width &&
++ fival->height == fmt.active_height) {
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++ fival->discrete.denominator = fmt.frame_rate;
++ return 0;
++ }
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "adv7180_decoder");
++ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_ADV7180;
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_init\n");
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_dev_init\n");
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module.
++ */
++static struct v4l2_int_ioctl_desc adv7180_ioctl_desc[] = {
++
++ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init},
++
++ /*!
++ * Delinitialise the dev. at slave detach.
++ * The complement of ioctl_dev_init.
++ */
++/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */
++
++ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power},
++ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm},
++/* {vidioc_int_g_needs_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
++/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
++ {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init},
++
++ /*!
++ * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
++ */
++/* {vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */
++
++ /*!
++ * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type.
++ * This ioctl is used to negotiate the image capture size and
++ * pixel format without actually making it take effect.
++ */
++/* {vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
++
++ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap},
++
++ /*!
++ * If the requested format is supported, configures the HW to use that
++ * format, returns error code if format not supported or HW can't be
++ * correctly configured.
++ */
++/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
++
++ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm},
++ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm},
++ {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl},
++ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl},
++ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl},
++ {vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_framesizes},
++ {vidioc_int_enum_frameintervals_num,
++ (v4l2_int_ioctl_func *)
++ ioctl_enum_frameintervals},
++ {vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *)ioctl_g_chip_ident},
++};
++
++static struct v4l2_int_slave adv7180_slave = {
++ .ioctls = adv7180_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(adv7180_ioctl_desc),
++};
++
++static struct v4l2_int_device adv7180_int_device = {
++ .module = THIS_MODULE,
++ .name = "adv7180",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &adv7180_slave,
++ },
++};
++
++
++/***********************************************************************
++ * I2C client and driver.
++ ***********************************************************************/
++
++/*! ADV7180 Reset function.
++ *
++ * @return None.
++ */
++static void adv7180_hard_reset(bool cvbs)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "In adv7180:adv7180_hard_reset\n");
++
++ if (cvbs) {
++ /* Set CVBS input on AIN1 */
++ adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
++ } else {
++ /*
++ * Set YPbPr input on AIN1,4,5 and normal
++ * operations(autodection of all stds).
++ */
++ adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
++ }
++
++ /* Datasheet recommends */
++ adv7180_write_reg(0x01, 0xc8);
++ adv7180_write_reg(0x02, 0x04);
++ adv7180_write_reg(0x03, 0x00);
++ adv7180_write_reg(0x04, 0x45);
++ adv7180_write_reg(0x05, 0x00);
++ adv7180_write_reg(0x06, 0x02);
++ adv7180_write_reg(0x07, 0x7F);
++ adv7180_write_reg(0x08, 0x80);
++ adv7180_write_reg(0x0A, 0x00);
++ adv7180_write_reg(0x0B, 0x00);
++ adv7180_write_reg(0x0C, 0x36);
++ adv7180_write_reg(0x0D, 0x7C);
++ adv7180_write_reg(0x0E, 0x00);
++ adv7180_write_reg(0x0F, 0x00);
++ adv7180_write_reg(0x13, 0x00);
++ adv7180_write_reg(0x14, 0x12);
++ adv7180_write_reg(0x15, 0x00);
++ adv7180_write_reg(0x16, 0x00);
++ adv7180_write_reg(0x17, 0x01);
++ adv7180_write_reg(0x18, 0x93);
++ adv7180_write_reg(0xF1, 0x19);
++ adv7180_write_reg(0x1A, 0x00);
++ adv7180_write_reg(0x1B, 0x00);
++ adv7180_write_reg(0x1C, 0x00);
++ adv7180_write_reg(0x1D, 0x40);
++ adv7180_write_reg(0x1E, 0x00);
++ adv7180_write_reg(0x1F, 0x00);
++ adv7180_write_reg(0x20, 0x00);
++ adv7180_write_reg(0x21, 0x00);
++ adv7180_write_reg(0x22, 0x00);
++ adv7180_write_reg(0x23, 0xC0);
++ adv7180_write_reg(0x24, 0x00);
++ adv7180_write_reg(0x25, 0x00);
++ adv7180_write_reg(0x26, 0x00);
++ adv7180_write_reg(0x27, 0x58);
++ adv7180_write_reg(0x28, 0x00);
++ adv7180_write_reg(0x29, 0x00);
++ adv7180_write_reg(0x2A, 0x00);
++ adv7180_write_reg(0x2B, 0xE1);
++ adv7180_write_reg(0x2C, 0xAE);
++ adv7180_write_reg(0x2D, 0xF4);
++ adv7180_write_reg(0x2E, 0x00);
++ adv7180_write_reg(0x2F, 0xF0);
++ adv7180_write_reg(0x30, 0x00);
++ adv7180_write_reg(0x31, 0x12);
++ adv7180_write_reg(0x32, 0x41);
++ adv7180_write_reg(0x33, 0x84);
++ adv7180_write_reg(0x34, 0x00);
++ adv7180_write_reg(0x35, 0x02);
++ adv7180_write_reg(0x36, 0x00);
++ adv7180_write_reg(0x37, 0x01);
++ adv7180_write_reg(0x38, 0x80);
++ adv7180_write_reg(0x39, 0xC0);
++ adv7180_write_reg(0x3A, 0x10);
++ adv7180_write_reg(0x3B, 0x05);
++ adv7180_write_reg(0x3C, 0x58);
++ adv7180_write_reg(0x3D, 0xB2);
++ adv7180_write_reg(0x3E, 0x64);
++ adv7180_write_reg(0x3F, 0xE4);
++ adv7180_write_reg(0x40, 0x90);
++ adv7180_write_reg(0x41, 0x01);
++ adv7180_write_reg(0x42, 0x7E);
++ adv7180_write_reg(0x43, 0xA4);
++ adv7180_write_reg(0x44, 0xFF);
++ adv7180_write_reg(0x45, 0xB6);
++ adv7180_write_reg(0x46, 0x12);
++ adv7180_write_reg(0x48, 0x00);
++ adv7180_write_reg(0x49, 0x00);
++ adv7180_write_reg(0x4A, 0x00);
++ adv7180_write_reg(0x4B, 0x00);
++ adv7180_write_reg(0x4C, 0x00);
++ adv7180_write_reg(0x4D, 0xEF);
++ adv7180_write_reg(0x4E, 0x08);
++ adv7180_write_reg(0x4F, 0x08);
++ adv7180_write_reg(0x50, 0x08);
++ adv7180_write_reg(0x51, 0x24);
++ adv7180_write_reg(0x52, 0x0B);
++ adv7180_write_reg(0x53, 0x4E);
++ adv7180_write_reg(0x54, 0x80);
++ adv7180_write_reg(0x55, 0x00);
++ adv7180_write_reg(0x56, 0x10);
++ adv7180_write_reg(0x57, 0x00);
++ adv7180_write_reg(0x58, 0x00);
++ adv7180_write_reg(0x59, 0x00);
++ adv7180_write_reg(0x5A, 0x00);
++ adv7180_write_reg(0x5B, 0x00);
++ adv7180_write_reg(0x5C, 0x00);
++ adv7180_write_reg(0x5D, 0x00);
++ adv7180_write_reg(0x5E, 0x00);
++ adv7180_write_reg(0x5F, 0x00);
++ adv7180_write_reg(0x60, 0x00);
++ adv7180_write_reg(0x61, 0x00);
++ adv7180_write_reg(0x62, 0x20);
++ adv7180_write_reg(0x63, 0x00);
++ adv7180_write_reg(0x64, 0x00);
++ adv7180_write_reg(0x65, 0x00);
++ adv7180_write_reg(0x66, 0x00);
++ adv7180_write_reg(0x67, 0x03);
++ adv7180_write_reg(0x68, 0x01);
++ adv7180_write_reg(0x69, 0x00);
++ adv7180_write_reg(0x6A, 0x00);
++ adv7180_write_reg(0x6B, 0xC0);
++ adv7180_write_reg(0x6C, 0x00);
++ adv7180_write_reg(0x6D, 0x00);
++ adv7180_write_reg(0x6E, 0x00);
++ adv7180_write_reg(0x6F, 0x00);
++ adv7180_write_reg(0x70, 0x00);
++ adv7180_write_reg(0x71, 0x00);
++ adv7180_write_reg(0x72, 0x00);
++ adv7180_write_reg(0x73, 0x10);
++ adv7180_write_reg(0x74, 0x04);
++ adv7180_write_reg(0x75, 0x01);
++ adv7180_write_reg(0x76, 0x00);
++ adv7180_write_reg(0x77, 0x3F);
++ adv7180_write_reg(0x78, 0xFF);
++ adv7180_write_reg(0x79, 0xFF);
++ adv7180_write_reg(0x7A, 0xFF);
++ adv7180_write_reg(0x7B, 0x1E);
++ adv7180_write_reg(0x7C, 0xC0);
++ adv7180_write_reg(0x7D, 0x00);
++ adv7180_write_reg(0x7E, 0x00);
++ adv7180_write_reg(0x7F, 0x00);
++ adv7180_write_reg(0x80, 0x00);
++ adv7180_write_reg(0x81, 0xC0);
++ adv7180_write_reg(0x82, 0x04);
++ adv7180_write_reg(0x83, 0x00);
++ adv7180_write_reg(0x84, 0x0C);
++ adv7180_write_reg(0x85, 0x02);
++ adv7180_write_reg(0x86, 0x03);
++ adv7180_write_reg(0x87, 0x63);
++ adv7180_write_reg(0x88, 0x5A);
++ adv7180_write_reg(0x89, 0x08);
++ adv7180_write_reg(0x8A, 0x10);
++ adv7180_write_reg(0x8B, 0x00);
++ adv7180_write_reg(0x8C, 0x40);
++ adv7180_write_reg(0x8D, 0x00);
++ adv7180_write_reg(0x8E, 0x40);
++ adv7180_write_reg(0x8F, 0x00);
++ adv7180_write_reg(0x90, 0x00);
++ adv7180_write_reg(0x91, 0x50);
++ adv7180_write_reg(0x92, 0x00);
++ adv7180_write_reg(0x93, 0x00);
++ adv7180_write_reg(0x94, 0x00);
++ adv7180_write_reg(0x95, 0x00);
++ adv7180_write_reg(0x96, 0x00);
++ adv7180_write_reg(0x97, 0xF0);
++ adv7180_write_reg(0x98, 0x00);
++ adv7180_write_reg(0x99, 0x00);
++ adv7180_write_reg(0x9A, 0x00);
++ adv7180_write_reg(0x9B, 0x00);
++ adv7180_write_reg(0x9C, 0x00);
++ adv7180_write_reg(0x9D, 0x00);
++ adv7180_write_reg(0x9E, 0x00);
++ adv7180_write_reg(0x9F, 0x00);
++ adv7180_write_reg(0xA0, 0x00);
++ adv7180_write_reg(0xA1, 0x00);
++ adv7180_write_reg(0xA2, 0x00);
++ adv7180_write_reg(0xA3, 0x00);
++ adv7180_write_reg(0xA4, 0x00);
++ adv7180_write_reg(0xA5, 0x00);
++ adv7180_write_reg(0xA6, 0x00);
++ adv7180_write_reg(0xA7, 0x00);
++ adv7180_write_reg(0xA8, 0x00);
++ adv7180_write_reg(0xA9, 0x00);
++ adv7180_write_reg(0xAA, 0x00);
++ adv7180_write_reg(0xAB, 0x00);
++ adv7180_write_reg(0xAC, 0x00);
++ adv7180_write_reg(0xAD, 0x00);
++ adv7180_write_reg(0xAE, 0x60);
++ adv7180_write_reg(0xAF, 0x00);
++ adv7180_write_reg(0xB0, 0x00);
++ adv7180_write_reg(0xB1, 0x60);
++ adv7180_write_reg(0xB2, 0x1C);
++ adv7180_write_reg(0xB3, 0x54);
++ adv7180_write_reg(0xB4, 0x00);
++ adv7180_write_reg(0xB5, 0x00);
++ adv7180_write_reg(0xB6, 0x00);
++ adv7180_write_reg(0xB7, 0x13);
++ adv7180_write_reg(0xB8, 0x03);
++ adv7180_write_reg(0xB9, 0x33);
++ adv7180_write_reg(0xBF, 0x02);
++ adv7180_write_reg(0xC0, 0x00);
++ adv7180_write_reg(0xC1, 0x00);
++ adv7180_write_reg(0xC2, 0x00);
++ adv7180_write_reg(0xC3, 0x00);
++ adv7180_write_reg(0xC4, 0x00);
++ adv7180_write_reg(0xC5, 0x81);
++ adv7180_write_reg(0xC6, 0x00);
++ adv7180_write_reg(0xC7, 0x00);
++ adv7180_write_reg(0xC8, 0x00);
++ adv7180_write_reg(0xC9, 0x04);
++ adv7180_write_reg(0xCC, 0x69);
++ adv7180_write_reg(0xCD, 0x00);
++ adv7180_write_reg(0xCE, 0x01);
++ adv7180_write_reg(0xCF, 0xB4);
++ adv7180_write_reg(0xD0, 0x00);
++ adv7180_write_reg(0xD1, 0x10);
++ adv7180_write_reg(0xD2, 0xFF);
++ adv7180_write_reg(0xD3, 0xFF);
++ adv7180_write_reg(0xD4, 0x7F);
++ adv7180_write_reg(0xD5, 0x7F);
++ adv7180_write_reg(0xD6, 0x3E);
++ adv7180_write_reg(0xD7, 0x08);
++ adv7180_write_reg(0xD8, 0x3C);
++ adv7180_write_reg(0xD9, 0x08);
++ adv7180_write_reg(0xDA, 0x3C);
++ adv7180_write_reg(0xDB, 0x9B);
++ adv7180_write_reg(0xDC, 0xAC);
++ adv7180_write_reg(0xDD, 0x4C);
++ adv7180_write_reg(0xDE, 0x00);
++ adv7180_write_reg(0xDF, 0x00);
++ adv7180_write_reg(0xE0, 0x14);
++ adv7180_write_reg(0xE1, 0x80);
++ adv7180_write_reg(0xE2, 0x80);
++ adv7180_write_reg(0xE3, 0x80);
++ adv7180_write_reg(0xE4, 0x80);
++ adv7180_write_reg(0xE5, 0x25);
++ adv7180_write_reg(0xE6, 0x44);
++ adv7180_write_reg(0xE7, 0x63);
++ adv7180_write_reg(0xE8, 0x65);
++ adv7180_write_reg(0xE9, 0x14);
++ adv7180_write_reg(0xEA, 0x63);
++ adv7180_write_reg(0xEB, 0x55);
++ adv7180_write_reg(0xEC, 0x55);
++ adv7180_write_reg(0xEE, 0x00);
++ adv7180_write_reg(0xEF, 0x4A);
++ adv7180_write_reg(0xF0, 0x44);
++ adv7180_write_reg(0xF1, 0x0C);
++ adv7180_write_reg(0xF2, 0x32);
++ adv7180_write_reg(0xF3, 0x00);
++ adv7180_write_reg(0xF4, 0x3F);
++ adv7180_write_reg(0xF5, 0xE0);
++ adv7180_write_reg(0xF6, 0x69);
++ adv7180_write_reg(0xF7, 0x10);
++ adv7180_write_reg(0xF8, 0x00);
++ adv7180_write_reg(0xF9, 0x03);
++ adv7180_write_reg(0xFA, 0xFA);
++ adv7180_write_reg(0xFB, 0x40);
++}
++
++/*! ADV7180 I2C attach function.
++ *
++ * @param *adapter struct i2c_adapter *.
++ *
++ * @return Error code indicating success or failure.
++ */
++
++/*!
++ * ADV7180 I2C probe function.
++ * Function set in i2c_driver struct.
++ * Called by insmod.
++ *
++ * @param *adapter I2C adapter descriptor.
++ *
++ * @return Error code indicating success or failure.
++ */
++static int adv7180_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ int rev_id;
++ int ret = 0;
++ u32 cvbs = true;
++ struct pinctrl *pinctrl;
++ struct device *dev = &client->dev;
++
++ printk(KERN_ERR"DBG sensor data is at %p\n", &adv7180_data);
++
++ /* ov5640 pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "setup pinctrl failed\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_err(dev, "no sensor pwdn pin available\n");
++ return -ENODEV;
++ }
++ ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "adv7180_pwdn");
++ if (ret < 0) {
++ dev_err(dev, "no power pin available!\n");
++ return ret;
++ }
++
++ adv7180_regulator_enable(dev);
++
++ adv7180_power_down(0);
++
++ msleep(1);
++
++ /* Set initial values for the sensor struct. */
++ memset(&adv7180_data, 0, sizeof(adv7180_data));
++ adv7180_data.sen.i2c_client = client;
++ adv7180_data.sen.streamcap.timeperframe.denominator = 30;
++ adv7180_data.sen.streamcap.timeperframe.numerator = 1;
++ adv7180_data.std_id = V4L2_STD_ALL;
++ video_idx = ADV7180_NOT_LOCKED;
++ adv7180_data.sen.pix.width = video_fmts[video_idx].raw_width;
++ adv7180_data.sen.pix.height = video_fmts[video_idx].raw_height;
++ adv7180_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */
++ adv7180_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */
++ adv7180_data.sen.on = true;
++
++ adv7180_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(adv7180_data.sen.sensor_clk)) {
++ dev_err(dev, "get mclk failed\n");
++ return PTR_ERR(adv7180_data.sen.sensor_clk);
++ }
++
++ ret = of_property_read_u32(dev->of_node, "mclk",
++ &adv7180_data.sen.mclk);
++ if (ret) {
++ dev_err(dev, "mclk frequency is invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(
++ dev->of_node, "mclk_source",
++ (u32 *) &(adv7180_data.sen.mclk_source));
++ if (ret) {
++ dev_err(dev, "mclk_source invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(dev->of_node, "csi_id",
++ &(adv7180_data.sen.csi));
++ if (ret) {
++ dev_err(dev, "csi_id invalid\n");
++ return ret;
++ }
++
++ clk_prepare_enable(adv7180_data.sen.sensor_clk);
++
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:adv7180 probe i2c address is 0x%02X\n",
++ __func__, adv7180_data.sen.i2c_client->addr);
++
++ /*! Read the revision ID of the tvin chip */
++ rev_id = adv7180_read(ADV7180_IDENT);
++ dev_dbg(dev,
++ "%s:Analog Device adv7%2X0 detected!\n", __func__,
++ rev_id);
++
++ ret = of_property_read_u32(dev->of_node, "cvbs", &(cvbs));
++ if (ret) {
++ dev_err(dev, "cvbs setting is not found\n");
++ cvbs = true;
++ }
++
++ /*! ADV7180 initialization. */
++ adv7180_hard_reset(cvbs);
++
++ pr_debug(" type is %d (expect %d)\n",
++ adv7180_int_device.type, v4l2_int_type_slave);
++ pr_debug(" num ioctls is %d\n",
++ adv7180_int_device.u.slave->num_ioctls);
++
++ /* This function attaches this structure to the /dev/video0 device.
++ * The pointer in priv points to the adv7180_data structure here.*/
++ adv7180_int_device.priv = &adv7180_data;
++ ret = v4l2_int_device_register(&adv7180_int_device);
++
++ clk_disable_unprepare(adv7180_data.sen.sensor_clk);
++
++ return ret;
++}
++
++/*!
++ * ADV7180 I2C detach function.
++ * Called on rmmod.
++ *
++ * @param *client struct i2c_client*.
++ *
++ * @return Error code indicating success or failure.
++ */
++static int adv7180_detach(struct i2c_client *client)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev,
++ "%s:Removing %s video decoder @ 0x%02X from adapter %s\n",
++ __func__, IF_NAME, client->addr << 1, client->adapter->name);
++
++ /* Power down via i2c */
++ adv7180_write_reg(ADV7180_PWR_MNG, 0x24);
++
++ if (dvddio_regulator)
++ regulator_disable(dvddio_regulator);
++
++ if (dvdd_regulator)
++ regulator_disable(dvdd_regulator);
++
++ if (avdd_regulator)
++ regulator_disable(avdd_regulator);
++
++ if (pvdd_regulator)
++ regulator_disable(pvdd_regulator);
++
++ v4l2_int_device_unregister(&adv7180_int_device);
++
++ return 0;
++}
++
++/*!
++ * ADV7180 init function.
++ * Called on insmod.
++ *
++ * @return Error code indicating success or failure.
++ */
++static __init int adv7180_init(void)
++{
++ u8 err = 0;
++
++ pr_debug("In adv7180_init\n");
++
++ /* Tells the i2c driver what functions to call for this driver. */
++ err = i2c_add_driver(&adv7180_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * ADV7180 cleanup function.
++ * Called on rmmod.
++ *
++ * @return Error code indicating success or failure.
++ */
++static void __exit adv7180_clean(void)
++{
++ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180_clean\n");
++ i2c_del_driver(&adv7180_i2c_driver);
++}
++
++module_init(adv7180_init);
++module_exit(adv7180_clean);
++
++MODULE_AUTHOR("Freescale Semiconductor");
++MODULE_DESCRIPTION("Anolog Device ADV7180 video decoder driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c linux-3.14.72/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,493 @@
++
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_bg_overlay_sdc_bg.c
++ *
++ * @brief IPU Use case for PRP-VF back-ground
++ *
++ * @ingroup IPU
++ */
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/fb.h>
++#include <linux/ipu.h>
++#include <linux/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int csi_buffer_num;
++static u32 bpp, csi_mem_bufsize = 3;
++static u32 out_format;
++static struct ipu_soc *disp_ipu;
++static u32 offset;
++
++static void csi_buf_work_func(struct work_struct *work)
++{
++ int err = 0;
++ cam_data *cam =
++ container_of(work, struct _cam_data, csi_work_struct);
++
++ struct ipu_task task;
++ memset(&task, 0, sizeof(task));
++
++ if (csi_buffer_num)
++ task.input.paddr = cam->vf_bufs[0];
++ else
++ task.input.paddr = cam->vf_bufs[1];
++ task.input.width = cam->crop_current.width;
++ task.input.height = cam->crop_current.height;
++ task.input.format = IPU_PIX_FMT_UYVY;
++
++ task.output.paddr = offset;
++ task.output.width = cam->overlay_fb->var.xres;
++ task.output.height = cam->overlay_fb->var.yres;
++ task.output.format = out_format;
++ task.output.rotate = cam->rotation;
++ task.output.crop.pos.x = cam->win.w.left;
++ task.output.crop.pos.y = cam->win.w.top;
++ if (cam->win.w.width > 1024 || cam->win.w.height > 1024) {
++ task.output.crop.w = cam->overlay_fb->var.xres;
++ task.output.crop.h = cam->overlay_fb->var.yres;
++ } else {
++ task.output.crop.w = cam->win.w.width;
++ task.output.crop.h = cam->win.w.height;
++ }
++again:
++ err = ipu_check_task(&task);
++ if (err != IPU_CHECK_OK) {
++ if (err > IPU_CHECK_ERR_MIN) {
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) {
++ task.input.crop.w -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) {
++ task.input.crop.h -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
++ task.output.width -= 8;
++ task.output.crop.w = task.output.width;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
++ task.output.height -= 8;
++ task.output.crop.h = task.output.height;
++ goto again;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ err = ipu_queue_task(&task);
++ if (err < 0)
++ printk(KERN_ERR "queue ipu task error\n");
++}
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++
++/*!
++ * csi ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t csi_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, csi_buffer_num);
++ schedule_work(&cam->csi_work_struct);
++ csi_buffer_num = (csi_buffer_num == 0) ? 1 : 0;
++ return IRQ_HANDLED;
++}
++
++static int csi_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t params;
++ u32 pixel_fmt;
++ int err = 0, sensor_protocol = 0;
++
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++
++ memset(&params, 0, sizeof(ipu_channel_params_t));
++ params.csi_mem.csi = cam->csi;
++
++ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi);
++ switch (sensor_protocol) {
++ case IPU_CSI_CLK_MODE_GATED_CLK:
++ case IPU_CSI_CLK_MODE_NONGATED_CLK:
++ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
++ params.csi_mem.interlaced = false;
++ break;
++ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
++ params.csi_mem.interlaced = true;
++ break;
++ default:
++ printk(KERN_ERR "sensor protocol unsupported\n");
++ return -EINVAL;
++ }
++ err = cam_mipi_csi2_enable(cam, &params.csi_mem.mipi);
++ if (err)
++ return err;
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ }
++ csi_mem_bufsize =
++ cam->crop_current.width * cam->crop_current.height * 2;
++ cam->vf_bufs_size[0] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ (dma_addr_t *) &
++ cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_2;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ (dma_addr_t *) &
++ cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_1;
++ }
++ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
++
++ err = ipu_channel_request(cam->ipu, CSI_MEM, &params, &cam->ipu_chan);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d\n", __func__, err);
++ goto out_1;
++ }
++
++ pixel_fmt = IPU_PIX_FMT_UYVY;
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ pixel_fmt, cam->crop_current.width,
++ cam->crop_current.height,
++ cam->crop_current.width, IPU_ROTATE_NONE,
++ cam->vf_bufs[0], cam->vf_bufs[1], 0,
++ cam->offset.u_offset, cam->offset.u_offset);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_MEM output buffer\n");
++ goto out_1;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
++ goto out_1;
++ }
++
++ csi_buffer_num = 0;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 1);
++ return err;
++out_1:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++out_2:
++ return err;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ csi_enc_callback, 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering CSI0_OUT_EOF irq\n");
++ return err;
++ }
++
++ INIT_WORK(&cam->csi_work_struct, csi_buf_work_func);
++
++ err = csi_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "csi_enc_setup %d\n", err);
++ goto out1;
++ }
++
++ return err;
++out1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++ return err;
++}
++
++/*!
++ * bg_overlay_start - start the overlay task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int bg_overlay_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already start.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ out_format = cam->v4l2_fb.fmt.pixelformat;
++ if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) {
++ bpp = 3, csi_mem_bufsize = 3;
++ pr_info("BGR24\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) {
++ bpp = 2, csi_mem_bufsize = 2;
++ pr_info("RGB565\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) {
++ bpp = 4, csi_mem_bufsize = 4;
++ pr_info("BGR32\n");
++ } else {
++ printk(KERN_ERR
++ "unsupported fix format from the framebuffer.\n");
++ return -EINVAL;
++ }
++
++ offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top +
++ csi_mem_bufsize * cam->win.w.left;
++
++ if (cam->v4l2_fb.base == 0)
++ printk(KERN_ERR "invalid frame buffer address.\n");
++ else
++ offset += (u32) cam->v4l2_fb.base;
++
++ csi_mem_bufsize = cam->win.w.width * cam->win.w.height
++ * csi_mem_bufsize;
++
++ err = csi_enc_enabling_tasks(cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error csi enc enable fail\n");
++ return err;
++ }
++
++ cam->overlay_active = true;
++ return err;
++}
++
++/*!
++ * bg_overlay_stop - stop the overlay task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int bg_overlay_stop(void *private)
++{
++ int err = 0;
++ int err2 = 0;
++ cam_data *cam = (cam_data *) private;
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ err = ipu_channel_disable(cam->ipu_chan, true);
++
++ ipu_channel_free(&cam->ipu_chan);
++
++ csi_buffer_num = 0;
++
++ err2 = cam_mipi_csi2_disable(cam);
++ flush_work(&cam->csi_work_struct);
++ cancel_work_sync(&cam->csi_work_struct);
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[0],
++ cam->rot_vf_bufs_vaddr[0],
++ cam->rot_vf_bufs[0]);
++ cam->rot_vf_bufs_vaddr[0] = NULL;
++ cam->rot_vf_bufs[0] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[1],
++ cam->rot_vf_bufs_vaddr[1],
++ cam->rot_vf_bufs[1]);
++ cam->rot_vf_bufs_vaddr[1] = NULL;
++ cam->rot_vf_bufs[1] = 0;
++ }
++
++ cam->overlay_active = false;
++ return err ? err : err2;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int bg_overlay_enable_csi(void *private)
++{
++ return cam_ipu_enable_csi((cam_data *)private);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int bg_overlay_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++ return cam_ipu_disable_csi(cam);
++}
++
++/*!
++ * function to select bg as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int bg_overlay_sdc_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = bg_overlay_start;
++ cam->vf_stop_sdc = bg_overlay_stop;
++ cam->vf_enable_csi = bg_overlay_enable_csi;
++ cam->vf_disable_csi = bg_overlay_disable_csi;
++ cam->overlay_active = false;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(bg_overlay_sdc_select);
++
++/*!
++ * function to de-select bg as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int bg_overlay_sdc_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(bg_overlay_sdc_deselect);
++
++/*!
++ * Init background overlay task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int bg_overlay_sdc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit background overlay task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit bg_overlay_sdc_exit(void)
++{
++}
++
++module_init(bg_overlay_sdc_init);
++module_exit(bg_overlay_sdc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_csi_enc.c linux-3.14.72/drivers/media/platform/mxc/capture/ipu_csi_enc.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_csi_enc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_csi_enc.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,384 @@
++/*
++ * Copyright 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_csi_enc.c
++ *
++ * @brief CSI Use case for video capture
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/dma-mapping.h>
++#include <linux/ipu.h>
++#include <linux/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#ifdef CAMERA_DBG
++ #define CAMERA_TRACE(x) (printk)x
++#else
++ #define CAMERA_TRACE(x)
++#endif
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * csi ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t csi_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ if (cam->enc_callback == NULL)
++ return IRQ_HANDLED;
++
++ cam->enc_callback(irq, dev_id);
++ return IRQ_HANDLED;
++}
++
++/*!
++ * CSI ENC enable channel setup function
++ *
++ * @param cam struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t params;
++ u32 pixel_fmt;
++ int err = 0, sensor_protocol = 0;
++ dma_addr_t dummy = cam->dummy_frame.buffer.m.offset;
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ int ipu_id;
++ int csi_id;
++#endif
++ struct v4l2_format cam_fmt;
++
++ CAMERA_TRACE("In csi_enc_setup\n");
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++
++ memset(&params, 0, sizeof(ipu_channel_params_t));
++ params.csi_mem.csi = cam->csi;
++
++ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi);
++ switch (sensor_protocol) {
++ case IPU_CSI_CLK_MODE_GATED_CLK:
++ case IPU_CSI_CLK_MODE_NONGATED_CLK:
++ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
++ params.csi_mem.interlaced = false;
++ break;
++ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
++ params.csi_mem.interlaced = true;
++ break;
++ default:
++ printk(KERN_ERR "sensor protocol unsupported\n");
++ return -EINVAL;
++ }
++
++ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
++ pixel_fmt = IPU_PIX_FMT_YUV420P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420)
++ pixel_fmt = IPU_PIX_FMT_YVU420P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P)
++ pixel_fmt = IPU_PIX_FMT_YUV422P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY)
++ {
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++ if (cam_fmt.fmt.pix.pixelformat == IPU_PIX_FMT_GENERIC_16)
++ pixel_fmt = cam_fmt.fmt.pix.pixelformat;
++ else
++ pixel_fmt = IPU_PIX_FMT_UYVY;
++ }
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
++ pixel_fmt = IPU_PIX_FMT_YUYV;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)
++ pixel_fmt = IPU_PIX_FMT_NV12;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24)
++ pixel_fmt = IPU_PIX_FMT_BGR24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
++ pixel_fmt = IPU_PIX_FMT_RGB24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565)
++ pixel_fmt = IPU_PIX_FMT_RGB565;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32)
++ pixel_fmt = IPU_PIX_FMT_BGR32;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32)
++ pixel_fmt = IPU_PIX_FMT_RGB32;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_SBGGR8)
++ pixel_fmt = IPU_PIX_FMT_GENERIC;
++ else {
++ printk(KERN_ERR "format not supported\n");
++ return -EINVAL;
++ }
++ err = cam_mipi_csi2_enable(cam, &params.csi_mem.mipi);
++ if (err)
++ return err;
++
++ err = ipu_channel_request(cam->ipu, CSI_MEM, &params, &cam->ipu_chan);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d\n", __func__, err);
++ return err;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ pixel_fmt, cam->v2f.fmt.pix.width,
++ cam->v2f.fmt.pix.height,
++ cam->v2f.fmt.pix.bytesperline,
++ cam->rotation,
++ dummy, dummy, 0,
++ cam->offset.u_offset,
++ cam->offset.v_offset);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_MEM output buffer\n");
++ return err;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * function to update physical buffer address for encorder IDMA channel
++ *
++ * @param eba physical buffer address for encorder IDMA channel
++ * @param buffer_num int buffer 0 or buffer 1
++ *
++ * @return status
++ */
++static int csi_enc_eba_update(struct ipu_soc *ipu, dma_addr_t eba,
++ int *buffer_num)
++{
++ int err = 0;
++
++ pr_debug("eba %x\n", eba);
++ err = ipu_update_channel_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num, eba);
++ if (err != 0) {
++ ipu_clear_buffer_ready(ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num);
++
++ err = ipu_update_channel_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num, eba);
++ if (err != 0) {
++ pr_err("ERROR: v4l2 capture: fail to update "
++ "buf%d\n", *buffer_num);
++ return err;
++ }
++ }
++
++ ipu_select_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER, *buffer_num);
++
++ *buffer_num = (*buffer_num == 0) ? 1 : 0;
++
++ return 0;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n");
++
++ if (cam->dummy_frame.vaddress &&
++ cam->dummy_frame.buffer.length
++ < PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage)) {
++ dma_free_coherent(0, cam->dummy_frame.buffer.length,
++ cam->dummy_frame.vaddress,
++ cam->dummy_frame.paddress);
++ cam->dummy_frame.vaddress = 0;
++ }
++
++ if (!cam->dummy_frame.vaddress) {
++ cam->dummy_frame.vaddress = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->dummy_frame.paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->dummy_frame.vaddress == 0) {
++ pr_err("ERROR: v4l2 capture: Allocate dummy frame "
++ "failed.\n");
++ return -ENOBUFS;
++ }
++ cam->dummy_frame.buffer.length =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ }
++ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE;
++ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ csi_enc_callback, 0, "Mxc Camera", cam);
++ if (err != 0) {
++ pr_err("%s: Error requesting IPU_IRQ_CSI0_OUT_EOF\n", __func__);
++ return err;
++ }
++
++ err = csi_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "csi_enc_setup %d\n", err);
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * Disable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++static int csi_enc_disabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ int err2 = 0;
++
++ err = ipu_channel_disable(cam->ipu_chan, true);
++
++ ipu_channel_free(&cam->ipu_chan);
++
++ err2 = cam_mipi_csi2_disable(cam);
++ return err ? err : err2;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enable_csi(void *private)
++{
++ return cam_ipu_enable_csi((cam_data *)private);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++ return cam_ipu_disable_csi(cam);
++}
++
++/*!
++ * function to select CSI ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int csi_enc_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = csi_enc_eba_update;
++ cam->enc_enable = csi_enc_enabling_tasks;
++ cam->enc_disable = csi_enc_disabling_tasks;
++ cam->enc_enable_csi = csi_enc_enable_csi;
++ cam->enc_disable_csi = csi_enc_disable_csi;
++ } else {
++ err = -EIO;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(csi_enc_select);
++
++/*!
++ * function to de-select CSI ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int csi_enc_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = NULL;
++ cam->enc_enable = NULL;
++ cam->enc_disable = NULL;
++ cam->enc_enable_csi = NULL;
++ cam->enc_disable_csi = NULL;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(csi_enc_deselect);
++
++/*!
++ * Init the Encorder channels
++ *
++ * @return Error code indicating success or failure
++ */
++__init int csi_enc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit the Encorder channels
++ *
++ */
++void __exit csi_enc_exit(void)
++{
++}
++
++module_init(csi_enc_init);
++module_exit(csi_enc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("CSI ENC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c linux-3.14.72/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,580 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++/* * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_foreground_sdc.c
++ *
++ * @brief IPU Use case for PRP-VF
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/console.h>
++#include <linux/ipu.h>
++#include <linux/mxcfb.h>
++#include <linux/mipi_csi2.h>
++
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#ifdef CAMERA_DBG
++ #define CAMERA_TRACE(x) (printk)x
++#else
++ #define CAMERA_TRACE(x)
++#endif
++
++static int csi_buffer_num, buffer_num;
++static u32 csi_mem_bufsize;
++static struct ipu_soc *disp_ipu;
++static struct fb_info *fbi;
++static struct fb_var_screeninfo fbvar;
++static u32 vf_out_format;
++static void csi_buf_work_func(struct work_struct *work)
++{
++ int err = 0;
++ cam_data *cam =
++ container_of(work, struct _cam_data, csi_work_struct);
++
++ struct ipu_task task;
++ memset(&task, 0, sizeof(task));
++
++ if (csi_buffer_num)
++ task.input.paddr = cam->vf_bufs[0];
++ else
++ task.input.paddr = cam->vf_bufs[1];
++ task.input.width = cam->crop_current.width;
++ task.input.height = cam->crop_current.height;
++ task.input.format = IPU_PIX_FMT_NV12;
++
++ if (buffer_num == 0)
++ task.output.paddr = fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres);
++ else
++ task.output.paddr = fbi->fix.smem_start;
++ task.output.width = cam->win.w.width;
++ task.output.height = cam->win.w.height;
++ task.output.format = vf_out_format;
++ task.output.rotate = cam->rotation;
++again:
++ err = ipu_check_task(&task);
++ if (err != IPU_CHECK_OK) {
++ if (err > IPU_CHECK_ERR_MIN) {
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) {
++ task.input.crop.w -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) {
++ task.input.crop.h -= 8;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
++ task.output.width -= 8;
++ task.output.crop.w = task.output.width;
++ goto again;
++ }
++ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
++ task.output.height -= 8;
++ task.output.crop.h = task.output.height;
++ goto again;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ printk(KERN_ERR "check ipu taks fail\n");
++ return;
++ }
++ err = ipu_queue_task(&task);
++ if (err < 0)
++ printk(KERN_ERR "queue ipu task error\n");
++ ipu_select_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++}
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++/*!
++ * csi ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t csi_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, csi_buffer_num);
++ if ((cam->crop_current.width != cam->win.w.width) ||
++ (cam->crop_current.height != cam->win.w.height) ||
++ (vf_out_format != IPU_PIX_FMT_NV12) ||
++ (cam->rotation >= IPU_ROTATE_VERT_FLIP))
++ schedule_work(&cam->csi_work_struct);
++ csi_buffer_num = (csi_buffer_num == 0) ? 1 : 0;
++ return IRQ_HANDLED;
++}
++
++static int csi_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t params;
++ int err = 0, sensor_protocol = 0;
++
++ CAMERA_TRACE("In csi_enc_setup\n");
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++
++ memset(&params, 0, sizeof(ipu_channel_params_t));
++ params.csi_mem.csi = cam->csi;
++
++ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi);
++ switch (sensor_protocol) {
++ case IPU_CSI_CLK_MODE_GATED_CLK:
++ case IPU_CSI_CLK_MODE_NONGATED_CLK:
++ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
++ params.csi_mem.interlaced = false;
++ break;
++ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
++ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
++ params.csi_mem.interlaced = true;
++ break;
++ default:
++ printk(KERN_ERR "sensor protocol unsupported\n");
++ return -EINVAL;
++ }
++ err = cam_mipi_csi2_enable(cam, &params.csi_mem.mipi);
++ if (err)
++ return err;
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ }
++ csi_mem_bufsize = cam->crop_current.width *
++ cam->crop_current.height * 3/2;
++ cam->vf_bufs_size[0] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ (dma_addr_t *) &
++ cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_2;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(csi_mem_bufsize);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ (dma_addr_t *) &
++ cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_1;
++ }
++ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
++
++ err = ipu_channel_request(cam->ipu, CSI_MEM, &params, &cam->ipu_chan);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d\n", __func__, err);
++ goto out_1;
++ }
++
++ if ((cam->crop_current.width == cam->win.w.width) &&
++ (cam->crop_current.height == cam->win.w.height) &&
++ (vf_out_format == IPU_PIX_FMT_NV12) &&
++ (cam->rotation < IPU_ROTATE_VERT_FLIP)) {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM,
++ IPU_OUTPUT_BUFFER,
++ IPU_PIX_FMT_NV12,
++ cam->crop_current.width,
++ cam->crop_current.height,
++ cam->crop_current.width, IPU_ROTATE_NONE,
++ fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres),
++ fbi->fix.smem_start, 0,
++ cam->offset.u_offset, cam->offset.u_offset);
++ } else {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM,
++ IPU_OUTPUT_BUFFER,
++ IPU_PIX_FMT_NV12,
++ cam->crop_current.width,
++ cam->crop_current.height,
++ cam->crop_current.width, IPU_ROTATE_NONE,
++ cam->vf_bufs[0], cam->vf_bufs[1], 0,
++ cam->offset.u_offset, cam->offset.u_offset);
++ }
++ if (err != 0) {
++ printk(KERN_ERR "CSI_MEM output buffer\n");
++ goto out_1;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n");
++ goto out_1;
++ }
++
++ csi_buffer_num = 0;
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 1);
++ return err;
++out_1:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++out_2:
++ return err;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int csi_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n");
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ csi_enc_callback, 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering CSI0_OUT_EOF irq\n");
++ return err;
++ }
++
++ INIT_WORK(&cam->csi_work_struct, csi_buf_work_func);
++
++ err = csi_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "csi_enc_setup %d\n", err);
++ goto out1;
++ }
++
++ return err;
++out1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++ return err;
++}
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * foreground_start - start the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int foreground_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0, i = 0, screen_size;
++ char *base;
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already started.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ fbvar = fbi->var;
++
++ /* Store the overlay frame buffer's original std */
++ cam->fb_origin_std = fbvar.nonstd;
++
++ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) {
++ /* Use DP to do CSC so that we can get better performance */
++ vf_out_format = IPU_PIX_FMT_NV12;
++ fbvar.nonstd = vf_out_format;
++ } else {
++ vf_out_format = IPU_PIX_FMT_RGB565;
++ fbvar.nonstd = 0;
++ }
++
++ fbvar.bits_per_pixel = 16;
++ fbvar.xres = fbvar.xres_virtual = cam->win.w.width;
++ fbvar.yres = cam->win.w.height;
++ fbvar.yres_virtual = cam->win.w.height * 2;
++ fbvar.yoffset = 0;
++ fbvar.vmode &= ~FB_VMODE_YWRAP;
++ fbvar.accel_flags = FB_ACCEL_DOUBLE_FLAG;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++
++ ipu_disp_set_window_pos(disp_ipu, MEM_FG_SYNC, cam->win.w.left,
++ cam->win.w.top);
++
++ /* Fill black color for framebuffer */
++ base = (char *) fbi->screen_base;
++ screen_size = fbi->var.xres * fbi->var.yres;
++ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) {
++ memset(base, 0, screen_size);
++ base += screen_size;
++ for (i = 0; i < screen_size / 2; i++, base++)
++ *base = 0x80;
++ } else {
++ for (i = 0; i < screen_size * 2; i++, base++)
++ *base = 0x00;
++ }
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++
++ /* correct display ch buffer address */
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 0, fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres));
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 1, fbi->fix.smem_start);
++
++ err = csi_enc_enabling_tasks(cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error csi enc enable fail\n");
++ return err;
++ }
++
++ cam->overlay_active = true;
++ return err;
++
++}
++
++/*!
++ * foreground_stop - stop the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int foreground_stop(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0, i = 0;
++ int err2 = 0;
++ struct fb_info *fbi = NULL;
++ struct fb_var_screeninfo fbvar;
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ err = ipu_channel_disable(cam->ipu_chan, true);
++
++ ipu_channel_free(&cam->ipu_chan);
++
++ csi_buffer_num = 0;
++ buffer_num = 0;
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ console_unlock();
++
++ /* Set the overlay frame buffer std to what it is used to be */
++ fbvar = fbi->var;
++ fbvar.accel_flags = FB_ACCEL_TRIPLE_FLAG;
++ fbvar.nonstd = cam->fb_origin_std;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++ err2 = cam_mipi_csi2_disable(cam);
++
++ flush_work(&cam->csi_work_struct);
++ cancel_work_sync(&cam->csi_work_struct);
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++
++ cam->overlay_active = false;
++ return err ? err : err2;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int foreground_enable_csi(void *private)
++{
++ return cam_ipu_enable_csi((cam_data *)private);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int foreground_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++ return cam_ipu_disable_csi(cam);
++}
++
++/*!
++ * function to select foreground as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int foreground_sdc_select(void *private)
++{
++ cam_data *cam;
++ int err = 0;
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = foreground_start;
++ cam->vf_stop_sdc = foreground_stop;
++ cam->vf_enable_csi = foreground_enable_csi;
++ cam->vf_disable_csi = foreground_disable_csi;
++ cam->overlay_active = false;
++ } else
++ err = -EIO;
++
++ return err;
++}
++EXPORT_SYMBOL(foreground_sdc_select);
++
++/*!
++ * function to de-select foreground as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return int
++ */
++int foreground_sdc_deselect(void *private)
++{
++ cam_data *cam;
++
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(foreground_sdc_deselect);
++
++/*!
++ * Init viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int foreground_sdc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit foreground_sdc_exit(void)
++{
++}
++
++module_init(foreground_sdc_init);
++module_exit(foreground_sdc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_enc.c linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_enc.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_enc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_enc.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,538 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_enc.c
++ *
++ * @brief IPU Use case for PRP-ENC
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/ipu.h>
++#include <linux/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#ifdef CAMERA_DBG
++ #define CAMERA_TRACE(x) (printk)x
++#else
++ #define CAMERA_TRACE(x)
++#endif
++
++static ipu_rotate_mode_t grotation = IPU_ROTATE_NONE;
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * IPU ENC callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prp_enc_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ if (cam->enc_callback == NULL)
++ return IRQ_HANDLED;
++
++ cam->enc_callback(irq, dev_id);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * PrpENC enable channel setup function
++ *
++ * @param cam struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_setup(cam_data *cam)
++{
++ ipu_channel_params_t enc;
++ int err = 0;
++ dma_addr_t dummy = cam->dummy_frame.buffer.m.offset;
++
++ CAMERA_TRACE("In prp_enc_setup\n");
++ if (!cam) {
++ printk(KERN_ERR "cam private is NULL\n");
++ return -ENXIO;
++ }
++ memset(&enc, 0, sizeof(ipu_channel_params_t));
++
++ ipu_csi_get_window_size(cam->ipu, &enc.csi_prp_enc_mem.in_width,
++ &enc.csi_prp_enc_mem.in_height, cam->csi);
++
++ enc.csi_prp_enc_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
++ enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.width;
++ enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.height;
++ enc.csi_prp_enc_mem.csi = cam->csi;
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.height;
++ enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.width;
++ }
++
++ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV420P;
++ pr_info("YUV420\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YVU420P;
++ pr_info("YVU420\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV422P;
++ pr_info("YUV422P\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUYV;
++ pr_info("YUYV\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_UYVY;
++ pr_info("UYVY\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_NV12;
++ pr_info("NV12\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR24;
++ pr_info("BGR24\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB24;
++ pr_info("RGB24\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB565;
++ pr_info("RGB565\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR32;
++ pr_info("BGR32\n");
++ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) {
++ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB32;
++ pr_info("RGB32\n");
++ } else {
++ printk(KERN_ERR "format not supported\n");
++ return -EINVAL;
++ }
++ err = cam_mipi_csi2_enable(cam, &enc.csi_prp_enc_mem.mipi);
++ if (err)
++ return err;
++
++ err = ipu_channel_request(cam->ipu, CSI_PRP_ENC_MEM, &enc, &cam->ipu_chan);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d\n", __func__, err);
++ return err;
++ }
++
++ grotation = cam->rotation;
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ if (cam->rot_enc_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[0],
++ cam->rot_enc_bufs_vaddr[0],
++ cam->rot_enc_bufs[0]);
++ }
++ if (cam->rot_enc_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[1],
++ cam->rot_enc_bufs_vaddr[1],
++ cam->rot_enc_bufs[1]);
++ }
++ cam->rot_enc_buf_size[0] =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->rot_enc_bufs_vaddr[0] =
++ (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[0],
++ &cam->rot_enc_bufs[0],
++ GFP_DMA | GFP_KERNEL);
++ if (!cam->rot_enc_bufs_vaddr[0]) {
++ printk(KERN_ERR "alloc enc_bufs0\n");
++ return -ENOMEM;
++ }
++ cam->rot_enc_buf_size[1] =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->rot_enc_bufs_vaddr[1] =
++ (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[1],
++ &cam->rot_enc_bufs[1],
++ GFP_DMA | GFP_KERNEL);
++ if (!cam->rot_enc_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[0],
++ cam->rot_enc_bufs_vaddr[0],
++ cam->rot_enc_bufs[0]);
++ cam->rot_enc_bufs_vaddr[0] = NULL;
++ cam->rot_enc_bufs[0] = 0;
++ printk(KERN_ERR "alloc enc_bufs1\n");
++ return -ENOMEM;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_width,
++ enc.csi_prp_enc_mem.out_height,
++ enc.csi_prp_enc_mem.out_width,
++ IPU_ROTATE_NONE,
++ cam->rot_enc_bufs[0],
++ cam->rot_enc_bufs[1], 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_PRP_ENC_MEM err\n");
++ return err;
++ }
++
++ err = ipu_channel_request(cam->ipu, MEM_ROT_ENC_MEM, NULL, &cam->ipu_chan_rot);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d for rot\n", __func__, err);
++ return err;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_ENC_MEM,
++ IPU_INPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_width,
++ enc.csi_prp_enc_mem.out_height,
++ enc.csi_prp_enc_mem.out_width,
++ cam->rotation,
++ cam->rot_enc_bufs[0],
++ cam->rot_enc_bufs[1], 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "MEM_ROT_ENC_MEM input buffer\n");
++ return err;
++ }
++
++ err =
++ ipu_init_channel_buffer(cam->ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_height,
++ enc.csi_prp_enc_mem.out_width,
++ cam->v2f.fmt.pix.bytesperline /
++ bytes_per_pixel(enc.csi_prp_enc_mem.
++ out_pixel_fmt),
++ IPU_ROTATE_NONE,
++ dummy, dummy, 0,
++ cam->offset.u_offset,
++ cam->offset.v_offset);
++ if (err != 0) {
++ printk(KERN_ERR "MEM_ROT_ENC_MEM output buffer\n");
++ return err;
++ }
++
++ err = ipu_link_channels(cam->ipu,
++ CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR
++ "link CSI_PRP_ENC_MEM-MEM_ROT_ENC_MEM\n");
++ return err;
++ }
++
++ err = ipu_enable_channel(cam->ipu, CSI_PRP_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n");
++ return err;
++ }
++ err = ipu_enable_channel(cam->ipu, MEM_ROT_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel MEM_ROT_ENC_MEM\n");
++ return err;
++ }
++
++ ipu_select_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER, 1);
++ } else {
++ err =
++ ipu_init_channel_buffer(cam->ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ enc.csi_prp_enc_mem.out_pixel_fmt,
++ enc.csi_prp_enc_mem.out_width,
++ enc.csi_prp_enc_mem.out_height,
++ cam->v2f.fmt.pix.bytesperline /
++ bytes_per_pixel(enc.csi_prp_enc_mem.
++ out_pixel_fmt),
++ cam->rotation,
++ dummy, dummy, 0,
++ cam->offset.u_offset,
++ cam->offset.v_offset);
++ if (err != 0) {
++ printk(KERN_ERR "CSI_PRP_ENC_MEM output buffer\n");
++ return err;
++ }
++ err = ipu_enable_channel(cam->ipu, CSI_PRP_ENC_MEM);
++ if (err < 0) {
++ printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n");
++ return err;
++ }
++ }
++
++ return err;
++}
++
++/*!
++ * function to update physical buffer address for encorder IDMA channel
++ *
++ * @param eba physical buffer address for encorder IDMA channel
++ * @param buffer_num int buffer 0 or buffer 1
++ *
++ * @return status
++ */
++static int prp_enc_eba_update(struct ipu_soc *ipu, dma_addr_t eba,
++ int *buffer_num)
++{
++ int err = 0;
++
++ pr_debug("eba %x\n", eba);
++ if (grotation >= IPU_ROTATE_90_RIGHT) {
++ err = ipu_update_channel_buffer(ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER, *buffer_num,
++ eba);
++ } else {
++ err = ipu_update_channel_buffer(ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER, *buffer_num,
++ eba);
++ }
++ if (err != 0) {
++ if (grotation >= IPU_ROTATE_90_RIGHT) {
++ ipu_clear_buffer_ready(ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ err = ipu_update_channel_buffer(ipu, MEM_ROT_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num,
++ eba);
++ } else {
++ ipu_clear_buffer_ready(ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ err = ipu_update_channel_buffer(ipu, CSI_PRP_ENC_MEM,
++ IPU_OUTPUT_BUFFER,
++ *buffer_num,
++ eba);
++ }
++
++ if (err != 0) {
++ pr_err("ERROR: v4l2 capture: fail to update "
++ "buf%d\n", *buffer_num);
++ return err;
++ }
++ }
++
++ if (grotation >= IPU_ROTATE_90_RIGHT) {
++ ipu_select_buffer(ipu, MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ } else {
++ ipu_select_buffer(ipu, CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER,
++ *buffer_num);
++ }
++
++ *buffer_num = (*buffer_num == 0) ? 1 : 0;
++ return 0;
++}
++
++/*!
++ * Enable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_enabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ int irq;
++ CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n");
++
++ cam->dummy_frame.vaddress = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->dummy_frame.paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->dummy_frame.vaddress == 0) {
++ pr_err("ERROR: v4l2 capture: Allocate dummy frame "
++ "failed.\n");
++ return -ENOBUFS;
++ }
++ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE;
++ cam->dummy_frame.buffer.length =
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
++ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
++
++ irq = (cam->rotation >= IPU_ROTATE_90_RIGHT) ?
++ IPU_IRQ_PRP_ENC_ROT_OUT_EOF : IPU_IRQ_PRP_ENC_OUT_EOF;
++ err = ipu_request_irq(cam->ipu, irq,
++ prp_enc_callback, 0, "Mxc Camera", cam);
++ if (err) {
++ pr_err("%s: Error requesting irq=%d\n", __func__, irq);
++ return err;
++ }
++
++ err = prp_enc_setup(cam);
++ if (err != 0) {
++ printk(KERN_ERR "prp_enc_setup %d\n", err);
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * Disable encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++static int prp_enc_disabling_tasks(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++ int err2 = 0;
++ int err3 = 0;
++
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF, cam);
++ ipu_unlink_channels(cam->ipu, CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM);
++ }
++
++ err = ipu_channel_disable(cam->ipu_chan, true);
++ err2 = ipu_channel_disable(cam->ipu_chan_rot, true);
++
++ ipu_channel_free(&cam->ipu_chan);
++ ipu_channel_free(&cam->ipu_chan_rot);
++
++ if (cam->dummy_frame.vaddress != 0) {
++ dma_free_coherent(0, cam->dummy_frame.buffer.length,
++ cam->dummy_frame.vaddress,
++ cam->dummy_frame.paddress);
++ cam->dummy_frame.vaddress = 0;
++ }
++ err3 = cam_mipi_csi2_disable(cam);
++ return err ? err : (err2 ? err2 : err3);
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_enable_csi(void *private)
++{
++ return cam_ipu_enable_csi((cam_data *)private);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_enc_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ if (cam->rotation < IPU_ROTATE_90_RIGHT)
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF, cam);
++ return cam_ipu_disable_csi(cam);
++}
++
++/*!
++ * function to select PRP-ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int prp_enc_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = prp_enc_eba_update;
++ cam->enc_enable = prp_enc_enabling_tasks;
++ cam->enc_disable = prp_enc_disabling_tasks;
++ cam->enc_enable_csi = prp_enc_enable_csi;
++ cam->enc_disable_csi = prp_enc_disable_csi;
++ } else {
++ err = -EIO;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(prp_enc_select);
++
++/*!
++ * function to de-select PRP-ENC as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return int
++ */
++int prp_enc_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ if (cam) {
++ cam->enc_update_eba = NULL;
++ cam->enc_enable = NULL;
++ cam->enc_disable = NULL;
++ cam->enc_enable_csi = NULL;
++ cam->enc_disable_csi = NULL;
++ if (cam->rot_enc_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[0],
++ cam->rot_enc_bufs_vaddr[0],
++ cam->rot_enc_bufs[0]);
++ cam->rot_enc_bufs_vaddr[0] = NULL;
++ cam->rot_enc_bufs[0] = 0;
++ }
++ if (cam->rot_enc_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_enc_buf_size[1],
++ cam->rot_enc_bufs_vaddr[1],
++ cam->rot_enc_bufs[1]);
++ cam->rot_enc_bufs_vaddr[1] = NULL;
++ cam->rot_enc_bufs[1] = 0;
++ }
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(prp_enc_deselect);
++
++/*!
++ * Init the Encorder channels
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_enc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit the Encorder channels
++ *
++ */
++void __exit prp_enc_exit(void)
++{
++}
++
++module_init(prp_enc_init);
++module_exit(prp_enc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP ENC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_sw.h linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_sw.h
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_sw.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_sw.h 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,43 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_sw.h
++ *
++ * @brief This file contains the IPU PRP use case driver header.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef _INCLUDE_IPU__PRP_SW_H_
++#define _INCLUDE_IPU__PRP_SW_H_
++
++int csi_enc_select(void *private);
++int csi_enc_deselect(void *private);
++int prp_enc_select(void *private);
++int prp_enc_deselect(void *private);
++#ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++int prp_vf_sdc_select(void *private);
++int prp_vf_sdc_deselect(void *private);
++int prp_vf_sdc_select_bg(void *private);
++int prp_vf_sdc_deselect_bg(void *private);
++#else
++int foreground_sdc_select(void *private);
++int foreground_sdc_deselect(void *private);
++int bg_overlay_sdc_select(void *private);
++int bg_overlay_sdc_deselect(void *private);
++#endif
++int prp_still_select(void *private);
++int prp_still_deselect(void *private);
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,472 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_vf_sdc_bg.c
++ *
++ * @brief IPU Use case for PRP-VF back-ground
++ *
++ * @ingroup IPU
++ */
++#include <linux/dma-mapping.h>
++#include <linux/fb.h>
++#include <linux/ipu.h>
++#include <linux/module.h>
++#include <mach/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int buffer_num;
++static int buffer_ready;
++static struct ipu_soc *disp_ipu;
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++/*
++ * Function definitions
++ */
++
++/*!
++ * SDC V-Sync callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prpvf_sdc_vsync_callback(int irq, void *dev_id)
++{
++ cam_data *cam = dev_id;
++ if (buffer_ready > 0) {
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ buffer_ready--;
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * VF EOF callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prpvf_vf_eof_callback(int irq, void *dev_id)
++{
++ cam_data *cam = dev_id;
++ pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num);
++
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++ buffer_ready++;
++ return IRQ_HANDLED;
++}
++
++/*!
++ * prpvf_start - start the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ ipu_channel_params_t vf;
++ u32 format;
++ u32 offset;
++ u32 bpp, size = 3;
++ int err = 0;
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already start.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ format = cam->v4l2_fb.fmt.pixelformat;
++ if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) {
++ bpp = 3, size = 3;
++ pr_info("BGR24\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) {
++ bpp = 2, size = 2;
++ pr_info("RGB565\n");
++ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) {
++ bpp = 4, size = 4;
++ pr_info("BGR32\n");
++ } else {
++ printk(KERN_ERR
++ "unsupported fix format from the framebuffer.\n");
++ return -EINVAL;
++ }
++
++ offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top +
++ size * cam->win.w.left;
++
++ if (cam->v4l2_fb.base == 0)
++ printk(KERN_ERR "invalid frame buffer address.\n");
++ else
++ offset += (u32) cam->v4l2_fb.base;
++
++ memset(&vf, 0, sizeof(ipu_channel_params_t));
++ ipu_csi_get_window_size(cam->ipu, &vf.csi_prp_vf_mem.in_width,
++ &vf.csi_prp_vf_mem.in_height, cam->csi);
++ vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
++ vf.csi_prp_vf_mem.out_width = cam->win.w.width;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.height;
++ vf.csi_prp_vf_mem.csi = cam->csi;
++ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
++ vf.csi_prp_vf_mem.out_width = cam->win.w.height;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.width;
++ }
++ vf.csi_prp_vf_mem.out_pixel_fmt = format;
++ size = cam->win.w.width * cam->win.w.height * size;
++
++ err = cam_mipi_csi2_enable(cam, &vf.csi_prp_vf_mem.mipi);
++ if (err)
++ return err;
++
++ err = ipu_channel_request(cam->ipu, CSI_PRP_VF_MEM, &vf, &cam->ipu_chan);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d\n", __func__, err);
++ goto out_4;
++ }
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ }
++ cam->vf_bufs_size[0] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ &cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_3;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ &cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_3;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ format, vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ IPU_ROTATE_NONE,
++ cam->vf_bufs[0],
++ cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n");
++ goto out_3;
++ }
++ err = ipu_channel_request(cam->ipu, MEM_ROT_VF_MEM, NULL, &cam->ipu_chan_rot);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d for rot\n", __func__, err);
++ goto out_3;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_INPUT_BUFFER,
++ format, vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ cam->vf_rotation,
++ cam->vf_bufs[0],
++ cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n");
++ goto out_2;
++ }
++
++ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ format,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ cam->overlay_fb->var.xres * bpp,
++ IPU_ROTATE_NONE,
++ offset, 0, 0, 0, 0);
++
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
++ goto out_2;
++ }
++ } else {
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ format,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ cam->overlay_fb->var.xres * bpp,
++ IPU_ROTATE_NONE,
++ offset, 0, 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
++ goto out_2;
++ }
++ }
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF,
++ prpvf_vf_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR
++ "Error registering IPU_IRQ_PRP_VF_OUT_EOF irq.\n");
++ goto out_2;
++ }
++
++ ipu_clear_irq(disp_ipu, IPU_IRQ_BG_SF_END);
++ err = ipu_request_irq(disp_ipu, IPU_IRQ_BG_SF_END,
++ prpvf_sdc_vsync_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering IPU_IRQ_BG_SF_END irq.\n");
++ goto out_1;
++ }
++
++ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM);
++ ipu_enable_channel(cam->ipu, MEM_ROT_VF_MEM);
++
++ buffer_num = 0;
++ buffer_ready = 0;
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0);
++
++ cam->overlay_active = true;
++ return err;
++
++out_1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL);
++out_2:
++ ipu_channel_free(&cam->ipu_chan_rot);
++out_3:
++ ipu_channel_free(&cam->ipu_chan);
++out_4:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[0],
++ cam->rot_vf_bufs_vaddr[0],
++ cam->rot_vf_bufs[0]);
++ cam->rot_vf_bufs_vaddr[0] = NULL;
++ cam->rot_vf_bufs[0] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[1],
++ cam->rot_vf_bufs_vaddr[1],
++ cam->rot_vf_bufs[1]);
++ cam->rot_vf_bufs_vaddr[1] = NULL;
++ cam->rot_vf_bufs[1] = 0;
++ }
++ return err;
++}
++
++/*!
++ * prpvf_stop - stop the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_stop(void *private)
++{
++ int err = 0;
++ cam_data *cam = (cam_data *) private;
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ ipu_free_irq(disp_ipu, IPU_IRQ_BG_SF_END, cam);
++
++ ipu_channel_disable(cam->ipu_chan, true);
++ ipu_channel_disable(cam->ipu_chan_rot, true);
++ ipu_channel_free(&cam->ipu_chan);
++ ipu_channel_free(&cam->ipu_chan_rot);
++
++ err = cam_mipi_csi2_disable(cam);
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[0],
++ cam->rot_vf_bufs_vaddr[0],
++ cam->rot_vf_bufs[0]);
++ cam->rot_vf_bufs_vaddr[0] = NULL;
++ cam->rot_vf_bufs[0] = 0;
++ }
++ if (cam->rot_vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->rot_vf_buf_size[1],
++ cam->rot_vf_bufs_vaddr[1],
++ cam->rot_vf_bufs[1]);
++ cam->rot_vf_bufs_vaddr[1] = NULL;
++ cam->rot_vf_bufs[1] = 0;
++ }
++
++ buffer_num = 0;
++ buffer_ready = 0;
++ cam->overlay_active = false;
++ return err;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_enable_csi(void *private)
++{
++ return cam_ipu_enable_csi((cam_data *)private);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam);
++ return cam_ipu_disable_csi(cam);
++}
++
++/*!
++ * function to select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int prp_vf_sdc_select_bg(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = prpvf_start;
++ cam->vf_stop_sdc = prpvf_stop;
++ cam->vf_enable_csi = prp_vf_enable_csi;
++ cam->vf_disable_csi = prp_vf_disable_csi;
++ cam->overlay_active = false;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(prp_vf_sdc_select_bg);
++
++/*!
++ * function to de-select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int prp_vf_sdc_deselect_bg(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(prp_vf_sdc_deselect_bg);
++
++/*!
++ * Init viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_vf_sdc_init_bg(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit prp_vf_sdc_exit_bg(void)
++{
++}
++
++module_init(prp_vf_sdc_init_bg);
++module_exit(prp_vf_sdc_exit_bg);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,528 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++/* * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_prp_vf_sdc.c
++ *
++ * @brief IPU Use case for PRP-VF
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/console.h>
++#include <linux/ipu.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <mach/hardware.h>
++#include <mach/mipi_csi2.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int buffer_num;
++static struct ipu_soc *disp_ipu;
++
++static void get_disp_ipu(cam_data *cam)
++{
++ if (cam->output > 2)
++ disp_ipu = ipu_get_soc(1); /* using DISP4 */
++ else
++ disp_ipu = ipu_get_soc(0);
++}
++
++static irqreturn_t prpvf_rot_eof_callback(int irq, void *dev_id)
++{
++ cam_data *cam = dev_id;
++ pr_debug("buffer_num %d\n", buffer_num);
++
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
++ ipu_select_buffer(disp_ipu, MEM_FG_SYNC,
++ IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++ } else {
++ ipu_select_buffer(disp_ipu, MEM_FG_SYNC,
++ IPU_INPUT_BUFFER, buffer_num);
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++ }
++ return IRQ_HANDLED;
++}
++/*
++ * Function definitions
++ */
++
++/*!
++ * prpvf_start - start the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_start(void *private)
++{
++ struct fb_var_screeninfo fbvar;
++ struct fb_info *fbi = NULL;
++ cam_data *cam = (cam_data *) private;
++ ipu_channel_params_t vf;
++ u32 vf_out_format = 0;
++ u32 size = 2, temp = 0;
++ int err = 0, i = 0;
++ short *tmp, color;
++
++ if (!cam) {
++ printk(KERN_ERR "private is NULL\n");
++ return -EIO;
++ }
++
++ if (cam->overlay_active == true) {
++ pr_debug("already started.\n");
++ return 0;
++ }
++
++ get_disp_ipu(cam);
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ fbvar = fbi->var;
++
++ /* Store the overlay frame buffer's original std */
++ cam->fb_origin_std = fbvar.nonstd;
++
++ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) {
++ /* Use DP to do CSC so that we can get better performance */
++ vf_out_format = IPU_PIX_FMT_UYVY;
++ fbvar.nonstd = vf_out_format;
++ color = 0x80;
++ } else {
++ vf_out_format = IPU_PIX_FMT_RGB565;
++ fbvar.nonstd = 0;
++ color = 0x0;
++ }
++
++ fbvar.bits_per_pixel = 16;
++ fbvar.xres = fbvar.xres_virtual = cam->win.w.width;
++ fbvar.yres = cam->win.w.height;
++ fbvar.yres_virtual = cam->win.w.height * 2;
++ fbvar.yoffset = 0;
++ fbvar.accel_flags = FB_ACCEL_DOUBLE_FLAG;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++
++ ipu_disp_set_window_pos(disp_ipu, MEM_FG_SYNC, cam->win.w.left,
++ cam->win.w.top);
++
++ /* Fill black color for framebuffer */
++ tmp = (short *) fbi->screen_base;
++ for (i = 0; i < (fbi->fix.line_length * fbi->var.yres)/2;
++ i++, tmp++)
++ *tmp = color;
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++
++ /* correct display ch buffer address */
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 0, fbi->fix.smem_start +
++ (fbi->fix.line_length * fbvar.yres));
++ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER,
++ 1, fbi->fix.smem_start);
++
++ memset(&vf, 0, sizeof(ipu_channel_params_t));
++ ipu_csi_get_window_size(cam->ipu, &vf.csi_prp_vf_mem.in_width,
++ &vf.csi_prp_vf_mem.in_height, cam->csi);
++ vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY;
++ vf.csi_prp_vf_mem.out_width = cam->win.w.width;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.height;
++ vf.csi_prp_vf_mem.csi = cam->csi;
++ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) {
++ vf.csi_prp_vf_mem.out_width = cam->win.w.height;
++ vf.csi_prp_vf_mem.out_height = cam->win.w.width;
++ }
++ vf.csi_prp_vf_mem.out_pixel_fmt = vf_out_format;
++ size = cam->win.w.width * cam->win.w.height * size;
++
++ err = cam_mipi_csi2_enable(cam, &vf.csi_prp_vf_mem.mipi);
++ if (err)
++ return err;
++
++ err = ipu_channel_request(cam->ipu, CSI_PRP_VF_MEM, &vf, &cam->ipu_chan);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d\n", __func__, err);
++ goto out_5;
++ }
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ }
++ cam->vf_bufs_size[0] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[0],
++ (dma_addr_t *) &
++ cam->vf_bufs[0],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[0] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_4;
++ }
++ cam->vf_bufs_size[1] = PAGE_ALIGN(size);
++ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0,
++ cam->vf_bufs_size[1],
++ (dma_addr_t *) &
++ cam->vf_bufs[1],
++ GFP_DMA |
++ GFP_KERNEL);
++ if (cam->vf_bufs_vaddr[1] == NULL) {
++ printk(KERN_ERR "Error to allocate vf buffer\n");
++ err = -ENOMEM;
++ goto out_3;
++ }
++ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]);
++
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ vf_out_format,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ IPU_ROTATE_NONE,
++ cam->vf_bufs[0], cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0)
++ goto out_3;
++
++ err = ipu_channel_request(cam->ipu, MEM_ROT_VF_MEM, NULL, &cam->ipu_chan_rot);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d for rot\n", __func__, err);
++ goto out_3;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_INPUT_BUFFER,
++ vf_out_format,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ cam->vf_rotation,
++ cam->vf_bufs[0],
++ cam->vf_bufs[1],
++ 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n");
++ goto out_2;
++ }
++
++ if (cam->vf_rotation < IPU_ROTATE_90_RIGHT) {
++ temp = vf.csi_prp_vf_mem.out_width;
++ vf.csi_prp_vf_mem.out_width =
++ vf.csi_prp_vf_mem.out_height;
++ vf.csi_prp_vf_mem.out_height = temp;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ vf_out_format,
++ vf.csi_prp_vf_mem.out_height,
++ vf.csi_prp_vf_mem.out_width,
++ vf.csi_prp_vf_mem.out_height,
++ IPU_ROTATE_NONE,
++ fbi->fix.smem_start +
++ (fbi->fix.line_length *
++ fbi->var.yres),
++ fbi->fix.smem_start, 0, 0, 0);
++
++ if (err != 0) {
++ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n");
++ goto out_2;
++ }
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF,
++ prpvf_rot_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err < 0) {
++ printk(KERN_ERR "Error request irq:IPU_IRQ_PRP_VF_ROT_OUT_EOF\n");
++ goto out_2;
++ }
++
++ err = ipu_link_channels(cam->ipu,
++ CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
++ if (err < 0) {
++ printk(KERN_ERR
++ "Error link CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n");
++ goto out_1;
++ }
++
++ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM);
++ ipu_enable_channel(cam->ipu, MEM_ROT_VF_MEM);
++
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, 1);
++ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ } else {
++ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER,
++ vf_out_format, cam->win.w.width,
++ cam->win.w.height,
++ cam->win.w.width,
++ cam->vf_rotation,
++ fbi->fix.smem_start +
++ (fbi->fix.line_length *
++ fbi->var.yres),
++ fbi->fix.smem_start, 0, 0, 0);
++ if (err != 0) {
++ printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n");
++ goto out_4;
++ }
++ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF,
++ prpvf_rot_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err < 0) {
++ printk(KERN_ERR "Error request irq:IPU_IRQ_PRP_VF_OUT_EOF\n");
++ goto out_4;
++ }
++
++ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM);
++
++ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM,
++ IPU_OUTPUT_BUFFER, 0);
++ }
++
++ cam->overlay_active = true;
++ return err;
++
++out_1:
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL);
++out_2:
++ ipu_channel_free(&cam->ipu_chan_rot);
++out_3:
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++out_4:
++ ipu_channel_free(&cam->ipu_chan);
++out_5:
++ return err;
++}
++
++/*!
++ * prpvf_stop - stop the vf task
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ */
++static int prpvf_stop(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0, i = 0;
++ int err2;
++ struct fb_info *fbi = NULL;
++ struct fb_var_screeninfo fbvar;
++
++ if (cam->overlay_active == false)
++ return 0;
++
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) ||
++ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++
++ if (fbi == NULL) {
++ printk(KERN_ERR "DISP FG fb not found\n");
++ return -EPERM;
++ }
++
++ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) {
++ ipu_unlink_channels(cam->ipu, CSI_PRP_VF_MEM, MEM_ROT_VF_MEM);
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF, cam);
++ }
++ buffer_num = 0;
++
++ ipu_channel_disable(cam->ipu_chan, true);
++ ipu_channel_disable(cam->ipu_chan_rot, true);
++ ipu_channel_free(&cam->ipu_chan_rot);
++ ipu_channel_free(&cam->ipu_chan);
++
++ console_lock();
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ console_unlock();
++
++ /* Set the overlay frame buffer std to what it is used to be */
++ fbvar = fbi->var;
++ fbvar.accel_flags = FB_ACCEL_TRIPLE_FLAG;
++ fbvar.nonstd = cam->fb_origin_std;
++ fbvar.activate |= FB_ACTIVATE_FORCE;
++ fb_set_var(fbi, &fbvar);
++ err2 = cam_mipi_csi2_disable(cam);
++
++ if (cam->vf_bufs_vaddr[0]) {
++ dma_free_coherent(0, cam->vf_bufs_size[0],
++ cam->vf_bufs_vaddr[0],
++ (dma_addr_t) cam->vf_bufs[0]);
++ cam->vf_bufs_vaddr[0] = NULL;
++ cam->vf_bufs[0] = 0;
++ }
++ if (cam->vf_bufs_vaddr[1]) {
++ dma_free_coherent(0, cam->vf_bufs_size[1],
++ cam->vf_bufs_vaddr[1],
++ (dma_addr_t) cam->vf_bufs[1]);
++ cam->vf_bufs_vaddr[1] = NULL;
++ cam->vf_bufs[1] = 0;
++ }
++
++ cam->overlay_active = false;
++ return err ? err : err2;
++}
++
++/*!
++ * Enable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_enable_csi(void *private)
++{
++ return cam_ipu_enable_csi((cam_data *)private);
++}
++
++/*!
++ * Disable csi
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_vf_disable_csi(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ /* free csi eof irq firstly.
++ * when disable csi, wait for idmac eof.
++ * it requests eof irq again */
++ if (cam->vf_rotation < IPU_ROTATE_VERT_FLIP)
++ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam);
++ return cam_ipu_disable_csi(cam);
++}
++
++/*!
++ * function to select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return status
++ */
++int prp_vf_sdc_select(void *private)
++{
++ cam_data *cam;
++ int err = 0;
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = prpvf_start;
++ cam->vf_stop_sdc = prpvf_stop;
++ cam->vf_enable_csi = prp_vf_enable_csi;
++ cam->vf_disable_csi = prp_vf_disable_csi;
++ cam->overlay_active = false;
++ } else
++ err = -EIO;
++
++ return err;
++}
++EXPORT_SYMBOL(prp_vf_sdc_select);
++
++/*!
++ * function to de-select PRP-VF as the working path
++ *
++ * @param private cam_data * mxc v4l2 main structure
++ *
++ * @return int
++ */
++int prp_vf_sdc_deselect(void *private)
++{
++ cam_data *cam;
++
++ if (private) {
++ cam = (cam_data *) private;
++ cam->vf_start_sdc = NULL;
++ cam->vf_stop_sdc = NULL;
++ cam->vf_enable_csi = NULL;
++ cam->vf_disable_csi = NULL;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(prp_vf_sdc_deselect);
++
++/*!
++ * Init viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_vf_sdc_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit viewfinder task.
++ *
++ * @return Error code indicating success or failure
++ */
++void __exit prp_vf_sdc_exit(void)
++{
++}
++
++module_init(prp_vf_sdc_init);
++module_exit(prp_vf_sdc_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP VF SDC Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_still.c linux-3.14.72/drivers/media/platform/mxc/capture/ipu_still.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ipu_still.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ipu_still.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,269 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_still.c
++ *
++ * @brief IPU Use case for still image capture
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/module.h>
++#include <linux/semaphore.h>
++#include <linux/sched.h>
++#include <linux/ipu.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++static int callback_eof_flag;
++#ifndef CONFIG_MXC_IPU_V1
++static int buffer_num;
++#endif
++
++#ifdef CONFIG_MXC_IPU_V1
++static int callback_flag;
++/*
++ * Function definitions
++ */
++/*!
++ * CSI EOF callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prp_csi_eof_callback(int irq, void *dev_id)
++{
++ cam_data *cam = devid;
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ callback_flag%2 ? 1 : 0);
++ if (callback_flag == 0)
++ ipu_enable_channel(cam->ipu, CSI_MEM);
++
++ callback_flag++;
++ return IRQ_HANDLED;
++}
++#endif
++
++/*!
++ * CSI callback function.
++ *
++ * @param irq int irq line
++ * @param dev_id void * device id
++ *
++ * @return status IRQ_HANDLED for handled
++ */
++static irqreturn_t prp_still_callback(int irq, void *dev_id)
++{
++ cam_data *cam = (cam_data *) dev_id;
++
++ callback_eof_flag++;
++ if (callback_eof_flag < 5) {
++#ifndef CONFIG_MXC_IPU_V1
++ buffer_num = (buffer_num == 0) ? 1 : 0;
++ ipu_select_buffer(cam->ipu, CSI_MEM,
++ IPU_OUTPUT_BUFFER, buffer_num);
++#endif
++ } else {
++ cam->still_counter++;
++ wake_up_interruptible(&cam->still_queue);
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * start csi->mem task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_still_start(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ u32 pixel_fmt;
++ int err;
++ ipu_channel_params_t params;
++
++ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
++ pixel_fmt = IPU_PIX_FMT_YUV420P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12)
++ pixel_fmt = IPU_PIX_FMT_NV12;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P)
++ pixel_fmt = IPU_PIX_FMT_YUV422P;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY)
++ pixel_fmt = IPU_PIX_FMT_UYVY;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV)
++ pixel_fmt = IPU_PIX_FMT_YUYV;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24)
++ pixel_fmt = IPU_PIX_FMT_BGR24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24)
++ pixel_fmt = IPU_PIX_FMT_RGB24;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565)
++ pixel_fmt = IPU_PIX_FMT_RGB565;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32)
++ pixel_fmt = IPU_PIX_FMT_BGR32;
++ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32)
++ pixel_fmt = IPU_PIX_FMT_RGB32;
++ else {
++ printk(KERN_ERR "format not supported\n");
++ return -EINVAL;
++ }
++
++ memset(&params, 0, sizeof(params));
++ err = ipu_channel_request(cam->ipu, CSI_MEM, &params, &cam->ipu_chan);
++ if (err) {
++ pr_err("%s:ipu_channel_request %d\n", __func__, err);
++ return err;
++ }
++
++ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER,
++ pixel_fmt, cam->v2f.fmt.pix.width,
++ cam->v2f.fmt.pix.height,
++ cam->v2f.fmt.pix.width, IPU_ROTATE_NONE,
++ cam->still_buf[0], cam->still_buf[1], 0,
++ 0, 0);
++ if (err != 0)
++ return err;
++
++#ifdef CONFIG_MXC_IPU_V1
++ ipu_clear_irq(IPU_IRQ_SENSOR_OUT_EOF);
++ err = ipu_request_irq(IPU_IRQ_SENSOR_OUT_EOF, prp_still_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering irq.\n");
++ return err;
++ }
++ callback_flag = 0;
++ callback_eof_flag = 0;
++ ipu_clear_irq(IPU_IRQ_SENSOR_EOF);
++ err = ipu_request_irq(IPU_IRQ_SENSOR_EOF, prp_csi_eof_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error IPU_IRQ_SENSOR_EOF\n");
++ return err;
++ }
++#else
++ callback_eof_flag = 0;
++ buffer_num = 0;
++
++ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF);
++ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF,
++ prp_still_callback,
++ 0, "Mxc Camera", cam);
++ if (err != 0) {
++ printk(KERN_ERR "Error registering irq.\n");
++ return err;
++ }
++
++ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0);
++ ipu_enable_channel(cam->ipu, CSI_MEM);
++ cam_ipu_enable_csi(cam);
++#endif
++
++ return err;
++}
++
++/*!
++ * stop csi->mem encoder task
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++static int prp_still_stop(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++#ifdef CONFIG_MXC_IPU_V1
++ ipu_free_irq(IPU_IRQ_SENSOR_EOF, NULL);
++ ipu_free_irq(IPU_IRQ_SENSOR_OUT_EOF, cam);
++#else
++ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam);
++#endif
++
++ cam_ipu_disable_csi(cam);
++ ipu_channel_disable(cam->ipu_chan, true);
++ ipu_channel_free(&cam->ipu_chan);
++ return err;
++}
++
++/*!
++ * function to select CSI_MEM as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++int prp_still_select(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++
++ if (cam) {
++ cam->csi_start = prp_still_start;
++ cam->csi_stop = prp_still_stop;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(prp_still_select);
++
++/*!
++ * function to de-select CSI_MEM as the working path
++ *
++ * @param private struct cam_data * mxc capture instance
++ *
++ * @return status
++ */
++int prp_still_deselect(void *private)
++{
++ cam_data *cam = (cam_data *) private;
++ int err = 0;
++
++ err = prp_still_stop(cam);
++
++ if (cam) {
++ cam->csi_start = NULL;
++ cam->csi_stop = NULL;
++ }
++
++ return err;
++}
++EXPORT_SYMBOL(prp_still_deselect);
++
++/*!
++ * Init the Encorder channels
++ *
++ * @return Error code indicating success or failure
++ */
++__init int prp_still_init(void)
++{
++ return 0;
++}
++
++/*!
++ * Deinit the Encorder channels
++ *
++ */
++void __exit prp_still_exit(void)
++{
++}
++
++module_init(prp_still_init);
++module_exit(prp_still_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IPU PRP STILL IMAGE Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/Kconfig linux-3.14.72/drivers/media/platform/mxc/capture/Kconfig
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/Kconfig 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,108 @@
++if VIDEO_MXC_CAPTURE
++config VIDEO_V4L2_MXC_INT_DEVICE
++ tristate
++
++menu "MXC Camera/V4L2 PRP Features support"
++config VIDEO_MXC_IPU_CAMERA
++ bool
++ select VIDEO_V4L2_MXC_INT_DEVICE
++ select MXC_IPU_CSI_ENC
++ select MXC_IPU_PRP_ENC
++ depends on VIDEO_MXC_CAPTURE && MXC_IPU
++ default y
++
++config MXC_TVIN_TDA1997X
++ tristate "NXP TDA1997x HDMI Receiver Input support"
++ depends on I2C
++ ---help---
++ If you plan to use the NXP tda1997x/tdf1997x HDMI reciever with your i
++
++config MXC_CAMERA_OV5640
++ tristate "OmniVision ov5640 camera support"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the ov5640 Camera with your MXC system, say Y here.
++
++config MXC_CAMERA_OV5642
++ tristate "OmniVision ov5642 camera support"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the ov5642 Camera with your MXC system, say Y here.
++
++config MXC_CAMERA_OV5640_MIPI
++ tristate "OmniVision ov5640 camera support using mipi"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ select MXC_MIPI_CSI2
++ select VIDEO_V4L2_MXC_INT_DEVICE
++ ---help---
++ If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here.
++
++config MXC_CAMERA_OV5647_MIPI
++ tristate "OmniVision ov5647 camera support using mipi"
++ depends on MXC_MIPI_CSI2
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the ov5647 Camera with mipi interface in your MXC system, say Y here.
++
++config MXC_HDMI_CSI2_TC358743
++ tristate "Toshiba tc358743 Hdmi to CSI 2 bridge"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ select MXC_MIPI_CSI2 if ARCH_MX6Q
++ select MXC_CAMERA_SENSOR_CLK
++ ---help---
++ Toshina HDMI to MIPI-CSI2 bridge
++
++config MXC_TVIN_ADV7180
++ tristate "Analog Device adv7180 TV Decoder Input support"
++ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
++ ---help---
++ If you plan to use the adv7180 video decoder with your MXC system, say Y here.
++
++choice
++ prompt "Select Overlay Rounting"
++ default MXC_IPU_DEVICE_QUEUE_SDC
++ depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_SYNC_PANEL
++
++config MXC_IPU_DEVICE_QUEUE_SDC
++ tristate "Queue ipu device for overlay library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ ---help---
++ Use case CSI->MEM->IPU DEVICE->SDC:
++ Images from sensor will be frist recieved in memory,then
++ queue to ipu device for processing if needed, and displaying
++ it on synchronous display with SDC use case.
++
++config MXC_IPU_PRP_VF_SDC
++ bool "Pre-Processor VF SDC library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ ---help---
++ Use case PRP_VF_SDC:
++ Preprocessing image from smart sensor for viewfinder and
++ displaying it on synchronous display with SDC use case.
++ If SDC BG is selected, Rotation will not be supported.
++ CSI -> IC (PRP VF) -> MEM
++ MEM -> IC (ROT) -> MEM
++ MEM -> SDC (FG/BG)
++
++endchoice
++
++config MXC_IPU_PRP_ENC
++ tristate "Pre-processor Encoder library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ default y
++ ---help---
++ Use case PRP_ENC:
++ Preprocessing image from smart sensor for encoder.
++ CSI -> IC (PRP ENC) -> MEM
++
++config MXC_IPU_CSI_ENC
++ tristate "IPU CSI Encoder library"
++ depends on VIDEO_MXC_IPU_CAMERA
++ default y
++ ---help---
++ Use case IPU_CSI_ENC:
++ Get raw image with CSI from smart sensor for encoder.
++ CSI -> MEM
++endmenu
++
++endif
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/Makefile linux-3.14.72/drivers/media/platform/mxc/capture/Makefile
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/Makefile 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,30 @@
++ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y)
++ obj-$(CONFIG_VIDEO_MXC_CAPTURE) += mxc_v4l2_capture.o
++ obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o
++ obj-$(CONFIG_MXC_IPU_DEVICE_QUEUE_SDC) += ipu_fg_overlay_sdc.o ipu_bg_overlay_sdc.o
++ obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o
++ obj-$(CONFIG_MXC_IPU_CSI_ENC) += ipu_csi_enc.o ipu_still.o
++endif
++
++ov5640_camera_int-objs := ov5640.o
++obj-$(CONFIG_MXC_CAMERA_OV5640) += ov5640_camera_int.o
++
++ov5642_camera-objs := ov5642.o
++obj-$(CONFIG_MXC_CAMERA_OV5642) += ov5642_camera.o
++
++ov5640_camera_mipi-objs := ov5640_mipi.o
++obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI) += ov5640_camera_mipi.o
++
++ov5647_camera_mipi-objs := ov5647_mipi.o
++obj-$(CONFIG_MXC_CAMERA_OV5647_MIPI) += ov5647_camera_mipi.o
++
++tc358743_h2c_bridge-objs := tc358743_h2c.o
++obj-$(CONFIG_MXC_HDMI_CSI2_TC358743) += tc358743_h2c_bridge.o
++
++adv7180_tvin-objs := adv7180.o
++obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o
++
++obj-$(CONFIG_VIDEO_V4L2_MXC_INT_DEVICE) += v4l2-int-device.o
++
++tda1997x-video-objs := tda1997x.o
++obj-$(CONFIG_MXC_TVIN_TDA1997X) += tda1997x-video.o
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c linux-3.14.72/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c 2016-06-19 22:11:55.173148668 +0200
+@@ -0,0 +1,3383 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file drivers/media/video/mxc/capture/mxc_v4l2_capture.c
++ *
++ * @brief Mxc Video For Linux 2 driver
++ *
++ * @ingroup MXC_V4L2_CAPTURE
++ */
++#include <linux/version.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/fs.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/semaphore.h>
++#include <linux/pagemap.h>
++#include <linux/vmalloc.h>
++#include <linux/types.h>
++#include <linux/fb.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/mutex.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <media/v4l2-chip-ident.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-device.h>
++#include "v4l2-int-device.h"
++#include <linux/fsl_devices.h>
++#include "mxc_v4l2_capture.h"
++#include "ipu_prp_sw.h"
++
++#define init_MUTEX(sem) sema_init(sem, 1)
++
++static struct platform_device_id imx_v4l2_devtype[] = {
++ {
++ .name = "v4l2-capture-imx5",
++ .driver_data = IMX5_V4L2,
++ }, {
++ .name = "v4l2-capture-imx6",
++ .driver_data = IMX6_V4L2,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_v4l2_devtype);
++
++static const struct of_device_id mxc_v4l2_dt_ids[] = {
++ {
++ .compatible = "fsl,imx6q-v4l2-capture",
++ .data = &imx_v4l2_devtype[IMX6_V4L2],
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, mxc_v4l2_dt_ids);
++
++static int video_nr = -1;
++
++/*! This data is used for the output to the display. */
++#define MXC_V4L2_CAPTURE_NUM_OUTPUTS 6
++#define MXC_V4L2_CAPTURE_NUM_INPUTS 2
++static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = {
++ {
++ .index = 0,
++ .name = "DISP3 BG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 1,
++ .name = "DISP3 BG - DI1",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 2,
++ .name = "DISP3 FG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 3,
++ .name = "DISP4 BG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 4,
++ .name = "DISP4 BG - DI1",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++ {
++ .index = 5,
++ .name = "DISP4 FG",
++ .type = V4L2_OUTPUT_TYPE_ANALOG,
++ .audioset = 0,
++ .modulator = 0,
++ .std = V4L2_STD_UNKNOWN,
++ },
++};
++
++static struct v4l2_input mxc_capture_inputs[MXC_V4L2_CAPTURE_NUM_INPUTS] = {
++ {
++ .index = 0,
++ .name = "CSI IC MEM",
++ .type = V4L2_INPUT_TYPE_CAMERA,
++ .audioset = 0,
++ .tuner = 0,
++ .std = V4L2_STD_UNKNOWN,
++ .status = 0,
++ },
++ {
++ .index = 1,
++ .name = "CSI MEM",
++ .type = V4L2_INPUT_TYPE_CAMERA,
++ .audioset = 0,
++ .tuner = 0,
++ .std = V4L2_STD_UNKNOWN,
++ .status = V4L2_IN_ST_NO_POWER,
++ },
++};
++
++/*! List of TV input video formats supported. The video formats is corresponding
++ * to the v4l2_id in video_fmt_t.
++ * Currently, only PAL and NTSC is supported. Needs to be expanded in the
++ * future.
++ */
++typedef enum {
++ TV_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
++ TV_PAL, /*!< (B, G, H, I, N)PAL video signal. */
++ TV_NOT_LOCKED, /*!< Not locked on a signal. */
++} video_fmt_idx;
++
++/*! Number of video standards supported (including 'not locked' signal). */
++#define TV_STD_MAX (TV_NOT_LOCKED + 1)
++
++/*! Video format structure. */
++typedef struct {
++ int v4l2_id; /*!< Video for linux ID. */
++ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */
++ u16 raw_width; /*!< Raw width. */
++ u16 raw_height; /*!< Raw height. */
++ u16 active_width; /*!< Active width. */
++ u16 active_height; /*!< Active height. */
++ u16 active_top; /*!< Active top. */
++ u16 active_left; /*!< Active left. */
++} video_fmt_t;
++
++/*!
++ * Description of video formats supported.
++ *
++ * PAL: raw=720x625, active=720x576.
++ * NTSC: raw=720x525, active=720x480.
++ */
++static video_fmt_t video_fmts[] = {
++ { /*! NTSC */
++ .v4l2_id = V4L2_STD_NTSC,
++ .name = "NTSC",
++ .raw_width = 720, /* SENS_FRM_WIDTH */
++ .raw_height = 525, /* SENS_FRM_HEIGHT */
++ .active_width = 720, /* ACT_FRM_WIDTH */
++ .active_height = 480, /* ACT_FRM_HEIGHT */
++ .active_top = 0,
++ .active_left = 0,
++ },
++ { /*! (B, G, H, I, N) PAL */
++ .v4l2_id = V4L2_STD_PAL,
++ .name = "PAL",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ .active_top = 0,
++ .active_left = 0,
++ },
++ { /*! Unlocked standard */
++ .v4l2_id = V4L2_STD_ALL,
++ .name = "Autodetect",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ .active_top = 0,
++ .active_left = 0,
++ },
++};
++
++/*!* Standard index of TV. */
++static video_fmt_idx video_index = TV_NOT_LOCKED;
++
++static int mxc_v4l2_master_attach(struct v4l2_int_device *slave);
++static void mxc_v4l2_master_detach(struct v4l2_int_device *slave);
++static int start_preview(cam_data *cam);
++static int stop_preview(cam_data *cam);
++
++/*! Information about this driver. */
++static struct v4l2_int_master mxc_v4l2_master = {
++ .attach = mxc_v4l2_master_attach,
++ .detach = mxc_v4l2_master_detach,
++};
++
++/***************************************************************************
++ * Functions for handling Frame buffers.
++ **************************************************************************/
++
++/*!
++ * Free frame buffers
++ *
++ * @param cam Structure cam_data *
++ *
++ * @return status 0 success.
++ */
++static int mxc_free_frame_buf(cam_data *cam)
++{
++ int i;
++
++ pr_debug("%s\n", __func__);
++
++ for (i = 0; i < FRAME_NUM; i++) {
++ if (cam->frame[i].vaddress != 0) {
++ dma_free_coherent(0, cam->frame[i].buffer.length,
++ cam->frame[i].vaddress,
++ cam->frame[i].paddress);
++ cam->frame[i].vaddress = 0;
++ }
++ }
++
++ return 0;
++}
++
++/*!
++ * Allocate frame buffers
++ *
++ * @param cam Structure cam_data*
++ * @param count int number of buffer need to allocated
++ *
++ * @return status -0 Successfully allocated a buffer, -ENOBUFS failed.
++ */
++static int mxc_allocate_frame_buf(cam_data *cam, int count)
++{
++ int i;
++ u32 map_sizeimage;
++ struct sensor_data *sensor = cam->sensor->priv;
++
++ if (sensor && sensor->adata) {
++ const struct additional_data *adata = sensor->adata;
++ map_sizeimage = adata->map_sizeimage;
++ }
++ else {
++ map_sizeimage = cam->v2f.fmt.pix.sizeimage;
++ }
++
++ pr_debug("%s: size=%d\n", __func__, map_sizeimage);
++
++ for (i = 0; i < count; i++) {
++ cam->frame[i].vaddress =
++ dma_alloc_coherent(0,
++ PAGE_ALIGN(map_sizeimage),
++ &cam->frame[i].paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->frame[i].vaddress == 0) {
++ pr_err("%s: failed.\n", __func__);
++ mxc_free_frame_buf(cam);
++ return -ENOBUFS;
++ }
++ cam->frame[i].buffer.index = i;
++ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++ cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cam->frame[i].buffer.length = PAGE_ALIGN(map_sizeimage);
++ cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP;
++ cam->frame[i].buffer.m.offset = cam->frame[i].paddress;
++ cam->frame[i].index = i;
++ }
++
++ return 0;
++}
++
++/*!
++ * Free frame buffers status
++ *
++ * @param cam Structure cam_data *
++ *
++ * @return none
++ */
++static void mxc_free_frames(cam_data *cam)
++{
++ int i;
++
++ pr_debug("%s\n", __func__);
++
++ for (i = 0; i < FRAME_NUM; i++)
++ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++
++ cam->enc_counter = 0;
++ INIT_LIST_HEAD(&cam->ready_q);
++ INIT_LIST_HEAD(&cam->working_q);
++ INIT_LIST_HEAD(&cam->done_q);
++}
++
++/*!
++ * Return the buffer status
++ *
++ * @param cam Structure cam_data *
++ * @param buf Structure v4l2_buffer *
++ *
++ * @return status 0 success, EINVAL failed.
++ */
++static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf)
++{
++ pr_debug("%s\n", __func__);
++
++ if (buf->index < 0 || buf->index >= FRAME_NUM) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l2_buffer_status buffers "
++ "not allocated\n");
++ return -EINVAL;
++ }
++
++ memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf));
++ return 0;
++}
++
++static int mxc_v4l2_release_bufs(cam_data *cam)
++{
++ pr_debug("%s\n", __func__);
++ return 0;
++}
++
++static int mxc_v4l2_prepare_bufs(cam_data *cam, struct v4l2_buffer *buf)
++{
++ pr_debug("%s\n", __func__);
++
++ if (buf->index < 0 || buf->index >= FRAME_NUM || buf->length <
++ cam->v2f.fmt.pix.sizeimage) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l2_prepare_bufs buffers "
++ "not allocated,index=%d, length=%d\n", buf->index,
++ buf->length);
++ return -EINVAL;
++ }
++
++ cam->frame[buf->index].buffer.index = buf->index;
++ cam->frame[buf->index].buffer.flags = V4L2_BUF_FLAG_MAPPED;
++ cam->frame[buf->index].buffer.length = buf->length;
++ cam->frame[buf->index].buffer.m.offset = cam->frame[buf->index].paddress
++ = buf->m.offset;
++ cam->frame[buf->index].buffer.type = buf->type;
++ cam->frame[buf->index].buffer.memory = V4L2_MEMORY_USERPTR;
++ cam->frame[buf->index].index = buf->index;
++
++ return 0;
++}
++
++/***************************************************************************
++ * Functions for handling the video stream.
++ **************************************************************************/
++
++/*!
++ * Indicates whether the palette is supported.
++ *
++ * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32
++ *
++ * @return 0 if failed
++ */
++static inline int valid_mode(u32 palette)
++{
++ return ((palette == V4L2_PIX_FMT_RGB565) ||
++ (palette == V4L2_PIX_FMT_BGR24) ||
++ (palette == V4L2_PIX_FMT_RGB24) ||
++ (palette == V4L2_PIX_FMT_BGR32) ||
++ (palette == V4L2_PIX_FMT_RGB32) ||
++ (palette == V4L2_PIX_FMT_YUV422P) ||
++ (palette == V4L2_PIX_FMT_UYVY) ||
++ (palette == V4L2_PIX_FMT_YUYV) ||
++ (palette == V4L2_PIX_FMT_YUV420) ||
++ (palette == V4L2_PIX_FMT_YVU420) ||
++ (palette == V4L2_PIX_FMT_NV12 ||
++ palette == V4L2_PIX_FMT_SBGGR8));
++}
++
++/*!
++ * Start the encoder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int mxc_streamon(cam_data *cam)
++{
++ struct mxc_v4l_frame *frame;
++ unsigned long lock_flags;
++ int err = 0;
++
++ pr_debug("%s\n", __func__);
++
++ if (NULL == cam) {
++ pr_err("ERROR! cam parameter is NULL\n");
++ return -1;
++ }
++
++ if (cam->capture_on) {
++ pr_err("ERROR: v4l2 capture: Capture stream has been turned "
++ " on\n");
++ return -1;
++ }
++
++ if (list_empty(&cam->ready_q)) {
++ pr_err("ERROR: v4l2 capture: mxc_streamon buffer has not been "
++ "queued yet\n");
++ return -EINVAL;
++ }
++ if (cam->enc_update_eba &&
++ cam->ready_q.prev == cam->ready_q.next) {
++ pr_err("ERROR: v4l2 capture: mxc_streamon buffer need "
++ "ping pong at least two buffers\n");
++ return -EINVAL;
++ }
++
++ cam->capture_pid = current->pid;
++
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ if (cam->enc_enable) {
++ err = cam->enc_enable(cam);
++ if (err != 0)
++ return err;
++ }
++
++ spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
++ cam->ping_pong_csi = 0;
++ cam->local_buf_num = 0;
++ if (cam->enc_update_eba) {
++ frame =
++ list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->ready_q.next);
++ list_add_tail(&frame->queue, &cam->working_q);
++ frame->ipu_buf_num = cam->ping_pong_csi;
++ err = cam->enc_update_eba(cam->ipu, frame->buffer.m.offset,
++ &cam->ping_pong_csi);
++
++ frame =
++ list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->ready_q.next);
++ list_add_tail(&frame->queue, &cam->working_q);
++ frame->ipu_buf_num = cam->ping_pong_csi;
++ err |= cam->enc_update_eba(cam->ipu, frame->buffer.m.offset,
++ &cam->ping_pong_csi);
++ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
++ } else {
++ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
++ return -EINVAL;
++ }
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ if (cam->enc_enable_csi) {
++ err = cam->enc_enable_csi(cam);
++ if (err != 0)
++ return err;
++ }
++
++ cam->capture_on = true;
++
++ return err;
++}
++
++/*!
++ * Shut down the encoder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int mxc_streamoff(cam_data *cam)
++{
++ int err = 0;
++
++ pr_debug("%s: ipu%d/csi%d capture_on=%d %s\n", __func__, cam->ipu_id,
++ cam->csi, cam->capture_on,
++ mxc_capture_inputs[cam->current_input].name);
++ if (cam->capture_on == false)
++ return 0;
++ /* For both CSI--MEM and CSI--IC--MEM
++ * 1. wait for idmac eof
++ * 2. disable csi first
++ * 3. disable idmac
++ * 4. disable smfc (CSI--MEM channel)
++ */
++ if (mxc_capture_inputs[cam->current_input].name != NULL) {
++ if (cam->enc_disable_csi) {
++ err = cam->enc_disable_csi(cam);
++ if (err != 0)
++ return err;
++ }
++ if (cam->enc_disable) {
++ err = cam->enc_disable(cam);
++ if (err != 0)
++ return err;
++ }
++ }
++
++ mxc_free_frames(cam);
++ mxc_capture_inputs[cam->current_input].status |= V4L2_IN_ST_NO_POWER;
++ cam->capture_on = false;
++ return err;
++}
++
++/*!
++ * Valid and adjust the overlay window size, position
++ *
++ * @param cam structure cam_data *
++ * @param win struct v4l2_window *
++ *
++ * @return 0
++ */
++static int verify_preview(cam_data *cam, struct v4l2_window *win)
++{
++ int i = 0, width_bound = 0, height_bound = 0;
++ int *width, *height;
++ unsigned int ipu_ch = CHAN_NONE;
++ struct fb_info *bg_fbi = NULL, *fbi = NULL;
++ bool foregound_fb = false;
++ mm_segment_t old_fs;
++
++ pr_debug("%s\n", __func__);
++
++ do {
++ fbi = (struct fb_info *)registered_fb[i];
++ if (fbi == NULL) {
++ pr_err("ERROR: verify_preview frame buffer NULL.\n");
++ return -1;
++ }
++
++ /* Which DI supports 2 layers? */
++ if (((strncmp(fbi->fix.id, "DISP3 BG", 8) == 0) &&
++ (cam->output < 3)) ||
++ ((strncmp(fbi->fix.id, "DISP4 BG", 8) == 0) &&
++ (cam->output >= 3))) {
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
++ (unsigned long)&ipu_ch);
++ set_fs(old_fs);
++ }
++ if (ipu_ch == MEM_BG_SYNC) {
++ bg_fbi = fbi;
++ pr_debug("Found background frame buffer.\n");
++ }
++ }
++
++ /* Found the frame buffer to preview on. */
++ if (strcmp(fbi->fix.id,
++ mxc_capture_outputs[cam->output].name) == 0) {
++ if (((strcmp(fbi->fix.id, "DISP3 FG") == 0) &&
++ (cam->output < 3)) ||
++ ((strcmp(fbi->fix.id, "DISP4 FG") == 0) &&
++ (cam->output >= 3)))
++ foregound_fb = true;
++
++ cam->overlay_fb = fbi;
++ break;
++ }
++ } while (++i < FB_MAX);
++
++ if (foregound_fb) {
++ width_bound = bg_fbi->var.xres;
++ height_bound = bg_fbi->var.yres;
++
++ if (win->w.width + win->w.left > bg_fbi->var.xres ||
++ win->w.height + win->w.top > bg_fbi->var.yres) {
++ pr_err("ERROR: FG window position exceeds.\n");
++ return -1;
++ }
++ } else {
++ /* 4 bytes alignment for BG */
++ width_bound = cam->overlay_fb->var.xres;
++ height_bound = cam->overlay_fb->var.yres;
++
++ if (cam->overlay_fb->var.bits_per_pixel == 24)
++ win->w.left -= win->w.left % 4;
++ else if (cam->overlay_fb->var.bits_per_pixel == 16)
++ win->w.left -= win->w.left % 2;
++
++ if (win->w.width + win->w.left > cam->overlay_fb->var.xres)
++ win->w.width = cam->overlay_fb->var.xres - win->w.left;
++ if (win->w.height + win->w.top > cam->overlay_fb->var.yres)
++ win->w.height = cam->overlay_fb->var.yres - win->w.top;
++ }
++
++ /* stride line limitation */
++ win->w.height -= win->w.height % 8;
++ win->w.width -= win->w.width % 8;
++
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ height = &win->w.width;
++ width = &win->w.height;
++ } else {
++ width = &win->w.width;
++ height = &win->w.height;
++ }
++
++ if (*width == 0 || *height == 0) {
++ pr_err("ERROR: v4l2 capture: width or height"
++ " too small.\n");
++ return -EINVAL;
++ }
++
++ if ((cam->crop_bounds.width / *width > 8) ||
++ ((cam->crop_bounds.width / *width == 8) &&
++ (cam->crop_bounds.width % *width))) {
++ *width = cam->crop_bounds.width / 8;
++ if (*width % 8)
++ *width += 8 - *width % 8;
++ if (*width + win->w.left > width_bound) {
++ pr_err("ERROR: v4l2 capture: width exceeds "
++ "resize limit.\n");
++ return -1;
++ }
++ pr_err("ERROR: v4l2 capture: width exceeds limit. "
++ "Resize to %d.\n",
++ *width);
++ }
++
++ if ((cam->crop_bounds.height / *height > 8) ||
++ ((cam->crop_bounds.height / *height == 8) &&
++ (cam->crop_bounds.height % *height))) {
++ *height = cam->crop_bounds.height / 8;
++ if (*height % 8)
++ *height += 8 - *height % 8;
++ if (*height + win->w.top > height_bound) {
++ pr_err("ERROR: v4l2 capture: height exceeds "
++ "resize limit.\n");
++ return -1;
++ }
++ pr_err("ERROR: v4l2 capture: height exceeds limit "
++ "resize to %d.\n",
++ *height);
++ }
++
++ return 0;
++}
++
++/*!
++ * start the viewfinder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int start_preview(cam_data *cam)
++{
++ int err = 0;
++
++ pr_debug("MVC: start_preview\n");
++
++ if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_select(cam);
++ #else
++ err = foreground_sdc_select(cam);
++ #endif
++ else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_select_bg(cam);
++ #else
++ err = bg_overlay_sdc_select(cam);
++ #endif
++ if (err != 0)
++ return err;
++
++ if (cam->vf_start_sdc) {
++ err = cam->vf_start_sdc(cam);
++ if (err != 0)
++ return err;
++ }
++
++ if (cam->vf_enable_csi)
++ err = cam->vf_enable_csi(cam);
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ return err;
++}
++
++/*!
++ * shut down the viewfinder job
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int stop_preview(cam_data *cam)
++{
++ int err = 0;
++
++ if (cam->vf_disable_csi) {
++ err = cam->vf_disable_csi(cam);
++ if (err != 0)
++ return err;
++ }
++
++ if (cam->vf_stop_sdc) {
++ err = cam->vf_stop_sdc(cam);
++ if (err != 0)
++ return err;
++ }
++
++ if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_deselect(cam);
++ #else
++ err = foreground_sdc_deselect(cam);
++ #endif
++ else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY)
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ err = prp_vf_sdc_deselect_bg(cam);
++ #else
++ err = bg_overlay_sdc_deselect(cam);
++ #endif
++
++ return err;
++}
++
++/***************************************************************************
++ * VIDIOC Functions.
++ **************************************************************************/
++
++/*!
++ * V4L2 - mxc_v4l2_g_fmt function
++ *
++ * @param cam structure cam_data *
++ *
++ * @param f structure v4l2_format *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f)
++{
++ int retval = 0;
++
++ pr_debug("%s: type=%d\n", __func__, f->type);
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ f->fmt.pix = cam->v2f.fmt.pix;
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
++ f->fmt.win = cam->win;
++ break;
++ default:
++ pr_debug(" type is invalid\n");
++ retval = -EINVAL;
++ }
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ return retval;
++}
++
++/*!
++ * V4L2 - mxc_v4l2_s_fmt function
++ *
++ * @param cam structure cam_data *
++ *
++ * @param f structure v4l2_format *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f, bool try_fmt)
++{
++ int retval = 0;
++ int size = 0;
++ int bytesperline = 0;
++ int *width, *height;
++
++ pr_debug("%s\n", __func__);
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ if (!valid_mode(f->fmt.pix.pixelformat)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l2_s_fmt: format "
++ "not supported\n");
++ return -EINVAL;
++ }
++
++ /*
++ * Force the capture window resolution to be crop bounds
++ * for CSI MEM input mode.
++ */
++ if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI MEM") == 0) {
++ f->fmt.pix.width = cam->crop_current.width;
++ f->fmt.pix.height = cam->crop_current.height;
++ }
++
++ if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
++ height = &f->fmt.pix.width;
++ width = &f->fmt.pix.height;
++ } else {
++ width = &f->fmt.pix.width;
++ height = &f->fmt.pix.height;
++ }
++
++ /* stride line limitation */
++ *width -= *width % 8;
++ *height -= *height % 8;
++
++ if (*width == 0 || *height == 0) {
++ pr_err("ERROR: v4l2 capture: width or height"
++ " too small.\n");
++ return -EINVAL;
++ }
++
++ if ((cam->crop_current.width / *width > 8) ||
++ ((cam->crop_current.width / *width == 8) &&
++ (cam->crop_current.width % *width))) {
++ *width = cam->crop_current.width / 8;
++ if (*width % 8)
++ *width += 8 - *width % 8;
++ pr_err("ERROR: v4l2 capture: width exceeds limit "
++ "resize to %d.\n",
++ *width);
++ }
++
++ if ((cam->crop_current.height / *height > 8) ||
++ ((cam->crop_current.height / *height == 8) &&
++ (cam->crop_current.height % *height))) {
++ *height = cam->crop_current.height / 8;
++ if (*height % 8)
++ *height += 8 - *height % 8;
++ pr_err("ERROR: v4l2 capture: height exceeds limit "
++ "resize to %d.\n",
++ *height);
++ }
++
++ switch (f->fmt.pix.pixelformat) {
++ case V4L2_PIX_FMT_RGB565:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ bytesperline = f->fmt.pix.width * 2;
++ break;
++ case V4L2_PIX_FMT_BGR24:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3;
++ bytesperline = f->fmt.pix.width * 3;
++ break;
++ case V4L2_PIX_FMT_RGB24:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3;
++ bytesperline = f->fmt.pix.width * 3;
++ break;
++ case V4L2_PIX_FMT_BGR32:
++ size = f->fmt.pix.width * f->fmt.pix.height * 4;
++ bytesperline = f->fmt.pix.width * 4;
++ break;
++ case V4L2_PIX_FMT_RGB32:
++ size = f->fmt.pix.width * f->fmt.pix.height * 4;
++ bytesperline = f->fmt.pix.width * 4;
++ break;
++ case V4L2_PIX_FMT_YUV422P:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ bytesperline = f->fmt.pix.width;
++ break;
++ case V4L2_PIX_FMT_UYVY:
++ case V4L2_PIX_FMT_YUYV:
++ size = f->fmt.pix.width * f->fmt.pix.height * 2;
++ bytesperline = f->fmt.pix.width * 2;
++ break;
++ case V4L2_PIX_FMT_YUV420:
++ case V4L2_PIX_FMT_YVU420:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
++ bytesperline = f->fmt.pix.width;
++ break;
++ case V4L2_PIX_FMT_NV12:
++ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2;
++ bytesperline = f->fmt.pix.width;
++ break;
++ case V4L2_PIX_FMT_SBGGR8:
++ size = f->fmt.pix.width * f->fmt.pix.height;
++ bytesperline = f->fmt.pix.width;
++ break;
++ default:
++ break;
++ }
++
++ if (f->fmt.pix.bytesperline < bytesperline)
++ f->fmt.pix.bytesperline = bytesperline;
++ else
++ bytesperline = f->fmt.pix.bytesperline;
++
++ if (try_fmt) {
++ /* XXX: workaround for gstreamer */
++ if (f->fmt.pix.sizeimage < size ||
++ f->fmt.pix.sizeimage % size)
++ f->fmt.pix.sizeimage = size;
++ else
++ size = f->fmt.pix.sizeimage;
++
++ break;
++ }
++ else {
++ if (f->fmt.pix.sizeimage < size)
++ f->fmt.pix.sizeimage = size;
++ else
++ size = f->fmt.pix.sizeimage;
++ }
++
++ cam->v2f.fmt.pix = f->fmt.pix;
++
++ if (cam->v2f.fmt.pix.priv != 0) {
++ if (copy_from_user(&cam->offset,
++ (void *)cam->v2f.fmt.pix.priv,
++ sizeof(cam->offset))) {
++ retval = -EFAULT;
++ break;
++ }
++ }
++ break;
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n");
++ retval = verify_preview(cam, &f->fmt.win);
++ if (!try_fmt)
++ cam->win = f->fmt.win;
++ break;
++ default:
++ retval = -EINVAL;
++ }
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ return retval;
++}
++
++/*!
++ * get control param
++ *
++ * @param cam structure cam_data *
++ *
++ * @param c structure v4l2_control *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
++{
++ int status = 0;
++
++ pr_debug("%s\n", __func__);
++
++ /* probably don't need to store the values that can be retrieved,
++ * locally, but they are for now. */
++ switch (c->id) {
++ case V4L2_CID_HFLIP:
++ /* This is handled in the ipu. */
++ if (cam->rotation == IPU_ROTATE_HORIZ_FLIP)
++ c->value = 1;
++ break;
++ case V4L2_CID_VFLIP:
++ /* This is handled in the ipu. */
++ if (cam->rotation == IPU_ROTATE_VERT_FLIP)
++ c->value = 1;
++ break;
++ case V4L2_CID_MXC_ROT:
++ /* This is handled in the ipu. */
++ c->value = cam->rotation;
++ break;
++ case V4L2_CID_BRIGHTNESS:
++ if (cam->sensor) {
++ c->value = cam->bright;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->bright = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_HUE:
++ if (cam->sensor) {
++ c->value = cam->hue;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->hue = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_CONTRAST:
++ if (cam->sensor) {
++ c->value = cam->contrast;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->contrast = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_SATURATION:
++ if (cam->sensor) {
++ c->value = cam->saturation;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->saturation = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_RED_BALANCE:
++ if (cam->sensor) {
++ c->value = cam->red;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->red = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ if (cam->sensor) {
++ c->value = cam->blue;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->blue = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BLACK_LEVEL:
++ if (cam->sensor) {
++ c->value = cam->ae_mode;
++ status = vidioc_int_g_ctrl(cam->sensor, c);
++ cam->ae_mode = c->value;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ status = -ENODEV;
++ }
++ break;
++ default:
++ pr_err("ERROR: v4l2 capture: unsupported ioctrl!\n");
++ }
++
++ return status;
++}
++
++static int mxc_v4l2_send_command(cam_data *cam,
++ struct v4l2_send_command_control *c) {
++ int ret =0;
++
++ if (vidioc_int_send_command(cam->sensor, c)) {
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++/*!
++ * V4L2 - set_control function
++ * V4L2_CID_PRIVATE_BASE is the extention for IPU preprocessing.
++ * 0 for normal operation
++ * 1 for vertical flip
++ * 2 for horizontal flip
++ * 3 for horizontal and vertical flip
++ * 4 for 90 degree rotation
++ * @param cam structure cam_data *
++ *
++ * @param c structure v4l2_control *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
++{
++ int i, ret = 0;
++ int tmp_rotation = IPU_ROTATE_NONE;
++ struct sensor_data *sensor_data;
++
++ pr_debug("%s\n", __func__);
++
++ switch (c->id) {
++ case V4L2_CID_HFLIP:
++ /* This is done by the IPU */
++ if (c->value == 1) {
++ if ((cam->rotation != IPU_ROTATE_VERT_FLIP) &&
++ (cam->rotation != IPU_ROTATE_180))
++ cam->rotation = IPU_ROTATE_HORIZ_FLIP;
++ else
++ cam->rotation = IPU_ROTATE_180;
++ } else {
++ if (cam->rotation == IPU_ROTATE_HORIZ_FLIP)
++ cam->rotation = IPU_ROTATE_NONE;
++ if (cam->rotation == IPU_ROTATE_180)
++ cam->rotation = IPU_ROTATE_VERT_FLIP;
++ }
++ break;
++ case V4L2_CID_VFLIP:
++ /* This is done by the IPU */
++ if (c->value == 1) {
++ if ((cam->rotation != IPU_ROTATE_HORIZ_FLIP) &&
++ (cam->rotation != IPU_ROTATE_180))
++ cam->rotation = IPU_ROTATE_VERT_FLIP;
++ else
++ cam->rotation = IPU_ROTATE_180;
++ } else {
++ if (cam->rotation == IPU_ROTATE_VERT_FLIP)
++ cam->rotation = IPU_ROTATE_NONE;
++ if (cam->rotation == IPU_ROTATE_180)
++ cam->rotation = IPU_ROTATE_HORIZ_FLIP;
++ }
++ break;
++ case V4L2_CID_MXC_ROT:
++ case V4L2_CID_MXC_VF_ROT:
++ /* This is done by the IPU */
++ switch (c->value) {
++ case V4L2_MXC_ROTATE_NONE:
++ tmp_rotation = IPU_ROTATE_NONE;
++ break;
++ case V4L2_MXC_ROTATE_VERT_FLIP:
++ tmp_rotation = IPU_ROTATE_VERT_FLIP;
++ break;
++ case V4L2_MXC_ROTATE_HORIZ_FLIP:
++ tmp_rotation = IPU_ROTATE_HORIZ_FLIP;
++ break;
++ case V4L2_MXC_ROTATE_180:
++ tmp_rotation = IPU_ROTATE_180;
++ break;
++ case V4L2_MXC_ROTATE_90_RIGHT:
++ tmp_rotation = IPU_ROTATE_90_RIGHT;
++ break;
++ case V4L2_MXC_ROTATE_90_RIGHT_VFLIP:
++ tmp_rotation = IPU_ROTATE_90_RIGHT_VFLIP;
++ break;
++ case V4L2_MXC_ROTATE_90_RIGHT_HFLIP:
++ tmp_rotation = IPU_ROTATE_90_RIGHT_HFLIP;
++ break;
++ case V4L2_MXC_ROTATE_90_LEFT:
++ tmp_rotation = IPU_ROTATE_90_LEFT;
++ break;
++ case V4L2_MXC_CAM_ROTATE_NONE:
++ if (vidioc_int_s_ctrl(cam->sensor, c)) {
++ ret = -EINVAL;
++ }
++ break;
++ case V4L2_MXC_CAM_ROTATE_VERT_FLIP:
++ if (vidioc_int_s_ctrl(cam->sensor, c)) {
++ ret = -EINVAL;
++ }
++ break;
++ case V4L2_MXC_CAM_ROTATE_HORIZ_FLIP:
++ if (vidioc_int_s_ctrl(cam->sensor, c)) {
++ ret = -EINVAL;
++ }
++ break;
++ case V4L2_MXC_CAM_ROTATE_180:
++ if (vidioc_int_s_ctrl(cam->sensor, c)) {
++ ret = -EINVAL;
++ }
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC
++ if (c->id == V4L2_CID_MXC_VF_ROT)
++ cam->vf_rotation = tmp_rotation;
++ else
++ cam->rotation = tmp_rotation;
++ #else
++ cam->rotation = tmp_rotation;
++ #endif
++
++ break;
++ case V4L2_CID_HUE:
++ if (cam->sensor) {
++ cam->hue = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_CONTRAST:
++ if (cam->sensor) {
++ cam->contrast = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BRIGHTNESS:
++ if (cam->sensor) {
++ cam->bright = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_SATURATION:
++ if (cam->sensor) {
++ cam->saturation = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_RED_BALANCE:
++ if (cam->sensor) {
++ cam->red = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ if (cam->sensor) {
++ cam->blue = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_EXPOSURE:
++ if (cam->sensor) {
++ cam->ae_mode = c->value;
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ ret = -ENODEV;
++ }
++ break;
++ case V4L2_CID_MXC_FLASH:
++#ifdef CONFIG_MXC_IPU_V1
++ ipu_csi_flash_strobe(true);
++#endif
++ break;
++
++ case V4L2_CID_AUTO_FOCUS_START: {
++ ret = vidioc_int_s_ctrl(cam->sensor, c);
++ break;
++ }
++
++ case V4L2_CID_AUTO_FOCUS_STOP: {
++ if (vidioc_int_s_ctrl(cam->sensor, c)) {
++ ret = -EINVAL;
++ }
++ break;
++ }
++
++ case V4L2_CID_MXC_SWITCH_CAM:
++ if (cam->sensor == cam->all_sensors[c->value])
++ break;
++
++ /* power down other cameraes before enable new one */
++ for (i = 0; i < cam->sensor_index; i++) {
++ if (i != c->value) {
++ vidioc_int_dev_exit(cam->all_sensors[i]);
++ vidioc_int_s_power(cam->all_sensors[i], 0);
++ if (cam->mclk_on[cam->mclk_source]) {
++ ipu_csi_enable_mclk_if(cam->ipu,
++ CSI_MCLK_I2C,
++ cam->mclk_source,
++ false, false);
++ cam->mclk_on[cam->mclk_source] =
++ false;
++ }
++ }
++ }
++ sensor_data = cam->all_sensors[c->value]->priv;
++ if (sensor_data->io_init)
++ sensor_data->io_init();
++ cam->sensor = cam->all_sensors[c->value];
++ cam->mclk_source = sensor_data->mclk_source;
++ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
++ cam->mclk_source, true, true);
++ cam->mclk_on[cam->mclk_source] = true;
++ vidioc_int_s_power(cam->sensor, 1);
++ vidioc_int_dev_init(cam->sensor);
++ break;
++ default:
++ pr_debug(" default case\n");
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++void setup_ifparm(cam_data *cam, int init_defrect)
++{
++ struct v4l2_format cam_fmt;
++ ipu_csi_signal_cfg_t csi_param;
++ struct v4l2_ifparm ifparm;
++ int swidth, sheight;
++ int sleft, stop;
++
++ vidioc_int_g_ifparm(cam->sensor, &ifparm);
++ memset(&csi_param, 0, sizeof(csi_param));
++ csi_param.csi = cam->csi;
++ csi_param.mclk = ifparm.u.bt656.clock_curr;
++
++ pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
++ switch (ifparm.if_type) {
++ case V4L2_IF_TYPE_BT1120_PROGRESSIVE_DDR:
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR;
++ break;
++ case V4L2_IF_TYPE_BT1120_PROGRESSIVE_SDR:
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR;
++ break;
++ case V4L2_IF_TYPE_BT1120_INTERLACED_DDR:
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR;
++ break;
++ case V4L2_IF_TYPE_BT1120_INTERLACED_SDR:
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR;
++ break;
++ case V4L2_IF_TYPE_BT656_PROGRESSIVE:
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
++ break;
++ case V4L2_IF_TYPE_BT656_INTERLACED:
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
++ break;
++ case V4L2_IF_TYPE_BT656:
++// csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
++// break;
++ default:
++ if (ifparm.u.bt656.clock_curr == 0) {
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
++ /*protocol bt656 use 27Mhz pixel clock */
++ csi_param.mclk = 27000000;
++ } else if (ifparm.u.bt656.clock_curr == 1) {
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
++ } else
++ csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
++ }
++
++ csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;
++
++ csi_param.data_width =
++ (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) ||
++ (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_BT_10BIT) ?
++ IPU_CSI_DATA_WIDTH_10 : IPU_CSI_DATA_WIDTH_8;
++
++ csi_param.pack_tight = (csi_param.data_width == IPU_CSI_DATA_WIDTH_10) ? 1 : 0;
++
++ csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv;
++ csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv;
++ csi_param.ext_vsync = ifparm.u.bt656.bt_sync_correct;
++ pr_debug("vsync_pol(%d) hsync_pol(%d) ext_vsync(%d)\n", csi_param.Vsync_pol, csi_param.Hsync_pol, csi_param.ext_vsync);
++
++ /* if the capturemode changed, the size bounds will have changed. */
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++ pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n",
++ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
++
++ switch (cam_fmt.fmt.pix.pixelformat) {
++ case V4L2_PIX_FMT_RGB565:
++ csi_param.data_fmt = IPU_PIX_FMT_RGB565;
++ break;
++ case V4L2_PIX_FMT_BGR24:
++ csi_param.data_fmt = IPU_PIX_FMT_BGR24;
++ break;
++ case V4L2_PIX_FMT_RGB24:
++ csi_param.data_fmt = IPU_PIX_FMT_RGB24;
++ break;
++ case V4L2_PIX_FMT_BGR32:
++ csi_param.data_fmt = IPU_PIX_FMT_BGR32;
++ break;
++ case V4L2_PIX_FMT_RGB32:
++ csi_param.data_fmt = IPU_PIX_FMT_RGB32;
++ break;
++ case V4L2_PIX_FMT_YUV422P:
++ csi_param.data_fmt = IPU_PIX_FMT_YUV422P;
++ break;
++ case V4L2_PIX_FMT_UYVY:
++ csi_param.data_fmt = IPU_PIX_FMT_UYVY;
++ break;
++ case V4L2_PIX_FMT_YUYV:
++ csi_param.data_fmt = IPU_PIX_FMT_YUYV;
++ break;
++ case V4L2_PIX_FMT_YUV420:
++ csi_param.data_fmt = IPU_PIX_FMT_YUV420P;
++ break;
++ case V4L2_PIX_FMT_YVU420:
++ csi_param.data_fmt = IPU_PIX_FMT_YVU420P;;
++ break;
++ case V4L2_PIX_FMT_NV12:
++ csi_param.data_fmt = IPU_PIX_FMT_NV12;
++ break;
++ case V4L2_PIX_FMT_SBGGR8:
++ default:
++ csi_param.data_fmt = IPU_PIX_FMT_GENERIC;
++ break;
++ }
++
++ cam->crop_bounds.top = cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = cam_fmt.fmt.pix.width;
++ cam->crop_bounds.height = cam_fmt.fmt.pix.height;
++
++ /*
++ * Set the default current cropped resolution to be the same with
++ * the cropping boundary(except for tvin module).
++ */
++ if (cam->device_type != 1) {
++ cam->crop_current.width = cam->crop_bounds.width;
++ cam->crop_current.height = cam->crop_bounds.height;
++ }
++
++ if (init_defrect) {
++ /* This also is the max crop size for this device. */
++ cam->crop_defrect.top = cam->crop_defrect.left = 0;
++ cam->crop_defrect.width = cam_fmt.fmt.pix.width;
++ cam->crop_defrect.height = cam_fmt.fmt.pix.height;
++
++ /* At this point, this is also the current image size. */
++ cam->crop_current.top = cam->crop_current.left = 0;
++ cam->crop_current.width = cam_fmt.fmt.pix.width;
++ cam->crop_current.height = cam_fmt.fmt.pix.height;
++ pr_debug("On Open: Input to ipu size is %d x %d\n",
++ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height);
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n", __func__,
++ cam->crop_current.width, cam->crop_current.height);
++ }
++ swidth = cam->crop_current.width;
++ sheight = cam->crop_current.height;
++ sleft = 0;
++ stop = 0;
++ cam_fmt.type = V4L2_BUF_TYPE_SENSOR;
++ cam_fmt.fmt.spix.swidth = 0;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++ if (cam_fmt.fmt.spix.swidth) {
++ swidth = cam_fmt.fmt.spix.swidth;
++ sheight = cam_fmt.fmt.spix.sheight;
++ sleft = cam_fmt.fmt.spix.left;
++ stop = cam_fmt.fmt.spix.top;
++ }
++ /* This essentially loses the data at the left and bottom of the image
++ * giving a digital zoom image, if crop_current is less than the full
++ * size of the image. */
++ ipu_csi_window_size_crop(cam->ipu,
++ swidth, sheight,
++ cam->crop_current.width, cam->crop_current.height,
++ sleft + cam->crop_current.left, stop + cam->crop_current.top,
++ cam->csi);
++ ipu_csi_init_interface(cam->ipu, cam->crop_bounds.width,
++ cam->crop_bounds.height,
++ csi_param.data_fmt, csi_param);
++}
++
++/*!
++ * V4L2 - mxc_v4l2_s_param function
++ * Allows setting of capturemode and frame rate.
++ *
++ * @param cam structure cam_data *
++ * @param parm structure v4l2_streamparm *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
++{
++ struct v4l2_streamparm currentparm;
++ u32 current_fps, parm_fps;
++ int err = 0;
++
++ pr_debug("%s\n", __func__);
++
++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n");
++ return -EINVAL;
++ }
++
++ /* Stop the viewfinder */
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++
++ /* First check that this device can support the changes requested. */
++ err = vidioc_int_g_parm(cam->sensor, &currentparm);
++ if (err) {
++ pr_err("%s: vidioc_int_g_parm returned an error %d\n",
++ __func__, err);
++ goto exit;
++ }
++
++ current_fps = currentparm.parm.capture.timeperframe.denominator
++ / currentparm.parm.capture.timeperframe.numerator;
++ parm_fps = parm->parm.capture.timeperframe.denominator
++ / parm->parm.capture.timeperframe.numerator;
++
++ pr_debug(" Current capabilities are %x\n",
++ currentparm.parm.capture.capability);
++ pr_debug(" Current capturemode is %d change to %d\n",
++ currentparm.parm.capture.capturemode,
++ parm->parm.capture.capturemode);
++ pr_debug(" Current framerate is %d change to %d\n",
++ current_fps, parm_fps);
++
++ /* This will change any camera settings needed. */
++ err = vidioc_int_s_parm(cam->sensor, parm);
++ if (err) {
++ pr_err("%s: vidioc_int_s_parm returned an error %d\n",
++ __func__, err);
++ goto exit;
++ }
++
++ /* If resolution changed, need to re-program the CSI */
++ /* Get new values. */
++ setup_ifparm(cam, 0);
++
++exit:
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ return err;
++}
++
++/*!
++ * V4L2 - mxc_v4l2_s_std function
++ *
++ * Sets the TV standard to be used.
++ *
++ * @param cam structure cam_data *
++ * @param parm structure v4l2_streamparm *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e)
++{
++ pr_debug("%s: %Lx\n", __func__, e);
++ switch (e) {
++ case V4L2_STD_PAL:
++ pr_debug(" Setting standard to PAL %Lx\n", V4L2_STD_PAL);
++ cam->standard.id = V4L2_STD_PAL;
++ video_index = TV_PAL;
++ break;
++ case V4L2_STD_NTSC:
++ pr_debug(" Setting standard to NTSC %Lx\n",
++ V4L2_STD_NTSC);
++ /* Get rid of the white dot line in NTSC signal input */
++ cam->standard.id = V4L2_STD_NTSC;
++ video_index = TV_NTSC;
++ break;
++ case V4L2_STD_UNKNOWN:
++ case V4L2_STD_ALL:
++ /* auto-detect don't report an error */
++ cam->standard.id = V4L2_STD_ALL;
++ video_index = TV_NOT_LOCKED;
++ break;
++ default:
++ cam->standard.id = V4L2_STD_ALL;
++ video_index = TV_NOT_LOCKED;
++ pr_err("ERROR: unrecognized std! %Lx (PAL=%Lx, NTSC=%Lx\n",
++ e, V4L2_STD_PAL, V4L2_STD_NTSC);
++ }
++
++ cam->standard.index = video_index;
++ strcpy(cam->standard.name, video_fmts[video_index].name);
++ cam->crop_bounds.width = video_fmts[video_index].raw_width;
++ cam->crop_bounds.height = video_fmts[video_index].raw_height;
++ cam->crop_current.width = video_fmts[video_index].active_width;
++ cam->crop_current.height = video_fmts[video_index].active_height;
++ cam->crop_current.top = video_fmts[video_index].active_top;
++ cam->crop_current.left = video_fmts[video_index].active_left;
++
++ return 0;
++}
++
++/*!
++ * V4L2 - mxc_v4l2_g_std function
++ *
++ * Gets the TV standard from the TV input device.
++ *
++ * @param cam structure cam_data *
++ *
++ * @param e structure v4l2_streamparm *
++ *
++ * @return status 0 success, EINVAL failed
++ */
++static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e)
++{
++ struct v4l2_format tv_fmt;
++
++ pr_debug("%s\n", __func__);
++
++ if (cam->device_type == 1) {
++ /* Use this function to get what the TV-In device detects the
++ * format to be. pixelformat is used to return the std value
++ * since the interface has no vidioc_g_std.*/
++ tv_fmt.type = V4L2_BUF_TYPE_PRIVATE;
++ vidioc_int_g_fmt_cap(cam->sensor, &tv_fmt);
++
++ /* If the TV-in automatically detects the standard, then if it
++ * changes, the settings need to change. */
++ if (cam->standard_autodetect) {
++ if (cam->standard.id != tv_fmt.fmt.pix.pixelformat) {
++ pr_debug("MVC: mxc_v4l2_g_std: "
++ "Changing standard\n");
++ mxc_v4l2_s_std(cam, tv_fmt.fmt.pix.pixelformat);
++ }
++ }
++
++ *e = tv_fmt.fmt.pix.pixelformat;
++ }
++
++ return 0;
++}
++
++/*!
++ * Dequeue one V4L capture buffer
++ *
++ * @param cam structure cam_data *
++ * @param buf structure v4l2_buffer *
++ *
++ * @return status 0 success, EINVAL invalid frame number,
++ * ETIME timeout, ERESTARTSYS interrupted by user
++ */
++static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
++{
++ int retval = 0;
++ struct mxc_v4l_frame *frame;
++ unsigned long lock_flags;
++
++ pr_debug("%s\n", __func__);
++
++ if (!wait_event_interruptible_timeout(cam->enc_queue,
++ cam->enc_counter != 0,
++ 50 * HZ)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout "
++ "enc_counter %x\n",
++ cam->enc_counter);
++ return -ETIME;
++ } else if (signal_pending(current)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() "
++ "interrupt received\n");
++ return -ERESTARTSYS;
++ }
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EBUSY;
++
++ spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags);
++ cam->enc_counter--;
++
++ frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue);
++ list_del(cam->done_q.next);
++ if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) {
++ frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE;
++ } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
++ "Buffer not filled.\n");
++ frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++ retval = -EINVAL;
++ } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: "
++ "Buffer not queued.\n");
++ retval = -EINVAL;
++ }
++
++ cam->frame[frame->index].buffer.field = cam->device_type ?
++ V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
++
++ buf->bytesused = cam->v2f.fmt.pix.sizeimage;
++ buf->index = frame->index;
++ buf->flags = frame->buffer.flags;
++ buf->m = cam->frame[frame->index].buffer.m;
++ buf->timestamp = cam->frame[frame->index].buffer.timestamp;
++ buf->field = cam->frame[frame->index].buffer.field;
++ spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags);
++
++ up(&cam->busy_lock);
++ return retval;
++}
++
++static void power_down_callback(struct work_struct *work)
++{
++ cam_data *cam = container_of(work, struct _cam_data, power_down_work.work);
++
++ down(&cam->busy_lock);
++ if (!cam->open_count) {
++ pr_info("%s: ipu%d/csi%d\n", __func__, cam->ipu_id, cam->csi);
++ vidioc_int_s_power(cam->sensor, 0);
++ cam->power_on = 0;
++ }
++ up(&cam->busy_lock);
++}
++
++/* cam->busy_lock is held */
++void power_up_camera(cam_data *cam)
++{
++ if (cam->power_on) {
++ cancel_delayed_work(&cam->power_down_work);
++ return;
++ }
++ vidioc_int_s_power(cam->sensor, 1);
++ vidioc_int_init(cam->sensor);
++ vidioc_int_dev_init(cam->sensor);
++ cam->power_on = 1;
++}
++
++
++void power_off_camera(cam_data *cam)
++{
++ schedule_delayed_work(&cam->power_down_work, (HZ * 2));
++}
++
++unsigned long csi_in_use;
++
++/*!
++ * V4L interface - open function
++ *
++ * @param file structure file *
++ *
++ * @return status 0 success, ENODEV invalid device instance,
++ * ENODEV timeout, ERESTARTSYS interrupted by user
++ */
++static int mxc_v4l_open(struct file *file)
++{
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ int err = 0;
++ struct sensor_data *sensor;
++ int csi_bit;
++
++ if (!cam) {
++ pr_err("%s: %s cam_data not found!\n", __func__, dev->name);
++ return -EBADF;
++ }
++ if (!cam->sensor) {
++ pr_err("%s: %s no sensor ipu%d/csi%d\n",
++ __func__, dev->name, cam->ipu_id, cam->csi);
++ return -EAGAIN;
++ }
++ if (cam->sensor->type != v4l2_int_type_slave) {
++ pr_err("%s: %s wrong type ipu%d/csi%d, type=%d/%d\n",
++ __func__, dev->name, cam->ipu_id, cam->csi,
++ cam->sensor->type, v4l2_int_type_slave);
++ return -EAGAIN;
++ }
++
++ sensor = cam->sensor->priv;
++ if (!sensor) {
++ pr_err("%s: Internal error, sensor_data is not found!\n",
++ __func__);
++ return -EBADF;
++ }
++ pr_debug("%s: %s ipu%d/csi%d\n", __func__, dev->name,
++ cam->ipu_id, cam->csi);
++
++ down(&cam->busy_lock);
++
++ err = 0;
++ if (signal_pending(current))
++ goto oops;
++
++ if (cam->open_count++ == 0) {
++ struct regmap *gpr;
++
++ csi_bit = (cam->ipu_id << 1) | cam->csi;
++ if (test_and_set_bit(csi_bit, &csi_in_use)) {
++ pr_err("%s: %s CSI already in use\n", __func__, dev->name);
++ err = -EBUSY;
++ cam->open_count = 0;
++ goto oops;
++ }
++ cam->csi_in_use = 1;
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ if (of_machine_is_compatible("fsl,imx6q")) {
++ if (cam->ipu_id == cam->csi) {
++ unsigned shift = 19 + cam->csi;
++ unsigned mask = 1 << shift;
++ unsigned val = (cam->mipi_camera ? 0 : 1) << shift;
++
++ regmap_update_bits(gpr, IOMUXC_GPR1, mask, val);
++ }
++ } else if (of_machine_is_compatible("fsl,imx6dl")) {
++ unsigned shift = cam->csi * 3;
++ unsigned mask = 7 << shift;
++ unsigned val = (cam->mipi_camera ? csi_bit : 4) << shift;
++
++ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
++ }
++ } else {
++ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
++ __func__);
++ }
++
++ wait_event_interruptible(cam->power_queue,
++ cam->low_power == false);
++
++ if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++ err = csi_enc_select(cam);
++#endif
++ } else if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI IC MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
++ err = prp_enc_select(cam);
++#endif
++ }
++
++ cam->enc_counter = 0;
++ INIT_LIST_HEAD(&cam->ready_q);
++ INIT_LIST_HEAD(&cam->working_q);
++ INIT_LIST_HEAD(&cam->done_q);
++ setup_ifparm(cam, 1);
++ if (!IS_ERR(sensor->sensor_clk))
++ clk_prepare_enable(sensor->sensor_clk);
++ power_up_camera(cam);
++ }
++
++ file->private_data = dev;
++
++oops:
++ up(&cam->busy_lock);
++ return err;
++}
++
++/*!
++ * V4L interface - close function
++ *
++ * @param file struct file *
++ *
++ * @return 0 success
++ */
++static int mxc_v4l_close(struct file *file)
++{
++ struct video_device *dev = video_devdata(file);
++ int err = 0;
++ cam_data *cam = video_get_drvdata(dev);
++ struct sensor_data *sensor;
++ pr_debug("%s\n", __func__);
++
++ if (!cam) {
++ pr_err("%s: cam_data not found!\n", __func__);
++ return -EBADF;
++ }
++
++ if (!cam->sensor) {
++ pr_err("%s: Internal error, camera is not found!\n",
++ __func__);
++ return -EBADF;
++ }
++
++ sensor = cam->sensor->priv;
++ if (!sensor) {
++ pr_err("%s: Internal error, sensor_data is not found!\n",
++ __func__);
++ return -EBADF;
++ }
++
++ down(&cam->busy_lock);
++
++ /* for the case somebody hit the ctrl C */
++ if (cam->overlay_pid == current->pid && cam->overlay_on) {
++ err = stop_preview(cam);
++ cam->overlay_on = false;
++ }
++
++ if (--cam->open_count == 0) {
++ if (cam->capture_pid == current->pid) {
++ err |= mxc_streamoff(cam);
++ wake_up_interruptible(&cam->enc_queue);
++ }
++ if (!IS_ERR(sensor->sensor_clk))
++ clk_disable_unprepare(sensor->sensor_clk);
++ wait_event_interruptible(cam->power_queue,
++ cam->low_power == false);
++ pr_debug("mxc_v4l_close: release resource\n");
++
++ if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++ err |= csi_enc_deselect(cam);
++#endif
++ } else if (strcmp(mxc_capture_inputs[cam->current_input].name,
++ "CSI IC MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
++ err |= prp_enc_deselect(cam);
++#endif
++ }
++
++ mxc_free_frame_buf(cam);
++ file->private_data = NULL;
++
++ /* capture off */
++ wake_up_interruptible(&cam->enc_queue);
++ mxc_free_frames(cam);
++ cam->enc_counter++;
++ power_off_camera(cam);
++
++ if (cam->csi_in_use) {
++ int csi_bit = (cam->ipu_id << 1) | cam->csi;
++
++ clear_bit(csi_bit, &csi_in_use);
++ cam->csi_in_use = 0;
++ }
++ }
++
++ up(&cam->busy_lock);
++
++ return err;
++}
++
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC) || \
++ defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) || \
++ defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++/*
++ * V4L interface - read function
++ *
++ * @param file struct file *
++ * @param read buf char *
++ * @param count size_t
++ * @param ppos structure loff_t *
++ *
++ * @return bytes read
++ */
++static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count,
++ loff_t *ppos)
++{
++ int err = 0;
++ u8 *v_address[2];
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ /* Stop the viewfinder */
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++
++ v_address[0] = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->still_buf[0],
++ GFP_DMA | GFP_KERNEL);
++
++ v_address[1] = dma_alloc_coherent(0,
++ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage),
++ &cam->still_buf[1],
++ GFP_DMA | GFP_KERNEL);
++
++ if (!v_address[0] || !v_address[1]) {
++ err = -ENOBUFS;
++ goto exit0;
++ }
++
++ err = prp_still_select(cam);
++ if (err != 0) {
++ err = -EIO;
++ goto exit0;
++ }
++
++ cam->still_counter = 0;
++ err = cam->csi_start(cam);
++ if (err != 0) {
++ err = -EIO;
++ goto exit1;
++ }
++
++ if (!wait_event_interruptible_timeout(cam->still_queue,
++ cam->still_counter != 0,
++ 10 * HZ)) {
++ pr_err("ERROR: v4l2 capture: mxc_v4l_read timeout counter %x\n",
++ cam->still_counter);
++ err = -ETIME;
++ goto exit1;
++ }
++ err = copy_to_user(buf, v_address[1], cam->v2f.fmt.pix.sizeimage);
++
++exit1:
++ prp_still_deselect(cam);
++
++exit0:
++ if (v_address[0] != 0)
++ dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[0],
++ cam->still_buf[0]);
++ if (v_address[1] != 0)
++ dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[1],
++ cam->still_buf[1]);
++
++ cam->still_buf[0] = cam->still_buf[1] = 0;
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++
++ up(&cam->busy_lock);
++ if (err < 0)
++ return err;
++
++ return cam->v2f.fmt.pix.sizeimage - err;
++}
++#endif
++
++/*!
++ * V4L interface - ioctl function
++ *
++ * @param file struct file*
++ *
++ * @param ioctlnr unsigned int
++ *
++ * @param arg void*
++ *
++ * @return 0 success, ENODEV for invalid device instance,
++ * -1 for other errors.
++ */
++static long mxc_v4l_do_ioctl(struct file *file,
++ unsigned int ioctlnr, void *arg)
++{
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ int retval = 0;
++ unsigned long lock_flags;
++
++ pr_debug("%s: %x ipu%d/csi%d\n", __func__, ioctlnr, cam->ipu_id, cam->csi);
++ wait_event_interruptible(cam->power_queue, cam->low_power == false);
++ /* make this _really_ smp-safe */
++ if (ioctlnr != VIDIOC_DQBUF)
++ if (down_interruptible(&cam->busy_lock))
++ return -EBUSY;
++
++ switch (ioctlnr) {
++ /*!
++ * V4l2 VIDIOC_QUERYCAP ioctl
++ */
++ case VIDIOC_QUERYCAP: {
++ struct v4l2_capability *cap = arg;
++ pr_debug(" case VIDIOC_QUERYCAP\n");
++ strcpy(cap->driver, "mxc_v4l2");
++ cap->version = KERNEL_VERSION(0, 1, 11);
++ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
++ V4L2_CAP_VIDEO_OVERLAY |
++ V4L2_CAP_STREAMING |
++ V4L2_CAP_READWRITE;
++ cap->card[0] = '\0';
++ cap->bus_info[0] = '\0';
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_FMT ioctl
++ */
++ case VIDIOC_G_FMT: {
++ struct v4l2_format *gf = arg;
++ pr_debug(" case VIDIOC_G_FMT\n");
++ retval = mxc_v4l2_g_fmt(cam, gf);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_FMT ioctl
++ */
++ /* XXX: workaround for gstreamer */
++ case VIDIOC_TRY_FMT: {
++ struct v4l2_format *sf = arg;
++ pr_debug(" case VIDIOC_TRY_FMT\n");
++ retval = mxc_v4l2_s_fmt(cam, sf, true);
++ break;
++ }
++ case VIDIOC_S_FMT: {
++ struct v4l2_format *sf = arg;
++ pr_debug(" case VIDIOC_S_FMT\n");
++ retval = mxc_v4l2_s_fmt(cam, sf, false);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_REQBUFS ioctl
++ */
++ case VIDIOC_REQBUFS: {
++ struct v4l2_requestbuffers *req = arg;
++ pr_debug(" case VIDIOC_REQBUFS\n");
++
++ if (req->count > FRAME_NUM) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
++ "not enough buffers\n");
++ req->count = FRAME_NUM;
++ }
++
++ if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: "
++ "wrong buffer type\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ mxc_streamoff(cam);
++ if (req->memory & V4L2_MEMORY_MMAP) {
++ mxc_free_frame_buf(cam);
++ retval = mxc_allocate_frame_buf(cam, req->count);
++ }
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_QUERYBUF ioctl
++ */
++ case VIDIOC_QUERYBUF: {
++ struct v4l2_buffer *buf = arg;
++ int index = buf->index;
++ pr_debug(" case VIDIOC_QUERYBUF\n");
++
++ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
++ pr_err("ERROR: v4l2 capture: "
++ "VIDIOC_QUERYBUFS: "
++ "wrong buffer type\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (buf->memory & V4L2_MEMORY_MMAP) {
++ memset(buf, 0, sizeof(buf));
++ buf->index = index;
++ }
++
++ down(&cam->param_lock);
++ if (buf->memory & V4L2_MEMORY_USERPTR) {
++ mxc_v4l2_release_bufs(cam);
++ retval = mxc_v4l2_prepare_bufs(cam, buf);
++ }
++
++ if (buf->memory & V4L2_MEMORY_MMAP)
++ retval = mxc_v4l2_buffer_status(cam, buf);
++ up(&cam->param_lock);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_QBUF ioctl
++ */
++ case VIDIOC_QBUF: {
++ struct v4l2_buffer *buf = arg;
++ int index = buf->index;
++ pr_debug(" case VIDIOC_QBUF\n");
++
++ spin_lock_irqsave(&cam->queue_int_lock, lock_flags);
++ if ((cam->frame[index].buffer.flags & 0x7) ==
++ V4L2_BUF_FLAG_MAPPED) {
++ cam->frame[index].buffer.flags |=
++ V4L2_BUF_FLAG_QUEUED;
++ list_add_tail(&cam->frame[index].queue,
++ &cam->ready_q);
++ } else if (cam->frame[index].buffer.
++ flags & V4L2_BUF_FLAG_QUEUED) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
++ "buffer already queued\n");
++ retval = -EINVAL;
++ } else if (cam->frame[index].buffer.
++ flags & V4L2_BUF_FLAG_DONE) {
++ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: "
++ "overwrite done buffer.\n");
++ cam->frame[index].buffer.flags &=
++ ~V4L2_BUF_FLAG_DONE;
++ cam->frame[index].buffer.flags |=
++ V4L2_BUF_FLAG_QUEUED;
++ retval = -EINVAL;
++ }
++
++ buf->flags = cam->frame[index].buffer.flags;
++ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_DQBUF ioctl
++ */
++ case VIDIOC_DQBUF: {
++ struct v4l2_buffer *buf = arg;
++ pr_debug(" case VIDIOC_DQBUF\n");
++
++ if ((cam->enc_counter == 0) &&
++ (file->f_flags & O_NONBLOCK)) {
++ retval = -EAGAIN;
++ break;
++ }
++
++ retval = mxc_v4l_dqueue(cam, buf);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_STREAMON ioctl
++ */
++ case VIDIOC_STREAMON: {
++ pr_debug(" case VIDIOC_STREAMON\n");
++ retval = mxc_streamon(cam);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_STREAMOFF ioctl
++ */
++ case VIDIOC_STREAMOFF: {
++ pr_debug(" case VIDIOC_STREAMOFF\n");
++ retval = mxc_streamoff(cam);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_CTRL ioctl
++ */
++ case VIDIOC_G_CTRL: {
++ pr_debug(" case VIDIOC_G_CTRL\n");
++ retval = mxc_v4l2_g_ctrl(cam, arg);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_CTRL ioctl
++ */
++ case VIDIOC_S_CTRL: {
++ pr_debug(" case VIDIOC_S_CTRL\n");
++ retval = mxc_v4l2_s_ctrl(cam, arg);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_CROPCAP ioctl
++ */
++ case VIDIOC_CROPCAP: {
++ struct v4l2_cropcap *cap = arg;
++ pr_debug(" case VIDIOC_CROPCAP\n");
++ if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
++ retval = -EINVAL;
++ break;
++ }
++ cap->bounds = cam->crop_bounds;
++ cap->defrect = cam->crop_defrect;
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_CROP ioctl
++ */
++ case VIDIOC_G_CROP: {
++ struct v4l2_crop *crop = arg;
++ pr_debug(" case VIDIOC_G_CROP\n");
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
++ retval = -EINVAL;
++ break;
++ }
++ crop->c = cam->crop_current;
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_CROP ioctl
++ */
++ case VIDIOC_S_CROP: {
++ struct v4l2_crop *crop = arg;
++ struct v4l2_rect *b = &cam->crop_bounds;
++ pr_debug(" case VIDIOC_S_CROP\n");
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
++ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) {
++ retval = -EINVAL;
++ break;
++ }
++
++ crop->c.top = (crop->c.top < b->top) ? b->top
++ : crop->c.top;
++ if (crop->c.top > b->top + b->height)
++ crop->c.top = b->top + b->height - 1;
++ if (crop->c.height > b->top + b->height - crop->c.top)
++ crop->c.height =
++ b->top + b->height - crop->c.top;
++
++ crop->c.left = (crop->c.left < b->left) ? b->left
++ : crop->c.left;
++ if (crop->c.left > b->left + b->width)
++ crop->c.left = b->left + b->width - 1;
++ if (crop->c.width > b->left - crop->c.left + b->width)
++ crop->c.width =
++ b->left - crop->c.left + b->width;
++
++ crop->c.width -= crop->c.width % 8;
++ crop->c.left -= crop->c.left % 4;
++ cam->crop_current = crop->c;
++
++ pr_debug(" Cropping Input to ipu size %d x %d\n",
++ cam->crop_current.width,
++ cam->crop_current.height);
++ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width,
++ cam->crop_current.height,
++ cam->csi);
++ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left,
++ cam->crop_current.top,
++ cam->csi);
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_OVERLAY ioctl
++ */
++ case VIDIOC_OVERLAY: {
++ int *on = arg;
++ pr_debug(" VIDIOC_OVERLAY on=%d\n", *on);
++ if (*on) {
++ cam->overlay_on = true;
++ cam->overlay_pid = current->pid;
++ retval = start_preview(cam);
++ }
++ if (!*on) {
++ retval = stop_preview(cam);
++ cam->overlay_on = false;
++ }
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_G_FBUF ioctl
++ */
++ case VIDIOC_G_FBUF: {
++ struct v4l2_framebuffer *fb = arg;
++ pr_debug(" case VIDIOC_G_FBUF\n");
++ *fb = cam->v4l2_fb;
++ fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY;
++ break;
++ }
++
++ /*!
++ * V4l2 VIDIOC_S_FBUF ioctl
++ */
++ case VIDIOC_S_FBUF: {
++ struct v4l2_framebuffer *fb = arg;
++ pr_debug(" case VIDIOC_S_FBUF\n");
++ cam->v4l2_fb = *fb;
++ break;
++ }
++
++ case VIDIOC_G_PARM: {
++ struct v4l2_streamparm *parm = arg;
++ pr_debug(" case VIDIOC_G_PARM\n");
++ if (cam->sensor)
++ retval = vidioc_int_g_parm(cam->sensor, parm);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ case VIDIOC_S_PARM: {
++ struct v4l2_streamparm *parm = arg;
++ pr_debug(" case VIDIOC_S_PARM\n");
++ if (cam->sensor)
++ retval = mxc_v4l2_s_param(cam, parm);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ /* linux v4l2 bug, kernel c0485619 user c0405619 */
++ case VIDIOC_ENUMSTD: {
++ struct v4l2_standard *e = arg;
++ pr_debug(" case VIDIOC_ENUMSTD\n");
++ if (e->index > 0) {
++ retval = -EINVAL;
++ break;
++ }
++ *e = cam->standard;
++ break;
++ }
++
++ case VIDIOC_G_STD: {
++ v4l2_std_id *e = arg;
++ pr_debug(" case VIDIOC_G_STD\n");
++ if (cam->sensor)
++ retval = mxc_v4l2_g_std(cam, e);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ case VIDIOC_S_STD: {
++ v4l2_std_id *e = arg;
++ pr_debug(" case VIDIOC_S_STD\n");
++ retval = mxc_v4l2_s_std(cam, *e);
++
++ break;
++ }
++
++ case VIDIOC_ENUMOUTPUT: {
++ struct v4l2_output *output = arg;
++ pr_debug(" case VIDIOC_ENUMOUTPUT\n");
++ if (output->index >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++ *output = mxc_capture_outputs[output->index];
++
++ break;
++ }
++ case VIDIOC_G_OUTPUT: {
++ int *p_output_num = arg;
++ pr_debug(" case VIDIOC_G_OUTPUT\n");
++ *p_output_num = cam->output;
++ break;
++ }
++
++ case VIDIOC_S_OUTPUT: {
++ int *p_output_num = arg;
++ pr_debug(" case VIDIOC_S_OUTPUT\n");
++ if (*p_output_num >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++ cam->output = *p_output_num;
++ break;
++ }
++
++ case VIDIOC_ENUMINPUT: {
++ struct v4l2_input *input = arg;
++ pr_debug(" case VIDIOC_ENUMINPUT\n");
++ if (input->index >= MXC_V4L2_CAPTURE_NUM_INPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++ *input = mxc_capture_inputs[input->index];
++ break;
++ }
++
++ case VIDIOC_G_INPUT: {
++ int *index = arg;
++ pr_debug(" case VIDIOC_G_INPUT\n");
++ *index = cam->current_input;
++ break;
++ }
++
++ case VIDIOC_S_INPUT: {
++ int *index = arg;
++ pr_debug(" case VIDIOC_S_INPUT\n");
++ if (*index >= MXC_V4L2_CAPTURE_NUM_INPUTS) {
++ retval = -EINVAL;
++ break;
++ }
++
++ if (*index == cam->current_input)
++ break;
++
++ if ((mxc_capture_inputs[cam->current_input].status &
++ V4L2_IN_ST_NO_POWER) == 0) {
++ retval = mxc_streamoff(cam);
++ if (retval)
++ break;
++ mxc_capture_inputs[cam->current_input].status |=
++ V4L2_IN_ST_NO_POWER;
++ }
++
++ if (strcmp(mxc_capture_inputs[*index].name, "CSI MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE)
++ retval = csi_enc_select(cam);
++ if (retval)
++ break;
++#endif
++ } else if (strcmp(mxc_capture_inputs[*index].name,
++ "CSI IC MEM") == 0) {
++#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE)
++ retval = prp_enc_select(cam);
++ if (retval)
++ break;
++#endif
++ }
++
++ mxc_capture_inputs[*index].status &= ~V4L2_IN_ST_NO_POWER;
++ cam->current_input = *index;
++ break;
++ }
++ case VIDIOC_ENUM_FMT: {
++ struct v4l2_fmtdesc *f = arg;
++ if (cam->sensor)
++ retval = vidioc_int_enum_fmt_cap(cam->sensor, f);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_ENUM_FRAMESIZES: {
++ struct v4l2_frmsizeenum *fsize = arg;
++ if (cam->sensor)
++ retval = vidioc_int_enum_framesizes(cam->sensor, fsize);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_ENUM_FRAMEINTERVALS: {
++ struct v4l2_frmivalenum *fival = arg;
++ if (cam->sensor) {
++ retval = vidioc_int_enum_frameintervals(cam->sensor,
++ fival);
++ } else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++ case VIDIOC_DBG_G_CHIP_IDENT: {
++ struct v4l2_dbg_chip_ident *p = arg;
++ p->ident = V4L2_IDENT_NONE;
++ p->revision = 0;
++ if (cam->sensor)
++ retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p);
++ else {
++ pr_err("ERROR: v4l2 capture: slave not found!\n");
++ retval = -ENODEV;
++ }
++ break;
++ }
++
++ case VIDIOC_SEND_COMMAND: {
++ retval = mxc_v4l2_send_command(cam, arg);
++ break;
++ }
++
++ /* XXX: workaround for gstreamer */
++/* case VIDIOC_TRY_FMT: */
++ case VIDIOC_QUERYCTRL:
++ case VIDIOC_G_TUNER:
++ case VIDIOC_S_TUNER:
++ case VIDIOC_G_FREQUENCY:
++ case VIDIOC_S_FREQUENCY:
++ default:
++ pr_debug(" case default or not supported\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (ioctlnr != VIDIOC_DQBUF)
++ up(&cam->busy_lock);
++ return retval;
++}
++
++/*
++ * V4L interface - ioctl function
++ *
++ * @return None
++ */
++static long mxc_v4l_ioctl(struct file *file, unsigned int cmd,
++ unsigned long arg)
++{
++ pr_debug("%s\n", __func__);
++ return video_usercopy(file, cmd, arg, mxc_v4l_do_ioctl);
++}
++
++/*!
++ * V4L interface - mmap function
++ *
++ * @param file structure file *
++ *
++ * @param vma structure vm_area_struct *
++ *
++ * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error
++ */
++static int mxc_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ struct video_device *dev = video_devdata(file);
++ unsigned long size;
++ int res = 0;
++ cam_data *cam = video_get_drvdata(dev);
++
++ pr_debug("%s:pgoff=0x%lx, start=0x%lx, end=0x%lx\n", __func__,
++ vma->vm_pgoff, vma->vm_start, vma->vm_end);
++
++ /* make this _really_ smp-safe */
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ size = vma->vm_end - vma->vm_start;
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start,
++ vma->vm_pgoff, size, vma->vm_page_prot)) {
++ pr_err("ERROR: v4l2 capture: mxc_mmap: "
++ "remap_pfn_range failed\n");
++ res = -ENOBUFS;
++ goto mxc_mmap_exit;
++ }
++
++ vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */
++
++mxc_mmap_exit:
++ up(&cam->busy_lock);
++ return res;
++}
++
++/*!
++ * V4L interface - poll function
++ *
++ * @param file structure file *
++ *
++ * @param wait structure poll_table_struct *
++ *
++ * @return status POLLIN | POLLRDNORM
++ */
++static unsigned int mxc_poll(struct file *file, struct poll_table_struct *wait)
++{
++ struct video_device *dev = video_devdata(file);
++ cam_data *cam = video_get_drvdata(dev);
++ wait_queue_head_t *queue = NULL;
++ int res = POLLIN | POLLRDNORM;
++
++ pr_debug("%s\n", __func__);
++
++ if (down_interruptible(&cam->busy_lock))
++ return -EINTR;
++
++ queue = &cam->enc_queue;
++ poll_wait(file, queue, wait);
++
++ up(&cam->busy_lock);
++
++ return res;
++}
++
++/*!
++ * This structure defines the functions to be called in this driver.
++ */
++static struct v4l2_file_operations mxc_v4l_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_v4l_open,
++ .release = mxc_v4l_close,
++ .read = mxc_v4l_read,
++ .ioctl = mxc_v4l_ioctl,
++ .mmap = mxc_mmap,
++ .poll = mxc_poll,
++};
++
++static struct video_device mxc_v4l_template = {
++ .name = "Mxc Camera",
++ .fops = &mxc_v4l_fops,
++ .release = video_device_release,
++};
++
++/*!
++ * This function can be used to release any platform data on closing.
++ */
++static void camera_platform_release(struct device *device)
++{
++}
++
++/*!
++ * Camera V4l2 callback function.
++ *
++ * @param mask u32
++ *
++ * @param dev void device structure
++ *
++ * @return status
++ */
++static void camera_callback(u32 mask, void *dev)
++{
++ struct mxc_v4l_frame *done_frame;
++ struct mxc_v4l_frame *ready_frame;
++ struct timeval cur_time;
++
++ cam_data *cam = (cam_data *) dev;
++ if (cam == NULL)
++ return;
++
++ pr_debug("%s\n", __func__);
++
++ spin_lock(&cam->queue_int_lock);
++ spin_lock(&cam->dqueue_int_lock);
++ if (!list_empty(&cam->working_q)) {
++ do_gettimeofday(&cur_time);
++
++ done_frame = list_entry(cam->working_q.next,
++ struct mxc_v4l_frame,
++ queue);
++
++ if (done_frame->ipu_buf_num != cam->local_buf_num)
++ goto next;
++
++ /*
++ * Set the current time to done frame buffer's
++ * timestamp. Users can use this information to judge
++ * the frame's usage.
++ */
++ done_frame->buffer.timestamp = cur_time;
++
++ if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) {
++ done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE;
++ done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED;
++
++ /* Added to the done queue */
++ list_del(cam->working_q.next);
++ list_add_tail(&done_frame->queue, &cam->done_q);
++
++ /* Wake up the queue */
++ cam->enc_counter++;
++ wake_up_interruptible(&cam->enc_queue);
++ } else
++ pr_err("ERROR: v4l2 capture: camera_callback: "
++ "buffer not queued\n");
++ }
++
++next:
++ if (!list_empty(&cam->ready_q)) {
++ ready_frame = list_entry(cam->ready_q.next,
++ struct mxc_v4l_frame,
++ queue);
++ if (cam->enc_update_eba)
++ if (cam->enc_update_eba(cam->ipu,
++ ready_frame->buffer.m.offset,
++ &cam->ping_pong_csi) == 0) {
++ list_del(cam->ready_q.next);
++ list_add_tail(&ready_frame->queue,
++ &cam->working_q);
++ ready_frame->ipu_buf_num = cam->local_buf_num;
++ }
++ } else {
++ if (cam->enc_update_eba)
++ cam->enc_update_eba(
++ cam->ipu, cam->dummy_frame.buffer.m.offset,
++ &cam->ping_pong_csi);
++ }
++
++ cam->local_buf_num = (cam->local_buf_num == 0) ? 1 : 0;
++ spin_unlock(&cam->dqueue_int_lock);
++ spin_unlock(&cam->queue_int_lock);
++
++ return;
++}
++
++/*!
++ * initialize cam_data structure
++ *
++ * @param cam structure cam_data *
++ *
++ * @return status 0 Success
++ */
++static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
++{
++ const struct of_device_id *of_id =
++ of_match_device(mxc_v4l2_dt_ids, &pdev->dev);
++ struct device_node *np = pdev->dev.of_node;
++ int ipu_id, csi_id, mclk_source, mipi_camera, def_input;
++ int ret = 0;
++ struct v4l2_device *v4l2_dev;
++ static int camera_id;
++
++ pr_debug("%s\n", __func__);
++
++ ret = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (ret) {
++ dev_err(&pdev->dev, "ipu_id missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "csi_id", &csi_id);
++ if (ret) {
++ dev_err(&pdev->dev, "csi_id missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "mclk_source", &mclk_source);
++ if (ret) {
++ dev_err(&pdev->dev, "sensor mclk missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "mipi_camera", &mipi_camera);
++ if (ret)
++ mipi_camera = 0;
++
++ ret = of_property_read_u32(np, "default_input", &def_input);
++ if (ret || (def_input != 0 && def_input != 1))
++ def_input = 0;
++
++ /* Default everything to 0 */
++ memset(cam, 0, sizeof(cam_data));
++
++ /* get devtype to distinguish if the cpu is imx5 or imx6
++ * IMX5_V4L2 specify the cpu is imx5
++ * IMX6_V4L2 specify the cpu is imx6q or imx6sdl
++ */
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ cam->devtype = pdev->id_entry->driver_data;
++
++ cam->ipu = ipu_get_soc(ipu_id);
++ if (cam->ipu == NULL) {
++ pr_err("ERROR: v4l2 capture: failed to get ipu\n");
++ return -EINVAL;
++ } else if (cam->ipu == ERR_PTR(-ENODEV)) {
++ pr_err("ERROR: v4l2 capture: get invalid ipu\n");
++ return -ENODEV;
++ }
++
++ init_MUTEX(&cam->param_lock);
++ init_MUTEX(&cam->busy_lock);
++ INIT_DELAYED_WORK(&cam->power_down_work, power_down_callback);
++
++ cam->video_dev = video_device_alloc();
++ if (cam->video_dev == NULL)
++ return -ENODEV;
++
++ *(cam->video_dev) = mxc_v4l_template;
++
++ video_set_drvdata(cam->video_dev, cam);
++ dev_set_drvdata(&pdev->dev, (void *)cam);
++ cam->video_dev->minor = -1;
++
++ v4l2_dev = kzalloc(sizeof(*v4l2_dev), GFP_KERNEL);
++ if (!v4l2_dev) {
++ dev_err(&pdev->dev, "failed to allocate v4l2_dev structure\n");
++ video_device_release(cam->video_dev);
++ return -ENOMEM;
++ }
++
++ if (v4l2_device_register(&pdev->dev, v4l2_dev) < 0) {
++ dev_err(&pdev->dev, "register v4l2 device failed\n");
++ video_device_release(cam->video_dev);
++ kfree(v4l2_dev);
++ return -ENODEV;
++ }
++ cam->video_dev->v4l2_dev = v4l2_dev;
++
++ init_waitqueue_head(&cam->enc_queue);
++ init_waitqueue_head(&cam->still_queue);
++
++ /* setup cropping */
++ cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = 640;
++ cam->crop_bounds.top = 0;
++ cam->crop_bounds.height = 480;
++ cam->crop_current = cam->crop_defrect = cam->crop_bounds;
++ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width,
++ cam->crop_current.height, cam->csi);
++ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left,
++ cam->crop_current.top, cam->csi);
++ cam->streamparm.parm.capture.capturemode = 0;
++
++ cam->standard.index = 0;
++ cam->standard.id = V4L2_STD_UNKNOWN;
++ cam->standard.frameperiod.denominator = 30;
++ cam->standard.frameperiod.numerator = 1;
++ cam->standard.framelines = 480;
++ cam->standard_autodetect = true;
++ cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod;
++ cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
++ cam->overlay_on = false;
++ cam->capture_on = false;
++ cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY;
++
++ cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2;
++ cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2;
++ cam->v2f.fmt.pix.width = 288;
++ cam->v2f.fmt.pix.height = 352;
++ cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
++ cam->win.w.width = 160;
++ cam->win.w.height = 160;
++ cam->win.w.left = 0;
++ cam->win.w.top = 0;
++
++ cam->ipu_id = ipu_id;
++ cam->csi = csi_id;
++ cam->mipi_camera = mipi_camera;
++ cam->mclk_source = mclk_source;
++ cam->mclk_on[cam->mclk_source] = false;
++ cam->current_input = def_input;
++
++ cam->enc_callback = camera_callback;
++ init_waitqueue_head(&cam->power_queue);
++ spin_lock_init(&cam->queue_int_lock);
++ spin_lock_init(&cam->dqueue_int_lock);
++
++ cam->dummy_frame.vaddress = dma_alloc_coherent(0,
++ SZ_8M, &cam->dummy_frame.paddress,
++ GFP_DMA | GFP_KERNEL);
++ if (cam->dummy_frame.vaddress == 0)
++ pr_err("ERROR: v4l2 capture: Allocate dummy frame "
++ "failed.\n");
++ cam->dummy_frame.buffer.length = SZ_8M;
++
++ cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL);
++ cam->self->module = THIS_MODULE;
++ sprintf(cam->self->name, "mxc_v4l2_cap%d", camera_id++);
++ cam->self->type = v4l2_int_type_master;
++ cam->self->u.master = &mxc_v4l2_master;
++
++ return 0;
++}
++
++static ssize_t show_streaming(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct video_device *video_dev = container_of(dev,
++ struct video_device, dev);
++ cam_data *cam = video_get_drvdata(video_dev);
++
++ if (cam->capture_on)
++ return sprintf(buf, "stream on\n");
++ else
++ return sprintf(buf, "stream off\n");
++}
++static DEVICE_ATTR(fsl_v4l2_capture_property, S_IRUGO, show_streaming, NULL);
++
++static ssize_t show_overlay(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct video_device *video_dev = container_of(dev,
++ struct video_device, dev);
++ cam_data *cam = video_get_drvdata(video_dev);
++
++ if (cam->overlay_on)
++ return sprintf(buf, "overlay on\n");
++ else
++ return sprintf(buf, "overlay off\n");
++}
++static DEVICE_ATTR(fsl_v4l2_overlay_property, S_IRUGO, show_overlay, NULL);
++
++static ssize_t show_csi(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct video_device *video_dev = container_of(dev,
++ struct video_device, dev);
++ cam_data *cam = video_get_drvdata(video_dev);
++
++ return sprintf(buf, "ipu%d_csi%d\n", cam->ipu_id, cam->csi);
++}
++static DEVICE_ATTR(fsl_csi_property, S_IRUGO, show_csi, NULL);
++
++/*!
++ * This function is called to probe the devices if registered.
++ *
++ * @param pdev the device structure used to give information on which device
++ * to probe
++ *
++ * @return The function returns 0 on success and -1 on failure.
++ */
++static int mxc_v4l2_probe(struct platform_device *pdev)
++{
++ int err;
++
++ /* Create cam and initialize it. */
++ cam_data *cam = kmalloc(sizeof(cam_data), GFP_KERNEL);
++ if (cam == NULL) {
++ pr_err("ERROR: v4l2 capture: failed to register camera\n");
++ return -1;
++ }
++
++ err = init_camera_struct(cam, pdev);
++ if (err)
++ return err;
++ pdev->dev.release = camera_platform_release;
++
++ /* Set up the v4l2 device and register it*/
++ cam->self->priv = cam;
++ v4l2_int_device_register(cam->self);
++
++ /* register v4l video device */
++ if (video_register_device(cam->video_dev, VFL_TYPE_GRABBER, video_nr)
++ < 0) {
++ kfree(cam);
++ cam = NULL;
++ pr_err("ERROR: v4l2 capture: video_register_device failed\n");
++ return -1;
++ }
++
++ pr_info("V4L2 device '%s' on IPU%d_CSI%d registered as %s\n",
++ cam->video_dev->name,
++ cam->ipu_id + 1, cam->csi,
++ video_device_node_name(cam->video_dev));
++
++ if (device_create_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_capture_property))
++ dev_err(&pdev->dev, "Error on creating sysfs file"
++ " for capture\n");
++
++ if (device_create_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_overlay_property))
++ dev_err(&pdev->dev, "Error on creating sysfs file"
++ " for overlay\n");
++
++ if (device_create_file(&cam->video_dev->dev,
++ &dev_attr_fsl_csi_property))
++ dev_err(&pdev->dev, "Error on creating sysfs file"
++ " for csi number\n");
++
++ return 0;
++}
++
++/*!
++ * This function is called to remove the devices when device unregistered.
++ *
++ * @param pdev the device structure used to give information on which device
++ * to remove
++ *
++ * @return The function returns 0 on success and -1 on failure.
++ */
++static int mxc_v4l2_remove(struct platform_device *pdev)
++{
++ cam_data *cam = (cam_data *)platform_get_drvdata(pdev);
++
++ if (cam->open_count) {
++ pr_err("ERROR: v4l2 capture:camera open "
++ "-- setting ops to NULL\n");
++ return -EBUSY;
++ } else {
++ struct v4l2_device *v4l2_dev = cam->video_dev->v4l2_dev;
++ device_remove_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_capture_property);
++ device_remove_file(&cam->video_dev->dev,
++ &dev_attr_fsl_v4l2_overlay_property);
++ device_remove_file(&cam->video_dev->dev,
++ &dev_attr_fsl_csi_property);
++
++ pr_info("V4L2 freeing image input device\n");
++ v4l2_int_device_unregister(cam->self);
++ video_unregister_device(cam->video_dev);
++
++ if (cam->dummy_frame.vaddress != 0) {
++ dma_free_coherent(0, cam->dummy_frame.buffer.length,
++ cam->dummy_frame.vaddress,
++ cam->dummy_frame.paddress);
++ cam->dummy_frame.vaddress = 0;
++ }
++
++ mxc_free_frame_buf(cam);
++ kfree(cam);
++
++ v4l2_device_unregister(v4l2_dev);
++ kfree(v4l2_dev);
++ }
++
++ pr_info("V4L2 unregistering video\n");
++ return 0;
++}
++
++/*!
++ * This function is called to put the sensor in a low power state.
++ * Refer to the document driver-model/driver.txt in the kernel source tree
++ * for more information.
++ *
++ * @param pdev the device structure used to give information on which I2C
++ * to suspend
++ * @param state the power state the device is entering
++ *
++ * @return The function returns 0 on success and -1 on failure.
++ */
++static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ cam_data *cam = platform_get_drvdata(pdev);
++
++ pr_debug("%s\n", __func__);
++
++ if (cam == NULL)
++ return -1;
++
++ down(&cam->busy_lock);
++
++ cam->low_power = true;
++
++ if (cam->overlay_on == true)
++ stop_preview(cam);
++ if ((cam->capture_on == true) && cam->enc_disable)
++ cam->enc_disable(cam);
++
++ if (cam->sensor && cam->open_count) {
++ if (cam->mclk_on[cam->mclk_source]) {
++ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
++ cam->mclk_source,
++ false, false);
++ cam->mclk_on[cam->mclk_source] = false;
++ }
++ vidioc_int_s_power(cam->sensor, 0);
++ }
++
++ up(&cam->busy_lock);
++
++ return 0;
++}
++
++/*!
++ * This function is called to bring the sensor back from a low power state.
++ * Refer to the document driver-model/driver.txt in the kernel source tree
++ * for more information.
++ *
++ * @param pdev the device structure
++ *
++ * @return The function returns 0 on success and -1 on failure
++ */
++static int mxc_v4l2_resume(struct platform_device *pdev)
++{
++ cam_data *cam = platform_get_drvdata(pdev);
++
++ pr_debug("%s\n", __func__);
++
++ if (cam == NULL)
++ return -1;
++
++ down(&cam->busy_lock);
++
++ cam->low_power = false;
++ wake_up_interruptible(&cam->power_queue);
++
++ if (cam->sensor && cam->open_count) {
++ if ((cam->overlay_on == true) || (cam->capture_on == true))
++ vidioc_int_s_power(cam->sensor, 1);
++
++ if (!cam->mclk_on[cam->mclk_source]) {
++ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
++ cam->mclk_source,
++ true, true);
++ cam->mclk_on[cam->mclk_source] = true;
++ }
++ }
++
++ if (cam->overlay_on == true)
++ start_preview(cam);
++ if (cam->capture_on == true)
++ mxc_streamon(cam);
++
++ up(&cam->busy_lock);
++
++ return 0;
++}
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxc_v4l2_driver = {
++ .driver = {
++ .name = "mxc_v4l2_capture",
++ .owner = THIS_MODULE,
++ .of_match_table = mxc_v4l2_dt_ids,
++ },
++ .id_table = imx_v4l2_devtype,
++ .probe = mxc_v4l2_probe,
++ .remove = mxc_v4l2_remove,
++ .suspend = mxc_v4l2_suspend,
++ .resume = mxc_v4l2_resume,
++ .shutdown = NULL,
++};
++
++/*!
++ * Initializes the camera driver.
++ */
++static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
++{
++ cam_data *cam = slave->u.slave->master->priv;
++ struct v4l2_format cam_fmt;
++ int i;
++ struct sensor_data *sdata = slave->priv;
++
++ pr_debug("%s:slave.name = %s, master.name = %s\n", __func__,
++ slave->name, slave->u.slave->master->name);
++
++ if (slave == NULL) {
++ pr_err("ERROR: v4l2 capture: slave parameter not valid.\n");
++ return -1;
++ }
++
++ if ((sdata->ipu_id != cam->ipu_id) || (sdata->csi != cam->csi) || (sdata->mipi_camera != cam->mipi_camera)) {
++ pr_info("%s: ipu(%d:%d)/csi(%d:%d)/mipi(%d:%d) doesn't match\n", __func__,
++ sdata->ipu_id, cam->ipu_id, sdata->csi, cam->csi, sdata->mipi_camera, cam->mipi_camera);
++ return -1;
++ }
++
++ cam->sensor = slave;
++
++ if (cam->sensor_index < MXC_SENSOR_NUM) {
++ cam->all_sensors[cam->sensor_index] = slave;
++ cam->sensor_index++;
++ } else {
++ pr_err("ERROR: v4l2 capture: slave number exceeds "
++ "the maximum.\n");
++ return -1;
++ }
++
++ for (i = 0; i < cam->sensor_index; i++) {
++ pr_err("%s: %x\n", __func__, i);
++ vidioc_int_dev_exit(cam->all_sensors[i]);
++ vidioc_int_s_power(cam->all_sensors[i], 0);
++ }
++
++ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt);
++
++ /* Used to detect TV in (type 1) vs. camera (type 0)*/
++ cam->device_type = cam_fmt.fmt.pix.priv;
++
++ /* Set the input size to the ipu for this device */
++ cam->crop_bounds.top = cam->crop_bounds.left = 0;
++ cam->crop_bounds.width = cam_fmt.fmt.pix.width;
++ cam->crop_bounds.height = cam_fmt.fmt.pix.height;
++
++ /* This also is the max crop size for this device. */
++ cam->crop_defrect.top = cam->crop_defrect.left = 0;
++ cam->crop_defrect.width = cam_fmt.fmt.pix.width;
++ cam->crop_defrect.height = cam_fmt.fmt.pix.height;
++
++ /* At this point, this is also the current image size. */
++ cam->crop_current.top = cam->crop_current.left = 0;
++ cam->crop_current.width = cam_fmt.fmt.pix.width;
++ cam->crop_current.height = cam_fmt.fmt.pix.height;
++
++ pr_debug("End of %s: v2f pix widthxheight %d x %d\n",
++ __func__,
++ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height);
++ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n",
++ __func__,
++ cam->crop_bounds.width, cam->crop_bounds.height);
++ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n",
++ __func__,
++ cam->crop_defrect.width, cam->crop_defrect.height);
++ pr_debug("End of %s: crop_current widthxheight %d x %d\n",
++ __func__,
++ cam->crop_current.width, cam->crop_current.height);
++
++ pr_info("%s: ipu%d:/csi%d %s attached %s:%s\n", __func__,
++ cam->ipu_id, cam->csi, cam->mipi_camera ? "mipi" : "parallel",
++ slave->name, slave->u.slave->master->name);
++ return 0;
++}
++
++/*!
++ * Disconnects the camera driver.
++ */
++static void mxc_v4l2_master_detach(struct v4l2_int_device *slave)
++{
++ unsigned int i;
++ cam_data *cam = slave->u.slave->master->priv;
++
++ pr_debug("%s\n", __func__);
++
++ if (cam->sensor_index > 1) {
++ for (i = 0; i < cam->sensor_index; i++) {
++ if (cam->all_sensors[i] != slave)
++ continue;
++ /* Move all the sensors behind this
++ * sensor one step forward
++ */
++ for (; i <= MXC_SENSOR_NUM - 2; i++)
++ cam->all_sensors[i] = cam->all_sensors[i+1];
++ break;
++ }
++ /* Point current sensor to the last one */
++ cam->sensor = cam->all_sensors[cam->sensor_index - 2];
++ } else
++ cam->sensor = NULL;
++
++ cam->sensor_index--;
++ vidioc_int_dev_exit(slave);
++}
++
++DEFINE_MUTEX(camera_common_mutex);
++
++void mxc_camera_common_lock(void)
++{
++ mutex_lock(&camera_common_mutex);
++}
++EXPORT_SYMBOL(mxc_camera_common_lock);
++
++void mxc_camera_common_unlock(void)
++{
++ mutex_unlock(&camera_common_mutex);
++}
++EXPORT_SYMBOL(mxc_camera_common_unlock);
++
++/*!
++ * Entry point for the V4L2
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int camera_init(void)
++{
++ u8 err = 0;
++
++ pr_debug("%s\n", __func__);
++
++ /* Register the device driver structure. */
++ err = platform_driver_register(&mxc_v4l2_driver);
++ if (err != 0) {
++ pr_err("ERROR: v4l2 capture:camera_init: "
++ "platform_driver_register failed.\n");
++ return err;
++ }
++
++ return err;
++}
++
++/*!
++ * Exit and cleanup for the V4L2
++ */
++static void __exit camera_exit(void)
++{
++ pr_debug("%s\n", __func__);
++
++ platform_driver_unregister(&mxc_v4l2_driver);
++}
++
++module_init(camera_init);
++module_exit(camera_exit);
++
++module_param(video_nr, int, 0444);
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("video");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h linux-3.14.72/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h 2016-06-19 22:11:55.177148406 +0200
+@@ -0,0 +1,358 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup MXC_V4L2_CAPTURE MXC V4L2 Video Capture Driver
++ */
++/*!
++ * @file mxc_v4l2_capture.h
++ *
++ * @brief mxc V4L2 capture device API Header file
++ *
++ * It include all the defines for frame operations, also three structure defines
++ * use case ops structure, common v4l2 driver structure and frame structure.
++ *
++ * @ingroup MXC_V4L2_CAPTURE
++ */
++#ifndef __MXC_V4L2_CAPTURE_H__
++#define __MXC_V4L2_CAPTURE_H__
++
++#include <linux/uaccess.h>
++#include <linux/list.h>
++#include <linux/mxc_v4l2.h>
++#include <linux/completion.h>
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++#include <linux/ipu-v3.h>
++#include <linux/platform_data/dma-imx.h>
++#include <linux/mipi_csi2.h>
++
++#include <media/v4l2-dev.h>
++#include "v4l2-int-device.h"
++
++
++#define FRAME_NUM 10
++#define MXC_SENSOR_NUM 2
++
++enum imx_v4l2_devtype {
++ IMX5_V4L2,
++ IMX6_V4L2,
++};
++
++/*!
++ * v4l2 frame structure.
++ */
++struct mxc_v4l_frame {
++ u32 paddress;
++ void *vaddress;
++ int count;
++ int width;
++ int height;
++
++ struct v4l2_buffer buffer;
++ struct list_head queue;
++ int index;
++ union {
++ int ipu_buf_num;
++ int csi_buf_num;
++ };
++};
++
++/* Only for old version. Will go away soon. */
++typedef struct {
++ u8 clk_mode;
++ u8 ext_vsync;
++ u8 Vsync_pol;
++ u8 Hsync_pol;
++ u8 pixclk_pol;
++ u8 data_pol;
++ u8 data_width;
++ u8 pack_tight;
++ u8 force_eof;
++ u8 data_en_pol;
++ u16 width;
++ u16 height;
++ u32 pixel_fmt;
++ u32 mclk;
++ u16 active_width;
++ u16 active_height;
++} sensor_interface;
++
++/* Sensor control function */
++/* Only for old version. Will go away soon. */
++struct camera_sensor {
++ void (*set_color) (int bright, int saturation, int red, int green,
++ int blue);
++ void (*get_color) (int *bright, int *saturation, int *red, int *green,
++ int *blue);
++ void (*set_ae_mode) (int ae_mode);
++ void (*get_ae_mode) (int *ae_mode);
++ sensor_interface *(*config) (int *frame_rate, int high_quality);
++ sensor_interface *(*reset) (void);
++ void (*get_std) (v4l2_std_id *std);
++ void (*set_std) (v4l2_std_id std);
++ unsigned int csi;
++};
++
++/*!
++ * common v4l2 driver structure.
++ */
++typedef struct _cam_data {
++ struct video_device *video_dev;
++ int device_type;
++
++ /* semaphore guard against SMP multithreading */
++ struct semaphore busy_lock;
++
++ int open_count;
++ struct delayed_work power_down_work;
++ int power_on;
++
++ /* params lock for this camera */
++ struct semaphore param_lock;
++
++ /* Encoder */
++ struct list_head ready_q;
++ struct list_head done_q;
++ struct list_head working_q;
++ int ping_pong_csi;
++ spinlock_t queue_int_lock;
++ spinlock_t dqueue_int_lock;
++ struct mxc_v4l_frame frame[FRAME_NUM];
++ struct mxc_v4l_frame dummy_frame;
++ wait_queue_head_t enc_queue;
++ int enc_counter;
++ dma_addr_t rot_enc_bufs[2];
++ void *rot_enc_bufs_vaddr[2];
++ int rot_enc_buf_size[2];
++ enum v4l2_buf_type type;
++
++ /* still image capture */
++ wait_queue_head_t still_queue;
++ int still_counter;
++ dma_addr_t still_buf[2];
++ void *still_buf_vaddr;
++
++ /* overlay */
++ struct v4l2_window win;
++ struct v4l2_framebuffer v4l2_fb;
++ dma_addr_t vf_bufs[2];
++ void *vf_bufs_vaddr[2];
++ int vf_bufs_size[2];
++ dma_addr_t rot_vf_bufs[2];
++ void *rot_vf_bufs_vaddr[2];
++ int rot_vf_buf_size[2];
++ bool overlay_active;
++ int output;
++ struct fb_info *overlay_fb;
++ int fb_origin_std;
++ struct work_struct csi_work_struct;
++
++ /* v4l2 format */
++ struct v4l2_format v2f;
++ struct v4l2_format input_fmt; /* camera in */
++ bool bswapenable;
++ int rotation; /* for IPUv1 and IPUv3, this means encoder rotation */
++ int vf_rotation; /* viewfinder rotation only for IPUv1 and IPUv3 */
++ struct v4l2_mxc_offset offset;
++
++ /* V4l2 control bit */
++ int bright;
++ int hue;
++ int contrast;
++ int saturation;
++ int red;
++ int green;
++ int blue;
++ int ae_mode;
++
++ /* standard */
++ struct v4l2_streamparm streamparm;
++ struct v4l2_standard standard;
++ bool standard_autodetect;
++
++ /* crop */
++ struct v4l2_rect crop_bounds;
++ struct v4l2_rect crop_defrect;
++ struct v4l2_rect crop_current;
++
++ int (*enc_update_eba) (struct ipu_soc *ipu, dma_addr_t eba,
++ int *bufferNum);
++ int (*enc_enable) (void *private);
++ int (*enc_disable) (void *private);
++ int (*enc_enable_csi) (void *private);
++ int (*enc_disable_csi) (void *private);
++ void (*enc_callback) (u32 mask, void *dev);
++ int (*vf_start_adc) (void *private);
++ int (*vf_stop_adc) (void *private);
++ int (*vf_start_sdc) (void *private);
++ int (*vf_stop_sdc) (void *private);
++ int (*vf_enable_csi) (void *private);
++ int (*vf_disable_csi) (void *private);
++ int (*csi_start) (void *private);
++ int (*csi_stop) (void *private);
++
++ /* misc status flag */
++ bool overlay_on;
++ bool capture_on;
++ bool ipu_enable_csi_called;
++ bool mipi_pixelclk_enabled;
++ struct ipu_chan *ipu_chan;
++ struct ipu_chan *ipu_chan_rot;
++ int overlay_pid;
++ int capture_pid;
++ bool low_power;
++ wait_queue_head_t power_queue;
++ unsigned int ipu_id;
++ unsigned int csi;
++ unsigned mipi_camera;
++ int csi_in_use;
++ u8 mclk_source;
++ bool mclk_on[2]; /* two mclk sources at most now */
++ int current_input;
++
++ int local_buf_num;
++
++ /* camera sensor interface */
++ struct camera_sensor *cam_sensor; /* old version */
++ struct v4l2_int_device *all_sensors[MXC_SENSOR_NUM];
++ struct v4l2_int_device *sensor;
++ struct v4l2_int_device *self;
++ int sensor_index;
++ void *ipu;
++ void *csi_soc;
++ enum imx_v4l2_devtype devtype;
++
++ /* v4l2 buf elements related to PxP DMA */
++ struct completion pxp_tx_cmpl;
++ struct pxp_channel *pxp_chan;
++ struct pxp_config_data pxp_conf;
++ struct dma_async_tx_descriptor *txd;
++ dma_cookie_t cookie;
++ struct scatterlist sg[2];
++} cam_data;
++
++struct additional_data {
++ u32 map_sizeimage;
++};
++
++struct sensor_data {
++ const struct additional_data *adata;
++ struct v4l2_int_device *v4l2_int_device;
++ struct i2c_client *i2c_client;
++ struct v4l2_pix_format pix;
++ struct v4l2_sensor_dimension spix;
++ struct v4l2_captureparm streamcap;
++ bool on;
++
++ /* control settings */
++ int brightness;
++ int hue;
++ int contrast;
++ int saturation;
++ int red;
++ int green;
++ int blue;
++ int ae_mode;
++
++ u32 mclk;
++ u8 mclk_source;
++ struct clk *sensor_clk;
++ int ipu_id;
++ int csi;
++ int last_reg;
++ unsigned mipi_camera;
++ unsigned virtual_channel; /* Used with mipi */
++
++ void (*io_init)(void);
++};
++
++void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi);
++void mxc_camera_common_lock(void);
++void mxc_camera_common_unlock(void);
++
++static inline int cam_ipu_enable_csi(cam_data *cam)
++{
++ int ret = ipu_enable_csi(cam->ipu, cam->csi);
++ if (!ret)
++ cam->ipu_enable_csi_called = 1;
++ return ret;
++}
++
++static inline int cam_ipu_disable_csi(cam_data *cam)
++{
++ if (!cam->ipu_enable_csi_called)
++ return 0;
++ cam->ipu_enable_csi_called = 0;
++ return ipu_disable_csi(cam->ipu, cam->csi);
++}
++
++static inline int cam_mipi_csi2_enable(cam_data *cam, struct mipi_fields *mf)
++{
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++ struct sensor_data *sensor;
++
++ if (!cam->sensor)
++ return 0;
++ sensor = cam->sensor->priv;
++ if (!sensor)
++ return 0;
++ if (!sensor->mipi_camera)
++ return 0;
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (!mipi_csi2_info) {
++// printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++// __func__, __FILE__);
++// return -EPERM;
++ return 0;
++ }
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ mf->en = true;
++ mf->vc = 0;//sensor->virtual_channel;
++ mf->id = mipi_csi2_get_datatype(mipi_csi2_info);
++ if (!mipi_csi2_pixelclk_enable(mipi_csi2_info))
++ cam->mipi_pixelclk_enabled = 1;
++ return 0;
++ }
++ mf->en = false;
++ mf->vc = 0;
++ mf->id = 0;
++#endif
++ return 0;
++}
++
++static inline int cam_mipi_csi2_disable(cam_data *cam)
++{
++#ifdef CONFIG_MXC_MIPI_CSI2
++ void *mipi_csi2_info;
++
++ if (!cam->mipi_pixelclk_enabled)
++ return 0;
++ cam->mipi_pixelclk_enabled = 0;
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ if (!mipi_csi2_info) {
++// printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++// __func__, __FILE__);
++// return -EPERM;
++ return 0;
++ }
++ if (mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_pixelclk_disable(mipi_csi2_info);
++#endif
++ return 0;
++}
++#endif /* __MXC_V4L2_CAPTURE_H__ */
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5640.c linux-3.14.72/drivers/media/platform/mxc/capture/ov5640.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5640.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ov5640.c 2016-06-19 22:11:55.177148406 +0200
+@@ -0,0 +1,1958 @@
++/*
++ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-chip-ident.h>
++#include "v4l2-int-device.h"
++#include "mxc_v4l2_capture.h"
++
++#define OV5640_VOLTAGE_ANALOG 2800000
++#define OV5640_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5640_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5640_XCLK_MIN 6000000
++#define OV5640_XCLK_MAX 24000000
++
++#define OV5640_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5640_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5640_mode {
++ ov5640_mode_MIN = 0,
++ ov5640_mode_VGA_640_480 = 0,
++ ov5640_mode_QVGA_320_240 = 1,
++ ov5640_mode_NTSC_720_480 = 2,
++ ov5640_mode_PAL_720_576 = 3,
++ ov5640_mode_720P_1280_720 = 4,
++ ov5640_mode_1080P_1920_1080 = 5,
++ ov5640_mode_QSXGA_2592_1944 = 6,
++ ov5640_mode_QCIF_176_144 = 7,
++ ov5640_mode_XGA_1024_768 = 8,
++ ov5640_mode_MAX = 8
++};
++
++enum ov5640_frame_rate {
++ ov5640_15_fps,
++ ov5640_30_fps
++};
++
++static int ov5640_framerates[] = {
++ [ov5640_15_fps] = 15,
++ [ov5640_30_fps] = 30,
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5640_mode_info {
++ enum ov5640_mode mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct sensor_data ov5640_data;
++static int pwn_gpio, rst_gpio;
++static int prev_sysclk;
++static int AE_Target = 52, night_mode;
++static int prev_HTS;
++static int AE_high, AE_low;
++
++static struct reg_value ov5640_global_init_setting[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
++ {0x3034, 0x1a, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0},
++ {0x3630, 0x36, 0, 0}, {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0},
++ {0x3633, 0x12, 0, 0}, {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0},
++ {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0},
++ {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0},
++ {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0},
++ {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0},
++ {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0},
++ {0x3a13, 0x43, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3635, 0x13, 0, 0}, {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0},
++ {0x3622, 0x01, 0, 0}, {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0},
++ {0x3c05, 0x98, 0, 0}, {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3c08, 0x00, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0},
++ {0x3c0b, 0x40, 0, 0}, {0x3810, 0x00, 0, 0}, {0x3811, 0x10, 0, 0},
++ {0x3812, 0x00, 0, 0}, {0x3708, 0x64, 0, 0}, {0x4001, 0x02, 0, 0},
++ {0x4005, 0x1a, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
++ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x440e, 0x00, 0, 0}, {0x5000, 0xa7, 0, 0},
++ {0x3008, 0x02, 0, 0},
++};
++
++static struct reg_value ov5640_init_setting_30fps_VGA[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
++ {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0},
++ {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0},
++ {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
++ {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
++ {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
++ {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
++ {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
++ {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
++ {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
++ {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
++ {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
++ {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5000, 0xa7, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0xf2, 0, 0},
++ {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, {0x5187, 0x09, 0, 0},
++ {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0}, {0x518a, 0x54, 0, 0},
++ {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x50, 0, 0},
++ {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x6c, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x09, 0, 0},
++ {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0}, {0x5381, 0x1e, 0, 0},
++ {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0}, {0x5384, 0x0a, 0, 0},
++ {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, {0x5387, 0x7c, 0, 0},
++ {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, {0x538a, 0x01, 0, 0},
++ {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, {0x5301, 0x30, 0, 0},
++ {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, {0x5304, 0x08, 0, 0},
++ {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, {0x5307, 0x16, 0, 0},
++ {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, {0x530b, 0x04, 0, 0},
++ {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, {0x5481, 0x08, 0, 0},
++ {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, {0x5484, 0x51, 0, 0},
++ {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, {0x5487, 0x7d, 0, 0},
++ {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, {0x548a, 0x9a, 0, 0},
++ {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, {0x548d, 0xcd, 0, 0},
++ {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, {0x5490, 0x1d, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x10, 0, 0},
++ {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, {0x558b, 0xf8, 0, 0},
++ {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0}, {0x5802, 0x0f, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0}, {0x5805, 0x26, 0, 0},
++ {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, {0x5808, 0x05, 0, 0},
++ {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, {0x580b, 0x0d, 0, 0},
++ {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0}, {0x580e, 0x00, 0, 0},
++ {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, {0x5811, 0x09, 0, 0},
++ {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x00, 0, 0},
++ {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0}, {0x5817, 0x08, 0, 0},
++ {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0}, {0x581a, 0x05, 0, 0},
++ {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0}, {0x581d, 0x0e, 0, 0},
++ {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0}, {0x5820, 0x11, 0, 0},
++ {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, {0x5823, 0x28, 0, 0},
++ {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0}, {0x5829, 0x26, 0, 0},
++ {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0}, {0x582c, 0x24, 0, 0},
++ {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0}, {0x582f, 0x22, 0, 0},
++ {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0}, {0x5832, 0x24, 0, 0},
++ {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0}, {0x5835, 0x22, 0, 0},
++ {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0}, {0x5838, 0x44, 0, 0},
++ {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0}, {0x583b, 0x28, 0, 0},
++ {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, {0x5025, 0x00, 0, 0},
++ {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0},
++ {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0},
++ {0x3008, 0x02, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_VGA_640_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_VGA_640_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
++ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
++ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_PAL_720_576[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_PAL_720_576[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_720P_1280_720[] = {
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
++ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
++ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++ {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_720P_1280_720[] = {
++ {0x3035, 0x41, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
++ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
++ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++ {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
++ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
++ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++
++static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = {
++ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
++ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0xee, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x05, 0, 0},
++ {0x3807, 0xc3, 0, 0}, {0x3808, 0x07, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, {0x380c, 0x0b, 0, 0},
++ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
++ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
++ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
++ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = {
++ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
++ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9f, 0, 0}, {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0},
++ {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0},
++ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
++ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
++ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
++ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = {
++ {
++ {ov5640_mode_VGA_640_480, 640, 480,
++ ov5640_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, 320, 240,
++ ov5640_setting_15fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, 720, 480,
++ ov5640_setting_15fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, 720, 576,
++ ov5640_setting_15fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, 1280, 720,
++ ov5640_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, 1920, 1080,
++ ov5640_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)},
++ {ov5640_mode_QSXGA_2592_1944, 2592, 1944,
++ ov5640_setting_15fps_QSXGA_2592_1944,
++ ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)},
++ {ov5640_mode_QCIF_176_144, 176, 144,
++ ov5640_setting_15fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, 1024, 768,
++ ov5640_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)},
++ },
++ {
++ {ov5640_mode_VGA_640_480, 640, 480,
++ ov5640_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, 320, 240,
++ ov5640_setting_30fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, 720, 480,
++ ov5640_setting_30fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, 720, 576,
++ ov5640_setting_30fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, 1280, 720,
++ ov5640_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, 0, 0, NULL, 0},
++ {ov5640_mode_QSXGA_2592_1944, 0, 0, NULL, 0},
++ {ov5640_mode_QCIF_176_144, 176, 144,
++ ov5640_setting_30fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, 1024, 768,
++ ov5640_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++
++static int ov5640_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5640_remove(struct i2c_client *client);
++
++static s32 ov5640_read_reg(u16 reg, u8 *val);
++static s32 ov5640_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5640_id[] = {
++ {"ov564x", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5640_id);
++
++static struct i2c_driver ov5640_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov564x",
++ },
++ .probe = ov5640_probe,
++ .remove = ov5640_remove,
++ .id_table = ov5640_id,
++};
++
++static inline void ov5640_power_down(int enable)
++{
++ gpio_set_value(pwn_gpio, enable);
++
++ msleep(2);
++}
++
++static inline void ov5640_reset(void)
++{
++ /* camera reset */
++ gpio_set_value(rst_gpio, 1);
++
++ /* camera power down */
++ gpio_set_value(pwn_gpio, 1);
++ msleep(5);
++ gpio_set_value(pwn_gpio, 0);
++ msleep(5);
++ gpio_set_value(rst_gpio, 0);
++ msleep(1);
++ gpio_set_value(rst_gpio, 1);
++ msleep(5);
++ gpio_set_value(pwn_gpio, 1);
++}
++
++static int ov5640_regulator_enable(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5640_VOLTAGE_DIGITAL_IO,
++ OV5640_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ dev_err(dev, "set io voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set io voltage ok\n");
++ }
++ } else {
++ io_regulator = NULL;
++ dev_warn(dev, "cannot get io voltage\n");
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5640_VOLTAGE_DIGITAL_CORE,
++ OV5640_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ dev_err(dev, "set core voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set core voltage ok\n");
++ }
++ } else {
++ core_regulator = NULL;
++ dev_warn(dev, "cannot get core voltage\n");
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5640_VOLTAGE_ANALOG,
++ OV5640_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ dev_err(dev, "set analog voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set analog voltage ok\n");
++ }
++ } else {
++ analog_regulator = NULL;
++ dev_warn(dev, "cannot get analog voltage\n");
++ }
++
++ return ret;
++}
++
++static s32 ov5640_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++
++ return 0;
++}
++
++static s32 ov5640_read_reg(u16 reg, u8 *val)
++{
++ u8 au8RegBuf[2] = {0};
++ u8 u8RdVal = 0;
++
++ au8RegBuf[0] = reg >> 8;
++ au8RegBuf[1] = reg & 0xff;
++
++ if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) {
++ pr_err("%s:write reg error:reg=%x\n",
++ __func__, reg);
++ return -1;
++ }
++
++ if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) {
++ pr_err("%s:read reg error:reg=%x,val=%x\n",
++ __func__, reg, u8RdVal);
++ return -1;
++ }
++
++ *val = u8RdVal;
++
++ return u8RdVal;
++}
++
++static void ov5640_soft_reset(void)
++{
++ /* sysclk from pad */
++ ov5640_write_reg(0x3103, 0x11);
++
++ /* software reset */
++ ov5640_write_reg(0x3008, 0x82);
++
++ /* delay at least 5ms */
++ msleep(10);
++}
++
++/* set sensor driver capability
++ * 0x302c[7:6] - strength
++ 00 - 1x
++ 01 - 2x
++ 10 - 3x
++ 11 - 4x
++ */
++static int ov5640_driver_capability(int strength)
++{
++ u8 temp = 0;
++
++ if (strength > 4 || strength < 1) {
++ pr_err("The valid driver capability of ov5640 is 1x~4x\n");
++ return -EINVAL;
++ }
++
++ ov5640_read_reg(0x302c, &temp);
++
++ temp &= ~0xc0; /* clear [7:6] */
++ temp |= ((strength - 1) << 6); /* set [7:6] */
++
++ ov5640_write_reg(0x302c, temp);
++
++ return 0;
++}
++
++/* calculate sysclk */
++static int ov5640_get_sysclk(void)
++{
++ int xvclk = ov5640_data.mclk / 10000;
++ int sysclk;
++ int temp1, temp2;
++ int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv;
++ int sclk_rdiv_map[] = {1, 2, 4, 8};
++ u8 regval = 0;
++
++ temp1 = ov5640_read_reg(0x3034, &regval);
++ temp2 = temp1 & 0x0f;
++ if (temp2 == 8 || temp2 == 10) {
++ Bit_div2x = temp2 / 2;
++ } else {
++ pr_err("ov5640: unsupported bit mode %d\n", temp2);
++ return -1;
++ }
++
++ temp1 = ov5640_read_reg(0x3035, &regval);
++ SysDiv = temp1 >> 4;
++ if (SysDiv == 0)
++ SysDiv = 16;
++
++ temp1 = ov5640_read_reg(0x3036, &regval);
++ Multiplier = temp1;
++ temp1 = ov5640_read_reg(0x3037, &regval);
++ PreDiv = temp1 & 0x0f;
++ Pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
++
++ temp1 = ov5640_read_reg(0x3108, &regval);
++ temp2 = temp1 & 0x03;
++
++ sclk_rdiv = sclk_rdiv_map[temp2];
++ VCO = xvclk * Multiplier / PreDiv;
++ sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv;
++
++ return sysclk;
++}
++
++/* read HTS from register settings */
++static int ov5640_get_HTS(void)
++{
++ int HTS;
++ u8 temp = 0;
++
++ HTS = ov5640_read_reg(0x380c, &temp);
++ HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp);
++ return HTS;
++}
++
++/* read VTS from register settings */
++static int ov5640_get_VTS(void)
++{
++ int VTS;
++ u8 temp = 0;
++
++ VTS = ov5640_read_reg(0x380e, &temp);
++ VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp);
++
++ return VTS;
++}
++
++/* write VTS to registers */
++static int ov5640_set_VTS(int VTS)
++{
++ int temp;
++
++ temp = VTS & 0xff;
++ ov5640_write_reg(0x380f, temp);
++
++ temp = VTS>>8;
++ ov5640_write_reg(0x380e, temp);
++ return 0;
++}
++
++/* read shutter, in number of line period */
++static int ov5640_get_shutter(void)
++{
++ int shutter;
++ u8 regval;
++
++ shutter = (ov5640_read_reg(0x03500, &regval) & 0x0f);
++
++ shutter = (shutter<<8) + ov5640_read_reg(0x3501, &regval);
++ shutter = (shutter<<4) + (ov5640_read_reg(0x3502, &regval)>>4);
++
++ return shutter;
++}
++
++/* write shutter, in number of line period */
++static int ov5640_set_shutter(int shutter)
++{
++ int temp;
++
++ shutter = shutter & 0xffff;
++ temp = shutter & 0x0f;
++ temp = temp<<4;
++ ov5640_write_reg(0x3502, temp);
++
++ temp = shutter & 0xfff;
++ temp = temp>>4;
++ ov5640_write_reg(0x3501, temp);
++
++ temp = shutter>>12;
++ ov5640_write_reg(0x3500, temp);
++
++ return 0;
++}
++
++/* read gain, 16 = 1x */
++static int ov5640_get_gain16(void)
++{
++ int gain16;
++ u8 regval;
++
++ gain16 = ov5640_read_reg(0x350a, &regval) & 0x03;
++ gain16 = (gain16<<8) + ov5640_read_reg(0x350b, &regval);
++
++ return gain16;
++}
++
++/* write gain, 16 = 1x */
++static int ov5640_set_gain16(int gain16)
++{
++ int temp;
++
++ gain16 = gain16 & 0x3ff;
++ temp = gain16 & 0xff;
++
++ ov5640_write_reg(0x350b, temp);
++ temp = gain16>>8;
++
++ ov5640_write_reg(0x350a, temp);
++ return 0;
++}
++
++/* get banding filter value */
++static int ov5640_get_light_freq(void)
++{
++ int temp, temp1, light_frequency;
++ u8 regval;
++
++ temp = ov5640_read_reg(0x3c01, &regval);
++ if (temp & 0x80) {
++ /* manual */
++ temp1 = ov5640_read_reg(0x3c00, &regval);
++ if (temp1 & 0x04) {
++ /* 50Hz */
++ light_frequency = 50;
++ } else {
++ /* 60Hz */
++ light_frequency = 60;
++ }
++ } else {
++ /* auto */
++ temp1 = ov5640_read_reg(0x3c0c, &regval);
++ if (temp1 & 0x01) {
++ /* 50Hz */
++ light_frequency = 50;
++ } else {
++ /* 60Hz */
++ light_frequency = 60;
++ }
++ }
++
++ return light_frequency;
++}
++
++static void ov5640_set_bandingfilter(void)
++{
++ int prev_VTS;
++ int band_step60, max_band60, band_step50, max_band50;
++
++ /* read preview PCLK */
++ prev_sysclk = ov5640_get_sysclk();
++
++ /* read preview HTS */
++ prev_HTS = ov5640_get_HTS();
++
++ /* read preview VTS */
++ prev_VTS = ov5640_get_VTS();
++
++ /* calculate banding filter */
++ /* 60Hz */
++ band_step60 = prev_sysclk * 100/prev_HTS * 100/120;
++ ov5640_write_reg(0x3a0a, (band_step60 >> 8));
++ ov5640_write_reg(0x3a0b, (band_step60 & 0xff));
++
++ max_band60 = (int)((prev_VTS-4)/band_step60);
++ ov5640_write_reg(0x3a0d, max_band60);
++
++ /* 50Hz */
++ band_step50 = prev_sysclk * 100/prev_HTS;
++ ov5640_write_reg(0x3a08, (band_step50 >> 8));
++ ov5640_write_reg(0x3a09, (band_step50 & 0xff));
++
++ max_band50 = (int)((prev_VTS-4)/band_step50);
++ ov5640_write_reg(0x3a0e, max_band50);
++}
++
++/* stable in high */
++static int ov5640_set_AE_target(int target)
++{
++ int fast_high, fast_low;
++
++ AE_low = target * 23 / 25; /* 0.92 */
++ AE_high = target * 27 / 25; /* 1.08 */
++ fast_high = AE_high << 1;
++
++ if (fast_high > 255)
++ fast_high = 255;
++ fast_low = AE_low >> 1;
++
++ ov5640_write_reg(0x3a0f, AE_high);
++ ov5640_write_reg(0x3a10, AE_low);
++ ov5640_write_reg(0x3a1b, AE_high);
++ ov5640_write_reg(0x3a1e, AE_low);
++ ov5640_write_reg(0x3a11, fast_high);
++ ov5640_write_reg(0x3a1f, fast_low);
++
++ return 0;
++}
++
++/* enable = 0 to turn off night mode
++ enable = 1 to turn on night mode */
++static int ov5640_set_night_mode(int enable)
++{
++ u8 mode;
++
++ ov5640_read_reg(0x3a00, &mode);
++
++ if (enable) {
++ /* night mode on */
++ mode |= 0x04;
++ ov5640_write_reg(0x3a00, mode);
++ } else {
++ /* night mode off */
++ mode &= 0xfb;
++ ov5640_write_reg(0x3a00, mode);
++ }
++
++ return 0;
++}
++
++/* enable = 0 to turn off AEC/AGC
++ enable = 1 to turn on AEC/AGC */
++static void ov5640_turn_on_AE_AG(int enable)
++{
++ u8 ae_ag_ctrl;
++
++ ov5640_read_reg(0x3503, &ae_ag_ctrl);
++ if (enable) {
++ /* turn on auto AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl & ~(0x03);
++ } else {
++ /* turn off AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl | 0x03;
++ }
++ ov5640_write_reg(0x3503, ae_ag_ctrl);
++}
++
++/* download ov5640 settings to sensor through i2c */
++static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize)
++{
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int i, retval = 0;
++
++ for (i = 0; i < ArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5640_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5640_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++static int ov5640_init_mode(void)
++{
++ struct reg_value *pModeSetting = NULL;
++ int ArySize = 0, retval = 0;
++
++ ov5640_soft_reset();
++
++ pModeSetting = ov5640_global_init_setting;
++ ArySize = ARRAY_SIZE(ov5640_global_init_setting);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ pModeSetting = ov5640_init_setting_30fps_VGA;
++ ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* change driver capability to 2x according to validation board.
++ * if the image is not stable, please increase the driver strength.
++ */
++ ov5640_driver_capability(2);
++ ov5640_set_bandingfilter();
++ ov5640_set_AE_target(AE_Target);
++ ov5640_set_night_mode(night_mode);
++
++ /* skip 9 vysnc: start capture at 10th vsync */
++ msleep(300);
++
++ /* turn off night mode */
++ night_mode = 0;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++err:
++ return retval;
++}
++
++/* change to or back to subsampling mode set the mode directly
++ * image size below 1280 * 960 is subsampling mode */
++static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ pModeSetting = ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width = ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height = ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* set ov5640 to subsampling mode */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++
++ /* turn on AE AG for subsampling mode, in case the firmware didn't */
++ ov5640_turn_on_AE_AG(1);
++
++ /* calculate banding filter */
++ ov5640_set_bandingfilter();
++
++ /* set AE target */
++ ov5640_set_AE_target(AE_Target);
++
++ /* update night mode setting */
++ ov5640_set_night_mode(night_mode);
++
++ /* skip 9 vysnc: start capture at 10th vsync */
++ if (mode == ov5640_mode_XGA_1024_768 && frame_rate == ov5640_30_fps) {
++ pr_warning("ov5640: actual frame rate of XGA is 22.5fps\n");
++ /* 1/22.5 * 9*/
++ msleep(400);
++ return retval;
++ }
++
++ if (frame_rate == ov5640_15_fps) {
++ /* 1/15 * 9*/
++ msleep(600);
++ } else if (frame_rate == ov5640_30_fps) {
++ /* 1/30 * 9*/
++ msleep(300);
++ }
++
++ return retval;
++}
++
++/* change to scaling mode go through exposure calucation
++ * image size above 1280 * 960 is scaling mode */
++static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ int prev_shutter, prev_gain16, average;
++ int cap_shutter, cap_gain16;
++ int cap_sysclk, cap_HTS, cap_VTS;
++ int light_freq, cap_bandfilt, cap_maxband;
++ long cap_gain16_shutter;
++ u8 temp;
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width =
++ ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height =
++ ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* read preview shutter */
++ prev_shutter = ov5640_get_shutter();
++
++ /* read preview gain */
++ prev_gain16 = ov5640_get_gain16();
++
++ /* get average */
++ average = ov5640_read_reg(0x56a1, &temp);
++
++ /* turn off night mode for capture */
++ ov5640_set_night_mode(0);
++
++ /* turn off overlay */
++ ov5640_write_reg(0x3022, 0x06);
++
++ /* Write capture setting */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* turn off AE AG when capture image. */
++ ov5640_turn_on_AE_AG(0);
++
++ /* read capture VTS */
++ cap_VTS = ov5640_get_VTS();
++ cap_HTS = ov5640_get_HTS();
++ cap_sysclk = ov5640_get_sysclk();
++
++ /* calculate capture banding filter */
++ light_freq = ov5640_get_light_freq();
++ if (light_freq == 60) {
++ /* 60Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120;
++ } else {
++ /* 50Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS;
++ }
++ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt);
++ /* calculate capture shutter/gain16 */
++ if (average > AE_low && average < AE_high) {
++ /* in stable range */
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
++ prev_HTS/cap_HTS * AE_Target / average;
++ } else {
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
++ prev_HTS/cap_HTS;
++ }
++
++ /* gain to shutter */
++ if (cap_gain16_shutter < (cap_bandfilt * 16)) {
++ /* shutter < 1/100 */
++ cap_shutter = cap_gain16_shutter/16;
++ if (cap_shutter < 1)
++ cap_shutter = 1;
++ cap_gain16 = cap_gain16_shutter/cap_shutter;
++ if (cap_gain16 < 16)
++ cap_gain16 = 16;
++ } else {
++ if (cap_gain16_shutter > (cap_bandfilt*cap_maxband*16)) {
++ /* exposure reach max */
++ cap_shutter = cap_bandfilt*cap_maxband;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ } else {
++ /* 1/100 < cap_shutter =< max, cap_shutter = n/100 */
++ cap_shutter =
++ ((int)(cap_gain16_shutter/16/cap_bandfilt))
++ * cap_bandfilt;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ }
++ }
++
++ /* write capture gain */
++ ov5640_set_gain16(cap_gain16);
++
++ /* write capture shutter */
++ if (cap_shutter > (cap_VTS - 4)) {
++ cap_VTS = cap_shutter + 4;
++ ov5640_set_VTS(cap_VTS);
++ }
++
++ ov5640_set_shutter(cap_shutter);
++
++ /* skip 2 vysnc: start capture at 3rd vsync
++ * frame rate of QSXGA and 1080P is 7.5fps: 1/7.5 * 2
++ */
++ pr_warning("ov5640: the actual frame rate of %s is 7.5fps\n",
++ mode == ov5640_mode_1080P_1920_1080 ? "1080P" : "QSXGA");
++ msleep(267);
++err:
++ return retval;
++}
++
++static int ov5640_change_mode(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ int retval = 0;
++
++ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ if (mode == ov5640_mode_1080P_1920_1080 ||
++ mode == ov5640_mode_QSXGA_2592_1944) {
++ /* change to scaling mode go through exposure calucation
++ * image size above 1280 * 960 is scaling mode */
++ retval = ov5640_change_mode_exposure_calc(frame_rate, mode);
++ } else {
++ /* change back to subsampling modem download firmware directly
++ * image size below 1280 * 960 is subsampling mode */
++ retval = ov5640_change_mode_direct(frame_rate, mode);
++ }
++
++ return retval;
++}
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = ov5640_data.mclk;
++ pr_debug(" clock_curr=mclk=%d\n", ov5640_data.mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_min = OV5640_XCLK_MIN;
++ p->u.bt656.clock_max = OV5640_XCLK_MAX;
++ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor_data *sensor = s->priv;
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5640_power_down(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ ov5640_power_down(1);
++}
++
++ sensor->on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ int ret = 0;
++
++ /* Make sure power on */
++ ov5640_power_down(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ return -EINVAL;
++ }
++
++ ret = ov5640_change_mode(frame_rate,
++ a->parm.capture.capturemode);
++ if (ret < 0)
++ return ret;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode = a->parm.capture.capturemode;
++
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor_data *sensor = s->priv;
++
++ f->fmt.pix = sensor->pix;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = ov5640_data.brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = ov5640_data.hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = ov5640_data.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = ov5640_data.saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = ov5640_data.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = ov5640_data.blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = ov5640_data.ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++
++ pr_debug("In ov5640:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fsize->pixel_format = ov5640_data.pix.pixelformat;
++ fsize->discrete.width =
++ max(ov5640_mode_info_data[0][fsize->index].width,
++ ov5640_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5640_mode_info_data[0][fsize->index].height,
++ ov5640_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ioctl_enum_frameintervals - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMEINTERVALS ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
++ struct v4l2_frmivalenum *fival)
++{
++ int i, j, count;
++
++ if (fival->index < 0 || fival->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ if (fival->width == 0 || fival->height == 0 ||
++ fival->pixel_format == 0) {
++ pr_warning("Please assign pixelformat, width and height.\n");
++ return -EINVAL;
++ }
++
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++
++ count = 0;
++ for (i = 0; i < ARRAY_SIZE(ov5640_mode_info_data); i++) {
++ for (j = 0; j < (ov5640_mode_MAX + 1); j++) {
++ if (fival->pixel_format == ov5640_data.pix.pixelformat
++ && fival->width == ov5640_mode_info_data[i][j].width
++ && fival->height == ov5640_mode_info_data[i][j].height
++ && ov5640_mode_info_data[i][j].init_data_ptr != NULL) {
++ count++;
++ }
++ if (fival->index == (count - 1)) {
++ fival->discrete.denominator =
++ ov5640_framerates[i];
++ return 0;
++ }
++ }
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5640_camera");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fmt->pixelformat = ov5640_data.pix.pixelformat;
++
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct sensor_data *sensor = s->priv;
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ int ret;
++
++ ov5640_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5640_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN);
++ ov5640_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++ clk_set_rate(ov5640_data.sensor_clk, ov5640_data.mclk);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ ret = ov5640_init_mode();
++ return ret;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = {
++ { vidioc_int_dev_init_num,
++ (v4l2_int_ioctl_func *)ioctl_dev_init },
++ { vidioc_int_dev_exit_num,
++ ioctl_dev_exit},
++ { vidioc_int_s_power_num,
++ (v4l2_int_ioctl_func *)ioctl_s_power },
++ { vidioc_int_g_ifparm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ifparm },
++ { vidioc_int_init_num,
++ (v4l2_int_ioctl_func *)ioctl_init },
++ { vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap },
++ { vidioc_int_g_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_g_fmt_cap },
++ { vidioc_int_g_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_parm },
++ { vidioc_int_s_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_s_parm },
++ { vidioc_int_g_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ctrl },
++ { vidioc_int_s_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_s_ctrl },
++ { vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_framesizes },
++ { vidioc_int_enum_frameintervals_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_frameintervals },
++ { vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *)ioctl_g_chip_ident },
++};
++
++static struct v4l2_int_slave ov5640_slave = {
++ .ioctls = ov5640_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(ov5640_ioctl_desc),
++};
++
++static struct v4l2_int_device ov5640_int_device = {
++ .module = THIS_MODULE,
++ .name = "ov564x",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &ov5640_slave,
++ },
++};
++
++/*!
++ * ov5640 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct pinctrl *pinctrl;
++ struct device *dev = &client->dev;
++ int retval;
++ u8 chip_id_high, chip_id_low;
++ struct sensor_data *sensor = &ov5640_data;
++
++ /* ov5640 pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "setup pinctrl failed\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_err(dev, "no sensor pwdn pin available\n");
++ return -ENODEV;
++ }
++ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_pwdn");
++ if (retval < 0)
++ return retval;
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(rst_gpio)) {
++ dev_err(dev, "no sensor reset pin available\n");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_reset");
++ if (retval < 0)
++ return retval;
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5640_data, 0, sizeof(ov5640_data));
++ ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5640_data.sensor_clk)) {
++ dev_err(dev, "get mclk failed\n");
++ return PTR_ERR(ov5640_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ &ov5640_data.mclk);
++ if (retval) {
++ dev_err(dev, "mclk frequency is invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5640_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "ipu_id",
++ &sensor->ipu_id);
++ if (retval) {
++ dev_err(dev, "ipu_id missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5640_data.csi));
++ if (retval) {
++ dev_err(dev, "csi_id invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5640_data.sensor_clk);
++
++ ov5640_data.io_init = ov5640_reset;
++ ov5640_data.i2c_client = client;
++ ov5640_data.pix.pixelformat = V4L2_PIX_FMT_YUYV;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++ ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5640_data.streamcap.capturemode = 0;
++ ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5640_data.streamcap.timeperframe.numerator = 1;
++
++ ov5640_regulator_enable(&client->dev);
++
++ ov5640_reset();
++
++ ov5640_power_down(0);
++
++ retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ pr_warning("camera ov5640 is not found\n");
++ return -ENODEV;
++ }
++ retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x40) {
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ pr_warning("camera ov5640 is not found\n");
++ return -ENODEV;
++ }
++
++ ov5640_power_down(1);
++
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++
++ ov5640_int_device.priv = &ov5640_data;
++ retval = v4l2_int_device_register(&ov5640_int_device);
++
++ pr_info("camera ov5640 is found\n");
++ return retval;
++}
++
++/*!
++ * ov5640 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_remove(struct i2c_client *client)
++{
++ v4l2_int_device_unregister(&ov5640_int_device);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++module_i2c_driver(ov5640_i2c_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("OV5640 Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5640_mipi.c linux-3.14.72/drivers/media/platform/mxc/capture/ov5640_mipi.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5640_mipi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ov5640_mipi.c 2016-06-19 22:11:55.177148406 +0200
+@@ -0,0 +1,2231 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/of_device.h>
++#include <linux/i2c.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/fsl_devices.h>
++#include <linux/mipi_csi2.h>
++#include <media/v4l2-chip-ident.h>
++#include "v4l2-int-device.h"
++#include "mxc_v4l2_capture.h"
++
++#define OV5640_VOLTAGE_ANALOG 2800000
++#define OV5640_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5640_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5640_XCLK_MIN 6000000
++#define OV5640_XCLK_MAX 24000000
++
++#define OV5640_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5640_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5640_mode {
++ ov5640_mode_MIN = 0,
++ ov5640_mode_VGA_640_480 = 0,
++ ov5640_mode_QVGA_320_240 = 1,
++ ov5640_mode_NTSC_720_480 = 2,
++ ov5640_mode_PAL_720_576 = 3,
++ ov5640_mode_720P_1280_720 = 4,
++ ov5640_mode_1080P_1920_1080 = 5,
++ ov5640_mode_QSXGA_2592_1944 = 6,
++ ov5640_mode_QCIF_176_144 = 7,
++ ov5640_mode_XGA_1024_768 = 8,
++ ov5640_mode_MAX = 8,
++ ov5640_mode_INIT = 0xff, /*only for sensor init*/
++};
++
++enum ov5640_frame_rate {
++ ov5640_15_fps,
++ ov5640_30_fps
++};
++
++static int ov5640_framerates[] = {
++ [ov5640_15_fps] = 15,
++ [ov5640_30_fps] = 30,
++};
++
++/* image size under 1280 * 960 are SUBSAMPLING
++ * image size upper 1280 * 960 are SCALING
++ */
++enum ov5640_downsize_mode {
++ SUBSAMPLING,
++ SCALING,
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5640_mode_info {
++ enum ov5640_mode mode;
++ enum ov5640_downsize_mode dn_mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct sensor_data ov5640_data;
++static int pwn_gpio, rst_gpio;
++
++static struct reg_value ov5640_init_setting_30fps_VGA[] = {
++
++ {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0x00, 0, 0}, {0x3018, 0x00, 0, 0},
++ {0x3034, 0x18, 0, 0}, {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0},
++ {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0},
++ {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
++ {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
++ {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
++ {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
++ {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
++ {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
++ {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
++ {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
++ {0x3c01, 0xa4, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
++ {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x300e, 0x45, 0, 0}, {0x302e, 0x08, 0, 0}, {0x4300, 0x3f, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x4837, 0x0a, 0, 0}, {0x4800, 0x04, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0},
++ {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0},
++ {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0},
++ {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0},
++ {0x518a, 0x54, 0, 0}, {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0},
++ {0x518d, 0x50, 0, 0}, {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0},
++ {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0},
++ {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0},
++ {0x5199, 0x6c, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0},
++ {0x519c, 0x09, 0, 0}, {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0},
++ {0x5381, 0x1e, 0, 0}, {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0},
++ {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0},
++ {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0},
++ {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0},
++ {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0},
++ {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0},
++ {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0},
++ {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0},
++ {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0},
++ {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0},
++ {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0},
++ {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0},
++ {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0},
++ {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0},
++ {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0},
++ {0x5802, 0x0f, 0, 0}, {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0},
++ {0x5805, 0x26, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0},
++ {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0},
++ {0x580b, 0x0d, 0, 0}, {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0},
++ {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0},
++ {0x5811, 0x09, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0},
++ {0x5814, 0x00, 0, 0}, {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0},
++ {0x5817, 0x08, 0, 0}, {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0},
++ {0x581a, 0x05, 0, 0}, {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0},
++ {0x581d, 0x0e, 0, 0}, {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0},
++ {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0},
++ {0x5823, 0x28, 0, 0}, {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0},
++ {0x5826, 0x08, 0, 0}, {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0},
++ {0x5829, 0x26, 0, 0}, {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0},
++ {0x582c, 0x24, 0, 0}, {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0},
++ {0x582f, 0x22, 0, 0}, {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0},
++ {0x5832, 0x24, 0, 0}, {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0},
++ {0x5835, 0x22, 0, 0}, {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0},
++ {0x5838, 0x44, 0, 0}, {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0},
++ {0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0},
++ {0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0},
++ {0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0},
++ {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300},
++};
++
++static struct reg_value ov5640_setting_30fps_VGA_640_480[] = {
++
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_VGA_640_480[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = {
++
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0},
++ {0x380b, 0x00, 0, 0}, {0x3035, 0x12, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3808, 0x04, 0, 0},
++ {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = {
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = {
++ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = {
++ {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_PAL_720_576[] = {
++ {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_PAL_720_576[] = {
++ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_720P_1280_720[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
++ {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
++ {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, {0x4005, 0x1a, 0, 0},
++ {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_720P_1280_720[] = {
++ {0x3035, 0x41, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
++ {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
++ {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0},
++ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
++ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0},
++ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
++ {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
++ {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0},
++ {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0},
++ {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
++ {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
++ {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
++ {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
++ {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0},
++ {0x3503, 0, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0},
++ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
++ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0},
++ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x54, 0, 1}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
++ {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
++ {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0},
++ {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0},
++ {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
++ {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
++ {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
++ {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
++ {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = {
++ {0x4202, 0x0f, 0, 0}, /* stream off the sensor */
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, /*disable flip*/
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0},
++ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
++ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0},
++ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70},
++ {0x4202, 0x00, 0, 0}, /* stream on the sensor */
++};
++
++static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = {
++ {
++ {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480,
++ ov5640_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240,
++ ov5640_setting_15fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480,
++ ov5640_setting_15fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576,
++ ov5640_setting_15fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720,
++ ov5640_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080,
++ ov5640_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)},
++ {ov5640_mode_QSXGA_2592_1944, SCALING, 2592, 1944,
++ ov5640_setting_15fps_QSXGA_2592_1944,
++ ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)},
++ {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144,
++ ov5640_setting_15fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768,
++ ov5640_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)},
++ },
++ {
++ {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480,
++ ov5640_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240,
++ ov5640_setting_30fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480,
++ ov5640_setting_30fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576,
++ ov5640_setting_30fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720,
++ ov5640_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080,
++ ov5640_setting_30fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)},
++ {ov5640_mode_QSXGA_2592_1944, -1, 0, 0, NULL, 0},
++ {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144,
++ ov5640_setting_30fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768,
++ ov5640_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++static struct regulator *gpo_regulator;
++
++static int ov5640_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5640_remove(struct i2c_client *client);
++
++static s32 ov5640_read_reg(u16 reg, u8 *val);
++static s32 ov5640_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5640_id[] = {
++ {"ov5640_mipi", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5640_id);
++
++static struct i2c_driver ov5640_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov5640_mipi",
++ },
++ .probe = ov5640_probe,
++ .remove = ov5640_remove,
++ .id_table = ov5640_id,
++};
++
++static void ov5640_standby(s32 enable)
++{
++ if (enable)
++ gpio_set_value(pwn_gpio, 1);
++ else
++ gpio_set_value(pwn_gpio, 0);
++ pr_debug("ov5640_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio);
++ msleep(2);
++}
++
++static void ov5640_reset(void)
++{
++ /* camera reset */
++ gpio_set_value(rst_gpio, 1);
++
++ /* camera power dowmn */
++ gpio_set_value(pwn_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 0);
++ msleep(5);
++
++ gpio_set_value(rst_gpio, 0);
++ msleep(1);
++
++ gpio_set_value(rst_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 1);
++}
++
++static int ov5640_power_on(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5640_VOLTAGE_DIGITAL_IO,
++ OV5640_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ pr_err("%s:io set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:io set voltage ok\n", __func__);
++ }
++ } else {
++ pr_err("%s: cannot get io voltage error\n", __func__);
++ io_regulator = NULL;
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5640_VOLTAGE_DIGITAL_CORE,
++ OV5640_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ pr_err("%s:core set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:core set voltage ok\n", __func__);
++ }
++ } else {
++ core_regulator = NULL;
++ pr_err("%s: cannot get core voltage error\n", __func__);
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5640_VOLTAGE_ANALOG,
++ OV5640_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ pr_err("%s:analog set voltage error\n",
++ __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:analog set voltage ok\n", __func__);
++ }
++ } else {
++ analog_regulator = NULL;
++ pr_err("%s: cannot get analog voltage error\n", __func__);
++ }
++
++ return ret;
++}
++
++static s32 ov5640_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++ pr_debug("reg=%x,val=%x\n", reg, val);
++ return 0;
++}
++
++static s32 ov5640_read_reg(u16 reg, u8 *val)
++{
++ struct sensor_data *sensor = &ov5640_data;
++ struct i2c_client *client = sensor->i2c_client;
++ struct i2c_msg msgs[2];
++ u8 buf[2];
++ int ret;
++
++ buf[0] = reg >> 8;
++ buf[1] = reg & 0xff;
++ msgs[0].addr = client->addr;
++ msgs[0].flags = 0;
++ msgs[0].len = 2;
++ msgs[0].buf = buf;
++
++ msgs[1].addr = client->addr;
++ msgs[1].flags = I2C_M_RD;
++ msgs[1].len = 1;
++ msgs[1].buf = buf;
++
++ ret = i2c_transfer(client->adapter, msgs, 2);
++ if (ret < 0) {
++ pr_err("%s(mipi):reg=%x ret=%d\n", __func__, reg, ret);
++ return ret;
++ }
++ *val = buf[0];
++ pr_debug("%s(mipi):reg=%x,val=%x\n", __func__, reg, buf[0]);
++ return buf[0];
++}
++
++static int prev_sysclk, prev_HTS;
++static int AE_low, AE_high, AE_Target = 52;
++
++void OV5640_stream_on(void)
++{
++ ov5640_write_reg(0x4202, 0x00);
++}
++
++void OV5640_stream_off(void)
++{
++ ov5640_write_reg(0x4202, 0x0f);
++}
++
++static const int sclk_rdiv_map[] = {1, 2, 4, 8};
++
++int OV5640_get_sysclk(void)
++{
++ /* calculate sysclk */
++ int tmp;
++ unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1;
++ unsigned div, sclk_rdiv, sysclk;
++ u8 temp;
++
++ tmp = ov5640_read_reg(0x3034, &temp);
++ if (tmp < 0)
++ return tmp;
++ tmp &= 0x0f;
++ if (tmp == 8 || tmp == 10)
++ Bit_div2x = tmp / 2;
++
++ tmp = ov5640_read_reg(0x3035, &temp);
++ if (tmp < 0)
++ return tmp;
++ SysDiv = tmp >> 4;
++ if (SysDiv == 0)
++ SysDiv = 16;
++
++ tmp = ov5640_read_reg(0x3036, &temp);
++ if (tmp < 0)
++ return tmp;
++ Multiplier = tmp;
++
++ tmp = ov5640_read_reg(0x3037, &temp);
++ if (tmp < 0)
++ return tmp;
++ PreDiv = tmp & 0x0f;
++ Pll_rdiv = ((tmp >> 4) & 0x01) + 1;
++
++ tmp = ov5640_read_reg(0x3108, &temp);
++ if (tmp < 0)
++ return tmp;
++ sclk_rdiv = sclk_rdiv_map[tmp & 0x03];
++
++ sysclk = ov5640_data.mclk / 10000 * Multiplier;
++ div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv;
++ if (!div) {
++ pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n",
++ __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
++ return -EINVAL;
++ }
++ if (!sysclk) {
++ pr_err("%s:Error 0 clk, ov5640_data.mclk=%d, Multiplier=%d\n",
++ __func__, ov5640_data.mclk, Multiplier);
++ return -EINVAL;
++ }
++ sysclk /= div;
++ pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n",
++ __func__, sysclk, ov5640_data.mclk, Multiplier,
++ PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
++ return sysclk;
++}
++
++void OV5640_set_night_mode(void)
++{
++ /* read HTS from register settings */
++ u8 mode;
++
++ ov5640_read_reg(0x3a00, &mode);
++ mode &= 0xfb;
++ ov5640_write_reg(0x3a00, mode);
++}
++
++int OV5640_get_HTS(void)
++{
++ /* read HTS from register settings */
++ int HTS;
++ u8 temp;
++
++ HTS = ov5640_read_reg(0x380c, &temp);
++ HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp);
++
++ return HTS;
++}
++
++int OV5640_get_VTS(void)
++{
++ /* read VTS from register settings */
++ int VTS;
++ u8 temp;
++
++ /* total vertical size[15:8] high byte */
++ VTS = ov5640_read_reg(0x380e, &temp);
++
++ VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp);
++
++ return VTS;
++}
++
++int OV5640_set_VTS(int VTS)
++{
++ /* write VTS to registers */
++ int temp;
++
++ temp = VTS & 0xff;
++ ov5640_write_reg(0x380f, temp);
++
++ temp = VTS>>8;
++ ov5640_write_reg(0x380e, temp);
++
++ return 0;
++}
++
++int OV5640_get_shutter(void)
++{
++ /* read shutter, in number of line period */
++ int shutter;
++ u8 temp;
++
++ shutter = (ov5640_read_reg(0x03500, &temp) & 0x0f);
++ shutter = (shutter<<8) + ov5640_read_reg(0x3501, &temp);
++ shutter = (shutter<<4) + (ov5640_read_reg(0x3502, &temp)>>4);
++
++ return shutter;
++}
++
++int OV5640_set_shutter(int shutter)
++{
++ /* write shutter, in number of line period */
++ int temp;
++
++ shutter = shutter & 0xffff;
++
++ temp = shutter & 0x0f;
++ temp = temp<<4;
++ ov5640_write_reg(0x3502, temp);
++
++ temp = shutter & 0xfff;
++ temp = temp>>4;
++ ov5640_write_reg(0x3501, temp);
++
++ temp = shutter>>12;
++ ov5640_write_reg(0x3500, temp);
++
++ return 0;
++}
++
++int OV5640_get_gain16(void)
++{
++ /* read gain, 16 = 1x */
++ int gain16;
++ u8 temp;
++
++ gain16 = ov5640_read_reg(0x350a, &temp) & 0x03;
++ gain16 = (gain16<<8) + ov5640_read_reg(0x350b, &temp);
++
++ return gain16;
++}
++
++int OV5640_set_gain16(int gain16)
++{
++ /* write gain, 16 = 1x */
++ u8 temp;
++ gain16 = gain16 & 0x3ff;
++
++ temp = gain16 & 0xff;
++ ov5640_write_reg(0x350b, temp);
++
++ temp = gain16>>8;
++ ov5640_write_reg(0x350a, temp);
++
++ return 0;
++}
++
++int OV5640_get_light_freq(void)
++{
++ /* get banding filter value */
++ int temp, temp1, light_freq = 0;
++ u8 tmp;
++
++ temp = ov5640_read_reg(0x3c01, &tmp);
++
++ if (temp & 0x80) {
++ /* manual */
++ temp1 = ov5640_read_reg(0x3c00, &tmp);
++ if (temp1 & 0x04) {
++ /* 50Hz */
++ light_freq = 50;
++ } else {
++ /* 60Hz */
++ light_freq = 60;
++ }
++ } else {
++ /* auto */
++ temp1 = ov5640_read_reg(0x3c0c, &tmp);
++ if (temp1 & 0x01) {
++ /* 50Hz */
++ light_freq = 50;
++ } else {
++ /* 60Hz */
++ light_freq = 60;
++ }
++ }
++ return light_freq;
++}
++
++void OV5640_set_bandingfilter(void)
++{
++ int prev_VTS;
++ int band_step60, max_band60, band_step50, max_band50;
++
++ /* read preview PCLK */
++ prev_sysclk = OV5640_get_sysclk();
++ /* read preview HTS */
++ prev_HTS = OV5640_get_HTS();
++
++ /* read preview VTS */
++ prev_VTS = OV5640_get_VTS();
++
++ /* calculate banding filter */
++ /* 60Hz */
++ band_step60 = prev_sysclk * 100/prev_HTS * 100/120;
++ ov5640_write_reg(0x3a0a, (band_step60 >> 8));
++ ov5640_write_reg(0x3a0b, (band_step60 & 0xff));
++
++ max_band60 = (int)((prev_VTS-4)/band_step60);
++ ov5640_write_reg(0x3a0d, max_band60);
++
++ /* 50Hz */
++ band_step50 = prev_sysclk * 100/prev_HTS;
++ ov5640_write_reg(0x3a08, (band_step50 >> 8));
++ ov5640_write_reg(0x3a09, (band_step50 & 0xff));
++
++ max_band50 = (int)((prev_VTS-4)/band_step50);
++ ov5640_write_reg(0x3a0e, max_band50);
++}
++
++int OV5640_set_AE_target(int target)
++{
++ /* stable in high */
++ int fast_high, fast_low;
++ AE_low = target * 23 / 25; /* 0.92 */
++ AE_high = target * 27 / 25; /* 1.08 */
++
++ fast_high = AE_high<<1;
++ if (fast_high > 255)
++ fast_high = 255;
++
++ fast_low = AE_low >> 1;
++
++ ov5640_write_reg(0x3a0f, AE_high);
++ ov5640_write_reg(0x3a10, AE_low);
++ ov5640_write_reg(0x3a1b, AE_high);
++ ov5640_write_reg(0x3a1e, AE_low);
++ ov5640_write_reg(0x3a11, fast_high);
++ ov5640_write_reg(0x3a1f, fast_low);
++
++ return 0;
++}
++
++void OV5640_turn_on_AE_AG(int enable)
++{
++ u8 ae_ag_ctrl;
++
++ ov5640_read_reg(0x3503, &ae_ag_ctrl);
++ if (enable) {
++ /* turn on auto AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl & ~(0x03);
++ } else {
++ /* turn off AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl | 0x03;
++ }
++ ov5640_write_reg(0x3503, ae_ag_ctrl);
++}
++
++bool ov5640_binning_on(void)
++{
++ u8 temp;
++ ov5640_read_reg(0x3821, &temp);
++ temp &= 0xfe;
++ if (temp)
++ return true;
++ else
++ return false;
++}
++
++static void ov5640_set_virtual_channel(int channel)
++{
++ u8 channel_id;
++
++ ov5640_read_reg(0x4814, &channel_id);
++ channel_id &= ~(3 << 6);
++ ov5640_write_reg(0x4814, channel_id | (channel << 6));
++}
++
++/* download ov5640 settings to sensor through i2c */
++static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize)
++{
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int i, retval = 0;
++
++ for (i = 0; i < ArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5640_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5640_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++/* sensor changes between scaling and subsampling
++ * go through exposure calcualtion
++ */
++static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ u8 average;
++ int prev_shutter, prev_gain16;
++ int cap_shutter, cap_gain16;
++ int cap_sysclk, cap_HTS, cap_VTS;
++ int light_freq, cap_bandfilt, cap_maxband;
++ long cap_gain16_shutter;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width =
++ ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height =
++ ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* auto focus */
++ /* OV5640_auto_focus();//if no af function, just skip it */
++
++ /* turn off AE/AG */
++ OV5640_turn_on_AE_AG(0);
++
++ /* read preview shutter */
++ prev_shutter = OV5640_get_shutter();
++ if ((ov5640_binning_on()) && (mode != ov5640_mode_720P_1280_720)
++ && (mode != ov5640_mode_1080P_1920_1080))
++ prev_shutter *= 2;
++
++ /* read preview gain */
++ prev_gain16 = OV5640_get_gain16();
++
++ /* get average */
++ ov5640_read_reg(0x56a1, &average);
++
++ /* turn off night mode for capture */
++ OV5640_set_night_mode();
++
++ /* turn off overlay */
++ /* ov5640_write_reg(0x3022, 0x06);//if no af function, just skip it */
++
++ OV5640_stream_off();
++
++ /* Write capture setting */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* read capture VTS */
++ cap_VTS = OV5640_get_VTS();
++ cap_HTS = OV5640_get_HTS();
++ cap_sysclk = OV5640_get_sysclk();
++
++ /* calculate capture banding filter */
++ light_freq = OV5640_get_light_freq();
++ if (light_freq == 60) {
++ /* 60Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120;
++ } else {
++ /* 50Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS;
++ }
++ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt);
++
++ /* calculate capture shutter/gain16 */
++ if (average > AE_low && average < AE_high) {
++ /* in stable range */
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk
++ * prev_HTS/cap_HTS * AE_Target / average;
++ } else {
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk
++ * prev_HTS/cap_HTS;
++ }
++
++ /* gain to shutter */
++ if (cap_gain16_shutter < (cap_bandfilt * 16)) {
++ /* shutter < 1/100 */
++ cap_shutter = cap_gain16_shutter/16;
++ if (cap_shutter < 1)
++ cap_shutter = 1;
++
++ cap_gain16 = cap_gain16_shutter/cap_shutter;
++ if (cap_gain16 < 16)
++ cap_gain16 = 16;
++ } else {
++ if (cap_gain16_shutter >
++ (cap_bandfilt * cap_maxband * 16)) {
++ /* exposure reach max */
++ cap_shutter = cap_bandfilt * cap_maxband;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ } else {
++ /* 1/100 < (cap_shutter = n/100) =< max */
++ cap_shutter =
++ ((int) (cap_gain16_shutter/16 / cap_bandfilt))
++ *cap_bandfilt;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ }
++ }
++
++ /* write capture gain */
++ OV5640_set_gain16(cap_gain16);
++
++ /* write capture shutter */
++ if (cap_shutter > (cap_VTS - 4)) {
++ cap_VTS = cap_shutter + 4;
++ OV5640_set_VTS(cap_VTS);
++ }
++ OV5640_set_shutter(cap_shutter);
++
++ OV5640_stream_on();
++
++err:
++ return retval;
++}
++
++/* if sensor changes inside scaling or subsampling
++ * change mode directly
++ * */
++static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width =
++ ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height =
++ ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* turn off AE/AG */
++ OV5640_turn_on_AE_AG(0);
++
++ OV5640_stream_off();
++
++ /* Write capture setting */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ OV5640_stream_on();
++
++ OV5640_turn_on_AE_AG(1);
++
++err:
++ return retval;
++}
++
++static int ov5640_init_mode(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode, enum ov5640_mode orig_mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++ void *mipi_csi2_info;
++ u32 mipi_reg, msec_wait4stable = 0;
++ enum ov5640_downsize_mode dn_mode, orig_dn_mode;
++
++ if ((mode > ov5640_mode_MAX || mode < ov5640_mode_MIN)
++ && (mode != ov5640_mode_INIT)) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* initial mipi dphy */
++ if (!mipi_csi2_info) {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -1;
++ }
++
++ if (!mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_enable(mipi_csi2_info);
++
++ if (!mipi_csi2_get_status(mipi_csi2_info)) {
++ pr_err("Can not enable mipi csi2 driver!\n");
++ return -1;
++ }
++
++ mipi_csi2_set_lanes(mipi_csi2_info, 2);
++
++ /*Only reset MIPI CSI2 HW at sensor initialize*/
++ if (mode == ov5640_mode_INIT)
++ mipi_csi2_reset(mipi_csi2_info);
++
++ if (ov5640_data.pix.pixelformat == V4L2_PIX_FMT_UYVY)
++ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_YUV422);
++ else if (ov5640_data.pix.pixelformat == V4L2_PIX_FMT_RGB565)
++ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_RGB565);
++ else
++ pr_err("currently this sensor format can not be supported!\n");
++
++ dn_mode = ov5640_mode_info_data[frame_rate][mode].dn_mode;
++ orig_dn_mode = ov5640_mode_info_data[frame_rate][orig_mode].dn_mode;
++ if (mode == ov5640_mode_INIT) {
++ pModeSetting = ov5640_init_setting_30fps_VGA;
++ ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA);
++
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ pModeSetting = ov5640_setting_30fps_VGA_640_480;
++ ArySize = ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ } else if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) ||
++ (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) {
++ /* change between subsampling and scaling
++ * go through exposure calucation */
++ retval = ov5640_change_mode_exposure_calc(frame_rate, mode);
++ } else {
++ /* change inside subsampling or scaling
++ * download firmware directly */
++ retval = ov5640_change_mode_direct(frame_rate, mode);
++ }
++
++ if (retval < 0)
++ goto err;
++
++ OV5640_set_AE_target(AE_Target);
++ OV5640_get_light_freq();
++ OV5640_set_bandingfilter();
++ ov5640_set_virtual_channel(ov5640_data.virtual_channel);
++
++ /* add delay to wait for sensor stable */
++ if (mode == ov5640_mode_QSXGA_2592_1944) {
++ /* dump the first two frames: 1/7.5*2
++ * the frame rate of QSXGA is 7.5fps */
++ msec_wait4stable = 267;
++ } else if (frame_rate == ov5640_15_fps) {
++ /* dump the first nine frames: 1/15*9 */
++ msec_wait4stable = 600;
++ } else if (frame_rate == ov5640_30_fps) {
++ /* dump the first nine frames: 1/30*9 */
++ msec_wait4stable = 300;
++ }
++ msleep(msec_wait4stable);
++
++ if (mipi_csi2_info) {
++ unsigned int i = 0;
++
++ /* wait for mipi sensor ready */
++ while (1) {
++ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
++ if (mipi_reg != 0x200)
++ break;
++ if (i++ >= 20) {
++ pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg);
++ return -1;
++ }
++ msleep(10);
++ }
++
++ i = 0;
++ /* wait for mipi stable */
++ while (1) {
++ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
++ if (!mipi_reg)
++ break;
++ if (i++ >= 20) {
++ pr_err("mipi csi2 can not receive data correctly!\n");
++ return -1;
++ }
++ msleep(10);
++ }
++
++ }
++err:
++ return retval;
++}
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = ov5640_data.mclk;
++ pr_debug(" clock_curr=mclk=%d\n", ov5640_data.mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_min = OV5640_XCLK_MIN;
++ p->u.bt656.clock_max = OV5640_XCLK_MAX;
++ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor_data *sensor = s->priv;
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (gpo_regulator)
++ if (regulator_enable(gpo_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5640_standby(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ ov5640_standby(1);
++ }
++
++ sensor->on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ enum ov5640_mode orig_mode;
++ int ret = 0;
++
++ /* Make sure power on */
++ ov5640_standby(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ return -EINVAL;
++ }
++
++ orig_mode = sensor->streamcap.capturemode;
++ ret = ov5640_init_mode(frame_rate,
++ (u32)a->parm.capture.capturemode, orig_mode);
++ if (ret < 0)
++ return ret;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode =
++ (u32)a->parm.capture.capturemode;
++
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor_data *sensor = s->priv;
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ f->fmt.pix = sensor->pix;
++ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height);
++ break;
++
++ case V4L2_BUF_TYPE_SENSOR:
++ pr_debug("%s: left=%d, top=%d, %dx%d\n", __func__,
++ sensor->spix.left, sensor->spix.top,
++ sensor->spix.swidth, sensor->spix.sheight);
++ f->fmt.spix = sensor->spix;
++ break;
++
++ case V4L2_BUF_TYPE_PRIVATE:
++ break;
++
++ default:
++ f->fmt.pix = sensor->pix;
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = ov5640_data.brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = ov5640_data.hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = ov5640_data.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = ov5640_data.saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = ov5640_data.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = ov5640_data.blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = ov5640_data.ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++
++ pr_debug("In ov5640:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fsize->pixel_format = ov5640_data.pix.pixelformat;
++ fsize->discrete.width =
++ max(ov5640_mode_info_data[0][fsize->index].width,
++ ov5640_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5640_mode_info_data[0][fsize->index].height,
++ ov5640_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ioctl_enum_frameintervals - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMEINTERVALS ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
++ struct v4l2_frmivalenum *fival)
++{
++ int i, j, count = 0;
++
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++
++ for (i = 0; i < ARRAY_SIZE(ov5640_mode_info_data); i++)
++ for (j = 0; j < (ov5640_mode_MAX + 1); j++)
++ if (fival->pixel_format == ov5640_data.pix.pixelformat
++ && fival->width == ov5640_mode_info_data[i][j].width
++ && fival->height == ov5640_mode_info_data[i][j].height
++ && ov5640_mode_info_data[i][j].init_data_ptr != NULL
++ && fival->index == count++) {
++ fival->discrete.denominator =
++ ov5640_framerates[i];
++ return 0;
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "ov5640_mipi_camera");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fmt->pixelformat = ov5640_data.pix.pixelformat;
++
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct sensor_data *sensor = s->priv;
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ int ret;
++ enum ov5640_frame_rate frame_rate;
++ void *mipi_csi2_info;
++
++ ov5640_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5640_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN);
++ ov5640_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* enable mipi csi2 */
++ if (mipi_csi2_info)
++ mipi_csi2_enable(mipi_csi2_info);
++ else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++
++ ret = ov5640_init_mode(frame_rate, ov5640_mode_INIT, ov5640_mode_INIT);
++
++ return ret;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ void *mipi_csi2_info;
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* disable mipi csi2 */
++ if (mipi_csi2_info)
++ if (mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_disable(mipi_csi2_info);
++
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = {
++ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *) ioctl_dev_init},
++ {vidioc_int_dev_exit_num, ioctl_dev_exit},
++ {vidioc_int_s_power_num, (v4l2_int_ioctl_func *) ioctl_s_power},
++ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *) ioctl_g_ifparm},
++/* {vidioc_int_g_needs_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
++/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
++ {vidioc_int_init_num, (v4l2_int_ioctl_func *) ioctl_init},
++ {vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap},
++/* {vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
++ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
++/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_s_fmt_cap}, */
++ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
++ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
++/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */
++ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl},
++ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
++ {vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
++ {vidioc_int_enum_frameintervals_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_frameintervals},
++ {vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *) ioctl_g_chip_ident},
++};
++
++static struct v4l2_int_slave ov5640_slave = {
++ .ioctls = ov5640_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(ov5640_ioctl_desc),
++};
++
++static struct v4l2_int_device ov5640_int_device = {
++ .module = THIS_MODULE,
++ .name = "ov5640_mipi",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &ov5640_slave,
++ },
++};
++
++static ssize_t show_reg(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ u8 val;
++ s32 rval = ov5640_read_reg(ov5640_data.last_reg, &val);
++
++ return sprintf(buf, "ov5640[0x%04x]=0x%02x\n",ov5640_data.last_reg, rval);
++}
++static ssize_t set_reg(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int regnum, value;
++ int num_parsed = sscanf(buf, "%04x=%02x", &regnum, &value);
++ if (1 <= num_parsed) {
++ if (0xffff < (unsigned)regnum){
++ pr_err("%s:invalid regnum %x\n", __func__, regnum);
++ return 0;
++ }
++ ov5640_data.last_reg = regnum;
++ }
++ if (2 == num_parsed) {
++ if (0xff < (unsigned)value) {
++ pr_err("%s:invalid value %x\n", __func__, value);
++ return 0;
++ }
++ ov5640_write_reg(ov5640_data.last_reg, value);
++ }
++ return count;
++}
++static DEVICE_ATTR(ov5640_reg, S_IRUGO|S_IWUGO, show_reg, set_reg);
++
++/*!
++ * ov5640 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct device *dev = &client->dev;
++ int retval;
++ u8 chip_id_high, chip_id_low;
++ struct sensor_data *sensor = &ov5640_data;
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_warn(dev, "no sensor pwdn pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_mipi_pwdn");
++ if (retval < 0) {
++ dev_warn(dev, "request of pwn_gpio failed");
++ return retval;
++ }
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(rst_gpio)) {
++ dev_warn(dev, "no sensor reset pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_mipi_reset");
++ if (retval < 0) {
++ dev_warn(dev, "request of ov5640_mipi_reset failed");
++ return retval;
++ }
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5640_data, 0, sizeof(ov5640_data));
++
++ sensor->mipi_camera = 1;
++ ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5640_data.sensor_clk)) {
++ /* assuming clock enabled by default */
++ ov5640_data.sensor_clk = NULL;
++ dev_err(dev, "clock-frequency missing or invalid\n");
++ return PTR_ERR(ov5640_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ &(ov5640_data.mclk));
++ if (retval) {
++ dev_err(dev, "mclk missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5640_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "ipu_id",
++ &sensor->ipu_id);
++ if (retval) {
++ dev_err(dev, "ipu_id missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5640_data.csi));
++ if (retval) {
++ dev_err(dev, "csi id missing or invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5640_data.sensor_clk);
++
++ ov5640_data.io_init = ov5640_reset;
++ ov5640_data.i2c_client = client;
++ ov5640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++ ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5640_data.streamcap.capturemode = 0;
++ ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5640_data.streamcap.timeperframe.numerator = 1;
++
++ ov5640_power_on(dev);
++
++ ov5640_reset();
++
++ ov5640_standby(0);
++
++ retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ pr_warning("camera ov5640_mipi is not found\n");
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ return -ENODEV;
++ }
++ retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x40) {
++ pr_warning("camera ov5640_mipi is not found\n");
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ return -ENODEV;
++ }
++
++ sensor->virtual_channel = sensor->csi | (sensor->ipu_id << 1);
++ ov5640_standby(1);
++
++ ov5640_int_device.priv = &ov5640_data;
++ retval = v4l2_int_device_register(&ov5640_int_device);
++
++// clk_disable_unprepare(ov5640_data.sensor_clk);
++
++ if (device_create_file(dev, &dev_attr_ov5640_reg))
++ dev_err(dev, "%s: error creating ov5640_reg entry\n", __func__);
++ pr_info("camera ov5640_mipi is found\n");
++ return retval;
++}
++
++/*!
++ * ov5640 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_remove(struct i2c_client *client)
++{
++ v4l2_int_device_unregister(&ov5640_int_device);
++
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++/*!
++ * ov5640 init function
++ * Called by insmod ov5640_camera.ko.
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int ov5640_init(void)
++{
++ u8 err;
++
++ err = i2c_add_driver(&ov5640_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * OV5640 cleanup function
++ * Called on rmmod ov5640_camera.ko
++ *
++ * @return Error code indicating success or failure
++ */
++static void __exit ov5640_clean(void)
++{
++ i2c_del_driver(&ov5640_i2c_driver);
++}
++
++module_init(ov5640_init);
++module_exit(ov5640_clean);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("OV5640 MIPI Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5642.c linux-3.14.72/drivers/media/platform/mxc/capture/ov5642.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5642.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ov5642.c 2016-06-19 22:11:55.181148143 +0200
+@@ -0,0 +1,6294 @@
++/*
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/of_device.h>
++#include <linux/i2c.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/fsl_devices.h>
++#include <media/v4l2-chip-ident.h>
++#include "v4l2-int-device.h"
++#include "mxc_v4l2_capture.h"
++
++#define OV5642_VOLTAGE_ANALOG 2800000
++#define OV5642_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5642_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5642_XCLK_MIN 6000000
++#define OV5642_XCLK_MAX 24000000
++
++/* OV5642 Camera Auto Focus Registers */
++#define REG_CMD_MAIN 0x3024
++#define REG_STA_FOCUS 0x3027
++#define REG_STA_ZONE 0x3026
++#define REG_CMD_TAG 0x3025
++#define REG_CMD_PARA3 0x5082
++#define REG_CMD_PARA2 0x5083
++#define REG_CMD_PARA1 0x5084
++#define REG_CMD_PARA0 0x5085
++
++
++/* OV5642 Auto Focus Commands and Responses */
++#define S_STARTUP 0xFA
++#define S_FIRWARE 0xFF
++#define S_STARTUP 0xFA
++#define S_ERROR 0xFE
++#define S_DRVICERR 0xEE
++#define S_IDLE 0x00
++#define S_FOCUSING 0x01
++#define S_FOCUSED 0x02
++#define S_CAPTURE 0x12
++#define S_STEP 0x20
++
++/*OV5642 AWB Registers*/
++#define REG_AWB_MANUAL 0x3406
++#define REG_AWB_R_GAIN_HIGH 0x3400
++#define REG_AWB_R_GAIN_LOW 0x3401
++#define REG_AWB_G_GAIN_HIGH 0x3402
++#define REG_AWB_G_GAIN_LOW 0x3403
++#define REG_AWB_B_GAIN_HIGH 0x3404
++#define REG_AWB_B_GAIN_LOW 0x3405
++
++#define CMD_ENABLE_OVERLAY 0x01
++#define CMD_DISABLE_OVERLAY 0x02
++#define CMD_SINGLE_FOCUS_MODE 0x03
++#define CMD_CONST_FOCUS_MODE 0x04
++#define CMD_STEP_FOCUS_MODE 0x05
++#define CMD_PAUSE 0x06
++#define CMD_IDLE_MODE 0x08
++#define CMD_SET_ZONE_MODE 0x10
++#define CMD_UPDATE_ZONE_MODE 0x12
++#define CMD_MOTOR_MODE 0x20
++#define CMD_SCAN_MODE 0x30
++
++#define OV5642_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5642_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5642_mode {
++ ov5642_mode_MIN = 0,
++ ov5642_mode_VGA_640_480 = 0,
++ ov5642_mode_QVGA_320_240 = 1,
++ ov5642_mode_NTSC_720_480 = 2,
++ ov5642_mode_PAL_720_576 = 3,
++ ov5642_mode_720P_1280_720 = 4,
++ ov5642_mode_1080P_1920_1080 = 5,
++ ov5642_mode_QSXGA_2592_1944 = 6,
++ ov5642_mode_QCIF_176_144 = 7,
++ ov5642_mode_XGA_1024_768 = 8,
++ ov5642_mode_MAX = 8
++};
++
++enum ov5642_frame_rate {
++ ov5642_15_fps,
++ ov5642_30_fps
++};
++
++static int ov5642_framerates[] = {
++ [ov5642_15_fps] = 15,
++ [ov5642_30_fps] = 30,
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5642_mode_info {
++ enum ov5642_mode mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct sensor_data ov5642_data;
++static int pwn_gpio, rst_gpio;
++
++static struct reg_value ov5642_rot_none_VGA[] = {
++ {0x3818, 0xc1, 0x00, 0x00}, {0x3621, 0x87, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_vert_flip_VGA[] = {
++ {0x3818, 0x20, 0xbf, 0x00}, {0x3621, 0x20, 0xff, 0x00},
++};
++
++static struct reg_value ov5642_rot_horiz_flip_VGA[] = {
++ {0x3818, 0x81, 0x00, 0x01}, {0x3621, 0xa7, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_180_VGA[] = {
++ {0x3818, 0x60, 0xff, 0x00}, {0x3621, 0x00, 0xdf, 0x00},
++};
++
++
++static struct reg_value ov5642_rot_none_FULL[] = {
++ {0x3818, 0xc0, 0x00, 0x00}, {0x3621, 0x09, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_vert_flip_FULL[] = {
++ {0x3818, 0x20, 0xbf, 0x01}, {0x3621, 0x20, 0xff, 0x00},
++};
++
++static struct reg_value ov5642_rot_horiz_flip_FULL[] = {
++ {0x3818, 0x80, 0x00, 0x01}, {0x3621, 0x29, 0x00, 0x00},
++};
++
++static struct reg_value ov5642_rot_180_FULL[] = {
++ {0x3818, 0x60, 0xff, 0x00}, {0x3621, 0x00, 0xdf, 0x00},
++};
++
++
++static struct reg_value ov5642_initial_setting[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c00, 0x04, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0},
++ {0x5182, 0x00, 0, 0}, {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5001, 0xff, 0, 0}, {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0},
++ {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0},
++ {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0},
++ {0x350b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x0b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 300},
++};
++
++static struct reg_value ov5642_af_firmware[] = {
++ {0x3000, 0x20, 0, 0},{0x8000, 0x02, 0, 0},{0x8001, 0x00, 0, 0},
++ {0x8002, 0x06, 0, 0},{0x8003, 0x02, 0, 0},{0x8004, 0x0b, 0, 0},
++ {0x8005, 0x44, 0, 0},{0x8006, 0x78, 0, 0},{0x8007, 0x7f, 0, 0},
++ {0x8008, 0xe4, 0, 0},{0x8009, 0xf6, 0, 0},{0x800a, 0xd8, 0, 0},
++ {0x800b, 0xfd, 0, 0},{0x800c, 0x75, 0, 0},{0x800d, 0x81, 0, 0},
++ {0x800e, 0x7d, 0, 0},{0x800f, 0x02, 0, 0},{0x8010, 0x13, 0, 0},
++ {0x8011, 0xb6, 0, 0},{0x8012, 0x00, 0, 0},{0x8013, 0x02, 0, 0},
++ {0x8014, 0x12, 0, 0},{0x8015, 0xe1, 0, 0},{0x8016, 0xe0, 0, 0},
++ {0x8017, 0xf5, 0, 0},{0x8018, 0x71, 0, 0},{0x8019, 0xa3, 0, 0},
++ {0x801a, 0xe0, 0, 0},{0x801b, 0xf5, 0, 0},{0x801c, 0x72, 0, 0},
++ {0x801d, 0xae, 0, 0},{0x801e, 0x69, 0, 0},{0x801f, 0xe4, 0, 0},
++ {0x8020, 0x85, 0, 0},{0x8021, 0x6a, 0, 0},{0x8022, 0x55, 0, 0},
++ {0x8023, 0x8e, 0, 0},{0x8024, 0x54, 0, 0},{0x8025, 0xf5, 0, 0},
++ {0x8026, 0x53, 0, 0},{0x8027, 0xf5, 0, 0},{0x8028, 0x52, 0, 0},
++ {0x8029, 0xab, 0, 0},{0x802a, 0x55, 0, 0},{0x802b, 0xaa, 0, 0},
++ {0x802c, 0x54, 0, 0},{0x802d, 0xa9, 0, 0},{0x802e, 0x53, 0, 0},
++ {0x802f, 0xa8, 0, 0},{0x8030, 0x52, 0, 0},{0x8031, 0xaf, 0, 0},
++ {0x8032, 0x2c, 0, 0},{0x8033, 0xfc, 0, 0},{0x8034, 0xfd, 0, 0},
++ {0x8035, 0xfe, 0, 0},{0x8036, 0x12, 0, 0},{0x8037, 0x08, 0, 0},
++ {0x8038, 0x7f, 0, 0},{0x8039, 0x8f, 0, 0},{0x803a, 0x55, 0, 0},
++ {0x803b, 0x8e, 0, 0},{0x803c, 0x54, 0, 0},{0x803d, 0x8d, 0, 0},
++ {0x803e, 0x53, 0, 0},{0x803f, 0x8c, 0, 0},{0x8040, 0x52, 0, 0},
++ {0x8041, 0xaf, 0, 0},{0x8042, 0x55, 0, 0},{0x8043, 0xae, 0, 0},
++ {0x8044, 0x54, 0, 0},{0x8045, 0xad, 0, 0},{0x8046, 0x53, 0, 0},
++ {0x8047, 0xac, 0, 0},{0x8048, 0x52, 0, 0},{0x8049, 0x8f, 0, 0},
++ {0x804a, 0x2b, 0, 0},{0x804b, 0x8e, 0, 0},{0x804c, 0x2a, 0, 0},
++ {0x804d, 0x8d, 0, 0},{0x804e, 0x29, 0, 0},{0x804f, 0x8c, 0, 0},
++ {0x8050, 0x28, 0, 0},{0x8051, 0xae, 0, 0},{0x8052, 0x6b, 0, 0},
++ {0x8053, 0xe4, 0, 0},{0x8054, 0x85, 0, 0},{0x8055, 0x6c, 0, 0},
++ {0x8056, 0x55, 0, 0},{0x8057, 0x8e, 0, 0},{0x8058, 0x54, 0, 0},
++ {0x8059, 0xf5, 0, 0},{0x805a, 0x53, 0, 0},{0x805b, 0xf5, 0, 0},
++ {0x805c, 0x52, 0, 0},{0x805d, 0xab, 0, 0},{0x805e, 0x55, 0, 0},
++ {0x805f, 0xaa, 0, 0},{0x8060, 0x54, 0, 0},{0x8061, 0xa9, 0, 0},
++ {0x8062, 0x53, 0, 0},{0x8063, 0xa8, 0, 0},{0x8064, 0x52, 0, 0},
++ {0x8065, 0xaf, 0, 0},{0x8066, 0x2d, 0, 0},{0x8067, 0xfc, 0, 0},
++ {0x8068, 0xfd, 0, 0},{0x8069, 0xfe, 0, 0},{0x806a, 0x12, 0, 0},
++ {0x806b, 0x08, 0, 0},{0x806c, 0x7f, 0, 0},{0x806d, 0x8f, 0, 0},
++ {0x806e, 0x55, 0, 0},{0x806f, 0x8e, 0, 0},{0x8070, 0x54, 0, 0},
++ {0x8071, 0x8d, 0, 0},{0x8072, 0x53, 0, 0},{0x8073, 0x8c, 0, 0},
++ {0x8074, 0x52, 0, 0},{0x8075, 0xe5, 0, 0},{0x8076, 0x2b, 0, 0},
++ {0x8077, 0x25, 0, 0},{0x8078, 0x55, 0, 0},{0x8079, 0xf5, 0, 0},
++ {0x807a, 0x2b, 0, 0},{0x807b, 0xe5, 0, 0},{0x807c, 0x2a, 0, 0},
++ {0x807d, 0x35, 0, 0},{0x807e, 0x54, 0, 0},{0x807f, 0xf5, 0, 0},
++ {0x8080, 0x2a, 0, 0},{0x8081, 0xe5, 0, 0},{0x8082, 0x29, 0, 0},
++ {0x8083, 0x35, 0, 0},{0x8084, 0x53, 0, 0},{0x8085, 0xf5, 0, 0},
++ {0x8086, 0x29, 0, 0},{0x8087, 0xe5, 0, 0},{0x8088, 0x28, 0, 0},
++ {0x8089, 0x35, 0, 0},{0x808a, 0x52, 0, 0},{0x808b, 0xf5, 0, 0},
++ {0x808c, 0x28, 0, 0},{0x808d, 0xae, 0, 0},{0x808e, 0x6d, 0, 0},
++ {0x808f, 0xe4, 0, 0},{0x8090, 0x85, 0, 0},{0x8091, 0x6e, 0, 0},
++ {0x8092, 0x55, 0, 0},{0x8093, 0x8e, 0, 0},{0x8094, 0x54, 0, 0},
++ {0x8095, 0xf5, 0, 0},{0x8096, 0x53, 0, 0},{0x8097, 0xf5, 0, 0},
++ {0x8098, 0x52, 0, 0},{0x8099, 0xab, 0, 0},{0x809a, 0x55, 0, 0},
++ {0x809b, 0xaa, 0, 0},{0x809c, 0x54, 0, 0},{0x809d, 0xa9, 0, 0},
++ {0x809e, 0x53, 0, 0},{0x809f, 0xa8, 0, 0},{0x80a0, 0x52, 0, 0},
++ {0x80a1, 0xaf, 0, 0},{0x80a2, 0x2e, 0, 0},{0x80a3, 0xfc, 0, 0},
++ {0x80a4, 0xfd, 0, 0},{0x80a5, 0xfe, 0, 0},{0x80a6, 0x12, 0, 0},
++ {0x80a7, 0x08, 0, 0},{0x80a8, 0x7f, 0, 0},{0x80a9, 0x8f, 0, 0},
++ {0x80aa, 0x55, 0, 0},{0x80ab, 0x8e, 0, 0},{0x80ac, 0x54, 0, 0},
++ {0x80ad, 0x8d, 0, 0},{0x80ae, 0x53, 0, 0},{0x80af, 0x8c, 0, 0},
++ {0x80b0, 0x52, 0, 0},{0x80b1, 0xe5, 0, 0},{0x80b2, 0x2b, 0, 0},
++ {0x80b3, 0x25, 0, 0},{0x80b4, 0x55, 0, 0},{0x80b5, 0xf5, 0, 0},
++ {0x80b6, 0x2b, 0, 0},{0x80b7, 0xe5, 0, 0},{0x80b8, 0x2a, 0, 0},
++ {0x80b9, 0x35, 0, 0},{0x80ba, 0x54, 0, 0},{0x80bb, 0xf5, 0, 0},
++ {0x80bc, 0x2a, 0, 0},{0x80bd, 0xe5, 0, 0},{0x80be, 0x29, 0, 0},
++ {0x80bf, 0x35, 0, 0},{0x80c0, 0x53, 0, 0},{0x80c1, 0xf5, 0, 0},
++ {0x80c2, 0x29, 0, 0},{0x80c3, 0xe5, 0, 0},{0x80c4, 0x28, 0, 0},
++ {0x80c5, 0x35, 0, 0},{0x80c6, 0x52, 0, 0},{0x80c7, 0xf5, 0, 0},
++ {0x80c8, 0x28, 0, 0},{0x80c9, 0xae, 0, 0},{0x80ca, 0x6f, 0, 0},
++ {0x80cb, 0xe4, 0, 0},{0x80cc, 0x85, 0, 0},{0x80cd, 0x70, 0, 0},
++ {0x80ce, 0x55, 0, 0},{0x80cf, 0x8e, 0, 0},{0x80d0, 0x54, 0, 0},
++ {0x80d1, 0xf5, 0, 0},{0x80d2, 0x53, 0, 0},{0x80d3, 0xf5, 0, 0},
++ {0x80d4, 0x52, 0, 0},{0x80d5, 0xab, 0, 0},{0x80d6, 0x55, 0, 0},
++ {0x80d7, 0xaa, 0, 0},{0x80d8, 0x54, 0, 0},{0x80d9, 0xa9, 0, 0},
++ {0x80da, 0x53, 0, 0},{0x80db, 0xa8, 0, 0},{0x80dc, 0x52, 0, 0},
++ {0x80dd, 0xaf, 0, 0},{0x80de, 0x2f, 0, 0},{0x80df, 0xfc, 0, 0},
++ {0x80e0, 0xfd, 0, 0},{0x80e1, 0xfe, 0, 0},{0x80e2, 0x12, 0, 0},
++ {0x80e3, 0x08, 0, 0},{0x80e4, 0x7f, 0, 0},{0x80e5, 0x8f, 0, 0},
++ {0x80e6, 0x55, 0, 0},{0x80e7, 0x8e, 0, 0},{0x80e8, 0x54, 0, 0},
++ {0x80e9, 0x8d, 0, 0},{0x80ea, 0x53, 0, 0},{0x80eb, 0x8c, 0, 0},
++ {0x80ec, 0x52, 0, 0},{0x80ed, 0xe5, 0, 0},{0x80ee, 0x2b, 0, 0},
++ {0x80ef, 0x25, 0, 0},{0x80f0, 0x55, 0, 0},{0x80f1, 0xf5, 0, 0},
++ {0x80f2, 0x2b, 0, 0},{0x80f3, 0xe5, 0, 0},{0x80f4, 0x2a, 0, 0},
++ {0x80f5, 0x35, 0, 0},{0x80f6, 0x54, 0, 0},{0x80f7, 0xf5, 0, 0},
++ {0x80f8, 0x2a, 0, 0},{0x80f9, 0xe5, 0, 0},{0x80fa, 0x29, 0, 0},
++ {0x80fb, 0x35, 0, 0},{0x80fc, 0x53, 0, 0},{0x80fd, 0xf5, 0, 0},
++ {0x80fe, 0x29, 0, 0},{0x80ff, 0xe5, 0, 0},{0x8100, 0x28, 0, 0},
++ {0x8101, 0x35, 0, 0},{0x8102, 0x52, 0, 0},{0x8103, 0xf5, 0, 0},
++ {0x8104, 0x28, 0, 0},{0x8105, 0xae, 0, 0},{0x8106, 0x71, 0, 0},
++ {0x8107, 0xe4, 0, 0},{0x8108, 0x85, 0, 0},{0x8109, 0x72, 0, 0},
++ {0x810a, 0x55, 0, 0},{0x810b, 0x8e, 0, 0},{0x810c, 0x54, 0, 0},
++ {0x810d, 0xf5, 0, 0},{0x810e, 0x53, 0, 0},{0x810f, 0xf5, 0, 0},
++ {0x8110, 0x52, 0, 0},{0x8111, 0xab, 0, 0},{0x8112, 0x55, 0, 0},
++ {0x8113, 0xaa, 0, 0},{0x8114, 0x54, 0, 0},{0x8115, 0xa9, 0, 0},
++ {0x8116, 0x53, 0, 0},{0x8117, 0xa8, 0, 0},{0x8118, 0x52, 0, 0},
++ {0x8119, 0xaf, 0, 0},{0x811a, 0x30, 0, 0},{0x811b, 0xfc, 0, 0},
++ {0x811c, 0xfd, 0, 0},{0x811d, 0xfe, 0, 0},{0x811e, 0x12, 0, 0},
++ {0x811f, 0x08, 0, 0},{0x8120, 0x7f, 0, 0},{0x8121, 0x8f, 0, 0},
++ {0x8122, 0x55, 0, 0},{0x8123, 0x8e, 0, 0},{0x8124, 0x54, 0, 0},
++ {0x8125, 0x8d, 0, 0},{0x8126, 0x53, 0, 0},{0x8127, 0x8c, 0, 0},
++ {0x8128, 0x52, 0, 0},{0x8129, 0xe5, 0, 0},{0x812a, 0x2b, 0, 0},
++ {0x812b, 0x25, 0, 0},{0x812c, 0x55, 0, 0},{0x812d, 0xf5, 0, 0},
++ {0x812e, 0x2b, 0, 0},{0x812f, 0xe5, 0, 0},{0x8130, 0x2a, 0, 0},
++ {0x8131, 0x35, 0, 0},{0x8132, 0x54, 0, 0},{0x8133, 0xf5, 0, 0},
++ {0x8134, 0x2a, 0, 0},{0x8135, 0xe5, 0, 0},{0x8136, 0x29, 0, 0},
++ {0x8137, 0x35, 0, 0},{0x8138, 0x53, 0, 0},{0x8139, 0xf5, 0, 0},
++ {0x813a, 0x29, 0, 0},{0x813b, 0xe5, 0, 0},{0x813c, 0x28, 0, 0},
++ {0x813d, 0x35, 0, 0},{0x813e, 0x52, 0, 0},{0x813f, 0xf5, 0, 0},
++ {0x8140, 0x28, 0, 0},{0x8141, 0x22, 0, 0},{0x8142, 0xab, 0, 0},
++ {0x8143, 0x0d, 0, 0},{0x8144, 0xaa, 0, 0},{0x8145, 0x0c, 0, 0},
++ {0x8146, 0xa9, 0, 0},{0x8147, 0x0b, 0, 0},{0x8148, 0xa8, 0, 0},
++ {0x8149, 0x0a, 0, 0},{0x814a, 0xfc, 0, 0},{0x814b, 0xfd, 0, 0},
++ {0x814c, 0xfe, 0, 0},{0x814d, 0x12, 0, 0},{0x814e, 0x08, 0, 0},
++ {0x814f, 0x7f, 0, 0},{0x8150, 0x8f, 0, 0},{0x8151, 0x0d, 0, 0},
++ {0x8152, 0x8e, 0, 0},{0x8153, 0x0c, 0, 0},{0x8154, 0x8d, 0, 0},
++ {0x8155, 0x0b, 0, 0},{0x8156, 0x8c, 0, 0},{0x8157, 0x0a, 0, 0},
++ {0x8158, 0x7b, 0, 0},{0x8159, 0x40, 0, 0},{0x815a, 0xe4, 0, 0},
++ {0x815b, 0xfa, 0, 0},{0x815c, 0xf9, 0, 0},{0x815d, 0xf8, 0, 0},
++ {0x815e, 0x12, 0, 0},{0x815f, 0x09, 0, 0},{0x8160, 0x0a, 0, 0},
++ {0x8161, 0x8f, 0, 0},{0x8162, 0x0d, 0, 0},{0x8163, 0x8e, 0, 0},
++ {0x8164, 0x0c, 0, 0},{0x8165, 0x8d, 0, 0},{0x8166, 0x0b, 0, 0},
++ {0x8167, 0x8c, 0, 0},{0x8168, 0x0a, 0, 0},{0x8169, 0x22, 0, 0},
++ {0x816a, 0xd2, 0, 0},{0x816b, 0x29, 0, 0},{0x816c, 0x90, 0, 0},
++ {0x816d, 0x30, 0, 0},{0x816e, 0x1b, 0, 0},{0x816f, 0xe5, 0, 0},
++ {0x8170, 0x25, 0, 0},{0x8171, 0xf0, 0, 0},{0x8172, 0x22, 0, 0},
++ {0x8173, 0xfe, 0, 0},{0x8174, 0xe4, 0, 0},{0x8175, 0xfc, 0, 0},
++ {0x8176, 0xfd, 0, 0},{0x8177, 0xe5, 0, 0},{0x8178, 0x3f, 0, 0},
++ {0x8179, 0x2f, 0, 0},{0x817a, 0xf5, 0, 0},{0x817b, 0x3f, 0, 0},
++ {0x817c, 0xe5, 0, 0},{0x817d, 0x3e, 0, 0},{0x817e, 0x3e, 0, 0},
++ {0x817f, 0xf5, 0, 0},{0x8180, 0x3e, 0, 0},{0x8181, 0xed, 0, 0},
++ {0x8182, 0x35, 0, 0},{0x8183, 0x3d, 0, 0},{0x8184, 0xf5, 0, 0},
++ {0x8185, 0x3d, 0, 0},{0x8186, 0xec, 0, 0},{0x8187, 0x35, 0, 0},
++ {0x8188, 0x3c, 0, 0},{0x8189, 0xf5, 0, 0},{0x818a, 0x3c, 0, 0},
++ {0x818b, 0xaf, 0, 0},{0x818c, 0x3f, 0, 0},{0x818d, 0xae, 0, 0},
++ {0x818e, 0x3e, 0, 0},{0x818f, 0xfc, 0, 0},{0x8190, 0xad, 0, 0},
++ {0x8191, 0x3d, 0, 0},{0x8192, 0x78, 0, 0},{0x8193, 0x08, 0, 0},
++ {0x8194, 0x12, 0, 0},{0x8195, 0x09, 0, 0},{0x8196, 0xaf, 0, 0},
++ {0x8197, 0x8f, 0, 0},{0x8198, 0x3f, 0, 0},{0x8199, 0x8e, 0, 0},
++ {0x819a, 0x3e, 0, 0},{0x819b, 0x8d, 0, 0},{0x819c, 0x3d, 0, 0},
++ {0x819d, 0x8c, 0, 0},{0x819e, 0x3c, 0, 0},{0x819f, 0x22, 0, 0},
++ {0x81a0, 0xe5, 0, 0},{0x81a1, 0x49, 0, 0},{0x81a2, 0x25, 0, 0},
++ {0x81a3, 0x7b, 0, 0},{0x81a4, 0xf5, 0, 0},{0x81a5, 0x82, 0, 0},
++ {0x81a6, 0xe4, 0, 0},{0x81a7, 0x35, 0, 0},{0x81a8, 0x48, 0, 0},
++ {0x81a9, 0xf5, 0, 0},{0x81aa, 0x83, 0, 0},{0x81ab, 0xe4, 0, 0},
++ {0x81ac, 0x93, 0, 0},{0x81ad, 0xff, 0, 0},{0x81ae, 0x85, 0, 0},
++ {0x81af, 0x49, 0, 0},{0x81b0, 0x82, 0, 0},{0x81b1, 0x85, 0, 0},
++ {0x81b2, 0x48, 0, 0},{0x81b3, 0x83, 0, 0},{0x81b4, 0xe4, 0, 0},
++ {0x81b5, 0x93, 0, 0},{0x81b6, 0xfd, 0, 0},{0x81b7, 0xc3, 0, 0},
++ {0x81b8, 0xef, 0, 0},{0x81b9, 0x9d, 0, 0},{0x81ba, 0xff, 0, 0},
++ {0x81bb, 0xe4, 0, 0},{0x81bc, 0x94, 0, 0},{0x81bd, 0x00, 0, 0},
++ {0x81be, 0x22, 0, 0},{0x81bf, 0xe5, 0, 0},{0x81c0, 0x0b, 0, 0},
++ {0x81c1, 0x24, 0, 0},{0x81c2, 0x01, 0, 0},{0x81c3, 0xff, 0, 0},
++ {0x81c4, 0xe4, 0, 0},{0x81c5, 0x33, 0, 0},{0x81c6, 0xfe, 0, 0},
++ {0x81c7, 0x22, 0, 0},{0x81c8, 0xaf, 0, 0},{0x81c9, 0x2b, 0, 0},
++ {0x81ca, 0xae, 0, 0},{0x81cb, 0x2a, 0, 0},{0x81cc, 0xad, 0, 0},
++ {0x81cd, 0x29, 0, 0},{0x81ce, 0xac, 0, 0},{0x81cf, 0x28, 0, 0},
++ {0x81d0, 0x78, 0, 0},{0x81d1, 0x06, 0, 0},{0x81d2, 0x12, 0, 0},
++ {0x81d3, 0x09, 0, 0},{0x81d4, 0x9c, 0, 0},{0x81d5, 0x8f, 0, 0},
++ {0x81d6, 0x2b, 0, 0},{0x81d7, 0x8e, 0, 0},{0x81d8, 0x2a, 0, 0},
++ {0x81d9, 0x8d, 0, 0},{0x81da, 0x29, 0, 0},{0x81db, 0x8c, 0, 0},
++ {0x81dc, 0x28, 0, 0},{0x81dd, 0xd3, 0, 0},{0x81de, 0xe5, 0, 0},
++ {0x81df, 0x29, 0, 0},{0x81e0, 0x94, 0, 0},{0x81e1, 0x00, 0, 0},
++ {0x81e2, 0xe5, 0, 0},{0x81e3, 0x28, 0, 0},{0x81e4, 0x94, 0, 0},
++ {0x81e5, 0x00, 0, 0},{0x81e6, 0x22, 0, 0},{0x81e7, 0x12, 0, 0},
++ {0x81e8, 0x08, 0, 0},{0x81e9, 0x7f, 0, 0},{0x81ea, 0x8f, 0, 0},
++ {0x81eb, 0x68, 0, 0},{0x81ec, 0x8e, 0, 0},{0x81ed, 0x67, 0, 0},
++ {0x81ee, 0x8d, 0, 0},{0x81ef, 0x66, 0, 0},{0x81f0, 0x8c, 0, 0},
++ {0x81f1, 0x65, 0, 0},{0x81f2, 0xaf, 0, 0},{0x81f3, 0x68, 0, 0},
++ {0x81f4, 0xae, 0, 0},{0x81f5, 0x67, 0, 0},{0x81f6, 0xad, 0, 0},
++ {0x81f7, 0x66, 0, 0},{0x81f8, 0xac, 0, 0},{0x81f9, 0x65, 0, 0},
++ {0x81fa, 0x22, 0, 0},{0x81fb, 0xe0, 0, 0},{0x81fc, 0x44, 0, 0},
++ {0x81fd, 0x01, 0, 0},{0x81fe, 0xf0, 0, 0},{0x81ff, 0xe0, 0, 0},
++ {0x8200, 0x44, 0, 0},{0x8201, 0x02, 0, 0},{0x8202, 0xf0, 0, 0},
++ {0x8203, 0xe0, 0, 0},{0x8204, 0x44, 0, 0},{0x8205, 0x04, 0, 0},
++ {0x8206, 0xf0, 0, 0},{0x8207, 0x22, 0, 0},{0x8208, 0xd2, 0, 0},
++ {0x8209, 0x09, 0, 0},{0x820a, 0x90, 0, 0},{0x820b, 0x30, 0, 0},
++ {0x820c, 0x18, 0, 0},{0x820d, 0xe5, 0, 0},{0x820e, 0x21, 0, 0},
++ {0x820f, 0xf0, 0, 0},{0x8210, 0x22, 0, 0},{0x8211, 0xe4, 0, 0},
++ {0x8212, 0x85, 0, 0},{0x8213, 0x11, 0, 0},{0x8214, 0x0d, 0, 0},
++ {0x8215, 0x85, 0, 0},{0x8216, 0x10, 0, 0},{0x8217, 0x0c, 0, 0},
++ {0x8218, 0xf5, 0, 0},{0x8219, 0x0b, 0, 0},{0x821a, 0xf5, 0, 0},
++ {0x821b, 0x0a, 0, 0},{0x821c, 0xab, 0, 0},{0x821d, 0x0d, 0, 0},
++ {0x821e, 0xaa, 0, 0},{0x821f, 0x0c, 0, 0},{0x8220, 0xa9, 0, 0},
++ {0x8221, 0x0b, 0, 0},{0x8222, 0xa8, 0, 0},{0x8223, 0x0a, 0, 0},
++ {0x8224, 0x22, 0, 0},{0x8225, 0x90, 0, 0},{0x8226, 0x30, 0, 0},
++ {0x8227, 0x42, 0, 0},{0x8228, 0xe0, 0, 0},{0x8229, 0xf5, 0, 0},
++ {0x822a, 0x22, 0, 0},{0x822b, 0x75, 0, 0},{0x822c, 0x51, 0, 0},
++ {0x822d, 0x0a, 0, 0},{0x822e, 0x22, 0, 0},{0x822f, 0xf5, 0, 0},
++ {0x8230, 0x82, 0, 0},{0x8231, 0xe4, 0, 0},{0x8232, 0x3a, 0, 0},
++ {0x8233, 0xf5, 0, 0},{0x8234, 0x83, 0, 0},{0x8235, 0x02, 0, 0},
++ {0x8236, 0x09, 0, 0},{0x8237, 0xc2, 0, 0},{0x8238, 0x8f, 0, 0},
++ {0x8239, 0x0a, 0, 0},{0x823a, 0x74, 0, 0},{0x823b, 0x4a, 0, 0},
++ {0x823c, 0x2f, 0, 0},{0x823d, 0xf8, 0, 0},{0x823e, 0xe6, 0, 0},
++ {0x823f, 0x22, 0, 0},{0x8240, 0xc2, 0, 0},{0x8241, 0x07, 0, 0},
++ {0x8242, 0xc2, 0, 0},{0x8243, 0x06, 0, 0},{0x8244, 0xc2, 0, 0},
++ {0x8245, 0x02, 0, 0},{0x8246, 0xc2, 0, 0},{0x8247, 0x01, 0, 0},
++ {0x8248, 0xc2, 0, 0},{0x8249, 0x00, 0, 0},{0x824a, 0xc2, 0, 0},
++ {0x824b, 0x03, 0, 0},{0x824c, 0xd2, 0, 0},{0x824d, 0x04, 0, 0},
++ {0x824e, 0x22, 0, 0},{0x824f, 0xf5, 0, 0},{0x8250, 0x82, 0, 0},
++ {0x8251, 0xe4, 0, 0},{0x8252, 0x35, 0, 0},{0x8253, 0x48, 0, 0},
++ {0x8254, 0xf5, 0, 0},{0x8255, 0x83, 0, 0},{0x8256, 0xe4, 0, 0},
++ {0x8257, 0x22, 0, 0},{0x8258, 0x8e, 0, 0},{0x8259, 0x67, 0, 0},
++ {0x825a, 0x8f, 0, 0},{0x825b, 0x68, 0, 0},{0x825c, 0x85, 0, 0},
++ {0x825d, 0x68, 0, 0},{0x825e, 0x64, 0, 0},{0x825f, 0xe5, 0, 0},
++ {0x8260, 0x68, 0, 0},{0x8261, 0xae, 0, 0},{0x8262, 0x67, 0, 0},
++ {0x8263, 0x78, 0, 0},{0x8264, 0x06, 0, 0},{0x8265, 0x22, 0, 0},
++ {0x8266, 0xe5, 0, 0},{0x8267, 0x16, 0, 0},{0x8268, 0x25, 0, 0},
++ {0x8269, 0xe0, 0, 0},{0x826a, 0x25, 0, 0},{0x826b, 0xe0, 0, 0},
++ {0x826c, 0x22, 0, 0},{0x826d, 0x12, 0, 0},{0x826e, 0x09, 0, 0},
++ {0x826f, 0x0a, 0, 0},{0x8270, 0x8f, 0, 0},{0x8271, 0x68, 0, 0},
++ {0x8272, 0x8e, 0, 0},{0x8273, 0x67, 0, 0},{0x8274, 0x8d, 0, 0},
++ {0x8275, 0x66, 0, 0},{0x8276, 0x8c, 0, 0},{0x8277, 0x65, 0, 0},
++ {0x8278, 0x22, 0, 0},{0x8279, 0xe4, 0, 0},{0x827a, 0x85, 0, 0},
++ {0x827b, 0x0f, 0, 0},{0x827c, 0x0d, 0, 0},{0x827d, 0x85, 0, 0},
++ {0x827e, 0x0e, 0, 0},{0x827f, 0x0c, 0, 0},{0x8280, 0xf5, 0, 0},
++ {0x8281, 0x0b, 0, 0},{0x8282, 0xf5, 0, 0},{0x8283, 0x0a, 0, 0},
++ {0x8284, 0x22, 0, 0},{0x8285, 0x90, 0, 0},{0x8286, 0x11, 0, 0},
++ {0x8287, 0xdd, 0, 0},{0x8288, 0xe4, 0, 0},{0x8289, 0x93, 0, 0},
++ {0x828a, 0xff, 0, 0},{0x828b, 0x90, 0, 0},{0x828c, 0x30, 0, 0},
++ {0x828d, 0x0a, 0, 0},{0x828e, 0xe0, 0, 0},{0x828f, 0x22, 0, 0},
++ {0x8290, 0xc2, 0, 0},{0x8291, 0x02, 0, 0},{0x8292, 0xc2, 0, 0},
++ {0x8293, 0x01, 0, 0},{0x8294, 0xd2, 0, 0},{0x8295, 0x00, 0, 0},
++ {0x8296, 0xc2, 0, 0},{0x8297, 0x03, 0, 0},{0x8298, 0xc2, 0, 0},
++ {0x8299, 0x04, 0, 0},{0x829a, 0x22, 0, 0},{0x829b, 0x85, 0, 0},
++ {0x829c, 0x0e, 0, 0},{0x829d, 0x64, 0, 0},{0x829e, 0xe5, 0, 0},
++ {0x829f, 0x0e, 0, 0},{0x82a0, 0xae, 0, 0},{0x82a1, 0x0d, 0, 0},
++ {0x82a2, 0x78, 0, 0},{0x82a3, 0x06, 0, 0},{0x82a4, 0x22, 0, 0},
++ {0x82a5, 0xd2, 0, 0},{0x82a6, 0x02, 0, 0},{0x82a7, 0xd2, 0, 0},
++ {0x82a8, 0x01, 0, 0},{0x82a9, 0xc2, 0, 0},{0x82aa, 0x00, 0, 0},
++ {0x82ab, 0x22, 0, 0},{0x82ac, 0xd3, 0, 0},{0x82ad, 0xe5, 0, 0},
++ {0x82ae, 0x68, 0, 0},{0x82af, 0x94, 0, 0},{0x82b0, 0xff, 0, 0},
++ {0x82b1, 0xe5, 0, 0},{0x82b2, 0x67, 0, 0},{0x82b3, 0x94, 0, 0},
++ {0x82b4, 0x00, 0, 0},{0x82b5, 0x22, 0, 0},{0x82b6, 0x30, 0, 0},
++ {0x82b7, 0x18, 0, 0},{0x82b8, 0x50, 0, 0},{0x82b9, 0x20, 0, 0},
++ {0x82ba, 0x19, 0, 0},{0x82bb, 0x4d, 0, 0},{0x82bc, 0x75, 0, 0},
++ {0x82bd, 0x0a, 0, 0},{0x82be, 0x02, 0, 0},{0x82bf, 0x74, 0, 0},
++ {0x82c0, 0x4a, 0, 0},{0x82c1, 0x25, 0, 0},{0x82c2, 0x0a, 0, 0},
++ {0x82c3, 0xf8, 0, 0},{0x82c4, 0xe6, 0, 0},{0x82c5, 0xff, 0, 0},
++ {0x82c6, 0xe5, 0, 0},{0x82c7, 0x4a, 0, 0},{0x82c8, 0xd3, 0, 0},
++ {0x82c9, 0x9f, 0, 0},{0x82ca, 0x40, 0, 0},{0x82cb, 0x04, 0, 0},
++ {0x82cc, 0x7f, 0, 0},{0x82cd, 0x00, 0, 0},{0x82ce, 0x80, 0, 0},
++ {0x82cf, 0x02, 0, 0},{0x82d0, 0xaf, 0, 0},{0x82d1, 0x0a, 0, 0},
++ {0x82d2, 0x12, 0, 0},{0x82d3, 0x02, 0, 0},{0x82d4, 0x38, 0, 0},
++ {0x82d5, 0xff, 0, 0},{0x82d6, 0xe5, 0, 0},{0x82d7, 0x4b, 0, 0},
++ {0x82d8, 0xd3, 0, 0},{0x82d9, 0x9f, 0, 0},{0x82da, 0x40, 0, 0},
++ {0x82db, 0x04, 0, 0},{0x82dc, 0x7f, 0, 0},{0x82dd, 0x01, 0, 0},
++ {0x82de, 0x80, 0, 0},{0x82df, 0x02, 0, 0},{0x82e0, 0xaf, 0, 0},
++ {0x82e1, 0x0a, 0, 0},{0x82e2, 0x12, 0, 0},{0x82e3, 0x02, 0, 0},
++ {0x82e4, 0x38, 0, 0},{0x82e5, 0xff, 0, 0},{0x82e6, 0xe5, 0, 0},
++ {0x82e7, 0x4d, 0, 0},{0x82e8, 0xd3, 0, 0},{0x82e9, 0x9f, 0, 0},
++ {0x82ea, 0x40, 0, 0},{0x82eb, 0x04, 0, 0},{0x82ec, 0x7f, 0, 0},
++ {0x82ed, 0x03, 0, 0},{0x82ee, 0x80, 0, 0},{0x82ef, 0x02, 0, 0},
++ {0x82f0, 0xaf, 0, 0},{0x82f1, 0x0a, 0, 0},{0x82f2, 0x12, 0, 0},
++ {0x82f3, 0x02, 0, 0},{0x82f4, 0x38, 0, 0},{0x82f5, 0xff, 0, 0},
++ {0x82f6, 0xe5, 0, 0},{0x82f7, 0x4e, 0, 0},{0x82f8, 0xd3, 0, 0},
++ {0x82f9, 0x9f, 0, 0},{0x82fa, 0x40, 0, 0},{0x82fb, 0x04, 0, 0},
++ {0x82fc, 0x7f, 0, 0},{0x82fd, 0x04, 0, 0},{0x82fe, 0x80, 0, 0},
++ {0x82ff, 0x02, 0, 0},{0x8300, 0xaf, 0, 0},{0x8301, 0x0a, 0, 0},
++ {0x8302, 0x12, 0, 0},{0x8303, 0x02, 0, 0},{0x8304, 0x38, 0, 0},
++ {0x8305, 0xf5, 0, 0},{0x8306, 0x0b, 0, 0},{0x8307, 0x80, 0, 0},
++ {0x8308, 0x06, 0, 0},{0x8309, 0x85, 0, 0},{0x830a, 0x78, 0, 0},
++ {0x830b, 0x0a, 0, 0},{0x830c, 0x85, 0, 0},{0x830d, 0x4f, 0, 0},
++ {0x830e, 0x0b, 0, 0},{0x830f, 0x7f, 0, 0},{0x8310, 0x01, 0, 0},
++ {0x8311, 0xe4, 0, 0},{0x8312, 0xfe, 0, 0},{0x8313, 0x74, 0, 0},
++ {0x8314, 0x4a, 0, 0},{0x8315, 0x25, 0, 0},{0x8316, 0x0a, 0, 0},
++ {0x8317, 0xf8, 0, 0},{0x8318, 0xe6, 0, 0},{0x8319, 0xfd, 0, 0},
++ {0x831a, 0xe5, 0, 0},{0x831b, 0x0b, 0, 0},{0x831c, 0xc3, 0, 0},
++ {0x831d, 0x9d, 0, 0},{0x831e, 0x50, 0, 0},{0x831f, 0x04, 0, 0},
++ {0x8320, 0x7d, 0, 0},{0x8321, 0x01, 0, 0},{0x8322, 0x80, 0, 0},
++ {0x8323, 0x02, 0, 0},{0x8324, 0x7d, 0, 0},{0x8325, 0xff, 0, 0},
++ {0x8326, 0xac, 0, 0},{0x8327, 0x0b, 0, 0},{0x8328, 0xe5, 0, 0},
++ {0x8329, 0x4e, 0, 0},{0x832a, 0xb5, 0, 0},{0x832b, 0x0b, 0, 0},
++ {0x832c, 0x03, 0, 0},{0x832d, 0xd3, 0, 0},{0x832e, 0x80, 0, 0},
++ {0x832f, 0x01, 0, 0},{0x8330, 0xc3, 0, 0},{0x8331, 0x92, 0, 0},
++ {0x8332, 0x1f, 0, 0},{0x8333, 0xe5, 0, 0},{0x8334, 0x4d, 0, 0},
++ {0x8335, 0xb5, 0, 0},{0x8336, 0x0b, 0, 0},{0x8337, 0x03, 0, 0},
++ {0x8338, 0xd3, 0, 0},{0x8339, 0x80, 0, 0},{0x833a, 0x01, 0, 0},
++ {0x833b, 0xc3, 0, 0},{0x833c, 0x92, 0, 0},{0x833d, 0x1e, 0, 0},
++ {0x833e, 0xe5, 0, 0},{0x833f, 0x4c, 0, 0},{0x8340, 0xb5, 0, 0},
++ {0x8341, 0x0b, 0, 0},{0x8342, 0x03, 0, 0},{0x8343, 0xd3, 0, 0},
++ {0x8344, 0x80, 0, 0},{0x8345, 0x01, 0, 0},{0x8346, 0xc3, 0, 0},
++ {0x8347, 0x92, 0, 0},{0x8348, 0x1d, 0, 0},{0x8349, 0xe5, 0, 0},
++ {0x834a, 0x4b, 0, 0},{0x834b, 0xb5, 0, 0},{0x834c, 0x0b, 0, 0},
++ {0x834d, 0x03, 0, 0},{0x834e, 0xd3, 0, 0},{0x834f, 0x80, 0, 0},
++ {0x8350, 0x01, 0, 0},{0x8351, 0xc3, 0, 0},{0x8352, 0x92, 0, 0},
++ {0x8353, 0x1c, 0, 0},{0x8354, 0xe5, 0, 0},{0x8355, 0x4a, 0, 0},
++ {0x8356, 0xb5, 0, 0},{0x8357, 0x0b, 0, 0},{0x8358, 0x03, 0, 0},
++ {0x8359, 0xd3, 0, 0},{0x835a, 0x80, 0, 0},{0x835b, 0x01, 0, 0},
++ {0x835c, 0xc3, 0, 0},{0x835d, 0x92, 0, 0},{0x835e, 0x1b, 0, 0},
++ {0x835f, 0xe5, 0, 0},{0x8360, 0x30, 0, 0},{0x8361, 0xd3, 0, 0},
++ {0x8362, 0x94, 0, 0},{0x8363, 0x00, 0, 0},{0x8364, 0x40, 0, 0},
++ {0x8365, 0x04, 0, 0},{0x8366, 0xa2, 0, 0},{0x8367, 0x1f, 0, 0},
++ {0x8368, 0x80, 0, 0},{0x8369, 0x01, 0, 0},{0x836a, 0xc3, 0, 0},
++ {0x836b, 0x92, 0, 0},{0x836c, 0x1f, 0, 0},{0x836d, 0xe5, 0, 0},
++ {0x836e, 0x2f, 0, 0},{0x836f, 0xd3, 0, 0},{0x8370, 0x94, 0, 0},
++ {0x8371, 0x00, 0, 0},{0x8372, 0x40, 0, 0},{0x8373, 0x04, 0, 0},
++ {0x8374, 0xa2, 0, 0},{0x8375, 0x1e, 0, 0},{0x8376, 0x80, 0, 0},
++ {0x8377, 0x01, 0, 0},{0x8378, 0xc3, 0, 0},{0x8379, 0x92, 0, 0},
++ {0x837a, 0x1e, 0, 0},{0x837b, 0xe5, 0, 0},{0x837c, 0x2e, 0, 0},
++ {0x837d, 0xd3, 0, 0},{0x837e, 0x94, 0, 0},{0x837f, 0x00, 0, 0},
++ {0x8380, 0x40, 0, 0},{0x8381, 0x04, 0, 0},{0x8382, 0xa2, 0, 0},
++ {0x8383, 0x1d, 0, 0},{0x8384, 0x80, 0, 0},{0x8385, 0x01, 0, 0},
++ {0x8386, 0xc3, 0, 0},{0x8387, 0x92, 0, 0},{0x8388, 0x1d, 0, 0},
++ {0x8389, 0xe5, 0, 0},{0x838a, 0x2d, 0, 0},{0x838b, 0xd3, 0, 0},
++ {0x838c, 0x94, 0, 0},{0x838d, 0x00, 0, 0},{0x838e, 0x40, 0, 0},
++ {0x838f, 0x04, 0, 0},{0x8390, 0xa2, 0, 0},{0x8391, 0x1c, 0, 0},
++ {0x8392, 0x80, 0, 0},{0x8393, 0x01, 0, 0},{0x8394, 0xc3, 0, 0},
++ {0x8395, 0x92, 0, 0},{0x8396, 0x1c, 0, 0},{0x8397, 0xe5, 0, 0},
++ {0x8398, 0x2c, 0, 0},{0x8399, 0xd3, 0, 0},{0x839a, 0x94, 0, 0},
++ {0x839b, 0x00, 0, 0},{0x839c, 0x40, 0, 0},{0x839d, 0x04, 0, 0},
++ {0x839e, 0xa2, 0, 0},{0x839f, 0x1b, 0, 0},{0x83a0, 0x80, 0, 0},
++ {0x83a1, 0x01, 0, 0},{0x83a2, 0xc3, 0, 0},{0x83a3, 0x92, 0, 0},
++ {0x83a4, 0x1b, 0, 0},{0x83a5, 0xe5, 0, 0},{0x83a6, 0x23, 0, 0},
++ {0x83a7, 0x54, 0, 0},{0x83a8, 0xf8, 0, 0},{0x83a9, 0x70, 0, 0},
++ {0x83aa, 0x43, 0, 0},{0x83ab, 0xbf, 0, 0},{0x83ac, 0x01, 0, 0},
++ {0x83ad, 0x08, 0, 0},{0x83ae, 0xed, 0, 0},{0x83af, 0xf4, 0, 0},
++ {0x83b0, 0x04, 0, 0},{0x83b1, 0xfd, 0, 0},{0x83b2, 0x7f, 0, 0},
++ {0x83b3, 0x02, 0, 0},{0x83b4, 0x80, 0, 0},{0x83b5, 0x06, 0, 0},
++ {0x83b6, 0xbf, 0, 0},{0x83b7, 0x02, 0, 0},{0x83b8, 0x02, 0, 0},
++ {0x83b9, 0x7f, 0, 0},{0x83ba, 0x01, 0, 0},{0x83bb, 0x0e, 0, 0},
++ {0x83bc, 0xd3, 0, 0},{0x83bd, 0xed, 0, 0},{0x83be, 0x64, 0, 0},
++ {0x83bf, 0x80, 0, 0},{0x83c0, 0x94, 0, 0},{0x83c1, 0x80, 0, 0},
++ {0x83c2, 0x40, 0, 0},{0x83c3, 0x12, 0, 0},{0x83c4, 0xec, 0, 0},
++ {0x83c5, 0x2e, 0, 0},{0x83c6, 0xf5, 0, 0},{0x83c7, 0x0b, 0, 0},
++ {0x83c8, 0xc3, 0, 0},{0x83c9, 0x95, 0, 0},{0x83ca, 0x7b, 0, 0},
++ {0x83cb, 0x50, 0, 0},{0x83cc, 0x03, 0, 0},{0x83cd, 0x02, 0, 0},
++ {0x83ce, 0x03, 0, 0},{0x83cf, 0x28, 0, 0},{0x83d0, 0x7d, 0, 0},
++ {0x83d1, 0xff, 0, 0},{0x83d2, 0xe4, 0, 0},{0x83d3, 0xff, 0, 0},
++ {0x83d4, 0x80, 0, 0},{0x83d5, 0x11, 0, 0},{0x83d6, 0xec, 0, 0},
++ {0x83d7, 0xd3, 0, 0},{0x83d8, 0x9e, 0, 0},{0x83d9, 0x50, 0, 0},
++ {0x83da, 0x0b, 0, 0},{0x83db, 0x7d, 0, 0},{0x83dc, 0x01, 0, 0},
++ {0x83dd, 0xe4, 0, 0},{0x83de, 0xff, 0, 0},{0x83df, 0xec, 0, 0},
++ {0x83e0, 0x2e, 0, 0},{0x83e1, 0xf5, 0, 0},{0x83e2, 0x0b, 0, 0},
++ {0x83e3, 0x02, 0, 0},{0x83e4, 0x03, 0, 0},{0x83e5, 0x28, 0, 0},
++ {0x83e6, 0xc3, 0, 0},{0x83e7, 0xec, 0, 0},{0x83e8, 0x9e, 0, 0},
++ {0x83e9, 0xf5, 0, 0},{0x83ea, 0x0b, 0, 0},{0x83eb, 0x02, 0, 0},
++ {0x83ec, 0x03, 0, 0},{0x83ed, 0x28, 0, 0},{0x83ee, 0x12, 0, 0},
++ {0x83ef, 0x01, 0, 0},{0x83f0, 0xbf, 0, 0},{0x83f1, 0xe5, 0, 0},
++ {0x83f2, 0x4e, 0, 0},{0x83f3, 0xb5, 0, 0},{0x83f4, 0x07, 0, 0},
++ {0x83f5, 0x07, 0, 0},{0x83f6, 0xe4, 0, 0},{0x83f7, 0xb5, 0, 0},
++ {0x83f8, 0x06, 0, 0},{0x83f9, 0x03, 0, 0},{0x83fa, 0xd3, 0, 0},
++ {0x83fb, 0x80, 0, 0},{0x83fc, 0x02, 0, 0},{0x83fd, 0xa2, 0, 0},
++ {0x83fe, 0x1f, 0, 0},{0x83ff, 0x92, 0, 0},{0x8400, 0x1f, 0, 0},
++ {0x8401, 0xe5, 0, 0},{0x8402, 0x4d, 0, 0},{0x8403, 0xb5, 0, 0},
++ {0x8404, 0x07, 0, 0},{0x8405, 0x07, 0, 0},{0x8406, 0xe4, 0, 0},
++ {0x8407, 0xb5, 0, 0},{0x8408, 0x06, 0, 0},{0x8409, 0x03, 0, 0},
++ {0x840a, 0xd3, 0, 0},{0x840b, 0x80, 0, 0},{0x840c, 0x02, 0, 0},
++ {0x840d, 0xa2, 0, 0},{0x840e, 0x1e, 0, 0},{0x840f, 0x92, 0, 0},
++ {0x8410, 0x1e, 0, 0},{0x8411, 0x12, 0, 0},{0x8412, 0x01, 0, 0},
++ {0x8413, 0xbf, 0, 0},{0x8414, 0xe5, 0, 0},{0x8415, 0x4c, 0, 0},
++ {0x8416, 0xb5, 0, 0},{0x8417, 0x07, 0, 0},{0x8418, 0x07, 0, 0},
++ {0x8419, 0xe4, 0, 0},{0x841a, 0xb5, 0, 0},{0x841b, 0x06, 0, 0},
++ {0x841c, 0x03, 0, 0},{0x841d, 0xd3, 0, 0},{0x841e, 0x80, 0, 0},
++ {0x841f, 0x02, 0, 0},{0x8420, 0xa2, 0, 0},{0x8421, 0x1d, 0, 0},
++ {0x8422, 0x92, 0, 0},{0x8423, 0x1d, 0, 0},{0x8424, 0xe5, 0, 0},
++ {0x8425, 0x4b, 0, 0},{0x8426, 0xb5, 0, 0},{0x8427, 0x07, 0, 0},
++ {0x8428, 0x07, 0, 0},{0x8429, 0xe4, 0, 0},{0x842a, 0xb5, 0, 0},
++ {0x842b, 0x06, 0, 0},{0x842c, 0x03, 0, 0},{0x842d, 0xd3, 0, 0},
++ {0x842e, 0x80, 0, 0},{0x842f, 0x02, 0, 0},{0x8430, 0xa2, 0, 0},
++ {0x8431, 0x1c, 0, 0},{0x8432, 0x92, 0, 0},{0x8433, 0x1c, 0, 0},
++ {0x8434, 0x12, 0, 0},{0x8435, 0x01, 0, 0},{0x8436, 0xbf, 0, 0},
++ {0x8437, 0xe5, 0, 0},{0x8438, 0x4a, 0, 0},{0x8439, 0xb5, 0, 0},
++ {0x843a, 0x07, 0, 0},{0x843b, 0x07, 0, 0},{0x843c, 0xe4, 0, 0},
++ {0x843d, 0xb5, 0, 0},{0x843e, 0x06, 0, 0},{0x843f, 0x03, 0, 0},
++ {0x8440, 0xd3, 0, 0},{0x8441, 0x80, 0, 0},{0x8442, 0x02, 0, 0},
++ {0x8443, 0xa2, 0, 0},{0x8444, 0x1b, 0, 0},{0x8445, 0x92, 0, 0},
++ {0x8446, 0x1b, 0, 0},{0x8447, 0xe5, 0, 0},{0x8448, 0x4e, 0, 0},
++ {0x8449, 0x12, 0, 0},{0x844a, 0x01, 0, 0},{0x844b, 0xc1, 0, 0},
++ {0x844c, 0xad, 0, 0},{0x844d, 0x0b, 0, 0},{0x844e, 0x7c, 0, 0},
++ {0x844f, 0x00, 0, 0},{0x8450, 0xef, 0, 0},{0x8451, 0xb5, 0, 0},
++ {0x8452, 0x05, 0, 0},{0x8453, 0x07, 0, 0},{0x8454, 0xec, 0, 0},
++ {0x8455, 0xb5, 0, 0},{0x8456, 0x06, 0, 0},{0x8457, 0x03, 0, 0},
++ {0x8458, 0xd3, 0, 0},{0x8459, 0x80, 0, 0},{0x845a, 0x02, 0, 0},
++ {0x845b, 0xa2, 0, 0},{0x845c, 0x1f, 0, 0},{0x845d, 0x92, 0, 0},
++ {0x845e, 0x1f, 0, 0},{0x845f, 0xe5, 0, 0},{0x8460, 0x4d, 0, 0},
++ {0x8461, 0x12, 0, 0},{0x8462, 0x01, 0, 0},{0x8463, 0xc1, 0, 0},
++ {0x8464, 0xef, 0, 0},{0x8465, 0xb5, 0, 0},{0x8466, 0x05, 0, 0},
++ {0x8467, 0x07, 0, 0},{0x8468, 0xee, 0, 0},{0x8469, 0xb5, 0, 0},
++ {0x846a, 0x04, 0, 0},{0x846b, 0x03, 0, 0},{0x846c, 0xd3, 0, 0},
++ {0x846d, 0x80, 0, 0},{0x846e, 0x02, 0, 0},{0x846f, 0xa2, 0, 0},
++ {0x8470, 0x1e, 0, 0},{0x8471, 0x92, 0, 0},{0x8472, 0x1e, 0, 0},
++ {0x8473, 0xe5, 0, 0},{0x8474, 0x4c, 0, 0},{0x8475, 0x12, 0, 0},
++ {0x8476, 0x01, 0, 0},{0x8477, 0xc1, 0, 0},{0x8478, 0xad, 0, 0},
++ {0x8479, 0x0b, 0, 0},{0x847a, 0x7c, 0, 0},{0x847b, 0x00, 0, 0},
++ {0x847c, 0xef, 0, 0},{0x847d, 0xb5, 0, 0},{0x847e, 0x05, 0, 0},
++ {0x847f, 0x07, 0, 0},{0x8480, 0xec, 0, 0},{0x8481, 0xb5, 0, 0},
++ {0x8482, 0x06, 0, 0},{0x8483, 0x03, 0, 0},{0x8484, 0xd3, 0, 0},
++ {0x8485, 0x80, 0, 0},{0x8486, 0x02, 0, 0},{0x8487, 0xa2, 0, 0},
++ {0x8488, 0x1d, 0, 0},{0x8489, 0x92, 0, 0},{0x848a, 0x1d, 0, 0},
++ {0x848b, 0xe5, 0, 0},{0x848c, 0x4b, 0, 0},{0x848d, 0x12, 0, 0},
++ {0x848e, 0x01, 0, 0},{0x848f, 0xc1, 0, 0},{0x8490, 0xef, 0, 0},
++ {0x8491, 0xb5, 0, 0},{0x8492, 0x05, 0, 0},{0x8493, 0x07, 0, 0},
++ {0x8494, 0xee, 0, 0},{0x8495, 0xb5, 0, 0},{0x8496, 0x04, 0, 0},
++ {0x8497, 0x03, 0, 0},{0x8498, 0xd3, 0, 0},{0x8499, 0x80, 0, 0},
++ {0x849a, 0x02, 0, 0},{0x849b, 0xa2, 0, 0},{0x849c, 0x1c, 0, 0},
++ {0x849d, 0x92, 0, 0},{0x849e, 0x1c, 0, 0},{0x849f, 0xe5, 0, 0},
++ {0x84a0, 0x4a, 0, 0},{0x84a1, 0x12, 0, 0},{0x84a2, 0x01, 0, 0},
++ {0x84a3, 0xc1, 0, 0},{0x84a4, 0x7c, 0, 0},{0x84a5, 0x00, 0, 0},
++ {0x84a6, 0xef, 0, 0},{0x84a7, 0xb5, 0, 0},{0x84a8, 0x0b, 0, 0},
++ {0x84a9, 0x07, 0, 0},{0x84aa, 0xec, 0, 0},{0x84ab, 0xb5, 0, 0},
++ {0x84ac, 0x06, 0, 0},{0x84ad, 0x03, 0, 0},{0x84ae, 0xd3, 0, 0},
++ {0x84af, 0x80, 0, 0},{0x84b0, 0x02, 0, 0},{0x84b1, 0xa2, 0, 0},
++ {0x84b2, 0x1b, 0, 0},{0x84b3, 0x92, 0, 0},{0x84b4, 0x1b, 0, 0},
++ {0x84b5, 0xe5, 0, 0},{0x84b6, 0x30, 0, 0},{0x84b7, 0xd3, 0, 0},
++ {0x84b8, 0x94, 0, 0},{0x84b9, 0x00, 0, 0},{0x84ba, 0x40, 0, 0},
++ {0x84bb, 0x04, 0, 0},{0x84bc, 0xa2, 0, 0},{0x84bd, 0x1f, 0, 0},
++ {0x84be, 0x80, 0, 0},{0x84bf, 0x01, 0, 0},{0x84c0, 0xc3, 0, 0},
++ {0x84c1, 0x92, 0, 0},{0x84c2, 0x1f, 0, 0},{0x84c3, 0xe5, 0, 0},
++ {0x84c4, 0x2f, 0, 0},{0x84c5, 0xd3, 0, 0},{0x84c6, 0x94, 0, 0},
++ {0x84c7, 0x00, 0, 0},{0x84c8, 0x40, 0, 0},{0x84c9, 0x04, 0, 0},
++ {0x84ca, 0xa2, 0, 0},{0x84cb, 0x1e, 0, 0},{0x84cc, 0x80, 0, 0},
++ {0x84cd, 0x01, 0, 0},{0x84ce, 0xc3, 0, 0},{0x84cf, 0x92, 0, 0},
++ {0x84d0, 0x1e, 0, 0},{0x84d1, 0xe5, 0, 0},{0x84d2, 0x2e, 0, 0},
++ {0x84d3, 0xd3, 0, 0},{0x84d4, 0x94, 0, 0},{0x84d5, 0x00, 0, 0},
++ {0x84d6, 0x40, 0, 0},{0x84d7, 0x04, 0, 0},{0x84d8, 0xa2, 0, 0},
++ {0x84d9, 0x1d, 0, 0},{0x84da, 0x80, 0, 0},{0x84db, 0x01, 0, 0},
++ {0x84dc, 0xc3, 0, 0},{0x84dd, 0x92, 0, 0},{0x84de, 0x1d, 0, 0},
++ {0x84df, 0xe5, 0, 0},{0x84e0, 0x2d, 0, 0},{0x84e1, 0xd3, 0, 0},
++ {0x84e2, 0x94, 0, 0},{0x84e3, 0x00, 0, 0},{0x84e4, 0x40, 0, 0},
++ {0x84e5, 0x04, 0, 0},{0x84e6, 0xa2, 0, 0},{0x84e7, 0x1c, 0, 0},
++ {0x84e8, 0x80, 0, 0},{0x84e9, 0x01, 0, 0},{0x84ea, 0xc3, 0, 0},
++ {0x84eb, 0x92, 0, 0},{0x84ec, 0x1c, 0, 0},{0x84ed, 0xe5, 0, 0},
++ {0x84ee, 0x2c, 0, 0},{0x84ef, 0xd3, 0, 0},{0x84f0, 0x94, 0, 0},
++ {0x84f1, 0x00, 0, 0},{0x84f2, 0x40, 0, 0},{0x84f3, 0x04, 0, 0},
++ {0x84f4, 0xa2, 0, 0},{0x84f5, 0x1b, 0, 0},{0x84f6, 0x80, 0, 0},
++ {0x84f7, 0x01, 0, 0},{0x84f8, 0xc3, 0, 0},{0x84f9, 0x92, 0, 0},
++ {0x84fa, 0x1b, 0, 0},{0x84fb, 0x85, 0, 0},{0x84fc, 0x0a, 0, 0},
++ {0x84fd, 0x78, 0, 0},{0x84fe, 0xe5, 0, 0},{0x84ff, 0x7c, 0, 0},
++ {0x8500, 0xb5, 0, 0},{0x8501, 0x0b, 0, 0},{0x8502, 0x03, 0, 0},
++ {0x8503, 0x02, 0, 0},{0x8504, 0x15, 0, 0},{0x8505, 0x18, 0, 0},
++ {0x8506, 0x85, 0, 0},{0x8507, 0x0b, 0, 0},{0x8508, 0x0c, 0, 0},
++ {0x8509, 0x12, 0, 0},{0x850a, 0x0f, 0, 0},{0x850b, 0x11, 0, 0},
++ {0x850c, 0xd2, 0, 0},{0x850d, 0x02, 0, 0},{0x850e, 0xc2, 0, 0},
++ {0x850f, 0x01, 0, 0},{0x8510, 0xd2, 0, 0},{0x8511, 0x00, 0, 0},
++ {0x8512, 0x75, 0, 0},{0x8513, 0x31, 0, 0},{0x8514, 0x03, 0, 0},
++ {0x8515, 0x22, 0, 0},{0x8516, 0xe5, 0, 0},{0x8517, 0x7d, 0, 0},
++ {0x8518, 0x24, 0, 0},{0x8519, 0xfe, 0, 0},{0x851a, 0x60, 0, 0},
++ {0x851b, 0x27, 0, 0},{0x851c, 0x14, 0, 0},{0x851d, 0x60, 0, 0},
++ {0x851e, 0x31, 0, 0},{0x851f, 0x24, 0, 0},{0x8520, 0xf8, 0, 0},
++ {0x8521, 0x60, 0, 0},{0x8522, 0x3a, 0, 0},{0x8523, 0x14, 0, 0},
++ {0x8524, 0x60, 0, 0},{0x8525, 0x4b, 0, 0},{0x8526, 0x14, 0, 0},
++ {0x8527, 0x60, 0, 0},{0x8528, 0x59, 0, 0},{0x8529, 0x14, 0, 0},
++ {0x852a, 0x60, 0, 0},{0x852b, 0x6a, 0, 0},{0x852c, 0x24, 0, 0},
++ {0x852d, 0xfd, 0, 0},{0x852e, 0x70, 0, 0},{0x852f, 0x03, 0, 0},
++ {0x8530, 0x02, 0, 0},{0x8531, 0x05, 0, 0},{0x8532, 0xcb, 0, 0},
++ {0x8533, 0x24, 0, 0},{0x8534, 0x10, 0, 0},{0x8535, 0x60, 0, 0},
++ {0x8536, 0x03, 0, 0},{0x8537, 0x02, 0, 0},{0x8538, 0x06, 0, 0},
++ {0x8539, 0xc6, 0, 0},{0x853a, 0xe4, 0, 0},{0x853b, 0xf5, 0, 0},
++ {0x853c, 0x0a, 0, 0},{0x853d, 0x12, 0, 0},{0x853e, 0x10, 0, 0},
++ {0x853f, 0xb5, 0, 0},{0x8540, 0x02, 0, 0},{0x8541, 0x06, 0, 0},
++ {0x8542, 0xaf, 0, 0},{0x8543, 0x75, 0, 0},{0x8544, 0x0a, 0, 0},
++ {0x8545, 0x01, 0, 0},{0x8546, 0x12, 0, 0},{0x8547, 0x06, 0, 0},
++ {0x8548, 0xc7, 0, 0},{0x8549, 0xc2, 0, 0},{0x854a, 0x3a, 0, 0},
++ {0x854b, 0xd2, 0, 0},{0x854c, 0x39, 0, 0},{0x854d, 0x02, 0, 0},
++ {0x854e, 0x06, 0, 0},{0x854f, 0xc0, 0, 0},{0x8550, 0x75, 0, 0},
++ {0x8551, 0x0a, 0, 0},{0x8552, 0x02, 0, 0},{0x8553, 0x12, 0, 0},
++ {0x8554, 0x06, 0, 0},{0x8555, 0xc7, 0, 0},{0x8556, 0xd2, 0, 0},
++ {0x8557, 0x3a, 0, 0},{0x8558, 0xc2, 0, 0},{0x8559, 0x39, 0, 0},
++ {0x855a, 0x02, 0, 0},{0x855b, 0x06, 0, 0},{0x855c, 0xc0, 0, 0},
++ {0x855d, 0x30, 0, 0},{0x855e, 0x36, 0, 0},{0x855f, 0x0c, 0, 0},
++ {0x8560, 0x20, 0, 0},{0x8561, 0x3a, 0, 0},{0x8562, 0x03, 0, 0},
++ {0x8563, 0x30, 0, 0},{0x8564, 0x39, 0, 0},{0x8565, 0x06, 0, 0},
++ {0x8566, 0xe4, 0, 0},{0x8567, 0xf5, 0, 0},{0x8568, 0x0a, 0, 0},
++ {0x8569, 0x12, 0, 0},{0x856a, 0x12, 0, 0},{0x856b, 0x92, 0, 0},
++ {0x856c, 0xd2, 0, 0},{0x856d, 0x18, 0, 0},{0x856e, 0xc2, 0, 0},
++ {0x856f, 0x19, 0, 0},{0x8570, 0x22, 0, 0},{0x8571, 0x30, 0, 0},
++ {0x8572, 0x36, 0, 0},{0x8573, 0x09, 0, 0},{0x8574, 0x20, 0, 0},
++ {0x8575, 0x3a, 0, 0},{0x8576, 0x03, 0, 0},{0x8577, 0x30, 0, 0},
++ {0x8578, 0x39, 0, 0},{0x8579, 0x03, 0, 0},{0x857a, 0x12, 0, 0},
++ {0x857b, 0x06, 0, 0},{0x857c, 0xd8, 0, 0},{0x857d, 0xd2, 0, 0},
++ {0x857e, 0x18, 0, 0},{0x857f, 0xd2, 0, 0},{0x8580, 0x19, 0, 0},
++ {0x8581, 0x22, 0, 0},{0x8582, 0x30, 0, 0},{0x8583, 0x36, 0, 0},
++ {0x8584, 0x0c, 0, 0},{0x8585, 0x20, 0, 0},{0x8586, 0x3a, 0, 0},
++ {0x8587, 0x03, 0, 0},{0x8588, 0x30, 0, 0},{0x8589, 0x39, 0, 0},
++ {0x858a, 0x06, 0, 0},{0x858b, 0x75, 0, 0},{0x858c, 0x0a, 0, 0},
++ {0x858d, 0x02, 0, 0},{0x858e, 0x12, 0, 0},{0x858f, 0x12, 0, 0},
++ {0x8590, 0x92, 0, 0},{0x8591, 0xc2, 0, 0},{0x8592, 0x18, 0, 0},
++ {0x8593, 0xd2, 0, 0},{0x8594, 0x19, 0, 0},{0x8595, 0x22, 0, 0},
++ {0x8596, 0x20, 0, 0},{0x8597, 0x3a, 0, 0},{0x8598, 0x06, 0, 0},
++ {0x8599, 0x20, 0, 0},{0x859a, 0x39, 0, 0},{0x859b, 0x03, 0, 0},
++ {0x859c, 0x02, 0, 0},{0x859d, 0x06, 0, 0},{0x859e, 0xc6, 0, 0},
++ {0x859f, 0xe5, 0, 0},{0x85a0, 0x78, 0, 0},{0x85a1, 0xd3, 0, 0},
++ {0x85a2, 0x94, 0, 0},{0x85a3, 0x03, 0, 0},{0x85a4, 0x40, 0, 0},
++ {0x85a5, 0x04, 0, 0},{0x85a6, 0x7f, 0, 0},{0x85a7, 0x00, 0, 0},
++ {0x85a8, 0x80, 0, 0},{0x85a9, 0x04, 0, 0},{0x85aa, 0xe5, 0, 0},
++ {0x85ab, 0x78, 0, 0},{0x85ac, 0x04, 0, 0},{0x85ad, 0xff, 0, 0},
++ {0x85ae, 0x8f, 0, 0},{0x85af, 0x78, 0, 0},{0x85b0, 0x30, 0, 0},
++ {0x85b1, 0x18, 0, 0},{0x85b2, 0x06, 0, 0},{0x85b3, 0x30, 0, 0},
++ {0x85b4, 0x19, 0, 0},{0x85b5, 0x03, 0, 0},{0x85b6, 0x12, 0, 0},
++ {0x85b7, 0x06, 0, 0},{0x85b8, 0xd8, 0, 0},{0x85b9, 0x30, 0, 0},
++ {0x85ba, 0x18, 0, 0},{0x85bb, 0x03, 0, 0},{0x85bc, 0x02, 0, 0},
++ {0x85bd, 0x06, 0, 0},{0x85be, 0xc6, 0, 0},{0x85bf, 0x20, 0, 0},
++ {0x85c0, 0x19, 0, 0},{0x85c1, 0x03, 0, 0},{0x85c2, 0x02, 0, 0},
++ {0x85c3, 0x06, 0, 0},{0x85c4, 0xc6, 0, 0},{0x85c5, 0x75, 0, 0},
++ {0x85c6, 0x0a, 0, 0},{0x85c7, 0x02, 0, 0},{0x85c8, 0x02, 0, 0},
++ {0x85c9, 0x12, 0, 0},{0x85ca, 0x92, 0, 0},{0x85cb, 0xe5, 0, 0},
++ {0x85cc, 0x67, 0, 0},{0x85cd, 0xd3, 0, 0},{0x85ce, 0x94, 0, 0},
++ {0x85cf, 0x38, 0, 0},{0x85d0, 0x40, 0, 0},{0x85d1, 0x04, 0, 0},
++ {0x85d2, 0x7f, 0, 0},{0x85d3, 0x34, 0, 0},{0x85d4, 0x80, 0, 0},
++ {0x85d5, 0x02, 0, 0},{0x85d6, 0xaf, 0, 0},{0x85d7, 0x67, 0, 0},
++ {0x85d8, 0x8f, 0, 0},{0x85d9, 0x67, 0, 0},{0x85da, 0xe5, 0, 0},
++ {0x85db, 0x67, 0, 0},{0x85dc, 0xc3, 0, 0},{0x85dd, 0x94, 0, 0},
++ {0x85de, 0x08, 0, 0},{0x85df, 0x50, 0, 0},{0x85e0, 0x04, 0, 0},
++ {0x85e1, 0x7f, 0, 0},{0x85e2, 0x08, 0, 0},{0x85e3, 0x80, 0, 0},
++ {0x85e4, 0x02, 0, 0},{0x85e5, 0xaf, 0, 0},{0x85e6, 0x67, 0, 0},
++ {0x85e7, 0x8f, 0, 0},{0x85e8, 0x67, 0, 0},{0x85e9, 0xe5, 0, 0},
++ {0x85ea, 0x68, 0, 0},{0x85eb, 0xd3, 0, 0},{0x85ec, 0x94, 0, 0},
++ {0x85ed, 0x2a, 0, 0},{0x85ee, 0x40, 0, 0},{0x85ef, 0x04, 0, 0},
++ {0x85f0, 0x7f, 0, 0},{0x85f1, 0x2a, 0, 0},{0x85f2, 0x80, 0, 0},
++ {0x85f3, 0x02, 0, 0},{0x85f4, 0xaf, 0, 0},{0x85f5, 0x68, 0, 0},
++ {0x85f6, 0x8f, 0, 0},{0x85f7, 0x68, 0, 0},{0x85f8, 0xe5, 0, 0},
++ {0x85f9, 0x68, 0, 0},{0x85fa, 0xc3, 0, 0},{0x85fb, 0x94, 0, 0},
++ {0x85fc, 0x06, 0, 0},{0x85fd, 0x50, 0, 0},{0x85fe, 0x04, 0, 0},
++ {0x85ff, 0x7f, 0, 0},{0x8600, 0x06, 0, 0},{0x8601, 0x80, 0, 0},
++ {0x8602, 0x02, 0, 0},{0x8603, 0xaf, 0, 0},{0x8604, 0x68, 0, 0},
++ {0x8605, 0x8f, 0, 0},{0x8606, 0x68, 0, 0},{0x8607, 0xaf, 0, 0},
++ {0x8608, 0x67, 0, 0},{0x8609, 0xef, 0, 0},{0x860a, 0x24, 0, 0},
++ {0x860b, 0xf8, 0, 0},{0x860c, 0xff, 0, 0},{0x860d, 0xe4, 0, 0},
++ {0x860e, 0x34, 0, 0},{0x860f, 0xff, 0, 0},{0x8610, 0xfe, 0, 0},
++ {0x8611, 0xe4, 0, 0},{0x8612, 0x8f, 0, 0},{0x8613, 0x3f, 0, 0},
++ {0x8614, 0x8e, 0, 0},{0x8615, 0x3e, 0, 0},{0x8616, 0xf5, 0, 0},
++ {0x8617, 0x3d, 0, 0},{0x8618, 0xf5, 0, 0},{0x8619, 0x3c, 0, 0},
++ {0x861a, 0xac, 0, 0},{0x861b, 0x3c, 0, 0},{0x861c, 0x12, 0, 0},
++ {0x861d, 0x01, 0, 0},{0x861e, 0x90, 0, 0},{0x861f, 0xaf, 0, 0},
++ {0x8620, 0x68, 0, 0},{0x8621, 0xef, 0, 0},{0x8622, 0x24, 0, 0},
++ {0x8623, 0xfa, 0, 0},{0x8624, 0xff, 0, 0},{0x8625, 0xe4, 0, 0},
++ {0x8626, 0x34, 0, 0},{0x8627, 0xff, 0, 0},{0x8628, 0x12, 0, 0},
++ {0x8629, 0x01, 0, 0},{0x862a, 0x73, 0, 0},{0x862b, 0xaf, 0, 0},
++ {0x862c, 0x67, 0, 0},{0x862d, 0xef, 0, 0},{0x862e, 0x24, 0, 0},
++ {0x862f, 0x08, 0, 0},{0x8630, 0xff, 0, 0},{0x8631, 0xe4, 0, 0},
++ {0x8632, 0x33, 0, 0},{0x8633, 0x12, 0, 0},{0x8634, 0x01, 0, 0},
++ {0x8635, 0x73, 0, 0},{0x8636, 0xaf, 0, 0},{0x8637, 0x68, 0, 0},
++ {0x8638, 0xef, 0, 0},{0x8639, 0x24, 0, 0},{0x863a, 0x06, 0, 0},
++ {0x863b, 0xff, 0, 0},{0x863c, 0xe4, 0, 0},{0x863d, 0x33, 0, 0},
++ {0x863e, 0xfe, 0, 0},{0x863f, 0xe4, 0, 0},{0x8640, 0xfc, 0, 0},
++ {0x8641, 0xfd, 0, 0},{0x8642, 0xe5, 0, 0},{0x8643, 0x3f, 0, 0},
++ {0x8644, 0x2f, 0, 0},{0x8645, 0xf5, 0, 0},{0x8646, 0x3f, 0, 0},
++ {0x8647, 0xe5, 0, 0},{0x8648, 0x3e, 0, 0},{0x8649, 0x3e, 0, 0},
++ {0x864a, 0xf5, 0, 0},{0x864b, 0x3e, 0, 0},{0x864c, 0xed, 0, 0},
++ {0x864d, 0x35, 0, 0},{0x864e, 0x3d, 0, 0},{0x864f, 0xf5, 0, 0},
++ {0x8650, 0x3d, 0, 0},{0x8651, 0xec, 0, 0},{0x8652, 0x35, 0, 0},
++ {0x8653, 0x3c, 0, 0},{0x8654, 0xf5, 0, 0},{0x8655, 0x3c, 0, 0},
++ {0x8656, 0xe4, 0, 0},{0x8657, 0x25, 0, 0},{0x8658, 0x3f, 0, 0},
++ {0x8659, 0xf5, 0, 0},{0x865a, 0x37, 0, 0},{0x865b, 0xe4, 0, 0},
++ {0x865c, 0x35, 0, 0},{0x865d, 0x3e, 0, 0},{0x865e, 0xf5, 0, 0},
++ {0x865f, 0x36, 0, 0},{0x8660, 0xe4, 0, 0},{0x8661, 0x35, 0, 0},
++ {0x8662, 0x3d, 0, 0},{0x8663, 0xf5, 0, 0},{0x8664, 0x35, 0, 0},
++ {0x8665, 0xe5, 0, 0},{0x8666, 0x3c, 0, 0},{0x8667, 0x34, 0, 0},
++ {0x8668, 0x08, 0, 0},{0x8669, 0xf5, 0, 0},{0x866a, 0x34, 0, 0},
++ {0x866b, 0xe4, 0, 0},{0x866c, 0x25, 0, 0},{0x866d, 0x3f, 0, 0},
++ {0x866e, 0xf5, 0, 0},{0x866f, 0x3b, 0, 0},{0x8670, 0xe4, 0, 0},
++ {0x8671, 0x35, 0, 0},{0x8672, 0x3e, 0, 0},{0x8673, 0xf5, 0, 0},
++ {0x8674, 0x3a, 0, 0},{0x8675, 0xe5, 0, 0},{0x8676, 0x3d, 0, 0},
++ {0x8677, 0x34, 0, 0},{0x8678, 0x06, 0, 0},{0x8679, 0xf5, 0, 0},
++ {0x867a, 0x39, 0, 0},{0x867b, 0xe4, 0, 0},{0x867c, 0x35, 0, 0},
++ {0x867d, 0x3c, 0, 0},{0x867e, 0xf5, 0, 0},{0x867f, 0x38, 0, 0},
++ {0x8680, 0xe5, 0, 0},{0x8681, 0x3f, 0, 0},{0x8682, 0x24, 0, 0},
++ {0x8683, 0xfa, 0, 0},{0x8684, 0xf5, 0, 0},{0x8685, 0x43, 0, 0},
++ {0x8686, 0xe5, 0, 0},{0x8687, 0x3e, 0, 0},{0x8688, 0x34, 0, 0},
++ {0x8689, 0xff, 0, 0},{0x868a, 0xf5, 0, 0},{0x868b, 0x42, 0, 0},
++ {0x868c, 0xe5, 0, 0},{0x868d, 0x3d, 0, 0},{0x868e, 0x34, 0, 0},
++ {0x868f, 0xff, 0, 0},{0x8690, 0xf5, 0, 0},{0x8691, 0x41, 0, 0},
++ {0x8692, 0xe5, 0, 0},{0x8693, 0x3c, 0, 0},{0x8694, 0x34, 0, 0},
++ {0x8695, 0xff, 0, 0},{0x8696, 0xf5, 0, 0},{0x8697, 0x40, 0, 0},
++ {0x8698, 0xe4, 0, 0},{0x8699, 0x25, 0, 0},{0x869a, 0x3f, 0, 0},
++ {0x869b, 0xf5, 0, 0},{0x869c, 0x47, 0, 0},{0x869d, 0xe5, 0, 0},
++ {0x869e, 0x3e, 0, 0},{0x869f, 0x34, 0, 0},{0x86a0, 0xf8, 0, 0},
++ {0x86a1, 0xf5, 0, 0},{0x86a2, 0x46, 0, 0},{0x86a3, 0xe5, 0, 0},
++ {0x86a4, 0x3d, 0, 0},{0x86a5, 0x34, 0, 0},{0x86a6, 0xff, 0, 0},
++ {0x86a7, 0xf5, 0, 0},{0x86a8, 0x45, 0, 0},{0x86a9, 0xe5, 0, 0},
++ {0x86aa, 0x3c, 0, 0},{0x86ab, 0x34, 0, 0},{0x86ac, 0xff, 0, 0},
++ {0x86ad, 0xf5, 0, 0},{0x86ae, 0x44, 0, 0},{0x86af, 0x75, 0, 0},
++ {0x86b0, 0x78, 0, 0},{0x86b1, 0x02, 0, 0},{0x86b2, 0x75, 0, 0},
++ {0x86b3, 0x0a, 0, 0},{0x86b4, 0x01, 0, 0},{0x86b5, 0x12, 0, 0},
++ {0x86b6, 0x12, 0, 0},{0x86b7, 0x92, 0, 0},{0x86b8, 0xd2, 0, 0},
++ {0x86b9, 0x18, 0, 0},{0x86ba, 0xd2, 0, 0},{0x86bb, 0x19, 0, 0},
++ {0x86bc, 0xc2, 0, 0},{0x86bd, 0x3a, 0, 0},{0x86be, 0xc2, 0, 0},
++ {0x86bf, 0x39, 0, 0},{0x86c0, 0xd2, 0, 0},{0x86c1, 0x1a, 0, 0},
++ {0x86c2, 0xd2, 0, 0},{0x86c3, 0x36, 0, 0},{0x86c4, 0xd2, 0, 0},
++ {0x86c5, 0x30, 0, 0},{0x86c6, 0x22, 0, 0},{0x86c7, 0x12, 0, 0},
++ {0x86c8, 0x10, 0, 0},{0x86c9, 0xb5, 0, 0},{0x86ca, 0x75, 0, 0},
++ {0x86cb, 0x78, 0, 0},{0x86cc, 0x02, 0, 0},{0x86cd, 0xe4, 0, 0},
++ {0x86ce, 0xf5, 0, 0},{0x86cf, 0x0a, 0, 0},{0x86d0, 0x12, 0, 0},
++ {0x86d1, 0x12, 0, 0},{0x86d2, 0x92, 0, 0},{0x86d3, 0xd2, 0, 0},
++ {0x86d4, 0x18, 0, 0},{0x86d5, 0xc2, 0, 0},{0x86d6, 0x19, 0, 0},
++ {0x86d7, 0x22, 0, 0},{0x86d8, 0x75, 0, 0},{0x86d9, 0x0a, 0, 0},
++ {0x86da, 0x01, 0, 0},{0x86db, 0x12, 0, 0},{0x86dc, 0x12, 0, 0},
++ {0x86dd, 0x92, 0, 0},{0x86de, 0x22, 0, 0},{0x86df, 0x90, 0, 0},
++ {0x86e0, 0x38, 0, 0},{0x86e1, 0x04, 0, 0},{0x86e2, 0xe0, 0, 0},
++ {0x86e3, 0xfe, 0, 0},{0x86e4, 0xa3, 0, 0},{0x86e5, 0xe0, 0, 0},
++ {0x86e6, 0xfd, 0, 0},{0x86e7, 0xed, 0, 0},{0x86e8, 0xff, 0, 0},
++ {0x86e9, 0xee, 0, 0},{0x86ea, 0x54, 0, 0},{0x86eb, 0x0f, 0, 0},
++ {0x86ec, 0xf5, 0, 0},{0x86ed, 0x0e, 0, 0},{0x86ee, 0x8f, 0, 0},
++ {0x86ef, 0x0f, 0, 0},{0x86f0, 0xa3, 0, 0},{0x86f1, 0xe0, 0, 0},
++ {0x86f2, 0xfe, 0, 0},{0x86f3, 0xa3, 0, 0},{0x86f4, 0xe0, 0, 0},
++ {0x86f5, 0xfd, 0, 0},{0x86f6, 0xed, 0, 0},{0x86f7, 0xff, 0, 0},
++ {0x86f8, 0xee, 0, 0},{0x86f9, 0x54, 0, 0},{0x86fa, 0x07, 0, 0},
++ {0x86fb, 0xf5, 0, 0},{0x86fc, 0x10, 0, 0},{0x86fd, 0x8f, 0, 0},
++ {0x86fe, 0x11, 0, 0},{0x86ff, 0xe5, 0, 0},{0x8700, 0x0e, 0, 0},
++ {0x8701, 0xc4, 0, 0},{0x8702, 0xf8, 0, 0},{0x8703, 0x54, 0, 0},
++ {0x8704, 0xf0, 0, 0},{0x8705, 0xc8, 0, 0},{0x8706, 0x68, 0, 0},
++ {0x8707, 0xf5, 0, 0},{0x8708, 0x0e, 0, 0},{0x8709, 0xe5, 0, 0},
++ {0x870a, 0x0f, 0, 0},{0x870b, 0xc4, 0, 0},{0x870c, 0x54, 0, 0},
++ {0x870d, 0x0f, 0, 0},{0x870e, 0x48, 0, 0},{0x870f, 0xf5, 0, 0},
++ {0x8710, 0x0f, 0, 0},{0x8711, 0xe5, 0, 0},{0x8712, 0x10, 0, 0},
++ {0x8713, 0xc4, 0, 0},{0x8714, 0xf8, 0, 0},{0x8715, 0x54, 0, 0},
++ {0x8716, 0xf0, 0, 0},{0x8717, 0xc8, 0, 0},{0x8718, 0x68, 0, 0},
++ {0x8719, 0xf5, 0, 0},{0x871a, 0x10, 0, 0},{0x871b, 0xe5, 0, 0},
++ {0x871c, 0x11, 0, 0},{0x871d, 0xc4, 0, 0},{0x871e, 0x54, 0, 0},
++ {0x871f, 0x0f, 0, 0},{0x8720, 0x48, 0, 0},{0x8721, 0xf5, 0, 0},
++ {0x8722, 0x11, 0, 0},{0x8723, 0xe4, 0, 0},{0x8724, 0xf5, 0, 0},
++ {0x8725, 0x17, 0, 0},{0x8726, 0x75, 0, 0},{0x8727, 0x16, 0, 0},
++ {0x8728, 0x04, 0, 0},{0x8729, 0x12, 0, 0},{0x872a, 0x02, 0, 0},
++ {0x872b, 0x66, 0, 0},{0x872c, 0x24, 0, 0},{0x872d, 0x34, 0, 0},
++ {0x872e, 0xf8, 0, 0},{0x872f, 0xe6, 0, 0},{0x8730, 0xf5, 0, 0},
++ {0x8731, 0x12, 0, 0},{0x8732, 0x12, 0, 0},{0x8733, 0x02, 0, 0},
++ {0x8734, 0x66, 0, 0},{0x8735, 0x24, 0, 0},{0x8736, 0x35, 0, 0},
++ {0x8737, 0xf8, 0, 0},{0x8738, 0xe6, 0, 0},{0x8739, 0xf5, 0, 0},
++ {0x873a, 0x14, 0, 0},{0x873b, 0x12, 0, 0},{0x873c, 0x02, 0, 0},
++ {0x873d, 0x66, 0, 0},{0x873e, 0x24, 0, 0},{0x873f, 0x36, 0, 0},
++ {0x8740, 0xf8, 0, 0},{0x8741, 0xe6, 0, 0},{0x8742, 0xf5, 0, 0},
++ {0x8743, 0x13, 0, 0},{0x8744, 0x12, 0, 0},{0x8745, 0x02, 0, 0},
++ {0x8746, 0x66, 0, 0},{0x8747, 0x24, 0, 0},{0x8748, 0x37, 0, 0},
++ {0x8749, 0xf8, 0, 0},{0x874a, 0xe6, 0, 0},{0x874b, 0xf5, 0, 0},
++ {0x874c, 0x15, 0, 0},{0x874d, 0x12, 0, 0},{0x874e, 0x02, 0, 0},
++ {0x874f, 0x79, 0, 0},{0x8750, 0xaf, 0, 0},{0x8751, 0x12, 0, 0},
++ {0x8752, 0x12, 0, 0},{0x8753, 0x01, 0, 0},{0x8754, 0x42, 0, 0},
++ {0x8755, 0x8f, 0, 0},{0x8756, 0x12, 0, 0},{0x8757, 0x12, 0, 0},
++ {0x8758, 0x02, 0, 0},{0x8759, 0x79, 0, 0},{0x875a, 0xaf, 0, 0},
++ {0x875b, 0x13, 0, 0},{0x875c, 0x12, 0, 0},{0x875d, 0x01, 0, 0},
++ {0x875e, 0x42, 0, 0},{0x875f, 0x8f, 0, 0},{0x8760, 0x13, 0, 0},
++ {0x8761, 0x12, 0, 0},{0x8762, 0x02, 0, 0},{0x8763, 0x11, 0, 0},
++ {0x8764, 0xaf, 0, 0},{0x8765, 0x14, 0, 0},{0x8766, 0xfc, 0, 0},
++ {0x8767, 0xfd, 0, 0},{0x8768, 0xfe, 0, 0},{0x8769, 0x12, 0, 0},
++ {0x876a, 0x08, 0, 0},{0x876b, 0x7f, 0, 0},{0x876c, 0x12, 0, 0},
++ {0x876d, 0x01, 0, 0},{0x876e, 0x61, 0, 0},{0x876f, 0x7b, 0, 0},
++ {0x8770, 0x30, 0, 0},{0x8771, 0x12, 0, 0},{0x8772, 0x01, 0, 0},
++ {0x8773, 0x5a, 0, 0},{0x8774, 0x8f, 0, 0},{0x8775, 0x14, 0, 0},
++ {0x8776, 0x12, 0, 0},{0x8777, 0x02, 0, 0},{0x8778, 0x11, 0, 0},
++ {0x8779, 0xaf, 0, 0},{0x877a, 0x15, 0, 0},{0x877b, 0xfc, 0, 0},
++ {0x877c, 0xfd, 0, 0},{0x877d, 0xfe, 0, 0},{0x877e, 0x12, 0, 0},
++ {0x877f, 0x08, 0, 0},{0x8780, 0x7f, 0, 0},{0x8781, 0x12, 0, 0},
++ {0x8782, 0x01, 0, 0},{0x8783, 0x61, 0, 0},{0x8784, 0xe4, 0, 0},
++ {0x8785, 0x7b, 0, 0},{0x8786, 0x30, 0, 0},{0x8787, 0x12, 0, 0},
++ {0x8788, 0x01, 0, 0},{0x8789, 0x5b, 0, 0},{0x878a, 0x8f, 0, 0},
++ {0x878b, 0x15, 0, 0},{0x878c, 0xc3, 0, 0},{0x878d, 0xe5, 0, 0},
++ {0x878e, 0x13, 0, 0},{0x878f, 0x95, 0, 0},{0x8790, 0x12, 0, 0},
++ {0x8791, 0xff, 0, 0},{0x8792, 0x0f, 0, 0},{0x8793, 0xef, 0, 0},
++ {0x8794, 0xc3, 0, 0},{0x8795, 0x13, 0, 0},{0x8796, 0xff, 0, 0},
++ {0x8797, 0xc3, 0, 0},{0x8798, 0x94, 0, 0},{0x8799, 0x04, 0, 0},
++ {0x879a, 0x50, 0, 0},{0x879b, 0x27, 0, 0},{0x879c, 0xe5, 0, 0},
++ {0x879d, 0x12, 0, 0},{0x879e, 0x9f, 0, 0},{0x879f, 0x40, 0, 0},
++ {0x87a0, 0x06, 0, 0},{0x87a1, 0xe5, 0, 0},{0x87a2, 0x12, 0, 0},
++ {0x87a3, 0x9f, 0, 0},{0x87a4, 0xfe, 0, 0},{0x87a5, 0x80, 0, 0},
++ {0x87a6, 0x02, 0, 0},{0x87a7, 0x7e, 0, 0},{0x87a8, 0x00, 0, 0},
++ {0x87a9, 0x8e, 0, 0},{0x87aa, 0x12, 0, 0},{0x87ab, 0xef, 0, 0},
++ {0x87ac, 0xfd, 0, 0},{0x87ad, 0xe5, 0, 0},{0x87ae, 0x13, 0, 0},
++ {0x87af, 0x2d, 0, 0},{0x87b0, 0xfd, 0, 0},{0x87b1, 0xe4, 0, 0},
++ {0x87b2, 0x33, 0, 0},{0x87b3, 0xfc, 0, 0},{0x87b4, 0xc3, 0, 0},
++ {0x87b5, 0xed, 0, 0},{0x87b6, 0x95, 0, 0},{0x87b7, 0x0f, 0, 0},
++ {0x87b8, 0xec, 0, 0},{0x87b9, 0x95, 0, 0},{0x87ba, 0x0e, 0, 0},
++ {0x87bb, 0x50, 0, 0},{0x87bc, 0x02, 0, 0},{0x87bd, 0x80, 0, 0},
++ {0x87be, 0x02, 0, 0},{0x87bf, 0xad, 0, 0},{0x87c0, 0x0f, 0, 0},
++ {0x87c1, 0x8d, 0, 0},{0x87c2, 0x13, 0, 0},{0x87c3, 0xc3, 0, 0},
++ {0x87c4, 0xe5, 0, 0},{0x87c5, 0x15, 0, 0},{0x87c6, 0x95, 0, 0},
++ {0x87c7, 0x14, 0, 0},{0x87c8, 0xff, 0, 0},{0x87c9, 0xc3, 0, 0},
++ {0x87ca, 0x94, 0, 0},{0x87cb, 0x04, 0, 0},{0x87cc, 0x50, 0, 0},
++ {0x87cd, 0x29, 0, 0},{0x87ce, 0xe5, 0, 0},{0x87cf, 0x14, 0, 0},
++ {0x87d0, 0x9f, 0, 0},{0x87d1, 0x40, 0, 0},{0x87d2, 0x06, 0, 0},
++ {0x87d3, 0xe5, 0, 0},{0x87d4, 0x14, 0, 0},{0x87d5, 0x9f, 0, 0},
++ {0x87d6, 0xfe, 0, 0},{0x87d7, 0x80, 0, 0},{0x87d8, 0x02, 0, 0},
++ {0x87d9, 0x7e, 0, 0},{0x87da, 0x00, 0, 0},{0x87db, 0x8e, 0, 0},
++ {0x87dc, 0x14, 0, 0},{0x87dd, 0xef, 0, 0},{0x87de, 0xfd, 0, 0},
++ {0x87df, 0xe5, 0, 0},{0x87e0, 0x15, 0, 0},{0x87e1, 0x2d, 0, 0},
++ {0x87e2, 0xfd, 0, 0},{0x87e3, 0xe4, 0, 0},{0x87e4, 0x33, 0, 0},
++ {0x87e5, 0xfc, 0, 0},{0x87e6, 0xc3, 0, 0},{0x87e7, 0xed, 0, 0},
++ {0x87e8, 0x95, 0, 0},{0x87e9, 0x11, 0, 0},{0x87ea, 0xec, 0, 0},
++ {0x87eb, 0x95, 0, 0},{0x87ec, 0x10, 0, 0},{0x87ed, 0x50, 0, 0},
++ {0x87ee, 0x04, 0, 0},{0x87ef, 0xaf, 0, 0},{0x87f0, 0x05, 0, 0},
++ {0x87f1, 0x80, 0, 0},{0x87f2, 0x02, 0, 0},{0x87f3, 0xaf, 0, 0},
++ {0x87f4, 0x11, 0, 0},{0x87f5, 0x8f, 0, 0},{0x87f6, 0x15, 0, 0},
++ {0x87f7, 0xe5, 0, 0},{0x87f8, 0x15, 0, 0},{0x87f9, 0xd3, 0, 0},
++ {0x87fa, 0x95, 0, 0},{0x87fb, 0x17, 0, 0},{0x87fc, 0x40, 0, 0},
++ {0x87fd, 0x04, 0, 0},{0x87fe, 0xaf, 0, 0},{0x87ff, 0x15, 0, 0},
++ {0x8800, 0x80, 0, 0},{0x8801, 0x02, 0, 0},{0x8802, 0xaf, 0, 0},
++ {0x8803, 0x17, 0, 0},{0x8804, 0x8f, 0, 0},{0x8805, 0x17, 0, 0},
++ {0x8806, 0xd3, 0, 0},{0x8807, 0xe5, 0, 0},{0x8808, 0x16, 0, 0},
++ {0x8809, 0x64, 0, 0},{0x880a, 0x80, 0, 0},{0x880b, 0x94, 0, 0},
++ {0x880c, 0x80, 0, 0},{0x880d, 0x40, 0, 0},{0x880e, 0x04, 0, 0},
++ {0x880f, 0xaf, 0, 0},{0x8810, 0x15, 0, 0},{0x8811, 0x80, 0, 0},
++ {0x8812, 0x02, 0, 0},{0x8813, 0xaf, 0, 0},{0x8814, 0x17, 0, 0},
++ {0x8815, 0x8f, 0, 0},{0x8816, 0x15, 0, 0},{0x8817, 0xe5, 0, 0},
++ {0x8818, 0x16, 0, 0},{0x8819, 0xfd, 0, 0},{0x881a, 0x33, 0, 0},
++ {0x881b, 0x95, 0, 0},{0x881c, 0xe0, 0, 0},{0x881d, 0xfc, 0, 0},
++ {0x881e, 0xed, 0, 0},{0x881f, 0xae, 0, 0},{0x8820, 0x04, 0, 0},
++ {0x8821, 0x78, 0, 0},{0x8822, 0x02, 0, 0},{0x8823, 0xc3, 0, 0},
++ {0x8824, 0x33, 0, 0},{0x8825, 0xce, 0, 0},{0x8826, 0x33, 0, 0},
++ {0x8827, 0xce, 0, 0},{0x8828, 0xd8, 0, 0},{0x8829, 0xf9, 0, 0},
++ {0x882a, 0xff, 0, 0},{0x882b, 0x24, 0, 0},{0x882c, 0x01, 0, 0},
++ {0x882d, 0xfb, 0, 0},{0x882e, 0xee, 0, 0},{0x882f, 0x34, 0, 0},
++ {0x8830, 0x60, 0, 0},{0x8831, 0x8b, 0, 0},{0x8832, 0x82, 0, 0},
++ {0x8833, 0xf5, 0, 0},{0x8834, 0x83, 0, 0},{0x8835, 0xe5, 0, 0},
++ {0x8836, 0x12, 0, 0},{0x8837, 0xf0, 0, 0},{0x8838, 0xef, 0, 0},
++ {0x8839, 0x24, 0, 0},{0x883a, 0x02, 0, 0},{0x883b, 0xff, 0, 0},
++ {0x883c, 0xee, 0, 0},{0x883d, 0x34, 0, 0},{0x883e, 0x60, 0, 0},
++ {0x883f, 0x8f, 0, 0},{0x8840, 0x82, 0, 0},{0x8841, 0xf5, 0, 0},
++ {0x8842, 0x83, 0, 0},{0x8843, 0xe5, 0, 0},{0x8844, 0x14, 0, 0},
++ {0x8845, 0xf0, 0, 0},{0x8846, 0xed, 0, 0},{0x8847, 0xae, 0, 0},
++ {0x8848, 0x04, 0, 0},{0x8849, 0x78, 0, 0},{0x884a, 0x02, 0, 0},
++ {0x884b, 0xc3, 0, 0},{0x884c, 0x33, 0, 0},{0x884d, 0xce, 0, 0},
++ {0x884e, 0x33, 0, 0},{0x884f, 0xce, 0, 0},{0x8850, 0xd8, 0, 0},
++ {0x8851, 0xf9, 0, 0},{0x8852, 0xff, 0, 0},{0x8853, 0x24, 0, 0},
++ {0x8854, 0x03, 0, 0},{0x8855, 0xfd, 0, 0},{0x8856, 0xee, 0, 0},
++ {0x8857, 0x34, 0, 0},{0x8858, 0x60, 0, 0},{0x8859, 0x8d, 0, 0},
++ {0x885a, 0x82, 0, 0},{0x885b, 0xf5, 0, 0},{0x885c, 0x83, 0, 0},
++ {0x885d, 0xe5, 0, 0},{0x885e, 0x13, 0, 0},{0x885f, 0xf0, 0, 0},
++ {0x8860, 0xef, 0, 0},{0x8861, 0x24, 0, 0},{0x8862, 0x04, 0, 0},
++ {0x8863, 0xff, 0, 0},{0x8864, 0xee, 0, 0},{0x8865, 0x34, 0, 0},
++ {0x8866, 0x60, 0, 0},{0x8867, 0x8f, 0, 0},{0x8868, 0x82, 0, 0},
++ {0x8869, 0xf5, 0, 0},{0x886a, 0x83, 0, 0},{0x886b, 0xe5, 0, 0},
++ {0x886c, 0x15, 0, 0},{0x886d, 0xf0, 0, 0},{0x886e, 0x15, 0, 0},
++ {0x886f, 0x16, 0, 0},{0x8870, 0xc3, 0, 0},{0x8871, 0xe5, 0, 0},
++ {0x8872, 0x16, 0, 0},{0x8873, 0x64, 0, 0},{0x8874, 0x80, 0, 0},
++ {0x8875, 0x94, 0, 0},{0x8876, 0x80, 0, 0},{0x8877, 0x40, 0, 0},
++ {0x8878, 0x03, 0, 0},{0x8879, 0x02, 0, 0},{0x887a, 0x07, 0, 0},
++ {0x887b, 0x29, 0, 0},{0x887c, 0xc2, 0, 0},{0x887d, 0x30, 0, 0},
++ {0x887e, 0x22, 0, 0},{0x887f, 0xe8, 0, 0},{0x8880, 0x8f, 0, 0},
++ {0x8881, 0xf0, 0, 0},{0x8882, 0xa4, 0, 0},{0x8883, 0xcc, 0, 0},
++ {0x8884, 0x8b, 0, 0},{0x8885, 0xf0, 0, 0},{0x8886, 0xa4, 0, 0},
++ {0x8887, 0x2c, 0, 0},{0x8888, 0xfc, 0, 0},{0x8889, 0xe9, 0, 0},
++ {0x888a, 0x8e, 0, 0},{0x888b, 0xf0, 0, 0},{0x888c, 0xa4, 0, 0},
++ {0x888d, 0x2c, 0, 0},{0x888e, 0xfc, 0, 0},{0x888f, 0x8a, 0, 0},
++ {0x8890, 0xf0, 0, 0},{0x8891, 0xed, 0, 0},{0x8892, 0xa4, 0, 0},
++ {0x8893, 0x2c, 0, 0},{0x8894, 0xfc, 0, 0},{0x8895, 0xea, 0, 0},
++ {0x8896, 0x8e, 0, 0},{0x8897, 0xf0, 0, 0},{0x8898, 0xa4, 0, 0},
++ {0x8899, 0xcd, 0, 0},{0x889a, 0xa8, 0, 0},{0x889b, 0xf0, 0, 0},
++ {0x889c, 0x8b, 0, 0},{0x889d, 0xf0, 0, 0},{0x889e, 0xa4, 0, 0},
++ {0x889f, 0x2d, 0, 0},{0x88a0, 0xcc, 0, 0},{0x88a1, 0x38, 0, 0},
++ {0x88a2, 0x25, 0, 0},{0x88a3, 0xf0, 0, 0},{0x88a4, 0xfd, 0, 0},
++ {0x88a5, 0xe9, 0, 0},{0x88a6, 0x8f, 0, 0},{0x88a7, 0xf0, 0, 0},
++ {0x88a8, 0xa4, 0, 0},{0x88a9, 0x2c, 0, 0},{0x88aa, 0xcd, 0, 0},
++ {0x88ab, 0x35, 0, 0},{0x88ac, 0xf0, 0, 0},{0x88ad, 0xfc, 0, 0},
++ {0x88ae, 0xeb, 0, 0},{0x88af, 0x8e, 0, 0},{0x88b0, 0xf0, 0, 0},
++ {0x88b1, 0xa4, 0, 0},{0x88b2, 0xfe, 0, 0},{0x88b3, 0xa9, 0, 0},
++ {0x88b4, 0xf0, 0, 0},{0x88b5, 0xeb, 0, 0},{0x88b6, 0x8f, 0, 0},
++ {0x88b7, 0xf0, 0, 0},{0x88b8, 0xa4, 0, 0},{0x88b9, 0xcf, 0, 0},
++ {0x88ba, 0xc5, 0, 0},{0x88bb, 0xf0, 0, 0},{0x88bc, 0x2e, 0, 0},
++ {0x88bd, 0xcd, 0, 0},{0x88be, 0x39, 0, 0},{0x88bf, 0xfe, 0, 0},
++ {0x88c0, 0xe4, 0, 0},{0x88c1, 0x3c, 0, 0},{0x88c2, 0xfc, 0, 0},
++ {0x88c3, 0xea, 0, 0},{0x88c4, 0xa4, 0, 0},{0x88c5, 0x2d, 0, 0},
++ {0x88c6, 0xce, 0, 0},{0x88c7, 0x35, 0, 0},{0x88c8, 0xf0, 0, 0},
++ {0x88c9, 0xfd, 0, 0},{0x88ca, 0xe4, 0, 0},{0x88cb, 0x3c, 0, 0},
++ {0x88cc, 0xfc, 0, 0},{0x88cd, 0x22, 0, 0},{0x88ce, 0x75, 0, 0},
++ {0x88cf, 0xf0, 0, 0},{0x88d0, 0x08, 0, 0},{0x88d1, 0x75, 0, 0},
++ {0x88d2, 0x82, 0, 0},{0x88d3, 0x00, 0, 0},{0x88d4, 0xef, 0, 0},
++ {0x88d5, 0x2f, 0, 0},{0x88d6, 0xff, 0, 0},{0x88d7, 0xee, 0, 0},
++ {0x88d8, 0x33, 0, 0},{0x88d9, 0xfe, 0, 0},{0x88da, 0xcd, 0, 0},
++ {0x88db, 0x33, 0, 0},{0x88dc, 0xcd, 0, 0},{0x88dd, 0xcc, 0, 0},
++ {0x88de, 0x33, 0, 0},{0x88df, 0xcc, 0, 0},{0x88e0, 0xc5, 0, 0},
++ {0x88e1, 0x82, 0, 0},{0x88e2, 0x33, 0, 0},{0x88e3, 0xc5, 0, 0},
++ {0x88e4, 0x82, 0, 0},{0x88e5, 0x9b, 0, 0},{0x88e6, 0xed, 0, 0},
++ {0x88e7, 0x9a, 0, 0},{0x88e8, 0xec, 0, 0},{0x88e9, 0x99, 0, 0},
++ {0x88ea, 0xe5, 0, 0},{0x88eb, 0x82, 0, 0},{0x88ec, 0x98, 0, 0},
++ {0x88ed, 0x40, 0, 0},{0x88ee, 0x0c, 0, 0},{0x88ef, 0xf5, 0, 0},
++ {0x88f0, 0x82, 0, 0},{0x88f1, 0xee, 0, 0},{0x88f2, 0x9b, 0, 0},
++ {0x88f3, 0xfe, 0, 0},{0x88f4, 0xed, 0, 0},{0x88f5, 0x9a, 0, 0},
++ {0x88f6, 0xfd, 0, 0},{0x88f7, 0xec, 0, 0},{0x88f8, 0x99, 0, 0},
++ {0x88f9, 0xfc, 0, 0},{0x88fa, 0x0f, 0, 0},{0x88fb, 0xd5, 0, 0},
++ {0x88fc, 0xf0, 0, 0},{0x88fd, 0xd6, 0, 0},{0x88fe, 0xe4, 0, 0},
++ {0x88ff, 0xce, 0, 0},{0x8900, 0xfb, 0, 0},{0x8901, 0xe4, 0, 0},
++ {0x8902, 0xcd, 0, 0},{0x8903, 0xfa, 0, 0},{0x8904, 0xe4, 0, 0},
++ {0x8905, 0xcc, 0, 0},{0x8906, 0xf9, 0, 0},{0x8907, 0xa8, 0, 0},
++ {0x8908, 0x82, 0, 0},{0x8909, 0x22, 0, 0},{0x890a, 0xb8, 0, 0},
++ {0x890b, 0x00, 0, 0},{0x890c, 0xc1, 0, 0},{0x890d, 0xb9, 0, 0},
++ {0x890e, 0x00, 0, 0},{0x890f, 0x59, 0, 0},{0x8910, 0xba, 0, 0},
++ {0x8911, 0x00, 0, 0},{0x8912, 0x2d, 0, 0},{0x8913, 0xec, 0, 0},
++ {0x8914, 0x8b, 0, 0},{0x8915, 0xf0, 0, 0},{0x8916, 0x84, 0, 0},
++ {0x8917, 0xcf, 0, 0},{0x8918, 0xce, 0, 0},{0x8919, 0xcd, 0, 0},
++ {0x891a, 0xfc, 0, 0},{0x891b, 0xe5, 0, 0},{0x891c, 0xf0, 0, 0},
++ {0x891d, 0xcb, 0, 0},{0x891e, 0xf9, 0, 0},{0x891f, 0x78, 0, 0},
++ {0x8920, 0x18, 0, 0},{0x8921, 0xef, 0, 0},{0x8922, 0x2f, 0, 0},
++ {0x8923, 0xff, 0, 0},{0x8924, 0xee, 0, 0},{0x8925, 0x33, 0, 0},
++ {0x8926, 0xfe, 0, 0},{0x8927, 0xed, 0, 0},{0x8928, 0x33, 0, 0},
++ {0x8929, 0xfd, 0, 0},{0x892a, 0xec, 0, 0},{0x892b, 0x33, 0, 0},
++ {0x892c, 0xfc, 0, 0},{0x892d, 0xeb, 0, 0},{0x892e, 0x33, 0, 0},
++ {0x892f, 0xfb, 0, 0},{0x8930, 0x10, 0, 0},{0x8931, 0xd7, 0, 0},
++ {0x8932, 0x03, 0, 0},{0x8933, 0x99, 0, 0},{0x8934, 0x40, 0, 0},
++ {0x8935, 0x04, 0, 0},{0x8936, 0xeb, 0, 0},{0x8937, 0x99, 0, 0},
++ {0x8938, 0xfb, 0, 0},{0x8939, 0x0f, 0, 0},{0x893a, 0xd8, 0, 0},
++ {0x893b, 0xe5, 0, 0},{0x893c, 0xe4, 0, 0},{0x893d, 0xf9, 0, 0},
++ {0x893e, 0xfa, 0, 0},{0x893f, 0x22, 0, 0},{0x8940, 0x78, 0, 0},
++ {0x8941, 0x18, 0, 0},{0x8942, 0xef, 0, 0},{0x8943, 0x2f, 0, 0},
++ {0x8944, 0xff, 0, 0},{0x8945, 0xee, 0, 0},{0x8946, 0x33, 0, 0},
++ {0x8947, 0xfe, 0, 0},{0x8948, 0xed, 0, 0},{0x8949, 0x33, 0, 0},
++ {0x894a, 0xfd, 0, 0},{0x894b, 0xec, 0, 0},{0x894c, 0x33, 0, 0},
++ {0x894d, 0xfc, 0, 0},{0x894e, 0xc9, 0, 0},{0x894f, 0x33, 0, 0},
++ {0x8950, 0xc9, 0, 0},{0x8951, 0x10, 0, 0},{0x8952, 0xd7, 0, 0},
++ {0x8953, 0x05, 0, 0},{0x8954, 0x9b, 0, 0},{0x8955, 0xe9, 0, 0},
++ {0x8956, 0x9a, 0, 0},{0x8957, 0x40, 0, 0},{0x8958, 0x07, 0, 0},
++ {0x8959, 0xec, 0, 0},{0x895a, 0x9b, 0, 0},{0x895b, 0xfc, 0, 0},
++ {0x895c, 0xe9, 0, 0},{0x895d, 0x9a, 0, 0},{0x895e, 0xf9, 0, 0},
++ {0x895f, 0x0f, 0, 0},{0x8960, 0xd8, 0, 0},{0x8961, 0xe0, 0, 0},
++ {0x8962, 0xe4, 0, 0},{0x8963, 0xc9, 0, 0},{0x8964, 0xfa, 0, 0},
++ {0x8965, 0xe4, 0, 0},{0x8966, 0xcc, 0, 0},{0x8967, 0xfb, 0, 0},
++ {0x8968, 0x22, 0, 0},{0x8969, 0x75, 0, 0},{0x896a, 0xf0, 0, 0},
++ {0x896b, 0x10, 0, 0},{0x896c, 0xef, 0, 0},{0x896d, 0x2f, 0, 0},
++ {0x896e, 0xff, 0, 0},{0x896f, 0xee, 0, 0},{0x8970, 0x33, 0, 0},
++ {0x8971, 0xfe, 0, 0},{0x8972, 0xed, 0, 0},{0x8973, 0x33, 0, 0},
++ {0x8974, 0xfd, 0, 0},{0x8975, 0xcc, 0, 0},{0x8976, 0x33, 0, 0},
++ {0x8977, 0xcc, 0, 0},{0x8978, 0xc8, 0, 0},{0x8979, 0x33, 0, 0},
++ {0x897a, 0xc8, 0, 0},{0x897b, 0x10, 0, 0},{0x897c, 0xd7, 0, 0},
++ {0x897d, 0x07, 0, 0},{0x897e, 0x9b, 0, 0},{0x897f, 0xec, 0, 0},
++ {0x8980, 0x9a, 0, 0},{0x8981, 0xe8, 0, 0},{0x8982, 0x99, 0, 0},
++ {0x8983, 0x40, 0, 0},{0x8984, 0x0a, 0, 0},{0x8985, 0xed, 0, 0},
++ {0x8986, 0x9b, 0, 0},{0x8987, 0xfd, 0, 0},{0x8988, 0xec, 0, 0},
++ {0x8989, 0x9a, 0, 0},{0x898a, 0xfc, 0, 0},{0x898b, 0xe8, 0, 0},
++ {0x898c, 0x99, 0, 0},{0x898d, 0xf8, 0, 0},{0x898e, 0x0f, 0, 0},
++ {0x898f, 0xd5, 0, 0},{0x8990, 0xf0, 0, 0},{0x8991, 0xda, 0, 0},
++ {0x8992, 0xe4, 0, 0},{0x8993, 0xcd, 0, 0},{0x8994, 0xfb, 0, 0},
++ {0x8995, 0xe4, 0, 0},{0x8996, 0xcc, 0, 0},{0x8997, 0xfa, 0, 0},
++ {0x8998, 0xe4, 0, 0},{0x8999, 0xc8, 0, 0},{0x899a, 0xf9, 0, 0},
++ {0x899b, 0x22, 0, 0},{0x899c, 0xe8, 0, 0},{0x899d, 0x60, 0, 0},
++ {0x899e, 0x0f, 0, 0},{0x899f, 0xec, 0, 0},{0x89a0, 0xc3, 0, 0},
++ {0x89a1, 0x13, 0, 0},{0x89a2, 0xfc, 0, 0},{0x89a3, 0xed, 0, 0},
++ {0x89a4, 0x13, 0, 0},{0x89a5, 0xfd, 0, 0},{0x89a6, 0xee, 0, 0},
++ {0x89a7, 0x13, 0, 0},{0x89a8, 0xfe, 0, 0},{0x89a9, 0xef, 0, 0},
++ {0x89aa, 0x13, 0, 0},{0x89ab, 0xff, 0, 0},{0x89ac, 0xd8, 0, 0},
++ {0x89ad, 0xf1, 0, 0},{0x89ae, 0x22, 0, 0},{0x89af, 0xe8, 0, 0},
++ {0x89b0, 0x60, 0, 0},{0x89b1, 0x0f, 0, 0},{0x89b2, 0xef, 0, 0},
++ {0x89b3, 0xc3, 0, 0},{0x89b4, 0x33, 0, 0},{0x89b5, 0xff, 0, 0},
++ {0x89b6, 0xee, 0, 0},{0x89b7, 0x33, 0, 0},{0x89b8, 0xfe, 0, 0},
++ {0x89b9, 0xed, 0, 0},{0x89ba, 0x33, 0, 0},{0x89bb, 0xfd, 0, 0},
++ {0x89bc, 0xec, 0, 0},{0x89bd, 0x33, 0, 0},{0x89be, 0xfc, 0, 0},
++ {0x89bf, 0xd8, 0, 0},{0x89c0, 0xf1, 0, 0},{0x89c1, 0x22, 0, 0},
++ {0x89c2, 0xe4, 0, 0},{0x89c3, 0x93, 0, 0},{0x89c4, 0xfc, 0, 0},
++ {0x89c5, 0x74, 0, 0},{0x89c6, 0x01, 0, 0},{0x89c7, 0x93, 0, 0},
++ {0x89c8, 0xfd, 0, 0},{0x89c9, 0x74, 0, 0},{0x89ca, 0x02, 0, 0},
++ {0x89cb, 0x93, 0, 0},{0x89cc, 0xfe, 0, 0},{0x89cd, 0x74, 0, 0},
++ {0x89ce, 0x03, 0, 0},{0x89cf, 0x93, 0, 0},{0x89d0, 0xff, 0, 0},
++ {0x89d1, 0x22, 0, 0},{0x89d2, 0xd0, 0, 0},{0x89d3, 0x83, 0, 0},
++ {0x89d4, 0xd0, 0, 0},{0x89d5, 0x82, 0, 0},{0x89d6, 0xf8, 0, 0},
++ {0x89d7, 0xe4, 0, 0},{0x89d8, 0x93, 0, 0},{0x89d9, 0x70, 0, 0},
++ {0x89da, 0x12, 0, 0},{0x89db, 0x74, 0, 0},{0x89dc, 0x01, 0, 0},
++ {0x89dd, 0x93, 0, 0},{0x89de, 0x70, 0, 0},{0x89df, 0x0d, 0, 0},
++ {0x89e0, 0xa3, 0, 0},{0x89e1, 0xa3, 0, 0},{0x89e2, 0x93, 0, 0},
++ {0x89e3, 0xf8, 0, 0},{0x89e4, 0x74, 0, 0},{0x89e5, 0x01, 0, 0},
++ {0x89e6, 0x93, 0, 0},{0x89e7, 0xf5, 0, 0},{0x89e8, 0x82, 0, 0},
++ {0x89e9, 0x88, 0, 0},{0x89ea, 0x83, 0, 0},{0x89eb, 0xe4, 0, 0},
++ {0x89ec, 0x73, 0, 0},{0x89ed, 0x74, 0, 0},{0x89ee, 0x02, 0, 0},
++ {0x89ef, 0x93, 0, 0},{0x89f0, 0x68, 0, 0},{0x89f1, 0x60, 0, 0},
++ {0x89f2, 0xef, 0, 0},{0x89f3, 0xa3, 0, 0},{0x89f4, 0xa3, 0, 0},
++ {0x89f5, 0xa3, 0, 0},{0x89f6, 0x80, 0, 0},{0x89f7, 0xdf, 0, 0},
++ {0x89f8, 0x75, 0, 0},{0x89f9, 0x12, 0, 0},{0x89fa, 0x0a, 0, 0},
++ {0x89fb, 0xa2, 0, 0},{0x89fc, 0xaf, 0, 0},{0x89fd, 0x92, 0, 0},
++ {0x89fe, 0x32, 0, 0},{0x89ff, 0xc2, 0, 0},{0x8a00, 0xaf, 0, 0},
++ {0x8a01, 0xc2, 0, 0},{0x8a02, 0x33, 0, 0},{0x8a03, 0x12, 0, 0},
++ {0x8a04, 0x01, 0, 0},{0x8a05, 0x6a, 0, 0},{0x8a06, 0x12, 0, 0},
++ {0x8a07, 0x02, 0, 0},{0x8a08, 0x08, 0, 0},{0x8a09, 0x12, 0, 0},
++ {0x8a0a, 0x01, 0, 0},{0x8a0b, 0x6a, 0, 0},{0x8a0c, 0x75, 0, 0},
++ {0x8a0d, 0x51, 0, 0},{0x8a0e, 0x05, 0, 0},{0x8a0f, 0xaf, 0, 0},
++ {0x8a10, 0x51, 0, 0},{0x8a11, 0x15, 0, 0},{0x8a12, 0x51, 0, 0},
++ {0x8a13, 0xef, 0, 0},{0x8a14, 0x70, 0, 0},{0x8a15, 0xf9, 0, 0},
++ {0x8a16, 0xd2, 0, 0},{0x8a17, 0x28, 0, 0},{0x8a18, 0x12, 0, 0},
++ {0x8a19, 0x01, 0, 0},{0x8a1a, 0x6c, 0, 0},{0x8a1b, 0x75, 0, 0},
++ {0x8a1c, 0x51, 0, 0},{0x8a1d, 0x0a, 0, 0},{0x8a1e, 0xaf, 0, 0},
++ {0x8a1f, 0x51, 0, 0},{0x8a20, 0x15, 0, 0},{0x8a21, 0x51, 0, 0},
++ {0x8a22, 0xef, 0, 0},{0x8a23, 0x70, 0, 0},{0x8a24, 0xf9, 0, 0},
++ {0x8a25, 0xc2, 0, 0},{0x8a26, 0x29, 0, 0},{0x8a27, 0x12, 0, 0},
++ {0x8a28, 0x01, 0, 0},{0x8a29, 0x6c, 0, 0},{0x8a2a, 0x75, 0, 0},
++ {0x8a2b, 0x51, 0, 0},{0x8a2c, 0x05, 0, 0},{0x8a2d, 0xaf, 0, 0},
++ {0x8a2e, 0x51, 0, 0},{0x8a2f, 0x15, 0, 0},{0x8a30, 0x51, 0, 0},
++ {0x8a31, 0xef, 0, 0},{0x8a32, 0x70, 0, 0},{0x8a33, 0xf9, 0, 0},
++ {0x8a34, 0xc2, 0, 0},{0x8a35, 0x28, 0, 0},{0x8a36, 0x12, 0, 0},
++ {0x8a37, 0x01, 0, 0},{0x8a38, 0x6c, 0, 0},{0x8a39, 0x75, 0, 0},
++ {0x8a3a, 0x51, 0, 0},{0x8a3b, 0x05, 0, 0},{0x8a3c, 0xaf, 0, 0},
++ {0x8a3d, 0x51, 0, 0},{0x8a3e, 0x15, 0, 0},{0x8a3f, 0x51, 0, 0},
++ {0x8a40, 0xef, 0, 0},{0x8a41, 0x70, 0, 0},{0x8a42, 0xf9, 0, 0},
++ {0x8a43, 0x75, 0, 0},{0x8a44, 0x13, 0, 0},{0x8a45, 0x18, 0, 0},
++ {0x8a46, 0x12, 0, 0},{0x8a47, 0x0b, 0, 0},{0x8a48, 0x38, 0, 0},
++ {0x8a49, 0x75, 0, 0},{0x8a4a, 0x51, 0, 0},{0x8a4b, 0x0a, 0, 0},
++ {0x8a4c, 0xaf, 0, 0},{0x8a4d, 0x51, 0, 0},{0x8a4e, 0x15, 0, 0},
++ {0x8a4f, 0x51, 0, 0},{0x8a50, 0xef, 0, 0},{0x8a51, 0x70, 0, 0},
++ {0x8a52, 0xf9, 0, 0},{0x8a53, 0xd2, 0, 0},{0x8a54, 0x28, 0, 0},
++ {0x8a55, 0x12, 0, 0},{0x8a56, 0x01, 0, 0},{0x8a57, 0x6c, 0, 0},
++ {0x8a58, 0x12, 0, 0},{0x8a59, 0x02, 0, 0},{0x8a5a, 0x25, 0, 0},
++ {0x8a5b, 0xaf, 0, 0},{0x8a5c, 0x51, 0, 0},{0x8a5d, 0x15, 0, 0},
++ {0x8a5e, 0x51, 0, 0},{0x8a5f, 0xef, 0, 0},{0x8a60, 0x70, 0, 0},
++ {0x8a61, 0xf9, 0, 0},{0x8a62, 0xc2, 0, 0},{0x8a63, 0x28, 0, 0},
++ {0x8a64, 0x12, 0, 0},{0x8a65, 0x01, 0, 0},{0x8a66, 0x6c, 0, 0},
++ {0x8a67, 0x75, 0, 0},{0x8a68, 0x51, 0, 0},{0x8a69, 0x0a, 0, 0},
++ {0x8a6a, 0xaf, 0, 0},{0x8a6b, 0x51, 0, 0},{0x8a6c, 0x15, 0, 0},
++ {0x8a6d, 0x51, 0, 0},{0x8a6e, 0xef, 0, 0},{0x8a6f, 0x70, 0, 0},
++ {0x8a70, 0xf9, 0, 0},{0x8a71, 0x30, 0, 0},{0x8a72, 0x11, 0, 0},
++ {0x8a73, 0x03, 0, 0},{0x8a74, 0x02, 0, 0},{0x8a75, 0x0a, 0, 0},
++ {0x8a76, 0xef, 0, 0},{0x8a77, 0x12, 0, 0},{0x8a78, 0x01, 0, 0},
++ {0x8a79, 0x6a, 0, 0},{0x8a7a, 0x12, 0, 0},{0x8a7b, 0x02, 0, 0},
++ {0x8a7c, 0x08, 0, 0},{0x8a7d, 0xe5, 0, 0},{0x8a7e, 0x10, 0, 0},
++ {0x8a7f, 0xf5, 0, 0},{0x8a80, 0x13, 0, 0},{0x8a81, 0x12, 0, 0},
++ {0x8a82, 0x0b, 0, 0},{0x8a83, 0x38, 0, 0},{0x8a84, 0x75, 0, 0},
++ {0x8a85, 0x51, 0, 0},{0x8a86, 0x0a, 0, 0},{0x8a87, 0xaf, 0, 0},
++ {0x8a88, 0x51, 0, 0},{0x8a89, 0x15, 0, 0},{0x8a8a, 0x51, 0, 0},
++ {0x8a8b, 0xef, 0, 0},{0x8a8c, 0x70, 0, 0},{0x8a8d, 0xf9, 0, 0},
++ {0x8a8e, 0xd2, 0, 0},{0x8a8f, 0x28, 0, 0},{0x8a90, 0x12, 0, 0},
++ {0x8a91, 0x01, 0, 0},{0x8a92, 0x6c, 0, 0},{0x8a93, 0x12, 0, 0},
++ {0x8a94, 0x02, 0, 0},{0x8a95, 0x25, 0, 0},{0x8a96, 0xaf, 0, 0},
++ {0x8a97, 0x51, 0, 0},{0x8a98, 0x15, 0, 0},{0x8a99, 0x51, 0, 0},
++ {0x8a9a, 0xef, 0, 0},{0x8a9b, 0x70, 0, 0},{0x8a9c, 0xf9, 0, 0},
++ {0x8a9d, 0xc2, 0, 0},{0x8a9e, 0x28, 0, 0},{0x8a9f, 0x12, 0, 0},
++ {0x8aa0, 0x01, 0, 0},{0x8aa1, 0x6c, 0, 0},{0x8aa2, 0x75, 0, 0},
++ {0x8aa3, 0x51, 0, 0},{0x8aa4, 0x0a, 0, 0},{0x8aa5, 0xaf, 0, 0},
++ {0x8aa6, 0x51, 0, 0},{0x8aa7, 0x15, 0, 0},{0x8aa8, 0x51, 0, 0},
++ {0x8aa9, 0xef, 0, 0},{0x8aaa, 0x70, 0, 0},{0x8aab, 0xf9, 0, 0},
++ {0x8aac, 0x30, 0, 0},{0x8aad, 0x11, 0, 0},{0x8aae, 0x04, 0, 0},
++ {0x8aaf, 0x15, 0, 0},{0x8ab0, 0x12, 0, 0},{0x8ab1, 0x80, 0, 0},
++ {0x8ab2, 0x45, 0, 0},{0x8ab3, 0x12, 0, 0},{0x8ab4, 0x01, 0, 0},
++ {0x8ab5, 0x6a, 0, 0},{0x8ab6, 0x12, 0, 0},{0x8ab7, 0x02, 0, 0},
++ {0x8ab8, 0x08, 0, 0},{0x8ab9, 0x85, 0, 0},{0x8aba, 0x11, 0, 0},
++ {0x8abb, 0x13, 0, 0},{0x8abc, 0x12, 0, 0},{0x8abd, 0x13, 0, 0},
++ {0x8abe, 0x72, 0, 0},{0x8abf, 0xc2, 0, 0},{0x8ac0, 0x09, 0, 0},
++ {0x8ac1, 0x12, 0, 0},{0x8ac2, 0x02, 0, 0},{0x8ac3, 0x0a, 0, 0},
++ {0x8ac4, 0x75, 0, 0},{0x8ac5, 0x51, 0, 0},{0x8ac6, 0x0a, 0, 0},
++ {0x8ac7, 0xaf, 0, 0},{0x8ac8, 0x51, 0, 0},{0x8ac9, 0x15, 0, 0},
++ {0x8aca, 0x51, 0, 0},{0x8acb, 0xef, 0, 0},{0x8acc, 0x70, 0, 0},
++ {0x8acd, 0xf9, 0, 0},{0x8ace, 0xd2, 0, 0},{0x8acf, 0x28, 0, 0},
++ {0x8ad0, 0x12, 0, 0},{0x8ad1, 0x01, 0, 0},{0x8ad2, 0x6c, 0, 0},
++ {0x8ad3, 0x12, 0, 0},{0x8ad4, 0x02, 0, 0},{0x8ad5, 0x25, 0, 0},
++ {0x8ad6, 0xaf, 0, 0},{0x8ad7, 0x51, 0, 0},{0x8ad8, 0x15, 0, 0},
++ {0x8ad9, 0x51, 0, 0},{0x8ada, 0xef, 0, 0},{0x8adb, 0x70, 0, 0},
++ {0x8adc, 0xf9, 0, 0},{0x8add, 0xc2, 0, 0},{0x8ade, 0x28, 0, 0},
++ {0x8adf, 0x12, 0, 0},{0x8ae0, 0x01, 0, 0},{0x8ae1, 0x6c, 0, 0},
++ {0x8ae2, 0x75, 0, 0},{0x8ae3, 0x51, 0, 0},{0x8ae4, 0x0a, 0, 0},
++ {0x8ae5, 0xaf, 0, 0},{0x8ae6, 0x51, 0, 0},{0x8ae7, 0x15, 0, 0},
++ {0x8ae8, 0x51, 0, 0},{0x8ae9, 0xef, 0, 0},{0x8aea, 0x70, 0, 0},
++ {0x8aeb, 0xf9, 0, 0},{0x8aec, 0x30, 0, 0},{0x8aed, 0x11, 0, 0},
++ {0x8aee, 0x06, 0, 0},{0x8aef, 0x15, 0, 0},{0x8af0, 0x12, 0, 0},
++ {0x8af1, 0xd2, 0, 0},{0x8af2, 0x33, 0, 0},{0x8af3, 0x80, 0, 0},
++ {0x8af4, 0x03, 0, 0},{0x8af5, 0xe4, 0, 0},{0x8af6, 0xf5, 0, 0},
++ {0x8af7, 0x12, 0, 0},{0x8af8, 0x12, 0, 0},{0x8af9, 0x01, 0, 0},
++ {0x8afa, 0x6a, 0, 0},{0x8afb, 0x12, 0, 0},{0x8afc, 0x02, 0, 0},
++ {0x8afd, 0x08, 0, 0},{0x8afe, 0xc2, 0, 0},{0x8aff, 0x29, 0, 0},
++ {0x8b00, 0x12, 0, 0},{0x8b01, 0x01, 0, 0},{0x8b02, 0x6c, 0, 0},
++ {0x8b03, 0x75, 0, 0},{0x8b04, 0x51, 0, 0},{0x8b05, 0x05, 0, 0},
++ {0x8b06, 0xaf, 0, 0},{0x8b07, 0x51, 0, 0},{0x8b08, 0x15, 0, 0},
++ {0x8b09, 0x51, 0, 0},{0x8b0a, 0xef, 0, 0},{0x8b0b, 0x70, 0, 0},
++ {0x8b0c, 0xf9, 0, 0},{0x8b0d, 0xd2, 0, 0},{0x8b0e, 0x28, 0, 0},
++ {0x8b0f, 0x12, 0, 0},{0x8b10, 0x01, 0, 0},{0x8b11, 0x6c, 0, 0},
++ {0x8b12, 0x75, 0, 0},{0x8b13, 0x51, 0, 0},{0x8b14, 0x05, 0, 0},
++ {0x8b15, 0xaf, 0, 0},{0x8b16, 0x51, 0, 0},{0x8b17, 0x15, 0, 0},
++ {0x8b18, 0x51, 0, 0},{0x8b19, 0xef, 0, 0},{0x8b1a, 0x70, 0, 0},
++ {0x8b1b, 0xf9, 0, 0},{0x8b1c, 0x12, 0, 0},{0x8b1d, 0x01, 0, 0},
++ {0x8b1e, 0x6a, 0, 0},{0x8b1f, 0x75, 0, 0},{0x8b20, 0x51, 0, 0},
++ {0x8b21, 0x05, 0, 0},{0x8b22, 0xaf, 0, 0},{0x8b23, 0x51, 0, 0},
++ {0x8b24, 0x15, 0, 0},{0x8b25, 0x51, 0, 0},{0x8b26, 0xef, 0, 0},
++ {0x8b27, 0x70, 0, 0},{0x8b28, 0xf9, 0, 0},{0x8b29, 0xa2, 0, 0},
++ {0x8b2a, 0x32, 0, 0},{0x8b2b, 0x92, 0, 0},{0x8b2c, 0xaf, 0, 0},
++ {0x8b2d, 0xe5, 0, 0},{0x8b2e, 0x12, 0, 0},{0x8b2f, 0xd3, 0, 0},
++ {0x8b30, 0x94, 0, 0},{0x8b31, 0x00, 0, 0},{0x8b32, 0x40, 0, 0},
++ {0x8b33, 0x03, 0, 0},{0x8b34, 0x02, 0, 0},{0x8b35, 0x09, 0, 0},
++ {0x8b36, 0xff, 0, 0},{0x8b37, 0x22, 0, 0},{0x8b38, 0x12, 0, 0},
++ {0x8b39, 0x13, 0, 0},{0x8b3a, 0x72, 0, 0},{0x8b3b, 0xc2, 0, 0},
++ {0x8b3c, 0x09, 0, 0},{0x8b3d, 0x90, 0, 0},{0x8b3e, 0x30, 0, 0},
++ {0x8b3f, 0x18, 0, 0},{0x8b40, 0xe5, 0, 0},{0x8b41, 0x21, 0, 0},
++ {0x8b42, 0xf0, 0, 0},{0x8b43, 0x22, 0, 0},{0x8b44, 0xc0, 0, 0},
++ {0x8b45, 0xe0, 0, 0},{0x8b46, 0xc0, 0, 0},{0x8b47, 0xf0, 0, 0},
++ {0x8b48, 0xc0, 0, 0},{0x8b49, 0x83, 0, 0},{0x8b4a, 0xc0, 0, 0},
++ {0x8b4b, 0x82, 0, 0},{0x8b4c, 0xc0, 0, 0},{0x8b4d, 0xd0, 0, 0},
++ {0x8b4e, 0x75, 0, 0},{0x8b4f, 0xd0, 0, 0},{0x8b50, 0x00, 0, 0},
++ {0x8b51, 0xc0, 0, 0},{0x8b52, 0x00, 0, 0},{0x8b53, 0xc0, 0, 0},
++ {0x8b54, 0x01, 0, 0},{0x8b55, 0xc0, 0, 0},{0x8b56, 0x02, 0, 0},
++ {0x8b57, 0xc0, 0, 0},{0x8b58, 0x03, 0, 0},{0x8b59, 0xc0, 0, 0},
++ {0x8b5a, 0x04, 0, 0},{0x8b5b, 0xc0, 0, 0},{0x8b5c, 0x05, 0, 0},
++ {0x8b5d, 0xc0, 0, 0},{0x8b5e, 0x06, 0, 0},{0x8b5f, 0xc0, 0, 0},
++ {0x8b60, 0x07, 0, 0},{0x8b61, 0x90, 0, 0},{0x8b62, 0x3f, 0, 0},
++ {0x8b63, 0x0c, 0, 0},{0x8b64, 0xe0, 0, 0},{0x8b65, 0xf5, 0, 0},
++ {0x8b66, 0x08, 0, 0},{0x8b67, 0xe5, 0, 0},{0x8b68, 0x08, 0, 0},
++ {0x8b69, 0x20, 0, 0},{0x8b6a, 0xe3, 0, 0},{0x8b6b, 0x03, 0, 0},
++ {0x8b6c, 0x02, 0, 0},{0x8b6d, 0x0b, 0, 0},{0x8b6e, 0xf5, 0, 0},
++ {0x8b6f, 0x30, 0, 0},{0x8b70, 0x35, 0, 0},{0x8b71, 0x03, 0, 0},
++ {0x8b72, 0x02, 0, 0},{0x8b73, 0x0b, 0, 0},{0x8b74, 0xf5, 0, 0},
++ {0x8b75, 0x90, 0, 0},{0x8b76, 0x60, 0, 0},{0x8b77, 0x16, 0, 0},
++ {0x8b78, 0xe0, 0, 0},{0x8b79, 0xf5, 0, 0},{0x8b7a, 0x69, 0, 0},
++ {0x8b7b, 0xa3, 0, 0},{0x8b7c, 0xe0, 0, 0},{0x8b7d, 0xf5, 0, 0},
++ {0x8b7e, 0x6a, 0, 0},{0x8b7f, 0x90, 0, 0},{0x8b80, 0x60, 0, 0},
++ {0x8b81, 0x1e, 0, 0},{0x8b82, 0xe0, 0, 0},{0x8b83, 0xf5, 0, 0},
++ {0x8b84, 0x6b, 0, 0},{0x8b85, 0xa3, 0, 0},{0x8b86, 0xe0, 0, 0},
++ {0x8b87, 0xf5, 0, 0},{0x8b88, 0x6c, 0, 0},{0x8b89, 0x90, 0, 0},
++ {0x8b8a, 0x60, 0, 0},{0x8b8b, 0x26, 0, 0},{0x8b8c, 0xe0, 0, 0},
++ {0x8b8d, 0xf5, 0, 0},{0x8b8e, 0x6d, 0, 0},{0x8b8f, 0xa3, 0, 0},
++ {0x8b90, 0xe0, 0, 0},{0x8b91, 0xf5, 0, 0},{0x8b92, 0x6e, 0, 0},
++ {0x8b93, 0x90, 0, 0},{0x8b94, 0x60, 0, 0},{0x8b95, 0x2e, 0, 0},
++ {0x8b96, 0xe0, 0, 0},{0x8b97, 0xf5, 0, 0},{0x8b98, 0x6f, 0, 0},
++ {0x8b99, 0xa3, 0, 0},{0x8b9a, 0xe0, 0, 0},{0x8b9b, 0xf5, 0, 0},
++ {0x8b9c, 0x70, 0, 0},{0x8b9d, 0x90, 0, 0},{0x8b9e, 0x60, 0, 0},
++ {0x8b9f, 0x36, 0, 0},{0x8ba0, 0x12, 0, 0},{0x8ba1, 0x00, 0, 0},
++ {0x8ba2, 0x16, 0, 0},{0x8ba3, 0x12, 0, 0},{0x8ba4, 0x01, 0, 0},
++ {0x8ba5, 0xc8, 0, 0},{0x8ba6, 0x40, 0, 0},{0x8ba7, 0x06, 0, 0},
++ {0x8ba8, 0x75, 0, 0},{0x8ba9, 0x2a, 0, 0},{0x8baa, 0xff, 0, 0},
++ {0x8bab, 0x75, 0, 0},{0x8bac, 0x2b, 0, 0},{0x8bad, 0xff, 0, 0},
++ {0x8bae, 0x85, 0, 0},{0x8baf, 0x2a, 0, 0},{0x8bb0, 0x73, 0, 0},
++ {0x8bb1, 0x85, 0, 0},{0x8bb2, 0x2b, 0, 0},{0x8bb3, 0x74, 0, 0},
++ {0x8bb4, 0x90, 0, 0},{0x8bb5, 0x60, 0, 0},{0x8bb6, 0x1a, 0, 0},
++ {0x8bb7, 0xe0, 0, 0},{0x8bb8, 0xf5, 0, 0},{0x8bb9, 0x69, 0, 0},
++ {0x8bba, 0xa3, 0, 0},{0x8bbb, 0xe0, 0, 0},{0x8bbc, 0xf5, 0, 0},
++ {0x8bbd, 0x6a, 0, 0},{0x8bbe, 0x90, 0, 0},{0x8bbf, 0x60, 0, 0},
++ {0x8bc0, 0x22, 0, 0},{0x8bc1, 0xe0, 0, 0},{0x8bc2, 0xf5, 0, 0},
++ {0x8bc3, 0x6b, 0, 0},{0x8bc4, 0xa3, 0, 0},{0x8bc5, 0xe0, 0, 0},
++ {0x8bc6, 0xf5, 0, 0},{0x8bc7, 0x6c, 0, 0},{0x8bc8, 0x90, 0, 0},
++ {0x8bc9, 0x60, 0, 0},{0x8bca, 0x2a, 0, 0},{0x8bcb, 0xe0, 0, 0},
++ {0x8bcc, 0xf5, 0, 0},{0x8bcd, 0x6d, 0, 0},{0x8bce, 0xa3, 0, 0},
++ {0x8bcf, 0xe0, 0, 0},{0x8bd0, 0xf5, 0, 0},{0x8bd1, 0x6e, 0, 0},
++ {0x8bd2, 0x90, 0, 0},{0x8bd3, 0x60, 0, 0},{0x8bd4, 0x32, 0, 0},
++ {0x8bd5, 0xe0, 0, 0},{0x8bd6, 0xf5, 0, 0},{0x8bd7, 0x6f, 0, 0},
++ {0x8bd8, 0xa3, 0, 0},{0x8bd9, 0xe0, 0, 0},{0x8bda, 0xf5, 0, 0},
++ {0x8bdb, 0x70, 0, 0},{0x8bdc, 0x90, 0, 0},{0x8bdd, 0x60, 0, 0},
++ {0x8bde, 0x3a, 0, 0},{0x8bdf, 0x12, 0, 0},{0x8be0, 0x00, 0, 0},
++ {0x8be1, 0x16, 0, 0},{0x8be2, 0x12, 0, 0},{0x8be3, 0x01, 0, 0},
++ {0x8be4, 0xc8, 0, 0},{0x8be5, 0x40, 0, 0},{0x8be6, 0x06, 0, 0},
++ {0x8be7, 0x75, 0, 0},{0x8be8, 0x2a, 0, 0},{0x8be9, 0xff, 0, 0},
++ {0x8bea, 0x75, 0, 0},{0x8beb, 0x2b, 0, 0},{0x8bec, 0xff, 0, 0},
++ {0x8bed, 0x85, 0, 0},{0x8bee, 0x2a, 0, 0},{0x8bef, 0x75, 0, 0},
++ {0x8bf0, 0x85, 0, 0},{0x8bf1, 0x2b, 0, 0},{0x8bf2, 0x76, 0, 0},
++ {0x8bf3, 0xd2, 0, 0},{0x8bf4, 0x3b, 0, 0},{0x8bf5, 0xe5, 0, 0},
++ {0x8bf6, 0x08, 0, 0},{0x8bf7, 0x30, 0, 0},{0x8bf8, 0xe5, 0, 0},
++ {0x8bf9, 0x41, 0, 0},{0x8bfa, 0x90, 0, 0},{0x8bfb, 0x56, 0, 0},
++ {0x8bfc, 0x90, 0, 0},{0x8bfd, 0xe0, 0, 0},{0x8bfe, 0xf5, 0, 0},
++ {0x8bff, 0x55, 0, 0},{0x8c00, 0xe5, 0, 0},{0x8c01, 0x7a, 0, 0},
++ {0x8c02, 0x12, 0, 0},{0x8c03, 0x01, 0, 0},{0x8c04, 0xc1, 0, 0},
++ {0x8c05, 0xad, 0, 0},{0x8c06, 0x55, 0, 0},{0x8c07, 0xc3, 0, 0},
++ {0x8c08, 0xef, 0, 0},{0x8c09, 0x9d, 0, 0},{0x8c0a, 0x74, 0, 0},
++ {0x8c0b, 0x80, 0, 0},{0x8c0c, 0xf8, 0, 0},{0x8c0d, 0x6e, 0, 0},
++ {0x8c0e, 0x98, 0, 0},{0x8c0f, 0x50, 0, 0},{0x8c10, 0x02, 0, 0},
++ {0x8c11, 0x80, 0, 0},{0x8c12, 0x01, 0, 0},{0x8c13, 0xc3, 0, 0},
++ {0x8c14, 0x92, 0, 0},{0x8c15, 0x27, 0, 0},{0x8c16, 0xaf, 0, 0},
++ {0x8c17, 0x55, 0, 0},{0x8c18, 0xef, 0, 0},{0x8c19, 0x24, 0, 0},
++ {0x8c1a, 0x01, 0, 0},{0x8c1b, 0xff, 0, 0},{0x8c1c, 0xe4, 0, 0},
++ {0x8c1d, 0x33, 0, 0},{0x8c1e, 0xfe, 0, 0},{0x8c1f, 0xc3, 0, 0},
++ {0x8c20, 0xef, 0, 0},{0x8c21, 0x95, 0, 0},{0x8c22, 0x7a, 0, 0},
++ {0x8c23, 0x74, 0, 0},{0x8c24, 0x80, 0, 0},{0x8c25, 0xf8, 0, 0},
++ {0x8c26, 0x6e, 0, 0},{0x8c27, 0x98, 0, 0},{0x8c28, 0x50, 0, 0},
++ {0x8c29, 0x02, 0, 0},{0x8c2a, 0x80, 0, 0},{0x8c2b, 0x02, 0, 0},
++ {0x8c2c, 0xa2, 0, 0},{0x8c2d, 0x27, 0, 0},{0x8c2e, 0x92, 0, 0},
++ {0x8c2f, 0x27, 0, 0},{0x8c30, 0x30, 0, 0},{0x8c31, 0x27, 0, 0},
++ {0x8c32, 0x04, 0, 0},{0x8c33, 0xaf, 0, 0},{0x8c34, 0x55, 0, 0},
++ {0x8c35, 0x80, 0, 0},{0x8c36, 0x02, 0, 0},{0x8c37, 0xaf, 0, 0},
++ {0x8c38, 0x7a, 0, 0},{0x8c39, 0x8f, 0, 0},{0x8c3a, 0x7a, 0, 0},
++ {0x8c3b, 0xe5, 0, 0},{0x8c3c, 0x08, 0, 0},{0x8c3d, 0x30, 0, 0},
++ {0x8c3e, 0xe1, 0, 0},{0x8c3f, 0x08, 0, 0},{0x8c40, 0x90, 0, 0},
++ {0x8c41, 0x30, 0, 0},{0x8c42, 0x24, 0, 0},{0x8c43, 0xe0, 0, 0},
++ {0x8c44, 0xf5, 0, 0},{0x8c45, 0x33, 0, 0},{0x8c46, 0xe4, 0, 0},
++ {0x8c47, 0xf0, 0, 0},{0x8c48, 0x90, 0, 0},{0x8c49, 0x3f, 0, 0},
++ {0x8c4a, 0x0c, 0, 0},{0x8c4b, 0xe5, 0, 0},{0x8c4c, 0x08, 0, 0},
++ {0x8c4d, 0xf0, 0, 0},{0x8c4e, 0xd0, 0, 0},{0x8c4f, 0x07, 0, 0},
++ {0x8c50, 0xd0, 0, 0},{0x8c51, 0x06, 0, 0},{0x8c52, 0xd0, 0, 0},
++ {0x8c53, 0x05, 0, 0},{0x8c54, 0xd0, 0, 0},{0x8c55, 0x04, 0, 0},
++ {0x8c56, 0xd0, 0, 0},{0x8c57, 0x03, 0, 0},{0x8c58, 0xd0, 0, 0},
++ {0x8c59, 0x02, 0, 0},{0x8c5a, 0xd0, 0, 0},{0x8c5b, 0x01, 0, 0},
++ {0x8c5c, 0xd0, 0, 0},{0x8c5d, 0x00, 0, 0},{0x8c5e, 0xd0, 0, 0},
++ {0x8c5f, 0xd0, 0, 0},{0x8c60, 0xd0, 0, 0},{0x8c61, 0x82, 0, 0},
++ {0x8c62, 0xd0, 0, 0},{0x8c63, 0x83, 0, 0},{0x8c64, 0xd0, 0, 0},
++ {0x8c65, 0xf0, 0, 0},{0x8c66, 0xd0, 0, 0},{0x8c67, 0xe0, 0, 0},
++ {0x8c68, 0x32, 0, 0},{0x8c69, 0xe5, 0, 0},{0x8c6a, 0x33, 0, 0},
++ {0x8c6b, 0x70, 0, 0},{0x8c6c, 0x03, 0, 0},{0x8c6d, 0x02, 0, 0},
++ {0x8c6e, 0x0d, 0, 0},{0x8c6f, 0x76, 0, 0},{0x8c70, 0xc2, 0, 0},
++ {0x8c71, 0xaf, 0, 0},{0x8c72, 0xaf, 0, 0},{0x8c73, 0x33, 0, 0},
++ {0x8c74, 0xe4, 0, 0},{0x8c75, 0xf5, 0, 0},{0x8c76, 0x33, 0, 0},
++ {0x8c77, 0xd2, 0, 0},{0x8c78, 0xaf, 0, 0},{0x8c79, 0x90, 0, 0},
++ {0x8c7a, 0x30, 0, 0},{0x8c7b, 0x25, 0, 0},{0x8c7c, 0xe0, 0, 0},
++ {0x8c7d, 0xf5, 0, 0},{0x8c7e, 0x7d, 0, 0},{0x8c7f, 0x90, 0, 0},
++ {0x8c80, 0x50, 0, 0},{0x8c81, 0x82, 0, 0},{0x8c82, 0xe0, 0, 0},
++ {0x8c83, 0xf5, 0, 0},{0x8c84, 0x65, 0, 0},{0x8c85, 0xa3, 0, 0},
++ {0x8c86, 0xe0, 0, 0},{0x8c87, 0xf5, 0, 0},{0x8c88, 0x66, 0, 0},
++ {0x8c89, 0xa3, 0, 0},{0x8c8a, 0xe0, 0, 0},{0x8c8b, 0xf5, 0, 0},
++ {0x8c8c, 0x67, 0, 0},{0x8c8d, 0xa3, 0, 0},{0x8c8e, 0xe0, 0, 0},
++ {0x8c8f, 0xf5, 0, 0},{0x8c90, 0x68, 0, 0},{0x8c91, 0xef, 0, 0},
++ {0x8c92, 0x12, 0, 0},{0x8c93, 0x09, 0, 0},{0x8c94, 0xd2, 0, 0},
++ {0x8c95, 0x0c, 0, 0},{0x8c96, 0xba, 0, 0},{0x8c97, 0x03, 0, 0},
++ {0x8c98, 0x0c, 0, 0},{0x8c99, 0xcf, 0, 0},{0x8c9a, 0x05, 0, 0},
++ {0x8c9b, 0x0c, 0, 0},{0x8c9c, 0xf9, 0, 0},{0x8c9d, 0x06, 0, 0},
++ {0x8c9e, 0x0c, 0, 0},{0x8c9f, 0xe7, 0, 0},{0x8ca0, 0x08, 0, 0},
++ {0x8ca1, 0x0d, 0, 0},{0x8ca2, 0x06, 0, 0},{0x8ca3, 0x10, 0, 0},
++ {0x8ca4, 0x0d, 0, 0},{0x8ca5, 0x1a, 0, 0},{0x8ca6, 0x12, 0, 0},
++ {0x8ca7, 0x0d, 0, 0},{0x8ca8, 0x1f, 0, 0},{0x8ca9, 0x20, 0, 0},
++ {0x8caa, 0x0d, 0, 0},{0x8cab, 0x2d, 0, 0},{0x8cac, 0x21, 0, 0},
++ {0x8cad, 0x0d, 0, 0},{0x8cae, 0x32, 0, 0},{0x8caf, 0x30, 0, 0},
++ {0x8cb0, 0x0d, 0, 0},{0x8cb1, 0x5b, 0, 0},{0x8cb2, 0x50, 0, 0},
++ {0x8cb3, 0x0d, 0, 0},{0x8cb4, 0x3d, 0, 0},{0x8cb5, 0xd8, 0, 0},
++ {0x8cb6, 0x00, 0, 0},{0x8cb7, 0x00, 0, 0},{0x8cb8, 0x0d, 0, 0},
++ {0x8cb9, 0x68, 0, 0},{0x8cba, 0x20, 0, 0},{0x8cbb, 0x05, 0, 0},
++ {0x8cbc, 0x03, 0, 0},{0x8cbd, 0x02, 0, 0},{0x8cbe, 0x0d, 0, 0},
++ {0x8cbf, 0x68, 0, 0},{0x8cc0, 0x30, 0, 0},{0x8cc1, 0x00, 0, 0},
++ {0x8cc2, 0x03, 0, 0},{0x8cc3, 0x02, 0, 0},{0x8cc4, 0x0d, 0, 0},
++ {0x8cc5, 0x68, 0, 0},{0x8cc6, 0xd2, 0, 0},{0x8cc7, 0x07, 0, 0},
++ {0x8cc8, 0xc2, 0, 0},{0x8cc9, 0x06, 0, 0},{0x8cca, 0x12, 0, 0},
++ {0x8ccb, 0x02, 0, 0},{0x8ccc, 0x90, 0, 0},{0x8ccd, 0x80, 0, 0},
++ {0x8cce, 0x24, 0, 0},{0x8ccf, 0x20, 0, 0},{0x8cd0, 0x05, 0, 0},
++ {0x8cd1, 0x03, 0, 0},{0x8cd2, 0x02, 0, 0},{0x8cd3, 0x0d, 0, 0},
++ {0x8cd4, 0x68, 0, 0},{0x8cd5, 0x30, 0, 0},{0x8cd6, 0x00, 0, 0},
++ {0x8cd7, 0x03, 0, 0},{0x8cd8, 0x02, 0, 0},{0x8cd9, 0x0d, 0, 0},
++ {0x8cda, 0x68, 0, 0},{0x8cdb, 0xc2, 0, 0},{0x8cdc, 0x07, 0, 0},
++ {0x8cdd, 0xd2, 0, 0},{0x8cde, 0x06, 0, 0},{0x8cdf, 0x12, 0, 0},
++ {0x8ce0, 0x02, 0, 0},{0x8ce1, 0xa5, 0, 0},{0x8ce2, 0xc2, 0, 0},
++ {0x8ce3, 0x04, 0, 0},{0x8ce4, 0x02, 0, 0},{0x8ce5, 0x0d, 0, 0},
++ {0x8ce6, 0x68, 0, 0},{0x8ce7, 0x12, 0, 0},{0x8ce8, 0x02, 0, 0},
++ {0x8ce9, 0x40, 0, 0},{0x8cea, 0x30, 0, 0},{0x8ceb, 0x05, 0, 0},
++ {0x8cec, 0x06, 0, 0},{0x8ced, 0xe4, 0, 0},{0x8cee, 0xf5, 0, 0},
++ {0x8cef, 0x0c, 0, 0},{0x8cf0, 0x12, 0, 0},{0x8cf1, 0x0f, 0, 0},
++ {0x8cf2, 0x11, 0, 0},{0x8cf3, 0xc2, 0, 0},{0x8cf4, 0x31, 0, 0},
++ {0x8cf5, 0xd2, 0, 0},{0x8cf6, 0x34, 0, 0},{0x8cf7, 0x80, 0, 0},
++ {0x8cf8, 0x6f, 0, 0},{0x8cf9, 0x30, 0, 0},{0x8cfa, 0x07, 0, 0},
++ {0x8cfb, 0x6c, 0, 0},{0x8cfc, 0x30, 0, 0},{0x8cfd, 0x06, 0, 0},
++ {0x8cfe, 0x69, 0, 0},{0x8cff, 0x12, 0, 0},{0x8d00, 0x02, 0, 0},
++ {0x8d01, 0x90, 0, 0},{0x8d02, 0xd2, 0, 0},{0x8d03, 0x31, 0, 0},
++ {0x8d04, 0x80, 0, 0},{0x8d05, 0x62, 0, 0},{0x8d06, 0x20, 0, 0},
++ {0x8d07, 0x07, 0, 0},{0x8d08, 0x03, 0, 0},{0x8d09, 0x30, 0, 0},
++ {0x8d0a, 0x06, 0, 0},{0x8d0b, 0x09, 0, 0},{0x8d0c, 0xe5, 0, 0},
++ {0x8d0d, 0x7d, 0, 0},{0x8d0e, 0x64, 0, 0},{0x8d0f, 0x0e, 0, 0},
++ {0x8d10, 0x70, 0, 0},{0x8d11, 0x56, 0, 0},{0x8d12, 0x20, 0, 0},
++ {0x8d13, 0x00, 0, 0},{0x8d14, 0x53, 0, 0},{0x8d15, 0x12, 0, 0},
++ {0x8d16, 0x05, 0, 0},{0x8d17, 0x16, 0, 0},{0x8d18, 0x80, 0, 0},
++ {0x8d19, 0x4e, 0, 0},{0x8d1a, 0x12, 0, 0},{0x8d1b, 0x06, 0, 0},
++ {0x8d1c, 0xdf, 0, 0},{0x8d1d, 0x80, 0, 0},{0x8d1e, 0x49, 0, 0},
++ {0x8d1f, 0x30, 0, 0},{0x8d20, 0x05, 0, 0},{0x8d21, 0x46, 0, 0},
++ {0x8d22, 0x20, 0, 0},{0x8d23, 0x07, 0, 0},{0x8d24, 0x43, 0, 0},
++ {0x8d25, 0x20, 0, 0},{0x8d26, 0x06, 0, 0},{0x8d27, 0x40, 0, 0},
++ {0x8d28, 0x12, 0, 0},{0x8d29, 0x15, 0, 0},{0x8d2a, 0x4c, 0, 0},
++ {0x8d2b, 0x80, 0, 0},{0x8d2c, 0x3b, 0, 0},{0x8d2d, 0x12, 0, 0},
++ {0x8d2e, 0x11, 0, 0},{0x8d2f, 0x7d, 0, 0},{0x8d30, 0x80, 0, 0},
++ {0x8d31, 0x36, 0, 0},{0x8d32, 0x20, 0, 0},{0x8d33, 0x07, 0, 0},
++ {0x8d34, 0x33, 0, 0},{0x8d35, 0x20, 0, 0},{0x8d36, 0x06, 0, 0},
++ {0x8d37, 0x30, 0, 0},{0x8d38, 0x12, 0, 0},{0x8d39, 0x15, 0, 0},
++ {0x8d3a, 0x5b, 0, 0},{0x8d3b, 0x80, 0, 0},{0x8d3c, 0x2b, 0, 0},
++ {0x8d3d, 0xe5, 0, 0},{0x8d3e, 0x7d, 0, 0},{0x8d3f, 0x64, 0, 0},
++ {0x8d40, 0x01, 0, 0},{0x8d41, 0x70, 0, 0},{0x8d42, 0x25, 0, 0},
++ {0x8d43, 0xd2, 0, 0},{0x8d44, 0x35, 0, 0},{0x8d45, 0x90, 0, 0},
++ {0x8d46, 0x50, 0, 0},{0x8d47, 0x82, 0, 0},{0x8d48, 0xe5, 0, 0},
++ {0x8d49, 0x73, 0, 0},{0x8d4a, 0xf0, 0, 0},{0x8d4b, 0xa3, 0, 0},
++ {0x8d4c, 0xe5, 0, 0},{0x8d4d, 0x74, 0, 0},{0x8d4e, 0xf0, 0, 0},
++ {0x8d4f, 0xa3, 0, 0},{0x8d50, 0xe5, 0, 0},{0x8d51, 0x75, 0, 0},
++ {0x8d52, 0xf0, 0, 0},{0x8d53, 0xa3, 0, 0},{0x8d54, 0xe5, 0, 0},
++ {0x8d55, 0x76, 0, 0},{0x8d56, 0xf0, 0, 0},{0x8d57, 0xc2, 0, 0},
++ {0x8d58, 0x35, 0, 0},{0x8d59, 0x80, 0, 0},{0x8d5a, 0x0d, 0, 0},
++ {0x8d5b, 0x90, 0, 0},{0x8d5c, 0x50, 0, 0},{0x8d5d, 0x82, 0, 0},
++ {0x8d5e, 0x30, 0, 0},{0x8d5f, 0x33, 0, 0},{0x8d60, 0x05, 0, 0},
++ {0x8d61, 0x74, 0, 0},{0x8d62, 0x55, 0, 0},{0x8d63, 0xf0, 0, 0},
++ {0x8d64, 0x80, 0, 0},{0x8d65, 0x02, 0, 0},{0x8d66, 0xe4, 0, 0},
++ {0x8d67, 0xf0, 0, 0},{0x8d68, 0x20, 0, 0},{0x8d69, 0x07, 0, 0},
++ {0x8d6a, 0x06, 0, 0},{0x8d6b, 0x30, 0, 0},{0x8d6c, 0x06, 0, 0},
++ {0x8d6d, 0x03, 0, 0},{0x8d6e, 0x30, 0, 0},{0x8d6f, 0x04, 0, 0},
++ {0x8d70, 0x05, 0, 0},{0x8d71, 0x90, 0, 0},{0x8d72, 0x30, 0, 0},
++ {0x8d73, 0x25, 0, 0},{0x8d74, 0xe4, 0, 0},{0x8d75, 0xf0, 0, 0},
++ {0x8d76, 0x22, 0, 0},{0x8d77, 0x30, 0, 0},{0x8d78, 0x04, 0, 0},
++ {0x8d79, 0x03, 0, 0},{0x8d7a, 0x02, 0, 0},{0x8d7b, 0x0e, 0, 0},
++ {0x8d7c, 0x62, 0, 0},{0x8d7d, 0xd2, 0, 0},{0x8d7e, 0x04, 0, 0},
++ {0x8d7f, 0xe5, 0, 0},{0x8d80, 0x7d, 0, 0},{0x8d81, 0xb4, 0, 0},
++ {0x8d82, 0x01, 0, 0},{0x8d83, 0x06, 0, 0},{0x8d84, 0x12, 0, 0},
++ {0x8d85, 0x15, 0, 0},{0x8d86, 0x2c, 0, 0},{0x8d87, 0x02, 0, 0},
++ {0x8d88, 0x0e, 0, 0},{0x8d89, 0x5b, 0, 0},{0x8d8a, 0xe5, 0, 0},
++ {0x8d8b, 0x7d, 0, 0},{0x8d8c, 0xb4, 0, 0},{0x8d8d, 0x02, 0, 0},
++ {0x8d8e, 0x06, 0, 0},{0x8d8f, 0x12, 0, 0},{0x8d90, 0x15, 0, 0},
++ {0x8d91, 0x3d, 0, 0},{0x8d92, 0x02, 0, 0},{0x8d93, 0x0e, 0, 0},
++ {0x8d94, 0x5b, 0, 0},{0x8d95, 0xe5, 0, 0},{0x8d96, 0x7d, 0, 0},
++ {0x8d97, 0xb4, 0, 0},{0x8d98, 0x03, 0, 0},{0x8d99, 0x05, 0, 0},
++ {0x8d9a, 0xe4, 0, 0},{0x8d9b, 0xf5, 0, 0},{0x8d9c, 0x0c, 0, 0},
++ {0x8d9d, 0x80, 0, 0},{0x8d9e, 0x08, 0, 0},{0x8d9f, 0xe5, 0, 0},
++ {0x8da0, 0x7d, 0, 0},{0x8da1, 0xb4, 0, 0},{0x8da2, 0x04, 0, 0},
++ {0x8da3, 0x09, 0, 0},{0x8da4, 0x85, 0, 0},{0x8da5, 0x7b, 0, 0},
++ {0x8da6, 0x0c, 0, 0},{0x8da7, 0x12, 0, 0},{0x8da8, 0x0f, 0, 0},
++ {0x8da9, 0x11, 0, 0},{0x8daa, 0x02, 0, 0},{0x8dab, 0x0e, 0, 0},
++ {0x8dac, 0x5b, 0, 0},{0x8dad, 0xe5, 0, 0},{0x8dae, 0x7d, 0, 0},
++ {0x8daf, 0x64, 0, 0},{0x8db0, 0x0f, 0, 0},{0x8db1, 0x70, 0, 0},
++ {0x8db2, 0x1f, 0, 0},{0x8db3, 0x12, 0, 0},{0x8db4, 0x02, 0, 0},
++ {0x8db5, 0xac, 0, 0},{0x8db6, 0x40, 0, 0},{0x8db7, 0x06, 0, 0},
++ {0x8db8, 0x7e, 0, 0},{0x8db9, 0x00, 0, 0},{0x8dba, 0x7f, 0, 0},
++ {0x8dbb, 0xff, 0, 0},{0x8dbc, 0x80, 0, 0},{0x8dbd, 0x04, 0, 0},
++ {0x8dbe, 0xae, 0, 0},{0x8dbf, 0x67, 0, 0},{0x8dc0, 0xaf, 0, 0},
++ {0x8dc1, 0x68, 0, 0},{0x8dc2, 0x12, 0, 0},{0x8dc3, 0x02, 0, 0},
++ {0x8dc4, 0x58, 0, 0},{0x8dc5, 0xc3, 0, 0},{0x8dc6, 0x33, 0, 0},
++ {0x8dc7, 0xce, 0, 0},{0x8dc8, 0x33, 0, 0},{0x8dc9, 0xce, 0, 0},
++ {0x8dca, 0xd8, 0, 0},{0x8dcb, 0xf9, 0, 0},{0x8dcc, 0x12, 0, 0},
++ {0x8dcd, 0x0e, 0, 0},{0x8dce, 0x63, 0, 0},{0x8dcf, 0x02, 0, 0},
++ {0x8dd0, 0x0e, 0, 0},{0x8dd1, 0x5b, 0, 0},{0x8dd2, 0xe5, 0, 0},
++ {0x8dd3, 0x7d, 0, 0},{0x8dd4, 0x64, 0, 0},{0x8dd5, 0x10, 0, 0},
++ {0x8dd6, 0x60, 0, 0},{0x8dd7, 0x03, 0, 0},{0x8dd8, 0x02, 0, 0},
++ {0x8dd9, 0x0e, 0, 0},{0x8dda, 0x5b, 0, 0},{0x8ddb, 0xf5, 0, 0},
++ {0x8ddc, 0x65, 0, 0},{0x8ddd, 0xf5, 0, 0},{0x8dde, 0x66, 0, 0},
++ {0x8ddf, 0xf5, 0, 0},{0x8de0, 0x67, 0, 0},{0x8de1, 0xab, 0, 0},
++ {0x8de2, 0x68, 0, 0},{0x8de3, 0xaa, 0, 0},{0x8de4, 0x67, 0, 0},
++ {0x8de5, 0xa9, 0, 0},{0x8de6, 0x66, 0, 0},{0x8de7, 0xa8, 0, 0},
++ {0x8de8, 0x65, 0, 0},{0x8de9, 0x12, 0, 0},{0x8dea, 0x01, 0, 0},
++ {0x8deb, 0xa0, 0, 0},{0x8dec, 0xfe, 0, 0},{0x8ded, 0xe4, 0, 0},
++ {0x8dee, 0xfc, 0, 0},{0x8def, 0xfd, 0, 0},{0x8df0, 0x12, 0, 0},
++ {0x8df1, 0x01, 0, 0},{0x8df2, 0xe7, 0, 0},{0x8df3, 0xe4, 0, 0},
++ {0x8df4, 0x7b, 0, 0},{0x8df5, 0xff, 0, 0},{0x8df6, 0xfa, 0, 0},
++ {0x8df7, 0xf9, 0, 0},{0x8df8, 0xf8, 0, 0},{0x8df9, 0x12, 0, 0},
++ {0x8dfa, 0x02, 0, 0},{0x8dfb, 0x6d, 0, 0},{0x8dfc, 0x85, 0, 0},
++ {0x8dfd, 0x49, 0, 0},{0x8dfe, 0x82, 0, 0},{0x8dff, 0x85, 0, 0},
++ {0x8e00, 0x48, 0, 0},{0x8e01, 0x83, 0, 0},{0x8e02, 0xe4, 0, 0},
++ {0x8e03, 0x93, 0, 0},{0x8e04, 0xff, 0, 0},{0x8e05, 0xe4, 0, 0},
++ {0x8e06, 0xfc, 0, 0},{0x8e07, 0xfd, 0, 0},{0x8e08, 0xfe, 0, 0},
++ {0x8e09, 0xe5, 0, 0},{0x8e0a, 0x68, 0, 0},{0x8e0b, 0x2f, 0, 0},
++ {0x8e0c, 0xf5, 0, 0},{0x8e0d, 0x68, 0, 0},{0x8e0e, 0xee, 0, 0},
++ {0x8e0f, 0x35, 0, 0},{0x8e10, 0x67, 0, 0},{0x8e11, 0xf5, 0, 0},
++ {0x8e12, 0x67, 0, 0},{0x8e13, 0xed, 0, 0},{0x8e14, 0x35, 0, 0},
++ {0x8e15, 0x66, 0, 0},{0x8e16, 0xf5, 0, 0},{0x8e17, 0x66, 0, 0},
++ {0x8e18, 0xec, 0, 0},{0x8e19, 0x35, 0, 0},{0x8e1a, 0x65, 0, 0},
++ {0x8e1b, 0xf5, 0, 0},{0x8e1c, 0x65, 0, 0},{0x8e1d, 0x12, 0, 0},
++ {0x8e1e, 0x02, 0, 0},{0x8e1f, 0xac, 0, 0},{0x8e20, 0x40, 0, 0},
++ {0x8e21, 0x04, 0, 0},{0x8e22, 0x7f, 0, 0},{0x8e23, 0xff, 0, 0},
++ {0x8e24, 0x80, 0, 0},{0x8e25, 0x04, 0, 0},{0x8e26, 0xae, 0, 0},
++ {0x8e27, 0x67, 0, 0},{0x8e28, 0xaf, 0, 0},{0x8e29, 0x68, 0, 0},
++ {0x8e2a, 0x12, 0, 0},{0x8e2b, 0x02, 0, 0},{0x8e2c, 0x58, 0, 0},
++ {0x8e2d, 0xc3, 0, 0},{0x8e2e, 0x33, 0, 0},{0x8e2f, 0xce, 0, 0},
++ {0x8e30, 0x33, 0, 0},{0x8e31, 0xce, 0, 0},{0x8e32, 0xd8, 0, 0},
++ {0x8e33, 0xf9, 0, 0},{0x8e34, 0x12, 0, 0},{0x8e35, 0x0e, 0, 0},
++ {0x8e36, 0x63, 0, 0},{0x8e37, 0xe4, 0, 0},{0x8e38, 0xf5, 0, 0},
++ {0x8e39, 0x66, 0, 0},{0x8e3a, 0xf5, 0, 0},{0x8e3b, 0x66, 0, 0},
++ {0x8e3c, 0xe5, 0, 0},{0x8e3d, 0x66, 0, 0},{0x8e3e, 0xd3, 0, 0},
++ {0x8e3f, 0x95, 0, 0},{0x8e40, 0x7b, 0, 0},{0x8e41, 0x50, 0, 0},
++ {0x8e42, 0x15, 0, 0},{0x8e43, 0xaf, 0, 0},{0x8e44, 0x66, 0, 0},
++ {0x8e45, 0xe5, 0, 0},{0x8e46, 0x49, 0, 0},{0x8e47, 0x2f, 0, 0},
++ {0x8e48, 0x12, 0, 0},{0x8e49, 0x02, 0, 0},{0x8e4a, 0x4f, 0, 0},
++ {0x8e4b, 0x93, 0, 0},{0x8e4c, 0xc3, 0, 0},{0x8e4d, 0x95, 0, 0},
++ {0x8e4e, 0x68, 0, 0},{0x8e4f, 0xe4, 0, 0},{0x8e50, 0x95, 0, 0},
++ {0x8e51, 0x67, 0, 0},{0x8e52, 0x50, 0, 0},{0x8e53, 0x04, 0, 0},
++ {0x8e54, 0x05, 0, 0},{0x8e55, 0x66, 0, 0},{0x8e56, 0x80, 0, 0},
++ {0x8e57, 0xe4, 0, 0},{0x8e58, 0x85, 0, 0},{0x8e59, 0x66, 0, 0},
++ {0x8e5a, 0x7c, 0, 0},{0x8e5b, 0x90, 0, 0},{0x8e5c, 0x30, 0, 0},
++ {0x8e5d, 0x25, 0, 0},{0x8e5e, 0xe4, 0, 0},{0x8e5f, 0xf0, 0, 0},
++ {0x8e60, 0xd2, 0, 0},{0x8e61, 0x34, 0, 0},{0x8e62, 0x22, 0, 0},
++ {0x8e63, 0xf5, 0, 0},{0x8e64, 0x68, 0, 0},{0x8e65, 0x8e, 0, 0},
++ {0x8e66, 0x67, 0, 0},{0x8e67, 0x85, 0, 0},{0x8e68, 0x67, 0, 0},
++ {0x8e69, 0x10, 0, 0},{0x8e6a, 0x85, 0, 0},{0x8e6b, 0x68, 0, 0},
++ {0x8e6c, 0x11, 0, 0},{0x8e6d, 0x12, 0, 0},{0x8e6e, 0x09, 0, 0},
++ {0x8e6f, 0xf8, 0, 0},{0x8e70, 0x22, 0, 0},{0x8e71, 0x12, 0, 0},
++ {0x8e72, 0x02, 0, 0},{0x8e73, 0x85, 0, 0},{0x8e74, 0xb5, 0, 0},
++ {0x8e75, 0x07, 0, 0},{0x8e76, 0x03, 0, 0},{0x8e77, 0xd3, 0, 0},
++ {0x8e78, 0x80, 0, 0},{0x8e79, 0x01, 0, 0},{0x8e7a, 0xc3, 0, 0},
++ {0x8e7b, 0x40, 0, 0},{0x8e7c, 0x03, 0, 0},{0x8e7d, 0x02, 0, 0},
++ {0x8e7e, 0x0f, 0, 0},{0x8e7f, 0x10, 0, 0},{0x8e80, 0x90, 0, 0},
++ {0x8e81, 0x30, 0, 0},{0x8e82, 0x04, 0, 0},{0x8e83, 0xe0, 0, 0},
++ {0x8e84, 0x44, 0, 0},{0x8e85, 0x20, 0, 0},{0x8e86, 0xf0, 0, 0},
++ {0x8e87, 0xa3, 0, 0},{0x8e88, 0xe0, 0, 0},{0x8e89, 0x44, 0, 0},
++ {0x8e8a, 0x40, 0, 0},{0x8e8b, 0xf0, 0, 0},{0x8e8c, 0x90, 0, 0},
++ {0x8e8d, 0x50, 0, 0},{0x8e8e, 0x25, 0, 0},{0x8e8f, 0xe0, 0, 0},
++ {0x8e90, 0x44, 0, 0},{0x8e91, 0x04, 0, 0},{0x8e92, 0xf0, 0, 0},
++ {0x8e93, 0x90, 0, 0},{0x8e94, 0x50, 0, 0},{0x8e95, 0x03, 0, 0},
++ {0x8e96, 0xe0, 0, 0},{0x8e97, 0x54, 0, 0},{0x8e98, 0xfd, 0, 0},
++ {0x8e99, 0xf0, 0, 0},{0x8e9a, 0x90, 0, 0},{0x8e9b, 0x50, 0, 0},
++ {0x8e9c, 0x27, 0, 0},{0x8e9d, 0xe0, 0, 0},{0x8e9e, 0x44, 0, 0},
++ {0x8e9f, 0x01, 0, 0},{0x8ea0, 0xf0, 0, 0},{0x8ea1, 0x90, 0, 0},
++ {0x8ea2, 0x50, 0, 0},{0x8ea3, 0x31, 0, 0},{0x8ea4, 0xe4, 0, 0},
++ {0x8ea5, 0xf0, 0, 0},{0x8ea6, 0x90, 0, 0},{0x8ea7, 0x50, 0, 0},
++ {0x8ea8, 0x33, 0, 0},{0x8ea9, 0xf0, 0, 0},{0x8eaa, 0x90, 0, 0},
++ {0x8eab, 0x30, 0, 0},{0x8eac, 0x1e, 0, 0},{0x8ead, 0x12, 0, 0},
++ {0x8eae, 0x01, 0, 0},{0x8eaf, 0xfb, 0, 0},{0x8eb0, 0x90, 0, 0},
++ {0x8eb1, 0x30, 0, 0},{0x8eb2, 0x18, 0, 0},{0x8eb3, 0x12, 0, 0},
++ {0x8eb4, 0x01, 0, 0},{0x8eb5, 0xfb, 0, 0},{0x8eb6, 0x90, 0, 0},
++ {0x8eb7, 0x30, 0, 0},{0x8eb8, 0x1b, 0, 0},{0x8eb9, 0x12, 0, 0},
++ {0x8eba, 0x01, 0, 0},{0x8ebb, 0xfb, 0, 0},{0x8ebc, 0xe0, 0, 0},
++ {0x8ebd, 0xf5, 0, 0},{0x8ebe, 0x25, 0, 0},{0x8ebf, 0x90, 0, 0},
++ {0x8ec0, 0x30, 0, 0},{0x8ec1, 0x18, 0, 0},{0x8ec2, 0xe0, 0, 0},
++ {0x8ec3, 0xf5, 0, 0},{0x8ec4, 0x21, 0, 0},{0x8ec5, 0x90, 0, 0},
++ {0x8ec6, 0x60, 0, 0},{0x8ec7, 0x00, 0, 0},{0x8ec8, 0x74, 0, 0},
++ {0x8ec9, 0xf5, 0, 0},{0x8eca, 0xf0, 0, 0},{0x8ecb, 0x90, 0, 0},
++ {0x8ecc, 0x3f, 0, 0},{0x8ecd, 0x01, 0, 0},{0x8ece, 0xe4, 0, 0},
++ {0x8ecf, 0xf0, 0, 0},{0x8ed0, 0xa3, 0, 0},{0x8ed1, 0xf0, 0, 0},
++ {0x8ed2, 0x90, 0, 0},{0x8ed3, 0x3f, 0, 0},{0x8ed4, 0x01, 0, 0},
++ {0x8ed5, 0xe0, 0, 0},{0x8ed6, 0x44, 0, 0},{0x8ed7, 0x08, 0, 0},
++ {0x8ed8, 0xf0, 0, 0},{0x8ed9, 0xe0, 0, 0},{0x8eda, 0x44, 0, 0},
++ {0x8edb, 0x20, 0, 0},{0x8edc, 0xf0, 0, 0},{0x8edd, 0x90, 0, 0},
++ {0x8ede, 0x3f, 0, 0},{0x8edf, 0x05, 0, 0},{0x8ee0, 0x74, 0, 0},
++ {0x8ee1, 0x30, 0, 0},{0x8ee2, 0xf0, 0, 0},{0x8ee3, 0xa3, 0, 0},
++ {0x8ee4, 0x74, 0, 0},{0x8ee5, 0x24, 0, 0},{0x8ee6, 0xf0, 0, 0},
++ {0x8ee7, 0x90, 0, 0},{0x8ee8, 0x3f, 0, 0},{0x8ee9, 0x0b, 0, 0},
++ {0x8eea, 0xe0, 0, 0},{0x8eeb, 0x44, 0, 0},{0x8eec, 0x0f, 0, 0},
++ {0x8eed, 0xf0, 0, 0},{0x8eee, 0x90, 0, 0},{0x8eef, 0x3f, 0, 0},
++ {0x8ef0, 0x01, 0, 0},{0x8ef1, 0xe0, 0, 0},{0x8ef2, 0x44, 0, 0},
++ {0x8ef3, 0x02, 0, 0},{0x8ef4, 0xf0, 0, 0},{0x8ef5, 0xc2, 0, 0},
++ {0x8ef6, 0x8c, 0, 0},{0x8ef7, 0x75, 0, 0},{0x8ef8, 0x89, 0, 0},
++ {0x8ef9, 0x03, 0, 0},{0x8efa, 0x75, 0, 0},{0x8efb, 0xa8, 0, 0},
++ {0x8efc, 0x07, 0, 0},{0x8efd, 0x75, 0, 0},{0x8efe, 0xb8, 0, 0},
++ {0x8eff, 0x04, 0, 0},{0x8f00, 0xe4, 0, 0},{0x8f01, 0xf5, 0, 0},
++ {0x8f02, 0xd8, 0, 0},{0x8f03, 0xf5, 0, 0},{0x8f04, 0xe8, 0, 0},
++ {0x8f05, 0x90, 0, 0},{0x8f06, 0x30, 0, 0},{0x8f07, 0x01, 0, 0},
++ {0x8f08, 0xe0, 0, 0},{0x8f09, 0x44, 0, 0},{0x8f0a, 0x40, 0, 0},
++ {0x8f0b, 0xf0, 0, 0},{0x8f0c, 0xe0, 0, 0},{0x8f0d, 0x54, 0, 0},
++ {0x8f0e, 0xbf, 0, 0},{0x8f0f, 0xf0, 0, 0},{0x8f10, 0x22, 0, 0},
++ {0x8f11, 0xe5, 0, 0},{0x8f12, 0x0c, 0, 0},{0x8f13, 0xd3, 0, 0},
++ {0x8f14, 0x95, 0, 0},{0x8f15, 0x7b, 0, 0},{0x8f16, 0x40, 0, 0},
++ {0x8f17, 0x01, 0, 0},{0x8f18, 0x22, 0, 0},{0x8f19, 0xe5, 0, 0},
++ {0x8f1a, 0x49, 0, 0},{0x8f1b, 0x25, 0, 0},{0x8f1c, 0x0c, 0, 0},
++ {0x8f1d, 0x12, 0, 0},{0x8f1e, 0x02, 0, 0},{0x8f1f, 0x4f, 0, 0},
++ {0x8f20, 0x93, 0, 0},{0x8f21, 0x75, 0, 0},{0x8f22, 0x0d, 0, 0},
++ {0x8f23, 0x00, 0, 0},{0x8f24, 0xf5, 0, 0},{0x8f25, 0x0e, 0, 0},
++ {0x8f26, 0x45, 0, 0},{0x8f27, 0x0d, 0, 0},{0x8f28, 0x70, 0, 0},
++ {0x8f29, 0x05, 0, 0},{0x8f2a, 0x85, 0, 0},{0x8f2b, 0x64, 0, 0},
++ {0x8f2c, 0x0f, 0, 0},{0x8f2d, 0x80, 0, 0},{0x8f2e, 0x1b, 0, 0},
++ {0x8f2f, 0x12, 0, 0},{0x8f30, 0x02, 0, 0},{0x8f31, 0x9b, 0, 0},
++ {0x8f32, 0xc3, 0, 0},{0x8f33, 0x33, 0, 0},{0x8f34, 0xce, 0, 0},
++ {0x8f35, 0x33, 0, 0},{0x8f36, 0xce, 0, 0},{0x8f37, 0xd8, 0, 0},
++ {0x8f38, 0xf9, 0, 0},{0x8f39, 0xf5, 0, 0},{0x8f3a, 0x0e, 0, 0},
++ {0x8f3b, 0x8e, 0, 0},{0x8f3c, 0x0d, 0, 0},{0x8f3d, 0x85, 0, 0},
++ {0x8f3e, 0x0d, 0, 0},{0x8f3f, 0x10, 0, 0},{0x8f40, 0xf5, 0, 0},
++ {0x8f41, 0x11, 0, 0},{0x8f42, 0x12, 0, 0},{0x8f43, 0x09, 0, 0},
++ {0x8f44, 0xf8, 0, 0},{0x8f45, 0x30, 0, 0},{0x8f46, 0x33, 0, 0},
++ {0x8f47, 0x63, 0, 0},{0x8f48, 0xc3, 0, 0},{0x8f49, 0x22, 0, 0},
++ {0x8f4a, 0xe5, 0, 0},{0x8f4b, 0x0f, 0, 0},{0x8f4c, 0xd3, 0, 0},
++ {0x8f4d, 0x94, 0, 0},{0x8f4e, 0x10, 0, 0},{0x8f4f, 0x40, 0, 0},
++ {0x8f50, 0x33, 0, 0},{0x8f51, 0xe5, 0, 0},{0x8f52, 0x0f, 0, 0},
++ {0x8f53, 0xd3, 0, 0},{0x8f54, 0x94, 0, 0},{0x8f55, 0x60, 0, 0},
++ {0x8f56, 0x40, 0, 0},{0x8f57, 0x05, 0, 0},{0x8f58, 0x75, 0, 0},
++ {0x8f59, 0x0f, 0, 0},{0x8f5a, 0x58, 0, 0},{0x8f5b, 0x80, 0, 0},
++ {0x8f5c, 0x11, 0, 0},{0x8f5d, 0xe5, 0, 0},{0x8f5e, 0x0f, 0, 0},
++ {0x8f5f, 0xd3, 0, 0},{0x8f60, 0x94, 0, 0},{0x8f61, 0x40, 0, 0},
++ {0x8f62, 0x40, 0, 0},{0x8f63, 0x04, 0, 0},{0x8f64, 0x74, 0, 0},
++ {0x8f65, 0xf0, 0, 0},{0x8f66, 0x80, 0, 0},{0x8f67, 0x02, 0, 0},
++ {0x8f68, 0x74, 0, 0},{0x8f69, 0xf8, 0, 0},{0x8f6a, 0x25, 0, 0},
++ {0x8f6b, 0x0f, 0, 0},{0x8f6c, 0xf5, 0, 0},{0x8f6d, 0x0f, 0, 0},
++ {0x8f6e, 0x75, 0, 0},{0x8f6f, 0x0d, 0, 0},{0x8f70, 0x00, 0, 0},
++ {0x8f71, 0x85, 0, 0},{0x8f72, 0x0f, 0, 0},{0x8f73, 0x0e, 0, 0},
++ {0x8f74, 0x12, 0, 0},{0x8f75, 0x02, 0, 0},{0x8f76, 0x9b, 0, 0},
++ {0x8f77, 0xc3, 0, 0},{0x8f78, 0x33, 0, 0},{0x8f79, 0xce, 0, 0},
++ {0x8f7a, 0x33, 0, 0},{0x8f7b, 0xce, 0, 0},{0x8f7c, 0xd8, 0, 0},
++ {0x8f7d, 0xf9, 0, 0},{0x8f7e, 0xf5, 0, 0},{0x8f7f, 0x0e, 0, 0},
++ {0x8f80, 0x8e, 0, 0},{0x8f81, 0x0d, 0, 0},{0x8f82, 0x80, 0, 0},
++ {0x8f83, 0x0a, 0, 0},{0x8f84, 0xe4, 0, 0},{0x8f85, 0xf5, 0, 0},
++ {0x8f86, 0x0f, 0, 0},{0x8f87, 0x75, 0, 0},{0x8f88, 0x0d, 0, 0},
++ {0x8f89, 0x80, 0, 0},{0x8f8a, 0xf5, 0, 0},{0x8f8b, 0x0e, 0, 0},
++ {0x8f8c, 0xf5, 0, 0},{0x8f8d, 0x64, 0, 0},{0x8f8e, 0x85, 0, 0},
++ {0x8f8f, 0x0d, 0, 0},{0x8f90, 0x10, 0, 0},{0x8f91, 0x85, 0, 0},
++ {0x8f92, 0x0e, 0, 0},{0x8f93, 0x11, 0, 0},{0x8f94, 0x12, 0, 0},
++ {0x8f95, 0x09, 0, 0},{0x8f96, 0xf8, 0, 0},{0x8f97, 0x30, 0, 0},
++ {0x8f98, 0x33, 0, 0},{0x8f99, 0x02, 0, 0},{0x8f9a, 0xc3, 0, 0},
++ {0x8f9b, 0x22, 0, 0},{0x8f9c, 0xe5, 0, 0},{0x8f9d, 0x0f, 0, 0},
++ {0x8f9e, 0x60, 0, 0},{0x8f9f, 0x0b, 0, 0},{0x8fa0, 0x75, 0, 0},
++ {0x8fa1, 0x10, 0, 0},{0x8fa2, 0x00, 0, 0},{0x8fa3, 0x75, 0, 0},
++ {0x8fa4, 0x11, 0, 0},{0x8fa5, 0x32, 0, 0},{0x8fa6, 0x12, 0, 0},
++ {0x8fa7, 0x14, 0, 0},{0x8fa8, 0xcd, 0, 0},{0x8fa9, 0x80, 0, 0},
++ {0x8faa, 0x9f, 0, 0},{0x8fab, 0x85, 0, 0},{0x8fac, 0x0c, 0, 0},
++ {0x8fad, 0x7c, 0, 0},{0x8fae, 0xd3, 0, 0},{0x8faf, 0x22, 0, 0},
++ {0x8fb0, 0x30, 0, 0},{0x8fb1, 0x3c, 0, 0},{0x8fb2, 0x09, 0, 0},
++ {0x8fb3, 0x30, 0, 0},{0x8fb4, 0x20, 0, 0},{0x8fb5, 0x06, 0, 0},
++ {0x8fb6, 0xae, 0, 0},{0x8fb7, 0x56, 0, 0},{0x8fb8, 0xaf, 0, 0},
++ {0x8fb9, 0x57, 0, 0},{0x8fba, 0x80, 0, 0},{0x8fbb, 0x04, 0, 0},
++ {0x8fbc, 0xae, 0, 0},{0x8fbd, 0x69, 0, 0},{0x8fbe, 0xaf, 0, 0},
++ {0x8fbf, 0x6a, 0, 0},{0x8fc0, 0x8e, 0, 0},{0x8fc1, 0x56, 0, 0},
++ {0x8fc2, 0x8f, 0, 0},{0x8fc3, 0x57, 0, 0},{0x8fc4, 0x30, 0, 0},
++ {0x8fc5, 0x3c, 0, 0},{0x8fc6, 0x09, 0, 0},{0x8fc7, 0x30, 0, 0},
++ {0x8fc8, 0x21, 0, 0},{0x8fc9, 0x06, 0, 0},{0x8fca, 0xae, 0, 0},
++ {0x8fcb, 0x58, 0, 0},{0x8fcc, 0xaf, 0, 0},{0x8fcd, 0x59, 0, 0},
++ {0x8fce, 0x80, 0, 0},{0x8fcf, 0x04, 0, 0},{0x8fd0, 0xae, 0, 0},
++ {0x8fd1, 0x6b, 0, 0},{0x8fd2, 0xaf, 0, 0},{0x8fd3, 0x6c, 0, 0},
++ {0x8fd4, 0x8e, 0, 0},{0x8fd5, 0x58, 0, 0},{0x8fd6, 0x8f, 0, 0},
++ {0x8fd7, 0x59, 0, 0},{0x8fd8, 0x30, 0, 0},{0x8fd9, 0x3c, 0, 0},
++ {0x8fda, 0x09, 0, 0},{0x8fdb, 0x30, 0, 0},{0x8fdc, 0x22, 0, 0},
++ {0x8fdd, 0x06, 0, 0},{0x8fde, 0xae, 0, 0},{0x8fdf, 0x5a, 0, 0},
++ {0x8fe0, 0xaf, 0, 0},{0x8fe1, 0x5b, 0, 0},{0x8fe2, 0x80, 0, 0},
++ {0x8fe3, 0x04, 0, 0},{0x8fe4, 0xae, 0, 0},{0x8fe5, 0x6d, 0, 0},
++ {0x8fe6, 0xaf, 0, 0},{0x8fe7, 0x6e, 0, 0},{0x8fe8, 0x8e, 0, 0},
++ {0x8fe9, 0x5a, 0, 0},{0x8fea, 0x8f, 0, 0},{0x8feb, 0x5b, 0, 0},
++ {0x8fec, 0x30, 0, 0},{0x8fed, 0x3c, 0, 0},{0x8fee, 0x09, 0, 0},
++ {0x8fef, 0x30, 0, 0},{0x8ff0, 0x23, 0, 0},{0x8ff1, 0x06, 0, 0},
++ {0x8ff2, 0xae, 0, 0},{0x8ff3, 0x5c, 0, 0},{0x8ff4, 0xaf, 0, 0},
++ {0x8ff5, 0x5d, 0, 0},{0x8ff6, 0x80, 0, 0},{0x8ff7, 0x04, 0, 0},
++ {0x8ff8, 0xae, 0, 0},{0x8ff9, 0x6f, 0, 0},{0x8ffa, 0xaf, 0, 0},
++ {0x8ffb, 0x70, 0, 0},{0x8ffc, 0x8e, 0, 0},{0x8ffd, 0x5c, 0, 0},
++ {0x8ffe, 0x8f, 0, 0},{0x8fff, 0x5d, 0, 0},{0x9000, 0x30, 0, 0},
++ {0x9001, 0x3c, 0, 0},{0x9002, 0x09, 0, 0},{0x9003, 0x30, 0, 0},
++ {0x9004, 0x24, 0, 0},{0x9005, 0x06, 0, 0},{0x9006, 0xae, 0, 0},
++ {0x9007, 0x5e, 0, 0},{0x9008, 0xaf, 0, 0},{0x9009, 0x5f, 0, 0},
++ {0x900a, 0x80, 0, 0},{0x900b, 0x04, 0, 0},{0x900c, 0xae, 0, 0},
++ {0x900d, 0x71, 0, 0},{0x900e, 0xaf, 0, 0},{0x900f, 0x72, 0, 0},
++ {0x9010, 0x8e, 0, 0},{0x9011, 0x5e, 0, 0},{0x9012, 0x8f, 0, 0},
++ {0x9013, 0x5f, 0, 0},{0x9014, 0x30, 0, 0},{0x9015, 0x3c, 0, 0},
++ {0x9016, 0x09, 0, 0},{0x9017, 0x30, 0, 0},{0x9018, 0x25, 0, 0},
++ {0x9019, 0x06, 0, 0},{0x901a, 0xae, 0, 0},{0x901b, 0x60, 0, 0},
++ {0x901c, 0xaf, 0, 0},{0x901d, 0x61, 0, 0},{0x901e, 0x80, 0, 0},
++ {0x901f, 0x04, 0, 0},{0x9020, 0xae, 0, 0},{0x9021, 0x73, 0, 0},
++ {0x9022, 0xaf, 0, 0},{0x9023, 0x74, 0, 0},{0x9024, 0x8e, 0, 0},
++ {0x9025, 0x60, 0, 0},{0x9026, 0x8f, 0, 0},{0x9027, 0x61, 0, 0},
++ {0x9028, 0x30, 0, 0},{0x9029, 0x3c, 0, 0},{0x902a, 0x09, 0, 0},
++ {0x902b, 0x30, 0, 0},{0x902c, 0x26, 0, 0},{0x902d, 0x06, 0, 0},
++ {0x902e, 0xae, 0, 0},{0x902f, 0x62, 0, 0},{0x9030, 0xaf, 0, 0},
++ {0x9031, 0x63, 0, 0},{0x9032, 0x80, 0, 0},{0x9033, 0x04, 0, 0},
++ {0x9034, 0xae, 0, 0},{0x9035, 0x75, 0, 0},{0x9036, 0xaf, 0, 0},
++ {0x9037, 0x76, 0, 0},{0x9038, 0x8e, 0, 0},{0x9039, 0x62, 0, 0},
++ {0x903a, 0x8f, 0, 0},{0x903b, 0x63, 0, 0},{0x903c, 0x22, 0, 0},
++ {0x903d, 0xd3, 0, 0},{0x903e, 0xe5, 0, 0},{0x903f, 0x57, 0, 0},
++ {0x9040, 0x95, 0, 0},{0x9041, 0x6a, 0, 0},{0x9042, 0xe5, 0, 0},
++ {0x9043, 0x56, 0, 0},{0x9044, 0x95, 0, 0},{0x9045, 0x69, 0, 0},
++ {0x9046, 0x40, 0, 0},{0x9047, 0x03, 0, 0},{0x9048, 0xd3, 0, 0},
++ {0x9049, 0x80, 0, 0},{0x904a, 0x01, 0, 0},{0x904b, 0xc3, 0, 0},
++ {0x904c, 0x92, 0, 0},{0x904d, 0x20, 0, 0},{0x904e, 0xd3, 0, 0},
++ {0x904f, 0xe5, 0, 0},{0x9050, 0x59, 0, 0},{0x9051, 0x95, 0, 0},
++ {0x9052, 0x6c, 0, 0},{0x9053, 0xe5, 0, 0},{0x9054, 0x58, 0, 0},
++ {0x9055, 0x95, 0, 0},{0x9056, 0x6b, 0, 0},{0x9057, 0x40, 0, 0},
++ {0x9058, 0x03, 0, 0},{0x9059, 0xd3, 0, 0},{0x905a, 0x80, 0, 0},
++ {0x905b, 0x01, 0, 0},{0x905c, 0xc3, 0, 0},{0x905d, 0x92, 0, 0},
++ {0x905e, 0x21, 0, 0},{0x905f, 0xd3, 0, 0},{0x9060, 0xe5, 0, 0},
++ {0x9061, 0x5b, 0, 0},{0x9062, 0x95, 0, 0},{0x9063, 0x6e, 0, 0},
++ {0x9064, 0xe5, 0, 0},{0x9065, 0x5a, 0, 0},{0x9066, 0x95, 0, 0},
++ {0x9067, 0x6d, 0, 0},{0x9068, 0x40, 0, 0},{0x9069, 0x03, 0, 0},
++ {0x906a, 0xd3, 0, 0},{0x906b, 0x80, 0, 0},{0x906c, 0x01, 0, 0},
++ {0x906d, 0xc3, 0, 0},{0x906e, 0x92, 0, 0},{0x906f, 0x22, 0, 0},
++ {0x9070, 0xd3, 0, 0},{0x9071, 0xe5, 0, 0},{0x9072, 0x5d, 0, 0},
++ {0x9073, 0x95, 0, 0},{0x9074, 0x70, 0, 0},{0x9075, 0xe5, 0, 0},
++ {0x9076, 0x5c, 0, 0},{0x9077, 0x95, 0, 0},{0x9078, 0x6f, 0, 0},
++ {0x9079, 0x40, 0, 0},{0x907a, 0x03, 0, 0},{0x907b, 0xd3, 0, 0},
++ {0x907c, 0x80, 0, 0},{0x907d, 0x01, 0, 0},{0x907e, 0xc3, 0, 0},
++ {0x907f, 0x92, 0, 0},{0x9080, 0x23, 0, 0},{0x9081, 0xd3, 0, 0},
++ {0x9082, 0xe5, 0, 0},{0x9083, 0x5f, 0, 0},{0x9084, 0x95, 0, 0},
++ {0x9085, 0x72, 0, 0},{0x9086, 0xe5, 0, 0},{0x9087, 0x5e, 0, 0},
++ {0x9088, 0x95, 0, 0},{0x9089, 0x71, 0, 0},{0x908a, 0x40, 0, 0},
++ {0x908b, 0x03, 0, 0},{0x908c, 0xd3, 0, 0},{0x908d, 0x80, 0, 0},
++ {0x908e, 0x01, 0, 0},{0x908f, 0xc3, 0, 0},{0x9090, 0x92, 0, 0},
++ {0x9091, 0x24, 0, 0},{0x9092, 0xd3, 0, 0},{0x9093, 0xe5, 0, 0},
++ {0x9094, 0x61, 0, 0},{0x9095, 0x95, 0, 0},{0x9096, 0x74, 0, 0},
++ {0x9097, 0xe5, 0, 0},{0x9098, 0x60, 0, 0},{0x9099, 0x95, 0, 0},
++ {0x909a, 0x73, 0, 0},{0x909b, 0x40, 0, 0},{0x909c, 0x03, 0, 0},
++ {0x909d, 0xd3, 0, 0},{0x909e, 0x80, 0, 0},{0x909f, 0x01, 0, 0},
++ {0x90a0, 0xc3, 0, 0},{0x90a1, 0x92, 0, 0},{0x90a2, 0x25, 0, 0},
++ {0x90a3, 0xd3, 0, 0},{0x90a4, 0xe5, 0, 0},{0x90a5, 0x63, 0, 0},
++ {0x90a6, 0x95, 0, 0},{0x90a7, 0x76, 0, 0},{0x90a8, 0xe5, 0, 0},
++ {0x90a9, 0x62, 0, 0},{0x90aa, 0x95, 0, 0},{0x90ab, 0x75, 0, 0},
++ {0x90ac, 0x40, 0, 0},{0x90ad, 0x03, 0, 0},{0x90ae, 0xd3, 0, 0},
++ {0x90af, 0x80, 0, 0},{0x90b0, 0x01, 0, 0},{0x90b1, 0xc3, 0, 0},
++ {0x90b2, 0x92, 0, 0},{0x90b3, 0x26, 0, 0},{0x90b4, 0x22, 0, 0},
++ {0x90b5, 0xe5, 0, 0},{0x90b6, 0x0a, 0, 0},{0x90b7, 0x70, 0, 0},
++ {0x90b8, 0x04, 0, 0},{0x90b9, 0x7a, 0, 0},{0x90ba, 0x11, 0, 0},
++ {0x90bb, 0x7b, 0, 0},{0x90bc, 0xee, 0, 0},{0x90bd, 0xe5, 0, 0},
++ {0x90be, 0x0a, 0, 0},{0x90bf, 0xb4, 0, 0},{0x90c0, 0x01, 0, 0},
++ {0x90c1, 0x04, 0, 0},{0x90c2, 0x7a, 0, 0},{0x90c3, 0x12, 0, 0},
++ {0x90c4, 0x7b, 0, 0},{0x90c5, 0x02, 0, 0},{0x90c6, 0xe5, 0, 0},
++ {0x90c7, 0x0a, 0, 0},{0x90c8, 0xb4, 0, 0},{0x90c9, 0x02, 0, 0},
++ {0x90ca, 0x04, 0, 0},{0x90cb, 0x7a, 0, 0},{0x90cc, 0x12, 0, 0},
++ {0x90cd, 0x7b, 0, 0},{0x90ce, 0x16, 0, 0},{0x90cf, 0x8b, 0, 0},
++ {0x90d0, 0x82, 0, 0},{0x90d1, 0x8a, 0, 0},{0x90d2, 0x83, 0, 0},
++ {0x90d3, 0x12, 0, 0},{0x90d4, 0x09, 0, 0},{0x90d5, 0xc2, 0, 0},
++ {0x90d6, 0x8f, 0, 0},{0x90d7, 0x37, 0, 0},{0x90d8, 0x8e, 0, 0},
++ {0x90d9, 0x36, 0, 0},{0x90da, 0x8d, 0, 0},{0x90db, 0x35, 0, 0},
++ {0x90dc, 0x8c, 0, 0},{0x90dd, 0x34, 0, 0},{0x90de, 0xe5, 0, 0},
++ {0x90df, 0x82, 0, 0},{0x90e0, 0x24, 0, 0},{0x90e1, 0x04, 0, 0},
++ {0x90e2, 0xf5, 0, 0},{0x90e3, 0x82, 0, 0},{0x90e4, 0xe4, 0, 0},
++ {0x90e5, 0x35, 0, 0},{0x90e6, 0x83, 0, 0},{0x90e7, 0xf5, 0, 0},
++ {0x90e8, 0x83, 0, 0},{0x90e9, 0x12, 0, 0},{0x90ea, 0x09, 0, 0},
++ {0x90eb, 0xc2, 0, 0},{0x90ec, 0x8f, 0, 0},{0x90ed, 0x3b, 0, 0},
++ {0x90ee, 0x8e, 0, 0},{0x90ef, 0x3a, 0, 0},{0x90f0, 0x8d, 0, 0},
++ {0x90f1, 0x39, 0, 0},{0x90f2, 0x8c, 0, 0},{0x90f3, 0x38, 0, 0},
++ {0x90f4, 0xeb, 0, 0},{0x90f5, 0x24, 0, 0},{0x90f6, 0x08, 0, 0},
++ {0x90f7, 0x12, 0, 0},{0x90f8, 0x02, 0, 0},{0x90f9, 0x2f, 0, 0},
++ {0x90fa, 0x12, 0, 0},{0x90fb, 0x01, 0, 0},{0x90fc, 0x97, 0, 0},
++ {0x90fd, 0xeb, 0, 0},{0x90fe, 0x24, 0, 0},{0x90ff, 0x0c, 0, 0},
++ {0x9100, 0x12, 0, 0},{0x9101, 0x02, 0, 0},{0x9102, 0x2f, 0, 0},
++ {0x9103, 0x8f, 0, 0},{0x9104, 0x43, 0, 0},{0x9105, 0x8e, 0, 0},
++ {0x9106, 0x42, 0, 0},{0x9107, 0x8d, 0, 0},{0x9108, 0x41, 0, 0},
++ {0x9109, 0x8c, 0, 0},{0x910a, 0x40, 0, 0},{0x910b, 0xeb, 0, 0},
++ {0x910c, 0x24, 0, 0},{0x910d, 0x10, 0, 0},{0x910e, 0x12, 0, 0},
++ {0x910f, 0x02, 0, 0},{0x9110, 0x2f, 0, 0},{0x9111, 0x8f, 0, 0},
++ {0x9112, 0x47, 0, 0},{0x9113, 0x8e, 0, 0},{0x9114, 0x46, 0, 0},
++ {0x9115, 0x8d, 0, 0},{0x9116, 0x45, 0, 0},{0x9117, 0x8c, 0, 0},
++ {0x9118, 0x44, 0, 0},{0x9119, 0x22, 0, 0},{0x911a, 0x30, 0, 0},
++ {0x911b, 0x3c, 0, 0},{0x911c, 0x07, 0, 0},{0x911d, 0x30, 0, 0},
++ {0x911e, 0x20, 0, 0},{0x911f, 0x04, 0, 0},{0x9120, 0xaf, 0, 0},
++ {0x9121, 0x4a, 0, 0},{0x9122, 0x80, 0, 0},{0x9123, 0x02, 0, 0},
++ {0x9124, 0xaf, 0, 0},{0x9125, 0x7c, 0, 0},{0x9126, 0x8f, 0, 0},
++ {0x9127, 0x4a, 0, 0},{0x9128, 0x30, 0, 0},{0x9129, 0x3c, 0, 0},
++ {0x912a, 0x07, 0, 0},{0x912b, 0x30, 0, 0},{0x912c, 0x21, 0, 0},
++ {0x912d, 0x04, 0, 0},{0x912e, 0xaf, 0, 0},{0x912f, 0x4b, 0, 0},
++ {0x9130, 0x80, 0, 0},{0x9131, 0x02, 0, 0},{0x9132, 0xaf, 0, 0},
++ {0x9133, 0x7c, 0, 0},{0x9134, 0x8f, 0, 0},{0x9135, 0x4b, 0, 0},
++ {0x9136, 0x30, 0, 0},{0x9137, 0x3c, 0, 0},{0x9138, 0x07, 0, 0},
++ {0x9139, 0x30, 0, 0},{0x913a, 0x22, 0, 0},{0x913b, 0x04, 0, 0},
++ {0x913c, 0xaf, 0, 0},{0x913d, 0x4c, 0, 0},{0x913e, 0x80, 0, 0},
++ {0x913f, 0x02, 0, 0},{0x9140, 0xaf, 0, 0},{0x9141, 0x7c, 0, 0},
++ {0x9142, 0x8f, 0, 0},{0x9143, 0x4c, 0, 0},{0x9144, 0x30, 0, 0},
++ {0x9145, 0x3c, 0, 0},{0x9146, 0x07, 0, 0},{0x9147, 0x30, 0, 0},
++ {0x9148, 0x23, 0, 0},{0x9149, 0x04, 0, 0},{0x914a, 0xaf, 0, 0},
++ {0x914b, 0x4d, 0, 0},{0x914c, 0x80, 0, 0},{0x914d, 0x02, 0, 0},
++ {0x914e, 0xaf, 0, 0},{0x914f, 0x7c, 0, 0},{0x9150, 0x8f, 0, 0},
++ {0x9151, 0x4d, 0, 0},{0x9152, 0x30, 0, 0},{0x9153, 0x3c, 0, 0},
++ {0x9154, 0x07, 0, 0},{0x9155, 0x30, 0, 0},{0x9156, 0x24, 0, 0},
++ {0x9157, 0x04, 0, 0},{0x9158, 0xaf, 0, 0},{0x9159, 0x4e, 0, 0},
++ {0x915a, 0x80, 0, 0},{0x915b, 0x02, 0, 0},{0x915c, 0xaf, 0, 0},
++ {0x915d, 0x7c, 0, 0},{0x915e, 0x8f, 0, 0},{0x915f, 0x4e, 0, 0},
++ {0x9160, 0x30, 0, 0},{0x9161, 0x3c, 0, 0},{0x9162, 0x07, 0, 0},
++ {0x9163, 0x30, 0, 0},{0x9164, 0x25, 0, 0},{0x9165, 0x04, 0, 0},
++ {0x9166, 0xaf, 0, 0},{0x9167, 0x4f, 0, 0},{0x9168, 0x80, 0, 0},
++ {0x9169, 0x02, 0, 0},{0x916a, 0xaf, 0, 0},{0x916b, 0x7c, 0, 0},
++ {0x916c, 0x8f, 0, 0},{0x916d, 0x4f, 0, 0},{0x916e, 0x30, 0, 0},
++ {0x916f, 0x3c, 0, 0},{0x9170, 0x07, 0, 0},{0x9171, 0x30, 0, 0},
++ {0x9172, 0x26, 0, 0},{0x9173, 0x04, 0, 0},{0x9174, 0xaf, 0, 0},
++ {0x9175, 0x50, 0, 0},{0x9176, 0x80, 0, 0},{0x9177, 0x02, 0, 0},
++ {0x9178, 0xaf, 0, 0},{0x9179, 0x7c, 0, 0},{0x917a, 0x8f, 0, 0},
++ {0x917b, 0x50, 0, 0},{0x917c, 0x22, 0, 0},{0x917d, 0xe5, 0, 0},
++ {0x917e, 0x7d, 0, 0},{0x917f, 0x64, 0, 0},{0x9180, 0x01, 0, 0},
++ {0x9181, 0x70, 0, 0},{0x9182, 0x47, 0, 0},{0x9183, 0xe5, 0, 0},
++ {0x9184, 0x49, 0, 0},{0x9185, 0x25, 0, 0},{0x9186, 0x7c, 0, 0},
++ {0x9187, 0x12, 0, 0},{0x9188, 0x01, 0, 0},{0x9189, 0xa4, 0, 0},
++ {0x918a, 0xfe, 0, 0},{0x918b, 0xe4, 0, 0},{0x918c, 0x8f, 0, 0},
++ {0x918d, 0x68, 0, 0},{0x918e, 0x8e, 0, 0},{0x918f, 0x67, 0, 0},
++ {0x9190, 0xf5, 0, 0},{0x9191, 0x66, 0, 0},{0x9192, 0xf5, 0, 0},
++ {0x9193, 0x65, 0, 0},{0x9194, 0x12, 0, 0},{0x9195, 0x01, 0, 0},
++ {0x9196, 0xf2, 0, 0},{0x9197, 0x7b, 0, 0},{0x9198, 0xff, 0, 0},
++ {0x9199, 0xfa, 0, 0},{0x919a, 0xf9, 0, 0},{0x919b, 0xf8, 0, 0},
++ {0x919c, 0x12, 0, 0},{0x919d, 0x01, 0, 0},{0x919e, 0xe7, 0, 0},
++ {0x919f, 0xc0, 0, 0},{0x91a0, 0x05, 0, 0},{0x91a1, 0xc0, 0, 0},
++ {0x91a2, 0x06, 0, 0},{0x91a3, 0xc0, 0, 0},{0x91a4, 0x07, 0, 0},
++ {0x91a5, 0x12, 0, 0},{0x91a6, 0x01, 0, 0},{0x91a7, 0xa0, 0, 0},
++ {0x91a8, 0xab, 0, 0},{0x91a9, 0x07, 0, 0},{0x91aa, 0xfa, 0, 0},
++ {0x91ab, 0xe4, 0, 0},{0x91ac, 0xf9, 0, 0},{0x91ad, 0xf8, 0, 0},
++ {0x91ae, 0xd0, 0, 0},{0x91af, 0x07, 0, 0},{0x91b0, 0xd0, 0, 0},
++ {0x91b1, 0x06, 0, 0},{0x91b2, 0xd0, 0, 0},{0x91b3, 0x05, 0, 0},
++ {0x91b4, 0x12, 0, 0},{0x91b5, 0x02, 0, 0},{0x91b6, 0x6d, 0, 0},
++ {0x91b7, 0x85, 0, 0},{0x91b8, 0x68, 0, 0},{0x91b9, 0x65, 0, 0},
++ {0x91ba, 0x85, 0, 0},{0x91bb, 0x7c, 0, 0},{0x91bc, 0x66, 0, 0},
++ {0x91bd, 0xe5, 0, 0},{0x91be, 0x49, 0, 0},{0x91bf, 0x25, 0, 0},
++ {0x91c0, 0x7c, 0, 0},{0x91c1, 0x12, 0, 0},{0x91c2, 0x02, 0, 0},
++ {0x91c3, 0x4f, 0, 0},{0x91c4, 0x93, 0, 0},{0x91c5, 0x75, 0, 0},
++ {0x91c6, 0x67, 0, 0},{0x91c7, 0x00, 0, 0},{0x91c8, 0xf5, 0, 0},
++ {0x91c9, 0x68, 0, 0},{0x91ca, 0x90, 0, 0},{0x91cb, 0x50, 0, 0},
++ {0x91cc, 0x82, 0, 0},{0x91cd, 0xe5, 0, 0},{0x91ce, 0x65, 0, 0},
++ {0x91cf, 0xf0, 0, 0},{0x91d0, 0xa3, 0, 0},{0x91d1, 0xe5, 0, 0},
++ {0x91d2, 0x66, 0, 0},{0x91d3, 0xf0, 0, 0},{0x91d4, 0xa3, 0, 0},
++ {0x91d5, 0xe5, 0, 0},{0x91d6, 0x67, 0, 0},{0x91d7, 0xf0, 0, 0},
++ {0x91d8, 0xa3, 0, 0},{0x91d9, 0xe5, 0, 0},{0x91da, 0x68, 0, 0},
++ {0x91db, 0xf0, 0, 0},{0x91dc, 0x22, 0, 0},{0x91dd, 0x56, 0, 0},
++ {0x91de, 0x0c, 0, 0},{0x91df, 0x04, 0, 0},{0x91e0, 0x00, 0, 0},
++ {0x91e1, 0x2a, 0, 0},{0x91e2, 0x35, 0, 0},{0x91e3, 0x40, 0, 0},
++ {0x91e4, 0x49, 0, 0},{0x91e5, 0x52, 0, 0},{0x91e6, 0x5b, 0, 0},
++ {0x91e7, 0x64, 0, 0},{0x91e8, 0x6d, 0, 0},{0x91e9, 0x76, 0, 0},
++ {0x91ea, 0x7f, 0, 0},{0x91eb, 0x88, 0, 0},{0x91ec, 0x91, 0, 0},
++ {0x91ed, 0x07, 0, 0},{0x91ee, 0x20, 0, 0},{0x91ef, 0x12, 0, 0},
++ {0x91f0, 0x28, 0, 0},{0x91f1, 0x1e, 0, 0},{0x91f2, 0x18, 0, 0},
++ {0x91f3, 0x18, 0, 0},{0x91f4, 0x28, 0, 0},{0x91f5, 0x1e, 0, 0},
++ {0x91f6, 0x18, 0, 0},{0x91f7, 0x12, 0, 0},{0x91f8, 0x28, 0, 0},
++ {0x91f9, 0x1e, 0, 0},{0x91fa, 0x18, 0, 0},{0x91fb, 0x12, 0, 0},
++ {0x91fc, 0x28, 0, 0},{0x91fd, 0x18, 0, 0},{0x91fe, 0x18, 0, 0},
++ {0x91ff, 0x12, 0, 0},{0x9200, 0x20, 0, 0},{0x9201, 0x18, 0, 0},
++ {0x9202, 0x28, 0, 0},{0x9203, 0x1c, 0, 0},{0x9204, 0x30, 0, 0},
++ {0x9205, 0x24, 0, 0},{0x9206, 0x10, 0, 0},{0x9207, 0x1c, 0, 0},
++ {0x9208, 0x18, 0, 0},{0x9209, 0x24, 0, 0},{0x920a, 0x1c, 0, 0},
++ {0x920b, 0x14, 0, 0},{0x920c, 0x24, 0, 0},{0x920d, 0x1c, 0, 0},
++ {0x920e, 0x28, 0, 0},{0x920f, 0x0c, 0, 0},{0x9210, 0x30, 0, 0},
++ {0x9211, 0x14, 0, 0},{0x9212, 0x10, 0, 0},{0x9213, 0x0c, 0, 0},
++ {0x9214, 0x18, 0, 0},{0x9215, 0x14, 0, 0},{0x9216, 0x1c, 0, 0},
++ {0x9217, 0x20, 0, 0},{0x9218, 0x24, 0, 0},{0x9219, 0x28, 0, 0},
++ {0x921a, 0x0c, 0, 0},{0x921b, 0x14, 0, 0},{0x921c, 0x14, 0, 0},
++ {0x921d, 0x1c, 0, 0},{0x921e, 0x1c, 0, 0},{0x921f, 0x14, 0, 0},
++ {0x9220, 0x24, 0, 0},{0x9221, 0x1c, 0, 0},{0x9222, 0x2c, 0, 0},
++ {0x9223, 0x14, 0, 0},{0x9224, 0x34, 0, 0},{0x9225, 0x1c, 0, 0},
++ {0x9226, 0x1c, 0, 0},{0x9227, 0x08, 0, 0},{0x9228, 0x24, 0, 0},
++ {0x9229, 0x10, 0, 0},{0x922a, 0x19, 0, 0},{0x922b, 0x19, 0, 0},
++ {0x922c, 0x1c, 0, 0},{0x922d, 0x19, 0, 0},{0x922e, 0x19, 0, 0},
++ {0x922f, 0x10, 0, 0},{0x9230, 0x10, 0, 0},{0x9231, 0x10, 0, 0},
++ {0x9232, 0x10, 0, 0},{0x9233, 0x10, 0, 0},{0x9234, 0x00, 0, 0},
++ {0x9235, 0x00, 0, 0},{0x9236, 0x00, 0, 0},{0x9237, 0x00, 0, 0},
++ {0x9238, 0x00, 0, 0},{0x9239, 0xc2, 0, 0},{0x923a, 0x34, 0, 0},
++ {0x923b, 0x20, 0, 0},{0x923c, 0x05, 0, 0},{0x923d, 0x05, 0, 0},
++ {0x923e, 0x75, 0, 0},{0x923f, 0x0a, 0, 0},{0x9240, 0xee, 0, 0},
++ {0x9241, 0x80, 0, 0},{0x9242, 0x36, 0, 0},{0x9243, 0x20, 0, 0},
++ {0x9244, 0x07, 0, 0},{0x9245, 0x08, 0, 0},{0x9246, 0x20, 0, 0},
++ {0x9247, 0x06, 0, 0},{0x9248, 0x05, 0, 0},{0x9249, 0xe4, 0, 0},
++ {0x924a, 0xf5, 0, 0},{0x924b, 0x0a, 0, 0},{0x924c, 0x80, 0, 0},
++ {0x924d, 0x2b, 0, 0},{0x924e, 0x20, 0, 0},{0x924f, 0x07, 0, 0},
++ {0x9250, 0x08, 0, 0},{0x9251, 0x30, 0, 0},{0x9252, 0x06, 0, 0},
++ {0x9253, 0x05, 0, 0},{0x9254, 0x75, 0, 0},{0x9255, 0x0a, 0, 0},
++ {0x9256, 0x20, 0, 0},{0x9257, 0x80, 0, 0},{0x9258, 0x20, 0, 0},
++ {0x9259, 0x30, 0, 0},{0x925a, 0x00, 0, 0},{0x925b, 0x05, 0, 0},
++ {0x925c, 0x75, 0, 0},{0x925d, 0x0a, 0, 0},{0x925e, 0x01, 0, 0},
++ {0x925f, 0x80, 0, 0},{0x9260, 0x18, 0, 0},{0x9261, 0xe5, 0, 0},
++ {0x9262, 0x20, 0, 0},{0x9263, 0x54, 0, 0},{0x9264, 0x07, 0, 0},
++ {0x9265, 0xff, 0, 0},{0x9266, 0xbf, 0, 0},{0x9267, 0x06, 0, 0},
++ {0x9268, 0x0d, 0, 0},{0x9269, 0x30, 0, 0},{0x926a, 0x31, 0, 0},
++ {0x926b, 0x04, 0, 0},{0x926c, 0x7f, 0, 0},{0x926d, 0x12, 0, 0},
++ {0x926e, 0x80, 0, 0},{0x926f, 0x02, 0, 0},{0x9270, 0x7f, 0, 0},
++ {0x9271, 0x02, 0, 0},{0x9272, 0x8f, 0, 0},{0x9273, 0x0a, 0, 0},
++ {0x9274, 0x80, 0, 0},{0x9275, 0x03, 0, 0},{0x9276, 0x75, 0, 0},
++ {0x9277, 0x0a, 0, 0},{0x9278, 0xfe, 0, 0},{0x9279, 0x90, 0, 0},
++ {0x927a, 0x30, 0, 0},{0x927b, 0x27, 0, 0},{0x927c, 0xe5, 0, 0},
++ {0x927d, 0x0a, 0, 0},{0x927e, 0xf0, 0, 0},{0x927f, 0xe5, 0, 0},
++ {0x9280, 0x23, 0, 0},{0x9281, 0x54, 0, 0},{0x9282, 0xf8, 0, 0},
++ {0x9283, 0xf5, 0, 0},{0x9284, 0x0a, 0, 0},{0x9285, 0xe5, 0, 0},
++ {0x9286, 0x78, 0, 0},{0x9287, 0x25, 0, 0},{0x9288, 0x0a, 0, 0},
++ {0x9289, 0xf5, 0, 0},{0x928a, 0x0a, 0, 0},{0x928b, 0x90, 0, 0},
++ {0x928c, 0x30, 0, 0},{0x928d, 0x26, 0, 0},{0x928e, 0xe5, 0, 0},
++ {0x928f, 0x0a, 0, 0},{0x9290, 0xf0, 0, 0},{0x9291, 0x22, 0, 0},
++ {0x9292, 0xe5, 0, 0},{0x9293, 0x0a, 0, 0},{0x9294, 0x70, 0, 0},
++ {0x9295, 0x04, 0, 0},{0x9296, 0x7e, 0, 0},{0x9297, 0x12, 0, 0},
++ {0x9298, 0x7f, 0, 0},{0x9299, 0x2a, 0, 0},{0x929a, 0xe5, 0, 0},
++ {0x929b, 0x0a, 0, 0},{0x929c, 0xb4, 0, 0},{0x929d, 0x01, 0, 0},
++ {0x929e, 0x04, 0, 0},{0x929f, 0x7e, 0, 0},{0x92a0, 0x12, 0, 0},
++ {0x92a1, 0x7f, 0, 0},{0x92a2, 0x2f, 0, 0},{0x92a3, 0xe5, 0, 0},
++ {0x92a4, 0x0a, 0, 0},{0x92a5, 0xb4, 0, 0},{0x92a6, 0x02, 0, 0},
++ {0x92a7, 0x04, 0, 0},{0x92a8, 0x7e, 0, 0},{0x92a9, 0x12, 0, 0},
++ {0x92aa, 0x7f, 0, 0},{0x92ab, 0x34, 0, 0},{0x92ac, 0x8f, 0, 0},
++ {0x92ad, 0x82, 0, 0},{0x92ae, 0x8e, 0, 0},{0x92af, 0x83, 0, 0},
++ {0x92b0, 0xe4, 0, 0},{0x92b1, 0x93, 0, 0},{0x92b2, 0xf5, 0, 0},
++ {0x92b3, 0x2c, 0, 0},{0x92b4, 0x74, 0, 0},{0x92b5, 0x01, 0, 0},
++ {0x92b6, 0x93, 0, 0},{0x92b7, 0xf5, 0, 0},{0x92b8, 0x2d, 0, 0},
++ {0x92b9, 0x74, 0, 0},{0x92ba, 0x02, 0, 0},{0x92bb, 0x93, 0, 0},
++ {0x92bc, 0xf5, 0, 0},{0x92bd, 0x2e, 0, 0},{0x92be, 0x74, 0, 0},
++ {0x92bf, 0x03, 0, 0},{0x92c0, 0x93, 0, 0},{0x92c1, 0xf5, 0, 0},
++ {0x92c2, 0x2f, 0, 0},{0x92c3, 0x74, 0, 0},{0x92c4, 0x04, 0, 0},
++ {0x92c5, 0x93, 0, 0},{0x92c6, 0xf5, 0, 0},{0x92c7, 0x30, 0, 0},
++ {0x92c8, 0xe5, 0, 0},{0x92c9, 0x0a, 0, 0},{0x92ca, 0xb4, 0, 0},
++ {0x92cb, 0x01, 0, 0},{0x92cc, 0x07, 0, 0},{0x92cd, 0x74, 0, 0},
++ {0x92ce, 0x2c, 0, 0},{0x92cf, 0x25, 0, 0},{0x92d0, 0x78, 0, 0},
++ {0x92d1, 0xf8, 0, 0},{0x92d2, 0x76, 0, 0},{0x92d3, 0x40, 0, 0},
++ {0x92d4, 0xe5, 0, 0},{0x92d5, 0x0a, 0, 0},{0x92d6, 0xb4, 0, 0},
++ {0x92d7, 0x02, 0, 0},{0x92d8, 0x07, 0, 0},{0x92d9, 0x74, 0, 0},
++ {0x92da, 0x2c, 0, 0},{0x92db, 0x25, 0, 0},{0x92dc, 0x78, 0, 0},
++ {0x92dd, 0xf8, 0, 0},{0x92de, 0x76, 0, 0},{0x92df, 0x80, 0, 0},
++ {0x92e0, 0x22, 0, 0},{0x92e1, 0xc0, 0, 0},{0x92e2, 0xe0, 0, 0},
++ {0x92e3, 0xc0, 0, 0},{0x92e4, 0x83, 0, 0},{0x92e5, 0xc0, 0, 0},
++ {0x92e6, 0x82, 0, 0},{0x92e7, 0xc0, 0, 0},{0x92e8, 0xd0, 0, 0},
++ {0x92e9, 0x90, 0, 0},{0x92ea, 0x3f, 0, 0},{0x92eb, 0x0d, 0, 0},
++ {0x92ec, 0xe0, 0, 0},{0x92ed, 0xf5, 0, 0},{0x92ee, 0x09, 0, 0},
++ {0x92ef, 0xe5, 0, 0},{0x92f0, 0x09, 0, 0},{0x92f1, 0x30, 0, 0},
++ {0x92f2, 0xe0, 0, 0},{0x92f3, 0x2e, 0, 0},{0x92f4, 0xe5, 0, 0},
++ {0x92f5, 0x79, 0, 0},{0x92f6, 0xb4, 0, 0},{0x92f7, 0x01, 0, 0},
++ {0x92f8, 0x09, 0, 0},{0x92f9, 0x90, 0, 0},{0x92fa, 0x3a, 0, 0},
++ {0x92fb, 0x00, 0, 0},{0x92fc, 0xe0, 0, 0},{0x92fd, 0xf5, 0, 0},
++ {0x92fe, 0x77, 0, 0},{0x92ff, 0x44, 0, 0},{0x9300, 0x01, 0, 0},
++ {0x9301, 0xf0, 0, 0},{0x9302, 0xe5, 0, 0},{0x9303, 0x79, 0, 0},
++ {0x9304, 0xb4, 0, 0},{0x9305, 0x03, 0, 0},{0x9306, 0x09, 0, 0},
++ {0x9307, 0x90, 0, 0},{0x9308, 0x3a, 0, 0},{0x9309, 0x00, 0, 0},
++ {0x930a, 0xe0, 0, 0},{0x930b, 0xf5, 0, 0},{0x930c, 0x77, 0, 0},
++ {0x930d, 0x54, 0, 0},{0x930e, 0xfe, 0, 0},{0x930f, 0xf0, 0, 0},
++ {0x9310, 0xe5, 0, 0},{0x9311, 0x79, 0, 0},{0x9312, 0xb4, 0, 0},
++ {0x9313, 0x03, 0, 0},{0x9314, 0x05, 0, 0},{0x9315, 0x75, 0, 0},
++ {0x9316, 0x79, 0, 0},{0x9317, 0x00, 0, 0},{0x9318, 0x80, 0, 0},
++ {0x9319, 0x02, 0, 0},{0x931a, 0x05, 0, 0},{0x931b, 0x79, 0, 0},
++ {0x931c, 0x90, 0, 0},{0x931d, 0x3f, 0, 0},{0x931e, 0x0d, 0, 0},
++ {0x931f, 0x74, 0, 0},{0x9320, 0x01, 0, 0},{0x9321, 0xf0, 0, 0},
++ {0x9322, 0xd0, 0, 0},{0x9323, 0xd0, 0, 0},{0x9324, 0xd0, 0, 0},
++ {0x9325, 0x82, 0, 0},{0x9326, 0xd0, 0, 0},{0x9327, 0x83, 0, 0},
++ {0x9328, 0xd0, 0, 0},{0x9329, 0xe0, 0, 0},{0x932a, 0x32, 0, 0},
++ {0x932b, 0x90, 0, 0},{0x932c, 0x50, 0, 0},{0x932d, 0x27, 0, 0},
++ {0x932e, 0xe0, 0, 0},{0x932f, 0x44, 0, 0},{0x9330, 0x01, 0, 0},
++ {0x9331, 0xf0, 0, 0},{0x9332, 0x90, 0, 0},{0x9333, 0x50, 0, 0},
++ {0x9334, 0x34, 0, 0},{0x9335, 0x74, 0, 0},{0x9336, 0x80, 0, 0},
++ {0x9337, 0xf0, 0, 0},{0x9338, 0xa3, 0, 0},{0x9339, 0x74, 0, 0},
++ {0x933a, 0x2a, 0, 0},{0x933b, 0xf0, 0, 0},{0x933c, 0xa3, 0, 0},
++ {0x933d, 0x74, 0, 0},{0x933e, 0x14, 0, 0},{0x933f, 0xf0, 0, 0},
++ {0x9340, 0x90, 0, 0},{0x9341, 0x50, 0, 0},{0x9342, 0x30, 0, 0},
++ {0x9343, 0xe4, 0, 0},{0x9344, 0xf0, 0, 0},{0x9345, 0xa3, 0, 0},
++ {0x9346, 0x74, 0, 0},{0x9347, 0x02, 0, 0},{0x9348, 0xf0, 0, 0},
++ {0x9349, 0xa3, 0, 0},{0x934a, 0xe4, 0, 0},{0x934b, 0xf0, 0, 0},
++ {0x934c, 0xa3, 0, 0},{0x934d, 0x74, 0, 0},{0x934e, 0x80, 0, 0},
++ {0x934f, 0xf0, 0, 0},{0x9350, 0xe4, 0, 0},{0x9351, 0xf5, 0, 0},
++ {0x9352, 0x0a, 0, 0},{0x9353, 0x12, 0, 0},{0x9354, 0x10, 0, 0},
++ {0x9355, 0xb5, 0, 0},{0x9356, 0x75, 0, 0},{0x9357, 0x78, 0, 0},
++ {0x9358, 0x02, 0, 0},{0x9359, 0x75, 0, 0},{0x935a, 0x0a, 0, 0},
++ {0x935b, 0x01, 0, 0},{0x935c, 0x12, 0, 0},{0x935d, 0x12, 0, 0},
++ {0x935e, 0x92, 0, 0},{0x935f, 0xd2, 0, 0},{0x9360, 0x18, 0, 0},
++ {0x9361, 0xd2, 0, 0},{0x9362, 0x19, 0, 0},{0x9363, 0xc2, 0, 0},
++ {0x9364, 0x3a, 0, 0},{0x9365, 0xc2, 0, 0},{0x9366, 0x39, 0, 0},
++ {0x9367, 0xd2, 0, 0},{0x9368, 0x1a, 0, 0},{0x9369, 0xd2, 0, 0},
++ {0x936a, 0x36, 0, 0},{0x936b, 0xd2, 0, 0},{0x936c, 0x30, 0, 0},
++ {0x936d, 0xc2, 0, 0},{0x936e, 0x35, 0, 0},{0x936f, 0xc2, 0, 0},
++ {0x9370, 0x3b, 0, 0},{0x9371, 0x22, 0, 0},{0x9372, 0x85, 0, 0},
++ {0x9373, 0x13, 0, 0},{0x9374, 0x14, 0, 0},{0x9375, 0x7f, 0, 0},
++ {0x9376, 0x08, 0, 0},{0x9377, 0xe5, 0, 0},{0x9378, 0x14, 0, 0},
++ {0x9379, 0x30, 0, 0},{0x937a, 0xe7, 0, 0},{0x937b, 0x04, 0, 0},
++ {0x937c, 0xd2, 0, 0},{0x937d, 0x29, 0, 0},{0x937e, 0x80, 0, 0},
++ {0x937f, 0x02, 0, 0},{0x9380, 0xc2, 0, 0},{0x9381, 0x29, 0, 0},
++ {0x9382, 0x12, 0, 0},{0x9383, 0x01, 0, 0},{0x9384, 0x6c, 0, 0},
++ {0x9385, 0x75, 0, 0},{0x9386, 0x51, 0, 0},{0x9387, 0x0a, 0, 0},
++ {0x9388, 0xae, 0, 0},{0x9389, 0x51, 0, 0},{0x938a, 0x15, 0, 0},
++ {0x938b, 0x51, 0, 0},{0x938c, 0xee, 0, 0},{0x938d, 0x70, 0, 0},
++ {0x938e, 0xf9, 0, 0},{0x938f, 0xe5, 0, 0},{0x9390, 0x14, 0, 0},
++ {0x9391, 0x25, 0, 0},{0x9392, 0xe0, 0, 0},{0x9393, 0xf5, 0, 0},
++ {0x9394, 0x14, 0, 0},{0x9395, 0xd2, 0, 0},{0x9396, 0x28, 0, 0},
++ {0x9397, 0x12, 0, 0},{0x9398, 0x01, 0, 0},{0x9399, 0x6c, 0, 0},
++ {0x939a, 0x75, 0, 0},{0x939b, 0x51, 0, 0},{0x939c, 0x0a, 0, 0},
++ {0x939d, 0xae, 0, 0},{0x939e, 0x51, 0, 0},{0x939f, 0x15, 0, 0},
++ {0x93a0, 0x51, 0, 0},{0x93a1, 0xee, 0, 0},{0x93a2, 0x70, 0, 0},
++ {0x93a3, 0xf9, 0, 0},{0x93a4, 0xc2, 0, 0},{0x93a5, 0x28, 0, 0},
++ {0x93a6, 0x12, 0, 0},{0x93a7, 0x01, 0, 0},{0x93a8, 0x6c, 0, 0},
++ {0x93a9, 0x75, 0, 0},{0x93aa, 0x51, 0, 0},{0x93ab, 0x05, 0, 0},
++ {0x93ac, 0xae, 0, 0},{0x93ad, 0x51, 0, 0},{0x93ae, 0x15, 0, 0},
++ {0x93af, 0x51, 0, 0},{0x93b0, 0xee, 0, 0},{0x93b1, 0x70, 0, 0},
++ {0x93b2, 0xf9, 0, 0},{0x93b3, 0xdf, 0, 0},{0x93b4, 0xc2, 0, 0},
++ {0x93b5, 0x22, 0, 0},{0x93b6, 0xc2, 0, 0},{0x93b7, 0xaf, 0, 0},
++ {0x93b8, 0x90, 0, 0},{0x93b9, 0x30, 0, 0},{0x93ba, 0x27, 0, 0},
++ {0x93bb, 0x74, 0, 0},{0x93bc, 0xfa, 0, 0},{0x93bd, 0xf0, 0, 0},
++ {0x93be, 0x12, 0, 0},{0x93bf, 0x0e, 0, 0},{0x93c0, 0x71, 0, 0},
++ {0x93c1, 0x12, 0, 0},{0x93c2, 0x14, 0, 0},{0x93c3, 0x84, 0, 0},
++ {0x93c4, 0xe4, 0, 0},{0x93c5, 0xf5, 0, 0},{0x93c6, 0x33, 0, 0},
++ {0x93c7, 0xd2, 0, 0},{0x93c8, 0xaf, 0, 0},{0x93c9, 0x12, 0, 0},
++ {0x93ca, 0x0c, 0, 0},{0x93cb, 0x69, 0, 0},{0x93cc, 0x30, 0, 0},
++ {0x93cd, 0x30, 0, 0},{0x93ce, 0x03, 0, 0},{0x93cf, 0x12, 0, 0},
++ {0x93d0, 0x06, 0, 0},{0x93d1, 0xdf, 0, 0},{0x93d2, 0x30, 0, 0},
++ {0x93d3, 0x34, 0, 0},{0x93d4, 0x03, 0, 0},{0x93d5, 0x12, 0, 0},
++ {0x93d6, 0x12, 0, 0},{0x93d7, 0x39, 0, 0},{0x93d8, 0x30, 0, 0},
++ {0x93d9, 0x3b, 0, 0},{0x93da, 0xee, 0, 0},{0x93db, 0xc2, 0, 0},
++ {0x93dc, 0x3b, 0, 0},{0x93dd, 0xd2, 0, 0},{0x93de, 0x35, 0, 0},
++ {0x93df, 0x30, 0, 0},{0x93e0, 0x00, 0, 0},{0x93e1, 0x05, 0, 0},
++ {0x93e2, 0x12, 0, 0},{0x93e3, 0x14, 0, 0},{0x93e4, 0x57, 0, 0},
++ {0x93e5, 0x80, 0, 0},{0x93e6, 0x09, 0, 0},{0x93e7, 0x20, 0, 0},
++ {0x93e8, 0x07, 0, 0},{0x93e9, 0x06, 0, 0},{0x93ea, 0x30, 0, 0},
++ {0x93eb, 0x06, 0, 0},{0x93ec, 0x03, 0, 0},{0x93ed, 0x12, 0, 0},
++ {0x93ee, 0x0d, 0, 0},{0x93ef, 0x77, 0, 0},{0x93f0, 0xc2, 0, 0},
++ {0x93f1, 0x35, 0, 0},{0x93f2, 0x80, 0, 0},{0x93f3, 0xd5, 0, 0},
++ {0x93f4, 0x12, 0, 0},{0x93f5, 0x10, 0, 0},{0x93f6, 0x3d, 0, 0},
++ {0x93f7, 0xd2, 0, 0},{0x93f8, 0x3c, 0, 0},{0x93f9, 0x12, 0, 0},
++ {0x93fa, 0x0f, 0, 0},{0x93fb, 0xb0, 0, 0},{0x93fc, 0xd2, 0, 0},
++ {0x93fd, 0x3c, 0, 0},{0x93fe, 0x12, 0, 0},{0x93ff, 0x11, 0, 0},
++ {0x9400, 0x1a, 0, 0},{0x9401, 0xe5, 0, 0},{0x9402, 0x7b, 0, 0},
++ {0x9403, 0xd3, 0, 0},{0x9404, 0x95, 0, 0},{0x9405, 0x7c, 0, 0},
++ {0x9406, 0x40, 0, 0},{0x9407, 0x03, 0, 0},{0x9408, 0xd3, 0, 0},
++ {0x9409, 0x80, 0, 0},{0x940a, 0x01, 0, 0},{0x940b, 0xc3, 0, 0},
++ {0x940c, 0x50, 0, 0},{0x940d, 0x14, 0, 0},{0x940e, 0x20, 0, 0},
++ {0x940f, 0x37, 0, 0},{0x9410, 0x0e, 0, 0},{0x9411, 0xe5, 0, 0},
++ {0x9412, 0x24, 0, 0},{0x9413, 0x54, 0, 0},{0x9414, 0x1f, 0, 0},
++ {0x9415, 0xff, 0, 0},{0x9416, 0xbf, 0, 0},{0x9417, 0x1f, 0, 0},
++ {0x9418, 0x06, 0, 0},{0x9419, 0x30, 0, 0},{0x941a, 0x25, 0, 0},
++ {0x941b, 0x03, 0, 0},{0x941c, 0x20, 0, 0},{0x941d, 0x26, 0, 0},
++ {0x941e, 0x03, 0, 0},{0x941f, 0x02, 0, 0},{0x9420, 0x15, 0, 0},
++ {0x9421, 0x2c, 0, 0},{0x9422, 0x12, 0, 0},{0x9423, 0x02, 0, 0},
++ {0x9424, 0xb6, 0, 0},{0x9425, 0x22, 0, 0},{0x9426, 0xe5, 0, 0},
++ {0x9427, 0x7c, 0, 0},{0x9428, 0x70, 0, 0},{0x9429, 0x19, 0, 0},
++ {0x942a, 0x12, 0, 0},{0x942b, 0x15, 0, 0},{0x942c, 0x04, 0, 0},
++ {0x942d, 0xc2, 0, 0},{0x942e, 0x3c, 0, 0},{0x942f, 0x12, 0, 0},
++ {0x9430, 0x0f, 0, 0},{0x9431, 0xb0, 0, 0},{0x9432, 0xc2, 0, 0},
++ {0x9433, 0x3c, 0, 0},{0x9434, 0x12, 0, 0},{0x9435, 0x11, 0, 0},
++ {0x9436, 0x1a, 0, 0},{0x9437, 0xc2, 0, 0},{0x9438, 0x03, 0, 0},
++ {0x9439, 0x12, 0, 0},{0x943a, 0x15, 0, 0},{0x943b, 0x2c, 0, 0},
++ {0x943c, 0xd2, 0, 0},{0x943d, 0x02, 0, 0},{0x943e, 0xd2, 0, 0},
++ {0x943f, 0x01, 0, 0},{0x9440, 0xd2, 0, 0},{0x9441, 0x00, 0, 0},
++ {0x9442, 0x22, 0, 0},{0x9443, 0x30, 0, 0},{0x9444, 0x03, 0, 0},
++ {0x9445, 0x08, 0, 0},{0x9446, 0xc2, 0, 0},{0x9447, 0x03, 0, 0},
++ {0x9448, 0xc2, 0, 0},{0x9449, 0x04, 0, 0},{0x944a, 0x12, 0, 0},
++ {0x944b, 0x02, 0, 0},{0x944c, 0xa5, 0, 0},{0x944d, 0x22, 0, 0},
++ {0x944e, 0xe4, 0, 0},{0x944f, 0xf5, 0, 0},{0x9450, 0x0c, 0, 0},
++ {0x9451, 0x12, 0, 0},{0x9452, 0x0f, 0, 0},{0x9453, 0x11, 0, 0},
++ {0x9454, 0xd2, 0, 0},{0x9455, 0x03, 0, 0},{0x9456, 0x22, 0, 0},
++ {0x9457, 0xe5, 0, 0},{0x9458, 0x20, 0, 0},{0x9459, 0x54, 0, 0},
++ {0x945a, 0x07, 0, 0},{0x945b, 0xff, 0, 0},{0x945c, 0xbf, 0, 0},
++ {0x945d, 0x01, 0, 0},{0x945e, 0x03, 0, 0},{0x945f, 0x02, 0, 0},
++ {0x9460, 0x14, 0, 0},{0x9461, 0x26, 0, 0},{0x9462, 0xe5, 0, 0},
++ {0x9463, 0x20, 0, 0},{0x9464, 0x54, 0, 0},{0x9465, 0x07, 0, 0},
++ {0x9466, 0xff, 0, 0},{0x9467, 0xbf, 0, 0},{0x9468, 0x07, 0, 0},
++ {0x9469, 0x03, 0, 0},{0x946a, 0x02, 0, 0},{0x946b, 0x14, 0, 0},
++ {0x946c, 0xaa, 0, 0},{0x946d, 0xe5, 0, 0},{0x946e, 0x20, 0, 0},
++ {0x946f, 0x54, 0, 0},{0x9470, 0x07, 0, 0},{0x9471, 0xff, 0, 0},
++ {0x9472, 0xbf, 0, 0},{0x9473, 0x03, 0, 0},{0x9474, 0x03, 0, 0},
++ {0x9475, 0x02, 0, 0},{0x9476, 0x13, 0, 0},{0x9477, 0xf4, 0, 0},
++ {0x9478, 0xe5, 0, 0},{0x9479, 0x20, 0, 0},{0x947a, 0x54, 0, 0},
++ {0x947b, 0x07, 0, 0},{0x947c, 0xff, 0, 0},{0x947d, 0xbf, 0, 0},
++ {0x947e, 0x05, 0, 0},{0x947f, 0x03, 0, 0},{0x9480, 0x12, 0, 0},
++ {0x9481, 0x15, 0, 0},{0x9482, 0x6a, 0, 0},{0x9483, 0x22, 0, 0},
++ {0x9484, 0x12, 0, 0},{0x9485, 0x13, 0, 0},{0x9486, 0x2b, 0, 0},
++ {0x9487, 0x12, 0, 0},{0x9488, 0x15, 0, 0},{0x9489, 0x78, 0, 0},
++ {0x948a, 0x50, 0, 0},{0x948b, 0x04, 0, 0},{0x948c, 0xd2, 0, 0},
++ {0x948d, 0x05, 0, 0},{0x948e, 0x80, 0, 0},{0x948f, 0x02, 0, 0},
++ {0x9490, 0xc2, 0, 0},{0x9491, 0x05, 0, 0},{0x9492, 0x12, 0, 0},
++ {0x9493, 0x02, 0, 0},{0x9494, 0x40, 0, 0},{0x9495, 0xc2, 0, 0},
++ {0x9496, 0x37, 0, 0},{0x9497, 0xc2, 0, 0},{0x9498, 0x31, 0, 0},
++ {0x9499, 0xd2, 0, 0},{0x949a, 0x34, 0, 0},{0x949b, 0x12, 0, 0},
++ {0x949c, 0x02, 0, 0},{0x949d, 0x85, 0, 0},{0x949e, 0xb5, 0, 0},
++ {0x949f, 0x07, 0, 0},{0x94a0, 0x03, 0, 0},{0x94a1, 0xd3, 0, 0},
++ {0x94a2, 0x80, 0, 0},{0x94a3, 0x01, 0, 0},{0x94a4, 0xc3, 0, 0},
++ {0x94a5, 0x40, 0, 0},{0x94a6, 0x02, 0, 0},{0x94a7, 0xc2, 0, 0},
++ {0x94a8, 0x05, 0, 0},{0x94a9, 0x22, 0, 0},{0x94aa, 0x12, 0, 0},
++ {0x94ab, 0x10, 0, 0},{0x94ac, 0x3d, 0, 0},{0x94ad, 0xd2, 0, 0},
++ {0x94ae, 0x3c, 0, 0},{0x94af, 0x12, 0, 0},{0x94b0, 0x0f, 0, 0},
++ {0x94b1, 0xb0, 0, 0},{0x94b2, 0xd2, 0, 0},{0x94b3, 0x3c, 0, 0},
++ {0x94b4, 0x12, 0, 0},{0x94b5, 0x11, 0, 0},{0x94b6, 0x1a, 0, 0},
++ {0x94b7, 0x12, 0, 0},{0x94b8, 0x15, 0, 0},{0x94b9, 0x2c, 0, 0},
++ {0x94ba, 0xe5, 0, 0},{0x94bb, 0x32, 0, 0},{0x94bc, 0xd3, 0, 0},
++ {0x94bd, 0x95, 0, 0},{0x94be, 0x7c, 0, 0},{0x94bf, 0x40, 0, 0},
++ {0x94c0, 0x05, 0, 0},{0x94c1, 0xe4, 0, 0},{0x94c2, 0x95, 0, 0},
++ {0x94c3, 0x7c, 0, 0},{0x94c4, 0x40, 0, 0},{0x94c5, 0x06, 0, 0},
++ {0x94c6, 0xc2, 0, 0},{0x94c7, 0x02, 0, 0},{0x94c8, 0xd2, 0, 0},
++ {0x94c9, 0x01, 0, 0},{0x94ca, 0xd2, 0, 0},{0x94cb, 0x00, 0, 0},
++ {0x94cc, 0x22, 0, 0},{0x94cd, 0xe4, 0, 0},{0x94ce, 0xff, 0, 0},
++ {0x94cf, 0xfe, 0, 0},{0x94d0, 0xc3, 0, 0},{0x94d1, 0xef, 0, 0},
++ {0x94d2, 0x95, 0, 0},{0x94d3, 0x11, 0, 0},{0x94d4, 0xee, 0, 0},
++ {0x94d5, 0x95, 0, 0},{0x94d6, 0x10, 0, 0},{0x94d7, 0x50, 0, 0},
++ {0x94d8, 0x15, 0, 0},{0x94d9, 0x7d, 0, 0},{0x94da, 0x8a, 0, 0},
++ {0x94db, 0x7c, 0, 0},{0x94dc, 0x02, 0, 0},{0x94dd, 0xed, 0, 0},
++ {0x94de, 0x1d, 0, 0},{0x94df, 0xaa, 0, 0},{0x94e0, 0x04, 0, 0},
++ {0x94e1, 0x70, 0, 0},{0x94e2, 0x01, 0, 0},{0x94e3, 0x1c, 0, 0},
++ {0x94e4, 0x4a, 0, 0},{0x94e5, 0x70, 0, 0},{0x94e6, 0xf6, 0, 0},
++ {0x94e7, 0x0f, 0, 0},{0x94e8, 0xbf, 0, 0},{0x94e9, 0x00, 0, 0},
++ {0x94ea, 0x01, 0, 0},{0x94eb, 0x0e, 0, 0},{0x94ec, 0x80, 0, 0},
++ {0x94ed, 0xe2, 0, 0},{0x94ee, 0x22, 0, 0},{0x94ef, 0x75, 0, 0},
++ {0x94f0, 0x48, 0, 0},{0x94f1, 0x11, 0, 0},{0x94f2, 0x75, 0, 0},
++ {0x94f3, 0x49, 0, 0},{0x94f4, 0xe0, 0, 0},{0x94f5, 0x90, 0, 0},
++ {0x94f6, 0x11, 0, 0},{0x94f7, 0xde, 0, 0},{0x94f8, 0xe4, 0, 0},
++ {0x94f9, 0x93, 0, 0},{0x94fa, 0xf5, 0, 0},{0x94fb, 0x7b, 0, 0},
++ {0x94fc, 0xa3, 0, 0},{0x94fd, 0xe4, 0, 0},{0x94fe, 0x93, 0, 0},
++ {0x94ff, 0xf5, 0, 0},{0x9500, 0x32, 0, 0},{0x9501, 0xc2, 0, 0},
++ {0x9502, 0x38, 0, 0},{0x9503, 0x22, 0, 0},{0x9504, 0xe4, 0, 0},
++ {0x9505, 0xff, 0, 0},{0x9506, 0xef, 0, 0},{0x9507, 0x25, 0, 0},
++ {0x9508, 0xe0, 0, 0},{0x9509, 0x24, 0, 0},{0x950a, 0x56, 0, 0},
++ {0x950b, 0xf8, 0, 0},{0x950c, 0xe4, 0, 0},{0x950d, 0xf6, 0, 0},
++ {0x950e, 0x08, 0, 0},{0x950f, 0xf6, 0, 0},{0x9510, 0x0f, 0, 0},
++ {0x9511, 0xbf, 0, 0},{0x9512, 0x07, 0, 0},{0x9513, 0xf2, 0, 0},
++ {0x9514, 0x53, 0, 0},{0x9515, 0x24, 0, 0},{0x9516, 0x80, 0, 0},
++ {0x9517, 0x22, 0, 0},{0x9518, 0xc2, 0, 0},{0x9519, 0x03, 0, 0},
++ {0x951a, 0xd2, 0, 0},{0x951b, 0x04, 0, 0},{0x951c, 0x12, 0, 0},
++ {0x951d, 0x02, 0, 0},{0x951e, 0xa5, 0, 0},{0x951f, 0xc2, 0, 0},
++ {0x9520, 0x3c, 0, 0},{0x9521, 0x12, 0, 0},{0x9522, 0x0f, 0, 0},
++ {0x9523, 0xb0, 0, 0},{0x9524, 0xc2, 0, 0},{0x9525, 0x3c, 0, 0},
++ {0x9526, 0x12, 0, 0},{0x9527, 0x11, 0, 0},{0x9528, 0x1a, 0, 0},
++ {0x9529, 0xd2, 0, 0},{0x952a, 0x34, 0, 0},{0x952b, 0x22, 0, 0},
++ {0x952c, 0xe5, 0, 0},{0x952d, 0x7c, 0, 0},{0x952e, 0xc3, 0, 0},
++ {0x952f, 0x95, 0, 0},{0x9530, 0x7b, 0, 0},{0x9531, 0x40, 0, 0},
++ {0x9532, 0x01, 0, 0},{0x9533, 0x22, 0, 0},{0x9534, 0xe5, 0, 0},
++ {0x9535, 0x7c, 0, 0},{0x9536, 0x04, 0, 0},{0x9537, 0xf5, 0, 0},
++ {0x9538, 0x0c, 0, 0},{0x9539, 0x12, 0, 0},{0x953a, 0x0f, 0, 0},
++ {0x953b, 0x11, 0, 0},{0x953c, 0x22, 0, 0},{0x953d, 0xe5, 0, 0},
++ {0x953e, 0x7c, 0, 0},{0x953f, 0x70, 0, 0},{0x9540, 0x02, 0, 0},
++ {0x9541, 0xc3, 0, 0},{0x9542, 0x22, 0, 0},{0x9543, 0xe5, 0, 0},
++ {0x9544, 0x7c, 0, 0},{0x9545, 0x14, 0, 0},{0x9546, 0xf5, 0, 0},
++ {0x9547, 0x0c, 0, 0},{0x9548, 0x12, 0, 0},{0x9549, 0x0f, 0, 0},
++ {0x954a, 0x11, 0, 0},{0x954b, 0x22, 0, 0},{0x954c, 0xe5, 0, 0},
++ {0x954d, 0x7d, 0, 0},{0x954e, 0xb4, 0, 0},{0x954f, 0x01, 0, 0},
++ {0x9550, 0x09, 0, 0},{0x9551, 0x12, 0, 0},{0x9552, 0x14, 0, 0},
++ {0x9553, 0xef, 0, 0},{0x9554, 0xe4, 0, 0},{0x9555, 0xf5, 0, 0},
++ {0x9556, 0x0c, 0, 0},{0x9557, 0x12, 0, 0},{0x9558, 0x0f, 0, 0},
++ {0x9559, 0x11, 0, 0},{0x955a, 0x22, 0, 0},{0x955b, 0xe5, 0, 0},
++ {0x955c, 0x7d, 0, 0},{0x955d, 0x24, 0, 0},{0x955e, 0xfe, 0, 0},
++ {0x955f, 0x60, 0, 0},{0x9560, 0x06, 0, 0},{0x9561, 0x04, 0, 0},
++ {0x9562, 0x70, 0, 0},{0x9563, 0x05, 0, 0},{0x9564, 0xd2, 0, 0},
++ {0x9565, 0x37, 0, 0},{0x9566, 0x22, 0, 0},{0x9567, 0xc2, 0, 0},
++ {0x9568, 0x37, 0, 0},{0x9569, 0x22, 0, 0},{0x956a, 0xe5, 0, 0},
++ {0x956b, 0x31, 0, 0},{0x956c, 0xd3, 0, 0},{0x956d, 0x94, 0, 0},
++ {0x956e, 0x00, 0, 0},{0x956f, 0x40, 0, 0},{0x9570, 0x03, 0, 0},
++ {0x9571, 0x15, 0, 0},{0x9572, 0x31, 0, 0},{0x9573, 0x22, 0, 0},
++ {0x9574, 0x12, 0, 0},{0x9575, 0x15, 0, 0},{0x9576, 0x18, 0, 0},
++ {0x9577, 0x22, 0, 0},{0x9578, 0x12, 0, 0},{0x9579, 0x14, 0, 0},
++ {0x957a, 0xef, 0, 0},{0x957b, 0xe4, 0, 0},{0x957c, 0xf5, 0, 0},
++ {0x957d, 0x0c, 0, 0},{0x957e, 0x12, 0, 0},{0x957f, 0x0f, 0, 0},
++ {0x9580, 0x11, 0, 0},{0x9581, 0x22, 0, 0},{0x3024, 0x00, 0, 0},
++ {0x3025, 0x00, 0, 0},{0x5082, 0x00, 0, 0},{0x5083, 0x00, 0, 0},
++ {0x5084, 0x00, 0, 0},{0x5085, 0x00, 0, 0},{0x3026, 0x00, 0, 0},
++ {0x3027, 0xFF, 0, 0},{0x3000, 0x00, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_QCIF_176_144[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_QCIF_176_144[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x10, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0x90, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_QSXGA_2592_1944[] = {
++ {0x3503, 0x07, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0},
++ {0x3002, 0x00, 0, 0}, {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
++ {0x3005, 0xff, 0, 0}, {0x3006, 0xff, 0, 0}, {0x3007, 0x3f, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3818, 0xc0, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3602, 0xe4, 0, 0}, {0x3612, 0xac, 0, 0}, {0x3613, 0x44, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3623, 0x22, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3705, 0xda, 0, 0}, {0x370a, 0x80, 0, 0}, {0x3801, 0x95, 0, 0},
++ {0x3803, 0x0e, 0, 0}, {0x3804, 0x0a, 0, 0}, {0x3805, 0x20, 0, 0},
++ {0x3806, 0x07, 0, 0}, {0x3807, 0x98, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3815, 0x44, 0, 0},
++ {0x3824, 0x11, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x5682, 0x0a, 0, 0}, {0x5683, 0x20, 0, 0}, {0x5686, 0x07, 0, 0},
++ {0x5687, 0x98, 0, 0}, {0x5001, 0xff, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x4407, 0x04, 0, 0}, {0x3008, 0x02, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x460c, 0x22, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x471c, 0xd0, 0, 0}, {0x3815, 0x01, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0},
++ {0x5002, 0xe0, 0, 0}, {0x530a, 0x01, 0, 0}, {0x530d, 0x10, 0, 0},
++ {0x530c, 0x04, 0, 0}, {0x5312, 0x20, 0, 0}, {0x5282, 0x01, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x3012, 0x00, 0, 0},
++};
++
++
++static struct reg_value ov5642_setting_VGA_2_QVGA[] = {
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x3815, 0x04, 0, 0},
++};
++
++static struct reg_value ov5642_setting_QSXGA_2_VGA[] = {
++ {0x3503, 0x00, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0},
++ {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
++ {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x3818, 0xc1, 0, 0}, {0x3621, 0x87, 0, 0},
++ {0x350c, 0x03, 0, 0}, {0x350d, 0xe8, 0, 0}, {0x3602, 0xfc, 0, 0},
++ {0x3612, 0xff, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3622, 0x60, 0, 0},
++ {0x3623, 0x01, 0, 0}, {0x3604, 0x48, 0, 0}, {0x3705, 0xdb, 0, 0},
++ {0x370a, 0x81, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x3806, 0x03, 0, 0},
++ {0x3807, 0xc0, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3810, 0x40, 0, 0}, {0x3815, 0x04, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3825, 0xb4, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0},
++ {0x5001, 0xff, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x4407, 0x0c, 0, 0}, {0x3008, 0x02, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x471d, 0x05, 0, 0}, {0x4713, 0x02, 0, 0},
++ {0x471c, 0xd0, 0, 0}, {0x3815, 0x04, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x3002, 0x5c, 0, 0}, {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0},
++ {0x530a, 0x01, 0, 0}, {0x530d, 0x0c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x5312, 0x40, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x3012, 0x02, 0, 0}, {0x3010, 0x00, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_VGA_640_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_VGA_640_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++
++static struct reg_value ov5642_setting_30fps_XGA_1024_768[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0},
++ {0x380b, 0x00, 0, 0}, {0x3815, 0x02, 0, 0}, {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_XGA_1024_768[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0},
++ {0x380b, 0x00, 0, 0}, {0x3815, 0x02, 0, 0}, {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_QVGA_320_240[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3808, 0x01, 0, 0},
++ {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_NTSC_720_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0},
++ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0x58, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_PAL_720_576[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0},
++ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0},
++ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0},
++ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xd8, 0, 0},
++ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0},
++ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0},
++ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0},
++ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0},
++ {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0},
++ {0x3804, 0x04, 0, 0}, {0x3805, 0xb0, 0, 0}, {0x5682, 0x04, 0, 0},
++ {0x5683, 0xb0, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0},
++ {0x5686, 0x03, 0, 0}, {0x5687, 0x58, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0},
++ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0},
++ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0},
++ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0},
++ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0},
++ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0},
++ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0},
++ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0},
++ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0},
++ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0},
++ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0},
++ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0},
++ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x302c, 0x60, 0x60, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_720P_1280_720[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0},
++ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0},
++ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0},
++ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0},
++ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0},
++ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0},
++ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0},
++ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0},
++ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0},
++ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0},
++ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x350c, 0x02, 0, 0}, {0x350d, 0xe4, 0, 0}, {0x3621, 0xc9, 0, 0},
++ {0x370a, 0x81, 0, 0}, {0x3803, 0x08, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x3806, 0x02, 0, 0}, {0x3807, 0xd0, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x08, 0, 0}, {0x380d, 0x72, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0xc0, 0, 0},
++ {0x3818, 0xc9, 0, 0}, {0x381c, 0x10, 0, 0}, {0x381d, 0xa0, 0, 0},
++ {0x381e, 0x05, 0, 0}, {0x381f, 0xb0, 0, 0}, {0x3820, 0x00, 0, 0},
++ {0x3821, 0x00, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3a08, 0x1b, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x17, 0, 0}, {0x3a0b, 0x20, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a0e, 0x01, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, {0x5686, 0x02, 0, 0},
++ {0x5687, 0xcc, 0, 0}, {0x5001, 0x7f, 0, 0}, {0x589b, 0x06, 0, 0},
++ {0x589a, 0xc5, 0, 0}, {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0},
++ {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0},
++ {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0}, {0x3010, 0x30, 0, 0},
++ {0x3a08, 0x06, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x05, 0, 0},
++ {0x3a0b, 0x50, 0, 0}, {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x07, 0, 0},
++};
++
++static struct reg_value ov5642_setting_30fps_720P_1280_720[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0},
++ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0},
++ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0},
++ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0},
++ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0},
++ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0},
++ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0},
++ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0},
++ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0},
++ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0},
++ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x350c, 0x02, 0, 0}, {0x350d, 0xe4, 0, 0}, {0x3621, 0xc9, 0, 0},
++ {0x370a, 0x81, 0, 0}, {0x3803, 0x08, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x3806, 0x02, 0, 0}, {0x3807, 0xd0, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x08, 0, 0}, {0x380d, 0x72, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0xc0, 0, 0},
++ {0x3818, 0xc9, 0, 0}, {0x381c, 0x10, 0, 0}, {0x381d, 0xa0, 0, 0},
++ {0x381e, 0x05, 0, 0}, {0x381f, 0xb0, 0, 0}, {0x3820, 0x00, 0, 0},
++ {0x3821, 0x00, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3a08, 0x1b, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x17, 0, 0}, {0x3a0b, 0x20, 0, 0},
++ {0x3a0d, 0x02, 0, 0}, {0x3a0e, 0x01, 0, 0}, {0x401c, 0x04, 0, 0},
++ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, {0x5686, 0x02, 0, 0},
++ {0x5687, 0xcc, 0, 0}, {0x5001, 0x7f, 0, 0}, {0x589b, 0x06, 0, 0},
++ {0x589a, 0xc5, 0, 0}, {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0},
++ {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0},
++ {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_1080P_1920_1080[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0},
++ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0},
++ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0},
++ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0},
++ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0},
++ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0},
++ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0},
++ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0},
++ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0},
++ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0},
++ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0},
++ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0},
++ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0},
++ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0},
++ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0},
++ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0},
++ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0},
++ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0},
++ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0},
++ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0},
++ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0},
++ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0},
++ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0},
++ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0},
++ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0},
++ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0},
++ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0},
++ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0},
++ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0},
++ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0},
++ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0},
++ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0},
++ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0},
++ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0},
++ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0},
++ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0},
++ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0},
++ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0},
++ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0},
++ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0},
++ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0},
++ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0},
++ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0},
++ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0},
++ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0},
++ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0},
++ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0},
++ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0},
++ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0},
++ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0},
++ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0},
++ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0},
++ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0},
++ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0},
++ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0},
++ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0},
++ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0},
++ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0},
++ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0},
++ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0},
++ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0},
++ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0},
++ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0},
++ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0},
++ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0},
++ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0},
++ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0},
++ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0},
++ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0},
++ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0},
++ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0},
++ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0},
++ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0},
++ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0},
++ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0},
++ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0},
++ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0},
++ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0},
++ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0},
++ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0},
++ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0},
++ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0},
++ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0},
++ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0},
++ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0},
++ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0},
++ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0},
++ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0},
++ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0},
++ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0},
++ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0},
++ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0},
++ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0},
++ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0},
++ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0},
++ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0},
++ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0},
++ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0},
++ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0},
++ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0},
++ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0},
++ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0},
++ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0},
++ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0},
++ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0},
++ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0},
++ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0},
++ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0},
++ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0},
++ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0},
++ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0},
++ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0},
++ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0},
++ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0},
++ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0},
++ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0},
++ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0},
++ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0},
++ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0},
++ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0},
++ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0},
++ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0},
++ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0},
++ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0},
++ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0},
++ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x07, 0, 0},
++ {0x350c, 0x04, 0, 0}, {0x350d, 0x58, 0, 0}, {0x3801, 0x8a, 0, 0},
++ {0x3803, 0x0a, 0, 0}, {0x3804, 0x07, 0, 0}, {0x3805, 0x80, 0, 0},
++ {0x3806, 0x04, 0, 0}, {0x3807, 0x39, 0, 0}, {0x3808, 0x07, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0},
++ {0x380c, 0x09, 0, 0}, {0x380d, 0xd6, 0, 0}, {0x380e, 0x04, 0, 0},
++ {0x380f, 0x58, 0, 0}, {0x381c, 0x11, 0, 0}, {0x381d, 0xba, 0, 0},
++ {0x381e, 0x04, 0, 0}, {0x381f, 0x48, 0, 0}, {0x3820, 0x04, 0, 0},
++ {0x3821, 0x18, 0, 0}, {0x3a08, 0x14, 0, 0}, {0x3a09, 0xe0, 0, 0},
++ {0x3a0a, 0x11, 0, 0}, {0x3a0b, 0x60, 0, 0}, {0x3a0d, 0x04, 0, 0},
++ {0x3a0e, 0x03, 0, 0}, {0x5682, 0x07, 0, 0}, {0x5683, 0x60, 0, 0},
++ {0x5686, 0x04, 0, 0}, {0x5687, 0x1c, 0, 0}, {0x5001, 0x7f, 0, 0},
++ {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0}, {0x471d, 0x05, 0, 0},
++ {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0}, {0x501f, 0x00, 0, 0},
++ {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0},
++ {0x5002, 0xe0, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_QVGA_320_240[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0},
++ {0x380b, 0xf0, 0, 0}, {0x3a00, 0x78, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_NTSC_720_480[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3824, 0x11, 0, 0}, {0x3825, 0xb4, 0, 0}, {0x3826, 0x00, 0, 0},
++ {0x3827, 0x3d, 0, 0}, {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380A, 0x01, 0, 0}, {0x380B, 0xe0, 0, 0},
++ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x3806, 0x03, 0, 0},
++ {0x3807, 0x55, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0x55, 0, 0},
++ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++};
++
++static struct reg_value ov5642_setting_15fps_PAL_720_576[] = {
++ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0},
++ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0},
++ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0},
++ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0},
++ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0},
++ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0},
++ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0},
++ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0},
++ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0},
++ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0},
++ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0},
++ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0},
++ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0},
++ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0},
++ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0},
++ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0},
++ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0},
++ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0},
++ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0},
++ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0},
++ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0},
++ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0},
++ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0},
++ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0},
++ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0},
++ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0},
++ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0},
++ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0},
++ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0},
++ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0},
++ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0},
++ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0},
++ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0},
++ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0},
++ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0},
++ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0},
++ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0},
++ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0},
++ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0},
++ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0},
++ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0},
++ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0},
++ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0},
++ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0},
++ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0},
++ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0},
++ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0},
++ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0},
++ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0},
++ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0},
++ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0},
++ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0},
++ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0},
++ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0},
++ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0},
++ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0},
++ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0},
++ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0},
++ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0},
++ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0},
++ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0},
++ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0},
++ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0},
++ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0},
++ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0},
++ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0},
++ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0},
++ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0},
++ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0},
++ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0},
++ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0},
++ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0},
++ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0},
++ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0},
++ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0},
++ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0},
++ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0},
++ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0},
++ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0},
++ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0},
++ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0},
++ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0},
++ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0},
++ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0},
++ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0},
++ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0},
++ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0},
++ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0},
++ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0},
++ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0},
++ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0},
++ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0},
++ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0},
++ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0},
++ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0},
++ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0},
++ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0},
++ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0},
++ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0},
++ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0},
++ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0},
++ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0},
++ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0},
++ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0},
++ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0},
++ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0},
++ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0},
++ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0},
++ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0},
++ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0},
++ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0},
++ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0},
++ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0},
++ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0},
++ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0},
++ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0},
++ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0},
++ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0},
++ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0},
++ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0},
++ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0},
++ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0},
++ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0},
++ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0},
++ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0},
++ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0},
++ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0},
++ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0},
++ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0},
++ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0},
++ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0},
++ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0},
++ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0},
++ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0},
++ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0},
++ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0},
++ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0},
++ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0},
++ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0},
++ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0},
++ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0},
++ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0},
++ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0},
++ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0},
++ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0},
++ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0},
++ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0},
++ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0},
++ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0},
++ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0},
++ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0},
++ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0},
++ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0},
++ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0},
++ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0},
++ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0},
++ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0},
++ {0x3824, 0x11, 0, 0}, {0x3825, 0xdc, 0, 0}, {0x3826, 0x00, 0, 0},
++ {0x3827, 0x08, 0, 0}, {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, {0x3808, 0x02, 0, 0},
++ {0x3809, 0xd0, 0, 0}, {0x380A, 0x02, 0, 0}, {0x380B, 0x40, 0, 0},
++ {0x3804, 0x04, 0, 0}, {0x3805, 0xb0, 0, 0}, {0x3806, 0x03, 0, 0},
++ {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0xc0, 0, 0},
++ {0x5682, 0x04, 0, 0}, {0x5683, 0xb0, 0, 0},
++};
++
++static struct ov5642_mode_info ov5642_mode_info_data[2][ov5642_mode_MAX + 1] = {
++ {
++ {ov5642_mode_VGA_640_480, 640, 480,
++ ov5642_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5642_setting_15fps_VGA_640_480)},
++ {ov5642_mode_QVGA_320_240, 320, 240,
++ ov5642_setting_15fps_QVGA_320_240,
++ ARRAY_SIZE(ov5642_setting_15fps_QVGA_320_240)},
++ {ov5642_mode_NTSC_720_480, 720, 480,
++ ov5642_setting_15fps_NTSC_720_480,
++ ARRAY_SIZE(ov5642_setting_15fps_NTSC_720_480)},
++ {ov5642_mode_PAL_720_576, 720, 576,
++ ov5642_setting_15fps_PAL_720_576,
++ ARRAY_SIZE(ov5642_setting_15fps_PAL_720_576)},
++ {ov5642_mode_720P_1280_720, 1280, 720,
++ ov5642_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5642_setting_15fps_720P_1280_720)},
++ {ov5642_mode_1080P_1920_1080, 1920, 1080,
++ ov5642_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5642_setting_15fps_1080P_1920_1080)},
++ {ov5642_mode_QSXGA_2592_1944, 2592, 1944,
++ ov5642_setting_15fps_QSXGA_2592_1944,
++ ARRAY_SIZE(ov5642_setting_15fps_QSXGA_2592_1944)},
++ {ov5642_mode_QCIF_176_144, 176, 144,
++ ov5642_setting_15fps_QCIF_176_144,
++ ARRAY_SIZE(ov5642_setting_15fps_QCIF_176_144)},
++ {ov5642_mode_XGA_1024_768, 1024, 768,
++ ov5642_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5642_setting_15fps_XGA_1024_768)},
++ },
++ {
++ {ov5642_mode_VGA_640_480, 640, 480,
++ ov5642_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5642_setting_30fps_VGA_640_480)},
++ {ov5642_mode_QVGA_320_240, 320, 240,
++ ov5642_setting_30fps_QVGA_320_240,
++ ARRAY_SIZE(ov5642_setting_30fps_QVGA_320_240)},
++ {ov5642_mode_NTSC_720_480, 720, 480,
++ ov5642_setting_30fps_NTSC_720_480,
++ ARRAY_SIZE(ov5642_setting_30fps_NTSC_720_480)},
++ {ov5642_mode_PAL_720_576, 720, 576,
++ ov5642_setting_30fps_PAL_720_576,
++ ARRAY_SIZE(ov5642_setting_30fps_PAL_720_576)},
++ {ov5642_mode_720P_1280_720, 1280, 720,
++ ov5642_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5642_setting_30fps_720P_1280_720)},
++ {ov5642_mode_1080P_1920_1080, 0, 0, NULL, 0},
++ {ov5642_mode_QSXGA_2592_1944, 0, 0, NULL, 0},
++ {ov5642_mode_QCIF_176_144, 176, 144,
++ ov5642_setting_30fps_QCIF_176_144,
++ ARRAY_SIZE(ov5642_setting_30fps_QCIF_176_144)},
++ {ov5642_mode_XGA_1024_768, 1024, 768,
++ ov5642_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5642_setting_30fps_XGA_1024_768)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++static struct regulator *gpo_regulator;
++
++static int ov5642_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5642_remove(struct i2c_client *client);
++
++static s32 ov5642_read_reg(u16 reg, u8 *val);
++static s32 ov5642_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5642_id[] = {
++ {"ov5642", 0},
++ {"ov564x", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5642_id);
++
++static struct i2c_driver ov5642_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov5642",
++ },
++ .probe = ov5642_probe,
++ .remove = ov5642_remove,
++ .id_table = ov5642_id,
++};
++
++static void ov5642_standby(s32 enable)
++{
++ if (enable)
++ gpio_set_value(pwn_gpio, 1);
++ else
++ gpio_set_value(pwn_gpio, 0);
++
++ msleep(2);
++}
++
++static void ov5642_reset(void)
++{
++ /* camera reset */
++ gpio_set_value(rst_gpio, 1);
++
++ /* camera power down */
++ gpio_set_value(pwn_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 0);
++ msleep(5);
++
++ gpio_set_value(rst_gpio, 0);
++ msleep(1);
++
++ gpio_set_value(rst_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, 1);
++}
++
++static int ov5642_power_on(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5642_VOLTAGE_DIGITAL_IO,
++ OV5642_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ pr_err("%s:io set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:io set voltage ok\n", __func__);
++ }
++ } else {
++ pr_err("%s: cannot get io voltage error\n", __func__);
++ io_regulator = NULL;
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5642_VOLTAGE_DIGITAL_CORE,
++ OV5642_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ pr_err("%s:core set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:core set voltage ok\n", __func__);
++ }
++ } else {
++ core_regulator = NULL;
++ pr_err("%s: cannot get core voltage error\n", __func__);
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5642_VOLTAGE_ANALOG,
++ OV5642_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ pr_err("%s:analog set voltage error\n",
++ __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:analog set voltage ok\n", __func__);
++ }
++ } else {
++ analog_regulator = NULL;
++ pr_err("%s: cannot get analog voltage error\n", __func__);
++ }
++
++ return ret;
++}
++
++static s32 ov5642_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++
++ return 0;
++}
++
++static s32 ov5642_read_reg(u16 reg, u8 *val)
++{
++ u8 au8RegBuf[2] = {0};
++ u8 u8RdVal = 0;
++
++ au8RegBuf[0] = reg >> 8;
++ au8RegBuf[1] = reg & 0xff;
++
++ if (2 != i2c_master_send(ov5642_data.i2c_client, au8RegBuf, 2)) {
++ pr_err("%s:write reg error:reg=%x\n",
++ __func__, reg);
++ return -1;
++ }
++
++ if (1 != i2c_master_recv(ov5642_data.i2c_client, &u8RdVal, 1)) {
++ pr_err("%s:read reg error:reg=%x,val=%x\n",
++ __func__, reg, u8RdVal);
++ return -1;
++ }
++
++ *val = u8RdVal;
++
++ return u8RdVal;
++}
++
++static int ov5642_set_idle_mode(void) {
++ register u16 RegAddr = 0;
++ u8 ReadVal = 0;
++ u8 WriteVal = 0;
++ int retval = 0;
++ int lc = 0;
++
++ ReadVal = -1;
++ RegAddr = REG_STA_FOCUS;
++ retval = ov5642_read_reg(RegAddr, &ReadVal);
++ if (retval < 0) {
++ pr_err("%s, read reg 0x%x failed\n", __FUNCTION__, RegAddr);
++ }
++
++ for (lc = 0; (lc < 100) && (ReadVal != S_IDLE); ++lc) {
++ WriteVal = CMD_IDLE_MODE;
++ RegAddr = REG_CMD_MAIN;
++ retval = ov5642_write_reg(RegAddr, WriteVal);
++ if (retval < 0) {
++ pr_err("%s, write reg 0x%x failed\n", __FUNCTION__, RegAddr);
++ }
++
++ mdelay(1);
++
++ ReadVal = -1;
++ RegAddr = REG_STA_FOCUS;
++ retval = ov5642_read_reg(RegAddr, &ReadVal);
++ if (retval < 0) {
++ pr_err("%s, read reg 0x%x failed\n", __FUNCTION__, RegAddr);
++ }
++ }
++
++ if (ReadVal != S_IDLE)
++ retval = -1;
++ else
++ retval = 0;
++ return retval;
++}
++
++static int ov5642_config_auto_focus(void){
++ ov5642_write_reg(REG_CMD_TAG, 0x01);
++ ov5642_write_reg(REG_CMD_MAIN, 0x10);
++ return 0;
++}
++
++static int ov5642_set_rot_mode(struct reg_value *rot_mode)
++{
++ s32 i = 0;
++ s32 iModeSettingArySize = 2;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++ for (i = 0; i < iModeSettingArySize; ++i, ++rot_mode) {
++ Delay_ms = rot_mode->u32Delay_ms;
++ RegAddr = rot_mode->u16RegAddr;
++ Val = rot_mode->u8Val;
++ Mask = rot_mode->u8Mask;
++
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0) {
++ pr_err("%s, read reg 0x%x failed\n",
++ __func__, RegAddr);
++ goto err;
++ }
++
++ Val |= RegVal;
++ Val &= Mask;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0) {
++ pr_err("%s, write reg 0x%x failed\n",
++ __func__, RegAddr);
++ goto err;
++ }
++
++ if (Delay_ms)
++ mdelay(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++static int ov5642_auto_focus_start(void) {
++ register u16 RegAddr = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++
++ retval = ov5642_set_idle_mode();
++ ov5642_config_auto_focus();
++
++ if (retval > -1) {
++ RegVal = CMD_SINGLE_FOCUS_MODE;
++ RegAddr = REG_CMD_MAIN;
++ retval = ov5642_write_reg(RegAddr, RegVal);
++ if (retval < 0) {
++ pr_err("%s, write reg 0x%x failed\n", __FUNCTION__, RegAddr);
++ }
++ } else {
++ pr_err("Could not get camera into idle mode. Abandoning focus attempt");
++ }
++
++ return retval;
++}
++
++static int ov5642_init_mode(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode);
++static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode);
++static int ov5642_change_mode(enum ov5642_frame_rate new_frame_rate,
++ enum ov5642_frame_rate old_frame_rate,
++ enum ov5642_mode new_mode,
++ enum ov5642_mode orig_mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 i = 0;
++ s32 iModeSettingArySize = 0;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++
++ if (new_mode > ov5642_mode_MAX || new_mode < ov5642_mode_MIN) {
++ pr_err("Wrong ov5642 mode detected!\n");
++ return -1;
++ }
++
++ if ((new_frame_rate == old_frame_rate) &&
++ (new_mode == ov5642_mode_VGA_640_480) &&
++ (orig_mode == ov5642_mode_QSXGA_2592_1944)) {
++ pModeSetting = ov5642_setting_QSXGA_2_VGA;
++ iModeSettingArySize = ARRAY_SIZE(ov5642_setting_QSXGA_2_VGA);
++ ov5642_data.pix.width = 640;
++ ov5642_data.pix.height = 480;
++ } else if ((new_frame_rate == old_frame_rate) &&
++ (new_mode == ov5642_mode_QVGA_320_240) &&
++ (orig_mode == ov5642_mode_VGA_640_480)) {
++ pModeSetting = ov5642_setting_VGA_2_QVGA;
++ iModeSettingArySize = ARRAY_SIZE(ov5642_setting_VGA_2_QVGA);
++ ov5642_data.pix.width = 320;
++ ov5642_data.pix.height = 240;
++ } else {
++ retval = ov5642_write_snapshot_para(new_frame_rate, new_mode);
++ goto err;
++ }
++
++ if (ov5642_data.pix.width == 0 || ov5642_data.pix.height == 0 ||
++ pModeSetting == NULL || iModeSettingArySize == 0)
++ return -EINVAL;
++
++ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0) {
++ pr_err("read reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0) {
++ pr_err("write reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++static int ov5642_init_mode(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 i = 0;
++ s32 iModeSettingArySize = 0;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++
++ if (mode > ov5642_mode_MAX || mode < ov5642_mode_MIN) {
++ pr_err("Wrong ov5642 mode detected!\n");
++ return -1;
++ }
++
++ pModeSetting = ov5642_mode_info_data[frame_rate][mode].init_data_ptr;
++ iModeSettingArySize =
++ ov5642_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5642_data.pix.width = ov5642_mode_info_data[frame_rate][mode].width;
++ ov5642_data.pix.height = ov5642_mode_info_data[frame_rate][mode].height;
++
++ if (ov5642_data.pix.width == 0 || ov5642_data.pix.height == 0 ||
++ pModeSetting == NULL || iModeSettingArySize == 0)
++ return -EINVAL;
++
++ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0) {
++ pr_err("read reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0) {
++ pr_err("write reg error addr=0x%x", RegAddr);
++ goto err;
++ }
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate,
++ enum ov5642_mode mode)
++{
++ int ret = 0;
++ bool m_60Hz = false;
++ u16 cap_frame_rate = 50;
++ u16 g_prev_frame_rate = 225;
++
++ u8 ev_low, ev_mid, ev_high;
++ u8 ret_l, ret_m, ret_h, gain, lines_10ms;
++ u16 ulcap_ev, icap_gain, prev_maxlines;
++ u32 ulcap_ev_gain, cap_maxlines, g_prev_ev;
++
++ ov5642_write_reg(0x3503, 0x07);
++
++ ret_h = ret_m = ret_l = 0;
++ g_prev_ev = 0;
++ ov5642_read_reg(0x3500, &ret_h);
++ ov5642_read_reg(0x3501, &ret_m);
++ ov5642_read_reg(0x3502, &ret_l);
++ g_prev_ev = (ret_h << 12) + (ret_m << 4) + (ret_l >> 4);
++
++ ret_h = ret_m = ret_l = 0;
++ prev_maxlines = 0;
++ ov5642_read_reg(0x380e, &ret_h);
++ ov5642_read_reg(0x380f, &ret_l);
++ prev_maxlines = (ret_h << 8) + ret_l;
++ /*Read back AGC Gain for preview*/
++ gain = 0;
++ ov5642_read_reg(0x350b, &gain);
++
++ ret = ov5642_init_mode(frame_rate, mode);
++ if (ret < 0)
++ return ret;
++
++ ret_h = ret_m = ret_l = 0;
++ ov5642_read_reg(0x380e, &ret_h);
++ ov5642_read_reg(0x380f, &ret_l);
++ cap_maxlines = (ret_h << 8) + ret_l;
++ if (m_60Hz == true)
++ lines_10ms = cap_frame_rate * cap_maxlines/12000;
++ else
++ lines_10ms = cap_frame_rate * cap_maxlines/10000;
++
++ if (prev_maxlines == 0)
++ prev_maxlines = 1;
++
++ ulcap_ev = (g_prev_ev*(cap_frame_rate)*(cap_maxlines))/
++ (((prev_maxlines)*(g_prev_frame_rate)));
++ icap_gain = (gain & 0x0f) + 16;
++ if (gain & 0x10)
++ icap_gain = icap_gain << 1;
++
++ if (gain & 0x20)
++ icap_gain = icap_gain << 1;
++
++ if (gain & 0x40)
++ icap_gain = icap_gain << 1;
++
++ if (gain & 0x80)
++ icap_gain = icap_gain << 1;
++
++ ulcap_ev_gain = 2 * ulcap_ev * icap_gain;
++
++ if (ulcap_ev_gain < cap_maxlines*16) {
++ ulcap_ev = ulcap_ev_gain/16;
++ if (ulcap_ev > lines_10ms) {
++ ulcap_ev /= lines_10ms;
++ ulcap_ev *= lines_10ms;
++ }
++ } else
++ ulcap_ev = cap_maxlines;
++
++ if (ulcap_ev == 0)
++ ulcap_ev = 1;
++
++ icap_gain = (ulcap_ev_gain*2/ulcap_ev + 1)/2;
++ ev_low = ((unsigned char)ulcap_ev)<<4;
++ ev_mid = (unsigned char)(ulcap_ev >> 4) & 0xff;
++ ev_high = (unsigned char)(ulcap_ev >> 12);
++
++ gain = 0;
++ if (icap_gain > 31) {
++ gain |= 0x10;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 31) {
++ gain |= 0x20;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 31) {
++ gain |= 0x40;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 31) {
++ gain |= 0x80;
++ icap_gain = icap_gain >> 1;
++ }
++ if (icap_gain > 16)
++ gain |= ((icap_gain - 16) & 0x0f);
++
++ if (gain == 0x10)
++ gain = 0x11;
++
++ ov5642_write_reg(0x350b, gain);
++ ov5642_write_reg(0x3502, ev_low);
++ ov5642_write_reg(0x3501, ev_mid);
++ ov5642_write_reg(0x3500, ev_high);
++ msleep(500);
++
++ return ret ;
++}
++
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = ov5642_data.mclk;
++ pr_debug(" clock_curr=mclk=%d\n", ov5642_data.mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_min = OV5642_XCLK_MIN;
++ p->u.bt656.clock_max = OV5642_XCLK_MAX;
++ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor_data *sensor = s->priv;
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (gpo_regulator)
++ if (regulator_enable(gpo_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5642_standby(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ ov5642_standby(1);
++ }
++
++ sensor->on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps, old_fps; /* target frames per secound */
++ enum ov5642_frame_rate new_frame_rate, old_frame_rate;
++ int ret = 0;
++
++ /* Make sure power on */
++ ov5642_standby(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ new_frame_rate = ov5642_15_fps;
++ else if (tgt_fps == 30)
++ new_frame_rate = ov5642_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ return -EINVAL;
++ }
++
++ if (sensor->streamcap.timeperframe.numerator != 0)
++ old_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++ else
++ old_fps = 30;
++
++ if (old_fps == 15)
++ old_frame_rate = ov5642_15_fps;
++ else if (old_fps == 30)
++ old_frame_rate = ov5642_30_fps;
++ else {
++ pr_warning(" No valid frame rate set!\n");
++ old_frame_rate = ov5642_30_fps;
++ }
++
++ ret = ov5642_change_mode(new_frame_rate, old_frame_rate,
++ a->parm.capture.capturemode,
++ sensor->streamcap.capturemode);
++ if (ret < 0)
++ return ret;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode =
++ (u32)a->parm.capture.capturemode;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor_data *sensor = s->priv;
++
++ f->fmt.pix = sensor->pix;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = ov5642_data.brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = ov5642_data.hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = ov5642_data.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = ov5642_data.saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = ov5642_data.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = ov5642_data.blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = ov5642_data.ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++ struct sensor_data *sensor = s->priv;
++ __u32 captureMode = sensor->streamcap.capturemode;
++ struct reg_value *rot_mode = NULL;
++
++ pr_debug("In ov5642:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_AUTO_FOCUS_START:
++ retval = ov5642_auto_focus_start();
++ break;
++ case V4L2_CID_AUTO_FOCUS_STOP:
++ retval = ov5642_set_idle_mode();
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ case V4L2_CID_MXC_ROT:
++ case V4L2_CID_MXC_VF_ROT:
++ switch (vc->value) {
++ case V4L2_MXC_ROTATE_NONE:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_none_FULL;
++ else
++ rot_mode = ov5642_rot_none_VGA;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ case V4L2_MXC_ROTATE_VERT_FLIP:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_vert_flip_FULL;
++ else
++ rot_mode = ov5642_rot_vert_flip_VGA ;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ case V4L2_MXC_ROTATE_HORIZ_FLIP:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_horiz_flip_FULL;
++ else
++ rot_mode = ov5642_rot_horiz_flip_VGA;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ case V4L2_MXC_ROTATE_180:
++ if (captureMode == ov5642_mode_QSXGA_2592_1944)
++ rot_mode = ov5642_rot_180_FULL;
++ else
++ rot_mode = ov5642_rot_180_VGA;
++
++ if (ov5642_set_rot_mode(rot_mode))
++ retval = -EPERM;
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++static int ioctl_send_command(struct v4l2_int_device *s, struct v4l2_send_command_control *vc) {
++ int ret = -1;
++ int retval1,retval2;
++ u8 loca_val=0;
++
++ ret = ov5642_set_idle_mode();
++ if (0 != ret)
++ pr_err("error %d setting idle mode\n", ret);
++ ov5642_config_auto_focus();
++ switch (vc->id) {
++ case 101: //step to near
++ pr_debug("Stepping to near object\n");
++ retval1=ov5642_write_reg(REG_CMD_TAG, 0x01);
++ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05);
++ if(retval1 == 0 && retval2 == 0)
++ ret = 0;
++ break;
++ case 102: //step to far
++ pr_debug("Stepping to far object\n");
++ retval1=ov5642_write_reg(REG_CMD_TAG, 0x02);
++ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05);
++ if(retval1 == 0 && retval2 == 0)
++ ret = 0;
++ break;
++
++ case 103: //step to furthest
++ pr_debug("Stepping to furthest object\n");
++ retval1=ov5642_write_reg(REG_CMD_TAG, 0x03);
++ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05);
++ if(retval1 == 0 && retval2 == 0)
++ ret = 0;
++ break;
++
++ case 104: //step to nearest
++ pr_debug("Stepping to nearest object\n");
++ retval1=ov5642_write_reg(REG_CMD_TAG, 0x04);
++ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05);
++ if(retval1 == 0 && retval2 == 0)
++ ret = 0;
++ break;
++
++
++ case 105: //step to specified position
++ pr_debug("Stepping to position: %d\n", vc->value0);
++ if(vc->value0 < 0 || vc->value0 > 255)
++ return ret;
++ loca_val = vc->value0;
++ retval1=ov5642_write_reg(REG_CMD_TAG, 0x10);
++ retval2=ov5642_write_reg(REG_CMD_PARA0, loca_val);
++ ret=ov5642_write_reg(REG_CMD_MAIN, 0x05);
++ if(retval1 != 0 && retval2 != 0 && ret != 0)
++ ret = -1;
++ break;
++ default:
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5642_mode_MAX)
++ return -EINVAL;
++
++ fsize->pixel_format = ov5642_data.pix.pixelformat;
++ fsize->discrete.width =
++ max(ov5642_mode_info_data[0][fsize->index].width,
++ ov5642_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5642_mode_info_data[0][fsize->index].height,
++ ov5642_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ioctl_enum_frameintervals - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMEINTERVALS ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
++ struct v4l2_frmivalenum *fival)
++{
++ int i, j, count;
++
++ if (fival->index < 0 || fival->index > ov5642_mode_MAX)
++ return -EINVAL;
++
++ if (fival->pixel_format == 0 || fival->width == 0 ||
++ fival->height == 0) {
++ pr_warning("Please assign pixelformat, width and height.\n");
++ return -EINVAL;
++ }
++
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++
++ count = 0;
++ for (i = 0; i < ARRAY_SIZE(ov5642_mode_info_data); i++) {
++ for (j = 0; j < (ov5642_mode_MAX + 1); j++) {
++ if (fival->pixel_format == ov5642_data.pix.pixelformat
++ && fival->width == ov5642_mode_info_data[i][j].width
++ && fival->height == ov5642_mode_info_data[i][j].height
++ && ov5642_mode_info_data[i][j].init_data_ptr != NULL) {
++ count++;
++ }
++ if (fival->index == (count - 1)) {
++ fival->discrete.denominator =
++ ov5642_framerates[i];
++ return 0;
++ }
++ }
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5642_camera");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index > 0) /* only 1 pixelformat support so far */
++ return -EINVAL;
++
++ fmt->pixelformat = ov5642_data.pix.pixelformat;
++
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 i = 0;
++ s32 iModeSettingArySize = 0;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int retval = 0;
++
++ struct sensor_data *sensor = s->priv;
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5642_frame_rate frame_rate;
++
++ ov5642_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5642_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5642_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5642_XCLK_MIN);
++ ov5642_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5642_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5642_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ pModeSetting = ov5642_initial_setting;
++ iModeSettingArySize = ARRAY_SIZE(ov5642_initial_setting);
++
++ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++ if (Mask) {
++ retval = ov5642_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5642_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc ov5642_ioctl_desc[] = {
++ { vidioc_int_dev_init_num,
++ (v4l2_int_ioctl_func *)ioctl_dev_init },
++ { vidioc_int_dev_exit_num, ioctl_dev_exit},
++ { vidioc_int_s_power_num,
++ (v4l2_int_ioctl_func *)ioctl_s_power },
++ { vidioc_int_g_ifparm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ifparm },
++/* { vidioc_int_g_needs_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_g_needs_reset }, */
++/* { vidioc_int_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_reset }, */
++ { vidioc_int_init_num,
++ (v4l2_int_ioctl_func *)ioctl_init },
++ { vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap },
++/* { vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap }, */
++ { vidioc_int_g_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_g_fmt_cap },
++/* { vidioc_int_s_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_s_fmt_cap }, */
++ { vidioc_int_g_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_g_parm },
++ { vidioc_int_s_parm_num,
++ (v4l2_int_ioctl_func *)ioctl_s_parm },
++/* { vidioc_int_queryctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_queryctrl }, */
++ { vidioc_int_g_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_g_ctrl },
++ { vidioc_int_s_ctrl_num,
++ (v4l2_int_ioctl_func *)ioctl_s_ctrl },
++ { vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_framesizes },
++ { vidioc_int_enum_frameintervals_num,
++ (v4l2_int_ioctl_func *)ioctl_enum_frameintervals },
++ { vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *)ioctl_g_chip_ident },
++ {vidioc_int_send_command_num,
++ (v4l2_int_ioctl_func *) ioctl_send_command},
++};
++
++static struct v4l2_int_slave ov5642_slave = {
++ .ioctls = ov5642_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(ov5642_ioctl_desc),
++};
++
++static struct v4l2_int_device ov5642_int_device = {
++ .module = THIS_MODULE,
++ .name = "ov5642",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &ov5642_slave,
++ },
++};
++
++/*!
++ * ov5642 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5642_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct pinctrl *pinctrl;
++ struct device *dev = &client->dev;
++ int retval;
++ u8 chip_id_high, chip_id_low;
++ struct reg_value *firmware_regs;
++ int i;
++ struct sensor_data *sensor = &ov5642_data;
++
++ /* ov5642 pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "ov5642 setup pinctrl failed!");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_warn(dev, "no sensor pwdn pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5642_pwdn");
++ if (retval < 0)
++ return retval;
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(rst_gpio)) {
++ dev_warn(dev, "no sensor reset pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5642_reset");
++ if (retval < 0)
++ return retval;
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5642_data, 0, sizeof(ov5642_data));
++ ov5642_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5642_data.sensor_clk)) {
++ /* assuming clock enabled by default */
++ ov5642_data.sensor_clk = NULL;
++ dev_err(dev, "clock-frequency missing or invalid\n");
++ return PTR_ERR(ov5642_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ (u32 *) &(ov5642_data.mclk));
++ if (retval) {
++ dev_err(dev, "mclk missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5642_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "ipu_id",
++ &sensor->ipu_id);
++ if (retval) {
++ dev_err(dev, "ipu_id missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5642_data.csi));
++ if (retval) {
++ dev_err(dev, "csi_id missing or invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5642_data.sensor_clk);
++
++ ov5642_data.io_init = ov5642_reset;
++ ov5642_data.i2c_client = client;
++ ov5642_data.pix.pixelformat = V4L2_PIX_FMT_YUYV;
++ ov5642_data.pix.width = 640;
++ ov5642_data.pix.height = 480;
++ ov5642_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5642_data.streamcap.capturemode = 0;
++ ov5642_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5642_data.streamcap.timeperframe.numerator = 1;
++
++ ov5642_power_on(&client->dev);
++
++ ov5642_reset();
++
++ ov5642_standby(0);
++
++ retval = ov5642_read_reg(OV5642_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ pr_warning("camera ov5642 is not found\n");
++ clk_disable_unprepare(ov5642_data.sensor_clk);
++ return -ENODEV;
++ }
++ retval = ov5642_read_reg(OV5642_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x42) {
++ pr_warning("camera ov5642 is not found\n");
++ clk_disable_unprepare(ov5642_data.sensor_clk);
++ return -ENODEV;
++ }
++
++ ov5642_standby(1);
++
++ ov5642_int_device.priv = &ov5642_data;
++
++ pr_info("Upload Auto-focus firmware");
++ firmware_regs = ov5642_af_firmware;
++ for (i = 0; i < ARRAY_SIZE(ov5642_af_firmware); ++i, ++firmware_regs) {
++ retval = ov5642_write_reg(firmware_regs->u16RegAddr,
++ firmware_regs->u8Val);
++ if (retval < 0)
++ break;
++ }
++
++ retval = v4l2_int_device_register(&ov5642_int_device);
++
++ clk_disable_unprepare(ov5642_data.sensor_clk);
++
++ pr_info("camera ov5642 is found\n");
++ return retval;
++}
++
++/*!
++ * ov5642 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5642_remove(struct i2c_client *client)
++{
++ v4l2_int_device_unregister(&ov5642_int_device);
++
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++/*!
++ * ov5642 init function
++ * Called by insmod ov5642_camera.ko.
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int ov5642_init(void)
++{
++ u8 err;
++
++ err = i2c_add_driver(&ov5642_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * OV5642 cleanup function
++ * Called on rmmod ov5642_camera.ko
++ *
++ * @return Error code indicating success or failure
++ */
++static void __exit ov5642_clean(void)
++{
++ i2c_del_driver(&ov5642_i2c_driver);
++}
++
++module_init(ov5642_init);
++module_exit(ov5642_clean);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("OV5642 Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5647_mipi.c linux-3.14.72/drivers/media/platform/mxc/capture/ov5647_mipi.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/ov5647_mipi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/ov5647_mipi.c 2016-06-19 22:11:55.181148143 +0200
+@@ -0,0 +1,3781 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/of_device.h>
++#include <linux/i2c.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/fsl_devices.h>
++#include <linux/mipi_csi2.h>
++#include <media/v4l2-chip-ident.h>
++#include "v4l2-int-device.h"
++#include "mxc_v4l2_capture.h"
++
++#define OV5647_VOLTAGE_ANALOG 2800000
++#define OV5647_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5647_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5647_XCLK_MIN 6000000
++#define OV5647_XCLK_MAX 27000000
++
++#define OV5647_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5647_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5647_mode {
++ ov5647_mode_MIN = 0,
++ ov5647_mode_960P_1280_960 = 0,
++ ov5647_mode_720P_1280_720 = 1,
++ ov5647_mode_1080P_1920_1080 = 2,
++ ov5647_mode_VGA_640_480 = 3,
++ ov5647_mode_XGA_1024_768 = 4,
++ ov5647_mode_960_720 = 5,
++ ov5647_mode_VGA_640_480_narrow = 6,
++ ov5647_mode_MAX = 6,
++ ov5647_mode_INIT = 0xff, /*only for sensor init*/
++};
++
++enum ov5647_frame_rate {
++ ov5647_15_fps,
++ ov5647_30_fps
++};
++
++/* image size under 1280 * 960 are SUBSAMPLING
++ * image size upper 1280 * 960 are SCALING
++ */
++enum ov5647_downsize_mode {
++ SUBSAMPLING,
++ SCALING,
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5647_mode_info {
++ enum ov5647_mode mode;
++ enum ov5647_downsize_mode dn_mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct sensor_data ov5647_data;
++static struct additional_data ov5647_data_add;
++static int pwn_gpio = -EINVAL;
++static int powon_active;
++static int rst_gpio = -EINVAL;
++static int rst_active;
++static int led_gpio = -EINVAL;
++static int led_active;
++
++static struct reg_value ov5647_setting_30fps_960P_1280_960[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x21 , 0 , 0 } ,
++ { 0x3036 , 0x52 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x07 , 0 , 0 } ,
++ { 0x380d , 0x68 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x05 , 0 , 0 } ,
++ { 0x3809 , 0x00 , 0 , 0 } ,
++ { 0x380a , 0x03 , 0 , 0 } ,
++ { 0x380b , 0xc0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x07 , 0 , 0 } ,
++ { 0x3807 , 0xa1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_15fps_960P_1280_960[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0x52 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x07 , 0 , 0 } ,
++ { 0x380d , 0x68 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x05 , 0 , 0 } ,
++ { 0x3809 , 0x00 , 0 , 0 } ,
++ { 0x380a , 0x03 , 0 , 0 } ,
++ { 0x380b , 0xc0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x07 , 0 , 0 } ,
++ { 0x3807 , 0xa1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_30fps_720P_1280_720[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0xa0 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x06 , 0 , 0 } ,
++ { 0x380d , 0xd6 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x05 , 0 , 0 } ,
++ { 0x3809 , 0x00 , 0 , 0 } ,
++ { 0x380a , 0x02 , 0 , 0 } ,
++ { 0x380b , 0xd0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x06 , 0 , 0 } ,
++ { 0x3807 , 0xb2 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_15fps_720P_1280_720[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0x49 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x06 , 0 , 0 } ,
++ { 0x380d , 0xd6 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x05 , 0 , 0 } ,
++ { 0x3809 , 0x00 , 0 , 0 } ,
++ { 0x380a , 0x02 , 0 , 0 } ,
++ { 0x380b , 0xd0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x06 , 0 , 0 } ,
++ { 0x3807 , 0xb2 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_30fps_1080P_1920_1080[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x21 , 0 , 0 } ,
++ { 0x3036 , 0x7b , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x06 , 0 , 0 } ,
++ { 0x3820 , 0x00 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x04 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x36 , 0 , 0 } ,
++ { 0x380d , 0x4e , 0 , 0 } ,
++ { 0x380e , 0x04 , 0 , 0 } ,
++ { 0x380f , 0x60 , 0 , 0 } ,
++ { 0x3814 , 0x11 , 0 , 0 } ,
++ { 0x3815 , 0x11 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x07 , 0 , 0 } ,
++ { 0x3809 , 0x80 , 0 , 0 } ,
++ { 0x380a , 0x04 , 0 , 0 } ,
++ { 0x380b , 0x39 , 0 , 0 } ,
++ { 0x3800 , 0x01 , 0 , 0 } ,
++ { 0x3801 , 0x5c , 0 , 0 } ,
++ { 0x3802 , 0x01 , 0 , 0 } ,
++ { 0x3803 , 0xb2 , 0 , 0 } ,
++ { 0x3804 , 0x08 , 0 , 0 } ,
++ { 0x3805 , 0xe7 , 0 , 0 } ,
++ { 0x3806 , 0x05 , 0 , 0 } ,
++ { 0x3807 , 0xf1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_15fps_1080P_1920_1080[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0x7b , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x06 , 0 , 0 } ,
++ { 0x3820 , 0x00 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x04 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x36 , 0 , 0 } ,
++ { 0x380d , 0x4e , 0 , 0 } ,
++ { 0x380e , 0x04 , 0 , 0 } ,
++ { 0x380f , 0x60 , 0 , 0 } ,
++ { 0x3814 , 0x11 , 0 , 0 } ,
++ { 0x3815 , 0x11 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x07 , 0 , 0 } ,
++ { 0x3809 , 0x80 , 0 , 0 } ,
++ { 0x380a , 0x04 , 0 , 0 } ,
++ { 0x380b , 0x39 , 0 , 0 } ,
++ { 0x3800 , 0x01 , 0 , 0 } ,
++ { 0x3801 , 0x5c , 0 , 0 } ,
++ { 0x3802 , 0x01 , 0 , 0 } ,
++ { 0x3803 , 0xb2 , 0 , 0 } ,
++ { 0x3804 , 0x08 , 0 , 0 } ,
++ { 0x3805 , 0xe7 , 0 , 0 } ,
++ { 0x3806 , 0x05 , 0 , 0 } ,
++ { 0x3807 , 0xf1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_30fps_VGA_640_480[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x21 , 0 , 0 } ,
++ { 0x3036 , 0x52 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x07 , 0 , 0 } ,
++ { 0x380d , 0x68 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x71 , 0 , 0 } ,
++ { 0x3815 , 0x71 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x02 , 0 , 0 } ,
++ { 0x3809 , 0x80 , 0 , 0 } ,
++ { 0x380a , 0x01 , 0 , 0 } ,
++ { 0x380b , 0xe0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x07 , 0 , 0 } ,
++ { 0x3807 , 0xa1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++ { 0x3814 , 0x31 , 0 , 0 } , /* overwrite */
++ { 0x3815 , 0x31 , 0 , 0 } , /* overwrite */
++};
++
++static struct reg_value ov5647_setting_15fps_VGA_640_480[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0x52 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x07 , 0 , 0 } ,
++ { 0x380d , 0x68 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x71 , 0 , 0 } ,
++ { 0x3815 , 0x71 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x02 , 0 , 0 } ,
++ { 0x3809 , 0x80 , 0 , 0 } ,
++ { 0x380a , 0x01 , 0 , 0 } ,
++ { 0x380b , 0xe0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x07 , 0 , 0 } ,
++ { 0x3807 , 0xa1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++ { 0x3814 , 0x31 , 0 , 0 } , /* overwrite */
++ { 0x3815 , 0x31 , 0 , 0 } , /* overwrite */
++};
++
++static struct reg_value ov5647_setting_30fps_XGA_1024_768[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x21 , 0 , 0 } ,
++ { 0x3036 , 0x52 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x07 , 0 , 0 } ,
++ { 0x380d , 0x68 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x04 , 0 , 0 } ,
++ { 0x3809 , 0x00 , 0 , 0 } ,
++ { 0x380a , 0x03 , 0 , 0 } ,
++ { 0x380b , 0x00 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x07 , 0 , 0 } ,
++ { 0x3807 , 0xa1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_15fps_XGA_1024_768[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0x52 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x07 , 0 , 0 } ,
++ { 0x380d , 0x68 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x04 , 0 , 0 } ,
++ { 0x3809 , 0x00 , 0 , 0 } ,
++ { 0x380a , 0x03 , 0 , 0 } ,
++ { 0x380b , 0x00 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x07 , 0 , 0 } ,
++ { 0x3807 , 0xa1 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_30fps_960_720[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0xa0 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x06 , 0 , 0 } ,
++ { 0x380d , 0xd6 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x03 , 0 , 0 } ,
++ { 0x3809 , 0xc0 , 0 , 0 } ,
++ { 0x380a , 0x02 , 0 , 0 } ,
++ { 0x380b , 0xd0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x06 , 0 , 0 } ,
++ { 0x3807 , 0xb2 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct reg_value ov5647_setting_15fps_960_720[] = {
++ { 0x0100 , 0x00 , 0 , 0 } ,
++ { 0x0103 , 0x01 , 0 , 0 } ,
++ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */
++ { 0x3035 , 0x41 , 0 , 0 } ,
++ { 0x3036 , 0x49 , 0 , 0 } ,
++ { 0x303c , 0x11 , 0 , 0 } ,
++ { 0x3106 , 0xf5 , 0 , 0 } ,
++ { 0x3821 , 0x07 , 0 , 0 } ,
++ { 0x3820 , 0x41 , 0 , 0 } ,
++ { 0x3827 , 0xec , 0 , 0 } ,
++ { 0x370c , 0x03 , 0 , 0 } ,
++ { 0x3612 , 0x4b , 0 , 0 } ,
++ { 0x3618 , 0x00 , 0 , 0 } ,
++ { 0x5001 , 0x01 , 0 , 0 } ,
++ { 0x5002 , 0x40 , 0 , 0 } ,
++ { 0x5003 , 0x08 , 0 , 0 } ,
++ { 0x5a00 , 0x08 , 0 , 0 } ,
++ { 0x3000 , 0x00 , 0 , 0 } ,
++ { 0x3001 , 0x00 , 0 , 0 } ,
++ { 0x3002 , 0x00 , 0 , 0 } ,
++ { 0x3016 , 0x08 , 0 , 0 } ,
++ { 0x3017 , 0xe0 , 0 , 0 } ,
++ { 0x3018 , 0x44 , 0 , 0 } ,
++ { 0x301c , 0xf8 , 0 , 0 } ,
++ { 0x301d , 0xf0 , 0 , 0 } ,
++ { 0x3a18 , 0x00 , 0 , 0 } ,
++ { 0x3a19 , 0xf8 , 0 , 0 } ,
++ { 0x3c01 , 0x80 , 0 , 0 } ,
++ { 0x3b07 , 0x0c , 0 , 0 } ,
++ { 0x380c , 0x06 , 0 , 0 } ,
++ { 0x380d , 0xd6 , 0 , 0 } ,
++ { 0x380e , 0x03 , 0 , 0 } ,
++ { 0x380f , 0xd8 , 0 , 0 } ,
++ { 0x3814 , 0x31 , 0 , 0 } ,
++ { 0x3815 , 0x31 , 0 , 0 } ,
++ { 0x3708 , 0x64 , 0 , 0 } ,
++ { 0x3709 , 0x52 , 0 , 0 } ,
++ { 0x3808 , 0x03 , 0 , 0 } ,
++ { 0x3809 , 0xc0 , 0 , 0 } ,
++ { 0x380a , 0x02 , 0 , 0 } ,
++ { 0x380b , 0xd0 , 0 , 0 } ,
++ { 0x3800 , 0x00 , 0 , 0 } ,
++ { 0x3801 , 0x00 , 0 , 0 } ,
++ { 0x3802 , 0x00 , 0 , 0 } ,
++ { 0x3803 , 0x00 , 0 , 0 } ,
++ { 0x3804 , 0x0a , 0 , 0 } ,
++ { 0x3805 , 0x3f , 0 , 0 } ,
++ { 0x3806 , 0x06 , 0 , 0 } ,
++ { 0x3807 , 0xb2 , 0 , 0 } ,
++ { 0x3811 , 0x08 , 0 , 0 } ,
++ { 0x3813 , 0x02 , 0 , 0 } ,
++ { 0x3630 , 0x2e , 0 , 0 } ,
++ { 0x3632 , 0xe2 , 0 , 0 } ,
++ { 0x3633 , 0x23 , 0 , 0 } ,
++ { 0x3634 , 0x44 , 0 , 0 } ,
++ { 0x3636 , 0x06 , 0 , 0 } ,
++ { 0x3620 , 0x64 , 0 , 0 } ,
++ { 0x3621 , 0xe0 , 0 , 0 } ,
++ { 0x3600 , 0x37 , 0 , 0 } ,
++ { 0x3704 , 0xa0 , 0 , 0 } ,
++ { 0x3703 , 0x5a , 0 , 0 } ,
++ { 0x3715 , 0x78 , 0 , 0 } ,
++ { 0x3717 , 0x01 , 0 , 0 } ,
++ { 0x3731 , 0x02 , 0 , 0 } ,
++ { 0x370b , 0x60 , 0 , 0 } ,
++ { 0x3705 , 0x1a , 0 , 0 } ,
++ { 0x3f05 , 0x02 , 0 , 0 } ,
++ { 0x3f06 , 0x10 , 0 , 0 } ,
++ { 0x3f01 , 0x0a , 0 , 0 } ,
++ { 0x3a08 , 0x01 , 0 , 0 } ,
++ { 0x3a09 , 0x27 , 0 , 0 } ,
++ { 0x3a0a , 0x00 , 0 , 0 } ,
++ { 0x3a0b , 0xf6 , 0 , 0 } ,
++ { 0x3a0d , 0x04 , 0 , 0 } ,
++ { 0x3a0e , 0x03 , 0 , 0 } ,
++ { 0x3a0f , 0x58 , 0 , 0 } ,
++ { 0x3a10 , 0x50 , 0 , 0 } ,
++ { 0x3a1b , 0x58 , 0 , 0 } ,
++ { 0x3a1e , 0x50 , 0 , 0 } ,
++ { 0x3a11 , 0x60 , 0 , 0 } ,
++ { 0x3a1f , 0x28 , 0 , 300 } ,
++ { 0x4001 , 0x02 , 0 , 0 } ,
++ { 0x4004 , 0x02 , 0 , 0 } ,
++ { 0x4000 , 0x09 , 0 , 0 } ,
++ { 0x4837 , 0x24 , 0 , 0 } ,
++ { 0x4050 , 0x6e , 0 , 0 } ,
++ { 0x4051 , 0x8f , 0 , 0 } ,
++ { 0x0100 , 0x01 , 0 , 0 } ,
++#if 0
++ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */
++ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */
++#endif
++ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */
++ { 0x5800 , 0x00 , 0 , 0 } ,
++ { 0x5801 , 0x00 , 0 , 0 } ,
++ { 0x5802 , 0x00 , 0 , 0 } ,
++ { 0x5803 , 0x00 , 0 , 0 } ,
++ { 0x5804 , 0x00 , 0 , 0 } ,
++ { 0x5805 , 0x00 , 0 , 0 } ,
++ { 0x5806 , 0x00 , 0 , 0 } ,
++ { 0x5807 , 0x00 , 0 , 0 } ,
++ { 0x5808 , 0x00 , 0 , 0 } ,
++ { 0x5809 , 0x00 , 0 , 0 } ,
++ { 0x580a , 0x00 , 0 , 0 } ,
++ { 0x580b , 0x00 , 0 , 0 } ,
++ { 0x580c , 0x00 , 0 , 0 } ,
++ { 0x580d , 0x00 , 0 , 0 } ,
++ { 0x580e , 0x00 , 0 , 0 } ,
++ { 0x580f , 0x00 , 0 , 0 } ,
++ { 0x5810 , 0x00 , 0 , 0 } ,
++ { 0x5811 , 0x00 , 0 , 0 } ,
++ { 0x5812 , 0x00 , 0 , 0 } ,
++ { 0x5813 , 0x00 , 0 , 0 } ,
++ { 0x5814 , 0x00 , 0 , 0 } ,
++ { 0x5815 , 0x00 , 0 , 0 } ,
++ { 0x5816 , 0x00 , 0 , 0 } ,
++ { 0x5817 , 0x00 , 0 , 0 } ,
++ { 0x5818 , 0x00 , 0 , 0 } ,
++ { 0x5819 , 0x00 , 0 , 0 } ,
++ { 0x581a , 0x00 , 0 , 0 } ,
++ { 0x581b , 0x00 , 0 , 0 } ,
++ { 0x581c , 0x00 , 0 , 0 } ,
++ { 0x581d , 0x00 , 0 , 0 } ,
++ { 0x581e , 0x00 , 0 , 0 } ,
++ { 0x581f , 0x00 , 0 , 0 } ,
++ { 0x5820 , 0x00 , 0 , 0 } ,
++ { 0x5821 , 0x00 , 0 , 0 } ,
++ { 0x5822 , 0x00 , 0 , 0 } ,
++ { 0x5823 , 0x00 , 0 , 0 } ,
++ { 0x5824 , 0xfe , 0 , 0 } ,
++ { 0x5825 , 0xfe , 0 , 0 } ,
++ { 0x5826 , 0xfe , 0 , 0 } ,
++ { 0x5827 , 0xfe , 0 , 0 } ,
++ { 0x5828 , 0xfe , 0 , 0 } ,
++ { 0x5829 , 0xfe , 0 , 0 } ,
++ { 0x582a , 0xed , 0 , 0 } ,
++ { 0x582b , 0xed , 0 , 0 } ,
++ { 0x582c , 0xed , 0 , 0 } ,
++ { 0x582d , 0xfe , 0 , 0 } ,
++ { 0x582e , 0xfe , 0 , 0 } ,
++ { 0x582f , 0xed , 0 , 0 } ,
++ { 0x5830 , 0xdc , 0 , 0 } ,
++ { 0x5831 , 0xed , 0 , 0 } ,
++ { 0x5832 , 0xfe , 0 , 0 } ,
++ { 0x5833 , 0xfe , 0 , 0 } ,
++ { 0x5834 , 0xed , 0 , 0 } ,
++ { 0x5835 , 0xed , 0 , 0 } ,
++ { 0x5836 , 0xed , 0 , 0 } ,
++ { 0x5837 , 0xfe , 0 , 0 } ,
++ { 0x5838 , 0xfe , 0 , 0 } ,
++ { 0x5839 , 0xfe , 0 , 0 } ,
++ { 0x583a , 0xfe , 0 , 0 } ,
++ { 0x583b , 0xfe , 0 , 0 } ,
++ { 0x583c , 0xfe , 0 , 0 } ,
++ { 0x583d , 0xce , 0 , 0 } ,
++ { 0x3501 , 0x10 , 0 , 0 } ,
++ { 0x3502 , 0x80 , 0 , 0 } ,
++ { 0x350a , 0x00 , 0 , 0 } ,
++ { 0x350b , 0x7f , 0 , 0 } ,
++ { 0x3c00 , 0x04 , 0 , 300 } ,
++ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */
++};
++
++static struct ov5647_mode_info ov5647_mode_info_data[2][ov5647_mode_MAX + 1] = {
++ {
++ {ov5647_mode_960P_1280_960, SUBSAMPLING, 1280, 960,
++ ov5647_setting_15fps_960P_1280_960,
++ ARRAY_SIZE(ov5647_setting_15fps_960P_1280_960)},
++ {ov5647_mode_720P_1280_720, SUBSAMPLING, 1280, 720,
++ ov5647_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5647_setting_15fps_720P_1280_720)},
++ {ov5647_mode_1080P_1920_1080, SCALING, 1920, 1080,
++ ov5647_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5647_setting_15fps_1080P_1920_1080)},
++ {ov5647_mode_VGA_640_480, SUBSAMPLING, 640, 480,
++ ov5647_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5647_setting_15fps_VGA_640_480) - 2},
++ {ov5647_mode_XGA_1024_768, SUBSAMPLING, 1024, 768,
++ ov5647_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5647_setting_15fps_XGA_1024_768)},
++ {ov5647_mode_960_720, SUBSAMPLING, 960, 720,
++ ov5647_setting_15fps_960_720,
++ ARRAY_SIZE(ov5647_setting_15fps_960_720)},
++ {ov5647_mode_VGA_640_480_narrow, SUBSAMPLING, 640, 480,
++ ov5647_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5647_setting_15fps_VGA_640_480)},
++ },
++ {
++ {ov5647_mode_960P_1280_960, SUBSAMPLING, 1280, 960,
++ ov5647_setting_30fps_960P_1280_960,
++ ARRAY_SIZE(ov5647_setting_30fps_960P_1280_960)},
++ {ov5647_mode_720P_1280_720, SUBSAMPLING, 1280, 720,
++ ov5647_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5647_setting_30fps_720P_1280_720)},
++ {ov5647_mode_1080P_1920_1080, SCALING, 1920, 1080,
++ ov5647_setting_30fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5647_setting_30fps_1080P_1920_1080)},
++ {ov5647_mode_VGA_640_480, SUBSAMPLING, 640, 480,
++ ov5647_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5647_setting_30fps_VGA_640_480) - 2},
++ {ov5647_mode_XGA_1024_768, SUBSAMPLING, 1024, 768,
++ ov5647_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5647_setting_30fps_XGA_1024_768)},
++ {ov5647_mode_960_720, SUBSAMPLING, 960, 720,
++ ov5647_setting_30fps_960_720,
++ ARRAY_SIZE(ov5647_setting_15fps_960_720)},
++ {ov5647_mode_VGA_640_480_narrow, SUBSAMPLING, 640, 480,
++ ov5647_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5647_setting_30fps_VGA_640_480)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++static struct regulator *gpo_regulator;
++
++static int ov5647_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5647_remove(struct i2c_client *client);
++
++static s32 ov5647_read_reg(u16 reg, u8 *val);
++static s32 ov5647_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5647_id[] = {
++ {"ov5647_mipi", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5647_id);
++
++static struct i2c_driver ov5647_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov5647_mipi",
++ },
++ .probe = ov5647_probe,
++ .remove = ov5647_remove,
++ .id_table = ov5647_id,
++};
++
++static void ov5647_standby(s32 enable)
++{
++ if (!gpio_is_valid(pwn_gpio))
++ return;
++
++ if (enable) {
++ gpio_set_value(pwn_gpio, !powon_active);
++ if (gpio_is_valid(led_gpio))
++ gpio_set_value(led_gpio, !led_active);
++ }
++ else {
++ gpio_set_value(pwn_gpio, powon_active);
++ if (gpio_is_valid(led_gpio))
++ gpio_set_value(led_gpio, led_active);
++ }
++
++ pr_debug("ov5647_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio);
++ msleep(2);
++}
++
++static void ov5647_reset(void)
++{
++ if (!gpio_is_valid(rst_gpio))
++ return;
++
++ /* camera reset */
++ gpio_set_value(rst_gpio, !rst_active);
++
++ /* camera power dowmn */
++ if (gpio_is_valid(pwn_gpio)) {
++ gpio_set_value(pwn_gpio, !powon_active);
++ msleep(5);
++
++ gpio_set_value(pwn_gpio, powon_active);
++ msleep(5);
++ }
++
++ gpio_set_value(rst_gpio, rst_active);
++ msleep(1);
++
++ gpio_set_value(rst_gpio, !rst_active);
++ msleep(5);
++
++ if (gpio_is_valid(pwn_gpio))
++ gpio_set_value(pwn_gpio, !powon_active);
++}
++
++static int ov5647_power_on(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5647_VOLTAGE_DIGITAL_IO,
++ OV5647_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ pr_err("%s:io set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:io set voltage ok\n", __func__);
++ }
++ } else {
++ pr_err("%s: cannot get io voltage error\n", __func__);
++ io_regulator = NULL;
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5647_VOLTAGE_DIGITAL_CORE,
++ OV5647_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ pr_err("%s:core set voltage error\n", __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:core set voltage ok\n", __func__);
++ }
++ } else {
++ core_regulator = NULL;
++ pr_err("%s: cannot get core voltage error\n", __func__);
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5647_VOLTAGE_ANALOG,
++ OV5647_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ pr_err("%s:analog set voltage error\n",
++ __func__);
++ return ret;
++ } else {
++ dev_dbg(dev,
++ "%s:analog set voltage ok\n", __func__);
++ }
++ } else {
++ analog_regulator = NULL;
++ pr_err("%s: cannot get analog voltage error\n", __func__);
++ }
++
++ return ret;
++}
++
++static s32 ov5647_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5647_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++ pr_debug("reg=%x,val=%x\n", reg, val);
++ return 0;
++}
++
++static s32 ov5647_read_reg(u16 reg, u8 *val)
++{
++ struct sensor_data *sensor = &ov5647_data;
++ struct i2c_client *client = sensor->i2c_client;
++ struct i2c_msg msgs[2];
++ u8 buf[2];
++ int ret;
++
++ buf[0] = reg >> 8;
++ buf[1] = reg & 0xff;
++ msgs[0].addr = client->addr;
++ msgs[0].flags = 0;
++ msgs[0].len = 2;
++ msgs[0].buf = buf;
++
++ msgs[1].addr = client->addr;
++ msgs[1].flags = I2C_M_RD;
++ msgs[1].len = 1;
++ msgs[1].buf = buf;
++
++ ret = i2c_transfer(client->adapter, msgs, 2);
++ if (ret < 0) {
++ pr_err("%s(mipi):reg=%x ret=%d\n", __func__, reg, ret);
++ return ret;
++ }
++ *val = buf[0];
++ pr_debug("%s(mipi):reg=%x,val=%x\n", __func__, reg, buf[0]);
++ return buf[0];
++}
++
++static int prev_sysclk, prev_HTS;
++static int AE_low, AE_high, AE_Target = 44;
++
++void OV5647_stream_on(void)
++{
++ ov5647_write_reg(0x4202, 0x00);
++ ov5647_write_reg(0x300D, 0x00);
++}
++
++void OV5647_stream_off(void)
++{
++ ov5647_write_reg(0x4202, 0x0f);
++ ov5647_write_reg(0x300D, 0x01);
++}
++
++static const int sclk_rdiv_map[] = {1, 2, 4, 8};
++
++int OV5647_get_sysclk(void)
++{
++ /* calculate sysclk */
++ int tmp;
++ unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1;
++ unsigned div, sclk_rdiv, sysclk;
++ u8 temp;
++
++ tmp = ov5647_read_reg(0x3034, &temp);
++ if (tmp < 0)
++ return tmp;
++ tmp &= 0x0f;
++ if (tmp == 8 || tmp == 10)
++ Bit_div2x = tmp / 2;
++
++ tmp = ov5647_read_reg(0x3035, &temp);
++ if (tmp < 0)
++ return tmp;
++ SysDiv = tmp >> 4;
++ if (SysDiv == 0)
++ SysDiv = 16;
++
++ tmp = ov5647_read_reg(0x3036, &temp);
++ if (tmp < 0)
++ return tmp;
++ Multiplier = tmp;
++
++ tmp = ov5647_read_reg(0x3037, &temp);
++ if (tmp < 0)
++ return tmp;
++ PreDiv = tmp & 0x0f;
++ Pll_rdiv = ((tmp >> 4) & 0x01) + 1;
++
++ tmp = ov5647_read_reg(0x3108, &temp);
++ if (tmp < 0)
++ return tmp;
++ sclk_rdiv = sclk_rdiv_map[tmp & 0x03];
++
++ sysclk = ov5647_data.mclk / 10000 * Multiplier;
++ div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv;
++ if (!div) {
++ pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n",
++ __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
++ return -EINVAL;
++ }
++ if (!sysclk) {
++ pr_err("%s:Error 0 clk, ov5647_data.mclk=%d, Multiplier=%d\n",
++ __func__, ov5647_data.mclk, Multiplier);
++ return -EINVAL;
++ }
++ sysclk /= div;
++ pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n",
++ __func__, sysclk, ov5647_data.mclk, Multiplier,
++ PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
++ return sysclk;
++}
++
++void OV5647_set_night_mode(void)
++{
++ /* read HTS from register settings */
++ u8 mode;
++
++ ov5647_read_reg(0x3a00, &mode);
++ mode &= 0xfb;
++ ov5647_write_reg(0x3a00, mode);
++}
++
++int OV5647_get_HTS(void)
++{
++ /* read HTS from register settings */
++ int HTS;
++ u8 temp;
++
++ HTS = ov5647_read_reg(0x380c, &temp);
++ HTS = (HTS<<8) + ov5647_read_reg(0x380d, &temp);
++
++ return HTS;
++}
++
++int OV5647_get_VTS(void)
++{
++ /* read VTS from register settings */
++ int VTS;
++ u8 temp;
++
++ /* total vertical size[15:8] high byte */
++ VTS = ov5647_read_reg(0x380e, &temp);
++
++ VTS = (VTS<<8) + ov5647_read_reg(0x380f, &temp);
++
++ return VTS;
++}
++
++int OV5647_set_VTS(int VTS)
++{
++ /* write VTS to registers */
++ int temp;
++
++ temp = VTS & 0xff;
++ ov5647_write_reg(0x380f, temp);
++
++ temp = VTS>>8;
++ ov5647_write_reg(0x380e, temp);
++
++ return 0;
++}
++
++int OV5647_get_shutter(void)
++{
++ /* read shutter, in number of line period */
++ int shutter;
++ u8 temp;
++
++ shutter = (ov5647_read_reg(0x03500, &temp) & 0x0f);
++ shutter = (shutter<<8) + ov5647_read_reg(0x3501, &temp);
++ shutter = (shutter<<4) + (ov5647_read_reg(0x3502, &temp)>>4);
++
++ return shutter;
++}
++
++int OV5647_set_shutter(int shutter)
++{
++ /* write shutter, in number of line period */
++ int temp;
++
++ shutter = shutter & 0xffff;
++
++ temp = shutter & 0x0f;
++ temp = temp<<4;
++ ov5647_write_reg(0x3502, temp);
++
++ temp = shutter & 0xfff;
++ temp = temp>>4;
++ ov5647_write_reg(0x3501, temp);
++
++ temp = shutter>>12;
++ ov5647_write_reg(0x3500, temp);
++
++ return 0;
++}
++
++int OV5647_get_gain16(void)
++{
++ /* read gain, 16 = 1x */
++ int gain16;
++ u8 temp;
++
++ gain16 = ov5647_read_reg(0x350a, &temp) & 0x03;
++ gain16 = (gain16<<8) + ov5647_read_reg(0x350b, &temp);
++
++ return gain16;
++}
++
++int OV5647_set_gain16(int gain16)
++{
++ /* write gain, 16 = 1x */
++ u8 temp;
++ gain16 = gain16 & 0x3ff;
++
++ temp = gain16 & 0xff;
++ ov5647_write_reg(0x350b, temp);
++
++ temp = gain16>>8;
++ ov5647_write_reg(0x350a, temp);
++
++ return 0;
++}
++
++int OV5647_get_light_freq(void)
++{
++ /* get banding filter value */
++ int temp, temp1, light_freq = 0;
++ u8 tmp;
++
++ temp = ov5647_read_reg(0x3c01, &tmp);
++
++ if (temp & 0x80) {
++ /* manual */
++ temp1 = ov5647_read_reg(0x3c00, &tmp);
++ if (temp1 & 0x04) {
++ /* 50Hz */
++ light_freq = 50;
++ } else {
++ /* 60Hz */
++ light_freq = 60;
++ }
++ } else {
++ /* auto */
++ temp1 = ov5647_read_reg(0x3c0c, &tmp);
++ if (temp1 & 0x01) {
++ /* 50Hz */
++ light_freq = 50;
++ } else {
++ /* 60Hz */
++ light_freq = 60;
++ }
++ }
++ return light_freq;
++}
++
++void OV5647_set_bandingfilter(void)
++{
++ int prev_VTS;
++ int band_step60, max_band60, band_step50, max_band50;
++
++ /* read preview PCLK */
++ prev_sysclk = OV5647_get_sysclk();
++ /* read preview HTS */
++ prev_HTS = OV5647_get_HTS();
++
++ /* read preview VTS */
++ prev_VTS = OV5647_get_VTS();
++
++ /* calculate banding filter */
++ /* 60Hz */
++ band_step60 = prev_sysclk * 100/prev_HTS * 100/120;
++ ov5647_write_reg(0x3a0a, (band_step60 >> 8));
++ ov5647_write_reg(0x3a0b, (band_step60 & 0xff));
++
++ max_band60 = (int)((prev_VTS-4)/band_step60);
++ ov5647_write_reg(0x3a0d, max_band60);
++
++ /* 50Hz */
++ band_step50 = prev_sysclk * 100/prev_HTS;
++ ov5647_write_reg(0x3a08, (band_step50 >> 8));
++ ov5647_write_reg(0x3a09, (band_step50 & 0xff));
++
++ max_band50 = (int)((prev_VTS-4)/band_step50);
++ ov5647_write_reg(0x3a0e, max_band50);
++}
++
++int OV5647_set_AE_target(int target)
++{
++ /* stable in high */
++ int fast_high, fast_low;
++ AE_low = target * 23 / 25; /* 0.92 */
++ AE_high = target * 27 / 25; /* 1.08 */
++
++ fast_high = AE_high<<1;
++ if (fast_high > 255)
++ fast_high = 255;
++
++ fast_low = AE_low >> 1;
++
++ ov5647_write_reg(0x3a0f, AE_high);
++ ov5647_write_reg(0x3a10, AE_low);
++ ov5647_write_reg(0x3a1b, AE_high);
++ ov5647_write_reg(0x3a1e, AE_low);
++ ov5647_write_reg(0x3a11, fast_high);
++ ov5647_write_reg(0x3a1f, fast_low);
++
++ return 0;
++}
++
++void OV5647_turn_on_AE_AG(int enable)
++{
++ u8 ae_ag_ctrl;
++
++ ov5647_read_reg(0x3503, &ae_ag_ctrl);
++ if (enable) {
++ /* turn on auto AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl & ~(0x03);
++ } else {
++ /* turn off AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl | 0x03;
++ }
++ ov5647_write_reg(0x3503, ae_ag_ctrl);
++}
++
++bool ov5647_binning_on(void)
++{
++ u8 temp;
++ ov5647_read_reg(0x3821, &temp);
++ temp &= 0xfe;
++ if (temp)
++ return true;
++ else
++ return false;
++}
++
++static void ov5647_set_virtual_channel(int channel)
++{
++ u8 channel_id;
++
++ ov5647_read_reg(0x4814, &channel_id);
++ channel_id &= ~(3 << 6);
++ ov5647_write_reg(0x4814, channel_id | (channel << 6));
++}
++
++/* download ov5647 settings to sensor through i2c */
++static int ov5647_download_firmware(struct reg_value *pModeSetting, s32 ArySize)
++{
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int i, retval = 0;
++
++ for (i = 0; i < ArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5647_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5647_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++/* sensor changes between scaling and subsampling
++ * go through exposure calcualtion
++ */
++static int ov5647_change_mode_exposure_calc(enum ov5647_frame_rate frame_rate,
++ enum ov5647_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ u8 average;
++ int prev_shutter, prev_gain16;
++ int cap_shutter, cap_gain16;
++ int cap_sysclk, cap_HTS, cap_VTS;
++ int light_freq, cap_bandfilt, cap_maxband;
++ long cap_gain16_shutter;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5647_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5647_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5647_data.pix.width =
++ ov5647_mode_info_data[frame_rate][mode].width;
++ ov5647_data.pix.height =
++ ov5647_mode_info_data[frame_rate][mode].height;
++ ov5647_data_add.map_sizeimage =
++ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2;
++
++ if (ov5647_data.pix.width == 0 || ov5647_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* turn off AE/AG */
++ OV5647_turn_on_AE_AG(0);
++
++ /* read preview shutter */
++ prev_shutter = OV5647_get_shutter();
++ if ((ov5647_binning_on()) && (mode != ov5647_mode_960P_1280_960) &&
++ (mode != ov5647_mode_720P_1280_720) && (mode != ov5647_mode_1080P_1920_1080))
++ prev_shutter *= 2;
++
++ /* read preview gain */
++ prev_gain16 = OV5647_get_gain16();
++
++ /* get average */
++ ov5647_read_reg(0x5693, &average);
++
++ /* turn off night mode for capture */
++ OV5647_set_night_mode();
++
++ /* turn off overlay */
++ /* ov5647_write_reg(0x3022, 0x06);//if no af function, just skip it */
++
++ OV5647_stream_off();
++
++ /* Write capture setting */
++ retval = ov5647_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* read capture VTS */
++ cap_VTS = OV5647_get_VTS();
++ cap_HTS = OV5647_get_HTS();
++ cap_sysclk = OV5647_get_sysclk();
++
++ /* calculate capture banding filter */
++ light_freq = OV5647_get_light_freq();
++ if (light_freq == 60) {
++ /* 60Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120;
++ } else {
++ /* 50Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS;
++ }
++ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt);
++
++ /* calculate capture shutter/gain16 */
++ if (average > AE_low && average < AE_high) {
++ /* in stable range */
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk
++ * prev_HTS/cap_HTS * AE_Target / average;
++ } else {
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk
++ * prev_HTS/cap_HTS;
++ }
++
++ /* gain to shutter */
++ if (cap_gain16_shutter < (cap_bandfilt * 16)) {
++ /* shutter < 1/100 */
++ cap_shutter = cap_gain16_shutter/16;
++ if (cap_shutter < 1)
++ cap_shutter = 1;
++
++ cap_gain16 = cap_gain16_shutter/cap_shutter;
++ if (cap_gain16 < 16)
++ cap_gain16 = 16;
++ } else {
++ if (cap_gain16_shutter >
++ (cap_bandfilt * cap_maxband * 16)) {
++ /* exposure reach max */
++ cap_shutter = cap_bandfilt * cap_maxband;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ } else {
++ /* 1/100 < (cap_shutter = n/100) =< max */
++ cap_shutter =
++ ((int) (cap_gain16_shutter/16 / cap_bandfilt))
++ *cap_bandfilt;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ }
++ }
++
++ /* write capture gain */
++ OV5647_set_gain16(cap_gain16);
++
++ /* write capture shutter */
++ if (cap_shutter > (cap_VTS - 4)) {
++ cap_VTS = cap_shutter + 4;
++ OV5647_set_VTS(cap_VTS);
++ }
++ OV5647_set_shutter(cap_shutter);
++
++ OV5647_stream_on();
++
++err:
++ return retval;
++}
++
++/* if sensor changes inside scaling or subsampling
++ * change mode directly
++ * */
++static int ov5647_change_mode_direct(enum ov5647_frame_rate frame_rate,
++ enum ov5647_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5647_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5647_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5647_data.pix.width =
++ ov5647_mode_info_data[frame_rate][mode].width;
++ ov5647_data.pix.height =
++ ov5647_mode_info_data[frame_rate][mode].height;
++ ov5647_data_add.map_sizeimage =
++ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2;
++
++ if (ov5647_data.pix.width == 0 || ov5647_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* turn off AE/AG */
++ OV5647_turn_on_AE_AG(0);
++
++ OV5647_stream_off();
++
++ /* Write capture setting */
++ retval = ov5647_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ OV5647_stream_on();
++
++ OV5647_turn_on_AE_AG(1);
++
++err:
++ return retval;
++}
++
++static int ov5647_init_mode(enum ov5647_frame_rate frame_rate,
++ enum ov5647_mode mode, enum ov5647_mode orig_mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++ void *mipi_csi2_info;
++ u32 mipi_reg, msec_wait4stable = 0;
++ enum ov5647_downsize_mode dn_mode, orig_dn_mode;
++
++ if ((mode > ov5647_mode_MAX || mode < ov5647_mode_MIN)
++ && (mode != ov5647_mode_INIT)) {
++ pr_err("Wrong ov5647 mode detected!\n");
++ return -1;
++ }
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* initial mipi dphy */
++ if (!mipi_csi2_info) {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -1;
++ }
++
++ ov5647_write_reg(0x4800, 0x25);
++ OV5647_stream_off();
++
++ if (!mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_enable(mipi_csi2_info);
++
++ if (!mipi_csi2_get_status(mipi_csi2_info)) {
++ pr_err("Can not enable mipi csi2 driver!\n");
++ return -1;
++ }
++
++ mipi_csi2_set_lanes(mipi_csi2_info, 2);
++
++ /*Only reset MIPI CSI2 HW at sensor initialize*/
++ if (mode == ov5647_mode_INIT)
++ mipi_csi2_reset(mipi_csi2_info);
++
++ /* reg 0x3034[3:0] == 0x8 is 8bit mode */
++ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_RAW8);
++
++ if (orig_mode != ov5647_mode_INIT) {
++ dn_mode = ov5647_mode_info_data[frame_rate][mode].dn_mode;
++ orig_dn_mode = ov5647_mode_info_data[frame_rate][orig_mode].dn_mode;
++ }
++ else {
++ orig_dn_mode = dn_mode = 0;
++ }
++
++ if (mode == ov5647_mode_INIT) {
++ int index = (int)ov5647_data.streamcap.capturemode;
++
++ pModeSetting = ov5647_mode_info_data[frame_rate][index].init_data_ptr;
++ ArySize = ov5647_mode_info_data[frame_rate][index].init_data_size;
++ retval = ov5647_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++ } else if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) ||
++ (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) {
++ /* change between subsampling and scaling
++ * go through exposure calucation */
++ retval = ov5647_change_mode_exposure_calc(frame_rate, mode);
++ } else {
++ /* change inside subsampling or scaling
++ * download firmware directly */
++ retval = ov5647_change_mode_direct(frame_rate, mode);
++ }
++
++ if (retval < 0)
++ goto err;
++
++ OV5647_set_AE_target(AE_Target);
++ OV5647_get_light_freq();
++ OV5647_set_bandingfilter();
++ ov5647_set_virtual_channel(ov5647_data.virtual_channel);
++
++ /* add delay to wait for sensor stable */
++ if (frame_rate == ov5647_15_fps) {
++ /* dump the first nine frames: 1/15*9 */
++ msec_wait4stable = 600;
++ } else if (frame_rate == ov5647_30_fps) {
++ /* dump the first nine frames: 1/30*9 */
++ msec_wait4stable = 300;
++ }
++ msleep(msec_wait4stable);
++
++ if (mipi_csi2_info) {
++ unsigned int i = 0;
++ u8 resetval;
++
++ /* wait for mipi sensor ready */
++ while (1) {
++ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
++ if (mipi_reg != 0x200)
++ break;
++ if (i++ >= 20) {
++ pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg);
++ return -1;
++ }
++ msleep(10);
++ }
++
++ i = 0;
++ /* wait for mipi stable */
++ while (1) {
++ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
++ if (!mipi_reg)
++ break;
++ if (i++ >= 20) {
++ pr_err("mipi csi2 can not receive data correctly!\n");
++ return -1;
++ }
++ msleep(10);
++ }
++
++ pr_debug("receiving data");
++ mipi_reg = mipi_csi2_get_error2(mipi_csi2_info);
++ pr_debug("mipi_csi2 error2 = 0x%X\n", mipi_reg);
++ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
++ pr_debug("mipi_csi2_dphy_status = 0x%X\n", mipi_reg);
++
++ ov5647_read_reg(0x0100, &resetval);
++ if (!resetval&0x01) {
++ pr_info("DEVICE WAS IN SOFTWARE STANDBY");
++ ov5647_write_reg(0x0100, 0x01);
++ }
++
++ ov5647_write_reg(0x4800, 0x04);
++ msleep(266);
++ OV5647_stream_on();
++ msleep(30);
++ OV5647_turn_on_AE_AG(1);
++ }
++err:
++ return retval;
++}
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -1;
++ }
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = ov5647_data.mclk;
++ pr_debug(" clock_curr=mclk=%d\n", ov5647_data.mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT;
++ p->u.bt656.clock_min = OV5647_XCLK_MIN;
++ p->u.bt656.clock_max = OV5647_XCLK_MAX;
++ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor_data *sensor = s->priv;
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (gpo_regulator)
++ if (regulator_enable(gpo_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5647_standby(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ ov5647_standby(1);
++ }
++
++ sensor->on = on;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor_data *sensor = s->priv;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5647_frame_rate frame_rate;
++ enum ov5647_mode orig_mode;
++ int ret = 0;
++
++ /* Make sure power on */
++ ov5647_standby(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5647_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5647_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ return -EINVAL;
++ }
++
++ orig_mode = sensor->streamcap.capturemode;
++ ret = ov5647_init_mode(frame_rate,
++ (u32)a->parm.capture.capturemode, orig_mode);
++ if (ret < 0)
++ return ret;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode =
++ (u32)a->parm.capture.capturemode;
++
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor_data *sensor = s->priv;
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ f->fmt.pix = sensor->pix;
++ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height);
++ break;
++
++ case V4L2_BUF_TYPE_SENSOR:
++ pr_debug("%s: left=%d, top=%d, %dx%d\n", __func__,
++ sensor->spix.left, sensor->spix.top,
++ sensor->spix.swidth, sensor->spix.sheight);
++ f->fmt.spix = sensor->spix;
++ break;
++
++ case V4L2_BUF_TYPE_PRIVATE:
++ break;
++
++ default:
++ f->fmt.pix = sensor->pix;
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int ret = 0;
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = ov5647_data.brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = ov5647_data.hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = ov5647_data.contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = ov5647_data.saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = ov5647_data.red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = ov5647_data.blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = ov5647_data.ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++
++ pr_debug("In ov5647:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5647_mode_MAX)
++ return -EINVAL;
++
++ fsize->pixel_format = ov5647_data.pix.pixelformat;
++ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++ fsize->discrete.width =
++ max(ov5647_mode_info_data[0][fsize->index].width,
++ ov5647_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5647_mode_info_data[0][fsize->index].height,
++ ov5647_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "ov5647_mipi_camera");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index > ov5647_mode_MAX)
++ return -EINVAL;
++
++ fmt->pixelformat = ov5647_data.pix.pixelformat;
++
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct sensor_data *sensor = s->priv;
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ int ret;
++ enum ov5647_frame_rate frame_rate;
++ void *mipi_csi2_info;
++
++ ov5647_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5647_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5647_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5647_XCLK_MIN);
++ ov5647_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5647_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5647_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* enable mipi csi2 */
++ if (mipi_csi2_info)
++ mipi_csi2_enable(mipi_csi2_info);
++ else {
++ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n",
++ __func__, __FILE__);
++ return -EPERM;
++ }
++
++ ret = ov5647_init_mode(frame_rate, ov5647_mode_INIT, ov5647_mode_INIT);
++
++ return ret;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ void *mipi_csi2_info;
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* disable mipi csi2 */
++ if (mipi_csi2_info)
++ if (mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_disable(mipi_csi2_info);
++
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc ov5647_ioctl_desc[] = {
++ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *) ioctl_dev_init},
++ {vidioc_int_dev_exit_num, ioctl_dev_exit},
++ {vidioc_int_s_power_num, (v4l2_int_ioctl_func *) ioctl_s_power},
++ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *) ioctl_g_ifparm},
++/* {vidioc_int_g_needs_reset_num,
++ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
++/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
++ {vidioc_int_init_num, (v4l2_int_ioctl_func *) ioctl_init},
++ {vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap},
++/* {vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
++ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
++/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_s_fmt_cap}, */
++ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
++ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
++/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */
++ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl},
++ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
++ {vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
++ {vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *) ioctl_g_chip_ident},
++};
++
++static struct v4l2_int_slave ov5647_slave = {
++ .ioctls = ov5647_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(ov5647_ioctl_desc),
++};
++
++static struct v4l2_int_device ov5647_int_device = {
++ .module = THIS_MODULE,
++ .name = "ov5647_mipi",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &ov5647_slave,
++ },
++};
++
++static ssize_t show_reg(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ u8 val;
++ s32 rval = ov5647_read_reg(ov5647_data.last_reg, &val);
++
++ return sprintf(buf, "ov5647[0x%04x]=0x%02x\n",ov5647_data.last_reg, rval);
++}
++static ssize_t set_reg(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int regnum, value;
++ int num_parsed = sscanf(buf, "%04x=%02x", &regnum, &value);
++ if (1 <= num_parsed) {
++ if (0xffff < (unsigned)regnum){
++ pr_err("%s:invalid regnum %x\n", __func__, regnum);
++ return 0;
++ }
++ ov5647_data.last_reg = regnum;
++ }
++ if (2 == num_parsed) {
++ if (0xff < (unsigned)value) {
++ pr_err("%s:invalid value %x\n", __func__, value);
++ return 0;
++ }
++ ov5647_write_reg(ov5647_data.last_reg, value);
++ }
++ return count;
++}
++
++/* XXX: workaround for v4l2 client except for gstreamer-imx */
++static ssize_t show_mode(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "ov5647 mode = 0x%02x\n", (int)ov5647_data.streamcap.capturemode);
++}
++
++static ssize_t set_mode(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ unsigned long mode;
++
++ mode = simple_strtoul(buf, NULL, 10);
++ if ((enum ov5647_mode)mode >= ov5647_mode_MIN &&
++ (enum ov5647_mode)mode <= ov5647_mode_MAX) {
++
++ ov5647_data.streamcap.capturemode = mode;
++ ov5647_data.pix.width =
++ max(ov5647_mode_info_data[0][mode].width,
++ ov5647_mode_info_data[1][mode].width);
++ ov5647_data.pix.height =
++ max(ov5647_mode_info_data[0][mode].height,
++ ov5647_mode_info_data[1][mode].height);
++ ov5647_data_add.map_sizeimage =
++ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2;
++ }
++
++ return count;
++}
++
++static DEVICE_ATTR(ov5647_reg, S_IRUGO|S_IWUGO, show_reg, set_reg);
++static DEVICE_ATTR(ov5647_mode, S_IRUGO|S_IWUGO, show_mode, set_mode);
++
++/*!
++ * ov5647 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5647_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct device *dev = &client->dev;
++ int retval, init, gpio;
++ u8 chip_id_high, chip_id_low;
++ struct sensor_data *sensor = &ov5647_data;
++ enum of_gpio_flags flags;
++ bool extbuf;
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio_flags(dev->of_node, "pwn-gpios", 0, &flags);
++ if (gpio_is_valid(pwn_gpio)) {
++ /* powon_active - camera power on */
++ /* !powon_active - camera power down */
++ powon_active = !(flags & OF_GPIO_ACTIVE_LOW);
++ init = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++
++ retval = devm_gpio_request_one(dev, pwn_gpio, init, "ov5647_mipi_pwdn");
++ if (retval < 0) {
++ dev_warn(dev, "request of pwn_gpio failed");
++ pwn_gpio = -EINVAL;
++ }
++ }
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio_flags(dev->of_node, "rst-gpios", 0, &flags);
++ if (gpio_is_valid(rst_gpio)) {
++ /* rst_active - camera reset */
++ /* !rst_active - clear camera reset */
++ rst_active = !(flags & OF_GPIO_ACTIVE_LOW);
++ init = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++
++ retval = devm_gpio_request_one(dev, rst_gpio, init, "ov5647_mipi_reset");
++ if (retval < 0) {
++ dev_warn(dev, "request of ov5647_mipi_reset failed");
++ rst_gpio = -EINVAL;
++ }
++ }
++
++ /* request LED(for sanity) pin */
++ gpio = of_get_named_gpio_flags(dev->of_node, "led-gpios", 0, &flags);
++ if (gpio_is_valid(gpio)) {
++ /* led_active - LED turn on */
++ /* !led_active - LED trun off */
++ led_active = !(flags & OF_GPIO_ACTIVE_LOW);
++ init = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++
++ retval = devm_gpio_request_one(dev, gpio, init, "ov5647_mipi_led");
++ if (retval < 0) {
++ dev_warn(dev, "request of led_gpio failed");
++ gpio = -EINVAL;
++ }
++ }
++
++ /* allocate extended video frame buffer */
++ extbuf = of_find_property(dev->of_node, "extended-buffer", NULL);
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5647_data, 0, sizeof(ov5647_data));
++ memset(&ov5647_data_add, 0, sizeof(ov5647_data_add));
++
++ sensor->mipi_camera = 1;
++ ov5647_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5647_data.sensor_clk)) {
++ /* assuming clock enabled by default */
++ ov5647_data.sensor_clk = NULL;
++ dev_err(dev, "clock-frequency missing or invalid\n");
++ return PTR_ERR(ov5647_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ &(ov5647_data.mclk));
++ if (retval) {
++ dev_err(dev, "mclk missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5647_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "ipu_id",
++ &sensor->ipu_id);
++ if (retval) {
++ dev_err(dev, "ipu_id missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5647_data.csi));
++ if (retval) {
++ dev_err(dev, "csi id missing or invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5647_data.sensor_clk);
++
++ ov5647_data.io_init = ov5647_reset;
++ ov5647_data.i2c_client = client;
++ /* real OV5647 pixelformat is V4L2_PIX_FMT_SBGGR10. */
++ /* i.MX6 CSI CPD convert 10 bits color data to 8 bits. */
++ /* (see drivers/mxc/ipu3/ipu_capture.c - _ipu_csi_init) */
++ ov5647_data.pix.pixelformat = V4L2_PIX_FMT_SBGGR8;
++ ov5647_data.pix.width = 1024;
++ ov5647_data.pix.height = 768;
++ ov5647_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5647_data.streamcap.capturemode = ov5647_mode_XGA_1024_768;
++ ov5647_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5647_data.streamcap.timeperframe.numerator = 1;
++
++ /* lager memory allocate for Vivante direct texture mapping API */
++ /* (VIDIOC_REQBUFS ioctl) */
++ ov5647_data_add.map_sizeimage =
++ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2; /* I420 */
++
++ if (extbuf) {
++ ov5647_data.adata = &ov5647_data_add;
++ }
++
++ ov5647_power_on(dev);
++
++ ov5647_reset();
++
++ ov5647_standby(0);
++
++ retval = ov5647_read_reg(OV5647_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ pr_warning("camera ov5647_mipi is not found\n");
++ clk_disable_unprepare(ov5647_data.sensor_clk);
++ return -ENODEV;
++ }
++ retval = ov5647_read_reg(OV5647_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x47) {
++ pr_warning("camera ov5647_mipi is not found\n");
++ clk_disable_unprepare(ov5647_data.sensor_clk);
++ return -ENODEV;
++ }
++
++ sensor->virtual_channel = sensor->csi | (sensor->ipu_id << 1);
++ ov5647_standby(1);
++
++ led_gpio = gpio;
++ ov5647_int_device.priv = &ov5647_data;
++ retval = v4l2_int_device_register(&ov5647_int_device);
++
++// clk_disable_unprepare(ov5647_data.sensor_clk);
++
++ if (device_create_file(dev, &dev_attr_ov5647_reg))
++ dev_err(dev, "%s: error creating ov5647_reg entry\n", __func__);
++ if (device_create_file(dev, &dev_attr_ov5647_mode))
++ dev_err(dev, "%s: error creating ov5647_mode entry\n", __func__);
++
++ pr_info("camera ov5647_mipi is found\n");
++ return retval;
++}
++
++/*!
++ * ov5647 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5647_remove(struct i2c_client *client)
++{
++ v4l2_int_device_unregister(&ov5647_int_device);
++
++ if (gpo_regulator)
++ regulator_disable(gpo_regulator);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++/*!
++ * ov5647 init function
++ * Called by insmod ov5647_camera.ko.
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int ov5647_init(void)
++{
++ u8 err;
++
++ err = i2c_add_driver(&ov5647_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * OV5647 cleanup function
++ * Called on rmmod ov5647_camera.ko
++ *
++ * @return Error code indicating success or failure
++ */
++static void __exit ov5647_clean(void)
++{
++ i2c_del_driver(&ov5647_i2c_driver);
++}
++
++module_init(ov5647_init);
++module_exit(ov5647_clean);
++
++MODULE_AUTHOR("Viion Systems Inc.");
++MODULE_DESCRIPTION("OV5647 MIPI Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/tc358743_h2c.c linux-3.14.72/drivers/media/platform/mxc/capture/tc358743_h2c.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/tc358743_h2c.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/tc358743_h2c.c 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,3674 @@
++/*
++ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2014 Boundary Devices
++ */
++
++/*
++ * Modifyed by: Edison Fernández <edison.fernandez@ridgerun.com>
++ * Added support to use it with Nitrogen6x
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/ctype.h>
++#include <linux/types.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/clk.h>
++#include <linux/i2c.h>
++#include <linux/of_gpio.h>
++#include <linux/regulator/consumer.h>
++#include <linux/fsl_devices.h>
++#include <linux/mutex.h>
++#include <linux/mipi_csi2.h>
++#include <media/v4l2-chip-ident.h>
++#include "v4l2-int-device.h"
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/jack.h>
++#include <sound/soc-dapm.h>
++#include <asm/mach-types.h>
++//#include <mach/audmux.h>
++#include <linux/slab.h>
++#include "mxc_v4l2_capture.h"
++
++#define CODEC_CLOCK 16500000
++/* SSI clock sources */
++#define IMX_SSP_SYS_CLK 0
++
++#define MIN_FPS 30
++#define MAX_FPS 60
++#define DEFAULT_FPS 60
++
++#define TC358743_XCLK_MIN 27000000
++#define TC358743_XCLK_MAX 42000000
++
++#define TC358743_CHIP_ID_HIGH_BYTE 0x0
++#define TC358743_CHIP_ID_LOW_BYTE 0x0
++#define TC3587430_HDMI_DETECT 0x0f //0x10
++
++#define TC_VOLTAGE_DIGITAL_IO 1800000
++#define TC_VOLTAGE_DIGITAL_CORE 1500000
++#define TC_VOLTAGE_DIGITAL_GPO 1500000
++#define TC_VOLTAGE_ANALOG 2800000
++
++#define MAX_COLORBAR tc358743_mode_INIT6
++#define IS_COLORBAR(a) (a <= MAX_COLORBAR)
++
++enum tc358743_mode {
++ tc358743_mode_INIT,
++ tc358743_mode_INIT1,
++ tc358743_mode_INIT2,
++ tc358743_mode_INIT3,
++ tc358743_mode_INIT4,
++ tc358743_mode_INIT5,
++ tc358743_mode_INIT6,
++ tc358743_mode_480P_720_480,
++ tc358743_mode_720P_60_1280_720,
++ tc358743_mode_480P_640_480,
++ tc358743_mode_1080P_1920_1080,
++ tc358743_mode_720P_1280_720,
++ tc358743_mode_1024x768,
++ tc358743_mode_MAX,
++};
++
++enum tc358743_frame_rate {
++ tc358743_60_fps,
++ tc358743_30_fps,
++ tc358743_max_fps
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u32 u32Val;
++ u32 u32Mask;
++ u8 u8Length;
++ u32 u32Delay_ms;
++};
++
++struct tc358743_mode_info {
++ const char *name;
++ enum tc358743_mode mode;
++ u32 width;
++ u32 height;
++ u32 vformat;
++ u32 fps;
++ u32 lanes;
++ u32 freq;
++ const struct reg_value *init_data_ptr;
++ u32 init_data_size;
++ __u32 flags;
++};
++
++/*!
++ * Maintains the information on the current state of the sensor.
++ */
++struct tc_data {
++ struct sensor_data sensor;
++ struct delayed_work det_work;
++ struct mutex access_lock;
++ int det_work_enable;
++ int det_work_timeout;
++ int det_changed;
++#define REGULATOR_IO 0
++#define REGULATOR_CORE 1
++#define REGULATOR_GPO 2
++#define REGULATOR_ANALOG 3
++#define REGULATOR_CNT 4
++ struct regulator *regulator[REGULATOR_CNT];
++#ifdef CONFIG_TC358743_AUDIO
++ struct platform_device *snd_device;
++#endif
++ u32 lock;
++ u32 bounce;
++ enum tc358743_mode mode;
++ u32 fps;
++ u32 audio;
++ int pwn_gpio;
++ int rst_gpio;
++ u16 hpd_active;
++ int edid_initialized;
++};
++
++static struct tc_data *g_td;
++
++
++#define DET_WORK_TIMEOUT_DEFAULT 100
++#define DET_WORK_TIMEOUT_DEFERRED 2000
++#define MAX_BOUNCE 5
++
++static void tc_standby(struct tc_data *td, s32 standby)
++{
++ if (gpio_is_valid(td->pwn_gpio))
++ gpio_set_value(td->pwn_gpio, standby ? 1 : 0);
++ pr_debug("tc_standby: powerdown=%x, power_gp=0x%x\n", standby, td->pwn_gpio);
++ msleep(2);
++}
++
++static void tc_reset(struct tc_data *td)
++{
++ /* camera reset */
++ gpio_set_value(td->rst_gpio, 1);
++
++ /* camera power dowmn */
++ if (gpio_is_valid(td->pwn_gpio)) {
++ gpio_set_value(td->pwn_gpio, 1);
++ msleep(5);
++
++ gpio_set_value(td->pwn_gpio, 0);
++ }
++ msleep(5);
++
++ gpio_set_value(td->rst_gpio, 0);
++ msleep(1);
++
++ gpio_set_value(td->rst_gpio, 1);
++ msleep(20);
++
++ if (gpio_is_valid(td->pwn_gpio))
++ gpio_set_value(td->pwn_gpio, 1);
++}
++
++static void tc_io_init(void)
++{
++ return tc_reset(g_td);
++}
++
++const char * const sregulator[REGULATOR_CNT] = {
++ [REGULATOR_IO] = "DOVDD",
++ [REGULATOR_CORE] = "DVDD",
++ [REGULATOR_GPO] = "DGPO",
++ [REGULATOR_ANALOG] = "AVDD",
++};
++
++static const int voltages[REGULATOR_CNT] = {
++ [REGULATOR_IO] = TC_VOLTAGE_DIGITAL_IO,
++ [REGULATOR_CORE] = TC_VOLTAGE_DIGITAL_CORE,
++ [REGULATOR_GPO] = TC_VOLTAGE_DIGITAL_GPO,
++ [REGULATOR_ANALOG] = TC_VOLTAGE_ANALOG,
++};
++
++static int tc_regulator_init(struct tc_data *td, struct device *dev)
++{
++ int i;
++ int ret = 0;
++
++ for (i = 0; i < REGULATOR_CNT; i++) {
++ td->regulator[i] = devm_regulator_get(dev, sregulator[i]);
++ if (!IS_ERR(td->regulator[i])) {
++ regulator_set_voltage(td->regulator[i],
++ voltages[i], voltages[i]);
++ } else {
++ pr_err("%s:%s devm_regulator_get failed\n", __func__, sregulator[i]);
++ td->regulator[i] = NULL;
++ }
++ }
++ return ret;
++}
++
++static void det_work_enable(struct tc_data *td, int enable)
++{
++ td->det_work_enable = enable;
++ td->det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
++ if (enable)
++ schedule_delayed_work(&td->det_work, msecs_to_jiffies(10));
++ pr_debug("%s: %d %d\n", __func__, td->det_work_enable, td->det_work_timeout);
++}
++
++static const u8 cHDMIEDID[256] = {
++ /* FIXME! This is the edid that my ASUS HDMI monitor returns */
++ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, //0 - header[8] - fixed pattern
++ 0x04, 0x69, //8 - manufacturer_name[2]
++ 0xf3, 0x24, //10 - product_code[2]
++ 0xd6, 0x12, 0x00, 0x00, //12 - serial_number[4]
++ 0x16, //16 - week
++ 0x16, //17 - year 22+1990=2012
++ 0x01, //18 - version
++ 0x03, //19 - revision
++ 0x80, //20 - video_input_definition(digital input)
++ 0x34, //21 - max_size_horizontal 52cm
++ 0x1d, //22 - max_size_vertical 29cm
++ 0x78, //23 - gamma
++ 0x3a, //24 - feature_support (RGB 4:4:4 + YCrCb 4:4:4 + YCrCb 4:2:2)
++ 0xc7, 0x20, 0xa4, 0x55, 0x49, 0x99, 0x27, 0x13, 0x50, 0x54, //25 - color_characteristics[10]
++ 0xbf, 0xef, 0x00, //35 - established_timings[3]
++ 0x71, 0x4f, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00, 0xd1, 0xc0, 0x01, 0x01, 0x01, 0x01, //38 - standard_timings[8]
++/* 1080P */
++ 0x02, 0x3a, //54(0) - descriptor[0], 0x3a02 = 148.50 MHz
++ 0x80, //56(2) h - active 0x780 (1920)
++ 0x18, //57(3) h - blank 0x118 (280)
++ 0x71, //58(4)
++ 0x38, //59(5) v - active 0x438 (1080)
++ 0x2d, //60(6) v - blank 0x02d(45)
++ 0x40, //61(7)
++ 0x58, //62(8) - h sync offset(0x58)
++ 0x2c, //63(9) - h sync width(0x2c)
++ 0x45, //64(10) - v sync offset(0x4), v sync width(0x5)
++ 0x00, //65(11)
++ 0x09, //66(12) - h display size (0x209) 521 mm
++ 0x25, //67(13) - v display size (0x125) 293 mm
++ 0x21, //68(14)
++ 0x00, //69(15) - h border pixels
++ 0x00, //70(16) - v border pixels
++ 0x1e, //71(17) - no stereo, digital separate, hsync+, vsync+
++ 0x00, 0x00, 0x00, 0xff, 0x00, //72 - descriptor[1]
++ 0x43, 0x36, 0x4c, 0x4d, 0x54, 0x46, 0x30, 0x30, 0x34, 0x38, 0x32, 0x32, 0x0a, //"C6LMTF004822\n"
++ 0x00, 0x00, 0x00, 0xfd, 0x00, //90 - descriptor[2]
++ 0x37, 0x4b, 0x1e, 0x55, 0x10, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
++ 0x00, 0x00, 0x00, 0xfc, 0x00, //108 - descriptor[3]
++ 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x48, 0x32, 0x34, 0x32, 0x48, 0x0a, 0x20, //"ASUS VH242H\n "
++ 0x01, //126 - extension_flag
++ 0x68, //127 - checksum
++
++ 0x02, //0 - cea-861 extension
++ 0x03, //1 - rev 3
++ 0x22, //2 - detailed timings at offset 34
++ 0x71, //3 - # of detailed timing descriptor
++ 0x4f, 0x01, 0x02, 0x03, 0x11, 0x12, //4
++ 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f, //10
++ 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, //16
++ 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, //22
++ 0x65, 0x03, 0x0c, 0x00, 0x10, 0x00, //28
++/* 720x480@59.94 27000000/858/525 = 59.94 Hz */
++ 0x8c, 0x0a, //34 - descriptor[0] - 0x0a8c - 27 Mhz
++ 0xd0, //h - active 0x2d0 (720)
++ 0x8a, //h - blank 0x8a(138)
++ 0x20,
++ 0xe0, //v - active 0x1e0 (480)
++ 0x2d, //v - blank 0x2d (45)
++ 0x10,
++ 0x10, 0x3e, 0x96, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18,
++/* 1280x720@60 74250000/1650/750 = 60 Hz*/
++ 0x01, 0x1d, //52 - 0x1d01 74.25MHz
++ 0x00, //h - active (0x500)1280
++ 0x72, //h - blank (0x172)370
++ 0x51,
++ 0xd0, //v active 0x2d0(720)
++ 0x1e, //v blank 0x1e(30)
++ 0x20,
++ 0x6e, 0x28, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e,
++/* 1280x720@50 74250000/1980/750 = 50 Hz */
++ 0x01, 0x1d, //70 - 0x1d01 74.25MHz
++ 0x00, //h - active (0x500)1280
++ 0xbc, //h - blank (0x2bc)700
++ 0x52,
++ 0xd0, //v active 0x2d0 (720)
++ 0x1e, //v blank 0x1e(30)
++ 0x20,
++ 0xb8, 0x28, 0x55, 0x40, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e,
++/* 720x576@50 27000000/864/625 = 50 Hz */
++ 0x8c, 0x0a, //88 0x0a8c - 27 Mhz
++ 0xd0, //h - active 0x2d0(720)
++ 0x90, //h - blank 0x90(144)
++ 0x20,
++ 0x40, //v active 0x240(576)
++ 0x31, //v blanking 0x31(49)
++ 0x20,
++ 0x0c, 0x40, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18,
++/* done */
++ 0x00, 0x00, 0x00, 0x00, 0x00, //106
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, //124
++ 0x00, //126 - extension_flag
++ 0x73, //127 - checksum
++};
++
++static const struct reg_value tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz[] = {
++ {0x0006, 0x00000040, 0x00000000, 2, 0},
++ {0x0014, 0x00000000, 0x00000000, 2, 0},
++ {0x0016, 0x000005ff, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x0000402d, 0x00000000, 2, 0},
++ {0x0022, 0x00000213, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00000e00, 0x00000000, 4, 0},
++ {0x0214, 0x00000001, 0x00000000, 4, 0},
++ {0x0218, 0x00000801, 0x00000000, 4, 0},
++ {0x021c, 0x00000001, 0x00000000, 4, 0},
++ {0x0220, 0x00000001, 0x00000000, 4, 0},
++ {0x0224, 0x00004800, 0x00000000, 4, 0},
++ {0x0228, 0x00000005, 0x00000000, 4, 0},
++ {0x022c, 0x00000000, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa300be82, 0x00000000, 4, 0},
++// HDMI Interrupt Mask
++ {0x8502, 0x00000001, 0x00000000, 1, 0},
++ {0x8512, 0x000000fe, 0x00000000, 1, 0},
++ {0x8514, 0x00000000, 0x00000000, 1, 0},
++ {0x8515, 0x00000000, 0x00000000, 1, 0},
++ {0x8516, 0x00000000, 0x00000000, 1, 0},
++// HDMI Audio
++ {0x8531, 0x00000001, 0x00000000, 1, 0},
++ {0x8630, 0x000000b0, 0x00000000, 1, 0},
++ {0x8631, 0x0000001e, 0x00000000, 1, 0},
++ {0x8632, 0x00000004, 0x00000000, 1, 0},
++ {0x8670, 0x00000001, 0x00000000, 1, 0},
++// HDMI PHY
++ {0x8532, 0x00000080, 0x00000000, 1, 0},
++ {0x8536, 0x00000040, 0x00000000, 1, 0},
++ {0x853f, 0x0000000a, 0x00000000, 1, 0},
++// HDMI System
++ {0x8545, 0x00000031, 0x00000000, 1, 0},
++ {0x8546, 0x0000002d, 0x00000000, 1, 0},
++// HDCP Setting
++ {0x85d1, 0x00000001, 0x00000000, 1, 0},
++ {0x8560, 0x00000024, 0x00000000, 1, 0},
++ {0x8563, 0x00000011, 0x00000000, 1, 0},
++ {0x8564, 0x0000000f, 0x00000000, 1, 0},
++// Video settings
++ {0x8573, 0x00000081, 0x00000000, 1, 0},
++ {0x8571, 0x00000002, 0x00000000, 1, 0},
++// HDMI Audio In Setting
++ {0x8600, 0x00000000, 0x00000000, 1, 0},
++ {0x8602, 0x000000f3, 0x00000000, 1, 0},
++ {0x8603, 0x00000002, 0x00000000, 1, 0},
++ {0x8604, 0x0000000c, 0x00000000, 1, 0},
++ {0x8606, 0x00000005, 0x00000000, 1, 0},
++ {0x8607, 0x00000000, 0x00000000, 1, 0},
++ {0x8620, 0x00000022, 0x00000000, 1, 0},
++ {0x8640, 0x00000001, 0x00000000, 1, 0},
++ {0x8641, 0x00000065, 0x00000000, 1, 0},
++ {0x8642, 0x00000007, 0x00000000, 1, 0},
++// {0x8651, 0x00000003, 0x00000000, 1, 0}, // Inverted LRCK polarity - (Sony) format
++ {0x8652, 0x00000002, 0x00000000, 1, 0}, // Left-justified I2S (Phillips) format
++// {0x8652, 0x00000000, 0x00000000, 1, 0}, // Right-justified (Sony) format
++ {0x8665, 0x00000010, 0x00000000, 1, 0},
++// InfoFrame Extraction
++ {0x8709, 0x000000ff, 0x00000000, 1, 0},
++ {0x870b, 0x0000002c, 0x00000000, 1, 0},
++ {0x870c, 0x00000053, 0x00000000, 1, 0},
++ {0x870d, 0x00000001, 0x00000000, 1, 0},
++ {0x870e, 0x00000030, 0x00000000, 1, 0},
++ {0x9007, 0x00000010, 0x00000000, 1, 0},
++ {0x854a, 0x00000001, 0x00000000, 1, 0},
++// Output Control
++ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
++ };
++
++static const struct reg_value tc358743_setting_YUV422_4lane_1024x768_60fps_125MHz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0014, 0x0000ffff, 0x00000000, 2, 0},
++ {0x0016, 0x000005ff, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x0000405c, 0x00000000, 2, 0}, /* Input divide 5(4+1), Feedback divide 92(0x5c+1)*/
++ {0x0022, 0x00000613, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00000d00, 0x00000000, 4, 0},
++ {0x0214, 0x00000001, 0x00000000, 4, 0},
++ {0x0218, 0x00000701, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000001, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000005, 0x00000000, 4, 0},
++ {0x022c, 0x00000000, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0},
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa300be86, 0x00000000, 4, 0},
++// HDMI Interrupt Mask
++ {0x8502, 0x00000001, 0x00000000, 1, 0},
++ {0x8512, 0x000000fe, 0x00000000, 1, 0},
++ {0x8514, 0x00000000, 0x00000000, 1, 0},
++ {0x8515, 0x00000000, 0x00000000, 1, 0},
++ {0x8516, 0x00000000, 0x00000000, 1, 0},
++// HDMI Audio
++ {0x8531, 0x00000001, 0x00000000, 1, 0},
++ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
++ {0x8670, 0x00000001, 0x00000000, 1, 0},
++// HDMI PHY
++ {0x8532, 0x00000080, 0x00000000, 1, 0},
++ {0x8536, 0x00000040, 0x00000000, 1, 0},
++ {0x853f, 0x0000000a, 0x00000000, 1, 0},
++// HDMI System
++ {0x8545, 0x00000031, 0x00000000, 1, 0},
++ {0x8546, 0x0000002d, 0x00000000, 1, 0},
++// HDCP Setting
++ {0x85d1, 0x00000001, 0x00000000, 1, 0},
++ {0x8560, 0x00000024, 0x00000000, 1, 0},
++ {0x8563, 0x00000011, 0x00000000, 1, 0},
++ {0x8564, 0x0000000f, 0x00000000, 1, 0},
++// RGB --> YUV Conversion
++// {0x8574, 0x00000000, 0x00000000, 1, 0},
++ {0x8573, 0x00000081, 0x00000000, 1, 0},
++ {0x8571, 0x00000002, 0x00000000, 1, 0},
++// HDMI Audio In Setting
++ {0x8600, 0x00000000, 0x00000000, 1, 0},
++ {0x8602, 0x000000f3, 0x00000000, 1, 0},
++ {0x8603, 0x00000002, 0x00000000, 1, 0},
++ {0x8604, 0x0000000c, 0x00000000, 1, 0},
++ {0x8606, 0x00000005, 0x00000000, 1, 0},
++ {0x8607, 0x00000000, 0x00000000, 1, 0},
++ {0x8620, 0x00000022, 0x00000000, 1, 0},
++ {0x8640, 0x00000001, 0x00000000, 1, 0},
++ {0x8641, 0x00000065, 0x00000000, 1, 0},
++ {0x8642, 0x00000007, 0x00000000, 1, 0},
++ {0x8652, 0x00000002, 0x00000000, 1, 0},
++ {0x8665, 0x00000010, 0x00000000, 1, 0},
++// InfoFrame Extraction
++ {0x8709, 0x000000ff, 0x00000000, 1, 0},
++ {0x870b, 0x0000002c, 0x00000000, 1, 0},
++ {0x870c, 0x00000053, 0x00000000, 1, 0},
++ {0x870d, 0x00000001, 0x00000000, 1, 0},
++ {0x870e, 0x00000030, 0x00000000, 1, 0},
++ {0x9007, 0x00000010, 0x00000000, 1, 0},
++ {0x854a, 0x00000001, 0x00000000, 1, 0},
++// Output Control
++ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
++
++};
++
++static const struct reg_value tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0014, 0x0000ffff, 0x00000000, 2, 0},
++ {0x0016, 0x000005ff, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x00004062, 0x00000000, 2, 0},
++ {0x0022, 0x00000613, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00000d00, 0x00000000, 4, 0},
++ {0x0214, 0x00000001, 0x00000000, 4, 0},
++ {0x0218, 0x00000701, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000001, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000005, 0x00000000, 4, 0},
++ {0x022c, 0x00000000, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0},
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa300be86, 0x00000000, 4, 0},
++// HDMI Interrupt Mask
++ {0x8502, 0x00000001, 0x00000000, 1, 0},
++ {0x8512, 0x000000fe, 0x00000000, 1, 0},
++ {0x8514, 0x00000000, 0x00000000, 1, 0},
++ {0x8515, 0x00000000, 0x00000000, 1, 0},
++ {0x8516, 0x00000000, 0x00000000, 1, 0},
++// HDMI Audio
++ {0x8531, 0x00000001, 0x00000000, 1, 0},
++ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
++ {0x8670, 0x00000001, 0x00000000, 1, 0},
++// HDMI PHY
++ {0x8532, 0x00000080, 0x00000000, 1, 0},
++ {0x8536, 0x00000040, 0x00000000, 1, 0},
++ {0x853f, 0x0000000a, 0x00000000, 1, 0},
++// HDMI System
++ {0x8545, 0x00000031, 0x00000000, 1, 0},
++ {0x8546, 0x0000002d, 0x00000000, 1, 0},
++// HDCP Setting
++ {0x85d1, 0x00000001, 0x00000000, 1, 0},
++ {0x8560, 0x00000024, 0x00000000, 1, 0},
++ {0x8563, 0x00000011, 0x00000000, 1, 0},
++ {0x8564, 0x0000000f, 0x00000000, 1, 0},
++// RGB --> YUV Conversion
++// {0x8574, 0x00000000, 0x00000000, 1, 0},
++ {0x8573, 0x00000081, 0x00000000, 1, 0},
++ {0x8571, 0x00000002, 0x00000000, 1, 0},
++// HDMI Audio In Setting
++ {0x8600, 0x00000000, 0x00000000, 1, 0},
++ {0x8602, 0x000000f3, 0x00000000, 1, 0},
++ {0x8603, 0x00000002, 0x00000000, 1, 0},
++ {0x8604, 0x0000000c, 0x00000000, 1, 0},
++ {0x8606, 0x00000005, 0x00000000, 1, 0},
++ {0x8607, 0x00000000, 0x00000000, 1, 0},
++ {0x8620, 0x00000022, 0x00000000, 1, 0},
++ {0x8640, 0x00000001, 0x00000000, 1, 0},
++ {0x8641, 0x00000065, 0x00000000, 1, 0},
++ {0x8642, 0x00000007, 0x00000000, 1, 0},
++ {0x8652, 0x00000002, 0x00000000, 1, 0},
++ {0x8665, 0x00000010, 0x00000000, 1, 0},
++// InfoFrame Extraction
++ {0x8709, 0x000000ff, 0x00000000, 1, 0},
++ {0x870b, 0x0000002c, 0x00000000, 1, 0},
++ {0x870c, 0x00000053, 0x00000000, 1, 0},
++ {0x870d, 0x00000001, 0x00000000, 1, 0},
++ {0x870e, 0x00000030, 0x00000000, 1, 0},
++ {0x9007, 0x00000010, 0x00000000, 1, 0},
++ {0x854a, 0x00000001, 0x00000000, 1, 0},
++// Output Control
++ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
++};
++
++static const struct reg_value tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0010, 0x0000001e, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x0000405c, 0x00000000, 2, 0},
++ {0x0022, 0x00000613, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00000e00, 0x00000000, 4, 0},
++ {0x0214, 0x00000001, 0x00000000, 4, 0},
++ {0x0218, 0x00000801, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000001, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000006, 0x00000000, 4, 0},
++ {0x022c, 0x00000000, 0x00000000, 4, 0},
++ {0x0234, 0x00000007, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa30080a2, 0x00000000, 4, 0},
++// 1280x720 colorbar
++ {0x000a, 0x00000a00, 0x00000000, 2, 0},
++ {0x7080, 0x00000082, 0x00000000, 2, 0},
++// 128 pixel black - repeat 128 times
++ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
++// 128 pixel blue - repeat 64 times
++ {0x7000, 0x000000ff, 0x00000000, 2, 0},
++ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel red - repeat 64 times
++ {0x7000, 0x00000000, 0x00000000, 2, 0},
++ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel pink - repeat 64 times
++ {0x7000, 0x00007fff, 0x00000000, 2, 0},
++ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel green - repeat 64 times
++ {0x7000, 0x00007f00, 0x00000000, 2, 0},
++ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel light blue - repeat 64 times
++ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
++ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel yellow - repeat 64 times
++ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
++ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel white - repeat 64 times
++ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
++ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
++// 720 lines
++ {0x7090, 0x000002cf, 0x00000000, 2, 0},
++ {0x7092, 0x00000580, 0x00000000, 2, 0},
++ {0x7094, 0x00000010, 0x00000000, 2, 0},
++ {0x7080, 0x00000083, 0x00000000, 2, 0},
++};
++
++static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0010, 0x0000001e, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x0000405c, 0x00000000, 2, 0},
++ {0x0022, 0x00000613, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00000e00, 0x00000000, 4, 0},
++ {0x0214, 0x00000001, 0x00000000, 4, 0},
++ {0x0218, 0x00000801, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000001, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000006, 0x00000000, 4, 0},
++ {0x022c, 0x00000000, 0x00000000, 4, 0},
++ {0x0234, 0x0000001F, 0x00000000, 4, 0}, //{0x0234, 0x00000007, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, //{0x0500, 0xa30080a2, 0x00000000, 4, 0},
++// 1280x720 colorbar
++ {0x000a, 0x00000a00, 0x00000000, 2, 0},
++ {0x7080, 0x00000082, 0x00000000, 2, 0},
++// 128 pixel black - repeat 128 times
++ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
++// 128 pixel blue - repeat 64 times
++ {0x7000, 0x000000ff, 0x00000000, 2, 0},
++ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel red - repeat 64 times
++ {0x7000, 0x00000000, 0x00000000, 2, 0},
++ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel pink - repeat 64 times
++ {0x7000, 0x00007fff, 0x00000000, 2, 0},
++ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel green - repeat 64 times
++ {0x7000, 0x00007f00, 0x00000000, 2, 0},
++ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel light blue - repeat 64 times
++ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
++ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel yellow - repeat 64 times
++ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
++ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel white - repeat 64 times
++ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
++ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
++// 720 lines
++ {0x7090, 0x000002cf, 0x00000000, 2, 0},
++ {0x7092, 0x00000300, 0x00000000, 2, 0}, //{0x7092, 0x00000580, 0x00000000, 2, 0},
++ {0x7094, 0x00000010, 0x00000000, 2, 0},
++ {0x7080, 0x00000083, 0x00000000, 2, 0},
++};
++
++
++static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0010, 0x0000001e, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x00004050, 0x00000000, 2, 0},
++ {0x0022, 0x00000213, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00001800, 0x00000000, 4, 0},
++ {0x0214, 0x00000002, 0x00000000, 4, 0},
++ {0x0218, 0x00001102, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000003, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000007, 0x00000000, 4, 0},
++ {0x022c, 0x00000001, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
++// 1280x720 colorbar
++ {0x000a, 0x00000800, 0x00000000, 2, 0},
++ {0x7080, 0x00000082, 0x00000000, 2, 0},
++// 128 pixel black - repeat 128 times
++ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
++// 128 pixel blue - repeat 64 times
++ {0x7000, 0x000000ff, 0x00000000, 2, 0},
++ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel red - repeat 64 times
++ {0x7000, 0x00000000, 0x00000000, 2, 0},
++ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel pink - repeat 64 times
++ {0x7000, 0x00007fff, 0x00000000, 2, 0},
++ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel green - repeat 64 times
++ {0x7000, 0x00007f00, 0x00000000, 2, 0},
++ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel light blue - repeat 64 times
++ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
++ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel yellow - repeat 64 times
++ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
++ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel white - repeat 64 times
++ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
++ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
++// 720 lines
++ {0x0020, 0x0000406f, 0x00000000, 2, 100},
++ {0x7090, 0x000002cf, 0x00000000, 2, 0},
++ {0x7092, 0x00000540, 0x00000000, 2, 0},
++ {0x7094, 0x00000010, 0x00000000, 2, 0},
++ {0x7080, 0x00000083, 0x00000000, 2, 0},
++};
++
++static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0010, 0x0000001e, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x000080c7, 0x00000000, 2, 0},
++ {0x0022, 0x00000213, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00001e00, 0x00000000, 4, 0},
++ {0x0214, 0x00000003, 0x00000000, 4, 0},
++ {0x0218, 0x00001402, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000003, 0x00000000, 4, 0},
++ {0x0224, 0x00004a00, 0x00000000, 4, 0},
++ {0x0228, 0x00000008, 0x00000000, 4, 0},
++ {0x022c, 0x00000002, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
++// 1280x720 colorbar
++ {0x000a, 0x00000a00, 0x00000000, 2, 0},
++ {0x7080, 0x00000082, 0x00000000, 2, 0},
++// 128 pixel black - repeat 128 times
++ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
++// 128 pixel blue - repeat 64 times
++ {0x7000, 0x000000ff, 0x00000000, 2, 0},
++ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel red - repeat 64 times
++ {0x7000, 0x00000000, 0x00000000, 2, 0},
++ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel pink - repeat 64 times
++ {0x7000, 0x00007fff, 0x00000000, 2, 0},
++ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel green - repeat 64 times
++ {0x7000, 0x00007f00, 0x00000000, 2, 0},
++ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel light blue - repeat 64 times
++ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
++ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel yellow - repeat 64 times
++ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
++ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel white - repeat 64 times
++ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
++ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
++// 720 lines
++ {0x7090, 0x000002cf, 0x00000000, 2, 0},
++ {0x7092, 0x000006b8, 0x00000000, 2, 0},
++ {0x7094, 0x00000010, 0x00000000, 2, 0},
++ {0x7080, 0x00000083, 0x00000000, 2, 0},
++};
++
++static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0010, 0x0000001e, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x000080c7, 0x00000000, 2, 0},
++ {0x0022, 0x00000213, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00001e00, 0x00000000, 4, 0},
++ {0x0214, 0x00000003, 0x00000000, 4, 0},
++ {0x0218, 0x00001402, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000003, 0x00000000, 4, 0},
++ {0x0224, 0x00004a00, 0x00000000, 4, 0},
++ {0x0228, 0x00000008, 0x00000000, 4, 0},
++ {0x022c, 0x00000002, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
++// 1920x1023 colorbar
++ {0x000a, 0x00000f00, 0x00000000, 2, 0},
++ {0x7080, 0x00000082, 0x00000000, 2, 0},
++// 128 pixel black - repeat 128 times
++ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
++// 128 pixel blue - repeat 64 times
++ {0x7000, 0x000000ff, 0x00000000, 2, 0},
++ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel red - repeat 64 times
++ {0x7000, 0x00000000, 0x00000000, 2, 0},
++ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel pink - repeat 64 times
++ {0x7000, 0x00007fff, 0x00000000, 2, 0},
++ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel green - repeat 64 times
++ {0x7000, 0x00007f00, 0x00000000, 2, 0},
++ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel light blue - repeat 64 times
++ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
++ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel yellow - repeat 64 times
++ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
++ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
++// 128 pixel white - repeat 64 times
++ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
++ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
++// 1023 lines
++ {0x7090, 0x000003fe, 0x00000000, 2, 0},
++ {0x7092, 0x000004d8, 0x00000000, 2, 0},
++ {0x7094, 0x0000002d, 0x00000000, 2, 0},
++ {0x7080, 0x00000083, 0x00000000, 2, 0},
++};
++
++static const struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0010, 0x0000001e, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x00008073, 0x00000000, 2, 0},
++ {0x0022, 0x00000213, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++// {0x014c, 0x00000000, 0x00000000, 4, 0},
++// {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00001200, 0x00000000, 4, 0},
++ {0x0214, 0x00000002, 0x00000000, 4, 0},
++ {0x0218, 0x00000b02, 0x00000000, 4, 0},
++ {0x021c, 0x00000001, 0x00000000, 4, 0},
++ {0x0220, 0x00000103, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000008, 0x00000000, 4, 0},
++ {0x022c, 0x00000002, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000000, 0x00000000, 4, 0},
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xA3008082, 0x00000000, 4, 0},
++// 640x480 colorbar
++ {0x000a, 0x00000500, 0x00000000, 2, 0},
++ {0x7080, 0x00000082, 0x00000000, 2, 0},
++// 80 pixel black - repeate 80 times
++ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)},
++// 80 pixel blue - repeate 40 times
++ {0x7000, 0x000000ff, 0x00000000, 2, 0},
++ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel red - repeate 40 times
++ {0x7000, 0x00000000, 0x00000000, 2, 0},
++ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel pink - repeate 40 times
++ {0x7000, 0x00007fff, 0x00000000, 2, 0},
++ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel green - repeate 40 times
++ {0x7000, 0x00007f00, 0x00000000, 2, 0},
++ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel light blue - repeate 40 times
++ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
++ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel yellow - repeate 40 times
++ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
++ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel white - repeate 40 times
++ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
++ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)},
++// 480 lines
++ {0x7090, 0x000001df, 0x00000000, 2, 0},
++ {0x7092, 0x00000898, 0x00000000, 2, 0},
++ {0x7094, 0x00000285, 0x00000000, 2, 0},
++ {0x7080, 0x00000083, 0x00000000, 2, 0},
++};
++
++static const struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont[] = {
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0010, 0x0000001e, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x0000404F, 0x00000000, 2, 0},
++ {0x0022, 0x00000613, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00001800, 0x00000000, 4, 0},
++ {0x0214, 0x00000002, 0x00000000, 4, 0},
++ {0x0218, 0x00001102, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000003, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000007, 0x00000000, 4, 0},
++ {0x022c, 0x00000001, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0},
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
++// 640x480 colorbar
++ {0x000a, 0x00000500, 0x00000000, 2, 0},
++ {0x7080, 0x00000082, 0x00000000, 2, 0},
++// 80 pixel black - repeate 80 times
++ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)},
++// 80 pixel blue - repeate 40 times
++ {0x7000, 0x000000ff, 0x00000000, 2, 0},
++ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel red - repeate 40 times
++ {0x7000, 0x00000000, 0x00000000, 2, 0},
++ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel pink - repeate 40 times
++ {0x7000, 0x00007fff, 0x00000000, 2, 0},
++ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel green - repeate 40 times
++ {0x7000, 0x00007f00, 0x00000000, 2, 0},
++ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel light blue - repeate 40 times
++ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
++ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel yellow - repeate 40 times
++ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
++ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)},
++// 80 pixel white - repeate 40 times
++ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
++ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)},
++// 480 lines
++ {0x7090, 0x000001df, 0x00000000, 2, 0},
++ {0x7092, 0x00000700, 0x00000000, 2, 0},
++ {0x7094, 0x00000010, 0x00000000, 2, 0},
++ {0x7080, 0x00000083, 0x00000000, 2, 0},
++};
++
++//480p RGB2YUV442
++static const struct reg_value tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz[] = {
++ {0x0006, 0x00000040, 0x00000000, 2, 0},
++// {0x000a, 0x000005a0, 0x00000000, 2, 0},
++// {0x0010, 0x0000001e, 0x00000000, 2, 0},
++ {0x0014, 0x00000000, 0x00000000, 2, 0},
++ {0x0016, 0x000005ff, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x0000405c, 0x00000000, 2, 0},
++ {0x0022, 0x00000613, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00000d00, 0x00000000, 4, 0},
++ {0x0214, 0x00000001, 0x00000000, 4, 0},
++ {0x0218, 0x00000701, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000001, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000005, 0x00000000, 4, 0},
++ {0x022c, 0x00000000, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0},
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
++// HDMI Interrupt Mask
++ {0x8502, 0x00000001, 0x00000000, 1, 0},
++ {0x8512, 0x000000fe, 0x00000000, 1, 0},
++ {0x8514, 0x00000000, 0x00000000, 1, 0},
++ {0x8515, 0x00000000, 0x00000000, 1, 0},
++ {0x8516, 0x00000000, 0x00000000, 1, 0},
++// HDMI Audio
++ {0x8531, 0x00000001, 0x00000000, 1, 0},
++ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
++ {0x8670, 0x00000001, 0x00000000, 1, 0},
++// HDMI PHY
++ {0x8532, 0x00000080, 0x00000000, 1, 0},
++ {0x8536, 0x00000040, 0x00000000, 1, 0},
++ {0x853f, 0x0000000a, 0x00000000, 1, 0},
++// HDMI System
++ {0x8545, 0x00000031, 0x00000000, 1, 0},
++ {0x8546, 0x0000002d, 0x00000000, 1, 0},
++// HDCP Setting
++ {0x85d1, 0x00000001, 0x00000000, 1, 0},
++ {0x8560, 0x00000024, 0x00000000, 1, 0},
++ {0x8563, 0x00000011, 0x00000000, 1, 0},
++ {0x8564, 0x0000000f, 0x00000000, 1, 0},
++// RGB --> YUV Conversion
++ {0x8573, 0x00000081, 0x00000000, 1, 0},
++ {0x8571, 0x00000002, 0x00000000, 1, 0},
++// HDMI Audio In Setting
++ {0x8600, 0x00000000, 0x00000000, 1, 0},
++ {0x8602, 0x000000f3, 0x00000000, 1, 0},
++ {0x8603, 0x00000002, 0x00000000, 1, 0},
++ {0x8604, 0x0000000c, 0x00000000, 1, 0},
++ {0x8606, 0x00000005, 0x00000000, 1, 0},
++ {0x8607, 0x00000000, 0x00000000, 1, 0},
++ {0x8620, 0x00000022, 0x00000000, 1, 0},
++ {0x8640, 0x00000001, 0x00000000, 1, 0},
++ {0x8641, 0x00000065, 0x00000000, 1, 0},
++ {0x8642, 0x00000007, 0x00000000, 1, 0},
++ {0x8652, 0x00000002, 0x00000000, 1, 0},
++ {0x8665, 0x00000010, 0x00000000, 1, 0},
++// InfoFrame Extraction
++ {0x8709, 0x000000ff, 0x00000000, 1, 0},
++ {0x870b, 0x0000002c, 0x00000000, 1, 0},
++ {0x870c, 0x00000053, 0x00000000, 1, 0},
++ {0x870d, 0x00000001, 0x00000000, 1, 0},
++ {0x870e, 0x00000030, 0x00000000, 1, 0},
++ {0x9007, 0x00000010, 0x00000000, 1, 0},
++ {0x854a, 0x00000001, 0x00000000, 1, 0},
++// Output Control
++ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
++ };
++
++//480p RGB2YUV442
++static const struct reg_value tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz[] = {
++ {0x0006, 0x00000040, 0x00000000, 2, 0},
++ {0x000a, 0x000005a0, 0x00000000, 2, 0},
++// {0x0010, 0x0000001e, 0x00000000, 2, 0},
++ {0x0014, 0x00000000, 0x00000000, 2, 0},
++ {0x0016, 0x000005ff, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x0000405b, 0x00000000, 2, 0},
++ {0x0022, 0x00000613, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00000d00, 0x00000000, 4, 0},
++ {0x0214, 0x00000001, 0x00000000, 4, 0},
++ {0x0218, 0x00000701, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000001, 0x00000000, 4, 0},
++ {0x0224, 0x00004000, 0x00000000, 4, 0},
++ {0x0228, 0x00000005, 0x00000000, 4, 0},
++ {0x022c, 0x00000000, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0},
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
++// HDMI Interrupt Mask
++ {0x8502, 0x00000001, 0x00000000, 1, 0},
++ {0x8512, 0x000000fe, 0x00000000, 1, 0},
++ {0x8514, 0x00000000, 0x00000000, 1, 0},
++ {0x8515, 0x00000000, 0x00000000, 1, 0},
++ {0x8516, 0x00000000, 0x00000000, 1, 0},
++// HDMI Audio
++ {0x8531, 0x00000001, 0x00000000, 1, 0},
++ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
++ {0x8670, 0x00000001, 0x00000000, 1, 0},
++// HDMI PHY
++ {0x8532, 0x00000080, 0x00000000, 1, 0},
++ {0x8536, 0x00000040, 0x00000000, 1, 0},
++ {0x853f, 0x0000000a, 0x00000000, 1, 0},
++// HDMI System
++ {0x8545, 0x00000031, 0x00000000, 1, 0},
++ {0x8546, 0x0000002d, 0x00000000, 1, 0},
++// HDCP Setting
++ {0x85d1, 0x00000001, 0x00000000, 1, 0},
++ {0x8560, 0x00000024, 0x00000000, 1, 0},
++ {0x8563, 0x00000011, 0x00000000, 1, 0},
++ {0x8564, 0x0000000f, 0x00000000, 1, 0},
++// RGB --> YUV Conversion
++ {0x8573, 0x00000081, 0x00000000, 1, 0},
++ {0x8571, 0x00000002, 0x00000000, 1, 0},
++// HDMI Audio In Setting
++ {0x8600, 0x00000000, 0x00000000, 1, 0},
++ {0x8602, 0x000000f3, 0x00000000, 1, 0},
++ {0x8603, 0x00000002, 0x00000000, 1, 0},
++ {0x8604, 0x0000000c, 0x00000000, 1, 0},
++ {0x8606, 0x00000005, 0x00000000, 1, 0},
++ {0x8607, 0x00000000, 0x00000000, 1, 0},
++ {0x8620, 0x00000022, 0x00000000, 1, 0},
++ {0x8640, 0x00000001, 0x00000000, 1, 0},
++ {0x8641, 0x00000065, 0x00000000, 1, 0},
++ {0x8642, 0x00000007, 0x00000000, 1, 0},
++ {0x8652, 0x00000002, 0x00000000, 1, 0},
++ {0x8665, 0x00000010, 0x00000000, 1, 0},
++// InfoFrame Extraction
++ {0x8709, 0x000000ff, 0x00000000, 1, 0},
++ {0x870b, 0x0000002c, 0x00000000, 1, 0},
++ {0x870c, 0x00000053, 0x00000000, 1, 0},
++ {0x870d, 0x00000001, 0x00000000, 1, 0},
++ {0x870e, 0x00000030, 0x00000000, 1, 0},
++ {0x9007, 0x00000010, 0x00000000, 1, 0},
++ {0x854a, 0x00000001, 0x00000000, 1, 0},
++// Output Control
++ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
++ };
++
++static const struct reg_value tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz[] = {
++ {0x0004, 0x00000084, 0x00000000, 2, 0},
++ {0x0006, 0x00000000, 0x00000000, 2, 0},
++ {0x0014, 0x00000000, 0x00000000, 2, 0},
++ {0x0016, 0x000005ff, 0x00000000, 2, 0},
++// Program CSI Tx PLL
++ {0x0020, 0x000080c7, 0x00000000, 2, 0},
++ {0x0022, 0x00000213, 0x00000000, 2, 0},
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0},
++ {0x0144, 0x00000000, 0x00000000, 4, 0},
++ {0x0148, 0x00000000, 0x00000000, 4, 0},
++ {0x014c, 0x00000000, 0x00000000, 4, 0},
++ {0x0150, 0x00000000, 0x00000000, 4, 0},
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00001e00, 0x00000000, 4, 0},
++ {0x0214, 0x00000003, 0x00000000, 4, 0},
++ {0x0218, 0x00001402, 0x00000000, 4, 0},
++ {0x021c, 0x00000000, 0x00000000, 4, 0},
++ {0x0220, 0x00000003, 0x00000000, 4, 0},
++ {0x0224, 0x00004a00, 0x00000000, 4, 0},
++ {0x0228, 0x00000008, 0x00000000, 4, 0},
++ {0x022c, 0x00000002, 0x00000000, 4, 0},
++ {0x0234, 0x0000001f, 0x00000000, 4, 0},
++ {0x0238, 0x00000001, 0x00000000, 4, 0},
++ {0x0204, 0x00000001, 0x00000000, 4, 0},
++ {0x0518, 0x00000001, 0x00000000, 4, 0},
++ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
++// HDMI Interrupt Mask
++ {0x8502, 0x00000001, 0x00000000, 1, 0},
++ {0x8512, 0x000000fe, 0x00000000, 1, 0},
++ {0x8514, 0x00000000, 0x00000000, 1, 0},
++ {0x8515, 0x00000000, 0x00000000, 1, 0},
++ {0x8516, 0x00000000, 0x00000000, 1, 0},
++// HDMI Audio
++ {0x8531, 0x00000001, 0x00000000, 1, 0},
++ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
++ {0x8670, 0x00000001, 0x00000000, 1, 0},
++// HDMI PHY
++ {0x8532, 0x00000080, 0x00000000, 1, 0},
++ {0x8536, 0x00000040, 0x00000000, 1, 0},
++ {0x853f, 0x0000000a, 0x00000000, 1, 0},
++// HDMI System
++ {0x8545, 0x00000031, 0x00000000, 1, 0},
++ {0x8546, 0x0000002d, 0x00000000, 1, 0},
++// HDCP Setting
++ {0x85d1, 0x00000001, 0x00000000, 1, 0},
++ {0x8560, 0x00000024, 0x00000000, 1, 0},
++ {0x8563, 0x00000011, 0x00000000, 1, 0},
++ {0x8564, 0x0000000f, 0x00000000, 1, 0},
++// RGB --> YUV Conversion
++ {0x8571, 0x00000002, 0x00000000, 1, 0},
++ {0x8573, 0x00000081, 0x00000000, 1, 0},
++ {0x8576, 0x00000060, 0x00000000, 1, 0},
++// HDMI Audio In Setting
++ {0x8600, 0x00000000, 0x00000000, 1, 0},
++ {0x8602, 0x000000f3, 0x00000000, 1, 0},
++ {0x8603, 0x00000002, 0x00000000, 1, 0},
++ {0x8604, 0x0000000c, 0x00000000, 1, 0},
++ {0x8606, 0x00000005, 0x00000000, 1, 0},
++ {0x8607, 0x00000000, 0x00000000, 1, 0},
++ {0x8620, 0x00000022, 0x00000000, 1, 0},
++ {0x8640, 0x00000001, 0x00000000, 1, 0},
++ {0x8641, 0x00000065, 0x00000000, 1, 0},
++ {0x8642, 0x00000007, 0x00000000, 1, 0},
++ {0x8652, 0x00000002, 0x00000000, 1, 0},
++ {0x8665, 0x00000010, 0x00000000, 1, 0},
++// InfoFrame Extraction
++ {0x8709, 0x000000ff, 0x00000000, 1, 0},
++ {0x870b, 0x0000002c, 0x00000000, 1, 0},
++ {0x870c, 0x00000053, 0x00000000, 1, 0},
++ {0x870d, 0x00000001, 0x00000000, 1, 0},
++ {0x870e, 0x00000030, 0x00000000, 1, 0},
++ {0x9007, 0x00000010, 0x00000000, 1, 0},
++ {0x854a, 0x00000001, 0x00000000, 1, 0},
++// Output Control
++ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
++};
++
++static const struct reg_value tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz[] = {
++ {0x0004, 0x00000084, 0x00000000, 2, 0}, // Internal Generated output pattern,Do not send InfoFrame data out to CSI2,Audio output to CSI2-TX i/f,I2C address index increments on every data byte transfer, disable audio and video TX buffers
++ {0x0006, 0x000001f8, 0x00000000, 2, 0}, // FIFO level = 1f8 = 504
++ {0x0014, 0x00000000, 0x00000000, 2, 0}, // Clear interrupt status bits
++ {0x0016, 0x000005ff, 0x00000000, 2, 0}, // Mask audio mute, CSI-TX, and the other interrups
++// Program CSI Tx PLL
++ //{0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200
++ {0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200
++ {0x0022, 0x00000213, 0x00000000, 2, 0}, // HSCK frequency = 500MHz – 1GHz HSCK frequency, Loop bandwidth setting = 50% of maximum loop bandwidth (default), REFCLK toggling –> normal operation, REFCLK stops -> no oscillation, Bypass clock = normal operation, clocks switched off (output LOW), PLL Reset normal operation, PLL Enable = PLL on
++// CSI Tx PHY (32-bit Registers)
++ {0x0140, 0x00000000, 0x00000000, 4, 0}, // Clock Lane DPHY Control: Bypass Lane Enable from PPI Layer enable.
++ {0x0144, 0x00000000, 0x00000000, 4, 0}, // Data Lane 0 DPHY Control: Bypass Lane Enable from PPI Layer enable.
++ {0x0148, 0x00000000, 0x00000000, 4, 0}, // Data Lane 1 DPHY Control: Bypass Lane Enable from PPI Layer enable.
++ {0x014c, 0x00000000, 0x00000000, 4, 0}, // Data Lane 2 DPHY Control: Bypass Lane Enable from PPI Layer enable.
++ {0x0150, 0x00000000, 0x00000000, 4, 0}, // Data Lane 3 DPHY Control: Bypass Lane Enable from PPI Layer enable.
++// CSI Tx PPI (32-bit Registers)
++ {0x0210, 0x00001e00, 0x00000000, 4, 0}, // LINEINITCNT: Line Initialization Wait Counter = 0x1e00 = 7680
++ {0x0214, 0x00000003, 0x00000000, 4, 0}, // LPTXTIMECNT: SYSLPTX Timing Generation Counter = 3
++ {0x0218, 0x00001402, 0x00000000, 4, 0}, // TCLK_HEADERCNT: TCLK_ZERO Counter = 0x14 = 20, TCLK_PREPARE Counter = 0x02 = 2
++ {0x021c, 0x00000000, 0x00000000, 4, 0}, // TCLK_TRAILCNT: TCLK_TRAIL Counter = 0
++ {0x0220, 0x00000003, 0x00000000, 4, 0}, // THS_HEADERCNT: THS_ZERO Counter = 0, THS_PREPARE Counter = 3
++ {0x0224, 0x00004a00, 0x00000000, 4, 0}, // TWAKEUP: TWAKEUP Counter = 0x4a00 = 18944
++ {0x0228, 0x00000008, 0x00000000, 4, 0}, // TCLK_POSTCNT: TCLK_POST Counter = 8
++ {0x022c, 0x00000002, 0x00000000, 4, 0}, // THS_TRAILCNT: THS_TRAIL Counter = 2
++ {0x0234, 0x0000001f, 0x00000000, 4, 0}, // HSTXVREGEN: Enable voltage regulators for lanes and clk
++ {0x0238, 0x00000001, 0x00000000, 4, 0}, // TXOPTIONCNTRL: Set Continuous Clock Mode
++ {0x0204, 0x00000001, 0x00000000, 4, 0}, // PPI STARTCNTRL: start PPI function
++ {0x0518, 0x00000001, 0x00000000, 4, 0}, // CSI_START: start
++ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, // CSI Configuration Register: set register 0x040C with data 0x80a6 (CSI MOde, Disables the HTX_TO timer, High-Speed data transfer is performed to Tx, DSCClk Stays in HS mode when Data Lane goes to LP, 4 Data Lanes,The EOT packet is automatically granted at the end of HS transfer then is transmitted)
++// HDMI Interrupt Mask
++ {0x8502, 0x00000001, 0x00000000, 1, 0}, // SYSTEM INTERRUPT: clear DDC power change detection interrupt
++ {0x8512, 0x000000fe, 0x00000000, 1, 0}, // SYS INTERRUPT MASK: DDC power change detection interrupt not masked
++ {0x8514, 0x00000000, 0x00000000, 1, 0}, // PACKET INTERRUPT MASK: unmask all
++ {0x8515, 0x00000000, 0x00000000, 1, 0}, // CBIT INTERRUPT MASK: unmask all
++ {0x8516, 0x00000000, 0x00000000, 1, 0}, // AUDIO INTERRUPT MASK: unmask all
++// HDMI Audio
++ {0x8531, 0x00000001, 0x00000000, 1, 0}, // PHY CONTROL0: 27MHz, DDC5V detection operation.
++ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, // Audio FS Lock Detect Control: for 27MHz
++ {0x8670, 0x00000001, 0x00000000, 1, 0},
++// HDMI PHY
++ {0x8532, 0x00000080, 0x00000000, 1, 0}, //
++ {0x8536, 0x00000040, 0x00000000, 1, 0}, //
++ {0x853f, 0x0000000a, 0x00000000, 1, 0}, //
++// HDMI System
++ {0x8545, 0x00000031, 0x00000000, 1, 0}, // ANA CONTROL: PLL charge pump setting for Audio = normal, DAC/PLL power ON/OFF setting for Audio = ON
++ {0x8546, 0x0000002d, 0x00000000, 1, 0}, // AVMUTE CONTROL: AVM_CTL = 0x2d
++// HDCP Setting
++ {0x85d1, 0x00000001, 0x00000000, 1, 0}, //
++ {0x8560, 0x00000024, 0x00000000, 1, 0}, // HDCP MODE: HDCP automatic reset when DVI⇔HDMI switched = on, HDCP Line Rekey timing switch = 7clk mode (Data island delay ON), Bcaps[5] KSVINFO_READY(0x8840[5]) auto clear mode = Auto clear using AKSV write
++ {0x8563, 0x00000011, 0x00000000, 1, 0}, //
++ {0x8564, 0x0000000f, 0x00000000, 1, 0}, //
++// RGB --> YUV Conversion
++ {0x8571, 0x00000002, 0x00000000, 1, 0}, //
++ {0x8573, 0x000000c1, 0x00000000, 1, 0}, // VOUT SET2 REGISTER: 422 fixed output, Video Output 422 conversion mode selection 000: During 444 input, 3tap filter; during 422 input, simple decimation, Enable RGB888 to YUV422 Conversion (Fixed Color output)
++ {0x8574, 0x00000008, 0x00000000, 1, 0}, // VOUT SET3 REGISTER (VOUT_SET3): Follow register bit 0x8573[7] setting
++ {0x8576, 0x00000060, 0x00000000, 1, 0}, // VOUT_COLOR: Output Color = 601 YCbCr Limited, Input Pixel Repetition judgment = automatic, Input Pixel Repetition HOST setting = no repetition
++// HDMI Audio In Setting
++ {0x8600, 0x00000000, 0x00000000, 1, 0},
++ {0x8602, 0x000000f3, 0x00000000, 1, 0},
++ {0x8603, 0x00000002, 0x00000000, 1, 0},
++ {0x8604, 0x0000000c, 0x00000000, 1, 0},
++ {0x8606, 0x00000005, 0x00000000, 1, 0},
++ {0x8607, 0x00000000, 0x00000000, 1, 0},
++ {0x8620, 0x00000022, 0x00000000, 1, 0},
++ {0x8640, 0x00000001, 0x00000000, 1, 0},
++ {0x8641, 0x00000065, 0x00000000, 1, 0},
++ {0x8642, 0x00000007, 0x00000000, 1, 0},
++ {0x8652, 0x00000002, 0x00000000, 1, 0},
++ {0x8665, 0x00000010, 0x00000000, 1, 0},
++// InfoFrame Extraction
++ {0x8709, 0x000000ff, 0x00000000, 1, 0}, // PACKET INTERRUPT MODE: all enable
++ {0x870b, 0x0000002c, 0x00000000, 1, 0}, // NO PACKET LIMIT: NO_ACP_LIMIT = 0x2, NO_AVI_LIMIT = 0xC
++ {0x870c, 0x00000053, 0x00000000, 1, 0}, // When VS receive interrupt is detected, VS storage register automatic clear, When ACP receive interrupt is detected, ACP storage register automatic clear, When AVI receive interrupt occurs, judge input video signal with RGB and no Repetition, When AVI receive interrupt is detected, AVI storage register automatic clear.
++ {0x870d, 0x00000001, 0x00000000, 1, 0}, // ERROR PACKET LIMIT: Packet continuing receive error occurrence detection threshold = 1
++ {0x870e, 0x00000030, 0x00000000, 1, 0}, // NO PACKET LIMIT:
++ {0x9007, 0x00000010, 0x00000000, 1, 0}, //
++ {0x854a, 0x00000001, 0x00000000, 1, 0}, // Initialization completed flag
++// Output Control
++ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, // Configuration Control Register: Power Island Normal, I2S/TDM clock are free running, Enable 2 Audio channels, Audio channel number Auto detect by HW, I2S/TDM Data no delay, Select YCbCr422 8-bit (HDMI YCbCr422 12-bit data format), Send InfoFrame data out to CSI2, Audio output to I2S i/f (valid for 2 channel only), I2C address index increments on every data byte transfer, Audio and Video tx buffres enable.
++};
++
++/* list of image formats supported by TCM825X sensor */
++static const struct v4l2_fmtdesc tc358743_formats[] = {
++ {
++ .description = "RGB888 (RGB24)",
++ .pixelformat = V4L2_PIX_FMT_RGB24, /* 24 RGB-8-8-8 */
++ .flags = MIPI_DT_RGB888 // 0x24
++ },
++ {
++ .description = "RAW12 (Y/CbCr 4:2:0)",
++ .pixelformat = V4L2_PIX_FMT_UYVY, /* 12 Y/CbCr 4:2:0 */
++ .flags = MIPI_DT_RAW12 // 0x2c
++ },
++ {
++ .description = "YUV 4:2:2 8-bit",
++ .pixelformat = V4L2_PIX_FMT_YUYV, /* 8 8-bit color */
++ .flags = MIPI_DT_YUV422 // 0x1e /* UYVY... */
++ },
++};
++
++
++static const struct tc358743_mode_info tc358743_mode_info_data[2][tc358743_mode_MAX] = {
++/* Color bar test settings */
++ [1][tc358743_mode_INIT] =
++ {"cb640x480-108MHz@30", tc358743_mode_INIT, 640, 480,
++ 6, 1, 2, 108,
++ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont),
++ MIPI_DT_YUV422
++ },
++ [0][tc358743_mode_INIT] =
++ {"cb640x480-108MHz@60", tc358743_mode_INIT, 640, 480,
++ 6, 1, 2, 108,
++ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_INIT4] =
++ {"cb640x480-174Mhz@30", tc358743_mode_INIT4, 640, 480,
++ 6, 1, 2, 174,
++ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz),
++ MIPI_DT_YUV422
++ },
++ [0][tc358743_mode_INIT4] =
++ {"cb640x480-174MHz@60", tc358743_mode_INIT4, 640, 480,
++ 6, 1, 2, 174,
++ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_INIT3] =
++ {"cb1024x720-4lane@30", tc358743_mode_INIT3, 1024, 720,
++ 6, 1, 4, 300,
++ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz),
++ MIPI_DT_YUV422
++ },
++ [0][tc358743_mode_INIT3] =
++ {"cb1024x720-4lane@60", tc358743_mode_INIT3, 1024, 720,
++ 6, 1, 4, 300,
++ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_INIT1] =
++ {"cb1280x720-2lane@30", tc358743_mode_INIT1, 1280, 720,
++ 12, 0, 2, 125,
++ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz),
++ MIPI_DT_YUV422
++ },
++ [0][tc358743_mode_INIT1] =
++ {"cb1280x720-2lane@60", tc358743_mode_INIT1, 1280, 720,
++ 12, 0, 2, 125,
++ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_INIT2] =
++ {"cb1280x720-4lane-125MHz@30", tc358743_mode_INIT2, 1280, 720,
++ 12, 0, 4, 125,
++ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz),
++ MIPI_DT_YUV422
++ },
++ [0][tc358743_mode_INIT2] =
++ {"cb1280x720-4lane-125MHz@60", tc358743_mode_INIT2, 1280, 720,
++ 12, 0, 4, 125,
++ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_INIT5] =
++ {"cb1280x720-4lane-300MHz@30", tc358743_mode_INIT5, 1280, 720,
++ 12, 0, 4, 300,
++ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz),
++ MIPI_DT_YUV422
++ },
++ [0][tc358743_mode_INIT5] =
++ {"cb1280x720-4lane-300MHz@60", tc358743_mode_INIT5, 1280, 720,
++ 12, 0, 4, 300,
++ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_INIT6] =
++ {"cb1920x1023@30", tc358743_mode_INIT6, 1920, 1023,
++ 15, 0, 4, 300,
++ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz),
++ MIPI_DT_YUV422
++ },
++ [0][tc358743_mode_INIT6] =
++ {"cb1920x1023@60", tc358743_mode_INIT6, 1920, 1023,
++ 15, 0, 4, 300,
++ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz),
++ MIPI_DT_YUV422
++ },
++/* Input settings */
++ [tc358743_60_fps][tc358743_mode_480P_640_480] =
++ {"640x480@60", tc358743_mode_480P_640_480, 640, 480,
++ 1, (0x02)<<8|(0x00), 2, 125,
++ tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz),
++ MIPI_DT_YUV422,
++ },
++ [1][tc358743_mode_480P_720_480] =
++ {"720x480@30", tc358743_mode_480P_720_480, 720, 480,
++ 6, (0x02)<<8|(0x00), 2, 125,
++ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz),
++ MIPI_DT_YUV422,
++ },
++ [tc358743_60_fps][tc358743_mode_480P_720_480] =
++ {"720x480@60", tc358743_mode_480P_720_480, 720, 480,
++ 6, (0x02)<<8|(0x00), 2, 125,
++ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz),
++ MIPI_DT_YUV422,
++ },
++ [tc358743_60_fps][tc358743_mode_1024x768] =
++ {"1024x768@60", tc358743_mode_1024x768, 1024, 768,
++ 16, 60, 4, 125,
++ tc358743_setting_YUV422_4lane_1024x768_60fps_125MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1024x768_60fps_125MHz),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_720P_1280_720] =
++ {"1280x720-2lane@30", tc358743_mode_720P_1280_720, 1280, 720,
++ 12, (0x3e)<<8|(0x3c), 2, 125,
++ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz),
++ MIPI_DT_YUV422,
++ },
++ [0][tc358743_mode_720P_1280_720] =
++ {"1280x720-2lane@60", tc358743_mode_720P_1280_720, 1280, 720,
++ 12, (0x3e)<<8|(0x3c), 2, 125,
++ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz),
++ MIPI_DT_YUV422,
++ },
++ [1][tc358743_mode_720P_60_1280_720] =
++ {"1280x720-4lane-133Mhz@30", tc358743_mode_720P_60_1280_720, 1280, 720,
++ 12, 0, 4, 133,
++ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz),
++ MIPI_DT_YUV422
++ },
++ [tc358743_60_fps][tc358743_mode_720P_60_1280_720] =
++ {"1280x720-4lane@60", tc358743_mode_720P_60_1280_720, 1280, 720,
++ 12, 0, 4, 133,
++ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz),
++ MIPI_DT_YUV422
++ },
++ [1][tc358743_mode_1080P_1920_1080] =
++ {"1920x1080@30", tc358743_mode_1080P_1920_1080, 1920, 1080,
++ 15, 0xa, 4, 300,
++ tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz),
++ MIPI_DT_YUV422
++ },
++ [tc358743_60_fps][tc358743_mode_1080P_1920_1080] =
++ {"1920x1080@60", tc358743_mode_1080P_1920_1080, 1920, 1080,
++ 15, 0x0b, 4, 300,
++ tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz,
++ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz),
++ MIPI_DT_YUV422
++ },
++};
++
++static int tc358743_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int tc358743_remove(struct i2c_client *client);
++
++static const struct i2c_device_id tc358743_id[] = {
++ {"tc358743_mipi", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, tc358743_id);
++
++static struct i2c_driver tc358743_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "tc358743_mipi",
++ },
++ .probe = tc358743_probe,
++ .remove = tc358743_remove,
++ .id_table = tc358743_id,
++};
++
++struct _reg_size
++{
++ u16 startaddr, endaddr;
++ int size;
++};
++
++static const struct _reg_size tc358743_read_reg_size[] =
++{
++ {0x0000, 0x005a, 2},
++ {0x0140, 0x0150, 4},
++ {0x0204, 0x0238, 4},
++ {0x040c, 0x0418, 4},
++ {0x044c, 0x0454, 4},
++ {0x0500, 0x0518, 4},
++ {0x0600, 0x06cc, 4},
++ {0x7000, 0x7100, 2},
++ {0x8500, 0x8bff, 1},
++ {0x8c00, 0x8fff, 4},
++ {0x9000, 0x90ff, 1},
++ {0x9100, 0x92ff, 1},
++ {0, 0, 0},
++};
++
++int get_reg_size(u16 reg, int len)
++{
++ const struct _reg_size *p = tc358743_read_reg_size;
++ int size;
++
++#if 0 //later #ifndef DEBUG
++ if (len)
++ return len;
++#endif
++ while (p->size) {
++ if ((p->startaddr <= reg) && (reg <= p->endaddr)) {
++ size = p->size;
++ if (len && (size != len)) {
++ pr_err("%s:reg len error:reg=%x %d instead of %d\n",
++ __func__, reg, len, size);
++ return 0;
++ }
++ if (reg % size) {
++ pr_err("%s:cannot read from the middle of a register, reg(%x) size(%d)\n",
++ __func__, reg, size);
++ return 0;
++ }
++ return size;
++ }
++ p++;
++ }
++ pr_err("%s:reg=%x size is not defined\n",__func__, reg);
++ return 0;
++}
++
++static s32 tc358743_read_reg(struct sensor_data *sensor, u16 reg, void *rxbuf)
++{
++ struct i2c_client *client = sensor->i2c_client;
++ struct i2c_msg msgs[2];
++ u8 txbuf[2];
++ int ret;
++ int size = get_reg_size(reg, 0);
++
++ if (!size)
++ return -EINVAL;
++
++ txbuf[0] = reg >> 8;
++ txbuf[1] = reg & 0xff;
++ msgs[0].addr = client->addr;
++ msgs[0].flags = 0;
++ msgs[0].len = 2;
++ msgs[0].buf = txbuf;
++
++ msgs[1].addr = client->addr;
++ msgs[1].flags = I2C_M_RD;
++ msgs[1].len = size;
++ msgs[1].buf = rxbuf;
++
++ ret = i2c_transfer(client->adapter, msgs, 2);
++ if (ret < 0) {
++ pr_err("%s:reg=%x ret=%d\n", __func__, reg, ret);
++ return ret;
++ }
++// pr_debug("%s:reg=%x,val=%x\n", __func__, reg, ((char *)rxbuf)[0]);
++ return 0;
++}
++
++static s32 tc358743_read_reg_val(struct sensor_data *sensor, u16 reg)
++{
++ u32 val = 0;
++ tc358743_read_reg(sensor, reg, &val);
++ return val;
++}
++
++static s32 tc358743_read_reg_val16(struct sensor_data *sensor, u16 reg)
++{
++#if 0
++ struct i2c_client *client = sensor->i2c_client;
++ struct i2c_msg msgs[3];
++ u8 txbuf[4];
++ u8 rxbuf1[4];
++ u8 rxbuf2[4];
++ int ret;
++ int size = get_reg_size(reg, 0);
++
++ if (size != 1)
++ return -EINVAL;
++
++ txbuf[0] = reg >> 8;
++ txbuf[1] = reg & 0xff;
++ msgs[0].addr = client->addr;
++ msgs[0].flags = 0;
++ msgs[0].len = 2;
++ msgs[0].buf = txbuf;
++
++ msgs[1].addr = client->addr;
++ msgs[1].flags = I2C_M_RD;
++ msgs[1].len = size;
++ msgs[1].buf = rxbuf1;
++
++ msgs[2].addr = client->addr;
++ msgs[2].flags = I2C_M_RD;
++ msgs[2].len = size;
++ msgs[2].buf = rxbuf2;
++
++ ret = i2c_transfer(client->adapter, msgs, 3);
++ if (ret < 0) {
++ pr_err("%s:reg=%x ret=%d\n", __func__, reg, ret);
++ return ret;
++ }
++// pr_debug("%s:reg=%x,val=%x\n", __func__, reg, ((char *)rxbuf)[0]);
++ return rxbuf1[0] | (rxbuf2[0] << 8);
++#else
++ u32 val1 = 0;
++ u32 val2 = 0;
++ tc358743_read_reg(sensor, reg, &val1);
++ tc358743_read_reg(sensor, reg+1, &val2);
++ return val1 | (val2 << 8);
++
++#endif
++}
++
++static s32 tc358743_write_reg(struct sensor_data *sensor, u16 reg, u32 val, int len)
++{
++ int ret;
++ int i = 0;
++ u32 data = val;
++ u8 au8Buf[6] = {0};
++ int size = get_reg_size(reg, len);
++
++ if (!size)
++ return -EINVAL;
++
++ au8Buf[i++] = reg >> 8;
++ au8Buf[i++] = reg & 0xff;
++ while (size-- > 0) {
++ au8Buf[i++] = (u8)data;
++ data >>= 8;
++ }
++
++ ret = i2c_master_send(sensor->i2c_client, au8Buf, i);
++ if (ret < 0) {
++ pr_err("%s:write reg error(%d):reg=%x,val=%x\n",
++ __func__, ret, reg, val);
++ return ret;
++ }
++ if ((reg < 0x7000) || (reg >= 0x7100)) {
++ if (0) pr_debug("%s:reg=%x,val=%x 8543=%02x\n", __func__, reg, val, tc358743_read_reg_val(sensor, 0x8543));
++ }
++ return 0;
++}
++
++static void tc358743_software_reset(struct sensor_data *sensor)
++{
++ int freq = sensor->mclk / 10000;
++ tc358743_write_reg(sensor, 0x7080, 0, 2);
++ tc358743_write_reg(sensor, 0x0002, 0x0f00, 2);
++ msleep(100);
++ tc358743_write_reg(sensor, 0x0002, 0x0000, 2);
++ msleep(1000);
++ tc358743_write_reg(sensor, 0x0004, 0x0004, 2); /* autoinc */
++ pr_debug("%s:freq=%d\n", __func__, freq);
++ tc358743_write_reg(sensor, 0x8540, freq, 1);
++ tc358743_write_reg(sensor, 0x8541, freq >> 8, 1);
++}
++
++static void tc358743_enable_edid(struct sensor_data *sensor)
++{
++ pr_debug("Activate EDID\n");
++ // EDID
++ tc358743_write_reg(sensor, 0x85c7, 0x01, 1); // EDID MODE REGISTER: nternal EDID-RAM & DDC2B mode
++ tc358743_write_reg(sensor, 0x85ca, 0x00, 1);
++ tc358743_write_reg(sensor, 0x85cb, 0x01, 1); // 0x85cb:0x85ca - EDID Length = 0x01:00 (Size = 0x100 = 256)
++ tc358743_write_reg(sensor, 0x8543, 0x36, 1); // DDC CONTROL: DDC_ACK output terminal H active, DDC5V_active detect delay 200ms
++ tc358743_write_reg(sensor, 0x854a, 0x01, 1); // mark init done
++ if (0) pr_debug("%s: c7=%02x ca=%02x cb=%02x 43=%02x 4a=%02x\n", __func__,
++ tc358743_read_reg_val(sensor, 0x85c7),
++ tc358743_read_reg_val(sensor, 0x85ca),
++ tc358743_read_reg_val(sensor, 0x85cb),
++ tc358743_read_reg_val(sensor, 0x8543),
++ tc358743_read_reg_val(sensor, 0x854a));
++}
++
++static int tc358743_write_edid(struct sensor_data *sensor, const u8 *edid, int len)
++{
++ int i = 0, off = 0;
++ u8 au8Buf[16+2] = {0};
++ int size = 0;
++ int checksum = 0;
++ u16 reg;
++
++ reg = 0x8C00;
++ off = 0;
++ size = ARRAY_SIZE(au8Buf) - 2;
++ pr_debug("Write EDID: %d (%d)\n", len, size);
++ while (len > 0) {
++ i = 0;
++ au8Buf[i++] = (reg >> 8) & 0xff;
++ au8Buf[i++] = reg & 0xff;
++ if (size > len)
++ size = len;
++ while (i < size + 2) {
++ u8 byte = edid[off++];
++ if ((off & 0x7f) == 0) {
++ checksum &= 0xff;
++ if (checksum != byte) {
++ pr_info("%schecksum=%x, byte=%x\n", __func__, checksum, byte);
++ byte = checksum;
++ checksum = 0;
++ }
++ } else {
++ checksum -= byte;
++ }
++ au8Buf[i++] = byte;
++ }
++
++ if (i2c_master_send(sensor->i2c_client, au8Buf, i) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, off);
++ return -1;
++ }
++ len -= (u8)size;
++ reg += (u16)size;
++ }
++ tc358743_enable_edid(sensor);
++ return 0;
++}
++
++static s32 power_control(struct tc_data *td, int on)
++{
++ struct sensor_data *sensor = &td->sensor;
++ int i;
++ int ret = 0;
++
++ pr_debug("%s: %d\n", __func__, on);
++ if (sensor->on != on) {
++ if (on) {
++ for (i = 0; i < REGULATOR_CNT; i++) {
++ if (td->regulator[i]) {
++ ret = regulator_enable(td->regulator[i]);
++ if (ret) {
++ pr_err("%s:regulator_enable failed(%d)\n",
++ __func__, ret);
++ on = 0; /* power all off */
++ break;
++ }
++ }
++ }
++ }
++ tc_standby(td, on ? 0 : 1);
++ sensor->on = on;
++ if (!on) {
++ for (i = REGULATOR_CNT - 1; i >= 0; i--) {
++ if (td->regulator[i])
++ regulator_disable(td->regulator[i]);
++ }
++ }
++ }
++ return ret;
++}
++
++static int tc358743_toggle_hpd(struct sensor_data *sensor, int active)
++{
++ int ret = 0;
++ if (active) {
++ ret += tc358743_write_reg(sensor, 0x8544, 0x00, 1);
++ mdelay(500);
++ ret += tc358743_write_reg(sensor, 0x8544, 0x10, 1);
++ } else {
++ ret += tc358743_write_reg(sensor, 0x8544, 0x10, 1);
++ mdelay(500);
++ ret += tc358743_write_reg(sensor, 0x8544, 0x00, 1);
++ }
++ return ret;
++}
++
++static int get_format_index(enum tc358743_frame_rate frame_rate, enum tc358743_mode mode)
++{
++ int ifmt;
++ u32 flags = tc358743_mode_info_data[frame_rate][mode].flags;
++
++ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) {
++ if (flags == tc358743_formats[ifmt].flags)
++ return ifmt;
++ }
++ return -1;
++}
++
++static int get_pixelformat(enum tc358743_frame_rate frame_rate, enum tc358743_mode mode)
++{
++ int ifmt = get_format_index(frame_rate, mode);
++
++ if (ifmt < 0) {
++ pr_debug("%s: unsupported format, %d, %d\n", __func__, frame_rate, mode);
++ return 0;
++ }
++ pr_debug("%s: %s (%x, %x)\n", __func__,
++ tc358743_formats[ifmt].description,
++ tc358743_formats[ifmt].pixelformat,
++ tc358743_formats[ifmt].flags);
++ return tc358743_formats[ifmt].pixelformat;
++}
++
++int set_frame_rate_mode(struct tc_data *td,
++ enum tc358743_frame_rate frame_rate, enum tc358743_mode mode)
++{
++ struct sensor_data *sensor = &td->sensor;
++ const struct reg_value *pModeSetting = NULL;
++ s32 i = 0;
++ s32 iModeSettingArySize = 0;
++ register u32 RepeateLines = 0;
++ register int RepeateTimes = 0;
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u32 Mask = 0;
++ register u32 Val = 0;
++ u8 Length;
++ int retval = 0;
++
++ pModeSetting =
++ tc358743_mode_info_data[frame_rate][mode].init_data_ptr;
++ iModeSettingArySize =
++ tc358743_mode_info_data[frame_rate][mode].init_data_size;
++
++ sensor->pix.pixelformat = get_pixelformat(frame_rate, mode);
++ sensor->pix.width =
++ tc358743_mode_info_data[frame_rate][mode].width;
++ sensor->pix.height =
++ tc358743_mode_info_data[frame_rate][mode].height;
++ pr_debug("%s: Set %d regs from %p for frs %d mode %d with width %d height %d\n", __func__,
++ iModeSettingArySize,
++ pModeSetting,
++ frame_rate,
++ mode,
++ sensor->pix.width,
++ sensor->pix.height);
++ for (i = 0; i < iModeSettingArySize; ++i) {
++ pModeSetting = tc358743_mode_info_data[frame_rate][mode].init_data_ptr + i;
++
++ Delay_ms = pModeSetting->u32Delay_ms & (0xffff);
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u32Val;
++ Mask = pModeSetting->u32Mask;
++ Length = pModeSetting->u8Length;
++ if (Mask) {
++ u32 RegVal = 0;
++
++ retval = tc358743_read_reg(sensor, RegAddr, &RegVal);
++ if (retval < 0) {
++ pr_err("%s: read failed, reg=0x%x\n", __func__, RegAddr);
++ return retval;
++ }
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = tc358743_write_reg(sensor, RegAddr, Val, Length);
++ if (retval < 0) {
++ pr_err("%s: write failed, reg=0x%x\n", __func__, RegAddr);
++ return retval;
++ }
++ if (Delay_ms)
++ msleep(Delay_ms);
++
++ if (0 != ((pModeSetting->u32Delay_ms>>16) & (0xff))) {
++ if (!RepeateTimes) {
++ RepeateTimes = (pModeSetting->u32Delay_ms>>16) & (0xff);
++ RepeateLines = (pModeSetting->u32Delay_ms>>24) & (0xff);
++ }
++ if (--RepeateTimes > 0) {
++ i -= RepeateLines;
++ }
++ }
++ }
++ tc358743_enable_edid(sensor);
++ if (!td->edid_initialized) {
++ retval = tc358743_write_edid(sensor, cHDMIEDID, ARRAY_SIZE(cHDMIEDID));
++ if (retval)
++ pr_err("%s: Fail to write EDID(%d) to tc35874!\n", __func__, retval);
++ else
++ td->edid_initialized = 1;
++ }
++
++ return retval;
++}
++
++void mipi_csi2_swreset(struct mipi_csi2_info *info);
++#include "../../../../mxc/mipi/mxc_mipi_csi2.h"
++
++int mipi_reset(void *mipi_csi2_info,
++ enum tc358743_frame_rate frame_rate,
++ enum tc358743_mode mode)
++{
++ int lanes = tc358743_mode_info_data[frame_rate][mode].lanes;
++
++ if (!lanes)
++ lanes = 4;
++
++ pr_debug("%s: mipi_csi2_info:\n"
++ "mipi_en: %d\n"
++ "datatype: %d\n"
++ "dphy_clk: %p\n"
++ "pixel_clk: %p\n"
++ "mipi_csi2_base:%p\n"
++ "pdev: %p\n"
++ , __func__,
++ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_en,
++ ((struct mipi_csi2_info *)mipi_csi2_info)->datatype,
++ ((struct mipi_csi2_info *)mipi_csi2_info)->dphy_clk,
++ ((struct mipi_csi2_info *)mipi_csi2_info)->pixel_clk,
++ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_csi2_base,
++ ((struct mipi_csi2_info *)mipi_csi2_info)->pdev
++ );
++ if (mipi_csi2_get_status(mipi_csi2_info)) {
++ mipi_csi2_disable(mipi_csi2_info);
++ msleep(1);
++ }
++ mipi_csi2_enable(mipi_csi2_info);
++
++ if (!mipi_csi2_get_status(mipi_csi2_info)) {
++ pr_err("Can not enable mipi csi2 driver!\n");
++ return -1;
++ }
++ lanes = mipi_csi2_set_lanes(mipi_csi2_info, lanes);
++ pr_debug("Now Using %d lanes\n", lanes);
++
++ mipi_csi2_reset(mipi_csi2_info);
++ mipi_csi2_set_datatype(mipi_csi2_info, tc358743_mode_info_data[frame_rate][mode].flags);
++ return 0;
++}
++
++int mipi_wait(void *mipi_csi2_info)
++{
++ unsigned i = 0;
++ unsigned j;
++ u32 mipi_reg;
++ u32 mipi_reg_test[10];
++
++ /* wait for mipi sensor ready */
++ for (;;) {
++ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
++ mipi_reg_test[i++] = mipi_reg;
++ if (mipi_reg != 0x200)
++ break;
++ if (i >= 10) {
++ pr_err("mipi csi2 can not receive sensor clk!\n");
++ return -1;
++ }
++ msleep(10);
++ }
++
++ for (j = 0; j < i; j++) {
++ pr_debug("%d mipi csi2 dphy status %x\n", j, mipi_reg_test[j]);
++ }
++
++ i = 0;
++
++ /* wait for mipi stable */
++ for (;;) {
++ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
++ mipi_reg_test[i++] = mipi_reg;
++ if (!mipi_reg)
++ break;
++ if (i >= 10) {
++ pr_err("mipi csi2 can not reveive data correctly!\n");
++ return -1;
++ }
++ msleep(10);
++ }
++
++ for (j = 0; j < i; j++) {
++ pr_debug("%d mipi csi2 err1 %x\n", j, mipi_reg_test[j]);
++ }
++ return 0;
++}
++
++static int tc358743_init_mode(struct tc_data *td,
++ enum tc358743_frame_rate frame_rate,
++ enum tc358743_mode mode)
++{
++ struct sensor_data *sensor = &td->sensor;
++ int retval = 0;
++ void *mipi_csi2_info;
++
++ pr_debug("%s rate: %d mode: %d\n", __func__, frame_rate, mode);
++ if ((mode >= tc358743_mode_MAX || mode < 0)
++ && (mode != tc358743_mode_INIT)) {
++ pr_debug("%s Wrong tc358743 mode detected! %d. Set mode 0\n", __func__, mode);
++ mode = 0;
++ }
++ /* initial mipi dphy */
++ tc358743_toggle_hpd(sensor, 0);
++ tc358743_software_reset(sensor);
++
++ mipi_csi2_info = mipi_csi2_get_info();
++ pr_debug("%s rate: %d mode: %d, info %p\n", __func__, frame_rate, mode, mipi_csi2_info);
++
++ if (!mipi_csi2_info) {
++ pr_err("Fail to get mipi_csi2_info!\n");
++ return -1;
++ }
++ retval = mipi_reset(mipi_csi2_info, frame_rate, tc358743_mode_INIT);
++ if (retval)
++ return retval;
++ retval = set_frame_rate_mode(td, frame_rate, tc358743_mode_INIT);
++ if (retval)
++ return retval;
++ retval = mipi_wait(mipi_csi2_info);
++
++ if (mode != tc358743_mode_INIT) {
++ tc358743_software_reset(sensor);
++ retval = mipi_reset(mipi_csi2_info, frame_rate, mode);
++ if (retval)
++ return retval;
++ retval = set_frame_rate_mode(td, frame_rate, mode);
++ if (retval)
++ return retval;
++ retval = mipi_wait(mipi_csi2_info);
++ }
++ if (td->hpd_active)
++ tc358743_toggle_hpd(sensor, td->hpd_active);
++ return retval;
++}
++
++static int tc358743_minit(struct tc_data *td)
++{
++ struct sensor_data *sensor = &td->sensor;
++ int ret;
++ enum tc358743_frame_rate frame_rate = tc358743_60_fps;
++ u32 tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 60)
++ frame_rate = tc358743_60_fps;
++ else if (tgt_fps == 30)
++ frame_rate = tc358743_30_fps;
++
++ pr_debug("%s: capture mode: %d fps: %d\n", __func__,
++ sensor->streamcap.capturemode, tgt_fps);
++
++ ret = tc358743_init_mode(td, frame_rate, sensor->streamcap.capturemode);
++ if (ret)
++ pr_err("%s: Fail to init tc35874!\n", __func__);
++ return ret;
++}
++
++static int tc358743_reset(struct tc_data *td)
++{
++ int loop = 0;
++ int ret;
++
++ det_work_enable(td, 0);
++ for (;;) {
++ pr_debug("%s: RESET\n", __func__);
++ power_control(td, 0);
++ mdelay(100);
++ power_control(td, 1);
++ mdelay(1000);
++
++ ret = tc358743_minit(td);
++ if (!ret)
++ break;
++ if (loop++ >= 3) {
++ pr_err("%s:failed(%d)\n", __func__, ret);
++ break;
++ }
++ }
++ det_work_enable(td, 1);
++ return ret;
++}
++
++/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
++
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ struct tc_data *td = s->priv;
++ struct sensor_data *sensor = &td->sensor;
++
++ pr_debug("%s\n", __func__);
++
++ memset(p, 0, sizeof(*p));
++ p->u.bt656.clock_curr = TC358743_XCLK_MIN; //sensor->mclk;
++ pr_debug("%s: clock_curr=mclk=%d\n", __func__, sensor->mclk);
++ p->if_type = V4L2_IF_TYPE_BT656;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_min = TC358743_XCLK_MIN;
++ p->u.bt656.clock_max = TC358743_XCLK_MAX;
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct tc_data *td = s->priv;
++ int ret;
++
++ mutex_lock(&td->access_lock);
++ if (on && !td->mode) {
++ ret = tc358743_reset(td);
++ } else {
++ ret = power_control(td, on);
++ }
++ mutex_unlock(&td->access_lock);
++ return ret;
++}
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct tc_data *td = s->priv;
++ struct sensor_data *sensor = &td->sensor;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ pr_debug("%s type: %x\n", __func__, a->type);
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ cparm->extendedmode = sensor->streamcap.extendedmode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++ pr_debug("%s done %d\n", __func__, ret);
++ return ret;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct tc_data *td = s->priv;
++ struct sensor_data *sensor = &td->sensor;
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps; /* target frames per secound */
++ enum tc358743_frame_rate frame_rate = tc358743_60_fps, frame_rate_now = tc358743_60_fps;
++ enum tc358743_mode mode;
++ int ret = 0;
++
++ pr_debug("%s\n", __func__);
++ mutex_lock(&td->access_lock);
++ det_work_enable(td, 0);
++ /* Make sure power on */
++ power_control(td, 1);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 60)
++ frame_rate = tc358743_60_fps;
++ else if (tgt_fps == 30)
++ frame_rate = tc358743_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ ret = -EINVAL;
++ break;
++ }
++
++ if ((u32)a->parm.capture.capturemode >= tc358743_mode_MAX) {
++ a->parm.capture.capturemode = 0;
++ pr_debug("%s: Force mode: %d \n", __func__,
++ (u32)a->parm.capture.capturemode);
++ }
++
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 60)
++ frame_rate_now = tc358743_60_fps;
++ else if (tgt_fps == 30)
++ frame_rate_now = tc358743_30_fps;
++
++ mode = td->mode;
++ if (IS_COLORBAR(mode)) {
++ mode = (u32)a->parm.capture.capturemode;
++ } else {
++ a->parm.capture.capturemode = mode;
++ frame_rate = td->fps;
++ timeperframe->denominator = (frame_rate == tc358743_60_fps) ? 60 : 30;
++ timeperframe->numerator = 1;
++ }
++
++ if (frame_rate_now != frame_rate ||
++ sensor->streamcap.capturemode != mode ||
++ sensor->streamcap.extendedmode != (u32)a->parm.capture.extendedmode) {
++
++ if (mode != tc358743_mode_INIT) {
++ sensor->streamcap.capturemode = mode;
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.extendedmode =
++ (u32)a->parm.capture.extendedmode;
++ pr_debug("%s: capture mode: %d\n", __func__,
++ mode);
++ ret = tc358743_init_mode(td, frame_rate, mode);
++ } else {
++ a->parm.capture.capturemode = sensor->streamcap.capturemode;
++ *timeperframe = sensor->streamcap.timeperframe;
++ a->parm.capture.extendedmode = sensor->streamcap.extendedmode;
++ }
++ } else {
++ pr_debug("%s: Keep current settings\n", __func__);
++ }
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ det_work_enable(td, 1);
++ mutex_unlock(&td->access_lock);
++ return ret;
++}
++
++/*!
++ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
++ *
++ * If the requested control is supported, returns the control's current
++ * value from the video_control[] array. Otherwise, returns -EINVAL
++ * if the control is not supported.
++ */
++static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ struct tc_data *td = s->priv;
++ struct sensor_data *sensor = &td->sensor;
++ int ret = 0;
++
++ pr_debug("%s\n", __func__);
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ vc->value = sensor->brightness;
++ break;
++ case V4L2_CID_HUE:
++ vc->value = sensor->hue;
++ break;
++ case V4L2_CID_CONTRAST:
++ vc->value = sensor->contrast;
++ break;
++ case V4L2_CID_SATURATION:
++ vc->value = sensor->saturation;
++ break;
++ case V4L2_CID_RED_BALANCE:
++ vc->value = sensor->red;
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ vc->value = sensor->blue;
++ break;
++ case V4L2_CID_EXPOSURE:
++ vc->value = sensor->ae_mode;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++/*!
++ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
++ *
++ * If the requested control is supported, sets the control's current
++ * value in HW (and updates the video_control[] array). Otherwise,
++ * returns -EINVAL if the control is not supported.
++ */
++static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
++{
++ int retval = 0;
++
++ pr_debug("In tc358743:ioctl_s_ctrl %d\n",
++ vc->id);
++
++ switch (vc->id) {
++ case V4L2_CID_BRIGHTNESS:
++ break;
++ case V4L2_CID_CONTRAST:
++ break;
++ case V4L2_CID_SATURATION:
++ break;
++ case V4L2_CID_HUE:
++ break;
++ case V4L2_CID_AUTO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_DO_WHITE_BALANCE:
++ break;
++ case V4L2_CID_RED_BALANCE:
++ break;
++ case V4L2_CID_BLUE_BALANCE:
++ break;
++ case V4L2_CID_GAMMA:
++ break;
++ case V4L2_CID_EXPOSURE:
++ break;
++ case V4L2_CID_AUTOGAIN:
++ break;
++ case V4L2_CID_GAIN:
++ break;
++ case V4L2_CID_HFLIP:
++ break;
++ case V4L2_CID_VFLIP:
++ break;
++ default:
++ retval = -EPERM;
++ break;
++ }
++
++ return retval;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ struct tc_data *td = s->priv;
++ enum tc358743_mode query_mode= fsize->index;
++ enum tc358743_mode mode = td->mode;
++
++ if (IS_COLORBAR(mode)) {
++ if (query_mode > MAX_COLORBAR)
++ return -EINVAL;
++ mode = query_mode;
++ } else {
++ if (query_mode)
++ return -EINVAL;
++ }
++ pr_debug("%s, mode: %d\n", __func__, mode);
++
++ fsize->pixel_format = get_pixelformat(0, mode);
++ fsize->discrete.width =
++ tc358743_mode_info_data[0][mode].width;
++ fsize->discrete.height =
++ tc358743_mode_info_data[0][mode].height;
++ pr_debug("%s %d:%d format: %x\n", __func__, fsize->discrete.width, fsize->discrete.height, fsize->pixel_format);
++ return 0;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "tc358743_mipi");
++
++ return 0;
++}
++
++/*!
++ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
++ * @s: pointer to standard V4L2 device structure
++ */
++static int ioctl_init(struct v4l2_int_device *s)
++{
++ pr_debug("%s\n", __func__);
++ return 0;
++}
++
++/*!
++ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
++ * @s: pointer to standard V4L2 device structure
++ * @fmt: pointer to standard V4L2 fmt description structure
++ *
++ * Return 0.
++ */
++static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_fmtdesc *fmt)
++{
++ struct tc_data *td = s->priv;
++ struct sensor_data *sensor = &td->sensor;
++ int index = fmt->index;
++
++ if (!index)
++ index = sensor->streamcap.capturemode;
++ pr_debug("%s, INDEX: %d\n", __func__, index);
++ if (index >= tc358743_mode_MAX)
++ return -EINVAL;
++
++ fmt->pixelformat = get_pixelformat(0, index);
++
++ pr_debug("%s: format: %x\n", __func__, fmt->pixelformat);
++ return 0;
++}
++
++static int ioctl_try_fmt_cap(struct v4l2_int_device *s,
++ struct v4l2_format *f)
++{
++ struct tc_data *td = s->priv;
++ struct sensor_data *sensor = &td->sensor;
++ u32 tgt_fps; /* target frames per secound */
++ enum tc358743_frame_rate frame_rate;
++// enum image_size isize;
++ int ret = 0;
++ struct v4l2_pix_format *pix = &f->fmt.pix;
++ int mode;
++
++ pr_debug("%s\n", __func__);
++
++ mutex_lock(&td->access_lock);
++ tgt_fps = sensor->streamcap.timeperframe.denominator /
++ sensor->streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 60) {
++ frame_rate = tc358743_60_fps;
++ } else if (tgt_fps == 30) {
++ frame_rate = tc358743_30_fps;
++ } else {
++ pr_debug("%s: %d fps (%d,%d) is not supported\n", __func__, tgt_fps, sensor->streamcap.timeperframe.denominator,sensor->streamcap.timeperframe.numerator);
++ ret = -EINVAL;
++ goto out;
++ }
++ mode = sensor->streamcap.capturemode;
++ sensor->pix.pixelformat = get_pixelformat(frame_rate, mode);
++ sensor->pix.width = pix->width = tc358743_mode_info_data[frame_rate][mode].width;
++ sensor->pix.height = pix->height = tc358743_mode_info_data[frame_rate][mode].height;
++ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height);
++
++ pix->pixelformat = sensor->pix.pixelformat;
++ pix->field = V4L2_FIELD_NONE;
++ pix->bytesperline = pix->width * 4;
++ pix->sizeimage = pix->bytesperline * pix->height;
++ pix->priv = 0;
++
++ switch (pix->pixelformat) {
++ case V4L2_PIX_FMT_UYVY:
++ default:
++ pix->colorspace = V4L2_COLORSPACE_SRGB;
++ break;
++ }
++
++ {
++ pr_debug("SYS_STATUS: 0x%x\n", tc358743_read_reg_val(sensor, 0x8520));
++ pr_debug("VI_STATUS0: 0x%x\n", tc358743_read_reg_val(sensor, 0x8521));
++ pr_debug("VI_STATUS1: 0x%x\n", tc358743_read_reg_val(sensor, 0x8522));
++ pr_debug("VI_STATUS2: 0x%x\n", tc358743_read_reg_val(sensor, 0x8525));
++ pr_debug("VI_STATUS3: 0x%x\n", tc358743_read_reg_val(sensor, 0x8528));
++ pr_debug("%s %d:%d format: %x\n", __func__, pix->width, pix->height, pix->pixelformat);
++ }
++out:
++ mutex_unlock(&td->access_lock);
++ return ret;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct tc_data *td = s->priv;
++ struct sensor_data *sensor = &td->sensor;
++ int mode = sensor->streamcap.capturemode;
++
++ sensor->pix.pixelformat = get_pixelformat(0, mode);
++ sensor->pix.width = tc358743_mode_info_data[0][mode].width;
++ sensor->pix.height = tc358743_mode_info_data[0][mode].height;
++
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ f->fmt.pix = sensor->pix;
++ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height);
++ break;
++
++ case V4L2_BUF_TYPE_SENSOR:
++ pr_debug("%s: left=%d, top=%d, %dx%d\n", __func__,
++ sensor->spix.left, sensor->spix.top,
++ sensor->spix.swidth, sensor->spix.sheight);
++ f->fmt.spix = sensor->spix;
++ break;
++
++ case V4L2_BUF_TYPE_PRIVATE:
++ pr_debug("%s: private\n", __func__);
++ break;
++
++ default:
++ f->fmt.pix = sensor->pix;
++ pr_debug("%s: type=%d, %dx%d\n", __func__, f->type, sensor->pix.width, sensor->pix.height);
++ break;
++ }
++ return 0;
++}
++
++/*!
++ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Initialise the device when slave attaches to the master.
++ */
++static int ioctl_dev_init(struct v4l2_int_device *s)
++{
++ struct tc_data *td = s->priv;
++
++ if (td->det_changed) {
++ mutex_lock(&td->access_lock);
++ td->det_changed = 0;
++ pr_debug("%s\n", __func__);
++ tc358743_minit(td);
++ mutex_unlock(&td->access_lock);
++ }
++ pr_debug("%s\n", __func__);
++ return 0;
++}
++
++/*!
++ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
++ * @s: pointer to standard V4L2 device structure
++ *
++ * Delinitialise the device when slave detaches to the master.
++ */
++static int ioctl_dev_exit(struct v4l2_int_device *s)
++{
++ void *mipi_csi2_info;
++
++ mipi_csi2_info = mipi_csi2_get_info();
++
++ /* disable mipi csi2 */
++ if (mipi_csi2_info)
++ if (mipi_csi2_get_status(mipi_csi2_info))
++ mipi_csi2_disable(mipi_csi2_info);
++
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module and links them to the
++ * enumeration.
++ */
++static struct v4l2_int_ioctl_desc tc358743_ioctl_desc[] = {
++ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init},
++ {vidioc_int_dev_exit_num, ioctl_dev_exit},
++ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power},
++ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm},
++ {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init},
++ {vidioc_int_enum_fmt_cap_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap},
++ {vidioc_int_try_fmt_cap_num,
++ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap},
++ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
++ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
++ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
++ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl},
++ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
++ {vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
++ {vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *) ioctl_g_chip_ident},
++};
++
++static struct v4l2_int_slave tc358743_slave = {
++ .ioctls = tc358743_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(tc358743_ioctl_desc),
++};
++
++static struct v4l2_int_device tc358743_int_device = {
++ .module = THIS_MODULE,
++ .name = "tc358743",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &tc358743_slave,
++ },
++};
++
++
++#ifdef CONFIG_TC358743_AUDIO
++struct imx_ssi {
++ struct platform_device *ac97_dev;
++
++ struct snd_soc_dai *imx_ac97;
++ struct clk *clk;
++ void __iomem *base;
++ int irq;
++ int fiq_enable;
++ unsigned int offset;
++
++ unsigned int flags;
++
++ void (*ac97_reset) (struct snd_ac97 *ac97);
++ void (*ac97_warm_reset)(struct snd_ac97 *ac97);
++
++ struct imx_pcm_dma_params dma_params_rx;
++ struct imx_pcm_dma_params dma_params_tx;
++
++ int enabled;
++
++ struct platform_device *soc_platform_pdev;
++ struct platform_device *soc_platform_pdev_fiq;
++};
++#define SSI_SCR 0x10
++#define SSI_SRCR 0x20
++#define SSI_STCCR 0x24
++#define SSI_SRCCR 0x28
++#define SSI_SCR_I2S_MODE_NORM (0 << 5)
++#define SSI_SCR_I2S_MODE_MSTR (1 << 5)
++#define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
++#define SSI_I2S_MODE_MASK (3 << 5)
++#define SSI_SCR_SYN (1 << 4)
++#define SSI_SRCR_RSHFD (1 << 4)
++#define SSI_SRCR_RSCKP (1 << 3)
++#define SSI_SRCR_RFSI (1 << 2)
++#define SSI_SRCR_REFS (1 << 0)
++#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
++#define SSI_STCCR_WL_MASK (0xf << 13)
++#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
++#define SSI_SRCCR_WL_MASK (0xf << 13)
++/* Audio setup */
++
++static int imxpac_tc358743_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ int ret;
++
++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
++ SND_SOC_DAIFMT_NB_IF |
++ SND_SOC_DAIFMT_CBM_CFM);
++ if (ret) {
++ pr_err("%s: failed set cpu dai format\n", __func__);
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
++ SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM);
++ if (ret) {
++ pr_err("%s: failed set codec dai format\n", __func__);
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_sysclk(codec_dai, 0,
++ CODEC_CLOCK, SND_SOC_CLOCK_OUT);
++ if (ret) {
++ pr_err("%s: failed setting codec sysclk\n", __func__);
++ return ret;
++ }
++ snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0);
++
++ ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
++ SND_SOC_CLOCK_IN);
++ if (ret) {
++ pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n");
++ return ret;
++ }
++#if 1
++// clear SSI_SRCR_RXBIT0 and SSI_SRCR_RSHFD in order to push Right-justified MSB data fro
++ {
++ struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 scr = 0, srcr = 0, stccr = 0, srccr = 0;
++
++ pr_debug("%s: base %p\n", __func__, (void *)ssi->base);
++ scr = readl(ssi->base + SSI_SCR);
++ pr_debug("%s: SSI_SCR before: %p\n", __func__, (void *)scr);
++ writel(scr, ssi->base + SSI_SCR);
++ pr_debug("%s: SSI_SCR after: %p\n", __func__, (void *)scr);
++
++ srcr = readl(ssi->base + SSI_SRCR);
++ pr_debug("%s: SSI_SRCR before: %p\n", __func__, (void *)srcr);
++ writel(srcr, ssi->base + SSI_SRCR);
++ pr_debug("%s: SSI_SRCR after: %p\n", __func__, (void *)srcr);
++
++ stccr = readl(ssi->base + SSI_STCCR);
++ pr_debug("%s: SSI_STCCR before: %p\n", __func__, (void *)stccr);
++ stccr &= ~SSI_STCCR_WL_MASK;
++ stccr |= SSI_STCCR_WL(16);
++ writel(stccr, ssi->base + SSI_STCCR);
++ pr_debug("%s: SSI_STCCR after: %p\n", __func__, (void *)stccr);
++
++ srccr = readl(ssi->base + SSI_SRCCR);
++ pr_debug("%s: SSI_SRCCR before: %p\n", __func__, (void *)srccr);
++ srccr &= ~SSI_SRCCR_WL_MASK;
++ srccr |= SSI_SRCCR_WL(16);
++ writel(srccr, ssi->base + SSI_SRCCR);
++ pr_debug("%s: SSI_SRCCR after: %p\n", __func__, (void *)srccr);
++ }
++#endif
++ return 0;
++}
++
++
++
++/* imx_3stack card dapm widgets */
++static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets_a[] = {
++};
++
++
++
++static const struct snd_kcontrol_new tc358743_machine_controls_a[] = {
++};
++
++/* imx_3stack machine connections to the codec pins */
++static const struct snd_soc_dapm_route audio_map_a[] = {
++};
++
++static int imx_3stack_tc358743_init(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_soc_codec *codec = rtd->codec;
++ int ret;
++
++ const struct snd_soc_dapm_widget *imx_3stack_dapm_widgets;
++ int imx_3stack_dapm_widgets_size;
++ const struct snd_kcontrol_new *tc358743_machine_controls;
++ int tc358743_machine_controls_size;
++ const struct snd_soc_dapm_route *audio_map;
++ int audio_map_size;
++ int gpio_num = -1;
++ char *gpio_name;
++
++ pr_debug("%s started\n", __func__);
++
++ imx_3stack_dapm_widgets = imx_3stack_dapm_widgets_a;
++ imx_3stack_dapm_widgets_size = ARRAY_SIZE(imx_3stack_dapm_widgets_a);
++ tc358743_machine_controls = tc358743_machine_controls_a;
++ tc358743_machine_controls_size = ARRAY_SIZE(tc358743_machine_controls_a);
++ audio_map = audio_map_a;
++ audio_map_size = ARRAY_SIZE(audio_map_a);
++ gpio_num = -1; //card_a_gpio_num;
++ gpio_name = NULL;
++
++ ret = snd_soc_add_controls(codec, tc358743_machine_controls,
++ tc358743_machine_controls_size);
++ if (ret) {
++ pr_err("%s: snd_soc_add_controls failed. err = %d\n", __func__, ret);
++ return ret;
++ }
++ /* Add imx_3stack specific widgets */
++ snd_soc_dapm_new_controls(&codec->dapm, imx_3stack_dapm_widgets,
++ imx_3stack_dapm_widgets_size);
++
++ /* Set up imx_3stack specific audio path audio_map */
++ snd_soc_dapm_add_routes(&codec->dapm, audio_map, audio_map_size);
++ snd_soc_dapm_sync(&codec->dapm);
++ return 0;
++}
++
++
++static struct snd_soc_ops imxpac_tc358743_snd_ops = {
++ .hw_params = imxpac_tc358743_hw_params,
++};
++
++static struct snd_soc_dai_link imxpac_tc358743_dai = {
++ .name = "tc358743",
++ .stream_name = "TC358743",
++ .codec_dai_name = "tc358743-hifi",
++ .platform_name = "imx-pcm-audio.2",
++ .codec_name = "tc358743_mipi.1-000f",
++ .cpu_dai_name = "imx-ssi.2",
++ .init = imx_3stack_tc358743_init,
++ .ops = &imxpac_tc358743_snd_ops,
++};
++
++static struct snd_soc_card imxpac_tc358743 = {
++ .name = "cpuimx-audio_hdmi_in",
++ .dai_link = &imxpac_tc358743_dai,
++ .num_links = 1,
++};
++
++static int imx_audmux_config(int slave, int master)
++{
++ unsigned int ptcr, pdcr;
++ slave = slave - 1;
++ master = master - 1;
++
++ /* SSI0 mastered by port 5 */
++ ptcr = MXC_AUDMUX_V2_PTCR_SYN |
++ MXC_AUDMUX_V2_PTCR_TFSDIR |
++ MXC_AUDMUX_V2_PTCR_TFSEL(master | 0x8) |
++ MXC_AUDMUX_V2_PTCR_TCLKDIR |
++ MXC_AUDMUX_V2_PTCR_RFSDIR |
++ MXC_AUDMUX_V2_PTCR_RFSEL(master | 0x8) |
++ MXC_AUDMUX_V2_PTCR_RCLKDIR |
++ MXC_AUDMUX_V2_PTCR_RCSEL(master | 0x8) |
++ MXC_AUDMUX_V2_PTCR_TCSEL(master | 0x8);
++ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
++ mxc_audmux_v2_configure_port(slave, ptcr, pdcr);
++
++ ptcr = MXC_AUDMUX_V2_PTCR_SYN;
++ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
++ mxc_audmux_v2_configure_port(master, ptcr, pdcr);
++ return 0;
++}
++
++static int __devinit imx_tc358743_probe(struct platform_device *pdev)
++{
++ struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
++ int ret = 0;
++
++
++ imx_audmux_config(plat->src_port, plat->ext_port);
++
++ ret = -EINVAL;
++ if (plat->init && plat->init())
++ return ret;
++
++ printk("%s %d %s\n",__func__,__LINE__,pdev->name);
++ return 0;
++}
++
++static int imx_tc358743_remove(struct platform_device *pdev)
++{
++ struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
++
++ if (plat->finit)
++ plat->finit();
++
++ return 0;
++}
++
++static struct platform_driver imx_tc358743_audio1_driver = {
++ .probe = imx_tc358743_probe,
++ .remove = imx_tc358743_remove,
++ .driver = {
++ .name = "imx-tc358743",
++ },
++};
++
++
++/* Codec setup */
++static int tc358743_codec_probe(struct snd_soc_codec *codec)
++{
++ return 0;
++}
++
++static int tc358743_codec_remove(struct snd_soc_codec *codec)
++{
++ return 0;
++}
++
++static int tc358743_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
++{
++// tc358743_set_bias_level(codec, SND_SOC_BIAS_OFF);
++ return 0;
++}
++
++static int tc358743_codec_resume(struct snd_soc_codec *codec)
++{
++// tc358743_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++ return 0;
++}
++
++static int tc358743_set_bias_level(struct snd_soc_codec *codec,
++ enum snd_soc_bias_level level)
++{
++ return 0;
++}
++
++static const u8 tc358743_reg[0] = {
++};
++
++static struct snd_soc_codec_driver soc_codec_dev_tc358743 = {
++ .set_bias_level = tc358743_set_bias_level,
++ .reg_cache_size = ARRAY_SIZE(tc358743_reg),
++ .reg_word_size = sizeof(u8),
++ .reg_cache_default = tc358743_reg,
++ .probe = tc358743_codec_probe,
++ .remove = tc358743_codec_remove,
++ .suspend = tc358743_codec_suspend,
++ .resume = tc358743_codec_resume,
++};
++
++#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
++#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE)
++
++static int tc358743_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ return 0;
++}
++
++static int tc358743_mute(struct snd_soc_dai *dai, int mute)
++{
++ return 0;
++}
++
++static int tc358743_set_dai_sysclk(struct snd_soc_dai *codec_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ return 0;
++}
++
++static int tc358743_set_dai_fmt(struct snd_soc_dai *codec_dai,
++ unsigned int fmt)
++{
++ return 0;
++}
++
++static struct snd_soc_dai_ops tc358743_dai_ops = {
++ .hw_params = tc358743_hw_params,
++ .digital_mute = tc358743_mute,
++ .set_sysclk = tc358743_set_dai_sysclk,
++ .set_fmt = tc358743_set_dai_fmt,
++};
++
++static struct snd_soc_dai_driver tc358743_dai = {
++ .name = "tc358743-hifi",
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = AIC3X_RATES,
++ .formats = AIC3X_FORMATS,},
++ .ops = &tc358743_dai_ops,
++ .symmetric_rates = 1,
++};
++
++#endif
++
++struct tc_mode_list {
++ const char *name;
++ enum tc358743_mode mode;
++};
++
++static const struct tc_mode_list tc358743_mode_list[] =
++{
++ {"None", 0}, /* 0 */
++ {"VGA", tc358743_mode_480P_640_480}, /* 1 */
++ {"240p/480i", 0}, /* 2 */
++ {"288p/576i", 0}, /* 3 */
++ {"W240p/480i", 0}, /* 4 */
++ {"W288p/576i", 0}, /* 5 */
++ {"480p", 0}, /* 6 */
++ {"576p", 0}, /* 7 */
++ {"W480p", tc358743_mode_480P_720_480}, /* 8 */
++ {"W576p", 0}, /* 9 */
++ {"WW480p", 0}, /* 10 */
++ {"WW576p", 0}, /* 11 */
++ {"720p", tc358743_mode_720P_60_1280_720}, /* 12 */
++ {"1035i", 0}, /* 13 */
++ {"1080i", 0}, /* 14 */
++ {"1080p", tc358743_mode_1080P_1920_1080}, /* 15 */
++};
++
++static char tc358743_fps_list[tc358743_max_fps+1] =
++{
++[tc358743_60_fps] = 60,
++[tc358743_30_fps] = 30,
++[tc358743_max_fps] = 0
++};
++
++static int tc358743_audio_list[16] =
++{
++ 44100,
++ 0,
++ 48000,
++ 32000,
++ 22050,
++ 384000,
++ 24000,
++ 352800,
++ 88200,
++ 768000,
++ 96000,
++ 705600,
++ 176400,
++ 0,
++ 192000,
++ 0
++};
++
++static char str_on[80];
++static void report_netlink(struct tc_data *td)
++{
++ struct sensor_data *sensor = &td->sensor;
++ char *envp[2];
++ envp[0] = &str_on[0];
++ envp[1] = NULL;
++ sprintf(envp[0], "HDMI RX: %d (%s) %d %d",
++ td->mode,
++ tc358743_mode_info_data[td->fps][td->mode].name,
++ tc358743_fps_list[td->fps], tc358743_audio_list[td->audio]);
++ kobject_uevent_env(&(sensor->i2c_client->dev.kobj), KOBJ_CHANGE, envp);
++ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
++ pr_debug("%s: HDMI RX (%d) mode: %s fps: %d (%d, %d) audio: %d\n",
++ __func__, td->mode,
++ tc358743_mode_info_data[td->fps][td->mode].name, td->fps, td->bounce,
++ td->det_work_timeout, tc358743_audio_list[td->audio]);
++}
++
++static void tc_det_worker(struct work_struct *work)
++{
++ struct tc_data *td = container_of(work, struct tc_data, det_work.work);
++ struct sensor_data *sensor = &td->sensor;
++ int ret;
++ u32 u32val, u852f;
++ enum tc358743_mode mode = tc358743_mode_INIT;
++
++
++ if (!td->det_work_enable)
++ return;
++ mutex_lock(&td->access_lock);
++
++ if (!td->det_work_enable) {
++ goto out2;
++ }
++ u32val = 0;
++ ret = tc358743_read_reg(sensor, 0x8621, &u32val);
++ if (ret >= 0) {
++ if (td->audio != (((unsigned char)u32val) & 0x0f)) {
++ td->audio = ((unsigned char)u32val) & 0x0f;
++ report_netlink(td);
++ }
++ }
++ u852f = 0;
++ ret = tc358743_read_reg(sensor, 0x852f, &u852f);
++ if (ret < 0) {
++ pr_err("%s: Error reading lock\n", __func__);
++ td->det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
++ goto out;
++ }
++// pr_info("%s: 852f=%x\n", __func__, u32val);
++ if (u852f & TC3587430_HDMI_DETECT) {
++ pr_info("%s: hdmi detect %x\n", __func__, u852f);
++ td->lock = u852f & TC3587430_HDMI_DETECT;
++ u32val = 0;
++ ret = tc358743_read_reg(sensor, 0x8521, &u32val);
++ if (ret < 0) {
++ pr_err("%s: Error reading mode\n", __func__);
++ }
++ pr_info("%s: detect 8521=%x\n", __func__, u32val);
++ u32val &= 0x0f;
++ td->fps = tc358743_60_fps;
++ if (!u32val) {
++ int hsize, vsize;
++
++ hsize = tc358743_read_reg_val16(sensor, 0x8582);
++ vsize = tc358743_read_reg_val16(sensor, 0x8588);
++ pr_info("%s: detect hsize=%d, vsize=%d\n", __func__, hsize, vsize);
++ if ((hsize == 1024) && (vsize == 768))
++ mode = tc358743_mode_1024x768;
++ } else {
++ mode = tc358743_mode_list[u32val].mode;
++ if (td->mode != mode)
++ pr_debug("%s: %s detected\n", __func__, tc358743_mode_list[u32val].name);
++ if (u852f >= 0xe)
++ td->fps = ((u852f & 0x0f) > 0xa)? tc358743_60_fps: tc358743_30_fps;
++ }
++ } else {
++ if (td->lock)
++ td->lock = 0;
++ u32val = 0;
++ ret = tc358743_read_reg(sensor, 0x8521, &u32val);
++ if (ret < 0) {
++ pr_err("%s: Error reading mode\n", __func__);
++ }
++// pr_info("%s: 8521=%x\n", __func__, u32val);
++ }
++ if (td->mode != mode) {
++ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
++ td->bounce = MAX_BOUNCE;
++ pr_debug("%s: HDMI RX (%d != %d) mode: %s fps: %d (%d, %d)\n",
++ __func__, td->mode, mode,
++ tc358743_mode_info_data[td->fps][mode].name,
++ td->fps, td->bounce, td->det_work_timeout);
++ td->mode = mode;
++ sensor->streamcap.capturemode = mode;
++ sensor->spix.swidth = tc358743_mode_info_data[td->fps][mode].width;
++ sensor->spix.sheight = tc358743_mode_info_data[td->fps][mode].height;
++ td->det_changed = 1;
++ } else if (td->bounce) {
++ td->bounce--;
++ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
++
++ if (!td->bounce) {
++ u32val = 0;
++ ret = tc358743_read_reg(sensor, 0x8621, &u32val);
++ if (ret >= 0) {
++ td->audio = ((unsigned char)u32val) & 0x0f;
++ report_netlink(td);
++ }
++ if (td->mode) {
++ td->det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
++ goto out2;
++ }
++ }
++ } else if (td->mode && !td->bounce) {
++ goto out2;
++ }
++out:
++ schedule_delayed_work(&td->det_work, msecs_to_jiffies(td->det_work_timeout));
++out2:
++ mutex_unlock(&td->access_lock);
++}
++
++static irqreturn_t tc358743_detect_handler(int irq, void *data)
++{
++ struct tc_data *td = data;
++ struct sensor_data *sensor = &td->sensor;
++
++ pr_debug("%s: IRQ %d\n", __func__, sensor->i2c_client->irq);
++ schedule_delayed_work(&td->det_work, msecs_to_jiffies(10));
++ return IRQ_HANDLED;
++}
++
++
++/*!
++ * tc358743 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++#define DUMP_LENGTH 256
++static u16 regoffs = 0;
++
++static ssize_t tc358743_show_regdump(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct tc_data *td = g_td;
++ struct sensor_data *sensor = &td->sensor;
++ int i, len = 0;
++ int retval;
++
++ if (!td)
++ return len;
++ mutex_lock(&td->access_lock);
++ for (i=0; i<DUMP_LENGTH; ) {
++ u32 u32val = 0;
++ int reg = regoffs+i;
++ int size = get_reg_size(reg, 0);
++
++ retval = tc358743_read_reg(sensor, reg, &u32val);
++ if (retval < 0) {
++ u32val = 0xff;
++ retval = 1;
++ }
++ if (!(i & 0xf))
++ len += sprintf(buf+len, "\n%04X:", reg);
++ if (size == 1)
++ len += sprintf(buf+len, " %02X", u32val&0xff);
++ else if (size == 2)
++ len += sprintf(buf+len, " %04X", u32val&0xffff);
++ else
++ len += sprintf(buf+len, " %08X", u32val);
++ i += size;
++ }
++ mutex_unlock(&td->access_lock);
++ len += sprintf(buf+len, "\n");
++ return len;
++}
++
++static DEVICE_ATTR(regdump, S_IRUGO, tc358743_show_regdump, NULL);
++
++static ssize_t tc358743_store_regoffs(struct device *device,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ u32 val;
++ int retval;
++ retval = sscanf(buf, "%x", &val);
++ if (1 == retval)
++ regoffs = (u16)val;
++ return count;
++}
++
++static ssize_t tc358743_show_regoffs(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int len = 0;
++
++ len += sprintf(buf+len, "0x%04X\n", regoffs);
++ return len;
++}
++
++static DEVICE_ATTR(regoffs, S_IRUGO|S_IWUSR, tc358743_show_regoffs, tc358743_store_regoffs);
++
++static ssize_t tc358743_store_hpd(struct device *device,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct tc_data *td = g_td;
++ u32 val;
++ int retval;
++ retval = sscanf(buf, "%d", &val);
++ if (1 == retval)
++ td->hpd_active = (u16)val;
++ return count;
++}
++
++static ssize_t tc358743_show_hpd(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct tc_data *td = g_td;
++ int len = 0;
++
++ len += sprintf(buf+len, "%d\n", td->hpd_active);
++ return len;
++}
++
++static DEVICE_ATTR(hpd, S_IRUGO|S_IWUSR, tc358743_show_hpd, tc358743_store_hpd);
++
++static ssize_t tc358743_show_hdmirx(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct tc_data *td = g_td;
++ int len = 0;
++
++ len += sprintf(buf+len, "%d\n", td->mode);
++ return len;
++}
++
++static DEVICE_ATTR(hdmirx, S_IRUGO, tc358743_show_hdmirx, NULL);
++
++static ssize_t tc358743_show_fps(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct tc_data *td = g_td;
++ int len = 0;
++
++ len += sprintf(buf+len, "%d\n", tc358743_fps_list[td->fps]);
++ return len;
++}
++
++static DEVICE_ATTR(fps, S_IRUGO, tc358743_show_fps, NULL);
++
++#ifdef CONFIG_TC358743_AUDIO
++static ssize_t tc358743_show_audio(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct tc_data *td = g_td;
++ int len = 0;
++
++ len += sprintf(buf+len, "%d\n", tc358743_audio_list[td->audio]);
++ return len;
++}
++
++static DEVICE_ATTR(audio, S_IRUGO, tc358743_show_audio, NULL);
++#endif
++
++static int tc358743_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct device *dev = &client->dev;
++ int retval;
++ struct tc_data *td;
++ struct sensor_data *sensor;
++ u8 chip_id_high;
++ u32 u32val;
++ int mode = tc358743_mode_INIT;
++
++ td = kzalloc(sizeof(*td), GFP_KERNEL);
++ if (!td)
++ return -ENOMEM;
++ td->hpd_active = 1;
++ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
++ td->audio = 2;
++ mutex_init(&td->access_lock);
++ mutex_lock(&td->access_lock);
++ sensor = &td->sensor;
++
++ /* request power down pin */
++ td->pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(td->pwn_gpio)) {
++ dev_warn(dev, "no sensor pwdn pin available");
++ } else {
++ retval = devm_gpio_request_one(dev, td->pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "tc_mipi_pwdn");
++ if (retval < 0) {
++ dev_warn(dev, "request of pwn_gpio failed");
++ return retval;
++ }
++ }
++ /* request reset pin */
++ td->rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(td->rst_gpio)) {
++ dev_warn(dev, "no sensor reset pin available");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, td->rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "tc_mipi_reset");
++ if (retval < 0) {
++ dev_warn(dev, "request of tc_mipi_reset failed");
++ return retval;
++ }
++
++ /* Set initial values for the sensor struct. */
++ sensor->mipi_camera = 1;
++ sensor->virtual_channel = 0;
++ sensor->sensor_clk = devm_clk_get(dev, "csi_mclk");
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ &(sensor->mclk));
++ if (retval) {
++ dev_err(dev, "mclk missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(sensor->mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "ipu_id",
++ &sensor->ipu_id);
++ if (retval) {
++ dev_err(dev, "ipu_id missing or invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(sensor->csi));
++ if (retval) {
++ dev_err(dev, "csi id missing or invalid\n");
++ return retval;
++ }
++ if ((unsigned)sensor->ipu_id || (unsigned)sensor->csi) {
++ dev_err(dev, "invalid ipu/csi\n");
++ return -EINVAL;
++ }
++
++ if (!IS_ERR(sensor->sensor_clk))
++ clk_prepare_enable(sensor->sensor_clk);
++
++ sensor->io_init = tc_io_init;
++ sensor->i2c_client = client;
++ sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ sensor->streamcap.capturemode = mode;
++ sensor->streamcap.timeperframe.denominator = DEFAULT_FPS;
++ sensor->streamcap.timeperframe.numerator = 1;
++
++ sensor->pix.pixelformat = get_pixelformat(0, mode);
++ sensor->pix.width = tc358743_mode_info_data[0][mode].width;
++ sensor->pix.height = tc358743_mode_info_data[0][mode].height;
++ pr_debug("%s: format: %x, capture mode: %d fps: %d width: %d height: %d\n",
++ __func__, sensor->pix.pixelformat, mode,
++ sensor->streamcap.timeperframe.denominator *
++ sensor->streamcap.timeperframe.numerator,
++ sensor->pix.width,
++ sensor->pix.height);
++
++ tc_regulator_init(td, dev);
++ power_control(td, 1);
++ tc_reset(td);
++
++ u32val = 0;
++ retval = tc358743_read_reg(sensor, TC358743_CHIP_ID_HIGH_BYTE, &u32val);
++ if (retval < 0) {
++ pr_err("%s:cannot find camera\n", __func__);
++ retval = -ENODEV;
++ goto err4;
++ }
++ chip_id_high = (u8)u32val;
++
++ tc358743_int_device.priv = td;
++ if (!g_td)
++ g_td = td;
++
++#ifdef CONFIG_TC358743_AUDIO
++ retval = device_create_file(&client->dev, &dev_attr_audio);
++#endif
++ retval = device_create_file(&client->dev, &dev_attr_fps);
++ retval = device_create_file(&client->dev, &dev_attr_hdmirx);
++ retval = device_create_file(&client->dev, &dev_attr_hpd);
++ retval = device_create_file(&client->dev, &dev_attr_regoffs);
++ retval = device_create_file(&client->dev, &dev_attr_regdump);
++
++ if (retval) {
++ pr_err("%s: create bin file failed, error=%d\n",
++ __func__, retval);
++ goto err4;
++ }
++
++#ifdef CONFIG_TC358743_AUDIO
++/* Audio setup */
++ retval = snd_soc_register_codec(&client->dev,
++ &soc_codec_dev_tc358743, &tc358743_dai, 1);
++ if (retval) {
++ pr_err("%s: register failed, error=%d\n",
++ __func__, retval);
++ goto err4;
++ }
++
++ retval = platform_driver_register(&imx_tc358743_audio1_driver);
++ if (retval) {
++ pr_err("%s: Platform driver register failed, error=%d\n",
++ __func__, retval);
++ goto err4;
++ }
++
++ td->snd_device = platform_device_alloc("soc-audio", 5);
++ if (!td->snd_device) {
++ pr_err("%s: Platform device allocation failed, error=%d\n",
++ __func__, retval);
++ goto err4;
++ }
++
++ platform_set_drvdata(td->snd_device, &imxpac_tc358743);
++ retval = platform_device_add(td->snd_device);
++
++ if (retval) {
++ pr_err("%s: Platform device add failed, error=%d\n",
++ __func__, retval);
++ platform_device_put(td->snd_device);
++ goto err4;
++ }
++#endif
++
++#if 1
++ INIT_DELAYED_WORK(&td->det_work, tc_det_worker);
++ if (sensor->i2c_client->irq) {
++ retval = request_irq(sensor->i2c_client->irq, tc358743_detect_handler,
++ IRQF_SHARED | IRQF_TRIGGER_FALLING,
++ "tc358743_det", td);
++ if (retval < 0)
++ dev_warn(&sensor->i2c_client->dev,
++ "cound not request det irq %d\n",
++ sensor->i2c_client->irq);
++ }
++
++ schedule_delayed_work(&td->det_work, msecs_to_jiffies(td->det_work_timeout));
++#endif
++ retval = tc358743_reset(td);
++ if (retval)
++ goto err4;
++
++ i2c_set_clientdata(client, td);
++ mutex_unlock(&td->access_lock);
++ retval = v4l2_int_device_register(&tc358743_int_device);
++ mutex_lock(&td->access_lock);
++ if (retval) {
++ pr_err("%s: v4l2_int_device_register failed, error=%d\n",
++ __func__, retval);
++ goto err4;
++ }
++ power_control(td, 0);
++ mutex_unlock(&td->access_lock);
++ pr_debug("%s: finished, error=%d\n", __func__, retval);
++ return retval;
++
++err4:
++ power_control(td, 0);
++ mutex_unlock(&td->access_lock);
++ pr_err("%s: failed, error=%d\n", __func__, retval);
++ if (g_td == td)
++ g_td = NULL;
++ mutex_destroy(&td->access_lock);
++ kfree(td);
++ return retval;
++}
++
++/*!
++ * tc358743 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int tc358743_remove(struct i2c_client *client)
++{
++ int i;
++ struct tc_data *td = i2c_get_clientdata(client);
++ struct sensor_data *sensor = &td->sensor;
++
++ // Stop delayed work
++ cancel_delayed_work_sync(&td->det_work);
++ mutex_lock(&td->access_lock);
++
++ power_control(td, 0);
++ // Remove IRQ
++ if (sensor->i2c_client->irq) {
++ free_irq(sensor->i2c_client->irq, sensor);
++ }
++
++#ifdef CONFIG_TC358743_AUDIO
++/* Audio breakdown */
++ snd_soc_unregister_codec(&client->dev);
++ platform_driver_unregister(&imx_tc358743_audio1_driver);
++ platform_device_unregister(td->snd_device);
++#endif
++ /*Remove sysfs entries*/
++#ifdef CONFIG_TC358743_AUDIO
++ device_remove_file(&client->dev, &dev_attr_audio);
++#endif
++ device_remove_file(&client->dev, &dev_attr_fps);
++ device_remove_file(&client->dev, &dev_attr_hdmirx);
++ device_remove_file(&client->dev, &dev_attr_hpd);
++ device_remove_file(&client->dev, &dev_attr_regoffs);
++ device_remove_file(&client->dev, &dev_attr_regdump);
++
++ mutex_unlock(&td->access_lock);
++ v4l2_int_device_unregister(&tc358743_int_device);
++
++ for (i = REGULATOR_CNT - 1; i >= 0; i--) {
++ if (td->regulator[i]) {
++ regulator_disable(td->regulator[i]);
++ }
++ }
++ mutex_destroy(&td->access_lock);
++ if (g_td == td)
++ g_td = NULL;
++ kfree(td);
++ return 0;
++}
++
++/*!
++ * tc358743 init function
++ * Called by insmod tc358743_camera.ko.
++ *
++ * @return Error code indicating success or failure
++ */
++static __init int tc358743_init(void)
++{
++ int err;
++
++ err = i2c_add_driver(&tc358743_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d\n",
++ __func__, err);
++
++ return err;
++}
++
++/*!
++ * tc358743 cleanup function
++ * Called on rmmod tc358743_camera.ko
++ *
++ * @return Error code indicating success or failure
++ */
++static void __exit tc358743_clean(void)
++{
++ i2c_del_driver(&tc358743_i2c_driver);
++}
++
++module_init(tc358743_init);
++module_exit(tc358743_clean);
++
++MODULE_AUTHOR("Panasonic Avionics Corp.");
++MODULE_DESCRIPTION("Toshiba TC358743 HDMI-to-CSI2 Bridge MIPI Input Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/tda1997x.c linux-3.14.72/drivers/media/platform/mxc/capture/tda1997x.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/tda1997x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/tda1997x.c 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,451 @@
++/*
++ * tda1997x.c -- MXC video capture driver for i.MX boards with
++ * tda1997x HDMI receiver
++ *
++ * Copyright (C) 2013 Gateworks Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++/* The tda1997x-core driver manages the i2c interface with the device.
++ * This driver merely calls into that driver for current video parameters
++ * when necessary. The platform data for the core driver contains the
++ * video output bus configuration that configures the video port
++ * mapping between the tda1997x and a i.MX6 CSI parallel bus for 8bit
++ * bt656 with embedded syncs as this is the only video format compatible
++ * between the tda1997x and the i.MX6 CSI.
++ *
++ * see <linux/include/mfd/tda1997x-core.h> for details
++ */
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/fsl_devices.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/mfd/tda1997x-core.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/types.h>
++#include <linux/videodev2.h>
++#include <linux/workqueue.h>
++
++#include <media/v4l2-chip-ident.h>
++
++#include "v4l2-int-device.h"
++#include "mxc_v4l2_capture.h"
++
++/*!
++ * Maintains the information on the current state of the sensor.
++ */
++struct sensor {
++ struct sensor_data sen;
++ tda1997x_videofmt_t vidfmt;
++} tda1997x_data;
++
++/***********************************************************************
++ * mxc_v4l2_capture interface.
++ ***********************************************************************/
++
++/***********************************************************************
++ * IOCTL Functions from v4l2_int_ioctl_desc.
++ ***********************************************************************/
++
++/*!
++ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
++ * s: pointer to standard V4L2 device structure
++ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
++ *
++ * Gets slave interface parameters.
++ * Calculates the required xclk value to support the requested
++ * clock parameters in p. This value is returned in the p
++ * parameter.
++ *
++ * vidioc_int_g_ifparm returns platform-specific information about the
++ * interface settings used by the sensor.
++ *
++ * Called on open.
++ */
++static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
++{
++ struct sensor *sensor = s->priv;
++ tda1997x_vidout_fmt_t fmt;
++
++ if (s == NULL) {
++ pr_err(" ERROR!! no slave device set!\n");
++ return -ENODEV;
++ }
++
++ if (tda1997x_get_vidout_fmt(&fmt))
++ return -ENODEV;
++ pr_debug("%s: %dx%d%c@%dfps\n", __func__, fmt.width, fmt.height,
++ fmt.interlaced?'i':'p', fmt.fps);
++
++ /* Initialize structure to 0s then set any non-0 values. */
++ memset(p, 0, sizeof(*p));
++ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
++
++ if (sensor->vidfmt == VIDEOFMT_422_SMP) { /* YCbCr 4:2:2 semi-planar */
++ p->u.bt656.nobt_vs_inv = 0;
++ p->u.bt656.nobt_hs_inv = 1;
++ p->u.bt656.bt_sync_correct = 1;
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_16BIT;
++ p->u.bt656.clock_curr = -1; /* gated clock mode */
++ } else if (sensor->vidfmt == VIDEOFMT_422_CCIR) { /* YCbCr 4:2:2 CCIR656 */
++ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
++ p->u.bt656.clock_curr = (fmt.interlaced)?0:1;
++ }
++
++ return 0;
++}
++
++/*!
++ * Sets the device power.
++ *
++ * s pointer to the device device
++ * on if 1, power is to be turned on. 0 means power is to be turned off
++ *
++ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
++ * @s: pointer to standard V4L2 device structure
++ * @on: power state to which device is to be set
++ *
++ * Sets devices power state to requrested state, if possible.
++ * This is called on open, close, suspend and resume.
++static int ioctl_s_power(struct v4l2_int_device *s, int on)
++{
++ struct sensor *sensor = s->priv;
++
++ if (on && !sensor->sen.on) {
++ } else if (!on && sensor->sen.on) {
++ }
++
++ sensor->sen.on = on;
++
++ return 0;
++}
++ */
++
++/*!
++ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ struct sensor *sensor = s->priv;
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++
++ switch (a->type) {
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->sen.streamcap.capability;
++ cparm->timeperframe = sensor->sen.streamcap.timeperframe;
++ cparm->capturemode = sensor->sen.streamcap.capturemode;
++ break;
++
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ break;
++
++ default:
++ pr_debug("ioctl_g_parm:type is unknown %d\n", a->type);
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ *
++ * This driver cannot change these settings.
++ */
++static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
++{
++ switch (a->type) {
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
++ * @s: pointer to standard V4L2 device structure
++ * @f: pointer to standard V4L2 v4l2_format structure
++ *
++ * Returns the sensor's current pixel format in the v4l2_format
++ * parameter.
++ */
++static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
++{
++ struct sensor *sensor = s->priv;
++ tda1997x_vidout_fmt_t fmt;
++
++ if (tda1997x_get_vidout_fmt(&fmt))
++ return -ENODEV;
++
++ pr_debug("%s: %dx%d%c@%dfps\n", __func__, fmt.width, fmt.height,
++ fmt.interlaced?'i':'p', fmt.fps);
++ sensor->sen.pix.height = fmt.height;
++ sensor->sen.pix.width = fmt.width;
++ sensor->sen.streamcap.timeperframe.denominator = fmt.fps;
++ sensor->sen.streamcap.timeperframe.numerator = 1;
++ switch (f->type) {
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ pr_debug(" Returning size of %dx%d\n",
++ sensor->sen.pix.width, sensor->sen.pix.height);
++ f->fmt.pix = sensor->sen.pix;
++ pr_debug(" Returning format of %s\n", (char*)&f->fmt.pix.pixelformat);
++ break;
++
++ case V4L2_BUF_TYPE_PRIVATE: {
++ }
++ break;
++
++ default:
++ f->fmt.pix = sensor->sen.pix;
++ break;
++ }
++
++ return 0;
++}
++
++/*!
++ * ioctl_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ioctl_enum_framesizes(struct v4l2_int_device *s,
++ struct v4l2_frmsizeenum *fsize)
++{
++ struct sensor *sensor = s->priv;
++ tda1997x_vidout_fmt_t fmt;
++
++ if (fsize->index >= 1)
++ return -EINVAL;
++
++ if (tda1997x_get_vidout_fmt(&fmt))
++ return -ENODEV;
++
++ pr_debug("%s: %dx%d%c@%dfps\n", __func__, fmt.height, fmt.width,
++ fmt.interlaced?'i':'p', fmt.fps);
++ sensor->sen.pix.height = fmt.height;
++ sensor->sen.pix.width = fmt.width;
++ fsize->discrete.width = sensor->sen.pix.width;
++ fsize->discrete.height = sensor->sen.pix.height;
++
++ return 0;
++}
++
++/*!
++ * ioctl_g_chip_ident - V4L2 sensor interface handler for
++ * VIDIOC_DBG_G_CHIP_IDENT ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @id: pointer to int
++ *
++ * Return 0.
++ */
++static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
++{
++ struct sensor *sensor = s->priv;
++ ((struct v4l2_dbg_chip_ident *)id)->match.type =
++ V4L2_CHIP_MATCH_I2C_DRIVER;
++ if (sensor->vidfmt == VIDEOFMT_422_SMP) { /* YCbCr 4:2:2 semi-planar */
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "tda1997x_decoder_yuv422");
++ } else
++ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
++ "tda1997x_decoder_bt656");
++ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_TDA19971;
++
++ return 0;
++}
++
++/*!
++ * This structure defines all the ioctls for this module.
++ */
++static struct v4l2_int_ioctl_desc tda1997x_ioctl_desc[] = {
++
++/* {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, */
++ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm},
++ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap},
++ /*!
++ * If the requested format is supported, configures the HW to use that
++ * format, returns error code if format not supported or HW can't be
++ * correctly configured.
++ */
++ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm},
++ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm},
++ {vidioc_int_enum_framesizes_num,
++ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
++ {vidioc_int_g_chip_ident_num,
++ (v4l2_int_ioctl_func *)ioctl_g_chip_ident},
++};
++
++static struct v4l2_int_slave tda1997x_slave = {
++ .ioctls = tda1997x_ioctl_desc,
++ .num_ioctls = ARRAY_SIZE(tda1997x_ioctl_desc),
++};
++
++static struct v4l2_int_device tda1997x_int_device = {
++ .module = THIS_MODULE,
++ .name = "tda1997x-video",
++ .type = v4l2_int_type_slave,
++ .u = {
++ .slave = &tda1997x_slave,
++ },
++};
++
++static int tda1997x_video_probe(struct platform_device *pdev)
++{
++ struct sensor *sens = &tda1997x_data;
++ struct pinctrl *pinctrl;
++ struct device *dev = &pdev->dev;
++ struct regmap *gpr;
++ tda1997x_vidout_fmt_t fmt;
++ int ret;
++
++ dev_dbg(dev, "%s\n", __func__);
++
++ /* pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "setup pinctrl failed\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* Set initial values for the sensor struct. */
++ memset(sens, 0, sizeof(tda1997x_data));
++ if (tda1997x_get_vidout_fmt(&fmt))
++ return -ENODEV;
++ sens->vidfmt = fmt.sensor_vidfmt;
++ sens->sen.streamcap.timeperframe.denominator = 0;
++ sens->sen.streamcap.timeperframe.numerator = 0;
++ sens->sen.pix.width = 0;
++ sens->sen.pix.height = 0;
++ if (sens->vidfmt == VIDEOFMT_422_SMP)
++ sens->sen.pix.pixelformat = IPU_PIX_FMT_GENERIC_16;
++ else
++ sens->sen.pix.pixelformat = V4L2_PIX_FMT_UYVY;
++ sens->sen.on = true;
++
++ ret = of_property_read_u32(dev->of_node, "csi_id",
++ &(sens->sen.csi));
++ if (ret) {
++ dev_err(dev, "csi_id invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(dev->of_node, "ipu_id",
++ &(sens->sen.ipu_id));
++ if (ret) {
++ dev_err(dev, "ipu_id invalid\n");
++ return ret;
++ }
++
++ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ if (!IS_ERR(gpr)) {
++ if (of_machine_is_compatible("fsl,imx6q")) {
++ int mask = sens->sen.csi ? (1 << 20) : (1 << 19);
++
++ regmap_update_bits(gpr, IOMUXC_GPR1, mask, mask);
++ } else if (of_machine_is_compatible("fsl,imx6dl")) {
++ int mask = sens->sen.csi ? (7 << 3) : (7 << 0);
++ int val = sens->sen.csi ? (4 << 3) : (4 << 0);
++
++ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
++ }
++ } else {
++ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
++ __func__);
++ }
++
++ dev_dbg(dev, "IPU%d_CSI%d\n", sens->sen.ipu_id + 1, sens->sen.csi);
++ dev_dbg(dev, "type is %d (expect %d)\n",
++ tda1997x_int_device.type, v4l2_int_type_slave);
++ dev_dbg(dev, "num ioctls is %d\n",
++ tda1997x_int_device.u.slave->num_ioctls);
++
++ /* This function attaches this structure to the /dev/video<n> device */
++ tda1997x_int_device.priv = sens;
++ ret = v4l2_int_device_register(&tda1997x_int_device);
++
++ return ret;
++}
++
++static int tda1997x_video_remove(struct platform_device *pdev)
++{
++ v4l2_int_device_unregister(&tda1997x_int_device);
++
++ return 0;
++}
++
++static const struct of_device_id tda1997x_video_driver_ids[] = {
++ { .compatible = "fsl,imx-tda1997x-video", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver tda1997x_video_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "imx-tda1997x-video",
++ .of_match_table = tda1997x_video_driver_ids,
++ },
++ .probe = tda1997x_video_probe,
++ .remove = tda1997x_video_remove,
++};
++module_platform_driver(tda1997x_video_driver);
++
++MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
++MODULE_DESCRIPTION("TDA1997X hdmi receiver MXC video capture driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-tda1997x-video");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/v4l2-int-device.c linux-3.14.72/drivers/media/platform/mxc/capture/v4l2-int-device.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/v4l2-int-device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/v4l2-int-device.c 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,165 @@
++/*
++ * drivers/media/video/v4l2-int-device.c
++ *
++ * V4L2 internal ioctl interface.
++ *
++ * Copyright 2005-2014 Freescale Semiconductor, Inc.
++ * Copyright (C) 2007 Nokia Corporation.
++ *
++ * Contact: Sakari Ailus <sakari.ailus@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ */
++
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/sort.h>
++#include <linux/string.h>
++#include <linux/module.h>
++
++#include "v4l2-int-device.h"
++
++static DEFINE_MUTEX(mutex);
++static LIST_HEAD(int_list);
++
++void v4l2_int_device_try_attach_all(void)
++{
++ struct v4l2_int_device *m, *s;
++
++ list_for_each_entry(m, &int_list, head) {
++ if (m->type != v4l2_int_type_master)
++ continue;
++
++ list_for_each_entry(s, &int_list, head) {
++ if (s->type != v4l2_int_type_slave)
++ continue;
++
++ /* Slave is connected? */
++ if (s->u.slave->master)
++ continue;
++
++ /* Slave wants to attach to master? */
++ if (s->u.slave->attach_to[0] != 0
++ && strncmp(m->name, s->u.slave->attach_to,
++ V4L2NAMESIZE))
++ continue;
++
++ if (!try_module_get(m->module))
++ continue;
++
++ s->u.slave->master = m;
++ if (m->u.master->attach(s)) {
++ s->u.slave->master = NULL;
++ module_put(m->module);
++ continue;
++ }
++ }
++ }
++}
++EXPORT_SYMBOL_GPL(v4l2_int_device_try_attach_all);
++
++static int ioctl_sort_cmp(const void *a, const void *b)
++{
++ const struct v4l2_int_ioctl_desc *d1 = a, *d2 = b;
++
++ if (d1->num > d2->num)
++ return 1;
++
++ if (d1->num < d2->num)
++ return -1;
++
++ return 0;
++}
++
++int v4l2_int_device_register(struct v4l2_int_device *d)
++{
++ if (d->type == v4l2_int_type_slave)
++ sort(d->u.slave->ioctls, d->u.slave->num_ioctls,
++ sizeof(struct v4l2_int_ioctl_desc),
++ &ioctl_sort_cmp, NULL);
++ mutex_lock(&mutex);
++ list_add(&d->head, &int_list);
++ v4l2_int_device_try_attach_all();
++ mutex_unlock(&mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(v4l2_int_device_register);
++
++void v4l2_int_device_unregister(struct v4l2_int_device *d)
++{
++ mutex_lock(&mutex);
++ list_del(&d->head);
++ if (d->type == v4l2_int_type_slave
++ && d->u.slave->master != NULL) {
++ d->u.slave->master->u.master->detach(d);
++ module_put(d->u.slave->master->module);
++ d->u.slave->master = NULL;
++ }
++ mutex_unlock(&mutex);
++}
++EXPORT_SYMBOL_GPL(v4l2_int_device_unregister);
++
++/* Adapted from search_extable in extable.c. */
++static v4l2_int_ioctl_func *find_ioctl(struct v4l2_int_slave *slave, int cmd,
++ v4l2_int_ioctl_func *no_such_ioctl)
++{
++ const struct v4l2_int_ioctl_desc *first = slave->ioctls;
++ const struct v4l2_int_ioctl_desc *last =
++ first + slave->num_ioctls - 1;
++
++ while (first <= last) {
++ const struct v4l2_int_ioctl_desc *mid;
++
++ mid = (last - first) / 2 + first;
++
++ if (mid->num < cmd)
++ first = mid + 1;
++ else if (mid->num > cmd)
++ last = mid - 1;
++ else
++ return mid->func;
++ }
++
++ return no_such_ioctl;
++}
++
++static int no_such_ioctl_0(struct v4l2_int_device *d)
++{
++ return -ENOIOCTLCMD;
++}
++
++int v4l2_int_ioctl_0(struct v4l2_int_device *d, int cmd)
++{
++ return ((v4l2_int_ioctl_func_0 *)
++ find_ioctl(d->u.slave, cmd,
++ (v4l2_int_ioctl_func *)no_such_ioctl_0))(d);
++}
++EXPORT_SYMBOL_GPL(v4l2_int_ioctl_0);
++
++static int no_such_ioctl_1(struct v4l2_int_device *d, void *arg)
++{
++ return -ENOIOCTLCMD;
++}
++
++int v4l2_int_ioctl_1(struct v4l2_int_device *d, int cmd, void *arg)
++{
++ return ((v4l2_int_ioctl_func_1 *)
++ find_ioctl(d->u.slave, cmd,
++ (v4l2_int_ioctl_func *)no_such_ioctl_1))(d, arg);
++}
++EXPORT_SYMBOL_GPL(v4l2_int_ioctl_1);
++
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/capture/v4l2-int-device.h linux-3.14.72/drivers/media/platform/mxc/capture/v4l2-int-device.h
+--- linux-3.14.72.orig/drivers/media/platform/mxc/capture/v4l2-int-device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/capture/v4l2-int-device.h 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,317 @@
++/*
++ * include/media/v4l2-int-device.h
++ *
++ * V4L2 internal ioctl interface.
++ *
++ * Copyright 2005-2014 Freescale Semiconductor, Inc.
++ * Copyright (C) 2007 Nokia Corporation.
++ *
++ * Contact: Sakari Ailus <sakari.ailus@nokia.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++ * 02110-1301 USA
++ */
++
++#ifndef V4L2_INT_DEVICE_H
++#define V4L2_INT_DEVICE_H
++
++#include <media/v4l2-common.h>
++
++#define V4L2NAMESIZE 32
++
++/*
++ *
++ * The internal V4L2 device interface core.
++ *
++ */
++
++enum v4l2_int_type {
++ v4l2_int_type_master = 1,
++ v4l2_int_type_slave
++};
++
++struct module;
++
++struct v4l2_int_device;
++
++struct v4l2_int_master {
++ int (*attach)(struct v4l2_int_device *slave);
++ void (*detach)(struct v4l2_int_device *slave);
++};
++
++typedef int (v4l2_int_ioctl_func)(struct v4l2_int_device *);
++typedef int (v4l2_int_ioctl_func_0)(struct v4l2_int_device *);
++typedef int (v4l2_int_ioctl_func_1)(struct v4l2_int_device *, void *);
++
++struct v4l2_int_ioctl_desc {
++ int num;
++ v4l2_int_ioctl_func *func;
++};
++
++struct v4l2_int_slave {
++ /* Don't touch master. */
++ struct v4l2_int_device *master;
++
++ char attach_to[V4L2NAMESIZE];
++
++ int num_ioctls;
++ struct v4l2_int_ioctl_desc *ioctls;
++};
++
++struct v4l2_int_device {
++ /* Don't touch head. */
++ struct list_head head;
++
++ struct module *module;
++
++ char name[V4L2NAMESIZE];
++
++ enum v4l2_int_type type;
++ union {
++ struct v4l2_int_master *master;
++ struct v4l2_int_slave *slave;
++ } u;
++
++ void *priv;
++};
++
++void v4l2_int_device_try_attach_all(void);
++
++int v4l2_int_device_register(struct v4l2_int_device *d);
++void v4l2_int_device_unregister(struct v4l2_int_device *d);
++
++int v4l2_int_ioctl_0(struct v4l2_int_device *d, int cmd);
++int v4l2_int_ioctl_1(struct v4l2_int_device *d, int cmd, void *arg);
++
++/*
++ *
++ * Types and definitions for IOCTL commands.
++ *
++ */
++
++enum v4l2_power {
++ V4L2_POWER_OFF = 0,
++ V4L2_POWER_ON,
++ V4L2_POWER_STANDBY,
++};
++
++/* Slave interface type. */
++enum v4l2_if_type {
++ /*
++ * Parallel 8-, 10- or 12-bit interface, used by for example
++ * on certain image sensors.
++ */
++ V4L2_IF_TYPE_BT656,
++ V4L2_IF_TYPE_BT1120_PROGRESSIVE_DDR,
++ V4L2_IF_TYPE_BT1120_PROGRESSIVE_SDR,
++ V4L2_IF_TYPE_BT1120_INTERLACED_DDR,
++ V4L2_IF_TYPE_BT1120_INTERLACED_SDR,
++ V4L2_IF_TYPE_BT656_PROGRESSIVE,
++ V4L2_IF_TYPE_BT656_INTERLACED
++};
++
++enum v4l2_if_type_bt656_mode {
++ /*
++ * Modes without Bt synchronisation codes. Separate
++ * synchronisation signal lines are used.
++ */
++ V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT,
++ V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT,
++ V4L2_IF_TYPE_BT656_MODE_NOBT_12BIT,
++ /*
++ * Use Bt synchronisation codes. The vertical and horizontal
++ * synchronisation is done based on synchronisation codes.
++ */
++ V4L2_IF_TYPE_BT656_MODE_BT_8BIT,
++ V4L2_IF_TYPE_BT656_MODE_BT_10BIT,
++};
++
++struct v4l2_if_type_bt656 {
++ /*
++ * 0: Frame begins when vsync is high.
++ * 1: Frame begins when vsync changes from low to high.
++ */
++ unsigned frame_start_on_rising_vs:1;
++ /* Use Bt synchronisation codes for sync correction. */
++ unsigned bt_sync_correct:1;
++ /* Swap every two adjacent image data elements. */
++ unsigned swap:1;
++ /* Inverted latch clock polarity from slave. */
++ unsigned latch_clk_inv:1;
++ /* Hs polarity. 0 is active high, 1 active low. */
++ unsigned nobt_hs_inv:1;
++ /* Vs polarity. 0 is active high, 1 active low. */
++ unsigned nobt_vs_inv:1;
++ enum v4l2_if_type_bt656_mode mode;
++ /* Minimum accepted bus clock for slave (in Hz). */
++ u32 clock_min;
++ /* Maximum accepted bus clock for slave. */
++ u32 clock_max;
++ /*
++ * Current wish of the slave. May only change in response to
++ * ioctls that affect image capture.
++ */
++ u32 clock_curr;
++};
++
++struct v4l2_ifparm {
++ enum v4l2_if_type if_type;
++ union {
++ struct v4l2_if_type_bt656 bt656;
++ } u;
++};
++
++/* IOCTL command numbers. */
++enum v4l2_int_ioctl_num {
++ /*
++ *
++ * "Proper" V4L ioctls, as in struct video_device.
++ *
++ */
++ vidioc_int_enum_fmt_cap_num = 1,
++ vidioc_int_g_fmt_cap_num,
++ vidioc_int_s_fmt_cap_num,
++ vidioc_int_try_fmt_cap_num,
++ vidioc_int_queryctrl_num,
++ vidioc_int_g_ctrl_num,
++ vidioc_int_s_ctrl_num,
++ vidioc_int_cropcap_num,
++ vidioc_int_g_crop_num,
++ vidioc_int_s_crop_num,
++ vidioc_int_g_parm_num,
++ vidioc_int_s_parm_num,
++ vidioc_int_querystd_num,
++ vidioc_int_s_std_num,
++ vidioc_int_s_video_routing_num,
++ vidioc_int_send_command_num,
++
++ /*
++ *
++ * Strictly internal ioctls.
++ *
++ */
++ /* Initialise the device when slave attaches to the master. */
++ vidioc_int_dev_init_num = 1000,
++ /* Delinitialise the device at slave detach. */
++ vidioc_int_dev_exit_num,
++ /* Set device power state. */
++ vidioc_int_s_power_num,
++ /*
++ * Get slave private data, e.g. platform-specific slave
++ * configuration used by the master.
++ */
++ vidioc_int_g_priv_num,
++ /* Get slave interface parameters. */
++ vidioc_int_g_ifparm_num,
++ /* Does the slave need to be reset after VIDIOC_DQBUF? */
++ vidioc_int_g_needs_reset_num,
++ vidioc_int_enum_framesizes_num,
++ vidioc_int_enum_frameintervals_num,
++
++ /*
++ *
++ * VIDIOC_INT_* ioctls.
++ *
++ */
++ /* VIDIOC_INT_RESET */
++ vidioc_int_reset_num,
++ /* VIDIOC_INT_INIT */
++ vidioc_int_init_num,
++ /* VIDIOC_DBG_G_CHIP_IDENT */
++ vidioc_int_g_chip_ident_num,
++
++ /*
++ *
++ * Start of private ioctls.
++ *
++ */
++ vidioc_int_priv_start_num = 2000,
++};
++
++/*
++ *
++ * IOCTL wrapper functions for better type checking.
++ *
++ */
++
++#define V4L2_INT_WRAPPER_0(name) \
++ static inline int vidioc_int_##name(struct v4l2_int_device *d) \
++ { \
++ return v4l2_int_ioctl_0(d, vidioc_int_##name##_num); \
++ } \
++ \
++ static inline struct v4l2_int_ioctl_desc \
++ vidioc_int_##name##_cb(int (*func) \
++ (struct v4l2_int_device *)) \
++ { \
++ struct v4l2_int_ioctl_desc desc; \
++ \
++ desc.num = vidioc_int_##name##_num; \
++ desc.func = (v4l2_int_ioctl_func *)func; \
++ \
++ return desc; \
++ }
++
++#define V4L2_INT_WRAPPER_1(name, arg_type, asterisk) \
++ static inline int vidioc_int_##name(struct v4l2_int_device *d, \
++ arg_type asterisk arg) \
++ { \
++ return v4l2_int_ioctl_1(d, vidioc_int_##name##_num, \
++ (void *)(unsigned long)arg); \
++ } \
++ \
++ static inline struct v4l2_int_ioctl_desc \
++ vidioc_int_##name##_cb(int (*func) \
++ (struct v4l2_int_device *, \
++ arg_type asterisk)) \
++ { \
++ struct v4l2_int_ioctl_desc desc; \
++ \
++ desc.num = vidioc_int_##name##_num; \
++ desc.func = (v4l2_int_ioctl_func *)func; \
++ \
++ return desc; \
++ }
++
++V4L2_INT_WRAPPER_1(enum_fmt_cap, struct v4l2_fmtdesc, *);
++V4L2_INT_WRAPPER_1(g_fmt_cap, struct v4l2_format, *);
++V4L2_INT_WRAPPER_1(s_fmt_cap, struct v4l2_format, *);
++V4L2_INT_WRAPPER_1(try_fmt_cap, struct v4l2_format, *);
++V4L2_INT_WRAPPER_1(queryctrl, struct v4l2_queryctrl, *);
++V4L2_INT_WRAPPER_1(g_ctrl, struct v4l2_control, *);
++V4L2_INT_WRAPPER_1(s_ctrl, struct v4l2_control, *);
++V4L2_INT_WRAPPER_1(cropcap, struct v4l2_cropcap, *);
++V4L2_INT_WRAPPER_1(g_crop, struct v4l2_crop, *);
++V4L2_INT_WRAPPER_1(s_crop, struct v4l2_crop, *);
++V4L2_INT_WRAPPER_1(g_parm, struct v4l2_streamparm, *);
++V4L2_INT_WRAPPER_1(s_parm, struct v4l2_streamparm, *);
++V4L2_INT_WRAPPER_1(querystd, v4l2_std_id, *);
++V4L2_INT_WRAPPER_1(s_std, v4l2_std_id, *);
++V4L2_INT_WRAPPER_1(s_video_routing, struct v4l2_routing, *);
++V4L2_INT_WRAPPER_1(send_command, struct v4l2_send_command_control, *);
++
++V4L2_INT_WRAPPER_0(dev_init);
++V4L2_INT_WRAPPER_0(dev_exit);
++V4L2_INT_WRAPPER_1(s_power, enum v4l2_power, /*dummy arg*/);
++V4L2_INT_WRAPPER_1(g_priv, void, *);
++V4L2_INT_WRAPPER_1(g_ifparm, struct v4l2_ifparm, *);
++V4L2_INT_WRAPPER_1(g_needs_reset, void, *);
++V4L2_INT_WRAPPER_1(enum_framesizes, struct v4l2_frmsizeenum, *);
++V4L2_INT_WRAPPER_1(enum_frameintervals, struct v4l2_frmivalenum, *);
++
++V4L2_INT_WRAPPER_0(reset);
++V4L2_INT_WRAPPER_0(init);
++V4L2_INT_WRAPPER_1(g_chip_ident, int, *);
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/output/Kconfig linux-3.14.72/drivers/media/platform/mxc/output/Kconfig
+--- linux-3.14.72.orig/drivers/media/platform/mxc/output/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/output/Kconfig 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,16 @@
++config VIDEO_MXC_IPU_OUTPUT
++ tristate "IPU v4l2 output support"
++ depends on VIDEO_MXC_OUTPUT && MXC_IPU
++ ---help---
++ This is the video4linux2 driver for IPU post processing video output.
++
++config VIDEO_MXC_PXP_V4L2
++ tristate "MXC PxP V4L2 driver"
++ depends on VIDEO_DEV && VIDEO_V4L2
++ select VIDEOBUF_DMA_CONTIG
++ ---help---
++ This is a video4linux driver for the Freescale PxP
++ (Pixel Pipeline). This module supports output overlay of
++ the MXC framebuffer on a video stream.
++
++ To compile this driver as a module, choose M here.
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/output/Makefile linux-3.14.72/drivers/media/platform/mxc/output/Makefile
+--- linux-3.14.72.orig/drivers/media/platform/mxc/output/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/output/Makefile 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc_vout.o
++obj-$(CONFIG_VIDEO_MXC_PXP_V4L2) += mxc_pxp_v4l2.o
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c linux-3.14.72/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/output/mxc_pxp_v4l2.c 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,1338 @@
++/*
++ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X PxP driver
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/platform_device.h>
++#include <linux/vmalloc.h>
++#include <linux/videodev2.h>
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++#include <linux/delay.h>
++#include <linux/console.h>
++#include <linux/mxcfb.h>
++
++#include <media/videobuf-dma-contig.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-dev.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++
++#include "mxc_pxp_v4l2.h"
++
++#define PXP_DRIVER_NAME "pxp-v4l2"
++#define PXP_DRIVER_MAJOR 2
++#define PXP_DRIVER_MINOR 0
++
++#define PXP_DEF_BUFS 2
++#define PXP_MIN_PIX 8
++
++#define V4L2_OUTPUT_TYPE_INTERNAL 4
++
++static int video_nr = -1; /* -1 ==> auto assign */
++static struct pxp_data_format pxp_s0_formats[] = {
++ {
++ .name = "24-bit RGB",
++ .bpp = 4,
++ .fourcc = V4L2_PIX_FMT_RGB24,
++ .colorspace = V4L2_COLORSPACE_SRGB,
++ }, {
++ .name = "16-bit RGB 5:6:5",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_RGB565,
++ .colorspace = V4L2_COLORSPACE_SRGB,
++ }, {
++ .name = "16-bit RGB 5:5:5",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_RGB555,
++ .colorspace = V4L2_COLORSPACE_SRGB,
++ }, {
++ .name = "YUV 4:2:0 Planar",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_YUV420,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ }, {
++ .name = "YUV 4:2:2 Planar",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_YUV422P,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ }, {
++ .name = "UYVY",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_UYVY,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ }, {
++ .name = "YUYV",
++ .bpp = 2,
++ .fourcc = V4L2_PIX_FMT_YUYV,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ }, {
++ .name = "YUV32",
++ .bpp = 4,
++ .fourcc = V4L2_PIX_FMT_YUV32,
++ .colorspace = V4L2_COLORSPACE_JPEG,
++ },
++};
++
++static unsigned int v4l2_fmt_to_pxp_fmt(u32 v4l2_pix_fmt)
++{
++ u32 pxp_fmt = 0;
++
++ if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB24)
++ pxp_fmt = PXP_PIX_FMT_RGB24;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB565)
++ pxp_fmt = PXP_PIX_FMT_RGB565;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555)
++ pxp_fmt = PXP_PIX_FMT_RGB555;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_RGB555)
++ pxp_fmt = PXP_PIX_FMT_RGB555;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV420)
++ pxp_fmt = PXP_PIX_FMT_YUV420P;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV422P)
++ pxp_fmt = PXP_PIX_FMT_YUV422P;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_UYVY)
++ pxp_fmt = PXP_PIX_FMT_UYVY;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUV32)
++ pxp_fmt = PXP_PIX_FMT_VUY444;
++ else if (v4l2_pix_fmt == V4L2_PIX_FMT_YUYV)
++ pxp_fmt = PXP_PIX_FMT_YUYV;
++
++ return pxp_fmt;
++}
++struct v4l2_queryctrl pxp_controls[] = {
++ {
++ .id = V4L2_CID_HFLIP,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ .name = "Horizontal Flip",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_VFLIP,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ .name = "Vertical Flip",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ .name = "Rotation",
++ .minimum = 0,
++ .maximum = 270,
++ .step = 90,
++ .default_value = 0,
++ .flags = 0,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE + 1,
++ .name = "Background Color",
++ .minimum = 0,
++ .maximum = 0xFFFFFF,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE + 2,
++ .name = "Set S0 Chromakey",
++ .minimum = -1,
++ .maximum = 0xFFFFFF,
++ .step = 1,
++ .default_value = -1,
++ .flags = 0,
++ .type = V4L2_CTRL_TYPE_INTEGER,
++ }, {
++ .id = V4L2_CID_PRIVATE_BASE + 3,
++ .name = "YUV Colorspace",
++ .minimum = 0,
++ .maximum = 1,
++ .step = 1,
++ .default_value = 0,
++ .flags = 0,
++ .type = V4L2_CTRL_TYPE_BOOLEAN,
++ },
++};
++
++static void free_dma_buf(struct pxps *pxp, struct dma_mem *buf)
++{
++ dma_free_coherent(&pxp->pdev->dev, buf->size, buf->vaddr, buf->paddr);
++ dev_dbg(&pxp->pdev->dev,
++ "free dma size:0x%x, paddr:0x%x\n",
++ buf->size, buf->paddr);
++ memset(buf, 0, sizeof(*buf));
++}
++
++static int alloc_dma_buf(struct pxps *pxp, struct dma_mem *buf)
++{
++
++ buf->vaddr = dma_alloc_coherent(&pxp->pdev->dev, buf->size, &buf->paddr,
++ GFP_DMA | GFP_KERNEL);
++ if (!buf->vaddr) {
++ dev_err(&pxp->pdev->dev,
++ "cannot get dma buf size:0x%x\n", buf->size);
++ return -ENOMEM;
++ }
++ dev_dbg(&pxp->pdev->dev,
++ "alloc dma buf size:0x%x, paddr:0x%x\n", buf->size, buf->paddr);
++ return 0;
++}
++
++/* callback function */
++static void video_dma_done(void *arg)
++{
++ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
++ struct dma_chan *chan = tx_desc->txd.chan;
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct pxps *pxp = pxp_chan->client;
++ struct videobuf_buffer *vb;
++
++ dev_dbg(chan->device->dev, "callback cookie %d, active DMA 0x%08x\n",
++ tx_desc->txd.cookie,
++ pxp->active ? sg_dma_address(&pxp->active->sg[0]) : 0);
++
++ spin_lock(&pxp->lock);
++ if (pxp->active) {
++ vb = &pxp->active->vb;
++
++ list_del_init(&vb->queue);
++ vb->state = VIDEOBUF_DONE;
++ do_gettimeofday(&vb->ts);
++ vb->field_count++;
++ wake_up(&vb->done);
++ }
++
++ if (list_empty(&pxp->outq)) {
++ pxp->active = NULL;
++ spin_unlock(&pxp->lock);
++
++ return;
++ }
++
++ pxp->active = list_entry(pxp->outq.next,
++ struct pxp_buffer, vb.queue);
++ pxp->active->vb.state = VIDEOBUF_ACTIVE;
++ spin_unlock(&pxp->lock);
++}
++
++static int acquire_dma_channel(struct pxps *pxp)
++{
++ dma_cap_mask_t mask;
++ struct dma_chan *chan;
++ struct pxp_channel **pchan = &pxp->pxp_channel[0];
++
++ if (*pchan) {
++ struct videobuf_buffer *vb, *_vb;
++ dma_release_channel(&(*pchan)->dma_chan);
++ *pchan = NULL;
++ pxp->active = NULL;
++ list_for_each_entry_safe(vb, _vb, &pxp->outq, queue) {
++ list_del_init(&vb->queue);
++ vb->state = VIDEOBUF_ERROR;
++ wake_up(&vb->done);
++ }
++ }
++
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_PRIVATE, mask);
++ chan = dma_request_channel(mask, NULL, NULL);
++ if (!chan)
++ return -EBUSY;
++
++ *pchan = to_pxp_channel(chan);
++ (*pchan)->client = pxp;
++
++ return 0;
++}
++
++static int _get_fbinfo(struct fb_info **fbi)
++{
++ int i;
++ for (i = 0; i < num_registered_fb; i++) {
++ char *idstr = registered_fb[i]->fix.id;
++ if (strncmp(idstr, "mxs", 3) == 0) {
++ *fbi = registered_fb[i];
++ return 0;
++ }
++ }
++
++ return -ENODEV;
++}
++
++static int pxp_set_fbinfo(struct pxps *pxp)
++{
++ struct v4l2_framebuffer *fb = &pxp->fb;
++ int err;
++
++ err = _get_fbinfo(&pxp->fbi);
++ if (err)
++ return err;
++
++ fb->fmt.width = pxp->fbi->var.xres;
++ fb->fmt.height = pxp->fbi->var.yres;
++ pxp->pxp_conf.out_param.stride = pxp->fbi->var.xres;
++ if (pxp->fbi->var.bits_per_pixel == 16)
++ fb->fmt.pixelformat = V4L2_PIX_FMT_RGB565;
++ else
++ fb->fmt.pixelformat = V4L2_PIX_FMT_RGB24;
++
++ fb->base = (void *)pxp->fbi->fix.smem_start;
++
++ return 0;
++}
++
++static int _get_cur_fb_blank(struct pxps *pxp)
++{
++ struct fb_info *fbi;
++ mm_segment_t old_fs;
++ int err = 0;
++
++ err = _get_fbinfo(&fbi);
++ if (err)
++ return err;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ err = fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_BLANK,
++ (unsigned int)(&pxp->fb_blank));
++ set_fs(old_fs);
++ }
++
++ return err;
++}
++
++static int pxp_show_buf(struct pxps *pxp, unsigned long paddr)
++{
++ struct fb_info *fbi = pxp->fbi;
++ int ret = -EINVAL;
++
++ if (paddr == 0) {
++ dev_err(&pxp->pdev->dev, "Invalid paddr\n");
++ return ret;
++ }
++
++ console_lock();
++ fbi->fix.smem_start = paddr;
++ ret = fb_pan_display(fbi, &fbi->var);
++ console_unlock();
++
++ return ret;
++}
++
++static int set_fb_blank(int blank)
++{
++ struct fb_info *fbi;
++ int err = 0;
++
++ err = _get_fbinfo(&fbi);
++ if (err)
++ return err;
++
++ console_lock();
++ fb_blank(fbi, blank);
++ console_unlock();
++
++ return err;
++}
++
++static int pxp_set_cstate(struct pxps *pxp, struct v4l2_control *vc)
++{
++
++ if (vc->id == V4L2_CID_HFLIP) {
++ pxp->pxp_conf.proc_data.hflip = vc->value;
++ } else if (vc->id == V4L2_CID_VFLIP) {
++ pxp->pxp_conf.proc_data.vflip = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE) {
++ if (vc->value % 90)
++ return -ERANGE;
++ pxp->pxp_conf.proc_data.rotate = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE + 1) {
++ pxp->pxp_conf.proc_data.bgcolor = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE + 2) {
++ pxp->pxp_conf.s0_param.color_key = vc->value;
++ } else if (vc->id == V4L2_CID_PRIVATE_BASE + 3) {
++ pxp->pxp_conf.proc_data.yuv = vc->value;
++ }
++
++ return 0;
++}
++
++static int pxp_get_cstate(struct pxps *pxp, struct v4l2_control *vc)
++{
++ if (vc->id == V4L2_CID_HFLIP)
++ vc->value = pxp->pxp_conf.proc_data.hflip;
++ else if (vc->id == V4L2_CID_VFLIP)
++ vc->value = pxp->pxp_conf.proc_data.vflip;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE)
++ vc->value = pxp->pxp_conf.proc_data.rotate;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE + 1)
++ vc->value = pxp->pxp_conf.proc_data.bgcolor;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE + 2)
++ vc->value = pxp->pxp_conf.s0_param.color_key;
++ else if (vc->id == V4L2_CID_PRIVATE_BASE + 3)
++ vc->value = pxp->pxp_conf.proc_data.yuv;
++
++ return 0;
++}
++
++static int pxp_enumoutput(struct file *file, void *fh,
++ struct v4l2_output *o)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ if ((o->index < 0) || (o->index > 1))
++ return -EINVAL;
++
++ memset(o, 0, sizeof(struct v4l2_output));
++ if (o->index == 0) {
++ strcpy(o->name, "PxP Display Output");
++ pxp->output = 0;
++ } else {
++ strcpy(o->name, "PxP Virtual Output");
++ pxp->output = 1;
++ }
++ o->type = V4L2_OUTPUT_TYPE_INTERNAL;
++ o->std = 0;
++ o->reserved[0] = pxp->outbuf.paddr;
++
++ return 0;
++}
++
++static int pxp_g_output(struct file *file, void *fh,
++ unsigned int *i)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ *i = pxp->output;
++
++ return 0;
++}
++
++static int pxp_s_output(struct file *file, void *fh,
++ unsigned int i)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_pix_format *fmt = &pxp->fb.fmt;
++ u32 size;
++ int ret, bpp;
++
++ if ((i < 0) || (i > 1))
++ return -EINVAL;
++
++ /* Output buffer is same format as fbdev */
++ if (fmt->pixelformat == V4L2_PIX_FMT_RGB24 ||
++ fmt->pixelformat == V4L2_PIX_FMT_YUV32)
++ bpp = 4;
++ else
++ bpp = 2;
++
++ size = fmt->width * fmt->height * bpp;
++ if (size > pxp->outbuf.size) {
++ if (pxp->outbuf.vaddr)
++ free_dma_buf(pxp, &pxp->outbuf);
++ pxp->outbuf.size = size;
++ ret = alloc_dma_buf(pxp, &pxp->outbuf);
++ if (ret < 0)
++ return ret;
++ }
++ memset(pxp->outbuf.vaddr, 0x0, pxp->outbuf.size);
++
++ pxp->pxp_conf.out_param.width = fmt->width;
++ pxp->pxp_conf.out_param.height = fmt->height;
++ if (fmt->pixelformat == V4L2_PIX_FMT_RGB24)
++ pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB24;
++ else
++ pxp->pxp_conf.out_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++
++ return 0;
++}
++
++static int pxp_enum_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_fmtdesc *fmt)
++{
++ enum v4l2_buf_type type = fmt->type;
++ int index = fmt->index;
++
++ if ((fmt->index < 0) || (fmt->index >= ARRAY_SIZE(pxp_s0_formats)))
++ return -EINVAL;
++
++ memset(fmt, 0, sizeof(struct v4l2_fmtdesc));
++ fmt->index = index;
++ fmt->type = type;
++ fmt->pixelformat = pxp_s0_formats[index].fourcc;
++ strcpy(fmt->description, pxp_s0_formats[index].name);
++
++ return 0;
++}
++
++static int pxp_g_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct v4l2_pix_format *pf = &f->fmt.pix;
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct pxp_data_format *fmt = pxp->s0_fmt;
++
++ pf->width = pxp->pxp_conf.s0_param.width;
++ pf->height = pxp->pxp_conf.s0_param.height;
++ pf->pixelformat = fmt->fourcc;
++ pf->field = V4L2_FIELD_NONE;
++ pf->bytesperline = fmt->bpp * pf->width;
++ pf->sizeimage = pf->bytesperline * pf->height;
++ pf->colorspace = fmt->colorspace;
++ pf->priv = 0;
++
++ return 0;
++}
++
++static struct pxp_data_format *pxp_get_format(struct v4l2_format *f)
++{
++ struct pxp_data_format *fmt;
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pxp_s0_formats); i++) {
++ fmt = &pxp_s0_formats[i];
++ if (fmt->fourcc == f->fmt.pix.pixelformat)
++ break;
++ }
++
++ if (i == ARRAY_SIZE(pxp_s0_formats))
++ return NULL;
++
++ return &pxp_s0_formats[i];
++}
++
++static int pxp_try_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ int w = f->fmt.pix.width;
++ int h = f->fmt.pix.height;
++ struct pxp_data_format *fmt = pxp_get_format(f);
++
++ if (!fmt)
++ return -EINVAL;
++
++ w = min(w, 2040);
++ w = max(w, 8);
++ h = min(h, 2040);
++ h = max(h, 8);
++ f->fmt.pix.field = V4L2_FIELD_NONE;
++ f->fmt.pix.width = w;
++ f->fmt.pix.height = h;
++ f->fmt.pix.pixelformat = fmt->fourcc;
++
++ return 0;
++}
++
++static int pxp_s_fmt_video_output(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_pix_format *pf = &f->fmt.pix;
++ int ret;
++
++ ret = acquire_dma_channel(pxp);
++ if (ret < 0)
++ return ret;
++
++ ret = pxp_try_fmt_video_output(file, fh, f);
++ if (ret == 0) {
++ pxp->s0_fmt = pxp_get_format(f);
++ pxp->pxp_conf.s0_param.pixel_fmt =
++ v4l2_fmt_to_pxp_fmt(pxp->s0_fmt->fourcc);
++ pxp->pxp_conf.s0_param.width = pf->width;
++ pxp->pxp_conf.s0_param.height = pf->height;
++ }
++
++
++ return ret;
++}
++
++static int pxp_g_fmt_output_overlay(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_window *wf = &f->fmt.win;
++
++ memset(wf, 0, sizeof(struct v4l2_window));
++ wf->chromakey = pxp->s1_chromakey;
++ wf->global_alpha = pxp->global_alpha;
++ wf->field = V4L2_FIELD_NONE;
++ wf->clips = NULL;
++ wf->clipcount = 0;
++ wf->bitmap = NULL;
++ wf->w.left = pxp->pxp_conf.proc_data.srect.left;
++ wf->w.top = pxp->pxp_conf.proc_data.srect.top;
++ wf->w.width = pxp->pxp_conf.proc_data.srect.width;
++ wf->w.height = pxp->pxp_conf.proc_data.srect.height;
++
++ return 0;
++}
++
++static int pxp_try_fmt_output_overlay(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_window *wf = &f->fmt.win;
++ struct v4l2_rect srect;
++ u32 s1_chromakey = wf->chromakey;
++ u8 global_alpha = wf->global_alpha;
++
++ memcpy(&srect, &(wf->w), sizeof(struct v4l2_rect));
++
++ pxp_g_fmt_output_overlay(file, fh, f);
++
++ wf->chromakey = s1_chromakey;
++ wf->global_alpha = global_alpha;
++
++ /* Constrain parameters to the input buffer */
++ wf->w.left = srect.left;
++ wf->w.top = srect.top;
++ wf->w.width = min(srect.width,
++ ((__u32)pxp->pxp_conf.s0_param.width - wf->w.left));
++ wf->w.height = min(srect.height,
++ ((__u32)pxp->pxp_conf.s0_param.height - wf->w.top));
++
++ return 0;
++}
++
++static int pxp_s_fmt_output_overlay(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ struct v4l2_window *wf = &f->fmt.win;
++ int ret = pxp_try_fmt_output_overlay(file, fh, f);
++
++ if (ret == 0) {
++ pxp->global_alpha = wf->global_alpha;
++ pxp->s1_chromakey = wf->chromakey;
++ pxp->pxp_conf.proc_data.srect.left = wf->w.left;
++ pxp->pxp_conf.proc_data.srect.top = wf->w.top;
++ pxp->pxp_conf.proc_data.srect.width = wf->w.width;
++ pxp->pxp_conf.proc_data.srect.height = wf->w.height;
++ pxp->pxp_conf.ol_param[0].global_alpha = pxp->global_alpha;
++ pxp->pxp_conf.ol_param[0].color_key = pxp->s1_chromakey;
++ pxp->pxp_conf.ol_param[0].color_key_enable =
++ pxp->s1_chromakey_state;
++ }
++
++ return ret;
++}
++
++static int pxp_reqbufs(struct file *file, void *priv,
++ struct v4l2_requestbuffers *r)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ return videobuf_reqbufs(&pxp->s0_vbq, r);
++}
++
++static int pxp_querybuf(struct file *file, void *priv,
++ struct v4l2_buffer *b)
++{
++ int ret;
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ ret = videobuf_querybuf(&pxp->s0_vbq, b);
++ if (!ret) {
++ struct videobuf_buffer *vb = pxp->s0_vbq.bufs[b->index];
++ if (b->flags & V4L2_BUF_FLAG_MAPPED)
++ b->m.offset = videobuf_to_dma_contig(vb);
++ }
++
++ return ret;
++}
++
++static int pxp_qbuf(struct file *file, void *priv,
++ struct v4l2_buffer *b)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ return videobuf_qbuf(&pxp->s0_vbq, b);
++}
++
++static int pxp_dqbuf(struct file *file, void *priv,
++ struct v4l2_buffer *b)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ return videobuf_dqbuf(&pxp->s0_vbq, b, file->f_flags & O_NONBLOCK);
++}
++
++static int pxp_streamon(struct file *file, void *priv,
++ enum v4l2_buf_type t)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret = 0;
++
++ if (t != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ _get_cur_fb_blank(pxp);
++ set_fb_blank(FB_BLANK_UNBLANK);
++
++ ret = videobuf_streamon(&pxp->s0_vbq);
++
++ if (!ret && (pxp->output == 0))
++ pxp_show_buf(pxp, pxp->outbuf.paddr);
++
++ return ret;
++}
++
++static int pxp_streamoff(struct file *file, void *priv,
++ enum v4l2_buf_type t)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret = 0;
++
++ if ((t != V4L2_BUF_TYPE_VIDEO_OUTPUT))
++ return -EINVAL;
++
++ ret = videobuf_streamoff(&pxp->s0_vbq);
++
++ pxp_show_buf(pxp, (unsigned long)pxp->fb.base);
++
++ if (pxp->fb_blank)
++ set_fb_blank(FB_BLANK_POWERDOWN);
++
++ return ret;
++}
++
++static int pxp_buf_setup(struct videobuf_queue *q,
++ unsigned int *count, unsigned *size)
++{
++ struct pxps *pxp = q->priv_data;
++
++ *size = pxp->pxp_conf.s0_param.width *
++ pxp->pxp_conf.s0_param.height * pxp->s0_fmt->bpp;
++
++ if (0 == *count)
++ *count = PXP_DEF_BUFS;
++
++ return 0;
++}
++
++static void pxp_buf_free(struct videobuf_queue *q, struct pxp_buffer *buf)
++{
++ struct videobuf_buffer *vb = &buf->vb;
++
++ BUG_ON(in_interrupt());
++
++ pr_debug("%s (vb=0x%p) 0x%08lx %d\n", __func__,
++ vb, vb->baddr, vb->bsize);
++
++ /*
++ * This waits until this buffer is out of danger, i.e., until it is no
++ * longer in STATE_QUEUED or STATE_ACTIVE
++ */
++ videobuf_waiton(q, vb, 0, 0);
++
++ videobuf_dma_contig_free(q, vb);
++ buf->txd = NULL;
++
++ vb->state = VIDEOBUF_NEEDS_INIT;
++}
++
++static int pxp_buf_prepare(struct videobuf_queue *q,
++ struct videobuf_buffer *vb,
++ enum v4l2_field field)
++{
++ struct pxps *pxp = q->priv_data;
++ struct pxp_config_data *pxp_conf = &pxp->pxp_conf;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb);
++ struct pxp_tx_desc *desc;
++ int ret = 0;
++ int i, length;
++
++ if (!pxp->outbuf.paddr) {
++ dev_err(&pxp->pdev->dev, "Not allocate memory for "
++ "PxP Out buffer?\n");
++ return -ENOMEM;
++ }
++
++ vb->width = pxp->pxp_conf.s0_param.width;
++ vb->height = pxp->pxp_conf.s0_param.height;
++ vb->size = vb->width * vb->height * pxp->s0_fmt->bpp;
++ vb->field = V4L2_FIELD_NONE;
++ if (vb->state != VIDEOBUF_NEEDS_INIT)
++ pxp_buf_free(q, buf);
++
++ if (vb->state == VIDEOBUF_NEEDS_INIT) {
++ struct pxp_channel *pchan = pxp->pxp_channel[0];
++ struct scatterlist *sg = &buf->sg[0];
++
++ /* This actually (allocates and) maps buffers */
++ ret = videobuf_iolock(q, vb, NULL);
++ if (ret) {
++ pr_err("fail to call videobuf_iolock, ret = %d\n", ret);
++ goto fail;
++ }
++
++ /*
++ * sg[0] for input(S0)
++ * Sg[1] for output
++ */
++ sg_init_table(sg, 3);
++
++ buf->txd = pchan->dma_chan.device->device_prep_slave_sg(
++ &pchan->dma_chan, sg, 3, DMA_FROM_DEVICE,
++ DMA_PREP_INTERRUPT, NULL);
++ if (!buf->txd) {
++ ret = -EIO;
++ goto fail;
++ }
++
++ buf->txd->callback_param = buf->txd;
++ buf->txd->callback = video_dma_done;
++
++ desc = to_tx_desc(buf->txd);
++ length = desc->len;
++ for (i = 0; i < length; i++) {
++ if (i == 0) {/* S0 */
++ memcpy(&desc->proc_data, proc_data,
++ sizeof(struct pxp_proc_data));
++ pxp_conf->s0_param.paddr =
++ videobuf_to_dma_contig(vb);
++ memcpy(&desc->layer_param.s0_param,
++ &pxp_conf->s0_param,
++ sizeof(struct pxp_layer_param));
++ } else if (i == 1) { /* Output */
++ /* we should always pass the output
++ * width and height which is the value
++ * after been rotated.
++ */
++ pxp_conf->out_param.width =
++ pxp->fb.fmt.width;
++ pxp_conf->out_param.height =
++ pxp->fb.fmt.height;
++
++ pxp_conf->out_param.paddr = pxp->outbuf.paddr;
++ memcpy(&desc->layer_param.out_param,
++ &pxp_conf->out_param,
++ sizeof(struct pxp_layer_param));
++ } else if (pxp_conf->ol_param[0].combine_enable) {
++ /* Overlay */
++ pxp_conf->ol_param[0].paddr =
++ (dma_addr_t)pxp->fb.base;
++ pxp_conf->ol_param[0].width = pxp->fb.fmt.width;
++ pxp_conf->ol_param[0].height =
++ pxp->fb.fmt.height;
++ pxp_conf->ol_param[0].pixel_fmt =
++ pxp_conf->out_param.pixel_fmt;
++ memcpy(&desc->layer_param.ol_param,
++ &pxp_conf->ol_param[0],
++ sizeof(struct pxp_layer_param));
++ }
++
++ desc = desc->next;
++ }
++
++ vb->state = VIDEOBUF_PREPARED;
++ }
++
++ return 0;
++
++fail:
++ pxp_buf_free(q, buf);
++ return ret;
++}
++
++
++static void pxp_buf_queue(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ struct pxps *pxp = q->priv_data;
++ struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb);
++ struct dma_async_tx_descriptor *txd = buf->txd;
++ struct pxp_channel *pchan = pxp->pxp_channel[0];
++ dma_cookie_t cookie;
++
++ BUG_ON(!irqs_disabled());
++
++ list_add_tail(&vb->queue, &pxp->outq);
++
++ if (!pxp->active) {
++ pxp->active = buf;
++ vb->state = VIDEOBUF_ACTIVE;
++ } else {
++ vb->state = VIDEOBUF_QUEUED;
++ }
++
++ spin_unlock_irq(&pxp->lock);
++
++ cookie = txd->tx_submit(txd);
++ dev_dbg(&pxp->pdev->dev, "Submitted cookie %d DMA 0x%08x\n",
++ cookie, sg_dma_address(&buf->sg[0]));
++ mdelay(5);
++ /* trigger ePxP */
++ dma_async_issue_pending(&pchan->dma_chan);
++
++ spin_lock_irq(&pxp->lock);
++
++ if (cookie >= 0)
++ return;
++
++ /* Submit error */
++ pr_err("%s: Submit error\n", __func__);
++ vb->state = VIDEOBUF_PREPARED;
++
++ list_del_init(&vb->queue);
++
++ if (pxp->active == buf)
++ pxp->active = NULL;
++}
++
++static void pxp_buf_release(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ struct pxps *pxp = q->priv_data;
++ struct pxp_buffer *buf = container_of(vb, struct pxp_buffer, vb);
++ unsigned long flags;
++
++ spin_lock_irqsave(&pxp->lock, flags);
++ if ((vb->state == VIDEOBUF_ACTIVE || vb->state == VIDEOBUF_QUEUED) &&
++ !list_empty(&vb->queue)) {
++ vb->state = VIDEOBUF_ERROR;
++
++ list_del_init(&vb->queue);
++ if (pxp->active == buf)
++ pxp->active = NULL;
++ }
++ spin_unlock_irqrestore(&pxp->lock, flags);
++
++ pxp_buf_free(q, buf);
++}
++
++static struct videobuf_queue_ops pxp_vbq_ops = {
++ .buf_setup = pxp_buf_setup,
++ .buf_prepare = pxp_buf_prepare,
++ .buf_queue = pxp_buf_queue,
++ .buf_release = pxp_buf_release,
++};
++
++static int pxp_querycap(struct file *file, void *fh,
++ struct v4l2_capability *cap)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ memset(cap, 0, sizeof(*cap));
++ strcpy(cap->driver, "pxp");
++ strcpy(cap->card, "pxp");
++ strlcpy(cap->bus_info, dev_name(&pxp->pdev->dev),
++ sizeof(cap->bus_info));
++
++ cap->version = (PXP_DRIVER_MAJOR << 8) + PXP_DRIVER_MINOR;
++
++ cap->capabilities = V4L2_CAP_VIDEO_OUTPUT |
++ V4L2_CAP_VIDEO_OUTPUT_OVERLAY |
++ V4L2_CAP_STREAMING;
++
++ return 0;
++}
++
++static int pxp_g_fbuf(struct file *file, void *priv,
++ struct v4l2_framebuffer *fb)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ memset(fb, 0, sizeof(*fb));
++
++ fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY |
++ V4L2_FBUF_CAP_CHROMAKEY |
++ V4L2_FBUF_CAP_LOCAL_ALPHA |
++ V4L2_FBUF_CAP_GLOBAL_ALPHA;
++
++ if (pxp->global_alpha_state)
++ fb->flags |= V4L2_FBUF_FLAG_GLOBAL_ALPHA;
++ if (pxp->s1_chromakey_state)
++ fb->flags |= V4L2_FBUF_FLAG_CHROMAKEY;
++
++ return 0;
++}
++
++static int pxp_s_fbuf(struct file *file, void *priv,
++ const struct v4l2_framebuffer *fb)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ pxp->overlay_state =
++ (fb->flags & V4L2_FBUF_FLAG_OVERLAY) != 0;
++ pxp->global_alpha_state =
++ (fb->flags & V4L2_FBUF_FLAG_GLOBAL_ALPHA) != 0;
++ pxp->s1_chromakey_state =
++ (fb->flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0;
++
++ pxp->pxp_conf.ol_param[0].combine_enable = pxp->overlay_state;
++ pxp->pxp_conf.ol_param[0].global_alpha_enable = pxp->global_alpha_state;
++
++ return 0;
++}
++
++static int pxp_g_crop(struct file *file, void *fh,
++ struct v4l2_crop *c)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
++ return -EINVAL;
++
++ c->c.left = pxp->pxp_conf.proc_data.drect.left;
++ c->c.top = pxp->pxp_conf.proc_data.drect.top;
++ c->c.width = pxp->pxp_conf.proc_data.drect.width;
++ c->c.height = pxp->pxp_conf.proc_data.drect.height;
++
++ return 0;
++}
++
++static int pxp_s_crop(struct file *file, void *fh,
++ const struct v4l2_crop *c)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int l = c->c.left;
++ int t = c->c.top;
++ int w = c->c.width;
++ int h = c->c.height;
++ int fbw = pxp->fb.fmt.width;
++ int fbh = pxp->fb.fmt.height;
++
++ if (c->type != V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY)
++ return -EINVAL;
++
++ /* Constrain parameters to FB limits */
++ w = min(w, fbw);
++ w = max(w, PXP_MIN_PIX);
++ h = min(h, fbh);
++ h = max(h, PXP_MIN_PIX);
++ if ((l + w) > fbw)
++ l = 0;
++ if ((t + h) > fbh)
++ t = 0;
++
++ /* Round up values to PxP pixel block */
++ l = roundup(l, PXP_MIN_PIX);
++ t = roundup(t, PXP_MIN_PIX);
++ w = roundup(w, PXP_MIN_PIX);
++ h = roundup(h, PXP_MIN_PIX);
++
++ pxp->pxp_conf.proc_data.drect.left = l;
++ pxp->pxp_conf.proc_data.drect.top = t;
++ pxp->pxp_conf.proc_data.drect.width = w;
++ pxp->pxp_conf.proc_data.drect.height = h;
++
++ memset(pxp->outbuf.vaddr, 0x0, pxp->outbuf.size);
++
++ return 0;
++}
++
++static int pxp_queryctrl(struct file *file, void *priv,
++ struct v4l2_queryctrl *qc)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (qc->id && qc->id == pxp_controls[i].id) {
++ memcpy(qc, &(pxp_controls[i]), sizeof(*qc));
++ return 0;
++ }
++
++ return -EINVAL;
++}
++
++static int pxp_g_ctrl(struct file *file, void *priv,
++ struct v4l2_control *vc)
++{
++ int i;
++
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (vc->id == pxp_controls[i].id)
++ return pxp_get_cstate(pxp, vc);
++
++ return -EINVAL;
++}
++
++static int pxp_s_ctrl(struct file *file, void *priv,
++ struct v4l2_control *vc)
++{
++ int i;
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++)
++ if (vc->id == pxp_controls[i].id) {
++ if (vc->value < pxp_controls[i].minimum ||
++ vc->value > pxp_controls[i].maximum)
++ return -ERANGE;
++ return pxp_set_cstate(pxp, vc);
++ }
++
++ memset(pxp->outbuf.vaddr, 0x0, pxp->outbuf.size);
++
++ return -EINVAL;
++}
++
++void pxp_release(struct video_device *vfd)
++{
++ struct pxps *pxp = video_get_drvdata(vfd);
++
++ spin_lock(&pxp->lock);
++ video_device_release(vfd);
++ spin_unlock(&pxp->lock);
++}
++
++static int pxp_open(struct file *file)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret = 0;
++
++ mutex_lock(&pxp->mutex);
++ pxp->users++;
++
++ if (pxp->users > 1) {
++ pxp->users--;
++ ret = -EBUSY;
++ goto out;
++ }
++out:
++ mutex_unlock(&pxp->mutex);
++ if (ret)
++ return ret;
++
++ ret = pxp_set_fbinfo(pxp);
++ if (ret) {
++ dev_err(&pxp->pdev->dev, "failed to call pxp_set_fbinfo\n");
++ return ret;
++ }
++
++ videobuf_queue_dma_contig_init(&pxp->s0_vbq,
++ &pxp_vbq_ops,
++ &pxp->pdev->dev,
++ &pxp->lock,
++ V4L2_BUF_TYPE_VIDEO_OUTPUT,
++ V4L2_FIELD_NONE,
++ sizeof(struct pxp_buffer),
++ pxp,
++ NULL);
++ dev_dbg(&pxp->pdev->dev, "call pxp_open\n");
++
++ return 0;
++}
++
++static int pxp_close(struct file *file)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++
++ pxp_streamoff(file, NULL, V4L2_BUF_TYPE_VIDEO_OUTPUT);
++ videobuf_stop(&pxp->s0_vbq);
++ videobuf_mmap_free(&pxp->s0_vbq);
++ pxp->active = NULL;
++
++ mutex_lock(&pxp->mutex);
++ pxp->users--;
++ mutex_unlock(&pxp->mutex);
++
++ return 0;
++}
++
++static int pxp_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ struct pxps *pxp = video_get_drvdata(video_devdata(file));
++ int ret;
++
++ ret = videobuf_mmap_mapper(&pxp->s0_vbq, vma);
++
++ return ret;
++}
++
++static const struct v4l2_file_operations pxp_fops = {
++ .owner = THIS_MODULE,
++ .open = pxp_open,
++ .release = pxp_close,
++ .unlocked_ioctl = video_ioctl2,
++ .mmap = pxp_mmap,
++};
++
++static const struct v4l2_ioctl_ops pxp_ioctl_ops = {
++ .vidioc_querycap = pxp_querycap,
++
++ .vidioc_reqbufs = pxp_reqbufs,
++ .vidioc_querybuf = pxp_querybuf,
++ .vidioc_qbuf = pxp_qbuf,
++ .vidioc_dqbuf = pxp_dqbuf,
++
++ .vidioc_streamon = pxp_streamon,
++ .vidioc_streamoff = pxp_streamoff,
++
++ .vidioc_enum_output = pxp_enumoutput,
++ .vidioc_g_output = pxp_g_output,
++ .vidioc_s_output = pxp_s_output,
++
++ .vidioc_enum_fmt_vid_out = pxp_enum_fmt_video_output,
++ .vidioc_try_fmt_vid_out = pxp_try_fmt_video_output,
++ .vidioc_g_fmt_vid_out = pxp_g_fmt_video_output,
++ .vidioc_s_fmt_vid_out = pxp_s_fmt_video_output,
++
++ .vidioc_try_fmt_vid_out_overlay = pxp_try_fmt_output_overlay,
++ .vidioc_g_fmt_vid_out_overlay = pxp_g_fmt_output_overlay,
++ .vidioc_s_fmt_vid_out_overlay = pxp_s_fmt_output_overlay,
++
++ .vidioc_g_fbuf = pxp_g_fbuf,
++ .vidioc_s_fbuf = pxp_s_fbuf,
++
++ .vidioc_g_crop = pxp_g_crop,
++ .vidioc_s_crop = pxp_s_crop,
++
++ .vidioc_queryctrl = pxp_queryctrl,
++ .vidioc_g_ctrl = pxp_g_ctrl,
++ .vidioc_s_ctrl = pxp_s_ctrl,
++};
++
++static const struct video_device pxp_template = {
++ .name = "PxP",
++ .vfl_type = V4L2_CAP_VIDEO_OUTPUT |
++ V4L2_CAP_VIDEO_OVERLAY |
++ V4L2_CAP_STREAMING,
++ .vfl_dir = VFL_DIR_TX,
++ .fops = &pxp_fops,
++ .release = pxp_release,
++ .minor = -1,
++ .ioctl_ops = &pxp_ioctl_ops,
++};
++
++static const struct of_device_id imx_pxpv4l2_dt_ids[] = {
++ { .compatible = "fsl,imx6sl-pxp-v4l2", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_pxpv4l2_dt_ids);
++
++static int pxp_probe(struct platform_device *pdev)
++{
++ struct pxps *pxp;
++ struct v4l2_device *v4l2_dev;
++ int err = 0;
++
++ pxp = kzalloc(sizeof(*pxp), GFP_KERNEL);
++ if (!pxp) {
++ dev_err(&pdev->dev, "failed to allocate control object\n");
++ err = -ENOMEM;
++ goto exit;
++ }
++
++ dev_set_drvdata(&pdev->dev, pxp);
++
++ v4l2_dev = kzalloc(sizeof(*v4l2_dev), GFP_KERNEL);
++ if (!v4l2_dev) {
++ dev_err(&pdev->dev, "failed to allocate v4l2_dev structure\n");
++ err = -ENOMEM;
++ goto freeirq;
++ }
++
++ err = v4l2_device_register(&pdev->dev, v4l2_dev);
++ if (err) {
++ dev_err(&pdev->dev, "register v4l2 device failed\n");
++ goto freev4l2;
++ }
++
++ INIT_LIST_HEAD(&pxp->outq);
++ spin_lock_init(&pxp->lock);
++ mutex_init(&pxp->mutex);
++
++ pxp->pdev = pdev;
++
++ pxp->vdev = video_device_alloc();
++ if (!pxp->vdev) {
++ dev_err(&pdev->dev, "video_device_alloc() failed\n");
++ err = -ENOMEM;
++ goto relv4l2;
++ }
++
++ memcpy(pxp->vdev, &pxp_template, sizeof(pxp_template));
++ pxp->vdev->v4l2_dev = v4l2_dev;
++ video_set_drvdata(pxp->vdev, pxp);
++
++ err = video_register_device(pxp->vdev, VFL_TYPE_GRABBER, video_nr);
++ if (err) {
++ dev_err(&pdev->dev, "failed to register video device\n");
++ goto freevdev;
++ }
++
++ dev_info(&pdev->dev, "initialized\n");
++
++exit:
++ return err;
++
++freevdev:
++ video_device_release(pxp->vdev);
++relv4l2:
++ v4l2_device_unregister(v4l2_dev);
++freev4l2:
++ kfree(v4l2_dev);
++freeirq:
++ kfree(pxp);
++
++ return err;
++}
++
++static int pxp_remove(struct platform_device *pdev)
++{
++ struct pxps *pxp = platform_get_drvdata(pdev);
++ struct v4l2_device *v4l2_dev = pxp->vdev->v4l2_dev;
++
++ video_unregister_device(pxp->vdev);
++ video_device_release(pxp->vdev);
++ v4l2_device_unregister(v4l2_dev);
++ kfree(v4l2_dev);
++
++ free_dma_buf(pxp, &pxp->outbuf);
++
++ kfree(pxp);
++
++ return 0;
++}
++
++static struct platform_driver pxp_driver = {
++ .driver = {
++ .name = PXP_DRIVER_NAME,
++ .of_match_table = of_match_ptr(imx_pxpv4l2_dt_ids),
++ },
++ .probe = pxp_probe,
++ .remove = pxp_remove,
++};
++
++module_platform_driver(pxp_driver);
++
++module_param(video_nr, int, 0444);
++MODULE_DESCRIPTION("MXC PxP V4L2 driver");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h linux-3.14.72/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h
+--- linux-3.14.72.orig/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/output/mxc_pxp_v4l2.h 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,87 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X PxP driver
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#ifndef _MXC_PXP_V4L2_H
++#define _MXC_PXP_V4L2_H
++
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++
++struct pxp_buffer {
++ /* Must be first! */
++ struct videobuf_buffer vb;
++
++ /* One descriptor per scatterlist (per frame) */
++ struct dma_async_tx_descriptor *txd;
++
++ struct scatterlist sg[3];
++};
++
++struct dma_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ size_t size;
++};
++
++struct pxps {
++ struct platform_device *pdev;
++
++ spinlock_t lock;
++ struct mutex mutex;
++ int users;
++
++ struct video_device *vdev;
++
++ struct videobuf_queue s0_vbq;
++ struct pxp_buffer *active;
++ struct list_head outq;
++ struct pxp_channel *pxp_channel[1]; /* We need 1 channel */
++ struct pxp_config_data pxp_conf;
++ struct dma_mem outbuf;
++
++ int output;
++
++ /* Current S0 configuration */
++ struct pxp_data_format *s0_fmt;
++
++ struct fb_info *fbi;
++ struct v4l2_framebuffer fb;
++
++ /* Output overlay support */
++ int overlay_state;
++ int global_alpha_state;
++ u8 global_alpha;
++ int s1_chromakey_state;
++ u32 s1_chromakey;
++
++ int fb_blank;
++};
++
++struct pxp_data_format {
++ char *name;
++ unsigned int bpp;
++ u32 fourcc;
++ enum v4l2_colorspace colorspace;
++};
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/output/mxc_vout.c linux-3.14.72/drivers/media/platform/mxc/output/mxc_vout.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/output/mxc_vout.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/output/mxc_vout.c 2016-06-19 22:11:55.185147881 +0200
+@@ -0,0 +1,2277 @@
++/*
++ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/console.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/mxc_v4l2.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/types.h>
++#include <linux/videodev2.h>
++#include <linux/vmalloc.h>
++
++#include <media/videobuf-dma-contig.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++
++#define UYVY_BLACK (0x00800080)
++#define RGB_BLACK (0x0)
++#define UV_BLACK (0x80)
++#define Y_BLACK (0x0)
++
++#define MAX_FB_NUM 6
++#define FB_BUFS 3
++#define VDOA_FB_BUFS (FB_BUFS - 1)
++#define VALID_HEIGHT_1080P (1080)
++#define FRAME_HEIGHT_1080P (1088)
++#define FRAME_WIDTH_1080P (1920)
++#define CHECK_TILED_1080P_DISPLAY(vout) \
++ ((((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) || \
++ ((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12F)) &&\
++ ((vout)->task.input.width == FRAME_WIDTH_1080P) && \
++ ((vout)->task.input.height == FRAME_HEIGHT_1080P) && \
++ ((vout)->task.input.crop.w == FRAME_WIDTH_1080P) && \
++ (((vout)->task.input.crop.h == FRAME_HEIGHT_1080P) || \
++ ((vout)->task.input.crop.h == VALID_HEIGHT_1080P)) && \
++ ((vout)->task.output.width == FRAME_WIDTH_1080P) && \
++ ((vout)->task.output.height == VALID_HEIGHT_1080P) && \
++ ((vout)->task.output.crop.w == FRAME_WIDTH_1080P) && \
++ ((vout)->task.output.crop.h == VALID_HEIGHT_1080P))
++#define CHECK_TILED_1080P_STREAM(vout) \
++ ((((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) || \
++ ((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12F)) &&\
++ ((vout)->task.input.width == FRAME_WIDTH_1080P) && \
++ ((vout)->task.input.crop.w == FRAME_WIDTH_1080P) && \
++ ((vout)->task.input.height == FRAME_HEIGHT_1080P) && \
++ ((vout)->task.input.crop.h == FRAME_HEIGHT_1080P))
++#define IS_PLANAR_PIXEL_FORMAT(format) \
++ (format == IPU_PIX_FMT_NV12 || \
++ format == IPU_PIX_FMT_YUV420P2 || \
++ format == IPU_PIX_FMT_YUV420P || \
++ format == IPU_PIX_FMT_YVU420P || \
++ format == IPU_PIX_FMT_YUV422P || \
++ format == IPU_PIX_FMT_YVU422P || \
++ format == IPU_PIX_FMT_YUV444P)
++
++#define NSEC_PER_FRAME_30FPS (33333333)
++
++struct mxc_vout_fb {
++ char *name;
++ int ipu_id;
++ struct v4l2_rect crop_bounds;
++ unsigned int disp_fmt;
++ bool disp_support_csc;
++ bool disp_support_windows;
++};
++
++struct dma_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ size_t size;
++};
++
++struct mxc_vout_output {
++ int open_cnt;
++ struct fb_info *fbi;
++ unsigned long fb_smem_start;
++ unsigned long fb_smem_len;
++ struct video_device *vfd;
++ struct mutex mutex;
++ struct mutex task_lock;
++ enum v4l2_buf_type type;
++
++ struct videobuf_queue vbq;
++ spinlock_t vbq_lock;
++
++ struct list_head queue_list;
++ struct list_head active_list;
++
++ struct v4l2_rect crop_bounds;
++ unsigned int disp_fmt;
++ struct mxcfb_pos win_pos;
++ bool disp_support_windows;
++ bool disp_support_csc;
++
++ bool fmt_init;
++ bool release;
++ bool linear_bypass_pp;
++ bool vdoa_1080p;
++ bool tiled_bypass_pp;
++ struct v4l2_rect in_rect;
++ struct ipu_task task;
++ struct ipu_task vdoa_task;
++ struct dma_mem vdoa_work;
++ struct dma_mem vdoa_output[VDOA_FB_BUFS];
++
++ bool timer_stop;
++ struct hrtimer timer;
++ struct workqueue_struct *v4l_wq;
++ struct work_struct disp_work;
++ unsigned long frame_count;
++ unsigned long vdi_frame_cnt;
++ ktime_t start_ktime;
++
++ int ctrl_rotate;
++ int ctrl_vflip;
++ int ctrl_hflip;
++
++ dma_addr_t disp_bufs[FB_BUFS];
++
++ struct videobuf_buffer *pre1_vb;
++ struct videobuf_buffer *pre2_vb;
++};
++
++struct mxc_vout_dev {
++ struct device *dev;
++ struct v4l2_device v4l2_dev;
++ struct mxc_vout_output *out[MAX_FB_NUM];
++ int out_num;
++};
++
++/* Driver Configuration macros */
++#define VOUT_NAME "mxc_vout"
++
++/* Variables configurable through module params*/
++static int debug;
++static int vdi_rate_double;
++static int video_nr = 16;
++
++/* Module parameters */
++module_param(video_nr, int, S_IRUGO);
++MODULE_PARM_DESC(video_nr, "video device numbers");
++module_param(debug, int, 0600);
++MODULE_PARM_DESC(debug, "Debug level (0-1)");
++module_param(vdi_rate_double, int, 0600);
++MODULE_PARM_DESC(vdi_rate_double, "vdi frame rate double on/off");
++
++static const struct v4l2_fmtdesc mxc_formats[] = {
++ {
++ .description = "RGB565",
++ .pixelformat = V4L2_PIX_FMT_RGB565,
++ },
++ {
++ .description = "BGR24",
++ .pixelformat = V4L2_PIX_FMT_BGR24,
++ },
++ {
++ .description = "RGB24",
++ .pixelformat = V4L2_PIX_FMT_RGB24,
++ },
++ {
++ .description = "RGB32",
++ .pixelformat = V4L2_PIX_FMT_RGB32,
++ },
++ {
++ .description = "BGR32",
++ .pixelformat = V4L2_PIX_FMT_BGR32,
++ },
++ {
++ .description = "NV12",
++ .pixelformat = V4L2_PIX_FMT_NV12,
++ },
++ {
++ .description = "UYVY",
++ .pixelformat = V4L2_PIX_FMT_UYVY,
++ },
++ {
++ .description = "YUYV",
++ .pixelformat = V4L2_PIX_FMT_YUYV,
++ },
++ {
++ .description = "YUV422 planar",
++ .pixelformat = V4L2_PIX_FMT_YUV422P,
++ },
++ {
++ .description = "YUV444",
++ .pixelformat = V4L2_PIX_FMT_YUV444,
++ },
++ {
++ .description = "YUV420",
++ .pixelformat = V4L2_PIX_FMT_YUV420,
++ },
++ {
++ .description = "YVU420",
++ .pixelformat = V4L2_PIX_FMT_YVU420,
++ },
++ {
++ .description = "TILED NV12P",
++ .pixelformat = IPU_PIX_FMT_TILED_NV12,
++ },
++ {
++ .description = "TILED NV12F",
++ .pixelformat = IPU_PIX_FMT_TILED_NV12F,
++ },
++ {
++ .description = "YUV444 planar",
++ .pixelformat = IPU_PIX_FMT_YUV444P,
++ },
++};
++
++#define NUM_MXC_VOUT_FORMATS (ARRAY_SIZE(mxc_formats))
++
++#define DEF_INPUT_WIDTH 320
++#define DEF_INPUT_HEIGHT 240
++
++static int mxc_vidioc_streamoff(struct file *file, void *fh,
++ enum v4l2_buf_type i);
++
++static struct mxc_vout_fb g_fb_setting[MAX_FB_NUM];
++static int config_disp_output(struct mxc_vout_output *vout);
++static void release_disp_output(struct mxc_vout_output *vout);
++
++static unsigned int get_frame_size(struct mxc_vout_output *vout)
++{
++ unsigned int size;
++
++ if (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format)
++ size = TILED_NV12_FRAME_SIZE(vout->task.input.width,
++ vout->task.input.height);
++ else if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) {
++ size = TILED_NV12_FRAME_SIZE(vout->task.input.width,
++ vout->task.input.height/2);
++ size *= 2;
++ } else
++ size = vout->task.input.width * vout->task.input.height *
++ fmt_to_bpp(vout->task.input.format)/8;
++
++ return size;
++}
++
++static void free_dma_buf(struct mxc_vout_output *vout, struct dma_mem *buf)
++{
++ dma_free_coherent(vout->vbq.dev, buf->size, buf->vaddr, buf->paddr);
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "free dma size:0x%x, paddr:0x%x\n",
++ buf->size, buf->paddr);
++ memset(buf, 0, sizeof(*buf));
++}
++
++static int alloc_dma_buf(struct mxc_vout_output *vout, struct dma_mem *buf)
++{
++
++ buf->vaddr = dma_alloc_coherent(vout->vbq.dev, buf->size, &buf->paddr,
++ GFP_DMA | GFP_KERNEL);
++ if (!buf->vaddr) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "cannot get dma buf size:0x%x\n", buf->size);
++ return -ENOMEM;
++ }
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "alloc dma buf size:0x%x, paddr:0x%x\n", buf->size, buf->paddr);
++ return 0;
++}
++
++static ipu_channel_t get_ipu_channel(struct fb_info *fbi)
++{
++ ipu_channel_t ipu_ch = CHAN_NONE;
++ mm_segment_t old_fs;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN,
++ (unsigned long)&ipu_ch);
++ set_fs(old_fs);
++ }
++
++ return ipu_ch;
++}
++
++static unsigned int get_ipu_fmt(struct fb_info *fbi)
++{
++ mm_segment_t old_fs;
++ unsigned int fb_fmt;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_DIFMT,
++ (unsigned long)&fb_fmt);
++ set_fs(old_fs);
++ }
++
++ return fb_fmt;
++}
++
++static void update_display_setting(void)
++{
++ int i;
++ struct fb_info *fbi;
++ struct v4l2_rect bg_crop_bounds[2];
++
++ for (i = 0; i < num_registered_fb; i++) {
++ fbi = registered_fb[i];
++
++ memset(&g_fb_setting[i], 0, sizeof(struct mxc_vout_fb));
++
++ if (!strncmp(fbi->fix.id, "DISP3", 5))
++ g_fb_setting[i].ipu_id = 0;
++ else
++ g_fb_setting[i].ipu_id = 1;
++
++ g_fb_setting[i].name = fbi->fix.id;
++ g_fb_setting[i].crop_bounds.left = 0;
++ g_fb_setting[i].crop_bounds.top = 0;
++ g_fb_setting[i].crop_bounds.width = fbi->var.xres;
++ g_fb_setting[i].crop_bounds.height = fbi->var.yres;
++ g_fb_setting[i].disp_fmt = get_ipu_fmt(fbi);
++
++ if (get_ipu_channel(fbi) == MEM_BG_SYNC) {
++ bg_crop_bounds[g_fb_setting[i].ipu_id] =
++ g_fb_setting[i].crop_bounds;
++ g_fb_setting[i].disp_support_csc = true;
++ } else if (get_ipu_channel(fbi) == MEM_FG_SYNC) {
++ g_fb_setting[i].disp_support_csc = true;
++ g_fb_setting[i].disp_support_windows = true;
++ }
++ }
++
++ for (i = 0; i < num_registered_fb; i++) {
++ fbi = registered_fb[i];
++
++ if (get_ipu_channel(fbi) == MEM_FG_SYNC)
++ g_fb_setting[i].crop_bounds =
++ bg_crop_bounds[g_fb_setting[i].ipu_id];
++ }
++}
++
++/* called after g_fb_setting filled by update_display_setting */
++static int update_setting_from_fbi(struct mxc_vout_output *vout,
++ struct fb_info *fbi)
++{
++ int i;
++ bool found = false;
++
++ for (i = 0; i < MAX_FB_NUM; i++) {
++ if (g_fb_setting[i].name) {
++ if (!strcmp(fbi->fix.id, g_fb_setting[i].name)) {
++ vout->crop_bounds = g_fb_setting[i].crop_bounds;
++ vout->disp_fmt = g_fb_setting[i].disp_fmt;
++ vout->disp_support_csc =
++ g_fb_setting[i].disp_support_csc;
++ vout->disp_support_windows =
++ g_fb_setting[i].disp_support_windows;
++ found = true;
++ break;
++ }
++ }
++ }
++
++ if (!found) {
++ v4l2_err(vout->vfd->v4l2_dev, "can not find output\n");
++ return -EINVAL;
++ }
++ strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name));
++
++ memset(&vout->task, 0, sizeof(struct ipu_task));
++
++ vout->task.input.width = DEF_INPUT_WIDTH;
++ vout->task.input.height = DEF_INPUT_HEIGHT;
++ vout->task.input.crop.pos.x = 0;
++ vout->task.input.crop.pos.y = 0;
++ vout->task.input.crop.w = DEF_INPUT_WIDTH;
++ vout->task.input.crop.h = DEF_INPUT_HEIGHT;
++
++ vout->task.output.width = vout->crop_bounds.width;
++ vout->task.output.height = vout->crop_bounds.height;
++ vout->task.output.crop.pos.x = 0;
++ vout->task.output.crop.pos.y = 0;
++ vout->task.output.crop.w = vout->crop_bounds.width;
++ vout->task.output.crop.h = vout->crop_bounds.height;
++ if (colorspaceofpixel(vout->disp_fmt) == YUV_CS)
++ vout->task.output.format = IPU_PIX_FMT_UYVY;
++ else
++ vout->task.output.format = IPU_PIX_FMT_RGB565;
++
++ return 0;
++}
++
++static inline unsigned long get_jiffies(struct timeval *t)
++{
++ struct timeval cur;
++
++ if (t->tv_usec >= 1000000) {
++ t->tv_sec += t->tv_usec / 1000000;
++ t->tv_usec = t->tv_usec % 1000000;
++ }
++
++ do_gettimeofday(&cur);
++ if ((t->tv_sec < cur.tv_sec)
++ || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec)))
++ return jiffies;
++
++ if (t->tv_usec < cur.tv_usec) {
++ cur.tv_sec = t->tv_sec - cur.tv_sec - 1;
++ cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec;
++ } else {
++ cur.tv_sec = t->tv_sec - cur.tv_sec;
++ cur.tv_usec = t->tv_usec - cur.tv_usec;
++ }
++
++ return jiffies + timeval_to_jiffies(&cur);
++}
++
++static bool deinterlace_3_field(struct mxc_vout_output *vout)
++{
++ return (vout->task.input.deinterlace.enable &&
++ (vout->task.input.deinterlace.motion != HIGH_MOTION));
++}
++
++static int set_field_fmt(struct mxc_vout_output *vout, enum v4l2_field field)
++{
++ struct ipu_deinterlace *deinterlace = &vout->task.input.deinterlace;
++
++ switch (field) {
++ /* Images are in progressive format, not interlaced */
++ case V4L2_FIELD_NONE:
++ case V4L2_FIELD_ANY:
++ deinterlace->enable = false;
++ deinterlace->field_fmt = 0;
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "Progressive frame.\n");
++ break;
++ case V4L2_FIELD_INTERLACED_TB:
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "Enable deinterlace TB.\n");
++ deinterlace->enable = true;
++ deinterlace->field_fmt = IPU_DEINTERLACE_FIELD_TOP;
++ break;
++ case V4L2_FIELD_INTERLACED_BT:
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "Enable deinterlace BT.\n");
++ deinterlace->enable = true;
++ deinterlace->field_fmt = IPU_DEINTERLACE_FIELD_BOTTOM;
++ break;
++ default:
++ v4l2_err(vout->vfd->v4l2_dev,
++ "field format:%d not supported yet!\n", field);
++ return -EINVAL;
++ }
++
++ if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) {
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "tiled fmt enable deinterlace.\n");
++ deinterlace->enable = true;
++ }
++
++ if (deinterlace->enable && vdi_rate_double)
++ deinterlace->field_fmt |= IPU_DEINTERLACE_RATE_EN;
++
++ return 0;
++}
++
++static bool is_pp_bypass(struct mxc_vout_output *vout)
++{
++ if ((IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format))
++ return false;
++ if ((vout->task.input.width == vout->task.output.width) &&
++ (vout->task.input.height == vout->task.output.height) &&
++ (vout->task.input.crop.w == vout->task.output.crop.w) &&
++ (vout->task.input.crop.h == vout->task.output.crop.h) &&
++ (vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) &&
++ !vout->task.input.deinterlace.enable) {
++ if (vout->disp_support_csc)
++ return true;
++ else if (!need_csc(vout->task.input.format, vout->disp_fmt))
++ return true;
++ /*
++ * input crop show to full output which can show based on
++ * xres_virtual/yres_virtual
++ */
++ } else if ((vout->task.input.crop.w == vout->task.output.crop.w) &&
++ (vout->task.output.crop.w == vout->task.output.width) &&
++ (vout->task.input.crop.h == vout->task.output.crop.h) &&
++ (vout->task.output.crop.h ==
++ vout->task.output.height) &&
++ (vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) &&
++ !vout->task.input.deinterlace.enable) {
++ if (vout->disp_support_csc)
++ return true;
++ else if (!need_csc(vout->task.input.format, vout->disp_fmt))
++ return true;
++ }
++ return false;
++}
++
++static void setup_buf_timer(struct mxc_vout_output *vout,
++ struct videobuf_buffer *vb)
++{
++ ktime_t expiry_time, now;
++
++ /* if timestamp is 0, then default to 30fps */
++ if ((vb->ts.tv_sec == 0) && (vb->ts.tv_usec == 0))
++ expiry_time = ktime_add_ns(vout->start_ktime,
++ NSEC_PER_FRAME_30FPS * vout->frame_count);
++ else
++ expiry_time = timeval_to_ktime(vb->ts);
++
++ now = hrtimer_cb_get_time(&vout->timer);
++ if ((now.tv64 > expiry_time.tv64)) {
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "warning: timer timeout already expired.\n");
++ expiry_time = now;
++ }
++
++ hrtimer_start(&vout->timer, expiry_time, HRTIMER_MODE_ABS);
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "timer handler next "
++ "schedule: %lldnsecs\n", expiry_time.tv64);
++}
++
++static int show_buf(struct mxc_vout_output *vout, int idx,
++ struct ipu_pos *ipos)
++{
++ struct fb_info *fbi = vout->fbi;
++ struct fb_var_screeninfo var;
++ int ret;
++ u32 fb_base = 0;
++
++ memcpy(&var, &fbi->var, sizeof(var));
++
++ if (vout->linear_bypass_pp || vout->tiled_bypass_pp) {
++ /*
++ * crack fb base
++ * NOTE: should not do other fb operation during v4l2
++ */
++ console_lock();
++ fb_base = fbi->fix.smem_start;
++ fbi->fix.smem_start = vout->task.output.paddr;
++ fbi->var.yoffset = ipos->y + 1;
++ var.xoffset = ipos->x;
++ var.yoffset = ipos->y;
++ var.vmode |= FB_VMODE_YWRAP;
++ ret = fb_pan_display(fbi, &var);
++ fbi->fix.smem_start = fb_base;
++ console_unlock();
++ } else {
++ console_lock();
++ var.yoffset = idx * fbi->var.yres;
++ var.vmode &= ~FB_VMODE_YWRAP;
++ ret = fb_pan_display(fbi, &var);
++ console_unlock();
++ }
++
++ return ret;
++}
++
++static void disp_work_func(struct work_struct *work)
++{
++ struct mxc_vout_output *vout =
++ container_of(work, struct mxc_vout_output, disp_work);
++ struct videobuf_queue *q = &vout->vbq;
++ struct videobuf_buffer *vb, *vb_next = NULL;
++ unsigned long flags = 0;
++ struct ipu_pos ipos;
++ int ret = 0;
++ u32 in_fmt = 0, in_width = 0, in_height = 0;
++ u32 vdi_cnt = 0;
++ u32 vdi_frame;
++ u32 index = 0;
++ u32 ocrop_h = 0;
++ u32 o_height = 0;
++ u32 tiled_interlaced = 0;
++ bool tiled_fmt = false;
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work begin one frame\n");
++
++ spin_lock_irqsave(q->irqlock, flags);
++
++ if (list_empty(&vout->active_list)) {
++ v4l2_warn(vout->vfd->v4l2_dev,
++ "no entry in active_list, should not be here\n");
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return;
++ }
++
++ vb = list_first_entry(&vout->active_list,
++ struct videobuf_buffer, queue);
++ ret = set_field_fmt(vout, vb->field);
++ if (ret < 0) {
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return;
++ }
++ if (deinterlace_3_field(vout)) {
++ if (list_is_singular(&vout->active_list)) {
++ if (list_empty(&vout->queue_list)) {
++ vout->timer_stop = true;
++ spin_unlock_irqrestore(q->irqlock, flags);
++ v4l2_warn(vout->vfd->v4l2_dev,
++ "no enough entry for 3 fields "
++ "deinterlacer\n");
++ return;
++ }
++
++ /*
++ * We need to use the next vb even if it is
++ * not on the active list.
++ */
++ vb_next = list_first_entry(&vout->queue_list,
++ struct videobuf_buffer, queue);
++ } else
++ vb_next = list_first_entry(vout->active_list.next,
++ struct videobuf_buffer, queue);
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "cur field_fmt:%d, next field_fmt:%d.\n",
++ vb->field, vb_next->field);
++ /* repeat the last field during field format changing */
++ if ((vb->field != vb_next->field) &&
++ (vb_next->field != V4L2_FIELD_NONE))
++ vb_next = vb;
++ }
++
++ spin_unlock_irqrestore(q->irqlock, flags);
++
++vdi_frame_rate_double:
++ mutex_lock(&vout->task_lock);
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "v4l2 frame_cnt:%ld, vb_field:%d, fmt:%d\n",
++ vout->frame_count, vb->field,
++ vout->task.input.deinterlace.field_fmt);
++ if (vb->memory == V4L2_MEMORY_USERPTR)
++ vout->task.input.paddr = vb->baddr;
++ else
++ vout->task.input.paddr = videobuf_to_dma_contig(vb);
++
++ if (vout->task.input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN)
++ index = vout->vdi_frame_cnt % FB_BUFS;
++ else
++ index = vout->frame_count % FB_BUFS;
++ if (vout->linear_bypass_pp) {
++ vout->task.output.paddr = vout->task.input.paddr;
++ ipos.x = vout->task.input.crop.pos.x;
++ ipos.y = vout->task.input.crop.pos.y;
++ } else {
++ if (deinterlace_3_field(vout)) {
++ if (vb->memory == V4L2_MEMORY_USERPTR)
++ vout->task.input.paddr_n = vb_next->baddr;
++ else
++ vout->task.input.paddr_n =
++ videobuf_to_dma_contig(vb_next);
++ }
++ vout->task.output.paddr = vout->disp_bufs[index];
++ if (vout->vdoa_1080p) {
++ o_height = vout->task.output.height;
++ ocrop_h = vout->task.output.crop.h;
++ vout->task.output.height = FRAME_HEIGHT_1080P;
++ vout->task.output.crop.h = FRAME_HEIGHT_1080P;
++ }
++ tiled_fmt =
++ (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format);
++ if (vout->tiled_bypass_pp) {
++ ipos.x = vout->task.input.crop.pos.x;
++ ipos.y = vout->task.input.crop.pos.y;
++ } else if (tiled_fmt) {
++ vout->vdoa_task.input.paddr = vout->task.input.paddr;
++ if (deinterlace_3_field(vout))
++ vout->vdoa_task.input.paddr_n =
++ vout->task.input.paddr_n;
++ vout->vdoa_task.output.paddr = vout->vdoa_work.paddr;
++ ret = ipu_queue_task(&vout->vdoa_task);
++ if (ret < 0) {
++ mutex_unlock(&vout->task_lock);
++ goto err;
++ }
++ vout->task.input.paddr = vout->vdoa_task.output.paddr;
++ in_fmt = vout->task.input.format;
++ in_width = vout->task.input.width;
++ in_height = vout->task.input.height;
++ vout->task.input.format = vout->vdoa_task.output.format;
++ vout->task.input.width = vout->vdoa_task.output.width;
++ vout->task.input.height = vout->vdoa_task.output.height;
++ if (vout->task.input.deinterlace.enable) {
++ tiled_interlaced = 1;
++ vout->task.input.deinterlace.enable = 0;
++ }
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "tiled queue task\n");
++ }
++ ret = ipu_queue_task(&vout->task);
++ if ((!vout->tiled_bypass_pp) && tiled_fmt) {
++ vout->task.input.format = in_fmt;
++ vout->task.input.width = in_width;
++ vout->task.input.height = in_height;
++ }
++ if (tiled_interlaced)
++ vout->task.input.deinterlace.enable = 1;
++ if (ret < 0) {
++ mutex_unlock(&vout->task_lock);
++ goto err;
++ }
++ if (vout->vdoa_1080p) {
++ vout->task.output.crop.h = ocrop_h;
++ vout->task.output.height = o_height;
++ }
++ }
++
++ mutex_unlock(&vout->task_lock);
++
++ ret = show_buf(vout, index, &ipos);
++ if (ret < 0)
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "show buf with ret %d\n", ret);
++
++ if (vout->task.input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN) {
++ vdi_frame = vout->task.input.deinterlace.field_fmt
++ & IPU_DEINTERLACE_RATE_FRAME1;
++ if (vdi_frame)
++ vout->task.input.deinterlace.field_fmt &=
++ ~IPU_DEINTERLACE_RATE_FRAME1;
++ else
++ vout->task.input.deinterlace.field_fmt |=
++ IPU_DEINTERLACE_RATE_FRAME1;
++ vout->vdi_frame_cnt++;
++ vdi_cnt++;
++ if (vdi_cnt < IPU_DEINTERLACE_MAX_FRAME)
++ goto vdi_frame_rate_double;
++ }
++ spin_lock_irqsave(q->irqlock, flags);
++
++ list_del(&vb->queue);
++
++ /*
++ * The videobuf before the last one has been shown. Set
++ * VIDEOBUF_DONE state here to avoid tearing issue in ic bypass
++ * case, which makes sure a buffer being shown will not be
++ * dequeued to be overwritten. It also brings side-effect that
++ * the last 2 buffers can not be dequeued correctly, apps need
++ * to take care of it.
++ */
++ if (vout->pre2_vb) {
++ vout->pre2_vb->state = VIDEOBUF_DONE;
++ wake_up_interruptible(&vout->pre2_vb->done);
++ vout->pre2_vb = NULL;
++ }
++
++ if (vout->linear_bypass_pp) {
++ vout->pre2_vb = vout->pre1_vb;
++ vout->pre1_vb = vb;
++ } else {
++ if (vout->pre1_vb) {
++ vout->pre1_vb->state = VIDEOBUF_DONE;
++ wake_up_interruptible(&vout->pre1_vb->done);
++ vout->pre1_vb = NULL;
++ }
++ vb->state = VIDEOBUF_DONE;
++ wake_up_interruptible(&vb->done);
++ }
++
++ vout->frame_count++;
++
++ /* pick next queue buf to setup timer */
++ if (list_empty(&vout->queue_list))
++ vout->timer_stop = true;
++ else {
++ vb = list_first_entry(&vout->queue_list,
++ struct videobuf_buffer, queue);
++ setup_buf_timer(vout, vb);
++ }
++
++ spin_unlock_irqrestore(q->irqlock, flags);
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work finish one frame\n");
++
++ return;
++err:
++ v4l2_err(vout->vfd->v4l2_dev, "display work fail ret = %d\n", ret);
++ vout->timer_stop = true;
++ vb->state = VIDEOBUF_ERROR;
++ return;
++}
++
++static enum hrtimer_restart mxc_vout_timer_handler(struct hrtimer *timer)
++{
++ struct mxc_vout_output *vout = container_of(timer,
++ struct mxc_vout_output,
++ timer);
++ struct videobuf_queue *q = &vout->vbq;
++ struct videobuf_buffer *vb;
++ unsigned long flags = 0;
++
++ spin_lock_irqsave(q->irqlock, flags);
++
++ /*
++ * put first queued entry into active, if previous entry did not
++ * finish, setup current entry's timer again.
++ */
++ if (list_empty(&vout->queue_list)) {
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return HRTIMER_NORESTART;
++ }
++
++ /* move videobuf from queued list to active list */
++ vb = list_first_entry(&vout->queue_list,
++ struct videobuf_buffer, queue);
++ list_del(&vb->queue);
++ list_add_tail(&vb->queue, &vout->active_list);
++
++ if (queue_work(vout->v4l_wq, &vout->disp_work) == 0) {
++ v4l2_warn(vout->vfd->v4l2_dev,
++ "disp work was in queue already, queue buf again next time\n");
++ list_del(&vb->queue);
++ list_add(&vb->queue, &vout->queue_list);
++ spin_unlock_irqrestore(q->irqlock, flags);
++ return HRTIMER_NORESTART;
++ }
++
++ vb->state = VIDEOBUF_ACTIVE;
++
++ spin_unlock_irqrestore(q->irqlock, flags);
++
++ return HRTIMER_NORESTART;
++}
++
++/* Video buffer call backs */
++
++/*
++ * Buffer setup function is called by videobuf layer when REQBUF ioctl is
++ * called. This is used to setup buffers and return size and count of
++ * buffers allocated. After the call to this buffer, videobuf layer will
++ * setup buffer queue depending on the size and count of buffers
++ */
++static int mxc_vout_buffer_setup(struct videobuf_queue *q, unsigned int *count,
++ unsigned int *size)
++{
++ struct mxc_vout_output *vout = q->priv_data;
++ unsigned int frame_size;
++
++ if (!vout)
++ return -EINVAL;
++
++ if (V4L2_BUF_TYPE_VIDEO_OUTPUT != q->type)
++ return -EINVAL;
++
++ frame_size = get_frame_size(vout);
++ *size = PAGE_ALIGN(frame_size);
++
++ return 0;
++}
++
++/*
++ * This function will be called when VIDIOC_QBUF ioctl is called.
++ * It prepare buffers before give out for the display. This function
++ * converts user space virtual address into physical address if userptr memory
++ * exchange mechanism is used.
++ */
++static int mxc_vout_buffer_prepare(struct videobuf_queue *q,
++ struct videobuf_buffer *vb,
++ enum v4l2_field field)
++{
++ vb->state = VIDEOBUF_PREPARED;
++ return 0;
++}
++
++/*
++ * Buffer queue funtion will be called from the videobuf layer when _QBUF
++ * ioctl is called. It is used to enqueue buffer, which is ready to be
++ * displayed.
++ * This function is protected by q->irqlock.
++ */
++static void mxc_vout_buffer_queue(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ struct mxc_vout_output *vout = q->priv_data;
++ struct videobuf_buffer *active_vb;
++
++ list_add_tail(&vb->queue, &vout->queue_list);
++ vb->state = VIDEOBUF_QUEUED;
++
++ if (vout->timer_stop) {
++ if (deinterlace_3_field(vout) &&
++ !list_empty(&vout->active_list)) {
++ active_vb = list_first_entry(&vout->active_list,
++ struct videobuf_buffer, queue);
++ setup_buf_timer(vout, active_vb);
++ } else {
++ setup_buf_timer(vout, vb);
++ }
++ vout->timer_stop = false;
++ }
++}
++
++/*
++ * Buffer release function is called from videobuf layer to release buffer
++ * which are already allocated
++ */
++static void mxc_vout_buffer_release(struct videobuf_queue *q,
++ struct videobuf_buffer *vb)
++{
++ vb->state = VIDEOBUF_NEEDS_INIT;
++}
++
++static int mxc_vout_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ int ret;
++ struct mxc_vout_output *vout = file->private_data;
++
++ if (!vout)
++ return -ENODEV;
++
++ ret = videobuf_mmap_mapper(&vout->vbq, vma);
++ if (ret < 0)
++ v4l2_err(vout->vfd->v4l2_dev,
++ "offset invalid [offset=0x%lx]\n",
++ (vma->vm_pgoff << PAGE_SHIFT));
++
++ return ret;
++}
++
++static int mxc_vout_release(struct file *file)
++{
++ unsigned int ret = 0;
++ struct videobuf_queue *q;
++ struct mxc_vout_output *vout = file->private_data;
++
++ if (!vout)
++ return 0;
++
++ if (--vout->open_cnt == 0) {
++ q = &vout->vbq;
++ if (q->streaming)
++ mxc_vidioc_streamoff(file, vout, vout->type);
++ else {
++ release_disp_output(vout);
++ videobuf_queue_cancel(q);
++ }
++ destroy_workqueue(vout->v4l_wq);
++ ret = videobuf_mmap_free(q);
++ }
++
++ return ret;
++}
++
++static int mxc_vout_open(struct file *file)
++{
++ struct mxc_vout_output *vout = NULL;
++ int ret = 0;
++
++ vout = video_drvdata(file);
++
++ if (vout == NULL)
++ return -ENODEV;
++
++ if (vout->open_cnt++ == 0) {
++ vout->ctrl_rotate = 0;
++ vout->ctrl_vflip = 0;
++ vout->ctrl_hflip = 0;
++ update_display_setting();
++ ret = update_setting_from_fbi(vout, vout->fbi);
++ if (ret < 0)
++ goto err;
++
++ vout->v4l_wq = create_singlethread_workqueue("v4l2q");
++ if (!vout->v4l_wq) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Could not create work queue\n");
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ INIT_WORK(&vout->disp_work, disp_work_func);
++
++ INIT_LIST_HEAD(&vout->queue_list);
++ INIT_LIST_HEAD(&vout->active_list);
++
++ vout->fmt_init = false;
++ vout->frame_count = 0;
++ vout->vdi_frame_cnt = 0;
++
++ vout->win_pos.x = 0;
++ vout->win_pos.y = 0;
++ vout->release = true;
++ }
++
++ file->private_data = vout;
++
++err:
++ return ret;
++}
++
++/*
++ * V4L2 ioctls
++ */
++static int mxc_vidioc_querycap(struct file *file, void *fh,
++ struct v4l2_capability *cap)
++{
++ struct mxc_vout_output *vout = fh;
++
++ strlcpy(cap->driver, VOUT_NAME, sizeof(cap->driver));
++ strlcpy(cap->card, vout->vfd->name, sizeof(cap->card));
++ cap->bus_info[0] = '\0';
++ cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT;
++
++ return 0;
++}
++
++static int mxc_vidioc_enum_fmt_vid_out(struct file *file, void *fh,
++ struct v4l2_fmtdesc *fmt)
++{
++ if (fmt->index >= NUM_MXC_VOUT_FORMATS)
++ return -EINVAL;
++
++ strlcpy(fmt->description, mxc_formats[fmt->index].description,
++ sizeof(fmt->description));
++ fmt->pixelformat = mxc_formats[fmt->index].pixelformat;
++
++ return 0;
++}
++
++static int mxc_vidioc_g_fmt_vid_out(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct mxc_vout_output *vout = fh;
++ struct v4l2_rect rect;
++
++ f->fmt.pix.width = vout->task.input.width;
++ f->fmt.pix.height = vout->task.input.height;
++ f->fmt.pix.pixelformat = vout->task.input.format;
++ f->fmt.pix.sizeimage = get_frame_size(vout);
++
++ if (f->fmt.pix.priv) {
++ rect.left = vout->task.input.crop.pos.x;
++ rect.top = vout->task.input.crop.pos.y;
++ rect.width = vout->task.input.crop.w;
++ rect.height = vout->task.input.crop.h;
++ if (copy_to_user((void __user *)f->fmt.pix.priv,
++ &rect, sizeof(rect)))
++ return -EFAULT;
++ }
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "frame_size:0x%x, pix_fmt:0x%x\n",
++ f->fmt.pix.sizeimage,
++ vout->task.input.format);
++
++ return 0;
++}
++
++static inline int ipu_try_task(struct mxc_vout_output *vout)
++{
++ int ret;
++ struct ipu_task *task = &vout->task;
++
++again:
++ ret = ipu_check_task(task);
++ if (ret != IPU_CHECK_OK) {
++ if (ret > IPU_CHECK_ERR_MIN) {
++ if (ret == IPU_CHECK_ERR_SPLIT_INPUTW_OVER ||
++ ret == IPU_CHECK_ERR_W_DOWNSIZE_OVER) {
++ task->input.crop.w -= 8;
++ goto again;
++ }
++ if (ret == IPU_CHECK_ERR_SPLIT_INPUTH_OVER ||
++ ret == IPU_CHECK_ERR_H_DOWNSIZE_OVER) {
++ task->input.crop.h -= 8;
++ goto again;
++ }
++ if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
++ if (vout->disp_support_windows) {
++ task->output.width -= 8;
++ task->output.crop.w =
++ task->output.width;
++ } else
++ task->output.crop.w -= 8;
++ goto again;
++ }
++ if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
++ if (vout->disp_support_windows) {
++ task->output.height -= 8;
++ task->output.crop.h =
++ task->output.height;
++ } else
++ task->output.crop.h -= 8;
++ goto again;
++ }
++ ret = -EINVAL;
++ }
++ } else
++ ret = 0;
++
++ return ret;
++}
++
++static inline int vdoaipu_try_task(struct mxc_vout_output *vout)
++{
++ int ret;
++ int is_1080p_stream;
++ int in_width, in_height;
++ size_t size;
++ struct ipu_task *ipu_task = &vout->task;
++ struct ipu_crop *icrop = &ipu_task->input.crop;
++ struct ipu_task *vdoa_task = &vout->vdoa_task;
++ u32 deinterlace = 0;
++ u32 in_fmt;
++
++ if (vout->task.input.deinterlace.enable)
++ deinterlace = 1;
++
++ memset(vdoa_task, 0, sizeof(*vdoa_task));
++ vdoa_task->output.format = IPU_PIX_FMT_NV12;
++ memcpy(&vdoa_task->input, &ipu_task->input,
++ sizeof(ipu_task->input));
++ if ((icrop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (icrop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN)) {
++ vdoa_task->input.crop.w =
++ ALIGN(icrop->w, IPU_PIX_FMT_TILED_NV12_MBALIGN);
++ vdoa_task->input.crop.h =
++ ALIGN(icrop->h, IPU_PIX_FMT_TILED_NV12_MBALIGN);
++ }
++ vdoa_task->output.width = vdoa_task->input.crop.w;
++ vdoa_task->output.height = vdoa_task->input.crop.h;
++ vdoa_task->output.crop.w = vdoa_task->input.crop.w;
++ vdoa_task->output.crop.h = vdoa_task->input.crop.h;
++
++ size = PAGE_ALIGN(vdoa_task->input.crop.w *
++ vdoa_task->input.crop.h *
++ fmt_to_bpp(vdoa_task->output.format)/8);
++ if (size > vout->vdoa_work.size) {
++ if (vout->vdoa_work.vaddr)
++ free_dma_buf(vout, &vout->vdoa_work);
++ vout->vdoa_work.size = size;
++ ret = alloc_dma_buf(vout, &vout->vdoa_work);
++ if (ret < 0)
++ return ret;
++ }
++ ret = ipu_check_task(vdoa_task);
++ if (ret != IPU_CHECK_OK)
++ return -EINVAL;
++
++ is_1080p_stream = CHECK_TILED_1080P_STREAM(vout);
++ if (is_1080p_stream)
++ ipu_task->input.crop.h = VALID_HEIGHT_1080P;
++ in_fmt = ipu_task->input.format;
++ in_width = ipu_task->input.width;
++ in_height = ipu_task->input.height;
++ ipu_task->input.format = vdoa_task->output.format;
++ ipu_task->input.height = vdoa_task->output.height;
++ ipu_task->input.width = vdoa_task->output.width;
++ if (deinterlace)
++ ipu_task->input.deinterlace.enable = 0;
++ ret = ipu_try_task(vout);
++ if (deinterlace)
++ ipu_task->input.deinterlace.enable = 1;
++ ipu_task->input.format = in_fmt;
++ ipu_task->input.width = in_width;
++ ipu_task->input.height = in_height;
++
++ return ret;
++}
++
++static int mxc_vout_try_task(struct mxc_vout_output *vout)
++{
++ int ret = 0;
++ struct ipu_output *output = &vout->task.output;
++ struct ipu_input *input = &vout->task.input;
++ struct ipu_crop *crop = &input->crop;
++ u32 o_height = 0;
++ u32 ocrop_h = 0;
++ bool tiled_fmt = false;
++ bool tiled_need_pp = false;
++
++ vout->vdoa_1080p = CHECK_TILED_1080P_DISPLAY(vout);
++ if (vout->vdoa_1080p) {
++ input->crop.h = FRAME_HEIGHT_1080P;
++ o_height = output->height;
++ ocrop_h = output->crop.h;
++ output->height = FRAME_HEIGHT_1080P;
++ output->crop.h = FRAME_HEIGHT_1080P;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == input->format) ||
++ (IPU_PIX_FMT_TILED_NV12F == input->format)) {
++ if ((input->width % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (input->height % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (crop->pos.x % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (crop->pos.y % IPU_PIX_FMT_TILED_NV12_MBALIGN)) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "ERR: tiled fmt needs 16 pixel align.\n");
++ return -EINVAL;
++ }
++ if ((crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN) ||
++ (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ tiled_need_pp = true;
++ } else {
++ crop->w -= crop->w % 8;
++ crop->h -= crop->h % 8;
++ }
++ /* assume task.output already set by S_CROP */
++ vout->linear_bypass_pp = is_pp_bypass(vout);
++ if (vout->linear_bypass_pp) {
++ v4l2_info(vout->vfd->v4l2_dev, "Bypass IC.\n");
++ output->format = input->format;
++ } else {
++ /* if need CSC, choose IPU-DP or IPU_IC do it */
++ if (vout->disp_support_csc) {
++ if (colorspaceofpixel(input->format) == YUV_CS)
++ output->format = IPU_PIX_FMT_UYVY;
++ else
++ output->format = IPU_PIX_FMT_RGB565;
++ } else {
++ if (colorspaceofpixel(vout->disp_fmt) == YUV_CS)
++ output->format = IPU_PIX_FMT_UYVY;
++ else
++ output->format = IPU_PIX_FMT_RGB565;
++ }
++
++ vout->tiled_bypass_pp = false;
++ if ((IPU_PIX_FMT_TILED_NV12 == input->format) ||
++ (IPU_PIX_FMT_TILED_NV12F == input->format)) {
++ /* check resize/rotate/flip, or csc task */
++ if (!(tiled_need_pp ||
++ (IPU_ROTATE_NONE != output->rotate) ||
++ (input->crop.w != output->crop.w) ||
++ (input->crop.h != output->crop.h) ||
++ (!vout->disp_support_csc &&
++ (colorspaceofpixel(vout->disp_fmt) == RGB_CS)))
++ ) {
++ /* IC bypass */
++ output->format = IPU_PIX_FMT_NV12;
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "tiled bypass pp\n");
++ vout->tiled_bypass_pp = true;
++ }
++ tiled_fmt = true;
++ }
++
++ if ((!vout->tiled_bypass_pp) && tiled_fmt)
++ ret = vdoaipu_try_task(vout);
++ else
++ ret = ipu_try_task(vout);
++ }
++
++ if (vout->vdoa_1080p) {
++ output->height = o_height;
++ output->crop.h = ocrop_h;
++ }
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "icrop.w:%u, icrop.h:%u, iw:%u, ih:%u,"
++ "ocrop.w:%u, ocrop.h:%u, ow:%u, oh:%u\n",
++ input->crop.w, input->crop.h,
++ input->width, input->height,
++ output->crop.w, output->crop.h,
++ output->width, output->height);
++ return ret;
++}
++
++static int mxc_vout_try_format(struct mxc_vout_output *vout,
++ struct v4l2_format *f)
++{
++ int ret = 0;
++ struct v4l2_rect rect;
++
++ if ((f->fmt.pix.field != V4L2_FIELD_NONE) &&
++ (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format)) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "progressive tiled fmt should used V4L2_FIELD_NONE!\n");
++ return -EINVAL;
++ }
++
++ if (f->fmt.pix.priv && copy_from_user(&rect,
++ (void __user *)f->fmt.pix.priv, sizeof(rect)))
++ return -EFAULT;
++
++ vout->task.input.width = f->fmt.pix.width;
++ vout->task.input.height = f->fmt.pix.height;
++ vout->task.input.format = f->fmt.pix.pixelformat;
++
++ ret = set_field_fmt(vout, f->fmt.pix.field);
++ if (ret < 0)
++ return ret;
++
++ if (f->fmt.pix.priv) {
++ vout->task.input.crop.pos.x = rect.left;
++ vout->task.input.crop.pos.y = rect.top;
++ vout->task.input.crop.w = rect.width;
++ vout->task.input.crop.h = rect.height;
++ } else {
++ vout->task.input.crop.pos.x = 0;
++ vout->task.input.crop.pos.y = 0;
++ vout->task.input.crop.w = f->fmt.pix.width;
++ vout->task.input.crop.h = f->fmt.pix.height;
++ }
++ memcpy(&vout->in_rect, &vout->task.input.crop, sizeof(vout->in_rect));
++
++ ret = mxc_vout_try_task(vout);
++ if (!ret) {
++ if (f->fmt.pix.priv) {
++ rect.width = vout->task.input.crop.w;
++ rect.height = vout->task.input.crop.h;
++ if (copy_to_user((void __user *)f->fmt.pix.priv,
++ &rect, sizeof(rect)))
++ ret = -EFAULT;
++ } else {
++ f->fmt.pix.width = vout->task.input.crop.w;
++ f->fmt.pix.height = vout->task.input.crop.h;
++ }
++ }
++
++ return ret;
++}
++
++static bool mxc_vout_need_fb_reconfig(struct mxc_vout_output *vout,
++ struct mxc_vout_output *pre_vout)
++{
++ if (!vout->vbq.streaming)
++ return false;
++
++ if (vout->tiled_bypass_pp)
++ return true;
++
++ if (vout->linear_bypass_pp != pre_vout->linear_bypass_pp)
++ return true;
++
++ /* cropped output resolution or format are changed */
++ if (vout->task.output.format != pre_vout->task.output.format ||
++ vout->task.output.crop.w != pre_vout->task.output.crop.w ||
++ vout->task.output.crop.h != pre_vout->task.output.crop.h)
++ return true;
++
++ /* overlay: window position or resolution are changed */
++ if (vout->disp_support_windows &&
++ (vout->win_pos.x != pre_vout->win_pos.x ||
++ vout->win_pos.y != pre_vout->win_pos.y ||
++ vout->task.output.width != pre_vout->task.output.width ||
++ vout->task.output.height != pre_vout->task.output.height))
++ return true;
++
++ /* background: cropped position is changed */
++ if (!vout->disp_support_windows &&
++ (vout->task.output.crop.pos.x !=
++ pre_vout->task.output.crop.pos.x ||
++ vout->task.output.crop.pos.y !=
++ pre_vout->task.output.crop.pos.y))
++ return true;
++
++ return false;
++}
++
++static int mxc_vidioc_s_fmt_vid_out(struct file *file, void *fh,
++ struct v4l2_format *f)
++{
++ struct mxc_vout_output *vout = fh;
++ int ret = 0;
++
++ if (vout->vbq.streaming)
++ return -EBUSY;
++
++ mutex_lock(&vout->task_lock);
++ ret = mxc_vout_try_format(vout, f);
++ if (ret >= 0)
++ vout->fmt_init = true;
++ mutex_unlock(&vout->task_lock);
++
++ return ret;
++}
++
++static int mxc_vidioc_cropcap(struct file *file, void *fh,
++ struct v4l2_cropcap *cropcap)
++{
++ struct mxc_vout_output *vout = fh;
++
++ if (cropcap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ cropcap->bounds = vout->crop_bounds;
++ cropcap->defrect = vout->crop_bounds;
++
++ return 0;
++}
++
++static int mxc_vidioc_g_crop(struct file *file, void *fh,
++ struct v4l2_crop *crop)
++{
++ struct mxc_vout_output *vout = fh;
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ if (vout->disp_support_windows) {
++ crop->c.left = vout->win_pos.x;
++ crop->c.top = vout->win_pos.y;
++ crop->c.width = vout->task.output.width;
++ crop->c.height = vout->task.output.height;
++ } else {
++ if (vout->task.output.crop.w && vout->task.output.crop.h) {
++ crop->c.left = vout->task.output.crop.pos.x;
++ crop->c.top = vout->task.output.crop.pos.y;
++ crop->c.width = vout->task.output.crop.w;
++ crop->c.height = vout->task.output.crop.h;
++ } else {
++ crop->c.left = 0;
++ crop->c.top = 0;
++ crop->c.width = vout->task.output.width;
++ crop->c.height = vout->task.output.height;
++ }
++ }
++
++ return 0;
++}
++
++static int mxc_vidioc_s_crop(struct file *file, void *fh,
++ const struct v4l2_crop *crop)
++{
++ struct mxc_vout_output *vout = fh, *pre_vout;
++ struct v4l2_rect *b = &vout->crop_bounds;
++ struct v4l2_crop fix_up_crop;
++ int ret = 0;
++
++ memcpy(&fix_up_crop, crop, sizeof(*crop));
++
++ if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ if (crop->c.width < 0 || crop->c.height < 0)
++ return -EINVAL;
++
++ if (crop->c.width == 0)
++ fix_up_crop.c.width = b->width - b->left;
++ if (crop->c.height == 0)
++ fix_up_crop.c.height = b->height - b->top;
++
++ if (crop->c.top < b->top)
++ fix_up_crop.c.top = b->top;
++ if (crop->c.top >= b->top + b->height)
++ fix_up_crop.c.top = b->top + b->height - 1;
++ if (crop->c.height > b->top - crop->c.top + b->height)
++ fix_up_crop.c.height =
++ b->top - fix_up_crop.c.top + b->height;
++
++ if (crop->c.left < b->left)
++ fix_up_crop.c.left = b->left;
++ if (crop->c.left >= b->left + b->width)
++ fix_up_crop.c.left = b->left + b->width - 1;
++ if (crop->c.width > b->left - crop->c.left + b->width)
++ fix_up_crop.c.width =
++ b->left - fix_up_crop.c.left + b->width;
++
++ /* stride line limitation */
++ fix_up_crop.c.height -= fix_up_crop.c.height % 8;
++ fix_up_crop.c.width -= fix_up_crop.c.width % 8;
++ if ((fix_up_crop.c.width <= 0) || (fix_up_crop.c.height <= 0) ||
++ ((fix_up_crop.c.left + fix_up_crop.c.width) >
++ (b->left + b->width)) ||
++ ((fix_up_crop.c.top + fix_up_crop.c.height) >
++ (b->top + b->height))) {
++ v4l2_err(vout->vfd->v4l2_dev, "s_crop err: %d, %d, %d, %d",
++ fix_up_crop.c.left, fix_up_crop.c.top,
++ fix_up_crop.c.width, fix_up_crop.c.height);
++ return -EINVAL;
++ }
++
++ /* the same setting, return */
++ if (vout->disp_support_windows) {
++ if ((vout->win_pos.x == fix_up_crop.c.left) &&
++ (vout->win_pos.y == fix_up_crop.c.top) &&
++ (vout->task.output.crop.w == fix_up_crop.c.width) &&
++ (vout->task.output.crop.h == fix_up_crop.c.height))
++ return 0;
++ } else {
++ if ((vout->task.output.crop.pos.x == fix_up_crop.c.left) &&
++ (vout->task.output.crop.pos.y == fix_up_crop.c.top) &&
++ (vout->task.output.crop.w == fix_up_crop.c.width) &&
++ (vout->task.output.crop.h == fix_up_crop.c.height))
++ return 0;
++ }
++
++ pre_vout = vmalloc(sizeof(*pre_vout));
++ if (!pre_vout)
++ return -ENOMEM;
++
++ /* wait current work finish */
++ if (vout->vbq.streaming)
++ flush_workqueue(vout->v4l_wq);
++
++ mutex_lock(&vout->task_lock);
++
++ memcpy(pre_vout, vout, sizeof(*vout));
++
++ if (vout->disp_support_windows) {
++ vout->task.output.crop.pos.x = 0;
++ vout->task.output.crop.pos.y = 0;
++ vout->win_pos.x = fix_up_crop.c.left;
++ vout->win_pos.y = fix_up_crop.c.top;
++ vout->task.output.width = fix_up_crop.c.width;
++ vout->task.output.height = fix_up_crop.c.height;
++ } else {
++ vout->task.output.crop.pos.x = fix_up_crop.c.left;
++ vout->task.output.crop.pos.y = fix_up_crop.c.top;
++ }
++
++ vout->task.output.crop.w = fix_up_crop.c.width;
++ vout->task.output.crop.h = fix_up_crop.c.height;
++
++ /*
++ * must S_CROP before S_FMT, for fist time S_CROP, will not check
++ * ipu task, it will check in S_FMT, after S_FMT, S_CROP should
++ * check ipu task too.
++ */
++ if (vout->fmt_init) {
++ memcpy(&vout->task.input.crop, &vout->in_rect,
++ sizeof(vout->in_rect));
++ ret = mxc_vout_try_task(vout);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "vout check task failed\n");
++ memcpy(vout, pre_vout, sizeof(*vout));
++ goto done;
++ }
++
++ if (mxc_vout_need_fb_reconfig(vout, pre_vout)) {
++ ret = config_disp_output(vout);
++ if (ret < 0)
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Config display output failed\n");
++ }
++ }
++
++done:
++ vfree(pre_vout);
++ mutex_unlock(&vout->task_lock);
++
++ return ret;
++}
++
++static int mxc_vidioc_queryctrl(struct file *file, void *fh,
++ struct v4l2_queryctrl *ctrl)
++{
++ int ret = 0;
++
++ switch (ctrl->id) {
++ case V4L2_CID_ROTATE:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 270, 90, 0);
++ break;
++ case V4L2_CID_VFLIP:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0);
++ break;
++ case V4L2_CID_HFLIP:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0);
++ break;
++ case V4L2_CID_MXC_MOTION:
++ ret = v4l2_ctrl_query_fill(ctrl, 0, 2, 1, 0);
++ break;
++ default:
++ ctrl->name[0] = '\0';
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static int mxc_vidioc_g_ctrl(struct file *file, void *fh,
++ struct v4l2_control *ctrl)
++{
++ int ret = 0;
++ struct mxc_vout_output *vout = fh;
++
++ switch (ctrl->id) {
++ case V4L2_CID_ROTATE:
++ ctrl->value = vout->ctrl_rotate;
++ break;
++ case V4L2_CID_VFLIP:
++ ctrl->value = vout->ctrl_vflip;
++ break;
++ case V4L2_CID_HFLIP:
++ ctrl->value = vout->ctrl_hflip;
++ break;
++ case V4L2_CID_MXC_MOTION:
++ if (vout->task.input.deinterlace.enable)
++ ctrl->value = vout->task.input.deinterlace.motion;
++ else
++ ctrl->value = 0;
++ break;
++ default:
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
++static void setup_task_rotation(struct mxc_vout_output *vout)
++{
++ if (vout->ctrl_rotate == 0) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_180;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_VERT_FLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_NONE;
++ } else if (vout->ctrl_rotate == 90) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_LEFT;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT;
++ } else if (vout->ctrl_rotate == 180) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_NONE;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_VERT_FLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_180;
++ } else if (vout->ctrl_rotate == 270) {
++ if (vout->ctrl_vflip && vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT;
++ else if (vout->ctrl_vflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP;
++ else if (vout->ctrl_hflip)
++ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP;
++ else
++ vout->task.output.rotate = IPU_ROTATE_90_LEFT;
++ }
++}
++
++static int mxc_vidioc_s_ctrl(struct file *file, void *fh,
++ struct v4l2_control *ctrl)
++{
++ int ret = 0;
++ struct mxc_vout_output *vout = fh, *pre_vout;
++
++ pre_vout = vmalloc(sizeof(*pre_vout));
++ if (!pre_vout)
++ return -ENOMEM;
++
++ /* wait current work finish */
++ if (vout->vbq.streaming)
++ flush_workqueue(vout->v4l_wq);
++
++ mutex_lock(&vout->task_lock);
++
++ memcpy(pre_vout, vout, sizeof(*vout));
++
++ switch (ctrl->id) {
++ case V4L2_CID_ROTATE:
++ {
++ vout->ctrl_rotate = (ctrl->value/90) * 90;
++ if (vout->ctrl_rotate > 270)
++ vout->ctrl_rotate = 270;
++ setup_task_rotation(vout);
++ break;
++ }
++ case V4L2_CID_VFLIP:
++ {
++ vout->ctrl_vflip = ctrl->value;
++ setup_task_rotation(vout);
++ break;
++ }
++ case V4L2_CID_HFLIP:
++ {
++ vout->ctrl_hflip = ctrl->value;
++ setup_task_rotation(vout);
++ break;
++ }
++ case V4L2_CID_MXC_MOTION:
++ {
++ vout->task.input.deinterlace.motion = ctrl->value;
++ break;
++ }
++ default:
++ ret = -EINVAL;
++ goto done;
++ }
++
++ if (vout->fmt_init) {
++ memcpy(&vout->task.input.crop, &vout->in_rect,
++ sizeof(vout->in_rect));
++ ret = mxc_vout_try_task(vout);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "vout check task failed\n");
++ memcpy(vout, pre_vout, sizeof(*vout));
++ goto done;
++ }
++
++ if (mxc_vout_need_fb_reconfig(vout, pre_vout)) {
++ ret = config_disp_output(vout);
++ if (ret < 0)
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Config display output failed\n");
++ }
++ }
++
++done:
++ vfree(pre_vout);
++ mutex_unlock(&vout->task_lock);
++
++ return ret;
++}
++
++static int mxc_vidioc_reqbufs(struct file *file, void *fh,
++ struct v4l2_requestbuffers *req)
++{
++ int ret = 0;
++ struct mxc_vout_output *vout = fh;
++ struct videobuf_queue *q = &vout->vbq;
++
++ if (req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
++ return -EINVAL;
++
++ /* should not be here after streaming, videobuf_reqbufs will control */
++ mutex_lock(&vout->task_lock);
++
++ ret = videobuf_reqbufs(q, req);
++
++ mutex_unlock(&vout->task_lock);
++ return ret;
++}
++
++static int mxc_vidioc_querybuf(struct file *file, void *fh,
++ struct v4l2_buffer *b)
++{
++ int ret;
++ struct mxc_vout_output *vout = fh;
++
++ ret = videobuf_querybuf(&vout->vbq, b);
++ if (!ret) {
++ /* return physical address */
++ struct videobuf_buffer *vb = vout->vbq.bufs[b->index];
++ if (b->flags & V4L2_BUF_FLAG_MAPPED)
++ b->m.offset = videobuf_to_dma_contig(vb);
++ }
++
++ return ret;
++}
++
++static int mxc_vidioc_qbuf(struct file *file, void *fh,
++ struct v4l2_buffer *buffer)
++{
++ struct mxc_vout_output *vout = fh;
++
++ return videobuf_qbuf(&vout->vbq, buffer);
++}
++
++static int mxc_vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *b)
++{
++ struct mxc_vout_output *vout = fh;
++
++ if (!vout->vbq.streaming)
++ return -EINVAL;
++
++ if (file->f_flags & O_NONBLOCK)
++ return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 1);
++ else
++ return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 0);
++}
++
++static int set_window_position(struct mxc_vout_output *vout,
++ struct mxcfb_pos *pos)
++{
++ struct fb_info *fbi = vout->fbi;
++ mm_segment_t old_fs;
++ int ret = 0;
++
++ if (vout->disp_support_windows) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ ret = fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS,
++ (unsigned long)pos);
++ set_fs(old_fs);
++ }
++
++ return ret;
++}
++
++static int config_disp_output(struct mxc_vout_output *vout)
++{
++ struct dma_mem *buf = NULL;
++ struct fb_info *fbi = vout->fbi;
++ struct fb_var_screeninfo var;
++ struct mxcfb_pos pos;
++ int i, fb_num, ret;
++ u32 fb_base;
++ u32 size;
++ u32 display_buf_size;
++ u32 *pixel = NULL;
++ u32 color;
++ int j;
++
++ memcpy(&var, &fbi->var, sizeof(var));
++ fb_base = fbi->fix.smem_start;
++
++ var.xres = vout->task.output.width;
++ var.yres = vout->task.output.height;
++ if (vout->linear_bypass_pp || vout->tiled_bypass_pp) {
++ fb_num = 1;
++ /* input crop */
++ if (vout->task.input.width > vout->task.output.width)
++ var.xres_virtual = vout->task.input.width;
++ else
++ var.xres_virtual = var.xres;
++ if (vout->task.input.height > vout->task.output.height)
++ var.yres_virtual = vout->task.input.height;
++ else
++ var.yres_virtual = var.yres;
++ var.rotate = vout->task.output.rotate;
++ var.vmode |= FB_VMODE_YWRAP;
++ } else {
++ fb_num = FB_BUFS;
++ var.xres_virtual = var.xres;
++ var.yres_virtual = fb_num * var.yres;
++ var.vmode &= ~FB_VMODE_YWRAP;
++ }
++ var.bits_per_pixel = fmt_to_bpp(vout->task.output.format);
++ var.nonstd = vout->task.output.format;
++
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "set display fb to %d %d\n",
++ var.xres, var.yres);
++
++ /*
++ * To setup the overlay fb from scratch without
++ * the last time overlay fb position or resolution's
++ * impact, we take the following steps:
++ * - blank fb
++ * - set fb position to the starting point
++ * - reconfigure fb
++ * - set fb position to a specific point
++ * - unblank fb
++ * This procedure applies to non-overlay fbs as well.
++ */
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ pos.x = 0;
++ pos.y = 0;
++ ret = set_window_position(vout, &pos);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev, "failed to set fb position "
++ "to starting point\n");
++ return ret;
++ }
++
++ /* Init display channel through fb API */
++ var.yoffset = 0;
++ var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_set_var(fbi, &var);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "ERR:%s fb_set_var ret:%d\n", __func__, ret);
++ return ret;
++ }
++
++ ret = set_window_position(vout, &vout->win_pos);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev, "failed to set fb position\n");
++ return ret;
++ }
++
++ if (vout->linear_bypass_pp || vout->tiled_bypass_pp)
++ display_buf_size = fbi->fix.line_length * fbi->var.yres_virtual;
++ else
++ display_buf_size = fbi->fix.line_length * fbi->var.yres;
++ for (i = 0; i < fb_num; i++)
++ vout->disp_bufs[i] = fbi->fix.smem_start + i * display_buf_size;
++ if (vout->tiled_bypass_pp) {
++ size = PAGE_ALIGN(vout->task.input.crop.w *
++ vout->task.input.crop.h *
++ fmt_to_bpp(vout->task.output.format)/8);
++ if (size > vout->vdoa_output[0].size) {
++ for (i = 0; i < VDOA_FB_BUFS; i++) {
++ buf = &vout->vdoa_output[i];
++ if (buf->vaddr)
++ free_dma_buf(vout, buf);
++ buf->size = size;
++ ret = alloc_dma_buf(vout, buf);
++ if (ret < 0)
++ goto err;
++ }
++ }
++ for (i = fb_num; i < (fb_num + VDOA_FB_BUFS); i++)
++ vout->disp_bufs[i] =
++ vout->vdoa_output[i - fb_num].paddr;
++ }
++ vout->fb_smem_len = fbi->fix.smem_len;
++ vout->fb_smem_start = fbi->fix.smem_start;
++ if (fb_base != fbi->fix.smem_start) {
++ v4l2_dbg(1, debug, vout->vfd->v4l2_dev,
++ "realloc fb mem size:0x%x@0x%lx,old paddr @0x%x\n",
++ fbi->fix.smem_len, fbi->fix.smem_start, fb_base);
++ }
++
++ /* fill black when video config changed */
++ color = colorspaceofpixel(vout->task.output.format) == YUV_CS ?
++ UYVY_BLACK : RGB_BLACK;
++ if (IS_PLANAR_PIXEL_FORMAT(vout->task.output.format)) {
++ size = display_buf_size * 8 /
++ fmt_to_bpp(vout->task.output.format);
++ memset(fbi->screen_base, Y_BLACK, size);
++ memset(fbi->screen_base + size, UV_BLACK,
++ display_buf_size - size);
++ } else {
++ pixel = (u32 *)fbi->screen_base;
++ for (i = 0; i < ((display_buf_size * fb_num) >> 2); i++)
++ *pixel++ = color;
++ }
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_blank(fbi, FB_BLANK_UNBLANK);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ vout->release = false;
++
++ return ret;
++err:
++ for (j = i - 1; j >= 0; j--) {
++ buf = &vout->vdoa_output[j];
++ if (buf->vaddr)
++ free_dma_buf(vout, buf);
++ }
++ return ret;
++}
++
++static inline void wait_for_vsync(struct mxc_vout_output *vout)
++{
++ struct fb_info *fbi = vout->fbi;
++ mm_segment_t old_fs;
++
++ if (fbi->fbops->fb_ioctl) {
++ old_fs = get_fs();
++ set_fs(KERNEL_DS);
++ fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC,
++ (unsigned long)NULL);
++ set_fs(old_fs);
++ }
++
++ return;
++}
++
++static void release_disp_output(struct mxc_vout_output *vout)
++{
++ struct fb_info *fbi = vout->fbi;
++ struct mxcfb_pos pos;
++
++ if (vout->release)
++ return;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ /* restore pos to 0,0 avoid fb pan display hang? */
++ pos.x = 0;
++ pos.y = 0;
++ set_window_position(vout, &pos);
++
++ if (get_ipu_channel(fbi) == MEM_BG_SYNC) {
++ console_lock();
++ fbi->fix.smem_start = vout->disp_bufs[0];
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_blank(fbi, FB_BLANK_UNBLANK);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ }
++
++ vout->release = true;
++}
++
++static int mxc_vidioc_streamon(struct file *file, void *fh,
++ enum v4l2_buf_type i)
++{
++ struct mxc_vout_output *vout = fh;
++ struct videobuf_queue *q = &vout->vbq;
++ int ret;
++
++ if (q->streaming) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "video output already run\n");
++ ret = -EBUSY;
++ goto done;
++ }
++
++ if (deinterlace_3_field(vout) && list_is_singular(&q->stream)) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "deinterlacing: need queue 2 frame before streamon\n");
++ ret = -EINVAL;
++ goto done;
++ }
++
++ ret = config_disp_output(vout);
++ if (ret < 0) {
++ v4l2_err(vout->vfd->v4l2_dev,
++ "Config display output failed\n");
++ goto done;
++ }
++
++ hrtimer_init(&vout->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS);
++ vout->timer.function = mxc_vout_timer_handler;
++ vout->timer_stop = true;
++
++ vout->start_ktime = hrtimer_cb_get_time(&vout->timer);
++
++ vout->pre1_vb = NULL;
++ vout->pre2_vb = NULL;
++
++ ret = videobuf_streamon(q);
++done:
++ return ret;
++}
++
++static int mxc_vidioc_streamoff(struct file *file, void *fh,
++ enum v4l2_buf_type i)
++{
++ struct mxc_vout_output *vout = fh;
++ struct videobuf_queue *q = &vout->vbq;
++ int ret = 0;
++
++ if (q->streaming) {
++ flush_workqueue(vout->v4l_wq);
++
++ hrtimer_cancel(&vout->timer);
++
++ /*
++ * Wait for 2 vsyncs to make sure
++ * frames are drained on triple
++ * buffer.
++ */
++ wait_for_vsync(vout);
++ wait_for_vsync(vout);
++
++ release_disp_output(vout);
++
++ ret = videobuf_streamoff(&vout->vbq);
++ }
++ INIT_LIST_HEAD(&vout->queue_list);
++ INIT_LIST_HEAD(&vout->active_list);
++
++ return ret;
++}
++
++static const struct v4l2_ioctl_ops mxc_vout_ioctl_ops = {
++ .vidioc_querycap = mxc_vidioc_querycap,
++ .vidioc_enum_fmt_vid_out = mxc_vidioc_enum_fmt_vid_out,
++ .vidioc_g_fmt_vid_out = mxc_vidioc_g_fmt_vid_out,
++ .vidioc_s_fmt_vid_out = mxc_vidioc_s_fmt_vid_out,
++ .vidioc_cropcap = mxc_vidioc_cropcap,
++ .vidioc_g_crop = mxc_vidioc_g_crop,
++ .vidioc_s_crop = mxc_vidioc_s_crop,
++ .vidioc_queryctrl = mxc_vidioc_queryctrl,
++ .vidioc_g_ctrl = mxc_vidioc_g_ctrl,
++ .vidioc_s_ctrl = mxc_vidioc_s_ctrl,
++ .vidioc_reqbufs = mxc_vidioc_reqbufs,
++ .vidioc_querybuf = mxc_vidioc_querybuf,
++ .vidioc_qbuf = mxc_vidioc_qbuf,
++ .vidioc_dqbuf = mxc_vidioc_dqbuf,
++ .vidioc_streamon = mxc_vidioc_streamon,
++ .vidioc_streamoff = mxc_vidioc_streamoff,
++};
++
++static const struct v4l2_file_operations mxc_vout_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = video_ioctl2,
++ .mmap = mxc_vout_mmap,
++ .open = mxc_vout_open,
++ .release = mxc_vout_release,
++};
++
++static struct video_device mxc_vout_template = {
++ .name = "MXC Video Output",
++ .fops = &mxc_vout_fops,
++ .ioctl_ops = &mxc_vout_ioctl_ops,
++ .release = video_device_release,
++};
++
++static struct videobuf_queue_ops mxc_vout_vbq_ops = {
++ .buf_setup = mxc_vout_buffer_setup,
++ .buf_prepare = mxc_vout_buffer_prepare,
++ .buf_release = mxc_vout_buffer_release,
++ .buf_queue = mxc_vout_buffer_queue,
++};
++
++static void mxc_vout_free_output(struct mxc_vout_dev *dev)
++{
++ int i;
++ int j;
++ struct mxc_vout_output *vout;
++ struct video_device *vfd;
++
++ for (i = 0; i < dev->out_num; i++) {
++ vout = dev->out[i];
++ vfd = vout->vfd;
++ if (vout->vdoa_work.vaddr)
++ free_dma_buf(vout, &vout->vdoa_work);
++ for (j = 0; j < VDOA_FB_BUFS; j++) {
++ if (vout->vdoa_output[j].vaddr)
++ free_dma_buf(vout, &vout->vdoa_output[j]);
++ }
++ if (vfd) {
++ if (!video_is_registered(vfd))
++ video_device_release(vfd);
++ else
++ video_unregister_device(vfd);
++ }
++ kfree(vout);
++ }
++}
++
++static int mxc_vout_setup_output(struct mxc_vout_dev *dev)
++{
++ struct videobuf_queue *q;
++ struct fb_info *fbi;
++ struct mxc_vout_output *vout;
++ int i, ret = 0;
++
++ update_display_setting();
++
++ /* all output/overlay based on fb */
++ for (i = 0; i < num_registered_fb; i++) {
++ fbi = registered_fb[i];
++
++ vout = kzalloc(sizeof(struct mxc_vout_output), GFP_KERNEL);
++ if (!vout) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ dev->out[dev->out_num] = vout;
++ dev->out_num++;
++
++ vout->fbi = fbi;
++ vout->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
++ vout->vfd = video_device_alloc();
++ if (!vout->vfd) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ *vout->vfd = mxc_vout_template;
++ vout->vfd->debug = debug;
++ vout->vfd->v4l2_dev = &dev->v4l2_dev;
++ vout->vfd->lock = &vout->mutex;
++ vout->vfd->vfl_dir = VFL_DIR_TX;
++
++ mutex_init(&vout->mutex);
++ mutex_init(&vout->task_lock);
++
++ strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name));
++
++ video_set_drvdata(vout->vfd, vout);
++
++ if (video_register_device(vout->vfd,
++ VFL_TYPE_GRABBER, video_nr + i) < 0) {
++ ret = -ENODEV;
++ break;
++ }
++
++ q = &vout->vbq;
++ q->dev = dev->dev;
++ spin_lock_init(&vout->vbq_lock);
++ videobuf_queue_dma_contig_init(q, &mxc_vout_vbq_ops, q->dev,
++ &vout->vbq_lock, vout->type, V4L2_FIELD_NONE,
++ sizeof(struct videobuf_buffer), vout, NULL);
++
++ v4l2_info(vout->vfd->v4l2_dev, "V4L2 device registered as %s\n",
++ video_device_node_name(vout->vfd));
++
++ }
++
++ return ret;
++}
++
++static int mxc_vout_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct mxc_vout_dev *dev;
++
++ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++ if (!dev)
++ return -ENOMEM;
++
++ dev->dev = &pdev->dev;
++ dev->dev->dma_mask = kmalloc(sizeof(*dev->dev->dma_mask), GFP_KERNEL);
++ *dev->dev->dma_mask = DMA_BIT_MASK(32);
++ dev->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ ret = v4l2_device_register(dev->dev, &dev->v4l2_dev);
++ if (ret) {
++ dev_err(dev->dev, "v4l2_device_register failed\n");
++ goto free_dev;
++ }
++
++ ret = mxc_vout_setup_output(dev);
++ if (ret < 0)
++ goto rel_vdev;
++
++ return 0;
++
++rel_vdev:
++ mxc_vout_free_output(dev);
++ v4l2_device_unregister(&dev->v4l2_dev);
++free_dev:
++ kfree(dev);
++ return ret;
++}
++
++static int mxc_vout_remove(struct platform_device *pdev)
++{
++ struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev);
++ struct mxc_vout_dev *dev = container_of(v4l2_dev, struct
++ mxc_vout_dev, v4l2_dev);
++
++ mxc_vout_free_output(dev);
++ v4l2_device_unregister(v4l2_dev);
++ kfree(dev);
++ return 0;
++}
++
++static const struct of_device_id mxc_v4l2_dt_ids[] = {
++ { .compatible = "fsl,mxc_v4l2_output", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_vout_driver = {
++ .driver = {
++ .name = "mxc_v4l2_output",
++ .of_match_table = mxc_v4l2_dt_ids,
++ },
++ .probe = mxc_vout_probe,
++ .remove = mxc_vout_remove,
++};
++
++static int __init mxc_vout_init(void)
++{
++ if (platform_driver_register(&mxc_vout_driver) != 0) {
++ printk(KERN_ERR VOUT_NAME ":Could not register Video driver\n");
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static void mxc_vout_cleanup(void)
++{
++ platform_driver_unregister(&mxc_vout_driver);
++}
++
++module_init(mxc_vout_init);
++module_exit(mxc_vout_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("V4L2-driver for MXC video output");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/subdev/Kconfig linux-3.14.72/drivers/media/platform/mxc/subdev/Kconfig
+--- linux-3.14.72.orig/drivers/media/platform/mxc/subdev/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/subdev/Kconfig 2016-06-19 22:11:55.189147618 +0200
+@@ -0,0 +1,21 @@
++if VIDEO_MXC_CAPTURE && SOC_IMX6SX
++
++config VIDEO_MXC_CSI_CAMERA
++ tristate "CSI camera support"
++ depends on VIDEO_MXC_CAPTURE && VIDEO_V4L2
++ ---help---
++ This is the video4linux2 capture driver based on CSI module.
++
++config MXC_CAMERA_OV5640
++ tristate "OmniVision ov5640 camera support"
++ depends on VIDEO_MXC_CAPTURE && I2C
++ ---help---
++ If you plan to use the ov5640 Camera with your MXC system, say Y here.
++
++config MXC_VADC
++ tristate "mxc VADC support"
++ depends on VIDEO_MXC_CAPTURE && VIDEO_V4L2
++ ---help---
++ If you plan to use the VADC with your MXC system, say Y here.
++
++endif
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/subdev/Makefile linux-3.14.72/drivers/media/platform/mxc/subdev/Makefile
+--- linux-3.14.72.orig/drivers/media/platform/mxc/subdev/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/subdev/Makefile 2016-06-19 22:11:55.189147618 +0200
+@@ -0,0 +1,7 @@
++#Makefile for mxc csi driver
++
++obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += mx6s_capture.o
++obj-$(CONFIG_MXC_VADC) += mxc_vadc.o
++
++ov5640_camera-objs := ov5640.o
++obj-$(CONFIG_MXC_CAMERA_OV5640) += ov5640_camera.o
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/subdev/mx6s_capture.c linux-3.14.72/drivers/media/platform/mxc/subdev/mx6s_capture.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/subdev/mx6s_capture.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/subdev/mx6s_capture.c 2016-06-19 22:11:55.189147618 +0200
+@@ -0,0 +1,1756 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mx6s_csi.c
++ *
++ * @brief mx6sx CMOS Sensor interface functions
++ *
++ * @ingroup CSI
++ */
++#include <asm/dma.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/fs.h>
++#include <linux/gcd.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/math64.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/slab.h>
++#include <linux/time.h>
++#include <linux/v4l2-mediabus.h>
++#include <media/v4l2-common.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-dev.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ioctl.h>
++#include <media/v4l2-of.h>
++#include <media/videobuf2-core.h>
++#include <media/videobuf2-dma-contig.h>
++
++#define MX6S_CAM_DRV_NAME "mx6s-csi"
++#define MX6S_CAM_VERSION "0.0.1"
++#define MX6S_CAM_DRIVER_DESCRIPTION "i.MX6S_CSI"
++
++#define MAX_VIDEO_MEM 16
++
++/* reset values */
++#define CSICR1_RESET_VAL 0x40000800
++#define CSICR2_RESET_VAL 0x0
++#define CSICR3_RESET_VAL 0x0
++
++/* csi control reg 1 */
++#define BIT_SWAP16_EN (0x1 << 31)
++#define BIT_EXT_VSYNC (0x1 << 30)
++#define BIT_EOF_INT_EN (0x1 << 29)
++#define BIT_PRP_IF_EN (0x1 << 28)
++#define BIT_CCIR_MODE (0x1 << 27)
++#define BIT_COF_INT_EN (0x1 << 26)
++#define BIT_SF_OR_INTEN (0x1 << 25)
++#define BIT_RF_OR_INTEN (0x1 << 24)
++#define BIT_SFF_DMA_DONE_INTEN (0x1 << 22)
++#define BIT_STATFF_INTEN (0x1 << 21)
++#define BIT_FB2_DMA_DONE_INTEN (0x1 << 20)
++#define BIT_FB1_DMA_DONE_INTEN (0x1 << 19)
++#define BIT_RXFF_INTEN (0x1 << 18)
++#define BIT_SOF_POL (0x1 << 17)
++#define BIT_SOF_INTEN (0x1 << 16)
++#define BIT_MCLKDIV (0xF << 12)
++#define BIT_HSYNC_POL (0x1 << 11)
++#define BIT_CCIR_EN (0x1 << 10)
++#define BIT_MCLKEN (0x1 << 9)
++#define BIT_FCC (0x1 << 8)
++#define BIT_PACK_DIR (0x1 << 7)
++#define BIT_CLR_STATFIFO (0x1 << 6)
++#define BIT_CLR_RXFIFO (0x1 << 5)
++#define BIT_GCLK_MODE (0x1 << 4)
++#define BIT_INV_DATA (0x1 << 3)
++#define BIT_INV_PCLK (0x1 << 2)
++#define BIT_REDGE (0x1 << 1)
++#define BIT_PIXEL_BIT (0x1 << 0)
++
++#define SHIFT_MCLKDIV 12
++
++/* control reg 3 */
++#define BIT_FRMCNT (0xFFFF << 16)
++#define BIT_FRMCNT_RST (0x1 << 15)
++#define BIT_DMA_REFLASH_RFF (0x1 << 14)
++#define BIT_DMA_REFLASH_SFF (0x1 << 13)
++#define BIT_DMA_REQ_EN_RFF (0x1 << 12)
++#define BIT_DMA_REQ_EN_SFF (0x1 << 11)
++#define BIT_STATFF_LEVEL (0x7 << 8)
++#define BIT_HRESP_ERR_EN (0x1 << 7)
++#define BIT_RXFF_LEVEL (0x7 << 4)
++#define BIT_TWO_8BIT_SENSOR (0x1 << 3)
++#define BIT_ZERO_PACK_EN (0x1 << 2)
++#define BIT_ECC_INT_EN (0x1 << 1)
++#define BIT_ECC_AUTO_EN (0x1 << 0)
++
++#define SHIFT_FRMCNT 16
++#define SHIFT_RXFIFO_LEVEL 4
++
++/* csi status reg */
++#define BIT_ADDR_CH_ERR_INT (0x1 << 28)
++#define BIT_FIELD0_INT (0x1 << 27)
++#define BIT_FIELD1_INT (0x1 << 26)
++#define BIT_SFF_OR_INT (0x1 << 25)
++#define BIT_RFF_OR_INT (0x1 << 24)
++#define BIT_DMA_TSF_DONE_SFF (0x1 << 22)
++#define BIT_STATFF_INT (0x1 << 21)
++#define BIT_DMA_TSF_DONE_FB2 (0x1 << 20)
++#define BIT_DMA_TSF_DONE_FB1 (0x1 << 19)
++#define BIT_RXFF_INT (0x1 << 18)
++#define BIT_EOF_INT (0x1 << 17)
++#define BIT_SOF_INT (0x1 << 16)
++#define BIT_F2_INT (0x1 << 15)
++#define BIT_F1_INT (0x1 << 14)
++#define BIT_COF_INT (0x1 << 13)
++#define BIT_HRESP_ERR_INT (0x1 << 7)
++#define BIT_ECC_INT (0x1 << 1)
++#define BIT_DRDY (0x1 << 0)
++
++/* csi control reg 18 */
++#define BIT_CSI_ENABLE (0x1 << 31)
++#define BIT_BASEADDR_CHG_ERR_EN (0x1 << 9)
++#define BIT_BASEADDR_SWITCH_SEL (0x1 << 5)
++#define BIT_BASEADDR_SWITCH_EN (0x1 << 4)
++#define BIT_PARALLEL24_EN (0x1 << 3)
++#define BIT_DEINTERLACE_EN (0x1 << 2)
++#define BIT_TVDECODER_IN_EN (0x1 << 1)
++#define BIT_NTSC_EN (0x1 << 0)
++
++#define CSI_MCLK_VF 1
++#define CSI_MCLK_ENC 2
++#define CSI_MCLK_RAW 4
++#define CSI_MCLK_I2C 8
++
++#define CSI_CSICR1 0x0
++#define CSI_CSICR2 0x4
++#define CSI_CSICR3 0x8
++#define CSI_STATFIFO 0xC
++#define CSI_CSIRXFIFO 0x10
++#define CSI_CSIRXCNT 0x14
++#define CSI_CSISR 0x18
++
++#define CSI_CSIDBG 0x1C
++#define CSI_CSIDMASA_STATFIFO 0x20
++#define CSI_CSIDMATS_STATFIFO 0x24
++#define CSI_CSIDMASA_FB1 0x28
++#define CSI_CSIDMASA_FB2 0x2C
++#define CSI_CSIFBUF_PARA 0x30
++#define CSI_CSIIMAG_PARA 0x34
++
++#define CSI_CSICR18 0x48
++#define CSI_CSICR19 0x4c
++
++#define NUM_FORMATS ARRAY_SIZE(formats)
++#define MX6SX_MAX_SENSORS 1
++
++struct csi_signal_cfg_t {
++ unsigned data_width:3;
++ unsigned clk_mode:2;
++ unsigned ext_vsync:1;
++ unsigned Vsync_pol:1;
++ unsigned Hsync_pol:1;
++ unsigned pixclk_pol:1;
++ unsigned data_pol:1;
++ unsigned sens_clksrc:1;
++};
++
++struct csi_config_t {
++ /* control reg 1 */
++ unsigned int swap16_en:1;
++ unsigned int ext_vsync:1;
++ unsigned int eof_int_en:1;
++ unsigned int prp_if_en:1;
++ unsigned int ccir_mode:1;
++ unsigned int cof_int_en:1;
++ unsigned int sf_or_inten:1;
++ unsigned int rf_or_inten:1;
++ unsigned int sff_dma_done_inten:1;
++ unsigned int statff_inten:1;
++ unsigned int fb2_dma_done_inten:1;
++ unsigned int fb1_dma_done_inten:1;
++ unsigned int rxff_inten:1;
++ unsigned int sof_pol:1;
++ unsigned int sof_inten:1;
++ unsigned int mclkdiv:4;
++ unsigned int hsync_pol:1;
++ unsigned int ccir_en:1;
++ unsigned int mclken:1;
++ unsigned int fcc:1;
++ unsigned int pack_dir:1;
++ unsigned int gclk_mode:1;
++ unsigned int inv_data:1;
++ unsigned int inv_pclk:1;
++ unsigned int redge:1;
++ unsigned int pixel_bit:1;
++
++ /* control reg 3 */
++ unsigned int frmcnt:16;
++ unsigned int frame_reset:1;
++ unsigned int dma_reflash_rff:1;
++ unsigned int dma_reflash_sff:1;
++ unsigned int dma_req_en_rff:1;
++ unsigned int dma_req_en_sff:1;
++ unsigned int statff_level:3;
++ unsigned int hresp_err_en:1;
++ unsigned int rxff_level:3;
++ unsigned int two_8bit_sensor:1;
++ unsigned int zero_pack_en:1;
++ unsigned int ecc_int_en:1;
++ unsigned int ecc_auto_en:1;
++ /* fifo counter */
++ unsigned int rxcnt;
++};
++
++/*
++ * Basic structures
++ */
++struct mx6s_fmt {
++ char name[32];
++ u32 fourcc; /* v4l2 format id */
++ u32 pixelformat;
++ enum v4l2_mbus_pixelcode mbus_code;
++ int bpp;
++};
++
++static struct mx6s_fmt formats[] = {
++ {
++ .name = "UYVY-16",
++ .fourcc = V4L2_PIX_FMT_UYVY,
++ .pixelformat = V4L2_PIX_FMT_UYVY,
++ .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
++ .bpp = 2,
++ }, {
++ .name = "YUYV-16",
++ .fourcc = V4L2_PIX_FMT_YUYV,
++ .pixelformat = V4L2_PIX_FMT_YUYV,
++ .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
++ .bpp = 2,
++ }, {
++ .name = "YUV32 (X-Y-U-V)",
++ .fourcc = V4L2_PIX_FMT_YUV32,
++ .pixelformat = V4L2_PIX_FMT_YUV32,
++ .mbus_code = V4L2_MBUS_FMT_AYUV8_1X32,
++ .bpp = 4,
++ }
++};
++
++struct mx6s_buf_internal {
++ struct list_head queue;
++ int bufnum;
++ bool discard;
++};
++
++/* buffer for one video frame */
++struct mx6s_buffer {
++ /* common v4l buffer stuff -- must be first */
++ struct vb2_buffer vb;
++ struct mx6s_buf_internal internal;
++};
++
++struct mx6s_csi_dev {
++ struct device *dev;
++ struct video_device *vdev;
++ struct v4l2_subdev *sd;
++ struct v4l2_device v4l2_dev;
++
++ struct vb2_queue vb2_vidq;
++ struct vb2_alloc_ctx *alloc_ctx;
++ struct v4l2_ctrl_handler ctrl_handler;
++
++ struct mutex lock;
++ spinlock_t slock;
++
++ /* clock */
++ struct clk *clk_disp_axi;
++ struct clk *clk_disp_dcic;
++ struct clk *clk_csi_mclk;
++
++ void __iomem *regbase;
++ int irq;
++
++ u32 type;
++ u32 bytesperline;
++ v4l2_std_id std;
++ struct mx6s_fmt *fmt;
++ struct v4l2_pix_format pix;
++ enum v4l2_mbus_pixelcode mbus_code;
++
++ unsigned int frame_count;
++
++ struct list_head capture;
++ struct list_head active_bufs;
++ struct list_head discard;
++
++ void *discard_buffer;
++ dma_addr_t discard_buffer_dma;
++ size_t discard_size;
++ struct mx6s_buf_internal buf_discard[2];
++
++ struct v4l2_async_subdev asd;
++ struct v4l2_async_notifier subdev_notifier;
++ struct v4l2_async_subdev *async_subdevs[2];
++};
++
++static inline int csi_read(struct mx6s_csi_dev *csi, unsigned int offset)
++{
++ return __raw_readl(csi->regbase + offset);
++}
++static inline void csi_write(struct mx6s_csi_dev *csi, unsigned int value,
++ unsigned int offset)
++{
++ __raw_writel(value, csi->regbase + offset);
++}
++
++static inline struct mx6s_csi_dev
++ *notifier_to_mx6s_dev(struct v4l2_async_notifier *n)
++{
++ return container_of(n, struct mx6s_csi_dev, subdev_notifier);
++}
++
++struct mx6s_fmt *format_by_fourcc(int fourcc)
++{
++ int i;
++
++ for (i = 0; i < NUM_FORMATS; i++) {
++ if (formats[i].pixelformat == fourcc)
++ return formats + i;
++ }
++
++ pr_err("unknown pixelformat:'%4.4s'\n", (char *)&fourcc);
++ return NULL;
++}
++
++struct mx6s_fmt *format_by_mbus(enum v4l2_mbus_pixelcode code)
++{
++ int i;
++
++ for (i = 0; i < NUM_FORMATS; i++) {
++ if (formats[i].mbus_code == code)
++ return formats + i;
++ }
++
++ pr_err("unknown pixelformat:'%4.4s'\n", (char *)&code);
++ return NULL;
++}
++
++static struct mx6s_buffer *mx6s_ibuf_to_buf(struct mx6s_buf_internal *int_buf)
++{
++ return container_of(int_buf, struct mx6s_buffer, internal);
++}
++
++void csi_clk_enable(struct mx6s_csi_dev *csi_dev)
++{
++ clk_prepare_enable(csi_dev->clk_disp_axi);
++ clk_prepare_enable(csi_dev->clk_disp_dcic);
++ clk_prepare_enable(csi_dev->clk_csi_mclk);
++}
++
++void csi_clk_disable(struct mx6s_csi_dev *csi_dev)
++{
++ clk_disable_unprepare(csi_dev->clk_csi_mclk);
++ clk_disable_unprepare(csi_dev->clk_disp_dcic);
++ clk_disable_unprepare(csi_dev->clk_disp_axi);
++}
++
++static void csihw_reset(struct mx6s_csi_dev *csi_dev)
++{
++ __raw_writel(__raw_readl(csi_dev->regbase + CSI_CSICR3)
++ | BIT_FRMCNT_RST,
++ csi_dev->regbase + CSI_CSICR3);
++
++ __raw_writel(CSICR1_RESET_VAL, csi_dev->regbase + CSI_CSICR1);
++ __raw_writel(CSICR2_RESET_VAL, csi_dev->regbase + CSI_CSICR2);
++ __raw_writel(CSICR3_RESET_VAL, csi_dev->regbase + CSI_CSICR3);
++}
++
++static void csisw_reset(struct mx6s_csi_dev *csi_dev)
++{
++ int cr1, cr3, cr18, isr;
++
++ /* Disable csi */
++ cr18 = csi_read(csi_dev, CSI_CSICR18);
++ cr18 &= ~BIT_CSI_ENABLE;
++ csi_write(csi_dev, cr18, CSI_CSICR18);
++
++ /* Clear RX FIFO */
++ cr1 = csi_read(csi_dev, CSI_CSICR1);
++ csi_write(csi_dev, cr1 & ~BIT_FCC, CSI_CSICR1);
++ cr1 = csi_read(csi_dev, CSI_CSICR1);
++ csi_write(csi_dev, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
++
++ /* DMA reflash */
++ cr3 = csi_read(csi_dev, CSI_CSICR3);
++ cr3 |= BIT_DMA_REFLASH_RFF | BIT_FRMCNT_RST;
++ csi_write(csi_dev, cr3, CSI_CSICR3);
++
++ msleep(2);
++
++ cr1 = csi_read(csi_dev, CSI_CSICR1);
++ csi_write(csi_dev, cr1 | BIT_FCC, CSI_CSICR1);
++
++ isr = csi_read(csi_dev, CSI_CSISR);
++ csi_write(csi_dev, isr, CSI_CSISR);
++
++ /* Ensable csi */
++ cr18 |= BIT_CSI_ENABLE;
++ csi_write(csi_dev, cr18, CSI_CSICR18);
++}
++
++/*!
++ * csi_init_interface
++ * Init csi interface
++ */
++static void csi_init_interface(struct mx6s_csi_dev *csi_dev)
++{
++ unsigned int val = 0;
++ unsigned int imag_para;
++
++ val |= BIT_SOF_POL;
++ val |= BIT_REDGE;
++ val |= BIT_GCLK_MODE;
++ val |= BIT_HSYNC_POL;
++ val |= BIT_FCC;
++ val |= 1 << SHIFT_MCLKDIV;
++ val |= BIT_MCLKEN;
++ __raw_writel(val, csi_dev->regbase + CSI_CSICR1);
++
++ imag_para = (640 << 16) | 960;
++ __raw_writel(imag_para, csi_dev->regbase + CSI_CSIIMAG_PARA);
++
++ val = BIT_DMA_REFLASH_RFF;
++ __raw_writel(val, csi_dev->regbase + CSI_CSICR3);
++}
++
++static void csi_enable_int(struct mx6s_csi_dev *csi_dev, int arg)
++{
++ unsigned long cr1 = __raw_readl(csi_dev->regbase + CSI_CSICR1);
++
++ cr1 |= BIT_SOF_INTEN;
++ if (arg == 1) {
++ /* still capture needs DMA intterrupt */
++ cr1 |= BIT_FB1_DMA_DONE_INTEN;
++ cr1 |= BIT_FB2_DMA_DONE_INTEN;
++ }
++ __raw_writel(cr1, csi_dev->regbase + CSI_CSICR1);
++}
++
++static void csi_disable_int(struct mx6s_csi_dev *csi_dev)
++{
++ unsigned long cr1 = __raw_readl(csi_dev->regbase + CSI_CSICR1);
++
++ cr1 &= ~BIT_SOF_INTEN;
++ cr1 &= ~BIT_FB1_DMA_DONE_INTEN;
++ cr1 &= ~BIT_FB2_DMA_DONE_INTEN;
++ __raw_writel(cr1, csi_dev->regbase + CSI_CSICR1);
++}
++
++static void csi_enable(struct mx6s_csi_dev *csi_dev, int arg)
++{
++ unsigned long cr = __raw_readl(csi_dev->regbase + CSI_CSICR18);
++
++ if (arg == 1)
++ cr |= BIT_CSI_ENABLE;
++ else
++ cr &= ~BIT_CSI_ENABLE;
++ __raw_writel(cr, csi_dev->regbase + CSI_CSICR18);
++}
++
++static void csi_buf_stride_set(struct mx6s_csi_dev *csi_dev, u32 stride)
++{
++ __raw_writel(stride, csi_dev->regbase + CSI_CSIFBUF_PARA);
++}
++
++static void csi_deinterlace_enable(struct mx6s_csi_dev *csi_dev, bool enable)
++{
++ unsigned long cr18 = __raw_readl(csi_dev->regbase + CSI_CSICR18);
++
++ if (enable == true)
++ cr18 |= BIT_DEINTERLACE_EN;
++ else
++ cr18 &= ~BIT_DEINTERLACE_EN;
++
++ __raw_writel(cr18, csi_dev->regbase + CSI_CSICR18);
++}
++
++static void csi_deinterlace_mode(struct mx6s_csi_dev *csi_dev, int mode)
++{
++ unsigned long cr18 = __raw_readl(csi_dev->regbase + CSI_CSICR18);
++
++ if (mode == V4L2_STD_NTSC)
++ cr18 |= BIT_NTSC_EN;
++ else
++ cr18 &= ~BIT_NTSC_EN;
++
++ __raw_writel(cr18, csi_dev->regbase + CSI_CSICR18);
++}
++
++static void csi_tvdec_enable(struct mx6s_csi_dev *csi_dev, bool enable)
++{
++ unsigned long cr18 = __raw_readl(csi_dev->regbase + CSI_CSICR18);
++ unsigned long cr1 = __raw_readl(csi_dev->regbase + CSI_CSICR1);
++
++ if (enable == true) {
++ cr18 |= (BIT_TVDECODER_IN_EN |
++ BIT_BASEADDR_SWITCH_EN |
++ BIT_BASEADDR_SWITCH_SEL |
++ BIT_BASEADDR_CHG_ERR_EN);
++ cr1 |= BIT_CCIR_MODE;
++ cr1 &= ~(BIT_SOF_POL | BIT_REDGE);
++ } else {
++ cr18 &= ~(BIT_TVDECODER_IN_EN |
++ BIT_BASEADDR_SWITCH_EN |
++ BIT_BASEADDR_SWITCH_SEL |
++ BIT_BASEADDR_CHG_ERR_EN);
++ cr1 &= ~BIT_CCIR_MODE;
++ cr1 |= BIT_SOF_POL | BIT_REDGE;
++ }
++
++ __raw_writel(cr18, csi_dev->regbase + CSI_CSICR18);
++ __raw_writel(cr1, csi_dev->regbase + CSI_CSICR1);
++}
++
++static void csi_dmareq_rff_enable(struct mx6s_csi_dev *csi_dev)
++{
++ unsigned long cr3 = __raw_readl(csi_dev->regbase + CSI_CSICR3);
++ unsigned long cr2 = __raw_readl(csi_dev->regbase + CSI_CSICR2);
++
++ /* Burst Type of DMA Transfer from RxFIFO. INCR16 */
++ cr2 |= 0xC0000000;
++
++ cr3 |= BIT_DMA_REQ_EN_RFF;
++ cr3 |= BIT_HRESP_ERR_EN;
++ cr3 &= ~BIT_RXFF_LEVEL;
++ cr3 |= 0x2 << 4;
++
++ __raw_writel(cr3, csi_dev->regbase + CSI_CSICR3);
++ __raw_writel(cr2, csi_dev->regbase + CSI_CSICR2);
++}
++
++static void csi_dmareq_rff_disable(struct mx6s_csi_dev *csi_dev)
++{
++ unsigned long cr3 = __raw_readl(csi_dev->regbase + CSI_CSICR3);
++
++ cr3 &= ~BIT_DMA_REQ_EN_RFF;
++ cr3 &= ~BIT_HRESP_ERR_EN;
++ __raw_writel(cr3, csi_dev->regbase + CSI_CSICR3);
++}
++
++static void csi_set_32bit_imagpara(struct mx6s_csi_dev *csi,
++ int width, int height)
++{
++ int imag_para = 0;
++ unsigned long cr3 = __raw_readl(csi->regbase + CSI_CSICR3);
++
++ imag_para = (width << 16) | height;
++ __raw_writel(imag_para, csi->regbase + CSI_CSIIMAG_PARA);
++
++ /* reflash the embeded DMA controller */
++ __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, csi->regbase + CSI_CSICR3);
++}
++
++static void csi_set_16bit_imagpara(struct mx6s_csi_dev *csi,
++ int width, int height)
++{
++ int imag_para = 0;
++ unsigned long cr3 = __raw_readl(csi->regbase + CSI_CSICR3);
++
++ imag_para = (width << 16) | (height * 2);
++ __raw_writel(imag_para, csi->regbase + CSI_CSIIMAG_PARA);
++
++ /* reflash the embeded DMA controller */
++ __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, csi->regbase + CSI_CSICR3);
++}
++
++/*
++ * Videobuf operations
++ */
++static int mx6s_videobuf_setup(struct vb2_queue *vq,
++ const struct v4l2_format *fmt,
++ unsigned int *count, unsigned int *num_planes,
++ unsigned int sizes[], void *alloc_ctxs[])
++{
++ struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vq);
++
++ dev_dbg(csi_dev->dev, "count=%d, size=%d\n", *count, sizes[0]);
++
++ /* TODO: support for VIDIOC_CREATE_BUFS not ready */
++ if (fmt != NULL)
++ return -ENOTTY;
++
++ alloc_ctxs[0] = csi_dev->alloc_ctx;
++
++ sizes[0] = csi_dev->pix.sizeimage;
++
++ pr_debug("size=%d\n", sizes[0]);
++ if (0 == *count)
++ *count = 32;
++ if (!*num_planes &&
++ sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
++ *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
++
++ *num_planes = 1;
++
++ return 0;
++}
++
++static int mx6s_videobuf_prepare(struct vb2_buffer *vb)
++{
++ struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vb->vb2_queue);
++ int ret = 0;
++
++ dev_dbg(csi_dev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
++ vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
++
++#ifdef DEBUG
++ /*
++ * This can be useful if you want to see if we actually fill
++ * the buffer with something
++ */
++ memset((void *)vb2_plane_vaddr(vb, 0),
++ 0xaa, vb2_get_plane_payload(vb, 0));
++#endif
++
++ vb2_set_plane_payload(vb, 0, csi_dev->pix.sizeimage);
++ if (vb2_plane_vaddr(vb, 0) &&
++ vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
++ ret = -EINVAL;
++ goto out;
++ }
++
++ return 0;
++
++out:
++ return ret;
++}
++
++static void mx6s_videobuf_queue(struct vb2_buffer *vb)
++{
++ struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vb->vb2_queue);
++ struct mx6s_buffer *buf = container_of(vb, struct mx6s_buffer, vb);
++ unsigned long flags;
++
++ dev_dbg(csi_dev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
++ vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
++
++ spin_lock_irqsave(&csi_dev->slock, flags);
++
++ list_add_tail(&buf->internal.queue, &csi_dev->capture);
++
++ spin_unlock_irqrestore(&csi_dev->slock, flags);
++}
++
++static void mx6s_update_csi_buf(struct mx6s_csi_dev *csi_dev,
++ unsigned long phys, int bufnum)
++{
++ if (bufnum == 1)
++ csi_write(csi_dev, phys, CSI_CSIDMASA_FB2);
++ else
++ csi_write(csi_dev, phys, CSI_CSIDMASA_FB1);
++}
++
++static void mx6s_csi_init(struct mx6s_csi_dev *csi_dev)
++{
++ csi_clk_enable(csi_dev);
++ csihw_reset(csi_dev);
++ csi_init_interface(csi_dev);
++ csi_dmareq_rff_disable(csi_dev);
++}
++
++static void mx6s_csi_deinit(struct mx6s_csi_dev *csi_dev)
++{
++ csihw_reset(csi_dev);
++ csi_init_interface(csi_dev);
++ csi_dmareq_rff_disable(csi_dev);
++ csi_clk_disable(csi_dev);
++}
++
++static void mx6s_csi_enable(struct mx6s_csi_dev *csi_dev)
++{
++ struct v4l2_pix_format *pix = &csi_dev->pix;
++
++ csisw_reset(csi_dev);
++
++ if (pix->field == V4L2_FIELD_INTERLACED)
++ csi_tvdec_enable(csi_dev, true);
++
++ csi_dmareq_rff_enable(csi_dev);
++ csi_enable_int(csi_dev, 1);
++ csi_enable(csi_dev, 1);
++
++}
++
++static void mx6s_csi_disable(struct mx6s_csi_dev *csi_dev)
++{
++ struct v4l2_pix_format *pix = &csi_dev->pix;
++
++ csi_dmareq_rff_disable(csi_dev);
++ csi_disable_int(csi_dev);
++
++ /* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */
++ csi_write(csi_dev, 0, CSI_CSIDMASA_FB1);
++ csi_write(csi_dev, 0, CSI_CSIDMASA_FB2);
++
++ csi_buf_stride_set(csi_dev, 0);
++
++ if (pix->field == V4L2_FIELD_INTERLACED) {
++ csi_deinterlace_enable(csi_dev, false);
++ csi_tvdec_enable(csi_dev, false);
++ }
++
++ csi_enable(csi_dev, 0);
++}
++
++static int mx6s_configure_csi(struct mx6s_csi_dev *csi_dev)
++{
++ struct v4l2_pix_format *pix = &csi_dev->pix;
++
++ if (pix->field == V4L2_FIELD_INTERLACED) {
++ csi_deinterlace_enable(csi_dev, true);
++ csi_buf_stride_set(csi_dev, csi_dev->pix.width);
++ csi_deinterlace_mode(csi_dev, csi_dev->std);
++ } else {
++ csi_deinterlace_enable(csi_dev, false);
++ csi_buf_stride_set(csi_dev, 0);
++ }
++
++ switch (csi_dev->fmt->pixelformat) {
++ case V4L2_PIX_FMT_YUV32:
++ csi_set_32bit_imagpara(csi_dev, pix->width, pix->height);
++ break;
++ case V4L2_PIX_FMT_UYVY:
++ csi_set_16bit_imagpara(csi_dev, pix->width, pix->height);
++ break;
++ case V4L2_PIX_FMT_YUYV:
++ csi_set_16bit_imagpara(csi_dev, pix->width, pix->height);
++ break;
++ default:
++ pr_debug(" case not supported\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int mx6s_start_streaming(struct vb2_queue *vq, unsigned int count)
++{
++ struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vq);
++ struct vb2_buffer *vb;
++ struct mx6s_buffer *buf;
++ unsigned long phys;
++ unsigned long flags;
++
++ if (count < 2)
++ return -ENOBUFS;
++
++ /*
++ * I didn't manage to properly enable/disable
++ * a per frame basis during running transfers,
++ * thus we allocate a buffer here and use it to
++ * discard frames when no buffer is available.
++ * Feel free to work on this ;)
++ */
++ csi_dev->discard_size = csi_dev->pix.sizeimage;
++ csi_dev->discard_buffer = dma_alloc_coherent(csi_dev->v4l2_dev.dev,
++ PAGE_ALIGN(csi_dev->discard_size),
++ &csi_dev->discard_buffer_dma,
++ GFP_DMA | GFP_KERNEL);
++ if (!csi_dev->discard_buffer)
++ return -ENOMEM;
++
++ spin_lock_irqsave(&csi_dev->slock, flags);
++
++ csi_dev->buf_discard[0].discard = true;
++ list_add_tail(&csi_dev->buf_discard[0].queue,
++ &csi_dev->discard);
++
++ csi_dev->buf_discard[1].discard = true;
++ list_add_tail(&csi_dev->buf_discard[1].queue,
++ &csi_dev->discard);
++
++ /* csi buf 0 */
++ buf = list_first_entry(&csi_dev->capture, struct mx6s_buffer,
++ internal.queue);
++ buf->internal.bufnum = 0;
++ vb = &buf->vb;
++
++ phys = vb2_dma_contig_plane_dma_addr(vb, 0);
++
++ mx6s_update_csi_buf(csi_dev, phys, buf->internal.bufnum);
++ list_move_tail(csi_dev->capture.next, &csi_dev->active_bufs);
++
++ /* csi buf 1 */
++ buf = list_first_entry(&csi_dev->capture, struct mx6s_buffer,
++ internal.queue);
++ buf->internal.bufnum = 1;
++ vb = &buf->vb;
++
++ phys = vb2_dma_contig_plane_dma_addr(vb, 0);
++ mx6s_update_csi_buf(csi_dev, phys, buf->internal.bufnum);
++ list_move_tail(csi_dev->capture.next, &csi_dev->active_bufs);
++
++ spin_unlock_irqrestore(&csi_dev->slock, flags);
++
++ mx6s_csi_enable(csi_dev);
++
++ return 0;
++}
++
++static int mx6s_stop_streaming(struct vb2_queue *vq)
++{
++ struct mx6s_csi_dev *csi_dev = vb2_get_drv_priv(vq);
++ unsigned long flags;
++ struct mx6s_buffer *buf, *tmp;
++ void *b;
++
++ mx6s_csi_disable(csi_dev);
++
++ spin_lock_irqsave(&csi_dev->slock, flags);
++
++
++ list_for_each_entry_safe(buf, tmp,
++ &csi_dev->active_bufs, internal.queue) {
++ list_del_init(&buf->internal.queue);
++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
++ }
++
++ INIT_LIST_HEAD(&csi_dev->capture);
++ INIT_LIST_HEAD(&csi_dev->active_bufs);
++ INIT_LIST_HEAD(&csi_dev->discard);
++
++ b = csi_dev->discard_buffer;
++ csi_dev->discard_buffer = NULL;
++
++ spin_unlock_irqrestore(&csi_dev->slock, flags);
++
++ dma_free_coherent(csi_dev->v4l2_dev.dev,
++ csi_dev->discard_size, b,
++ csi_dev->discard_buffer_dma);
++
++ return 0;
++}
++
++static struct vb2_ops mx6s_videobuf_ops = {
++ .queue_setup = mx6s_videobuf_setup,
++ .buf_prepare = mx6s_videobuf_prepare,
++ .buf_queue = mx6s_videobuf_queue,
++ .wait_prepare = vb2_ops_wait_prepare,
++ .wait_finish = vb2_ops_wait_finish,
++ .start_streaming = mx6s_start_streaming,
++ .stop_streaming = mx6s_stop_streaming,
++};
++
++static void mx6s_csi_frame_done(struct mx6s_csi_dev *csi_dev,
++ int bufnum, bool err)
++{
++ struct mx6s_buf_internal *ibuf;
++ struct mx6s_buffer *buf;
++ struct vb2_buffer *vb;
++ unsigned long phys;
++
++ ibuf = list_first_entry(&csi_dev->active_bufs, struct mx6s_buf_internal,
++ queue);
++
++ if (ibuf->discard) {
++ /*
++ * Discard buffer must not be returned to user space.
++ * Just return it to the discard queue.
++ */
++ list_move_tail(csi_dev->active_bufs.next, &csi_dev->discard);
++ } else {
++ buf = mx6s_ibuf_to_buf(ibuf);
++
++ vb = &buf->vb;
++ phys = vb2_dma_contig_plane_dma_addr(vb, 0);
++ if (bufnum == 1) {
++ if (csi_read(csi_dev, CSI_CSIDMASA_FB2) != phys) {
++ dev_err(csi_dev->dev, "%lx != %x\n", phys,
++ csi_read(csi_dev, CSI_CSIDMASA_FB2));
++ }
++ } else {
++ if (csi_read(csi_dev, CSI_CSIDMASA_FB1) != phys) {
++ dev_err(csi_dev->dev, "%lx != %x\n", phys,
++ csi_read(csi_dev, CSI_CSIDMASA_FB1));
++ }
++ }
++ dev_dbg(csi_dev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
++ vb2_plane_vaddr(vb, 0),
++ vb2_get_plane_payload(vb, 0));
++
++ list_del_init(&buf->internal.queue);
++ v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
++ vb->v4l2_buf.sequence = csi_dev->frame_count;
++ if (err)
++ vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
++ else
++ vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
++ }
++
++ csi_dev->frame_count++;
++
++ /* Config discard buffer to active_bufs */
++ if (list_empty(&csi_dev->capture)) {
++ if (list_empty(&csi_dev->discard)) {
++ dev_warn(csi_dev->dev,
++ "%s: trying to access empty discard list\n",
++ __func__);
++ return;
++ }
++
++ ibuf = list_first_entry(&csi_dev->discard,
++ struct mx6s_buf_internal, queue);
++ ibuf->bufnum = bufnum;
++
++ list_move_tail(csi_dev->discard.next, &csi_dev->active_bufs);
++
++ mx6s_update_csi_buf(csi_dev,
++ csi_dev->discard_buffer_dma, bufnum);
++ return;
++ }
++
++ buf = list_first_entry(&csi_dev->capture, struct mx6s_buffer,
++ internal.queue);
++
++ buf->internal.bufnum = bufnum;
++
++ list_move_tail(csi_dev->capture.next, &csi_dev->active_bufs);
++
++ vb = &buf->vb;
++
++ phys = vb2_dma_contig_plane_dma_addr(vb, 0);
++ mx6s_update_csi_buf(csi_dev, phys, bufnum);
++}
++
++static irqreturn_t mx6s_csi_irq_handler(int irq, void *data)
++{
++ struct mx6s_csi_dev *csi_dev = data;
++ unsigned long status;
++ u32 cr1, cr3, cr18;
++
++ spin_lock(&csi_dev->slock);
++
++ status = csi_read(csi_dev, CSI_CSISR);
++ csi_write(csi_dev, status, CSI_CSISR);
++
++ if (list_empty(&csi_dev->active_bufs)) {
++ dev_warn(csi_dev->dev,
++ "%s: called while active list is empty\n",
++ __func__);
++
++ spin_unlock(&csi_dev->slock);
++ return IRQ_HANDLED;
++ }
++
++ if (status & BIT_HRESP_ERR_INT) {
++ /* software reset */
++
++ /* Disable csi */
++ cr18 = csi_read(csi_dev, CSI_CSICR18);
++ cr18 &= ~BIT_CSI_ENABLE;
++ csi_write(csi_dev, cr18, CSI_CSICR18);
++
++ /* Clear RX FIFO */
++ cr1 = csi_read(csi_dev, CSI_CSICR1);
++ csi_write(csi_dev, cr1 & ~BIT_FCC, CSI_CSICR1);
++ cr1 = csi_read(csi_dev, CSI_CSICR1);
++ csi_write(csi_dev, cr1 | BIT_CLR_RXFIFO, CSI_CSICR1);
++
++ cr1 = csi_read(csi_dev, CSI_CSICR1);
++ csi_write(csi_dev, cr1 | BIT_FCC, CSI_CSICR1);
++
++ /* DMA reflash */
++ cr3 = csi_read(csi_dev, CSI_CSICR3);
++ cr3 |= BIT_DMA_REFLASH_RFF;
++ csi_write(csi_dev, cr3, CSI_CSICR3);
++
++ /* Ensable csi */
++ cr18 |= BIT_CSI_ENABLE;
++ csi_write(csi_dev, cr18, CSI_CSICR18);
++
++ pr_warning("Hresponse error is detected.\n");
++ }
++
++ if (status & BIT_ADDR_CH_ERR_INT) {
++ /* Disable csi */
++ cr18 = csi_read(csi_dev, CSI_CSICR18);
++ cr18 &= ~BIT_CSI_ENABLE;
++ csi_write(csi_dev, cr18, CSI_CSICR18);
++
++ /* DMA reflash */
++ cr3 = csi_read(csi_dev, CSI_CSICR3);
++ cr3 |= BIT_DMA_REFLASH_RFF;
++ csi_write(csi_dev, cr3, CSI_CSICR3);
++
++ /* Ensable csi */
++ cr18 |= BIT_CSI_ENABLE;
++ csi_write(csi_dev, cr18, CSI_CSICR18);
++
++ pr_debug("base address switching Change Err.\n");
++ }
++
++ if ((status & BIT_DMA_TSF_DONE_FB1) &&
++ (status & BIT_DMA_TSF_DONE_FB2)) {
++ /* For both FB1 and FB2 interrupter bits set case,
++ * CSI DMA is work in one of FB1 and FB2 buffer,
++ * but software can not know the state.
++ * Skip it to avoid base address updated
++ * when csi work in field0 and field1 will write to
++ * new base address.
++ * PDM TKT230775 */
++ pr_debug("Skip two frames\n");
++ } else if (status & BIT_DMA_TSF_DONE_FB1) {
++ mx6s_csi_frame_done(csi_dev, 0, false);
++ } else if (status & BIT_DMA_TSF_DONE_FB2) {
++ mx6s_csi_frame_done(csi_dev, 1, false);
++ }
++
++ spin_unlock(&csi_dev->slock);
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * File operations for the device
++ */
++static int mx6s_csi_open(struct file *file)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct vb2_queue *q = &csi_dev->vb2_vidq;
++ int ret = 0;
++
++ file->private_data = csi_dev;
++
++ if (mutex_lock_interruptible(&csi_dev->lock))
++ return -ERESTARTSYS;
++
++ csi_dev->alloc_ctx = vb2_dma_contig_init_ctx(csi_dev->dev);
++ if (IS_ERR(csi_dev->alloc_ctx))
++ goto unlock;
++
++ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ q->io_modes = VB2_MMAP | VB2_USERPTR;
++ q->drv_priv = csi_dev;
++ q->ops = &mx6s_videobuf_ops;
++ q->mem_ops = &vb2_dma_contig_memops;
++ q->buf_struct_size = sizeof(struct mx6s_buffer);
++ q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
++ q->lock = &csi_dev->lock;
++
++ ret = vb2_queue_init(q);
++ if (ret < 0)
++ goto eallocctx;
++
++ pm_runtime_get_sync(csi_dev->dev);
++
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ mx6s_csi_init(csi_dev);
++
++ mutex_unlock(&csi_dev->lock);
++
++ return ret;
++eallocctx:
++ vb2_dma_contig_cleanup_ctx(csi_dev->alloc_ctx);
++unlock:
++ mutex_unlock(&csi_dev->lock);
++ return ret;
++}
++
++static int mx6s_csi_close(struct file *file)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ mutex_lock(&csi_dev->lock);
++
++ vb2_queue_release(&csi_dev->vb2_vidq);
++
++ mx6s_csi_deinit(csi_dev);
++
++ vb2_dma_contig_cleanup_ctx(csi_dev->alloc_ctx);
++ mutex_unlock(&csi_dev->lock);
++
++ file->private_data = NULL;
++
++ release_bus_freq(BUS_FREQ_HIGH);
++
++ pm_runtime_put_sync_suspend(csi_dev->dev);
++ return 0;
++}
++
++static ssize_t mx6s_csi_read(struct file *file, char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ int ret;
++
++ dev_dbg(csi_dev->dev, "read called, buf %p\n", buf);
++
++ mutex_lock(&csi_dev->lock);
++ ret = vb2_read(&csi_dev->vb2_vidq, buf, count, ppos,
++ file->f_flags & O_NONBLOCK);
++ mutex_unlock(&csi_dev->lock);
++ return ret;
++}
++
++static int mx6s_csi_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ int ret;
++
++ if (mutex_lock_interruptible(&csi_dev->lock))
++ return -ERESTARTSYS;
++ ret = vb2_mmap(&csi_dev->vb2_vidq, vma);
++ mutex_unlock(&csi_dev->lock);
++
++ pr_debug("vma start=0x%08lx, size=%ld, ret=%d\n",
++ (unsigned long)vma->vm_start,
++ (unsigned long)vma->vm_end-(unsigned long)vma->vm_start,
++ ret);
++
++ return ret;
++}
++
++static struct v4l2_file_operations mx6s_csi_fops = {
++ .owner = THIS_MODULE,
++ .open = mx6s_csi_open,
++ .release = mx6s_csi_close,
++ .read = mx6s_csi_read,
++ .poll = vb2_fop_poll,
++ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
++ .mmap = mx6s_csi_mmap,
++};
++
++/*
++ * Video node IOCTLs
++ */
++static int mx6s_vidioc_enum_input(struct file *file, void *priv,
++ struct v4l2_input *inp)
++{
++ if (inp->index != 0)
++ return -EINVAL;
++
++ /* default is camera */
++ inp->type = V4L2_INPUT_TYPE_CAMERA;
++ strcpy(inp->name, "Camera");
++
++ return 0;
++}
++
++static int mx6s_vidioc_g_input(struct file *file, void *priv, unsigned int *i)
++{
++ *i = 0;
++
++ return 0;
++}
++
++static int mx6s_vidioc_s_input(struct file *file, void *priv, unsigned int i)
++{
++ if (i > 0)
++ return -EINVAL;
++
++ return 0;
++}
++
++static int mx6s_vidioc_querystd(struct file *file, void *priv, v4l2_std_id *a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ return v4l2_subdev_call(sd, video, querystd, a);
++}
++
++static int mx6s_vidioc_s_std(struct file *file, void *priv, v4l2_std_id a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ return v4l2_subdev_call(sd, core, s_std, a);
++}
++
++static int mx6s_vidioc_g_std(struct file *file, void *priv, v4l2_std_id *a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ return v4l2_subdev_call(sd, core, g_std, a);
++}
++
++static int mx6s_vidioc_reqbufs(struct file *file, void *priv,
++ struct v4l2_requestbuffers *p)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ WARN_ON(priv != file->private_data);
++
++ return vb2_reqbufs(&csi_dev->vb2_vidq, p);
++}
++
++static int mx6s_vidioc_querybuf(struct file *file, void *priv,
++ struct v4l2_buffer *p)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ int ret;
++
++ WARN_ON(priv != file->private_data);
++
++ ret = vb2_querybuf(&csi_dev->vb2_vidq, p);
++
++ if (!ret) {
++ /* return physical address */
++ struct vb2_buffer *vb = csi_dev->vb2_vidq.bufs[p->index];
++ if (p->flags & V4L2_BUF_FLAG_MAPPED)
++ p->m.offset = vb2_dma_contig_plane_dma_addr(vb, 0);
++ }
++ return ret;
++}
++
++static int mx6s_vidioc_qbuf(struct file *file, void *priv,
++ struct v4l2_buffer *p)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ WARN_ON(priv != file->private_data);
++
++ return vb2_qbuf(&csi_dev->vb2_vidq, p);
++}
++
++static int mx6s_vidioc_dqbuf(struct file *file, void *priv,
++ struct v4l2_buffer *p)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ WARN_ON(priv != file->private_data);
++
++ return vb2_dqbuf(&csi_dev->vb2_vidq, p, file->f_flags & O_NONBLOCK);
++}
++
++static int mx6s_vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_fmtdesc *f)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++ enum v4l2_mbus_pixelcode code;
++ struct mx6s_fmt *fmt;
++ int ret;
++
++ int index = f->index;
++
++ WARN_ON(priv != file->private_data);
++
++ ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, index, &code);
++ if (ret < 0)
++ /* no more formats */
++ return -EINVAL;
++
++
++ fmt = format_by_mbus(code);
++ if (!fmt) {
++ dev_err(csi_dev->dev, "mbus (0x%08x) invalid.", code);
++ return -EINVAL;
++ }
++
++ strlcpy(f->description, fmt->name, sizeof(f->description));
++ f->pixelformat = fmt->pixelformat;
++
++ return 0;
++}
++
++static int mx6s_vidioc_try_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++ struct v4l2_pix_format *pix = &f->fmt.pix;
++ struct v4l2_mbus_framefmt mbus_fmt;
++ struct mx6s_fmt *fmt;
++ int ret;
++
++ fmt = format_by_fourcc(f->fmt.pix.pixelformat);
++ if (!fmt) {
++ dev_err(csi_dev->dev, "Fourcc format (0x%08x) invalid.",
++ f->fmt.pix.pixelformat);
++ return -EINVAL;
++ }
++
++ v4l2_fill_mbus_format(&mbus_fmt, pix, fmt->mbus_code);
++ ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mbus_fmt);
++ v4l2_fill_pix_format(pix, &mbus_fmt);
++
++ if (pix->field != V4L2_FIELD_INTERLACED)
++ pix->field = V4L2_FIELD_NONE;
++
++ pix->sizeimage = fmt->bpp * pix->height * pix->width;
++ pix->bytesperline = fmt->bpp * pix->width;
++
++ return ret;
++}
++
++/*
++ * The real work of figuring out a workable format.
++ */
++
++static int mx6s_vidioc_s_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ int ret;
++
++ ret = mx6s_vidioc_try_fmt_vid_cap(file, csi_dev, f);
++ if (ret < 0)
++ return ret;
++
++ csi_dev->fmt = format_by_fourcc(f->fmt.pix.pixelformat);
++ csi_dev->pix.width = f->fmt.pix.width;
++ csi_dev->pix.height = f->fmt.pix.height;
++ csi_dev->pix.sizeimage = f->fmt.pix.sizeimage;
++ csi_dev->pix.field = f->fmt.pix.field;
++ csi_dev->type = f->type;
++ dev_dbg(csi_dev->dev, "set to pixelformat '%4.6s'\n",
++ (char *)&csi_dev->fmt->name);
++
++ /* Config csi */
++ mx6s_configure_csi(csi_dev);
++
++ return 0;
++}
++
++static int mx6s_vidioc_g_fmt_vid_cap(struct file *file, void *priv,
++ struct v4l2_format *f)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ WARN_ON(priv != file->private_data);
++
++ f->fmt.pix = csi_dev->pix;
++
++ return 0;
++}
++
++static int mx6s_vidioc_querycap(struct file *file, void *priv,
++ struct v4l2_capability *cap)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ WARN_ON(priv != file->private_data);
++
++ /* cap->name is set by the friendly caller:-> */
++ strlcpy(cap->driver, MX6S_CAM_DRV_NAME, sizeof(cap->driver));
++ strlcpy(cap->card, MX6S_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
++ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
++ dev_name(csi_dev->dev));
++
++ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++ return 0;
++}
++
++static int mx6s_vidioc_streamon(struct file *file, void *priv,
++ enum v4l2_buf_type i)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++ int ret;
++
++ WARN_ON(priv != file->private_data);
++
++ if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++
++ ret = vb2_streamon(&csi_dev->vb2_vidq, i);
++
++ if (!ret)
++ v4l2_subdev_call(sd, video, s_stream, 1);
++
++ return ret;
++}
++
++static int mx6s_vidioc_streamoff(struct file *file, void *priv,
++ enum v4l2_buf_type i)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ WARN_ON(priv != file->private_data);
++
++ if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++
++ /*
++ * This calls buf_release from host driver's videobuf_queue_ops for all
++ * remaining buffers. When the last buffer is freed, stop capture
++ */
++ vb2_streamoff(&csi_dev->vb2_vidq, i);
++
++ v4l2_subdev_call(sd, video, s_stream, 0);
++
++ return 0;
++}
++
++static int mx6s_vidioc_cropcap(struct file *file, void *fh,
++ struct v4l2_cropcap *a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++ dev_dbg(csi_dev->dev, "VIDIOC_CROPCAP not implemented\n");
++
++ return 0;
++}
++
++static int mx6s_vidioc_g_crop(struct file *file, void *priv,
++ struct v4l2_crop *a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++ dev_dbg(csi_dev->dev, "VIDIOC_G_CROP not implemented\n");
++
++ return 0;
++}
++
++static int mx6s_vidioc_s_crop(struct file *file, void *priv,
++ const struct v4l2_crop *a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++
++ if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++
++ dev_dbg(csi_dev->dev, "VIDIOC_S_CROP not implemented\n");
++
++ return 0;
++}
++
++static int mx6s_vidioc_g_parm(struct file *file, void *priv,
++ struct v4l2_streamparm *a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ return v4l2_subdev_call(sd, video, g_parm, a);
++}
++
++static int mx6s_vidioc_s_parm(struct file *file, void *priv,
++ struct v4l2_streamparm *a)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ return v4l2_subdev_call(sd, video, s_parm, a);
++}
++
++static int mx6s_vidioc_enum_framesizes(struct file *file, void *priv,
++ struct v4l2_frmsizeenum *fsize)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ return v4l2_subdev_call(sd, video, enum_framesizes, fsize);
++}
++
++static int mx6s_vidioc_enum_frameintervals(struct file *file, void *priv,
++ struct v4l2_frmivalenum *interval)
++{
++ struct mx6s_csi_dev *csi_dev = video_drvdata(file);
++ struct v4l2_subdev *sd = csi_dev->sd;
++
++ return v4l2_subdev_call(sd, video, enum_frameintervals, interval);
++}
++
++static const struct v4l2_ioctl_ops mx6s_csi_ioctl_ops = {
++ .vidioc_querycap = mx6s_vidioc_querycap,
++ .vidioc_enum_fmt_vid_cap = mx6s_vidioc_enum_fmt_vid_cap,
++ .vidioc_try_fmt_vid_cap = mx6s_vidioc_try_fmt_vid_cap,
++ .vidioc_g_fmt_vid_cap = mx6s_vidioc_g_fmt_vid_cap,
++ .vidioc_s_fmt_vid_cap = mx6s_vidioc_s_fmt_vid_cap,
++ .vidioc_cropcap = mx6s_vidioc_cropcap,
++ .vidioc_s_crop = mx6s_vidioc_s_crop,
++ .vidioc_g_crop = mx6s_vidioc_g_crop,
++ .vidioc_reqbufs = mx6s_vidioc_reqbufs,
++ .vidioc_querybuf = mx6s_vidioc_querybuf,
++ .vidioc_qbuf = mx6s_vidioc_qbuf,
++ .vidioc_dqbuf = mx6s_vidioc_dqbuf,
++ .vidioc_g_std = mx6s_vidioc_g_std,
++ .vidioc_s_std = mx6s_vidioc_s_std,
++ .vidioc_querystd = mx6s_vidioc_querystd,
++ .vidioc_enum_input = mx6s_vidioc_enum_input,
++ .vidioc_g_input = mx6s_vidioc_g_input,
++ .vidioc_s_input = mx6s_vidioc_s_input,
++ .vidioc_streamon = mx6s_vidioc_streamon,
++ .vidioc_streamoff = mx6s_vidioc_streamoff,
++ .vidioc_g_parm = mx6s_vidioc_g_parm,
++ .vidioc_s_parm = mx6s_vidioc_s_parm,
++ .vidioc_enum_framesizes = mx6s_vidioc_enum_framesizes,
++ .vidioc_enum_frameintervals = mx6s_vidioc_enum_frameintervals,
++};
++
++static int subdev_notifier_bound(struct v4l2_async_notifier *notifier,
++ struct v4l2_subdev *subdev,
++ struct v4l2_async_subdev *asd)
++{
++ struct mx6s_csi_dev *csi_dev = notifier_to_mx6s_dev(notifier);
++
++ /* Find platform data for this sensor subdev */
++ if (csi_dev->asd.match.of.node == subdev->dev->of_node)
++ csi_dev->sd = subdev;
++
++ if (subdev == NULL)
++ return -EINVAL;
++
++ v4l2_info(&csi_dev->v4l2_dev, "Registered sensor subdevice: %s\n",
++ subdev->name);
++
++ return 0;
++}
++
++static int mx6sx_register_subdevs(struct mx6s_csi_dev *csi_dev)
++{
++ struct device_node *parent = csi_dev->dev->of_node;
++ struct device_node *node, *port, *rem;
++ int ret;
++
++ /* Attach sensors linked to csi receivers */
++ for_each_available_child_of_node(parent, node) {
++ if (of_node_cmp(node->name, "port"))
++ continue;
++
++ /* The csi node can have only port subnode. */
++ port = of_get_next_child(node, NULL);
++ if (!port)
++ continue;
++ rem = v4l2_of_get_remote_port_parent(port);
++ of_node_put(port);
++ if (rem == NULL) {
++ v4l2_info(&csi_dev->v4l2_dev,
++ "Remote device at %s not found\n",
++ port->full_name);
++ return -1;
++ }
++
++ csi_dev->asd.match_type = V4L2_ASYNC_MATCH_OF;
++ csi_dev->asd.match.of.node = rem;
++ csi_dev->async_subdevs[0] = &csi_dev->asd;
++
++ of_node_put(rem);
++ break;
++ }
++
++ csi_dev->subdev_notifier.subdevs = csi_dev->async_subdevs;
++ csi_dev->subdev_notifier.num_subdevs = 1;
++ csi_dev->subdev_notifier.bound = subdev_notifier_bound;
++
++ ret = v4l2_async_notifier_register(&csi_dev->v4l2_dev,
++ &csi_dev->subdev_notifier);
++ if (ret)
++ dev_err(csi_dev->dev,
++ "Error register async notifier regoster\n");
++
++ return ret;
++}
++
++static int mx6s_csi_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct mx6s_csi_dev *csi_dev;
++ struct video_device *vdev;
++ struct resource *res;
++ int ret = 0;
++
++ dev_dbg(dev, "initialising\n");
++
++ /* Prepare our private structure */
++ csi_dev = devm_kzalloc(dev, sizeof(struct mx6s_csi_dev), GFP_ATOMIC);
++ if (!csi_dev) {
++ dev_err(dev, "Can't allocate private structure\n");
++ return -ENODEV;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ csi_dev->irq = platform_get_irq(pdev, 0);
++ if (res == NULL || csi_dev->irq < 0) {
++ dev_err(dev, "Missing platform resources data\n");
++ return -ENODEV;
++ }
++
++ csi_dev->regbase = devm_ioremap_resource(dev, res);
++ if (IS_ERR(csi_dev->regbase)) {
++ dev_err(dev, "Failed platform resources map\n");
++ return -ENODEV;
++ }
++
++ /* init video dma queues */
++ INIT_LIST_HEAD(&csi_dev->capture);
++ INIT_LIST_HEAD(&csi_dev->active_bufs);
++ INIT_LIST_HEAD(&csi_dev->discard);
++
++ csi_dev->clk_disp_axi = devm_clk_get(dev, "disp-axi");
++ if (IS_ERR(csi_dev->clk_disp_axi)) {
++ dev_err(dev, "Could not get csi axi clock\n");
++ return -ENODEV;
++ }
++
++ csi_dev->clk_disp_dcic = devm_clk_get(dev, "disp_dcic");
++ if (IS_ERR(csi_dev->clk_disp_dcic)) {
++ dev_err(dev, "Could not get disp dcic clock\n");
++ return -ENODEV;
++ }
++
++ csi_dev->clk_csi_mclk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(csi_dev->clk_csi_mclk)) {
++ dev_err(dev, "Could not get csi mclk clock\n");
++ return -ENODEV;
++ }
++
++ csi_dev->dev = dev;
++
++ snprintf(csi_dev->v4l2_dev.name,
++ sizeof(csi_dev->v4l2_dev.name), "CSI");
++
++ ret = v4l2_device_register(dev, &csi_dev->v4l2_dev);
++ if (ret < 0) {
++ dev_err(dev, "v4l2_device_register() failed: %d\n", ret);
++ return -ENODEV;
++ }
++
++ /* initialize locks */
++ mutex_init(&csi_dev->lock);
++ spin_lock_init(&csi_dev->slock);
++
++ /* Allocate memory for video device */
++ vdev = video_device_alloc();
++ if (vdev == NULL) {
++ ret = -ENOMEM;
++ goto err_vdev;
++ }
++
++ snprintf(vdev->name, sizeof(vdev->name), "mx6s-csi");
++
++ vdev->v4l2_dev = &csi_dev->v4l2_dev;
++ vdev->fops = &mx6s_csi_fops;
++ vdev->ioctl_ops = &mx6s_csi_ioctl_ops;
++ vdev->release = video_device_release;
++ vdev->lock = &csi_dev->lock;
++
++ vdev->queue = &csi_dev->vb2_vidq;
++
++ csi_dev->vdev = vdev;
++
++ video_set_drvdata(csi_dev->vdev, csi_dev);
++ mutex_lock(&csi_dev->lock);
++
++ ret = video_register_device(csi_dev->vdev, VFL_TYPE_GRABBER, -1);
++ if (ret < 0) {
++ video_device_release(csi_dev->vdev);
++ mutex_unlock(&csi_dev->lock);
++ goto err_vdev;
++ }
++
++ /* install interrupt handler */
++ if (devm_request_irq(dev, csi_dev->irq, mx6s_csi_irq_handler,
++ 0, "csi", (void *)csi_dev)) {
++ mutex_unlock(&csi_dev->lock);
++ dev_err(dev, "Request CSI IRQ failed.\n");
++ ret = -ENODEV;
++ goto err_irq;
++ }
++
++ mutex_unlock(&csi_dev->lock);
++
++ ret = mx6sx_register_subdevs(csi_dev);
++ if (ret < 0)
++ goto err_irq;
++
++ pm_runtime_enable(csi_dev->dev);
++ return 0;
++
++err_irq:
++ video_unregister_device(csi_dev->vdev);
++err_vdev:
++ v4l2_device_unregister(&csi_dev->v4l2_dev);
++ return ret;
++}
++
++static int mx6s_csi_remove(struct platform_device *pdev)
++{
++ struct v4l2_device *v4l2_dev = dev_get_drvdata(&pdev->dev);
++ struct mx6s_csi_dev *csi_dev =
++ container_of(v4l2_dev, struct mx6s_csi_dev, v4l2_dev);
++
++ v4l2_async_notifier_unregister(&csi_dev->subdev_notifier);
++
++ video_unregister_device(csi_dev->vdev);
++ v4l2_device_unregister(&csi_dev->v4l2_dev);
++
++ pm_runtime_disable(csi_dev->dev);
++ return 0;
++}
++
++#ifdef CONFIG_PM_RUNTIME
++static int mx6s_csi_runtime_suspend(struct device *dev)
++{
++ dev_dbg(dev, "csi v4l2 busfreq high release.\n");
++ return 0;
++}
++
++static int mx6s_csi_runtime_resume(struct device *dev)
++{
++ dev_dbg(dev, "csi v4l2 busfreq high request.\n");
++ return 0;
++}
++#else
++#define mx6s_csi_runtime_suspend NULL
++#define mx6s_csi_runtime_resume NULL
++#endif
++
++static const struct dev_pm_ops mx6s_csi_pm_ops = {
++ SET_RUNTIME_PM_OPS(mx6s_csi_runtime_suspend, mx6s_csi_runtime_resume, NULL)
++};
++
++static const struct of_device_id mx6s_csi_dt_ids[] = {
++ { .compatible = "fsl,imx6s-csi", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, mx6s_csi_dt_ids);
++
++static struct platform_driver mx6s_csi_driver = {
++ .driver = {
++ .name = MX6S_CAM_DRV_NAME,
++ .of_match_table = of_match_ptr(mx6s_csi_dt_ids),
++ .pm = &mx6s_csi_pm_ops,
++ },
++ .probe = mx6s_csi_probe,
++ .remove = mx6s_csi_remove,
++};
++
++module_platform_driver(mx6s_csi_driver);
++
++MODULE_DESCRIPTION("i.MX6Sx SoC Camera Host driver");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
++MODULE_VERSION(MX6S_CAM_VERSION);
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/subdev/mxc_vadc.c linux-3.14.72/drivers/media/platform/mxc/subdev/mxc_vadc.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/subdev/mxc_vadc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/subdev/mxc_vadc.c 2016-06-19 22:11:55.189147618 +0200
+@@ -0,0 +1,813 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/of_address.h>
++#include <linux/of_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <media/v4l2-ioctl.h>
++#include <linux/videodev2.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++#include "mxc_vadc.h"
++
++/* Resource names for the VADC driver. */
++#define VAFE_REGS_ADDR_RES_NAME "vadc-vafe"
++#define VDEC_REGS_ADDR_RES_NAME "vadc-vdec"
++
++#define reg32_write(addr, val) __raw_writel(val, addr)
++#define reg32_read(addr) __raw_readl(addr)
++#define reg32setbit(addr, bitpos) \
++ reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos))))
++
++#define reg32clrbit(addr, bitpos) \
++ reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos)))))
++
++#define GPC_CNTR 0x00
++#define IMX6SX_GPC_CNTR_VADC_ANALOG_OFF_MASK BIT(17)
++#define IMX6SX_GPC_CNTR_VADC_POWER_DOWN_MASK BIT(18)
++
++void __iomem *vafe_regbase;
++void __iomem *vdec_regbase;
++
++
++/* List of input video formats supported. The video formats is corresponding
++ * with v4l2 id in video_fmt
++ */
++enum video_fmt_idx {
++ VADC_NTSC = 0, /* Locked on (M) NTSC video signal. */
++ VADC_PAL, /* (B, G, H, I, N)PAL video signal. */
++};
++
++/* Number of video standards supported (including 'not locked' signal). */
++#define VADC_STD_MAX (VADC_PAL + 1)
++
++/* Video format structure. */
++struct video_fmt{
++ v4l2_std_id v4l2_std; /* Video for linux ID. */
++ char name[16]; /* Name (e.g., "NTSC", "PAL", etc.) */
++ u16 raw_width; /* Raw width. */
++ u16 raw_height; /* Raw height. */
++ u16 active_width; /* Active width. */
++ u16 active_height; /* Active height. */
++ u16 framerates;
++};
++
++/*
++ * Maintains the information on the current state of the sensor.
++ */
++struct vadc_state {
++ struct v4l2_device v4l2_dev;
++ struct v4l2_subdev sd;
++ struct video_fmt *fmt;
++
++ struct clk *vadc_clk;
++ struct clk *csi_clk;
++ struct regmap *gpr;
++ void __iomem *gpc_reg;
++
++ u32 vadc_in;
++ u32 csi_id;
++};
++
++static int vadc_querystd(struct v4l2_subdev *sd, v4l2_std_id *std);
++
++/* Description of video formats supported.
++ *
++ * PAL: raw=720x625, active=720x576.
++ * NTSC: raw=720x525, active=720x480.
++ */
++static struct video_fmt video_fmts[] = {
++ /* NTSC */
++ {
++ .v4l2_std = V4L2_STD_NTSC,
++ .name = "NTSC",
++ .raw_width = 720,
++ .raw_height = 525,
++ .active_width = 720,
++ .active_height = 480,
++ .framerates = 30,
++ },
++ /* (B, G, H, I, N) PAL */
++ {
++ .v4l2_std = V4L2_STD_PAL,
++ .name = "PAL",
++ .raw_width = 720,
++ .raw_height = 625,
++ .active_width = 720,
++ .active_height = 576,
++ .framerates = 25,
++ },
++};
++
++static void afe_voltage_clampingmode(void)
++{
++ reg32_write(AFE_CLAMP, 0x07);
++ reg32_write(AFE_CLMPAMP, 0x60);
++ reg32_write(AFE_CLMPDAT, 0xF0);
++}
++
++static void afe_alwayson_clampingmode(void)
++{
++ reg32_write(AFE_CLAMP, 0x15);
++ reg32_write(AFE_CLMPDAT, 0x08);
++ reg32_write(AFE_CLMPAMP, 0x00);
++}
++
++static void afe_init(void)
++{
++ pr_debug("%s\n", __func__);
++
++ reg32_write(AFE_PDBUF, 0x1f);
++ reg32_write(AFE_PDADC, 0x0f);
++ reg32_write(AFE_PDSARH, 0x01);
++ reg32_write(AFE_PDSARL, 0xff);
++ reg32_write(AFE_PDADCRFH, 0x01);
++ reg32_write(AFE_PDADCRFL, 0xff);
++ reg32_write(AFE_ICTRL, 0x3a);
++ reg32_write(AFE_ICTLSTG, 0x1e);
++
++ reg32_write(AFE_RCTRLSTG, 0x1e);
++ reg32_write(AFE_INPBUF, 0x035);
++ reg32_write(AFE_INPFLT, 0x02);
++ reg32_write(AFE_ADCDGN, 0x40);
++ reg32_write(AFE_TSTSEL, 0x10);
++
++ reg32_write(AFE_ACCTST, 0x07);
++
++ reg32_write(AFE_BGREG, 0x08);
++
++ reg32_write(AFE_ADCGN, 0x09);
++
++ /* set current controlled clamping
++ * always on, low current */
++ reg32_write(AFE_CLAMP, 0x11);
++ reg32_write(AFE_CLMPAMP, 0x08);
++}
++
++static void vdec_mode_timing_init(int std)
++{
++ if (std == V4L2_STD_NTSC) {
++ /* NTSC 720x480 */
++ reg32_write(VDEC_HACTS, 0x66);
++ reg32_write(VDEC_HACTE, 0x24);
++
++ reg32_write(VDEC_VACTS, 0x29);
++ reg32_write(VDEC_VACTE, 0x04);
++
++ /* set V Position */
++ reg32_write(VDEC_VRTPOS, 0x2);
++ } else if (std == V4L2_STD_PAL) {
++ /* PAL 720x576 */
++ reg32_write(VDEC_HACTS, 0x66);
++ reg32_write(VDEC_HACTE, 0x24);
++
++ reg32_write(VDEC_VACTS, 0x29);
++ reg32_write(VDEC_VACTE, 0x04);
++
++ /* set V Position */
++ reg32_write(VDEC_VRTPOS, 0x6);
++ } else
++ pr_debug("Error not support video mode\n");
++
++ /* set H Position */
++ reg32_write(VDEC_HZPOS, 0x60);
++
++ /* set H ignore start */
++ reg32_write(VDEC_HSIGS, 0xf8);
++
++ /* set H ignore end */
++ reg32_write(VDEC_HSIGE, 0x18);
++}
++
++/*
++* vdec_init()
++* Initialises the VDEC registers
++* Returns: nothing
++*/
++static void vdec_init(struct vadc_state *vadc)
++{
++ v4l2_std_id std;
++
++ pr_debug("%s\n", __func__);
++
++ /* Get work mode PAL or NTSC */
++ vadc_querystd(&vadc->sd, &std);
++
++ vdec_mode_timing_init(std);
++
++ /* vcr detect threshold high, automatic detections */
++ reg32_write(VDEC_VSCON2, 0);
++
++ reg32_write(VDEC_BASE + 0x110, 0x01);
++
++ /* set the noramp mode on the Hloop PLL. */
++ reg32_write(VDEC_BASE+(0x14*4), 0x10);
++
++ /* set the YC relative delay.*/
++ reg32_write(VDEC_YCDEL, 0x90);
++
++ /* setup the Hpll */
++ reg32_write(VDEC_BASE+(0x13*4), 0x13);
++
++ /* setup the 2d comb */
++ /* set the gain of the Hdetail output to 3
++ * set the notch alpha gain to 1 */
++ reg32_write(VDEC_CFC2, 0x34);
++
++ /* setup various 2d comb bits.*/
++ reg32_write(VDEC_BASE+(0x02*4), 0x01);
++ reg32_write(VDEC_BASE+(0x03*4), 0x18);
++ reg32_write(VDEC_BASE+(0x04*4), 0x34);
++
++ /* set the start of the burst gate */
++ reg32_write(VDEC_BRSTGT, 0x30);
++
++ /* set 1f motion gain */
++ reg32_write(VDEC_BASE+(0x0f*4), 0x20);
++
++ /* set the 1F chroma motion detector thresh
++ * for colour reverse detection */
++ reg32_write(VDEC_THSH1, 0x02);
++ reg32_write(VDEC_BASE+(0x4a*4), 0x20);
++ reg32_write(VDEC_BASE+(0x4b*4), 0x08);
++
++ reg32_write(VDEC_BASE+(0x4c*4), 0x08);
++
++ /* set the threshold for the narrow/wide adaptive chroma BW */
++ reg32_write(VDEC_BASE+(0x20*4), 0x20);
++
++ /* turn up the colour with the new colour gain reg */
++ /* hue: */
++ reg32_write(VDEC_HUE, 0x00);
++
++ /* cbgain: 22 B4 */
++ reg32_write(VDEC_CBGN, 0xb4);
++ /* cr gain 80 */
++ reg32_write(VDEC_CRGN, 0x80);
++ /* luma gain (contrast) */
++ reg32_write(VDEC_CNTR, 0x80);
++
++ /* setup the signed black level register, brightness */
++ reg32_write(VDEC_BRT, 0x00);
++
++ /* filter the standard detection
++ * enable the comb for the ntsc443 */
++ reg32_write(VDEC_STDDBG, 0x20);
++
++ /* setup chroma kill thresh for no chroma */
++ reg32_write(VDEC_CHBTH, 0x0);
++
++ /* set chroma loop to wider BW
++ * no set it to normal BW. i fixed the bw problem.*/
++ reg32_write(VDEC_YCDEL, 0x00);
++
++ /* set the compensation in the chroma loop for the Hloop
++ * set the ratio for the nonarithmetic 3d comb modes.*/
++ reg32_write(VDEC_BASE + (0x1d*4), 0x90);
++
++ /* set the threshold for the nonarithmetic mode for the 2d comb
++ * the higher the value the more Fc Fh offset
++ * we will tolerate before turning off the comb. */
++ reg32_write(VDEC_BASE + (0x33*4), 0xa0);
++
++ /* setup the bluescreen output colour */
++ reg32_write(VDEC_BASE + (0x3d*4), 35);
++ reg32_write(VDEC_BLSCRCR, 114);
++ reg32_write(VDEC_BLSCRCB, 212);
++
++ /* disable the active blanking */
++ reg32_write(VDEC_BASE + (0x15*4), 0x02);
++
++ /* setup the luma agc for automatic gain. */
++ reg32_write(VDEC_LMAGC2, 0x5e);
++ reg32_write(VDEC_LMAGC1, 0x81);
++
++ /* setup chroma agc */
++ reg32_write(VDEC_CHAGC2, 0xa0);
++ reg32_write(VDEC_CHAGC1, 0x01);
++
++ /* setup the MV thresh lower nibble
++ * setup the sync top cap, upper nibble */
++ reg32_write(VDEC_BASE + (0x3a*4), 0x80);
++ reg32_write(VDEC_SHPIMP, 0x00);
++
++ /* setup the vsync block */
++ reg32_write(VDEC_VSCON1, 0x87);
++
++ /* set the nosignal threshold
++ * set the vsync threshold */
++ reg32_write(VDEC_VSSGTH, 0x35);
++
++ /* set length for min hphase filter
++ * (or saturate limit if saturate is chosen) */
++ reg32_write(VDEC_BASE + (0x45*4), 0x40);
++
++ /* enable the internal resampler,
++ * select min filter not saturate for
++ * hphase noise filter for vcr detect.
++ * enable vcr pause mode different field lengths */
++ reg32_write(VDEC_BASE + (0x46*4), 0x90);
++
++ /* disable VCR detection, lock to the Hsync rather than the Vsync */
++ reg32_write(VDEC_VSCON2, 0x04);
++
++ /* set tiplevel goal for dc clamp. */
++ reg32_write(VDEC_BASE + (0x3c*4), 0xB0);
++
++ /* override SECAM detection and force SECAM off */
++ reg32_write(VDEC_BASE + (0x2f*4), 0x20);
++
++ /* Set r3d_hardblend in 3D control2 reg */
++ reg32_write(VDEC_BASE + (0x0c*4), 0x04);
++}
++
++/* set Input selector & input pull-downs */
++static void vadc_s_routing(int vadc_in)
++{
++ switch (vadc_in) {
++ case 0:
++ reg32_write(AFE_INPFLT, 0x02);
++ reg32_write(AFE_OFFDRV, 0x00);
++ reg32_write(AFE_INPCONFIG, 0x1e);
++ break;
++ case 1:
++ reg32_write(AFE_INPFLT, 0x02);
++ reg32_write(AFE_OFFDRV, 0x00);
++ reg32_write(AFE_INPCONFIG, 0x2d);
++ break;
++ case 2:
++ reg32_write(AFE_INPFLT, 0x02);
++ reg32_write(AFE_OFFDRV, 0x00);
++ reg32_write(AFE_INPCONFIG, 0x4b);
++ break;
++ case 3:
++ reg32_write(AFE_INPFLT, 0x02);
++ reg32_write(AFE_OFFDRV, 0x00);
++ reg32_write(AFE_INPCONFIG, 0x87);
++ break;
++ default:
++ pr_debug("error video input %d\n", vadc_in);
++ }
++}
++
++static void vadc_power_up(struct vadc_state *state)
++{
++ /* Power on vadc analog */
++ reg32clrbit(state->gpc_reg + GPC_CNTR, 17);
++
++ /* Power down vadc ext power */
++ reg32clrbit(state->gpc_reg + GPC_CNTR, 18);
++
++ /* software reset afe */
++ regmap_update_bits(state->gpr, IOMUXC_GPR1,
++ IMX6SX_GPR1_VADC_SW_RST_MASK,
++ IMX6SX_GPR1_VADC_SW_RST_RESET);
++
++ msleep(10);
++
++ /* clock config for vadc */
++ reg32_write(VDEC_BASE + 0x320, 0xe3);
++ reg32_write(VDEC_BASE + 0x324, 0x38);
++ reg32_write(VDEC_BASE + 0x328, 0x8e);
++ reg32_write(VDEC_BASE + 0x32c, 0x23);
++
++ /* Release reset bit */
++ regmap_update_bits(state->gpr, IOMUXC_GPR1,
++ IMX6SX_GPR1_VADC_SW_RST_MASK,
++ IMX6SX_GPR1_VADC_SW_RST_RELEASE);
++
++ /* Power on vadc ext power */
++ reg32setbit(state->gpc_reg + GPC_CNTR, 18);
++}
++
++static void vadc_power_down(struct vadc_state *state)
++{
++ /* Power down vadc analog */
++ reg32setbit(state->gpc_reg + GPC_CNTR, 17);
++
++ /* Power down vadc ext power */
++ reg32clrbit(state->gpc_reg + GPC_CNTR, 18);
++
++}
++static void vadc_init(struct vadc_state *vadc)
++{
++ pr_debug("%s\n", __func__);
++
++ vadc_power_up(vadc);
++
++ afe_init();
++
++ /* select Video Input 0-3 */
++ vadc_s_routing(vadc->vadc_in);
++
++ afe_voltage_clampingmode();
++
++ vdec_init(vadc);
++
++ /*
++ * current control loop will move sinewave input off below
++ * the bottom of the signal range visible
++ * when the testbus is viewed as magnitude,
++ * so have to break before this point while capturing ENOB data:
++ */
++ afe_alwayson_clampingmode();
++}
++
++static inline struct vadc_state *to_state(struct v4l2_subdev *sd)
++{
++ return container_of(sd, struct vadc_state, sd);
++}
++
++static int vadc_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
++{
++ struct vadc_state *state = to_state(sd);
++
++ *std = state->fmt->v4l2_std;
++ return 0;
++}
++
++/*!
++ * Return attributes of current video standard.
++ * Since this device autodetects the current standard, this function also
++ * sets the values that need to be changed if the standard changes.
++ * There is no set std equivalent function.
++ *
++ * @return None.
++ */
++static int vadc_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
++{
++ struct vadc_state *state = to_state(sd);
++ int mod;
++ int idx;
++ int i;
++
++ /* Read auto mode detected result */
++ printk(KERN_INFO"wait vadc auto detect video mode....\n");
++ for (i = 0; i < 10; i++) {
++ msleep(200);
++ mod = reg32_read(VDEC_VIDMOD);
++ /* Check video signal states */
++ if ((mod & VDEC_VIDMOD_SIGNAL_MASK)
++ == VDEC_VIDMOD_SIGNAL_DETECT)
++ break;
++ }
++ if (i == 10)
++ printk(KERN_INFO"Timeout detect video signal mod=0x%x\n", mod);
++
++ if ((mod & VDEC_VIDMOD_PAL_MASK) || (mod & VDEC_VIDMOD_M625_MASK))
++ idx = VADC_PAL;
++ else
++ idx = VADC_NTSC;
++
++ *std = video_fmts[idx].v4l2_std;
++ state->fmt = &video_fmts[idx];
++
++ printk(KERN_INFO"video mode %s\n", video_fmts[idx].name);
++ return 0;
++}
++
++static int vadc_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index,
++ enum v4l2_mbus_pixelcode *code)
++{
++ /* support only one format */
++ if (index >= 1)
++ return -EINVAL;
++
++ *code = V4L2_MBUS_FMT_AYUV8_1X32;
++ return 0;
++}
++
++static int vadc_mbus_fmt(struct v4l2_subdev *sd,
++ struct v4l2_mbus_framefmt *fmt)
++{
++ struct vadc_state *state = to_state(sd);
++
++ fmt->code = V4L2_MBUS_FMT_AYUV8_1X32;
++ fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
++ fmt->field = V4L2_FIELD_INTERLACED;
++ fmt->width = 720;
++ fmt->height = state->fmt->v4l2_std & V4L2_STD_NTSC ? 480 : 576;
++
++ return 0;
++}
++
++static int vadc_enum_framesizes(struct v4l2_subdev *sd,
++ struct v4l2_frmsizeenum *fsize)
++{
++ struct vadc_state *state = to_state(sd);
++ if (fsize->index >= 1)
++ return -EINVAL;
++
++ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++ fsize->discrete.width = state->fmt->active_width;
++ fsize->discrete.height = state->fmt->active_height;
++
++ return 0;
++}
++static int vadc_enum_frameintervals(struct v4l2_subdev *sd,
++ struct v4l2_frmivalenum *fival)
++{
++ struct vadc_state *state = to_state(sd);
++
++ if (fival->index < 0 || fival->index >= 1)
++ return -EINVAL;
++
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++
++ fival->discrete.denominator = state->fmt->framerates;
++
++ return 0;
++}
++
++static int vadc_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
++{
++ struct vadc_state *state = to_state(sd);
++
++ if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
++ return -EINVAL;
++
++ if (parms->parm.capture.timeperframe.denominator
++ != state->fmt->framerates)
++ parms->parm.capture.timeperframe.denominator
++ = state->fmt->framerates;
++
++ return 0;
++}
++
++static const struct v4l2_subdev_video_ops vadc_video_ops = {
++ .querystd = vadc_querystd,
++ .enum_mbus_fmt = vadc_enum_mbus_fmt,
++ .try_mbus_fmt = vadc_mbus_fmt,
++ .g_mbus_fmt = vadc_mbus_fmt,
++ .enum_framesizes = vadc_enum_framesizes,
++ .enum_frameintervals = vadc_enum_frameintervals,
++ .s_parm = vadc_s_parm,
++};
++
++static const struct v4l2_subdev_core_ops vadc_core_ops = {
++ .g_std = vadc_g_std,
++};
++
++static const struct v4l2_subdev_ops vadc_ops = {
++ .core = &vadc_core_ops,
++ .video = &vadc_video_ops,
++};
++
++static const struct of_device_id fsl_vadc_dt_ids[] = {
++ { .compatible = "fsl,imx6sx-vadc", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_vadc_dt_ids);
++
++static int vadc_of_init(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct device_node *gpc_np;
++ struct vadc_state *state = platform_get_drvdata(pdev);
++ int csi_id;
++ int ret;
++
++ /* Get csi_id to setting vadc to csi mux in gpr */
++ ret = of_property_read_u32(np, "csi_id", &csi_id);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property csi_id\n");
++ return ret;
++ }
++
++ state->csi_id = csi_id;
++
++ /* remap GPR register */
++ state->gpr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++ "gpr");
++ if (IS_ERR(state->gpr)) {
++ dev_dbg(&pdev->dev, "can not get gpr\n");
++ return -ENOMEM;
++ }
++
++ /* Configuration vadc-to-csi 0 or 1 */
++ if (csi_id) {
++ regmap_update_bits(state->gpr, IOMUXC_GPR5,
++ IMX6SX_GPR5_CSI2_MUX_CTRL_MASK,
++ IMX6SX_GPR5_CSI2_MUX_CTRL_CVD);
++ } else {
++ regmap_update_bits(state->gpr, IOMUXC_GPR5,
++ IMX6SX_GPR5_CSI1_MUX_CTRL_MASK,
++ IMX6SX_GPR5_CSI1_MUX_CTRL_CVD);
++ }
++
++ /* Get default vadc_in number */
++ ret = of_property_read_u32(np, "vadc_in", &state->vadc_in);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property vadc_in\n");
++ return ret;
++ }
++
++ /* map GPC register */
++ gpc_np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc");
++ state->gpc_reg = of_iomap(gpc_np, 0);
++ if (!state->gpc_reg) {
++ dev_err(&pdev->dev, "ioremap failed with gpc base\n");
++ goto error;
++ }
++
++ return ret;
++
++error:
++ iounmap(state->gpc_reg);
++ return ret;
++}
++
++static void vadc_v4l2_subdev_init(struct v4l2_subdev *sd,
++ struct platform_device *pdev,
++ const struct v4l2_subdev_ops *ops)
++{
++ struct vadc_state *state = platform_get_drvdata(pdev);
++ int ret = 0;
++
++ v4l2_subdev_init(sd, ops);
++ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
++ sd->owner = pdev->dev.driver->owner;
++ sd->dev = &pdev->dev;
++
++ /* initialize name */
++ snprintf(sd->name, sizeof(sd->name), "%s",
++ pdev->dev.driver->name);
++
++ v4l2_set_subdevdata(sd, state);
++
++ ret = v4l2_async_register_subdev(sd);
++ if (ret < 0)
++ dev_err(&pdev->dev, "%s--Async register faialed, ret=%d\n", __func__, ret);
++}
++
++static int vadc_probe(struct platform_device *pdev)
++{
++ struct vadc_state *state;
++ struct v4l2_subdev *sd;
++ struct resource *res;
++ int ret = 0;
++
++ state = devm_kzalloc(&pdev->dev, sizeof(struct vadc_state), GFP_KERNEL);
++ if (!state) {
++ dev_err(&pdev->dev, "Cannot allocate device data\n");
++ return -ENOMEM;
++ }
++
++ /* Set initial values for the sensor struct. */
++ state->fmt = &video_fmts[VADC_NTSC];
++
++ sd = &state->sd;
++
++ /* map vafe address */
++ res = platform_get_resource_byname(pdev,
++ IORESOURCE_MEM, VAFE_REGS_ADDR_RES_NAME);
++ if (!res) {
++ dev_err(&pdev->dev, "No vafe base address found.\n");
++ return -ENOMEM;
++ }
++ vafe_regbase = devm_ioremap_resource(&pdev->dev, res);
++ if (!vafe_regbase) {
++ dev_err(&pdev->dev, "ioremap failed with vafe base\n");
++ return -ENOMEM;
++ }
++
++ /* map vdec address */
++ res = platform_get_resource_byname(pdev,
++ IORESOURCE_MEM, VDEC_REGS_ADDR_RES_NAME);
++ if (!res) {
++ dev_err(&pdev->dev, "No vdec base address found.\n");
++ return -ENODEV;
++ }
++ vdec_regbase = devm_ioremap_resource(&pdev->dev, res);
++ if (!vdec_regbase) {
++ dev_err(&pdev->dev, "ioremap failed with vdec base\n");
++ return -ENOMEM;
++ }
++
++ /* Get clock */
++ state->vadc_clk = devm_clk_get(&pdev->dev, "vadc");
++ if (IS_ERR(state->vadc_clk)) {
++ ret = PTR_ERR(state->vadc_clk);
++ return ret;
++ }
++
++ state->csi_clk = devm_clk_get(&pdev->dev, "csi");
++ if (IS_ERR(state->csi_clk)) {
++ ret = PTR_ERR(state->csi_clk);
++ return ret;
++ }
++
++ /* clock */
++ clk_prepare_enable(state->csi_clk);
++ clk_prepare_enable(state->vadc_clk);
++
++ platform_set_drvdata(pdev, state);
++
++ vadc_v4l2_subdev_init(sd, pdev, &vadc_ops);
++
++ pm_runtime_enable(&pdev->dev);
++
++ pm_runtime_get_sync(&pdev->dev);
++ /* Init VADC */
++ ret = vadc_of_init(pdev);
++ if (ret < 0)
++ goto err;
++ vadc_init(state);
++
++ pr_info("vadc driver loaded\n");
++
++ return 0;
++err:
++ pm_runtime_put_sync(&pdev->dev);
++ pm_runtime_disable(&pdev->dev);
++ v4l2_async_unregister_subdev(&state->sd);
++ clk_disable_unprepare(state->csi_clk);
++ clk_disable_unprepare(state->vadc_clk);
++ return ret;
++}
++
++static int vadc_remove(struct platform_device *pdev)
++{
++ struct vadc_state *state = platform_get_drvdata(pdev);
++
++ pm_runtime_put_sync(&pdev->dev);
++ pm_runtime_disable(&pdev->dev);
++ v4l2_async_unregister_subdev(&state->sd);
++ clk_disable_unprepare(state->csi_clk);
++ clk_disable_unprepare(state->vadc_clk);
++
++ vadc_power_down(state);
++ return true;
++}
++
++static int vadc_suspend(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct vadc_state *state = platform_get_drvdata(pdev);
++
++ clk_disable(state->csi_clk);
++ clk_disable(state->vadc_clk);
++
++ vadc_power_down(state);
++
++ return 0;
++}
++
++static int vadc_resume(struct device *dev)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct vadc_state *state = platform_get_drvdata(pdev);
++
++ clk_enable(state->csi_clk);
++ clk_enable(state->vadc_clk);
++
++ vadc_init(state);
++ return 0;
++}
++
++static const struct dev_pm_ops vadc_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(vadc_suspend, vadc_resume)
++};
++
++static struct platform_driver vadc_driver = {
++ .driver = {
++ .name = "fsl_vadc",
++ .of_match_table = of_match_ptr(fsl_vadc_dt_ids),
++ .pm = &vadc_pm_ops,
++ },
++ .probe = vadc_probe,
++ .remove = vadc_remove,
++};
++
++module_platform_driver(vadc_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("fsl VADC/VDEC driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/subdev/mxc_vadc.h linux-3.14.72/drivers/media/platform/mxc/subdev/mxc_vadc.h
+--- linux-3.14.72.orig/drivers/media/platform/mxc/subdev/mxc_vadc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/subdev/mxc_vadc.h 2016-06-19 22:11:55.189147618 +0200
+@@ -0,0 +1,239 @@
++/*
++ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#ifndef MXC_VDEC_H
++#define MXC_VDEC_H
++
++/*** define base address ***/
++#define VDEC_BASE vdec_regbase
++#define AFE_BASE vafe_regbase
++
++/* AFE - Register offsets */
++#define AFE_BLOCK_ID_OFFSET 0x00000000
++#define AFE_PDBUF_OFFSET 0x00000004
++#define AFE_SWRST_OFFSET 0x00000008
++#define AFE_TSTSEL_OFFSET 0x0000000c
++#define AFE_TSTMSC_OFFSET 0x00000010
++#define AFE_ENPADIO_OFFSET 0x00000014
++#define AFE_BGREG_OFFSET 0x00000018
++#define AFE_ACCESSAR_ID_OFFSET 0x00000400
++#define AFE_PDADC_OFFSET 0x00000404
++#define AFE_PDSARH_OFFSET 0x00000408
++#define AFE_PDSARL_OFFSET 0x0000040C
++#define AFE_PDADCRFH_OFFSET 0x00000410
++#define AFE_PDADCRFL_OFFSET 0x00000414
++#define AFE_ACCTST_OFFSET 0x00000418
++#define AFE_ADCGN_OFFSET 0x0000041C
++#define AFE_ICTRL_OFFSET 0x00000420
++#define AFE_ICTLSTG_OFFSET 0x00000424
++#define AFE_RCTRLSTG_OFFSET 0x00000428
++#define AFE_TCTRLSTG_OFFSET 0x0000042c
++#define AFE_REFMOD_OFFSET 0x00000430
++#define AFE_REFTRIML_OFFSET 0x00000434
++#define AFE_REFTRIMH_OFFSET 0x00000438
++#define AFE_ADCR_OFFSET 0x0000043c
++#define AFE_DUMMY0_OFFSET 0x00000440
++#define AFE_DUMMY1_OFFSET 0x00000444
++#define AFE_DUMMY2_OFFSET 0x00000448
++#define AFE_DACAMP_OFFSET 0x0000044c
++#define AFE_CLMPTST_OFFSET 0x00000450
++#define AFE_CLMPDAT_OFFSET 0x00000454
++#define AFE_CLMPAMP_OFFSET 0x00000458
++#define AFE_CLAMP_OFFSET 0x0000045c
++#define AFE_INPBUF_OFFSET 0x00000460
++#define AFE_INPFLT_OFFSET 0x00000464
++#define AFE_ADCDGN_OFFSET 0x00000468
++#define AFE_OFFDRV_OFFSET 0x0000046c
++#define AFE_INPCONFIG_OFFSET 0x00000470
++#define AFE_PROGDELAY_OFFSET 0x00000474
++#define AFE_ADCOMT_OFFSET 0x00000478
++#define AFE_ALGDELAY_OFFSET 0x0000047c
++#define AFE_ACC_ID_OFFSET 0x00000800
++#define AFE_ACCSTA_OFFSET 0x00000804
++#define AFE_ACCNOSLI_OFFSET 0x00000808
++#define AFE_ACCCALCON_OFFSET 0x0000080c
++#define AFE_BWEWRICTRL_OFFSET 0x00000810
++#define AFE_SELSLI_OFFSET 0x00000814
++#define AFE_SELBYT_OFFSET 0x00000818
++#define AFE_REDVAL_OFFSET 0x00000820
++#define AFE_WRIBYT_OFFSET 0x00000824
++
++/* AFE Register per module */
++#define AFE_BLOCK_ID (AFE_BASE + AFE_BLOCK_ID_OFFSET)
++#define AFE_PDBUF (AFE_BASE + AFE_PDBUF_OFFSET)
++#define AFE_SWRST (AFE_BASE + AFE_SWRST_OFFSET)
++#define AFE_TSTSEL (AFE_BASE + AFE_TSTSEL_OFFSET)
++#define AFE_TSTMSC (AFE_BASE + AFE_TSTMSC_OFFSET)
++#define AFE_ENPADIO (AFE_BASE + AFE_ENPADIO_OFFSET)
++#define AFE_BGREG (AFE_BASE + AFE_BGREG_OFFSET)
++#define AFE_ACCESSAR_ID (AFE_BASE + AFE_ACCESSAR_ID_OFFSET)
++#define AFE_PDADC (AFE_BASE + AFE_PDADC_OFFSET)
++#define AFE_PDSARH (AFE_BASE + AFE_PDSARH_OFFSET)
++#define AFE_PDSARL (AFE_BASE + AFE_PDSARL_OFFSET)
++#define AFE_PDADCRFH (AFE_BASE + AFE_PDADCRFH_OFFSET)
++#define AFE_PDADCRFL (AFE_BASE + AFE_PDADCRFL_OFFSET)
++#define AFE_ACCTST (AFE_BASE + AFE_ACCTST_OFFSET)
++#define AFE_ADCGN (AFE_BASE + AFE_ADCGN_OFFSET)
++#define AFE_ICTRL (AFE_BASE + AFE_ICTRL_OFFSET)
++#define AFE_ICTLSTG (AFE_BASE + AFE_ICTLSTG_OFFSET)
++#define AFE_RCTRLSTG (AFE_BASE + AFE_RCTRLSTG_OFFSET)
++#define AFE_TCTRLSTG (AFE_BASE + AFE_TCTRLSTG_OFFSET)
++#define AFE_REFMOD (AFE_BASE + AFE_REFMOD_OFFSET)
++#define AFE_REFTRIML (AFE_BASE + AFE_REFTRIML_OFFSET)
++#define AFE_REFTRIMH (AFE_BASE + AFE_REFTRIMH_OFFSET)
++#define AFE_ADCR (AFE_BASE + AFE_ADCR_OFFSET)
++#define AFE_DUMMY0 (AFE_BASE + AFE_DUMMY0_OFFSET)
++#define AFE_DUMMY1 (AFE_BASE + AFE_DUMMY1_OFFSET)
++#define AFE_DUMMY2 (AFE_BASE + AFE_DUMMY2_OFFSET)
++#define AFE_DACAMP (AFE_BASE + AFE_DACAMP_OFFSET)
++#define AFE_CLMPTST (AFE_BASE + AFE_CLMPTST_OFFSET)
++#define AFE_CLMPDAT (AFE_BASE + AFE_CLMPDAT_OFFSET)
++#define AFE_CLMPAMP (AFE_BASE + AFE_CLMPAMP_OFFSET)
++#define AFE_CLAMP (AFE_BASE + AFE_CLAMP_OFFSET)
++#define AFE_INPBUF (AFE_BASE + AFE_INPBUF_OFFSET)
++#define AFE_INPFLT (AFE_BASE + AFE_INPFLT_OFFSET)
++#define AFE_ADCDGN (AFE_BASE + AFE_ADCDGN_OFFSET)
++#define AFE_OFFDRV (AFE_BASE + AFE_OFFDRV_OFFSET)
++#define AFE_INPCONFIG (AFE_BASE + AFE_INPCONFIG_OFFSET)
++#define AFE_PROGDELAY (AFE_BASE + AFE_PROGDELAY_OFFSET)
++#define AFE_ADCOMT (AFE_BASE + AFE_ADCOMT_OFFSET)
++#define AFE_ALGDELAY (AFE_BASE + AFE_ALGDELAY_OFFSET)
++#define AFE_ACC_ID (AFE_BASE + AFE_ACC_ID_OFFSET)
++#define AFE_ACCSTA (AFE_BASE + AFE_ACCSTA_OFFSET)
++#define AFE_ACCNOSLI (AFE_BASE + AFE_ACCNOSLI_OFFSET)
++#define AFE_ACCCALCON (AFE_BASE + AFE_ACCCALCON_OFFSET)
++#define AFE_BWEWRICTRL (AFE_BASE + AFE_BWEWRICTRL_OFFSET)
++#define AFE_SELSLI (AFE_BASE + AFE_SELSLI_OFFSET)
++#define AFE_SELBYT (AFE_BASE + AFE_SELBYT_OFFSET)
++#define AFE_REDVAL (AFE_BASE + AFE_REDVAL_OFFSET)
++#define AFE_WRIBYT (AFE_BASE + AFE_WRIBYT_OFFSET)
++
++/* VDEC - Register offsets */
++#define VDEC_CFC1_OFFSET 0x00000000
++#define VDEC_CFC2_OFFSET 0x00000004
++#define VDEC_BRSTGT_OFFSET 0x00000024
++#define VDEC_HZPOS_OFFSET 0x00000040
++#define VDEC_VRTPOS_OFFSET 0x00000044
++#define VDEC_HVSHIFT_OFFSET 0x00000054
++#define VDEC_HSIGS_OFFSET 0x00000058
++#define VDEC_HSIGE_OFFSET 0x0000005C
++#define VDEC_VSCON1_OFFSET 0x00000060
++#define VDEC_VSCON2_OFFSET 0x00000064
++#define VDEC_YCDEL_OFFSET 0x0000006C
++#define VDEC_AFTCLP_OFFSET 0x00000070
++#define VDEC_DCOFF_OFFSET 0x00000078
++#define VDEC_CSID_OFFSET 0x00000084
++#define VDEC_CBGN_OFFSET 0x00000088
++#define VDEC_CRGN_OFFSET 0x0000008C
++#define VDEC_CNTR_OFFSET 0x00000090
++#define VDEC_BRT_OFFSET 0x00000094
++#define VDEC_HUE_OFFSET 0x00000098
++#define VDEC_CHBTH_OFFSET 0x0000009C
++#define VDEC_SHPIMP_OFFSET 0x000000A4
++#define VDEC_CHPLLIM_OFFSET 0x000000A8
++#define VDEC_VIDMOD_OFFSET 0x000000AC
++#define VDEC_VIDSTS_OFFSET 0x000000B0
++#define VDEC_NOISE_OFFSET 0x000000B4
++#define VDEC_STDDBG_OFFSET 0x000000B8
++#define VDEC_MANOVR_OFFSET 0x000000BC
++#define VDEC_VSSGTH_OFFSET 0x000000C8
++#define VDEC_DBGFBH_OFFSET 0x000000D0
++#define VDEC_DBGFBL_OFFSET 0x000000D4
++#define VDEC_HACTS_OFFSET 0x000000D8
++#define VDEC_HACTE_OFFSET 0x000000DC
++#define VDEC_VACTS_OFFSET 0x000000E0
++#define VDEC_VACTE_OFFSET 0x000000E4
++#define VDEC_HSTIP_OFFSET 0x000000EC
++#define VDEC_BLSCRY_OFFSET 0x000000F4
++#define VDEC_BLSCRCR_OFFSET 0x000000F8
++#define VDEC_BLSCRCB_OFFSET 0x000000FC
++#define VDEC_LMAGC1_OFFSET 0x00000100
++#define VDEC_LMAGC2_OFFSET 0x00000104
++#define VDEC_CHAGC1_OFFSET 0x00000108
++#define VDEC_CHAGC2_OFFSET 0x0000010C
++#define VDEC_MINTH_OFFSET 0x00000114
++#define VDEC_VFRQOH_OFFSET 0x0000011C
++#define VDEC_VFRQOL_OFFSET 0x00000120
++#define VDEC_THSH1_OFFSET 0x00000124
++#define VDEC_THSH2_OFFSET 0x00000128
++#define VDEC_NCHTH_OFFSET 0x0000012C
++#define VDEC_TH1F_OFFSET 0x00000130
++
++/* VDEC Register per module */
++#define VDEC_CFC1 (VDEC_BASE + VDEC_CFC1_OFFSET)
++#define VDEC_CFC2 (VDEC_BASE + VDEC_CFC2_OFFSET)
++#define VDEC_BRSTGT (VDEC_BASE + VDEC_BRSTGT_OFFSET)
++#define VDEC_HZPOS (VDEC_BASE + VDEC_HZPOS_OFFSET)
++#define VDEC_VRTPOS (VDEC_BASE + VDEC_VRTPOS_OFFSET)
++#define VDEC_HVSHIFT (VDEC_BASE + VDEC_HVSHIFT_OFFSET)
++#define VDEC_HSIGS (VDEC_BASE + VDEC_HSIGS_OFFSET)
++#define VDEC_HSIGE (VDEC_BASE + VDEC_HSIGE_OFFSET)
++#define VDEC_VSCON1 (VDEC_BASE + VDEC_VSCON1_OFFSET)
++#define VDEC_VSCON2 (VDEC_BASE + VDEC_VSCON2_OFFSET)
++#define VDEC_YCDEL (VDEC_BASE + VDEC_YCDEL_OFFSET)
++#define VDEC_AFTCLP (VDEC_BASE + VDEC_AFTCLP_OFFSET)
++#define VDEC_DCOFF (VDEC_BASE + VDEC_DCOFF_OFFSET)
++#define VDEC_CSID (VDEC_BASE + VDEC_CSID_OFFSET)
++#define VDEC_CBGN (VDEC_BASE + VDEC_CBGN_OFFSET)
++#define VDEC_CRGN (VDEC_BASE + VDEC_CRGN_OFFSET)
++#define VDEC_CNTR (VDEC_BASE + VDEC_CNTR_OFFSET)
++#define VDEC_BRT (VDEC_BASE + VDEC_BRT_OFFSET)
++#define VDEC_HUE (VDEC_BASE + VDEC_HUE_OFFSET)
++#define VDEC_CHBTH (VDEC_BASE + VDEC_CHBTH_OFFSET)
++#define VDEC_SHPIMP (VDEC_BASE + VDEC_SHPIMP_OFFSET)
++#define VDEC_CHPLLIM (VDEC_BASE + VDEC_CHPLLIM_OFFSET)
++#define VDEC_VIDMOD (VDEC_BASE + VDEC_VIDMOD_OFFSET)
++#define VDEC_VIDSTS (VDEC_BASE + VDEC_VIDSTS_OFFSET)
++#define VDEC_NOISE (VDEC_BASE + VDEC_NOISE_OFFSET)
++#define VDEC_STDDBG (VDEC_BASE + VDEC_STDDBG_OFFSET)
++#define VDEC_MANOVR (VDEC_BASE + VDEC_MANOVR_OFFSET)
++#define VDEC_VSSGTH (VDEC_BASE + VDEC_VSSGTH_OFFSET)
++#define VDEC_DBGFBH (VDEC_BASE + VDEC_DBGFBH_OFFSET)
++#define VDEC_DBGFBL (VDEC_BASE + VDEC_DBGFBL_OFFSET)
++#define VDEC_HACTS (VDEC_BASE + VDEC_HACTS_OFFSET)
++#define VDEC_HACTE (VDEC_BASE + VDEC_HACTE_OFFSET)
++#define VDEC_VACTS (VDEC_BASE + VDEC_VACTS_OFFSET)
++#define VDEC_VACTE (VDEC_BASE + VDEC_VACTE_OFFSET)
++#define VDEC_HSTIP (VDEC_BASE + VDEC_HSTIP_OFFSET)
++#define VDEC_BLSCRY (VDEC_BASE + VDEC_BLSCRY_OFFSET)
++#define VDEC_BLSCRCR (VDEC_BASE + VDEC_BLSCRCR_OFFSET)
++#define VDEC_BLSCRCB (VDEC_BASE + VDEC_BLSCRCB_OFFSET)
++#define VDEC_LMAGC1 (VDEC_BASE + VDEC_LMAGC1_OFFSET)
++#define VDEC_LMAGC2 (VDEC_BASE + VDEC_LMAGC2_OFFSET)
++#define VDEC_CHAGC1 (VDEC_BASE + VDEC_CHAGC1_OFFSET)
++#define VDEC_CHAGC2 (VDEC_BASE + VDEC_CHAGC2_OFFSET)
++#define VDEC_MINTH (VDEC_BASE + VDEC_MINTH_OFFSET)
++#define VDEC_VFRQOH (VDEC_BASE + VDEC_VFRQOH_OFFSET)
++#define VDEC_VFRQOL (VDEC_BASE + VDEC_VFRQOL_OFFSET)
++#define VDEC_THSH1 (VDEC_BASE + VDEC_THSH1_OFFSET)
++#define VDEC_THSH2 (VDEC_BASE + VDEC_THSH2_OFFSET)
++#define VDEC_NCHTH (VDEC_BASE + VDEC_NCHTH_OFFSET)
++#define VDEC_TH1F (VDEC_BASE + VDEC_TH1F_OFFSET)
++
++#define VDEC_VIDMOD_SIGNAL_MASK 0x0F
++#define VDEC_VIDMOD_SIGNAL_DETECT 0x0F
++
++#define VDEC_VIDMOD_M625_SHIFT 4
++#define VDEC_VIDMOD_M625_MASK (1 << VDEC_VIDMOD_M625_SHIFT)
++
++#define VDEC_VIDMOD_PAL_SHIFT 7
++#define VDEC_VIDMOD_PAL_MASK (1 << VDEC_VIDMOD_PAL_SHIFT)
++/*** define base address ***/
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/media/platform/mxc/subdev/ov5640.c linux-3.14.72/drivers/media/platform/mxc/subdev/ov5640.c
+--- linux-3.14.72.orig/drivers/media/platform/mxc/subdev/ov5640.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/media/platform/mxc/subdev/ov5640.c 2016-06-19 22:11:55.189147618 +0200
+@@ -0,0 +1,1918 @@
++/*
++ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/v4l2-mediabus.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-ctrls.h>
++
++#define OV5640_VOLTAGE_ANALOG 2800000
++#define OV5640_VOLTAGE_DIGITAL_CORE 1500000
++#define OV5640_VOLTAGE_DIGITAL_IO 1800000
++
++#define MIN_FPS 15
++#define MAX_FPS 30
++#define DEFAULT_FPS 30
++
++#define OV5640_XCLK_MIN 6000000
++#define OV5640_XCLK_MAX 24000000
++
++#define OV5640_CHIP_ID_HIGH_BYTE 0x300A
++#define OV5640_CHIP_ID_LOW_BYTE 0x300B
++
++enum ov5640_mode {
++ ov5640_mode_MIN = 0,
++ ov5640_mode_VGA_640_480 = 0,
++ ov5640_mode_QVGA_320_240 = 1,
++ ov5640_mode_NTSC_720_480 = 2,
++ ov5640_mode_PAL_720_576 = 3,
++ ov5640_mode_720P_1280_720 = 4,
++ ov5640_mode_1080P_1920_1080 = 5,
++ ov5640_mode_QSXGA_2592_1944 = 6,
++ ov5640_mode_QCIF_176_144 = 7,
++ ov5640_mode_XGA_1024_768 = 8,
++ ov5640_mode_MAX = 8
++};
++
++enum ov5640_frame_rate {
++ ov5640_15_fps,
++ ov5640_30_fps
++};
++
++static int ov5640_framerates[] = {
++ [ov5640_15_fps] = 15,
++ [ov5640_30_fps] = 30,
++};
++
++struct ov5640_datafmt {
++ enum v4l2_mbus_pixelcode code;
++ enum v4l2_colorspace colorspace;
++};
++
++struct reg_value {
++ u16 u16RegAddr;
++ u8 u8Val;
++ u8 u8Mask;
++ u32 u32Delay_ms;
++};
++
++struct ov5640_mode_info {
++ enum ov5640_mode mode;
++ u32 width;
++ u32 height;
++ struct reg_value *init_data_ptr;
++ u32 init_data_size;
++};
++
++struct ov5640 {
++ struct v4l2_subdev subdev;
++ struct i2c_client *i2c_client;
++ struct v4l2_pix_format pix;
++ const struct ov5640_datafmt *fmt;
++ struct v4l2_captureparm streamcap;
++ bool on;
++
++ /* control settings */
++ int brightness;
++ int hue;
++ int contrast;
++ int saturation;
++ int red;
++ int green;
++ int blue;
++ int ae_mode;
++
++ u32 mclk;
++ u8 mclk_source;
++ struct clk *sensor_clk;
++ int csi;
++
++ void (*io_init)(void);
++};
++
++/*!
++ * Maintains the information on the current state of the sesor.
++ */
++static struct ov5640 ov5640_data;
++static int pwn_gpio, rst_gpio;
++static int prev_sysclk;
++static int AE_Target = 52, night_mode;
++static int prev_HTS;
++static int AE_high, AE_low;
++
++static struct reg_value ov5640_global_init_setting[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
++ {0x3034, 0x1a, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0},
++ {0x3630, 0x36, 0, 0}, {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0},
++ {0x3633, 0x12, 0, 0}, {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0},
++ {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0},
++ {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0},
++ {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0},
++ {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0},
++ {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0},
++ {0x3a13, 0x43, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0},
++ {0x3635, 0x13, 0, 0}, {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0},
++ {0x3622, 0x01, 0, 0}, {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0},
++ {0x3c05, 0x98, 0, 0}, {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3c08, 0x00, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0},
++ {0x3c0b, 0x40, 0, 0}, {0x3810, 0x00, 0, 0}, {0x3811, 0x10, 0, 0},
++ {0x3812, 0x00, 0, 0}, {0x3708, 0x64, 0, 0}, {0x4001, 0x02, 0, 0},
++ {0x4005, 0x1a, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3004, 0xff, 0, 0},
++ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x440e, 0x00, 0, 0}, {0x5000, 0xa7, 0, 0},
++ {0x3008, 0x02, 0, 0},
++};
++
++static struct reg_value ov5640_init_setting_30fps_VGA[] = {
++ {0x3008, 0x42, 0, 0},
++ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0},
++ {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0},
++ {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0},
++ {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
++ {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
++ {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
++ {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
++ {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
++ {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
++ {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
++ {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
++ {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
++ {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
++ {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
++ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
++ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0},
++ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0},
++ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0},
++ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
++ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
++ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
++ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
++ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0},
++ {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0},
++ {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
++ {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5000, 0xa7, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0xf2, 0, 0},
++ {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0},
++ {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, {0x5187, 0x09, 0, 0},
++ {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0}, {0x518a, 0x54, 0, 0},
++ {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x50, 0, 0},
++ {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0}, {0x5190, 0x46, 0, 0},
++ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0},
++ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0},
++ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x6c, 0, 0},
++ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x09, 0, 0},
++ {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0}, {0x5381, 0x1e, 0, 0},
++ {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0}, {0x5384, 0x0a, 0, 0},
++ {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, {0x5387, 0x7c, 0, 0},
++ {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, {0x538a, 0x01, 0, 0},
++ {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, {0x5301, 0x30, 0, 0},
++ {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, {0x5304, 0x08, 0, 0},
++ {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, {0x5307, 0x16, 0, 0},
++ {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, {0x530b, 0x04, 0, 0},
++ {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, {0x5481, 0x08, 0, 0},
++ {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, {0x5484, 0x51, 0, 0},
++ {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, {0x5487, 0x7d, 0, 0},
++ {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, {0x548a, 0x9a, 0, 0},
++ {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, {0x548d, 0xcd, 0, 0},
++ {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, {0x5490, 0x1d, 0, 0},
++ {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x10, 0, 0},
++ {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, {0x558b, 0xf8, 0, 0},
++ {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0}, {0x5802, 0x0f, 0, 0},
++ {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0}, {0x5805, 0x26, 0, 0},
++ {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, {0x5808, 0x05, 0, 0},
++ {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, {0x580b, 0x0d, 0, 0},
++ {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0}, {0x580e, 0x00, 0, 0},
++ {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, {0x5811, 0x09, 0, 0},
++ {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x00, 0, 0},
++ {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0}, {0x5817, 0x08, 0, 0},
++ {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0}, {0x581a, 0x05, 0, 0},
++ {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0}, {0x581d, 0x0e, 0, 0},
++ {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0}, {0x5820, 0x11, 0, 0},
++ {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, {0x5823, 0x28, 0, 0},
++ {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0}, {0x5826, 0x08, 0, 0},
++ {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0}, {0x5829, 0x26, 0, 0},
++ {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0}, {0x582c, 0x24, 0, 0},
++ {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0}, {0x582f, 0x22, 0, 0},
++ {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0}, {0x5832, 0x24, 0, 0},
++ {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0}, {0x5835, 0x22, 0, 0},
++ {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0}, {0x5838, 0x44, 0, 0},
++ {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0}, {0x583b, 0x28, 0, 0},
++ {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, {0x5025, 0x00, 0, 0},
++ {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0},
++ {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0},
++ {0x3008, 0x02, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_VGA_640_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_VGA_640_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
++ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0},
++ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_PAL_720_576[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_PAL_720_576[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0},
++ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_720P_1280_720[] = {
++ {0x3035, 0x21, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
++ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
++ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++ {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_720P_1280_720[] = {
++ {0x3035, 0x41, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0},
++ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
++ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
++ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
++ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
++ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0},
++ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0},
++ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0},
++ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0},
++ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0},
++ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0},
++ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0},
++ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
++ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
++ {0x3503, 0x00, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0},
++ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
++ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = {
++ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0},
++ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0},
++ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0},
++ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0},
++ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0},
++ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0},
++ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0},
++ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++
++static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = {
++ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
++ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0xee, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x05, 0, 0},
++ {0x3807, 0xc3, 0, 0}, {0x3808, 0x07, 0, 0}, {0x3809, 0x80, 0, 0},
++ {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, {0x380c, 0x0b, 0, 0},
++ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
++ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
++ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
++ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = {
++ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0},
++ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0},
++ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0},
++ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0},
++ {0x3807, 0x9f, 0, 0}, {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0},
++ {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0},
++ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0},
++ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0},
++ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0},
++ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0},
++ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0},
++ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0},
++ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0},
++ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0},
++ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0},
++};
++
++static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = {
++ {
++ {ov5640_mode_VGA_640_480, 640, 480,
++ ov5640_setting_15fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, 320, 240,
++ ov5640_setting_15fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, 720, 480,
++ ov5640_setting_15fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, 720, 576,
++ ov5640_setting_15fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, 1280, 720,
++ ov5640_setting_15fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, 1920, 1080,
++ ov5640_setting_15fps_1080P_1920_1080,
++ ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)},
++ {ov5640_mode_QSXGA_2592_1944, 2592, 1944,
++ ov5640_setting_15fps_QSXGA_2592_1944,
++ ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)},
++ {ov5640_mode_QCIF_176_144, 176, 144,
++ ov5640_setting_15fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, 1024, 768,
++ ov5640_setting_15fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)},
++ },
++ {
++ {ov5640_mode_VGA_640_480, 640, 480,
++ ov5640_setting_30fps_VGA_640_480,
++ ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)},
++ {ov5640_mode_QVGA_320_240, 320, 240,
++ ov5640_setting_30fps_QVGA_320_240,
++ ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)},
++ {ov5640_mode_NTSC_720_480, 720, 480,
++ ov5640_setting_30fps_NTSC_720_480,
++ ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)},
++ {ov5640_mode_PAL_720_576, 720, 576,
++ ov5640_setting_30fps_PAL_720_576,
++ ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)},
++ {ov5640_mode_720P_1280_720, 1280, 720,
++ ov5640_setting_30fps_720P_1280_720,
++ ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)},
++ {ov5640_mode_1080P_1920_1080, 0, 0, NULL, 0},
++ {ov5640_mode_QSXGA_2592_1944, 0, 0, NULL, 0},
++ {ov5640_mode_QCIF_176_144, 176, 144,
++ ov5640_setting_30fps_QCIF_176_144,
++ ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)},
++ {ov5640_mode_XGA_1024_768, 1024, 768,
++ ov5640_setting_30fps_XGA_1024_768,
++ ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)},
++ },
++};
++
++static struct regulator *io_regulator;
++static struct regulator *core_regulator;
++static struct regulator *analog_regulator;
++
++static int ov5640_probe(struct i2c_client *adapter,
++ const struct i2c_device_id *device_id);
++static int ov5640_remove(struct i2c_client *client);
++
++static s32 ov5640_read_reg(u16 reg, u8 *val);
++static s32 ov5640_write_reg(u16 reg, u8 val);
++
++static const struct i2c_device_id ov5640_id[] = {
++ {"ov5640", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, ov5640_id);
++
++static struct i2c_driver ov5640_i2c_driver = {
++ .driver = {
++ .owner = THIS_MODULE,
++ .name = "ov5640",
++ },
++ .probe = ov5640_probe,
++ .remove = ov5640_remove,
++ .id_table = ov5640_id,
++};
++
++static const struct ov5640_datafmt ov5640_colour_fmts[] = {
++ {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
++};
++
++static struct ov5640 *to_ov5640(const struct i2c_client *client)
++{
++ return container_of(i2c_get_clientdata(client), struct ov5640, subdev);
++}
++
++/* Find a data format by a pixel code in an array */
++static const struct ov5640_datafmt
++ *ov5640_find_datafmt(enum v4l2_mbus_pixelcode code)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(ov5640_colour_fmts); i++)
++ if (ov5640_colour_fmts[i].code == code)
++ return ov5640_colour_fmts + i;
++
++ return NULL;
++}
++
++static inline void ov5640_power_down(int enable)
++{
++ gpio_set_value(pwn_gpio, enable);
++
++ msleep(2);
++}
++
++static inline void ov5640_reset(void)
++{
++ /* camera reset */
++ gpio_set_value(rst_gpio, 1);
++
++ /* camera power down */
++ gpio_set_value(pwn_gpio, 1);
++ msleep(5);
++ gpio_set_value(pwn_gpio, 0);
++ msleep(5);
++ gpio_set_value(rst_gpio, 0);
++ msleep(1);
++ gpio_set_value(rst_gpio, 1);
++ msleep(5);
++ gpio_set_value(pwn_gpio, 1);
++}
++
++static int ov5640_regulator_enable(struct device *dev)
++{
++ int ret = 0;
++
++ io_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(io_regulator)) {
++ regulator_set_voltage(io_regulator,
++ OV5640_VOLTAGE_DIGITAL_IO,
++ OV5640_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(io_regulator);
++ if (ret) {
++ dev_err(dev, "set io voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set io voltage ok\n");
++ }
++ } else {
++ io_regulator = NULL;
++ dev_warn(dev, "cannot get io voltage\n");
++ }
++
++ core_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(core_regulator)) {
++ regulator_set_voltage(core_regulator,
++ OV5640_VOLTAGE_DIGITAL_CORE,
++ OV5640_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(core_regulator);
++ if (ret) {
++ dev_err(dev, "set core voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set core voltage ok\n");
++ }
++ } else {
++ core_regulator = NULL;
++ dev_warn(dev, "cannot get core voltage\n");
++ }
++
++ analog_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(analog_regulator)) {
++ regulator_set_voltage(analog_regulator,
++ OV5640_VOLTAGE_ANALOG,
++ OV5640_VOLTAGE_ANALOG);
++ ret = regulator_enable(analog_regulator);
++ if (ret) {
++ dev_err(dev, "set analog voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set analog voltage ok\n");
++ }
++ } else {
++ analog_regulator = NULL;
++ dev_warn(dev, "cannot get analog voltage\n");
++ }
++
++ return ret;
++}
++
++static s32 ov5640_write_reg(u16 reg, u8 val)
++{
++ u8 au8Buf[3] = {0};
++
++ au8Buf[0] = reg >> 8;
++ au8Buf[1] = reg & 0xff;
++ au8Buf[2] = val;
++
++ if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
++ pr_err("%s:write reg error:reg=%x,val=%x\n",
++ __func__, reg, val);
++ return -1;
++ }
++
++ return 0;
++}
++
++static s32 ov5640_read_reg(u16 reg, u8 *val)
++{
++ u8 au8RegBuf[2] = {0};
++ u8 u8RdVal = 0;
++
++ au8RegBuf[0] = reg >> 8;
++ au8RegBuf[1] = reg & 0xff;
++
++ if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) {
++ pr_err("%s:write reg error:reg=%x\n",
++ __func__, reg);
++ return -1;
++ }
++
++ if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) {
++ pr_err("%s:read reg error:reg=%x,val=%x\n",
++ __func__, reg, u8RdVal);
++ return -1;
++ }
++
++ *val = u8RdVal;
++
++ return u8RdVal;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int ov5640_get_register(struct v4l2_subdev *sd,
++ struct v4l2_dbg_register *reg)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ int ret;
++ u8 val;
++
++ if (reg->reg & ~0xffff)
++ return -EINVAL;
++
++ reg->size = 1;
++
++ ret = ov5640_read_reg(reg->reg, &val);
++ if (!ret)
++ reg->val = (__u64)val;
++
++ return ret;
++}
++
++static int ov5640_set_register(struct v4l2_subdev *sd,
++ const struct v4l2_dbg_register *reg)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++
++ if (reg->reg & ~0xffff || reg->val & ~0xff)
++ return -EINVAL;
++
++ return ov5640_write_reg(reg->reg, reg->val);
++}
++#endif
++
++static void ov5640_soft_reset(void)
++{
++ /* sysclk from pad */
++ ov5640_write_reg(0x3103, 0x11);
++
++ /* software reset */
++ ov5640_write_reg(0x3008, 0x82);
++
++ /* delay at least 5ms */
++ msleep(10);
++}
++
++/* set sensor driver capability
++ * 0x302c[7:6] - strength
++ 00 - 1x
++ 01 - 2x
++ 10 - 3x
++ 11 - 4x
++ */
++static int ov5640_driver_capability(int strength)
++{
++ u8 temp = 0;
++
++ if (strength > 4 || strength < 1) {
++ pr_err("The valid driver capability of ov5640 is 1x~4x\n");
++ return -EINVAL;
++ }
++
++ ov5640_read_reg(0x302c, &temp);
++
++ temp &= ~0xc0; /* clear [7:6] */
++ temp |= ((strength - 1) << 6); /* set [7:6] */
++
++ ov5640_write_reg(0x302c, temp);
++
++ return 0;
++}
++
++/* calculate sysclk */
++static int ov5640_get_sysclk(void)
++{
++ int xvclk = ov5640_data.mclk / 10000;
++ int sysclk;
++ int temp1, temp2;
++ int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv;
++ int sclk_rdiv_map[] = {1, 2, 4, 8};
++ u8 regval = 0;
++
++ temp1 = ov5640_read_reg(0x3034, &regval);
++ temp2 = temp1 & 0x0f;
++ if (temp2 == 8 || temp2 == 10) {
++ Bit_div2x = temp2 / 2;
++ } else {
++ pr_err("ov5640: unsupported bit mode %d\n", temp2);
++ return -1;
++ }
++
++ temp1 = ov5640_read_reg(0x3035, &regval);
++ SysDiv = temp1 >> 4;
++ if (SysDiv == 0)
++ SysDiv = 16;
++
++ temp1 = ov5640_read_reg(0x3036, &regval);
++ Multiplier = temp1;
++ temp1 = ov5640_read_reg(0x3037, &regval);
++ PreDiv = temp1 & 0x0f;
++ Pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
++
++ temp1 = ov5640_read_reg(0x3108, &regval);
++ temp2 = temp1 & 0x03;
++
++ sclk_rdiv = sclk_rdiv_map[temp2];
++ VCO = xvclk * Multiplier / PreDiv;
++ sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv;
++
++ return sysclk;
++}
++
++/* read HTS from register settings */
++static int ov5640_get_HTS(void)
++{
++ int HTS;
++ u8 temp = 0;
++
++ HTS = ov5640_read_reg(0x380c, &temp);
++ HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp);
++ return HTS;
++}
++
++/* read VTS from register settings */
++static int ov5640_get_VTS(void)
++{
++ int VTS;
++ u8 temp = 0;
++
++ VTS = ov5640_read_reg(0x380e, &temp);
++ VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp);
++
++ return VTS;
++}
++
++/* write VTS to registers */
++static int ov5640_set_VTS(int VTS)
++{
++ int temp;
++
++ temp = VTS & 0xff;
++ ov5640_write_reg(0x380f, temp);
++
++ temp = VTS>>8;
++ ov5640_write_reg(0x380e, temp);
++ return 0;
++}
++
++/* read shutter, in number of line period */
++static int ov5640_get_shutter(void)
++{
++ int shutter;
++ u8 regval;
++
++ shutter = (ov5640_read_reg(0x03500, &regval) & 0x0f);
++
++ shutter = (shutter<<8) + ov5640_read_reg(0x3501, &regval);
++ shutter = (shutter<<4) + (ov5640_read_reg(0x3502, &regval)>>4);
++
++ return shutter;
++}
++
++/* write shutter, in number of line period */
++static int ov5640_set_shutter(int shutter)
++{
++ int temp;
++
++ shutter = shutter & 0xffff;
++ temp = shutter & 0x0f;
++ temp = temp<<4;
++ ov5640_write_reg(0x3502, temp);
++
++ temp = shutter & 0xfff;
++ temp = temp>>4;
++ ov5640_write_reg(0x3501, temp);
++
++ temp = shutter>>12;
++ ov5640_write_reg(0x3500, temp);
++
++ return 0;
++}
++
++/* read gain, 16 = 1x */
++static int ov5640_get_gain16(void)
++{
++ int gain16;
++ u8 regval;
++
++ gain16 = ov5640_read_reg(0x350a, &regval) & 0x03;
++ gain16 = (gain16<<8) + ov5640_read_reg(0x350b, &regval);
++
++ return gain16;
++}
++
++/* write gain, 16 = 1x */
++static int ov5640_set_gain16(int gain16)
++{
++ int temp;
++
++ gain16 = gain16 & 0x3ff;
++ temp = gain16 & 0xff;
++
++ ov5640_write_reg(0x350b, temp);
++ temp = gain16>>8;
++
++ ov5640_write_reg(0x350a, temp);
++ return 0;
++}
++
++/* get banding filter value */
++static int ov5640_get_light_freq(void)
++{
++ int temp, temp1, light_frequency;
++ u8 regval;
++
++ temp = ov5640_read_reg(0x3c01, &regval);
++ if (temp & 0x80) {
++ /* manual */
++ temp1 = ov5640_read_reg(0x3c00, &regval);
++ if (temp1 & 0x04) {
++ /* 50Hz */
++ light_frequency = 50;
++ } else {
++ /* 60Hz */
++ light_frequency = 60;
++ }
++ } else {
++ /* auto */
++ temp1 = ov5640_read_reg(0x3c0c, &regval);
++ if (temp1 & 0x01) {
++ /* 50Hz */
++ light_frequency = 50;
++ } else {
++ /* 60Hz */
++ light_frequency = 60;
++ }
++ }
++
++ return light_frequency;
++}
++
++static void ov5640_set_bandingfilter(void)
++{
++ int prev_VTS;
++ int band_step60, max_band60, band_step50, max_band50;
++
++ /* read preview PCLK */
++ prev_sysclk = ov5640_get_sysclk();
++
++ /* read preview HTS */
++ prev_HTS = ov5640_get_HTS();
++
++ /* read preview VTS */
++ prev_VTS = ov5640_get_VTS();
++
++ /* calculate banding filter */
++ /* 60Hz */
++ band_step60 = prev_sysclk * 100/prev_HTS * 100/120;
++ ov5640_write_reg(0x3a0a, (band_step60 >> 8));
++ ov5640_write_reg(0x3a0b, (band_step60 & 0xff));
++
++ max_band60 = (int)((prev_VTS-4)/band_step60);
++ ov5640_write_reg(0x3a0d, max_band60);
++
++ /* 50Hz */
++ band_step50 = prev_sysclk * 100/prev_HTS;
++ ov5640_write_reg(0x3a08, (band_step50 >> 8));
++ ov5640_write_reg(0x3a09, (band_step50 & 0xff));
++
++ max_band50 = (int)((prev_VTS-4)/band_step50);
++ ov5640_write_reg(0x3a0e, max_band50);
++}
++
++/* stable in high */
++static int ov5640_set_AE_target(int target)
++{
++ int fast_high, fast_low;
++
++ AE_low = target * 23 / 25; /* 0.92 */
++ AE_high = target * 27 / 25; /* 1.08 */
++ fast_high = AE_high << 1;
++
++ if (fast_high > 255)
++ fast_high = 255;
++ fast_low = AE_low >> 1;
++
++ ov5640_write_reg(0x3a0f, AE_high);
++ ov5640_write_reg(0x3a10, AE_low);
++ ov5640_write_reg(0x3a1b, AE_high);
++ ov5640_write_reg(0x3a1e, AE_low);
++ ov5640_write_reg(0x3a11, fast_high);
++ ov5640_write_reg(0x3a1f, fast_low);
++
++ return 0;
++}
++
++/* enable = 0 to turn off night mode
++ enable = 1 to turn on night mode */
++static int ov5640_set_night_mode(int enable)
++{
++ u8 mode;
++
++ ov5640_read_reg(0x3a00, &mode);
++
++ if (enable) {
++ /* night mode on */
++ mode |= 0x04;
++ ov5640_write_reg(0x3a00, mode);
++ } else {
++ /* night mode off */
++ mode &= 0xfb;
++ ov5640_write_reg(0x3a00, mode);
++ }
++
++ return 0;
++}
++
++/* enable = 0 to turn off AEC/AGC
++ enable = 1 to turn on AEC/AGC */
++static void ov5640_turn_on_AE_AG(int enable)
++{
++ u8 ae_ag_ctrl;
++
++ ov5640_read_reg(0x3503, &ae_ag_ctrl);
++ if (enable) {
++ /* turn on auto AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl & ~(0x03);
++ } else {
++ /* turn off AE/AG */
++ ae_ag_ctrl = ae_ag_ctrl | 0x03;
++ }
++ ov5640_write_reg(0x3503, ae_ag_ctrl);
++}
++
++/* download ov5640 settings to sensor through i2c */
++static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize)
++{
++ register u32 Delay_ms = 0;
++ register u16 RegAddr = 0;
++ register u8 Mask = 0;
++ register u8 Val = 0;
++ u8 RegVal = 0;
++ int i, retval = 0;
++
++ for (i = 0; i < ArySize; ++i, ++pModeSetting) {
++ Delay_ms = pModeSetting->u32Delay_ms;
++ RegAddr = pModeSetting->u16RegAddr;
++ Val = pModeSetting->u8Val;
++ Mask = pModeSetting->u8Mask;
++
++ if (Mask) {
++ retval = ov5640_read_reg(RegAddr, &RegVal);
++ if (retval < 0)
++ goto err;
++
++ RegVal &= ~(u8)Mask;
++ Val &= Mask;
++ Val |= RegVal;
++ }
++
++ retval = ov5640_write_reg(RegAddr, Val);
++ if (retval < 0)
++ goto err;
++
++ if (Delay_ms)
++ msleep(Delay_ms);
++ }
++err:
++ return retval;
++}
++
++static int ov5640_init_mode(void)
++{
++ struct reg_value *pModeSetting = NULL;
++ int ArySize = 0, retval = 0;
++
++ ov5640_soft_reset();
++
++ pModeSetting = ov5640_global_init_setting;
++ ArySize = ARRAY_SIZE(ov5640_global_init_setting);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ pModeSetting = ov5640_init_setting_30fps_VGA;
++ ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA);
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* change driver capability to 2x according to validation board.
++ * if the image is not stable, please increase the driver strength.
++ */
++ ov5640_driver_capability(2);
++ ov5640_set_bandingfilter();
++ ov5640_set_AE_target(AE_Target);
++ ov5640_set_night_mode(night_mode);
++
++ /* skip 9 vysnc: start capture at 10th vsync */
++ msleep(300);
++
++ /* turn off night mode */
++ night_mode = 0;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++err:
++ return retval;
++}
++
++/* change to or back to subsampling mode set the mode directly
++ * image size below 1280 * 960 is subsampling mode */
++static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ pModeSetting = ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width = ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height = ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* set ov5640 to subsampling mode */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++
++ /* turn on AE AG for subsampling mode, in case the firmware didn't */
++ ov5640_turn_on_AE_AG(1);
++
++ /* calculate banding filter */
++ ov5640_set_bandingfilter();
++
++ /* set AE target */
++ ov5640_set_AE_target(AE_Target);
++
++ /* update night mode setting */
++ ov5640_set_night_mode(night_mode);
++
++ /* skip 9 vysnc: start capture at 10th vsync */
++ if (mode == ov5640_mode_XGA_1024_768 && frame_rate == ov5640_30_fps) {
++ pr_warning("ov5640: actual frame rate of XGA is 22.5fps\n");
++ /* 1/22.5 * 9*/
++ msleep(400);
++ return retval;
++ }
++
++ if (frame_rate == ov5640_15_fps) {
++ /* 1/15 * 9*/
++ msleep(600);
++ } else if (frame_rate == ov5640_30_fps) {
++ /* 1/30 * 9*/
++ msleep(300);
++ }
++
++ return retval;
++}
++
++/* change to scaling mode go through exposure calucation
++ * image size above 1280 * 960 is scaling mode */
++static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ int prev_shutter, prev_gain16, average;
++ int cap_shutter, cap_gain16;
++ int cap_sysclk, cap_HTS, cap_VTS;
++ int light_freq, cap_bandfilt, cap_maxband;
++ long cap_gain16_shutter;
++ u8 temp;
++ struct reg_value *pModeSetting = NULL;
++ s32 ArySize = 0;
++ int retval = 0;
++
++ /* check if the input mode and frame rate is valid */
++ pModeSetting =
++ ov5640_mode_info_data[frame_rate][mode].init_data_ptr;
++ ArySize =
++ ov5640_mode_info_data[frame_rate][mode].init_data_size;
++
++ ov5640_data.pix.width =
++ ov5640_mode_info_data[frame_rate][mode].width;
++ ov5640_data.pix.height =
++ ov5640_mode_info_data[frame_rate][mode].height;
++
++ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 ||
++ pModeSetting == NULL || ArySize == 0)
++ return -EINVAL;
++
++ /* read preview shutter */
++ prev_shutter = ov5640_get_shutter();
++
++ /* read preview gain */
++ prev_gain16 = ov5640_get_gain16();
++
++ /* get average */
++ average = ov5640_read_reg(0x56a1, &temp);
++
++ /* turn off night mode for capture */
++ ov5640_set_night_mode(0);
++
++ /* turn off overlay */
++ ov5640_write_reg(0x3022, 0x06);
++
++ /* Write capture setting */
++ retval = ov5640_download_firmware(pModeSetting, ArySize);
++ if (retval < 0)
++ goto err;
++
++ /* turn off AE AG when capture image. */
++ ov5640_turn_on_AE_AG(0);
++
++ /* read capture VTS */
++ cap_VTS = ov5640_get_VTS();
++ cap_HTS = ov5640_get_HTS();
++ cap_sysclk = ov5640_get_sysclk();
++
++ /* calculate capture banding filter */
++ light_freq = ov5640_get_light_freq();
++ if (light_freq == 60) {
++ /* 60Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120;
++ } else {
++ /* 50Hz */
++ cap_bandfilt = cap_sysclk * 100 / cap_HTS;
++ }
++ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt);
++ /* calculate capture shutter/gain16 */
++ if (average > AE_low && average < AE_high) {
++ /* in stable range */
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
++ prev_HTS/cap_HTS * AE_Target / average;
++ } else {
++ cap_gain16_shutter =
++ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk *
++ prev_HTS/cap_HTS;
++ }
++
++ /* gain to shutter */
++ if (cap_gain16_shutter < (cap_bandfilt * 16)) {
++ /* shutter < 1/100 */
++ cap_shutter = cap_gain16_shutter/16;
++ if (cap_shutter < 1)
++ cap_shutter = 1;
++ cap_gain16 = cap_gain16_shutter/cap_shutter;
++ if (cap_gain16 < 16)
++ cap_gain16 = 16;
++ } else {
++ if (cap_gain16_shutter > (cap_bandfilt*cap_maxband*16)) {
++ /* exposure reach max */
++ cap_shutter = cap_bandfilt*cap_maxband;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ } else {
++ /* 1/100 < cap_shutter =< max, cap_shutter = n/100 */
++ cap_shutter =
++ ((int)(cap_gain16_shutter/16/cap_bandfilt))
++ * cap_bandfilt;
++ cap_gain16 = cap_gain16_shutter / cap_shutter;
++ }
++ }
++
++ /* write capture gain */
++ ov5640_set_gain16(cap_gain16);
++
++ /* write capture shutter */
++ if (cap_shutter > (cap_VTS - 4)) {
++ cap_VTS = cap_shutter + 4;
++ ov5640_set_VTS(cap_VTS);
++ }
++
++ ov5640_set_shutter(cap_shutter);
++
++ /* skip 2 vysnc: start capture at 3rd vsync
++ * frame rate of QSXGA and 1080P is 7.5fps: 1/7.5 * 2
++ */
++ pr_warning("ov5640: the actual frame rate of %s is 7.5fps\n",
++ mode == ov5640_mode_1080P_1920_1080 ? "1080P" : "QSXGA");
++ msleep(267);
++err:
++ return retval;
++}
++
++static int ov5640_change_mode(enum ov5640_frame_rate frame_rate,
++ enum ov5640_mode mode)
++{
++ int retval = 0;
++
++ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) {
++ pr_err("Wrong ov5640 mode detected!\n");
++ return -1;
++ }
++
++ if (mode == ov5640_mode_1080P_1920_1080 ||
++ mode == ov5640_mode_QSXGA_2592_1944) {
++ /* change to scaling mode go through exposure calucation
++ * image size above 1280 * 960 is scaling mode */
++ retval = ov5640_change_mode_exposure_calc(frame_rate, mode);
++ } else {
++ /* change back to subsampling modem download firmware directly
++ * image size below 1280 * 960 is subsampling mode */
++ retval = ov5640_change_mode_direct(frame_rate, mode);
++ }
++
++ return retval;
++}
++
++/*!
++ * ov5640_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @on: indicates power mode (on or off)
++ *
++ * Turns the power on or off, depending on the value of on and returns the
++ * appropriate error code.
++ */
++static int ov5640_s_power(struct v4l2_subdev *sd, int on)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ov5640 *sensor = to_ov5640(client);
++
++ if (on)
++ clk_enable(ov5640_data.sensor_clk);
++ else
++ clk_disable(ov5640_data.sensor_clk);
++
++ if (on && !sensor->on) {
++ if (io_regulator)
++ if (regulator_enable(io_regulator) != 0)
++ return -EIO;
++ if (core_regulator)
++ if (regulator_enable(core_regulator) != 0)
++ return -EIO;
++ if (analog_regulator)
++ if (regulator_enable(analog_regulator) != 0)
++ return -EIO;
++ /* Make sure power on */
++ ov5640_power_down(0);
++ } else if (!on && sensor->on) {
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++ if (core_regulator)
++ regulator_disable(core_regulator);
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ ov5640_power_down(1);
++ }
++
++ sensor->on = on;
++
++ return 0;
++}
++
++static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
++{
++ if (enable) {
++ clk_enable(ov5640_data.sensor_clk);
++ ov5640_power_down(0);
++ } else {
++ ov5640_power_down(1);
++ clk_disable(ov5640_data.sensor_clk);
++ }
++ return 0;
++}
++
++/*!
++ * ov5640_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
++ * @s: pointer to standard V4L2 sub device structure
++ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
++ *
++ * Returns the sensor's video CAPTURE parameters.
++ */
++static int ov5640_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ov5640 *sensor = to_ov5640(client);
++ struct v4l2_captureparm *cparm = &a->parm.capture;
++ int ret = 0;
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ memset(a, 0, sizeof(*a));
++ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
++ cparm->capability = sensor->streamcap.capability;
++ cparm->timeperframe = sensor->streamcap.timeperframe;
++ cparm->capturemode = sensor->streamcap.capturemode;
++ ret = 0;
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++/*!
++ * ov5460_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
++ * @s: pointer to standard V4L2 sub device structure
++ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
++ *
++ * Configures the sensor to use the input parameters, if possible. If
++ * not possible, reverts to the old parameters and returns the
++ * appropriate error code.
++ */
++static int ov5640_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ov5640 *sensor = to_ov5640(client);
++ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ int ret = 0;
++
++ /* Make sure power on */
++ clk_enable(ov5640_data.sensor_clk);
++ ov5640_power_down(0);
++
++ switch (a->type) {
++ /* This is the only case currently handled. */
++ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
++ /* Check that the new frame rate is allowed. */
++ if ((timeperframe->numerator == 0) ||
++ (timeperframe->denominator == 0)) {
++ timeperframe->denominator = DEFAULT_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps > MAX_FPS) {
++ timeperframe->denominator = MAX_FPS;
++ timeperframe->numerator = 1;
++ } else if (tgt_fps < MIN_FPS) {
++ timeperframe->denominator = MIN_FPS;
++ timeperframe->numerator = 1;
++ }
++
++ /* Actual frame rate we use */
++ tgt_fps = timeperframe->denominator /
++ timeperframe->numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else {
++ pr_err(" The camera frame rate is not supported!\n");
++ goto error;
++ }
++
++ ret = ov5640_change_mode(frame_rate,
++ a->parm.capture.capturemode);
++ if (ret < 0)
++ goto error;
++
++ sensor->streamcap.timeperframe = *timeperframe;
++ sensor->streamcap.capturemode = a->parm.capture.capturemode;
++
++ break;
++
++ /* These are all the possible cases. */
++ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
++ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
++ case V4L2_BUF_TYPE_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_VBI_OUTPUT:
++ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
++ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
++ pr_debug(" type is not " \
++ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
++ a->type);
++ ret = -EINVAL;
++ break;
++
++ default:
++ pr_debug(" type is unknown - %d\n", a->type);
++ ret = -EINVAL;
++ break;
++ }
++
++error:
++ ov5640_power_down(1);
++ clk_disable(ov5640_data.sensor_clk);
++ return ret;
++}
++
++static int ov5640_try_fmt(struct v4l2_subdev *sd,
++ struct v4l2_mbus_framefmt *mf)
++{
++ const struct ov5640_datafmt *fmt = ov5640_find_datafmt(mf->code);
++
++ if (!fmt) {
++ mf->code = ov5640_colour_fmts[0].code;
++ mf->colorspace = ov5640_colour_fmts[0].colorspace;
++ }
++
++ mf->field = V4L2_FIELD_NONE;
++
++ return 0;
++}
++
++static int ov5640_s_fmt(struct v4l2_subdev *sd,
++ struct v4l2_mbus_framefmt *mf)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ov5640 *sensor = to_ov5640(client);
++
++ /* MIPI CSI could have changed the format, double-check */
++ if (!ov5640_find_datafmt(mf->code))
++ return -EINVAL;
++
++ ov5640_try_fmt(sd, mf);
++ sensor->fmt = ov5640_find_datafmt(mf->code);
++
++ return 0;
++}
++
++static int ov5640_g_fmt(struct v4l2_subdev *sd,
++ struct v4l2_mbus_framefmt *mf)
++{
++ struct i2c_client *client = v4l2_get_subdevdata(sd);
++ struct ov5640 *sensor = to_ov5640(client);
++
++ const struct ov5640_datafmt *fmt = sensor->fmt;
++
++ mf->code = fmt->code;
++ mf->colorspace = fmt->colorspace;
++ mf->field = V4L2_FIELD_NONE;
++
++ return 0;
++}
++
++static int ov5640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
++ enum v4l2_mbus_pixelcode *code)
++{
++ if (index >= ARRAY_SIZE(ov5640_colour_fmts))
++ return -EINVAL;
++
++ *code = ov5640_colour_fmts[index].code;
++ return 0;
++}
++
++/*!
++ * ov5640_enum_framesizes - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMESIZES ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ov5640_enum_framesizes(struct v4l2_subdev *sd,
++ struct v4l2_frmsizeenum *fsize)
++{
++ if (fsize->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
++ fsize->discrete.width =
++ max(ov5640_mode_info_data[0][fsize->index].width,
++ ov5640_mode_info_data[1][fsize->index].width);
++ fsize->discrete.height =
++ max(ov5640_mode_info_data[0][fsize->index].height,
++ ov5640_mode_info_data[1][fsize->index].height);
++ return 0;
++}
++
++/*!
++ * ov5640_enum_frameintervals - V4L2 sensor interface handler for
++ * VIDIOC_ENUM_FRAMEINTERVALS ioctl
++ * @s: pointer to standard V4L2 device structure
++ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure
++ *
++ * Return 0 if successful, otherwise -EINVAL.
++ */
++static int ov5640_enum_frameintervals(struct v4l2_subdev *sd,
++ struct v4l2_frmivalenum *fival)
++{
++ int i, j, count;
++
++ if (fival->index < 0 || fival->index > ov5640_mode_MAX)
++ return -EINVAL;
++
++ if (fival->width == 0 || fival->height == 0 ||
++ fival->pixel_format == 0) {
++ pr_warning("Please assign pixelformat, width and height.\n");
++ return -EINVAL;
++ }
++
++ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
++ fival->discrete.numerator = 1;
++
++ count = 0;
++ for (i = 0; i < ARRAY_SIZE(ov5640_mode_info_data); i++) {
++ for (j = 0; j < (ov5640_mode_MAX + 1); j++) {
++ if (fival->pixel_format == ov5640_data.pix.pixelformat
++ && fival->width == ov5640_mode_info_data[i][j].width
++ && fival->height == ov5640_mode_info_data[i][j].height
++ && ov5640_mode_info_data[i][j].init_data_ptr != NULL) {
++ count++;
++ }
++ if (fival->index == (count - 1)) {
++ fival->discrete.denominator =
++ ov5640_framerates[i];
++ return 0;
++ }
++ }
++ }
++
++ return -EINVAL;
++}
++
++/*!
++ * dev_init - V4L2 sensor init
++ * @s: pointer to standard V4L2 device structure
++ *
++ */
++static int init_device(void)
++{
++ u32 tgt_xclk; /* target xclk */
++ u32 tgt_fps; /* target frames per secound */
++ enum ov5640_frame_rate frame_rate;
++ int ret;
++
++ ov5640_data.on = true;
++
++ /* mclk */
++ tgt_xclk = ov5640_data.mclk;
++ tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX);
++ tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN);
++ ov5640_data.mclk = tgt_xclk;
++
++ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000);
++ clk_set_rate(ov5640_data.sensor_clk, ov5640_data.mclk);
++
++ /* Default camera frame rate is set in probe */
++ tgt_fps = ov5640_data.streamcap.timeperframe.denominator /
++ ov5640_data.streamcap.timeperframe.numerator;
++
++ if (tgt_fps == 15)
++ frame_rate = ov5640_15_fps;
++ else if (tgt_fps == 30)
++ frame_rate = ov5640_30_fps;
++ else
++ return -EINVAL; /* Only support 15fps or 30fps now. */
++
++ ret = ov5640_init_mode();
++
++ return ret;
++}
++
++static struct v4l2_subdev_video_ops ov5640_subdev_video_ops = {
++ .s_stream = ov5640_s_stream,
++ .g_parm = ov5640_g_parm,
++ .s_parm = ov5640_s_parm,
++
++ .s_mbus_fmt = ov5640_s_fmt,
++ .g_mbus_fmt = ov5640_g_fmt,
++ .try_mbus_fmt = ov5640_try_fmt,
++ .enum_mbus_fmt = ov5640_enum_fmt,
++ .enum_framesizes = ov5640_enum_framesizes,
++ .enum_frameintervals = ov5640_enum_frameintervals,
++};
++
++static struct v4l2_subdev_core_ops ov5640_subdev_core_ops = {
++ .s_power = ov5640_s_power,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++ .g_register = ov5640_get_register,
++ .s_register = ov5640_set_register,
++#endif
++};
++
++static struct v4l2_subdev_ops ov5640_subdev_ops = {
++ .core = &ov5640_subdev_core_ops,
++ .video = &ov5640_subdev_video_ops,
++};
++
++/*!
++ * ov5640 I2C probe function
++ *
++ * @param adapter struct i2c_adapter *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct pinctrl *pinctrl;
++ struct device *dev = &client->dev;
++ int retval;
++ u8 chip_id_high, chip_id_low;
++
++ /* ov5640 pinctrl */
++ pinctrl = devm_pinctrl_get_select_default(dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(dev, "setup pinctrl failed\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ /* request power down pin */
++ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
++ if (!gpio_is_valid(pwn_gpio)) {
++ dev_err(dev, "no sensor pwdn pin available\n");
++ return -ENODEV;
++ }
++ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_pwdn");
++ if (retval < 0)
++ return retval;
++
++ /* request reset pin */
++ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
++ if (!gpio_is_valid(rst_gpio)) {
++ dev_err(dev, "no sensor reset pin available\n");
++ return -EINVAL;
++ }
++ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
++ "ov5640_reset");
++ if (retval < 0)
++ return retval;
++
++ /* Set initial values for the sensor struct. */
++ memset(&ov5640_data, 0, sizeof(ov5640_data));
++ ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk");
++ if (IS_ERR(ov5640_data.sensor_clk)) {
++ dev_err(dev, "get mclk failed\n");
++ return PTR_ERR(ov5640_data.sensor_clk);
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk",
++ &ov5640_data.mclk);
++ if (retval) {
++ dev_err(dev, "mclk frequency is invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "mclk_source",
++ (u32 *) &(ov5640_data.mclk_source));
++ if (retval) {
++ dev_err(dev, "mclk_source invalid\n");
++ return retval;
++ }
++
++ retval = of_property_read_u32(dev->of_node, "csi_id",
++ &(ov5640_data.csi));
++ if (retval) {
++ dev_err(dev, "csi_id invalid\n");
++ return retval;
++ }
++
++ clk_prepare_enable(ov5640_data.sensor_clk);
++
++ ov5640_data.io_init = ov5640_reset;
++ ov5640_data.i2c_client = client;
++ ov5640_data.pix.pixelformat = V4L2_PIX_FMT_YUYV;
++ ov5640_data.pix.width = 640;
++ ov5640_data.pix.height = 480;
++ ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY |
++ V4L2_CAP_TIMEPERFRAME;
++ ov5640_data.streamcap.capturemode = 0;
++ ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
++ ov5640_data.streamcap.timeperframe.numerator = 1;
++
++ ov5640_regulator_enable(&client->dev);
++
++ ov5640_reset();
++
++ ov5640_power_down(0);
++
++ retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high);
++ if (retval < 0 || chip_id_high != 0x56) {
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ pr_warning("camera ov5640 is not found\n");
++ return -ENODEV;
++ }
++ retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low);
++ if (retval < 0 || chip_id_low != 0x40) {
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ pr_warning("camera ov5640 is not found\n");
++ return -ENODEV;
++ }
++
++ retval = init_device();
++ if (retval < 0) {
++ clk_disable_unprepare(ov5640_data.sensor_clk);
++ pr_warning("camera ov5640 init failed\n");
++ ov5640_power_down(1);
++ return retval;
++ }
++
++ ov5640_power_down(1);
++
++ clk_disable(ov5640_data.sensor_clk);
++
++ v4l2_i2c_subdev_init(&ov5640_data.subdev, client, &ov5640_subdev_ops);
++
++ retval = v4l2_async_register_subdev(&ov5640_data.subdev);
++ if (retval < 0)
++ dev_err(&client->dev,
++ "%s--Async register failed, ret=%d\n", __func__, retval);
++
++ pr_info("camera ov5640, is found\n");
++ return retval;
++}
++
++/*!
++ * ov5640 I2C detach function
++ *
++ * @param client struct i2c_client *
++ * @return Error code indicating success or failure
++ */
++static int ov5640_remove(struct i2c_client *client)
++{
++ struct v4l2_subdev *sd = i2c_get_clientdata(client);
++
++ v4l2_async_unregister_subdev(sd);
++
++ clk_unprepare(ov5640_data.sensor_clk);
++
++ if (analog_regulator)
++ regulator_disable(analog_regulator);
++
++ if (core_regulator)
++ regulator_disable(core_regulator);
++
++ if (io_regulator)
++ regulator_disable(io_regulator);
++
++ return 0;
++}
++
++module_i2c_driver(ov5640_i2c_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("OV5640 Camera Driver");
++MODULE_LICENSE("GPL");
++MODULE_VERSION("1.0");
++MODULE_ALIAS("CSI");
+diff -Nur linux-3.14.72.orig/drivers/media/v4l2-core/v4l2-compat-ioctl32.c linux-3.14.72/drivers/media/v4l2-core/v4l2-compat-ioctl32.c
+--- linux-3.14.72.orig/drivers/media/v4l2-core/v4l2-compat-ioctl32.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/v4l2-core/v4l2-compat-ioctl32.c 2016-06-19 22:11:55.189147618 +0200
+@@ -1072,6 +1072,7 @@
+ case VIDIOC_TRY_DECODER_CMD:
+ case VIDIOC_DBG_S_REGISTER:
+ case VIDIOC_DBG_G_REGISTER:
++ case VIDIOC_DBG_G_CHIP_IDENT:
+ case VIDIOC_S_HW_FREQ_SEEK:
+ case VIDIOC_S_DV_TIMINGS:
+ case VIDIOC_G_DV_TIMINGS:
+diff -Nur linux-3.14.72.orig/drivers/media/v4l2-core/v4l2-dev.c linux-3.14.72/drivers/media/v4l2-core/v4l2-dev.c
+--- linux-3.14.72.orig/drivers/media/v4l2-core/v4l2-dev.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/v4l2-core/v4l2-dev.c 2016-06-19 22:11:55.189147618 +0200
+@@ -499,8 +499,8 @@
+ };
+
+ /**
+- * get_index - assign stream index number based on v4l2_dev
+- * @vdev: video_device to assign index number to, vdev->v4l2_dev should be assigned
++ * get_index - assign stream index number based on parent device
++ * @vdev: video_device to assign index number to, vdev->parent should be assigned
+ *
+ * Note that when this is called the new device has not yet been registered
+ * in the video_device array, but it was able to obtain a minor number.
+@@ -518,11 +518,15 @@
+ static DECLARE_BITMAP(used, VIDEO_NUM_DEVICES);
+ int i;
+
++ /* Some drivers do not set the parent. In that case always return 0. */
++ if (vdev->parent == NULL)
++ return 0;
++
+ bitmap_zero(used, VIDEO_NUM_DEVICES);
+
+ for (i = 0; i < VIDEO_NUM_DEVICES; i++) {
+ if (video_device[i] != NULL &&
+- video_device[i]->v4l2_dev == vdev->v4l2_dev) {
++ video_device[i]->parent == vdev->parent) {
+ set_bit(video_device[i]->index, used);
+ }
+ }
+@@ -596,6 +600,7 @@
+ set_bit(_IOC_NR(VIDIOC_DBG_G_REGISTER), valid_ioctls);
+ set_bit(_IOC_NR(VIDIOC_DBG_S_REGISTER), valid_ioctls);
+ #endif
++ SET_VALID_IOCTL(ops, VIDIOC_DBG_G_CHIP_IDENT, vidioc_g_chip_ident);
+ /* yes, really vidioc_subscribe_event */
+ SET_VALID_IOCTL(ops, VIDIOC_DQEVENT, vidioc_subscribe_event);
+ SET_VALID_IOCTL(ops, VIDIOC_SUBSCRIBE_EVENT, vidioc_subscribe_event);
+@@ -775,9 +780,6 @@
+ /* the release callback MUST be present */
+ if (WARN_ON(!vdev->release))
+ return -EINVAL;
+- /* the v4l2_dev pointer MUST be present */
+- if (WARN_ON(!vdev->v4l2_dev))
+- return -EINVAL;
+
+ /* v4l2_fh support */
+ spin_lock_init(&vdev->fh_lock);
+@@ -805,14 +807,16 @@
+
+ vdev->vfl_type = type;
+ vdev->cdev = NULL;
+- if (vdev->dev_parent == NULL)
+- vdev->dev_parent = vdev->v4l2_dev->dev;
+- if (vdev->ctrl_handler == NULL)
+- vdev->ctrl_handler = vdev->v4l2_dev->ctrl_handler;
+- /* If the prio state pointer is NULL, then use the v4l2_device
+- prio state. */
+- if (vdev->prio == NULL)
+- vdev->prio = &vdev->v4l2_dev->prio;
++ if (vdev->v4l2_dev) {
++ if (vdev->v4l2_dev->dev)
++ vdev->parent = vdev->v4l2_dev->dev;
++ if (vdev->ctrl_handler == NULL)
++ vdev->ctrl_handler = vdev->v4l2_dev->ctrl_handler;
++ /* If the prio state pointer is NULL, then use the v4l2_device
++ prio state. */
++ if (vdev->prio == NULL)
++ vdev->prio = &vdev->v4l2_dev->prio;
++ }
+
+ /* Part 2: find a free minor, device node number and device index. */
+ #ifdef CONFIG_VIDEO_FIXED_MINOR_RANGES
+@@ -898,7 +902,8 @@
+ /* Part 4: register the device with sysfs */
+ vdev->dev.class = &video_class;
+ vdev->dev.devt = MKDEV(VIDEO_MAJOR, vdev->minor);
+- vdev->dev.parent = vdev->dev_parent;
++ if (vdev->parent)
++ vdev->dev.parent = vdev->parent;
+ dev_set_name(&vdev->dev, "%s%d", name_base, vdev->num);
+ ret = device_register(&vdev->dev);
+ if (ret < 0) {
+diff -Nur linux-3.14.72.orig/drivers/media/v4l2-core/v4l2-ioctl.c linux-3.14.72/drivers/media/v4l2-core/v4l2-ioctl.c
+--- linux-3.14.72.orig/drivers/media/v4l2-core/v4l2-ioctl.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/v4l2-core/v4l2-ioctl.c 2016-06-19 22:11:55.189147618 +0200
+@@ -26,6 +26,7 @@
+ #include <media/v4l2-fh.h>
+ #include <media/v4l2-event.h>
+ #include <media/v4l2-device.h>
++#include <media/v4l2-chip-ident.h>
+ #include <media/videobuf2-core.h>
+
+ #define CREATE_TRACE_POINTS
+@@ -621,6 +622,20 @@
+ pr_info("pts=%llu\n", p->stop.pts);
+ }
+
++static void v4l_print_dbg_chip_ident(const void *arg, bool write_only)
++{
++ const struct v4l2_dbg_chip_ident *p = arg;
++
++ pr_cont("type=%u, ", p->match.type);
++ if (p->match.type == V4L2_CHIP_MATCH_I2C_DRIVER)
++ pr_cont("name=%.*s, ",
++ (int)sizeof(p->match.name), p->match.name);
++ else
++ pr_cont("addr=%u, ", p->match.addr);
++ pr_cont("chip_ident=%u, revision=0x%x\n",
++ p->ident, p->revision);
++}
++
+ static void v4l_print_dbg_chip_info(const void *arg, bool write_only)
+ {
+ const struct v4l2_dbg_chip_info *p = arg;
+@@ -1801,6 +1816,18 @@
+ #endif
+ }
+
++static int v4l_dbg_g_chip_ident(const struct v4l2_ioctl_ops *ops,
++ struct file *file, void *fh, void *arg)
++{
++ struct v4l2_dbg_chip_ident *p = arg;
++
++ p->ident = V4L2_IDENT_NONE;
++ p->revision = 0;
++ if (p->match.type == V4L2_CHIP_MATCH_SUBDEV)
++ return -EINVAL;
++ return ops->vidioc_g_chip_ident(file, fh, p);
++}
++
+ static int v4l_dbg_g_chip_info(const struct v4l2_ioctl_ops *ops,
+ struct file *file, void *fh, void *arg)
+ {
+@@ -1816,7 +1843,12 @@
+ p->flags |= V4L2_CHIP_FL_WRITABLE;
+ if (ops->vidioc_g_register)
+ p->flags |= V4L2_CHIP_FL_READABLE;
+- strlcpy(p->name, vfd->v4l2_dev->name, sizeof(p->name));
++ if (vfd->v4l2_dev)
++ strlcpy(p->name, vfd->v4l2_dev->name, sizeof(p->name));
++ else if (vfd->parent)
++ strlcpy(p->name, vfd->parent->driver->name, sizeof(p->name));
++ else
++ strlcpy(p->name, "bridge", sizeof(p->name));
+ if (ops->vidioc_g_chip_info)
+ return ops->vidioc_g_chip_info(file, fh, arg);
+ if (p->match.addr)
+@@ -2045,6 +2077,7 @@
+ IOCTL_INFO_STD(VIDIOC_TRY_DECODER_CMD, vidioc_try_decoder_cmd, v4l_print_decoder_cmd, 0),
+ IOCTL_INFO_FNC(VIDIOC_DBG_S_REGISTER, v4l_dbg_s_register, v4l_print_dbg_register, 0),
+ IOCTL_INFO_FNC(VIDIOC_DBG_G_REGISTER, v4l_dbg_g_register, v4l_print_dbg_register, 0),
++ IOCTL_INFO_FNC(VIDIOC_DBG_G_CHIP_IDENT, v4l_dbg_g_chip_ident, v4l_print_dbg_chip_ident, 0),
+ IOCTL_INFO_FNC(VIDIOC_S_HW_FREQ_SEEK, v4l_s_hw_freq_seek, v4l_print_hw_freq_seek, INFO_FL_PRIO),
+ IOCTL_INFO_STD(VIDIOC_S_DV_TIMINGS, vidioc_s_dv_timings, v4l_print_dv_timings, INFO_FL_PRIO),
+ IOCTL_INFO_STD(VIDIOC_G_DV_TIMINGS, vidioc_g_dv_timings, v4l_print_dv_timings, 0),
+diff -Nur linux-3.14.72.orig/drivers/media/v4l2-core/videobuf-dma-contig.c linux-3.14.72/drivers/media/v4l2-core/videobuf-dma-contig.c
+--- linux-3.14.72.orig/drivers/media/v4l2-core/videobuf-dma-contig.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/media/v4l2-core/videobuf-dma-contig.c 2016-06-19 22:11:55.189147618 +0200
+@@ -305,7 +305,16 @@
+ /* Try to remap memory */
+ size = vma->vm_end - vma->vm_start;
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+- retval = vm_iomap_memory(vma, vma->vm_start, size);
++
++ /* the "vm_pgoff" is just used in v4l2 to find the
++ * corresponding buffer data structure which is allocated
++ * earlier and it does not mean the offset from the physical
++ * buffer start address as usual. So set it to 0 to pass
++ * the sanity check in vm_iomap_memory().
++ */
++ vma->vm_pgoff = 0;
++
++ retval = vm_iomap_memory(vma, mem->dma_handle, size);
+ if (retval) {
+ dev_err(q->dev, "mmap: remap failed with error %d. ",
+ retval);
+diff -Nur linux-3.14.72.orig/drivers/mfd/Kconfig linux-3.14.72/drivers/mfd/Kconfig
+--- linux-3.14.72.orig/drivers/mfd/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mfd/Kconfig 2016-06-19 22:11:55.189147618 +0200
+@@ -163,6 +163,21 @@
+ Additional drivers must be enabled in order to use the functionality
+ of the device.
+
++config MFD_MXC_HDMI
++ tristate "Freescale HDMI Core"
++ select MFD_CORE
++ help
++ This is the core driver for the Freescale i.MX6 on-chip HDMI.
++ This MFD driver connects with the video and audio drivers for HDMI.
++
++config MFD_MXC_HDMI_ANDROID
++ tristate "Freescale HDMI Core for Android"
++ select MFD_CORE
++ depends on MFD_MXC_HDMI=y
++ help
++ This is the core driver for the Freescale i.MX6 on-chip HDMI.
++ This MFD driver connects with the video and audio drivers for HDMI.
++
+ config MFD_MC13XXX
+ tristate
+ depends on (SPI_MASTER || I2C)
+@@ -317,6 +332,13 @@
+ select individual components like voltage regulators, RTC and
+ battery-charger under the corresponding menus.
+
++config MFD_MAX17135
++ tristate "Maxim MAX17135 EPD PMIC core"
++ depends on I2C
++ help
++ This is the MAX17135 PMIC support. It includes
++ core support for communication with the MAX17135 chip.
++
+ config MFD_MAX14577
+ bool "Maxim Semiconductor MAX14577 MUIC + Charger Support"
+ depends on I2C=y
+@@ -1193,6 +1215,14 @@
+ in various ST Microelectronics and ST-Ericsson embedded
+ Nomadik series.
+
++config MFD_TDA1997X
++ tristate "TDA1997X HDMI Receiver Core"
++ select MFD_CORE
++ depends on I2C=y
++ help
++ This is the core driver for the TDA1997X HDMI Reciver. This MFD
++ driver connects with video and audio drivers for HDMI Input.
++
+ endmenu
+ endif
+
+diff -Nur linux-3.14.72.orig/drivers/mfd/Makefile linux-3.14.72/drivers/mfd/Makefile
+--- linux-3.14.72.orig/drivers/mfd/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mfd/Makefile 2016-06-19 22:11:55.193147356 +0200
+@@ -112,6 +112,7 @@
+ obj-$(CONFIG_MFD_DA9063) += da9063.o
+
+ obj-$(CONFIG_MFD_MAX14577) += max14577.o
++obj-$(CONFIG_MFD_MAX17135) += max17135-core.o
+ obj-$(CONFIG_MFD_MAX77686) += max77686.o max77686-irq.o
+ obj-$(CONFIG_MFD_MAX77693) += max77693.o max77693-irq.o
+ obj-$(CONFIG_MFD_MAX8907) += max8907.o
+@@ -166,3 +167,5 @@
+ obj-$(CONFIG_MFD_AS3711) += as3711.o
+ obj-$(CONFIG_MFD_AS3722) += as3722.o
+ obj-$(CONFIG_MFD_STW481X) += stw481x.o
++obj-$(CONFIG_MFD_MXC_HDMI) += mxc-hdmi-core.o
++obj-$(CONFIG_MFD_TDA1997X) += tda1997x-core.o
+diff -Nur linux-3.14.72.orig/drivers/mfd/max17135-core.c linux-3.14.72/drivers/mfd/max17135-core.c
+--- linux-3.14.72.orig/drivers/mfd/max17135-core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mfd/max17135-core.c 2016-06-19 22:11:55.193147356 +0200
+@@ -0,0 +1,295 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++/*!
++ * @file pmic/core/max17135.c
++ * @brief This file contains MAX17135 specific PMIC code. This implementaion
++ * may differ for each PMIC chip.
++ *
++ * @ingroup PMIC_CORE
++ */
++
++/*
++ * Includes
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/uaccess.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <linux/pmic_status.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/max17135.h>
++#include <asm/mach-types.h>
++
++static int max17135_detect(struct i2c_client *client,
++ struct i2c_board_info *info);
++struct i2c_client *max17135_client;
++static struct regulator *gpio_regulator;
++
++static struct mfd_cell max17135_devs[] = {
++ { .name = "max17135-pmic", },
++ { .name = "max17135-sns", },
++};
++
++static const unsigned short normal_i2c[] = {0x48, I2C_CLIENT_END};
++
++int max17135_reg_read(int reg_num, unsigned int *reg_val)
++{
++ int result;
++
++ if (max17135_client == NULL)
++ return PMIC_ERROR;
++
++ if ((reg_num == REG_MAX17135_EXT_TEMP) ||
++ (reg_num == REG_MAX17135_INT_TEMP)) {
++ result = i2c_smbus_read_word_data(max17135_client, reg_num);
++ if (result < 0) {
++ dev_err(&max17135_client->dev,
++ "Unable to read MAX17135 register via I2C\n");
++ return PMIC_ERROR;
++ }
++ /* Swap bytes for dword read */
++ result = (result >> 8) | ((result & 0xFF) << 8);
++ } else {
++ result = i2c_smbus_read_byte_data(max17135_client, reg_num);
++ if (result < 0) {
++ dev_err(&max17135_client->dev,
++ "Unable to read MAX17135 register via I2C\n");
++ return PMIC_ERROR;
++ }
++ }
++
++ *reg_val = result;
++ return PMIC_SUCCESS;
++}
++
++int max17135_reg_write(int reg_num, const unsigned int reg_val)
++{
++ int result;
++
++ if (max17135_client == NULL)
++ return PMIC_ERROR;
++
++ result = i2c_smbus_write_byte_data(max17135_client, reg_num, reg_val);
++ if (result < 0) {
++ dev_err(&max17135_client->dev,
++ "Unable to write MAX17135 register via I2C\n");
++ return PMIC_ERROR;
++ }
++
++ return PMIC_SUCCESS;
++}
++
++#ifdef CONFIG_OF
++static struct max17135_platform_data *max17135_i2c_parse_dt_pdata(
++ struct device *dev)
++{
++ struct max17135_platform_data *pdata;
++
++ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
++ if (!pdata) {
++ dev_err(dev, "could not allocate memory for pdata\n");
++ return ERR_PTR(-ENOMEM);
++ }
++
++ return pdata;
++}
++#else
++static struct max17135_platform_data *max17135_i2c_parse_dt_pdata(
++ struct device *dev)
++{
++ return NULL;
++}
++#endif /* !CONFIG_OF */
++
++static int max17135_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct max17135 *max17135;
++ struct max17135_platform_data *pdata = client->dev.platform_data;
++ struct device_node *np = client->dev.of_node;
++ int ret = 0;
++
++ if (!np)
++ return -ENODEV;
++
++ gpio_regulator = devm_regulator_get(&client->dev, "SENSOR");
++ if (!IS_ERR(gpio_regulator)) {
++ ret = regulator_enable(gpio_regulator);
++ if (ret) {
++ dev_err(&client->dev, "gpio set voltage error\n");
++ return ret;
++ }
++ }
++
++ /* Create the PMIC data structure */
++ max17135 = kzalloc(sizeof(struct max17135), GFP_KERNEL);
++ if (max17135 == NULL) {
++ kfree(client);
++ return -ENOMEM;
++ }
++
++ /* Initialize the PMIC data structure */
++ i2c_set_clientdata(client, max17135);
++ max17135->dev = &client->dev;
++ max17135->i2c_client = client;
++
++ max17135_client = client;
++ ret = max17135_detect(client, NULL);
++ if (ret)
++ goto err1;
++
++ mfd_add_devices(max17135->dev, -1, max17135_devs,
++ ARRAY_SIZE(max17135_devs),
++ NULL, 0, NULL);
++
++ if (max17135->dev->of_node) {
++ pdata = max17135_i2c_parse_dt_pdata(max17135->dev);
++ if (IS_ERR(pdata)) {
++ ret = PTR_ERR(pdata);
++ goto err2;
++ }
++
++ }
++ max17135->pdata = pdata;
++
++ dev_info(&client->dev, "PMIC MAX17135 for eInk display\n");
++
++ return ret;
++err2:
++ mfd_remove_devices(max17135->dev);
++err1:
++ kfree(max17135);
++
++ return ret;
++}
++
++
++static int max17135_remove(struct i2c_client *i2c)
++{
++ struct max17135 *max17135 = i2c_get_clientdata(i2c);
++
++ mfd_remove_devices(max17135->dev);
++ return 0;
++}
++
++static int max17135_suspend(struct i2c_client *client, pm_message_t state)
++{
++ return 0;
++}
++
++static int max17135_resume(struct i2c_client *client)
++{
++ return 0;
++}
++
++/* Return 0 if detection is successful, -ENODEV otherwise */
++static int max17135_detect(struct i2c_client *client,
++ struct i2c_board_info *info)
++{
++ struct i2c_adapter *adapter = client->adapter;
++ u8 chip_rev, chip_id;
++
++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
++ return -ENODEV;
++
++ /* detection */
++ if (i2c_smbus_read_byte_data(client,
++ REG_MAX17135_PRODUCT_REV) != 0) {
++ dev_err(&adapter->dev,
++ "Max17135 PMIC not found!\n");
++ return -ENODEV;
++ }
++
++ /* identification */
++ chip_rev = i2c_smbus_read_byte_data(client,
++ REG_MAX17135_PRODUCT_REV);
++ chip_id = i2c_smbus_read_byte_data(client,
++ REG_MAX17135_PRODUCT_ID);
++
++ if (chip_rev != 0x00 || chip_id != 0x4D) { /* identification failed */
++ dev_info(&adapter->dev,
++ "Unsupported chip (man_id=0x%02X, "
++ "chip_id=0x%02X).\n", chip_rev, chip_id);
++ return -ENODEV;
++ }
++
++ if (info)
++ strlcpy(info->type, "max17135_sensor", I2C_NAME_SIZE);
++
++ return 0;
++}
++
++static const struct i2c_device_id max17135_id[] = {
++ { "max17135", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, max17135_id);
++
++static const struct of_device_id max17135_dt_ids[] = {
++ {
++ .compatible = "maxim,max17135",
++ .data = (void *) &max17135_id[0],
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(of, max17135_dt_ids);
++
++
++static struct i2c_driver max17135_driver = {
++ .driver = {
++ .name = "max17135",
++ .owner = THIS_MODULE,
++ .of_match_table = max17135_dt_ids,
++ },
++ .probe = max17135_probe,
++ .remove = max17135_remove,
++ .suspend = max17135_suspend,
++ .resume = max17135_resume,
++ .id_table = max17135_id,
++ .detect = max17135_detect,
++ .address_list = &normal_i2c[0],
++};
++
++static int __init max17135_init(void)
++{
++ return i2c_add_driver(&max17135_driver);
++}
++
++static void __exit max17135_exit(void)
++{
++ i2c_del_driver(&max17135_driver);
++}
++
++/*
++ * Module entry points
++ */
++subsys_initcall(max17135_init);
++module_exit(max17135_exit);
+diff -Nur linux-3.14.72.orig/drivers/mfd/mxc-hdmi-core.c linux-3.14.72/drivers/mfd/mxc-hdmi-core.c
+--- linux-3.14.72.orig/drivers/mfd/mxc-hdmi-core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mfd/mxc-hdmi-core.c 2016-06-19 22:11:55.193147356 +0200
+@@ -0,0 +1,792 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/spinlock.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/gcd.h>
++
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <asm/mach-types.h>
++
++#include <video/mxc_hdmi.h>
++#include <linux/ipu-v3.h>
++#include <video/mxc_edid.h>
++#include "../mxc/ipu3/ipu_prv.h"
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/of_device.h>
++#include <linux/mod_devicetable.h>
++
++struct mxc_hdmi_data {
++ struct platform_device *pdev;
++ unsigned long __iomem *reg_base;
++ unsigned long reg_phys_base;
++ struct device *dev;
++};
++
++struct mxc_hdmi_ctsn_t {
++ int freq;
++ int n;
++ int cts;
++};
++
++struct mxc_hdmi_ctsn {
++ int pixclk;
++ struct mxc_hdmi_ctsn_t ctsn[3];
++};
++
++static void __iomem *hdmi_base;
++static struct clk *isfr_clk;
++static struct clk *iahb_clk;
++static struct clk *mipi_core_clk;
++static spinlock_t irq_spinlock;
++static spinlock_t edid_spinlock;
++static unsigned int sample_rate;
++static unsigned long pixel_clk_rate;
++static struct clk *pixel_clk;
++static int hdmi_ratio;
++int mxc_hdmi_ipu_id;
++int mxc_hdmi_disp_id;
++static int hdmi_core_edid_status;
++static struct mxc_edid_cfg hdmi_core_edid_cfg;
++static int hdmi_core_init;
++static unsigned int hdmi_dma_running;
++static struct snd_pcm_substream *hdmi_audio_stream_playback;
++static unsigned int hdmi_cable_state;
++static unsigned int hdmi_blank_state;
++static unsigned int hdmi_abort_state;
++static spinlock_t hdmi_audio_lock, hdmi_blank_state_lock, hdmi_cable_state_lock;
++
++void hdmi_set_dvi_mode(unsigned int state)
++{
++ if (state) {
++ mxc_hdmi_abort_stream();
++ hdmi_cec_stop_device();
++ } else {
++ hdmi_cec_start_device();
++ }
++}
++EXPORT_SYMBOL(hdmi_set_dvi_mode);
++
++unsigned int hdmi_set_cable_state(unsigned int state)
++{
++ unsigned long flags;
++ struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags);
++ hdmi_cable_state = state;
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
++
++#ifndef CONFIG_MFD_MXC_HDMI_ANDROID
++ if (check_hdmi_state() && substream && hdmi_abort_state) {
++ hdmi_abort_state = 0;
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_PAUSE_RELEASE);
++ }
++#endif
++ return 0;
++}
++EXPORT_SYMBOL(hdmi_set_cable_state);
++
++unsigned int hdmi_set_blank_state(unsigned int state)
++{
++ unsigned long flags;
++ struct snd_pcm_substream *substream = hdmi_audio_stream_playback;
++
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags);
++ hdmi_blank_state = state;
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
++
++#ifndef CONFIG_MFD_MXC_HDMI_ANDROID
++ if (check_hdmi_state() && substream && hdmi_abort_state) {
++ hdmi_abort_state = 0;
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_PAUSE_RELEASE);
++ }
++#endif
++
++ return 0;
++}
++EXPORT_SYMBOL(hdmi_set_blank_state);
++
++static void hdmi_audio_abort_stream(struct snd_pcm_substream *substream)
++{
++ unsigned long flags;
++
++ snd_pcm_stream_lock_irqsave(substream, flags);
++
++#ifndef CONFIG_MFD_MXC_HDMI_ANDROID
++ if (snd_pcm_running(substream)) {
++ hdmi_abort_state = 1;
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_PAUSE_PUSH);
++ }
++#else
++ if (snd_pcm_running(substream))
++ snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
++#endif
++
++ snd_pcm_stream_unlock_irqrestore(substream, flags);
++}
++
++int mxc_hdmi_abort_stream(void)
++{
++ unsigned long flags;
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ if (hdmi_audio_stream_playback)
++ hdmi_audio_abort_stream(hdmi_audio_stream_playback);
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_hdmi_abort_stream);
++
++int check_hdmi_state(void)
++{
++ unsigned long flags1, flags2;
++ unsigned int ret;
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags1);
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags2);
++
++ ret = hdmi_cable_state && hdmi_blank_state;
++
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags2);
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags1);
++
++ return ret;
++}
++EXPORT_SYMBOL(check_hdmi_state);
++
++int mxc_hdmi_register_audio(struct snd_pcm_substream *substream)
++{
++ unsigned long flags, flags1;
++ int ret = 0;
++
++ snd_pcm_stream_lock_irqsave(substream, flags);
++
++ if (substream && check_hdmi_state()) {
++ spin_lock_irqsave(&hdmi_audio_lock, flags1);
++ if (hdmi_audio_stream_playback) {
++ pr_err("%s unconsist hdmi auido stream!\n", __func__);
++ ret = -EINVAL;
++ }
++ hdmi_audio_stream_playback = substream;
++ hdmi_abort_state = 0;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags1);
++ } else
++ ret = -EINVAL;
++
++ snd_pcm_stream_unlock_irqrestore(substream, flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(mxc_hdmi_register_audio);
++
++void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ hdmi_audio_stream_playback = NULL;
++ hdmi_abort_state = 0;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++}
++EXPORT_SYMBOL(mxc_hdmi_unregister_audio);
++
++u8 hdmi_readb(unsigned int reg)
++{
++ u8 value;
++
++ value = __raw_readb(hdmi_base + reg);
++
++ return value;
++}
++EXPORT_SYMBOL(hdmi_readb);
++
++#ifdef DEBUG
++static bool overflow_lo;
++static bool overflow_hi;
++
++bool hdmi_check_overflow(void)
++{
++ u8 val, lo, hi;
++
++ val = hdmi_readb(HDMI_IH_FC_STAT2);
++ lo = (val & HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW) != 0;
++ hi = (val & HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW) != 0;
++
++ if ((lo != overflow_lo) || (hi != overflow_hi)) {
++ pr_debug("%s LowPriority=%d HighPriority=%d <=======================\n",
++ __func__, lo, hi);
++ overflow_lo = lo;
++ overflow_hi = hi;
++ return true;
++ }
++ return false;
++}
++#else
++bool hdmi_check_overflow(void)
++{
++ return false;
++}
++#endif
++EXPORT_SYMBOL(hdmi_check_overflow);
++
++void hdmi_writeb(u8 value, unsigned int reg)
++{
++ hdmi_check_overflow();
++ __raw_writeb(value, hdmi_base + reg);
++ hdmi_check_overflow();
++}
++EXPORT_SYMBOL(hdmi_writeb);
++
++void hdmi_mask_writeb(u8 data, unsigned int reg, u8 shift, u8 mask)
++{
++ u8 value = hdmi_readb(reg) & ~mask;
++ value |= (data << shift) & mask;
++ hdmi_writeb(value, reg);
++}
++EXPORT_SYMBOL(hdmi_mask_writeb);
++
++unsigned int hdmi_read4(unsigned int reg)
++{
++ /* read a four byte address from registers */
++ return (hdmi_readb(reg + 3) << 24) |
++ (hdmi_readb(reg + 2) << 16) |
++ (hdmi_readb(reg + 1) << 8) |
++ hdmi_readb(reg);
++}
++EXPORT_SYMBOL(hdmi_read4);
++
++void hdmi_write4(unsigned int value, unsigned int reg)
++{
++ /* write a four byte address to hdmi regs */
++ hdmi_writeb(value & 0xff, reg);
++ hdmi_writeb((value >> 8) & 0xff, reg + 1);
++ hdmi_writeb((value >> 16) & 0xff, reg + 2);
++ hdmi_writeb((value >> 24) & 0xff, reg + 3);
++}
++EXPORT_SYMBOL(hdmi_write4);
++
++static void initialize_hdmi_ih_mutes(void)
++{
++ u8 ih_mute;
++
++ /*
++ * Boot up defaults are:
++ * HDMI_IH_MUTE = 0x03 (disabled)
++ * HDMI_IH_MUTE_* = 0x00 (enabled)
++ */
++
++ /* Disable top level interrupt bits in HDMI block */
++ ih_mute = hdmi_readb(HDMI_IH_MUTE) |
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
++
++ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
++
++ /* by default mask all interrupts */
++ hdmi_writeb(0xff, HDMI_VP_MASK);
++ hdmi_writeb(0xff, HDMI_FC_MASK0);
++ hdmi_writeb(0xff, HDMI_FC_MASK1);
++ hdmi_writeb(0xff, HDMI_FC_MASK2);
++ hdmi_writeb(0xff, HDMI_PHY_MASK0);
++ hdmi_writeb(0xff, HDMI_PHY_I2CM_INT_ADDR);
++ hdmi_writeb(0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
++ hdmi_writeb(0xff, HDMI_AUD_INT);
++ hdmi_writeb(0xff, HDMI_AUD_SPDIFINT);
++ hdmi_writeb(0xff, HDMI_AUD_HBR_MASK);
++ hdmi_writeb(0xff, HDMI_GP_MASK);
++ hdmi_writeb(0xff, HDMI_A_APIINTMSK);
++ hdmi_writeb(0xff, HDMI_CEC_MASK);
++ hdmi_writeb(0xff, HDMI_I2CM_INT);
++ hdmi_writeb(0xff, HDMI_I2CM_CTLINT);
++
++ /* Disable interrupts in the IH_MUTE_* registers */
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT1);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_FC_STAT2);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AS_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_PHY_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CM_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_VP_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++
++ /* Enable top level interrupt bits in HDMI block */
++ ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
++ hdmi_writeb(ih_mute, HDMI_IH_MUTE);
++}
++
++static void hdmi_set_clock_regenerator_n(unsigned int value)
++{
++ u8 val;
++
++ if (!hdmi_dma_running) {
++ hdmi_writeb(value & 0xff, HDMI_AUD_N1);
++ hdmi_writeb(0, HDMI_AUD_N2);
++ hdmi_writeb(0, HDMI_AUD_N3);
++ }
++
++ hdmi_writeb(value & 0xff, HDMI_AUD_N1);
++ hdmi_writeb((value >> 8) & 0xff, HDMI_AUD_N2);
++ hdmi_writeb((value >> 16) & 0x0f, HDMI_AUD_N3);
++
++ /* nshift factor = 0 */
++ val = hdmi_readb(HDMI_AUD_CTS3);
++ val &= ~HDMI_AUD_CTS3_N_SHIFT_MASK;
++ hdmi_writeb(val, HDMI_AUD_CTS3);
++}
++
++static void hdmi_set_clock_regenerator_cts(unsigned int cts)
++{
++ u8 val;
++
++ if (!hdmi_dma_running) {
++ hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
++ hdmi_writeb(0, HDMI_AUD_CTS2);
++ hdmi_writeb(0, HDMI_AUD_CTS3);
++ }
++
++ /* Must be set/cleared first */
++ val = hdmi_readb(HDMI_AUD_CTS3);
++ val &= ~HDMI_AUD_CTS3_CTS_MANUAL;
++ hdmi_writeb(val, HDMI_AUD_CTS3);
++
++ hdmi_writeb(cts & 0xff, HDMI_AUD_CTS1);
++ hdmi_writeb((cts >> 8) & 0xff, HDMI_AUD_CTS2);
++ hdmi_writeb(((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
++ HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
++}
++
++static const struct mxc_hdmi_ctsn mxc_hdmi_ctsn_tbl[] = {
++ /* 32kHz 44.1kHz 48kHz */
++ /* Clock N CTS N CTS N CTS */
++ { 25175, { { 32000, 4096, 25175 }, { 44100, 28224, 125875 }, { 48000, 6144, 25175 } } }, /* 25,20/1.001 MHz */
++ { 25200, { { 32000, 4096, 25200 }, { 44100, 6272, 28000 }, { 48000, 6144, 25200 } } }, /* 25.20 MHz */
++ { 27000, { { 32000, 4096, 27000 }, { 44100, 6272, 30000 }, { 48000, 6144, 27000 } } }, /* 27.00 MHz */
++ { 27027, { { 32000, 4096, 27027 }, { 44100, 6272, 30030 }, { 48000, 6144, 27027 } } }, /* 27.00*1.001 MHz */
++ { 54000, { { 32000, 4096, 54000 }, { 44100, 6272, 60000 }, { 48000, 6144, 54000 } } }, /* 54.00 MHz */
++ { 54054, { { 32000, 4096, 54054 }, { 44100, 6272, 60060 }, { 48000, 6144, 54054 } } }, /* 54.00*1.001 MHz */
++ { 74176, { { 32000, 4096, 74176 }, { 44100, 5733, 75335 }, { 48000, 6144, 74176 } } }, /* 74.25/1.001 MHz */
++ { 74250, { { 32000, 4096, 74250 }, { 44100, 6272, 82500 }, { 48000, 6144, 74250 } } }, /* 74.25 MHz */
++ {148352, { { 32000, 4096, 148352 }, { 44100, 5733, 150670 }, { 48000, 6144, 148352 } } }, /* 148.50/1.001 MHz */
++ {148500, { { 32000, 4096, 148500 }, { 44100, 6272, 165000 }, { 48000, 6144, 148500 } } }, /* 148.50 MHz */
++};
++
++static bool hdmi_compute_cts_n(unsigned int freq, unsigned long pixel_clk,
++ unsigned int *N, unsigned int *CTS)
++{
++ int n, cts;
++ unsigned long div, mul;
++
++ /* Safe, but overly large values */
++ n = 128 * freq;
++ cts = pixel_clk;
++
++ /* Smallest valid fraction */
++ div = gcd(n, cts);
++
++ n /= div;
++ cts /= div;
++
++ /*
++ * The optimal N is 128*freq/1000. Calculate the closest larger
++ * value that doesn't truncate any bits.
++ */
++ mul = ((128*freq/1000) + (n-1))/n;
++
++ n *= mul;
++ cts *= mul;
++
++ /* Check that we are in spec (not always possible) */
++ if (n < (128*freq/1500)) {
++ pr_warn("%s: calculated ACR N value is too small. Audio will be disabled.\n", __func__);
++ return false;
++ }
++ if (n > (128*freq/300)) {
++ pr_warn("%s: calculated ACR N value is too large. Audio will be disabled.\n", __func__);
++ return false;
++ }
++
++ *N = n;
++ *CTS = cts;
++ return true;
++}
++
++static void hdmi_lookup_cts_n(unsigned int freq, unsigned long pixel_clk,
++ unsigned int *n, unsigned int *cts)
++{
++ unsigned int clk = pixel_clk / 1000;
++ unsigned int frq = freq;
++ int i, j;
++
++ *n = 1;
++ switch (frq) {
++ case 88200:
++ frq = 44100;
++ *n = 2;
++ break;
++ case 96000:
++ frq = 48000;
++ *n = 2;
++ break;
++ case 176400:
++ frq = 44100;
++ *n = 4;
++ break;
++ case 192000:
++ frq = 48000;
++ *n = 4;
++ break;
++ default:
++ break;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(mxc_hdmi_ctsn_tbl); i++) {
++ if (mxc_hdmi_ctsn_tbl[i].pixclk == clk) {
++ for (j = 0; j < 3; j++) {
++ if (mxc_hdmi_ctsn_tbl[i].ctsn[j].freq == frq) {
++ *n *= mxc_hdmi_ctsn_tbl[i].ctsn[j].n;
++ *cts = mxc_hdmi_ctsn_tbl[i].ctsn[j].cts;
++ return;
++ }
++ }
++ }
++ }
++}
++
++static void hdmi_set_clk_regenerator(void)
++{
++ unsigned int clk_n, clk_cts = 0;
++
++ hdmi_lookup_cts_n(sample_rate, pixel_clk_rate, &clk_n, &clk_cts);
++
++ if (clk_cts == 0 && hdmi_compute_cts_n(sample_rate, pixel_clk_rate, &clk_n, &clk_cts))
++ pr_debug("%s: pixel clock not supported - using fallback calculation.\n", __func__);
++ else if (clk_cts == 0) {
++ mxc_hdmi_abort_stream();
++ return;
++ }
++
++ if (hdmi_ratio != 100)
++ clk_cts = (clk_cts * hdmi_ratio) / 100;
++
++ pr_debug("%s: samplerate=%d ratio=%d pixelclk=%d N=%d cts=%d\n",
++ __func__, sample_rate, hdmi_ratio, (int)pixel_clk_rate,
++ clk_n, clk_cts);
++
++ hdmi_set_clock_regenerator_cts(clk_cts);
++ hdmi_set_clock_regenerator_n(clk_n);
++}
++
++static int hdmi_core_get_of_property(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ int ipu_id, disp_id;
++
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++
++ mxc_hdmi_ipu_id = ipu_id;
++ mxc_hdmi_disp_id = disp_id;
++
++ return err;
++}
++
++/* Need to run this before phy is enabled the first time to prevent
++ * overflow condition in HDMI_IH_FC_STAT2 */
++void hdmi_init_clk_regenerator(void)
++{
++ if (pixel_clk_rate == 0) {
++ pixel_clk_rate = 74250000;
++ hdmi_set_clk_regenerator();
++ }
++}
++EXPORT_SYMBOL(hdmi_init_clk_regenerator);
++
++void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock, u32 vmode)
++{
++
++ /* Translate pixel clock in ps (pico seconds) to Hz */
++ pixel_clk_rate = mxcPICOS2KHZ(pixclock, vmode) * 1000UL;
++ hdmi_set_clk_regenerator();
++}
++EXPORT_SYMBOL(hdmi_clk_regenerator_update_pixel_clock);
++
++void hdmi_set_dma_mode(unsigned int dma_running)
++{
++ hdmi_dma_running = dma_running;
++ hdmi_set_clk_regenerator();
++}
++EXPORT_SYMBOL(hdmi_set_dma_mode);
++
++void hdmi_set_sample_rate(unsigned int rate)
++{
++ sample_rate = rate;
++}
++EXPORT_SYMBOL(hdmi_set_sample_rate);
++
++void hdmi_set_edid_cfg(int edid_status, struct mxc_edid_cfg *cfg)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&edid_spinlock, flags);
++ hdmi_core_edid_status = edid_status;
++ memcpy(&hdmi_core_edid_cfg, cfg, sizeof(struct mxc_edid_cfg));
++ spin_unlock_irqrestore(&edid_spinlock, flags);
++}
++EXPORT_SYMBOL(hdmi_set_edid_cfg);
++
++int hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&edid_spinlock, flags);
++ memcpy(cfg, &hdmi_core_edid_cfg, sizeof(struct mxc_edid_cfg));
++ spin_unlock_irqrestore(&edid_spinlock, flags);
++
++ return hdmi_core_edid_status;
++}
++EXPORT_SYMBOL(hdmi_get_edid_cfg);
++
++void hdmi_set_registered(int registered)
++{
++ hdmi_core_init = registered;
++}
++EXPORT_SYMBOL(hdmi_set_registered);
++
++int hdmi_get_registered(void)
++{
++ return hdmi_core_init;
++}
++EXPORT_SYMBOL(hdmi_get_registered);
++
++static int mxc_hdmi_core_probe(struct platform_device *pdev)
++{
++ struct mxc_hdmi_data *hdmi_data;
++ struct resource *res;
++ unsigned long flags;
++ int ret = 0;
++
++#ifdef DEBUG
++ overflow_lo = false;
++ overflow_hi = false;
++#endif
++
++ hdmi_core_init = 0;
++ hdmi_dma_running = 0;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENOENT;
++
++ ret = hdmi_core_get_of_property(pdev);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get hdmi of property fail\n");
++ return -ENOENT;
++ }
++
++ hdmi_data = devm_kzalloc(&pdev->dev, sizeof(struct mxc_hdmi_data), GFP_KERNEL);
++ if (!hdmi_data) {
++ dev_err(&pdev->dev, "Couldn't allocate mxc hdmi mfd device\n");
++ return -ENOMEM;
++ }
++ hdmi_data->pdev = pdev;
++
++ pixel_clk = NULL;
++ sample_rate = 48000;
++ pixel_clk_rate = 0;
++ hdmi_ratio = 100;
++
++ spin_lock_init(&irq_spinlock);
++ spin_lock_init(&edid_spinlock);
++
++
++ spin_lock_init(&hdmi_cable_state_lock);
++ spin_lock_init(&hdmi_blank_state_lock);
++ spin_lock_init(&hdmi_audio_lock);
++
++ spin_lock_irqsave(&hdmi_cable_state_lock, flags);
++ hdmi_cable_state = 0;
++ spin_unlock_irqrestore(&hdmi_cable_state_lock, flags);
++
++ spin_lock_irqsave(&hdmi_blank_state_lock, flags);
++ hdmi_blank_state = 0;
++ spin_unlock_irqrestore(&hdmi_blank_state_lock, flags);
++
++ spin_lock_irqsave(&hdmi_audio_lock, flags);
++ hdmi_audio_stream_playback = NULL;
++ hdmi_abort_state = 0;
++ spin_unlock_irqrestore(&hdmi_audio_lock, flags);
++
++ mipi_core_clk = clk_get(&hdmi_data->pdev->dev, "mipi_core");
++ if (IS_ERR(mipi_core_clk)) {
++ ret = PTR_ERR(mipi_core_clk);
++ dev_err(&hdmi_data->pdev->dev,
++ "Unable to get mipi core clk: %d\n", ret);
++ goto eclkg;
++ }
++
++ ret = clk_prepare_enable(mipi_core_clk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot enable mipi core clock: %d\n", ret);
++ goto eclke;
++ }
++
++ isfr_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_isfr");
++ if (IS_ERR(isfr_clk)) {
++ ret = PTR_ERR(isfr_clk);
++ dev_err(&hdmi_data->pdev->dev,
++ "Unable to get HDMI isfr clk: %d\n", ret);
++ goto eclkg1;
++ }
++
++ ret = clk_prepare_enable(isfr_clk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
++ goto eclke1;
++ }
++
++ pr_debug("%s isfr_clk:%d\n", __func__,
++ (int)clk_get_rate(isfr_clk));
++
++ iahb_clk = clk_get(&hdmi_data->pdev->dev, "hdmi_iahb");
++ if (IS_ERR(iahb_clk)) {
++ ret = PTR_ERR(iahb_clk);
++ dev_err(&hdmi_data->pdev->dev,
++ "Unable to get HDMI iahb clk: %d\n", ret);
++ goto eclkg2;
++ }
++
++ ret = clk_prepare_enable(iahb_clk);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot enable HDMI clock: %d\n", ret);
++ goto eclke2;
++ }
++
++ hdmi_data->reg_phys_base = res->start;
++ if (!request_mem_region(res->start, resource_size(res),
++ dev_name(&pdev->dev))) {
++ dev_err(&pdev->dev, "request_mem_region failed\n");
++ ret = -EBUSY;
++ goto emem;
++ }
++
++ hdmi_data->reg_base = ioremap(res->start, resource_size(res));
++ if (!hdmi_data->reg_base) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto eirq;
++ }
++ hdmi_base = hdmi_data->reg_base;
++
++ pr_debug("\n%s hdmi hw base = 0x%08x\n\n", __func__, (int)res->start);
++
++ initialize_hdmi_ih_mutes();
++
++ /* Disable HDMI clocks until video/audio sub-drivers are initialized */
++ clk_disable_unprepare(isfr_clk);
++ clk_disable_unprepare(iahb_clk);
++ clk_disable_unprepare(mipi_core_clk);
++
++ /* Replace platform data coming in with a local struct */
++ platform_set_drvdata(pdev, hdmi_data);
++
++ return ret;
++
++eirq:
++ release_mem_region(res->start, resource_size(res));
++emem:
++ clk_disable_unprepare(iahb_clk);
++eclke2:
++ clk_put(iahb_clk);
++eclkg2:
++ clk_disable_unprepare(isfr_clk);
++eclke1:
++ clk_put(isfr_clk);
++eclkg1:
++ clk_disable_unprepare(mipi_core_clk);
++eclke:
++ clk_put(mipi_core_clk);
++eclkg:
++ return ret;
++}
++
++
++static int __exit mxc_hdmi_core_remove(struct platform_device *pdev)
++{
++ struct mxc_hdmi_data *hdmi_data = platform_get_drvdata(pdev);
++ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ iounmap(hdmi_data->reg_base);
++ release_mem_region(res->start, resource_size(res));
++
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx6q-hdmi-core", },
++ { .compatible = "fsl,imx6dl-hdmi-core", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_hdmi_core_driver = {
++ .driver = {
++ .name = "mxc_hdmi_core",
++ .of_match_table = imx_hdmi_dt_ids,
++ .owner = THIS_MODULE,
++ },
++ .remove = __exit_p(mxc_hdmi_core_remove),
++};
++
++static int __init mxc_hdmi_core_init(void)
++{
++ return platform_driver_probe(&mxc_hdmi_core_driver,
++ mxc_hdmi_core_probe);
++}
++
++static void __exit mxc_hdmi_core_exit(void)
++{
++ platform_driver_unregister(&mxc_hdmi_core_driver);
++}
++
++subsys_initcall(mxc_hdmi_core_init);
++module_exit(mxc_hdmi_core_exit);
++
++MODULE_DESCRIPTION("Core driver for Freescale i.Mx on-chip HDMI");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/mfd/si476x-i2c.c linux-3.14.72/drivers/mfd/si476x-i2c.c
+--- linux-3.14.72.orig/drivers/mfd/si476x-i2c.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mfd/si476x-i2c.c 2016-06-19 22:11:55.193147356 +0200
+@@ -303,7 +303,7 @@
+ */
+ udelay(100);
+
+- err = si476x_core_start(core, false);
++ err = si476x_core_start(core, true);
+ if (err < 0)
+ goto disable_regulators;
+
+@@ -312,7 +312,7 @@
+
+ case SI476X_POWER_DOWN:
+ core->power_state = next_state;
+- err = si476x_core_stop(core, false);
++ err = si476x_core_stop(core, true);
+ if (err < 0)
+ core->power_state = SI476X_POWER_INCONSISTENT;
+ disable_regulators:
+@@ -740,8 +740,15 @@
+ memcpy(&core->pinmux, &pdata->pinmux,
+ sizeof(struct si476x_pinmux));
+ } else {
+- dev_err(&client->dev, "No platform data provided\n");
+- return -EINVAL;
++ dev_warn(&client->dev, "Using default platform data.\n");
++ core->power_up_parameters.xcload = 0x28;
++ core->power_up_parameters.func = SI476X_FUNC_FM_RECEIVER;
++ core->power_up_parameters.freq = SI476X_FREQ_37P209375_MHZ;
++ core->diversity_mode = SI476X_PHDIV_DISABLED;
++ core->pinmux.dclk = SI476X_DCLK_DAUDIO;
++ core->pinmux.dfs = SI476X_DFS_DAUDIO;
++ core->pinmux.dout = SI476X_DOUT_I2S_OUTPUT;
++ core->pinmux.xout = SI476X_XOUT_TRISTATE;
+ }
+
+ core->supplies[0].supply = "vd";
+@@ -799,12 +806,19 @@
+
+ core->chip_id = id->driver_data;
+
++ /* Power down si476x first */
++ core->power_state = SI476X_POWER_UP_FULL;
++ si476x_core_set_power_state(core, SI476X_POWER_DOWN);
++
+ rval = si476x_core_get_revision_info(core);
+ if (rval < 0) {
+ rval = -ENODEV;
+ goto free_kfifo;
+ }
+
++ if (of_property_read_bool(client->dev.of_node, "revision-a10"))
++ core->revision = SI476X_REVISION_A10;
++
+ cell_num = 0;
+
+ cell = &core->cells[SI476X_RADIO_CELL];
+@@ -820,6 +834,7 @@
+ core->pinmux.xout == SI476X_XOUT_TRISTATE) {
+ cell = &core->cells[SI476X_CODEC_CELL];
+ cell->name = "si476x-codec";
++ cell->of_compatible = "si476x-codec";
+ cell_num++;
+ }
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/mfd/tda1997x-core.c linux-3.14.72/drivers/mfd/tda1997x-core.c
+--- linux-3.14.72.orig/drivers/mfd/tda1997x-core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mfd/tda1997x-core.c 2016-06-19 22:11:55.193147356 +0200
+@@ -0,0 +1,4605 @@
++/*
++ * Copyright (C) 2013 Gateworks Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ * TODO
++ * - add gpio reset pin
++ * - add gpio pwrdn pin
++ * - document devicetree bindings
++ * - unload/reload module interrupts never fire (something not getting reset)
++ */
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/gpio.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/spinlock.h>
++#include <linux/irq.h>
++#include <linux/interrupt.h>
++#include <linux/of_device.h>
++#include <linux/i2c.h>
++#include <linux/sysfs.h>
++#include <linux/delay.h>
++#include <linux/regulator/consumer.h>
++#include <linux/fsl_devices.h>
++#include <linux/workqueue.h>
++#include <linux/timer.h>
++#include <linux/mfd/tda1997x-core.h>
++#include <linux/time.h>
++
++#include <drm/drm_edid.h>
++#include <drm/drm_crtc.h>
++
++/* Voltage regulators */
++#define TDA1997X_VOLTAGE_DIGITAL_IO 3300000
++#define TDA1997X_VOLTAGE_DIGITAL_CORE 1800000
++#define TDA1997X_VOLTAGE_ANALOG 1800000
++
++static struct regulator *dvddio_regulator;
++static struct regulator *dvdd_regulator;
++static struct regulator *avdd_regulator;
++
++/* Page 0x00 */
++#define REG_VERSION 0x0000
++#define REG_INPUT_SEL 0x0001
++#define REG_SERVICE_MODE 0x0002
++#define REG_HPD_MAN_CTRL 0x0003
++#define REG_RT_MAN_CTRL 0x0004
++#define REG_STANDBY_SOFT_RST 0x000A
++#define REG_HDMI_SOFT_RST 0x000B
++#define REG_HDMI_INFO_RST 0x000C
++#define REG_INT_FLG_CLR_TOP 0x000E
++#define REG_INT_FLG_CLR_SUS 0x000F
++#define REG_INT_FLG_CLR_DDC 0x0010
++#define REG_INT_FLG_CLR_RATE 0x0011
++#define REG_INT_FLG_CLR_MODE 0x0012
++#define REG_INT_FLG_CLR_INFO 0x0013
++#define REG_INT_FLG_CLR_AUDIO 0x0014
++#define REG_INT_FLG_CLR_HDCP 0x0015
++#define REG_INT_FLG_CLR_AFE 0x0016
++#define REG_INT_MASK_TOP 0x0017
++#define REG_INT_MASK_SUS 0x0018
++#define REG_INT_MASK_DDC 0x0019
++#define REG_INT_MASK_RATE 0x001A
++#define REG_INT_MASK_MODE 0x001B
++#define REG_INT_MASK_INFO 0x001C
++#define REG_INT_MASK_AUDIO 0x001D
++#define REG_INT_MASK_HDCP 0x001E
++#define REG_INT_MASK_AFE 0x001F
++#define REG_DETECT_5V 0x0020
++#define REG_SUS_STATUS 0x0021
++#define REG_V_PER 0x0022
++#define REG_H_PER 0x0025
++#define REG_HS_WIDTH 0x0027
++#define REG_FMT_H_TOT 0x0029
++#define REG_FMT_H_ACT 0x002b
++#define REG_FMT_H_FRONT 0x002d
++#define REG_FMT_H_SYNC 0x002f
++#define REG_FMT_H_BACK 0x0031
++#define REG_FMT_V_TOT 0x0033
++#define REG_FMT_V_ACT 0x0035
++#define REG_FMT_V_FRONT_F1 0x0037
++#define REG_FMT_V_FRONT_F2 0x0038
++#define REG_FMT_V_SYNC 0x0039
++#define REG_FMT_V_BACK_F1 0x003a
++#define REG_FMT_V_BACK_F2 0x003b
++#define REG_FMT_DE_ACT 0x003c
++#define REG_RATE_CTRL 0x0040
++#define REG_CLK_MIN_RATE 0x0043
++#define REG_CLK_MAX_RATE 0x0046
++#define REG_CLK_A_STATUS 0x0049
++#define REG_CLK_A_RATE 0x004A
++#define REG_DRIFT_CLK_A_REG 0x004D
++#define REG_CLK_B_STATUS 0x004E
++#define REG_CLK_B_RATE 0x004F
++#define REG_DRIFT_CLK_B_REG 0x0052
++#define REG_HDCP_CTRL 0x0060
++#define REG_HDCP_KDS 0x0061
++#define REG_HDCP_BCAPS 0x0063
++#define REG_HDCP_KEY_CTRL 0x0064
++#define REG_INFO_CTRL 0x0076
++#define REG_INFO_EXCEED 0x0077
++#define REG_PIX_REPEAT 0x007B
++#define REG_AUDIO_PATH 0x007C
++#define REG_AUDIO_SEL 0x007D
++#define REG_AUDIO_OUT_ENABLE 0x007E
++#define REG_AUDIO_OUT_HIZ 0x007F
++#define REG_VDP_CTRL 0x0080
++#define REG_VHREF_CTRL 0x00A0
++#define REG_PXCNT_PR 0x00A2
++#define REG_PXCNT_NPIX 0x00A4
++#define REG_LCNT_PR 0x00A6
++#define REG_LCNT_NLIN 0x00A8
++#define REG_HREF_S 0x00AA
++#define REG_HREF_E 0x00AC
++#define REG_HS_S 0x00AE
++#define REG_HS_E 0x00B0
++#define REG_VREF_F1_S 0x00B2
++#define REG_VREF_F1_WIDTH 0x00B4
++#define REG_VREF_F2_S 0x00B5
++#define REG_VREF_F2_WIDTH 0x00B7
++#define REG_VS_F1_LINE_S 0x00B8
++#define REG_VS_F1_LINE_WIDTH 0x00BA
++#define REG_VS_F2_LINE_S 0x00BB
++#define REG_VS_F2_LINE_WIDTH 0x00BD
++#define REG_VS_F1_PIX_S 0x00BE
++#define REG_VS_F1_PIX_E 0x00C0
++#define REG_VS_F2_PIX_S 0x00C2
++#define REG_VS_F2_PIX_E 0x00C4
++#define REG_FREF_F1_S 0x00C6
++#define REG_FREF_F2_S 0x00C8
++#define REG_FDW_S 0x00ca
++#define REG_FDW_E 0x00cc
++#define REG_BLK_GY 0x00da
++#define REG_BLK_BU 0x00dc
++#define REG_BLK_RV 0x00de
++#define REG_FILTERS_CTRL 0x00e0
++#define REG_DITHERING_CTRL 0x00E9
++#define REG_OF_CTRL 0x00EA
++#define REG_CLKOUT_CTRL 0x00EB
++#define REG_HS_HREF_SEL 0x00EC
++#define REG_VS_VREF_SEL 0x00ED
++#define REG_DE_FREF_SEL 0x00EE
++#define REG_VP35_32_CTRL 0x00EF
++#define REG_VP31_28_CTRL 0x00F0
++#define REG_VP27_24_CTRL 0x00F1
++#define REG_VP23_20_CTRL 0x00F2
++#define REG_VP19_16_CTRL 0x00F3
++#define REG_VP15_12_CTRL 0x00F4
++#define REG_VP11_08_CTRL 0x00F5
++#define REG_VP07_04_CTRL 0x00F6
++#define REG_VP03_00_CTRL 0x00F7
++#define REG_CURPAGE_00H 0xFF
++#define MASK_VPER 0x3fffff
++#define MASK_HPER 0x0fff
++#define MASK_HSWIDTH 0x03ff
++
++/* Page 0x01 */
++#define REG_HDMI_FLAGS 0x0100
++#define REG_DEEP_COLOR_MODE 0x0101
++#define REG_AUDIO_FLAGS 0x0108
++#define REG_AUDIO_FREQ 0x0109
++#define REG_ACP_PACKET_TYPE 0x0141
++#define REG_ISRC1_PACKET_TYPE 0x0161
++#define REG_ISRC2_PACKET_TYPE 0x0181
++#define REG_GBD_PACKET_TYPE 0x01a1
++#define ISRC_PACKET_HDR_LEN 3
++#define ISRC_PACKET_DAT_LEN 16
++#define GDB_PACKET_HDR_LEN 3
++#define GDB_PACKET_DAT_LEN 28
++#define ACP_PACKET_HDR_LEN 3
++#define ACP_PACKET_DAT_LEN 16
++#define MASK_AUDIO_DST_RATE 0x80
++#define MASK_AUDIO_FREQ 0x07
++#define MASK_DC_PIXEL_PHASE 0xf0
++#define MASK_DC_COLOR_DEPTH 0x0f
++
++/* Page 0x12 */
++#define REG_CLK_CFG 0x1200
++#define REG_CLK_OUT_CFG 0x1201
++#define REG_CFG1 0x1202
++#define REG_CFG2 0x1203
++#define REG_WDL_CFG 0x1210
++#define REG_DELOCK_DELAY 0x1212
++#define REG_PON_OVR_EN 0x12A0
++#define REG_PON_CBIAS 0x12A1
++#define REG_PON_RESCAL 0x12A2
++#define REG_PON_RES 0x12A3
++#define REG_PON_CLK 0x12A4
++#define REG_PON_PLL 0x12A5
++#define REG_PON_EQ 0x12A6
++#define REG_PON_DES 0x12A7
++#define REG_PON_OUT 0x12A8
++#define REG_PON_MUX 0x12A9
++#define REG_MODE_RECOVER_CFG1 0x12F8
++#define REG_MODE_RECOVER_CFG2 0x12F9
++#define REG_MODE_RECOVER_STS 0x12FA
++#define REG_AUDIO_LAYOUT 0x12D0
++
++/* Page 0x13 */
++#define REG_DEEP_COLOR_CTRL 0x1300
++#define REG_CGU_DEBUG_SEL 0x1305
++#define REG_HDCP_DDC_ADDR 0x1310
++#define REG_HDCP_KIDX 0x1316
++#define REG_DEEP_PLL7 0x1347
++#define REG_HDCP_DE_CTRL 0x1370
++#define REG_HDCP_EP_FILT_CTRL 0x1371
++#define REG_HDMI_CTRL 0x1377
++#define REG_HMTP_CTRL 0x137a
++#define REG_TIMER_D 0x13CF
++#define REG_SUS_SET_RGB0 0x13E1
++#define REG_SUS_SET_RGB1 0x13E2
++#define REG_SUS_SET_RGB2 0x13E3
++#define REG_SUS_SET_RGB3 0x13E4
++#define REG_SUS_SET_RGB4 0x13E5
++#define REG_MAN_SUS_HDMI_SEL 0x13E8
++#define REG_MAN_HDMI_SET 0x13E9
++#define REG_SUS_CLOCK_GOOD 0x13EF
++
++/* CGU_DEBUG_SEL bits */
++#define CGU_DEBUG_CFG_CLK_MASK 0x18
++#define CGU_DEBUG_XO_FRO_SEL (1<<2)
++#define CGU_DEBUG_VDP_CLK_SEL (1<<1)
++#define CGU_DEBUG_PIX_CLK_SEL (1<<0)
++
++/* REG_MAN_SUS_HDMI_SEL / REG_MAN_HDMI_SET bits */
++#define MAN_DIS_OUT_BUF (1<<7)
++#define MAN_DIS_ANA_PATH (1<<6)
++#define MAN_DIS_HDCP (1<<5)
++#define MAN_DIS_TMDS_ENC (1<<4)
++#define MAN_DIS_TMDS_FLOW (1<<3)
++#define MAN_RST_HDCP (1<<2)
++#define MAN_RST_TMDS_ENC (1<<1)
++#define MAN_RST_TMDS_FLOW (1<<0)
++
++/* Page 0x14 */
++#define REG_FIFO_LATENCY_VAL 0x1403
++#define REG_AUDIO_CLOCK_MODE 0x1411
++#define REG_TEST_NCTS_CTRL 0x1415
++#define REG_TEST_AUDIO_FREQ 0x1426
++#define REG_TEST_MODE 0x1437
++
++/* Page 0x20 */
++#define REG_EDID_IN_BYTE0 0x2000 /* EDID base */
++#define REG_EDID_IN_VERSION 0x2080
++#define REG_EDID_ENABLE 0x2081
++#define REG_HPD_POWER 0x2084
++#define REG_HPD_AUTO_CTRL 0x2085
++#define REG_HPD_DURATION 0x2086
++#define REG_RX_HPD_HEAC 0x2087
++
++/* Page 0x21 */
++#define REG_EDID_IN_BYTE128 0x2100 /* CEA Extension block */
++#define REG_EDID_IN_SPA_SUB 0x2180
++#define REG_EDID_IN_SPA_AB_A 0x2181
++#define REG_EDID_IN_SPA_CD_A 0x2182
++#define REG_EDID_IN_CKSUM_A 0x2183
++#define REG_EDID_IN_SPA_AB_B 0x2184
++#define REG_EDID_IN_SPA_CD_B 0x2185
++#define REG_EDID_IN_CKSUM_B 0x2186
++
++/* Page 0x30 */
++#define REG_RT_AUTO_CTRL 0x3000
++#define REG_EQ_MAN_CTRL0 0x3001
++#define REG_EQ_MAN_CTRL1 0x3002
++#define REG_OUTPUT_CFG 0x3003
++#define REG_MUTE_CTRL 0x3004
++#define REG_SLAVE_ADDR 0x3005
++#define REG_CMTP_REG6 0x3006
++#define REG_CMTP_REG7 0x3007
++#define REG_CMTP_REG8 0x3008
++#define REG_CMTP_REG9 0x3009
++#define REG_CMTP_REGA 0x300A
++#define REG_CMTP_REGB 0x300B
++#define REG_CMTP_REGC 0x300C
++#define REG_CMTP_REGD 0x300D
++#define REG_CMTP_REGE 0x300E
++#define REG_CMTP_REGF 0x300F
++#define REG_CMTP_REG10 0x3010
++#define REG_CMTP_REG11 0x3011
++
++/* CEC */
++#define REG_PWR_CONTROL 0x80F4
++#define REG_OSC_DIVIDER 0x80F5
++#define REG_EN_OSC_PERIOD_LSB 0x80F8
++#define REG_CONTROL 0x80FF
++
++/* global interrupt flags (INT_FLG_CRL_TOP) */
++#define INTERRUPT_AFE (1<<7) /* AFE module */
++#define INTERRUPT_HDCP (1<<6) /* HDCP module */
++#define INTERRUPT_AUDIO (1<<5) /* Audio module */
++#define INTERRUPT_INFO (1<<4) /* Infoframe module */
++#define INTERRUPT_MODE (1<<3) /* HDMI mode module */
++#define INTERRUPT_RATE (1<<2) /* rate module */
++#define INTERRUPT_DDC (1<<1) /* DDC module */
++#define INTERRUPT_SUS (1<<0) /* SUS module */
++
++/* INT_FLG_CLR_HDCP bits */
++#define MASK_HDCP_MTP (1<<7) /* HDCP MTP busy */
++#define MASK_HDCP_DLMTP (1<<4) /* HDCP end download MTP to SRAM */
++#define MASK_HDCP_DLRAM (1<<3) /* HDCP end download keys from SRAM */
++#define MASK_HDCP_ENC (1<<2) /* HDCP ENC */
++#define MASK_STATE_C5 (1<<1) /* HDCP State C5 reached */
++#define MASK_AKSV (1<<0) /* AKSV received (start of auth) */
++
++/* INT_FLG_CLR_RATE bits */
++#define MASK_RATE_B_DRIFT (1<<7) /* Rate measurement drifted */
++#define MASK_RATE_B_ST (1<<6) /* Rate measurement stability change */
++#define MASK_RATE_B_ACT (1<<5) /* Rate measurement activity change */
++#define MASK_RATE_B_PST (1<<4) /* Rate measreument presence change */
++#define MASK_RATE_A_DRIFT (1<<3) /* Rate measurement drifted */
++#define MASK_RATE_A_ST (1<<2) /* Rate measurement stability change */
++#define MASK_RATE_A_ACT (1<<1) /* Rate measurement presence change */
++#define MASK_RATE_A_PST (1<<0) /* Rate measreument presence change */
++
++/* INT_FLG_CLR_SUS (Start Up Sequencer) bits */
++#define MASK_MPT_BIT (1<<7) /* Config MTP end of process */
++#define MASK_FMT_BIT (1<<5) /* Video format changed */
++#define MASK_RT_PULSE_BIT (1<<4) /* End of termination resistance pulse */
++#define MASK_SUS_END_BIT (1<<3) /* SUS last state reached */
++#define MASK_SUS_ACT_BIT (1<<2) /* Activity of selected input changed */
++#define MASK_SUS_CH_BIT (1<<1) /* Selected input changed */
++#define MASK_SUS_ST_BIT (1<<0) /* SUS state changed */
++
++/* INT_FLG_CLR_DDC bits */
++#define MASK_EDID_MTP (1<<7) /* EDID MTP end of process */
++#define MASK_DDC_ERR (1<<6) /* master DDC error */
++#define MASK_DDC_CMD_DONE (1<<5) /* master DDC cmd send correct */
++#define MASK_READ_DONE (1<<4) /* End of down EDID read */
++#define MASK_RX_DDC_SW (1<<3) /* Output DDC switching finished */
++#define MASK_HDCP_DDC_SW (1<<2) /* HDCP DDC switching finished */
++#define MASK_HDP_PULSE_END (1<<1) /* End of Hot Plug Detect pulse */
++#define MASK_DET_5V (1<<0) /* Detection of +5V */
++
++/* INT_FLG_CLR_MODE bits */
++#define MASK_HDMI_FLG (1<<7) /* HDMI mode, avmute, encrypt-on, FIFO fail */
++#define MASK_GAMUT (1<<6) /* Gamut packet */
++#define MASK_ISRC2 (1<<5) /* ISRC2 packet */
++#define MASK_ISRC1 (1<<4) /* ISRC1 packet */
++#define MASK_ACP (1<<3) /* Audio Content Protection packet */
++#define MASK_DC_NO_GCP (1<<2) /* GCP not recieved in 5 frames */
++#define MASK_DC_PHASE (1<<1) /* deep color mode pixel phase needs update */
++#define MASK_DC_MODE (1<<0) /* deep color mode color depth changed */
++
++/* INT_FLG_CLR_INFO bits */
++#define MASK_MPS_IF (1<<6) /* MPEG Source Product IF change */
++#define MASK_AUD_IF (1<<5) /* Audio IF change */
++#define MASK_SPD_IF (1<<4) /* Source Product Descriptor IF change */
++#define MASK_AVI_IF (1<<3) /* Auxiliary Video information IF change */
++#define MASK_VS_IF_OTHER_BK2 (1<<2) /* Vendor Specific IF (bank2) change */
++#define MASK_VS_IF_OTHER_BK1 (1<<1) /* Vendor Specific IF (bank1) change */
++#define MASK_VS_IF_HDMI (1<<0) /* Vendor Specific IF (with HDMI LLC reg code) change */
++
++/* INT_FLG_CLR_AUDIO bits */
++#define MASK_AUDIO_FREQ_FLG (1<<5) /* Audio freq change */
++#define MASK_AUDIO_FLG (1<<4) /* DST, OBA, HBR, ASP change */
++#define MASK_MUTE_FLG (1<<3) /* Audio Mute */
++#define MASK_CH_STATE (1<<2) /* Channel status */
++#define MASK_UNMUTE_FIFO (1<<1) /* Audio Unmute */
++#define MASK_ERROR_FIFO_PT (1<<0) /* Audio FIFO pointer error */
++
++/* INT_FLG_CLR_AFE bits */
++#define MASK_AFE_WDL_UNLOCKED (1<<7) /* Wordlocker was unlocked */
++#define MASK_AFE_GAIN_DONE (1<<6) /* Gain calibration done */
++#define MASK_AFE_OFFSET_DONE (1<<5) /* Offset calibration done */
++#define MASK_AFE_ACTIVITY_DET (1<<4) /* Activity detected on data */
++#define MASK_AFE_PLL_LOCK (1<<3) /* TMDS PLL is locked */
++#define MASK_AFE_TRMCAL_DONE (1<<2) /* Termination calibration done */
++#define MASK_AFE_ASU_STATE (1<<1) /* ASU state is reached */
++#define MASK_AFE_ASU_READY (1<<0) /* AFE calibration done: TMDS ready */
++
++/* OF_CTRL bits */
++#define VP_OUT (1<<7) /* enable VP[35:0], HS, VS, DE, V_CLK */
++#define VP_HIZ (1<<6) /* unused VP pins Hi-Z */
++#define VP_BLK (1<<4) /* Insert blanking code in data */
++#define VP_TRC (1<<3) /* Insert timing code (SAV/EAV) in data*/
++#define VP_FORMAT_SEL_MASK 0x7 /* format selection */
++
++/* HDMI_SOFT_RST bits */
++#define RESET_DC (1<<7) /* Reset deep color module */
++#define RESET_HDCP (1<<6) /* Reset HDCP module */
++#define RESET_KSV (1<<5) /* Reset KSV-FIFO */
++#define RESET_SCFG (1<<4) /* Reset HDCP and repeater function */
++#define RESET_HCFG (1<<3) /* Reset HDCP DDC part */
++#define RESET_PA (1<<2) /* Reset polarity adjust */
++#define RESET_EP (1<<1) /* Reset Error protection */
++#define RESET_TMDS (1<<0) /* Reset TMDS (calib, encoding, flow) */
++
++/* HDMI_INFO_RST bits */
++#define NACK_HDCP (1<<7) /* No ACK on HDCP request */
++#define RESET_FIFO (1<<4) /* Reset Audio FIFO control */
++#define RESET_GAMUT (1<<3) /* Clear Gamut packet */
++#define RESET_AI (1<<2) /* Clear ACP and ISRC packets */
++#define RESET_IF (1<<1) /* Clear all Audio infoframe packets */
++#define RESET_AUDIO (1<<0) /* Reset Audio FIFO control */
++
++/* HDCP_BCAPS bits */
++#define HDCP_HDMI (1<<7) /* HDCP suports HDMI (vs DVI only) */
++#define HDCP_REPEATER (1<<6) /* HDCP supports repeater function */
++#define HDCP_READY (1<<5) /* set by repeater function */
++#define HDCP_FAST (1<<4) /* Up to 400kHz */
++#define HDCP_11 (1<<1) /* HDCP 1.1 supported */
++#define HDCP_FAST_REAUTH (1<<0) /* fast reauthentication suported */
++
++/* masks for interrupt status registers */
++#define MASK_SUS_STATE_VALUE 0x1F
++#define LAST_STATE_REACHED 0x1B
++#define MASK_CLK_STABLE 0x04
++#define MASK_CLK_ACTIVE 0x02
++#define MASK_SUS_STATE_BIT 0x10
++#define MASK_SR_FIFO_FIFO_CTRL 0x30
++#define MASK_AUDIO_FLAG 0x10
++
++/* Power Control */
++#define MASK_OF_CTRL_OUT_HIZ 0x80
++#define MASK_AUDIO_PLL_PD 0x80
++#define DC_PLL_PD 0x01
++#define DC_PLL_PON 0x00
++#define MASK_XTAL_OSC_PD 0x02
++#define MASK_TMDS_CLK_DIS 0x08
++#define CBIAS_PON 0x01
++#define CBIAS_POFF 0x00
++#define TMDS_AUTO_PON 0x00
++#define TMDS_MAN_PON 0x01
++#define MASK_LOW_PW_EDID 0x01
++
++/* Rate measurement */
++#define RATE_REFTIM_ENABLE 0x01
++#define CLK_MIN_RATE 0x0057e4
++#define CLK_MAX_RATE 0x0395f8
++#define WDL_CFG_VAL 0x82
++#define DC_FILTER_VAL 0x31
++
++/* Infoframe */
++#define VS_HDMI_IF_UPDATE 0x0200
++#define VS_HDMI_IF_TYPE 0x0201
++#define VS_BK1_IF_UPDATE 0x0220
++#define VS_BK1_IF_TYPE 0x0221
++#define VS_BK2_IF_UPDATE 0x0240
++#define VS_BK2_IF_TYPE 0x0241
++#define AVI_IF_UPDATE 0x0260
++#define AVI_IF_TYPE 0x0261
++#define AVI_IF_NB_DATA 17
++#define SPD_IF_UPDATE 0x0280
++#define SPD_IF_TYPE 0x0281
++#define SPD_IF_NB_DATA 31
++#define AUD_IF_UPDATE 0x02a0
++#define AUD_IF_TYPE 0x02a1
++#define AUD_IF_NB_DATA 14
++#define MPS_IF_UPDATE 0x02c0
++#define MPS_IF_TYPE 0x02c1
++#define MPS_IF_NB_DATA 14
++#define MAX_IF_DATA 40
++#define VS_IF_NB 31
++
++/* Input Selection */
++#define MASK_DIG_INPUT 0x01
++#define MASK_DIG_INPUT_VDPR_FMT 0x85
++#define MASK_HDMIOUTMODE 0x02
++#define FORMAT_RESET 0x80
++
++/* Colorspace Conversion Registers */
++#define MAT_OFFSET_NB 3
++#define MAT_COEFF_NB 9
++#define OFFSET_LOOP_NB 2
++#define MIN_VAL_OFFSET -4096
++#define MAX_VAL_OFFSET 4095
++#define MIN_VAL_COEFF -16384
++#define MAX_VAL_COEFF 16383
++#define MASK_MAT_COEFF_LSB 0x00FF
++
++/* Blanking code values depend on output colorspace (RGB or YUV) */
++typedef struct
++{
++ s16 blankingCodeGy;
++ s16 blankingCodeBu;
++ s16 blankingCodeRv;
++} blankingcodes_t;
++
++blankingcodes_t RGBBlankingCode = {64, 64, 64};
++blankingcodes_t YUVBlankingCode = {64, 512, 512};
++
++/* Video Colorspace formats */
++typedef enum {
++ COLORSPACE_RGB,
++ COLORSPACE_YCBCR_422,
++ COLORSPACE_YCBCR_444,
++ COLORSPACE_FUTURE,
++} tda1997x_colorspace_t;
++
++/* Video Colorimetry formats */
++typedef enum {
++ COLORIMETRY_NONE,
++ COLORIMETRY_ITU601,
++ COLORIMETRY_ITU709,
++ COLORIMETRY_XVYCC,
++} tda1997x_colorimetry_t;
++
++/* Video colormode formats */
++typedef enum {
++ DEEPCOLORMODE_NOT_INDICATED = 0x00,
++ DEEPCOLORMODE_24 = 0x04,
++ DEEPCOLORMODE_30 = 0x05,
++ DEEPCOLORMODE_36 = 0x06,
++ DEEPCOLORMODE_48 = 0x07,
++} tda1997x_deepcolor_t;
++
++/* resolution type */
++typedef enum {
++ RESTYPE_SDTV,
++ RESTYPE_HDTV,
++ RESTYPE_PC,
++} tda1997x_restype_t;
++
++/* Video output port format */
++const char *vidfmt_names[] = {
++ "RGB444/YUV444", /* RGB/YUV444 16bit data bus, 8bpp */
++ "YUV422 semi-planar", /* YUV422 16bit data base, 8bpp */
++ "YUV422 CCIR656", /* BT656 (YUV 8bpp 2 clock per pixel) */
++};
++
++static char *colorspace_names[] = {
++ "RGB", "YUV422", "YUV444", "Future"
++};
++
++static char *colorimetry_names[] = {
++ "", "ITU601", "ITU709", "XVYCC"
++};
++
++/* HDCP */
++#define RX_SEED_TABLE_LEN 10 /* HDCP Seed */
++typedef enum
++{
++ HDCP_DECRYPTKEY_OFF = 0x00,
++ HDCP_DECRYPTKEY_ON = 0x02
++} hdcp_key_t;
++typedef enum
++{
++ DISABLE = 0x00,
++ ENABLE = 0x01
++} enable_t;
++
++/* MTP */
++typedef enum {
++ MTP_START_DOWNLOAD,
++ MTP_START_READ,
++} mtp_command_t;
++
++/* HPD modes */
++typedef enum {
++ HPD_LOW, /* HPD low and pulse of at least 100ms */
++ HPD_LOW_OTHER, /* HPD low and pulse of at least 100ms */
++ HPD_HIGH, /* HIGH */
++ HPD_HIGH_OTHER,
++ HPD_PULSE, /* HPD low pulse */
++} hpdmode_t;
++
++/** configure colorspace conversion matrix
++ * The color conversion matrix will convert between the colorimetry of the
++ * HDMI input to the desired output format RGB|YUV
++ */
++typedef enum {
++ ITU709_RGBLimited,
++ RGBLimited_ITU601,
++ ITU601_RGBLimited,
++} colorconversion_t;
++
++/* Colorspace conversion matrix coefficients and offsets
++ */
++typedef struct
++{
++ /* Input offsets */
++ s16 offInt1;
++ s16 offInt2;
++ s16 offInt3;
++ /* Coeficients */
++ s16 P11Coef;
++ s16 P12Coef;
++ s16 P13Coef;
++ s16 P21Coef;
++ s16 P22Coef;
++ s16 P23Coef;
++ s16 P31Coef;
++ s16 P32Coef;
++ s16 P33Coef;
++ /* Output offsets */
++ s16 offOut1;
++ s16 offOut2;
++ s16 offOut3;
++} colormatrixcoefs_t;
++
++/* Conversion matrixes */
++colormatrixcoefs_t conversion_matrix[] = {
++ /* ITU709 -> RGBLimited */
++ {
++ -256, -2048, -2048, /*Input Offset*/
++ 4096, -1875, -750,
++ 4096, 6307, 0,
++ 4096, 0, 7431,
++ 256, 256, 256 /*Output Offset*/
++ },
++ /* RGBLimited -> ITU601 */
++ {
++ -256, -256, -256, /*Input Offset*/
++ 2404, 1225, 467,
++ -1754, 2095, -341,
++ -1388, -707, 2095, /*RGB limited range => ITU-601 YUV limited range */
++ 256, 2048, 2048 /*Output Offset*/
++ },
++ /* YUV601 -> RGBLimited */
++ {
++ -256, -2048, -2048, /*Input Offset*/
++ 4096, -2860, -1378,
++ 4096, 5615, 0,
++ 4096, 0, 7097, /*ITU-601 YUV limited range => RGB limited range */
++ 256, 256, 256 /*Output Offset*/
++ }
++};
++
++/* HDCP seed table, arranged as pairs of 16bit integrers: lookup val, seed val
++ * If no table is programmed or KEY_SED in config file is null, HDCP will be
++ * disabled
++ */
++typedef struct {
++ u16 lookUpVal;
++ u16 seedVal;
++} hdmi_cfg_seed_t;
++
++const hdmi_cfg_seed_t rx_seed_table[RX_SEED_TABLE_LEN] = {
++ {0xF0, 0x1234},
++ {0xF1, 0xDBE6},
++ {0xF2, 0xDBE6},
++ {0, 0x1234},
++ {0, 0},
++ {0, 0},
++ {0, 0},
++ {0, 0},
++ {0, 0},
++ {0, 0}
++};
++
++/** Video Input mode database
++ * TODO: can I use something like modedb instead?
++ * More recent kernels have some CEA data
++ */
++static char *restype_names[] = {
++ "SDTV", "HDTV", "PC",
++};
++
++typedef enum
++{
++ VIDEORES_1280_720p_24HZ,
++ VIDEORES_1280_720p_25HZ,
++ VIDEORES_1280_720p_30HZ,
++ VIDEORES_1920_1080p_24HZ,
++ VIDEORES_1920_1080p_25HZ,
++ VIDEORES_1920_1080p_30HZ,
++
++ VIDEORES_720_480p_60HZ,
++ VIDEORES_1280_720p_60HZ,
++ VIDEORES_1920_1080i_60HZ,
++ VIDEORES_720_480i_60HZ,
++ VIDEORES_1920_1080p_60HZ,
++
++ VIDEORES_720_576p_50HZ,
++ VIDEORES_1280_720p_50HZ,
++ VIDEORES_1920_1080i_50HZ,
++ VIDEORES_720_576i_50HZ,
++ VIDEORES_1920_1080p_50HZ,
++
++ VIDEORES_640_480p_60HZ, /* VGA */
++ VIDEORES_800_600p_60HZ, /* SVGA */
++ VIDEORES_1024_768p_60HZ, /* XGA */
++ VIDEORES_1280_768p_60HZ, /* WXGA */
++ VIDEORES_1280_960p_60HZ, /* ???? */
++ VIDEORES_1280_1024p_60HZ, /* SXGA */
++ VIDEORES_1440_900p_60HZ, /* ???? */
++ VIDEORES_1600_1200p_60HZ, /* UGA */
++ VIDEORES_1680_1050p_60HZ_RB, /* WSXGA */
++ VIDEORES_1920_1200p_60HZ_RB, /* WUXGA */
++
++ VIDEORES_640_480p_75HZ, /* VGA */
++ VIDEORES_800_600p_75HZ, /* SVGA */
++ VIDEORES_1024_768p_75HZ, /* XGA */
++ VIDEORES_1280_768p_75HZ, /* WXGA */
++ VIDEORES_1280_1024p_75HZ, /* SXGA */
++
++ VIDEORES_640_480p_85HZ, /* VGA */
++ VIDEORES_800_600p_85HZ, /* SVGA */
++ VIDEORES_1024_768p_85HZ, /* XGA */
++ VIDEORES_1280_768p_85HZ, /* WXGA */
++ VIDEORES_1280_1024p_85HZ, /* SXGA */
++
++ VIDEORES_720_240p_60HZ_M1, /* 720(1440, 2880)x240p 60Hz mode 1 */
++ VIDEORES_720_240p_60HZ_M2, /* 720(1440, 2880)x240p 60Hz mode 2 */
++
++ VIDEORES_720_288p_50HZ_M1, /* 720(1440)x288p 50Hz mode 1 */
++ VIDEORES_720_288p_50HZ_M2, /* 720(1440)x288p 50Hz mode 1 */
++ VIDEORES_720_288p_50HZ_M3, /* 720(1440)x288p 50Hz mode 1 */
++
++ VIDEORES_1360_768p_60HZ, /* 1360x768p 60Hz (PC resolution) */
++ VIDEORES_1400_1050p_60HZ, /* 1400x1050p 60Hz (PC resolution) */
++ VIDEORES_1400_1050p_60HZ_RB, /* 1400x1050p 60Hz Reduced Blanking (PC) */
++
++ VIDEORES_1024_768p_70HZ, /* XGA */
++ VIDEORES_640_480p_72HZ, /* VGA */
++ VIDEORES_800_600p_72HZ, /* SVGA */
++
++ VIDEORES_640_350p_85HZ, /* 640x350p 85Hz (PC) */
++ VIDEORES_640_400p_85HZ, /* 640x400p 85Hz (PC) */
++ VIDEORES_720_400p_85HZ, /* 720x400p 85Hz (PC) */
++ VIDEORES_UNKNOWN
++} resolutionid_t;
++
++/* structure for video format measurements */
++typedef struct
++{
++ u8 videoFormat; /* 1=interlaced or 0=progressive */
++ u8 vsPolarity; /* 1=negative 0=positive */
++ u8 hsPolarity; /* 1=negative 0=positive */
++ u16 horizontalTotalPeriod; /* period of 1 line (pixel clocks) */
++ u16 horizontalVideoActiveWidth; /* period of 1 active line (pixel clocks) */
++ u16 horizontalFrontPorchWidth; /* width of front porch */
++ u16 horizontalBackPorchWidth; /* width of back porch */
++ u16 horizontalSyncWidthPixClk;
++ u16 verticalTotalPeriod; /* period of a frame in line numbers */
++ u16 verticalVideoActiveWidth;
++ u16 verticalFrontPorchWidthF1; /* vertical front porch width of field 1 */
++ u16 verticalFrontPorchWidthF2; /* vertical front porch width of field 2*/
++ u16 verticalSyncWidth; /* width of the VS in line numbers */
++ u16 verticalBackPorchWidthF1; /* vertical back porch width of field 1 */
++ u16 verticalBackPorchWidthF2; /* vertical back porch width of field 2 */
++ u16 dataEnablePresent; /* 1=DE signal present */
++} videoFormatDetails;
++
++typedef struct
++{
++ u8 resolutionID;
++ u16 width;
++ u16 height;
++ u8 horizfreq;
++ u8 interlaced;
++ u32 verticalPeriodMin; /* = MCLK(27MHz) / VFreq minus 0.7% */
++ u32 verticalPeriodMax; /* same + 0.7% */
++ u16 horizontalPeriodMin; /* = MCLK(27MHz) / HFreq minus 1% */
++ u16 horizontalPeriodMax;
++ u16 hsWidthMin; /* = MCLK(27MHz) / pixclk * hWidth minux ...% */
++ u16 hsWidthMax;
++} resolution_data_t;
++
++typedef struct
++{
++ u16 href_start;
++ u16 href_end;
++ u16 vref_f1_start;
++ u8 vref_f1_width;
++ u16 vref_f2_start;
++ u8 vref_f2_width;
++ u16 fieldref_f1_start;
++ u8 fieldPolarity;
++ u16 fieldref_f2_start;
++} vhref_values_t;
++
++typedef struct
++{
++ u8 resolutionID;
++ u16 pixCountPreset;
++ u16 pixCountNb;
++ u16 lineCountPreset;
++ u16 lineCountNb;
++ vhref_values_t vhref_values;
++} resolution_timings_t;
++
++const resolution_timings_t resolution_timings[] = {
++ /* Low TV */
++ {VIDEORES_1280_720p_24HZ, 1, 3300, 1, 750,
++ {261, 1541, 745, 30, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1280_720p_25HZ, 1, 3960, 1, 750,
++ {261, 1541, 745, 30, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1280_720p_30HZ, 1, 3300, 1, 750,
++ {261, 1541, 745, 30, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1920_1080p_24HZ, 1, 2750, 1, 1125,
++ {193, 2113, 1121, 45, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1920_1080p_25HZ, 1, 2640, 1, 1125,
++ {193, 2113, 1121, 45, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1920_1080p_30HZ, 1, 2200, 1, 1125,
++ {193, 2113, 1121, 45, 0, 0, 1, 0, 0}
++ },
++
++ /* 60 Hz TV */
++ {VIDEORES_720_480p_60HZ, 1, 858, 1, 525,
++ {123, 843, 516, 45, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1280_720p_60HZ, 1, 1650, 1, 750,
++ {261, 1541, 745, 30, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1920_1080i_60HZ, 1, 2200, 1, 1125,
++ {193, 2113, 1123, 22, 560, 23, 1, 0, 563}
++ },
++ {VIDEORES_720_480i_60HZ, 1, 858, 1, 525,
++ {120, 840, 521, 22, 258, 23, 1, 0, 263}
++ },
++ {VIDEORES_1920_1080p_60HZ, 1, 2200, 1, 1125,
++ {193, 2113, 1121, 45, 0, 0, 1, 0, 0}
++ },
++
++ /* 50 Hz TV */
++ {VIDEORES_720_576p_50HZ, 1, 864, 1, 625,
++ {133, 853, 620, 49, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1280_720p_50HZ, 1, 1980, 1, 750,
++ {261, 1541, 745, 30, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_1920_1080i_50HZ, 1, 2640, 1, 1125,
++ {193, 2113, 1123, 22, 560, 23, 1, 0, 563}
++ },
++ {VIDEORES_720_576i_50HZ, 1, 864, 1, 625,
++ {133, 853, 623, 24, 310, 25, 1, 0, 313 }
++ },
++ {VIDEORES_1920_1080p_50HZ, 1, 2640, 1, 1125,
++ {193, 2113, 1121, 45, 0, 0, 1, 0, 0}
++ },
++
++ /* 60 Hz PC */
++ {VIDEORES_640_480p_60HZ, 1, 800, 1, 525,
++ {145, 785, 515, 45, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_800_600p_60HZ, 1, 1056, 1, 628,
++ {217, 1017, 627, 28, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1024_768p_60HZ, 1, 1344, 1, 806,
++ {297, 1321, 803, 38, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1280_768p_60HZ, 1, 1440, 1, 790,
++ {321, 1601, 795, 30, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1280_960p_60HZ, 1, 1800, 1, 1000,
++ {425, 1705, 999, 40, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1280_1024p_60HZ, 1, 1688, 1, 1066,
++ {361, 1641, 1065, 42, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1440_900p_60HZ, 1, 1904, 1, 934,
++ {385, 1825, 931, 34, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1600_1200p_60HZ, 1, 2160, 1, 1250,
++ {497, 2097, 1249, 50, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1680_1050p_60HZ_RB, 1, 1840, 1, 1080,
++ {113, 1793, 1077, 30, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1920_1200p_60HZ_RB, 1, 2080, 1, 1235,
++ {113, 2033, 1232, 35, 0, 0, 0, 0, 0}
++ },
++
++ /* 75 HZ PC */
++ {VIDEORES_640_480p_75HZ, 1, 840, 1, 500,
++ {185, 825, 499, 20, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_800_600p_75HZ, 1, 1056, 1, 625,
++ {241, 1041, 624, 25, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1024_768p_75HZ, 1, 1312, 1, 800,
++ {273, 1297, 799, 32, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1280_768p_75HZ, 1, 1696, 1, 805,
++ {337, 1617, 802, 37, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1280_1024p_75HZ, 1, 1688, 1, 1066,
++ {393, 1673, 1065, 42, 0, 0, 0, 0, 0}
++ },
++
++ /* 85 HZ PC */
++ {VIDEORES_640_480p_85HZ, 1, 832, 1, 509,
++ {137, 777, 508, 29, 0, 0, 1, 0, 0}
++ },
++ {VIDEORES_800_600p_85HZ, 1, 1048, 1, 631,
++ {217, 1017, 630, 31, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1024_768p_85HZ, 1, 1376, 1, 808,
++ {305, 1329, 807, 40, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1280_768p_85HZ, 1, 1712, 1, 908,
++ {353, 1633, 905, 140, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1280_1024p_85HZ, 1, 1728, 1, 1072,
++ {385, 1665, 1071, 48, 0, 0, 0, 0, 0}
++ },
++
++ /* Other resolutions */
++ {VIDEORES_720_240p_60HZ_M1, 1, 858, 1, 262,
++ {120, 840, 258, 22, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_720_240p_60HZ_M2, 1, 858, 1, 263,
++ {120, 840, 258, 23, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_720_288p_50HZ_M1, 1, 864, 1, 312,
++ {133, 853, 310, 24, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_720_288p_50HZ_M2, 1, 864, 1, 313,
++ {133, 853, 310, 25, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_720_288p_50HZ_M3, 1, 864, 1, 314,
++ {133, 853, 310, 26, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1360_768p_60HZ, 1, 1792, 1, 795,
++ {369, 1729, 792, 27, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1400_1050p_60HZ, 1, 1864, 1, 1089,
++ {377, 1777, 1086, 39, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1400_1050p_60HZ_RB, 1, 1560, 1, 1080,
++ {113, 1513, 1077, 30, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_1024_768p_70HZ, 1, 1328, 1, 806,
++ {281, 1305, 803, 38, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_640_480p_72HZ, 1, 832, 1, 520,
++ {169, 809, 511, 40, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_800_600p_72HZ, 1, 1040, 1, 666,
++ {185, 985, 629, 66, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_640_350p_85HZ, 1, 832, 1, 445,
++ {161, 801, 413, 95, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_640_400p_85HZ, 1, 832, 1, 445,
++ {161, 801, 444, 45, 0, 0, 0, 0, 0}
++ },
++ {VIDEORES_720_400p_85HZ, 1, 936, 1, 446,
++ {181, 901, 445, 46, 0, 0, 0, 0, 0}
++ }
++};
++
++const resolution_data_t supported_res[] =
++{
++ /* Low TV */
++ {VIDEORES_1280_720p_24HZ, 1280,720,24,0, 1117178, 1134065, 1488, 1513, 17, 19},
++ {VIDEORES_1280_720p_25HZ, 1280,720,25,0, 1072491, 1087614, 1428, 1451, 13, 15},
++ {VIDEORES_1280_720p_30HZ, 1280,720,30,0, 893742, 907252, 1190, 1210, 13, 15},
++ {VIDEORES_1920_1080p_24HZ, 1920,1080,24,0, 1117178, 1134065, 992, 1009, 14, 17},
++ {VIDEORES_1920_1080p_25HZ, 1920,1080,25,0, 1072491, 1087614, 952, 967, 14, 17},
++ {VIDEORES_1920_1080p_30HZ, 1920,1080,30,0, 893742, 907252, 794, 806, 14, 17},
++
++ /* 60 Hz TV */
++ {VIDEORES_720_480p_60HZ, 720,480,60,0, 446870, 453626, 850, 865, 60, 63},
++ {VIDEORES_1280_720p_60HZ, 1280,720,60,0, 446870, 453626, 594, 605, 13, 15},
++ {VIDEORES_1920_1080i_60HZ, 1920,1080,60,1, 446870, 453626, 793, 807, 14, 17},
++ {VIDEORES_720_480i_60HZ, 720,480,60,1, 446870, 453626, 1701, 1729, 122, 125},
++ {VIDEORES_1920_1080p_60HZ, 1920,1080,60,0, 446870, 453626, 396, 404, 6, 9},
++
++ /* 50 Hz TV */
++ {VIDEORES_720_576p_50HZ, 720,576,50,0, 536245, 543807, 856, 871, 62, 65},
++ {VIDEORES_1280_720p_50HZ, 1280,720,50,0, 536245, 543807, 713, 726, 13, 15},
++ {VIDEORES_1920_1080i_50HZ, 1920,1080,50,1, 536245, 543807, 952, 967, 14, 17},
++ {VIDEORES_720_576i_50HZ, 720,576,50,1, 536245, 543807, 1714, 1741, 124, 127},
++ {VIDEORES_1920_1080p_50HZ, 1920,1080,50,0, 536245, 543807, 475, 484, 6, 9},
++
++ /* 60 HZ PC */
++ {VIDEORES_640_480p_60HZ, 640,480,60,0, 446870, 453626, 850, 865, 101, 104},
++ {VIDEORES_800_600p_60HZ, 800,600,60,0, 444523, 450791, 708, 718, 84, 88},
++ {VIDEORES_1024_768p_60HZ, 1024,768,60,0, 446842, 453142, 554, 562, 54, 58},
++ {VIDEORES_1280_768p_60HZ, 1280,768,60,0, 447842, 454156, 561, 569, 41, 46},
++ {VIDEORES_1280_960p_60HZ, 1280,960,60,0, 446872, 453172, 447, 453, 26, 30},
++ {VIDEORES_1280_1024p_60HZ, 1280,1024,60,0, 446723, 453021, 419, 425, 26, 30},
++ {VIDEORES_1440_900p_60HZ, 1440,900,60,0, 446723, 453021, 478, 486, 35, 40},
++ {VIDEORES_1600_1200p_60HZ, 1600,1200,60,0, 446872, 453172, 357, 363, 30, 34},
++ {VIDEORES_1680_1050p_60HZ_RB, 1680,1050,60,0, 447745, 454058, 415, 420, 5, 9},
++ {VIDEORES_1920_1200p_60HZ_RB, 1920,1200,60,0, 447235, 453550, 362, 367, 4, 8},
++
++ /* 75 HZ PC */
++ {VIDEORES_640_480p_75HZ, 640,480,75,0, 357498, 362538, 715, 725, 53, 57},
++ {VIDEORES_800_600p_75HZ, 800,600,75,0, 357498, 362538, 572, 580, 42, 46},
++ {VIDEORES_1024_768p_75HZ, 1024,768,75,0, 357359, 362398, 447, 453, 31, 35},
++ {VIDEORES_1280_768p_75HZ, 1280,768,75,0, 357480, 362520, 444, 450, 32, 36},
++ {VIDEORES_1280_1024p_75HZ, 1280,1024,75,0, 357378, 362417, 335, 340, 27, 31},
++
++ /* 85 HZ PC */
++ {VIDEORES_640_480p_85HZ, 640,480,85,0, 315409, 319856, 620, 628, 40, 44},
++ {VIDEORES_800_600p_85HZ, 800,600,85,0, 315213, 319657, 500, 507, 29, 33},
++ {VIDEORES_1024_768p_85HZ, 1024,768,85,0, 315450, 319898, 390, 396, 25, 29},
++ {VIDEORES_1280_768p_85HZ, 1280,768,85,0, 315423, 319871, 391, 396, 29, 33},
++ {VIDEORES_1280_1024p_85HZ, 1280,1024,85,0, 315350, 319796, 294, 298, 26, 30},
++
++ /* Other resolutions */
++ {VIDEORES_720_240p_60HZ_M1, 720,240,60,0, 446017, 452305, 1702, 1726, 122, 126},
++ {VIDEORES_720_240p_60HZ_M2, 720,240,60,0, 447723, 454035, 1702, 1726, 122, 126},
++ {VIDEORES_720_288p_50HZ_M1, 720,288,50,0, 535390, 542938, 1716, 1740, 124, 128},
++ {VIDEORES_720_288p_50HZ_M2, 720,288,50,0, 537106, 544678, 1716, 1740, 124, 128},
++ {VIDEORES_720_288p_50HZ_M3, 720,288,50,0, 538822, 546419, 1716, 1740, 124, 128},
++ {VIDEORES_1360_768p_60HZ, 1360,768,60,0, 446760, 453059, 562, 570, 33, 37},
++ {VIDEORES_1400_1050p_60HZ, 1400,1050,60,0, 447036, 453338, 411, 416, 30, 34},
++ {VIDEORES_1400_1050p_60HZ_RB, 1400,1050,60,0, 447260, 453565, 414, 420, 7, 11},
++
++ {VIDEORES_1024_768p_70HZ, 1024,768,70,0, 382656, 388051, 475, 481, 47, 51},
++ {VIDEORES_640_480p_72HZ, 640,480,72,0, 368255, 373447, 708, 718, 32, 36},
++ {VIDEORES_800_600p_72HZ, 800,600,72,0, 371423, 376660, 558, 566, 63, 67},
++
++ {VIDEORES_640_350p_85HZ, 640,350,85,0, 315142, 319585, 708, 718, 53, 57},
++ {VIDEORES_640_400p_85HZ, 640,400,85,0, 315142, 319585, 708, 718, 53, 57},
++ {VIDEORES_720_400p_85HZ, 720,400,85,0, 315294, 319740, 707, 717, 53, 57}
++};
++
++/* Platform Data */
++struct tda1997x_platform_data {
++
++ /* Misc */
++ char hdcp; /* enable HDCP */
++ char external_edid; /* use external EDID */
++ char ddc_slave; /* DDC i2c slave address */
++
++ /* Audio */
++ tda1997x_audiofmt_t audout_format; /* output data format */
++ tda1997x_audiosysclk_t audout_sysclk; /* clock config */
++ tda1997x_audiolayout_t audout_layout; /* physical bus layout */
++ bool audio_force_channel_assignment; /* use AUD IF info if unset */
++ bool audio_auto_mute; /* enable hardware audio auto-mute */
++ bool audout_invert_clk; /* data valid on rising edge of BCLK */
++
++ /* Video */
++ tda1997x_videofmt_t vidout_format; /* video output data format */
++ bool vidout_blc; /* insert blanking codes (SAV/EAV) */
++ bool vidout_trc; /* insert timing codes */
++ tda1997x_videoclkmode_t vidout_clkmode; /* clock mode */
++ /* pin polarity (1=invert) */
++ bool vidout_invert_de;
++ bool vidout_invert_hs;
++ bool vidout_invert_vs;
++ /* clock delays (0=-8, 1=-7 ... 15=+7 pixels) */
++ char vidout_delay_hs;
++ char vidout_delay_vs;
++ char vidout_delay_de;
++ char vidout_delay_clk;
++ /* sync selections (controls how sync pins are derived) */
++ tda1997x_sync_output_hs_t vidout_sel_hs;
++ tda1997x_sync_output_vs_t vidout_sel_vs;
++ tda1997x_sync_output_de_t vidout_sel_de;
++ /* Video port configs */
++ u8 vidout_port_config[9];
++ u8 vidout_port_config_no;
++ /* Max pixel rate (MP/sec) */
++ int max_pixel_rate;
++};
++
++/**
++ * Maintains the information on the current state of the chip
++ */
++struct tda1997x_data {
++ struct i2c_client *client;
++ struct i2c_client *client_cec;
++ char page;
++ struct work_struct work;
++ int irq;
++ tda1997x_state_t state;
++ tda1997x_input_t input;
++ spinlock_t lock;
++ struct tda1997x_platform_data *pdata;
++ struct mutex page_lock;
++ struct mutex cec_lock;
++
++ /* detected info from chip */
++ int chip;
++ int chip_version;
++ int chip_revision;
++ char eess_detected;
++ char hdmi_detected;
++ char hdcp_detected;
++ char internal_edid;
++ char port_30bit;
++ char output_2p5;
++ char tmdsb_clk;
++ char tmdsb_soc;
++ char cec_enabled;
++ char cec_slave;
++
++ /* status info */
++ char hdmi_status;
++ char vsi_received;
++ char mptrw_in_progress;
++ char state_c5_reached;
++ char activity_status_reg;
++ char input_detect[2];
++ char vendor[12];
++ char product[18];
++ u16 key_decryption_seed;
++
++ /* video source */
++ tda1997x_colorspace_t colorspace;
++ tda1997x_colorimetry_t colorimetry;
++ tda1997x_restype_t resolutiontype;
++
++ /* video source and output format */
++ tda1997x_vidout_fmt_t video_mode;
++
++ /* audio source */
++ u8 channel_assignment;
++ int source_channels;
++
++ /* audio output format */
++ tda1997x_audout_fmt_t audio_mode;
++};
++
++#ifdef DEBUG
++/* kernel parameters */
++static int debug = 0;
++module_param(debug, int, 0644);
++MODULE_PARM_DESC(debug, "Debug level");
++
++#define DPRINTK(x, fmt, args...) { if (debug>=x) printk(KERN_DEBUG fmt, ## args); }
++
++/* HPD modes */
++const char *hpd_names[] = {
++ "HPD_LOW",
++ "HPD_LOW_OTHER",
++ "HPD_HIGH",
++ "HPD_HIGH_OTHER",
++ "HPD_PULSE",
++};
++
++/* Audio output port layout (hardware pins) */
++const char *audlayout_names[] = {
++ "AUDIO_LAYOUT_AUTO",
++ "AUDIO_LAYOUT_0",
++ "AUDIO_LAYOUT_1",
++};
++
++/* Audio format */
++const char *audfmt_names[] = {
++ "AUDIO_FMT_I2S16",
++ "AUDIO_FMT_I2S32",
++ "AUDIO_FMT_SPDIF",
++ "AUDIO_FMT_OBA",
++ "AUDIO_FMT_I2S16_HBR_STRAIGHT",
++ "AUDIO_FMT_I2S16_HBR_DEMUX",
++ "AUDIO_FMT_I2S32_HBR_DEMUX",
++ "AUDIO_FMT_SPDIF_HBR_DEMUX",
++ "AUDIO_FMT_DST",
++};
++#else
++#define DPRINTK(x, fmt, args...)
++#endif
++
++static struct tda1997x_data tda1997x_data;
++
++static int tda1997x_manual_hpd(struct tda1997x_data *tda1997x, hpdmode_t mode);
++
++/** API for CEC
++ */
++int tda1997x_cec_read(u8 reg)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ int val;
++
++ mutex_lock(&tda1997x->cec_lock);
++ val = i2c_smbus_read_byte_data(tda1997x_data.client_cec, reg);
++ if (val < 0) {
++ dev_dbg(&tda1997x_data.client_cec->dev,
++ "%s:read reg error: reg=%2x\n", __func__, reg);
++ val = -1;
++ }
++
++ mutex_unlock(&tda1997x->cec_lock);
++ return val;
++}
++EXPORT_SYMBOL(tda1997x_cec_read);
++
++int tda1997x_cec_write(u8 reg, u8 val)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ int ret = 0;
++
++ mutex_unlock(&tda1997x->cec_lock);
++ ret = i2c_smbus_write_byte_data(tda1997x_data.client_cec, reg, val);
++ if (ret < 0) {
++ dev_dbg(&tda1997x_data.client_cec->dev,
++ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
++ reg, val);
++ ret = -1;
++ }
++ mutex_unlock(&tda1997x->cec_lock);
++
++ return ret;
++}
++EXPORT_SYMBOL(tda1997x_cec_write);
++
++/** API for MFD children
++ */
++
++/** get current state
++ */
++tda1997x_state_t
++tda1997x_get_state(void)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ tda1997x_state_t state;
++ unsigned long flags;
++
++ dev_dbg(&tda1997x_data.client->dev, "%s\n", __func__);
++ spin_lock_irqsave(&tda1997x->lock, flags);
++ state = tda1997x->state;
++ spin_unlock_irqrestore(&tda1997x->lock, flags);
++
++ return state;
++}
++EXPORT_SYMBOL(tda1997x_get_state);
++
++int
++tda1997x_get_vidout_fmt(tda1997x_vidout_fmt_t *fmt)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ unsigned long flags;
++
++ dev_dbg(&tda1997x_data.client->dev, "%s\n", __func__);
++ spin_lock_irqsave(&tda1997x->lock, flags);
++ memcpy(fmt, &(tda1997x->video_mode), sizeof(*fmt));
++ fmt->sensor_vidfmt = tda1997x->pdata->vidout_format;
++ fmt->sensor_clkmode = tda1997x->pdata->vidout_clkmode;
++ spin_unlock_irqrestore(&tda1997x->lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(tda1997x_get_vidout_fmt);
++
++int
++tda1997x_get_audout_fmt(tda1997x_audout_fmt_t *fmt)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ unsigned long flags;
++
++ dev_dbg(&tda1997x_data.client->dev, "%s\n", __func__);
++ spin_lock_irqsave(&tda1997x->lock, flags);
++ memcpy(fmt, &(tda1997x->audio_mode), sizeof(*fmt));
++ spin_unlock_irqrestore(&tda1997x->lock, flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(tda1997x_get_audout_fmt);
++
++
++/***********************************************************************
++ * I2C transfer
++ ***********************************************************************/
++
++/** set the current page
++ *
++ * @param page number
++ * @returns 0 if success, an error code otherwise.
++ */
++static int tda1997x_setpage(u8 page) {
++ int ret;
++
++ if (tda1997x_data.page != page) {
++ ret = i2c_smbus_write_byte_data(tda1997x_data.client,
++ REG_CURPAGE_00H, page);
++ if (ret < 0) {
++ dev_dbg(&tda1997x_data.client->dev,
++ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
++ REG_CURPAGE_00H, page);
++ return -1;
++ }
++ tda1997x_data.page = page;
++ }
++ return 0;
++}
++
++/** Read one register from a tda1997x i2c slave device.
++ *
++ * @param reg register in the device we wish to access.
++ * high byte is page, low byte is reg
++ * @returns 0 if success, an error code otherwise.
++ */
++static inline int io_read(u16 reg)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ int val;
++
++ /* page 80 denotes CEC reg which needs to go out cec_client */
++ BUG_ON(reg>>8 == 0x80);
++
++ mutex_lock(&tda1997x->page_lock);
++ if (tda1997x_setpage(reg>>8)) {
++ val = -1;
++ goto out;
++ }
++
++ val = i2c_smbus_read_byte_data(tda1997x_data.client, reg&0xff);
++ if (!(reg == REG_INT_FLG_CLR_TOP && val == 0x00)) {
++ DPRINTK(3, "<< 0x%04x=0x%02x\n", reg, val);
++ }
++ if (val < 0) {
++ dev_dbg(&tda1997x_data.client->dev,
++ "%s:read reg error: reg=%2x\n", __func__, reg&0xff);
++ val = -1;
++ goto out;
++ }
++
++out:
++ mutex_unlock(&tda1997x->page_lock);
++ return val;
++}
++/* 16bit read */
++static inline long io_read16(u16 reg)
++{
++ u8 val;
++ long lval = 0;
++
++ if ( (val = io_read(reg)) < 0)
++ return -1;
++ lval |= (val<<8);
++ if ( (val = io_read(reg+1)) < 0)
++ return -1;
++ lval |= val;
++
++ return lval;
++}
++/* 24bit read */
++static inline long io_read24(u16 reg)
++{
++ u8 val;
++ long lval = 0;
++
++ if ( (val = io_read(reg)) < 0)
++ return -1;
++ lval |= (val<<16);
++ if ( (val = io_read(reg+1)) < 0)
++ return -1;
++ lval |= (val<<8);
++ if ( (val = io_read(reg+2)) < 0)
++ return -1;
++ lval |= val;
++
++ return lval;
++}
++/* n-byte read */
++static unsigned int io_readn(u16 reg, u8 len, u8 *data)
++{
++ int i;
++ int sz = 0;
++ u8 val;
++
++ for (i = 0; i < len; i++) {
++ if ( (val = io_read(reg + i)) < 0)
++ break;
++ data[i] = val;
++ sz++;
++ }
++
++ return sz;
++}
++
++/** Write one register of a tda1997x i2c slave device.
++ *
++ * @param reg register in the device we wish to access.
++ * high byte is page, low byte is reg
++ * @returns 0 if success, an error code otherwise.
++ */
++static int io_write(u16 reg, u8 val)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ s32 ret = 0;
++
++ /* page 80 denotes CEC reg which needs to go out cec_client */
++ BUG_ON(reg>>8 == 0x80);
++
++ mutex_lock(&tda1997x->page_lock);
++ if (tda1997x_setpage(reg>>8)) {
++ ret = -1;
++ goto out;
++ }
++
++ DPRINTK(3, ">> 0x%04x=0x%02x\n", reg, val);
++ ret = i2c_smbus_write_byte_data(tda1997x_data.client, reg&0xff, val);
++ if (ret < 0) {
++ dev_dbg(&tda1997x_data.client->dev,
++ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
++ reg&0xff, val);
++ ret = -1;
++ goto out;
++ }
++
++out:
++ mutex_unlock(&tda1997x->page_lock);
++ return ret;
++}
++/* 16bit write */
++static int io_write16(u16 reg, u16 val)
++{
++ if (io_write(reg, (val>>8)&0xff) < 0)
++ return -1;
++ if (io_write(reg+1, val&0xff) < 0)
++ return -1;
++ return 0;
++}
++/* 24bit write */
++static int io_write24(u16 reg, u32 val)
++{
++ if (io_write(reg, (val>>16)&0xff) < 0)
++ return -1;
++ if (io_write(reg+1, (val>>8)&0xff) < 0)
++ return -1;
++ if (io_write(reg+2, val&0xff) < 0)
++ return -1;
++ return 0;
++}
++/* n-byte write */
++static unsigned int io_writen(u16 reg, u8 len, u8 *data)
++{
++ int i;
++ int sz = 0;
++
++ for (i = 0; i < len; i++) {
++ io_write(reg + i, data[i]);
++ sz++;
++ }
++
++ return sz;
++}
++
++
++/***********************************************************************
++ * EDID
++ ***********************************************************************/
++
++/* Modified from the NXP exapp71a application for Ventana */
++u8 edid_block[256] = {
++ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
++ 0x1e, 0xe3, 0x00, 0x50, 0x01, 0x00, 0x00, 0x00,
++ 0x01, 0x17, 0x01, 0x03, 0xa2, 0x00, 0x00, 0x00,
++ 0x02, 0xee, 0x95, 0xa3, 0x54, 0x4c, 0x99, 0x26,
++ 0x0f, 0x50, 0x54, 0x20, 0x00, 0x00, 0x01, 0x01,
++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
++ 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
++ 0x45, 0x00, 0xc4, 0x8e, 0x21, 0x00, 0x00, 0x1e,
++ 0x00, 0x00, 0x00, 0xfc, 0x00, 0x47, 0x57, 0x20,
++ 0x56, 0x65, 0x6e, 0x74, 0x61, 0x6e, 0x61, 0x0a,
++ 0x20, 0x20, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x1e,
++ 0x3c, 0x0f, 0x44, 0x09, 0x00, 0x0a, 0x20, 0x20,
++ 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfe,
++ 0x00, 0x31, 0x30, 0x38, 0x30, 0x70, 0x44, 0x43,
++ 0x78, 0x76, 0x43, 0x33, 0x44, 0x0a, 0x01, 0x89,
++ 0x02, 0x03, 0x21, 0xf0, 0x4c, 0x22, 0x20, 0x21,
++ 0x04, 0x13, 0x03, 0x12, 0x05, 0x14, 0x07, 0x16,
++ 0x01, 0x23, 0x09, 0x07, 0x07, 0x83, 0x01, 0x00,
++ 0x00, 0x67, 0x03, 0x0c, 0x00, 0x00, 0x00, 0xb8,
++ 0x2d, 0x01, 0x1d, 0x80, 0x18, 0x71, 0x38, 0x2d,
++ 0x40, 0x58, 0x2c, 0x45, 0x00, 0x80, 0x38, 0x74,
++ 0x00, 0x00, 0x3f, 0x01, 0x1d, 0x00, 0x72, 0x51,
++ 0xd0, 0x1e, 0x20, 0x6e, 0x50, 0x55, 0x00, 0x00,
++ 0xd0, 0x52, 0x00, 0x00, 0x39, 0xa0, 0x0f, 0x20,
++ 0x00, 0x31, 0x58, 0x1c, 0x20, 0x28, 0x80, 0x14,
++ 0x00, 0x20, 0x58, 0x32, 0x00, 0x00, 0x3f, 0xd7,
++ 0x09, 0x80, 0xa0, 0x20, 0xe0, 0x2d, 0x10, 0x08,
++ 0x60, 0x22, 0x01, 0x80, 0xe0, 0x21, 0x00, 0x00,
++ 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
++};
++
++/* DDC config 0 (page 0x20) */
++u8 ddc_config0[8] = {
++ /* 0x80: EDID_VERSION */
++ 0x19, /* main=0x19 */
++
++ /* 0x81: EDID_ENABLE bits:
++ * 7 - unused
++ * 6 - edid_only
++ * 5:2 - unused
++ * 1 - edid_b_en
++ * 0 - edid_a_en
++ */
++ 0x41, /* enable EDID for A only */
++
++ /* 0x82: EDID_BLOCK_SELECT bits:
++ * 7:6 - ddc_b_blk1_sel
++ * 5:4 - ddc_b_blk0_sel
++ * 3:2 - ddc_a_blk1_sel
++ * 1:0 - ddc_a_blk0_sel
++ */
++ 0x44, /* ddc_b_blk1_sel=1 ddc_a_blk1_sel=1 */
++
++ /* 0x83: empty */
++ 0x00,
++
++ /* 0x84: HPD_POWER bits:
++ * 7:5 - unused
++ * 4:3 - hpd_bp
++ * 2 - hpd_edid_only
++ * 1:0 - unused
++ */
++ 0x06, /* hpd_bp=1 hpd_edid_only=1 */
++
++ /* 0x85: HPD_AUTO_CTRL bits
++ * 7 - read_edid
++ * 6 - unused
++ * 5 - hpd_f3tech
++ * 4 - hpd_other
++ * 3 - hpd_unsel
++ * 2 - hpd_all_ch
++ * 1 - hpd_prv_ch
++ * 0 - hpd_new_ch
++ */
++ 0x18, /* hpd_other=1, hdp_unsel=1 */
++
++ /* 0x86: HPD_DURATION */
++ 0x00, /* hpd_duration=0 */
++
++ /* 0x87: RX_HPD_HEAC bits
++ * 7:2 - unused
++ * 1 - heac_b_en
++ * 0 - heac_a_en
++ */
++ 0x00,
++};
++
++/* RT config (page 0x30) */
++u8 rt_config[6] = {
++ /* 0x00: RT_AUTO_CTRL bits:
++ * 7 - unused
++ * 6 - rt_other
++ * 5 - rt_hpd_low
++ * 4 - rt_no_5v
++ * 3 - rt_unsel
++ * 2 - rt_all_ch
++ * 1 - rt_prv_ch
++ * 0 - rt_new_ch
++ */
++ 0x78,
++
++ /* 0x01: EQ_MAN_CTRL0 bits:
++ * 7-3 - unused
++ * 2-0 - ch0_man_gain
++ */
++ 0x03, /* ch0_man_gain=3 */
++
++ /* 0x02: EQ_MAN_CTRL1 bits:
++ * 7 - unused
++ * 6-4 - ch1_man_gain
++ * 3 - unused
++ * 2-0 - ch2_man_gain
++ */
++ 0x33, /* ch1_man_gain=3 ch2_man_gain=3 */
++
++ /* 0x03: OUTPUT_CFG bits
++ * 7 - eq_cal_act
++ * 6 - eq_cal_ch
++ * 5 - eq_cal_5v
++ * 4 - eq_cal_cond
++ * 3 - unused
++ * 2 - out_idle
++ * 1 - ap_idle
++ * 0 - vp_idle
++ */
++ 0xf0, /* eq_cal_act=1 eq_cal_ch=1 eq_cal_5v=1 eq_cal_cond=1 */
++
++ /* 0x04: MUTE_CTRL bits
++ * 7:3 - unused
++ * 2 - mute_man
++ * 1 - mute_pol
++ * 0 - mute_ena
++ */
++ 0x00,
++
++ /* 0x05: SLAVE_ADDR bits
++ * 7:6 - unused
++ * 5 - i2c_cec_a1
++ * 4 - i2c_cec_a0
++ * 3 - unused
++ * 2 - i2c_a2
++ * 1 - i2c_a1
++ * 0 - i2c_a0
++ */
++ 0x10, /* i2c_cec_a0=1 */
++};
++
++static u32 reg = 0;
++
++/** Loads EDID data into embedded EDID memory of receiver device
++ * @edid - pointer to two block EDID (array of 256 bytes) common to both inputs
++ *
++ * A common EDID block is used for both inputs with the exception of the
++ * SPA (Source Physical Address) used for CEC. Therefore, we locate the SPA
++ * within the EDID passed and treating it as the SPA for InputA while adding
++ * 1 to it for the SPA for InputB. The EDID is written into nvram as well
++ * as the SPA offset, SPA's and adjusted checksums for both inputs.
++ */
++static int tda1997x_load_edid_data(u8 *edid)
++{
++ u8 chksum, chksum_spa;
++ int i, n, spa_offset = 0;
++ u16 spa;
++
++ DPRINTK(0,"%s\n", __func__);
++
++ /* sanity check EDID data: base block, extensions, checksums */
++ if (!drm_edid_is_valid((struct edid *) edid)) {
++ printk(KERN_ERR "edid data is invalid\n");
++ return -EINVAL;
++ }
++ if (edid[0x7e] != 1) {
++ printk(KERN_ERR "edid requires a single CEA extension block\n");
++ return -EINVAL;
++ }
++
++ /* Find SPA offset within CEA extentsion */
++ for (i = 1; i <= edid[0x7e]; i++) {
++ u8 *ext = edid + (i * EDID_LENGTH);
++
++ /* look for CEA v3 extension */
++ if (ext[0] != 0x02 || ext[1] != 0x03)
++ continue;
++
++ /* make sure we have a DBC */
++ if (ext[2] < 5)
++ continue;
++
++ /* iterate through DBC's until we find the Vendor block */
++ for (n = 4; n < ext[2]; n++) {
++ char type = (ext[n] & 0xe0) >> 5;
++ char len = (ext[n] & 0x1f);
++ if (type == 3) {
++ if (ext[n+1] == 0x03 && ext[n+2] == 0x0c) {
++ spa_offset = n+4;
++ spa = ext[spa_offset] << 8 |
++ ext[spa_offset+1];
++ }
++ }
++ n += len;
++ }
++ }
++ if (!spa_offset) {
++ printk(KERN_ERR
++ "EDID requires an HDMI Vendor Specific Data Block\n");
++ return -EINVAL;
++ }
++
++ /* calculate ext block checksum w/o SPA */
++ chksum = 0;
++ for (i = 0; i < 127; i++)
++ if (i != spa_offset && i != (spa_offset + 1))
++ chksum += edid[i+128];
++
++ /* write base EDID */
++ for (i = 0; i < 128; i++)
++ io_write(REG_EDID_IN_BYTE0 + i, edid[i]);
++
++ /* write CEA Extension */
++ for (i = 0; i < 128; i++)
++ io_write(REG_EDID_IN_BYTE128 + i, edid[i+128]);
++
++ /* SPA for InputA */
++ io_write16(REG_EDID_IN_SPA_AB_A, spa);
++ chksum_spa = (u8)((spa & 0xff00)>>8) + (u8)(spa & 0x00ff) + chksum;
++ chksum_spa = (u8)((0xff - chksum_spa) + 0x01); /* 2's complement */
++ io_write(REG_EDID_IN_CKSUM_A, chksum_spa);
++
++ /* SPA for InputB */
++ spa += 1;
++ io_write16(REG_EDID_IN_SPA_AB_B, spa);
++ chksum_spa = (u8)((spa & 0xff00)>>8) + (u8)(spa & 0x00ff) + chksum;
++ chksum_spa = (u8)((0xff - chksum_spa) + 0x01); /* 2's comp */
++ io_write(REG_EDID_IN_CKSUM_B, chksum_spa);
++
++ /* write source physical address subaddress offset */
++ io_write(REG_EDID_IN_SPA_SUB, spa_offset);
++
++ return 0;
++}
++
++/*
++ * sysfs hooks
++ */
++static ssize_t b_show(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ int rz = 0;
++ const char *name = attr->attr.name;
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ unsigned long flags;
++ const char *sname = "";
++
++ spin_lock_irqsave(&tda1997x->lock, flags);
++ if (strcasecmp(name, "state") == 0) {
++ switch(tda1997x->state) {
++ case STATE_NOT_INITIALIZED: sname = "not initialized"; break;
++ case STATE_INITIALIZED: sname = "initalized"; break;
++ case STATE_LOCKED: sname = "locked"; break;
++ case STATE_UNLOCKED: sname = "unlocked"; break;
++ case STATE_CONFIGURED: sname = "configured"; break;
++ }
++ rz = sprintf(buf, "%s\n", sname);
++ }
++ else if (strcasecmp(name, "vidmode") == 0) {
++ if (tda1997x->state == STATE_LOCKED) {
++ rz = sprintf(buf, "%dx%d%c@%dHz\n",
++ tda1997x->video_mode.width, tda1997x->video_mode.height,
++ (tda1997x->video_mode.interlaced)?'i':'p',
++ tda1997x->video_mode.fps);
++ } else
++ rz = sprintf(buf, "no signal\n");
++ } else if (strcasecmp(name, "colorspace") == 0) {
++ rz = sprintf(buf, "%s %s\n",
++ colorspace_names[tda1997x->colorspace],
++ colorimetry_names[tda1997x->colorimetry]);
++ } else if (strcasecmp(name, "audmode") == 0) {
++ if (tda1997x->state == STATE_LOCKED) {
++ rz = sprintf(buf, "%dHz\n", tda1997x->audio_mode.samplerate);
++ } else
++ rz = sprintf(buf, "no signal\n");
++ } else if (strcasecmp(name, "vendor") == 0) {
++ rz = sprintf(buf, "%s\n", tda1997x->vendor);
++ } else if (strcasecmp(name, "product") == 0) {
++ rz = sprintf(buf, "%s\n", tda1997x->product);
++ } else if (strcasecmp(name, "info") == 0) {
++ rz = sprintf(buf, "%s%s%s\n",
++ (tda1997x->hdmi_detected)?"HDMI ":"",
++ (tda1997x->eess_detected)?"EESS ":"",
++ (tda1997x->hdcp_detected)?"HDCP ":"");
++ } else if (strcasecmp(name, "edid") == 0) {
++ for (rz = 0; rz < sizeof(edid_block); rz++)
++ buf[rz] = edid_block[rz];
++ } else if (strcasecmp(name, "reg") == 0) {
++ rz = sprintf(buf, "%02x\n", io_read(reg) );
++ printk(KERN_INFO "TDA1997x-core: Register 0x%04x=%s\n", reg, buf);
++ } else {
++ rz = sprintf(buf, "invalid attr\n");
++ }
++ spin_unlock_irqrestore(&tda1997x->lock, flags);
++
++ return rz;
++}
++
++static ssize_t b_store(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ u32 val = 0;
++ const char *name = attr->attr.name;
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ int i;
++
++
++ if (strcasecmp(name, "edid") == 0) {
++ for (i = 0; i < count; i++)
++ edid_block[i] = buf[i];
++ printk(KERN_INFO "TDA1997x-core: New EDID being loaded\n");
++ /* Set HPD low */
++ tda1997x_manual_hpd(tda1997x, HPD_LOW);
++ tda1997x_load_edid_data(edid_block);
++ /* Set HPD high (now that EDID is ready) */
++ tda1997x_manual_hpd(tda1997x, HPD_HIGH);
++ } else if (strcasecmp(name, "reg") == 0) {
++ i = sscanf(buf, "%x %x", &reg, &val);
++ if (i == 2) {
++ io_write( (u16)reg, (u8)val);
++ printk(KERN_INFO "TDA1997x-core: Register 0x%04x=0x%02x\n", reg, val);
++ } else {
++ printk(KERN_INFO "TDA1997x-core: Register 0x%04x\n", reg);
++ }
++ } else {
++ printk(KERN_ERR "invalid name '%s'\n", attr->attr.name);
++ }
++
++ return count;
++}
++
++/*
++ * Create a group of attributes so that we can create and destory them all
++ * at once.
++ */
++static struct device_attribute attr_state =
++ __ATTR(state, 0660, b_show, b_store);
++static struct device_attribute attr_vidmode =
++ __ATTR(vidmode, 0660, b_show, NULL);
++static struct device_attribute attr_audmode =
++ __ATTR(audmode, 0660, b_show, NULL);
++static struct device_attribute attr_vendor =
++ __ATTR(vendor, 0660, b_show, NULL);
++static struct device_attribute attr_product =
++ __ATTR(product, 0660, b_show, NULL);
++static struct device_attribute attr_info =
++ __ATTR(info, 0660, b_show, NULL);
++static struct device_attribute attr_edid =
++ __ATTR(edid, 0770, b_show, b_store);
++static struct device_attribute attr_colorspace =
++ __ATTR(colorspace, 0660, b_show, NULL);
++static struct device_attribute attr_reg =
++ __ATTR(reg, 0660, b_show, b_store);
++
++static struct attribute *tda1997x_attrs[] = {
++ &attr_state.attr,
++ &attr_vidmode.attr,
++ &attr_audmode.attr,
++ &attr_vendor.attr,
++ &attr_product.attr,
++ &attr_info.attr,
++ &attr_edid.attr,
++ &attr_colorspace.attr,
++ &attr_reg.attr,
++ NULL
++};
++
++static struct attribute_group attr_group = {
++ .attrs = tda1997x_attrs,
++};
++
++/** Loads DDC and RT configuration data into embedded memory of receiver device
++ * @ddc_config - pointer to the DDC block configuration (8 bytes)
++ * @rt_config - pointer to the RT block configuration (6 bytes)
++ */
++static int tda1997x_load_config_data(struct tda1997x_data *tda1997x,
++ const u8 *ddc, const u8 *rt)
++{
++ int i;
++
++ if (!tda1997x->internal_edid)
++ return -EPERM;
++
++ /* DDC to page 20h */
++ for (i = 0; i < 8; i++)
++ io_write(REG_EDID_IN_VERSION + i, ddc[i]);
++ /* RT to page 30h */
++ for (i = 0; i < 6; i++)
++ io_write(REG_RT_AUTO_CTRL + i, rt[i]);
++
++ return 0;
++}
++
++
++/***********************************************************************
++ * Signal Control
++ ***********************************************************************/
++
++/** manual HPD (Hot Plug Detect) control
++ * @param hdp_mode
++ * @returns 0 on success
++ */
++static int tda1997x_manual_hpd(struct tda1997x_data *tda1997x, hpdmode_t mode)
++{
++ u8 hpd_auto, hpd_pwr, hpd_man;
++
++ DPRINTK(0, "%s: %s\n", __func__, hpd_names[mode]);
++
++ /* HPD_POWER bits:
++ * 7:4 - unused
++ * 3:2 - hpd_bp[1:0]
++ * 1 - hpd_edid_only
++ * 0 - unused
++ *
++ * HPD_AUTO_CTRL bits:
++ * 7 - read_edid
++ * 6 - unused
++ * 5 - hpd_f3tech
++ * 4 - hp_other
++ * 3 - hpd_unsel
++ * 2 - hpd_all_ch
++ * 1 - hpd_prv_ch
++ * 0 - hpd_new_ch
++ *
++ * HPD_MAN bits:
++ * 7 - ?
++ * 6-3 - unused
++ * 2:0 - man_gain
++ */
++ hpd_auto = io_read(REG_HPD_AUTO_CTRL);
++ hpd_pwr = io_read(REG_HPD_POWER);
++ hpd_man = io_read(REG_HPD_MAN_CTRL);
++ hpd_man &= 0x87;
++
++ switch(mode) {
++ /* HPD low and pulse of at least 100ms */
++ case HPD_LOW:
++ hpd_man &= ~0x03; /* man_gain=0 */
++ hpd_pwr &= ~0x0c; /* hpd_bp=0 */
++ io_write(REG_HPD_POWER, hpd_pwr);
++ io_write(REG_HPD_MAN_CTRL, hpd_man);
++ break;
++ /* HPD high */
++ case HPD_HIGH:
++ /* hpd_bp=1 */
++ hpd_pwr = (hpd_pwr & ~0x0c) | 0x04;
++ io_write(REG_HPD_POWER, hpd_pwr);
++ break;
++ /* HPD low and pulse of at least 100ms */
++ case HPD_LOW_OTHER:
++ hpd_man &= ~0x03; /* man_gain=0 */
++ hpd_auto &= ~0x10; /* hp_other=0 */
++ io_write(REG_HPD_AUTO_CTRL, hpd_auto);
++ io_write(REG_HPD_MAN_CTRL, hpd_man);
++ break;
++ /* HPD high */
++ case HPD_HIGH_OTHER:
++ hpd_auto |= 0x10; /* hp_other=1 */
++ io_write(REG_HPD_AUTO_CTRL, hpd_auto);
++ break;
++ /* HPD low pulse */
++ case HPD_PULSE:
++ hpd_man &= ~0x03; /* man_gain=0 */
++ /* write HPD_MAN to have HPD low pulse */
++ io_write(REG_HPD_MAN_CTRL, hpd_man);
++ break;
++ }
++
++ return 0;
++}
++
++/** configure the receiver with the new colorspace
++ * @returns 0 on success
++ * colorspace conversion depends on input format and output format
++ * blanking codes depend on the output colorspace
++ */
++static int tda1997x_configure_conversion(struct tda1997x_data *tda1997x,
++ tda1997x_colorspace_t colorspace, tda1997x_colorimetry_t colorimetry,
++ tda1997x_videofmt_t vidout_format)
++{
++ colormatrixcoefs_t *pCoefficients = NULL;
++ blankingcodes_t *pBlankingCodes = NULL;
++ u8 data[31];
++
++ printk(KERN_INFO "%s: %s %s => %s\n", KBUILD_MODNAME,
++ colorspace_names[colorspace],
++ (colorspace == COLORSPACE_RGB) ? "" :
++ colorimetry_names[colorimetry],
++ vidfmt_names[vidout_format]);
++
++ switch (vidout_format) {
++ /* RGB 4:4:4 output */
++ case VIDEOFMT_444:
++ pBlankingCodes = &RGBBlankingCode;
++ if (colorspace != COLORSPACE_RGB) {
++ if (colorimetry == COLORIMETRY_ITU709)
++ pCoefficients = &conversion_matrix[ITU709_RGBLimited];
++ else
++ pCoefficients = &conversion_matrix[ITU601_RGBLimited];
++ }
++ break;
++
++ /* YUV422 output */
++ case VIDEOFMT_422_SMP: /* YUV422 semi-planar */
++ case VIDEOFMT_422_CCIR:/* YUV422 CCIR656 */
++ pBlankingCodes = &YUVBlankingCode;
++ if (colorspace == COLORSPACE_RGB)
++ pCoefficients = &conversion_matrix[RGBLimited_ITU601];
++ break;
++ }
++
++ if (pCoefficients) {
++ s16 *pTabCoeff = &(pCoefficients->offInt1);
++ u8 i, j;
++
++ /* test the range of the coefs */
++ for (i = 0; i < OFFSET_LOOP_NB; i++) {
++ for (j = 0; j < MAT_OFFSET_NB; j++) {
++ if ( (pTabCoeff[j] < MIN_VAL_OFFSET) || pTabCoeff[j] > MAX_VAL_OFFSET)
++ return -EINVAL;
++ }
++ pTabCoeff = &(pCoefficients->offOut1);
++ }
++ pTabCoeff = &(pCoefficients->P11Coef);
++
++ for (i = 0; i < MAT_COEFF_NB; i++) {
++ if ( (pTabCoeff[i] < MIN_VAL_OFFSET) || pTabCoeff[i] > MAX_VAL_OFFSET)
++ return -EINVAL;
++ }
++
++ /* enable matrix conversion by disabling bypass: mat_bp=0 */
++ data[0] = io_read(REG_VDP_CTRL);
++ data[0] &= ~(1<<0);
++ /* offset input 1 value */
++ data[1] = (u8) ((u16)(pCoefficients->offInt1) >> 8);
++ data[2] = (u8) (pCoefficients->offInt1 & MASK_MAT_COEFF_LSB);
++ /* offset input 2 value */
++ data[3] = (u8) ((u16)(pCoefficients->offInt2) >> 8);
++ data[4] = (u8) (pCoefficients->offInt2 & MASK_MAT_COEFF_LSB);
++ /* offset input 3 value */
++ data[5] = (u8) ((u16)(pCoefficients->offInt3) >> 8);
++ data[6] = (u8) (pCoefficients->offInt3 & MASK_MAT_COEFF_LSB);
++ /* Coefficient (1,1) value */
++ data[7] = (u8) ((u16)(pCoefficients->P11Coef) >> 8);
++ data[8] = (u8) (pCoefficients->P11Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (1,2) value */
++ data[9] = (u8) ((u16)(pCoefficients->P12Coef) >> 8);
++ data[10] = (u8) (pCoefficients->P12Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (1,3) value */
++ data[11] = (u8) ((u16)(pCoefficients->P13Coef) >> 8);
++ data[12] = (u8) (pCoefficients->P13Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (2,1) value */
++ data[13] = (u8) ((u16)(pCoefficients->P21Coef) >> 8);
++ data[14] = (u8) (pCoefficients->P21Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (2,2) value */
++ data[15] = (u8) ((u16)(pCoefficients->P22Coef) >> 8);
++ data[16] = (u8) (pCoefficients->P22Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (2,3) value */
++ data[17] = (u8) ((u16)(pCoefficients->P23Coef) >> 8);
++ data[18] = (u8) (pCoefficients->P23Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (3,1) value */
++ data[19] = (u8) ((u16)(pCoefficients->P31Coef) >> 8);
++ data[20] = (u8) (pCoefficients->P31Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (3,2) value */
++ data[21] = (u8) ((u16)(pCoefficients->P32Coef) >> 8);
++ data[22] = (u8) (pCoefficients->P32Coef & MASK_MAT_COEFF_LSB);
++ /* Coefficient (3,3) value */
++ data[23] = (u8) ((u16)(pCoefficients->P33Coef) >> 8);
++ data[24] = (u8) (pCoefficients->P33Coef & MASK_MAT_COEFF_LSB);
++ /* Offset output 1 value */
++ data[25] = (u8) ((u16)(pCoefficients->offOut1) >> 8);
++ data[26] = (u8) (pCoefficients->offOut1 & MASK_MAT_COEFF_LSB);
++ /* Offset output 2 value */
++ data[27] = (u8) ((u16)(pCoefficients->offOut2) >> 8);
++ data[28] = (u8) (pCoefficients->offOut2 & MASK_MAT_COEFF_LSB);
++ /* Offset output 3 value */
++ data[29] = (u8) ((u16)(pCoefficients->offOut3) >> 8);
++ data[30] = (u8) (pCoefficients->offOut3 & MASK_MAT_COEFF_LSB);
++
++ io_writen(REG_VDP_CTRL, 31, data);
++ } else {
++ /* enable matrix conversion bypass (mat_b) */
++ data[0] = io_read(REG_VDP_CTRL);
++ data[0] |= (1<<0); /* mat_bp=1 */
++ io_write(REG_VDP_CTRL, data[0]);
++ }
++
++ /* SetBlankingCodes */
++ if (pBlankingCodes) {
++ io_write16(REG_BLK_GY, pBlankingCodes->blankingCodeGy);
++ io_write16(REG_BLK_BU, pBlankingCodes->blankingCodeBu);
++ io_write16(REG_BLK_RV, pBlankingCodes->blankingCodeRv);
++ }
++
++ return 0;
++}
++
++/** Configure the active input to the given resolution
++ * @param resolution ID
++ * @returns 0 on success
++ */
++static int
++tda1997x_configure_input_resolution(resolutionid_t resolution)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ u8 reg;
++ const resolution_timings_t *timings = NULL;
++ const vhref_values_t *vh;
++ int i;
++
++ DPRINTK(0,"%s\n", __func__);
++
++ /* scan through resolution table looking for a match for timings */
++ for (i = 0; i < ARRAY_SIZE(resolution_timings); i++) {
++ if (resolution == resolution_timings[i].resolutionID)
++ {
++ timings = &resolution_timings[i];
++ vh = &timings->vhref_values;
++ break;
++ }
++ }
++ if (!timings) {
++ printk(KERN_INFO "%s: resolution not supported\n", KBUILD_MODNAME);
++ return -1;
++ }
++
++ /* Configure Frame Detection Window:
++ * define the horizontal area where the VHREF modules consider a VSYNC a
++ * new frame (values typically depend on the video mode being processed
++ */
++ /* start position of the frame detection window */
++ io_write16(REG_FDW_S, 0x2ef & 0x3fff);
++ /* end position of the frame detection window */
++ io_write16(REG_FDW_E, 0x141 & 0x3fff);
++
++ /* Set Pixel And Line Counters */
++ if (tda1997x->chip_revision == 0)
++ /* add 1 line to lineCountPreset */
++ io_write16(REG_PXCNT_PR, (timings->pixCountPreset + 3) & 0x3fff);
++ else
++ io_write16(REG_PXCNT_PR, timings->pixCountPreset & 0x3fff);
++ io_write16(REG_PXCNT_NPIX, timings->pixCountNb & 0x3fff);
++ io_write16(REG_LCNT_PR, timings->lineCountPreset & 0x3fff);
++ io_write16(REG_LCNT_NLIN, timings->lineCountNb & 0x3fff);
++
++ /* Configure VHRef:
++ * configure the VHRef timing generator responsible for rebuilding all
++ * horiz and vert synch and ref signals from its input allowing automatic
++ * detection algorithms and forcing predefined modes (480i & 576i)
++ *
++ * REG_VHREF_CTRL bits:
++ * bit7 - interlaced_det - interlace detect method: 1=alternate,0=framefield
++ * bit6:5 - vsync_type: 0=Auto,1=FDW,2=Even,3=Odd
++ * bit4:3 - std_det: 0=PAL,1=NTSC,2=AUTO,3=OFF
++ * bit2 - href_src - VREF source: 1=from standard, 0=manual
++ * bit1 - href_src - HREF source: 1=from standard, 0=manual
++ * bit0 - hsync_sel - HSYNC signal: 1=HS,0=VS
++ */
++ reg = io_read(REG_VHREF_CTRL);
++ io_write(REG_VHREF_CTRL, 0x3<<3 /* std_det=off */);
++
++ /* Set VHRef:
++ * configure the VHRef timing values. In case the VHREF generator has
++ * been configured in manual mode, this will allow to manually set all horiz
++ * and vert ref values (non-active pixel areas) of the generator
++ * and allows setting the frame reference params. These values typically
++ * depend on the video mode being processed
++ */
++ /* horizontal reference start/end */
++ io_write16(REG_HREF_S, vh->href_start & 0x3fff);
++ io_write16(REG_HREF_E, vh->href_end & 0x3fff);
++ /* vertical reference f1 start/end */
++ io_write16(REG_VREF_F1_S, vh->vref_f1_start & 0x3fff);
++ io_write (REG_VREF_F1_WIDTH, vh->vref_f1_width);
++ /* vertical reference f2 start/end */
++ io_write16(REG_VREF_F2_S, vh->vref_f2_start & 0x3fff);
++ io_write (REG_VREF_F2_WIDTH, vh->vref_f2_width);
++ /* F1/F2 FREF, field polarity */
++ io_write16(REG_FREF_F1_S, (vh->fieldref_f1_start & 0x3fff)
++ || (vh->fieldPolarity<<8));
++ io_write16(REG_FREF_F2_S, vh->fieldref_f2_start & 0x3fff);
++
++ /* set the state machine */
++ tda1997x->state = STATE_CONFIGURED;
++
++ return 0;
++}
++
++/** Configure Audio output formatter
++ * @param pdata with audio output configuration
++ * @param channel_assignment
++ * @returns 0 on success
++ */
++static int
++tda1997x_configure_audio_formatter(struct tda1997x_platform_data *pdata,
++ u8 channel_assignment)
++{
++ u8 fifo_latency = 0x80;
++ bool sp_used_by_fifo = 0;
++ bool ws_active = 0;
++ u8 reg;
++
++ DPRINTK(0,"%s: %s %s channel_assignment=%d enable_auto_mute=%d\n", __func__,
++ audlayout_names[pdata->audout_layout],
++ audfmt_names[pdata->audout_format],
++ channel_assignment, pdata->audio_auto_mute);
++
++ /* AUDIO_PATH bits:
++ * 7:0 - channel assignment (CEA-861-D Table 20)
++ */
++ io_write(REG_AUDIO_PATH, channel_assignment);
++
++ /* AUDIO_SEL bits:
++ * 7 - aclk_inv - Polarity of clock signal on A_CLK pin (1=invert)
++ * 6 - test_tone - Audio test tone generator (1=on)
++ * 5 - i2s_spdif - Selection of audio output format (0=I2S, 1=SPDIF)
++ * 4 - i2s_32 - Size of I2S samples (0=16bit, 1=32bit)
++ * 3 - hwmute_ena - Automatic audio mute (1=enabled)
++ * 2 - hbr_demux - High Bit Rate output mode:
++ * 0:straight via AP0
++ * 1:demuxed via AP0,AP1,AP2,AP3
++ * 1:0 - audio_type - Selection of audio output packet mode
++ * 00: Audio samples
++ * 01: High-Bit Rate (HBR)
++ * 10: One Bit Audio (OBA)
++ * 11: Direct Stream Transfer (DST)
++ */
++ reg = io_read(REG_AUDIO_SEL);
++ if (pdata->audio_auto_mute)
++ reg |= 1<<3;
++ else
++ reg &= ~(1<<3);
++ switch(pdata->audout_format) {
++ case AUDIO_FMT_I2S16:
++ /* 16bit I2S mode, SP flag used by FIFO */
++ reg &= ~(1<<4);
++ reg &= ~(1<<5);
++ sp_used_by_fifo = 1;
++ ws_active = 1;
++ break;
++ case AUDIO_FMT_I2S32:
++ /* 32bit I2S mode, SP flag used by FIFO */
++ reg |= (1<<4);
++ reg &= ~(1<<5);
++ sp_used_by_fifo = 1;
++ ws_active = 1;
++ break;
++ case AUDIO_FMT_OBA:
++ /* One Bit Audio */
++ reg &= ~(1<<5);
++ sp_used_by_fifo = 1;
++ ws_active = 1;
++ break;
++ case AUDIO_FMT_SPDIF: /* SPDIF */
++ /* SPDIF mode, SP flag used by FIFO */
++ reg |= (1<<5);
++ sp_used_by_fifo = 1;
++ break;
++ case AUDIO_FMT_I2S16_HBR_DEMUX:
++ /* 16bit I2S High Bit Rate demux */
++ reg &= ~(1<<4);
++ reg &= ~(1<<5);
++ sp_used_by_fifo = 1;
++ ws_active = 1;
++ break;
++ case AUDIO_FMT_I2S32_HBR_DEMUX:
++ /* 32bit I2S High Bit Rate demux */
++ reg |= (1<<4);
++ reg &= ~(1<<5);
++ sp_used_by_fifo = 1;
++ ws_active = 1;
++ break;
++ case AUDIO_FMT_DST:
++ /* Direct Stream Transfer */
++ sp_used_by_fifo = 0;
++ break;
++ case AUDIO_FMT_SPDIF_HBR_DEMUX:
++ /* SPDIF High Bit Rate demux */
++ reg |= (1<<5);
++ sp_used_by_fifo = 0;
++ break;
++ default:
++ break;
++ }
++ /* Clock polarity */
++ reg &= ~(1<<7);
++ if (pdata->audout_invert_clk)
++ reg |= 1<<7;
++ io_write(REG_AUDIO_SEL, reg);
++
++ /* AUDIO_LAYOUT bits:
++ * 2 - sp_flag :
++ * 0 - sp flag ignored by FIFO-control (4 subpackets written in FIFO)
++ * 1 - sp flag used by FIFO-control (Present samples subpackets written in FIFO)
++ * 1 - layout_man:
++ * 0 - layout defined by audio packet header
++ * 1 - manual control of layout
++ * 0 - layout: value of layout in case of manual selection
++ * 0 - layout0
++ * 1 - layout1
++ */
++ io_write(REG_AUDIO_LAYOUT,
++ ((sp_used_by_fifo)?(1<<2):0) | pdata->audout_layout);
++
++ /* FIFO Latency value */
++ io_write(REG_FIFO_LATENCY_VAL, fifo_latency);
++
++ /* AUDIO_OUT_ENABLE bits: enable AP, ACLK and WS if needed
++ * 5 - aclk_out - 1=Audio clock port active
++ * 4 - ws_out - 1=Word selection port active
++ * 3 - ap3_out - 1=AP0 active
++ * 2 - ap2_out - 1=AP1 active
++ * 1 - ap1_out - 1=AP2 active
++ * 0 - ap0_out - 1=AP3 active
++ */
++ if (!sp_used_by_fifo) {
++ reg = 0x0f;
++ } else {
++ /* TODO: ensure audio out DAI allows AP1,2,3? */
++ reg = 0x01; /* AP0 always enabled */
++ if (channel_assignment >= 0x01)
++ reg |= 2; /* >1 also need AP1 */
++ if (channel_assignment >= 0x04)
++ reg |= 4; /* >4 also need AP2 */
++ if (channel_assignment >= 0x0C)
++ reg |= 8; /* >12 also need AP3 */
++ /* specific cases where AP1 is not used */
++ if ((channel_assignment == 0x04)
++ || (channel_assignment == 0x08)
++ || (channel_assignment == 0x0c)
++ || (channel_assignment == 0x10)
++ || (channel_assignment == 0x14)
++ || (channel_assignment == 0x18)
++ || (channel_assignment == 0x1c))
++ reg &= ~2;
++ /* specific cases where AP2 is not used */
++ if ((channel_assignment >= 0x14)
++ && (channel_assignment <= 0x17))
++ reg &= ~4;
++ }
++ if (ws_active)
++ reg |= 0x30;
++ io_write(REG_AUDIO_OUT_ENABLE, reg);
++
++ /* reset test mode to normal audio freq auto selection */
++ io_write(REG_TEST_MODE, 0x00);
++
++ /* reset sw_ncts_en & ncts_en if i2s layout_0 */
++ if (reg & 0x18) {
++ reg = io_read(REG_TEST_NCTS_CTRL);
++ reg &= ~0x03;
++ io_write(REG_TEST_NCTS_CTRL, reg);
++ }
++
++ return 0;
++}
++
++
++/** Selects HDMI input
++ * here as well.
++ *
++ * @param input
++ * @returns 0 on success
++ */
++int
++tda1997x_select_input(tda1997x_input_t input)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ u8 reg;
++
++ DPRINTK(0,"%s: HDMI-%c\n", __func__, input?'B':'A');
++ reg = io_read(REG_INPUT_SEL);
++ /* keep loop mode for TDA19973 */
++ if (tda1997x->chip == 19973)
++ reg &= ~MASK_DIG_INPUT_VDPR_FMT;
++ else
++ reg &= ~(MASK_DIG_INPUT_VDPR_FMT | MASK_HDMIOUTMODE);
++ reg |= 0x80; /* RESET_FTM - vdp reset */
++ reg |= input;
++ reg |= FORMAT_RESET; /* Soft reset of format measurement timing */
++ /* update INPUT_SEL */
++ io_write(REG_INPUT_SEL, reg);
++
++ return 0;
++}
++EXPORT_SYMBOL(tda1997x_select_input);
++
++
++/** configure video output format (output pins and sync config)
++ * @param pdata with video output configuration
++ * @returns 0 on success
++ */
++static int
++tda1997x_set_video_outputformat(struct tda1997x_platform_data *pdata)
++{
++ u8 reg;
++
++ DPRINTK(0,"%s: %s\n", __func__, vidfmt_names[pdata->vidout_format]);
++
++ /* Configure pixel clock generator:
++ * - delay and polarity from platform data
++ * - clock per output format
++ *
++ * CLKOUT_CTRL bits:
++ * 7 - unused
++ * 6:4 - clkout_del - Delay of clock signal on V_CLK pin
++ * 3 - unused
++ * 2 - clkout_tog - polarity of clock signal on V_CLK pin (1 - invert)
++ * 1:0 - clkout_sel: Selection of the clock signal output on CKP pin
++ * 00: Pix_clock (and selection for Chroma/Luma in case of CCIR-656, so
++ * clock for CCIR-656 DDR)
++ * 01: Pix_clock_x2 (for 422_CCIR)
++ * 10: Pix_clock_div2
++ * 11: Pix_clock_div4
++ */
++ reg = pdata->vidout_delay_clk << 4;
++ if (pdata->vidout_clkmode == CLOCK_SINGLE_EDGE) { /* single edge */
++ switch (pdata->vidout_format) {
++ case VIDEOFMT_444: /* RGB444/YUV444 */
++ case VIDEOFMT_422_SMP: /* YUV422 semi-planar */
++ break;
++ case VIDEOFMT_422_CCIR:/* YUV422 CCIR656 */
++ reg |= 0x01; /* clk_x2 */
++ break;
++ }
++ } else { /* dual edge */
++ switch (pdata->vidout_format) {
++ case VIDEOFMT_444: /* RGB444/YUV444 */
++ case VIDEOFMT_422_SMP: /* YUV422 semi-planar */
++ reg |= 0x02; /* clk_div2 */
++ break;
++ case VIDEOFMT_422_CCIR:/* YUV422 CCIR656 */
++ break;
++ }
++ }
++ io_write(REG_CLKOUT_CTRL, reg);
++
++ /* Configure pre-filter:
++ *
++ * FILTERS_CTRL:
++ * 3:2 - Bu Filter control
++ * 00: Off
++ * 01: 2 Taps
++ * 10: 7 Taps
++ * 11: 2/7 Taps
++ * 1:0 - Rv Filter control
++ * 00: Off
++ * 01: 2 Taps
++ * 10: 7 Taps
++ * 11: 2/7 Taps
++ */
++ reg = 0x00; /* filters off */
++ /* 4:2:2 mode requires conversion */
++ if ((pdata->vidout_format == VIDEOFMT_422_SMP)
++ || (pdata->vidout_format == VIDEOFMT_422_CCIR))
++ reg = 0x0f; /* 27taps for Rv and Bu */
++ io_write(REG_FILTERS_CTRL, reg);
++
++ /* Enable Blanking code and timing ref (EAV/SAV) insertion */
++ reg = VP_OUT | pdata->vidout_format;
++ if (pdata->vidout_blc)
++ reg |= VP_BLK;
++ if (pdata->vidout_trc)
++ reg |= VP_TRC;
++ io_write(REG_OF_CTRL, reg);
++
++ /* Configure bypass:
++ * VDP_CTRL bits:
++ * 5 - compdel_bp - 1:bypass compdel
++ * 4 - formatter_bp - 1:bypass formatter
++ * 3 - ?
++ * 2 - ?
++ * 1 - prefilter_bp - 1:bypass prefilter
++ * 0 - mat_bp - 1:bypass matrix conversion
++ */
++ reg = io_read(REG_VDP_CTRL);
++ /* bypass pre-filter if not needed (REG_FILTERS_CTRL == 0) */
++ if ( (io_read(REG_FILTERS_CTRL) & 0x0f) == 0)
++ reg |= (1<<1); /* disable pre-filter */
++ else
++ reg &= ~(1<<1); /* enable pre-filter */
++ /* bypass formatter if not needed:
++ * (444 mode and no insertion of timing/blanking codes */
++ if ( (pdata->vidout_format == VIDEOFMT_444)
++ && !pdata->vidout_blc
++ && !pdata->vidout_trc
++ ) {
++ reg |= (1<<4); /* disable formatter */
++ } else {
++ /* enable formatter and compdel: needed for timing/blanking codes */
++ reg &= ~((1<<4)|(1<<5));
++ }
++ /* activate compdel for small sync delays */
++ if ((pdata->vidout_delay_vs < 4) || (pdata->vidout_delay_hs < 4)) {
++ reg &= ~(1<<5);
++ }
++ io_write(REG_VDP_CTRL, reg);
++
++ /* Configure DE output signal:
++ * - delay, polarity, and source from platform data
++ *
++ * DE_FREF_SEL bits:
++ * 7:4 - de_del - DE from HDMI delay (Latency datapath + [-8..+7] pixels)
++ * 3 - de_pxq - DE pixel qualification (only when del_sel = 00)
++ * 0: Timing codes are not signaled by DE
++ * 1: Timing codes are signaled by DE
++ * 2 - de_pol - Polarity of signal output on DE/FREF pin
++ * 0: No specific action
++ * 1: Invert signal
++ * 1:0 - de_sel - Selection of signal output on DE/FREF pin
++ * 00: DE from VHREF [HREF and not(VREF)]
++ * 01: FREF from VHREF
++ * 10: FREF from HDMI
++ */
++ io_write(REG_DE_FREF_SEL,
++ (pdata->vidout_delay_de << 4) |
++ (pdata->vidout_invert_de << 2) |
++ (pdata->vidout_sel_de));
++
++ /* HS_HREF_SEL bits:
++ * 7:4 - hs_del - HS from HDMI delay (Latency datapath + [-8..+7] pixels)
++ * 3 - href_pxq - HREF pixel qualifcation:
++ * 0 - Timing codes are not signaled by HREF
++ * 1 - Timing codes are signaled by HREF
++ * 2 - hsync_pol: Polarity of signal output on HS/HREF pin
++ * 0 - No specific action
++ * 1 - Invert signal
++ * 1:0 - hsync_sel - Selection of signal output on HS/HREF pin
++ * 00: HS from VHREF (Select HS signal output from internal sync generator
++ * on HS_HREF hardware pin)
++ * 01: HREF from VHREF (Select HREF signal output from internal sync
++ * generator on HS_HREF hardware pin)
++ * 10: HREF from HDMI (Select HREF signal output from HDMI input sync
++ * processor on HS_HREF hardware pin)
++ */
++ io_write(REG_HS_HREF_SEL,
++ (pdata->vidout_delay_hs << 4) |
++ (pdata->vidout_invert_hs << 2) |
++ (pdata->vidout_sel_hs));
++
++ /* VS_VREF_SEL bits:
++ * 7:4 - vs_del - VS from HDMI delay (Latency datapath + [-8..+7] pixels)
++ * 3 - unused
++ * 2 - vsync_pol: Polarity of signal output on VS/VREF pin
++ * 0 - No specific action
++ * 1 - Invert signal
++ * 1:0 - vsync_sel - Selection of signal output on VS/VREF pin
++ * 00: VS from VHREF (Select VS signal output from internal sync generator
++ * on HS_VREF hardware pin) (BSLHDMIRX_SYNCOUTPUT_VSYNC_VHREF)
++ * 01: VREF from VHREF (Select VREF signal output from internal sync
++ * generator on HS_VREF hardware pin) (BSLHDMIRX_SYNCOUTPUT_VREF_VHREF)
++ * 10: VREF from HDMI (Select HREF signal output from HDMI input sync
++ * processor on HS_VREF hardware pin) (BSLHDMIRX_SYNCOUTPUT_VSYNC_HDMI)
++ */
++ io_write(REG_VS_VREF_SEL,
++ (pdata->vidout_delay_vs << 4) |
++ (pdata->vidout_invert_vs << 2) |
++ (pdata->vidout_sel_vs));
++
++ return 0;
++}
++
++
++/** Soft Reset of specific hdmi info
++ * @param info_rst - reset to apply to HDMI_INFO_RST
++ * @param bresetSus - reset start-up sequencer
++ * @returns 0 on success
++ */
++static int
++tda1997x_hdmi_info_reset(u8 info_rst, bool bresetSus)
++{
++ u8 reg;
++
++ DPRINTK(0,"%s: 0x%02x %s\n", __func__, info_rst, bresetSus?"RESET_SUS":"");
++
++ reg = io_read(REG_HDMI_INFO_RST);
++ io_write(REG_HDMI_INFO_RST, info_rst);
++
++ /* if IF has been reset, clear INT_FLG_MODE as all ITs are raided by the
++ * reset IF */
++ if (reg & RESET_IF) {
++ reg = io_read(REG_INT_FLG_CLR_MODE);
++ io_write(REG_INT_FLG_CLR_MODE, reg);
++ }
++
++ /* Write SUS_RESET register (bit hdcp_dcc_man does not exist on TDA19972) */
++ if (!bresetSus) {
++ reg = io_read(REG_RATE_CTRL);
++ reg |= RATE_REFTIM_ENABLE;
++ reg = io_write(REG_RATE_CTRL, reg);
++ } else {
++ reg = io_read(REG_RATE_CTRL);
++ reg &= ~RATE_REFTIM_ENABLE;
++ reg = io_write(REG_RATE_CTRL, reg);
++ }
++
++ return 0;
++}
++
++/* Configure HDCP: set basic configuration for HDCP module:
++ * enable/disable, key encryption, DDC address, key description seed
++ *
++ * @param decrypt_keys - Key internal decryption (on/off)
++ * @param hdcp_enable - Enable/disable HDCP function
++ * @param i2c_addr - Display data channel I2C slave address
++ * @param key_decryption_seed - Key decryption Seed
++ * @returns 0 on success
++ */
++static int
++tda1997x_configure_hdcp(struct tda1997x_data *tda1997x,
++ hdcp_key_t decrypt_keys,
++ enable_t hdcp_enable,
++ u8 ddc_i2c_addr,
++ u16 key_decryption_seed)
++{
++ u8 reg;
++ u8 regs[3];
++
++ DPRINTK(0,"%s: enable=%d ddc=0x%02x seed=0x%04x\n",
++ __func__, hdcp_enable, ddc_i2c_addr, key_decryption_seed);
++
++ /* HDCP control */
++ regs[0] = decrypt_keys | hdcp_enable;
++ /* keys description seed MSB */
++ regs[1] = key_decryption_seed >> 8;
++ /* keys description seed LSB */
++ regs[2] = key_decryption_seed & 0x00ff;
++
++ if (tda1997x->chip_revision == 0) {
++ /* enable clock on TMDS PLL by using FRO */
++ io_write(REG_CLK_CFG, 0x03);
++ io_write(REG_PON_CBIAS, 0x01);
++ io_write(REG_PON_PLL, 0x01);
++ io_write(REG_PON_OVR_EN, 0x01);
++ }
++
++ /* write HDCP_CTRL regs */
++ io_writen(REG_HDCP_CTRL, 3, regs);
++
++ /* write i2c addr */
++ io_write(REG_HDCP_DDC_ADDR, ddc_i2c_addr);
++
++ if (tda1997x->chip_revision == 0) {
++ /* disable clock on TMDS PLL by using FRO */
++ io_write(REG_CLK_CFG, 0x00);
++ io_write(REG_PON_OVR_EN, 0x00);
++
++ /* Restore clock */
++ io_write(REG_PON_CBIAS, 0x00);
++ io_write(REG_CGU_DEBUG_SEL, 0x08);
++
++ /* Clear HDMI mode flag in BCAPS (for N1) */
++ io_write(REG_CLK_CFG, 0x03);
++ io_write(REG_PON_OVR_EN, 0x01);
++ io_write(REG_PON_CBIAS, 0x01);
++ io_write(REG_PON_PLL, 0x01);
++ reg = io_read(REG_MODE_RECOVER_CFG1);
++ reg &= ~0x06;
++ reg |= 0x02;
++ io_write(REG_MODE_RECOVER_CFG1, reg);
++ io_write(REG_CLK_CFG, 0x00);
++ io_write(REG_PON_OVR_EN, 0x00);
++ reg = io_read(REG_MODE_RECOVER_CFG1);
++ reg &= ~0x06;
++ io_write(REG_MODE_RECOVER_CFG1, reg);
++ }
++
++ /* clear HDCP interrupt status bits that may have been raised during this
++ * process
++ */
++ io_write(REG_INT_FLG_CLR_HDCP, 0x07);
++
++ return 0;
++}
++
++/* Configure HDCP MTP
++ * @param cmd - command to be sent (download or read)
++ * @returns 0 on success
++ */
++static int
++tda1997x_configure_mtp(struct tda1997x_data *tda1997x, mtp_command_t cmd)
++{
++ u8 reg;
++ unsigned int timeout;
++
++ switch (cmd) {
++ case MTP_START_DOWNLOAD:
++ DPRINTK(0,"%s: MTP_START_DOWNLOAD\n", __func__);
++ if (tda1997x->chip_revision == 0) {
++ /* disable termination and enable HDCP block */
++ io_write(REG_RT_MAN_CTRL, 0x00);
++ io_write(REG_MAN_SUS_HDMI_SEL, MAN_RST_HDCP | MAN_DIS_HDCP);
++
++ /* enable clock on TMDS PLL by using FRO */
++ io_write(REG_CLK_CFG, 0x03);
++ io_write(REG_PON_CBIAS, 0x01);
++ io_write(REG_PON_PLL, 0x01);
++ io_write(REG_PON_OVR_EN, 0x01);
++ io_write(REG_CGU_DEBUG_SEL, 0x00);
++
++ /* reset HDCP block */
++ io_write(REG_MAN_SUS_HDMI_SEL, MAN_RST_HDCP | MAN_DIS_HDCP);
++ io_write(REG_MAN_HDMI_SET, 0x04);
++ io_write(REG_MAN_HDMI_SET, 0x00);
++
++ /* remove force */
++ io_write(REG_PON_OVR_EN, 0x00);
++ io_write(REG_CLK_CFG, 0x03);
++
++ /* copy byte KEY_0(39) (0x4002) into private_area (0x425f) */
++ reg = io_read(0x4002 /*REG_MTP_KEY39_LSB*/);
++ io_write(0x425f /*REG_MTP_PRIVATE_AREA*/, reg);
++ }
++
++ /* Enable HDCP */
++ io_write(REG_HDMI_INFO_RST, 0x00);
++ io_write(REG_HDCP_CTRL, 0x03);
++
++ /* clear flag hdcp_dlmtp: 0x0015:4 */
++ io_write(REG_INT_FLG_CLR_HDCP, 0x18);
++
++ /* download key into HDCP engine */
++ io_write(REG_HDCP_KEY_CTRL, 0x01);
++
++ /* check flag hdcp_dlram: 0x0015:3 */
++ timeout = jiffies + msecs_to_jiffies(100);
++ do {
++ reg = io_read(REG_INT_FLG_CLR_HDCP);
++ } while ( (jiffies < timeout) & ((reg & 0x08) != 0x08));
++
++ /* download MTP into SRAM: hmtp_dl_all (0x137a) */
++ io_write(REG_HMTP_CTRL, 0x01);
++
++ /* check flag hdcp_dlmtp: 0x0015:4 */
++ timeout = jiffies + msecs_to_jiffies(100);
++ do {
++ reg = io_read(REG_INT_FLG_CLR_HDCP);
++ } while ( (jiffies < timeout) & ((reg & 0x10) != 0x10));
++
++ /* clear HDCP interrupt status bits that may have been raised */
++ io_write(REG_INT_FLG_CLR_HDCP, 0x07);
++ break;
++
++ case MTP_START_READ:
++ DPRINTK(0,"%s: MTP_START_READ\n", __func__);
++ /* clear flag hdcp_dlmtp */
++ io_write(REG_INT_FLG_CLR_HDCP, 0x10);
++
++ /* Download MTP into SRAM: hmtp_dl_all */
++ io_write(REG_HMTP_CTRL, 0x01);
++
++ /* check flag hdcp_dlmtp */
++ timeout = jiffies + msecs_to_jiffies(100);
++ do {
++ reg = io_read(REG_INT_FLG_CLR_HDCP);
++ } while ( (jiffies < timeout) & ((reg & 0x10) != 0x10));
++ break;
++ }
++
++ return 0;
++}
++
++
++/** set power mode
++ */
++static void
++tda1997x_power_mode(struct tda1997x_data *tda1997x, bool bEnable)
++{
++ u8 reg;
++
++ dev_dbg(&tda1997x->client->dev, "%s %s\n", __func__, bEnable?"on":"off");
++ DPRINTK(0,"%s %s\n", __func__, bEnable?"on":"off");
++
++ if (bEnable) {
++ /* Power on sequence */
++
++#if 0
++ /* Disable low power mode */
++ reg = io_read(REG_EDID_POWER);
++ reg &= ~MASK_LOW_PW_EDID;
++ io_write(REG_EDID_POWER, reg);
++#endif
++
++ /* Automatic control of TMDS */
++ io_write(REG_PON_OVR_EN, TMDS_AUTO_PON);
++
++ /* Enable current bias unit */
++ io_write(REG_CFG1, CBIAS_PON);
++
++#if 0
++ /* Enable TMDS clock in the digital equalizer */
++ reg = io_read(REG_SUS_RESET);
++ reg &= ~MASK_TMDS_CLK_DIS;
++ io_write(REG_SUS_RESET, reg);
++
++ /* Enable Xtal Osc */
++ reg = io_read(REG_XOSC_CFG);
++ reg &= ~MASK_XTAL_OSC_PD;
++ io_write(REG_XOSC_CFG, reg);
++#endif
++
++ /* Enable deep color PLL */
++ io_write(REG_DEEP_PLL7, DC_PLL_PON);
++
++#if 0
++ /* Enable audio PLL */
++ reg = io_read(REG_CLOCKS_MODE);
++ reg &= ~MASK_AUDIO_PLL_PD;
++ io_write(REG_CLOCKS_MODE, reg);
++#endif
++
++ /* Output buffers active */
++ reg = io_read(REG_OF_CTRL);
++ reg &= ~MASK_OF_CTRL_OUT_HIZ;
++ io_write(REG_OF_CTRL, reg);
++
++ } else {
++ /* Power down EDID mode sequence */
++
++ /* Output buffers in HiZ */
++ reg = io_read(REG_OF_CTRL);
++ reg |= MASK_OF_CTRL_OUT_HIZ;
++ io_write(REG_OF_CTRL, reg);
++
++#if 0
++ /* Disable audio PLL */
++ reg = io_read(REG_CLOCKS_MODE);
++ reg |= MASK_AUDIO_PLL_PD;
++ io_write(REG_CLOCKS_MODE, reg);
++#endif
++
++ /* Disable deep color PLL */
++ io_write(REG_DEEP_PLL7, DC_PLL_PD);
++
++#if 0
++ /* Disable Xtal Osc */
++ reg = io_read(REG_XOSC_CFG);
++ reg |= MASK_XTAL_OSC_PD;
++ io_write(REG_XOSC_CFG, reg);
++
++ /* Disable TMDS clock in the digital equalizer */
++ reg = io_read(REG_SUS_RESET);
++ reg |= MASK_TMDS_CLK_DIS;
++ io_write(REG_SUS_RESET, reg);
++#endif
++
++ /* Disable current bias unit */
++ io_write(REG_CFG1, CBIAS_POFF);
++
++ /* Manual control of TMDS */
++ io_write(REG_PON_OVR_EN, TMDS_MAN_PON);
++
++#if 0
++ /* Enable low power mode */
++ reg = io_read(REG_EDID_POWER);
++ reg |= MASK_LOW_PW_EDID;
++ io_write(REG_EDID_POWER, reg);
++#endif
++ }
++
++}
++
++
++/* check the audio samplerate for change
++ * @returns 0 on success
++ */
++static int
++tda1997x_get_audio_frequency(struct tda1997x_data *tda1997x)
++{
++ u8 reg;
++ long freq = 0;
++
++ reg = io_read(REG_AUDIO_FREQ);
++ switch(reg & MASK_AUDIO_FREQ) {
++ case 0x00: break;
++ case 0x01: freq= 32000; break;
++ case 0x02: freq= 44100; break;
++ case 0x03: freq= 48000; break;
++ case 0x04: freq= 88200; break;
++ case 0x05: freq= 96000; break;
++ case 0x06: freq=176400; break;
++ case 0x07: freq=192000; break;
++ }
++
++ DPRINTK(0, "REG_AUDIO_FREQ=0x%02x: %ldHz\n", reg, freq);
++ tda1997x->audio_mode.samplerate = freq;
++
++ return 0;
++}
++
++/** detect an appropriate video mode from:
++ * video input verticalPeriod, horizontalPeriod, and hsWidth
++ * @returns resolution_data *
++ */
++static const resolution_data_t *
++tda1997x_detect_resolution(struct tda1997x_data *tda1997x)
++{
++ u32 verticalPeriod;
++ u16 horizontalPeriod;
++ u16 hsWidth;
++ char vPerCmp = 0, hPerCmp = 0, hsWidthCmp = 0;
++ const resolution_data_t *res;
++ int i;
++
++ /* Read the FMT registers */
++ verticalPeriod = io_read24(REG_V_PER) & MASK_VPER;
++ horizontalPeriod = io_read16(REG_H_PER) & MASK_HPER;
++ hsWidth = io_read16(REG_HS_WIDTH) & MASK_HSWIDTH;
++ DPRINTK(0,"verticalPeriod=%d horizontalPeriod=%d hsWidth=%d\n",
++ verticalPeriod, horizontalPeriod, hsWidth);
++
++#if 1 // more details
++{
++ videoFormatDetails fmt;
++ videoFormatDetails *pFMT = &fmt;
++
++ /* read the FMT registers */
++ pFMT->vsPolarity = io_read(REG_V_PER) & 0x80;
++ pFMT->hsPolarity = io_read(REG_H_PER) & 0x80;
++ pFMT->videoFormat = io_read(REG_HS_WIDTH) & 0x80;
++ pFMT->horizontalTotalPeriod = io_read16(REG_FMT_H_TOT)&0x3fff;
++ pFMT->horizontalVideoActiveWidth = io_read16(REG_FMT_H_ACT)&0x3fff;
++ pFMT->horizontalFrontPorchWidth = io_read16(REG_FMT_H_FRONT)&0x3fff;
++ pFMT->horizontalSyncWidthPixClk = io_read16(REG_FMT_H_SYNC)&0x3fff;
++ pFMT->horizontalBackPorchWidth = io_read16(REG_FMT_H_BACK)&0x3fff;
++ pFMT->verticalTotalPeriod = io_read16(REG_FMT_V_TOT)&0x3fff;
++ pFMT->verticalVideoActiveWidth = io_read16(REG_FMT_V_ACT)&0x3fff;
++ pFMT->verticalFrontPorchWidthF1 = io_read(REG_FMT_V_FRONT_F1);
++ pFMT->verticalFrontPorchWidthF2 = io_read(REG_FMT_V_FRONT_F2);
++ pFMT->verticalSyncWidth = io_read(REG_FMT_V_SYNC);
++ pFMT->verticalBackPorchWidthF1 = io_read(REG_FMT_V_BACK_F1);
++ pFMT->verticalBackPorchWidthF2 = io_read(REG_FMT_V_BACK_F2);
++ pFMT->dataEnablePresent = io_read(REG_FMT_DE_ACT)&0x01;
++
++ DPRINTK(2,"vsPolarity=%d hsPolarity=%d videoFormat=%d\n"
++ "horizTotalPeriod=%d horizVideoActiveWidth=%d horizFrontPorchWidth=%d\n"
++ "horizSyncWidthPixClk=%d horizBackPorchWidth=%d\n"
++ "vertTotalPeriod=%d vertVideoActiveWidth=%d vertFrontPorchWidthF1=%d"
++ "vertFrontPorchWidthF2=%d\n"
++ "vertBackPorchWidthF1=%d vertBackPorchWidthF1=%d dataEnablePresent=%d\n",
++ pFMT->vsPolarity, pFMT->hsPolarity, pFMT->videoFormat,
++ pFMT->horizontalTotalPeriod, pFMT->horizontalVideoActiveWidth,
++ pFMT->horizontalFrontPorchWidth, pFMT->horizontalSyncWidthPixClk,
++ pFMT->horizontalBackPorchWidth,
++ pFMT->verticalTotalPeriod, pFMT->verticalVideoActiveWidth,
++ pFMT->verticalFrontPorchWidthF1, pFMT->verticalFrontPorchWidthF2,
++ pFMT->verticalBackPorchWidthF1,
++ pFMT->verticalBackPorchWidthF2,
++ pFMT->dataEnablePresent);
++}
++#endif
++
++ /* iterate over list of supported resolutions and find best match */
++ for (i = 0; i < ARRAY_SIZE(supported_res); i++) {
++ res = &supported_res[i];
++
++ vPerCmp = (char) ((verticalPeriod >= res->verticalPeriodMin) &&
++ (verticalPeriod <= res->verticalPeriodMax));
++ hPerCmp = (char) ((horizontalPeriod >= res->horizontalPeriodMin) &&
++ (horizontalPeriod <= res->horizontalPeriodMax));
++ hsWidthCmp = (char) ((hsWidth >= res->hsWidthMin) &&
++ (hsWidth <= res->hsWidthMax));
++
++ DPRINTK(1,"\t%02d: %dx%d@%d%c: %d/%d/%d\n", i, res->width, res->height,
++ res->horizfreq, res->interlaced?'i':'p',
++ vPerCmp, hPerCmp, hsWidthCmp);
++ if (vPerCmp && hPerCmp && hsWidthCmp) {
++ int pixrate;
++
++ /* resolutiontype used to determine Default Colorimetry */
++ switch (res->height) {
++ case 480:
++ case 576:
++ case 240:
++ case 288:
++ tda1997x->resolutiontype = RESTYPE_SDTV;
++ break;
++ case 720:
++ case 1080:
++ tda1997x->resolutiontype = RESTYPE_HDTV;
++ break;
++ default:
++ tda1997x->resolutiontype = RESTYPE_PC;
++ }
++
++ printk(KERN_INFO "%s: matched resolution: %dx%d%c@%d %s\n",
++ KBUILD_MODNAME, res->width, res->height,
++ res->interlaced?'i':'p',
++ res->horizfreq,
++ restype_names[tda1997x->resolutiontype]);
++
++ /* validate input mode */
++ pixrate = (res->width * res->height * res->horizfreq) /
++ 1000000;
++ if (res->interlaced)
++ pixrate /= 2;
++ switch(tda1997x->pdata->vidout_format) {
++ case VIDEOFMT_444:
++ case VIDEOFMT_422_SMP:
++ /* FIXME: have not figured out how to get HS output asserted on 2nd field */
++ if (res->interlaced) {
++ printk(KERN_INFO "%s: Error %s: interlaced not supported\n", KBUILD_MODNAME,
++ vidfmt_names[tda1997x->pdata->vidout_format]);
++ return NULL;
++ }
++ break;
++ case VIDEOFMT_422_CCIR:
++ /* BT656 requires 2-clocks per pixel */
++ pixrate *= 2;
++ break;
++ }
++ if (tda1997x->pdata->max_pixel_rate &&
++ (pixrate > tda1997x->pdata->max_pixel_rate))
++ {
++ printk(KERN_INFO "%s: Error: %dMP/s exceeds max of %dMP/s\n", KBUILD_MODNAME,
++ pixrate,
++ tda1997x->pdata->max_pixel_rate);
++ return NULL;
++ }
++
++ return res;
++ }
++ }
++
++ printk(KERN_ERR "%s: found no video resolution match for: %d/%d/%d\n",
++ KBUILD_MODNAME, verticalPeriod, horizontalPeriod, hsWidth);
++ return NULL;
++}
++
++/** read input activity registers
++ *
++ * @returns activity_sate bitmask:
++ * 7: unused
++ * 6: unused
++ * 5: unused
++ * 4: tmds_locked
++ * 3: inputD_clock_stable (unsupported)
++ * 2: inputC_clock_stable (unsupported)
++ * 1: inputB_clock_stable
++ * 0: inputA_clock_stable
++ */
++static u8
++tda1997x_read_activity_status_regs(void)
++{
++ u8 reg, status = 0;
++
++ /* Activity detection must only be notified when stable_clk_x AND active_x
++ * bits are set to 1. If only stable_clk_x bit is set to 1 but not
++ * active_x, it means that the TMDS clock is not in the defined range,
++ * so activity detection must not be notified
++ * => regStatus must be set to 0 in that case. If stable_clk_x bit is
++ * set to 0, regStatus must also be set to 0
++ */
++
++ /* Read CLK_A_STATUS register */
++ reg = io_read(REG_CLK_A_STATUS);
++ /* when stable_clk_x is set to 1, check active_x bit */
++ if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE) )
++ reg &= ~MASK_CLK_STABLE;
++ status |= ((reg & MASK_CLK_STABLE) >> 2);
++
++ /* Read CLK_B_STATUS register */
++ reg = io_read(REG_CLK_B_STATUS);
++ /* when stable_clk_x is set to 1, check active_x bit */
++ if ((reg & MASK_CLK_STABLE) && !(reg & MASK_CLK_ACTIVE) )
++ reg &= ~MASK_CLK_STABLE;
++ status |= ((reg & MASK_CLK_STABLE) >> 1);
++
++ /* Read the SUS_STATUS register */
++ reg = io_read(REG_SUS_STATUS);
++
++ /* If state = 5 => TMDS is locked */
++ if ( (reg & MASK_SUS_STATE_VALUE) == LAST_STATE_REACHED)
++ status |= MASK_SUS_STATE_BIT;
++ else
++ status &= ~MASK_SUS_STATE_BIT;
++
++ return status;
++}
++
++
++/** parse an infoframe and do some sanity checks on it
++ *
++ * @type of inforframe
++ * @returns 0 on success
++ */
++static unsigned int
++tda1997x_parse_infoframe(struct tda1997x_data *tda1997x, int type)
++{
++ u8 d[MAX_IF_DATA];
++ u8 crc;
++ int len = 0;
++ int i;
++
++ /* determine length based on type */
++ switch(type) {
++ case MPS_IF_TYPE: len = MPS_IF_NB_DATA; break;
++ case AUD_IF_TYPE: len = AUD_IF_NB_DATA; break;
++ case SPD_IF_TYPE: len = SPD_IF_NB_DATA; break;
++ case AVI_IF_TYPE: len = AVI_IF_NB_DATA; break;
++ case VS_HDMI_IF_TYPE:
++ case VS_BK1_IF_TYPE:
++ case VS_BK2_IF_TYPE:
++ len = VS_IF_NB;
++ break;
++ }
++
++ /* read data */
++ if (io_readn(type, len, d) != len) {
++ printk(KERN_ERR "infoframe type0x%02x failed read\n", type);
++ return -1;
++ }
++
++ /* verify crc */
++ for (i = 0, crc = 0; i < len; i++)
++ crc += d[i];
++ if (crc) {
++ printk(KERN_ERR "infoframe type0x%02x failed CRC\n", type);
++ return -2;
++ }
++
++ /* parse details */
++ switch(type) {
++ case MPS_IF_TYPE:
++ /* parse infoframe to get bitrate, fieldrepeat, MPEG_Frame */
++ DPRINTK(0,"\t\tbitrate=%d,%d,%d,%d fieldRepeat=%d MPEG_Frame=%d\n",
++ d[4], d[5], d[6], d[7], d[8] & 0x10, d[8] & 0x03);
++ break;
++
++ /* Audio InfoFrame: see HDMI spec 8.2.2 */
++ case AUD_IF_TYPE:
++ /*
++ * CC0..CC2 - Channel Count. See CEA-861-D table 17
++ * CT0..CT3 - Coding Type. The CT bits shall always be 0 (use Stream Header)
++ * SS0..SS1 - Sample Size. The SS bits shall always be 0 (use Stream Header)
++ * SF0..SF2 - Sample Freq. See CEA-861-D table 18.
++ * - For L-PCM and IEC 61937 compressed audio streams the SF bits
++ * shall always be 0 (use Stream Header).
++ * - For One Bit Audio and DST streams, the SF bits shall equal
++ * the ACR fs value.
++ * - For Super Audio CD, the SF bits are typically 0, 1, 0
++ * indicating a sample freq of 2.8224MSamples/s (64*44.1kHz)
++ * CA0..CA7 - Channel/Speaker Allocation. See CEA-861-D Section 6.6.2
++ * - this is not valid for IEC 61937 compressed audio streams
++ * LSV0..LSV3 - Level Shif Value (for downmixing). See CEA-861-D 6.6.2
++ * and CEA-861-D table 21
++ * DM_INH - Downmix inibit. See CEA-861-D sec 6.6.2 and table 22
++ * The DM_INH field is to be set only for DVD-Audio
++ *
++ * CT, SS, and SF values of 0 indicate that these items are carried in the
++ * audio stream itself.
++ */
++ DPRINTK(0,"\t\tcodingType=%d channelCount=%d samplefrequency=%d "
++ "samplesize=%d dataByte3=%d channelAllocation=%d downmixInhibit=%d "
++ "levelShiftValue=%d\n",
++ (d[4] & 0xf0) >> 4, /* CT3, CT2, CT1, CT0 */
++ (d[4] & 0x07), /* CC2, CC1, CC0 */
++ (d[5] & 0x1c) >> 2, /* SF2, SF1, SF0 */
++ (d[5] & 0x03), /* SS1, SS0 */
++ d[6],
++ d[7], /* CA7 .. CA0 */
++ (d[8] & 0x80) >> 7, /* DM_INH */
++ (d[8] & 0x78) >> 3); /* LSV3, LSV2, LSV1, LSV0 */
++
++ /* Channel Count */
++ tda1997x->source_channels = (d[4] & 0x07) + 1;
++ DPRINTK(0, "Audio Channels: %d\n",
++ tda1997x->source_channels);
++
++ /* Channel Assignment */
++ if ( (d[7] <= 0x1f) /* MAX_CHANNEL_ALLOC */
++ && (d[7] != tda1997x->channel_assignment)
++ && !tda1997x->pdata->audio_force_channel_assignment)
++ {
++ /* use the channel assignment from the audio infoframe */
++ DPRINTK(0, "channel assignment changed: %d\n", d[7]);
++ tda1997x->channel_assignment = d[7];
++
++ /* configure audio output */
++ tda1997x_configure_audio_formatter(tda1997x->pdata,
++ tda1997x->channel_assignment);
++
++ /* reset the audio FIFO */
++ tda1997x_hdmi_info_reset(RESET_AUDIO, 0);
++ //tda1997x_hdmi_info_reset(0x00, 0);
++ }
++ break;
++
++ /* Source Product Descriptor information (SPD) */
++ case SPD_IF_TYPE:
++ for (i = 0; i < 8; i++)
++ tda1997x->vendor[i] = d[4 + i];
++ for (i = 0; i < 16; i++)
++ tda1997x->product[i] = d[4 + 8 + i];
++ printk(KERN_INFO "%s: Source Product Descriptor: %s %s\n", KBUILD_MODNAME,
++ tda1997x->vendor, tda1997x->product);
++ break;
++
++
++ /* Auxiliary Video information (AVI) InfoFrame: see HDMI spec 8.2.1 */
++ case AVI_IF_TYPE: {
++ u8 pixel_repetitionfactor;
++ u8 reg;
++
++ if (d[0] != 0x82) {
++ printk(KERN_ERR "INFOFRAME AVI: wrong packet type! (0x%02x)\n", d[0]);
++ }
++ DPRINTK(0,"\t\tcolorIndicator=%d activeInfoPresent=%d "
++ "barInfomationDataValid=%d scanInformation=%d colorimetry=%d "
++ "pictureAspectRatio=%d activeFormatAspectRation=%d "
++ "nonUinformPictureScaling=%d videoFormatIdentificationCode=%d "
++ "pixelRepetitionFactor=%d\n",
++ (d[4] & 0x60) >> 5, /* colorspace: Y1, Y0 */
++ (d[4] & 0x10) >> 4, /* activeInfoPresent: A0 */
++ (d[4] & 0x0c) >> 2, /* barInformationValid: B1, B0 */
++ (d[4] & 0x03), /* scanInformation: S1, S0 */
++ (d[5] & 0xc0) >> 6, /* coloriemtry: C1, C0 */
++ (d[5] & 0x30) >> 4, /* pictureAspectRatio: M1, M0 */
++ (d[5] & 0x0f), /* activeFormatAspectRatio: R3, R2, R1, R0 */
++ (d[6] & 0x03), /* nonUniformPictureScaling: SC1, SC0 */
++ (d[7] & 0x7f), /* videoFormatID: VIC6, VIC5, VIC4 */
++ (d[8] & 0x0f) /* pixelRepetitionFactor: PR3, PR2, PR1, PR0 */
++ );
++ tda1997x->colorspace = (d[4] & 0x60) >> 5; /* Y1, Y0 */
++ tda1997x->colorimetry = (d[5] & 0xc0) >> 6; /* C1, C0 */
++ pixel_repetitionfactor = d[8] & 0x0f; /* PR3, PR2, PR1, PR0 */
++ /* If colorimetry not specified, conversion depends on resolutiontype:
++ * - SDTV: ITU601 for SD (480/576/240/288 line resolution)
++ * - HDTV: ITU709 for HD (720/1080 line resolution)
++ * - PC: sRGB
++ * see HDMI specification section 6.7
++ */
++ if ( (tda1997x->colorspace == COLORSPACE_YCBCR_422 ||
++ tda1997x->colorspace == COLORSPACE_YCBCR_444) &&
++ (tda1997x->colorimetry == COLORIMETRY_XVYCC ||
++ tda1997x->colorimetry == COLORIMETRY_NONE) )
++ {
++
++ if (tda1997x->resolutiontype == RESTYPE_HDTV)
++ tda1997x->colorimetry = COLORIMETRY_ITU709;
++ else if (tda1997x->resolutiontype == RESTYPE_SDTV)
++ tda1997x->colorimetry = COLORIMETRY_ITU601;
++ else
++ tda1997x->colorimetry = COLORIMETRY_NONE;
++ dev_info(&tda1997x->client->dev,
++ "invalid/undefined colorimetry defaulted to %s (%s)\n",
++ colorimetry_names[tda1997x->colorimetry],
++ restype_names[tda1997x->resolutiontype]);
++ }
++
++ /* configure upsampler per sample format */
++ /* ConfigureUpDownSampler: 0=bypass 1=repeatchroma 2=interpolate */
++ reg = io_read(REG_PIX_REPEAT);
++ reg = (reg & ~0x30 /* MASK_UP_SEL */);
++ if (tda1997x->colorspace == COLORSPACE_YCBCR_422)
++ reg |= (1 << 4); /* repeatchroma */
++ io_write(REG_PIX_REPEAT, reg);
++
++ /* ConfigurePixelRepeater - repeat n-times each pixel */
++ reg = io_read(REG_PIX_REPEAT);
++ reg = (reg & ~0x0f /*MASK_PIX_REP*/) | pixel_repetitionfactor;
++ io_write(REG_PIX_REPEAT, reg);
++
++ /* configure the receiver with the new colorspace */
++ tda1997x_configure_conversion(tda1997x,
++ tda1997x->colorspace,
++ tda1997x->colorimetry,
++ tda1997x->pdata->vidout_format);
++
++ } break;
++
++ case VS_HDMI_IF_TYPE:
++ case VS_BK1_IF_TYPE:
++ case VS_BK2_IF_TYPE:
++ /* read update flag and store at the end */
++ d[VS_IF_NB] = io_read(type);
++ if (type == VS_HDMI_IF_TYPE && d[VS_IF_NB] > 3) /* HDMI_INFO_EXCEED */
++ {
++ DPRINTK(0,"HDMI_INFO_EXCEED\n");
++ return -3;
++ }
++ DPRINTK(0, "\t\tieee_id[0]=%d ieee_id[1]=%d ieee_id[2]=%d\n",d[0],d[1],d[2]);
++ break;
++ }
++
++ return 0;
++}
++
++
++/* tda1997x_work - deferred work procedure for handling interrupt
++ */
++static void tda1997x_work(struct work_struct *work)
++{
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ u8 reg, interrupt_top_flags, source;
++
++ do {
++ /* read interrupt flags */
++ interrupt_top_flags = io_read(REG_INT_FLG_CLR_TOP);
++ if (interrupt_top_flags == 0)
++ break;
++ DPRINTK(0,"interrupt:0x%02x\n", interrupt_top_flags);
++
++ /* SUS interrupt source (Input activity events) */
++ if (interrupt_top_flags & INTERRUPT_SUS) {
++ source = io_read(REG_INT_FLG_CLR_SUS);
++ io_write(REG_INT_FLG_CLR_SUS, source);
++ DPRINTK(0,"SUS: 0x%02x\n", source);
++
++ if (source & MASK_MPT_BIT) {
++ DPRINTK(0,"\tConfig MTP end of process\n");
++
++ /* reset MTP in use flag if set */
++ if (tda1997x->mptrw_in_progress)
++ tda1997x->mptrw_in_progress = 0;
++ }
++
++ if (source & MASK_SUS_END_BIT) {
++ /* reset audio FIFO */
++ reg = io_read(REG_HDMI_INFO_RST);
++ reg |= MASK_SR_FIFO_FIFO_CTRL;
++ io_write(REG_HDMI_INFO_RST, reg);
++ reg &= ~MASK_SR_FIFO_FIFO_CTRL;
++ io_write(REG_HDMI_INFO_RST, reg);
++
++ DPRINTK(0,"\tRESET AUDIO SUS_END\n");
++
++ /* reset HDMI flags memory and vsi_received flag */
++ tda1997x->hdmi_status = 0;
++ tda1997x->vsi_received = 0;
++ }
++
++ /* filter FMT interrupt based on SUS state */
++ reg = io_read(REG_SUS_STATUS);
++ if ( ((reg & MASK_SUS_STATE_VALUE) != LAST_STATE_REACHED)
++ || (source & MASK_MPT_BIT))
++ {
++ DPRINTK(0,"sus_state_value=0x%02x filter video fmt changed\n",
++ reg & MASK_SUS_STATE_VALUE);
++ source &= ~MASK_FMT_BIT;
++ }
++
++ if (source & (MASK_FMT_BIT | MASK_SUS_END_BIT)) {
++ const resolution_data_t *res;
++ DPRINTK(0, "\tHDMI LOCKED\n");
++
++ reg = io_read(REG_SUS_STATUS);
++ if ((reg & MASK_SUS_STATE_VALUE) != LAST_STATE_REACHED) {
++ printk(KERN_ERR "%s: BAD SUS STATUS\n", KBUILD_MODNAME);
++ continue;
++ }
++
++ /* There is a new activity, the status for HDCP repeater state */
++ tda1997x->state_c5_reached = 0;
++
++ /* Detect the new resolution */
++ res = tda1997x_detect_resolution(tda1997x);
++ if (res) {
++ tda1997x->video_mode.width = res->width;
++ tda1997x->video_mode.height = res->height;
++ tda1997x->video_mode.fps = res->horizfreq;
++ tda1997x->video_mode.interlaced = res->interlaced;
++ tda1997x->video_mode.signal = 1;
++
++ /* configure the active input to the given resolution */
++ tda1997x_configure_input_resolution(res->resolutionID);
++
++ } else {
++ tda1997x->video_mode.width = 0;
++ tda1997x->video_mode.height = 0;
++ tda1997x->video_mode.fps = 0;
++ tda1997x->video_mode.interlaced = 0;
++ tda1997x->video_mode.signal = 1;
++ }
++
++ /* on 'input locked' event, RGB colorspace is forced (the AVI infoframe
++ * is not received yet at this moment)
++ * if AVI infoframe is received later, the colorspace will be
++ * reconfigured in the AVI infoframe handler
++ */
++ tda1997x->colorspace = COLORSPACE_RGB;
++ tda1997x->colorimetry = COLORIMETRY_NONE;
++ /* bypass colorspace conversion */
++ io_write(REG_VDP_CTRL, io_read(REG_VDP_CTRL) | (1<<0));
++ /* SetBlankingCodes */
++ io_write16(REG_BLK_GY, RGBBlankingCode.blankingCodeGy);
++ io_write16(REG_BLK_BU, RGBBlankingCode.blankingCodeBu);
++ io_write16(REG_BLK_RV, RGBBlankingCode.blankingCodeRv);
++
++ /* set the state machine */
++ tda1997x->state = STATE_LOCKED;
++ }
++
++ if (source & MASK_RT_PULSE_BIT) {
++ DPRINTK(0,"\tEnd of termination resistance pulse\n");
++ }
++ if (source & MASK_SUS_ACT_BIT) {
++ DPRINTK(0,"\tActivity of selected input changed\n");
++ }
++ if (source & MASK_SUS_CH_BIT) {
++ DPRINTK(0,"\tSelected input changed\n");
++ }
++ if (source & MASK_SUS_ST_BIT) {
++ DPRINTK(0,"\tSUS state changed\n");
++ }
++ }
++
++ /* DDC interrupt source (Display Data Channel) */
++ else if (interrupt_top_flags & INTERRUPT_DDC ) {
++ source = io_read(REG_INT_FLG_CLR_DDC );
++ io_write(REG_INT_FLG_CLR_DDC, source);
++ DPRINTK(0,"DDC: 0x%02x\n", source);
++
++ if (source & MASK_EDID_MTP) {
++ DPRINTK(0,"\tEDID MTP end of process\n");
++ /* reset MTP in use flag if set */
++ if (tda1997x->mptrw_in_progress)
++ tda1997x->mptrw_in_progress = 0;
++ }
++
++ /* we don't care about these */
++ if (source & MASK_DDC_ERR) {
++ DPRINTK(0,"\tmaster DDC error\n");
++ }
++ if (source & MASK_DDC_CMD_DONE) {
++ DPRINTK(0,"\tmaster DDC cmd send correct\n");
++ }
++ if (source & MASK_READ_DONE) {
++ DPRINTK(0,"\tEnd of Down EDID read\n");
++ }
++ if (source & MASK_RX_DDC_SW) {
++ DPRINTK(0,"\tOutput DDC switching finished\n");
++ }
++ if (source & MASK_HDCP_DDC_SW) {
++ DPRINTK(0,"\tHDCP DDC switching finished\n");
++ }
++ if (source & MASK_HDP_PULSE_END) {
++ DPRINTK(0,"\tEnd of Hot Plug Detect pulse\n");
++ }
++ if (source & MASK_DET_5V) {
++ DPRINTK(0,"\tDetected +5V\n");
++ }
++ }
++
++ /* RATE interrupt source (Digital Input A/B activity: rate/presence/drift) */
++ else if (interrupt_top_flags & INTERRUPT_RATE) {
++ u8 irq_status, last_irq_status;
++
++ source = io_read(REG_INT_FLG_CLR_RATE);
++ io_write(REG_INT_FLG_CLR_RATE, source);
++ DPRINTK(0,"RATE: 0x%02x\n", source);
++
++ /* read status regs */
++ last_irq_status = irq_status = tda1997x_read_activity_status_regs();
++
++ /* read clock status reg until INT_FLG_CLR_RATE is still 0
++ * after the read to make sure its the last one
++ */
++ reg = source;
++ while (reg != 0) {
++ irq_status = tda1997x_read_activity_status_regs();
++ reg = io_read(REG_INT_FLG_CLR_RATE);
++ io_write(REG_INT_FLG_CLR_RATE, reg);
++ source |= reg;
++ }
++
++ /* we don't use these indicators */
++#if 0
++ if (source & MASK_RATE_B_DRIFT) {
++ DPRINTK(0, "\tRate measrement of input B drifted\n");
++ }
++ if (source & MASK_RATE_B_ACT) {
++ DPRINTK(0, "\tRate measurement of input B activity change\n");
++ }
++ if (source & MASK_RATE_B_PST) {
++ DPRINTK(0, "\tRate measurement of input B presence change\n");
++ }
++ if (source & MASK_RATE_A_DRIFT) {
++ DPRINTK(0, "\tRate measrement of input A drifted\n");
++ }
++ if (source & MASK_RATE_A_ACT) {
++ DPRINTK(0, "\tRate measurement of input A activity change\n");
++ }
++ if (source & MASK_RATE_A_PST) {
++ DPRINTK(0, "\tRate measurement of input A presence change\n");
++ }
++#endif
++
++ /* we only pay attention to stability change events */
++ if (source & (MASK_RATE_A_ST | MASK_RATE_B_ST)) {
++ int input = (source & MASK_RATE_A_ST)?0:1;
++ u8 mask = 1<<input;
++
++ DPRINTK(0, "\tHDMI-%c: Rate measurement stability change\n", input+'A');
++ DPRINTK(0, "\tirq_status=0x%02x/0x%02x/0x%02x\n",
++ irq_status, last_irq_status, tda1997x->activity_status_reg);
++
++ /* state change */
++ if ((irq_status & mask) != (tda1997x->activity_status_reg & mask)) {
++
++ /* activity lost */
++ if ( (irq_status & mask) == 0) {
++ printk(KERN_INFO "%s: HDMI-%c: Digital Activity Lost\n",
++ KBUILD_MODNAME, input+'A');
++ tda1997x->state = STATE_UNLOCKED;
++ tda1997x->input_detect[input] = 0;
++ tda1997x->hdmi_status = 0;
++ tda1997x->hdmi_detected = 0;
++ tda1997x->hdcp_detected = 0;
++ tda1997x->eess_detected = 0;
++
++ /* ConfigureUpDownSampler: 0=bypass 1=repeatchroma 2=interpolate */
++ reg = io_read(REG_PIX_REPEAT);
++ reg = (reg & ~0x30 /*MASK_UP_SEL*/) | (0 << 4); /* bypass */
++ io_write(REG_PIX_REPEAT, reg);
++
++ /* ConfigurePixelRepeater - repeat n-times each pixel */
++ reg = io_read(REG_PIX_REPEAT);
++ reg = (reg & ~0x0f /*MASK_PIX_REP*/) | 0; /* 0-times: disable */
++ io_write(REG_PIX_REPEAT, reg);
++
++ if (tda1997x->chip_revision == 0) {
++ /* Clear HDMI mode flag in BCAPS (for N1) */
++ io_write(REG_CLK_CFG, 0x03);
++ io_write(REG_PON_OVR_EN, 0x01);
++ io_write(REG_PON_CBIAS, 0x01);
++ io_write(REG_PON_PLL, 0x01);
++ reg = io_read(REG_MODE_RECOVER_CFG1);
++ reg &= ~0x06;
++ reg |= 0x02;
++ io_write(REG_MODE_RECOVER_CFG1, reg);
++ io_write(REG_CLK_CFG, 0x00);
++ io_write(REG_PON_OVR_EN, 0x00);
++ reg = io_read(REG_MODE_RECOVER_CFG1);
++ reg &= ~0x06;
++ io_write(REG_MODE_RECOVER_CFG1, reg);
++ }
++
++ tda1997x->video_mode.width = 0;
++ tda1997x->video_mode.height = 0;
++ tda1997x->video_mode.fps = 0;
++ tda1997x->video_mode.interlaced = 0;
++ tda1997x->video_mode.signal = 0;
++ }
++
++ else {
++ printk(KERN_INFO "%s: HDMI-%c: Digital Activity Detected\n",
++ KBUILD_MODNAME, input+'A');
++ tda1997x->input_detect[input] = 1;
++ }
++
++ /* hold onto current state */
++ tda1997x->activity_status_reg = (irq_status & mask);
++ }
++ }
++ }
++
++ /* MODE interrupt source (Gamut, ISRC2, ISRC1, ACP, GCP, Deep color flags) */
++ else if (interrupt_top_flags & INTERRUPT_MODE) {
++ source = io_read(REG_INT_FLG_CLR_MODE);
++ io_write(REG_INT_FLG_CLR_MODE, source);
++ DPRINTK(0,"MODE: 0x%02x\n", source);
++
++ /* special processing for HDMI Flag IT */
++ if (source & MASK_HDMI_FLG) {
++ u8 statusChange;
++
++ reg = io_read(REG_HDMI_FLAGS);
++ reg &= 0x7c; /* ignore fifo_fail and fifo_warning bits */
++ statusChange = tda1997x->hdmi_status ^ reg;
++ DPRINTK(0,"\tHDMI_FLAGS:0x%02x prev=0x%02x changed=0x%02x\n", reg,
++ tda1997x->hdmi_status, statusChange);
++ if (statusChange) {
++ tda1997x->hdmi_status = reg;
++ /* Get HDMI Status */
++ if (statusChange & 0x80)
++ DPRINTK(0,"\t\tAUDIOFLAG - Audio packet in last videoframe\n");
++ if (statusChange & 0x40)
++ DPRINTK(0,"\t\tHDMI mode detected\n");
++ tda1997x->hdmi_detected = 1;
++ if (statusChange & 0x20)
++ DPRINTK(0,"\t\tEESS mode detected\n");
++ tda1997x->eess_detected = 1;
++ if (statusChange & 0x10)
++ DPRINTK(0,"\t\tHDCP encryption detected\n");
++ tda1997x->hdcp_detected = 1;
++ if (statusChange & 0x08)
++ DPRINTK(0,"\t\tAVMUTE\n");
++ if (statusChange & 0x04)
++ DPRINTK(0,"\t\tLayout status Audio Sample Packet\n");
++ if (statusChange & 0x02)
++ DPRINTK(0,"\t\tFIFO read/write pointers are crossed\n");
++ if (statusChange & 0x01)
++ DPRINTK(0,"\t\tFIFO read ptr closer than 2 samples from write ptr\n");
++ }
++ }
++ if (source & MASK_GAMUT) {
++ u8 d[GDB_PACKET_HDR_LEN + GDB_PACKET_DAT_LEN];
++ io_readn(REG_GBD_PACKET_TYPE, sizeof(d), d);
++ DPRINTK(0,"\tGamut packet: type=%d nextField=%d GBDProfile=%d "
++ "affectedGamutSeqNum=%d noCrntGBD=%d packetSeq=%d curSeq=%d\n",
++ d[0], /* type */
++ (d[1] & 0x80) >> 7, /* nextField */
++ (d[1] & 0x70) >> 4, /* GBDProfile */
++ (d[1] & 0x0f), /* affected Gamut SeqNum */
++ (d[2] & 0x80) >> 7, /* noCrntGBD */
++ (d[2] & 0x30) >> 4, /* packet SeqNum */
++ (d[2] & 0x0f) /* current SeqNum */
++ );
++ }
++#if 0
++ if (source & MASK_ISRC2) {
++ DPRINTK(0,"\tISRC2 packet\n");
++
++ if (1) // untested
++ {
++ u8 d[ISRC_PACKET_HDR_LEN + ISRC_PACKET_DAT_LEN];
++ u8 crc = 0, i;
++
++ io_readn(REG_ISRC2_PACKET_TYPE, sizeof(d), d);
++ for (i = 0; i < sizeof(d); i++)
++ crc += d[i];
++ if (crc) {
++ printk(KERN_ERR "%s: ISRC2 packet CRC failed\n", KBUILD_MODNAME);
++ }
++ }
++ }
++ if (source & MASK_ISRC1) {
++ DPRINTK(0,"\tISRC1 packet\n");
++
++ if (1) // untested
++ {
++ u8 d[ISRC_PACKET_HDR_LEN + ISRC_PACKET_DAT_LEN];
++ u8 crc = 0, i;
++
++ io_readn(REG_ISRC1_PACKET_TYPE, sizeof(d), d);
++ for (i = 0; i < sizeof(d); i++)
++ crc += d[i];
++ if (crc) {
++ printk(KERN_ERR "%s: ISRC1 packet CRC failed\n", KBUILD_MODNAME);
++ } else {
++ DPRINTK(0,"\tISRC1 packet: type=%d ISRCCont=%d ISRCValid=%d "
++ "ISRCStatus=%d\n",
++ d[0],
++ (d[1] & 0x80) >> 7,
++ (d[1] & 0x40) >> 6,
++ (d[1] & 0x07)
++ );
++ }
++ }
++ }
++ if (source & MASK_ACP) {
++ DPRINTK(0,"\tAudio Content Protection (ACP) Packet\n");
++
++ if (1) // untested
++ {
++ u8 d[ACP_PACKET_HDR_LEN + ACP_PACKET_DAT_LEN];
++ u8 crc = 0, i;
++
++ io_readn(REG_ACP_PACKET_TYPE, sizeof(d), d);
++ for (i = 0; i < sizeof(d); i++)
++ crc += d[i];
++ if (crc) {
++ printk(KERN_ERR "%s: ACP packet CRC failed\n", KBUILD_MODNAME);
++ }
++ }
++ }
++#endif
++ if (source & MASK_DC_NO_GCP) {
++ DPRINTK(0,"\tGCP not received in 5 frames\n");
++ }
++ if (source & MASK_DC_PHASE) {
++ DPRINTK(0,"\tDeep color mode pixel phase needs update\n");
++ }
++ if (source & MASK_DC_MODE) {
++ reg = io_read(REG_DEEP_COLOR_MODE);
++ DPRINTK(0,"\tDeep color mode color depth changed: "
++ "pixelPackingPhase=0x%02x mode=%d\n",
++ reg & MASK_DC_PIXEL_PHASE,
++ reg & MASK_DC_COLOR_DEPTH);
++ }
++ }
++
++ /* Infoframe change interrupt source */
++ else if (interrupt_top_flags & INTERRUPT_INFO ) {
++ source = io_read(REG_INT_FLG_CLR_INFO);
++ io_write(REG_INT_FLG_CLR_INFO, source);
++ DPRINTK(0,"INFO: 0x%02x\n", source);
++
++ /* Vendor-Specific Infoframe */
++ if (source & MASK_VS_IF_OTHER_BK2 ||
++ source & MASK_VS_IF_OTHER_BK1 ||
++ source & MASK_VS_IF_HDMI)
++ {
++ u8 VSIUpdate, VSOther1Update, VSOther2Update;
++
++ /* Read the Update registers */
++ VSIUpdate = io_read(VS_HDMI_IF_UPDATE);
++ VSOther1Update = io_read(VS_BK1_IF_UPDATE);
++ VSOther2Update = io_read(VS_BK2_IF_UPDATE);
++
++ /* discard ITs that are too old */
++ if (VSIUpdate >= 3) source &= ~MASK_VS_IF_HDMI;
++ if (VSOther1Update >= 3) source &= ~MASK_VS_IF_OTHER_BK1;
++ if (VSOther2Update >= 3) source &= ~MASK_VS_IF_OTHER_BK2;
++
++ /* No new VSI has been received if these 3 registers are > 3 */
++ if (tda1997x->vsi_received
++ && (VSIUpdate>=3) && (VSOther1Update>=3) && (VSOther2Update>=3))
++ {
++ /* false VSI received */
++ tda1997x->vsi_received = 0;
++ }
++ else
++ {
++ tda1997x->vsi_received = 1;
++
++ if (source & MASK_VS_IF_HDMI) {
++ DPRINTK(0,"\tVendor-Specific InfoFrame: HDMI\n");
++ tda1997x_parse_infoframe(tda1997x, VS_HDMI_IF_TYPE);
++ }
++
++ if (source & MASK_VS_IF_OTHER_BK1) {
++ DPRINTK(0,"\tVendor-Specific InfoFrame: BK1\n");
++ tda1997x_parse_infoframe(tda1997x, VS_BK1_IF_TYPE);
++ }
++
++ if (source & MASK_VS_IF_OTHER_BK2) {
++ DPRINTK(0,"\tVendor-Specific InfoFrame: BK2\n");
++ tda1997x_parse_infoframe(tda1997x, VS_BK2_IF_TYPE);
++ }
++ }
++ }
++
++ /* MPEG Source Product infoframe */
++ if (source & MASK_MPS_IF) {
++ DPRINTK(0, "\tMPEG Source Product InfoFrame content change\n");
++ tda1997x_parse_infoframe(tda1997x, MPS_IF_TYPE);
++ }
++
++ /* Audio infoframe */
++ if (source & MASK_AUD_IF) {
++ DPRINTK(0, "\tAudio InfoFrame content change\n");
++ tda1997x_parse_infoframe(tda1997x, AUD_IF_TYPE);
++ }
++
++ /* Source Product Descriptor infoframe change */
++ if (source & MASK_SPD_IF) {
++ DPRINTK(0, "\tSource Product Descriptor InfoFrame change\n");
++ tda1997x_parse_infoframe(tda1997x, SPD_IF_TYPE);
++ }
++
++ /* Auxillary Video Information infoframe */
++ if (source & MASK_AVI_IF) {
++ DPRINTK(0, "\tAuxiliary Video information InfoFrame change\n");
++ tda1997x_parse_infoframe(tda1997x, AVI_IF_TYPE);
++ }
++ }
++
++ /* Audio interrupt source:
++ * freq change, DST,OBA,HBR,ASP flags, mute, FIFO err
++ */
++ else if (interrupt_top_flags & INTERRUPT_AUDIO ) {
++ source = io_read(REG_INT_FLG_CLR_AUDIO);
++ io_write(REG_INT_FLG_CLR_AUDIO, source);
++ DPRINTK(0,"AUDIO: 0x%02x\n", source);
++
++ if (source & MASK_ERROR_FIFO_PT || /* Audio FIFO pointer error */
++ source & MASK_MUTE_FLG) /* Audio mute */
++ {
++ if (source & MASK_MUTE_FLG) {
++ DPRINTK(0, "\tAudio MUTE\n");
++ } else {
++ DPRINTK(0, "\tAudio FIFO error\n");
++ }
++
++ /* audio reset audio FIFO */
++ reg = io_read(REG_SUS_STATUS);
++ if ((reg & MASK_SUS_STATE_VALUE) == LAST_STATE_REACHED) {
++ reg = io_read(REG_HDMI_INFO_RST);
++ reg |= MASK_SR_FIFO_FIFO_CTRL;
++ io_write(REG_HDMI_INFO_RST, reg);
++ reg &= ~MASK_SR_FIFO_FIFO_CTRL;
++ io_write(REG_HDMI_INFO_RST, reg);
++
++ /* reset channel status IT if present */
++ source &= ~(MASK_CH_STATE);
++ }
++ }
++ if (source & MASK_AUDIO_FREQ_FLG) {
++ DPRINTK(0, "\tAudio freq change\n");
++ tda1997x_get_audio_frequency(tda1997x);
++ printk(KERN_INFO "%s: Audio Frequency Change: %dHz\n",
++ KBUILD_MODNAME,
++ tda1997x->audio_mode.samplerate);
++ }
++ if (source & MASK_AUDIO_FLG) {
++ reg = io_read(REG_AUDIO_FLAGS);
++ DPRINTK(0, "\tAudio flag: 0x%02x\n", reg);
++ if (reg & 0x08) {
++ DPRINTK(0, "\t\tDTS packets detected\n");
++ }
++ if (reg & 0x04) {
++ DPRINTK(0, "\t\tOBA packets detected\n");
++ }
++ if (reg & 0x02) {
++ DPRINTK(0, "\t\tHBR packets detected\n");
++ }
++ if (reg & 0x01) {
++ DPRINTK(0, "\t\tAudio sample packets detected\n");
++ }
++ }
++ if (source & MASK_CH_STATE) {
++ DPRINTK(0, "\tChannel status\n");
++ }
++ if (source & MASK_UNMUTE_FIFO) {
++ DPRINTK(0, "\tUnmute audio FIFO\n");
++ }
++ }
++
++ /* HDCP interrupt source (content protection) */
++ if (interrupt_top_flags & INTERRUPT_HDCP) {
++ source = io_read(REG_INT_FLG_CLR_HDCP);
++ io_write(REG_INT_FLG_CLR_HDCP, source);
++ DPRINTK(0,"HDCP: 0x%02x\n", source);
++
++ /* reset MTP in use flag if set */
++ if (source & MASK_HDCP_MTP) {
++ DPRINTK(0, "\tHDCP MTP in use\n");
++ tda1997x->mptrw_in_progress = 0;
++ }
++ if (source & MASK_HDCP_DLMTP) {
++ DPRINTK(0,"\tHDCP end download MTP to SRAM\n");
++ }
++ if (source & MASK_HDCP_DLRAM) {
++ DPRINTK(0,"\tHDCP end download keys from SRAM to HDCP core\n");
++ }
++ if (source & MASK_HDCP_ENC) {
++ DPRINTK(0,"\tHDCP_ENC\n");
++ }
++ if (source & MASK_STATE_C5) {
++ DPRINTK(0,"\tHDCP State C5 reached\n");
++
++ /* REPEATER: mask AUDIO and IF interrupts to avoid IF during auth */
++ reg = io_read(REG_INT_MASK_TOP);
++ reg &= ~(INTERRUPT_AUDIO | INTERRUPT_INFO);
++ io_write(REG_INT_MASK_TOP, reg);
++ interrupt_top_flags &= (INTERRUPT_AUDIO | INTERRUPT_INFO);
++ }
++ if (source & MASK_AKSV) {
++ DPRINTK(0,"\tAKSV received (Start of Authentication)\n");
++ }
++ }
++
++ /* AFE interrupt source */
++ else if (interrupt_top_flags & INTERRUPT_AFE ) {
++ source = io_read(REG_INT_FLG_CLR_AFE);
++ io_write(REG_INT_FLG_CLR_AFE, source);
++ DPRINTK(0,"AFE: 0x%02x\n", source);
++ }
++ } while (interrupt_top_flags != 0);
++
++ /* we handled all alerts; re-enable level-triggered IRQ */
++ enable_irq(tda1997x->irq);
++}
++
++/** tda1997x interrupt handler
++ */
++static irqreturn_t tda1997x_isr(int irq, void *d)
++{
++ struct tda1997x_data *tda1997x = d;
++
++ /* disable level-triggered IRQs until we handle them */
++ disable_irq_nosync(irq);
++ schedule_work(&tda1997x->work);
++
++ return IRQ_HANDLED;
++}
++
++/***********************************************************************
++ * I2C client and driver.
++ ***********************************************************************/
++
++/**
++ * tda1997x I2C detach function.
++ * Called on rmmod.
++ *
++ * @param *client struct i2c_client*.
++ * @return Error code indicating success or failure.
++ */
++static int tda1997x_remove(struct i2c_client *client)
++{
++ struct tda1997x_data *tda1997x = i2c_get_clientdata(client);
++ dev_dbg(&tda1997x_data.client->dev,
++ "%s:Removing tda1997x video decoder @ 0x%02X from adapter %s\n",
++ __func__, client->addr << 1, client->adapter->name);
++
++ tda1997x_power_mode(&tda1997x_data, 0);
++
++ if (client->irq) {
++ devm_free_irq(&client->dev, client->irq, &tda1997x_data);
++ }
++
++/*
++ if (tda1997x->vid_child) {
++ platform_device_del(tda1997x->vid_child);
++ }
++*/
++
++ if (tda1997x->client_cec)
++ i2c_unregister_device(tda1997x->client_cec);
++
++ sysfs_remove_group(&client->dev.kobj, &attr_group);
++
++ if (dvddio_regulator)
++ regulator_disable(dvddio_regulator);
++ if (dvdd_regulator)
++ regulator_disable(dvdd_regulator);
++ if (avdd_regulator)
++ regulator_disable(avdd_regulator);
++
++ return 0;
++}
++
++
++static int tda1997x_regulator_enable(struct device *dev,
++ struct tda1997x_platform_data *pdata)
++{
++ int ret = 0;
++
++ dvddio_regulator = devm_regulator_get(dev, "DOVDD");
++ if (!IS_ERR(dvddio_regulator)) {
++ regulator_set_voltage(dvddio_regulator,
++ TDA1997X_VOLTAGE_DIGITAL_IO,
++ TDA1997X_VOLTAGE_DIGITAL_IO);
++ ret = regulator_enable(dvddio_regulator);
++ if (ret) {
++ dev_err(dev, "set io voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set io voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get io voltage\n");
++ }
++
++ dvdd_regulator = devm_regulator_get(dev, "DVDD");
++ if (!IS_ERR(dvdd_regulator)) {
++ ret = regulator_set_voltage(dvdd_regulator,
++ TDA1997X_VOLTAGE_DIGITAL_CORE,
++ TDA1997X_VOLTAGE_DIGITAL_CORE);
++ ret = regulator_enable(dvdd_regulator);
++ if (ret) {
++ dev_err(dev, "set core voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set core voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get core voltage\n");
++ }
++
++ avdd_regulator = devm_regulator_get(dev, "AVDD");
++ if (!IS_ERR(avdd_regulator)) {
++ ret = regulator_set_voltage(avdd_regulator,
++ TDA1997X_VOLTAGE_ANALOG,
++ TDA1997X_VOLTAGE_ANALOG);
++ ret = regulator_enable(avdd_regulator);
++ if (ret) {
++ dev_err(dev, "set analog voltage failed\n");
++ return ret;
++ } else {
++ dev_dbg(dev, "set analog voltage ok\n");
++ }
++ } else {
++ dev_warn(dev, "cannot get analog voltage\n");
++ }
++
++ return ret;
++}
++
++static int parse_vidout_fmt(const char *mode)
++{
++ int clkmode;
++ if (!strcmp(mode, "444"))
++ clkmode = VIDEOFMT_444;
++ else if (!strcmp(mode, "422_smp"))
++ clkmode = VIDEOFMT_422_SMP;
++ else if (!strcmp(mode, "422_ccir"))
++ clkmode = VIDEOFMT_422_CCIR;
++ else
++ clkmode = -EINVAL;
++
++ return clkmode;
++}
++
++static int parse_vidout_clkmode(const char *mode)
++{
++ int clkmode;
++ if (!strcmp(mode, "single_edge"))
++ clkmode = CLOCK_SINGLE_EDGE;
++ else if (!strcmp(mode, "dual_edge"))
++ clkmode = CLOCK_DUAL_EDGE;
++ else if (!strcmp(mode, "single_edge_toggled"))
++ clkmode = CLOCK_SINGLE_EDGE_TOGGLED;
++ else if (!strcmp(mode, "dual_edge_toggled"))
++ clkmode = CLOCK_DUAL_EDGE_TOGGLED;
++ else
++ clkmode = -EINVAL;
++
++ return clkmode;
++}
++
++static int parse_audout_fmt(const char *mode)
++{
++ int clkmode;
++ if (!strcmp(mode, "i2s16"))
++ clkmode = AUDIO_FMT_I2S16;
++ else if (!strcmp(mode, "i2s32"))
++ clkmode = AUDIO_FMT_I2S32;
++ else if (!strcmp(mode, "spdif"))
++ clkmode = AUDIO_FMT_SPDIF;
++ else if (!strcmp(mode, "oba"))
++ clkmode = AUDIO_FMT_OBA;
++ else if (!strcmp(mode, "i2s16_hbr_straight"))
++ clkmode = AUDIO_FMT_I2S16_HBR_STRAIGHT;
++ else if (!strcmp(mode, "i2s16_hbr_demux"))
++ clkmode = AUDIO_FMT_I2S16_HBR_DEMUX;
++ else if (!strcmp(mode, "i2s32_hbr_demux"))
++ clkmode = AUDIO_FMT_I2S32_HBR_DEMUX;
++ else if (!strcmp(mode, "dst"))
++ clkmode = AUDIO_FMT_DST;
++ else
++ clkmode = -EINVAL;
++
++ return clkmode;
++}
++
++static int tda1997x_get_of_property(struct device *dev,
++ struct tda1997x_platform_data *pdata)
++{
++ struct device_node *np = dev->of_node;
++ const char *vidout_fmt, *vidout_clk, *audout_fmt;
++ u32 hdcp, ddc_slave, blc, trc;
++ u32 port_configs;
++ u32 audout_clk, audout_layout, max_pixel_rate = 0;
++ int err;
++
++ /* defaults (use inverted vs/hs/de) */
++ /* TODO: add of bindings for these */
++ pdata->vidout_sel_vs = 1;
++ pdata->vidout_invert_vs =1;
++ pdata->vidout_sel_hs = 1;
++ pdata->vidout_invert_hs =1;
++ pdata->vidout_sel_de = 1;
++ pdata->vidout_invert_de =1;
++
++ /* enable HDCP */
++ err = of_property_read_u32(np, "hdcp", &hdcp);
++ if (err) {
++ dev_dbg(dev, "get of property hdcp fail\n");
++ return err;
++ }
++ /* DDC Slave address */
++ err = of_property_read_u32(np, "ddc_slave", &ddc_slave);
++ if (err) {
++ dev_dbg(dev, "get of property ddc_slave fail\n");
++ return err;
++ }
++
++ /* Video output mode */
++ err = of_property_read_string(np, "vidout_fmt", &vidout_fmt);
++ if (err) {
++ dev_dbg(dev, "get of property vidout_fmt fail\n");
++ return err;
++ }
++ /* insert timing codes (SAV/EAV) in stream */
++ err = of_property_read_u32(np, "vidout_trc", &trc);
++ if (err) {
++ dev_dbg(dev, "get of property vidout_trc fail\n");
++ return err;
++ }
++ /* insert blanking codes in stream */
++ err = of_property_read_u32(np, "vidout_blc", &blc);
++ if (err) {
++ dev_dbg(dev, "get of property vidout_blc fail\n");
++ return err;
++ }
++ /* video output clock mode */
++ err = of_property_read_string(np, "vidout_clkmode", &vidout_clk);
++ if (err) {
++ dev_dbg(dev, "get of property vidout_clkmode fail\n");
++ return err;
++ }
++ /* video output port config */
++ of_find_property(np, "vidout_portcfg", &port_configs);
++ err = of_property_read_u8_array(np, "vidout_portcfg",
++ pdata->vidout_port_config,
++ port_configs);
++ if (err) {
++ dev_dbg(dev, "get of property vidout_portcfg fail\n");
++ return err;
++ }
++ pdata->vidout_port_config_no = port_configs;
++ /* max pixrate */
++ of_property_read_u32(np, "max-pixel-rate", &max_pixel_rate);
++
++ /* audio output format */
++ err = of_property_read_string(np, "audout_fmt", &audout_fmt);
++ if (err) {
++ dev_dbg(dev, "get of property audout_fmt fail\n");
++ return err;
++ }
++ /* audio output sysclk */
++ err = of_property_read_u32(np, "audout_sysclk", &audout_clk);
++ if (err) {
++ dev_dbg(dev, "get of property audout_clkmode fail\n");
++ return err;
++ }
++ /* audio layout */
++ err = of_property_read_u32(np, "audout_layout", &audout_layout);
++ if (err) {
++ dev_dbg(dev, "get of property audout_layout fail\n");
++ return err;
++ }
++
++ pdata->hdcp = hdcp;
++ pdata->ddc_slave = ddc_slave;
++ pdata->vidout_format = parse_vidout_fmt(vidout_fmt);
++ pdata->vidout_trc = trc;
++ pdata->vidout_blc = blc;
++ pdata->vidout_clkmode = parse_vidout_clkmode(vidout_clk);
++ pdata->max_pixel_rate = max_pixel_rate;
++ pdata->audout_layout = audout_layout;
++ pdata->audout_format = parse_audout_fmt(audout_fmt);
++ switch (audout_clk) {
++ default:
++ case 128:
++ pdata->audout_sysclk = AUDIO_SYSCLK_128FS;
++ break;
++ case 256:
++ pdata->audout_sysclk = AUDIO_SYSCLK_256FS;
++ break;
++ case 512:
++ pdata->audout_sysclk = AUDIO_SYSCLK_512FS;
++ break;
++ }
++
++ return err;
++}
++
++/**
++ * tda1997x I2C probe function.
++ * Function set in i2c_driver struct.
++ * Called by insmod.
++ *
++ * @param *adapter I2C adapter descriptor.
++ *
++ * @return Error code indicating success or failure.
++ */
++static int tda1997x_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ int ret = 0;
++ int i;
++ u8 reg;
++ struct tda1997x_data *tda1997x = &tda1997x_data;
++ struct tda1997x_platform_data *pdata;
++ struct device *dev = &client->dev;
++
++ dev_dbg(dev, "%s\n", __func__);
++ pdata = devm_kzalloc(dev, sizeof(struct tda1997x_platform_data),
++ GFP_KERNEL);
++ if (!pdata)
++ return -ENOMEM;
++ dev->platform_data = pdata;
++
++ if (!client->irq) {
++ dev_err(dev, "get tda1997x of interrupt fail\n");
++ return -EINVAL;
++ }
++
++ ret = tda1997x_get_of_property(dev, pdata);
++ if (ret < 0) {
++ dev_err(dev, "get tda1997x of property fail\n");
++ return ret;
++ }
++
++ /* probe chip */
++/*
++ ret = i2c_smbus_read_byte_data(client, REG_CMTP_REG10 & 0xff);
++ if (ret < 0)
++ return -ENODEV;
++*/
++
++ tda1997x_regulator_enable(dev, pdata);
++
++ memset(tda1997x, 0, sizeof(tda1997x_data));
++ i2c_set_clientdata(client, tda1997x);
++ spin_lock_init(&tda1997x->lock);
++ tda1997x->page = 0xff;
++ tda1997x->client = client;
++ tda1997x->irq = client->irq;
++ tda1997x->pdata = pdata;
++ tda1997x->internal_edid = !pdata->external_edid;
++ INIT_WORK(&tda1997x->work, tda1997x_work);
++ mutex_init(&tda1997x->page_lock);
++ mutex_init(&tda1997x->cec_lock);
++ switch(pdata->audout_layout) {
++ case AUDIO_LAYOUT_FORCED_0:
++ tda1997x->audio_mode.channels = 2;
++ break;
++ case AUDIO_LAYOUT_FORCED_1:
++ tda1997x->audio_mode.channels = 8;
++ break;
++ default:
++ tda1997x->audio_mode.channels = 8;
++ break;
++ }
++ switch(pdata->audout_format) {
++ case AUDIO_FMT_I2S16:
++ tda1997x->audio_mode.samplesize = 2;
++ break;
++ case AUDIO_FMT_I2S32:
++ tda1997x->audio_mode.samplesize = 2;
++ break;
++ default:
++ tda1997x->audio_mode.samplesize = 0;
++ }
++
++ /* sysfs hooks */
++ ret = sysfs_create_group(&client->dev.kobj, &attr_group);
++ if (ret)
++ printk(KERN_ERR "%s: failed creating sysfs attrs\n", KBUILD_MODNAME);
++
++ tda1997x->colorspace = COLORSPACE_RGB;
++ tda1997x->colorimetry = COLORIMETRY_NONE;
++ tda1997x->resolutiontype = RESTYPE_SDTV;
++
++ /* disable/reset HDCP to get correct I2C access to Rx HDMI */
++ io_write(REG_MAN_SUS_HDMI_SEL, MAN_RST_HDCP | MAN_DIS_HDCP);
++
++ /* Read chip configuration*/
++ reg = io_read(REG_CMTP_REG10);
++ tda1997x->tmdsb_clk = (reg >> 6) & 0x01; /* use tmds clock B_inv for B */
++ tda1997x->tmdsb_soc = (reg >> 5) & 0x01; /* tmds of input B */
++ tda1997x->port_30bit = (reg >> 2) & 0x03; /* 30bit vs 24bit */
++ tda1997x->output_2p5 = (reg >> 1) & 0x01; /* output supply 2.5v */
++ tda1997x->cec_enabled = (reg >> 0) & 0x01; /* CEC enabled */
++ switch((reg >> 4) & 0x03) {
++ case 0x00:
++ tda1997x->chip = 19971;
++ tda1997x->input = INPUT_HDMI_A;
++ break;
++ case 0x01:
++ tda1997x->chip = 19972;
++ tda1997x->input = INPUT_AUTO_DIGITAL;
++ break;
++ case 0x02:
++ case 0x03:
++ tda1997x->chip = 19973;
++ tda1997x->input = INPUT_HDMI_A;
++ break;
++ }
++
++ /* read chip revision */
++ tda1997x->chip_revision = io_read(REG_CMTP_REG11);
++
++ /* if N2 version, reset compdel_bp as it may generate some small pixel
++ * shifts in case of embedded sync/or delay lower than 4 */
++ if (tda1997x->chip_revision != 0) {
++ io_write(REG_MAN_SUS_HDMI_SEL, 0x00);
++ io_write (REG_VDP_CTRL, 0x1f);
++ }
++
++ /* The CEC I2C address is not yet correct. We need to take into account
++ * possible config setting in SLAVE_ADDR register, however the Hw I2C address
++ */
++ tda1997x->cec_slave = 0x34 + ((io_read(REG_SLAVE_ADDR)>>4) & 0x03);
++
++ pr_info("NXP TDA%d N%d detected: %dbit VP%s\n",
++ tda1997x->chip,
++ tda1997x->chip_revision + 1,
++ (tda1997x->port_30bit)?30:24,
++ (tda1997x->cec_enabled)?", CEC ":"");
++ pr_info("video out format: %s\n", vidfmt_names[pdata->vidout_format]);
++ if (tda1997x->cec_enabled)
++ pr_info("CEC slave address 0x%02x\n", tda1997x->cec_slave);
++ if (tda1997x->pdata->max_pixel_rate)
++ pr_info("max pixel rate: %d MP/sec\n", pdata->max_pixel_rate);
++
++ /* Attach a second dummy i2c_client for CEC register access */
++ tda1997x->client_cec = i2c_new_dummy(client->adapter, tda1997x->cec_slave);
++ if (!tda1997x->client_cec) {
++ printk(KERN_ERR "%s: failed to register CEC client\n", KBUILD_MODNAME);
++ }
++
++ /* disable HPD */
++ io_write(REG_HPD_AUTO_CTRL, 0x08); /* hpd_unsel */
++
++ if (tda1997x->chip_revision == 0) {
++ io_write(REG_MAN_SUS_HDMI_SEL, MAN_DIS_HDCP | MAN_RST_HDCP);
++ io_write(REG_CGU_DEBUG_SEL, 0x08);
++ }
++
++ /* reset infoframe at end of start-up-sequencer */
++ io_write(REG_SUS_SET_RGB2, 0x06);
++ io_write(REG_SUS_SET_RGB3, 0x06);
++
++ /* update page 0 */
++ io_write(REG_RT_MAN_CTRL, 0x43);
++
++ /* CEC
++ */
++ /* enable sync measurement timing */
++ tda1997x_cec_write(REG_PWR_CONTROL & 0xff, 0x04);
++ /* adjust CEC clock divider */
++ tda1997x_cec_write(REG_OSC_DIVIDER & 0xff, 0x03);
++ tda1997x_cec_write(REG_EN_OSC_PERIOD_LSB & 0xff, 0xa0);
++ io_write(REG_TIMER_D, 0x54);
++ /* enable power switch - SRAM content is always valid
++ * (in case E-MTP is not or mis-programmed)
++ */
++ reg = tda1997x_cec_read(REG_CONTROL & 0xff);
++ reg |= 0x20;
++ tda1997x_cec_write(REG_CONTROL & 0xff, reg);
++ mdelay(50);
++
++ /* read the chip version */
++ reg = io_read(REG_VERSION);
++ /* get the chip configuration */
++ reg = io_read(REG_CMTP_REG10);
++
++ /* init interrupt masks we care about */
++ io_write(REG_INT_MASK_TOP, 0x7f); /* hdcp,audio,info,mode,rate,ddc,sus */
++ io_write(REG_INT_MASK_SUS, 0xa8); /* config_mtp,fmt,sus_end,sus_st */
++ io_write(REG_INT_MASK_DDC, 0x00); /* none */
++ io_write(REG_INT_MASK_RATE, 0x44); /* rate_b_st, rate_a_st */
++ io_write(REG_INT_MASK_MODE, 0xf9); /* hdmi_flg,gamut,isrc2,isrc1,acp,dc_mode */
++ io_write(REG_INT_MASK_INFO, 0x7f); /* mps_if,aud_if,spd_if,avi_if,
++ vs_if_other_bk2,vs_if_other_bk1,
++ vs_if_hdmi */
++ io_write(REG_INT_MASK_AUDIO,0x3f); /* audio_freq,audio_flg,mute_flg,
++ ch stat,unmount_fifo,fifo_err */
++ io_write(REG_INT_MASK_HDCP, 0x02); /* state_c5 */
++ io_write(REG_INT_MASK_AFE, 0x00); /* none */
++
++ /* clear all interrupts */
++ io_write(REG_INT_FLG_CLR_TOP, 0xff);
++ io_write(REG_INT_FLG_CLR_SUS, 0xff);
++ io_write(REG_INT_FLG_CLR_DDC, 0xff);
++ io_write(REG_INT_FLG_CLR_RATE, 0xff);
++ io_write(REG_INT_FLG_CLR_MODE, 0xff);
++ io_write(REG_INT_FLG_CLR_INFO, 0xff);
++ io_write(REG_INT_FLG_CLR_AUDIO, 0xff);
++ io_write(REG_INT_FLG_CLR_HDCP, 0xff);
++ io_write(REG_INT_FLG_CLR_AFE, 0xff);
++
++ /* init TMDS equalizer */
++ if (tda1997x->chip_revision == 0)
++ io_write(REG_CGU_DEBUG_SEL, 0x08);
++ io_write24(REG_CLK_MIN_RATE, CLK_MIN_RATE);
++ io_write24(REG_CLK_MAX_RATE, CLK_MAX_RATE);
++ if (tda1997x->chip_revision == 0)
++ io_write(REG_WDL_CFG, WDL_CFG_VAL);
++ /* DC filter */
++ io_write(REG_DEEP_COLOR_CTRL, DC_FILTER_VAL);
++
++ /* disable test pattern */
++ io_write(REG_SERVICE_MODE, 0x00);
++
++ /* update HDMI INFO CTRL */
++ io_write(REG_INFO_CTRL, 0xff);
++
++ /* write HDMI INFO EXCEED value */
++ io_write(REG_INFO_EXCEED, 3);
++
++ if (tda1997x->chip_revision == 0) {
++ /* clear HDMI mode flag in BCAPS (for N1) */
++ io_write(REG_CLK_CFG, 0x03);
++ io_write(REG_PON_OVR_EN, 0x01);
++ io_write(REG_PON_CBIAS, 0x01);
++ io_write(REG_PON_PLL, 0x01);
++
++ reg = io_read(REG_MODE_RECOVER_CFG1);
++ reg &= ~0x06;
++ reg |= 0x02;
++ io_write(REG_MODE_RECOVER_CFG1, reg);
++ io_write(REG_CLK_CFG, 0x00);
++ io_write(REG_PON_OVR_EN, 0x00);
++ reg = io_read(REG_MODE_RECOVER_CFG1);
++ reg &= ~0x06;
++ io_write(REG_MODE_RECOVER_CFG1, reg);
++ }
++
++ /* No HDCP acknowledge when HDCP is disabled
++ * and reset SUS to force format detection
++ */
++ tda1997x_hdmi_info_reset(NACK_HDCP, 1);
++ //tda1997x_hdmi_info_reset(NACK_HDCP, 0);
++
++ /* get key description seed in fuction of seed table if provded */
++ tda1997x_configure_mtp(tda1997x, MTP_START_READ); /* Start read */
++ reg = io_read(0x4000); /* read from MTP */
++ for (i = 0; i < RX_SEED_TABLE_LEN; i++) {
++ if ((rx_seed_table[i].seedVal == 0) && (rx_seed_table[i].lookUpVal == 0))
++ break;
++ else if (rx_seed_table[i].lookUpVal == reg) { /* MTP_DATA_LSB */
++ /* found seed replace seed in key_decryption_seed */
++ tda1997x->key_decryption_seed = rx_seed_table[i].seedVal;
++ break;
++ }
++ }
++ DPRINTK(0,"HDCP decryption seed:0x%04x\n", tda1997x->key_decryption_seed);
++
++ /* disable HDCP */
++ tda1997x_configure_hdcp(tda1997x, HDCP_DECRYPTKEY_ON, DISABLE,
++ tda1997x->pdata->ddc_slave, tda1997x->key_decryption_seed);
++
++ /* set the state machine */
++ tda1997x->state = STATE_INITIALIZED;
++
++ /* Set HPD low */
++ tda1997x_manual_hpd(tda1997x, HPD_LOW);
++
++ /* Configure receiver capabilities */
++ io_write(REG_HDCP_BCAPS, HDCP_HDMI | HDCP_FAST_REAUTH);
++
++ /* Configure HDMI
++ *
++ * HDMI_CTRL bits:
++ * 3:2 - mute_mode:
++ * 00: use control packet
++ * 01: mute off
++ * 10: mute on
++ * 1:0 - hdcp_mode:
++ * 00: auto
++ * 01: oess
++ * 10: eess
++ */
++ io_write(REG_HDMI_CTRL, 0x00); /* Auto HDCP mode, packet controlled mute */
++
++ /* Configure EDID
++ *
++ * EDID_ENABLE bits:
++ * 7 - nack_off
++ * 6 - edid_only
++ * 1 - edid_b_en
++ * 0 - edid_a_en
++ */
++ reg = io_read(REG_EDID_ENABLE);
++ if (!tda1997x->internal_edid)
++ reg &= ~0x83; /* EDID Nack ON */
++ else
++ reg |= 0x83; /* EDID Nack OFF */
++ io_write(REG_EDID_ENABLE, reg);
++
++ /* HDCP Activation */
++ if (pdata->hdcp) {
++ DPRINTK(0,"%s: Activating HDCP\n", __func__);
++
++ /* No HDCP acknowledge when HDCP is disabled */
++ tda1997x_hdmi_info_reset(NACK_HDCP, 0);
++
++ /* disable HDCP */
++ tda1997x_configure_hdcp(tda1997x, HDCP_DECRYPTKEY_ON, DISABLE,
++ tda1997x->pdata->ddc_slave, tda1997x->key_decryption_seed);
++
++ /* index first secret key */
++ io_write(REG_HDCP_KIDX, 0x00);
++
++ /* download MTP */
++ tda1997x_configure_mtp(tda1997x, MTP_START_DOWNLOAD);
++ mdelay(20);
++
++ /* enable HDCP */
++ tda1997x_configure_hdcp(tda1997x, HDCP_DECRYPTKEY_OFF, ENABLE,
++ tda1997x->pdata->ddc_slave, tda1997x->key_decryption_seed);
++
++ /* Enable HDCP acknowledge when HDCP is enabled */
++ //tda1997x_hdmi_info_reset(0x00, 0);
++
++ /* Configure HDCP error protection
++ */
++ DPRINTK(0,"Configure HDCP error protection\n");
++ /* delockDelay - Delay before delocking the word locker */
++ io_write(REG_DELOCK_DELAY, 0x07); /* delockDelay (7=max) */
++ /* HDCP_DE_CTRL bits:
++ * 7:6 - de_measurement_mode:
++ * 00: 1_VDP
++ * 01: 2_VDP
++ * 10: 3_VDP
++ * 11: 4_VDP
++ * 5 - de_regen_mode: 1-enable
++ * 4:3 - de_filter_sensitivity:
++ * 2:0 - de_composition_mode:
++ * 000: CH0
++ * 001: CH1
++ * 010: CH2
++ * 011: AND
++ * 100: OR
++ * 101: MIXED
++ */
++ io_write(REG_HDCP_DE_CTRL, 3<<3); /* de_filter_sensitivity=3 */
++ /* HDCP_EP_FILT_CTRL bits:
++ * 5:4 - ctl_filter_sensitivity
++ * 3:2 - vs_filter_sensitivity
++ * 1:0 - hs_filter_sensitivity
++ */
++ /* ctl_filter_sentivity = vs_filter_sensitivity = hs_filter_sensitivity = 3 */
++ io_write(REG_HDCP_EP_FILT_CTRL, (0x3<<4) | (0x3<<2) | 0x3);
++ }
++
++ /* reset start-up-sequencer to force format detection */
++ tda1997x_hdmi_info_reset(0x00, 1);
++ //tda1997x_hdmi_info_reset(0x00, 0);
++
++ /* Set HPD high */
++ tda1997x_manual_hpd(tda1997x, HPD_HIGH_OTHER);
++
++ /* Internal EDIDs are enabled - we can now load EDID */
++ if (tda1997x->internal_edid) {
++ /* Load EDID into embedded memory */
++ tda1997x_load_edid_data(edid_block);
++
++ /* Load DDC and RT data into embedded memory */
++ tda1997x_load_config_data(tda1997x, ddc_config0, rt_config);
++ }
++
++ /* Set HPD high (now that EDID is ready) */
++ tda1997x_manual_hpd(tda1997x, HPD_HIGH);
++
++ /* Select input */
++ tda1997x_select_input(tda1997x->input);
++
++ /* enable matrix conversion bypass (no conversion) */
++ io_write(REG_VDP_CTRL, io_read(REG_VDP_CTRL) | (1<<0));
++
++ /* set video output mode */
++ tda1997x_set_video_outputformat(tda1997x->pdata);
++ for (i = 0; i < tda1997x->pdata->vidout_port_config_no; i++)
++ io_write(REG_VP35_32_CTRL + i, tda1997x->pdata->vidout_port_config[i]);
++
++ /* configure audio output mode */
++ tda1997x_configure_audio_formatter(tda1997x->pdata, 0);
++ /* configure audio clock mode:
++ * Audio clock generation from Xtal: 128fs, 256fs, 512fs and
++ * Fs = 32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 172.4kHz, 192kHz
++ */
++ //io_write(REG_AUDIO_CLOCK_MODE, tda1997x->pdata->audio_sysclk);
++ io_write(REG_AUDIO_CLOCK_MODE, AUDIO_SYSCLK_128FS);
++
++ /* reset advanced infoframes (ISRC1/ISRC2/ACP) */
++ tda1997x_hdmi_info_reset(RESET_AI, 0);
++ //tda1997x_hdmi_info_reset(0x00, 0);
++ /* reset infoframe */
++ tda1997x_hdmi_info_reset(RESET_IF, 0);
++ //tda1997x_hdmi_info_reset(0x00, 0);
++ /* reset audio infoframes */
++ tda1997x_hdmi_info_reset(RESET_AUDIO, 0);
++ //tda1997x_hdmi_info_reset(0x00, 0);
++ /* reset gamut */
++ tda1997x_hdmi_info_reset(RESET_GAMUT, 0);
++ //tda1997x_hdmi_info_reset(0x00, 0);
++
++ /* get initial HDMI status */
++ tda1997x->hdmi_status = io_read(REG_HDMI_FLAGS);
++
++ /* get DEEP color mode */
++ reg = io_read(REG_DEEP_COLOR_MODE);
++
++ /* register interrupt handler */
++ if (client->irq) {
++ ret = devm_request_irq(&client->dev, client->irq, tda1997x_isr, 0,
++ "tda1997x_irq", tda1997x);
++ if (ret < 0) {
++ pr_err("%s:interrupt gpio%d registration failed, error=%d \n",
++ __func__, client->irq, ret);
++ }
++ pr_debug("registered irq%d\n", client->irq);
++ }
++
++ return ret;
++}
++
++static const struct i2c_device_id tda1997x_id[] = {
++ {"tda1997x", 0},
++ {},
++};
++
++MODULE_DEVICE_TABLE(i2c, tda1997x_id);
++
++//static const struct of_device_id tda1997x_dt_ids[] = {
++// { .compatible = "nxp,tda1997x", },
++// { /* sentinel */ }
++//};
++//MODULE_DEVICE_TABLE(of, tda1997x_dt_ids);
++
++static struct i2c_driver tda1997x_i2c_driver = {
++ .driver = {
++ .name = "tda1997x",
++ .owner = THIS_MODULE,
++ //.of_match_table = tda1997x_dt_ids,
++ },
++ .probe = tda1997x_probe,
++ .remove = tda1997x_remove,
++ .id_table = tda1997x_id,
++};
++
++/**
++ * tda1997x init function.
++ * Called on insmod.
++ *
++ * @return Error code indicating success or failure.
++ */
++static __init int tda1997x_init(void)
++{
++ u8 err = 0;
++
++ pr_debug("%s\n", __func__);
++
++ /* Tells the i2c driver what functions to call for this driver. */
++ err = i2c_add_driver(&tda1997x_i2c_driver);
++ if (err != 0)
++ pr_err("%s:driver registration failed, error=%d \n",
++ __func__, err);
++
++ return err;
++}
++
++/**
++ * tda1997x cleanup function.
++ * Called on rmmod.
++ *
++ * @return Error code indicating success or failure.
++ */
++static void __exit tda1997x_clean(void)
++{
++ dev_dbg(&tda1997x_data.client->dev, "%s\n", __func__);
++ i2c_del_driver(&tda1997x_i2c_driver);
++}
++
++module_init(tda1997x_init);
++module_exit(tda1997x_clean);
++
++MODULE_DESCRIPTION("Core driver for TDA1997X HDMI Receiver");
++MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/misc/sram.c linux-3.14.72/drivers/misc/sram.c
+--- linux-3.14.72.orig/drivers/misc/sram.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/misc/sram.c 2016-06-19 22:11:55.193147356 +0200
+@@ -29,7 +29,7 @@
+ #include <linux/spinlock.h>
+ #include <linux/genalloc.h>
+
+-#define SRAM_GRANULARITY 32
++#define SRAM_GRANULARITY 4096
+
+ struct sram_dev {
+ struct gen_pool *pool;
+diff -Nur linux-3.14.72.orig/drivers/mmc/card/block.c linux-3.14.72/drivers/mmc/card/block.c
+--- linux-3.14.72.orig/drivers/mmc/card/block.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/card/block.c 2016-06-19 22:11:55.193147356 +0200
+@@ -2056,7 +2056,15 @@
+ * index anymore so we keep track of a name index.
+ */
+ if (!subname) {
+- md->name_idx = find_first_zero_bit(name_use, max_devices);
++ int idx;
++
++ idx = mmc_get_reserved_index(card->host);
++ if (idx >= 0 && !test_bit(idx, name_use))
++ md->name_idx = idx;
++ else
++ md->name_idx = find_next_zero_bit(name_use, max_devices,
++ mmc_first_nonreserved_index());
++
+ __set_bit(md->name_idx, name_use);
+ } else
+ md->name_idx = ((struct mmc_blk_data *)
+@@ -2344,6 +2352,10 @@
+ *
+ * N.B. This doesn't affect SD cards.
+ */
++ MMC_FIXUP("SDMB-32", CID_MANFID_SANDISK, CID_OEMID_ANY, add_quirk_mmc,
++ MMC_QUIRK_BLK_NO_CMD23),
++ MMC_FIXUP("SDM032", CID_MANFID_SANDISK, CID_OEMID_ANY, add_quirk_mmc,
++ MMC_QUIRK_BLK_NO_CMD23),
+ MMC_FIXUP("MMC08G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_BLK_NO_CMD23),
+ MMC_FIXUP("MMC16G", CID_MANFID_TOSHIBA, CID_OEMID_ANY, add_quirk_mmc,
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/core.c linux-3.14.72/drivers/mmc/core/core.c
+--- linux-3.14.72.orig/drivers/mmc/core/core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/core.c 2016-06-19 22:11:55.193147356 +0200
+@@ -13,11 +13,14 @@
+ #include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
++#include <linux/clk.h>
+ #include <linux/completion.h>
+ #include <linux/device.h>
+ #include <linux/delay.h>
++#include <linux/of.h>
+ #include <linux/pagemap.h>
+ #include <linux/err.h>
++#include <linux/gpio.h>
+ #include <linux/leds.h>
+ #include <linux/scatterlist.h>
+ #include <linux/log2.h>
+@@ -1434,18 +1437,20 @@
+ pr_warning("%s: cannot verify signal voltage switch\n",
+ mmc_hostname(host));
+
++ mmc_host_clk_hold(host);
++
+ cmd.opcode = SD_SWITCH_VOLTAGE;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
+
+ err = mmc_wait_for_cmd(host, &cmd, 0);
+ if (err)
+- return err;
++ goto err_command;
+
+- if (!mmc_host_is_spi(host) && (cmd.resp[0] & R1_ERROR))
+- return -EIO;
+-
+- mmc_host_clk_hold(host);
++ if (!mmc_host_is_spi(host) && (cmd.resp[0] & R1_ERROR)) {
++ err = -EIO;
++ goto err_command;
++ }
+ /*
+ * The card should drive cmd and dat[0:3] low immediately
+ * after the response of cmd11, but wait 1 ms to be sure
+@@ -1494,6 +1499,7 @@
+ mmc_power_cycle(host, ocr);
+ }
+
++err_command:
+ mmc_host_clk_release(host);
+
+ return err;
+@@ -1521,6 +1527,43 @@
+ mmc_host_clk_release(host);
+ }
+
++static void mmc_card_power_up(struct mmc_host *host)
++{
++ int i;
++ struct gpio_desc **gds = host->card_reset_gpios;
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ if (gds[i]) {
++ dev_dbg(host->parent, "Asserting reset line %d", i);
++ gpiod_set_value(gds[i], 1);
++ }
++ }
++
++ if (host->card_regulator) {
++ dev_dbg(host->parent, "Enabling external regulator");
++ if (regulator_enable(host->card_regulator))
++ dev_err(host->parent, "Failed to enable external regulator");
++ }
++
++ if (host->card_clk) {
++ dev_dbg(host->parent, "Enabling external clock");
++ clk_prepare_enable(host->card_clk);
++ }
++
++ /* 2ms delay to let clocks and power settle */
++ mmc_delay(20);
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ if (gds[i]) {
++ dev_dbg(host->parent, "Deasserting reset line %d", i);
++ gpiod_set_value(gds[i], 0);
++ }
++ }
++
++ /* 2ms delay to after reset release */
++ mmc_delay(20);
++}
++
+ /*
+ * Apply power to the MMC stack. This is a two-stage process.
+ * First, we enable power to the card without the clock running.
+@@ -1537,6 +1580,9 @@
+ if (host->ios.power_mode == MMC_POWER_ON)
+ return;
+
++ /* Power up the card/module first, if needed */
++ mmc_card_power_up(host);
++
+ mmc_host_clk_hold(host);
+
+ host->ios.vdd = fls(ocr) - 1;
+@@ -1606,7 +1652,7 @@
+ {
+ mmc_power_off(host);
+ /* Wait at least 1 ms according to SD spec */
+- mmc_delay(1);
++ mmc_delay(3);
+ mmc_power_up(host, ocr);
+ }
+
+@@ -2008,6 +2054,7 @@
+ unsigned int arg)
+ {
+ unsigned int rem, to = from + nr;
++ int err;
+
+ if (!(card->host->caps & MMC_CAP_ERASE) ||
+ !(card->csd.cmdclass & CCC_ERASE))
+@@ -2058,6 +2105,23 @@
+ /* 'from' and 'to' are inclusive */
+ to -= 1;
+
++ /*
++ * Special case where only one erase-group fits in the timeout budget:
++ * If the region crosses an erase-group boundary on this particular
++ * case, we will be trimming more than one erase-group which, does not
++ * fit in the timeout budget of the controller, so we need to split it
++ * and call mmc_do_erase() twice if necessary. This special case is
++ * identified by the card->eg_boundary flag.
++ */
++ if ((arg & MMC_TRIM_ARGS) && (card->eg_boundary) &&
++ (from % card->erase_size)) {
++ rem = card->erase_size - (from % card->erase_size);
++ err = mmc_do_erase(card, from, from + rem - 1, arg);
++ from += rem;
++ if ((err) || (to <= from))
++ return err;
++ }
++
+ return mmc_do_erase(card, from, to, arg);
+ }
+ EXPORT_SYMBOL(mmc_erase);
+@@ -2152,16 +2216,28 @@
+ if (!qty)
+ return 0;
+
++ /*
++ * When specifying a sector range to trim, chances are we might cross
++ * an erase-group boundary even if the amount of sectors is less than
++ * one erase-group.
++ * If we can only fit one erase-group in the controller timeout budget,
++ * we have to care that erase-group boundaries are not crossed by a
++ * single trim operation. We flag that special case with "eg_boundary".
++ * In all other cases we can just decrement qty and pretend that we
++ * always touch (qty + 1) erase-groups as a simple optimization.
++ */
+ if (qty == 1)
+- return 1;
++ card->eg_boundary = 1;
++ else
++ qty--;
+
+ /* Convert qty to sectors */
+ if (card->erase_shift)
+- max_discard = --qty << card->erase_shift;
++ max_discard = qty << card->erase_shift;
+ else if (mmc_card_sd(card))
+- max_discard = qty;
++ max_discard = qty + 1;
+ else
+- max_discard = --qty * card->erase_size;
++ max_discard = qty * card->erase_size;
+
+ return max_discard;
+ }
+@@ -2715,6 +2791,41 @@
+ init_waitqueue_head(&host->context_info.wait);
+ }
+
++static int __mmc_max_reserved_idx = -1;
++
++/**
++ * mmc_first_nonreserved_index() - get the first index that is not reserved
++ */
++int mmc_first_nonreserved_index(void)
++{
++ return __mmc_max_reserved_idx + 1;
++}
++
++/**
++ * mmc_get_reserved_index() - get the index reserved for this host
++ *
++ * Return: The index reserved for this host or negative error value if
++ * no index is reserved for this host
++ */
++int mmc_get_reserved_index(struct mmc_host *host)
++{
++ return of_alias_get_id(host->parent->of_node, "mmc");
++}
++
++static void mmc_of_reserve_idx(void)
++{
++ int max;
++
++ max = of_alias_max_index("mmc");
++ if (max < 0)
++ return;
++
++ __mmc_max_reserved_idx = max;
++
++ pr_debug("MMC: reserving %d slots for of aliases\n",
++ __mmc_max_reserved_idx + 1);
++}
++
+ static int __init mmc_init(void)
+ {
+ int ret;
+@@ -2723,6 +2834,8 @@
+ if (!workqueue)
+ return -ENOMEM;
+
++ mmc_of_reserve_idx();
++
+ ret = mmc_register_bus();
+ if (ret)
+ goto destroy_workqueue;
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/debugfs.c linux-3.14.72/drivers/mmc/core/debugfs.c
+--- linux-3.14.72.orig/drivers/mmc/core/debugfs.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/debugfs.c 2016-06-19 22:11:55.197147093 +0200
+@@ -135,6 +135,9 @@
+ case MMC_TIMING_UHS_DDR50:
+ str = "sd uhs DDR50";
+ break;
++ case MMC_TIMING_MMC_DDR52:
++ str = "mmc DDR52";
++ break;
+ case MMC_TIMING_MMC_HS200:
+ str = "mmc high-speed SDR200";
+ break;
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/host.c linux-3.14.72/drivers/mmc/core/host.c
+--- linux-3.14.72.orig/drivers/mmc/core/host.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/host.c 2016-06-19 22:11:55.197147093 +0200
+@@ -12,14 +12,18 @@
+ * MMC host class device management
+ */
+
++#include <linux/kernel.h>
++#include <linux/clk.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
++#include <linux/gpio/consumer.h>
+ #include <linux/idr.h>
+ #include <linux/of.h>
+ #include <linux/of_gpio.h>
+ #include <linux/pagemap.h>
+ #include <linux/export.h>
+ #include <linux/leds.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ #include <linux/suspend.h>
+
+@@ -439,6 +443,68 @@
+
+ EXPORT_SYMBOL(mmc_of_parse);
+
++int mmc_max_reserved_idx(void);
++
++static int mmc_of_parse_child(struct mmc_host *host)
++{
++ struct device_node *np;
++ struct clk *clk;
++ int i;
++
++ if (!host->parent || !host->parent->of_node)
++ return 0;
++
++ np = host->parent->of_node;
++
++ host->card_regulator = regulator_get(host->parent, "card-external-vcc");
++ if (IS_ERR(host->card_regulator)) {
++ if (PTR_ERR(host->card_regulator) == -EPROBE_DEFER)
++ return PTR_ERR(host->card_regulator);
++ host->card_regulator = NULL;
++ }
++
++ /* Parse card power/reset/clock control */
++ if (of_find_property(np, "card-reset-gpios", NULL)) {
++ struct gpio_desc *gpd;
++ int level = 0;
++
++ /*
++ * If the regulator is enabled, then we can hold the
++ * card in reset with an active high resets. Otherwise,
++ * hold the resets low.
++ */
++ if (host->card_regulator && regulator_is_enabled(host->card_regulator))
++ level = 1;
++
++ for (i = 0; i < ARRAY_SIZE(host->card_reset_gpios); i++) {
++ gpd = devm_gpiod_get_index(host->parent, "card-reset", i);
++ if (IS_ERR(gpd)) {
++ if (PTR_ERR(gpd) == -EPROBE_DEFER)
++ return PTR_ERR(gpd);
++ break;
++ }
++ gpiod_direction_output(gpd, gpiod_is_active_low(gpd) | level);
++ host->card_reset_gpios[i] = gpd;
++ }
++
++ gpd = devm_gpiod_get_index(host->parent, "card-reset", ARRAY_SIZE(host->card_reset_gpios));
++ if (!IS_ERR(gpd)) {
++ dev_warn(host->parent, "More reset gpios than we can handle");
++ gpiod_put(gpd);
++ }
++ }
++
++ clk = of_clk_get_by_name(np, "card_ext_clock");
++ if (IS_ERR(clk)) {
++ if (PTR_ERR(clk) == -EPROBE_DEFER)
++ return PTR_ERR(clk);
++ clk = NULL;
++ }
++ host->card_clk = clk;
++
++ return 0;
++}
++
+ /**
+ * mmc_alloc_host - initialise the per-host structure.
+ * @extra: sizeof private data structure
+@@ -450,6 +516,7 @@
+ {
+ int err;
+ struct mmc_host *host;
++ int alias_id, min_idx, max_idx;
+
+ host = kzalloc(sizeof(struct mmc_host) + extra, GFP_KERNEL);
+ if (!host)
+@@ -459,7 +526,18 @@
+ host->rescan_disable = 1;
+ idr_preload(GFP_KERNEL);
+ spin_lock(&mmc_host_lock);
+- err = idr_alloc(&mmc_host_idr, host, 0, 0, GFP_NOWAIT);
++
++ host->parent = dev;
++ alias_id = mmc_get_reserved_index(host);
++ if (alias_id >= 0) {
++ min_idx = alias_id;
++ max_idx = alias_id + 1;
++ } else {
++ min_idx = mmc_first_nonreserved_index();
++ max_idx = 0;
++ }
++
++ err = idr_alloc(&mmc_host_idr, host, min_idx, max_idx, GFP_NOWAIT);
+ if (err >= 0)
+ host->index = err;
+ spin_unlock(&mmc_host_lock);
+@@ -469,7 +547,6 @@
+
+ dev_set_name(&host->class_dev, "mmc%d", host->index);
+
+- host->parent = dev;
+ host->class_dev.parent = dev;
+ host->class_dev.class = &mmc_host_class;
+ device_initialize(&host->class_dev);
+@@ -518,6 +595,10 @@
+ {
+ int err;
+
++ err = mmc_of_parse_child(host);
++ if (err)
++ return err;
++
+ WARN_ON((host->caps & MMC_CAP_SDIO_IRQ) &&
+ !host->ops->enable_sdio_irq);
+
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/mmc.c linux-3.14.72/drivers/mmc/core/mmc.c
+--- linux-3.14.72.orig/drivers/mmc/core/mmc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/mmc.c 2016-06-19 22:11:55.197147093 +0200
+@@ -320,6 +320,10 @@
+ mmc_card_set_blockaddr(card);
+ }
+
++ card->ext_csd.boot_info = ext_csd[EXT_CSD_BOOT_INFO];
++ card->ext_csd.boot_size = ext_csd[EXT_CSD_BOOT_MULT];
++ card->ext_csd.boot_bus_width = ext_csd[EXT_CSD_BOOT_BUS_WIDTH];
++
+ card->ext_csd.raw_card_type = ext_csd[EXT_CSD_CARD_TYPE];
+ mmc_select_card_type(card);
+
+@@ -662,6 +666,372 @@
+ return err;
+ }
+
++static ssize_t mmc_boot_info_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ char *boot_partition[8] = {
++ "Device not boot enabled",
++ "Boot partition 1 enabled",
++ "Boot partition 2 enabled",
++ "Reserved",
++ "Reserved",
++ "Reserved",
++ "Reserved",
++ "User area enabled for boot"};
++
++ char *bus_width[4] = {
++ "x1 (sdr) or x4 (ddr) bus width in boot operation mode",
++ "x4 (sdr/ddr) bus width in boot operation mode",
++ "x8 (sdr/ddr) bus width in boot operation mode",
++ "Reserved"};
++
++ char *boot_mode[4] = {
++ "Use single data rate + backward compatible timings in boot operation",
++ "Use single data rate + high speed timings in boot operation mode",
++ "Use dual data rate in boot operation",
++ "Reserved"};
++
++ int partition;
++ int width;
++ int mode;
++ int err;
++ u8 *ext_csd = NULL;
++ struct mmc_card *card = container_of(dev, struct mmc_card, dev);
++
++ /* read it again because user may change it */
++ mmc_claim_host(card->host);
++ err = mmc_get_ext_csd(card, &ext_csd);
++ mmc_release_host(card->host);
++ if (err || !ext_csd) {
++ pr_err("%s: failed to get ext_csd, err=%d\n",
++ mmc_hostname(card->host),
++ err);
++ return err;
++ }
++
++ mmc_read_ext_csd(card, ext_csd);
++ mmc_free_ext_csd(ext_csd);
++
++ partition = (card->ext_csd.part_config >> 3) & 0x7;
++ width = card->ext_csd.boot_bus_width & 0x3;
++ mode = (card->ext_csd.boot_bus_width >> 3) & 0x3;
++
++ return sprintf(buf,
++ "boot_info:0x%02x;\n"
++ " ALT_BOOT_MODE:%x - %s\n"
++ " DDR_BOOT_MODE:%x - %s\n"
++ " HS_BOOTMODE:%x - %s\n"
++ "boot_size:%04dKB\n"
++ "boot_partition:0x%02x;\n"
++ " BOOT_ACK:%x - %s\n"
++ " BOOT_PARTITION-ENABLE: %x - %s\n"
++ "boot_bus:0x%02x\n"
++ " BOOT_MODE:%x - %s\n"
++ " RESET_BOOT_BUS_WIDTH:%x - %s\n"
++ " BOOT_BUS_WIDTH:%x - %s\n",
++
++ card->ext_csd.boot_info,
++ !!(card->ext_csd.boot_info & 0x1),
++ (card->ext_csd.boot_info & 0x1) ?
++ "Supports alternate boot method" :
++ "Does not support alternate boot method",
++ !!(card->ext_csd.boot_info & 0x2),
++ (card->ext_csd.boot_info & 0x2) ?
++ "Supports alternate dual data rate during boot" :
++ "Does not support dual data rate during boot",
++ !!(card->ext_csd.boot_info & 0x4),
++ (card->ext_csd.boot_info & 0x4) ?
++ "Supports high speed timing during boot" :
++ "Does not support high speed timing during boot",
++
++ card->ext_csd.boot_size * 128,
++
++ card->ext_csd.part_config,
++ !!(card->ext_csd.part_config & 0x40),
++ (card->ext_csd.part_config & 0x40) ?
++ "Boot acknowledge sent during boot operation" :
++ "No boot acknowledge sent",
++ partition,
++ boot_partition[partition],
++
++ card->ext_csd.boot_bus_width,
++ mode,
++ boot_mode[mode],
++ !!(card->ext_csd.boot_bus_width & 0x4),
++ (card->ext_csd.boot_bus_width & 0x4) ?
++ "Retain boot bus width and boot mode after boot operation" :
++ "Reset bus width to x1, single data rate and backward"
++ "compatible timings after boot operation",
++ width,
++ bus_width[width]);
++}
++
++/* set up boot partitions */
++static ssize_t
++setup_boot_partitions(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int err, busy = 0;
++ u32 part;
++ u8 *ext_csd, boot_config;
++ struct mmc_command cmd;
++ struct mmc_card *card = container_of(dev, struct mmc_card, dev);
++
++ BUG_ON(!card);
++
++ sscanf(buf, "%d\n", &part);
++
++ if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
++ pr_err("%s: invalid mmc version" \
++ " mmc version is below version 4!)\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ /* it's a normal SD/MMC but user request to configure boot partition */
++ if (card->ext_csd.boot_size <= 0) {
++ pr_err("%s: fail to send SWITCH command to card " \
++ "to update boot_config of the EXT_CSD!\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ /*
++ * partition must be -
++ * 0 - user area
++ * 1 - boot partition 1
++ * 2 - boot partition 2
++ * DO NOT switch the partitions that used to be accessed
++ * in OS layer HERE
++ */
++ if (part & EXT_CSD_BOOT_PARTITION_ACCESS_MASK) {
++ pr_err("%s: DO NOT switch the partitions that used to be\n" \
++ " accessed in OS layer HERE. please following the\n" \
++ " guidance of Documentation/mmc/mmc-dev-parts.txt.\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ ext_csd = kmalloc(512, GFP_KERNEL);
++ if (!ext_csd) {
++ pr_err("%s: could not allocate a buffer to " \
++ "receive the ext_csd.\n", mmc_hostname(card->host));
++ return -ENOMEM;
++ }
++
++ mmc_claim_host(card->host);
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: unable to read EXT_CSD.\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* enable the boot partition in boot mode */
++ /* boot enable be -
++ * 0x00 - disable boot enable.
++ * 0x08 - boot partition 1 is enabled for boot.
++ * 0x10 - boot partition 2 is enabled for boot.
++ * 0x38 - User area is enabled for boot.
++ */
++ switch (part & EXT_CSD_BOOT_PARTITION_ENABLE_MASK) {
++ case 0:
++ boot_config = (ext_csd[EXT_CSD_PART_CONFIG]
++ & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK
++ & ~EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ case EXT_CSD_BOOT_PARTITION_PART1:
++ boot_config = ((ext_csd[EXT_CSD_PART_CONFIG]
++ & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK)
++ | EXT_CSD_BOOT_PARTITION_PART1
++ | EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ case EXT_CSD_BOOT_PARTITION_PART2:
++ boot_config = ((ext_csd[EXT_CSD_PART_CONFIG]
++ & ~EXT_CSD_BOOT_PARTITION_ENABLE_MASK)
++ | EXT_CSD_BOOT_PARTITION_PART2
++ | EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ case EXT_CSD_BOOT_PARTITION_ENABLE_MASK:
++ boot_config = ((ext_csd[EXT_CSD_PART_CONFIG]
++ | EXT_CSD_BOOT_PARTITION_ENABLE_MASK)
++ & ~EXT_CSD_BOOT_ACK_ENABLE);
++ break;
++ default:
++ pr_err("%s: wrong boot config parameter" \
++ " 00 (disable boot), 08 (enable boot1)," \
++ "16 (enable boot2), 56 (User area)\n",
++ mmc_hostname(card->host));
++ err = -EINVAL;
++ goto err_rtn;
++ }
++
++ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
++ EXT_CSD_PART_CONFIG, boot_config, card->ext_csd.part_time);
++ if (err) {
++ pr_err("%s: fail to send SWITCH command to card " \
++ "to update boot_config of the EXT_CSD!\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* waiting for the card to finish the busy state */
++ do {
++ memset(&cmd, 0, sizeof(struct mmc_command));
++
++ cmd.opcode = MMC_SEND_STATUS;
++ cmd.arg = card->rca << 16;
++ cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
++
++ err = mmc_wait_for_cmd(card->host, &cmd, 0);
++ if (err || busy > 100) {
++ pr_err("%s: failed to wait for" \
++ "the busy state to end.\n",
++ mmc_hostname(card->host));
++ break;
++ }
++
++ if (!busy && !(cmd.resp[0] & R1_READY_FOR_DATA)) {
++ pr_info("%s: card is in busy state" \
++ "pls wait for busy state to end.\n",
++ mmc_hostname(card->host));
++ }
++ busy++;
++ } while (!(cmd.resp[0] & R1_READY_FOR_DATA));
++
++ /* Now check whether it works */
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: %d unable to re-read EXT_CSD.\n",
++ mmc_hostname(card->host), err);
++ goto err_rtn;
++ }
++
++ card->ext_csd.part_config = ext_csd[EXT_CSD_PART_CONFIG];
++
++err_rtn:
++ mmc_release_host(card->host);
++ kfree(ext_csd);
++ if (err)
++ return err;
++ else
++ return count;
++}
++
++/* configure the boot bus */
++static ssize_t
++setup_boot_bus(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ int err, busy = 0;
++ u32 boot_bus, new_bus;
++ u8 *ext_csd;
++ struct mmc_command cmd;
++ struct mmc_card *card = container_of(dev, struct mmc_card, dev);
++
++ BUG_ON(!card);
++
++ sscanf(buf, "%d\n", &boot_bus);
++
++ if (card->csd.mmca_vsn < CSD_SPEC_VER_4) {
++ pr_err("%s: invalid mmc version" \
++ " mmc version is below version 4!)\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ /* it's a normal SD/MMC but user request to configure boot bus */
++ if (card->ext_csd.boot_size <= 0) {
++ pr_err("%s: this is a normal SD/MMC card" \
++ " but you request to configure boot bus !\n",
++ mmc_hostname(card->host));
++ return -EINVAL;
++ }
++
++ ext_csd = kmalloc(512, GFP_KERNEL);
++ if (!ext_csd) {
++ pr_err("%s: could not allocate a buffer to " \
++ "receive the ext_csd.\n", mmc_hostname(card->host));
++ return -ENOMEM;
++ }
++
++ mmc_claim_host(card->host);
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: unable to read EXT_CSD.\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* Configure the boot bus width when boot partition is enabled */
++ if (((boot_bus & EXT_CSD_BOOT_BUS_WIDTH_MODE_MASK) >> 3) > 2
++ || (boot_bus & EXT_CSD_BOOT_BUS_WIDTH_WIDTH_MASK) > 2
++ || (boot_bus & ~EXT_CSD_BOOT_BUS_WIDTH_MASK) > 0) {
++ pr_err("%s: Invalid inputs!\n",
++ mmc_hostname(card->host));
++ err = -EINVAL;
++ goto err_rtn;
++ }
++
++ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
++ EXT_CSD_BOOT_BUS_WIDTH, boot_bus, card->ext_csd.part_time);
++ if (err) {
++ pr_err("%s: fail to send SWITCH command to card " \
++ "to update boot_config of the EXT_CSD!\n",
++ mmc_hostname(card->host));
++ goto err_rtn;
++ }
++
++ /* waiting for the card to finish the busy state */
++ do {
++ memset(&cmd, 0, sizeof(struct mmc_command));
++
++ cmd.opcode = MMC_SEND_STATUS;
++ cmd.arg = card->rca << 16;
++ cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
++
++ err = mmc_wait_for_cmd(card->host, &cmd, 0);
++ if (err || busy > 100) {
++ pr_err("%s: failed to wait for" \
++ "the busy state to end.\n",
++ mmc_hostname(card->host));
++ break;
++ }
++
++ if (!busy && !(cmd.resp[0] & R1_READY_FOR_DATA)) {
++ pr_info("%s: card is in busy state" \
++ "pls wait for busy state to end.\n",
++ mmc_hostname(card->host));
++ }
++ busy++;
++ } while (!(cmd.resp[0] & R1_READY_FOR_DATA));
++
++ /* Now check whether it works */
++ err = mmc_send_ext_csd(card, ext_csd);
++ if (err) {
++ pr_err("%s: %d unable to re-read EXT_CSD.\n",
++ mmc_hostname(card->host), err);
++ goto err_rtn;
++ }
++
++ new_bus = ext_csd[EXT_CSD_BOOT_BUS_WIDTH];
++ if (boot_bus != new_bus) {
++ pr_err("%s: after SWITCH, current boot bus mode %d" \
++ " is not same as requested bus mode %d!\n",
++ mmc_hostname(card->host), new_bus, boot_bus);
++ goto err_rtn;
++ }
++ card->ext_csd.boot_bus_width = ext_csd[EXT_CSD_BOOT_BUS_WIDTH];
++
++err_rtn:
++ mmc_release_host(card->host);
++ mmc_free_ext_csd(ext_csd);
++ if (err)
++ return err;
++ else
++ return count;
++}
++
+ MMC_DEV_ATTR(cid, "%08x%08x%08x%08x\n", card->raw_cid[0], card->raw_cid[1],
+ card->raw_cid[2], card->raw_cid[3]);
+ MMC_DEV_ATTR(csd, "%08x%08x%08x%08x\n", card->raw_csd[0], card->raw_csd[1],
+@@ -681,6 +1051,9 @@
+ MMC_DEV_ATTR(enhanced_area_size, "%u\n", card->ext_csd.enhanced_area_size);
+ MMC_DEV_ATTR(raw_rpmb_size_mult, "%#x\n", card->ext_csd.raw_rpmb_size_mult);
+ MMC_DEV_ATTR(rel_sectors, "%#x\n", card->ext_csd.rel_sectors);
++DEVICE_ATTR(boot_info, S_IRUGO, mmc_boot_info_show, NULL);
++DEVICE_ATTR(boot_config, S_IWUGO, NULL, setup_boot_partitions);
++DEVICE_ATTR(boot_bus_config, S_IWUGO, NULL, setup_boot_bus);
+
+ static struct attribute *mmc_std_attrs[] = {
+ &dev_attr_cid.attr,
+@@ -699,6 +1072,9 @@
+ &dev_attr_enhanced_area_size.attr,
+ &dev_attr_raw_rpmb_size_mult.attr,
+ &dev_attr_rel_sectors.attr,
++ &dev_attr_boot_info.attr,
++ &dev_attr_boot_config.attr,
++ &dev_attr_boot_bus_config.attr,
+ NULL,
+ };
+
+@@ -1268,7 +1644,7 @@
+ goto err;
+ }
+ mmc_card_set_ddr_mode(card);
+- mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50);
++ mmc_set_timing(card->host, MMC_TIMING_MMC_DDR52);
+ mmc_set_bus_width(card->host, bus_width);
+ }
+ }
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/mmc_ops.c linux-3.14.72/drivers/mmc/core/mmc_ops.c
+--- linux-3.14.72.orig/drivers/mmc/core/mmc_ops.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/mmc_ops.c 2016-06-19 22:11:55.197147093 +0200
+@@ -445,6 +445,12 @@
+ return 0;
+
+ /*
++ * WORKAROUND: for Sandisk eMMC cards, it might need certain delay
++ * before sending CMD13 after CMD6
++ */
++ mdelay(1);
++
++ /*
+ * Must check status to be sure of no errors
+ * If CMD13 is to check the busy completion of the timing change,
+ * disable the check of CRC error.
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/sd.c linux-3.14.72/drivers/mmc/core/sd.c
+--- linux-3.14.72.orig/drivers/mmc/core/sd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/sd.c 2016-06-19 22:11:55.197147093 +0200
+@@ -522,6 +522,13 @@
+ else {
+ mmc_set_timing(card->host, timing);
+ mmc_set_clock(card->host, card->sw_caps.uhs_max_dtr);
++
++ /*
++ * FIXME: Sandisk SD3.0 cards DDR50 mode requires such
++ * delay to get stable, without this delay we may encounter
++ * CRC errors after switch to DDR50 mode
++ */
++ mmc_delay(100);
+ }
+
+ return 0;
+@@ -555,7 +562,7 @@
+ static int sd_set_current_limit(struct mmc_card *card, u8 *status)
+ {
+ int current_limit = SD_SET_CURRENT_NO_CHANGE;
+- int err;
++ int i, err;
+ u32 max_current;
+
+ /*
+@@ -591,18 +598,23 @@
+ else if (max_current >= 200)
+ current_limit = SD_SET_CURRENT_LIMIT_200;
+
+- if (current_limit != SD_SET_CURRENT_NO_CHANGE) {
+- err = mmc_sd_switch(card, 1, 3, current_limit, status);
+- if (err)
+- return err;
++ if (current_limit == SD_SET_CURRENT_NO_CHANGE)
++ return 0;
+
+- if (((status[15] >> 4) & 0x0F) != current_limit)
+- pr_warning("%s: Problem setting current limit!\n",
+- mmc_hostname(card->host));
++ for (i = current_limit; i >= 0; i--) {
++ err = mmc_sd_switch(card, 1, 3, i, status);
++ if (err)
++ continue;
+
++ if (((status[15] >> 4) & 0x0F) != i) {
++ pr_warning("%s: Problem setting current limit to %d!\n",
++ mmc_hostname(card->host), i);
++ } else {
++ break;
++ }
+ }
+
+- return 0;
++ return err;
+ }
+
+ /*
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/sdio.c linux-3.14.72/drivers/mmc/core/sdio.c
+--- linux-3.14.72.orig/drivers/mmc/core/sdio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/sdio.c 2016-06-19 22:11:55.197147093 +0200
+@@ -1015,8 +1015,16 @@
+ }
+ }
+
+- if (!err && host->sdio_irqs)
+- wake_up_process(host->sdio_irq_thread);
++ if (!err && host->sdio_irqs) {
++ if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) {
++ wake_up_process(host->sdio_irq_thread);
++ } else if (host->caps & MMC_CAP_SDIO_IRQ) {
++ mmc_host_clk_hold(host);
++ host->ops->enable_sdio_irq(host, 1);
++ mmc_host_clk_release(host);
++ }
++ }
++
+ mmc_release_host(host);
+
+ /*
+diff -Nur linux-3.14.72.orig/drivers/mmc/core/sdio_irq.c linux-3.14.72/drivers/mmc/core/sdio_irq.c
+--- linux-3.14.72.orig/drivers/mmc/core/sdio_irq.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/core/sdio_irq.c 2016-06-19 22:11:55.197147093 +0200
+@@ -90,6 +90,15 @@
+ return ret;
+ }
+
++void sdio_run_irqs(struct mmc_host *host)
++{
++ mmc_claim_host(host);
++ host->sdio_irq_pending = true;
++ process_sdio_pending_irqs(host);
++ mmc_release_host(host);
++}
++EXPORT_SYMBOL_GPL(sdio_run_irqs);
++
+ static int sdio_irq_thread(void *_host)
+ {
+ struct mmc_host *host = _host;
+@@ -189,14 +198,20 @@
+ WARN_ON(!host->claimed);
+
+ if (!host->sdio_irqs++) {
+- atomic_set(&host->sdio_irq_thread_abort, 0);
+- host->sdio_irq_thread =
+- kthread_run(sdio_irq_thread, host, "ksdioirqd/%s",
+- mmc_hostname(host));
+- if (IS_ERR(host->sdio_irq_thread)) {
+- int err = PTR_ERR(host->sdio_irq_thread);
+- host->sdio_irqs--;
+- return err;
++ if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) {
++ atomic_set(&host->sdio_irq_thread_abort, 0);
++ host->sdio_irq_thread =
++ kthread_run(sdio_irq_thread, host,
++ "ksdioirqd/%s", mmc_hostname(host));
++ if (IS_ERR(host->sdio_irq_thread)) {
++ int err = PTR_ERR(host->sdio_irq_thread);
++ host->sdio_irqs--;
++ return err;
++ }
++ } else if (host->caps & MMC_CAP_SDIO_IRQ) {
++ mmc_host_clk_hold(host);
++ host->ops->enable_sdio_irq(host, 1);
++ mmc_host_clk_release(host);
+ }
+ }
+
+@@ -211,8 +226,14 @@
+ BUG_ON(host->sdio_irqs < 1);
+
+ if (!--host->sdio_irqs) {
+- atomic_set(&host->sdio_irq_thread_abort, 1);
+- kthread_stop(host->sdio_irq_thread);
++ if (!(host->caps2 & MMC_CAP2_SDIO_IRQ_NOTHREAD)) {
++ atomic_set(&host->sdio_irq_thread_abort, 1);
++ kthread_stop(host->sdio_irq_thread);
++ } else if (host->caps & MMC_CAP_SDIO_IRQ) {
++ mmc_host_clk_hold(host);
++ host->ops->enable_sdio_irq(host, 0);
++ mmc_host_clk_release(host);
++ }
+ }
+
+ return 0;
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/dw_mmc.c linux-3.14.72/drivers/mmc/host/dw_mmc.c
+--- linux-3.14.72.orig/drivers/mmc/host/dw_mmc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/dw_mmc.c 2016-06-19 22:11:55.197147093 +0200
+@@ -2147,6 +2147,8 @@
+ if (!mmc)
+ return -ENOMEM;
+
++ mmc_of_parse(mmc);
++
+ slot = mmc_priv(mmc);
+ slot->id = id;
+ slot->mmc = mmc;
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/Kconfig linux-3.14.72/drivers/mmc/host/Kconfig
+--- linux-3.14.72.orig/drivers/mmc/host/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/Kconfig 2016-06-19 22:11:55.197147093 +0200
+@@ -25,8 +25,7 @@
+ If unsure, say N.
+
+ config MMC_SDHCI
+- tristate "Secure Digital Host Controller Interface support"
+- depends on HAS_DMA
++ tristate
+ help
+ This selects the generic Secure Digital Host Controller Interface.
+ It is used by manufacturers such as Texas Instruments(R), Ricoh(R)
+@@ -59,7 +58,8 @@
+
+ config MMC_SDHCI_PCI
+ tristate "SDHCI support on PCI bus"
+- depends on MMC_SDHCI && PCI
++ depends on PCI && HAS_DMA
++ select MMC_SDHCI
+ help
+ This selects the PCI Secure Digital Host Controller Interface.
+ Most controllers found today are PCI devices.
+@@ -83,7 +83,8 @@
+
+ config MMC_SDHCI_ACPI
+ tristate "SDHCI support for ACPI enumerated SDHCI controllers"
+- depends on MMC_SDHCI && ACPI
++ depends on ACPI && HAS_DMA
++ select MMC_SDHCI
+ help
+ This selects support for ACPI enumerated SDHCI controllers,
+ identified by ACPI Compatibility ID PNP0D40 or specific
+@@ -94,8 +95,8 @@
+ If unsure, say N.
+
+ config MMC_SDHCI_PLTFM
+- tristate "SDHCI platform and OF driver helper"
+- depends on MMC_SDHCI
++ tristate
++ select MMC_SDHCI
+ help
+ This selects the common helper functions support for Secure Digital
+ Host Controller Interface based platform and OF drivers.
+@@ -106,8 +107,8 @@
+
+ config MMC_SDHCI_OF_ARASAN
+ tristate "SDHCI OF support for the Arasan SDHCI controllers"
+- depends on MMC_SDHCI_PLTFM
+- depends on OF
++ depends on OF && HAS_DMA
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the Arasan Secure Digital Host Controller Interface
+ (SDHCI). This hardware is found e.g. in Xilinx' Zynq SoC.
+@@ -118,9 +119,9 @@
+
+ config MMC_SDHCI_OF_ESDHC
+ tristate "SDHCI OF support for the Freescale eSDHC controller"
+- depends on MMC_SDHCI_PLTFM
+- depends on PPC_OF
++ depends on PPC_OF && HAS_DMA
+ select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the Freescale eSDHC controller support.
+
+@@ -130,9 +131,9 @@
+
+ config MMC_SDHCI_OF_HLWD
+ tristate "SDHCI OF support for the Nintendo Wii SDHCI controllers"
+- depends on MMC_SDHCI_PLTFM
+- depends on PPC_OF
++ depends on PPC_OF && HAS_DMA
+ select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ found in the "Hollywood" chipset of the Nintendo Wii video game
+@@ -144,8 +145,8 @@
+
+ config MMC_SDHCI_CNS3XXX
+ tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
+- depends on ARCH_CNS3XXX
+- depends on MMC_SDHCI_PLTFM
++ depends on ARCH_CNS3XXX && HAS_DMA
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the SDHCI support for CNS3xxx System-on-Chip devices.
+
+@@ -155,9 +156,9 @@
+
+ config MMC_SDHCI_ESDHC_IMX
+ tristate "SDHCI support for the Freescale eSDHC/uSDHC i.MX controller"
+- depends on ARCH_MXC
+- depends on MMC_SDHCI_PLTFM
++ depends on ARCH_MXC && HAS_DMA
+ select MMC_SDHCI_IO_ACCESSORS
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the Freescale eSDHC/uSDHC controller support
+ found on i.MX25, i.MX35 i.MX5x and i.MX6x.
+@@ -168,9 +169,9 @@
+
+ config MMC_SDHCI_DOVE
+ tristate "SDHCI support on Marvell's Dove SoC"
+- depends on ARCH_DOVE
+- depends on MMC_SDHCI_PLTFM
++ depends on ARCH_DOVE && HAS_DMA
+ select MMC_SDHCI_IO_ACCESSORS
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the Secure Digital Host Controller Interface in
+ Marvell's Dove SoC.
+@@ -181,9 +182,9 @@
+
+ config MMC_SDHCI_TEGRA
+ tristate "SDHCI platform support for the Tegra SD/MMC Controller"
+- depends on ARCH_TEGRA
+- depends on MMC_SDHCI_PLTFM
++ depends on ARCH_TEGRA && HAS_DMA
+ select MMC_SDHCI_IO_ACCESSORS
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the Tegra SD/MMC controller. If you have a Tegra
+ platform with SD or MMC devices, say Y or M here.
+@@ -192,7 +193,8 @@
+
+ config MMC_SDHCI_S3C
+ tristate "SDHCI support on Samsung S3C SoC"
+- depends on MMC_SDHCI && PLAT_SAMSUNG
++ depends on PLAT_SAMSUNG && HAS_DMA
++ select MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ often referrered to as the HSMMC block in some of the Samsung S3C
+@@ -204,8 +206,8 @@
+
+ config MMC_SDHCI_SIRF
+ tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
+- depends on ARCH_SIRF
+- depends on MMC_SDHCI_PLTFM
++ depends on ARCH_SIRF && HAS_DMA
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the SDHCI support for SiRF System-on-Chip devices.
+
+@@ -215,8 +217,7 @@
+
+ config MMC_SDHCI_PXAV3
+ tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
+- depends on CLKDEV_LOOKUP
+- select MMC_SDHCI
++ depends on CLKDEV_LOOKUP && HAS_DMA
+ select MMC_SDHCI_PLTFM
+ default CPU_MMP2
+ help
+@@ -228,8 +229,7 @@
+
+ config MMC_SDHCI_PXAV2
+ tristate "Marvell PXA9XX SD Host Controller support (PXAV2)"
+- depends on CLKDEV_LOOKUP
+- select MMC_SDHCI
++ depends on CLKDEV_LOOKUP && HAS_DMA
+ select MMC_SDHCI_PLTFM
+ default CPU_PXA910
+ help
+@@ -241,7 +241,8 @@
+
+ config MMC_SDHCI_SPEAR
+ tristate "SDHCI support on ST SPEAr platform"
+- depends on MMC_SDHCI && PLAT_SPEAR
++ depends on PLAT_SPEAR && HAS_DMA
++ select MMC_SDHCI
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ often referrered to as the HSMMC block in some of the ST SPEAR range
+@@ -263,7 +264,7 @@
+
+ config MMC_SDHCI_BCM_KONA
+ tristate "SDHCI support on Broadcom KONA platform"
+- depends on ARCH_BCM
++ depends on ARCH_BCM && HAS_DMA
+ select MMC_SDHCI_PLTFM
+ help
+ This selects the Broadcom Kona Secure Digital Host Controller
+@@ -274,9 +275,9 @@
+
+ config MMC_SDHCI_BCM2835
+ tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
+- depends on ARCH_BCM2835
+- depends on MMC_SDHCI_PLTFM
++ depends on ARCH_BCM2835 && HAS_DMA
+ select MMC_SDHCI_IO_ACCESSORS
++ select MMC_SDHCI_PLTFM
+ help
+ This selects the BCM2835 SD/MMC controller. If you have a BCM2835
+ platform with SD or MMC devices, say Y or M here.
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-acpi.c linux-3.14.72/drivers/mmc/host/sdhci-acpi.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-acpi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-acpi.c 2016-06-19 22:11:55.197147093 +0200
+@@ -101,11 +101,19 @@
+ }
+
+ static const struct sdhci_ops sdhci_acpi_ops_dflt = {
++ .set_clock = sdhci_set_clock,
+ .enable_dma = sdhci_acpi_enable_dma,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_ops sdhci_acpi_ops_int = {
++ .set_clock = sdhci_set_clock,
+ .enable_dma = sdhci_acpi_enable_dma,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .hw_reset = sdhci_acpi_int_hw_reset,
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-bcm2835.c linux-3.14.72/drivers/mmc/host/sdhci-bcm2835.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-bcm2835.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-bcm2835.c 2016-06-19 22:11:55.197147093 +0200
+@@ -131,8 +131,12 @@
+ .read_l = bcm2835_sdhci_readl,
+ .read_w = bcm2835_sdhci_readw,
+ .read_b = bcm2835_sdhci_readb,
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .get_min_clock = bcm2835_sdhci_get_min_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-bcm-kona.c linux-3.14.72/drivers/mmc/host/sdhci-bcm-kona.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-bcm-kona.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-bcm-kona.c 2016-06-19 22:11:55.197147093 +0200
+@@ -205,9 +205,13 @@
+ }
+
+ static struct sdhci_ops sdhci_bcm_kona_ops = {
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_bcm_kona_get_max_clk,
+ .get_timeout_clock = sdhci_bcm_kona_get_timeout_clock,
+ .platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .card_event = sdhci_bcm_kona_card_event,
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci.c linux-3.14.72/drivers/mmc/host/sdhci.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci.c 2016-06-19 22:11:55.201146831 +0200
+@@ -28,6 +28,7 @@
+ #include <linux/mmc/mmc.h>
+ #include <linux/mmc/host.h>
+ #include <linux/mmc/card.h>
++#include <linux/mmc/sdio.h>
+ #include <linux/mmc/slot-gpio.h>
+
+ #include "sdhci.h"
+@@ -44,6 +45,8 @@
+
+ #define MAX_TUNING_LOOP 40
+
++#define ADMA_SIZE ((128 * 2 + 1) * 4)
++
+ static unsigned int debug_quirks = 0;
+ static unsigned int debug_quirks2;
+
+@@ -53,6 +56,9 @@
+ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
+ static void sdhci_tuning_timer(unsigned long data);
+ static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
++static int sdhci_pre_dma_transfer(struct sdhci_host *host,
++ struct mmc_data *data,
++ struct sdhci_host_next *next);
+
+ #ifdef CONFIG_PM_RUNTIME
+ static int sdhci_runtime_pm_get(struct sdhci_host *host);
+@@ -131,43 +137,27 @@
+ * *
+ \*****************************************************************************/
+
+-static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
+-{
+- u32 ier;
+-
+- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+- ier &= ~clear;
+- ier |= set;
+- sdhci_writel(host, ier, SDHCI_INT_ENABLE);
+- sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+-}
+-
+-static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
+-{
+- sdhci_clear_set_irqs(host, 0, irqs);
+-}
+-
+-static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
+-{
+- sdhci_clear_set_irqs(host, irqs, 0);
+-}
+-
+ static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
+ {
+- u32 present, irqs;
++ u32 present;
++ int gpio_cd = mmc_gpio_get_cd(host->mmc);
+
+ if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
+- (host->mmc->caps & MMC_CAP_NONREMOVABLE))
++ (host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
++ !IS_ERR_VALUE(gpio_cd))
+ return;
+
+- present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
+- SDHCI_CARD_PRESENT;
+- irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
++ if (enable) {
++ present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
++ SDHCI_CARD_PRESENT;
++ host->ier |= present ? SDHCI_INT_CARD_REMOVE :
++ SDHCI_INT_CARD_INSERT;
++ } else {
++ host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
++ }
+
+- if (enable)
+- sdhci_unmask_irqs(host, irqs);
+- else
+- sdhci_mask_irqs(host, irqs);
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
+
+ static void sdhci_enable_card_detection(struct sdhci_host *host)
+@@ -180,22 +170,9 @@
+ sdhci_set_card_detection(host, false);
+ }
+
+-static void sdhci_reset(struct sdhci_host *host, u8 mask)
++void sdhci_reset(struct sdhci_host *host, u8 mask)
+ {
+ unsigned long timeout;
+- u32 uninitialized_var(ier);
+-
+- if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
+- if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
+- SDHCI_CARD_PRESENT))
+- return;
+- }
+-
+- if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+-
+- if (host->ops->platform_reset_enter)
+- host->ops->platform_reset_enter(host, mask);
+
+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+
+@@ -220,16 +197,27 @@
+ timeout--;
+ mdelay(1);
+ }
++}
++EXPORT_SYMBOL_GPL(sdhci_reset);
+
+- if (host->ops->platform_reset_exit)
+- host->ops->platform_reset_exit(host, mask);
++static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
++{
++ if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
++ if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
++ SDHCI_CARD_PRESENT))
++ return;
++ }
+
+- if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
+- sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
++ host->ops->reset(host, mask);
+
+- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
+- if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
+- host->ops->enable_dma(host);
++ if (mask & SDHCI_RESET_ALL) {
++ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
++ if (host->ops->enable_dma)
++ host->ops->enable_dma(host);
++ }
++
++ /* Resetting the controller clears many */
++ host->preset_enabled = false;
+ }
+ }
+
+@@ -238,15 +226,18 @@
+ static void sdhci_init(struct sdhci_host *host, int soft)
+ {
+ if (soft)
+- sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
+ else
+- sdhci_reset(host, SDHCI_RESET_ALL);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
++
++ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
++ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
++ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
++ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
++ SDHCI_INT_RESPONSE;
+
+- sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
+- SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
+- SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
+- SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
+- SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+ if (soft) {
+ /* force clock reconfiguration */
+@@ -502,20 +493,14 @@
+ else
+ direction = DMA_TO_DEVICE;
+
+- /*
+- * The ADMA descriptor table is mapped further down as we
+- * need to fill it with data first.
+- */
+-
+ host->align_addr = dma_map_single(mmc_dev(host->mmc),
+ host->align_buffer, 128 * 4, direction);
+ if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
+ goto fail;
+ BUG_ON(host->align_addr & 0x3);
+
+- host->sg_count = dma_map_sg(mmc_dev(host->mmc),
+- data->sg, data->sg_len, direction);
+- if (host->sg_count == 0)
++ host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
++ if (host->sg_count < 0)
+ goto unmap_align;
+
+ desc = host->adma_desc;
+@@ -567,7 +552,7 @@
+ * If this triggers then we have a calculation bug
+ * somewhere. :/
+ */
+- WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
++ WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
+ }
+
+ if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
+@@ -595,17 +580,8 @@
+ host->align_addr, 128 * 4, direction);
+ }
+
+- host->adma_addr = dma_map_single(mmc_dev(host->mmc),
+- host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
+- if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
+- goto unmap_entries;
+- BUG_ON(host->adma_addr & 0x3);
+-
+ return 0;
+
+-unmap_entries:
+- dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+- data->sg_len, direction);
+ unmap_align:
+ dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
+ 128 * 4, direction);
+@@ -623,19 +599,25 @@
+ u8 *align;
+ char *buffer;
+ unsigned long flags;
++ bool has_unaligned;
+
+ if (data->flags & MMC_DATA_READ)
+ direction = DMA_FROM_DEVICE;
+ else
+ direction = DMA_TO_DEVICE;
+
+- dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
+- (128 * 2 + 1) * 4, DMA_TO_DEVICE);
+-
+ dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
+ 128 * 4, direction);
+
+- if (data->flags & MMC_DATA_READ) {
++ /* Do a quick scan of the SG list for any unaligned mappings */
++ has_unaligned = false;
++ for_each_sg(data->sg, sg, host->sg_count, i)
++ if (sg_dma_address(sg) & 3) {
++ has_unaligned = true;
++ break;
++ }
++
++ if (has_unaligned && data->flags & MMC_DATA_READ) {
+ dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
+ data->sg_len, direction);
+
+@@ -655,8 +637,9 @@
+ }
+ }
+
+- dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+- data->sg_len, direction);
++ if (!data->host_cookie)
++ dma_unmap_sg(mmc_dev(host->mmc), data->sg,
++ data->sg_len, direction);
+ }
+
+ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
+@@ -721,9 +704,12 @@
+ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
+
+ if (host->flags & SDHCI_REQ_USE_DMA)
+- sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
++ host->ier = (host->ier & ~pio_irqs) | dma_irqs;
+ else
+- sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
++ host->ier = (host->ier & ~dma_irqs) | pio_irqs;
++
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
+
+ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
+@@ -836,12 +822,8 @@
+ } else {
+ int sg_cnt;
+
+- sg_cnt = dma_map_sg(mmc_dev(host->mmc),
+- data->sg, data->sg_len,
+- (data->flags & MMC_DATA_READ) ?
+- DMA_FROM_DEVICE :
+- DMA_TO_DEVICE);
+- if (sg_cnt == 0) {
++ sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
++ if (sg_cnt <= 0) {
+ /*
+ * This only happens when someone fed
+ * us an invalid request.
+@@ -915,7 +897,8 @@
+ * If we are sending CMD23, CMD12 never gets sent
+ * on successful completion (so no Auto-CMD12).
+ */
+- if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
++ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
++ (cmd->opcode != SD_IO_RW_EXTENDED))
+ mode |= SDHCI_TRNS_AUTO_CMD12;
+ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
+ mode |= SDHCI_TRNS_AUTO_CMD23;
+@@ -944,8 +927,10 @@
+ if (host->flags & SDHCI_USE_ADMA)
+ sdhci_adma_table_post(host, data);
+ else {
+- dma_unmap_sg(mmc_dev(host->mmc), data->sg,
+- data->sg_len, (data->flags & MMC_DATA_READ) ?
++ if (!data->host_cookie)
++ dma_unmap_sg(mmc_dev(host->mmc),
++ data->sg, data->sg_len,
++ (data->flags & MMC_DATA_READ) ?
+ DMA_FROM_DEVICE : DMA_TO_DEVICE);
+ }
+ }
+@@ -976,8 +961,8 @@
+ * upon error conditions.
+ */
+ if (data->error) {
+- sdhci_reset(host, SDHCI_RESET_CMD);
+- sdhci_reset(host, SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD);
++ sdhci_do_reset(host, SDHCI_RESET_DATA);
+ }
+
+ sdhci_send_command(host, data->stop);
+@@ -1107,24 +1092,24 @@
+
+ static u16 sdhci_get_preset_value(struct sdhci_host *host)
+ {
+- u16 ctrl, preset = 0;
+-
+- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
++ u16 preset = 0;
+
+- switch (ctrl & SDHCI_CTRL_UHS_MASK) {
+- case SDHCI_CTRL_UHS_SDR12:
++ switch (host->timing) {
++ case MMC_TIMING_UHS_SDR12:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
+ break;
+- case SDHCI_CTRL_UHS_SDR25:
++ case MMC_TIMING_UHS_SDR25:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
+ break;
+- case SDHCI_CTRL_UHS_SDR50:
++ case MMC_TIMING_UHS_SDR50:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
+ break;
+- case SDHCI_CTRL_UHS_SDR104:
++ case MMC_TIMING_UHS_SDR104:
++ case MMC_TIMING_MMC_HS200:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
+ break;
+- case SDHCI_CTRL_UHS_DDR50:
++ case MMC_TIMING_UHS_DDR50:
++ case MMC_TIMING_MMC_DDR52:
+ preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
+ break;
+ default:
+@@ -1136,32 +1121,22 @@
+ return preset;
+ }
+
+-static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
++void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+ {
+ int div = 0; /* Initialized for compiler warning */
+ int real_div = div, clk_mul = 1;
+ u16 clk = 0;
+ unsigned long timeout;
+
+- if (clock && clock == host->clock)
+- return;
+-
+ host->mmc->actual_clock = 0;
+
+- if (host->ops->set_clock) {
+- host->ops->set_clock(host, clock);
+- if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
+- return;
+- }
+-
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+- goto out;
++ return;
+
+ if (host->version >= SDHCI_SPEC_300) {
+- if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
+- SDHCI_CTRL_PRESET_VAL_ENABLE) {
++ if (host->preset_enabled) {
+ u16 pre_val;
+
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+@@ -1247,26 +1222,16 @@
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+-
+-out:
+- host->clock = clock;
+ }
++EXPORT_SYMBOL_GPL(sdhci_set_clock);
+
+-static inline void sdhci_update_clock(struct sdhci_host *host)
+-{
+- unsigned int clock;
+-
+- clock = host->clock;
+- host->clock = 0;
+- sdhci_set_clock(host, clock);
+-}
+-
+-static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
++static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
++ unsigned short vdd)
+ {
+ u8 pwr = 0;
+
+- if (power != (unsigned short)-1) {
+- switch (1 << power) {
++ if (mode != MMC_POWER_OFF) {
++ switch (1 << vdd) {
+ case MMC_VDD_165_195:
+ pwr = SDHCI_POWER_180;
+ break;
+@@ -1284,7 +1249,7 @@
+ }
+
+ if (host->pwr == pwr)
+- return -1;
++ return;
+
+ host->pwr = pwr;
+
+@@ -1292,38 +1257,43 @@
+ sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
+ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
+ sdhci_runtime_pm_bus_off(host);
+- return 0;
+- }
+-
+- /*
+- * Spec says that we should clear the power reg before setting
+- * a new value. Some controllers don't seem to like this though.
+- */
+- if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
+- sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
++ vdd = 0;
++ } else {
++ /*
++ * Spec says that we should clear the power reg before setting
++ * a new value. Some controllers don't seem to like this though.
++ */
++ if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
++ sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
+
+- /*
+- * At least the Marvell CaFe chip gets confused if we set the voltage
+- * and set turn on power at the same time, so set the voltage first.
+- */
+- if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
+- sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
++ /*
++ * At least the Marvell CaFe chip gets confused if we set the
++ * voltage and set turn on power at the same time, so set the
++ * voltage first.
++ */
++ if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
++ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+- pwr |= SDHCI_POWER_ON;
++ pwr |= SDHCI_POWER_ON;
+
+- sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
++ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+- if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
+- sdhci_runtime_pm_bus_on(host);
++ if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
++ sdhci_runtime_pm_bus_on(host);
+
+- /*
+- * Some controllers need an extra 10ms delay of 10ms before they
+- * can apply clock after applying power
+- */
+- if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
+- mdelay(10);
++ /*
++ * Some controllers need an extra 10ms delay of 10ms before
++ * they can apply clock after applying power
++ */
++ if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
++ mdelay(10);
++ }
+
+- return power;
++ if (host->vmmc) {
++ spin_unlock_irq(&host->lock);
++ mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd);
++ spin_lock_irq(&host->lock);
++ }
+ }
+
+ /*****************************************************************************\
+@@ -1428,10 +1398,52 @@
+ spin_unlock_irqrestore(&host->lock, flags);
+ }
+
++void sdhci_set_bus_width(struct sdhci_host *host, int width)
++{
++ u8 ctrl;
++
++ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
++ if (width == MMC_BUS_WIDTH_8) {
++ ctrl &= ~SDHCI_CTRL_4BITBUS;
++ if (host->version >= SDHCI_SPEC_300)
++ ctrl |= SDHCI_CTRL_8BITBUS;
++ } else {
++ if (host->version >= SDHCI_SPEC_300)
++ ctrl &= ~SDHCI_CTRL_8BITBUS;
++ if (width == MMC_BUS_WIDTH_4)
++ ctrl |= SDHCI_CTRL_4BITBUS;
++ else
++ ctrl &= ~SDHCI_CTRL_4BITBUS;
++ }
++ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
++}
++EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
++
++void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
++{
++ u16 ctrl_2;
++
++ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
++ /* Select Bus Speed Mode for host */
++ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
++ if ((timing == MMC_TIMING_MMC_HS200) ||
++ (timing == MMC_TIMING_UHS_SDR104))
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
++ else if (timing == MMC_TIMING_UHS_SDR12)
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
++ else if (timing == MMC_TIMING_UHS_SDR25)
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
++ else if (timing == MMC_TIMING_UHS_SDR50)
++ ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
++ else if (timing == MMC_TIMING_UHS_DDR50)
++ ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
++ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
++}
++EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
++
+ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
+ {
+ unsigned long flags;
+- int vdd_bit = -1;
+ u8 ctrl;
+
+ spin_lock_irqsave(&host->lock, flags);
+@@ -1457,45 +1469,17 @@
+ !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
+ sdhci_enable_preset_value(host, false);
+
+- sdhci_set_clock(host, ios->clock);
+-
+- if (ios->power_mode == MMC_POWER_OFF)
+- vdd_bit = sdhci_set_power(host, -1);
+- else
+- vdd_bit = sdhci_set_power(host, ios->vdd);
+-
+- if (host->vmmc && vdd_bit != -1) {
+- spin_unlock_irqrestore(&host->lock, flags);
+- mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
+- spin_lock_irqsave(&host->lock, flags);
++ if (!ios->clock || ios->clock != host->clock) {
++ host->ops->set_clock(host, ios->clock);
++ host->clock = ios->clock;
+ }
+
++ sdhci_set_power(host, ios->power_mode, ios->vdd);
++
+ if (host->ops->platform_send_init_74_clocks)
+ host->ops->platform_send_init_74_clocks(host, ios->power_mode);
+
+- /*
+- * If your platform has 8-bit width support but is not a v3 controller,
+- * or if it requires special setup code, you should implement that in
+- * platform_bus_width().
+- */
+- if (host->ops->platform_bus_width) {
+- host->ops->platform_bus_width(host, ios->bus_width);
+- } else {
+- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+- if (ios->bus_width == MMC_BUS_WIDTH_8) {
+- ctrl &= ~SDHCI_CTRL_4BITBUS;
+- if (host->version >= SDHCI_SPEC_300)
+- ctrl |= SDHCI_CTRL_8BITBUS;
+- } else {
+- if (host->version >= SDHCI_SPEC_300)
+- ctrl &= ~SDHCI_CTRL_8BITBUS;
+- if (ios->bus_width == MMC_BUS_WIDTH_4)
+- ctrl |= SDHCI_CTRL_4BITBUS;
+- else
+- ctrl &= ~SDHCI_CTRL_4BITBUS;
+- }
+- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+- }
++ host->ops->set_bus_width(host, ios->bus_width);
+
+ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
+
+@@ -1517,13 +1501,13 @@
+ (ios->timing == MMC_TIMING_UHS_SDR25))
+ ctrl |= SDHCI_CTRL_HISPD;
+
+- ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+- if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
++ if (!host->preset_enabled) {
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ /*
+ * We only need to set Driver Strength if the
+ * preset value enable is not set.
+ */
++ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
+ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
+@@ -1547,41 +1531,24 @@
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ /* Re-enable SD Clock */
+- sdhci_update_clock(host);
++ host->ops->set_clock(host, host->clock);
+ }
+
+-
+ /* Reset SD Clock Enable */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+- if (host->ops->set_uhs_signaling)
+- host->ops->set_uhs_signaling(host, ios->timing);
+- else {
+- ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+- /* Select Bus Speed Mode for host */
+- ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+- if ((ios->timing == MMC_TIMING_MMC_HS200) ||
+- (ios->timing == MMC_TIMING_UHS_SDR104))
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+- else if (ios->timing == MMC_TIMING_UHS_SDR12)
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+- else if (ios->timing == MMC_TIMING_UHS_SDR25)
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+- else if (ios->timing == MMC_TIMING_UHS_SDR50)
+- ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+- else if (ios->timing == MMC_TIMING_UHS_DDR50)
+- ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+- sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+- }
++ host->ops->set_uhs_signaling(host, ios->timing);
++ host->timing = ios->timing;
+
+ if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
+ ((ios->timing == MMC_TIMING_UHS_SDR12) ||
+ (ios->timing == MMC_TIMING_UHS_SDR25) ||
+ (ios->timing == MMC_TIMING_UHS_SDR50) ||
+ (ios->timing == MMC_TIMING_UHS_SDR104) ||
+- (ios->timing == MMC_TIMING_UHS_DDR50))) {
++ (ios->timing == MMC_TIMING_UHS_DDR50) ||
++ (ios->timing == MMC_TIMING_MMC_DDR52))) {
+ u16 preset;
+
+ sdhci_enable_preset_value(host, true);
+@@ -1591,7 +1558,7 @@
+ }
+
+ /* Re-enable SD Clock */
+- sdhci_update_clock(host);
++ host->ops->set_clock(host, host->clock);
+ } else
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+@@ -1601,7 +1568,7 @@
+ * it on each ios seems to solve the problem.
+ */
+ if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
+- sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+ mmiowb();
+ spin_unlock_irqrestore(&host->lock, flags);
+@@ -1710,24 +1677,16 @@
+
+ static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
+ {
+- if (host->flags & SDHCI_DEVICE_DEAD)
+- goto out;
+-
+- if (enable)
+- host->flags |= SDHCI_SDIO_IRQ_ENABLED;
+- else
+- host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
+-
+- /* SDIO IRQ will be enabled as appropriate in runtime resume */
+- if (host->runtime_suspended)
+- goto out;
++ if (!(host->flags & SDHCI_DEVICE_DEAD)) {
++ if (enable)
++ host->ier |= SDHCI_INT_CARD_INT;
++ else
++ host->ier &= ~SDHCI_INT_CARD_INT;
+
+- if (enable)
+- sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
+- else
+- sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
+-out:
+- mmiowb();
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
++ mmiowb();
++ }
+ }
+
+ static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
+@@ -1735,9 +1694,18 @@
+ struct sdhci_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
++ sdhci_runtime_pm_get(host);
++
+ spin_lock_irqsave(&host->lock, flags);
++ if (enable)
++ host->flags |= SDHCI_SDIO_IRQ_ENABLED;
++ else
++ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
++
+ sdhci_enable_sdio_irq_nolock(host, enable);
+ spin_unlock_irqrestore(&host->lock, flags);
++
++ sdhci_runtime_pm_put(host);
+ }
+
+ static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
+@@ -1856,22 +1824,16 @@
+
+ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
+ {
+- struct sdhci_host *host;
++ struct sdhci_host *host = mmc_priv(mmc);
+ u16 ctrl;
+- u32 ier;
+ int tuning_loop_counter = MAX_TUNING_LOOP;
+ unsigned long timeout;
+ int err = 0;
+- bool requires_tuning_nonuhs = false;
+ unsigned long flags;
+
+- host = mmc_priv(mmc);
+-
+ sdhci_runtime_pm_get(host);
+ spin_lock_irqsave(&host->lock, flags);
+
+- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+-
+ /*
+ * The Host Controller needs tuning only in case of SDR104 mode
+ * and for SDR50 mode when Use Tuning for SDR50 is set in the
+@@ -1879,15 +1841,18 @@
+ * If the Host Controller supports the HS200 mode then the
+ * tuning function has to be executed.
+ */
+- if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
+- (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
+- host->flags & SDHCI_SDR104_NEEDS_TUNING))
+- requires_tuning_nonuhs = true;
+-
+- if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
+- requires_tuning_nonuhs)
+- ctrl |= SDHCI_CTRL_EXEC_TUNING;
+- else {
++ switch (host->timing) {
++ case MMC_TIMING_MMC_HS200:
++ case MMC_TIMING_UHS_SDR104:
++ break;
++
++ case MMC_TIMING_UHS_SDR50:
++ if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
++ host->flags & SDHCI_SDR104_NEEDS_TUNING)
++ break;
++ /* FALLTHROUGH */
++
++ default:
+ spin_unlock_irqrestore(&host->lock, flags);
+ sdhci_runtime_pm_put(host);
+ return 0;
+@@ -1900,6 +1865,8 @@
+ return err;
+ }
+
++ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
++ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /*
+@@ -1912,8 +1879,8 @@
+ * to make sure we don't hit a controller bug, we _only_
+ * enable Buffer Read Ready interrupt here.
+ */
+- ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+- sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
++ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
++ sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
+
+ /*
+ * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
+@@ -2046,7 +2013,8 @@
+ if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
+ err = 0;
+
+- sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ spin_unlock_irqrestore(&host->lock, flags);
+ sdhci_runtime_pm_put(host);
+
+@@ -2056,29 +2024,104 @@
+
+ static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
+ {
+- u16 ctrl;
+-
+ /* Host Controller v3.00 defines preset value registers */
+ if (host->version < SDHCI_SPEC_300)
+ return;
+
+- ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+-
+ /*
+ * We only enable or disable Preset Value if they are not already
+ * enabled or disabled respectively. Otherwise, we bail out.
+ */
+- if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+- ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
+- sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+- host->flags |= SDHCI_PV_ENABLED;
+- } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+- ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
++ if (host->preset_enabled != enable) {
++ u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
++
++ if (enable)
++ ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
++ else
++ ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
++
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+- host->flags &= ~SDHCI_PV_ENABLED;
++
++ if (enable)
++ host->flags |= SDHCI_PV_ENABLED;
++ else
++ host->flags &= ~SDHCI_PV_ENABLED;
++
++ host->preset_enabled = enable;
+ }
+ }
+
++static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
++ int err)
++{
++ struct sdhci_host *host = mmc_priv(mmc);
++ struct mmc_data *data = mrq->data;
++
++ if (host->flags & SDHCI_REQ_USE_DMA) {
++ if (data->host_cookie)
++ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
++ data->flags & MMC_DATA_WRITE ?
++ DMA_TO_DEVICE : DMA_FROM_DEVICE);
++ mrq->data->host_cookie = 0;
++ }
++}
++
++static int sdhci_pre_dma_transfer(struct sdhci_host *host,
++ struct mmc_data *data,
++ struct sdhci_host_next *next)
++{
++ int sg_count;
++
++ if (!next && data->host_cookie &&
++ data->host_cookie != host->next_data.cookie) {
++ pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
++ __func__, data->host_cookie, host->next_data.cookie);
++ data->host_cookie = 0;
++ }
++
++ /* Check if next job is already prepared */
++ if (next ||
++ (!next && data->host_cookie != host->next_data.cookie)) {
++ sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
++ data->sg_len,
++ data->flags & MMC_DATA_WRITE ?
++ DMA_TO_DEVICE : DMA_FROM_DEVICE);
++
++ } else {
++ sg_count = host->next_data.sg_count;
++ host->next_data.sg_count = 0;
++ }
++
++
++ if (sg_count == 0)
++ return -EINVAL;
++
++ if (next) {
++ next->sg_count = sg_count;
++ data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
++ } else
++ host->sg_count = sg_count;
++
++ return sg_count;
++}
++
++static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
++ bool is_first_req)
++{
++ struct sdhci_host *host = mmc_priv(mmc);
++
++ if (mrq->data->host_cookie) {
++ mrq->data->host_cookie = 0;
++ return;
++ }
++
++ if (host->flags & SDHCI_REQ_USE_DMA)
++ if (sdhci_pre_dma_transfer(host,
++ mrq->data,
++ &host->next_data) < 0)
++ mrq->data->host_cookie = 0;
++}
++
+ static void sdhci_card_event(struct mmc_host *mmc)
+ {
+ struct sdhci_host *host = mmc_priv(mmc);
+@@ -2100,8 +2143,8 @@
+ pr_err("%s: Resetting controller.\n",
+ mmc_hostname(host->mmc));
+
+- sdhci_reset(host, SDHCI_RESET_CMD);
+- sdhci_reset(host, SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD);
++ sdhci_do_reset(host, SDHCI_RESET_DATA);
+
+ host->mrq->cmd->error = -ENOMEDIUM;
+ tasklet_schedule(&host->finish_tasklet);
+@@ -2112,6 +2155,8 @@
+
+ static const struct mmc_host_ops sdhci_ops = {
+ .request = sdhci_request,
++ .post_req = sdhci_post_req,
++ .pre_req = sdhci_pre_req,
+ .set_ios = sdhci_set_ios,
+ .get_cd = sdhci_get_cd,
+ .get_ro = sdhci_get_ro,
+@@ -2129,15 +2174,6 @@
+ * *
+ \*****************************************************************************/
+
+-static void sdhci_tasklet_card(unsigned long param)
+-{
+- struct sdhci_host *host = (struct sdhci_host*)param;
+-
+- sdhci_card_event(host->mmc);
+-
+- mmc_detect_change(host->mmc, msecs_to_jiffies(200));
+-}
+-
+ static void sdhci_tasklet_finish(unsigned long param)
+ {
+ struct sdhci_host *host;
+@@ -2174,12 +2210,12 @@
+ /* Some controllers need this kick or reset won't work here */
+ if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
+ /* This is to force an update */
+- sdhci_update_clock(host);
++ host->ops->set_clock(host, host->clock);
+
+ /* Spec says we should do both at the same time, but Ricoh
+ controllers do not like that. */
+- sdhci_reset(host, SDHCI_RESET_CMD);
+- sdhci_reset(host, SDHCI_RESET_DATA);
++ sdhci_do_reset(host, SDHCI_RESET_CMD);
++ sdhci_do_reset(host, SDHCI_RESET_DATA);
+ }
+
+ host->mrq = NULL;
+@@ -2429,14 +2465,14 @@
+
+ static irqreturn_t sdhci_irq(int irq, void *dev_id)
+ {
+- irqreturn_t result;
++ irqreturn_t result = IRQ_NONE;
+ struct sdhci_host *host = dev_id;
+- u32 intmask, unexpected = 0;
+- int cardint = 0, max_loops = 16;
++ u32 intmask, mask, unexpected = 0;
++ int max_loops = 16;
+
+ spin_lock(&host->lock);
+
+- if (host->runtime_suspended) {
++ if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
+ spin_unlock(&host->lock);
+ pr_warning("%s: got irq while runtime suspended\n",
+ mmc_hostname(host->mmc));
+@@ -2444,88 +2480,81 @@
+ }
+
+ intmask = sdhci_readl(host, SDHCI_INT_STATUS);
+-
+ if (!intmask || intmask == 0xffffffff) {
+ result = IRQ_NONE;
+ goto out;
+ }
+
+-again:
+- DBG("*** %s got interrupt: 0x%08x\n",
+- mmc_hostname(host->mmc), intmask);
+-
+- if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
+- u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
+- SDHCI_CARD_PRESENT;
+-
+- /*
+- * There is a observation on i.mx esdhc. INSERT bit will be
+- * immediately set again when it gets cleared, if a card is
+- * inserted. We have to mask the irq to prevent interrupt
+- * storm which will freeze the system. And the REMOVE gets
+- * the same situation.
+- *
+- * More testing are needed here to ensure it works for other
+- * platforms though.
+- */
+- sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
+- SDHCI_INT_CARD_REMOVE);
+- sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
+- SDHCI_INT_CARD_INSERT);
+-
+- sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
+- SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
+- intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
+- tasklet_schedule(&host->card_tasklet);
+- }
+-
+- if (intmask & SDHCI_INT_CMD_MASK) {
+- sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
+- SDHCI_INT_STATUS);
+- sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
+- }
++ do {
++ /* Clear selected interrupts. */
++ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
++ SDHCI_INT_BUS_POWER);
++ sdhci_writel(host, mask, SDHCI_INT_STATUS);
++
++ DBG("*** %s got interrupt: 0x%08x\n",
++ mmc_hostname(host->mmc), intmask);
++
++ if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
++ u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
++ SDHCI_CARD_PRESENT;
+
+- if (intmask & SDHCI_INT_DATA_MASK) {
+- sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
+- SDHCI_INT_STATUS);
+- sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
+- }
++ /*
++ * There is a observation on i.mx esdhc. INSERT
++ * bit will be immediately set again when it gets
++ * cleared, if a card is inserted. We have to mask
++ * the irq to prevent interrupt storm which will
++ * freeze the system. And the REMOVE gets the
++ * same situation.
++ *
++ * More testing are needed here to ensure it works
++ * for other platforms though.
++ */
++ host->ier &= ~(SDHCI_INT_CARD_INSERT |
++ SDHCI_INT_CARD_REMOVE);
++ host->ier |= present ? SDHCI_INT_CARD_REMOVE :
++ SDHCI_INT_CARD_INSERT;
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+
+- intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
++ sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
++ SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
+
+- intmask &= ~SDHCI_INT_ERROR;
++ host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
++ SDHCI_INT_CARD_REMOVE);
++ result = IRQ_WAKE_THREAD;
++ }
+
+- if (intmask & SDHCI_INT_BUS_POWER) {
+- pr_err("%s: Card is consuming too much power!\n",
+- mmc_hostname(host->mmc));
+- sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
+- }
++ if (intmask & SDHCI_INT_CMD_MASK)
++ sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
+
+- intmask &= ~SDHCI_INT_BUS_POWER;
++ if (intmask & SDHCI_INT_DATA_MASK)
++ sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
+
+- if (intmask & SDHCI_INT_CARD_INT)
+- cardint = 1;
++ if (intmask & SDHCI_INT_BUS_POWER)
++ pr_err("%s: Card is consuming too much power!\n",
++ mmc_hostname(host->mmc));
+
+- intmask &= ~SDHCI_INT_CARD_INT;
++ if (intmask & SDHCI_INT_CARD_INT) {
++ sdhci_enable_sdio_irq_nolock(host, false);
++ host->thread_isr |= SDHCI_INT_CARD_INT;
++ result = IRQ_WAKE_THREAD;
++ }
+
+- if (intmask) {
+- unexpected |= intmask;
+- sdhci_writel(host, intmask, SDHCI_INT_STATUS);
+- }
++ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
++ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
++ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
++ SDHCI_INT_CARD_INT);
+
+- result = IRQ_HANDLED;
++ if (intmask) {
++ unexpected |= intmask;
++ sdhci_writel(host, intmask, SDHCI_INT_STATUS);
++ }
+
+- intmask = sdhci_readl(host, SDHCI_INT_STATUS);
++ if (result == IRQ_NONE)
++ result = IRQ_HANDLED;
+
+- /*
+- * If we know we'll call the driver to signal SDIO IRQ, disregard
+- * further indications of Card Interrupt in the status to avoid a
+- * needless loop.
+- */
+- if (cardint)
+- intmask &= ~SDHCI_INT_CARD_INT;
+- if (intmask && --max_loops)
+- goto again;
++ intmask = sdhci_readl(host, SDHCI_INT_STATUS);
++ } while (intmask && --max_loops);
+ out:
+ spin_unlock(&host->lock);
+
+@@ -2534,15 +2563,38 @@
+ mmc_hostname(host->mmc), unexpected);
+ sdhci_dumpregs(host);
+ }
+- /*
+- * We have to delay this as it calls back into the driver.
+- */
+- if (cardint && host->mmc->sdio_irqs)
+- mmc_signal_sdio_irq(host->mmc);
+
+ return result;
+ }
+
++static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
++{
++ struct sdhci_host *host = dev_id;
++ unsigned long flags;
++ u32 isr;
++
++ spin_lock_irqsave(&host->lock, flags);
++ isr = host->thread_isr;
++ host->thread_isr = 0;
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
++ sdhci_card_event(host->mmc);
++ mmc_detect_change(host->mmc, msecs_to_jiffies(200));
++ }
++
++ if (isr & SDHCI_INT_CARD_INT) {
++ sdio_run_irqs(host->mmc);
++
++ spin_lock_irqsave(&host->lock, flags);
++ if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
++ sdhci_enable_sdio_irq_nolock(host, true);
++ spin_unlock_irqrestore(&host->lock, flags);
++ }
++
++ return isr ? IRQ_HANDLED : IRQ_NONE;
++}
++
+ /*****************************************************************************\
+ * *
+ * Suspend/resume *
+@@ -2552,6 +2604,7 @@
+ #ifdef CONFIG_PM
+ void sdhci_enable_irq_wakeups(struct sdhci_host *host)
+ {
++ int gpio_cd = mmc_gpio_get_cd(host->mmc);
+ u8 val;
+ u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
+ | SDHCI_WAKE_ON_INT;
+@@ -2559,7 +2612,8 @@
+ val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
+ val |= mask ;
+ /* Avoid fake wake up */
+- if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
++ if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION ||
++ !IS_ERR_VALUE(gpio_cd))
+ val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
+ sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
+ }
+@@ -2579,9 +2633,6 @@
+
+ int sdhci_suspend_host(struct sdhci_host *host)
+ {
+- if (host->ops->platform_suspend)
+- host->ops->platform_suspend(host);
+-
+ sdhci_disable_card_detection(host);
+
+ /* Disable tuning since we are suspending */
+@@ -2591,7 +2642,9 @@
+ }
+
+ if (!device_may_wakeup(mmc_dev(host->mmc))) {
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ host->ier = 0;
++ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
++ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+ } else {
+ sdhci_enable_irq_wakeups(host);
+@@ -2612,8 +2665,9 @@
+ }
+
+ if (!device_may_wakeup(mmc_dev(host->mmc))) {
+- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
+- mmc_hostname(host->mmc), host);
++ ret = request_threaded_irq(host->irq, sdhci_irq,
++ sdhci_thread_irq, IRQF_SHARED,
++ mmc_hostname(host->mmc), host);
+ if (ret)
+ return ret;
+ } else {
+@@ -2635,9 +2689,6 @@
+
+ sdhci_enable_card_detection(host);
+
+- if (host->ops->platform_resume)
+- host->ops->platform_resume(host);
+-
+ /* Set the re-tuning expiration flag */
+ if (host->flags & SDHCI_USING_RETUNING_TIMER)
+ host->flags |= SDHCI_NEEDS_RETUNING;
+@@ -2689,10 +2740,12 @@
+ }
+
+ spin_lock_irqsave(&host->lock, flags);
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ host->ier &= SDHCI_INT_CARD_INT;
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+- synchronize_irq(host->irq);
++ synchronize_hardirq(host->irq);
+
+ spin_lock_irqsave(&host->lock, flags);
+ host->runtime_suspended = true;
+@@ -2736,7 +2789,7 @@
+ host->runtime_suspended = false;
+
+ /* Enable SDIO IRQ */
+- if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
++ if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
+ sdhci_enable_sdio_irq_nolock(host, true);
+
+ /* Enable Card Detection */
+@@ -2795,7 +2848,7 @@
+ if (debug_quirks2)
+ host->quirks2 = debug_quirks2;
+
+- sdhci_reset(host, SDHCI_RESET_ALL);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
+
+ host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+ host->version = (host->version & SDHCI_SPEC_VER_MASK)
+@@ -2855,15 +2908,29 @@
+ * (128) and potentially one alignment transfer for
+ * each of those entries.
+ */
+- host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
++ host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
++ ADMA_SIZE, &host->adma_addr,
++ GFP_KERNEL);
+ host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
+ if (!host->adma_desc || !host->align_buffer) {
+- kfree(host->adma_desc);
++ dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
++ host->adma_desc, host->adma_addr);
+ kfree(host->align_buffer);
+ pr_warning("%s: Unable to allocate ADMA "
+ "buffers. Falling back to standard DMA.\n",
+ mmc_hostname(mmc));
+ host->flags &= ~SDHCI_USE_ADMA;
++ host->adma_desc = NULL;
++ host->align_buffer = NULL;
++ } else if (host->adma_addr & 3) {
++ pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
++ mmc_hostname(mmc));
++ host->flags &= ~SDHCI_USE_ADMA;
++ dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
++ host->adma_desc, host->adma_addr);
++ kfree(host->align_buffer);
++ host->adma_desc = NULL;
++ host->align_buffer = NULL;
+ }
+ }
+
+@@ -2895,6 +2962,7 @@
+ host->max_clk = host->ops->get_max_clock(host);
+ }
+
++ host->next_data.cookie = 1;
+ /*
+ * In case of Host Controller v3.00, find out whether clock
+ * multiplier is supported.
+@@ -2945,9 +3013,22 @@
+ if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
+ host->timeout_clk = mmc->f_max / 1000;
+
+- mmc->max_discard_to = (1 << 27) / host->timeout_clk;
++ if (host->quirks2 & SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER) {
++ if (host->ops->get_max_timeout_counter) {
++ mmc->max_discard_to =
++ host->ops->get_max_timeout_counter(host)
++ / host->timeout_clk;
++ } else {
++ pr_err("%s: Hardware doesn't specify max timeout "
++ "counter\n", mmc_hostname(mmc));
++ return -ENODEV;
++ }
++ } else {
++ mmc->max_discard_to = (1 << 27) / host->timeout_clk;
++ }
+
+ mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
++ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
+
+ if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+ host->flags |= SDHCI_AUTO_CMD12;
+@@ -3218,8 +3299,6 @@
+ /*
+ * Init tasklets.
+ */
+- tasklet_init(&host->card_tasklet,
+- sdhci_tasklet_card, (unsigned long)host);
+ tasklet_init(&host->finish_tasklet,
+ sdhci_tasklet_finish, (unsigned long)host);
+
+@@ -3236,8 +3315,8 @@
+
+ sdhci_init(host, 0);
+
+- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
+- mmc_hostname(mmc), host);
++ ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
++ IRQF_SHARED, mmc_hostname(mmc), host);
+ if (ret) {
+ pr_err("%s: Failed to request IRQ %d: %d\n",
+ mmc_hostname(mmc), host->irq, ret);
+@@ -3279,12 +3358,12 @@
+
+ #ifdef SDHCI_USE_LEDS_CLASS
+ reset:
+- sdhci_reset(host, SDHCI_RESET_ALL);
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
++ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
++ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+ #endif
+ untasklet:
+- tasklet_kill(&host->card_tasklet);
+ tasklet_kill(&host->finish_tasklet);
+
+ return ret;
+@@ -3321,27 +3400,31 @@
+ #endif
+
+ if (!dead)
+- sdhci_reset(host, SDHCI_RESET_ALL);
++ sdhci_do_reset(host, SDHCI_RESET_ALL);
+
+- sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
++ sdhci_writel(host, 0, SDHCI_INT_ENABLE);
++ sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
+ free_irq(host->irq, host);
+
+ del_timer_sync(&host->timer);
+
+- tasklet_kill(&host->card_tasklet);
+ tasklet_kill(&host->finish_tasklet);
+
+ if (host->vmmc) {
+- regulator_disable(host->vmmc);
++ if (regulator_is_enabled(host->vmmc))
++ regulator_disable(host->vmmc);
+ regulator_put(host->vmmc);
+ }
+
+ if (host->vqmmc) {
+- regulator_disable(host->vqmmc);
++ if (regulator_is_enabled(host->vqmmc))
++ regulator_disable(host->vqmmc);
+ regulator_put(host->vqmmc);
+ }
+
+- kfree(host->adma_desc);
++ if (host->adma_desc)
++ dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
++ host->adma_desc, host->adma_addr);
+ kfree(host->align_buffer);
+
+ host->adma_desc = NULL;
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-cns3xxx.c linux-3.14.72/drivers/mmc/host/sdhci-cns3xxx.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-cns3xxx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-cns3xxx.c 2016-06-19 22:11:55.201146831 +0200
+@@ -30,13 +30,12 @@
+ u16 clk;
+ unsigned long timeout;
+
+- if (clock == host->clock)
+- return;
++ host->mmc->actual_clock = 0;
+
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+ if (clock == 0)
+- goto out;
++ return;
+
+ while (host->max_clk / div > clock) {
+ /*
+@@ -75,13 +74,14 @@
+
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+-out:
+- host->clock = clock;
+ }
+
+ static const struct sdhci_ops sdhci_cns3xxx_ops = {
+ .get_max_clock = sdhci_cns3xxx_get_max_clk,
+ .set_clock = sdhci_cns3xxx_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
+@@ -90,8 +90,7 @@
+ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+ SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+- SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
+- SDHCI_QUIRK_NONSTANDARD_CLOCK,
++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
+ };
+
+ static int sdhci_cns3xxx_probe(struct platform_device *pdev)
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-dove.c linux-3.14.72/drivers/mmc/host/sdhci-dove.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-dove.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-dove.c 2016-06-19 22:11:55.201146831 +0200
+@@ -86,6 +86,10 @@
+ static const struct sdhci_ops sdhci_dove_ops = {
+ .read_w = sdhci_dove_readw,
+ .read_l = sdhci_dove_readl,
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_dove_pdata = {
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-esdhc.h linux-3.14.72/drivers/mmc/host/sdhci-esdhc.h
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-esdhc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-esdhc.h 2016-06-19 22:11:55.201146831 +0200
+@@ -20,10 +20,8 @@
+
+ #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
+ SDHCI_QUIRK_NO_BUSY_IRQ | \
+- SDHCI_QUIRK_NONSTANDARD_CLOCK | \
+ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
+- SDHCI_QUIRK_PIO_NEEDS_DELAY | \
+- SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
++ SDHCI_QUIRK_PIO_NEEDS_DELAY)
+
+ #define ESDHC_SYSTEM_CONTROL 0x2c
+ #define ESDHC_CLOCK_MASK 0x0000fff0
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-esdhc-imx.c linux-3.14.72/drivers/mmc/host/sdhci-esdhc-imx.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-esdhc-imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-esdhc-imx.c 2016-06-19 22:11:55.201146831 +0200
+@@ -11,6 +11,7 @@
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
++#include <linux/busfreq-imx6.h>
+ #include <linux/io.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
+@@ -114,6 +115,10 @@
+ #define ESDHC_FLAG_STD_TUNING BIT(5)
+ /* The IP has SDHCI_CAPABILITIES_1 register */
+ #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
++/* The IP has errata ERR004536 */
++#define ESDHC_FLAG_ERR004536 BIT(7)
++/* need request bus freq during low power */
++#define ESDHC_FLAG_BUSFREQ BIT(8)
+
+ struct esdhc_soc_data {
+ u32 flags;
+@@ -141,6 +146,12 @@
+
+ static struct esdhc_soc_data usdhc_imx6sl_data = {
+ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
++ | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
++ | ESDHC_FLAG_BUSFREQ,
++};
++
++static struct esdhc_soc_data usdhc_imx6sx_data = {
++ .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+ | ESDHC_FLAG_HAVE_CAP1,
+ };
+
+@@ -160,7 +171,6 @@
+ MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
+ WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
+ } multiblock_status;
+- u32 uhs_mode;
+ u32 is_ddr;
+ };
+
+@@ -185,6 +195,7 @@
+ { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
+ { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
+ { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
++ { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
+ { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
+ { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
+ { /* sentinel */ }
+@@ -382,7 +393,6 @@
+ if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
+ ret |= SDHCI_CTRL_TUNED_CLK;
+
+- ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK);
+ ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+
+ return ret;
+@@ -429,7 +439,6 @@
+ else
+ new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
+ writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
+- imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK;
+ if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
+ new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
+ if (val & SDHCI_CTRL_TUNED_CLK)
+@@ -450,6 +459,10 @@
+ if (val & SDHCI_CTRL_EXEC_TUNING) {
+ v |= ESDHC_MIX_CTRL_EXE_TUNE;
+ m |= ESDHC_MIX_CTRL_FBCLK_SEL;
++ writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
++ ESDHC_STD_TUNING_EN |
++ ESDHC_TUNING_START_TAP,
++ host->ioaddr + ESDHC_TUNING_CTRL);
+ } else {
+ v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
+ }
+@@ -600,12 +613,14 @@
+ u32 temp, val;
+
+ if (clock == 0) {
++ host->mmc->actual_clock = 0;
++
+ if (esdhc_is_usdhc(imx_data)) {
+ val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
+ writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
+ host->ioaddr + ESDHC_VENDOR_SPEC);
+ }
+- goto out;
++ return;
+ }
+
+ if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
+@@ -645,8 +660,6 @@
+ }
+
+ mdelay(1);
+-out:
+- host->clock = clock;
+ }
+
+ static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
+@@ -668,7 +681,7 @@
+ return -ENOSYS;
+ }
+
+-static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
++static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u32 ctrl;
+
+@@ -686,8 +699,6 @@
+
+ esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
+ SDHCI_HOST_CONTROL);
+-
+- return 0;
+ }
+
+ static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
+@@ -697,6 +708,7 @@
+ /* FIXME: delay a bit for card to be ready for next tuning due to errors */
+ mdelay(1);
+
++ /* This is balanced by the runtime put in sdhci_tasklet_finish */
+ pm_runtime_get_sync(host->mmc->parent);
+ reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
+ reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
+@@ -713,13 +725,12 @@
+ complete(&mrq->completion);
+ }
+
+-static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode)
++static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode,
++ struct scatterlist *sg)
+ {
+ struct mmc_command cmd = {0};
+ struct mmc_request mrq = {NULL};
+ struct mmc_data data = {0};
+- struct scatterlist sg;
+- char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN];
+
+ cmd.opcode = opcode;
+ cmd.arg = 0;
+@@ -728,11 +739,9 @@
+ data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
+ data.blocks = 1;
+ data.flags = MMC_DATA_READ;
+- data.sg = &sg;
++ data.sg = sg;
+ data.sg_len = 1;
+
+- sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern));
+-
+ mrq.cmd = &cmd;
+ mrq.cmd->mrq = &mrq;
+ mrq.data = &data;
+@@ -742,14 +751,12 @@
+ mrq.done = esdhc_request_done;
+ init_completion(&(mrq.completion));
+
+- disable_irq(host->irq);
+- spin_lock(&host->lock);
++ spin_lock_irq(&host->lock);
+ host->mrq = &mrq;
+
+ sdhci_send_command(host, mrq.cmd);
+
+- spin_unlock(&host->lock);
+- enable_irq(host->irq);
++ spin_unlock_irq(&host->lock);
+
+ wait_for_completion(&mrq.completion);
+
+@@ -772,13 +779,21 @@
+
+ static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
+ {
++ struct scatterlist sg;
++ char *tuning_pattern;
+ int min, max, avg, ret;
+
++ tuning_pattern = kmalloc(ESDHC_TUNING_BLOCK_PATTERN_LEN, GFP_KERNEL);
++ if (!tuning_pattern)
++ return -ENOMEM;
++
++ sg_init_one(&sg, tuning_pattern, ESDHC_TUNING_BLOCK_PATTERN_LEN);
++
+ /* find the mininum delay first which can pass tuning */
+ min = ESDHC_TUNE_CTRL_MIN;
+ while (min < ESDHC_TUNE_CTRL_MAX) {
+ esdhc_prepare_tuning(host, min);
+- if (!esdhc_send_tuning_cmd(host, opcode))
++ if (!esdhc_send_tuning_cmd(host, opcode, &sg))
+ break;
+ min += ESDHC_TUNE_CTRL_STEP;
+ }
+@@ -787,7 +802,7 @@
+ max = min + ESDHC_TUNE_CTRL_STEP;
+ while (max < ESDHC_TUNE_CTRL_MAX) {
+ esdhc_prepare_tuning(host, max);
+- if (esdhc_send_tuning_cmd(host, opcode)) {
++ if (esdhc_send_tuning_cmd(host, opcode, &sg)) {
+ max -= ESDHC_TUNE_CTRL_STEP;
+ break;
+ }
+@@ -797,9 +812,11 @@
+ /* use average delay to get the best timing */
+ avg = (min + max) / 2;
+ esdhc_prepare_tuning(host, avg);
+- ret = esdhc_send_tuning_cmd(host, opcode);
++ ret = esdhc_send_tuning_cmd(host, opcode, &sg);
+ esdhc_post_tuning(host);
+
++ kfree(tuning_pattern);
++
+ dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
+ ret ? "failed" : "passed", avg, ret);
+
+@@ -837,28 +854,21 @@
+ return pinctrl_select_state(imx_data->pinctrl, pinctrl);
+ }
+
+-static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
++static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data = pltfm_host->priv;
+ struct esdhc_platform_data *boarddata = &imx_data->boarddata;
+
+- switch (uhs) {
++ switch (timing) {
+ case MMC_TIMING_UHS_SDR12:
+- imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12;
+- break;
+ case MMC_TIMING_UHS_SDR25:
+- imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25;
+- break;
+ case MMC_TIMING_UHS_SDR50:
+- imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50;
+- break;
+ case MMC_TIMING_UHS_SDR104:
+ case MMC_TIMING_MMC_HS200:
+- imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104;
+ break;
++ case MMC_TIMING_MMC_DDR52:
+ case MMC_TIMING_UHS_DDR50:
+- imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
+ writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
+ ESDHC_MIX_CTRL_DDREN,
+ host->ioaddr + ESDHC_MIX_CTRL);
+@@ -875,7 +885,20 @@
+ break;
+ }
+
+- return esdhc_change_pinstate(host, uhs);
++ esdhc_change_pinstate(host, timing);
++}
++
++static unsigned int esdhc_get_max_timeout_counter(struct sdhci_host *host)
++{
++ return 1 << 28;
++}
++
++static void esdhc_reset(struct sdhci_host *host, u8 mask)
++{
++ sdhci_reset(host, mask);
++
++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ }
+
+ static struct sdhci_ops sdhci_esdhc_ops = {
+@@ -888,8 +911,9 @@
+ .get_max_clock = esdhc_pltfm_get_max_clock,
+ .get_min_clock = esdhc_pltfm_get_min_clock,
+ .get_ro = esdhc_pltfm_get_ro,
+- .platform_bus_width = esdhc_pltfm_bus_width,
++ .set_bus_width = esdhc_pltfm_set_bus_width,
+ .set_uhs_signaling = esdhc_set_uhs_signaling,
++ .reset = esdhc_reset,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
+@@ -906,6 +930,7 @@
+ struct esdhc_platform_data *boarddata)
+ {
+ struct device_node *np = pdev->dev.of_node;
++ struct sdhci_host *host = platform_get_drvdata(pdev);
+
+ if (!np)
+ return -ENODEV;
+@@ -939,6 +964,12 @@
+ if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
+ boarddata->delay_line = 0;
+
++ if (of_find_property(np, "keep-power-in-suspend", NULL))
++ host->mmc->pm_caps |= MMC_PM_KEEP_POWER;
++
++ if (of_find_property(np, "enable-sdio-wakeup", NULL))
++ host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
++
+ return 0;
+ }
+ #else
+@@ -996,6 +1027,10 @@
+
+ pltfm_host->clk = imx_data->clk_per;
+ pltfm_host->clock = clk_get_rate(pltfm_host->clk);
++
++ if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ)
++ request_bus_freq(BUS_FREQ_HIGH);
++
+ clk_prepare_enable(imx_data->clk_per);
+ clk_prepare_enable(imx_data->clk_ipg);
+ clk_prepare_enable(imx_data->clk_ahb);
+@@ -1027,18 +1062,25 @@
+ */
+ if (esdhc_is_usdhc(imx_data)) {
+ writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
+- host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
++ host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
++ SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER;
+ host->mmc->caps |= MMC_CAP_1_8V_DDR;
++
++ /*
++ * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
++ * TO1.1, it's harmless for MX6SL
++ */
++ writel(readl(host->ioaddr + 0x6c) | BIT(7), host->ioaddr + 0x6c);
++ sdhci_esdhc_ops.get_max_timeout_counter =
++ esdhc_get_max_timeout_counter;
+ }
+
+ if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
+ sdhci_esdhc_ops.platform_execute_tuning =
+ esdhc_executing_tuning;
+
+- if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
+- writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
+- ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
+- host->ioaddr + ESDHC_TUNING_CTRL);
++ if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
++ host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
+
+ boarddata = &imx_data->boarddata;
+ if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
+@@ -1116,15 +1158,17 @@
+ host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
+ }
+
++ device_set_wakeup_capable(&pdev->dev, 1);
++
+ err = sdhci_add_host(host);
+ if (err)
+ goto disable_clk;
+
+ pm_runtime_set_active(&pdev->dev);
+- pm_runtime_enable(&pdev->dev);
+ pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_suspend_ignore_children(&pdev->dev, 1);
++ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+
+@@ -1132,6 +1176,8 @@
+ clk_disable_unprepare(imx_data->clk_per);
+ clk_disable_unprepare(imx_data->clk_ipg);
+ clk_disable_unprepare(imx_data->clk_ahb);
++ if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ)
++ release_bus_freq(BUS_FREQ_HIGH);
+ free_sdhci:
+ sdhci_pltfm_free(pdev);
+ return err;
+@@ -1170,10 +1216,15 @@
+
+ ret = sdhci_runtime_suspend_host(host);
+
+- clk_disable_unprepare(imx_data->clk_per);
+- clk_disable_unprepare(imx_data->clk_ipg);
++ if (!sdhci_sdio_irq_enabled(host)) {
++ clk_disable_unprepare(imx_data->clk_per);
++ clk_disable_unprepare(imx_data->clk_ipg);
++ }
+ clk_disable_unprepare(imx_data->clk_ahb);
+
++ if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ)
++ release_bus_freq(BUS_FREQ_HIGH);
++
+ return ret;
+ }
+
+@@ -1183,8 +1234,13 @@
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct pltfm_imx_data *imx_data = pltfm_host->priv;
+
+- clk_prepare_enable(imx_data->clk_per);
+- clk_prepare_enable(imx_data->clk_ipg);
++ if (imx_data->socdata->flags & ESDHC_FLAG_BUSFREQ)
++ request_bus_freq(BUS_FREQ_HIGH);
++
++ if (!sdhci_sdio_irq_enabled(host)) {
++ clk_prepare_enable(imx_data->clk_per);
++ clk_prepare_enable(imx_data->clk_ipg);
++ }
+ clk_prepare_enable(imx_data->clk_ahb);
+
+ return sdhci_runtime_resume_host(host);
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci.h linux-3.14.72/drivers/mmc/host/sdhci.h
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci.h 2016-06-19 22:11:55.201146831 +0200
+@@ -281,18 +281,15 @@
+ unsigned int (*get_max_clock)(struct sdhci_host *host);
+ unsigned int (*get_min_clock)(struct sdhci_host *host);
+ unsigned int (*get_timeout_clock)(struct sdhci_host *host);
+- int (*platform_bus_width)(struct sdhci_host *host,
+- int width);
++ unsigned int (*get_max_timeout_counter)(struct sdhci_host *host);
++ void (*set_bus_width)(struct sdhci_host *host, int width);
+ void (*platform_send_init_74_clocks)(struct sdhci_host *host,
+ u8 power_mode);
+ unsigned int (*get_ro)(struct sdhci_host *host);
+- void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
+- void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
++ void (*reset)(struct sdhci_host *host, u8 mask);
+ int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
+- int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
++ void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
+ void (*hw_reset)(struct sdhci_host *host);
+- void (*platform_suspend)(struct sdhci_host *host);
+- void (*platform_resume)(struct sdhci_host *host);
+ void (*adma_workaround)(struct sdhci_host *host, u32 intmask);
+ void (*platform_init)(struct sdhci_host *host);
+ void (*card_event)(struct sdhci_host *host);
+@@ -397,6 +394,16 @@
+ extern void sdhci_send_command(struct sdhci_host *host,
+ struct mmc_command *cmd);
+
++static inline bool sdhci_sdio_irq_enabled(struct sdhci_host *host)
++{
++ return !!(host->flags & SDHCI_SDIO_IRQ_ENABLED);
++}
++
++void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
++void sdhci_set_bus_width(struct sdhci_host *host, int width);
++void sdhci_reset(struct sdhci_host *host, u8 mask);
++void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
++
+ #ifdef CONFIG_PM
+ extern int sdhci_suspend_host(struct sdhci_host *host);
+ extern int sdhci_resume_host(struct sdhci_host *host);
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-of-arasan.c linux-3.14.72/drivers/mmc/host/sdhci-of-arasan.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-of-arasan.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-of-arasan.c 2016-06-19 22:11:55.201146831 +0200
+@@ -52,8 +52,12 @@
+ }
+
+ static struct sdhci_ops sdhci_arasan_ops = {
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .get_timeout_clock = sdhci_arasan_get_timeout_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static struct sdhci_pltfm_data sdhci_arasan_pdata = {
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-of-esdhc.c linux-3.14.72/drivers/mmc/host/sdhci-of-esdhc.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-of-esdhc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-of-esdhc.c 2016-06-19 22:11:55.201146831 +0200
+@@ -199,13 +199,14 @@
+
+ static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
+ {
+-
+ int pre_div = 2;
+ int div = 1;
+ u32 temp;
+
++ host->mmc->actual_clock = 0;
++
+ if (clock == 0)
+- goto out;
++ return;
+
+ /* Workaround to reduce the clock frequency for p1010 esdhc */
+ if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
+@@ -238,24 +239,8 @@
+ | (pre_div << ESDHC_PREDIV_SHIFT));
+ sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
+ mdelay(1);
+-out:
+- host->clock = clock;
+ }
+
+-#ifdef CONFIG_PM
+-static u32 esdhc_proctl;
+-static void esdhc_of_suspend(struct sdhci_host *host)
+-{
+- esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
+-}
+-
+-static void esdhc_of_resume(struct sdhci_host *host)
+-{
+- esdhc_of_enable_dma(host);
+- sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
+-}
+-#endif
+-
+ static void esdhc_of_platform_init(struct sdhci_host *host)
+ {
+ u32 vvn;
+@@ -269,7 +254,7 @@
+ host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
+ }
+
+-static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
++static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u32 ctrl;
+
+@@ -289,8 +274,6 @@
+
+ clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL,
+ ESDHC_CTRL_BUSWIDTH_MASK, ctrl);
+-
+- return 0;
+ }
+
+ static const struct sdhci_ops sdhci_esdhc_ops = {
+@@ -305,13 +288,46 @@
+ .get_max_clock = esdhc_of_get_max_clock,
+ .get_min_clock = esdhc_of_get_min_clock,
+ .platform_init = esdhc_of_platform_init,
+-#ifdef CONFIG_PM
+- .platform_suspend = esdhc_of_suspend,
+- .platform_resume = esdhc_of_resume,
+-#endif
+ .adma_workaround = esdhci_of_adma_workaround,
+- .platform_bus_width = esdhc_pltfm_bus_width,
++ .set_bus_width = esdhc_pltfm_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
++};
++
++#ifdef CONFIG_PM
++
++static u32 esdhc_proctl;
++static int esdhc_of_suspend(struct device *dev)
++{
++ struct sdhci_host *host = dev_get_drvdata(dev);
++
++ esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
++
++ return sdhci_suspend_host(host);
++}
++
++static void esdhc_of_resume(device *dev)
++{
++ struct sdhci_host *host = dev_get_drvdata(dev);
++ int ret = sdhci_resume_host(host);
++
++ if (ret == 0) {
++ /* Isn't this already done by sdhci_resume_host() ? --rmk */
++ esdhc_of_enable_dma(host);
++ sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
++ }
++
++ return ret;
++}
++
++static const struct dev_pm_ops esdhc_pmops = {
++ .suspend = esdhci_of_suspend,
++ .resume = esdhci_of_resume,
+ };
++#define ESDHC_PMOPS (&esdhc_pmops)
++#else
++#define ESDHC_PMOPS NULL
++#endif
+
+ static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
+ /*
+@@ -374,7 +390,7 @@
+ .name = "sdhci-esdhc",
+ .owner = THIS_MODULE,
+ .of_match_table = sdhci_esdhc_of_match,
+- .pm = SDHCI_PLTFM_PMOPS,
++ .pm = ESDHC_PMOPS,
+ },
+ .probe = sdhci_esdhc_probe,
+ .remove = sdhci_esdhc_remove,
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-of-hlwd.c linux-3.14.72/drivers/mmc/host/sdhci-of-hlwd.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-of-hlwd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-of-hlwd.c 2016-06-19 22:11:55.201146831 +0200
+@@ -58,6 +58,10 @@
+ .write_l = sdhci_hlwd_writel,
+ .write_w = sdhci_hlwd_writew,
+ .write_b = sdhci_hlwd_writeb,
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_hlwd_pdata = {
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-pci.c linux-3.14.72/drivers/mmc/host/sdhci-pci.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-pci.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-pci.c 2016-06-19 22:11:55.201146831 +0200
+@@ -1023,7 +1023,7 @@
+ return 0;
+ }
+
+-static int sdhci_pci_bus_width(struct sdhci_host *host, int width)
++static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u8 ctrl;
+
+@@ -1044,8 +1044,6 @@
+ }
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+-
+- return 0;
+ }
+
+ static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
+@@ -1072,8 +1070,11 @@
+ }
+
+ static const struct sdhci_ops sdhci_pci_ops = {
++ .set_clock = sdhci_set_clock,
+ .enable_dma = sdhci_pci_enable_dma,
+- .platform_bus_width = sdhci_pci_bus_width,
++ .set_bus_width = sdhci_pci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .hw_reset = sdhci_pci_hw_reset,
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-pltfm.c linux-3.14.72/drivers/mmc/host/sdhci-pltfm.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-pltfm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-pltfm.c 2016-06-19 22:11:55.201146831 +0200
+@@ -45,6 +45,10 @@
+ EXPORT_SYMBOL_GPL(sdhci_pltfm_clk_get_max_clock);
+
+ static const struct sdhci_ops sdhci_pltfm_ops = {
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ #ifdef CONFIG_OF
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-pxav2.c linux-3.14.72/drivers/mmc/host/sdhci-pxav2.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-pxav2.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-pxav2.c 2016-06-19 22:11:55.201146831 +0200
+@@ -51,11 +51,13 @@
+ #define MMC_CARD 0x1000
+ #define MMC_WIDTH 0x0100
+
+-static void pxav2_set_private_registers(struct sdhci_host *host, u8 mask)
++static void pxav2_reset(struct sdhci_host *host, u8 mask)
+ {
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
++ sdhci_reset(host, mask);
++
+ if (mask == SDHCI_RESET_ALL) {
+ u16 tmp = 0;
+
+@@ -88,7 +90,7 @@
+ }
+ }
+
+-static int pxav2_mmc_set_width(struct sdhci_host *host, int width)
++static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u8 ctrl;
+ u16 tmp;
+@@ -107,14 +109,14 @@
+ }
+ writew(tmp, host->ioaddr + SD_CE_ATA_2);
+ writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
+-
+- return 0;
+ }
+
+ static const struct sdhci_ops pxav2_sdhci_ops = {
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+- .platform_reset_exit = pxav2_set_private_registers,
+- .platform_bus_width = pxav2_mmc_set_width,
++ .set_bus_width = pxav2_mmc_set_bus_width,
++ .reset = pxav2_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ #ifdef CONFIG_OF
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-pxav3.c linux-3.14.72/drivers/mmc/host/sdhci-pxav3.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-pxav3.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-pxav3.c 2016-06-19 22:11:55.201146831 +0200
+@@ -57,11 +57,13 @@
+ #define SDCE_MISC_INT (1<<2)
+ #define SDCE_MISC_INT_EN (1<<1)
+
+-static void pxav3_set_private_registers(struct sdhci_host *host, u8 mask)
++static void pxav3_reset(struct sdhci_host *host, u8 mask)
+ {
+ struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+ struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+
++ sdhci_reset(host, mask);
++
+ if (mask == SDHCI_RESET_ALL) {
+ /*
+ * tune timing of read data/command when crc error happen
+@@ -168,10 +170,13 @@
+ }
+
+ static const struct sdhci_ops pxav3_sdhci_ops = {
+- .platform_reset_exit = pxav3_set_private_registers,
++ .set_clock = sdhci_set_clock,
+ .set_uhs_signaling = pxav3_set_uhs_signaling,
+ .platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = pxav3_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-s3c.c linux-3.14.72/drivers/mmc/host/sdhci-s3c.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-s3c.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-s3c.c 2016-06-19 22:11:55.201146831 +0200
+@@ -57,6 +57,8 @@
+
+ struct clk *clk_io;
+ struct clk *clk_bus[MAX_BUS_CLK];
++
++ bool no_divider;
+ };
+
+ /**
+@@ -69,6 +71,7 @@
+ */
+ struct sdhci_s3c_drv_data {
+ unsigned int sdhci_quirks;
++ bool no_divider;
+ };
+
+ static inline struct sdhci_s3c *to_s3c(struct sdhci_host *host)
+@@ -153,7 +156,7 @@
+ * If controller uses a non-standard clock division, find the best clock
+ * speed possible with selected clock source and skip the division.
+ */
+- if (ourhost->host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
++ if (ourhost->no_divider) {
+ rate = clk_round_rate(clksrc, wanted);
+ return wanted - rate;
+ }
+@@ -188,9 +191,13 @@
+ int src;
+ u32 ctrl;
+
++ host->mmc->actual_clock = 0;
++
+ /* don't bother if the clock is going off. */
+- if (clock == 0)
++ if (clock == 0) {
++ sdhci_set_clock(host, clock);
+ return;
++ }
+
+ for (src = 0; src < MAX_BUS_CLK; src++) {
+ delta = sdhci_s3c_consider_clock(ourhost, src, clock);
+@@ -240,6 +247,8 @@
+ if (clock < 25 * 1000000)
+ ctrl |= (S3C_SDHCI_CTRL3_FCSEL3 | S3C_SDHCI_CTRL3_FCSEL2);
+ writel(ctrl, host->ioaddr + S3C_SDHCI_CONTROL3);
++
++ sdhci_set_clock(host, clock);
+ }
+
+ /**
+@@ -296,10 +305,11 @@
+ unsigned long timeout;
+ u16 clk = 0;
+
++ host->mmc->actual_clock = 0;
++
+ /* If the clock is going off, set to 0 at clock control register */
+ if (clock == 0) {
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+- host->clock = clock;
+ return;
+ }
+
+@@ -307,8 +317,6 @@
+
+ clk_set_rate(ourhost->clk_bus[ourhost->cur_clk], clock);
+
+- host->clock = clock;
+-
+ clk = SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+@@ -330,14 +338,14 @@
+ }
+
+ /**
+- * sdhci_s3c_platform_bus_width - support 8bit buswidth
++ * sdhci_s3c_set_bus_width - support 8bit buswidth
+ * @host: The SDHCI host being queried
+ * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
+ *
+ * We have 8-bit width support but is not a v3 controller.
+ * So we add platform_bus_width() and support 8bit width.
+ */
+-static int sdhci_s3c_platform_bus_width(struct sdhci_host *host, int width)
++static void sdhci_s3c_set_bus_width(struct sdhci_host *host, int width)
+ {
+ u8 ctrl;
+
+@@ -359,15 +367,15 @@
+ }
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+-
+- return 0;
+ }
+
+ static struct sdhci_ops sdhci_s3c_ops = {
+ .get_max_clock = sdhci_s3c_get_max_clk,
+ .set_clock = sdhci_s3c_set_clock,
+ .get_min_clock = sdhci_s3c_get_min_clock,
+- .platform_bus_width = sdhci_s3c_platform_bus_width,
++ .set_bus_width = sdhci_s3c_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
+@@ -617,8 +625,10 @@
+ /* Setup quirks for the controller */
+ host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
+ host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
+- if (drv_data)
++ if (drv_data) {
+ host->quirks |= drv_data->sdhci_quirks;
++ sc->no_divider = drv_data->no_divider;
++ }
+
+ #ifndef CONFIG_MMC_SDHCI_S3C_DMA
+
+@@ -667,7 +677,7 @@
+ * If controller does not have internal clock divider,
+ * we can use overriding functions instead of default.
+ */
+- if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) {
++ if (sc->no_divider) {
+ sdhci_s3c_ops.set_clock = sdhci_cmu_set_clock;
+ sdhci_s3c_ops.get_min_clock = sdhci_cmu_get_min_clock;
+ sdhci_s3c_ops.get_max_clock = sdhci_cmu_get_max_clock;
+@@ -813,7 +823,7 @@
+
+ #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
+ static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data = {
+- .sdhci_quirks = SDHCI_QUIRK_NONSTANDARD_CLOCK,
++ .no_divider = true,
+ };
+ #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
+ #else
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-sirf.c linux-3.14.72/drivers/mmc/host/sdhci-sirf.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-sirf.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-sirf.c 2016-06-19 22:11:55.201146831 +0200
+@@ -28,7 +28,11 @@
+ }
+
+ static struct sdhci_ops sdhci_sirf_ops = {
++ .set_clock = sdhci_set_clock,
+ .get_max_clock = sdhci_sirf_get_max_clk,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static struct sdhci_pltfm_data sdhci_sirf_pdata = {
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-spear.c linux-3.14.72/drivers/mmc/host/sdhci-spear.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-spear.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-spear.c 2016-06-19 22:11:55.201146831 +0200
+@@ -37,7 +37,10 @@
+
+ /* sdhci ops */
+ static const struct sdhci_ops sdhci_pltfm_ops = {
+- /* Nothing to do for now. */
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = sdhci_set_bus_width,
++ .reset = sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ /* gpio card detection interrupt handler */
+diff -Nur linux-3.14.72.orig/drivers/mmc/host/sdhci-tegra.c linux-3.14.72/drivers/mmc/host/sdhci-tegra.c
+--- linux-3.14.72.orig/drivers/mmc/host/sdhci-tegra.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mmc/host/sdhci-tegra.c 2016-06-19 22:11:55.201146831 +0200
+@@ -48,19 +48,6 @@
+ int power_gpio;
+ };
+
+-static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
+-{
+- u32 val;
+-
+- if (unlikely(reg == SDHCI_PRESENT_STATE)) {
+- /* Use wp_gpio here instead? */
+- val = readl(host->ioaddr + reg);
+- return val | SDHCI_WRITE_PROTECT;
+- }
+-
+- return readl(host->ioaddr + reg);
+-}
+-
+ static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+@@ -108,12 +95,14 @@
+ return mmc_gpio_get_ro(host->mmc);
+ }
+
+-static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
++static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_tegra *tegra_host = pltfm_host->priv;
+ const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
+
++ sdhci_reset(host, mask);
++
+ if (!(mask & SDHCI_RESET_ALL))
+ return;
+
+@@ -127,7 +116,7 @@
+ }
+ }
+
+-static int tegra_sdhci_buswidth(struct sdhci_host *host, int bus_width)
++static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width)
+ {
+ u32 ctrl;
+
+@@ -144,16 +133,16 @@
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ }
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+- return 0;
+ }
+
+ static const struct sdhci_ops tegra_sdhci_ops = {
+ .get_ro = tegra_sdhci_get_ro,
+- .read_l = tegra_sdhci_readl,
+ .read_w = tegra_sdhci_readw,
+ .write_l = tegra_sdhci_writel,
+- .platform_bus_width = tegra_sdhci_buswidth,
+- .platform_reset_exit = tegra_sdhci_reset_exit,
++ .set_clock = sdhci_set_clock,
++ .set_bus_width = tegra_sdhci_set_bus_width,
++ .reset = tegra_sdhci_reset,
++ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ };
+
+ static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
+diff -Nur linux-3.14.72.orig/drivers/mtd/devices/Kconfig linux-3.14.72/drivers/mtd/devices/Kconfig
+--- linux-3.14.72.orig/drivers/mtd/devices/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/devices/Kconfig 2016-06-19 22:11:55.201146831 +0200
+@@ -80,7 +80,7 @@
+
+ config MTD_M25P80
+ tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
+- depends on SPI_MASTER
++ depends on SPI_MASTER && MTD_SPI_NOR
+ help
+ This enables access to most modern SPI flash chips, used for
+ program and data storage. Series supported include Atmel AT26DF,
+diff -Nur linux-3.14.72.orig/drivers/mtd/devices/m25p80.c linux-3.14.72/drivers/mtd/devices/m25p80.c
+--- linux-3.14.72.orig/drivers/mtd/devices/m25p80.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/devices/m25p80.c 2016-06-19 22:11:55.205146568 +0200
+@@ -15,484 +15,102 @@
+ *
+ */
+
+-#include <linux/init.h>
+ #include <linux/err.h>
+ #include <linux/errno.h>
+ #include <linux/module.h>
+ #include <linux/device.h>
+-#include <linux/interrupt.h>
+-#include <linux/mutex.h>
+-#include <linux/math64.h>
+-#include <linux/slab.h>
+-#include <linux/sched.h>
+-#include <linux/mod_devicetable.h>
+
+-#include <linux/mtd/cfi.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
+-#include <linux/of_platform.h>
+
+ #include <linux/spi/spi.h>
+ #include <linux/spi/flash.h>
++#include <linux/mtd/spi-nor.h>
+
+-/* Flash opcodes. */
+-#define OPCODE_WREN 0x06 /* Write enable */
+-#define OPCODE_RDSR 0x05 /* Read status register */
+-#define OPCODE_WRSR 0x01 /* Write status register 1 byte */
+-#define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
+-#define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
+-#define OPCODE_QUAD_READ 0x6b /* Read data bytes */
+-#define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
+-#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
+-#define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
+-#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
+-#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
+-#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
+-#define OPCODE_RDID 0x9f /* Read JEDEC ID */
+-#define OPCODE_RDCR 0x35 /* Read configuration register */
+-
+-/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
+-#define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
+-#define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
+-#define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes */
+-#define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
+-#define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
+-
+-/* Used for SST flashes only. */
+-#define OPCODE_BP 0x02 /* Byte program */
+-#define OPCODE_WRDI 0x04 /* Write disable */
+-#define OPCODE_AAI_WP 0xad /* Auto address increment word program */
+-
+-/* Used for Macronix and Winbond flashes. */
+-#define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
+-#define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
+-
+-/* Used for Spansion flashes only. */
+-#define OPCODE_BRWR 0x17 /* Bank register write */
+-
+-/* Status Register bits. */
+-#define SR_WIP 1 /* Write in progress */
+-#define SR_WEL 2 /* Write enable latch */
+-/* meaning of other SR_* bits may differ between vendors */
+-#define SR_BP0 4 /* Block protect 0 */
+-#define SR_BP1 8 /* Block protect 1 */
+-#define SR_BP2 0x10 /* Block protect 2 */
+-#define SR_SRWD 0x80 /* SR write protect */
+-
+-#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
+-
+-/* Configuration Register bits. */
+-#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
+-
+-/* Define max times to check status register before we give up. */
+-#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
+ #define MAX_CMD_SIZE 6
+-
+-#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
+-
+-/****************************************************************************/
+-
+-enum read_type {
+- M25P80_NORMAL = 0,
+- M25P80_FAST,
+- M25P80_QUAD,
+-};
+-
+ struct m25p {
+ struct spi_device *spi;
+- struct mutex lock;
++ struct spi_nor spi_nor;
+ struct mtd_info mtd;
+- u16 page_size;
+- u16 addr_width;
+- u8 erase_opcode;
+- u8 read_opcode;
+- u8 program_opcode;
+- u8 *command;
+- enum read_type flash_read;
++ u8 command[MAX_CMD_SIZE];
+ };
+
+-static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
+-{
+- return container_of(mtd, struct m25p, mtd);
+-}
+-
+-/****************************************************************************/
+-
+-/*
+- * Internal helper functions
+- */
+-
+-/*
+- * Read the status register, returning its value in the location
+- * Return the status register value.
+- * Returns negative if error occurred.
+- */
+-static int read_sr(struct m25p *flash)
+-{
+- ssize_t retval;
+- u8 code = OPCODE_RDSR;
+- u8 val;
+-
+- retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
+-
+- if (retval < 0) {
+- dev_err(&flash->spi->dev, "error %d reading SR\n",
+- (int) retval);
+- return retval;
+- }
+-
+- return val;
+-}
+-
+-/*
+- * Read configuration register, returning its value in the
+- * location. Return the configuration register value.
+- * Returns negative if error occured.
+- */
+-static int read_cr(struct m25p *flash)
++static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)
+ {
+- u8 code = OPCODE_RDCR;
++ struct m25p *flash = nor->priv;
++ struct spi_device *spi = flash->spi;
+ int ret;
+- u8 val;
+-
+- ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
+- if (ret < 0) {
+- dev_err(&flash->spi->dev, "error %d reading CR\n", ret);
+- return ret;
+- }
+-
+- return val;
+-}
+-
+-/*
+- * Write status register 1 byte
+- * Returns negative if error occurred.
+- */
+-static int write_sr(struct m25p *flash, u8 val)
+-{
+- flash->command[0] = OPCODE_WRSR;
+- flash->command[1] = val;
+-
+- return spi_write(flash->spi, flash->command, 2);
+-}
+-
+-/*
+- * Set write enable latch with Write Enable command.
+- * Returns negative if error occurred.
+- */
+-static inline int write_enable(struct m25p *flash)
+-{
+- u8 code = OPCODE_WREN;
+-
+- return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
+-}
+-
+-/*
+- * Send write disble instruction to the chip.
+- */
+-static inline int write_disable(struct m25p *flash)
+-{
+- u8 code = OPCODE_WRDI;
+-
+- return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
+-}
+-
+-/*
+- * Enable/disable 4-byte addressing mode.
+- */
+-static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
+-{
+- int status;
+- bool need_wren = false;
+-
+- switch (JEDEC_MFR(jedec_id)) {
+- case CFI_MFR_ST: /* Micron, actually */
+- /* Some Micron need WREN command; all will accept it */
+- need_wren = true;
+- case CFI_MFR_MACRONIX:
+- case 0xEF /* winbond */:
+- if (need_wren)
+- write_enable(flash);
+-
+- flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
+- status = spi_write(flash->spi, flash->command, 1);
+-
+- if (need_wren)
+- write_disable(flash);
+-
+- return status;
+- default:
+- /* Spansion style */
+- flash->command[0] = OPCODE_BRWR;
+- flash->command[1] = enable << 7;
+- return spi_write(flash->spi, flash->command, 2);
+- }
+-}
+-
+-/*
+- * Service routine to read status register until ready, or timeout occurs.
+- * Returns non-zero if error.
+- */
+-static int wait_till_ready(struct m25p *flash)
+-{
+- unsigned long deadline;
+- int sr;
+-
+- deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+-
+- do {
+- if ((sr = read_sr(flash)) < 0)
+- break;
+- else if (!(sr & SR_WIP))
+- return 0;
+-
+- cond_resched();
+-
+- } while (!time_after_eq(jiffies, deadline));
+-
+- return 1;
+-}
+-
+-/*
+- * Write status Register and configuration register with 2 bytes
+- * The first byte will be written to the status register, while the
+- * second byte will be written to the configuration register.
+- * Return negative if error occured.
+- */
+-static int write_sr_cr(struct m25p *flash, u16 val)
+-{
+- flash->command[0] = OPCODE_WRSR;
+- flash->command[1] = val & 0xff;
+- flash->command[2] = (val >> 8);
+
+- return spi_write(flash->spi, flash->command, 3);
+-}
++ ret = spi_write_then_read(spi, &code, 1, val, len);
++ if (ret < 0)
++ dev_err(&spi->dev, "error %d reading %x\n", ret, code);
+
+-static int macronix_quad_enable(struct m25p *flash)
+-{
+- int ret, val;
+- u8 cmd[2];
+- cmd[0] = OPCODE_WRSR;
+-
+- val = read_sr(flash);
+- cmd[1] = val | SR_QUAD_EN_MX;
+- write_enable(flash);
+-
+- spi_write(flash->spi, &cmd, 2);
+-
+- if (wait_till_ready(flash))
+- return 1;
+-
+- ret = read_sr(flash);
+- if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
+- dev_err(&flash->spi->dev, "Macronix Quad bit not set\n");
+- return -EINVAL;
+- }
+-
+- return 0;
++ return ret;
+ }
+
+-static int spansion_quad_enable(struct m25p *flash)
++static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
+ {
+- int ret;
+- int quad_en = CR_QUAD_EN_SPAN << 8;
+-
+- write_enable(flash);
+-
+- ret = write_sr_cr(flash, quad_en);
+- if (ret < 0) {
+- dev_err(&flash->spi->dev,
+- "error while writing configuration register\n");
+- return -EINVAL;
+- }
+-
+- /* read back and check it */
+- ret = read_cr(flash);
+- if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
+- dev_err(&flash->spi->dev, "Spansion Quad bit not set\n");
+- return -EINVAL;
+- }
+-
+- return 0;
++ /* opcode is in cmd[0] */
++ cmd[1] = addr >> (nor->addr_width * 8 - 8);
++ cmd[2] = addr >> (nor->addr_width * 8 - 16);
++ cmd[3] = addr >> (nor->addr_width * 8 - 24);
++ cmd[4] = addr >> (nor->addr_width * 8 - 32);
+ }
+
+-static int set_quad_mode(struct m25p *flash, u32 jedec_id)
++static int m25p_cmdsz(struct spi_nor *nor)
+ {
+- int status;
+-
+- switch (JEDEC_MFR(jedec_id)) {
+- case CFI_MFR_MACRONIX:
+- status = macronix_quad_enable(flash);
+- if (status) {
+- dev_err(&flash->spi->dev,
+- "Macronix quad-read not enabled\n");
+- return -EINVAL;
+- }
+- return status;
+- default:
+- status = spansion_quad_enable(flash);
+- if (status) {
+- dev_err(&flash->spi->dev,
+- "Spansion quad-read not enabled\n");
+- return -EINVAL;
+- }
+- return status;
+- }
++ return 1 + nor->addr_width;
+ }
+
+-/*
+- * Erase the whole flash memory
+- *
+- * Returns 0 if successful, non-zero otherwise.
+- */
+-static int erase_chip(struct m25p *flash)
++static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
++ int wr_en)
+ {
+- pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
+- (long long)(flash->mtd.size >> 10));
+-
+- /* Wait until finished previous write command. */
+- if (wait_till_ready(flash))
+- return 1;
+-
+- /* Send write enable, then erase commands. */
+- write_enable(flash);
+-
+- /* Set up command buffer. */
+- flash->command[0] = OPCODE_CHIP_ERASE;
++ struct m25p *flash = nor->priv;
++ struct spi_device *spi = flash->spi;
+
+- spi_write(flash->spi, flash->command, 1);
+-
+- return 0;
+-}
+-
+-static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
+-{
+- /* opcode is in cmd[0] */
+- cmd[1] = addr >> (flash->addr_width * 8 - 8);
+- cmd[2] = addr >> (flash->addr_width * 8 - 16);
+- cmd[3] = addr >> (flash->addr_width * 8 - 24);
+- cmd[4] = addr >> (flash->addr_width * 8 - 32);
+-}
++ flash->command[0] = opcode;
++ if (buf)
++ memcpy(&flash->command[1], buf, len);
+
+-static int m25p_cmdsz(struct m25p *flash)
+-{
+- return 1 + flash->addr_width;
++ return spi_write(spi, flash->command, len + 1);
+ }
+
+-/*
+- * Erase one sector of flash memory at offset ``offset'' which is any
+- * address within the sector which should be erased.
+- *
+- * Returns 0 if successful, non-zero otherwise.
+- */
+-static int erase_sector(struct m25p *flash, u32 offset)
++static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
++ size_t *retlen, const u_char *buf)
+ {
+- pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
+- __func__, flash->mtd.erasesize / 1024, offset);
+-
+- /* Wait until finished previous write command. */
+- if (wait_till_ready(flash))
+- return 1;
+-
+- /* Send write enable, then erase commands. */
+- write_enable(flash);
+-
+- /* Set up command buffer. */
+- flash->command[0] = flash->erase_opcode;
+- m25p_addr2cmd(flash, offset, flash->command);
+-
+- spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
+-
+- return 0;
+-}
++ struct m25p *flash = nor->priv;
++ struct spi_device *spi = flash->spi;
++ struct spi_transfer t[2] = {};
++ struct spi_message m;
++ int cmd_sz = m25p_cmdsz(nor);
+
+-/****************************************************************************/
++ spi_message_init(&m);
+
+-/*
+- * MTD implementation
+- */
++ if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
++ cmd_sz = 1;
+
+-/*
+- * Erase an address range on the flash chip. The address range may extend
+- * one or more erase sectors. Return an error is there is a problem erasing.
+- */
+-static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
+-{
+- struct m25p *flash = mtd_to_m25p(mtd);
+- u32 addr,len;
+- uint32_t rem;
+-
+- pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
+- __func__, (long long)instr->addr,
+- (long long)instr->len);
+-
+- div_u64_rem(instr->len, mtd->erasesize, &rem);
+- if (rem)
+- return -EINVAL;
+-
+- addr = instr->addr;
+- len = instr->len;
+-
+- mutex_lock(&flash->lock);
+-
+- /* whole-chip erase? */
+- if (len == flash->mtd.size) {
+- if (erase_chip(flash)) {
+- instr->state = MTD_ERASE_FAILED;
+- mutex_unlock(&flash->lock);
+- return -EIO;
+- }
+-
+- /* REVISIT in some cases we could speed up erasing large regions
+- * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
+- * to use "small sector erase", but that's not always optimal.
+- */
+-
+- /* "sector"-at-a-time erase */
+- } else {
+- while (len) {
+- if (erase_sector(flash, addr)) {
+- instr->state = MTD_ERASE_FAILED;
+- mutex_unlock(&flash->lock);
+- return -EIO;
+- }
+-
+- addr += mtd->erasesize;
+- len -= mtd->erasesize;
+- }
+- }
++ flash->command[0] = nor->program_opcode;
++ m25p_addr2cmd(nor, to, flash->command);
+
+- mutex_unlock(&flash->lock);
++ t[0].tx_buf = flash->command;
++ t[0].len = cmd_sz;
++ spi_message_add_tail(&t[0], &m);
+
+- instr->state = MTD_ERASE_DONE;
+- mtd_erase_callback(instr);
++ t[1].tx_buf = buf;
++ t[1].len = len;
++ spi_message_add_tail(&t[1], &m);
+
+- return 0;
+-}
++ spi_sync(spi, &m);
+
+-/*
+- * Dummy Cycle calculation for different type of read.
+- * It can be used to support more commands with
+- * different dummy cycle requirements.
+- */
+-static inline int m25p80_dummy_cycles_read(struct m25p *flash)
+-{
+- switch (flash->flash_read) {
+- case M25P80_FAST:
+- case M25P80_QUAD:
+- return 1;
+- case M25P80_NORMAL:
+- return 0;
+- default:
+- dev_err(&flash->spi->dev, "No valid read type supported\n");
+- return -1;
+- }
++ *retlen += m.actual_length - cmd_sz;
+ }
+
+-static inline unsigned int m25p80_rx_nbits(const struct m25p *flash)
++static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor)
+ {
+- switch (flash->flash_read) {
+- case M25P80_QUAD:
++ switch (nor->flash_read) {
++ case SPI_NOR_DUAL:
++ return 2;
++ case SPI_NOR_QUAD:
+ return 4;
+ default:
+ return 0;
+@@ -500,588 +118,75 @@
+ }
+
+ /*
+- * Read an address range from the flash chip. The address range
++ * Read an address range from the nor chip. The address range
+ * may be any size provided it is within the physical boundaries.
+ */
+-static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
+- size_t *retlen, u_char *buf)
++static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
++ size_t *retlen, u_char *buf)
+ {
+- struct m25p *flash = mtd_to_m25p(mtd);
++ struct m25p *flash = nor->priv;
++ struct spi_device *spi = flash->spi;
+ struct spi_transfer t[2];
+ struct spi_message m;
+- uint8_t opcode;
+- int dummy;
++ unsigned int dummy = nor->read_dummy;
++ int ret;
+
+- pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
+- __func__, (u32)from, len);
++ /* convert the dummy cycles to the number of bytes */
++ dummy /= 8;
++
++ /* Wait till previous write/erase is done. */
++ ret = nor->wait_till_ready(nor);
++ if (ret)
++ return ret;
+
+ spi_message_init(&m);
+ memset(t, 0, (sizeof t));
+
+- dummy = m25p80_dummy_cycles_read(flash);
+- if (dummy < 0) {
+- dev_err(&flash->spi->dev, "No valid read command supported\n");
+- return -EINVAL;
+- }
++ flash->command[0] = nor->read_opcode;
++ m25p_addr2cmd(nor, from, flash->command);
+
+ t[0].tx_buf = flash->command;
+- t[0].len = m25p_cmdsz(flash) + dummy;
++ t[0].len = m25p_cmdsz(nor) + dummy;
+ spi_message_add_tail(&t[0], &m);
+
+ t[1].rx_buf = buf;
+- t[1].rx_nbits = m25p80_rx_nbits(flash);
++ t[1].rx_nbits = m25p80_rx_nbits(nor);
+ t[1].len = len;
+ spi_message_add_tail(&t[1], &m);
+
+- mutex_lock(&flash->lock);
+-
+- /* Wait till previous write/erase is done. */
+- if (wait_till_ready(flash)) {
+- /* REVISIT status return?? */
+- mutex_unlock(&flash->lock);
+- return 1;
+- }
+-
+- /* Set up the write data buffer. */
+- opcode = flash->read_opcode;
+- flash->command[0] = opcode;
+- m25p_addr2cmd(flash, from, flash->command);
+-
+- spi_sync(flash->spi, &m);
+-
+- *retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
+-
+- mutex_unlock(&flash->lock);
+-
+- return 0;
+-}
+-
+-/*
+- * Write an address range to the flash chip. Data must be written in
+- * FLASH_PAGESIZE chunks. The address range may be any size provided
+- * it is within the physical boundaries.
+- */
+-static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
+- size_t *retlen, const u_char *buf)
+-{
+- struct m25p *flash = mtd_to_m25p(mtd);
+- u32 page_offset, page_size;
+- struct spi_transfer t[2];
+- struct spi_message m;
+-
+- pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
+- __func__, (u32)to, len);
+-
+- spi_message_init(&m);
+- memset(t, 0, (sizeof t));
+-
+- t[0].tx_buf = flash->command;
+- t[0].len = m25p_cmdsz(flash);
+- spi_message_add_tail(&t[0], &m);
+-
+- t[1].tx_buf = buf;
+- spi_message_add_tail(&t[1], &m);
+-
+- mutex_lock(&flash->lock);
+-
+- /* Wait until finished previous write command. */
+- if (wait_till_ready(flash)) {
+- mutex_unlock(&flash->lock);
+- return 1;
+- }
+-
+- write_enable(flash);
+-
+- /* Set up the opcode in the write buffer. */
+- flash->command[0] = flash->program_opcode;
+- m25p_addr2cmd(flash, to, flash->command);
+-
+- page_offset = to & (flash->page_size - 1);
+-
+- /* do all the bytes fit onto one page? */
+- if (page_offset + len <= flash->page_size) {
+- t[1].len = len;
+-
+- spi_sync(flash->spi, &m);
+-
+- *retlen = m.actual_length - m25p_cmdsz(flash);
+- } else {
+- u32 i;
+-
+- /* the size of data remaining on the first page */
+- page_size = flash->page_size - page_offset;
+-
+- t[1].len = page_size;
+- spi_sync(flash->spi, &m);
+-
+- *retlen = m.actual_length - m25p_cmdsz(flash);
+-
+- /* write everything in flash->page_size chunks */
+- for (i = page_size; i < len; i += page_size) {
+- page_size = len - i;
+- if (page_size > flash->page_size)
+- page_size = flash->page_size;
+-
+- /* write the next page to flash */
+- m25p_addr2cmd(flash, to + i, flash->command);
+-
+- t[1].tx_buf = buf + i;
+- t[1].len = page_size;
+-
+- wait_till_ready(flash);
+-
+- write_enable(flash);
+-
+- spi_sync(flash->spi, &m);
+-
+- *retlen += m.actual_length - m25p_cmdsz(flash);
+- }
+- }
+-
+- mutex_unlock(&flash->lock);
++ spi_sync(spi, &m);
+
++ *retlen = m.actual_length - m25p_cmdsz(nor) - dummy;
+ return 0;
+ }
+
+-static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
+- size_t *retlen, const u_char *buf)
++static int m25p80_erase(struct spi_nor *nor, loff_t offset)
+ {
+- struct m25p *flash = mtd_to_m25p(mtd);
+- struct spi_transfer t[2];
+- struct spi_message m;
+- size_t actual;
+- int cmd_sz, ret;
+-
+- pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
+- __func__, (u32)to, len);
+-
+- spi_message_init(&m);
+- memset(t, 0, (sizeof t));
+-
+- t[0].tx_buf = flash->command;
+- t[0].len = m25p_cmdsz(flash);
+- spi_message_add_tail(&t[0], &m);
+-
+- t[1].tx_buf = buf;
+- spi_message_add_tail(&t[1], &m);
++ struct m25p *flash = nor->priv;
++ int ret;
+
+- mutex_lock(&flash->lock);
++ dev_dbg(nor->dev, "%dKiB at 0x%08x\n",
++ flash->mtd.erasesize / 1024, (u32)offset);
+
+ /* Wait until finished previous write command. */
+- ret = wait_till_ready(flash);
++ ret = nor->wait_till_ready(nor);
+ if (ret)
+- goto time_out;
+-
+- write_enable(flash);
+-
+- actual = to % 2;
+- /* Start write from odd address. */
+- if (actual) {
+- flash->command[0] = OPCODE_BP;
+- m25p_addr2cmd(flash, to, flash->command);
+-
+- /* write one byte. */
+- t[1].len = 1;
+- spi_sync(flash->spi, &m);
+- ret = wait_till_ready(flash);
+- if (ret)
+- goto time_out;
+- *retlen += m.actual_length - m25p_cmdsz(flash);
+- }
+- to += actual;
+-
+- flash->command[0] = OPCODE_AAI_WP;
+- m25p_addr2cmd(flash, to, flash->command);
++ return ret;
+
+- /* Write out most of the data here. */
+- cmd_sz = m25p_cmdsz(flash);
+- for (; actual < len - 1; actual += 2) {
+- t[0].len = cmd_sz;
+- /* write two bytes. */
+- t[1].len = 2;
+- t[1].tx_buf = buf + actual;
+-
+- spi_sync(flash->spi, &m);
+- ret = wait_till_ready(flash);
+- if (ret)
+- goto time_out;
+- *retlen += m.actual_length - cmd_sz;
+- cmd_sz = 1;
+- to += 2;
+- }
+- write_disable(flash);
+- ret = wait_till_ready(flash);
++ /* Send write enable, then erase commands. */
++ ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
+ if (ret)
+- goto time_out;
+-
+- /* Write out trailing byte if it exists. */
+- if (actual != len) {
+- write_enable(flash);
+- flash->command[0] = OPCODE_BP;
+- m25p_addr2cmd(flash, to, flash->command);
+- t[0].len = m25p_cmdsz(flash);
+- t[1].len = 1;
+- t[1].tx_buf = buf + actual;
+-
+- spi_sync(flash->spi, &m);
+- ret = wait_till_ready(flash);
+- if (ret)
+- goto time_out;
+- *retlen += m.actual_length - m25p_cmdsz(flash);
+- write_disable(flash);
+- }
+-
+-time_out:
+- mutex_unlock(&flash->lock);
+- return ret;
+-}
+-
+-static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+-{
+- struct m25p *flash = mtd_to_m25p(mtd);
+- uint32_t offset = ofs;
+- uint8_t status_old, status_new;
+- int res = 0;
+-
+- mutex_lock(&flash->lock);
+- /* Wait until finished previous command */
+- if (wait_till_ready(flash)) {
+- res = 1;
+- goto err;
+- }
+-
+- status_old = read_sr(flash);
+-
+- if (offset < flash->mtd.size-(flash->mtd.size/2))
+- status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
+- else if (offset < flash->mtd.size-(flash->mtd.size/4))
+- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
+- else if (offset < flash->mtd.size-(flash->mtd.size/8))
+- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
+- else if (offset < flash->mtd.size-(flash->mtd.size/16))
+- status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
+- else if (offset < flash->mtd.size-(flash->mtd.size/32))
+- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
+- else if (offset < flash->mtd.size-(flash->mtd.size/64))
+- status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
+- else
+- status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
+-
+- /* Only modify protection if it will not unlock other areas */
+- if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
+- (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
+- write_enable(flash);
+- if (write_sr(flash, status_new) < 0) {
+- res = 1;
+- goto err;
+- }
+- }
+-
+-err: mutex_unlock(&flash->lock);
+- return res;
+-}
+-
+-static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+-{
+- struct m25p *flash = mtd_to_m25p(mtd);
+- uint32_t offset = ofs;
+- uint8_t status_old, status_new;
+- int res = 0;
+-
+- mutex_lock(&flash->lock);
+- /* Wait until finished previous command */
+- if (wait_till_ready(flash)) {
+- res = 1;
+- goto err;
+- }
+-
+- status_old = read_sr(flash);
+-
+- if (offset+len > flash->mtd.size-(flash->mtd.size/64))
+- status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
+- else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
+- status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
+- else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
+- status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
+- else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
+- status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
+- else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
+- status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
+- else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
+- status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
+- else
+- status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
+-
+- /* Only modify protection if it will not lock other areas */
+- if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
+- (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
+- write_enable(flash);
+- if (write_sr(flash, status_new) < 0) {
+- res = 1;
+- goto err;
+- }
+- }
+-
+-err: mutex_unlock(&flash->lock);
+- return res;
+-}
+-
+-/****************************************************************************/
+-
+-/*
+- * SPI device driver setup and teardown
+- */
++ return ret;
+
+-struct flash_info {
+- /* JEDEC id zero means "no ID" (most older chips); otherwise it has
+- * a high byte of zero plus three data bytes: the manufacturer id,
+- * then a two byte device id.
+- */
+- u32 jedec_id;
+- u16 ext_id;
+-
+- /* The size listed here is what works with OPCODE_SE, which isn't
+- * necessarily called a "sector" by the vendor.
+- */
+- unsigned sector_size;
+- u16 n_sectors;
+-
+- u16 page_size;
+- u16 addr_width;
+-
+- u16 flags;
+-#define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
+-#define M25P_NO_ERASE 0x02 /* No erase command needed */
+-#define SST_WRITE 0x04 /* use SST byte programming */
+-#define M25P_NO_FR 0x08 /* Can't do fastread */
+-#define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
+-#define M25P80_QUAD_READ 0x20 /* Flash supports Quad Read */
+-};
++ /* Set up command buffer. */
++ flash->command[0] = nor->erase_opcode;
++ m25p_addr2cmd(nor, offset, flash->command);
+
+-#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+- ((kernel_ulong_t)&(struct flash_info) { \
+- .jedec_id = (_jedec_id), \
+- .ext_id = (_ext_id), \
+- .sector_size = (_sector_size), \
+- .n_sectors = (_n_sectors), \
+- .page_size = 256, \
+- .flags = (_flags), \
+- })
+-
+-#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
+- ((kernel_ulong_t)&(struct flash_info) { \
+- .sector_size = (_sector_size), \
+- .n_sectors = (_n_sectors), \
+- .page_size = (_page_size), \
+- .addr_width = (_addr_width), \
+- .flags = (_flags), \
+- })
+-
+-/* NOTE: double check command sets and memory organization when you add
+- * more flash chips. This current list focusses on newer chips, which
+- * have been converging on command sets which including JEDEC ID.
+- */
+-static const struct spi_device_id m25p_ids[] = {
+- /* Atmel -- some are (confusingly) marketed as "DataFlash" */
+- { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
+- { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
+-
+- { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
+- { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
+- { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
+-
+- { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
+- { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
+- { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
+- { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
+-
+- { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
+-
+- /* EON -- en25xxx */
+- { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
+- { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
+- { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
+- { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
+- { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
+- { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
+-
+- /* ESMT */
+- { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
+-
+- /* Everspin */
+- { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
+- { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
+-
+- /* GigaDevice */
+- { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
+- { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
+-
+- /* Intel/Numonyx -- xxxs33b */
+- { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
+- { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
+- { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
+-
+- /* Macronix */
+- { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
+- { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
+- { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
+- { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
+- { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
+- { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
+- { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
+- { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
+- { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
+- { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
+- { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
+- { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, M25P80_QUAD_READ) },
+-
+- /* Micron */
+- { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
+- { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
+- { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
+- { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
+- { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
+-
+- /* PMC */
+- { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
+- { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
+- { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
+-
+- /* Spansion -- single (large) sector size only, at least
+- * for the chips listed here (without boot sectors).
+- */
+- { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
+- { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
+- { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
+- { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, M25P80_QUAD_READ) },
+- { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, M25P80_QUAD_READ) },
+- { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
+- { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
+- { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
+- { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
+- { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
+- { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
+- { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
+- { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
+- { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
+- { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
+- { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
+- { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
+-
+- /* SST -- large erase sizes are "overlays", "sectors" are 4K */
+- { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
+- { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
+- { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
+- { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
+- { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
+- { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
+- { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
+- { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
+- { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
+-
+- /* ST Microelectronics -- newer production may have feature updates */
+- { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
+- { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
+- { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
+- { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
+- { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
+- { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
+- { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
+- { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
+- { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
+- { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
+-
+- { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
+- { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
+- { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
+- { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
+- { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
+- { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
+- { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
+- { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
+- { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
+-
+- { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
+- { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
+- { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
+-
+- { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
+- { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
+- { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
+-
+- { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
+- { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
+- { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
+- { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
+- { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
+-
+- /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
+- { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
+- { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
+- { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
+- { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
+- { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
+- { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
+- { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
+- { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
+- { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
+- { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
+- { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
+- { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
+- { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
+- { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
+- { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
+-
+- /* Catalyst / On Semiconductor -- non-JEDEC */
+- { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) },
+- { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) },
+- { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
+- { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
+- { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) },
+- { },
+-};
+-MODULE_DEVICE_TABLE(spi, m25p_ids);
++ spi_write(flash->spi, flash->command, m25p_cmdsz(nor));
+
+-static const struct spi_device_id *jedec_probe(struct spi_device *spi)
+-{
+- int tmp;
+- u8 code = OPCODE_RDID;
+- u8 id[5];
+- u32 jedec;
+- u16 ext_jedec;
+- struct flash_info *info;
+-
+- /* JEDEC also defines an optional "extended device information"
+- * string for after vendor-specific data, after the three bytes
+- * we use here. Supporting some chips might require using it.
+- */
+- tmp = spi_write_then_read(spi, &code, 1, id, 5);
+- if (tmp < 0) {
+- pr_debug("%s: error %d reading JEDEC ID\n",
+- dev_name(&spi->dev), tmp);
+- return ERR_PTR(tmp);
+- }
+- jedec = id[0];
+- jedec = jedec << 8;
+- jedec |= id[1];
+- jedec = jedec << 8;
+- jedec |= id[2];
+-
+- ext_jedec = id[3] << 8 | id[4];
+-
+- for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
+- info = (void *)m25p_ids[tmp].driver_data;
+- if (info->jedec_id == jedec) {
+- if (info->ext_id != 0 && info->ext_id != ext_jedec)
+- continue;
+- return &m25p_ids[tmp];
+- }
+- }
+- dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
+- return ERR_PTR(-ENODEV);
++ return 0;
+ }
+
+-
+ /*
+ * board specific setup should have ensured the SPI clock used here
+ * matches what the READ command supports, at least until this driver
+@@ -1089,223 +194,46 @@
+ */
+ static int m25p_probe(struct spi_device *spi)
+ {
+- const struct spi_device_id *id = spi_get_device_id(spi);
+- struct flash_platform_data *data;
+- struct m25p *flash;
+- struct flash_info *info;
+- unsigned i;
+ struct mtd_part_parser_data ppdata;
+- struct device_node *np = spi->dev.of_node;
++ struct flash_platform_data *data;
++ struct m25p *flash;
++ struct spi_nor *nor;
++ enum read_mode mode = SPI_NOR_NORMAL;
+ int ret;
+
+- /* Platform data helps sort out which chip type we have, as
+- * well as how this board partitions it. If we don't have
+- * a chip ID, try the JEDEC id commands; they'll work for most
+- * newer chips, even if we don't recognize the particular chip.
+- */
+- data = dev_get_platdata(&spi->dev);
+- if (data && data->type) {
+- const struct spi_device_id *plat_id;
+-
+- for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
+- plat_id = &m25p_ids[i];
+- if (strcmp(data->type, plat_id->name))
+- continue;
+- break;
+- }
+-
+- if (i < ARRAY_SIZE(m25p_ids) - 1)
+- id = plat_id;
+- else
+- dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
+- }
+-
+- info = (void *)id->driver_data;
+-
+- if (info->jedec_id) {
+- const struct spi_device_id *jid;
+-
+- jid = jedec_probe(spi);
+- if (IS_ERR(jid)) {
+- return PTR_ERR(jid);
+- } else if (jid != id) {
+- /*
+- * JEDEC knows better, so overwrite platform ID. We
+- * can't trust partitions any longer, but we'll let
+- * mtd apply them anyway, since some partitions may be
+- * marked read-only, and we don't want to lose that
+- * information, even if it's not 100% accurate.
+- */
+- dev_warn(&spi->dev, "found %s, expected %s\n",
+- jid->name, id->name);
+- id = jid;
+- info = (void *)jid->driver_data;
+- }
+- }
+-
+ flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
+ if (!flash)
+ return -ENOMEM;
+
+- flash->command = devm_kzalloc(&spi->dev, MAX_CMD_SIZE, GFP_KERNEL);
+- if (!flash->command)
+- return -ENOMEM;
++ nor = &flash->spi_nor;
+
+- flash->spi = spi;
+- mutex_init(&flash->lock);
+- spi_set_drvdata(spi, flash);
+-
+- /*
+- * Atmel, SST and Intel/Numonyx serial flash tend to power
+- * up with the software protection bits set
+- */
+-
+- if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
+- JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
+- JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
+- write_enable(flash);
+- write_sr(flash, 0);
+- }
++ /* install the hooks */
++ nor->read = m25p80_read;
++ nor->write = m25p80_write;
++ nor->erase = m25p80_erase;
++ nor->write_reg = m25p80_write_reg;
++ nor->read_reg = m25p80_read_reg;
++
++ nor->dev = &spi->dev;
++ nor->np = spi->dev.of_node;
++ nor->mtd = &flash->mtd;
++ nor->priv = flash;
+
+- if (data && data->name)
+- flash->mtd.name = data->name;
+- else
+- flash->mtd.name = dev_name(&spi->dev);
+-
+- flash->mtd.type = MTD_NORFLASH;
+- flash->mtd.writesize = 1;
+- flash->mtd.flags = MTD_CAP_NORFLASH;
+- flash->mtd.size = info->sector_size * info->n_sectors;
+- flash->mtd._erase = m25p80_erase;
+- flash->mtd._read = m25p80_read;
+-
+- /* flash protection support for STmicro chips */
+- if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
+- flash->mtd._lock = m25p80_lock;
+- flash->mtd._unlock = m25p80_unlock;
+- }
+-
+- /* sst flash chips use AAI word program */
+- if (info->flags & SST_WRITE)
+- flash->mtd._write = sst_write;
+- else
+- flash->mtd._write = m25p80_write;
+-
+- /* prefer "small sector" erase if possible */
+- if (info->flags & SECT_4K) {
+- flash->erase_opcode = OPCODE_BE_4K;
+- flash->mtd.erasesize = 4096;
+- } else if (info->flags & SECT_4K_PMC) {
+- flash->erase_opcode = OPCODE_BE_4K_PMC;
+- flash->mtd.erasesize = 4096;
+- } else {
+- flash->erase_opcode = OPCODE_SE;
+- flash->mtd.erasesize = info->sector_size;
+- }
++ spi_set_drvdata(spi, flash);
++ flash->mtd.priv = nor;
++ flash->spi = spi;
+
+- if (info->flags & M25P_NO_ERASE)
+- flash->mtd.flags |= MTD_NO_ERASE;
++ if (spi->mode & SPI_RX_QUAD)
++ mode = SPI_NOR_QUAD;
++ else if (spi->mode & SPI_RX_DUAL)
++ mode = SPI_NOR_DUAL;
++ ret = spi_nor_scan(nor, spi_get_device_id(spi), mode);
++ if (ret)
++ return ret;
+
++ data = dev_get_platdata(&spi->dev);
+ ppdata.of_node = spi->dev.of_node;
+- flash->mtd.dev.parent = &spi->dev;
+- flash->page_size = info->page_size;
+- flash->mtd.writebufsize = flash->page_size;
+-
+- if (np) {
+- /* If we were instantiated by DT, use it */
+- if (of_property_read_bool(np, "m25p,fast-read"))
+- flash->flash_read = M25P80_FAST;
+- else
+- flash->flash_read = M25P80_NORMAL;
+- } else {
+- /* If we weren't instantiated by DT, default to fast-read */
+- flash->flash_read = M25P80_FAST;
+- }
+-
+- /* Some devices cannot do fast-read, no matter what DT tells us */
+- if (info->flags & M25P_NO_FR)
+- flash->flash_read = M25P80_NORMAL;
+-
+- /* Quad-read mode takes precedence over fast/normal */
+- if (spi->mode & SPI_RX_QUAD && info->flags & M25P80_QUAD_READ) {
+- ret = set_quad_mode(flash, info->jedec_id);
+- if (ret) {
+- dev_err(&flash->spi->dev, "quad mode not supported\n");
+- return ret;
+- }
+- flash->flash_read = M25P80_QUAD;
+- }
+-
+- /* Default commands */
+- switch (flash->flash_read) {
+- case M25P80_QUAD:
+- flash->read_opcode = OPCODE_QUAD_READ;
+- break;
+- case M25P80_FAST:
+- flash->read_opcode = OPCODE_FAST_READ;
+- break;
+- case M25P80_NORMAL:
+- flash->read_opcode = OPCODE_NORM_READ;
+- break;
+- default:
+- dev_err(&flash->spi->dev, "No Read opcode defined\n");
+- return -EINVAL;
+- }
+-
+- flash->program_opcode = OPCODE_PP;
+-
+- if (info->addr_width)
+- flash->addr_width = info->addr_width;
+- else if (flash->mtd.size > 0x1000000) {
+- /* enable 4-byte addressing if the device exceeds 16MiB */
+- flash->addr_width = 4;
+- if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
+- /* Dedicated 4-byte command set */
+- switch (flash->flash_read) {
+- case M25P80_QUAD:
+- flash->read_opcode = OPCODE_QUAD_READ_4B;
+- break;
+- case M25P80_FAST:
+- flash->read_opcode = OPCODE_FAST_READ_4B;
+- break;
+- case M25P80_NORMAL:
+- flash->read_opcode = OPCODE_NORM_READ_4B;
+- break;
+- }
+- flash->program_opcode = OPCODE_PP_4B;
+- /* No small sector erase for 4-byte command set */
+- flash->erase_opcode = OPCODE_SE_4B;
+- flash->mtd.erasesize = info->sector_size;
+- } else
+- set_4byte(flash, info->jedec_id, 1);
+- } else {
+- flash->addr_width = 3;
+- }
+-
+- dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
+- (long long)flash->mtd.size >> 10);
+
+- pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
+- ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
+- flash->mtd.name,
+- (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
+- flash->mtd.erasesize, flash->mtd.erasesize / 1024,
+- flash->mtd.numeraseregions);
+-
+- if (flash->mtd.numeraseregions)
+- for (i = 0; i < flash->mtd.numeraseregions; i++)
+- pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
+- ".erasesize = 0x%.8x (%uKiB), "
+- ".numblocks = %d }\n",
+- i, (long long)flash->mtd.eraseregions[i].offset,
+- flash->mtd.eraseregions[i].erasesize,
+- flash->mtd.eraseregions[i].erasesize / 1024,
+- flash->mtd.eraseregions[i].numblocks);
+-
+-
+- /* partitions should match sector boundaries; and it may be good to
+- * use readonly partitions for writeprotected sectors (BP2..BP0).
+- */
+ return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
+ data ? data->parts : NULL,
+ data ? data->nr_parts : 0);
+@@ -1326,7 +254,7 @@
+ .name = "m25p80",
+ .owner = THIS_MODULE,
+ },
+- .id_table = m25p_ids,
++ .id_table = spi_nor_ids,
+ .probe = m25p_probe,
+ .remove = m25p_remove,
+
+diff -Nur linux-3.14.72.orig/drivers/mtd/Kconfig linux-3.14.72/drivers/mtd/Kconfig
+--- linux-3.14.72.orig/drivers/mtd/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/Kconfig 2016-06-19 22:11:55.205146568 +0200
+@@ -321,6 +321,8 @@
+
+ source "drivers/mtd/lpddr/Kconfig"
+
++source "drivers/mtd/spi-nor/Kconfig"
++
+ source "drivers/mtd/ubi/Kconfig"
+
+ endif # MTD
+diff -Nur linux-3.14.72.orig/drivers/mtd/Makefile linux-3.14.72/drivers/mtd/Makefile
+--- linux-3.14.72.orig/drivers/mtd/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/Makefile 2016-06-19 22:11:55.205146568 +0200
+@@ -30,6 +30,7 @@
+ nftl-objs := nftlcore.o nftlmount.o
+ inftl-objs := inftlcore.o inftlmount.o
+
++obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/
+ obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
+
+ obj-$(CONFIG_MTD_UBI) += ubi/
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/atmel_nand.c linux-3.14.72/drivers/mtd/nand/atmel_nand.c
+--- linux-3.14.72.orig/drivers/mtd/nand/atmel_nand.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/atmel_nand.c 2016-06-19 22:11:55.205146568 +0200
+@@ -1660,8 +1660,8 @@
+ nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
+ }
+
+-static int nfc_make_addr(struct mtd_info *mtd, int column, int page_addr,
+- unsigned int *addr1234, unsigned int *cycle0)
++static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
++ int page_addr, unsigned int *addr1234, unsigned int *cycle0)
+ {
+ struct nand_chip *chip = mtd->priv;
+
+@@ -1675,7 +1675,8 @@
+ *addr1234 = 0;
+
+ if (column != -1) {
+- if (chip->options & NAND_BUSWIDTH_16)
++ if (chip->options & NAND_BUSWIDTH_16 &&
++ !nand_opcode_8bits(command))
+ column >>= 1;
+ addr_bytes[acycle++] = column & 0xff;
+ if (mtd->writesize > 512)
+@@ -1788,8 +1789,8 @@
+ }
+
+ if (do_addr)
+- acycle = nfc_make_addr(mtd, column, page_addr, &addr1234,
+- &cycle0);
++ acycle = nfc_make_addr(mtd, command, column, page_addr,
++ &addr1234, &cycle0);
+
+ nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
+ nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/au1550nd.c linux-3.14.72/drivers/mtd/nand/au1550nd.c
+--- linux-3.14.72.orig/drivers/mtd/nand/au1550nd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/au1550nd.c 2016-06-19 22:11:55.205146568 +0200
+@@ -308,7 +308,8 @@
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+- if (this->options & NAND_BUSWIDTH_16)
++ if (this->options & NAND_BUSWIDTH_16 &&
++ !nand_opcode_8bits(command))
+ column >>= 1;
+ ctx->write_byte(mtd, column);
+ }
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/cafe_nand.c linux-3.14.72/drivers/mtd/nand/cafe_nand.c
+--- linux-3.14.72.orig/drivers/mtd/nand/cafe_nand.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/cafe_nand.c 2016-06-19 22:11:55.205146568 +0200
+@@ -627,6 +627,8 @@
+ struct cafe_priv *cafe;
+ uint32_t ctrl;
+ int err = 0;
++ int old_dma;
++ struct nand_buffers *nbuf;
+
+ /* Very old versions shared the same PCI ident for all three
+ functions on the chip. Verify the class too... */
+@@ -655,13 +657,6 @@
+ err = -ENOMEM;
+ goto out_free_mtd;
+ }
+- cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
+- &cafe->dmaaddr, GFP_KERNEL);
+- if (!cafe->dmabuf) {
+- err = -ENOMEM;
+- goto out_ior;
+- }
+- cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
+
+ cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
+ if (!cafe->rs) {
+@@ -721,7 +716,7 @@
+ "CAFE NAND", mtd);
+ if (err) {
+ dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
+- goto out_free_dma;
++ goto out_ior;
+ }
+
+ /* Disable master reset, enable NAND clock */
+@@ -735,6 +730,32 @@
+ cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
+ cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
+
++ /* Enable NAND IRQ in global IRQ mask register */
++ cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
++ cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
++ cafe_readl(cafe, GLOBAL_CTRL),
++ cafe_readl(cafe, GLOBAL_IRQ_MASK));
++
++ /* Do not use the DMA for the nand_scan_ident() */
++ old_dma = usedma;
++ usedma = 0;
++
++ /* Scan to find existence of the device */
++ if (nand_scan_ident(mtd, 2, NULL)) {
++ err = -ENXIO;
++ goto out_irq;
++ }
++
++ cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev,
++ 2112 + sizeof(struct nand_buffers) +
++ mtd->writesize + mtd->oobsize,
++ &cafe->dmaaddr, GFP_KERNEL);
++ if (!cafe->dmabuf) {
++ err = -ENOMEM;
++ goto out_irq;
++ }
++ cafe->nand.buffers = nbuf = (void *)cafe->dmabuf + 2112;
++
+ /* Set up DMA address */
+ cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
+ if (sizeof(cafe->dmaaddr) > 4)
+@@ -746,16 +767,13 @@
+ cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
+ cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
+
+- /* Enable NAND IRQ in global IRQ mask register */
+- cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
+- cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
+- cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
++ /* this driver does not need the @ecccalc and @ecccode */
++ nbuf->ecccalc = NULL;
++ nbuf->ecccode = NULL;
++ nbuf->databuf = (uint8_t *)(nbuf + 1);
+
+- /* Scan to find existence of the device */
+- if (nand_scan_ident(mtd, 2, NULL)) {
+- err = -ENXIO;
+- goto out_irq;
+- }
++ /* Restore the DMA flag */
++ usedma = old_dma;
+
+ cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
+ if (mtd->writesize == 2048)
+@@ -773,7 +791,7 @@
+ } else {
+ printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
+ mtd->writesize);
+- goto out_irq;
++ goto out_free_dma;
+ }
+ cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
+ cafe->nand.ecc.size = mtd->writesize;
+@@ -790,7 +808,7 @@
+
+ err = nand_scan_tail(mtd);
+ if (err)
+- goto out_irq;
++ goto out_free_dma;
+
+ pci_set_drvdata(pdev, mtd);
+
+@@ -799,12 +817,15 @@
+
+ goto out;
+
++ out_free_dma:
++ dma_free_coherent(&cafe->pdev->dev,
++ 2112 + sizeof(struct nand_buffers) +
++ mtd->writesize + mtd->oobsize,
++ cafe->dmabuf, cafe->dmaaddr);
+ out_irq:
+ /* Disable NAND IRQ in global IRQ mask register */
+ cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
+ free_irq(pdev->irq, mtd);
+- out_free_dma:
+- dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
+ out_ior:
+ pci_iounmap(pdev, cafe->mmio);
+ out_free_mtd:
+@@ -824,7 +845,10 @@
+ nand_release(mtd);
+ free_rs(cafe->rs);
+ pci_iounmap(pdev, cafe->mmio);
+- dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
++ dma_free_coherent(&cafe->pdev->dev,
++ 2112 + sizeof(struct nand_buffers) +
++ mtd->writesize + mtd->oobsize,
++ cafe->dmabuf, cafe->dmaaddr);
+ kfree(mtd);
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/denali.c linux-3.14.72/drivers/mtd/nand/denali.c
+--- linux-3.14.72.orig/drivers/mtd/nand/denali.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/denali.c 2016-06-19 22:11:55.205146568 +0200
+@@ -1233,7 +1233,7 @@
+ return status;
+ }
+
+-static void denali_erase(struct mtd_info *mtd, int page)
++static int denali_erase(struct mtd_info *mtd, int page)
+ {
+ struct denali_nand_info *denali = mtd_to_denali(mtd);
+
+@@ -1250,8 +1250,7 @@
+ irq_status = wait_for_irq(denali, INTR_STATUS__ERASE_COMP |
+ INTR_STATUS__ERASE_FAIL);
+
+- denali->status = (irq_status & INTR_STATUS__ERASE_FAIL) ?
+- NAND_STATUS_FAIL : PASS;
++ return (irq_status & INTR_STATUS__ERASE_FAIL) ? NAND_STATUS_FAIL : PASS;
+ }
+
+ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
+@@ -1584,7 +1583,7 @@
+ denali->nand.ecc.write_page_raw = denali_write_page_raw;
+ denali->nand.ecc.read_oob = denali_read_oob;
+ denali->nand.ecc.write_oob = denali_write_oob;
+- denali->nand.erase_cmd = denali_erase;
++ denali->nand.erase = denali_erase;
+
+ if (nand_scan_tail(&denali->mtd)) {
+ ret = -ENXIO;
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/diskonchip.c linux-3.14.72/drivers/mtd/nand/diskonchip.c
+--- linux-3.14.72.orig/drivers/mtd/nand/diskonchip.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/diskonchip.c 2016-06-19 22:11:55.205146568 +0200
+@@ -698,7 +698,8 @@
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+- if (this->options & NAND_BUSWIDTH_16)
++ if (this->options & NAND_BUSWIDTH_16 &&
++ !nand_opcode_8bits(command))
+ column >>= 1;
+ WriteDOC(column, docptr, Mplus_FlashAddress);
+ }
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/docg4.c linux-3.14.72/drivers/mtd/nand/docg4.c
+--- linux-3.14.72.orig/drivers/mtd/nand/docg4.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/docg4.c 2016-06-19 22:11:55.205146568 +0200
+@@ -872,7 +872,7 @@
+ return 0;
+ }
+
+-static void docg4_erase_block(struct mtd_info *mtd, int page)
++static int docg4_erase_block(struct mtd_info *mtd, int page)
+ {
+ struct nand_chip *nand = mtd->priv;
+ struct docg4_priv *doc = nand->priv;
+@@ -916,6 +916,8 @@
+ write_nop(docptr);
+ poll_status(doc);
+ write_nop(docptr);
++
++ return nand->waitfunc(mtd, nand);
+ }
+
+ static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
+@@ -1236,7 +1238,7 @@
+ nand->block_markbad = docg4_block_markbad;
+ nand->read_buf = docg4_read_buf;
+ nand->write_buf = docg4_write_buf16;
+- nand->erase_cmd = docg4_erase_block;
++ nand->erase = docg4_erase_block;
+ nand->ecc.read_page = docg4_read_page;
+ nand->ecc.write_page = docg4_write_page;
+ nand->ecc.read_page_raw = docg4_read_page_raw;
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/bch-regs.h linux-3.14.72/drivers/mtd/nand/gpmi-nand/bch-regs.h
+--- linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/bch-regs.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/gpmi-nand/bch-regs.h 2016-06-19 22:11:55.205146568 +0200
+@@ -54,7 +54,7 @@
+ #define MX6Q_BP_BCH_FLASH0LAYOUT0_ECC0 11
+ #define MX6Q_BM_BCH_FLASH0LAYOUT0_ECC0 (0x1f << MX6Q_BP_BCH_FLASH0LAYOUT0_ECC0)
+ #define BF_BCH_FLASH0LAYOUT0_ECC0(v, x) \
+- (GPMI_IS_MX6Q(x) \
++ (GPMI_IS_MX6(x) \
+ ? (((v) << MX6Q_BP_BCH_FLASH0LAYOUT0_ECC0) \
+ & MX6Q_BM_BCH_FLASH0LAYOUT0_ECC0) \
+ : (((v) << BP_BCH_FLASH0LAYOUT0_ECC0) \
+@@ -65,7 +65,7 @@
+ #define MX6Q_BM_BCH_FLASH0LAYOUT0_GF_13_14 \
+ (0x1 << MX6Q_BP_BCH_FLASH0LAYOUT0_GF_13_14)
+ #define BF_BCH_FLASH0LAYOUT0_GF(v, x) \
+- ((GPMI_IS_MX6Q(x) && ((v) == 14)) \
++ ((GPMI_IS_MX6(x) && ((v) == 14)) \
+ ? (((1) << MX6Q_BP_BCH_FLASH0LAYOUT0_GF_13_14) \
+ & MX6Q_BM_BCH_FLASH0LAYOUT0_GF_13_14) \
+ : 0 \
+@@ -77,7 +77,7 @@
+ #define MX6Q_BM_BCH_FLASH0LAYOUT0_DATA0_SIZE \
+ (0x3ff << BP_BCH_FLASH0LAYOUT0_DATA0_SIZE)
+ #define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v, x) \
+- (GPMI_IS_MX6Q(x) \
++ (GPMI_IS_MX6(x) \
+ ? (((v) >> 2) & MX6Q_BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) \
+ : ((v) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) \
+ )
+@@ -96,7 +96,7 @@
+ #define MX6Q_BP_BCH_FLASH0LAYOUT1_ECCN 11
+ #define MX6Q_BM_BCH_FLASH0LAYOUT1_ECCN (0x1f << MX6Q_BP_BCH_FLASH0LAYOUT1_ECCN)
+ #define BF_BCH_FLASH0LAYOUT1_ECCN(v, x) \
+- (GPMI_IS_MX6Q(x) \
++ (GPMI_IS_MX6(x) \
+ ? (((v) << MX6Q_BP_BCH_FLASH0LAYOUT1_ECCN) \
+ & MX6Q_BM_BCH_FLASH0LAYOUT1_ECCN) \
+ : (((v) << BP_BCH_FLASH0LAYOUT1_ECCN) \
+@@ -107,7 +107,7 @@
+ #define MX6Q_BM_BCH_FLASH0LAYOUT1_GF_13_14 \
+ (0x1 << MX6Q_BP_BCH_FLASH0LAYOUT1_GF_13_14)
+ #define BF_BCH_FLASH0LAYOUT1_GF(v, x) \
+- ((GPMI_IS_MX6Q(x) && ((v) == 14)) \
++ ((GPMI_IS_MX6(x) && ((v) == 14)) \
+ ? (((1) << MX6Q_BP_BCH_FLASH0LAYOUT1_GF_13_14) \
+ & MX6Q_BM_BCH_FLASH0LAYOUT1_GF_13_14) \
+ : 0 \
+@@ -119,7 +119,7 @@
+ #define MX6Q_BM_BCH_FLASH0LAYOUT1_DATAN_SIZE \
+ (0x3ff << BP_BCH_FLASH0LAYOUT1_DATAN_SIZE)
+ #define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v, x) \
+- (GPMI_IS_MX6Q(x) \
++ (GPMI_IS_MX6(x) \
+ ? (((v) >> 2) & MX6Q_BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) \
+ : ((v) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) \
+ )
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/gpmi-lib.c linux-3.14.72/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+--- linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/gpmi-lib.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/gpmi-nand/gpmi-lib.c 2016-06-19 22:11:55.205146568 +0200
+@@ -861,7 +861,7 @@
+ struct resources *r = &this->resources;
+ unsigned long rate = clk_get_rate(r->clock[0]);
+ int mode = this->timing_mode;
+- int dll_threshold = 16; /* in ns */
++ int dll_threshold = this->devdata->max_chain_delay;
+ unsigned long delay;
+ unsigned long clk_period;
+ int t_rea;
+@@ -886,9 +886,6 @@
+ /* [3] for GPMI_HW_GPMI_CTRL1 */
+ hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
+
+- if (GPMI_IS_MX6Q(this))
+- dll_threshold = 12;
+-
+ /*
+ * Enlarge 10 times for the numerator and denominator in {3}.
+ * This make us to get more accurate result.
+@@ -974,7 +971,7 @@
+ struct nand_chip *chip = &this->nand;
+
+ /* Enable the asynchronous EDO feature. */
+- if (GPMI_IS_MX6Q(this) && chip->onfi_version) {
++ if (GPMI_IS_MX6(this) && chip->onfi_version) {
+ int mode = onfi_get_async_timing_mode(chip);
+
+ /* We only support the timing mode 4 and mode 5. */
+@@ -1096,12 +1093,12 @@
+ if (GPMI_IS_MX23(this)) {
+ mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
+ reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
+- } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6Q(this)) {
++ } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6(this)) {
+ /*
+ * In the imx6, all the ready/busy pins are bound
+ * together. So we only need to check chip 0.
+ */
+- if (GPMI_IS_MX6Q(this))
++ if (GPMI_IS_MX6(this))
+ chip = 0;
+
+ /* MX28 shares the same R/B register as MX6Q. */
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.c linux-3.14.72/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+--- linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/gpmi-nand/gpmi-nand.c 2016-06-19 22:11:55.205146568 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Freescale GPMI NAND Flash Driver
+ *
+- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2008 Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+@@ -27,6 +27,7 @@
+ #include <linux/of_device.h>
+ #include <linux/of_mtd.h>
+ #include "gpmi-nand.h"
++#include "bch-regs.h"
+
+ /* Resource names for the GPMI NAND driver. */
+ #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
+@@ -52,6 +53,30 @@
+ .oobfree = { {.offset = 0, .length = 0} }
+ };
+
++static const struct gpmi_devdata gpmi_devdata_imx23 = {
++ .type = IS_MX23,
++ .bch_max_ecc_strength = 20,
++ .max_chain_delay = 16,
++};
++
++static const struct gpmi_devdata gpmi_devdata_imx28 = {
++ .type = IS_MX28,
++ .bch_max_ecc_strength = 20,
++ .max_chain_delay = 16,
++};
++
++static const struct gpmi_devdata gpmi_devdata_imx6q = {
++ .type = IS_MX6Q,
++ .bch_max_ecc_strength = 40,
++ .max_chain_delay = 12,
++};
++
++static const struct gpmi_devdata gpmi_devdata_imx6sx = {
++ .type = IS_MX6SX,
++ .bch_max_ecc_strength = 62,
++ .max_chain_delay = 12,
++};
++
+ static irqreturn_t bch_irq(int irq, void *cookie)
+ {
+ struct gpmi_nand_data *this = cookie;
+@@ -101,14 +126,8 @@
+ /* The mx23/mx28 only support the GF13. */
+ if (geo->gf_len == 14)
+ return false;
+-
+- if (geo->ecc_strength > MXS_ECC_STRENGTH_MAX)
+- return false;
+- } else if (GPMI_IS_MX6Q(this)) {
+- if (geo->ecc_strength > MX6_ECC_STRENGTH_MAX)
+- return false;
+ }
+- return true;
++ return geo->ecc_strength <= this->devdata->bch_max_ecc_strength;
+ }
+
+ /*
+@@ -117,7 +136,7 @@
+ *
+ * We may have available oob space in this case.
+ */
+-static bool set_geometry_by_ecc_info(struct gpmi_nand_data *this)
++static int set_geometry_by_ecc_info(struct gpmi_nand_data *this)
+ {
+ struct bch_geometry *geo = &this->bch_geometry;
+ struct mtd_info *mtd = &this->mtd;
+@@ -126,7 +145,7 @@
+ unsigned int block_mark_bit_offset;
+
+ if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
+- return false;
++ return -EINVAL;
+
+ switch (chip->ecc_step_ds) {
+ case SZ_512:
+@@ -139,19 +158,19 @@
+ dev_err(this->dev,
+ "unsupported nand chip. ecc bits : %d, ecc size : %d\n",
+ chip->ecc_strength_ds, chip->ecc_step_ds);
+- return false;
++ return -EINVAL;
+ }
+ geo->ecc_chunk_size = chip->ecc_step_ds;
+ geo->ecc_strength = round_up(chip->ecc_strength_ds, 2);
+ if (!gpmi_check_ecc(this))
+- return false;
++ return -EINVAL;
+
+ /* Keep the C >= O */
+ if (geo->ecc_chunk_size < mtd->oobsize) {
+ dev_err(this->dev,
+ "unsupported nand chip. ecc size: %d, oob size : %d\n",
+ chip->ecc_step_ds, mtd->oobsize);
+- return false;
++ return -EINVAL;
+ }
+
+ /* The default value, see comment in the legacy_set_geometry(). */
+@@ -223,7 +242,7 @@
+ + ALIGN(geo->ecc_chunk_count, 4);
+
+ if (!this->swap_block_mark)
+- return true;
++ return 0;
+
+ /* For bit swap. */
+ block_mark_bit_offset = mtd->writesize * 8 -
+@@ -232,7 +251,7 @@
+
+ geo->block_mark_byte_offset = block_mark_bit_offset / 8;
+ geo->block_mark_bit_offset = block_mark_bit_offset % 8;
+- return true;
++ return 0;
+ }
+
+ static int legacy_set_geometry(struct gpmi_nand_data *this)
+@@ -266,11 +285,11 @@
+ geo->ecc_strength = get_ecc_strength(this);
+ if (!gpmi_check_ecc(this)) {
+ dev_err(this->dev,
+- "We can not support this nand chip."
+- " Its required ecc strength(%d) is beyond our"
+- " capability(%d).\n", geo->ecc_strength,
+- (GPMI_IS_MX6Q(this) ? MX6_ECC_STRENGTH_MAX
+- : MXS_ECC_STRENGTH_MAX));
++ " Default ecc strength(%d) is beyond our"
++ " capability(%d)."
++ " Try to use minimum required ecc strength.\n"
++ , geo->ecc_strength,
++ this->devdata->bch_max_ecc_strength);
+ return -EINVAL;
+ }
+
+@@ -349,10 +368,12 @@
+
+ int common_nfc_set_geometry(struct gpmi_nand_data *this)
+ {
+- if (of_property_read_bool(this->dev->of_node, "fsl,use-minimum-ecc")
+- && set_geometry_by_ecc_info(this))
+- return 0;
+- return legacy_set_geometry(this);
++
++ if ((of_property_read_bool(this->dev->of_node, "fsl,use-minimum-ecc"))
++ || legacy_set_geometry(this))
++ return set_geometry_by_ecc_info(this);
++
++ return 0;
+ }
+
+ struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
+@@ -571,7 +592,7 @@
+ }
+
+ /* Get extra clocks */
+- if (GPMI_IS_MX6Q(this))
++ if (GPMI_IS_MX6(this))
+ extra_clks = extra_clks_for_mx6q;
+ if (!extra_clks)
+ return 0;
+@@ -589,9 +610,9 @@
+ r->clock[i] = clk;
+ }
+
+- if (GPMI_IS_MX6Q(this))
++ if (GPMI_IS_MX6(this))
+ /*
+- * Set the default value for the gpmi clock in mx6q:
++ * Set the default value for the gpmi clock.
+ *
+ * If you want to use the ONFI nand which is in the
+ * Synchronous Mode, you should change the clock as you need.
+@@ -985,7 +1006,7 @@
+ int ret;
+
+ dev_dbg(this->dev, "page number is : %d\n", page);
+- ret = read_page_prepare(this, buf, mtd->writesize,
++ ret = read_page_prepare(this, buf, nfc_geo->payload_size,
+ this->payload_virt, this->payload_phys,
+ nfc_geo->payload_size,
+ &payload_virt, &payload_phys);
+@@ -999,7 +1020,7 @@
+
+ /* go! */
+ ret = gpmi_read_page(this, payload_phys, auxiliary_phys);
+- read_page_end(this, buf, mtd->writesize,
++ read_page_end(this, buf, nfc_geo->payload_size,
+ this->payload_virt, this->payload_phys,
+ nfc_geo->payload_size,
+ payload_virt, payload_phys);
+@@ -1041,7 +1062,7 @@
+ chip->oob_poi[0] = ((uint8_t *) auxiliary_virt)[0];
+ }
+
+- read_page_swap_end(this, buf, mtd->writesize,
++ read_page_swap_end(this, buf, nfc_geo->payload_size,
+ this->payload_virt, this->payload_phys,
+ nfc_geo->payload_size,
+ payload_virt, payload_phys);
+@@ -1049,6 +1070,90 @@
+ return max_bitflips;
+ }
+
++/* Fake a virtual small page for the subpage read */
++static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
++ uint32_t offs, uint32_t len, uint8_t *buf, int page)
++{
++ struct gpmi_nand_data *this = chip->priv;
++ void __iomem *bch_regs = this->resources.bch_regs;
++ struct bch_geometry old_geo = this->bch_geometry;
++ struct bch_geometry *geo = &this->bch_geometry;
++ int size = chip->ecc.size; /* ECC chunk size */
++ int meta, n, page_size;
++ u32 r1_old, r2_old, r1_new, r2_new;
++ unsigned int max_bitflips;
++ int first, last, marker_pos;
++ int ecc_parity_size;
++ int col = 0;
++
++ /* The size of ECC parity */
++ ecc_parity_size = geo->gf_len * geo->ecc_strength / 8;
++
++ /* Align it with the chunk size */
++ first = offs / size;
++ last = (offs + len - 1) / size;
++
++ /*
++ * Find the chunk which contains the Block Marker. If this chunk is
++ * in the range of [first, last], we have to read out the whole page.
++ * Why? since we had swapped the data at the position of Block Marker
++ * to the metadata which is bound with the chunk 0.
++ */
++ marker_pos = geo->block_mark_byte_offset / size;
++ if (last >= marker_pos && first <= marker_pos) {
++ dev_dbg(this->dev, "page:%d, first:%d, last:%d, marker at:%d\n",
++ page, first, last, marker_pos);
++ return gpmi_ecc_read_page(mtd, chip, buf, 0, page);
++ }
++
++ meta = geo->metadata_size;
++ if (first) {
++ col = meta + (size + ecc_parity_size) * first;
++ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
++
++ meta = 0;
++ buf = buf + first * size;
++ }
++
++ /* Save the old environment */
++ r1_old = r1_new = readl(bch_regs + HW_BCH_FLASH0LAYOUT0);
++ r2_old = r2_new = readl(bch_regs + HW_BCH_FLASH0LAYOUT1);
++
++ /* change the BCH registers and bch_geometry{} */
++ n = last - first + 1;
++ page_size = meta + (size + ecc_parity_size) * n;
++
++ r1_new &= ~(BM_BCH_FLASH0LAYOUT0_NBLOCKS |
++ BM_BCH_FLASH0LAYOUT0_META_SIZE);
++ r1_new |= BF_BCH_FLASH0LAYOUT0_NBLOCKS(n - 1)
++ | BF_BCH_FLASH0LAYOUT0_META_SIZE(meta);
++ writel(r1_new, bch_regs + HW_BCH_FLASH0LAYOUT0);
++
++ r2_new &= ~BM_BCH_FLASH0LAYOUT1_PAGE_SIZE;
++ r2_new |= BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size);
++ writel(r2_new, bch_regs + HW_BCH_FLASH0LAYOUT1);
++
++ geo->ecc_chunk_count = n;
++ geo->payload_size = n * size;
++ geo->page_size = page_size;
++ geo->auxiliary_status_offset = ALIGN(meta, 4);
++
++ dev_dbg(this->dev, "page:%d(%d:%d)%d, chunk:(%d:%d), BCH PG size:%d\n",
++ page, offs, len, col, first, n, page_size);
++
++ /* Read the subpage now */
++ this->swap_block_mark = false;
++ max_bitflips = gpmi_ecc_read_page(mtd, chip, buf, 0, page);
++
++ /* Restore */
++ writel(r1_old, bch_regs + HW_BCH_FLASH0LAYOUT0);
++ writel(r2_old, bch_regs + HW_BCH_FLASH0LAYOUT1);
++ this->bch_geometry = old_geo;
++ this->swap_block_mark = true;
++
++ return max_bitflips;
++}
++
+ static int gpmi_ecc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf, int oob_required)
+ {
+@@ -1566,6 +1671,17 @@
+ ecc->layout = &gpmi_hw_ecclayout;
+
+ /*
++ * We only enable the subpage read when:
++ * (1) the chip is imx6, and
++ * (2) the size of the ECC parity is byte aligned.
++ */
++ if (GPMI_IS_MX6(this) &&
++ ((bch_geo->gf_len * bch_geo->ecc_strength) % 8) == 0) {
++ ecc->read_subpage = gpmi_ecc_read_subpage;
++ chip->options |= NAND_SUBPAGE_READ;
++ }
++
++ /*
+ * Can we enable the extra features? such as EDO or Sync mode.
+ *
+ * We do not check the return value now. That's means if we fail in
+@@ -1615,7 +1731,7 @@
+ if (ret)
+ goto err_out;
+
+- ret = nand_scan_ident(mtd, GPMI_IS_MX6Q(this) ? 2 : 1, NULL);
++ ret = nand_scan_ident(mtd, GPMI_IS_MX6(this) ? 2 : 1, NULL);
+ if (ret)
+ goto err_out;
+
+@@ -1644,23 +1760,19 @@
+ return ret;
+ }
+
+-static const struct platform_device_id gpmi_ids[] = {
+- { .name = "imx23-gpmi-nand", .driver_data = IS_MX23, },
+- { .name = "imx28-gpmi-nand", .driver_data = IS_MX28, },
+- { .name = "imx6q-gpmi-nand", .driver_data = IS_MX6Q, },
+- {}
+-};
+-
+ static const struct of_device_id gpmi_nand_id_table[] = {
+ {
+ .compatible = "fsl,imx23-gpmi-nand",
+- .data = (void *)&gpmi_ids[IS_MX23],
++ .data = (void *)&gpmi_devdata_imx23,
+ }, {
+ .compatible = "fsl,imx28-gpmi-nand",
+- .data = (void *)&gpmi_ids[IS_MX28],
++ .data = (void *)&gpmi_devdata_imx28,
+ }, {
+ .compatible = "fsl,imx6q-gpmi-nand",
+- .data = (void *)&gpmi_ids[IS_MX6Q],
++ .data = (void *)&gpmi_devdata_imx6q,
++ }, {
++ .compatible = "fsl,imx6sx-gpmi-nand",
++ .data = (void *)&gpmi_devdata_imx6sx,
+ }, {}
+ };
+ MODULE_DEVICE_TABLE(of, gpmi_nand_id_table);
+@@ -1671,18 +1783,18 @@
+ const struct of_device_id *of_id;
+ int ret;
+
++ this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
++ if (!this)
++ return -ENOMEM;
++
+ of_id = of_match_device(gpmi_nand_id_table, &pdev->dev);
+ if (of_id) {
+- pdev->id_entry = of_id->data;
++ this->devdata = of_id->data;
+ } else {
+ dev_err(&pdev->dev, "Failed to find the right device id.\n");
+ return -ENODEV;
+ }
+
+- this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
+- if (!this)
+- return -ENOMEM;
+-
+ platform_set_drvdata(pdev, this);
+ this->pdev = pdev;
+ this->dev = &pdev->dev;
+@@ -1720,14 +1832,56 @@
+ return 0;
+ }
+
++static int gpmi_pm_suspend(struct device *dev)
++{
++ struct gpmi_nand_data *this = dev_get_drvdata(dev);
++
++ release_dma_channels(this);
++ return 0;
++}
++
++static int gpmi_pm_resume(struct device *dev)
++{
++ struct gpmi_nand_data *this = dev_get_drvdata(dev);
++ int ret;
++
++ ret = acquire_dma_channels(this);
++ if (ret < 0)
++ return ret;
++
++ /* re-init the GPMI registers */
++ this->flags &= ~GPMI_TIMING_INIT_OK;
++ ret = gpmi_init(this);
++ if (ret) {
++ dev_err(this->dev, "Error setting GPMI : %d\n", ret);
++ return ret;
++ }
++
++ /* re-init the BCH registers */
++ ret = bch_set_geometry(this);
++ if (ret) {
++ dev_err(this->dev, "Error setting BCH : %d\n", ret);
++ return ret;
++ }
++
++ /* re-init others */
++ gpmi_extra_init(this);
++
++ return 0;
++}
++
++static const struct dev_pm_ops gpmi_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(gpmi_pm_suspend, gpmi_pm_resume)
++};
++
+ static struct platform_driver gpmi_nand_driver = {
+ .driver = {
+ .name = "gpmi-nand",
++ .pm = &gpmi_pm_ops,
+ .of_match_table = gpmi_nand_id_table,
+ },
+ .probe = gpmi_nand_probe,
+ .remove = gpmi_nand_remove,
+- .id_table = gpmi_ids,
+ };
+ module_platform_driver(gpmi_nand_driver);
+
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.h linux-3.14.72/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+--- linux-3.14.72.orig/drivers/mtd/nand/gpmi-nand/gpmi-nand.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/gpmi-nand/gpmi-nand.h 2016-06-19 22:11:55.205146568 +0200
+@@ -119,11 +119,25 @@
+ int8_t tRHOH_in_ns;
+ };
+
++enum gpmi_type {
++ IS_MX23,
++ IS_MX28,
++ IS_MX6Q,
++ IS_MX6SX
++};
++
++struct gpmi_devdata {
++ enum gpmi_type type;
++ int bch_max_ecc_strength;
++ int max_chain_delay; /* See the async EDO mode */
++};
++
+ struct gpmi_nand_data {
+ /* flags */
+ #define GPMI_ASYNC_EDO_ENABLED (1 << 0)
+ #define GPMI_TIMING_INIT_OK (1 << 1)
+ int flags;
++ const struct gpmi_devdata *devdata;
+
+ /* System Interface */
+ struct device *dev;
+@@ -281,15 +295,11 @@
+ #define STATUS_ERASED 0xff
+ #define STATUS_UNCORRECTABLE 0xfe
+
+-/* BCH's bit correction capability. */
+-#define MXS_ECC_STRENGTH_MAX 20 /* mx23 and mx28 */
+-#define MX6_ECC_STRENGTH_MAX 40
+-
+-/* Use the platform_id to distinguish different Archs. */
+-#define IS_MX23 0x0
+-#define IS_MX28 0x1
+-#define IS_MX6Q 0x2
+-#define GPMI_IS_MX23(x) ((x)->pdev->id_entry->driver_data == IS_MX23)
+-#define GPMI_IS_MX28(x) ((x)->pdev->id_entry->driver_data == IS_MX28)
+-#define GPMI_IS_MX6Q(x) ((x)->pdev->id_entry->driver_data == IS_MX6Q)
++/* Use the devdata to distinguish different Archs. */
++#define GPMI_IS_MX23(x) ((x)->devdata->type == IS_MX23)
++#define GPMI_IS_MX28(x) ((x)->devdata->type == IS_MX28)
++#define GPMI_IS_MX6Q(x) ((x)->devdata->type == IS_MX6Q)
++#define GPMI_IS_MX6SX(x) ((x)->devdata->type == IS_MX6SX)
++
++#define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x))
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/nand_base.c linux-3.14.72/drivers/mtd/nand/nand_base.c
+--- linux-3.14.72.orig/drivers/mtd/nand/nand_base.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/nand_base.c 2016-06-19 22:11:55.209146306 +0200
+@@ -37,6 +37,7 @@
+ #include <linux/err.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
++#include <linux/mm.h>
+ #include <linux/types.h>
+ #include <linux/mtd/mtd.h>
+ #include <linux/mtd/nand.h>
+@@ -589,7 +590,8 @@
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+- if (chip->options & NAND_BUSWIDTH_16)
++ if (chip->options & NAND_BUSWIDTH_16 &&
++ !nand_opcode_8bits(command))
+ column >>= 1;
+ chip->cmd_ctrl(mtd, column, ctrl);
+ ctrl &= ~NAND_CTRL_CHANGE;
+@@ -680,7 +682,8 @@
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+- if (chip->options & NAND_BUSWIDTH_16)
++ if (chip->options & NAND_BUSWIDTH_16 &&
++ !nand_opcode_8bits(command))
+ column >>= 1;
+ chip->cmd_ctrl(mtd, column, ctrl);
+ ctrl &= ~NAND_CTRL_CHANGE;
+@@ -1160,9 +1163,11 @@
+ * @data_offs: offset of requested data within the page
+ * @readlen: data length
+ * @bufpoi: buffer to store read data
++ * @page: page number to read
+ */
+ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
+- uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
++ uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
++ int page)
+ {
+ int start_step, end_step, num_steps;
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+@@ -1170,13 +1175,14 @@
+ int data_col_addr, i, gaps = 0;
+ int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
+ int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
+- int index = 0;
++ int index;
+ unsigned int max_bitflips = 0;
+
+ /* Column address within the page aligned to ECC size (256bytes) */
+ start_step = data_offs / chip->ecc.size;
+ end_step = (data_offs + readlen - 1) / chip->ecc.size;
+ num_steps = end_step - start_step + 1;
++ index = start_step * chip->ecc.bytes;
+
+ /* Data size aligned to ECC ecc.size */
+ datafrag_len = num_steps * chip->ecc.size;
+@@ -1199,8 +1205,7 @@
+ * ecc.pos. Let's make sure that there are no gaps in ECC positions.
+ */
+ for (i = 0; i < eccfrag_len - 1; i++) {
+- if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
+- eccpos[i + start_step * chip->ecc.bytes + 1]) {
++ if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
+ gaps = 1;
+ break;
+ }
+@@ -1213,8 +1218,6 @@
+ * Send the command to read the particular ECC bytes take care
+ * about buswidth alignment in read_buf.
+ */
+- index = start_step * chip->ecc.bytes;
+-
+ aligned_pos = eccpos[index] & ~(busw - 1);
+ aligned_len = eccfrag_len;
+ if (eccpos[index] & (busw - 1))
+@@ -1498,6 +1501,7 @@
+ mtd->oobavail : mtd->oobsize;
+
+ uint8_t *bufpoi, *oob, *buf;
++ int use_bufpoi;
+ unsigned int max_bitflips = 0;
+ int retry_mode = 0;
+ bool ecc_fail = false;
+@@ -1520,9 +1524,20 @@
+ bytes = min(mtd->writesize - col, readlen);
+ aligned = (bytes == mtd->writesize);
+
++ if (!aligned)
++ use_bufpoi = 1;
++ else if (chip->options & NAND_USE_BOUNCE_BUFFER)
++ use_bufpoi = !virt_addr_valid(buf);
++ else
++ use_bufpoi = 0;
++
+ /* Is the current page in the buffer? */
+ if (realpage != chip->pagebuf || oob) {
+- bufpoi = aligned ? buf : chip->buffers->databuf;
++ bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
++
++ if (use_bufpoi && aligned)
++ pr_debug("%s: using read bounce buffer for buf@%p\n",
++ __func__, buf);
+
+ read_retry:
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+@@ -1538,12 +1553,13 @@
+ else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
+ !oob)
+ ret = chip->ecc.read_subpage(mtd, chip,
+- col, bytes, bufpoi);
++ col, bytes, bufpoi,
++ page);
+ else
+ ret = chip->ecc.read_page(mtd, chip, bufpoi,
+ oob_required, page);
+ if (ret < 0) {
+- if (!aligned)
++ if (use_bufpoi)
+ /* Invalidate page cache */
+ chip->pagebuf = -1;
+ break;
+@@ -1552,7 +1568,7 @@
+ max_bitflips = max_t(unsigned int, max_bitflips, ret);
+
+ /* Transfer not aligned data */
+- if (!aligned) {
++ if (use_bufpoi) {
+ if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
+ !(mtd->ecc_stats.failed - ecc_failures) &&
+ (ops->mode != MTD_OPS_RAW)) {
+@@ -2372,11 +2388,23 @@
+ int bytes = mtd->writesize;
+ int cached = writelen > bytes && page != blockmask;
+ uint8_t *wbuf = buf;
++ int use_bufpoi;
++ int part_pagewr = (column || writelen < (mtd->writesize - 1));
++
++ if (part_pagewr)
++ use_bufpoi = 1;
++ else if (chip->options & NAND_USE_BOUNCE_BUFFER)
++ use_bufpoi = !virt_addr_valid(buf);
++ else
++ use_bufpoi = 0;
+
+- /* Partial page write? */
+- if (unlikely(column || writelen < (mtd->writesize - 1))) {
++ /* Partial page write?, or need to use bounce buffer */
++ if (use_bufpoi) {
++ pr_debug("%s: using write bounce buffer for buf@%p\n",
++ __func__, buf);
+ cached = 0;
+- bytes = min_t(int, bytes - column, (int) writelen);
++ if (part_pagewr)
++ bytes = min_t(int, bytes - column, writelen);
+ chip->pagebuf = -1;
+ memset(chip->buffers->databuf, 0xff, mtd->writesize);
+ memcpy(&chip->buffers->databuf[column], buf, bytes);
+@@ -2614,18 +2642,20 @@
+ }
+
+ /**
+- * single_erase_cmd - [GENERIC] NAND standard block erase command function
++ * single_erase - [GENERIC] NAND standard block erase command function
+ * @mtd: MTD device structure
+ * @page: the page address of the block which will be erased
+ *
+- * Standard erase command for NAND chips.
++ * Standard erase command for NAND chips. Returns NAND status.
+ */
+-static void single_erase_cmd(struct mtd_info *mtd, int page)
++static int single_erase(struct mtd_info *mtd, int page)
+ {
+ struct nand_chip *chip = mtd->priv;
+ /* Send commands to erase a block */
+ chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+ chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
++
++ return chip->waitfunc(mtd, chip);
+ }
+
+ /**
+@@ -2706,9 +2736,7 @@
+ (page + pages_per_block))
+ chip->pagebuf = -1;
+
+- chip->erase_cmd(mtd, page & chip->pagemask);
+-
+- status = chip->waitfunc(mtd, chip);
++ status = chip->erase(mtd, page & chip->pagemask);
+
+ /*
+ * See if operation failed and additional status checks are
+@@ -3161,6 +3189,87 @@
+ }
+
+ /*
++ * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
++ */
++static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
++ int *busw)
++{
++ struct nand_jedec_params *p = &chip->jedec_params;
++ struct jedec_ecc_info *ecc;
++ int val;
++ int i, j;
++
++ /* Try JEDEC for unknown chip or LP */
++ chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
++ if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
++ chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
++ chip->read_byte(mtd) != 'C')
++ return 0;
++
++ chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
++ for (i = 0; i < 3; i++) {
++ for (j = 0; j < sizeof(*p); j++)
++ ((uint8_t *)p)[j] = chip->read_byte(mtd);
++
++ if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
++ le16_to_cpu(p->crc))
++ break;
++ }
++
++ if (i == 3) {
++ pr_err("Could not find valid JEDEC parameter page; aborting\n");
++ return 0;
++ }
++
++ /* Check version */
++ val = le16_to_cpu(p->revision);
++ if (val & (1 << 2))
++ chip->jedec_version = 10;
++ else if (val & (1 << 1))
++ chip->jedec_version = 1; /* vendor specific version */
++
++ if (!chip->jedec_version) {
++ pr_info("unsupported JEDEC version: %d\n", val);
++ return 0;
++ }
++
++ sanitize_string(p->manufacturer, sizeof(p->manufacturer));
++ sanitize_string(p->model, sizeof(p->model));
++ if (!mtd->name)
++ mtd->name = p->model;
++
++ mtd->writesize = le32_to_cpu(p->byte_per_page);
++
++ /* Please reference to the comment for nand_flash_detect_onfi. */
++ mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
++ mtd->erasesize *= mtd->writesize;
++
++ mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
++
++ /* Please reference to the comment for nand_flash_detect_onfi. */
++ chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
++ chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
++ chip->bits_per_cell = p->bits_per_cell;
++
++ if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
++ *busw = NAND_BUSWIDTH_16;
++ else
++ *busw = 0;
++
++ /* ECC info */
++ ecc = &p->ecc_info[0];
++
++ if (ecc->codeword_size >= 9) {
++ chip->ecc_strength_ds = ecc->ecc_bits;
++ chip->ecc_step_ds = 1 << ecc->codeword_size;
++ } else {
++ pr_warn("Invalid codeword size\n");
++ }
++
++ return 1;
++}
++
++/*
+ * nand_id_has_period - Check if an ID string has a given wraparound period
+ * @id_data: the ID string
+ * @arrlen: the length of the @id_data array
+@@ -3466,10 +3575,10 @@
+ */
+ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
+ struct nand_chip *chip,
+- int busw,
+ int *maf_id, int *dev_id,
+ struct nand_flash_dev *type)
+ {
++ int busw;
+ int i, maf_idx;
+ u8 id_data[8];
+
+@@ -3522,9 +3631,13 @@
+
+ chip->onfi_version = 0;
+ if (!type->name || !type->pagesize) {
+- /* Check is chip is ONFI compliant */
++ /* Check if the chip is ONFI compliant */
+ if (nand_flash_detect_onfi(mtd, chip, &busw))
+ goto ident_done;
++
++ /* Check if the chip is JEDEC compliant */
++ if (nand_flash_detect_jedec(mtd, chip, &busw))
++ goto ident_done;
+ }
+
+ if (!type->name)
+@@ -3596,7 +3709,7 @@
+ }
+
+ chip->badblockbits = 8;
+- chip->erase_cmd = single_erase_cmd;
++ chip->erase = single_erase;
+
+ /* Do not replace user supplied command function! */
+ if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
+@@ -3604,8 +3717,17 @@
+
+ pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
+ *maf_id, *dev_id);
+- pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
+- chip->onfi_version ? chip->onfi_params.model : type->name);
++
++ if (chip->onfi_version)
++ pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
++ chip->onfi_params.model);
++ else if (chip->jedec_version)
++ pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
++ chip->jedec_params.model);
++ else
++ pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
++ type->name);
++
+ pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
+ (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
+ mtd->writesize, mtd->oobsize);
+@@ -3626,18 +3748,16 @@
+ int nand_scan_ident(struct mtd_info *mtd, int maxchips,
+ struct nand_flash_dev *table)
+ {
+- int i, busw, nand_maf_id, nand_dev_id;
++ int i, nand_maf_id, nand_dev_id;
+ struct nand_chip *chip = mtd->priv;
+ struct nand_flash_dev *type;
+
+- /* Get buswidth to select the correct functions */
+- busw = chip->options & NAND_BUSWIDTH_16;
+ /* Set the default functions */
+- nand_set_defaults(chip, busw);
++ nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
+
+ /* Read the flash type */
+- type = nand_get_flash_type(mtd, chip, busw,
+- &nand_maf_id, &nand_dev_id, table);
++ type = nand_get_flash_type(mtd, chip, &nand_maf_id,
++ &nand_dev_id, table);
+
+ if (IS_ERR(type)) {
+ if (!(chip->options & NAND_SCAN_SILENT_NODEV))
+@@ -3674,6 +3794,39 @@
+ }
+ EXPORT_SYMBOL(nand_scan_ident);
+
++/*
++ * Check if the chip configuration meet the datasheet requirements.
++
++ * If our configuration corrects A bits per B bytes and the minimum
++ * required correction level is X bits per Y bytes, then we must ensure
++ * both of the following are true:
++ *
++ * (1) A / B >= X / Y
++ * (2) A >= X
++ *
++ * Requirement (1) ensures we can correct for the required bitflip density.
++ * Requirement (2) ensures we can correct even when all bitflips are clumped
++ * in the same sector.
++ */
++static bool nand_ecc_strength_good(struct mtd_info *mtd)
++{
++ struct nand_chip *chip = mtd->priv;
++ struct nand_ecc_ctrl *ecc = &chip->ecc;
++ int corr, ds_corr;
++
++ if (ecc->size == 0 || chip->ecc_step_ds == 0)
++ /* Not enough information */
++ return true;
++
++ /*
++ * We get the number of corrected bits per page to compare
++ * the correction density.
++ */
++ corr = (mtd->writesize * ecc->strength) / ecc->size;
++ ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
++
++ return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
++}
+
+ /**
+ * nand_scan_tail - [NAND Interface] Scan for the NAND device
+@@ -3688,15 +3841,26 @@
+ int i;
+ struct nand_chip *chip = mtd->priv;
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
++ struct nand_buffers *nbuf;
+
+ /* New bad blocks should be marked in OOB, flash-based BBT, or both */
+ BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
+ !(chip->bbt_options & NAND_BBT_USE_FLASH));
+
+- if (!(chip->options & NAND_OWN_BUFFERS))
+- chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
+- if (!chip->buffers)
+- return -ENOMEM;
++ if (!(chip->options & NAND_OWN_BUFFERS)) {
++ nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
++ + mtd->oobsize * 3, GFP_KERNEL);
++ if (!nbuf)
++ return -ENOMEM;
++ nbuf->ecccalc = (uint8_t *)(nbuf + 1);
++ nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
++ nbuf->databuf = nbuf->ecccode + mtd->oobsize;
++
++ chip->buffers = nbuf;
++ } else {
++ if (!chip->buffers)
++ return -ENOMEM;
++ }
+
+ /* Set the internal oob buffer location, just after the page data */
+ chip->oob_poi = chip->buffers->databuf + mtd->writesize;
+@@ -3817,7 +3981,7 @@
+
+ case NAND_ECC_SOFT_BCH:
+ if (!mtd_nand_has_bch()) {
+- pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
++ pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
+ BUG();
+ }
+ ecc->calculate = nand_bch_calculate_ecc;
+@@ -3883,6 +4047,9 @@
+ ecc->layout->oobavail += ecc->layout->oobfree[i].length;
+ mtd->oobavail = ecc->layout->oobavail;
+
++ /* ECC sanity check: warn noisily if it's too weak */
++ WARN_ON(!nand_ecc_strength_good(mtd));
++
+ /*
+ * Set the number of read / write steps for one page depending on ECC
+ * mode.
+@@ -3916,8 +4083,16 @@
+ chip->pagebuf = -1;
+
+ /* Large page NAND with SOFT_ECC should support subpage reads */
+- if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
+- chip->options |= NAND_SUBPAGE_READ;
++ switch (ecc->mode) {
++ case NAND_ECC_SOFT:
++ case NAND_ECC_SOFT_BCH:
++ if (chip->page_shift > 9)
++ chip->options |= NAND_SUBPAGE_READ;
++ break;
++
++ default:
++ break;
++ }
+
+ /* Fill in remaining MTD driver data */
+ mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/nand_bbt.c linux-3.14.72/drivers/mtd/nand/nand_bbt.c
+--- linux-3.14.72.orig/drivers/mtd/nand/nand_bbt.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/nand_bbt.c 2016-06-19 22:11:55.209146306 +0200
+@@ -528,7 +528,7 @@
+ {
+ struct nand_chip *this = mtd->priv;
+ int i, chips;
+- int bits, startblock, block, dir;
++ int startblock, block, dir;
+ int scanlen = mtd->writesize + mtd->oobsize;
+ int bbtblocks;
+ int blocktopage = this->bbt_erase_shift - this->page_shift;
+@@ -552,9 +552,6 @@
+ bbtblocks = mtd->size >> this->bbt_erase_shift;
+ }
+
+- /* Number of bits for each erase block in the bbt */
+- bits = td->options & NAND_BBT_NRBITS_MSK;
+-
+ for (i = 0; i < chips; i++) {
+ /* Reset version information */
+ td->version[i] = 0;
+@@ -1285,6 +1282,7 @@
+ int nand_default_bbt(struct mtd_info *mtd)
+ {
+ struct nand_chip *this = mtd->priv;
++ int ret;
+
+ /* Is a flash based bad block table requested? */
+ if (this->bbt_options & NAND_BBT_USE_FLASH) {
+@@ -1303,8 +1301,11 @@
+ this->bbt_md = NULL;
+ }
+
+- if (!this->badblock_pattern)
+- nand_create_badblock_pattern(this);
++ if (!this->badblock_pattern) {
++ ret = nand_create_badblock_pattern(this);
++ if (ret)
++ return ret;
++ }
+
+ return nand_scan_bbt(mtd, this->badblock_pattern);
+ }
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/nand_ids.c linux-3.14.72/drivers/mtd/nand/nand_ids.c
+--- linux-3.14.72.orig/drivers/mtd/nand/nand_ids.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/nand_ids.c 2016-06-19 22:11:55.209146306 +0200
+@@ -43,6 +43,9 @@
+ {"TC58NVG6D2 64G 3.3V 8-bit",
+ { .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
+ SZ_8K, SZ_8K, SZ_2M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
++ {"SDTNRGAMA 64G 3.3V 8-bit",
++ { .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
++ SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
+
+ LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
+ LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
+diff -Nur linux-3.14.72.orig/drivers/mtd/nand/nuc900_nand.c linux-3.14.72/drivers/mtd/nand/nuc900_nand.c
+--- linux-3.14.72.orig/drivers/mtd/nand/nuc900_nand.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/nand/nuc900_nand.c 2016-06-19 22:11:55.209146306 +0200
+@@ -152,7 +152,8 @@
+ if (column != -1 || page_addr != -1) {
+
+ if (column != -1) {
+- if (chip->options & NAND_BUSWIDTH_16)
++ if (chip->options & NAND_BUSWIDTH_16 &&
++ !nand_opcode_8bits(command))
+ column >>= 1;
+ write_addr_reg(nand, column);
+ write_addr_reg(nand, column >> 8 | ENDADDR);
+diff -Nur linux-3.14.72.orig/drivers/mtd/spi-nor/fsl-quadspi.c linux-3.14.72/drivers/mtd/spi-nor/fsl-quadspi.c
+--- linux-3.14.72.orig/drivers/mtd/spi-nor/fsl-quadspi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mtd/spi-nor/fsl-quadspi.c 2016-06-19 22:11:55.209146306 +0200
+@@ -0,0 +1,1180 @@
++/*
++ * Freescale QuadSPI driver.
++ *
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/interrupt.h>
++#include <linux/errno.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/timer.h>
++#include <linux/jiffies.h>
++#include <linux/completion.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/spi-nor.h>
++#include <linux/mutex.h>
++#include <linux/pm_qos.h>
++
++/* The registers */
++#define QUADSPI_MCR 0x00
++#define MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_SHIFT 29
++#define MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_MASK \
++ (1 << MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_SHIFT)
++#define QUADSPI_MCR_RESERVED_SHIFT 16
++#define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
++#define QUADSPI_MCR_MDIS_SHIFT 14
++#define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
++#define QUADSPI_MCR_CLR_TXF_SHIFT 11
++#define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
++#define QUADSPI_MCR_CLR_RXF_SHIFT 10
++#define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
++#define QUADSPI_MCR_DDR_EN_SHIFT 7
++#define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
++#define QUADSPI_MCR_END_CFG_SHIFT 2
++#define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
++#define QUADSPI_MCR_SWRSTHD_SHIFT 1
++#define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
++#define QUADSPI_MCR_SWRSTSD_SHIFT 0
++#define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
++
++#define QUADSPI_IPCR 0x08
++#define QUADSPI_IPCR_SEQID_SHIFT 24
++#define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
++
++#define QUADSPI_BUF0CR 0x10
++#define QUADSPI_BUF1CR 0x14
++#define QUADSPI_BUF2CR 0x18
++#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
++
++#define QUADSPI_BUF3CR 0x1c
++#define QUADSPI_BUF3CR_ALLMST_SHIFT 31
++#define QUADSPI_BUF3CR_ALLMST_MASK (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
++#define QUADSPI_BUF3CR_ADATSZ_SHIFT 8
++#define QUADSPI_BUF3CR_ADATSZ_MASK (0xFF << QUADSPI_BUF3CR_ADATSZ_SHIFT)
++
++#define QUADSPI_BFGENCR 0x20
++#define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
++#define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
++#define QUADSPI_BFGENCR_SEQID_SHIFT 12
++#define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
++
++#define QUADSPI_BUF0IND 0x30
++#define QUADSPI_BUF1IND 0x34
++#define QUADSPI_BUF2IND 0x38
++#define QUADSPI_SFAR 0x100
++
++#define QUADSPI_SMPR 0x108
++#define QUADSPI_SMPR_DDRSMP_SHIFT 16
++#define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
++#define QUADSPI_SMPR_FSDLY_SHIFT 6
++#define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
++#define QUADSPI_SMPR_FSPHS_SHIFT 5
++#define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
++#define QUADSPI_SMPR_HSENA_SHIFT 0
++#define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
++
++#define QUADSPI_RBSR 0x10c
++#define QUADSPI_RBSR_RDBFL_SHIFT 8
++#define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
++
++#define QUADSPI_RBCT 0x110
++#define QUADSPI_RBCT_WMRK_MASK 0x1F
++#define QUADSPI_RBCT_RXBRD_SHIFT 8
++#define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
++
++#define QUADSPI_TBSR 0x150
++#define QUADSPI_TBDR 0x154
++#define QUADSPI_SR 0x15c
++#define QUADSPI_SR_IP_ACC_SHIFT 1
++#define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
++#define QUADSPI_SR_AHB_ACC_SHIFT 2
++#define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
++
++#define QUADSPI_FR 0x160
++#define QUADSPI_FR_TFF_MASK 0x1
++
++#define QUADSPI_SFA1AD 0x180
++#define QUADSPI_SFA2AD 0x184
++#define QUADSPI_SFB1AD 0x188
++#define QUADSPI_SFB2AD 0x18c
++#define QUADSPI_RBDR 0x200
++
++#define QUADSPI_LUTKEY 0x300
++#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
++
++#define QUADSPI_LCKCR 0x304
++#define QUADSPI_LCKER_LOCK 0x1
++#define QUADSPI_LCKER_UNLOCK 0x2
++
++#define QUADSPI_RSER 0x164
++#define QUADSPI_RSER_TFIE (0x1 << 0)
++
++#define QUADSPI_LUT_BASE 0x310
++
++/*
++ * The definition of the LUT register shows below:
++ *
++ * ---------------------------------------------------
++ * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
++ * ---------------------------------------------------
++ */
++#define OPRND0_SHIFT 0
++#define PAD0_SHIFT 8
++#define INSTR0_SHIFT 10
++#define OPRND1_SHIFT 16
++
++/* Instruction set for the LUT register. */
++#define LUT_STOP 0
++#define LUT_CMD 1
++#define LUT_ADDR 2
++#define LUT_DUMMY 3
++#define LUT_MODE 4
++#define LUT_MODE2 5
++#define LUT_MODE4 6
++#define LUT_READ 7
++#define LUT_WRITE 8
++#define LUT_JMP_ON_CS 9
++#define LUT_ADDR_DDR 10
++#define LUT_MODE_DDR 11
++#define LUT_MODE2_DDR 12
++#define LUT_MODE4_DDR 13
++#define LUT_READ_DDR 14
++#define LUT_WRITE_DDR 15
++#define LUT_DATA_LEARN 16
++
++/*
++ * The PAD definitions for LUT register.
++ *
++ * The pad stands for the lines number of IO[0:3].
++ * For example, the Quad read need four IO lines, so you should
++ * set LUT_PAD4 which means we use four IO lines.
++ */
++#define LUT_PAD1 0
++#define LUT_PAD2 1
++#define LUT_PAD4 2
++
++/* Oprands for the LUT register. */
++#define ADDR24BIT 0x18
++#define ADDR32BIT 0x20
++
++/* Macros for constructing the LUT register. */
++#define LUT0(ins, pad, opr) \
++ (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
++ ((LUT_##ins) << INSTR0_SHIFT))
++
++#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
++
++/* other macros for LUT register. */
++#define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
++#define QUADSPI_LUT_NUM 64
++
++/* SEQID -- we can have 16 seqids at most. */
++#define SEQID_QUAD_READ 0
++#define SEQID_WREN 1
++#define SEQID_WRDI 2
++#define SEQID_RDSR 3
++#define SEQID_SE 4
++#define SEQID_CHIP_ERASE 5
++#define SEQID_PP 6
++#define SEQID_RDID 7
++#define SEQID_WRSR 8
++#define SEQID_RDCR 9
++#define SEQID_EN4B 10
++#define SEQID_BRWR 11
++
++enum fsl_qspi_devtype {
++ FSL_QUADSPI_VYBRID,
++ FSL_QUADSPI_IMX6SX,
++};
++
++struct fsl_qspi_devtype_data {
++ enum fsl_qspi_devtype devtype;
++ int rxfifo;
++ int txfifo;
++ int ahb_buf_size;
++};
++
++static struct fsl_qspi_devtype_data vybrid_data = {
++ .devtype = FSL_QUADSPI_VYBRID,
++ .rxfifo = 128,
++ .txfifo = 64,
++ .ahb_buf_size = 1024
++};
++
++static struct fsl_qspi_devtype_data imx6sx_data = {
++ .devtype = FSL_QUADSPI_IMX6SX,
++ .rxfifo = 128,
++ .txfifo = 512,
++ .ahb_buf_size = 1024
++};
++
++#define FSL_QSPI_MAX_CHIP 4
++struct fsl_qspi {
++ struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
++ struct spi_nor nor[FSL_QSPI_MAX_CHIP];
++ void __iomem *iobase;
++ void __iomem *ahb_addr;
++ u32 memmap_phy;
++ u32 memmap_offs;
++ u32 memmap_len;
++ struct clk *clk, *clk_en;
++ struct device *dev;
++ struct completion c;
++ struct fsl_qspi_devtype_data *devtype_data;
++ u32 nor_size;
++ u32 nor_num;
++ u32 clk_rate;
++ unsigned int chip_base_addr; /* We may support two chips. */
++ u32 ddr_smp;
++ struct mutex lock;
++ struct pm_qos_request pm_qos_req;
++};
++
++static inline int is_vybrid_qspi(struct fsl_qspi *q)
++{
++ return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
++}
++
++static inline int is_imx6sx_qspi(struct fsl_qspi *q)
++{
++ return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
++}
++
++/*
++ * An IC bug makes us to re-arrange the 32-bit data.
++ * The following chips, such as IMX6SLX, have fixed this bug.
++ */
++static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
++{
++ return is_vybrid_qspi(q) ? __swab32(a) : a;
++}
++
++static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
++{
++ writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
++ writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
++}
++
++static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
++{
++ writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
++ writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
++}
++
++static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
++{
++ struct fsl_qspi *q = dev_id;
++ u32 reg;
++
++ /* clear interrupt */
++ reg = readl(q->iobase + QUADSPI_FR);
++ writel(reg, q->iobase + QUADSPI_FR);
++
++ if (reg & QUADSPI_FR_TFF_MASK)
++ complete(&q->c);
++
++ dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
++ return IRQ_HANDLED;
++}
++
++static void fsl_qspi_init_lut(struct fsl_qspi *q)
++{
++ void __iomem *base = q->iobase;
++ int rxfifo = q->devtype_data->rxfifo;
++ struct spi_nor *nor = &q->nor[0];
++ u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
++ u32 lut_base;
++ u8 op, dm;
++ int i;
++
++ fsl_qspi_unlock_lut(q);
++
++ /* Clear all the LUT table */
++ for (i = 0; i < QUADSPI_LUT_NUM; i++)
++ writel(0, base + QUADSPI_LUT_BASE + i * 4);
++
++ /* Quad Read and DDR Quad Read*/
++ lut_base = SEQID_QUAD_READ * 4;
++ op = nor->read_opcode;
++ dm = nor->read_dummy;
++ if (nor->flash_read == SPI_NOR_QUAD) {
++ if (op == SPINOR_OP_READ_1_1_4 || op == SPINOR_OP_READ4_1_1_4) {
++ /* read mode : 1-1-4 */
++ writel(LUT0(CMD, PAD1, op) | LUT1(ADDR, PAD1, addrlen),
++ base + QUADSPI_LUT(lut_base));
++
++ writel(LUT0(DUMMY, PAD1, dm) | LUT1(READ, PAD4, rxfifo),
++ base + QUADSPI_LUT(lut_base + 1));
++ } else {
++ dev_err(nor->dev, "Unsupported opcode : 0x%.2x\n", op);
++ }
++ } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
++ if (op == SPINOR_OP_READ_1_4_4_D ||
++ op == SPINOR_OP_READ4_1_4_4_D) {
++ /* read mode : 1-4-4, such as Spansion s25fl128s. */
++ writel(LUT0(CMD, PAD1, op)
++ | LUT1(ADDR_DDR, PAD4, addrlen),
++ base + QUADSPI_LUT(lut_base));
++
++ writel(LUT0(MODE_DDR, PAD4, 0xff)
++ | LUT1(DUMMY, PAD1, dm),
++ base + QUADSPI_LUT(lut_base + 1));
++
++ writel(LUT0(READ_DDR, PAD4, rxfifo)
++ | LUT1(JMP_ON_CS, PAD1, 0),
++ base + QUADSPI_LUT(lut_base + 2));
++ } else if (op == SPINOR_OP_READ_1_1_4_D) {
++ /* read mode : 1-1-4, such as Micron N25Q256A. */
++ writel(LUT0(CMD, PAD1, op)
++ | LUT1(ADDR_DDR, PAD1, addrlen),
++ base + QUADSPI_LUT(lut_base));
++
++ writel(LUT0(DUMMY, PAD1, dm)
++ | LUT1(READ_DDR, PAD4, rxfifo),
++ base + QUADSPI_LUT(lut_base + 1));
++
++ writel(LUT0(JMP_ON_CS, PAD1, 0),
++ base + QUADSPI_LUT(lut_base + 2));
++ } else {
++ dev_err(nor->dev, "Unsupported opcode : 0x%.2x\n", op);
++ }
++ }
++
++ /* Write enable */
++ lut_base = SEQID_WREN * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
++
++ /* Page Program */
++ lut_base = SEQID_PP * 4;
++ writel(LUT0(CMD, PAD1, nor->program_opcode) | LUT1(ADDR, PAD1, addrlen),
++ base + QUADSPI_LUT(lut_base));
++ writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
++
++ /* Read Status */
++ lut_base = SEQID_RDSR * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
++ base + QUADSPI_LUT(lut_base));
++
++ /* Erase a sector */
++ lut_base = SEQID_SE * 4;
++ writel(LUT0(CMD, PAD1, nor->erase_opcode) | LUT1(ADDR, PAD1, addrlen),
++ base + QUADSPI_LUT(lut_base));
++
++ /* Erase the whole chip */
++ lut_base = SEQID_CHIP_ERASE * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
++ base + QUADSPI_LUT(lut_base));
++
++ /* READ ID */
++ lut_base = SEQID_RDID * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
++ base + QUADSPI_LUT(lut_base));
++
++ /* Write Register */
++ lut_base = SEQID_WRSR * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
++ base + QUADSPI_LUT(lut_base));
++
++ /* Read Configuration Register */
++ lut_base = SEQID_RDCR * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
++ base + QUADSPI_LUT(lut_base));
++
++ /* Write disable */
++ lut_base = SEQID_WRDI * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
++
++ /* Enter 4 Byte Mode (Micron) */
++ lut_base = SEQID_EN4B * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
++
++ /* Enter 4 Byte Mode (Spansion) */
++ lut_base = SEQID_BRWR * 4;
++ writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
++
++ fsl_qspi_lock_lut(q);
++}
++
++/* Get the SEQID for the command */
++static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
++{
++ switch (cmd) {
++ case SPINOR_OP_READ_1_1_4_D:
++ case SPINOR_OP_READ_1_4_4_D:
++ case SPINOR_OP_READ4_1_4_4_D:
++ case SPINOR_OP_READ4_1_1_4:
++ case SPINOR_OP_READ_1_1_4:
++ return SEQID_QUAD_READ;
++ case SPINOR_OP_WREN:
++ return SEQID_WREN;
++ case SPINOR_OP_WRDI:
++ return SEQID_WRDI;
++ case SPINOR_OP_RDSR:
++ return SEQID_RDSR;
++ case SPINOR_OP_BE_4K:
++ case SPINOR_OP_SE:
++ return SEQID_SE;
++ case SPINOR_OP_CHIP_ERASE:
++ return SEQID_CHIP_ERASE;
++ case SPINOR_OP_PP:
++ return SEQID_PP;
++ case SPINOR_OP_RDID:
++ return SEQID_RDID;
++ case SPINOR_OP_WRSR:
++ return SEQID_WRSR;
++ case SPINOR_OP_RDCR:
++ return SEQID_RDCR;
++ case SPINOR_OP_EN4B:
++ return SEQID_EN4B;
++ case SPINOR_OP_BRWR:
++ return SEQID_BRWR;
++ default:
++ dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
++ break;
++ }
++ return -EINVAL;
++}
++
++static int
++fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
++{
++ void __iomem *base = q->iobase;
++ int seqid;
++ u32 reg, reg2;
++ int err;
++
++ init_completion(&q->c);
++ dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
++ q->chip_base_addr, addr, len, cmd);
++
++ /* save the reg */
++ reg = readl(base + QUADSPI_MCR);
++
++ writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
++ writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
++ base + QUADSPI_RBCT);
++ writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
++
++ do {
++ reg2 = readl(base + QUADSPI_SR);
++ if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
++ udelay(1);
++ dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
++ continue;
++ }
++ break;
++ } while (1);
++
++ /* trigger the LUT now */
++ seqid = fsl_qspi_get_seqid(q, cmd);
++ writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
++
++ /* Wait for the interrupt. */
++ err = wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000));
++ if (!err) {
++ dev_err(q->dev,
++ "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
++ cmd, addr, readl(base + QUADSPI_FR),
++ readl(base + QUADSPI_SR));
++ err = -ETIMEDOUT;
++ } else {
++ err = 0;
++ }
++
++ /* restore the MCR */
++ writel(reg, base + QUADSPI_MCR);
++
++ return err;
++}
++
++/* Read out the data from the QUADSPI_RBDR buffer registers. */
++static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
++{
++ u32 tmp;
++ int i = 0;
++
++ while (len > 0) {
++ tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
++ tmp = fsl_qspi_endian_xchg(q, tmp);
++ dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
++ q->chip_base_addr, tmp);
++
++ if (len >= 4) {
++ *((u32 *)rxbuf) = tmp;
++ rxbuf += 4;
++ } else {
++ memcpy(rxbuf, &tmp, len);
++ break;
++ }
++
++ len -= 4;
++ i++;
++ }
++}
++
++/*
++ * If we have changed the content of the flash by writing or erasing,
++ * we need to invalidate the AHB buffer. If we do not do so, we may read out
++ * the wrong data. The spec tells us reset the AHB domain and Serial Flash
++ * domain at the same time.
++ */
++static inline void fsl_qspi_invalid(struct fsl_qspi *q)
++{
++ u32 reg;
++
++ reg = readl(q->iobase + QUADSPI_MCR);
++ reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
++ writel(reg, q->iobase + QUADSPI_MCR);
++
++ /*
++ * The minimum delay : 1 AHB + 2 SFCK clocks.
++ * Delay 1 us is enough.
++ */
++ udelay(1);
++
++ reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
++ writel(reg, q->iobase + QUADSPI_MCR);
++}
++
++static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
++ u8 opcode, unsigned int to, u32 *txbuf,
++ unsigned count, size_t *retlen)
++{
++ int ret, i, j;
++ u32 tmp;
++
++ dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
++ q->chip_base_addr, to, count);
++
++ /* clear the TX FIFO. */
++ tmp = readl(q->iobase + QUADSPI_MCR);
++ writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
++
++ /* fill the TX data to the FIFO */
++ for (j = 0, i = ((count + 3) / 4); j < i; j++) {
++ tmp = fsl_qspi_endian_xchg(q, *txbuf);
++ writel(tmp, q->iobase + QUADSPI_TBDR);
++ txbuf++;
++ }
++
++ /* Trigger it */
++ ret = fsl_qspi_runcmd(q, opcode, to, count);
++
++ if (ret == 0 && retlen)
++ *retlen += count;
++
++ return ret;
++}
++
++static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
++{
++ int nor_size = q->nor_size;
++ void __iomem *base = q->iobase;
++
++ writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
++ writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
++ writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
++ writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
++}
++
++/*
++ * There are two different ways to read out the data from the flash:
++ * the "IP Command Read" and the "AHB Command Read".
++ *
++ * The IC guy suggests we use the "AHB Command Read" which is faster
++ * then the "IP Command Read". (What's more is that there is a bug in
++ * the "IP Command Read" in the Vybrid.)
++ *
++ * After we set up the registers for the "AHB Command Read", we can use
++ * the memcpy to read the data directly. A "missed" access to the buffer
++ * causes the controller to clear the buffer, and use the sequence pointed
++ * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
++ */
++static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
++{
++ void __iomem *base = q->iobase;
++ struct spi_nor *nor = &q->nor[0];
++ u32 reg, reg2;
++ int seqid;
++
++ /* AHB configuration for access buffer 0/1/2 . */
++ writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
++ writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
++ writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
++ /*
++ * Set ADATSZ with the maximum AHB buffer size to improve the
++ * read performance.
++ */
++ writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8)
++ << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR);
++
++ /* We only use the buffer3 */
++ writel(0, base + QUADSPI_BUF0IND);
++ writel(0, base + QUADSPI_BUF1IND);
++ writel(0, base + QUADSPI_BUF2IND);
++
++ /* Set the default lut sequence for AHB Read. */
++ seqid = fsl_qspi_get_seqid(q, nor->read_opcode);
++ writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
++ q->iobase + QUADSPI_BFGENCR);
++
++ /* enable the DDR quad read */
++ if (nor->flash_read == SPI_NOR_DDR_QUAD) {
++ reg = readl(q->iobase + QUADSPI_MCR);
++
++ /* Firstly, disable the module */
++ writel(reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
++
++ /* Set the Sampling Register for DDR */
++ reg2 = readl(q->iobase + QUADSPI_SMPR);
++ reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
++ reg2 |= ((q->ddr_smp << QUADSPI_SMPR_DDRSMP_SHIFT) &
++ QUADSPI_SMPR_DDRSMP_MASK);
++ writel(reg2, q->iobase + QUADSPI_SMPR);
++
++ /* Enable the module again (enable the DDR too) */
++ reg |= QUADSPI_MCR_DDR_EN_MASK;
++ if (is_imx6sx_qspi(q))
++ reg |= MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_MASK;
++
++ writel(reg, q->iobase + QUADSPI_MCR);
++ }
++}
++
++/* This function was used to prepare and enable QSPI clock */
++static int fsl_qspi_clk_prep_enable(struct fsl_qspi *q)
++{
++ int ret;
++
++ ret = clk_prepare_enable(q->clk_en);
++ if (ret)
++ return ret;
++
++ ret = clk_prepare_enable(q->clk);
++ if (ret) {
++ clk_disable_unprepare(q->clk_en);
++ return ret;
++ }
++
++ pm_qos_add_request(&q->pm_qos_req,
++ PM_QOS_CPU_DMA_LATENCY,
++ 0);
++
++ return 0;
++}
++
++/* This function was used to disable and unprepare QSPI clock */
++static int fsl_qspi_clk_disable_unprep(struct fsl_qspi *q)
++{
++ pm_qos_remove_request(&q->pm_qos_req);
++ clk_disable_unprepare(q->clk);
++ clk_disable_unprepare(q->clk_en);
++ return 0;
++}
++
++/* We use this function to do some basic init for spi_nor_scan(). */
++static int fsl_qspi_nor_setup(struct fsl_qspi *q)
++{
++ void __iomem *base = q->iobase;
++ u32 reg;
++ int ret;
++
++ /* disable and unprepare clock first */
++ fsl_qspi_clk_disable_unprep(q);
++
++ /* the default frequency, we will change it in the future. */
++ ret = clk_set_rate(q->clk, 66000000);
++ if (ret)
++ return ret;
++
++ /* prepare and enable the clock */
++ ret = fsl_qspi_clk_prep_enable(q);
++ if (ret)
++ return ret;
++
++ /* Reset the module */
++ writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK,
++ base + QUADSPI_MCR);
++ udelay(1);
++
++ /* Init the LUT table. */
++ fsl_qspi_init_lut(q);
++
++ /* Disable the module */
++ writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
++ base + QUADSPI_MCR);
++
++ reg = readl(base + QUADSPI_SMPR);
++ writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
++ | QUADSPI_SMPR_FSPHS_MASK
++ | QUADSPI_SMPR_HSENA_MASK
++ | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
++
++ /* Enable the module */
++ writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
++ base + QUADSPI_MCR);
++
++ /* enable the interrupt */
++ writel(0xffffffff, q->iobase + QUADSPI_FR);
++ writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
++
++ return 0;
++}
++
++static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
++{
++ unsigned long rate = q->clk_rate;
++ int ret;
++
++ if (is_imx6sx_qspi(q))
++ rate *= 4;
++
++ /* disable and unprepare clock first */
++ fsl_qspi_clk_disable_unprep(q);
++
++ ret = clk_set_rate(q->clk, rate);
++ if (ret)
++ return ret;
++
++ /* prepare and enable the clock */
++ ret = fsl_qspi_clk_prep_enable(q);
++ if (ret)
++ return ret;
++
++ /* Init the LUT table again. */
++ fsl_qspi_init_lut(q);
++
++ /* Init for AHB read */
++ fsl_qspi_init_abh_read(q);
++
++ return 0;
++}
++
++static struct of_device_id fsl_qspi_dt_ids[] = {
++ { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
++ { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
++
++static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
++{
++ q->chip_base_addr = q->nor_size * (nor - q->nor);
++}
++
++static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
++{
++ int ret;
++ struct fsl_qspi *q = nor->priv;
++
++ ret = fsl_qspi_runcmd(q, opcode, 0, len);
++ if (ret)
++ return ret;
++
++ fsl_qspi_read_data(q, len, buf);
++ return 0;
++}
++
++static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
++ int write_enable)
++{
++ struct fsl_qspi *q = nor->priv;
++ int ret;
++
++ if (!buf) {
++ ret = fsl_qspi_runcmd(q, opcode, 0, 1);
++ if (ret)
++ return ret;
++
++ if (opcode == SPINOR_OP_CHIP_ERASE)
++ fsl_qspi_invalid(q);
++
++ } else if (len > 0) {
++ ret = fsl_qspi_nor_write(q, nor, opcode, 0,
++ (u32 *)buf, len, NULL);
++ } else {
++ dev_err(q->dev, "invalid cmd %d\n", opcode);
++ ret = -EINVAL;
++ }
++
++ return ret;
++}
++
++static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
++ size_t len, size_t *retlen, const u_char *buf)
++{
++ struct fsl_qspi *q = nor->priv;
++
++ fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
++ (u32 *)buf, len, retlen);
++
++ /* invalid the data in the AHB buffer. */
++ fsl_qspi_invalid(q);
++}
++
++static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
++ size_t len, size_t *retlen, u_char *buf)
++{
++ struct fsl_qspi *q = nor->priv;
++ u8 cmd = nor->read_opcode;
++ int ret;
++
++ /* Wait until the previous command is finished. */
++ ret = nor->wait_till_ready(nor);
++ if (ret)
++ return ret;
++
++ /* if necessary,ioremap buffer before AHB read, */
++ /* generally 4MB should be large enough */
++ if (!q->ahb_addr) {
++ q->ahb_addr = ioremap_nocache(
++ q->memmap_phy + q->chip_base_addr + from,
++ len > SZ_4M ? len : SZ_4M);
++ if (!q->ahb_addr) {
++ dev_err(q->dev, "ioremap failed\n");
++ return -ENOMEM;
++ }
++ q->memmap_offs = q->chip_base_addr + from;
++ q->memmap_len = len > SZ_4M ? len : SZ_4M;
++ /* ioremap if the data requested is out of range */
++ } else if (q->chip_base_addr + from < q->memmap_offs
++ || q->chip_base_addr + from + len >
++ q->memmap_offs + q->memmap_len) {
++ iounmap(q->ahb_addr);
++ q->ahb_addr = ioremap_nocache(
++ q->memmap_phy + q->chip_base_addr + from,
++ len > SZ_4M ? len : SZ_4M);
++ if (!q->ahb_addr) {
++ dev_err(q->dev, "ioremap failed\n");
++ return -ENOMEM;
++ }
++ q->memmap_offs = q->chip_base_addr + from;
++ q->memmap_len = len > SZ_4M ? len : SZ_4M;
++ }
++
++ dev_dbg(q->dev, "cmd [%x],read from 0x%p, len:%d\n",
++ cmd, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
++ len);
++
++ /* Read out the data directly from the AHB buffer.*/
++ memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
++ len);
++
++ *retlen += len;
++
++ return 0;
++}
++
++static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
++{
++ struct fsl_qspi *q = nor->priv;
++ int ret;
++
++ dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
++ nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
++
++ /* Wait until finished previous write command. */
++ ret = nor->wait_till_ready(nor);
++ if (ret)
++ return ret;
++
++ /* Send write enable, then erase commands. */
++ ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
++ if (ret)
++ return ret;
++
++ ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
++ if (ret)
++ return ret;
++
++ fsl_qspi_invalid(q);
++ return 0;
++}
++
++static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
++{
++ struct fsl_qspi *q = nor->priv;
++ int ret;
++
++ mutex_lock(&q->lock);
++
++ ret = fsl_qspi_clk_prep_enable(q);
++ if (ret)
++ return ret;
++
++ fsl_qspi_set_base_addr(q, nor);
++ return 0;
++}
++
++static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
++{
++ struct fsl_qspi *q = nor->priv;
++
++ fsl_qspi_clk_disable_unprep(q);
++ mutex_unlock(&q->lock);
++}
++
++static int fsl_qspi_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct mtd_part_parser_data ppdata;
++ struct device *dev = &pdev->dev;
++ struct fsl_qspi *q;
++ struct resource *res;
++ struct spi_nor *nor;
++ struct mtd_info *mtd;
++ int ret, i = 0;
++ bool has_second_chip = false;
++ const struct of_device_id *of_id =
++ of_match_device(fsl_qspi_dt_ids, &pdev->dev);
++
++ q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
++ if (!q)
++ return -ENOMEM;
++
++ q->nor_num = of_get_child_count(dev->of_node);
++ if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
++ return -ENODEV;
++
++ /* find the resources */
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
++ q->iobase = devm_ioremap_resource(dev, res);
++ if (IS_ERR(q->iobase)) {
++ ret = PTR_ERR(q->iobase);
++ goto map_failed;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++ "QuadSPI-memory");
++ q->memmap_phy = res->start;
++
++ /* find the clocks */
++ q->clk_en = devm_clk_get(dev, "qspi_en");
++ if (IS_ERR(q->clk_en)) {
++ ret = PTR_ERR(q->clk_en);
++ goto map_failed;
++ }
++
++ q->clk = devm_clk_get(dev, "qspi");
++ if (IS_ERR(q->clk)) {
++ ret = PTR_ERR(q->clk);
++ goto map_failed;
++ }
++
++ /* find ddrsmp value */
++ ret = of_property_read_u32(dev->of_node, "ddrsmp",
++ &q->ddr_smp);
++ if (ret)
++ q->ddr_smp = 0;
++
++ ret = fsl_qspi_clk_prep_enable(q);
++ if (ret) {
++ dev_err(dev, "can not enable the clock\n");
++ goto map_failed;
++ }
++
++ /* find the irq */
++ ret = platform_get_irq(pdev, 0);
++ if (ret < 0) {
++ dev_err(dev, "failed to get the irq\n");
++ goto irq_failed;
++ }
++
++ ret = devm_request_irq(dev, ret,
++ fsl_qspi_irq_handler, 0, pdev->name, q);
++ if (ret) {
++ dev_err(dev, "failed to request irq.\n");
++ goto irq_failed;
++ }
++
++ q->dev = dev;
++ q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
++ platform_set_drvdata(pdev, q);
++
++ ret = fsl_qspi_nor_setup(q);
++ if (ret)
++ goto irq_failed;
++
++ if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
++ has_second_chip = true;
++
++ mutex_init(&q->lock);
++
++ /* iterate the subnodes. */
++ for_each_available_child_of_node(dev->of_node, np) {
++ const struct spi_device_id *id;
++ enum read_mode mode = SPI_NOR_QUAD;
++ char modalias[40];
++ u32 dummy = 0;
++
++ /* skip the holes */
++ if (!has_second_chip)
++ i *= 2;
++
++ nor = &q->nor[i];
++ mtd = &q->mtd[i];
++
++ nor->mtd = mtd;
++ nor->dev = dev;
++ nor->np = np;
++ nor->priv = q;
++ mtd->priv = nor;
++
++ /* fill the hooks */
++ nor->read_reg = fsl_qspi_read_reg;
++ nor->write_reg = fsl_qspi_write_reg;
++ nor->read = fsl_qspi_read;
++ nor->write = fsl_qspi_write;
++ nor->erase = fsl_qspi_erase;
++
++ nor->prepare = fsl_qspi_prep;
++ nor->unprepare = fsl_qspi_unprep;
++
++ ret = of_modalias_node(np, modalias, sizeof(modalias));
++ if (ret < 0)
++ goto irq_failed;
++
++ id = spi_nor_match_id(modalias);
++ if (!id) {
++ ret = -EINVAL;
++ goto irq_failed;
++ }
++
++ ret = of_property_read_u32(np, "spi-max-frequency",
++ &q->clk_rate);
++ if (ret < 0)
++ goto irq_failed;
++
++ /* Can we enable the DDR Quad Read? */
++ ret = of_property_read_u32(np, "spi-nor,ddr-quad-read-dummy",
++ &dummy);
++ if (!ret && dummy > 0)
++ mode = SPI_NOR_DDR_QUAD;
++
++ /* set the chip address for READID */
++ fsl_qspi_set_base_addr(q, nor);
++
++ ret = spi_nor_scan(nor, id, mode);
++ if (ret)
++ goto irq_failed;
++
++ ppdata.of_node = np;
++ ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
++ if (ret)
++ goto irq_failed;
++
++ /* Set the correct NOR size now. */
++ if (q->nor_size == 0) {
++ q->nor_size = mtd->size;
++
++ /* Map the SPI NOR to accessiable address */
++ fsl_qspi_set_map_addr(q);
++ }
++
++ /*
++ * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
++ * may writes 265 bytes per time. The write is working in the
++ * unit of the TX FIFO, not in the unit of the SPI NOR's page
++ * size.
++ *
++ * So shrink the spi_nor->page_size if it is larger then the
++ * TX FIFO.
++ */
++ if (nor->page_size > q->devtype_data->txfifo)
++ nor->page_size = q->devtype_data->txfifo;
++
++ i++;
++ }
++
++ /* finish the rest init. */
++ ret = fsl_qspi_nor_setup_last(q);
++ if (ret)
++ goto last_init_failed;
++
++ fsl_qspi_clk_disable_unprep(q);
++ dev_info(dev, "QuadSPI SPI NOR flash driver\n");
++ return 0;
++
++last_init_failed:
++ for (i = 0; i < FSL_QSPI_MAX_CHIP; i++)
++ mtd_device_unregister(&q->mtd[i]);
++
++irq_failed:
++ fsl_qspi_clk_disable_unprep(q);
++map_failed:
++ dev_err(dev, "Freescale QuadSPI probe failed\n");
++ return ret;
++}
++
++static int fsl_qspi_remove(struct platform_device *pdev)
++{
++ struct fsl_qspi *q = platform_get_drvdata(pdev);
++ int i;
++
++ for (i = 0; i < FSL_QSPI_MAX_CHIP; i++)
++ mtd_device_unregister(&q->mtd[i]);
++
++ /* disable the hardware */
++ writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
++ writel(0x0, q->iobase + QUADSPI_RSER);
++
++ if (q->ahb_addr)
++ iounmap(q->ahb_addr);
++
++ return 0;
++}
++
++static int fsl_qspi_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ return 0;
++}
++
++static int fsl_qspi_resume(struct platform_device *pdev)
++{
++ int ret;
++ struct fsl_qspi *q = platform_get_drvdata(pdev);
++
++ ret = fsl_qspi_clk_prep_enable(q);
++ if (ret)
++ return ret;
++
++ fsl_qspi_nor_setup(q);
++ fsl_qspi_set_map_addr(q);
++ fsl_qspi_nor_setup_last(q);
++
++ fsl_qspi_clk_disable_unprep(q);
++
++ return 0;
++}
++
++static struct platform_driver fsl_qspi_driver = {
++ .driver = {
++ .name = "fsl-quadspi",
++ .bus = &platform_bus_type,
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_qspi_dt_ids,
++ },
++ .probe = fsl_qspi_probe,
++ .remove = fsl_qspi_remove,
++ .suspend = fsl_qspi_suspend,
++ .resume = fsl_qspi_resume,
++};
++module_platform_driver(fsl_qspi_driver);
++
++MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
++MODULE_AUTHOR("Freescale Semiconductor Inc.");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/mtd/spi-nor/Kconfig linux-3.14.72/drivers/mtd/spi-nor/Kconfig
+--- linux-3.14.72.orig/drivers/mtd/spi-nor/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mtd/spi-nor/Kconfig 2016-06-19 22:11:55.209146306 +0200
+@@ -0,0 +1,17 @@
++menuconfig MTD_SPI_NOR
++ tristate "SPI-NOR device support"
++ depends on MTD
++ help
++ This is the framework for the SPI NOR which can be used by the SPI
++ device drivers and the SPI-NOR device driver.
++
++if MTD_SPI_NOR
++
++config SPI_FSL_QUADSPI
++ tristate "Freescale Quad SPI controller"
++ depends on ARCH_MXC
++ help
++ This enables support for the Quad SPI controller in master mode.
++ We only connect the NOR to this controller now.
++
++endif # MTD_SPI_NOR
+diff -Nur linux-3.14.72.orig/drivers/mtd/spi-nor/Makefile linux-3.14.72/drivers/mtd/spi-nor/Makefile
+--- linux-3.14.72.orig/drivers/mtd/spi-nor/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mtd/spi-nor/Makefile 2016-06-19 22:11:55.209146306 +0200
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
++obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
+diff -Nur linux-3.14.72.orig/drivers/mtd/spi-nor/spi-nor.c linux-3.14.72/drivers/mtd/spi-nor/spi-nor.c
+--- linux-3.14.72.orig/drivers/mtd/spi-nor/spi-nor.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mtd/spi-nor/spi-nor.c 2016-06-19 22:11:55.209146306 +0200
+@@ -0,0 +1,1182 @@
++/*
++ * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
++ * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
++ *
++ * Copyright (C) 2005, Intec Automation Inc.
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This code is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/mutex.h>
++#include <linux/math64.h>
++
++#include <linux/mtd/cfi.h>
++#include <linux/mtd/mtd.h>
++#include <linux/of_platform.h>
++#include <linux/spi/flash.h>
++#include <linux/mtd/spi-nor.h>
++
++/* Define max times to check status register before we give up. */
++#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
++
++#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
++
++/*
++ * Read the status register, returning its value in the location
++ * Return the status register value.
++ * Returns negative if error occurred.
++ */
++static int read_sr(struct spi_nor *nor)
++{
++ int ret;
++ u8 val;
++
++ ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
++ if (ret < 0) {
++ pr_err("error %d reading SR\n", (int) ret);
++ return ret;
++ }
++
++ return val;
++}
++
++/*
++ * Read configuration register, returning its value in the
++ * location. Return the configuration register value.
++ * Returns negative if error occured.
++ */
++static int read_cr(struct spi_nor *nor)
++{
++ int ret;
++ u8 val;
++
++ ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
++ if (ret < 0) {
++ dev_err(nor->dev, "error %d reading CR\n", ret);
++ return ret;
++ }
++
++ return val;
++}
++
++/*
++ * Dummy Cycle calculation for different type of read.
++ * It can be used to support more commands with
++ * different dummy cycle requirements.
++ */
++static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
++{
++ u32 dummy;
++
++ switch (nor->flash_read) {
++ case SPI_NOR_DDR_QUAD:
++ /*
++ * The m25p80.c can not support the DDR quad read.
++ * We set the dummy cycles to 8 by default. The SPI NOR
++ * controller driver can set it in its child DT node.
++ * We parse it out here.
++ */
++ if (nor->np && !of_property_read_u32(nor->np,
++ "spi-nor,ddr-quad-read-dummy", &dummy)) {
++ return dummy;
++ }
++ case SPI_NOR_FAST:
++ case SPI_NOR_DUAL:
++ case SPI_NOR_QUAD:
++ return 8;
++ case SPI_NOR_NORMAL:
++ return 0;
++ }
++ return 0;
++}
++
++/*
++ * Write status register 1 byte
++ * Returns negative if error occurred.
++ */
++static inline int write_sr(struct spi_nor *nor, u8 val)
++{
++ nor->cmd_buf[0] = val;
++ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
++}
++
++/*
++ * Set write enable latch with Write Enable command.
++ * Returns negative if error occurred.
++ */
++static inline int write_enable(struct spi_nor *nor)
++{
++ return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
++}
++
++/*
++ * Send write disble instruction to the chip.
++ */
++static inline int write_disable(struct spi_nor *nor)
++{
++ return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
++}
++
++static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
++{
++ return mtd->priv;
++}
++
++/* Enable/disable 4-byte addressing mode. */
++static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
++{
++ int status;
++ bool need_wren = false;
++ u8 cmd;
++
++ switch (JEDEC_MFR(jedec_id)) {
++ case CFI_MFR_ST: /* Micron, actually */
++ /* Some Micron need WREN command; all will accept it */
++ need_wren = true;
++ case CFI_MFR_MACRONIX:
++ case 0xEF /* winbond */:
++ if (need_wren)
++ write_enable(nor);
++
++ cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
++ status = nor->write_reg(nor, cmd, NULL, 0, 0);
++ if (need_wren)
++ write_disable(nor);
++
++ return status;
++ default:
++ /* Spansion style */
++ nor->cmd_buf[0] = enable << 7;
++ return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
++ }
++}
++
++static int spi_nor_wait_till_ready(struct spi_nor *nor)
++{
++ unsigned long deadline;
++ int sr;
++
++ deadline = jiffies + MAX_READY_WAIT_JIFFIES;
++
++ do {
++ cond_resched();
++
++ sr = read_sr(nor);
++ if (sr < 0)
++ break;
++ else if (!(sr & SR_WIP))
++ return 0;
++ } while (!time_after_eq(jiffies, deadline));
++
++ return -ETIMEDOUT;
++}
++
++/*
++ * Service routine to read status register until ready, or timeout occurs.
++ * Returns non-zero if error.
++ */
++static int wait_till_ready(struct spi_nor *nor)
++{
++ return nor->wait_till_ready(nor);
++}
++
++/*
++ * Erase the whole flash memory
++ *
++ * Returns 0 if successful, non-zero otherwise.
++ */
++static int erase_chip(struct spi_nor *nor)
++{
++ int ret;
++
++ dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
++
++ /* Wait until finished previous write command. */
++ ret = wait_till_ready(nor);
++ if (ret)
++ return ret;
++
++ /* Send write enable, then erase commands. */
++ write_enable(nor);
++
++ return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
++}
++
++static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
++{
++ int ret = 0;
++
++ mutex_lock(&nor->lock);
++
++ if (nor->prepare) {
++ ret = nor->prepare(nor, ops);
++ if (ret) {
++ dev_err(nor->dev, "failed in the preparation.\n");
++ mutex_unlock(&nor->lock);
++ return ret;
++ }
++ }
++ return ret;
++}
++
++static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
++{
++ if (nor->unprepare)
++ nor->unprepare(nor, ops);
++ mutex_unlock(&nor->lock);
++}
++
++/*
++ * Erase an address range on the nor chip. The address range may extend
++ * one or more erase sectors. Return an error is there is a problem erasing.
++ */
++static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ u32 addr, len;
++ uint32_t rem;
++ int ret;
++
++ dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
++ (long long)instr->len);
++
++ div_u64_rem(instr->len, mtd->erasesize, &rem);
++ if (rem)
++ return -EINVAL;
++
++ addr = instr->addr;
++ len = instr->len;
++
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
++ if (ret)
++ return ret;
++
++ /* whole-chip erase? */
++ if (len == mtd->size) {
++ if (erase_chip(nor)) {
++ ret = -EIO;
++ goto erase_err;
++ }
++
++ /* REVISIT in some cases we could speed up erasing large regions
++ * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
++ * to use "small sector erase", but that's not always optimal.
++ */
++
++ /* "sector"-at-a-time erase */
++ } else {
++ while (len) {
++ if (nor->erase(nor, addr)) {
++ ret = -EIO;
++ goto erase_err;
++ }
++
++ addr += mtd->erasesize;
++ len -= mtd->erasesize;
++ }
++ }
++
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
++
++ instr->state = MTD_ERASE_DONE;
++ mtd_erase_callback(instr);
++
++ return ret;
++
++erase_err:
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
++ instr->state = MTD_ERASE_FAILED;
++ return ret;
++}
++
++static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ uint32_t offset = ofs;
++ uint8_t status_old, status_new;
++ int ret = 0;
++
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
++ if (ret)
++ return ret;
++
++ /* Wait until finished previous command */
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto err;
++
++ status_old = read_sr(nor);
++
++ if (offset < mtd->size - (mtd->size / 2))
++ status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
++ else if (offset < mtd->size - (mtd->size / 4))
++ status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
++ else if (offset < mtd->size - (mtd->size / 8))
++ status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
++ else if (offset < mtd->size - (mtd->size / 16))
++ status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
++ else if (offset < mtd->size - (mtd->size / 32))
++ status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
++ else if (offset < mtd->size - (mtd->size / 64))
++ status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
++ else
++ status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
++
++ /* Only modify protection if it will not unlock other areas */
++ if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
++ (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
++ write_enable(nor);
++ ret = write_sr(nor, status_new);
++ if (ret)
++ goto err;
++ }
++
++err:
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
++ return ret;
++}
++
++static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ uint32_t offset = ofs;
++ uint8_t status_old, status_new;
++ int ret = 0;
++
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
++ if (ret)
++ return ret;
++
++ /* Wait until finished previous command */
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto err;
++
++ status_old = read_sr(nor);
++
++ if (offset+len > mtd->size - (mtd->size / 64))
++ status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
++ else if (offset+len > mtd->size - (mtd->size / 32))
++ status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
++ else if (offset+len > mtd->size - (mtd->size / 16))
++ status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
++ else if (offset+len > mtd->size - (mtd->size / 8))
++ status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
++ else if (offset+len > mtd->size - (mtd->size / 4))
++ status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
++ else if (offset+len > mtd->size - (mtd->size / 2))
++ status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
++ else
++ status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
++
++ /* Only modify protection if it will not lock other areas */
++ if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
++ (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
++ write_enable(nor);
++ ret = write_sr(nor, status_new);
++ if (ret)
++ goto err;
++ }
++
++err:
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
++ return ret;
++}
++
++struct flash_info {
++ /* JEDEC id zero means "no ID" (most older chips); otherwise it has
++ * a high byte of zero plus three data bytes: the manufacturer id,
++ * then a two byte device id.
++ */
++ u32 jedec_id;
++ u32 ext_id;
++
++ /* The size listed here is what works with SPINOR_OP_SE, which isn't
++ * necessarily called a "sector" by the vendor.
++ */
++ unsigned sector_size;
++ u16 n_sectors;
++
++ u16 page_size;
++ u16 addr_width;
++
++ u16 flags;
++#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
++#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
++#define SST_WRITE 0x04 /* use SST byte programming */
++#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
++#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
++#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
++#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
++#define SPI_NOR_DDR_QUAD_READ 0x80 /* Flash supports DDR Quad Read */
++};
++
++#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
++ ((kernel_ulong_t)&(struct flash_info) { \
++ .jedec_id = (_jedec_id), \
++ .ext_id = (_ext_id), \
++ .sector_size = (_sector_size), \
++ .n_sectors = (_n_sectors), \
++ .page_size = 256, \
++ .flags = (_flags), \
++ })
++
++#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
++ ((kernel_ulong_t)&(struct flash_info) { \
++ .sector_size = (_sector_size), \
++ .n_sectors = (_n_sectors), \
++ .page_size = (_page_size), \
++ .addr_width = (_addr_width), \
++ .flags = (_flags), \
++ })
++
++/* NOTE: double check command sets and memory organization when you add
++ * more nor chips. This current list focusses on newer chips, which
++ * have been converging on command sets which including JEDEC ID.
++ */
++const struct spi_device_id spi_nor_ids[] = {
++ /* Atmel -- some are (confusingly) marketed as "DataFlash" */
++ { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
++ { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
++
++ { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
++ { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
++ { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
++
++ { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
++ { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
++ { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
++ { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
++
++ { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
++
++ /* EON -- en25xxx */
++ { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
++ { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
++ { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
++ { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
++ { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
++ { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
++
++ /* ESMT */
++ { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
++
++ /* Everspin */
++ { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
++ { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
++
++ /* GigaDevice */
++ { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
++ { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
++
++ /* Intel/Numonyx -- xxxs33b */
++ { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
++ { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
++ { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
++
++ /* Macronix */
++ { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
++ { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
++ { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
++ { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
++ { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
++ { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
++ { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
++ { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
++ { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
++ { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
++ { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
++ { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
++ { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
++
++ /* Micron */
++ { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
++ { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
++ { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
++ { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_DDR_QUAD_READ) },
++ { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
++
++ /* PMC */
++ { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
++ { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
++ { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
++
++ /* Spansion -- single (large) sector size only, at least
++ * for the chips listed here (without boot sectors).
++ */
++ { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++ { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
++ { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
++ { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++ { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++ { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
++ { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
++ { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
++ { "s25fl128s", INFO(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ | SPI_NOR_DDR_QUAD_READ) },
++ { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
++ { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
++ { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
++ { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
++ { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
++ { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
++ { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
++ { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
++ { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
++ { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
++
++ /* SST -- large erase sizes are "overlays", "sectors" are 4K */
++ { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
++ { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
++ { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
++ { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
++ { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
++ { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
++ { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
++ { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
++ { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
++
++ /* ST Microelectronics -- newer production may have feature updates */
++ { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
++ { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
++ { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
++ { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
++ { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
++ { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
++ { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
++ { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
++ { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
++ { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
++
++ { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
++ { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
++ { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
++ { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
++ { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
++ { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
++ { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
++ { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
++ { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
++
++ { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
++ { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
++ { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
++
++ { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
++ { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
++ { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
++
++ { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
++ { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
++ { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
++ { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
++ { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
++
++ /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
++ { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
++ { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
++ { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
++ { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
++ { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
++ { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
++ { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
++ { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
++ { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
++ { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
++ { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
++ { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
++ { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
++ { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
++ { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
++
++ /* Catalyst / On Semiconductor -- non-JEDEC */
++ { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
++ { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
++ { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
++ { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
++ { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
++ { },
++};
++EXPORT_SYMBOL_GPL(spi_nor_ids);
++
++static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
++{
++ int tmp;
++ u8 id[6];
++ u32 jedec;
++ u32 ext_jedec;
++ struct flash_info *info;
++ int matched = -1;
++
++ tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 6);
++ if (tmp < 0) {
++ dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
++ return ERR_PTR(tmp);
++ }
++ jedec = id[0];
++ jedec = jedec << 8;
++ jedec |= id[1];
++ jedec = jedec << 8;
++ jedec |= id[2];
++
++ ext_jedec = id[3] << 8 | id[4];
++
++ for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
++ info = (void *)spi_nor_ids[tmp].driver_data;
++ if (info->jedec_id == jedec) {
++ if (info->ext_id == 0)
++ return &spi_nor_ids[tmp];
++
++ /* the legacy two bytes ext_id */
++ if ((info->ext_id >> 16) == 0) {
++ if (info->ext_id == ext_jedec)
++ matched = tmp;
++ } else {
++ /* check the sixth byte now */
++ ext_jedec = ext_jedec << 8 | id[5];
++ if (info->ext_id == ext_jedec)
++ return &spi_nor_ids[tmp];
++
++ /* reset back the ext_jedec */
++ ext_jedec >>= 8;
++ }
++ } else {
++ /* shortcut */
++ if (matched != -1)
++ return &spi_nor_ids[matched];
++ }
++ }
++ dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
++ return ERR_PTR(-ENODEV);
++}
++
++static const struct spi_device_id *jedec_probe(struct spi_nor *nor)
++{
++ return nor->read_id(nor);
++}
++
++static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
++ size_t *retlen, u_char *buf)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ int ret;
++
++ dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
++
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
++ if (ret)
++ return ret;
++
++ ret = nor->read(nor, from, len, retlen, buf);
++
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
++ return ret;
++}
++
++static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
++ size_t *retlen, const u_char *buf)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ size_t actual;
++ int ret;
++
++ dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
++
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
++ if (ret)
++ return ret;
++
++ /* Wait until finished previous write command. */
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto time_out;
++
++ write_enable(nor);
++
++ nor->sst_write_second = false;
++
++ actual = to % 2;
++ /* Start write from odd address. */
++ if (actual) {
++ nor->program_opcode = SPINOR_OP_BP;
++
++ /* write one byte. */
++ nor->write(nor, to, 1, retlen, buf);
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto time_out;
++ }
++ to += actual;
++
++ /* Write out most of the data here. */
++ for (; actual < len - 1; actual += 2) {
++ nor->program_opcode = SPINOR_OP_AAI_WP;
++
++ /* write two bytes. */
++ nor->write(nor, to, 2, retlen, buf + actual);
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto time_out;
++ to += 2;
++ nor->sst_write_second = true;
++ }
++ nor->sst_write_second = false;
++
++ write_disable(nor);
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto time_out;
++
++ /* Write out trailing byte if it exists. */
++ if (actual != len) {
++ write_enable(nor);
++
++ nor->program_opcode = SPINOR_OP_BP;
++ nor->write(nor, to, 1, retlen, buf + actual);
++
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto time_out;
++ write_disable(nor);
++ }
++time_out:
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
++ return ret;
++}
++
++/*
++ * Write an address range to the nor chip. Data must be written in
++ * FLASH_PAGESIZE chunks. The address range may be any size provided
++ * it is within the physical boundaries.
++ */
++static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
++ size_t *retlen, const u_char *buf)
++{
++ struct spi_nor *nor = mtd_to_spi_nor(mtd);
++ u32 page_offset, page_size, i;
++ int ret;
++
++ dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
++
++ ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
++ if (ret)
++ return ret;
++
++ /* Wait until finished previous write command. */
++ ret = wait_till_ready(nor);
++ if (ret)
++ goto write_err;
++
++ write_enable(nor);
++
++ page_offset = to & (nor->page_size - 1);
++
++ /* do all the bytes fit onto one page? */
++ if (page_offset + len <= nor->page_size) {
++ nor->write(nor, to, len, retlen, buf);
++ } else {
++ /* the size of data remaining on the first page */
++ page_size = nor->page_size - page_offset;
++ nor->write(nor, to, page_size, retlen, buf);
++
++ /* write everything in nor->page_size chunks */
++ for (i = page_size; i < len; i += page_size) {
++ page_size = len - i;
++ if (page_size > nor->page_size)
++ page_size = nor->page_size;
++
++ wait_till_ready(nor);
++ write_enable(nor);
++
++ nor->write(nor, to + i, page_size, retlen, buf + i);
++ }
++ }
++
++write_err:
++ spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
++ return 0;
++}
++
++static int macronix_quad_enable(struct spi_nor *nor)
++{
++ int ret, val;
++
++ val = read_sr(nor);
++ write_enable(nor);
++
++ nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
++ nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
++
++ if (wait_till_ready(nor))
++ return 1;
++
++ ret = read_sr(nor);
++ if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
++ dev_err(nor->dev, "Macronix Quad bit not set\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * Write status Register and configuration register with 2 bytes
++ * The first byte will be written to the status register, while the
++ * second byte will be written to the configuration register.
++ * Return negative if error occured.
++ */
++static int write_sr_cr(struct spi_nor *nor, u16 val)
++{
++ nor->cmd_buf[0] = val & 0xff;
++ nor->cmd_buf[1] = (val >> 8);
++
++ return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
++}
++
++static int spansion_quad_enable(struct spi_nor *nor)
++{
++ int ret;
++ int quad_en = CR_QUAD_EN_SPAN << 8;
++
++ write_enable(nor);
++
++ ret = write_sr_cr(nor, quad_en);
++ if (ret < 0) {
++ dev_err(nor->dev,
++ "error while writing configuration register\n");
++ return -EINVAL;
++ }
++
++ /* read back and check it */
++ ret = read_cr(nor);
++ if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
++ dev_err(nor->dev, "Spansion Quad bit not set\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int set_ddr_quad_mode(struct spi_nor *nor, u32 jedec_id)
++{
++ int status;
++
++ switch (JEDEC_MFR(jedec_id)) {
++ case CFI_MFR_AMD: /* Spansion, actually */
++ status = spansion_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev,
++ "Spansion DDR quad-read not enabled\n");
++ return status;
++ }
++ return status;
++ case CFI_MFR_ST: /* Micron, actually */
++ /* DTR quad read works with the Extended SPI protocol. */
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
++{
++ int status;
++
++ switch (JEDEC_MFR(jedec_id)) {
++ case CFI_MFR_MACRONIX:
++ status = macronix_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev, "Macronix quad-read not enabled\n");
++ return -EINVAL;
++ }
++ return status;
++ default:
++ status = spansion_quad_enable(nor);
++ if (status) {
++ dev_err(nor->dev, "Spansion quad-read not enabled\n");
++ return -EINVAL;
++ }
++ return status;
++ }
++}
++
++static int spi_nor_check(struct spi_nor *nor)
++{
++ if (!nor->dev || !nor->read || !nor->write ||
++ !nor->read_reg || !nor->write_reg || !nor->erase) {
++ pr_err("spi-nor: please fill all the necessary fields!\n");
++ return -EINVAL;
++ }
++
++ if (!nor->read_id)
++ nor->read_id = spi_nor_read_id;
++ if (!nor->wait_till_ready)
++ nor->wait_till_ready = spi_nor_wait_till_ready;
++
++ return 0;
++}
++
++int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
++ enum read_mode mode)
++{
++ struct flash_info *info;
++ struct flash_platform_data *data;
++ struct device *dev = nor->dev;
++ struct mtd_info *mtd = nor->mtd;
++ struct device_node *np = nor->np;
++ int ret;
++ int i;
++
++ ret = spi_nor_check(nor);
++ if (ret)
++ return ret;
++
++ /* Platform data helps sort out which chip type we have, as
++ * well as how this board partitions it. If we don't have
++ * a chip ID, try the JEDEC id commands; they'll work for most
++ * newer chips, even if we don't recognize the particular chip.
++ */
++ data = dev_get_platdata(dev);
++ if (data && data->type) {
++ const struct spi_device_id *plat_id;
++
++ for (i = 0; i < ARRAY_SIZE(spi_nor_ids) - 1; i++) {
++ plat_id = &spi_nor_ids[i];
++ if (strcmp(data->type, plat_id->name))
++ continue;
++ break;
++ }
++
++ if (i < ARRAY_SIZE(spi_nor_ids) - 1)
++ id = plat_id;
++ else
++ dev_warn(dev, "unrecognized id %s\n", data->type);
++ }
++
++ info = (void *)id->driver_data;
++
++ if (info->jedec_id) {
++ const struct spi_device_id *jid;
++
++ jid = jedec_probe(nor);
++ if (IS_ERR(jid)) {
++ return PTR_ERR(jid);
++ } else if (jid != id) {
++ /*
++ * JEDEC knows better, so overwrite platform ID. We
++ * can't trust partitions any longer, but we'll let
++ * mtd apply them anyway, since some partitions may be
++ * marked read-only, and we don't want to lose that
++ * information, even if it's not 100% accurate.
++ */
++ dev_warn(dev, "found %s, expected %s\n",
++ jid->name, id->name);
++ id = jid;
++ info = (void *)jid->driver_data;
++ }
++ }
++
++ mutex_init(&nor->lock);
++
++ /*
++ * Atmel, SST and Intel/Numonyx serial nor tend to power
++ * up with the software protection bits set
++ */
++
++ if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
++ JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
++ JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
++ write_enable(nor);
++ write_sr(nor, 0);
++ }
++
++ if (data && data->name)
++ mtd->name = data->name;
++ else
++ mtd->name = dev_name(dev);
++
++ mtd->type = MTD_NORFLASH;
++ mtd->writesize = 1;
++ mtd->flags = MTD_CAP_NORFLASH;
++ mtd->size = info->sector_size * info->n_sectors;
++ mtd->_erase = spi_nor_erase;
++ mtd->_read = spi_nor_read;
++
++ /* nor protection support for STmicro chips */
++ if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
++ mtd->_lock = spi_nor_lock;
++ mtd->_unlock = spi_nor_unlock;
++ }
++
++ /* sst nor chips use AAI word program */
++ if (info->flags & SST_WRITE)
++ mtd->_write = sst_write;
++ else
++ mtd->_write = spi_nor_write;
++
++ /* prefer "small sector" erase if possible */
++ if (info->flags & SECT_4K) {
++ nor->erase_opcode = SPINOR_OP_BE_4K;
++ mtd->erasesize = 4096;
++ } else if (info->flags & SECT_4K_PMC) {
++ nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
++ mtd->erasesize = 4096;
++ } else {
++ nor->erase_opcode = SPINOR_OP_SE;
++ mtd->erasesize = info->sector_size;
++ }
++
++ if (info->flags & SPI_NOR_NO_ERASE)
++ mtd->flags |= MTD_NO_ERASE;
++
++ mtd->dev.parent = dev;
++ nor->page_size = info->page_size;
++ mtd->writebufsize = nor->page_size;
++
++ if (np) {
++ /* If we were instantiated by DT, use it */
++ if (of_property_read_bool(np, "m25p,fast-read"))
++ nor->flash_read = SPI_NOR_FAST;
++ else
++ nor->flash_read = SPI_NOR_NORMAL;
++ } else {
++ /* If we weren't instantiated by DT, default to fast-read */
++ nor->flash_read = SPI_NOR_FAST;
++ }
++
++ /* Some devices cannot do fast-read, no matter what DT tells us */
++ if (info->flags & SPI_NOR_NO_FR)
++ nor->flash_read = SPI_NOR_NORMAL;
++
++ /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
++ if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
++ ret = set_ddr_quad_mode(nor, info->jedec_id);
++ if (ret) {
++ dev_err(dev, "DDR quad mode not supported\n");
++ return ret;
++ }
++ nor->flash_read = SPI_NOR_DDR_QUAD;
++ } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
++ ret = set_quad_mode(nor, info->jedec_id);
++ if (ret) {
++ dev_err(dev, "quad mode not supported\n");
++ return ret;
++ }
++ nor->flash_read = SPI_NOR_QUAD;
++ } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
++ nor->flash_read = SPI_NOR_DUAL;
++ }
++
++ /* Default commands */
++ switch (nor->flash_read) {
++ case SPI_NOR_DDR_QUAD:
++ if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) { /* Spansion */
++ nor->read_opcode = SPINOR_OP_READ_1_4_4_D;
++ } else if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
++ nor->read_opcode = SPINOR_OP_READ_1_1_4_D;
++ } else {
++ dev_err(dev, "DDR Quad Read is not supported.\n");
++ return -EINVAL;
++ }
++ break;
++ case SPI_NOR_QUAD:
++ nor->read_opcode = SPINOR_OP_READ_1_1_4;
++ break;
++ case SPI_NOR_DUAL:
++ nor->read_opcode = SPINOR_OP_READ_1_1_2;
++ break;
++ case SPI_NOR_FAST:
++ nor->read_opcode = SPINOR_OP_READ_FAST;
++ break;
++ case SPI_NOR_NORMAL:
++ nor->read_opcode = SPINOR_OP_READ;
++ break;
++ default:
++ dev_err(dev, "No Read opcode defined\n");
++ return -EINVAL;
++ }
++
++ nor->program_opcode = SPINOR_OP_PP;
++
++ if (info->addr_width)
++ nor->addr_width = info->addr_width;
++ else if (mtd->size > 0x1000000) {
++ /* enable 4-byte addressing if the device exceeds 16MiB */
++ nor->addr_width = 4;
++ if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
++ /* Dedicated 4-byte command set */
++ switch (nor->flash_read) {
++ case SPI_NOR_DDR_QUAD:
++ nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
++ break;
++ case SPI_NOR_QUAD:
++ nor->read_opcode = SPINOR_OP_READ4_1_1_4;
++ break;
++ case SPI_NOR_DUAL:
++ nor->read_opcode = SPINOR_OP_READ4_1_1_2;
++ break;
++ case SPI_NOR_FAST:
++ nor->read_opcode = SPINOR_OP_READ4_FAST;
++ break;
++ case SPI_NOR_NORMAL:
++ nor->read_opcode = SPINOR_OP_READ4;
++ break;
++ }
++ nor->program_opcode = SPINOR_OP_PP_4B;
++ /* No small sector erase for 4-byte command set */
++ nor->erase_opcode = SPINOR_OP_SE_4B;
++ mtd->erasesize = info->sector_size;
++ } else
++ set_4byte(nor, info->jedec_id, 1);
++ } else {
++ nor->addr_width = 3;
++ }
++
++ nor->read_dummy = spi_nor_read_dummy_cycles(nor);
++
++ dev_info(dev, "%s (%lld Kbytes)\n", id->name,
++ (long long)mtd->size >> 10);
++
++ dev_dbg(dev,
++ "mtd .name = %s, .size = 0x%llx (%lldMiB), "
++ ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
++ mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
++ mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
++
++ if (mtd->numeraseregions)
++ for (i = 0; i < mtd->numeraseregions; i++)
++ dev_dbg(dev,
++ "mtd.eraseregions[%d] = { .offset = 0x%llx, "
++ ".erasesize = 0x%.8x (%uKiB), "
++ ".numblocks = %d }\n",
++ i, (long long)mtd->eraseregions[i].offset,
++ mtd->eraseregions[i].erasesize,
++ mtd->eraseregions[i].erasesize / 1024,
++ mtd->eraseregions[i].numblocks);
++ return 0;
++}
++EXPORT_SYMBOL_GPL(spi_nor_scan);
++
++const struct spi_device_id *spi_nor_match_id(char *name)
++{
++ const struct spi_device_id *id = spi_nor_ids;
++
++ while (id->name[0]) {
++ if (!strcmp(name, id->name))
++ return id;
++ id++;
++ }
++ return NULL;
++}
++EXPORT_SYMBOL_GPL(spi_nor_match_id);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
++MODULE_AUTHOR("Mike Lavender");
++MODULE_DESCRIPTION("framework for SPI NOR");
+diff -Nur linux-3.14.72.orig/drivers/mtd/ubi/build.c linux-3.14.72/drivers/mtd/ubi/build.c
+--- linux-3.14.72.orig/drivers/mtd/ubi/build.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/mtd/ubi/build.c 2016-06-19 22:11:55.209146306 +0200
+@@ -640,7 +640,7 @@
+ dbg_gen("sizeof(struct ubi_ainf_peb) %zu", sizeof(struct ubi_ainf_peb));
+ dbg_gen("sizeof(struct ubi_wl_entry) %zu", sizeof(struct ubi_wl_entry));
+
+- if (ubi->mtd->numeraseregions != 0) {
++ if (ubi->mtd->numeraseregions > 1) {
+ /*
+ * Some flashes have several erase regions. Different regions
+ * may have different eraseblock size and other
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/config linux-3.14.72/drivers/mxc/gpu-viv/config
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/config 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/config 2016-06-19 22:11:55.209146306 +0200
+@@ -0,0 +1,36 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2014 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++ARCH_TYPE ?= arm
++SDK_DIR ?= $(AQROOT)/build/sdk
++VIVANTE_ENABLE_3D ?= 1
++VIVANTE_ENABLE_2D ?= 1
++VIVANTE_ENABLE_VG ?= 1
++FORCE_ALL_VIDEO_MEMORY_CACHED ?= 0
++NONPAGED_MEMORY_CACHEABLE ?= 0
++NONPAGED_MEMORY_BUFFERABLE ?= 1
++CACHE_FUNCTION_UNIMPLEMENTED ?= 0
++ENABLE_OUTER_CACHE_PATCH ?= 1
++USE_BANK_ALIGNMENT ?= 1
++BANK_BIT_START ?= 13
++BANK_BIT_END ?= 15
++BANK_CHANNEL_BIT ?= 12
++PLATFORM ?= freescale/gc_hal_kernel_platform_imx6q14
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.c 2016-06-19 22:11:55.213146043 +0200
+@@ -0,0 +1,2317 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++#include "gc_hal_kernel_buffer.h"
++
++/******************************************************************************\
++******************************** Debugging Macro *******************************
++\******************************************************************************/
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++
++/******************************************************************************\
++************************** Context State Buffer Helpers ************************
++\******************************************************************************/
++
++#define _STATE(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT(reg, count) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_COUNT_OFFSET(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _STATE_MIRROR_COUNT(reg, mirror, count) \
++ _StateMirror(\
++ Context, \
++ reg ## _Address >> 2, \
++ count, \
++ mirror ## _Address >> 2 \
++ )
++
++#define _STATE_HINT(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_HINT_BLOCK(reg, block, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + (block << reg ## _BLK), \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_COUNT_OFFSET_HINT(reg, offset, count) \
++ _State(\
++ Context, index, \
++ (reg ## _Address >> 2) + offset, \
++ reg ## _ResetValue, \
++ count, \
++ gcvFALSE, gcvTRUE \
++ )
++
++#define _STATE_X(reg) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ reg ## _ResetValue, \
++ reg ## _Count, \
++ gcvTRUE, gcvFALSE \
++ )
++
++#define _STATE_INIT_VALUE(reg, value) \
++ _State(\
++ Context, index, \
++ reg ## _Address >> 2, \
++ value, \
++ reg ## _Count, \
++ gcvFALSE, gcvFALSE \
++ )
++
++#define _CLOSE_RANGE() \
++ _TerminateStateBlock(Context, index)
++
++#define _ENABLE(reg, field) \
++ do \
++ { \
++ if (gcmVERIFYFIELDVALUE(data, reg, MASK_ ## field, ENABLED)) \
++ { \
++ enable |= gcmFIELDMASK(reg, field); \
++ } \
++ } \
++ while (gcvFALSE)
++
++#define _BLOCK_COUNT(reg) \
++ ((reg ## _Count) >> (reg ## _BLK))
++
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++#define gcdSTATE_MASK \
++ (((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 | 0xC0FFEE & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))))
++
++#if gcdENABLE_3D
++static gctUINT32
++_TerminateStateBlock(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 align;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ /* Flush the current state block; make sure no pairing with the states
++ to follow happens. */
++ if (align && (buffer != gcvNULL))
++ {
++ buffer[Index] = 0xDEADDEAD;
++ }
++
++ /* Reset last address. */
++ Context->lastAddress = ~0U;
++
++ /* Return alignment requirement. */
++ return align;
++}
++#endif
++
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gctUINT32
++_FlushPipe(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ gctBOOL fcFlushStall;
++ gctUINT32 flushSlots;
++ gctBOOL iCacheInvalidate;
++
++ fcFlushStall
++ = gckHARDWARE_IsFeatureAvailable(Context->hardware, gcvFEATURE_FC_FLUSH_STALL);
++
++ iCacheInvalidate
++ = ((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ flushSlots = 6;
++
++ if (fcFlushStall)
++ {
++ /* Flush tile status cache. */
++ flushSlots += 6;
++ }
++
++ if (iCacheInvalidate)
++ {
++ flushSlots += 12;
++ }
++
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Flush the current pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ if (fcFlushStall)
++ {
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ if (iCacheInvalidate)
++ {
++ /* Invalidate I$ after pipe is stalled */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ }
++
++ /* Number of slots taken by flushing pipe. */
++ return flushSlots;
++}
++#endif
++
++#if gcdENABLE_3D
++static gctUINT32
++_SemaphoreStall(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index
++ )
++{
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ /* Semaphore/stall takes 4 slots. */
++ return 4;
++}
++#endif
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gctUINT32
++_SwitchPipe(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gcePIPE_SELECT Pipe
++ )
++{
++ gctUINT32 slots = 6;
++
++ if (Context->buffer != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Address correct index. */
++ buffer = Context->buffer->logical + Index;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ /* Semaphore from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall from FE to PE. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ Context->pipeSelectBytes = slots * gcmSIZEOF(gctUINT32);
++
++ return slots;
++}
++#endif
++
++#if gcdENABLE_3D
++static gctUINT32
++_State(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Index,
++ IN gctUINT32 Address,
++ IN gctUINT32 Value,
++ IN gctUINT32 Size,
++ IN gctBOOL FixedPoint,
++ IN gctBOOL Hinted
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 align;
++ gctUINT32 i;
++
++ /* Determine if we need alignment. */
++ align = (Index & 1) ? 1 : 0;
++
++ /* Address correct index. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++ if ((buffer == gcvNULL) && (Address + Size > Context->stateCount))
++ {
++ /* Determine maximum state. */
++ Context->stateCount = Address + Size;
++ }
++
++ /* Do we need a new entry? */
++ if ((Address != Context->lastAddress) || (FixedPoint != Context->lastFixed))
++ {
++ if (buffer != gcvNULL)
++ {
++ if (align)
++ {
++ /* Add filler. */
++ buffer[Index++] = 0xDEADDEAD;
++ }
++
++ /* LoadState(Address, Count). */
++ gcmkASSERT((Index & 1) == 0);
++
++ if (FixedPoint)
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++ else
++ {
++ buffer[Index]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ /* Walk all the states. */
++ for (i = 0; i < (gctUINT32)Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + 1 + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = (gctUINT)Index + 1 + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Save information for this LoadState. */
++ Context->lastIndex = (gctUINT)Index;
++ Context->lastAddress = Address + (gctUINT32)Size;
++ Context->lastSize = Size;
++ Context->lastFixed = FixedPoint;
++
++ /* Return size for load state. */
++ return align + 1 + Size;
++ }
++
++ /* Append this state to the previous one. */
++ if (buffer != gcvNULL)
++ {
++ /* Update last load state. */
++ buffer[Context->lastIndex] =
++ ((((gctUINT32) (buffer[Context->lastIndex])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Context->lastSize + Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Walk all the states. */
++ for (i = 0; i < (gctUINT32)Size; i += 1)
++ {
++ /* Set state to uninitialized value. */
++ buffer[Index + i] = Value;
++
++ /* Set index in state mapping table. */
++ Context->map[Address + i].index = (gctUINT)Index + i;
++
++#if gcdSECURE_USER
++ /* Save hint. */
++ if (Context->hint != gcvNULL)
++ {
++ Context->hint[Address + i] = Hinted;
++ }
++#endif
++ }
++ }
++
++ /* Update last address and size. */
++ Context->lastAddress += (gctUINT32)Size;
++ Context->lastSize += Size;
++
++ /* Return number of slots required. */
++ return Size;
++}
++
++static gctUINT32
++_StateMirror(
++ IN gckCONTEXT Context,
++ IN gctUINT32 Address,
++ IN gctUINT32 Size,
++ IN gctUINT32 AddressMirror
++ )
++{
++ gctUINT32 i;
++
++ /* Process when buffer is set. */
++ if (Context->buffer != gcvNULL)
++ {
++ /* Walk all states. */
++ for (i = 0; i < Size; i++)
++ {
++ /* Copy the mapping address. */
++ Context->map[Address + i].index =
++ Context->map[AddressMirror + i].index;
++ }
++ }
++
++ /* Return the number of required maps. */
++ return Size;
++}
++#endif
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++static gceSTATUS
++_InitializeContextBuffer(
++ IN gckCONTEXT Context
++ )
++{
++ gctUINT32_PTR buffer;
++ gctUINT32 index;
++
++#if gcdENABLE_3D
++ gctBOOL halti0, halti1, halti2, halti3;
++ gctUINT i;
++ gctUINT vertexUniforms, fragmentUniforms, vsConstBase, psConstBase, constMax;
++ gctBOOL unifiedUniform;
++ gctUINT fe2vsCount;
++#endif
++
++ /* Reset the buffer index. */
++ index = 0;
++
++ /* Reset the last state address. */
++ Context->lastAddress = ~0U;
++
++ /* Get the buffer pointer. */
++ buffer = (Context->buffer == gcvNULL)
++ ? gcvNULL
++ : Context->buffer->logical;
++
++
++ /**************************************************************************/
++ /* Build 2D states. *******************************************************/
++
++
++#if gcdENABLE_3D
++ /**************************************************************************/
++ /* Build 3D states. *******************************************************/
++
++ halti0 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) );
++ halti1 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) );
++ halti2 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) );
++ halti3 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures5)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) );
++
++ /* Query how many uniforms can support for non-unified uniform mode. */
++ {if (Context->hardware->identity.numConstants > 256){ unifiedUniform = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; constMax = Context->hardware->identity.numConstants; vertexUniforms = 256; fragmentUniforms = constMax - vertexUniforms;}else if (Context->hardware->identity.numConstants == 256){ if (Context->hardware->identity.chipModel == gcv2000 && Context->hardware->identity.chipRevision == 0x5118) { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 64; constMax = 320; } else { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 256; constMax = 512; }}else{ unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 168; fragmentUniforms = 64; constMax = 232;}};
++
++#if !gcdENABLE_UNIFIED_CONSTANT
++ if (Context->hardware->identity.numConstants > 256)
++ {
++ unifiedUniform = gcvTRUE;
++ }
++ else
++ {
++ unifiedUniform = gcvFALSE;
++ }
++#endif
++
++ /* Store the 3D entry index. */
++ Context->entryOffset3D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Current context pointer. */
++#if gcdDEBUG
++ index += _State(Context, index, 0x03850 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ index += _FlushPipe(Context, index, gcvPIPE_3D);
++
++ /* Global states. */
++ index += _State(Context, index, 0x03814 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03818 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0381C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03820 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03828 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0382C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03834 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03854 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0384C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Front End states. */
++ fe2vsCount = 12;
++ if (halti0)
++ {
++ fe2vsCount = 16;
++ }
++ index += _State(Context, index, 0x00600 >> 2, 0x00000000, fe2vsCount, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x00644 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00648 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0064C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x00650 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00680 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x006A0 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0067C >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x006C0 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00700 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00740 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00780 >> 2, 0x3F800000, 16, gcvFALSE, gcvFALSE);
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x14600 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14640 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14680 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ }
++
++ /* This register is programed by all chips, which program all DECODE_SELECT as VS
++ ** except SAMPLER_DECODE_SELECT.
++ */
++ index += _State(Context, index, 0x00860 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ /* I-Cache states. */
++ index += _State(Context, index, 0x00868 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0086C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0304C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01028 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x00890 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0104C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++ }
++ }
++
++ /* Vertex Shader states. */
++ index += _State(Context, index, 0x00804 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00808 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0080C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00810 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00820 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00830 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++
++ /* Primitive Assembly states. */
++ index += _State(Context, index, 0x00A00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A0C >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A10 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A1C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A28 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A2C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A30 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A40 >> 2, 0x00000000, Context->hardware->identity.varyingsCount, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A34 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A38 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A3C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A80 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00A8C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00A88 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++#if gcdMULTI_GPU
++ index += _State(Context, index, 0x03A00 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03A04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x03A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++ /* Setup states. */
++ index += _State(Context, index, 0x00C00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C08 >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C0C >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C10 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C1C >> 2, 0x42000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00C20 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++ index += _State(Context, index, 0x00C24 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE);
++
++ /* Raster states. */
++ index += _State(Context, index, 0x00E00 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E10 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E40 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E08 >> 2, 0x00000031, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E24 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00E20 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x00E0C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ /* Pixel Shader states. */
++ index += _State(Context, index, 0x01004 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0100C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01010 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++
++ /* Texture states. */
++ index += _State(Context, index, 0x02000 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02040 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02080 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x020C0 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02100 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02140 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02180 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x021C0 >> 2, 0x00321000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02200 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x02240 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x02400 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02440 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02480 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x024C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02500 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02540 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02580 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x025C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02600 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02640 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02680 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x026C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02700 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x02740 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 22:22)) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) ))
++ {
++ /*
++ * Linear stride LODn will overwrite LOD0 on GC880,GC2000.
++ * And only LOD0 is valid for this register.
++ */
++ gctUINT count = halti1 ? 14 : 1;
++
++ for (i = 0; i < 12; i += 1)
++ {
++ index += _State(Context, index, (0x02C00 >> 2) + i * 16, 0x00000000, count, gcvFALSE, gcvFALSE);
++ }
++ }
++
++ if (halti1)
++ {
++ gctUINT texBlockCount;
++ gctUINT gcregTXLogSizeResetValue;
++
++ /* Enable the integer filter pipe for all texture samplers
++ so that the floating point filter clock will shut off until
++ we start using the floating point filter.
++ */
++ gcregTXLogSizeResetValue = ((((gctUINT32) (0x00000000)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29)));
++
++ /* New texture block. */
++ index += _State(Context, index, 0x10000 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10080 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10100 >> 2, gcregTXLogSizeResetValue, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10180 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10200 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10280 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10300 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10380 >> 2, 0x00321000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10400 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10480 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 15:15)) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x12000 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x12400 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE);
++ }
++
++ texBlockCount = ((512) >> (4));
++
++ for (i = 0; i < texBlockCount; i += 1)
++ {
++ index += _State(Context, index, (0x10800 >> 2) + (i << 4), 0x00000000, 14, gcvFALSE, gcvTRUE);
++ }
++ }
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x10700 >> 2, 0x00000F00, 32, gcvFALSE, gcvFALSE);
++ }
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x10780 >> 2, 0x00030000, 32, gcvFALSE, gcvFALSE);
++ }
++
++ /* ASTC */
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 13:13)) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) ))
++ {
++ index += _State(Context, index, 0x10500 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10580 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10600 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x10680 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE);
++ }
++
++ /* YUV. */
++ index += _State(Context, index, 0x01678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0167C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01680 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01684 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01688 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0168C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01690 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01694 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01698 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0169C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* Thread walker states. */
++ index += _State(Context, index, 0x00900 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00904 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00908 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0090C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00910 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00914 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00918 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0091C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00924 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ index += _State(Context, index, 0x00940 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00944 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00948 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0094C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00950 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00954 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++
++ if (!halti3)
++ {
++ if (Context->hardware->identity.instructionCount > 1024)
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x20000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ else if (Context->hardware->identity.instructionCount > 256)
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ /* VX instruction memory. */
++ for (i = 0;
++ i < Context->hardware->identity.instructionCount << 2;
++ i += 256 << 2
++ )
++ {
++ index += _State(Context, index, (0x0C000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ _StateMirror(Context, 0x08000 >> 2, Context->hardware->identity.instructionCount << 2 , 0x0C000 >> 2);
++ }
++ else /* if (Context->hardware->identity.instructionCount <= 256) */
++ {
++ /* old shader instruction PC registers */
++ index += _State(Context, index, 0x00800 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x01000 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01018 >> 2, 0x01000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ index += _State(Context, index, 0x04000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x06000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++ }
++ /* I cache use the new instruction PC registers */
++ else
++ {
++ /* New Shader instruction PC registers. */
++ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ if (unifiedUniform)
++ {
++ gctINT numConstants = Context->hardware->identity.numConstants;
++
++ index += _State(Context, index, 0x01024 >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x00864 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ for (i = 0;
++ numConstants > 0;
++ i += 256 << 2,
++ numConstants -= 256
++ )
++ {
++ if (numConstants >= 256)
++ {
++ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, numConstants << 2, gcvFALSE, gcvFALSE);
++ }
++ index += _CLOSE_RANGE();
++ }
++ }
++#if gcdENABLE_UNIFIED_CONSTANT
++ else
++#endif
++ {
++ index += _State(Context, index, 0x05000 >> 2, 0x00000000, vertexUniforms * 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x07000 >> 2, 0x00000000, fragmentUniforms * 4, gcvFALSE, gcvFALSE);
++ }
++
++ /* Store the index of the "XD" entry. */
++ Context->entryOffsetXDFrom3D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++
++ /* Pixel Engine states. */
++ index += _State(Context, index, 0x01400 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01404 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01408 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0140C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01414 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01418 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0141C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01420 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01424 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01428 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0142C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01434 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01454 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01458 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0145C >> 2, 0x00000010, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A8 >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014AC >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014A4 >> 2, 0x000E400C, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01580 >> 2, 0x00000000, 3, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x014B8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ /* Composition states. */
++ index += _State(Context, index, 0x03008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ if (Context->hardware->identity.pixelPipes == 1)
++ {
++ index += _State(Context, index, 0x01460 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01430 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01410 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ }
++ else
++ {
++ index += _State(Context, index, (0x01460 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ if (Context->hardware->identity.pixelPipes > 1 || halti0)
++ {
++ index += _State(Context, index, (0x01480 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ for (i = 0; i < 3; i++)
++ {
++ index += _State(Context, index, (0x01500 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++
++ if (halti2)
++ {
++ for (i = 0; i < 7; i++)
++ {
++ index += _State(Context, index, (0x14800 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++ }
++ index += _State(Context, index, 0x14900 >> 2, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ }
++
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x014BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ }
++
++ /* Resolve states. */
++ index += _State(Context, index, 0x01604 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01608 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0160C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01610 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01614 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01620 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01630 >> 2, 0x00000000, 2, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01640 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x0163C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++
++ if ((Context->hardware->identity.pixelPipes > 1) || halti1)
++ {
++ index += _State(Context, index, (0x016C0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, (0x016E0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE);
++
++ index += _State(Context, index, 0x01700 >> 2, 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvFALSE);
++ }
++
++#if gcd3DBLIT
++ index += _State(Context, index, (0x14000 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1400C >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14010 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14014 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x14018 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14020 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x14024 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14028 >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1402C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14034 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14038 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1403C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14040 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14044 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14048 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1404C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14050 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14058 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1405C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14054 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14100 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14200 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14064 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14068 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _State(Context, index, 0x1406C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14070 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14074 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14078 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1407C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14080 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14084 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14088 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x1408C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14090 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++
++ index += _State(Context, index, 0x14094 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x14098 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++#endif
++
++ /* Tile status. */
++ index += _State(Context, index, 0x01654 >> 2, 0x00200000, 1, gcvFALSE, gcvFALSE);
++
++ index += _CLOSE_RANGE();
++ index += _State(Context, index, 0x01658 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0165C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01660 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01664 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01668 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x0166C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A4 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x016AC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016A8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01720 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x01740 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, 0x01760 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++
++
++ if (halti2)
++ {
++ index += _State(Context, index, 0x01780 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, 0x016BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x017A0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x017C0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x017E0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE);
++ index += _State(Context, index, (0x01A00 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x01A20 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ index += _State(Context, index, (0x01A40 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE);
++ }
++
++ index += _CLOSE_RANGE();
++
++ if(((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 25:25) & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1))))))))
++ {
++ index += _State(Context, index, 0x03860 >> 2, 0x6, 1, gcvFALSE, gcvFALSE);
++ index += _CLOSE_RANGE();
++ }
++
++ if (halti3)
++ {
++ index += _State(Context, index, 0x01A80 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE);
++ index += _CLOSE_RANGE();
++ }
++
++ /* Semaphore/stall. */
++ index += _SemaphoreStall(Context, index);
++#endif
++
++ /**************************************************************************/
++ /* Link to another address. ***********************************************/
++
++ Context->linkIndex3D = (gctUINT)index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++ /* Store the end of the context buffer. */
++ Context->bufferSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /**************************************************************************/
++ /* Pipe switch for the case where neither 2D nor 3D are used. *************/
++
++ /* Store the 3D entry index. */
++ Context->entryOffsetXDFrom2D = (gctUINT)index * gcmSIZEOF(gctUINT32);
++
++ /* Flush 2D pipe. */
++ index += _FlushPipe(Context, index, gcvPIPE_2D);
++
++ /* Switch to 3D pipe. */
++ index += _SwitchPipe(Context, index, gcvPIPE_3D);
++
++ /* Store the location of the link. */
++ Context->linkIndexXD = (gctUINT)index;
++
++ if (buffer != gcvNULL)
++ {
++ buffer[index + 0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[index + 1]
++ = 0;
++ }
++
++ index += 2;
++
++
++ /**************************************************************************/
++ /* Save size for buffer. **************************************************/
++
++ Context->totalSize = index * gcmSIZEOF(gctUINT32);
++
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++static gceSTATUS
++_DestroyContext(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ if (Context != gcvNULL)
++ {
++ gcsCONTEXT_PTR bufferHead;
++
++ /* Free context buffers. */
++ for (bufferHead = Context->buffer; Context->buffer != gcvNULL;)
++ {
++ /* Get a shortcut to the current buffer. */
++ gcsCONTEXT_PTR buffer = Context->buffer;
++
++ /* Get the next buffer. */
++ gcsCONTEXT_PTR next = buffer->next;
++
++ /* Last item? */
++ if (next == bufferHead)
++ {
++ next = gcvNULL;
++ }
++
++ /* Destroy the signal. */
++ if (buffer->signal != gcvNULL)
++ {
++ gcmkONERROR(gckOS_DestroySignal(
++ Context->os, buffer->signal
++ ));
++
++ buffer->signal = gcvNULL;
++ }
++
++ /* Free state delta map. */
++ if (buffer->logical != gcvNULL)
++ {
++ if (Context->hardware->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckEVENT_DestroyVirtualCommandBuffer(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckEVENT_FreeContiguousMemory(
++ Context->hardware->kernel->eventObj,
++ Context->totalSize,
++ buffer->physical,
++ buffer->logical,
++ gcvKERNEL_PIXEL
++ ));
++ }
++
++ buffer->logical = gcvNULL;
++ }
++
++ /* Free context buffer. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, buffer));
++
++ /* Remove from the list. */
++ Context->buffer = next;
++ }
++
++#if gcdSECURE_USER
++ /* Free the hint array. */
++ if (Context->hint != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->hint));
++ }
++#endif
++ /* Free record array copy. */
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (Context->recordArrayMap != gcvNULL)
++ {
++ gcsRECORD_ARRAY_MAP_PTR map = Context->recordArrayMap;
++
++ do
++ {
++ /* Free record array. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, map->kData));
++ map = map->next;
++ }
++ while (map != Context->recordArrayMap);
++
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArrayMap));
++ }
++#else
++ if (Context->recordArray != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArray));
++ }
++#endif
++
++ /* Free the state mapping. */
++ if (Context->map != gcvNULL)
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->map));
++ }
++
++ /* Mark the gckCONTEXT object as unknown. */
++ Context->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCONTEXT object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context));
++ }
++
++OnError:
++ return status;
++}
++
++
++/******************************************************************************\
++**************************** Context Management API ****************************
++\******************************************************************************/
++
++/******************************************************************************\
++**
++** gckCONTEXT_Construct
++**
++** Construct a new gckCONTEXT object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gckHARDWARE Hardware
++** Pointer to gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable thet will receive the gckCONTEXT object
++** pointer.
++*/
++#if (gcdENABLE_3D || gcdENABLE_2D)
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gctUINT32 allocationSize;
++ gctUINT i;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Os=0x%08X Hardware=0x%08X", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++
++
++ /**************************************************************************/
++ /* Allocate and initialize basic fields of gckCONTEXT. ********************/
++
++ /* The context object size. */
++ allocationSize = gcmSIZEOF(struct _gckCONTEXT);
++
++ /* Allocate the object. */
++ gcmkONERROR(gckOS_Allocate(
++ Os, allocationSize, &pointer
++ ));
++
++ context = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(context, allocationSize));
++
++ /* Initialize the gckCONTEXT object. */
++ context->object.type = gcvOBJ_CONTEXT;
++ context->os = Os;
++ context->hardware = Hardware;
++
++
++#if !gcdENABLE_3D
++ context->entryPipe = gcvPIPE_2D;
++ context->exitPipe = gcvPIPE_2D;
++#elif gcdCMD_NO_2D_CONTEXT
++ context->entryPipe = gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#else
++ context->entryPipe
++ = (((((gctUINT32) (context->hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) )
++ ? gcvPIPE_2D
++ : gcvPIPE_3D;
++ context->exitPipe = gcvPIPE_3D;
++#endif
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Hardware,
++ &context->alignment,
++ &context->reservedHead,
++ &context->reservedTail
++ ));
++
++ /* Mark the context as dirty to force loading of the entire state table
++ the first time. */
++ context->dirty = gcvTRUE;
++
++
++ /**************************************************************************/
++ /* Get the size of the context buffer. ************************************/
++
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++
++ /**************************************************************************/
++ /* Compute the size of the record array. **********************************/
++
++ context->recordArraySize
++ = gcmSIZEOF(gcsSTATE_DELTA_RECORD) * (gctUINT)context->stateCount;
++
++
++ if (context->stateCount > 0)
++ {
++ /**************************************************************************/
++ /* Allocate and reset the state mapping table. ****************************/
++
++ /* Allocate the state mapping table. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsSTATE_MAP) * context->stateCount,
++ &pointer
++ ));
++
++ context->map = pointer;
++
++ /* Zero the state mapping table. */
++ gcmkONERROR(gckOS_ZeroMemory(
++ context->map, gcmSIZEOF(gcsSTATE_MAP) * context->stateCount
++ ));
++
++
++ /**************************************************************************/
++ /* Allocate the hint array. ***********************************************/
++
++#if gcdSECURE_USER
++ /* Allocate hints. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gctBOOL) * context->stateCount,
++ &pointer
++ ));
++
++ context->hint = pointer;
++#endif
++ }
++
++ /**************************************************************************/
++ /* Allocate the context and state delta buffers. **************************/
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i += 1)
++ {
++ /* Allocate a context buffer. */
++ gcsCONTEXT_PTR buffer;
++
++ gctSIZE_T totalSize = context->totalSize;
++
++ /* Allocate the context buffer structure. */
++ gcmkONERROR(gckOS_Allocate(
++ Os,
++ gcmSIZEOF(gcsCONTEXT),
++ &pointer
++ ));
++
++ buffer = pointer;
++
++ /* Reset the context buffer structure. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ buffer, gcmSIZEOF(gcsCONTEXT)
++ ));
++
++ /* Append to the list. */
++ if (context->buffer == gcvNULL)
++ {
++ buffer->next = buffer;
++ context->buffer = buffer;
++ }
++ else
++ {
++ buffer->next = context->buffer->next;
++ context->buffer->next = buffer;
++ }
++
++ /* Set the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ buffer->num = i;
++#endif
++
++ /* Create the busy signal. */
++ gcmkONERROR(gckOS_CreateSignal(
++ Os, gcvFALSE, &buffer->signal
++ ));
++
++ /* Set the signal, buffer is currently not busy. */
++ gcmkONERROR(gckOS_Signal(
++ Os, buffer->signal, gcvTRUE
++ ));
++
++ /* Create a new physical context buffer. */
++ if (context->hardware->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckKERNEL_AllocateVirtualCommandBuffer(
++ context->hardware->kernel,
++ gcvFALSE,
++ &totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++ gcmkONERROR(gckKERNEL_GetGPUAddress(
++ context->hardware->kernel,
++ pointer,
++ gcvFALSE,
++ &address
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Os,
++ gcvFALSE,
++ &totalSize,
++ &buffer->physical,
++ &pointer
++ ));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ context->hardware,
++ pointer,
++ gcvFALSE,
++ &address
++ ));
++ }
++
++ buffer->logical = pointer;
++ buffer->address = address;
++
++ /* Set gckEVENT object pointer. */
++ buffer->eventObj = Hardware->kernel->eventObj;
++
++ /* Set the pointers to the LINK commands. */
++ if (context->linkIndex2D != 0)
++ {
++ buffer->link2D = &buffer->logical[context->linkIndex2D];
++ }
++
++ if (context->linkIndex3D != 0)
++ {
++ buffer->link3D = &buffer->logical[context->linkIndex3D];
++ }
++
++ if (context->linkIndexXD != 0)
++ {
++ gctPOINTER xdLink;
++ gctUINT32 xdEntryAddress;
++ gctUINT32 xdEntrySize;
++ gctUINT32 linkBytes;
++
++ /* Determine LINK parameters. */
++ xdLink
++ = &buffer->logical[context->linkIndexXD];
++
++ xdEntryAddress
++ = buffer->address
++ + context->entryOffsetXDFrom3D;
++
++ xdEntrySize
++ = context->bufferSize
++ - context->entryOffsetXDFrom3D;
++
++ /* Query LINK size. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware, gcvNULL, 0, 0, &linkBytes
++ ));
++
++ /* Generate a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Hardware,
++ xdLink,
++ xdEntryAddress,
++ xdEntrySize,
++ &linkBytes
++ ));
++ }
++ }
++
++
++ /**************************************************************************/
++ /* Initialize the context buffers. ****************************************/
++
++ /* Initialize the current context buffer. */
++ gcmkONERROR(_InitializeContextBuffer(context));
++
++ /* Make all created contexts equal. */
++ {
++ gcsCONTEXT_PTR currContext, tempContext;
++
++ /* Set the current context buffer. */
++ currContext = context->buffer;
++
++ /* Get the next context buffer. */
++ tempContext = currContext->next;
++
++ /* Loop through all buffers. */
++ while (tempContext != currContext)
++ {
++ if (tempContext == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ /* Copy the current context. */
++ gckOS_MemCopy(
++ tempContext->logical,
++ currContext->logical,
++ context->totalSize
++ );
++
++ /* Get the next context buffer. */
++ tempContext = tempContext->next;
++ }
++ }
++
++ /* Return pointer to the gckCONTEXT object. */
++ *Context = context;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%08X", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back on error. */
++ gcmkVERIFY_OK(_DestroyContext(context));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/******************************************************************************\
++**
++** gckCONTEXT_Destroy
++**
++** Destroy a gckCONTEXT object.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Context=0x%08X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Destroy the context and all related objects. */
++ status = _DestroyContext(Context);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/******************************************************************************\
++**
++** gckCONTEXT_Update
++**
++** Merge all pending state delta buffers into the current context buffer.
++**
++** INPUT:
++**
++** gckCONTEXT Context
++** Pointer to an gckCONTEXT object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ )
++{
++#if gcdENABLE_3D
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSTATE_DELTA _stateDelta;
++ gckKERNEL kernel;
++ gcsCONTEXT_PTR buffer;
++ gcsSTATE_MAP_PTR map;
++ gctBOOL needCopy = gcvFALSE;
++ gcsSTATE_DELTA_PTR nDelta;
++ gcsSTATE_DELTA_PTR uDelta = gcvNULL;
++ gcsSTATE_DELTA_PTR kDelta = gcvNULL;
++ gcsSTATE_DELTA_RECORD_PTR record;
++ gcsSTATE_DELTA_RECORD_PTR recordArray = gcvNULL;
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ gcsRECORD_ARRAY_MAP_PTR recordArrayMap = gcvNULL;
++#endif
++ gctUINT elementCount;
++ gctUINT address;
++ gctUINT32 mask;
++ gctUINT32 data;
++ gctUINT index;
++ gctUINT i, j;
++
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++
++ gcmkHEADER_ARG(
++ "Context=0x%08X ProcessID=%d StateDelta=0x%08X",
++ Context, ProcessID, StateDelta
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ /* Get a shortcut to the kernel object. */
++ kernel = Context->hardware->kernel;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Context->os, ProcessID, &needCopy));
++
++ /* Allocate the copy buffer for the user record array. */
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy && (Context->recordArrayMap == gcvNULL))
++ {
++ /* Allocate enough maps. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ gcmSIZEOF(gcsRECORD_ARRAY_MAP_PTR) * gcdCONTEXT_BUFFER_COUNT,
++ (gctPOINTER *) &Context->recordArrayMap
++ ));
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++)
++ {
++ /* Next mapping id. */
++ gctUINT n = (i + 1) % gcdCONTEXT_BUFFER_COUNT;
++
++ recordArrayMap = &Context->recordArrayMap[i];
++
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &recordArrayMap->kData
++ ));
++
++ /* Initialize fields. */
++ recordArrayMap->key = 0;
++ recordArrayMap->next = &Context->recordArrayMap[n];
++ }
++ }
++#else
++ if (needCopy && (Context->recordArray == gcvNULL))
++ {
++ /* Allocate the buffer. */
++ gcmkONERROR(gckOS_Allocate(
++ Context->os,
++ Context->recordArraySize,
++ (gctPOINTER *) &Context->recordArray
++ ));
++ }
++#endif
++
++ /* Get the current context buffer. */
++ buffer = Context->buffer;
++
++ /* Wait until the context buffer becomes available; this will
++ also reset the signal and mark the buffer as busy. */
++ gcmkONERROR(gckOS_WaitSignal(
++ Context->os, buffer->signal, gcvINFINITE
++ ));
++
++#if gcdSECURE_USER
++ /* Get the cache form the database. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(kernel, ProcessID, &cache));
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE) && 1 && gcdENABLE_3D
++ /* Update current context token. */
++ buffer->logical[Context->map[0x0E14].index]
++ = (gctUINT32)gcmPTR2INT32(Context);
++#endif
++
++ /* Are there any pending deltas? */
++ if (buffer->deltaCount != 0)
++ {
++ /* Get the state map. */
++ map = Context->map;
++
++ /* Get the first delta item. */
++ uDelta = buffer->delta;
++
++ /* Reset the vertex stream count. */
++ elementCount = 0;
++
++ /* Merge all pending deltas. */
++ for (i = 0; i < buffer->deltaCount; i += 1)
++ {
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy)
++ {
++ recordArray = gcvNULL;
++ recordArrayMap = Context->recordArrayMap;
++
++ do
++ {
++ /* Check if recordArray is alreay opened. */
++ if (recordArrayMap->key == kDelta->recordArray)
++ {
++ /* Found. */
++ recordArray = recordArrayMap->kData;
++ break;
++ }
++
++ recordArrayMap = recordArrayMap->next;
++ }
++ while (recordArrayMap != Context->recordArrayMap);
++
++ if (recordArray == gcvNULL)
++ {
++ while (recordArrayMap->key != 0)
++ {
++ /* Found an empty slot. */
++ recordArrayMap = recordArrayMap->next;
++ }
++
++ /* Get access to the state records. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ kernel->os,
++ recordArrayMap->kData,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize
++ ));
++
++ /* Save user pointer as key. */
++ recordArrayMap->key = kDelta->recordArray;
++ recordArray = recordArrayMap->kData;
++ }
++ }
++ else
++ {
++ /* Get access to the state records. */
++ gcmkONERROR(gckOS_MapUserPointer(
++ kernel->os,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++#else
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ Context->recordArray,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++#endif
++
++ /* Merge all pending states. */
++ for (j = 0; j < kDelta->recordCount; j += 1)
++ {
++ if (j >= Context->stateCount)
++ {
++ break;
++ }
++
++ /* Get the current state record. */
++ record = &recordArray[j];
++
++ /* Get the state address. */
++ address = record->address;
++
++ /* Make sure the state is a part of the mapping table. */
++ if (address >= Context->stateCount)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): State 0x%04X is not mapped.\n",
++ __FUNCTION__, __LINE__,
++ address
++ );
++
++ continue;
++ }
++
++ /* Get the state index. */
++ index = map[address].index;
++
++ /* Skip the state if not mapped. */
++ if (index == 0)
++ {
++ continue;
++ }
++
++ /* Get the data mask. */
++ mask = record->mask;
++
++ /* Masked states that are being completly reset or regular states. */
++ if ((mask == 0) || (mask == ~0U))
++ {
++ /* Get the new data value. */
++ data = record->data;
++
++ /* Process special states. */
++ if (address == 0x0595)
++ {
++ /* Force auto-disable to be disabled. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13)));
++ }
++
++#if gcdSECURE_USER
++ /* Do we need to convert the logical address? */
++ if (Context->hint[address])
++ {
++ /* Map handle into physical address. */
++ gcmkONERROR(gckKERNEL_MapLogicalToPhysical(
++ kernel, cache, (gctPOINTER) &data
++ ));
++ }
++#endif
++
++ /* Set new data. */
++ buffer->logical[index] = data;
++ }
++
++ /* Masked states that are being set partially. */
++ else
++ {
++ buffer->logical[index]
++ = (~mask & buffer->logical[index])
++ | (mask & record->data);
++ }
++ }
++
++ /* Get the element count. */
++ if (kDelta->elementCount != 0)
++ {
++ elementCount = kDelta->elementCount;
++ }
++
++ /* Dereference delta. */
++ kDelta->refCount -= 1;
++ gcmkASSERT(kDelta->refCount >= 0);
++
++ /* Get the next state delta. */
++ nDelta = gcmUINT64_TO_PTR(kDelta->next);
++
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ if (needCopy)
++ {
++ if (kDelta->refCount == 0)
++ {
++ /* No other reference, reset the mapping. */
++ recordArrayMap->key = 0;
++ }
++ }
++ else
++ {
++ /* Close access to the state records. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ kernel->os,
++ gcmUINT64_TO_PTR(kDelta->recordArray),
++ Context->recordArraySize,
++ (gctPOINTER *) recordArray
++ ));
++
++ recordArray = gcvNULL;
++ }
++#else
++ /* Get access to the state records. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++#endif
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Update the user delta pointer. */
++ uDelta = nDelta;
++ }
++
++ /* Hardware disables all input streams when the stream 0 is programmed,
++ it then reenables those streams that were explicitely programmed by
++ the software. Because of this we cannot program the entire array of
++ values, otherwise we'll get all streams reenabled, but rather program
++ only those that are actully needed by the software. */
++ if (elementCount != 0)
++ {
++ gctUINT base;
++ gctUINT nopCount;
++ gctUINT32_PTR nop;
++ gctUINT fe2vsCount = 12;
++
++ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ))
++ {
++ fe2vsCount = 16;
++ }
++
++ /* Determine the base index of the vertex stream array. */
++ base = map[0x0180].index;
++
++ /* Set the proper state count. */
++ buffer->logical[base - 1]
++ = ((((gctUINT32) (buffer->logical[base - 1])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (elementCount ) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine the number of NOP commands. */
++ nopCount
++ = (fe2vsCount / 2)
++ - (elementCount / 2);
++
++ /* Determine the location of the first NOP. */
++ nop = &buffer->logical[base + (elementCount | 1)];
++
++ /* Fill the unused space with NOPs. */
++ for (i = 0; i < nopCount; i += 1)
++ {
++ if (nop >= buffer->logical + Context->totalSize)
++ {
++ break;
++ }
++
++ /* Generate a NOP command. */
++ *nop = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ /* Advance. */
++ nop += 2;
++ }
++ }
++
++ /* Reset pending deltas. */
++ buffer->deltaCount = 0;
++ buffer->delta = gcvNULL;
++ }
++
++ /* Set state delta user pointer. */
++ uDelta = StateDelta;
++
++ /* Get access to the state delta. */
++ gcmkONERROR(gckKERNEL_OpenUserData(
++ kernel, needCopy,
++ &_stateDelta,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* State delta cannot be attached to anything yet. */
++ if (kDelta->refCount != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): kDelta->refCount = %d (has to be 0).\n",
++ __FUNCTION__, __LINE__,
++ kDelta->refCount
++ );
++ }
++
++ /* Attach to all contexts. */
++ buffer = Context->buffer;
++
++ do
++ {
++ /* Attach to the context if nothing is attached yet. If a delta
++ is allready attached, all we need to do is to increment
++ the number of deltas in the context. */
++ if (buffer->delta == gcvNULL)
++ {
++ buffer->delta = uDelta;
++ }
++
++ /* Update reference count. */
++ kDelta->refCount += 1;
++
++ /* Update counters. */
++ buffer->deltaCount += 1;
++
++ /* Get the next context buffer. */
++ buffer = buffer->next;
++
++ if (buffer == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++ }
++ while (Context->buffer != buffer);
++
++ /* Close access to the current state delta. */
++ gcmkONERROR(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Schedule an event to mark the context buffer as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ buffer->eventObj, buffer->signal, gcvKERNEL_PIXEL
++ ));
++
++ /* Advance to the next context buffer. */
++ Context->buffer = buffer->next;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Get access to the state records. */
++ if (kDelta != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvFALSE,
++ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize,
++ (gctPOINTER *) &recordArray
++ ));
++ }
++
++ /* Close access to the current state delta. */
++ gcmkVERIFY_OK(gckKERNEL_CloseUserData(
++ kernel, needCopy,
++ gcvTRUE,
++ uDelta, gcmSIZEOF(gcsSTATE_DELTA),
++ (gctPOINTER *) &kDelta
++ ));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++gceSTATUS
++gckCONTEXT_MapBuffer(
++ IN gckCONTEXT Context,
++ OUT gctUINT32 *Physicals,
++ OUT gctUINT64 *Logicals,
++ OUT gctUINT32 *Bytes
++ )
++{
++ gceSTATUS status;
++ int i = 0;
++ gctSIZE_T pageCount;
++ gckVIRTUAL_COMMAND_BUFFER_PTR commandBuffer;
++ gckKERNEL kernel = Context->hardware->kernel;
++ gctPOINTER logical;
++ gctPHYS_ADDR physical;
++
++ gcsCONTEXT_PTR buffer;
++
++ gcmkHEADER();
++
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ buffer = Context->buffer;
++
++ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++)
++ {
++ if (kernel->virtualCommandBuffer)
++ {
++ commandBuffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)buffer->physical;
++ physical = commandBuffer->physical;
++
++ gcmkONERROR(gckOS_CreateUserVirtualMapping(
++ kernel->os,
++ physical,
++ Context->totalSize,
++ &logical,
++ &pageCount));
++ }
++ else
++ {
++ physical = buffer->physical;
++
++ gcmkONERROR(gckOS_MapMemory(
++ kernel->os,
++ physical,
++ Context->totalSize,
++ &logical));
++ }
++
++ Physicals[i] = gcmPTR_TO_NAME(physical);
++
++ Logicals[i] = gcmPTR_TO_UINT64(logical);
++
++ buffer = buffer->next;
++ }
++
++ *Bytes = (gctUINT)Context->totalSize;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_context.h 2016-06-19 22:11:55.213146043 +0200
+@@ -0,0 +1,183 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_context_h_
++#define __gc_hal_kernel_context_h_
++
++#include "gc_hal_kernel_buffer.h"
++
++/* Exprimental optimization. */
++#define REMOVE_DUPLICATED_COPY_FROM_USER 1
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Maps state locations within the context buffer. */
++typedef struct _gcsSTATE_MAP * gcsSTATE_MAP_PTR;
++typedef struct _gcsSTATE_MAP
++{
++ /* Index of the state in the context buffer. */
++ gctUINT index;
++
++ /* State mask. */
++ gctUINT32 mask;
++}
++gcsSTATE_MAP;
++
++/* Context buffer. */
++typedef struct _gcsCONTEXT * gcsCONTEXT_PTR;
++typedef struct _gcsCONTEXT
++{
++ /* For debugging: the number of context buffer in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Context busy signal. */
++ gctSIGNAL signal;
++
++ /* Physical address of the context buffer. */
++ gctPHYS_ADDR physical;
++
++ /* Logical address of the context buffer. */
++ gctUINT32_PTR logical;
++
++ /* Hardware address of the context buffer. */
++ gctUINT32 address;
++
++ /* Pointer to the LINK commands. */
++ gctPOINTER link2D;
++ gctPOINTER link3D;
++
++ /* The number of pending state deltas. */
++ gctUINT deltaCount;
++
++ /* Pointer to the first delta to be applied. */
++ gcsSTATE_DELTA_PTR delta;
++
++ /* Next context buffer. */
++ gcsCONTEXT_PTR next;
++}
++gcsCONTEXT;
++
++typedef struct _gcsRECORD_ARRAY_MAP * gcsRECORD_ARRAY_MAP_PTR;
++struct _gcsRECORD_ARRAY_MAP
++{
++ /* User pointer key. */
++ gctUINT64 key;
++
++ /* Kernel memory buffer. */
++ gcsSTATE_DELTA_RECORD_PTR kData;
++
++ /* Next map. */
++ gcsRECORD_ARRAY_MAP_PTR next;
++
++};
++
++/* gckCONTEXT structure that hold the current context. */
++struct _gckCONTEXT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Command buffer alignment. */
++ gctUINT32 alignment;
++ gctUINT32 reservedHead;
++ gctUINT32 reservedTail;
++
++ /* Context buffer metrics. */
++ gctSIZE_T stateCount;
++ gctUINT32 totalSize;
++ gctUINT32 bufferSize;
++ gctUINT32 linkIndex2D;
++ gctUINT32 linkIndex3D;
++ gctUINT32 linkIndexXD;
++ gctUINT32 entryOffset3D;
++ gctUINT32 entryOffsetXDFrom2D;
++ gctUINT32 entryOffsetXDFrom3D;
++
++ /* Dirty flags. */
++ gctBOOL dirty;
++ gctBOOL dirty2D;
++ gctBOOL dirty3D;
++ gcsCONTEXT_PTR dirtyBuffer;
++
++ /* State mapping. */
++ gcsSTATE_MAP_PTR map;
++
++ /* List of context buffers. */
++ gcsCONTEXT_PTR buffer;
++
++ /* A copy of the user record array. */
++ gctUINT recordArraySize;
++#if REMOVE_DUPLICATED_COPY_FROM_USER
++ gcsRECORD_ARRAY_MAP_PTR recordArrayMap;
++#else
++ gcsSTATE_DELTA_RECORD_PTR recordArray;
++#endif
++
++ /* Requested pipe select for context. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Variables used for building state buffer. */
++ gctUINT32 lastAddress;
++ gctSIZE_T lastSize;
++ gctUINT32 lastIndex;
++ gctBOOL lastFixed;
++
++ gctUINT32 pipeSelectBytes;
++
++ /* Hint array. */
++#if gcdSECURE_USER
++ gctBOOL_PTR hint;
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gcsPROFILER_COUNTERS latestProfiler;
++ gcsPROFILER_COUNTERS histroyProfiler;
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++#endif
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_context_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c 2016-06-19 22:11:55.217145781 +0200
+@@ -0,0 +1,8036 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#if VIVANTE_PROFILER_CONTEXT
++#include "gc_hal_kernel_context.h"
++#endif
++
++#define gcdDISABLE_FE_L2 1
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++#define gcmSEMAPHORESTALL(buffer) \
++ do \
++ { \
++ /* Arm the PE-FE Semaphore. */ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, 1) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, 0x0E02); \
++ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END) \
++ | gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE);\
++ \
++ /* STALL FE until PE is done flushing. */ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \
++ \
++ *buffer++ \
++ = gcmSETFIELDVALUE(0, STALL_STALL, SOURCE, FRONT_END) \
++ | gcmSETFIELDVALUE(0, STALL_STALL, DESTINATION, PIXEL_ENGINE); \
++ } while(0)
++
++typedef struct _gcsiDEBUG_REGISTERS * gcsiDEBUG_REGISTERS_PTR;
++typedef struct _gcsiDEBUG_REGISTERS
++{
++ gctSTRING module;
++ gctUINT index;
++ gctUINT shift;
++ gctUINT data;
++ gctUINT count;
++ gctUINT32 signature;
++}
++gcsiDEBUG_REGISTERS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gctBOOL
++_IsHardwareMatch(
++ IN gckHARDWARE Hardware,
++ IN gctINT32 ChipModel,
++ IN gctUINT32 ChipRevision
++ )
++{
++ return ((Hardware->identity.chipModel == ChipModel) &&
++ (Hardware->identity.chipRevision == ChipRevision));
++}
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gceSTATUS status;
++
++ gctUINT32 chipIdentity;
++
++ gctUINT32 streamCount = 0;
++ gctUINT32 registerMax = 0;
++ gctUINT32 threadCount = 0;
++ gctUINT32 shaderCoreCount = 0;
++ gctUINT32 vertexCacheSize = 0;
++ gctUINT32 vertexOutputBufferSize = 0;
++ gctUINT32 pixelPipes = 0;
++ gctUINT32 instructionCount = 0;
++ gctUINT32 numConstants = 0;
++ gctUINT32 bufferSize = 0;
++ gctUINT32 varyingsCount = 0;
++#if gcdMULTI_GPU
++ gctUINT32 gpuCoreCount = 0;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /***************************************************************************
++ ** Get chip ID and revision.
++ */
++
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00018,
++ &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ Identity->chipModel = gcv500;
++ Identity->chipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00020,
++ (gctUINT32_PTR) &Identity->chipModel));
++
++ if (((Identity->chipModel & 0xFF00) == 0x0400)
++ && (Identity->chipModel != 0x0420)
++ && (Identity->chipModel != 0x0428))
++ {
++ Identity->chipModel = (gceCHIPMODEL) (Identity->chipModel & 0x0400);
++ }
++
++ /* Read CHIP_REV register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00024,
++ &Identity->chipRevision));
++
++ if ((Identity->chipModel == gcv300)
++ && (Identity->chipRevision == 0x2201)
++ )
++ {
++ gctUINT32 chipDate;
++ gctUINT32 chipTime;
++
++ /* Read date and time registers. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00028,
++ &chipDate));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0002C,
++ &chipTime));
++
++ if ((chipDate == 0x20080814) && (chipTime == 0x12051100))
++ {
++ /* This IP has an ECO; put the correct revision in it. */
++ Identity->chipRevision = 0x1051;
++ }
++ }
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x000A8,
++ &Identity->productID));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipModel=%X",
++ Identity->chipModel);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipRevision=%X",
++ Identity->chipRevision);
++
++
++ /***************************************************************************
++ ** Get chip features.
++ */
++
++ /* Read chip feature register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0001C,
++ &Identity->chipFeatures));
++
++#if gcdENABLE_3D
++ /* Disable fast clear on GC700. */
++ if (Identity->chipModel == gcv700)
++ {
++ Identity->chipFeatures
++ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++#endif
++
++ if (((Identity->chipModel == gcv500) && (Identity->chipRevision < 2))
++ || ((Identity->chipModel == gcv300) && (Identity->chipRevision < 0x2000))
++ )
++ {
++ /* GC500 rev 1.x and GC300 rev < 2.0 doesn't have these registers. */
++ Identity->chipMinorFeatures = 0;
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ Identity->chipMinorFeatures5 = 0;
++ }
++ else
++ {
++ /* Read chip minor feature register #0. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00034,
++ &Identity->chipMinorFeatures));
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))
++ )
++ {
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00074,
++ &Identity->chipMinorFeatures1));
++
++ /* Read chip minor featuress register #2. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00084,
++ &Identity->chipMinorFeatures2));
++
++ /*Identity->chipMinorFeatures2 &= ~(0x1 << 3);*/
++
++ /* Read chip minor featuress register #1. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00088,
++ &Identity->chipMinorFeatures3));
++
++
++ /* Read chip minor featuress register #4. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00094,
++ &Identity->chipMinorFeatures4));
++
++ /* Read chip minor featuress register #5. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x000A0,
++ &Identity->chipMinorFeatures5));
++ }
++ else
++ {
++ /* Chip doesn't has minor features register #1 or 2 or 3 or 4. */
++ Identity->chipMinorFeatures1 = 0;
++ Identity->chipMinorFeatures2 = 0;
++ Identity->chipMinorFeatures3 = 0;
++ Identity->chipMinorFeatures4 = 0;
++ Identity->chipMinorFeatures5 = 0;
++ }
++ }
++
++ /* Get the Supertile layout in the hardware. */
++ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))))
++ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))))
++ {
++ Identity->superTileMode = 2;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))))
++ {
++ Identity->superTileMode = 1;
++ }
++ else
++ {
++ Identity->superTileMode = 0;
++ }
++
++ /* Exception for GC1000, revision 5035 & GC800, revision 4612 */
++ if (((Identity->chipModel == gcv1000) && ((Identity->chipRevision == 0x5035)
++ || (Identity->chipRevision == 0x5036)
++ || (Identity->chipRevision == 0x5037)
++ || (Identity->chipRevision == 0x5039)
++ || (Identity->chipRevision >= 0x5040)))
++ || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612))
++ || ((Identity->chipModel == gcv600) && (Identity->chipRevision >= 0x4650))
++ || ((Identity->chipModel == gcv860) && (Identity->chipRevision == 0x4647))
++ || ((Identity->chipModel == gcv400) && (Identity->chipRevision >= 0x4633)))
++ {
++ Identity->superTileMode = 1;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipFeatures=0x%08X",
++ Identity->chipFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures=0x%08X",
++ Identity->chipMinorFeatures);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures1=0x%08X",
++ Identity->chipMinorFeatures1);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures2=0x%08X",
++ Identity->chipMinorFeatures2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures3=0x%08X",
++ Identity->chipMinorFeatures3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures4=0x%08X",
++ Identity->chipMinorFeatures4);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipMinorFeatures5=0x%08X",
++ Identity->chipMinorFeatures5);
++
++ /***************************************************************************
++ ** Get chip specs.
++ */
++
++ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ gctUINT32 specs, specs2, specs3, specs4;
++
++ /* Read gcChipSpecs register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00048,
++ &specs));
++
++ /* Extract the fields. */
++ registerMax = (((((gctUINT32) (specs)) >> (0 ? 7:4)) & ((gctUINT32) ((((1 ? 7:4) - (0 ? 7:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:4) - (0 ? 7:4) + 1)))))) );
++ threadCount = (((((gctUINT32) (specs)) >> (0 ? 11:8)) & ((gctUINT32) ((((1 ? 11:8) - (0 ? 11:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:8) - (0 ? 11:8) + 1)))))) );
++ shaderCoreCount = (((((gctUINT32) (specs)) >> (0 ? 24:20)) & ((gctUINT32) ((((1 ? 24:20) - (0 ? 24:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:20) - (0 ? 24:20) + 1)))))) );
++ vertexCacheSize = (((((gctUINT32) (specs)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ vertexOutputBufferSize = (((((gctUINT32) (specs)) >> (0 ? 31:28)) & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1)))))) );
++ pixelPipes = (((((gctUINT32) (specs)) >> (0 ? 27:25)) & ((gctUINT32) ((((1 ? 27:25) - (0 ? 27:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:25) - (0 ? 27:25) + 1)))))) );
++
++ /* Read gcChipSpecs2 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x00080,
++ &specs2));
++
++ instructionCount = (((((gctUINT32) (specs2)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ numConstants = (((((gctUINT32) (specs2)) >> (0 ? 31:16)) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1)))))) );
++ bufferSize = (((((gctUINT32) (specs2)) >> (0 ? 7:0)) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1)))))) );
++
++ /* Read gcChipSpecs3 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0008C,
++ &specs3));
++
++ varyingsCount = (((((gctUINT32) (specs3)) >> (0 ? 8:4)) & ((gctUINT32) ((((1 ? 8:4) - (0 ? 8:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:4) - (0 ? 8:4) + 1)))))) );
++#if gcdMULTI_GPU
++ gpuCoreCount = (((((gctUINT32) (specs3)) >> (0 ? 2:0)) & ((gctUINT32) ((((1 ? 2:0) - (0 ? 2:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:0) - (0 ? 2:0) + 1)))))) );
++#endif
++
++ /* Read gcChipSpecs4 register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os, Core,
++ 0x0009C,
++ &specs4));
++
++
++ streamCount = (((((gctUINT32) (specs4)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) );
++ if (streamCount == 0)
++ {
++ /* Extract stream count from older register. */
++ streamCount = (((((gctUINT32) (specs)) >> (0 ? 3:0)) & ((gctUINT32) ((((1 ? 3:0) - (0 ? 3:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:0) - (0 ? 3:0) + 1)))))) );
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs1=0x%08X",
++ specs);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs2=0x%08X",
++ specs2);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs3=0x%08X",
++ specs3);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Identity: chipSpecs4=0x%08X",
++ specs4);
++ }
++
++ /* Get the number of pixel pipes. */
++ Identity->pixelPipes = gcmMAX(pixelPipes, 1);
++
++ /* Get the stream count. */
++ Identity->streamCount = (streamCount != 0)
++ ? streamCount
++ : (Identity->chipModel >= gcv1000) ? 4 : 1;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: streamCount=%u%s",
++ Identity->streamCount,
++ (streamCount == 0) ? " (default)" : "");
++
++ /* Get the vertex output buffer size. */
++ Identity->vertexOutputBufferSize = (vertexOutputBufferSize != 0)
++ ? 1 << vertexOutputBufferSize
++ : (Identity->chipModel == gcv400)
++ ? (Identity->chipRevision < 0x4000) ? 512
++ : (Identity->chipRevision < 0x4200) ? 256
++ : 128
++ : (Identity->chipModel == gcv530)
++ ? (Identity->chipRevision < 0x4200) ? 512
++ : 128
++ : 512;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexOutputBufferSize=%u%s",
++ Identity->vertexOutputBufferSize,
++ (vertexOutputBufferSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of threads. */
++ Identity->threadCount = (threadCount != 0)
++ ? 1 << threadCount
++ : (Identity->chipModel == gcv400) ? 64
++ : (Identity->chipModel == gcv500) ? 128
++ : (Identity->chipModel == gcv530) ? 128
++ : 256;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: threadCount=%u%s",
++ Identity->threadCount,
++ (threadCount == 0) ? " (default)" : "");
++
++ /* Get the number of shader cores. */
++ Identity->shaderCoreCount = (shaderCoreCount != 0)
++ ? shaderCoreCount
++ : (Identity->chipModel >= gcv1000) ? 2
++ : 1;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: shaderCoreCount=%u%s",
++ Identity->shaderCoreCount,
++ (shaderCoreCount == 0) ? " (default)" : "");
++
++ /* Get the vertex cache size. */
++ Identity->vertexCacheSize = (vertexCacheSize != 0)
++ ? vertexCacheSize
++ : 8;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: vertexCacheSize=%u%s",
++ Identity->vertexCacheSize,
++ (vertexCacheSize == 0) ? " (default)" : "");
++
++ /* Get the maximum number of temporary registers. */
++ Identity->registerMax = (registerMax != 0)
++ /* Maximum of registerMax/4 registers are accessible to 1 shader */
++ ? 1 << registerMax
++ : (Identity->chipModel == gcv400) ? 32
++ : 64;
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: registerMax=%u%s",
++ Identity->registerMax,
++ (registerMax == 0) ? " (default)" : "");
++
++ /* Get the instruction count. */
++ Identity->instructionCount = (instructionCount == 0) ? 256
++ : (instructionCount == 1) ? 1024
++ : (instructionCount == 2) ? 2048
++ : (instructionCount == 0xFF) ? 512
++ : 256;
++
++ if (Identity->instructionCount == 256)
++ {
++ if ((Identity->chipModel == gcv2000 && Identity->chipRevision == 0x5108)
++ || Identity->chipModel == gcv880)
++ {
++ Identity->instructionCount = 512;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))))
++ {
++ Identity->instructionCount = 512;
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: instructionCount=%u%s",
++ Identity->instructionCount,
++ (instructionCount == 0) ? " (default)" : "");
++
++ /* Get the number of constants. */
++ Identity->numConstants = (numConstants == 0) ? 168 : numConstants;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: numConstants=%u%s",
++ Identity->numConstants,
++ (numConstants == 0) ? " (default)" : "");
++
++ /* Get the buffer size. */
++ Identity->bufferSize = bufferSize;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Specs: bufferSize=%u%s",
++ Identity->bufferSize,
++ (bufferSize == 0) ? " (default)" : "");
++
++
++ if (varyingsCount != 0)
++ {
++ Identity->varyingsCount = varyingsCount;
++ }
++ else if (((((gctUINT32) (Identity->chipMinorFeatures1)) >> (0 ? 23:23) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))))
++ {
++ Identity->varyingsCount = 12;
++ }
++ else
++ {
++ Identity->varyingsCount = 8;
++ }
++
++ /* For some cores, it consumes two varying for position, so the max varying vectors should minus one. */
++ if ((Identity->chipModel == gcv5000 && Identity->chipRevision == 0x5434) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5222) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5208) ||
++ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5245) ||
++ (Identity->chipModel == gcv3000 && Identity->chipRevision == 0x5435) ||
++ (Identity->chipModel == gcv2200 && Identity->chipRevision == 0x5244) ||
++ (Identity->chipModel == gcv1500 && Identity->chipRevision == 0x5246) ||
++ ((Identity->chipModel == gcv2100 || Identity->chipModel == gcv2000) && Identity->chipRevision == 0x5108) ||
++ (Identity->chipModel == gcv880 && (Identity->chipRevision == 0x5107 || Identity->chipRevision == 0x5106)))
++ {
++ Identity->varyingsCount -= 1;
++ }
++
++ Identity->chip2DControl = 0;
++ if (Identity->chipModel == gcv320)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x0002C,
++ &data));
++
++ if ((data != 33956864) &&
++ ((Identity->chipRevision == 0x5007) ||
++ (Identity->chipRevision == 0x5220)))
++ {
++ Identity->chip2DControl |= 0xFF &
++ (Identity->chipRevision == 0x5220 ? 8 :
++ (Identity->chipRevision == 0x5007 ? 12 : 0));
++ }
++
++ if (Identity->chipRevision == 0x5007)
++ {
++ /* Disable splitting rectangle. */
++ Identity->chip2DControl |= 0x100;
++
++ /* Enable 2D Flush. */
++ Identity->chip2DControl |= 0x200;
++ }
++ }
++
++#if gcdMULTI_GPU
++#if gcdMULTI_GPU > 1
++ Identity->gpuCoreCount = gpuCoreCount + 1;
++#else
++ Identity->gpuCoreCount = 1;
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#define gcdDEBUG_MODULE_CLOCK_GATING 0
++#define gcdDISABLE_MODULE_CLOCK_GATING 0
++#define gcdDISABLE_FE_CLOCK_GATING 0
++#define gcdDISABLE_PE_CLOCK_GATING 0
++#define gcdDISABLE_SH_CLOCK_GATING 0
++#define gcdDISABLE_PA_CLOCK_GATING 0
++#define gcdDISABLE_SE_CLOCK_GATING 0
++#define gcdDISABLE_RA_CLOCK_GATING 0
++#define gcdDISABLE_RA_EZ_CLOCK_GATING 0
++#define gcdDISABLE_RA_HZ_CLOCK_GATING 0
++#define gcdDISABLE_TX_CLOCK_GATING 0
++
++#if gcdDEBUG_MODULE_CLOCK_GATING
++gceSTATUS
++_ConfigureModuleLevelClockGating(
++ gckHARDWARE Hardware
++ )
++{
++ gctUINT32 data;
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++#if gcdDISABLE_FE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++#endif
++
++#if gcdDISABLE_PE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++#endif
++
++#if gcdDISABLE_SH_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++#endif
++
++#if gcdDISABLE_PA_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++#endif
++
++#if gcdDISABLE_SE_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++#endif
++
++#if gcdDISABLE_RA_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++#endif
++
++#if gcdDISABLE_TX_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++#endif
++
++#if gcdDISABLE_RA_EZ_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++#endif
++
++#if gcdDISABLE_RA_HZ_CLOCK_GATING
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++#endif
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++
++#if gcdDISABLE_MODULE_CLOCK_GATING
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++#endif
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_PowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckHARDWARE hardware = (gckHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++static gceSTATUS
++_VerifyDMA(
++ IN gckOS Os,
++ IN gceCORE Core,
++ gctUINT32_PTR Address1,
++ gctUINT32_PTR Address2,
++ gctUINT32_PTR State1,
++ gctUINT32_PTR State2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State1));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address1));
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State2));
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address2));
++
++ if (*Address1 != *Address2)
++ {
++ break;
++ }
++
++ if (*State1 != *State2)
++ {
++ break;
++ }
++ }
++
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_DumpDebugRegisters(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gcsiDEBUG_REGISTERS_PTR Descriptor
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 select;
++ gctUINT32 data = 0;
++ gctUINT i;
++
++ gcmkHEADER_ARG("Os=0x%X Descriptor=0x%X", Os, Descriptor);
++
++ gcmkPRINT_N(4, " %s debug registers:\n", Descriptor->module);
++
++ for (i = 0; i < Descriptor->count; i += 1)
++ {
++ select = i << Descriptor->shift;
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ gcmkPRINT_N(12, " [0x%02X] 0x%08X\n", i, data);
++ }
++
++ select = 0xF << Descriptor->shift;
++
++ for (i = 0; i < 500; i += 1)
++ {
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select));
++#if gcdFPGA_BUILD
++ gcmkONERROR(gckOS_Delay(Os, 1000));
++#endif
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data));
++
++ if (data == Descriptor->signature)
++ {
++ break;
++ }
++ }
++
++ if (i == 500)
++ {
++ gcmkPRINT_N(4, " failed to obtain the signature (read 0x%08X).\n", data);
++ }
++ else
++ {
++ gcmkPRINT_N(8, " signature = 0x%08X (%d read attempt(s))\n", data, i + 1);
++ }
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IsGPUPresent(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ control));
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Hardware->os,
++ Hardware->core,
++ &identity));
++
++ /* Check if these are the same values as saved before. */
++ if ((Hardware->identity.chipModel != identity.chipModel)
++ || (Hardware->identity.chipRevision != identity.chipRevision)
++ || (Hardware->identity.chipFeatures != identity.chipFeatures)
++ || (Hardware->identity.chipMinorFeatures != identity.chipMinorFeatures)
++ || (Hardware->identity.chipMinorFeatures1 != identity.chipMinorFeatures1)
++ || (Hardware->identity.chipMinorFeatures2 != identity.chipMinorFeatures2)
++ )
++ {
++ gcmkPRINT("[galcore]: GPU is not present.");
++ gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++_FlushCache(
++ gckHARDWARE Hardware,
++ gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 bytes, requested;
++ gctPOINTER buffer;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(Command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(Command, requested));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++gctBOOL
++_IsGPUIdle(
++ IN gctUINT32 Idle
++ )
++{
++ return (((((gctUINT32) (Idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) )
++ && (((((gctUINT32) (Idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) )
++ ;
++}
++
++/******************************************************************************\
++****************************** gckHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHARDWARE_Construct
++**
++** Construct a new gckHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** OUTPUT:
++**
++** gckHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckHARDWARE
++** object.
++*/
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware = gcvNULL;
++ gctUINT16 data = 0xff00;
++ gctPOINTER pointer = gcvNULL;
++#if gcdMULTI_GPU_AFFINITY
++ gctUINT32 control;
++#endif
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ /* Enable the GPU. */
++ gcmkONERROR(gckOS_SetGPUPower(Os, Core, gcvTRUE, gcvTRUE));
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Allocate the gckHARDWARE object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckHARDWARE),
++ &pointer));
++
++ hardware = (gckHARDWARE) pointer;
++
++ /* Initialize the gckHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++ hardware->core = Core;
++
++ /* Identify the hardware. */
++ gcmkONERROR(_IdentifyHardware(Os, Core, &hardware->identity));
++
++ /* Determine the hardware type */
++ switch (hardware->identity.chipModel)
++ {
++ case gcv350:
++ case gcv355:
++ hardware->type = gcvHARDWARE_VG;
++ break;
++
++ case gcv200:
++ case gcv300:
++ case gcv320:
++ case gcv328:
++ case gcv420:
++ case gcv428:
++ hardware->type = gcvHARDWARE_2D;
++ break;
++
++ default:
++#if gcdMULTI_GPU_AFFINITY
++ hardware->type = (Core == gcvCORE_MAJOR) ? gcvHARDWARE_3D : gcvHARDWARE_OCL;
++#else
++ hardware->type = gcvHARDWARE_3D;
++#endif
++
++ if(hardware->identity.chipModel == gcv880 && hardware->identity.chipRevision == 0x5107)
++ {
++ /*set outstanding limit*/
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x00010;
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot));
++ }
++
++
++ if ((((((gctUINT32) (hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ))
++ {
++ hardware->type = (gceHARDWARE_TYPE) (hardware->type | gcvHARDWARE_2D);
++ }
++ }
++
++ hardware->powerBaseAddress
++ = ((hardware->identity.chipModel == gcv300)
++ && (hardware->identity.chipRevision < 0x2000))
++ ? 0x0100
++ : 0x0000;
++
++ /* _ResetGPU need powerBaseAddress. */
++ status = _ResetGPU(hardware, Os, Core);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++#if gcdMULTI_GPU
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0055C,
++#if gcdDISABLE_FE_L2
++ 0x00FFFFFF));
++#else
++ 0x00FFFF05));
++#endif
++
++#elif gcdMULTI_GPU_AFFINITY
++ control = ((((gctUINT32) (0x00FF0A05)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0055C,
++ control));
++#endif
++
++ hardware->powerMutex = gcvNULL;
++
++ hardware->mmuVersion
++ = (((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 28:28)) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) );
++
++ /* Determine whether bug fixes #1 are present. */
++ hardware->extraEventStates = ((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))));
++
++ /* Check if big endian */
++ hardware->bigEndian = (*(gctUINT8 *)&data == 0xff);
++
++ /* Initialize the fast clear. */
++ gcmkONERROR(gckHARDWARE_SetFastClear(hardware, -1, -1));
++
++#if !gcdENABLE_128B_MERGE
++
++ if (((((gctUINT32) (hardware->identity.chipMinorFeatures2)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))))
++ {
++ /* 128B merge is turned on by default. Disable it. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00558, 0));
++ }
++
++#endif
++
++ /* Set power state to ON. */
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++ hardware->lastWaitLink = ~0U;
++ hardware->lastEnd = ~0U;
++ hardware->globalSemaphore = gcvNULL;
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ hardware->powerOnFscaleVal = 64;
++#endif
++
++ gcmkONERROR(gckOS_CreateMutex(Os, &hardware->powerMutex));
++ gcmkONERROR(gckOS_CreateSemaphore(Os, &hardware->globalSemaphore));
++ hardware->startIsr = gcvNULL;
++ hardware->stopIsr = gcvNULL;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _PowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pendingEvent));
++
++#if gcdLINK_QUEUE_SIZE
++ hardware->linkQueue.front = 0;
++ hardware->linkQueue.rear = 0;
++ hardware->linkQueue.count = 0;
++#endif
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Disable profiler by default */
++ hardware->gpuProfiler = gcvFALSE;
++
++#if defined(LINUX) || defined(__QNXNTO__) || defined(UNDERCE)
++ if (hardware->mmuVersion)
++ {
++ hardware->endAfterFlushMmuCache = gcvTRUE;
++ }
++ else
++#endif
++ {
++ hardware->endAfterFlushMmuCache = gcvFALSE;
++ }
++
++ gcmkONERROR(gckOS_QueryOption(Os, "mmu", (gctUINT32_PTR)&hardware->enableMMU));
++
++ hardware->minFscaleValue = 1;
++
++ /* Return pointer to the gckHARDWARE object. */
++ *Hardware = hardware;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Hardware=0x%x", *Hardware);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, Core, gcvFALSE, gcvFALSE));
++
++ if (hardware->globalSemaphore != gcvNULL)
++ {
++ /* Destroy the global semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Os,
++ hardware->globalSemaphore));
++ }
++
++ if (hardware->powerMutex != gcvNULL)
++ {
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ if (hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware->pendingEvent != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pendingEvent));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, hardware));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Destroy
++**
++** Destroy an gckHARDWARE object.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Destroy the power semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++
++ /* Destroy the power mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Hardware->os, Hardware->powerMutex));
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pendingEvent));
++
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ Hardware->os,
++ Hardware->functionBytes,
++ Hardware->functionPhysical,
++ Hardware->functionLogical
++ ));
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the object. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Hardware->os, Hardware));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_GetType
++**
++** Get the hardware type.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gceHARDWARE_TYPE * Type
++** Pointer to a variable that receives the type of hardware object.
++*/
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkVERIFY_ARGUMENT(Type != gcvNULL);
++
++ *Type = Hardware->type;
++
++ gcmkFOOTER_ARG("*Type=%d", *Type);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_InitializeHardware
++**
++** Initialize the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++ gctUINT32 chipRev;
++ gctUINT32 control;
++ gctUINT32 data;
++ gctUINT32 regPMC = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the chip revision register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00024,
++ &chipRev));
++
++ if (chipRev != Hardware->identity.chipRevision)
++ {
++ /* Chip is not there! */
++ gcmkONERROR(gcvSTATUS_CONTEXT_LOSSED);
++ }
++
++ /* Disable isolate GPU bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)))));
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ /* Reset memory counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ ~0U));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++
++ /* Get the system's physical base address. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Program the base addesses. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0041C,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00418,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00428,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00420,
++ baseAddress));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00424,
++ baseAddress));
++
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ /* Enable clock gating. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ if ((Hardware->identity.chipRevision == 0x4301)
++ || (Hardware->identity.chipRevision == 0x4302)
++ )
++ {
++ /* Disable stall module level clock gating for 4.3.0.1 and 4.3.0.2
++ ** revisions. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++
++#if gcdENABLE_3D
++ /* Disable PE clock gating on revs < 5.0 when HZ is present without a
++ ** bug fix. */
++ if ((Hardware->identity.chipRevision < 0x5000)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HZ)
++ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))))
++ )
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable PE clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ }
++
++#endif
++ }
++
++ if (Hardware->identity.chipModel == gcv4000 &&
++ ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222)))
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)))));
++ }
++
++ if (Hardware->identity.chipModel == gcv1000 &&
++ (Hardware->identity.chipRevision == 0x5039 ||
++ Hardware->identity.chipRevision == 0x5040))
++ {
++ gctUINT32 pulseEater;
++
++ pulseEater = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (pulseEater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)))));
++ }
++
++ if ((gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) == gcvSTATUS_FALSE)
++ || (Hardware->identity.chipRevision < 0x5422)
++ )
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15)));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108))
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ &data));
++
++ /* Set FE bus to one, TX bus to zero */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00480,
++ data));
++ }
++
++ gcmkONERROR(
++ gckHARDWARE_SetMMU(Hardware,
++ Hardware->kernel->mmu->pageTableLogical));
++
++ if (Hardware->identity.chipModel >= gcv400
++ && Hardware->identity.chipModel != gcv420)
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable PA clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++
++ /* Limit 2D outstanding request. */
++ if (_IsHardwareMatch(Hardware, gcv880, 0x5107))
++ {
++ gctUINT32 axi_ot;
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &axi_ot));
++ axi_ot = (axi_ot & (~0xFF)) | 0x00010;
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00414, axi_ot));
++ }
++
++ if (Hardware->identity.chip2DControl & 0xFF)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (Hardware->identity.chip2DControl & 0xFF) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv1000, 0x5035))
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ &data));
++
++ /* Disable HZ-L2. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)));
++
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ data));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv4000, 0x5222))
++ {
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable TX clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv880, 0x5106))
++ {
++ Hardware->kernel->timeOut = 140 * 1000;
++ }
++
++ if (regPMC == 0)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &regPMC));
++ }
++
++ /* Disable RA HZ clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable RA EZ clock gating. */
++ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++
++ if (regPMC != 0)
++ {
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ regPMC));
++ }
++
++ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108)
++ || _IsHardwareMatch(Hardware, gcv320, 0x5007)
++ || _IsHardwareMatch(Hardware, gcv880, 0x5106)
++ || _IsHardwareMatch(Hardware, gcv400, 0x4645)
++ )
++ {
++ /* Update GPU AXI cache atttribute. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00008,
++ 0x00002200));
++ }
++
++
++ if ((Hardware->identity.chipRevision > 0x5420)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D))
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ /* Disable internal DFS. */
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++ }
++
++#if gcdDEBUG_MODULE_CLOCK_GATING
++ _ConfigureModuleLevelClockGating(Hardware);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*InternalSize=%lu *InternalBaseAddress=0x%08x "
++ "*InternalAlignment=0x%08x *ExternalSize=%lu "
++ "*ExternalBaseAddress=0x%08x *ExtenalAlignment=0x%08x "
++ "*HorizontalTileSize=%u *VerticalTileSize=%u",
++ gcmOPT_VALUE(InternalSize),
++ gcmOPT_VALUE(InternalBaseAddress),
++ gcmOPT_VALUE(InternalAlignment),
++ gcmOPT_VALUE(ExternalSize),
++ gcmOPT_VALUE(ExternalBaseAddress),
++ gcmOPT_VALUE(ExternalAlignment),
++ gcmOPT_VALUE(HorizontalTileSize),
++ gcmOPT_VALUE(VerticalTileSize));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++** Pointer to the identity structure.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ )
++{
++ gctUINT32 features;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Identity != gcvNULL);
++
++ /* Return chip model and revision. */
++ Identity->chipModel = Hardware->identity.chipModel;
++ Identity->chipRevision = Hardware->identity.chipRevision;
++
++ /* Return feature set. */
++ features = Hardware->identity.chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ /* Override fast clear by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ if ((((((gctUINT32) (features)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ))
++ {
++ /* Override compression by command line. */
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (Hardware->allowCompression) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 through GC500.2 and GC300,
++ ** since they did not have this bit. */
++ if (((Hardware->identity.chipModel == gcv500) && (Hardware->identity.chipRevision <= 2))
++ || (Hardware->identity.chipModel == gcv300)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ Identity->chipFeatures = features;
++
++ /* Return minor features. */
++ Identity->chipMinorFeatures = Hardware->identity.chipMinorFeatures;
++ Identity->chipMinorFeatures1 = Hardware->identity.chipMinorFeatures1;
++ Identity->chipMinorFeatures2 = Hardware->identity.chipMinorFeatures2;
++ Identity->chipMinorFeatures3 = Hardware->identity.chipMinorFeatures3;
++ Identity->chipMinorFeatures4 = Hardware->identity.chipMinorFeatures4;
++ Identity->chipMinorFeatures5 = Hardware->identity.chipMinorFeatures5;
++
++ /* Return chip specs. */
++ Identity->streamCount = Hardware->identity.streamCount;
++ Identity->registerMax = Hardware->identity.registerMax;
++ Identity->threadCount = Hardware->identity.threadCount;
++ Identity->shaderCoreCount = Hardware->identity.shaderCoreCount;
++ Identity->vertexCacheSize = Hardware->identity.vertexCacheSize;
++ Identity->vertexOutputBufferSize = Hardware->identity.vertexOutputBufferSize;
++ Identity->pixelPipes = Hardware->identity.pixelPipes;
++ Identity->instructionCount = Hardware->identity.instructionCount;
++ Identity->numConstants = Hardware->identity.numConstants;
++ Identity->bufferSize = Hardware->identity.bufferSize;
++ Identity->varyingsCount = Hardware->identity.varyingsCount;
++ Identity->superTileMode = Hardware->identity.superTileMode;
++#if gcdMULTI_GPU
++ Identity->gpuCoreCount = Hardware->identity.gpuCoreCount;
++#endif
++ Identity->chip2DControl = Hardware->identity.chip2DControl;
++
++ Identity->productID = Hardware->identity.productID;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Addres=0x%08x", Hardware, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 31:31)) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x1:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = (((((gctUINT32) (Address)) >> (0 ? 30:0)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1)))))) );
++ }
++ else
++ {
++ *Pool = gcvPOOL_SYSTEM;
++ *Offset = Address;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Pool=%d *Offset=0x%08x", *Pool, *Offset);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT32 Address
++** Hardware address of command buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes for the prefetch unit (until after the first LINK).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Bytes=%lu",
++ Hardware, Address, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Enable all events. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00014, ~0U));
++
++ /* Write address register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00654, Address));
++
++ /* Build control register. */
++ control = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) ((Bytes + 7) >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ /* Set big endian */
++ if (Hardware->bigEndian)
++ {
++ control |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20)));
++ }
++
++ /* Write control register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00658, control));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Started command buffer @ 0x%08x",
++ Address);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_WaitLink
++**
++** Append a WAIT/LINK command sequence at the specified location in the command
++** queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** WAIT/LINK command sequence at or gcvNULL just to query the size of the
++** WAIT/LINK command sequence.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the WAIT/LINK command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the WAIT/LINK command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitOffset
++** Pointer to a variable that will receive the offset of the WAIT command
++** from the specified logcial pointer.
++** If 'WaitOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitSize
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command. If 'LinkSize' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctUINT32 * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctUINT32 * WaitSize
++ )
++{
++ static const gctUINT waitCount = 200;
++
++ gceSTATUS status;
++ gctUINT32 address;
++ gctUINT32_PTR logical;
++ gctUINT32 bytes;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x *Bytes=%lu",
++ Hardware, Logical, Offset, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical != gcvNULL) || (Bytes != gcvNULL));
++
++#if gcdMULTI_GPU && !gcdDISABLE_FE_L2
++ bytes = gcmALIGN(Offset + 40, 8) - Offset;
++#else
++ /* Compute number of bytes required. */
++ bytes = gcmALIGN(Offset + 16, 8) - Offset;
++#endif
++ /* Cast the input pointer. */
++ logical = (gctUINT32_PTR) Logical;
++
++ if (logical != gcvNULL)
++ {
++ /* Not enough space? */
++ if (*Bytes < bytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Convert logical into hardware specific address. */
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address));
++
++ /* Store the WAIT/LINK address. */
++ Hardware->lastWaitLink = address;
++
++ /* Append WAIT(count). */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (waitCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++#if gcdMULTI_GPU && !gcdDISABLE_FE_L2
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | gcvCORE_3D_0_MASK;
++
++ logical[3] = 0;
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[5] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ logical[6] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | gcvCORE_3D_ALL_MASK;
++
++ logical[7] = 0;
++
++ /* Append LINK(2, address). */
++ logical[8] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[9] = address;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, waitCount
++ );
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", address + 8, logical[3]);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: LINK 0x%08x, #%lu",
++ address + 16, address, bytes
++ );
++#else
++
++ /* Append LINK(2, address). */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3] = address;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: WAIT %u", address, waitCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: LINK 0x%08x, #%lu",
++ address + 8, address, bytes
++ );
++#endif
++ if (WaitOffset != gcvNULL)
++ {
++ /* Return the offset pointer to WAIT command. */
++ *WaitOffset = 0;
++ }
++
++ if (WaitSize != gcvNULL)
++ {
++ /* Return number of bytes used by the WAIT command. */
++#if gcdMULTI_GPU && !gcdDISABLE_FE_L2
++ *WaitSize = 32;
++#else
++ *WaitSize = 8;
++#endif
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the WAIT/LINK command
++ ** sequence. */
++ *Bytes = bytes;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *WaitOffset=0x%x *WaitSize=%lu",
++ gcmOPT_VALUE(Bytes), gcmOPT_VALUE(WaitOffset),
++ gcmOPT_VALUE(WaitSize));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_End
++**
++** Append an END command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** END command at or gcvNULL just to query the size of the END command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append END. */
++ logical[0] =
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: END", Logical);
++
++ /* Make sure the CPU writes out the data to memory. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address));
++
++ Hardware->lastEnd = address;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckHARDWARE_ChipEnable(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gceCORE_3D_MASK ChipEnable,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x ChipEnable=0x%x *Bytes=%lu",
++ Hardware, Logical, ChipEnable, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append CHIPENABLE. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x0D & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ChipEnable;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: CHIPENABLE 0x%x", Logical, ChipEnable);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the CHIPENABLE command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_Nop
++**
++** Append a NOP command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** NOP command at or gcvNULL just to query the size of the NOP command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the NOP command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ /* Append NOP. */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: NOP", Logical);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the NOP command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Event
++**
++** Append an EVENT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the EVENT command at or gcvNULL just to query the size of the EVENT
++** command.
++**
++** gctUINT8 Event
++** Event ID to program.
++**
++** gceKERNEL_WHERE FromWhere
++** Location of the pipe to send the event.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the EVENT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT size;
++ gctUINT32 destination = 0;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Event=%u FromWhere=%d *Bytes=%lu",
++ Hardware, Logical, Event, FromWhere, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++ gcmkVERIFY_ARGUMENT(Event < 32);
++
++#if gcdMULTI_GPU
++ if (FromWhere == gcvKERNEL_COMMAND) FromWhere = gcvKERNEL_PIXEL;
++#endif
++
++ /* Determine the size of the command. */
++
++ size = (Hardware->extraEventStates && (FromWhere == gcvKERNEL_PIXEL))
++ ? gcmALIGN(8 + (1 + 5) * 4, 8) /* EVENT + 5 STATES */
++ : 8;
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < size)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ switch (FromWhere)
++ {
++ case gcvKERNEL_COMMAND:
++ /* From command processor. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ break;
++
++ case gcvKERNEL_PIXEL:
++ /* From pixel engine. */
++ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Append EVENT(Event, destiantion). */
++ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1] = ((((gctUINT32) (destination)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (Event) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ /* Make sure the event ID gets written out before GPU can access it. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ {
++ gctUINT32 phys;
++ gckOS_GetPhysicalAddress(Hardware->os, Logical, &phys);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%08x: EVENT %d", phys, Event);
++ }
++#endif
++
++ /* Append the extra states. These are needed for the chips that do not
++ ** support back-to-back events due to the async interface. The extra
++ ** states add the necessary delay to ensure that event IDs do not
++ ** collide. */
++ if (size > 8)
++ {
++ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0100) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++ logical[3] = 0;
++ logical[4] = 0;
++ logical[5] = 0;
++ logical[6] = 0;
++ logical[7] = 0;
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ if (Event < gcmCOUNTOF(Hardware->kernel->eventObj->queues))
++ {
++ gckOS_AtomSetMask(Hardware->pendingEvent, 1 << Event);
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT command. */
++ *Bytes = size;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_PipeSelect
++**
++** Append a PIPESELECT command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the PIPESELECT command at or gcvNULL just to query the size of the
++** PIPESELECT command.
++**
++** gcePIPE_SELECT Pipe
++** Pipe value to select.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the PIPESELECT command.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the PIPESELECT command. If 'Bytes' is gcvNULL, nothing will be
++** returned.
++*/
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Pipe=%d *Bytes=%lu",
++ Hardware, Logical, Pipe, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ /* Append a PipeSelect. */
++ if (Logical != gcvNULL)
++ {
++ gctUINT32 flush, stall;
++
++ if (*Bytes < 32)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ flush = (Pipe == gcvPIPE_2D)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++
++ stall = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LoadState(AQFlush, 1), flush. */
++ logical[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[1]
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical, flush);
++
++ /* LoadState(AQSempahore, 1), stall. */
++ logical[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ logical[3]
++ = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: SEMAPHORE 0x%x", logical + 2, stall);
++
++ /* Stall, stall. */
++ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ logical[5] = stall;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: STALL 0x%x", logical + 4, stall);
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ logical[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ logical[7] = (Pipe == gcvPIPE_2D)
++ ? 0x1
++ : 0x0;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: PIPE %d", logical + 6, Pipe);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the PIPESELECT command. */
++ *Bytes = 32;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Link
++**
++** Append a LINK command at the specified location in the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** the LINK command at or gcvNULL just to query the size of the LINK
++** command.
++**
++** gctUINT32 FetchAddress
++** Hardware address of destination of LINK.
++**
++** gctSIZE_T FetchSize
++** Number of bytes in destination of LINK.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the LINK command. If
++** 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the LINK command. If 'Bytes' is gcvNULL, nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT32 FetchSize,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gctUINT32 link;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x FetchAddress=0x%x FetchSize=%lu "
++ "*Bytes=%lu",
++ Hardware, Logical, FetchAddress, FetchSize,
++ gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL));
++
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < 8)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical + 1, FetchAddress));
++
++ /* Make sure the address got written before the LINK command. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical + 1));
++
++ /* Compute number of 64-byte aligned bytes to fetch. */
++ bytes = gcmALIGN(FetchAddress + FetchSize, 64) - FetchAddress;
++
++ /* Append LINK(bytes / 8), FetchAddress. */
++ link = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ gcmkONERROR(
++ gckOS_WriteMemory(Hardware->os, logical, link));
++
++ /* Memory barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, logical));
++
++#if gcdLINK_QUEUE_SIZE && !gcdPROCESS_ADDRESS_SPACE
++ if ((Hardware->kernel->virtualCommandBuffer)
++ && (Hardware->kernel->stuckDump > 2)
++ )
++ {
++ gctBOOL in;
++
++ gcmkVERIFY_OK(gckCOMMAND_AddressInKernelCommandBuffer(
++ Hardware->kernel->command, FetchAddress, &in));
++
++ if (in == gcvFALSE)
++ {
++ /* Record user command buffer and context buffer link
++ ** information for stuck dump.
++ **/
++ gckLINKQUEUE_Enqueue(
++ &Hardware->linkQueue, FetchAddress, FetchAddress + (gctUINT)bytes);
++ }
++ }
++#endif
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_UpdateQueueTail
++**
++** Update the tail of the command queue.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the start of the command queue.
++**
++** gctUINT32 Offset
++** Offset into the command queue of the tail (last command).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x",
++ Hardware, Logical, Offset);
++
++ /* Verify the hardware. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Force a barrier. */
++ gcmkONERROR(
++ gckOS_MemoryBarrier(Hardware->os, Logical));
++
++ /* Notify gckKERNEL object of change. */
++#if gcdMULTI_GPU
++ gcmkONERROR(
++ gckKERNEL_Notify(Hardware->kernel,
++ 0,
++ gcvNOTIFY_COMMAND_QUEUE,
++ gcvFALSE));
++#else
++ gcmkONERROR(
++ gckKERNEL_Notify(Hardware->kernel,
++ gcvNOTIFY_COMMAND_QUEUE,
++ gcvFALSE));
++#endif
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ gcmkONERROR(gcvSTATUS_DEVICE);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the memory in user space.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d",
++ Hardware, Logical, InUserSpace);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Convert logical address into a physical address. */
++ if (InUserSpace)
++ {
++ gcmkONERROR(gckOS_UserLogicalToPhysical(Hardware->os, Logical, &address));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++ }
++
++ /* For old MMU, get GPU address according to baseAddress. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress));
++
++ /* Subtract base address to get a GPU address. */
++ gcmkASSERT(address >= baseAddress);
++ address -= baseAddress;
++ }
++
++ /* Return hardware specific address. */
++ *Address = (Hardware->mmuVersion == 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)))
++ : address;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Interrupt
++**
++** Process an interrupt.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL InterruptValid
++** If gcvTRUE, this function will read the interrupt acknowledge
++** register, stores the data, and return whether or not the interrupt
++** is ours or not. If gcvFALSE, this functions will read the interrupt
++** acknowledge register and combine it with any stored value to handle
++** the event notifications.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++#if gcdMULTI_GPU
++ IN gctUINT CoreId,
++#endif
++ IN gctBOOL InterruptValid
++ )
++{
++ gckEVENT eventObj;
++ gctUINT32 data = 0;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x InterruptValid=%d", Hardware, InterruptValid);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Extract gckEVENT object. */
++ eventObj = Hardware->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ if (InterruptValid)
++ {
++ /* Read AQIntrAcknowledge register. */
++#if gcdMULTI_GPU
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterByCoreId(Hardware->os,
++ Hardware->core,
++ CoreId,
++ 0x00010,
++ &data));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00010,
++ &data));
++ }
++#else
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00010,
++ &data));
++#endif
++
++ if (data == 0)
++ {
++ /* Not our interrupt. */
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ }
++ else
++ {
++
++#if gcdINTERRUPT_STATISTIC
++ gckOS_AtomClearMask(Hardware->pendingEvent, data);
++#endif
++
++ /* Inform gckEVENT of the interrupt. */
++ status = gckEVENT_Interrupt(eventObj,
++#if gcdMULTI_GPU
++ CoreId,
++#endif
++ data);
++ }
++ }
++ else
++ {
++ /* Handle events. */
++ status = gckEVENT_Notify(eventObj, 0);
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryCommandBuffer
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Alignment
++** Pointer to a variable receiving the alignment for each command.
++**
++** gctSIZE_T * ReservedHead
++** Pointer to a variable receiving the number of reserved bytes at the
++** head of each command buffer.
++**
++** gctSIZE_T * ReservedTail
++** Pointer to a variable receiving the number of bytes reserved at the
++** tail of each command buffer.
++*/
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Alignment,
++ OUT gctUINT32 * ReservedHead,
++ OUT gctUINT32 * ReservedTail
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Alignment != gcvNULL)
++ {
++ /* Align every 8 bytes. */
++ *Alignment = 8;
++ }
++
++ if (ReservedHead != gcvNULL)
++ {
++ /* Reserve space for SelectPipe(). */
++ *ReservedHead = 32;
++ }
++
++ if (ReservedTail != gcvNULL)
++ {
++ /* Reserve space for Link(). */
++ *ReservedTail = 8;
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Alignment=%lu *ReservedHead=%lu *ReservedTail=%lu",
++ gcmOPT_VALUE(Alignment), gcmOPT_VALUE(ReservedHead),
++ gcmOPT_VALUE(ReservedTail));
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = 1U << 31;
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*SystemSize=%lu *SystemBaseAddress=%lu",
++ gcmOPT_VALUE(SystemSize), gcmOPT_VALUE(SystemBaseAddress));
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_3D
++/*******************************************************************************
++**
++** gckHARDWARE_QueryShaderCaps
++**
++** Query the shader capabilities.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT * VertexUniforms
++** Pointer to a variable receiving the number of uniforms in the vertex
++** shader.
++**
++** gctUINT * FragmentUniforms
++** Pointer to a variable receiving the number of uniforms in the
++** fragment shader.
++**
++** gctBOOL * UnifiedUnforms
++** Pointer to a variable receiving whether the uniformas are unified.
++*/
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctBOOL * UnifiedUnforms
++ )
++{
++ gctBOOL unifiedConst;
++ gctUINT32 vsConstMax;
++ gctUINT32 psConstMax;
++ gctUINT32 vsConstBase;
++ gctUINT32 psConstBase;
++ gctUINT32 ConstMax;
++
++ gcmkHEADER_ARG("Hardware=0x%x VertexUniforms=0x%x "
++ "FragmentUniforms=0x%x UnifiedUnforms=0x%x",
++ Hardware, VertexUniforms,
++ FragmentUniforms, UnifiedUnforms);
++
++ {if (Hardware->identity.numConstants > 256){ unifiedConst = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; ConstMax = Hardware->identity.numConstants; vsConstMax = 256; psConstMax = ConstMax - vsConstMax;}else if (Hardware->identity.numConstants == 256){ if (Hardware->identity.chipModel == gcv2000 && Hardware->identity.chipRevision == 0x5118) { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 64; ConstMax = 320; } else { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 256; ConstMax = 512; }}else{ unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 168; psConstMax = 64; ConstMax = 232;}};
++
++ if (VertexUniforms != gcvNULL)
++ {
++ /* Return the vs shader const count. */
++ *VertexUniforms = vsConstMax;
++ }
++
++ if (FragmentUniforms != gcvNULL)
++ {
++ /* Return the ps shader const count. */
++ *FragmentUniforms = psConstMax;
++ }
++
++ if (UnifiedUnforms != gcvNULL)
++ {
++ /* Return whether the uniformas are unified. */
++ *UnifiedUnforms = unifiedConst;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++ gctUINT32 idle;
++ gctUINT32 timer = 0, delay = 1;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert the logical address into physical address. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Setting page table to 0x%08X",
++ address);
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00400,
++ address));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00410,
++ address));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00404,
++ address));
++
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00408,
++ address));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0040C,
++ address));
++ }
++ else if (Hardware->enableMMU == gcvTRUE)
++ {
++ /* Execute prepared command sequence. */
++ gcmkONERROR(gckHARDWARE_Execute(
++ Hardware,
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address,
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes
++ ));
++
++ /* Wait until MMU configure finishes. */
++ do
++ {
++ gckOS_Delay(Hardware->os, delay);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(
++ Hardware->os,
++ Hardware->core,
++ 0x00004,
++ &idle));
++
++ timer += delay;
++ delay *= 2;
++
++#if gcdGPU_TIMEOUT
++ if (timer >= Hardware->kernel->timeOut)
++ {
++ /* Even if hardware is not reset correctly, let software
++ ** continue to avoid software stuck. Software will timeout again
++ ** and try to recover GPU in next timeout.
++ */
++ gcmkONERROR(gcvSTATUS_DEVICE);
++ }
++#endif
++ }
++ while (!(((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ));
++
++ /* Enable MMU. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os,
++ Hardware->core,
++ 0x0018C,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (gcvTRUE) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command;
++ gctUINT32_PTR buffer;
++ gctUINT32 bufferSize;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 flushSize;
++ gctUINT32 count;
++ gctUINT32 physical;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Verify the gckCOMMAND object pointer. */
++ command = Hardware->kernel->command;
++
++ /* Flush the memory controller. */
++ if (Hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, 8, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ gcmkONERROR(gckCOMMAND_Execute(command, 8));
++ }
++ else
++ {
++ flushSize = 16 * 4;
++
++ gcmkONERROR(gckCOMMAND_Reserve(
++ command, flushSize, &pointer, &bufferSize
++ ));
++
++ buffer = (gctUINT32_PTR) pointer;
++
++ count = ((gctUINT)bufferSize - flushSize + 7) >> 3;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(command->os, buffer, &physical));
++
++ /* Flush cache. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[3]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[4]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[5]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[6]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[7]
++ = physical + 8 * gcmSIZEOF(gctUINT32);
++
++ /* Flush MMU cache. */
++ buffer[8]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[9]
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ buffer[10]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[11]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ buffer[12]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ buffer[13]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ buffer[14]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[15]
++ = physical + flushSize;
++
++ gcmkONERROR(gckCOMMAND_Execute(command, flushSize));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetMMUStates(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gceSTATUS status;
++ gctUINT32 config, address;
++ gctUINT32_PTR buffer;
++ gctBOOL ace;
++ gctUINT32 reserveBytes = 16 + 4 * 4;
++
++ gctBOOL config2D;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Hardware->mmuVersion != 0);
++
++ ace = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_ACE);
++
++ if (ace)
++ {
++ reserveBytes += 8;
++ }
++
++ config2D = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D)
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_2D);
++
++ if (config2D)
++ {
++ reserveBytes +=
++ /* Pipe Select. */
++ 4 * 4
++ /* Configure MMU States. */
++ + 4 * 4
++ /* Semaphore stall */
++ + 4 * 8;
++ }
++
++ /* Convert logical address into physical address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, MtlbAddress, &config));
++
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Hardware->os, SafeAddress, &address));
++
++ if (address & 0x3F)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ switch (Mode)
++ {
++ case gcvMMU_MODE_1K:
++ if (config & 0x3FF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ case gcvMMU_MODE_4K:
++ if (config & 0xFFF)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (Logical != gcvNULL)
++ {
++ buffer = Logical;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = config;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = address;
++
++ if (ace)
++ {
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0068) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0;
++ }
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++
++ if (config2D)
++ {
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0x1;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = config;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = address;
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++
++ /* LoadState(AQPipeSelect, 1), pipe. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++ = 0x0;
++
++ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);;
++ }
++
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ *Bytes = reserveBytes;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_NO();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++/*******************************************************************************
++**
++** gckHARDWARE_ConfigMMU
++**
++** Append a MMU Configuration command sequence at the specified location in the command
++** queue. That command sequence consists of mmu configuration, LINK and WAIT/LINK.
++** LINK is fetched and paresed with new mmu configuration.
++**
++** If MMU Configuration is not changed between commit, change last WAIT/LINK to
++** link to ENTRY.
++**
++** -+-----------+-----------+-----------------------------------------
++** | WAIT/LINK | WAIT/LINK |
++** -+-----------+-----------+-----------------------------------------
++** | /|\
++** \|/ |
++** +--------------------+
++** | ENTRY | ... | LINK |
++** +--------------------+
++**
++** If MMU Configuration is changed between commit, change last WAIT/LINK to
++** link to MMU CONFIGURATION command sequence, and there are an EVNET and
++** an END at the end of this command sequence, when interrupt handler
++** receives this event, it will start FE at ENTRY to continue the command
++** buffer execution.
++**
++** -+-----------+-------------------+---------+---------+-----------+--
++** | WAIT/LINK | MMU CONFIGURATION | EVENT | END | WAIT/LINK |
++** -+-----------+-------------------+---------+---------+-----------+--
++** | /|\ /|\
++** +-------------+ |
++** +--------------------+
++** | ENTRY | ... | LINK |
++** +--------------------+
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command queue to append
++** command sequence at or gcvNULL just to query the size of the
++** command sequence.
++**
++** gctPOINTER MtlbLogical
++** Pointer to the current Master TLB.
++**
++** gctUINT32 Offset
++** Offset into command buffer required for alignment.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the command
++** sequence. If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** by the command sequence. If 'Bytes' is gcvNULL, nothing will
++** be returned.
++**
++** gctUINT32 * WaitLinkOffset
++** Pointer to a variable that will receive the offset of the WAIT/LINK command
++** from the specified logcial pointer.
++** If 'WaitLinkOffset' is gcvNULL nothing will be returned.
++**
++** gctSIZE_T * WaitLinkBytes
++** Pointer to a variable that will receive the number of bytes used by
++** the WAIT command.
++** If 'WaitLinkBytes' is gcvNULL nothing will be returned.
++*/
++gceSTATUS
++gckHARDWARE_ConfigMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER MtlbLogical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctSIZE_T * WaitLinkOffset,
++ OUT gctSIZE_T * WaitLinkBytes
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T bytes, bytesAligned;
++ gctUINT32 config;
++ gctUINT32_PTR buffer = (gctUINT32_PTR) Logical;
++ gctUINT32 physical;
++ gctUINT32 event;
++
++ gcmkHEADER_ARG("Hardware=0x%08X Logical=0x%08x MtlbLogical=0x%08X",
++ Hardware, Logical, MtlbLogical);
++
++ bytes
++ /* Flush cache states. */
++ = 18 * 4
++ /* MMU configuration states. */
++ + 6 * 4
++ /* EVENT. */
++ + 2 * 4
++ /* END. */
++ + 2 * 4
++ /* WAIT/LINK. */
++ + 4 * 4;
++
++ /* Compute number of bytes required. */
++ bytesAligned = gcmALIGN(Offset + bytes, 8) - Offset;
++
++ if (buffer != gcvNULL)
++ {
++ if (MtlbLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get physical address of this command buffer segment. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, buffer, &physical));
++
++ /* Get physical address of Master TLB. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, MtlbLogical, &config));
++
++ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++
++ /* Flush cache. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Flush tile status cache. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = physical + 10 * gcmSIZEOF(gctUINT32);
++
++ /* Configure MMU. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))));
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* LINK to next slot to flush FE FIFO. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = physical + 18 * 4;
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *buffer++
++ = config;
++
++ /* Arm the PE-FE Semaphore. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* STALL FE until PE is done flushing. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Event 29. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ event = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ event = ((((gctUINT32) (event)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (29) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++
++ *buffer++
++ = event;
++
++ /* Append END. */
++ *buffer++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ *Bytes = bytesAligned;
++ }
++
++ if (WaitLinkOffset != gcvNULL)
++ {
++ *WaitLinkOffset = bytes - 4 * 4;
++ }
++
++ if (WaitLinkBytes != gcvNULL)
++ {
++#if gcdMULTI_GPU
++ *WaitLinkBytes = 40;
++#else
++ *WaitLinkBytes = 4 * 4;
++#endif
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Index=%u Offset=%u", Hardware, Index, Offset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ *Address = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (Offset | (Index << 12)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0)));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle = 0;
++ gctINT retry, poll, pollCount;
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Wait=%d", Hardware, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++
++ /* If we have to wait, try 100 polls per millisecond. */
++ pollCount = Wait ? 100 : 1;
++
++ /* At most, try for 1 second. */
++ for (retry = 0; retry < 1000; ++retry)
++ {
++ /* If we have to wait, try 100 polls per millisecond. */
++ for (poll = pollCount; poll > 0; --poll)
++ {
++ /* Read register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++
++ /* See if we have to wait for FE idle. */
++ if (_IsGPUIdle(idle)
++ && (address == Hardware->lastEnd + 8)
++ )
++ {
++ /* FE is idle. */
++ break;
++ }
++ }
++
++ /* Check if we need to wait for FE and FE is busy. */
++ if (Wait && !_IsGPUIdle(idle))
++ {
++ /* Wait a little. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "%s: Waiting for idle: 0x%08X",
++ __FUNCTION__, idle);
++
++ gcmkVERIFY_OK(gckOS_Delay(Hardware->os, 1));
++ }
++ else
++ {
++ break;
++ }
++ }
++
++ /* Return idle to caller. */
++ *Data = idle;
++
++#if defined(EMULATOR)
++ /* Wait a little while until CModel FE gets END.
++ * END is supposed to be appended by caller.
++ */
++ gckOS_Delay(gcvNULL, 100);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gctUINT32 pipe;
++ gctUINT32 flush = 0;
++ gctBOOL flushTileStatus;
++ gctUINT32_PTR logical = (gctUINT32_PTR) Logical;
++ gceSTATUS status;
++ gctUINT32 reserveBytes
++ /* Semaphore/Stall */
++ = 4 * gcmSIZEOF(gctUINT32);
++
++ gcmkHEADER_ARG("Hardware=0x%x Flush=0x%x Logical=0x%x *Bytes=%lu",
++ Hardware, Flush, Logical, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get current pipe. */
++ pipe = Hardware->kernel->command->pipeSelect;
++
++ /* Flush tile status cache. */
++ flushTileStatus = Flush & gcvFLUSH_TILE_STATUS;
++
++ /* Flush 3D color cache. */
++ if ((Flush & gcvFLUSH_COLOR) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)));
++ }
++
++ /* Flush 3D depth cache. */
++ if ((Flush & gcvFLUSH_DEPTH) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Flush 3D texture cache. */
++ if ((Flush & gcvFLUSH_TEXTURE) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)));
++ }
++
++ /* Flush 2D cache. */
++ if ((Flush & gcvFLUSH_2D) && (pipe == 0x1))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)));
++ }
++
++#if gcdMULTI_GPU
++ /* Flush L2 cache. */
++ if ((Flush & gcvFLUSH_L2) && (pipe == 0x0))
++ {
++ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++#endif
++
++ /* Determine reserve bytes. */
++ if (flush)
++ {
++ reserveBytes += 2 * gcmSIZEOF(gctUINT32);
++ }
++
++ if (flushTileStatus)
++ {
++ reserveBytes += 2 * gcmSIZEOF(gctUINT32);
++ }
++
++ /* See if there is a valid flush. */
++ if ((flush == 0) && (flushTileStatus == gcvFALSE))
++ {
++ if (Bytes != gcvNULL)
++ {
++ /* No bytes required. */
++ *Bytes = 0;
++ }
++ }
++
++ else
++ {
++ /* Copy to command queue. */
++ if (Logical != gcvNULL)
++ {
++ if (*Bytes < reserveBytes)
++ {
++ /* Command queue too small. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++
++ if (flush)
++ {
++ /* Append LOAD_STATE to AQFlush. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *logical++
++ = flush;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH 0x%x", logical - 1, flush);
++ }
++
++ if (flushTileStatus)
++ {
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "0x%x: FLUSH TILE STATUS 0x%x", logical - 1, logical[-1]);
++ }
++
++ /* Semaphore. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++
++ /* Stall. */
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++
++ *logical++
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x05 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* bytes required. */
++ *Bytes = reserveBytes;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ )
++{
++#if gcdENABLE_3D
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Enable=%d Compression=%d",
++ Hardware, Enable, Compression);
++
++ /* Only process if fast clear is available. */
++ if ((((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ if (Enable == -1)
++ {
++ /* Determine automatic value for fast clear. */
++ Enable = ((Hardware->identity.chipModel != gcv500)
++ || (Hardware->identity.chipRevision >= 3)
++ ) ? 1 : 0;
++ }
++
++ if (Compression == -1)
++ {
++ /* Determine automatic value for compression. */
++ Compression = Enable
++ & (((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) );
++ }
++
++ /* Read AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &debug));
++
++ /* Set fast clear bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++ if (
++ ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) ||
++ (Hardware->identity.chipModel >= gcv4000))
++ {
++ /* Set compression bypass. */
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21))) | (((gctUINT32) ((gctUINT32) (Compression == 0) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21)));
++ }
++
++ /* Write back AQMemoryDebug register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00414,
++ debug));
++
++ /* Store fast clear and comprersison flags. */
++ Hardware->allowFastClear = Enable;
++ Hardware->allowCompression = Compression;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "FastClear=%d Compression=%d", Enable, Compression);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ return gcvSTATUS_OK;
++#endif
++}
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++}
++gcePOWER_FLAGS;
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++static gctCONST_STRING
++_PowerEnum(gceCHIPPOWERSTATE State)
++{
++ const gctCONST_STRING states[] =
++ {
++ gcmSTRING(gcvPOWER_ON),
++ gcmSTRING(gcvPOWER_OFF),
++ gcmSTRING(gcvPOWER_IDLE),
++ gcmSTRING(gcvPOWER_SUSPEND),
++ gcmSTRING(gcvPOWER_SUSPEND_ATPOWERON),
++ gcmSTRING(gcvPOWER_OFF_ATPOWERON),
++ gcmSTRING(gcvPOWER_IDLE_BROADCAST),
++ gcmSTRING(gcvPOWER_SUSPEND_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_BROADCAST),
++ gcmSTRING(gcvPOWER_OFF_RECOVERY),
++ gcmSTRING(gcvPOWER_OFF_TIMEOUT),
++ gcmSTRING(gcvPOWER_ON_AUTO)
++ };
++
++ if ((State >= gcvPOWER_ON) && (State <= gcvPOWER_ON_AUTO))
++ {
++ return states[State - gcvPOWER_ON];
++ }
++
++ return "unknown";
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag, clock;
++ gctPOINTER buffer;
++ gctUINT32 bytes, requested;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL broadcast = gcvFALSE;
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++ gctUINT32 process, thread;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL commandStarted = gcvFALSE;
++ gctBOOL isrStarted = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++ gctBOOL global = gcvFALSE;
++ gctBOOL globalAcquired = gcvFALSE;
++ gctBOOL configMmu = gcvFALSE;
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_RELEASE,
++ /* OFF */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ /* Clocks. */
++ static const gctUINT clocks[4] =
++ {
++ /* gcvPOWER_ON */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (64) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_OFF */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_IDLE */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++
++ /* gcvPOWER_SUSPEND */
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))),
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d(%s)",
++ State, _PowerEnum(State));
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ if (Hardware->powerManagement == gcvFALSE
++ && State != gcvPOWER_ON
++ )
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State != gcvPOWER_ON)
++ {
++ /* Called from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ status = gcvSTATUS_INVALID_REQUEST;
++ goto OnError;
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ clock = clocks[State];
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ if (State == gcvPOWER_ON)
++ {
++ clock = ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (Hardware->powerOnFscaleVal) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)));
++ }
++#endif
++
++ if (State == gcvPOWER_SUSPEND && Hardware->chipPowerState == gcvPOWER_OFF && broadcast)
++ {
++#if gcdPOWER_SUSPEND_WHEN_IDLE
++ /* Do nothing */
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++#else
++ /* Clock should be on when switch power from off to suspend */
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) ;
++#endif
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE or SUSPEND. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Power Off GPU[%d] at %u [supposed to be at %u]",
++ Hardware->core, currentTime, Hardware->powerOffTime);
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* If this is an internal power management, we have to check if we can grab
++ ** the global power semaphore. If we cannot, we have to wait until the
++ ** external world changes power management. */
++ if (!global)
++ {
++ /* Try to acquire the global semaphore. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Called from thread routine which should NEVER sleep.*/
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Release the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Releasing the power mutex.");
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ /* Wait for the semaphore. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Waiting for global semaphore.");
++ gcmkONERROR(gckOS_AcquireSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvTRUE;
++
++ /* Acquire the power mutex. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Reacquiring the power mutex.");
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ mutexAcquired = gcvTRUE;
++
++ /* chipPowerState may be changed by external world during the time
++ ** we give up powerMutex, so updating flag now is necessary. */
++ flag = flags[Hardware->chipPowerState][State];
++
++ if (flag == 0)
++ {
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++ mutexAcquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Error. */
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore again. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ else
++ {
++ if (State == gcvPOWER_OFF || State == gcvPOWER_SUSPEND || State == gcvPOWER_IDLE)
++ {
++ /* Acquire the global semaphore if it has not been acquired. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status == gcvSTATUS_OK)
++ {
++ globalAcquired = gcvTRUE;
++ }
++ else if (status != gcvSTATUS_TIMEOUT)
++ {
++ /* Other errors. */
++ gcmkONERROR(status);
++ }
++ /* Ignore gcvSTATUS_TIMEOUT and leave globalAcquired as gcvFALSE.
++ ** gcvSTATUS_TIMEOUT means global semaphore has already
++ ** been acquired before this operation, so even if we fail,
++ ** we should not release it in our error handling. It should be
++ ** released by the next successful global gcvPOWER_ON. */
++ }
++
++ /* Global power management can't be aborted, so sync with
++ ** proceeding last commit. */
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ for (;;)
++ {
++ /* Check if GPU is present and awake. */
++ status = _IsGPUPresent(Hardware);
++
++ /* Check if the GPU is not responding. */
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Turn off the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvFALSE, gcvFALSE));
++
++ Hardware->clockState = gcvFALSE;
++ Hardware->powerState = gcvFALSE;
++
++ /* Wait a little. */
++ gckOS_Delay(os, 1);
++
++ /* Turn on the power and clock. */
++ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++
++ /* We need to initialize the hardware and start the command
++ * processor. */
++ flag |= gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_START;
++ }
++ else
++ {
++ /* Test for error. */
++ gcmkONERROR(status);
++
++ /* Break out of loop. */
++ break;
++ }
++ }
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ gctBOOL idle;
++ gctINT32 atomValue;
++
++ /* For global operation, all pending commits have already been
++ ** blocked by globalSemaphore or powerSemaphore.*/
++ if (!global)
++ {
++ /* Check commit atom. */
++ gcmkONERROR(gckOS_AtomGet(os, command->atomCommit, &atomValue));
++
++ if (atomValue > 0)
++ {
++ /* Commits are pending - abort power management. */
++ status = broadcast ? gcvSTATUS_CHIP_NOT_READY
++ : gcvSTATUS_MORE_DATA;
++ goto OnError;
++ }
++ }
++
++ if (broadcast)
++ {
++ /* Check for idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle));
++
++ if (!idle)
++ {
++ status = gcvSTATUS_CHIP_NOT_READY;
++ goto OnError;
++ }
++ }
++
++ else
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvTRUE));
++ commitEntered = gcvTRUE;
++
++ /* Get the size of the flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(Hardware,
++ gcvFLUSH_ALL,
++ gcvNULL,
++ &requested));
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command,
++ requested,
++ &buffer,
++ &bytes));
++
++ /* Append a flush. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ Hardware, gcvFLUSH_ALL, buffer, &bytes
++ ));
++
++ /* Execute the command queue. */
++ gcmkONERROR(gckCOMMAND_Execute(command, requested));
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ commitEntered = gcvFALSE;
++
++ /* Wait to finish all commands. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE, gcvCORE_3D_ALL_MASK));
++#else
++ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE));
++#endif
++ }
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++ }
++
++ if (flag & gcvPOWER_FLAG_STOP)
++ {
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ /* Stop the Isr. */
++ if (Hardware->stopIsr)
++ {
++ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext));
++ }
++ }
++
++ /* Flush Cache before Power Off. */
++ if (flag & gcvPOWER_FLAG_POWER_OFF)
++ {
++ if (Hardware->clockState == gcvFALSE)
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ gcvTRUE,
++ gcvTRUE));
++
++ Hardware->clockState = gcvTRUE;
++
++ if (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE)
++ {
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clocks[0]));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clocks[0])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++ }
++
++ gcmkONERROR(gckCOMMAND_Start(command));
++
++ gcmkONERROR(_FlushCache(Hardware, command));
++
++ gckOS_Delay(gcvNULL, 1);
++
++ /* Stop the command parser. */
++ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE));
++
++ flag |= gcvPOWER_FLAG_CLOCK_OFF;
++ }
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++ /* Only process this when hardware is enabled. */
++ if (Hardware->clockState && Hardware->powerState
++ /* Don't touch clock control if dynamic frequency scaling is available. */
++ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE
++ )
++ {
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ if (Hardware->identity.chipModel == gcv4000
++ && ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222)))
++ {
++ clock &= ~2U;
++ }
++ }
++
++ /* Write the clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++ }
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(Hardware,
++ Hardware->allowFastClear,
++ Hardware->allowCompression));
++
++ /* Force the command queue to reload the next context. */
++ command->currContext = gcvNULL;
++
++ /* Need to config mmu after command start. */
++ configMmu = gcvTRUE;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ Hardware->core,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++ if (flag & gcvPOWER_FLAG_START)
++ {
++ /* Start the command processor. */
++ gcmkONERROR(gckCOMMAND_Start(command));
++ commandStarted = gcvTRUE;
++
++ if (Hardware->startIsr)
++ {
++ /* Start the Isr. */
++ gcmkONERROR(Hardware->startIsr(Hardware->isrContext));
++ isrStarted = gcvTRUE;
++ }
++ }
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++
++ if (global)
++ {
++ /* Verify global semaphore has been acquired already before
++ ** we release it.
++ ** If it was acquired, gckOS_TryAcquireSemaphore will return
++ ** gcvSTATUS_TIMEOUT and we release it. Otherwise, global
++ ** semaphore will be acquried now, but it still is released
++ ** immediately. */
++ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore);
++ if (status != gcvSTATUS_TIMEOUT)
++ {
++ gcmkONERROR(status);
++ }
++
++ /* Release the global semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore));
++ globalAcquired = gcvFALSE;
++ }
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++#if gcdDVFS
++ if (State == gcvPOWER_ON && Hardware->kernel->dvfs)
++ {
++ gckDVFS_Start(Hardware->kernel->dvfs);
++ }
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++ /* Reset power off time */
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++
++ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND)
++ {
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (commandStarted)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Stop(command, gcvFALSE));
++ }
++
++ if (isrStarted)
++ {
++ gcmkVERIFY_OK(Hardware->stopIsr(Hardware->isrContext));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvTRUE));
++ }
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (globalAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ Hardware->globalSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ if(!Hardware->powerManagementLock)
++ {
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++
++ Hardware->powerManagement = PowerManagement;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementLock
++**
++** Disable dynamic GPU power management switch.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL Lock
++** Power Mangement Lock State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetPowerManagementLock(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Lock
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagementLock = Lock;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++/*******************************************************************************
++**
++** gckHARDWARE_SetGpuProfiler
++**
++** Configure GPU profiler function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL GpuProfiler
++** GOU Profiler State.
++**
++*/
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (GpuProfiler == gcvTRUE)
++ {
++ gctUINT32 data = 0;
++
++ /* Need to disable clock gating when doing profiling. */
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress +
++ 0x00100,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++
++
++ gcmkVERIFY_OK(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00100,
++ data));
++ }
++
++ Hardware->gpuProfiler = GpuProfiler;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ )
++{
++ gceSTATUS status;
++ gctUINT32 clock;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x FscaleValue=%d", Hardware, FscaleValue);
++
++ gcmkVERIFY_ARGUMENT(FscaleValue > 0 && FscaleValue <= 64);
++
++ gcmkONERROR(
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ Hardware->powerOnFscaleVal = FscaleValue;
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gctUINT32 data;
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ &data));
++
++ /* Disable all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (FscaleValue) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Done loading the frequency scaler. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ /* Restore all clock gating. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ Hardware->powerBaseAddress
++ + 0x00104,
++ data));
++ }
++
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ )
++{
++ *FscaleValue = Hardware->powerOnFscaleVal;
++ *MinFscaleValue = Hardware->minFscaleValue;
++ *MaxFscaleValue = 64;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetMinFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT MinFscaleValue
++ )
++{
++ if (MinFscaleValue >= 1 && MinFscaleValue <= 64)
++ {
++ Hardware->minFscaleValue = MinFscaleValue;
++ }
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++)
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle, address;
++ gctBOOL isIdle;
++#if gcdMULTI_GPU > 1
++ gctUINT32 idle3D1 = 0;
++ gctUINT32 address3D1;
++ gctBOOL isIdle3D1 = gcvFALSE;
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 pendingInterrupt;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ isIdle = gcvTRUE;
++#if gcdMULTI_GPU > 1
++ isIdle3D1 = gcvTRUE;
++#endif
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle));
++
++#if gcdMULTI_GPU > 1
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ gcmkONERROR(
++ gckOS_ReadRegisterByCoreId(Hardware->os,
++ Hardware->core,
++ gcvCORE_3D_1_ID,
++ 0x00004,
++ &idle3D1));
++ }
++#endif
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ isIdle = gcvFALSE;
++ }
++
++ else
++ {
++#if gcdSECURITY
++ isIdle = gcvTRUE;
++ address = 0;
++#else
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00664,
++ &address));
++
++ /* Test if address is inside the last WAIT/LINK sequence. */
++ if ((address >= Hardware->lastWaitLink)
++#if gcdMULTI_GPU
++ && (address <= Hardware->lastWaitLink + 40)
++#else
++ && (address <= Hardware->lastWaitLink + 16)
++#endif
++ )
++ {
++ /* FE is in last WAIT/LINK and the pipe is idle. */
++ isIdle = gcvTRUE;
++ }
++ else
++ {
++ /* FE is not in WAIT/LINK yet. */
++ isIdle = gcvFALSE;
++ }
++#endif
++ }
++
++#if gcdMULTI_GPU > 1
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle3D1)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle3D1)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ isIdle3D1 = gcvFALSE;
++ }
++
++ else
++ {
++ /* Read the current FE address. */
++ gcmkONERROR(gckOS_ReadRegisterByCoreId(Hardware->os,
++ Hardware->core,
++ gcvCORE_3D_1_ID,
++ 0x00664,
++ &address3D1));
++
++ /* Test if address is inside the last WAIT/LINK sequence. */
++ if ((address3D1 >= Hardware->lastWaitLink)
++ && (address3D1 <= Hardware->lastWaitLink + 40)
++ )
++ {
++ /* FE is in last WAIT/LINK and the pipe is idle. */
++ isIdle3D1 = gcvTRUE;
++ }
++ else
++ {
++ /* FE is not in WAIT/LINK yet. */
++ isIdle3D1 = gcvFALSE;
++ }
++ }
++ }
++#endif
++
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkONERROR(gckOS_AtomGet(
++ Hardware->os,
++ Hardware->kernel->eventObj->interruptCount,
++ &pendingInterrupt
++ ));
++
++ if (pendingInterrupt)
++ {
++ isIdle = gcvFALSE;
++ }
++#endif
++
++#if gcdMULTI_GPU > 1
++ if (Hardware->core == gcvCORE_MAJOR)
++ {
++ *IsIdle = (isIdle & isIdle3D1);
++ }
++ else
++#endif
++ {
++ *IsIdle = isIdle;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** Handy macros that will help in reading those debug registers.
++*/
++
++#define gcmkREAD_DEBUG_REGISTER(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &profiler->data))
++
++#define gcmkREAD_DEBUG_REGISTER_N(control, block, index, data) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ index))); \
++ gcmkONERROR(\
++ gckOS_ReadRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_SIGNALS_##block##_Address, \
++ &data))
++
++#define gcmkRESET_DEBUG_REGISTER(control, block) \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 15))); \
++ gcmkONERROR(\
++ gckOS_WriteRegisterEx(Hardware->os, \
++ Hardware->core, \
++ GC_DEBUG_CONTROL##control##_Address, \
++ gcmSETFIELD(0, \
++ GC_DEBUG_CONTROL##control, \
++ block, \
++ 0)))
++
++/*******************************************************************************
++**
++** gckHARDWARE_ProfileEngine2D
++**
++** Read the profile registers available in the 2D engine and sets them in the
++** profile. The function will also reset the pixelsRendered counter every time.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** OPTIONAL gcs2D_PROFILE_PTR Profile
++** Pointer to a gcs2D_Profile structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ )
++{
++ gceSTATUS status;
++ gcs2D_PROFILE_PTR profiler = Profile;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Profile != gcvNULL)
++ {
++ /* Read the cycle count. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &Profile->cycleCount));
++
++ /* Read pixels rendered by 2D engine. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &profiler->pixelsRendered));
++
++ /* Reset counter. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++ gctUINT i, clock;
++ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn;
++ gctUINT32 totalRead, totalWrite;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
++#if VIVANTE_PROFILER_CONTEXT
++#define gcmkUPDATE_PROFILE_DATA(data) \
++ profilerHistroy->data += profiler->data
++
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ )
++{
++ gceSTATUS status;
++ gckCOMMAND command = Hardware->kernel->command;
++ gcsPROFILER_COUNTERS * profiler = Counters;
++
++ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os, command->mutexContextSeq, gcvINFINITE
++ ));
++
++ /* Read the counters. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ profiler, &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ /* Reset counters. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS)
++ ));
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os, command->mutexContextSeq
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gctUINT32
++CalcDelta(
++ IN gctUINT32 new,
++ IN gctUINT32 old
++ )
++{
++ if (new >= old)
++ {
++ return new - old;
++ }
++ else
++ {
++ return (gctUINT32)((gctUINT64)new + 0x100000000ll - old);
++ }
++}
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gcsPROFILER_COUNTERS * profiler = &Context->latestProfiler;
++ gcsPROFILER_COUNTERS * profilerHistroy = &Context->histroyProfiler;
++ gctUINT i, clock;
++ gctUINT32 colorKilled = 0, colorDrawn = 0, depthKilled = 0, depthDrawn = 0;
++ gctUINT32 totalRead, totalWrite;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 temp;
++ gctBOOL needResetShader = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x Context=0x%x", Hardware, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT);
++
++ chipModel = Hardware->identity.chipModel;
++ chipRevision = Hardware->identity.chipRevision;
++ if (chipModel == gcv2000 || (chipModel == gcv2100 && chipRevision == 0x5118))
++ {
++ needResetShader = gcvTRUE;
++ }
++
++ /* Read the counters. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &profiler->gpuCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &profiler->gpuTotalCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuTotalCyclesCounter);
++
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &profiler->gpuIdleCyclesCounter));
++ gcmkUPDATE_PROFILE_DATA(gpuIdleCyclesCounter);
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ profiler->gpuTotalRead64BytesPerFrame = 0;
++ profiler->gpuTotalWrite64BytesPerFrame = 0;
++ profiler->pe_pixel_count_killed_by_color_pipe = 0;
++ profiler->pe_pixel_count_killed_by_depth_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_color_pipe = 0;
++ profiler->pe_pixel_count_drawn_by_depth_pipe = 0;
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* BW */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &totalRead));
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &totalWrite));
++
++ profiler->gpuTotalRead64BytesPerFrame += totalRead;
++ profiler->gpuTotalWrite64BytesPerFrame += totalWrite;
++ gcmkUPDATE_PROFILE_DATA(gpuTotalRead64BytesPerFrame);
++ gcmkUPDATE_PROFILE_DATA(gpuTotalWrite64BytesPerFrame);
++
++ /* PE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn));
++
++ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled;
++ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled;
++ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn;
++ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn;
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_depth_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_color_pipe);
++ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_depth_pipe);
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++
++ /* Reset counters. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0));
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* SH */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->ps_inst_counter;
++ profiler->ps_inst_counter = CalcDelta(temp, Context->prevPSInstCount);
++ Context->prevPSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(ps_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_pixel_counter;
++ profiler->rendered_pixel_counter = CalcDelta(temp, Context->prevPSPixelCount);
++ Context->prevPSPixelCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_pixel_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vs_inst_counter;
++ profiler->vs_inst_counter = CalcDelta(temp, Context->prevVSInstCount);
++ Context->prevVSInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vs_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter));
++ if (needResetShader)
++ {
++ temp = profiler->rendered_vertice_counter;
++ profiler->rendered_vertice_counter = CalcDelta(temp, Context->prevVSVertexCount);
++ Context->prevVSVertexCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(rendered_vertice_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_branch_inst_counter;
++ profiler->vtx_branch_inst_counter = CalcDelta(temp, Context->prevVSBranchInstCount);
++ Context->prevVSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->vtx_texld_inst_counter;
++ profiler->vtx_texld_inst_counter = CalcDelta(temp, Context->prevVSTexInstCount);
++ Context->prevVSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(vtx_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_branch_inst_counter;
++ profiler->pxl_branch_inst_counter = CalcDelta(temp, Context->prevPSBranchInstCount);
++ Context->prevPSBranchInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_branch_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter));
++ if (needResetShader)
++ {
++ temp = profiler->pxl_texld_inst_counter;
++ profiler->pxl_texld_inst_counter = CalcDelta(temp, Context->prevPSTexInstCount);
++ Context->prevPSTexInstCount = temp;
++ }
++ gcmkUPDATE_PROFILE_DATA(pxl_texld_inst_counter);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* PA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_vtx_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_input_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_output_prim_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_depth_clipped_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_trivial_rejected_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter));
++ gcmkUPDATE_PROFILE_DATA(pa_culled_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* SE */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_triangle_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count));
++ gcmkUPDATE_PROFILE_DATA(se_culled_lines_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* RA */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_pixel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_quad_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z));
++ gcmkUPDATE_PROFILE_DATA(ra_valid_quad_count_after_early_z);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count));
++ gcmkUPDATE_PROFILE_DATA(ra_total_primitive_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_pipe_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter));
++ gcmkUPDATE_PROFILE_DATA(ra_prefetch_cache_miss_counter);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))
++));
++
++ /* TX */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_bilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_trilinear_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_discarded_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests));
++ gcmkUPDATE_PROFILE_DATA(tx_total_texture_requests);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count));
++ gcmkUPDATE_PROFILE_DATA(tx_mem_read_in_8B_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_hit_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count));
++ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_texel_count);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24)))
++));
++
++ /* MC */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP));
++ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_IP);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline));
++ gcmkUPDATE_PROFILE_DATA(mc_total_write_req_8B_from_pipeline);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0)))
++));
++
++ /* HI */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_read_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_request_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled));
++ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_data_stalled);
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) ));
++gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))
++));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++
++#if VIVANTE_PROFILER_NEW
++gceSTATUS
++gckHARDWARE_InitProfiler(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 control;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &control));
++ /* Enable debug register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11)))));
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_ResetGPU(
++ IN gckHARDWARE Hardware,
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ Hardware->powerBaseAddress +
++ 0x00104,
++ 0x00000000));
++
++ control = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17)));
++
++ /* Disable pulse-eater. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x0010C,
++ control));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)))));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ 0x00000900));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ Core,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++#if gcdMULTI_GPU > 1
++ if (Core == gcvCORE_MAJOR)
++ {
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterByCoreId(Os,
++ Core,
++ gcvCORE_3D_1_ID,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++ }
++#endif
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ Core,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++#if gcdMULTI_GPU > 1
++ if (Core == gcvCORE_MAJOR)
++ {
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterByCoreId(Os,
++ Core,
++ gcvCORE_3D_1_ID,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++ }
++#endif
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++
++ /* Hardware reset. */
++ status = gckOS_ResetGPU(Hardware->os, Hardware->core);
++
++ if (gcmIS_ERROR(status))
++ {
++ if (Hardware->identity.chipRevision < 0x4600)
++ {
++ /* Not supported - we need the isolation bit. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ /* Soft reset. */
++ gcmkONERROR(_ResetGPU(Hardware, Hardware->os, Hardware->core));
++ }
++
++ /* Initialize hardware. */
++ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware));
++
++ /* Jump to address into which GPU should run if it doesn't stuck. */
++ gcmkONERROR(gckHARDWARE_Execute(Hardware, Hardware->kernel->restoreAddress, 16));
++
++ gcmkPRINT("[galcore]: recovery done");
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkPRINT("[galcore]: Hardware not reset successfully, give up");
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Test if we have a new Memory Controller. */
++ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))))
++ {
++ /* No base address required. */
++ *BaseAddress = 0;
++ }
++ else
++ {
++ /* Get the base address from the OS. */
++ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, BaseAddress));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ )
++{
++ gctBOOL need = gcvFALSE;
++
++ gcmkHEADER_ARG("Hardware=0x%x State=0x%08x", Hardware, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(NeedBase != gcvNULL);
++
++ /* Make sure this is a load state. */
++ if (((((gctUINT32) (State)) >> (0 ? 31:27) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))))
++ {
++#if gcdENABLE_3D
++ /* Get the state address. */
++ switch ((((((gctUINT32) (State)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) ))
++ {
++ case 0x0596:
++ case 0x0597:
++ case 0x0599:
++ case 0x059A:
++ case 0x05A9:
++ /* These states need a TRUE physical address. */
++ need = gcvTRUE;
++ break;
++ }
++#else
++ /* 2D addresses don't need a base address. */
++#endif
++ }
++
++ /* Return the flag. */
++ *NeedBase = need;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedBase=%d", *NeedBase);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Hardware=0x%x, StartIsr=0x%x, StopIsr=0x%x, Context=0x%x",
++ Hardware, StartIsr, StopIsr, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (StartIsr == gcvNULL ||
++ StopIsr == gcvNULL ||
++ Context == gcvNULL)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ Hardware->startIsr = StartIsr;
++ Hardware->stopIsr = StopIsr;
++ Hardware->isrContext = Context;
++
++ /* Success. */
++ gcmkFOOTER();
++
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_Compose
++**
++** Start a composition.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ )
++{
++#if gcdENABLE_3D
++ gceSTATUS status;
++ gctUINT32_PTR triggerState;
++
++ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x Logical=0x%x"
++ " Offset=%d Size=%d EventID=%d",
++ Hardware, Physical, Logical, Offset, Size, EventID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(((Size + 8) & 63) == 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Program the trigger state. */
++ triggerState = (gctUINT32_PTR) ((gctUINT8_PTR) Logical + Offset + Size);
++ triggerState[0] = 0x0C03;
++ triggerState[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16))) | (((gctUINT32) ((gctUINT32) (EventID) & ((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16)))
++ ;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Hardware->os, ProcessID, gcvNULL,
++ (gctUINT32)Physical, Logical, Offset + Size
++ ));
++#endif
++
++ /* Start composition. */
++ gcmkONERROR(gckOS_WriteRegisterEx(
++ Hardware->os, Hardware->core, 0x00554,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)))
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#else
++ /* Return the status. */
++ return gcvSTATUS_NOT_SUPPORTED;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_IsFeatureAvailable
++**
++** Verifies whether the specified feature is available in hardware.
++**
++** INPUT:
++**
++** gckHARDWARE Hardware
++** Pointer to an gckHARDWARE object.
++**
++** gceFEATURE Feature
++** Feature to be verified.
++*/
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ )
++{
++ gctBOOL available;
++
++ gcmkHEADER_ARG("Hardware=0x%x Feature=%d", Hardware, Feature);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Only features needed by common kernel logic added here. */
++ switch (Feature)
++ {
++ case gcvFEATURE_END_EVENT:
++ /*available = gcmVERIFYFIELDVALUE(Hardware->identity.chipMinorFeatures2,
++ GC_MINOR_FEATURES2, END_EVENT, AVAILABLE
++ );*/
++ available = gcvFALSE;
++ break;
++
++ case gcvFEATURE_MC20:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))));
++ break;
++
++ case gcvFEATURE_EARLY_Z:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ case gcvFEATURE_HZ:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))));
++ break;
++
++ case gcvFEATURE_NEW_HZ:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))));
++ break;
++
++ case gcvFEATURE_FAST_MSAA:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))));
++ break;
++
++ case gcvFEATURE_SMALL_MSAA:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++ break;
++
++ case gcvFEATURE_DYNAMIC_FREQUENCY_SCALING:
++ /* This feature doesn't apply for 2D cores. */
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 14:14) & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))))
++ && ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++
++ if (Hardware->identity.chipModel == gcv1000 &&
++ (Hardware->identity.chipRevision == 0x5039 ||
++ Hardware->identity.chipRevision == 0x5040))
++ {
++ available = gcvFALSE;
++ }
++ break;
++
++ case gcvFEATURE_ACE:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++ break;
++
++ case gcvFEATURE_HALTI2:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_2D:
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))));
++ break;
++
++ case gcvFEATURE_PIPE_3D:
++#if gcdENABLE_3D
++ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))));
++#else
++ available = gcvFALSE;
++#endif
++ break;
++
++ case gcvFEATURE_FC_FLUSH_STALL:
++ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 31:31) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))));
++ break;
++
++ default:
++ gcmkFATAL("Invalid feature has been requested.");
++ available = gcvFALSE;
++ }
++
++ /* Return result. */
++ gcmkFOOTER_ARG("%d", available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE);
++ return available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpMMUException
++**
++** Dump the MMU debug info on an MMU exception.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ )
++{
++ gctUINT32 mmu = 0;
++ gctUINT32 mmuStatus = 0;
++ gctUINT32 address = 0;
++ gctUINT32 i = 0;
++ gctUINT32 mtlb = 0;
++ gctUINT32 stlb = 0;
++ gctUINT32 offset = 0;
++#if gcdPROCESS_ADDRESS_SPACE
++ gcsDATABASE_PTR database;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkPRINT("GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ Hardware->core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** MMU ERROR DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00188,
++ &mmuStatus));
++
++ gcmkPRINT(" MMU status = 0x%08X\n", mmuStatus);
++
++ for (i = 0; i < 4; i += 1)
++ {
++ mmu = mmuStatus & 0xF;
++ mmuStatus >>= 4;
++
++ if (mmu == 0)
++ {
++ continue;
++ }
++
++ switch (mmu)
++ {
++ case 1:
++ gcmkPRINT(" MMU%d: slave not present\n", i);
++ break;
++
++ case 2:
++ gcmkPRINT(" MMU%d: page not present\n", i);
++ break;
++
++ case 3:
++ gcmkPRINT(" MMU%d: write violation\n", i);
++ break;
++
++ default:
++ gcmkPRINT(" MMU%d: unknown state\n", i);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00190 + i * 4,
++ &address));
++
++ mtlb = (address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ stlb = (address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++ offset = address & gcdMMU_OFFSET_4K_MASK;
++
++ gcmkPRINT(" MMU%d: exception address = 0x%08X\n", i, address);
++
++ gcmkPRINT(" MTLB entry = %d\n", mtlb);
++
++ gcmkPRINT(" STLB entry = %d\n", stlb);
++
++ gcmkPRINT(" Offset = 0x%08X (%d)\n", offset, offset);
++
++ gckMMU_DumpPageTableEntry(Hardware->kernel->mmu, address);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ for (i = 0; i < gcmCOUNTOF(Hardware->kernel->db->db); ++i)
++ {
++ for (database = Hardware->kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ gcmkPRINT(" database [%d] :", database->processID);
++ gckMMU_DumpPageTableEntry(database->mmu, address);
++ }
++ }
++#endif
++ }
++
++ gckHARDWARE_DumpGPUState(Hardware);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_DumpGPUState
++**
++** Dump the GPU debug registers.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ )
++{
++ static gctCONST_STRING _cmdState[] =
++ {
++ "PAR_IDLE_ST", "PAR_DEC_ST", "PAR_ADR0_ST", "PAR_LOAD0_ST",
++ "PAR_ADR1_ST", "PAR_LOAD1_ST", "PAR_3DADR_ST", "PAR_3DCMD_ST",
++ "PAR_3DCNTL_ST", "PAR_3DIDXCNTL_ST", "PAR_INITREQDMA_ST",
++ "PAR_DRAWIDX_ST", "PAR_DRAW_ST", "PAR_2DRECT0_ST", "PAR_2DRECT1_ST",
++ "PAR_2DDATA0_ST", "PAR_2DDATA1_ST", "PAR_WAITFIFO_ST", "PAR_WAIT_ST",
++ "PAR_LINK_ST", "PAR_END_ST", "PAR_STALL_ST"
++ };
++
++ static gctCONST_STRING _cmdDmaState[] =
++ {
++ "CMD_IDLE_ST", "CMD_START_ST", "CMD_REQ_ST", "CMD_END_ST"
++ };
++
++ static gctCONST_STRING _cmdFetState[] =
++ {
++ "FET_IDLE_ST", "FET_RAMVALID_ST", "FET_VALID_ST"
++ };
++
++ static gctCONST_STRING _reqDmaState[] =
++ {
++ "REQ_IDLE_ST", "REQ_WAITIDX_ST", "REQ_CAL_ST"
++ };
++
++ static gctCONST_STRING _calState[] =
++ {
++ "CAL_IDLE_ST", "CAL_LDADR_ST", "CAL_IDXCALC_ST"
++ };
++
++ static gctCONST_STRING _veReqState[] =
++ {
++ "VER_IDLE_ST", "VER_CKCACHE_ST", "VER_MISS_ST"
++ };
++
++ static gcsiDEBUG_REGISTERS _dbgRegs[] =
++ {
++ { "RA", 0x474, 16, 0x448, 16, 0x12344321 },
++ { "TX", 0x474, 24, 0x44C, 16, 0x12211221 },
++ { "FE", 0x470, 0, 0x450, 16, 0xBABEF00D },
++ { "PE", 0x470, 16, 0x454, 16, 0xBABEF00D },
++ { "DE", 0x470, 8, 0x458, 16, 0xBABEF00D },
++ { "SH", 0x470, 24, 0x45C, 16, 0xDEADBEEF },
++ { "PA", 0x474, 0, 0x460, 16, 0x0000AAAA },
++ { "SE", 0x474, 8, 0x464, 16, 0x5E5E5E5E },
++ { "MC", 0x478, 0, 0x468, 16, 0x12345678 },
++ { "HI", 0x478, 8, 0x46C, 16, 0xAAAAAAAA }
++ };
++
++ static gctUINT32 _otherRegs[] =
++ {
++ 0x040, 0x044, 0x04C, 0x050, 0x054, 0x058, 0x05C, 0x060,
++ 0x43c, 0x440, 0x444, 0x414,
++ };
++
++ gceSTATUS status;
++ gckKERNEL kernel = gcvNULL;
++ gctUINT32 idle = 0, axi = 0;
++ gctUINT32 dmaAddress1 = 0, dmaAddress2 = 0;
++ gctUINT32 dmaState1 = 0, dmaState2 = 0;
++ gctUINT32 dmaLow = 0, dmaHigh = 0;
++ gctUINT32 cmdState = 0, cmdDmaState = 0, cmdFetState = 0;
++ gctUINT32 dmaReqState = 0, calState = 0, veReqState = 0;
++ gctUINT i;
++ gctUINT pipe = 0, pixelPipes = 0;
++ gctUINT32 control = 0, oldControl = 0;
++ gckOS os = Hardware->os;
++ gceCORE core = Hardware->core;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ kernel = Hardware->kernel;
++
++ gcmkPRINT_N(12, "GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n",
++ core,
++ Hardware->identity.chipModel,
++ Hardware->identity.chipRevision);
++
++ pixelPipes = Hardware->identity.pixelPipes
++ ? Hardware->identity.pixelPipes
++ : 1;
++
++ /* Reset register values. */
++ idle = axi =
++ dmaState1 = dmaState2 =
++ dmaAddress1 = dmaAddress2 =
++ dmaLow = dmaHigh = 0;
++
++ /* Verify whether DMA is running. */
++ gcmkONERROR(_VerifyDMA(
++ os, core, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2
++ ));
++
++ cmdState = dmaState2 & 0x1F;
++ cmdDmaState = (dmaState2 >> 8) & 0x03;
++ cmdFetState = (dmaState2 >> 10) & 0x03;
++ dmaReqState = (dmaState2 >> 12) & 0x03;
++ calState = (dmaState2 >> 14) & 0x03;
++ veReqState = (dmaState2 >> 16) & 0x03;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x004, &idle));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x00C, &axi));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x668, &dmaLow));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x66C, &dmaHigh));
++
++ gcmkPRINT_N(0, "**************************\n");
++ gcmkPRINT_N(0, "*** GPU STATE DUMP ***\n");
++ gcmkPRINT_N(0, "**************************\n");
++
++ gcmkPRINT_N(4, " axi = 0x%08X\n", axi);
++
++ gcmkPRINT_N(4, " idle = 0x%08X\n", idle);
++ if ((idle & 0x00000001) == 0) gcmkPRINT_N(0, " FE not idle\n");
++ if ((idle & 0x00000002) == 0) gcmkPRINT_N(0, " DE not idle\n");
++ if ((idle & 0x00000004) == 0) gcmkPRINT_N(0, " PE not idle\n");
++ if ((idle & 0x00000008) == 0) gcmkPRINT_N(0, " SH not idle\n");
++ if ((idle & 0x00000010) == 0) gcmkPRINT_N(0, " PA not idle\n");
++ if ((idle & 0x00000020) == 0) gcmkPRINT_N(0, " SE not idle\n");
++ if ((idle & 0x00000040) == 0) gcmkPRINT_N(0, " RA not idle\n");
++ if ((idle & 0x00000080) == 0) gcmkPRINT_N(0, " TX not idle\n");
++ if ((idle & 0x00000100) == 0) gcmkPRINT_N(0, " VG not idle\n");
++ if ((idle & 0x00000200) == 0) gcmkPRINT_N(0, " IM not idle\n");
++ if ((idle & 0x00000400) == 0) gcmkPRINT_N(0, " FP not idle\n");
++ if ((idle & 0x00000800) == 0) gcmkPRINT_N(0, " TS not idle\n");
++ if ((idle & 0x80000000) != 0) gcmkPRINT_N(0, " AXI low power mode\n");
++
++ if (
++ (dmaAddress1 == dmaAddress2)
++ && (dmaState1 == dmaState2)
++ )
++ {
++ gcmkPRINT_N(0, " DMA appears to be stuck at this address:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ }
++ else
++ {
++ if (dmaAddress1 == dmaAddress2)
++ {
++ gcmkPRINT_N(0, " DMA address is constant, but state is changing:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaState2);
++ }
++ else
++ {
++ gcmkPRINT_N(0, " DMA is running; known addresses are:\n");
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1);
++ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress2);
++ }
++ }
++
++ gcmkPRINT_N(4, " dmaLow = 0x%08X\n", dmaLow);
++ gcmkPRINT_N(4, " dmaHigh = 0x%08X\n", dmaHigh);
++ gcmkPRINT_N(4, " dmaState = 0x%08X\n", dmaState2);
++ gcmkPRINT_N(8, " command state = %d (%s)\n", cmdState, _cmdState [cmdState]);
++ gcmkPRINT_N(8, " command DMA state = %d (%s)\n", cmdDmaState, _cmdDmaState[cmdDmaState]);
++ gcmkPRINT_N(8, " command fetch state = %d (%s)\n", cmdFetState, _cmdFetState[cmdFetState]);
++ gcmkPRINT_N(8, " DMA request state = %d (%s)\n", dmaReqState, _reqDmaState[dmaReqState]);
++ gcmkPRINT_N(8, " cal state = %d (%s)\n", calState, _calState [calState]);
++ gcmkPRINT_N(8, " VE request state = %d (%s)\n", veReqState, _veReqState [veReqState]);
++
++ /* Record control. */
++ gckOS_ReadRegisterEx(os, core, 0x0, &oldControl);
++
++ for (pipe = 0; pipe < pixelPipes; pipe++)
++ {
++ gcmkPRINT_N(4, " Debug registers of pipe[%d]:\n", pipe);
++
++ /* Switch pipe. */
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x0, &control));
++ control &= ~(0xF << 20);
++ control |= (pipe << 20);
++ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, control));
++
++ for (i = 0; i < gcmCOUNTOF(_dbgRegs); i += 1)
++ {
++ gcmkONERROR(_DumpDebugRegisters(os, core, &_dbgRegs[i]));
++ }
++
++ gcmkPRINT_N(0, " Other Registers:\n");
++ for (i = 0; i < gcmCOUNTOF(_otherRegs); i += 1)
++ {
++ gctUINT32 read;
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, _otherRegs[i], &read));
++ gcmkPRINT_N(12, " [0x%04X] 0x%08X\n", _otherRegs[i], read);
++ }
++ }
++
++ if (kernel->hardware->identity.chipFeatures & (1 << 4))
++ {
++ gctUINT32 read0, read1, write;
++
++ read0 = read1 = write = 0;
++
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x43C, &read0));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x440, &read1));
++ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x444, &write));
++
++ gcmkPRINT_N(4, " read0 = 0x%08X\n", read0);
++ gcmkPRINT_N(4, " read1 = 0x%08X\n", read1);
++ gcmkPRINT_N(4, " write = 0x%08X\n", write);
++ }
++
++ /* Restore control. */
++ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, oldControl));
++
++ /* dump stack. */
++ gckOS_DumpCallStack(os);
++
++OnError:
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckHARDWARE_ReadPerformanceRegister(
++ IN gckHARDWARE Hardware,
++ IN gctUINT PerformanceAddress,
++ IN gctUINT IndexAddress,
++ IN gctUINT IndexShift,
++ IN gctUINT Index,
++ OUT gctUINT32_PTR Value
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x PerformanceAddress=0x%x IndexAddress=0x%x "
++ "IndexShift=%u Index=%u",
++ Hardware, PerformanceAddress, IndexAddress, IndexShift,
++ Index);
++
++ /* Write the index. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ IndexAddress,
++ Index << IndexShift));
++
++ /* Read the register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ PerformanceAddress,
++ Value));
++
++ /* Test for reset. */
++ if (Index == 15)
++ {
++ /* Index another register to get out of reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, IndexAddress, 0));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=0x%x", *Value);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ )
++{
++ gceSTATUS status;
++ gctUINT i, clock;
++ gcsHAL_FRAME_INFO info;
++#if gcdFRAME_DB_RESET
++ gctUINT reset;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Get profile tick. */
++ gcmkONERROR(gckOS_GetProfileTick(&info.ticks));
++
++ /* Read SH counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 4,
++ &info.shaderCycles));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 9,
++ &info.vsInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 12,
++ &info.vsTextureCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 7,
++ &info.psInstructionCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 14,
++ &info.psTextureCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0045C,
++ 0x00470,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read PA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 3,
++ &info.vertexCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 4,
++ &info.primitiveCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 7,
++ &info.rejectedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 8,
++ &info.culledPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 6,
++ &info.clippedPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 5,
++ &info.outPrimitives));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00460,
++ 0x00474,
++ 0,
++ 15,
++ &reset));
++#endif
++
++ /* Read RA counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 3,
++ &info.inPrimitives));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 11,
++ &info.culledQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 1,
++ &info.totalQuadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 2,
++ &info.quadCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 0,
++ &info.totalPixelCount));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00448,
++ 0x00474,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Read TX counters and reset them. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 0,
++ &info.bilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 1,
++ &info.trilinearRequests));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 8,
++ &info.txHitCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 9,
++ &info.txMissCount));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 6,
++ &info.txBytes8));
++#if gcdFRAME_DB_RESET
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x0044C,
++ 0x00474,
++ 24,
++ 15,
++ &reset));
++#endif
++
++ /* Read clock control register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ &clock));
++
++ /* Walk through all avaiable pixel pipes. */
++ for (i = 0; i < Hardware->identity.pixelPipes; ++i)
++ {
++ /* Select proper pipe. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20)))));
++
++ /* Read cycle registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ &info.cycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0007C,
++ &info.idleCycles[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00438,
++ &info.mcCycles[i]));
++
++ /* Read bandwidth registers. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0005C,
++ &info.readRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00040,
++ &info.readBytes8[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00050,
++ &info.writeRequests[i]));
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00044,
++ &info.writeBytes8[i]));
++
++ /* Read PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 0,
++ &info.colorKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 2,
++ &info.colorDrawn[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 1,
++ &info.depthKilled[i]));
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 3,
++ &info.depthDrawn[i]));
++ }
++
++ /* Zero out remaning reserved counters. */
++ for (; i < 8; ++i)
++ {
++ info.readBytes8[i] = 0;
++ info.writeBytes8[i] = 0;
++ info.cycles[i] = 0;
++ info.idleCycles[i] = 0;
++ info.mcCycles[i] = 0;
++ info.readRequests[i] = 0;
++ info.writeRequests[i] = 0;
++ info.colorKilled[i] = 0;
++ info.colorDrawn[i] = 0;
++ info.depthKilled[i] = 0;
++ info.depthDrawn[i] = 0;
++ }
++
++ /* Reset clock control register. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00000,
++ clock));
++
++ /* Reset cycle and bandwidth counters. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 1));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0003C,
++ 0));
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00078,
++ 0));
++
++#if gcdFRAME_DB_RESET
++ /* Reset PE counters. */
++ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister(
++ Hardware,
++ 0x00454,
++ 0x00470,
++ 16,
++ 15,
++ &reset));
++#endif
++
++ /* Copy to user. */
++ gcmkONERROR(gckOS_CopyToUserData(Hardware->os,
++ &info,
++ FrameInfo,
++ gcmSIZEOF(info)));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdDVFS
++#define READ_FROM_EATER1 0
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ )
++{
++ gctUINT32 debug1;
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Load != gcvNULL);
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00110,
++ Load));
++#if READ_FROM_EATER1
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00134,
++ Load));
++#endif
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00114,
++ &debug1));
++
++ /* Patch result of 0x110 with result of 0x114. */
++ if ((debug1 & 0xFF) == 1)
++ {
++ *Load &= ~0xFF;
++ *Load |= 1;
++ }
++
++ if (((debug1 & 0xFF00) >> 8) == 1)
++ {
++ *Load &= ~(0xFF << 8);
++ *Load |= 1 << 8;
++ }
++
++ if (((debug1 & 0xFF0000) >> 16) == 1)
++ {
++ *Load &= ~(0xFF << 16);
++ *Load |= 1 << 16;
++ }
++
++ if (((debug1 & 0xFF000000) >> 24) == 1)
++ {
++ *Load &= ~(0xFF << 24);
++ *Load |= 1 << 24;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 Frequency
++ )
++{
++ gceSTATUS status;
++ gctUINT32 period;
++ gctUINT32 eater;
++
++#if READ_FROM_EATER1
++ gctUINT32 period1;
++ gctUINT32 eater1;
++#endif
++
++ gcmkHEADER_ARG("Hardware=0x%X Frequency=%d", Hardware, Frequency);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ period = 0;
++
++ while((64 << period) < (gcdDVFS_ANAYLSE_WINDOW * Frequency * 1000) )
++ {
++ period++;
++ }
++
++#if READ_FROM_EATER1
++ /*
++ * Peroid = F * 1000 * 1000 / (60 * 16 * 1024);
++ */
++ period1 = Frequency * 6250 / 6114;
++#endif
++
++ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE);
++
++ if (Hardware->chipPowerState == gcvPOWER_ON)
++ {
++ /* Get current configure. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &eater));
++
++ /* Change peroid. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ ((((gctUINT32) (eater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (period) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8)))));
++
++#if READ_FROM_EATER1
++ /* Config eater1. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ &eater1));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x00130,
++ ((((gctUINT32) (eater1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16))) | (((gctUINT32) ((gctUINT32) (period1) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16)))));
++#endif
++ }
++ else
++ {
++ status = gcvSTATUS_INVALID_REQUEST;
++ }
++
++OnError:
++ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gctUINT32 data;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ &data));
++
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23)));
++ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22)));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "DVFS Configure=0x%X",
++ data);
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os,
++ Hardware->core,
++ 0x0010C,
++ data));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckHARDWARE_PrepareFunctions
++**
++** Generate command buffer snippets which will be used by gckHARDWARE, by which
++** gckHARDWARE can manipulate GPU by FE command without using gckCOMMAND to avoid
++** race condition and deadlock.
++**
++** Notice:
++** 1. Each snippet can only be executed when GPU is idle.
++** 2. Execution is triggered by AHB (0x658)
++** 3. Each snippet followed by END so software can sync with GPU by checking GPU
++** idle
++** 4. It is transparent to gckCOMMAND command buffer.
++**
++** Existing Snippets:
++** 1. MMU Configure
++** For new MMU, after GPU is reset, FE execute this command sequence to enble MMU.
++*/
++gceSTATUS
++gckHARDWARE_PrepareFunctions(
++ gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckOS os;
++ gctUINT32 offset = 0;
++ gctUINT32 mmuBytes;
++ gctUINT32 endBytes;
++ gctUINT8_PTR logical;
++
++ gcmkHEADER_ARG("%x", Hardware);
++
++ os = Hardware->os;
++
++ gcmkVERIFY_OK(gckOS_GetPageSize(os, &Hardware->functionBytes));
++
++ /* Allocate a command buffer. */
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ os,
++ gcvFALSE,
++ &Hardware->functionBytes,
++ &Hardware->functionPhysical,
++ &Hardware->functionLogical
++ ));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ os,
++ Hardware->functionLogical,
++ &Hardware->functionAddress
++ ));
++
++ if (Hardware->mmuVersion > 0)
++ {
++ /* MMU configure command sequence. */
++ logical = (gctUINT8_PTR)Hardware->functionLogical + offset;
++
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address
++ = Hardware->functionAddress + offset;
++
++ gcmkONERROR(gckHARDWARE_SetMMUStates(
++ Hardware,
++ Hardware->kernel->mmu->mtlbLogical,
++ gcvMMU_MODE_4K,
++ (gctUINT8_PTR)Hardware->kernel->mmu->mtlbLogical + gcdMMU_MTLB_SIZE,
++ logical,
++ &mmuBytes
++ ));
++
++ offset += mmuBytes;
++
++ logical = (gctUINT8_PTR)Hardware->functionLogical + offset;
++
++ gcmkONERROR(gckHARDWARE_End(
++ Hardware,
++ gcvNULL,
++ &endBytes
++ ));
++
++ gcmkONERROR(gckHARDWARE_End(
++ Hardware,
++ logical,
++ &endBytes
++ ));
++
++ offset += endBytes;
++
++ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes = mmuBytes + endBytes;
++ }
++
++ gcmkASSERT(offset < Hardware->functionBytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.h 2016-06-19 22:11:55.217145781 +0200
+@@ -0,0 +1,160 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_h_
++#define __gc_hal_kernel_hardware_h_
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_hardware_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++typedef enum {
++ gcvHARDWARE_FUNCTION_MMU,
++ gcvHARDWARE_FUNCTION_FLUSH,
++
++ gcvHARDWARE_FUNCTION_NUM,
++}
++gceHARDWARE_FUNCTION;
++
++
++typedef struct _gcsHARWARE_FUNCTION
++{
++ /* Entry of the function. */
++ gctUINT32 address;
++
++ /* Bytes of the function. */
++ gctUINT32 bytes;
++}
++gcsHARDWARE_FUNCTION;
++
++/* gckHARDWARE object. */
++struct _gckHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gctKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Pointer to gctOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Chip characteristics. */
++ gcsHAL_QUERY_CHIP_IDENTITY identity;
++ gctBOOL allowFastClear;
++ gctBOOL allowCompression;
++ gctUINT32 powerBaseAddress;
++ gctBOOL extraEventStates;
++
++ /* Big endian */
++ gctBOOL bigEndian;
++
++ /* Chip status */
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gctUINT32 lastWaitLink;
++ gctUINT32 lastEnd;
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER globalSemaphore;
++
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++
++ gctUINT32 mmuVersion;
++
++ /* Whether use new MMU. It is meaningless
++ ** for old MMU since old MMU is always enabled.
++ */
++ gctBOOL enableMMU;
++
++ /* Type */
++ gceHARDWARE_TYPE type;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gctUINT32 powerOnFscaleVal;
++#endif
++ gctPOINTER pageTableDirty;
++
++#if gcdLINK_QUEUE_SIZE
++ struct _gckLINKQUEUE linkQueue;
++#endif
++
++ gctBOOL powerManagement;
++ gctBOOL powerManagementLock;
++ gctBOOL gpuProfiler;
++
++ gctBOOL endAfterFlushMmuCache;
++
++ gctUINT32 minFscaleValue;
++
++ gctPOINTER pendingEvent;
++
++ /* Function used by gckHARDWARE. */
++ gctPHYS_ADDR functionPhysical;
++ gctPOINTER functionLogical;
++ gctUINT32 functionAddress;
++ gctSIZE_T functionBytes;
++
++ gcsHARDWARE_FUNCTION functions[gcvHARDWARE_FUNCTION_NUM];
++};
++
++gceSTATUS
++gckHARDWARE_GetBaseAddress(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++gceSTATUS
++gckHARDWARE_NeedBaseAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 State,
++ OUT gctBOOL_PTR NeedBase
++ );
++
++gceSTATUS
++gckHARDWARE_GetFrameInfo(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_FRAME_INFO * FrameInfo
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_recorder.c 2016-06-19 22:11:55.217145781 +0200
+@@ -0,0 +1,679 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_context.h"
++
++/*
++ * -----------------------
++ * HARDWARE STATE RECORDER
++ * -----------------------
++ *
++ * State mirror buffer is used to 'mirror' hardware states since hardware
++ * states can't be dumpped. It is a context buffer which stores 'global'
++ * context.
++ *
++ * For each commit, state recorder
++ * 1) Records context buffer (if there is) and command buffers in this commit.
++ * 2) Parse those buffers to estimate the state changed.
++ * 3) Stores result to a mirror buffer.
++ *
++ * == Commit 0 ====================================================================
++ *
++ * Context Buffer 0
++ *
++ * Command Buffer 0
++ *
++ * Mirror Buffer 0 <- Context Buffer 0 + Command Buffer 0
++ *
++ * == Commit 1 ====================================================================
++ *
++ * Command Buffer 1
++ *
++ * Mirror Buffer 1 <- Command buffer 1 + Mirror Buffer 0
++ *
++ * == Commit 2 ====================================================================
++ *
++ * Context Buffer 2 (optional)
++ *
++ * Command Buffer 2
++ *
++ * Mirror Buffer 2 <- Command buffer 2 + Context Buffer 2 + Mirror Buffer 1
++ *
++ * == Commit N ====================================================================
++ *
++ * For Commit N, these buffers are needed to reproduce hardware's behavior in
++ * this commit.
++ *
++ * Mirror Buffer [N - 1] : State Mirror accumlated by past commits,
++ * which is used to restore hardware state.
++ * Context Buffer [N] :
++ * Command Buffer [N] : Command buffer executed by hardware in this commit.
++ *
++ * If sequence of states programming matters, hardware's behavior can't be reproduced,
++ * but the state values stored in mirror buffer are assuring.
++ */
++
++/* Queue size. */
++#define gcdNUM_RECORDS 6
++
++typedef struct _gcsPARSER_HANDLER * gckPARSER_HANDLER;
++
++typedef void
++(*HandlerFunction)(
++ IN gckPARSER_HANDLER Handler,
++ IN gctUINT32 Addr,
++ IN gctUINT32 Data
++ );
++
++typedef struct _gcsPARSER_HANDLER
++{
++ gctUINT32 type;
++ gctUINT32 cmd;
++ gctPOINTER private;
++ HandlerFunction function;
++}
++gcsPARSER_HANDLER;
++
++typedef struct _gcsPARSER * gckPARSER;
++typedef struct _gcsPARSER
++{
++ gctUINT8_PTR currentCmdBufferAddr;
++
++ /* Current command. */
++ gctUINT32 lo;
++ gctUINT32 hi;
++
++ gctUINT8 cmdOpcode;
++ gctUINT16 cmdAddr;
++ gctUINT32 cmdSize;
++ gctUINT32 cmdRectCount;
++ gctUINT8 skip;
++ gctUINT32 skipCount;
++
++ gctBOOL allow;
++
++ /* Callback used by parser to handle a command. */
++ gckPARSER_HANDLER commandHandler;
++}
++gcsPARSER;
++
++typedef struct _gcsMIRROR
++{
++ gctUINT32_PTR logical[gcdNUM_RECORDS];
++ gctUINT32 bytes;
++ gcsSTATE_MAP_PTR map;
++ gctUINT32 stateCount;
++}
++gcsMIRROR;
++
++typedef struct _gcsDELTA
++{
++ gctUINT64 commitStamp;
++ gctUINT32_PTR command;
++ gctUINT32 commandBytes;
++ gctUINT32_PTR context;
++ gctUINT32 contextBytes;
++}
++gcsDELTA;
++
++typedef struct _gcsRECORDER
++{
++ gckOS os;
++ gcsMIRROR mirror;
++ gcsDELTA deltas[gcdNUM_RECORDS];
++
++ /* Index of current record. */
++ gctUINT index;
++
++ /* Number of records. */
++ gctUINT num;
++
++ /* Plugin used by gckPARSER. */
++ gcsPARSER_HANDLER recorderHandler;
++ gckPARSER parser;
++}
++gcsRECORDER;
++
++
++/******************************************************************************\
++***************************** Command Buffer Parser ****************************
++\******************************************************************************/
++
++/*
++** Command buffer parser checks command buffer in FE's view to make sure there
++** is no format error.
++**
++** Parser provide a callback mechnisam, so plug-in can be added to implement
++** other functions.
++*/
++
++static void
++_HandleLoadState(
++ IN OUT gckPARSER Parser
++ )
++{
++ gctUINT i;
++ gctUINT32_PTR data = (gctUINT32_PTR)Parser->currentCmdBufferAddr;
++ gctUINT32 cmdAddr = Parser->cmdAddr;
++
++ if (Parser->commandHandler == gcvNULL
++ || Parser->commandHandler->cmd != 0x01
++ )
++ {
++ /* No handler for this command. */
++ return;
++ }
++
++ for (i = 0; i < Parser->cmdSize; i++)
++ {
++ Parser->commandHandler->function(Parser->commandHandler, cmdAddr, *data);
++
++ /* Advance to next state. */
++ cmdAddr++;
++ data++;
++ }
++}
++
++static void
++_GetCommand(
++ IN OUT gckPARSER Parser
++ )
++{
++ gctUINT32 * buffer = (gctUINT32 *)Parser->currentCmdBufferAddr;
++
++ gctUINT16 cmdRectCount;
++ gctUINT16 cmdDataCount;
++
++ Parser->hi = buffer[0];
++ Parser->lo = buffer[1];
++
++ Parser->cmdOpcode = (((((gctUINT32) (Parser->hi)) >> (0 ? 31:27)) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) );
++ Parser->cmdRectCount = 1;
++
++ switch (Parser->cmdOpcode)
++ {
++ case 0x01:
++ /* Extract count. */
++ Parser->cmdSize = (((((gctUINT32) (Parser->hi)) >> (0 ? 25:16)) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1)))))) );
++ if (Parser->cmdSize == 0)
++ {
++ /* 0 means 1024. */
++ Parser->cmdSize = 1024;
++ }
++ Parser->skip = (Parser->cmdSize & 0x1) ? 0 : 1;
++
++ /* Extract address. */
++ Parser->cmdAddr = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) );
++
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 4;
++ Parser->skipCount = Parser->cmdSize + Parser->skip;
++ break;
++
++ case 0x05:
++ Parser->cmdSize = 4;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x06:
++ Parser->cmdSize = 5;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x0C:
++ Parser->cmdSize = 3;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x09:
++ Parser->cmdSize = 2;
++ Parser->cmdAddr = 0x0F16;
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2);
++ break;
++
++ case 0x04:
++ Parser->cmdSize = 1;
++ Parser->cmdAddr = 0x0F06;
++
++ cmdRectCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) );
++ cmdDataCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 26:16)) & ((gctUINT32) ((((1 ? 26:16) - (0 ? 26:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:16) - (0 ? 26:16) + 1)))))) );
++
++ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2)
++ + cmdRectCount * 2
++ + gcmALIGN(cmdDataCount, 2);
++
++ Parser->cmdRectCount = cmdRectCount;
++ break;
++
++ case 0x03:
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8;
++ Parser->skipCount = 0;
++ break;
++
++ case 0x02:
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8;
++ Parser->skipCount = 0;
++ break;
++
++ default:
++ /* Unknown command is a risk. */
++ Parser->allow = gcvFALSE;
++ break;
++ }
++}
++
++static void
++_ParseCommand(
++ IN OUT gckPARSER Parser
++ )
++{
++ switch(Parser->cmdOpcode)
++ {
++ case 0x01:
++ _HandleLoadState(Parser);
++ break;
++ case 0x05:
++ case 0x06:
++ case 0x0C:
++ break;
++ case 0x04:
++ break;
++ default:
++ break;
++ }
++
++ /* Advance to next command. */
++ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr
++ + (Parser->skipCount << 2);
++}
++
++gceSTATUS
++gckPARSER_Parse(
++ IN gckPARSER Parser,
++ IN gctUINT8_PTR Buffer,
++ IN gctUINT32 Bytes
++ )
++{
++ gckPARSER parser = Parser;
++ gctUINT8_PTR end = (gctUINT8_PTR)Buffer + Bytes;
++
++ /* Initialize parser. */
++ parser->currentCmdBufferAddr = (gctUINT8_PTR)Buffer;
++ parser->skip = 0;
++ parser->allow = gcvTRUE;
++
++ /* Go through command buffer until reaching the end
++ ** or meeting an error. */
++ do
++ {
++ _GetCommand(parser);
++
++ _ParseCommand(parser);
++ }
++ while ((parser->currentCmdBufferAddr < end) && (parser->allow == gcvTRUE));
++
++ if (parser->allow == gcvFALSE)
++ {
++ /* Error detected. */
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckPARSER_RegisterCommandHandler
++**
++** Register a command handler which will be called when parser get a command.
++**
++*/
++gceSTATUS
++gckPARSER_RegisterCommandHandler(
++ IN gckPARSER Parser,
++ IN gckPARSER_HANDLER Handler
++ )
++{
++ Parser->commandHandler = Handler;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckPARSER_Construct(
++ IN gckOS Os,
++ IN gckPARSER_HANDLER Handler,
++ OUT gckPARSER * Parser
++ )
++{
++ gceSTATUS status;
++ gckPARSER pointer;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsPARSER), (gctPOINTER *)&pointer));
++
++ /* Put it here temp, should have a more general plug-in mechnisam. */
++ pointer->commandHandler = Handler;
++
++ *Parser = pointer;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++void
++gckPARSER_Destroy(
++ IN gckOS Os,
++ IN gckPARSER Parser
++ )
++{
++ gcmkOS_SAFE_FREE(Os, Parser);
++}
++
++/******************************************************************************\
++**************************** Hardware States Recorder **************************
++\******************************************************************************/
++
++static void
++_RecodeState(
++ IN gckPARSER_HANDLER Handler,
++ IN gctUINT32 Addr,
++ IN gctUINT32 Data
++ )
++{
++ gcmkVERIFY_OK(gckRECORDER_UpdateMirror(Handler->private, Addr, Data));
++}
++
++static gctUINT
++_Previous(
++ IN gctUINT Index
++ )
++{
++ if (Index == 0)
++ {
++ return gcdNUM_RECORDS - 1;
++ }
++
++ return Index - 1;
++}
++
++static gctUINT
++_Next(
++ IN gctUINT Index
++ )
++{
++ return (Index + 1) % gcdNUM_RECORDS;
++}
++
++gceSTATUS
++gckRECORDER_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ OUT gckRECORDER * Recorder
++ )
++{
++ gceSTATUS status;
++ gckCONTEXT context = gcvNULL;
++ gckRECORDER recorder = gcvNULL;
++ gctUINT32 mapSize;
++ gctUINT i;
++ gctBOOL virtualCommandBuffer = Hardware->kernel->virtualCommandBuffer;
++
++ /* TODO: We only need context buffer and state map, it should be able to get without construct a
++ ** new context.
++ ** Now it is leaked, since we can't free it when command buffer is gone.
++ */
++
++ /* MMU is not ready now. */
++ Hardware->kernel->virtualCommandBuffer = gcvFALSE;
++
++ gcmkONERROR(gckCONTEXT_Construct(Os, Hardware, 0, &context));
++
++ /* Restore. */
++ Hardware->kernel->virtualCommandBuffer = virtualCommandBuffer;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsRECORDER), (gctPOINTER *)&recorder));
++
++ gckOS_ZeroMemory(recorder, gcmSIZEOF(gcsRECORDER));
++
++ /* Copy state map. */
++ recorder->mirror.stateCount = context->stateCount;
++
++ mapSize = context->stateCount * gcmSIZEOF(gcsSTATE_MAP);
++
++ gcmkONERROR(gckOS_Allocate(Os, mapSize, (gctPOINTER *)&recorder->mirror.map));
++
++ gckOS_MemCopy(recorder->mirror.map, context->map, mapSize);
++
++ /* Copy context buffer. */
++ recorder->mirror.bytes = context->totalSize;
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->mirror.logical[i]));
++ gckOS_MemCopy(recorder->mirror.logical[i], context->buffer->logical, context->totalSize);
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ /* TODO : Optimize size. */
++ gcmkONERROR(gckOS_Allocate(Os, gcdCMD_BUFFER_SIZE, (gctPOINTER *)&recorder->deltas[i].command));
++ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->deltas[i].context));
++ }
++
++ recorder->index = 0;
++ recorder->num = 0;
++
++ /* Initialize Parser plugin. */
++ recorder->recorderHandler.cmd = 0x01;
++ recorder->recorderHandler.private = recorder;
++ recorder->recorderHandler.function = _RecodeState;
++
++ gcmkONERROR(gckPARSER_Construct(Os, &recorder->recorderHandler, &recorder->parser));
++
++ recorder->os = Os;
++
++ *Recorder = recorder;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (recorder)
++ {
++ gckRECORDER_Destory(Os, recorder);
++ }
++
++ return status;
++}
++
++gceSTATUS
++gckRECORDER_Destory(
++ IN gckOS Os,
++ IN gckRECORDER Recorder
++ )
++{
++ gctUINT i;
++
++ if (Recorder->mirror.map)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->mirror.map);
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ if (Recorder->mirror.logical[i])
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->mirror.logical[i]);
++ }
++ }
++
++ for (i = 0; i < gcdNUM_RECORDS; i++)
++ {
++ if (Recorder->deltas[i].command)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].command);
++ }
++
++ if (Recorder->deltas[i].context)
++ {
++ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].context);
++ }
++ }
++
++ if (Recorder->parser)
++ {
++ gckPARSER_Destroy(Os, Recorder->parser);
++ }
++
++ gcmkOS_SAFE_FREE(Os, Recorder);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckRECORDER_UpdateMirror(
++ IN gckRECORDER Recorder,
++ IN gctUINT32 State,
++ IN gctUINT32 Data
++ )
++{
++ gctUINT32 index;
++ gcsSTATE_MAP_PTR map = Recorder->mirror.map;
++ gctUINT32_PTR buffer = Recorder->mirror.logical[Recorder->index];
++
++ if (State >= Recorder->mirror.stateCount)
++ {
++ /* Ignore them just like HW does. */
++ return gcvSTATUS_OK;
++ }
++
++ index = map[State].index;
++
++ if (index)
++ {
++ buffer[index] = Data;
++ }
++
++ return gcvSTATUS_OK;
++}
++
++void
++gckRECORDER_AdvanceIndex(
++ IN gckRECORDER Recorder,
++ IN gctUINT64 CommitStamp
++ )
++{
++ /* Get next record. */
++ gctUINT next = (Recorder->index + 1) % gcdNUM_RECORDS;
++
++ /* Record stamp of this commit. */
++ Recorder->deltas[Recorder->index].commitStamp = CommitStamp;
++
++ /* Mirror of next record is mirror of this record and delta in next record. */
++ gckOS_MemCopy(Recorder->mirror.logical[next],
++ Recorder->mirror.logical[Recorder->index], Recorder->mirror.bytes);
++
++ /* Advance to next record. */
++ Recorder->index = next;
++
++ Recorder->num = gcmMIN(Recorder->num + 1, gcdNUM_RECORDS - 1);
++
++
++ /* Reset delta. */
++ Recorder->deltas[Recorder->index].commandBytes = 0;
++ Recorder->deltas[Recorder->index].contextBytes = 0;
++}
++
++void
++gckRECORDER_Record(
++ IN gckRECORDER Recorder,
++ IN gctUINT8_PTR CommandBuffer,
++ IN gctUINT32 CommandBytes,
++ IN gctUINT8_PTR ContextBuffer,
++ IN gctUINT32 ContextBytes
++ )
++{
++ gcsDELTA * delta = &Recorder->deltas[Recorder->index];
++
++ if (CommandBytes != 0xFFFFFFFF)
++ {
++ gckPARSER_Parse(Recorder->parser, CommandBuffer, CommandBytes);
++ gckOS_MemCopy(delta->command, CommandBuffer, CommandBytes);
++ delta->commandBytes = CommandBytes;
++ }
++
++ if (ContextBytes != 0xFFFFFFFF)
++ {
++ gckPARSER_Parse(Recorder->parser, ContextBuffer, ContextBytes);
++ gckOS_MemCopy(delta->context, ContextBuffer, ContextBytes);
++ delta->contextBytes = ContextBytes;
++ }
++}
++
++void
++gckRECORDER_Dump(
++ IN gckRECORDER Recorder
++ )
++{
++ gctUINT last = Recorder->index;
++ gctUINT previous;
++ gctUINT i;
++ gcsMIRROR *mirror = &Recorder->mirror;
++ gcsDELTA *delta;
++ gckOS os = Recorder->os;
++
++ for (i = 0; i < Recorder->num; i++)
++ {
++ last = _Previous(last);
++ }
++
++ for (i = 0; i < Recorder->num; i++)
++ {
++ delta = &Recorder->deltas[last];
++
++ /* Dump record */
++ gcmkPRINT("#[commit %llu]", delta->commitStamp);
++
++ if (delta->commitStamp)
++ {
++ previous = _Previous(last);
++
++ gcmkPRINT("#[mirror]");
++ gckOS_DumpBuffer(os, mirror->logical[previous], mirror->bytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++ }
++
++ if (delta->contextBytes)
++ {
++ gckOS_DumpBuffer(os, delta->context, delta->contextBytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++ }
++
++ gckOS_DumpBuffer(os, delta->command, delta->commandBytes, gceDUMP_BUFFER_USER, gcvTRUE);
++ gcmkPRINT("@[kernel.execute]");
++
++ last = _Next(last);
++ }
++}
++
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.c 2016-06-19 22:11:55.217145781 +0200
+@@ -0,0 +1,932 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_InitializeInfo
++**
++** Initialize architecture dependent command buffer information.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ /* Reset interrupts. */
++ Command->info.feBufferInt = -1;
++ Command->info.tsOverflowInt = -1;
++
++ /* Set command buffer attributes. */
++ Command->info.addressAlignment = 64;
++ Command->info.commandAlignment = 8;
++
++ /* Determine command alignment address mask. */
++ Command->info.addressMask = ((((gctUINT32) (Command->info.addressAlignment - 1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0 ) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Query the number of bytes needed by the STATE command. */
++ gcmkERR_BREAK(gckVGCOMMAND_StateCommand(
++ Command, 0x0, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.stateCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RESTART command. */
++ gcmkERR_BREAK(gckVGCOMMAND_RestartCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.restartCommandSize
++ ));
++
++ /* Query the number of bytes needed by the FETCH command. */
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.fetchCommandSize
++ ));
++
++ /* Query the number of bytes needed by the CALL command. */
++ gcmkERR_BREAK(gckVGCOMMAND_CallCommand(
++ Command, gcvNULL, (gctUINT32)~0, 0,
++ &Command->info.callCommandSize
++ ));
++
++ /* Query the number of bytes needed by the RETURN command. */
++ gcmkERR_BREAK(gckVGCOMMAND_ReturnCommand(
++ Command, gcvNULL,
++ &Command->info.returnCommandSize
++ ));
++
++ /* Query the number of bytes needed by the EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, gcvNULL, gcvBLOCK_PIXEL, -1,
++ &Command->info.eventCommandSize
++ ));
++
++ /* Query the number of bytes needed by the END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command, gcvNULL, -1,
++ &Command->info.endCommandSize
++ ));
++
++ /* Determine the tail reserve size. */
++ Command->info.staticTailSize = gcmMAX(
++ Command->info.fetchCommandSize,
++ gcmMAX(
++ Command->info.returnCommandSize,
++ Command->info.endCommandSize
++ )
++ );
++
++ /* Determine the maximum tail size. */
++ Command->info.dynamicTailSize
++ = Command->info.staticTailSize
++ + Command->info.eventCommandSize * gcvBLOCK_COUNT;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_StateCommand
++**
++** Append a STATE command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctUINT32 Pipe
++** Harwdare destination pipe.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** STATE command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 Address
++** Starting register address of the state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT32 Count
++** Number of states in state buffer.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the STATE command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the STATE command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Pipe=0x%x Logical=0x%x Address=0x%x Count=0x%x Bytes = 0x%x",
++ Command, Pipe, Logical, Address, Count, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) ((gctUINT32) (Pipe) & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LOAD_STATE. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the STATE command. */
++ *Bytes = 4 * (Count + 1);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_RestartCommand
++**
++** Form a RESTART command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RESTART command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this RESTART
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this RESTART command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RESTART command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RESTART command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++ gctUINT32 beginEndMark;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Determine Begin/End flag. */
++ beginEndMark = (FetchCount > 0)
++ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)))
++ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24)));
++
++ /* Append RESTART. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x9 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)))
++ | beginEndMark;
++
++ buffer[1]
++ = FetchAddress;
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RESTART command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_FetchCommand
++**
++** Form a FETCH command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** FETCH command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this FETCH
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this FETCH command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the FETCH command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the FETCH command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append FETCH. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x5 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the FETCH command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append LINK. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the LINK command. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_CallCommand
++**
++** Append a CALL command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** CALL command at or gcvNULL to query the size of the command.
++**
++** gctUINT32 FetchAddress
++** The address of another command buffer to be executed by this CALL
++** command. If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gctUINT FetchCount
++** The number of 64-bit data quantities in another command buffer to
++** be executed by this CALL command. If 'Logical' is gcvNULL, this
++** argument is ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the CALL command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the CALL command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x",
++ Command, Logical, FetchAddress, FetchCount, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append CALL. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x6 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0)));
++
++ buffer[1]
++ = gcmkFIXADDRESS(FetchAddress);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the CALL command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_ReturnCommand
++**
++** Append a RETURN command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to an gckVGCOMMAND object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** RETURN command at or gcvNULL to query the size of the command.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the RETURN command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the RETURN command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Bytes = 0x%x",
++ Command, Logical, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append RETURN. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x7 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the RETURN command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EventCommand
++**
++** Form an EVENT command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** EVENT command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument is ignored.
++**
++** gceBLOCK Block
++** Block that will generate the interrupt.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the EVENT command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Block=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, Block, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ typedef struct _gcsEVENTSTATES
++ {
++ /* Chips before VG21 use these values. */
++ gctUINT eventFromFE;
++ gctUINT eventFromPE;
++
++ /* VG21 chips and later use SOURCE field. */
++ gctUINT eventSource;
++ }
++ gcsEVENTSTATES;
++
++ static gcsEVENTSTATES states[] =
++ {
++ /* gcvBLOCK_COMMAND */
++ {
++ (gctUINT)~0,
++ (gctUINT)~0,
++ (gctUINT)~0
++ },
++
++ /* gcvBLOCK_TESSELLATOR */
++ {
++ 0x0,
++ 0x1,
++ 0x10
++ },
++
++ /* gcvBLOCK_TESSELLATOR2 */
++ {
++ 0x0,
++ 0x1,
++ 0x12
++ },
++
++ /* gcvBLOCK_TESSELLATOR3 */
++ {
++ 0x0,
++ 0x1,
++ 0x14
++ },
++
++ /* gcvBLOCK_RASTER */
++ {
++ 0x0,
++ 0x1,
++ 0x07,
++ },
++
++ /* gcvBLOCK_VG */
++ {
++ 0x0,
++ 0x1,
++ 0x0F
++ },
++
++ /* gcvBLOCK_VG2 */
++ {
++ 0x0,
++ 0x1,
++ 0x11
++ },
++
++ /* gcvBLOCK_VG3 */
++ {
++ 0x0,
++ 0x1,
++ 0x13
++ },
++
++ /* gcvBLOCK_PIXEL */
++ {
++ 0x0,
++ 0x1,
++ 0x07
++ },
++ };
++
++ /* Verify block ID. */
++ gcmkVERIFY_ARGUMENT(gcmIS_VALID_INDEX(Block, states));
++
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12)));
++
++ /* Determine chip version. */
++ if (Command->vg21)
++ {
++ /* Get the event source for the block. */
++ gctUINT eventSource = states[Block].eventSource;
++
++ /* Supported? */
++ if (eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) ((gctUINT32) (eventSource) & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));
++ }
++ else
++ {
++ /* Get the event source for the block. */
++ gctUINT eventFromFE = states[Block].eventFromFE;
++ gctUINT eventFromPE = states[Block].eventFromPE;
++
++ /* Supported? */
++ if (eventFromFE == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (eventFromFE) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (eventFromPE) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Make sure the events are directly supported for the block. */
++ if (states[Block].eventSource == ~0)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))));
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ /* Determine event source. */
++ if (Block == gcvBLOCK_COMMAND)
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5)));
++ }
++ else
++ {
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++ }
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 8;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGCOMMAND_EndCommand
++**
++** Form an END command at the specified location in the command buffer.
++**
++** INPUT:
++**
++** gckVGCOMMAND Command
++** Pointer to the Command object.
++**
++** gctPOINTER Logical
++** Pointer to the current location inside the command buffer to append
++** END command at or gcvNULL to query the size of the command.
++**
++** gctINT32 InterruptId
++** The ID of the interrupt to generate.
++** If 'Logical' is gcvNULL, this argument will be ignored.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes available for the END command.
++** If 'Logical' is gcvNULL, the value from this argument is ignored.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that will receive the number of bytes required
++** for the END command. If 'Bytes' is gcvNULL, nothing is returned.
++*/
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Logical=0x%x InterruptId=0x%x Bytes = 0x%x",
++ Command, Logical, InterruptId, Bytes);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->fe20)
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR buffer;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ buffer = (gctUINT32_PTR) Logical;
++
++ /* Append END. */
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the END command. */
++ *Bytes = 8;
++ }
++ }
++ else
++ {
++ if (Logical != gcvNULL)
++ {
++ gctUINT32_PTR memory;
++
++ /* Verify the event ID. */
++ gcmkVERIFY_ARGUMENT(InterruptId >= 0);
++
++ /* Cast the buffer pointer. */
++ memory = (gctUINT32_PTR) Logical;
++
++ /* Append EVENT. */
++ memory[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ memory[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6)));
++
++ /* Append END. */
++ memory[2]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)));
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return number of bytes required by the EVENT and END commands. */
++ *Bytes = 16;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_command_vg.h 2016-06-19 22:11:55.217145781 +0200
+@@ -0,0 +1,319 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_command_vg_h_
++#define __gc_hal_kernel_hardware_command_vg_h_
++
++/******************************************************************************\
++******************* Task and Interrupt Management Structures. ******************
++\******************************************************************************/
++
++/* Task storage header. */
++typedef struct _gcsTASK_STORAGE * gcsTASK_STORAGE_PTR;
++typedef struct _gcsTASK_STORAGE
++{
++ /* Next allocated storage buffer. */
++ gcsTASK_STORAGE_PTR next;
++}
++gcsTASK_STORAGE;
++
++/* Task container header. */
++typedef struct _gcsTASK_CONTAINER * gcsTASK_CONTAINER_PTR;
++typedef struct _gcsTASK_CONTAINER
++{
++ /* The number of tasks left to be processed in the container. */
++ gctINT referenceCount;
++
++ /* Size of the buffer. */
++ gctUINT size;
++
++ /* Link to the previous and the next allocated containers. */
++ gcsTASK_CONTAINER_PTR allocPrev;
++ gcsTASK_CONTAINER_PTR allocNext;
++
++ /* Link to the previous and the next containers in the free list. */
++ gcsTASK_CONTAINER_PTR freePrev;
++ gcsTASK_CONTAINER_PTR freeNext;
++}
++gcsTASK_CONTAINER;
++
++/* Kernel space task master table entry. */
++typedef struct _gcsBLOCK_TASK_ENTRY * gcsBLOCK_TASK_ENTRY_PTR;
++typedef struct _gcsBLOCK_TASK_ENTRY
++{
++ /* Pointer to the current task container for the block. */
++ gcsTASK_CONTAINER_PTR container;
++
++ /* Pointer to the current task data within the container. */
++ gcsTASK_HEADER_PTR task;
++
++ /* Pointer to the last link task within the container. */
++ gcsTASK_LINK_PTR link;
++
++ /* Number of interrupts allocated for this block. */
++ gctUINT interruptCount;
++
++ /* The index of the current interrupt. */
++ gctUINT interruptIndex;
++
++ /* Interrupt semaphore. */
++ gctSEMAPHORE interruptSemaphore;
++
++ /* Interrupt value array. */
++ gctINT32 interruptArray[32];
++}
++gcsBLOCK_TASK_ENTRY;
++
++
++/******************************************************************************\
++********************* Command Queue Management Structures. *********************
++\******************************************************************************/
++
++/* Command queue kernel element pointer. */
++typedef struct _gcsKERNEL_CMDQUEUE * gcsKERNEL_CMDQUEUE_PTR;
++
++/* Command queue object handler function type. */
++typedef gceSTATUS (* gctOBJECT_HANDLER) (
++ gckVGKERNEL Kernel,
++ gcsKERNEL_CMDQUEUE_PTR Entry
++ );
++
++/* Command queue kernel element. */
++typedef struct _gcsKERNEL_CMDQUEUE
++{
++ /* The number of buffers in the queue. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Pointer to the object handler function. */
++ gctOBJECT_HANDLER handler;
++}
++gcsKERNEL_CMDQUEUE;
++
++/* Command queue header. */
++typedef struct _gcsKERNEL_QUEUE_HEADER * gcsKERNEL_QUEUE_HEADER_PTR;
++typedef struct _gcsKERNEL_QUEUE_HEADER
++{
++ /* The size of the buffer in bytes. */
++ gctUINT size;
++
++ /* The number of pending entries to be processed. */
++ volatile gctUINT pending;
++
++ /* The current command queue entry. */
++ gcsKERNEL_CMDQUEUE_PTR currentEntry;
++
++ /* Next buffer. */
++ gcsKERNEL_QUEUE_HEADER_PTR next;
++}
++gcsKERNEL_QUEUE_HEADER;
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++/* gckVGCOMMAND object. */
++struct _gckVGCOMMAND
++{
++ /***************************************************************************
++ ** Object data and pointers.
++ */
++
++ gcsOBJECT object;
++ gckVGKERNEL kernel;
++ gckOS os;
++ gckVGHARDWARE hardware;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++
++ /***************************************************************************
++ ** Enable command queue dumping.
++ */
++
++ gctBOOL enableDumping;
++
++
++ /***************************************************************************
++ ** Bus Error interrupt.
++ */
++
++ gctINT32 busErrorInt;
++
++
++ /***************************************************************************
++ ** Command buffer information.
++ */
++
++ gcsCOMMAND_BUFFER_INFO info;
++
++
++ /***************************************************************************
++ ** Synchronization objects.
++ */
++
++ gctPOINTER queueMutex;
++ gctPOINTER taskMutex;
++ gctPOINTER commitMutex;
++
++
++ /***************************************************************************
++ ** Task management.
++ */
++
++ /* The head of the storage buffer linked list. */
++ gcsTASK_STORAGE_PTR taskStorage;
++
++ /* Allocation size. */
++ gctUINT taskStorageGranularity;
++ gctUINT taskStorageUsable;
++
++ /* The free container list. */
++ gcsTASK_CONTAINER_PTR taskFreeHead;
++ gcsTASK_CONTAINER_PTR taskFreeTail;
++
++ /* Task table */
++ gcsBLOCK_TASK_ENTRY taskTable[gcvBLOCK_COUNT];
++
++
++ /***************************************************************************
++ ** Command queue.
++ */
++
++ /* Pointer to the allocated queue memory. */
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++
++ /* Pointer to the current available queue from which new queue entries
++ will be allocated. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* If different from queueHead, points to the command queue which is
++ currently being executed by the hardware. */
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++
++ /* Points to the queue to merge the tail with when the tail is processed. */
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++
++ /* Queue overflow counter. */
++ gctUINT queueOverflow;
++
++
++ /***************************************************************************
++ ** Context.
++ */
++
++ /* Context counter used for unique ID. */
++ gctUINT64 contextCounter;
++
++ /* Current context ID. */
++ gctUINT64 currentContext;
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++ gctINT32 powerStallInt;
++ gcsCMDBUFFER_PTR powerStallBuffer;
++ gctSIGNAL powerStallSignal;
++
++};
++
++/******************************************************************************\
++************************ gckVGCOMMAND Object Internal API. ***********************
++\******************************************************************************/
++
++/* Initialize architecture dependent command buffer information. */
++gceSTATUS
++gckVGCOMMAND_InitializeInfo(
++ IN gckVGCOMMAND Command
++ );
++
++/* Form a STATE command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_StateCommand(
++ IN gckVGCOMMAND Command,
++ IN gctUINT32 Pipe,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a RESTART command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_RestartCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a FETCH command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_FetchCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a CALL command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_CallCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT FetchCount,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form a RETURN command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_ReturnCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form an EVENT command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EventCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gceBLOCK Block,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Form an END command at the specified location in the command buffer. */
++gceSTATUS
++gckVGCOMMAND_EndCommand(
++ IN gckVGCOMMAND Command,
++ IN gctPOINTER Logical,
++ IN gctINT32 InterruptId,
++ IN OUT gctUINT32 * Bytes
++ );
++
++#endif /* __gc_hal_kernel_hardware_command_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.c 2016-06-19 22:11:55.217145781 +0200
+@@ -0,0 +1,2119 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_HARDWARE
++
++typedef enum
++{
++ gcvPOWER_FLAG_INITIALIZE = 1 << 0,
++ gcvPOWER_FLAG_STALL = 1 << 1,
++ gcvPOWER_FLAG_STOP = 1 << 2,
++ gcvPOWER_FLAG_START = 1 << 3,
++ gcvPOWER_FLAG_RELEASE = 1 << 4,
++ gcvPOWER_FLAG_DELAY = 1 << 5,
++ gcvPOWER_FLAG_SAVE = 1 << 6,
++ gcvPOWER_FLAG_ACQUIRE = 1 << 7,
++ gcvPOWER_FLAG_POWER_OFF = 1 << 8,
++ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9,
++ gcvPOWER_FLAG_CLOCK_ON = 1 << 10,
++ gcvPOWER_FLAG_NOP = 1 << 11,
++}
++gcePOWER_FLAGS;
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_ResetGPU(
++ IN gckOS Os
++ )
++{
++ gctUINT32 control, idle;
++ gceSTATUS status;
++
++ /* Read register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ for (;;)
++ {
++ /* Disable clock gating. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00104,
++ 0x00000000));
++
++ /* Wait for clock being stable. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Isolate the GPU. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Set soft reset. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Wait for reset. */
++ gcmkONERROR(gckOS_Delay(Os, 1));
++
++ /* Reset soft reset bit. */
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12)))));
++
++ /* Reset GPU isolation. */
++ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19)));
++
++ gcmkONERROR(gckOS_WriteRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ control));
++
++ /* Read idle register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00004,
++ &idle));
++
++ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0)
++ {
++ continue;
++ }
++
++ /* Read reset register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(Os,
++ gcvCORE_VG,
++ 0x00000,
++ &control));
++
++ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0)
++ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0)
++ )
++ {
++ continue;
++ }
++
++ /* GPU is idle. */
++ break;
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the error. */
++ return status;
++}
++
++
++static gceSTATUS
++_IdentifyHardware(
++ IN gckOS Os,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32 * ChipFeatures,
++ OUT gctUINT32 * ChipMinorFeatures,
++ OUT gctUINT32 * ChipMinorFeatures2
++ )
++{
++ gceSTATUS status;
++ gctUINT32 chipIdentity;
++
++ do
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, 0x00018, &chipIdentity));
++
++ /* Special case for older graphic cores. */
++ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))))
++ {
++ *ChipModel = gcv500;
++ *ChipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) );
++ }
++
++ else
++ {
++ /* Read chip identity register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00020,
++ (gctUINT32 *) ChipModel));
++
++ /* Read CHIP_REV register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG,
++ 0x00024,
++ ChipRevision));
++ }
++
++ /* Read chip feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x0001C, ChipFeatures
++ ));
++
++ /* Read chip minor feature register. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00034, ChipMinorFeatures
++ ));
++
++ /* Read chip minor feature register #2. */
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(
++ Os, gcvCORE_VG, 0x00074, ChipMinorFeatures2
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_VERBOSE,
++ "ChipModel=0x%08X\n"
++ "ChipRevision=0x%08X\n"
++ "ChipFeatures=0x%08X\n"
++ "ChipMinorFeatures=0x%08X\n"
++ "ChipMinorFeatures2=0x%08X\n",
++ *ChipModel,
++ *ChipRevision,
++ *ChipFeatures,
++ *ChipMinorFeatures,
++ *ChipMinorFeatures2
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++void
++_VGPowerTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckVGHARDWARE hardware = (gckVGHARDWARE)Data;
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT));
++}
++#endif
++
++/******************************************************************************\
++****************************** gckVGHARDWARE API code *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Construct
++**
++** Construct a new gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an initialized gckOS object.
++**
++** OUTPUT:
++**
++** gckVGHARDWARE * Hardware
++** Pointer to a variable that will hold the pointer to the gckVGHARDWARE
++** object.
++*/
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ )
++{
++ gckVGHARDWARE hardware = gcvNULL;
++ gceSTATUS status;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x ", Os, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ status = _ResetGPU(Os);
++
++ if (status != gcvSTATUS_OK)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "_ResetGPU failed: status=%d\n", status);
++ }
++
++ /* Identify the hardware. */
++ gcmkERR_BREAK(_IdentifyHardware(Os,
++ &chipModel, &chipRevision,
++ &chipFeatures, &chipMinorFeatures, &chipMinorFeatures2
++ ));
++
++ /* Allocate the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckVGHARDWARE), (gctPOINTER *) &hardware
++ ));
++
++ /* Initialize the gckVGHARDWARE object. */
++ hardware->object.type = gcvOBJ_HARDWARE;
++ hardware->os = Os;
++
++ /* Set chip identity. */
++ hardware->chipModel = chipModel;
++ hardware->chipRevision = chipRevision;
++ hardware->chipFeatures = chipFeatures;
++ hardware->chipMinorFeatures = chipMinorFeatures;
++ hardware->chipMinorFeatures2 = chipMinorFeatures2;
++
++ hardware->powerMutex = gcvNULL;
++ hardware->chipPowerState = gcvPOWER_ON;
++ hardware->chipPowerStateGlobal = gcvPOWER_ON;
++ hardware->clockState = gcvTRUE;
++ hardware->powerState = gcvTRUE;
++
++#if gcdPOWEROFF_TIMEOUT
++ hardware->powerOffTime = 0;
++ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT;
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(Os,
++ _VGPowerTimerFunction,
++ (gctPOINTER)hardware,
++ &hardware->powerOffTimer));
++#endif
++
++ /* Determine whether FE 2.0 is present. */
++ hardware->fe20 = ((((gctUINT32) (hardware->chipFeatures)) >> (0 ? 28:28) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))));
++
++ /* Determine whether VG 2.0 is present. */
++ hardware->vg20 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 13:13) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))));
++
++ /* Determine whether VG 2.1 is present. */
++ hardware->vg21 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))));
++
++ /* Set default event mask. */
++ hardware->eventMask = 0xFFFFFFFF;
++
++ gcmkERR_BREAK(gckOS_AtomConstruct(Os, &hardware->pageTableDirty));
++
++ /* Set fast clear to auto. */
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(hardware, -1));
++
++ gcmkERR_BREAK(gckOS_CreateMutex(Os, &hardware->powerMutex));
++
++ /* Enable power management by default. */
++ hardware->powerManagement = gcvTRUE;
++
++ /* Return pointer to the gckVGHARDWARE object. */
++ *Hardware = hardware;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++#if gcdPOWEROFF_TIMEOUT
++ if (hardware->powerOffTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer));
++ }
++#endif
++
++ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvFALSE, gcvFALSE));
++
++ if (hardware != gcvNULL && hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty));
++ }
++
++ if (hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Free(Os, hardware));
++ }
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Destroy
++**
++** Destroy an gckVGHARDWARE object.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Mark the object as unknown. */
++ Hardware->object.type = gcvOBJ_UNKNOWN;
++
++ if (Hardware->powerMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(
++ Hardware->os, Hardware->powerMutex));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer));
++#endif
++
++ if (Hardware->pageTableDirty != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty));
++ }
++
++ /* Free the object. */
++ status = gckOS_Free(Hardware->os, Hardware);
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryMemory
++**
++** Query the amount of memory available on the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * InternalSize
++** Pointer to a variable that will hold the size of the internal video
++** memory in bytes. If 'InternalSize' is gcvNULL, no information of the
++** internal memory will be returned.
++**
++** gctUINT32 * InternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * InternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the internal video memory. This pointer cannot be gcvNULL if
++** 'InternalSize' is also non-gcvNULL.
++**
++** gctSIZE_T * ExternalSize
++** Pointer to a variable that will hold the size of the external video
++** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the
++** external memory will be returned.
++**
++** gctUINT32 * ExternalBaseAddress
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * ExternalAlignment
++** Pointer to a variable that will hold the hardware's base address for
++** the external video memory. This pointer cannot be gcvNULL if
++** 'ExternalSize' is also non-gcvNULL.
++**
++** gctUINT32 * HorizontalTileSize
++** Number of horizontal pixels per tile. If 'HorizontalTileSize' is
++** gcvNULL, no horizontal pixel per tile will be returned.
++**
++** gctUINT32 * VerticalTileSize
++** Number of vertical pixels per tile. If 'VerticalTileSize' is
++** gcvNULL, no vertical pixel per tile will be returned.
++*/
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x InternalSize=0x%x InternalBaseAddress=0x%x InternalAlignment=0x%x"
++ "ExternalSize=0x%x ExternalBaseAddress=0x%x ExternalAlignment=0x%x HorizontalTileSize=0x%x VerticalTileSize=0x%x",
++ Hardware, InternalSize, InternalBaseAddress, InternalAlignment,
++ ExternalSize, ExternalBaseAddress, ExternalAlignment, HorizontalTileSize, VerticalTileSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (InternalSize != gcvNULL)
++ {
++ /* No internal memory. */
++ *InternalSize = 0;
++ }
++
++ if (ExternalSize != gcvNULL)
++ {
++ /* No external memory. */
++ *ExternalSize = 0;
++ }
++
++ if (HorizontalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *HorizontalTileSize = 4;
++ }
++
++ if (VerticalTileSize != gcvNULL)
++ {
++ /* 4x4 tiles. */
++ *VerticalTileSize = 4;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QueryChipIdentity
++**
++** Query the identity of the hardware.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gceCHIPMODEL * ChipModel
++** If 'ChipModel' is not gcvNULL, the variable it points to will
++** receive the model of the chip.
++**
++** gctUINT32 * ChipRevision
++** If 'ChipRevision' is not gcvNULL, the variable it points to will
++** receive the revision of the chip.
++**
++** gctUINT32 * ChipFeatures
++** If 'ChipFeatures' is not gcvNULL, the variable it points to will
++** receive the feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures
++** If 'ChipMinorFeatures' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++** gctUINT32 * ChipMinorFeatures2
++** If 'ChipMinorFeatures2' is not gcvNULL, the variable it points to
++** will receive the minor feature set of the chip.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL * ChipModel,
++ OUT gctUINT32 * ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures2
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x ChipModel=0x%x ChipRevision=0x%x ChipFeatures = 0x%x ChipMinorFeatures = 0x%x ChipMinorFeatures2 = 0x%x",
++ Hardware, ChipModel, ChipRevision, ChipFeatures, ChipMinorFeatures, ChipMinorFeatures2);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Return chip model. */
++ if (ChipModel != gcvNULL)
++ {
++ *ChipModel = Hardware->chipModel;
++ }
++
++ /* Return revision number. */
++ if (ChipRevision != gcvNULL)
++ {
++ *ChipRevision = Hardware->chipRevision;
++ }
++
++ /* Return feature set. */
++ if (ChipFeatures != gcvNULL)
++ {
++ gctUINT32 features = Hardware->chipFeatures;
++
++ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)));
++ }
++
++ /* Mark 2D pipe as available for GC500.0 since it did not have this *\
++ \* bit. */
++ if ((Hardware->chipModel == gcv500)
++ && (Hardware->chipRevision == 0)
++ )
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ /* Mark 2D pipe as available for GC300 since it did not have this *\
++ \* bit. */
++ if (Hardware->chipModel == gcv300)
++ {
++ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9)));
++ }
++
++ *ChipFeatures = features;
++ }
++
++ /* Return minor feature set. */
++ if (ChipMinorFeatures != gcvNULL)
++ {
++ *ChipMinorFeatures = Hardware->chipMinorFeatures;
++ }
++
++ /* Return minor feature set #2. */
++ if (ChipMinorFeatures2 != gcvNULL)
++ {
++ *ChipMinorFeatures2 = Hardware->chipMinorFeatures2;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertFormat
++**
++** Convert an API format to hardware parameters.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gceSURF_FORMAT Format
++** API format to convert.
++**
++** OUTPUT:
++**
++** gctUINT32 * BitsPerPixel
++** Pointer to a variable that will hold the number of bits per pixel.
++**
++** gctUINT32 * BytesPerTile
++** Pointer to a variable that will hold the number of bytes per tile.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ )
++{
++ gctUINT32 bitsPerPixel;
++ gctUINT32 bytesPerTile;
++
++ gcmkHEADER_ARG("Hardware=0x%x Format=0x%x BitsPerPixel=0x%x BytesPerTile = 0x%x",
++ Hardware, Format, BitsPerPixel, BytesPerTile);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Dispatch on format. */
++ switch (Format)
++ {
++ case gcvSURF_A1:
++ case gcvSURF_L1:
++ /* 1-bpp format. */
++ bitsPerPixel = 1;
++ bytesPerTile = (1 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_A4:
++ /* 4-bpp format. */
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_INDEX8:
++ case gcvSURF_A8:
++ case gcvSURF_L8:
++ /* 8-bpp format. */
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_YV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_NV12:
++ /* 12-bpp planar YUV formats. */
++ bitsPerPixel = 12;
++ bytesPerTile = (12 * 4 * 4) / 8;
++ break;
++
++ /* 4444 variations. */
++ case gcvSURF_X4R4G4B4:
++ case gcvSURF_A4R4G4B4:
++ case gcvSURF_R4G4B4X4:
++ case gcvSURF_R4G4B4A4:
++ case gcvSURF_B4G4R4X4:
++ case gcvSURF_B4G4R4A4:
++ case gcvSURF_X4B4G4R4:
++ case gcvSURF_A4B4G4R4:
++
++ /* 1555 variations. */
++ case gcvSURF_X1R5G5B5:
++ case gcvSURF_A1R5G5B5:
++ case gcvSURF_R5G5B5X1:
++ case gcvSURF_R5G5B5A1:
++ case gcvSURF_X1B5G5R5:
++ case gcvSURF_A1B5G5R5:
++ case gcvSURF_B5G5R5X1:
++ case gcvSURF_B5G5R5A1:
++
++ /* 565 variations. */
++ case gcvSURF_R5G6B5:
++ case gcvSURF_B5G6R5:
++
++ case gcvSURF_A8L8:
++ case gcvSURF_YUY2:
++ case gcvSURF_UYVY:
++ case gcvSURF_D16:
++ /* 16-bpp format. */
++ bitsPerPixel = 16;
++ bytesPerTile = (16 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_X8R8G8B8:
++ case gcvSURF_A8R8G8B8:
++ case gcvSURF_X8B8G8R8:
++ case gcvSURF_A8B8G8R8:
++ case gcvSURF_R8G8B8X8:
++ case gcvSURF_R8G8B8A8:
++ case gcvSURF_B8G8R8X8:
++ case gcvSURF_B8G8R8A8:
++ case gcvSURF_D32:
++ /* 32-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_D24S8:
++ /* 24-bpp format. */
++ bitsPerPixel = 32;
++ bytesPerTile = (32 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT1:
++ case gcvSURF_ETC1:
++ bitsPerPixel = 4;
++ bytesPerTile = (4 * 4 * 4) / 8;
++ break;
++
++ case gcvSURF_DXT2:
++ case gcvSURF_DXT3:
++ case gcvSURF_DXT4:
++ case gcvSURF_DXT5:
++ bitsPerPixel = 8;
++ bytesPerTile = (8 * 4 * 4) / 8;
++ break;
++
++ default:
++ /* Invalid format. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Set the result. */
++ if (BitsPerPixel != gcvNULL)
++ {
++ * BitsPerPixel = bitsPerPixel;
++ }
++
++ if (BytesPerTile != gcvNULL)
++ {
++ * BytesPerTile = bytesPerTile;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SplitMemory
++**
++** Split a hardware specific memory address into a pool and offset.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address in hardware specific format.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to a variable that will hold the pool type for the address.
++**
++** gctUINT32 * Offset
++** Pointer to a variable that will hold the offset for the address.
++*/
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Pool=0x%x Offset = 0x%x",
++ Hardware, Address, Pool, Offset);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Offset != gcvNULL);
++
++ /* Dispatch on memory type. */
++ switch ((((((gctUINT32) (Address)) >> (0 ? 1:0)) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1)))))) ))
++ {
++ case 0x0:
++ /* System memory. */
++ *Pool = gcvPOOL_SYSTEM;
++ break;
++
++ case 0x2:
++ /* Virtual memory. */
++ *Pool = gcvPOOL_VIRTUAL;
++ break;
++
++ default:
++ /* Invalid memory type. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Return offset of address. */
++ *Offset = ((((gctUINT32) (Address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_Execute
++**
++** Kickstart the hardware's command processor with an initialized command
++** buffer.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to the gckVGHARDWARE object.
++**
++** gctUINT32 Address
++** Address of the command buffer.
++**
++** gctSIZE_T Count
++** Number of command-sized data units to be executed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Count=0x%x",
++ Hardware, Address, Count);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ /* Enable all events. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00014,
++ Hardware->eventMask
++ ));
++
++ if (Hardware->fe20)
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00500,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00504,
++ Count
++ ));
++ }
++ else
++ {
++ /* Write address register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00654,
++ gcmkFIXADDRESS(Address)
++ ));
++
++ /* Write control register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(
++ Hardware->os,
++ gcvCORE_VG,
++ 0x00658,
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) |
++ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_AlignToTile
++**
++** Align the specified width and height to tile boundaries.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gceSURF_TYPE Type
++** Type of alignment.
++**
++** gctUINT32 * Width
++** Pointer to the width to be aligned. If 'Width' is gcvNULL, no width
++** will be aligned.
++**
++** gctUINT32 * Height
++** Pointer to the height to be aligned. If 'Height' is gcvNULL, no height
++** will be aligned.
++**
++** OUTPUT:
++**
++** gctUINT32 * Width
++** Pointer to a variable that will receive the aligned width.
++**
++** gctUINT32 * Height
++** Pointer to a variable that will receive the aligned height.
++*/
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32 * Width,
++ IN OUT gctUINT32 * Height
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Type=0x%x Width=0x%x Height=0x%x",
++ Hardware, Type, Width, Height);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (Width != gcvNULL)
++ {
++ /* Align the width. */
++ *Width = gcmALIGN(*Width, (Type == gcvSURF_TEXTURE) ? 4 : 16);
++ }
++
++ if (Height != gcvNULL)
++ {
++ /* Special case for VG images. */
++ if ((*Height == 0) && (Type == gcvSURF_IMAGE))
++ {
++ *Height = 4;
++ }
++ else
++ {
++ /* Align the height. */
++ *Height = gcmALIGN(*Height, 4);
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_ConvertLogical
++**
++** Convert a logical system address into a hardware specific address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Hardware
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address to convert.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the memory in user space.
++**
++** gctUINT32* Address
++** Return hardware specific address.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d Address=0x%x",
++ Hardware, Logical, InUserSpace, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ /* Convert logical address into a physical address. */
++ if (InUserSpace)
++ {
++ gcmkERR_BREAK(gckOS_UserLogicalToPhysical(
++ Hardware->os, Logical, &address
++ ));
++ }
++ else
++ {
++ gcmkERR_BREAK(gckOS_GetPhysicalAddress(
++ Hardware->os, Logical, &address
++ ));
++ }
++
++ /* Return hardware specific address. */
++ *Address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_QuerySystemMemory
++**
++** Query the command buffer alignment and number of reserved bytes.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * SystemSize
++** Pointer to a variable that receives the maximum size of the system
++** memory.
++**
++** gctUINT32 * SystemBaseAddress
++** Poinetr to a variable that receives the base address for system
++** memory.
++*/
++gceSTATUS gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x SystemSize=0x%x SystemBaseAddress=0x%x",
++ Hardware, SystemSize, SystemBaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ if (SystemSize != gcvNULL)
++ {
++ /* Maximum system memory can be 2GB. */
++ *SystemSize = (gctSIZE_T)(1 << 31);
++ }
++
++ if (SystemBaseAddress != gcvNULL)
++ {
++ /* Set system memory base address. */
++ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetMMU
++**
++** Set the page table base address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctPOINTER Logical
++** Logical address of the page table.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 address = 0;
++
++ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x",
++ Hardware, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ do
++ {
++ /* Convert the logical address into an hardware address. */
++ gcmkERR_BREAK(gckVGHARDWARE_ConvertLogical(Hardware, Logical,
++ gcvFALSE, &address));
++
++ /* Write the AQMemoryFePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00400,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryTxPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00404,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryPePageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00408,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryPezPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x0040C,
++ gcmkFIXADDRESS(address)));
++
++ /* Write the AQMemoryRaPageTable register. */
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00410,
++ gcmkFIXADDRESS(address)));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_FlushMMU
++**
++** Flush the page table.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x ", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++ gctUINT32_PTR buffer;
++
++ /* Create a shortcut to the command buffer object. */
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &commandBuffer, (gctPOINTER *) &buffer
++ ));
++
++ buffer[0]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16)));
++
++ buffer[1]
++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3)))
++ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4)));
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_BuildVirtualAddress
++**
++** Build a virtual address.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckVGHARDWARE object.
++**
++** gctUINT32 Index
++** Index into page table.
++**
++** gctUINT32 Offset
++** Offset into page.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable receiving te hardware address.
++*/
++gceSTATUS gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ )
++{
++ gctUINT32 address;
++
++ gcmkHEADER_ARG("Hardware=0x%x Index=0x%x Offset=0x%x Address=0x%x",
++ Hardware, Index, Offset, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Build virtual address. */
++ address = (Index << 12) | Offset;
++
++ /* Set virtual type. */
++ address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0)));
++
++ /* Set the result. */
++ *Address = address;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x Data=0x%x", Hardware, Data);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ /* Read register and return. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, Data);
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ )
++{
++ gctUINT32 debug;
++ gceSTATUS status;
++
++ if (!(((((gctUINT32) (Hardware->chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ))
++ {
++ return gcvSTATUS_OK;
++ }
++
++ do
++ {
++ if (Enable == -1)
++ {
++ Enable = (Hardware->chipModel > gcv500) ||
++ ((Hardware->chipModel == gcv500) && (Hardware->chipRevision >= 3));
++ }
++
++ gcmkERR_BREAK(gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ &debug));
++
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20)));
++
++#ifdef AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION
++ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION)));
++#endif
++
++ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00414,
++ debug));
++
++ Hardware->allowFastClear = Enable;
++
++ status = gcvFALSE;
++ }
++ while (gcvFALSE);
++
++ return status;
++}
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Hardware=0x%x IDs=0x%x", Hardware, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IDs != gcvNULL);
++
++ /* Read AQIntrAcknowledge register. */
++ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG,
++ 0x00010,
++ IDs);
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS _CommandStall(
++ gckVGHARDWARE Hardware)
++{
++ gceSTATUS status;
++ gckVGCOMMAND command;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ do
++ {
++ gctUINT32_PTR buffer;
++ command = Hardware->kernel->command;
++
++ /* Allocate command buffer space. */
++ gcmkERR_BREAK(gckVGCOMMAND_Allocate(
++ command, 8, &command->powerStallBuffer,
++ (gctPOINTER *) &buffer
++ ));
++
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ command, buffer, gcvBLOCK_PIXEL,
++ command->powerStallInt, gcvNULL));
++
++ gcmkERR_BREAK(gckVGCOMMAND_Execute(
++ command,
++ command->powerStallBuffer
++ ));
++
++ /* Wait the signal. */
++ gcmkERR_BREAK(gckOS_WaitSignal(
++ command->os,
++ command->powerStallSignal,
++ command->kernel->kernel->timeOut));
++
++
++ }
++ while(gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_SetPowerManagementState
++**
++** Set GPU to a specified power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ )
++{
++ gceSTATUS status;
++ gckVGCOMMAND command = gcvNULL;
++ gckOS os;
++ gctUINT flag/*, clock*/;
++
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL stall = gcvTRUE;
++ gctBOOL commitMutex = gcvFALSE;
++ gctBOOL mutexAcquired = gcvFALSE;
++
++#if gcdPOWEROFF_TIMEOUT
++ gctBOOL timeout = gcvFALSE;
++ gctBOOL isAfter = gcvFALSE;
++ gctUINT32 currentTime;
++#endif
++
++ gctBOOL broadcast = gcvFALSE;
++ gctUINT32 process, thread;
++ gctBOOL global = gcvFALSE;
++
++#if gcdENABLE_PROFILING
++ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime,
++ initTime, offTime, startTime, totalTime;
++#endif
++
++ /* State transition flags. */
++ static const gctUINT flags[4][4] =
++ {
++ /* gcvPOWER_ON */
++ { /* ON */ 0,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_NOP,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STALL |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_OFF */
++ { /* ON */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* OFF */ 0,
++ /* IDLE */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY,
++ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_IDLE */
++ { /* ON */ gcvPOWER_FLAG_NOP,
++ /* OFF */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ 0,
++ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE |
++ gcvPOWER_FLAG_STOP |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ },
++
++ /* gcvPOWER_SUSPEND */
++ { /* ON */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* OFF */ gcvPOWER_FLAG_SAVE |
++ gcvPOWER_FLAG_POWER_OFF |
++ gcvPOWER_FLAG_CLOCK_OFF,
++ /* IDLE */ gcvPOWER_FLAG_START |
++ gcvPOWER_FLAG_DELAY |
++ gcvPOWER_FLAG_RELEASE |
++ gcvPOWER_FLAG_CLOCK_ON,
++ /* SUSPEND */ 0,
++ },
++ };
++
++ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State);
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "Switching to power state %d",
++ State);
++#endif
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ /* Get the gckOS object pointer. */
++ os = Hardware->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Get the gckCOMMAND object pointer. */
++ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL);
++ command = Hardware->kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++ if (Hardware->powerManagement == gcvFALSE)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Start profiler. */
++ gcmkPROFILE_INIT(freq, time);
++
++ /* Convert the broadcast power state. */
++ switch (State)
++ {
++ case gcvPOWER_SUSPEND_ATPOWERON:
++ /* Convert to SUSPEND and don't wait for STALL. */
++ State = gcvPOWER_SUSPEND;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_OFF_ATPOWERON:
++ /* Convert to OFF and don't wait for STALL. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ break;
++
++ case gcvPOWER_IDLE_BROADCAST:
++ /* Convert to IDLE and note we are inside broadcast. */
++ State = gcvPOWER_IDLE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_SUSPEND_BROADCAST:
++ /* Convert to SUSPEND and note we are inside broadcast. */
++ State = gcvPOWER_SUSPEND;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_BROADCAST:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_OFF_RECOVERY:
++ /* Convert to OFF and note we are inside recovery. */
++ State = gcvPOWER_OFF;
++ stall = gcvFALSE;
++ broadcast = gcvTRUE;
++ break;
++
++ case gcvPOWER_ON_AUTO:
++ /* Convert to ON and note we are inside recovery. */
++ State = gcvPOWER_ON;
++ break;
++
++ case gcvPOWER_ON:
++ case gcvPOWER_IDLE:
++ case gcvPOWER_SUSPEND:
++ case gcvPOWER_OFF:
++ /* Mark as global power management. */
++ global = gcvTRUE;
++ break;
++
++#if gcdPOWEROFF_TIMEOUT
++ case gcvPOWER_OFF_TIMEOUT:
++ /* Convert to OFF and note we are inside broadcast. */
++ State = gcvPOWER_OFF;
++ broadcast = gcvTRUE;
++ /* Check time out */
++ timeout = gcvTRUE;
++ break;
++#endif
++
++ default:
++ break;
++ }
++
++ /* Get current process and thread IDs. */
++ gcmkONERROR(gckOS_GetProcessID(&process));
++ gcmkONERROR(gckOS_GetThreadID(&thread));
++
++ /* Acquire the power mutex. */
++ if (broadcast)
++ {
++ /* Try to acquire the power mutex. */
++ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 0);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Check if we already own this mutex. */
++ if ((Hardware->powerProcess == process)
++ && (Hardware->powerThread == thread)
++ )
++ {
++ /* Bail out on recursive power management. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ else if (State == gcvPOWER_IDLE)
++ {
++ /* gcvPOWER_IDLE_BROADCAST is from IST,
++ ** so waiting here will cause deadlock,
++ ** if lock holder call gckCOMMAND_Stall() */
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os,
++ Hardware->powerMutex,
++ gcvINFINITE));
++ }
++ }
++ }
++ else
++ {
++ /* Acquire the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE));
++ }
++
++ /* Get time until mtuex acquired. */
++ gcmkPROFILE_QUERY(time, mutexTime);
++
++ Hardware->powerProcess = process;
++ Hardware->powerThread = thread;
++ mutexAcquired = gcvTRUE;
++
++ /* Grab control flags and clock. */
++ flag = flags[Hardware->chipPowerState][State];
++ /*clock = clocks[State];*/
++
++#if gcdPOWEROFF_TIMEOUT
++ if (timeout)
++ {
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ gcmkONERROR(
++ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter));
++
++ /* powerOffTime is pushed forward, give up.*/
++ if (isAfter
++ /* Expect a transition start from IDLE. */
++ || (Hardware->chipPowerState == gcvPOWER_ON)
++ || (Hardware->chipPowerState == gcvPOWER_OFF)
++ )
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++#endif
++
++ if (flag == 0)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* internal power control */
++ if (!global)
++ {
++ if (Hardware->chipPowerStateGlobal == gcvPOWER_OFF)
++ {
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* No need to do anything. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++ acquired = gcvTRUE;
++
++ /* avoid acquiring again. */
++ flag &= ~gcvPOWER_FLAG_ACQUIRE;
++ }
++ }
++
++ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON))
++ {
++ /* Turn on the power. */
++ gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG, gcvTRUE, gcvTRUE));
++
++ /* Mark clock and power as enabled. */
++ Hardware->clockState = gcvTRUE;
++ Hardware->powerState = gcvTRUE;
++ }
++
++ /* Get time until powered on. */
++ gcmkPROFILE_QUERY(time, onTime);
++
++ if ((flag & gcvPOWER_FLAG_STALL) && stall)
++ {
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ command->os,
++ command->commitMutex,
++ gcvINFINITE
++ ));
++
++ commitMutex = gcvTRUE;
++
++ gcmkONERROR(_CommandStall(Hardware));
++ }
++
++ /* Get time until stalled. */
++ gcmkPROFILE_QUERY(time, stallTime);
++
++ if (flag & gcvPOWER_FLAG_ACQUIRE)
++ {
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore));
++
++ acquired = gcvTRUE;
++ }
++
++
++ /* Get time until stopped. */
++ gcmkPROFILE_QUERY(time, stopTime);
++
++
++ if (flag & gcvPOWER_FLAG_DELAY)
++ {
++ /* Wait for the specified amount of time to settle coming back from
++ ** power-off or suspend state. */
++ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY));
++ }
++
++ /* Get time until delayed. */
++ gcmkPROFILE_QUERY(time, delayTime);
++
++ if (flag & gcvPOWER_FLAG_INITIALIZE)
++ {
++
++ /* Initialize GPU here, replaced by InitializeHardware later */
++ gcmkONERROR(gckVGHARDWARE_SetMMU(Hardware, Hardware->kernel->mmu->pageTableLogical));
++ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(Hardware, -1));
++
++ /* Force the command queue to reload the next context. */
++ command->currentContext = 0;
++ }
++
++ /* Get time until initialized. */
++ gcmkPROFILE_QUERY(time, initTime);
++
++ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF))
++ {
++ /* Turn off the GPU power. */
++ gcmkONERROR(
++ gckOS_SetGPUPower(os,
++ gcvCORE_VG,
++ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE,
++ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE));
++
++ /* Save current hardware power and clock states. */
++ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE
++ : gcvTRUE;
++ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE
++ : gcvTRUE;
++ }
++
++ /* Get time until off. */
++ gcmkPROFILE_QUERY(time, offTime);
++
++
++ /* Get time until started. */
++ gcmkPROFILE_QUERY(time, startTime);
++
++ if (flag & gcvPOWER_FLAG_RELEASE)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore));
++ acquired = gcvFALSE;
++ }
++
++ /* Save the new power state. */
++ Hardware->chipPowerState = State;
++
++ if (global)
++ {
++ /* Save the new power state. */
++ Hardware->chipPowerStateGlobal = State;
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++#if gcdPOWEROFF_TIMEOUT
++ /* Reset power off time */
++ gcmkONERROR(gckOS_GetTicks(&currentTime));
++
++ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout;
++
++ if (State == gcvPOWER_IDLE)
++ {
++ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */
++ gcmkVERIFY_OK(gckOS_StartTimer(os,
++ Hardware->powerOffTimer,
++ Hardware->powerOffTimeout));
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer");
++
++ /* Cancel running timer when GPU enters ON or OFF. */
++ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer));
++ }
++#endif
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex));
++
++ /* Get total time. */
++ gcmkPROFILE_QUERY(time, totalTime);
++#if gcdENABLE_PROFILING
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu",
++ freq, mutexTime, onTime, stallTime, stopTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE,
++ " delay:%llu init:%llu off:%llu start:%llu total:%llu",
++ delayTime, initTime, offTime, startTime, totalTime);
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (acquired)
++ {
++ /* Release semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os,
++ command->powerSemaphore));
++ }
++
++ if (mutexAcquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex));
++ }
++
++ if (commitMutex)
++ {
++ /* Acquire the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ command->os,
++ command->commitMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHARDWARE_QueryPowerManagementState
++**
++** Get GPU power state.
++**
++** INPUT:
++**
++** gckHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gceCHIPPOWERSTATE* State
++** Power State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(State != gcvNULL);
++
++ /* Return the statue. */
++ *State = Hardware->chipPowerState;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGHARDWARE_SetPowerManagement
++**
++** Configure GPU power management function.
++** Only used in driver initialization stage.
++**
++** INPUT:
++**
++** gckVGHARDWARE Harwdare
++** Pointer to an gckHARDWARE object.
++**
++** gctBOOL PowerManagement
++** Power Mangement State.
++**
++*/
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ Hardware->powerManagement = PowerManagement;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout);
++
++ Hardware->powerOffTimeout = Timeout;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ )
++{
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ *Timeout = Hardware->powerOffTimeout;
++
++ gcmkFOOTER_ARG("*Timeout=%d", *Timeout);
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Hardware=0x%x", Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL);
++
++ /* We are idle when the power is not ON. */
++ if (Hardware->chipPowerState != gcvPOWER_ON)
++ {
++ *IsIdle = gcvTRUE;
++ }
++
++ else
++ {
++ /* Read idle register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, &idle));
++
++ /* Pipe must be idle. */
++ if (((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 8:8)) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 10:10)) & ((gctUINT32) ((((1 ? 10:10) - (0 ? 10:10) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 10:10) - (0 ? 10:10) + 1)))))) ) != 1)
++ || ((((((gctUINT32) (idle)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ) != 1)
++ )
++ {
++ /* Something is busy. */
++ *IsIdle = gcvFALSE;
++ }
++
++ else
++ {
++ *IsIdle = gcvTRUE;
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif /* gcdENABLE_VG */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/archvg/gc_hal_kernel_hardware_vg.h 2016-06-19 22:11:55.217145781 +0200
+@@ -0,0 +1,74 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_hardware_vg_h_
++#define __gc_hal_kernel_hardware_vg_h_
++
++/* gckHARDWARE object. */
++struct _gckVGHARDWARE
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckKERNEL object. */
++ gckVGKERNEL kernel;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Chip characteristics. */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 chipFeatures;
++ gctUINT32 chipMinorFeatures;
++ gctUINT32 chipMinorFeatures2;
++ gctBOOL allowFastClear;
++
++ /* Features. */
++ gctBOOL fe20;
++ gctBOOL vg20;
++ gctBOOL vg21;
++
++ /* Event mask. */
++ gctUINT32 eventMask;
++
++ gctBOOL clockState;
++ gctBOOL powerState;
++ gctPOINTER powerMutex;
++ gctUINT32 powerProcess;
++ gctUINT32 powerThread;
++ gceCHIPPOWERSTATE chipPowerState;
++ gceCHIPPOWERSTATE chipPowerStateGlobal;
++ gctISRMANAGERFUNC startIsr;
++ gctISRMANAGERFUNC stopIsr;
++ gctPOINTER isrContext;
++ gctPOINTER pageTableDirty;
++#if gcdPOWEROFF_TIMEOUT
++ gctUINT32 powerOffTime;
++ gctUINT32 powerOffTimeout;
++ gctPOINTER powerOffTimer;
++#endif
++
++ gctBOOL powerManagement;
++};
++
++#endif /* __gc_hal_kernel_hardware_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c 2016-06-19 22:11:55.221145518 +0200
+@@ -0,0 +1,5040 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/*******************************************************************************
++***** Version Signature *******************************************************/
++
++#define _gcmTXT2STR(t) #t
++#define gcmTXT2STR(t) _gcmTXT2STR(t)
++const char * _VERSION = "\n\0$VERSION$"
++ gcmTXT2STR(gcvVERSION_MAJOR) "."
++ gcmTXT2STR(gcvVERSION_MINOR) "."
++ gcmTXT2STR(gcvVERSION_PATCH) ":"
++ gcmTXT2STR(gcvVERSION_BUILD) "$\n";
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define gcmDEFINE2TEXT(d) #d
++gctCONST_STRING _DispatchText[] =
++{
++ gcmDEFINE2TEXT(gcvHAL_QUERY_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_CHIP_IDENTITY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_NON_PAGED_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_FREE_CONTIGUOUS_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_RELEASE_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_MAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNMAP_USER_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_LOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_UNLOCK_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_EVENT_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_USER_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_SIGNAL),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_DATA),
++ gcmDEFINE2TEXT(gcvHAL_COMMIT),
++ gcmDEFINE2TEXT(gcvHAL_STALL),
++ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER),
++ gcmDEFINE2TEXT(gcvHAL_GET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_SET_PROFILE_SETTING),
++ gcmDEFINE2TEXT(gcvHAL_READ_ALL_PROFILE_REGISTERS),
++ gcmDEFINE2TEXT(gcvHAL_PROFILE_REGISTERS_2D),
++#if VIVANTE_PROFILER_PERDRAW
++ gcvHAL_READ_PROFILER_REGISTER_SETTING,
++#endif
++ gcmDEFINE2TEXT(gcvHAL_SET_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_POWER_MANAGEMENT_STATE),
++ gcmDEFINE2TEXT(gcvHAL_GET_BASE_ADDRESS),
++ gcmDEFINE2TEXT(gcvHAL_SET_IDLE),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_KERNEL_SETTINGS),
++ gcmDEFINE2TEXT(gcvHAL_RESET),
++ gcmDEFINE2TEXT(gcvHAL_MAP_PHYSICAL),
++ gcmDEFINE2TEXT(gcvHAL_DEBUG),
++ gcmDEFINE2TEXT(gcvHAL_CACHE),
++ gcmDEFINE2TEXT(gcvHAL_TIMESTAMP),
++ gcmDEFINE2TEXT(gcvHAL_DATABASE),
++ gcmDEFINE2TEXT(gcvHAL_VERSION),
++ gcmDEFINE2TEXT(gcvHAL_CHIP_INFO),
++ gcmDEFINE2TEXT(gcvHAL_ATTACH),
++ gcmDEFINE2TEXT(gcvHAL_DETACH),
++ gcmDEFINE2TEXT(gcvHAL_COMPOSE),
++ gcmDEFINE2TEXT(gcvHAL_SET_TIMEOUT),
++ gcmDEFINE2TEXT(gcvHAL_GET_FRAME_INFO),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_COMMAND_BUFFER),
++ gcmDEFINE2TEXT(gcvHAL_COMMIT_DONE),
++ gcmDEFINE2TEXT(gcvHAL_DUMP_GPU_STATE),
++ gcmDEFINE2TEXT(gcvHAL_DUMP_EVENT),
++ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER),
++ gcmDEFINE2TEXT(gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER),
++ gcmDEFINE2TEXT(gcvHAL_SET_FSCALE_VALUE),
++ gcmDEFINE2TEXT(gcvHAL_GET_FSCALE_VALUE),
++ gcmDEFINE2TEXT(gcvHAL_NAME_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_IMPORT_VIDEO_MEMORY),
++ gcmDEFINE2TEXT(gcvHAL_QUERY_RESET_TIME_STAMP),
++ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER_EX),
++ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER_EX),
++ gcmDEFINE2TEXT(gcvHAL_SYNC_POINT),
++ gcmDEFINE2TEXT(gcvHAL_CREATE_NATIVE_FENCE),
++ gcmDEFINE2TEXT(gcvHAL_DESTROY_MMU),
++ gcmDEFINE2TEXT(gcvHAL_SHBUF),
++};
++#endif
++
++#if gcdGPU_TIMEOUT && gcdINTERRUPT_STATISTIC
++void
++_MonitorTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckKERNEL kernel = (gckKERNEL)Data;
++ gctUINT32 pendingInterrupt;
++ gctBOOL reset = gcvFALSE;
++ gctUINT32 mask;
++ gctUINT32 advance = kernel->timeOut/2;
++
++#if gcdENABLE_VG
++ if (kernel->core == gcvCORE_VG)
++ {
++ return;
++ }
++#endif
++
++ if (kernel->monitorTimerStop)
++ {
++ /* Stop. */
++ return;
++ }
++
++ gckOS_AtomGet(kernel->os, kernel->eventObj->interruptCount, &pendingInterrupt);
++
++ if (kernel->monitoring == gcvFALSE)
++ {
++ if (pendingInterrupt)
++ {
++ /* Begin to mointor GPU state. */
++ kernel->monitoring = gcvTRUE;
++
++ /* Record current state. */
++ kernel->lastCommitStamp = kernel->eventObj->lastCommitStamp;
++ kernel->restoreAddress = kernel->hardware->lastWaitLink;
++ gcmkVERIFY_OK(gckOS_AtomGet(
++ kernel->os,
++ kernel->hardware->pendingEvent,
++ &kernel->restoreMask
++ ));
++
++ /* Clear timeout. */
++ kernel->timer = 0;
++ }
++ }
++ else
++ {
++ if (pendingInterrupt)
++ {
++ gcmkVERIFY_OK(gckOS_AtomGet(
++ kernel->os,
++ kernel->hardware->pendingEvent,
++ &mask
++ ));
++
++ if (kernel->eventObj->lastCommitStamp == kernel->lastCommitStamp
++ && kernel->hardware->lastWaitLink == kernel->restoreAddress
++ && mask == kernel->restoreMask
++ )
++ {
++ /* GPU state is not changed, accumlate timeout. */
++ kernel->timer += advance;
++
++ if (kernel->timer >= kernel->timeOut)
++ {
++ /* GPU stuck, trigger reset. */
++ reset = gcvTRUE;
++ }
++ }
++ else
++ {
++ /* GPU state changed, cancel current timeout.*/
++ kernel->monitoring = gcvFALSE;
++ }
++ }
++ else
++ {
++ /* GPU finish all jobs, cancel current timeout*/
++ kernel->monitoring = gcvFALSE;
++ }
++ }
++
++ if (reset)
++ {
++ gckKERNEL_Recovery(kernel);
++
++ /* Work in this timeout is done. */
++ kernel->monitoring = gcvFALSE;
++ }
++
++ gcmkVERIFY_OK(gckOS_StartTimer(kernel->os, kernel->monitorTimer, advance));
++}
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++_MapCommandBuffer(
++ IN gckKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++ gctUINT32 i;
++ gctUINT32 physical;
++ gckMMU mmu;
++
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu));
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Kernel->os,
++ Kernel->command->queues[i].logical,
++ &physical
++ ));
++
++ gcmkONERROR(gckMMU_FlatMapping(mmu, physical));
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++#endif
++
++void
++_DumpDriverConfigure(
++ IN gckKERNEL Kernel
++ )
++{
++ gcmkPRINT_N(0, "**************************\n");
++ gcmkPRINT_N(0, "*** GPU DRV CONFIG ***\n");
++ gcmkPRINT_N(0, "**************************\n");
++
++ gcmkPRINT("Galcore version %d.%d.%d.%d\n",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
++
++ gckOS_DumpParam();
++}
++
++void
++_DumpState(
++ IN gckKERNEL Kernel
++ )
++{
++ /* Dump GPU Debug registers. */
++ gcmkVERIFY_OK(gckHARDWARE_DumpGPUState(Kernel->hardware));
++
++ if (Kernel->virtualCommandBuffer)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_DumpExecutingBuffer(Kernel->command));
++ }
++
++ /* Dump Pending event. */
++ gcmkVERIFY_OK(gckEVENT_Dump(Kernel->eventObj));
++
++ /* Dump Process DB. */
++ gcmkVERIFY_OK(gckKERNEL_DumpProcessDB(Kernel));
++
++#if gcdRECORD_COMMAND
++ /* Dump record. */
++ gckRECORDER_Dump(Kernel->command->recorder);
++#endif
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gceCORE Core
++** Specified core.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** IN gckDB SharedDB,
++** Pointer to a shared DB.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ )
++{
++ gckKERNEL kernel = gcvNULL;
++ gceSTATUS status;
++ gctSIZE_T i;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ /* Allocate the gckKERNEL object. */
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckKERNEL),
++ &pointer));
++
++ kernel = pointer;
++
++ /* Zero the object pointers. */
++ kernel->hardware = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->eventObj = gcvNULL;
++ kernel->mmu = gcvNULL;
++#if gcdDVFS
++ kernel->dvfs = gcvNULL;
++#endif
++ kernel->monitorTimer = gcvNULL;
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->core = Core;
++
++ if (SharedDB == gcvNULL)
++ {
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(struct _gckDB),
++ &pointer));
++
++ kernel->db = pointer;
++ kernel->dbCreated = gcvTRUE;
++ kernel->db->freeDatabase = gcvNULL;
++ kernel->db->freeRecord = gcvNULL;
++ kernel->db->dbMutex = gcvNULL;
++ kernel->db->lastDatabase = gcvNULL;
++ kernel->db->idleTime = 0;
++ kernel->db->lastIdle = 0;
++ kernel->db->lastSlowdown = 0;
++
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ kernel->db->db[i] = gcvNULL;
++ }
++
++ /* Construct a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->dbMutex));
++
++ /* Construct a video memory name database. */
++ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->nameDatabase));
++
++ /* Construct a video memory name database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->nameDatabaseMutex));
++
++ /* Construct a pointer name database. */
++ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->pointerDatabase));
++
++ /* Construct a pointer name database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->pointerDatabaseMutex));
++ }
++ else
++ {
++ kernel->db = SharedDB;
++ kernel->dbCreated = gcvFALSE;
++ }
++
++ for (i = 0; i < gcmCOUNTOF(kernel->timers); ++i)
++ {
++ kernel->timers[i].startTime = 0;
++ kernel->timers[i].stopTime = 0;
++ }
++
++ /* Save context. */
++ kernel->context = Context;
++
++ /* Construct atom holding number of clients. */
++ kernel->atomClients = gcvNULL;
++ gcmkONERROR(gckOS_AtomConstruct(Os, &kernel->atomClients));
++
++#if gcdENABLE_VG
++ kernel->vg = gcvNULL;
++
++ if (Core == gcvCORE_VG)
++ {
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckVGKERNEL_Construct(Os, Context, kernel, &kernel->vg));
++
++ kernel->timeOut = gcdGPU_TIMEOUT;
++ }
++ else
++#endif
++ {
++ /* Construct the gckHARDWARE object. */
++ gcmkONERROR(
++ gckHARDWARE_Construct(Os, kernel->core, &kernel->hardware));
++
++ /* Set pointer to gckKERNEL object in gckHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ kernel->timeOut = kernel->hardware->type == gcvHARDWARE_2D
++ ? gcdGPU_2D_TIMEOUT
++ : gcdGPU_TIMEOUT
++ ;
++
++ /* Initialize virtual command buffer. */
++ /* TODO: Remove platform limitation after porting. */
++#if (defined(LINUX) || defined(__QNXNTO__))
++ kernel->virtualCommandBuffer = gcvTRUE;
++#else
++ kernel->virtualCommandBuffer = gcvFALSE;
++#endif
++
++#if gcdSECURITY
++ kernel->virtualCommandBuffer = gcvFALSE;
++#endif
++
++ /* Construct the gckCOMMAND object. */
++ gcmkONERROR(
++ gckCOMMAND_Construct(kernel, &kernel->command));
++
++ /* Construct the gckEVENT object. */
++ gcmkONERROR(
++ gckEVENT_Construct(kernel, &kernel->eventObj));
++
++ /* Construct the gckMMU object. */
++ gcmkONERROR(
++ gckMMU_Construct(kernel, gcdMMU_SIZE, &kernel->mmu));
++
++ gcmkVERIFY_OK(gckOS_GetTime(&kernel->resetTimeStamp));
++
++ gcmkONERROR(gckHARDWARE_PrepareFunctions(kernel->hardware));
++
++ /* Initialize the hardware. */
++ gcmkONERROR(
++ gckHARDWARE_InitializeHardware(kernel->hardware));
++
++#if gcdDVFS
++ if (gckHARDWARE_IsFeatureAvailable(kernel->hardware,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING))
++ {
++ gcmkONERROR(gckDVFS_Construct(kernel->hardware, &kernel->dvfs));
++ gcmkONERROR(gckDVFS_Start(kernel->dvfs));
++ }
++#endif
++ }
++
++#if VIVANTE_PROFILER
++ /* Initialize profile setting */
++ kernel->profileEnable = gcvFALSE;
++ kernel->profileCleanRegister = gcvTRUE;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkONERROR(gckOS_CreateSyncTimeline(Os, &kernel->timeline));
++#endif
++
++ kernel->recovery = gcvTRUE;
++ kernel->stuckDump = 1;
++
++ kernel->virtualBufferHead =
++ kernel->virtualBufferTail = gcvNULL;
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Os, (gctPOINTER)&kernel->virtualBufferLock));
++
++#if gcdSECURITY
++ /* Connect to security service for this GPU. */
++ gcmkONERROR(gckKERNEL_SecurityOpen(kernel, kernel->core, &kernel->securityChannel));
++#endif
++
++#if gcdGPU_TIMEOUT && gcdINTERRUPT_STATISTIC
++ if (kernel->timeOut)
++ {
++ gcmkVERIFY_OK(gckOS_CreateTimer(
++ Os,
++ (gctTIMERFUNCTION)_MonitorTimerFunction,
++ (gctPOINTER)kernel,
++ &kernel->monitorTimer
++ ));
++
++ kernel->monitoring = gcvFALSE;
++
++ kernel->monitorTimerStop = gcvFALSE;
++
++ gcmkVERIFY_OK(gckOS_StartTimer(
++ Os,
++ kernel->monitorTimer,
++ 100
++ ));
++ }
++#endif
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (kernel != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Core != gcvCORE_VG)
++#endif
++ {
++ if (kernel->eventObj != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_Destroy(kernel->eventObj));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ /* Turn off the power. */
++ gcmkVERIFY_OK(gckOS_SetGPUPower(kernel->hardware->os,
++ kernel->hardware->core,
++ gcvFALSE,
++ gcvFALSE));
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(kernel->hardware));
++ }
++ }
++
++ if (kernel->atomClients != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, kernel->atomClients));
++ }
++
++ if (kernel->dbCreated && kernel->db != gcvNULL)
++ {
++ if (kernel->db->dbMutex != gcvNULL)
++ {
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->db->dbMutex));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel->db));
++ }
++
++ if (kernel->virtualBufferLock != gcvNULL)
++ {
++ /* Destroy the virtual command buffer mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->virtualBufferLock));
++ }
++
++#if gcdDVFS
++ if (kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (kernel->timeline)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Os, kernel->timeline));
++ }
++#endif
++
++ if (kernel->monitorTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Os, kernel->monitorTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, kernel->monitorTimer));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel));
++ }
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ )
++{
++ gctSIZE_T i;
++ gcsDATABASE_PTR database, databaseNext;
++ gcsDATABASE_RECORD_PTR record, recordNext;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->debugMutex));
++#endif
++
++ /* Destroy the database. */
++ if (Kernel->dbCreated)
++ {
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ if (Kernel->db->db[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyProcessDB(Kernel, Kernel->db->db[i]->processID));
++ }
++ }
++
++ /* Free all databases. */
++ for (database = Kernel->db->freeDatabase;
++ database != gcvNULL;
++ database = databaseNext)
++ {
++ databaseNext = database->next;
++
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->counterMutex));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, database));
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->lastDatabase->counterMutex));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db->lastDatabase));
++ }
++
++ /* Free all database records. */
++ for (record = Kernel->db->freeRecord; record != gcvNULL; record = recordNext)
++ {
++ recordNext = record->next;
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Destroy the database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Destroy video memory name database. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->nameDatabase));
++
++ /* Destroy video memory name database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->nameDatabaseMutex));
++
++
++ /* Destroy id-pointer database. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->pointerDatabase));
++
++ /* Destroy id-pointer database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++
++ /* Destroy the database. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db));
++
++ /* Notify stuck timer to quit. */
++ Kernel->monitorTimerStop = gcvTRUE;
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg)
++ {
++ gcmkVERIFY_OK(gckVGKERNEL_Destroy(Kernel->vg));
++ }
++ else
++#endif
++ {
++ /* Destroy the gckMMU object. */
++ gcmkVERIFY_OK(gckMMU_Destroy(Kernel->mmu));
++
++ /* Destroy the gckCOMMNAND object. */
++ gcmkVERIFY_OK(gckCOMMAND_Destroy(Kernel->command));
++
++ /* Destroy the gckEVENT object. */
++ gcmkVERIFY_OK(gckEVENT_Destroy(Kernel->eventObj));
++
++ /* Destroy the gckHARDWARE object. */
++ gcmkVERIFY_OK(gckHARDWARE_Destroy(Kernel->hardware));
++ }
++
++ /* Detsroy the client atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Kernel->atomClients));
++
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->virtualBufferLock));
++
++#if gcdDVFS
++ if (Kernel->dvfs)
++ {
++ gcmkVERIFY_OK(gckDVFS_Stop(Kernel->dvfs));
++ gcmkVERIFY_OK(gckDVFS_Destroy(Kernel->dvfs));
++ }
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Kernel->os, Kernel->timeline));
++#endif
++
++#if gcdSECURITY
++ gcmkVERIFY_OK(gckKERNEL_SecurityClose(Kernel->securityChannel));
++#endif
++
++ if (Kernel->monitorTimer)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Kernel->os, Kernel->monitorTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Kernel->os, Kernel->monitorTimer));
++ }
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** _AllocateMemory
++**
++** Private function to walk all required memory pools to allocate the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 Flag,
++ OUT gctUINT32 * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++ gctINT loopCount;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctBOOL tileStatusInVirtual;
++ gctBOOL contiguous = gcvFALSE;
++ gctBOOL cacheable = gcvFALSE;
++ gctSIZE_T bytes = Bytes;
++ gctUINT32 handle = 0;
++ gceDATABASE_TYPE type;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=%d Bytes=%lu Alignment=%lu Type=%d",
++ Kernel, *Pool, Bytes, Alignment, Type);
++
++ gcmkVERIFY_ARGUMENT(Pool != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes != 0);
++
++ /* Get basic type. */
++ Type &= 0xFF;
++
++ /* Check flags. */
++ contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS;
++ cacheable = Flag & gcvALLOC_FLAG_CACHEABLE;
++
++AllocateMemory:
++
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ case gcvPOOL_CONTIGUOUS:
++ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS;
++ break;
++
++ default:
++ loopCount = 1;
++ break;
++ }
++
++ while (loopCount-- > 0)
++ {
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkONERROR(
++ gckVIDMEM_ConstructVirtual(Kernel, Flag | gcvALLOC_FLAG_NON_CONTIGUOUS, Bytes, &node));
++
++ bytes = node->Virtual.bytes;
++ node->Virtual.type = Type;
++
++ /* Success. */
++ break;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++#if gcdCONTIGUOUS_SIZE_LIMIT
++ if (Bytes > gcdCONTIGUOUS_SIZE_LIMIT && contiguous == gcvFALSE)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ }
++ else
++#endif
++ {
++ /* Create a gcuVIDMEM_NODE from contiguous memory. */
++ status = gckVIDMEM_ConstructVirtual(
++ Kernel,
++ Flag | gcvALLOC_FLAG_CONTIGUOUS,
++ Bytes,
++ &node);
++ }
++
++ if (gcmIS_SUCCESS(status))
++ {
++ bytes = node->Virtual.bytes;
++ node->Virtual.type = Type;
++
++ /* Memory allocated. */
++ break;
++ }
++ }
++
++ else
++ /* gcvPOOL_SYSTEM can't be cacheable. */
++ if (cacheable == gcvFALSE)
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Allocate memory. */
++#if defined(gcdLINEAR_SIZE_LIMIT)
++ /* 512 KB */
++ if (Bytes > gcdLINEAR_SIZE_LIMIT)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ }
++ else
++#endif
++ {
++ status = gckVIDMEM_AllocateLinear(Kernel,
++ videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ (*Pool == gcvPOOL_SYSTEM),
++ &node);
++ }
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Memory allocated. */
++ node->VidMem.pool = pool;
++ bytes = node->VidMem.bytes;
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++
++ else
++ if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++
++ else
++ if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to contiguous memory. */
++ pool = gcvPOOL_CONTIGUOUS;
++ }
++
++ else
++ if (pool == gcvPOOL_CONTIGUOUS)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg)
++ {
++ tileStatusInVirtual = gcvFALSE;
++ }
++ else
++#endif
++ {
++ tileStatusInVirtual =
++ gckHARDWARE_IsFeatureAvailable(Kernel->hardware,
++ gcvFEATURE_MC20);
++ }
++
++ if (Type == gcvSURF_TILE_STATUS && tileStatusInVirtual != gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (contiguous)
++ {
++ break;
++ }
++
++ /* Advance to virtual memory. */
++ pool = gcvPOOL_VIRTUAL;
++ }
++
++ else
++ {
++ /* Out of pools. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ if (contiguous)
++ {
++ /* Broadcast OOM message. */
++ status = gckOS_Broadcast(Kernel->os, Kernel->hardware, gcvBROADCAST_OUT_OF_MEMORY);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Get some memory. */
++ gckOS_Delay(gcvNULL, 1);
++ goto AllocateMemory;
++ }
++ }
++
++ /* Nothing allocated. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Allocate handle for this video memory. */
++ gcmkONERROR(
++ gckVIDMEM_NODE_Allocate(Kernel, node, Type, pool, &handle));
++
++ /* Return node and pool used for allocation. */
++ *Node = handle;
++ *Pool = pool;
++
++ /* Encode surface type and pool to database type. */
++ type = gcvDB_VIDEO_MEMORY
++ | (Type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT)
++ | (pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT);
++
++ /* Record in process db. */
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ ProcessID,
++ type,
++ gcmINT2PTR(handle),
++ gcvNULL,
++ bytes));
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Pool=%d *Node=0x%x", *Pool, *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (handle)
++ {
++ /* Destroy handle allocated. */
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(Kernel, ProcessID, handle));
++ }
++
++ if (node)
++ {
++ /* Free video memory allocated. */
++ gcmkVERIFY_OK(gckVIDMEM_Free(Kernel, node));
++ }
++
++ /* For some case like chrome with webgl test, it needs too much memory so that it invokes oom_killer
++ * And the case is killed by oom_killer, the user wants not to see the crash and hope the case iteself handles the condition
++ * So the patch reports the out_of_memory to the case */
++ if ( status == gcvSTATUS_OUT_OF_MEMORY && (Flag & gcvALLOC_FLAG_MEMLIMIT) )
++ gcmkPRINT("The running case is out_of_memory");
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_ReleaseVideoMemory
++**
++** Release handle of a video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID of current process.
++**
++** gctUINT32 Handle
++** Handle of video memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_ReleaseVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject;
++ gceDATABASE_TYPE type;
++
++ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d Handle=%d",
++ Kernel, ProcessID, Handle);
++
++ gcmkONERROR(
++ gckVIDMEM_HANDLE_Lookup(Kernel, ProcessID, Handle, &nodeObject));
++
++ type = gcvDB_VIDEO_MEMORY
++ | (nodeObject->type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT)
++ | (nodeObject->pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT);
++
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ ProcessID,
++ type,
++ gcmINT2PTR(Handle)));
++
++ gckVIDMEM_HANDLE_Dereference(Kernel, ProcessID, Handle);
++
++ gckVIDMEM_NODE_Dereference(Kernel, nodeObject);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_LockVideoMemory
++**
++** Lock a video memory node. It will generate a cpu virtual address used
++** by software and a GPU address used by GPU.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gceCORE Core
++** GPU to which video memory is locked.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_LockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject = gcvNULL;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctBOOL locked = gcvFALSE;
++ gctBOOL asynchronous = gcvFALSE;
++#ifndef __QNXNTO__
++ gctPOINTER pointer = gcvNULL;
++#endif
++
++ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d",
++ Kernel, ProcessID);
++
++ gcmkONERROR(
++ gckVIDMEM_HANDLE_LookupAndReference(Kernel,
++ Interface->u.LockVideoMemory.node,
++ &nodeObject));
++
++ node = nodeObject->node;
++
++ Interface->u.LockVideoMemory.gid = 0;
++
++ /* Lock video memory. */
++ gcmkONERROR(
++ gckVIDMEM_Lock(Kernel,
++ nodeObject,
++ Interface->u.LockVideoMemory.cacheable,
++ &Interface->u.LockVideoMemory.address,
++ &Interface->u.LockVideoMemory.gid,
++ &Interface->u.LockVideoMemory.physicalAddress));
++
++ locked = gcvTRUE;
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Map video memory address into user space. */
++#ifdef __QNXNTO__
++ if (node->VidMem.logical == gcvNULL)
++ {
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemory(Kernel,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ ProcessID,
++ node->VidMem.bytes,
++ &node->VidMem.logical));
++ }
++ gcmkASSERT(node->VidMem.logical != gcvNULL);
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->VidMem.logical);
++#else
++ gcmkONERROR(
++ gckKERNEL_MapVideoMemoryEx(Kernel,
++ Core,
++ FromUser,
++ Interface->u.LockVideoMemory.address,
++ &pointer));
++
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(pointer);
++#endif
++ }
++ else
++ {
++ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->Virtual.logical);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckVIDMEM_Node_Lock(
++ Kernel,
++ nodeObject,
++ &Interface->u.LockVideoMemory.address
++ ));
++#endif
++
++
++#if gcdSECURE_USER
++ /* Return logical address as physical address. */
++ Interface->u.LockVideoMemory.address =
++ (gctUINT32)(Interface->u.LockVideoMemory.memory);
++#endif
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ ProcessID, gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmINT2PTR(Interface->u.LockVideoMemory.node),
++ gcvNULL,
++ 0));
++
++ gckVIDMEM_HANDLE_Reference(
++ Kernel, ProcessID, (gctUINT32)Interface->u.LockVideoMemory.node);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (locked)
++ {
++ /* Roll back the lock. */
++ gcmkVERIFY_OK(gckVIDMEM_Unlock(Kernel,
++ nodeObject,
++ gcvSURF_TYPE_UNKNOWN,
++ &asynchronous));
++
++ if (gcvTRUE == asynchronous)
++ {
++ /* Bottom Half */
++ gcmkVERIFY_OK(gckVIDMEM_Unlock(Kernel,
++ nodeObject,
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++ }
++ }
++
++ if (nodeObject != gcvNULL)
++ {
++ gckVIDMEM_NODE_Dereference(Kernel, nodeObject);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_UnlockVideoMemory
++**
++** Unlock a video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID of current process.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_UnlockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject;
++ gcuVIDMEM_NODE_PTR node;
++
++ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d",
++ Kernel, ProcessID);
++
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(
++ Kernel,
++ ProcessID,
++ (gctUINT32)Interface->u.UnlockVideoMemory.node,
++ &nodeObject));
++
++ node = nodeObject->node;
++
++ /* Unlock video memory. */
++#if gcdSECURE_USER
++ /* Save node information before it disappears. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock video memory. */
++ gcmkONERROR(gckVIDMEM_Unlock(
++ Kernel,
++ nodeObject,
++ Interface->u.UnlockVideoMemory.type,
++ &Interface->u.UnlockVideoMemory.asynchroneous));
++
++#if gcdSECURE_USER
++ /* Flush the translation cache for virtual surfaces. */
++ if (logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(Kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gctINT i;
++ gcuDATABASE_INFO tmp;
++
++ gceDATABASE_TYPE type[3] = {
++ gcvDB_VIDEO_MEMORY | (gcvPOOL_SYSTEM << gcdDB_VIDEO_MEMORY_POOL_SHIFT),
++ gcvDB_VIDEO_MEMORY | (gcvPOOL_CONTIGUOUS << gcdDB_VIDEO_MEMORY_POOL_SHIFT),
++ gcvDB_VIDEO_MEMORY | (gcvPOOL_VIRTUAL << gcdDB_VIDEO_MEMORY_POOL_SHIFT),
++ };
++
++ gcmkHEADER();
++
++ /* Query video memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_VIDEO_MEMORY,
++ &Interface->u.Database.vidMem));
++
++ /* Query non-paged memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_NON_PAGED,
++ &Interface->u.Database.nonPaged));
++
++ /* Query contiguous memory. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_CONTIGUOUS,
++ &Interface->u.Database.contiguous));
++
++ /* Query GPU idle time. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_IDLE,
++ &Interface->u.Database.gpuIdle));
++ for (i = 0; i < 3; i++)
++ {
++ /* Query each video memory pool. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ type[i],
++ &Interface->u.Database.vidMemPool[i]));
++ }
++
++ /* Query virtual command buffer pool. */
++ gcmkONERROR(
++ gckKERNEL_QueryProcessDB(Kernel,
++ Interface->u.Database.processID,
++ !Interface->u.Database.validProcessID,
++ gcvDB_COMMAND_BUFFER,
++ &tmp));
++
++ Interface->u.Database.vidMemPool[2].counters.bytes += tmp.counters.bytes;
++ Interface->u.Database.vidMemPool[2].counters.maxBytes += tmp.counters.maxBytes;
++ Interface->u.Database.vidMemPool[2].counters.totalBytes += tmp.counters.totalBytes;
++
++ Interface->u.Database.vidMem.counters.bytes += tmp.counters.bytes;
++ Interface->u.Database.vidMem.counters.maxBytes += tmp.counters.maxBytes;
++ Interface->u.Database.vidMem.counters.totalBytes += tmp.counters.totalBytes;
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gckKERNEL_DumpVidMemUsage(Kernel, Interface->u.Database.processID);
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_ConfigPowerManagement(
++ IN gckKERNEL Kernel,
++ IN OUT gcsHAL_INTERFACE * Interface
++)
++{
++ gceSTATUS status;
++ gctBOOL enable = Interface->u.ConfigPowerManagement.enable;
++
++ gcmkHEADER();
++
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(Kernel->hardware, enable));
++
++ if (enable == gcvTRUE)
++ {
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Kernel->hardware, gcvPOWER_ON));
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL FromUser
++** whether the call is from the user space.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctSIZE_T bytes;
++ gctPOINTER logical = gcvNULL;
++ gctPOINTER info = gcvNULL;
++#if (gcdENABLE_3D || gcdENABLE_2D)
++ gckCONTEXT context = gcvNULL;
++#endif
++ gckKERNEL kernel = Kernel;
++ gctUINT32 address;
++ gctUINT32 processID;
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++ gctPOINTER logical;
++#endif
++ gctUINT32 paddr = gcvINVALID_ADDRESS;
++#if !USE_NEW_LINUX_SIGNAL
++ gctSIGNAL signal;
++#endif
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++
++ gckVIDMEM_NODE nodeObject;
++ gctBOOL powerMutexAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x FromUser=%d Interface=0x%x",
++ Kernel, FromUser, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "Dispatching command %d (%s)",
++ Interface->command, _DispatchText[Interface->command]);
++#endif
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gckOS_AcquireMutex(Kernel->os, Kernel->debugMutex, gcvINFINITE);
++#endif
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Kernel, processID, &cache));
++#endif
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkONERROR(
++ gckOS_GetBaseAddress(Kernel->os,
++ &Interface->u.GetBaseAddress.baseAddress));
++ break;
++
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkONERROR(gckKERNEL_QueryVideoMemory(Kernel, Interface));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkONERROR(
++ gckHARDWARE_QueryChipIdentity(
++ Kernel->hardware,
++ &Interface->u.QueryChipIdentity));
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.MapMemory.physical);
++
++ /* Map memory. */
++ gcmkONERROR(
++ gckKERNEL_MapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes,
++ &logical));
++
++ Interface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ logical,
++ physical,
++ (gctSIZE_T) Interface->u.MapMemory.bytes));
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ physical = gcmINT2PTR(Interface->u.UnmapMemory.physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_MEMORY,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++
++ /* Unmap memory. */
++ gcmkONERROR(
++ gckKERNEL_UnmapMemory(Kernel,
++ physical,
++ (gctSIZE_T) Interface->u.UnmapMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical)));
++ break;
++
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateNonPagedMemory.bytes;
++
++ /* Allocate non-paged memory. */
++ gcmkONERROR(
++ gckOS_AllocateNonPagedMemory(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateNonPagedMemory.bytes = bytes;
++ Interface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateNonPagedMemory.physical),
++ bytes));
++ break;
++
++ case gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER:
++ bytes = (gctSIZE_T) Interface->u.AllocateVirtualCommandBuffer.bytes;
++
++ gcmkONERROR(
++ gckKERNEL_AllocateVirtualCommandBuffer(
++ Kernel,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateVirtualCommandBuffer.bytes = bytes;
++ Interface->u.AllocateVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateVirtualCommandBuffer.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_COMMAND_BUFFER,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateVirtualCommandBuffer.physical),
++ bytes));
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Free non-paged memory. */
++ gcmkONERROR(
++ gckOS_FreeNonPagedMemory(Kernel->os,
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical),
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes));
++#endif
++
++ gcmRELEASE_NAME(Interface->u.FreeNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) Interface->u.AllocateContiguousMemory.bytes;
++
++ /* Allocate contiguous memory. */
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Kernel->os,
++ FromUser,
++ &bytes,
++ &physical,
++ &logical));
++
++ Interface->u.AllocateContiguousMemory.bytes = bytes;
++ Interface->u.AllocateContiguousMemory.logical = gcmPTR_TO_UINT64(logical);
++ Interface->u.AllocateContiguousMemory.physical = gcmPTR_TO_NAME(physical);
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ logical,
++ gcvTRUE,
++ &Interface->u.AllocateContiguousMemory.address));
++
++ gcmkVERIFY_OK(gckKERNEL_AddProcessDB(
++ Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ logical,
++ gcmINT2PTR(Interface->u.AllocateContiguousMemory.physical),
++ bytes));
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++
++ /* Free contiguous memory. */
++ gcmkONERROR(
++ gckOS_FreeContiguous(Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes));
++#endif
++
++ gcmRELEASE_NAME(Interface->u.FreeContiguousMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ /* Allocate memory. */
++ gcmkONERROR(
++ gckKERNEL_AllocateLinearMemory(Kernel, processID,
++ &Interface->u.AllocateLinearVideoMemory.pool,
++ Interface->u.AllocateLinearVideoMemory.bytes,
++ Interface->u.AllocateLinearVideoMemory.alignment,
++ Interface->u.AllocateLinearVideoMemory.type,
++ Interface->u.AllocateLinearVideoMemory.flag,
++ &Interface->u.AllocateLinearVideoMemory.node));
++ break;
++
++ case gcvHAL_RELEASE_VIDEO_MEMORY:
++ /* Release video memory. */
++ gcmkONERROR(gckKERNEL_ReleaseVideoMemory(
++ Kernel, processID,
++ (gctUINT32)Interface->u.ReleaseVideoMemory.node
++ ));
++ break;
++
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ /* Lock video memory. */
++ gcmkONERROR(gckKERNEL_LockVideoMemory(Kernel, Kernel->core, processID, FromUser, Interface));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ /* Unlock video memory. */
++ gcmkONERROR(gckKERNEL_UnlockVideoMemory(Kernel, processID, Interface));
++ break;
++
++ case gcvHAL_EVENT_COMMIT:
++ /* Commit an event queue. */
++#if gcdMULTI_GPU
++ if (Interface->u.Event.gpuMode == gcvMULTI_GPU_MODE_INDEPENDENT)
++ {
++ gcmkONERROR(
++ gckEVENT_Commit(Kernel->eventObj,
++ gcmUINT64_TO_PTR(Interface->u.Event.queue),
++ Interface->u.Event.chipEnable));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckEVENT_Commit(Kernel->eventObj,
++ gcmUINT64_TO_PTR(Interface->u.Event.queue),
++ gcvCORE_3D_ALL_MASK));
++ }
++#else
++ gcmkONERROR(
++ gckEVENT_Commit(Kernel->eventObj,
++ gcmUINT64_TO_PTR(Interface->u.Event.queue)));
++#endif
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++#if gcdMULTI_GPU
++ if (Interface->u.Commit.gpuMode == gcvMULTI_GPU_MODE_INDEPENDENT)
++ {
++ gcmkONERROR(
++ gckCOMMAND_Commit(Kernel->command,
++ Interface->u.Commit.context ?
++ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL,
++ gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer),
++ gcmUINT64_TO_PTR(Interface->u.Commit.delta),
++ gcmUINT64_TO_PTR(Interface->u.Commit.queue),
++ processID,
++ Interface->u.Commit.chipEnable));
++ }
++ else
++ {
++ gcmkONERROR(
++ gckCOMMAND_Commit(Kernel->command,
++ Interface->u.Commit.context ?
++ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL,
++ gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer),
++ gcmUINT64_TO_PTR(Interface->u.Commit.delta),
++ gcmUINT64_TO_PTR(Interface->u.Commit.queue),
++ processID,
++ gcvCORE_3D_ALL_MASK));
++ }
++#else
++ gcmkONERROR(
++ gckCOMMAND_Commit(Kernel->command,
++ Interface->u.Commit.context ?
++ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL,
++ gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer),
++ gcmUINT64_TO_PTR(Interface->u.Commit.delta),
++ gcmUINT64_TO_PTR(Interface->u.Commit.queue),
++ processID));
++#endif
++
++ break;
++
++ case gcvHAL_STALL:
++ /* Stall the command queue. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckCOMMAND_Stall(Kernel->command, gcvFALSE, gcvCORE_3D_ALL_MASK));
++#else
++ gcmkONERROR(gckCOMMAND_Stall(Kernel->command, gcvFALSE));
++#endif
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkONERROR(
++ gckOS_MapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ Interface->u.MapUserMemory.physical,
++ (gctSIZE_T) Interface->u.MapUserMemory.size,
++ &info,
++ &Interface->u.MapUserMemory.address));
++
++ Interface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.MapUserMemory.info),
++ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory),
++ (gctSIZE_T) Interface->u.MapUserMemory.size));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ address = Interface->u.UnmapUserMemory.address;
++ info = gcmNAME_TO_PTR(Interface->u.UnmapUserMemory.info);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Interface->u.UnmapUserMemory.info)));
++ /* Unmap user memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) Interface->u.UnmapUserMemory.size,
++ info,
++ address));
++
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Kernel,
++ cache,
++ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) Interface->u.UnmapUserMemory.size));
++#endif
++
++ gcmRELEASE_NAME(Interface->u.UnmapUserMemory.info);
++ break;
++
++#if !USE_NEW_LINUX_SIGNAL
++ case gcvHAL_USER_SIGNAL:
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkONERROR(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkONERROR(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++
++ break;
++
++ case gcvUSER_SIGNAL_MAP:
++ gcmkONERROR(
++ gckOS_MapSignal(Kernel->os,
++ (gctSIGNAL)(gctUINTPTR_T)Interface->u.UserSignal.id,
++ (gctHANDLE)(gctUINTPTR_T)processID,
++ &signal));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_UNMAP:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++
++ /* Destroy the signal. */
++ gcmkONERROR(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ break;
++#endif
++
++ case gcvHAL_SET_POWER_MANAGEMENT_STATE:
++ /* Set the power management state. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(
++ Kernel->hardware,
++ Interface->u.SetPowerManagement.state));
++ break;
++
++ case gcvHAL_QUERY_POWER_MANAGEMENT_STATE:
++ /* Chip is not idle. */
++ Interface->u.QueryPowerManagement.isIdle = gcvFALSE;
++
++ /* Query the power management state. */
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(
++ Kernel->hardware,
++ &Interface->u.QueryPowerManagement.state));
++
++ /* Query the idle state. */
++ gcmkONERROR(
++ gckHARDWARE_QueryIdle(Kernel->hardware,
++ &Interface->u.QueryPowerManagement.isIdle));
++ break;
++
++ case gcvHAL_READ_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE));
++ powerMutexAcquired = gcvTRUE;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Read a register. */
++ gcmkONERROR(gckOS_ReadRegisterEx(
++ Kernel->os,
++ Kernel->core,
++ Interface->u.ReadRegisterData.address,
++ &Interface->u.ReadRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ powerMutexAcquired = gcvFALSE;
++ }
++#else
++ /* No access from user land to read registers. */
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++#if gcdMULTI_GPU
++ case gcvHAL_READ_REGISTER_EX:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++ gctUINT32 coreId = 0;
++ gctUINT32 coreSelect = Interface->u.ReadRegisterDataEx.coreSelect;
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE));
++ powerMutexAcquired = gcvTRUE;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ for (; coreSelect != 0; coreSelect >>= 1, coreId++)
++ {
++ if (coreSelect & 1UL)
++ {
++ /* Read a register. */
++ gcmkONERROR(
++ gckOS_ReadRegisterByCoreId(
++ Kernel->os,
++ Kernel->core,
++ coreId,
++ Interface->u.ReadRegisterDataEx.address,
++ &Interface->u.ReadRegisterDataEx.data[coreId]));
++ }
++ }
++ }
++ else
++ {
++ for (coreId = 0; coreId < gcdMULTI_GPU; coreId++)
++ {
++ /* Chip is in power-state. */
++ Interface->u.ReadRegisterDataEx.data[coreId] = 0;
++ }
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ powerMutexAcquired = gcvFALSE;
++ }
++#else
++ gctUINT32 coreId;
++
++ /* No access from user land to read registers. */
++ for (coreId = 0; coreId < gcdMULTI_GPU; coreId++)
++ {
++ Interface->u.ReadRegisterDataEx.data[coreId] = 0;
++ }
++
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_WRITE_REGISTER_EX:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++ gctUINT32 coreId = 0;
++ gctUINT32 coreSelect = Interface->u.WriteRegisterDataEx.coreSelect;
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE));
++ powerMutexAcquired = gcvTRUE;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ for (; coreSelect != 0; coreSelect >>= 1, coreId++)
++ {
++ if (coreSelect & 1UL)
++ {
++ /* Write a register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterByCoreId(
++ Kernel->os,
++ Kernel->core,
++ coreId,
++ Interface->u.WriteRegisterDataEx.address,
++ Interface->u.WriteRegisterDataEx.data[coreId]));
++ }
++ }
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ for (coreId = 0; coreId < gcdMULTI_GPU; coreId++)
++ {
++ Interface->u.WriteRegisterDataEx.data[coreId] = 0;
++ }
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ powerMutexAcquired = gcvFALSE;
++ }
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++#endif
++
++ case gcvHAL_WRITE_REGISTER:
++#if gcdREGISTER_ACCESS_FROM_USER
++ {
++ gceCHIPPOWERSTATE power;
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE));
++ powerMutexAcquired = gcvTRUE;
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware,
++ &power));
++ if (power == gcvPOWER_ON)
++ {
++ /* Write a register. */
++ gcmkONERROR(
++ gckOS_WriteRegisterEx(Kernel->os,
++ Kernel->core,
++ Interface->u.WriteRegisterData.address,
++ Interface->u.WriteRegisterData.data));
++ }
++ else
++ {
++ /* Chip is in power-state. */
++ Interface->u.WriteRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++ }
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ powerMutexAcquired = gcvFALSE;
++ }
++#else
++ /* No access from user land to write registers. */
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_READ_ALL_PROFILE_REGISTERS:
++#if VIVANTE_PROFILER && VIVANTE_PROFILER_CONTEXT
++ /* Read profile data according to the context. */
++ gcmkONERROR(
++ gckHARDWARE_QueryContextProfile(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ gcmNAME_TO_PTR(Interface->u.RegisterProfileData.context),
++ &Interface->u.RegisterProfileData.counters));
++#elif VIVANTE_PROFILER
++ /* Read all 3D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_QueryProfileRegisters(
++ Kernel->hardware,
++ Kernel->profileCleanRegister,
++ &Interface->u.RegisterProfileData.counters));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_PROFILE_REGISTERS_2D:
++#if VIVANTE_PROFILER
++ /* Read all 2D profile registers. */
++ gcmkONERROR(
++ gckHARDWARE_ProfileEngine2D(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.RegisterProfileData2D.hwProfile2D)));
++#else
++ status = gcvSTATUS_OK;
++#endif
++ break;
++
++ case gcvHAL_GET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Get profile setting */
++ Interface->u.GetProfileSetting.enable = Kernel->profileEnable;
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_SET_PROFILE_SETTING:
++#if VIVANTE_PROFILER
++ /* Set profile setting */
++ if(Kernel->hardware->gpuProfiler)
++ {
++ Kernel->profileEnable = Interface->u.SetProfileSetting.enable;
++#if VIVANTE_PROFILER_NEW
++ if (Kernel->profileEnable)
++ gckHARDWARE_InitProfiler(Kernel->hardware);
++#endif
++ }
++ else
++ {
++ status = gcvSTATUS_NOT_SUPPORTED;
++ break;
++ }
++#endif
++
++ status = gcvSTATUS_OK;
++ break;
++
++#if VIVANTE_PROFILER_PERDRAW
++ case gcvHAL_READ_PROFILER_REGISTER_SETTING:
++ #if VIVANTE_PROFILER
++ Kernel->profileCleanRegister = Interface->u.SetProfilerRegisterClear.bclear;
++ #endif
++ status = gcvSTATUS_OK;
++ break;
++#endif
++
++ case gcvHAL_QUERY_KERNEL_SETTINGS:
++ /* Get kernel settings. */
++ gcmkONERROR(
++ gckKERNEL_QuerySettings(Kernel,
++ &Interface->u.QueryKernelSettings.settings));
++ break;
++
++ case gcvHAL_RESET:
++ /* Reset the hardware. */
++ gcmkONERROR(
++ gckHARDWARE_Reset(Kernel->hardware));
++ break;
++
++ case gcvHAL_DEBUG:
++ /* Set debug level and zones. */
++ if (Interface->u.Debug.set)
++ {
++ gckOS_SetDebugLevel(Interface->u.Debug.level);
++ gckOS_SetDebugZones(Interface->u.Debug.zones,
++ Interface->u.Debug.enable);
++ }
++
++ if (Interface->u.Debug.message[0] != '\0')
++ {
++ /* Print a message to the debugger. */
++ if (Interface->u.Debug.type == gcvMESSAGE_TEXT)
++ {
++ gckOS_CopyPrint(Interface->u.Debug.message);
++ }
++ else
++ {
++ gckOS_DumpBuffer(Kernel->os,
++ Interface->u.Debug.message,
++ Interface->u.Debug.messageSize,
++ gceDUMP_BUFFER_FROM_USER,
++ gcvTRUE);
++ }
++ }
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_DUMP_GPU_STATE:
++ {
++ gceCHIPPOWERSTATE power;
++
++ _DumpDriverConfigure(Kernel);
++
++ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(
++ Kernel->hardware,
++ &power
++ ));
++
++ if (power == gcvPOWER_ON)
++ {
++ Interface->u.ReadRegisterData.data = 1;
++
++ _DumpState(Kernel);
++ }
++ else
++ {
++ Interface->u.ReadRegisterData.data = 0;
++ status = gcvSTATUS_CHIP_NOT_READY;
++
++ gcmkPRINT("[galcore]: Can't dump state if GPU isn't POWER ON.");
++ }
++ }
++ break;
++
++ case gcvHAL_DUMP_EVENT:
++ break;
++
++ case gcvHAL_CACHE:
++
++ logical = gcmUINT64_TO_PTR(Interface->u.Cache.logical);
++
++ if (Interface->u.Cache.node)
++ {
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(
++ Kernel,
++ processID,
++ Interface->u.Cache.node,
++ &nodeObject));
++
++ if (nodeObject->node->VidMem.memory->object.type == gcvOBJ_VIDMEM
++ || nodeObject->node->Virtual.contiguous
++ )
++ {
++ /* If memory is contiguous, get physical address. */
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Kernel->os, logical, (gctUINT32*)&paddr));
++ }
++ }
++
++ bytes = (gctSIZE_T) Interface->u.Cache.bytes;
++ switch(Interface->u.Cache.operation)
++ {
++ case gcvCACHE_FLUSH:
++ /* Clean and invalidate the cache. */
++ status = gckOS_CacheFlush(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_CLEAN:
++ /* Clean the cache. */
++ status = gckOS_CacheClean(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++ case gcvCACHE_INVALIDATE:
++ /* Invalidate the cache. */
++ status = gckOS_CacheInvalidate(Kernel->os,
++ processID,
++ physical,
++ paddr,
++ logical,
++ bytes);
++ break;
++
++ case gcvCACHE_MEMORY_BARRIER:
++ status = gckOS_MemoryBarrier(Kernel->os,
++ logical);
++ break;
++ default:
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ /* Check for invalid timer. */
++ if ((Interface->u.TimeStamp.timer >= gcmCOUNTOF(Kernel->timers))
++ || (Interface->u.TimeStamp.request != 2))
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Return timer results and reset timer. */
++ {
++ gcsTIMER_PTR timer = &(Kernel->timers[Interface->u.TimeStamp.timer]);
++ gctUINT64 timeDelta = 0;
++
++ if (timer->stopTime < timer->startTime )
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ timeDelta = timer->stopTime - timer->startTime;
++
++ /* Check truncation overflow. */
++ Interface->u.TimeStamp.timeDelta = (gctINT32) timeDelta;
++ /*bit0~bit30 is available*/
++ if (timeDelta>>31)
++ {
++ Interface->u.TimeStamp.timeDelta = 0;
++ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW);
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ break;
++
++ case gcvHAL_DATABASE:
++ gcmkONERROR(gckKERNEL_QueryDatabase(Kernel, processID, Interface));
++ break;
++
++ case gcvHAL_VERSION:
++ Interface->u.Version.major = gcvVERSION_MAJOR;
++ Interface->u.Version.minor = gcvVERSION_MINOR;
++ Interface->u.Version.patch = gcvVERSION_PATCH;
++ Interface->u.Version.build = gcvVERSION_BUILD;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "KERNEL version %d.%d.%d build %u %s %s",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH,
++ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME);
++#endif
++ break;
++
++ case gcvHAL_CHIP_INFO:
++ /* Only if not support multi-core */
++ Interface->u.ChipInfo.count = 1;
++ Interface->u.ChipInfo.types[0] = Kernel->hardware->type;
++ break;
++
++#if (gcdENABLE_3D || gcdENABLE_2D)
++ case gcvHAL_ATTACH:
++ /* Attach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Attach(Kernel->command,
++ &context,
++ &bytes,
++ processID));
++
++ Interface->u.Attach.stateCount = bytes;
++ Interface->u.Attach.context = gcmPTR_TO_NAME(context);
++
++ if (Interface->u.Attach.map == gcvTRUE)
++ {
++ gcmkVERIFY_OK(
++ gckCONTEXT_MapBuffer(context,
++ Interface->u.Attach.physicals,
++ Interface->u.Attach.logicals,
++ &Interface->u.Attach.bytes));
++ }
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Attach.context),
++ gcvNULL,
++ 0));
++ break;
++#endif
++
++ case gcvHAL_DETACH:
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_CONTEXT,
++ gcmINT2PTR(Interface->u.Detach.context)));
++
++ /* Detach user process. */
++ gcmkONERROR(
++ gckCOMMAND_Detach(Kernel->command,
++ gcmNAME_TO_PTR(Interface->u.Detach.context)));
++
++ gcmRELEASE_NAME(Interface->u.Detach.context);
++ break;
++
++ case gcvHAL_COMPOSE:
++ Interface->u.Compose.physical = gcmPTR_TO_UINT64(gcmNAME_TO_PTR(Interface->u.Compose.physical));
++ /* Start composition. */
++ gcmkONERROR(
++ gckEVENT_Compose(Kernel->eventObj,
++ &Interface->u.Compose));
++ break;
++
++ case gcvHAL_SET_TIMEOUT:
++ /* set timeOut value from user */
++ gckKERNEL_SetTimeOut(Kernel, Interface->u.SetTimeOut.timeOut);
++ break;
++
++ case gcvHAL_GET_FRAME_INFO:
++ gcmkONERROR(gckHARDWARE_GetFrameInfo(
++ Kernel->hardware,
++ gcmUINT64_TO_PTR(Interface->u.GetFrameInfo.frameInfo)));
++ break;
++
++ case gcvHAL_SET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_SetFscaleValue(Kernel->hardware,
++ Interface->u.SetFscaleValue.value);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++ case gcvHAL_GET_FSCALE_VALUE:
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ status = gckHARDWARE_GetFscaleValue(Kernel->hardware,
++ &Interface->u.GetFscaleValue.value,
++ &Interface->u.GetFscaleValue.minValue,
++ &Interface->u.GetFscaleValue.maxValue);
++#else
++ status = gcvSTATUS_NOT_SUPPORTED;
++#endif
++ break;
++
++ case gcvHAL_NAME_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Name(Kernel,
++ Interface->u.NameVideoMemory.handle,
++ &Interface->u.NameVideoMemory.name));
++ break;
++
++ case gcvHAL_IMPORT_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Import(Kernel,
++ Interface->u.ImportVideoMemory.name,
++ &Interface->u.ImportVideoMemory.handle));
++
++ gcmkONERROR(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ gcmINT2PTR(Interface->u.ImportVideoMemory.handle),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_GET_VIDEO_MEMORY_FD:
++ gcmkONERROR(gckVIDMEM_NODE_GetFd(
++ Kernel,
++ Interface->u.GetVideoMemoryFd.handle,
++ &Interface->u.GetVideoMemoryFd.fd
++ ));
++
++ /* No need to add it to processDB because OS will release all fds when
++ ** process quits.
++ */
++ break;
++
++ case gcvHAL_QUERY_RESET_TIME_STAMP:
++ Interface->u.QueryResetTimeStamp.timeStamp = Kernel->resetTimeStamp;
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)gcmNAME_TO_PTR(Interface->u.FreeVirtualCommandBuffer.physical);
++
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID,
++ gcvDB_COMMAND_BUFFER,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++
++ gcmkONERROR(gckOS_DestroyUserVirtualMapping(
++ Kernel->os,
++ buffer->physical,
++ (gctSIZE_T)Interface->u.FreeVirtualCommandBuffer.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++
++ gcmkONERROR(gckKERNEL_DestroyVirtualCommandBuffer(
++ Kernel,
++ (gctSIZE_T)Interface->u.FreeVirtualCommandBuffer.bytes,
++ (gctPHYS_ADDR)buffer,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++
++ gcmRELEASE_NAME(Interface->u.FreeVirtualCommandBuffer.physical);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ switch (Interface->u.SyncPoint.command)
++ {
++ case gcvSYNC_POINT_CREATE:
++ gcmkONERROR(gckOS_CreateSyncPoint(Kernel->os, &syncPoint));
++
++ Interface->u.SyncPoint.syncPoint = gcmPTR_TO_UINT64(syncPoint);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSYNC_POINT_DESTROY:
++ syncPoint = gcmUINT64_TO_PTR(Interface->u.SyncPoint.syncPoint);
++
++ gcmkONERROR(gckOS_DestroySyncPoint(Kernel->os, syncPoint));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID, gcvDB_SYNC_POINT,
++ syncPoint));
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++
++ case gcvHAL_CREATE_NATIVE_FENCE:
++ {
++ gctINT fenceFD;
++ gctSYNC_POINT syncPoint =
++ gcmUINT64_TO_PTR(Interface->u.CreateNativeFence.syncPoint);
++
++ gcmkONERROR(
++ gckOS_CreateNativeFence(Kernel->os,
++ Kernel->timeline,
++ syncPoint,
++ &fenceFD));
++
++ Interface->u.CreateNativeFence.fenceFD = fenceFD;
++ }
++ break;
++#endif
++
++ case gcvHAL_SHBUF:
++ {
++ gctSHBUF shBuf;
++ gctPOINTER uData;
++ gctUINT32 bytes;
++
++ switch (Interface->u.ShBuf.command)
++ {
++ case gcvSHBUF_CREATE:
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Create. */
++ gcmkONERROR(gckKERNEL_CreateShBuffer(Kernel, bytes, &shBuf));
++
++ Interface->u.ShBuf.id = gcmPTR_TO_UINT64(shBuf);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_DESTROY:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Check db first to avoid illegal destroy in the process. */
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf));
++
++ gcmkONERROR(gckKERNEL_DestroyShBuffer(Kernel, shBuf));
++ break;
++
++ case gcvSHBUF_MAP:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Map for current process access. */
++ gcmkONERROR(gckKERNEL_MapShBuffer(Kernel, shBuf));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_WRITE:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Write. */
++ gcmkONERROR(
++ gckKERNEL_WriteShBuffer(Kernel, shBuf, uData, bytes));
++ break;
++
++ case gcvSHBUF_READ:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Read. */
++ gcmkONERROR(
++ gckKERNEL_ReadShBuffer(Kernel,
++ shBuf,
++ uData,
++ bytes,
++ &bytes));
++
++ /* Return copied size. */
++ Interface->u.ShBuf.bytes = bytes;
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++
++ case gcvHAL_CONFIG_POWER_MANAGEMENT:
++ gcmkONERROR(gckKERNEL_ConfigPowerManagement(Kernel, Interface));
++ break;
++
++ default:
++ /* Invalid command. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++OnError:
++ /* Save status. */
++ Interface->status = status;
++
++#if QNX_SINGLE_THREADED_DEBUGGING
++ gckOS_ReleaseMutex(Kernel->os, Kernel->debugMutex);
++#endif
++
++ if (powerMutexAcquired == gcvTRUE)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcess
++**
++** Attach or detach a process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d", Kernel, Attach);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_AttachProcessEx(Kernel, Attach, processID));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AttachProcessEx
++**
++** Attach or detach a process with the given PID. Can be paired with gckKERNEL_AttachProcess
++** provided the programmer is aware of the consequences.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL Attach
++** gcvTRUE if a new process gets attached or gcFALSE when a process
++** gets detatched.
++**
++** gctUINT32 PID
++** PID of the process to attach or detach.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ )
++{
++ gceSTATUS status;
++ gctINT32 old;
++
++ gcmkHEADER_ARG("Kernel=0x%x Attach=%d PID=%d", Kernel, Attach, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (Attach)
++ {
++ /* Increment the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomIncrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 0)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_FIRST_PROCESS));
++ }
++ }
++
++ if (Kernel->dbCreated)
++ {
++ /* Create the process database. */
++ gcmkONERROR(gckKERNEL_CreateProcessDB(Kernel, PID));
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Map kernel command buffer in the process's own MMU. */
++ gcmkONERROR(_MapCommandBuffer(Kernel));
++#endif
++ }
++ else
++ {
++ if (Kernel->dbCreated)
++ {
++ /* Clean up the process database. */
++ gcmkONERROR(gckKERNEL_DestroyProcessDB(Kernel, PID));
++
++ /* Save the last know process ID. */
++ Kernel->db->lastProcessID = PID;
++ }
++
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++#if gcdMULTI_GPU
++ status = gckEVENT_Submit(Kernel->eventObj, gcvTRUE, gcvFALSE, gcvCORE_3D_ALL_MASK);
++#else
++ status = gckEVENT_Submit(Kernel->eventObj, gcvTRUE, gcvFALSE);
++#endif
++
++ if (status == gcvSTATUS_INTERRUPTED && Kernel->eventObj->submitTimer)
++ {
++ gcmkONERROR(gckOS_StartTimer(Kernel->os,
++ Kernel->eventObj->submitTimer,
++ 1));
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++ }
++
++ /* Decrement the number of clients attached. */
++ gcmkONERROR(
++ gckOS_AtomDecrement(Kernel->os, Kernel->atomClients, &old));
++
++ if (old == 1)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ /* Last client detached, switch to SUSPEND power state. */
++ gcmkONERROR(gckOS_Broadcast(Kernel->os,
++ Kernel->hardware,
++ gcvBROADCAST_LAST_PROCESS));
++ }
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++ }
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++gceSTATUS
++gckKERNEL_MapLogicalToPhysical(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN OUT gctPOINTER * Data
++ )
++{
++ gceSTATUS status;
++ static gctBOOL baseAddressValid = gcvFALSE;
++ static gctUINT32 baseAddress;
++ gctBOOL needBase;
++ gcskLOGICAL_CACHE_PTR slot;
++
++ gcmkHEADER_ARG("Kernel=0x%x Cache=0x%x *Data=0x%x",
++ Kernel, Cache, gcmOPT_POINTER(Data));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (!baseAddressValid)
++ {
++ /* Get base address. */
++ gcmkONERROR(gckHARDWARE_GetBaseAddress(Kernel->hardware, &baseAddress));
++
++ baseAddressValid = gcvTRUE;
++ }
++
++ /* Does this state load need a base address? */
++ gcmkONERROR(gckHARDWARE_NeedBaseAddress(Kernel->hardware,
++ ((gctUINT32_PTR) Data)[-1],
++ &needBase));
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LRU
++ {
++ gcskLOGICAL_CACHE_PTR next;
++ gctINT i;
++
++ /* Walk all used cache slots. */
++ for (i = 1, slot = Cache->cache[0].next, next = gcvNULL;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->next
++ )
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++ }
++
++ /* See if we had a miss. */
++ if (next == gcvNULL)
++ {
++ /* Use the tail of the cache. */
++ slot = Cache->cache[0].prev;
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++
++ /* Move slot to head of list. */
++ if (slot != Cache->cache[0].next)
++ {
++ /* Unlink. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Move to head of chain. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ {
++ gctINT i;
++ gcskLOGICAL_CACHE_PTR next = gcvNULL;
++ gcskLOGICAL_CACHE_PTR oldestSlot = gcvNULL;
++ slot = gcvNULL;
++
++ if (Cache->cacheIndex != gcvNULL)
++ {
++ /* Walk the cache forwards. */
++ for (i = 1, slot = Cache->cacheIndex;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->next)
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++
++ /* Determine age of this slot. */
++ if ((oldestSlot == gcvNULL)
++ || (oldestSlot->stamp > slot->stamp)
++ )
++ {
++ oldestSlot = slot;
++ }
++ }
++
++ if (next == gcvNULL)
++ {
++ /* Walk the cache backwards. */
++ for (slot = Cache->cacheIndex->prev;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = slot->prev)
++ {
++ if (slot->logical == *Data)
++ {
++ /* Bail out. */
++ next = slot;
++ break;
++ }
++
++ /* Determine age of this slot. */
++ if ((oldestSlot == gcvNULL)
++ || (oldestSlot->stamp > slot->stamp)
++ )
++ {
++ oldestSlot = slot;
++ }
++ }
++ }
++ }
++
++ /* See if we had a miss. */
++ if (next == gcvNULL)
++ {
++ if (Cache->cacheFree != 0)
++ {
++ slot = &Cache->cache[Cache->cacheFree];
++ gcmkASSERT(slot->logical == gcvNULL);
++
++ ++ Cache->cacheFree;
++ if (Cache->cacheFree >= gcmCOUNTOF(Cache->cache))
++ {
++ Cache->cacheFree = 0;
++ }
++ }
++ else
++ {
++ /* Use the oldest cache slot. */
++ gcmkASSERT(oldestSlot != gcvNULL);
++ slot = oldestSlot;
++
++ /* Unlink from the chain. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append to the end. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++
++ /* Save time stamp. */
++ slot->stamp = ++ Cache->cacheStamp;
++
++ /* Save current slot for next lookup. */
++ Cache->cacheIndex = slot;
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ {
++ gctINT i;
++ gctUINT32 data = gcmPTR2INT32(*Data);
++ gctUINT32 key, index;
++ gcskLOGICAL_CACHE_PTR hash;
++
++ /* Generate a hash key. */
++ key = (data >> 24) + (data >> 16) + (data >> 8) + data;
++ index = key % gcmCOUNTOF(Cache->hash);
++
++ /* Get the hash entry. */
++ hash = &Cache->hash[index];
++
++ for (slot = hash->nextHash, i = 0;
++ (slot != gcvNULL) && (i < gcdSECURE_CACHE_SLOTS);
++ slot = slot->nextHash, ++i
++ )
++ {
++ if (slot->logical == (*Data))
++ {
++ break;
++ }
++ }
++
++ if (slot == gcvNULL)
++ {
++ /* Grab from the tail of the cache. */
++ slot = Cache->cache[0].prev;
++
++ /* Unlink slot from any hash table it is part of. */
++ if (slot->prevHash != gcvNULL)
++ {
++ slot->prevHash->nextHash = slot->nextHash;
++ }
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot->prevHash;
++ }
++
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++
++ if (hash->nextHash != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "Hash Collision: logical=0x%x key=0x%08x",
++ *Data, key);
++ }
++
++ /* Insert the slot at the head of the hash list. */
++ slot->nextHash = hash->nextHash;
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot;
++ }
++ slot->prevHash = hash;
++ hash->nextHash = slot;
++ }
++
++ /* Move slot to head of list. */
++ if (slot != Cache->cache[0].next)
++ {
++ /* Unlink. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Move to head of chain. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++ }
++ }
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_TABLE
++ {
++ gctUINT32 index = (gcmPTR2INT32(*Data) % gcdSECURE_CACHE_SLOTS) + 1;
++
++ /* Get cache slot. */
++ slot = &Cache->cache[index];
++
++ /* Check for cache miss. */
++ if (slot->logical != *Data)
++ {
++ /* Initialize the cache line. */
++ slot->logical = *Data;
++
++ /* Map the logical address to a DMA address. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddress(Kernel->os, *Data, &slot->dma));
++ }
++ }
++#endif
++
++ /* Return DMA address. */
++ *Data = gcmINT2PTR(slot->dma + (needBase ? baseAddress : 0));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FlushTranslationCache(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gctINT i;
++ gcskLOGICAL_CACHE_PTR slot;
++ gctUINT8_PTR ptr;
++
++ gcmkHEADER_ARG("Kernel=0x%x Cache=0x%x Logical=0x%x Bytes=%lu",
++ Kernel, Cache, Logical, Bytes);
++
++ /* Do we need to flush the entire cache? */
++ if (Logical == gcvNULL)
++ {
++ /* Clear all cache slots. */
++ for (i = 1; i <= gcdSECURE_CACHE_SLOTS; ++i)
++ {
++ Cache->cache[i].logical = gcvNULL;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ Cache->cache[i].nextHash = gcvNULL;
++ Cache->cache[i].prevHash = gcvNULL;
++#endif
++}
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Zero the hash table. */
++ for (i = 0; i < gcmCOUNTOF(Cache->hash); ++i)
++ {
++ Cache->hash[i].nextHash = gcvNULL;
++ }
++#endif
++
++ /* Reset the cache functionality. */
++ Cache->cacheIndex = gcvNULL;
++ Cache->cacheFree = 1;
++ Cache->cacheStamp = 0;
++ }
++
++ else
++ {
++ gctUINT8_PTR low = (gctUINT8_PTR) Logical;
++ gctUINT8_PTR high = low + Bytes;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LRU
++ gcskLOGICAL_CACHE_PTR next;
++
++ /* Walk all used cache slots. */
++ for (i = 1, slot = Cache->cache[0].next;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = next
++ )
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Unlink slot. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append slot to tail of cache. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ gcskLOGICAL_CACHE_PTR next;
++
++ for (i = 1, slot = Cache->cache[0].next;
++ (i <= gcdSECURE_CACHE_SLOTS) && (slot->logical != gcvNULL);
++ ++i, slot = next)
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Test if this slot is the current slot. */
++ if (slot == Cache->cacheIndex)
++ {
++ /* Move to next or previous slot. */
++ Cache->cacheIndex = (slot->next->logical != gcvNULL)
++ ? slot->next
++ : (slot->prev->logical != gcvNULL)
++ ? slot->prev
++ : gcvNULL;
++ }
++
++ /* Unlink slot from cache. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Insert slot to head of cache. */
++ slot->prev = &Cache->cache[0];
++ slot->next = Cache->cache[0].next;
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ slot->stamp = 0;
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ gctINT j;
++ gcskLOGICAL_CACHE_PTR hash, next;
++
++ /* Walk all hash tables. */
++ for (i = 0, hash = Cache->hash;
++ i < gcmCOUNTOF(Cache->hash);
++ ++i, ++hash)
++ {
++ /* Walk all slots in the hash. */
++ for (j = 0, slot = hash->nextHash;
++ (j < gcdSECURE_CACHE_SLOTS) && (slot != gcvNULL);
++ ++j, slot = next)
++ {
++ /* Save pointer to next slot. */
++ next = slot->next;
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Unlink slot from hash table. */
++ if (slot->prevHash == hash)
++ {
++ hash->nextHash = slot->nextHash;
++ }
++ else
++ {
++ slot->prevHash->nextHash = slot->nextHash;
++ }
++
++ if (slot->nextHash != gcvNULL)
++ {
++ slot->nextHash->prevHash = slot->prevHash;
++ }
++
++ /* Unlink slot from cache. */
++ slot->prev->next = slot->next;
++ slot->next->prev = slot->prev;
++
++ /* Append slot to tail of cache. */
++ slot->prev = Cache->cache[0].prev;
++ slot->next = &Cache->cache[0];
++ slot->prev->next = slot;
++ slot->next->prev = slot;
++
++ /* Mark slot as empty. */
++ slot->logical = gcvNULL;
++ slot->prevHash = gcvNULL;
++ slot->nextHash = gcvNULL;
++ }
++ }
++ }
++
++#elif gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_TABLE
++ gctUINT32 index;
++
++ /* Loop while inside the range. */
++ for (i = 1; (low < high) && (i <= gcdSECURE_CACHE_SLOTS); ++i)
++ {
++ /* Get index into cache for this range. */
++ index = (gcmPTR2INT32(low) % gcdSECURE_CACHE_SLOTS) + 1;
++ slot = &Cache->cache[index];
++
++ /* Test if this slot falls within the range to flush. */
++ ptr = (gctUINT8_PTR) slot->logical;
++ if ((ptr >= low) && (ptr < high))
++ {
++ /* Remove entry from cache. */
++ slot->logical = gcvNULL;
++ }
++
++ /* Next block. */
++ low += gcdSECURE_CACHE_SLOTS;
++ }
++#endif
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++ gckEVENT eventObj;
++ gckHARDWARE hardware;
++#if gcdSECURE_USER
++ gctUINT32 processID;
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ gctUINT32 mask = 0;
++ gckCOMMAND command;
++ gckENTRYDATA data;
++ gctUINT32 i = 0, count = 0;
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 oldValue;
++#endif
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Grab gckEVENT object. */
++ eventObj = Kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Grab gckCOMMAND object. */
++ command = Kernel->command;
++ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND);
++
++#if gcdSECURE_USER
++ /* Flush the secure mapping cache. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Kernel, processID, &cache));
++ gcmkONERROR(gckKERNEL_FlushTranslationCache(Kernel, cache, gcvNULL, 0));
++#endif
++
++ if (Kernel->stuckDump == gcdSTUCK_DUMP_MINIMAL)
++ {
++ gcmkPRINT("[galcore]: GPU[%d] hang, automatic recovery.", Kernel->core);
++ }
++ else
++ {
++ _DumpDriverConfigure(Kernel);
++ _DumpState(Kernel);
++ }
++
++ if (Kernel->recovery == gcvFALSE)
++ {
++ gcmkPRINT("[galcore]: Stop driver to keep scene.");
++
++ for (;;)
++ {
++ gckOS_Delay(Kernel->os, 10000);
++ }
++ }
++
++ /* Clear queue. */
++ do
++ {
++ status = gckENTRYQUEUE_Dequeue(&command->queue, &data);
++ }
++ while (status == gcvSTATUS_OK);
++
++ /* Issuing a soft reset for the GPU. */
++ gcmkONERROR(gckHARDWARE_Reset(hardware));
++
++ mask = Kernel->restoreMask;
++
++ for (i = 0; i < 32; i++)
++ {
++ if (mask & (1 << i))
++ {
++ count++;
++ }
++ }
++
++ /* Handle all outstanding events now. */
++#if gcdSMP
++#if gcdMULTI_GPU
++ if (Kernel->core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending3D[i], mask));
++ }
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, mask));
++ }
++#else
++ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, mask));
++#endif
++#else
++#if gcdMULTI_GPU
++ if (Kernel->core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ eventObj->pending3D[i] = mask;
++ }
++ }
++ else
++ {
++ eventObj->pending = mask;
++ }
++#else
++ eventObj->pending = mask;
++#endif
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ while (count--)
++ {
++ gcmkONERROR(gckOS_AtomDecrement(
++ Kernel->os,
++ eventObj->interruptCount,
++ &oldValue
++ ));
++ }
++
++ gckOS_AtomClearMask(Kernel->hardware->pendingEvent, mask);
++#endif
++
++ gcmkONERROR(gckEVENT_Notify(eventObj, 1));
++
++ gcmkVERIFY_OK(gckOS_GetTime(&Kernel->resetTimeStamp));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_OpenUserData
++**
++** Get access to the user data.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctPOINTER StaticStorage
++** Pointer to the kernel storage where the data is to be copied if
++** NeedCopy is gcvTRUE.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to the kernel pointer that will be pointing to the data.
++*/
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d StaticStorage=0x%08X "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, StaticStorage, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(!NeedCopy || (StaticStorage != gcvNULL));
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ if (NeedCopy)
++ {
++ /* Copy the user data to the static storage. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Kernel->os, StaticStorage, UserPointer, Size
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = StaticStorage;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map the user pointer. */
++ gcmkONERROR(gckOS_MapUserPointer(
++ Kernel->os, UserPointer, Size, &pointer
++ ));
++
++ /* Set the kernel pointer. */
++ * KernelPointer = pointer;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_CloseUserData
++**
++** Release resources associated with the user data connection opened by
++** gckKERNEL_OpenUserData.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL NeedCopy
++** The flag indicating whether or not the data should be copied.
++**
++** gctBOOL FlushData
++** If gcvTRUE, the data is written back to the user.
++**
++** gctPOINTER UserPointer
++** User pointer to the data.
++**
++** gctSIZE_T Size
++** Size of the data.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Kernel pointer to the data.
++*/
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG(
++ "Kernel=0x%08X NeedCopy=%d FlushData=%d "
++ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X",
++ Kernel, NeedCopy, FlushData, UserPointer, Size, KernelPointer
++ );
++
++ /* Validate the arguemnts. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Get a shortcut to the kernel pointer. */
++ pointer = * KernelPointer;
++
++ if (pointer != gcvNULL)
++ {
++ if (NeedCopy)
++ {
++ if (FlushData)
++ {
++ gcmkONERROR(gckOS_CopyToUserData(
++ Kernel->os, * KernelPointer, UserPointer, Size
++ ));
++ }
++ }
++ else
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Kernel->os,
++ UserPointer,
++ Size,
++ * KernelPointer
++ ));
++ }
++
++ /* Reset the kernel pointer. */
++ * KernelPointer = gcvNULL;
++ }
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ )
++{
++ gcmkHEADER_ARG("Kernel=0x%x timeOut=%d", Kernel, timeOut);
++#if gcdGPU_TIMEOUT
++ Kernel->timeOut = timeOut;
++#endif
++ gcmkFOOTER_NO();
++}
++
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckOS os = Kernel->os;
++ gceSTATUS status;
++ gctPOINTER logical = gcvNULL;
++ gctSIZE_T pageCount;
++ gctSIZE_T bytes = *Bytes;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = gcvNULL;
++ gckMMU mmu;
++ gctUINT32 flag = gcvALLOC_FLAG_NON_CONTIGUOUS;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(os,
++ sizeof(gckVIRTUAL_COMMAND_BUFFER),
++ (gctPOINTER)&buffer));
++
++ gcmkONERROR(gckOS_ZeroMemory(buffer, sizeof(gckVIRTUAL_COMMAND_BUFFER)));
++
++ buffer->bytes = bytes;
++
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(os,
++ flag,
++ bytes,
++ gcvNULL,
++ &buffer->physical));
++
++ if (InUserSpace)
++ {
++ gcmkONERROR(gckOS_CreateUserVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ &logical,
++ &pageCount));
++
++ *Logical =
++ buffer->userLogical = logical;
++ }
++ else
++ {
++ gcmkONERROR(gckOS_CreateKernelVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ &logical,
++ &pageCount));
++
++ *Logical =
++ buffer->kernelLogical = logical;
++ }
++
++ buffer->pageCount = pageCount;
++ buffer->kernel = Kernel;
++
++ gcmkONERROR(gckOS_GetProcessID(&buffer->pid));
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu));
++ buffer->mmu = mmu;
++#else
++ mmu = Kernel->mmu;
++#endif
++
++ gcmkONERROR(gckMMU_AllocatePages(mmu,
++ pageCount,
++ &buffer->pageTable,
++ &buffer->gpuAddress));
++
++
++ gcmkONERROR(gckOS_MapPagesEx(os,
++ Kernel->core,
++ buffer->physical,
++ pageCount,
++ buffer->gpuAddress,
++ buffer->pageTable));
++
++ gcmkONERROR(gckMMU_Flush(mmu, gcvSURF_INDEX));
++
++ *Physical = buffer;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL,
++ "gpuAddress = %x pageCount = %d kernelLogical = %x userLogical=%x",
++ buffer->gpuAddress, buffer->pageCount,
++ buffer->kernelLogical, buffer->userLogical);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ if (Kernel->virtualBufferHead == gcvNULL)
++ {
++ Kernel->virtualBufferHead =
++ Kernel->virtualBufferTail = buffer;
++ }
++ else
++ {
++ buffer->prev = Kernel->virtualBufferTail;
++ Kernel->virtualBufferTail->next = buffer;
++ Kernel->virtualBufferTail = buffer;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (buffer->gpuAddress)
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(mmu, buffer->pageTable, buffer->pageCount));
++#else
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu, buffer->pageTable, buffer->pageCount));
++#endif
++ }
++
++ if (buffer->userLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyUserVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ buffer->userLogical));
++ }
++
++ if (buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ bytes,
++ buffer->kernelLogical));
++ }
++
++ if (buffer->physical)
++ {
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, bytes));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ gckOS os;
++ gckKERNEL kernel;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)Physical;
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(buffer != gcvNULL);
++
++ kernel = buffer->kernel;
++ os = kernel->os;
++
++ if (!buffer->userLogical)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ Bytes,
++ Logical));
++ }
++
++#if !gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(kernel->mmu, buffer->pageTable, buffer->pageCount));
++#endif
++
++ gcmkVERIFY_OK(gckOS_UnmapPages(os, buffer->pageCount, buffer->gpuAddress));
++
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, Bytes));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, kernel->virtualBufferLock, gcvINFINITE));
++
++ if (buffer == kernel->virtualBufferHead)
++ {
++ if ((kernel->virtualBufferHead = buffer->next) == gcvNULL)
++ {
++ kernel->virtualBufferTail = gcvNULL;
++ }
++ }
++ else
++ {
++ buffer->prev->next = buffer->next;
++
++ if (buffer == kernel->virtualBufferTail)
++ {
++ kernel->virtualBufferTail = buffer->prev;
++ }
++ else
++ {
++ buffer->next->prev = buffer->prev;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, kernel->virtualBufferLock));
++
++ gcmkVERIFY_OK(gckOS_Free(os, buffer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctPOINTER start;
++ gctUINT32 pid;
++
++ gcmkHEADER_ARG("Logical = %x InUserSpace=%d.", Logical, InUserSpace);
++
++ gcmkVERIFY_OK(gckOS_GetProcessID(&pid));
++
++ status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffer. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ if (InUserSpace)
++ {
++ start = buffer->userLogical;
++ }
++ else
++ {
++ start = buffer->kernelLogical;
++ }
++
++ if (start == gcvNULL)
++ {
++ continue;
++ }
++
++ if (Logical >= start
++ && (Logical < (gctPOINTER)((gctUINT8_PTR)start + buffer->pageCount * 4096))
++ && pid == buffer->pid
++ )
++ {
++ * Address = buffer->gpuAddress + (gctUINT32)((gctUINT8_PTR)Logical - (gctUINT8_PTR)start);
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ )
++{
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 start;
++ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED;
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE));
++
++ /* Walk all command buffers. */
++ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next)
++ {
++ start = (gctUINT32)buffer->gpuAddress;
++
++ if (GpuAddress >= start && GpuAddress < (start + buffer->pageCount * 4096))
++ {
++ /* Find a range matched. */
++ *Buffer = buffer;
++ status = gcvSTATUS_OK;
++ break;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock));
++
++ return status;
++}
++
++#if gcdLINK_QUEUE_SIZE
++static void
++gckLINKQUEUE_Dequeue(
++ IN gckLINKQUEUE LinkQueue
++ )
++{
++ gcmkASSERT(LinkQueue->count == gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count--;
++ LinkQueue->front = (LinkQueue->front + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ )
++{
++ if (LinkQueue->count == gcdLINK_QUEUE_SIZE)
++ {
++ gckLINKQUEUE_Dequeue(LinkQueue);
++ }
++
++ gcmkASSERT(LinkQueue->count < gcdLINK_QUEUE_SIZE);
++
++ LinkQueue->count++;
++
++ LinkQueue->data[LinkQueue->rear].start = start;
++ LinkQueue->data[LinkQueue->rear].end = end;
++
++ gcmkVERIFY_OK(
++ gckOS_GetProcessID(&LinkQueue->data[LinkQueue->rear].pid));
++
++ LinkQueue->rear = (LinkQueue->rear + 1) % gcdLINK_QUEUE_SIZE;
++}
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ )
++{
++ gcmkASSERT(Index >= 0 && Index < gcdLINK_QUEUE_SIZE);
++
++ *Data = &LinkQueue->data[(Index + LinkQueue->front) % gcdLINK_QUEUE_SIZE];
++}
++#endif
++
++/*
++* gckENTRYQUEUE_Enqueue is called with Command->mutexQueue acquired.
++*/
++gceSTATUS
++gckENTRYQUEUE_Enqueue(
++ IN gckKERNEL Kernel,
++ IN gckENTRYQUEUE Queue,
++ IN gctUINT32 physical,
++ IN gctUINT32 bytes
++ )
++{
++ gctUINT32 next = (Queue->rear + 1) % gcdENTRY_QUEUE_SIZE;
++
++ if (next == Queue->front)
++ {
++ /* Queue is full. */
++ return gcvSTATUS_INVALID_REQUEST;
++ }
++
++ /* Copy data. */
++ Queue->data[Queue->rear].physical = physical;
++ Queue->data[Queue->rear].bytes = bytes;
++
++ gcmkVERIFY_OK(gckOS_MemoryBarrier(Kernel->os, &Queue->rear));
++
++ /* Update rear. */
++ Queue->rear = next;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckENTRYQUEUE_Dequeue(
++ IN gckENTRYQUEUE Queue,
++ OUT gckENTRYDATA * Data
++ )
++{
++ if (Queue->front == Queue->rear)
++ {
++ /* Queue is empty. */
++ return gcvSTATUS_INVALID_REQUEST;
++ }
++
++ /* Copy data. */
++ *Data = &Queue->data[Queue->front];
++
++ /* Update front. */
++ Queue->front = (Queue->front + 1) % gcdENTRY_QUEUE_SIZE;
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++*************************** Pointer - ID translation ***************************
++\******************************************************************************/
++#define gcdID_TABLE_LENGTH 1024
++typedef struct _gcsINTEGERDB * gckINTEGERDB;
++typedef struct _gcsINTEGERDB
++{
++ gckOS os;
++ gctPOINTER* table;
++ gctPOINTER mutex;
++ gctUINT32 tableLen;
++ gctUINT32 currentID;
++ gctUINT32 unused;
++}
++gcsINTEGERDB;
++
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Allocate a database. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gcsINTEGERDB), (gctPOINTER *)&database));
++
++ gcmkONERROR(gckOS_ZeroMemory(database, gcmSIZEOF(gcsINTEGERDB)));
++
++ /* Allocate a pointer table. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH, (gctPOINTER *)&database->table));
++
++ gcmkONERROR(gckOS_ZeroMemory(database->table, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH));
++
++ /* Allocate a database mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->mutex));
++
++ /* Initialize. */
++ database->currentID = 0;
++ database->unused = gcdID_TABLE_LENGTH;
++ database->os = Kernel->os;
++ database->tableLen = gcdID_TABLE_LENGTH;
++
++ *Database = database;
++
++ gcmkFOOTER_ARG("*Database=0x%08X", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Rollback. */
++ if (database)
++ {
++ if (database->table)
++ {
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++ }
++
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ )
++{
++ gckINTEGERDB database = Database;
++
++ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Database != gcvNULL);
++
++ /* Destroy pointer table. */
++ gcmkOS_SAFE_FREE(Kernel->os, database->table);
++
++ /* Destroy database mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->mutex));
++
++ /* Destroy database. */
++ gcmkOS_SAFE_FREE(Kernel->os, database);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctUINT32 i, unused, currentID, tableLen;
++ gctPOINTER * table;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Pointer=0x%08X", Database, Pointer);
++
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (database->unused < 1)
++ {
++ /* Extend table. */
++ gcmkONERROR(
++ gckOS_Allocate(os,
++ gcmSIZEOF(gctPOINTER) * (database->tableLen + gcdID_TABLE_LENGTH),
++ (gctPOINTER *)&table));
++
++ gcmkONERROR(gckOS_ZeroMemory(table + database->tableLen,
++ gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH));
++
++ /* Copy data from old table. */
++ gckOS_MemCopy(table,
++ database->table,
++ database->tableLen * gcmSIZEOF(gctPOINTER));
++
++ gcmkOS_SAFE_FREE(os, database->table);
++
++ /* Update databse with new allocated table. */
++ database->table = table;
++ database->currentID = database->tableLen;
++ database->tableLen += gcdID_TABLE_LENGTH;
++ database->unused += gcdID_TABLE_LENGTH;
++ }
++
++ table = database->table;
++ currentID = database->currentID;
++ tableLen = database->tableLen;
++ unused = database->unused;
++
++ /* Connect id with pointer. */
++ table[currentID] = Pointer;
++
++ *Id = currentID + 1;
++
++ /* Update the currentID. */
++ if (--unused > 0)
++ {
++ for (i = 0; i < tableLen; i++)
++ {
++ if (++currentID >= tableLen)
++ {
++ /* Wrap to the begin. */
++ currentID = 0;
++ }
++
++ if (table[currentID] == gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ database->table = table;
++ database->currentID = currentID;
++ database->tableLen = tableLen;
++ database->unused = unused;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_ARG("*Id=%d", *Id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ database->table[Id] = gcvNULL;
++
++ if (database->unused++ == 0)
++ {
++ database->currentID = Id;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ )
++{
++ gceSTATUS status;
++ gckINTEGERDB database = Database;
++ gctPOINTER pointer;
++ gckOS os = database->os;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (!(Id > 0 && Id <= database->tableLen))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ Id -= 1;
++
++ pointer = database->table[Id];
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ acquired = gcvFALSE;
++
++ if (pointer)
++ {
++ *Pointer = pointer;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_NOT_FOUND);
++ }
++
++ gcmkFOOTER_ARG("*Pointer=0x%08X", *Pointer);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gctUINT32 name;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Pointer=0x%X", Kernel, Pointer);
++
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(database, Pointer, &name));
++
++ gcmkFOOTER_ARG("name=%d", name);
++ return name;
++
++OnError:
++ gcmkFOOTER();
++ return 0;
++}
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer = gcvNULL;
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name);
++
++ /* Lookup in database to get pointer. */
++ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, &pointer));
++
++ gcmkFOOTER_ARG("pointer=0x%X", pointer);
++ return pointer;
++
++OnError:
++ gcmkFOOTER();
++ return gcvNULL;
++}
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ )
++{
++ gctPOINTER database = Kernel->db->pointerDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=0x%X", Kernel, Name);
++
++ /* Free name if exists. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Name));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckKERNEL_SetRecovery(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Recovery,
++ IN gctUINT32 StuckDump
++ )
++{
++ Kernel->recovery = Recovery;
++
++ if (Recovery == gcvFALSE)
++ {
++ /* Dump stuck information if Recovery is disabled. */
++ Kernel->stuckDump = gcmMAX(StuckDump, gcdSTUCK_DUMP_MIDDLE);
++ }
++
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++***** Shared Buffer ************************************************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_CreateShBuffer
++**
++** Create shared buffer.
++** The shared buffer can be used across processes. Other process needs call
++** gckKERNEL_MapShBuffer before use it.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Size
++** Specify the shared buffer size.
++**
++** OUTPUT:
++**
++** gctSHBUF * ShBuf
++** Pointer to hold return shared buffer handle.
++*/
++gceSTATUS
++gckKERNEL_CreateShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Size,
++ OUT gctSHBUF * ShBuf
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%X, Size=%u", Kernel, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (Size == 0)
++ {
++ /* Invalid size. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++ else if (Size > 1024)
++ {
++ /* Limite shared buffer size. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Create a shared buffer structure. */
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof (gcsSHBUF),
++ (gctPOINTER *)&shBuf));
++
++ /* Initialize shared buffer. */
++ shBuf->id = 0;
++ shBuf->reference = gcvNULL;
++ shBuf->size = Size;
++ shBuf->data = gcvNULL;
++
++ /* Allocate integer id for this shared buffer. */
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(Kernel->db->pointerDatabase,
++ shBuf,
++ &shBuf->id));
++
++ /* Allocate atom. */
++ gcmkONERROR(gckOS_AtomConstruct(Kernel->os, &shBuf->reference));
++
++ /* Set default reference count to 1. */
++ gcmkVERIFY_OK(gckOS_AtomSet(Kernel->os, shBuf->reference, 1));
++
++ /* Return integer id. */
++ *ShBuf = (gctSHBUF)(gctUINTPTR_T)shBuf->id;
++
++ gcmkFOOTER_ARG("*ShBuf=%u", shBuf->id);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Error roll back. */
++ if (shBuf != gcvNULL)
++ {
++ if (shBuf->id != 0)
++ {
++ gcmkVERIFY_OK(
++ gckKERNEL_FreeIntegerId(Kernel->db->pointerDatabase,
++ shBuf->id));
++ }
++
++ gcmkOS_SAFE_FREE(Kernel->os, shBuf);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_DestroyShBuffer
++**
++** Destroy shared buffer.
++** This will decrease reference of specified shared buffer and do actual
++** destroy when no reference on it.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_DestroyShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctINT32 oldValue = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ /* Decrease the reference count. */
++ gckOS_AtomDecrement(Kernel->os, shBuf->reference, &oldValue);
++
++ if (oldValue == 1)
++ {
++ /* Free integer id. */
++ gcmkVERIFY_OK(
++ gckKERNEL_FreeIntegerId(Kernel->db->pointerDatabase,
++ shBuf->id));
++
++ /* Free atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, shBuf->reference));
++
++ if (shBuf->data)
++ {
++ gcmkOS_SAFE_FREE(Kernel->os, shBuf->data);
++ shBuf->data = gcvNULL;
++ }
++
++ /* Free the shared buffer. */
++ gcmkOS_SAFE_FREE(Kernel->os, shBuf);
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapShBuffer
++**
++** Map shared buffer into this process so that it can be used in this process.
++** This will increase reference count on the specified shared buffer.
++** Call gckKERNEL_DestroyShBuffer to dereference.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be mapped.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_MapShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctINT32 oldValue = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ /* Increase the reference count. */
++ gckOS_AtomIncrement(Kernel->os, shBuf->reference, &oldValue);
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_WriteShBuffer
++**
++** Write user data into shared buffer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be written to.
++**
++** gctPOINTER UserData
++** User mode pointer to hold the source data.
++**
++** gctUINT32 ByteCount
++** Specify number of bytes to write. If this is larger than
++** shared buffer size, gcvSTATUS_INVALID_ARGUMENT is returned.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_WriteShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u UserData=0x%X ByteCount=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf, UserData, ByteCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ if ((ByteCount > shBuf->size) ||
++ (ByteCount == 0) ||
++ (UserData == gcvNULL))
++ {
++ /* Exceeds buffer max size or invalid. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (shBuf->data == gcvNULL)
++ {
++ /* Allocate buffer data when first time write. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os, ByteCount, &shBuf->data));
++ }
++
++ /* Copy data from user. */
++ gcmkONERROR(
++ gckOS_CopyFromUserData(Kernel->os,
++ shBuf->data,
++ UserData,
++ ByteCount));
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_ReadShBuffer
++**
++** Read data from shared buffer and copy to user pointer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSHBUF ShBuf
++** Specify the shared buffer to be read from.
++**
++** gctPOINTER UserData
++** User mode pointer to save output data.
++**
++** gctUINT32 ByteCount
++** Specify number of bytes to read.
++** If this is larger than shared buffer size, only avaiable bytes are
++** copied. If smaller, copy requested size.
++**
++** OUTPUT:
++**
++** gctUINT32 * BytesRead
++** Pointer to hold how many bytes actually read from shared buffer.
++*/
++gceSTATUS
++gckKERNEL_ReadShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount,
++ OUT gctUINT32 * BytesRead
++ )
++{
++ gceSTATUS status;
++ gcsSHBUF_PTR shBuf;
++ gctUINT32 bytes;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u UserData=0x%X ByteCount=%u",
++ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf, UserData, ByteCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL);
++
++ /* Acquire mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os,
++ Kernel->db->pointerDatabaseMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Find shared buffer structure. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase,
++ (gctUINT32)(gctUINTPTR_T)ShBuf,
++ (gctPOINTER)&shBuf));
++
++ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf);
++
++ if (shBuf->data == gcvNULL)
++ {
++ *BytesRead = 0;
++
++ /* No data in shared buffer, skip copy. */
++ status = gcvSTATUS_SKIP;
++ goto OnError;
++ }
++ else if (ByteCount == 0)
++ {
++ /* Invalid size to read. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Determine bytes to copy. */
++ bytes = (ByteCount < shBuf->size) ? ByteCount : shBuf->size;
++
++ /* Copy data to user. */
++ gcmkONERROR(
++ gckOS_CopyToUserData(Kernel->os,
++ shBuf->data,
++ UserData,
++ bytes));
++
++ /* Return copied size. */
++ *BytesRead = bytes;
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_ARG("*BytesRead=%u", bytes);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++/*******************************************************************************
++***** Test Code ****************************************************************
++*******************************************************************************/
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c 2016-06-19 22:11:55.221145518 +0200
+@@ -0,0 +1,3423 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_context.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _NewQueue
++**
++** Allocate a new command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** OUTPUT:
++**
++** gckCOMMAND Command
++** gckCOMMAND object has been updated with a new command queue.
++*/
++static gceSTATUS
++_NewQueue(
++ IN OUT gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctINT currentIndex, newIndex;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Switch to the next command buffer. */
++ currentIndex = Command->index;
++ newIndex = (currentIndex + 1) % gcdCOMMAND_QUEUES;
++
++ /* Wait for availability. */
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.waitsignal]");
++#endif
++
++ gcmkONERROR(gckOS_WaitSignal(
++ Command->os,
++ Command->queues[newIndex].signal,
++ gcvINFINITE
++ ));
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ if (newIndex < currentIndex)
++ {
++ Command->wrapCount += 1;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 2 * 4,
++ "%s(%d): queue array wrapped around.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): total queue wrap arounds %d.\n",
++ __FUNCTION__, __LINE__, Command->wrapCount
++ );
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ 3 * 4,
++ "%s(%d): switched to queue %d.\n",
++ __FUNCTION__, __LINE__, newIndex
++ );
++#endif
++
++ /* Update gckCOMMAND object with new command queue. */
++ Command->index = newIndex;
++ Command->newQueue = gcvTRUE;
++ Command->logical = Command->queues[newIndex].logical;
++ Command->address = Command->queues[newIndex].address;
++ Command->offset = 0;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Command->os,
++ Command->logical,
++ (gctUINT32 *) &Command->physical
++ ));
++
++ if (currentIndex != -1)
++ {
++ /* Mark the command queue as available. */
++ gcmkONERROR(gckEVENT_Signal(
++ Command->kernel->eventObj,
++ Command->queues[currentIndex].signal,
++ gcvKERNEL_COMMAND
++ ));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("Command->index=%d", Command->index);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_IncrementCommitAtom(
++ IN gckCOMMAND Command,
++ IN gctBOOL Increment
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctINT32 atomValue;
++ gctBOOL powerAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Grab the power mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, hardware->powerMutex, gcvINFINITE
++ ));
++ powerAcquired = gcvTRUE;
++
++ /* Increment the commit atom. */
++ if (Increment)
++ {
++ gcmkONERROR(gckOS_AtomIncrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckOS_AtomDecrement(
++ Command->os, Command->atomCommit, &atomValue
++ ));
++ }
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ powerAcquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (powerAcquired)
++ {
++ /* Release the power mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ Command->os, hardware->powerMutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdSECURE_USER
++static gceSTATUS
++_ProcessHints(
++ IN gckCOMMAND Command,
++ IN gctUINT32 ProcessID,
++ IN gcoCMDBUF CommandBuffer
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gckKERNEL kernel;
++ gctBOOL needCopy = gcvFALSE;
++ gcskSECURE_CACHE_PTR cache;
++ gctUINT8_PTR commandBufferLogical;
++ gctUINT8_PTR hintedData;
++ gctUINT32_PTR hintArray;
++ gctUINT i, hintCount;
++
++ gcmkHEADER_ARG(
++ "Command=0x%08X ProcessID=%d CommandBuffer=0x%08X",
++ Command, ProcessID, CommandBuffer
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Reset state array pointer. */
++ hintArray = gcvNULL;
++
++ /* Get the kernel object. */
++ kernel = Command->kernel;
++
++ /* Get the cache form the database. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(kernel, ProcessID, &cache));
++
++ /* Determine the start of the command buffer. */
++ commandBufferLogical
++ = (gctUINT8_PTR) CommandBuffer->logical
++ + CommandBuffer->startOffset;
++
++ /* Determine the number of records in the state array. */
++ hintCount = CommandBuffer->hintArrayTail - CommandBuffer->hintArray;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
++
++ /* Get access to the state array. */
++ if (needCopy)
++ {
++ gctUINT copySize;
++
++ if (Command->hintArrayAllocated &&
++ (Command->hintArraySize < CommandBuffer->hintArraySize))
++ {
++ gcmkONERROR(gcmkOS_SAFE_FREE(Command->os, gcmUINT64_TO_PTR(Command->hintArray)));
++ Command->hintArraySize = gcvFALSE;
++ }
++
++ if (!Command->hintArrayAllocated)
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkONERROR(gckOS_Allocate(
++ Command->os,
++ CommandBuffer->hintArraySize,
++ &pointer
++ ));
++
++ Command->hintArray = gcmPTR_TO_UINT64(pointer);
++ Command->hintArrayAllocated = gcvTRUE;
++ Command->hintArraySize = CommandBuffer->hintArraySize;
++ }
++
++ hintArray = gcmUINT64_TO_PTR(Command->hintArray);
++ copySize = hintCount * gcmSIZEOF(gctUINT32);
++
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os,
++ hintArray,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ copySize
++ ));
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ CommandBuffer->hintArraySize,
++ &pointer
++ ));
++
++ hintArray = pointer;
++ }
++
++ /* Scan through the buffer. */
++ for (i = 0; i < hintCount; i += 1)
++ {
++ /* Determine the location of the hinted data. */
++ hintedData = commandBufferLogical + hintArray[i];
++
++ /* Map handle into physical address. */
++ gcmkONERROR(gckKERNEL_MapLogicalToPhysical(
++ kernel, cache, (gctPOINTER) hintedData
++ ));
++ }
++
++OnError:
++ /* Get access to the state array. */
++ if (!needCopy && (hintArray != gcvNULL))
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ gcmUINT64_TO_PTR(CommandBuffer->hintArray),
++ CommandBuffer->hintArraySize,
++ hintArray
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++static gceSTATUS
++_FlushMMU(
++ IN gckCOMMAND Command
++ )
++{
++#if gcdSECURITY
++ return gcvSTATUS_OK;
++#else
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckHARDWARE hardware = Command->kernel->hardware;
++ gctBOOL pause = gcvFALSE;
++
++ gctUINT8_PTR pointer;
++ gctUINT32 eventBytes;
++ gctUINT32 endBytes;
++ gctUINT32 bufferSize;
++ gctUINT32 executeBytes;
++ gctUINT32 waitLinkBytes;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckHARDWARE_FlushMMU(hardware));
++
++ if ((oldValue & gcvPAGE_TABLE_DIRTY_BIT_FE)
++ && (hardware->endAfterFlushMmuCache)
++ )
++ {
++ pause = gcvTRUE;
++ }
++ }
++
++ if (pause)
++ {
++ /* Query size. */
++ gcmkONERROR(gckHARDWARE_Event(hardware, gcvNULL, 0, gcvKERNEL_PIXEL, &eventBytes));
++ gcmkONERROR(gckHARDWARE_End(hardware, gcvNULL, &endBytes));
++
++ executeBytes = eventBytes + endBytes;
++
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ gcvNULL,
++ Command->offset + executeBytes,
++ &waitLinkBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Reserve space. */
++ gcmkONERROR(gckCOMMAND_Reserve(
++ Command,
++ executeBytes,
++ (gctPOINTER *)&pointer,
++ &bufferSize
++ ));
++
++ /* Append EVENT(29). */
++ gcmkONERROR(gckHARDWARE_Event(
++ hardware,
++ pointer,
++ 29,
++ gcvKERNEL_PIXEL,
++ &eventBytes
++ ));
++
++ /* Append END. */
++ pointer += eventBytes;
++ gcmkONERROR(gckHARDWARE_End(hardware, pointer, &endBytes));
++
++ /* Store address to queue. */
++ gcmkONERROR(gckENTRYQUEUE_Enqueue(
++ Command->kernel,
++ &Command->queue,
++ Command->address + Command->offset + executeBytes,
++ waitLinkBytes
++ ));
++
++ gcmkONERROR(gckCOMMAND_Execute(Command, executeBytes));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++#endif
++}
++
++static void
++_DumpBuffer(
++ IN gctPOINTER Buffer,
++ IN gctUINT32 GpuAddress,
++ IN gctSIZE_T Size
++ )
++{
++ gctSIZE_T i, line, left;
++ gctUINT32_PTR data = Buffer;
++
++ line = Size / 32;
++ left = Size % 32;
++
++ for (i = 0; i < line; i++)
++ {
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]);
++ data += 8;
++ GpuAddress += 8 * 4;
++ }
++
++ switch(left)
++ {
++ case 28:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6]);
++ break;
++ case 24:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5]);
++ break;
++ case 20:
++ gcmkPRINT("%X : %08X %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3], data[4]);
++ break;
++ case 16:
++ gcmkPRINT("%X : %08X %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2], data[3]);
++ break;
++ case 12:
++ gcmkPRINT("%X : %08X %08X %08X ",
++ GpuAddress, data[0], data[1], data[2]);
++ break;
++ case 8:
++ gcmkPRINT("%X : %08X %08X ",
++ GpuAddress, data[0], data[1]);
++ break;
++ case 4:
++ gcmkPRINT("%X : %08X ",
++ GpuAddress, data[0]);
++ break;
++ default:
++ break;
++ }
++}
++
++static void
++_DumpKernelCommandBuffer(
++ IN gckCOMMAND Command
++ )
++{
++ gctINT i;
++ gctUINT32 physical = 0;
++ gctPOINTER entry = gcvNULL;
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ entry = Command->queues[i].logical;
++
++ gckOS_GetPhysicalAddress(Command->os, entry, &physical);
++
++ gcmkPRINT("Kernel command buffer %d\n", i);
++
++ _DumpBuffer(entry, physical, Command->pageSize);
++ }
++}
++
++/******************************************************************************\
++****************************** gckCOMMAND API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckCOMMAND_Construct
++**
++** Construct a new gckCOMMAND object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckCOMMAND * Command
++** Pointer to a variable that will hold the pointer to the gckCOMMAND
++** object.
++*/
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ )
++{
++ gckOS os;
++ gckCOMMAND command = gcvNULL;
++ gceSTATUS status;
++ gctINT i;
++ gctPOINTER pointer = gcvNULL;
++ gctSIZE_T pageSize;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ /* Extract the gckOS object. */
++ os = Kernel->os;
++
++ /* Allocate the gckCOMMAND structure. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckCOMMAND), &pointer));
++ command = pointer;
++
++ /* Reset the entire object. */
++ gcmkONERROR(gckOS_ZeroMemory(command, gcmSIZEOF(struct _gckCOMMAND)));
++
++ /* Initialize the gckCOMMAND object.*/
++ command->object.type = gcvOBJ_COMMAND;
++ command->kernel = Kernel;
++ command->os = os;
++
++ /* Get the command buffer requirements. */
++ gcmkONERROR(gckHARDWARE_QueryCommandBuffer(
++ Kernel->hardware,
++ &command->alignment,
++ &command->reservedHead,
++ &command->reservedTail
++ ));
++
++ /* Create the command queue mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexQueue));
++
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Create the context switching mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContextSeq));
++#endif
++
++ /* Create the power management semaphore. */
++ gcmkONERROR(gckOS_CreateSemaphore(os, &command->powerSemaphore));
++
++ /* Create the commit atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &command->atomCommit));
++
++ /* Get the page size from teh OS. */
++ gcmkONERROR(gckOS_GetPageSize(os, &pageSize));
++
++ gcmkSAFECASTSIZET(command->pageSize, pageSize);
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&command->kernelProcessID));
++
++ /* Set hardware to pipe 0. */
++ command->pipeSelect = gcvPIPE_INVALID;
++
++ /* Pre-allocate the command queues. */
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ os,
++ gcvFALSE,
++ &pageSize,
++ &command->queues[i].physical,
++ &command->queues[i].logical
++ ));
++
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ command->queues[i].logical,
++ gcvFALSE,
++ &command->queues[i].address
++ ));
++
++ gcmkONERROR(gckOS_CreateSignal(
++ os, gcvFALSE, &command->queues[i].signal
++ ));
++
++ gcmkONERROR(gckOS_Signal(
++ os, command->queues[i].signal, gcvTRUE
++ ));
++ }
++
++#if gcdRECORD_COMMAND
++ gcmkONERROR(gckRECORDER_Construct(os, Kernel->hardware, &command->recorder));
++#endif
++
++ /* No command queue in use yet. */
++ command->index = -1;
++ command->logical = gcvNULL;
++ command->newQueue = gcvFALSE;
++
++ /* Command is not yet running. */
++ command->running = gcvFALSE;
++
++ /* Command queue is idle. */
++ command->idle = gcvTRUE;
++
++ /* Commit stamp is zero. */
++ command->commitStamp = 0;
++
++ /* END event signal not created. */
++ command->endEventSignal = gcvNULL;
++
++ command->queue.front = 0;
++ command->queue.rear = 0;
++ command->queue.count = 0;
++
++ /* Return pointer to the gckCOMMAND object. */
++ *Command = command;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Command=0x%x", *Command);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ if (command->atomCommit != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, command->atomCommit));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(os, command->powerSemaphore));
++ }
++
++ if (command->mutexContext != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContext));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (command->mutexContextSeq != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContextSeq));
++ }
++#endif
++
++ if (command->mutexQueue != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexQueue));
++ }
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ if (command->queues[i].signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ os, command->queues[i].signal
++ ));
++ }
++
++ if (command->queues[i].logical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ os,
++ command->pageSize,
++ command->queues[i].physical,
++ command->queues[i].logical
++ ));
++ }
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, command));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Destroy
++**
++** Destroy an gckCOMMAND object.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Stop the command queue. */
++ gcmkVERIFY_OK(gckCOMMAND_Stop(Command, gcvFALSE));
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; ++i)
++ {
++ gcmkASSERT(Command->queues[i].signal != gcvNULL);
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->queues[i].signal
++ ));
++
++ gcmkASSERT(Command->queues[i].logical != gcvNULL);
++ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory(
++ Command->os,
++ Command->pageSize,
++ Command->queues[i].physical,
++ Command->queues[i].logical
++ ));
++ }
++
++ /* END event signal. */
++ if (Command->endEventSignal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, Command->endEventSignal
++ ));
++ }
++
++ /* Delete the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContext));
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (Command->mutexContextSeq != gcvNULL)
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContextSeq));
++#endif
++
++ /* Delete the command queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexQueue));
++
++ /* Destroy the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(Command->os, Command->powerSemaphore));
++
++ /* Destroy the commit atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Command->os, Command->atomCommit));
++
++#if gcdSECURE_USER
++ /* Free state array. */
++ if (Command->hintArrayAllocated)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, gcmUINT64_TO_PTR(Command->hintArray)));
++ Command->hintArrayAllocated = gcvFALSE;
++ }
++#endif
++
++#if gcdRECORD_COMMAND
++ gckRECORDER_Destory(Command->os, Command->recorder);
++#endif
++
++ /* Mark object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckCOMMAND object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, Command));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_EnterCommit
++**
++** Acquire command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctBOOL atomIncremented = gcvFALSE;
++ gctBOOL semaAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (!FromPower)
++ {
++ /* Increment COMMIT atom to let power management know that a commit is
++ ** in progress. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvTRUE));
++ atomIncremented = gcvTRUE;
++
++ /* Notify the system the GPU has a commit. */
++ gcmkONERROR(gckOS_Broadcast(Command->os,
++ hardware,
++ gcvBROADCAST_GPU_COMMIT));
++
++ /* Acquire the power management semaphore. */
++ gcmkONERROR(gckOS_AcquireSemaphore(Command->os,
++ Command->powerSemaphore));
++ semaAcquired = gcvTRUE;
++ }
++
++ /* Grab the conmmand queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Command->os,
++ Command->mutexQueue,
++ gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (semaAcquired)
++ {
++ /* Release the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++ }
++
++ if (atomIncremented)
++ {
++ /* Decrement the commit atom. */
++ gcmkVERIFY_OK(_IncrementCommitAtom(
++ Command, gcvFALSE
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_ExitCommit
++**
++** Release command queue synchronization objects.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to destroy.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Release the power mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexQueue));
++
++ if (!FromPower)
++ {
++ /* Release the power management semaphore. */
++ gcmkONERROR(gckOS_ReleaseSemaphore(Command->os,
++ Command->powerSemaphore));
++
++ /* Decrement the commit atom. */
++ gcmkONERROR(_IncrementCommitAtom(Command, gcvFALSE));
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Start
++**
++** Start up the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to start.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckHARDWARE hardware;
++ gctUINT32 waitOffset = 0;
++ gctUINT32 waitLinkBytes;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->running)
++ {
++ /* Command queue already running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (Command->logical == gcvNULL)
++ {
++ /* Start at beginning of a new queue. */
++ gcmkONERROR(_NewQueue(Command));
++ }
++
++ /* Start at beginning of page. */
++ Command->offset = 0;
++
++ /* Set abvailable number of bytes for WAIT/LINK command sequence. */
++ waitLinkBytes = Command->pageSize;
++
++ /* Append WAIT/LINK. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ Command->logical,
++ 0,
++ &waitLinkBytes,
++ &waitOffset,
++ &Command->waitSize
++ ));
++
++ Command->waitLogical = (gctUINT8_PTR) Command->logical + waitOffset;
++ Command->waitPhysical = (gctUINT8_PTR) Command->physical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the wait/link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->physical,
++ Command->logical,
++ waitLinkBytes
++ ));
++#endif
++
++ /* Adjust offset. */
++ Command->offset = waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++#if gcdSECURITY
++ /* Start FE by calling security service. */
++ gckKERNEL_SecurityStartCommand(
++ Command->kernel
++ );
++#else
++ /* Enable command processor. */
++ gcmkONERROR(gckHARDWARE_Execute(
++ hardware,
++ Command->address,
++ waitLinkBytes
++ ));
++#endif
++
++ /* Command queue is running. */
++ Command->running = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stop
++**
++** Stop the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object to stop.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ )
++{
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gctUINT32 idle;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (!Command->running)
++ {
++ /* Command queue is not running. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Extract the gckHARDWARE object. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ if (gckHARDWARE_IsFeatureAvailable(hardware,
++ gcvFEATURE_END_EVENT) == gcvSTATUS_TRUE)
++ {
++ /* Allocate the signal. */
++ if (Command->endEventSignal == gcvNULL)
++ {
++ gcmkONERROR(gckOS_CreateSignal(Command->os,
++ gcvTRUE,
++ &Command->endEventSignal));
++ }
++
++ /* Append the END EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Stop(Command->kernel->eventObj,
++ Command->kernelProcessID,
++ Command->waitPhysical,
++ Command->waitLogical,
++ Command->endEventSignal,
++ &Command->waitSize));
++ }
++ else
++ {
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ hardware, Command->waitLogical, &Command->waitSize
++ ));
++
++#if gcdSECURITY
++ gcmkONERROR(gckKERNEL_SecurityExecute(
++ Command->kernel, Command->waitLogical, 8
++ ));
++#endif
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(Command->kernel->hardware,
++ Command->logical,
++ Command->offset));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ /* Wait for idle. */
++ gcmkONERROR(gckHARDWARE_GetIdle(hardware, !FromRecovery, &idle));
++ }
++
++ /* Command queue is no longer running. */
++ Command->running = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Commit
++**
++** Commit a command buffer to the command queue.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object.
++**
++** gcoCMDBUF CommandBuffer
++** Pointer to a gcoCMDBUF object.
++**
++** gcsSTATE_DELTA_PTR StateDelta
++** Pointer to the state delta.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++#if gcdMULTI_GPU
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID,
++ IN gceCORE_3D_MASK ChipEnable
++ )
++#else
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ )
++#endif
++{
++ gceSTATUS status;
++ gctBOOL commitEntered = gcvFALSE;
++ gctBOOL contextAcquired = gcvFALSE;
++ gckHARDWARE hardware;
++ gctBOOL needCopy = gcvFALSE;
++ gcsQUEUE_PTR eventRecord = gcvNULL;
++ gcsQUEUE _eventRecord;
++ gcsQUEUE_PTR nextEventRecord;
++ gctBOOL commandBufferMapped = gcvFALSE;
++ gcoCMDBUF commandBufferObject = gcvNULL;
++
++#if !gcdNULL_DRIVER
++ gcsCONTEXT_PTR contextBuffer;
++ struct _gcoCMDBUF _commandBufferObject;
++ gctPHYS_ADDR commandBufferPhysical;
++ gctUINT8_PTR commandBufferLogical = gcvNULL;
++ gctUINT32 commandBufferAddress = 0;
++ gctUINT8_PTR commandBufferLink = gcvNULL;
++ gctUINT commandBufferSize;
++ gctSIZE_T nopBytes;
++ gctUINT32 pipeBytes;
++ gctUINT32 linkBytes;
++ gctSIZE_T bytes;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR entryPhysical;
++#endif
++ gctPOINTER entryLogical;
++ gctUINT32 entryAddress;
++ gctUINT32 entryBytes;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR exitPhysical;
++#endif
++ gctPOINTER exitLogical;
++ gctUINT32 exitAddress;
++ gctUINT32 exitBytes;
++ gctPHYS_ADDR waitLinkPhysical;
++ gctPOINTER waitLinkLogical;
++ gctUINT32 waitLinkAddress;
++ gctUINT32 waitLinkBytes;
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctUINT32 waitSize;
++
++#ifdef __QNXNTO__
++ gctPOINTER userCommandBufferLogical = gcvNULL;
++ gctBOOL userCommandBufferLogicalMapped = gcvFALSE;
++ gctPOINTER userCommandBufferLink = gcvNULL;
++ gctBOOL userCommandBufferLinkMapped = gcvFALSE;
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gctSIZE_T mmuConfigureBytes;
++ gctPOINTER mmuConfigureLogical = gcvNULL;
++ gctUINT32 mmuConfigureAddress;
++ gctPOINTER mmuConfigurePhysical = 0;
++ gctSIZE_T mmuConfigureWaitLinkOffset;
++ gckMMU mmu;
++ gctSIZE_T reservedBytes;
++ gctUINT32 oldValue;
++#endif
++
++#if gcdDUMP_COMMAND
++ gctPOINTER contextDumpLogical = gcvNULL;
++ gctSIZE_T contextDumpBytes = 0;
++ gctPOINTER bufferDumpLogical = gcvNULL;
++ gctSIZE_T bufferDumpBytes = 0;
++# endif
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ gctBOOL sequenceAcquired = gcvFALSE;
++#endif
++
++ gctPOINTER pointer = gcvNULL;
++
++#if gcdMULTI_GPU
++ gctSIZE_T chipEnableBytes;
++#endif
++
++ gcmkHEADER_ARG(
++ "Command=0x%x CommandBuffer=0x%x ProcessID=%d",
++ Command, CommandBuffer, ProcessID
++ );
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ if (Command->kernel->hardware->type== gcvHARDWARE_2D)
++ {
++ /* There is no context for 2D. */
++ Context = gcvNULL;
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Command->kernel, &mmu));
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ mmu->pageTableDirty[Command->kernel->core],
++ 0,
++ &oldValue));
++#else
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++ if((Command->kernel->hardware->gpuProfiler) && (Command->kernel->profileEnable))
++ {
++ /* Acquire the context sequnence mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContextSeq, gcvINFINITE
++ ));
++ sequenceAcquired = gcvTRUE;
++ }
++#endif
++
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(Command, gcvFALSE));
++ commitEntered = gcvTRUE;
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ contextAcquired = gcvTRUE;
++
++ /* Extract the gckHARDWARE and gckEVENT objects. */
++ hardware = Command->kernel->hardware;
++
++ /* Check wehther we need to copy the structures or not. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy));
++
++#if gcdNULL_DRIVER
++ /* Context switch required? */
++ if ((Context != gcvNULL) && (Command->currContext != Context))
++ {
++ /* Yes, merge in the deltas. */
++ gckCONTEXT_Update(Context, ProcessID, StateDelta);
++
++ /* Update the current context. */
++ Command->currContext = Context;
++ }
++#else
++ if (needCopy)
++ {
++ commandBufferObject = &_commandBufferObject;
++
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os,
++ commandBufferObject,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF)
++ ));
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ }
++ else
++ {
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ &pointer
++ ));
++
++ commandBufferObject = pointer;
++
++ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER);
++ commandBufferMapped = gcvTRUE;
++ }
++
++ /* Query the size of NOP command. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware, gcvNULL, &nopBytes
++ ));
++
++ /* Query the size of pipe select command sequence. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ hardware, gcvNULL, gcvPIPE_3D, &pipeBytes
++ ));
++
++ /* Query the size of LINK command. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware, gcvNULL, 0, 0, &linkBytes
++ ));
++
++#if gcdMULTI_GPU
++ /* Query the size of chip enable command sequence. */
++ gcmkONERROR(gckHARDWARE_ChipEnable(
++ hardware, gcvNULL, 0, &chipEnableBytes
++ ));
++#endif
++
++ /* Compute the command buffer entry and the size. */
++ commandBufferLogical
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->startOffset;
++
++ /* Get the hardware address. */
++ if (Command->kernel->virtualCommandBuffer)
++ {
++ gcmkONERROR(gckKERNEL_GetGPUAddress(
++ Command->kernel,
++ commandBufferLogical,
++ gcvTRUE,
++ &commandBufferAddress
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ hardware,
++ commandBufferLogical,
++ gcvTRUE,
++ &commandBufferAddress
++ ));
++ }
++
++ /* Get the physical address. */
++ gcmkONERROR(gckOS_UserLogicalToPhysical(
++ Command->os,
++ commandBufferLogical,
++ (gctUINT32_PTR)&commandBufferPhysical
++ ));
++
++#ifdef __QNXNTO__
++ userCommandBufferLogical = (gctPOINTER) commandBufferLogical;
++
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ userCommandBufferLogical,
++ 0,
++ &pointer));
++
++ commandBufferLogical = pointer;
++
++ userCommandBufferLogicalMapped = gcvTRUE;
++#endif
++
++ commandBufferSize
++ = commandBufferObject->offset
++ + Command->reservedTail
++ - commandBufferObject->startOffset;
++
++ gcmkONERROR(_FlushMMU(Command));
++
++ /* Get the current offset. */
++ offset = Command->offset;
++
++ /* Compute number of bytes left in current kernel command queue. */
++ bytes = Command->pageSize - offset;
++
++#if gcdMULTI_GPU
++ if (Command->kernel->core == gcvCORE_MAJOR)
++ {
++ commandBufferSize += chipEnableBytes;
++
++ gcmkONERROR(gckHARDWARE_ChipEnable(
++ hardware,
++ commandBufferLogical + pipeBytes,
++ ChipEnable,
++ &chipEnableBytes
++ ));
++
++ gcmkONERROR(gckHARDWARE_ChipEnable(
++ hardware,
++ commandBufferLogical + commandBufferSize - linkBytes - chipEnableBytes,
++ gcvCORE_3D_ALL_MASK,
++ &chipEnableBytes
++ ));
++ }
++ else
++ {
++ commandBufferSize += nopBytes;
++
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ commandBufferLogical + pipeBytes,
++ &nopBytes
++ ));
++
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ commandBufferLogical + commandBufferSize - linkBytes - nopBytes,
++ &nopBytes
++ ));
++ }
++#endif
++
++ /* Query the size of WAIT/LINK command sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ gcvNULL,
++ offset,
++ &waitLinkBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < waitLinkBytes)
++ {
++ /* No, create a new one. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Get the new current offset. */
++ offset = Command->offset;
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - offset;
++ gcmkASSERT(bytes >= waitLinkBytes);
++ }
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + offset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + offset;
++ waitLinkAddress = Command->address + offset;
++
++ /* Context switch required? */
++ if (Context == gcvNULL)
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryAddress = commandBufferAddress + offset;
++ entryBytes = commandBufferSize - offset;
++
++ Command->currContext = gcvNULL;
++ }
++ else if (Command->currContext != Context)
++ {
++ /* Temporary disable context length oprimization. */
++ Context->dirty = gcvTRUE;
++
++ /* Get the current context buffer. */
++ contextBuffer = Context->buffer;
++
++ /* Yes, merge in the deltas. */
++ gcmkONERROR(gckCONTEXT_Update(Context, ProcessID, StateDelta));
++
++ /* Determine context entry and exit points. */
++ if (0)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D and 3D are used.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++
++ /* Mark context as not dirty. */
++ Context->dirty = gcvFALSE;
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 2D only command buffer.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++ /* Not using 2D. */
++ else
++ {
++
++ /* Store the current context buffer. */
++ Context->dirtyBuffer = contextBuffer;
++
++ if (Context->dirty || commandBufferObject->using3D)
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: 3D only command buffer.
++ */
++
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + Context->pipeSelectBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryAddress = contextBuffer->address + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /***************************************************************
++ ** SWITCHING CONTEXT: "XD" command buffer - neither 2D nor 3D.
++ */
++
++ /* Mark 3D as dirty. */
++ Context->dirty3D = gcvTRUE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_3D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom3D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom3D;
++
++ entryAddress
++ = contextBuffer->address
++ + Context->entryOffsetXDFrom3D;
++
++ entryBytes
++ = Context->bufferSize
++ - Context->entryOffsetXDFrom3D;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical
++ = (gctUINT8_PTR) contextBuffer->physical
++ + Context->entryOffsetXDFrom2D;
++#endif
++ entryLogical
++ = (gctUINT8_PTR) contextBuffer->logical
++ + Context->entryOffsetXDFrom2D;
++
++ entryAddress
++ = contextBuffer->address
++ + Context->entryOffsetXDFrom2D;
++
++ entryBytes
++ = Context->totalSize
++ - Context->entryOffsetXDFrom2D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the context buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)entryPhysical,
++ entryLogical,
++ entryBytes
++ ));
++#endif
++
++ /* Update the current context. */
++ Command->currContext = Context;
++
++#if gcdDUMP_COMMAND
++ contextDumpLogical = entryLogical;
++ contextDumpBytes = entryBytes;
++#endif
++
++#if gcdSECURITY
++ /* Commit context buffer to trust zone. */
++ gckKERNEL_SecurityExecute(
++ Command->kernel,
++ entryLogical,
++ entryBytes - 8
++ );
++#endif
++
++#if gcdRECORD_COMMAND
++ gckRECORDER_Record(
++ Command->recorder,
++ gcvNULL,
++ 0xFFFFFFFF,
++ entryLogical,
++ entryBytes - 8
++ );
++#endif
++ }
++
++ /* Same context. */
++ else
++ {
++ /* Determine context entry and exit points. */
++ if (commandBufferObject->using2D && Context->dirty2D)
++ {
++ /* Reset 2D dirty flag. */
++ Context->dirty2D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->bufferSize - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->bufferSize;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Ensure the NOP between 2D and 3D is in place so that the
++ execution falls through from 2D to 3D. */
++ gcmkONERROR(gckHARDWARE_Nop(
++ hardware,
++ contextBuffer->link2D,
++ &nopBytes
++ ));
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* Compute the entry. */
++ if (Command->pipeSelect == gcvPIPE_2D)
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes;
++ entryAddress = contextBuffer->address + pipeBytes;
++ entryBytes = Context->entryOffset3D - pipeBytes;
++ }
++ else
++ {
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical;
++ entryAddress = contextBuffer->address;
++ entryBytes = Context->entryOffset3D;
++ }
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_2D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* 3D is not used, generate a LINK from the end of 2D part of
++ the context buffer to the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link2D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ }
++ else
++ {
++ if (commandBufferObject->using3D && Context->dirty3D)
++ {
++ /* Reset 3D dirty flag. */
++ Context->dirty3D = gcvFALSE;
++
++ /* Get the "dirty" context buffer. */
++ contextBuffer = Context->dirtyBuffer;
++
++ /* Determine context buffer entry offset. */
++ offset = (Command->pipeSelect == gcvPIPE_3D)
++
++ /* Skip pipe switching sequence. */
++ ? Context->entryOffset3D + pipeBytes
++
++ /* Do not skip pipe switching sequence. */
++ : Context->entryOffset3D;
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset;
++#endif
++ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset;
++ entryAddress = contextBuffer->address + offset;
++ entryBytes = Context->bufferSize - offset;
++
++ /* See if we have to switch pipes between the context
++ and command buffers. */
++ if (commandBufferObject->entryPipe == gcvPIPE_3D)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the initial context pipes are
++ different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Generate a LINK from the context buffer to
++ the command buffer. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ contextBuffer->link3D,
++ commandBufferAddress + offset,
++ commandBufferSize - offset,
++ &linkBytes
++ ));
++ }
++ else
++ {
++ /* See if we have to switch pipes for the command buffer. */
++ if (commandBufferObject->entryPipe == Command->pipeSelect)
++ {
++ /* Skip pipe switching sequence. */
++ offset = pipeBytes;
++ }
++ else
++ {
++ /* The current hardware and the entry command buffer pipes
++ ** are different, switch to the correct pipe. */
++ gcmkONERROR(gckHARDWARE_PipeSelect(
++ Command->kernel->hardware,
++ commandBufferLogical,
++ commandBufferObject->entryPipe,
++ &pipeBytes
++ ));
++
++ /* Do not skip pipe switching sequence. */
++ offset = 0;
++ }
++
++ /* Compute the entry. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset;
++#endif
++ entryLogical = commandBufferLogical + offset;
++ entryAddress = commandBufferAddress + offset;
++ entryBytes = commandBufferSize - offset;
++ }
++ }
++ }
++
++#if gcdDUMP_COMMAND
++ bufferDumpLogical = commandBufferLogical + offset;
++ bufferDumpBytes = commandBufferSize - offset;
++#endif
++
++#if gcdSECURE_USER
++ /* Process user hints. */
++ gcmkONERROR(_ProcessHints(Command, ProcessID, commandBufferObject));
++#endif
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = Command->physical;
++#endif
++
++ exitLogical = Command->logical;
++ exitAddress = Command->address;
++ exitBytes = Command->offset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump to the new
++ WAIT/LINK command sequence. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ exitPhysical = waitLinkPhysical;
++#endif
++ exitLogical = waitLinkLogical;
++ exitAddress = waitLinkAddress;
++ exitBytes = waitLinkBytes;
++ }
++
++ /* Add a new WAIT/LINK command sequence. When the command buffer which is
++ currently being scheduled is fully executed by the GPU, the FE will
++ jump to this WAIT/LINK sequence. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ hardware,
++ waitLinkLogical,
++ offset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitSize
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = (gctUINT8_PTR) waitLinkLogical + waitOffset;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command queue cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)exitPhysical,
++ exitLogical,
++ exitBytes
++ ));
++#endif
++
++ /* Determine the location of the LINK command in the command buffer. */
++ commandBufferLink
++ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical)
++ + commandBufferObject->offset;
++
++#ifdef __QNXNTO__
++ userCommandBufferLink = (gctPOINTER) commandBufferLink;
++
++ gcmkONERROR(gckOS_MapUserPointer(
++ Command->os,
++ userCommandBufferLink,
++ 0,
++ &pointer));
++
++ commandBufferLink = pointer;
++
++ userCommandBufferLinkMapped = gcvTRUE;
++#endif
++
++#if gcdMULTI_GPU
++ if (Command->kernel->core == gcvCORE_MAJOR)
++ {
++ commandBufferLink += chipEnableBytes;
++ }
++ else
++ {
++ commandBufferLink += nopBytes;
++ }
++#endif
++
++ /* Generate a LINK from the end of the command buffer being scheduled
++ back to the kernel command queue. */
++#if !gcdSECURITY
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ commandBufferLink,
++ exitAddress,
++ exitBytes,
++ &linkBytes
++ ));
++#endif
++
++#ifdef __QNXNTO__
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os,
++ userCommandBufferLink,
++ 0,
++ commandBufferLink));
++
++ userCommandBufferLinkMapped = gcvFALSE;
++#endif
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the command buffer cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ ProcessID,
++ gcvNULL,
++ (gctUINT32)commandBufferPhysical,
++ commandBufferLogical,
++ commandBufferSize
++ ));
++#endif
++
++#if gcdRECORD_COMMAND
++ gckRECORDER_Record(
++ Command->recorder,
++ commandBufferLogical + offset,
++ commandBufferSize - offset - 8,
++ gcvNULL,
++ 0xFFFFFFFF
++ );
++
++ gckRECORDER_AdvanceIndex(Command->recorder, Command->commitStamp);
++
++ Command->commitStamp++;
++#endif
++
++#if gcdSECURITY
++ /* Submit command buffer to trust zone. */
++ gckKERNEL_SecurityExecute(
++ Command->kernel,
++ commandBufferLogical + offset,
++ commandBufferSize - offset - 8
++ );
++#else
++ /* Generate a LINK from the previous WAIT/LINK command sequence to the
++ entry determined above (either the context or the command buffer).
++ This LINK replaces the WAIT instruction from the previous WAIT/LINK
++ pair, therefore we use WAIT metrics for generation of this LINK.
++ This action will execute the entire sequence. */
++ gcmkONERROR(gckHARDWARE_Link(
++ hardware,
++ Command->waitLogical,
++ entryAddress,
++ entryBytes,
++ &Command->waitSize
++ ));
++#endif
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the link. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ contextDumpLogical,
++ contextDumpBytes,
++ gceDUMP_BUFFER_CONTEXT,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ bufferDumpLogical,
++ bufferDumpBytes,
++ gceDUMP_BUFFER_USER,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ waitLinkLogical,
++ waitLinkBytes,
++ gceDUMP_BUFFER_WAITLINK,
++ gcvFALSE
++ );
++
++ /* Update the current pipe. */
++ Command->pipeSelect = commandBufferObject->exitPipe;
++
++ /* Update command queue offset. */
++ Command->offset += waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update address of last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitSize;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.commit]");
++#endif
++#endif /* gcdNULL_DRIVER */
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ contextAcquired = gcvFALSE;
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ commitEntered = gcvFALSE;
++
++#if VIVANTE_PROFILER_CONTEXT
++ if(sequenceAcquired)
++ {
++#if gcdMULTI_GPU
++ gcmkONERROR(gckCOMMAND_Stall(Command, gcvTRUE, ChipEnable));
++#else
++ gcmkONERROR(gckCOMMAND_Stall(Command, gcvTRUE));
++#endif
++ if (Command->currContext)
++ {
++ gcmkONERROR(gckHARDWARE_UpdateContextProfile(
++ hardware,
++ Command->currContext));
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ sequenceAcquired = gcvFALSE;
++ }
++#endif
++
++ /* Loop while there are records in the queue. */
++ while (EventQueue != gcvNULL)
++ {
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ eventRecord = &_eventRecord;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(
++ Command->os, eventRecord, EventQueue, gcmSIZEOF(gcsQUEUE)
++ ));
++ }
++ else
++ {
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ eventRecord = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(gckEVENT_AddList(
++ Command->kernel->eventObj, &eventRecord->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE
++ ));
++
++ /* Next record in the queue. */
++ nextEventRecord = gcmUINT64_TO_PTR(eventRecord->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os, EventQueue, gcmSIZEOF(gcsQUEUE), (gctPOINTER *) eventRecord
++ ));
++
++ eventRecord = gcvNULL;
++ }
++
++ EventQueue = nextEventRecord;
++ }
++
++ if (Command->kernel->eventObj->queueHead == gcvNULL
++ && Command->kernel->hardware->powerManagement == gcvTRUE
++ )
++ {
++ /* Commit done event by which work thread knows all jobs done. */
++ gcmkVERIFY_OK(
++ gckEVENT_CommitDone(Command->kernel->eventObj, gcvKERNEL_PIXEL));
++ }
++
++ /* Submit events. */
++#if gcdMULTI_GPU
++ status = gckEVENT_Submit(Command->kernel->eventObj, gcvTRUE, gcvFALSE, ChipEnable);
++#else
++ status = gckEVENT_Submit(Command->kernel->eventObj, gcvTRUE, gcvFALSE);
++#endif
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkTRACE(
++ gcvLEVEL_INFO,
++ "%s(%d): Intterupted in gckEVENT_Submit",
++ __FUNCTION__, __LINE__
++ );
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkONERROR(status);
++ }
++
++#ifdef __QNXNTO__
++ if (userCommandBufferLogicalMapped)
++ {
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os,
++ userCommandBufferLogical,
++ 0,
++ commandBufferLogical));
++
++ userCommandBufferLogicalMapped = gcvFALSE;
++ }
++#endif
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++
++ commandBufferMapped = gcvFALSE;
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((eventRecord != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ EventQueue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) eventRecord
++ ));
++ }
++
++ if (contextAcquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Command, gcvFALSE));
++ }
++
++#if VIVANTE_PROFILER_CONTEXT
++ if (sequenceAcquired)
++ {
++ /* Release the context sequence mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq));
++ }
++#endif
++
++#ifdef __QNXNTO__
++ if (userCommandBufferLinkMapped)
++ {
++ gcmkONERROR(gckOS_UnmapUserPointer(
++ Command->os,
++ userCommandBufferLink,
++ 0,
++ commandBufferLink));
++ }
++
++ if (userCommandBufferLogicalMapped)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ userCommandBufferLogical,
++ 0,
++ commandBufferLogical));
++ }
++#endif
++
++ /* Unmap the command buffer pointer. */
++ if (commandBufferMapped)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ CommandBuffer,
++ gcmSIZEOF(struct _gcoCMDBUF),
++ commandBufferObject
++ ));
++ }
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Reserve
++**
++** Reserve space in the command queue. Also acquire the command queue mutex.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** gctPOINTER * Buffer
++** Pointer to a variable that will receive the address of the reserved
++** space.
++**
++** gctSIZE_T * BufferSize
++** Pointer to a variable that will receive the number of bytes
++** available in the command queue.
++*/
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctUINT32 * BufferSize
++ )
++{
++ gceSTATUS status;
++ gctUINT32 bytes;
++ gctUINT32 requiredBytes;
++ gctUINT32 requestedAligned;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute aligned number of reuested bytes. */
++ requestedAligned = gcmALIGN(RequestedBytes, Command->alignment);
++
++ /* Another WAIT/LINK command sequence will have to be appended after
++ the requested area being reserved. Compute the number of bytes
++ required for WAIT/LINK at the location after the reserved area. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ gcvNULL,
++ Command->offset + requestedAligned,
++ &requiredBytes,
++ gcvNULL,
++ gcvNULL
++ ));
++
++ /* Compute total number of bytes required. */
++ requiredBytes += requestedAligned;
++
++ /* Compute number of bytes available in command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Is there enough space in the current command queue? */
++ if (bytes < requiredBytes)
++ {
++ /* Create a new command queue. */
++ gcmkONERROR(_NewQueue(Command));
++
++ /* Recompute the number of bytes in the new kernel command queue. */
++ bytes = Command->pageSize - Command->offset;
++
++ /* Still not enough space? */
++ if (bytes < requiredBytes)
++ {
++ /* Rare case, not enough room in command queue. */
++ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL);
++ }
++ }
++
++ /* Return pointer to empty slot command queue. */
++ *Buffer = (gctUINT8 *) Command->logical + Command->offset;
++
++ /* Return number of bytes left in command queue. */
++ *BufferSize = bytes;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Buffer=0x%x *BufferSize=%lu", *Buffer, *BufferSize);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Execute
++**
++** Execute a previously reserved command queue by appending a WAIT/LINK command
++** sequence after it and modifying the last WAIT into a LINK command. The
++** command FIFO mutex will be released whether this function succeeds or not.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctSIZE_T RequestedBytes
++** Number of bytes previously reserved.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequestedBytes
++ )
++{
++ gceSTATUS status;
++
++ gctPHYS_ADDR waitLinkPhysical;
++ gctUINT8_PTR waitLinkLogical;
++ gctUINT32 waitLinkOffset;
++ gctUINT32 waitLinkBytes;
++
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitOffset;
++ gctUINT32 waitBytes;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gctPHYS_ADDR execPhysical;
++#endif
++ gctPOINTER execLogical;
++ gctUINT32 execAddress;
++ gctUINT32 execBytes;
++
++ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Compute offset for WAIT/LINK. */
++ waitLinkOffset = Command->offset + RequestedBytes;
++
++ /* Compute number of bytes left in command queue. */
++ waitLinkBytes = Command->pageSize - waitLinkOffset;
++
++ /* Compute the location if WAIT/LINK command sequence. */
++ waitLinkPhysical = (gctUINT8_PTR) Command->physical + waitLinkOffset;
++ waitLinkLogical = (gctUINT8_PTR) Command->logical + waitLinkOffset;
++
++ /* Append WAIT/LINK in command queue. */
++ gcmkONERROR(gckHARDWARE_WaitLink(
++ Command->kernel->hardware,
++ waitLinkLogical,
++ waitLinkOffset,
++ &waitLinkBytes,
++ &waitOffset,
++ &waitBytes
++ ));
++
++ /* Compute the location if WAIT command. */
++ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset;
++ waitLogical = waitLinkLogical + waitOffset;
++
++ /* Determine the location to jump to for the command buffer being
++ ** scheduled. */
++ if (Command->newQueue)
++ {
++ /* New command queue, jump to the beginning of it. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = Command->physical;
++#endif
++ execLogical = Command->logical;
++ execAddress = Command->address;
++ execBytes = waitLinkOffset + waitLinkBytes;
++ }
++ else
++ {
++ /* Still within the preexisting command queue, jump directly to the
++ reserved area. */
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ execPhysical = (gctUINT8 *) Command->physical + Command->offset;
++#endif
++ execLogical = (gctUINT8 *) Command->logical + Command->offset;
++ execAddress = Command->address + Command->offset;
++ execBytes = RequestedBytes + waitLinkBytes;
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)execPhysical,
++ execLogical,
++ execBytes
++ ));
++#endif
++
++ /* Convert the last WAIT into a LINK. */
++ gcmkONERROR(gckHARDWARE_Link(
++ Command->kernel->hardware,
++ Command->waitLogical,
++ execAddress,
++ execBytes,
++ &Command->waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Command->os,
++ Command->kernelProcessID,
++ gcvNULL,
++ (gctUINT32)Command->waitPhysical,
++ Command->waitLogical,
++ Command->waitSize
++ ));
++#endif
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ Command->waitLogical,
++ Command->waitSize,
++ gceDUMP_BUFFER_LINK,
++ gcvFALSE
++ );
++
++ gcmkDUMPCOMMAND(
++ Command->os,
++ execLogical,
++ execBytes,
++ gceDUMP_BUFFER_KERNEL,
++ gcvFALSE
++ );
++
++ /* Update the pointer to the last WAIT. */
++ Command->waitPhysical = waitPhysical;
++ Command->waitLogical = waitLogical;
++ Command->waitSize = waitBytes;
++
++ /* Update the command queue. */
++ Command->offset += RequestedBytes + waitLinkBytes;
++ Command->newQueue = gcvFALSE;
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ Command->kernel->hardware, Command->logical, Command->offset
++ ));
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.execute]");
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Stall
++**
++** The calling thread will be suspended until the command queue has been
++** completed.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to an gckCOMMAND object.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++#if gcdMULTI_GPU
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower,
++ IN gceCORE_3D_MASK ChipEnable
++ )
++#else
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ )
++#endif
++{
++#if gcdNULL_DRIVER
++ /* Do nothing with infinite hardware. */
++ return gcvSTATUS_OK;
++#else
++ gckOS os;
++ gckHARDWARE hardware;
++ gckEVENT eventObject;
++ gceSTATUS status;
++ gctSIGNAL signal = gcvNULL;
++ gctUINT timer = 0;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Extract the gckOS object pointer. */
++ os = Command->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Command->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Extract the gckEVENT object pointer. */
++ eventObject = Command->kernel->eventObj;
++ gcmkVERIFY_OBJECT(eventObject, gcvOBJ_EVENT);
++
++ /* Allocate the signal. */
++ gcmkONERROR(gckOS_CreateSignal(os, gcvTRUE, &signal));
++
++ /* Append the EVENT command to trigger the signal. */
++ gcmkONERROR(gckEVENT_Signal(eventObject, signal, gcvKERNEL_PIXEL));
++
++ /* Submit the event queue. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckEVENT_Submit(eventObject, gcvTRUE, FromPower, ChipEnable));
++#else
++ gcmkONERROR(gckEVENT_Submit(eventObject, gcvTRUE, FromPower));
++#endif
++
++#if gcdDUMP_COMMAND
++ gcmkPRINT("@[kernel.stall]");
++#endif
++
++ if (status == gcvSTATUS_CHIP_NOT_READY)
++ {
++ /* Error. */
++ goto OnError;
++ }
++
++ do
++ {
++ /* Wait for the signal. */
++ status = gckOS_WaitSignal(os, signal, gcdGPU_ADVANCETIMER);
++
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT32 idle;
++
++ /* Read idle register. */
++ gcmkVERIFY_OK(gckHARDWARE_GetIdle(
++ hardware, gcvFALSE, &idle
++ ));
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): idle=%08x",
++ __FUNCTION__, __LINE__, idle
++ );
++
++ gcmkVERIFY_OK(gckOS_MemoryBarrier(os, gcvNULL));
++#endif
++
++ /* Advance timer. */
++ timer += gcdGPU_ADVANCETIMER;
++ }
++ else if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkONERROR(gcvSTATUS_INTERRUPTED);
++ }
++
++ }
++ while (gcmIS_ERROR(status));
++
++ /* Bail out on timeout. */
++ if (gcmIS_ERROR(status))
++ {
++ /* Broadcast the stuck GPU. */
++ gcmkONERROR(gckOS_Broadcast(
++ os, hardware, gcvBROADCAST_GPU_STUCK
++ ));
++ }
++
++ /* Delete the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ /* Free the signal. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++#endif
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_Attach
++**
++** Attach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gctUINT32 ProcessID
++** Current process ID.
++**
++** OUTPUT:
++**
++** gckCONTEXT * Context
++** Pointer to a variable that will receive a pointer to a new
++** gckCONTEXT object.
++**
++** gctSIZE_T * StateCount
++** Pointer to a variable that will receive the number of states
++** in the context buffer.
++*/
++#if (gcdENABLE_3D || gcdENABLE_2D)
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Construct(
++ Command->os,
++ Command->kernel->hardware,
++ ProcessID,
++ Context
++ ));
++
++ /* Return the number of states in the context. */
++ * StateCount = (* Context)->stateCount;
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Context=0x%x", *Context);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckCOMMAND_Detach
++**
++** Detach user process.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** gckCONTEXT Context
++** Pointer to a gckCONTEXT object to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x", Command, Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ /* Acquire the context switching mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(
++ Command->os, Command->mutexContext, gcvINFINITE
++ ));
++ acquired = gcvTRUE;
++
++ /* Construct a gckCONTEXT object. */
++ gcmkONERROR(gckCONTEXT_Destroy(Context));
++
++ if (Command->currContext == Context)
++ {
++ /* Detach from gckCOMMAND object if the destoryed context is current context. */
++ Command->currContext = gcvNULL;
++ }
++
++ /* Release the context switching mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release mutex. */
++ if (acquired)
++ {
++ /* Release the context switching mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext));
++ acquired = gcvFALSE;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckCOMMAND_DumpExecutingBuffer
++**
++** Dump the command buffer which GPU is executing.
++**
++** INPUT:
++**
++** gckCOMMAND Command
++** Pointer to a gckCOMMAND object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gctUINT32 gpuAddress;
++ gctSIZE_T pageCount;
++ gctPOINTER entry;
++ gckOS os = Command->os;
++ gckKERNEL kernel = Command->kernel;
++ gctINT pid;
++ gctUINT32 i, rear;
++ gctUINT32 start, end;
++ gctUINT32 dumpFront, dumpRear;
++ gckLINKQUEUE queue = &kernel->hardware->linkQueue;
++ gckLINKQUEUE queueMirror;
++ gctUINT32 bytes;
++ gckLINKDATA linkData;
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("**** COMMAND BUF DUMP ****\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(os, kernel->core, 0x664, &gpuAddress));
++
++ gcmkPRINT("DMA Address 0x%08X", gpuAddress);
++
++ if (Command->kernel->stuckDump > gcdSTUCK_DUMP_MIDDLE)
++ {
++ gcmkPRINT("Dump Level is %d", Command->kernel->stuckDump);
++
++ /* Duplicate queue because it will be changed.*/
++ gcmkONERROR(gckOS_AllocateMemory(os,
++ sizeof(struct _gckLINKQUEUE),
++ (gctPOINTER *)&queueMirror));
++
++ gckOS_MemCopy(queueMirror,
++ queue,
++ sizeof(struct _gckLINKQUEUE));
++
++ /* If kernel command buffer link to a context buffer, then link to a user command
++ ** buffer, the second link will be in queue first, so we must fix this.
++ ** In Queue: C1 U1 U2 C2 U3 U4 U5 C3
++ ** Real: C1 X1 U1 C2 U2 U3 U4 C3 U5
++ ** Command buffer X1 which is after C1 is out of queue, so C1 is meaningless.
++ */
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Can't find it in virtual command buffer list, ignore it. */
++ continue;
++ }
++
++ if (buffer->kernelLogical)
++ {
++ /* It is a context buffer. */
++ if (i == 0)
++ {
++ /* The real command buffer is out, so clear this slot. */
++ linkData->start = 0;
++ linkData->end = 0;
++ linkData->pid = 0;
++ }
++ else
++ {
++ /* switch context buffer and command buffer. */
++ struct _gckLINKDATA tmp = *linkData;
++ gckLINKDATA linkDataPrevious;
++
++ gckLINKQUEUE_GetData(queueMirror, i - 1, &linkDataPrevious);
++ *linkData = *linkDataPrevious;
++ *linkDataPrevious = tmp;
++ }
++ }
++ }
++
++ /* Clear search result. */
++ dumpFront = dumpRear = gcvINFINITE;
++
++ gcmkPRINT("Link Stack:");
++
++ /* Search stuck address in link queue from rear. */
++ rear = gcdLINK_QUEUE_SIZE - 1;
++ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ start = linkData->start;
++ end = linkData->end;
++ pid = linkData->pid;
++
++ if (gpuAddress >= start && gpuAddress < end)
++ {
++ /* Find latest matched command buffer. */
++ gcmkPRINT(" %d, [%08X - %08X]", pid, start, end);
++
++ /* Initiliaze dump information. */
++ dumpFront = dumpRear = rear;
++ }
++
++ /* Advance to previous one. */
++ rear--;
++
++ if (dumpFront != gcvINFINITE)
++ {
++ break;
++ }
++ }
++
++ if (dumpFront == gcvINFINITE)
++ {
++ /* Can't find matched record in link queue, dump kernel command buffer. */
++ _DumpKernelCommandBuffer(Command);
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++ }
++
++ /* Search the last context buffer linked. */
++ while (rear > 0)
++ {
++ gckLINKQUEUE_GetData(queueMirror, rear, &linkData);
++
++ gcmkPRINT(" %d, [%08X - %08X]",
++ linkData->pid,
++ linkData->start,
++ linkData->end);
++
++ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer);
++
++ if (gcmIS_SUCCESS(status) && buffer->kernelLogical)
++ {
++ /* Find a context buffer. */
++ dumpFront = rear;
++ break;
++ }
++
++ rear--;
++ }
++
++ if (dumpFront == dumpRear)
++ {
++ /* No context buffer is found, dump all we got.*/
++ dumpFront = 0;
++ }
++
++ /* Dump from last context buffer to last command buffer where hang happens. */
++ for (i = dumpFront; i <= dumpRear; i++)
++ {
++ gckLINKQUEUE_GetData(queueMirror, i, &linkData);
++
++ /* Get gpu address of this command buffer. */
++ gpuAddress = linkData->start;
++ bytes = linkData->end - gpuAddress;
++
++ /* Get the whole buffer. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkPRINT("Buffer [%08X - %08X] is lost or not belong to current process",
++ linkData->start,
++ linkData->end);
++ continue;
++ }
++
++ /* Get kernel logical for dump. */
++ if (buffer->kernelLogical)
++ {
++ /* Get kernel logical directly if it is a context buffer. */
++ entry = buffer->kernelLogical;
++ gcmkPRINT("Context Buffer:");
++ }
++ else
++ {
++ /* Make it accessiable by kernel if it is a user command buffer. */
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ &entry,
++ &pageCount));
++ gcmkPRINT("User Command Buffer:");
++ }
++
++ /* Dump from the entry. */
++ _DumpBuffer((gctUINT8_PTR)entry + (gpuAddress - buffer->gpuAddress), gpuAddress, bytes);
++
++ /* Release kernel logical address if neccessary. */
++ if (!buffer->kernelLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ entry));
++ }
++ }
++
++ /* Free local copy. */
++ gcmkOS_SAFE_FREE(os, queueMirror);
++ return gcvSTATUS_OK;
++ OnError:
++ return status;
++ }
++ else
++ {
++ gcmkPRINT("Dump Level is %d, dump memory near the stuck address",
++ Command->kernel->stuckDump);
++
++ /* Without link queue information, we don't know the entry of last command
++ ** buffer, just dump the page where GPU stuck. */
++ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CreateKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ &entry,
++ &pageCount));
++
++ if (entry)
++ {
++ gctUINT32 offset = gpuAddress - buffer->gpuAddress;
++ gctPOINTER entryDump = entry;
++
++ /* Dump one pages. */
++ gctUINT32 bytes = 4096;
++
++ /* Align to page. */
++ offset &= 0xfffff000;
++
++ /* Kernel address of page where stall point stay. */
++ entryDump = (gctUINT8_PTR)entryDump + offset;
++
++ /* Align to page. */
++ gpuAddress &= 0xfffff000;
++
++ gcmkPRINT("User Command Buffer:\n");
++ _DumpBuffer(entryDump, gpuAddress, bytes);
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_DestroyKernelVirtualMapping(os,
++ buffer->physical,
++ buffer->bytes,
++ entry));
++ }
++ else
++ {
++ _DumpKernelCommandBuffer(Command);
++ }
++
++ return gcvSTATUS_OK;
++ }
++}
++
++gceSTATUS
++gckCOMMAND_AddressInKernelCommandBuffer(
++ IN gckCOMMAND Command,
++ IN gctUINT32 Address,
++ OUT gctBOOL *In
++ )
++{
++ gctBOOL in = gcvFALSE;
++ gctINT i;
++
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ if ((Address >= Command->queues[i].address)
++ && (Address < (Command->queues[i].address + Command->pageSize))
++ )
++ {
++ in = gcvTRUE;
++ break;
++ }
++ }
++
++ *In = in;
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c 2016-06-19 22:11:55.225145256 +0200
+@@ -0,0 +1,3787 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#include "gc_hal_kernel_hardware_command_vg.h"
++
++#define _GC_OBJ_ZONE gcvZONE_COMMAND
++
++/******************************************************************************\
++*********************************** Debugging **********************************
++\******************************************************************************/
++
++#define gcvDISABLE_TIMEOUT 1
++#define gcvDUMP_COMMAND_BUFFER 0
++#define gcvDUMP_COMMAND_LINES 0
++
++
++#if gcvDEBUG || defined(EMULATOR) || gcvDISABLE_TIMEOUT
++# define gcvQUEUE_TIMEOUT ~0
++#else
++# define gcvQUEUE_TIMEOUT 10
++#endif
++
++
++/******************************************************************************\
++********************************** Definitions *********************************
++\******************************************************************************/
++
++/* Minimum buffer size. */
++#define gcvMINUMUM_BUFFER \
++ gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) + \
++ gcmSIZEOF(gcsKERNEL_CMDQUEUE) * 2
++
++#define gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ static gceSTATUS \
++ _EventHandler_##Block##_##Number( \
++ IN gckVGKERNEL Kernel \
++ )
++
++#define gcmDEFINE_INTERRUPT_HANDLER(Block, Number) \
++ gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \
++ { \
++ return _EventHandler_Block( \
++ Kernel, \
++ &Kernel->command->taskTable[gcvBLOCK_##Block], \
++ gcvFALSE \
++ ); \
++ }
++
++#define gcmDEFINE_INTERRUPT_HANDLER_ENTRY(Block, Number) \
++ { gcvBLOCK_##Block, _EventHandler_##Block##_##Number }
++
++/* Block interrupt handling table entry. */
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER * gcsBLOCK_INTERRUPT_HANDLER_PTR;
++typedef struct _gcsBLOCK_INTERRUPT_HANDLER
++{
++ gceBLOCK block;
++ gctINTERRUPT_HANDLER handler;
++}
++gcsBLOCK_INTERRUPT_HANDLER;
++
++/* Queue control functions. */
++typedef struct _gcsQUEUE_UPDATE_CONTROL * gcsQUEUE_UPDATE_CONTROL_PTR;
++typedef struct _gcsQUEUE_UPDATE_CONTROL
++{
++ gctOBJECT_HANDLER execute;
++ gctOBJECT_HANDLER update;
++ gctOBJECT_HANDLER lastExecute;
++ gctOBJECT_HANDLER lastUpdate;
++}
++gcsQUEUE_UPDATE_CONTROL;
++
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++static gceSTATUS
++_FlushMMU(
++ IN gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status;
++ gctUINT32 oldValue;
++ gckVGHARDWARE hardware = Command->hardware;
++
++ gcmkONERROR(gckOS_AtomicExchange(Command->os,
++ hardware->pageTableDirty,
++ 0,
++ &oldValue));
++
++ if (oldValue)
++ {
++ /* Page Table is upated, flush mmu before commit. */
++ gcmkONERROR(gckVGHARDWARE_FlushMMU(hardware));
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++static gceSTATUS
++_WaitForIdle(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctUINT32 idle;
++ gctUINT timeout = 0;
++
++ /* Loop while not idle. */
++ while (Queue->pending)
++ {
++ /* Did we reach the timeout limit? */
++ if (timeout == gcvQUEUE_TIMEOUT)
++ {
++ /* Hardware is probably dead... */
++ return gcvSTATUS_TIMEOUT;
++ }
++
++ /* Sleep for 100ms. */
++ gcmkERR_BREAK(gckOS_Delay(Command->os, 100));
++
++ /* Not the first loop? */
++ if (timeout > 0)
++ {
++ /* Read IDLE register. */
++ gcmkVERIFY_OK(gckVGHARDWARE_GetIdle(Command->hardware, &idle));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_COMMAND,
++ "%s: timeout, IDLE=%08X\n",
++ __FUNCTION__, idle
++ );
++ }
++
++ /* Increment the timeout counter. */
++ timeout += 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gctINT32
++_GetNextInterrupt(
++ IN gckVGCOMMAND Command,
++ IN gceBLOCK Block
++ )
++{
++ gctUINT index;
++ gcsBLOCK_TASK_ENTRY_PTR entry;
++ gctINT32 interrupt;
++
++ /* Get the block entry. */
++ entry = &Command->taskTable[Block];
++
++ /* Make sure we have initialized interrupts. */
++ gcmkASSERT(entry->interruptCount > 0);
++
++ /* Decrement the interrupt usage semaphore. */
++ gcmkVERIFY_OK(gckOS_DecrementSemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++
++ /* Get the value index. */
++ index = entry->interruptIndex;
++
++ /* Get the interrupt value. */
++ interrupt = entry->interruptArray[index];
++
++ /* Must be a valid value. */
++ gcmkASSERT((interrupt >= 0) && (interrupt <= 31));
++
++ /* Advance the index to the next value. */
++ index += 1;
++
++ /* Set the new index. */
++ entry->interruptIndex = (index == entry->interruptCount)
++ ? 0
++ : index;
++
++ /* Return interrupt value. */
++ return interrupt;
++}
++
++
++/******************************************************************************\
++***************************** Task Storage Management **************************
++\******************************************************************************/
++
++/* Minimum task buffer size. */
++#define gcvMIN_TASK_BUFFER \
++( \
++ gcmSIZEOF(gcsTASK_CONTAINER) + 128 \
++)
++
++/* Free list terminator. */
++#define gcvFREE_TASK_TERMINATOR \
++( \
++ (gcsTASK_CONTAINER_PTR) gcmINT2PTR(~0) \
++)
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------- Allocated Task Buffer List Management ------------------*/
++
++static void
++_InsertTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR AddAfter,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR addBefore;
++
++ /* Cannot add before the first buffer. */
++ gcmkASSERT(AddAfter != gcvNULL);
++
++ /* Create a shortcut to the next buffer. */
++ addBefore = AddAfter->allocNext;
++
++ /* Initialize the links. */
++ Buffer->allocPrev = AddAfter;
++ Buffer->allocNext = addBefore;
++
++ /* Link to the previous buffer. */
++ AddAfter->allocNext = Buffer;
++
++ /* Link to the next buffer. */
++ if (addBefore != gcvNULL)
++ {
++ addBefore->allocPrev = Buffer;
++ }
++}
++
++static void
++_RemoveTaskBuffer(
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++
++ /* Cannot remove the first buffer. */
++ gcmkASSERT(Buffer->allocPrev != gcvNULL);
++
++ /* Create shortcuts to the previous and next buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Tail buffer? */
++ if (next == gcvNULL)
++ {
++ /* Remove from the list. */
++ prev->allocNext = gcvNULL;
++ }
++
++ /* Buffer from the middle. */
++ else
++ {
++ prev->allocNext = next;
++ next->allocPrev = prev;
++ }
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*--------------------- Free Task Buffer List Management ---------------------*/
++
++static void
++_AppendToFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Cannot be a part of the free list already. */
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* First buffer to add? */
++ if (Command->taskFreeHead == gcvNULL)
++ {
++ /* Terminate the links. */
++ Buffer->freePrev = gcvFREE_TASK_TERMINATOR;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Initialize the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = Buffer;
++ }
++
++ /* Not the first, add after the tail. */
++ else
++ {
++ /* Initialize the new tail buffer. */
++ Buffer->freePrev = Command->taskFreeTail;
++ Buffer->freeNext = gcvFREE_TASK_TERMINATOR;
++
++ /* Add after the tail. */
++ Command->taskFreeTail->freeNext = Buffer;
++ Command->taskFreeTail = Buffer;
++ }
++}
++
++static void
++_RemoveFromFreeList(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ /* Has to be a part of the free list. */
++ gcmkASSERT(Buffer->freePrev != gcvNULL);
++ gcmkASSERT(Buffer->freeNext != gcvNULL);
++
++ /* Head buffer? */
++ if (Buffer->freePrev == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Tail buffer as well? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Reset the list pointer. */
++ Command->taskFreeHead = Command->taskFreeTail = gcvNULL;
++ }
++
++ /* No, just the head. */
++ else
++ {
++ /* Update the head. */
++ Command->taskFreeHead = Buffer->freeNext;
++
++ /* Terminate the next buffer. */
++ Command->taskFreeHead->freePrev = gcvFREE_TASK_TERMINATOR;
++ }
++ }
++
++ /* Not the head. */
++ else
++ {
++ /* Tail buffer? */
++ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR)
++ {
++ /* Update the tail. */
++ Command->taskFreeTail = Buffer->freePrev;
++
++ /* Terminate the previous buffer. */
++ Command->taskFreeTail->freeNext = gcvFREE_TASK_TERMINATOR;
++ }
++
++ /* A buffer in the middle. */
++ else
++ {
++ /* Remove the buffer from the list. */
++ Buffer->freePrev->freeNext = Buffer->freeNext;
++ Buffer->freeNext->freePrev = Buffer->freePrev;
++ }
++ }
++
++ /* Reset free list pointers. */
++ Buffer->freePrev = gcvNULL;
++ Buffer->freeNext = gcvNULL;
++}
++
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- Task Buffer Allocation --------------------------*/
++
++static void
++_SplitTaskBuffer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer,
++ IN gctUINT Size
++ )
++{
++ /* Determine the size of the new buffer. */
++ gctINT splitBufferSize = Buffer->size - Size;
++ gcmkASSERT(splitBufferSize >= 0);
++
++ /* Is the split buffer big enough to become a separate buffer? */
++ if (splitBufferSize >= gcvMIN_TASK_BUFFER)
++ {
++ /* Place the new path data. */
++ gcsTASK_CONTAINER_PTR splitBuffer = (gcsTASK_CONTAINER_PTR)
++ (
++ (gctUINT8_PTR) Buffer + Size
++ );
++
++ /* Set the trimmed buffer size. */
++ Buffer->size = Size;
++
++ /* Initialize the split buffer. */
++ splitBuffer->referenceCount = 0;
++ splitBuffer->size = splitBufferSize;
++ splitBuffer->freePrev = gcvNULL;
++ splitBuffer->freeNext = gcvNULL;
++
++ /* Link in. */
++ _InsertTaskBuffer(Buffer, splitBuffer);
++ _AppendToFreeList(Command, splitBuffer);
++ }
++}
++
++static gceSTATUS
++_AllocateTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ OUT gcsTASK_CONTAINER_PTR * Buffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x, Buffer ==0x%x", Command, Size, Buffer);
++
++ /* Verify arguments. */
++ gcmkVERIFY_ARGUMENT(Buffer != gcvNULL);
++
++ do
++ {
++ gcsTASK_STORAGE_PTR storage;
++ gcsTASK_CONTAINER_PTR buffer;
++
++ /* Adjust the size. */
++ Size += gcmSIZEOF(gcsTASK_CONTAINER);
++
++ /* Adjust the allocation size if not big enough. */
++ if (Size > Command->taskStorageUsable)
++ {
++ Command->taskStorageGranularity
++ = gcmALIGN(Size + gcmSIZEOF(gcsTASK_STORAGE), 1024);
++
++ Command->taskStorageUsable
++ = Command->taskStorageGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++ }
++
++ /* Is there a free buffer available? */
++ else if (Command->taskFreeHead != gcvNULL)
++ {
++ /* Set the initial free buffer. */
++ gcsTASK_CONTAINER_PTR buffer = Command->taskFreeHead;
++
++ do
++ {
++ /* Is the buffer big enough? */
++ if (buffer->size >= Size)
++ {
++ /* Remove the buffer from the free list. */
++ _RemoveFromFreeList(Command, buffer);
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++
++ /* Get the next free buffer. */
++ buffer = buffer->freeNext;
++ }
++ while (buffer != gcvFREE_TASK_TERMINATOR);
++ }
++
++ /* Allocate a container. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Command->os,
++ Command->taskStorageGranularity,
++ (gctPOINTER *) &storage
++ ));
++
++ /* Link in the storage buffer. */
++ storage->next = Command->taskStorage;
++ Command->taskStorage = storage;
++
++ /* Place the task buffer. */
++ buffer = (gcsTASK_CONTAINER_PTR) (storage + 1);
++
++ /* Determine the size of the buffer. */
++ buffer->size
++ = Command->taskStorageGranularity
++ - gcmSIZEOF(gcsTASK_STORAGE);
++
++ /* Initialize the task buffer. */
++ buffer->referenceCount = 0;
++ buffer->allocPrev = gcvNULL;
++ buffer->allocNext = gcvNULL;
++ buffer->freePrev = gcvNULL;
++ buffer->freeNext = gcvNULL;
++
++ /* Split the buffer. */
++ _SplitTaskBuffer(Command, buffer, Size);
++
++ /* Set the result. */
++ * Buffer = buffer;
++
++ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++static void
++_FreeTaskContainer(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_CONTAINER_PTR Buffer
++ )
++{
++ gcsTASK_CONTAINER_PTR prev;
++ gcsTASK_CONTAINER_PTR next;
++ gcsTASK_CONTAINER_PTR merged;
++
++ gctUINT32 mergedSize;
++
++ /* Verify arguments. */
++ gcmkASSERT(Buffer != gcvNULL);
++ gcmkASSERT(Buffer->freePrev == gcvNULL);
++ gcmkASSERT(Buffer->freeNext == gcvNULL);
++
++ /* Get shortcuts to the previous and next path data buffers. */
++ prev = Buffer->allocPrev;
++ next = Buffer->allocNext;
++
++ /* Is the previous path data buffer already free? */
++ if (prev && prev->freeNext)
++ {
++ /* The previous path data buffer is the one that remains. */
++ merged = prev;
++
++ /* Is the next path data buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge all three path data buffers into the previous. */
++ mergedSize = prev->size + Buffer->size + next->size;
++
++ /* Remove the next path data buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++ }
++ else
++ {
++ /* Merge the current path data buffer into the previous. */
++ mergedSize = prev->size + Buffer->size;
++ }
++
++ /* Delete the current path data buffer. */
++ _RemoveTaskBuffer(Buffer);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++ else
++ {
++ /* The current path data buffer is the one that remains. */
++ merged = Buffer;
++
++ /* Is the next buffer already free? */
++ if (next && next->freeNext)
++ {
++ /* Merge the next into the current. */
++ mergedSize = Buffer->size + next->size;
++
++ /* Remove the next buffer. */
++ _RemoveFromFreeList(Command, next);
++ _RemoveTaskBuffer(next);
++
++ /* Set new size. */
++ merged->size = mergedSize;
++ }
++
++ /* Add the current buffer into the free list. */
++ _AppendToFreeList(Command, merged);
++ }
++}
++
++gceSTATUS
++_RemoveRecordFromProcesDB(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_HEADER_PTR Task
++ )
++{
++ gceSTATUS status;
++ gcsTASK_PTR task = (gcsTASK_PTR)((gctUINT8_PTR)Task - sizeof(gcsTASK));
++ gcsTASK_FREE_VIDEO_MEMORY_PTR freeVideoMemory;
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR unlockVideoMemory;
++ gctINT pid;
++ gctUINT32 size;
++ gctUINT32 handle;
++ gckKERNEL kernel = Command->kernel->kernel;
++ gckVIDMEM_NODE unlockNode = gcvNULL;
++ gckVIDMEM_NODE nodeObject = gcvNULL;
++ gceDATABASE_TYPE type;
++
++ /* Get the total size of all tasks. */
++ size = task->size;
++
++ gcmkVERIFY_OK(gckOS_GetProcessID((gctUINT32_PTR)&pid));
++
++ do
++ {
++ switch (Task->id)
++ {
++ case gcvTASK_FREE_VIDEO_MEMORY:
++ freeVideoMemory = (gcsTASK_FREE_VIDEO_MEMORY_PTR)Task;
++
++ handle = (gctUINT32)freeVideoMemory->node;
++
++ status = gckVIDMEM_HANDLE_Lookup(
++ Command->kernel->kernel,
++ pid,
++ handle,
++ &nodeObject);
++
++ if (gcmIS_ERROR(status))
++ {
++ return status;
++ }
++
++ gckVIDMEM_HANDLE_Dereference(kernel, pid, handle);
++ freeVideoMemory->node = gcmALL_TO_UINT32(nodeObject);
++
++ type = gcvDB_VIDEO_MEMORY
++ | (nodeObject->type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT)
++ | (nodeObject->pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT);
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ type,
++ gcmINT2PTR(handle)));
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_FREE_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(freeVideoMemory + 1);
++
++ break;
++ case gcvTASK_UNLOCK_VIDEO_MEMORY:
++ unlockVideoMemory = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR)Task;
++
++ /* Remove record from process db. */
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Command->kernel->kernel,
++ pid,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(unlockVideoMemory->node)));
++
++ handle = (gctUINT32)unlockVideoMemory->node;
++
++ status = gckVIDMEM_HANDLE_Lookup(
++ Command->kernel->kernel,
++ pid,
++ handle,
++ &unlockNode);
++
++ if (gcmIS_ERROR(status))
++ {
++ return status;
++ }
++
++ gckVIDMEM_HANDLE_Dereference(kernel, pid, handle);
++ unlockVideoMemory->node = gcmPTR_TO_UINT64(unlockNode);
++
++ /* Advance to next task. */
++ size -= sizeof(gcsTASK_UNLOCK_VIDEO_MEMORY);
++ Task = (gcsTASK_HEADER_PTR)(unlockVideoMemory + 1);
++
++ break;
++ default:
++ /* Skip the whole task. */
++ size = 0;
++ break;
++ }
++ }
++ while(size);
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++********************************* Task Scheduling ******************************
++\******************************************************************************/
++
++static gceSTATUS
++_ScheduleTasks(
++ IN gckVGCOMMAND Command,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable,
++ IN gctUINT8_PTR PreviousEnd
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gctINT block;
++ gcsTASK_CONTAINER_PTR container;
++ gcsTASK_MASTER_ENTRY_PTR userTaskEntry;
++ gcsBLOCK_TASK_ENTRY_PTR kernelTaskEntry;
++ gcsTASK_PTR userTask;
++ gctUINT8_PTR kernelTask;
++ gctINT32 interrupt;
++ gctUINT8_PTR eventCommand;
++
++#ifdef __QNXNTO__
++ gcsTASK_PTR oldUserTask = gcvNULL;
++ gctPOINTER pointer;
++#endif
++
++ /* Nothing to schedule? */
++ if (TaskTable->size == 0)
++ {
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->taskMutex,
++ gcvINFINITE
++ ));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ do
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " number of tasks scheduled = %d\n"
++ " size of event data in bytes = %d\n",
++ TaskTable->count,
++ TaskTable->size
++ );
++
++ /* Allocate task buffer. */
++ gcmkERR_BREAK(_AllocateTaskContainer(
++ Command,
++ TaskTable->size,
++ &container
++ ));
++
++ /* Determine the task data pointer. */
++ kernelTask = (gctUINT8_PTR) (container + 1);
++
++ /* Initialize the reference count. */
++ container->referenceCount = TaskTable->count;
++
++ /* Process tasks. */
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " processing tasks for block %d\n",
++ block
++ );
++
++ /* Get the current kernel table entry. */
++ kernelTaskEntry = &Command->taskTable[block];
++
++ /* Are there tasks for the current block scheduled? */
++ if (kernelTaskEntry->container == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " first task container for the block added\n",
++ block
++ );
++
++ /* Nothing yet, set the container buffer pointer. */
++ kernelTaskEntry->container = container;
++ kernelTaskEntry->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Yes, append to the end. */
++ else
++ {
++ kernelTaskEntry->link->cotainer = container;
++ kernelTaskEntry->link->task = (gcsTASK_HEADER_PTR) kernelTask;
++ }
++
++ /* Set initial task. */
++ userTask = userTaskEntry->head;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " copying user tasks over to the kernel\n"
++ );
++
++ /* Copy tasks. */
++ do
++ {
++ gcsTASK_HEADER_PTR taskHeader;
++
++#ifdef __QNXNTO__
++ oldUserTask = userTask;
++
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ oldUserTask,
++ 0,
++ &pointer));
++
++ userTask = pointer;
++#endif
++
++ taskHeader = (gcsTASK_HEADER_PTR) (userTask + 1);
++
++ gcmkVERIFY_OK(_RemoveRecordFromProcesDB(Command, taskHeader));
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " task ID = %d, size = %d\n",
++ ((gcsTASK_HEADER_PTR) (userTask + 1))->id,
++ userTask->size
++ );
++
++#ifdef __QNXNTO__
++ if (taskHeader->id == gcvTASK_SIGNAL)
++ {
++ ((gcsTASK_SIGNAL_PTR)taskHeader)->coid = TaskTable->coid;
++ ((gcsTASK_SIGNAL_PTR)taskHeader)->rcvid = TaskTable->rcvid;
++ }
++#endif
++
++ /* Copy the task data. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ kernelTask, taskHeader, userTask->size
++ ));
++
++ /* Advance to the next task. */
++ kernelTask += userTask->size;
++ userTask = userTask->next;
++
++#ifdef __QNXNTO__
++ gcmkERR_BREAK(gckOS_UnmapUserPointer(
++ Command->os,
++ oldUserTask,
++ 0,
++ pointer));
++#endif
++ }
++ while (userTask != gcvNULL);
++
++ /* Update link pointer in the header. */
++ kernelTaskEntry->link = (gcsTASK_LINK_PTR) kernelTask;
++
++ /* Initialize link task. */
++ kernelTaskEntry->link->id = gcvTASK_LINK;
++ kernelTaskEntry->link->cotainer = gcvNULL;
++ kernelTaskEntry->link->task = gcvNULL;
++
++ /* Advance the task data pointer. */
++ kernelTask += gcmSIZEOF(gcsTASK_LINK);
++ }
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->taskMutex
++ ));
++
++ /* Assign interrupts to the blocks. */
++ eventCommand = PreviousEnd;
++
++ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1)
++ {
++ /* Get the current user table entry. */
++ userTaskEntry = &TaskTable->table[block];
++
++ /* Are there tasks scheduled? */
++ if (userTaskEntry->head == gcvNULL)
++ {
++ /* No, skip to the next block. */
++ continue;
++ }
++
++ /* Get the interrupt number. */
++ interrupt = _GetNextInterrupt(Command, block);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): block = %d interrupt = %d\n",
++ __FUNCTION__, __LINE__,
++ block, interrupt
++ );
++
++ /* Determine the command position. */
++ eventCommand -= Command->info.eventCommandSize;
++
++ /* Append an EVENT command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EventCommand(
++ Command, eventCommand, block, interrupt, gcvNULL
++ ));
++ }
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************** Memory Management *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_HardwareToKernel(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM memory;
++ gctUINT32 offset;
++ gctUINT32 nodePhysical;
++ gctPOINTER *logical;
++ gctSIZE_T bytes;
++ status = gcvSTATUS_OK;
++
++ memory = Node->VidMem.memory;
++
++ if (memory->object.type == gcvOBJ_VIDMEM)
++ {
++ nodePhysical = memory->baseAddress
++ + (gctUINT32)Node->VidMem.offset
++ + Node->VidMem.alignment;
++ bytes = Node->VidMem.bytes;
++ logical = &Node->VidMem.kernelVirtual;
++ }
++ else
++ {
++ nodePhysical = Node->Virtual.physicalAddress;
++ bytes = Node->Virtual.bytes;
++ logical = &Node->Virtual.kernelVirtual;
++ }
++
++ if (*logical == gcvNULL)
++ {
++ status = gckOS_MapPhysical(Os, nodePhysical, bytes, logical);
++
++ if (gcmkIS_ERROR(status))
++ {
++ return status;
++ }
++ }
++
++ offset = Address - nodePhysical;
++ *KernelPointer = (gctPOINTER)((gctUINT8_PTR)(*logical) + offset);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_ConvertUserCommandBufferPointer(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR UserCommandBuffer,
++ OUT gcsCMDBUFFER_PTR * KernelCommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcsCMDBUFFER_PTR mappedUserCommandBuffer = gcvNULL;
++ gckKERNEL kernel = Command->kernel->kernel;
++ gctUINT32 pid;
++ gckVIDMEM_NODE node;
++
++ gckOS_GetProcessID(&pid);
++
++ do
++ {
++ gctUINT32 headerAddress;
++
++ /* Map the command buffer structure into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ (gctPOINTER *) &mappedUserCommandBuffer
++ ));
++
++ /* Determine the address of the header. */
++ headerAddress
++ = mappedUserCommandBuffer->address
++ - mappedUserCommandBuffer->bufferOffset;
++
++ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(
++ kernel,
++ pid,
++ gcmPTR2INT32(mappedUserCommandBuffer->node),
++ &node));
++
++ /* Translate the logical address to the kernel space. */
++ gcmkERR_BREAK(_HardwareToKernel(
++ Command->os,
++ node->node,
++ headerAddress,
++ (gctPOINTER *) KernelCommandBuffer
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Unmap the user command buffer. */
++ if (mappedUserCommandBuffer != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_UnmapUserPointer(
++ Command->os,
++ UserCommandBuffer,
++ gcmSIZEOF(gcsCMDBUFFER),
++ mappedUserCommandBuffer
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_AllocateLinear(
++ IN gckVGCOMMAND Command,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gcuVIDMEM_NODE_PTR * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status, last;
++ gctPOINTER logical;
++ gctPHYS_ADDR physical;
++ gctUINT32 address;
++ gctSIZE_T size = Size;
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Command->os,
++ gcvFALSE,
++ &size,
++ &physical,
++ &logical
++ ));
++
++ gcmkERR_BREAK(gckOS_GetPhysicalAddress(Command->os, logical, &address));
++
++ /* Set return values. */
++ * Node = physical;
++ * Address = address;
++ * Logical = logical;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (physical != gcvNULL)
++ {
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(gckOS_FreeContiguous(Command->os, physical, logical, size));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeLinear(
++ IN gckVGKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctPOINTER Logical
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ do
++ {
++ gcmkERR_BREAK(gckOS_FreeContiguous(Kernel->os, Node, Logical, 1));
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++_AllocateCommandBuffer(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer
++ )
++{
++ gceSTATUS status, last;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gcsCMDBUFFER_PTR commandBuffer = gcvNULL;
++
++ do
++ {
++ gctUINT alignedHeaderSize;
++ gctUINT requestedSize;
++ gctUINT allocationSize;
++ gctUINT32 address = 0;
++ gctUINT8_PTR endCommand;
++
++ /* Determine the aligned header size. */
++ alignedHeaderSize
++ = (gctUINT32)gcmALIGN(gcmSIZEOF(gcsCMDBUFFER), Command->info.addressAlignment);
++
++ /* Align the requested size. */
++ requestedSize
++ = (gctUINT32)gcmALIGN(Size, Command->info.commandAlignment);
++
++ /* Determine the size of the buffer to allocate. */
++ allocationSize
++ = alignedHeaderSize
++ + requestedSize
++ + (gctUINT32)Command->info.staticTailSize;
++
++ /* Allocate the command buffer. */
++ gcmkERR_BREAK(_AllocateLinear(
++ Command,
++ allocationSize,
++ Command->info.addressAlignment,
++ &node,
++ &address,
++ (gctPOINTER *) &commandBuffer
++ ));
++
++ /* Initialize the structure. */
++ commandBuffer->completion = gcvVACANT_BUFFER;
++ commandBuffer->node = node;
++ commandBuffer->address = address + alignedHeaderSize;
++ commandBuffer->bufferOffset = alignedHeaderSize;
++ commandBuffer->size = requestedSize;
++ commandBuffer->offset = requestedSize;
++ commandBuffer->nextAllocated = gcvNULL;
++ commandBuffer->nextSubBuffer = gcvNULL;
++
++ /* Determine the data count. */
++ commandBuffer->dataCount
++ = (requestedSize + Command->info.staticTailSize)
++ / Command->info.commandAlignment;
++
++ /* Determine the location of the END command. */
++ endCommand
++ = (gctUINT8_PTR) commandBuffer
++ + alignedHeaderSize
++ + requestedSize;
++
++ /* Append an END command. */
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ endCommand,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++
++ /* Set the return pointer. */
++ * CommandBuffer = commandBuffer;
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Free the command buffer. */
++ gcmkCHECK_STATUS(_FreeLinear(Command->kernel, node, commandBuffer));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_FreeCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ /* Free the buffer. */
++ status = _FreeLinear(Kernel, CommandBuffer->node, CommandBuffer);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++****************************** TS Overflow Handler *****************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_TSOverflow(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** TS OVERFLOW ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++
++/******************************************************************************\
++****************************** Bus Error Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_BusError(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): **** BUS ERROR ENCOUNTERED ****\n",
++ __FUNCTION__, __LINE__
++ );
++
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************\
++****************************** Power Stall Handler *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_PowerStall(
++ IN gckVGKERNEL Kernel
++ )
++{
++ /* Signal. */
++ return gckOS_Signal(
++ Kernel->os,
++ Kernel->command->powerStallSignal,
++ gcvTRUE);
++}
++
++/******************************************************************************\
++******************************** Task Routines *********************************
++\******************************************************************************/
++
++typedef gceSTATUS (* gctTASKROUTINE) (
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ );
++
++static gctTASKROUTINE _taskRoutine[] =
++{
++ _TaskLink, /* gcvTASK_LINK */
++ _TaskCluster, /* gcvTASK_CLUSTER */
++ _TaskIncrement, /* gcvTASK_INCREMENT */
++ _TaskDecrement, /* gcvTASK_DECREMENT */
++ _TaskSignal, /* gcvTASK_SIGNAL */
++ _TaskLockdown, /* gcvTASK_LOCKDOWN */
++ _TaskUnlockVideoMemory, /* gcvTASK_UNLOCK_VIDEO_MEMORY */
++ _TaskFreeVideoMemory, /* gcvTASK_FREE_VIDEO_MEMORY */
++ _TaskFreeContiguousMemory, /* gcvTASK_FREE_CONTIGUOUS_MEMORY */
++ _TaskUnmapUserMemory, /* gcvTASK_UNMAP_USER_MEMORY */
++};
++
++static gceSTATUS
++_TaskLink(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ /* Cast the task pointer. */
++ gcsTASK_LINK_PTR task = (gcsTASK_LINK_PTR) TaskHeader->task;
++
++ /* Save the pointer to the container. */
++ gcsTASK_CONTAINER_PTR container = TaskHeader->container;
++
++ /* No more tasks in the list? */
++ if (task->task == gcvNULL)
++ {
++ /* Reset the entry. */
++ TaskHeader->container = gcvNULL;
++ TaskHeader->task = gcvNULL;
++ TaskHeader->link = gcvNULL;
++ }
++ else
++ {
++ /* Update the entry. */
++ TaskHeader->container = task->cotainer;
++ TaskHeader->task = task->task;
++ }
++
++ /* Decrement the task buffer reference. */
++ gcmkASSERT(container->referenceCount >= 0);
++ if (container->referenceCount == 0)
++ {
++ /* Free the container. */
++ _FreeTaskContainer(Command, container);
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_TaskCluster(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ /* Cast the task pointer. */
++ gcsTASK_CLUSTER_PTR cluster = (gcsTASK_CLUSTER_PTR) TaskHeader->task;
++
++ /* Get the number of tasks. */
++ gctUINT taskCount = cluster->taskCount;
++
++ /* Advance to the next task. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (cluster + 1);
++
++ /* Perform all tasks in the cluster. */
++ while (taskCount)
++ {
++ /* Perform the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ Command,
++ TaskHeader
++ ));
++
++ /* Update the task count. */
++ taskCount -= 1;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskIncrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_INCREMENT_PTR task = (gcsTASK_INCREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Increment data. */
++ (* logical) += 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskDecrement(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_DECREMENT_PTR task = (gcsTASK_DECREMENT_PTR) TaskHeader->task;
++
++ /* Convert physical into logical address. */
++ gctUINT32_PTR logical;
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->address,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &logical
++ ));
++
++ /* Decrement data. */
++ (* logical) -= 1;
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(gckOS_UnmapPhysical(
++ Command->os,
++ logical,
++ gcmSIZEOF(gctUINT32)
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskSignal(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_SIGNAL_PTR task = (gcsTASK_SIGNAL_PTR) TaskHeader->task;
++
++
++ /* Map the signal into kernel space. */
++#ifdef __QNXNTO__
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, task->signal, task->rcvid, task->coid
++ ));
++#else
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, task->signal, task->process
++ ));
++#endif /* __QNXNTO__ */
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskLockdown(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR userCounter = gcvNULL;
++ gctUINT32_PTR kernelCounter = gcvNULL;
++ gctSIGNAL signal = gcvNULL;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_LOCKDOWN_PTR task = (gcsTASK_LOCKDOWN_PTR) TaskHeader->task;
++
++ /* Convert physical addresses into logical. */
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->userCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &userCounter
++ ));
++
++ gcmkERR_BREAK(gckOS_MapPhysical(
++ Command->os,
++ task->kernelCounter,
++ gcmSIZEOF(gctUINT32),
++ (gctPOINTER *) &kernelCounter
++ ));
++
++ /* Update the kernel counter. */
++ (* kernelCounter) += 1;
++
++ /* Are the counters equal? */
++ if ((* userCounter) == (* kernelCounter))
++ {
++ /* Map the signal into kernel space. */
++ gcmkERR_BREAK(gckOS_MapSignal(
++ Command->os, task->signal, task->process, &signal
++ ));
++
++ if (signal == gcvNULL)
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, task->signal, gcvTRUE
++ ));
++ }
++ else
++ {
++ /* Signal. */
++ gcmkERR_BREAK(gckOS_Signal(
++ Command->os, signal, gcvTRUE
++ ));
++ }
++ }
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Destroy the mapped signal. */
++ if (signal != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Command->os, signal
++ ));
++ }
++
++ /* Unmap the physical memory. */
++ if (kernelCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ kernelCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ if (userCounter != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapPhysical(
++ Command->os,
++ userCounter,
++ gcmSIZEOF(gctUINT32)
++ ));
++ }
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnlockVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR task
++ = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Unlock video memory. */
++ gcmkERR_BREAK(gckVIDMEM_Unlock(
++ Command->kernel->kernel,
++ (gckVIDMEM_NODE)gcmUINT64_TO_PTR(task->node),
++ gcvSURF_TYPE_UNKNOWN,
++ gcvNULL));
++
++ gcmkERR_BREAK(gckVIDMEM_NODE_Dereference(
++ Command->kernel->kernel,
++ gcmUINT64_TO_PTR(task->node)));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeVideoMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_VIDEO_MEMORY_PTR task
++ = (gcsTASK_FREE_VIDEO_MEMORY_PTR) TaskHeader->task;
++
++ /* Free video memory. */
++ gcmkERR_BREAK(gckVIDMEM_NODE_Dereference(
++ Command->kernel->kernel,
++ gcmINT2PTR(task->node)));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskFreeContiguousMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR task
++ = (gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR) TaskHeader->task;
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Command->os, task->physical, task->logical, task->bytes
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_TaskUnmapUserMemory(
++ gckVGCOMMAND Command,
++ gcsBLOCK_TASK_ENTRY_PTR TaskHeader
++ )
++{
++ gceSTATUS status;
++ gctPOINTER info;
++
++ do
++ {
++ /* Cast the task pointer. */
++ gcsTASK_UNMAP_USER_MEMORY_PTR task
++ = (gcsTASK_UNMAP_USER_MEMORY_PTR) TaskHeader->task;
++
++ info = gckKERNEL_QueryPointerFromName(
++ Command->kernel->kernel, gcmALL_TO_UINT32(task->info));
++
++ /* Unmap the user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Command->os, gcvCORE_VG, task->memory, task->size, info, task->address
++ ));
++
++ /* Update the reference counter. */
++ TaskHeader->container->referenceCount -= 1;
++
++ /* Update the task pointer. */
++ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1);
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++************ Hardware Block Interrupt Handlers For Scheduled Events ************
++\******************************************************************************/
++
++static gceSTATUS
++_EventHandler_Block(
++ IN gckVGKERNEL Kernel,
++ IN gcsBLOCK_TASK_ENTRY_PTR TaskHeader,
++ IN gctBOOL ProcessAll
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskHeader=0x%x ProcessAll=0x%x", Kernel, TaskHeader, ProcessAll);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ if (TaskHeader->task == gcvNULL)
++ {
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++ }
++
++ do
++ {
++ gckVGCOMMAND command;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Increment the interrupt usage semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, TaskHeader->interruptSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->taskMutex,
++ gcvINFINITE
++ ));
++
++ /* Verify inputs. */
++ gcmkASSERT(TaskHeader != gcvNULL);
++ gcmkASSERT(TaskHeader->container != gcvNULL);
++ gcmkASSERT(TaskHeader->task != gcvNULL);
++ gcmkASSERT(TaskHeader->link != gcvNULL);
++
++ /* Process tasks. */
++ do
++ {
++ /* Process the current task. */
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Is the next task is LINK? */
++ if (TaskHeader->task->id == gcvTASK_LINK)
++ {
++ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id](
++ command,
++ TaskHeader
++ ));
++
++ /* Done. */
++ break;
++ }
++ }
++ while (ProcessAll);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->taskMutex
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gcmDECLARE_INTERRUPT_HANDLER(COMMAND, 0)
++{
++ gceSTATUS status, last;
++
++ gcmkHEADER_ARG("Kernel=0x%x ", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++
++ do
++ {
++ gckVGCOMMAND command;
++ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue;
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT entryCount;
++
++ /* Get the command buffer object. */
++ command = Kernel->command;
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ command->os,
++ command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Get the current queue. */
++ queueTail = command->queueTail;
++
++ /* Get the current queue entry. */
++ entry = queueTail->currentEntry;
++
++ /* Get the number of entries in the queue. */
++ entryCount = queueTail->pending;
++
++ /* Process all entries. */
++ while (gcvTRUE)
++ {
++ /* Call post-execution function. */
++ status = entry->handler(Kernel, entry);
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: post action failed.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Executed the next buffer? */
++ if (status == gcvSTATUS_EXECUTED)
++ {
++ /* Update the queue. */
++ queueTail->pending = entryCount;
++ queueTail->currentEntry = entry;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++
++ /* Break out of the loop. */
++ break;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ entryCount -= 1;
++
++ /* Last entry? */
++ if (entryCount == 0)
++ {
++ /* Reset the queue to idle. */
++ queueTail->pending = 0;
++
++ /* Get a shortcut to the queue to merge with. */
++ mergeQueue = command->mergeQueue;
++
++ /* Merge the queues if necessary. */
++ if (mergeQueue != queueTail)
++ {
++ gcmkASSERT(mergeQueue < queueTail);
++ gcmkASSERT(mergeQueue->next == queueTail);
++
++ mergeQueue->size
++ += gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + queueTail->size;
++
++ mergeQueue->next = queueTail->next;
++ }
++
++ /* Advance to the next queue. */
++ queueTail = queueTail->next;
++
++ /* Did it wrap around? */
++ if (command->queue == queueTail)
++ {
++ /* Reset merge queue. */
++ command->mergeQueue = queueTail;
++ }
++
++ /* Set new queue. */
++ command->queueTail = queueTail;
++
++ /* Is the next queue scheduled? */
++ if (queueTail->pending > 0)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ status = gckVGHARDWARE_Execute(
++ command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Failed? */
++ if (gcmkIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR,
++ gcvZONE_COMMAND,
++ "[%s] line %d: failed to start the next queue.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ }
++ else
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(
++ Kernel->command->hardware, gcvPOWER_IDLE_BROADCAST
++ );
++ }
++
++ /* Break out of the loop. */
++ break;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ command->os,
++ command->queueMutex
++ ));
++ }
++ while (gcvFALSE);
++
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/* Define standard block interrupt handlers. */
++gcmDEFINE_INTERRUPT_HANDLER(TESSELLATOR, 0)
++gcmDEFINE_INTERRUPT_HANDLER(VG, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 0)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 1)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 2)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 3)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 4)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 5)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 6)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 7)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 8)
++gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 9)
++
++/* The entries in the array are arranged by event priority. */
++static gcsBLOCK_INTERRUPT_HANDLER _blockHandlers[] =
++{
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(TESSELLATOR, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(VG, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 0),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 1),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 2),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 3),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 4),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 5),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 6),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 7),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 8),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 9),
++ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(COMMAND, 0),
++};
++
++
++/******************************************************************************\
++************************* Static Command Buffer Handlers ***********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Cast the command buffer header. */
++ commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastStaticCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastStaticCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++************************* Dynamic Command Buffer Handlers **********************
++\******************************************************************************/
++
++static gceSTATUS
++_UpdateDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d)\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_ExecuteDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UpdateLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++#if gcvDEBUG || gcdFORCE_MESSAGES
++ /* Get the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Validate the command buffer. */
++ gcmkASSERT(commandBuffer->completion != gcvNULL);
++ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER);
++
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): processing all tasks scheduled for FE.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Perform scheduled tasks. */
++ return _EventHandler_Block(
++ Kernel,
++ &Kernel->command->taskTable[gcvBLOCK_COMMAND],
++ gcvTRUE
++ );
++}
++
++static gceSTATUS
++_ExecuteLastDynamicCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Cast the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer;
++
++ /* Set to update the command buffer next time. */
++ Entry->handler = _UpdateLastDynamicCommandBuffer;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n",
++ __FUNCTION__, __LINE__,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ );
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Kernel->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++
++ /* Success. */
++ return gcvSTATUS_EXECUTED;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++********************************* Other Handlers *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_FreeKernelCommandBuffer(
++ IN gckVGKERNEL Kernel,
++ IN gcsKERNEL_CMDQUEUE_PTR Entry
++ )
++{
++ gceSTATUS status;
++
++ /* Free the command buffer. */
++ status = _FreeCommandBuffer(Kernel, Entry->commandBuffer);
++
++ /* Return status. */
++ return status;
++}
++
++
++/******************************************************************************\
++******************************* Queue Management *******************************
++\******************************************************************************/
++
++#if gcvDUMP_COMMAND_BUFFER
++static void
++_DumpCommandQueue(
++ IN gckVGCOMMAND Command,
++ IN gcsKERNEL_QUEUE_HEADER_PTR QueueHeader,
++ IN gctUINT EntryCount
++ )
++{
++ gcsKERNEL_CMDQUEUE_PTR entry;
++ gctUINT queueIndex;
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ static gctUINT arrayCount = 0;
++#endif
++
++ /* Is dumpinng enabled? */
++ if (!Commad->enableDumping)
++ {
++ return;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "COMMAND QUEUE DUMP: %d entries\n", EntryCount
++ );
++#endif
++
++ /* Get the pointer to the first entry. */
++ entry = QueueHeader->currentEntry;
++
++ /* Iterate through the queue. */
++ for (queueIndex = 0; queueIndex < EntryCount; queueIndex += 1)
++ {
++ gcsCMDBUFFER_PTR buffer;
++ gctUINT bufferCount;
++ gctUINT bufferIndex;
++ gctUINT i, count;
++ gctUINT size;
++ gctUINT32_PTR data;
++
++#if gcvDUMP_COMMAND_LINES
++ gctUINT lineNumber;
++#endif
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_COMMAND,
++ "ENTRY %d\n", queueIndex
++ );
++#endif
++
++ /* Reset the count. */
++ bufferCount = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Update the count. */
++ bufferCount += 1;
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ }
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ if (bufferCount > 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER SET: %d buffers.\n",
++ bufferCount
++ );
++ }
++#endif
++
++ /* Reset the buffer index. */
++ bufferIndex = 0;
++
++ /* Set the initial buffer. */
++ buffer = entry->commandBuffer;
++
++ /* Loop through all subbuffers. */
++ while (buffer)
++ {
++ /* Determine the size of the buffer. */
++ size = buffer->dataCount * Command->info.commandAlignment;
++
++#if !defined(gcvCOMMAND_BUFFER_NAME)
++ /* A single buffer? */
++ if (bufferCount == 1)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER: count=%d (0x%X), size=%d bytes @ %08X.\n",
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ " COMMAND BUFFER %d: count=%d (0x%X), size=%d bytes @ %08X\n",
++ bufferIndex,
++ buffer->dataCount,
++ buffer->dataCount,
++ size,
++ buffer->address
++ );
++ }
++#endif
++
++ /* Determine the number of double words to print. */
++ count = size / 4;
++
++ /* Determine the buffer location. */
++ data = (gctUINT32_PTR)
++ (
++ (gctUINT8_PTR) buffer + buffer->bufferOffset
++ );
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "unsigned int _" gcvCOMMAND_BUFFER_NAME "_%d[] =\n",
++ arrayCount
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "{\n"
++ );
++
++ arrayCount += 1;
++#endif
++
++#if gcvDUMP_COMMAND_LINES
++ /* Reset the line number. */
++ lineNumber = 0;
++#endif
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ count -= 2;
++#endif
++
++ for (i = 0; i < count; i += 1)
++ {
++ if ((i % 8) == 0)
++ {
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\t");
++#else
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " ");
++#endif
++ }
++
++#if gcvDUMP_COMMAND_LINES
++ if (lineNumber == gcvDUMP_COMMAND_LINES)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " . . . . . . . . .\n");
++ break;
++ }
++#endif
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "0x%08X", data[i]);
++
++ if (i + 1 == count)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ if (((i + 1) % 8) == 0)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ",\n");
++
++#if gcvDUMP_COMMAND_LINES
++ lineNumber += 1;
++#endif
++ }
++ else
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ", ");
++ }
++ }
++ }
++
++#if defined(gcvCOMMAND_BUFFER_NAME)
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO,
++ gcvZONE_COMMAND,
++ "};\n\n"
++ );
++#endif
++
++ /* Advance to the next subbuffer. */
++ buffer = buffer->nextSubBuffer;
++ bufferIndex += 1;
++ }
++
++ /* Advance to the next entry. */
++ entry += 1;
++ }
++}
++#endif
++
++static gceSTATUS
++_LockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ OUT gcsKERNEL_CMDQUEUE_PTR * Entries,
++ OUT gctUINT_PTR EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++
++ /* Get a shortcut to the head of the queue. */
++ queueHead = Command->queueHead;
++
++ /* Is the head buffer still being worked on? */
++ if (queueHead->pending)
++ {
++ /* Increment overflow count. */
++ Command->queueOverflow += 1;
++
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, queueHead));
++ }
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++
++ /* Determine the first queue entry. */
++ queueHead->currentEntry = (gcsKERNEL_CMDQUEUE_PTR)
++ (
++ (gctUINT8_PTR) queueHead + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ );
++
++ /* Set the pointer to the first entry. */
++ * Entries = queueHead->currentEntry;
++
++ /* Determine the number of available entries. */
++ * EntryCount = queueHead->size / gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++static gceSTATUS
++_UnlockCurrentQueue(
++ IN gckVGCOMMAND Command,
++ IN gctUINT EntryCount
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++#if !gcdENABLE_INFINITE_SPEED_HW
++ gcsKERNEL_QUEUE_HEADER_PTR queueTail;
++ gcsKERNEL_QUEUE_HEADER_PTR queueHead;
++ gcsKERNEL_QUEUE_HEADER_PTR queueNext;
++ gctUINT queueSize;
++ gctUINT newSize;
++ gctUINT unusedSize;
++
++ /* Get shortcut to the head and to the tail of the queue. */
++ queueTail = Command->queueTail;
++ queueHead = Command->queueHead;
++
++ /* Dump the command buffer. */
++#if gcvDUMP_COMMAND_BUFFER
++ _DumpCommandQueue(Command, queueHead, EntryCount);
++#endif
++
++ /* Get a shortcut to the current queue size. */
++ queueSize = queueHead->size;
++
++ /* Determine the new queue size. */
++ newSize = EntryCount * gcmSIZEOF(gcsKERNEL_CMDQUEUE);
++ gcmkASSERT(newSize <= queueSize);
++
++ /* Determine the size of the unused area. */
++ unusedSize = queueSize - newSize;
++
++ /* Is the unused area big enough to become a buffer? */
++ if (unusedSize >= gcvMINUMUM_BUFFER)
++ {
++ gcsKERNEL_QUEUE_HEADER_PTR nextHead;
++
++ /* Place the new header. */
++ nextHead = (gcsKERNEL_QUEUE_HEADER_PTR)
++ (
++ (gctUINT8_PTR) queueHead
++ + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER)
++ + newSize
++ );
++
++ /* Initialize the buffer. */
++ nextHead->size = unusedSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ nextHead->pending = 0;
++
++ /* Link the buffer in. */
++ nextHead->next = queueHead->next;
++ queueHead->next = nextHead;
++ queueNext = nextHead;
++
++ /* Update the size of the current buffer. */
++ queueHead->size = newSize;
++ }
++
++ /* Not big enough. */
++ else
++ {
++ /* Determine the next queue. */
++ queueNext = queueHead->next;
++ }
++
++ /* Mark the buffer as busy. */
++ queueHead->pending = EntryCount;
++
++ /* Advance to the next buffer. */
++ Command->queueHead = queueNext;
++
++ /* Start the command processor if the queue was empty. */
++ if (queueTail == queueHead)
++ {
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* The first entry must be a command buffer. */
++ commandBuffer = queueTail->currentEntry->commandBuffer;
++
++ /* Start the command processor. */
++ gcmkERR_BREAK(gckVGHARDWARE_Execute(
++ Command->hardware,
++ commandBuffer->address,
++ commandBuffer->dataCount
++ ));
++ }
++
++ /* The queue was not empty. */
++ else
++ {
++ /* Advance the merge buffer if needed. */
++ if (queueHead == Command->mergeQueue)
++ {
++ Command->mergeQueue = queueNext;
++ }
++ }
++#endif
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ return status;
++}
++
++
++
++/******************************************************************************\
++****************************** gckVGCOMMAND API Code *****************************
++\******************************************************************************/
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ )
++{
++ gceSTATUS status, last;
++ gckVGCOMMAND command = gcvNULL;
++ gcsKERNEL_QUEUE_HEADER_PTR queue;
++ gctUINT i, j;
++
++ gcmkHEADER_ARG("Kernel=0x%x TaskGranularity=0x%x QueueSize=0x%x Command=0x%x",
++ Kernel, TaskGranularity, QueueSize, Command);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(QueueSize >= gcvMINUMUM_BUFFER);
++ gcmkVERIFY_ARGUMENT(Command != gcvNULL);
++
++ do
++ {
++ /***********************************************************************
++ ** Generic object initialization.
++ */
++
++ /* Allocate the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGCOMMAND),
++ (gctPOINTER *) &command
++ ));
++
++ /* Initialize the object. */
++ command->object.type = gcvOBJ_COMMAND;
++
++ /* Set the object pointers. */
++ command->kernel = Kernel;
++ command->os = Kernel->os;
++ command->hardware = Kernel->hardware;
++
++ /* Reset pointers. */
++ command->queue = gcvNULL;
++ command->queueMutex = gcvNULL;
++ command->taskMutex = gcvNULL;
++ command->commitMutex = gcvNULL;
++
++ command->powerStallBuffer = gcvNULL;
++ command->powerStallSignal = gcvNULL;
++ command->powerSemaphore = gcvNULL;
++
++ /* Reset context states. */
++ command->contextCounter = 0;
++ command->currentContext = 0;
++
++ /* Enable command buffer dumping. */
++ command->enableDumping = gcvTRUE;
++
++ /* Set features. */
++ command->fe20 = Kernel->hardware->fe20;
++ command->vg20 = Kernel->hardware->vg20;
++ command->vg21 = Kernel->hardware->vg21;
++
++ /* Reset task table .*/
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ command->taskTable, gcmSIZEOF(command->taskTable)
++ ));
++
++ /* Query command buffer attributes. */
++ gcmkERR_BREAK(gckVGCOMMAND_InitializeInfo(command));
++
++ /* Create the control mutexes. */
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->queueMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->taskMutex));
++ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->commitMutex));
++
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphore(Kernel->os,
++ &command->powerSemaphore));
++
++ gcmkERR_BREAK(gckOS_CreateSignal(Kernel->os,
++ gcvFALSE, &command->powerStallSignal));
++
++ /***********************************************************************
++ ** Command queue initialization.
++ */
++
++ /* Allocate the command queue. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ QueueSize,
++ (gctPOINTER *) &command->queue
++ ));
++
++ /* Initialize the command queue. */
++ queue = command->queue;
++
++ queue->size = QueueSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER);
++ queue->pending = 0;
++ queue->next = queue;
++
++ command->queueHead =
++ command->queueTail =
++ command->mergeQueue = command->queue;
++
++ command->queueOverflow = 0;
++
++
++ /***********************************************************************
++ ** Enable TS overflow interrupt.
++ */
++
++ command->info.tsOverflowInt = 0;
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->info.tsOverflowInt,
++ _EventHandler_TSOverflow
++ ));
++
++ /* Mask out the interrupt. */
++ Kernel->hardware->eventMask &= ~(1 << command->info.tsOverflowInt);
++
++
++ /***********************************************************************
++ ** Enable Bus Error interrupt.
++ */
++
++ /* Hardwired to bit 31. */
++ command->busErrorInt = 31;
++
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->busErrorInt,
++ _EventHandler_BusError
++ ));
++
++
++ command->powerStallInt = 30;
++ /* Enable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &command->powerStallInt,
++ _EventHandler_PowerStall
++ ));
++
++ /***********************************************************************
++ ** Task management initialization.
++ */
++
++ command->taskStorage = gcvNULL;
++ command->taskStorageGranularity = TaskGranularity;
++ command->taskStorageUsable = TaskGranularity - gcmSIZEOF(gcsTASK_STORAGE);
++
++ command->taskFreeHead = gcvNULL;
++ command->taskFreeTail = gcvNULL;
++
++ /* Enable block handlers. */
++ for (i = 0; i < gcmCOUNTOF(_blockHandlers); i += 1)
++ {
++ /* Get the target hardware block. */
++ gceBLOCK block = _blockHandlers[i].block;
++
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[block];
++
++ /* Determine the interrupt value index. */
++ gctUINT index = entry->interruptCount;
++
++ /* Create the block semaphore. */
++ if (entry->interruptSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ command->os, &entry->interruptSemaphore
++ ));
++ }
++
++ /* Enable auto-detection. */
++ entry->interruptArray[index] = -1;
++
++ /* Enable interrupt for the block. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Enable(
++ Kernel->interrupt,
++ &entry->interruptArray[index],
++ _blockHandlers[i].handler
++ ));
++
++ /* Update the number of registered interrupts. */
++ entry->interruptCount += 1;
++
++ /* Inrement the semaphore to allow the usage of the registered
++ interrupt. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Get the FE interrupt. */
++ command->info.feBufferInt
++ = command->taskTable[gcvBLOCK_COMMAND].interruptArray[0];
++
++ /* Return gckVGCOMMAND object pointer. */
++ *Command = command;
++
++ gcmkFOOTER_ARG("*Command=0x%x",*Command);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (command != gcvNULL)
++ {
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the task table entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[i];
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ for (j = 0; j < entry->interruptCount; j += 1)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[j] >= 0);
++ gcmkASSERT(entry->interruptArray[j] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ entry->interruptArray[j]
++ ));
++ }
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (command->info.tsOverflowInt != -1)
++ {
++ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable(
++ Kernel->interrupt,
++ command->info.tsOverflowInt
++ ));
++ }
++
++ /* Delete the commit mutex. */
++ if (command->commitMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->commitMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->taskMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->taskMutex
++ ));
++ }
++
++ /* Delete the command queue mutex. */
++ if (command->queueMutex != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DeleteMutex(
++ Kernel->os, command->queueMutex
++ ));
++ }
++
++ /* Delete the command queue. */
++ if (command->queue != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command->queue
++ ));
++ }
++
++ if (command->powerSemaphore != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DestroySemaphore(
++ Kernel->os, command->powerSemaphore));
++ }
++
++ if (command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkVERIFY_OK(gckOS_DestroySignal(
++ Kernel->os,
++ command->powerStallSignal));
++ }
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkCHECK_STATUS(gckOS_Free(
++ Kernel->os, command
++ ));
++ }
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ OUT gckVGCOMMAND Command
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Command=0x%x", Command);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++
++ do
++ {
++ gctUINT i;
++ gcsTASK_STORAGE_PTR nextStorage;
++
++ if (Command->queueHead != gcvNULL)
++ {
++ /* Wait until the head becomes idle. */
++ gcmkERR_BREAK(_WaitForIdle(Command, Command->queueHead));
++ }
++
++ /* Disable block handlers. */
++ for (i = 0; i < gcvBLOCK_COUNT; i += 1)
++ {
++ /* Get the interrupt array entry. */
++ gcsBLOCK_TASK_ENTRY_PTR entry = &Command->taskTable[i];
++
++ /* Determine the index of the last interrupt in the array. */
++ gctINT index = entry->interruptCount - 1;
++
++ /* Destroy the semaphore. */
++ if (entry->interruptSemaphore != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, entry->interruptSemaphore
++ ));
++ }
++
++ /* Disable all enabled interrupts. */
++ while (index >= 0)
++ {
++ /* Must be a valid value. */
++ gcmkASSERT(entry->interruptArray[index] >= 0);
++ gcmkASSERT(entry->interruptArray[index] <= 31);
++
++ /* Disable the interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ entry->interruptArray[index]
++ ));
++
++ /* Update to the next interrupt. */
++ index -= 1;
++ entry->interruptCount -= 1;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Disable the bus error interrupt. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->busErrorInt
++ ));
++
++ /* Disable TS overflow interrupt. */
++ if (Command->info.tsOverflowInt != -1)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Disable(
++ Command->kernel->interrupt,
++ Command->info.tsOverflowInt
++ ));
++
++ Command->info.tsOverflowInt = -1;
++ }
++
++ /* Delete the commit mutex. */
++ if (Command->commitMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->commitMutex
++ ));
++
++ Command->commitMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->taskMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->taskMutex
++ ));
++
++ Command->taskMutex = gcvNULL;
++ }
++
++ /* Delete the command queue mutex. */
++ if (Command->queueMutex != gcvNULL)
++ {
++ gcmkERR_BREAK(gckOS_DeleteMutex(
++ Command->os, Command->queueMutex
++ ));
++
++ Command->queueMutex = gcvNULL;
++ }
++
++ if (Command->powerSemaphore != gcvNULL)
++ {
++ /* Destroy the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++
++ if (Command->powerStallSignal != gcvNULL)
++ {
++ /* Create the power management semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySignal(
++ Command->os,
++ Command->powerStallSignal));
++ }
++
++ if (Command->queue != gcvNULL)
++ {
++ /* Delete the command queue. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->queue
++ ));
++ }
++
++ /* Destroy all allocated buffers. */
++ while (Command->taskStorage)
++ {
++ /* Copy the buffer pointer. */
++ nextStorage = Command->taskStorage->next;
++
++ /* Free the current container. */
++ gcmkERR_BREAK(gckOS_Free(
++ Command->os, Command->taskStorage
++ ));
++
++ /* Advance to the next one. */
++ Command->taskStorage = nextStorage;
++ }
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* Mark the object as unknown. */
++ Command->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGCOMMAND structure. */
++ gcmkERR_BREAK(gckOS_Free(Command->os, Command));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Restore the object type if failed. */
++ Command->object.type = gcvOBJ_COMMAND;
++
++ gcmkFOOTER();
++ /* Return the error. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gcmkHEADER_ARG("Command=0x%x Information=0x%x", Command, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Information != gcvNULL);
++
++ /* Copy the information. */
++ gcmkVERIFY_OK(gckOS_MemCopy(
++ Information, &Command->info, sizeof(gcsCOMMAND_BUFFER_INFO)
++ ));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x Size=0x%x CommandBuffer=0x%x Data=0x%x",
++ Command, Size, CommandBuffer, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ do
++ {
++ /* Allocate the buffer. */
++ gcmkERR_BREAK(_AllocateCommandBuffer(Command, Size, CommandBuffer));
++
++ /* Determine the data pointer. */
++ * Data = (gctUINT8_PTR) (*CommandBuffer) + (* CommandBuffer)->bufferOffset;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ /* Free command buffer. */
++ status = _FreeCommandBuffer(Command->kernel, CommandBuffer);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x",
++ Command, CommandBuffer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL);
++
++ do
++ {
++ gctUINT queueLength;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Set the buffer. */
++ kernelEntry->commandBuffer = CommandBuffer;
++ kernelEntry->handler = _FreeKernelCommandBuffer;
++
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, 1
++ ));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ )
++{
++ /*
++ The first buffer is executed through a direct gckVGHARDWARE_Execute call,
++ therefore only an update is needed after the execution is over. All
++ consequent buffers need to be executed upon the first update call from
++ the FE interrupt handler.
++ */
++
++ static gcsQUEUE_UPDATE_CONTROL _dynamicBuffer[] =
++ {
++ {
++ _UpdateDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ },
++ {
++ _ExecuteDynamicCommandBuffer,
++ _UpdateDynamicCommandBuffer,
++ _ExecuteLastDynamicCommandBuffer,
++ _UpdateLastDynamicCommandBuffer
++ }
++ };
++
++ static gcsQUEUE_UPDATE_CONTROL _staticBuffer[] =
++ {
++ {
++ _UpdateStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ },
++ {
++ _ExecuteStaticCommandBuffer,
++ _UpdateStaticCommandBuffer,
++ _ExecuteLastStaticCommandBuffer,
++ _UpdateLastStaticCommandBuffer
++ }
++ };
++
++ gceSTATUS status, last;
++
++#ifdef __QNXNTO__
++ gcsVGCONTEXT_PTR userContext = gcvNULL;
++ gctBOOL userContextMapped = gcvFALSE;
++ gcsTASK_MASTER_TABLE_PTR userTaskTable = gcvNULL;
++ gctBOOL userTaskTableMapped = gcvFALSE;
++ gctPOINTER pointer = gcvNULL;
++#endif
++
++ gcmkHEADER_ARG("Command=0x%x Context=0x%x Queue=0x%x EntryCount=0x%x TaskTable=0x%x",
++ Command, Context, Queue, EntryCount, TaskTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND);
++ gcmkVERIFY_ARGUMENT(Context != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++ gcmkVERIFY_ARGUMENT(EntryCount > 1);
++
++ do
++ {
++ gctBOOL haveFETasks;
++ gctUINT queueSize;
++ gcsVGCMDQUEUE_PTR mappedQueue;
++ gcsVGCMDQUEUE_PTR userEntry;
++ gcsKERNEL_CMDQUEUE_PTR kernelEntry;
++ gcsQUEUE_UPDATE_CONTROL_PTR queueControl;
++ gctUINT currentLength;
++ gctUINT queueLength;
++ gctUINT entriesQueued;
++ gctUINT8_PTR previousEnd;
++ gctBOOL previousDynamic;
++ gctBOOL previousExecuted;
++ gctUINT controlIndex;
++
++#ifdef __QNXNTO__
++ /* Map the context into the kernel space. */
++ userContext = Context;
++
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ userContext,
++ gcmSIZEOF(*userContext),
++ &pointer));
++
++ Context = pointer;
++
++ userContextMapped = gcvTRUE;
++
++ /* Map the taskTable into the kernel space. */
++ userTaskTable = TaskTable;
++
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ userTaskTable,
++ gcmSIZEOF(*userTaskTable),
++ &pointer));
++
++ TaskTable = pointer;
++
++ userTaskTableMapped = gcvTRUE;
++
++ /* Update the signal info. */
++ TaskTable->coid = Context->coid;
++ TaskTable->rcvid = Context->rcvid;
++#endif
++
++ gcmkERR_BREAK(gckVGHARDWARE_SetPowerManagementState(
++ Command->hardware, gcvPOWER_ON_AUTO
++ ));
++
++ /* Acquire the power semaphore. */
++ gcmkERR_BREAK(gckOS_AcquireSemaphore(
++ Command->os, Command->powerSemaphore
++ ));
++
++ /* Acquire the mutex. */
++ status = gckOS_AcquireMutex(
++ Command->os,
++ Command->commitMutex,
++ gcvINFINITE
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ break;
++ }
++
++ do
++ {
++ gcmkERR_BREAK(_FlushMMU(Command));
++
++ /* Assign a context ID if not yet assigned. */
++ if (Context->id == 0)
++ {
++ /* Assign the next context number. */
++ Context->id = ++ Command->contextCounter;
++
++ /* See if we overflowed. */
++ if (Command->contextCounter == 0)
++ {
++ /* We actually did overflow, wow... */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++ }
++
++ /* The first entry in the queue is always the context buffer.
++ Verify whether the user context is the same as the current
++ context and if that's the case, skip the first entry. */
++ if (Context->id == Command->currentContext)
++ {
++ /* Same context as before, skip the first entry. */
++ EntryCount -= 1;
++ Queue += 1;
++
++ /* Set the signal to avoid user waiting. */
++#ifdef __QNXNTO__
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, Context->signal, Context->rcvid, Context->coid
++ ));
++#else
++ gcmkERR_BREAK(gckOS_UserSignal(
++ Command->os, Context->signal, Context->process
++ ));
++
++#endif /* __QNXNTO__ */
++
++ }
++ else
++ {
++ /* Different user context - keep the first entry.
++ Set the user context as the current one. */
++ Command->currentContext = Context->id;
++ }
++
++ /* Reset pointers. */
++ queueControl = gcvNULL;
++ previousEnd = gcvNULL;
++
++ /* Determine whether there are FE tasks to be performed. */
++ haveFETasks = (TaskTable->table[gcvBLOCK_COMMAND].head != gcvNULL);
++
++ /* Determine the size of the queue. */
++ queueSize = EntryCount * gcmSIZEOF(gcsVGCMDQUEUE);
++
++ /* Map the command queue into the kernel space. */
++ gcmkERR_BREAK(gckOS_MapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ (gctPOINTER *) &mappedQueue
++ ));
++
++ /* Set the first entry. */
++ userEntry = mappedQueue;
++
++ /* Process the command queue. */
++ while (EntryCount)
++ {
++ /* Lock the current queue. */
++ gcmkERR_BREAK(_LockCurrentQueue(
++ Command, &kernelEntry, &queueLength
++ ));
++
++ /* Determine the number of entries to process. */
++ currentLength = (queueLength < EntryCount)
++ ? queueLength
++ : EntryCount;
++
++ /* Update the number of the entries left to process. */
++ EntryCount -= currentLength;
++
++ /* Reset previous flags. */
++ previousDynamic = gcvFALSE;
++ previousExecuted = gcvFALSE;
++
++ /* Set the initial control index. */
++ controlIndex = 0;
++
++ /* Process entries. */
++ for (entriesQueued = 0; entriesQueued < currentLength; entriesQueued += 1)
++ {
++ /* Get the kernel pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer = gcvNULL;
++ gcmkERR_BREAK(_ConvertUserCommandBufferPointer(
++ Command,
++ userEntry->commandBuffer,
++ &commandBuffer
++ ));
++
++ /* Is it a dynamic command buffer? */
++ if (userEntry->dynamic)
++ {
++ /* Select dynamic buffer control functions. */
++ queueControl = &_dynamicBuffer[controlIndex];
++ }
++
++ /* No, a static command buffer. */
++ else
++ {
++ /* Select static buffer control functions. */
++ queueControl = &_staticBuffer[controlIndex];
++ }
++
++ /* Set the command buffer pointer to the entry. */
++ kernelEntry->commandBuffer = commandBuffer;
++
++ /* If the previous entry was a dynamic command buffer,
++ link it to the current. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand(
++ Command,
++ previousEnd,
++ commandBuffer->address,
++ commandBuffer->dataCount,
++ gcvNULL
++ ));
++
++ /* The buffer will be auto-executed, only need to
++ update it after it has been executed. */
++ kernelEntry->handler = queueControl->update;
++
++ /* The buffer is only being updated. */
++ previousExecuted = gcvFALSE;
++ }
++ else
++ {
++ /* Set the buffer up for execution. */
++ kernelEntry->handler = queueControl->execute;
++
++ /* The buffer is being updated. */
++ previousExecuted = gcvTRUE;
++ }
++
++ /* The current buffer's END command becomes the last END. */
++ previousEnd
++ = ((gctUINT8_PTR) commandBuffer)
++ + commandBuffer->bufferOffset
++ + commandBuffer->dataCount * Command->info.commandAlignment
++ - Command->info.staticTailSize;
++
++ /* Update the last entry info. */
++ previousDynamic = userEntry->dynamic;
++
++ /* Advance entries. */
++ userEntry += 1;
++ kernelEntry += 1;
++
++ /* Update the control index. */
++ controlIndex = 1;
++ }
++
++ /* If the previous entry was a dynamic command buffer,
++ terminate it with an END. */
++ if (previousDynamic)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_EndCommand(
++ Command,
++ previousEnd,
++ Command->info.feBufferInt,
++ gcvNULL
++ ));
++ }
++
++ /* Last buffer? */
++ if (EntryCount == 0)
++ {
++ /* Modify the last command buffer's routines to handle
++ tasks if any.*/
++ if (haveFETasks)
++ {
++ if (previousExecuted)
++ {
++ kernelEntry[-1].handler = queueControl->lastExecute;
++ }
++ else
++ {
++ kernelEntry[-1].handler = queueControl->lastUpdate;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkERR_BREAK(gckOS_ReleaseMutex(
++ Command->os,
++ Command->queueMutex
++ ));
++ /* Schedule tasks. */
++ gcmkERR_BREAK(_ScheduleTasks(Command, TaskTable, previousEnd));
++
++ /* Acquire the mutex. */
++ gcmkERR_BREAK(gckOS_AcquireMutex(
++ Command->os,
++ Command->queueMutex,
++ gcvINFINITE
++ ));
++ }
++
++ /* Unkock and schedule the current queue for execution. */
++ gcmkERR_BREAK(_UnlockCurrentQueue(
++ Command, currentLength
++ ));
++ }
++
++
++ /* Unmap the user command buffer. */
++ gcmkERR_BREAK(gckOS_UnmapUserPointer(
++ Command->os,
++ Queue,
++ queueSize,
++ mappedQueue
++ ));
++ }
++ while (gcvFALSE);
++
++ /* Release the mutex. */
++ gcmkCHECK_STATUS(gckOS_ReleaseMutex(
++ Command->os,
++ Command->commitMutex
++ ));
++
++ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(
++ Command->os, Command->powerSemaphore));
++ }
++ while (gcvFALSE);
++
++#ifdef __QNXNTO__
++ if (userContextMapped)
++ {
++ /* Unmap the user context. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ userContext,
++ gcmSIZEOF(*userContext),
++ Context));
++ }
++
++ if (userTaskTableMapped)
++ {
++ /* Unmap the user taskTable. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(
++ Command->os,
++ userTaskTable,
++ gcmSIZEOF(*userTaskTable),
++ TaskTable));
++ }
++#endif
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_db.c 2016-06-19 22:11:55.225145256 +0200
+@@ -0,0 +1,1861 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_DATABASE
++
++/*******************************************************************************
++***** Private fuctions ********************************************************/
++
++#define _GetSlot(database, x) \
++ (gctUINT32)(gcmPTR_TO_UINT64(x) % gcmCOUNTOF(database->list))
++
++/*******************************************************************************
++** gckKERNEL_NewDatabase
++**
++** Create a new database structure and insert it to the head of the hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++static gceSTATUS
++gckKERNEL_NewDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctBOOL acquired = gcvFALSE;
++ gctSIZE_T slot;
++ gcsDATABASE_PTR existingDatabase;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Walk the hash list. */
++ for (existingDatabase = Kernel->db->db[slot];
++ existingDatabase != gcvNULL;
++ existingDatabase = existingDatabase->next)
++ {
++ if (existingDatabase->processID == ProcessID)
++ {
++ /* One process can't be added twice. */
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++ }
++
++ if (Kernel->db->freeDatabase != gcvNULL)
++ {
++ /* Allocate a database from the free list. */
++ database = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = database->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate a new database from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE),
++ &pointer));
++
++ gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsDATABASE));
++
++ database = pointer;
++
++ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->counterMutex));
++ }
++
++ /* Insert the database into the hash. */
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++
++ /* Save the hash slot. */
++ database->slot = slot;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindDatabase
++**
++** Find a database identified by a process ID and move it to the head of the
++** hash list.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** ProcessID that identifies the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** OUTPUT:
++**
++** gcsDATABASE_PTR * Database
++** Pointer to a variable receiving the database structure pointer on
++** success.
++*/
++gceSTATUS
++gckKERNEL_FindDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ OUT gcsDATABASE_PTR * Database
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database, previous;
++ gctSIZE_T slot;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d LastProcessID=%d",
++ Kernel, ProcessID, LastProcessID);
++
++ /* Compute the hash for the database. */
++ slot = ProcessID % gcmCOUNTOF(Kernel->db->db);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Check whether we are getting the last known database. */
++ if (LastProcessID)
++ {
++ /* Use last database. */
++ database = Kernel->db->lastDatabase;
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ else
++ {
++ /* Walk the hash list. */
++ for (previous = gcvNULL, database = Kernel->db->db[slot];
++ database != gcvNULL;
++ database = database->next)
++ {
++ if (database->processID == ProcessID)
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = database;
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Database not found. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (previous != gcvNULL)
++ {
++ /* Move database to the head of the hash list. */
++ previous->next = database->next;
++ database->next = Kernel->db->db[slot];
++ Kernel->db->db[slot] = database;
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the database. */
++ *Database = database;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Database=0x%x", *Database);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteDatabase
++**
++** Remove a database from the hash list and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to the database structure to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++static gceSTATUS
++gckKERNEL_DeleteDatabase(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Check slot value. */
++ gcmkVERIFY_ARGUMENT(Database->slot < gcmCOUNTOF(Kernel->db->db));
++
++ if (Database->slot < gcmCOUNTOF(Kernel->db->db))
++ {
++ /* Check if database if the head of the hash list. */
++ if (Kernel->db->db[Database->slot] == Database)
++ {
++ /* Remove the database from the hash list. */
++ Kernel->db->db[Database->slot] = Database->next;
++ }
++ else
++ {
++ /* Walk the has list to find the database. */
++ for (database = Kernel->db->db[Database->slot];
++ database != gcvNULL;
++ database = database->next
++ )
++ {
++ /* Check if the next list entry is this database. */
++ if (database->next == Database)
++ {
++ /* Remove the database from the hash list. */
++ database->next = Database->next;
++ break;
++ }
++ }
++
++ if (database == gcvNULL)
++ {
++ /* Ouch! Something got corrupted. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++ }
++ }
++
++ if (Kernel->db->lastDatabase != gcvNULL)
++ {
++ /* Insert database to the free list. */
++ Kernel->db->lastDatabase->next = Kernel->db->freeDatabase;
++ Kernel->db->freeDatabase = Kernel->db->lastDatabase;
++ }
++
++ /* Keep database as the last database. */
++ Kernel->db->lastDatabase = Database;
++
++ /* Destory handle db. */
++ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Database->handleDatabase));
++ Database->handleDatabase = gcvNULL;
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Database->handleDatabaseMutex));
++ Database->handleDatabaseMutex = gcvNULL;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Destory process MMU. */
++ gcmkVERIFY_OK(gckEVENT_DestroyMmu(Kernel->eventObj, Database->mmu, gcvKERNEL_PIXEL));
++ Database->mmu = gcvNULL;
++#endif
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_NewRecord
++**
++** Create a new database record structure and insert it to the head of the
++** database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR * Record
++** Pointer to a variable receiving the database record structure
++** pointer on success.
++*/
++static gceSTATUS
++gckKERNEL_NewRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gctUINT32 Slot,
++ OUT gcsDATABASE_RECORD_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ if (Kernel->db->freeRecord != gcvNULL)
++ {
++ /* Allocate the record from the free list. */
++ record = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record->next;
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Allocate the record from the heap. */
++ gcmkONERROR(gckOS_Allocate(Kernel->os,
++ gcmSIZEOF(gcsDATABASE_RECORD),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Insert the record in the database. */
++ record->next = Database->list[Slot];
++ Database->list[Slot] = record;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Return the record. */
++ *Record = record;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", *Record);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DeleteRecord
++**
++** Remove a database record from the database and delete its structure.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_DeleteRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T_PTR Bytes OPTIONAL
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record, previous;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot], previous = gcvNULL;
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++
++ previous = record;
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Bytes != gcvNULL)
++ {
++ /* Return size of record. */
++ *Bytes = record->bytes;
++ }
++
++ /* Remove record from database. */
++ if (previous == gcvNULL)
++ {
++ Database->list[slot] = record->next;
++ }
++ else
++ {
++ previous->next = record->next;
++ }
++
++ /* Insert record in free list. */
++ record->next = Kernel->db->freeRecord;
++ Kernel->db->freeRecord = record;
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes));
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindRecord
++**
++** Find a database record from the database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gcsDATABASE_PTR Database
++** Pointer to a database structure.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to remove.
++**
++** gctPOINTER Data
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gctSIZE_T_PTR Bytes
++** Pointer to a variable that receives the size of the record deleted.
++** Can be gcvNULL if the size is not required.
++*/
++static gceSTATUS
++gckKERNEL_FindRecord(
++ IN gckKERNEL Kernel,
++ IN gcsDATABASE_PTR Database,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Data,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsDATABASE_RECORD_PTR record;
++ gctUINT32 slot = _GetSlot(Database, Data);
++
++ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x",
++ Kernel, Database, Type, Data);
++
++ /* Acquire the database mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Scan the database for this record. */
++ for (record = Database->list[slot];
++ record != gcvNULL;
++ record = record->next
++ )
++ {
++ if ((record->type == Type)
++ && (record->data == Data)
++ )
++ {
++ /* Found it! */
++ break;
++ }
++ }
++
++ if (record == gcvNULL)
++ {
++ /* Ouch! This record is not found? */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ if (Record != gcvNULL)
++ {
++ /* Return information of record. */
++ gcmkONERROR(
++ gckOS_MemCopy(Record, record, sizeof(gcsDATABASE_RECORD)));
++ }
++
++ /* Release the database mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("Record=0x%x", Record);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++***** Public API **************************************************************/
++
++/*******************************************************************************
++** gckKERNEL_CreateProcessDB
++**
++** Create a new process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database = gcvNULL;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Create a new database. */
++ gcmkONERROR(gckKERNEL_NewDatabase(Kernel, ProcessID, &database));
++
++ /* Initialize the database. */
++ database->processID = ProcessID;
++ database->vidMem.bytes = 0;
++ database->vidMem.maxBytes = 0;
++ database->vidMem.totalBytes = 0;
++ database->nonPaged.bytes = 0;
++ database->nonPaged.maxBytes = 0;
++ database->nonPaged.totalBytes = 0;
++ database->contiguous.bytes = 0;
++ database->contiguous.maxBytes = 0;
++ database->contiguous.totalBytes = 0;
++ database->mapMemory.bytes = 0;
++ database->mapMemory.maxBytes = 0;
++ database->mapMemory.totalBytes = 0;
++ database->mapUserMemory.bytes = 0;
++ database->mapUserMemory.maxBytes = 0;
++ database->mapUserMemory.totalBytes = 0;
++ database->virtualCommandBuffer.bytes = 0;
++ database->virtualCommandBuffer.maxBytes = 0;
++ database->virtualCommandBuffer.totalBytes = 0;
++
++ for (i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++ database->list[i] = gcvNULL;
++ }
++
++ for (i = 0; i < gcvSURF_NUM_TYPES; i++)
++ {
++ database->vidMemType[i].bytes = 0;
++ database->vidMemType[i].maxBytes = 0;
++ database->vidMemType[i].totalBytes = 0;
++ }
++
++ for (i = 0; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ database->vidMemPool[i].bytes = 0;
++ database->vidMemPool[i].maxBytes = 0;
++ database->vidMemPool[i].totalBytes = 0;
++ }
++
++ gcmkASSERT(database->handleDatabase == gcvNULL);
++ gcmkONERROR(
++ gckKERNEL_CreateIntegerDatabase(Kernel, &database->handleDatabase));
++
++ gcmkASSERT(database->handleDatabaseMutex == gcvNULL);
++ gcmkONERROR(
++ gckOS_CreateMutex(Kernel->os, &database->handleDatabaseMutex));
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkASSERT(database->mmu == gcvNULL);
++ gcmkONERROR(
++ gckMMU_Construct(Kernel, gcdMMU_SIZE, &database->mmu));
++#endif
++
++#if gcdSECURE_USER
++ {
++ gctINT slot;
++ gcskSECURE_CACHE * cache = &database->cache;
++
++ /* Setup the linked list of cache nodes. */
++ for (slot = 1; slot <= gcdSECURE_CACHE_SLOTS; ++slot)
++ {
++ cache->cache[slot].logical = gcvNULL;
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ cache->cache[slot].prev = &cache->cache[slot - 1];
++ cache->cache[slot].next = &cache->cache[slot + 1];
++# endif
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ cache->cache[slot].nextHash = gcvNULL;
++ cache->cache[slot].prevHash = gcvNULL;
++# endif
++ }
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ /* Setup the head and tail of the cache. */
++ cache->cache[0].next = &cache->cache[1];
++ cache->cache[0].prev = &cache->cache[gcdSECURE_CACHE_SLOTS];
++ cache->cache[0].logical = gcvNULL;
++
++ /* Fix up the head and tail pointers. */
++ cache->cache[0].next->prev = &cache->cache[0];
++ cache->cache[0].prev->next = &cache->cache[0];
++# endif
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Zero out the hash table. */
++ for (slot = 0; slot < gcmCOUNTOF(cache->hash); ++slot)
++ {
++ cache->hash[slot].logical = gcvNULL;
++ cache->hash[slot].nextHash = gcvNULL;
++ }
++# endif
++
++ /* Initialize cache index. */
++ cache->cacheIndex = gcvNULL;
++ cache->cacheFree = 1;
++ cache->cacheStamp = 0;
++ }
++#endif
++
++ /* Reset idle timer. */
++ Kernel->db->lastIdle = 0;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_AddProcessDB
++**
++** Add a record to a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to add.
++**
++** gctPOINTER Pointer
++** Data of the record to add.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the record to add.
++**
++** gctSIZE_T Size
++** Size of the record to add.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record = gcvNULL;
++ gcsDATABASE_COUNTERS * count;
++ gctUINT32 vidMemType;
++ gcePOOL vidMemPool;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x "
++ "Physical=0x%x Size=%lu",
++ Kernel, ProcessID, Type, Pointer, Physical, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Decode type. */
++ vidMemType = (Type & gcdDB_VIDEO_MEMORY_TYPE_MASK) >> gcdDB_VIDEO_MEMORY_TYPE_SHIFT;
++ vidMemPool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT;
++
++ Type &= gcdDATABASE_TYPE_MASK;
++
++ /* Special case the idle record. */
++ if (Type == gcvDB_IDLE)
++ {
++ gctUINT64 time;
++
++ /* Get the current profile time. */
++ gcmkONERROR(gckOS_GetProfileTick(&time));
++
++ if ((ProcessID == 0) && (Kernel->db->lastIdle != 0))
++ {
++ /* Out of idle, adjust time it was idle. */
++ Kernel->db->idleTime += time - Kernel->db->lastIdle;
++ Kernel->db->lastIdle = 0;
++ }
++ else if (ProcessID == 1)
++ {
++ /* Save current idle time. */
++ Kernel->db->lastIdle = time;
++ }
++
++#if gcdDYNAMIC_SPEED
++ {
++ /* Test for first call. */
++ if (Kernel->db->lastSlowdown == 0)
++ {
++ /* Save milliseconds. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ else
++ {
++ /* Compute ellapsed time in milliseconds. */
++ gctUINT delta = gckOS_ProfileToMS(time - Kernel->db->lastSlowdown);
++
++ /* Test for end of period. */
++ if (delta >= gcdDYNAMIC_SPEED)
++ {
++ /* Compute number of idle milliseconds. */
++ gctUINT idle = gckOS_ProfileToMS(
++ Kernel->db->idleTime - Kernel->db->lastSlowdownIdle);
++
++ /* Broadcast to slow down the GPU. */
++ gcmkONERROR(gckOS_BroadcastCalibrateSpeed(Kernel->os,
++ Kernel->hardware,
++ idle,
++ delta));
++
++ /* Save current time. */
++ Kernel->db->lastSlowdown = time;
++ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime;
++ }
++ }
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Create a new record in the database. */
++ gcmkONERROR(gckKERNEL_NewRecord(Kernel, database, _GetSlot(database, Pointer), &record));
++
++ /* Initialize the record. */
++ record->kernel = Kernel;
++ record->type = Type;
++ record->data = Pointer;
++ record->physical = Physical;
++ record->bytes = Size;
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ count = &database->vidMem;
++ break;
++
++ case gcvDB_NON_PAGED:
++ count = &database->nonPaged;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ count = &database->contiguous;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ count = &database->mapMemory;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ count = &database->mapUserMemory;
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ count = &database->virtualCommandBuffer;
++ break;
++
++ default:
++ count = gcvNULL;
++ break;
++ }
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE));
++
++ if (count != gcvNULL)
++ {
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++ }
++
++ if (Type == gcvDB_VIDEO_MEMORY)
++ {
++ count = &database->vidMemType[vidMemType];
++
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++
++ count = &database->vidMemPool[vidMemPool];
++
++ /* Adjust counters. */
++ count->totalBytes += Size;
++ count->bytes += Size;
++
++ if (count->bytes > count->maxBytes)
++ {
++ count->maxBytes = count->bytes;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_RemoveProcessDB
++**
++** Remove a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctSIZE_T bytes = 0;
++ gctUINT32 vidMemType;
++ gcePOOL vidMempool;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Decode type. */
++ vidMemType = (Type & gcdDB_VIDEO_MEMORY_TYPE_MASK) >> gcdDB_VIDEO_MEMORY_TYPE_SHIFT;
++ vidMempool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT;
++
++ Type &= gcdDATABASE_TYPE_MASK;
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Delete the record. */
++ gcmkONERROR(
++ gckKERNEL_DeleteRecord(Kernel, database, Type, Pointer, &bytes));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE));
++
++ /* Update counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ database->vidMem.bytes -= bytes;
++ database->vidMemType[vidMemType].bytes -= bytes;
++ database->vidMemPool[vidMempool].bytes -= bytes;
++ break;
++
++ case gcvDB_NON_PAGED:
++ database->nonPaged.bytes -= bytes;
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ database->contiguous.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ database->mapMemory.bytes -= bytes;
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ database->mapUserMemory.bytes -= bytes;
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ database->virtualCommandBuffer.bytes -= bytes;
++ break;
++
++ default:
++ break;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_FindProcessDB
++**
++** Find a record from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gceDATABASE_TYPE TYPE
++** Type of the record to remove.
++**
++** gctPOINTER Pointer
++** Data of the record to remove.
++**
++** OUTPUT:
++**
++** gcsDATABASE_RECORD_PTR Record
++** Copy of record.
++*/
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x",
++ Kernel, ProcessID, ThreadID, Type, Pointer);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Find the record. */
++ gcmkONERROR(
++ gckKERNEL_FindRecord(Kernel, database, Type, Pointer, Record));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_DestroyProcessDB
++**
++** Destroy a process database. If the database contains any records, the data
++** inside those records will be deleted as well. This aids in the cleanup if
++** a process has died unexpectedly or has memory leaks.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_RECORD_PTR record, next;
++ gctBOOL asynchronous = gcvTRUE;
++ gckVIDMEM_NODE nodeObject;
++ gctPHYS_ADDR physical;
++ gckKERNEL kernel = Kernel;
++ gctUINT32 handle;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): VidMem: total=%lu max=%lu",
++ ProcessID, database->vidMem.totalBytes,
++ database->vidMem.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): NonPaged: total=%lu max=%lu",
++ ProcessID, database->nonPaged.totalBytes,
++ database->nonPaged.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Contiguous: total=%lu max=%lu",
++ ProcessID, database->contiguous.totalBytes,
++ database->contiguous.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Idle time=%llu",
++ ProcessID, Kernel->db->idleTime);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapMemory.totalBytes,
++ database->mapMemory.maxBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE,
++ "DB(%d): Map: total=%lu max=%lu",
++ ProcessID, database->mapUserMemory.totalBytes,
++ database->mapUserMemory.maxBytes);
++
++ if (database->list != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "Process %d has entries in its database:",
++ ProcessID);
++ }
++
++ for(i = 0; i < gcmCOUNTOF(database->list); i++)
++ {
++
++ /* Walk all records. */
++ for (record = database->list[i]; record != gcvNULL; record = next)
++ {
++ /* Next next record. */
++ next = record->next;
++
++ /* Dispatch on record type. */
++ switch (record->type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(record->kernel,
++ ProcessID,
++ gcmPTR2INT32(record->data),
++ &nodeObject));
++
++ /* Free the video memory. */
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel,
++ ProcessID,
++ gcmPTR2INT32(record->data)));
++
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel,
++ nodeObject));
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_NON_PAGED:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the non paged memory. */
++ status = gckEVENT_FreeNonPagedMemory(Kernel->eventObj,
++ record->bytes,
++ physical,
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: NON_PAGED 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ /* Free the command buffer. */
++ status = gckEVENT_DestroyVirtualCommandBuffer(record->kernel->eventObj,
++ record->bytes,
++ gcmNAME_TO_PTR(record->physical),
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: COMMAND_BUFFER 0x%x, bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ physical = gcmNAME_TO_PTR(record->physical);
++ /* Unmap user logical memory first. */
++ status = gckOS_UnmapUserLogical(Kernel->os,
++ physical,
++ record->bytes,
++ record->data);
++
++ /* Free the contiguous memory. */
++ status = gckEVENT_FreeContiguousMemory(Kernel->eventObj,
++ record->bytes,
++ physical,
++ record->data,
++ gcvKERNEL_PIXEL);
++ gcmRELEASE_NAME(record->physical);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTIGUOUS 0x%x bytes=%lu (status=%d)",
++ record->data, record->bytes, status);
++ break;
++
++ case gcvDB_SIGNAL:
++#if USE_NEW_LINUX_SIGNAL
++ status = gcvSTATUS_NOT_SUPPORTED;
++#else
++ /* Free the user signal. */
++ status = gckOS_DestroyUserSignal(Kernel->os,
++ gcmPTR2INT32(record->data));
++#endif /* USE_NEW_LINUX_SIGNAL */
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SIGNAL %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++
++ case gcvDB_VIDEO_MEMORY_LOCKED:
++ handle = gcmPTR2INT32(record->data);
++
++ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(record->kernel,
++ ProcessID,
++ handle,
++ &nodeObject));
++
++ /* Unlock what we still locked */
++ status = gckVIDMEM_Unlock(record->kernel,
++ nodeObject,
++ nodeObject->type,
++ &asynchronous);
++
++#if gcdENABLE_VG
++ if (record->kernel->core == gcvCORE_VG)
++ {
++ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous))
++ {
++ /* TODO: we maybe need to schedule a event here */
++ status = gckVIDMEM_Unlock(record->kernel,
++ nodeObject,
++ nodeObject->type,
++ gcvNULL);
++ }
++
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel,
++ ProcessID,
++ handle));
++
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel,
++ nodeObject));
++ }
++ else
++#endif
++ {
++ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel,
++ ProcessID,
++ handle));
++
++ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous))
++ {
++ status = gckEVENT_Unlock(record->kernel->eventObj,
++ gcvKERNEL_PIXEL,
++ nodeObject,
++ nodeObject->type);
++ }
++ else
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel,
++ nodeObject));
++ }
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: VIDEO_MEMORY_LOCKED 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_CONTEXT:
++ /* TODO: Free the context */
++ status = gckCOMMAND_Detach(Kernel->command, gcmNAME_TO_PTR(record->data));
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: CONTEXT 0x%x (status=%d)",
++ record->data, status);
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ /* Unmap memory. */
++ status = gckKERNEL_UnmapMemory(Kernel,
++ record->physical,
++ record->bytes,
++ record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP MEMORY %d (status=%d)",
++ gcmPTR2INT32(record->data), status);
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ /* TODO: Unmap user memory. */
++ status = gckOS_UnmapUserMemory(Kernel->os,
++ Kernel->core,
++ record->physical,
++ record->bytes,
++ gcmNAME_TO_PTR(record->data),
++ 0);
++ gcmRELEASE_NAME(record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: MAP USER MEMORY %d (status=%d)",
++ gcmPTR2INT32(record->data), status);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvDB_SYNC_POINT:
++ /* Free the user signal. */
++ status = gckOS_DestroySyncPoint(Kernel->os,
++ (gctSYNC_POINT) record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SYNC POINT %d (status=%d)",
++ (gctINT)(gctUINTPTR_T)record->data, status);
++ break;
++#endif
++
++ case gcvDB_SHBUF:
++ /* Free shared buffer. */
++ status = gckKERNEL_DestroyShBuffer(Kernel,
++ (gctSHBUF) record->data);
++
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE,
++ "DB: SHBUF %u (status=%d)",
++ (gctUINT32)(gctUINTPTR_T) record->data, status);
++ break;
++
++ default:
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DATABASE,
++ "DB: Correcupted record=0x%08x type=%d",
++ record, record->type);
++ break;
++ }
++
++ /* Delete the record. */
++ gcmkONERROR(gckKERNEL_DeleteRecord(Kernel,
++ database,
++ record->type,
++ record->data,
++ gcvNULL));
++ }
++
++ }
++
++ /* Delete the database. */
++ gcmkONERROR(gckKERNEL_DeleteDatabase(Kernel, database));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckKERNEL_QueryProcessDB
++**
++** Query a process database for the current usage of a particular record type.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** gctBOOL LastProcessID
++** gcvTRUE if searching for the last known process ID. gcvFALSE if
++** we need to search for the process ID specified by the ProcessID
++** argument.
++**
++** gceDATABASE_TYPE Type
++** Type of the record to query.
++**
++** OUTPUT:
++**
++** gcuDATABASE_INFO * Info
++** Pointer to a variable that receives the requested information.
++*/
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcePOOL vidMemPool;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Info=0x%x",
++ Kernel, ProcessID, Type, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Deocde pool. */
++ vidMemPool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT;
++
++ Type &= gcdDATABASE_TYPE_MASK;
++
++ /* Find the database. */
++ if(Type != gcvDB_IDLE)
++ {
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(Kernel, ProcessID, LastProcessID, &database));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE));
++
++ /* Get pointer to counters. */
++ switch (Type)
++ {
++ case gcvDB_VIDEO_MEMORY:
++ if (vidMemPool != gcvPOOL_UNKNOWN)
++ {
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMemPool[vidMemPool],
++ gcmSIZEOF(database->vidMemPool[vidMemPool]));
++ }
++ else
++ {
++ gckOS_MemCopy(&Info->counters,
++ &database->vidMem,
++ gcmSIZEOF(database->vidMem));
++ }
++ break;
++
++ case gcvDB_NON_PAGED:
++ gckOS_MemCopy(&Info->counters,
++ &database->nonPaged,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_CONTIGUOUS:
++ gckOS_MemCopy(&Info->counters,
++ &database->contiguous,
++ gcmSIZEOF(database->vidMem));
++ break;
++
++ case gcvDB_MAP_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapMemory,
++ gcmSIZEOF(database->mapMemory));
++ break;
++
++ case gcvDB_MAP_USER_MEMORY:
++ gckOS_MemCopy(&Info->counters,
++ &database->mapUserMemory,
++ gcmSIZEOF(database->mapUserMemory));
++ break;
++
++ case gcvDB_COMMAND_BUFFER:
++ gckOS_MemCopy(&Info->counters,
++ &database->virtualCommandBuffer,
++ gcmSIZEOF(database->virtualCommandBuffer));
++ break;
++
++ default:
++ break;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex));
++ }
++ else
++ {
++ Info->time = Kernel->db->idleTime;
++ Kernel->db->idleTime = 0;
++ }
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_FindHandleDatbase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gctPOINTER * HandleDatabase,
++ OUT gctPOINTER * HandleDatabaseMutex
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d",
++ Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ *HandleDatabase = database->handleDatabase;
++ *HandleDatabaseMutex = database->handleDatabaseMutex;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckKERNEL_GetProcessMMU(
++ IN gckKERNEL Kernel,
++ OUT gckMMU * Mmu
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctUINT32 processID;
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, processID, gcvFALSE, &database));
++
++ *Mmu = database->mmu;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++#endif
++
++#if gcdSECURE_USER
++/*******************************************************************************
++** gckKERNEL_GetProcessDBCache
++**
++** Get teh secure cache from a process database.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to a gckKERNEL object.
++**
++** gctUINT32 ProcessID
++** Process ID used to identify the database.
++**
++** OUTPUT:
++**
++** gcskSECURE_CACHE_PTR * Cache
++** Pointer to a variable that receives the secure cache pointer.
++*/
++gceSTATUS
++gckKERNEL_GetProcessDBCache(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcskSECURE_CACHE_PTR * Cache
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Cache != gcvNULL);
++
++ /* Find the database. */
++ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ /* Return the pointer to the cache. */
++ *Cache = &database->cache;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Cache=0x%x", *Cache);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ )
++{
++ gcsDATABASE_PTR database;
++ gctINT i, pid;
++ gctUINT8 name[24];
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** PROCESS DB DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkPRINT_N(8, "%-8s%s\n", "PID", "NAME");
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ for (database = Kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ pid = database->processID;
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ gcmkPRINT_N(8, "%-8d%s\n", pid, name);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_DumpCounter(
++ IN gcsDATABASE_COUNTERS * Counter,
++ IN gctCONST_STRING Name
++ )
++{
++ gcmkPRINT("%s:", Name);
++ gcmkPRINT(" Currently allocated : %10lld", Counter->bytes);
++ gcmkPRINT(" Maximum allocated : %10lld", Counter->maxBytes);
++ gcmkPRINT(" Total allocated : %10lld", Counter->totalBytes);
++}
++
++gceSTATUS
++gckKERNEL_DumpVidMemUsage(
++ IN gckKERNEL Kernel,
++ IN gctINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gcsDATABASE_COUNTERS * counter;
++ gctUINT32 i = 0;
++
++ static gctCONST_STRING surfaceTypes[] = {
++ "UNKNOWN",
++ "INDEX",
++ "VERTEX",
++ "TEXTURE",
++ "RENDER_TARGET",
++ "DEPTH",
++ "BITMAP",
++ "TILE_STATUS",
++ "IMAGE",
++ "MASK",
++ "SCISSOR",
++ "HIERARCHICAL_DEPTH",
++ };
++
++ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d",
++ Kernel, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Find the database. */
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database));
++
++ gcmkPRINT("VidMem Usage (Process %d):", ProcessID);
++
++ /* Get pointer to counters. */
++ counter = &database->vidMem;
++
++ _DumpCounter(counter, "Total Video Memory");
++
++ for (i = 0; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ _DumpCounter(counter, surfaceTypes[i]);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c 2016-06-19 22:11:55.225145256 +0200
+@@ -0,0 +1,2785 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include <gc_hal_kernel_debug.h>
++
++/******************************************************************************\
++******************************** Debug Variables *******************************
++\******************************************************************************/
++
++static gceSTATUS _lastError = gcvSTATUS_OK;
++static gctUINT32 _debugLevel = gcvLEVEL_ERROR;
++/*
++_debugZones config value
++Please Reference define in gc_hal_base.h
++*/
++static gctUINT32 _debugZones = gcvZONE_NONE;
++
++/******************************************************************************\
++********************************* Debug Switches *******************************
++\******************************************************************************/
++
++/*
++ gcdBUFFERED_OUTPUT
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console. gcdBUFFERED_SIZE determines the size of the buffer.
++*/
++#define gcdBUFFERED_OUTPUT 0
++
++/*
++ gcdBUFFERED_SIZE
++
++ When set to non-zero, all output is collected into a buffer with the
++ specified size. Once the buffer gets full, the debug buffer will be
++ printed to the console.
++*/
++#define gcdBUFFERED_SIZE (1024 * 1024 * 2)
++
++/*
++ gcdDMA_BUFFER_COUNT
++
++ If greater then zero, the debugger will attempt to find the command buffer
++ where DMA is currently executing and then print this buffer and
++ (gcdDMA_BUFFER_COUNT - 1) buffers before the current one. If set to zero
++ or the current buffer is not found, all buffers are printed.
++*/
++#define gcdDMA_BUFFER_COUNT 0
++
++/*
++ gcdTHREAD_BUFFERS
++
++ When greater then one, will accumulate messages from the specified number
++ of threads in separate output buffers.
++*/
++#define gcdTHREAD_BUFFERS 1
++
++/*
++ gcdENABLE_OVERFLOW
++
++ When set to non-zero, and the output buffer gets full, instead of being
++ printed, it will be allowed to overflow removing the oldest messages.
++*/
++#define gcdENABLE_OVERFLOW 1
++
++/*
++ gcdSHOW_LINE_NUMBER
++
++ When enabledm each print statement will be preceeded with the current
++ line number.
++*/
++#define gcdSHOW_LINE_NUMBER 0
++
++/*
++ gcdSHOW_PROCESS_ID
++
++ When enabledm each print statement will be preceeded with the current
++ process ID.
++*/
++#define gcdSHOW_PROCESS_ID 0
++
++/*
++ gcdSHOW_THREAD_ID
++
++ When enabledm each print statement will be preceeded with the current
++ thread ID.
++*/
++#define gcdSHOW_THREAD_ID 0
++
++/*
++ gcdSHOW_TIME
++
++ When enabled each print statement will be preceeded with the current
++ high-resolution time.
++*/
++#define gcdSHOW_TIME 0
++
++
++/******************************************************************************\
++****************************** Miscellaneous Macros ****************************
++\******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmDBGASSERT(Expression, Format, Value) \
++ if (!(Expression)) \
++ { \
++ _DirectPrint( \
++ "*** gcmDBGASSERT ***************************\n" \
++ " function : %s\n" \
++ " line : %d\n" \
++ " expression : " #Expression "\n" \
++ " actual value : " Format "\n", \
++ __FUNCTION__, __LINE__, Value \
++ ); \
++ }
++#else
++# define gcmDBGASSERT(Expression, Format, Value)
++#endif
++
++#define gcmPTRALIGNMENT(Pointer, Alignemnt) \
++( \
++ gcmALIGN(gcmPTR2INT32(Pointer), Alignemnt) - gcmPTR2INT32(Pointer) \
++)
++
++#if gcdALIGNBYSIZE
++# define gcmISALIGNED(Offset, Alignment) \
++ (((Offset) & ((Alignment) - 1)) == 0)
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment) \
++ Pointer = (Type) gcmINT2PTR(gcmALIGN(gcmPTR2INT32(Pointer), Alignment))
++#else
++# define gcmISALIGNED(Offset, Alignment) \
++ gcvTRUE
++
++# define gcmkALIGNPTR(Type, Pointer, Alignment)
++#endif
++
++#define gcmALIGNSIZE(Offset, Size) \
++ ((Size - Offset) + Size)
++
++#define gcdHAVEPREFIX \
++( \
++ gcdSHOW_TIME \
++ || gcdSHOW_LINE_NUMBER \
++ || gcdSHOW_PROCESS_ID \
++ || gcdSHOW_THREAD_ID \
++)
++
++#if gcdHAVEPREFIX
++
++# define gcdOFFSET 0
++
++#if gcdSHOW_TIME
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdTIMESIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdTIMESIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdTIMEFORMAT "0x%016llX"
++# else
++# define gcdTIMEFORMAT ", 0x%016llX"
++# endif
++# else
++# define gcdTIMESIZE 0
++# define gcdTIMEFORMAT
++# endif
++
++#if gcdSHOW_LINE_NUMBER
++#if gcmISALIGNED(gcdOFFSET, 8)
++# define gcdNUMSIZE gcmSIZEOF(gctUINT64)
++# elif gcdOFFSET == 4
++# define gcdNUMSIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64))
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 8
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64)
++# define gcdNUMFORMAT "%8llu"
++# else
++# define gcdNUMFORMAT ", %8llu"
++# endif
++# else
++# define gcdNUMSIZE 0
++# define gcdNUMFORMAT
++# endif
++
++#if gcdSHOW_PROCESS_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdPIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPIDFORMAT "pid=%5d"
++# else
++# define gcdPIDFORMAT ", pid=%5d"
++# endif
++# else
++# define gcdPIDSIZE 0
++# define gcdPIDFORMAT
++# endif
++
++#if gcdSHOW_THREAD_ID
++#if gcmISALIGNED(gcdOFFSET, 4)
++# define gcdTIDSIZE gcmSIZEOF(gctUINT32)
++# else
++# error "Unexpected offset value."
++# endif
++# undef gcdOFFSET
++# define gcdOFFSET 4
++#if !defined(gcdPREFIX_LEADER)
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdTIDFORMAT "tid=%5d"
++# else
++# define gcdTIDFORMAT ", tid=%5d"
++# endif
++# else
++# define gcdTIDSIZE 0
++# define gcdTIDFORMAT
++# endif
++
++# define gcdPREFIX_SIZE \
++ ( \
++ gcdTIMESIZE \
++ + gcdNUMSIZE \
++ + gcdPIDSIZE \
++ + gcdTIDSIZE \
++ )
++
++ static const char * _prefixFormat =
++ "["
++ gcdTIMEFORMAT
++ gcdNUMFORMAT
++ gcdPIDFORMAT
++ gcdTIDFORMAT
++ "] ";
++
++#else
++
++# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32)
++# define gcdPREFIX_SIZE 0
++
++#endif
++
++/* Assumed largest variable argument leader size. */
++#define gcdVARARG_LEADER gcmSIZEOF(gctUINT64)
++
++/* Alignnments. */
++#if gcdALIGNBYSIZE
++# define gcdPREFIX_ALIGNMENT gcdPREFIX_LEADER
++# define gcdVARARG_ALIGNMENT gcdVARARG_LEADER
++#else
++# define gcdPREFIX_ALIGNMENT 0
++# define gcdVARARG_ALIGNMENT 0
++#endif
++
++#if gcdBUFFERED_OUTPUT
++# define gcdOUTPUTPREFIX _AppendPrefix
++# define gcdOUTPUTSTRING _AppendString
++# define gcdOUTPUTCOPY _AppendCopy
++# define gcdOUTPUTBUFFER _AppendBuffer
++#else
++# define gcdOUTPUTPREFIX _PrintPrefix
++# define gcdOUTPUTSTRING _PrintString
++# define gcdOUTPUTCOPY _PrintString
++# define gcdOUTPUTBUFFER _PrintBuffer
++#endif
++
++/******************************************************************************\
++****************************** Private Structures ******************************
++\******************************************************************************/
++
++typedef enum _gceBUFITEM
++{
++ gceBUFITEM_NONE,
++ gcvBUFITEM_PREFIX,
++ gcvBUFITEM_STRING,
++ gcvBUFITEM_COPY,
++ gcvBUFITEM_BUFFER
++}
++gceBUFITEM;
++
++/* Common item head/buffer terminator. */
++typedef struct _gcsBUFITEM_HEAD * gcsBUFITEM_HEAD_PTR;
++typedef struct _gcsBUFITEM_HEAD
++{
++ gceBUFITEM type;
++}
++gcsBUFITEM_HEAD;
++
++/* String prefix (for ex. [ 1,tid=0x019A]) */
++typedef struct _gcsBUFITEM_PREFIX * gcsBUFITEM_PREFIX_PTR;
++typedef struct _gcsBUFITEM_PREFIX
++{
++ gceBUFITEM type;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_PREFIX;
++
++/* Buffered string. */
++typedef struct _gcsBUFITEM_STRING * gcsBUFITEM_STRING_PTR;
++typedef struct _gcsBUFITEM_STRING
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctCONST_STRING message;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_STRING;
++
++/* Buffered string (copy of the string is included with the record). */
++typedef struct _gcsBUFITEM_COPY * gcsBUFITEM_COPY_PTR;
++typedef struct _gcsBUFITEM_COPY
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gctPOINTER messageData;
++ gctUINT messageDataSize;
++}
++gcsBUFITEM_COPY;
++
++/* Memory buffer. */
++typedef struct _gcsBUFITEM_BUFFER * gcsBUFITEM_BUFFER_PTR;
++typedef struct _gcsBUFITEM_BUFFER
++{
++ gceBUFITEM type;
++ gctINT indent;
++ gceDUMP_BUFFER bufferType;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ gctUINT32 dmaAddress;
++#endif
++
++ gctUINT dataSize;
++ gctUINT32 address;
++#if gcdHAVEPREFIX
++ gctPOINTER prefixData;
++#endif
++}
++gcsBUFITEM_BUFFER;
++
++typedef struct _gcsBUFFERED_OUTPUT * gcsBUFFERED_OUTPUT_PTR;
++typedef struct _gcsBUFFERED_OUTPUT
++{
++#if gcdTHREAD_BUFFERS > 1
++ gctUINT32 threadID;
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ gctUINT64 lineNumber;
++#endif
++
++ gctINT indent;
++
++#if gcdBUFFERED_OUTPUT
++ gctINT start;
++ gctINT index;
++ gctINT count;
++ gctUINT8 buffer[gcdBUFFERED_SIZE];
++#endif
++
++ gcsBUFFERED_OUTPUT_PTR prev;
++ gcsBUFFERED_OUTPUT_PTR next;
++}
++gcsBUFFERED_OUTPUT;
++
++typedef gctUINT (* gcfPRINTSTRING) (
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++typedef gctINT (* gcfGETITEMSIZE) (
++ IN gcsBUFITEM_HEAD_PTR Item
++ );
++
++/******************************************************************************\
++******************************* Private Variables ******************************
++\******************************************************************************/
++
++static gcsBUFFERED_OUTPUT _outputBuffer[gcdTHREAD_BUFFERS];
++static gcsBUFFERED_OUTPUT_PTR _outputBufferHead = gcvNULL;
++static gcsBUFFERED_OUTPUT_PTR _outputBufferTail = gcvNULL;
++
++/******************************************************************************\
++****************************** Item Size Functions *****************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++static gctINT
++_GetTerminatorItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctINT
++_GetPrefixItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item = (gcsBUFITEM_PREFIX_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctINT
++_GetStringItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item = (gcsBUFITEM_STRING_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetCopyItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item = (gcsBUFITEM_COPY_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++ return vlen + item->messageDataSize;
++}
++
++static gctINT
++_GetBufferItemSize(
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item;
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfGETITEMSIZE _itemSize[] =
++{
++ _GetTerminatorItemSize,
++ _GetPrefixItemSize,
++ _GetStringItemSize,
++ _GetCopyItemSize,
++ _GetBufferItemSize
++};
++#endif
++
++/******************************************************************************\
++******************************* Printing Functions *****************************
++\******************************************************************************/
++
++#if gcdDEBUG || gcdBUFFERED_OUTPUT
++static void
++_DirectPrint(
++ gctCONST_STRING Message,
++ ...
++ )
++{
++ gctINT len;
++ char buffer[768];
++ gctARGUMENTS arguments;
++
++ gcmkARGUMENTS_START(arguments, Message);
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), Message, &arguments);
++ gcmkARGUMENTS_END(arguments);
++
++ buffer[len] = '\0';
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static int
++_AppendIndent(
++ IN gctINT Indent,
++ IN char * Buffer,
++ IN int BufferSize
++ )
++{
++ gctINT i;
++
++ gctINT len = 0;
++ gctINT indent = Indent % 40;
++
++ for (i = 0; i < indent; i += 1)
++ {
++ Buffer[len++] = ' ';
++ }
++
++ if (indent != Indent)
++ {
++ len += gcmkSPRINTF(
++ Buffer + len, BufferSize - len, " <%d> ", Indent
++ );
++
++ Buffer[len] = '\0';
++ }
++
++ return len;
++}
++
++#if gcdHAVEPREFIX
++static void
++_PrintPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Format the string. */
++ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, Data);
++ buffer[len] = '\0';
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++#endif
++
++static void
++_PrintString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ char buffer[768];
++ gctINT len;
++
++ /* Append the indent string. */
++ len = _AppendIndent(Indent, buffer, gcmSIZEOF(buffer));
++
++ /* Format the string. */
++ len += gcmkVSPRINTF(buffer + len, gcmSIZEOF(buffer) - len, Message, Data);
++ buffer[len] = '\0';
++
++ /* Add end-of-line if missing. */
++ if (buffer[len - 1] != '\n')
++ {
++ buffer[len++] = '\n';
++ buffer[len] = '\0';
++ }
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++}
++
++static void
++_PrintBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++ static gctCONST_STRING _titleString[] =
++ {
++ "CONTEXT BUFFER",
++ "USER COMMAND BUFFER",
++ "KERNEL COMMAND BUFFER",
++ "LINK BUFFER",
++ "WAIT LINK BUFFER",
++ ""
++ };
++
++ static const gctINT COLUMN_COUNT = 8;
++
++ gctUINT i, count, column, address;
++ gctUINT32_PTR data;
++ gctCHAR buffer[768];
++ gctUINT indent, len;
++ gctBOOL command;
++
++ /* Append space for the prefix. */
++#if gcdHAVEPREFIX
++ indent = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, PrefixData);
++ buffer[indent] = '\0';
++#else
++ indent = 0;
++#endif
++
++ /* Append the indent string. */
++ indent += _AppendIndent(
++ Indent, buffer + indent, gcmSIZEOF(buffer) - indent
++ );
++
++ switch (Type)
++ {
++ case gceDUMP_BUFFER_CONTEXT:
++ case gceDUMP_BUFFER_USER:
++ case gceDUMP_BUFFER_KERNEL:
++ case gceDUMP_BUFFER_LINK:
++ case gceDUMP_BUFFER_WAITLINK:
++ /* Form and print the title string. */
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "%s%s\n", _titleString[Type],
++ ((DmaAddress >= Address) && (DmaAddress < Address + DataSize))
++ ? " (CURRENT)" : ""
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++
++ /* This is a command buffer. */
++ command = gcvTRUE;
++ break;
++
++ case gceDUMP_BUFFER_FROM_USER:
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++
++ /* No title. */
++ break;
++
++ default:
++ gcmDBGASSERT(gcvFALSE, "%s", "invalid buffer type");
++
++ /* This is not a command buffer. */
++ command = gcvFALSE;
++ }
++
++ /* Overwrite the prefix with spaces. */
++ for (i = 0; i < indent; i += 1)
++ {
++ buffer[i] = ' ';
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ gcmkSPRINTF2(
++ buffer + indent, gcmSIZEOF(buffer) - indent,
++ "@[kernel.command %08X %08X\n", Address, DataSize
++ );
++
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Terminate the string. */
++ buffer[indent] = '\0';
++ }
++
++ /* Get initial address. */
++ address = Address;
++
++ /* Cast the data pointer. */
++ data = (gctUINT32_PTR) Data;
++
++ /* Compute the number of double words. */
++ count = DataSize / gcmSIZEOF(gctUINT32);
++
++ /* Print the buffer. */
++ for (i = 0, len = indent, column = 0; i < count; i += 1)
++ {
++ /* Append the address. */
++ if (column == 0)
++ {
++ len += gcmkSPRINTF(
++ buffer + len, gcmSIZEOF(buffer) - len, "0x%08X:", address
++ );
++ }
++
++ /* Append the data value. */
++ len += gcmkSPRINTF2(
++ buffer + len, gcmSIZEOF(buffer) - len, "%c%08X",
++ (address == DmaAddress)? '>' : ' ', data[i]
++ );
++
++ buffer[len] = '\0';
++
++ /* Update the address. */
++ address += gcmSIZEOF(gctUINT32);
++
++ /* Advance column count. */
++ column += 1;
++
++ /* End of line? */
++ if ((column % COLUMN_COUNT) == 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++
++ /* Reset. */
++ len = indent;
++ column = 0;
++ }
++ }
++
++ /* Print the last partial string. */
++ if (column != 0)
++ {
++ /* Append EOL. */
++ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n");
++
++ /* Print the string. */
++ gcmkOUTPUT_STRING(buffer);
++ }
++
++ /* Form and print the opening string. */
++ if (command)
++ {
++ buffer[indent] = '\0';
++ gcmkSTRCAT(buffer, gcmSIZEOF(buffer), "] -- command\n");
++ gcmkOUTPUT_STRING(buffer);
++ }
++}
++
++#if gcdBUFFERED_OUTPUT
++static gctUINT
++_PrintNone(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_HEAD);
++}
++
++static gctUINT
++_PrintPrefixWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gcsBUFITEM_PREFIX_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_PREFIX_PTR) Item;
++
++ /* Print the message. */
++ _PrintPrefix(OutputBuffer, item->prefixData);
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE;
++#else
++ return gcmSIZEOF(gcsBUFITEM_PREFIX);
++#endif
++}
++
++static gctUINT
++_PrintStringWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_STRING_PTR item;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_STRING_PTR) Item;
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, item->message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintCopyWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++ gcsBUFITEM_COPY_PTR item;
++ gctCONST_STRING message;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_COPY_PTR) Item;
++
++ /* Determine the string pointer. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Print the message. */
++ _PrintString(
++ OutputBuffer,
++ item->indent, message, item->messageDataSize, item->messageData
++ );
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + item->messageDataSize;
++}
++
++static gctUINT
++_PrintBufferWrapper(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gcsBUFITEM_HEAD_PTR Item
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctPOINTER data;
++ gctUINT vlen;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Compute the data address. */
++ data = ((gctUINT8_PTR) item->prefixData) + gcdPREFIX_SIZE;
++
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, item->prefixData,
++ data, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Compute the size of the variable portion of the structure. */
++ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item);
++
++ /* Return the size of the node. */
++ return vlen + gcdPREFIX_SIZE + item->dataSize;
++#else
++ gctUINT32 dmaAddress;
++ gcsBUFITEM_BUFFER_PTR item;
++
++ /* Get access to the data. */
++ item = (gcsBUFITEM_BUFFER_PTR) Item;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ dmaAddress = item->dmaAddress;
++#else
++ dmaAddress = 0xFFFFFFFF;
++#endif
++
++ if (dmaAddress != 0)
++ {
++ /* Print buffer. */
++ _PrintBuffer(
++ OutputBuffer,
++ item->indent, gcvNULL,
++ item + 1, item->address, item->dataSize,
++ item->bufferType, dmaAddress
++ );
++ }
++
++ /* Return the size of the node. */
++ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize;
++#endif
++}
++
++static gcfPRINTSTRING _printArray[] =
++{
++ _PrintNone,
++ _PrintPrefixWrapper,
++ _PrintStringWrapper,
++ _PrintCopyWrapper,
++ _PrintBufferWrapper
++};
++#endif
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++#if gcdBUFFERED_OUTPUT
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++static gcsBUFITEM_BUFFER_PTR
++_FindCurrentDMABuffer(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR dmaCurrent;
++
++ /* Reset the current buffer. */
++ dmaCurrent = gcvNULL;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ if ((DmaAddress >= buffer->address) &&
++ (DmaAddress < buffer->address + buffer->dataSize))
++ {
++ dmaCurrent = buffer;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Return result. */
++ return dmaCurrent;
++}
++
++static void
++_EnableAllDMABuffers(
++ void
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Enable the buffer. */
++ buffer->dmaAddress = ~0U;
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++}
++
++static void
++_EnableDMABuffers(
++ gctUINT32 DmaAddress,
++ gcsBUFITEM_BUFFER_PTR CurrentDMABuffer
++ )
++{
++ gctINT i, skip, index;
++ gcsBUFITEM_HEAD_PTR item;
++ gcsBUFITEM_BUFFER_PTR buffers[gcdDMA_BUFFER_COUNT];
++
++ /* Reset buffer pointers. */
++ gckOS_ZeroMemory(buffers, gcmSIZEOF(buffers));
++
++ /* Set the current buffer index. */
++ index = -1;
++
++ /* Get the first stored item. */
++ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start];
++
++ /* Run through all items until the current DMA buffer is found. */
++ for (i = 0; i < _outputBufferHead->count; i += 1)
++ {
++ /* Buffer item? */
++ if (item->type == gcvBUFITEM_BUFFER)
++ {
++ /* Advance the index. */
++ index = (index + 1) % gcdDMA_BUFFER_COUNT;
++
++ /* Add to the buffer array. */
++ buffers[index] = (gcsBUFITEM_BUFFER_PTR) item;
++
++ /* Stop if this is the current DMA buffer. */
++ if ((gcsBUFITEM_BUFFER_PTR) item == CurrentDMABuffer)
++ {
++ break;
++ }
++ }
++
++ /* Get the item size and skip it. */
++ skip = (* _itemSize[item->type]) (item);
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ /* End of the buffer? Wrap around. */
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer;
++ }
++ }
++
++ /* Enable the found buffers. */
++ gcmDBGASSERT(index != -1, "%d", index);
++
++ for (i = 0; i < gcdDMA_BUFFER_COUNT; i += 1)
++ {
++ if (buffers[index] == gcvNULL)
++ {
++ break;
++ }
++
++ buffers[index]->dmaAddress = DmaAddress;
++
++ index -= 1;
++
++ if (index == -1)
++ {
++ index = gcdDMA_BUFFER_COUNT - 1;
++ }
++ }
++}
++#endif
++
++static void
++_Flush(
++ gctUINT32 DmaAddress
++ )
++{
++ gctINT i, skip;
++ gcsBUFITEM_HEAD_PTR item;
++
++ gcsBUFFERED_OUTPUT_PTR outputBuffer = _outputBufferHead;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ if ((outputBuffer != gcvNULL) && (outputBuffer->count != 0))
++ {
++ /* Find the current DMA buffer. */
++ gcsBUFITEM_BUFFER_PTR dmaCurrent = _FindCurrentDMABuffer(DmaAddress);
++
++ /* Was the current buffer found? */
++ if (dmaCurrent == gcvNULL)
++ {
++ /* No, print all buffers. */
++ _EnableAllDMABuffers();
++ }
++ else
++ {
++ /* Yes, enable only specified number of buffers. */
++ _EnableDMABuffers(DmaAddress, dmaCurrent);
++ }
++ }
++#endif
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->count != 0)
++ {
++ _DirectPrint("********************************************************************************\n");
++ _DirectPrint("FLUSHING DEBUG OUTPUT BUFFER (%d elements).\n", outputBuffer->count);
++ _DirectPrint("********************************************************************************\n");
++
++ item = (gcsBUFITEM_HEAD_PTR) &outputBuffer->buffer[outputBuffer->start];
++
++ for (i = 0; i < outputBuffer->count; i += 1)
++ {
++ skip = (* _printArray[item->type]) (outputBuffer, item);
++
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) outputBuffer->buffer;
++ }
++ }
++
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++}
++
++static gcsBUFITEM_HEAD_PTR
++_AllocateItem(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Size
++ )
++{
++ gctINT skip;
++ gcsBUFITEM_HEAD_PTR item, next;
++
++#if gcdENABLE_OVERFLOW
++ if (
++ (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ ||
++ (
++ (OutputBuffer->index < OutputBuffer->start) &&
++ (OutputBuffer->index + Size >= OutputBuffer->start)
++ )
++ )
++ {
++ if (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ if (OutputBuffer->index < OutputBuffer->start)
++ {
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (item->type != gceBUFITEM_NONE)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++ }
++
++ OutputBuffer->start = 0;
++ }
++
++ OutputBuffer->index = 0;
++ }
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start];
++
++ while (OutputBuffer->start - OutputBuffer->index <= Size)
++ {
++ skip = (* _itemSize[item->type]) (item);
++
++ OutputBuffer->start += skip;
++ OutputBuffer->count -= 1;
++
++ item->type = gceBUFITEM_NONE;
++ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip);
++
++ if (item->type == gceBUFITEM_NONE)
++ {
++ OutputBuffer->start = 0;
++ break;
++ }
++ }
++ }
++#else
++ if (OutputBuffer->index + Size > gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD))
++ {
++ _DirectPrint("\nMessage buffer full; forcing message flush.\n\n");
++ _Flush(~0U);
++ }
++#endif
++
++ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->index];
++
++ OutputBuffer->index += Size;
++ OutputBuffer->count += 1;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + Size);
++ next->type = gceBUFITEM_NONE;
++
++ return item;
++}
++
++#if gcdALIGNBYSIZE
++static void
++_FreeExtraSpace(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Item,
++ IN gctINT ItemSize,
++ IN gctINT FreeSize
++ )
++{
++ gcsBUFITEM_HEAD_PTR next;
++
++ OutputBuffer->index -= FreeSize;
++
++ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) Item + ItemSize);
++ next->type = gceBUFITEM_NONE;
++}
++#endif
++
++#if gcdHAVEPREFIX
++static void
++_AppendPrefix(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_PREFIX_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_PREFIX)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_PREFIX_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_PREFIX;
++ item->prefixData = prefixData;
++
++ /* Copy argument value. */
++ memcpy(prefixData, Data, gcdPREFIX_SIZE);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_PREFIX) + gcdPREFIX_SIZE + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++#endif
++
++static void
++_AppendString(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_STRING_PTR item;
++ gctINT allocSize;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_STRING)
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_STRING_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) (item + 1);
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_STRING;
++ item->indent = Indent;
++ item->message = Message;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size = gcmSIZEOF(gcsBUFITEM_STRING) + ArgumentSize + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendCopy(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctCONST_STRING Message,
++ IN gctUINT ArgumentSize,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR messageData;
++ gcsBUFITEM_COPY_PTR item;
++ gctINT allocSize;
++ gctINT messageLength;
++ gctCONST_STRING message;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ /* Get the length of the string. */
++ messageLength = strlen(Message) + 1;
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + gcdVARARG_ALIGNMENT;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_COPY_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Determine the message placement. */
++ message = (gctCONST_STRING) (item + 1);
++
++ /* Compute the initial message data pointer. */
++ messageData = (gctUINT8_PTR) message + messageLength;
++
++ /* Align the data pointer as necessary. */
++#if gcdALIGNBYSIZE
++ if (ArgumentSize == 0)
++ {
++ alignment = 0;
++ }
++ else
++ {
++ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT);
++ messageData += alignment;
++ }
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_COPY;
++ item->indent = Indent;
++ item->messageData = messageData;
++ item->messageDataSize = ArgumentSize;
++
++ /* Copy the message. */
++ memcpy((gctPOINTER) message, Message, messageLength);
++
++ /* Copy argument value. */
++ if (ArgumentSize != 0)
++ {
++ memcpy(messageData, Data, ArgumentSize);
++ }
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_COPY)
++ + messageLength
++ + ArgumentSize
++ + alignment;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++}
++
++static void
++_AppendBuffer(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctINT Indent,
++ IN gctPOINTER PrefixData,
++ IN gctPOINTER Data,
++ IN gctUINT Address,
++ IN gctUINT DataSize,
++ IN gceDUMP_BUFFER Type,
++ IN gctUINT32 DmaAddress
++ )
++{
++#if gcdHAVEPREFIX
++ gctUINT8_PTR prefixData;
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT allocSize;
++ gctPOINTER data;
++
++#if gcdALIGNBYSIZE
++ gctUINT alignment;
++ gctINT size, freeSize;
++#endif
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ allocSize
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + gcdPREFIX_ALIGNMENT
++ + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, allocSize);
++
++ /* Compute the initial prefix data pointer. */
++ prefixData = (gctUINT8_PTR) (item + 1);
++
++#if gcdALIGNBYSIZE
++ /* Align the data pointer as necessary. */
++ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT);
++ prefixData += alignment;
++#endif
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->bufferType = Type;
++ item->dataSize = DataSize;
++ item->address = Address;
++ item->prefixData = prefixData;
++
++#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1)
++ item->dmaAddress = DmaAddress;
++#endif
++
++ /* Copy prefix data. */
++ memcpy(prefixData, PrefixData, gcdPREFIX_SIZE);
++
++ /* Compute the data pointer. */
++ data = prefixData + gcdPREFIX_SIZE;
++
++ /* Copy argument value. */
++ memcpy(data, Data, DataSize);
++
++#if gcdALIGNBYSIZE
++ /* Compute the actual node size. */
++ size
++ = gcmSIZEOF(gcsBUFITEM_BUFFER)
++ + gcdPREFIX_SIZE
++ + alignment
++ + DataSize;
++
++ /* Free extra memory if any. */
++ freeSize = allocSize - size;
++ if (freeSize != 0)
++ {
++ _FreeExtraSpace(OutputBuffer, item, size, freeSize);
++ }
++#endif
++#else
++ gcsBUFITEM_BUFFER_PTR item;
++ gctINT size;
++
++ gcmDBGASSERT(DataSize != 0, "%d", DataSize);
++ gcmDBGASSERT(Data != gcvNULL, "%p", Data);
++
++ /* Determine the maximum item size. */
++ size = gcmSIZEOF(gcsBUFITEM_BUFFER) + DataSize;
++
++ /* Allocate prefix item. */
++ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, size);
++
++ /* Set item data. */
++ item->type = gcvBUFITEM_BUFFER;
++ item->indent = Indent;
++ item->dataSize = DataSize;
++ item->address = Address;
++
++ /* Copy argument value. */
++ memcpy(item + 1, Data, DataSize);
++#endif
++}
++#endif
++
++static gcmINLINE void
++_InitBuffers(
++ void
++ )
++{
++ int i;
++
++ if (_outputBufferHead == gcvNULL)
++ {
++ for (i = 0; i < gcdTHREAD_BUFFERS; i += 1)
++ {
++ if (_outputBufferTail == gcvNULL)
++ {
++ _outputBufferHead = &_outputBuffer[i];
++ }
++ else
++ {
++ _outputBufferTail->next = &_outputBuffer[i];
++ }
++
++#if gcdTHREAD_BUFFERS > 1
++ _outputBuffer[i].threadID = ~0U;
++#endif
++
++ _outputBuffer[i].prev = _outputBufferTail;
++ _outputBuffer[i].next = gcvNULL;
++
++ _outputBufferTail = &_outputBuffer[i];
++ }
++ }
++}
++
++static gcmINLINE gcsBUFFERED_OUTPUT_PTR
++_GetOutputBuffer(
++ void
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++
++#if gcdTHREAD_BUFFERS > 1
++ /* Get the current thread ID. */
++ gctUINT32 ThreadID = gcmkGETTHREADID();
++
++ /* Locate the output buffer for the thread. */
++ outputBuffer = _outputBufferHead;
++
++ while (outputBuffer != gcvNULL)
++ {
++ if (outputBuffer->threadID == ThreadID)
++ {
++ break;
++ }
++
++ outputBuffer = outputBuffer->next;
++ }
++
++ /* No matching buffer found? */
++ if (outputBuffer == gcvNULL)
++ {
++ /* Get the tail for the buffer. */
++ outputBuffer = _outputBufferTail;
++
++ /* Move it to the head. */
++ _outputBufferTail = _outputBufferTail->prev;
++ _outputBufferTail->next = gcvNULL;
++
++ outputBuffer->prev = gcvNULL;
++ outputBuffer->next = _outputBufferHead;
++
++ _outputBufferHead->prev = outputBuffer;
++ _outputBufferHead = outputBuffer;
++
++ /* Reset the buffer. */
++ outputBuffer->threadID = ThreadID;
++#if gcdBUFFERED_OUTPUT
++ outputBuffer->start = 0;
++ outputBuffer->index = 0;
++ outputBuffer->count = 0;
++#endif
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber = 0;
++#endif
++ }
++#else
++ outputBuffer = _outputBufferHead;
++#endif
++
++ return outputBuffer;
++}
++
++static gcmINLINE int _GetArgumentSize(
++ IN gctCONST_STRING Message
++ )
++{
++ int i, count;
++
++ gcmDBGASSERT(Message != gcvNULL, "%p", Message);
++
++ for (i = 0, count = 0; Message[i]; i += 1)
++ {
++ if (Message[i] == '%')
++ {
++ count += 1;
++ }
++ }
++
++ return count * gcmSIZEOF(gctUINT32);
++}
++
++#if gcdHAVEPREFIX
++static void
++_InitPrefixData(
++ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer,
++ IN gctPOINTER Data
++ )
++{
++ gctUINT8_PTR data = (gctUINT8_PTR) Data;
++
++#if gcdSHOW_TIME
++ {
++ gctUINT64 time;
++ gckOS_GetProfileTick(&time);
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = time;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_LINE_NUMBER
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64));
++ * ((gctUINT64_PTR) data) = OutputBuffer->lineNumber;
++ data += gcmSIZEOF(gctUINT64);
++ }
++#endif
++
++#if gcdSHOW_PROCESS_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETPROCESSID();
++ data += gcmSIZEOF(gctUINT32);
++ }
++#endif
++
++#if gcdSHOW_THREAD_ID
++ {
++ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32));
++ * ((gctUINT32_PTR) data) = gcmkGETTHREADID();
++ }
++#endif
++}
++#endif
++
++static void
++_Print(
++ IN gctUINT ArgumentSize,
++ IN gctBOOL CopyMessage,
++ IN gctCONST_STRING Message,
++ IN gctARGUMENTS * Arguments
++ )
++{
++ gcsBUFFERED_OUTPUT_PTR outputBuffer;
++ gcmkDECLARE_LOCK(lockHandle);
++
++ gcmkLOCKSECTION(lockHandle);
++
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Print prefix. */
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print the prefix. */
++ gcdOUTPUTPREFIX(outputBuffer, alignedPrefixData);
++ }
++#endif
++
++ /* Form the indent string. */
++ if (strncmp(Message, "--", 2) == 0)
++ {
++ outputBuffer->indent -= 2;
++ }
++
++ /* Print the message. */
++ if (CopyMessage)
++ {
++ gcdOUTPUTCOPY(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, (gctPOINTER) Arguments
++ );
++ }
++ else
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Message, ArgumentSize, ((gctPOINTER) Arguments)
++ );
++ }
++
++ /* Check increasing indent. */
++ if (strncmp(Message, "++", 2) == 0)
++ {
++ outputBuffer->indent += 2;
++ }
++
++ gcmkUNLOCKSECTION(lockHandle);
++}
++
++
++/******************************************************************************\
++********************************* Debug Macros *********************************
++\******************************************************************************/
++
++#ifdef __QNXNTO__
++
++extern volatile unsigned g_nQnxInIsrs;
++
++#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \
++{ \
++ if (atomic_add_value(&g_nQnxInIsrs, 1) == 0) \
++ { \
++ gctARGUMENTS __arguments__; \
++ gcmkARGUMENTS_START(__arguments__, Message); \
++ _Print(ArgumentSize, CopyMessage, Message, &__arguments__); \
++ gcmkARGUMENTS_END(__arguments__); \
++ } \
++ atomic_sub(&g_nQnxInIsrs, 1); \
++}
++
++#else
++
++#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \
++{ \
++ gctARGUMENTS __arguments__; \
++ gcmkARGUMENTS_START(__arguments__, Message); \
++ _Print(ArgumentSize, CopyMessage, Message, &__arguments__); \
++ gcmkARGUMENTS_END(__arguments__); \
++}
++
++#endif
++
++/******************************************************************************\
++********************************** Debug Code **********************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Print
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_PrintN
++**
++** Send a message to the debugger.
++**
++** INPUT:
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyPrint
++**
++** Send a message to the debugger. If in buffered output mode, the entire
++** message will be copied into the buffer instead of using the pointer to
++** the string.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvTRUE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DumpBuffer
++**
++** Print the contents of the specified buffer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Buffer
++** Pointer to the buffer to print.
++**
++** gctUINT Size
++** Size of the buffer.
++**
++** gceDUMP_BUFFER Type
++** Buffer type.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ )
++{
++ gctUINT32 address = 0;
++ gcsBUFFERED_OUTPUT_PTR outputBuffer = gcvNULL;
++ static gctBOOL userLocked;
++ gctCHAR *buffer = (gctCHAR*)Buffer;
++
++ gcmkDECLARE_LOCK(lockHandle);
++
++ /* Request lock when not coming from user,
++ or coming from user and not yet locked
++ and message is starting with @[. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ if ((Size > 2)
++ && (buffer[0] == '@')
++ && (buffer[1] == '['))
++ {
++ /* Beginning of a user dump. */
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvTRUE;
++ }
++ /* Else, let it pass through. */
++ }
++ else
++ {
++ gcmkLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++
++ if (Buffer != gcvNULL)
++ {
++ /* Initialize output buffer list. */
++ _InitBuffers();
++
++ /* Locate the proper output buffer. */
++ outputBuffer = _GetOutputBuffer();
++
++ /* Update the line number. */
++#if gcdSHOW_LINE_NUMBER
++ outputBuffer->lineNumber += 1;
++#endif
++
++ /* Get the physical address of the buffer. */
++ if (Type != gceDUMP_BUFFER_FROM_USER)
++ {
++ gcmkVERIFY_OK(gckOS_GetPhysicalAddress(Os, Buffer, &address));
++ }
++ else
++ {
++ address = 0;
++ }
++
++#if gcdHAVEPREFIX
++ {
++ gctUINT8_PTR alignedPrefixData;
++ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT];
++
++ /* Compute aligned pointer. */
++ alignedPrefixData = prefixData;
++ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT);
++
++ /* Initialize the prefix data. */
++ _InitPrefixData(outputBuffer, alignedPrefixData);
++
++ /* Print/schedule the buffer. */
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ alignedPrefixData, Buffer, address, Size, Type, 0
++ );
++ }
++#else
++ /* Print/schedule the buffer. */
++ if (Type == gceDUMP_BUFFER_FROM_USER)
++ {
++ gcdOUTPUTSTRING(
++ outputBuffer, outputBuffer->indent,
++ Buffer, 0, gcvNULL
++ );
++ }
++ else
++ {
++ gcdOUTPUTBUFFER(
++ outputBuffer, outputBuffer->indent,
++ gcvNULL, Buffer, address, Size, Type, 0
++ );
++ }
++#endif
++ }
++
++ /* Unlock when not coming from user,
++ or coming from user and not yet locked. */
++ if (userLocked)
++ {
++ if ((Size > 4)
++ && (buffer[0] == ']')
++ && (buffer[1] == ' ')
++ && (buffer[2] == '-')
++ && (buffer[3] == '-'))
++ {
++ /* End of a user dump. */
++ gcmkUNLOCKSECTION(lockHandle);
++ userLocked = gcvFALSE;
++ }
++ /* Else, let it pass through, don't unlock. */
++ }
++ else
++ {
++ gcmkUNLOCKSECTION(lockHandle);
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTrace
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceN
++**
++** Send a leveled message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level of message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if (Level > _debugLevel)
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZone
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugTraceZoneN
++**
++** Send a leveled and zoned message to the debugger.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** Debug level for message.
++**
++** gctUINT32 Zone
++** Debug zone for message.
++**
++** gctUINT ArgumentSize
++** The size of the optional arguments in bytes.
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ if ((Level > _debugLevel) || !(Zone & _debugZones))
++ {
++ return;
++ }
++
++ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugBreak
++**
++** Break into the debugger.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugBreak(
++ void
++ )
++{
++ gckOS_DebugTrace(gcvLEVEL_ERROR, "%s(%d)", __FUNCTION__, __LINE__);
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFatal
++**
++** Send a message to the debugger and break into the debugger.
++**
++** INPUT:
++**
++** gctCONST_STRING Message
++** Pointer to message.
++**
++** ...
++** Optional arguments.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++{
++ gcmkPRINT_VERSION();
++ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message);
++
++ /* Break into the debugger. */
++ gckOS_DebugBreak();
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevel
++**
++** Set the debug level.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ )
++{
++ _debugLevel = Level;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZone
++**
++** Set the debug zone.
++**
++** INPUT:
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ )
++{
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugLevelZone
++**
++** Set the debug level and zone.
++**
++** INPUT:
++**
++** gctUINT32 Level
++** New debug level.
++**
++** gctUINT32 Zone
++** New debug zone.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ )
++{
++ _debugLevel = Level;
++ _debugZones = Zone;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetDebugZones
++**
++** Enable or disable debug zones.
++**
++** INPUT:
++**
++** gctUINT32 Zones
++** Debug zones to enable or disable.
++**
++** gctBOOL Enable
++** Set to gcvTRUE to enable the zones (or the Zones with the current
++** zones) or gcvFALSE to disable the specified Zones.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ )
++{
++ if (Enable)
++ {
++ /* Enable the zones. */
++ _debugZones |= Zones;
++ }
++ else
++ {
++ /* Disable the zones. */
++ _debugZones &= ~Zones;
++ }
++}
++
++/*******************************************************************************
++**
++** gckOS_Verify
++**
++** Called to verify the result of a function call.
++**
++** INPUT:
++**
++** gceSTATUS Status
++** Function call result.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_Verify(
++ IN gceSTATUS status
++ )
++{
++ _lastError = status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DebugFlush
++**
++** Force messages to be flushed out.
++**
++** INPUT:
++**
++** gctCONST_STRING CallerName
++** Name of the caller function.
++**
++** gctUINT LineNumber
++** Line number of the caller.
++**
++** gctUINT32 DmaAddress
++** The current DMA address or ~0U to ignore.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ )
++{
++#if gcdBUFFERED_OUTPUT
++ _DirectPrint("\nFlush requested by %s(%d).\n\n", CallerName, LineNumber);
++ _Flush(DmaAddress);
++#endif
++}
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ )
++{
++ switch (status)
++ {
++ case gcvSTATUS_OK:
++ return "gcvSTATUS_OK";
++ case gcvSTATUS_TRUE:
++ return "gcvSTATUS_TRUE";
++ case gcvSTATUS_NO_MORE_DATA:
++ return "gcvSTATUS_NO_MORE_DATA";
++ case gcvSTATUS_CACHED:
++ return "gcvSTATUS_CACHED";
++ case gcvSTATUS_MIPMAP_TOO_LARGE:
++ return "gcvSTATUS_MIPMAP_TOO_LARGE";
++ case gcvSTATUS_NAME_NOT_FOUND:
++ return "gcvSTATUS_NAME_NOT_FOUND";
++ case gcvSTATUS_NOT_OUR_INTERRUPT:
++ return "gcvSTATUS_NOT_OUR_INTERRUPT";
++ case gcvSTATUS_MISMATCH:
++ return "gcvSTATUS_MISMATCH";
++ case gcvSTATUS_MIPMAP_TOO_SMALL:
++ return "gcvSTATUS_MIPMAP_TOO_SMALL";
++ case gcvSTATUS_LARGER:
++ return "gcvSTATUS_LARGER";
++ case gcvSTATUS_SMALLER:
++ return "gcvSTATUS_SMALLER";
++ case gcvSTATUS_CHIP_NOT_READY:
++ return "gcvSTATUS_CHIP_NOT_READY";
++ case gcvSTATUS_NEED_CONVERSION:
++ return "gcvSTATUS_NEED_CONVERSION";
++ case gcvSTATUS_SKIP:
++ return "gcvSTATUS_SKIP";
++ case gcvSTATUS_DATA_TOO_LARGE:
++ return "gcvSTATUS_DATA_TOO_LARGE";
++ case gcvSTATUS_INVALID_CONFIG:
++ return "gcvSTATUS_INVALID_CONFIG";
++ case gcvSTATUS_CHANGED:
++ return "gcvSTATUS_CHANGED";
++ case gcvSTATUS_NOT_SUPPORT_DITHER:
++ return "gcvSTATUS_NOT_SUPPORT_DITHER";
++
++ case gcvSTATUS_INVALID_ARGUMENT:
++ return "gcvSTATUS_INVALID_ARGUMENT";
++ case gcvSTATUS_INVALID_OBJECT:
++ return "gcvSTATUS_INVALID_OBJECT";
++ case gcvSTATUS_OUT_OF_MEMORY:
++ return "gcvSTATUS_OUT_OF_MEMORY";
++ case gcvSTATUS_MEMORY_LOCKED:
++ return "gcvSTATUS_MEMORY_LOCKED";
++ case gcvSTATUS_MEMORY_UNLOCKED:
++ return "gcvSTATUS_MEMORY_UNLOCKED";
++ case gcvSTATUS_HEAP_CORRUPTED:
++ return "gcvSTATUS_HEAP_CORRUPTED";
++ case gcvSTATUS_GENERIC_IO:
++ return "gcvSTATUS_GENERIC_IO";
++ case gcvSTATUS_INVALID_ADDRESS:
++ return "gcvSTATUS_INVALID_ADDRESS";
++ case gcvSTATUS_CONTEXT_LOSSED:
++ return "gcvSTATUS_CONTEXT_LOSSED";
++ case gcvSTATUS_TOO_COMPLEX:
++ return "gcvSTATUS_TOO_COMPLEX";
++ case gcvSTATUS_BUFFER_TOO_SMALL:
++ return "gcvSTATUS_BUFFER_TOO_SMALL";
++ case gcvSTATUS_INTERFACE_ERROR:
++ return "gcvSTATUS_INTERFACE_ERROR";
++ case gcvSTATUS_NOT_SUPPORTED:
++ return "gcvSTATUS_NOT_SUPPORTED";
++ case gcvSTATUS_MORE_DATA:
++ return "gcvSTATUS_MORE_DATA";
++ case gcvSTATUS_TIMEOUT:
++ return "gcvSTATUS_TIMEOUT";
++ case gcvSTATUS_OUT_OF_RESOURCES:
++ return "gcvSTATUS_OUT_OF_RESOURCES";
++ case gcvSTATUS_INVALID_DATA:
++ return "gcvSTATUS_INVALID_DATA";
++ case gcvSTATUS_INVALID_MIPMAP:
++ return "gcvSTATUS_INVALID_MIPMAP";
++ case gcvSTATUS_NOT_FOUND:
++ return "gcvSTATUS_NOT_FOUND";
++ case gcvSTATUS_NOT_ALIGNED:
++ return "gcvSTATUS_NOT_ALIGNED";
++ case gcvSTATUS_INVALID_REQUEST:
++ return "gcvSTATUS_INVALID_REQUEST";
++ case gcvSTATUS_GPU_NOT_RESPONDING:
++ return "gcvSTATUS_GPU_NOT_RESPONDING";
++ case gcvSTATUS_TIMER_OVERFLOW:
++ return "gcvSTATUS_TIMER_OVERFLOW";
++ case gcvSTATUS_VERSION_MISMATCH:
++ return "gcvSTATUS_VERSION_MISMATCH";
++ case gcvSTATUS_LOCKED:
++ return "gcvSTATUS_LOCKED";
++ case gcvSTATUS_INTERRUPTED:
++ return "gcvSTATUS_INTERRUPTED";
++ case gcvSTATUS_DEVICE:
++ return "gcvSTATUS_DEVICE";
++ case gcvSTATUS_NOT_MULTI_PIPE_ALIGNED:
++ return "gcvSTATUS_NOT_MULTI_PIPE_ALIGNED";
++
++ /* Linker errors. */
++ case gcvSTATUS_GLOBAL_TYPE_MISMATCH:
++ return "gcvSTATUS_GLOBAL_TYPE_MISMATCH";
++ case gcvSTATUS_TOO_MANY_ATTRIBUTES:
++ return "gcvSTATUS_TOO_MANY_ATTRIBUTES";
++ case gcvSTATUS_TOO_MANY_UNIFORMS:
++ return "gcvSTATUS_TOO_MANY_UNIFORMS";
++ case gcvSTATUS_TOO_MANY_SAMPLER:
++ return "gcvSTATUS_TOO_MANY_SAMPLER";
++ case gcvSTATUS_TOO_MANY_VARYINGS:
++ return "gcvSTATUS_TOO_MANY_VARYINGS";
++ case gcvSTATUS_UNDECLARED_VARYING:
++ return "gcvSTATUS_UNDECLARED_VARYING";
++ case gcvSTATUS_VARYING_TYPE_MISMATCH:
++ return "gcvSTATUS_VARYING_TYPE_MISMATCH";
++ case gcvSTATUS_MISSING_MAIN:
++ return "gcvSTATUS_MISSING_MAIN";
++ case gcvSTATUS_NAME_MISMATCH:
++ return "gcvSTATUS_NAME_MISMATCH";
++ case gcvSTATUS_INVALID_INDEX:
++ return "gcvSTATUS_INVALID_INDEX";
++ case gcvSTATUS_UNIFORM_MISMATCH:
++ return "gcvSTATUS_UNIFORM_MISMATCH";
++ case gcvSTATUS_UNSAT_LIB_SYMBOL:
++ return "gcvSTATUS_UNSAT_LIB_SYMBOL";
++ case gcvSTATUS_TOO_MANY_SHADERS:
++ return "gcvSTATUS_TOO_MANY_SHADERS";
++ case gcvSTATUS_LINK_INVALID_SHADERS:
++ return "gcvSTATUS_LINK_INVALID_SHADERS";
++ case gcvSTATUS_CS_NO_WORKGROUP_SIZE:
++ return "gcvSTATUS_CS_NO_WORKGROUP_SIZE";
++ case gcvSTATUS_LINK_LIB_ERROR:
++ return "gcvSTATUS_LINK_LIB_ERROR";
++ case gcvSTATUS_SHADER_VERSION_MISMATCH:
++ return "gcvSTATUS_SHADER_VERSION_MISMATCH";
++ case gcvSTATUS_TOO_MANY_INSTRUCTION:
++ return "gcvSTATUS_TOO_MANY_INSTRUCTION";
++ case gcvSTATUS_SSBO_MISMATCH:
++ return "gcvSTATUS_SSBO_MISMATCH";
++ case gcvSTATUS_TOO_MANY_OUTPUT:
++ return "gcvSTATUS_TOO_MANY_OUTPUT";
++ case gcvSTATUS_TOO_MANY_INPUT:
++ return "gcvSTATUS_TOO_MANY_INPUT";
++ case gcvSTATUS_NOT_SUPPORT_CL:
++ return "gcvSTATUS_NOT_SUPPORT_CL";
++ case gcvSTATUS_NOT_SUPPORT_INTEGER:
++ return "gcvSTATUS_NOT_SUPPORT_INTEGER";
++
++ /* Compiler errors. */
++ case gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR:
++ return "gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR";
++ case gcvSTATUS_COMPILER_FE_PARSER_ERROR:
++ return "gcvSTATUS_COMPILER_FE_PARSER_ERROR";
++
++ default:
++ return "nil";
++ }
++}
++
++/*******************************************************************************
++***** Binary Trace *************************************************************
++*******************************************************************************/
++
++/*******************************************************************************
++** _VerifyMessage
++**
++** Verify a binary trace message, decode it to human readable string and print
++** it.
++**
++** ARGUMENTS:
++**
++** gctCONST_STRING Buffer
++** Pointer to buffer to store.
++**
++** gctSIZE_T Bytes
++** Buffer length.
++*/
++void
++_VerifyMessage(
++ IN gctCONST_STRING Buffer,
++ IN gctSIZE_T Bytes
++ )
++{
++ char arguments[150] = {0};
++ char format[100] = {0};
++
++ gctSTRING function;
++ gctPOINTER args;
++ gctUINT32 numArguments;
++ int i = 0;
++ gctUINT32 functionBytes;
++
++ gcsBINARY_TRACE_MESSAGE_PTR message = (gcsBINARY_TRACE_MESSAGE_PTR)Buffer;
++
++ /* Check signature. */
++ if (message->signature != 0x7FFFFFFF)
++ {
++ gcmkPRINT("Signature error");
++ return;
++ }
++
++ /* Get function name. */
++ function = (gctSTRING)&message->payload;
++ functionBytes = (gctUINT32)strlen(function) + 1;
++
++ /* Get arguments number. */
++ numArguments = message->numArguments;
++
++ /* Get arguments . */
++ args = function + functionBytes;
++
++ /* Prepare format string. */
++ while (numArguments--)
++ {
++ format[i++] = '%';
++ format[i++] = 'x';
++ format[i++] = ' ';
++ }
++
++ format[i] = '\0';
++
++ if (numArguments)
++ {
++ gcmkVSPRINTF(arguments, 150, format, (gctARGUMENTS *) &args);
++ }
++
++ gcmkPRINT("[%d](%d): %s(%d) %s",
++ message->pid,
++ message->tid,
++ function,
++ message->line,
++ arguments);
++}
++
++
++/*******************************************************************************
++** gckOS_WriteToRingBuffer
++**
++** Store a buffer to ring buffer.
++**
++** ARGUMENTS:
++**
++** gctCONST_STRING Buffer
++** Pointer to buffer to store.
++**
++** gctSIZE_T Bytes
++** Buffer length.
++*/
++void
++gckOS_WriteToRingBuffer(
++ IN gctCONST_STRING Buffer,
++ IN gctSIZE_T Bytes
++ )
++{
++
++}
++
++/*******************************************************************************
++** gckOS_BinaryTrace
++**
++** Output a binary trace message.
++**
++** ARGUMENTS:
++**
++** gctCONST_STRING Function
++** Pointer to function name.
++**
++** gctINT Line
++** Line number.
++**
++** gctCONST_STRING Text OPTIONAL
++** Optional pointer to a descriptive text.
++**
++** ...
++** Optional arguments to the descriptive text.
++*/
++void
++gckOS_BinaryTrace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text OPTIONAL,
++ ...
++ )
++{
++ static gctUINT32 messageSignature = 0x7FFFFFFF;
++ char buffer[gcdBINARY_TRACE_MESSAGE_SIZE];
++ gctUINT32 numArguments = 0;
++ gctUINT32 functionBytes;
++ gctUINT32 i = 0;
++ gctSTRING payload;
++ gcsBINARY_TRACE_MESSAGE_PTR message = (gcsBINARY_TRACE_MESSAGE_PTR)buffer;
++
++ /* Calculate arguments number. */
++ if (Text)
++ {
++ while (Text[i] != '\0')
++ {
++ if (Text[i] == '%')
++ {
++ numArguments++;
++ }
++ i++;
++ }
++ }
++
++ message->signature = messageSignature;
++ message->pid = gcmkGETPROCESSID();
++ message->tid = gcmkGETTHREADID();
++ message->line = Line;
++ message->numArguments = numArguments;
++
++ payload = (gctSTRING)&message->payload;
++
++ /* Function name. */
++ functionBytes = (gctUINT32)gcmkSTRLEN(Function) + 1;
++ gcmkMEMCPY(payload, Function, functionBytes);
++
++ /* Advance to next payload. */
++ payload += functionBytes;
++
++ /* Arguments value. */
++ if (numArguments)
++ {
++ gctARGUMENTS p;
++ gcmkARGUMENTS_START(p, Text);
++
++ for (i = 0; i < numArguments; ++i)
++ {
++ gctPOINTER value = gcmkARGUMENTS_ARG(p, gctPOINTER);
++ gcmkMEMCPY(payload, &value, gcmSIZEOF(gctPOINTER));
++ payload += gcmSIZEOF(gctPOINTER);
++ }
++
++ gcmkARGUMENTS_END(p);
++ }
++
++ gcmkASSERT(payload - buffer <= gcdBINARY_TRACE_MESSAGE_SIZE);
++
++
++ /* Send buffer to ring buffer. */
++ gckOS_WriteToRingBuffer(buffer, (gctUINT32)(payload - buffer));
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,3459 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++#include "gc_hal_kernel_buffer.h"
++
++#ifdef __QNXNTO__
++#include <atomic.h>
++#include "gc_hal_kernel_qnx.h"
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_EVENT
++
++#define gcdEVENT_ALLOCATION_COUNT (4096 / gcmSIZEOF(gcsHAL_INTERFACE))
++#define gcdEVENT_MIN_THRESHOLD 4
++
++/******************************************************************************\
++********************************* Support Code *********************************
++\******************************************************************************/
++
++static gceSTATUS
++gckEVENT_AllocateQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR * Queue
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Do we have free queues? */
++ if (Event->freeList == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Move one free queue from the free list. */
++ * Queue = Event->freeList;
++ Event->freeList = Event->freeList->next;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Queue=0x%x", gcmOPT_POINTER(Queue));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeQueue(
++ IN gckEVENT Event,
++ OUT gcsEVENT_QUEUE_PTR Queue
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Queue != gcvNULL);
++
++ /* Move one free queue from the free list. */
++ Queue->next = Event->freeList;
++ Event->freeList = Queue;
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckEVENT_FreeRecord(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->freeEventMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Push the record on the free list. */
++ Record->next = Event->freeEventList;
++ Event->freeEventList = Record;
++ Event->freeEventCount += 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++gckEVENT_IsEmpty(
++ IN gckEVENT Event,
++ OUT gctBOOL_PTR IsEmpty
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T i;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(IsEmpty != gcvNULL);
++
++ /* Assume the event queue is empty. */
++ *IsEmpty = gcvTRUE;
++
++ /* Walk the event queue. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ /* Check whether this event is in use. */
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* The event is in use, hence the queue is not empty. */
++ *IsEmpty = gcvFALSE;
++ break;
++ }
++ }
++
++ /* Try acquiring the mutex. */
++ status = gckOS_AcquireMutex(Event->os, Event->eventQueueMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ /* Timeout - queue is no longer empty. */
++ *IsEmpty = gcvFALSE;
++ }
++ else
++ {
++ /* Bail out on error. */
++ gcmkONERROR(status);
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*IsEmpty=%d", gcmOPT_VALUE(IsEmpty));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_TryToIdleGPU(
++ IN gckEVENT Event
++)
++{
++ gceSTATUS status;
++ gctBOOL empty = gcvFALSE, idle = gcvFALSE;
++ gctBOOL powerLocked = gcvFALSE;
++ gckHARDWARE hardware;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Grab gckHARDWARE object. */
++ hardware = Event->kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Check whether the event queue is empty. */
++ gcmkONERROR(gckEVENT_IsEmpty(Event, &empty));
++
++ if (empty)
++ {
++ status = gckOS_AcquireMutex(hardware->os, hardware->powerMutex, 0);
++ if (status == gcvSTATUS_TIMEOUT)
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ powerLocked = gcvTRUE;
++
++ /* Query whether the hardware is idle. */
++ gcmkONERROR(gckHARDWARE_QueryIdle(Event->kernel->hardware, &idle));
++
++ gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex));
++ powerLocked = gcvFALSE;
++
++ if (idle)
++ {
++ /* Inform the system of idle GPU. */
++ gcmkONERROR(gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_IDLE));
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (powerLocked)
++ {
++ gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++__RemoveRecordFromProcessDB(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record
++ )
++{
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ while (Record != gcvNULL)
++ {
++ if (Record->info.command == gcvHAL_SIGNAL)
++ {
++ /* TODO: Find a better place to bind signal to hardware.*/
++ gcmkVERIFY_OK(gckOS_SignalSetHardware(Event->os,
++ gcmUINT64_TO_PTR(Record->info.u.Signal.signal),
++ Event->kernel->hardware));
++ }
++
++ if (Record->fromKernel)
++ {
++ /* No need to check db if event is from kernel. */
++ Record = Record->next;
++ continue;
++ }
++
++ switch (Record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_NON_PAGED,
++ gcmUINT64_TO_PTR(Record->info.u.FreeNonPagedMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_CONTIGUOUS,
++ gcmUINT64_TO_PTR(Record->info.u.FreeContiguousMemory.logical)));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_VIDEO_MEMORY_LOCKED,
++ gcmUINT64_TO_PTR(Record->info.u.UnlockVideoMemory.node)));
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_MAP_USER_MEMORY,
++ gcmINT2PTR(Record->info.u.UnmapUserMemory.info)));
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Event->kernel,
++ Record->processID,
++ gcvDB_COMMAND_BUFFER,
++ gcmUINT64_TO_PTR(Record->info.u.FreeVirtualCommandBuffer.logical)));
++ break;
++
++ default:
++ break;
++ }
++
++ Record = Record->next;
++ }
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_ReleaseVideoMemoryHandle(
++ IN gckKERNEL Kernel,
++ IN OUT gcsEVENT_PTR Record,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE nodeObject;
++ gctUINT32 handle;
++
++ switch(Interface->command)
++ {
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ handle = (gctUINT32)Interface->u.UnlockVideoMemory.node;
++
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(
++ Kernel, Record->processID, handle, &nodeObject));
++
++ Record->info.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(nodeObject);
++
++ gckVIDMEM_HANDLE_Dereference(Kernel, Record->processID, handle);
++ break;
++
++ default:
++ break;
++ }
++
++ return gcvSTATUS_OK;
++OnError:
++ return status;
++}
++
++/*******************************************************************************
++**
++** _QueryFlush
++**
++** Check the type of surfaces which will be released by current event and
++** determine the cache needed to flush.
++**
++*/
++static gceSTATUS
++_QueryFlush(
++ IN gckEVENT Event,
++ IN gcsEVENT_PTR Record,
++ OUT gceKERNEL_FLUSH *Flush
++ )
++{
++ gceKERNEL_FLUSH flush = 0;
++ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ while (Record != gcvNULL)
++ {
++ switch (Record->info.command)
++ {
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ switch(Record->info.u.UnlockVideoMemory.type)
++ {
++ case gcvSURF_TILE_STATUS:
++ flush |= gcvFLUSH_TILE_STATUS;
++ break;
++ case gcvSURF_RENDER_TARGET:
++ flush |= gcvFLUSH_COLOR;
++ break;
++ case gcvSURF_DEPTH:
++ flush |= gcvFLUSH_DEPTH;
++ break;
++ case gcvSURF_TEXTURE:
++ flush |= gcvFLUSH_TEXTURE;
++ break;
++ case gcvSURF_TYPE_UNKNOWN:
++ gcmkASSERT(0);
++ break;
++ default:
++ break;
++ }
++ break;
++ case gcvHAL_UNMAP_USER_MEMORY:
++ *Flush = gcvFLUSH_ALL;
++ return gcvSTATUS_OK;
++
++ default:
++ break;
++ }
++
++ Record = Record->next;
++ }
++
++ *Flush = flush;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_SubmitTimerFunction(
++ gctPOINTER Data
++ )
++{
++ gckEVENT event = (gckEVENT)Data;
++#if gcdMULTI_GPU
++ gcmkVERIFY_OK(gckEVENT_Submit(event, gcvTRUE, gcvFALSE, gcvCORE_3D_ALL_MASK));
++#else
++ gcmkVERIFY_OK(gckEVENT_Submit(event, gcvTRUE, gcvFALSE));
++#endif
++}
++
++/******************************************************************************\
++******************************* gckEVENT API Code *******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckEVENT_Construct
++**
++** Construct a new gckEVENT object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gckEVENT * Event
++** Pointer to a variable that receives the gckEVENT object pointer.
++*/
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gckEVENT eventObj = gcvNULL;
++ int i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Event != gcvNULL);
++
++ /* Extract the pointer to the gckOS object. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate the gckEVENT object. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckEVENT), &pointer));
++
++ eventObj = pointer;
++
++ /* Reset the object. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(eventObj, gcmSIZEOF(struct _gckEVENT)));
++
++ /* Initialize the gckEVENT object. */
++ eventObj->object.type = gcvOBJ_EVENT;
++ eventObj->kernel = Kernel;
++ eventObj->os = os;
++
++ /* Create the mutexes. */
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventQueueMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->freeEventMutex));
++ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventListMutex));
++
++ /* Create a bunch of event reccords. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsEVENT), &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = eventObj->freeEventList;
++ eventObj->freeEventList = record;
++ eventObj->freeEventCount += 1;
++ }
++
++ /* Initialize the free list of event queues. */
++ for (i = 0; i < gcdREPO_LIST_COUNT; i += 1)
++ {
++ eventObj->repoList[i].next = eventObj->freeList;
++ eventObj->freeList = &eventObj->repoList[i];
++ }
++
++ /* Construct the atom. */
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->freeAtom));
++ gcmkONERROR(gckOS_AtomSet(os,
++ eventObj->freeAtom,
++ gcmCOUNTOF(eventObj->queues)));
++
++#if gcdSMP
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pending));
++
++#if gcdMULTI_GPU
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pending3D[i]));
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pending3DMask[i]));
++ }
++
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pendingMask));
++#endif
++
++#endif
++
++ gcmkVERIFY_OK(gckOS_CreateTimer(os,
++ _SubmitTimerFunction,
++ (gctPOINTER)eventObj,
++ &eventObj->submitTimer));
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->interruptCount));
++ gcmkONERROR(gckOS_AtomSet(os,eventObj->interruptCount, 0));
++#endif
++
++ /* Return pointer to the gckEVENT object. */
++ *Event = eventObj;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Event=0x%x", *Event);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (eventObj != gcvNULL)
++ {
++ if (eventObj->eventQueueMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventQueueMutex));
++ }
++
++ if (eventObj->freeEventMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->freeEventMutex));
++ }
++
++ if (eventObj->eventListMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventListMutex));
++ }
++
++ while (eventObj->freeEventList != gcvNULL)
++ {
++ record = eventObj->freeEventList;
++ eventObj->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, record));
++ }
++
++ if (eventObj->freeAtom != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->freeAtom));
++ }
++
++#if gcdSMP
++ if (eventObj->pending != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->pending));
++ }
++
++#if gcdMULTI_GPU
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ if (eventObj->pending3D[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->pending3D[i]));
++ }
++
++ if (eventObj->pending3DMask[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->pending3DMask[i]));
++ }
++ }
++#endif
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ if (eventObj->interruptCount)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->interruptCount));
++ }
++#endif
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, eventObj));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Destroy
++**
++** Destroy an gckEVENT object.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_PTR record;
++ gcsEVENT_QUEUE_PTR queue;
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ if (Event->submitTimer != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_StopTimer(Event->os, Event->submitTimer));
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Event->os, Event->submitTimer));
++ }
++
++ /* Delete the queue mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventQueueMutex));
++
++ /* Free all free events. */
++ while (Event->freeEventList != gcvNULL)
++ {
++ record = Event->freeEventList;
++ Event->freeEventList = record->next;
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Delete the free mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->freeEventMutex));
++
++ /* Free all pending queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Free all pending events. */
++ while (queue->head != gcvNULL)
++ {
++ record = queue->head;
++ queue->head = record->next;
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(record) + gcmSIZEOF(queue->source),
++ "Event record 0x%x is still pending for %d.",
++ record, queue->source
++ );
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record));
++ }
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead =
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkVERIFY_OK(gckEVENT_FreeQueue(Event, queue));
++ }
++
++ /* Delete the list mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventListMutex));
++
++ /* Delete the atom. */
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->freeAtom));
++
++#if gcdSMP
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->pending));
++
++#if gcdMULTI_GPU
++ {
++ gctINT i;
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->pending3D[i]));
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->pending3DMask[i]));
++ }
++ }
++#endif
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->interruptCount));
++#endif
++
++ /* Mark the gckEVENT object as unknown. */
++ Event->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckEVENT object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_GetEvent
++**
++** Reserve the next available hardware event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Set to gcvTRUE to force the function to wait if no events are
++** immediately available.
++**
++** gceKERNEL_WHERE Source
++** Source of the event.
++**
++** OUTPUT:
++**
++** gctUINT8 * EventID
++** Reserved event ID.
++*/
++#define gcdINVALID_EVENT_PTR ((gcsEVENT_PTR)gcvMAXUINTPTR_T)
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckEVENT_GetEvent(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ OUT gctUINT8 * EventID,
++ IN gceKERNEL_WHERE Source,
++ IN gceCORE_3D_MASK ChipEnable
++ )
++#else
++gceSTATUS
++gckEVENT_GetEvent(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ OUT gctUINT8 * EventID,
++ IN gceKERNEL_WHERE Source
++ )
++#endif
++{
++ gctINT i, id;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT32 free;
++#if gcdMULTI_GPU
++ gctINT j;
++#endif
++
++ gcmkHEADER_ARG("Event=0x%x Source=%d", Event, Source);
++
++ while (gcvTRUE)
++ {
++ /* Grab the queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Walk through all events. */
++ id = Event->lastID;
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ gctINT nextID = gckMATH_ModuloInt((id + 1),
++ gcmCOUNTOF(Event->queues));
++
++ if (Event->queues[id].head == gcvNULL)
++ {
++ *EventID = (gctUINT8) id;
++
++ Event->lastID = (gctUINT8) nextID;
++
++ /* Save time stamp of event. */
++ Event->queues[id].head = gcdINVALID_EVENT_PTR;
++ Event->queues[id].stamp = ++(Event->stamp);
++ Event->queues[id].source = Source;
++
++#if gcdMULTI_GPU
++ Event->queues[id].chipEnable = ChipEnable;
++
++ if (ChipEnable == gcvCORE_3D_ALL_MASK)
++ {
++ gckOS_AtomSetMask(Event->pendingMask, (1 << id));
++
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ gckOS_AtomSetMask(Event->pending3DMask[j], (1 << id));
++ }
++ }
++ else
++ {
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ if (ChipEnable & (1 << j))
++ {
++ gckOS_AtomSetMask(Event->pending3DMask[j], (1 << id));
++ }
++ }
++ }
++#endif
++
++ gcmkONERROR(gckOS_AtomDecrement(Event->os,
++ Event->freeAtom,
++ &free));
++#if gcdDYNAMIC_SPEED
++ if (free <= gcdDYNAMIC_EVENT_THRESHOLD)
++ {
++ gcmkONERROR(gckOS_BroadcastHurry(
++ Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD - free));
++ }
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os,
++ Event->eventQueueMutex));
++
++ /* Success. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(id),
++ "Using id=%d",
++ id
++ );
++
++ gcmkFOOTER_ARG("*EventID=%u", *EventID);
++ return gcvSTATUS_OK;
++ }
++
++ id = nextID;
++ }
++
++#if gcdDYNAMIC_SPEED
++ /* No free events, speed up the GPU right now! */
++ gcmkONERROR(gckOS_BroadcastHurry(Event->os,
++ Event->kernel->hardware,
++ gcdDYNAMIC_EVENT_THRESHOLD));
++#endif
++
++ /* Release the queue mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Fail if wait is not requested. */
++ if (!Wait)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Delay a while. */
++ gcmkONERROR(gckOS_Delay(Event->os, 1));
++ }
++
++OnError:
++ if (acquired)
++ {
++ /* Release the queue mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AllocateRecord
++**
++** Allocate a record for the new event.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** gcsEVENT_PTR * Record
++** Allocated event record.
++*/
++gceSTATUS
++gckEVENT_AllocateRecord(
++ IN gckEVENT Event,
++ IN gctBOOL AllocateAllowed,
++ OUT gcsEVENT_PTR * Record
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctINT i;
++ gcsEVENT_PTR record;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Event=0x%x AllocateAllowed=%d", Event, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Record != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->freeEventMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Test if we are below the allocation threshold. */
++ if ( (AllocateAllowed && (Event->freeEventCount < gcdEVENT_MIN_THRESHOLD)) ||
++ (Event->freeEventCount == 0) )
++ {
++ /* Allocate a bunch of records. */
++ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1)
++ {
++ /* Allocate an event record. */
++ gcmkONERROR(gckOS_Allocate(Event->os,
++ gcmSIZEOF(gcsEVENT),
++ &pointer));
++
++ record = pointer;
++
++ /* Push it on the free list. */
++ record->next = Event->freeEventList;
++ Event->freeEventList = record;
++ Event->freeEventCount += 1;
++ }
++ }
++
++ *Record = Event->freeEventList;
++ Event->freeEventList = Event->freeEventList->next;
++ Event->freeEventCount -= 1;
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Record=0x%x", gcmOPT_POINTER(Record));
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_AddList
++**
++** Add a new event to the list of events.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_INTERFACE_PTR Interface
++** Pointer to the interface for the event to be added.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gctBOOL AllocateAllowed
++** State for allocation if out of free events.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record = gcvNULL;
++ gcsEVENT_QUEUE_PTR queue;
++ gckVIRTUAL_COMMAND_BUFFER_PTR buffer;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Interface=0x%x",
++ Event, Interface);
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, _GC_OBJ_ZONE,
++ "FromWhere=%d AllocateAllowed=%d",
++ FromWhere, AllocateAllowed);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ /* Verify the event command. */
++ gcmkASSERT
++ ( (Interface->command == gcvHAL_FREE_NON_PAGED_MEMORY)
++ || (Interface->command == gcvHAL_FREE_CONTIGUOUS_MEMORY)
++ || (Interface->command == gcvHAL_WRITE_DATA)
++ || (Interface->command == gcvHAL_UNLOCK_VIDEO_MEMORY)
++ || (Interface->command == gcvHAL_SIGNAL)
++ || (Interface->command == gcvHAL_UNMAP_USER_MEMORY)
++ || (Interface->command == gcvHAL_TIMESTAMP)
++ || (Interface->command == gcvHAL_COMMIT_DONE)
++ || (Interface->command == gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER)
++ || (Interface->command == gcvHAL_SYNC_POINT)
++ || (Interface->command == gcvHAL_DESTROY_MMU)
++ );
++
++ /* Validate the source. */
++ if ((FromWhere != gcvKERNEL_COMMAND) && (FromWhere != gcvKERNEL_PIXEL))
++ {
++ /* Invalid argument. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Allocate a free record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, AllocateAllowed, &record));
++
++ /* Termninate the record. */
++ record->next = gcvNULL;
++
++ /* Record the committer. */
++ record->fromKernel = FromKernel;
++
++ /* Copy the event interface into the record. */
++ gckOS_MemCopy(&record->info, Interface, gcmSIZEOF(record->info));
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&record->processID));
++
++ gcmkONERROR(__RemoveRecordFromProcessDB(Event, record));
++
++ /* Handle is belonged to current process, it must be released now. */
++ if (FromKernel == gcvFALSE)
++ {
++ status = _ReleaseVideoMemoryHandle(Event->kernel, record, Interface);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Ingore error because there are other events in the queue. */
++ status = gcvSTATUS_OK;
++ goto OnError;
++ }
++ }
++
++#ifdef __QNXNTO__
++ record->kernel = Event->kernel;
++#endif
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->eventListMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Do we need to allocate a new queue? */
++ if ((Event->queueTail == gcvNULL) || (Event->queueTail->source < FromWhere))
++ {
++ /* Allocate a new queue. */
++ gcmkONERROR(gckEVENT_AllocateQueue(Event, &queue));
++
++ /* Initialize the queue. */
++ queue->source = FromWhere;
++ queue->head = gcvNULL;
++ queue->next = gcvNULL;
++
++ /* Attach it to the list of allocated queues. */
++ if (Event->queueTail == gcvNULL)
++ {
++ Event->queueHead =
++ Event->queueTail = queue;
++ }
++ else
++ {
++ Event->queueTail->next = queue;
++ Event->queueTail = queue;
++ }
++ }
++ else
++ {
++ queue = Event->queueTail;
++ }
++
++ /* Attach the record to the queue. */
++ if (queue->head == gcvNULL)
++ {
++ queue->head = record;
++ queue->tail = record;
++ }
++ else
++ {
++ queue->tail->next = record;
++ queue->tail = record;
++ }
++
++ /* Unmap user space logical address.
++ * Linux kernel does not support unmap the memory of other process any more since 3.5.
++ * Let's unmap memory of self process before submit the event to gpu.
++ * */
++ switch(Interface->command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical),
++ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical)));
++ break;
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkONERROR(gckOS_UnmapUserLogical(
++ Event->os,
++ gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical),
++ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical)));
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)gcmNAME_TO_PTR(Interface->u.FreeVirtualCommandBuffer.physical);
++ if (buffer->userLogical)
++ {
++ gcmkONERROR(gckOS_DestroyUserVirtualMapping(
++ Event->os,
++ buffer->physical,
++ (gctSIZE_T) Interface->u.FreeVirtualCommandBuffer.bytes,
++ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical)));
++ }
++ break;
++
++ default:
++ break;
++ }
++
++ /* Release the mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (record != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Unlock
++**
++** Schedule an event to unlock virtual memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union that specifies the virtual memory
++** to unlock.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctPOINTER Node,
++ IN gceSURF_TYPE Type
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d Node=0x%x Type=%d",
++ Event, FromWhere, Node, Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Mark the event as an unlock. */
++ iface.command = gcvHAL_UNLOCK_VIDEO_MEMORY;
++ iface.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(Node);
++ iface.u.UnlockVideoMemory.type = Type;
++ iface.u.UnlockVideoMemory.asynchroneous = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeNonPagedMemory
++**
++** Schedule an event to free non-paged memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of non-paged memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of non-paged memory to free.
++**
++** gctPOINTER Logical
++** Logical address of non-paged memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_NON_PAGED_MEMORY;
++ iface.u.FreeNonPagedMemory.bytes = Bytes;
++ iface.u.FreeNonPagedMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeNonPagedMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER;
++ iface.u.FreeVirtualCommandBuffer.bytes = Bytes;
++ iface.u.FreeVirtualCommandBuffer.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_FreeContigiuousMemory
++**
++** Schedule an event to free contiguous memory.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIZE_T Bytes
++** Number of bytes of contiguous memory to free.
++**
++** gctPHYS_ADDR Physical
++** Physical address of contiguous memory to free.
++**
++** gctPOINTER Logical
++** Logical address of contiguous memory to free.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++*/
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gckKERNEL kernel = Event->kernel;
++
++ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x "
++ "FromWhere=%d",
++ Event, Bytes, Physical, Logical, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Create an event. */
++ iface.command = gcvHAL_FREE_CONTIGUOUS_MEMORY;
++ iface.u.FreeContiguousMemory.bytes = Bytes;
++ iface.u.FreeContiguousMemory.physical = gcmPTR_TO_NAME(Physical);
++ iface.u.FreeContiguousMemory.logical = gcmPTR_TO_UINT64(Logical);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Signal
++**
++** Schedule an event to trigger a signal.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x Signal=0x%x FromWhere=%d",
++ Event, Signal, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Mark the event as a signal. */
++ iface.command = gcvHAL_SIGNAL;
++ iface.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++#ifdef __QNXNTO__
++ iface.u.Signal.coid = 0;
++ iface.u.Signal.rcvid = 0;
++#endif
++ iface.u.Signal.auxSignal = 0;
++ iface.u.Signal.process = 0;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_CommitDone
++**
++** Schedule an event to wake up work thread when commit is done by GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gceKERNEL_WHERE FromWhere
++** Place in the pipe where the event needs to be generated.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ iface.command = gcvHAL_COMMIT_DONE;
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckEVENT_DestroyMmu(
++ IN gckEVENT Event,
++ IN gckMMU Mmu,
++ IN gceKERNEL_WHERE FromWhere
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++
++ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ iface.command = gcvHAL_DESTROY_MMU;
++ iface.u.DestroyMmu.mmu = gcmPTR_TO_UINT64(Mmu);
++
++ /* Append it to the queue. */
++ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckEVENT_Submit
++**
++** Submit the current event queue to the GPU.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctBOOL Wait
++** Submit requires one vacant event; if Wait is set to not zero,
++** and there are no vacant events at this time, the function will
++** wait until an event becomes vacant so that submission of the
++** queue is successful.
++**
++** gctBOOL FromPower
++** Determines whether the call originates from inside the power
++** management or not.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++#if gcdMULTI_GPU
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower,
++ IN gceCORE_3D_MASK ChipEnable
++ )
++#else
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT8 id = 0xFF;
++ gcsEVENT_QUEUE_PTR queue;
++ gctBOOL acquired = gcvFALSE;
++ gckCOMMAND command = gcvNULL;
++ gctBOOL commitEntered = gcvFALSE;
++#if !gcdNULL_DRIVER
++ gctUINT32 bytes;
++ gctPOINTER buffer;
++#endif
++
++#if gcdMULTI_GPU
++ gctSIZE_T chipEnableBytes;
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 oldValue;
++#endif
++
++#if gcdSECURITY
++ gctPOINTER reservedBuffer;
++#endif
++
++ gctUINT32 flushBytes;
++ gctUINT32 executeBytes;
++ gckHARDWARE hardware;
++
++ gceKERNEL_FLUSH flush = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Wait=%d", Event, Wait);
++
++ /* Get gckCOMMAND object. */
++ command = Event->kernel->command;
++ hardware = Event->kernel->hardware;
++
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ gckOS_GetTicks(&Event->lastCommitStamp);
++
++ /* Are there event queues? */
++ if (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the command queue. */
++ gcmkONERROR(gckCOMMAND_EnterCommit(command, FromPower));
++ commitEntered = gcvTRUE;
++
++ /* Process all queues. */
++ while (Event->queueHead != gcvNULL)
++ {
++ /* Acquire the list mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventListMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get the current queue. */
++ queue = Event->queueHead;
++
++ /* Allocate an event ID. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckEVENT_GetEvent(Event, Wait, &id, queue->source, ChipEnable));
++#else
++ gcmkONERROR(gckEVENT_GetEvent(Event, Wait, &id, queue->source));
++#endif
++
++ /* Copy event list to event ID queue. */
++ Event->queues[id].head = queue->head;
++
++ /* Remove the top queue from the list. */
++ if (Event->queueHead == Event->queueTail)
++ {
++ Event->queueHead = gcvNULL;
++ Event->queueTail = gcvNULL;
++ }
++ else
++ {
++ Event->queueHead = Event->queueHead->next;
++ }
++
++ /* Free the queue. */
++ gcmkONERROR(gckEVENT_FreeQueue(Event, queue));
++
++ /* Release the list mutex. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ acquired = gcvFALSE;
++
++ /* Determine cache needed to flush. */
++ gcmkVERIFY_OK(_QueryFlush(Event, Event->queues[id].head, &flush));
++
++#if gcdINTERRUPT_STATISTIC
++ gcmkVERIFY_OK(gckOS_AtomIncrement(
++ Event->os,
++ Event->interruptCount,
++ &oldValue
++ ));
++#endif
++
++#if gcdNULL_DRIVER
++ /* Notify immediately on infinite hardware. */
++ gcmkONERROR(gckEVENT_Interrupt(Event, 1 << id));
++
++ gcmkONERROR(gckEVENT_Notify(Event, 0));
++#else
++ /* Get the size of the hardware event. */
++ gcmkONERROR(gckHARDWARE_Event(
++ hardware,
++ gcvNULL,
++ id,
++ Event->queues[id].source,
++ &bytes
++ ));
++
++ /* Get the size of flush command. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ hardware,
++ flush,
++ gcvNULL,
++ &flushBytes
++ ));
++
++ bytes += flushBytes;
++
++#if gcdMULTI_GPU
++ gcmkONERROR(gckHARDWARE_ChipEnable(
++ hardware,
++ gcvNULL,
++ 0,
++ &chipEnableBytes
++ ));
++
++ bytes += chipEnableBytes * 2;
++#endif
++
++ /* Total bytes need to execute. */
++ executeBytes = bytes;
++
++ /* Reserve space in the command queue. */
++ gcmkONERROR(gckCOMMAND_Reserve(command, bytes, &buffer, &bytes));
++#if gcdSECURITY
++ reservedBuffer = buffer;
++#endif
++
++#if gcdMULTI_GPU
++ gcmkONERROR(gckHARDWARE_ChipEnable(
++ hardware,
++ buffer,
++ ChipEnable,
++ &chipEnableBytes
++ ));
++
++ buffer = (gctUINT8_PTR)buffer + chipEnableBytes;
++#endif
++
++ /* Set the flush in the command queue. */
++ gcmkONERROR(gckHARDWARE_Flush(
++ hardware,
++ flush,
++ buffer,
++ &flushBytes
++ ));
++
++ /* Advance to next command. */
++ buffer = (gctUINT8_PTR)buffer + flushBytes;
++
++ /* Set the hardware event in the command queue. */
++ gcmkONERROR(gckHARDWARE_Event(
++ hardware,
++ buffer,
++ id,
++ Event->queues[id].source,
++ &bytes
++ ));
++
++ /* Advance to next command. */
++ buffer = (gctUINT8_PTR)buffer + bytes;
++
++#if gcdMULTI_GPU
++ gcmkONERROR(gckHARDWARE_ChipEnable(
++ hardware,
++ buffer,
++ gcvCORE_3D_ALL_MASK,
++ &chipEnableBytes
++ ));
++#endif
++
++#if gcdSECURITY
++ gckKERNEL_SecurityExecute(
++ Event->kernel,
++ reservedBuffer,
++ executeBytes
++ );
++#else
++ /* Execute the hardware event. */
++ gcmkONERROR(gckCOMMAND_Execute(command, executeBytes));
++#endif
++#endif
++ }
++
++ /* Release the command queue. */
++ gcmkONERROR(gckCOMMAND_ExitCommit(command, FromPower));
++
++#if !gcdNULL_DRIVER
++ gcmkVERIFY_OK(_TryToIdleGPU(Event));
++#endif
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Need to unroll the mutex acquire. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex));
++ }
++
++ if (commitEntered)
++ {
++ /* Release the command queue mutex. */
++ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, FromPower));
++ }
++
++ if (id != 0xFF)
++ {
++ /* Need to unroll the event allocation. */
++ Event->queues[id].head = gcvNULL;
++ }
++
++ if (status == gcvSTATUS_GPU_NOT_RESPONDING)
++ {
++ /* Broadcast GPU stuck. */
++ status = gckOS_Broadcast(Event->os,
++ Event->kernel->hardware,
++ gcvBROADCAST_GPU_STUCK);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Commit
++**
++** Commit an event queue from the user.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsQUEUE_PTR Queue
++** User event queue.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++#if gcdMULTI_GPU
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue,
++ IN gceCORE_3D_MASK ChipEnable
++ )
++#else
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ )
++#endif
++{
++ gceSTATUS status;
++ gcsQUEUE_PTR record = gcvNULL, next;
++ gctUINT32 processID;
++ gctBOOL needCopy = gcvFALSE;
++
++ gcmkHEADER_ARG("Event=0x%x Queue=0x%x", Event, Queue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Get the current process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Query if we need to copy the client data. */
++ gcmkONERROR(gckOS_QueryNeedCopy(Event->os, processID, &needCopy));
++
++ /* Loop while there are records in the queue. */
++ while (Queue != gcvNULL)
++ {
++ gcsQUEUE queue;
++
++ if (needCopy)
++ {
++ /* Point to stack record. */
++ record = &queue;
++
++ /* Copy the data from the client. */
++ gcmkONERROR(gckOS_CopyFromUserData(Event->os,
++ record,
++ Queue,
++ gcmSIZEOF(gcsQUEUE)));
++ }
++ else
++ {
++ gctPOINTER pointer = gcvNULL;
++
++ /* Map record into kernel memory. */
++ gcmkONERROR(gckOS_MapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ &pointer));
++
++ record = pointer;
++ }
++
++ /* Append event record to event queue. */
++ gcmkONERROR(
++ gckEVENT_AddList(Event, &record->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE));
++
++ /* Next record in the queue. */
++ next = gcmUINT64_TO_PTR(record->next);
++
++ if (!needCopy)
++ {
++ /* Unmap record from kernel memory. */
++ gcmkONERROR(
++ gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ record = gcvNULL;
++ }
++
++ Queue = next;
++ }
++
++ /* Submit the event list. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE, ChipEnable));
++#else
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE));
++#endif
++
++ /* Success */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if ((record != gcvNULL) && !needCopy)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_UnmapUserPointer(Event->os,
++ Queue,
++ gcmSIZEOF(gcsQUEUE),
++ (gctPOINTER *) record));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Compose
++**
++** Schedule a composition event and start a composition.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gcsHAL_COMPOSE_PTR Info
++** Pointer to the composition structure.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ )
++{
++ gceSTATUS status;
++ gcsEVENT_PTR headRecord;
++ gcsEVENT_PTR tailRecord;
++ gcsEVENT_PTR tempRecord;
++ gctUINT8 id = 0xFF;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Event=0x%x Info=0x%x", Event, Info);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ /* Allocate an event ID. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, gcvKERNEL_PIXEL, gcvCORE_3D_ALL_MASK));
++#else
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, gcvKERNEL_PIXEL));
++#endif
++
++ /* Get process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ headRecord = tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->process;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->signal;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++
++ /* Allocate another record for user signal #1. */
++ if (gcmUINT64_TO_PTR(Info->userSignal1) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++ tailRecord = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->userSignal1;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Allocate another record for user signal #2. */
++ if (gcmUINT64_TO_PTR(Info->userSignal2) != gcvNULL)
++ {
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord));
++ tailRecord->next = tempRecord;
++
++ /* Initialize the record. */
++ tempRecord->info.command = gcvHAL_SIGNAL;
++ tempRecord->info.u.Signal.process = Info->userProcess;
++#ifdef __QNXNTO__
++ tempRecord->info.u.Signal.coid = Info->coid;
++ tempRecord->info.u.Signal.rcvid = Info->rcvid;
++#endif
++ tempRecord->info.u.Signal.signal = Info->userSignal2;
++ tempRecord->info.u.Signal.auxSignal = 0;
++ tempRecord->next = gcvNULL;
++ tempRecord->processID = processID;
++ }
++
++ /* Set the event list. */
++ Event->queues[id].head = headRecord;
++
++ /* Start composition. */
++ gcmkONERROR(gckHARDWARE_Compose(
++ Event->kernel->hardware, processID,
++ gcmUINT64_TO_PTR(Info->physical), gcmUINT64_TO_PTR(Info->logical), Info->offset, Info->size, id
++ ));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Interrupt
++**
++** Called by the interrupt service routine to store the triggered interrupt
++** mask to be later processed by gckEVENT_Notify.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 Data
++** Mask for the 32 interrupts.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++#if gcdMULTI_GPU
++ IN gctUINT CoreId,
++#endif
++ IN gctUINT32 Data
++ )
++{
++#if gcdMULTI_GPU
++#if defined(WIN32)
++ gctUINT32 i;
++#endif
++#endif
++ gcmkHEADER_ARG("Event=0x%x Data=0x%x", Event, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ if (Data & 0x20000000)
++ {
++ gckENTRYDATA data;
++ gctUINT32 idle;
++ Data &= ~0x20000000;
++
++#if gcdMULTI_GPU
++ if (Event->kernel->core == gcvCORE_MAJOR)
++#endif
++ {
++ /* Get first entry information. */
++ gcmkVERIFY_OK(
++ gckENTRYQUEUE_Dequeue(&Event->kernel->command->queue, &data));
++
++ /* Make sure FE is idle. */
++ do
++ {
++ gcmkVERIFY_OK(gckOS_ReadRegisterEx(
++ Event->os,
++ Event->kernel->core,
++ 0x4,
++ &idle));
++ }
++ while (idle != 0x7FFFFFFF);
++
++ /* Start Command Parser. */
++ gcmkVERIFY_OK(gckHARDWARE_Execute(
++ Event->kernel->hardware,
++ data->physical,
++ data->bytes
++ ));
++ }
++ }
++
++ /* Combine current interrupt status with pending flags. */
++#if gcdSMP
++#if gcdMULTI_GPU
++ if (Event->kernel->core == gcvCORE_MAJOR)
++ {
++ gckOS_AtomSetMask(Event->pending3D[CoreId], Data);
++ }
++ else
++#endif
++ {
++ gckOS_AtomSetMask(Event->pending, Data);
++ }
++#elif defined(__QNXNTO__)
++#if gcdMULTI_GPU
++ if (Event->kernel->core == gcvCORE_MAJOR)
++ {
++ atomic_set(&Event->pending3D[CoreId], Data);
++ }
++ else
++#endif
++ {
++ atomic_set(&Event->pending, Data);
++ }
++#else
++#if gcdMULTI_GPU
++#if defined(WIN32)
++ if (Event->kernel->core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ Event->pending3D[i] |= Data;
++ }
++ }
++ else
++#else
++ if (Event->kernel->core == gcvCORE_MAJOR)
++ {
++ Event->pending3D[CoreId] |= Data;
++ }
++ else
++#endif
++#endif
++ {
++ Event->pending |= Data;
++ }
++#endif
++
++#if gcdINTERRUPT_STATISTIC
++ {
++ gctINT j = 0;
++ gctINT32 oldValue;
++
++ for (j = 0; j < gcmCOUNTOF(Event->queues); j++)
++ {
++ if ((Data & (1 << j)))
++ {
++ gcmkVERIFY_OK(gckOS_AtomDecrement(Event->os,
++ Event->interruptCount,
++ &oldValue));
++ }
++ }
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckEVENT_Notify
++**
++** Process all triggered interrupts.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctINT i;
++ gcsEVENT_QUEUE * queue;
++ gctUINT mask = 0;
++ gctBOOL acquired = gcvFALSE;
++ gctPOINTER info;
++ gctSIGNAL signal;
++ gctUINT pending = 0;
++ gckKERNEL kernel = Event->kernel;
++#if gcdMULTI_GPU
++ gceCORE core = Event->kernel->core;
++ gctUINT32 busy;
++ gctUINT32 oldValue;
++ gctUINT pendingMask;
++#endif
++#if !gcdSMP
++ gctBOOL suspended = gcvFALSE;
++#endif
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctINT eventNumber = 0;
++#endif
++ gctINT32 free;
++#if gcdSECURE_USER
++ gcskSECURE_CACHE_PTR cache;
++#endif
++ gckVIDMEM_NODE nodeObject;
++ gcuVIDMEM_NODE_PTR node;
++
++ gcmkHEADER_ARG("Event=0x%x IDs=0x%x", Event, IDs);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ gcmDEBUG_ONLY(
++ if (IDs != 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++#if gcdMULTI_GPU
++ /* Set busy flag. */
++ gckOS_AtomicExchange(Event->os, &Event->busy, 1, &busy);
++ if (busy)
++ {
++ /* Another thread is already busy - abort. */
++ goto OnSuccess;
++ }
++#endif
++
++ for (;;)
++ {
++ gcsEVENT_PTR record;
++#if gcdMULTI_GPU
++ gctUINT32 pend[gcdMULTI_GPU];
++ gctUINT32 pendMask[gcdMULTI_GPU];
++#endif
++
++ /* Grab the mutex queue. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++#if gcdSMP
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ /* Get current interrupts. */
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ gckOS_AtomGet(Event->os, Event->pending3D[i], (gctINT32_PTR)&pend[i]);
++ gckOS_AtomGet(Event->os, Event->pending3DMask[i], (gctINT32_PTR)&pendMask[i]);
++ }
++
++ gckOS_AtomGet(Event->os, Event->pendingMask, (gctINT32_PTR)&pendingMask);
++ }
++ else
++#endif
++ {
++ gckOS_AtomGet(Event->os, Event->pending, (gctINT32_PTR)&pending);
++ }
++#else
++ /* Suspend interrupts. */
++ gcmkONERROR(gckOS_SuspendInterruptEx(Event->os, Event->kernel->core));
++ suspended = gcvTRUE;
++
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ /* Get current interrupts. */
++ pend[i] = Event->pending3D[i];
++ pendMask[i] = Event->pending3DMask[i];
++ }
++
++ pendingMask = Event->pendingMask;
++ }
++ else
++#endif
++ {
++ pending = Event->pending;
++ }
++
++ /* Resume interrupts. */
++ gcmkONERROR(gckOS_ResumeInterruptEx(Event->os, Event->kernel->core));
++ suspended = gcvFALSE;
++#endif
++
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ gctUINT32 bad_pend = (pend[i] & ~pendMask[i]);
++
++ if (bad_pend != 0)
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(bad_pend) + gcmSIZEOF(i),
++ "Interrupts 0x%x are not unexpected for Core%d.",
++ bad_pend, i
++ );
++
++ gckOS_AtomClearMask(Event->pending3D[i], bad_pend);
++
++ pend[i] &= pendMask[i];
++ }
++ }
++
++ pending = (pend[0] & pend[1] & pendingMask) /* Check combined events on both GPUs */
++ | (pend[0] & ~pendingMask) /* Check individual events on GPU 0 */
++ | (pend[1] & ~pendingMask); /* Check individual events on GPU 1 */
++ }
++#endif
++
++ if (pending == 0)
++ {
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* No more pending interrupts - done. */
++ break;
++ }
++
++ if (pending & 0x80000000)
++ {
++ gctUINT32 AQAxiStatus = 0;
++ gckOS_ReadRegisterEx(Event->os, Event->kernel->hardware->core, 0xC, &AQAxiStatus);
++
++ gcmkPRINT("GPU[%d]: AXI BUS ERROR, AQAxiStatus=0x%x\n", Event->kernel->hardware->core, AQAxiStatus);
++ pending &= 0x7FFFFFFF;
++ }
++
++ if (pending & 0x40000000)
++ {
++ gckHARDWARE_DumpMMUException(Event->kernel->hardware);
++
++ pending &= 0xBFFFFFFF;
++ }
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Pending interrupts 0x%x",
++ pending
++ );
++
++ queue = gcvNULL;
++
++ gcmDEBUG_ONLY(
++ if (IDs == 0)
++ {
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Queue(%d): stamp=%llu source=%d",
++ i,
++ Event->queues[i].stamp,
++ Event->queues[i].source);
++ }
++ }
++ }
++ );
++
++ /* Find the oldest pending interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (pending & (1 << i))
++ )
++ {
++ if ((queue == gcvNULL)
++ || (Event->queues[i].stamp < queue->stamp)
++ )
++ {
++ queue = &Event->queues[i];
++ mask = 1 << i;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ eventNumber = i;
++#endif
++ }
++ }
++ }
++
++ if (queue == gcvNULL)
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(pending),
++ "Interrupts 0x%x are not pending.",
++ pending
++ );
++
++#if gcdSMP
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ /* Mark pending interrupts as handled. */
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ gckOS_AtomClearMask(Event->pending3D[i], pending);
++ gckOS_AtomClearMask(Event->pending3DMask[i], pending);
++ }
++
++ gckOS_AtomClearMask(Event->pendingMask, pending);
++ }
++ else
++#endif
++ {
++ gckOS_AtomClearMask(Event->pending, pending);
++ }
++
++#elif defined(__QNXNTO__)
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ atomic_clr((gctUINT32_PTR)&Event->pending3D[i], pending);
++ atomic_clr((gctUINT32_PTR)&Event->pending3DMask[i], pending);
++ }
++
++ atomic_clr((gctUINT32_PTR)&Event->pendingMask, pending);
++ }
++ else
++#endif
++ {
++ atomic_clr((gctUINT32_PTR)&Event->pending, pending);
++ }
++#else
++ /* Suspend interrupts. */
++ gcmkONERROR(gckOS_SuspendInterruptEx(Event->os, Event->kernel->core));
++ suspended = gcvTRUE;
++
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ /* Mark pending interrupts as handled. */
++ Event->pending3D[i] &= ~pending;
++ Event->pending3DMask[i] &= ~pending;
++ }
++ }
++ else
++#endif
++ {
++ Event->pending &= ~pending;
++ }
++
++ /* Resume interrupts. */
++ gcmkONERROR(gckOS_ResumeInterruptEx(Event->os, Event->kernel->core));
++ suspended = gcvFALSE;
++#endif
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++ break;
++ }
++
++ /* Check whether there is a missed interrupt. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if ((Event->queues[i].head != gcvNULL)
++ && (Event->queues[i].stamp < queue->stamp)
++ && (Event->queues[i].source <= queue->source)
++#if gcdMULTI_GPU
++ && (Event->queues[i].chipEnable == queue->chipEnable)
++#endif
++ )
++ {
++ gcmkTRACE_N(
++ gcvLEVEL_ERROR,
++ gcmSIZEOF(i) + gcmSIZEOF(Event->queues[i].stamp),
++ "Event %d lost (stamp %llu)",
++ i, Event->queues[i].stamp
++ );
++
++ /* Use this event instead. */
++ queue = &Event->queues[i];
++ mask = 0;
++ }
++ }
++
++ if (mask != 0)
++ {
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(eventNumber),
++ "Processing interrupt %d",
++ eventNumber
++ );
++#endif
++ }
++
++#if gcdSMP
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ /* Mark pending interrupt as handled. */
++ gckOS_AtomClearMask(Event->pending3D[i], mask);
++ gckOS_AtomClearMask(Event->pending3DMask[i], mask);
++ }
++
++ gckOS_AtomClearMask(Event->pendingMask, mask);
++ }
++ else
++#endif
++ {
++ gckOS_AtomClearMask(Event->pending, mask);
++ }
++
++#elif defined(__QNXNTO__)
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ atomic_clr(&Event->pending3D[i], mask);
++ atomic_clr(&Event->pending3DMask[i], mask);
++ }
++
++ atomic_clr(&Event->pendingMask, mask);
++ }
++ else
++#endif
++ {
++ atomic_clr(&Event->pending, mask);
++ }
++#else
++ /* Suspend interrupts. */
++ gcmkONERROR(gckOS_SuspendInterruptEx(Event->os, Event->kernel->core));
++ suspended = gcvTRUE;
++
++#if gcdMULTI_GPU
++ if (core == gcvCORE_MAJOR)
++ {
++ for (i = 0; i < gcdMULTI_GPU; i++)
++ {
++ /* Mark pending interrupt as handled. */
++ Event->pending3D[i] &= ~mask;
++ Event->pending3DMask[i] &= ~mask;
++ }
++
++ Event->pendingMask &= ~mask;
++ }
++ else
++#endif
++ {
++ Event->pending &= ~mask;
++ }
++
++ /* Resume interrupts. */
++ gcmkONERROR(gckOS_ResumeInterruptEx(Event->os, Event->kernel->core));
++ suspended = gcvFALSE;
++#endif
++
++ /* Grab the event head. */
++ record = queue->head;
++
++ /* Now quickly clear its event list. */
++ queue->head = gcvNULL;
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Increase the number of free events. */
++ gcmkONERROR(gckOS_AtomIncrement(Event->os, Event->freeAtom, &free));
++
++ /* Walk all events for this interrupt. */
++ while (record != gcvNULL)
++ {
++ gcsEVENT_PTR recordNext;
++#ifndef __QNXNTO__
++ gctPOINTER logical;
++#endif
++#if gcdSECURE_USER
++ gctSIZE_T bytes;
++#endif
++
++ /* Grab next record. */
++ recordNext = record->next;
++
++#ifdef __QNXNTO__
++ /* Assign record->processID as the pid for this galcore thread.
++ * Used in OS calls like gckOS_UnlockMemory() which do not take a pid.
++ */
++ drv_thread_specific_key_assign(record->processID, 0, Event->kernel->core);
++#endif
++
++#if gcdSECURE_USER
++ /* Get the cache that belongs to this process. */
++ gcmkONERROR(gckKERNEL_GetProcessDBCache(Event->kernel,
++ record->processID,
++ &cache));
++#endif
++
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_INFO, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Processing event type: %d",
++ record->info.command
++ );
++
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_NON_PAGED_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical));
++
++ /* Free non-paged memory. */
++ status = gckOS_FreeNonPagedMemory(
++ Event->os,
++ (gctSIZE_T) record->info.u.FreeNonPagedMemory.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeNonPagedMemory.logical));
++
++ if (gcmIS_SUCCESS(status))
++ {
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->record.u.FreeNonPagedMemory.logical),
++ (gctSIZE_T) record->record.u.FreeNonPagedMemory.bytes));
++#endif
++ }
++ gcmRELEASE_NAME(record->info.u.FreeNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_FREE_CONTIGUOUS_MEMORY: 0x%x",
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical));
++
++ /* Unmap the user memory. */
++ status = gckOS_FreeContiguous(
++ Event->os,
++ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeContiguousMemory.logical),
++ (gctSIZE_T) record->info.u.FreeContiguousMemory.bytes);
++
++ if (gcmIS_SUCCESS(status))
++ {
++#if gcdSECURE_USER
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(event->event.u.FreeContiguousMemory.logical),
++ (gctSIZE_T) event->event.u.FreeContiguousMemory.bytes));
++#endif
++ }
++ gcmRELEASE_NAME(record->info.u.FreeContiguousMemory.physical);
++ break;
++
++ case gcvHAL_WRITE_DATA:
++#ifndef __QNXNTO__
++ /* Convert physical into logical address. */
++ gcmkERR_BREAK(
++ gckOS_MapPhysical(Event->os,
++ record->info.u.WriteData.address,
++ gcmSIZEOF(gctUINT32),
++ &logical));
++
++ /* Write data. */
++ gcmkERR_BREAK(
++ gckOS_WriteMemory(Event->os,
++ logical,
++ record->info.u.WriteData.data));
++
++ /* Unmap the physical memory. */
++ gcmkERR_BREAK(
++ gckOS_UnmapPhysical(Event->os,
++ logical,
++ gcmSIZEOF(gctUINT32)));
++#else
++ /* Write data. */
++ gcmkERR_BREAK(
++ gckOS_WriteMemory(Event->os,
++ (gctPOINTER)
++ record->info.u.WriteData.address,
++ record->info.u.WriteData.data));
++#endif
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNLOCK_VIDEO_MEMORY: 0x%x",
++ record->info.u.UnlockVideoMemory.node);
++
++ nodeObject = gcmUINT64_TO_PTR(record->info.u.UnlockVideoMemory.node);
++
++ node = nodeObject->node;
++
++ /* Save node information before it disappears. */
++#if gcdSECURE_USER
++ node = event->event.u.UnlockVideoMemory.node;
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ logical = gcvNULL;
++ bytes = 0;
++ }
++ else
++ {
++ logical = node->Virtual.logical;
++ bytes = node->Virtual.bytes;
++ }
++#endif
++
++ /* Unlock. */
++ status = gckVIDMEM_Unlock(
++ Event->kernel,
++ nodeObject,
++ record->info.u.UnlockVideoMemory.type,
++ gcvNULL);
++
++#if gcdSECURE_USER
++ if (gcmIS_SUCCESS(status) && (logical != gcvNULL))
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ logical,
++ bytes));
++ }
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Unlock(
++ Event->kernel,
++ nodeObject,
++ record->processID
++ ));
++#endif
++
++ status = gckVIDMEM_NODE_Dereference(Event->kernel, nodeObject);
++ break;
++
++ case gcvHAL_SIGNAL:
++ signal = gcmUINT64_TO_PTR(record->info.u.Signal.signal);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_SIGNAL: 0x%x",
++ signal);
++
++#ifdef __QNXNTO__
++ if ((record->info.u.Signal.coid == 0)
++ && (record->info.u.Signal.rcvid == 0)
++ )
++ {
++ /* Kernel signal. */
++ gcmkERR_BREAK(
++ gckOS_Signal(Event->os,
++ signal,
++ gcvTRUE));
++ }
++ else
++ {
++ /* User signal. */
++ gcmkERR_BREAK(
++ gckOS_UserSignal(Event->os,
++ signal,
++ record->info.u.Signal.rcvid,
++ record->info.u.Signal.coid));
++ }
++#else
++ /* Set signal. */
++ if (gcmUINT64_TO_PTR(record->info.u.Signal.process) == gcvNULL)
++ {
++ /* Kernel signal. */
++ gcmkERR_BREAK(
++ gckOS_Signal(Event->os,
++ signal,
++ gcvTRUE));
++ }
++ else
++ {
++ /* User signal. */
++ gcmkERR_BREAK(
++ gckOS_UserSignal(Event->os,
++ signal,
++ gcmUINT64_TO_PTR(record->info.u.Signal.process)));
++ }
++
++ gcmkASSERT(record->info.u.Signal.auxSignal == 0);
++#endif
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ info = gcmNAME_TO_PTR(record->info.u.UnmapUserMemory.info);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_UNMAP_USER_MEMORY: 0x%x",
++ info);
++
++ /* Unmap the user memory. */
++ status = gckOS_UnmapUserMemory(
++ Event->os,
++ Event->kernel->core,
++ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory),
++ (gctSIZE_T) record->info.u.UnmapUserMemory.size,
++ info,
++ record->info.u.UnmapUserMemory.address);
++
++#if gcdSECURE_USER
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(gckKERNEL_FlushTranslationCache(
++ Event->kernel,
++ cache,
++ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory),
++ (gctSIZE_T) record->info.u.UnmapUserMemory.size));
++ }
++#endif
++ gcmRELEASE_NAME(record->info.u.UnmapUserMemory.info);
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "gcvHAL_TIMESTAMP: %d %d",
++ record->info.u.TimeStamp.timer,
++ record->info.u.TimeStamp.request);
++
++ /* Process the timestamp. */
++ switch (record->info.u.TimeStamp.request)
++ {
++ case 0:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ stopTime);
++ break;
++
++ case 1:
++ status = gckOS_GetTime(&Event->kernel->timers[
++ record->info.u.TimeStamp.timer].
++ startTime);
++ break;
++
++ default:
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.u.TimeStamp.request),
++ "Invalid timestamp request: %d",
++ record->info.u.TimeStamp.request
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkVERIFY_OK(
++ gckKERNEL_DestroyVirtualCommandBuffer(Event->kernel,
++ (gctSIZE_T) record->info.u.FreeVirtualCommandBuffer.bytes,
++ gcmNAME_TO_PTR(record->info.u.FreeVirtualCommandBuffer.physical),
++ gcmUINT64_TO_PTR(record->info.u.FreeVirtualCommandBuffer.logical)
++ ));
++ gcmRELEASE_NAME(record->info.u.FreeVirtualCommandBuffer.physical);
++ break;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ case gcvHAL_SYNC_POINT:
++ {
++ gctSYNC_POINT syncPoint;
++
++ syncPoint = gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint);
++ status = gckOS_SignalSyncPoint(Event->os, syncPoint);
++ }
++ break;
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++ case gcvHAL_DESTROY_MMU:
++ status = gckMMU_Destroy(gcmUINT64_TO_PTR(record->info.u.DestroyMmu.mmu));
++ break;
++#endif
++
++ case gcvHAL_COMMIT_DONE:
++ break;
++
++ default:
++ /* Invalid argument. */
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_ERROR, gcvZONE_EVENT,
++ gcmSIZEOF(record->info.command),
++ "Unknown event type: %d",
++ record->info.command
++ );
++
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Make sure there are no errors generated. */
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE_N(
++ gcvLEVEL_WARNING, gcvZONE_EVENT,
++ gcmSIZEOF(status),
++ "Event produced status: %d(%s)",
++ status, gckOS_DebugStatus2Name(status));
++ }
++
++ /* Free the event. */
++ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record));
++
++ /* Advance to next record. */
++ record = recordNext;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT,
++ "Handled interrupt 0x%x", mask);
++ }
++
++#if gcdMULTI_GPU
++ /* Clear busy flag. */
++ gckOS_AtomicExchange(Event->os, &Event->busy, 0, &oldValue);
++#endif
++
++ if (IDs == 0)
++ {
++ gcmkONERROR(_TryToIdleGPU(Event));
++ }
++
++#if gcdMULTI_GPU
++OnSuccess:
++#endif
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++#if !gcdSMP
++ if (suspended)
++ {
++ /* Resume interrupts. */
++ gcmkVERIFY_OK(gckOS_ResumeInterruptEx(Event->os, Event->kernel->core));
++ }
++#endif
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_FreeProcess
++**
++** Free all events owned by a particular process ID.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID of the process to be freed up.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ )
++{
++ gctSIZE_T i;
++ gctBOOL acquired = gcvFALSE;
++ gcsEVENT_PTR record, next;
++ gceSTATUS status;
++ gcsEVENT_PTR deleteHead, deleteTail;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%d", Event, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Walk through all queues. */
++ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i)
++ {
++ if (Event->queues[i].head != gcvNULL)
++ {
++ /* Grab the event queue mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Event->os,
++ Event->eventQueueMutex,
++ gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Grab the mutex head. */
++ record = Event->queues[i].head;
++ Event->queues[i].head = gcvNULL;
++ Event->queues[i].tail = gcvNULL;
++ deleteHead = gcvNULL;
++ deleteTail = gcvNULL;
++
++ while (record != gcvNULL)
++ {
++ next = record->next;
++ if (record->processID == ProcessID)
++ {
++ if (deleteHead == gcvNULL)
++ {
++ deleteHead = record;
++ }
++ else
++ {
++ deleteTail->next = record;
++ }
++
++ deleteTail = record;
++ }
++ else
++ {
++ if (Event->queues[i].head == gcvNULL)
++ {
++ Event->queues[i].head = record;
++ }
++ else
++ {
++ Event->queues[i].tail->next = record;
++ }
++
++ Event->queues[i].tail = record;
++ }
++
++ record->next = gcvNULL;
++ record = next;
++ }
++
++ /* Release the mutex queue. */
++ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ acquired = gcvFALSE;
++
++ /* Loop through the entire list of events. */
++ for (record = deleteHead; record != gcvNULL; record = next)
++ {
++ /* Get the next event record. */
++ next = record->next;
++
++ /* Free the event record. */
++ gcmkONERROR(gckEVENT_FreeRecord(Event, record));
++ }
++ }
++ }
++
++ gcmkONERROR(_TryToIdleGPU(Event));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Release the event queue mutex. */
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++** gckEVENT_Stop
++**
++** Stop the hardware using the End event mechanism.
++**
++** INPUT:
++**
++** gckEVENT Event
++** Pointer to an gckEVENT object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIGNAL Signal
++** Pointer to the signal to trigger.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctUINT32 * waitSize
++ )
++{
++ gceSTATUS status;
++ /* gctSIZE_T waitSize;*/
++ gcsEVENT_PTR record;
++ gctUINT8 id = 0xFF;
++
++ gcmkHEADER_ARG("Event=0x%x ProcessID=%u Handle=0x%x Logical=0x%x "
++ "Signal=0x%x",
++ Event, ProcessID, Handle, Logical, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT);
++
++ /* Submit the current event queue. */
++#if gcdMULTI_GPU
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE, gcvCORE_3D_ALL_MASK));
++#else
++ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE));
++#endif
++#if gcdMULTI_GPU
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, gcvKERNEL_PIXEL, gcvCORE_3D_ALL_MASK));
++#else
++ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, gcvKERNEL_PIXEL));
++#endif
++
++ /* Allocate a record. */
++ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &record));
++
++ /* Initialize the record. */
++ record->next = gcvNULL;
++ record->processID = ProcessID;
++ record->info.command = gcvHAL_SIGNAL;
++ record->info.u.Signal.signal = gcmPTR_TO_UINT64(Signal);
++#ifdef __QNXNTO__
++ record->info.u.Signal.coid = 0;
++ record->info.u.Signal.rcvid = 0;
++#endif
++ record->info.u.Signal.auxSignal = 0;
++ record->info.u.Signal.process = 0;
++
++ /* Append the record. */
++ Event->queues[id].head = record;
++
++ /* Replace last WAIT with END. */
++ gcmkONERROR(gckHARDWARE_End(
++ Event->kernel->hardware, Logical, waitSize
++ ));
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Flush the cache for the END. */
++ gcmkONERROR(gckOS_CacheClean(
++ Event->os,
++ ProcessID,
++ gcvNULL,
++ (gctUINT32)Handle,
++ Logical,
++ *waitSize
++ ));
++#endif
++
++ /* Wait for the signal. */
++ gcmkONERROR(gckOS_WaitSignal(Event->os, Signal, gcvINFINITE));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_PrintRecord(
++ gcsEVENT_PTR record
++ )
++{
++ switch (record->info.command)
++ {
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_NON_PAGED_MEMORY");
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ gcmkPRINT(" gcvHAL_FREE_CONTIGUOUS_MEMORY");
++ break;
++
++ case gcvHAL_WRITE_DATA:
++ gcmkPRINT(" gcvHAL_WRITE_DATA");
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkPRINT(" gcvHAL_UNLOCK_VIDEO_MEMORY");
++ break;
++
++ case gcvHAL_SIGNAL:
++ gcmkPRINT(" gcvHAL_SIGNAL process=%d signal=0x%x",
++ record->info.u.Signal.process,
++ record->info.u.Signal.signal);
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ gcmkPRINT(" gcvHAL_UNMAP_USER_MEMORY");
++ break;
++
++ case gcvHAL_TIMESTAMP:
++ gcmkPRINT(" gcvHAL_TIMESTAMP");
++ break;
++
++ case gcvHAL_COMMIT_DONE:
++ gcmkPRINT(" gcvHAL_COMMIT_DONE");
++ break;
++
++ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER:
++ gcmkPRINT(" gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER logical=0x%08x",
++ record->info.u.FreeVirtualCommandBuffer.logical);
++ break;
++
++ case gcvHAL_SYNC_POINT:
++ gcmkPRINT(" gcvHAL_SYNC_POINT syncPoint=0x%08x",
++ gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint));
++
++ break;
++
++ case gcvHAL_DESTROY_MMU:
++ gcmkPRINT(" gcvHAL_DESTORY_MMU mmu=0x%08x",
++ gcmUINT64_TO_PTR(record->info.u.DestroyMmu.mmu));
++
++ break;
++ default:
++ gcmkPRINT(" Illegal Event %d", record->info.command);
++ break;
++ }
++}
++
++/*******************************************************************************
++** gckEVENT_Dump
++**
++** Dump record in event queue when stuck happens.
++** No protection for the event queue.
++**/
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ )
++{
++ gcsEVENT_QUEUE_PTR queueHead = Event->queueHead;
++ gcsEVENT_QUEUE_PTR queue;
++ gcsEVENT_PTR record = gcvNULL;
++ gctINT i;
++#if gcdINTERRUPT_STATISTIC
++ gctINT32 pendingInterrupt;
++ gctUINT32 intrAcknowledge;
++#endif
++
++ gcmkHEADER_ARG("Event=0x%x", Event);
++
++ gcmkPRINT("**************************\n");
++ gcmkPRINT("*** EVENT STATE DUMP ***\n");
++ gcmkPRINT("**************************\n");
++
++ gcmkPRINT(" Unsumbitted Event:");
++ while(queueHead)
++ {
++ queue = queueHead;
++ record = queueHead->head;
++
++ gcmkPRINT(" [%x]:", queue);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++
++ if (queueHead == Event->queueTail)
++ {
++ queueHead = gcvNULL;
++ }
++ else
++ {
++ queueHead = queueHead->next;
++ }
++ }
++
++ gcmkPRINT(" Untriggered Event:");
++ for (i = 0; i < gcmCOUNTOF(Event->queues); i++)
++ {
++ queue = &Event->queues[i];
++ record = queue->head;
++
++ gcmkPRINT(" [%d]:", i);
++ while(record)
++ {
++ _PrintRecord(record);
++ record = record->next;
++ }
++ }
++
++#if gcdINTERRUPT_STATISTIC
++ gckOS_AtomGet(Event->os, Event->interruptCount, &pendingInterrupt);
++ gcmkPRINT(" Number of Pending Interrupt: %d", pendingInterrupt);
++
++ if (Event->kernel->recovery == 0)
++ {
++ gckOS_ReadRegisterEx(
++ Event->os,
++ Event->kernel->core,
++ 0x10,
++ &intrAcknowledge
++ );
++
++ gcmkPRINT(" INTR_ACKNOWLEDGE=0x%x", intrAcknowledge);
++ }
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,1489 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_h_
++#define __gc_hal_kernel_h_
++
++#include "gc_hal.h"
++#include "gc_hal_kernel_hardware.h"
++#include "gc_hal_driver.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_kernel_vg.h"
++#endif
++
++#if gcdSECURITY
++#include "gc_hal_security_interface.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++/*******************************************************************************
++***** New MMU Defination *******************************************************/
++#define gcdMMU_MTLB_SHIFT 22
++#define gcdMMU_STLB_4K_SHIFT 12
++#define gcdMMU_STLB_64K_SHIFT 16
++
++#define gcdMMU_MTLB_BITS (32 - gcdMMU_MTLB_SHIFT)
++#define gcdMMU_PAGE_4K_BITS gcdMMU_STLB_4K_SHIFT
++#define gcdMMU_STLB_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_4K_BITS)
++#define gcdMMU_PAGE_64K_BITS gcdMMU_STLB_64K_SHIFT
++#define gcdMMU_STLB_64K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_64K_BITS)
++
++#define gcdMMU_MTLB_ENTRY_NUM (1 << gcdMMU_MTLB_BITS)
++#define gcdMMU_MTLB_SIZE (gcdMMU_MTLB_ENTRY_NUM << 2)
++#define gcdMMU_STLB_4K_ENTRY_NUM (1 << gcdMMU_STLB_4K_BITS)
++#define gcdMMU_STLB_4K_SIZE (gcdMMU_STLB_4K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_4K_SIZE (1 << gcdMMU_STLB_4K_SHIFT)
++#define gcdMMU_STLB_64K_ENTRY_NUM (1 << gcdMMU_STLB_64K_BITS)
++#define gcdMMU_STLB_64K_SIZE (gcdMMU_STLB_64K_ENTRY_NUM << 2)
++#define gcdMMU_PAGE_64K_SIZE (1 << gcdMMU_STLB_64K_SHIFT)
++
++#define gcdMMU_MTLB_MASK (~((1U << gcdMMU_MTLB_SHIFT)-1))
++#define gcdMMU_STLB_4K_MASK ((~0U << gcdMMU_STLB_4K_SHIFT) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_4K_MASK (gcdMMU_PAGE_4K_SIZE - 1)
++#define gcdMMU_STLB_64K_MASK ((~((1U << gcdMMU_STLB_64K_SHIFT)-1)) ^ gcdMMU_MTLB_MASK)
++#define gcdMMU_PAGE_64K_MASK (gcdMMU_PAGE_64K_SIZE - 1)
++
++/* Page offset definitions. */
++#define gcdMMU_OFFSET_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_4K_BITS)
++#define gcdMMU_OFFSET_4K_MASK ((1U << gcdMMU_OFFSET_4K_BITS) - 1)
++#define gcdMMU_OFFSET_16K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_16K_BITS)
++#define gcdMMU_OFFSET_16K_MASK ((1U << gcdMMU_OFFSET_16K_BITS) - 1)
++
++#define gcdMMU_MTLB_PRESENT 0x00000001
++#define gcdMMU_MTLB_EXCEPTION 0x00000002
++#define gcdMMU_MTLB_4K_PAGE 0x00000000
++
++#define gcdMMU_STLB_PRESENT 0x00000001
++#define gcdMMU_STLB_EXCEPTION 0x00000002
++#define gcdMMU_STLB_4K_PAGE 0x00000000
++
++/*******************************************************************************
++***** Stuck Dump Level ********************************************************/
++
++#define gcdSTUCK_DUMP_MINIMAL 1
++#define gcdSTUCK_DUMP_MIDDLE 2
++#define gcdSTUCK_DUMP_MAXIMAL 3
++
++/*******************************************************************************
++***** Process Secure Cache ****************************************************/
++
++#define gcdSECURE_CACHE_LRU 1
++#define gcdSECURE_CACHE_LINEAR 2
++#define gcdSECURE_CACHE_HASH 3
++#define gcdSECURE_CACHE_TABLE 4
++
++#define gcvPAGE_TABLE_DIRTY_BIT_OTHER (1 << 0)
++#define gcvPAGE_TABLE_DIRTY_BIT_FE (1 << 1)
++
++typedef struct _gcskLOGICAL_CACHE * gcskLOGICAL_CACHE_PTR;
++typedef struct _gcskLOGICAL_CACHE gcskLOGICAL_CACHE;
++struct _gcskLOGICAL_CACHE
++{
++ /* Logical address. */
++ gctPOINTER logical;
++
++ /* DMAable address. */
++ gctUINT32 dma;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Pointer to the previous and next hash tables. */
++ gcskLOGICAL_CACHE_PTR nextHash;
++ gcskLOGICAL_CACHE_PTR prevHash;
++#endif
++
++#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE
++ /* Pointer to the previous and next slot. */
++ gcskLOGICAL_CACHE_PTR next;
++ gcskLOGICAL_CACHE_PTR prev;
++#endif
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR
++ /* Time stamp. */
++ gctUINT64 stamp;
++#endif
++};
++
++typedef struct _gcskSECURE_CACHE * gcskSECURE_CACHE_PTR;
++typedef struct _gcskSECURE_CACHE
++{
++ /* Cache memory. */
++ gcskLOGICAL_CACHE cache[1 + gcdSECURE_CACHE_SLOTS];
++
++ /* Last known index for LINEAR mode. */
++ gcskLOGICAL_CACHE_PTR cacheIndex;
++
++ /* Current free slot for LINEAR mode. */
++ gctUINT32 cacheFree;
++
++ /* Time stamp for LINEAR mode. */
++ gctUINT64 cacheStamp;
++
++#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH
++ /* Hash table for HASH mode. */
++ gcskLOGICAL_CACHE hash[256];
++#endif
++}
++gcskSECURE_CACHE;
++
++/*******************************************************************************
++***** Process Database Management *********************************************/
++
++typedef enum _gceDATABASE_TYPE
++{
++ gcvDB_VIDEO_MEMORY = 1, /* Video memory created. */
++ gcvDB_COMMAND_BUFFER, /* Command Buffer. */
++ gcvDB_NON_PAGED, /* Non paged memory. */
++ gcvDB_CONTIGUOUS, /* Contiguous memory. */
++ gcvDB_SIGNAL, /* Signal. */
++ gcvDB_VIDEO_MEMORY_LOCKED, /* Video memory locked. */
++ gcvDB_CONTEXT, /* Context */
++ gcvDB_IDLE, /* GPU idle. */
++ gcvDB_MAP_MEMORY, /* Map memory */
++ gcvDB_MAP_USER_MEMORY, /* Map user memory */
++ gcvDB_SYNC_POINT, /* Sync point. */
++ gcvDB_SHBUF, /* Shared buffer. */
++}
++gceDATABASE_TYPE;
++
++#define gcdDATABASE_TYPE_MASK 0x000000FF
++#define gcdDB_VIDEO_MEMORY_TYPE_MASK 0x0000FF00
++#define gcdDB_VIDEO_MEMORY_TYPE_SHIFT 8
++
++#define gcdDB_VIDEO_MEMORY_POOL_MASK 0x00FF0000
++#define gcdDB_VIDEO_MEMORY_POOL_SHIFT 16
++
++typedef struct _gcsDATABASE_RECORD * gcsDATABASE_RECORD_PTR;
++typedef struct _gcsDATABASE_RECORD
++{
++ /* Pointer to kernel. */
++ gckKERNEL kernel;
++
++ /* Pointer to next database record. */
++ gcsDATABASE_RECORD_PTR next;
++
++ /* Type of record. */
++ gceDATABASE_TYPE type;
++
++ /* Data for record. */
++ gctPOINTER data;
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++}
++gcsDATABASE_RECORD;
++
++typedef struct _gcsDATABASE * gcsDATABASE_PTR;
++typedef struct _gcsDATABASE
++{
++ /* Pointer to next entry is hash list. */
++ gcsDATABASE_PTR next;
++ gctSIZE_T slot;
++
++ /* Process ID. */
++ gctUINT32 processID;
++
++ /* Sizes to query. */
++ gcsDATABASE_COUNTERS vidMem;
++ gcsDATABASE_COUNTERS nonPaged;
++ gcsDATABASE_COUNTERS contiguous;
++ gcsDATABASE_COUNTERS mapUserMemory;
++ gcsDATABASE_COUNTERS mapMemory;
++ gcsDATABASE_COUNTERS virtualCommandBuffer;
++
++ gcsDATABASE_COUNTERS vidMemType[gcvSURF_NUM_TYPES];
++ /* Counter for each video memory pool. */
++ gcsDATABASE_COUNTERS vidMemPool[gcvPOOL_NUMBER_OF_POOLS];
++ gctPOINTER counterMutex;
++
++ /* Idle time management. */
++ gctUINT64 lastIdle;
++ gctUINT64 idle;
++
++ /* Pointer to database. */
++ gcsDATABASE_RECORD_PTR list[48];
++
++#if gcdSECURE_USER
++ /* Secure cache. */
++ gcskSECURE_CACHE cache;
++#endif
++
++ gctPOINTER handleDatabase;
++ gctPOINTER handleDatabaseMutex;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++}
++gcsDATABASE;
++
++typedef struct _gcsRECORDER * gckRECORDER;
++
++typedef struct _gcsFDPRIVATE * gcsFDPRIVATE_PTR;
++typedef struct _gcsFDPRIVATE
++{
++ gctINT (* release) (gcsFDPRIVATE_PTR Private);
++}
++gcsFDPRIVATE;
++
++/* Create a process database that will contain all its allocations. */
++gceSTATUS
++gckKERNEL_CreateProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Add a record to the process database. */
++gceSTATUS
++gckKERNEL_AddProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Size
++ );
++
++/* Remove a record to the process database. */
++gceSTATUS
++gckKERNEL_RemoveProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer
++ );
++
++/* Destroy the process database. */
++gceSTATUS
++gckKERNEL_DestroyProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID
++ );
++
++/* Find a record to the process database. */
++gceSTATUS
++gckKERNEL_FindProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 ThreadID,
++ IN gceDATABASE_TYPE Type,
++ IN gctPOINTER Pointer,
++ OUT gcsDATABASE_RECORD_PTR Record
++ );
++
++/* Query the process database. */
++gceSTATUS
++gckKERNEL_QueryProcessDB(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ IN gceDATABASE_TYPE Type,
++ OUT gcuDATABASE_INFO * Info
++ );
++
++/* Dump the process database. */
++gceSTATUS
++gckKERNEL_DumpProcessDB(
++ IN gckKERNEL Kernel
++ );
++
++/* Dump the video memory usage for process specified. */
++gceSTATUS
++gckKERNEL_DumpVidMemUsage(
++ IN gckKERNEL Kernel,
++ IN gctINT32 ProcessID
++ );
++
++gceSTATUS
++gckKERNEL_FindDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL LastProcessID,
++ OUT gcsDATABASE_PTR * Database
++ );
++
++gceSTATUS
++gckKERNEL_FindHandleDatbase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gctPOINTER * HandleDatabase,
++ OUT gctPOINTER * HandleDatabaseMutex
++ );
++
++gceSTATUS
++gckKERNEL_GetProcessMMU(
++ IN gckKERNEL Kernel,
++ OUT gckMMU * Mmu
++ );
++
++gceSTATUS
++gckKERNEL_SetRecovery(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Recovery,
++ IN gctUINT32 StuckDump
++ );
++
++gceSTATUS
++gckMMU_FlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 Physical
++ );
++
++gceSTATUS
++gckMMU_GetPageEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctUINT32_PTR *PageTable
++ );
++
++gceSTATUS
++gckMMU_FreePagesEx(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctSIZE_T PageCount
++ );
++
++gceSTATUS
++gckKERNEL_CreateIntegerDatabase(
++ IN gckKERNEL Kernel,
++ OUT gctPOINTER * Database
++ );
++
++gceSTATUS
++gckKERNEL_DestroyIntegerDatabase(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Database
++ );
++
++gceSTATUS
++gckKERNEL_AllocateIntegerId(
++ IN gctPOINTER Database,
++ IN gctPOINTER Pointer,
++ OUT gctUINT32 * Id
++ );
++
++gceSTATUS
++gckKERNEL_FreeIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id
++ );
++
++gceSTATUS
++gckKERNEL_QueryIntegerId(
++ IN gctPOINTER Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * Pointer
++ );
++
++/* Pointer rename */
++gctUINT32
++gckKERNEL_AllocateNameFromPointer(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Pointer
++ );
++
++gctPOINTER
++gckKERNEL_QueryPointerFromName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++gceSTATUS
++gckKERNEL_DeleteName(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name
++ );
++
++#if gcdSECURE_USER
++/* Get secure cache from the process database. */
++gceSTATUS
++gckKERNEL_GetProcessDBCache(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ OUT gcskSECURE_CACHE_PTR * Cache
++ );
++#endif
++
++/*******************************************************************************
++********* Timer Management ****************************************************/
++typedef struct _gcsTIMER * gcsTIMER_PTR;
++typedef struct _gcsTIMER
++{
++ /* Start and Stop time holders. */
++ gctUINT64 startTime;
++ gctUINT64 stopTime;
++}
++gcsTIMER;
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckDB object. */
++struct _gckDB
++{
++ /* Database management. */
++ gcsDATABASE_PTR db[16];
++ gctPOINTER dbMutex;
++ gcsDATABASE_PTR freeDatabase;
++ gcsDATABASE_RECORD_PTR freeRecord;
++ gcsDATABASE_PTR lastDatabase;
++ gctUINT32 lastProcessID;
++ gctUINT64 lastIdle;
++ gctUINT64 idleTime;
++ gctUINT64 lastSlowdown;
++ gctUINT64 lastSlowdownIdle;
++ gctPOINTER nameDatabase;
++ gctPOINTER nameDatabaseMutex;
++
++ gctPOINTER pointerDatabase;
++ gctPOINTER pointerDatabaseMutex;
++};
++
++typedef struct _gckVIRTUAL_COMMAND_BUFFER * gckVIRTUAL_COMMAND_BUFFER_PTR;
++typedef struct _gckVIRTUAL_COMMAND_BUFFER
++{
++ gctPHYS_ADDR physical;
++ gctPOINTER userLogical;
++ gctPOINTER kernelLogical;
++ gctSIZE_T bytes;
++ gctSIZE_T pageCount;
++ gctPOINTER pageTable;
++ gctUINT32 gpuAddress;
++ gctUINT pid;
++ gckVIRTUAL_COMMAND_BUFFER_PTR next;
++ gckVIRTUAL_COMMAND_BUFFER_PTR prev;
++ gckKERNEL kernel;
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++}
++gckVIRTUAL_COMMAND_BUFFER;
++
++/* gckKERNEL object. */
++struct _gckKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Core */
++ gceCORE core;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* Pointer to gckCOMMAND object. */
++ gckCOMMAND command;
++
++ /* Pointer to gckEVENT object. */
++ gckEVENT eventObj;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckMMU mmu;
++
++ /* Arom holding number of clients. */
++ gctPOINTER atomClients;
++
++#if VIVANTE_PROFILER
++ /* Enable profiling */
++ gctBOOL profileEnable;
++ /* Clear profile register or not*/
++ gctBOOL profileCleanRegister;
++#endif
++
++#ifdef QNX_SINGLE_THREADED_DEBUGGING
++ gctPOINTER debugMutex;
++#endif
++
++ /* Database management. */
++ gckDB db;
++ gctBOOL dbCreated;
++
++ gctUINT64 resetTimeStamp;
++
++ /* Pointer to gckEVENT object. */
++ gcsTIMER timers[8];
++ gctUINT32 timeOut;
++
++#if gcdENABLE_VG
++ gckVGKERNEL vg;
++#endif
++
++ /* Virtual command buffer list. */
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferHead;
++ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferTail;
++ gctPOINTER virtualBufferLock;
++
++ /* Enable virtual command buffer. */
++ gctBOOL virtualCommandBuffer;
++
++#if gcdDVFS
++ gckDVFS dvfs;
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ gctHANDLE timeline;
++#endif
++
++ /* Enable recovery. */
++ gctBOOL recovery;
++
++ /* Level of dump information after stuck. */
++ gctUINT stuckDump;
++
++#if gcdSECURITY
++ gctUINT32 securityChannel;
++#endif
++
++ /* Timer to monitor GPU stuck. */
++ gctPOINTER monitorTimer;
++
++ /* Flag to quit monitor timer. */
++ gctBOOL monitorTimerStop;
++
++ /* Monitor states. */
++ gctBOOL monitoring;
++ gctUINT32 lastCommitStamp;
++ gctUINT32 timer;
++ gctUINT32 restoreAddress;
++ gctUINT32 restoreMask;
++};
++
++struct _FrequencyHistory
++{
++ gctUINT32 frequency;
++ gctUINT32 count;
++};
++
++/* gckDVFS object. */
++struct _gckDVFS
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gctPOINTER timer;
++ gctUINT32 pollingTime;
++ gctBOOL stop;
++ gctUINT32 totalConfig;
++ gctUINT32 loads[8];
++ gctUINT8 currentScale;
++ struct _FrequencyHistory frequencyHistory[16];
++};
++
++/* gckCOMMAND object. */
++struct _gckCOMMAND
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to required object. */
++ gckKERNEL kernel;
++ gckOS os;
++
++ /* Number of bytes per page. */
++ gctUINT32 pageSize;
++
++ /* Current pipe select. */
++ gcePIPE_SELECT pipeSelect;
++
++ /* Command queue running flag. */
++ gctBOOL running;
++
++ /* Idle flag and commit stamp. */
++ gctBOOL idle;
++ gctUINT64 commitStamp;
++
++ /* Command queue mutex. */
++ gctPOINTER mutexQueue;
++
++ /* Context switching mutex. */
++ gctPOINTER mutexContext;
++
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context sequence mutex. */
++ gctPOINTER mutexContextSeq;
++#endif
++
++ /* Command queue power semaphore. */
++ gctPOINTER powerSemaphore;
++
++ /* Current command queue. */
++ struct _gcskCOMMAND_QUEUE
++ {
++ gctSIGNAL signal;
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ gctUINT32 address;
++ }
++ queues[gcdCOMMAND_QUEUES];
++
++ gctPHYS_ADDR physical;
++ gctPOINTER logical;
++ gctUINT32 address;
++ gctUINT32 offset;
++ gctINT index;
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++ gctUINT wrapCount;
++#endif
++
++ /* The command queue is new. */
++ gctBOOL newQueue;
++
++ /* Context management. */
++ gckCONTEXT currContext;
++
++ /* Pointer to last WAIT command. */
++ gctPHYS_ADDR waitPhysical;
++ gctPOINTER waitLogical;
++ gctUINT32 waitSize;
++
++ /* Command buffer alignment. */
++ gctUINT32 alignment;
++ gctUINT32 reservedHead;
++ gctUINT32 reservedTail;
++
++ /* Commit counter. */
++ gctPOINTER atomCommit;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* End Event signal. */
++ gctSIGNAL endEventSignal;
++
++#if gcdSECURE_USER
++ /* Hint array copy buffer. */
++ gctBOOL hintArrayAllocated;
++ gctUINT hintArraySize;
++ gctUINT32_PTR hintArray;
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU currentMmu;
++#endif
++ struct _gckENTRYQUEUE queue;
++};
++
++typedef struct _gcsEVENT * gcsEVENT_PTR;
++
++/* Structure holding one event to be processed. */
++typedef struct _gcsEVENT
++{
++ /* Pointer to next event in queue. */
++ gcsEVENT_PTR next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE info;
++
++ /* Process ID owning the event. */
++ gctUINT32 processID;
++
++#ifdef __QNXNTO__
++ /* Kernel. */
++ gckKERNEL kernel;
++#endif
++
++ gctBOOL fromKernel;
++}
++gcsEVENT;
++
++/* Structure holding a list of events to be processed by an interrupt. */
++typedef struct _gcsEVENT_QUEUE * gcsEVENT_QUEUE_PTR;
++typedef struct _gcsEVENT_QUEUE
++{
++ /* Time stamp. */
++ gctUINT64 stamp;
++
++ /* Source of the event. */
++ gceKERNEL_WHERE source;
++
++#if gcdMULTI_GPU
++ /* Which chip(s) of the event */
++ gceCORE_3D_MASK chipEnable;
++#endif
++
++ /* Pointer to head of event queue. */
++ gcsEVENT_PTR head;
++
++ /* Pointer to tail of event queue. */
++ gcsEVENT_PTR tail;
++
++ /* Next list of events. */
++ gcsEVENT_QUEUE_PTR next;
++}
++gcsEVENT_QUEUE;
++
++/*
++ gcdREPO_LIST_COUNT defines the maximum number of event queues with different
++ hardware module sources that may coexist at the same time. Only two sources
++ are supported - gcvKERNEL_COMMAND and gcvKERNEL_PIXEL. gcvKERNEL_COMMAND
++ source is used only for managing the kernel command queue and is only issued
++ when the current command queue gets full. Since we commit event queues every
++ time we commit command buffers, in the worst case we can have up to three
++ pending event queues:
++ - gcvKERNEL_PIXEL
++ - gcvKERNEL_COMMAND (queue overflow)
++ - gcvKERNEL_PIXEL
++*/
++#define gcdREPO_LIST_COUNT 3
++
++/* gckEVENT object. */
++struct _gckEVENT
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to required objects. */
++ gckOS os;
++ gckKERNEL kernel;
++
++ /* Time stamp. */
++ gctUINT64 stamp;
++ gctUINT32 lastCommitStamp;
++
++ /* Queue mutex. */
++ gctPOINTER eventQueueMutex;
++
++ /* Array of event queues. */
++ gcsEVENT_QUEUE queues[29];
++ gctUINT8 lastID;
++ gctPOINTER freeAtom;
++
++ /* Pending events. */
++#if gcdSMP
++#if gcdMULTI_GPU
++ gctPOINTER pending3D[gcdMULTI_GPU];
++ gctPOINTER pending3DMask[gcdMULTI_GPU];
++ gctPOINTER pendingMask;
++#endif
++ gctPOINTER pending;
++#else
++#if gcdMULTI_GPU
++ volatile gctUINT pending3D[gcdMULTI_GPU];
++ volatile gctUINT pending3DMask[gcdMULTI_GPU];
++ volatile gctUINT pendingMask;
++#endif
++ volatile gctUINT pending;
++#endif
++#if gcdMULTI_GPU
++ gctUINT32 busy;
++#endif
++
++ /* List of free event structures and its mutex. */
++ gcsEVENT_PTR freeEventList;
++ gctSIZE_T freeEventCount;
++ gctPOINTER freeEventMutex;
++
++ /* Event queues. */
++ gcsEVENT_QUEUE_PTR queueHead;
++ gcsEVENT_QUEUE_PTR queueTail;
++ gcsEVENT_QUEUE_PTR freeList;
++ gcsEVENT_QUEUE repoList[gcdREPO_LIST_COUNT];
++ gctPOINTER eventListMutex;
++
++ gctPOINTER submitTimer;
++
++#if gcdINTERRUPT_STATISTIC
++ gctPOINTER interruptCount;
++#endif
++
++#if gcdRECORD_COMMAND
++ gckRECORDER recorder;
++#endif
++};
++
++/* Free all events belonging to a process. */
++gceSTATUS
++gckEVENT_FreeProcess(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID
++ );
++
++gceSTATUS
++gckEVENT_Stop(
++ IN gckEVENT Event,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctPOINTER Logical,
++ IN gctSIGNAL Signal,
++ IN OUT gctUINT32 * waitSize
++ );
++
++typedef struct _gcsLOCK_INFO * gcsLOCK_INFO_PTR;
++typedef struct _gcsLOCK_INFO
++{
++ gctUINT32 GPUAddresses[gcdMAX_GPU_COUNT];
++ gctPOINTER pageTables[gcdMAX_GPU_COUNT];
++ gctUINT32 lockeds[gcdMAX_GPU_COUNT];
++ gckKERNEL lockKernels[gcdMAX_GPU_COUNT];
++ gckMMU lockMmus[gcdMAX_GPU_COUNT];
++}
++gcsLOCK_INFO;
++
++typedef struct _gcsGPU_MAP * gcsGPU_MAP_PTR;
++typedef struct _gcsGPU_MAP
++{
++ gctINT pid;
++ gcsLOCK_INFO lockInfo;
++ gcsGPU_MAP_PTR prev;
++ gcsGPU_MAP_PTR next;
++}
++gcsGPU_MAP;
++
++/* gcuVIDMEM_NODE structure. */
++typedef union _gcuVIDMEM_NODE
++{
++ /* Allocated from gckVIDMEM. */
++ struct _gcsVIDMEM_NODE_VIDMEM
++ {
++ /* Owner of this node. */
++ gckVIDMEM memory;
++
++ /* Dual-linked list of nodes. */
++ gcuVIDMEM_NODE_PTR next;
++ gcuVIDMEM_NODE_PTR prev;
++
++ /* Dual linked list of free nodes. */
++ gcuVIDMEM_NODE_PTR nextFree;
++ gcuVIDMEM_NODE_PTR prevFree;
++
++ /* Information for this node. */
++ gctSIZE_T offset;
++ gctSIZE_T bytes;
++ gctUINT32 alignment;
++
++#ifdef __QNXNTO__
++ /* Client virtual address. */
++ gctPOINTER logical;
++#endif
++
++ /* Locked counter. */
++ gctINT32 locked;
++
++ /* Memory pool. */
++ gcePOOL pool;
++ gctUINT32 physical;
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++#if gcdENABLE_VG
++ gctPOINTER kernelVirtual;
++#endif
++ }
++ VidMem;
++
++ /* Allocated from gckOS. */
++ struct _gcsVIDMEM_NODE_VIRTUAL
++ {
++ /* Pointer to gckKERNEL object. */
++ gckKERNEL kernel;
++
++ /* Information for this node. */
++ /* Contiguously allocated? */
++ gctBOOL contiguous;
++ /* mdl record pointer... a kmalloc address. Process agnostic. */
++ gctPHYS_ADDR physical;
++ gctSIZE_T bytes;
++ /* do_mmap_pgoff address... mapped per-process. */
++ gctPOINTER logical;
++
++#if gcdENABLE_VG
++ /* Physical address of this node, only meaningful when it is contiguous. */
++ gctUINT32 physicalAddress;
++
++ /* Kernel logical of this node. */
++ gctPOINTER kernelVirtual;
++#endif
++
++ /* Customer private handle */
++ gctUINT32 gid;
++
++ /* Page table information. */
++ /* Used only when node is not contiguous */
++ gctSIZE_T pageCount;
++
++ /* Used only when node is not contiguous */
++ gctPOINTER pageTables[gcdMAX_GPU_COUNT];
++ /* Pointer to gckKERNEL object who lock this. */
++ gckKERNEL lockKernels[gcdMAX_GPU_COUNT];
++ /* Actual physical address */
++ gctUINT32 addresses[gcdMAX_GPU_COUNT];
++
++ /* Locked counter. */
++ gctINT32 lockeds[gcdMAX_GPU_COUNT];
++
++ /* Process ID owning this memory. */
++ gctUINT32 processID;
++
++ /* Surface type. */
++ gceSURF_TYPE type;
++ }
++ Virtual;
++}
++gcuVIDMEM_NODE;
++
++/* gckVIDMEM object. */
++struct _gckVIDMEM
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Information for this video memory heap. */
++ gctUINT32 baseAddress;
++ gctSIZE_T bytes;
++ gctSIZE_T freeBytes;
++
++ /* Mapping for each type of surface. */
++ gctINT mapping[gcvSURF_NUM_TYPES];
++
++ /* Sentinel nodes for up to 8 banks. */
++ gcuVIDMEM_NODE sentinel[8];
++
++ /* Allocation threshold. */
++ gctSIZE_T threshold;
++
++ /* The heap mutex. */
++ gctPOINTER mutex;
++};
++
++typedef struct _gcsVIDMEM_NODE
++{
++ /* Pointer to gcuVIDMEM_NODE. */
++ gcuVIDMEM_NODE_PTR node;
++
++ /* Mutex to protect node. */
++ gctPOINTER mutex;
++
++ /* Reference count. */
++ gctPOINTER reference;
++
++ /* Name for client to import. */
++ gctUINT32 name;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Head of mapping list. */
++ gcsGPU_MAP_PTR mapHead;
++
++ /* Tail of mapping list. */
++ gcsGPU_MAP_PTR mapTail;
++
++ gctPOINTER mapMutex;
++#endif
++
++ /* Surface Type. */
++ gceSURF_TYPE type;
++
++ /* Pool from which node is allocated. */
++ gcePOOL pool;
++}
++gcsVIDMEM_NODE;
++
++typedef struct _gcsVIDMEM_HANDLE * gckVIDMEM_HANDLE;
++typedef struct _gcsVIDMEM_HANDLE
++{
++ /* Pointer to gckVIDMEM_NODE. */
++ gckVIDMEM_NODE node;
++
++ /* Handle for current process. */
++ gctUINT32 handle;
++
++ /* Reference count for this handle. */
++ gctPOINTER reference;
++}
++gcsVIDMEM_HANDLE;
++
++typedef struct _gcsSHBUF * gcsSHBUF_PTR;
++typedef struct _gcsSHBUF
++{
++ /* ID. */
++ gctUINT32 id;
++
++ /* Reference count. */
++ gctPOINTER reference;
++
++ /* Data size. */
++ gctUINT32 size;
++
++ /* Data. */
++ gctPOINTER data;
++}
++gcsSHBUF;
++
++gceSTATUS
++gckVIDMEM_HANDLE_Reference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ );
++
++gceSTATUS
++gckVIDMEM_HANDLE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Allocate(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR VideoNode,
++ IN gceSURF_TYPE Type,
++ IN gcePOOL Pool,
++ IN gctUINT32 * Handle
++ );
++
++gceSTATUS
++gckVIDMEM_Node_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ OUT gctUINT32 *Address
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctUINT32 ProcessID
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Name(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ IN gctUINT32 * Name
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_Import(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name,
++ IN gctUINT32 * Handle
++ );
++
++gceSTATUS
++gckVIDMEM_HANDLE_LookupAndReference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ );
++
++gceSTATUS
++gckVIDMEM_HANDLE_Lookup(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ );
++
++gceSTATUS
++gckVIDMEM_NODE_GetFd(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gctINT * Fd
++ );
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckEVENT_DestroyMmu(
++ IN gckEVENT Event,
++ IN gckMMU Mmu,
++ IN gceKERNEL_WHERE FromWhere
++ );
++#endif
++
++/* gckMMU object. */
++struct _gckMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER pageTableMutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctUINT32_PTR pageTableLogical;
++ gctUINT32 pageTableEntries;
++
++ /* Master TLB information. */
++ gctSIZE_T mtlbSize;
++ gctPHYS_ADDR mtlbPhysical;
++ gctUINT32_PTR mtlbLogical;
++ gctUINT32 mtlbEntries;
++
++ /* Free entries. */
++ gctUINT32 heapList;
++ gctBOOL freeNodes;
++
++ gctPOINTER staticSTLB;
++ gctBOOL enabled;
++
++ gctUINT32 dynamicMappingStart;
++
++ gctUINT32_PTR mapLogical;
++#if gcdPROCESS_ADDRESS_SPACE
++ gctPOINTER pageTableDirty[gcdMAX_GPU_COUNT];
++ gctPOINTER stlbs;
++#endif
++};
++
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckOS_CreateUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++gceSTATUS
++gckOS_DestroyUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckOS_GetFd(
++ IN gctSTRING Name,
++ IN gcsFDPRIVATE_PTR Private,
++ OUT gctINT *Fd
++ );
++
++gceSTATUS
++gckKERNEL_AllocateVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++gceSTATUS
++gckKERNEL_DestroyVirtualCommandBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gckKERNEL_GetGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ );
++
++gceSTATUS
++gckKERNEL_QueryGPUAddress(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GpuAddress,
++ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer
++ );
++
++gceSTATUS
++gckKERNEL_AttachProcess(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach
++ );
++
++gceSTATUS
++gckKERNEL_AttachProcessEx(
++ IN gckKERNEL Kernel,
++ IN gctBOOL Attach,
++ IN gctUINT32 PID
++ );
++
++#if gcdSECURE_USER
++gceSTATUS
++gckKERNEL_MapLogicalToPhysical(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN OUT gctPOINTER * Data
++ );
++
++gceSTATUS
++gckKERNEL_FlushTranslationCache(
++ IN gckKERNEL Kernel,
++ IN gcskSECURE_CACHE_PTR Cache,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++#endif
++
++gceSTATUS
++gckHARDWARE_QueryIdle(
++ IN gckHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++
++#if gcdSECURITY
++gceSTATUS
++gckKERNEL_SecurityOpen(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GPU,
++ OUT gctUINT32 *Channel
++ );
++
++/*
++** Close a security service channel
++*/
++gceSTATUS
++gckKERNEL_SecurityClose(
++ IN gctUINT32 Channel
++ );
++
++/*
++** Security service interface.
++*/
++gceSTATUS
++gckKERNEL_SecurityCallService(
++ IN gctUINT32 Channel,
++ IN OUT gcsTA_INTERFACE * Interface
++ );
++
++gceSTATUS
++gckKERNEL_SecurityStartCommand(
++ IN gckKERNEL Kernel
++ );
++
++gceSTATUS
++gckKERNEL_SecurityAllocateSecurityMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Bytes,
++ OUT gctUINT32 * Handle
++ );
++
++gceSTATUS
++gckKERNEL_SecurityExecute(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Buffer,
++ IN gctUINT32 Bytes
++ );
++
++gceSTATUS
++gckKERNEL_SecurityMapMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 *PhysicalArray,
++ IN gctUINT32 PageCount,
++ OUT gctUINT32 * GPUAddress
++ );
++
++gceSTATUS
++gckKERNEL_SecurityUnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GPUAddress,
++ IN gctUINT32 PageCount
++ );
++
++#endif
++
++gceSTATUS
++gckKERNEL_CreateShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Size,
++ OUT gctSHBUF * ShBuf
++ );
++
++gceSTATUS
++gckKERNEL_DestroyShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ );
++
++gceSTATUS
++gckKERNEL_MapShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf
++ );
++
++gceSTATUS
++gckKERNEL_WriteShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount
++ );
++
++gceSTATUS
++gckKERNEL_ReadShBuffer(
++ IN gckKERNEL Kernel,
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER UserData,
++ IN gctUINT32 ByteCount,
++ OUT gctUINT32 * BytesRead
++ );
++
++
++/******************************************************************************\
++******************************* gckCONTEXT Object *******************************
++\******************************************************************************/
++
++gceSTATUS
++gckCONTEXT_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ OUT gckCONTEXT * Context
++ );
++
++gceSTATUS
++gckCONTEXT_Destroy(
++ IN gckCONTEXT Context
++ );
++
++gceSTATUS
++gckCONTEXT_Update(
++ IN gckCONTEXT Context,
++ IN gctUINT32 ProcessID,
++ IN gcsSTATE_DELTA_PTR StateDelta
++ );
++
++gceSTATUS
++gckCONTEXT_MapBuffer(
++ IN gckCONTEXT Context,
++ OUT gctUINT32 *Physicals,
++ OUT gctUINT64 *Logicals,
++ OUT gctUINT32 *Bytes
++ );
++
++#if gcdLINK_QUEUE_SIZE
++void
++gckLINKQUEUE_Enqueue(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 start,
++ IN gctUINT32 end
++ );
++
++void
++gckLINKQUEUE_GetData(
++ IN gckLINKQUEUE LinkQueue,
++ IN gctUINT32 Index,
++ OUT gckLINKDATA * Data
++ );
++#endif
++
++gceSTATUS
++gckENTRYQUEUE_Enqueue(
++ IN gckKERNEL Kernel,
++ IN gckENTRYQUEUE Queue,
++ IN gctUINT32 physical,
++ IN gctUINT32 bytes
++ );
++
++gceSTATUS
++gckENTRYQUEUE_Dequeue(
++ IN gckENTRYQUEUE Queue,
++ OUT gckENTRYDATA * Data
++ );
++
++/******************************************************************************\
++****************************** gckRECORDER Object ******************************
++\******************************************************************************/
++gceSTATUS
++gckRECORDER_Construct(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ OUT gckRECORDER * Recorder
++ );
++
++gceSTATUS
++gckRECORDER_Destory(
++ IN gckOS Os,
++ IN gckRECORDER Recorder
++ );
++
++void
++gckRECORDER_AdvanceIndex(
++ gckRECORDER Recorder,
++ gctUINT64 CommitStamp
++ );
++
++void
++gckRECORDER_Record(
++ gckRECORDER Recorder,
++ gctUINT8_PTR CommandBuffer,
++ gctUINT32 CommandBytes,
++ gctUINT8_PTR ContextBuffer,
++ gctUINT32 ContextBytes
++ );
++
++void
++gckRECORDER_Dump(
++ gckRECORDER Recorder
++ );
++
++gceSTATUS
++gckRECORDER_UpdateMirror(
++ gckRECORDER Recorder,
++ gctUINT32 State,
++ gctUINT32 Data
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_heap.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,858 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/**
++** @file
++** gckHEAP object for kernel HAL layer. The heap implemented here is an arena-
++** based memory allocation. An arena-based memory heap allocates data quickly
++** from specified arenas and reduces memory fragmentation.
++**
++*/
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_HEAP
++
++/*******************************************************************************
++***** Structures ***************************************************************
++*******************************************************************************/
++#define gcdIN_USE ((gcskNODE_PTR)gcvMAXUINTPTR_T)
++
++typedef struct _gcskNODE * gcskNODE_PTR;
++typedef struct _gcskNODE
++{
++ /* Number of byets in node. */
++ gctSIZE_T bytes;
++
++ /* Pointer to next free node, or gcvNULL to mark the node as freed, or
++ ** gcdIN_USE to mark the node as used. */
++ gcskNODE_PTR next;
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Time stamp of allocation. */
++ gctUINT64 timeStamp;
++#endif
++}
++gcskNODE;
++
++typedef struct _gcskHEAP * gcskHEAP_PTR;
++typedef struct _gcskHEAP
++{
++ /* Linked list. */
++ gcskHEAP_PTR next;
++ gcskHEAP_PTR prev;
++
++ /* Heap size. */
++ gctSIZE_T size;
++
++ /* Free list. */
++ gcskNODE_PTR freeList;
++}
++gcskHEAP;
++
++struct _gckHEAP
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to a gckOS object. */
++ gckOS os;
++
++ /* Locking mutex. */
++ gctPOINTER mutex;
++
++ /* Allocation parameters. */
++ gctSIZE_T allocationSize;
++
++ /* Heap list. */
++ gcskHEAP_PTR heap;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT64 timeStamp;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Profile information. */
++ gctUINT32 allocCount;
++ gctUINT64 allocBytes;
++ gctUINT64 allocBytesMax;
++ gctUINT64 allocBytesTotal;
++ gctUINT32 heapCount;
++ gctUINT32 heapCountMax;
++ gctUINT64 heapMemory;
++ gctUINT64 heapMemoryMax;
++#endif
++};
++
++/*******************************************************************************
++***** Static Support Functions *************************************************
++*******************************************************************************/
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++static gctSIZE_T
++_DumpHeap(
++ IN gcskHEAP_PTR Heap
++ )
++{
++ gctPOINTER p;
++ gctSIZE_T leaked = 0;
++
++ /* Start at first node. */
++ for (p = Heap + 1;;)
++ {
++ /* Convert the pointer. */
++ gcskNODE_PTR node = (gcskNODE_PTR) p;
++
++ /* Check if this is a used node. */
++ if (node->next == gcdIN_USE)
++ {
++ /* Print the leaking node. */
++ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_HEAP,
++ "Detected leaking: node=0x%x bytes=%lu timeStamp=%llu "
++ "(%08X %c%c%c%c)",
++ node, node->bytes, node->timeStamp,
++ ((gctUINT32_PTR) (node + 1))[0],
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[0]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[1]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[2]),
++ gcmPRINTABLE(((gctUINT8_PTR) (node + 1))[3]));
++
++ /* Add leaking byte count. */
++ leaked += node->bytes;
++ }
++
++ /* Test for end of heap. */
++ if (node->bytes == 0)
++ {
++ break;
++ }
++
++ else
++ {
++ /* Move to next node. */
++ p = (gctUINT8_PTR) node + node->bytes;
++ }
++ }
++
++ /* Return the number of leaked bytes. */
++ return leaked;
++}
++#endif
++
++static gceSTATUS
++_CompactKernelHeap(
++ IN gckHEAP Heap
++ )
++{
++ gcskHEAP_PTR heap, next;
++ gctPOINTER p;
++ gcskHEAP_PTR freeList = gcvNULL;
++
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ /* Walk all the heaps. */
++ for (heap = Heap->heap; heap != gcvNULL; heap = next)
++ {
++ gcskNODE_PTR lastFree = gcvNULL;
++
++ /* Zero out the free list. */
++ heap->freeList = gcvNULL;
++
++ /* Start at the first node. */
++ for (p = (gctUINT8_PTR) (heap + 1);;)
++ {
++ /* Convert the pointer. */
++ gcskNODE_PTR node = (gcskNODE_PTR) p;
++
++ gcmkASSERT(p <= (gctPOINTER) ((gctUINT8_PTR) (heap + 1) + heap->size));
++
++ /* Test if this node not used. */
++ if (node->next != gcdIN_USE)
++ {
++ /* Test if this is the end of the heap. */
++ if (node->bytes == 0)
++ {
++ break;
++ }
++
++ /* Test of this is the first free node. */
++ else if (lastFree == gcvNULL)
++ {
++ /* Initialzie the free list. */
++ heap->freeList = node;
++ lastFree = node;
++ }
++
++ else
++ {
++ /* Test if this free node is contiguous with the previous
++ ** free node. */
++ if ((gctUINT8_PTR) lastFree + lastFree->bytes == p)
++ {
++ /* Just increase the size of the previous free node. */
++ lastFree->bytes += node->bytes;
++ }
++ else
++ {
++ /* Add to linked list. */
++ lastFree->next = node;
++ lastFree = node;
++ }
++ }
++ }
++
++ /* Move to next node. */
++ p = (gctUINT8_PTR) node + node->bytes;
++ }
++
++ /* Mark the end of the chain. */
++ if (lastFree != gcvNULL)
++ {
++ lastFree->next = gcvNULL;
++ }
++
++ /* Get next heap. */
++ next = heap->next;
++
++ /* Check if the entire heap is free. */
++ if ((heap->freeList != gcvNULL)
++ && (heap->freeList->bytes == heap->size - gcmSIZEOF(gcskNODE))
++ )
++ {
++ /* Remove the heap from the linked list. */
++ if (heap->prev == gcvNULL)
++ {
++ Heap->heap = next;
++ }
++ else
++ {
++ heap->prev->next = next;
++ }
++
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap->prev;
++ }
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profiling. */
++ Heap->heapCount -= 1;
++ Heap->heapMemory -= heap->size + gcmSIZEOF(gcskHEAP);
++#endif
++
++ /* Add this heap to the list of heaps that need to be freed. */
++ heap->next = freeList;
++ freeList = heap;
++ }
++ }
++
++ if (freeList != gcvNULL)
++ {
++ /* Release the mutex, remove any chance for a dead lock. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Free all heaps in the free list. */
++ for (heap = freeList; heap != gcvNULL; heap = next)
++ {
++ /* Get pointer to the next heap. */
++ next = heap->next;
++
++ /* Free the heap. */
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HEAP,
++ "Freeing heap 0x%x (%lu bytes)",
++ heap, heap->size + gcmSIZEOF(gcskHEAP));
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, heap));
++ }
++
++ /* Acquire the mutex again. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++***** gckHEAP API Code *********************************************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckHEAP_Construct
++**
++** Construct a new gckHEAP object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctSIZE_T AllocationSize
++** Minimum size per arena.
++**
++** OUTPUT:
++**
++** gckHEAP * Heap
++** Pointer to a variable that will hold the pointer to the gckHEAP
++** object.
++*/
++gceSTATUS
++gckHEAP_Construct(
++ IN gckOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gckHEAP * Heap
++ )
++{
++ gceSTATUS status;
++ gckHEAP heap = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x AllocationSize=%lu", Os, AllocationSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Heap != gcvNULL);
++
++ /* Allocate the gckHEAP object. */
++ gcmkONERROR(gckOS_AllocateMemory(Os,
++ gcmSIZEOF(struct _gckHEAP),
++ &pointer));
++
++ heap = pointer;
++
++ /* Initialize the gckHEAP object. */
++ heap->object.type = gcvOBJ_HEAP;
++ heap->os = Os;
++ heap->allocationSize = AllocationSize;
++ heap->heap = gcvNULL;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ heap->timeStamp = 0;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Zero the counters. */
++ heap->allocCount = 0;
++ heap->allocBytes = 0;
++ heap->allocBytesMax = 0;
++ heap->allocBytesTotal = 0;
++ heap->heapCount = 0;
++ heap->heapCountMax = 0;
++ heap->heapMemory = 0;
++ heap->heapMemoryMax = 0;
++#endif
++
++ /* Create the mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &heap->mutex));
++
++ /* Return the pointer to the gckHEAP object. */
++ *Heap = heap;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Heap=0x%x", *Heap);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (heap != gcvNULL)
++ {
++ /* Free the heap structure. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Os, heap));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Destroy
++**
++** Destroy a gckHEAP object.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckHEAP_Destroy(
++ IN gckHEAP Heap
++ )
++{
++ gcskHEAP_PTR heap;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctSIZE_T leaked = 0;
++#endif
++
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ for (heap = Heap->heap; heap != gcvNULL; heap = Heap->heap)
++ {
++ /* Unlink heap from linked list. */
++ Heap->heap = heap->next;
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Check for leaked memory. */
++ leaked += _DumpHeap(heap);
++#endif
++
++ /* Free the heap. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, heap));
++ }
++
++ /* Free the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Heap->os, Heap->mutex));
++
++ /* Free the heap structure. */
++ gcmkVERIFY_OK(gckOS_FreeMemory(Heap->os, Heap));
++
++ /* Success. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gcmkFOOTER_ARG("leaked=%lu", leaked);
++#else
++ gcmkFOOTER_NO();
++#endif
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Allocate
++**
++** Allocate data from the heap.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object.
++**
++** IN gctSIZE_T Bytes
++** Number of byte to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the address of the allocated
++** memory.
++*/
++gceSTATUS
++gckHEAP_Allocate(
++ IN gckHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gctBOOL acquired = gcvFALSE;
++ gcskHEAP_PTR heap;
++ gceSTATUS status;
++ gctSIZE_T bytes;
++ gcskNODE_PTR node, used, prevFree = gcvNULL;
++ gctPOINTER memory = gcvNULL;
++
++ gcmkHEADER_ARG("Heap=0x%x Bytes=%lu", Heap, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Determine number of bytes required for a node. */
++ bytes = gcmALIGN(Bytes + gcmSIZEOF(gcskNODE), 8);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ /* Check if this allocation is bigger than the default allocation size. */
++ if (bytes > Heap->allocationSize - gcmSIZEOF(gcskHEAP) - gcmSIZEOF(gcskNODE))
++ {
++ /* Adjust allocation size. */
++ Heap->allocationSize = bytes * 2;
++ }
++
++ else if (Heap->heap != gcvNULL)
++ {
++ gctINT i;
++
++ /* 2 retries, since we might need to compact. */
++ for (i = 0; i < 2; ++i)
++ {
++ /* Walk all the heaps. */
++ for (heap = Heap->heap; heap != gcvNULL; heap = heap->next)
++ {
++ /* Check if this heap has enough bytes to hold the request. */
++ if (bytes <= heap->size - gcmSIZEOF(gcskNODE))
++ {
++ prevFree = gcvNULL;
++
++ /* Walk the chain of free nodes. */
++ for (node = heap->freeList;
++ node != gcvNULL;
++ node = node->next
++ )
++ {
++ gcmkASSERT(node->next != gcdIN_USE);
++
++ /* Check if this free node has enough bytes. */
++ if (node->bytes >= bytes)
++ {
++ /* Use the node. */
++ goto UseNode;
++ }
++
++ /* Save current free node for linked list management. */
++ prevFree = node;
++ }
++ }
++ }
++
++ if (i == 0)
++ {
++ /* Compact the heap. */
++ gcmkVERIFY_OK(_CompactKernelHeap(Heap));
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "===== KERNEL HEAP =====");
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of allocations : %12u",
++ Heap->allocCount);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of bytes allocated : %12llu",
++ Heap->allocBytes);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum allocation size : %12llu",
++ Heap->allocBytesMax);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Total number of bytes allocated : %12llu",
++ Heap->allocBytesTotal);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Number of heaps : %12u",
++ Heap->heapCount);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Heap memory in bytes : %12llu",
++ Heap->heapMemory);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum number of heaps : %12u",
++ Heap->heapCountMax);
++ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HEAP,
++ "Maximum heap memory in bytes : %12llu",
++ Heap->heapMemoryMax);
++#endif
++ }
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkONERROR(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ acquired = gcvFALSE;
++
++ /* Allocate a new heap. */
++ gcmkONERROR(
++ gckOS_AllocateMemory(Heap->os,
++ Heap->allocationSize,
++ &memory));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HEAP,
++ "Allocated heap 0x%x (%lu bytes)",
++ memory, Heap->allocationSize);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ /* Use the allocated memory as the heap. */
++ heap = (gcskHEAP_PTR) memory;
++
++ /* Insert this heap to the head of the chain. */
++ heap->next = Heap->heap;
++ heap->prev = gcvNULL;
++ heap->size = Heap->allocationSize - gcmSIZEOF(gcskHEAP);
++
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap;
++ }
++ Heap->heap = heap;
++
++ /* Mark the end of the heap. */
++ node = (gcskNODE_PTR) ( (gctUINT8_PTR) heap
++ + Heap->allocationSize
++ - gcmSIZEOF(gcskNODE)
++ );
++ node->bytes = 0;
++ node->next = gcvNULL;
++
++ /* Create a free list. */
++ node = (gcskNODE_PTR) (heap + 1);
++ heap->freeList = node;
++
++ /* Initialize the free list. */
++ node->bytes = heap->size - gcmSIZEOF(gcskNODE);
++ node->next = gcvNULL;
++
++ /* No previous free. */
++ prevFree = gcvNULL;
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profiling. */
++ Heap->heapCount += 1;
++ Heap->heapMemory += Heap->allocationSize;
++
++ if (Heap->heapCount > Heap->heapCountMax)
++ {
++ Heap->heapCountMax = Heap->heapCount;
++ }
++ if (Heap->heapMemory > Heap->heapMemoryMax)
++ {
++ Heap->heapMemoryMax = Heap->heapMemory;
++ }
++#endif
++
++UseNode:
++ /* Verify some stuff. */
++ gcmkASSERT(heap != gcvNULL);
++ gcmkASSERT(node != gcvNULL);
++ gcmkASSERT(node->bytes >= bytes);
++
++ if (heap->prev != gcvNULL)
++ {
++ /* Unlink the heap from the linked list. */
++ heap->prev->next = heap->next;
++ if (heap->next != gcvNULL)
++ {
++ heap->next->prev = heap->prev;
++ }
++
++ /* Move the heap to the front of the list. */
++ heap->next = Heap->heap;
++ heap->prev = gcvNULL;
++ Heap->heap = heap;
++ heap->next->prev = heap;
++ }
++
++ /* Check if there is enough free space left after usage for another free
++ ** node. */
++ if (node->bytes - bytes >= gcmSIZEOF(gcskNODE))
++ {
++ /* Allocated used space from the back of the free list. */
++ used = (gcskNODE_PTR) ((gctUINT8_PTR) node + node->bytes - bytes);
++
++ /* Adjust the number of free bytes. */
++ node->bytes -= bytes;
++ gcmkASSERT(node->bytes >= gcmSIZEOF(gcskNODE));
++ }
++ else
++ {
++ /* Remove this free list from the chain. */
++ if (prevFree == gcvNULL)
++ {
++ heap->freeList = node->next;
++ }
++ else
++ {
++ prevFree->next = node->next;
++ }
++
++ /* Consume the entire free node. */
++ used = (gcskNODE_PTR) node;
++ bytes = node->bytes;
++ }
++
++ /* Mark node as used. */
++ used->bytes = bytes;
++ used->next = gcdIN_USE;
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ used->timeStamp = ++Heap->timeStamp;
++#endif
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profile counters. */
++ Heap->allocCount += 1;
++ Heap->allocBytes += bytes;
++ Heap->allocBytesMax = gcmMAX(Heap->allocBytes, Heap->allocBytesMax);
++ Heap->allocBytesTotal += bytes;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Return pointer to memory. */
++ *Memory = used + 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%x", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++ }
++
++ if (memory != gcvNULL)
++ {
++ /* Free the heap memory. */
++ gckOS_FreeMemory(Heap->os, memory);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckHEAP_Free
++**
++** Free allocated memory from the heap.
++**
++** INPUT:
++**
++** gckHEAP Heap
++** Pointer to a gckHEAP object.
++**
++** IN gctPOINTER Memory
++** Pointer to memory to free.
++**
++** OUTPUT:
++**
++** NOTHING.
++*/
++gceSTATUS
++gckHEAP_Free(
++ IN gckHEAP Heap,
++ IN gctPOINTER Memory
++ )
++{
++ gcskNODE_PTR node;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Heap=0x%x Memory=0x%x", Heap, Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(Heap->os, Heap->mutex, gcvINFINITE));
++
++ /* Pointer to structure. */
++ node = (gcskNODE_PTR) Memory - 1;
++
++ /* Mark the node as freed. */
++ node->next = gcvNULL;
++
++#if VIVANTE_PROFILER || gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Update profile counters. */
++ Heap->allocBytes -= node->bytes;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_ReleaseMutex(Heap->os, Heap->mutex));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHEAP_ProfileStart(
++ IN gckHEAP Heap
++ )
++{
++ gcmkHEADER_ARG("Heap=0x%x", Heap);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++
++ /* Zero the counters. */
++ Heap->allocCount = 0;
++ Heap->allocBytes = 0;
++ Heap->allocBytesMax = 0;
++ Heap->allocBytesTotal = 0;
++ Heap->heapCount = 0;
++ Heap->heapCountMax = 0;
++ Heap->heapMemory = 0;
++ Heap->heapMemoryMax = 0;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckHEAP_ProfileEnd(
++ IN gckHEAP Heap,
++ IN gctCONST_STRING Title
++ )
++{
++ gcmkHEADER_ARG("Heap=0x%x Title=0x%x", Heap, Title);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Heap, gcvOBJ_HEAP);
++ gcmkVERIFY_ARGUMENT(Title != gcvNULL);
++
++ gcmkPRINT("");
++ gcmkPRINT("=====[ HEAP - %s ]=====", Title);
++ gcmkPRINT("Number of allocations : %12u", Heap->allocCount);
++ gcmkPRINT("Number of bytes allocated : %12llu", Heap->allocBytes);
++ gcmkPRINT("Maximum allocation size : %12llu", Heap->allocBytesMax);
++ gcmkPRINT("Total number of bytes allocated : %12llu", Heap->allocBytesTotal);
++ gcmkPRINT("Number of heaps : %12u", Heap->heapCount);
++ gcmkPRINT("Heap memory in bytes : %12llu", Heap->heapMemory);
++ gcmkPRINT("Maximum number of heaps : %12u", Heap->heapCountMax);
++ gcmkPRINT("Maximum heap memory in bytes : %12llu", Heap->heapMemoryMax);
++ gcmkPRINT("==============================================");
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif /* VIVANTE_PROFILER */
++
++/*******************************************************************************
++***** Test Code ****************************************************************
++*******************************************************************************/
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_interrupt_vg.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,877 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++/******************************************************************************\
++*********************** Support Functions and Definitions **********************
++\******************************************************************************/
++
++/* Interruot statistics will be accumulated if not zero. */
++#define gcmENABLE_INTERRUPT_STATISTICS 0
++
++#define _GC_OBJ_ZONE gcvZONE_INTERRUPT
++
++/* Object structure. */
++struct _gckVGINTERRUPT
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* gckVGKERNEL pointer. */
++ gckVGKERNEL kernel;
++
++ /* gckOS pointer. */
++ gckOS os;
++
++ /* Interrupt handlers. */
++ gctINTERRUPT_HANDLER handlers[32];
++
++ /* Main interrupt handler thread. */
++ gctTHREAD handler;
++ gctBOOL terminate;
++
++ /* Interrupt FIFO. */
++ gctSEMAPHORE fifoValid;
++ gctUINT32 fifo[256];
++ gctUINT fifoItems;
++ gctUINT8 head;
++ gctUINT8 tail;
++
++ /* Interrupt statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT maxFifoItems;
++ gctUINT fifoOverflow;
++ gctUINT maxSimultaneous;
++ gctUINT multipleCount;
++#endif
++};
++
++
++/*******************************************************************************
++**
++** _ProcessInterrupt
++**
++** The interrupt processor.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt,
++ gctUINT_PTR TriggeredCount
++ )
++#else
++static void
++_ProcessInterrupt(
++ gckVGINTERRUPT Interrupt
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++ gctUINT i;
++
++ /* Advance to the next entry. */
++ Interrupt->tail += 1;
++ Interrupt->fifoItems -= 1;
++
++ /* Get the interrupt value. */
++ triggered = Interrupt->fifo[Interrupt->tail];
++ gcmkASSERT(triggered != 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: triggered=0x%08X\n",
++ __FUNCTION__,
++ triggered
++ );
++
++ /* Walk through all possible interrupts. */
++ for (i = 0; i < gcmSIZEOF(Interrupt->handlers); i += 1)
++ {
++ /* Test if interrupt happened. */
++ if ((triggered & 1) == 1)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (TriggeredCount != gcvNULL)
++ {
++ (* TriggeredCount) += 1;
++ }
++#endif
++
++ /* Make sure we have valid handler. */
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Interrupt %d isn't registered.\n",
++ __FUNCTION__, i
++ );
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: interrupt=%d\n",
++ __FUNCTION__,
++ i
++ );
++
++ /* Call the handler. */
++ status = Interrupt->handlers[i] (Interrupt->kernel);
++
++ if (gcmkIS_ERROR(status))
++ {
++ /* Failed to signal the semaphore. */
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s: Error %d incrementing the semaphore #%d.\n",
++ __FUNCTION__, status, i
++ );
++ }
++ }
++ }
++
++ /* Next interrupt. */
++ triggered >>= 1;
++
++ /* No more interrupts to handle? */
++ if (triggered == 0)
++ {
++ break;
++ }
++ }
++}
++
++
++/*******************************************************************************
++**
++** _MainInterruptHandler
++**
++** The main interrupt thread serves the interrupt FIFO and calls registered
++** handlers for the interrupts that occured. The handlers are called in the
++** sequence interrupts occured with the exception when multiple interrupts
++** occured at the same time. In that case the handler calls are "sorted" by
++** the interrupt number therefore giving the interrupts with lower numbers
++** higher priority.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gctTHREADFUNCRESULT gctTHREADFUNCTYPE
++_MainInterruptHandler(
++ gctTHREADFUNCPARAMETER ThreadParameter
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gctUINT count;
++#endif
++
++ /* Cast the object. */
++ interrupt = (gckVGINTERRUPT) ThreadParameter;
++
++ /* Enter the loop. */
++ while (gcvTRUE)
++ {
++ /* Wait for an interrupt. */
++ status = gckOS_DecrementSemaphore(interrupt->os, interrupt->fifoValid);
++
++ /* Error? */
++ if (gcmkIS_ERROR(status))
++ {
++ break;
++ }
++
++ /* System termination request? */
++ if (status == gcvSTATUS_TERMINATE)
++ {
++ break;
++ }
++
++ /* Driver is shutting down? */
++ if (interrupt->terminate)
++ {
++ break;
++ }
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Reset triggered count. */
++ count = 0;
++
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt, &count);
++
++ /* Update conters. */
++ if (count > interrupt->maxSimultaneous)
++ {
++ interrupt->maxSimultaneous = count;
++ }
++
++ if (count > 1)
++ {
++ interrupt->multipleCount += 1;
++ }
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(interrupt);
++#endif
++ }
++
++ return 0;
++}
++
++
++/*******************************************************************************
++**
++** _StartInterruptHandler / _StopInterruptHandler
++**
++** Main interrupt handler routine control.
++**
++** INPUT:
++**
++** ThreadParameter
++** Pointer to the gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++static gceSTATUS
++_StartInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status, last;
++
++ do
++ {
++ /* Objects must not be already created. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++ gcmkASSERT(Interrupt->handler == gcvNULL);
++
++ /* Reset the termination request. */
++ Interrupt->terminate = gcvFALSE;
++
++#if !gcdENABLE_INFINITE_SPEED_HW
++ /* Construct the fifo semaphore. */
++ gcmkERR_BREAK(gckOS_CreateSemaphoreVG(
++ Interrupt->os, &Interrupt->fifoValid
++ ));
++
++ /* Start the interrupt handler thread. */
++ gcmkERR_BREAK(gckOS_StartThread(
++ Interrupt->os,
++ _MainInterruptHandler,
++ Interrupt,
++ &Interrupt->handler
++ ));
++#endif
++
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (Interrupt->fifoValid != gcvNULL)
++ {
++ gcmkCHECK_STATUS(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ Interrupt->fifoValid = gcvNULL;
++ }
++
++ /* Return the status. */
++ return status;
++}
++
++static gceSTATUS
++_StopInterruptHandler(
++ gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ do
++ {
++ /* Does the thread exist? */
++ if (Interrupt->handler == gcvNULL)
++ {
++ /* The semaphore must be NULL as well. */
++ gcmkASSERT(Interrupt->fifoValid == gcvNULL);
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* The semaphore must exist as well. */
++ gcmkASSERT(Interrupt->fifoValid != gcvNULL);
++
++ /* Set the termination request. */
++ Interrupt->terminate = gcvTRUE;
++
++ /* Unlock the thread. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Wait until the thread quits. */
++ gcmkERR_BREAK(gckOS_StopThread(
++ Interrupt->os,
++ Interrupt->handler
++ ));
++
++ /* Destroy the semaphore. */
++ gcmkERR_BREAK(gckOS_DestroySemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++
++ /* Reset handles. */
++ Interrupt->handler = gcvNULL;
++ Interrupt->fifoValid = gcvNULL;
++ }
++ while (gcvFALSE);
++
++ /* Return the status. */
++ return status;
++}
++
++
++/******************************************************************************\
++***************************** Interrupt Object API *****************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Construct
++**
++** Construct an interrupt object.
++**
++** INPUT:
++**
++** Kernel
++** Pointer to the gckVGKERNEL object.
++**
++** OUTPUT:
++**
++** Interrupt
++** Pointer to the new gckVGINTERRUPT object.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ )
++{
++ gceSTATUS status;
++ gckVGINTERRUPT interrupt = gcvNULL;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interrupt=0x%x", Kernel, Interrupt);
++
++ /* Verify argeuments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interrupt != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(struct _gckVGINTERRUPT),
++ (gctPOINTER *) &interrupt
++ ));
++
++ /* Reset the object data. */
++ gcmkVERIFY_OK(gckOS_ZeroMemory(
++ interrupt, gcmSIZEOF(struct _gckVGINTERRUPT)
++ ));
++
++ /* Initialize the object. */
++ interrupt->object.type = gcvOBJ_INTERRUPT;
++
++ /* Initialize the object pointers. */
++ interrupt->kernel = Kernel;
++ interrupt->os = Kernel->os;
++
++ /* Initialize the current FIFO position. */
++ interrupt->head = (gctUINT8)~0;
++ interrupt->tail = (gctUINT8)~0;
++
++ /* Start the thread. */
++ gcmkERR_BREAK(_StartInterruptHandler(interrupt));
++
++ /* Return interrupt object. */
++ *Interrupt = interrupt;
++
++ gcmkFOOTER_ARG("*Interrup=0x%x", *Interrupt);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (interrupt != gcvNULL)
++ {
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkVERIFY_OK(gckOS_Free(interrupt->os, interrupt));
++ }
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Destroy
++**
++** Destroy an interrupt object.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to the gckVGINTERRUPT object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ do
++ {
++ /* Stop the interrupt thread. */
++ gcmkERR_BREAK(_StopInterruptHandler(Interrupt));
++
++ /* Mark the object as unknown. */
++ Interrupt->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGINTERRUPT structure. */
++ gcmkERR_BREAK(gckOS_Free(Interrupt->os, Interrupt));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_DumpState
++**
++** Print the current state of the interrupt manager.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#if gcvDEBUG
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++ /* Print the header. */
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ "%s: INTERRUPT OBJECT STATUS\n",
++ __FUNCTION__
++ );
++
++ /* Print statistics. */
++#if gcmENABLE_INTERRUPT_STATISTICS
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of FIFO items accumulated at a single time: %d\n",
++ Interrupt->maxFifoItems
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Interrupt FIFO overflow happened times: %d\n",
++ Interrupt->fifoOverflow
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Maximum number of interrupts simultaneously generated: %d\n",
++ Interrupt->maxSimultaneous
++ );
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " Number of times when there were multiple interrupts generated: %d\n",
++ Interrupt->multipleCount
++ );
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " The current number of entries in the FIFO: %d\n",
++ Interrupt->fifoItems
++ );
++
++ /* Print the FIFO contents. */
++ if (Interrupt->fifoItems != 0)
++ {
++ gctUINT8 index;
++ gctUINT8 last;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " FIFO current contents:\n"
++ );
++
++ /* Get the current pointers. */
++ index = Interrupt->tail;
++ last = Interrupt->head;
++
++ while (index != last)
++ {
++ /* Advance to the next entry. */
++ index += 1;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_VERBOSE, gcvZONE_COMMAND,
++ " %d: 0x%08X\n",
++ index, Interrupt->fifo[index]
++ );
++ }
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enable
++**
++** Enable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Pointer to the variable that holds the interrupt number to be
++** registered in range 0..31.
++** If the value is less then 0, gckVGINTERRUPT_Enable will attempt
++** to find an unused interrupt. If such interrupt is found, the number
++** will be assigned to the variable if the functuion call succeedes.
++**
++** Handler
++** Pointer to the handler to register for the interrupt.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ )
++{
++ gceSTATUS status;
++ gctINT32 i;
++
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x Handler=0x%x", Interrupt, Id, Handler);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT(Id != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Handler != gcvNULL);
++
++ do
++ {
++ /* See if we need to allocate an ID. */
++ if (*Id < 0)
++ {
++ /* Find the first unused interrupt handler. */
++ for (i = 0; i < gcmCOUNTOF(Interrupt->handlers); ++i)
++ {
++ if (Interrupt->handlers[i] == gcvNULL)
++ {
++ break;
++ }
++ }
++
++ /* No unused innterrupts? */
++ if (i == gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ break;
++ }
++
++ /* Update the interrupt ID. */
++ *Id = i;
++ }
++
++ /* Make sure the ID is in range. */
++ else if (*Id >= gcmCOUNTOF(Interrupt->handlers))
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ /* Set interrupt handler. */
++ Interrupt->handlers[*Id] = Handler;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Disable
++**
++** Disable the specified interrupt.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** Id
++** Interrupt number to be disabled in range 0..31.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ )
++{
++ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x", Interrupt, Id);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++ gcmkVERIFY_ARGUMENT((Id >= 0) && (Id < gcmCOUNTOF(Interrupt->handlers)));
++
++ /* Reset interrupt handler. */
++ Interrupt->handlers[Id] = gcvNULL;
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckVGINTERRUPT_Enque
++**
++** Read the interrupt status register and put the value in the interrupt FIFO.
++**
++** INPUT:
++**
++** Interrupt
++** Pointer to a gckVGINTERRUPT object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++
++#ifndef __QNXNTO__
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ )
++#else
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt,
++ OUT gckOS *Os,
++ OUT gctSEMAPHORE *Semaphore
++ )
++#endif
++{
++ gceSTATUS status;
++ gctUINT32 triggered;
++
++ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT);
++
++#ifdef __QNXNTO__
++ *Os = gcvNULL;
++ *Semaphore = gcvNULL;
++#endif
++
++ do
++ {
++ /* Read interrupt status register. */
++ gcmkERR_BREAK(gckVGHARDWARE_ReadInterrupt(
++ Interrupt->kernel->hardware, &triggered
++ ));
++
++ /* Mask out TS overflow interrupt */
++ triggered &= 0xfffffffe;
++
++ /* No interrupts to process? */
++ if (triggered == 0)
++ {
++ status = gcvSTATUS_NOT_OUR_INTERRUPT;
++ break;
++ }
++
++ /* FIFO overflow? */
++ if (Interrupt->fifoItems == gcmCOUNTOF(Interrupt->fifo))
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ Interrupt->fifoOverflow += 1;
++#endif
++
++ /* OR the interrupt with the last value in the FIFO. */
++ Interrupt->fifo[Interrupt->head] |= triggered;
++
++ /* Success (kind of). */
++ status = gcvSTATUS_OK;
++ }
++ else
++ {
++ /* Advance to the next entry. */
++ Interrupt->head += 1;
++ Interrupt->fifoItems += 1;
++
++#if gcmENABLE_INTERRUPT_STATISTICS
++ if (Interrupt->fifoItems > Interrupt->maxFifoItems)
++ {
++ Interrupt->maxFifoItems = Interrupt->fifoItems;
++ }
++#endif
++
++ /* Set the new value. */
++ Interrupt->fifo[Interrupt->head] = triggered;
++
++#ifndef __QNXNTO__
++ /* Increment the FIFO semaphore. */
++ gcmkERR_BREAK(gckOS_IncrementSemaphore(
++ Interrupt->os, Interrupt->fifoValid
++ ));
++#else
++ *Os = Interrupt->os;
++ *Semaphore = Interrupt->fifoValid;
++#endif
++
++ /* Windows kills our threads prematurely when the application
++ exists. Verify here that the thread is still alive. */
++ status = gckOS_VerifyThread(Interrupt->os, Interrupt->handler);
++
++ /* Has the thread been prematurely terminated? */
++ if (status != gcvSTATUS_OK)
++ {
++ /* Process all accumulated interrupts. */
++ while (Interrupt->head != Interrupt->tail)
++ {
++#if gcmENABLE_INTERRUPT_STATISTICS
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt, gcvNULL);
++#else
++ /* Process the interrupt. */
++ _ProcessInterrupt(Interrupt);
++#endif
++ }
++
++ /* Set success. */
++ status = gcvSTATUS_OK;
++ }
++ }
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,2260 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++typedef enum _gceMMU_TYPE
++{
++ gcvMMU_USED = (0 << 4),
++ gcvMMU_SINGLE = (1 << 4),
++ gcvMMU_FREE = (2 << 4),
++}
++gceMMU_TYPE;
++
++#define gcmENTRY_TYPE(x) (x & 0xF0)
++
++#define gcdMMU_TABLE_DUMP 0
++
++#define gcdUSE_MMU_EXCEPTION 1
++
++/*
++ gcdMMU_CLEAR_VALUE
++
++ The clear value for the entry of the old MMU.
++*/
++#ifndef gcdMMU_CLEAR_VALUE
++# define gcdMMU_CLEAR_VALUE 0x00000ABC
++#endif
++
++#define gcdVERTEX_START (128 << 10)
++
++typedef struct _gcsMMU_STLB *gcsMMU_STLB_PTR;
++
++typedef struct _gcsMMU_STLB
++{
++ gctPHYS_ADDR physical;
++ gctUINT32_PTR logical;
++ gctSIZE_T size;
++ gctUINT32 physBase;
++ gctSIZE_T pageCount;
++ gctUINT32 mtlbIndex;
++ gctUINT32 mtlbEntryNum;
++ gcsMMU_STLB_PTR next;
++} gcsMMU_STLB;
++
++#if gcdSHARED_PAGETABLE
++typedef struct _gcsSharedPageTable * gcsSharedPageTable_PTR;
++typedef struct _gcsSharedPageTable
++{
++ /* Shared gckMMU object. */
++ gckMMU mmu;
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsSharedPageTable;
++
++static gcsSharedPageTable_PTR sharedPageTable = gcvNULL;
++#endif
++
++#if gcdMIRROR_PAGETABLE
++typedef struct _gcsMirrorPageTable * gcsMirrorPageTable_PTR;
++typedef struct _gcsMirrorPageTable
++{
++ /* gckMMU objects. */
++ gckMMU mmus[gcdMAX_GPU_COUNT];
++
++ /* Hardwares which use this shared pagetable. */
++ gckHARDWARE hardwares[gcdMAX_GPU_COUNT];
++
++ /* Number of cores use this shared pagetable. */
++ gctUINT32 reference;
++}
++gcsMirrorPageTable;
++
++static gcsMirrorPageTable_PTR mirrorPageTable = gcvNULL;
++static gctPOINTER mirrorPageTableMutex = gcvNULL;
++#endif
++
++typedef struct _gcsDynamicSpaceNode * gcsDynamicSpaceNode_PTR;
++typedef struct _gcsDynamicSpaceNode
++{
++ gctUINT32 start;
++ gctINT32 entries;
++}
++gcsDynamicSpaceNode;
++
++static void
++_WritePageEntry(
++ IN gctUINT32_PTR PageEntry,
++ IN gctUINT32 EntryValue
++ )
++{
++ static gctUINT16 data = 0xff00;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ *PageEntry = gcmSWAB32(EntryValue);
++ }
++ else
++ {
++ *PageEntry = EntryValue;
++ }
++}
++
++static gctUINT32
++_ReadPageEntry(
++ IN gctUINT32_PTR PageEntry
++ )
++{
++ static gctUINT16 data = 0xff00;
++ gctUINT32 entryValue;
++
++ if (*(gctUINT8 *)&data == 0xff)
++ {
++ entryValue = *PageEntry;
++ return gcmSWAB32(entryValue);
++ }
++ else
++ {
++ return *PageEntry;
++ }
++}
++
++static gceSTATUS
++_FillPageTable(
++ IN gctUINT32_PTR PageTable,
++ IN gctUINT32 PageCount,
++ IN gctUINT32 EntryValue
++)
++{
++ gctUINT i;
++
++ for (i = 0; i < PageCount; i++)
++ {
++ _WritePageEntry(PageTable + i, EntryValue);
++ }
++
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_Link(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Next
++ )
++{
++ if (Index >= Mmu->pageTableEntries)
++ {
++ /* Just move heap pointer. */
++ Mmu->heapList = Next;
++ }
++ else
++ {
++ /* Address page table. */
++ gctUINT32_PTR map = Mmu->mapLogical;
++
++ /* Dispatch on node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[Index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Set single index. */
++ _WritePageEntry(&map[Index], (Next << 8) | gcvMMU_SINGLE);
++ break;
++
++ case gcvMMU_FREE:
++ /* Set index. */
++ _WritePageEntry(&map[Index + 1], Next);
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", Index);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++static gceSTATUS
++_AddFree(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 Node,
++ IN gctUINT32 Count
++ )
++{
++ gctUINT32_PTR map = Mmu->mapLogical;
++
++ if (Count == 1)
++ {
++ /* Initialize a single page node. */
++ _WritePageEntry(map + Node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++ }
++ else
++ {
++ /* Initialize the node. */
++ _WritePageEntry(map + Node + 0, (Count << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + Node + 1, ~0U);
++ }
++
++ /* Append the node. */
++ return _Link(Mmu, Index, Node);
++}
++
++static gceSTATUS
++_Collect(
++ IN gckMMU Mmu
++ )
++{
++ gctUINT32_PTR map = Mmu->mapLogical;
++ gceSTATUS status;
++ gctUINT32 i, previous, start = 0, count = 0;
++
++ previous = Mmu->heapList = ~0U;
++ Mmu->freeNodes = gcvFALSE;
++
++ /* Walk the entire page table. */
++ for (i = 0; i < Mmu->pageTableEntries; ++i)
++ {
++ /* Dispatch based on type of page. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i])))
++ {
++ case gcvMMU_USED:
++ /* Used page, so close any open node. */
++ if (count > 0)
++ {
++ /* Add the node. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++
++ /* Reset the node. */
++ previous = start;
++ count = 0;
++ }
++ break;
++
++ case gcvMMU_SINGLE:
++ /* Single free node. */
++ if (count++ == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* A free node. */
++ if (count == 0)
++ {
++ /* Start a new node. */
++ start = i;
++ }
++
++ /* Advance the count. */
++ count += _ReadPageEntry(&map[i]) >> 8;
++
++ /* Advance the index into the page table. */
++ i += (_ReadPageEntry(&map[i]) >> 8) - 1;
++ break;
++
++ default:
++ gcmkFATAL("MMU page table correcupted at index %u!", i);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++ }
++
++ /* See if we have an open node left. */
++ if (count > 0)
++ {
++ /* Add the node to the list. */
++ gcmkONERROR(_AddFree(Mmu, previous, start, count));
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_MMU,
++ "Performed a garbage collection of the MMU heap.");
++
++ /* Success. */
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the staus. */
++ return status;
++}
++
++static gctUINT32
++_SetPage(gctUINT32 PageAddress)
++{
++ return PageAddress
++ /* writable */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gctUINT32
++_AddressToIndex(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ )
++{
++ gctUINT32 mtlbOffset = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 stlbOffset = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++
++ return (mtlbOffset - Mmu->dynamicMappingStart) * gcdMMU_STLB_4K_ENTRY_NUM + stlbOffset;
++}
++
++gctUINT32
++_MtlbOffset(
++ gctUINT32 Address
++ )
++{
++ return (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++}
++
++gctUINT32
++_StlbOffset(
++ gctUINT32 Address
++ )
++{
++ return (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++}
++
++static gceSTATUS
++_AllocateStlb(
++ IN gckOS Os,
++ OUT gcsMMU_STLB_PTR *Stlb
++ )
++{
++ gceSTATUS status;
++ gcsMMU_STLB_PTR stlb;
++ gctPOINTER pointer;
++
++ /* Allocate slave TLB record. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsMMU_STLB), &pointer));
++ stlb = pointer;
++
++ stlb->size = gcdMMU_STLB_4K_SIZE;
++
++ /* Allocate slave TLB entries. */
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Os,
++ gcvFALSE,
++ &stlb->size,
++ &stlb->physical,
++ (gctPOINTER)&stlb->logical
++ ));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(Os, stlb->logical, &stlb->physBase));
++
++#if gcdUSE_MMU_EXCEPTION
++ _FillPageTable(stlb->logical, stlb->size / 4, gcdMMU_STLB_EXCEPTION);
++#else
++ gckOS_ZeroMemory(stlb->logical, stlb->size);
++#endif
++
++ *Stlb = stlb;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++gceSTATUS
++_SetupProcessAddressSpace(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gctINT numEntries = 0;
++ gctUINT32_PTR map;
++
++ numEntries = gcdPROCESS_ADDRESS_SPACE_SIZE
++ /* Address space mapped by one MTLB entry. */
++ / (1 << gcdMMU_MTLB_SHIFT);
++
++ Mmu->dynamicMappingStart = 0;
++
++ Mmu->pageTableSize = numEntries * 4096;
++
++ Mmu->pageTableEntries = Mmu->pageTableSize / gcmSIZEOF(gctUINT32);
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ Mmu->pageTableSize,
++ (void **)&Mmu->mapLogical));
++
++ /* Initilization. */
++ map = Mmu->mapLogical;
++ _WritePageEntry(map, (Mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + 1, ~0U);
++ Mmu->heapList = 0;
++ Mmu->freeNodes = gcvFALSE;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++#else
++static gceSTATUS
++_FillFlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 PhysBase,
++ OUT gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gcsMMU_STLB_PTR head = gcvNULL, pre = gcvNULL;
++ gctUINT32 start = PhysBase & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 end = (PhysBase + Size - 1) & (~gcdMMU_PAGE_64K_MASK);
++ gctUINT32 mStart = start >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 mEnd = end >> gcdMMU_MTLB_SHIFT;
++ gctUINT32 sStart = (start & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++ gctUINT32 sEnd = (end & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE);
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ while (mStart <= mEnd)
++ {
++ gcmkASSERT(mStart < gcdMMU_MTLB_ENTRY_NUM);
++ if (*(Mmu->mtlbLogical + mStart) == 0)
++ {
++ gcsMMU_STLB_PTR stlb;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 last = (mStart == mEnd) ? sEnd : (gcdMMU_STLB_64K_ENTRY_NUM - 1);
++ gctUINT32 mtlbEntry;
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os, sizeof(struct _gcsMMU_STLB), &pointer));
++ stlb = pointer;
++
++ stlb->mtlbEntryNum = 0;
++ stlb->next = gcvNULL;
++ stlb->physical = gcvNULL;
++ stlb->logical = gcvNULL;
++ stlb->size = gcdMMU_STLB_64K_SIZE;
++ stlb->pageCount = 0;
++
++ if (pre == gcvNULL)
++ {
++ pre = head = stlb;
++ }
++ else
++ {
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = stlb;
++ pre = stlb;
++ }
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &stlb->size,
++ &stlb->physical,
++ (gctPOINTER)&stlb->logical));
++
++ gcmkONERROR(gckOS_ZeroMemory(stlb->logical, stlb->size));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ Mmu->os,
++ stlb->logical,
++ &stlb->physBase));
++
++ if (stlb->physBase & (gcdMMU_STLB_64K_SIZE - 1))
++ {
++ gcmkONERROR(gcvSTATUS_NOT_ALIGNED);
++ }
++
++ mtlbEntry = stlb->physBase
++ /* 64KB page size */
++ | (1 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++
++ if (ace)
++ {
++ mtlbEntry = mtlbEntry
++ /* Secure */
++ | (1 << 4);
++ }
++
++ _WritePageEntry(Mmu->mtlbLogical + mStart, mtlbEntry);
++
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ mStart,
++ _ReadPageEntry(Mmu->mtlbLogical + mStart));
++#endif
++
++ stlb->mtlbIndex = mStart;
++ stlb->mtlbEntryNum = 1;
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): STLB: logical:%08x -> physical:%08x\n",
++ __FUNCTION__, __LINE__,
++ stlb->logical,
++ stlb->physBase);
++#endif
++
++ while (sStart <= last)
++ {
++ gcmkASSERT(!(start & gcdMMU_PAGE_64K_MASK));
++ _WritePageEntry(stlb->logical + sStart, _SetPage(start));
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert STLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ sStart,
++ _ReadPageEntry(stlb->logical + sStart));
++#endif
++ /* next page. */
++ start += gcdMMU_PAGE_64K_SIZE;
++ sStart++;
++ stlb->pageCount++;
++ }
++
++ sStart = 0;
++ ++mStart;
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++ }
++
++ /* Insert the stlb into staticSTLB. */
++ if (Mmu->staticSTLB == gcvNULL)
++ {
++ Mmu->staticSTLB = head;
++ }
++ else
++ {
++ gcmkASSERT(pre == gcvNULL);
++ gcmkASSERT(pre->next == gcvNULL);
++ pre->next = Mmu->staticSTLB;
++ Mmu->staticSTLB = head;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Roll back. */
++ while (head != gcvNULL)
++ {
++ pre = head;
++ head = head->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_FindDynamicSpace(
++ IN gckMMU Mmu,
++ OUT gcsDynamicSpaceNode_PTR *Array,
++ OUT gctINT * Size
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gctPOINTER pointer = gcvNULL;
++ gcsDynamicSpaceNode_PTR array = gcvNULL;
++ gctINT size = 0;
++ gctINT i = 0, nodeStart = -1, nodeEntries = 0;
++
++ /* Allocate memory for the array. */
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ gcmSIZEOF(*array) * (gcdMMU_MTLB_ENTRY_NUM / 2),
++ &pointer));
++
++ array = (gcsDynamicSpaceNode_PTR)pointer;
++
++ /* Loop all the entries. */
++ while (i < gcdMMU_MTLB_ENTRY_NUM)
++ {
++ if (!Mmu->mtlbLogical[i])
++ {
++ if (nodeStart < 0)
++ {
++ /* This is the first entry of the dynamic space. */
++ nodeStart = i;
++ nodeEntries = 1;
++ }
++ else
++ {
++ /* Other entries of the dynamic space. */
++ nodeEntries++;
++ }
++ }
++ else if (nodeStart >= 0)
++ {
++ /* Save the previous node. */
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++
++ /* Reset the start. */
++ nodeStart = -1;
++ nodeEntries = 0;
++ }
++
++ i++;
++ }
++
++ /* Save the previous node. */
++ if (nodeStart >= 0)
++ {
++ array[size].start = nodeStart;
++ array[size].entries = nodeEntries;
++ size++;
++ }
++
++#if gcdMMU_TABLE_DUMP
++ for (i = 0; i < size; i++)
++ {
++ gckOS_Print("%s(%d): [%d]: start=%d, entries=%d.\n",
++ __FUNCTION__, __LINE__,
++ i,
++ array[i].start,
++ array[i].entries);
++ }
++#endif
++
++ *Array = array;
++ *Size = size;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (pointer != gcvNULL)
++ {
++ gckOS_Free(Mmu->os, pointer);
++ }
++
++ return status;
++}
++
++static gceSTATUS
++_SetupDynamicSpace(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gcsDynamicSpaceNode_PTR nodeArray = gcvNULL;
++ gctINT i, nodeArraySize = 0;
++ gctUINT32 physical;
++ gctINT numEntries = 0;
++ gctUINT32_PTR map;
++ gctBOOL acquired = gcvFALSE;
++ gctUINT32 mtlbEntry;
++ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE);
++
++ /* Find all the dynamic address space. */
++ gcmkONERROR(_FindDynamicSpace(Mmu, &nodeArray, &nodeArraySize));
++
++ /* TODO: We only use the largest one for now. */
++ for (i = 0; i < nodeArraySize; i++)
++ {
++ if (nodeArray[i].entries > numEntries)
++ {
++ Mmu->dynamicMappingStart = nodeArray[i].start;
++ numEntries = nodeArray[i].entries;
++ }
++ }
++
++ gckOS_Free(Mmu->os, (gctPOINTER)nodeArray);
++
++ Mmu->pageTableSize = numEntries * 4096;
++
++ gcmkSAFECASTSIZET(Mmu->pageTableEntries, Mmu->pageTableSize / gcmSIZEOF(gctUINT32));
++
++ gcmkONERROR(gckOS_Allocate(Mmu->os,
++ Mmu->pageTableSize,
++ (void **)&Mmu->mapLogical));
++
++ /* Construct Slave TLB. */
++ gcmkONERROR(gckOS_AllocateContiguous(Mmu->os,
++ gcvFALSE,
++ &Mmu->pageTableSize,
++ &Mmu->pageTablePhysical,
++ (gctPOINTER)&Mmu->pageTableLogical));
++
++#if gcdUSE_MMU_EXCEPTION
++ gcmkONERROR(_FillPageTable(Mmu->pageTableLogical,
++ Mmu->pageTableEntries,
++ /* Enable exception */
++ 1 << 1));
++#else
++ /* Invalidate all entries. */
++ gcmkONERROR(gckOS_ZeroMemory(Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++#endif
++
++ /* Initilization. */
++ map = Mmu->mapLogical;
++ _WritePageEntry(map, (Mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + 1, ~0U);
++ Mmu->heapList = 0;
++ Mmu->freeNodes = gcvFALSE;
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(Mmu->os,
++ Mmu->pageTableLogical,
++ &physical));
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Map to Master TLB. */
++ for (i = (gctINT)Mmu->dynamicMappingStart;
++ i < (gctINT)Mmu->dynamicMappingStart + numEntries;
++ i++)
++ {
++ mtlbEntry = physical
++ /* 4KB page size */
++ | (0 << 2)
++ /* Ignore exception */
++ | (0 << 1)
++ /* Present */
++ | (1 << 0);
++
++ if (ace)
++ {
++ mtlbEntry = mtlbEntry
++ /* Secure */
++ | (1 << 4);
++ }
++
++ _WritePageEntry(Mmu->mtlbLogical + i, mtlbEntry);
++
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n",
++ __FUNCTION__, __LINE__,
++ i,
++ _ReadPageEntry(Mmu->mtlbLogical + i));
++#endif
++ physical += gcdMMU_STLB_4K_SIZE;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (Mmu->mapLogical)
++ {
++ gcmkVERIFY_OK(
++ gckOS_Free(Mmu->os, (gctPOINTER) Mmu->mapLogical));
++
++
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** _Construct
++**
++** Construct a new gckMMU object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckMMU * Mmu
++** Pointer to a variable that receives the gckMMU object pointer.
++*/
++gceSTATUS
++_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++ gckOS os;
++ gckHARDWARE hardware;
++ gceSTATUS status;
++ gckMMU mmu = gcvNULL;
++ gctUINT32_PTR map;
++ gctPOINTER pointer = gcvNULL;
++#if gcdPROCESS_ADDRESS_SPACE
++ gctUINT32 i;
++ gctUINT32 physical;
++#endif
++ gctUINT32 physBase;
++ gctUINT32 physSize;
++ gctUINT32 gpuAddress;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=%lu", Kernel, MmuSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckMMU object. */
++ gcmkONERROR(gckOS_Allocate(os, sizeof(struct _gckMMU), &pointer));
++
++ mmu = pointer;
++
++ /* Initialize the gckMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++ mmu->pageTableMutex = gcvNULL;
++ mmu->pageTableLogical = gcvNULL;
++ mmu->mtlbLogical = gcvNULL;
++ mmu->staticSTLB = gcvNULL;
++ mmu->enabled = gcvFALSE;
++ mmu->mapLogical = gcvNULL;
++
++ /* Create the page table mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &mmu->pageTableMutex));
++
++ if (hardware->mmuVersion == 0)
++ {
++ mmu->pageTableSize = MmuSize;
++
++ /* Construct address space management table. */
++ gcmkONERROR(gckOS_Allocate(mmu->os,
++ mmu->pageTableSize,
++ &pointer));
++
++ mmu->mapLogical = pointer;
++
++ /* Construct page table read by GPU. */
++ gcmkONERROR(gckOS_AllocateContiguous(mmu->os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ (gctPOINTER)&mmu->pageTableLogical));
++
++
++ /* Compute number of entries in page table. */
++ gcmkSAFECASTSIZET(mmu->pageTableEntries, mmu->pageTableSize / sizeof(gctUINT32));
++
++ /* Mark all pages as free. */
++ map = mmu->mapLogical;
++
++#if gcdMMU_CLEAR_VALUE
++ _FillPageTable(mmu->pageTableLogical, mmu->pageTableEntries, gcdMMU_CLEAR_VALUE);
++#endif
++
++ _WritePageEntry(map, (mmu->pageTableEntries << 8) | gcvMMU_FREE);
++ _WritePageEntry(map + 1, ~0U);
++ mmu->heapList = 0;
++ mmu->freeNodes = gcvFALSE;
++ }
++ else
++ {
++ /* Allocate the 4K mode MTLB table. */
++ mmu->mtlbSize = gcdMMU_MTLB_SIZE + 64;
++
++ gcmkONERROR(
++ gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->mtlbSize,
++ &mmu->mtlbPhysical,
++ &pointer));
++
++ mmu->mtlbLogical = pointer;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ _FillPageTable(pointer, mmu->mtlbSize / 4, gcdMMU_MTLB_EXCEPTION);
++
++ /* Allocate a array to store stlbs. */
++ gcmkONERROR(gckOS_Allocate(os, mmu->mtlbSize, &mmu->stlbs));
++
++ gckOS_ZeroMemory(mmu->stlbs, mmu->mtlbSize);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ gcmkONERROR(gckOS_AtomConstruct(os, &mmu->pageTableDirty[i]));
++ }
++
++ _SetupProcessAddressSpace(mmu);
++
++ /* Map kernel command buffer in MMU. */
++ for (i = 0; i < gcdCOMMAND_QUEUES; i++)
++ {
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ mmu->os,
++ Kernel->command->queues[i].logical,
++ &physical
++ ));
++
++ gcmkONERROR(gckMMU_FlatMapping(mmu, physical));
++ }
++#else
++ /* Invalid all the entries. */
++ gcmkONERROR(
++ gckOS_ZeroMemory(pointer, mmu->mtlbSize));
++
++ gcmkONERROR(
++ gckOS_QueryOption(mmu->os, "physBase", &physBase));
++
++ gcmkONERROR(
++ gckOS_QueryOption(mmu->os, "physSize", &physSize));
++
++ gcmkONERROR(
++ gckOS_CPUPhysicalToGPUPhysical(mmu->os, physBase, &gpuAddress));
++
++ /* Setup [physBase - physSize) flat mapping. */
++ gcmkONERROR(_FillFlatMapping(
++ mmu,
++ gpuAddress,
++ physSize
++ ));
++
++ gcmkONERROR(_SetupDynamicSpace(mmu));
++#endif
++ }
++
++ /* Return the gckMMU object pointer. */
++ *Mmu = mmu;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Mmu=0x%x", *Mmu);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (mmu != gcvNULL)
++ {
++ if (mmu->mapLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_Free(os, (gctPOINTER) mmu->mapLogical));
++
++
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->pageTablePhysical,
++ (gctPOINTER) mmu->pageTableLogical,
++ mmu->pageTableSize));
++ }
++
++ if (mmu->mtlbLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(os,
++ mmu->mtlbPhysical,
++ (gctPOINTER) mmu->mtlbLogical,
++ mmu->mtlbSize));
++ }
++
++ if (mmu->pageTableMutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, mmu->pageTableMutex));
++ }
++
++ /* Mark the gckMMU object as unknown. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the allocates memory. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, mmu));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** _Destroy
++**
++** Destroy a gckMMU object.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#if gcdPROCESS_ADDRESS_SPACE
++ gctUINT32 i;
++#endif
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ while (Mmu->staticSTLB != gcvNULL)
++ {
++ gcsMMU_STLB_PTR pre = Mmu->staticSTLB;
++ Mmu->staticSTLB = pre->next;
++
++ if (pre->physical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ pre->physical,
++ pre->logical,
++ pre->size));
++ }
++
++ if (pre->mtlbEntryNum != 0)
++ {
++ gcmkASSERT(pre->mtlbEntryNum == 1);
++ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0);
++#if gcdMMU_TABLE_DUMP
++ gckOS_Print("%s(%d): clean MTLB[%d]\n",
++ __FUNCTION__, __LINE__,
++ pre->mtlbIndex);
++#endif
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre));
++ }
++
++ if (Mmu->hardware->mmuVersion != 0)
++ {
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->mtlbPhysical,
++ (gctPOINTER) Mmu->mtlbLogical,
++ Mmu->mtlbSize));
++ }
++
++ /* Free address space management table. */
++ if (Mmu->mapLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_Free(Mmu->os, (gctPOINTER) Mmu->mapLogical));
++ }
++
++ if (Mmu->pageTableLogical != gcvNULL)
++ {
++ /* Free page table. */
++ gcmkVERIFY_OK(
++ gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ (gctPOINTER) Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++ }
++
++ /* Delete the page table mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->pageTableMutex));
++
++#if gcdPROCESS_ADDRESS_SPACE
++ for (i = 0; i < Mmu->mtlbSize / 4; i++)
++ {
++ struct _gcsMMU_STLB *stlb = ((struct _gcsMMU_STLB **)Mmu->stlbs)[i];
++
++ if (stlb)
++ {
++ gcmkVERIFY_OK(gckOS_FreeContiguous(
++ Mmu->os,
++ stlb->physical,
++ stlb->logical,
++ stlb->size));
++
++ gcmkOS_SAFE_FREE(Mmu->os, stlb);
++ }
++ }
++
++ gcmkOS_SAFE_FREE(Mmu->os, Mmu->stlbs);
++#endif
++
++ /* Mark the gckMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckMMU object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, Mmu));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** _AdjstIndex
++**
++** Adjust the index from which we search for a usable node to make sure
++** index allocated is greater than Start.
++*/
++gceSTATUS
++_AdjustIndex(
++ IN gckMMU Mmu,
++ IN gctUINT32 Index,
++ IN gctUINT32 PageCount,
++ IN gctUINT32 Start,
++ OUT gctUINT32 * IndexAdjusted
++ )
++{
++ gceSTATUS status;
++ gctUINT32 index = Index;
++ gctUINT32_PTR map = Mmu->mapLogical;
++
++ gcmkHEADER();
++
++ for (; index < Mmu->pageTableEntries;)
++ {
++ gctUINT32 result = 0;
++ gctUINT32 nodeSize = 0;
++
++ if (index >= Start)
++ {
++ break;
++ }
++
++ switch (gcmENTRY_TYPE(map[index]))
++ {
++ case gcvMMU_SINGLE:
++ nodeSize = 1;
++ break;
++
++ case gcvMMU_FREE:
++ nodeSize = map[index] >> 8;
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ if (nodeSize > PageCount)
++ {
++ result = index + (nodeSize - PageCount);
++
++ if (result >= Start)
++ {
++ break;
++ }
++ }
++
++ switch (gcmENTRY_TYPE(map[index]))
++ {
++ case gcvMMU_SINGLE:
++ index = map[index] >> 8;
++ break;
++
++ case gcvMMU_FREE:
++ index = map[index + 1];
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ *IndexAdjusted = index;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (sharedPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsSharedPageTable),
++ &pointer));
++ sharedPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(sharedPageTable,
++ sizeof(struct _gcsSharedPageTable)));
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, &sharedPageTable->mmu));
++ }
++
++ *Mmu = sharedPageTable->mmu;
++
++ sharedPageTable->hardwares[sharedPageTable->reference] = Kernel->hardware;
++
++ sharedPageTable->reference++;
++
++ gcmkFOOTER_ARG("sharedPageTable->reference=%lu", sharedPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (sharedPageTable)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(gckMMU_Destroy(sharedPageTable->mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, sharedPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#elif gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pointer;
++
++ gcmkHEADER_ARG("Kernel=0x%08x", Kernel);
++
++ if (mirrorPageTable == gcvNULL)
++ {
++ gcmkONERROR(
++ gckOS_Allocate(Kernel->os,
++ sizeof(struct _gcsMirrorPageTable),
++ &pointer));
++ mirrorPageTable = pointer;
++
++ gcmkONERROR(
++ gckOS_ZeroMemory(mirrorPageTable,
++ sizeof(struct _gcsMirrorPageTable)));
++
++ gcmkONERROR(
++ gckOS_CreateMutex(Kernel->os, &mirrorPageTableMutex));
++ }
++
++ gcmkONERROR(_Construct(Kernel, MmuSize, Mmu));
++
++ mirrorPageTable->mmus[mirrorPageTable->reference] = *Mmu;
++
++ mirrorPageTable->hardwares[mirrorPageTable->reference] = Kernel->hardware;
++
++ mirrorPageTable->reference++;
++
++ gcmkFOOTER_ARG("mirrorPageTable->reference=%lu", mirrorPageTable->reference);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mirrorPageTable && mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, mirrorPageTable));
++ }
++
++ gcmkFOOTER();
++ return status;
++#else
++ return _Construct(Kernel, MmuSize, Mmu);
++#endif
++}
++
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ )
++{
++#if gcdSHARED_PAGETABLE
++ gckOS os = Mmu->os;
++
++ sharedPageTable->reference--;
++
++ if (sharedPageTable->reference == 0)
++ {
++ if (sharedPageTable->mmu)
++ {
++ gcmkVERIFY_OK(_Destroy(Mmu));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, sharedPageTable));
++ }
++
++ return gcvSTATUS_OK;
++#elif gcdMIRROR_PAGETABLE
++ mirrorPageTable->reference--;
++
++ if (mirrorPageTable->reference == 0)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTable));
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTableMutex));
++ }
++
++ return _Destroy(Mmu);
++#else
++ return _Destroy(Mmu);
++#endif
++}
++
++/*******************************************************************************
++**
++** gckMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS
++_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctBOOL mutex = gcvFALSE;
++ gctUINT32 index = 0, previous = ~0U, left;
++ gctUINT32_PTR map;
++ gctBOOL gotIt;
++ gctUINT32 address;
++ gctUINT32 pageCount;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=%lu", Mmu, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ if (PageCount > Mmu->pageTableEntries)
++ {
++ /* Not enough pages avaiable. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ gcmkSAFECASTSIZET(pageCount, PageCount);
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ mutex = gcvTRUE;
++
++ /* Cast pointer to page table. */
++ for (map = Mmu->mapLogical, gotIt = gcvFALSE; !gotIt;)
++ {
++ index = Mmu->heapList;
++
++ if ((Mmu->hardware->mmuVersion == 0) && (Type == gcvSURF_VERTEX))
++ {
++ gcmkONERROR(_AdjustIndex(
++ Mmu,
++ index,
++ pageCount,
++ gcdVERTEX_START / gcmSIZEOF(gctUINT32),
++ &index
++ ));
++ }
++
++ /* Walk the heap list. */
++ for (; !gotIt && (index < Mmu->pageTableEntries);)
++ {
++ /* Check the node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Single odes are valid if we only need 1 page. */
++ if (pageCount == 1)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&map[index]) >> 8;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ /* Test if the node has enough space. */
++ if (pageCount <= (_ReadPageEntry(&map[index]) >> 8))
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ /* Move to next node. */
++ previous = index;
++ index = _ReadPageEntry(&map[index + 1]);
++ }
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ /* Test if we are out of memory. */
++ if (index >= Mmu->pageTableEntries)
++ {
++ if (Mmu->freeNodes)
++ {
++ /* Time to move out the trash! */
++ gcmkONERROR(_Collect(Mmu));
++ }
++ else
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ }
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Unlink single node from free list. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&map[index]) >> 8));
++ break;
++
++ case gcvMMU_FREE:
++ /* Check how many pages will be left. */
++ left = (_ReadPageEntry(&map[index]) >> 8) - pageCount;
++ switch (left)
++ {
++ case 0:
++ /* The entire node is consumed, just unlink it. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&map[index + 1])));
++ break;
++
++ case 1:
++ /* One page will remain. Convert the node to a single node and
++ ** advance the index. */
++ _WritePageEntry(&map[index], (_ReadPageEntry(&map[index + 1]) << 8) | gcvMMU_SINGLE);
++ index ++;
++ break;
++
++ default:
++ /* Enough pages remain for a new node. However, we will just adjust
++ ** the size of the current node and advance the index. */
++ _WritePageEntry(&map[index], (left << 8) | gcvMMU_FREE);
++ index += left;
++ break;
++ }
++ break;
++ }
++
++ /* Mark node as used. */
++ gcmkONERROR(_FillPageTable(&map[index], pageCount, gcvMMU_USED));
++
++ /* Return pointer to page table. */
++ *PageTable = &Mmu->pageTableLogical[index];
++
++ /* Build virtual address. */
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(
++ gckHARDWARE_BuildVirtualAddress(Mmu->hardware, index, 0, &address));
++ }
++ else
++ {
++ gctUINT32 masterOffset = index / gcdMMU_STLB_4K_ENTRY_NUM
++ + Mmu->dynamicMappingStart;
++ gctUINT32 slaveOffset = index % gcdMMU_STLB_4K_ENTRY_NUM;
++
++ address = (masterOffset << gcdMMU_MTLB_SHIFT)
++ | (slaveOffset << gcdMMU_STLB_4K_SHIFT);
++ }
++
++ if (Address != gcvNULL)
++ {
++ *Address = address;
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageTable=0x%x *Address=%08x",
++ *PageTable, gcmOPT_VALUE(Address));
++ return gcvSTATUS_OK;
++
++OnError:
++
++ if (mutex)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckMMU Mmu
++** Pointer to an gckMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32_PTR node;
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctUINT32 pageCount;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=%lu",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ gcmkSAFECASTSIZET(pageCount, PageCount);
++
++ /* Get the node by index. */
++ node = Mmu->mapLogical + ((gctUINT32_PTR)PageTable - Mmu->pageTableLogical);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++#if gcdMMU_CLEAR_VALUE
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ _FillPageTable(PageTable, pageCount, gcdMMU_CLEAR_VALUE);
++ }
++#endif
++
++ if (PageCount == 1)
++ {
++ /* Single page node. */
++ _WritePageEntry(node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ _WritePageEntry(PageTable, (1 << 1));
++#endif
++ }
++ else
++ {
++ /* Mark the node as free. */
++ _WritePageEntry(node, (pageCount << 8) | gcvMMU_FREE);
++ _WritePageEntry(node + 1, ~0U);
++
++#if gcdUSE_MMU_EXCEPTION
++ /* Enable exception */
++ gcmkVERIFY_OK(_FillPageTable(PageTable, pageCount, 1 << 1));
++#endif
++ }
++
++ /* We have free nodes. */
++ Mmu->freeNodes = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ return gckMMU_AllocatePagesEx(
++ Mmu, PageCount, gcvSURF_TYPE_UNKNOWN, PageTable, Address);
++}
++
++gceSTATUS
++gckMMU_AllocatePagesEx(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gceSTATUS status;
++ gctPOINTER pageTable;
++ gctUINT32 address;
++ gctINT i;
++ gckMMU mmu;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL allocated = gcvFALSE;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++ acquired = gcvTRUE;
++
++ /* Allocate page table for current MMU. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ if (Mmu == mirrorPageTable->mmus[i])
++ {
++ gcmkONERROR(_AllocatePages(Mmu, PageCount, Type, PageTable, Address));
++ allocated = gcvTRUE;
++ }
++ }
++
++ /* Allocate page table for other MMUs. */
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (Mmu != mmu)
++ {
++ gcmkONERROR(_AllocatePages(mmu, PageCount, Type, &pageTable, &address));
++ gcmkASSERT(address == *Address);
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ acquired = gcvFALSE;
++
++ return gcvSTATUS_OK;
++OnError:
++
++ if (allocated)
++ {
++ /* Page tables for multiple GPU always keep the same. So it is impossible
++ * the fist one allocates successfully but others fail.
++ */
++ gcmkASSERT(0);
++ }
++
++ if (acquired)
++ {
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++ }
++
++ return status;
++#else
++ return _AllocatePages(Mmu, PageCount, Type, PageTable, Address);
++#endif
++}
++
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctINT i;
++ gctUINT32 offset;
++ gckMMU mmu;
++
++ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE);
++
++ gcmkVERIFY_OK(_FreePages(Mmu, PageTable, PageCount));
++
++ offset = (gctUINT32)PageTable - (gctUINT32)Mmu->pageTableLogical;
++
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ gcmkVERIFY_OK(_FreePages(mmu, mmu->pageTableLogical + offset/4, PageCount));
++ }
++ }
++
++ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex);
++
++ return gcvSTATUS_OK;
++#else
++ return _FreePages(Mmu, PageTable, PageCount);
++#endif
++}
++
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++#if gcdMIRROR_PAGETABLE
++ gctUINT32_PTR pageEntry;
++ gctINT i;
++ gckMMU mmu;
++ gctUINT32 offset = (gctUINT32)PageEntry - (gctUINT32)Mmu->pageTableLogical;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ if (Mmu->hardware->mmuVersion == 0)
++ {
++ _WritePageEntry(PageEntry, PageAddress);
++ }
++ else
++ {
++ _WritePageEntry(PageEntry, _SetPage(PageAddress));
++ }
++
++#if gcdMIRROR_PAGETABLE
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ mmu = mirrorPageTable->mmus[i];
++
++ if (mmu != Mmu)
++ {
++ pageEntry = mmu->pageTableLogical + offset / 4;
++
++ if (mmu->hardware->mmuVersion == 0)
++ {
++ _WritePageEntry(pageEntry, PageAddress);
++ }
++ else
++ {
++ _WritePageEntry(pageEntry, _SetPage(PageAddress));
++ }
++ }
++
++ }
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckMMU_GetPageEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctUINT32_PTR *PageTable
++ )
++{
++ gceSTATUS status;
++ struct _gcsMMU_STLB *stlb;
++ struct _gcsMMU_STLB **stlbs = Mmu->stlbs;
++ gctUINT32 offset = _MtlbOffset(Address);
++ gctUINT32 mtlbEntry;
++ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE);
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT((Address & 0xFFF) == 0);
++
++ stlb = stlbs[offset];
++
++ if (stlb == gcvNULL)
++ {
++ gcmkONERROR(_AllocateStlb(Mmu->os, &stlb));
++
++ mtlbEntry = stlb->physBase
++ | gcdMMU_MTLB_4K_PAGE
++ | gcdMMU_MTLB_PRESENT
++ ;
++
++ if (ace)
++ {
++ mtlbEntry = mtlbEntry
++ /* Secure */
++ | (1 << 4);
++ }
++
++ /* Insert Slave TLB address to Master TLB entry.*/
++ _WritePageEntry(Mmu->mtlbLogical + offset, mtlbEntry);
++
++ /* Record stlb. */
++ stlbs[offset] = stlb;
++ }
++
++ *PageTable = &stlb->logical[_StlbOffset(Address)];
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++_CheckMap(
++ IN gckMMU Mmu
++ )
++{
++ gceSTATUS status;
++ gctUINT32_PTR map = Mmu->mapLogical;
++ gctUINT32 index;
++
++ for (index = Mmu->heapList; index < Mmu->pageTableEntries;)
++ {
++ /* Check the node type. */
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index])))
++ {
++ case gcvMMU_SINGLE:
++ /* Move to next node. */
++ index = _ReadPageEntry(&map[index]) >> 8;
++ break;
++
++ case gcvMMU_FREE:
++ /* Move to next node. */
++ index = _ReadPageEntry(&map[index + 1]);
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index [%u] = %x!", index, map[index]);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++gceSTATUS
++gckMMU_FlatMapping(
++ IN gckMMU Mmu,
++ IN gctUINT32 Physical
++ )
++{
++ gceSTATUS status;
++ gctUINT32 index = _AddressToIndex(Mmu, Physical);
++ gctUINT32 i;
++ gctBOOL gotIt = gcvFALSE;
++ gctUINT32_PTR map = Mmu->mapLogical;
++ gctUINT32 previous = ~0U;
++ gctUINT32_PTR pageTable;
++
++ gckMMU_GetPageEntry(Mmu, Physical, &pageTable);
++
++ _WritePageEntry(pageTable, _SetPage(Physical));
++
++ if (map)
++ {
++ /* Find node which contains index. */
++ for (i = 0; !gotIt && (i < Mmu->pageTableEntries);)
++ {
++ gctUINT32 numPages;
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i])))
++ {
++ case gcvMMU_SINGLE:
++ if (i == index)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ previous = i;
++ i = _ReadPageEntry(&map[i]) >> 8;
++ }
++ break;
++
++ case gcvMMU_FREE:
++ numPages = _ReadPageEntry(&map[i]) >> 8;
++ if (index >= i && index < i + numPages)
++ {
++ gotIt = gcvTRUE;
++ }
++ else
++ {
++ previous = i;
++ i = _ReadPageEntry(&map[i + 1]);
++ }
++ break;
++
++ default:
++ gcmkFATAL("MMU table correcupted at index %u!", index);
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i])))
++ {
++ case gcvMMU_SINGLE:
++ /* Unlink single node from free list. */
++ gcmkONERROR(
++ _Link(Mmu, previous, _ReadPageEntry(&map[i]) >> 8));
++ break;
++
++ case gcvMMU_FREE:
++ /* Split the node. */
++ {
++ gctUINT32 start;
++ gctUINT32 next = _ReadPageEntry(&map[i+1]);
++ gctUINT32 total = _ReadPageEntry(&map[i]) >> 8;
++ gctUINT32 countLeft = index - i;
++ gctUINT32 countRight = total - countLeft - 1;
++
++ if (countLeft)
++ {
++ start = i;
++ _AddFree(Mmu, previous, start, countLeft);
++ previous = start;
++ }
++
++ if (countRight)
++ {
++ start = index + 1;
++ _AddFree(Mmu, previous, start, countRight);
++ previous = start;
++ }
++
++ _Link(Mmu, previous, next);
++ }
++ break;
++ }
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++
++ /* Roll back. */
++ return status;
++}
++
++
++
++gceSTATUS
++gckMMU_FreePagesEx(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32_PTR node;
++ gceSTATUS status;
++
++#if gcdUSE_MMU_EXCEPTION
++ gctUINT32 i;
++ struct _gcsMMU_STLB *stlb;
++ struct _gcsMMU_STLB **stlbs = Mmu->stlbs;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%x Address=0x%x PageCount=%lu",
++ Mmu, Address, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ /* Get the node by index. */
++ node = Mmu->mapLogical + _AddressToIndex(Mmu, Address);
++
++ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE));
++
++ if (PageCount == 1)
++ {
++ /* Single page node. */
++ _WritePageEntry(node, (~((1U<<8)-1)) | gcvMMU_SINGLE);
++ }
++ else
++ {
++ /* Mark the node as free. */
++ _WritePageEntry(node, (PageCount << 8) | gcvMMU_FREE);
++ _WritePageEntry(node + 1, ~0U);
++ }
++
++ /* We have free nodes. */
++ Mmu->freeNodes = gcvTRUE;
++
++#if gcdUSE_MMU_EXCEPTION
++ for (i = 0; i < PageCount; i++)
++ {
++ /* Get */
++ stlb = stlbs[_MtlbOffset(Address)];
++
++ /* Enable exception */
++ stlb->logical[_StlbOffset(Address)] = gcdMMU_STLB_EXCEPTION;
++ }
++#endif
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex));
++
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu,
++ IN gceSURF_TYPE Type
++ )
++{
++ gckHARDWARE hardware;
++ gctUINT32 mask;
++ gctINT i;
++
++ if (Type == gcvSURF_VERTEX || Type == gcvSURF_INDEX)
++ {
++ mask = gcvPAGE_TABLE_DIRTY_BIT_FE;
++ }
++ else
++ {
++ mask = gcvPAGE_TABLE_DIRTY_BIT_OTHER;
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ gcmkVERIFY_OK(
++ gckOS_AtomSetMask(Mmu->pageTableDirty[i], mask));
++ }
++#else
++#if gcdSHARED_PAGETABLE
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ hardware = sharedPageTable->hardwares[i];
++ if (hardware)
++ {
++ gcmkVERIFY_OK(gckOS_AtomSetMask(hardware->pageTableDirty, mask));
++ }
++ }
++#elif gcdMIRROR_PAGETABLE
++ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++)
++ {
++ hardware = mirrorPageTable->hardwares[i];
++
++ /* Notify cores who use this page table. */
++ gcmkVERIFY_OK(
++ gckOS_AtomSetMask(hardware->pageTableDirty, mask));
++ }
++#else
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSetMask(hardware->pageTableDirty, mask));
++#endif
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ )
++{
++#if gcdPROCESS_ADDRESS_SPACE
++ gcsMMU_STLB_PTR *stlbs = Mmu->stlbs;
++ gcsMMU_STLB_PTR stlbDesc = stlbs[_MtlbOffset(Address)];
++#else
++ gctUINT32_PTR pageTable;
++ gctUINT32 index;
++ gctUINT32 mtlb, stlb;
++#endif
++
++ gcmkHEADER_ARG("Mmu=0x%08X Address=0x%08X", Mmu, Address);
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ gcmkASSERT(Mmu->hardware->mmuVersion > 0);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ if (stlbDesc)
++ {
++ gcmkPRINT(" STLB entry = 0x%08X",
++ _ReadPageEntry(&stlbDesc->logical[_StlbOffset(Address)]));
++ }
++ else
++ {
++ gcmkPRINT(" MTLB entry is empty.");
++ }
++#else
++ mtlb = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT;
++
++ if (mtlb >= Mmu->dynamicMappingStart)
++ {
++ stlb = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT;
++
++ pageTable = Mmu->pageTableLogical;
++
++ index = (mtlb - Mmu->dynamicMappingStart)
++ * gcdMMU_STLB_4K_ENTRY_NUM
++ + stlb;
++
++ gcmkPRINT(" Page table entry = 0x%08X", _ReadPageEntry(pageTable + index));
++ }
++ else
++ {
++ gcsMMU_STLB_PTR stlbObj = Mmu->staticSTLB;
++ gctUINT32 entry = Mmu->mtlbLogical[mtlb];
++
++ stlb = (Address & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT;
++
++ entry &= 0xFFFFFFF0;
++
++ while (stlbObj)
++ {
++
++ if (entry == stlbObj->physBase)
++ {
++ gcmkPRINT(" Page table entry = 0x%08X", stlbObj->logical[stlb]);
++ break;
++ }
++
++ stlbObj = stlbObj->next;
++ }
++ }
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/******************************************************************************
++****************************** T E S T C O D E ******************************
++******************************************************************************/
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu_vg.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,522 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_MMU
++
++/*******************************************************************************
++**
++** gckVGMMU_Construct
++**
++** Construct a new gckVGMMU object.
++**
++** INPUT:
++**
++** gckVGKERNEL Kernel
++** Pointer to an gckVGKERNEL object.
++**
++** gctSIZE_T MmuSize
++** Number of bytes for the page table.
++**
++** OUTPUT:
++**
++** gckVGMMU * Mmu
++** Pointer to a variable that receives the gckVGMMU object pointer.
++*/
++gceSTATUS gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT32 MmuSize,
++ OUT gckVGMMU * Mmu
++ )
++{
++ gckOS os;
++ gckVGHARDWARE hardware;
++ gceSTATUS status;
++ gckVGMMU mmu;
++ gctUINT32 * pageTable;
++ gctUINT32 i;
++
++ gcmkHEADER_ARG("Kernel=0x%x MmuSize=0x%x Mmu=0x%x", Kernel, MmuSize, Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(MmuSize > 0);
++ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Extract the gckVGHARDWARE object pointer. */
++ hardware = Kernel->hardware;
++ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE);
++
++ /* Allocate memory for the gckVGMMU object. */
++ status = gckOS_Allocate(os, sizeof(struct _gckVGMMU), (gctPOINTER *) &mmu);
++
++ if (status < 0)
++ {
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate gckVGMMU object.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Initialize the gckVGMMU object. */
++ mmu->object.type = gcvOBJ_MMU;
++ mmu->os = os;
++ mmu->hardware = hardware;
++
++ /* Create the mutex. */
++ status = gckOS_CreateMutex(os, &mmu->mutex);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Allocate the page table. */
++ mmu->pageTableSize = (gctUINT32)MmuSize;
++ status = gckOS_AllocateContiguous(os,
++ gcvFALSE,
++ &mmu->pageTableSize,
++ &mmu->pageTablePhysical,
++ &mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not allocate page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Compute number of entries in page table. */
++ mmu->entryCount = (gctUINT32)mmu->pageTableSize / sizeof(gctUINT32);
++ mmu->entry = 0;
++
++ /* Mark the entire page table as available. */
++ pageTable = (gctUINT32 *) mmu->pageTableLogical;
++ for (i = 0; i < mmu->entryCount; i++)
++ {
++ pageTable[i] = (gctUINT32)~0;
++ }
++
++ /* Set page table address. */
++ status = gckVGHARDWARE_SetMMU(hardware, mmu->pageTableLogical);
++
++ if (status < 0)
++ {
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(mmu->os,
++ mmu->pageTablePhysical,
++ mmu->pageTableLogical,
++ mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex));
++
++ mmu->object.type = gcvOBJ_UNKNOWN;
++ gcmkVERIFY_OK(gckOS_Free(os, mmu));
++
++ /* Error. */
++ gcmkFATAL(
++ "%s(%d): could not program page table.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Return the gckVGMMU object pointer. */
++ *Mmu = mmu;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u entries at %p.(0x%08X)\n",
++ __FUNCTION__, __LINE__,
++ mmu->entryCount,
++ mmu->pageTableLogical,
++ mmu->pageTablePhysical
++ );
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_Destroy
++**
++** Destroy a nAQMMU object.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++
++ /* Free the page table. */
++ gcmkVERIFY_OK(gckOS_FreeContiguous(Mmu->os,
++ Mmu->pageTablePhysical,
++ Mmu->pageTableLogical,
++ Mmu->pageTableSize));
++
++ /* Roll back. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->mutex));
++
++ /* Mark the gckVGMMU object as unknown. */
++ Mmu->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVGMMU object. */
++ gcmkVERIFY_OK(gckOS_Free(Mmu->os, Mmu));
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_AllocatePages
++**
++** Allocate pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctSIZE_T PageCount
++** Number of pages to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * PageTable
++** Pointer to a variable that receives the base address of the page
++** table.
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the hardware specific address.
++*/
++gceSTATUS gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 tail, index, i;
++ gctUINT32 * table;
++ gctBOOL allocated = gcvFALSE;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageCount=0x%x PageTable=0x%x Address=0x%x",
++ Mmu, PageCount, PageTable, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ if (PageCount > Mmu->entryCount)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): page table too small for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ gcmkFOOTER_NO();
++ /* Not enough pages avaiable. */
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Grab the mutex. */
++ status = gckOS_AcquireMutex(Mmu->os, Mmu->mutex, gcvINFINITE);
++
++ if (status < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): could not acquire mutex.\n"
++ ,__FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER();
++ /* Error. */
++ return status;
++ }
++
++ /* Compute the tail for this allocation. */
++ tail = Mmu->entryCount - (gctUINT32)PageCount;
++
++ /* Walk all entries until we find enough slots. */
++ for (index = Mmu->entry; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++
++ if (!allocated)
++ {
++ if (status >= 0)
++ {
++ /* Walk all entries until we find enough slots. */
++ for (index = 0; index <= tail;)
++ {
++ /* Access page table. */
++ table = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ /* See if all slots are available. */
++ for (i = 0; i < PageCount; i++, table++)
++ {
++ if (*table != ~0)
++ {
++ /* Start from next slot. */
++ index += i + 1;
++ break;
++ }
++ }
++
++ if (i == PageCount)
++ {
++ /* Bail out if we have enough page entries. */
++ allocated = gcvTRUE;
++ break;
++ }
++ }
++ }
++ }
++
++ if (!allocated && (status >= 0))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_MMU,
++ "%s(%d): not enough free pages for %u pages.\n",
++ __FUNCTION__, __LINE__,
++ PageCount
++ );
++
++ /* Not enough empty slots available. */
++ status = gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ if (status >= 0)
++ {
++ /* Build virtual address. */
++ status = gckVGHARDWARE_BuildVirtualAddress(Mmu->hardware,
++ index,
++ 0,
++ Address);
++
++ if (status >= 0)
++ {
++ /* Update current entry into page table. */
++ Mmu->entry = index + (gctUINT32)PageCount;
++
++ /* Return pointer to page table. */
++ *PageTable = (gctUINT32 *) Mmu->pageTableLogical + index;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): allocated %u pages at index %u (0x%08X) @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ index,
++ *Address,
++ *PageTable
++ );
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->mutex));
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVGMMU_FreePages
++**
++** Free pages inside the page table.
++**
++** INPUT:
++**
++** gckVGMMU Mmu
++** Pointer to an gckVGMMU object.
++**
++** gctPOINTER PageTable
++** Base address of the page table to free.
++**
++** gctSIZE_T PageCount
++** Number of pages to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ )
++{
++ gctUINT32 * table;
++
++ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=0x%x",
++ Mmu, PageTable, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_MMU,
++ "%s(%d): freeing %u pages at index %u @ %p.\n",
++ __FUNCTION__, __LINE__,
++ PageCount,
++ ((gctUINT32 *) PageTable - (gctUINT32 *) Mmu->pageTableLogical),
++ PageTable
++ );
++
++ /* Convert pointer. */
++ table = (gctUINT32 *) PageTable;
++
++ /* Mark the page table entries as available. */
++ while (PageCount-- > 0)
++ {
++ *table++ = (gctUINT32)~0;
++ }
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ )
++{
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU);
++ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL);
++ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF));
++
++ *PageEntry = PageAddress;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ )
++{
++ gckVGHARDWARE hardware;
++
++ gcmkHEADER_ARG("Mmu=0x%x", Mmu);
++
++ hardware = Mmu->hardware;
++ gcmkVERIFY_OK(
++ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_power.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,347 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_POWER
++
++/******************************************************************************\
++************************ Dynamic Voltage Frequency Setting *********************
++\******************************************************************************/
++#if gcdDVFS
++static gctUINT32
++_GetLoadHistory(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Select,
++ IN gctUINT32 Index
++)
++{
++ return Dvfs->loads[Index];
++}
++
++static void
++_IncreaseScale(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ if (Dvfs->currentScale < 32)
++ {
++ *Scale = Dvfs->currentScale + 8;
++ }
++ else
++ {
++ *Scale = Dvfs->currentScale + 8;
++ *Scale = gcmMIN(64, *Scale);
++ }
++}
++
++static void
++_RecordFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory *history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ if (history->frequency == 0)
++ {
++ history->frequency = Frequency;
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ history->count++;
++ }
++}
++
++static gctUINT32
++_GetFrequencyHistory(
++ gckDVFS Dvfs,
++ gctUINT32 Frequency
++ )
++{
++ gctUINT32 i = 0;
++
++ struct _FrequencyHistory * history = Dvfs->frequencyHistory;
++
++ for (i = 0; i < 16; i++)
++ {
++ if (history->frequency == Frequency)
++ {
++ break;
++ }
++
++ history++;
++ }
++
++ if (i < 16)
++ {
++ return history->count;
++ }
++
++ return 0;
++}
++
++static void
++_Policy(
++ IN gckDVFS Dvfs,
++ IN gctUINT32 Load,
++ OUT gctUINT8 *Scale
++ )
++{
++ gctUINT8 load[4], nextLoad;
++ gctUINT8 scale;
++
++ /* Last 4 history. */
++ load[0] = (Load & 0xFF);
++ load[1] = (Load & 0xFF00) >> 8;
++ load[2] = (Load & 0xFF0000) >> 16;
++ load[3] = (Load & 0xFF000000) >> 24;
++
++ /* Determine target scale. */
++ if (load[0] > 54)
++ {
++ _IncreaseScale(Dvfs, Load, &scale);
++ }
++ else
++ {
++ nextLoad = (load[0] + load[1] + load[2] + load[3])/4;
++
++ scale = Dvfs->currentScale * (nextLoad) / 54;
++
++ scale = gcmMAX(1, scale);
++ scale = gcmMIN(64, scale);
++ }
++
++ Dvfs->totalConfig++;
++
++ Dvfs->loads[(load[0]-1)/8]++;
++
++ *Scale = scale;
++
++
++ if (Dvfs->totalConfig % 100 == 0)
++ {
++ gcmkPRINT("=======================================================");
++ gcmkPRINT("GPU Load: %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ 8, 16, 24, 32, 40, 48, 56, 64);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d",
++ _GetLoadHistory(Dvfs,2, 0),
++ _GetLoadHistory(Dvfs,2, 1),
++ _GetLoadHistory(Dvfs,2, 2),
++ _GetLoadHistory(Dvfs,2, 3),
++ _GetLoadHistory(Dvfs,2, 4),
++ _GetLoadHistory(Dvfs,2, 5),
++ _GetLoadHistory(Dvfs,2, 6),
++ _GetLoadHistory(Dvfs,2, 7)
++ );
++
++ gcmkPRINT("Frequency(MHz) %-8d %-8d %-8d %-8d %-8d",
++ 58, 120, 240, 360, 480);
++ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d",
++ _GetFrequencyHistory(Dvfs, 58),
++ _GetFrequencyHistory(Dvfs,120),
++ _GetFrequencyHistory(Dvfs,240),
++ _GetFrequencyHistory(Dvfs,360),
++ _GetFrequencyHistory(Dvfs,480)
++ );
++ }
++}
++
++static void
++_TimerFunction(
++ gctPOINTER Data
++ )
++{
++ gceSTATUS status;
++ gckDVFS dvfs = (gckDVFS) Data;
++ gckHARDWARE hardware = dvfs->hardware;
++ gctUINT32 value;
++ gctUINT32 frequency;
++ gctUINT8 scale;
++ gctUINT32 t1, t2, consumed;
++
++ gckOS_GetTicks(&t1);
++
++ gcmkONERROR(gckHARDWARE_QueryLoad(hardware, &value));
++
++ /* determine target sacle. */
++ _Policy(dvfs, value, &scale);
++
++ /* Set frequency and voltage. */
++ gcmkONERROR(gckOS_SetGPUFrequency(hardware->os, hardware->core, scale));
++
++ /* Query real frequency. */
++ gcmkONERROR(
++ gckOS_QueryGPUFrequency(hardware->os,
++ hardware->core,
++ &frequency,
++ &dvfs->currentScale));
++
++ _RecordFrequencyHistory(dvfs, frequency);
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_POWER,
++ "Current frequency = %d",
++ frequency);
++
++ /* Set period. */
++ gcmkONERROR(gckHARDWARE_SetDVFSPeroid(hardware, frequency));
++
++OnError:
++ /* Determine next querying time. */
++ gckOS_GetTicks(&t2);
++
++ consumed = gcmMIN(((long)t2 - (long)t1), 5);
++
++ if (dvfs->stop == gcvFALSE)
++ {
++ gcmkVERIFY_OK(gckOS_StartTimer(hardware->os,
++ dvfs->timer,
++ dvfs->pollingTime - consumed));
++ }
++
++ return;
++}
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Dvfs
++ )
++{
++ gceSTATUS status;
++ gctPOINTER pointer;
++ gckDVFS dvfs = gcvNULL;
++ gckOS os = Hardware->os;
++
++ gcmkHEADER_ARG("Hardware=0x%X", Hardware);
++
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Allocate a gckDVFS manager. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckDVFS), &pointer));
++
++ gckOS_ZeroMemory(pointer, gcmSIZEOF(struct _gckDVFS));
++
++ dvfs = pointer;
++
++ /* Initialization. */
++ dvfs->hardware = Hardware;
++ dvfs->pollingTime = gcdDVFS_POLLING_TIME;
++ dvfs->os = Hardware->os;
++ dvfs->currentScale = 64;
++
++ /* Create a polling timer. */
++ gcmkONERROR(gckOS_CreateTimer(os, _TimerFunction, pointer, &dvfs->timer));
++
++ /* Initialize frequency and voltage adjustment helper. */
++ gcmkONERROR(gckOS_PrepareGPUFrequency(os, Hardware->core));
++
++ /* Return result. */
++ *Dvfs = dvfs;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (dvfs)
++ {
++ if (dvfs->timer)
++ {
++ gcmkVERIFY_OK(gckOS_DestroyTimer(os, dvfs->timer));
++ }
++
++ gcmkOS_SAFE_FREE(os, dvfs);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ /* Deinitialize helper fuunction. */
++ gcmkVERIFY_OK(gckOS_FinishGPUFrequency(Dvfs->os, Dvfs->hardware->core));
++
++ /* DestroyTimer. */
++ gcmkVERIFY_OK(gckOS_DestroyTimer(Dvfs->os, Dvfs->timer));
++
++ gcmkOS_SAFE_FREE(Dvfs->os, Dvfs);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ gckHARDWARE_InitDVFS(Dvfs->hardware);
++
++ Dvfs->stop = gcvFALSE;
++
++ gckOS_StartTimer(Dvfs->os, Dvfs->timer, Dvfs->pollingTime);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ )
++{
++ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs);
++ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL);
++
++ Dvfs->stop = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_precomp.h 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,29 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_precomp_h_
++#define __gc_hal_kernel_precomp_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++
++#endif /* __gc_hal_kernel_precomp_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_security.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,239 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++
++
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++#if gcdSECURITY
++
++/*
++** Open a security service channel.
++*/
++gceSTATUS
++gckKERNEL_SecurityOpen(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GPU,
++ OUT gctUINT32 *Channel
++ )
++{
++ gceSTATUS status;
++
++ gcmkONERROR(gckOS_OpenSecurityChannel(Kernel->os, Kernel->core, Channel));
++ gcmkONERROR(gckOS_InitSecurityChannel(*Channel));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++/*
++** Close a security service channel
++*/
++gceSTATUS
++gckKERNEL_SecurityClose(
++ IN gctUINT32 Channel
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*
++** Security service interface.
++*/
++gceSTATUS
++gckKERNEL_SecurityCallService(
++ IN gctUINT32 Channel,
++ IN OUT gcsTA_INTERFACE * Interface
++)
++{
++ gceSTATUS status;
++ gcmkHEADER();
++
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ gckOS_CallSecurityService(Channel, Interface);
++
++ status = Interface->result;
++
++ gcmkONERROR(status);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityStartCommand(
++ IN gckKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_START_COMMAND;
++ iface.u.StartCommand.gpu = Kernel->core;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityAllocateSecurityMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Bytes,
++ OUT gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_ALLOCATE_SECRUE_MEMORY;
++ iface.u.AllocateSecurityMemory.bytes = Bytes;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ *Handle = iface.u.AllocateSecurityMemory.memory_handle;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityExecute(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Buffer,
++ IN gctUINT32 Bytes
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_EXECUTE;
++ iface.u.Execute.command_buffer = (gctUINT32 *)Buffer;
++ iface.u.Execute.gpu = Kernel->core;
++ iface.u.Execute.command_buffer_length = Bytes;
++
++#if defined(LINUX)
++ gcmkONERROR(gckOS_GetPhysicalAddress(Kernel->os, Buffer,
++ (gctUINT32 *)&iface.u.Execute.command_buffer));
++#endif
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ /* Update queue tail pointer. */
++ gcmkONERROR(gckHARDWARE_UpdateQueueTail(
++ Kernel->hardware, 0, 0
++ ));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityMapMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 *PhysicalArray,
++ IN gctUINT32 PageCount,
++ OUT gctUINT32 * GPUAddress
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_MAP_MEMORY;
++
++#if defined(LINUX)
++ gcmkONERROR(gckOS_GetPhysicalAddress(Kernel->os, PhysicalArray,
++ (gctUINT32 *)&iface.u.MapMemory.physicals));
++#endif
++
++ iface.u.MapMemory.pageCount = PageCount;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ *GPUAddress = iface.u.MapMemory.gpuAddress;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_SecurityUnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 GPUAddress,
++ IN gctUINT32 PageCount
++ )
++{
++ gceSTATUS status;
++ gcsTA_INTERFACE iface;
++
++ gcmkHEADER();
++
++ iface.command = KERNEL_UNMAP_MEMORY;
++
++ iface.u.UnmapMemory.gpuAddress = GPUAddress;
++ iface.u.UnmapMemory.pageCount = PageCount;
++
++ gcmkONERROR(gckKERNEL_SecurityCallService(Kernel->securityChannel, &iface));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.c 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,833 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#if gcdENABLE_VG
++
++#define _GC_OBJ_ZONE gcvZONE_VG
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_Construct
++**
++** Construct a new gckKERNEL object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN gctPOINTER Context
++** Pointer to a driver defined context.
++**
++** OUTPUT:
++**
++** gckKERNEL * Kernel
++** Pointer to a variable that will hold the pointer to the gckKERNEL
++** object.
++*/
++gceSTATUS gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ )
++{
++ gceSTATUS status;
++ gckVGKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++
++ do
++ {
++ /* Allocate the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Allocate(
++ Os,
++ sizeof(struct _gckVGKERNEL),
++ (gctPOINTER *) &kernel
++ ));
++
++ /* Initialize the gckKERNEL object. */
++ kernel->object.type = gcvOBJ_KERNEL;
++ kernel->os = Os;
++ kernel->context = Context;
++ kernel->hardware = gcvNULL;
++ kernel->interrupt = gcvNULL;
++ kernel->command = gcvNULL;
++ kernel->mmu = gcvNULL;
++ kernel->kernel = inKernel;
++
++ /* Construct the gckVGHARDWARE object. */
++ gcmkERR_BREAK(gckVGHARDWARE_Construct(
++ Os, &kernel->hardware
++ ));
++
++ /* Set pointer to gckKERNEL object in gckVGHARDWARE object. */
++ kernel->hardware->kernel = kernel;
++
++ /* Construct the gckVGINTERRUPT object. */
++ gcmkERR_BREAK(gckVGINTERRUPT_Construct(
++ kernel, &kernel->interrupt
++ ));
++
++ /* Construct the gckVGCOMMAND object. */
++ gcmkERR_BREAK(gckVGCOMMAND_Construct(
++ kernel, gcmKB2BYTES(8), gcmKB2BYTES(2), &kernel->command
++ ));
++
++ /* Construct the gckVGMMU object. */
++ gcmkERR_BREAK(gckVGMMU_Construct(
++ kernel, gcmKB2BYTES(32), &kernel->mmu
++ ));
++
++ /* Return pointer to the gckKERNEL object. */
++ *Kernel = kernel;
++
++ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel);
++ /* Success. */
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Roll back. */
++ if (kernel != gcvNULL)
++ {
++ if (kernel->mmu != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGMMU_Destroy(kernel->mmu));
++ }
++
++ if (kernel->command != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGCOMMAND_Destroy(kernel->command));
++ }
++
++ if (kernel->interrupt != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGINTERRUPT_Destroy(kernel->interrupt));
++ }
++
++ if (kernel->hardware != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckVGHARDWARE_Destroy(kernel->hardware));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(Os, kernel));
++ }
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Destroy
++**
++** Destroy an gckKERNEL object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ do
++ {
++ /* Destroy the gckVGMMU object. */
++ if (Kernel->mmu != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGMMU_Destroy(Kernel->mmu));
++ Kernel->mmu = gcvNULL;
++ }
++
++ /* Destroy the gckVGCOMMAND object. */
++ if (Kernel->command != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGCOMMAND_Destroy(Kernel->command));
++ Kernel->command = gcvNULL;
++ }
++
++ /* Destroy the gckVGINTERRUPT object. */
++ if (Kernel->interrupt != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGINTERRUPT_Destroy(Kernel->interrupt));
++ Kernel->interrupt = gcvNULL;
++ }
++
++ /* Destroy the gckVGHARDWARE object. */
++ if (Kernel->hardware != gcvNULL)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_Destroy(Kernel->hardware));
++ Kernel->hardware = gcvNULL;
++ }
++
++ /* Mark the gckKERNEL object as unknown. */
++ Kernel->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckKERNEL object. */
++ gcmkERR_BREAK(gckOS_Free(Kernel->os, Kernel));
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_AllocateLinearMemory
++**
++** Function walks all required memory pools and allocates the requested
++** amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL * Pool
++** Pointer the desired memory pool.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctSIZE_T Alignment
++** Required buffer alignment.
++**
++** gceSURF_TYPE Type
++** Surface type.
++**
++** OUTPUT:
++**
++** gcePOOL * Pool
++** Pointer to the actual pool where the memory was allocated.
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Allocated node.
++*/
++gceSTATUS
++gckVGKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gcePOOL pool;
++ gceSTATUS status;
++ gckVIDMEM videoMemory;
++
++ /* Get initial pool. */
++ switch (pool = *Pool)
++ {
++ case gcvPOOL_DEFAULT:
++ case gcvPOOL_LOCAL:
++ pool = gcvPOOL_LOCAL_INTERNAL;
++ break;
++
++ case gcvPOOL_UNIFIED:
++ pool = gcvPOOL_SYSTEM;
++ break;
++
++ default:
++ break;
++ }
++
++ do
++ {
++ /* Verify the number of bytes to allocate. */
++ if (Bytes == 0)
++ {
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++
++ if (pool == gcvPOOL_VIRTUAL)
++ {
++ /* Create a gcuVIDMEM_NODE for virtual memory. */
++ gcmkERR_BREAK(gckVIDMEM_ConstructVirtual(Kernel, gcvFALSE, Bytes, Node));
++
++ /* Success. */
++ break;
++ }
++
++ else
++ {
++ /* Get pointer to gckVIDMEM object for pool. */
++ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory);
++
++ if (status == gcvSTATUS_OK)
++ {
++ /* Allocate memory. */
++ status = gckVIDMEM_AllocateLinear(Kernel,
++ videoMemory,
++ Bytes,
++ Alignment,
++ Type,
++ (*Pool == gcvPOOL_SYSTEM),
++ Node);
++
++ if (status == gcvSTATUS_OK)
++ {
++ /* Memory allocated. */
++ break;
++ }
++ }
++ }
++
++ if (pool == gcvPOOL_LOCAL_INTERNAL)
++ {
++ /* Advance to external memory. */
++ pool = gcvPOOL_LOCAL_EXTERNAL;
++ }
++ else if (pool == gcvPOOL_LOCAL_EXTERNAL)
++ {
++ /* Advance to contiguous system memory. */
++ pool = gcvPOOL_SYSTEM;
++ }
++ else if (pool == gcvPOOL_SYSTEM)
++ {
++ /* Advance to virtual memory. */
++ pool = gcvPOOL_VIRTUAL;
++ }
++ else
++ {
++ /* Out of pools. */
++ break;
++ }
++ }
++ /* Loop only for multiple selection pools. */
++ while ((*Pool == gcvPOOL_DEFAULT)
++ || (*Pool == gcvPOOL_LOCAL)
++ || (*Pool == gcvPOOL_UNIFIED)
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Return pool used for allocation. */
++ *Pool = pool;
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_Dispatch
++**
++** Dispatch a command received from the user HAL layer.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that defines the command to
++** be dispatched.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to a gcsHAL_INTERFACE structure that receives any data to be
++** returned.
++*/
++gceSTATUS gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE * kernelInterface = Interface;
++ gctUINT32 processID;
++ gckKERNEL kernel = Kernel;
++ gctPOINTER info = gcvNULL;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctPOINTER logical = gcvNULL;
++ gctSIZE_T bytes = 0;
++
++ gcmkHEADER_ARG("Kernel=0x%x Interface=0x%x ", Kernel, Interface);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != gcvNULL);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ /* Dispatch on command. */
++ switch (Interface->command)
++ {
++ case gcvHAL_QUERY_VIDEO_MEMORY:
++ /* Query video memory size. */
++ gcmkERR_BREAK(gckKERNEL_QueryVideoMemory(
++ Kernel, kernelInterface
++ ));
++ break;
++
++ case gcvHAL_QUERY_CHIP_IDENTITY:
++ /* Query chip identity. */
++ gcmkERR_BREAK(gckVGHARDWARE_QueryChipIdentity(
++ Kernel->vg->hardware,
++ &kernelInterface->u.QueryChipIdentity.chipModel,
++ &kernelInterface->u.QueryChipIdentity.chipRevision,
++ &kernelInterface->u.QueryChipIdentity.chipFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures,
++ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures2
++ ));
++ break;
++
++ case gcvHAL_QUERY_COMMAND_BUFFER:
++ /* Query command buffer information. */
++ gcmkERR_BREAK(gckKERNEL_QueryCommandBuffer(
++ Kernel,
++ &kernelInterface->u.QueryCommandBuffer.information
++ ));
++ break;
++ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate non-paged memory. */
++ gcmkERR_BREAK(gckOS_AllocateNonPagedMemory(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_NON_PAGED_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free non-paged memory. */
++ gcmkERR_BREAK(gckOS_FreeNonPagedMemory(
++ Kernel->os,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY:
++ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes;
++ /* Allocate contiguous memory. */
++ gcmkERR_BREAK(gckOS_AllocateContiguous(
++ Kernel->os,
++ gcvTRUE,
++ &bytes,
++ &physical,
++ &logical
++ ));
++
++ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes;
++ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical);
++ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical);
++ break;
++
++ case gcvHAL_FREE_CONTIGUOUS_MEMORY:
++ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical);
++ /* Unmap user logical out of physical memory first. */
++ gcmkERR_BREAK(gckOS_UnmapUserLogical(
++ Kernel->os,
++ physical,
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical)
++ ));
++
++ /* Free contiguous memory. */
++ gcmkERR_BREAK(gckOS_FreeContiguous(
++ Kernel->os,
++ physical,
++ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical),
++ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical);
++ break;
++
++ case gcvHAL_ALLOCATE_VIDEO_MEMORY:
++ gcmkERR_BREAK(gcvSTATUS_NOT_SUPPORTED);
++ break;
++
++ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY:
++ /* Allocate memory. */
++ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory(
++ Kernel, processID,
++ &kernelInterface->u.AllocateLinearVideoMemory.pool,
++ kernelInterface->u.AllocateLinearVideoMemory.bytes,
++ kernelInterface->u.AllocateLinearVideoMemory.alignment,
++ kernelInterface->u.AllocateLinearVideoMemory.type,
++ kernelInterface->u.AllocateLinearVideoMemory.flag,
++ &kernelInterface->u.AllocateLinearVideoMemory.node
++ ));
++
++ break;
++
++ case gcvHAL_RELEASE_VIDEO_MEMORY:
++ /* Free video memory. */
++ gcmkERR_BREAK(gckKERNEL_ReleaseVideoMemory(
++ Kernel, processID,
++ (gctUINT32)kernelInterface->u.ReleaseVideoMemory.node
++ ));
++
++ break;
++
++ case gcvHAL_MAP_MEMORY:
++ /* Map memory. */
++ gcmkERR_BREAK(gckKERNEL_MapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ &logical
++ ));
++ kernelInterface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical);
++ break;
++
++ case gcvHAL_UNMAP_MEMORY:
++ /* Unmap memory. */
++ gcmkERR_BREAK(gckKERNEL_UnmapMemory(
++ Kernel,
++ gcmINT2PTR(kernelInterface->u.MapMemory.physical),
++ (gctSIZE_T) kernelInterface->u.MapMemory.bytes,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapMemory.logical)
++ ));
++ break;
++
++ case gcvHAL_MAP_USER_MEMORY:
++ /* Map user memory to DMA. */
++ gcmkERR_BREAK(gckOS_MapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.MapUserMemory.memory),
++ kernelInterface->u.MapUserMemory.physical,
++ (gctSIZE_T) kernelInterface->u.MapUserMemory.size,
++ &info,
++ &kernelInterface->u.MapUserMemory.address
++ ));
++
++ kernelInterface->u.MapUserMemory.info = gcmPTR_TO_NAME(info);
++
++ /* Clear temp storage. */
++ info = gcvNULL;
++ break;
++
++ case gcvHAL_UNMAP_USER_MEMORY:
++ /* Unmap user memory. */
++ gcmkERR_BREAK(gckOS_UnmapUserMemory(
++ Kernel->os,
++ gcvCORE_VG,
++ gcmUINT64_TO_PTR(kernelInterface->u.UnmapUserMemory.memory),
++ (gctSIZE_T) kernelInterface->u.UnmapUserMemory.size,
++ gcmNAME_TO_PTR(kernelInterface->u.UnmapUserMemory.info),
++ kernelInterface->u.UnmapUserMemory.address
++ ));
++
++ gcmRELEASE_NAME(kernelInterface->u.UnmapUserMemory.info);
++ break;
++
++ case gcvHAL_LOCK_VIDEO_MEMORY:
++ gcmkONERROR(gckKERNEL_LockVideoMemory(Kernel, gcvCORE_VG, processID, FromUser, Interface));
++ break;
++
++ case gcvHAL_UNLOCK_VIDEO_MEMORY:
++ gcmkONERROR(gckKERNEL_UnlockVideoMemory(Kernel, processID, Interface));
++ break;
++
++ case gcvHAL_USER_SIGNAL:
++#if !USE_NEW_LINUX_SIGNAL
++ /* Dispatch depends on the user signal subcommands. */
++ switch(Interface->u.UserSignal.command)
++ {
++ case gcvUSER_SIGNAL_CREATE:
++ /* Create a signal used in the user space. */
++ gcmkERR_BREAK(
++ gckOS_CreateUserSignal(Kernel->os,
++ Interface->u.UserSignal.manualReset,
++ &Interface->u.UserSignal.id));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvUSER_SIGNAL_DESTROY:
++ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB(
++ Kernel,
++ processID, gcvDB_SIGNAL,
++ gcmINT2PTR(Interface->u.UserSignal.id)));
++
++ /* Destroy the signal. */
++ gcmkERR_BREAK(
++ gckOS_DestroyUserSignal(Kernel->os,
++ Interface->u.UserSignal.id));
++
++ break;
++
++ case gcvUSER_SIGNAL_SIGNAL:
++ /* Signal the signal. */
++ gcmkERR_BREAK(
++ gckOS_SignalUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.state));
++ break;
++
++ case gcvUSER_SIGNAL_WAIT:
++ /* Wait on the signal. */
++ status = gckOS_WaitUserSignal(Kernel->os,
++ Interface->u.UserSignal.id,
++ Interface->u.UserSignal.wait);
++ break;
++
++ default:
++ /* Invalid user signal command. */
++ gcmkERR_BREAK(gcvSTATUS_INVALID_ARGUMENT);
++ }
++#endif
++ break;
++
++ case gcvHAL_COMMIT:
++ /* Commit a command and context buffer. */
++ gcmkERR_BREAK(gckVGCOMMAND_Commit(
++ Kernel->vg->command,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.context),
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.queue),
++ kernelInterface->u.VGCommit.entryCount,
++ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.taskTable)
++ ));
++ break;
++ case gcvHAL_VERSION:
++ kernelInterface->u.Version.major = gcvVERSION_MAJOR;
++ kernelInterface->u.Version.minor = gcvVERSION_MINOR;
++ kernelInterface->u.Version.patch = gcvVERSION_PATCH;
++ kernelInterface->u.Version.build = gcvVERSION_BUILD;
++ status = gcvSTATUS_OK;
++ break;
++
++ case gcvHAL_GET_BASE_ADDRESS:
++ /* Get base address. */
++ gcmkERR_BREAK(
++ gckOS_GetBaseAddress(Kernel->os,
++ &kernelInterface->u.GetBaseAddress.baseAddress));
++ break;
++ case gcvHAL_IMPORT_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Import(Kernel,
++ Interface->u.ImportVideoMemory.name,
++ &Interface->u.ImportVideoMemory.handle));
++ gcmkONERROR(gckKERNEL_AddProcessDB(Kernel,
++ processID, gcvDB_VIDEO_MEMORY,
++ gcmINT2PTR(Interface->u.ImportVideoMemory.handle),
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvHAL_NAME_VIDEO_MEMORY:
++ gcmkONERROR(gckVIDMEM_NODE_Name(Kernel,
++ Interface->u.NameVideoMemory.handle,
++ &Interface->u.NameVideoMemory.name));
++ break;
++
++ case gcvHAL_DATABASE:
++ gcmkONERROR(gckKERNEL_QueryDatabase(Kernel, processID, Interface));
++ break;
++ case gcvHAL_SHBUF:
++ {
++ gctSHBUF shBuf;
++ gctPOINTER uData;
++ gctUINT32 bytes;
++
++ switch (Interface->u.ShBuf.command)
++ {
++ case gcvSHBUF_CREATE:
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Create. */
++ gcmkONERROR(gckKERNEL_CreateShBuffer(Kernel, bytes, &shBuf));
++
++ Interface->u.ShBuf.id = gcmPTR_TO_UINT64(shBuf);
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_DESTROY:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Check db first to avoid illegal destroy in the process. */
++ gcmkONERROR(
++ gckKERNEL_RemoveProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf));
++
++ gcmkONERROR(gckKERNEL_DestroyShBuffer(Kernel, shBuf));
++ break;
++
++ case gcvSHBUF_MAP:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++
++ /* Map for current process access. */
++ gcmkONERROR(gckKERNEL_MapShBuffer(Kernel, shBuf));
++
++ gcmkVERIFY_OK(
++ gckKERNEL_AddProcessDB(Kernel,
++ processID,
++ gcvDB_SHBUF,
++ shBuf,
++ gcvNULL,
++ 0));
++ break;
++
++ case gcvSHBUF_WRITE:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Write. */
++ gcmkONERROR(
++ gckKERNEL_WriteShBuffer(Kernel, shBuf, uData, bytes));
++ break;
++
++ case gcvSHBUF_READ:
++ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id);
++ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data);
++ bytes = Interface->u.ShBuf.bytes;
++
++ /* Read. */
++ gcmkONERROR(
++ gckKERNEL_ReadShBuffer(Kernel,
++ shBuf,
++ uData,
++ bytes,
++ &bytes));
++
++ /* Return copied size. */
++ Interface->u.ShBuf.bytes = bytes;
++ break;
++
++ default:
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ break;
++ }
++ }
++ break;
++ default:
++ /* Invalid command. */
++ status = gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++OnError:
++ /* Save status. */
++ kernelInterface->status = status;
++
++ gcmkFOOTER();
++
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryCommandBuffer
++**
++** Query command buffer attributes.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckVGHARDWARE object.
++**
++** OUTPUT:
++**
++** gcsCOMMAND_BUFFER_INFO_PTR Information
++** Pointer to the information structure to receive buffer attributes.
++*/
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=0x%x *Pool=0x%x",
++ Kernel, Information);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get the information. */
++ status = gckVGCOMMAND_QueryCommandBuffer(Kernel->vg->command, Information);
++
++ gcmkFOOTER();
++ /* Return status. */
++ return status;
++}
++
++#endif /* gcdENABLE_VG */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_vg.h 2016-06-19 22:11:55.229144993 +0200
+@@ -0,0 +1,85 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_vg_h_
++#define __gc_hal_kernel_vg_h_
++
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel_hardware.h"
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++
++/* gckKERNEL object. */
++struct _gckVGKERNEL
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* Pointer to gckINTERRUPT object. */
++ gckVGINTERRUPT interrupt;
++
++ /* Pointer to gckCOMMAND object. */
++ gckVGCOMMAND command;
++
++ /* Pointer to context. */
++ gctPOINTER context;
++
++ /* Pointer to gckMMU object. */
++ gckVGMMU mmu;
++
++ gckKERNEL kernel;
++};
++
++/* gckMMU object. */
++struct _gckVGMMU
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to gckOS object. */
++ gckOS os;
++
++ /* Pointer to gckHARDWARE object. */
++ gckVGHARDWARE hardware;
++
++ /* The page table mutex. */
++ gctPOINTER mutex;
++
++ /* Page table information. */
++ gctSIZE_T pageTableSize;
++ gctPHYS_ADDR pageTablePhysical;
++ gctPOINTER pageTableLogical;
++
++ /* Allocation index. */
++ gctUINT32 entryCount;
++ gctUINT32 entry;
++};
++
++#endif /* __gc_hal_kernel_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c 2016-06-19 22:11:55.233144731 +0200
+@@ -0,0 +1,2807 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_precomp.h"
++
++#define _GC_OBJ_ZONE gcvZONE_VIDMEM
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** _Split
++**
++** Split a node on the required byte boundary.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the node to split.
++**
++** gctSIZE_T Bytes
++** Number of bytes to keep in the node.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gctBOOL
++** gcvTRUE if the node was split successfully, or gcvFALSE if there is an
++** error.
++**
++*/
++static gctBOOL
++_Split(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctPOINTER pointer = gcvNULL;
++
++ /* Make sure the byte boundary makes sense. */
++ if ((Bytes <= 0) || (Bytes > Node->VidMem.bytes))
++ {
++ return gcvFALSE;
++ }
++
++ /* Allocate a new gcuVIDMEM_NODE object. */
++ if (gcmIS_ERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(gcuVIDMEM_NODE),
++ &pointer)))
++ {
++ /* Error. */
++ return gcvFALSE;
++ }
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE structure. */
++ node->VidMem.offset = Node->VidMem.offset + Bytes;
++ node->VidMem.bytes = Node->VidMem.bytes - Bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.locked = 0;
++ node->VidMem.memory = Node->VidMem.memory;
++ node->VidMem.pool = Node->VidMem.pool;
++ node->VidMem.physical = Node->VidMem.physical;
++#ifdef __QNXNTO__
++ node->VidMem.processID = 0;
++ node->VidMem.logical = gcvNULL;
++#endif
++
++ /* Insert node behind specified node. */
++ node->VidMem.next = Node->VidMem.next;
++ node->VidMem.prev = Node;
++ Node->VidMem.next = node->VidMem.next->VidMem.prev = node;
++
++ /* Insert free node behind specified node. */
++ node->VidMem.nextFree = Node->VidMem.nextFree;
++ node->VidMem.prevFree = Node;
++ Node->VidMem.nextFree = node->VidMem.nextFree->VidMem.prevFree = node;
++
++ /* Adjust size of specified node. */
++ Node->VidMem.bytes = Bytes;
++
++ /* Success. */
++ return gcvTRUE;
++}
++
++/*******************************************************************************
++**
++** _Merge
++**
++** Merge two adjacent nodes together.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to the first of the two nodes to merge.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++*/
++static gceSTATUS
++_Merge(
++ IN gckOS Os,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gceSTATUS status;
++
++ /* Save pointer to next node. */
++ node = Node->VidMem.next;
++
++ /* This is a good time to make sure the heap is not corrupted. */
++ if (Node->VidMem.offset + Node->VidMem.bytes != node->VidMem.offset)
++ {
++ /* Corrupted heap. */
++ gcmkASSERT(
++ Node->VidMem.offset + Node->VidMem.bytes == node->VidMem.offset);
++ return gcvSTATUS_HEAP_CORRUPTED;
++ }
++
++ /* Adjust byte count. */
++ Node->VidMem.bytes += node->VidMem.bytes;
++
++ /* Unlink next node from linked list. */
++ Node->VidMem.next = node->VidMem.next;
++ Node->VidMem.nextFree = node->VidMem.nextFree;
++
++ Node->VidMem.next->VidMem.prev =
++ Node->VidMem.nextFree->VidMem.prevFree = Node;
++
++ /* Free next node. */
++ status = gcmkOS_SAFE_FREE(Os, node);
++ return status;
++}
++
++/******************************************************************************\
++******************************* gckVIDMEM API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckVIDMEM_ConstructVirtual
++**
++** Construct a new gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctSIZE_T Bytes
++** Number of byte to allocate.
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that receives the gcuVIDMEM_NODE union pointer.
++*/
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("Kernel=0x%x Flag=%x Bytes=%lu", Kernel, Flag, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate an gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union for virtual memory. */
++ node->Virtual.kernel = Kernel;
++ node->Virtual.contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS;
++ node->Virtual.logical = gcvNULL;
++#if gcdENABLE_VG
++ node->Virtual.kernelVirtual = gcvNULL;
++#endif
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ node->Virtual.lockeds[i] = 0;
++ node->Virtual.pageTables[i] = gcvNULL;
++ node->Virtual.lockKernels[i] = gcvNULL;
++ }
++
++ gcmkONERROR(gckOS_GetProcessID(&node->Virtual.processID));
++
++ /* Allocate the virtual memory. */
++ gcmkONERROR(
++ gckOS_AllocatePagedMemoryEx(os,
++ Flag,
++ node->Virtual.bytes = Bytes,
++ &node->Virtual.gid,
++ &node->Virtual.physical));
++
++ /* Return pointer to the gcuVIDMEM_NODE union. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Created virtual node 0x%x for %u bytes @ 0x%x",
++ node, Bytes, node->Virtual.physical);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (node != gcvNULL)
++ {
++ /* Free the structure. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_DestroyVirtual
++**
++** Destroy an gcuVIDMEM_NODE union for virtual memory.
++**
++** INPUT:
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gckOS os;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Node->Virtual.kernel, gcvOBJ_KERNEL);
++
++ /* Extact the gckOS object pointer. */
++ os = Node->Virtual.kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Delete the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, Node));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Construct
++**
++** Construct a new gckVIDMEM object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 BaseAddress
++** Base address for the video memory heap.
++**
++** gctSIZE_T Bytes
++** Number of bytes in the video memory heap.
++**
++** gctSIZE_T Threshold
++** Minimum number of bytes beyond am allocation before the node is
++** split. Can be used as a minimum alignment requirement.
++**
++** gctSIZE_T BankSize
++** Number of bytes per physical memory bank. Used by bank
++** optimization.
++**
++** OUTPUT:
++**
++** gckVIDMEM * Memory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object.
++*/
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T BankSize,
++ OUT gckVIDMEM * Memory
++ )
++{
++ gckVIDMEM memory = gcvNULL;
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctINT i, banks = 0;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 heapBytes;
++ gctUINT32 bankSize;
++
++ gcmkHEADER_ARG("Os=0x%x BaseAddress=%08x Bytes=%lu Threshold=%lu "
++ "BankSize=%lu",
++ Os, BaseAddress, Bytes, Threshold, BankSize);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ gcmkSAFECASTSIZET(heapBytes, Bytes);
++ gcmkSAFECASTSIZET(bankSize, BankSize);
++
++ /* Allocate the gckVIDMEM object. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct _gckVIDMEM), &pointer));
++
++ memory = pointer;
++
++ /* Initialize the gckVIDMEM object. */
++ memory->object.type = gcvOBJ_VIDMEM;
++ memory->os = Os;
++
++ /* Set video memory heap information. */
++ memory->baseAddress = BaseAddress;
++ memory->bytes = heapBytes;
++ memory->freeBytes = heapBytes;
++ memory->threshold = Threshold;
++ memory->mutex = gcvNULL;
++
++ BaseAddress = 0;
++
++ /* Walk all possible banks. */
++ for (i = 0; i < gcmCOUNTOF(memory->sentinel); ++i)
++ {
++ gctUINT32 bytes;
++
++ if (BankSize == 0)
++ {
++ /* Use all bytes for the first bank. */
++ bytes = heapBytes;
++ }
++ else
++ {
++ /* Compute number of bytes for this bank. */
++ bytes = gcmALIGN(BaseAddress + 1, bankSize) - BaseAddress;
++
++ if (bytes > heapBytes)
++ {
++ /* Make sure we don't exceed the total number of bytes. */
++ bytes = heapBytes;
++ }
++ }
++
++ if (bytes == 0)
++ {
++ /* Mark heap is not used. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = gcvNULL;
++ continue;
++ }
++
++ /* Allocate one gcuVIDMEM_NODE union. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer));
++
++ node = pointer;
++
++ /* Initialize gcuVIDMEM_NODE union. */
++ node->VidMem.memory = memory;
++
++ node->VidMem.next =
++ node->VidMem.prev =
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = &memory->sentinel[i];
++
++ node->VidMem.offset = BaseAddress;
++ node->VidMem.bytes = bytes;
++ node->VidMem.alignment = 0;
++ node->VidMem.physical = 0;
++ node->VidMem.pool = gcvPOOL_UNKNOWN;
++
++ node->VidMem.locked = 0;
++
++#ifdef __QNXNTO__
++ node->VidMem.processID = 0;
++ node->VidMem.logical = gcvNULL;
++#endif
++
++#if gcdENABLE_VG
++ node->VidMem.kernelVirtual = gcvNULL;
++#endif
++
++ /* Initialize the linked list of nodes. */
++ memory->sentinel[i].VidMem.next =
++ memory->sentinel[i].VidMem.prev =
++ memory->sentinel[i].VidMem.nextFree =
++ memory->sentinel[i].VidMem.prevFree = node;
++
++ /* Mark sentinel. */
++ memory->sentinel[i].VidMem.bytes = 0;
++
++ /* Adjust address for next bank. */
++ BaseAddress += bytes;
++ heapBytes -= bytes;
++ banks ++;
++ }
++
++ /* Assign all the bank mappings. */
++ memory->mapping[gcvSURF_RENDER_TARGET] = banks - 1;
++ memory->mapping[gcvSURF_BITMAP] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_DEPTH] = banks - 1;
++ memory->mapping[gcvSURF_HIERARCHICAL_DEPTH] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TEXTURE] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_VERTEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_INDEX] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TILE_STATUS] = banks - 1;
++ if (banks > 1) --banks;
++ memory->mapping[gcvSURF_TYPE_UNKNOWN] = 0;
++
++#if gcdENABLE_VG
++ memory->mapping[gcvSURF_IMAGE] = 0;
++ memory->mapping[gcvSURF_MASK] = 0;
++ memory->mapping[gcvSURF_SCISSOR] = 0;
++#endif
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] INDEX: bank %d",
++ memory->mapping[gcvSURF_INDEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] VERTEX: bank %d",
++ memory->mapping[gcvSURF_VERTEX]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TEXTURE: bank %d",
++ memory->mapping[gcvSURF_TEXTURE]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] RENDER_TARGET: bank %d",
++ memory->mapping[gcvSURF_RENDER_TARGET]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] DEPTH: bank %d",
++ memory->mapping[gcvSURF_DEPTH]);
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "[GALCORE] TILE_STATUS: bank %d",
++ memory->mapping[gcvSURF_TILE_STATUS]);
++
++ /* Allocate the mutex. */
++ gcmkONERROR(gckOS_CreateMutex(Os, &memory->mutex));
++
++ /* Return pointer to the gckVIDMEM object. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%x", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ if (memory != gcvNULL)
++ {
++ if (memory->mutex != gcvNULL)
++ {
++ /* Delete the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, memory->mutex));
++ }
++
++ for (i = 0; i < banks; ++i)
++ {
++ /* Free the heap. */
++ gcmkASSERT(memory->sentinel[i].VidMem.next != gcvNULL);
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory->sentinel[i].VidMem.next));
++ }
++
++ /* Free the object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Destroy
++**
++** Destroy an gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ )
++{
++ gcuVIDMEM_NODE_PTR node, next;
++ gctINT i;
++
++ gcmkHEADER_ARG("Memory=0x%x", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++
++ /* Walk all sentinels. */
++ for (i = 0; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ /* Bail out of the heap is not used. */
++ if (Memory->sentinel[i].VidMem.next == gcvNULL)
++ {
++ break;
++ }
++
++ /* Walk all the nodes until we reach the sentinel. */
++ for (node = Memory->sentinel[i].VidMem.next;
++ node->VidMem.bytes != 0;
++ node = next)
++ {
++ /* Save pointer to the next node. */
++ next = node->VidMem.next;
++
++ /* Free the node. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, node));
++ }
++ }
++
++ /* Free the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Memory->os, Memory->mutex));
++
++ /* Mark the object as unknown. */
++ Memory->object.type = gcvOBJ_UNKNOWN;
++
++ /* Free the gckVIDMEM object. */
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, Memory));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_BANK_ALIGNMENT
++
++#if !gcdBANK_BIT_START
++#error gcdBANK_BIT_START not defined.
++#endif
++
++#if !gcdBANK_BIT_END
++#error gcdBANK_BIT_END not defined.
++#endif
++/*******************************************************************************
++** _GetSurfaceBankAlignment
++**
++** Return the required offset alignment required to the make BaseAddress
++** aligned properly.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gcoOS object.
++**
++** gceSURF_TYPE Type
++** Type of allocation.
++**
++** gctUINT32 BaseAddress
++** Base address of current video memory node.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR AlignmentOffset
++** Pointer to a variable that will hold the number of bytes to skip in
++** the current video memory node in order to make the alignment bank
++** aligned.
++*/
++static gceSTATUS
++_GetSurfaceBankAlignment(
++ IN gckKERNEL Kernel,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 BaseAddress,
++ OUT gctUINT32_PTR AlignmentOffset
++ )
++{
++ gctUINT32 bank;
++ /* To retrieve the bank. */
++ static const gctUINT32 bankMask = (0xFFFFFFFF << gcdBANK_BIT_START)
++ ^ (0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ /* To retrieve the bank and all the lower bytes. */
++ static const gctUINT32 byteMask = ~(0xFFFFFFFF << (gcdBANK_BIT_END + 1));
++
++ gcmkHEADER_ARG("Type=%d BaseAddress=0x%x ", Type, BaseAddress);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(AlignmentOffset != gcvNULL);
++
++ switch (Type)
++ {
++ case gcvSURF_RENDER_TARGET:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the first bank. */
++ *AlignmentOffset = (bank == 0) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + 0) - (BaseAddress & byteMask);
++ break;
++
++ case gcvSURF_DEPTH:
++ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START);
++
++ /* Align to the third bank. */
++ *AlignmentOffset = (bank == 2) ?
++ 0 :
++ ((1 << (gcdBANK_BIT_END + 1)) + (2 << gcdBANK_BIT_START)) - (BaseAddress & byteMask);
++
++ /* Minimum 256 byte alignment needed for fast_msaa. */
++ if ((gcdBANK_CHANNEL_BIT > 7) ||
++ ((gckHARDWARE_IsFeatureAvailable(Kernel->hardware, gcvFEATURE_FAST_MSAA) != gcvSTATUS_TRUE) &&
++ (gckHARDWARE_IsFeatureAvailable(Kernel->hardware, gcvFEATURE_SMALL_MSAA) != gcvSTATUS_TRUE)))
++ {
++ /* Add a channel offset at the channel bit. */
++ *AlignmentOffset += (1 << gcdBANK_CHANNEL_BIT);
++ }
++ break;
++
++ default:
++ /* no alignment needed. */
++ *AlignmentOffset = 0;
++ }
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("*AlignmentOffset=%u", *AlignmentOffset);
++ return gcvSTATUS_OK;
++}
++#endif
++
++static gcuVIDMEM_NODE_PTR
++_FindNode(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctINT Bank,
++ IN gctSIZE_T Bytes,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Alignment
++ )
++{
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++
++#if gcdENABLE_BANK_ALIGNMENT
++ gctUINT32 bankAlignment;
++ gceSTATUS status;
++#endif
++
++ if (Memory->sentinel[Bank].VidMem.nextFree == gcvNULL)
++ {
++ /* No free nodes left. */
++ return gcvNULL;
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++ /* Walk all free nodes until we have one that is big enough or we have
++ ** reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++ if (node->VidMem.bytes < Bytes)
++ {
++ continue;
++ }
++
++ gcmkONERROR(_GetSurfaceBankAlignment(
++ Kernel,
++ Type,
++ node->VidMem.memory->baseAddress + node->VidMem.offset,
++ &bankAlignment));
++
++ bankAlignment = gcmALIGN(bankAlignment, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0)
++ ? 0
++ : (*Alignment - (node->VidMem.offset % *Alignment));
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment + bankAlignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment + bankAlignment;
++ return node;
++ }
++ }
++#endif
++
++ /* Walk all free nodes until we have one that is big enough or we have
++ reached the sentinel. */
++ for (node = Memory->sentinel[Bank].VidMem.nextFree;
++ node->VidMem.bytes != 0;
++ node = node->VidMem.nextFree)
++ {
++ gctUINT offset;
++
++ gctINT modulo;
++
++ gcmkSAFECASTSIZET(offset, node->VidMem.offset);
++
++ modulo = gckMATH_ModuloInt(offset, *Alignment);
++
++ /* Compute number of bytes to skip for alignment. */
++ alignment = (*Alignment == 0) ? 0 : (*Alignment - modulo);
++
++ if (alignment == *Alignment)
++ {
++ /* Node is already aligned. */
++ alignment = 0;
++ }
++
++ if (node->VidMem.bytes >= Bytes + alignment)
++ {
++ /* This node is big enough. */
++ *Alignment = alignment;
++ return node;
++ }
++ }
++
++#if gcdENABLE_BANK_ALIGNMENT
++OnError:
++#endif
++ /* Not enough memory. */
++ return gcvNULL;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_AllocateLinear
++**
++** Allocate linear memory from the gckVIDMEM object.
++**
++** INPUT:
++**
++** gckVIDMEM Memory
++** Pointer to an gckVIDMEM object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** gctUINT32 Alignment
++** Byte alignment for allocation.
++**
++** gceSURF_TYPE Type
++** Type of surface to allocate (use by bank optimization).
++**
++** gctBOOL Specified
++** If user must use this pool, it should set Specified to gcvTRUE,
++** otherwise allocator may reserve some memory for other usage, such
++** as small block size allocation request.
++**
++** OUTPUT:
++**
++** gcuVIDMEM_NODE_PTR * Node
++** Pointer to a variable that will hold the allocated memory node.
++*/
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctBOOL Specified,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ )
++{
++ gceSTATUS status;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 alignment;
++ gctINT bank, i;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Memory=0x%x Bytes=%lu Alignment=%u Type=%d",
++ Memory, Bytes, Alignment, Type);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Type < gcvSURF_NUM_TYPES);
++
++ /* Acquire the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(Memory->os, Memory->mutex, gcvINFINITE));
++
++ acquired = gcvTRUE;
++
++ if (Bytes > Memory->freeBytes)
++ {
++ /* Not enough memory. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++
++#if gcdSMALL_BLOCK_SIZE
++ if ((Memory->freeBytes < (Memory->bytes/gcdRATIO_FOR_SMALL_MEMORY))
++ && (Bytes >= gcdSMALL_BLOCK_SIZE)
++ && (Specified == gcvFALSE)
++ )
++ {
++ /* The left memory is for small memory.*/
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++#endif
++
++ /* Find the default bank for this surface type. */
++ gcmkASSERT((gctINT) Type < gcmCOUNTOF(Memory->mapping));
++ bank = Memory->mapping[Type];
++ alignment = Alignment;
++
++ /* Find a free node in the default bank. */
++ node = _FindNode(Kernel, Memory, bank, Bytes, Type, &alignment);
++
++ /* Out of memory? */
++ if (node == gcvNULL)
++ {
++ /* Walk all lower banks. */
++ for (i = bank - 1; i >= 0; --i)
++ {
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Kernel, Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ /* Walk all upper banks. */
++ for (i = bank + 1; i < gcmCOUNTOF(Memory->sentinel); ++i)
++ {
++ if (Memory->sentinel[i].VidMem.nextFree == gcvNULL)
++ {
++ /* Abort when we reach unused banks. */
++ break;
++ }
++
++ /* Find a free node inside the current bank. */
++ node = _FindNode(Kernel, Memory, i, Bytes, Type, &alignment);
++ if (node != gcvNULL)
++ {
++ break;
++ }
++ }
++ }
++
++ if (node == gcvNULL)
++ {
++ /* Out of memory. */
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ goto OnError;
++ }
++
++ /* Do we have an alignment? */
++ if (alignment > 0)
++ {
++ /* Split the node so it is aligned. */
++ if (_Split(Memory->os, node, alignment))
++ {
++ /* Successful split, move to aligned node. */
++ node = node->VidMem.next;
++
++ /* Remove alignment. */
++ alignment = 0;
++ }
++ }
++
++ /* Do we have enough memory after the allocation to split it? */
++ if (node->VidMem.bytes - Bytes > Memory->threshold)
++ {
++ /* Adjust the node size. */
++ _Split(Memory->os, node, Bytes);
++ }
++
++ /* Remove the node from the free list. */
++ node->VidMem.prevFree->VidMem.nextFree = node->VidMem.nextFree;
++ node->VidMem.nextFree->VidMem.prevFree = node->VidMem.prevFree;
++ node->VidMem.nextFree =
++ node->VidMem.prevFree = gcvNULL;
++
++ /* Fill in the information. */
++ node->VidMem.alignment = alignment;
++ node->VidMem.memory = Memory;
++#ifdef __QNXNTO__
++ node->VidMem.logical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&node->VidMem.processID));
++#endif
++
++ /* Adjust the number of free bytes. */
++ Memory->freeBytes -= node->VidMem.bytes;
++
++#if gcdENABLE_VG
++ node->VidMem.kernelVirtual = gcvNULL;
++#endif
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++
++ /* Return the pointer to the node. */
++ *Node = node;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Allocated %u bytes @ 0x%x [0x%08X]",
++ node->VidMem.bytes, node, node->VidMem.offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Node=0x%x", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Free
++**
++** Free an allocated video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckVIDMEM_Free(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ )
++{
++ gceSTATUS status;
++ gckKERNEL kernel = gcvNULL;
++ gckVIDMEM memory = gcvNULL;
++ gcuVIDMEM_NODE_PTR node;
++ gctBOOL mutexAcquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ if ((Node == gcvNULL)
++ || (Node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /**************************** Video Memory ********************************/
++
++ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ /* Extract pointer to gckVIDMEM object owning the node. */
++ memory = Node->VidMem.memory;
++
++ /* Acquire the mutex. */
++ gcmkONERROR(
++ gckOS_AcquireMutex(memory->os, memory->mutex, gcvINFINITE));
++
++ mutexAcquired = gcvTRUE;
++
++#ifdef __QNXNTO__
++ /* Unmap the video memory. */
++ if (Node->VidMem.logical != gcvNULL)
++ {
++ gckKERNEL_UnmapVideoMemory(
++ Kernel,
++ Node->VidMem.logical,
++ Node->VidMem.processID,
++ Node->VidMem.bytes);
++ Node->VidMem.logical = gcvNULL;
++ }
++
++ /* Reset. */
++ Node->VidMem.processID = 0;
++
++ /* Don't try to re-free an already freed node. */
++ if ((Node->VidMem.nextFree == gcvNULL)
++ && (Node->VidMem.prevFree == gcvNULL)
++ )
++#endif
++ {
++#if gcdENABLE_VG
++ if (Node->VidMem.kernelVirtual)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "%s(%d) Unmap %x from kernel space.",
++ __FUNCTION__, __LINE__,
++ Node->VidMem.kernelVirtual);
++
++ gcmkVERIFY_OK(
++ gckOS_UnmapPhysical(memory->os,
++ Node->VidMem.kernelVirtual,
++ Node->VidMem.bytes));
++
++ Node->VidMem.kernelVirtual = gcvNULL;
++ }
++#endif
++
++ /* Check if Node is already freed. */
++ if (Node->VidMem.nextFree)
++ {
++ /* Node is alread freed. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ /* Update the number of free bytes. */
++ memory->freeBytes += Node->VidMem.bytes;
++
++ /* Find the next free node. */
++ for (node = Node->VidMem.next;
++ node != gcvNULL && node->VidMem.nextFree == gcvNULL;
++ node = node->VidMem.next) ;
++
++ /* Insert this node in the free list. */
++ Node->VidMem.nextFree = node;
++ Node->VidMem.prevFree = node->VidMem.prevFree;
++
++ Node->VidMem.prevFree->VidMem.nextFree =
++ node->VidMem.prevFree = Node;
++
++ /* Is the next node a free node and not the sentinel? */
++ if ((Node->VidMem.next == Node->VidMem.nextFree)
++ && (Node->VidMem.next->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the next node. */
++ gcmkONERROR(_Merge(memory->os, node = Node));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++
++ /* Is the previous node a free node and not the sentinel? */
++ if ((Node->VidMem.prev == Node->VidMem.prevFree)
++ && (Node->VidMem.prev->VidMem.bytes != 0)
++ )
++ {
++ /* Merge this node with the previous node. */
++ gcmkONERROR(_Merge(memory->os, node = Node->VidMem.prev));
++ gcmkASSERT(node->VidMem.nextFree != node);
++ gcmkASSERT(node->VidMem.prevFree != node);
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(memory->os, memory->mutex));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Node 0x%x is freed.",
++ Node);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ /* Get gckKERNEL object. */
++ kernel = Node->Virtual.kernel;
++
++ /* Verify the gckKERNEL object pointer. */
++ gcmkVERIFY_OBJECT(kernel, gcvOBJ_KERNEL);
++
++#if gcdENABLE_VG
++ if (Node->Virtual.kernelVirtual)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "%s(%d) Unmap %x from kernel space.",
++ __FUNCTION__, __LINE__,
++ Node->Virtual.kernelVirtual);
++
++ gcmkVERIFY_OK(
++ gckOS_UnmapPhysical(kernel->os,
++ Node->Virtual.kernelVirtual,
++ Node->Virtual.bytes));
++
++ Node->Virtual.kernelVirtual = gcvNULL;
++ }
++#endif
++
++ /* Free the virtual memory. */
++ gcmkVERIFY_OK(gckOS_FreePagedMemory(kernel->os,
++ Node->Virtual.physical,
++ Node->Virtual.bytes));
++
++ /* Destroy the gcuVIDMEM_NODE union. */
++ gcmkVERIFY_OK(gckVIDMEM_DestroyVirtual(Node));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mutexAcquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(
++ memory->os, memory->mutex
++ ));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if !gcdPROCESS_ADDRESS_SPACE
++/*******************************************************************************
++**
++** _NeedVirtualMapping
++**
++** Whether setup GPU page table for video node.
++**
++** INPUT:
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** gceCORE Core
++** Id of current GPU.
++**
++** OUTPUT:
++** gctBOOL * NeedMapping
++** A pointer hold the result whether Node should be mapping.
++*/
++static gceSTATUS
++_NeedVirtualMapping(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gcuVIDMEM_NODE_PTR Node,
++ OUT gctBOOL * NeedMapping
++)
++{
++ gceSTATUS status;
++ gctUINT32 phys;
++ gctUINT32 end;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctUINT32 baseAddress;
++ gctUINT32 bytes;
++
++ gcmkHEADER_ARG("Node=0x%X", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(NeedMapping != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Core < gcdMAX_GPU_COUNT);
++
++ if (Node->Virtual.contiguous)
++ {
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ *NeedMapping = gcvFALSE;
++ }
++ else
++#endif
++ {
++ /* Convert logical address into a physical address. */
++ gcmkONERROR(gckOS_UserLogicalToPhysical(
++ Kernel->os, Node->Virtual.logical, &phys
++ ));
++
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++
++ gcmkASSERT(phys >= baseAddress);
++
++ /* Subtract baseAddress to get a GPU address used for programming. */
++ phys -= baseAddress;
++
++ /* If part of region is belong to gcvPOOL_VIRTUAL,
++ ** whole region has to be mapped. */
++ gcmkSAFECASTSIZET(bytes, Node->Virtual.bytes);
++ end = phys + bytes - 1;
++
++ gcmkONERROR(gckHARDWARE_SplitMemory(
++ Kernel->hardware, end, &pool, &offset
++ ));
++
++ *NeedMapping = (pool == gcvPOOL_VIRTUAL);
++ }
++ }
++ else
++ {
++ *NeedMapping = gcvTRUE;
++ }
++
++ gcmkFOOTER_ARG("*NeedMapping=%d", *NeedMapping);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++gcsGPU_MAP_PTR
++_FindGPUMap(
++ IN gcsGPU_MAP_PTR Head,
++ IN gctINT ProcessID
++ )
++{
++ gcsGPU_MAP_PTR map = Head;
++
++ while (map)
++ {
++ if (map->pid == ProcessID)
++ {
++ return map;
++ }
++
++ map = map->next;
++ }
++
++ return gcvNULL;
++}
++
++gcsGPU_MAP_PTR
++_CreateGPUMap(
++ IN gckOS Os,
++ IN gcsGPU_MAP_PTR *Head,
++ IN gcsGPU_MAP_PTR *Tail,
++ IN gctINT ProcessID
++ )
++{
++ gcsGPU_MAP_PTR gpuMap;
++ gctPOINTER pointer = gcvNULL;
++
++ gckOS_Allocate(Os, sizeof(gcsGPU_MAP), &pointer);
++
++ if (pointer == gcvNULL)
++ {
++ return gcvNULL;
++ }
++
++ gpuMap = pointer;
++
++ gckOS_ZeroMemory(pointer, sizeof(gcsGPU_MAP));
++
++ gpuMap->pid = ProcessID;
++
++ if (!*Head)
++ {
++ *Head = *Tail = gpuMap;
++ }
++ else
++ {
++ gpuMap->prev = *Tail;
++ (*Tail)->next = gpuMap;
++ *Tail = gpuMap;
++ }
++
++ return gpuMap;
++}
++
++void
++_DestroyGPUMap(
++ IN gckOS Os,
++ IN gcsGPU_MAP_PTR *Head,
++ IN gcsGPU_MAP_PTR *Tail,
++ IN gcsGPU_MAP_PTR gpuMap
++ )
++{
++
++ if (gpuMap == *Head)
++ {
++ if ((*Head = gpuMap->next) == gcvNULL)
++ {
++ *Tail = gcvNULL;
++ }
++ }
++ else
++ {
++ gpuMap->prev->next = gpuMap->next;
++ if (gpuMap == *Tail)
++ {
++ *Tail = gpuMap->prev;
++ }
++ else
++ {
++ gpuMap->next->prev = gpuMap->prev;
++ }
++ }
++
++ gcmkOS_SAFE_FREE(Os, gpuMap);
++}
++#endif
++
++/*******************************************************************************
++**
++** gckVIDMEM_Lock
++**
++** Lock a video memory node and return its hardware specific address.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable that will hold the hardware specific address.
++**
++** gctUINT32 * PhysicalAddress
++** Pointer to a variable that will hold the bus address of a contiguous
++** video node.
++*/
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address,
++ OUT gctUINT32 * Gid,
++ OUT gctUINT64 * PhysicalAddress
++ )
++{
++ gceSTATUS status;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL locked = gcvFALSE;
++ gckOS os = gcvNULL;
++#if !gcdPROCESS_ADDRESS_SPACE
++ gctBOOL needMapping = gcvFALSE;
++#endif
++ gctUINT32 baseAddress;
++ gctUINT32 physicalAddress;
++ gcuVIDMEM_NODE_PTR node = Node->node;
++
++ gcmkHEADER_ARG("Node=0x%x", Node);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Extract the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ if ((node == gcvNULL)
++ || (node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Node->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /**************************** Video Memory ********************************/
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ gctUINT32 offset;
++
++ if (Cacheable == gcvTRUE)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_REQUEST);
++ }
++
++ /* Increment the lock count. */
++ node->VidMem.locked ++;
++
++ /* Return the physical address of the node. */
++ gcmkSAFECASTSIZET(offset, node->VidMem.offset);
++
++ *Address = node->VidMem.memory->baseAddress
++ + offset
++ + node->VidMem.alignment;
++
++ physicalAddress = *Address;
++
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg == gcvNULL)
++#endif
++ {
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ /* Convert physical to GPU address for old mmu. */
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress));
++ gcmkASSERT(*Address > baseAddress);
++ *Address -= baseAddress;
++ }
++ }
++
++ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(
++ Kernel->os,
++ *Address,
++ Address
++ ));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Locked node 0x%x (%d) @ 0x%08X",
++ node,
++ node->VidMem.locked,
++ *Address);
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++
++ *Gid = node->Virtual.gid;
++
++#if gcdPAGED_MEMORY_CACHEABLE
++ /* Force video memory cacheable. */
++ Cacheable = gcvTRUE;
++#endif
++
++ gcmkONERROR(
++ gckOS_LockPages(os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ Cacheable,
++ &node->Virtual.logical,
++ &node->Virtual.pageCount));
++
++ gcmkONERROR(gckOS_GetPhysicalAddress(
++ os,
++ node->Virtual.logical,
++ &physicalAddress
++ ));
++
++#if gcdENABLE_VG
++ node->Virtual.physicalAddress = physicalAddress;
++#endif
++
++#if !gcdPROCESS_ADDRESS_SPACE
++ /* Increment the lock count. */
++ if (node->Virtual.lockeds[Kernel->core] ++ == 0)
++ {
++ locked = gcvTRUE;
++
++ gcmkONERROR(_NeedVirtualMapping(Kernel, Kernel->core, node, &needMapping));
++
++ if (needMapping == gcvFALSE)
++ {
++ /* Get hardware specific address. */
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(gckVGHARDWARE_ConvertLogical(
++ Kernel->vg->hardware,
++ node->Virtual.logical,
++ gcvTRUE,
++ &node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckHARDWARE_ConvertLogical(
++ Kernel->hardware,
++ node->Virtual.logical,
++ gcvTRUE,
++ &node->Virtual.addresses[Kernel->core]));
++ }
++ }
++ else
++ {
++#if gcdSECURITY
++ gctPHYS_ADDR physicalArrayPhysical;
++ gctPOINTER physicalArrayLogical;
++
++ gcmkONERROR(gckOS_AllocatePageArray(
++ os,
++ node->Virtual.physical,
++ node->Virtual.pageCount,
++ &physicalArrayLogical,
++ &physicalArrayPhysical
++ ));
++
++ gcmkONERROR(gckKERNEL_SecurityMapMemory(
++ Kernel,
++ physicalArrayLogical,
++ node->Virtual.pageCount,
++ &node->Virtual.addresses[Kernel->core]
++ ));
++
++ gcmkONERROR(gckOS_FreeNonPagedMemory(
++ os,
++ 1,
++ physicalArrayPhysical,
++ physicalArrayLogical
++ ));
++#else
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckVGMMU_AllocatePages(Kernel->vg->mmu,
++ node->Virtual.pageCount,
++ &node->Virtual.pageTables[Kernel->core],
++ &node->Virtual.addresses[Kernel->core]));
++ }
++ else
++#endif
++ {
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(
++ gckMMU_AllocatePagesEx(Kernel->mmu,
++ node->Virtual.pageCount,
++ node->Virtual.type,
++ &node->Virtual.pageTables[Kernel->core],
++ &node->Virtual.addresses[Kernel->core]));
++ }
++
++ node->Virtual.lockKernels[Kernel->core] = Kernel;
++
++ /* Map the pages. */
++ gcmkONERROR(
++ gckOS_MapPagesEx(os,
++ Kernel->core,
++ node->Virtual.physical,
++ node->Virtual.pageCount,
++ node->Virtual.addresses[Kernel->core],
++ node->Virtual.pageTables[Kernel->core]));
++
++#if gcdENABLE_VG
++ if (Kernel->core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Kernel->vg->mmu));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(gckMMU_Flush(Kernel->mmu, node->Virtual.type));
++ }
++#endif
++ }
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Mapped virtual node 0x%x to 0x%08X",
++ node,
++ node->Virtual.addresses[Kernel->core]);
++ }
++
++ /* Return hardware address. */
++ *Address = node->Virtual.addresses[Kernel->core];
++#endif
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++
++ *PhysicalAddress = (gctUINT64)physicalAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (locked)
++ {
++ if (node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++ gcmkVERIFY_OK(
++ gckMMU_FreePages(Kernel->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++ node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++
++ /* Unlock the pages. */
++ gcmkVERIFY_OK(
++ gckOS_UnlockPages(os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ node->Virtual.logical
++ ));
++
++ node->Virtual.lockeds[Kernel->core]--;
++ }
++
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_Unlock
++**
++** Unlock a video memory node.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a locked gcuVIDMEM_NODE union.
++**
++** gceSURF_TYPE Type
++** Type of surface to unlock.
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable specifying whether the surface should be
++** unlocked asynchroneously or not.
++**
++** OUTPUT:
++**
++** gctBOOL * Asynchroneous
++** Pointer to a variable receiving the number of bytes used in the
++** command buffer specified by 'Commands'. If gcvNULL, there is no
++** command buffer.
++*/
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ )
++{
++ gceSTATUS status;
++ gckOS os = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++ gcuVIDMEM_NODE_PTR node = Node->node;
++
++ gcmkHEADER_ARG("Node=0x%x Type=%d *Asynchroneous=%d",
++ Node, Type, gcmOPT_VALUE(Asynchroneous));
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Get the gckOS object pointer. */
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Verify the arguments. */
++ if ((node == gcvNULL)
++ || (node->VidMem.memory == gcvNULL)
++ )
++ {
++ /* Invalid object. */
++ gcmkONERROR(gcvSTATUS_INVALID_OBJECT);
++ }
++
++ /* Grab the mutex. */
++ gcmkONERROR(gckOS_AcquireMutex(os, Node->mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /**************************** Video Memory ********************************/
++
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ if (node->VidMem.locked <= 0)
++ {
++ /* The surface was not locked. */
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ if (Asynchroneous != gcvNULL)
++ {
++ /* Schedule an event to sync with GPU. */
++ *Asynchroneous = gcvTRUE;
++ }
++ else
++ {
++ /* Decrement the lock count. */
++ node->VidMem.locked --;
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unlocked node 0x%x (%d)",
++ node,
++ node->VidMem.locked);
++ }
++
++ /*************************** Virtual Memory *******************************/
++
++ else
++ {
++
++
++ if (Asynchroneous == gcvNULL)
++ {
++#if !gcdPROCESS_ADDRESS_SPACE
++ if (node->Virtual.lockeds[Kernel->core] == 0)
++ {
++ status = gcvSTATUS_MEMORY_UNLOCKED;
++ goto OnError;
++ }
++
++ /* Decrement lock count. */
++ -- node->Virtual.lockeds[Kernel->core];
++
++ /* See if we can unlock the resources. */
++ if (node->Virtual.lockeds[Kernel->core] == 0)
++ {
++#if gcdSECURITY
++ if (node->Virtual.addresses[Kernel->core] > 0x80000000)
++ {
++ gcmkONERROR(gckKERNEL_SecurityUnmapMemory(
++ Kernel,
++ node->Virtual.addresses[Kernel->core],
++ node->Virtual.pageCount
++ ));
++ }
++#else
++ /* Free the page table. */
++ if (node->Virtual.pageTables[Kernel->core] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (Kernel->vg != gcvNULL)
++ {
++ gcmkONERROR(
++ gckVGMMU_FreePages(Kernel->vg->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++ else
++#endif
++ {
++ gcmkONERROR(
++ gckMMU_FreePages(Kernel->mmu,
++ node->Virtual.pageTables[Kernel->core],
++ node->Virtual.pageCount));
++ }
++
++ gcmkONERROR(gckOS_UnmapPages(
++ Kernel->os,
++ node->Virtual.pageCount,
++ node->Virtual.addresses[Kernel->core]
++ ));
++
++ /* Mark page table as freed. */
++ node->Virtual.pageTables[Kernel->core] = gcvNULL;
++ node->Virtual.lockKernels[Kernel->core] = gcvNULL;
++ }
++#endif
++ }
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Unmapped virtual node 0x%x from 0x%08X",
++ node, node->Virtual.addresses[Kernel->core]);
++#endif
++
++ }
++
++ else
++ {
++ gcmkONERROR(
++ gckOS_UnlockPages(os,
++ node->Virtual.physical,
++ node->Virtual.bytes,
++ node->Virtual.logical));
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM,
++ "Scheduled unlock for virtual node 0x%x",
++ node);
++
++ /* Schedule the surface to be unlocked. */
++ *Asynchroneous = gcvTRUE;
++ }
++ }
++
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Asynchroneous=%d", gcmOPT_VALUE(Asynchroneous));
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex));
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdPROCESS_ADDRESS_SPACE
++gceSTATUS
++gckVIDMEM_Node_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ OUT gctUINT32 *Address
++ )
++{
++ gceSTATUS status;
++ gckOS os;
++ gcuVIDMEM_NODE_PTR node = Node->node;
++ gcsGPU_MAP_PTR gpuMap;
++ gctPHYS_ADDR physical = gcvNULL;
++ gctUINT32 phys = gcvINVALID_ADDRESS;
++ gctUINT32 processID;
++ gcsLOCK_INFO_PTR lockInfo;
++ gctUINT32 pageCount;
++ gckMMU mmu;
++ gctUINT32 i;
++ gctUINT32_PTR pageTableEntry;
++ gctUINT32 offset = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Node = %x", Node);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ os = Kernel->os;
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu));
++
++ gcmkONERROR(gckOS_AcquireMutex(os, Node->mapMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get map information for current process. */
++ gpuMap = _FindGPUMap(Node->mapHead, processID);
++
++ if (gpuMap == gcvNULL)
++ {
++ gpuMap = _CreateGPUMap(os, &Node->mapHead, &Node->mapTail, processID);
++
++ if (gpuMap == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ lockInfo = &gpuMap->lockInfo;
++
++ if (lockInfo->lockeds[Kernel->core] ++ == 0)
++ {
++ /* Get necessary information. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ phys = node->VidMem.memory->baseAddress
++ + node->VidMem.offset
++ + node->VidMem.alignment;
++
++ /* GPU page table use 4K page. */
++ pageCount = ((phys + node->VidMem.bytes + 4096 - 1) >> 12)
++ - (phys >> 12);
++
++ offset = phys & 0xFFF;
++ }
++ else
++ {
++ pageCount = node->Virtual.pageCount;
++ physical = node->Virtual.physical;
++ }
++
++ /* Allocate pages inside the MMU. */
++ gcmkONERROR(gckMMU_AllocatePages(
++ mmu,
++ pageCount,
++ &lockInfo->pageTables[Kernel->core],
++ &lockInfo->GPUAddresses[Kernel->core]));
++
++ /* Record MMU from which pages are allocated. */
++ lockInfo->lockMmus[Kernel->core] = mmu;
++
++ pageTableEntry = lockInfo->pageTables[Kernel->core];
++
++ /* Fill page table entries. */
++ if (phys != gcvINVALID_ADDRESS)
++ {
++ gctUINT32 address = lockInfo->GPUAddresses[Kernel->core];
++ for (i = 0; i < pageCount; i++)
++ {
++ gckMMU_GetPageEntry(mmu, address, &pageTableEntry);
++ gckMMU_SetPage(mmu, phys & 0xFFFFF000, pageTableEntry);
++ phys += 4096;
++ address += 4096;
++ pageTableEntry += 1;
++ }
++ }
++ else
++ {
++ gctUINT32 address = lockInfo->GPUAddresses[Kernel->core];
++ gcmkASSERT(physical != gcvNULL);
++ gcmkONERROR(gckOS_MapPagesEx(os,
++ Kernel->core,
++ physical,
++ pageCount,
++ address,
++ pageTableEntry));
++ }
++
++ gcmkONERROR(gckMMU_Flush(mmu));
++ }
++
++ *Address = lockInfo->GPUAddresses[Kernel->core] + offset;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mapMutex));
++ acquired = gcvFALSE;
++
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mapMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_NODE_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctUINT32 ProcessID
++ )
++{
++ gceSTATUS status;
++ gcsGPU_MAP_PTR gpuMap;
++ gcsLOCK_INFO_PTR lockInfo;
++ gckMMU mmu;
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 pageCount;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%08X, Node = %x, ProcessID=%d",
++ Kernel, Node, ProcessID);
++
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Node != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Node->mapMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Get map information for current process. */
++ gpuMap = _FindGPUMap(Node->mapHead, ProcessID);
++
++ if (gpuMap == gcvNULL)
++ {
++ /* No mapping for this process. */
++ gcmkONERROR(gcvSTATUS_INVALID_DATA);
++ }
++
++ lockInfo = &gpuMap->lockInfo;
++
++ if (--lockInfo->lockeds[Kernel->core] == 0)
++ {
++ node = Node->node;
++
++ /* Get necessary information. */
++ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ {
++ gctUINT32 phys = node->VidMem.memory->baseAddress
++ + node->VidMem.offset
++ + node->VidMem.alignment;
++
++ /* GPU page table use 4K page. */
++ pageCount = ((phys + node->VidMem.bytes + 4096 - 1) >> 12)
++ - (phys >> 12);
++ }
++ else
++ {
++ pageCount = node->Virtual.pageCount;
++ }
++
++ /* Get MMU which allocates pages. */
++ mmu = lockInfo->lockMmus[Kernel->core];
++
++ /* Free virtual spaces in page table. */
++ gcmkVERIFY_OK(gckMMU_FreePagesEx(
++ mmu,
++ lockInfo->GPUAddresses[Kernel->core],
++ pageCount
++ ));
++
++ _DestroyGPUMap(Kernel->os, &Node->mapHead, &Node->mapTail, gpuMap);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Node->mapMutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Node->mapMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckVIDMEM_HANDLE_Allocate
++**
++** Allocate a handle for a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gckVIDMEM_NODE Node
++** Pointer to a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Handle
++** Pointer to a variable receiving a handle represent this
++** gckVIDMEM_NODE in userspace.
++*/
++static gceSTATUS
++gckVIDMEM_HANDLE_Allocate(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ OUT gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID = 0;
++ gctPOINTER pointer = gcvNULL;
++ gctPOINTER handleDatabase = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctUINT32 handle = 0;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gckOS os = Kernel->os;
++
++ gcmkHEADER_ARG("Kernel=0x%X, Node=0x%X", Kernel, Node);
++
++ gcmkVERIFY_OBJECT(os, gcvOBJ_OS);
++
++ /* Allocate a gckVIDMEM_HANDLE object. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsVIDMEM_HANDLE), &pointer));
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsVIDMEM_HANDLE)));
++
++ handleObject = pointer;
++
++ gcmkONERROR(gckOS_AtomConstruct(os, &handleObject->reference));
++
++ /* Set default reference count to 1. */
++ gckOS_AtomSet(os, handleObject->reference, 1);
++
++ gcmkVERIFY_OK(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel,
++ processID,
++ &handleDatabase,
++ &mutex));
++
++ /* Allocate a handle for this object. */
++ gcmkONERROR(
++ gckKERNEL_AllocateIntegerId(handleDatabase, handleObject, &handle));
++
++ handleObject->node = Node;
++ handleObject->handle = handle;
++
++ *Handle = handle;
++
++ gcmkFOOTER_ARG("*Handle=%d", *Handle);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (handleObject != gcvNULL)
++ {
++ if (handleObject->reference != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, handleObject->reference));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, handleObject));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckVIDMEM_NODE_Reference(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node
++ )
++{
++ gctINT32 oldValue;
++ gcmkHEADER_ARG("Kernel=0x%X Node=0x%X", Kernel, Node);
++
++ gckOS_AtomIncrement(Kernel->os, Node->reference, &oldValue);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_Reference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gctPOINTER database = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctINT32 oldValue = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Handle=%d PrcoessID=%d", Handle, ProcessID);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel, ProcessID, &database, &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Translate handle to gckVIDMEM_HANDLE object. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject));
++
++ /* Increase the reference count. */
++ gckOS_AtomIncrement(Kernel->os, handleObject->reference, &oldValue);
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ )
++{
++ gceSTATUS status;
++ gctPOINTER handleDatabase = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctINT32 oldValue = 0;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Handle=%d PrcoessID=%d", Handle, ProcessID);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel,
++ ProcessID,
++ &handleDatabase,
++ &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Translate handle to gckVIDMEM_HANDLE. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(handleDatabase, Handle, (gctPOINTER *)&handleObject));
++
++ gckOS_AtomDecrement(Kernel->os, handleObject->reference, &oldValue);
++
++ if (oldValue == 1)
++ {
++ /* Remove handle from database if this is the last reference. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(handleDatabase, Handle));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ if (oldValue == 1)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, handleObject->reference));
++ gcmkOS_SAFE_FREE(Kernel->os, handleObject);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_LookupAndReference(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER database = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctUINT32 processID = 0;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle);
++
++ gckOS_GetProcessID(&processID);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel, processID, &database, &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Translate handle to gckVIDMEM_HANDLE object. */
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject));
++
++ /* Get gckVIDMEM_NODE object. */
++ node = handleObject->node;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ /* Reference this gckVIDMEM_NODE object. */
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Reference(Kernel, node));
++
++ /* Return result. */
++ *Node = node;
++
++ gcmkFOOTER_ARG("*Node=%d", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_HANDLE_Lookup(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle,
++ OUT gckVIDMEM_NODE * Node
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_HANDLE handleObject = gcvNULL;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER database = gcvNULL;
++ gctPOINTER mutex = gcvNULL;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X ProcessID=%d Handle=%d",
++ Kernel, ProcessID, Handle);
++
++ gcmkONERROR(
++ gckKERNEL_FindHandleDatbase(Kernel, ProcessID, &database, &mutex));
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject));
++
++ node = handleObject->node;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ *Node = node;
++
++ gcmkFOOTER_ARG("*Node=%d", *Node);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_Allocate
++**
++** Allocate a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcuVIDMEM_NODE_PTR Node
++** Pointer to a gcuVIDMEM_NODE union.
++**
++** OUTPUT:
++**
++** gctUINT32 * Handle
++** Pointer to a variable receiving a handle represent this
++** gckVIDMEM_NODE in userspace.
++*/
++gceSTATUS
++gckVIDMEM_NODE_Allocate(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR VideoNode,
++ IN gceSURF_TYPE Type,
++ IN gcePOOL Pool,
++ IN gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER pointer = gcvNULL;
++ gctUINT32 handle = 0;
++ gckOS os = Kernel->os;
++
++ gcmkHEADER_ARG("Kernel=0x%X VideoNode=0x%X", Kernel, VideoNode);
++
++ /* Construct a node. */
++ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsVIDMEM_NODE), &pointer));
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsVIDMEM_NODE)));
++
++ node = pointer;
++
++ node->node = VideoNode;
++ node->type = Type;
++ node->pool = Pool;
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckOS_CreateMutex(os, &node->mapMutex));
++#endif
++
++ gcmkONERROR(gckOS_AtomConstruct(os, &node->reference));
++
++ gcmkONERROR(gckOS_CreateMutex(os, &node->mutex));
++
++ /* Reference is 1 by default . */
++ gckVIDMEM_NODE_Reference(Kernel, node);
++
++ /* Create a handle to represent this node. */
++ gcmkONERROR(gckVIDMEM_HANDLE_Allocate(Kernel, node, &handle));
++
++ *Handle = handle;
++
++ gcmkFOOTER_ARG("*Handle=%d", *Handle);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (node != gcvNULL)
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ if (node->mapMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, node->mapMutex));
++ }
++#endif
++
++ if (node->mutex)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(os, node->mutex));
++ }
++
++ if (node->reference != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_AtomDestroy(os, node->reference));
++ }
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckVIDMEM_NODE_Dereference(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node
++ )
++{
++ gctINT32 oldValue = 0;
++ gctPOINTER database = Kernel->db->nameDatabase;
++ gctPOINTER mutex = Kernel->db->nameDatabaseMutex;
++
++ gcmkHEADER_ARG("Kernel=0x%X Node=0x%X", Kernel, Node);
++
++ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++
++ gcmkVERIFY_OK(gckOS_AtomDecrement(Kernel->os, Node->reference, &oldValue));
++
++ if (oldValue == 1 && Node->name)
++ {
++ /* Free name if exists. */
++ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Node->name));
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++
++ if (oldValue == 1)
++ {
++ /* Free gcuVIDMEM_NODE. */
++ gcmkVERIFY_OK(gckVIDMEM_Free(Kernel, Node->node));
++ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Node->reference));
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Node->mapMutex));
++#endif
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Node->mutex));
++ gcmkOS_SAFE_FREE(Kernel->os, Node);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_Name
++**
++** Naming a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Handle
++** Handle to a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Name
++** Pointer to a variable receiving a name which can be pass to another
++** process.
++*/
++gceSTATUS
++gckVIDMEM_NODE_Name(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ IN gctUINT32 * Name
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctUINT32 name = 0;
++ gctUINT32 processID = 0;
++ gctPOINTER database = Kernel->db->nameDatabase;
++ gctPOINTER mutex = Kernel->db->nameDatabaseMutex;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL referenced = gcvFALSE;
++ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle);
++
++ gcmkONERROR(gckOS_GetProcessID(&processID));
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(gckVIDMEM_HANDLE_LookupAndReference(Kernel, Handle, &node));
++ referenced = gcvTRUE;
++
++ if (node->name == 0)
++ {
++ /* Name this node. */
++ gcmkONERROR(gckKERNEL_AllocateIntegerId(database, node, &name));
++ node->name = name;
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++
++ if(node)
++ {
++ *Name = node->name;
++ }
++
++ gcmkFOOTER_ARG("*Name=%d", *Name);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (referenced)
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++ }
++
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_Import
++**
++** Import a gckVIDMEM_NODE object.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Name
++** Name of a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Handle
++** Pointer to a variable receiving a handle represent this
++** gckVIDMEM_NODE in userspace.
++*/
++gceSTATUS
++gckVIDMEM_NODE_Import(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Name,
++ IN gctUINT32 * Handle
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctPOINTER database = Kernel->db->nameDatabase;
++ gctPOINTER mutex = Kernel->db->nameDatabaseMutex;
++ gctBOOL acquired = gcvFALSE;
++ gctBOOL referenced = gcvFALSE;
++
++ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name);
++
++ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ /* Lookup in database to get the node. */
++ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, (gctPOINTER *)&node));
++
++ /* Reference the node. */
++ gcmkONERROR(gckVIDMEM_NODE_Reference(Kernel, node));
++ referenced = gcvTRUE;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ acquired = gcvFALSE;
++
++ /* Allocate a handle for current process. */
++ gcmkONERROR(gckVIDMEM_HANDLE_Allocate(Kernel, node, Handle));
++
++ gcmkFOOTER_ARG("*Handle=%d", *Handle);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (referenced)
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++ }
++
++ if (acquired)
++ {
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++typedef struct _gcsVIDMEM_NODE_FDPRIVATE
++{
++ gcsFDPRIVATE base;
++ gckKERNEL kernel;
++ gckVIDMEM_NODE node;
++}
++gcsVIDMEM_NODE_FDPRIVATE;
++
++
++static gctINT
++_ReleaseFdPrivate(
++ gcsFDPRIVATE_PTR FdPrivate
++ )
++{
++ /* Cast private info. */
++ gcsVIDMEM_NODE_FDPRIVATE * private = (gcsVIDMEM_NODE_FDPRIVATE *) FdPrivate;
++
++ gckVIDMEM_NODE_Dereference(private->kernel, private->node);
++ gckOS_Free(private->kernel->os, private);
++
++ return 0;
++}
++
++/*******************************************************************************
++**
++** gckVIDMEM_NODE_GetFd
++**
++** Attach a gckVIDMEM_NODE object to a native fd.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctUINT32 Handle
++** Handle to a gckVIDMEM_NODE object.
++**
++** OUTPUT:
++**
++** gctUINT32 * Fd
++** Pointer to a variable receiving a native fd from os.
++*/
++gceSTATUS
++gckVIDMEM_NODE_GetFd(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Handle,
++ OUT gctINT * Fd
++ )
++{
++ gceSTATUS status;
++ gckVIDMEM_NODE node = gcvNULL;
++ gctBOOL referenced = gcvFALSE;
++ gcsVIDMEM_NODE_FDPRIVATE * fdPrivate = gcvNULL;
++ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle);
++
++ /* Query and reference handle. */
++ gcmkONERROR(gckVIDMEM_HANDLE_LookupAndReference(Kernel, Handle, &node));
++ referenced = gcvTRUE;
++
++ /* Allocate memory for private info. */
++ gcmkONERROR(gckOS_Allocate(
++ Kernel->os,
++ gcmSIZEOF(gcsVIDMEM_NODE_FDPRIVATE),
++ (gctPOINTER *)&fdPrivate
++ ));
++
++ fdPrivate->base.release = _ReleaseFdPrivate;
++ fdPrivate->kernel = Kernel;
++ fdPrivate->node = node;
++
++ /* Allocated fd owns a reference. */
++ gcmkONERROR(gckOS_GetFd("vidmem", &fdPrivate->base, Fd));
++
++ gcmkFOOTER_ARG("*Fd=%d", *Fd);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (referenced)
++ {
++ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node));
++ }
++
++ if (fdPrivate)
++ {
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, fdPrivate));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h 2016-06-19 22:11:55.233144731 +0200
+@@ -0,0 +1,5520 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_base_h_
++#define __gc_hal_base_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++#include "gc_hal_dump.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckOS * gckOS;
++typedef struct _gcoHAL * gcoHAL;
++typedef struct _gcoOS * gcoOS;
++typedef struct _gco2D * gco2D;
++typedef struct gcsATOM * gcsATOM_PTR;
++
++#if gcdENABLE_3D
++typedef struct _gco3D * gco3D;
++typedef struct _gcoCL * gcoCL;
++typedef struct _gcsFAST_FLUSH * gcsFAST_FLUSH_PTR;
++#endif
++
++typedef struct _gcoSURF * gcoSURF;
++typedef struct _gcsSURF_INFO * gcsSURF_INFO_PTR;
++typedef struct _gcsSURF_NODE * gcsSURF_NODE_PTR;
++typedef struct _gcsSURF_FORMAT_INFO * gcsSURF_FORMAT_INFO_PTR;
++typedef struct _gcsPOINT * gcsPOINT_PTR;
++typedef struct _gcsSIZE * gcsSIZE_PTR;
++typedef struct _gcsRECT * gcsRECT_PTR;
++typedef struct _gcsBOUNDARY * gcsBOUNDARY_PTR;
++typedef struct _gcoDUMP * gcoDUMP;
++typedef struct _gcoHARDWARE * gcoHARDWARE;
++typedef union _gcuVIDMEM_NODE * gcuVIDMEM_NODE_PTR;
++typedef struct _gcsVIDMEM_NODE * gckVIDMEM_NODE;
++
++#if gcdENABLE_VG
++typedef struct _gcoVG * gcoVG;
++typedef struct _gcsCOMPLETION_SIGNAL * gcsCOMPLETION_SIGNAL_PTR;
++typedef struct _gcsCONTEXT_MAP * gcsCONTEXT_MAP_PTR;
++#else
++typedef void * gcoVG;
++#endif
++
++#if gcdSYNC
++typedef struct _gcoFENCE * gcoFENCE;
++typedef struct _gcsSYNC_CONTEXT * gcsSYNC_CONTEXT_PTR;
++#endif
++
++#if defined(ANDROID)
++typedef struct _gcoOS_SymbolsList gcoOS_SymbolsList;
++#endif
++
++/******************************************************************************\
++******************************* Process local storage *************************
++\******************************************************************************/
++
++typedef struct _gcsPLS * gcsPLS_PTR;
++
++#if gcdENABLE_3D
++/******************************************************************************
++**
++** Patch defines which should be moved to dedicate file later
++**
++** !!! ALWAYS ADD new ID in the TAIL, otherwise will break exising TRACE FILE
++*******************************************************************************/
++typedef enum _gcePATCH_ID
++{
++ gcvPATCH_NOTINIT = -1,
++ gcvPATCH_INVALID = 0,
++
++#if gcdDEBUG_OPTION
++ gcvPATCH_DEBUG,
++#endif
++
++ gcvPATCH_GTFES30,
++ gcvPATCH_CTGL11,
++ gcvPATCH_CTGL20,
++ gcvPATCH_GLBM11,
++ gcvPATCH_GLBM21,
++ gcvPATCH_GLBM25,
++ gcvPATCH_GLBM27,
++ gcvPATCH_GLBMGUI,
++ gcvPATCH_GFXBENCH,
++ gcvPATCH_ANTUTU, /* Antutu 3.x */
++ gcvPATCH_ANTUTU4X, /* Antutu 4.x */
++ gcvPATCH_QUADRANT,
++ gcvPATCH_GPUBENCH,
++ gcvPATCH_DUOKAN,
++ gcvPATCH_GLOFTSXHM,
++ gcvPATCH_XRUNNER,
++ gcvPATCH_BUSPARKING3D,
++ gcvPATCH_SIEGECRAFT,
++ gcvPATCH_PREMIUM,
++ gcvPATCH_RACEILLEGAL,
++ gcvPATCH_MEGARUN,
++ gcvPATCH_BMGUI,
++ gcvPATCH_NENAMARK,
++ gcvPATCH_NENAMARK2,
++ gcvPATCH_FISHNOODLE,
++ gcvPATCH_MM06,
++ gcvPATCH_MM07,
++ gcvPATCH_BM21,
++ gcvPATCH_SMARTBENCH,
++ gcvPATCH_JPCT,
++ gcvPATCH_NEOCORE,
++ gcvPATCH_RTESTVA,
++ gcvPATCH_NBA2013,
++ gcvPATCH_BARDTALE,
++ gcvPATCH_F18,
++ gcvPATCH_CARPARK,
++ gcvPATCH_CARCHALLENGE,
++ gcvPATCH_HEROESCALL,
++ gcvPATCH_GLOFTF3HM,
++ gcvPATCH_CRAZYRACING,
++ gcvPATCH_FIREFOX,
++ gcvPATCH_CHROME,
++ gcvPATCH_MONOPOLY,
++ gcvPATCH_SNOWCOLD,
++ gcvPATCH_BM3,
++ gcvPATCH_BASEMARKX,
++ gcvPATCH_DEQP,
++ gcvPATCH_SF4,
++ gcePATCH_MGOHEAVEN2,
++ gcePATCH_SILIBILI,
++ gcePATCH_ELEMENTSDEF,
++ gcePATCH_GLOFTKRHM,
++ gcvPATCH_OCLCTS,
++ gcvPATCH_A8HP,
++ gcvPATCH_A8CN,
++ gcvPATCH_WISTONESG,
++ gcvPATCH_SPEEDRACE,
++ gcvPATCH_FSBHAWAIIF,
++ gcvPATCH_AIRNAVY,
++ gcvPATCH_F18NEW,
++ gcvPATCH_CKZOMBIES2,
++ gcvPATCH_EADGKEEPER,
++ gcvPATCH_BASEMARK2V2,
++ gcvPATCH_RIPTIDEGP2,
++ gcvPATCH_OESCTS,
++ gcvPATCH_GANGSTAR,
++ gcvPATCH_WHRKYZIXOVAN,
++ gcvPATCH_NAMESGAS,
++ gcvPATCH_AFTERBURNER,
++ gcvPATCH_UIMARK,
++ gcvPATCH_FM_OES_PLAYER,
++ gcvPATCH_SUMSUNG_BENCH,
++ gcvPATCH_ROCKSTAR_MAXPAYNE,
++ gcvPATCH_TITANPACKING,
++ gcvPATCH_BASEMARKOSIICN,
++ gcvPATCH_FRUITNINJA,
++#if defined(ANDROID)
++ gcePATCH_ANDROID_CTS_MEDIA_PRESENTATIONTIME,
++#endif
++ gcvPATCH_ANDROID_COMPOSITOR,
++ gcvPATCH_CTS_TEXTUREVIEW,
++ gcvPATCH_WATER2_CHUKONG,
++
++ gcvPATCH_COUNT
++} gcePATCH_ID;
++#endif /* gcdENABLE_3D */
++
++typedef void (* gctPLS_DESTRUCTOR) (
++ gcsPLS_PTR
++ );
++
++typedef struct _gcsPLS
++{
++ /* Global objects. */
++ gcoOS os;
++ gcoHAL hal;
++
++ /* Internal memory pool. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctPOINTER internalLogical;
++
++ /* External memory pool. */
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctPOINTER externalLogical;
++
++ /* Contiguous memory pool. */
++ gctSIZE_T contiguousSize;
++ gctPHYS_ADDR contiguousPhysical;
++ gctPOINTER contiguousLogical;
++
++ /* EGL-specific process-wide objects. */
++ gctPOINTER eglDisplayInfo;
++ gctPOINTER eglSurfaceInfo;
++ gceSURF_FORMAT eglConfigFormat;
++
++ /* PLS reference count */
++ gcsATOM_PTR reference;
++
++ /* PorcessID of the constrcutor process */
++ gctUINT32 processID;
++
++ /* ThreadID of the constrcutor process. */
++ gctSIZE_T threadID;
++ /* Flag for calling module destructor. */
++ gctBOOL exiting;
++
++ gctBOOL bNeedSupportNP2Texture;
++
++ gctPLS_DESTRUCTOR destructor;
++ /* Mutex to guard PLS access. currently it's for EGL.
++ ** We can use this mutex for every PLS access.
++ */
++ gctPOINTER accessLock;
++#if gcdENABLE_3D
++ /* Global patchID to overwrite the detection */
++ gcePATCH_ID patchID;
++#endif
++}
++gcsPLS;
++
++extern gcsPLS gcPLS;
++
++#if gcdENABLE_3D
++#define gcPLS_INITIALIZER \
++{ \
++ gcvNULL, /* gcoOS object. */ \
++ gcvNULL, /* gcoHAL object. */ \
++ 0, /* internalSize */ \
++ gcvNULL, /* internalPhysical */ \
++ gcvNULL, /* internalLogical */ \
++ 0, /* externalSize */ \
++ gcvNULL, /* externalPhysical */ \
++ gcvNULL, /* externalLogical */ \
++ 0, /* contiguousSize */ \
++ gcvNULL, /* contiguousPhysical */ \
++ gcvNULL, /* contiguousLogical */ \
++ gcvNULL, /* eglDisplayInfo */ \
++ gcvNULL, /* eglSurfaceInfo */ \
++ gcvSURF_A8R8G8B8,/* eglConfigFormat */ \
++ gcvNULL, /* reference */ \
++ 0, /* processID */ \
++ 0, /* threadID */ \
++ gcvFALSE, /* exiting */ \
++ gcvFALSE, /* Special flag for NP2 texture. */ \
++ gcvNULL, /* destructor */ \
++ gcvNULL, /* accessLock */ \
++ gcvPATCH_NOTINIT,/* global patchID */ \
++}
++#else
++#define gcPLS_INITIALIZER \
++{ \
++ gcvNULL, /* gcoOS object. */ \
++ gcvNULL, /* gcoHAL object. */ \
++ 0, /* internalSize */ \
++ gcvNULL, /* internalPhysical */ \
++ gcvNULL, /* internalLogical */ \
++ 0, /* externalSize */ \
++ gcvNULL, /* externalPhysical */ \
++ gcvNULL, /* externalLogical */ \
++ 0, /* contiguousSize */ \
++ gcvNULL, /* contiguousPhysical */ \
++ gcvNULL, /* contiguousLogical */ \
++ gcvNULL, /* eglDisplayInfo */ \
++ gcvNULL, /* eglSurfaceInfo */ \
++ gcvSURF_A8R8G8B8,/* eglConfigFormat */ \
++ gcvNULL, /* reference */ \
++ 0, /* processID */ \
++ 0, /* threadID */ \
++ gcvFALSE, /* exiting */ \
++ gcvFALSE, /* Special flag for NP2 texture. */ \
++ gcvNULL, /* destructor */ \
++ gcvNULL, /* accessLock */ \
++}
++#endif
++
++/******************************************************************************\
++******************************* Thread local storage *************************
++\******************************************************************************/
++
++typedef struct _gcsTLS * gcsTLS_PTR;
++
++typedef void (* gctTLS_DESTRUCTOR) (
++ gcsTLS_PTR
++ );
++
++typedef struct _gcsTLS
++{
++ gceHARDWARE_TYPE currentType;
++
++ /* Current 3D hardwre of this thread */
++ gcoHARDWARE currentHardware;
++
++ /* Default 3D hardware of this thread */
++ gcoHARDWARE defaultHardware;
++
++ /* Only for separated 3D and 2D */
++ gcoHARDWARE hardware2D;
++#if gcdENABLE_VG
++ gcoVGHARDWARE vg;
++ gcoVG engineVG;
++#endif /* gcdENABLE_VG */
++#if gcdENABLE_3D
++ gco3D engine3D;
++#endif
++#if gcdENABLE_2D
++ gco2D engine2D;
++#endif
++
++ /*thread data */
++ gctPOINTER context;
++ /* ES(including es1 and es2) client driver context which is current state */
++ gctPOINTER esClientCtx;
++ gctTLS_DESTRUCTOR destructor;
++
++ gctBOOL copied;
++
++ /* libGAL.so handle */
++ gctHANDLE handle;
++
++ /* If true, do not releas 2d engine and hardware in hal layer */
++ gctBOOL release2DUpper;
++}
++gcsTLS;
++
++/******************************************************************************\
++********************************* Enumerations *********************************
++\******************************************************************************/
++
++typedef enum _gcePLS_VALUE
++{
++ gcePLS_VALUE_EGL_DISPLAY_INFO,
++ gcePLS_VALUE_EGL_SURFACE_INFO,
++ gcePLS_VALUE_EGL_CONFIG_FORMAT_INFO,
++ gcePLS_VALUE_EGL_DESTRUCTOR_INFO,
++}
++gcePLS_VALUE;
++
++/* Video memory pool type. */
++typedef enum _gcePOOL
++{
++ gcvPOOL_UNKNOWN = 0,
++ gcvPOOL_DEFAULT,
++ gcvPOOL_LOCAL,
++ gcvPOOL_LOCAL_INTERNAL,
++ gcvPOOL_LOCAL_EXTERNAL,
++ gcvPOOL_UNIFIED,
++ gcvPOOL_SYSTEM,
++ gcvPOOL_VIRTUAL,
++ gcvPOOL_USER,
++ gcvPOOL_CONTIGUOUS,
++
++ gcvPOOL_NUMBER_OF_POOLS
++}
++gcePOOL;
++
++#if gcdENABLE_3D
++/* Blending functions. */
++typedef enum _gceBLEND_FUNCTION
++{
++ gcvBLEND_ZERO,
++ gcvBLEND_ONE,
++ gcvBLEND_SOURCE_COLOR,
++ gcvBLEND_INV_SOURCE_COLOR,
++ gcvBLEND_SOURCE_ALPHA,
++ gcvBLEND_INV_SOURCE_ALPHA,
++ gcvBLEND_TARGET_COLOR,
++ gcvBLEND_INV_TARGET_COLOR,
++ gcvBLEND_TARGET_ALPHA,
++ gcvBLEND_INV_TARGET_ALPHA,
++ gcvBLEND_SOURCE_ALPHA_SATURATE,
++ gcvBLEND_CONST_COLOR,
++ gcvBLEND_INV_CONST_COLOR,
++ gcvBLEND_CONST_ALPHA,
++ gcvBLEND_INV_CONST_ALPHA,
++}
++gceBLEND_FUNCTION;
++
++/* Blending modes. */
++typedef enum _gceBLEND_MODE
++{
++ gcvBLEND_ADD,
++ gcvBLEND_SUBTRACT,
++ gcvBLEND_REVERSE_SUBTRACT,
++ gcvBLEND_MIN,
++ gcvBLEND_MAX,
++}
++gceBLEND_MODE;
++
++/* Depth modes. */
++typedef enum _gceDEPTH_MODE
++{
++ gcvDEPTH_NONE,
++ gcvDEPTH_Z,
++ gcvDEPTH_W,
++}
++gceDEPTH_MODE;
++#endif /* gcdENABLE_3D */
++
++#if (gcdENABLE_3D || gcdENABLE_VG)
++/* API flags. */
++typedef enum _gceAPI
++{
++ gcvAPI_D3D = 1,
++ gcvAPI_OPENGL_ES11,
++ gcvAPI_OPENGL_ES20,
++ gcvAPI_OPENGL_ES30,
++ gcvAPI_OPENGL,
++ gcvAPI_OPENVG,
++ gcvAPI_OPENCL,
++}
++gceAPI;
++#endif
++
++
++typedef enum _gceWHERE
++{
++ gcvWHERE_COMMAND,
++ gcvWHERE_RASTER,
++ gcvWHERE_PIXEL,
++}
++gceWHERE;
++
++typedef enum _gceHOW
++{
++ gcvHOW_SEMAPHORE = 0x1,
++ gcvHOW_STALL = 0x2,
++ gcvHOW_SEMAPHORE_STALL = 0x3,
++}
++gceHOW;
++
++typedef enum _gceSignalHandlerType
++{
++ gcvHANDLE_SIGFPE_WHEN_SIGNAL_CODE_IS_0 = 0x1,
++}
++gceSignalHandlerType;
++
++/* gcsHAL_Limits*/
++typedef struct _gcsHAL_LIMITS
++{
++ /* chip info */
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++ gctUINT32 featureCount;
++ gctUINT32 *chipFeatures;
++
++ /* target caps */
++ gctUINT32 maxWidth;
++ gctUINT32 maxHeight;
++ gctUINT32 multiTargetCount;
++ gctUINT32 maxSamples;
++
++}gcsHAL_LIMITS;
++
++/******************************************************************************\
++*********** Generic Memory Allocation Optimization Using Containers ************
++\******************************************************************************/
++
++/* Generic container definition. */
++typedef struct _gcsCONTAINER_LINK * gcsCONTAINER_LINK_PTR;
++typedef struct _gcsCONTAINER_LINK
++{
++ /* Points to the next container. */
++ gcsCONTAINER_LINK_PTR next;
++}
++gcsCONTAINER_LINK;
++
++typedef struct _gcsCONTAINER_RECORD * gcsCONTAINER_RECORD_PTR;
++typedef struct _gcsCONTAINER_RECORD
++{
++ gcsCONTAINER_RECORD_PTR prev;
++ gcsCONTAINER_RECORD_PTR next;
++}
++gcsCONTAINER_RECORD;
++
++typedef struct _gcsCONTAINER * gcsCONTAINER_PTR;
++typedef struct _gcsCONTAINER
++{
++ gctUINT containerSize;
++ gctUINT recordSize;
++ gctUINT recordCount;
++ gcsCONTAINER_LINK_PTR containers;
++ gcsCONTAINER_RECORD freeList;
++ gcsCONTAINER_RECORD allocList;
++}
++gcsCONTAINER;
++
++gceSTATUS
++gcsCONTAINER_Construct(
++ IN gcsCONTAINER_PTR Container,
++ gctUINT RecordsPerContainer,
++ gctUINT RecordSize
++ );
++
++gceSTATUS
++gcsCONTAINER_Destroy(
++ IN gcsCONTAINER_PTR Container
++ );
++
++gceSTATUS
++gcsCONTAINER_AllocateRecord(
++ IN gcsCONTAINER_PTR Container,
++ OUT gctPOINTER * Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeRecord(
++ IN gcsCONTAINER_PTR Container,
++ IN gctPOINTER Record
++ );
++
++gceSTATUS
++gcsCONTAINER_FreeAll(
++ IN gcsCONTAINER_PTR Container
++ );
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++/* Construct a new gcoHAL object. */
++gceSTATUS
++gcoHAL_ConstructEx(
++ IN gctPOINTER Context,
++ IN gcoOS Os,
++ OUT gcoHAL * Hal
++ );
++
++/* Destroy an gcoHAL object. */
++gceSTATUS
++gcoHAL_DestroyEx(
++ IN gcoHAL Hal
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoHAL_Construct(
++ IN gctPOINTER Context,
++ IN gcoOS Os,
++ OUT gcoHAL * Hal
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoHAL_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Get HAL options */
++gceSTATUS
++gcoHAL_GetOption(
++ IN gcoHAL Hal,
++ IN gceOPTION Option
++ );
++
++gceSTATUS
++gcoHAL_FrameInfoOps(
++ IN gcoHAL Hal,
++ IN gceFRAMEINFO FrameInfo,
++ IN gceFRAMEINFO_OP Op,
++ IN OUT gctUINT * Val
++ );
++
++
++gceSTATUS
++gcoHAL_GetHardware(
++ IN gcoHAL Hal,
++ OUT gcoHARDWARE* Hw
++ );
++
++#if gcdENABLE_2D
++/* Get pointer to gco2D object. */
++gceSTATUS
++gcoHAL_Get2DEngine(
++ IN gcoHAL Hal,
++ OUT gco2D * Engine
++ );
++#endif
++
++#if gcdENABLE_3D
++gceSTATUS
++gcoHAL_GetSpecialHintData(
++ IN gcoHAL Hal,
++ OUT gctINT * Hint
++ );
++/*
++** Deprecated(Don't use it), keep it here for external library(libgcu.so)
++*/
++gceSTATUS
++gcoHAL_Get3DEngine(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++#endif /* gcdEANBLE_3D */
++
++
++gceSTATUS
++gcoHAL_GetProductName(
++ IN gcoHAL Hal,
++ OUT gctSTRING *ProductName
++ );
++
++gceSTATUS
++gcoHAL_SetFscaleValue(
++ IN gctUINT FscaleValue
++ );
++
++gceSTATUS
++gcoHAL_GetFscaleValue(
++ OUT gctUINT * FscaleValue,
++ OUT gctUINT * MinFscaleValue,
++ OUT gctUINT * MaxFscaleValue
++ );
++
++gceSTATUS
++gcoHAL_SetBltNP2Texture(
++ gctBOOL enable
++ );
++
++gceSTATUS
++gcoHAL_NameVideoMemory(
++ IN gctUINT32 Handle,
++ OUT gctUINT32 * Name
++ );
++
++gceSTATUS
++gcoHAL_ImportVideoMemory(
++ IN gctUINT32 Name,
++ OUT gctUINT32 * Handle
++ );
++
++gceSTATUS
++gcoHAL_GetVideoMemoryFd(
++ IN gctUINT32 Handle,
++ OUT gctINT * Fd
++ );
++
++/* Verify whether the specified feature is available in hardware. */
++gceSTATUS
++gcoHAL_IsFeatureAvailable(
++ IN gcoHAL Hal,
++ IN gceFEATURE Feature
++ );
++
++gceSTATUS
++gcoHAL_IsSwwaNeeded(
++ IN gcoHAL Hal,
++ IN gceSWWA Swwa
++ );
++
++gceSTATUS
++gcoHAL_IsFeatureAvailable1(
++ IN gcoHAL Hal,
++ IN gceFEATURE Feature
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gcoHAL_QueryChipIdentity(
++ IN gcoHAL Hal,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++/* Query the minor features of the hardware. */
++gceSTATUS gcoHAL_QueryChipMinorFeatures(
++ IN gcoHAL Hal,
++ OUT gctUINT32* NumFeatures,
++ OUT gctUINT32* ChipMinorFeatures
++ );
++
++gctINT32
++gcoOS_EndRecordAllocation(void);
++void
++gcoOS_RecordAllocation(void);
++void
++gcoOS_AddRecordAllocation(gctSIZE_T Size);
++
++/* Query the amount of video memory. */
++gceSTATUS
++gcoHAL_QueryVideoMemory(
++ IN gcoHAL Hal,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Map video memory. */
++gceSTATUS
++gcoHAL_MapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap video memory. */
++gceSTATUS
++gcoHAL_UnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Schedule an unmap of a buffer mapped through its physical address. */
++gceSTATUS
++gcoHAL_ScheduleUnmapMemory(
++ IN gcoHAL Hal,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T NumberOfBytes,
++ IN gctPOINTER Logical
++ );
++
++/* Allocate video memory. */
++gceSTATUS
++gcoOS_AllocateVideoMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN gctBOOL InCacheable,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctUINT32 * Physical,
++ OUT gctPOINTER * Logical,
++ OUT gctPOINTER * Handle
++ );
++
++/* Free video memory. */
++gceSTATUS
++gcoOS_FreeVideoMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Handle
++ );
++
++/* Lock video memory. */
++gceSTATUS
++gcoOS_LockVideoMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Handle,
++ IN gctBOOL InUserSpace,
++ IN gctBOOL InCacheable,
++ OUT gctUINT32 * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoHAL_MapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR GPUAddress
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoHAL_UnmapUserMemory(
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 GPUAddress
++ );
++
++/* Schedule an unmap of a user buffer using event mechanism. */
++gceSTATUS
++gcoHAL_ScheduleUnmapUserMemory(
++ IN gcoHAL Hal,
++ IN gctPOINTER Info,
++ IN gctSIZE_T Size,
++ IN gctUINT32 Address,
++ IN gctPOINTER Memory
++ );
++
++/* Commit the current command buffer. */
++gceSTATUS
++gcoHAL_Commit(
++ IN gcoHAL Hal,
++ IN gctBOOL Stall
++ );
++
++#if gcdENABLE_3D
++/* Sencd fence command. */
++gceSTATUS
++gcoHAL_SendFence(
++ IN gcoHAL Hal
++ );
++#endif /* gcdENABLE_3D */
++
++/* Query the tile capabilities. */
++gceSTATUS
++gcoHAL_QueryTiled(
++ IN gcoHAL Hal,
++ OUT gctINT32 * TileWidth2D,
++ OUT gctINT32 * TileHeight2D,
++ OUT gctINT32 * TileWidth3D,
++ OUT gctINT32 * TileHeight3D
++ );
++
++gceSTATUS
++gcoHAL_Compact(
++ IN gcoHAL Hal
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoHAL_ProfileStart(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_ProfileEnd(
++ IN gcoHAL Hal,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++/* Power Management */
++gceSTATUS
++gcoHAL_SetPowerManagementState(
++ IN gcoHAL Hal,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gcoHAL_QueryPowerManagementState(
++ IN gcoHAL Hal,
++ OUT gceCHIPPOWERSTATE *State
++ );
++
++/* Set the filter type for filter blit. */
++gceSTATUS
++gcoHAL_SetFilterType(
++ IN gcoHAL Hal,
++ IN gceFILTER_TYPE FilterType
++ );
++
++gceSTATUS
++gcoHAL_GetDump(
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++#if gcdENABLE_3D
++gceSTATUS
++gcoHAL_SetPatchID(
++ IN gcoHAL Hal,
++ IN gcePATCH_ID PatchID
++ );
++
++/* Get Patch ID based on process name */
++gceSTATUS
++gcoHAL_GetPatchID(
++ IN gcoHAL Hal,
++ OUT gcePATCH_ID * PatchID
++ );
++
++gceSTATUS
++gcoHAL_SetGlobalPatchID(
++ IN gcoHAL Hal,
++ IN gcePATCH_ID PatchID
++ );
++#endif /* gcdENABLE_3D */
++/* Call the kernel HAL layer. */
++gceSTATUS
++gcoHAL_Call(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++/* Schedule an event. */
++gceSTATUS
++gcoHAL_ScheduleEvent(
++ IN gcoHAL Hal,
++ IN OUT gcsHAL_INTERFACE_PTR Interface
++ );
++
++/* Destroy a surface. */
++gceSTATUS
++gcoHAL_DestroySurface(
++ IN gcoHAL Hal,
++ IN gcoSURF Surface
++ );
++
++/* Request a start/stop timestamp. */
++gceSTATUS
++gcoHAL_SetTimer(
++ IN gcoHAL Hal,
++ IN gctUINT32 Index,
++ IN gctBOOL Start
++ );
++
++/* Get Time delta from a Timer in microseconds. */
++gceSTATUS
++gcoHAL_GetTimerTime(
++ IN gcoHAL Hal,
++ IN gctUINT32 Timer,
++ OUT gctINT32_PTR TimeDelta
++ );
++
++/* set timeout value. */
++gceSTATUS
++gcoHAL_SetTimeOut(
++ IN gcoHAL Hal,
++ IN gctUINT32 timeOut
++ );
++
++gceSTATUS
++gcoHAL_SetHardwareType(
++ IN gcoHAL Hal,
++ IN gceHARDWARE_TYPE HardwardType
++ );
++
++gceSTATUS
++gcoHAL_GetHardwareType(
++ IN gcoHAL Hal,
++ OUT gceHARDWARE_TYPE * HardwardType
++ );
++
++gceSTATUS
++gcoHAL_QueryChipCount(
++ IN gcoHAL Hal,
++ OUT gctINT32 * Count
++ );
++
++gceSTATUS
++gcoHAL_Query3DCoreCount(
++ IN gcoHAL Hal,
++ OUT gctUINT32 *Count
++ );
++
++gceSTATUS
++gcoHAL_QuerySeparated2D(
++ IN gcoHAL Hal
++ );
++
++gceSTATUS
++gcoHAL_Is3DAvailable(
++ IN gcoHAL Hal
++ );
++
++/* Get pointer to gcoVG object. */
++gceSTATUS
++gcoHAL_GetVGEngine(
++ IN gcoHAL Hal,
++ OUT gcoVG * Engine
++ );
++
++gceSTATUS
++gcoHAL_QueryChipLimits(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ IN gctINT32 Mask,
++ OUT gcsHAL_LIMITS *Limits);
++
++gceSTATUS
++gcoHAL_QueryChipFeature(
++ IN gcoHAL Hal,
++ IN gctINT32 Chip,
++ IN gctINT32 Mask,
++ IN gceFEATURE Feature);
++
++/*----------------------------------------------------------------------------*/
++/*----- Shared Buffer --------------------------------------------------------*/
++
++/* Create shared buffer. */
++gceSTATUS
++gcoHAL_CreateShBuffer(
++ IN gctUINT32 Size,
++ OUT gctSHBUF * ShBuf
++ );
++
++/* Destroy shared buffer. */
++gceSTATUS
++gcoHAL_DestroyShBuffer(
++ IN gctSHBUF ShBuf
++ );
++
++/* Map shared buffer to current process. */
++gceSTATUS
++gcoHAL_MapShBuffer(
++ IN gctSHBUF ShBuf
++ );
++
++/* Write user data to shared buffer. */
++gceSTATUS
++gcoHAL_WriteShBuffer(
++ IN gctSHBUF ShBuf,
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 ByteCount
++ );
++
++/* Read user data from shared buffer. */
++gceSTATUS
++gcoHAL_ReadShBuffer(
++ IN gctSHBUF ShBuf,
++ IN gctPOINTER Data,
++ IN gctUINT32 BytesCount,
++ OUT gctUINT32 * BytesRead
++ );
++
++/* Config power management to be enabled or disabled. */
++gceSTATUS
++gcoHAL_ConfigPowerManagement(
++ IN gctBOOL Enable
++ );
++
++#if gcdENABLE_3D || gcdENABLE_VG
++/* Query the target capabilities. */
++gceSTATUS
++gcoHAL_QueryTargetCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MultiTargetCount,
++ OUT gctUINT * MaxSamples
++ );
++#endif
++
++/******************************************************************************\
++********************************** gcoOS Object *********************************
++\******************************************************************************/
++/* Lock PLS access */
++gceSTATUS
++gcoOS_LockPLS(
++ void
++ );
++
++/* Unlock PLS access */
++gceSTATUS
++gcoOS_UnLockPLS(
++ void
++ );
++
++/* Get PLS value for given key */
++gctPOINTER
++gcoOS_GetPLSValue(
++ IN gcePLS_VALUE key
++ );
++
++/* Set PLS value of a given key */
++void
++gcoOS_SetPLSValue(
++ IN gcePLS_VALUE key,
++ OUT gctPOINTER value
++ );
++
++/* Get access to the thread local storage. */
++gceSTATUS
++gcoOS_GetTLS(
++ OUT gcsTLS_PTR * TLS
++ );
++
++ /* Copy the TLS from a source thread. */
++ gceSTATUS gcoOS_CopyTLS(IN gcsTLS_PTR Source);
++
++/* Destroy the objects associated with the current thread. */
++void
++gcoOS_FreeThreadData(
++ void
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoOS_Construct(
++ IN gctPOINTER Context,
++ OUT gcoOS * Os
++ );
++
++/* Empty function for compatibility. */
++gceSTATUS
++gcoOS_Destroy(
++ IN gcoOS Os
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gcoOS_GetBaseAddress(
++ IN gcoOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gcoOS_Allocate(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Get allocated memory size. */
++gceSTATUS
++gcoOS_GetMemorySize(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gcoOS_Free(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoOS_AllocateSharedMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoOS_FreeSharedMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoOS_AllocateMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoOS_FreeMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gcoOS_AllocateContiguous(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gcoOS_FreeContiguous(
++ IN gcoOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Map user memory. */
++gceSTATUS
++gcoOS_MapUserMemoryEx(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gcoOS_UnmapUserMemory(
++ IN gcoOS Os,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/* Device I/O Control call to the kernel HAL layer. */
++gceSTATUS
++gcoOS_DeviceControl(
++ IN gcoOS Os,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ IN gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/* Allocate non paged memory. */
++gceSTATUS
++gcoOS_AllocateNonPagedMemory(
++ IN gcoOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non paged memory. */
++gceSTATUS
++gcoOS_FreeNonPagedMemory(
++ IN gcoOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++#define gcmOS_SAFE_FREE(os, mem) \
++ gcoOS_Free(os, mem); \
++ mem = gcvNULL
++
++#define gcmOS_SAFE_FREE_SHARED_MEMORY(os, mem) \
++ gcoOS_FreeSharedMemory(os, mem); \
++ mem = gcvNULL
++
++#define gcmkOS_SAFE_FREE(os, mem) \
++ gckOS_Free(os, mem); \
++ mem = gcvNULL
++
++typedef enum _gceFILE_MODE
++{
++ gcvFILE_CREATE = 0,
++ gcvFILE_APPEND,
++ gcvFILE_READ,
++ gcvFILE_CREATETEXT,
++ gcvFILE_APPENDTEXT,
++ gcvFILE_READTEXT,
++}
++gceFILE_MODE;
++
++/* Open a file. */
++gceSTATUS
++gcoOS_Open(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ IN gceFILE_MODE Mode,
++ OUT gctFILE * File
++ );
++
++/* Close a file. */
++gceSTATUS
++gcoOS_Close(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Read data from a file. */
++gceSTATUS
++gcoOS_Read(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctPOINTER Data,
++ OUT gctSIZE_T * ByteRead
++ );
++
++/* Write data to a file. */
++gceSTATUS
++gcoOS_Write(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data to a file. */
++gceSTATUS
++gcoOS_Flush(
++ IN gcoOS Os,
++ IN gctFILE File
++ );
++
++/* Close a file descriptor. */
++gceSTATUS
++gcoOS_CloseFD(
++ IN gcoOS Os,
++ IN gctINT FD
++ );
++
++/* Dup file descriptor to another. */
++gceSTATUS
++gcoOS_DupFD(
++ IN gcoOS Os,
++ IN gctINT FD,
++ OUT gctINT * FD2
++ );
++
++/* Create an endpoint for communication. */
++gceSTATUS
++gcoOS_Socket(
++ IN gcoOS Os,
++ IN gctINT Domain,
++ IN gctINT Type,
++ IN gctINT Protocol,
++ OUT gctINT *SockFd
++ );
++
++/* Close a socket. */
++gceSTATUS
++gcoOS_CloseSocket(
++ IN gcoOS Os,
++ IN gctINT SockFd
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_Connect(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctCONST_POINTER HostName,
++ IN gctUINT Port);
++
++/* Shut down part of connection on a socket. */
++gceSTATUS
++gcoOS_Shutdown(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT How
++ );
++
++/* Send a message on a socket. */
++gceSTATUS
++gcoOS_Send(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data,
++ IN gctINT Flags
++ );
++
++/* Initiate a connection on a socket. */
++gceSTATUS
++gcoOS_WaitForSend(
++ IN gcoOS Os,
++ IN gctINT SockFd,
++ IN gctINT Seconds,
++ IN gctINT MicroSeconds);
++
++/* Get environment variable value. */
++gceSTATUS
++gcoOS_GetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ OUT gctSTRING * Value
++ );
++
++/* Set environment variable value. */
++gceSTATUS
++gcoOS_SetEnv(
++ IN gcoOS Os,
++ IN gctCONST_STRING VarName,
++ IN gctSTRING Value
++ );
++
++/* Get current working directory. */
++gceSTATUS
++gcoOS_GetCwd(
++ IN gcoOS Os,
++ IN gctINT SizeInBytes,
++ OUT gctSTRING Buffer
++ );
++
++/* Get file status info. */
++gceSTATUS
++gcoOS_Stat(
++ IN gcoOS Os,
++ IN gctCONST_STRING FileName,
++ OUT gctPOINTER Buffer
++ );
++
++typedef enum _gceFILE_WHENCE
++{
++ gcvFILE_SEEK_SET,
++ gcvFILE_SEEK_CUR,
++ gcvFILE_SEEK_END
++}
++gceFILE_WHENCE;
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_Seek(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Offset,
++ IN gceFILE_WHENCE Whence
++ );
++
++/* Set the current position of a file. */
++gceSTATUS
++gcoOS_SetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ IN gctUINT32 Position
++ );
++
++/* Get the current position of a file. */
++gceSTATUS
++gcoOS_GetPos(
++ IN gcoOS Os,
++ IN gctFILE File,
++ OUT gctUINT32 * Position
++ );
++
++/* Same as strstr. */
++gceSTATUS
++gcoOS_StrStr(
++ IN gctCONST_STRING String,
++ IN gctCONST_STRING SubString,
++ OUT gctSTRING * Output
++ );
++
++/* Find the last occurance of a character inside a string. */
++gceSTATUS
++gcoOS_StrFindReverse(
++ IN gctCONST_STRING String,
++ IN gctINT8 Character,
++ OUT gctSTRING * Output
++ );
++
++gceSTATUS
++gcoOS_StrDup(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ OUT gctSTRING * Target
++ );
++
++/* Copy a string. */
++gceSTATUS
++gcoOS_StrCopySafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Append a string. */
++gceSTATUS
++gcoOS_StrCatSafe(
++ IN gctSTRING Destination,
++ IN gctSIZE_T DestinationSize,
++ IN gctCONST_STRING Source
++ );
++
++/* Compare two strings. */
++gceSTATUS
++gcoOS_StrCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2
++ );
++
++/* Compare characters of two strings. */
++gceSTATUS
++gcoOS_StrNCmp(
++ IN gctCONST_STRING String1,
++ IN gctCONST_STRING String2,
++ IN gctSIZE_T Count
++ );
++
++/* Convert string to float. */
++gceSTATUS
++gcoOS_StrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert hex string to integer. */
++gceSTATUS gcoOS_HexStrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++/* Convert hex string to float. */
++gceSTATUS
++gcoOS_HexStrToFloat(
++ IN gctCONST_STRING String,
++ OUT gctFLOAT * Float
++ );
++
++/* Convert string to integer. */
++gceSTATUS
++gcoOS_StrToInt(
++ IN gctCONST_STRING String,
++ OUT gctINT * Int
++ );
++
++gceSTATUS
++gcoOS_MemCmp(
++ IN gctCONST_POINTER Memory1,
++ IN gctCONST_POINTER Memory2,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_PrintStrSafe(
++ OUT gctSTRING String,
++ IN gctSIZE_T StringSize,
++ IN OUT gctUINT * Offset,
++ IN gctCONST_STRING Format,
++ ...
++ );
++
++gceSTATUS
++gcoOS_LoadLibrary(
++ IN gcoOS Os,
++ IN gctCONST_STRING Library,
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeLibrary(
++ IN gcoOS Os,
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_GetProcAddress(
++ IN gcoOS Os,
++ IN gctHANDLE Handle,
++ IN gctCONST_STRING Name,
++ OUT gctPOINTER * Function
++ );
++
++gceSTATUS
++gcoOS_Compact(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_AddSignalHandler (
++ IN gceSignalHandlerType SignalHandlerType
++ );
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gcoOS_ProfileStart(
++ IN gcoOS Os
++ );
++
++gceSTATUS
++gcoOS_ProfileEnd(
++ IN gcoOS Os,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_SetProfileSetting(
++ IN gcoOS Os,
++ IN gctBOOL Enable,
++ IN gctCONST_STRING FileName
++ );
++#endif
++
++/* Query the video memory. */
++gceSTATUS
++gcoOS_QueryVideoMemory(
++ IN gcoOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Detect if the process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByNamePid(
++ IN gctCONST_STRING Name,
++ IN gctHANDLE Pid
++ );
++
++/* Detect if the current process is the executable specified. */
++gceSTATUS
++gcoOS_DetectProcessByName(
++ IN gctCONST_STRING Name
++ );
++
++gceSTATUS
++gcoOS_DetectProcessByEncryptedName(
++ IN gctCONST_STRING Name
++ );
++
++#if defined(ANDROID)
++gceSTATUS
++gcoOS_DetectProgrameByEncryptedSymbols(
++ IN gcoOS_SymbolsList Symbols
++ );
++#endif
++
++/*----------------------------------------------------------------------------*/
++/*----- Atoms ----------------------------------------------------------------*/
++
++/* Construct an atom. */
++gceSTATUS
++gcoOS_AtomConstruct(
++ IN gcoOS Os,
++ OUT gcsATOM_PTR * Atom
++ );
++
++/* Destroy an atom. */
++gceSTATUS
++gcoOS_AtomDestroy(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom
++ );
++
++/* Get the 32-bit value protected by an atom. */
++gceSTATUS
++gcoOS_AtomGet(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/* Set the 32-bit value protected by an atom. */
++gceSTATUS
++gcoOS_AtomSet(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ IN gctINT32 Value
++ );
++
++/* Increment an atom. */
++gceSTATUS
++gcoOS_AtomIncrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++/* Decrement an atom. */
++gceSTATUS
++gcoOS_AtomDecrement(
++ IN gcoOS Os,
++ IN gcsATOM_PTR Atom,
++ OUT gctINT32_PTR OldValue
++ );
++
++gctHANDLE
++gcoOS_GetCurrentProcessID(
++ void
++ );
++
++gctHANDLE
++gcoOS_GetCurrentThreadID(
++ void
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Time -----------------------------------------------------------------*/
++
++/* Get the number of milliseconds since the system started. */
++gctUINT32
++gcoOS_GetTicks(
++ void
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gcoOS_GetTime(
++ gctUINT64_PTR Time
++ );
++
++/* Get CPU usage in microseconds. */
++gceSTATUS
++gcoOS_GetCPUTime(
++ gctUINT64_PTR CPUTime
++ );
++
++/* Get memory usage. */
++gceSTATUS
++gcoOS_GetMemoryUsage(
++ gctUINT32_PTR MaxRSS,
++ gctUINT32_PTR IxRSS,
++ gctUINT32_PTR IdRSS,
++ gctUINT32_PTR IsRSS
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gcoOS_Delay(
++ IN gcoOS Os,
++ IN gctUINT32 Delay
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Threads --------------------------------------------------------------*/
++
++#ifdef _WIN32
++/* Cannot include windows.h here becuase "near" and "far"
++ * which are used in gcsDEPTH_INFO, are defined to nothing in WinDef.h.
++ * So, use the real value of DWORD and WINAPI, instead.
++ * DWORD is unsigned long, and WINAPI is __stdcall.
++ * If these two are change in WinDef.h, the following two typdefs
++ * need to be changed, too.
++ */
++typedef unsigned long gctTHREAD_RETURN;
++typedef unsigned long (__stdcall * gcTHREAD_ROUTINE)(void * Argument);
++#else
++typedef void * gctTHREAD_RETURN;
++typedef void * (* gcTHREAD_ROUTINE)(void *);
++#endif
++
++/* Create a new thread. */
++gceSTATUS
++gcoOS_CreateThread(
++ IN gcoOS Os,
++ IN gcTHREAD_ROUTINE Worker,
++ IN gctPOINTER Argument,
++ OUT gctPOINTER * Thread
++ );
++
++/* Close a thread. */
++gceSTATUS
++gcoOS_CloseThread(
++ IN gcoOS Os,
++ IN gctPOINTER Thread
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Mutexes --------------------------------------------------------------*/
++
++/* Create a new mutex. */
++gceSTATUS
++gcoOS_CreateMutex(
++ IN gcoOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gcoOS_DeleteMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gcoOS_AcquireMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gcoOS_ReleaseMutex(
++ IN gcoOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Signals --------------------------------------------------------------*/
++
++/* Create a signal. */
++gceSTATUS
++gcoOS_CreateSignal(
++ IN gcoOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gcoOS_DestroySignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gcoOS_Signal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gcoOS_WaitSignal(
++ IN gcoOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a signal from another process */
++gceSTATUS
++gcoOS_MapSignal(
++ IN gctSIGNAL RemoteSignal,
++ OUT gctSIGNAL * LocalSignal
++ );
++
++/* Unmap a signal mapped from another process */
++gceSTATUS
++gcoOS_UnmapSignal(
++ IN gctSIGNAL Signal
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Android Native Fence -------------------------------------------------*/
++
++/* Create sync point. */
++gceSTATUS
++gcoOS_CreateSyncPoint(
++ IN gcoOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++/* Destroy sync point. */
++gceSTATUS
++gcoOS_DestroySyncPoint(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++/* Create native fence. */
++gceSTATUS
++gcoOS_CreateNativeFence(
++ IN gcoOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++/* Wait on native fence. */
++gceSTATUS
++gcoOS_WaitNativeFence(
++ IN gcoOS Os,
++ IN gctINT FenceFD,
++ IN gctUINT32 Timeout
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Memory Access and Cache ----------------------------------------------*/
++
++/* Write a register. */
++gceSTATUS
++gcoOS_WriteRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Read a register. */
++gceSTATUS
++gcoOS_ReadRegister(
++ IN gcoOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++gceSTATUS
++gcoOS_CacheClean(
++ IN gcoOS Os,
++ IN gctUINT32 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheFlush(
++ IN gcoOS Os,
++ IN gctUINT32 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_CacheInvalidate(
++ IN gcoOS Os,
++ IN gctUINT32 Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoOS_MemoryBarrier(
++ IN gcoOS Os,
++ IN gctPOINTER Logical
++ );
++
++gceSTATUS
++gcoOS_CPUPhysicalToGPUPhysical(
++ IN gctUINT32 CPUPhysical,
++ OUT gctUINT32_PTR GPUPhysical
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ );
++
++gceSTATUS
++gcoOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ );
++
++gceSTATUS
++gcoOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ );
++
++#define _gcmPROFILE_INIT(prefix, freq, start) \
++ do { \
++ prefix ## OS_QueryProfileTickRate(&(freq)); \
++ prefix ## OS_GetProfileTick(&(start)); \
++ } while (gcvFALSE)
++
++#define _gcmPROFILE_QUERY(prefix, start, ticks) \
++ do { \
++ prefix ## OS_GetProfileTick(&(ticks)); \
++ (ticks) = ((ticks) > (start)) ? ((ticks) - (start)) \
++ : (~0ull - (start) + (ticks) + 1); \
++ } while (gcvFALSE)
++
++#if gcdENABLE_PROFILING
++# define gcmkPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gck, freq, start)
++# define gcmkPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gck, start, ticks)
++# define gcmPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gco, freq, start)
++# define gcmPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gco, start, ticks)
++# define gcmPROFILE_ONLY(x) x
++# define gcmPROFILE_ELSE(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ONLY(x) x
++# define gcmPROFILE_DECLARE_ELSE(x) typedef x
++#else
++# define gcmkPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmkPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_INIT(start, freq) do { } while (gcvFALSE)
++# define gcmPROFILE_QUERY(start, ticks) do { } while (gcvFALSE)
++# define gcmPROFILE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_ELSE(x) x
++# define gcmPROFILE_DECLARE_ONLY(x) do { } while (gcvFALSE)
++# define gcmPROFILE_DECLARE_ELSE(x) x
++#endif
++
++/*******************************************************************************
++** gcoMATH object
++*/
++
++#define gcdPI 3.14159265358979323846f
++
++/* Kernel. */
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++/* User. */
++gctUINT32
++gcoMATH_Log2in5dot5(
++ IN gctINT X
++ );
++
++
++gctFLOAT
++gcoMATH_UIntAsFloat(
++ IN gctUINT32 X
++ );
++
++gctUINT32
++gcoMATH_FloatAsUInt(
++ IN gctFLOAT X
++ );
++
++gctBOOL
++gcoMATH_CompareEqualF(
++ IN gctFLOAT X,
++ IN gctFLOAT Y
++ );
++
++gctUINT16
++gcoMATH_UInt8AsFloat16(
++ IN gctUINT8 X
++ );
++
++gctUINT32
++gcoMATH_Float16ToFloat(
++ IN gctUINT16 In
++ );
++
++gctUINT16
++gcoMATH_FloatToFloat16(
++ IN gctUINT32 In
++ );
++
++gctUINT32
++gcoMATH_Float11ToFloat(
++ IN gctUINT32 In
++ );
++
++gctUINT16
++gcoMATH_FloatToFloat11(
++ IN gctUINT32 In
++ );
++
++gctUINT32
++gcoMATH_Float10ToFloat(
++ IN gctUINT32 In
++ );
++
++gctUINT16
++gcoMATH_FloatToFloat10(
++ IN gctUINT32 In
++ );
++
++gctUINT32
++gcoMATH_Float14ToFloat(
++ IN gctUINT16 In
++ );
++
++/******************************************************************************\
++**************************** Coordinate Structures *****************************
++\******************************************************************************/
++
++typedef struct _gcsPOINT
++{
++ gctINT32 x;
++ gctINT32 y;
++}
++gcsPOINT;
++
++typedef struct _gcsSIZE
++{
++ gctINT32 width;
++ gctINT32 height;
++}
++gcsSIZE;
++
++typedef struct _gcsRECT
++{
++ gctINT32 left;
++ gctINT32 top;
++ gctINT32 right;
++ gctINT32 bottom;
++}
++gcsRECT;
++
++typedef union _gcsPIXEL
++{
++ struct
++ {
++ gctFLOAT r, g, b, a;
++ gctFLOAT d, s;
++ } pf;
++
++ struct
++ {
++ gctINT32 r, g, b, a;
++ gctINT32 d, s;
++ } pi;
++
++ struct
++ {
++ gctUINT32 r, g, b, a;
++ gctUINT32 d, s;
++ } pui;
++
++} gcsPIXEL;
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- gcoSURF Common ------------------------------*/
++
++/* Color format classes. */
++typedef enum _gceFORMAT_CLASS
++{
++ gcvFORMAT_CLASS_RGBA = 4500,
++ gcvFORMAT_CLASS_YUV,
++ gcvFORMAT_CLASS_INDEX,
++ gcvFORMAT_CLASS_LUMINANCE,
++ gcvFORMAT_CLASS_BUMP,
++ gcvFORMAT_CLASS_DEPTH,
++ gcvFORMAT_CLASS_ASTC,
++ gcvFORMAT_CLASS_OTHER
++}
++gceFORMAT_CLASS;
++
++/* Color format data type */
++typedef enum _gceFORMAT_DATATYPE
++{
++ gcvFORMAT_DATATYPE_UNSIGNED_NORMALIZED,
++ gcvFORMAT_DATATYPE_SIGNED_NORMALIZED,
++ gcvFORMAT_DATATYPE_UNSIGNED_INTEGER,
++ gcvFORMAT_DATATYPE_SIGNED_INTEGER,
++ gcvFORMAT_DATATYPE_FLOAT16,
++ gcvFORMAT_DATATYPE_FLOAT32,
++ gcvFORMAT_DATATYPE_FLOAT_E5B9G9R9,
++ gcvFORMAT_DATATYPE_FLOAT_B10G11R11F,
++ gcvFORMAT_DATATYPE_INDEX,
++ gcvFORMAT_DATATYPE_SRGB,
++ gcvFORMAT_DATATYPE_FLOAT32_UINT,
++}
++gceFORMAT_DATATYPE;
++
++/* Special enums for width field in gcsFORMAT_COMPONENT. */
++typedef enum _gceCOMPONENT_CONTROL
++{
++ gcvCOMPONENT_NOTPRESENT = 0x00,
++ gcvCOMPONENT_DONTCARE = 0x80,
++ gcvCOMPONENT_WIDTHMASK = 0x7F,
++ gcvCOMPONENT_ODD = 0x80
++}
++gceCOMPONENT_CONTROL;
++
++/* Color format component parameters. */
++typedef struct _gcsFORMAT_COMPONENT
++{
++ gctUINT8 start;
++ gctUINT8 width;
++}
++gcsFORMAT_COMPONENT;
++
++/* RGBA color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_RGBA
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT red;
++ gcsFORMAT_COMPONENT green;
++ gcsFORMAT_COMPONENT blue;
++}
++gcsFORMAT_CLASS_TYPE_RGBA;
++
++/* YUV color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_YUV
++{
++ gcsFORMAT_COMPONENT y;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT v;
++}
++gcsFORMAT_CLASS_TYPE_YUV;
++
++/* Index color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_INDEX
++{
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_INDEX;
++
++/* Luminance color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_LUMINANCE
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT value;
++}
++gcsFORMAT_CLASS_TYPE_LUMINANCE;
++
++/* Bump map color format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_BUMP
++{
++ gcsFORMAT_COMPONENT alpha;
++ gcsFORMAT_COMPONENT l;
++ gcsFORMAT_COMPONENT v;
++ gcsFORMAT_COMPONENT u;
++ gcsFORMAT_COMPONENT q;
++ gcsFORMAT_COMPONENT w;
++}
++gcsFORMAT_CLASS_TYPE_BUMP;
++
++/* Depth and stencil format class. */
++typedef struct _gcsFORMAT_CLASS_TYPE_DEPTH
++{
++ gcsFORMAT_COMPONENT depth;
++ gcsFORMAT_COMPONENT stencil;
++}
++gcsFORMAT_CLASS_TYPE_DEPTH;
++
++typedef union _gcuPIXEL_FORMAT_CLASS
++{
++ gcsFORMAT_CLASS_TYPE_BUMP bump;
++ gcsFORMAT_CLASS_TYPE_RGBA rgba;
++ gcsFORMAT_CLASS_TYPE_YUV yuv;
++ gcsFORMAT_CLASS_TYPE_LUMINANCE lum;
++ gcsFORMAT_CLASS_TYPE_INDEX index;
++ gcsFORMAT_CLASS_TYPE_DEPTH depth;
++}
++gcuPIXEL_FORMAT_CLASS;
++
++/* Format parameters. */
++typedef struct _gcsSURF_FORMAT_INFO
++{
++ /* Name of the format */
++ gctCONST_STRING formatName;
++
++ /* Format code and class. */
++ gceSURF_FORMAT format;
++ gceFORMAT_CLASS fmtClass;
++
++ /* Format data type */
++ gceFORMAT_DATATYPE fmtDataType;
++
++ /* The size of one pixel in bits. */
++ gctUINT8 bitsPerPixel;
++
++ /* Pixel block dimensions. */
++ gctUINT blockWidth;
++ gctUINT blockHeight;
++
++ /* Pixel block size in bits. */
++ gctUINT blockSize;
++
++ /* Some formats are larger than what the GPU can support. */
++ /* These formats are read in the number of layers specified. */
++ gctUINT8 layers;
++
++ /* The format is faked and software will interpret it differently
++ ** with HW. Most of them can't be blendable(PE) or filterable(TX).
++ */
++ gctBOOL fakedFormat;
++
++ /* Some formats have two neighbour pixels interleaved together. */
++ /* To describe such format, set the flag to 1 and add another */
++ /* like this one describing the odd pixel format. */
++ gctBOOL interleaved;
++
++ /* sRGB format. */
++ gctBOOL sRGB;
++
++ /* Format components. */
++ gcuPIXEL_FORMAT_CLASS u;
++
++ /* Format components. */
++ gcuPIXEL_FORMAT_CLASS uOdd;
++
++ /* Render format. */
++ gceSURF_FORMAT closestRenderFormat;
++ /*gctCLOSEST_FORMAT dynamicClosestRenderFormat;*/
++ gctUINT renderFormat;
++ const gceTEXTURE_SWIZZLE * pixelSwizzle;
++
++ /* Texture format. */
++ gceSURF_FORMAT closestTXFormat;
++ gctUINT txFormat;
++ const gceTEXTURE_SWIZZLE * txSwizzle;
++ gctBOOL txIntFilter;
++}
++gcsSURF_FORMAT_INFO;
++
++/* Frame buffer information. */
++typedef struct _gcsSURF_FRAMEBUFFER
++{
++ gctPOINTER logical;
++ gctUINT width, height;
++ gctINT stride;
++ gceSURF_FORMAT format;
++}
++gcsSURF_FRAMEBUFFER;
++
++/* Generic pixel component descriptors. */
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XXX8;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XX8X;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_X8XX;
++extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_8XXX;
++
++typedef enum _gceORIENTATION
++{
++ gcvORIENTATION_TOP_BOTTOM,
++ gcvORIENTATION_BOTTOM_TOP,
++}
++gceORIENTATION;
++
++
++/* Construct a new gcoSURF object. */
++gceSTATUS
++gcoSURF_Construct(
++ IN gcoHAL Hal,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++/* Destroy an gcoSURF object. */
++gceSTATUS
++gcoSURF_Destroy(
++ IN gcoSURF Surface
++ );
++
++/* Map user-allocated surface. */
++gceSTATUS
++gcoSURF_MapUserSurface(
++ IN gcoSURF Surface,
++ IN gctUINT Alignment,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Wrapp surface with known logical/GPU address */
++gceSTATUS
++gcoSURF_WrapSurface(
++ IN gcoSURF Surface,
++ IN gctUINT Alignment,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++
++/* Query vid mem node info. */
++gceSTATUS
++gcoSURF_QueryVidMemNode(
++ IN gcoSURF Surface,
++ OUT gctUINT32 * Node,
++ OUT gcePOOL * Pool,
++ OUT gctSIZE_T_PTR Bytes
++ );
++
++/* Set the color type of the surface. */
++gceSTATUS
++gcoSURF_SetColorType(
++ IN gcoSURF Surface,
++ IN gceSURF_COLOR_TYPE ColorType
++ );
++
++/* Get the color type of the surface. */
++gceSTATUS
++gcoSURF_GetColorType(
++ IN gcoSURF Surface,
++ OUT gceSURF_COLOR_TYPE *ColorType
++ );
++
++/* Set the color space of the surface. */
++gceSTATUS
++gcoSURF_SetColorSpace(
++ IN gcoSURF Surface,
++ IN gceSURF_COLOR_SPACE ColorSpace
++ );
++
++/* Get the color space of the surface. */
++gceSTATUS
++gcoSURF_GetColorSpace(
++ IN gcoSURF Surface,
++ OUT gceSURF_COLOR_SPACE *ColorSpace
++ );
++
++
++/* Set the surface ration angle. */
++gceSTATUS
++gcoSURF_SetRotation(
++ IN gcoSURF Surface,
++ IN gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_IsValid(
++ IN gcoSURF Surface
++ );
++
++#if gcdENABLE_3D
++/* Verify and return the state of the tile status mechanism. */
++gceSTATUS
++gcoSURF_IsTileStatusSupported(
++ IN gcoSURF Surface
++ );
++
++/* Verify if surface has tile status enabled. */
++gceSTATUS
++gcoSURF_IsTileStatusEnabled(
++ IN gcoSURF Surface
++ );
++
++/* Verify if surface is compressed. */
++gceSTATUS
++gcoSURF_IsCompressed(
++ IN gcoSURF Surface
++ );
++
++/* Enable tile status for the specified surface on zero slot. */
++gceSTATUS
++gcoSURF_EnableTileStatus(
++ IN gcoSURF Surface
++ );
++
++/* Enable tile status for the specified surface on specified slot. */
++gceSTATUS
++gcoSURF_EnableTileStatusEx(
++ IN gcoSURF Surface,
++ IN gctUINT RtIndex
++ );
++
++/* Disable tile status for the specified surface. */
++gceSTATUS
++gcoSURF_DisableTileStatus(
++ IN gcoSURF Surface,
++ IN gctBOOL Decompress
++ );
++
++/* Flush tile status cache for the specified surface. */
++gceSTATUS
++gcoSURF_FlushTileStatus(
++ IN gcoSURF Surface,
++ IN gctBOOL Decompress
++ );
++#endif /* gcdENABLE_3D */
++
++/* Get surface size. */
++gceSTATUS
++gcoSURF_GetSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctUINT * Depth
++ );
++
++/* Get surface aligned sizes. */
++gceSTATUS
++gcoSURF_GetAlignedSize(
++ IN gcoSURF Surface,
++ OUT gctUINT * Width,
++ OUT gctUINT * Height,
++ OUT gctINT * Stride
++ );
++
++/* Get alignments. */
++gceSTATUS
++gcoSURF_GetAlignment(
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT * AddressAlignment,
++ OUT gctUINT * XAlignment,
++ OUT gctUINT * YAlignment
++ );
++
++gceSTATUS
++gcoSURF_AlignResolveRect(
++ IN gcoSURF Surf,
++ IN gcsPOINT_PTR RectOrigin,
++ IN gcsPOINT_PTR RectSize,
++ OUT gcsPOINT_PTR AlignedOrigin,
++ OUT gcsPOINT_PTR AlignedSize
++ );
++
++/* Get surface type and format. */
++gceSTATUS
++gcoSURF_GetFormat(
++ IN gcoSURF Surface,
++ OUT OPTIONAL gceSURF_TYPE * Type,
++ OUT OPTIONAL gceSURF_FORMAT * Format
++ );
++
++/* Get surface information */
++gceSTATUS
++gcoSURF_GetFormatInfo(
++ IN gcoSURF Surface,
++ OUT gcsSURF_FORMAT_INFO_PTR * formatInfo
++ );
++
++/* Get Surface pack format */
++gceSTATUS
++gcoSURF_GetPackedFormat(
++ IN gcoSURF Surface,
++ OUT gceSURF_FORMAT * Format
++ );
++
++/* Get surface tiling. */
++gceSTATUS
++gcoSURF_GetTiling(
++ IN gcoSURF Surface,
++ OUT gceTILING * Tiling
++ );
++
++/* Get flip bitmap offset bytes. */
++gceSTATUS
++gcoSURF_GetFlipBitmapOffset(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR FlipBitmapOffset
++ );
++
++/* Get bottom buffer offset bytes. */
++gceSTATUS
++gcoSURF_GetBottomBufferOffset(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR BottomBufferOffset
++ );
++
++/* Lock the surface. */
++gceSTATUS
++gcoSURF_Lock(
++ IN gcoSURF Surface,
++ IN OUT gctUINT32 * Address,
++ IN OUT gctPOINTER * Memory
++ );
++
++/* Unlock the surface. */
++gceSTATUS
++gcoSURF_Unlock(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory
++ );
++
++/*. Query surface flags.*/
++gceSTATUS
++gcoSURF_QueryFlags(
++ IN gcoSURF Surface,
++ IN gceSURF_FLAG Flag
++ );
++
++/* Return pixel format parameters; Info is required to be a pointer to an
++ * array of at least two items because some formats have up to two records
++ * of description. */
++gceSTATUS
++gcoSURF_QueryFormat(
++ IN gceSURF_FORMAT Format,
++ OUT gcsSURF_FORMAT_INFO_PTR * Info
++ );
++
++/* Compute the color pixel mask. */
++gceSTATUS
++gcoSURF_ComputeColorMask(
++ IN gcsSURF_FORMAT_INFO_PTR Format,
++ OUT gctUINT32_PTR ColorMask
++ );
++
++/* Flush the surface. */
++gceSTATUS
++gcoSURF_Flush(
++ IN gcoSURF Surface
++ );
++
++/* Fill surface from it's tile status buffer. */
++gceSTATUS
++gcoSURF_FillFromTile(
++ IN gcoSURF Surface
++ );
++
++/* Fill surface with a value. */
++gceSTATUS
++gcoSURF_Fill(
++ IN gcoSURF Surface,
++ IN gcsPOINT_PTR Origin,
++ IN gcsSIZE_PTR Size,
++ IN gctUINT32 Value,
++ IN gctUINT32 Mask
++ );
++
++/* Alpha blend two surfaces together. */
++gceSTATUS
++gcoSURF_Blend(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrig,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsSIZE_PTR Size,
++ IN gceSURF_BLEND_MODE Mode
++ );
++
++/* Create a new gcoSURF wrapper object. */
++gceSTATUS
++gcoSURF_ConstructWrapper(
++ IN gcoHAL Hal,
++ OUT gcoSURF * Surface
++ );
++
++/* Set surface flags.*/
++gceSTATUS
++gcoSURF_SetFlags(
++ IN gcoSURF Surface,
++ IN gceSURF_FLAG Flag,
++ IN gctBOOL Value
++ );
++
++/* Set the underlying buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Stride,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical
++ );
++
++/* Set the underlying video buffer for the surface wrapper. */
++gceSTATUS
++gcoSURF_SetVideoBuffer(
++ IN gcoSURF Surface,
++ IN gceSURF_TYPE Type,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Stride,
++ IN gctPOINTER *LogicalPlane1,
++ IN gctUINT32 *PhysicalPlane1
++ );
++
++/* Set the size of the surface in pixels and map the underlying buffer. */
++gceSTATUS
++gcoSURF_SetWindow(
++ IN gcoSURF Surface,
++ IN gctUINT X,
++ IN gctUINT Y,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Set width/height alignment of the surface directly and calculate stride/size. This is only for dri backend now. Please be careful before use. */
++gceSTATUS
++gcoSURF_SetAlignment(
++ IN gcoSURF Surface,
++ IN gctUINT Width,
++ IN gctUINT Height
++ );
++
++/* Increase reference count of the surface. */
++gceSTATUS
++gcoSURF_ReferenceSurface(
++ IN gcoSURF Surface
++ );
++
++/* Get surface reference count. */
++gceSTATUS
++gcoSURF_QueryReferenceCount(
++ IN gcoSURF Surface,
++ OUT gctINT32 * ReferenceCount
++ );
++
++/* Set surface orientation. */
++gceSTATUS
++gcoSURF_SetOrientation(
++ IN gcoSURF Surface,
++ IN gceORIENTATION Orientation
++ );
++
++/* Query surface orientation. */
++gceSTATUS
++gcoSURF_QueryOrientation(
++ IN gcoSURF Surface,
++ OUT gceORIENTATION * Orientation
++ );
++
++gceSTATUS
++gcoSURF_SetOffset(
++ IN gcoSURF Surface,
++ IN gctSIZE_T Offset
++ );
++
++gceSTATUS
++gcoSURF_NODE_Cache(
++ IN gcsSURF_NODE_PTR Node,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Lock and unlock surface node */
++gceSTATUS
++gcoSURF_LockNode(
++ IN gcsSURF_NODE_PTR Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++gceSTATUS
++gcoSURF_UnLockNode(
++ IN gcsSURF_NODE_PTR Node,
++ IN gceSURF_TYPE Type
++ );
++
++/* Perform CPU cache operation on surface node */
++gceSTATUS
++gcoSURF_NODE_CPUCacheOperation(
++ IN gcsSURF_NODE_PTR Node,
++ IN gceSURF_TYPE Type,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Length,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Perform CPU cache operation on surface */
++gceSTATUS
++gcoSURF_CPUCacheOperation(
++ IN gcoSURF Surface,
++ IN gceCACHEOPERATION Operation
++ );
++
++
++gceSTATUS
++gcoSURF_Swap(
++ IN gcoSURF Surface1,
++ IN gcoSURF Surface2
++ );
++
++gceSTATUS
++gcoSURF_ResetSurWH(
++ IN gcoSURF Surface,
++ IN gctUINT oriw,
++ IN gctUINT orih,
++ IN gctUINT alignw,
++ IN gctUINT alignh,
++ IN gceSURF_FORMAT fmt
++);
++
++/* Update surface timestamp. */
++gceSTATUS
++gcoSURF_UpdateTimeStamp(
++ IN gcoSURF Surface
++ );
++
++/* Query surface current timestamp. */
++gceSTATUS
++gcoSURF_QueryTimeStamp(
++ IN gcoSURF Surface,
++ OUT gctUINT64 * TimeStamp
++ );
++
++/*
++ * Allocate shared buffer for this surface, so that
++ * surface states can be shared across processes.
++ */
++gceSTATUS
++gcoSURF_AllocShBuffer(
++ IN gcoSURF Surface,
++ OUT gctSHBUF * ShBuf
++ );
++
++/* Bind shared buffer to this surface */
++gceSTATUS
++gcoSURF_BindShBuffer(
++ IN gcoSURF Surface,
++ IN gctSHBUF ShBuf
++ );
++
++/* Push surface shared states to shared buffer. */
++gceSTATUS
++gcoSURF_PushSharedInfo(
++ IN gcoSURF Surface
++ );
++
++/* Pop shared states from shared buffer. */
++gceSTATUS
++gcoSURF_PopSharedInfo(
++ IN gcoSURF Surface
++ );
++
++#if (gcdENABLE_3D || gcdENABLE_VG)
++/* Copy surface. */
++gceSTATUS
++gcoSURF_Copy(
++ IN gcoSURF Surface,
++ IN gcoSURF Source
++ );
++
++/* Set number of samples for a gcoSURF object. */
++gceSTATUS
++gcoSURF_SetSamples(
++ IN gcoSURF Surface,
++ IN gctUINT Samples
++ );
++
++/* Get the number of samples per pixel. */
++gceSTATUS
++gcoSURF_GetSamples(
++ IN gcoSURF Surface,
++ OUT gctUINT_PTR Samples
++ );
++#endif
++
++/******************************************************************************\
++********************************* gcoDUMP Object ********************************
++\******************************************************************************/
++
++/* Construct a new gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Construct(
++ IN gcoOS Os,
++ IN gcoHAL Hal,
++ OUT gcoDUMP * Dump
++ );
++
++/* Destroy a gcoDUMP object. */
++gceSTATUS
++gcoDUMP_Destroy(
++ IN gcoDUMP Dump
++ );
++
++/* Enable/disable dumping. */
++gceSTATUS
++gcoDUMP_Control(
++ IN gcoDUMP Dump,
++ IN gctSTRING FileName
++ );
++
++gceSTATUS
++gcoDUMP_IsEnabled(
++ IN gcoDUMP Dump,
++ OUT gctBOOL * Enabled
++ );
++
++/* Add surface. */
++gceSTATUS
++gcoDUMP_AddSurface(
++ IN gcoDUMP Dump,
++ IN gctINT32 Width,
++ IN gctINT32 Height,
++ IN gceSURF_FORMAT PixelFormat,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount
++ );
++
++/* Mark the beginning of a frame. */
++gceSTATUS
++gcoDUMP_FrameBegin(
++ IN gcoDUMP Dump
++ );
++
++/* Mark the end of a frame. */
++gceSTATUS
++gcoDUMP_FrameEnd(
++ IN gcoDUMP Dump
++ );
++
++/* Dump data. */
++gceSTATUS
++gcoDUMP_DumpData(
++ IN gcoDUMP Dump,
++ IN gceDUMP_TAG Type,
++ IN gctUINT32 Address,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Delete an address. */
++gceSTATUS
++gcoDUMP_Delete(
++ IN gcoDUMP Dump,
++ IN gctUINT32 Address
++ );
++
++/* Enable dump or not. */
++gceSTATUS
++gcoDUMP_SetDumpFlag(
++ IN gctBOOL DumpState
++ );
++
++/******************************************************************************\
++******************************* gcsRECT Structure ******************************
++\******************************************************************************/
++
++/* Initialize rectangle structure. */
++gceSTATUS
++gcsRECT_Set(
++ OUT gcsRECT_PTR Rect,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Return the width of the rectangle. */
++gceSTATUS
++gcsRECT_Width(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Width
++ );
++
++/* Return the height of the rectangle. */
++gceSTATUS
++gcsRECT_Height(
++ IN gcsRECT_PTR Rect,
++ OUT gctINT32 * Height
++ );
++
++/* Ensure that top left corner is to the left and above the right bottom. */
++gceSTATUS
++gcsRECT_Normalize(
++ IN OUT gcsRECT_PTR Rect
++ );
++
++/* Compare two rectangles. */
++gceSTATUS
++gcsRECT_IsEqual(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * Equal
++ );
++
++/* Compare the sizes of two rectangles. */
++gceSTATUS
++gcsRECT_IsOfEqualSize(
++ IN gcsRECT_PTR Rect1,
++ IN gcsRECT_PTR Rect2,
++ OUT gctBOOL * EqualSize
++ );
++
++gceSTATUS
++gcsRECT_RelativeRotation(
++ IN gceSURF_ROTATION Orientation,
++ IN OUT gceSURF_ROTATION *Relation);
++
++gceSTATUS
++
++gcsRECT_Rotate(
++
++ IN OUT gcsRECT_PTR Rect,
++
++ IN gceSURF_ROTATION Rotation,
++
++ IN gceSURF_ROTATION toRotation,
++
++ IN gctINT32 SurfaceWidth,
++
++ IN gctINT32 SurfaceHeight
++
++ );
++
++/******************************************************************************\
++**************************** gcsBOUNDARY Structure *****************************
++\******************************************************************************/
++
++typedef struct _gcsBOUNDARY
++{
++ gctINT x;
++ gctINT y;
++ gctINT width;
++ gctINT height;
++}
++gcsBOUNDARY;
++
++/******************************************************************************\
++********************************* gcoHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gcoHEAP * gcoHEAP;
++
++/* Construct a new gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Construct(
++ IN gcoOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gcoHEAP * Heap
++ );
++
++/* Destroy an gcoHEAP object. */
++gceSTATUS
++gcoHEAP_Destroy(
++ IN gcoHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gcoHEAP_Allocate(
++ IN gcoHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcoHEAP_GetMemorySize(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Memory,
++ OUT gctSIZE_T_PTR MemorySize
++ );
++
++/* Free memory. */
++gceSTATUS
++gcoHEAP_Free(
++ IN gcoHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++#if (VIVANTE_PROFILER || gcdDEBUG)
++/* Profile the heap. */
++gceSTATUS
++gcoHEAP_ProfileStart(
++ IN gcoHEAP Heap
++ );
++
++gceSTATUS
++gcoHEAP_ProfileEnd(
++ IN gcoHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++#endif
++
++
++/******************************************************************************\
++******************************* Debugging Macros *******************************
++\******************************************************************************/
++
++void
++gcoOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gcoOS_GetDebugLevel(
++ OUT gctUINT32_PTR DebugLevel
++ );
++
++void
++gcoOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_GetDebugZone(
++ IN gctUINT32 Zone,
++ OUT gctUINT32_PTR DebugZone
++ );
++
++void
++gcoOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gcoOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gcoOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++gctFILE
++gcoOS_ReplaceDebugFile(
++ IN gctFILE fp
++ );
++
++void
++gcoOS_SysTraceBegin(
++ IN gctCONST_STRING FuncName
++ );
++
++void
++gcoOS_SysTraceEnd(
++ IN void);
++
++/*******************************************************************************
++**
++** gcmFATAL
++**
++** Print a message to the debugger and execute a break point.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugFatal(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_FATAL)
++# define gcmFATAL gcoOS_DebugFatal
++# define gcmkFATAL gckOS_DebugFatal
++#elif gcdHAS_ELLIPSIS
++# define gcmFATAL(...)
++# define gcmkFATAL(...)
++#else
++ gcmINLINE static void
++ __dummy_fatal(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmFATAL __dummy_fatal
++# define gcmkFATAL __dummy_fatal
++#endif
++
++#define gcmENUM2TEXT(e) case e: return #e
++
++/*******************************************************************************
++**
++** gcmTRACE
++**
++** Print a message to the debugfer if the correct level has been set. In
++** retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** level Level of message.
++** message Message.
++** ... Optional arguments.
++*/
++#define gcvLEVEL_NONE -1
++#define gcvLEVEL_ERROR 0
++#define gcvLEVEL_WARNING 1
++#define gcvLEVEL_INFO 2
++#define gcvLEVEL_VERBOSE 3
++
++void
++gckOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceN(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTrace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE gcoOS_DebugTrace
++# define gcmkTRACE gckOS_DebugTrace
++# define gcmkTRACE_N gckOS_DebugTraceN
++#elif gcdHAS_ELLIPSIS
++# define gcmTRACE(...)
++# define gcmkTRACE(...)
++# define gcmkTRACE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace(
++ IN gctUINT32 Level,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_n(
++ IN gctUINT32 Level,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE __dummy_trace
++# define gcmkTRACE __dummy_trace
++# define gcmkTRACE_N __dummy_trace_n
++#endif
++
++/* Zones common for kernel and user. */
++#define gcvZONE_OS (1 << 0)
++#define gcvZONE_HARDWARE (1 << 1)
++#define gcvZONE_HEAP (1 << 2)
++#define gcvZONE_SIGNAL (1 << 27)
++
++/* Kernel zones. */
++#define gcvZONE_KERNEL (1 << 3)
++#define gcvZONE_VIDMEM (1 << 4)
++#define gcvZONE_COMMAND (1 << 5)
++#define gcvZONE_DRIVER (1 << 6)
++#define gcvZONE_CMODEL (1 << 7)
++#define gcvZONE_MMU (1 << 8)
++#define gcvZONE_EVENT (1 << 9)
++#define gcvZONE_DEVICE (1 << 10)
++#define gcvZONE_DATABASE (1 << 11)
++#define gcvZONE_INTERRUPT (1 << 12)
++#define gcvZONE_POWER (1 << 13)
++
++/* User zones. */
++#define gcvZONE_HAL (1 << 3)
++#define gcvZONE_BUFFER (1 << 4)
++#define gcvZONE_CONTEXT (1 << 5)
++#define gcvZONE_SURFACE (1 << 6)
++#define gcvZONE_INDEX (1 << 7)
++#define gcvZONE_STREAM (1 << 8)
++#define gcvZONE_TEXTURE (1 << 9)
++#define gcvZONE_2D (1 << 10)
++#define gcvZONE_3D (1 << 11)
++#define gcvZONE_COMPILER (1 << 12)
++#define gcvZONE_MEMORY (1 << 13)
++#define gcvZONE_STATE (1 << 14)
++#define gcvZONE_AUX (1 << 15)
++#define gcvZONE_VERTEX (1 << 16)
++#define gcvZONE_CL (1 << 17)
++#define gcvZONE_COMPOSITION (1 << 17)
++#define gcvZONE_VG (1 << 18)
++#define gcvZONE_IMAGE (1 << 19)
++#define gcvZONE_UTILITY (1 << 20)
++#define gcvZONE_PARAMETERS (1 << 21)
++#define gcvZONE_BUFOBJ (1 << 22)
++#define gcvZONE_SHADER (1 << 23)
++#define gcvZONE_STREAM_OUT (1 << 24)
++
++/* API definitions. */
++#define gcvZONE_API_HAL (1 << 28)
++#define gcvZONE_API_EGL (2 << 28)
++#define gcvZONE_API_ES11 (3 << 28)
++#define gcvZONE_API_ES20 (4 << 28)
++#define gcvZONE_API_VG11 (5 << 28)
++#define gcvZONE_API_GL (6 << 28)
++#define gcvZONE_API_DFB (7 << 28)
++#define gcvZONE_API_GDI ((gctUINT32)8 << 28)
++#define gcvZONE_API_D3D ((gctUINT32)9 << 28)
++#define gcvZONE_API_ES30 ((gctUINT32)10 << 28)
++
++
++#define gcmZONE_GET_API(zone) ((zone) >> 28)
++/*Set gcdZONE_MASE like 0x0 | gcvZONE_API_EGL
++will enable print EGL module debug info*/
++#define gcdZONE_MASK 0x0FFFFFFF
++
++/* Handy zones. */
++#define gcvZONE_NONE 0
++#define gcvZONE_ALL 0x0FFFFFFF
++
++/*Dump API depth set 1 for API, 2 for API and API behavior*/
++#define gcvDUMP_API_DEPTH 1
++
++/*******************************************************************************
++**
++** gcmTRACE_ZONE
++**
++** Print a message to the debugger if the correct level and zone has been
++** set. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** Level Level of message.
++** Zone Zone of message.
++** Message Message.
++** ... Optional arguments.
++*/
++
++void
++gckOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_DebugTraceZoneN(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_DebugTraceZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++# define gcmTRACE_ZONE gcoOS_DebugTraceZone
++# define gcmkTRACE_ZONE gckOS_DebugTraceZone
++# define gcmkTRACE_ZONE_N gckOS_DebugTraceZoneN
++#elif gcdHAS_ELLIPSIS
++# define gcmTRACE_ZONE(...)
++# define gcmkTRACE_ZONE(...)
++# define gcmkTRACE_ZONE_N(...)
++#else
++ gcmINLINE static void
++ __dummy_trace_zone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++ gcmINLINE static void
++ __dummy_trace_zone_n(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone,
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++
++# define gcmTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE __dummy_trace_zone
++# define gcmkTRACE_ZONE_N __dummy_trace_zone_n
++#endif
++
++/*******************************************************************************
++**
++** gcmDEBUG_ONLY
++**
++** Execute a statement or function only in DEBUG mode.
++**
++** ARGUMENTS:
++**
++** f Statement or function to execute.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++# define gcmDEBUG_ONLY(f) f
++#else
++# define gcmDEBUG_ONLY(f)
++#endif
++
++/*******************************************************************************
++**
++** gcmSTACK_PUSH
++** gcmSTACK_POP
++** gcmSTACK_DUMP
++**
++** Push or pop a function with entry arguments on the trace stack.
++**
++** ARGUMENTS:
++**
++** Function Name of function.
++** Line Line number.
++** Text Optional text.
++** ... Optional arguments for text.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_STACK)
++ void gcoOS_StackPush(IN gctINT8_PTR Identity, IN gctCONST_STRING Function, IN gctINT Line, IN gctCONST_STRING Text, ...);
++ void gcoOS_StackPop(IN gctINT8_PTR Identity, IN gctCONST_STRING Function);
++ void gcoOS_StackDump(void);
++ void gcoOS_StackRemove(IN gctHANDLE Thread);
++
++# define gcmSTACK_PUSH gcoOS_StackPush
++# define gcmSTACK_POP gcoOS_StackPop
++# define gcmSTACK_DUMP gcoOS_StackDump
++# define gcmSTACK_REMOVE gcoOS_StackRemove
++#elif gcdHAS_ELLIPSIS
++# define gcmSTACK_PUSH(...) do { } while (0)
++# define gcmSTACK_POP(...) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++# define gcmSTACK_REMOVE(...) do { } while (0)
++#else
++ gcmINLINE static void
++ __dummy_stack_push(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text, ...
++ )
++ {
++ }
++# define gcmSTACK_PUSH __dummy_stack_push
++# define gcmSTACK_POP(a,b) do { } while (0)
++# define gcmSTACK_DUMP() do { } while (0)
++# define gcmSTACK_REMOVE(a) do { } while (0)
++#endif
++
++/******************************************************************************\
++******************************** Binary Trace **********************************
++\******************************************************************************/
++typedef struct _gcsBINARY_TRACE_MESSAGE * gcsBINARY_TRACE_MESSAGE_PTR;
++typedef struct _gcsBINARY_TRACE_MESSAGE
++{
++ gctUINT32 signature;
++ gctUINT32 pid;
++ gctUINT32 tid;
++ gctUINT32 line;
++ gctUINT32 numArguments;
++ gctUINT8 payload;
++}
++gcsBINARY_TRACE_MESSAGE;
++
++#define gcdBINARY_TRACE_MESSAGE_SIZE 240
++
++#if gcdBINARY_TRACE
++ void
++ gcoOS_BinaryTrace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text OPTIONAL,
++ ...
++ );
++
++ void
++ gckOS_BinaryTrace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text OPTIONAL,
++ ...
++ );
++
++# define gcmBINARY_TRACE gcoOS_BinaryTrace
++# define gcmkBINARY_TRACE gckOS_BinaryTrace
++#elif gcdHAS_ELLIPSIS
++# define gcmBINARY_TRACE(Function, Line, Text, ...)
++# define gcmkBINARY_TRACE(Function, Line, Text, ...)
++#else
++ gcmINLINE static void
++ __dummy_binary_trace(
++ IN gctCONST_STRING Function,
++ IN gctINT Line,
++ IN gctCONST_STRING Text,
++ )
++ {
++ }
++
++# define gcmBINARY_TRACE __dummy_binary_trace
++# define gcmkBINARY_TRACE __dummy_binary_trace
++#endif
++
++/******************************************************************************\
++******************************** Logging Macros ********************************
++\******************************************************************************/
++
++#define gcdHEADER_LEVEL gcvLEVEL_VERBOSE
++
++#ifndef gcdEMPTY_HEADER_FOOTER
++#define gcdEMPTY_HEADER_FOOTER 0
++#endif
++
++#if gcdENABLE_PROFILING
++void
++gcoOS_ProfileDB(
++ IN gctCONST_STRING Function,
++ IN OUT gctBOOL_PTR Initialized
++ );
++
++#define gcmHEADER() \
++ gctINT8 __user__ = 1; \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(&__user__, __FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmHEADER_ARG(...) \
++ gctINT8 __user__ = 1; \
++ static gctBOOL __profile__initialized__ = gcvFALSE; \
++ gcmSTACK_PUSH(&__user__, __FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__)
++#define gcmFOOTER() \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_ARG(...) \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(__FUNCTION__, gcvNULL)
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(&__user__, __FUNCTION__); \
++ gcoOS_ProfileDB(gcvNULL, gcvNULL)
++
++#else /* gcdENABLE_PROFILING */
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmHEADER()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmHEADER()
++#elif gcdHAS_ELLIPSIS
++#define gcmHEADER() \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__user_ptr__, __FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_header(void)
++ {
++ }
++# define gcmHEADER __dummy_header
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmHEADER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++#if gcdEMPTY_HEADER_FOOTER
++# define gcmHEADER_ARG(Text, ...)
++#else
++# define gcmHEADER_ARG(Text, ...) \
++ gctINT8 __user__ = 1; \
++ gctINT8_PTR __user_ptr__ = &__user__; \
++ gcmSTACK_PUSH(__user_ptr__, __FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#endif
++#else
++ gcmINLINE static void
++ __dummy_header_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmHEADER_ARG __dummy_header_arg
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmFOOTER()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER()
++#elif gcdHAS_ELLIPSIS
++# define gcmFOOTER() \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, \
++ status, gcoOS_DebugStatus2Name(status)); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer(void)
++ {
++ }
++# define gcmFOOTER __dummy_footer
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmFOOTER_NO()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER_NO()
++#elif gcdHAS_ELLIPSIS
++#define gcmFOOTER_NO() \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_no(void)
++ {
++ }
++# define gcmFOOTER_NO __dummy_footer_no
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmFOOTER_KILL()
++#elif gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER_KILL()
++#elif gcdHAS_ELLIPSIS
++#define gcmFOOTER_KILL() \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__user_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_footer_kill(void)
++ {
++ }
++# define gcmFOOTER_KILL __dummy_footer_kill
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmFOOTER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++#if gcdEMPTY_HEADER_FOOTER
++# define gcmFOOTER_ARG(Text, ...)
++#else
++# define gcmFOOTER_ARG(Text, ...) \
++ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \
++ gcmBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__user_ptr__ -= 1
++#endif
++#else
++ gcmINLINE static void
++ __dummy_footer_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmFOOTER_ARG __dummy_footer_arg
++#endif
++
++#endif /* gcdENABLE_PROFILING */
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmkHEADER()
++#elif gcdHAS_ELLIPSIS
++#define gcmkHEADER() \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d)", __FUNCTION__, __LINE__)
++#else
++ gcmINLINE static void
++ __dummy_kheader(void)
++ {
++ }
++# define gcmkHEADER __dummy_kheader
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmkHEADER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++# define gcmkHEADER_ARG(Text, ...) \
++ gctINT8 __kernel__ = 1; \
++ gctINT8_PTR __kernel_ptr__ = &__kernel__; \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__)
++#else
++ gcmINLINE static void
++ __dummy_kheader_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkHEADER_ARG __dummy_kheader_arg
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmkFOOTER()
++#elif gcdHAS_ELLIPSIS
++#define gcmkFOOTER() \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, status); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): status=%d(%s)", \
++ __FUNCTION__, __LINE__, status, gckOS_DebugStatus2Name(status)); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter(void)
++ {
++ }
++# define gcmkFOOTER __dummy_kfooter
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++#define gcmkFOOTER_NO()
++#elif gcdHAS_ELLIPSIS
++#define gcmkFOOTER_NO() \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d)", __FUNCTION__, __LINE__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_no(void)
++ {
++ }
++# define gcmkFOOTER_NO __dummy_kfooter_no
++#endif
++
++#ifdef gcdFSL_REL_BUILD
++# define gcmkFOOTER_ARG(Text, ...)
++#elif gcdHAS_ELLIPSIS
++# define gcmkFOOTER_ARG(Text, ...) \
++ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \
++ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \
++ "--%s(%d): " Text, \
++ __FUNCTION__, __LINE__, __VA_ARGS__); \
++ *__kernel_ptr__ -= 1
++#else
++ gcmINLINE static void
++ __dummy_kfooter_arg(
++ IN gctCONST_STRING Text,
++ ...
++ )
++ {
++ }
++# define gcmkFOOTER_ARG __dummy_kfooter_arg
++#endif
++
++#define gcmOPT_VALUE(ptr) (((ptr) == gcvNULL) ? 0 : *(ptr))
++#define gcmOPT_VALUE_INDEX(ptr, index) (((ptr) == gcvNULL) ? 0 : ptr[index])
++#define gcmOPT_POINTER(ptr) (((ptr) == gcvNULL) ? gcvNULL : *(ptr))
++#define gcmOPT_STRING(ptr) (((ptr) == gcvNULL) ? "(nil)" : (ptr))
++
++void
++gckOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_PrintN(
++ IN gctUINT ArgumentSize,
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gckOS_CopyPrint(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#define gcmPRINT gcoOS_Print
++#define gcmkPRINT gckOS_Print
++#define gcmkPRINT_N gckOS_PrintN
++
++#if gcdPRINT_VERSION
++# define gcmPRINT_VERSION() do { \
++ _gcmPRINT_VERSION(gcm); \
++ gcmSTACK_DUMP(); \
++ } while (0)
++# define gcmkPRINT_VERSION() _gcmPRINT_VERSION(gcmk)
++# define _gcmPRINT_VERSION(prefix) \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "Vivante HAL version %d.%d.%d build %d %s %s", \
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, \
++ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME )
++#else
++# define gcmPRINT_VERSION() do { gcmSTACK_DUMP(); } while (gcvFALSE)
++# define gcmkPRINT_VERSION() do { } while (gcvFALSE)
++#endif
++
++typedef enum _gceDUMP_BUFFER
++{
++ gceDUMP_BUFFER_CONTEXT,
++ gceDUMP_BUFFER_USER,
++ gceDUMP_BUFFER_KERNEL,
++ gceDUMP_BUFFER_LINK,
++ gceDUMP_BUFFER_WAITLINK,
++ gceDUMP_BUFFER_FROM_USER,
++}
++gceDUMP_BUFFER;
++
++void
++gckOS_DumpBuffer(
++ IN gckOS Os,
++ IN gctPOINTER Buffer,
++ IN gctUINT Size,
++ IN gceDUMP_BUFFER Type,
++ IN gctBOOL CopyMessage
++ );
++
++#define gcmkDUMPBUFFER gckOS_DumpBuffer
++
++#if gcdDUMP_COMMAND
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage) \
++ gcmkDUMPBUFFER(Os, Buffer, Size, Type, CopyMessage)
++#else
++# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage)
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++void
++gckOS_DebugFlush(
++ gctCONST_STRING CallerName,
++ gctUINT LineNumber,
++ gctUINT32 DmaAddress
++ );
++
++# define gcmkDEBUGFLUSH(DmaAddress) \
++ gckOS_DebugFlush(__FUNCTION__, __LINE__, DmaAddress)
++#else
++# define gcmkDEBUGFLUSH(DmaAddress)
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_FRAMERATE
++**
++** Print average frame rate
++**
++*/
++#if gcdDUMP_FRAMERATE
++ gceSTATUS
++ gcfDumpFrameRate(
++ void
++ );
++# define gcmDUMP_FRAMERATE gcfDumpFrameRate
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_FRAMERATE(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_frame_rate(
++ void
++ )
++ {
++ }
++# define gcmDUMP_FRAMERATE __dummy_dump_frame_rate
++#endif
++
++
++/*******************************************************************************
++**
++** gcmDUMP
++**
++** Print a dump message.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++#if gcdDUMP
++ gceSTATUS
++ gcfDump(
++ IN gcoOS Os,
++ IN gctCONST_STRING String,
++ ...
++ );
++# define gcmDUMP gcfDump
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP(...)
++#else
++ gcmINLINE static void
++ __dummy_dump(
++ IN gcoOS Os,
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP __dummy_dump
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_DATA
++**
++** Add data to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++ gceSTATUS
++ gcfDumpData(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_DATA gcfDumpData
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_data(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_DATA __dummy_dump_data
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_BUFFER
++**
++** Print a buffer to the dump.
++**
++** ARGUMENTS:
++**
++** gctSTRING Tag
++** Tag for dump.
++**
++** gctUINT32 Physical
++** Physical address of buffer.
++**
++** gctPOINTER Logical
++** Logical address of buffer.
++**
++** gctUINT32 Offset
++** Offset into buffer.
++**
++** gctSIZE_T Bytes
++** Number of bytes.
++*/
++
++#if gcdDUMP || gcdDUMP_COMMAND
++gceSTATUS
++gcfDumpBuffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ );
++# define gcmDUMP_BUFFER gcfDumpBuffer
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_BUFFER(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_buffer(
++ IN gcoOS Os,
++ IN gctSTRING Tag,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Bytes
++ )
++ {
++ }
++# define gcmDUMP_BUFFER __dummy_dump_buffer
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API
++**
++** Print a dump message for a high level API prefixed by the function name.
++**
++** ARGUMENTS:
++**
++** gctSTRING Message.
++**
++** ... Optional arguments.
++*/
++gceSTATUS gcfDumpApi(IN gctCONST_STRING String, ...);
++#if gcdDUMP_API
++# define gcmDUMP_API gcfDumpApi
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api(
++ IN gctCONST_STRING Message,
++ ...
++ )
++ {
++ }
++# define gcmDUMP_API __dummy_dump_api
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY
++**
++** Print an array of data.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Size.
++*/
++gceSTATUS gcfDumpArray(IN gctCONST_POINTER Data, IN gctUINT32 Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY gcfDumpArray
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API_ARRAY(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY __dummy_dump_api_array
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_ARRAY_TOKEN
++**
++** Print an array of data terminated by a token.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to array.
++** gctUINT32 Termination.
++*/
++gceSTATUS gcfDumpArrayToken(IN gctCONST_POINTER Data, IN gctUINT32 Termination);
++#if gcdDUMP_API
++# define gcmDUMP_API_ARRAY_TOKEN gcfDumpArrayToken
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API_ARRAY_TOKEN(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_array_token(
++ IN gctCONST_POINTER Data,
++ IN gctUINT32 Termination
++ )
++ {
++ }
++# define gcmDUMP_API_ARRAY_TOKEN __dummy_dump_api_array_token
++#endif
++
++/*******************************************************************************
++**
++** gcmDUMP_API_DATA
++**
++** Print an array of bytes.
++**
++** ARGUMENTS:
++**
++** gctCONST_POINTER Pointer to array.
++** gctSIZE_T Size.
++*/
++gceSTATUS gcfDumpApiData(IN gctCONST_POINTER Data, IN gctSIZE_T Size);
++#if gcdDUMP_API
++# define gcmDUMP_API_DATA gcfDumpApiData
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_API_DATA(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_api_data(
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Size
++ )
++ {
++ }
++# define gcmDUMP_API_DATA __dummy_dump_api_data
++#endif
++
++/*******************************************************************************
++** gcmDUMP_2D_COMMAND
++**
++** Print the 2D command buffer.
++**
++** ARGUMENTS:
++**
++** gctUINT32_PTR Pointer to the command buffer.
++** gctUINT32 Command buffer size.
++*/
++gceSTATUS gcfDump2DCommand(IN gctUINT32_PTR Command, IN gctUINT32 Size);
++#if gcdDUMP_2D
++# define gcmDUMP_2D_COMMAND gcfDump2DCommand
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_2D_COMMAND(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_2d_command(
++ IN gctUINT32_PTR Command,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_2D_COMMAND __dummy_dump_2d_command
++#endif
++
++/*******************************************************************************
++** gcmDUMP_2D_SURFACE
++**
++** Print the 2D surface memory.
++**
++** ARGUMENTS:
++**
++** gctBOOL Src.
++** gctUINT32 Address.
++*/
++gceSTATUS gcfDump2DSurface(IN gctBOOL Src, IN gctUINT32 Address);
++#if gcdDUMP_2D
++# define gcmDUMP_2D_SURFACE gcfDump2DSurface
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_2D_SURFACE(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_2d_surface(
++ IN gctBOOL Src,
++ IN gctUINT32 Address
++ )
++ {
++ }
++# define gcmDUMP_2D_SURFACE __dummy_dump_2d_surface
++#endif
++
++/*******************************************************************************
++** gcmDUMP_ADD_MEMORY_INFO
++**
++** Record the memory info.
++**
++** ARGUMENTS:
++**
++** gctUINT32 Address.
++** gctSIZE_T Size.
++*/
++gceSTATUS gcfAddMemoryInfo(IN gctUINT32 GPUAddress, IN gctPOINTER Logical, IN gctUINT32 Physical, IN gctUINT32 Size);
++#if gcdDUMP_2D
++# define gcmDUMP_ADD_MEMORY_INFO gcfAddMemoryInfo
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_ADD_MEMORY_INFO(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_add_memory_info(
++ IN gctUINT32 GPUAddress,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Size
++ )
++ {
++ }
++# define gcmDUMP_ADD_MEMORY_INFO __dummy_dump_add_memory_info
++#endif
++
++/*******************************************************************************
++** gcmDUMP_DEL_MEMORY_INFO
++**
++** Record the memory info.
++**
++** ARGUMENTS:
++**
++** gctUINT32 Address.
++*/
++gceSTATUS gcfDelMemoryInfo(IN gctUINT32 Address);
++#if gcdDUMP_2D
++# define gcmDUMP_DEL_MEMORY_INFO gcfDelMemoryInfo
++#elif gcdHAS_ELLIPSIS
++# define gcmDUMP_DEL_MEMORY_INFO(...)
++#else
++ gcmINLINE static void
++ __dummy_dump_del_memory_info(
++ IN gctUINT32 Address
++ )
++ {
++ }
++# define gcmDUMP_DEL_MEMORY_INFO __dummy_dump_del_memory_info
++#endif
++
++#if gcdDUMP_2D
++extern gctPOINTER dumpMemInfoListMutex;
++extern gctBOOL dump2DFlag;
++#endif
++
++/*******************************************************************************
++**
++** gcmTRACE_RELEASE
++**
++** Print a message to the shader debugger.
++**
++** ARGUMENTS:
++**
++** message Message.
++** ... Optional arguments.
++*/
++
++#define gcmTRACE_RELEASE gcoOS_DebugShaderTrace
++
++void
++gcoOS_DebugShaderTrace(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++void
++gcoOS_SetDebugShaderFiles(
++ IN gctCONST_STRING VSFileName,
++ IN gctCONST_STRING FSFileName
++ );
++
++void
++gcoOS_SetDebugShaderFileType(
++ IN gctUINT32 ShaderType
++ );
++
++void
++gcoOS_EnableDebugBuffer(
++ IN gctBOOL Enable
++ );
++
++/*******************************************************************************
++**
++** gcmBREAK
++**
++** Break into the debugger. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** None.
++*/
++
++void
++gcoOS_DebugBreak(
++ void
++ );
++
++void
++gckOS_DebugBreak(
++ void
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_BREAK)
++# define gcmBREAK gcoOS_DebugBreak
++# define gcmkBREAK gckOS_DebugBreak
++#else
++# define gcmBREAK()
++# define gcmkBREAK()
++#endif
++
++/*******************************************************************************
++**
++** gcmASSERT
++**
++** Evaluate an expression and break into the debugger if the expression
++** evaluates to false. In retail mode this macro does nothing.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define _gcmASSERT(prefix, exp) \
++ do \
++ { \
++ if (!(exp)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ASSERT at %s(%d)", \
++ __FUNCTION__, __LINE__); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ "(%s)", #exp); \
++ prefix##BREAK(); \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmASSERT(exp) _gcmASSERT(gcm, exp)
++# define gcmkASSERT(exp) _gcmASSERT(gcmk, exp)
++#else
++# define gcmASSERT(exp)
++# define gcmkASSERT(exp)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY
++**
++** Verify if an expression returns true. If the expression does not
++** evaluates to true, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** exp Expression to evaluate.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY(exp) gcmASSERT(exp)
++# define gcmkVERIFY(exp) gcmkASSERT(exp)
++#else
++# define gcmVERIFY(exp) exp
++# define gcmkVERIFY(exp) exp
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_OK
++**
++** Verify a fucntion returns gcvSTATUS_OK. If the function does not return
++** gcvSTATUS_OK, an assertion will happen in debug mode.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++
++void
++gcoOS_Verify(
++ IN gceSTATUS status
++ );
++
++void
++gckOS_Verify(
++ IN gceSTATUS status
++ );
++
++#if gcmIS_DEBUG(gcdDEBUG_ASSERT)
++# define gcmVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ gcoOS_Verify(verifyStatus); \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gcmASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++# define gcmkVERIFY_OK(func) \
++ do \
++ { \
++ gceSTATUS verifyStatus = func; \
++ if (verifyStatus != gcvSTATUS_OK) \
++ { \
++ gcmkTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmkVERIFY_OK(%d): function returned %d", \
++ __LINE__, verifyStatus \
++ ); \
++ } \
++ gckOS_Verify(verifyStatus); \
++ gcmkASSERT(verifyStatus == gcvSTATUS_OK); \
++ } \
++ while (gcvFALSE)
++#else
++# define gcmVERIFY_OK(func) func
++# define gcmkVERIFY_OK(func) func
++#endif
++
++gctCONST_STRING
++gcoOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++gctCONST_STRING
++gckOS_DebugStatus2Name(
++ gceSTATUS status
++ );
++
++/*******************************************************************************
++**
++** gcmERR_BREAK
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_BREAK(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_BREAK(func) _gcmERR_BREAK(gcm, func)
++#define gcmkERR_BREAK(func) _gcmkERR_BREAK(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmERR_RETURN
++**
++** Executes a return on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define _gcmkERR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ prefix##FOOTER(); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++#define gcmERR_RETURN(func) _gcmERR_RETURN(gcm, func)
++#define gcmkERR_RETURN(func) _gcmkERR_RETURN(gcmk, func)
++
++
++/*******************************************************************************
++**
++** gcmONERROR
++**
++** Jump to the error handler in case there is an error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkONERROR(prefix, func) \
++ do \
++ { \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \
++ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ goto OnError; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmONERROR(func) _gcmONERROR(gcm, func)
++#define gcmkONERROR(func) _gcmkONERROR(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmkSAFECASTSIZET
++**
++** Check wether value of a gctSIZE_T varible beyond the capability
++** of 32bits GPU hardware.
++**
++** ASSUMPTIONS:
++**
++**
++**
++** ARGUMENTS:
++**
++** x A gctUINT32 variable
++** y A gctSIZE_T variable
++*/
++#define gcmkSAFECASTSIZET(x, y) \
++ do \
++ { \
++ gctUINT32 tmp = (gctUINT32)(y); \
++ if (gcmSIZEOF(gctSIZE_T) > gcmSIZEOF(gctUINT32)) \
++ { \
++ gcmkASSERT(tmp <= gcvMAXUINT32); \
++ } \
++ (x) = tmp; \
++ } \
++ while (gcvFALSE)
++
++#define gcmSAFECASTSIZET(x, y) \
++ do \
++ { \
++ gctUINT32 tmp = (gctUINT32)(y); \
++ if (gcmSIZEOF(gctSIZE_T) > gcmSIZEOF(gctUINT32)) \
++ { \
++ gcmASSERT(tmp <= gcvMAXUINT32); \
++ } \
++ (x) = tmp; \
++ } \
++ while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmVERIFY_LOCK
++**
++** Verifies whether the surface is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_LOCK(surfaceInfo) \
++ if (!surfaceInfo->node.valid) \
++ { \
++ gcmONERROR(gcvSTATUS_MEMORY_UNLOCKED); \
++ } \
++
++/*******************************************************************************
++**
++** gcmVERIFY_NODE_LOCK
++**
++** Verifies whether the surface node is locked.
++**
++** ARGUMENTS:
++**
++** surfaceInfo Pointer to the surface iniformational structure.
++*/
++#define gcmVERIFY_NODE_LOCK(surfaceNode) \
++ if (!(surfaceNode)->valid) \
++ { \
++ status = gcvSTATUS_MEMORY_UNLOCKED; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmBADOBJECT_BREAK
++**
++** Executes a break statement on bad object.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#define gcmBADOBJECT_BREAK(obj, t) \
++ if ((obj == gcvNULL) \
++ || (((gcsOBJECT *)(obj))->type != t) \
++ ) \
++ { \
++ status = gcvSTATUS_INVALID_OBJECT; \
++ break; \
++ } \
++ do { } while (gcvFALSE)
++
++/*******************************************************************************
++**
++** gcmCHECK_STATUS
++**
++** Executes a break statement on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** func Function to evaluate.
++*/
++#define _gcmCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gcoOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define _gcmkCHECK_STATUS(prefix, func) \
++ do \
++ { \
++ last = func; \
++ if (gcmIS_ERROR(last)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \
++ last, gckOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \
++ status = last; \
++ } \
++ } \
++ while (gcvFALSE)
++#define gcmCHECK_STATUS(func) _gcmCHECK_STATUS(gcm, func)
++#define gcmkCHECK_STATUS(func) _gcmkCHECK_STATUS(gcmk, func)
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT(prefix, arg) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, #prefix "VERIFY_ARGUMENT failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); \
++ return gcvSTATUS_INVALID_ARGUMENT; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcmk, arg)
++
++/*******************************************************************************
++**
++** gcmDEBUG_VERIFY_ARGUMENT
++**
++** Works just like gcmVERIFY_ARGUMENT, but is only valid in debug mode.
++** Use this to verify arguments inside non-public API functions.
++*/
++#if gcdDEBUG
++# define gcmDEBUG_VERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg) _gcmkVERIFY_ARGUMENT(gcm, arg)
++#else
++# define gcmDEBUG_VERIFY_ARGUMENT(arg)
++# define gcmkDEBUG_VERIFY_ARGUMENT(arg)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFY_ARGUMENT_RETURN
++**
++** Assert if an argument does not apply to the specified expression. If
++** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be
++** returned from the current function. In retail mode this macro does
++** nothing.
++**
++** ARGUMENTS:
++**
++** arg Argument to evaluate.
++*/
++# define _gcmVERIFY_ARGUMENT_RETURN(prefix, arg, value) \
++ do \
++ { \
++ if (!(arg)) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "gcmVERIFY_ARGUMENT_RETURN failed:"); \
++ prefix##ASSERT(arg); \
++ prefix##FOOTER_ARG("value=%d", value); \
++ return value; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcm, arg, value)
++# define gcmkVERIFY_ARGUMENT_RETURN(arg, value) \
++ _gcmVERIFY_ARGUMENT_RETURN(gcmk, arg, value)
++
++#define MAX_LOOP_COUNT 0x7FFFFFFF
++
++/******************************************************************************\
++****************************** User Debug Option ******************************
++\******************************************************************************/
++
++/* User option. */
++typedef enum _gceDEBUG_MSG
++{
++ gcvDEBUG_MSG_NONE,
++ gcvDEBUG_MSG_ERROR,
++ gcvDEBUG_MSG_WARNING
++}
++gceDEBUG_MSG;
++
++typedef struct _gcsUSER_DEBUG_OPTION
++{
++ gceDEBUG_MSG debugMsg;
++}
++gcsUSER_DEBUG_OPTION;
++
++gcsUSER_DEBUG_OPTION *
++gcGetUserDebugOption(
++ void
++ );
++
++#if defined(ANDROID)
++struct _gcoOS_SymbolsList
++{
++#if gcdENABLE_3D
++ gcePATCH_ID patchId;
++#endif
++ const char * symList[10];
++};
++#endif
++
++#if gcdHAS_ELLIPSIS
++#define gcmUSER_DEBUG_MSG(level, ...) \
++ do \
++ { \
++ if (level <= gcGetUserDebugOption()->debugMsg) \
++ { \
++ gcoOS_Print(__VA_ARGS__); \
++ } \
++ } while (gcvFALSE)
++
++#define gcmUSER_DEBUG_ERROR_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_ERROR, "Error: " __VA_ARGS__)
++#define gcmUSER_DEBUG_WARNING_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_WARNING, "Warring: " __VA_ARGS__)
++#else
++#define gcmUSER_DEBUG_MSG
++#define gcmUSER_DEBUG_ERROR_MSG
++#define gcmUSER_DEBUG_WARNING_MSG
++#endif
++
++/*******************************************************************************
++**
++** A set of macros to aid state loading.
++**
++** ARGUMENTS:
++**
++** CommandBuffer Pointer to a gcoCMDBUF object.
++** StateDelta Pointer to a gcsSTATE_DELTA state delta structure.
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** PartOfContext Whether or not the state is a part of the context.
++** FixedPoint Whether or not the state is of the fixed point format.
++** Count Number of consecutive states to be loaded.
++** Address State address.
++** Data Data to be set to the state.
++*/
++
++/*----------------------------------------------------------------------------*/
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count) \
++ CommandBuffer->lastLoadStatePtr = gcmPTR_TO_UINT64(Memory); \
++ CommandBuffer->lastLoadStateAddress = Address; \
++ CommandBuffer->lastLoadStateCount = Count
++
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address) \
++ gcmASSERT( \
++ (gctUINT) (Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastLoadStatePtr, gctUINT32_PTR) - 1) \
++ == \
++ (gctUINT) (Address - CommandBuffer->lastLoadStateAddress) \
++ ); \
++ \
++ gcmASSERT(CommandBuffer->lastLoadStateCount > 0); \
++ \
++ CommandBuffer->lastLoadStateCount -= 1
++
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer) \
++ gcmASSERT(CommandBuffer->lastLoadStateCount == 0);
++
++# define gcmDEFINELOADSTATEBASE() \
++ gctUINT32_PTR LoadStateBase;
++
++# define gcmSETLOADSTATEBASE(CommandBuffer, OutSide) \
++ if (OutSide) \
++ {\
++ LoadStateBase = (gctUINT32_PTR)*OutSide; \
++ }\
++ else\
++ {\
++ LoadStateBase = (gctUINT_PTR)CommandBuffer->buffer;\
++ }
++
++
++# define gcmVERIFYLOADSTATEALIGNED(CommandBuffer, Memory) \
++ gcmASSERT(((Memory - LoadStateBase) & 1) == 0);
++
++# define gcmUNSETLOADSTATEBASE() \
++ LoadStateBase = LoadStateBase;
++
++#else
++
++# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count)
++# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address)
++# define gcmVERIFYLOADSTATEDONE(CommandBuffer)
++
++# define gcmDEFINELOADSTATEBASE()
++# define gcmSETLOADSTATEBASE(CommandBuffer, OutSide)
++# define gcmVERIFYLOADSTATEALIGNED(CommandBuffer, Memory)
++# define gcmUNSETLOADSTATEBASE()
++
++#endif
++
++#if gcdSECURE_USER
++
++# define gcmDEFINESECUREUSER() \
++ gctUINT __secure_user_offset__; \
++ gctUINT32_PTR __secure_user_hintArray__;
++
++# define gcmBEGINSECUREUSER() \
++ __secure_user_offset__ = reserve->lastOffset; \
++ \
++ __secure_user_hintArray__ = gcmUINT64_TO_PTR(reserve->hintArrayTail)
++
++# define gcmENDSECUREUSER() \
++ reserve->hintArrayTail = gcmPTR_TO_UINT64(__secure_user_hintArray__)
++
++# define gcmSKIPSECUREUSER() \
++ __secure_user_offset__ += gcmSIZEOF(gctUINT32)
++
++# define gcmUPDATESECUREUSER() \
++ *__secure_user_hintArray__ = __secure_user_offset__; \
++ \
++ __secure_user_offset__ += gcmSIZEOF(gctUINT32); \
++ __secure_user_hintArray__ += 1
++
++#else
++
++# define gcmDEFINESECUREUSER()
++# define gcmBEGINSECUREUSER()
++# define gcmENDSECUREUSER()
++# define gcmSKIPSECUREUSER()
++# define gcmUPDATESECUREUSER()
++
++#endif
++
++/*----------------------------------------------------------------------------*/
++
++#if gcdDUMP
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data) \
++ if (FixedPoint) \
++ { \
++ gcmDUMP(gcvNULL, "#[state.x 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ } \
++ else \
++ { \
++ gcmDUMP(gcvNULL, "#[state 0x%04X 0x%08X]", \
++ Address, Data \
++ ); \
++ }
++#else
++# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data)
++#endif
++
++#define gcmDEFINESTATEBUFFER(CommandBuffer, StateDelta, Memory, ReserveSize) \
++ gcmDEFINESECUREUSER() \
++ gctSIZE_T ReserveSize; \
++ gcoCMDBUF CommandBuffer; \
++ gctUINT32_PTR Memory; \
++ gcsSTATE_DELTA_PTR StateDelta
++
++#define gcmBEGINSTATEBUFFER(Hardware, CommandBuffer, StateDelta, Memory, ReserveSize) \
++{ \
++ gcmONERROR(gcoBUFFER_Reserve( \
++ Hardware->buffer, ReserveSize, gcvTRUE, gcvCOMMAND_3D, &CommandBuffer \
++ )); \
++ \
++ Memory = (gctUINT32_PTR) gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \
++ \
++ StateDelta = Hardware->delta; \
++ \
++ gcmBEGINSECUREUSER(); \
++}
++
++#define gcmENDSTATEBUFFER(Hardware, CommandBuffer, Memory, ReserveSize) \
++{ \
++ gcmENDSECUREUSER(); \
++ \
++ gcmASSERT( \
++ gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT8_PTR) + ReserveSize \
++ == \
++ (gctUINT8_PTR) Memory \
++ ); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, Count) \
++{ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++ gcmASSERT((gctUINT32)Count <= 1024); \
++ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count); \
++ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmENDSTATEBATCH(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ gcmSAFECASTSIZET(__temp_data32__, Data); \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, 0, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, Mask, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++
++#define gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETFILLER(CommandBuffer, Memory) \
++{ \
++ gcmVERIFYLOADSTATEDONE(CommandBuffer); \
++ \
++ Memory += 1; \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++
++#define gcmSETSINGLECTRLSTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++
++
++#define gcmSETSEMASTALLPIPE(StateDelta, CommandBuffer, Memory, Data) \
++{ \
++ gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, gcvFALSE, AQSemaphoreRegAddrs, Data); \
++ \
++ *Memory++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \
++ \
++ *Memory++ = Data; \
++ \
++ gcmDUMP(gcvNULL, "#[stall 0x%08X 0x%08X]", \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END), \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE)); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*******************************************************************************
++**
++** gcmSETSTARTDECOMMAND
++**
++** Form a START_DE command.
++**
++** ARGUMENTS:
++**
++** Memory Destination memory pointer of gctUINT32_PTR type.
++** Count Number of the rectangles.
++*/
++
++#define gcmSETSTARTDECOMMAND(Memory, Count) \
++{ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \
++ \
++ *Memory++ = 0xDEADDEED; \
++}
++
++/*****************************************
++** Temp command buffer macro
++*/
++#define gcmDEFINESTATEBUFFER_NEW(CommandBuffer, StateDelta, Memory) \
++ gcmDEFINESECUREUSER() \
++ gcmDEFINELOADSTATEBASE() \
++ gcsTEMPCMDBUF CommandBuffer = gcvNULL; \
++ gctUINT32_PTR Memory; \
++ gcsSTATE_DELTA_PTR StateDelta
++
++
++#define gcmBEGINSTATEBUFFER_NEW(Hardware, CommandBuffer, StateDelta, Memory, OutSide) \
++{ \
++ if (OutSide) \
++ {\
++ Memory = (gctUINT32_PTR)*OutSide; \
++ }\
++ else \
++ {\
++ gcmONERROR(gcoBUFFER_StartTEMPCMDBUF( \
++ Hardware->buffer, &CommandBuffer \
++ ));\
++ \
++ Memory = (gctUINT32_PTR)(CommandBuffer->buffer); \
++ \
++ }\
++ StateDelta = Hardware->delta; \
++ \
++ gcmBEGINSECUREUSER(); \
++ gcmSETLOADSTATEBASE(CommandBuffer,OutSide);\
++}
++
++#define gcmENDSTATEBUFFER_NEW(Hardware, CommandBuffer, Memory, OutSide) \
++{ \
++ gcmENDSECUREUSER(); \
++ \
++ if (OutSide) \
++ {\
++ *OutSide = Memory; \
++ }\
++ else \
++ {\
++ CommandBuffer->currentByteSize = (gctUINT32)((gctUINT8_PTR)Memory - \
++ (gctUINT8_PTR)CommandBuffer->buffer); \
++ \
++ gcmONERROR(gcoBUFFER_EndTEMPCMDBUF(Hardware->buffer));\
++ }\
++ gcmUNSETLOADSTATEBASE()\
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, Count) \
++{ \
++ gcmVERIFYLOADSTATEALIGNED(CommandBuffer,Memory);\
++ gcmASSERT((gctUINT32)Count <= 1024); \
++ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmENDSTATEBATCH_NEW(CommandBuffer, Memory) \
++ gcmVERIFYLOADSTATEALIGNED(CommandBuffer,Memory);
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSTATEDATA_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, 0, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcoHARDWARE_UpdateDelta( \
++ StateDelta, Address, Mask, __temp_data32__ \
++ ); \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++
++#define gcmSETCTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETFILLER_NEW(CommandBuffer, Memory) \
++{ \
++ Memory += 1; \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++/*----------------------------------------------------------------------------*/
++
++#define gcmSETSINGLESTATE_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++
++#define gcmSETSINGLECTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETCTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, Address, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++
++
++#define gcmSETSEMASTALLPIPE_NEW(StateDelta, CommandBuffer, Memory, Data) \
++{ \
++ gcmSETSINGLESTATE_NEW(StateDelta, CommandBuffer, Memory, gcvFALSE, AQSemaphoreRegAddrs, Data); \
++ \
++ *Memory++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \
++ \
++ *Memory++ = Data; \
++ \
++ gcmDUMP(gcvNULL, "#[stall 0x%08X 0x%08X]", \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END), \
++ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE)); \
++ \
++ gcmSKIPSECUREUSER(); \
++}
++
++#define gcmSETSTARTDECOMMAND_NEW(CommandBuffer, Memory, Count) \
++{ \
++ *Memory++ \
++ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \
++ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \
++ \
++ *Memory++ = 0xDEADDEED; \
++ \
++}
++
++#define gcmSETSTATEDATA_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSINGLESTATE_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \
++}
++
++#define gcmSETSTATEDATA_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ gcmSAFECASTSIZET(__temp_data32__, Data); \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSTATEDATAWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gctUINT32 __temp_data32__; \
++ \
++ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \
++ \
++ __temp_data32__ = Data; \
++ \
++ *Memory++ = __temp_data32__; \
++ \
++ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \
++ \
++ gcmUPDATESECUREUSER(); \
++}
++
++#define gcmSETSINGLESTATE_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATA_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmSETSINGLESTATEWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data) \
++{ \
++ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \
++ gcmSETSTATEDATAWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \
++ Address, Mask, Data); \
++ gcmENDSTATEBATCH(CommandBuffer, Memory); \
++}
++
++#define gcmDEFINESTATEBUFFER_NEW_FAST(CommandBuffer, Memory) \
++ gcmDEFINESECUREUSER() \
++ gcmDEFINELOADSTATEBASE() \
++ gcsTEMPCMDBUF CommandBuffer = gcvNULL; \
++ gctUINT32_PTR Memory;
++
++#define gcmDEFINESTATEBUFFER_FAST(CommandBuffer, Memory, ReserveSize) \
++ gcmDEFINESECUREUSER() \
++ gctSIZE_T ReserveSize; \
++ gcoCMDBUF CommandBuffer; \
++ gctUINT32_PTR Memory;
++
++#define gcmBEGINSTATEBUFFER_FAST(Hardware, CommandBuffer, Memory, ReserveSize) \
++{ \
++ gcmONERROR(gcoBUFFER_Reserve( \
++ Hardware->buffer, ReserveSize, gcvTRUE, &CommandBuffer \
++ )); \
++ \
++ Memory = (gctUINT32_PTR) gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \
++ \
++ gcmBEGINSECUREUSER(); \
++}
++
++#define gcmBEGINSTATEBUFFER_NEW_FAST(Hardware, CommandBuffer, Memory, OutSide) \
++{ \
++ if (OutSide) \
++ {\
++ Memory = (gctUINT32_PTR)*OutSide; \
++ }\
++ else \
++ {\
++ gcmONERROR(gcoBUFFER_StartTEMPCMDBUF( \
++ Hardware->buffer, &CommandBuffer \
++ ));\
++ \
++ Memory = (gctUINT32_PTR)(CommandBuffer->buffer); \
++ \
++ }\
++ \
++ gcmBEGINSECUREUSER(); \
++ gcmSETLOADSTATEBASE(CommandBuffer,OutSide);\
++}
++/*******************************************************************************
++**
++** gcmCONFIGUREUNIFORMS
++**
++** Configure uniforms according to chip and numConstants.
++*/
++#if !gcdENABLE_UNIFIED_CONSTANT
++#define gcmCONFIGUREUNIFORMS(ChipModel, ChipRevision, NumConstants, \
++ UnifiedConst, VsConstBase, PsConstBase, VsConstMax, PsConstMax, ConstMax) \
++{ \
++ if (ChipModel == gcv2000 && ChipRevision == 0x5118) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ else if (NumConstants == 320) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */ \
++ else if (NumConstants > 256 && ChipModel == gcv1000) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ else if (NumConstants > 256) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 256; \
++ ConstMax = 512; \
++ } \
++ else if (NumConstants == 256) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 256; \
++ ConstMax = 512; \
++ } \
++ else \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 168; \
++ PsConstMax = 64; \
++ ConstMax = 232; \
++ } \
++}
++#else
++#define gcmCONFIGUREUNIFORMS(ChipModel, ChipRevision, NumConstants, \
++ UnifiedConst, VsConstBase, PsConstBase, VsConstMax, PsConstMax, ConstMax) \
++{ \
++ if (NumConstants > 256) \
++ { \
++ UnifiedConst = gcvTRUE; \
++ VsConstBase = gcregSHUniformsRegAddrs; \
++ PsConstBase = gcregSHUniformsRegAddrs; \
++ ConstMax = NumConstants; \
++ VsConstMax = 256; \
++ PsConstMax = ConstMax - VsConstMax; \
++ } \
++ else if (NumConstants == 256) \
++ { \
++ if (ChipModel == gcv2000 && ChipRevision == 0x5118) \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 64; \
++ ConstMax = 320; \
++ } \
++ else \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 256; \
++ PsConstMax = 256; \
++ ConstMax = 512; \
++ } \
++ } \
++ else \
++ { \
++ UnifiedConst = gcvFALSE; \
++ VsConstBase = AQVertexShaderConstRegAddrs; \
++ PsConstBase = AQPixelShaderConstRegAddrs; \
++ VsConstMax = 168; \
++ PsConstMax = 64; \
++ ConstMax = 232; \
++ } \
++}
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_base_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver.h 2016-06-19 22:11:55.233144731 +0200
+@@ -0,0 +1,1136 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_driver_h_
++#define __gc_hal_driver_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#if gcdENABLE_VG
++#include "gc_hal_driver_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++#define IOCTL_GCHAL_KERNEL_INTERFACE 30001
++#define IOCTL_GCHAL_TERMINATE 30002
++
++#undef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++typedef enum _gceHAL_COMMAND_CODES
++{
++ /* Generic query. */
++ gcvHAL_QUERY_VIDEO_MEMORY,
++ gcvHAL_QUERY_CHIP_IDENTITY,
++
++ /* Contiguous memory. */
++ gcvHAL_ALLOCATE_NON_PAGED_MEMORY,
++ gcvHAL_FREE_NON_PAGED_MEMORY,
++ gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY,
++ gcvHAL_FREE_CONTIGUOUS_MEMORY,
++
++ /* Video memory allocation. */
++ gcvHAL_ALLOCATE_VIDEO_MEMORY, /* Enforced alignment. */
++ gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY, /* No alignment. */
++ gcvHAL_RELEASE_VIDEO_MEMORY,
++
++ /* Physical-to-logical mapping. */
++ gcvHAL_MAP_MEMORY,
++ gcvHAL_UNMAP_MEMORY,
++
++ /* Logical-to-physical mapping. */
++ gcvHAL_MAP_USER_MEMORY,
++ gcvHAL_UNMAP_USER_MEMORY,
++
++ /* Surface lock/unlock. */
++ gcvHAL_LOCK_VIDEO_MEMORY,
++ gcvHAL_UNLOCK_VIDEO_MEMORY,
++
++ /* Event queue. */
++ gcvHAL_EVENT_COMMIT,
++
++ gcvHAL_USER_SIGNAL,
++ gcvHAL_SIGNAL,
++ gcvHAL_WRITE_DATA,
++
++ gcvHAL_COMMIT,
++ gcvHAL_STALL,
++
++ gcvHAL_READ_REGISTER,
++ gcvHAL_WRITE_REGISTER,
++
++ gcvHAL_GET_PROFILE_SETTING,
++ gcvHAL_SET_PROFILE_SETTING,
++
++ gcvHAL_READ_ALL_PROFILE_REGISTERS,
++ gcvHAL_PROFILE_REGISTERS_2D,
++#if VIVANTE_PROFILER_PERDRAW
++ gcvHAL_READ_PROFILER_REGISTER_SETTING,
++#endif
++
++ /* Power management. */
++ gcvHAL_SET_POWER_MANAGEMENT_STATE,
++ gcvHAL_QUERY_POWER_MANAGEMENT_STATE,
++
++ gcvHAL_GET_BASE_ADDRESS,
++
++ gcvHAL_SET_IDLE, /* reserved */
++
++ /* Queries. */
++ gcvHAL_QUERY_KERNEL_SETTINGS,
++
++ /* Reset. */
++ gcvHAL_RESET,
++
++ /* Map physical address into handle. */
++ gcvHAL_MAP_PHYSICAL,
++
++ /* Debugger stuff. */
++ gcvHAL_DEBUG,
++
++ /* Cache stuff. */
++ gcvHAL_CACHE,
++
++ /* TimeStamp */
++ gcvHAL_TIMESTAMP,
++
++ /* Database. */
++ gcvHAL_DATABASE,
++
++ /* Version. */
++ gcvHAL_VERSION,
++
++ /* Chip info */
++ gcvHAL_CHIP_INFO,
++
++ /* Process attaching/detaching. */
++ gcvHAL_ATTACH,
++ gcvHAL_DETACH,
++
++ /* Composition. */
++ gcvHAL_COMPOSE,
++
++ /* Set timeOut value */
++ gcvHAL_SET_TIMEOUT,
++
++ /* Frame database. */
++ gcvHAL_GET_FRAME_INFO,
++
++ gcvHAL_QUERY_COMMAND_BUFFER,
++
++ gcvHAL_COMMIT_DONE,
++
++ /* GPU and event dump */
++ gcvHAL_DUMP_GPU_STATE,
++ gcvHAL_DUMP_EVENT,
++
++ /* Virtual command buffer. */
++ gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER,
++ gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER,
++
++ /* FSCALE_VAL. */
++ gcvHAL_SET_FSCALE_VALUE,
++ gcvHAL_GET_FSCALE_VALUE,
++
++ gcvHAL_NAME_VIDEO_MEMORY,
++ gcvHAL_IMPORT_VIDEO_MEMORY,
++
++ /* Reset time stamp. */
++ gcvHAL_QUERY_RESET_TIME_STAMP,
++
++ /* Multi-GPU read/write. */
++ gcvHAL_READ_REGISTER_EX,
++ gcvHAL_WRITE_REGISTER_EX,
++
++ /* Sync point operations. */
++ gcvHAL_SYNC_POINT,
++
++ /* Create native fence and return its fd. */
++ gcvHAL_CREATE_NATIVE_FENCE,
++
++ /* Destory MMU. */
++ gcvHAL_DESTROY_MMU,
++
++ /* Shared buffer. */
++ gcvHAL_SHBUF,
++
++ /* Config power management. */
++ gcvHAL_CONFIG_POWER_MANAGEMENT,
++
++ /* Connect a video node to an OS native fd. */
++ gcvHAL_GET_VIDEO_MEMORY_FD,
++}
++gceHAL_COMMAND_CODES;
++
++/******************************************************************************\
++****************************** Interface Structure *****************************
++\******************************************************************************/
++
++#define gcdMAX_PROFILE_FILE_NAME 128
++
++/* Kernel settings. */
++typedef struct _gcsKERNEL_SETTINGS
++{
++ /* Used RealTime signal between kernel and user. */
++ gctINT signal;
++}
++gcsKERNEL_SETTINGS;
++
++
++/* gcvHAL_QUERY_CHIP_IDENTITY */
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY * gcsHAL_QUERY_CHIP_IDENTITY_PTR;
++typedef struct _gcsHAL_QUERY_CHIP_IDENTITY
++{
++
++ /* Chip model. */
++ gceCHIPMODEL chipModel;
++
++ /* Revision value.*/
++ gctUINT32 chipRevision;
++
++ /* Supported feature fields. */
++ gctUINT32 chipFeatures;
++
++ /* Supported minor feature fields. */
++ gctUINT32 chipMinorFeatures;
++
++ /* Supported minor feature 1 fields. */
++ gctUINT32 chipMinorFeatures1;
++
++ /* Supported minor feature 2 fields. */
++ gctUINT32 chipMinorFeatures2;
++
++ /* Supported minor feature 3 fields. */
++ gctUINT32 chipMinorFeatures3;
++
++ /* Supported minor feature 4 fields. */
++ gctUINT32 chipMinorFeatures4;
++
++ /* Supported minor feature 5 fields. */
++ gctUINT32 chipMinorFeatures5;
++
++ /* Number of streams supported. */
++ gctUINT32 streamCount;
++
++ /* Total number of temporary registers per thread. */
++ gctUINT32 registerMax;
++
++ /* Maximum number of threads. */
++ gctUINT32 threadCount;
++
++ /* Number of shader cores. */
++ gctUINT32 shaderCoreCount;
++
++ /* Size of the vertex cache. */
++ gctUINT32 vertexCacheSize;
++
++ /* Number of entries in the vertex output buffer. */
++ gctUINT32 vertexOutputBufferSize;
++
++ /* Number of pixel pipes. */
++ gctUINT32 pixelPipes;
++
++ /* Number of instructions. */
++ gctUINT32 instructionCount;
++
++ /* Number of constants. */
++ gctUINT32 numConstants;
++
++ /* Buffer size */
++ gctUINT32 bufferSize;
++
++ /* Number of varyings */
++ gctUINT32 varyingsCount;
++
++ /* Supertile layout style in hardware */
++ gctUINT32 superTileMode;
++
++#if gcdMULTI_GPU
++ /* Number of 3D GPUs */
++ gctUINT32 gpuCoreCount;
++#endif
++
++ /* Special control bits for 2D chip. */
++ gctUINT32 chip2DControl;
++
++ /* Product ID */
++ gctUINT32 productID;
++}
++gcsHAL_QUERY_CHIP_IDENTITY;
++
++/* gcvHAL_COMPOSE. */
++typedef struct _gcsHAL_COMPOSE * gcsHAL_COMPOSE_PTR;
++typedef struct _gcsHAL_COMPOSE
++{
++ /* Composition state buffer. */
++ gctUINT64 physical;
++ gctUINT64 logical;
++ gctUINT offset;
++ gctUINT size;
++
++ /* Composition end signal. */
++ gctUINT64 process;
++ gctUINT64 signal;
++
++ /* User signals. */
++ gctUINT64 userProcess;
++ gctUINT64 userSignal1;
++ gctUINT64 userSignal2;
++
++#if defined(__QNXNTO__)
++ /* Client pulse side-channel connection ID. */
++ gctINT32 coid;
++
++ /* Set by server. */
++ gctINT32 rcvid;
++#endif
++}
++gcsHAL_COMPOSE;
++
++
++typedef struct _gcsHAL_INTERFACE
++{
++ /* Command code. */
++ gceHAL_COMMAND_CODES command;
++
++ /* Hardware type. */
++ gceHARDWARE_TYPE hardwareType;
++
++ /* Status value. */
++ gceSTATUS status;
++
++ /* Handle to this interface channel. */
++ gctUINT64 handle;
++
++ /* Pid of the client. */
++ gctUINT32 pid;
++
++ /* Union of command structures. */
++ union _u
++ {
++ /* gcvHAL_GET_BASE_ADDRESS */
++ struct _gcsHAL_GET_BASE_ADDRESS
++ {
++ /* Physical memory address of internal memory. */
++ OUT gctUINT32 baseAddress;
++ }
++ GetBaseAddress;
++
++ /* gcvHAL_QUERY_VIDEO_MEMORY */
++ struct _gcsHAL_QUERY_VIDEO_MEMORY
++ {
++ /* Physical memory address of internal memory. Just a name. */
++ OUT gctUINT32 internalPhysical;
++
++ /* Size in bytes of internal memory. */
++ OUT gctUINT64 internalSize;
++
++ /* Physical memory address of external memory. Just a name. */
++ OUT gctUINT32 externalPhysical;
++
++ /* Size in bytes of external memory.*/
++ OUT gctUINT64 externalSize;
++
++ /* Physical memory address of contiguous memory. Just a name. */
++ OUT gctUINT32 contiguousPhysical;
++
++ /* Size in bytes of contiguous memory.*/
++ OUT gctUINT64 contiguousSize;
++ }
++ QueryVideoMemory;
++
++ /* gcvHAL_QUERY_CHIP_IDENTITY */
++ gcsHAL_QUERY_CHIP_IDENTITY QueryChipIdentity;
++
++ /* gcvHAL_MAP_MEMORY */
++ struct _gcsHAL_MAP_MEMORY
++ {
++ /* Physical memory address to map. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to map. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory. */
++ OUT gctUINT64 logical;
++ }
++ MapMemory;
++
++ /* gcvHAL_UNMAP_MEMORY */
++ struct _gcsHAL_UNMAP_MEMORY
++ {
++ /* Physical memory address to unmap. Just a name on Linux/Qnx. */
++ IN gctUINT32 physical;
++
++ /* Number of bytes in physical memory to unmap. */
++ IN gctUINT64 bytes;
++
++ /* Address of mapped memory to unmap. */
++ IN gctUINT64 logical;
++ }
++ UnmapMemory;
++
++ /* gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_LINEAR_VIDEO_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT bytes;
++
++ /* Buffer alignment. */
++ IN gctUINT alignment;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Flag of allocation. */
++ IN gctUINT32 flag;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory. */
++ OUT gctUINT32 node;
++ }
++ AllocateLinearVideoMemory;
++
++ /* gcvHAL_ALLOCATE_VIDEO_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIDEO_MEMORY
++ {
++ /* Width of rectangle to allocate. */
++ IN OUT gctUINT width;
++
++ /* Height of rectangle to allocate. */
++ IN OUT gctUINT height;
++
++ /* Depth of rectangle to allocate. */
++ IN gctUINT depth;
++
++ /* Format rectangle to allocate in gceSURF_FORMAT. */
++ IN gceSURF_FORMAT format;
++
++ /* Type of allocation. */
++ IN gceSURF_TYPE type;
++
++ /* Memory pool to allocate from. */
++ IN OUT gcePOOL pool;
++
++ /* Allocated video memory. */
++ OUT gctUINT32 node;
++ }
++ AllocateVideoMemory;
++
++ /* gcvHAL_RELEASE_VIDEO_MEMORY */
++ struct _gcsHAL_RELEASE_VIDEO_MEMORY
++ {
++ /* Allocated video memory. */
++ IN gctUINT32 node;
++
++#ifdef __QNXNTO__
++/* TODO: This is part of the unlock - why is it here? */
++ /* Mapped logical address to unmap in user space. */
++ OUT gctUINT64 memory;
++
++ /* Number of bytes to allocated. */
++ OUT gctUINT64 bytes;
++#endif
++ }
++ ReleaseVideoMemory;
++
++ /* gcvHAL_LOCK_VIDEO_MEMORY */
++ struct _gcsHAL_LOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory. */
++ IN gctUINT32 node;
++
++ /* Cache configuration. */
++ /* Only gcvPOOL_CONTIGUOUS and gcvPOOL_VIRUTAL
++ ** can be configured */
++ IN gctBOOL cacheable;
++
++ /* Hardware specific address. */
++ OUT gctUINT32 address;
++
++ /* Mapped logical address. */
++ OUT gctUINT64 memory;
++
++ /* Customer priviate handle*/
++ OUT gctUINT32 gid;
++
++ /* Bus address of a contiguous video node. */
++ OUT gctUINT64 physicalAddress;
++ }
++ LockVideoMemory;
++
++ /* gcvHAL_UNLOCK_VIDEO_MEMORY */
++ struct _gcsHAL_UNLOCK_VIDEO_MEMORY
++ {
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++
++ /* Type of surface. */
++ IN gceSURF_TYPE type;
++
++ /* Flag to unlock surface asynchroneously. */
++ IN OUT gctBOOL asynchroneous;
++ }
++ UnlockVideoMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateNonPagedMemory;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_NON_PAGED_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeNonPagedMemory;
++
++ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */
++ struct _gcsHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateVirtualCommandBuffer;
++
++ /* gcvHAL_FREE_NON_PAGED_MEMORY */
++ struct _gcsHAL_FREE_VIRTUAL_COMMAND_BUFFER
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeVirtualCommandBuffer;
++
++ /* gcvHAL_EVENT_COMMIT. */
++ struct _gcsHAL_EVENT_COMMIT
++ {
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++
++#if gcdMULTI_GPU
++ IN gceCORE_3D_MASK chipEnable;
++
++ IN gceMULTI_GPU_MODE gpuMode;
++#endif
++ }
++ Event;
++
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_COMMIT
++ {
++ /* Context buffer object gckCONTEXT. */
++ IN gctUINT64 context;
++
++ /* Command buffer gcoCMDBUF. */
++ IN gctUINT64 commandBuffer;
++
++ /* State delta buffer in gcsSTATE_DELTA. */
++ gctUINT64 delta;
++
++ /* Event queue in gcsQUEUE. */
++ IN gctUINT64 queue;
++
++#if gcdMULTI_GPU
++ IN gceCORE_3D_MASK chipEnable;
++
++ IN gceMULTI_GPU_MODE gpuMode;
++#endif
++ }
++ Commit;
++
++ /* gcvHAL_MAP_USER_MEMORY */
++ struct _gcsHAL_MAP_USER_MEMORY
++ {
++ /* Base address of user memory to map. */
++ IN gctUINT64 memory;
++
++ /* Physical address of user memory to map. */
++ IN gctUINT32 physical;
++
++ /* Size of user memory in bytes to map. */
++ IN gctUINT64 size;
++
++ /* Info record required by gcvHAL_UNMAP_USER_MEMORY. Just a name. */
++ OUT gctUINT32 info;
++
++ /* Physical address of mapped memory. */
++ OUT gctUINT32 address;
++ }
++ MapUserMemory;
++
++ /* gcvHAL_UNMAP_USER_MEMORY */
++ struct _gcsHAL_UNMAP_USER_MEMORY
++ {
++ /* Base address of user memory to unmap. */
++ IN gctUINT64 memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctUINT64 size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. Just a name. */
++ IN gctUINT32 info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++ }
++ UnmapUserMemory;
++#if !USE_NEW_LINUX_SIGNAL
++ /* gcsHAL_USER_SIGNAL */
++ struct _gcsHAL_USER_SIGNAL
++ {
++ /* Command. */
++ gceUSER_SIGNAL_COMMAND_CODES command;
++
++ /* Signal ID. */
++ IN OUT gctINT id;
++
++ /* Reset mode. */
++ IN gctBOOL manualReset;
++
++ /* Wait timedout. */
++ IN gctUINT32 wait;
++
++ /* State. */
++ IN gctBOOL state;
++ }
++ UserSignal;
++#endif
++
++ /* gcvHAL_SIGNAL. */
++ struct _gcsHAL_SIGNAL
++ {
++ /* Signal handle to signal gctSIGNAL. */
++ IN gctUINT64 signal;
++
++ /* Reserved gctSIGNAL. */
++ IN gctUINT64 auxSignal;
++
++ /* Process owning the signal gctHANDLE. */
++ IN gctUINT64 process;
++
++#if defined(__QNXNTO__)
++ /* Client pulse side-channel connection ID. Set by client in gcoOS_CreateSignal. */
++ IN gctINT32 coid;
++
++ /* Set by server. */
++ IN gctINT32 rcvid;
++#endif
++ /* Event generated from where of pipeline */
++ IN gceKERNEL_WHERE fromWhere;
++ }
++ Signal;
++
++ /* gcvHAL_WRITE_DATA. */
++ struct _gcsHAL_WRITE_DATA
++ {
++ /* Address to write data to. */
++ IN gctUINT32 address;
++
++ /* Data to write. */
++ IN gctUINT32 data;
++ }
++ WriteData;
++
++ /* gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_ALLOCATE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes to allocate. */
++ IN OUT gctUINT64 bytes;
++
++ /* Hardware address of allocation. */
++ OUT gctUINT32 address;
++
++ /* Physical address of allocation. Just a name. */
++ OUT gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ OUT gctUINT64 logical;
++ }
++ AllocateContiguousMemory;
++
++ /* gcvHAL_FREE_CONTIGUOUS_MEMORY */
++ struct _gcsHAL_FREE_CONTIGUOUS_MEMORY
++ {
++ /* Number of bytes allocated. */
++ IN gctUINT64 bytes;
++
++ /* Physical address of allocation. Just a name. */
++ IN gctUINT32 physical;
++
++ /* Logical address of allocation. */
++ IN gctUINT64 logical;
++ }
++ FreeContiguousMemory;
++
++ /* gcvHAL_READ_REGISTER */
++ struct _gcsHAL_READ_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ OUT gctUINT32 data;
++ }
++ ReadRegisterData;
++
++ /* gcvHAL_WRITE_REGISTER */
++ struct _gcsHAL_WRITE_REGISTER
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ /* Data read. */
++ IN gctUINT32 data;
++ }
++ WriteRegisterData;
++
++#if gcdMULTI_GPU
++ /* gcvHAL_READ_REGISTER_EX */
++ struct _gcsHAL_READ_REGISTER_EX
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ IN gctUINT32 coreSelect;
++
++ /* Data read. */
++ OUT gctUINT32 data[gcdMULTI_GPU];
++ }
++ ReadRegisterDataEx;
++
++ /* gcvHAL_WRITE_REGISTER_EX */
++ struct _gcsHAL_WRITE_REGISTER_EX
++ {
++ /* Logical address of memory to write data to. */
++ IN gctUINT32 address;
++
++ IN gctUINT32 coreSelect;
++
++ /* Data read. */
++ IN gctUINT32 data[gcdMULTI_GPU];
++ }
++ WriteRegisterDataEx;
++#endif
++
++#if VIVANTE_PROFILER
++ /* gcvHAL_GET_PROFILE_SETTING */
++ struct _gcsHAL_GET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ OUT gctBOOL enable;
++ }
++ GetProfileSetting;
++
++ /* gcvHAL_SET_PROFILE_SETTING */
++ struct _gcsHAL_SET_PROFILE_SETTING
++ {
++ /* Enable profiling */
++ IN gctBOOL enable;
++ }
++ SetProfileSetting;
++
++#if VIVANTE_PROFILER_PERDRAW
++ /* gcvHAL_READ_PROFILER_REGISTER_SETTING */
++ struct _gcsHAL_READ_PROFILER_REGISTER_SETTING
++ {
++ /*Should Clear Register*/
++ IN gctBOOL bclear;
++ }
++ SetProfilerRegisterClear;
++#endif
++
++ /* gcvHAL_READ_ALL_PROFILE_REGISTERS */
++ struct _gcsHAL_READ_ALL_PROFILE_REGISTERS
++ {
++#if VIVANTE_PROFILER_CONTEXT
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++#endif
++
++ /* Data read. */
++ OUT gcsPROFILER_COUNTERS counters;
++ }
++ RegisterProfileData;
++
++ /* gcvHAL_PROFILE_REGISTERS_2D */
++ struct _gcsHAL_PROFILE_REGISTERS_2D
++ {
++ /* Data read in gcs2D_PROFILE. */
++ OUT gctUINT64 hwProfile2D;
++ }
++ RegisterProfileData2D;
++#endif
++
++ /* Power management. */
++ /* gcvHAL_SET_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_SET_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ IN gceCHIPPOWERSTATE state;
++ }
++ SetPowerManagement;
++
++ /* gcvHAL_QUERY_POWER_MANAGEMENT_STATE */
++ struct _gcsHAL_QUERY_POWER_MANAGEMENT
++ {
++ /* Data read. */
++ OUT gceCHIPPOWERSTATE state;
++
++ /* Idle query. */
++ OUT gctBOOL isIdle;
++ }
++ QueryPowerManagement;
++
++ /* gcvHAL_QUERY_KERNEL_SETTINGS */
++ struct _gcsHAL_QUERY_KERNEL_SETTINGS
++ {
++ /* Settings.*/
++ OUT gcsKERNEL_SETTINGS settings;
++ }
++ QueryKernelSettings;
++
++ /* gcvHAL_MAP_PHYSICAL */
++ struct _gcsHAL_MAP_PHYSICAL
++ {
++ /* gcvTRUE to map, gcvFALSE to unmap. */
++ IN gctBOOL map;
++
++ /* Physical address. */
++ IN OUT gctUINT64 physical;
++ }
++ MapPhysical;
++
++ /* gcvHAL_DEBUG */
++ struct _gcsHAL_DEBUG
++ {
++ /* If gcvTRUE, set the debug information. */
++ IN gctBOOL set;
++ IN gctUINT32 level;
++ IN gctUINT32 zones;
++ IN gctBOOL enable;
++
++ IN gceDEBUG_MESSAGE_TYPE type;
++ IN gctUINT32 messageSize;
++
++ /* Message to print if not empty. */
++ IN gctCHAR message[80];
++ }
++ Debug;
++
++ /* gcvHAL_CACHE */
++ struct _gcsHAL_CACHE
++ {
++ IN gceCACHEOPERATION operation;
++ IN gctUINT64 process;
++ IN gctUINT64 logical;
++ IN gctUINT64 bytes;
++ IN gctUINT32 node;
++ }
++ Cache;
++
++ /* gcvHAL_TIMESTAMP */
++ struct _gcsHAL_TIMESTAMP
++ {
++ /* Timer select. */
++ IN gctUINT32 timer;
++
++ /* Timer request type (0-stop, 1-start, 2-send delta). */
++ IN gctUINT32 request;
++
++ /* Result of delta time in microseconds. */
++ OUT gctINT32 timeDelta;
++ }
++ TimeStamp;
++
++ /* gcvHAL_DATABASE */
++ struct _gcsHAL_DATABASE
++ {
++ /* Set to gcvTRUE if you want to query a particular process ID.
++ ** Set to gcvFALSE to query the last detached process. */
++ IN gctBOOL validProcessID;
++
++ /* Process ID to query. */
++ IN gctUINT32 processID;
++
++ /* Information. */
++ OUT gcuDATABASE_INFO vidMem;
++ OUT gcuDATABASE_INFO nonPaged;
++ OUT gcuDATABASE_INFO contiguous;
++ OUT gcuDATABASE_INFO gpuIdle;
++
++ /* Detail information about video memory. */
++ OUT gcuDATABASE_INFO vidMemPool[3];
++ }
++ Database;
++
++ /* gcvHAL_VERSION */
++ struct _gcsHAL_VERSION
++ {
++ /* Major version: N.n.n. */
++ OUT gctINT32 major;
++
++ /* Minor version: n.N.n. */
++ OUT gctINT32 minor;
++
++ /* Patch version: n.n.N. */
++ OUT gctINT32 patch;
++
++ /* Build version. */
++ OUT gctUINT32 build;
++ }
++ Version;
++
++ /* gcvHAL_CHIP_INFO */
++ struct _gcsHAL_CHIP_INFO
++ {
++ /* Chip count. */
++ OUT gctINT32 count;
++
++ /* Chip types. */
++ OUT gceHARDWARE_TYPE types[gcdCHIP_COUNT];
++ }
++ ChipInfo;
++
++ /* gcvHAL_ATTACH */
++ struct _gcsHAL_ATTACH
++ {
++ /* Handle of context buffer object. */
++ OUT gctUINT32 context;
++
++ /* Number of states in the buffer. */
++ OUT gctUINT64 stateCount;
++
++ /* Map context buffer to user or not. */
++ IN gctBOOL map;
++
++ /* Physical of context buffer. */
++ OUT gctUINT32 physicals[2];
++
++ /* Physical of context buffer. */
++ OUT gctUINT64 logicals[2];
++
++ /* Bytes of context buffer. */
++ OUT gctUINT32 bytes;
++ }
++ Attach;
++
++ /* gcvHAL_DETACH */
++ struct _gcsHAL_DETACH
++ {
++ /* Context buffer object gckCONTEXT. Just a name. */
++ IN gctUINT32 context;
++ }
++ Detach;
++
++ /* gcvHAL_COMPOSE. */
++ gcsHAL_COMPOSE Compose;
++
++ /* gcvHAL_GET_FRAME_INFO. */
++ struct _gcsHAL_GET_FRAME_INFO
++ {
++ /* gcsHAL_FRAME_INFO* */
++ OUT gctUINT64 frameInfo;
++ }
++ GetFrameInfo;
++
++ /* gcvHAL_SET_TIME_OUT. */
++ struct _gcsHAL_SET_TIMEOUT
++ {
++ gctUINT32 timeOut;
++ }
++ SetTimeOut;
++
++#if gcdENABLE_VG
++ /* gcvHAL_COMMIT */
++ struct _gcsHAL_VGCOMMIT
++ {
++ /* Context buffer. gcsVGCONTEXT_PTR */
++ IN gctUINT64 context;
++
++ /* Command queue. gcsVGCMDQUEUE_PTR */
++ IN gctUINT64 queue;
++
++ /* Number of entries in the queue. */
++ IN gctUINT entryCount;
++
++ /* Task table. gcsTASK_MASTER_TABLE_PTR */
++ IN gctUINT64 taskTable;
++ }
++ VGCommit;
++
++ /* gcvHAL_QUERY_COMMAND_BUFFER */
++ struct _gcsHAL_QUERY_COMMAND_BUFFER
++ {
++ /* Command buffer attributes. */
++ OUT gcsCOMMAND_BUFFER_INFO information;
++ }
++ QueryCommandBuffer;
++
++#endif
++
++ struct _gcsHAL_SET_FSCALE_VALUE
++ {
++ IN gctUINT value;
++ }
++ SetFscaleValue;
++
++ struct _gcsHAL_GET_FSCALE_VALUE
++ {
++ OUT gctUINT value;
++ OUT gctUINT minValue;
++ OUT gctUINT maxValue;
++ }
++ GetFscaleValue;
++
++ struct _gcsHAL_NAME_VIDEO_MEMORY
++ {
++ IN gctUINT32 handle;
++ OUT gctUINT32 name;
++ }
++ NameVideoMemory;
++
++ struct _gcsHAL_IMPORT_VIDEO_MEMORY
++ {
++ IN gctUINT32 name;
++ OUT gctUINT32 handle;
++ }
++ ImportVideoMemory;
++
++ struct _gcsHAL_QUERY_RESET_TIME_STAMP
++ {
++ OUT gctUINT64 timeStamp;
++ }
++ QueryResetTimeStamp;
++
++ struct _gcsHAL_SYNC_POINT
++ {
++ /* Command. */
++ gceSYNC_POINT_COMMAND_CODES command;
++
++ /* Sync point. */
++ IN OUT gctUINT64 syncPoint;
++
++ /* From where. */
++ IN gceKERNEL_WHERE fromWhere;
++
++ /* Signaled state. */
++ OUT gctBOOL state;
++ }
++ SyncPoint;
++
++ struct _gcsHAL_CREATE_NATIVE_FENCE
++ {
++ /* Signal id to dup. */
++ IN gctUINT64 syncPoint;
++
++ /* Native fence file descriptor. */
++ OUT gctINT fenceFD;
++
++ }
++ CreateNativeFence;
++
++ struct _gcsHAL_DESTROY_MMU
++ {
++ /* Mmu object. */
++ IN gctUINT64 mmu;
++ }
++ DestroyMmu;
++
++ struct _gcsHAL_SHBUF
++ {
++ gceSHBUF_COMMAND_CODES command;
++
++ /* Shared buffer. */
++ IN OUT gctUINT64 id;
++
++ /* User data to be shared. */
++ IN gctUINT64 data;
++
++ /* Data size. */
++ IN OUT gctUINT32 bytes;
++ }
++ ShBuf;
++
++ struct _gcsHAL_CONFIG_POWER_MANAGEMENT
++ {
++ IN gctBOOL enable;
++ }
++ ConfigPowerManagement;
++
++ struct _gcsHAL_GET_VIDEO_MEMORY_FD
++ {
++ IN gctUINT32 handle;
++ OUT gctINT fd;
++ }
++ GetVideoMemoryFd;
++ }
++ u;
++}
++gcsHAL_INTERFACE;
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h 2016-06-19 22:11:55.233144731 +0200
+@@ -0,0 +1,270 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_driver_vg_h_
++#define __gc_hal_driver_vg_h_
++
++
++
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* I/O Control Codes ******************************
++\******************************************************************************/
++
++#define gcvHAL_CLASS "galcore"
++#define IOCTL_GCHAL_INTERFACE 30000
++
++/******************************************************************************\
++********************************* Command Codes ********************************
++\******************************************************************************/
++
++/******************************************************************************\
++********************* Command buffer information structure. ********************
++\******************************************************************************/
++
++typedef struct _gcsCOMMAND_BUFFER_INFO * gcsCOMMAND_BUFFER_INFO_PTR;
++typedef struct _gcsCOMMAND_BUFFER_INFO
++{
++ /* FE command buffer interrupt ID. */
++ gctINT32 feBufferInt;
++
++ /* TS overflow interrupt ID. */
++ gctINT32 tsOverflowInt;
++
++ /* Alignment and mask for the buffer address. */
++ gctUINT addressMask;
++ gctUINT32 addressAlignment;
++
++ /* Alignment for each command. */
++ gctUINT32 commandAlignment;
++
++ /* Number of bytes required by the STATE command. */
++ gctUINT32 stateCommandSize;
++
++ /* Number of bytes required by the RESTART command. */
++ gctUINT32 restartCommandSize;
++
++ /* Number of bytes required by the FETCH command. */
++ gctUINT32 fetchCommandSize;
++
++ /* Number of bytes required by the CALL command. */
++ gctUINT32 callCommandSize;
++
++ /* Number of bytes required by the RETURN command. */
++ gctUINT32 returnCommandSize;
++
++ /* Number of bytes required by the EVENT command. */
++ gctUINT32 eventCommandSize;
++
++ /* Number of bytes required by the END command. */
++ gctUINT32 endCommandSize;
++
++ /* Number of bytes reserved at the tail of a static command buffer. */
++ gctUINT32 staticTailSize;
++
++ /* Number of bytes reserved at the tail of a dynamic command buffer. */
++ gctUINT32 dynamicTailSize;
++}
++gcsCOMMAND_BUFFER_INFO;
++
++/******************************************************************************\
++******************************** Task Structures *******************************
++\******************************************************************************/
++
++typedef enum _gceTASK
++{
++ gcvTASK_LINK,
++ gcvTASK_CLUSTER,
++ gcvTASK_INCREMENT,
++ gcvTASK_DECREMENT,
++ gcvTASK_SIGNAL,
++ gcvTASK_LOCKDOWN,
++ gcvTASK_UNLOCK_VIDEO_MEMORY,
++ gcvTASK_FREE_VIDEO_MEMORY,
++ gcvTASK_FREE_CONTIGUOUS_MEMORY,
++ gcvTASK_UNMAP_USER_MEMORY
++}
++gceTASK;
++
++typedef struct _gcsTASK_HEADER * gcsTASK_HEADER_PTR;
++typedef struct _gcsTASK_HEADER
++{
++ /* Task ID. */
++ IN gceTASK id;
++}
++gcsTASK_HEADER;
++
++typedef struct _gcsTASK_LINK * gcsTASK_LINK_PTR;
++typedef struct _gcsTASK_LINK
++{
++ /* Task ID (gcvTASK_LINK). */
++ IN gceTASK id;
++
++ /* Pointer to the next task container. */
++ IN gctPOINTER cotainer;
++
++ /* Pointer to the next task from the next task container. */
++ IN gcsTASK_HEADER_PTR task;
++}
++gcsTASK_LINK;
++
++typedef struct _gcsTASK_CLUSTER * gcsTASK_CLUSTER_PTR;
++typedef struct _gcsTASK_CLUSTER
++{
++ /* Task ID (gcvTASK_CLUSTER). */
++ IN gceTASK id;
++
++ /* Number of tasks in the cluster. */
++ IN gctUINT taskCount;
++}
++gcsTASK_CLUSTER;
++
++typedef struct _gcsTASK_INCREMENT * gcsTASK_INCREMENT_PTR;
++typedef struct _gcsTASK_INCREMENT
++{
++ /* Task ID (gcvTASK_INCREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to increment. */
++ IN gctUINT32 address;
++}
++gcsTASK_INCREMENT;
++
++typedef struct _gcsTASK_DECREMENT * gcsTASK_DECREMENT_PTR;
++typedef struct _gcsTASK_DECREMENT
++{
++ /* Task ID (gcvTASK_DECREMENT). */
++ IN gceTASK id;
++
++ /* Address of the variable to decrement. */
++ IN gctUINT32 address;
++}
++gcsTASK_DECREMENT;
++
++typedef struct _gcsTASK_SIGNAL * gcsTASK_SIGNAL_PTR;
++typedef struct _gcsTASK_SIGNAL
++{
++ /* Task ID (gcvTASK_SIGNAL). */
++ IN gceTASK id;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++
++#if defined(__QNXNTO__)
++ IN gctINT32 coid;
++ IN gctINT32 rcvid;
++#endif
++}
++gcsTASK_SIGNAL;
++
++typedef struct _gcsTASK_LOCKDOWN * gcsTASK_LOCKDOWN_PTR;
++typedef struct _gcsTASK_LOCKDOWN
++{
++ /* Task ID (gcvTASK_LOCKDOWN). */
++ IN gceTASK id;
++
++ /* Address of the user space counter. */
++ IN gctUINT32 userCounter;
++
++ /* Address of the kernel space counter. */
++ IN gctUINT32 kernelCounter;
++
++ /* Process owning the signal. */
++ IN gctHANDLE process;
++
++ /* Signal handle to signal. */
++ IN gctSIGNAL signal;
++}
++gcsTASK_LOCKDOWN;
++
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY * gcsTASK_UNLOCK_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_UNLOCK_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT64 node;
++}
++gcsTASK_UNLOCK_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY * gcsTASK_FREE_VIDEO_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_VIDEO_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_VIDEO_MEMORY). */
++ IN gceTASK id;
++
++ /* Allocated video memory. */
++ IN gctUINT32 node;
++}
++gcsTASK_FREE_VIDEO_MEMORY;
++
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY * gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR;
++typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY
++{
++ /* Task ID (gcvTASK_FREE_CONTIGUOUS_MEMORY). */
++ IN gceTASK id;
++
++ /* Number of bytes allocated. */
++ IN gctSIZE_T bytes;
++
++ /* Physical address of allocation. */
++ IN gctPHYS_ADDR physical;
++
++ /* Logical address of allocation. */
++ IN gctPOINTER logical;
++}
++gcsTASK_FREE_CONTIGUOUS_MEMORY;
++
++typedef struct _gcsTASK_UNMAP_USER_MEMORY * gcsTASK_UNMAP_USER_MEMORY_PTR;
++typedef struct _gcsTASK_UNMAP_USER_MEMORY
++{
++ /* Task ID (gcvTASK_UNMAP_USER_MEMORY). */
++ IN gceTASK id;
++
++ /* Base address of user memory to unmap. */
++ IN gctPOINTER memory;
++
++ /* Size of user memory in bytes to unmap. */
++ IN gctSIZE_T size;
++
++ /* Info record returned by gcvHAL_MAP_USER_MEMORY. */
++ IN gctPOINTER info;
++
++ /* Physical address of mapped memory as returned by
++ gcvHAL_MAP_USER_MEMORY. */
++ IN gctUINT32 address;
++}
++gcsTASK_UNMAP_USER_MEMORY;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_driver_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_dump.h 2016-06-19 22:11:55.233144731 +0200
+@@ -0,0 +1,89 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_dump_h_
++#define __gc_hal_dump_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*
++** FILE LAYOUT:
++**
++** gcsDUMP_FILE structure
++**
++** gcsDUMP_DATA frame
++** gcsDUMP_DATA or gcDUMP_DATA_SIZE records rendingring the frame
++** gctUINT8 data[length]
++*/
++
++#define gcvDUMP_FILE_SIGNATURE gcmCC('g','c','D','B')
++
++typedef struct _gcsDUMP_FILE
++{
++ gctUINT32 signature; /* File signature */
++ gctSIZE_T length; /* Length of file */
++ gctUINT32 frames; /* Number of frames in file */
++}
++gcsDUMP_FILE;
++
++typedef enum _gceDUMP_TAG
++{
++ gcvTAG_SURFACE = gcmCC('s','u','r','f'),
++ gcvTAG_FRAME = gcmCC('f','r','m',' '),
++ gcvTAG_COMMAND = gcmCC('c','m','d',' '),
++ gcvTAG_INDEX = gcmCC('i','n','d','x'),
++ gcvTAG_STREAM = gcmCC('s','t','r','m'),
++ gcvTAG_TEXTURE = gcmCC('t','e','x','t'),
++ gcvTAG_RENDER_TARGET = gcmCC('r','n','d','r'),
++ gcvTAG_DEPTH = gcmCC('z','b','u','f'),
++ gcvTAG_RESOLVE = gcmCC('r','s','l','v'),
++ gcvTAG_DELETE = gcmCC('d','e','l',' '),
++ gcvTAG_BUFOBJ = gcmCC('b','u','f','o'),
++}
++gceDUMP_TAG;
++
++typedef struct _gcsDUMP_SURFACE
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctUINT32 address; /* Address of the surface. */
++ gctINT16 width; /* Width of surface. */
++ gctINT16 height; /* Height of surface. */
++ gceSURF_FORMAT format; /* Surface pixel format. */
++ gctSIZE_T length; /* Number of bytes inside the surface. */
++}
++gcsDUMP_SURFACE;
++
++typedef struct _gcsDUMP_DATA
++{
++ gceDUMP_TAG type; /* Type of record. */
++ gctSIZE_T length; /* Number of bytes of data. */
++ gctUINT32 address; /* Address for the data. */
++}
++gcsDUMP_DATA;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_dump_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h 2016-06-19 22:11:55.233144731 +0200
+@@ -0,0 +1,672 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_eglplatform_h_
++#define __gc_hal_eglplatform_h_
++
++/* Include VDK types. */
++#include "gc_hal_types.h"
++#include "gc_hal_base.h"
++#include "gc_hal_eglplatform_type.h"
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#if defined(_WIN32) || defined(__VC32__) && !defined(__CYGWIN__) && !defined(__SCITECH_SNAP__)
++/* Win32 and Windows CE platforms. */
++#include <windows.h>
++typedef HDC HALNativeDisplayType;
++typedef HWND HALNativeWindowType;
++typedef HBITMAP HALNativePixmapType;
++
++typedef struct __BITFIELDINFO{
++ BITMAPINFO bmi;
++ RGBQUAD bmiColors[2];
++} BITFIELDINFO;
++
++#elif defined(LINUX) && defined(EGL_API_DFB) && !defined(__APPLE__)
++#include <directfb.h>
++typedef struct _DFBDisplay * HALNativeDisplayType;
++typedef struct _DFBWindow * HALNativeWindowType;
++typedef struct _DFBPixmap * HALNativePixmapType;
++
++#elif defined(LINUX) && defined(EGL_API_FB) && !defined(__APPLE__)
++
++#if defined(EGL_API_WL)
++
++#if defined(__GNUC__)
++# define inline __inline__ /* GNU keyword. */
++#endif
++
++/* Wayland platform. */
++#include <wayland-egl.h>
++
++#define WL_EGL_NUM_BACKBUFFERS 3
++
++typedef struct _gcsWL_VIV_BUFFER
++{
++ struct wl_resource *wl_buffer;
++ gcoSURF surface;
++ gctINT32 width, height;
++} gcsWL_VIV_BUFFER;
++
++typedef struct _gcsWL_EGL_DISPLAY
++{
++ struct wl_display* wl_display;
++ struct wl_viv* wl_viv;
++ struct wl_registry *registry;
++ struct wl_event_queue *wl_queue;
++ gctINT swapInterval;
++} gcsWL_EGL_DISPLAY;
++
++typedef struct _gcsWL_EGL_BUFFER_INFO
++{
++ gctINT32 width;
++ gctINT32 height;
++ gctINT32 stride;
++ gceSURF_FORMAT format;
++ gcuVIDMEM_NODE_PTR node;
++ gcePOOL pool;
++ gctUINT bytes;
++ gcoSURF surface;
++ gcoSURF attached_surface;
++ gctINT32 invalidate;
++ gctBOOL locked;
++} gcsWL_EGL_BUFFER_INFO;
++
++typedef struct _gcsWL_EGL_BUFFER
++{
++ struct wl_buffer* wl_buffer;
++ gcsWL_EGL_BUFFER_INFO info;
++} gcsWL_EGL_BUFFER;
++
++typedef struct _gcsWL_EGL_WINDOW_INFO
++{
++ gctINT32 dx;
++ gctINT32 dy;
++ gctUINT width;
++ gctUINT height;
++ gctINT32 attached_width;
++ gctINT32 attached_height;
++ gceSURF_FORMAT format;
++ gctUINT bpp;
++} gcsWL_EGL_WINDOW_INFO;
++
++struct wl_egl_window
++{
++ gcsWL_EGL_DISPLAY* display;
++ gcsWL_EGL_BUFFER backbuffers[WL_EGL_NUM_BACKBUFFERS];
++ gcsWL_EGL_WINDOW_INFO info;
++ gctUINT current;
++ struct wl_surface* surface;
++ struct wl_callback* frame_callback;
++};
++
++typedef void* HALNativeDisplayType;
++typedef void* HALNativeWindowType;
++typedef void* HALNativePixmapType;
++#else
++/* Linux platform for FBDEV. */
++typedef struct _FBDisplay * HALNativeDisplayType;
++typedef struct _FBWindow * HALNativeWindowType;
++typedef struct _FBPixmap * HALNativePixmapType;
++#endif
++#elif defined(__ANDROID__) || defined(ANDROID)
++
++struct egl_native_pixmap_t;
++
++#if ANDROID_SDK_VERSION >= 9
++ #include <android/native_window.h>
++
++ typedef struct ANativeWindow* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t* HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#else
++ struct android_native_window_t;
++ typedef struct android_native_window_t* HALNativeWindowType;
++ typedef struct egl_native_pixmap_t * HALNativePixmapType;
++ typedef void* HALNativeDisplayType;
++#endif
++
++#elif defined(LINUX) || defined(__APPLE__)
++/* X11 platform. */
++#include <X11/Xlib.h>
++#include <X11/Xutil.h>
++
++typedef Display * HALNativeDisplayType;
++typedef Window HALNativeWindowType;
++
++#ifdef CUSTOM_PIXMAP
++typedef void * HALNativePixmapType;
++#else
++typedef Pixmap HALNativePixmapType;
++#endif /* CUSTOM_PIXMAP */
++
++/* Rename some badly named X defines. */
++#ifdef Status
++# define XStatus int
++# undef Status
++#endif
++#ifdef Always
++# define XAlways 2
++# undef Always
++#endif
++#ifdef CurrentTime
++# undef CurrentTime
++# define XCurrentTime 0
++#endif
++
++#elif defined(__QNXNTO__)
++#include <screen/screen.h>
++
++/* VOID */
++typedef int HALNativeDisplayType;
++typedef screen_window_t HALNativeWindowType;
++typedef screen_pixmap_t HALNativePixmapType;
++
++#else
++
++#error "Platform not recognized"
++
++/* VOID */
++typedef void * HALNativeDisplayType;
++typedef void * HALNativeWindowType;
++typedef void * HALNativePixmapType;
++
++#endif
++
++/* define DUMMY according to the system */
++#if defined(EGL_API_WL)
++# define WL_DUMMY (31415926)
++# define EGL_DUMMY WL_DUMMY
++#elif defined(__ANDROID__) || defined(ANDROID)
++# define ANDROID_DUMMY (31415926)
++# define EGL_DUMMY ANDROID_DUMMY
++#else
++# define EGL_DUMMY (31415926)
++#endif
++
++/*******************************************************************************
++** Display. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_GetDisplay(
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayByIndex(
++ IN gctINT DisplayIndex,
++ OUT HALNativeDisplayType * Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfo(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctSIZE_T * Physical,
++ OUT gctINT * Stride,
++ OUT gctINT * BitsPerPixel
++ );
++
++
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetNextDisplayInfoExByIndex(
++ IN gctINT Index,
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ OUT gctINT * Width,
++ OUT gctINT * Height
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbuffer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtual(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetDisplayVirtualEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER Context,
++ IN gcoSURF Surface,
++ IN gctUINT Offset,
++ IN gctINT X,
++ IN gctINT Y
++ );
++
++gceSTATUS
++gcoOS_SetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT Interval
++);
++
++gceSTATUS
++gcoOS_SetSwapIntervalEx(
++ IN HALNativeDisplayType Display,
++ IN gctINT Interval,
++ IN gctPOINTER localDisplay);
++
++gceSTATUS
++gcoOS_GetSwapInterval(
++ IN HALNativeDisplayType Display,
++ IN gctINT_PTR Min,
++ IN gctINT_PTR Max
++);
++
++gceSTATUS
++gcoOS_DisplayBufferRegions(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT NumRects,
++ IN gctINT_PTR Rects
++ );
++
++gceSTATUS
++gcoOS_DestroyDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_InitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_DeinitLocalDisplayInfo(
++ IN HALNativeDisplayType Display,
++ IN OUT gctPOINTER * localDisplay
++ );
++
++gceSTATUS
++gcoOS_GetDisplayInfoEx2(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ IN gctUINT DisplayInfoSize,
++ OUT halDISPLAY_INFO * DisplayInfo
++ );
++
++gceSTATUS
++gcoOS_GetDisplayBackbufferEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctPOINTER localDisplay,
++ OUT gctPOINTER * context,
++ OUT gcoSURF * surface,
++ OUT gctUINT * Offset,
++ OUT gctINT * X,
++ OUT gctINT * Y
++ );
++
++gceSTATUS
++gcoOS_IsValidDisplay(
++ IN HALNativeDisplayType Display
++ );
++
++gceSTATUS
++gcoOS_GetNativeVisualId(
++ IN HALNativeDisplayType Display,
++ OUT gctINT* nativeVisualId
++ );
++
++gctBOOL
++gcoOS_SynchronousFlip(
++ IN HALNativeDisplayType Display
++ );
++
++/*******************************************************************************
++** Windows. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreateWindow(
++ IN HALNativeDisplayType Display,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height,
++ OUT HALNativeWindowType * Window
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset
++ );
++
++gceSTATUS
++gcoOS_DestroyWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_DrawImage(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_GetImage(
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ OUT gctINT * BitsPerPixel,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_GetWindowInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT gctINT * X,
++ OUT gctINT * Y,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctUINT * Offset,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_DrawImageEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits,
++ IN gceSURF_FORMAT Format
++ );
++
++/*******************************************************************************
++** Pixmaps. ********************************************************************
++*/
++
++gceSTATUS
++gcoOS_CreatePixmap(
++ IN HALNativeDisplayType Display,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ OUT HALNativePixmapType * Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfo(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DrawPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctINT Left,
++ IN gctINT Top,
++ IN gctINT Right,
++ IN gctINT Bottom,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT BitsPerPixel,
++ IN gctPOINTER Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyPixmap(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap
++ );
++
++gceSTATUS
++gcoOS_GetPixmapInfoEx(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * BitsPerPixel,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits,
++ OUT gceSURF_FORMAT * Format
++ );
++
++gceSTATUS
++gcoOS_CopyPixmapBits(
++ IN HALNativeDisplayType Display,
++ IN HALNativePixmapType Pixmap,
++ IN gctUINT DstWidth,
++ IN gctUINT DstHeight,
++ IN gctINT DstStride,
++ IN gceSURF_FORMAT DstFormat,
++ OUT gctPOINTER DstBits
++ );
++
++/*******************************************************************************
++** OS relative. ****************************************************************
++*/
++gceSTATUS
++gcoOS_LoadEGLLibrary(
++ OUT gctHANDLE * Handle
++ );
++
++gceSTATUS
++gcoOS_FreeEGLLibrary(
++ IN gctHANDLE Handle
++ );
++
++gceSTATUS
++gcoOS_ShowWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_HideWindow(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_SetWindowTitle(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ IN gctCONST_STRING Title
++ );
++
++gceSTATUS
++gcoOS_CapturePointer(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window
++ );
++
++gceSTATUS
++gcoOS_GetEvent(
++ IN HALNativeDisplayType Display,
++ IN HALNativeWindowType Window,
++ OUT halEvent * Event
++ );
++
++gceSTATUS
++gcoOS_CreateClientBuffer(
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctINT Format,
++ IN gctINT Type,
++ OUT gctPOINTER * ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_GetClientBufferInfo(
++ IN gctPOINTER ClientBuffer,
++ OUT gctINT * Width,
++ OUT gctINT * Height,
++ OUT gctINT * Stride,
++ OUT gctPOINTER * Bits
++ );
++
++gceSTATUS
++gcoOS_DestroyClientBuffer(
++ IN gctPOINTER ClientBuffer
++ );
++
++gceSTATUS
++gcoOS_DestroyContext(
++ IN gctPOINTER Display,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_CreateContext(
++ IN gctPOINTER LocalDisplay,
++ IN gctPOINTER Context
++ );
++
++gceSTATUS
++gcoOS_MakeCurrent(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType DrawDrawable,
++ IN HALNativeWindowType ReadDrawable,
++ IN gctPOINTER Context,
++ IN gcoSURF ResolveTarget
++ );
++
++gceSTATUS
++gcoOS_CreateDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++
++gceSTATUS
++gcoOS_DestroyDrawable(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable
++ );
++gceSTATUS
++gcoOS_SwapBuffers(
++ IN gctPOINTER LocalDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gcoSURF RenderTarget,
++ IN gcoSURF ResolveTarget,
++ IN gctPOINTER ResolveBits,
++ OUT gctUINT *Width,
++ OUT gctUINT *Height
++ );
++
++#ifdef EGL_API_DRI
++gceSTATUS
++gcoOS_ResizeWindow(
++ IN gctPOINTER localDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gctUINT Width,
++ IN gctUINT Height)
++ ;
++
++#ifdef USE_FREESCALE_EGL_ACCEL
++gceSTATUS
++gcoOS_SwapBuffersGeneric_Async(
++ IN gctPOINTER localDisplay,
++ IN HALNativeWindowType Drawable,
++ IN gcoSURF RenderTarget,
++ IN gcoSURF ResolveTarget,
++ IN gctPOINTER ResolveBits,
++ OUT gctUINT *Width,
++ OUT gctUINT *Height,
++ IN void * resolveRect
++ );
++
++gceSTATUS
++gcoOS_DrawSurface(
++ IN gctPOINTER localDisplay,
++ IN HALNativeWindowType Drawable
++ );
++#endif
++
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform_type.h 2016-06-19 22:11:55.237144468 +0200
+@@ -0,0 +1,286 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_eglplatform_type_h_
++#define __gc_hal_eglplatform_type_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Events. *********************************************************************
++*/
++
++typedef enum _halEventType
++{
++ /* Keyboard event. */
++ HAL_KEYBOARD,
++
++ /* Mouse move event. */
++ HAL_POINTER,
++
++ /* Mouse button event. */
++ HAL_BUTTON,
++
++ /* Application close event. */
++ HAL_CLOSE,
++
++ /* Application window has been updated. */
++ HAL_WINDOW_UPDATE
++}
++halEventType;
++
++/* Scancodes for keyboard. */
++typedef enum _halKeys
++{
++ HAL_UNKNOWN = -1,
++
++ HAL_BACKSPACE = 0x08,
++ HAL_TAB,
++ HAL_ENTER = 0x0D,
++ HAL_ESCAPE = 0x1B,
++
++ HAL_SPACE = 0x20,
++ HAL_SINGLEQUOTE = 0x27,
++ HAL_PAD_ASTERISK = 0x2A,
++ HAL_COMMA = 0x2C,
++ HAL_HYPHEN,
++ HAL_PERIOD,
++ HAL_SLASH,
++ HAL_0,
++ HAL_1,
++ HAL_2,
++ HAL_3,
++ HAL_4,
++ HAL_5,
++ HAL_6,
++ HAL_7,
++ HAL_8,
++ HAL_9,
++ HAL_SEMICOLON = 0x3B,
++ HAL_EQUAL = 0x3D,
++ HAL_A = 0x41,
++ HAL_B,
++ HAL_C,
++ HAL_D,
++ HAL_E,
++ HAL_F,
++ HAL_G,
++ HAL_H,
++ HAL_I,
++ HAL_J,
++ HAL_K,
++ HAL_L,
++ HAL_M,
++ HAL_N,
++ HAL_O,
++ HAL_P,
++ HAL_Q,
++ HAL_R,
++ HAL_S,
++ HAL_T,
++ HAL_U,
++ HAL_V,
++ HAL_W,
++ HAL_X,
++ HAL_Y,
++ HAL_Z,
++ HAL_LBRACKET,
++ HAL_BACKSLASH,
++ HAL_RBRACKET,
++ HAL_BACKQUOTE = 0x60,
++
++ HAL_F1 = 0x80,
++ HAL_F2,
++ HAL_F3,
++ HAL_F4,
++ HAL_F5,
++ HAL_F6,
++ HAL_F7,
++ HAL_F8,
++ HAL_F9,
++ HAL_F10,
++ HAL_F11,
++ HAL_F12,
++
++ HAL_LCTRL,
++ HAL_RCTRL,
++ HAL_LSHIFT,
++ HAL_RSHIFT,
++ HAL_LALT,
++ HAL_RALT,
++ HAL_CAPSLOCK,
++ HAL_NUMLOCK,
++ HAL_SCROLLLOCK,
++ HAL_PAD_0,
++ HAL_PAD_1,
++ HAL_PAD_2,
++ HAL_PAD_3,
++ HAL_PAD_4,
++ HAL_PAD_5,
++ HAL_PAD_6,
++ HAL_PAD_7,
++ HAL_PAD_8,
++ HAL_PAD_9,
++ HAL_PAD_HYPHEN,
++ HAL_PAD_PLUS,
++ HAL_PAD_SLASH,
++ HAL_PAD_PERIOD,
++ HAL_PAD_ENTER,
++ HAL_SYSRQ,
++ HAL_PRNTSCRN,
++ HAL_BREAK,
++ HAL_UP,
++ HAL_LEFT,
++ HAL_RIGHT,
++ HAL_DOWN,
++ HAL_HOME,
++ HAL_END,
++ HAL_PGUP,
++ HAL_PGDN,
++ HAL_INSERT,
++ HAL_DELETE,
++ HAL_LWINDOW,
++ HAL_RWINDOW,
++ HAL_MENU,
++ HAL_POWER,
++ HAL_SLEEP,
++ HAL_WAKE
++}
++halKeys;
++
++/* Structure that defined keyboard mapping. */
++typedef struct _halKeyMap
++{
++ /* Normal key. */
++ halKeys normal;
++
++ /* Extended key. */
++ halKeys extended;
++}
++halKeyMap;
++
++/* Event structure. */
++typedef struct _halEvent
++{
++ /* Event type. */
++ halEventType type;
++
++ /* Event data union. */
++ union _halEventData
++ {
++ /* Event data for keyboard. */
++ struct _halKeyboard
++ {
++ /* Scancode. */
++ halKeys scancode;
++
++ /* ASCII characte of the key pressed. */
++ char key;
++
++ /* Flag whether the key was pressed (1) or released (0). */
++ char pressed;
++ }
++ keyboard;
++
++ /* Event data for pointer. */
++ struct _halPointer
++ {
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ pointer;
++
++ /* Event data for mouse buttons. */
++ struct _halButton
++ {
++ /* Left button state. */
++ int left;
++
++ /* Middle button state. */
++ int middle;
++
++ /* Right button state. */
++ int right;
++
++ /* Current pointer coordinate. */
++ int x;
++ int y;
++ }
++ button;
++ }
++ data;
++}
++halEvent;
++
++/* VFK_DISPLAY_INFO structure defining information returned by
++ vdkGetDisplayInfoEx. */
++typedef struct _halDISPLAY_INFO
++{
++ /* The size of the display in pixels. */
++ int width;
++ int height;
++
++ /* The stride of the dispay. -1 is returned if the stride is not known
++ ** for the specified display.*/
++ int stride;
++
++ /* The color depth of the display in bits per pixel. */
++ int bitsPerPixel;
++
++ /* The logical pointer to the display memory buffer. NULL is returned
++ ** if the pointer is not known for the specified display. */
++ void * logical;
++
++ /* The physical address of the display memory buffer. ~0 is returned
++ ** if the address is not known for the specified display. */
++ unsigned long physical;
++
++ int wrapFB; /* true if compositor, false otherwise. */
++
++#ifndef __QNXNTO__
++ /* 355_FB_MULTI_BUFFER */
++ int multiBuffer;
++ int backBufferY;
++#endif
++
++ /* The color info of the display. */
++ unsigned int alphaLength;
++ unsigned int alphaOffset;
++ unsigned int redLength;
++ unsigned int redOffset;
++ unsigned int greenLength;
++ unsigned int greenOffset;
++ unsigned int blueLength;
++ unsigned int blueOffset;
++
++ /* Display flip support. */
++ int flip;
++}
++halDISPLAY_INFO;
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_eglplatform_type_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h 2016-06-19 22:11:55.237144468 +0200
+@@ -0,0 +1,2587 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_h_
++#define __gc_hal_engine_h_
++
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++
++#if gcdENABLE_3D
++#if gcdENABLE_VG
++#include "gc_hal_engine_vg.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoSTREAM * gcoSTREAM;
++typedef struct _gcoVERTEX * gcoVERTEX;
++typedef struct _gcoTEXTURE * gcoTEXTURE;
++typedef struct _gcoINDEX * gcoINDEX;
++typedef struct _gcsVERTEX_ATTRIBUTES * gcsVERTEX_ATTRIBUTES_PTR;
++typedef struct _gcoVERTEXARRAY * gcoVERTEXARRAY;
++typedef struct _gcoBUFOBJ * gcoBUFOBJ;
++
++#define gcdATTRIBUTE_COUNT 16
++
++typedef enum _gcePROGRAM_STAGE
++{
++ gcvPROGRAM_STAGE_VERTEX = 0x0,
++ gcvPROGRAM_STAGE_TES = 0x1,
++ gcvPROGRAM_STAGE_TCS = 0x2,
++ gcvPROGRAM_STAGE_GEOMETRY = 0x3,
++ gcvPROGRAM_STAGE_FRAGMENT = 0x4,
++ gcvPROGRAM_STAGE_COMPUTE = 0x5,
++ gcvPROGRAM_STAGE_OPENCL = 0x6,
++ gcvPROGRAM_STAGE_LAST
++}
++gcePROGRAM_STAGE;
++
++typedef enum _gcePROGRAM_STAGE_BIT
++{
++ gcvPROGRAM_STAGE_VERTEX_BIT = 1 << gcvPROGRAM_STAGE_VERTEX,
++ gcvPROGRAM_STAGE_TES_BIT = 1 << gcvPROGRAM_STAGE_TES,
++ gcvPROGRAM_STAGE_TCS_BIT = 1 << gcvPROGRAM_STAGE_TCS,
++ gcvPROGRAM_STAGE_GEOMETRY_BIT = 1 << gcvPROGRAM_STAGE_GEOMETRY,
++ gcvPROGRAM_STAGE_FRAGMENT_BIT = 1 << gcvPROGRAM_STAGE_FRAGMENT,
++ gcvPROGRAM_STAGE_COMPUTE_BIT = 1 << gcvPROGRAM_STAGE_COMPUTE,
++ gcvPROGRAM_STAGE_OPENCL_BIT = 1 << gcvPROGRAM_STAGE_OPENCL,
++}
++gcePROGRAM_STAGE_BIT;
++
++
++/******************************************************************************\
++********************************* gcoHAL Object *********************************
++\******************************************************************************/
++
++gceSTATUS
++gcoHAL_QueryShaderCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctUINT * Varyings
++ );
++
++gceSTATUS
++gcoHAL_QueryShaderCapsEx(
++ IN gcoHAL Hal,
++ OUT gctUINT * ShaderCoreCount,
++ OUT gctUINT * ThreadCount,
++ OUT gctUINT * VertexInstructionCount,
++ OUT gctUINT * FragmentInstructionCount
++ );
++
++gceSTATUS
++gcoHAL_QuerySamplerBase(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * VertexCount,
++ OUT gctINT_PTR VertexBase,
++ OUT gctUINT32 * FragmentCount,
++ OUT gctINT_PTR FragmentBase
++ );
++
++gceSTATUS
++gcoHAL_QueryUniformBase(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * VertexBase,
++ OUT gctUINT32 * FragmentBase
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoHAL_QueryTextureMaxAniso(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxAnisoValue
++ );
++
++gceSTATUS
++gcoHAL_QueryStreamCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT32 * MaxAttributes,
++ OUT gctUINT32 * MaxStreamSize,
++ OUT gctUINT32 * NumberOfStreams,
++ OUT gctUINT32 * Alignment
++ );
++
++/******************************************************************************\
++********************************* gcoSURF Object ********************************
++\******************************************************************************/
++
++/*----------------------------------------------------------------------------*/
++/*--------------------------------- gcoSURF 3D --------------------------------*/
++typedef enum _gceBLIT_FLAG
++{
++ gcvBLIT_FLAG_SKIP_DEPTH_WRITE = 0x1,
++ gcvBLIT_FLAG_SKIP_STENCIL_WRITE = 0x2,
++} gceBLIT_FLAG;
++
++typedef struct _gcsSURF_BLIT_ARGS
++{
++ gcoSURF srcSurface;
++ gctINT srcX, srcY, srcZ;
++ gctINT srcWidth, srcHeight, srcDepth;
++ gcoSURF dstSurface;
++ gctINT dstX, dstY, dstZ;
++ gctINT dstWidth, dstHeight, dstDepth;
++ gctBOOL xReverse;
++ gctBOOL yReverse;
++ gctBOOL scissorTest;
++ gcsRECT scissor;
++ gctUINT flags;
++}
++gcsSURF_BLIT_ARGS;
++
++
++
++
++/* Clear flags. */
++typedef enum _gceCLEAR
++{
++ gcvCLEAR_COLOR = 0x1,
++ gcvCLEAR_DEPTH = 0x2,
++ gcvCLEAR_STENCIL = 0x4,
++ gcvCLEAR_HZ = 0x8,
++ gcvCLEAR_HAS_VAA = 0x10,
++ gcvCLEAR_WITH_GPU_ONLY = 0x100,
++ gcvCLEAR_WITH_CPU_ONLY = 0x200,
++}
++gceCLEAR;
++
++typedef struct _gcsSURF_CLEAR_ARGS
++{
++ /*
++ ** Color to fill the color portion of the framebuffer when clear
++ ** is called.
++ */
++ struct {
++ gcuVALUE r;
++ gcuVALUE g;
++ gcuVALUE b;
++ gcuVALUE a;
++ /*
++ ** Color has multiple value type so we must specify it.
++ */
++ gceVALUE_TYPE valueType;
++ } color;
++
++ gcuVALUE depth;
++
++ gctUINT stencil;
++
++
++
++ /*
++ ** stencil bit-wise mask
++ */
++ gctUINT8 stencilMask;
++ /*
++ ** Depth Write Mask
++ */
++ gctBOOL depthMask;
++ /*
++ ** 4-bit channel Mask: ABGR:MSB->LSB
++ */
++ gctUINT8 colorMask;
++ /*
++ ** If ClearRect is NULL, it means full clear
++ */
++ gcsRECT_PTR clearRect;
++ /*
++ ** clear flags
++ */
++ gceCLEAR flags;
++
++ /*
++ ** Offset in surface to cube/array/3D
++ */
++ gctUINT32 offset;
++
++} gcsSURF_CLEAR_ARGS;
++
++
++typedef gcsSURF_CLEAR_ARGS* gcsSURF_CLEAR_ARGS_PTR;
++
++typedef struct _gscSURF_BLITDRAW_BLIT
++{
++ gcoSURF srcSurface;
++ gcoSURF dstSurface;
++ gcsRECT srcRect;
++ gcsRECT dstRect;
++ gceTEXTURE_FILTER filterMode;
++ gctBOOL xReverse;
++ gctBOOL yReverse;
++ gctBOOL scissorEnabled;
++ gcsRECT scissor;
++}gscSURF_BLITDRAW_BLIT;
++
++
++typedef enum _gceBLITDRAW_TYPE
++{
++ gcvBLITDRAW_CLEAR = 0,
++ gcvBLITDRAW_BLIT = 1,
++
++ /* last number, not a real type */
++ gcvBLITDRAW_NUM_TYPE
++ }
++gceBLITDRAW_TYPE;
++
++
++typedef struct _gscSURF_BLITDRAW_ARGS
++{
++ /* always the fist member */
++ gceHAL_ARG_VERSION version;
++
++ union _gcsSURF_BLITDRAW_ARGS_UNION
++ {
++ struct _gscSURF_BLITDRAW_ARG_v1
++ {
++ /* Whether it's clear or blit operation, can be extended. */
++ gceBLITDRAW_TYPE type;
++
++ union _gscSURF_BLITDRAW_UNION
++ {
++ gscSURF_BLITDRAW_BLIT blit;
++
++ struct _gscSURF_BLITDRAW_CLEAR
++ {
++ gcsSURF_CLEAR_ARGS clearArgs;
++ gcoSURF rtSurface;
++ gcoSURF dsSurface;
++ } clear;
++ } u;
++ } v1;
++ } uArgs;
++}
++gcsSURF_BLITDRAW_ARGS;
++
++
++typedef struct _gcsSURF_RESOLVE_ARGS
++{
++ gceHAL_ARG_VERSION version;
++ union _gcsSURF_RESOLVE_ARGS_UNION
++ {
++ struct _gcsSURF_RESOLVE_ARG_v1
++ {
++ gctBOOL yInverted;
++ }v1;
++ } uArgs;
++}
++gcsSURF_RESOLVE_ARGS;
++
++
++/* CPU Blit with format (including linear <-> tile) conversion*/
++gceSTATUS
++gcoSURF_BlitCPU(
++ gcsSURF_BLIT_ARGS* args
++ );
++
++
++gceSTATUS
++gcoSURF_BlitDraw(
++ IN gcsSURF_BLITDRAW_ARGS *args
++ );
++#endif /* gcdENABLE_3D */
++
++
++
++#if gcdENABLE_3D
++/* Clear surface function. */
++gceSTATUS
++gcoSURF_Clear(
++ IN gcoSURF Surface,
++ IN gcsSURF_CLEAR_ARGS_PTR clearArg
++ );
++
++/* Preserve pixels from source. */
++gceSTATUS
++gcoSURF_Preserve(
++ IN gcoSURF Source,
++ IN gcoSURF Dest,
++ IN gcsRECT_PTR MaskRect
++ );
++
++
++/* TO BE REMOVED */
++ gceSTATUS
++ depr_gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight
++ );
++
++ gceSTATUS
++ depr_gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 DestAddress,
++ IN gctPOINTER DestBits,
++ IN gctINT DestStride,
++ IN gceSURF_TYPE DestType,
++ IN gceSURF_FORMAT DestFormat,
++ IN gctUINT DestWidth,
++ IN gctUINT DestHeight,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resample surface. */
++gceSTATUS
++gcoSURF_Resample(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++/* Resolve surface. */
++gceSTATUS
++gcoSURF_Resolve(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface
++ );
++
++gceSTATUS
++gcoSURF_ResolveEx(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsSURF_RESOLVE_ARGS *args
++ );
++
++
++/* Resolve rectangular area of a surface. */
++gceSTATUS
++gcoSURF_ResolveRect(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Resolve rectangular area of a surface. */
++gceSTATUS
++gcoSURF_ResolveRectEx(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize,
++ IN gcsSURF_RESOLVE_ARGS *args
++ );
++
++
++gceSTATUS
++gcoSURF_GetResolveAlignment(
++ IN gcoSURF Surface,
++ OUT gctUINT *originX,
++ OUT gctUINT *originY,
++ OUT gctUINT *sizeX,
++ OUT gctUINT *sizeY
++ );
++
++gceSTATUS
++gcoSURF_IsHWResolveable(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++/* Set surface resolvability. */
++gceSTATUS
++gcoSURF_SetResolvability(
++ IN gcoSURF Surface,
++ IN gctBOOL Resolvable
++ );
++
++gceSTATUS
++gcoSURF_IsRenderable(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSURF_IsFormatRenderableAsRT(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSURF_GetFence(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoBUFOBJ_GetFence(
++ IN gcoBUFOBJ bufObj
++ );
++
++gceSTATUS
++gcoBUFOBJ_WaitFence(
++ IN gcoBUFOBJ bufObj
++ );
++
++gceSTATUS
++gcoBUFOBJ_IsFenceEnabled(
++ IN gcoBUFOBJ bufObj
++ );
++
++gceSTATUS
++gcoSURF_WaitFence(
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoSTREAM_GetFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoSTREAM_WaitFence(
++ IN gcoSTREAM stream
++ );
++
++gceSTATUS
++gcoINDEX_GetFence(
++ IN gcoINDEX index
++ );
++
++gceSTATUS
++gcoINDEX_WaitFence(
++ IN gcoINDEX index
++ );
++
++gceSTATUS
++gcoSURF_3DBlitClearRect(
++ IN gcoSURF Surface,
++ IN gcsSURF_CLEAR_ARGS_PTR ClearArgs
++ );
++
++
++gceSTATUS
++gcoSURF_3DBlitBltRect(
++ IN gcoSURF SrcSurf,
++ IN gcoSURF DestSurf,
++ IN gcsPOINT_PTR SrcOrigin,
++ IN gcsPOINT_PTR DestOrigin,
++ IN gcsPOINT_PTR RectSize
++ );
++
++gceSTATUS
++gcoSURF_3DBlitCopy(
++ IN gctUINT32 SrcAddress,
++ IN gctUINT32 DestAddress,
++ IN gctUINT32 Bytes
++ );
++
++
++/******************************************************************************\
++******************************** gcoINDEX Object *******************************
++\******************************************************************************/
++
++/* Construct a new gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoINDEX * Index
++ );
++
++/* Destroy a gcoINDEX object. */
++gceSTATUS
++gcoINDEX_Destroy(
++ IN gcoINDEX Index
++ );
++
++/* Lock index in memory. */
++gceSTATUS
++gcoINDEX_Lock(
++ IN gcoINDEX Index,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Unlock index that was previously locked with gcoINDEX_Lock. */
++gceSTATUS
++gcoINDEX_Unlock(
++ IN gcoINDEX Index
++ );
++
++/* Upload index data into the memory. */
++gceSTATUS
++gcoINDEX_Load(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE IndexType,
++ IN gctUINT32 IndexCount,
++ IN gctPOINTER IndexBuffer
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_Bind(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoINDEX_BindOffset(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset
++ );
++
++/* Free existing index buffer. */
++gceSTATUS
++gcoINDEX_Free(
++ IN gcoINDEX Index
++ );
++
++/* Upload data into an index buffer. */
++gceSTATUS
++gcoINDEX_Upload(
++ IN gcoINDEX Index,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload data into an index buffer starting at an offset. */
++gceSTATUS
++gcoINDEX_UploadOffset(
++ IN gcoINDEX Index,
++ IN gctSIZE_T Offset,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Bytes
++ );
++
++/*Merge index2 to index1 from 0, index2 must subset of inex1*/
++gceSTATUS
++gcoINDEX_Merge(
++ IN gcoINDEX Index1,
++ IN gcoINDEX Index2
++ );
++
++/*check if index buffer is enough for this draw*/
++gctBOOL
++gcoINDEX_CheckRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctINT Count,
++ IN gctUINT32 Indices
++ );
++
++/* Query the index capabilities. */
++gceSTATUS
++gcoINDEX_QueryCaps(
++ OUT gctBOOL * Index8,
++ OUT gctBOOL * Index16,
++ OUT gctBOOL * Index32,
++ OUT gctUINT * MaxIndex
++ );
++
++/* Determine the index range in the current index buffer. */
++gceSTATUS
++gcoINDEX_GetIndexRange(
++ IN gcoINDEX Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Count,
++ OUT gctUINT32 * MinimumIndex,
++ OUT gctUINT32 * MaximumIndex
++ );
++
++/* Dynamic buffer management. */
++gceSTATUS
++gcoINDEX_SetDynamic(
++ IN gcoINDEX Index,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++/******************************************************************************\
++********************************** gco3D Object *********************************
++\******************************************************************************/
++
++/* Blending targets. */
++typedef enum _gceBLEND_UNIT
++{
++ gcvBLEND_SOURCE,
++ gcvBLEND_TARGET,
++}
++gceBLEND_UNIT;
++
++/* Construct a new gco3D object. */
++gceSTATUS
++gco3D_Construct(
++ IN gcoHAL Hal,
++ OUT gco3D * Engine
++ );
++
++/* Destroy an gco3D object. */
++gceSTATUS
++gco3D_Destroy(
++ IN gco3D Engine
++ );
++
++/* Set 3D API type. */
++gceSTATUS
++gco3D_SetAPI(
++ IN gco3D Engine,
++ IN gceAPI ApiType
++ );
++
++/* Get 3D API type. */
++gceSTATUS
++gco3D_GetAPI(
++ IN gco3D Engine,
++ OUT gceAPI * ApiType
++ );
++
++/* Set render target. */
++gceSTATUS
++gco3D_SetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Unset render target. */
++gceSTATUS
++gco3D_UnsetTarget(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gco3D_SetTargetEx(
++ IN gco3D Engine,
++ IN gctUINT32 TargetIndex,
++ IN gcoSURF Surface,
++ IN gctUINT32 LayerIndex
++ );
++
++gceSTATUS
++gco3D_UnsetTargetEx(
++ IN gco3D Engine,
++ IN gctUINT32 TargetIndex,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gco3D_SetTargetOffsetEx(
++ IN gco3D Engine,
++ IN gctUINT32 TargetIndex,
++ IN gctSIZE_T Offset
++ );
++
++
++gceSTATUS
++gco3D_SetPSOutputMapping(
++ IN gco3D Engine,
++ IN gctINT32 * psOutputMapping
++ );
++
++
++/* Set depth buffer. */
++gceSTATUS
++gco3D_SetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gco3D_SetDepthBufferOffset(
++ IN gco3D Engine,
++ IN gctSIZE_T Offset
++ );
++
++/* Unset depth buffer. */
++gceSTATUS
++gco3D_UnsetDepth(
++ IN gco3D Engine,
++ IN gcoSURF Surface
++ );
++
++/* Set viewport. */
++gceSTATUS
++gco3D_SetViewport(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set scissors. */
++gceSTATUS
++gco3D_SetScissors(
++ IN gco3D Engine,
++ IN gctINT32 Left,
++ IN gctINT32 Top,
++ IN gctINT32 Right,
++ IN gctINT32 Bottom
++ );
++
++/* Set clear color. */
++gceSTATUS
++gco3D_SetClearColor(
++ IN gco3D Engine,
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++/* Set fixed point clear color. */
++gceSTATUS
++gco3D_SetClearColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point clear color. */
++gceSTATUS
++gco3D_SetClearColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set fixed point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Depth
++ );
++
++/* Set floating point clear depth. */
++gceSTATUS
++gco3D_SetClearDepthF(
++ IN gco3D Engine,
++ IN gctFLOAT Depth
++ );
++
++/* Set clear stencil. */
++gceSTATUS
++gco3D_SetClearStencil(
++ IN gco3D Engine,
++ IN gctUINT32 Stencil
++ );
++
++/* Set shading mode. */
++gceSTATUS
++gco3D_SetShading(
++ IN gco3D Engine,
++ IN gceSHADING Shading
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_EnableBlending(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set blending function. */
++gceSTATUS
++gco3D_SetBlendFunction(
++ IN gco3D Engine,
++ IN gceBLEND_UNIT Unit,
++ IN gceBLEND_FUNCTION FunctionRGB,
++ IN gceBLEND_FUNCTION FunctionAlpha
++ );
++
++/* Set blending mode. */
++gceSTATUS
++gco3D_SetBlendMode(
++ IN gco3D Engine,
++ IN gceBLEND_MODE ModeRGB,
++ IN gceBLEND_MODE ModeAlpha
++ );
++
++/* Set blending color. */
++gceSTATUS
++gco3D_SetBlendColor(
++ IN gco3D Engine,
++ IN gctUINT Red,
++ IN gctUINT Green,
++ IN gctUINT Blue,
++ IN gctUINT Alpha
++ );
++
++/* Set fixed point blending color. */
++gceSTATUS
++gco3D_SetBlendColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++/* Set floating point blending color. */
++gceSTATUS
++gco3D_SetBlendColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Set culling mode. */
++gceSTATUS
++gco3D_SetCulling(
++ IN gco3D Engine,
++ IN gceCULL Mode
++ );
++
++/* Enable point size */
++gceSTATUS
++gco3D_SetPointSizeEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set point sprite */
++gceSTATUS
++gco3D_SetPointSprite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set fill mode. */
++gceSTATUS
++gco3D_SetFill(
++ IN gco3D Engine,
++ IN gceFILL Mode
++ );
++
++/* Set depth compare mode. */
++gceSTATUS
++gco3D_SetDepthCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Enable depth writing. */
++gceSTATUS
++gco3D_EnableDepthWrite(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth mode. */
++gceSTATUS
++gco3D_SetDepthMode(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeX(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFIXED_POINT Near,
++ IN gctFIXED_POINT Far
++ );
++
++/* Set depth range. */
++gceSTATUS
++gco3D_SetDepthRangeF(
++ IN gco3D Engine,
++ IN gceDEPTH_MODE Mode,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Set last pixel enable */
++gceSTATUS
++gco3D_SetLastPixelEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set depth Bias and Scale */
++gceSTATUS
++gco3D_SetDepthScaleBiasX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT DepthScale,
++ IN gctFIXED_POINT DepthBias
++ );
++
++gceSTATUS
++gco3D_SetDepthScaleBiasF(
++ IN gco3D Engine,
++ IN gctFLOAT DepthScale,
++ IN gctFLOAT DepthBias
++ );
++
++/* Set depth near and far clipping plane. */
++gceSTATUS
++gco3D_SetDepthPlaneF(
++ IN gco3D Engine,
++ IN gctFLOAT Near,
++ IN gctFLOAT Far
++ );
++
++/* Enable or disable dithering. */
++gceSTATUS
++gco3D_EnableDither(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set color write enable bits. */
++gceSTATUS
++gco3D_SetColorWrite(
++ IN gco3D Engine,
++ IN gctUINT8 Enable
++ );
++
++/* Enable or disable early depth. */
++gceSTATUS
++gco3D_SetEarlyDepth(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Deprecated: Enable or disable all early depth operations. */
++gceSTATUS
++gco3D_SetAllEarlyDepthModes(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Enable or disable all early depth operations. */
++gceSTATUS
++gco3D_SetAllEarlyDepthModesEx(
++ IN gco3D Engine,
++ IN gctBOOL Disable,
++ IN gctBOOL DisableModify,
++ IN gctBOOL DisablePassZ
++ );
++
++/* Switch dynamic early mode */
++gceSTATUS
++gco3D_SwitchDynamicEarlyDepthMode(
++ IN gco3D Engine
++ );
++
++/* Set dynamic early mode */
++gceSTATUS
++gco3D_DisableDynamicEarlyDepthMode(
++ IN gco3D Engine,
++ IN gctBOOL Disable
++ );
++
++/* Enable or disable depth-only mode. */
++gceSTATUS
++gco3D_SetDepthOnly(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++typedef struct _gcsSTENCIL_INFO * gcsSTENCIL_INFO_PTR;
++typedef struct _gcsSTENCIL_INFO
++{
++ gceSTENCIL_MODE mode;
++
++ gctUINT8 maskFront;
++ gctUINT8 maskBack;
++ gctUINT8 writeMaskFront;
++ gctUINT8 writeMaskBack;
++
++ gctUINT8 referenceFront;
++
++ gceCOMPARE compareFront;
++ gceSTENCIL_OPERATION passFront;
++ gceSTENCIL_OPERATION failFront;
++ gceSTENCIL_OPERATION depthFailFront;
++
++ gctUINT8 referenceBack;
++ gceCOMPARE compareBack;
++ gceSTENCIL_OPERATION passBack;
++ gceSTENCIL_OPERATION failBack;
++ gceSTENCIL_OPERATION depthFailBack;
++}
++gcsSTENCIL_INFO;
++
++/* Set stencil mode. */
++gceSTATUS
++gco3D_SetStencilMode(
++ IN gco3D Engine,
++ IN gceSTENCIL_MODE Mode
++ );
++
++/* Set stencil mask. */
++gceSTATUS
++gco3D_SetStencilMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back mask. */
++gceSTATUS
++gco3D_SetStencilMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMask(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil back write mask. */
++gceSTATUS
++gco3D_SetStencilWriteMaskBack(
++ IN gco3D Engine,
++ IN gctUINT8 Mask
++ );
++
++/* Set stencil reference. */
++gceSTATUS
++gco3D_SetStencilReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctBOOL Front
++ );
++
++/* Set stencil compare. */
++gceSTATUS
++gco3D_SetStencilCompare(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceCOMPARE Compare
++ );
++
++/* Set stencil operation on pass. */
++gceSTATUS
++gco3D_SetStencilPass(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on fail. */
++gceSTATUS
++gco3D_SetStencilFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set stencil operation on depth fail. */
++gceSTATUS
++gco3D_SetStencilDepthFail(
++ IN gco3D Engine,
++ IN gceSTENCIL_WHERE Where,
++ IN gceSTENCIL_OPERATION Operation
++ );
++
++/* Set all stencil states in one blow. */
++gceSTATUS
++gco3D_SetStencilAll(
++ IN gco3D Engine,
++ IN gcsSTENCIL_INFO_PTR Info
++ );
++
++typedef struct _gcsALPHA_INFO * gcsALPHA_INFO_PTR;
++typedef struct _gcsALPHA_INFO
++{
++ /* Alpha test states. */
++ gctBOOL test;
++ gceCOMPARE compare;
++ gctUINT8 reference;
++ gctFLOAT floatReference;
++
++ /* Alpha blending states. */
++ gctBOOL blend;
++
++ gceBLEND_FUNCTION srcFuncColor;
++ gceBLEND_FUNCTION srcFuncAlpha;
++ gceBLEND_FUNCTION trgFuncColor;
++ gceBLEND_FUNCTION trgFuncAlpha;
++
++ gceBLEND_MODE modeColor;
++ gceBLEND_MODE modeAlpha;
++
++ gctUINT32 color;
++}
++gcsALPHA_INFO;
++
++/* Enable or disable alpha test. */
++gceSTATUS
++gco3D_SetAlphaTest(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set alpha test compare. */
++gceSTATUS
++gco3D_SetAlphaCompare(
++ IN gco3D Engine,
++ IN gceCOMPARE Compare
++ );
++
++/* Set alpha test reference in unsigned integer. */
++gceSTATUS
++gco3D_SetAlphaReference(
++ IN gco3D Engine,
++ IN gctUINT8 Reference,
++ IN gctFLOAT FloatReference
++ );
++
++/* Set alpha test reference in fixed point. */
++gceSTATUS
++gco3D_SetAlphaReferenceX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Reference
++ );
++
++/* Set alpha test reference in floating point. */
++gceSTATUS
++gco3D_SetAlphaReferenceF(
++ IN gco3D Engine,
++ IN gctFLOAT Reference
++ );
++
++/* Enable/Disable anti-alias line. */
++gceSTATUS
++gco3D_SetAntiAliasLine(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Set texture slot for anti-alias line. */
++gceSTATUS
++gco3D_SetAALineTexSlot(
++ IN gco3D Engine,
++ IN gctUINT TexSlot
++ );
++
++/* Set anti-alias line width scale. */
++gceSTATUS
++gco3D_SetAALineWidth(
++ IN gco3D Engine,
++ IN gctFLOAT Width
++ );
++
++/* Draw a number of primitives. */
++gceSTATUS
++gco3D_DrawPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctSIZE_T StartVertex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++gceSTATUS
++gco3D_DrawInstancedPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctBOOL DrawIndex,
++ IN gctSIZE_T StartVertex,
++ IN gctSIZE_T StartIndex,
++ IN gctSIZE_T PrimitiveCount,
++ IN gctSIZE_T VertexCount,
++ IN gctSIZE_T InstanceCount
++ );
++
++gceSTATUS
++gco3D_DrawPrimitivesCount(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT* StartVertex,
++ IN gctSIZE_T* VertexCount,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++
++/* Draw a number of primitives using offsets. */
++gceSTATUS
++gco3D_DrawPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives. */
++gceSTATUS
++gco3D_DrawIndexedPrimitives(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctSIZE_T BaseVertex,
++ IN gctSIZE_T StartIndex,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a number of indexed primitives using offsets. */
++gceSTATUS
++gco3D_DrawIndexedPrimitivesOffset(
++ IN gco3D Engine,
++ IN gcePRIMITIVE Type,
++ IN gctINT32 BaseOffset,
++ IN gctINT32 StartOffset,
++ IN gctSIZE_T PrimitiveCount
++ );
++
++/* Draw a element from pattern */
++gceSTATUS
++gco3D_DrawPattern(
++ IN gco3D Engine,
++ IN gcsFAST_FLUSH_PTR FastFlushInfo
++ );
++
++/* Enable or disable anti-aliasing. */
++gceSTATUS
++gco3D_SetAntiAlias(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++/* Write data into the command buffer. */
++gceSTATUS
++gco3D_WriteBuffer(
++ IN gco3D Engine,
++ IN gctCONST_POINTER Data,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Aligned
++ );
++
++/* Send sempahore and stall until sempahore is signalled. */
++gceSTATUS
++gco3D_Semaphore(
++ IN gco3D Engine,
++ IN gceWHERE From,
++ IN gceWHERE To,
++ IN gceHOW How);
++
++/* Explicitly flush shader L1 cache */
++gceSTATUS
++gco3D_FlushSHL1Cache(
++ IN gco3D Engine
++ );
++
++/* Set the subpixels center. */
++gceSTATUS
++gco3D_SetCentroids(
++ IN gco3D Engine,
++ IN gctUINT32 Index,
++ IN gctPOINTER Centroids
++ );
++
++gceSTATUS
++gco3D_SetLogicOp(
++ IN gco3D Engine,
++ IN gctUINT8 Rop
++ );
++
++gceSTATUS
++gco3D_SetOQ(
++ IN gco3D Engine,
++ INOUT gctPOINTER * Result,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco3D_GetOQ(
++ IN gco3D Engine,
++ IN gctPOINTER Result,
++ OUT gctINT64 * Logical
++ );
++
++gceSTATUS
++gco3D_DeleteOQ(
++ IN gco3D Engine,
++ INOUT gctPOINTER Result
++ );
++
++gceSTATUS
++gco3D_SetColorOutCount(
++ IN gco3D Engine,
++ IN gctUINT32 ColorOutCount
++ );
++
++gceSTATUS
++gco3D_Set3DEngine(
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gco3D_UnSet3DEngine(
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gco3D_Get3DEngine(
++ OUT gco3D * Engine
++ );
++
++
++/* OCL thread walker information. */
++typedef struct _gcsTHREAD_WALKER_INFO * gcsTHREAD_WALKER_INFO_PTR;
++typedef struct _gcsTHREAD_WALKER_INFO
++{
++ gctUINT32 dimensions;
++ gctUINT32 traverseOrder;
++ gctUINT32 enableSwathX;
++ gctUINT32 enableSwathY;
++ gctUINT32 enableSwathZ;
++ gctUINT32 swathSizeX;
++ gctUINT32 swathSizeY;
++ gctUINT32 swathSizeZ;
++ gctUINT32 valueOrder;
++
++ gctUINT32 globalSizeX;
++ gctUINT32 globalOffsetX;
++ gctUINT32 globalSizeY;
++ gctUINT32 globalOffsetY;
++ gctUINT32 globalSizeZ;
++ gctUINT32 globalOffsetZ;
++
++ gctUINT32 workGroupSizeX;
++ gctUINT32 workGroupCountX;
++ gctUINT32 workGroupSizeY;
++ gctUINT32 workGroupCountY;
++ gctUINT32 workGroupSizeZ;
++ gctUINT32 workGroupCountZ;
++
++ gctUINT32 threadAllocation;
++}
++gcsTHREAD_WALKER_INFO;
++
++/* Start OCL thread walker. */
++gceSTATUS
++gco3D_InvokeThreadWalker(
++ IN gco3D Engine,
++ IN gcsTHREAD_WALKER_INFO_PTR Info
++ );
++
++gceSTATUS
++gco3D_GetClosestRenderFormat(
++ IN gco3D Engine,
++ IN gceSURF_FORMAT InFormat,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++/* Set w clip and w plane limit value. */
++gceSTATUS
++gco3D_SetWClipEnable(
++ IN gco3D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco3D_GetWClipEnable(
++ IN gco3D Engine,
++ OUT gctBOOL * Enable
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitF(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimitX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Value
++ );
++
++gceSTATUS
++gco3D_SetWPlaneLimit(
++ IN gco3D Engine,
++ IN gctFLOAT Value
++ );
++
++gceSTATUS
++gco3D_PrimitiveRestart(
++ IN gco3D Engine,
++ IN gctBOOL PrimitiveRestart);
++
++#if gcdSTREAM_OUT_BUFFER
++
++gceSTATUS
++gco3D_QueryStreamOut(
++ IN gco3D Engine,
++ IN gctUINT32 OriginalIndexAddress,
++ IN gctUINT32 OriginalIndexOffset,
++ IN gctUINT32 OriginalIndexCount,
++ OUT gctBOOL_PTR Found
++ );
++
++gceSTATUS
++gco3D_StartStreamOut(
++ IN gco3D Engine,
++ IN gctINT StreamOutStatus,
++ IN gctUINT32 IndexAddress,
++ IN gctUINT32 IndexOffset,
++ IN gctUINT32 IndexCount
++ );
++
++gceSTATUS
++gco3D_StopStreamOut(
++ IN gco3D Engine
++ );
++
++gceSTATUS
++gco3D_ReplayStreamOut(
++ IN gco3D Engine,
++ IN gctUINT32 IndexAddress,
++ IN gctUINT32 IndexOffset,
++ IN gctUINT32 IndexCount
++ );
++
++gceSTATUS
++gco3D_EndStreamOut(
++ IN gco3D Engine
++ );
++
++#endif
++
++/*----------------------------------------------------------------------------*/
++/*-------------------------- gco3D Fragment Processor ------------------------*/
++
++/* Set the fragment processor configuration. */
++gceSTATUS
++gco3D_SetFragmentConfiguration(
++ IN gco3D Engine,
++ IN gctBOOL ColorFromStream,
++ IN gctBOOL EnableFog,
++ IN gctBOOL EnableSmoothPoint,
++ IN gctUINT32 ClipPlanes
++ );
++
++/* Enable/disable texture stage operation. */
++gceSTATUS
++gco3D_EnableTextureStage(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL Enable
++ );
++
++/* Program the channel enable masks for the color texture function. */
++gceSTATUS
++gco3D_SetTextureColorMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the channel enable masks for the alpha texture function. */
++gceSTATUS
++gco3D_SetTextureAlphaMask(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctBOOL ColorEnabled,
++ IN gctBOOL AlphaEnabled
++ );
++
++/* Program the constant fragment color. */
++gceSTATUS
++gco3D_SetFragmentColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFragmentColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant fog color. */
++gceSTATUS
++gco3D_SetFogColorX(
++ IN gco3D Engine,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetFogColorF(
++ IN gco3D Engine,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Program the constant texture color. */
++gceSTATUS
++gco3D_SetTetxureColorX(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFIXED_POINT Red,
++ IN gctFIXED_POINT Green,
++ IN gctFIXED_POINT Blue,
++ IN gctFIXED_POINT Alpha
++ );
++
++gceSTATUS
++gco3D_SetTetxureColorF(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++/* Configure color texture function. */
++gceSTATUS
++gco3D_SetColorTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/* Configure alpha texture function. */
++gceSTATUS
++gco3D_SetAlphaTextureFunction(
++ IN gco3D Engine,
++ IN gctINT Stage,
++ IN gceTEXTURE_FUNCTION Function,
++ IN gceTEXTURE_SOURCE Source0,
++ IN gceTEXTURE_CHANNEL Channel0,
++ IN gceTEXTURE_SOURCE Source1,
++ IN gceTEXTURE_CHANNEL Channel1,
++ IN gceTEXTURE_SOURCE Source2,
++ IN gceTEXTURE_CHANNEL Channel2,
++ IN gctINT Scale
++ );
++
++/******************************************************************************\
++******************************* gcoTEXTURE Object *******************************
++\******************************************************************************/
++
++/* Cube faces. */
++typedef enum _gceTEXTURE_FACE
++{
++ gcvFACE_NONE,
++ gcvFACE_POSITIVE_X,
++ gcvFACE_NEGATIVE_X,
++ gcvFACE_POSITIVE_Y,
++ gcvFACE_NEGATIVE_Y,
++ gcvFACE_POSITIVE_Z,
++ gcvFACE_NEGATIVE_Z,
++}
++gceTEXTURE_FACE;
++
++typedef struct _gcsTEXTURE
++{
++ /* Addressing modes. */
++ gceTEXTURE_ADDRESSING s;
++ gceTEXTURE_ADDRESSING t;
++ gceTEXTURE_ADDRESSING r;
++
++ gceTEXTURE_SWIZZLE swizzle[gcvTEXTURE_COMPONENT_NUM];
++
++ /* Border color. */
++ gctUINT8 border[gcvTEXTURE_COMPONENT_NUM];
++
++ /* Filters. */
++ gceTEXTURE_FILTER minFilter;
++ gceTEXTURE_FILTER magFilter;
++ gceTEXTURE_FILTER mipFilter;
++ gctUINT anisoFilter;
++
++ /* Level of detail. */
++ gctFLOAT lodBias;
++ gctFLOAT lodMin;
++ gctFLOAT lodMax;
++
++ /* base/max level */
++ gctINT32 baseLevel;
++ gctINT32 maxLevel;
++
++ /* depth texture comparison */
++ gceTEXTURE_COMPARE_MODE compareMode;
++ gceCOMPARE compareFunc;
++
++}
++gcsTEXTURE, * gcsTEXTURE_PTR;
++
++/* Construct a new gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Construct(
++ IN gcoHAL Hal,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Construct a new gcoTEXTURE object with type information. */
++gceSTATUS
++gcoTEXTURE_ConstructEx(
++ IN gcoHAL Hal,
++ IN gceTEXTURE_TYPE Type,
++ OUT gcoTEXTURE * Texture
++ );
++
++
++/* Construct a new sized gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_ConstructSized(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Depth,
++ IN gctUINT Faces,
++ IN gctUINT MipMapCount,
++ IN gcePOOL Pool,
++ OUT gcoTEXTURE * Texture
++ );
++
++/* Destroy an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Destroy(
++ IN gcoTEXTURE Texture
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_Upload(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_COLOR_SPACE SrcColorSpace
++ );
++
++/* Upload data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadSub(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T X,
++ IN gctSIZE_T Y,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_COLOR_SPACE SrcColorSpace,
++ IN gctUINT32 PhysicalAddress
++ );
++
++
++/* Upload YUV data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadYUV(
++ IN gcoTEXTURE Texture,
++ IN gceTEXTURE_FACE Face,
++ IN gctUINT Width,
++ IN gctUINT Height,
++ IN gctUINT Slice,
++ IN gctPOINTER Memory[3],
++ IN gctINT Stride[3],
++ IN gceSURF_FORMAT Format
++ );
++
++/* Upload compressed data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressed(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Upload compressed sub data to an gcoTEXTURE object. */
++gceSTATUS
++gcoTEXTURE_UploadCompressedSub(
++ IN gcoTEXTURE Texture,
++ IN gctINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ IN gctSIZE_T XOffset,
++ IN gctSIZE_T YOffset,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctUINT Slice,
++ IN gctCONST_POINTER Memory,
++ IN gctSIZE_T Size
++ );
++
++/* Get gcoSURF object for a mipmap level. */
++gceSTATUS
++gcoTEXTURE_GetMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ OUT gcoSURF * Surface
++ );
++
++/* Get gcoSURF object for a mipmap level and face offset. */
++gceSTATUS
++gcoTEXTURE_GetMipMapFace(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gceTEXTURE_FACE Face,
++ OUT gcoSURF * Surface,
++ OUT gctSIZE_T_PTR Offset
++ );
++
++gceSTATUS
++gcoTEXTURE_GetMipMapSlice(
++ IN gcoTEXTURE Texture,
++ IN gctUINT MipMap,
++ IN gctUINT Slice,
++ OUT gcoSURF * Surface,
++ OUT gctSIZE_T_PTR Offset
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctINT InternalFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctSIZE_T Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool,
++ OUT gcoSURF * Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapWithFlag(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctINT InternalFormat,
++ IN gceSURF_FORMAT Format,
++ IN gctSIZE_T Width,
++ IN gctSIZE_T Height,
++ IN gctSIZE_T Depth,
++ IN gctUINT Faces,
++ IN gcePOOL Pool,
++ IN gctBOOL Protected,
++ OUT gcoSURF * Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromClient(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_AddMipMapFromSurface(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoTEXTURE_SetEndianHint(
++ IN gcoTEXTURE Texture,
++ IN gceENDIAN_HINT EndianHint
++ );
++
++gceSTATUS
++gcoTEXTURE_Disable(
++ IN gcoHAL Hal,
++ IN gctINT Sampler
++ );
++
++gceSTATUS
++gcoTEXTURE_Flush(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_FlushVS(
++ IN gcoTEXTURE Texture
++ );
++
++gceSTATUS
++gcoTEXTURE_QueryCaps(
++ IN gcoHAL Hal,
++ OUT gctUINT * MaxWidth,
++ OUT gctUINT * MaxHeight,
++ OUT gctUINT * MaxDepth,
++ OUT gctBOOL * Cubic,
++ OUT gctBOOL * NonPowerOfTwo,
++ OUT gctUINT * VertexSamplers,
++ OUT gctUINT * PixelSamplers
++ );
++
++gceSTATUS
++gcoTEXTURE_GetClosestFormat(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT InFormat,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++gceSTATUS
++gcoTEXTURE_GetClosestFormatEx(
++ IN gcoHAL Hal,
++ IN gceSURF_FORMAT InFormat,
++ IN gceTEXTURE_TYPE TextureType,
++ OUT gceSURF_FORMAT* OutFormat
++ );
++
++gceSTATUS
++gcoTEXTURE_GetFormatInfo(
++ IN gcoTEXTURE Texture,
++ IN gctINT preferLevel,
++ OUT gcsSURF_FORMAT_INFO_PTR * TxFormatInfo
++ );
++
++gceSTATUS
++gcoTEXTURE_GetTextureFormatName(
++ IN gcsSURF_FORMAT_INFO_PTR TxFormatInfo,
++ OUT gctCONST_STRING * TxName
++ );
++
++gceSTATUS
++gcoTEXTURE_RenderIntoMipMap(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_RenderIntoMipMap2(
++ IN gcoTEXTURE Texture,
++ IN gctINT Level,
++ IN gctBOOL Sync
++ );
++
++gceSTATUS
++gcoTEXTURE_IsRenderable(
++ IN gcoTEXTURE Texture,
++ IN gctUINT Level
++ );
++
++gceSTATUS
++gcoTEXTURE_IsComplete(
++ IN gcoTEXTURE Texture,
++ IN gcsTEXTURE_PTR Info,
++ IN gctINT BaseLevel,
++ IN gctINT MaxLevel
++ );
++
++gceSTATUS
++gcoTEXTURE_BindTexture(
++ IN gcoTEXTURE Texture,
++ IN gctINT Target,
++ IN gctINT Sampler,
++ IN gcsTEXTURE_PTR Info
++ );
++
++gceSTATUS
++gcoTEXTURE_BindTextureEx(
++ IN gcoTEXTURE Texture,
++ IN gctINT Target,
++ IN gctINT Sampler,
++ IN gcsTEXTURE_PTR Info,
++ IN gctINT textureLayer
++ );
++
++gceSTATUS
++gcoTEXTURE_InitParams(
++ IN gcoHAL Hal,
++ IN gcsTEXTURE_PTR TexParams
++ );
++
++gceSTATUS
++gcoTEXTURE_SetDepthTextureFlag(
++ IN gcoTEXTURE Texture,
++ IN gctBOOL unsized
++ );
++
++
++/******************************************************************************\
++******************************* gcoSTREAM Object ******************************
++\******************************************************************************/
++
++typedef enum _gceVERTEX_FORMAT
++{
++ gcvVERTEX_BYTE,
++ gcvVERTEX_UNSIGNED_BYTE,
++ gcvVERTEX_SHORT,
++ gcvVERTEX_UNSIGNED_SHORT,
++ gcvVERTEX_INT,
++ gcvVERTEX_UNSIGNED_INT,
++ gcvVERTEX_FIXED,
++ gcvVERTEX_HALF,
++ gcvVERTEX_FLOAT,
++ gcvVERTEX_UNSIGNED_INT_10_10_10_2,
++ gcvVERTEX_INT_10_10_10_2,
++ gcvVERTEX_UNSIGNED_INT_2_10_10_10_REV,
++ gcvVERTEX_INT_2_10_10_10_REV,
++ /* integer format */
++ gcvVERTEX_INT8,
++ gcvVERTEX_INT16,
++ gcvVERTEX_INT32,
++}
++gceVERTEX_FORMAT;
++
++/* What the SW converting scheme to create temp attrib */
++typedef enum _gceATTRIB_SCHEME
++{
++ gcvATTRIB_SCHEME_KEEP = 0,
++ gcvATTRIB_SCHEME_2_10_10_10_REV_TO_FLOAT,
++ gcvATTRIB_SCHEME_BYTE_TO_INT,
++ gcvATTRIB_SCHEME_SHORT_TO_INT,
++ gcvATTRIB_SCHEME_UBYTE_TO_UINT,
++ gcvATTRIB_SCHEME_USHORT_TO_UINT,
++} gceATTRIB_SCHEME;
++
++gceSTATUS
++gcoSTREAM_Construct(
++ IN gcoHAL Hal,
++ OUT gcoSTREAM * Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Destroy(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Upload(
++ IN gcoSTREAM Stream,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Dynamic
++ );
++
++gceSTATUS
++gcoSTREAM_SetStride(
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoSTREAM_Size(
++ IN gcoSTREAM Stream,
++ OUT gctSIZE_T *Size
++ );
++
++gceSTATUS
++gcoSTREAM_Node(
++ IN gcoSTREAM Stream,
++ OUT gcsSURF_NODE_PTR * Node
++ );
++
++gceSTATUS
++gcoSTREAM_Lock(
++ IN gcoSTREAM Stream,
++ OUT gctPOINTER * Logical,
++ OUT gctUINT32 * Physical
++ );
++
++gceSTATUS
++gcoSTREAM_Unlock(
++ IN gcoSTREAM Stream
++ );
++
++gceSTATUS
++gcoSTREAM_Reserve(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gcoSTREAM_Flush(
++ IN gcoSTREAM Stream
++ );
++
++/* Dynamic buffer API. */
++gceSTATUS
++gcoSTREAM_SetDynamic(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Bytes,
++ IN gctUINT Buffers
++ );
++
++typedef struct _gcsSTREAM_INFO
++{
++ gctUINT index;
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT components;
++ gctSIZE_T size;
++ gctCONST_POINTER data;
++ gctUINT stride;
++}
++gcsSTREAM_INFO, * gcsSTREAM_INFO_PTR;
++
++gceSTATUS
++gcoSTREAM_UploadDynamic(
++ IN gcoSTREAM Stream,
++ IN gctUINT VertexCount,
++ IN gctUINT InfoCount,
++ IN gcsSTREAM_INFO_PTR Info,
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoSTREAM_CPUCacheOperation(
++ IN gcoSTREAM Stream,
++ IN gceCACHEOPERATION Operation
++ );
++
++gceSTATUS
++gcoSTREAM_CPUCacheOperation_Range(
++ IN gcoSTREAM Stream,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Length,
++ IN gceCACHEOPERATION Operation
++ );
++
++/******************************************************************************\
++******************************** gcoVERTEX Object ******************************
++\******************************************************************************/
++
++typedef struct _gcsVERTEX_ATTRIBUTES
++{
++ gceVERTEX_FORMAT format;
++ gctBOOL normalized;
++ gctUINT32 components;
++ gctSIZE_T size;
++ gctUINT32 stream;
++ gctUINT32 offset;
++ gctUINT32 stride;
++}
++gcsVERTEX_ATTRIBUTES;
++
++gceSTATUS
++gcoVERTEX_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEX * Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Destroy(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_Reset(
++ IN gcoVERTEX Vertex
++ );
++
++gceSTATUS
++gcoVERTEX_EnableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index,
++ IN gceVERTEX_FORMAT Format,
++ IN gctBOOL Normalized,
++ IN gctUINT32 Components,
++ IN gcoSTREAM Stream,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Stride
++ );
++
++gceSTATUS
++gcoVERTEX_DisableAttribute(
++ IN gcoVERTEX Vertex,
++ IN gctUINT32 Index
++ );
++
++gceSTATUS
++gcoVERTEX_Bind(
++ IN gcoVERTEX Vertex
++ );
++
++/*******************************************************************************
++***** gcoVERTEXARRAY Object ***************************************************/
++
++typedef struct _gcsATTRIBUTE
++{
++ /* Enabled. */
++ gctBOOL enable;
++
++ /* Number of components. */
++ gctINT size;
++
++ /* Attribute format. */
++ gceVERTEX_FORMAT format;
++
++ /* Flag whether the attribute is normalized or not. */
++ gctBOOL normalized;
++
++ /* Stride of the component. */
++ gctSIZE_T stride;
++
++ /* Divisor of the attribute */
++ gctUINT divisor;
++
++ /* Pointer to the attribute data. */
++ gctCONST_POINTER pointer;
++
++ /* Stream object owning the attribute data. */
++ gcoBUFOBJ stream;
++
++ /* Generic values for attribute. */
++ gctFLOAT genericValue[4];
++
++ /* Generic size for attribute. */
++ gctINT genericSize;
++
++ /* Vertex shader linkage. */
++ gctUINT linkage;
++
++#if gcdUSE_WCLIP_PATCH
++ /* Does it hold positions? */
++ gctBOOL isPosition;
++#endif
++
++ /* Index to vertex array */
++ gctINT arrayIdx;
++
++ gceATTRIB_SCHEME convertScheme;
++
++ /* Pointer to the temporary buffer to be freed */
++ gcoBUFOBJ tempStream;
++
++ /* Pointer to the temporary memory to be freed */
++ gctCONST_POINTER tempMemory;
++}
++gcsATTRIBUTE,
++* gcsATTRIBUTE_PTR;
++
++
++typedef struct _gcsVERTEXARRAY
++{
++ /* Enabled. */
++ gctBOOL enable;
++
++ /* Number of components. */
++ gctINT size;
++
++ /* Attribute format. */
++ gceVERTEX_FORMAT format;
++
++ /* Flag whether the attribute is normalized or not. */
++ gctBOOL normalized;
++
++ /* Stride of the component. */
++ gctUINT stride;
++
++ /* Divisor of the attribute */
++ gctUINT divisor;
++
++ /* Pointer to the attribute data. */
++ gctCONST_POINTER pointer;
++
++ /* Stream object owning the attribute data. */
++ gcoSTREAM stream;
++
++ /* Generic values for attribute. */
++ gctFLOAT genericValue[4];
++
++ /* Generic size for attribute. */
++ gctINT genericSize;
++
++ /* Vertex shader linkage. */
++ gctUINT linkage;
++
++ gctBOOL isPosition;
++}
++gcsVERTEXARRAY,
++* gcsVERTEXARRAY_PTR;
++
++gceSTATUS
++gcoVERTEXARRAY_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVERTEXARRAY * Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Destroy(
++ IN gcoVERTEXARRAY Vertex
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind_Ex(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsVERTEXARRAY_PTR VertexArray,
++ IN gctUINT First,
++ IN gctSIZE_T Count,
++ IN gctBOOL DrawArraysInstanced,
++ IN gctSIZE_T InstanceCount,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoINDEX IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctUINT * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty
++#else
++ IN OUT gctUINT * PrimitiveCount
++#endif
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind_Ex2(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsATTRIBUTE_PTR VertexArray,
++ IN gctSIZE_T First,
++ IN gctSIZE_T Count,
++ IN gctBOOL DrawArraysInstanced,
++ IN gctSIZE_T InstanceCount,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoBUFOBJ IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctSIZE_T * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty,
++#else
++ IN OUT gctUINT * PrimitiveCount,
++#endif
++ IN gctINT VertexInstanceIdLinkage
++ );
++
++gceSTATUS
++gcoVERTEXARRAY_Bind(
++ IN gcoVERTEXARRAY Vertex,
++ IN gctUINT32 EnableBits,
++ IN gcsVERTEXARRAY_PTR VertexArray,
++ IN gctUINT First,
++ IN gctSIZE_T Count,
++ IN gceINDEX_TYPE IndexType,
++ IN gcoINDEX IndexObject,
++ IN gctPOINTER IndexMemory,
++ IN OUT gcePRIMITIVE * PrimitiveType,
++#if gcdUSE_WCLIP_PATCH
++ IN OUT gctUINT * PrimitiveCount,
++ IN OUT gctFLOAT * wLimitRms,
++ IN OUT gctBOOL * wLimitDirty
++#else
++ IN OUT gctUINT * PrimitiveCount
++#endif
++ );
++
++/*******************************************************************************
++***** Composition *************************************************************/
++
++typedef enum _gceCOMPOSITION
++{
++ gcvCOMPOSE_CLEAR = 1,
++ gcvCOMPOSE_BLUR,
++ gcvCOMPOSE_DIM,
++ gcvCOMPOSE_LAYER
++}
++gceCOMPOSITION;
++
++typedef struct _gcsCOMPOSITION * gcsCOMPOSITION_PTR;
++typedef struct _gcsCOMPOSITION
++{
++ /* Structure size. */
++ gctUINT structSize;
++
++ /* Composition operation. */
++ gceCOMPOSITION operation;
++
++ /* Layer to be composed. */
++ gcoSURF layer;
++
++ /* Source and target coordinates. */
++ gcsRECT srcRect;
++ gcsRECT trgRect;
++
++ /* Target rectangle */
++ gcsPOINT v0;
++ gcsPOINT v1;
++ gcsPOINT v2;
++
++ /* Blending parameters. */
++ gctBOOL enableBlending;
++ gctBOOL premultiplied;
++ gctUINT8 alphaValue;
++
++ /* Clear color. */
++ gctFLOAT r;
++ gctFLOAT g;
++ gctFLOAT b;
++ gctFLOAT a;
++}
++gcsCOMPOSITION;
++
++gceSTATUS
++gco3D_ProbeComposition(
++ IN gcoHARDWARE Hardware,
++ IN gctBOOL ResetIfEmpty
++ );
++
++gceSTATUS
++gco3D_CompositionBegin(
++ IN gcoHARDWARE Hardware
++ );
++
++gceSTATUS
++gco3D_ComposeLayer(
++ IN gcoHARDWARE Hardware,
++ IN gcsCOMPOSITION_PTR Layer
++ );
++
++gceSTATUS
++gco3D_CompositionSignals(
++ IN gcoHARDWARE Hardware,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal1,
++ IN gctSIGNAL Signal2
++ );
++
++gceSTATUS
++gco3D_CompositionEnd(
++ IN gcoHARDWARE Hardware,
++ IN gcoSURF Target,
++ IN gctBOOL Synchronous
++ );
++
++/* Frame Database */
++gceSTATUS
++gcoHAL_AddFrameDB(
++ void
++ );
++
++gceSTATUS
++gcoHAL_DumpFrameDB(
++ gctCONST_STRING Filename OPTIONAL
++ );
++
++/******************************************************************************
++**********************gcoBUFOBJ object*****************************************
++*******************************************************************************/
++typedef enum _gceBUFOBJ_TYPE
++{
++ gcvBUFOBJ_TYPE_ARRAY_BUFFER = 1,
++ gcvBUFOBJ_TYPE_ELEMENT_ARRAY_BUFFER = 2,
++ gcvBUFOBJ_TYPE_GENERIC_BUFFER = 100
++
++} gceBUFOBJ_TYPE;
++
++typedef enum _gceBUFOBJ_USAGE
++{
++ gcvBUFOBJ_USAGE_STREAM_DRAW = 1,
++ gcvBUFOBJ_USAGE_STREAM_READ,
++ gcvBUFOBJ_USAGE_STREAM_COPY,
++ gcvBUFOBJ_USAGE_STATIC_DRAW,
++ gcvBUFOBJ_USAGE_STATIC_READ,
++ gcvBUFOBJ_USAGE_STATIC_COPY,
++ gcvBUFOBJ_USAGE_DYNAMIC_DRAW,
++ gcvBUFOBJ_USAGE_DYNAMIC_READ,
++ gcvBUFOBJ_USAGE_DYNAMIC_COPY,
++
++} gceBUFOBJ_USAGE;
++
++/* Construct a new gcoBUFOBJ object. */
++gceSTATUS
++gcoBUFOBJ_Construct(
++ IN gcoHAL Hal,
++ IN gceBUFOBJ_TYPE Type,
++ OUT gcoBUFOBJ * BufObj
++ );
++
++/* Destroy a gcoBUFOBJ object. */
++gceSTATUS
++gcoBUFOBJ_Destroy(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Lock pbo in memory. */
++gceSTATUS
++gcoBUFOBJ_Lock(
++ IN gcoBUFOBJ BufObj,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Lock pbo in memory. */
++gceSTATUS
++gcoBUFOBJ_FastLock(
++ IN gcoBUFOBJ BufObj,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Unlock pbo that was previously locked with gcoBUFOBJ_Lock. */
++gceSTATUS
++gcoBUFOBJ_Unlock(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Free existing pbo buffer. */
++gceSTATUS
++gcoBUFOBJ_Free(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Upload data into an pbo buffer. */
++gceSTATUS
++gcoBUFOBJ_Upload(
++ IN gcoBUFOBJ BufObj,
++ IN gctCONST_POINTER Buffer,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Bytes,
++ IN gceBUFOBJ_USAGE Usage
++ );
++
++/* Bind an index object to the hardware. */
++gceSTATUS
++gcoBUFOBJ_IndexBind (
++ IN gcoBUFOBJ Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctSIZE_T Count
++ );
++
++/* Find min and max index for the index buffer */
++gceSTATUS
++gcoBUFOBJ_IndexGetRange(
++ IN gcoBUFOBJ Index,
++ IN gceINDEX_TYPE Type,
++ IN gctUINT32 Offset,
++ IN gctUINT32 Count,
++ OUT gctUINT32 * MinimumIndex,
++ OUT gctUINT32 * MaximumIndex
++ );
++
++/* Sets a buffer object as dirty */
++gceSTATUS
++gcoBUFOBJ_SetDirty(
++ IN gcoBUFOBJ BufObj
++ );
++
++/* Creates a new buffer if needed */
++gceSTATUS
++gcoBUFOBJ_AlignIndexBufferWhenNeeded(
++ IN gcoBUFOBJ BufObj,
++ IN gctSIZE_T Offset,
++ OUT gcoBUFOBJ * AlignedBufObj
++ );
++
++/* Cache operations on whole range */
++gceSTATUS
++gcoBUFOBJ_CPUCacheOperation(
++ IN gcoBUFOBJ BufObj,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Cache operations on a specified range */
++gceSTATUS
++gcoBUFOBJ_CPUCacheOperation_Range(
++ IN gcoBUFOBJ BufObj,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Length,
++ IN gceCACHEOPERATION Operation
++ );
++
++/* Return size of the bufobj */
++gceSTATUS
++gcoBUFOBJ_GetSize(
++ IN gcoBUFOBJ BufObj,
++ OUT gctSIZE_T_PTR Size
++ );
++
++/* Return memory node of the bufobj */
++gceSTATUS
++gcoBUFOBJ_GetNode(
++ IN gcoBUFOBJ BufObj,
++ OUT gcsSURF_NODE_PTR * Node
++ );
++
++/* Handle GPU cache operations */
++gceSTATUS
++gcoBUFOBJ_GPUCacheOperation(
++ gcoBUFOBJ BufObj
++ );
++
++/* Dump buffer. */
++void
++gcoBUFOBJ_Dump(
++ IN gcoBUFOBJ BufObj
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* gcdENABLE_3D */
++#endif /* __gc_hal_engine_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine_vg.h 2016-06-19 22:11:55.237144468 +0200
+@@ -0,0 +1,1215 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_engine_vg_h_
++#define __gc_hal_engine_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#include "gc_hal_types.h"
++
++/******************************************************************************\
++******************************** VG Enumerations *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Tiling mode for painting and imagig.
++**
++** This enumeration defines the tiling modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 tile modes.
++*/
++typedef enum _gceTILE_MODE
++{
++ gcvTILE_FILL,
++ gcvTILE_PAD,
++ gcvTILE_REPEAT,
++ gcvTILE_REFLECT
++}
++gceTILE_MODE;
++
++/******************************************************************************/
++/** @ingroup gcoVG
++**
++** @brief The different paint modes.
++**
++** This enumeration lists the available paint modes.
++*/
++typedef enum _gcePAINT_TYPE
++{
++ /** Solid color. */
++ gcvPAINT_MODE_SOLID,
++
++ /** Linear gradient. */
++ gcvPAINT_MODE_LINEAR,
++
++ /** Radial gradient. */
++ gcvPAINT_MODE_RADIAL,
++
++ /** Pattern. */
++ gcvPAINT_MODE_PATTERN,
++
++ /** Mode count. */
++ gcvPAINT_MODE_COUNT
++}
++gcePAINT_TYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Types of path data supported by HAL.
++**
++** This enumeration defines the types of path data supported by the HAL.
++** This is in fact a one-to-one mapping of the OpenVG 1.1 path types.
++*/
++typedef enum _gcePATHTYPE
++{
++ gcePATHTYPE_UNKNOWN = -1,
++ gcePATHTYPE_INT8,
++ gcePATHTYPE_INT16,
++ gcePATHTYPE_INT32,
++ gcePATHTYPE_FLOAT
++}
++gcePATHTYPE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Supported path segment commands.
++**
++** This enumeration defines the path segment commands supported by the HAL.
++*/
++typedef enum _gceVGCMD
++{
++ gcvVGCMD_END, /* 0: GCCMD_TS_OPCODE_END */
++ gcvVGCMD_CLOSE, /* 1: GCCMD_TS_OPCODE_CLOSE */
++ gcvVGCMD_MOVE, /* 2: GCCMD_TS_OPCODE_MOVE */
++ gcvVGCMD_MOVE_REL, /* 3: GCCMD_TS_OPCODE_MOVE_REL */
++ gcvVGCMD_LINE, /* 4: GCCMD_TS_OPCODE_LINE */
++ gcvVGCMD_LINE_REL, /* 5: GCCMD_TS_OPCODE_LINE_REL */
++ gcvVGCMD_QUAD, /* 6: GCCMD_TS_OPCODE_QUADRATIC */
++ gcvVGCMD_QUAD_REL, /* 7: GCCMD_TS_OPCODE_QUADRATIC_REL */
++ gcvVGCMD_CUBIC, /* 8: GCCMD_TS_OPCODE_CUBIC */
++ gcvVGCMD_CUBIC_REL, /* 9: GCCMD_TS_OPCODE_CUBIC_REL */
++ gcvVGCMD_BREAK, /* 10: GCCMD_TS_OPCODE_BREAK */
++ gcvVGCMD_HLINE, /* 11: ******* R E S E R V E D *******/
++ gcvVGCMD_HLINE_REL, /* 12: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE, /* 13: ******* R E S E R V E D *******/
++ gcvVGCMD_VLINE_REL, /* 14: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD, /* 15: ******* R E S E R V E D *******/
++ gcvVGCMD_SQUAD_REL, /* 16: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC, /* 17: ******* R E S E R V E D *******/
++ gcvVGCMD_SCUBIC_REL, /* 18: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC, /* 19: ******* R E S E R V E D *******/
++ gcvVGCMD_SCCWARC_REL, /* 20: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC, /* 21: ******* R E S E R V E D *******/
++ gcvVGCMD_SCWARC_REL, /* 22: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC, /* 23: ******* R E S E R V E D *******/
++ gcvVGCMD_LCCWARC_REL, /* 24: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC, /* 25: ******* R E S E R V E D *******/
++ gcvVGCMD_LCWARC_REL, /* 26: ******* R E S E R V E D *******/
++
++ /* The width of the command recognized by the hardware on bits. */
++ gcvVGCMD_WIDTH = 5,
++
++ /* Hardware command mask. */
++ gcvVGCMD_MASK = (1 << gcvVGCMD_WIDTH) - 1,
++
++ /* Command modifiers. */
++ gcvVGCMD_H_MOD = 1 << gcvVGCMD_WIDTH, /* = 32 */
++ gcvVGCMD_V_MOD = 2 << gcvVGCMD_WIDTH, /* = 64 */
++ gcvVGCMD_S_MOD = 3 << gcvVGCMD_WIDTH, /* = 96 */
++ gcvVGCMD_ARC_MOD = 4 << gcvVGCMD_WIDTH, /* = 128 */
++
++ /* Emulated LINE commands. */
++ gcvVGCMD_HLINE_EMUL = gcvVGCMD_H_MOD | gcvVGCMD_LINE, /* = 36 */
++ gcvVGCMD_HLINE_EMUL_REL = gcvVGCMD_H_MOD | gcvVGCMD_LINE_REL, /* = 37 */
++ gcvVGCMD_VLINE_EMUL = gcvVGCMD_V_MOD | gcvVGCMD_LINE, /* = 68 */
++ gcvVGCMD_VLINE_EMUL_REL = gcvVGCMD_V_MOD | gcvVGCMD_LINE_REL, /* = 69 */
++
++ /* Emulated SMOOTH commands. */
++ gcvVGCMD_SQUAD_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD, /* = 102 */
++ gcvVGCMD_SQUAD_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD_REL, /* = 103 */
++ gcvVGCMD_SCUBIC_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC, /* = 104 */
++ gcvVGCMD_SCUBIC_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC_REL, /* = 105 */
++
++ /* Emulation ARC commands. */
++ gcvVGCMD_ARC_LINE = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE, /* = 132 */
++ gcvVGCMD_ARC_LINE_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE_REL, /* = 133 */
++ gcvVGCMD_ARC_QUAD = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD, /* = 134 */
++ gcvVGCMD_ARC_QUAD_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD_REL /* = 135 */
++}
++gceVGCMD;
++typedef enum _gceVGCMD * gceVGCMD_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Blending modes supported by the HAL.
++**
++** This enumeration defines the blending modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 blending modes.
++*/
++typedef enum _gceVG_BLEND
++{
++ gcvVG_BLEND_SRC,
++ gcvVG_BLEND_SRC_OVER,
++ gcvVG_BLEND_DST_OVER,
++ gcvVG_BLEND_SRC_IN,
++ gcvVG_BLEND_DST_IN,
++ gcvVG_BLEND_MULTIPLY,
++ gcvVG_BLEND_SCREEN,
++ gcvVG_BLEND_DARKEN,
++ gcvVG_BLEND_LIGHTEN,
++ gcvVG_BLEND_ADDITIVE,
++ gcvVG_BLEND_SUBTRACT,
++ gcvVG_BLEND_FILTER
++}
++gceVG_BLEND;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Image modes supported by the HAL.
++**
++** This enumeration defines the image modes supported by the HAL. This is
++** in fact a one-to-one mapping of the OpenVG 1.1 image modes with the addition
++** of NO IMAGE.
++*/
++typedef enum _gceVG_IMAGE
++{
++ gcvVG_IMAGE_NONE,
++ gcvVG_IMAGE_NORMAL,
++ gcvVG_IMAGE_MULTIPLY,
++ gcvVG_IMAGE_STENCIL,
++ gcvVG_IMAGE_FILTER
++}
++gceVG_IMAGE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Filter mode patterns and imaging.
++**
++** This enumeration defines the filter modes supported by the HAL.
++*/
++typedef enum _gceIMAGE_FILTER
++{
++ gcvFILTER_POINT,
++ gcvFILTER_LINEAR,
++ gcvFILTER_BI_LINEAR
++}
++gceIMAGE_FILTER;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Primitive modes supported by the HAL.
++**
++** This enumeration defines the primitive modes supported by the HAL.
++*/
++typedef enum _gceVG_PRIMITIVE
++{
++ gcvVG_SCANLINE,
++ gcvVG_RECTANGLE,
++ gcvVG_TESSELLATED,
++ gcvVG_TESSELLATED_TILED
++}
++gceVG_PRIMITIVE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rendering quality modes supported by the HAL.
++**
++** This enumeration defines the rendering quality modes supported by the HAL.
++*/
++typedef enum _gceRENDER_QUALITY
++{
++ gcvVG_NONANTIALIASED,
++ gcvVG_2X2_MSAA,
++ gcvVG_2X4_MSAA,
++ gcvVG_4X4_MSAA
++}
++gceRENDER_QUALITY;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Fill rules supported by the HAL.
++**
++** This enumeration defines the fill rules supported by the HAL.
++*/
++typedef enum _gceFILL_RULE
++{
++ gcvVG_EVEN_ODD,
++ gcvVG_NON_ZERO
++}
++gceFILL_RULE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Cap styles supported by the HAL.
++**
++** This enumeration defines the cap styles supported by the HAL.
++*/
++typedef enum _gceCAP_STYLE
++{
++ gcvCAP_BUTT,
++ gcvCAP_ROUND,
++ gcvCAP_SQUARE
++}
++gceCAP_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Join styles supported by the HAL.
++**
++** This enumeration defines the join styles supported by the HAL.
++*/
++typedef enum _gceJOIN_STYLE
++{
++ gcvJOIN_MITER,
++ gcvJOIN_ROUND,
++ gcvJOIN_BEVEL
++}
++gceJOIN_STYLE;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Channel mask values.
++**
++** This enumeration defines the values for channel mask used in image
++** filtering.
++*/
++
++/* Base values for channel mask definitions. */
++#define gcvCHANNEL_X (0)
++#define gcvCHANNEL_R (1 << 0)
++#define gcvCHANNEL_G (1 << 1)
++#define gcvCHANNEL_B (1 << 2)
++#define gcvCHANNEL_A (1 << 3)
++
++typedef enum _gceCHANNEL
++{
++ gcvCHANNEL_XXXX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XXXA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XXBX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XXBA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_XGXX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_XGXA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_XGBX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_XGBA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RXXX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RXXA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RXBX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RXBA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A),
++
++ gcvCHANNEL_RGXX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X),
++ gcvCHANNEL_RGXA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A),
++ gcvCHANNEL_RGBX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X),
++ gcvCHANNEL_RGBA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A),
++}
++gceCHANNEL;
++
++/******************************************************************************\
++******************************** VG Structures *******************************
++\******************************************************************************/
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsCOLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFLOAT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFLOAT red;
++
++ /** Green color channel value for the color stop. */
++ gctFLOAT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFLOAT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFLOAT alpha;
++}
++gcsCOLOR_RAMP, * gcsCOLOR_RAMP_PTR;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the color ramp used by the gradient paints in fixed form.
++**
++** The gcsCOLOR_RAMP structure defines the layout of one single color inside
++** a color ramp which is used by gradient paints.
++*/
++typedef struct _gcsFIXED_COLOR_RAMP
++{
++ /** Value for the color stop. */
++ gctFIXED_POINT stop;
++
++ /** Red color channel value for the color stop. */
++ gctFIXED_POINT red;
++
++ /** Green color channel value for the color stop. */
++ gctFIXED_POINT green;
++
++ /** Blue color channel value for the color stop. */
++ gctFIXED_POINT blue;
++
++ /** Alpha color channel value for the color stop. */
++ gctFIXED_POINT alpha;
++}
++gcsFIXED_COLOR_RAMP, * gcsFIXED_COLOR_RAMP_PTR;
++
++
++/**
++** @ingroup gcoVG
++**
++** @brief Rectangle structure used by the gcoVG object.
++**
++** This structure defines the layout of a rectangle. Make sure width and
++** height are larger than 0.
++*/
++typedef struct _gcsVG_RECT * gcsVG_RECT_PTR;
++typedef struct _gcsVG_RECT
++{
++ /** Left location of the rectangle. */
++ gctINT x;
++
++ /** Top location of the rectangle. */
++ gctINT y;
++
++ /** Width of the rectangle. */
++ gctINT width;
++
++ /** Height of the rectangle. */
++ gctINT height;
++}
++gcsVG_RECT;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Path command buffer attribute structure.
++**
++** The gcsPATH_BUFFER_INFO structure contains the specifics about
++** the layout of the path data command buffer.
++*/
++typedef struct _gcsPATH_BUFFER_INFO * gcsPATH_BUFFER_INFO_PTR;
++typedef struct _gcsPATH_BUFFER_INFO
++{
++ gctUINT reservedForHead;
++ gctUINT reservedForTail;
++}
++gcsPATH_BUFFER_INFO;
++
++/**
++** @ingroup gcoVG
++**
++** @brief Definition of the path data container structure.
++**
++** The gcsPATH structure defines the layout of the path data container.
++*/
++typedef struct _gcsPATH_DATA * gcsPATH_DATA_PTR;
++typedef struct _gcsPATH_DATA
++{
++ /* Data container in command buffer format. */
++ gcsCMDBUFFER data;
++
++ /* Path data type. */
++ gcePATHTYPE dataType;
++}
++gcsPATH_DATA;
++
++
++/******************************************************************************\
++********************************* gcoHAL Object ********************************
++\******************************************************************************/
++
++/* Query path data storage attributes. */
++gceSTATUS
++gcoHAL_QueryPathStorage(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ OUT gcsPATH_BUFFER_INFO_PTR Information
++ );
++
++/* Associate a completion signal with the command buffer. */
++gceSTATUS
++gcoHAL_AssociateCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Release the current command buffer completion signal. */
++gceSTATUS
++gcoHAL_DeassociateCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Verify whether the command buffer is still in use. */
++gceSTATUS
++gcoHAL_CheckCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Wait until the command buffer is no longer in use. */
++gceSTATUS
++gcoHAL_WaitCompletion(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++/* Flush the pixel cache. */
++gceSTATUS
++gcoHAL_Flush(
++ IN gcoHAL Hal
++#if GC355_PROFILER
++ ,
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++#endif
++ );
++
++/* Split a harwdare address into pool and offset. */
++gceSTATUS
++gcoHAL_SplitAddress(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Combine pool and offset into a harwdare address. */
++gceSTATUS
++gcoHAL_CombineAddress(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcePOOL Pool,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Schedule to free linear video memory allocated. */
++gceSTATUS
++gcoHAL_ScheduleVideoMemory(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT32 Node
++ );
++
++/* Free linear video memory allocated with gcoHAL_AllocateLinearVideoMemory. */
++gceSTATUS
++gcoHAL_FreeVideoMemory(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT32 Node
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gcoHAL_QueryCommandBuffer(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++/* Allocate and lock linear video memory. */
++gceSTATUS
++gcoHAL_AllocateLinearVideoMemory(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ IN gcePOOL Pool,
++ OUT gctUINT32 * Node,
++ OUT gctUINT32 * Address,
++ OUT gctPOINTER * Memory
++ );
++
++/* Align the specified size accordingly to the hardware requirements. */
++gceSTATUS
++gcoHAL_GetAlignedSurfaceSize(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++gceSTATUS
++gcoHAL_ReserveTask(
++ IN gcoHAL Hal,
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceBLOCK Block,
++ IN gctUINT TaskCount,
++ IN gctUINT32 Bytes,
++ OUT gctPOINTER * Memory
++ );
++/******************************************************************************\
++********************************** gcoVG Object ********************************
++\******************************************************************************/
++
++/** @defgroup gcoVG gcoVG
++**
++** The gcoVG object abstracts the VG hardware pipe.
++*/
++#if GC355_PROFILER
++void
++gcoVG_ProfilerEnableDisable(
++ IN gcoVG Vg,
++ IN gctUINT enableGetAPITimes,
++ IN gctFILE apiTimeFile
++ );
++
++void
++gcoVG_ProfilerTreeDepth(
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth
++ );
++
++void
++gcoVG_ProfilerSetStates(
++ IN gcoVG Vg,
++ IN gctUINT treeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++ );
++#endif
++
++gctBOOL
++gcoVG_IsMaskSupported(
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsTargetSupported(
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_FORMAT Format
++ );
++
++gctBOOL
++gcoVG_IsImageSupported(
++#if GC355_PROFILER
++ IN gcoVG Vg,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceSURF_FORMAT Format
++ );
++
++gctUINT8 gcoVG_PackColorComponent(
++#if GC355_PROFILER
++ gcoVG Vg,
++ gctUINT TreeDepth,
++ gctUINT saveLayerTreeDepth,
++ gctUINT varTreeDepth,
++#endif
++ gctFLOAT Value
++ );
++
++gceSTATUS
++gcoVG_Construct(
++ IN gcoHAL Hal,
++ OUT gcoVG * Vg
++ );
++
++gceSTATUS
++gcoVG_Destroy(
++ IN gcoVG Vg
++#if GC355_PROFILER
++ ,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++#endif
++ );
++
++gceSTATUS
++gcoVG_SetTarget(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Target
++ );
++
++gceSTATUS
++gcoVG_UnsetTarget(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_SetUserToSurface(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT UserToSurface[9]
++ );
++
++gceSTATUS
++gcoVG_SetSurfaceToImage(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT SurfaceToImage[9]
++ );
++
++gceSTATUS
++gcoVG_EnableMask(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetMask(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Mask
++ );
++
++gceSTATUS
++gcoVG_UnsetMask(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Surface
++ );
++
++gceSTATUS
++gcoVG_FlushMask(
++ IN gcoVG Vg
++#if GC355_PROFILER
++ ,
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth
++#endif
++ );
++
++gceSTATUS
++gcoVG_EnableScissor(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetScissor(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctSIZE_T RectangleCount,
++ IN gcsVG_RECT_PTR Rectangles
++ );
++
++gceSTATUS
++gcoVG_EnableColorTransform(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gcoVG_SetColorTransform(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT ColorTransform[8]
++ );
++
++gceSTATUS
++gcoVG_SetTileFillColor(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT Red,
++ IN gctFLOAT Green,
++ IN gctFLOAT Blue,
++ IN gctFLOAT Alpha
++ );
++
++gceSTATUS
++gcoVG_SetSolidPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctUINT8 Red,
++ IN gctUINT8 Green,
++ IN gctUINT8 Blue,
++ IN gctUINT8 Alpha
++ );
++
++gceSTATUS
++gcoVG_SetLinearPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT Constant,
++ IN gctFLOAT StepX,
++ IN gctFLOAT StepY
++ );
++
++gceSTATUS
++gcoVG_SetRadialPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT LinConstant,
++ IN gctFLOAT LinStepX,
++ IN gctFLOAT LinStepY,
++ IN gctFLOAT RadConstant,
++ IN gctFLOAT RadStepX,
++ IN gctFLOAT RadStepY,
++ IN gctFLOAT RadStepXX,
++ IN gctFLOAT RadStepYY,
++ IN gctFLOAT RadStepXY
++ );
++
++gceSTATUS
++gcoVG_SetPatternPaint(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctFLOAT UConstant,
++ IN gctFLOAT UStepX,
++ IN gctFLOAT UStepY,
++ IN gctFLOAT VConstant,
++ IN gctFLOAT VStepX,
++ IN gctFLOAT VStepY,
++ IN gctBOOL Linear
++ );
++
++gceSTATUS
++gcoVG_SetColorRamp(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF ColorRamp,
++ IN gceTILE_MODE ColorRampSpreadMode
++ );
++
++gceSTATUS
++gcoVG_SetPattern(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctINT32 width,
++ IN gctINT32 height,
++ IN gcoSURF Pattern,
++ IN gceTILE_MODE TileMode,
++ IN gceIMAGE_FILTER Filter
++ );
++
++gceSTATUS
++gcoVG_SetImageMode(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceVG_IMAGE Mode
++ );
++
++gceSTATUS
++gcoVG_SetBlendMode(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_SetRenderingQuality(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceRENDER_QUALITY Quality
++ );
++
++gceSTATUS
++gcoVG_SetFillRule(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gceFILL_RULE FillRule
++ );
++
++gceSTATUS
++gcoVG_FinalizePath(
++ IN gcoVG Vg,
++ IN gcsPATH_DATA_PTR PathData
++ );
++
++gceSTATUS
++gcoVG_Clear(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctINT X,
++ IN gctINT Y,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_DrawPath(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcsPATH_DATA_PTR PathData,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++#if gcdMOVG
++ IN gctUINT32 Width,
++ IN gctUINT32 Height,
++ IN gctFLOAT *Bounds,
++#endif
++ IN gctBOOL SoftwareTesselation
++ );
++
++gceSTATUS
++gcoVG_DrawImage(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height,
++ IN gctBOOL Mask,
++ IN gctBOOL isDrawImage
++ );
++
++gceSTATUS
++gcoVG_TesselateImage(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Image,
++ IN gcsVG_RECT_PTR Rectangle,
++ IN gceIMAGE_FILTER Filter,
++ IN gctBOOL Mask,
++#if gcdMOVG
++ IN gctBOOL SoftwareTesselation,
++ IN gceVG_BLEND BlendMode
++#else
++ IN gctBOOL SoftwareTesselation
++#endif
++ );
++
++gceSTATUS
++gcoVG_Blit(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gcsVG_RECT_PTR SrcRect,
++ IN gcsVG_RECT_PTR TrgRect,
++ IN gceIMAGE_FILTER Filter,
++ IN gceVG_BLEND Mode
++ );
++
++gceSTATUS
++gcoVG_ColorMatrix(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN const gctFLOAT * Matrix,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_SeparableConvolve(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT KernelWidth,
++ IN gctINT KernelHeight,
++ IN gctINT ShiftX,
++ IN gctINT ShiftY,
++ IN const gctINT16 * KernelX,
++ IN const gctINT16 * KernelY,
++ IN gctFLOAT Scale,
++ IN gctFLOAT Bias,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_GaussianBlur(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctFLOAT StdDeviationX,
++ IN gctFLOAT StdDeviationY,
++ IN gceTILE_MODE TilingMode,
++ IN gctFLOAT_PTR FillColor,
++ IN gceCHANNEL ColorChannels,
++ IN gctBOOL FilterLinear,
++ IN gctBOOL FilterPremultiplied,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsPOINT_PTR TargetOrigin,
++ IN gcsSIZE_PTR SourceSize,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++gceSTATUS
++gcoVG_EnableDither(
++ IN gcoVG Vg,
++#if GC355_PROFILER
++ IN gctUINT TreeDepth,
++ IN gctUINT saveLayerTreeDepth,
++ IN gctUINT varTreeDepth,
++#endif
++ IN gctBOOL Enable
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_vg_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h 2016-06-19 22:11:55.237144468 +0200
+@@ -0,0 +1,1608 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_enum_h_
++#define __gc_hal_enum_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/* Chip models. */
++typedef enum _gceCHIPMODEL
++{
++ gcv200 = 0x0200,
++ gcv300 = 0x0300,
++ gcv320 = 0x0320,
++ gcv328 = 0x0328,
++ gcv350 = 0x0350,
++ gcv355 = 0x0355,
++ gcv400 = 0x0400,
++ gcv410 = 0x0410,
++ gcv420 = 0x0420,
++ gcv428 = 0x0428,
++ gcv450 = 0x0450,
++ gcv500 = 0x0500,
++ gcv520 = 0x0520,
++ gcv530 = 0x0530,
++ gcv600 = 0x0600,
++ gcv700 = 0x0700,
++ gcv800 = 0x0800,
++ gcv860 = 0x0860,
++ gcv880 = 0x0880,
++ gcv1000 = 0x1000,
++ gcv1500 = 0x1500,
++ gcv2000 = 0x2000,
++ gcv2100 = 0x2100,
++ gcv2200 = 0x2200,
++ gcv2500 = 0x2500,
++ gcv3000 = 0x3000,
++ gcv4000 = 0x4000,
++ gcv5000 = 0x5000,
++ gcv5200 = 0x5200,
++ gcv6400 = 0x6400,
++}
++gceCHIPMODEL;
++
++/* Chip features. */
++typedef enum _gceFEATURE
++{
++ gcvFEATURE_PIPE_2D = 0,
++ gcvFEATURE_PIPE_3D,
++ gcvFEATURE_PIPE_VG,
++ gcvFEATURE_DC,
++ gcvFEATURE_HIGH_DYNAMIC_RANGE,
++ gcvFEATURE_MODULE_CG,
++ gcvFEATURE_MIN_AREA,
++ gcvFEATURE_BUFFER_INTERLEAVING,
++ gcvFEATURE_BYTE_WRITE_2D,
++ gcvFEATURE_ENDIANNESS_CONFIG,
++ gcvFEATURE_DUAL_RETURN_BUS,
++ gcvFEATURE_DEBUG_MODE,
++ gcvFEATURE_YUY2_RENDER_TARGET,
++ gcvFEATURE_FRAGMENT_PROCESSOR,
++ gcvFEATURE_2DPE20,
++ gcvFEATURE_FAST_CLEAR,
++ gcvFEATURE_YUV420_TILER,
++ gcvFEATURE_YUY2_AVERAGING,
++ gcvFEATURE_FLIP_Y,
++ gcvFEATURE_EARLY_Z,
++ gcvFEATURE_COMPRESSION,
++ gcvFEATURE_MSAA,
++ gcvFEATURE_SPECIAL_ANTI_ALIASING,
++ gcvFEATURE_SPECIAL_MSAA_LOD,
++ gcvFEATURE_422_TEXTURE_COMPRESSION,
++ gcvFEATURE_DXT_TEXTURE_COMPRESSION,
++ gcvFEATURE_ETC1_TEXTURE_COMPRESSION,
++ gcvFEATURE_CORRECT_TEXTURE_CONVERTER,
++ gcvFEATURE_TEXTURE_8K,
++ gcvFEATURE_SCALER,
++ gcvFEATURE_YUV420_SCALER,
++ gcvFEATURE_SHADER_HAS_W,
++ gcvFEATURE_SHADER_HAS_SIGN,
++ gcvFEATURE_SHADER_HAS_FLOOR,
++ gcvFEATURE_SHADER_HAS_CEIL,
++ gcvFEATURE_SHADER_HAS_SQRT,
++ gcvFEATURE_SHADER_HAS_TRIG,
++ gcvFEATURE_VAA,
++ gcvFEATURE_HZ,
++ gcvFEATURE_CORRECT_STENCIL,
++ gcvFEATURE_VG20,
++ gcvFEATURE_VG_FILTER,
++ gcvFEATURE_VG21,
++ gcvFEATURE_VG_DOUBLE_BUFFER,
++ gcvFEATURE_MC20,
++ gcvFEATURE_SUPER_TILED,
++ gcvFEATURE_FAST_CLEAR_FLUSH,
++ gcvFEATURE_2D_FILTERBLIT_PLUS_ALPHABLEND,
++ gcvFEATURE_2D_DITHER,
++ gcvFEATURE_2D_A8_TARGET,
++ gcvFEATURE_2D_A8_NO_ALPHA,
++ gcvFEATURE_2D_FILTERBLIT_FULLROTATION,
++ gcvFEATURE_2D_BITBLIT_FULLROTATION,
++ gcvFEATURE_WIDE_LINE,
++ gcvFEATURE_FC_FLUSH_STALL,
++ gcvFEATURE_FULL_DIRECTFB,
++ gcvFEATURE_HALF_FLOAT_PIPE,
++ gcvFEATURE_LINE_LOOP,
++ gcvFEATURE_2D_YUV_BLIT,
++ gcvFEATURE_2D_TILING,
++ gcvFEATURE_NON_POWER_OF_TWO,
++ gcvFEATURE_3D_TEXTURE,
++ gcvFEATURE_TEXTURE_ARRAY,
++ gcvFEATURE_TILE_FILLER,
++ gcvFEATURE_LOGIC_OP,
++ gcvFEATURE_COMPOSITION,
++ gcvFEATURE_MIXED_STREAMS,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT,
++ gcvFEATURE_END_EVENT,
++ gcvFEATURE_VERTEX_10_10_10_2,
++ gcvFEATURE_TEXTURE_10_10_10_2,
++ gcvFEATURE_TEXTURE_ANISOTROPIC_FILTERING,
++ gcvFEATURE_TEXTURE_FLOAT_HALF_FLOAT,
++ gcvFEATURE_2D_ROTATION_STALL_FIX,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX,
++ gcvFEATURE_BUG_FIXES10,
++ gcvFEATURE_2D_MINOR_TILING,
++ /* Supertiled compressed textures are supported. */
++ gcvFEATURE_TEX_COMPRRESSION_SUPERTILED,
++ gcvFEATURE_FAST_MSAA,
++ gcvFEATURE_BUG_FIXED_INDEXED_TRIANGLE_STRIP,
++ gcvFEATURE_TEXTURE_TILE_STATUS_READ,
++ gcvFEATURE_DEPTH_BIAS_FIX,
++ gcvFEATURE_RECT_PRIMITIVE,
++ gcvFEATURE_BUG_FIXES11,
++ gcvFEATURE_SUPERTILED_TEXTURE,
++ gcvFEATURE_2D_NO_COLORBRUSH_INDEX8,
++ gcvFEATURE_RS_YUV_TARGET,
++ gcvFEATURE_2D_FC_SOURCE,
++ gcvFEATURE_2D_CC_NOAA_SOURCE,
++ gcvFEATURE_PE_DITHER_FIX,
++ gcvFEATURE_2D_YUV_SEPARATE_STRIDE,
++ gcvFEATURE_FRUSTUM_CLIP_FIX,
++ gcvFEATURE_TEXTURE_SWIZZLE,
++ gcvFEATURE_PRIMITIVE_RESTART,
++ gcvFEATURE_TEXTURE_LINEAR,
++ gcvFEATURE_TEXTURE_YUV_ASSEMBLER,
++ gcvFEATURE_LINEAR_RENDER_TARGET,
++ gcvFEATURE_SHADER_HAS_ATOMIC,
++ gcvFEATURE_SHADER_HAS_INSTRUCTION_CACHE,
++ gcvFEATURE_SHADER_ENHANCEMENTS2,
++ gcvFEATURE_BUG_FIXES7,
++ gcvFEATURE_SHADER_HAS_RTNE,
++ gcvFEATURE_SHADER_HAS_EXTRA_INSTRUCTIONS2,
++ gcvFEATURE_SHADER_ENHANCEMENTS3,
++ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING,
++ gcvFEATURE_SINGLE_BUFFER,
++ gcvFEATURE_OCCLUSION_QUERY,
++ gcvFEATURE_2D_GAMMA,
++ gcvFEATURE_2D_COLOR_SPACE_CONVERSION,
++ gcvFEATURE_2D_SUPER_TILE_VERSION,
++ gcvFEATURE_HALTI0,
++ gcvFEATURE_HALTI1,
++ gcvFEATURE_HALTI2,
++ gcvFEATURE_2D_MIRROR_EXTENSION,
++ gcvFEATURE_TEXTURE_ASTC,
++ gcvFEATURE_2D_SUPER_TILE_V1,
++ gcvFEATURE_2D_SUPER_TILE_V2,
++ gcvFEATURE_2D_SUPER_TILE_V3,
++ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX2,
++ gcvFEATURE_NEW_RA,
++ gcvFEATURE_BUG_FIXED_IMPLICIT_PRIMITIVE_RESTART,
++ gcvFEATURE_PE_MULTI_RT_BLEND_ENABLE_CONTROL,
++ gcvFEATURE_SMALL_MSAA, /* An upgraded version of Fast MSAA */
++ gcvFEATURE_VERTEX_INST_ID_AS_ATTRIBUTE,
++ gcvFEATURE_DUAL_16,
++ gcvFEATURE_BRANCH_ON_IMMEDIATE_REG,
++ gcvFEATURE_2D_COMPRESSION,
++ gcvFEATURE_TPC_COMPRESSION,
++ gcvFEATURE_2D_OPF_YUV_OUTPUT,
++ gcvFEATURE_2D_FILTERBLIT_A8_ALPHA,
++ gcvFEATURE_2D_MULTI_SRC_BLT_TO_UNIFIED_DST_RECT,
++ gcvFEATURE_V2_COMPRESSION_Z16_FIX,
++
++ gcvFEATURE_VERTEX_INST_ID_AS_INTEGER,
++ gcvFEATURE_2D_YUV_MODE,
++ gcvFEATURE_ACE,
++ gcvFEATURE_COLOR_COMPRESSION,
++
++ gcvFEATURE_32BPP_COMPONENT_TEXTURE_CHANNEL_SWIZZLE,
++ gcvFEATURE_64BPP_HW_CLEAR_SUPPORT,
++ gcvFEATURE_TX_LERP_PRECISION_FIX,
++ gcvFEATURE_COMPRESSION_V2,
++ gcvFEATURE_MMU,
++ gcvFEATURE_COMPRESSION_V3,
++ gcvFEATURE_TX_DECOMPRESSOR,
++ gcvFEATURE_MRT_TILE_STATUS_BUFFER,
++ gcvFEATURE_COMPRESSION_V1,
++ gcvFEATURE_V1_COMPRESSION_Z16_DECOMPRESS_FIX,
++ gcvFEATURE_RTT,
++ gcvFEATURE_GENERICS,
++ gcvFEATURE_2D_ONE_PASS_FILTER,
++ gcvFEATURE_2D_ONE_PASS_FILTER_TAP,
++ gcvFEATURE_2D_POST_FLIP,
++ gcvFEATURE_2D_PIXEL_ALIGNMENT,
++ gcvFEATURE_CORRECT_AUTO_DISABLE_COUNT,
++ gcvFEATURE_CORRECT_AUTO_DISABLE_COUNT_WIDTH,
++
++ gcvFEATURE_HALTI3,
++ gcvFEATURE_EEZ,
++ gcvFEATURE_INTEGER_PIPE_FIX,
++ gcvFEATURE_PSOUTPUT_MAPPING,
++ gcvFEATURE_8K_RT_FIX,
++ gcvFEATURE_TX_TILE_STATUS_MAPPING,
++ gcvFEATURE_SRGB_RT_SUPPORT,
++ gcvFEATURE_UNIFORM_APERTURE,
++ gcvFEATURE_TEXTURE_16K,
++ gcvFEATURE_PA_FARZCLIPPING_FIX,
++ gcvFEATURE_PE_DITHER_COLORMASK_FIX,
++ gcvFEATURE_ZSCALE_FIX,
++
++ gcvFEATURE_MULTI_PIXELPIPES,
++ gcvFEATURE_PIPE_CL,
++
++ gcvFEATURE_BUG_FIXES18,
++
++ gcvFEATURE_UNIFIED_SAMPLERS,
++ gcvFEATURE_CL_PS_WALKER,
++ gcvFEATURE_NEW_HZ,
++
++ gcvFEATURE_TX_FRAC_PRECISION_6BIT,
++ gcvFEATURE_SH_INSTRUCTION_PREFETCH,
++ gcvFEATURE_PROBE,
++
++ gcvFEATURE_BUG_FIXES8,
++ gcvFEATURE_2D_ALL_QUAD,
++
++ gcvFEATURE_SINGLE_PIPE_HALTI1,
++
++ gcvFEATURE_BLOCK_SIZE_16x16,
++
++ gcvFEATURE_NO_USER_CSC,
++ gcvFEATURE_ANDROID_ONLY,
++ gcvFEATURE_HAS_PRODUCTID,
++
++ gcvFEATURE_V2_MSAA_COMP_FIX,
++
++ gcvFEATURE_S8_ONLY_RENDERING,
++
++ gcvFEATURE_SEPARATE_SRC_DST,
++
++ gcvFEATURE_FE_START_VERTEX_SUPPORT,
++ gcvFEATURE_RS_DEPTHSTENCIL_NATIVE_SUPPORT,
++
++ /* Insert features above this comment only. */
++ gcvFEATURE_COUNT /* Not a feature. */
++}
++gceFEATURE;
++
++/* Chip SWWA. */
++typedef enum _gceSWWA
++{
++ gcvSWWA_601 = 0,
++ gcvSWWA_706,
++ gcvSWWA_1163,
++ gcvSWWA_1165,
++ /* Insert SWWA above this comment only. */
++ gcvSWWA_COUNT /* Not a SWWA. */
++}
++gceSWWA;
++
++
++/* Option Set*/
++typedef enum _gceOPITON
++{
++ /* HW setting we take PREFER */
++ gcvOPTION_PREFER_MULTIPIPE_RS = 0,
++ gcvOPTION_PREFER_ZCONVERT_BYPASS =1,
++
++
++ gcvOPTION_HW_NULL = 50,
++ gcvOPTION_PRINT_OPTION = 51,
++
++ gcvOPTION_FBO_PREFER_MEM = 80,
++
++ /* Insert option above this comment only */
++ gcvOPTION_COUNT /* Not a OPTION*/
++}
++gceOPTION;
++
++typedef enum _gceFRAMEINFO
++{
++ gcvFRAMEINFO_FRAME_NUM = 0,
++ gcvFRAMEINFO_DRAW_NUM = 1,
++ gcvFRAMEINFO_DRAW_DUAL16_NUM = 2,
++ gcvFRAMEINFO_DRAW_FL32_NUM = 3,
++
++
++ gcvFRAMEINFO_COUNT,
++}
++gceFRAMEINFO;
++
++typedef enum _gceFRAMEINFO_OP
++{
++ gcvFRAMEINFO_OP_INC = 0,
++ gcvFRAMEINFO_OP_DEC = 1,
++ gcvFRAMEINFO_OP_ZERO = 2,
++ gcvFRAMEINFO_OP_GET = 3,
++
++
++ gcvFRAMEINFO_OP_COUNT,
++}
++gceFRAMEINFO_OP;
++
++
++/* Chip Power Status. */
++typedef enum _gceCHIPPOWERSTATE
++{
++ gcvPOWER_ON = 0,
++ gcvPOWER_OFF,
++ gcvPOWER_IDLE,
++ gcvPOWER_SUSPEND,
++ gcvPOWER_SUSPEND_ATPOWERON,
++ gcvPOWER_OFF_ATPOWERON,
++ gcvPOWER_IDLE_BROADCAST,
++ gcvPOWER_SUSPEND_BROADCAST,
++ gcvPOWER_OFF_BROADCAST,
++ gcvPOWER_OFF_RECOVERY,
++ gcvPOWER_OFF_TIMEOUT,
++ gcvPOWER_ON_AUTO
++}
++gceCHIPPOWERSTATE;
++
++/* CPU cache operations */
++typedef enum _gceCACHEOPERATION
++{
++ gcvCACHE_CLEAN = 0x01,
++ gcvCACHE_INVALIDATE = 0x02,
++ gcvCACHE_FLUSH = gcvCACHE_CLEAN | gcvCACHE_INVALIDATE,
++ gcvCACHE_MEMORY_BARRIER = 0x04
++}
++gceCACHEOPERATION;
++
++/* Surface types. */
++typedef enum _gceSURF_TYPE
++{
++ gcvSURF_TYPE_UNKNOWN = 0,
++ gcvSURF_INDEX,
++ gcvSURF_VERTEX,
++ gcvSURF_TEXTURE,
++ gcvSURF_RENDER_TARGET,
++ gcvSURF_DEPTH,
++ gcvSURF_BITMAP,
++ gcvSURF_TILE_STATUS,
++ gcvSURF_IMAGE,
++ gcvSURF_MASK,
++ gcvSURF_SCISSOR,
++ gcvSURF_HIERARCHICAL_DEPTH,
++ gcvSURF_NUM_TYPES, /* Make sure this is the last one! */
++
++ /* Combinations. */
++ gcvSURF_NO_TILE_STATUS = 0x100,
++ gcvSURF_NO_VIDMEM = 0x200, /* Used to allocate surfaces with no underlying vidmem node.
++ In Android, vidmem node is allocated by another process. */
++ gcvSURF_CACHEABLE = 0x400, /* Used to allocate a cacheable surface */
++
++ gcvSURF_FLIP = 0x800, /* The Resolve Target the will been flip resolve from RT */
++
++ gcvSURF_TILE_STATUS_DIRTY = 0x1000, /* Init tile status to all dirty */
++
++ gcvSURF_LINEAR = 0x2000,
++
++ gcvSURF_CREATE_AS_TEXTURE = 0x4000, /* create it as a texture */
++
++ gcvSURF_PROTECTED_CONTENT = 0x8000, /* create it as content protected */
++
++ /* Create it as no compression, valid on when it has tile status. */
++ gcvSURF_NO_COMPRESSION = 0x40000,
++
++ gcvSURF_CONTIGUOUS = 0x20000, /*create it as contiguous */
++
++ gcvSURF_TEXTURE_LINEAR = gcvSURF_TEXTURE
++ | gcvSURF_LINEAR,
++
++ gcvSURF_RENDER_TARGET_LINEAR = gcvSURF_RENDER_TARGET
++ | gcvSURF_LINEAR,
++
++ gcvSURF_RENDER_TARGET_NO_TILE_STATUS = gcvSURF_RENDER_TARGET
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_RENDER_TARGET_TS_DIRTY = gcvSURF_RENDER_TARGET
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ gcvSURF_DEPTH_NO_TILE_STATUS = gcvSURF_DEPTH
++ | gcvSURF_NO_TILE_STATUS,
++
++ gcvSURF_DEPTH_TS_DIRTY = gcvSURF_DEPTH
++ | gcvSURF_TILE_STATUS_DIRTY,
++
++ /* Supported surface types with no vidmem node. */
++ gcvSURF_BITMAP_NO_VIDMEM = gcvSURF_BITMAP
++ | gcvSURF_NO_VIDMEM,
++
++ gcvSURF_TEXTURE_NO_VIDMEM = gcvSURF_TEXTURE
++ | gcvSURF_NO_VIDMEM,
++
++ /* Cacheable surface types with no vidmem node. */
++ gcvSURF_CACHEABLE_BITMAP_NO_VIDMEM = gcvSURF_BITMAP_NO_VIDMEM
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_CACHEABLE_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_CACHEABLE,
++
++ gcvSURF_FLIP_BITMAP = gcvSURF_BITMAP
++ | gcvSURF_FLIP,
++}
++gceSURF_TYPE;
++
++typedef enum _gceSURF_USAGE
++{
++ gcvSURF_USAGE_UNKNOWN,
++ gcvSURF_USAGE_RESOLVE_AFTER_CPU,
++ gcvSURF_USAGE_RESOLVE_AFTER_3D
++}
++gceSURF_USAGE;
++
++typedef enum _gceSURF_COLOR_SPACE
++{
++ gcvSURF_COLOR_SPACE_UNKNOWN,
++ gcvSURF_COLOR_SPACE_LINEAR,
++ gcvSURF_COLOR_SPACE_NONLINEAR,
++}
++gceSURF_COLOR_SPACE;
++
++typedef enum _gceSURF_COLOR_TYPE
++{
++ gcvSURF_COLOR_UNKNOWN = 0,
++ gcvSURF_COLOR_LINEAR = 0x01,
++ gcvSURF_COLOR_ALPHA_PRE = 0x02,
++}
++gceSURF_COLOR_TYPE;
++
++/* Rotation. */
++typedef enum _gceSURF_ROTATION
++{
++ gcvSURF_0_DEGREE = 0,
++ gcvSURF_90_DEGREE,
++ gcvSURF_180_DEGREE,
++ gcvSURF_270_DEGREE,
++ gcvSURF_FLIP_X,
++ gcvSURF_FLIP_Y,
++
++ gcvSURF_POST_FLIP_X = 0x40000000,
++ gcvSURF_POST_FLIP_Y = 0x80000000,
++}
++gceSURF_ROTATION;
++
++/* Surface flag */
++typedef enum _gceSURF_FLAG
++{
++ /* None flag */
++ gcvSURF_FLAG_NONE = 0x0,
++ /* content is preserved after swap */
++ gcvSURF_FLAG_CONTENT_PRESERVED = 0x1,
++ /* content is updated after swap*/
++ gcvSURF_FLAG_CONTENT_UPDATED = 0x2,
++ /* content is y inverted */
++ gcvSURF_FLAG_CONTENT_YINVERTED = 0x4,
++ /* content is protected */
++ gcvSURF_FLAG_CONTENT_PROTECTED = 0x8,
++ /* surface is contiguous. */
++ gcvSURF_FLAG_CONTIGUOUS = (1 << 4),
++}
++gceSURF_FLAG;
++
++typedef enum _gceMIPMAP_IMAGE_FORMAT
++{
++ gcvUNKNOWN_MIPMAP_IMAGE_FORMAT = -2
++}
++gceMIPMAP_IMAGE_FORMAT;
++
++/* Surface formats. */
++typedef enum _gceSURF_FORMAT
++{
++ /* Unknown format. */
++ gcvSURF_UNKNOWN = 0,
++
++ /* Palettized formats. */
++ gcvSURF_INDEX1 = 100,
++ gcvSURF_INDEX4,
++ gcvSURF_INDEX8,
++
++ /* RGB formats. */
++ gcvSURF_A2R2G2B2 = 200,
++ gcvSURF_R3G3B2,
++ gcvSURF_A8R3G3B2,
++ gcvSURF_X4R4G4B4,
++ gcvSURF_A4R4G4B4,
++ gcvSURF_R4G4B4A4,
++ gcvSURF_X1R5G5B5,
++ gcvSURF_A1R5G5B5,
++ gcvSURF_R5G5B5A1,
++ gcvSURF_R5G6B5,
++ gcvSURF_R8G8B8,
++ gcvSURF_X8R8G8B8,
++ gcvSURF_A8R8G8B8,
++ gcvSURF_R8G8B8A8,
++ gcvSURF_G8R8G8B8,
++ gcvSURF_R8G8B8G8,
++ gcvSURF_X2R10G10B10,
++ gcvSURF_A2R10G10B10,
++ gcvSURF_X12R12G12B12,
++ gcvSURF_A12R12G12B12,
++ gcvSURF_X16R16G16B16,
++ gcvSURF_A16R16G16B16,
++ gcvSURF_A32R32G32B32,
++ gcvSURF_R8G8B8X8,
++ gcvSURF_R5G5B5X1,
++ gcvSURF_R4G4B4X4,
++ gcvSURF_X16R16G16B16_2_A8R8G8B8,
++ gcvSURF_A16R16G16B16_2_A8R8G8B8,
++ gcvSURF_A32R32G32B32_2_G32R32F,
++ gcvSURF_A32R32G32B32_4_A8R8G8B8,
++
++ /* BGR formats. */
++ gcvSURF_A4B4G4R4 = 300,
++ gcvSURF_A1B5G5R5,
++ gcvSURF_B5G6R5,
++ gcvSURF_B8G8R8,
++ gcvSURF_B16G16R16,
++ gcvSURF_X8B8G8R8,
++ gcvSURF_A8B8G8R8,
++ gcvSURF_A2B10G10R10,
++ gcvSURF_X16B16G16R16,
++ gcvSURF_A16B16G16R16,
++ gcvSURF_B32G32R32,
++ gcvSURF_X32B32G32R32,
++ gcvSURF_A32B32G32R32,
++ gcvSURF_B4G4R4A4,
++ gcvSURF_B5G5R5A1,
++ gcvSURF_B8G8R8X8,
++ gcvSURF_B8G8R8A8,
++ gcvSURF_X4B4G4R4,
++ gcvSURF_X1B5G5R5,
++ gcvSURF_B4G4R4X4,
++ gcvSURF_B5G5R5X1,
++ gcvSURF_X2B10G10R10,
++ gcvSURF_B8G8R8_SNORM,
++ gcvSURF_X8B8G8R8_SNORM,
++ gcvSURF_A8B8G8R8_SNORM,
++ gcvSURF_A8B12G12R12_2_A8R8G8B8,
++
++ /* Compressed formats. */
++ gcvSURF_DXT1 = 400,
++ gcvSURF_DXT2,
++ gcvSURF_DXT3,
++ gcvSURF_DXT4,
++ gcvSURF_DXT5,
++ gcvSURF_CXV8U8,
++ gcvSURF_ETC1,
++ gcvSURF_R11_EAC,
++ gcvSURF_SIGNED_R11_EAC,
++ gcvSURF_RG11_EAC,
++ gcvSURF_SIGNED_RG11_EAC,
++ gcvSURF_RGB8_ETC2,
++ gcvSURF_SRGB8_ETC2,
++ gcvSURF_RGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2,
++ gcvSURF_RGBA8_ETC2_EAC,
++ gcvSURF_SRGB8_ALPHA8_ETC2_EAC,
++
++ /* YUV formats. */
++ gcvSURF_YUY2 = 500,
++ gcvSURF_UYVY,
++ gcvSURF_YV12,
++ gcvSURF_I420,
++ gcvSURF_NV12,
++ gcvSURF_NV21,
++ gcvSURF_NV16,
++ gcvSURF_NV61,
++ gcvSURF_YVYU,
++ gcvSURF_VYUY,
++
++ /* Depth formats. */
++ gcvSURF_D16 = 600,
++ gcvSURF_D24S8,
++ gcvSURF_D32,
++ gcvSURF_D24X8,
++ gcvSURF_D32F,
++ gcvSURF_S8D32F,
++ gcvSURF_S8D32F_1_G32R32F,
++ gcvSURF_S8D32F_2_A8R8G8B8,
++ gcvSURF_D24S8_1_A8R8G8B8,
++ gcvSURF_S8,
++
++ /* Alpha formats. */
++ gcvSURF_A4 = 700,
++ gcvSURF_A8,
++ gcvSURF_A12,
++ gcvSURF_A16,
++ gcvSURF_A32,
++ gcvSURF_A1,
++
++ /* Luminance formats. */
++ gcvSURF_L4 = 800,
++ gcvSURF_L8,
++ gcvSURF_L12,
++ gcvSURF_L16,
++ gcvSURF_L32,
++ gcvSURF_L1,
++
++ /* Alpha/Luminance formats. */
++ gcvSURF_A4L4 = 900,
++ gcvSURF_A2L6,
++ gcvSURF_A8L8,
++ gcvSURF_A4L12,
++ gcvSURF_A12L12,
++ gcvSURF_A16L16,
++
++ /* Bump formats. */
++ gcvSURF_L6V5U5 = 1000,
++ gcvSURF_V8U8,
++ gcvSURF_X8L8V8U8,
++ gcvSURF_Q8W8V8U8,
++ gcvSURF_A2W10V10U10,
++ gcvSURF_V16U16,
++ gcvSURF_Q16W16V16U16,
++
++ /* R/RG/RA formats. */
++ gcvSURF_R8 = 1100,
++ gcvSURF_X8R8,
++ gcvSURF_G8R8,
++ gcvSURF_X8G8R8,
++ gcvSURF_A8R8,
++ gcvSURF_R16,
++ gcvSURF_X16R16,
++ gcvSURF_G16R16,
++ gcvSURF_X16G16R16,
++ gcvSURF_A16R16,
++ gcvSURF_R32,
++ gcvSURF_X32R32,
++ gcvSURF_G32R32,
++ gcvSURF_X32G32R32,
++ gcvSURF_A32R32,
++ gcvSURF_RG16,
++ gcvSURF_R8_SNORM,
++ gcvSURF_G8R8_SNORM,
++
++ gcvSURF_R8_1_X8R8G8B8,
++ gcvSURF_G8R8_1_X8R8G8B8,
++
++ /* Floating point formats. */
++ gcvSURF_R16F = 1200,
++ gcvSURF_X16R16F,
++ gcvSURF_G16R16F,
++ gcvSURF_X16G16R16F,
++ gcvSURF_B16G16R16F,
++ gcvSURF_X16B16G16R16F,
++ gcvSURF_A16B16G16R16F,
++ gcvSURF_R32F,
++ gcvSURF_X32R32F,
++ gcvSURF_G32R32F,
++ gcvSURF_X32G32R32F,
++ gcvSURF_B32G32R32F,
++ gcvSURF_X32B32G32R32F,
++ gcvSURF_A32B32G32R32F,
++ gcvSURF_A16F,
++ gcvSURF_L16F,
++ gcvSURF_A16L16F,
++ gcvSURF_A16R16F,
++ gcvSURF_A32F,
++ gcvSURF_L32F,
++ gcvSURF_A32L32F,
++ gcvSURF_A32R32F,
++ gcvSURF_E5B9G9R9,
++ gcvSURF_B10G11R11F,
++
++ gcvSURF_X16B16G16R16F_2_A8R8G8B8,
++ gcvSURF_A16B16G16R16F_2_A8R8G8B8,
++ gcvSURF_G32R32F_2_A8R8G8B8,
++ gcvSURF_X32B32G32R32F_2_G32R32F,
++ gcvSURF_A32B32G32R32F_2_G32R32F,
++ gcvSURF_X32B32G32R32F_4_A8R8G8B8,
++ gcvSURF_A32B32G32R32F_4_A8R8G8B8,
++
++ gcvSURF_R16F_1_A4R4G4B4,
++ gcvSURF_G16R16F_1_A8R8G8B8,
++ gcvSURF_B16G16R16F_2_A8R8G8B8,
++
++ gcvSURF_R32F_1_A8R8G8B8,
++ gcvSURF_B32G32R32F_3_A8R8G8B8,
++
++ gcvSURF_B10G11R11F_1_A8R8G8B8,
++
++
++ /* sRGB format. */
++ gcvSURF_SBGR8 = 1400,
++ gcvSURF_A8_SBGR8,
++ gcvSURF_X8_SBGR8,
++
++ /* Integer formats. */
++ gcvSURF_R8I = 1500,
++ gcvSURF_R8UI,
++ gcvSURF_R16I,
++ gcvSURF_R16UI,
++ gcvSURF_R32I,
++ gcvSURF_R32UI,
++ gcvSURF_X8R8I,
++ gcvSURF_G8R8I,
++ gcvSURF_X8R8UI,
++ gcvSURF_G8R8UI,
++ gcvSURF_X16R16I,
++ gcvSURF_G16R16I,
++ gcvSURF_X16R16UI,
++ gcvSURF_G16R16UI,
++ gcvSURF_X32R32I,
++ gcvSURF_G32R32I,
++ gcvSURF_X32R32UI,
++ gcvSURF_G32R32UI,
++ gcvSURF_X8G8R8I,
++ gcvSURF_B8G8R8I,
++ gcvSURF_X8G8R8UI,
++ gcvSURF_B8G8R8UI,
++ gcvSURF_X16G16R16I,
++ gcvSURF_B16G16R16I,
++ gcvSURF_X16G16R16UI,
++ gcvSURF_B16G16R16UI,
++ gcvSURF_X32G32R32I,
++ gcvSURF_B32G32R32I,
++ gcvSURF_X32G32R32UI,
++ gcvSURF_B32G32R32UI,
++ gcvSURF_X8B8G8R8I,
++ gcvSURF_A8B8G8R8I,
++ gcvSURF_X8B8G8R8UI,
++ gcvSURF_A8B8G8R8UI,
++ gcvSURF_X16B16G16R16I,
++ gcvSURF_A16B16G16R16I,
++ gcvSURF_X16B16G16R16UI,
++ gcvSURF_A16B16G16R16UI,
++ gcvSURF_X32B32G32R32I,
++ gcvSURF_A32B32G32R32I,
++ gcvSURF_X32B32G32R32UI,
++ gcvSURF_A32B32G32R32UI,
++ gcvSURF_A2B10G10R10UI,
++ gcvSURF_G32R32I_2_A8R8G8B8,
++ gcvSURF_G32R32UI_2_A8R8G8B8,
++ gcvSURF_X16B16G16R16I_2_A8R8G8B8,
++ gcvSURF_A16B16G16R16I_2_A8R8G8B8,
++ gcvSURF_X16B16G16R16UI_2_A8R8G8B8,
++ gcvSURF_A16B16G16R16UI_2_A8R8G8B8,
++ gcvSURF_X32B32G32R32I_2_G32R32I,
++ gcvSURF_A32B32G32R32I_2_G32R32I,
++ gcvSURF_X32B32G32R32I_3_A8R8G8B8,
++ gcvSURF_A32B32G32R32I_4_A8R8G8B8,
++ gcvSURF_X32B32G32R32UI_2_G32R32UI,
++ gcvSURF_A32B32G32R32UI_2_G32R32UI,
++ gcvSURF_X32B32G32R32UI_3_A8R8G8B8,
++ gcvSURF_A32B32G32R32UI_4_A8R8G8B8,
++ gcvSURF_A2B10G10R10UI_1_A8R8G8B8,
++ gcvSURF_A8B8G8R8I_1_A8R8G8B8,
++ gcvSURF_A8B8G8R8UI_1_A8R8G8B8,
++ gcvSURF_R8I_1_A4R4G4B4,
++ gcvSURF_R8UI_1_A4R4G4B4,
++ gcvSURF_R16I_1_A4R4G4B4,
++ gcvSURF_R16UI_1_A4R4G4B4,
++ gcvSURF_R32I_1_A8R8G8B8,
++ gcvSURF_R32UI_1_A8R8G8B8,
++ gcvSURF_X8R8I_1_A4R4G4B4,
++ gcvSURF_X8R8UI_1_A4R4G4B4,
++ gcvSURF_G8R8I_1_A4R4G4B4,
++ gcvSURF_G8R8UI_1_A4R4G4B4,
++ gcvSURF_X16R16I_1_A4R4G4B4,
++ gcvSURF_X16R16UI_1_A4R4G4B4,
++ gcvSURF_G16R16I_1_A8R8G8B8,
++ gcvSURF_G16R16UI_1_A8R8G8B8,
++ gcvSURF_X32R32I_1_A8R8G8B8,
++ gcvSURF_X32R32UI_1_A8R8G8B8,
++ gcvSURF_X8G8R8I_1_A4R4G4B4,
++ gcvSURF_X8G8R8UI_1_A4R4G4B4,
++ gcvSURF_B8G8R8I_1_A8R8G8B8,
++ gcvSURF_B8G8R8UI_1_A8R8G8B8,
++ gcvSURF_B16G16R16I_2_A8R8G8B8,
++ gcvSURF_B16G16R16UI_2_A8R8G8B8,
++ gcvSURF_B32G32R32I_3_A8R8G8B8,
++ gcvSURF_B32G32R32UI_3_A8R8G8B8,
++
++ /* ASTC formats. */
++ gcvSURF_ASTC4x4 = 1600,
++ gcvSURF_ASTC5x4,
++ gcvSURF_ASTC5x5,
++ gcvSURF_ASTC6x5,
++ gcvSURF_ASTC6x6,
++ gcvSURF_ASTC8x5,
++ gcvSURF_ASTC8x6,
++ gcvSURF_ASTC8x8,
++ gcvSURF_ASTC10x5,
++ gcvSURF_ASTC10x6,
++ gcvSURF_ASTC10x8,
++ gcvSURF_ASTC10x10,
++ gcvSURF_ASTC12x10,
++ gcvSURF_ASTC12x12,
++ gcvSURF_ASTC4x4_SRGB,
++ gcvSURF_ASTC5x4_SRGB,
++ gcvSURF_ASTC5x5_SRGB,
++ gcvSURF_ASTC6x5_SRGB,
++ gcvSURF_ASTC6x6_SRGB,
++ gcvSURF_ASTC8x5_SRGB,
++ gcvSURF_ASTC8x6_SRGB,
++ gcvSURF_ASTC8x8_SRGB,
++ gcvSURF_ASTC10x5_SRGB,
++ gcvSURF_ASTC10x6_SRGB,
++ gcvSURF_ASTC10x8_SRGB,
++ gcvSURF_ASTC10x10_SRGB,
++ gcvSURF_ASTC12x10_SRGB,
++ gcvSURF_ASTC12x12_SRGB,
++
++ gcvSURF_FORMAT_COUNT
++}
++gceSURF_FORMAT;
++
++/* Format modifiers. */
++typedef enum _gceSURF_FORMAT_MODE
++{
++ gcvSURF_FORMAT_OCL = 0x80000000
++}
++gceSURF_FORMAT_MODE;
++
++/* Pixel swizzle modes. */
++typedef enum _gceSURF_SWIZZLE
++{
++ gcvSURF_NOSWIZZLE = 0,
++ gcvSURF_ARGB,
++ gcvSURF_ABGR,
++ gcvSURF_RGBA,
++ gcvSURF_BGRA
++}
++gceSURF_SWIZZLE;
++
++/* Transparency modes. */
++typedef enum _gceSURF_TRANSPARENCY
++{
++ /* Valid only for PE 1.0 */
++ gcvSURF_OPAQUE = 0,
++ gcvSURF_SOURCE_MATCH,
++ gcvSURF_SOURCE_MASK,
++ gcvSURF_PATTERN_MASK,
++}
++gceSURF_TRANSPARENCY;
++
++/* Surface Alignment. */
++typedef enum _gceSURF_ALIGNMENT
++{
++ gcvSURF_FOUR = 0,
++ gcvSURF_SIXTEEN,
++ gcvSURF_SUPER_TILED,
++ gcvSURF_SPLIT_TILED,
++ gcvSURF_SPLIT_SUPER_TILED
++}
++gceSURF_ALIGNMENT;
++
++/* Surface Addressing. */
++typedef enum _gceSURF_ADDRESSING
++{
++ gcvSURF_NO_STRIDE_TILED = 0,
++ gcvSURF_NO_STRIDE_LINEAR,
++ gcvSURF_STRIDE_TILED,
++ gcvSURF_STRIDE_LINEAR
++}
++gceSURF_ADDRESSING;
++
++/* Transparency modes. */
++typedef enum _gce2D_TRANSPARENCY
++{
++ /* Valid only for PE 2.0 */
++ gcv2D_OPAQUE = 0,
++ gcv2D_KEYED,
++ gcv2D_MASKED
++}
++gce2D_TRANSPARENCY;
++
++/* Mono packing modes. */
++typedef enum _gceSURF_MONOPACK
++{
++ gcvSURF_PACKED8 = 0,
++ gcvSURF_PACKED16,
++ gcvSURF_PACKED32,
++ gcvSURF_UNPACKED,
++}
++gceSURF_MONOPACK;
++
++/* Blending modes. */
++typedef enum _gceSURF_BLEND_MODE
++{
++ /* Porter-Duff blending modes. */
++ /* Fsrc Fdst */
++ gcvBLEND_CLEAR = 0, /* 0 0 */
++ gcvBLEND_SRC, /* 1 0 */
++ gcvBLEND_DST, /* 0 1 */
++ gcvBLEND_SRC_OVER_DST, /* 1 1 - Asrc */
++ gcvBLEND_DST_OVER_SRC, /* 1 - Adst 1 */
++ gcvBLEND_SRC_IN_DST, /* Adst 0 */
++ gcvBLEND_DST_IN_SRC, /* 0 Asrc */
++ gcvBLEND_SRC_OUT_DST, /* 1 - Adst 0 */
++ gcvBLEND_DST_OUT_SRC, /* 0 1 - Asrc */
++ gcvBLEND_SRC_ATOP_DST, /* Adst 1 - Asrc */
++ gcvBLEND_DST_ATOP_SRC, /* 1 - Adst Asrc */
++ gcvBLEND_SRC_XOR_DST, /* 1 - Adst 1 - Asrc */
++
++ /* Special blending modes. */
++ gcvBLEND_SET, /* DST = 1 */
++ gcvBLEND_SUB /* DST = DST * (1 - SRC) */
++}
++gceSURF_BLEND_MODE;
++
++/* Per-pixel alpha modes. */
++typedef enum _gceSURF_PIXEL_ALPHA_MODE
++{
++ gcvSURF_PIXEL_ALPHA_STRAIGHT = 0,
++ gcvSURF_PIXEL_ALPHA_INVERSED
++}
++gceSURF_PIXEL_ALPHA_MODE;
++
++/* Global alpha modes. */
++typedef enum _gceSURF_GLOBAL_ALPHA_MODE
++{
++ gcvSURF_GLOBAL_ALPHA_OFF = 0,
++ gcvSURF_GLOBAL_ALPHA_ON,
++ gcvSURF_GLOBAL_ALPHA_SCALE
++}
++gceSURF_GLOBAL_ALPHA_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gceSURF_PIXEL_COLOR_MODE
++{
++ gcvSURF_COLOR_STRAIGHT = 0,
++ gcvSURF_COLOR_MULTIPLY
++}
++gceSURF_PIXEL_COLOR_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_PIXEL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_COLOR_MULTIPLY_ENABLE
++}
++gce2D_PIXEL_COLOR_MULTIPLY_MODE;
++
++/* Color component modes for alpha blending. */
++typedef enum _gce2D_GLOBAL_COLOR_MULTIPLY_MODE
++{
++ gcv2D_GLOBAL_COLOR_MULTIPLY_DISABLE = 0,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_ALPHA,
++ gcv2D_GLOBAL_COLOR_MULTIPLY_COLOR
++}
++gce2D_GLOBAL_COLOR_MULTIPLY_MODE;
++
++/* Alpha blending factor modes. */
++typedef enum _gceSURF_BLEND_FACTOR_MODE
++{
++ gcvSURF_BLEND_ZERO = 0,
++ gcvSURF_BLEND_ONE,
++ gcvSURF_BLEND_STRAIGHT,
++ gcvSURF_BLEND_INVERSED,
++ gcvSURF_BLEND_COLOR,
++ gcvSURF_BLEND_COLOR_INVERSED,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED,
++ gcvSURF_BLEND_STRAIGHT_NO_CROSS,
++ gcvSURF_BLEND_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_COLOR_NO_CROSS,
++ gcvSURF_BLEND_COLOR_INVERSED_NO_CROSS,
++ gcvSURF_BLEND_SRC_ALPHA_SATURATED_CROSS
++}
++gceSURF_BLEND_FACTOR_MODE;
++
++/* Alpha blending porter duff rules. */
++typedef enum _gce2D_PORTER_DUFF_RULE
++{
++ gcvPD_CLEAR = 0,
++ gcvPD_SRC,
++ gcvPD_SRC_OVER,
++ gcvPD_DST_OVER,
++ gcvPD_SRC_IN,
++ gcvPD_DST_IN,
++ gcvPD_SRC_OUT,
++ gcvPD_DST_OUT,
++ gcvPD_SRC_ATOP,
++ gcvPD_DST_ATOP,
++ gcvPD_ADD,
++ gcvPD_XOR,
++ gcvPD_DST
++}
++gce2D_PORTER_DUFF_RULE;
++
++/* Alpha blending factor modes. */
++typedef enum _gce2D_YUV_COLOR_MODE
++{
++ gcv2D_YUV_601= 0,
++ gcv2D_YUV_709,
++ gcv2D_YUV_USER_DEFINED,
++ gcv2D_YUV_USER_DEFINED_CLAMP,
++
++ /* Default setting is for src. gcv2D_YUV_DST
++ can be ORed to set dst.
++ */
++ gcv2D_YUV_DST = 0x80000000,
++}
++gce2D_YUV_COLOR_MODE;
++
++typedef enum _gce2D_COMMAND
++{
++ gcv2D_CLEAR = 0,
++ gcv2D_LINE,
++ gcv2D_BLT,
++ gcv2D_STRETCH,
++ gcv2D_HOR_FILTER,
++ gcv2D_VER_FILTER,
++ gcv2D_MULTI_SOURCE_BLT,
++ gcv2D_FILTER_BLT,
++}
++gce2D_COMMAND;
++
++typedef enum _gce2D_TILE_STATUS_CONFIG
++{
++ gcv2D_TSC_DISABLE = 0,
++ gcv2D_TSC_ENABLE = 0x00000001,
++ gcv2D_TSC_COMPRESSED = 0x00000002,
++ gcv2D_TSC_DOWN_SAMPLER = 0x00000004,
++ gcv2D_TSC_2D_COMPRESSED = 0x00000008,
++ gcv2D_TSC_TPC_COMPRESSED = 0x00000010,
++}
++gce2D_TILE_STATUS_CONFIG;
++
++typedef enum _gce2D_QUERY
++{
++ gcv2D_QUERY_RGB_ADDRESS_MIN_ALIGN = 0,
++ gcv2D_QUERY_RGB_STRIDE_MIN_ALIGN,
++ gcv2D_QUERY_YUV_ADDRESS_MIN_ALIGN,
++ gcv2D_QUERY_YUV_STRIDE_MIN_ALIGN,
++}
++gce2D_QUERY;
++
++typedef enum _gce2D_SUPER_TILE_VERSION
++{
++ gcv2D_SUPER_TILE_VERSION_V1 = 1,
++ gcv2D_SUPER_TILE_VERSION_V2 = 2,
++ gcv2D_SUPER_TILE_VERSION_V3 = 3,
++}
++gce2D_SUPER_TILE_VERSION;
++
++typedef enum _gce2D_STATE
++{
++ gcv2D_STATE_SPECIAL_FILTER_MIRROR_MODE = 1,
++ gcv2D_STATE_SUPER_TILE_VERSION,
++ gcv2D_STATE_EN_GAMMA,
++ gcv2D_STATE_DE_GAMMA,
++ gcv2D_STATE_MULTI_SRC_BLIT_UNIFIED_DST_RECT,
++ gcv2D_STATE_PROFILE_ENABLE,
++ gcv2D_STATE_XRGB_ENABLE,
++
++ gcv2D_STATE_ARRAY_EN_GAMMA = 0x10001,
++ gcv2D_STATE_ARRAY_DE_GAMMA,
++ gcv2D_STATE_ARRAY_CSC_YUV_TO_RGB,
++ gcv2D_STATE_ARRAY_CSC_RGB_TO_YUV,
++}
++gce2D_STATE;
++
++typedef enum _gce2D_STATE_PROFILE
++{
++ gcv2D_STATE_PROFILE_NONE = 0x0,
++ gcv2D_STATE_PROFILE_COMMAND = 0x1,
++ gcv2D_STATE_PROFILE_SURFACE = 0x2,
++ gcv2D_STATE_PROFILE_ALL = 0xFFFF,
++}
++gce2D_STATE_PROFILE;
++
++/* Texture object types */
++typedef enum _gceTEXTURE_TYPE
++{
++ gcvTEXTURE_UNKNOWN = 0,
++ gcvTEXTURE_1D,
++ gcvTEXTURE_2D,
++ gcvTEXTURE_3D,
++ gcvTEXTURE_CUBEMAP,
++ gcvTEXTURE_1D_ARRAY,
++ gcvTEXTURE_2D_ARRAY,
++ gcvTEXTURE_EXTERNAL
++}
++gceTEXTURE_TYPE;
++
++#if gcdENABLE_3D
++/* Texture functions. */
++typedef enum _gceTEXTURE_FUNCTION
++{
++ gcvTEXTURE_DUMMY = 0,
++ gcvTEXTURE_REPLACE = 0,
++ gcvTEXTURE_MODULATE,
++ gcvTEXTURE_ADD,
++ gcvTEXTURE_ADD_SIGNED,
++ gcvTEXTURE_INTERPOLATE,
++ gcvTEXTURE_SUBTRACT,
++ gcvTEXTURE_DOT3
++}
++gceTEXTURE_FUNCTION;
++
++/* Texture sources. */
++typedef enum _gceTEXTURE_SOURCE
++{
++ gcvCOLOR_FROM_TEXTURE = 0,
++ gcvCOLOR_FROM_CONSTANT_COLOR,
++ gcvCOLOR_FROM_PRIMARY_COLOR,
++ gcvCOLOR_FROM_PREVIOUS_COLOR
++}
++gceTEXTURE_SOURCE;
++
++/* Texture source channels. */
++typedef enum _gceTEXTURE_CHANNEL
++{
++ gcvFROM_COLOR = 0,
++ gcvFROM_ONE_MINUS_COLOR,
++ gcvFROM_ALPHA,
++ gcvFROM_ONE_MINUS_ALPHA
++}
++gceTEXTURE_CHANNEL;
++#endif /* gcdENABLE_3D */
++
++/* Filter types. */
++typedef enum _gceFILTER_TYPE
++{
++ gcvFILTER_SYNC = 0,
++ gcvFILTER_BLUR,
++ gcvFILTER_USER
++}
++gceFILTER_TYPE;
++
++/* Filter pass types. */
++typedef enum _gceFILTER_PASS_TYPE
++{
++ gcvFILTER_HOR_PASS = 0,
++ gcvFILTER_VER_PASS
++}
++gceFILTER_PASS_TYPE;
++
++/* Endian hints. */
++typedef enum _gceENDIAN_HINT
++{
++ gcvENDIAN_NO_SWAP = 0,
++ gcvENDIAN_SWAP_WORD,
++ gcvENDIAN_SWAP_DWORD
++}
++gceENDIAN_HINT;
++
++/* Tiling modes. */
++typedef enum _gceTILING
++{
++ gcvINVALIDTILED = 0x0, /* Invalid tiling */
++ /* Tiling basic modes enum'ed in power of 2. */
++ gcvLINEAR = 0x1, /* No tiling. */
++ gcvTILED = 0x2, /* 4x4 tiling. */
++ gcvSUPERTILED = 0x4, /* 64x64 tiling. */
++ gcvMINORTILED = 0x8, /* 2x2 tiling. */
++
++ /* Tiling special layouts. */
++ gcvTILING_SPLIT_BUFFER = 0x100,
++
++ /* Tiling combination layouts. */
++ gcvMULTI_TILED = gcvTILED
++ | gcvTILING_SPLIT_BUFFER,
++
++ gcvMULTI_SUPERTILED = gcvSUPERTILED
++ | gcvTILING_SPLIT_BUFFER,
++}
++gceTILING;
++
++/* 2D pattern type. */
++typedef enum _gce2D_PATTERN
++{
++ gcv2D_PATTERN_SOLID = 0,
++ gcv2D_PATTERN_MONO,
++ gcv2D_PATTERN_COLOR,
++ gcv2D_PATTERN_INVALID
++}
++gce2D_PATTERN;
++
++/* 2D source type. */
++typedef enum _gce2D_SOURCE
++{
++ gcv2D_SOURCE_MASKED = 0,
++ gcv2D_SOURCE_MONO,
++ gcv2D_SOURCE_COLOR,
++ gcv2D_SOURCE_INVALID
++}
++gce2D_SOURCE;
++
++/* Pipes. */
++typedef enum _gcePIPE_SELECT
++{
++ gcvPIPE_INVALID = ~0,
++ gcvPIPE_3D = 0,
++ gcvPIPE_2D
++}
++gcePIPE_SELECT;
++
++/* Hardware type. */
++typedef enum _gceHARDWARE_TYPE
++{
++ gcvHARDWARE_INVALID = 0x00,
++ gcvHARDWARE_3D = 0x01,
++ gcvHARDWARE_2D = 0x02,
++ gcvHARDWARE_VG = 0x04,
++#if gcdMULTI_GPU_AFFINITY
++ gcvHARDWARE_OCL = 0x05,
++#endif
++ gcvHARDWARE_3D2D = gcvHARDWARE_3D | gcvHARDWARE_2D
++}
++gceHARDWARE_TYPE;
++
++#define gcdCHIP_COUNT 3
++
++typedef enum _gceMMU_MODE
++{
++ gcvMMU_MODE_1K,
++ gcvMMU_MODE_4K,
++} gceMMU_MODE;
++
++/* User signal command codes. */
++typedef enum _gceUSER_SIGNAL_COMMAND_CODES
++{
++ gcvUSER_SIGNAL_CREATE,
++ gcvUSER_SIGNAL_DESTROY,
++ gcvUSER_SIGNAL_SIGNAL,
++ gcvUSER_SIGNAL_WAIT,
++ gcvUSER_SIGNAL_MAP,
++ gcvUSER_SIGNAL_UNMAP,
++}
++gceUSER_SIGNAL_COMMAND_CODES;
++
++/* Sync point command codes. */
++typedef enum _gceSYNC_POINT_COMMAND_CODES
++{
++ gcvSYNC_POINT_CREATE,
++ gcvSYNC_POINT_DESTROY,
++ gcvSYNC_POINT_SIGNAL,
++}
++gceSYNC_POINT_COMMAND_CODES;
++
++/* Shared buffer command codes. */
++typedef enum _gceSHBUF_COMMAND_CODES
++{
++ gcvSHBUF_CREATE,
++ gcvSHBUF_DESTROY,
++ gcvSHBUF_MAP,
++ gcvSHBUF_WRITE,
++ gcvSHBUF_READ,
++}
++gceSHBUF_COMMAND_CODES;
++
++/* Event locations. */
++typedef enum _gceKERNEL_WHERE
++{
++ gcvKERNEL_COMMAND,
++ gcvKERNEL_VERTEX,
++ gcvKERNEL_TRIANGLE,
++ gcvKERNEL_TEXTURE,
++ gcvKERNEL_PIXEL,
++}
++gceKERNEL_WHERE;
++
++#if gcdENABLE_VG
++/* Hardware blocks. */
++typedef enum _gceBLOCK
++{
++ gcvBLOCK_COMMAND,
++ gcvBLOCK_TESSELLATOR,
++ gcvBLOCK_TESSELLATOR2,
++ gcvBLOCK_TESSELLATOR3,
++ gcvBLOCK_RASTER,
++ gcvBLOCK_VG,
++ gcvBLOCK_VG2,
++ gcvBLOCK_VG3,
++ gcvBLOCK_PIXEL,
++
++ /* Number of defined blocks. */
++ gcvBLOCK_COUNT
++}
++gceBLOCK;
++#endif
++
++/* gcdDUMP message type. */
++typedef enum _gceDEBUG_MESSAGE_TYPE
++{
++ gcvMESSAGE_TEXT,
++ gcvMESSAGE_DUMP
++}
++gceDEBUG_MESSAGE_TYPE;
++
++/* Shading format. */
++typedef enum _gceSHADING
++{
++ gcvSHADING_SMOOTH,
++ gcvSHADING_FLAT_D3D,
++ gcvSHADING_FLAT_OPENGL,
++}
++gceSHADING;
++
++/* Culling modes. */
++typedef enum _gceCULL
++{
++ gcvCULL_NONE,
++ gcvCULL_CCW,
++ gcvCULL_CW,
++}
++gceCULL;
++
++/* Fill modes. */
++typedef enum _gceFILL
++{
++ gcvFILL_POINT,
++ gcvFILL_WIRE_FRAME,
++ gcvFILL_SOLID,
++}
++gceFILL;
++
++/* Compare modes. */
++typedef enum _gceCOMPARE
++{
++ gcvCOMPARE_INVALID = 0,
++ gcvCOMPARE_NEVER,
++ gcvCOMPARE_NOT_EQUAL,
++ gcvCOMPARE_LESS,
++ gcvCOMPARE_LESS_OR_EQUAL,
++ gcvCOMPARE_EQUAL,
++ gcvCOMPARE_GREATER,
++ gcvCOMPARE_GREATER_OR_EQUAL,
++ gcvCOMPARE_ALWAYS,
++}
++gceCOMPARE;
++
++/* Stencil modes. */
++typedef enum _gceSTENCIL_MODE
++{
++ gcvSTENCIL_NONE,
++ gcvSTENCIL_SINGLE_SIDED,
++ gcvSTENCIL_DOUBLE_SIDED,
++}
++gceSTENCIL_MODE;
++
++/* Stencil operations. */
++typedef enum _gceSTENCIL_OPERATION
++{
++ gcvSTENCIL_KEEP,
++ gcvSTENCIL_REPLACE,
++ gcvSTENCIL_ZERO,
++ gcvSTENCIL_INVERT,
++ gcvSTENCIL_INCREMENT,
++ gcvSTENCIL_DECREMENT,
++ gcvSTENCIL_INCREMENT_SATURATE,
++ gcvSTENCIL_DECREMENT_SATURATE,
++ gcvSTENCIL_OPERATION_INVALID = -1
++}
++gceSTENCIL_OPERATION;
++
++/* Stencil selection. */
++typedef enum _gceSTENCIL_WHERE
++{
++ gcvSTENCIL_FRONT,
++ gcvSTENCIL_BACK,
++}
++gceSTENCIL_WHERE;
++
++/* Texture addressing selection. */
++typedef enum _gceTEXTURE_WHICH
++{
++ gcvTEXTURE_S,
++ gcvTEXTURE_T,
++ gcvTEXTURE_R,
++}
++gceTEXTURE_WHICH;
++
++/* Texture addressing modes. */
++typedef enum _gceTEXTURE_ADDRESSING
++{
++ gcvTEXTURE_INVALID = 0,
++ gcvTEXTURE_CLAMP,
++ gcvTEXTURE_WRAP,
++ gcvTEXTURE_MIRROR,
++ gcvTEXTURE_BORDER,
++ gcvTEXTURE_MIRROR_ONCE,
++}
++gceTEXTURE_ADDRESSING;
++
++/* Texture filters. */
++typedef enum _gceTEXTURE_FILTER
++{
++ gcvTEXTURE_NONE,
++ gcvTEXTURE_POINT,
++ gcvTEXTURE_LINEAR,
++ gcvTEXTURE_ANISOTROPIC,
++}
++gceTEXTURE_FILTER;
++
++typedef enum _gceTEXTURE_COMPONENT
++{
++ gcvTEXTURE_COMPONENT_R,
++ gcvTEXTURE_COMPONENT_G,
++ gcvTEXTURE_COMPONENT_B,
++ gcvTEXTURE_COMPONENT_A,
++
++ gcvTEXTURE_COMPONENT_NUM,
++} gceTEXTURE_COMPONENT;
++
++/* Texture swizzle modes. */
++typedef enum _gceTEXTURE_SWIZZLE
++{
++ gcvTEXTURE_SWIZZLE_R = 0,
++ gcvTEXTURE_SWIZZLE_G,
++ gcvTEXTURE_SWIZZLE_B,
++ gcvTEXTURE_SWIZZLE_A,
++ gcvTEXTURE_SWIZZLE_0,
++ gcvTEXTURE_SWIZZLE_1,
++
++ gcvTEXTURE_SWIZZLE_INVALID,
++} gceTEXTURE_SWIZZLE;
++
++typedef enum _gceTEXTURE_COMPARE_MODE
++{
++ gcvTEXTURE_COMPARE_MODE_INVALID = 0,
++ gcvTEXTURE_COMPARE_MODE_NONE,
++ gcvTEXTURE_COMPARE_MODE_REF,
++} gceTEXTURE_COMPARE_MODE;
++
++/* Pixel output swizzle modes. */
++typedef enum _gcePIXEL_SWIZZLE
++{
++ gcvPIXEL_SWIZZLE_R = gcvTEXTURE_SWIZZLE_R,
++ gcvPIXEL_SWIZZLE_G = gcvTEXTURE_SWIZZLE_G,
++ gcvPIXEL_SWIZZLE_B = gcvTEXTURE_SWIZZLE_B,
++ gcvPIXEL_SWIZZLE_A = gcvTEXTURE_SWIZZLE_A,
++
++ gcvPIXEL_SWIZZLE_INVALID,
++} gcePIXEL_SWIZZLE;
++
++/* Primitive types. */
++typedef enum _gcePRIMITIVE
++{
++ gcvPRIMITIVE_POINT_LIST,
++ gcvPRIMITIVE_LINE_LIST,
++ gcvPRIMITIVE_LINE_STRIP,
++ gcvPRIMITIVE_LINE_LOOP,
++ gcvPRIMITIVE_TRIANGLE_LIST,
++ gcvPRIMITIVE_TRIANGLE_STRIP,
++ gcvPRIMITIVE_TRIANGLE_FAN,
++ gcvPRIMITIVE_RECTANGLE,
++}
++gcePRIMITIVE;
++
++/* Index types. */
++typedef enum _gceINDEX_TYPE
++{
++ gcvINDEX_8,
++ gcvINDEX_16,
++ gcvINDEX_32,
++}
++gceINDEX_TYPE;
++
++/* Multi GPU rendering modes. */
++typedef enum _gceMULTI_GPU_RENDERING_MODE
++{
++ gcvMULTI_GPU_RENDERING_MODE_OFF,
++ gcvMULTI_GPU_RENDERING_MODE_SPLIT_WIDTH,
++ gcvMULTI_GPU_RENDERING_MODE_SPLIT_HEIGHT,
++ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_64x64,
++ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_128x64,
++ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_128x128
++}
++gceMULTI_GPU_RENDERING_MODE;
++
++typedef enum _gceCORE_3D_MASK
++{
++ gcvCORE_3D_0_MASK = (1 << 0),
++ gcvCORE_3D_1_MASK = (1 << 1),
++
++ gcvCORE_3D_ALL_MASK = (0xFFFF)
++}
++gceCORE_3D_MASK;
++
++typedef enum _gceCORE_3D_ID
++{
++ gcvCORE_3D_0_ID = 0,
++ gcvCORE_3D_1_ID = 1,
++
++ gcvCORE_3D_ID_INVALID = ~0UL
++}
++gceCORE_3D_ID;
++
++typedef enum _gceMULTI_GPU_MODE
++{
++ gcvMULTI_GPU_MODE_COMBINED = 0,
++ gcvMULTI_GPU_MODE_INDEPENDENT = 1
++}
++gceMULTI_GPU_MODE;
++
++typedef enum _gceMACHINECODE
++{
++ gcvMACHINECODE_ANTUTU0 = 0x0,
++
++ gcvMACHINECODE_GLB27_RELEASE_0,
++
++ gcvMACHINECODE_GLB25_RELEASE_0,
++ gcvMACHINECODE_GLB25_RELEASE_1,
++ gcvMACHINECODE_GLB25_RELEASE_2,
++
++ /* keep it as the last enum */
++ gcvMACHINECODE_COUNT
++}
++gceMACHINECODE;
++
++typedef enum _gceUNIFORMCVT
++{
++ gcvUNIFORMCVT_NONE = 0,
++ gcvUNIFORMCVT_TO_BOOL,
++ gcvUNIFORMCVT_TO_FLOAT,
++} gceUNIFORMCVT;
++
++typedef enum _gceHAL_ARG_VERSION
++{
++ gcvHAL_ARG_VERSION_V1 = 0x0,
++}
++gceHAL_ARG_VERSION;
++
++
++/*
++* Bit of a requirment is 1 means requirement is a must, 0 means requirement can
++* be ignored.
++*/
++#define gcvALLOC_FLAG_CONTIGUOUS_BIT 0
++#define gcvALLOC_FLAG_CACHEABLE_BIT 1
++#define gcvALLOC_FLAG_SECURITY_BIT 2
++#define gcvALLOC_FLAG_NON_CONTIGUOUS_BIT 3
++#define gcvALLOC_FLAG_MEMLIMIT_BIT 4
++
++/* No special needs. */
++#define gcvALLOC_FLAG_NONE (0)
++/* Physical contiguous. */
++#define gcvALLOC_FLAG_CONTIGUOUS (1 << gcvALLOC_FLAG_CONTIGUOUS_BIT)
++/* Can be remapped as cacheable. */
++#define gcvALLOC_FLAG_CACHEABLE (1 << gcvALLOC_FLAG_CACHEABLE_BIT)
++/* Secure buffer. */
++#define gcvALLOC_FLAG_SECURITY (1 << gcvALLOC_FLAG_SECURITY_BIT)
++/* Physical non contiguous. */
++#define gcvALLOC_FLAG_NON_CONTIGUOUS (1 << gcvALLOC_FLAG_NON_CONTIGUOUS_BIT)
++#define gcvALLOC_FLAG_MEMLIMIT (1 << gcvALLOC_FLAG_MEMLIMIT_BIT)
++
++/* GL_VIV internal usage */
++#ifndef GL_MAP_BUFFER_OBJ_VIV
++#define GL_MAP_BUFFER_OBJ_VIV 0x10000
++#endif
++
++/* Command buffer usage. */
++#define gcvCOMMAND_2D (1 << 0)
++#define gcvCOMMAND_3D (1 << 1)
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gckCONTEXT * gckCONTEXT;
++typedef struct _gcoCMDBUF * gcoCMDBUF;
++
++typedef struct _gcsSTATE_DELTA * gcsSTATE_DELTA_PTR;
++typedef struct _gcsQUEUE * gcsQUEUE_PTR;
++typedef struct _gcoQUEUE * gcoQUEUE;
++typedef struct _gcsHAL_INTERFACE * gcsHAL_INTERFACE_PTR;
++typedef struct _gcs2D_PROFILE * gcs2D_PROFILE_PTR;
++
++#if gcdENABLE_VG
++typedef struct _gcoVGHARDWARE * gcoVGHARDWARE;
++typedef struct _gcoVGBUFFER * gcoVGBUFFER;
++typedef struct _gckVGHARDWARE * gckVGHARDWARE;
++typedef struct _gcsVGCONTEXT * gcsVGCONTEXT_PTR;
++typedef struct _gcsVGCONTEXT_MAP * gcsVGCONTEXT_MAP_PTR;
++typedef struct _gcsVGCMDQUEUE * gcsVGCMDQUEUE_PTR;
++typedef struct _gcsTASK_MASTER_TABLE * gcsTASK_MASTER_TABLE_PTR;
++typedef struct _gckVGKERNEL * gckVGKERNEL;
++typedef void * gctTHREAD;
++#endif
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_enum_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h 2016-06-19 22:11:55.237144468 +0200
+@@ -0,0 +1,2859 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_h_
++#define __gc_hal_h_
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++#include "gc_hal_profiler.h"
++#include "gc_hal_driver.h"
++#if gcdENABLE_3D
++#include "gc_hal_statistics.h"
++#endif
++
++#if gcdSECURITY
++#include "gc_hal_security_interface.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++******************************* Alignment Macros *******************************
++\******************************************************************************/
++
++/* Alignment with a non-power of two value. */
++#define gcmALIGN_NP2(n, align) \
++( \
++ ((n) + (align) - 1) - (((n) + (align) - 1) % (align)) \
++)
++
++/* Alignment with a power of two value. */
++#define gcmALIGN(n, align) \
++( \
++ ((n) + ((align) - 1)) & ~((align) - 1) \
++)
++
++#define gcmALIGN_BASE(n, align) \
++( \
++ ((n) & ~((align) - 1)) \
++)
++
++/******************************************************************************\
++***************************** Element Count Macro *****************************
++\******************************************************************************/
++
++#define gcmSIZEOF(a) \
++( \
++ (gctSIZE_T) (sizeof(a)) \
++)
++
++#define gcmCOUNTOF(a) \
++( \
++ sizeof(a) / sizeof(a[0]) \
++)
++
++/******************************************************************************\
++********************************* Cast Macro **********************************
++\******************************************************************************/
++#define gcmNAME_TO_PTR(na) \
++ gckKERNEL_QueryPointerFromName(kernel, gcmALL_TO_UINT32(na))
++
++#define gcmPTR_TO_NAME(ptr) \
++ gckKERNEL_AllocateNameFromPointer(kernel, ptr)
++
++#define gcmRELEASE_NAME(na) \
++ gckKERNEL_DeleteName(kernel, gcmALL_TO_UINT32(na))
++
++#define gcmALL_TO_UINT32(t) \
++( \
++ (gctUINT32) (gctUINTPTR_T) (t)\
++)
++
++#define gcmPTR_TO_UINT64(p) \
++( \
++ (gctUINT64) (gctUINTPTR_T) (p)\
++)
++
++#define gcmUINT64_TO_PTR(u) \
++( \
++ (gctPOINTER) (gctUINTPTR_T) (u)\
++)
++
++#define gcmUINT64_TO_TYPE(u, t) \
++( \
++ (t) (gctUINTPTR_T) (u)\
++)
++
++/******************************************************************************\
++******************************** Useful Macro *********************************
++\******************************************************************************/
++
++#define gcvINVALID_ADDRESS ~0U
++
++#define gcmGET_PRE_ROTATION(rotate) \
++ ((rotate) & (~(gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y)))
++
++#define gcmGET_POST_ROTATION(rotate) \
++ ((rotate) & (gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y))
++
++/******************************************************************************\
++******************************** gcsOBJECT Object *******************************
++\******************************************************************************/
++
++/* Type of objects. */
++typedef enum _gceOBJECT_TYPE
++{
++ gcvOBJ_UNKNOWN = 0,
++ gcvOBJ_2D = gcmCC('2','D',' ',' '),
++ gcvOBJ_3D = gcmCC('3','D',' ',' '),
++ gcvOBJ_ATTRIBUTE = gcmCC('A','T','T','R'),
++ gcvOBJ_BRUSHCACHE = gcmCC('B','R','U','$'),
++ gcvOBJ_BRUSHNODE = gcmCC('B','R','U','n'),
++ gcvOBJ_BRUSH = gcmCC('B','R','U','o'),
++ gcvOBJ_BUFFER = gcmCC('B','U','F','R'),
++ gcvOBJ_COMMAND = gcmCC('C','M','D',' '),
++ gcvOBJ_COMMANDBUFFER = gcmCC('C','M','D','B'),
++ gcvOBJ_CONTEXT = gcmCC('C','T','X','T'),
++ gcvOBJ_DEVICE = gcmCC('D','E','V',' '),
++ gcvOBJ_DUMP = gcmCC('D','U','M','P'),
++ gcvOBJ_EVENT = gcmCC('E','V','N','T'),
++ gcvOBJ_FUNCTION = gcmCC('F','U','N','C'),
++ gcvOBJ_HAL = gcmCC('H','A','L',' '),
++ gcvOBJ_HARDWARE = gcmCC('H','A','R','D'),
++ gcvOBJ_HEAP = gcmCC('H','E','A','P'),
++ gcvOBJ_INDEX = gcmCC('I','N','D','X'),
++ gcvOBJ_INTERRUPT = gcmCC('I','N','T','R'),
++ gcvOBJ_KERNEL = gcmCC('K','E','R','N'),
++ gcvOBJ_KERNEL_FUNCTION = gcmCC('K','F','C','N'),
++ gcvOBJ_MEMORYBUFFER = gcmCC('M','E','M','B'),
++ gcvOBJ_MMU = gcmCC('M','M','U',' '),
++ gcvOBJ_OS = gcmCC('O','S',' ',' '),
++ gcvOBJ_OUTPUT = gcmCC('O','U','T','P'),
++ gcvOBJ_PAINT = gcmCC('P','N','T',' '),
++ gcvOBJ_PATH = gcmCC('P','A','T','H'),
++ gcvOBJ_QUEUE = gcmCC('Q','U','E',' '),
++ gcvOBJ_SAMPLER = gcmCC('S','A','M','P'),
++ gcvOBJ_SHADER = gcmCC('S','H','D','R'),
++ gcvOBJ_STREAM = gcmCC('S','T','R','M'),
++ gcvOBJ_SURF = gcmCC('S','U','R','F'),
++ gcvOBJ_TEXTURE = gcmCC('T','X','T','R'),
++ gcvOBJ_UNIFORM = gcmCC('U','N','I','F'),
++ gcvOBJ_VARIABLE = gcmCC('V','A','R','I'),
++ gcvOBJ_VERTEX = gcmCC('V','R','T','X'),
++ gcvOBJ_VIDMEM = gcmCC('V','M','E','M'),
++ gcvOBJ_VG = gcmCC('V','G',' ',' '),
++ gcvOBJ_BUFOBJ = gcmCC('B','U','F','O'),
++ gcvOBJ_UNIFORM_BLOCK = gcmCC('U','B','L','K'),
++ gcvOBJ_CL = gcmCC('C','L',' ',' '),
++}
++gceOBJECT_TYPE;
++
++/* gcsOBJECT object defintinon. */
++typedef struct _gcsOBJECT
++{
++ /* Type of an object. */
++ gceOBJECT_TYPE type;
++}
++gcsOBJECT;
++
++typedef struct _gckHARDWARE * gckHARDWARE;
++
++/* CORE flags. */
++typedef enum _gceCORE
++{
++ gcvCORE_MAJOR = 0x0,
++ gcvCORE_2D = 0x1,
++ gcvCORE_VG = 0x2,
++#if gcdMULTI_GPU_AFFINITY
++ gcvCORE_OCL = 0x3,
++#endif
++}
++gceCORE;
++
++#if gcdMULTI_GPU_AFFINITY
++#define gcdMAX_GPU_COUNT 4
++#else
++#define gcdMAX_GPU_COUNT 3
++#endif
++
++#define gcdMAX_SURF_LAYER 4
++
++#define gcdMAX_DRAW_BUFFERS 4
++
++/*******************************************************************************
++**
++** gcmVERIFY_OBJECT
++**
++** Assert if an object is invalid or is not of the specified type. If the
++** object is invalid or not of the specified type, gcvSTATUS_INVALID_OBJECT
++** will be returned from the current function. In retail mode this macro
++** does nothing.
++**
++** ARGUMENTS:
++**
++** obj Object to test.
++** t Expected type of the object.
++*/
++#if gcmIS_DEBUG(gcdDEBUG_TRACE)
++#define _gcmVERIFY_OBJECT(prefix, obj, t) \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \
++ return gcvSTATUS_INVALID_OBJECT; \
++ }
++
++# define gcmVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcm, obj, t)
++# define gcmkVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcmk, obj, t)
++#else
++# define gcmVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++# define gcmkVERIFY_OBJECT(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************/
++/*VERIFY_OBJECT if special return expected*/
++/******************************************************************************/
++#ifndef EGL_API_ANDROID
++# define _gcmVERIFY_OBJECT_RETURN(prefix, obj, t, retVal) \
++ do \
++ { \
++ if ((obj) == gcvNULL) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: NULL"); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT((obj) != gcvNULL); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ else if (((gcsOBJECT*) (obj))->type != t) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "VERIFY_OBJECT_RETURN failed: %c%c%c%c", \
++ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \
++ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \
++ gcmCC_PRINT(t)); \
++ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \
++ prefix##FOOTER_ARG("retVal=%d", retVal); \
++ return retVal; \
++ } \
++ } \
++ while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcm, obj, t, retVal)
++# define gcmkVERIFY_OBJECT_RETURN(obj, t, retVal) \
++ _gcmVERIFY_OBJECT_RETURN(gcmk, obj, t, retVal)
++#else
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE)
++#endif
++
++/******************************************************************************\
++********************************** gckOS Object *********************************
++\******************************************************************************/
++
++/* Construct a new gckOS object. */
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ );
++
++/* Destroy an gckOS object. */
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckOS_QueryVideoMemory(
++ IN gckOS Os,
++ OUT gctPHYS_ADDR * InternalAddress,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctPHYS_ADDR * ExternalAddress,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctPHYS_ADDR * ContiguousAddress,
++ OUT gctSIZE_T * ContiguousSize
++ );
++
++/* Allocate memory from the heap. */
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Free allocated memory. */
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Wrapper for allocation memory.. */
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ );
++
++/* Wrapper for freeing memory. */
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Allocate paged memory. */
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gctUINT32 * Gid,
++ OUT gctPHYS_ADDR * Physical
++ );
++
++/* Lock pages. */
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ );
++
++/* Map pages. */
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address,
++ IN gctPOINTER PageTable
++ );
++
++gceSTATUS
++gckOS_UnmapPages(
++ IN gckOS Os,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address
++ );
++
++/* Unlock pages. */
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Free paged memory. */
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Allocate non-paged memory. */
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free non-paged memory. */
++gceSTATUS
++gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ );
++
++/* Allocate contiguous memory. */
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ );
++
++/* Free contiguous memory. */
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Get the number fo bytes per page. */
++gceSTATUS
++gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Get the physical address of a corresponding user logical address. */
++gceSTATUS
++gckOS_UserLogicalToPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ );
++
++/* Get the physical address of a corresponding logical address. */
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ );
++
++/* Map physical memory. */
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap previously mapped physical memory. */
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ );
++
++/* Get real physical address from descriptor. */
++gceSTATUS
++gckOS_PhysicalToPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Physical,
++ OUT gctUINT32 * PhysicalAddress
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Read data from a hardware register. */
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++/* Write data to a hardware register. */
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckOS_ReadRegisterByCoreId(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 CoreId,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ );
++
++gceSTATUS
++gckOS_WriteRegisterByCoreId(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 CoreId,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ );
++#endif
++
++/* Write data to a 32-bit memory location. */
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ );
++
++/* Map physical memory into the process space. */
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap physical memory from the specified process space. */
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ );
++
++/* Unmap physical memory from the process space. */
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Unmap user logical memory out of physical memory.
++ * This function is only supported in Linux currently.
++ */
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Create a new mutex. */
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ );
++
++/* Delete a mutex. */
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Acquire a mutex. */
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ );
++
++/* Release a mutex. */
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ );
++
++/* Atomically exchange a pair of 32-bit values. */
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ );
++
++/* Atomically exchange a pair of pointers. */
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ );
++
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ );
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ );
++
++/* Delay a number of microseconds. */
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ );
++
++/* Get time in milliseconds. */
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ );
++
++/* Compare time value. */
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ );
++
++/* Get time in microseconds. */
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ );
++
++/* Memory barrier. */
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ );
++
++/* Map user pointer. */
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Unmap user pointer. */
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ );
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ );
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ );
++
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++/* Get the base address for the physical memory. */
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ );
++
++/* Perform a memory copy. */
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ );
++
++/* Zero memory. */
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ );
++
++/* Device I/O control to the kernel HAL layer. */
++gceSTATUS
++gckOS_DeviceControl(
++ IN gckOS Os,
++ IN gctBOOL FromUser,
++ IN gctUINT32 IoControlCode,
++ IN gctPOINTER InputBuffer,
++ IN gctSIZE_T InputBufferSize,
++ OUT gctPOINTER OutputBuffer,
++ IN gctSIZE_T OutputBufferSize
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++gceSTATUS
++gckOS_GetCurrentProcessID(
++ OUT gctUINT32_PTR ProcessID
++ );
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ );
++
++#if gcdSECURITY
++gceSTATUS
++gckOS_OpenSecurityChannel(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 *Channel
++ );
++
++gceSTATUS
++gckOS_CloseSecurityChannel(
++ IN gctUINT32 Channel
++ );
++
++gceSTATUS
++gckOS_CallSecurityService(
++ IN gctUINT32 Channel,
++ IN gcsTA_INTERFACE * Interface
++ );
++
++gceSTATUS
++gckOS_InitSecurityChannel(
++ OUT gctUINT32 Channel
++ );
++
++gceSTATUS
++gckOS_AllocatePageArray(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageArrayLogical,
++ OUT gctPHYS_ADDR * PageArrayPhysical
++ );
++#endif
++
++/******************************************************************************\
++********************************** Signal Object *********************************
++\******************************************************************************/
++
++/* Create a signal. */
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ );
++
++/* Destroy a signal. */
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Signal a signal. */
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ );
++
++/* Wait for a signal. */
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ );
++
++/* Map a user signal to the kernel space. */
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ );
++
++/* Unmap a user signal */
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ );
++
++/* Map user memory. */
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ );
++
++/* Unmap user memory. */
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ );
++
++/******************************************************************************\
++************************** Android Native Fence Sync ***************************
++\******************************************************************************/
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ );
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ );
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ );
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ );
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ );
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ );
++
++#if !USE_NEW_LINUX_SIGNAL
++/* Create signal to be used in the user space. */
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ );
++
++/* Destroy signal used in the user space. */
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ );
++
++/* Wait for signal used in the user space. */
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ );
++
++/* Signal a signal used in the user space. */
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ );
++#endif /* USE_NEW_LINUX_SIGNAL */
++
++/* Set a signal owned by a process. */
++#if defined(__QNXNTO__)
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctINT Recvid,
++ IN gctINT Coid
++ );
++#else
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ );
++#endif
++
++/******************************************************************************\
++** Cache Support
++*/
++
++gceSTATUS
++gckOS_CacheClean(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctUINT32 Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheFlush(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctUINT32 Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CacheInvalidate(
++ gckOS Os,
++ gctUINT32 ProcessID,
++ gctPHYS_ADDR Handle,
++ gctUINT32 Physical,
++ gctPOINTER Logical,
++ gctSIZE_T Bytes
++ );
++
++gceSTATUS
++gckOS_CPUPhysicalToGPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 CPUPhysical,
++ IN gctUINT32_PTR GPUPhysical
++ );
++
++gceSTATUS
++gckOS_GPUPhysicalToCPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 GPUPhysical,
++ IN gctUINT32_PTR CPUPhysical
++ );
++
++gceSTATUS
++gckOS_QueryOption(
++ IN gckOS Os,
++ IN gctCONST_STRING Option,
++ OUT gctUINT32 * Value
++ );
++
++/******************************************************************************\
++** Debug Support
++*/
++
++void
++gckOS_SetDebugLevel(
++ IN gctUINT32 Level
++ );
++
++void
++gckOS_SetDebugZone(
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugLevelZone(
++ IN gctUINT32 Level,
++ IN gctUINT32 Zone
++ );
++
++void
++gckOS_SetDebugZones(
++ IN gctUINT32 Zones,
++ IN gctBOOL Enable
++ );
++
++void
++gckOS_SetDebugFile(
++ IN gctCONST_STRING FileName
++ );
++
++/*******************************************************************************
++** Broadcast interface.
++*/
++
++typedef enum _gceBROADCAST
++{
++ /* GPU might be idle. */
++ gcvBROADCAST_GPU_IDLE,
++
++ /* A commit is going to happen. */
++ gcvBROADCAST_GPU_COMMIT,
++
++ /* GPU seems to be stuck. */
++ gcvBROADCAST_GPU_STUCK,
++
++ /* First process gets attached. */
++ gcvBROADCAST_FIRST_PROCESS,
++
++ /* Last process gets detached. */
++ gcvBROADCAST_LAST_PROCESS,
++
++ /* AXI bus error. */
++ gcvBROADCAST_AXI_BUS_ERROR,
++
++ /* Out of memory. */
++ gcvBROADCAST_OUT_OF_MEMORY,
++}
++gceBROADCAST;
++
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ );
++
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ );
++
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ );
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gceCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ );
++
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ );
++
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ );
++
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ );
++
++/*******************************************************************************
++** Semaphores.
++*/
++
++/* Create a new semaphore. */
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ );
++#endif
++
++/* Delete a semahore. */
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Acquire a semahore. */
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Try to acquire a semahore. */
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/* Release a semahore. */
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ );
++
++/*******************************************************************************
++** Timer API.
++*/
++
++typedef void (*gctTIMERFUNCTION)(gctPOINTER);
++
++/* Create a timer. */
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ );
++
++/* Destory a timer. */
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/* Start a timer. */
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ );
++
++/* Stop a timer. */
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ );
++
++/******************************************************************************\
++********************************* gckHEAP Object ********************************
++\******************************************************************************/
++
++typedef struct _gckHEAP * gckHEAP;
++
++/* Construct a new gckHEAP object. */
++gceSTATUS
++gckHEAP_Construct(
++ IN gckOS Os,
++ IN gctSIZE_T AllocationSize,
++ OUT gckHEAP * Heap
++ );
++
++/* Destroy an gckHEAP object. */
++gceSTATUS
++gckHEAP_Destroy(
++ IN gckHEAP Heap
++ );
++
++/* Allocate memory. */
++gceSTATUS
++gckHEAP_Allocate(
++ IN gckHEAP Heap,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckHEAP_Free(
++ IN gckHEAP Heap,
++ IN gctPOINTER Node
++ );
++
++/* Profile the heap. */
++gceSTATUS
++gckHEAP_ProfileStart(
++ IN gckHEAP Heap
++ );
++
++gceSTATUS
++gckHEAP_ProfileEnd(
++ IN gckHEAP Heap,
++ IN gctCONST_STRING Title
++ );
++
++
++/******************************************************************************\
++******************************** gckVIDMEM Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVIDMEM * gckVIDMEM;
++typedef struct _gckKERNEL * gckKERNEL;
++typedef struct _gckDB * gckDB;
++typedef struct _gckDVFS * gckDVFS;
++
++/* Construct a new gckVIDMEM object. */
++gceSTATUS
++gckVIDMEM_Construct(
++ IN gckOS Os,
++ IN gctUINT32 BaseAddress,
++ IN gctSIZE_T Bytes,
++ IN gctSIZE_T Threshold,
++ IN gctSIZE_T Banking,
++ OUT gckVIDMEM * Memory
++ );
++
++/* Destroy an gckVDIMEM object. */
++gceSTATUS
++gckVIDMEM_Destroy(
++ IN gckVIDMEM Memory
++ );
++
++/* Allocate linear memory. */
++gceSTATUS
++gckVIDMEM_AllocateLinear(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM Memory,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctBOOL Specified,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Free memory. */
++gceSTATUS
++gckVIDMEM_Free(
++ IN gckKERNEL Kernel,
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/* Lock memory. */
++gceSTATUS
++gckVIDMEM_Lock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gctBOOL Cacheable,
++ OUT gctUINT32 * Address,
++ OUT gctUINT32 * Gid,
++ OUT gctUINT64 * PhysicalAddress
++ );
++
++/* Unlock memory. */
++gceSTATUS
++gckVIDMEM_Unlock(
++ IN gckKERNEL Kernel,
++ IN gckVIDMEM_NODE Node,
++ IN gceSURF_TYPE Type,
++ IN OUT gctBOOL * Asynchroneous
++ );
++
++/* Construct a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_ConstructVirtual(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Destroy a gcuVIDMEM_NODE union for virtual memory. */
++gceSTATUS
++gckVIDMEM_DestroyVirtual(
++ IN gcuVIDMEM_NODE_PTR Node
++ );
++
++/******************************************************************************\
++******************************** gckKERNEL Object ******************************
++\******************************************************************************/
++
++struct _gcsHAL_INTERFACE;
++
++/* Notifications. */
++typedef enum _gceNOTIFY
++{
++ gcvNOTIFY_INTERRUPT,
++ gcvNOTIFY_COMMAND_QUEUE,
++}
++gceNOTIFY;
++
++/* Flush flags. */
++typedef enum _gceKERNEL_FLUSH
++{
++ gcvFLUSH_COLOR = 0x01,
++ gcvFLUSH_DEPTH = 0x02,
++ gcvFLUSH_TEXTURE = 0x04,
++ gcvFLUSH_2D = 0x08,
++#if gcdMULTI_GPU
++ gcvFLUSH_L2 = 0x10,
++#endif
++ gcvFLUSH_TILE_STATUS = 0x20,
++ gcvFLUSH_ALL = gcvFLUSH_COLOR
++ | gcvFLUSH_DEPTH
++ | gcvFLUSH_TEXTURE
++ | gcvFLUSH_2D
++#if gcdMULTI_GPU
++ | gcvFLUSH_L2
++#endif
++ | gcvFLUSH_TILE_STATUS
++}
++gceKERNEL_FLUSH;
++
++/* Construct a new gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Context,
++ IN gckDB SharedDB,
++ OUT gckKERNEL * Kernel
++ );
++
++/* Destroy an gckKERNEL object. */
++gceSTATUS
++gckKERNEL_Destroy(
++ IN gckKERNEL Kernel
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query Database requirements. */
++gceSTATUS
++ gckKERNEL_QueryDatabase(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ );
++
++/* Query the video memory. */
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Lookup the gckVIDMEM object for a pool. */
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ );
++
++gceSTATUS
++gckKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ IN gctUINT32 Flag,
++ OUT gctUINT32 * Node
++ );
++
++gceSTATUS
++gckKERNEL_ReleaseVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN gctUINT32 Handle
++ );
++
++gceSTATUS
++gckKERNEL_LockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctUINT32 ProcessID,
++ IN gctBOOL FromUser,
++ IN OUT gcsHAL_INTERFACE * Interface
++ );
++
++gceSTATUS
++gckKERNEL_UnlockVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 ProcessID,
++ IN OUT gcsHAL_INTERFACE * Interface
++ );
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++#ifdef __QNXNTO__
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes,
++#endif
++ OUT gctPOINTER * Logical
++ );
++
++/* Map video memory. */
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++#ifdef __QNXNTO__
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes,
++#endif
++ OUT gctPOINTER * Logical
++ );
++
++#ifdef __QNXNTO__
++/* Unmap video memory. */
++gceSTATUS
++gckKERNEL_UnmapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Pid,
++ IN gctUINT32 Bytes
++ );
++#endif
++
++/* Map memory. */
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Notification of events. */
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++#if gcdMULTI_GPU
++ IN gctUINT CoreId,
++#endif
++ IN gceNOTIFY Notifcation,
++ IN gctBOOL Data
++ );
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ );
++
++/*******************************************************************************
++**
++** gckKERNEL_Recovery
++**
++** Try to recover the GPU from a fatal error.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Recovery(
++ IN gckKERNEL Kernel
++ );
++
++/* Set the value of timeout on HW operation. */
++void
++gckKERNEL_SetTimeOut(
++ IN gckKERNEL Kernel,
++ IN gctUINT32 timeOut
++ );
++
++/* Get access to the user data. */
++gceSTATUS
++gckKERNEL_OpenUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctPOINTER StaticStorage,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Release resources associated with the user data connection. */
++gceSTATUS
++gckKERNEL_CloseUserData(
++ IN gckKERNEL Kernel,
++ IN gctBOOL NeedCopy,
++ IN gctBOOL FlushData,
++ IN gctPOINTER UserPointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ );
++
++gceSTATUS
++gckDVFS_Construct(
++ IN gckHARDWARE Hardware,
++ OUT gckDVFS * Frequency
++ );
++
++gceSTATUS
++gckDVFS_Destroy(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Start(
++ IN gckDVFS Dvfs
++ );
++
++gceSTATUS
++gckDVFS_Stop(
++ IN gckDVFS Dvfs
++ );
++
++/******************************************************************************\
++******************************* gckHARDWARE Object *****************************
++\******************************************************************************/
++
++/* Construct a new gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Construct(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gckHARDWARE * Hardware
++ );
++
++/* Destroy an gckHARDWARE object. */
++gceSTATUS
++gckHARDWARE_Destroy(
++ IN gckHARDWARE Hardware
++ );
++
++/* Get hardware type. */
++gceSTATUS
++gckHARDWARE_GetType(
++ IN gckHARDWARE Hardware,
++ OUT gceHARDWARE_TYPE * Type
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckHARDWARE_QuerySystemMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckHARDWARE_BuildVirtualAddress(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckHARDWARE_QueryCommandBuffer(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Alignment,
++ OUT gctUINT32 * ReservedHead,
++ OUT gctUINT32 * ReservedTail
++ );
++
++/* Add a WAIT/LINK pair in the command queue. */
++gceSTATUS
++gckHARDWARE_WaitLink(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset,
++ IN OUT gctUINT32 * Bytes,
++ OUT gctUINT32 * WaitOffset,
++ OUT gctUINT32 * WaitBytes
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckHARDWARE_Execute(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctSIZE_T Bytes
++ );
++
++/* Add an END command in the command queue. */
++gceSTATUS
++gckHARDWARE_End(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckHARDWARE_ChipEnable(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gceCORE_3D_MASK ChipEnable,
++ IN OUT gctSIZE_T * Bytes
++ );
++#endif
++
++/* Add a NOP command in the command queue. */
++gceSTATUS
++gckHARDWARE_Nop(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Add a PIPESELECT command in the command queue. */
++gceSTATUS
++gckHARDWARE_PipeSelect(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gcePIPE_SELECT Pipe,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Add a LINK command in the command queue. */
++gceSTATUS
++gckHARDWARE_Link(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 FetchAddress,
++ IN gctUINT32 FetchSize,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Add an EVENT command in the command queue. */
++gceSTATUS
++gckHARDWARE_Event(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT8 Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckHARDWARE_QueryMemory(
++ IN gckHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckHARDWARE_QueryChipIdentity(
++ IN gckHARDWARE Hardware,
++ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity
++ );
++
++/* Query the shader uniforms support. */
++gceSTATUS
++gckHARDWARE_QueryShaderCaps(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT * VertexUniforms,
++ OUT gctUINT * FragmentUniforms,
++ OUT gctBOOL * UnifiedUnforms
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckHARDWARE_SplitMemory(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Update command queue tail pointer. */
++gceSTATUS
++gckHARDWARE_UpdateQueueTail(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Offset
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckHARDWARE_ConvertLogical(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ );
++
++/* Interrupt manager. */
++gceSTATUS
++gckHARDWARE_Interrupt(
++ IN gckHARDWARE Hardware,
++#if gcdMULTI_GPU
++ IN gctUINT CoreId,
++#endif
++ IN gctBOOL InterruptValid
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckHARDWARE_SetMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckHARDWARE_FlushMMU(
++ IN gckHARDWARE Hardware
++ );
++
++/* Set the page table base address. */
++gceSTATUS
++gckHARDWARE_SetMMUv2(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Enable,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctBOOL FromPower
++ );
++
++#if gcdPROCESS_ADDRESS_SPACE
++/* Configure mmu configuration. */
++gceSTATUS
++gckHARDWARE_ConfigMMU(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctPOINTER MtlbLogical,
++ IN gctUINT32 Offset,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctSIZE_T * WaitLinkOffset,
++ OUT gctSIZE_T * WaitLinkBytes
++ );
++#endif
++
++/* Get idle register. */
++gceSTATUS
++gckHARDWARE_GetIdle(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Wait,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckHARDWARE_Flush(
++ IN gckHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckHARDWARE_SetFastClear(
++ IN gckHARDWARE Hardware,
++ IN gctINT Enable,
++ IN gctINT Compression
++ );
++
++gceSTATUS
++gckHARDWARE_ReadInterrupt(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckHARDWARE_SetPowerManagementState(
++ IN gckHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckHARDWARE_QueryPowerManagementState(
++ IN gckHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckHARDWARE_SetPowerManagement(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckHARDWARE_SetPowerManagementLock(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Lock
++ );
++
++gceSTATUS
++gckHARDWARE_SetGpuProfiler(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL GpuProfiler
++ );
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++gceSTATUS
++gckHARDWARE_SetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 FscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_GetFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT * FscaleValue,
++ IN gctUINT * MinFscaleValue,
++ IN gctUINT * MaxFscaleValue
++ );
++
++gceSTATUS
++gckHARDWARE_SetMinFscaleValue(
++ IN gckHARDWARE Hardware,
++ IN gctUINT MinFscaleValue
++ );
++#endif
++
++#if gcdPOWEROFF_TIMEOUT
++gceSTATUS
++gckHARDWARE_SetPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Timeout
++);
++
++gceSTATUS
++gckHARDWARE_QueryPowerOffTimeout(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++);
++#endif
++
++/* Profile 2D Engine. */
++gceSTATUS
++gckHARDWARE_ProfileEngine2D(
++ IN gckHARDWARE Hardware,
++ OUT gcs2D_PROFILE_PTR Profile
++ );
++
++gceSTATUS
++gckHARDWARE_InitializeHardware(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_Reset(
++ IN gckHARDWARE Hardware
++ );
++
++typedef gceSTATUS (*gctISRMANAGERFUNC)(gctPOINTER Context);
++
++gceSTATUS
++gckHARDWARE_SetIsrManager(
++ IN gckHARDWARE Hardware,
++ IN gctISRMANAGERFUNC StartIsr,
++ IN gctISRMANAGERFUNC StopIsr,
++ IN gctPOINTER Context
++ );
++
++/* Start a composition. */
++gceSTATUS
++gckHARDWARE_Compose(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Offset,
++ IN gctSIZE_T Size,
++ IN gctUINT8 EventID
++ );
++
++/* Check for Hardware features. */
++gceSTATUS
++gckHARDWARE_IsFeatureAvailable(
++ IN gckHARDWARE Hardware,
++ IN gceFEATURE Feature
++ );
++
++gceSTATUS
++gckHARDWARE_DumpMMUException(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_DumpGPUState(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_InitDVFS(
++ IN gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_QueryLoad(
++ IN gckHARDWARE Hardware,
++ OUT gctUINT32 * Load
++ );
++
++gceSTATUS
++gckHARDWARE_SetDVFSPeroid(
++ IN gckHARDWARE Hardware,
++ IN gctUINT32 Frequency
++ );
++
++gceSTATUS
++gckHARDWARE_PrepareFunctions(
++ gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckHARDWARE_SetMMUStates(
++ IN gckHARDWARE Hardware,
++ IN gctPOINTER MtlbAddress,
++ IN gceMMU_MODE Mode,
++ IN gctPOINTER SafeAddress,
++ IN gctPOINTER Logical,
++ IN OUT gctUINT32 * Bytes
++ );
++
++#if !gcdENABLE_VG
++/******************************************************************************\
++***************************** gckINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckINTERRUPT * gckINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckKERNEL Kernel
++ );
++
++gceSTATUS
++gckINTERRUPT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_Destroy(
++ IN gckINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckINTERRUPT_SetHandler(
++ IN gckINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckINTERRUPT_Notify(
++ IN gckINTERRUPT Interrupt,
++ IN gctBOOL Valid
++ );
++#endif
++/******************************************************************************\
++******************************** gckEVENT Object *******************************
++\******************************************************************************/
++
++typedef struct _gckEVENT * gckEVENT;
++
++/* Construct a new gckEVENT object. */
++gceSTATUS
++gckEVENT_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckEVENT * Event
++ );
++
++/* Destroy an gckEVENT object. */
++gceSTATUS
++gckEVENT_Destroy(
++ IN gckEVENT Event
++ );
++
++/* Reserve the next available hardware event. */
++#if gcdMULTI_GPU
++gceSTATUS
++gckEVENT_GetEvent(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ OUT gctUINT8 * EventID,
++ IN gceKERNEL_WHERE Source,
++ IN gceCORE_3D_MASK ChipEnable
++ );
++#else
++gceSTATUS
++gckEVENT_GetEvent(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ OUT gctUINT8 * EventID,
++ IN gceKERNEL_WHERE Source
++ );
++#endif
++
++/* Add a new event to the list of events. */
++gceSTATUS
++gckEVENT_AddList(
++ IN gckEVENT Event,
++ IN gcsHAL_INTERFACE_PTR Interface,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctBOOL AllocateAllowed,
++ IN gctBOOL FromKernel
++ );
++
++/* Schedule a FreeNonPagedMemory event. */
++gceSTATUS
++gckEVENT_FreeNonPagedMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeContiguousMemory event. */
++gceSTATUS
++gckEVENT_FreeContiguousMemory(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeVideoMemory event. */
++gceSTATUS
++gckEVENT_FreeVideoMemory(
++ IN gckEVENT Event,
++ IN gcuVIDMEM_NODE_PTR VideoMemory,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a signal event. */
++gceSTATUS
++gckEVENT_Signal(
++ IN gckEVENT Event,
++ IN gctSIGNAL Signal,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule an Unlock event. */
++gceSTATUS
++gckEVENT_Unlock(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere,
++ IN gctPOINTER Node,
++ IN gceSURF_TYPE Type
++ );
++
++gceSTATUS
++gckEVENT_CommitDone(
++ IN gckEVENT Event,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++/* Schedule a FreeVirtualCommandBuffer event. */
++gceSTATUS
++gckEVENT_DestroyVirtualCommandBuffer(
++ IN gckEVENT Event,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gceKERNEL_WHERE FromWhere
++ );
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower,
++ IN gceCORE_3D_MASK ChipEnable
++ );
++#else
++gceSTATUS
++gckEVENT_Submit(
++ IN gckEVENT Event,
++ IN gctBOOL Wait,
++ IN gctBOOL FromPower
++ );
++#endif
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue,
++ IN gceCORE_3D_MASK ChipEnable
++ );
++#else
++gceSTATUS
++gckEVENT_Commit(
++ IN gckEVENT Event,
++ IN gcsQUEUE_PTR Queue
++ );
++#endif
++
++/* Schedule a composition event. */
++gceSTATUS
++gckEVENT_Compose(
++ IN gckEVENT Event,
++ IN gcsHAL_COMPOSE_PTR Info
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Notify(
++ IN gckEVENT Event,
++ IN gctUINT32 IDs
++ );
++
++/* Event callback routine. */
++gceSTATUS
++gckEVENT_Interrupt(
++ IN gckEVENT Event,
++#if gcdMULTI_GPU
++ IN gctUINT CoreId,
++#endif
++ IN gctUINT32 IDs
++ );
++
++gceSTATUS
++gckEVENT_Dump(
++ IN gckEVENT Event
++ );
++/******************************************************************************\
++******************************* gckCOMMAND Object ******************************
++\******************************************************************************/
++
++typedef struct _gckCOMMAND * gckCOMMAND;
++
++/* Construct a new gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Construct(
++ IN gckKERNEL Kernel,
++ OUT gckCOMMAND * Command
++ );
++
++/* Destroy an gckCOMMAND object. */
++gceSTATUS
++gckCOMMAND_Destroy(
++ IN gckCOMMAND Command
++ );
++
++/* Acquire command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_EnterCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Release command queue synchronization objects. */
++gceSTATUS
++gckCOMMAND_ExitCommit(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++
++/* Start the command queue. */
++gceSTATUS
++gckCOMMAND_Start(
++ IN gckCOMMAND Command
++ );
++
++/* Stop the command queue. */
++gceSTATUS
++gckCOMMAND_Stop(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromRecovery
++ );
++
++#if gcdMULTI_GPU
++/* Commit a buffer to the command queue. */
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID,
++ IN gceCORE_3D_MASK ChipEnable
++ );
++#else
++gceSTATUS
++gckCOMMAND_Commit(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context,
++ IN gcoCMDBUF CommandBuffer,
++ IN gcsSTATE_DELTA_PTR StateDelta,
++ IN gcsQUEUE_PTR EventQueue,
++ IN gctUINT32 ProcessID
++ );
++#endif
++
++/* Reserve space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Reserve(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequestedBytes,
++ OUT gctPOINTER * Buffer,
++ OUT gctUINT32 * BufferSize
++ );
++
++/* Execute reserved space in the command buffer. */
++gceSTATUS
++gckCOMMAND_Execute(
++ IN gckCOMMAND Command,
++ IN gctUINT32 RequstedBytes
++ );
++
++/* Stall the command queue. */
++#if gcdMULTI_GPU
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower,
++ IN gceCORE_3D_MASK ChipEnable
++ );
++#else
++gceSTATUS
++gckCOMMAND_Stall(
++ IN gckCOMMAND Command,
++ IN gctBOOL FromPower
++ );
++#endif
++
++/* Attach user process. */
++gceSTATUS
++gckCOMMAND_Attach(
++ IN gckCOMMAND Command,
++ OUT gckCONTEXT * Context,
++ OUT gctSIZE_T * StateCount,
++ IN gctUINT32 ProcessID
++ );
++
++/* Detach user process. */
++gceSTATUS
++gckCOMMAND_Detach(
++ IN gckCOMMAND Command,
++ IN gckCONTEXT Context
++ );
++
++/* Dump command buffer being executed by GPU. */
++gceSTATUS
++gckCOMMAND_DumpExecutingBuffer(
++ IN gckCOMMAND Command
++ );
++
++/* Whether a kernel command buffer address. */
++gceSTATUS
++gckCOMMAND_AddressInKernelCommandBuffer(
++ IN gckCOMMAND Command,
++ IN gctUINT32 Address,
++ OUT gctBOOL *In
++ );
++
++/******************************************************************************\
++********************************* gckMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckMMU * gckMMU;
++
++/* Construct a new gckMMU object. */
++gceSTATUS
++gckMMU_Construct(
++ IN gckKERNEL Kernel,
++ IN gctSIZE_T MmuSize,
++ OUT gckMMU * Mmu
++ );
++
++/* Destroy an gckMMU object. */
++gceSTATUS
++gckMMU_Destroy(
++ IN gckMMU Mmu
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckMMU_AllocatePages(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++gceSTATUS
++gckMMU_AllocatePagesEx(
++ IN gckMMU Mmu,
++ IN gctSIZE_T PageCount,
++ IN gceSURF_TYPE Type,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckMMU_FreePages(
++ IN gckMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckMMU_SetPage(
++ IN gckMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++gceSTATUS
++gckMMU_Flush(
++ IN gckMMU Mmu,
++ IN gceSURF_TYPE Type
++ );
++
++gceSTATUS
++gckMMU_DumpPageTableEntry(
++ IN gckMMU Mmu,
++ IN gctUINT32 Address
++ );
++
++
++#if VIVANTE_PROFILER
++gceSTATUS
++gckHARDWARE_QueryProfileRegisters(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++#endif
++
++#if VIVANTE_PROFILER_CONTEXT
++gceSTATUS
++gckHARDWARE_QueryContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gctBOOL Reset,
++ IN gckCONTEXT Context,
++ OUT gcsPROFILER_COUNTERS * Counters
++ );
++
++gceSTATUS
++gckHARDWARE_UpdateContextProfile(
++ IN gckHARDWARE Hardware,
++ IN gckCONTEXT Context
++ );
++#endif
++
++#if VIVANTE_PROFILER_NEW
++gceSTATUS
++gckHARDWARE_InitProfiler(
++ IN gckHARDWARE Hardware
++ );
++#endif
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ );
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ gckHARDWARE Hardware
++ );
++
++gceSTATUS
++gckOS_DetectProcessByName(
++ IN gctCONST_POINTER Name
++ );
++
++void
++gckOS_DumpParam(
++ void
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#if gcdENABLE_VG
++#include "gc_hal_vg.h"
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_kernel_buffer.h 2016-06-19 22:11:55.237144468 +0200
+@@ -0,0 +1,225 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_buffer_h_
++#define __gc_hal_kernel_buffer_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++************************ Command Buffer and Event Objects **********************
++\******************************************************************************/
++
++/* The number of context buffers per user. */
++#define gcdCONTEXT_BUFFER_COUNT 2
++
++/* State delta record. */
++typedef struct _gcsSTATE_DELTA_RECORD * gcsSTATE_DELTA_RECORD_PTR;
++typedef struct _gcsSTATE_DELTA_RECORD
++{
++ /* State address. */
++ gctUINT address;
++
++ /* State mask. */
++ gctUINT32 mask;
++
++ /* State data. */
++ gctUINT32 data;
++}
++gcsSTATE_DELTA_RECORD;
++
++/* State delta. */
++typedef struct _gcsSTATE_DELTA
++{
++ /* For debugging: the number of delta in the order of creation. */
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ gctUINT num;
++#endif
++
++ /* Main state delta ID. Every time state delta structure gets reinitialized,
++ main ID is incremented. If main state ID overflows, all map entry IDs get
++ reinitialized to make sure there is no potential erroneous match after
++ the overflow.*/
++ gctUINT id;
++
++ /* The number of contexts pending modification by the delta. */
++ gctINT refCount;
++
++ /* Vertex element count for the delta buffer. */
++ gctUINT elementCount;
++
++ /* Number of states currently stored in the record array. */
++ gctUINT recordCount;
++
++ /* Record array; holds all modified states in gcsSTATE_DELTA_RECORD. */
++ gctUINT64 recordArray;
++
++ /* Map entry ID is used for map entry validation. If map entry ID does not
++ match the main state delta ID, the entry and the corresponding state are
++ considered not in use. */
++ gctUINT64 mapEntryID;
++ gctUINT mapEntryIDSize;
++
++ /* If the map entry ID matches the main state delta ID, index points to
++ the state record in the record array. */
++ gctUINT64 mapEntryIndex;
++
++ /* Previous and next state deltas in gcsSTATE_DELTA. */
++ gctUINT64 prev;
++ gctUINT64 next;
++}
++gcsSTATE_DELTA;
++
++/* Command buffer patch record. */
++struct _gcsPATCH
++{
++ /* Pointer within the buffer. */
++ gctUINT32_PTR pointer;
++
++ /* 32-bit data to write at the specified offset. */
++ gctUINT32 data;
++};
++
++/* List of patches for the command buffer. */
++struct _gcsPATCH_LIST
++{
++ /* Array of patch records. */
++ struct _gcsPATCH patch[1024];
++
++ /* Number of patches in the array. */
++ gctUINT count;
++
++ /* Next item in the list. */
++ struct _gcsPATCH_LIST *next;
++};
++
++/* Command buffer object. */
++struct _gcoCMDBUF
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Commit count. */
++ gctUINT count;
++
++ /* Command buffer entry and exit pipes. */
++ gcePIPE_SELECT entryPipe;
++ gcePIPE_SELECT exitPipe;
++
++ /* Feature usage flags. */
++ gctBOOL using2D;
++ gctBOOL using3D;
++ gctBOOL usingFilterBlit;
++ gctBOOL usingPalette;
++
++ /* Physical address of command buffer. Just a name. */
++ gctUINT32 physical;
++
++ /* Logical address of command buffer. */
++ gctUINT64 logical;
++
++ /* Number of bytes in command buffer. */
++ gctUINT32 bytes;
++
++ /* Start offset into the command buffer. */
++ gctUINT32 startOffset;
++
++ /* Current offset into the command buffer. */
++ gctUINT32 offset;
++
++ /* Number of free bytes in command buffer. */
++ gctUINT32 free;
++
++ /* Location of the last reserved area. */
++ gctUINT64 lastReserve;
++ gctUINT32 lastOffset;
++
++#if gcdSECURE_USER
++ /* Hint array for the current command buffer. */
++ gctUINT hintArraySize;
++ gctUINT64 hintArray;
++ gctUINT64 hintArrayTail;
++#endif
++
++#if gcmIS_DEBUG(gcdDEBUG_CODE)
++ /* Last load state command location and hardware address. */
++ gctUINT64 lastLoadStatePtr;
++ gctUINT32 lastLoadStateAddress;
++ gctUINT32 lastLoadStateCount;
++#endif
++
++ /* Completion signal. */
++ gctSIGNAL signal;
++
++ /* List of patches. */
++ struct _gcsPATCH_LIST *patchHead;
++ struct _gcsPATCH_LIST *patchTail;
++
++ /* Link to the siblings. */
++ gcoCMDBUF prev;
++ gcoCMDBUF next;
++};
++
++typedef struct _gcsQUEUE
++{
++ /* Pointer to next gcsQUEUE structure in gcsQUEUE. */
++ gctUINT64 next;
++
++ /* Event information. */
++ gcsHAL_INTERFACE iface;
++}
++gcsQUEUE;
++
++/* Event queue. */
++struct _gcoQUEUE
++{
++ /* The object. */
++ gcsOBJECT object;
++
++ /* Pointer to current event queue. */
++ gcsQUEUE_PTR head;
++ gcsQUEUE_PTR tail;
++
++ /* chunks of the records. */
++ gctPOINTER chunks;
++
++ /* List of free records. */
++ gcsQUEUE_PTR freeList;
++
++ #define gcdIN_QUEUE_RECORD_LIMIT 16
++ /* Number of records currently in queue */
++ gctUINT32 recordCount;
++};
++
++struct _gcsTEMPCMDBUF
++{
++ gctUINT32 currentByteSize;
++ gctPOINTER buffer;
++ gctBOOL inUse;
++};
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_buffer_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_mem.h 2016-06-19 22:11:55.237144468 +0200
+@@ -0,0 +1,530 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++/*
++** Include file for the local memory management.
++*/
++
++#ifndef __gc_hal_mem_h_
++#define __gc_hal_mem_h_
++#if (gcdENABLE_3D || gcdENABLE_VG)
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/*******************************************************************************
++** Usage:
++
++ The macros to declare MemPool type and functions are
++ gcmMEM_DeclareFSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareVSMemPool (Type, TypeName, Prefix)
++ gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix)
++
++ The data structures for MemPool are
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++
++ The MemPool constructor and destructor functions are
++ gcfMEM_InitFSMemPool(gcsMEM_FS_MEM_POOL *, gcoOS, gctUINT, gctUINT);
++ gcfMEM_FreeFSMemPool(gcsMEM_FS_MEM_POOL *);
++ gcfMEM_InitVSMemPool(gcsMEM_VS_MEM_POOL *, gcoOS, gctUINT, gctBOOL);
++ gcfMEM_FreeVSMemPool(gcsMEM_VS_MEM_POOL *);
++ gcfMEM_InitAFSMemPool(gcsMEM_AFS_MEM_POOL *, gcoOS, gctUINT);
++ gcfMEM_FreeAFSMemPool(gcsMEM_AFS_MEM_POOL *);
++
++ FS: for Fixed-Size data structures
++ VS: for Variable-size data structures
++ AFS: for Array of Fixed-Size data structures
++
++
++ // Example 1: For a fixed-size data structure, struct gcsNode.
++ // It is used locally in a file, so the functions are static without prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type.
++ // The second armument is the short name used in the fuctions.
++ gcmMEM_DeclareFSMemPool(struct gcsNode, Node, );
++
++ // The previous macro creates two inline functions,
++ // _AllocateNode and _FreeNode.
++
++ // In function or struct
++ gcsMEM_FS_MEM_POOL nodeMemPool;
++
++ // In function,
++ struct gcsNode * node;
++ gceSTATUS status;
++
++ // Before using the memory pool, initialize it.
++ // The second argument is the gcoOS object.
++ // The third argument is the number of data structures to allocate for each chunk.
++ status = gcfMEM_InitFSMemPool(&nodeMemPool, os, 100, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node.
++ status = _AllocateNode(nodeMemPool, &node);
++ ...
++ // Free a node.
++ _FreeNode(nodeMemPool, node);
++
++ // After using the memory pool, free it.
++ gcfMEM_FreeFSMemPool(&nodeMemPool);
++
++
++ // Example 2: For array of fixed-size data structures, struct gcsNode.
++ // It is used in several files, so the functions are extern with prefix.
++ // At top level, declear allocate and free functions.
++ // The first argument is the data type, and the second one is the short name
++ // used in the fuctions.
++ gcmMEM_DeclareAFSMemPool(struct gcsNode, NodeArray, gcfOpt);
++
++ // The previous macro creates two inline functions,
++ // gcfOpt_AllocateNodeArray and gcfOpt_FreeNodeArray.
++
++ // In function or struct
++ gcsMEM_AFS_MEM_POOL nodeArrayMemPool;
++
++ // In function,
++ struct gcsNode * nodeArray;
++ gceSTATUS status;
++
++ // Before using the array memory pool, initialize it.
++ // The second argument is the gcoOS object, the third is the number of data
++ // structures to allocate for each chunk.
++ status = gcfMEM_InitAFSMemPool(&nodeArrayMemPool, os, sizeof(struct gcsNode));
++ ...
++
++ // Allocate a node array of size 100.
++ status = gcfOpt_AllocateNodeArray(nodeArrayMemPool, &nodeArray, 100);
++ ...
++ // Free a node array.
++ gcfOpt_FreeNodeArray(&nodeArrayMemPool, nodeArray);
++
++ // After using the array memory pool, free it.
++ gcfMEM_FreeAFSMemPool(&nodeArrayMemPool);
++
++*******************************************************************************/
++
++/*******************************************************************************
++** To switch back to use gcoOS_Allocate and gcoOS_Free, add
++** #define USE_LOCAL_MEMORY_POOL 0
++** before including this file.
++*******************************************************************************/
++#ifndef USE_LOCAL_MEMORY_POOL
++/*
++ USE_LOCAL_MEMORY_POOL
++
++ This define enables the local memory management to improve performance.
++*/
++#define USE_LOCAL_MEMORY_POOL 1
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Structures
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL;
++ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL;
++ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL;
++#else
++ typedef gcoOS gcsMEM_FS_MEM_POOL;
++ typedef gcoOS gcsMEM_VS_MEM_POOL;
++ typedef gcoOS gcsMEM_AFS_MEM_POOL;
++#endif
++
++/*******************************************************************************
++** Memory Pool Macros
++*******************************************************************************/
++#if USE_LOCAL_MEMORY_POOL
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ return(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_FSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName##List( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * FirstPointer, \
++ Type * LastPointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x FirstPointer=0x%x LastPointer=0x%x", MemPool, FirstPointer, LastPointer); \
++ status = gcfMEM_FSMemPoolFreeAList(MemPool, (gctPOINTER) FirstPointer, (gctPOINTER) LastPointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status;\
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++ Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pinter); \
++ status = gcfMEM_VSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcfMEM_AFSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#else
++
++#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type ** Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_FS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ status = gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Size \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Size, \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Size); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_VS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++
++#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \
++gceSTATUS \
++Prefix##_Allocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ status = gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer); \
++ gcmFOOTER(); \
++ return status; \
++} \
++ \
++gceSTATUS \
++Prefix##_CAllocate##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type ** Pointer, \
++ gctUINT Count \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \
++ gcmERR_RETURN(gcoOS_Allocate(MemPool, \
++ Count * gcmSIZEOF(Type), \
++ (gctPOINTER *) Pointer)); \
++ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \
++ gcmFOOTER(); \
++ return gcvSTATUS_OK; \
++} \
++ \
++gceSTATUS \
++Prefix##_Free##TypeName( \
++ gcsMEM_AFS_MEM_POOL MemPool, \
++ Type * Pointer \
++ ) \
++{ \
++ gceSTATUS status; \
++ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \
++ status = gcmOS_SAFE_FREE(MemPool, Pointer); \
++ gcmFOOTER(); \
++ return status; \
++}
++#endif
++
++/*******************************************************************************
++** Memory Pool Data Functions
++*******************************************************************************/
++gceSTATUS
++gcfMEM_InitFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeFSMemPool(
++ IN gcsMEM_FS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolGetANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeANode(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_FSMemPoolFreeAList(
++ IN gcsMEM_FS_MEM_POOL MemPool,
++ IN gctPOINTER FirstNode,
++ IN gctPOINTER LastNode
++ );
++
++gceSTATUS
++gcfMEM_InitVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool,
++ IN gcoOS OS,
++ IN gctUINT BlockSize,
++ IN gctBOOL RecycleFreeNode
++ );
++
++gceSTATUS
++gcfMEM_FreeVSMemPool(
++ IN gcsMEM_VS_MEM_POOL * MemPool
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolGetANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctUINT Size,
++ IN gctUINT Alignment,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_VSMemPoolFreeANode(
++ IN gcsMEM_VS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++gceSTATUS
++gcfMEM_InitAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool,
++ IN gcoOS OS,
++ IN gctUINT NodeCount,
++ IN gctUINT NodeSize
++ );
++
++gceSTATUS
++gcfMEM_FreeAFSMemPool(
++ IN gcsMEM_AFS_MEM_POOL *MemPool
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolGetANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctUINT Count,
++ OUT gctPOINTER * Node
++ );
++
++gceSTATUS
++gcfMEM_AFSMemPoolFreeANode(
++ IN gcsMEM_AFS_MEM_POOL MemPool,
++ IN gctPOINTER Node
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* (gcdENABLE_3D || gcdENABLE_VG) */
++#endif /* __gc_hal_mem_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,1271 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++#ifndef __gc_hal_options_h_
++#define __gc_hal_options_h_
++
++/*
++ gcdSECURITY
++
++*/
++#ifndef gcdSECURITY
++# define gcdSECURITY 0
++#endif
++
++/*
++ gcdPRINT_VERSION
++
++ Print HAL version.
++*/
++#ifndef gcdPRINT_VERSION
++# define gcdPRINT_VERSION 0
++#endif
++
++/*
++ USE_NEW_LINUX_SIGNAL
++
++ This define enables the Linux kernel signaling between kernel and user.
++*/
++#ifndef USE_NEW_LINUX_SIGNAL
++# define USE_NEW_LINUX_SIGNAL 0
++#endif
++
++/*
++ VIVANTE_PROFILER
++
++ This define enables the profiler.
++*/
++#ifndef VIVANTE_PROFILER
++# define VIVANTE_PROFILER 1
++#endif
++
++/*
++ VIVANTE_PROFILER_CONTEXT
++
++ This define enables the profiler according each context.
++*/
++#ifndef VIVANTE_PROFILER_CONTEXT
++# define VIVANTE_PROFILER_CONTEXT 1
++#endif
++
++#ifndef VIVANTE_PROFILER_PERDRAW
++# define VIVANTE_PROFILER_PERDRAW 0
++#endif
++
++#ifndef VIVANTE_PROFILER_NEW
++# define VIVANTE_PROFILER_NEW 0
++#endif
++
++#ifndef VIVANTE_PROFILER_PM
++# define VIVANTE_PROFILER_PM 1
++#endif
++/*
++ gcdUSE_VG
++
++ Enable VG HAL layer (only for GC350).
++*/
++#ifndef gcdUSE_VG
++# define gcdUSE_VG 0
++#endif
++
++/*
++ USE_SW_FB
++
++ Set to 1 if the frame buffer memory cannot be accessed by the GPU.
++*/
++#ifndef USE_SW_FB
++# define USE_SW_FB 0
++#endif
++
++/*
++ PROFILE_HAL_COUNTERS
++
++ This define enables HAL counter profiling support. HW and SHADER
++ counter profiling depends on this.
++*/
++#ifndef PROFILE_HAL_COUNTERS
++# define PROFILE_HAL_COUNTERS 1
++#endif
++
++/*
++ PROFILE_HW_COUNTERS
++
++ This define enables HW counter profiling support.
++*/
++#ifndef PROFILE_HW_COUNTERS
++# define PROFILE_HW_COUNTERS 1
++#endif
++
++/*
++ PROFILE_SHADER_COUNTERS
++
++ This define enables SHADER counter profiling support.
++*/
++#ifndef PROFILE_SHADER_COUNTERS
++# define PROFILE_SHADER_COUNTERS 1
++#endif
++
++/*
++ COMMAND_PROCESSOR_VERSION
++
++ The version of the command buffer and task manager.
++*/
++#define COMMAND_PROCESSOR_VERSION 1
++
++/*
++ gcdDUMP_KEY
++
++ Set this to a string that appears in 'cat /proc/<pid>/cmdline'. E.g. 'camera'.
++ HAL will create dumps for the processes matching this key.
++*/
++#ifndef gcdDUMP_KEY
++# define gcdDUMP_KEY "process"
++#endif
++
++/*
++ gcdDUMP_PATH
++
++ The dump file location. Some processes cannot write to the sdcard.
++ Try apps' data dir, e.g. /data/data/com.android.launcher
++*/
++#ifndef gcdDUMP_PATH
++#if defined(ANDROID)
++# define gcdDUMP_PATH "/mnt/sdcard/"
++#else
++# define gcdDUMP_PATH "./"
++#endif
++#endif
++
++/*
++ gcdDUMP
++
++ When set to 1, a dump of all states and memory uploads, as well as other
++ hardware related execution will be printed to the debug console. This
++ data can be used for playing back applications.
++*/
++#ifndef gcdDUMP
++# define gcdDUMP 0
++#endif
++
++/*
++ gcdDUMP_API
++
++ When set to 1, a high level dump of the EGL and GL/VG APs's are
++ captured.
++*/
++#ifndef gcdDUMP_API
++# define gcdDUMP_API 0
++#endif
++
++
++
++/*
++ gcdDEBUG_OPTION
++ When set to 1, the debug options are enabled. We must set other MACRO to enable
++ sub case.
++*/
++#ifndef gcdDEBUG_OPTION
++# define gcdDEBUG_OPTION 0
++
++#if gcdDEBUG_OPTION
++/*
++ gcdDEBUG_OPTION_KEY
++ The process name of debug application.
++*/
++#ifndef gcdDEBUG_OPTION_KEY
++# define gcdDEBUG_OPTION_KEY "process"
++# endif
++/*
++ gcdDEBUG_OPTION_NO_GL_DRAWS
++ When set to 1, all glDrawArrays and glDrawElements will be skip.
++*/
++#ifndef gcdDEBUG_OPTION_NO_GL_DRAWS
++# define gcdDEBUG_OPTION_NO_GL_DRAWS 0
++# endif
++/*
++ gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES
++ When set to 1, all DrawPrimitives will be skip.
++*/
++#ifndef gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES
++# define gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES 0
++# endif
++/*
++ gcdDEBUG_OPTION_SKIP_SWAP
++ When set to 1, just one out of gcdDEBUG_OPTION_SKIP_FRAMES(such as 1/10) eglSwapBuffers will be resolve,
++ others skip.
++*/
++#ifndef gcdDEBUG_OPTION_SKIP_SWAP
++# define gcdDEBUG_OPTION_SKIP_SWAP 0
++# define gcdDEBUG_OPTION_SKIP_FRAMES 10
++# endif
++/*
++ gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET
++ When set to 1, the format of render target will force to RGB565.
++*/
++#ifndef gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET
++# define gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET 0
++# endif
++/*
++ gcdDEBUG_OPTION_NONE_TEXTURE
++ When set to 1, the type of texture will be set to AQ_TEXTURE_SAMPLE_MODE_TYPE_NONE.
++*/
++#ifndef gcdDEBUG_OPTION_NONE_TEXTURE
++# define gcdDEBUG_OPTION_NONE_TEXTURE 0
++# endif
++/*
++ gcdDEBUG_OPTION_NONE_DEPTH
++ When set to 1, the depth format of surface will be set to gcvSURF_UNKNOWN.
++*/
++#ifndef gcdDEBUG_OPTION_NONE_DEPTH
++# define gcdDEBUG_OPTION_NONE_DEPTH 0
++# endif
++
++# endif
++#endif
++
++/*
++ gcdDUMP_SWAP_PER_DRAW
++
++ When set to 1, dump swap command for every single draw to make simulation comparison happy.
++ Only valid for ES3 driver for now.
++*/
++#ifndef gcdDUMP_SWAP_PER_DRAW
++# define gcdDUMP_SWAP_PER_DRAW 0
++#endif
++
++/*
++ gcdDUMP_FRAMERATE
++ When set to a value other than zero, averaqe frame rate will be dumped.
++ The value set is the starting frame that the average will be calculated.
++ This is needed because sometimes first few frames are too slow to be included
++ in the average. Frame count starts from 1.
++*/
++#ifndef gcdDUMP_FRAMERATE
++# define gcdDUMP_FRAMERATE 0
++#endif
++
++/*
++ gcdENABLE_FSCALE_VAL_ADJUST
++ When non-zero, FSCALE_VAL when gcvPOWER_ON can be adjusted externally.
++ */
++#ifndef gcdENABLE_FSCALE_VAL_ADJUST
++# define gcdENABLE_FSCALE_VAL_ADJUST 1
++#endif
++
++/*
++ gcdDUMP_IN_KERNEL
++
++ When set to 1, all dumps will happen in the kernel. This is handy if
++ you want the kernel to dump its command buffers as well and the data
++ needs to be in sync.
++*/
++#ifndef gcdDUMP_IN_KERNEL
++# define gcdDUMP_IN_KERNEL 0
++#endif
++
++/*
++ gcdDUMP_COMMAND
++
++ When set to non-zero, the command queue will dump all incoming command
++ and context buffers as well as all other modifications to the command
++ queue.
++*/
++#ifndef gcdDUMP_COMMAND
++# define gcdDUMP_COMMAND 0
++#endif
++
++/*
++ gcdDUMP_2D
++
++ When set to non-zero, it will dump the 2D command and surface.
++*/
++#ifndef gcdDUMP_2D
++# define gcdDUMP_2D 0
++#endif
++
++/*
++ gcdDUMP_FRAME_TGA
++
++ When set to a value other than 0, a dump of the frame specified by the value,
++ will be done into frame.tga. Frame count starts from 1.
++ */
++#ifndef gcdDUMP_FRAME_TGA
++# define gcdDUMP_FRAME_TGA 0
++#endif
++/*
++ gcdNULL_DRIVER
++
++ Set to 1 for infinite speed hardware.
++ Set to 2 for bypassing the HAL.
++ Set to 3 for bypassing the drivers.
++*/
++#ifndef gcdNULL_DRIVER
++# define gcdNULL_DRIVER 0
++#endif
++
++/*
++ gcdENABLE_TIMEOUT_DETECTION
++
++ Enable timeout detection.
++*/
++#ifndef gcdENABLE_TIMEOUT_DETECTION
++# define gcdENABLE_TIMEOUT_DETECTION 0
++#endif
++
++/*
++ gcdCMD_BUFFER_SIZE
++
++ Number of bytes in a command buffer.
++*/
++#ifndef gcdCMD_BUFFER_SIZE
++# define gcdCMD_BUFFER_SIZE (128 << 10)
++#endif
++
++/*
++ gcdCMD_BUFFERS
++
++ Number of command buffers to use per client.
++*/
++#ifndef gcdCMD_BUFFERS
++# define gcdCMD_BUFFERS 2
++#endif
++
++/*
++ gcdMAX_CMD_BUFFERS
++
++ Maximum number of command buffers to use per client.
++*/
++#ifndef gcdMAX_CMD_BUFFERS
++# define gcdMAX_CMD_BUFFERS 8
++#endif
++
++/*
++ gcdCOMMAND_QUEUES
++
++ Number of command queues in the kernel.
++*/
++#ifndef gcdCOMMAND_QUEUES
++# define gcdCOMMAND_QUEUES 2
++#endif
++
++/*
++ gcdPOWER_CONTROL_DELAY
++
++ The delay in milliseconds required to wait until the GPU has woke up
++ from a suspend or power-down state. This is system dependent because
++ the bus clock also needs to stabalize.
++*/
++#ifndef gcdPOWER_CONTROL_DELAY
++# define gcdPOWER_CONTROL_DELAY 0
++#endif
++
++/*
++ gcdMIRROR_PAGETABLE
++
++ Enable it when GPUs with old MMU and new MMU exist at same SoC. It makes
++ each GPU use same virtual address to access same physical memory.
++*/
++#ifndef gcdMIRROR_PAGETABLE
++# define gcdMIRROR_PAGETABLE 0
++#endif
++
++/*
++ gcdMMU_SIZE
++
++ Size of the MMU page table in bytes. Each 4 bytes can hold 4kB worth of
++ virtual data.
++*/
++#ifndef gcdMMU_SIZE
++#if gcdMIRROR_PAGETABLE
++# define gcdMMU_SIZE 0x200000
++#else
++# define gcdMMU_SIZE (2048 << 10)
++#endif
++#endif
++
++/*
++ gcdSECURE_USER
++
++ Use logical addresses instead of physical addresses in user land. In
++ this case a hint table is created for both command buffers and context
++ buffers, and that hint table will be used to patch up those buffers in
++ the kernel when they are ready to submit.
++*/
++#ifndef gcdSECURE_USER
++# define gcdSECURE_USER 0
++#endif
++
++/*
++ gcdSECURE_CACHE_SLOTS
++
++ Number of slots in the logical to DMA address cache table. Each time a
++ logical address needs to be translated into a DMA address for the GPU,
++ this cache will be walked. The replacement scheme is LRU.
++*/
++#ifndef gcdSECURE_CACHE_SLOTS
++# define gcdSECURE_CACHE_SLOTS 1024
++#endif
++
++/*
++ gcdSECURE_CACHE_METHOD
++
++ Replacement scheme used for Secure Cache. The following options are
++ available:
++
++ gcdSECURE_CACHE_LRU
++ A standard LRU cache.
++
++ gcdSECURE_CACHE_LINEAR
++ A linear walker with the idea that an application will always
++ render the scene in a similar way, so the next entry in the
++ cache should be a hit most of the time.
++
++ gcdSECURE_CACHE_HASH
++ A 256-entry hash table.
++
++ gcdSECURE_CACHE_TABLE
++ A simple cache but with potential of a lot of cache replacement.
++*/
++#ifndef gcdSECURE_CACHE_METHOD
++# define gcdSECURE_CACHE_METHOD gcdSECURE_CACHE_HASH
++#endif
++
++/*
++ gcdREGISTER_ACCESS_FROM_USER
++
++ Set to 1 to allow IOCTL calls to get through from user land. This
++ should only be in debug or development drops.
++*/
++#ifndef gcdREGISTER_ACCESS_FROM_USER
++# define gcdREGISTER_ACCESS_FROM_USER 1
++#endif
++
++/*
++ gcdHEAP_SIZE
++
++ Set the allocation size for the internal heaps. Each time a heap is
++ full, a new heap will be allocated with this minmimum amount of bytes.
++ The bigger this size, the fewer heaps there are to allocate, the better
++ the performance. However, heaps won't be freed until they are
++ completely free, so there might be some more memory waste if the size is
++ too big.
++*/
++#ifndef gcdHEAP_SIZE
++# define gcdHEAP_SIZE (64 << 10)
++#endif
++
++/*
++ gcdPOWER_SUSPEND_WHEN_IDLE
++
++ Set to 1 to make GPU enter gcvPOWER_SUSPEND when idle detected,
++ otherwise GPU will enter gcvPOWER_IDLE.
++*/
++#ifndef gcdPOWER_SUSPEND_WHEN_IDLE
++# define gcdPOWER_SUSPEND_WHEN_IDLE 1
++#endif
++
++#ifndef gcdFPGA_BUILD
++# define gcdFPGA_BUILD 0
++#endif
++
++/*
++ gcdGPU_TIMEOUT
++
++ This define specified the number of milliseconds the system will wait
++ before it broadcasts the GPU is stuck. In other words, it will define
++ the timeout of any operation that needs to wait for the GPU.
++
++ If the value is 0, no timeout will be checked for.
++*/
++#ifndef gcdGPU_TIMEOUT
++#if gcdFPGA_BUILD
++# define gcdGPU_TIMEOUT 0
++# define gcdGPU_2D_TIMEOUT 0
++# else
++# define gcdGPU_TIMEOUT 20000
++# define gcdGPU_2D_TIMEOUT 4000
++# endif
++#endif
++
++/*
++ gcdGPU_ADVANCETIMER
++
++ it is advance timer.
++*/
++#ifndef gcdGPU_ADVANCETIMER
++# define gcdGPU_ADVANCETIMER 250
++#endif
++
++/*
++ gcdSTATIC_LINK
++
++ This define disalbes static linking;
++*/
++#ifndef gcdSTATIC_LINK
++# define gcdSTATIC_LINK 0
++#endif
++
++/*
++ gcdUSE_NEW_HEAP
++
++ Setting this define to 1 enables new heap.
++*/
++#ifndef gcdUSE_NEW_HEAP
++# define gcdUSE_NEW_HEAP 0
++#endif
++
++/*
++ gcdCMD_NO_2D_CONTEXT
++
++ This define enables no-context 2D command buffer.
++*/
++#ifndef gcdCMD_NO_2D_CONTEXT
++# define gcdCMD_NO_2D_CONTEXT 1
++#endif
++
++/*
++ gcdENABLE_BUFFER_ALIGNMENT
++
++ When enabled, video memory is allocated with atleast 16KB aligment
++ between multiple sub-buffers.
++*/
++#ifndef gcdENABLE_BUFFER_ALIGNMENT
++# define gcdENABLE_BUFFER_ALIGNMENT 1
++#endif
++
++/*
++ gcdENABLE_BANK_ALIGNMENT
++
++ When enabled, video memory is allocated bank aligned. The vendor can modify
++ _GetSurfaceBankAlignment() and _GetBankOffsetBytes() to define how
++ different types of allocations are bank and channel aligned.
++ When disabled (default), no bank alignment is done.
++*/
++#ifndef gcdENABLE_BANK_ALIGNMENT
++# define gcdENABLE_BANK_ALIGNMENT 0
++#endif
++
++/*
++ gcdBANK_BIT_START
++
++ Specifies the start bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_START
++# define gcdBANK_BIT_START 12
++#endif
++
++/*
++ gcdBANK_BIT_END
++
++ Specifies the end bit of the bank (inclusive).
++*/
++#ifndef gcdBANK_BIT_END
++# define gcdBANK_BIT_END 14
++#endif
++
++/*
++ gcdBANK_CHANNEL_BIT
++
++ When set, video memory when allocated bank aligned is allocated such that
++ render and depth buffer addresses alternate on the channel bit specified.
++ This option has an effect only when gcdENABLE_BANK_ALIGNMENT is enabled.
++ When disabled (default), no alteration is done.
++*/
++#ifndef gcdBANK_CHANNEL_BIT
++# define gcdBANK_CHANNEL_BIT 7
++#endif
++
++/*
++ gcdDYNAMIC_SPEED
++
++ When non-zero, it informs the kernel driver to use the speed throttling
++ broadcasting functions to inform the system the GPU should be spet up or
++ slowed down. It will send a broadcast for slowdown each "interval"
++ specified by this define in milliseconds
++ (gckOS_BroadcastCalibrateSpeed).
++*/
++#ifndef gcdDYNAMIC_SPEED
++# define gcdDYNAMIC_SPEED 2000
++#endif
++
++/*
++ gcdDYNAMIC_EVENT_THRESHOLD
++
++ When non-zero, it specifies the maximum number of available events at
++ which the kernel driver will issue a broadcast to speed up the GPU
++ (gckOS_BroadcastHurry).
++*/
++#ifndef gcdDYNAMIC_EVENT_THRESHOLD
++# define gcdDYNAMIC_EVENT_THRESHOLD 5
++#endif
++
++/*
++ gcdENABLE_PROFILING
++
++ Enable profiling macros.
++*/
++#ifndef gcdENABLE_PROFILING
++# define gcdENABLE_PROFILING 0
++#endif
++
++/*
++ gcdENABLE_128B_MERGE
++
++ Enable 128B merge for the BUS control.
++*/
++#ifndef gcdENABLE_128B_MERGE
++# define gcdENABLE_128B_MERGE 0
++#endif
++
++/*
++ gcdFRAME_DB
++
++ When non-zero, it specified the number of frames inside the frame
++ database. The frame DB will collect per-frame timestamps and hardware
++ counters.
++*/
++#ifndef gcdFRAME_DB
++# define gcdFRAME_DB 0
++# define gcdFRAME_DB_RESET 0
++# define gcdFRAME_DB_NAME "/var/log/frameDB.log"
++#endif
++
++/*
++ gcdDISABLE_CORES_2D3D
++ disable the 2D3D cores for 2D openVG
++*/
++#ifndef gcdDISABLE_CORES_2D3D
++# define gcdDISABLE_CORES_2D3D 0
++#endif
++
++/*
++ gcdPAGED_MEMORY_CACHEABLE
++
++ When non-zero, paged memory will be cacheable.
++
++ Normally, driver will detemines whether a video memory
++ is cacheable or not. When cacheable is not neccessary,
++ it will be writecombine.
++
++ This option is only for those SOC which can't enable
++ writecombine without enabling cacheable.
++*/
++#ifndef gcdPAGED_MEMORY_CACHEABLE
++# define gcdPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_CACHEABLE
++
++ When non-zero, non paged memory will be cacheable.
++*/
++#ifndef gcdNONPAGED_MEMORY_CACHEABLE
++# define gcdNONPAGED_MEMORY_CACHEABLE 0
++#endif
++
++/*
++ gcdNONPAGED_MEMORY_BUFFERABLE
++
++ When non-zero, non paged memory will be bufferable.
++ gcdNONPAGED_MEMORY_BUFFERABLE and gcdNONPAGED_MEMORY_CACHEABLE
++ can't be set 1 at same time
++*/
++#ifndef gcdNONPAGED_MEMORY_BUFFERABLE
++# define gcdNONPAGED_MEMORY_BUFFERABLE 1
++#endif
++
++/*
++ gcdENABLE_INFINITE_SPEED_HW
++ enable the Infinte HW , this is for 2D openVG
++*/
++#ifndef gcdENABLE_INFINITE_SPEED_HW
++# define gcdENABLE_INFINITE_SPEED_HW 0
++#endif
++
++/*
++ gcdMULTI_GPU
++
++ Enable/disable multi-GPU support.
++ 0 : Disable multi-GPU support
++ 1 : Enable one of the 3D cores
++ [2..X] : Number of 3D GPU Cores
++*/
++#ifndef gcdMULTI_GPU
++# define gcdMULTI_GPU 0
++#endif
++
++/*
++ gcdMULTI_GPU_AFFINITY
++
++ Enable/disable the binding of a context to one GPU
++*/
++#ifndef gcdMULTI_GPU_AFFINITY
++# define gcdMULTI_GPU_AFFINITY 0
++#endif
++
++/*
++ gcdPOWEROFF_TIMEOUT
++
++ When non-zero, GPU will power off automatically from
++ idle state, and gcdPOWEROFF_TIMEOUT is also the default
++ timeout in milliseconds.
++ */
++#ifndef gcdPOWEROFF_TIMEOUT
++# define gcdPOWEROFF_TIMEOUT 300
++#endif
++
++/*
++ QNX_SINGLE_THREADED_DEBUGGING
++*/
++#ifndef QNX_SINGLE_THREADED_DEBUGGING
++# define QNX_SINGLE_THREADED_DEBUGGING 0
++#endif
++
++/*
++ gcdRENDER_THREADS
++
++ Number of render threads. Make it zero, and there will be no render
++ threads.
++*/
++#ifndef gcdRENDER_THREADS
++# define gcdRENDER_THREADS 0
++#endif
++
++/*
++ gcdSMP
++
++ This define enables SMP support.
++
++ Currently, it only works on Linux/Android,
++ Kbuild will config it according to whether
++ CONFIG_SMP is set.
++
++*/
++#ifndef gcdSMP
++#ifdef __APPLE__
++# define gcdSMP 1
++#else
++# define gcdSMP 0
++#endif
++#endif
++
++/*
++ gcdSHARED_RESOLVE_BUFFER_ENABLED
++
++ Use shared resolve buffer for all app buffers.
++*/
++#ifndef gcdSHARED_RESOLVE_BUFFER_ENABLED
++# define gcdSHARED_RESOLVE_BUFFER_ENABLED 0
++#endif
++
++/*
++ gcdUSE_TRIANGLE_STRIP_PATCH
++ */
++#ifndef gcdUSE_TRIANGLE_STRIP_PATCH
++# define gcdUSE_TRIANGLE_STRIP_PATCH 1
++#endif
++
++/*
++ gcdENABLE_OUTER_CACHE_PATCH
++
++ Enable the outer cache patch.
++*/
++#ifndef gcdENABLE_OUTER_CACHE_PATCH
++# define gcdENABLE_OUTER_CACHE_PATCH 0
++#endif
++
++/*
++ gcdPROCESS_ADDRESS_SPACE
++
++ When non-zero, every process which attaches to galcore has its own GPU
++ address space, size of which is gcdPROCESS_ADDRESS_SPACE_SIZE.
++*/
++#ifndef gcdPROCESS_ADDRESS_SPACE
++# define gcdPROCESS_ADDRESS_SPACE 0
++# define gcdPROCESS_ADDRESS_SPACE_SIZE 0x80000000
++#endif
++
++/*
++ gcdSHARED_PAGETABLE
++
++ When non-zero, multiple GPUs in one chip with same MMU use
++ one shared pagetable. So that when accessing same surface,
++ they can use same GPU virtual address.
++*/
++#ifndef gcdSHARED_PAGETABLE
++# define gcdSHARED_PAGETABLE !gcdPROCESS_ADDRESS_SPACE
++#endif
++
++#ifndef gcdUSE_PVR
++# define gcdUSE_PVR 1
++#endif
++
++/*
++ gcdSMALL_BLOCK_SIZE
++
++ When non-zero, a part of VIDMEM will be reserved for requests
++ whose requesting size is less than gcdSMALL_BLOCK_SIZE.
++
++ For Linux, it's the size of a page. If this requeset fallbacks
++ to gcvPOOL_CONTIGUOUS or gcvPOOL_VIRTUAL, memory will be wasted
++ because they allocate a page at least.
++*/
++#ifndef gcdSMALL_BLOCK_SIZE
++# define gcdSMALL_BLOCK_SIZE 4096
++# define gcdRATIO_FOR_SMALL_MEMORY 32
++#endif
++
++/*
++ gcdCONTIGUOUS_SIZE_LIMIT
++ When non-zero, size of video node from gcvPOOL_CONTIGUOUS is
++ limited by gcdCONTIGUOUS_SIZE_LIMIT.
++*/
++#ifndef gcdCONTIGUOUS_SIZE_LIMIT
++# define gcdCONTIGUOUS_SIZE_LIMIT 0
++#endif
++
++/*
++ gcdLINK_QUEUE_SIZE
++
++ When non-zero, driver maintains a queue to record information of
++ latest lined context buffer and command buffer. Data in this queue
++ is be used to debug.
++*/
++#ifndef gcdLINK_QUEUE_SIZE
++# define gcdLINK_QUEUE_SIZE 5
++#endif
++
++/* gcdALPHA_KILL_IN_SHADER
++
++ Enable alpha kill inside the shader. This will be set automatically by the
++ HAL if certain states match a criteria.
++*/
++#ifndef gcdALPHA_KILL_IN_SHADER
++# define gcdALPHA_KILL_IN_SHADER 1
++#endif
++
++
++
++/*
++ gcdDVFS
++
++ When non-zero, software will make use of dynamic voltage and
++ frequency feature.
++ */
++#ifndef gcdDVFS
++# define gcdDVFS 0
++# define gcdDVFS_ANAYLSE_WINDOW 4
++# define gcdDVFS_POLLING_TIME (gcdDVFS_ANAYLSE_WINDOW * 4)
++#endif
++
++#ifndef gcdSYNC
++# define gcdSYNC 1
++#endif
++
++#ifndef gcdSHADER_SRC_BY_MACHINECODE
++# define gcdSHADER_SRC_BY_MACHINECODE 1
++#endif
++
++#ifndef gcdGLB27_SHADER_REPLACE_OPTIMIZATION
++# define gcdGLB27_SHADER_REPLACE_OPTIMIZATION 1
++#endif
++
++/*
++ gcdSTREAM_OUT_BUFFER
++
++ Enable suppport for the secondary stream out buffer.
++*/
++#ifndef gcdSTREAM_OUT_BUFFER
++# define gcdSTREAM_OUT_BUFFER 0
++# define gcdSTREAM_OUT_NAIVE_SYNC 0
++#endif
++
++/*
++ gcdUSE_HARDWARE_CONFIGURATION_TABLES
++
++ Enable the use of hardware configuration tables,
++ instead of query hardware and determine the features.
++*/
++#ifndef gcdUSE_HARDWARE_CONFIGURATION_TABLES
++# define gcdUSE_HARDWARE_CONFIGURATION_TABLES 0
++#endif
++
++/*
++ gcdSUPPORT_SWAP_RECTANGLE
++
++ Support swap with a specific rectangle.
++
++ Set the rectangle with eglSetSwapRectangleVIV api.
++ Android only.
++*/
++#ifndef gcdSUPPORT_SWAP_RECTANGLE
++# define gcdSUPPORT_SWAP_RECTANGLE 1
++#endif
++
++/*
++ gcdGPU_LINEAR_BUFFER_ENABLED
++
++ Use linear buffer for GPU apps so HWC can do 2D composition.
++ Android only.
++*/
++#ifndef gcdGPU_LINEAR_BUFFER_ENABLED
++# define gcdGPU_LINEAR_BUFFER_ENABLED 1
++#endif
++
++/*
++ gcdENABLE_RENDER_INTO_WINDOW
++
++ Enable Render-Into-Window (ie, No-Resolve) feature on android.
++ NOTE that even if enabled, it still depends on hardware feature and
++ android application behavior. When hardware feature or application
++ behavior can not support render into window mode, it will fail back
++ to normal mode.
++ When Render-Into-Window is finally used, window back buffer of android
++ applications will be allocated matching render target tiling format.
++ Otherwise buffer tiling is decided by the above option
++ 'gcdGPU_LINEAR_BUFFER_ENABLED'.
++ Android only for now.
++*/
++#ifndef gcdENABLE_RENDER_INTO_WINDOW
++# define gcdENABLE_RENDER_INTO_WINDOW 1
++#endif
++
++/*
++ gcdENABLE_RENDER_INTO_WINDOW_WITH_FC
++
++ Enable Direct-rendering (ie, No-Resolve) with tile status.
++ This is expremental and in development stage.
++ This will dynamically check if color compression is available.
++*/
++#ifndef gcdENABLE_RENDER_INTO_WINDOW_WITH_FC
++# define gcdENABLE_RENDER_INTO_WINDOW_WITH_FC 1
++#endif
++
++/*
++ gcdENABLE_BLIT_BUFFER_PRESERVE
++
++ Render-Into-Window (ie, No-Resolve) does not include preserved swap
++ behavior. This feature can enable buffer preserve in No-Resolve mode.
++ When enabled, previous buffer (may be part of ) will be resolve-blitted
++ to current buffer.
++*/
++#ifndef gcdENABLE_BLIT_BUFFER_PRESERVE
++# define gcdENABLE_BLIT_BUFFER_PRESERVE 1
++#endif
++
++/*
++ gcdANDROID_NATIVE_FENCE_SYNC
++
++ Enable android native fence sync. It is introduced since jellybean-4.2.
++ Depends on linux kernel option: CONFIG_SYNC.
++
++ 0: Disabled
++ 1: Build framework for native fence sync feature, and EGL extension
++ 2: Enable async swap buffers for client
++ * Native fence sync for client 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for layer in compositor side.
++ 3. Enable async hwcomposer composition.
++ * 'releaseFenceFd' for layer in compositor side, which is native
++ fence sync when client 'dequeueBuffer'
++ * Native fence sync for compositor 'queueBuffer' in EGL, which is
++ 'acquireFenceFd' for framebuffer target for DC
++ */
++#ifndef gcdANDROID_NATIVE_FENCE_SYNC
++# define gcdANDROID_NATIVE_FENCE_SYNC 0
++#endif
++
++/*
++ gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC
++
++ Enable implicit android native buffer sync.
++
++ For non-HW_RENDER buffer, CPU (or other hardware) and GPU can access
++ the buffer at the same time. This is to add implicit synchronization
++ between CPU (or the hardware) and GPU.
++
++ Eventually, please do not use implicit native buffer sync, but use
++ "fence sync" or "android native fence sync" instead in libgui, which
++ can be enabled in frameworks/native/libs/gui/Android.mk. This kind
++ of synchronization should be done by app but not driver itself.
++
++ Please disable this option when either "fence sync" or
++ "android native fence sync" is enabled.
++ */
++#ifndef gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC
++# define gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC 1
++#endif
++
++/*
++ * Implicit native buffer sync is not needed when ANDROID_native_fence_sync
++ * is available.
++ */
++#if gcdANDROID_NATIVE_FENCE_SYNC
++# undef gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC
++# define gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC 0
++#endif
++
++/*
++ gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++
++ Enable source surface address adjust when composition on android.
++ Android only.
++*/
++#ifndef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 1
++#endif
++
++/*
++ gcdUSE_WCLIP_PATCH
++
++ Enable wclipping patch.
++*/
++#ifndef gcdUSE_WCLIP_PATCH
++# define gcdUSE_WCLIP_PATCH 1
++#endif
++
++#ifndef gcdUSE_NPOT_PATCH
++# define gcdUSE_NPOT_PATCH 1
++#endif
++
++/*
++ gcd3DBLIT
++
++ TODO: Should be replaced by feature bit if available.
++*/
++#ifndef gcd3DBLIT
++# define gcd3DBLIT 0
++#endif
++
++/*
++ gcdINTERNAL_COMMENT
++
++ Wrap internal comment, content wrapped by it and the macor itself
++ will be removed in release driver.
++*/
++#ifndef gcdINTERNAL_COMMENT
++# define gcdINTERNAL_COMMENT 1
++#endif
++
++/*
++ gcdRTT_DISABLE_FC
++
++ Disable RTT FC support. For test only.
++*/
++#ifndef gcdRTT_DISABLE_FC
++# define gcdRTT_DISABLE_FC 0
++#endif
++
++/*
++ gcdFORCE_MIPMAP
++
++ Force generate mipmap for texture.
++*/
++#ifndef gcdFORCE_MIPMAP
++# define gcdFORCE_MIPMAP 0
++#endif
++
++/*
++ gcdFORCE_BILINEAR
++
++ Force bilinear for mipfilter.
++*/
++#ifndef gcdFORCE_BILINEAR
++# define gcdFORCE_BILINEAR 1
++#endif
++
++/*
++ gcdBINARY_TRACE
++
++ When non-zero, binary trace will be generated.
++
++ When gcdBINARY_TRACE_FILE_SIZE is non-zero, binary trace buffer will
++ be written to a file which size is limited to
++ gcdBINARY_TRACE_FILE_SIZE.
++*/
++#ifndef gcdBINARY_TRACE
++# define gcdBINARY_TRACE 0
++# define gcdBINARY_TRACE_FILE_SIZE 0
++#endif
++
++#ifndef gcdMOVG
++# define gcdMOVG 0
++#if gcdMOVG
++# define GC355_PROFILER 1
++# endif
++# define gcdENABLE_TS_DOUBLE_BUFFER 1
++#else
++#if gcdMOVG
++# define GC355_PROFILER 1
++# define gcdENABLE_TS_DOUBLE_BUFFER 0
++#else
++# define gcdENABLE_TS_DOUBLE_BUFFER 1
++#endif
++#endif
++
++/* gcdINTERRUPT_STATISTIC
++ *
++ * Monitor the event send to GPU and interrupt issued by GPU.
++ */
++
++#ifndef gcdINTERRUPT_STATISTIC
++#if defined(LINUX)
++# define gcdINTERRUPT_STATISTIC 1
++#else
++# define gcdINTERRUPT_STATISTIC 0
++#endif
++#endif
++
++/*
++ gcdYINVERTED_RENDERING
++ When it's not zero, we will rendering display buffer
++ with top-bottom direction. All other offscreen rendering
++ will be bottom-top, which follow OpenGL ES spec.
++*/
++#ifndef gcdYINVERTED_RENDERING
++# define gcdYINVERTED_RENDERING 1
++#endif
++
++#if gcdYINVERTED_RENDERING
++/* disable unaligned linear composition adjust in Y-inverted rendering mode. */
++# undef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST
++# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 0
++#endif
++
++/*
++ gcdFENCE_WAIT_LOOP_COUNT
++ Wait fence, loop count.
++*/
++#ifndef gcdFENCE_WAIT_LOOP_COUNT
++# define gcdFENCE_WAIT_LOOP_COUNT 100
++#endif
++
++/*
++ gcdHAL_3D_DRAWBLIT
++ When it's not zero, we will enable HAL 3D drawblit
++ to replace client 3dblit.
++*/
++#ifndef gcdHAL_3D_DRAWBLIT
++# define gcdHAL_3D_DRAWBLIT 1
++#endif
++
++/*
++ gcdPARTIAL_FAST_CLEAR
++ When it's not zero, partial fast clear is enabled.
++ Depends on gcdHAL_3D_DRAWBLIT, if gcdHAL_3D_DRAWBLIT is not enabled,
++ only available when scissor box is completely aligned.
++ Expremental, under test.
++*/
++#ifndef gcdPARTIAL_FAST_CLEAR
++# define gcdPARTIAL_FAST_CLEAR 1
++#endif
++
++/*
++ gcdREMOVE_SURF_ORIENTATION
++ When it's not zero, we will remove surface orientation function.
++ It wil become to a parameter of resolve function.
++*/
++#ifndef gcdREMOVE_SURF_ORIENTATION
++# define gcdREMOVE_SURF_ORIENTATION 0
++#endif
++
++/*
++ gcdPATTERN_FAST_PATH
++ For pattern match
++*/
++#ifndef gcdPATTERN_FAST_PATH
++# define gcdPATTERN_FAST_PATH 1
++#endif
++
++/*
++ gcdUSE_INPUT_DEVICE
++ disable input devices usage under fb mode to support fb+vdk multi-process
++*/
++#ifndef gcdUSE_INPUT_DEVICE
++# define gcdUSE_INPUT_DEVICE 1
++#endif
++
++
++/*
++ gcdFRAMEINFO_STATISTIC
++ When enable, collect frame information.
++*/
++#ifndef gcdFRAMEINFO_STATISTIC
++
++#if (defined(DBG) && DBG) || defined(DEBUG) || defined(_DEBUG) || gcdDUMP
++# define gcdFRAMEINFO_STATISTIC 1
++#else
++# define gcdFRAMEINFO_STATISTIC 0
++#endif
++
++#endif
++
++/*
++ gcdPACKED_OUTPUT_ADDRESS
++ When it's not zero, ps output is already packed after linked
++*/
++#ifndef gcdPACKED_OUTPUT_ADDRESS
++# define gcdPACKED_OUTPUT_ADDRESS 1
++#endif
++
++/*
++ gcdENABLE_THIRD_PARTY_OPERATION
++ Enable third party operation like tpc or not.
++*/
++#ifndef gcdENABLE_THIRD_PARTY_OPERATION
++# define gcdENABLE_THIRD_PARTY_OPERATION 1
++#endif
++
++
++/*
++ Core configurations. By default enable all cores.
++*/
++#ifndef gcdENABLE_3D
++# define gcdENABLE_3D 1
++#endif
++
++#ifndef gcdENABLE_2D
++# define gcdENABLE_2D 1
++#endif
++
++#ifndef gcdENABLE_VG
++# define gcdENABLE_VG 0
++#endif
++
++#ifndef gcdGC355_MEM_PRINT
++# define gcdGC355_MEM_PRINT 0
++#else
++#if (!((gcdENABLE_3D == 0) && (gcdENABLE_2D == 0) && (gcdENABLE_VG == 1)))
++# undef gcdGC355_MEM_PRINT
++# define gcdGC355_MEM_PRINT 0
++# endif
++#endif
++
++#ifndef gcdENABLE_UNIFIED_CONSTANT
++# define gcdENABLE_UNIFIED_CONSTANT 1
++#endif
++
++/*
++ gcdRECORD_COMMAND
++*/
++#ifndef gcdRECORD_COMMAND
++# define gcdRECORD_COMMAND 0
++#endif
++
++#endif /* __gc_hal_options_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_profiler.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,585 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_profiler_h_
++#define __gc_hal_profiler_h_
++
++#if VIVANTE_PROFILER_NEW
++#include "gc_hal_engine.h"
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++#define GLVERTEX_OBJECT 10
++#define GLVERTEX_OBJECT_BYTES 11
++
++#define GLINDEX_OBJECT 20
++#define GLINDEX_OBJECT_BYTES 21
++
++#define GLTEXTURE_OBJECT 30
++#define GLTEXTURE_OBJECT_BYTES 31
++
++#define GLBUFOBJ_OBJECT 40
++#define GLBUFOBJ_OBJECT_BYTES 41
++
++#if VIVANTE_PROFILER
++#define gcmPROFILE_GC(Enum, Value) gcoPROFILER_Count(gcvNULL, Enum, Value)
++#else
++#define gcmPROFILE_GC(Enum, Value) do { } while (gcvFALSE)
++#endif
++
++#ifndef gcdNEW_PROFILER_FILE
++#define gcdNEW_PROFILER_FILE 1
++#endif
++
++#define ES11_CALLS 151
++#define ES11_DRAWCALLS (ES11_CALLS + 1)
++#define ES11_STATECHANGECALLS (ES11_DRAWCALLS + 1)
++#define ES11_POINTCOUNT (ES11_STATECHANGECALLS + 1)
++#define ES11_LINECOUNT (ES11_POINTCOUNT + 1)
++#define ES11_TRIANGLECOUNT (ES11_LINECOUNT + 1)
++
++#define ES30_CALLS 159
++#define ES30_DRAWCALLS (ES30_CALLS + 1)
++#define ES30_STATECHANGECALLS (ES30_DRAWCALLS + 1)
++#define ES30_POINTCOUNT (ES30_STATECHANGECALLS + 1)
++#define ES30_LINECOUNT (ES30_POINTCOUNT + 1)
++#define ES30_TRIANGLECOUNT (ES30_LINECOUNT + 1)
++
++#define VG11_CALLS 88
++#define VG11_DRAWCALLS (VG11_CALLS + 1)
++#define VG11_STATECHANGECALLS (VG11_DRAWCALLS + 1)
++#define VG11_FILLCOUNT (VG11_STATECHANGECALLS + 1)
++#define VG11_STROKECOUNT (VG11_FILLCOUNT + 1)
++/* End of Driver API ID Definitions. */
++
++/* HAL & MISC IDs. */
++#define HAL_VERTBUFNEWBYTEALLOC 1
++#define HAL_VERTBUFTOTALBYTEALLOC (HAL_VERTBUFNEWBYTEALLOC + 1)
++#define HAL_VERTBUFNEWOBJALLOC (HAL_VERTBUFTOTALBYTEALLOC + 1)
++#define HAL_VERTBUFTOTALOBJALLOC (HAL_VERTBUFNEWOBJALLOC + 1)
++#define HAL_INDBUFNEWBYTEALLOC (HAL_VERTBUFTOTALOBJALLOC + 1)
++#define HAL_INDBUFTOTALBYTEALLOC (HAL_INDBUFNEWBYTEALLOC + 1)
++#define HAL_INDBUFNEWOBJALLOC (HAL_INDBUFTOTALBYTEALLOC + 1)
++#define HAL_INDBUFTOTALOBJALLOC (HAL_INDBUFNEWOBJALLOC + 1)
++#define HAL_TEXBUFNEWBYTEALLOC (HAL_INDBUFTOTALOBJALLOC + 1)
++#define HAL_TEXBUFTOTALBYTEALLOC (HAL_TEXBUFNEWBYTEALLOC + 1)
++#define HAL_TEXBUFNEWOBJALLOC (HAL_TEXBUFTOTALBYTEALLOC + 1)
++#define HAL_TEXBUFTOTALOBJALLOC (HAL_TEXBUFNEWOBJALLOC + 1)
++
++#define GPU_CYCLES 1
++#define GPU_READ64BYTE (GPU_CYCLES + 1)
++#define GPU_WRITE64BYTE (GPU_READ64BYTE + 1)
++#define GPU_TOTALCYCLES (GPU_WRITE64BYTE + 1)
++#define GPU_IDLECYCLES (GPU_TOTALCYCLES + 1)
++
++#define VS_INSTCOUNT 1
++#define VS_BRANCHINSTCOUNT (VS_INSTCOUNT + 1)
++#define VS_TEXLDINSTCOUNT (VS_BRANCHINSTCOUNT + 1)
++#define VS_RENDEREDVERTCOUNT (VS_TEXLDINSTCOUNT + 1)
++#define VS_SOURCE (VS_RENDEREDVERTCOUNT + 1)
++
++#define PS_INSTCOUNT 1
++#define PS_BRANCHINSTCOUNT (PS_INSTCOUNT + 1)
++#define PS_TEXLDINSTCOUNT (PS_BRANCHINSTCOUNT + 1)
++#define PS_RENDEREDPIXCOUNT (PS_TEXLDINSTCOUNT + 1)
++#define PS_SOURCE (PS_RENDEREDPIXCOUNT + 1)
++
++#define PA_INVERTCOUNT 1
++#define PA_INPRIMCOUNT (PA_INVERTCOUNT + 1)
++#define PA_OUTPRIMCOUNT (PA_INPRIMCOUNT + 1)
++#define PA_DEPTHCLIPCOUNT (PA_OUTPRIMCOUNT + 1)
++#define PA_TRIVIALREJCOUNT (PA_DEPTHCLIPCOUNT + 1)
++#define PA_CULLCOUNT (PA_TRIVIALREJCOUNT + 1)
++
++#define SE_TRIANGLECOUNT 1
++#define SE_LINECOUNT (SE_TRIANGLECOUNT + 1)
++
++#define RA_VALIDPIXCOUNT 1
++#define RA_TOTALQUADCOUNT (RA_VALIDPIXCOUNT + 1)
++#define RA_VALIDQUADCOUNTEZ (RA_TOTALQUADCOUNT + 1)
++#define RA_TOTALPRIMCOUNT (RA_VALIDQUADCOUNTEZ + 1)
++#define RA_PIPECACHEMISSCOUNT (RA_TOTALPRIMCOUNT + 1)
++#define RA_PREFCACHEMISSCOUNT (RA_PIPECACHEMISSCOUNT + 1)
++#define RA_EEZCULLCOUNT (RA_PREFCACHEMISSCOUNT + 1)
++
++#define TX_TOTBILINEARREQ 1
++#define TX_TOTTRILINEARREQ (TX_TOTBILINEARREQ + 1)
++#define TX_TOTDISCARDTEXREQ (TX_TOTTRILINEARREQ + 1)
++#define TX_TOTTEXREQ (TX_TOTDISCARDTEXREQ + 1)
++#define TX_MEMREADCOUNT (TX_TOTTEXREQ + 1)
++#define TX_MEMREADIN8BCOUNT (TX_MEMREADCOUNT + 1)
++#define TX_CACHEMISSCOUNT (TX_MEMREADIN8BCOUNT + 1)
++#define TX_CACHEHITTEXELCOUNT (TX_CACHEMISSCOUNT + 1)
++#define TX_CACHEMISSTEXELCOUNT (TX_CACHEHITTEXELCOUNT + 1)
++
++#define PE_KILLEDBYCOLOR 1
++#define PE_KILLEDBYDEPTH (PE_KILLEDBYCOLOR + 1)
++#define PE_DRAWNBYCOLOR (PE_KILLEDBYDEPTH + 1)
++#define PE_DRAWNBYDEPTH (PE_DRAWNBYCOLOR + 1)
++
++#define MC_READREQ8BPIPE 1
++#define MC_READREQ8BIP (MC_READREQ8BPIPE + 1)
++#define MC_WRITEREQ8BPIPE (MC_READREQ8BIP + 1)
++
++#define AXI_READREQSTALLED 1
++#define AXI_WRITEREQSTALLED (AXI_READREQSTALLED + 1)
++#define AXI_WRITEDATASTALLED (AXI_WRITEREQSTALLED + 1)
++
++#define PVS_INSTRCOUNT 1
++#define PVS_ALUINSTRCOUNT (PVS_INSTRCOUNT + 1)
++#define PVS_TEXINSTRCOUNT (PVS_ALUINSTRCOUNT + 1)
++#define PVS_ATTRIBCOUNT (PVS_TEXINSTRCOUNT + 1)
++#define PVS_UNIFORMCOUNT (PVS_ATTRIBCOUNT + 1)
++#define PVS_FUNCTIONCOUNT (PVS_UNIFORMCOUNT + 1)
++#define PVS_SOURCE (PVS_FUNCTIONCOUNT + 1)
++
++#define PPS_INSTRCOUNT 1
++#define PPS_ALUINSTRCOUNT (PPS_INSTRCOUNT + 1)
++#define PPS_TEXINSTRCOUNT (PPS_ALUINSTRCOUNT + 1)
++#define PPS_ATTRIBCOUNT (PPS_TEXINSTRCOUNT + 1)
++#define PPS_UNIFORMCOUNT (PPS_ATTRIBCOUNT + 1)
++#define PPS_FUNCTIONCOUNT (PPS_UNIFORMCOUNT + 1)
++#define PPS_SOURCE (PPS_FUNCTIONCOUNT + 1)
++/* End of MISC Counter IDs. */
++
++#ifdef gcdNEW_PROFILER_FILE
++
++/* Category Constants. */
++#define VPHEADER 0x010000
++#define VPG_INFO 0x020000
++#define VPG_TIME 0x030000
++#define VPG_MEM 0x040000
++#define VPG_ES11 0x050000
++#define VPG_ES30 0x060000
++#define VPG_VG11 0x070000
++#define VPG_HAL 0x080000
++#define VPG_HW 0x090000
++#define VPG_GPU 0x0a0000
++#define VPG_VS 0x0b0000
++#define VPG_PS 0x0c0000
++#define VPG_PA 0x0d0000
++#define VPG_SETUP 0x0e0000
++#define VPG_RA 0x0f0000
++#define VPG_TX 0x100000
++#define VPG_PE 0x110000
++#define VPG_MC 0x120000
++#define VPG_AXI 0x130000
++#define VPG_PROG 0x140000
++#define VPG_PVS 0x150000
++#define VPG_PPS 0x160000
++#define VPG_ES11_TIME 0x170000
++#define VPG_ES30_TIME 0x180000
++#define VPG_FRAME 0x190000
++#define VPG_ES11_DRAW 0x200000
++#define VPG_ES30_DRAW 0x210000
++#define VPG_VG11_TIME 0x220000
++#define VPG_END 0xff0000
++
++/* Info. */
++#define VPC_INFOCOMPANY (VPG_INFO + 1)
++#define VPC_INFOVERSION (VPC_INFOCOMPANY + 1)
++#define VPC_INFORENDERER (VPC_INFOVERSION + 1)
++#define VPC_INFOREVISION (VPC_INFORENDERER + 1)
++#define VPC_INFODRIVER (VPC_INFOREVISION + 1)
++#define VPC_INFODRIVERMODE (VPC_INFODRIVER + 1)
++#define VPC_INFOSCREENSIZE (VPC_INFODRIVERMODE + 1)
++
++/* Counter Constants. */
++#define VPC_ELAPSETIME (VPG_TIME + 1)
++#define VPC_CPUTIME (VPC_ELAPSETIME + 1)
++
++#define VPC_MEMMAXRES (VPG_MEM + 1)
++#define VPC_MEMSHARED (VPC_MEMMAXRES + 1)
++#define VPC_MEMUNSHAREDDATA (VPC_MEMSHARED + 1)
++#define VPC_MEMUNSHAREDSTACK (VPC_MEMUNSHAREDDATA + 1)
++
++/* OpenGL ES11 Statics Counter IDs. */
++#define VPC_ES11CALLS (VPG_ES11 + ES11_CALLS)
++#define VPC_ES11DRAWCALLS (VPG_ES11 + ES11_DRAWCALLS)
++#define VPC_ES11STATECHANGECALLS (VPG_ES11 + ES11_STATECHANGECALLS)
++#define VPC_ES11POINTCOUNT (VPG_ES11 + ES11_POINTCOUNT)
++#define VPC_ES11LINECOUNT (VPG_ES11 + ES11_LINECOUNT)
++#define VPC_ES11TRIANGLECOUNT (VPG_ES11 + ES11_TRIANGLECOUNT)
++
++/* OpenGL ES30 Statistics Counter IDs. */
++#define VPC_ES30CALLS (VPG_ES30 + ES30_CALLS)
++#define VPC_ES30DRAWCALLS (VPG_ES30 + ES30_DRAWCALLS)
++#define VPC_ES30STATECHANGECALLS (VPG_ES30 + ES30_STATECHANGECALLS)
++#define VPC_ES30POINTCOUNT (VPG_ES30 + ES30_POINTCOUNT)
++#define VPC_ES30LINECOUNT (VPG_ES30 + ES30_LINECOUNT)
++#define VPC_ES30TRIANGLECOUNT (VPG_ES30 + ES30_TRIANGLECOUNT)
++
++/* OpenVG Statistics Counter IDs. */
++#define VPC_VG11CALLS (VPG_VG11 + VG11_CALLS)
++#define VPC_VG11DRAWCALLS (VPG_VG11 + VG11_DRAWCALLS)
++#define VPC_VG11STATECHANGECALLS (VPG_VG11 + VG11_STATECHANGECALLS)
++#define VPC_VG11FILLCOUNT (VPG_VG11 + VG11_FILLCOUNT)
++#define VPC_VG11STROKECOUNT (VPG_VG11 + VG11_STROKECOUNT)
++
++/* HAL Counters. */
++#define VPC_HALVERTBUFNEWBYTEALLOC (VPG_HAL + HAL_VERTBUFNEWBYTEALLOC)
++#define VPC_HALVERTBUFTOTALBYTEALLOC (VPG_HAL + HAL_VERTBUFTOTALBYTEALLOC)
++#define VPC_HALVERTBUFNEWOBJALLOC (VPG_HAL + HAL_VERTBUFNEWOBJALLOC)
++#define VPC_HALVERTBUFTOTALOBJALLOC (VPG_HAL + HAL_VERTBUFTOTALOBJALLOC)
++#define VPC_HALINDBUFNEWBYTEALLOC (VPG_HAL + HAL_INDBUFNEWBYTEALLOC)
++#define VPC_HALINDBUFTOTALBYTEALLOC (VPG_HAL + HAL_INDBUFTOTALBYTEALLOC)
++#define VPC_HALINDBUFNEWOBJALLOC (VPG_HAL + HAL_INDBUFNEWOBJALLOC)
++#define VPC_HALINDBUFTOTALOBJALLOC (VPG_HAL + HAL_INDBUFTOTALOBJALLOC)
++#define VPC_HALTEXBUFNEWBYTEALLOC (VPG_HAL + HAL_TEXBUFNEWBYTEALLOC)
++#define VPC_HALTEXBUFTOTALBYTEALLOC (VPG_HAL + HAL_TEXBUFTOTALBYTEALLOC)
++#define VPC_HALTEXBUFNEWOBJALLOC (VPG_HAL + HAL_TEXBUFNEWOBJALLOC)
++#define VPC_HALTEXBUFTOTALOBJALLOC (VPG_HAL + HAL_TEXBUFTOTALOBJALLOC)
++
++/* HW: GPU Counters. */
++#define VPC_GPUCYCLES (VPG_GPU + GPU_CYCLES)
++#define VPC_GPUREAD64BYTE (VPG_GPU + GPU_READ64BYTE)
++#define VPC_GPUWRITE64BYTE (VPG_GPU + GPU_WRITE64BYTE)
++#define VPC_GPUTOTALCYCLES (VPG_GPU + GPU_TOTALCYCLES)
++#define VPC_GPUIDLECYCLES (VPG_GPU + GPU_IDLECYCLES)
++
++/* HW: Shader Counters. */
++#define VPC_VSINSTCOUNT (VPG_VS + VS_INSTCOUNT)
++#define VPC_VSBRANCHINSTCOUNT (VPG_VS + VS_BRANCHINSTCOUNT)
++#define VPC_VSTEXLDINSTCOUNT (VPG_VS + VS_TEXLDINSTCOUNT)
++#define VPC_VSRENDEREDVERTCOUNT (VPG_VS + VS_RENDEREDVERTCOUNT)
++/* HW: PS Count. */
++#define VPC_PSINSTCOUNT (VPG_PS + PS_INSTCOUNT)
++#define VPC_PSBRANCHINSTCOUNT (VPG_PS + PS_BRANCHINSTCOUNT)
++#define VPC_PSTEXLDINSTCOUNT (VPG_PS + PS_TEXLDINSTCOUNT)
++#define VPC_PSRENDEREDPIXCOUNT (VPG_PS + PS_RENDEREDPIXCOUNT)
++
++
++/* HW: PA Counters. */
++#define VPC_PAINVERTCOUNT (VPG_PA + PA_INVERTCOUNT)
++#define VPC_PAINPRIMCOUNT (VPG_PA + PA_INPRIMCOUNT)
++#define VPC_PAOUTPRIMCOUNT (VPG_PA + PA_OUTPRIMCOUNT)
++#define VPC_PADEPTHCLIPCOUNT (VPG_PA + PA_DEPTHCLIPCOUNT)
++#define VPC_PATRIVIALREJCOUNT (VPG_PA + PA_TRIVIALREJCOUNT)
++#define VPC_PACULLCOUNT (VPG_PA + PA_CULLCOUNT)
++
++/* HW: Setup Counters. */
++#define VPC_SETRIANGLECOUNT (VPG_SETUP + SE_TRIANGLECOUNT)
++#define VPC_SELINECOUNT (VPG_SETUP + SE_LINECOUNT)
++
++/* HW: RA Counters. */
++#define VPC_RAVALIDPIXCOUNT (VPG_RA + RA_VALIDPIXCOUNT)
++#define VPC_RATOTALQUADCOUNT (VPG_RA + RA_TOTALQUADCOUNT)
++#define VPC_RAVALIDQUADCOUNTEZ (VPG_RA + RA_VALIDQUADCOUNTEZ)
++#define VPC_RATOTALPRIMCOUNT (VPG_RA + RA_TOTALPRIMCOUNT)
++#define VPC_RAPIPECACHEMISSCOUNT (VPG_RA + RA_PIPECACHEMISSCOUNT)
++#define VPC_RAPREFCACHEMISSCOUNT (VPG_RA + RA_PREFCACHEMISSCOUNT)
++#define VPC_RAEEZCULLCOUNT (VPG_RA + RA_EEZCULLCOUNT)
++
++/* HW: TEX Counters. */
++#define VPC_TXTOTBILINEARREQ (VPG_TX + TX_TOTBILINEARREQ)
++#define VPC_TXTOTTRILINEARREQ (VPG_TX + TX_TOTTRILINEARREQ)
++#define VPC_TXTOTDISCARDTEXREQ (VPG_TX + TX_TOTDISCARDTEXREQ)
++#define VPC_TXTOTTEXREQ (VPG_TX + TX_TOTTEXREQ)
++#define VPC_TXMEMREADCOUNT (VPG_TX + TX_MEMREADCOUNT)
++#define VPC_TXMEMREADIN8BCOUNT (VPG_TX + TX_MEMREADIN8BCOUNT)
++#define VPC_TXCACHEMISSCOUNT (VPG_TX + TX_CACHEMISSCOUNT)
++#define VPC_TXCACHEHITTEXELCOUNT (VPG_TX + TX_CACHEHITTEXELCOUNT)
++#define VPC_TXCACHEMISSTEXELCOUNT (VPG_TX + TX_CACHEMISSTEXELCOUNT)
++
++/* HW: PE Counters. */
++#define VPC_PEKILLEDBYCOLOR (VPG_PE + PE_KILLEDBYCOLOR)
++#define VPC_PEKILLEDBYDEPTH (VPG_PE + PE_KILLEDBYDEPTH)
++#define VPC_PEDRAWNBYCOLOR (VPG_PE + PE_DRAWNBYCOLOR)
++#define VPC_PEDRAWNBYDEPTH (VPG_PE + PE_DRAWNBYDEPTH)
++
++/* HW: MC Counters. */
++#define VPC_MCREADREQ8BPIPE (VPG_MC + MC_READREQ8BPIPE)
++#define VPC_MCREADREQ8BIP (VPG_MC + MC_READREQ8BIP)
++#define VPC_MCWRITEREQ8BPIPE (VPG_MC + MC_WRITEREQ8BPIPE)
++
++/* HW: AXI Counters. */
++#define VPC_AXIREADREQSTALLED (VPG_AXI + AXI_READREQSTALLED)
++#define VPC_AXIWRITEREQSTALLED (VPG_AXI + AXI_WRITEREQSTALLED)
++#define VPC_AXIWRITEDATASTALLED (VPG_AXI + AXI_WRITEDATASTALLED)
++
++/* PROGRAM: Shader program counters. */
++#define VPC_PVSINSTRCOUNT (VPG_PVS + PVS_INSTRCOUNT)
++#define VPC_PVSALUINSTRCOUNT (VPG_PVS + PVS_ALUINSTRCOUNT)
++#define VPC_PVSTEXINSTRCOUNT (VPG_PVS + PVS_TEXINSTRCOUNT)
++#define VPC_PVSATTRIBCOUNT (VPG_PVS + PVS_ATTRIBCOUNT)
++#define VPC_PVSUNIFORMCOUNT (VPG_PVS + PVS_UNIFORMCOUNT)
++#define VPC_PVSFUNCTIONCOUNT (VPG_PVS + PVS_FUNCTIONCOUNT)
++#define VPC_PVSSOURCE (VPG_PVS + PVS_SOURCE)
++
++#define VPC_PPSINSTRCOUNT (VPG_PPS + PPS_INSTRCOUNT)
++#define VPC_PPSALUINSTRCOUNT (VPG_PPS + PPS_ALUINSTRCOUNT)
++#define VPC_PPSTEXINSTRCOUNT (VPG_PPS + PPS_TEXINSTRCOUNT)
++#define VPC_PPSATTRIBCOUNT (VPG_PPS + PPS_ATTRIBCOUNT)
++#define VPC_PPSUNIFORMCOUNT (VPG_PPS + PPS_UNIFORMCOUNT)
++#define VPC_PPSFUNCTIONCOUNT (VPG_PPS + PPS_FUNCTIONCOUNT)
++#define VPC_PPSSOURCE (VPG_PPS + PPS_SOURCE)
++
++#define VPC_PROGRAMHANDLE (VPG_PROG + 1)
++
++#define VPC_ES30_DRAW_NO (VPG_ES30_DRAW + 1)
++#define VPC_ES11_DRAW_NO (VPG_ES11_DRAW + 1)
++#endif
++
++
++/* HW profile information. */
++typedef struct _gcsPROFILER_COUNTERS
++{
++ /* HW static counters. */
++ gctUINT32 gpuClock;
++ gctUINT32 axiClock;
++ gctUINT32 shaderClock;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuClockStart;
++ gctUINT32 gpuClockEnd;
++
++ /* HW vairable counters. */
++ gctUINT32 gpuCyclesCounter;
++ gctUINT32 gpuTotalCyclesCounter;
++ gctUINT32 gpuIdleCyclesCounter;
++ gctUINT32 gpuTotalRead64BytesPerFrame;
++ gctUINT32 gpuTotalWrite64BytesPerFrame;
++
++ /* PE */
++ gctUINT32 pe_pixel_count_killed_by_color_pipe;
++ gctUINT32 pe_pixel_count_killed_by_depth_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_color_pipe;
++ gctUINT32 pe_pixel_count_drawn_by_depth_pipe;
++
++ /* SH */
++ gctUINT32 ps_inst_counter;
++ gctUINT32 rendered_pixel_counter;
++ gctUINT32 vs_inst_counter;
++ gctUINT32 rendered_vertice_counter;
++ gctUINT32 vtx_branch_inst_counter;
++ gctUINT32 vtx_texld_inst_counter;
++ gctUINT32 pxl_branch_inst_counter;
++ gctUINT32 pxl_texld_inst_counter;
++
++ /* PA */
++ gctUINT32 pa_input_vtx_counter;
++ gctUINT32 pa_input_prim_counter;
++ gctUINT32 pa_output_prim_counter;
++ gctUINT32 pa_depth_clipped_counter;
++ gctUINT32 pa_trivial_rejected_counter;
++ gctUINT32 pa_culled_counter;
++
++ /* SE */
++ gctUINT32 se_culled_triangle_count;
++ gctUINT32 se_culled_lines_count;
++
++ /* RA */
++ gctUINT32 ra_valid_pixel_count;
++ gctUINT32 ra_total_quad_count;
++ gctUINT32 ra_valid_quad_count_after_early_z;
++ gctUINT32 ra_total_primitive_count;
++ gctUINT32 ra_pipe_cache_miss_counter;
++ gctUINT32 ra_prefetch_cache_miss_counter;
++ gctUINT32 ra_eez_culled_counter;
++
++ /* TX */
++ gctUINT32 tx_total_bilinear_requests;
++ gctUINT32 tx_total_trilinear_requests;
++ gctUINT32 tx_total_discarded_texture_requests;
++ gctUINT32 tx_total_texture_requests;
++ gctUINT32 tx_mem_read_count;
++ gctUINT32 tx_mem_read_in_8B_count;
++ gctUINT32 tx_cache_miss_count;
++ gctUINT32 tx_cache_hit_texel_count;
++ gctUINT32 tx_cache_miss_texel_count;
++
++ /* MC */
++ gctUINT32 mc_total_read_req_8B_from_pipeline;
++ gctUINT32 mc_total_read_req_8B_from_IP;
++ gctUINT32 mc_total_write_req_8B_from_pipeline;
++
++ /* HI */
++ gctUINT32 hi_axi_cycles_read_request_stalled;
++ gctUINT32 hi_axi_cycles_write_request_stalled;
++ gctUINT32 hi_axi_cycles_write_data_stalled;
++}
++gcsPROFILER_COUNTERS;
++
++#if VIVANTE_PROFILER_NEW
++#define NumOfDrawBuf 64
++#endif
++
++/* HAL profile information. */
++typedef struct _gcsPROFILER
++{
++ gctUINT32 enable;
++ gctBOOL enableHal;
++ gctBOOL enableHW;
++ gctBOOL enableSH;
++ gctBOOL isSyncMode;
++ gctBOOL disableOutputCounter;
++
++ gctBOOL useSocket;
++ gctINT sockFd;
++
++ gctFILE file;
++
++ /* Aggregate Information */
++
++ /* Clock Info */
++ gctUINT64 frameStart;
++ gctUINT64 frameEnd;
++
++ /* Current frame information */
++ gctUINT32 frameNumber;
++ gctUINT64 frameStartTimeusec;
++ gctUINT64 frameEndTimeusec;
++ gctUINT64 frameStartCPUTimeusec;
++ gctUINT64 frameEndCPUTimeusec;
++
++#if PROFILE_HAL_COUNTERS
++ gctUINT32 vertexBufferTotalBytesAlloc;
++ gctUINT32 vertexBufferNewBytesAlloc;
++ int vertexBufferTotalObjectsAlloc;
++ int vertexBufferNewObjectsAlloc;
++
++ gctUINT32 indexBufferTotalBytesAlloc;
++ gctUINT32 indexBufferNewBytesAlloc;
++ int indexBufferTotalObjectsAlloc;
++ int indexBufferNewObjectsAlloc;
++
++ gctUINT32 textureBufferTotalBytesAlloc;
++ gctUINT32 textureBufferNewBytesAlloc;
++ int textureBufferTotalObjectsAlloc;
++ int textureBufferNewObjectsAlloc;
++
++ gctUINT32 numCommits;
++ gctUINT32 drawPointCount;
++ gctUINT32 drawLineCount;
++ gctUINT32 drawTriangleCount;
++ gctUINT32 drawVertexCount;
++ gctUINT32 redundantStateChangeCalls;
++#endif
++
++ gctUINT32 prevVSInstCount;
++ gctUINT32 prevVSBranchInstCount;
++ gctUINT32 prevVSTexInstCount;
++ gctUINT32 prevVSVertexCount;
++ gctUINT32 prevPSInstCount;
++ gctUINT32 prevPSBranchInstCount;
++ gctUINT32 prevPSTexInstCount;
++ gctUINT32 prevPSPixelCount;
++
++#if VIVANTE_PROFILER_NEW
++ gcoBUFOBJ newCounterBuf[NumOfDrawBuf];
++ gctUINT32 curBufId;
++#endif
++
++}
++gcsPROFILER;
++
++/* Memory profile information. */
++struct _gcsMemProfile
++{
++ /* Memory Usage */
++ gctUINT32 videoMemUsed;
++ gctUINT32 systemMemUsed;
++ gctUINT32 commitBufferSize;
++ gctUINT32 contextBufferCopyBytes;
++};
++
++/* Shader profile information. */
++struct _gcsSHADER_PROFILER
++{
++ gctUINT32 shaderLength;
++ gctUINT32 shaderALUCycles;
++ gctUINT32 shaderTexLoadCycles;
++ gctUINT32 shaderTempRegCount;
++ gctUINT32 shaderSamplerRegCount;
++ gctUINT32 shaderInputRegCount;
++ gctUINT32 shaderOutputRegCount;
++};
++
++/* Initialize the gcsProfiler. */
++gceSTATUS
++gcoPROFILER_Initialize(
++ IN gcoHAL Hal,
++ IN gctBOOL Enable
++ );
++
++/* Destroy the gcProfiler. */
++gceSTATUS
++gcoPROFILER_Destroy(
++ IN gcoHAL Hal
++ );
++
++/* Write data to profiler. */
++gceSTATUS
++gcoPROFILER_Write(
++ IN gcoHAL Hal,
++ IN gctSIZE_T ByteCount,
++ IN gctCONST_POINTER Data
++ );
++
++/* Flush data out. */
++gceSTATUS
++gcoPROFILER_Flush(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of frame. */
++gceSTATUS
++gcoPROFILER_EndFrame(
++ IN gcoHAL Hal
++ );
++
++/* Call to signal end of draw. */
++gceSTATUS
++gcoPROFILER_EndDraw(
++ IN gcoHAL Hal,
++ IN gctBOOL FirstDraw
++ );
++
++/* Increase profile counter Enum by Value. */
++gceSTATUS
++gcoPROFILER_Count(
++ IN gcoHAL Hal,
++ IN gctUINT32 Enum,
++ IN gctINT Value
++ );
++
++/* Profile input vertex shader. */
++gceSTATUS
++gcoPROFILER_ShaderVS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Vs
++ );
++
++/* Profile input fragment shader. */
++gceSTATUS
++gcoPROFILER_ShaderFS(
++ IN gcoHAL Hal,
++ IN gctPOINTER Fs
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_profiler_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_raster.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,1038 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_raster_h_
++#define __gc_hal_raster_h_
++
++#include "gc_hal_enum.h"
++#include "gc_hal_types.h"
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** Object Declarations *****************************
++\******************************************************************************/
++
++typedef struct _gcoBRUSH * gcoBRUSH;
++typedef struct _gcoBRUSH_CACHE * gcoBRUSH_CACHE;
++
++/******************************************************************************\
++******************************** gcoBRUSH Object *******************************
++\******************************************************************************/
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructSingleColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructMonochrome(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_ConstructColor(
++ IN gcoHAL Hal,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Destroy an gcoBRUSH object. */
++gceSTATUS
++gcoBRUSH_Destroy(
++ IN gcoBRUSH Brush
++ );
++
++/******************************************************************************\
++******************************** gcoSURF Object *******************************
++\******************************************************************************/
++
++/* Set cipping rectangle. */
++gceSTATUS
++gcoSURF_SetClipping(
++ IN gcoSURF Surface
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gcoSURF_Clear2D(
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 LoColor,
++ IN gctUINT32 HiColor
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gcoSURF_Line(
++ IN gcoSURF Surface,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Generic rectangular blit. */
++gceSTATUS
++gcoSURF_Blit(
++ IN OPTIONAL gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gctUINT32 RectCount,
++ IN OPTIONAL gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN OPTIONAL gceSURF_TRANSPARENCY Transparency,
++ IN OPTIONAL gctUINT32 TransparencyColor,
++ IN OPTIONAL gctPOINTER Mask,
++ IN OPTIONAL gceSURF_MONOPACK MaskPack
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gcoSURF_MonoBlit(
++ IN gcoSURF DestSurface,
++ IN gctPOINTER Source,
++ IN gceSURF_MONOPACK SourcePack,
++ IN gcsPOINT_PTR SourceSize,
++ IN gcsPOINT_PTR SourceOrigin,
++ IN gcsRECT_PTR DestRect,
++ IN OPTIONAL gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Filter blit. */
++gceSTATUS
++gcoSURF_FilterBlit(
++ IN gcoSURF SrcSurface,
++ IN gcoSURF DestSurface,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gcoSURF_EnableAlphaBlend(
++ IN gcoSURF Surface,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gcoSURF_DisableAlphaBlend(
++ IN gcoSURF Surface
++ );
++
++/* Copy a rectangular area with format conversion. */
++gceSTATUS
++gcoSURF_CopyPixels(
++ IN gcoSURF Source,
++ IN gcoSURF Target,
++ IN gctINT SourceX,
++ IN gctINT SourceY,
++ IN gctINT TargetX,
++ IN gctINT TargetY,
++ IN gctINT Width,
++ IN gctINT Height
++ );
++
++/* Read surface pixel. */
++gceSTATUS
++gcoSURF_ReadPixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ OUT gctPOINTER PixelValue
++ );
++
++/* Write surface pixel. */
++gceSTATUS
++gcoSURF_WritePixel(
++ IN gcoSURF Surface,
++ IN gctPOINTER Memory,
++ IN gctINT X,
++ IN gctINT Y,
++ IN gceSURF_FORMAT Format,
++ IN gctPOINTER PixelValue
++ );
++
++gceSTATUS
++gcoSURF_SetDither(
++ IN gcoSURF Surface,
++ IN gctBOOL Dither
++ );
++
++gceSTATUS
++gcoSURF_Set2DSource(
++ gcoSURF Surface,
++ gceSURF_ROTATION Rotation
++ );
++
++gceSTATUS
++gcoSURF_Set2DTarget(
++ gcoSURF Surface,
++ gceSURF_ROTATION Rotation
++ );
++
++/******************************************************************************\
++********************************** gco2D Object *********************************
++\******************************************************************************/
++
++/* Construct a new gco2D object. */
++gceSTATUS
++gco2D_Construct(
++ IN gcoHAL Hal,
++ OUT gco2D * Hardware
++ );
++
++/* Destroy an gco2D object. */
++gceSTATUS
++gco2D_Destroy(
++ IN gco2D Hardware
++ );
++
++/* Sets the maximum number of brushes in the brush cache. */
++gceSTATUS
++gco2D_SetBrushLimit(
++ IN gco2D Hardware,
++ IN gctUINT MaxCount
++ );
++
++/* Flush the brush. */
++gceSTATUS
++gco2D_FlushBrush(
++ IN gco2D Engine,
++ IN gcoBRUSH Brush,
++ IN gceSURF_FORMAT Format
++ );
++
++/* Program the specified solid color brush. */
++gceSTATUS
++gco2D_LoadSolidBrush(
++ IN gco2D Engine,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask
++ );
++
++gceSTATUS
++gco2D_LoadColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask
++ );
++
++/* Configure monochrome source. */
++gceSTATUS
++gco2D_SetMonochromeSource(
++ IN gco2D Engine,
++ IN gctBOOL ColorConvert,
++ IN gctUINT8 MonoTransparency,
++ IN gceSURF_MONOPACK DataPack,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source extension for full rotation. */
++gceSTATUS
++gco2D_SetColorSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_TRANSPARENCY Transparency,
++ IN gctUINT32 TransparencyColor
++ );
++
++/* Configure color source. */
++gceSTATUS
++gco2D_SetColorSourceAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctBOOL CoordRelative
++ );
++
++gceSTATUS
++gco2D_SetColorSourceN(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight,
++ IN gctUINT32 SurfaceNumber
++ );
++
++/* Configure masked color source. */
++gceSTATUS
++gco2D_SetMaskedSource(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack
++ );
++
++/* Configure masked color source extension for full rotation. */
++gceSTATUS
++gco2D_SetMaskedSourceEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_FORMAT Format,
++ IN gctBOOL CoordRelative,
++ IN gceSURF_MONOPACK MaskPack,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Setup the source rectangle. */
++gceSTATUS
++gco2D_SetSource(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect
++ );
++
++/* Set clipping rectangle. */
++gceSTATUS
++gco2D_SetClipping(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++/* Configure destination. */
++gceSTATUS
++gco2D_SetTarget(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth
++ );
++
++/* Configure destination extension for full rotation. */
++gceSTATUS
++gco2D_SetTargetEx(
++ IN gco2D Engine,
++ IN gctUINT32 Address,
++ IN gctUINT32 Stride,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++ );
++
++/* Calculate and program the stretch factors. */
++gceSTATUS
++gco2D_CalcStretchFactor(
++ IN gco2D Engine,
++ IN gctINT32 SrcSize,
++ IN gctINT32 DestSize,
++ OUT gctUINT32_PTR Factor
++ );
++
++gceSTATUS
++gco2D_SetStretchFactors(
++ IN gco2D Engine,
++ IN gctUINT32 HorFactor,
++ IN gctUINT32 VerFactor
++ );
++
++/* Calculate and program the stretch factors based on the rectangles. */
++gceSTATUS
++gco2D_SetStretchRectFactors(
++ IN gco2D Engine,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect
++ );
++
++/* Create a new solid color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructSingleColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 Color,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a new monochrome gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructMonochromeBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctUINT32 ColorConvert,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gctUINT64 Bits,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Create a color gcoBRUSH object. */
++gceSTATUS
++gco2D_ConstructColorBrush(
++ IN gco2D Engine,
++ IN gctUINT32 OriginX,
++ IN gctUINT32 OriginY,
++ IN gctPOINTER Address,
++ IN gceSURF_FORMAT Format,
++ IN gctUINT64 Mask,
++ gcoBRUSH * Brush
++ );
++
++/* Clear one or more rectangular areas. */
++gceSTATUS
++gco2D_Clear(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines. */
++gceSTATUS
++gco2D_Line(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gcoBRUSH Brush,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Draw one or more Bresenham lines based on the 32-bit color. */
++gceSTATUS
++gco2D_ColorLine(
++ IN gco2D Engine,
++ IN gctUINT32 LineCount,
++ IN gcsRECT_PTR Position,
++ IN gctUINT32 Color32,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Generic blit. */
++gceSTATUS
++gco2D_Blit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_Blend(
++ IN gco2D Engine,
++ IN gctUINT32 SrcCount,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Batch blit. */
++gceSTATUS
++gco2D_BatchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Stretch blit. */
++gceSTATUS
++gco2D_StretchBlit(
++ IN gco2D Engine,
++ IN gctUINT32 RectCount,
++ IN gcsRECT_PTR Rect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++/* Monochrome blit. */
++gceSTATUS
++gco2D_MonoBlit(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gcsPOINT_PTR StreamSize,
++ IN gcsRECT_PTR StreamRect,
++ IN gceSURF_MONOPACK SrcStreamPack,
++ IN gceSURF_MONOPACK DestStreamPack,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 FgRop,
++ IN gctUINT32 BgRop,
++ IN gceSURF_FORMAT DestFormat
++ );
++
++gceSTATUS
++gco2D_MonoBlitEx(
++ IN gco2D Engine,
++ IN gctPOINTER StreamBits,
++ IN gctINT32 StreamStride,
++ IN gctINT32 StreamWidth,
++ IN gctINT32 StreamHeight,
++ IN gctINT32 StreamX,
++ IN gctINT32 StreamY,
++ IN gctUINT32 FgColor,
++ IN gctUINT32 BgColor,
++ IN gcsRECT_PTR SrcRect,
++ IN gcsRECT_PTR DstRect,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++/* Set kernel size. */
++gceSTATUS
++gco2D_SetKernelSize(
++ IN gco2D Engine,
++ IN gctUINT8 HorKernelSize,
++ IN gctUINT8 VerKernelSize
++ );
++
++/* Set filter type. */
++gceSTATUS
++gco2D_SetFilterType(
++ IN gco2D Engine,
++ IN gceFILTER_TYPE FilterType
++ );
++
++/* Set the filter kernel by user. */
++gceSTATUS
++gco2D_SetUserFilterKernel(
++ IN gco2D Engine,
++ IN gceFILTER_PASS_TYPE PassType,
++ IN gctUINT16_PTR KernelArray
++ );
++
++/* Select the pass(es) to be done for user defined filter. */
++gceSTATUS
++gco2D_EnableUserFilterPasses(
++ IN gco2D Engine,
++ IN gctBOOL HorPass,
++ IN gctBOOL VerPass
++ );
++
++/* Frees the temporary buffer allocated by filter blit operation. */
++gceSTATUS
++gco2D_FreeFilterBuffer(
++ IN gco2D Engine
++ );
++
++/* Filter blit. */
++gceSTATUS
++gco2D_FilterBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Filter blit extension for full rotation. */
++gceSTATUS
++gco2D_FilterBlitEx(
++ IN gco2D Engine,
++ IN gctUINT32 SrcAddress,
++ IN gctUINT SrcStride,
++ IN gctUINT32 SrcUAddress,
++ IN gctUINT SrcUStride,
++ IN gctUINT32 SrcVAddress,
++ IN gctUINT SrcVStride,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32 DestAddress,
++ IN gctUINT DestStride,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++gceSTATUS
++gco2D_FilterBlitEx2(
++ IN gco2D Engine,
++ IN gctUINT32_PTR SrcAddresses,
++ IN gctUINT32 SrcAddressNum,
++ IN gctUINT32_PTR SrcStrides,
++ IN gctUINT32 SrcStrideNum,
++ IN gceTILING SrcTiling,
++ IN gceSURF_FORMAT SrcFormat,
++ IN gceSURF_ROTATION SrcRotation,
++ IN gctUINT32 SrcSurfaceWidth,
++ IN gctUINT32 SrcSurfaceHeight,
++ IN gcsRECT_PTR SrcRect,
++ IN gctUINT32_PTR DestAddresses,
++ IN gctUINT32 DestAddressNum,
++ IN gctUINT32_PTR DestStrides,
++ IN gctUINT32 DestStrideNum,
++ IN gceTILING DestTiling,
++ IN gceSURF_FORMAT DestFormat,
++ IN gceSURF_ROTATION DestRotation,
++ IN gctUINT32 DestSurfaceWidth,
++ IN gctUINT32 DestSurfaceHeight,
++ IN gcsRECT_PTR DestRect,
++ IN gcsRECT_PTR DestSubRect
++ );
++
++/* Enable alpha blending engine in the hardware and disengage the ROP engine. */
++gceSTATUS
++gco2D_EnableAlphaBlend(
++ IN gco2D Engine,
++ IN gctUINT8 SrcGlobalAlphaValue,
++ IN gctUINT8 DstGlobalAlphaValue,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode,
++ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode,
++ IN gceSURF_PIXEL_COLOR_MODE DstColorMode
++ );
++
++/* Enable alpha blending engine in the hardware. */
++gceSTATUS
++gco2D_EnableAlphaBlendAdvanced(
++ IN gco2D Engine,
++ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode,
++ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode,
++ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode,
++ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode,
++ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode
++ );
++
++/* Enable alpha blending engine with Porter Duff rule. */
++gceSTATUS
++gco2D_SetPorterDuffBlending(
++ IN gco2D Engine,
++ IN gce2D_PORTER_DUFF_RULE Rule
++ );
++
++/* Disable alpha blending engine in the hardware and engage the ROP engine. */
++gceSTATUS
++gco2D_DisableAlphaBlend(
++ IN gco2D Engine
++ );
++
++/* Retrieve the maximum number of 32-bit data chunks for a single DE command. */
++gctUINT32
++gco2D_GetMaximumDataCount(
++ void
++ );
++
++/* Retrieve the maximum number of rectangles, that can be passed in a single DE command. */
++gctUINT32
++gco2D_GetMaximumRectCount(
++ void
++ );
++
++/* Returns the pixel alignment of the surface. */
++gceSTATUS
++gco2D_GetPixelAlignment(
++ gceSURF_FORMAT Format,
++ gcsPOINT_PTR Alignment
++ );
++
++/* Retrieve monochrome stream pack size. */
++gceSTATUS
++gco2D_GetPackSize(
++ IN gceSURF_MONOPACK StreamPack,
++ OUT gctUINT32 * PackWidth,
++ OUT gctUINT32 * PackHeight
++ );
++
++/* Flush the 2D pipeline. */
++gceSTATUS
++gco2D_Flush(
++ IN gco2D Engine
++ );
++
++/* Load 256-entry color table for INDEX8 source surfaces. */
++gceSTATUS
++gco2D_LoadPalette(
++ IN gco2D Engine,
++ IN gctUINT FirstIndex,
++ IN gctUINT IndexCount,
++ IN gctPOINTER ColorTable,
++ IN gctBOOL ColorConvert
++ );
++
++/* Enable/disable 2D BitBlt mirrorring. */
++gceSTATUS
++gco2D_SetBitBlitMirror(
++ IN gco2D Engine,
++ IN gctBOOL HorizontalMirror,
++ IN gctBOOL VerticalMirror
++ );
++
++/*
++ * Set the transparency for source, destination and pattern.
++ * It also enable or disable the DFB color key mode.
++ */
++gceSTATUS
++gco2D_SetTransparencyAdvancedEx(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency,
++ IN gctBOOL EnableDFBColorKeyMode
++ );
++
++/* Set the transparency for source, destination and pattern. */
++gceSTATUS
++gco2D_SetTransparencyAdvanced(
++ IN gco2D Engine,
++ IN gce2D_TRANSPARENCY SrcTransparency,
++ IN gce2D_TRANSPARENCY DstTransparency,
++ IN gce2D_TRANSPARENCY PatTransparency
++ );
++
++/* Set the source color key. */
++gceSTATUS
++gco2D_SetSourceColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the source color key range. */
++gceSTATUS
++gco2D_SetSourceColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the target color key. */
++gceSTATUS
++gco2D_SetTargetColorKeyAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKey
++ );
++
++/* Set the target color key range. */
++gceSTATUS
++gco2D_SetTargetColorKeyRangeAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 ColorKeyLow,
++ IN gctUINT32 ColorKeyHigh
++ );
++
++/* Set the YUV color space mode. */
++gceSTATUS
++gco2D_SetYUVColorMode(
++ IN gco2D Engine,
++ IN gce2D_YUV_COLOR_MODE Mode
++ );
++
++/* Setup the source global color value in ARGB8 format. */
++gceSTATUS gco2D_SetSourceGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the target global color value in ARGB8 format. */
++gceSTATUS gco2D_SetTargetGlobalColorAdvanced(
++ IN gco2D Engine,
++ IN gctUINT32 Color32
++ );
++
++/* Setup the source and target pixel multiply modes. */
++gceSTATUS
++gco2D_SetPixelMultiplyModeAdvanced(
++ IN gco2D Engine,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE SrcPremultiplySrcAlpha,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstPremultiplyDstAlpha,
++ IN gce2D_GLOBAL_COLOR_MULTIPLY_MODE SrcPremultiplyGlobalMode,
++ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstDemultiplyDstAlpha
++ );
++
++/* Set the GPU clock cycles after which the idle engine will keep auto-flushing. */
++gceSTATUS
++gco2D_SetAutoFlushCycles(
++ IN gco2D Engine,
++ IN gctUINT32 Cycles
++ );
++
++#if VIVANTE_PROFILER
++/* Read the profile registers available in the 2D engine and sets them in the profile.
++ The function will also reset the pixelsRendered counter every time.
++*/
++gceSTATUS
++gco2D_ProfileEngine(
++ IN gco2D Engine,
++ OPTIONAL gcs2D_PROFILE_PTR Profile
++ );
++#endif
++
++/* Enable or disable 2D dithering. */
++gceSTATUS
++gco2D_EnableDither(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetGenericSource(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetGenericTarget(
++ IN gco2D Engine,
++ IN gctUINT32_PTR Addresses,
++ IN gctUINT32 AddressNum,
++ IN gctUINT32_PTR Strides,
++ IN gctUINT32 StrideNum,
++ IN gceTILING Tiling,
++ IN gceSURF_FORMAT Format,
++ IN gceSURF_ROTATION Rotation,
++ IN gctUINT32 SurfaceWidth,
++ IN gctUINT32 SurfaceHeight
++);
++
++gceSTATUS
++gco2D_SetCurrentSourceIndex(
++ IN gco2D Engine,
++ IN gctUINT32 SrcIndex
++ );
++
++gceSTATUS
++gco2D_MultiSourceBlit(
++ IN gco2D Engine,
++ IN gctUINT32 SourceMask,
++ IN gcsRECT_PTR DestRect,
++ IN gctUINT32 RectCount
++ );
++
++gceSTATUS
++gco2D_SetROP(
++ IN gco2D Engine,
++ IN gctUINT8 FgRop,
++ IN gctUINT8 BgRop
++ );
++
++gceSTATUS
++gco2D_SetGdiStretchMode(
++ IN gco2D Engine,
++ IN gctBOOL Enable
++ );
++
++gceSTATUS
++gco2D_SetSourceTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TSControl,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_SetTargetTileStatus(
++ IN gco2D Engine,
++ IN gce2D_TILE_STATUS_CONFIG TileStatusConfig,
++ IN gceSURF_FORMAT CompressedFormat,
++ IN gctUINT32 ClearValue,
++ IN gctUINT32 GpuAddress
++ );
++
++gceSTATUS
++gco2D_QueryU32(
++ IN gco2D Engine,
++ IN gce2D_QUERY Item,
++ OUT gctUINT32_PTR Value
++ );
++
++gceSTATUS
++gco2D_SetStateU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32 Value
++ );
++
++gceSTATUS
++gco2D_SetStateArrayI32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetStateArrayU32(
++ IN gco2D Engine,
++ IN gce2D_STATE State,
++ IN gctUINT32_PTR Array,
++ IN gctINT32 ArraySize
++ );
++
++gceSTATUS
++gco2D_SetTargetRect(
++ IN gco2D Engine,
++ IN gcsRECT_PTR Rect
++ );
++
++gceSTATUS
++gco2D_Set2DEngine(
++ IN gco2D Engine
++ );
++
++gceSTATUS
++gco2D_UnSet2DEngine(
++ IN gco2D Engine
++ );
++
++gceSTATUS
++gco2D_Get2DEngine(
++ OUT gco2D * Engine
++ );
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_raster_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_rename.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,243 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_rename_h_
++#define __gc_hal_rename_h_
++
++
++#if defined(_HAL2D_APPENDIX)
++
++#define _HAL2D_RENAME_2(api, appendix) api ## appendix
++#define _HAL2D_RENAME_1(api, appendix) _HAL2D_RENAME_2(api, appendix)
++#define gcmHAL2D(api) _HAL2D_RENAME_1(api, _HAL2D_APPENDIX)
++
++
++#define gckOS_Construct gcmHAL2D(gckOS_Construct)
++#define gckOS_Destroy gcmHAL2D(gckOS_Destroy)
++#define gckOS_QueryVideoMemory gcmHAL2D(gckOS_QueryVideoMemory)
++#define gckOS_Allocate gcmHAL2D(gckOS_Allocate)
++#define gckOS_Free gcmHAL2D(gckOS_Free)
++#define gckOS_AllocateMemory gcmHAL2D(gckOS_AllocateMemory)
++#define gckOS_FreeMemory gcmHAL2D(gckOS_FreeMemory)
++#define gckOS_AllocatePagedMemory gcmHAL2D(gckOS_AllocatePagedMemory)
++#define gckOS_AllocatePagedMemoryEx gcmHAL2D(gckOS_AllocatePagedMemoryEx)
++#define gckOS_LockPages gcmHAL2D(gckOS_LockPages)
++#define gckOS_MapPages gcmHAL2D(gckOS_MapPages)
++#define gckOS_UnlockPages gcmHAL2D(gckOS_UnlockPages)
++#define gckOS_FreePagedMemory gcmHAL2D(gckOS_FreePagedMemory)
++#define gckOS_AllocateNonPagedMemory gcmHAL2D(gckOS_AllocateNonPagedMemory)
++#define gckOS_FreeNonPagedMemory gcmHAL2D(gckOS_FreeNonPagedMemory)
++#define gckOS_AllocateContiguous gcmHAL2D(gckOS_AllocateContiguous)
++#define gckOS_FreeContiguous gcmHAL2D(gckOS_FreeContiguous)
++#define gckOS_GetPageSize gcmHAL2D(gckOS_GetPageSize)
++#define gckOS_GetPhysicalAddress gcmHAL2D(gckOS_GetPhysicalAddress)
++#define gckOS_UserLogicalToPhysical gcmHAL2D(gckOS_UserLogicalToPhysical)
++#define gckOS_GetPhysicalAddressProcess gcmHAL2D(gckOS_GetPhysicalAddressProcess)
++#define gckOS_MapPhysical gcmHAL2D(gckOS_MapPhysical)
++#define gckOS_UnmapPhysical gcmHAL2D(gckOS_UnmapPhysical)
++#define gckOS_ReadRegister gcmHAL2D(gckOS_ReadRegister)
++#define gckOS_WriteRegister gcmHAL2D(gckOS_WriteRegister)
++#define gckOS_WriteMemory gcmHAL2D(gckOS_WriteMemory)
++#define gckOS_MapMemory gcmHAL2D(gckOS_MapMemory)
++#define gckOS_UnmapMemory gcmHAL2D(gckOS_UnmapMemory)
++#define gckOS_UnmapMemoryEx gcmHAL2D(gckOS_UnmapMemoryEx)
++#define gckOS_CreateMutex gcmHAL2D(gckOS_CreateMutex)
++#define gckOS_DeleteMutex gcmHAL2D(gckOS_DeleteMutex)
++#define gckOS_AcquireMutex gcmHAL2D(gckOS_AcquireMutex)
++#define gckOS_ReleaseMutex gcmHAL2D(gckOS_ReleaseMutex)
++#define gckOS_AtomicExchange gcmHAL2D(gckOS_AtomicExchange)
++#define gckOS_AtomicExchangePtr gcmHAL2D(gckOS_AtomicExchangePtr)
++#define gckOS_AtomConstruct gcmHAL2D(gckOS_AtomConstruct)
++#define gckOS_AtomDestroy gcmHAL2D(gckOS_AtomDestroy)
++#define gckOS_AtomGet gcmHAL2D(gckOS_AtomGet)
++#define gckOS_AtomIncrement gcmHAL2D(gckOS_AtomIncrement)
++#define gckOS_AtomDecrement gcmHAL2D(gckOS_AtomDecrement)
++#define gckOS_Delay gcmHAL2D(gckOS_Delay)
++#define gckOS_GetTime gcmHAL2D(gckOS_GetTime)
++#define gckOS_MemoryBarrier gcmHAL2D(gckOS_MemoryBarrier)
++#define gckOS_MapUserPointer gcmHAL2D(gckOS_MapUserPointer)
++#define gckOS_UnmapUserPointer gcmHAL2D(gckOS_UnmapUserPointer)
++#define gckOS_QueryNeedCopy gcmHAL2D(gckOS_QueryNeedCopy)
++#define gckOS_CopyFromUserData gcmHAL2D(gckOS_CopyFromUserData)
++#define gckOS_CopyToUserData gcmHAL2D(gckOS_CopyToUserData)
++#define gckOS_SuspendInterrupt gcmHAL2D(gckOS_SuspendInterrupt)
++#define gckOS_ResumeInterrupt gcmHAL2D(gckOS_ResumeInterrupt)
++#define gckOS_GetBaseAddress gcmHAL2D(gckOS_GetBaseAddress)
++#define gckOS_MemCopy gcmHAL2D(gckOS_MemCopy)
++#define gckOS_ZeroMemory gcmHAL2D(gckOS_ZeroMemory)
++#define gckOS_DeviceControl gcmHAL2D(gckOS_DeviceControl)
++#define gckOS_GetProcessID gcmHAL2D(gckOS_GetProcessID)
++#define gckOS_GetThreadID gcmHAL2D(gckOS_GetThreadID)
++#define gckOS_CreateSignal gcmHAL2D(gckOS_CreateSignal)
++#define gckOS_DestroySignal gcmHAL2D(gckOS_DestroySignal)
++#define gckOS_Signal gcmHAL2D(gckOS_Signal)
++#define gckOS_WaitSignal gcmHAL2D(gckOS_WaitSignal)
++#define gckOS_MapSignal gcmHAL2D(gckOS_MapSignal)
++#define gckOS_MapUserMemory gcmHAL2D(gckOS_MapUserMemory)
++#define gckOS_UnmapUserMemory gcmHAL2D(gckOS_UnmapUserMemory)
++#define gckOS_CreateUserSignal gcmHAL2D(gckOS_CreateUserSignal)
++#define gckOS_DestroyUserSignal gcmHAL2D(gckOS_DestroyUserSignal)
++#define gckOS_WaitUserSignal gcmHAL2D(gckOS_WaitUserSignal)
++#define gckOS_SignalUserSignal gcmHAL2D(gckOS_SignalUserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal)
++#define gckOS_CacheClean gcmHAL2D(gckOS_CacheClean)
++#define gckOS_CacheFlush gcmHAL2D(gckOS_CacheFlush)
++#define gckOS_SetDebugLevel gcmHAL2D(gckOS_SetDebugLevel)
++#define gckOS_SetDebugZone gcmHAL2D(gckOS_SetDebugZone)
++#define gckOS_SetDebugLevelZone gcmHAL2D(gckOS_SetDebugLevelZone)
++#define gckOS_SetDebugZones gcmHAL2D(gckOS_SetDebugZones)
++#define gckOS_SetDebugFile gcmHAL2D(gckOS_SetDebugFile)
++#define gckOS_Broadcast gcmHAL2D(gckOS_Broadcast)
++#define gckOS_SetGPUPower gcmHAL2D(gckOS_SetGPUPower)
++#define gckOS_CreateSemaphore gcmHAL2D(gckOS_CreateSemaphore)
++#define gckOS_DestroySemaphore gcmHAL2D(gckOS_DestroySemaphore)
++#define gckOS_AcquireSemaphore gcmHAL2D(gckOS_AcquireSemaphore)
++#define gckOS_ReleaseSemaphore gcmHAL2D(gckOS_ReleaseSemaphore)
++#define gckHEAP_Construct gcmHAL2D(gckHEAP_Construct)
++#define gckHEAP_Destroy gcmHAL2D(gckHEAP_Destroy)
++#define gckHEAP_Allocate gcmHAL2D(gckHEAP_Allocate)
++#define gckHEAP_Free gcmHAL2D(gckHEAP_Free)
++#define gckHEAP_ProfileStart gcmHAL2D(gckHEAP_ProfileStart)
++#define gckHEAP_ProfileEnd gcmHAL2D(gckHEAP_ProfileEnd)
++#define gckHEAP_Test gcmHAL2D(gckHEAP_Test)
++#define gckVIDMEM_Construct gcmHAL2D(gckVIDMEM_Construct)
++#define gckVIDMEM_Destroy gcmHAL2D(gckVIDMEM_Destroy)
++#define gckVIDMEM_Allocate gcmHAL2D(gckVIDMEM_Allocate)
++#define gckVIDMEM_AllocateLinear gcmHAL2D(gckVIDMEM_AllocateLinear)
++#define gckVIDMEM_Free gcmHAL2D(gckVIDMEM_Free)
++#define gckVIDMEM_Lock gcmHAL2D(gckVIDMEM_Lock)
++#define gckVIDMEM_Unlock gcmHAL2D(gckVIDMEM_Unlock)
++#define gckVIDMEM_ConstructVirtual gcmHAL2D(gckVIDMEM_ConstructVirtual)
++#define gckVIDMEM_DestroyVirtual gcmHAL2D(gckVIDMEM_DestroyVirtual)
++#define gckKERNEL_Construct gcmHAL2D(gckKERNEL_Construct)
++#define gckKERNEL_Destroy gcmHAL2D(gckKERNEL_Destroy)
++#define gckKERNEL_Dispatch gcmHAL2D(gckKERNEL_Dispatch)
++#define gckKERNEL_QueryVideoMemory gcmHAL2D(gckKERNEL_QueryVideoMemory)
++#define gckKERNEL_GetVideoMemoryPool gcmHAL2D(gckKERNEL_GetVideoMemoryPool)
++#define gckKERNEL_MapVideoMemory gcmHAL2D(gckKERNEL_MapVideoMemory)
++#define gckKERNEL_UnmapVideoMemory gcmHAL2D(gckKERNEL_UnmapVideoMemory)
++#define gckKERNEL_MapMemory gcmHAL2D(gckKERNEL_MapMemory)
++#define gckKERNEL_UnmapMemory gcmHAL2D(gckKERNEL_UnmapMemory)
++#define gckKERNEL_Notify gcmHAL2D(gckKERNEL_Notify)
++#define gckKERNEL_QuerySettings gcmHAL2D(gckKERNEL_QuerySettings)
++#define gckKERNEL_Recovery gcmHAL2D(gckKERNEL_Recovery)
++#define gckKERNEL_OpenUserData gcmHAL2D(gckKERNEL_OpenUserData)
++#define gckKERNEL_CloseUserData gcmHAL2D(gckKERNEL_CloseUserData)
++#define gckHARDWARE_Construct gcmHAL2D(gckHARDWARE_Construct)
++#define gckHARDWARE_Destroy gcmHAL2D(gckHARDWARE_Destroy)
++#define gckHARDWARE_QuerySystemMemory gcmHAL2D(gckHARDWARE_QuerySystemMemory)
++#define gckHARDWARE_BuildVirtualAddress gcmHAL2D(gckHARDWARE_BuildVirtualAddress)
++#define gckHARDWARE_QueryCommandBuffer gcmHAL2D(gckHARDWARE_QueryCommandBuffer)
++#define gckHARDWARE_WaitLink gcmHAL2D(gckHARDWARE_WaitLink)
++#define gckHARDWARE_Execute gcmHAL2D(gckHARDWARE_Execute)
++#define gckHARDWARE_End gcmHAL2D(gckHARDWARE_End)
++#define gckHARDWARE_Nop gcmHAL2D(gckHARDWARE_Nop)
++#define gckHARDWARE_PipeSelect gcmHAL2D(gckHARDWARE_PipeSelect)
++#define gckHARDWARE_Link gcmHAL2D(gckHARDWARE_Link)
++#define gckHARDWARE_Event gcmHAL2D(gckHARDWARE_Event)
++#define gckHARDWARE_QueryMemory gcmHAL2D(gckHARDWARE_QueryMemory)
++#define gckHARDWARE_QueryChipIdentity gcmHAL2D(gckHARDWARE_QueryChipIdentity)
++#define gckHARDWARE_QueryChipSpecs gcmHAL2D(gckHARDWARE_QueryChipSpecs)
++#define gckHARDWARE_QueryShaderCaps gcmHAL2D(gckHARDWARE_QueryShaderCaps)
++#define gckHARDWARE_ConvertFormat gcmHAL2D(gckHARDWARE_ConvertFormat)
++#define gckHARDWARE_SplitMemory gcmHAL2D(gckHARDWARE_SplitMemory)
++#define gckHARDWARE_AlignToTile gcmHAL2D(gckHARDWARE_AlignToTile)
++#define gckHARDWARE_UpdateQueueTail gcmHAL2D(gckHARDWARE_UpdateQueueTail)
++#define gckHARDWARE_ConvertLogical gcmHAL2D(gckHARDWARE_ConvertLogical)
++#define gckHARDWARE_Interrupt gcmHAL2D(gckHARDWARE_Interrupt)
++#define gckHARDWARE_SetMMU gcmHAL2D(gckHARDWARE_SetMMU)
++#define gckHARDWARE_FlushMMU gcmHAL2D(gckHARDWARE_FlushMMU)
++#define gckHARDWARE_GetIdle gcmHAL2D(gckHARDWARE_GetIdle)
++#define gckHARDWARE_Flush gcmHAL2D(gckHARDWARE_Flush)
++#define gckHARDWARE_SetFastClear gcmHAL2D(gckHARDWARE_SetFastClear)
++#define gckHARDWARE_ReadInterrupt gcmHAL2D(gckHARDWARE_ReadInterrupt)
++#define gckHARDWARE_SetPowerManagementState gcmHAL2D(gckHARDWARE_SetPowerManagementState)
++#define gckHARDWARE_QueryPowerManagementState gcmHAL2D(gckHARDWARE_QueryPowerManagementState)
++#define gckHARDWARE_ProfileEngine2D gcmHAL2D(gckHARDWARE_ProfileEngine2D)
++#define gckHARDWARE_InitializeHardware gcmHAL2D(gckHARDWARE_InitializeHardware)
++#define gckHARDWARE_Reset gcmHAL2D(gckHARDWARE_Reset)
++#define gckINTERRUPT_Construct gcmHAL2D(gckINTERRUPT_Construct)
++#define gckINTERRUPT_Destroy gcmHAL2D(gckINTERRUPT_Destroy)
++#define gckINTERRUPT_SetHandler gcmHAL2D(gckINTERRUPT_SetHandler)
++#define gckINTERRUPT_Notify gcmHAL2D(gckINTERRUPT_Notify)
++#define gckEVENT_Construct gcmHAL2D(gckEVENT_Construct)
++#define gckEVENT_Destroy gcmHAL2D(gckEVENT_Destroy)
++#define gckEVENT_AddList gcmHAL2D(gckEVENT_AddList)
++#define gckEVENT_FreeNonPagedMemory gcmHAL2D(gckEVENT_FreeNonPagedMemory)
++#define gckEVENT_FreeContiguousMemory gcmHAL2D(gckEVENT_FreeContiguousMemory)
++#define gckEVENT_FreeVideoMemory gcmHAL2D(gckEVENT_FreeVideoMemory)
++#define gckEVENT_Signal gcmHAL2D(gckEVENT_Signal)
++#define gckEVENT_Unlock gcmHAL2D(gckEVENT_Unlock)
++#define gckEVENT_Submit gcmHAL2D(gckEVENT_Submit)
++#define gckEVENT_Commit gcmHAL2D(gckEVENT_Commit)
++#define gckEVENT_Notify gcmHAL2D(gckEVENT_Notify)
++#define gckEVENT_Interrupt gcmHAL2D(gckEVENT_Interrupt)
++#define gckCOMMAND_Construct gcmHAL2D(gckCOMMAND_Construct)
++#define gckCOMMAND_Destroy gcmHAL2D(gckCOMMAND_Destroy)
++#define gckCOMMAND_EnterCommit gcmHAL2D(gckCOMMAND_EnterCommit)
++#define gckCOMMAND_ExitCommit gcmHAL2D(gckCOMMAND_ExitCommit)
++#define gckCOMMAND_Start gcmHAL2D(gckCOMMAND_Start)
++#define gckCOMMAND_Stop gcmHAL2D(gckCOMMAND_Stop)
++#define gckCOMMAND_Commit gcmHAL2D(gckCOMMAND_Commit)
++#define gckCOMMAND_Reserve gcmHAL2D(gckCOMMAND_Reserve)
++#define gckCOMMAND_Execute gcmHAL2D(gckCOMMAND_Execute)
++#define gckCOMMAND_Stall gcmHAL2D(gckCOMMAND_Stall)
++#define gckCOMMAND_Attach gcmHAL2D(gckCOMMAND_Attach)
++#define gckCOMMAND_Detach gcmHAL2D(gckCOMMAND_Detach)
++#define gckMMU_Construct gcmHAL2D(gckMMU_Construct)
++#define gckMMU_Destroy gcmHAL2D(gckMMU_Destroy)
++#define gckMMU_AllocatePages gcmHAL2D(gckMMU_AllocatePages)
++#define gckMMU_FreePages gcmHAL2D(gckMMU_FreePages)
++#define gckMMU_Test gcmHAL2D(gckMMU_Test)
++#define gckHARDWARE_QueryProfileRegisters gcmHAL2D(gckHARDWARE_QueryProfileRegisters)
++
++
++#define FindMdlMap gcmHAL2D(FindMdlMap)
++#define OnProcessExit gcmHAL2D(OnProcessExit)
++
++#define gckGALDEVICE_Destroy gcmHAL2D(gckGALDEVICE_Destroy)
++#define gckOS_Print gcmHAL2D(gckOS_Print)
++#define gckGALDEVICE_FreeMemory gcmHAL2D(gckGALDEVICE_FreeMemory)
++#define gckGALDEVICE_AllocateMemory gcmHAL2D(gckGALDEVICE_AllocateMemory)
++#define gckOS_DebugBreak gcmHAL2D(gckOS_DebugBreak)
++#define gckGALDEVICE_Release_ISR gcmHAL2D(gckGALDEVICE_Release_ISR)
++#define gckOS_Verify gcmHAL2D(gckOS_Verify)
++#define gckCOMMAND_Release gcmHAL2D(gckCOMMAND_Release)
++#define gckGALDEVICE_Stop gcmHAL2D(gckGALDEVICE_Stop)
++#define gckGALDEVICE_Construct gcmHAL2D(gckGALDEVICE_Construct)
++#define gckOS_DebugFatal gcmHAL2D(gckOS_DebugFatal)
++#define gckOS_DebugTrace gcmHAL2D(gckOS_DebugTrace)
++#define gckHARDWARE_GetBaseAddress gcmHAL2D(gckHARDWARE_GetBaseAddress)
++#define gckGALDEVICE_Setup_ISR gcmHAL2D(gckGALDEVICE_Setup_ISR)
++#define gckKERNEL_AttachProcess gcmHAL2D(gckKERNEL_AttachProcess)
++#define gckKERNEL_AttachProcessEx gcmHAL2D(gckKERNEL_AttachProcessEx)
++#define gckGALDEVICE_Start_Thread gcmHAL2D(gckGALDEVICE_Start_Thread)
++#define gckHARDWARE_QueryIdle gcmHAL2D(gckHARDWARE_QueryIdle)
++#define gckGALDEVICE_Start gcmHAL2D(gckGALDEVICE_Start)
++#define gckOS_GetKernelLogical gcmHAL2D(gckOS_GetKernelLogical)
++#define gckOS_DebugTraceZone gcmHAL2D(gckOS_DebugTraceZone)
++#define gckGALDEVICE_Stop_Thread gcmHAL2D(gckGALDEVICE_Stop_Thread)
++#define gckHARDWARE_NeedBaseAddress gcmHAL2D(gckHARDWARE_NeedBaseAddress)
++
++#endif
++
++#endif /* __gc_hal_rename_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_security_interface.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,137 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef _GC_HAL_SECURITY_INTERFACE_H_
++#define _GC_HAL_SECURITY_INTERFACE_H_
++/*!
++ @brief Command codes between kernel module and TrustZone
++ @discussion
++ Critical services must be done in TrustZone to avoid sensitive content leak. Most of kernel module is kept in non-Secure os to minimize
++ code in TrustZone.
++ */
++typedef enum kernel_packet_command {
++ KERNEL_START_COMMAND,
++ KERNEL_SUBMIT,
++ KERNEL_MAP_MEMORY, /* */
++ KERNEL_UNMAP_MEMORY,
++ KERNEL_ALLOCATE_SECRUE_MEMORY, /*! Security memory management. */
++ KERNEL_FREE_SECURE_MEMORY,
++ KERNEL_EXECUTE, /* Execute a command buffer. */
++} kernel_packet_command_t;
++
++/*!
++ @brief gckCOMMAND Object requests TrustZone to start FE.
++ @discussion
++ DMA enabled register can only be written in TrustZone to avoid GPU from jumping to a hacked code.
++ Kernel module need use these command to ask TrustZone start command parser.
++ */
++struct kernel_start_command {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT8 gpu; /*! Which GPU. */
++};
++
++/*!
++ @brief gckCOMMAND Object requests TrustZone to submit command buffer.
++ @discussion
++ Code in trustzone will check content of command buffer after copying command buffer to TrustZone.
++ */
++struct kernel_submit {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT8 gpu; /*! Which GPU. */
++ gctUINT8 kernel_command; /*! Whether it is a kernel command. */
++ gctUINT32 command_buffer_handle; /*! Handle to command buffer. */
++ gctUINT32 offset; /* Offset in command buffer. */
++ gctUINT32 * command_buffer; /*! Content of command buffer need to be submit. */
++ gctUINT32 command_buffer_length; /*! Length of command buffer. */
++};
++
++
++/*!
++ @brief gckVIDMEM Object requests TrustZone to allocate security memory.
++ @discussion
++ Allocate a buffer from security GPU memory.
++ */
++struct kernel_allocate_security_memory {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT32 bytes; /*! Requested bytes. */
++ gctUINT32 memory_handle; /*! Handle of allocated memory. */
++};
++
++/*!
++ @brief gckVIDMEM Object requests TrustZone to allocate security memory.
++ @discussion
++ Free a video memory buffer from security GPU memory.
++ */
++struct kernel_free_security_memory {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT32 memory_handle; /*! Handle of allocated memory. */
++};
++
++struct kernel_execute {
++ kernel_packet_command_t command; /*! The command (always needs to be the first entry in a structure). */
++ gctUINT8 gpu; /*! Which GPU. */
++ gctUINT8 kernel_command; /*! Whether it is a kernel command. */
++ gctUINT32 * command_buffer; /*! Content of command buffer need to be submit. */
++ gctUINT32 command_buffer_length; /*! Length of command buffer. */
++};
++
++typedef struct kernel_map_scatter_gather {
++ gctUINT32 bytes;
++ gctUINT32 physical;
++ struct kernel_map_scatter_gather *next;
++}
++kernel_map_scatter_gather_t;
++
++struct kernel_map_memory {
++ kernel_packet_command_t command;
++ kernel_map_scatter_gather_t *scatter;
++ gctUINT32 *physicals;
++ gctUINT32 pageCount;
++ gctUINT32 gpuAddress;
++};
++
++struct kernel_unmap_memory {
++ gctUINT32 gpuAddress;
++ gctUINT32 pageCount;
++};
++
++typedef struct _gcsTA_INTERFACE {
++ kernel_packet_command_t command;
++ union {
++ struct kernel_submit Submit;
++ struct kernel_start_command StartCommand;
++ struct kernel_allocate_security_memory AllocateSecurityMemory;
++ struct kernel_execute Execute;
++ struct kernel_map_memory MapMemory;
++ struct kernel_unmap_memory UnmapMemory;
++ } u;
++ gceSTATUS result;
++} gcsTA_INTERFACE;
++
++enum {
++ gcvTA_COMMAND_INIT,
++ gcvTA_COMMAND_DISPATCH,
++
++ gcvTA_CALLBACK_ALLOC_SECURE_MEM,
++ gcvTA_CALLBACK_FREE_SECURE_MEM,
++};
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_statistics.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,99 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_statistics_h_
++#define __gc_hal_statistics_h_
++
++
++#define VIV_STAT_ENABLE_STATISTICS 0
++
++/* Toal number of frames for which the frame time is accounted. We have storage
++ to keep frame times for last this many frames.
++*/
++#define VIV_STAT_FRAME_BUFFER_SIZE 30
++
++
++/*
++ Total number of frames sampled for a mode. This means
++
++ # of frames for HZ Current : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ # of frames for HZ Switched : VIV_STAT_EARLY_Z_SAMPLE_FRAMES
++ +
++ --------------------------------------------------------
++ : (2 * VIV_STAT_EARLY_Z_SAMPLE_FRAMES) frames needed
++
++ IMPORTANT: This total must be smaller than VIV_STAT_FRAME_BUFFER_SIZE
++*/
++#define VIV_STAT_EARLY_Z_SAMPLE_FRAMES 7
++#define VIV_STAT_EARLY_Z_LATENCY_FRAMES 2
++
++/* Multiplication factor for previous Hz off mode. Make it more than 1.0 to advertise HZ on.*/
++#define VIV_STAT_EARLY_Z_FACTOR (1.05f)
++
++/* Defines the statistical data keys monitored by the statistics module */
++typedef enum _gceSTATISTICS
++{
++ gcvFRAME_FPS = 1,
++}
++gceSTATISTICS;
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS_EARLYZ
++{
++ gctUINT switchBackCount;
++ gctUINT nextCheckPoint;
++ gctBOOL disabled;
++}
++gcsSTATISTICS_EARLYZ;
++
++
++/* HAL statistics information. */
++typedef struct _gcsSTATISTICS
++{
++ gctUINT64 frameTime[VIV_STAT_FRAME_BUFFER_SIZE];
++ gctUINT64 previousFrameTime;
++ gctUINT frame;
++ gcsSTATISTICS_EARLYZ earlyZ;
++}
++gcsSTATISTICS;
++
++
++/* Add a frame based data into current statistics. */
++void
++gcfSTATISTICS_AddData(
++ IN gceSTATISTICS Key,
++ IN gctUINT Value
++ );
++
++/* Marks the frame end and triggers statistical calculations and decisions.*/
++void
++gcfSTATISTICS_MarkFrameEnd (
++ void
++ );
++
++/* Sets whether the dynmaic HZ is disabled or not .*/
++void
++gcfSTATISTICS_DisableDynamicEarlyZ (
++ IN gctBOOL Disabled
++ );
++
++#endif /*__gc_hal_statistics_h_ */
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_types.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,932 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_types_h_
++#define __gc_hal_types_h_
++
++#include "gc_hal_version.h"
++#include "gc_hal_options.h"
++
++#if !defined(VIV_KMD)
++#if defined(__KERNEL__)
++#include "linux/version.h"
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
++ typedef unsigned long uintptr_t;
++# endif
++# include "linux/types.h"
++#elif defined(UNDER_CE)
++#include <crtdefs.h>
++#elif defined(_MSC_VER) && (_MSC_VER <= 1500)
++#include <crtdefs.h>
++#include "vadefs.h"
++#elif defined(__QNXNTO__)
++#define _QNX_SOURCE
++#include <stdint.h>
++#include <stddef.h>
++#else
++#include <stdlib.h>
++#include <stddef.h>
++#include <stdint.h>
++#endif
++#endif
++
++#ifdef _WIN32
++#pragma warning(disable:4127) /* Conditional expression is constant (do { }
++ ** while(0)). */
++#pragma warning(disable:4100) /* Unreferenced formal parameter. */
++#pragma warning(disable:4204) /* Non-constant aggregate initializer (C99). */
++#pragma warning(disable:4131) /* Uses old-style declarator (for Bison and
++ ** Flex generated files). */
++#pragma warning(disable:4206) /* Translation unit is empty. */
++#pragma warning(disable:4214) /* Nonstandard extension used :
++ ** bit field types other than int. */
++#endif
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++** Platform macros.
++*/
++
++#if defined(__GNUC__)
++# define gcdHAS_ELLIPSIS 1 /* GCC always has it. */
++#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)
++# define gcdHAS_ELLIPSIS 1 /* C99 has it. */
++#elif defined(_MSC_VER) && (_MSC_VER >= 1500)
++# define gcdHAS_ELLIPSIS 1 /* MSVC 2007+ has it. */
++#elif defined(UNDER_CE)
++#if UNDER_CE >= 600
++# define gcdHAS_ELLIPSIS 1
++# else
++# define gcdHAS_ELLIPSIS 0
++# endif
++#else
++# error "gcdHAS_ELLIPSIS: Platform could not be determined"
++#endif
++
++/******************************************************************************\
++************************************ Keyword ***********************************
++\******************************************************************************/
++#if defined(ANDROID) && defined(__BIONIC_FORTIFY)
++# define gcmINLINE __inline__ __attribute__ ((always_inline)) __attribute__ ((gnu_inline)) __attribute__ ((artificial))
++#elif ((defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L)) || defined(__APPLE__))
++# define gcmINLINE inline /* C99 keyword. */
++#elif defined(__GNUC__)
++# define gcmINLINE __inline__ /* GNU keyword. */
++#elif defined(_MSC_VER) || defined(UNDER_CE)
++# define gcmINLINE __inline /* Internal keyword. */
++#else
++# error "gcmINLINE: Platform could not be determined"
++#endif
++
++/* Possible debug flags. */
++#define gcdDEBUG_NONE 0
++#define gcdDEBUG_ALL (1 << 0)
++#define gcdDEBUG_FATAL (1 << 1)
++#define gcdDEBUG_TRACE (1 << 2)
++#define gcdDEBUG_BREAK (1 << 3)
++#define gcdDEBUG_ASSERT (1 << 4)
++#define gcdDEBUG_CODE (1 << 5)
++#define gcdDEBUG_STACK (1 << 6)
++
++#define gcmIS_DEBUG(flag) ( gcdDEBUG & (flag | gcdDEBUG_ALL) )
++
++#ifndef gcdDEBUG
++#if (defined(DBG) && DBG) || defined(DEBUG) || defined(_DEBUG)
++# define gcdDEBUG gcdDEBUG_ALL
++# else
++# define gcdDEBUG gcdDEBUG_NONE
++# endif
++#endif
++
++#ifdef _USRDLL
++#ifdef _MSC_VER
++#ifdef HAL_EXPORTS
++# define HALAPI __declspec(dllexport)
++# else
++# define HALAPI __declspec(dllimport)
++# endif
++# define HALDECL __cdecl
++# else
++#ifdef HAL_EXPORTS
++# define HALAPI
++# else
++# define HALAPI extern
++# endif
++# endif
++#else
++# define HALAPI
++# define HALDECL
++#endif
++
++/******************************************************************************\
++********************************** Common Types ********************************
++\******************************************************************************/
++
++#define gcvFALSE 0
++#define gcvTRUE 1
++
++#define gcvINFINITE ((gctUINT32) ~0U)
++
++#define gcvINVALID_HANDLE ((gctHANDLE) ~0U)
++
++typedef int gctBOOL;
++typedef gctBOOL * gctBOOL_PTR;
++
++typedef int gctINT;
++typedef signed char gctINT8;
++typedef signed short gctINT16;
++typedef signed int gctINT32;
++typedef signed long long gctINT64;
++
++typedef gctINT * gctINT_PTR;
++typedef gctINT8 * gctINT8_PTR;
++typedef gctINT16 * gctINT16_PTR;
++typedef gctINT32 * gctINT32_PTR;
++typedef gctINT64 * gctINT64_PTR;
++
++typedef unsigned int gctUINT;
++typedef unsigned char gctUINT8;
++typedef unsigned short gctUINT16;
++typedef unsigned int gctUINT32;
++typedef unsigned long long gctUINT64;
++typedef uintptr_t gctUINTPTR_T;
++
++typedef gctUINT * gctUINT_PTR;
++typedef gctUINT8 * gctUINT8_PTR;
++typedef gctUINT16 * gctUINT16_PTR;
++typedef gctUINT32 * gctUINT32_PTR;
++typedef gctUINT64 * gctUINT64_PTR;
++
++typedef size_t gctSIZE_T;
++typedef gctSIZE_T * gctSIZE_T_PTR;
++typedef gctUINT32 gctTRACE;
++
++#ifdef __cplusplus
++# define gcvNULL 0
++#else
++# define gcvNULL ((void *) 0)
++#endif
++
++#define gcvMAXINT8 0x7f
++#define gcvMININT8 0x80
++#define gcvMAXINT16 0x7fff
++#define gcvMININT16 0x8000
++#define gcvMAXINT32 0x7fffffff
++#define gcvMININT32 0x80000000
++#define gcvMAXINT64 0x7fffffffffffffff
++#define gcvMININT64 0x8000000000000000
++#define gcvMAXUINT8 0xff
++#define gcvMINUINT8 0x0
++#define gcvMAXUINT16 0xffff
++#define gcvMINUINT16 0x8000
++#define gcvMAXUINT32 0xffffffff
++#define gcvMINUINT32 0x80000000
++#define gcvMAXUINT64 0xffffffffffffffff
++#define gcvMINUINT64 0x8000000000000000
++#define gcvMAXUINTPTR_T (~(gctUINTPTR_T)0)
++
++typedef float gctFLOAT;
++typedef signed int gctFIXED_POINT;
++typedef float * gctFLOAT_PTR;
++
++typedef void * gctPHYS_ADDR;
++typedef void * gctHANDLE;
++typedef void * gctFILE;
++typedef void * gctSIGNAL;
++typedef void * gctWINDOW;
++typedef void * gctIMAGE;
++typedef void * gctSYNC_POINT;
++typedef void * gctSHBUF;
++
++typedef void * gctSEMAPHORE;
++
++typedef void * gctPOINTER;
++typedef const void * gctCONST_POINTER;
++
++typedef char gctCHAR;
++typedef char * gctSTRING;
++typedef const char * gctCONST_STRING;
++
++typedef struct _gcsCOUNT_STRING
++{
++ gctSIZE_T Length;
++ gctCONST_STRING String;
++}
++gcsCOUNT_STRING;
++
++typedef union _gcuFLOAT_UINT32
++{
++ gctFLOAT f;
++ gctUINT32 u;
++}
++gcuFLOAT_UINT32;
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++
++
++#define gcmFIXEDCLAMP_NEG1_TO_1(_x) \
++ (((_x) < gcvNEGONE_X) \
++ ? gcvNEGONE_X \
++ : (((_x) > gcvONE_X) \
++ ? gcvONE_X \
++ : (_x)))
++
++#define gcmFLOATCLAMP_NEG1_TO_1(_f) \
++ (((_f) < -1.0f) \
++ ? -1.0f \
++ : (((_f) > 1.0f) \
++ ? 1.0f \
++ : (_f)))
++
++
++#define gcmFIXEDCLAMP_0_TO_1(_x) \
++ (((_x) < 0) \
++ ? 0 \
++ : (((_x) > gcvONE_X) \
++ ? gcvONE_X \
++ : (_x)))
++
++#define gcmFLOATCLAMP_0_TO_1(_f) \
++ (((_f) < 0.0f) \
++ ? 0.0f \
++ : (((_f) > 1.0f) \
++ ? 1.0f \
++ : (_f)))
++
++
++/******************************************************************************\
++******************************* Multicast Values *******************************
++\******************************************************************************/
++
++/* Value types. */
++typedef enum _gceVALUE_TYPE
++{
++ gcvVALUE_UINT = 0x0,
++ gcvVALUE_FIXED,
++ gcvVALUE_FLOAT,
++ gcvVALUE_INT,
++
++ /*
++ ** The value need be unsigned denormalized. clamp (0.0-1.0) should be done first.
++ */
++ gcvVALUE_FLAG_UNSIGNED_DENORM = 0x00010000,
++
++ /*
++ ** The value need be signed denormalized. clamp (-1.0-1.0) should be done first.
++ */
++ gcvVALUE_FLAG_SIGNED_DENORM = 0x00020000,
++
++ /*
++ ** The value need to gammar
++ */
++ gcvVALUE_FLAG_GAMMAR = 0x00040000,
++
++ /*
++ ** The value need to convert from float to float16
++ */
++ gcvVALUE_FLAG_FLOAT_TO_FLOAT16 = 0x0080000,
++
++ /*
++ ** Mask for flag field.
++ */
++ gcvVALUE_FLAG_MASK = 0xFFFF0000,
++}
++gceVALUE_TYPE;
++
++/* Value unions. */
++typedef union _gcuVALUE
++{
++ gctUINT uintValue;
++ gctFIXED_POINT fixedValue;
++ gctFLOAT floatValue;
++ gctINT intValue;
++}
++gcuVALUE;
++
++
++
++
++/* Stringizing macro. */
++#define gcmSTRING(Value) #Value
++
++/******************************************************************************\
++******************************* Fixed Point Math *******************************
++\******************************************************************************/
++
++#define gcmXMultiply(x1, x2) gcoMATH_MultiplyFixed(x1, x2)
++#define gcmXDivide(x1, x2) gcoMATH_DivideFixed(x1, x2)
++#define gcmXMultiplyDivide(x1, x2, x3) gcoMATH_MultiplyDivideFixed(x1, x2, x3)
++
++/* 2D Engine profile. */
++typedef struct _gcs2D_PROFILE
++{
++ /* Cycle count.
++ 32bit counter incremented every 2D clock cycle.
++ Wraps back to 0 when the counter overflows.
++ */
++ gctUINT32 cycleCount;
++
++ /* Pixels rendered by the 2D engine.
++ Resets to 0 every time it is read. */
++ gctUINT32 pixelsRendered;
++}
++gcs2D_PROFILE;
++
++/* Macro to combine four characters into a Charcater Code. */
++#define gcmCC(c1, c2, c3, c4) \
++( \
++ (char) (c1) \
++ | \
++ ((char) (c2) << 8) \
++ | \
++ ((char) (c3) << 16) \
++ | \
++ ((char) (c4) << 24) \
++)
++
++#define gcmPRINTABLE(c) ((((c) >= ' ') && ((c) <= '}')) ? ((c) != '%' ? (c) : ' ') : ' ')
++
++#define gcmCC_PRINT(cc) \
++ gcmPRINTABLE((char) ( (cc) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 8) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 16) & 0xFF)), \
++ gcmPRINTABLE((char) (((cc) >> 24) & 0xFF))
++
++/******************************************************************************\
++****************************** Function Parameters *****************************
++\******************************************************************************/
++
++#define IN
++#define OUT
++#define INOUT
++#define OPTIONAL
++
++/******************************************************************************\
++********************************* Status Codes *********************************
++\******************************************************************************/
++
++typedef enum _gceSTATUS
++{
++ gcvSTATUS_OK = 0,
++ gcvSTATUS_FALSE = 0,
++ gcvSTATUS_TRUE = 1,
++ gcvSTATUS_NO_MORE_DATA = 2,
++ gcvSTATUS_CACHED = 3,
++ gcvSTATUS_MIPMAP_TOO_LARGE = 4,
++ gcvSTATUS_NAME_NOT_FOUND = 5,
++ gcvSTATUS_NOT_OUR_INTERRUPT = 6,
++ gcvSTATUS_MISMATCH = 7,
++ gcvSTATUS_MIPMAP_TOO_SMALL = 8,
++ gcvSTATUS_LARGER = 9,
++ gcvSTATUS_SMALLER = 10,
++ gcvSTATUS_CHIP_NOT_READY = 11,
++ gcvSTATUS_NEED_CONVERSION = 12,
++ gcvSTATUS_SKIP = 13,
++ gcvSTATUS_DATA_TOO_LARGE = 14,
++ gcvSTATUS_INVALID_CONFIG = 15,
++ gcvSTATUS_CHANGED = 16,
++ gcvSTATUS_NOT_SUPPORT_DITHER = 17,
++ gcvSTATUS_EXECUTED = 18,
++ gcvSTATUS_TERMINATE = 19,
++
++ gcvSTATUS_INVALID_ARGUMENT = -1,
++ gcvSTATUS_INVALID_OBJECT = -2,
++ gcvSTATUS_OUT_OF_MEMORY = -3,
++ gcvSTATUS_MEMORY_LOCKED = -4,
++ gcvSTATUS_MEMORY_UNLOCKED = -5,
++ gcvSTATUS_HEAP_CORRUPTED = -6,
++ gcvSTATUS_GENERIC_IO = -7,
++ gcvSTATUS_INVALID_ADDRESS = -8,
++ gcvSTATUS_CONTEXT_LOSSED = -9,
++ gcvSTATUS_TOO_COMPLEX = -10,
++ gcvSTATUS_BUFFER_TOO_SMALL = -11,
++ gcvSTATUS_INTERFACE_ERROR = -12,
++ gcvSTATUS_NOT_SUPPORTED = -13,
++ gcvSTATUS_MORE_DATA = -14,
++ gcvSTATUS_TIMEOUT = -15,
++ gcvSTATUS_OUT_OF_RESOURCES = -16,
++ gcvSTATUS_INVALID_DATA = -17,
++ gcvSTATUS_INVALID_MIPMAP = -18,
++ gcvSTATUS_NOT_FOUND = -19,
++ gcvSTATUS_NOT_ALIGNED = -20,
++ gcvSTATUS_INVALID_REQUEST = -21,
++ gcvSTATUS_GPU_NOT_RESPONDING = -22,
++ gcvSTATUS_TIMER_OVERFLOW = -23,
++ gcvSTATUS_VERSION_MISMATCH = -24,
++ gcvSTATUS_LOCKED = -25,
++ gcvSTATUS_INTERRUPTED = -26,
++ gcvSTATUS_DEVICE = -27,
++ gcvSTATUS_NOT_MULTI_PIPE_ALIGNED = -28,
++
++ /* Linker errors. */
++ gcvSTATUS_GLOBAL_TYPE_MISMATCH = -1000,
++ gcvSTATUS_TOO_MANY_ATTRIBUTES = -1001,
++ gcvSTATUS_TOO_MANY_UNIFORMS = -1002,
++ gcvSTATUS_TOO_MANY_VARYINGS = -1003,
++ gcvSTATUS_UNDECLARED_VARYING = -1004,
++ gcvSTATUS_VARYING_TYPE_MISMATCH = -1005,
++ gcvSTATUS_MISSING_MAIN = -1006,
++ gcvSTATUS_NAME_MISMATCH = -1007,
++ gcvSTATUS_INVALID_INDEX = -1008,
++ gcvSTATUS_UNIFORM_MISMATCH = -1009,
++ gcvSTATUS_UNSAT_LIB_SYMBOL = -1010,
++ gcvSTATUS_TOO_MANY_SHADERS = -1011,
++ gcvSTATUS_LINK_INVALID_SHADERS = -1012,
++ gcvSTATUS_CS_NO_WORKGROUP_SIZE = -1013,
++ gcvSTATUS_LINK_LIB_ERROR = -1014,
++ gcvSTATUS_SHADER_VERSION_MISMATCH = -1015,
++ gcvSTATUS_TOO_MANY_INSTRUCTION = -1016,
++ gcvSTATUS_SSBO_MISMATCH = -1017,
++ gcvSTATUS_TOO_MANY_OUTPUT = -1018,
++ gcvSTATUS_TOO_MANY_INPUT = -1019,
++ gcvSTATUS_NOT_SUPPORT_CL = -1020,
++ gcvSTATUS_NOT_SUPPORT_INTEGER = -1021,
++ gcvSTATUS_UNIFORM_TYPE_MISMATCH = -1022,
++ gcvSTATUS_TOO_MANY_SAMPLER = -1023,
++
++ /* Compiler errors. */
++ gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR = -2000,
++ gcvSTATUS_COMPILER_FE_PARSER_ERROR = -2001,
++
++ /* Recompilation Errors */
++ gcvSTATUS_RECOMPILER_CONVERT_UNIMPLEMENTED = -3000,
++}
++gceSTATUS;
++
++/******************************************************************************\
++********************************* Status Macros ********************************
++\******************************************************************************/
++
++#define gcmIS_ERROR(status) (status < 0)
++#define gcmNO_ERROR(status) (status >= 0)
++#define gcmIS_SUCCESS(status) (status == gcvSTATUS_OK)
++
++/******************************************************************************\
++********************************* Field Macros *********************************
++\******************************************************************************/
++
++#define __gcmSTART(reg_field) \
++ (0 ? reg_field)
++
++#define __gcmEND(reg_field) \
++ (1 ? reg_field)
++
++#define __gcmGETSIZE(reg_field) \
++ (__gcmEND(reg_field) - __gcmSTART(reg_field) + 1)
++
++#define __gcmALIGN(data, reg_field) \
++ (((gctUINT32) (data)) << __gcmSTART(reg_field))
++
++#define __gcmMASK(reg_field) \
++ ((gctUINT32) ((__gcmGETSIZE(reg_field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg_field)))))
++
++/*******************************************************************************
++**
++** gcmFIELDMASK
++**
++** Get aligned field mask.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMASK(reg, field) \
++( \
++ __gcmALIGN(__gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETFIELD
++**
++** Extract the value of a field from specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETFIELD(data, reg, field) \
++( \
++ ((((gctUINT32) (data)) >> __gcmSTART(reg##_##field)) \
++ & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELD
++**
++** Set the value of a field within specified data.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETFIELD(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN((gctUINT32) (value) \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmSETFIELDVALUE
++**
++** Set the value of a field within specified data with a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmSETFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) \
++ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \
++ | __gcmALIGN(reg##_##field##_##value \
++ & __gcmMASK(reg##_##field), reg##_##field) \
++)
++
++/*******************************************************************************
++**
++** gcmGETMASKEDFIELDMASK
++**
++** Determine field mask of a masked field.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmGETMASKEDFIELDMASK(reg, field) \
++( \
++ gcmSETFIELD(0, reg, field, ~0) | \
++ gcmSETFIELD(0, reg, MASK_ ## field, ~0) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELD
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELD(reg, field, value) \
++( \
++ gcmSETFIELD (~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmSETMASKEDFIELDVALUE
++**
++** Set the value of a masked field with specified data.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmSETMASKEDFIELDVALUE(reg, field, value) \
++( \
++ gcmSETFIELDVALUE(~0, reg, field, value) & \
++ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \
++)
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDVALUE
++**
++** Verify if the value of a field within specified data equals a
++** predefined value.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Name of the value within the field.
++*/
++#define gcmVERIFYFIELDVALUE(data, reg, field, value) \
++( \
++ (((gctUINT32) (data)) >> __gcmSTART(reg##_##field) & \
++ __gcmMASK(reg##_##field)) \
++ == \
++ (reg##_##field##_##value & __gcmMASK(reg##_##field)) \
++)
++
++/*******************************************************************************
++** Bit field macros.
++*/
++
++#define __gcmSTARTBIT(Field) \
++ ( 1 ? Field )
++
++#define __gcmBITSIZE(Field) \
++ ( 0 ? Field )
++
++#define __gcmBITMASK(Field) \
++( \
++ (1 << __gcmBITSIZE(Field)) - 1 \
++)
++
++#define gcmGETBITS(Value, Type, Field) \
++( \
++ ( ((Type) (Value)) >> __gcmSTARTBIT(Field) ) \
++ & \
++ __gcmBITMASK(Field) \
++)
++
++#define gcmSETBITS(Value, Type, Field, NewValue) \
++( \
++ ( ((Type) (Value)) \
++ & ~(__gcmBITMASK(Field) << __gcmSTARTBIT(Field)) \
++ ) \
++ | \
++ ( ( ((Type) (NewValue)) \
++ & __gcmBITMASK(Field) \
++ ) << __gcmSTARTBIT(Field) \
++ ) \
++)
++
++/*******************************************************************************
++**
++** gcmISINREGRANGE
++**
++** Verify whether the specified address is in the register range.
++**
++** ARGUMENTS:
++**
++** Address Address to be verified.
++** Name Name of a register.
++*/
++
++#define gcmISINREGRANGE(Address, Name) \
++( \
++ ((Address & (~0U << Name ## _LSB)) == (Name ## _Address >> 2)) \
++)
++
++/******************************************************************************\
++******************************** Ceiling Macro ********************************
++\******************************************************************************/
++#define gcmCEIL(x) ((x - (gctUINT32)x) == 0 ? (gctUINT32)x : (gctUINT32)x + 1)
++
++/******************************************************************************\
++******************************** Min/Max Macros ********************************
++\******************************************************************************/
++
++#define gcmMIN(x, y) (((x) <= (y)) ? (x) : (y))
++#define gcmMAX(x, y) (((x) >= (y)) ? (x) : (y))
++#define gcmCLAMP(x, min, max) (((x) < (min)) ? (min) : \
++ ((x) > (max)) ? (max) : (x))
++#define gcmABS(x) (((x) < 0) ? -(x) : (x))
++#define gcmNEG(x) (((x) < 0) ? (x) : -(x))
++
++/******************************************************************************\
++******************************** Bit Macro ********************************
++\******************************************************************************/
++#define gcmBITSET(x, y) ((x) & (y))
++/*******************************************************************************
++**
++** gcmPTR2INT
++**
++** Convert a pointer to an integer value.
++**
++** ARGUMENTS:
++**
++** p Pointer value.
++*/
++#define gcmPTR2INT(p) \
++( \
++ (gctUINTPTR_T) (p) \
++)
++
++#define gcmPTR2INT32(p) \
++( \
++ (gctUINT32)(gctUINTPTR_T) (p) \
++)
++
++/*******************************************************************************
++**
++** gcmINT2PTR
++**
++** Convert an integer value into a pointer.
++**
++** ARGUMENTS:
++**
++** v Integer value.
++*/
++
++#define gcmINT2PTR(i) \
++( \
++ (gctPOINTER) (gctUINTPTR_T)(i) \
++)
++
++/*******************************************************************************
++**
++** gcmOFFSETOF
++**
++** Compute the byte offset of a field inside a structure.
++**
++** ARGUMENTS:
++**
++** s Structure name.
++** field Field name.
++*/
++#define gcmOFFSETOF(s, field) \
++( \
++ gcmPTR2INT32(& (((struct s *) 0)->field)) \
++)
++
++/*******************************************************************************
++**
++** gcmSWAB32
++**
++** Return a value with all bytes in the 32 bit argument swapped.
++*/
++#define gcmSWAB32(x) ((gctUINT32)( \
++ (((gctUINT32)(x) & (gctUINT32)0x000000FFUL) << 24) | \
++ (((gctUINT32)(x) & (gctUINT32)0x0000FF00UL) << 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0x00FF0000UL) >> 8) | \
++ (((gctUINT32)(x) & (gctUINT32)0xFF000000UL) >> 24)))
++
++/*******************************************************************************
++***** Database ****************************************************************/
++
++typedef struct _gcsDATABASE_COUNTERS
++{
++ /* Number of currently allocated bytes. */
++ gctUINT64 bytes;
++
++ /* Maximum number of bytes allocated (memory footprint). */
++ gctUINT64 maxBytes;
++
++ /* Total number of bytes allocated. */
++ gctUINT64 totalBytes;
++}
++gcsDATABASE_COUNTERS;
++
++typedef struct _gcuDATABASE_INFO
++{
++ /* Counters. */
++ gcsDATABASE_COUNTERS counters;
++
++ /* Time value. */
++ gctUINT64 time;
++}
++gcuDATABASE_INFO;
++
++/*******************************************************************************
++***** Frame database **********************************************************/
++
++/* gcsHAL_FRAME_INFO */
++typedef struct _gcsHAL_FRAME_INFO
++{
++ /* Current timer tick. */
++ OUT gctUINT64 ticks;
++
++ /* Bandwidth counters. */
++ OUT gctUINT readBytes8[8];
++ OUT gctUINT writeBytes8[8];
++
++ /* Counters. */
++ OUT gctUINT cycles[8];
++ OUT gctUINT idleCycles[8];
++ OUT gctUINT mcCycles[8];
++ OUT gctUINT readRequests[8];
++ OUT gctUINT writeRequests[8];
++
++ /* 3D counters. */
++ OUT gctUINT vertexCount;
++ OUT gctUINT primitiveCount;
++ OUT gctUINT rejectedPrimitives;
++ OUT gctUINT culledPrimitives;
++ OUT gctUINT clippedPrimitives;
++ OUT gctUINT outPrimitives;
++ OUT gctUINT inPrimitives;
++ OUT gctUINT culledQuadCount;
++ OUT gctUINT totalQuadCount;
++ OUT gctUINT quadCount;
++ OUT gctUINT totalPixelCount;
++
++ /* PE counters. */
++ OUT gctUINT colorKilled[8];
++ OUT gctUINT colorDrawn[8];
++ OUT gctUINT depthKilled[8];
++ OUT gctUINT depthDrawn[8];
++
++ /* Shader counters. */
++ OUT gctUINT shaderCycles;
++ OUT gctUINT vsInstructionCount;
++ OUT gctUINT vsTextureCount;
++ OUT gctUINT psInstructionCount;
++ OUT gctUINT psTextureCount;
++
++ /* Texture counters. */
++ OUT gctUINT bilinearRequests;
++ OUT gctUINT trilinearRequests;
++ OUT gctUINT txBytes8;
++ OUT gctUINT txHitCount;
++ OUT gctUINT txMissCount;
++}
++gcsHAL_FRAME_INFO;
++
++#if gcdLINK_QUEUE_SIZE
++typedef struct _gckLINKDATA * gckLINKDATA;
++struct _gckLINKDATA
++{
++ gctUINT32 start;
++ gctUINT32 end;
++ gctUINT32 pid;
++};
++
++typedef struct _gckLINKQUEUE * gckLINKQUEUE;
++struct _gckLINKQUEUE
++{
++ struct _gckLINKDATA data[gcdLINK_QUEUE_SIZE];
++ gctUINT32 rear;
++ gctUINT32 front;
++ gctUINT32 count;
++};
++#endif
++
++#define gcdENTRY_QUEUE_SIZE 256
++typedef struct _gckENTRYDATA * gckENTRYDATA;
++struct _gckENTRYDATA
++{
++ gctUINT32 physical;
++ gctUINT32 bytes;
++};
++
++typedef struct _gckENTRYQUEUE * gckENTRYQUEUE;
++struct _gckENTRYQUEUE
++{
++ struct _gckENTRYDATA data[gcdENTRY_QUEUE_SIZE];
++ gctUINT32 rear;
++ gctUINT32 front;
++ gctUINT32 count;
++};
++
++typedef enum _gceTRACEMODE
++{
++ gcvTRACEMODE_NONE = 0,
++ gcvTRACEMODE_FULL = 1,
++ gcvTRACEMODE_LOGGER = 2,
++ gcvTRACEMODE_PRE = 3,
++ gcvTRACEMODE_POST = 4,
++ gcvTRACEMODE_SYSTRACE = 5,
++
++} gceTRACEMODE;
++
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_types_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,39 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_version_h_
++#define __gc_hal_version_h_
++
++#define gcvVERSION_MAJOR 5
++
++#define gcvVERSION_MINOR 0
++
++#define gcvVERSION_PATCH 11
++
++#define gcvVERSION_BUILD 25762
++
++#define gcvVERSION_STRING "5.0.11.p4.25762"
++
++#define gcvVERSION_DATE __DATE__
++
++#define gcvVERSION_TIME __TIME__
++
++#endif /* __gc_hal_version_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_vg.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,896 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_vg_h_
++#define __gc_hal_vg_h_
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++
++#include "gc_hal_rename.h"
++#include "gc_hal_types.h"
++#include "gc_hal_enum.h"
++#include "gc_hal_base.h"
++
++#if gcdENABLE_VG
++
++/* Thread routine type. */
++#if defined(LINUX)
++ typedef gctINT gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE
++#elif defined(WIN32)
++ typedef gctUINT gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE __stdcall
++#elif defined(__QNXNTO__)
++ typedef void * gctTHREADFUNCRESULT;
++ typedef gctPOINTER gctTHREADFUNCPARAMETER;
++# define gctTHREADFUNCTYPE
++#endif
++
++typedef gctTHREADFUNCRESULT (gctTHREADFUNCTYPE * gctTHREADFUNC) (
++ gctTHREADFUNCPARAMETER ThreadParameter
++ );
++
++
++#if defined(gcvDEBUG)
++# undef gcvDEBUG
++#endif
++
++#define gcdFORCE_DEBUG 0
++#define gcdFORCE_MESSAGES 0
++
++
++#if DBG || defined(DEBUG) || defined(_DEBUG) || gcdFORCE_DEBUG
++# define gcvDEBUG 1
++#else
++# define gcvDEBUG 0
++#endif
++
++#define _gcmERROR_RETURN(prefix, func) \
++ status = func; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ prefix##PRINT_VERSION(); \
++ prefix##TRACE(gcvLEVEL_ERROR, \
++ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \
++ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \
++ return status; \
++ } \
++ do { } while (gcvFALSE)
++
++#define gcmERROR_RETURN(func) _gcmERROR_RETURN(gcm, func)
++
++#define gcmLOG_LOCATION()
++
++#define gcmkIS_ERROR(status) (status < 0)
++
++#define gcmALIGNDOWN(n, align) \
++( \
++ (n) & ~((align) - 1) \
++)
++
++#define gcmIS_VALID_INDEX(Index, Array) \
++ (((gctUINT) (Index)) < gcmCOUNTOF(Array))
++
++
++#define gcmIS_NAN(x) \
++( \
++ ((* (gctUINT32_PTR) &(x)) & 0x7FFFFFFF) == 0x7FFFFFFF \
++)
++
++#define gcmLERP(v1, v2, w) \
++ ((v1) * (w) + (v2) * (1.0f - (w)))
++
++#define gcmINTERSECT(Start1, Start2, Length) \
++ (gcmABS((Start1) - (Start2)) < (Length))
++
++/*******************************************************************************
++**
++** gcmERR_GOTO
++**
++** Prints a message and terminates the current loop on error.
++**
++** ASSUMPTIONS:
++**
++** 'status' variable of gceSTATUS type must be defined.
++**
++** ARGUMENTS:
++**
++** Function
++** Function to evaluate.
++*/
++
++#define gcmERR_GOTO(Function) \
++ status = Function; \
++ if (gcmIS_ERROR(status)) \
++ { \
++ gcmTRACE( \
++ gcvLEVEL_ERROR, \
++ "gcmERR_GOTO: status=%d @ line=%d in function %s.\n", \
++ status, __LINE__, __FUNCTION__ \
++ ); \
++ goto ErrorHandler; \
++ }
++
++#if gcvDEBUG || gcdFORCE_MESSAGES
++# define gcmVERIFY_BOOLEAN(Expression) \
++ gcmASSERT( \
++ ( (Expression) == gcvFALSE ) || \
++ ( (Expression) == gcvTRUE ) \
++ )
++#else
++# define gcmVERIFY_BOOLEAN(Expression)
++#endif
++
++/*******************************************************************************
++**
++** gcmVERIFYFIELDFIT
++**
++** Verify whether the value fits in the field.
++**
++** ARGUMENTS:
++**
++** data Data value.
++** reg Name of register.
++** field Name of field within register.
++** value Value for field.
++*/
++#define gcmVERIFYFIELDFIT(reg, field, value) \
++ gcmASSERT( \
++ (value) <= gcmFIELDMAX(reg, field) \
++ )
++/*******************************************************************************
++**
++** gcmFIELDMAX
++**
++** Get field maximum value.
++**
++** ARGUMENTS:
++**
++** reg Name of register.
++** field Name of field within register.
++*/
++#define gcmFIELDMAX(reg, field) \
++( \
++ (gctUINT32) \
++ ( \
++ (__gcmGETSIZE(reg##_##field) == 32) \
++ ? ~0 \
++ : (~(~0 << __gcmGETSIZE(reg##_##field))) \
++ ) \
++)
++
++
++/* ANSI C does not have the 'f' functions, define replacements here. */
++#define gcmSINF(x) ((gctFLOAT) sin(x))
++#define gcmCOSF(x) ((gctFLOAT) cos(x))
++#define gcmASINF(x) ((gctFLOAT) asin(x))
++#define gcmACOSF(x) ((gctFLOAT) acos(x))
++#define gcmSQRTF(x) ((gctFLOAT) sqrt(x))
++#define gcmFABSF(x) ((gctFLOAT) fabs(x))
++#define gcmFMODF(x, y) ((gctFLOAT) fmod((x), (y)))
++#define gcmCEILF(x) ((gctFLOAT) ceil(x))
++#define gcmFLOORF(x) ((gctFLOAT) floor(x))
++
++
++
++/* Fixed point constants. */
++#define gcvZERO_X ((gctFIXED_POINT) 0x00000000)
++#define gcvHALF_X ((gctFIXED_POINT) 0x00008000)
++#define gcvONE_X ((gctFIXED_POINT) 0x00010000)
++#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000)
++#define gcvTWO_X ((gctFIXED_POINT) 0x00020000)
++
++/* Integer constants. */
++#define gcvMAX_POS_INT ((gctINT) 0x7FFFFFFF)
++#define gcvMAX_NEG_INT ((gctINT) 0x80000000)
++
++/* Float constants. */
++#define gcvMAX_POS_FLOAT ((gctFLOAT) 3.4028235e+038)
++#define gcvMAX_NEG_FLOAT ((gctFLOAT) -3.4028235e+038)
++
++/******************************************************************************\
++***************************** Miscellaneous Macro ******************************
++\******************************************************************************/
++
++#define gcmKB2BYTES(Kilobyte) \
++( \
++ (Kilobyte) << 10 \
++)
++
++#define gcmMB2BYTES(Megabyte) \
++( \
++ (Megabyte) << 20 \
++)
++
++#define gcmMAT(Matrix, Row, Column) \
++( \
++ (Matrix) [(Row) * 3 + (Column)] \
++)
++
++#define gcmMAKE2CHAR(Char1, Char2) \
++( \
++ ((gctUINT16) (gctUINT8) (Char1) << 0) | \
++ ((gctUINT16) (gctUINT8) (Char2) << 8) \
++)
++
++#define gcmMAKE4CHAR(Char1, Char2, Char3, Char4) \
++( \
++ ((gctUINT32)(gctUINT8) (Char1) << 0) | \
++ ((gctUINT32)(gctUINT8) (Char2) << 8) | \
++ ((gctUINT32)(gctUINT8) (Char3) << 16) | \
++ ((gctUINT32)(gctUINT8) (Char4) << 24) \
++)
++
++/* some platforms need to fix the physical address for HW to access*/
++#define gcmFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++#define gcmkFIXADDRESS(address) \
++(\
++ (address)\
++)
++
++/******************************************************************************\
++****************************** Kernel Debug Macro ******************************
++\******************************************************************************/
++
++/* Set signal to signaled state for specified process. */
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/* Return the kernel logical pointer for the given physical one. */
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ );
++
++/*----------------------------------------------------------------------------*/
++/*----------------------------- Semaphore Object -----------------------------*/
++
++/* Increment the value of a semaphore. */
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++/* Decrement the value of a semaphore (waiting might occur). */
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ );
++
++
++/*----------------------------------------------------------------------------*/
++/*------------------------------- Thread Object ------------------------------*/
++
++/* Start a thread. */
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ );
++
++/* Stop a thread. */
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++/* Verify whether the thread is still running. */
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ );
++
++
++/* Construct a new gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Construct(
++ IN gckOS Os,
++ IN gctPOINTER Context,
++ IN gckKERNEL inKernel,
++ OUT gckVGKERNEL * Kernel
++ );
++
++/* Destroy an gckVGKERNEL object. */
++gceSTATUS
++gckVGKERNEL_Destroy(
++ IN gckVGKERNEL Kernel
++ );
++
++/* Allocate linear video memory. */
++gceSTATUS
++gckVGKERNEL_AllocateLinearMemory(
++ IN gckKERNEL Kernel,
++ IN OUT gcePOOL * Pool,
++ IN gctSIZE_T Bytes,
++ IN gctUINT32 Alignment,
++ IN gceSURF_TYPE Type,
++ OUT gcuVIDMEM_NODE_PTR * Node
++ );
++
++/* Unmap memory. */
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ );
++
++/* Dispatch a user-level command. */
++gceSTATUS
++gckVGKERNEL_Dispatch(
++ IN gckKERNEL Kernel,
++ IN gctBOOL FromUser,
++ IN OUT struct _gcsHAL_INTERFACE * Interface
++ );
++
++/* Query command buffer requirements. */
++gceSTATUS
++gckKERNEL_QueryCommandBuffer(
++ IN gckKERNEL Kernel,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++/******************************************************************************\
++******************************* gckVGHARDWARE Object ******************************
++\******************************************************************************/
++
++/* Construct a new gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Construct(
++ IN gckOS Os,
++ OUT gckVGHARDWARE * Hardware
++ );
++
++/* Destroy an gckVGHARDWARE object. */
++gceSTATUS
++gckVGHARDWARE_Destroy(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Query system memory requirements. */
++gceSTATUS
++gckVGHARDWARE_QuerySystemMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * SystemSize,
++ OUT gctUINT32 * SystemBaseAddress
++ );
++
++/* Build virtual address. */
++gceSTATUS
++gckVGHARDWARE_BuildVirtualAddress(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Index,
++ IN gctUINT32 Offset,
++ OUT gctUINT32 * Address
++ );
++
++/* Kickstart the command processor. */
++gceSTATUS
++gckVGHARDWARE_Execute(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ IN gctUINT32 Count
++ );
++
++/* Query the available memory. */
++gceSTATUS
++gckVGHARDWARE_QueryMemory(
++ IN gckVGHARDWARE Hardware,
++ OUT gctSIZE_T * InternalSize,
++ OUT gctUINT32 * InternalBaseAddress,
++ OUT gctUINT32 * InternalAlignment,
++ OUT gctSIZE_T * ExternalSize,
++ OUT gctUINT32 * ExternalBaseAddress,
++ OUT gctUINT32 * ExternalAlignment,
++ OUT gctUINT32 * HorizontalTileSize,
++ OUT gctUINT32 * VerticalTileSize
++ );
++
++/* Query the identity of the hardware. */
++gceSTATUS
++gckVGHARDWARE_QueryChipIdentity(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPMODEL* ChipModel,
++ OUT gctUINT32* ChipRevision,
++ OUT gctUINT32* ChipFeatures,
++ OUT gctUINT32* ChipMinorFeatures,
++ OUT gctUINT32* ChipMinorFeatures1
++ );
++
++/* Convert an API format. */
++gceSTATUS
++gckVGHARDWARE_ConvertFormat(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_FORMAT Format,
++ OUT gctUINT32 * BitsPerPixel,
++ OUT gctUINT32 * BytesPerTile
++ );
++
++/* Split a harwdare specific address into API stuff. */
++gceSTATUS
++gckVGHARDWARE_SplitMemory(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Address,
++ OUT gcePOOL * Pool,
++ OUT gctUINT32 * Offset
++ );
++
++/* Align size to tile boundary. */
++gceSTATUS
++gckVGHARDWARE_AlignToTile(
++ IN gckVGHARDWARE Hardware,
++ IN gceSURF_TYPE Type,
++ IN OUT gctUINT32_PTR Width,
++ IN OUT gctUINT32_PTR Height
++ );
++
++/* Convert logical address to hardware specific address. */
++gceSTATUS
++gckVGHARDWARE_ConvertLogical(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical,
++ IN gctBOOL InUserSpace,
++ OUT gctUINT32 * Address
++ );
++
++/* Program MMU. */
++gceSTATUS
++gckVGHARDWARE_SetMMU(
++ IN gckVGHARDWARE Hardware,
++ IN gctPOINTER Logical
++ );
++
++/* Flush the MMU. */
++gceSTATUS
++gckVGHARDWARE_FlushMMU(
++ IN gckVGHARDWARE Hardware
++ );
++
++/* Get idle register. */
++gceSTATUS
++gckVGHARDWARE_GetIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32 * Data
++ );
++
++/* Flush the caches. */
++gceSTATUS
++gckVGHARDWARE_Flush(
++ IN gckVGHARDWARE Hardware,
++ IN gceKERNEL_FLUSH Flush,
++ IN gctPOINTER Logical,
++ IN OUT gctSIZE_T * Bytes
++ );
++
++/* Enable/disable fast clear. */
++gceSTATUS
++gckVGHARDWARE_SetFastClear(
++ IN gckVGHARDWARE Hardware,
++ IN gctINT Enable
++ );
++
++gceSTATUS
++gckVGHARDWARE_ReadInterrupt(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32_PTR IDs
++ );
++
++/* Power management. */
++gceSTATUS
++gckVGHARDWARE_SetPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ IN gceCHIPPOWERSTATE State
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerManagementState(
++ IN gckVGHARDWARE Hardware,
++ OUT gceCHIPPOWERSTATE* State
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerManagement(
++ IN gckVGHARDWARE Hardware,
++ IN gctBOOL PowerManagement
++ );
++
++gceSTATUS
++gckVGHARDWARE_SetPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ IN gctUINT32 Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryPowerOffTimeout(
++ IN gckVGHARDWARE Hardware,
++ OUT gctUINT32* Timeout
++ );
++
++gceSTATUS
++gckVGHARDWARE_QueryIdle(
++ IN gckVGHARDWARE Hardware,
++ OUT gctBOOL_PTR IsIdle
++ );
++/******************************************************************************\
++*************************** Command Buffer Structures **************************
++\******************************************************************************/
++
++/* Vacant command buffer marker. */
++#define gcvVACANT_BUFFER ((gcsCOMPLETION_SIGNAL_PTR) ((gctSIZE_T)1))
++
++/* Command buffer header. */
++typedef struct _gcsCMDBUFFER * gcsCMDBUFFER_PTR;
++typedef struct _gcsCMDBUFFER
++{
++ /* Pointer to the completion signal. */
++ gcsCOMPLETION_SIGNAL_PTR completion;
++
++ /* The user sets this to the node of the container buffer whitin which
++ this particular command buffer resides. The kernel sets this to the
++ node of the internally allocated buffer. */
++ gcuVIDMEM_NODE_PTR node;
++
++ /* Command buffer hardware address. */
++ gctUINT32 address;
++
++ /* The offset of the buffer from the beginning of the header. */
++ gctUINT32 bufferOffset;
++
++ /* Size of the area allocated for the data portion of this particular
++ command buffer (headers and tail reserves are excluded). */
++ gctUINT32 size;
++
++ /* Offset into the buffer [0..size]; reflects exactly how much data has
++ been put into the command buffer. */
++ gctUINT offset;
++
++ /* The number of command units in the buffer for the hardware to
++ execute. */
++ gctUINT32 dataCount;
++
++ /* MANAGED BY : user HAL (gcoBUFFER object).
++ USED BY : user HAL (gcoBUFFER object).
++ Points to the immediate next allocated command buffer. */
++ gcsCMDBUFFER_PTR nextAllocated;
++
++ /* MANAGED BY : user layers (HAL and drivers).
++ USED BY : kernel HAL (gcoBUFFER object).
++ Points to the next subbuffer if any. A family of subbuffers are chained
++ together and are meant to be executed inseparably as a unit. Meaning
++ that context switching cannot occur while a chain of subbuffers is being
++ executed. */
++ gcsCMDBUFFER_PTR nextSubBuffer;
++}
++gcsCMDBUFFER;
++
++/* Command queue element. */
++typedef struct _gcsVGCMDQUEUE
++{
++ /* Pointer to the command buffer header. */
++ gcsCMDBUFFER_PTR commandBuffer;
++
++ /* Dynamic vs. static command buffer state. */
++ gctBOOL dynamic;
++}
++gcsVGCMDQUEUE;
++
++/* Context map entry. */
++typedef struct _gcsVGCONTEXT_MAP
++{
++ /* State index. */
++ gctUINT32 index;
++
++ /* New state value. */
++ gctUINT32 data;
++
++ /* Points to the next entry in the mod list. */
++ gcsVGCONTEXT_MAP_PTR next;
++}
++gcsVGCONTEXT_MAP;
++
++/* gcsVGCONTEXT structure that holds the current context. */
++typedef struct _gcsVGCONTEXT
++{
++ /* Context ID. */
++ gctUINT64 id;
++
++ /* State caching ebable flag. */
++ gctBOOL stateCachingEnabled;
++
++ /* Current pipe. */
++ gctUINT32 currentPipe;
++
++ /* State map/mod buffer. */
++ gctUINT32 mapFirst;
++ gctUINT32 mapLast;
++ gcsVGCONTEXT_MAP_PTR mapContainer;
++ gcsVGCONTEXT_MAP_PTR mapPrev;
++ gcsVGCONTEXT_MAP_PTR mapCurr;
++ gcsVGCONTEXT_MAP_PTR firstPrevMap;
++ gcsVGCONTEXT_MAP_PTR firstCurrMap;
++
++ /* Main context buffer. */
++ gcsCMDBUFFER_PTR header;
++ gctUINT32_PTR buffer;
++
++ /* Completion signal. */
++ gctHANDLE process;
++ gctSIGNAL signal;
++
++#if defined(__QNXNTO__)
++ gctINT32 coid;
++ gctINT32 rcvid;
++#endif
++}
++gcsVGCONTEXT;
++
++/* User space task header. */
++typedef struct _gcsTASK * gcsTASK_PTR;
++typedef struct _gcsTASK
++{
++ /* Pointer to the next task for the same interrupt in user space. */
++ gcsTASK_PTR next;
++
++ /* Size of the task data that immediately follows the structure. */
++ gctUINT size;
++
++ /* Task data starts here. */
++ /* ... */
++}
++gcsTASK;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_ENTRY * gcsTASK_MASTER_ENTRY_PTR;
++typedef struct _gcsTASK_MASTER_ENTRY
++{
++ /* Pointers to the head and to the tail of the task chain. */
++ gcsTASK_PTR head;
++ gcsTASK_PTR tail;
++}
++gcsTASK_MASTER_ENTRY;
++
++/* User space task master table entry. */
++typedef struct _gcsTASK_MASTER_TABLE
++{
++ /* Table with one entry per block. */
++ gcsTASK_MASTER_ENTRY table[gcvBLOCK_COUNT];
++
++ /* The total number of tasks sckeduled. */
++ gctUINT count;
++
++ /* The total size of event data in bytes. */
++ gctUINT size;
++
++#if defined(__QNXNTO__)
++ gctINT32 coid;
++ gctINT32 rcvid;
++#endif
++}
++gcsTASK_MASTER_TABLE;
++
++/******************************************************************************\
++***************************** gckVGINTERRUPT Object ******************************
++\******************************************************************************/
++
++typedef struct _gckVGINTERRUPT * gckVGINTERRUPT;
++
++typedef gceSTATUS (* gctINTERRUPT_HANDLER)(
++ IN gckVGKERNEL Kernel
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Construct(
++ IN gckVGKERNEL Kernel,
++ OUT gckVGINTERRUPT * Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Destroy(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Enable(
++ IN gckVGINTERRUPT Interrupt,
++ IN OUT gctINT32_PTR Id,
++ IN gctINTERRUPT_HANDLER Handler
++ );
++
++gceSTATUS
++gckVGINTERRUPT_Disable(
++ IN gckVGINTERRUPT Interrupt,
++ IN gctINT32 Id
++ );
++
++#ifndef __QNXNTO__
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++#else
++
++gceSTATUS
++gckVGINTERRUPT_Enque(
++ IN gckVGINTERRUPT Interrupt,
++ OUT gckOS *Os,
++ OUT gctSEMAPHORE *Semaphore
++ );
++
++#endif
++
++gceSTATUS
++gckVGINTERRUPT_DumpState(
++ IN gckVGINTERRUPT Interrupt
++ );
++
++
++/******************************************************************************\
++******************************* gckVGCOMMAND Object *******************************
++\******************************************************************************/
++
++typedef struct _gckVGCOMMAND * gckVGCOMMAND;
++
++/* Construct a new gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT TaskGranularity,
++ IN gctUINT QueueSize,
++ OUT gckVGCOMMAND * Command
++ );
++
++/* Destroy an gckVGCOMMAND object. */
++gceSTATUS
++gckVGCOMMAND_Destroy(
++ IN gckVGCOMMAND Command
++ );
++
++/* Query command buffer attributes. */
++gceSTATUS
++gckVGCOMMAND_QueryCommandBuffer(
++ IN gckVGCOMMAND Command,
++ OUT gcsCOMMAND_BUFFER_INFO_PTR Information
++ );
++
++/* Allocate a command queue. */
++gceSTATUS
++gckVGCOMMAND_Allocate(
++ IN gckVGCOMMAND Command,
++ IN gctSIZE_T Size,
++ OUT gcsCMDBUFFER_PTR * CommandBuffer,
++ OUT gctPOINTER * Data
++ );
++
++/* Release memory held by the command queue. */
++gceSTATUS
++gckVGCOMMAND_Free(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Schedule the command queue for execution. */
++gceSTATUS
++gckVGCOMMAND_Execute(
++ IN gckVGCOMMAND Command,
++ IN gcsCMDBUFFER_PTR CommandBuffer
++ );
++
++/* Commit a buffer to the command queue. */
++gceSTATUS
++gckVGCOMMAND_Commit(
++ IN gckVGCOMMAND Command,
++ IN gcsVGCONTEXT_PTR Context,
++ IN gcsVGCMDQUEUE_PTR Queue,
++ IN gctUINT EntryCount,
++ IN gcsTASK_MASTER_TABLE_PTR TaskTable
++ );
++
++/******************************************************************************\
++********************************* gckVGMMU Object ********************************
++\******************************************************************************/
++
++typedef struct _gckVGMMU * gckVGMMU;
++
++/* Construct a new gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Construct(
++ IN gckVGKERNEL Kernel,
++ IN gctUINT32 MmuSize,
++ OUT gckVGMMU * Mmu
++ );
++
++/* Destroy an gckVGMMU object. */
++gceSTATUS
++gckVGMMU_Destroy(
++ IN gckVGMMU Mmu
++ );
++
++/* Allocate pages inside the MMU. */
++gceSTATUS
++gckVGMMU_AllocatePages(
++ IN gckVGMMU Mmu,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageTable,
++ OUT gctUINT32 * Address
++ );
++
++/* Remove a page table from the MMU. */
++gceSTATUS
++gckVGMMU_FreePages(
++ IN gckVGMMU Mmu,
++ IN gctPOINTER PageTable,
++ IN gctSIZE_T PageCount
++ );
++
++/* Set the MMU page with info. */
++gceSTATUS
++gckVGMMU_SetPage(
++ IN gckVGMMU Mmu,
++ IN gctUINT32 PageAddress,
++ IN gctUINT32 *PageEntry
++ );
++
++/* Flush MMU */
++gceSTATUS
++gckVGMMU_Flush(
++ IN gckVGMMU Mmu
++ );
++
++#endif /* gcdENABLE_VG */
++
++#ifdef __cplusplus
++} /* extern "C" */
++#endif
++
++#endif /* __gc_hal_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/default/gc_hal_kernel_allocator_array.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,34 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++extern gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++
++gcsALLOCATOR_DESC allocatorArray[] =
++{
++ /* Default allocator. */
++ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit),
++};
++
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_array.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,45 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++extern gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++
++#if LINUX_CMA_FSL
++gceSTATUS
++_CMAFSLAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ );
++#endif
++
++gcsALLOCATOR_DESC allocatorArray[] =
++{
++#if LINUX_CMA_FSL
++ gcmkDEFINE_ALLOCATOR_DESC("cmafsl", _CMAFSLAlloctorInit),
++#endif
++ /* Default allocator. */
++ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit),
++};
++
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/allocator/freescale/gc_hal_kernel_allocator_cma.c 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,412 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_allocator.h"
++
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsCMA_PRIV * gcsCMA_PRIV_PTR;
++typedef struct _gcsCMA_PRIV {
++ gctUINT32 cmasize;
++}
++gcsCMA_PRIV;
++
++struct mdl_cma_priv {
++ gctPOINTER kvaddr;
++ dma_addr_t physical;
++};
++
++int gc_cma_usage_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckALLOCATOR Allocator = node->device;
++ gcsCMA_PRIV_PTR priv = Allocator->privateData;
++
++ seq_printf(m, "cma: %u bytes\n", priv->cmasize);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"cmausage", gc_cma_usage_show},
++};
++
++static void
++_DefaultAllocatorDebugfsInit(
++ IN gckALLOCATOR Allocator,
++ IN gckDEBUGFS_DIR Root
++ )
++{
++ gcmkVERIFY_OK(
++ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "cma"));
++
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList),
++ Allocator
++ ));
++}
++
++static void
++_DefaultAllocatorDebugfsCleanup(
++ IN gckALLOCATOR Allocator
++ )
++{
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList)
++ ));
++
++ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir);
++}
++
++static gceSTATUS
++_CMAFSLAlloc(
++ IN gckALLOCATOR Allocator,
++ INOUT PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flags
++ )
++{
++ gceSTATUS status;
++ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData;
++
++ struct mdl_cma_priv *mdl_priv=gcvNULL;
++ gckOS os = Allocator->os;
++
++ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages);
++
++ gcmkONERROR(gckOS_Allocate(os, sizeof(struct mdl_cma_priv), (gctPOINTER *)&mdl_priv));
++ mdl_priv->kvaddr = gcvNULL;
++
++ mdl_priv->kvaddr = dma_alloc_writecombine(gcvNULL,
++ NumPages * PAGE_SIZE,
++ &mdl_priv->physical,
++ GFP_KERNEL | gcdNOWARN);
++
++ if (mdl_priv->kvaddr == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ Mdl->priv = mdl_priv;
++ priv->cmasize += NumPages * PAGE_SIZE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if(mdl_priv)
++ gckOS_Free(os, mdl_priv);
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_CMAFSLFree(
++ IN gckALLOCATOR Allocator,
++ IN OUT PLINUX_MDL Mdl
++ )
++{
++ gckOS os = Allocator->os;
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData;
++ dma_free_writecombine(gcvNULL,
++ Mdl->numPages * PAGE_SIZE,
++ mdl_priv->kvaddr,
++ mdl_priv->physical);
++ gckOS_Free(os, mdl_priv);
++ priv->cmasize -= Mdl->numPages * PAGE_SIZE;
++}
++
++gctINT
++_CMAFSLMapUser(
++ gckALLOCATOR Allocator,
++ PLINUX_MDL Mdl,
++ PLINUX_MDL_MAP MdlMap,
++ gctBOOL Cacheable
++ )
++{
++
++ PLINUX_MDL mdl = Mdl;
++ PLINUX_MDL_MAP mdlMap = MdlMap;
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++
++ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (dma_mmap_writecombine(gcvNULL,
++ mdlMap->vma,
++ mdl_priv->kvaddr,
++ mdl_priv->physical,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): dma_mmap_attrs error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ gckOS_Print("incorrect mdl:conti%d\n",mdl->contiguous);
++ }
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_CMAUnmapUser(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ )
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,4,0)
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++#else
++ down_write(&current->mm->mmap_sem);
++ if (do_munmap(current->mm, (unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++ up_write(&current->mm->mmap_sem);
++#endif
++}
++
++gceSTATUS
++_CMAMapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ )
++{
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ *Logical =mdl_priv->kvaddr;
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_CMAUnmapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++extern gceSTATUS
++_DefaultLogicalToPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ );
++
++extern gceSTATUS
++_DefaultCache(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++gceSTATUS
++_CMAPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv;
++ gcmkASSERT(!Offset);
++ *Physical = mdl_priv->physical;
++
++ return gcvSTATUS_OK;
++}
++
++
++extern void
++_DefaultAllocatorDestructor(
++ IN void* PrivateData
++ );
++
++/* Default allocator operations. */
++gcsALLOCATOR_OPERATIONS CMAFSLAllocatorOperations = {
++ .Alloc = _CMAFSLAlloc,
++ .Free = _CMAFSLFree,
++ .MapUser = _CMAFSLMapUser,
++ .UnmapUser = _CMAUnmapUser,
++ .MapKernel = _CMAMapKernel,
++ .UnmapKernel = _CMAUnmapKernel,
++ .LogicalToPhysical = _DefaultLogicalToPhysical,
++ .Cache = _DefaultCache,
++ .Physical = _CMAPhysical,
++};
++
++/* Default allocator entry. */
++gceSTATUS
++_CMAFSLAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++ gcsCMA_PRIV_PTR priv = gcvNULL;
++
++ gcmkONERROR(
++ gckALLOCATOR_Construct(Os, &CMAFSLAllocatorOperations, &allocator));
++
++ priv = kzalloc(gcmSIZEOF(gcsCMA_PRIV), GFP_KERNEL | gcdNOWARN);
++
++ if (!priv)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Register private data. */
++ allocator->privateData = priv;
++ allocator->privateDataDestructor = _DefaultAllocatorDestructor;
++
++ allocator->debugfsInit = _DefaultAllocatorDebugfsInit;
++ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup;
++
++ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS;
++
++ *Allocator = allocator;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.c 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,938 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_allocator.h"
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++
++#include "gc_hal_kernel_allocator_array.h"
++#include "gc_hal_kernel_platform.h"
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsDEFAULT_PRIV * gcsDEFAULT_PRIV_PTR;
++typedef struct _gcsDEFAULT_PRIV {
++ gctUINT32 low;
++ gctUINT32 high;
++}
++gcsDEFAULT_PRIV;
++
++/******************************************************************************\
++************************** Default Allocator Debugfs ***************************
++\******************************************************************************/
++
++int gc_usage_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckALLOCATOR Allocator = node->device;
++ gcsDEFAULT_PRIV_PTR priv = Allocator->privateData;
++
++ seq_printf(m, "low: %u bytes\n", priv->low);
++ seq_printf(m, "high: %u bytes\n", priv->high);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"lowHighUsage", gc_usage_show},
++};
++
++static void
++_DefaultAllocatorDebugfsInit(
++ IN gckALLOCATOR Allocator,
++ IN gckDEBUGFS_DIR Root
++ )
++{
++ gcmkVERIFY_OK(
++ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "default"));
++
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList),
++ Allocator
++ ));
++}
++
++static void
++_DefaultAllocatorDebugfsCleanup(
++ IN gckALLOCATOR Allocator
++ )
++{
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(
++ &Allocator->debugfsDir,
++ InfoList,
++ gcmCOUNTOF(InfoList)
++ ));
++
++ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir);
++}
++
++
++static void
++_NonContiguousFree(
++ IN struct page ** Pages,
++ IN gctUINT32 NumPages
++ )
++{
++ gctINT i;
++
++ gcmkHEADER_ARG("Pages=0x%X, NumPages=%d", Pages, NumPages);
++
++ gcmkASSERT(Pages != gcvNULL);
++
++ for (i = 0; i < NumPages; i++)
++ {
++ __free_page(Pages[i]);
++ }
++
++ if (is_vmalloc_addr(Pages))
++ {
++ vfree(Pages);
++ }
++ else
++ {
++ kfree(Pages);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++static struct page **
++_NonContiguousAlloc(
++ IN gctUINT32 NumPages
++ )
++{
++ struct page ** pages;
++ struct page *p;
++ gctINT i, size;
++
++ gcmkHEADER_ARG("NumPages=%lu", NumPages);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)
++ if (NumPages > totalram_pages)
++#else
++ if (NumPages > num_physpages)
++#endif
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ size = NumPages * sizeof(struct page *);
++
++ pages = kmalloc(size, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ pages = vmalloc(size);
++
++ if (!pages)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ }
++
++ for (i = 0; i < NumPages; i++)
++ {
++ p = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN);
++
++ if (!p)
++ {
++ _NonContiguousFree(pages, i);
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ pages[i] = p;
++ }
++
++ gcmkFOOTER_ARG("pages=0x%X", pages);
++ return pages;
++}
++
++gctSTRING
++_CreateKernelVirtualMapping(
++ IN PLINUX_MDL Mdl
++ )
++{
++ gctSTRING addr = 0;
++ gctINT numPages = Mdl->numPages;
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ if (Mdl->contiguous)
++ {
++ addr = page_address(Mdl->u.contiguousPages);
++ }
++ else
++ {
++ addr = vmap(Mdl->u.nonContiguousPages,
++ numPages,
++ 0,
++ PAGE_KERNEL);
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++ }
++#else
++ struct page ** pages;
++ gctBOOL free = gcvFALSE;
++ gctINT i;
++
++ if (Mdl->contiguous)
++ {
++ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ return gcvNULL;
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ pages[i] = nth_page(Mdl->u.contiguousPages, i);
++ }
++
++ free = gcvTRUE;
++ }
++ else
++ {
++ pages = Mdl->u.nonContiguousPages;
++ }
++
++ /* ioremap() can't work on system memory since 2.6.38. */
++ addr = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL));
++
++ if (free)
++ {
++ kfree(pages);
++ }
++
++#endif
++
++ return addr;
++}
++
++void
++_DestoryKernelVirtualMapping(
++ IN gctSTRING Addr
++ )
++{
++#if !gcdNONPAGED_MEMORY_CACHEABLE
++ vunmap(Addr);
++#endif
++}
++
++void
++_UnmapUserLogical(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++)
++{
++ if (unlikely(current->mm == gcvNULL))
++ {
++ /* Do nothing if process is exiting. */
++ return;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (vm_munmap((unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): vm_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++#else
++ down_write(&current->mm->mmap_sem);
++ if (do_munmap(current->mm, (unsigned long)Logical, Size) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_munmap failed",
++ __FUNCTION__, __LINE__
++ );
++ }
++ up_write(&current->mm->mmap_sem);
++#endif
++}
++
++/***************************************************************************\
++************************ Default Allocator **********************************
++\***************************************************************************/
++#define C_MAX_PAGENUM (50*1024)
++static gceSTATUS
++_DefaultAlloc(
++ IN gckALLOCATOR Allocator,
++ INOUT PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flags
++ )
++{
++ gceSTATUS status;
++ gctUINT32 order;
++ gctSIZE_T bytes;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ gctPOINTER addr = gcvNULL;
++#endif
++ gctUINT32 numPages;
++ gctUINT i = 0;
++ gctBOOL contiguous = Flags & gcvALLOC_FLAG_CONTIGUOUS;
++ struct sysinfo temsysinfo;
++ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData;
++
++ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages);
++
++ numPages = NumPages;
++ bytes = NumPages * PAGE_SIZE;
++ order = get_order(bytes);
++
++ si_meminfo(&temsysinfo);
++
++ if (Flags & gcvALLOC_FLAG_MEMLIMIT)
++ {
++ if ( (temsysinfo.freeram < NumPages) || ((temsysinfo.freeram-NumPages) < C_MAX_PAGENUM) )
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ }
++
++ if (contiguous)
++ {
++ if (order >= MAX_ORDER)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ addr =
++ alloc_pages_exact(bytes, GFP_KERNEL | gcdNOWARN | __GFP_NORETRY);
++
++ Mdl->u.contiguousPages = addr
++ ? virt_to_page(addr)
++ : gcvNULL;
++
++ Mdl->exact = gcvTRUE;
++#else
++ Mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | gcdNOWARN | __GFP_NORETRY, order);
++#endif
++
++ if (Mdl->u.contiguousPages == gcvNULL)
++ {
++ Mdl->u.contiguousPages =
++ alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, order);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ Mdl->exact = gcvFALSE;
++#endif
++ }
++ }
++ else
++ {
++ Mdl->u.nonContiguousPages = _NonContiguousAlloc(numPages);
++ }
++
++ if (Mdl->u.contiguousPages == gcvNULL && Mdl->u.nonContiguousPages == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ struct page *page;
++
++ if (contiguous)
++ {
++ page = nth_page(Mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i);
++ }
++
++ SetPageReserved(page);
++
++ if (!PageHighMem(page) && page_to_phys(page))
++ {
++ gcmkVERIFY_OK(
++ gckOS_CacheFlush(Allocator->os, _GetProcessID(), gcvNULL,
++ page_to_phys(page),
++ page_address(page),
++ PAGE_SIZE));
++
++ priv->low += PAGE_SIZE;
++ }
++ else
++ {
++ flush_dcache_page(page);
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED && defined(CONFIG_OUTER_CACHE) && gcdENABLE_OUTER_CACHE_PATCH
++ if (page_to_phys(page))
++ {
++ _HandleOuterCache(
++ Allocator->os,
++ page_to_phys(page),
++ gcvNULL,
++ PAGE_SIZE,
++ gcvCACHE_FLUSH
++ );
++ }
++#endif
++
++ priv->high += PAGE_SIZE;
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static void
++_DefaultFree(
++ IN gckALLOCATOR Allocator,
++ IN OUT PLINUX_MDL Mdl
++ )
++{
++ gctINT i;
++ struct page * page;
++ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData;
++
++ for (i = 0; i < Mdl->numPages; i++)
++ {
++ if (Mdl->contiguous)
++ {
++ page = nth_page(Mdl->u.contiguousPages, i);
++ }
++ else
++ {
++ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i);
++ }
++
++ ClearPageReserved(page);
++
++ if (PageHighMem(page))
++ {
++ priv->high -= PAGE_SIZE;
++ }
++ else
++ {
++ priv->low -= PAGE_SIZE;
++ }
++ }
++
++ if (Mdl->contiguous)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ if (Mdl->exact == gcvTRUE)
++ {
++ free_pages_exact(page_address(Mdl->u.contiguousPages), Mdl->numPages * PAGE_SIZE);
++ }
++ else
++#endif
++ {
++ __free_pages(Mdl->u.contiguousPages, get_order(Mdl->numPages * PAGE_SIZE));
++ }
++ }
++ else
++ {
++ _NonContiguousFree(Mdl->u.nonContiguousPages, Mdl->numPages);
++ }
++}
++
++gctINT
++_DefaultMapUser(
++ gckALLOCATOR Allocator,
++ PLINUX_MDL Mdl,
++ PLINUX_MDL_MAP MdlMap,
++ gctBOOL Cacheable
++ )
++{
++
++ gctSTRING addr;
++ unsigned long start;
++ unsigned long pfn;
++ gctINT i;
++ gckOS os = Allocator->os;
++ gcsPLATFORM * platform = os->device->platform;
++
++ PLINUX_MDL mdl = Mdl;
++ PLINUX_MDL_MAP mdlMap = MdlMap;
++
++ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable);
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr,
++ (gctUINT32)(gctUINTPTR_T)mdl
++ );
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++
++ if (Cacheable == gcvFALSE)
++ {
++ /* Make this mapping non-cached. */
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ }
++
++ if (platform && platform->ops->adjustProt)
++ {
++ platform->ops->adjustProt(mdlMap->vma);
++ }
++
++ addr = mdl->addr;
++
++ /* Now map all the vmalloc pages to this user address. */
++ if (mdl->contiguous)
++ {
++ /* map kernel memory to user space.. */
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ page_to_pfn(mdl->u.contiguousPages),
++ mdlMap->vma->vm_end - mdlMap->vma->vm_start,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): unable to mmap ret",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++ else
++ {
++ start = mdlMap->vma->vm_start;
++
++ for (i = 0; i < mdl->numPages; i++)
++ {
++ pfn = _NonContiguousToPfn(mdl->u.nonContiguousPages, i);
++
++ if (remap_pfn_range(mdlMap->vma,
++ start,
++ pfn,
++ PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ start += PAGE_SIZE;
++ addr += PAGE_SIZE;
++ }
++ }
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++void
++_DefaultUnmapUser(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ )
++{
++ _UnmapUserLogical(Logical, Size);
++}
++
++gceSTATUS
++_DefaultMapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ )
++{
++ *Logical = _CreateKernelVirtualMapping(Mdl);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultUnmapKernel(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ )
++{
++ _DestoryKernelVirtualMapping(Logical);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultLogicalToPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ return _ConvertLogical2Physical(
++ Allocator->os, Logical, ProcessID, Mdl, Physical);
++}
++
++gceSTATUS
++_DefaultCache(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_DefaultPhysical(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ gcmkASSERT(Mdl->pagedMem && !Mdl->contiguous);
++ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, Offset);
++
++ return gcvSTATUS_OK;
++}
++
++void
++_DefaultAllocatorDestructor(
++ IN void* PrivateData
++ )
++{
++ kfree(PrivateData);
++}
++
++/* Default allocator operations. */
++gcsALLOCATOR_OPERATIONS DefaultAllocatorOperations = {
++ .Alloc = _DefaultAlloc,
++ .Free = _DefaultFree,
++ .MapUser = _DefaultMapUser,
++ .UnmapUser = _DefaultUnmapUser,
++ .MapKernel = _DefaultMapKernel,
++ .UnmapKernel = _DefaultUnmapKernel,
++ .LogicalToPhysical = _DefaultLogicalToPhysical,
++ .Cache = _DefaultCache,
++ .Physical = _DefaultPhysical,
++};
++
++/* Default allocator entry. */
++gceSTATUS
++_DefaultAlloctorInit(
++ IN gckOS Os,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++ gcsDEFAULT_PRIV_PTR priv = gcvNULL;
++
++ gcmkONERROR(
++ gckALLOCATOR_Construct(Os, &DefaultAllocatorOperations, &allocator));
++
++ priv = kzalloc(gcmSIZEOF(gcsDEFAULT_PRIV), GFP_KERNEL | gcdNOWARN);
++
++ if (!priv)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Register private data. */
++ allocator->privateData = priv;
++ allocator->privateDataDestructor = _DefaultAllocatorDestructor;
++
++ allocator->debugfsInit = _DefaultAllocatorDebugfsInit;
++ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup;
++
++ *Allocator = allocator;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++/***************************************************************************\
++************************ Allocator helper ***********************************
++\***************************************************************************/
++
++gceSTATUS
++gckALLOCATOR_Construct(
++ IN gckOS Os,
++ IN gcsALLOCATOR_OPERATIONS * Operations,
++ OUT gckALLOCATOR * Allocator
++ )
++{
++ gceSTATUS status;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=%p, Operations=%p, Allocator=%p",
++ Os, Operations, Allocator);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Allocator != gcvNULL);
++ gcmkVERIFY_ARGUMENT
++ ( Operations
++ && Operations->Alloc
++ && Operations->Free
++ && Operations->MapUser
++ && Operations->UnmapUser
++ && Operations->MapKernel
++ && Operations->UnmapKernel
++ && Operations->LogicalToPhysical
++ && Operations->Cache
++ && Operations->Physical
++ );
++
++ gcmkONERROR(
++ gckOS_Allocate(Os, gcmSIZEOF(gcsALLOCATOR), (gctPOINTER *)&allocator));
++
++ gckOS_ZeroMemory(allocator, gcmSIZEOF(gcsALLOCATOR));
++
++ /* Record os. */
++ allocator->os = Os;
++
++ /* Set operations. */
++ allocator->ops = Operations;
++
++ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS
++ | gcvALLOC_FLAG_NON_CONTIGUOUS
++ | gcvALLOC_FLAG_CACHEABLE
++ | gcvALLOC_FLAG_MEMLIMIT;
++ ;
++
++ *Allocator = allocator;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/******************************************************************************\
++******************************** Debugfs Support *******************************
++\******************************************************************************/
++
++static gceSTATUS
++_AllocatorDebugfsInit(
++ IN gckOS Os
++ )
++{
++ gceSTATUS status;
++ gckGALDEVICE device = Os->device;
++
++ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir;
++
++ gcmkONERROR(gckDEBUGFS_DIR_Init(dir, device->debugfsDir.root, "allocators"));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++static void
++_AllocatorDebugfsCleanup(
++ IN gckOS Os
++ )
++{
++ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir;
++
++ gckDEBUGFS_DIR_Deinit(dir);
++}
++
++/***************************************************************************\
++************************ Allocator management *******************************
++\***************************************************************************/
++
++gceSTATUS
++gckOS_ImportAllocators(
++ gckOS Os
++ )
++{
++ gceSTATUS status;
++ gctUINT i;
++ gckALLOCATOR allocator;
++
++ _AllocatorDebugfsInit(Os);
++
++ INIT_LIST_HEAD(&Os->allocatorList);
++
++ for (i = 0; i < gcmCOUNTOF(allocatorArray); i++)
++ {
++ if (allocatorArray[i].construct)
++ {
++ /* Construct allocator. */
++ status = allocatorArray[i].construct(Os, &allocator);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkPRINT("["DEVICE_NAME"]: Can't construct allocator(%s)",
++ allocatorArray[i].name);
++
++ continue;
++ }
++
++ allocator->name = allocatorArray[i].name;
++
++ if (allocator->debugfsInit)
++ {
++ /* Init allocator's debugfs. */
++ allocator->debugfsInit(allocator, &Os->allocatorDebugfsDir);
++ }
++
++ list_add_tail(&allocator->head, &Os->allocatorList);
++ }
++ }
++
++#if gcdDEBUG
++ list_for_each_entry(allocator, &Os->allocatorList, head)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d) Allocator: %s",
++ __FUNCTION__, __LINE__,
++ allocator->name
++ );
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_FreeAllocators(
++ gckOS Os
++ )
++{
++ gckALLOCATOR allocator;
++ gckALLOCATOR temp;
++
++ list_for_each_entry_safe(allocator, temp, &Os->allocatorList, head)
++ {
++ list_del(&allocator->head);
++
++ if (allocator->debugfsCleanup)
++ {
++ /* Clean up allocator's debugfs. */
++ allocator->debugfsCleanup(allocator);
++ }
++
++ /* Free private data. */
++ if (allocator->privateDataDestructor && allocator->privateData)
++ {
++ allocator->privateDataDestructor(allocator->privateData);
++ }
++
++ gckOS_Free(Os, allocator);
++ }
++
++ _AllocatorDebugfsCleanup(Os);
++
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_allocator.h 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,400 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_allocator_h_
++#define __gc_hal_kernel_allocator_h_
++
++#include "gc_hal_kernel_linux.h"
++
++typedef struct _gcsALLOCATOR * gckALLOCATOR;
++
++typedef struct _gcsALLOCATOR_OPERATIONS
++{
++ /**************************************************************************
++ **
++ ** Alloc
++ **
++ ** Allocte memory, request size is page aligned.
++ **
++ ** INPUT:
++ **
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_Mdl
++ ** Pointer to Mdl whichs stores information
++ ** about allocated memory.
++ **
++ ** gctSIZE_T NumPages
++ ** Number of pages need to allocate.
++ **
++ ** gctUINT32 Flag
++ ** Allocation option.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS
++ (*Alloc)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctSIZE_T NumPages,
++ IN gctUINT32 Flag
++ );
++
++ /**************************************************************************
++ **
++ ** Free
++ **
++ ** Free memory.
++ **
++ ** INPUT:
++ **
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Mdl which stores information.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ void
++ (*Free)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl
++ );
++
++ /**************************************************************************
++ **
++ ** MapUser
++ **
++ ** Map memory to user space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl.
++ **
++ ** PLINUX_MDL_MAP MdlMap
++ ** Pointer to a MdlMap, mapped address is stored
++ ** in MdlMap->vmaAddr
++ **
++ ** gctBOOL Cacheable
++ ** Whether this mapping is cacheable.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gctINT
++ (*MapUser)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap,
++ IN gctBOOL Cacheable
++ );
++
++ /**************************************************************************
++ **
++ ** UnmapUser
++ **
++ ** Unmap address from user address space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** gctPOINTER Logical
++ ** Address to be unmap
++ **
++ ** gctUINT32 Size
++ ** Size of address space
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ void
++ (*UnmapUser)(
++ IN gckALLOCATOR Allocator,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ );
++
++ /**************************************************************************
++ **
++ ** MapKernel
++ **
++ ** Map memory to kernel space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** OUTPUT:
++ ** gctPOINTER * Logical
++ ** Mapped kernel address.
++ */
++ gceSTATUS
++ (*MapKernel)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ OUT gctPOINTER *Logical
++ );
++
++ /**************************************************************************
++ **
++ ** UnmapKernel
++ **
++ ** Unmap memory from kernel space.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Mapped kernel address.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS
++ (*UnmapKernel)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical
++ );
++
++ /**************************************************************************
++ **
++ ** LogicalToPhysical
++ **
++ ** Get physical address from logical address, logical
++ ** address could be user virtual address or kernel
++ ** virtual address.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Mapped kernel address.
++ **
++ ** gctUINT32 ProcessID
++ ** pid of current process.
++ ** OUTPUT:
++ **
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ */
++ gceSTATUS
++ (*LogicalToPhysical)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32_PTR Physical
++ );
++
++ /**************************************************************************
++ **
++ ** Cache
++ **
++ ** Maintain cache coherency.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctPOINTER Logical
++ ** Logical address, could be user address or kernel address
++ **
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ ** gctUINT32 Bytes
++ ** Size of memory region.
++ **
++ ** gceCACHEOPERATION Opertaion
++ ** Cache operation.
++ **
++ ** OUTPUT:
++ **
++ ** Nothing.
++ **
++ */
++ gceSTATUS (*Cache)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctPOINTER Logical,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++
++ /**************************************************************************
++ **
++ ** Physical
++ **
++ ** Get physical address from a offset in memory region.
++ **
++ ** INPUT:
++ ** gckALLOCATOR Allocator
++ ** Pointer to an gckALLOCATOER object.
++ **
++ ** PLINUX_MDL Mdl
++ ** Pointer to a Mdl object.
++ **
++ ** gctUINT32 Offset
++ ** Offset in this memory region.
++ **
++ ** OUTPUT:
++ ** gctUINT32_PTR Physical
++ ** Physical address.
++ **
++ */
++ gceSTATUS (*Physical)(
++ IN gckALLOCATOR Allocator,
++ IN PLINUX_MDL Mdl,
++ IN gctUINT32 Offset,
++ OUT gctUINT32_PTR Physical
++ );
++}
++gcsALLOCATOR_OPERATIONS;
++
++typedef struct _gcsALLOCATOR
++{
++ /* Pointer to gckOS Object. */
++ gckOS os;
++
++ /* Name. */
++ gctSTRING name;
++
++ /* Operations. */
++ gcsALLOCATOR_OPERATIONS* ops;
++
++ /* Capability of this allocator. */
++ gctUINT32 capability;
++
++ struct list_head head;
++
++ /* Debugfs entry of this allocator. */
++ gcsDEBUGFS_DIR debugfsDir;
++
++ /* Init allocator debugfs. */
++ void (*debugfsInit)(gckALLOCATOR, gckDEBUGFS_DIR);
++
++ /* Cleanup allocator debugfs. */
++ void (*debugfsCleanup)(gckALLOCATOR);
++
++ /* Private data used by customer allocator. */
++ void * privateData;
++
++ /* Private data destructor. */
++ void (*privateDataDestructor)(void *);
++}
++gcsALLOCATOR;
++
++typedef struct _gcsALLOCATOR_DESC
++{
++ /* Name of a allocator. */
++ char * name;
++
++ /* Entry function to construct a allocator. */
++ gceSTATUS (*construct)(gckOS, gckALLOCATOR *);
++}
++gcsALLOCATOR_DESC;
++
++/*
++* Helpers
++*/
++
++/* Fill a gcsALLOCATOR_DESC structure. */
++#define gcmkDEFINE_ALLOCATOR_DESC(Name, Construct) \
++ { \
++ .name = Name, \
++ .construct = Construct, \
++ }
++
++/* Construct a allocator. */
++gceSTATUS
++gckALLOCATOR_Construct(
++ IN gckOS Os,
++ IN gcsALLOCATOR_OPERATIONS * Operations,
++ OUT gckALLOCATOR * Allocator
++ );
++
++/*
++ How to implement customer allocator
++
++ Build in customer alloctor
++
++ It is recommanded that customer allocator is implmented in independent
++ source file(s) which is specified by CUSOMTER_ALLOCATOR_OBJS in Kbuld.
++
++ Register gcsALLOCATOR
++
++ For each customer specified allocator, a desciption entry must be added
++ to allocatorArray defined in gc_hal_kernel_allocator_array.h.
++
++ An entry in allocatorArray is a gcsALLOCATOR_DESC structure which describes
++ name and constructor of a gckALLOCATOR object.
++
++
++ Implement gcsALLOCATOR_DESC.init()
++
++ In gcsALLOCATOR_DESC.init(), gckALLOCATOR_Construct should be called
++ to create a gckALLOCATOR object, customer specified private data can
++ be put in gcsALLOCATOR.privateData.
++
++
++ Implement gcsALLOCATOR_OPERATIONS
++
++ When call gckALLOCATOR_Construct to create a gckALLOCATOR object, a
++ gcsALLOCATOR_OPERATIONS structure must be provided whose all members
++ implemented.
++
++*/
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.c 2016-06-19 22:11:55.241144206 +0200
+@@ -0,0 +1,1166 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifdef MODULE
++#include <linux/module.h>
++#endif
++#include <linux/init.h>
++#include <linux/debugfs.h>
++#include <linux/slab.h>
++#ifdef MODVERSIONS
++#include <linux/modversions.h>
++#endif
++#include <linux/stddef.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/timer.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/mutex.h>
++#include <linux/vmalloc.h>
++#include <linux/types.h>
++#include <linux/fs.h>
++#include <linux/poll.h>
++#include <asm/uaccess.h>
++#include <linux/completion.h>
++#include <linux/seq_file.h>
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel.h"
++
++/*
++ Prequsite:
++
++ 1) Debugfs feature must be enabled in the kernel.
++ 1.a) You can enable this, in the compilation of the uImage, all you have to do is, In the "make menuconfig" part,
++ you have to enable the debugfs in the kernel hacking part of the menu.
++
++ HOW TO USE:
++ 1) insert the driver with the following option logFileSize, Ex: insmod galcore.ko ...... logFileSize=10240
++ This gives a circular buffer of 10 MB
++
++ 2)Usually after inserting the driver, the debug file system is mounted under /sys/kernel/debug/
++
++ 2.a)If the debugfs is not mounted, you must do "mount -t debugfs none /sys/kernel/debug"
++
++ 3) To read what is being printed in the debugfs file system:
++ Ex : cat /sys/kernel/debug/gc/galcore_trace
++
++ 4)To write into the debug file system from user side :
++ Ex: echo "hello" > cat /sys/kernel/debug/gc/galcore_trace
++
++ 5)To write into debugfs from kernel side, Use the function called gckDEBUGFS_Print
++
++ How to Get Video Memory Usage:
++ 1) Select a process whose video memory usage can be dump, no need to reset it until <pid> is needed to be change.
++ echo <pid> > /sys/kernel/debug/gc/vidmem
++
++ 2) Get video memory usage.
++ cat /sys/kernel/debug/gc/vidmem
++
++ USECASE Kernel Dump:
++
++ 1) Go to /hal/inc/gc_hal_options.h, and enable the following flags:
++ - # define gcdDUMP 1
++ - # define gcdDUMP_IN_KERNEL 1
++ - # define gcdDUMP_COMMAND 1
++
++ 2) Go to /hal/kernel/gc_hal_kernel_command.c and disable the following flag
++ -#define gcdSIMPLE_COMMAND_DUMP 0
++
++ 3) Compile the driver
++ 4) insmod it with the logFileSize option
++ 5) Run an application
++ 6) You can get the dump by cat /sys/kernel/debug/gpu/galcore_trace
++
++ */
++
++/**/
++typedef va_list gctDBGARGS ;
++#define gcmkARGS_START(argument, pointer) va_start(argument, pointer)
++#define gcmkARGS_END(argument) va_end(argument)
++
++#define gcmkDEBUGFS_PRINT(ArgumentSize, Message) \
++ { \
++ gctDBGARGS __arguments__; \
++ gcmkARGS_START(__arguments__, Message); \
++ _debugfs_res = _DebugFSPrint(ArgumentSize, Message, &__arguments__);\
++ gcmkARGS_END(__arguments__); \
++ }
++
++/* Debug File System Node Struct. */
++struct _gcsDEBUGFS_Node
++{
++ /*wait queues for read and write operations*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ wait_queue_head_t read_q , write_q ;
++#else
++ struct wait_queue *read_q , *write_q ;
++#endif
++ struct dentry *parent ; /*parent directory*/
++ struct dentry *filen ; /*filename*/
++ struct dentry *vidmem;
++ struct semaphore sem ; /* mutual exclusion semaphore */
++ char *data ; /* The circular buffer data */
++ int size ; /* Size of the buffer pointed to by 'data' */
++ int refcount ; /* Files that have this buffer open */
++ int read_point ; /* Offset in circ. buffer of oldest data */
++ int write_point ; /* Offset in circ. buffer of newest data */
++ int offset ; /* Byte number of read_point in the stream */
++ struct _gcsDEBUGFS_Node *next ;
++};
++
++/* amount of data in the queue */
++#define gcmkNODE_QLEN(node) ( (node)->write_point >= (node)->read_point ? \
++ (node)->write_point - (node)->read_point : \
++ (node)->size - (node)->read_point + (node)->write_point)
++
++/* byte number of the last byte in the queue */
++#define gcmkNODE_FIRST_EMPTY_BYTE(node) ((node)->offset + gcmkNODE_QLEN(node))
++
++/*Synchronization primitives*/
++#define gcmkNODE_READQ(node) (&((node)->read_q))
++#define gcmkNODE_WRITEQ(node) (&((node)->write_q))
++#define gcmkNODE_SEM(node) (&((node)->sem))
++
++/*Utilities*/
++#define gcmkMIN(x, y) ((x) < (y) ? (x) : y)
++
++/*Debug File System Struct*/
++typedef struct _gcsDEBUGFS_
++{
++ gcsDEBUGFS_Node* linkedlist ;
++ gcsDEBUGFS_Node* currentNode ;
++ int isInited ;
++} gcsDEBUGFS_ ;
++
++/*debug file system*/
++static gcsDEBUGFS_ gc_dbgfs ;
++
++static int gc_debugfs_open(struct inode *inode, struct file *file)
++{
++ gcsINFO_NODE *node = inode->i_private;
++
++ return single_open(file, node->info->show, node);
++}
++
++static const struct file_operations gc_debugfs_operations = {
++ .owner = THIS_MODULE,
++ .open = gc_debugfs_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++gceSTATUS
++gckDEBUGFS_DIR_Init(
++ IN gckDEBUGFS_DIR Dir,
++ IN struct dentry *root,
++ IN gctCONST_STRING Name
++ )
++{
++ Dir->root = debugfs_create_dir(Name, root);
++
++ if (!Dir->root)
++ {
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ INIT_LIST_HEAD(&Dir->nodeList);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckDEBUGFS_DIR_CreateFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count,
++ IN gctPOINTER Data
++ )
++{
++ int i;
++ gcsINFO_NODE * node;
++ gceSTATUS status;
++
++ for (i = 0; i < count; i++)
++ {
++ /* Create a node. */
++ node = (gcsINFO_NODE *)kzalloc(sizeof(gcsINFO_NODE), GFP_KERNEL);
++
++ node->info = &List[i];
++ node->device = Data;
++
++ /* Bind to a file. TODO: clean up when fail. */
++ node->entry = debugfs_create_file(
++ List[i].name, S_IRUGO|S_IWUSR, Dir->root, node, &gc_debugfs_operations);
++
++ if (!node->entry)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ list_add(&(node->head), &(Dir->nodeList));
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(Dir, List, count));
++ return status;
++}
++
++gceSTATUS
++gckDEBUGFS_DIR_RemoveFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count
++ )
++{
++ int i;
++ gcsINFO_NODE * node;
++ gcsINFO_NODE * temp;
++
++ for (i = 0; i < count; i++)
++ {
++ list_for_each_entry_safe(node, temp, &Dir->nodeList, head)
++ {
++ if (node->info == &List[i])
++ {
++ debugfs_remove(node->entry);
++ list_del(&node->head);
++ kfree(node);
++ }
++ }
++ }
++
++ return gcvSTATUS_OK;
++}
++
++void
++gckDEBUGFS_DIR_Deinit(
++ IN gckDEBUGFS_DIR Dir
++ )
++{
++ if (Dir->root != NULL)
++ {
++ debugfs_remove(Dir->root);
++ Dir->root = NULL;
++ }
++}
++
++/*******************************************************************************
++ **
++ ** READ & WRITE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _ReadFromNode
++ **
++ ** 1) reading bytes out of a circular buffer with wraparound.
++ ** 2)returns caddr_t, pointer to data read, which the caller must free.
++ ** 3) length is (a pointer to) the number of bytes to be read, which will be set by this function to
++ ** be the number of bytes actually returned
++ **
++ *******************************************************************************/
++static caddr_t
++_ReadFromNode (
++ gcsDEBUGFS_Node* Node ,
++ size_t *Length ,
++ loff_t *Offset
++ )
++{
++ caddr_t retval ;
++ int bytes_copied = 0 , n , start_point , remaining ;
++
++ /* is the user trying to read data that has already scrolled off? */
++ if ( *Offset < Node->offset )
++ {
++ *Offset = Node->offset ;
++ }
++
++ /* is the user trying to read past EOF? */
++ if ( *Offset >= gcmkNODE_FIRST_EMPTY_BYTE ( Node ) )
++ {
++ return NULL ;
++ }
++
++ /* find the smaller of the total bytes we have available and what
++ * the user is asking for */
++
++ *Length = gcmkMIN ( *Length , gcmkNODE_FIRST_EMPTY_BYTE ( Node ) - *Offset ) ;
++
++ remaining = * Length ;
++
++ /* figure out where to start based on user's Offset */
++ start_point = Node->read_point + ( *Offset - Node->offset ) ;
++
++ start_point = start_point % Node->size ;
++
++ /* allocate memory to return */
++ if ( ( retval = kmalloc ( sizeof (char ) * remaining , GFP_KERNEL ) ) == NULL )
++ return NULL ;
++
++ /* copy the (possibly noncontiguous) data to our buffer */
++ while ( remaining )
++ {
++ n = gcmkMIN ( remaining , Node->size - start_point ) ;
++ memcpy ( retval + bytes_copied , Node->data + start_point , n ) ;
++ bytes_copied += n ;
++ remaining -= n ;
++ start_point = ( start_point + n ) % Node->size ;
++ }
++
++ /* advance user's file pointer */
++ *Offset += * Length ;
++
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ ** _WriteToNode
++ **
++ ** 1) writes to a circular buffer with wraparound.
++ ** 2)in case of an overflow, it overwrites the oldest unread data.
++ **
++ *********************************************************************************/
++static void
++_WriteToNode (
++ gcsDEBUGFS_Node* Node ,
++ caddr_t Buf ,
++ int Length
++ )
++{
++ int bytes_copied = 0 ;
++ int overflow = 0 ;
++ int n ;
++
++ if ( Length + gcmkNODE_QLEN ( Node ) >= ( Node->size - 1 ) )
++ {
++ overflow = 1 ;
++
++ /* in case of overflow, figure out where the new buffer will
++ * begin. we start by figuring out where the current buffer ENDS:
++ * node->parent->offset + gcmkNODE_QLEN. we then advance the end-offset
++ * by the Length of the current write, and work backwards to
++ * figure out what the oldest unoverwritten data will be (i.e.,
++ * size of the buffer). */
++ Node->offset = Node->offset + gcmkNODE_QLEN ( Node ) + Length
++ - Node->size + 1 ;
++ }
++
++ while ( Length )
++ {
++ /* how many contiguous bytes are available from the write point to
++ * the end of the circular buffer? */
++ n = gcmkMIN ( Length , Node->size - Node->write_point ) ;
++ memcpy ( Node->data + Node->write_point , Buf + bytes_copied , n ) ;
++ bytes_copied += n ;
++ Length -= n ;
++ Node->write_point = ( Node->write_point + n ) % Node->size ;
++ }
++
++ /* if there is an overflow, reset the read point to read whatever is
++ * the oldest data that we have, that has not yet been
++ * overwritten. */
++ if ( overflow )
++ {
++ Node->read_point = ( Node->write_point + 1 ) % Node->size ;
++ }
++}
++
++/*******************************************************************************
++ **
++ ** PRINTING UTILITY (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** _GetArgumentSize
++ **
++ **
++ *******************************************************************************/
++static gctINT
++_GetArgumentSize (
++ IN gctCONST_STRING Message
++ )
++{
++ gctINT i , count ;
++
++ for ( i = 0 , count = 0 ; Message[i] ; i += 1 )
++ {
++ if ( Message[i] == '%' )
++ {
++ count += 1 ;
++ }
++ }
++ return count * sizeof (unsigned int ) ;
++}
++
++/*******************************************************************************
++ **
++ ** _AppendString
++ **
++ **
++ *******************************************************************************/
++static ssize_t
++_AppendString (
++ IN gcsDEBUGFS_Node* Node ,
++ IN gctCONST_STRING String ,
++ IN int Length
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( Length , Node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL )
++ return - ENOMEM ;
++
++ /* copy into our temp buffer */
++ memcpy ( message , String , n ) ;
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( Node , message , n ) ;
++ kfree ( message ) ;
++ return n ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSPrint
++ **
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSPrint (
++ IN unsigned int ArgumentSize ,
++ IN const char* Message ,
++ IN gctDBGARGS * Arguments
++
++ )
++{
++ char buffer[MAX_LINE_SIZE] ;
++ int len ;
++ ssize_t res=0;
++
++ if(in_interrupt())
++ {
++ return - ERESTARTSYS ;
++ }
++
++ if(down_interruptible( gcmkNODE_SEM ( gc_dbgfs.currentNode ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++ len = vsnprintf ( buffer , sizeof (buffer ) , Message , *( va_list * ) Arguments ) ;
++ buffer[len] = '\0' ;
++
++ /* Add end-of-line if missing. */
++ if ( buffer[len - 1] != '\n' )
++ {
++ buffer[len ++] = '\n' ;
++ buffer[len] = '\0' ;
++ }
++ res = _AppendString ( gc_dbgfs.currentNode , buffer , len ) ;
++ up ( gcmkNODE_SEM ( gc_dbgfs.currentNode ) ) ;
++ wake_up_interruptible ( gcmkNODE_READQ ( gc_dbgfs.currentNode ) ) ; /* blocked in read*/
++ return res;
++}
++
++/*******************************************************************************
++ **
++ ** LINUX SYSTEM FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** find the vivlog structure associated with an inode.
++ ** returns a pointer to the structure if found, NULL if not found
++ **
++ *******************************************************************************/
++static gcsDEBUGFS_Node*
++_GetNodeInfo (
++ IN struct inode *Inode
++ )
++{
++ gcsDEBUGFS_Node* node ;
++
++ if ( Inode == NULL )
++ return NULL ;
++
++ for ( node = gc_dbgfs.linkedlist ; node != NULL ; node = node->next )
++ if ( node->filen->d_inode->i_ino == Inode->i_ino )
++ return node ;
++
++ return NULL ;
++}
++
++/*******************************************************************************
++ **
++ ** _DebugFSRead
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSRead (
++ struct file *file ,
++ char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ int retval ;
++ caddr_t data_to_return ;
++ gcsDEBUGFS_Node* node ;
++ /* get the metadata about this emlog */
++ if ( ( node = _GetNodeInfo ( file->f_dentry->d_inode ) ) == NULL )
++ {
++ printk ( "debugfs_read: record not found\n" ) ;
++ return - EIO ;
++ }
++
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++
++ /* wait until there's data available (unless we do nonblocking reads) */
++ while ( *offset >= gcmkNODE_FIRST_EMPTY_BYTE ( node ) )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ if ( file->f_flags & O_NONBLOCK )
++ {
++ return - EAGAIN ;
++ }
++ if ( wait_event_interruptible ( ( *( gcmkNODE_READQ ( node ) ) ) , ( *offset < gcmkNODE_FIRST_EMPTY_BYTE ( node ) ) ) )
++ {
++ return - ERESTARTSYS ; /* signal: tell the fs layer to handle it */
++ }
++ /* otherwise loop, but first reacquire the lock */
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++ }
++ data_to_return = _ReadFromNode ( node , &length , offset ) ;
++ if ( data_to_return == NULL )
++ {
++ retval = 0 ;
++ goto unlock ;
++ }
++ if ( copy_to_user ( buffer , data_to_return , length ) > 0 )
++ {
++ retval = - EFAULT ;
++ }
++ else
++ {
++ retval = length ;
++ }
++ kfree ( data_to_return ) ;
++unlock:
++ up ( gcmkNODE_SEM ( node ) ) ;
++ wake_up_interruptible ( gcmkNODE_WRITEQ ( node ) ) ;
++ return retval ;
++}
++
++/*******************************************************************************
++ **
++ **_DebugFSWrite
++ **
++ *******************************************************************************/
++static ssize_t
++_DebugFSWrite (
++ struct file *file ,
++ const char __user * buffer ,
++ size_t length ,
++ loff_t * offset
++ )
++{
++ caddr_t message = NULL ;
++ int n ;
++ gcsDEBUGFS_Node*node ;
++
++ /* get the metadata about this log */
++ if ( ( node = _GetNodeInfo ( file->f_dentry->d_inode ) ) == NULL )
++ {
++ return - EIO ;
++ }
++
++ if ( down_interruptible ( gcmkNODE_SEM ( node ) ) )
++ {
++ return - ERESTARTSYS ;
++ }
++
++ /* if the message is longer than the buffer, just take the beginning
++ * of it, in hopes that the reader (if any) will have time to read
++ * before we wrap around and obliterate it */
++ n = gcmkMIN ( length , node->size - 1 ) ;
++
++ /* make sure we have the memory for it */
++ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ return - ENOMEM ;
++ }
++
++
++ /* copy into our temp buffer */
++ if ( copy_from_user ( message , buffer , n ) > 0 )
++ {
++ up ( gcmkNODE_SEM ( node ) ) ;
++ kfree ( message ) ;
++ return - EFAULT ;
++ }
++
++ /* now copy it into the circular buffer and free our temp copy */
++ _WriteToNode ( node , message , n ) ;
++
++ kfree ( message ) ;
++ up ( gcmkNODE_SEM ( node ) ) ;
++
++ /* wake up any readers that might be waiting for the data. we call
++ * schedule in the vague hope that a reader will run before the
++ * writer's next write, to avoid losing data. */
++ wake_up_interruptible ( gcmkNODE_READQ ( node ) ) ;
++
++ return n ;
++}
++
++int dumpProcess = 0;
++
++void
++_PrintCounter(
++ struct seq_file *file,
++ gcsDATABASE_COUNTERS * counter,
++ gctCONST_STRING Name
++ )
++{
++ seq_printf(file,"Counter: %s\n", Name);
++
++ seq_printf(file,"%-9s%10s","", "All");
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Current");
++
++ seq_printf(file,"%10lld", counter->bytes);
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Maximum");
++
++ seq_printf(file,"%10lld", counter->maxBytes);
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Total");
++
++ seq_printf(file,"%10lld", counter->totalBytes);
++
++ seq_printf(file, "\n");
++}
++
++void
++_ShowCounters(
++ struct seq_file *file,
++ gcsDATABASE_PTR database
++ )
++{
++ gctUINT i = 0;
++ gcsDATABASE_COUNTERS * counter;
++ gcsDATABASE_COUNTERS * nonPaged;
++
++ static gctCONST_STRING surfaceTypes[] = {
++ "UNKNOWN",
++ "Index",
++ "Vertex",
++ "Texture",
++ "RT",
++ "Depth",
++ "Bitmap",
++ "TS",
++ "Image",
++ "Mask",
++ "Scissor",
++ "HZDepth",
++ };
++
++ /* Get pointer to counters. */
++ counter = &database->vidMem;
++
++ nonPaged = &database->nonPaged;
++
++ seq_printf(file,"Counter: vidMem (for each surface type)\n");
++
++ seq_printf(file,"%-9s%10s","", "All");
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file, "%10s",surfaceTypes[i]);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Current");
++
++ seq_printf(file,"%10lld", database->vidMem.bytes);
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file,"%10lld", counter->bytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Maximum");
++
++ seq_printf(file,"%10lld", database->vidMem.maxBytes);
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file,"%10lld", counter->maxBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Total");
++
++ seq_printf(file,"%10lld", database->vidMem.totalBytes);
++
++ for (i = 1; i < gcvSURF_NUM_TYPES; i++)
++ {
++ counter = &database->vidMemType[i];
++
++ seq_printf(file,"%10lld", counter->totalBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"Counter: vidMem (for each pool)\n");
++
++ seq_printf(file,"%-9s%10s","", "All");
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ seq_printf(file, "%10d", i);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Current");
++
++ seq_printf(file,"%10lld", database->vidMem.bytes);
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ counter = &database->vidMemPool[i];
++
++ seq_printf(file,"%10lld", counter->bytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Maximum");
++
++ seq_printf(file,"%10lld", database->vidMem.maxBytes);
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ counter = &database->vidMemPool[i];
++
++ seq_printf(file,"%10lld", counter->maxBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ seq_printf(file,"%-9s","Total");
++
++ seq_printf(file,"%10lld", database->vidMem.totalBytes);
++
++ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++)
++ {
++ counter = &database->vidMemPool[i];
++
++ seq_printf(file,"%10lld", counter->totalBytes);
++ }
++
++ seq_printf(file, "\n");
++
++ /* Print nonPaged. */
++ _PrintCounter(file, &database->nonPaged, "nonPaged");
++ _PrintCounter(file, &database->contiguous, "contiguous");
++ _PrintCounter(file, &database->mapUserMemory, "mapUserMemory");
++ _PrintCounter(file, &database->mapMemory, "mapMemory");
++}
++
++gckKERNEL
++_GetValidKernel(
++ gckGALDEVICE Device
++);
++static int vidmem_show(struct seq_file *file, void *unused)
++{
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gckGALDEVICE device = file->private;
++
++ gckKERNEL kernel = _GetValidKernel(device);
++ if(kernel == gcvNULL)
++ {
++ return 0;
++ }
++
++ /* Find the database. */
++ gcmkONERROR(
++ gckKERNEL_FindDatabase(kernel, dumpProcess, gcvFALSE, &database));
++
++ seq_printf(file, "VidMem Usage (Process %d):\n", dumpProcess);
++
++ _ShowCounters(file, database);
++
++ return 0;
++
++OnError:
++ return 0;
++}
++
++static int
++vidmem_open(
++ struct inode *inode,
++ struct file *file
++ )
++{
++ return single_open(file, vidmem_show, inode->i_private);
++}
++
++static ssize_t
++vidmem_write(
++ struct file *file,
++ const char __user *buf,
++ size_t count,
++ loff_t *pos
++ )
++{
++ dumpProcess = simple_strtol(buf, NULL, 0);
++ return count;
++}
++
++/*******************************************************************************
++ **
++ ** File Operations Table
++ **
++ *******************************************************************************/
++static const struct file_operations debugfs_operations = {
++ .owner = THIS_MODULE ,
++ .read = _DebugFSRead ,
++ .write = _DebugFSWrite ,
++} ;
++
++static const struct file_operations vidmem_operations = {
++ .owner = THIS_MODULE ,
++ .open = vidmem_open,
++ .read = seq_read,
++ .write = vidmem_write,
++ .llseek = seq_lseek,
++} ;
++
++/*******************************************************************************
++ **
++ ** INTERFACE FUNCTIONS (START)
++ **
++ *******************************************************************************/
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_IsEnabled
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++
++gctINT
++gckDEBUGFS_IsEnabled ( void )
++{
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_Initialize
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDEBUGFS_Initialize ( void )
++{
++ if ( ! gc_dbgfs.isInited )
++ {
++ gc_dbgfs.linkedlist = gcvNULL ;
++ gc_dbgfs.currentNode = gcvNULL ;
++ gc_dbgfs.isInited = 1 ;
++ }
++ return gc_dbgfs.isInited ;
++}
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_Terminate
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++
++gctINT
++gckDEBUGFS_Terminate ( void )
++{
++ gcsDEBUGFS_Node * next = gcvNULL ;
++ gcsDEBUGFS_Node * temp = gcvNULL ;
++ if ( gc_dbgfs.isInited )
++ {
++ temp = gc_dbgfs.linkedlist ;
++ while ( temp != gcvNULL )
++ {
++ next = temp->next ;
++ gckDEBUGFS_FreeNode ( temp ) ;
++ kfree ( temp ) ;
++ temp = next ;
++ }
++ gc_dbgfs.isInited = 0 ;
++ }
++ return 0 ;
++}
++
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_CreateNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ ** gckDEBUGFS_FreeNode * Device
++ ** Pointer to a variable receiving the gcsDEBUGFS_Node object pointer on
++ ** success.
++ *********************************************************************************/
++
++gctINT
++gckDEBUGFS_CreateNode (
++ IN gctPOINTER Device,
++ IN gctINT SizeInKB ,
++ IN struct dentry * Root ,
++ IN gctCONST_STRING NodeName ,
++ OUT gcsDEBUGFS_Node **Node
++ )
++{
++ gcsDEBUGFS_Node*node ;
++ /* allocate space for our metadata and initialize it */
++ if ( ( node = kmalloc ( sizeof (gcsDEBUGFS_Node ) , GFP_KERNEL ) ) == NULL )
++ goto struct_malloc_failed ;
++
++ /*Zero it out*/
++ memset ( node , 0 , sizeof (gcsDEBUGFS_Node ) ) ;
++
++ /*Init the sync primitives*/
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_READQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_READQ ( node ) ) ;
++#endif
++
++#if defined(DECLARE_WAIT_QUEUE_HEAD)
++ init_waitqueue_head ( gcmkNODE_WRITEQ ( node ) ) ;
++#else
++ init_waitqueue ( gcmkNODE_WRITEQ ( node ) ) ;
++#endif
++ sema_init ( gcmkNODE_SEM ( node ) , 1 ) ;
++ /*End the sync primitives*/
++
++ /*creating the debug file system*/
++ node->parent = Root;
++
++ if (SizeInKB)
++ {
++ /* figure out how much of a buffer this should be and allocate the buffer */
++ node->size = 1024 * SizeInKB ;
++ if ( ( node->data = ( char * ) vmalloc ( sizeof (char ) * node->size ) ) == NULL )
++ goto data_malloc_failed ;
++
++ /*creating the file*/
++ node->filen = debugfs_create_file(NodeName, S_IRUGO|S_IWUSR, node->parent, NULL,
++ &debugfs_operations);
++ }
++
++ node->vidmem
++ = debugfs_create_file("vidmem", S_IRUGO|S_IWUSR, node->parent, Device, &vidmem_operations);
++
++ /* add it to our linked list */
++ node->next = gc_dbgfs.linkedlist ;
++ gc_dbgfs.linkedlist = node ;
++
++
++ /* pass the struct back */
++ *Node = node ;
++ return 0 ;
++
++
++data_malloc_failed:
++ kfree ( node ) ;
++struct_malloc_failed:
++ return - ENOMEM ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_FreeNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDEBUGFS_FreeNode (
++ IN gcsDEBUGFS_Node * Node
++ )
++{
++
++ gcsDEBUGFS_Node **ptr ;
++
++ if ( Node == NULL )
++ {
++ printk ( "null passed to free_vinfo\n" ) ;
++ return ;
++ }
++
++ down ( gcmkNODE_SEM ( Node ) ) ;
++ /*free data*/
++ vfree ( Node->data ) ;
++
++ /*Close Debug fs*/
++ if (Node->vidmem)
++ {
++ debugfs_remove(Node->vidmem);
++ }
++
++ if ( Node->filen )
++ {
++ debugfs_remove ( Node->filen ) ;
++ }
++
++ /* now delete the node from the linked list */
++ ptr = & ( gc_dbgfs.linkedlist ) ;
++ while ( *ptr != Node )
++ {
++ if ( ! *ptr )
++ {
++ printk ( "corrupt info list!\n" ) ;
++ break ;
++ }
++ else
++ ptr = & ( ( **ptr ).next ) ;
++ }
++ *ptr = Node->next ;
++ up ( gcmkNODE_SEM ( Node ) ) ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_SetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDEBUGFS_SetCurrentNode (
++ IN gcsDEBUGFS_Node * Node
++ )
++{
++ gc_dbgfs.currentNode = Node ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_GetCurrentNode
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++void
++gckDEBUGFS_GetCurrentNode (
++ OUT gcsDEBUGFS_Node ** Node
++ )
++{
++ *Node = gc_dbgfs.currentNode ;
++}
++
++/*******************************************************************************
++ **
++ ** gckDEBUGFS_Print
++ **
++ **
++ ** INPUT:
++ **
++ ** OUTPUT:
++ **
++ *******************************************************************************/
++ssize_t
++gckDEBUGFS_Print (
++ IN gctCONST_STRING Message ,
++ ...
++ )
++{
++ ssize_t _debugfs_res;
++ gcmkDEBUGFS_PRINT ( _GetArgumentSize ( Message ) , Message ) ;
++ return _debugfs_res;
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debugfs.h 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,135 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <stdarg.h>
++
++#ifndef __gc_hal_kernel_debugfs_h_
++#define __gc_hal_kernel_debugfs_h_
++
++ #define MAX_LINE_SIZE 768 /* Max bytes for a line of debug info */
++
++
++ typedef struct _gcsDEBUGFS_Node gcsDEBUGFS_Node;
++
++typedef struct _gcsDEBUGFS_DIR *gckDEBUGFS_DIR;
++typedef struct _gcsDEBUGFS_DIR
++{
++ struct dentry * root;
++ struct list_head nodeList;
++}
++gcsDEBUGFS_DIR;
++
++typedef struct _gcsINFO
++{
++ const char * name;
++ int (*show)(struct seq_file*, void*);
++}
++gcsINFO;
++
++typedef struct _gcsINFO_NODE
++{
++ gcsINFO * info;
++ gctPOINTER device;
++ struct dentry * entry;
++ struct list_head head;
++}
++gcsINFO_NODE;
++
++gceSTATUS
++gckDEBUGFS_DIR_Init(
++ IN gckDEBUGFS_DIR Dir,
++ IN struct dentry *root,
++ IN gctCONST_STRING Name
++ );
++
++gceSTATUS
++gckDEBUGFS_DIR_CreateFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count,
++ IN gctPOINTER Data
++ );
++
++gceSTATUS
++gckDEBUGFS_DIR_RemoveFiles(
++ IN gckDEBUGFS_DIR Dir,
++ IN gcsINFO * List,
++ IN int count
++ );
++
++void
++gckDEBUGFS_DIR_Deinit(
++ IN gckDEBUGFS_DIR Dir
++ );
++
++/*******************************************************************************
++ **
++ ** System Related
++ **
++ *******************************************************************************/
++
++gctINT gckDEBUGFS_IsEnabled(void);
++
++gctINT gckDEBUGFS_Initialize(void);
++
++gctINT gckDEBUGFS_Terminate(void);
++
++
++/*******************************************************************************
++ **
++ ** Node Related
++ **
++ *******************************************************************************/
++
++gctINT
++gckDEBUGFS_CreateNode(
++ IN gctPOINTER Device,
++ IN gctINT SizeInKB,
++ IN struct dentry * Root,
++ IN gctCONST_STRING NodeName,
++ OUT gcsDEBUGFS_Node **Node
++ );
++
++void gckDEBUGFS_FreeNode(
++ IN gcsDEBUGFS_Node * Node
++ );
++
++
++
++void gckDEBUGFS_SetCurrentNode(
++ IN gcsDEBUGFS_Node * Node
++ );
++
++
++
++void gckDEBUGFS_GetCurrentNode(
++ OUT gcsDEBUGFS_Node ** Node
++ );
++
++
++ssize_t gckDEBUGFS_Print(
++ IN gctCONST_STRING Message,
++ ...
++ );
++
++#endif
++
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_debug.h 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,113 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_debug_h_
++#define __gc_hal_kernel_debug_h_
++
++#include <gc_hal_kernel_linux.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <stdarg.h>
++
++#ifdef __cplusplus
++extern "C" {
++#endif
++
++/******************************************************************************\
++****************************** OS-dependent Macros *****************************
++\******************************************************************************/
++
++typedef va_list gctARGUMENTS;
++
++#define gcmkARGUMENTS_START(Arguments, Pointer) \
++ va_start(Arguments, Pointer)
++
++#define gcmkARGUMENTS_END(Arguments) \
++ va_end(Arguments)
++
++#define gcmkARGUMENTS_ARG(Arguments, Type) \
++ va_arg(Arguments, Type)
++
++#define gcmkDECLARE_LOCK(__spinLock__) \
++ static DEFINE_SPINLOCK(__spinLock__); \
++ unsigned long __spinLock__##flags = 0;
++
++#define gcmkLOCKSECTION(__spinLock__) \
++ spin_lock_irqsave(&__spinLock__, __spinLock__##flags)
++
++#define gcmkUNLOCKSECTION(__spinLock__) \
++ spin_unlock_irqrestore(&__spinLock__, __spinLock__##flags)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# define gcmkGETPROCESSID() \
++ task_tgid_vnr(current)
++#else
++# define gcmkGETPROCESSID() \
++ current->tgid
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++# define gcmkGETTHREADID() \
++ task_pid_vnr(current)
++#else
++# define gcmkGETTHREADID() \
++ current->pid
++#endif
++
++#define gcmkOUTPUT_STRING(String) \
++ if(gckDEBUGFS_IsEnabled()) {\
++ while(-ERESTARTSYS == gckDEBUGFS_Print(String));\
++ }else{\
++ printk(String); \
++ }\
++ touch_softlockup_watchdog()
++
++
++#define gcmkSPRINTF(Destination, Size, Message, Value) \
++ snprintf(Destination, Size, Message, Value)
++
++#define gcmkSPRINTF2(Destination, Size, Message, Value1, Value2) \
++ snprintf(Destination, Size, Message, Value1, Value2)
++
++#define gcmkSPRINTF3(Destination, Size, Message, Value1, Value2, Value3) \
++ snprintf(Destination, Size, Message, Value1, Value2, Value3)
++
++#define gcmkVSPRINTF(Destination, Size, Message, Arguments) \
++ vsnprintf(Destination, Size, Message, *((va_list*)Arguments))
++
++#define gcmkSTRCAT(Destination, Size, String) \
++ strncat(Destination, String, Size)
++
++#define gcmkMEMCPY(Destination, Source, Size) \
++ memcpy(Destination, Source, Size)
++
++#define gcmkSTRLEN(String) \
++ strlen(String)
++
++/* If not zero, forces data alignment in the variable argument list
++ by its individual size. */
++#define gcdALIGNBYSIZE 1
++
++#ifdef __cplusplus
++}
++#endif
++
++#endif /* __gc_hal_kernel_debug_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,2760 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <linux/slab.h>
++
++#define _GC_OBJ_ZONE gcvZONE_DEVICE
++
++#define DEBUG_FILE "galcore_trace"
++#define PARENT_FILE "gpu"
++
++
++#ifdef FLAREON
++ static struct dove_gpio_irq_handler gc500_handle;
++#endif
++
++gckKERNEL
++_GetValidKernel(
++ gckGALDEVICE Device
++ )
++{
++ if (Device->kernels[gcvCORE_MAJOR])
++ {
++ return Device->kernels[gcvCORE_MAJOR];
++ }
++ else
++ if (Device->kernels[gcvCORE_2D])
++ {
++ return Device->kernels[gcvCORE_2D];
++ }
++ else
++ if (Device->kernels[gcvCORE_VG])
++ {
++ return Device->kernels[gcvCORE_VG];
++ }
++ else
++ {
++ return gcvNULL;
++ }
++}
++
++/******************************************************************************\
++******************************** Debugfs Support *******************************
++\******************************************************************************/
++
++/******************************************************************************\
++***************************** DEBUG SHOW FUNCTIONS *****************************
++\******************************************************************************/
++
++int gc_info_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ int i = 0;
++ gceCHIPMODEL chipModel;
++ gctUINT32 chipRevision;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->irqLines[i] != -1)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ chipModel = device->kernels[i]->vg->hardware->chipModel;
++ chipRevision = device->kernels[i]->vg->hardware->chipRevision;
++ }
++ else
++#endif
++ {
++ chipModel = device->kernels[i]->hardware->identity.chipModel;
++ chipRevision = device->kernels[i]->hardware->identity.chipRevision;
++ }
++
++ seq_printf(m, "gpu : %d\n", i);
++ seq_printf(m, "model : %4x\n", chipModel);
++ seq_printf(m, "revision : %4x\n", chipRevision);
++ seq_printf(m, "\n");
++ }
++ }
++
++ return 0;
++}
++
++int gc_clients_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++
++ gckKERNEL kernel = _GetValidKernel(device);
++
++ gcsDATABASE_PTR database;
++ gctINT i, pid;
++ gctUINT8 name[24];
++
++ seq_printf(m, "%-8s%s\n", "PID", "NAME");
++ seq_printf(m, "------------------------\n");
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(kernel->os, kernel->db->dbMutex, gcvINFINITE));
++
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ for (database = kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ pid = database->processID;
++
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ seq_printf(m, "%-8d%s\n", pid, name);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(kernel->os, kernel->db->dbMutex));
++
++ /* Success. */
++ return 0;
++}
++
++static void
++_CounterAdd(
++ gcsDATABASE_COUNTERS * Dest,
++ gcsDATABASE_COUNTERS * Src
++ )
++{
++ Dest->bytes += Src->bytes;
++ Dest->maxBytes += Src->maxBytes;
++ Dest->totalBytes += Src->totalBytes;
++}
++
++static void
++_CounterPrint(
++ gcsDATABASE_COUNTERS * Counter,
++ gctCONST_STRING Name,
++ struct seq_file* m
++ )
++{
++ seq_printf(m, " %s:\n", Name);
++ seq_printf(m, " Used : %10llu B\n", Counter->bytes);
++}
++
++int gc_meminfo_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ gckKERNEL kernel = _GetValidKernel(device);
++ gckVIDMEM memory;
++ gceSTATUS status;
++ gcsDATABASE_PTR database;
++ gctUINT32 i;
++
++ gctUINT32 free = 0, used = 0, total = 0;
++
++ gcsDATABASE_COUNTERS contiguousCounter = {0, 0, 0};
++ gcsDATABASE_COUNTERS virtualCounter = {0, 0, 0};
++ gcsDATABASE_COUNTERS nonPagedCounter = {0, 0, 0};
++
++ status = gckKERNEL_GetVideoMemoryPool(kernel, gcvPOOL_SYSTEM, &memory);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(memory->os, memory->mutex, gcvINFINITE));
++
++ free = memory->freeBytes;
++ used = memory->bytes - memory->freeBytes;
++ total = memory->bytes;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(memory->os, memory->mutex));
++ }
++
++ seq_printf(m, "VIDEO MEMORY:\n");
++ seq_printf(m, " gcvPOOL_SYSTEM:\n");
++ seq_printf(m, " Free : %10u B\n", free);
++ seq_printf(m, " Used : %10u B\n", used);
++ seq_printf(m, " Total : %10u B\n", total);
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(kernel->os, kernel->db->dbMutex, gcvINFINITE));
++
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i)
++ {
++ for (database = kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ gcsDATABASE_COUNTERS * counter = &database->vidMemPool[gcvPOOL_CONTIGUOUS];
++ _CounterAdd(&contiguousCounter, counter);
++
++ counter = &database->vidMemPool[gcvPOOL_VIRTUAL];
++ _CounterAdd(&virtualCounter, counter);
++
++
++ counter = &database->nonPaged;
++ _CounterAdd(&nonPagedCounter, counter);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(kernel->os, kernel->db->dbMutex));
++
++ _CounterPrint(&contiguousCounter, "gcvPOOL_CONTIGUOUS", m);
++ _CounterPrint(&virtualCounter, "gcvPOOL_VIRTUAL", m);
++
++ seq_printf(m, "\n");
++
++ seq_printf(m, "NON PAGED MEMORY:\n");
++ seq_printf(m, " Used : %10llu B\n", nonPagedCounter.bytes);
++
++ return 0;
++}
++
++static int
++_ShowRecord(
++ IN struct seq_file *file,
++ IN gcsDATABASE_RECORD_PTR record
++ )
++{
++ seq_printf(file, "%4d%8d%16p%16p%16zu\n",
++ record->type,
++ record->kernel->core,
++ record->data,
++ record->physical,
++ record->bytes
++ );
++
++ return 0;
++}
++
++static int
++_ShowRecords(
++ IN struct seq_file *File,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gctUINT i;
++
++ seq_printf(File, "Records:\n");
++
++ seq_printf(File, "%s%8s%16s%16s%16s\n",
++ "Type", "GPU", "Data", "Physical", "Bytes");
++
++ for (i = 0; i < gcmCOUNTOF(Database->list); i++)
++ {
++ gcsDATABASE_RECORD_PTR record = Database->list[i];
++
++ while (record != NULL)
++ {
++ _ShowRecord(File, record);
++ record = record->next;
++ }
++ }
++
++ return 0;
++}
++
++void
++_ShowCounters(
++ struct seq_file *File,
++ gcsDATABASE_PTR Database
++ );
++
++static void
++_ShowProcess(
++ IN struct seq_file *File,
++ IN gcsDATABASE_PTR Database
++ )
++{
++ gctINT pid;
++ gctUINT8 name[24];
++
++ /* Process ID and name */
++ pid = Database->processID;
++ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name)));
++ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name));
++
++ seq_printf(File, "--------------------------------------------------------------------------------\n");
++ seq_printf(File, "Process: %-8d %s\n", pid, name);
++
++ /* Detailed records */
++ _ShowRecords(File, Database);
++
++ seq_printf(File, "Counters:\n");
++
++ _ShowCounters(File, Database);
++}
++
++static void
++_ShowProcesses(
++ IN struct seq_file * file,
++ IN gckKERNEL Kernel
++ )
++{
++ gcsDATABASE_PTR database;
++ gctINT i;
++
++ /* Acquire the database mutex. */
++ gcmkVERIFY_OK(
++ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE));
++
++ /* Idle time since last call */
++ seq_printf(file, "GPU Idle: %llu ns\n", Kernel->db->idleTime);
++ Kernel->db->idleTime = 0;
++
++ /* Walk the databases. */
++ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i)
++ {
++ for (database = Kernel->db->db[i];
++ database != gcvNULL;
++ database = database->next)
++ {
++ _ShowProcess(file, database);
++ }
++ }
++
++ /* Release the database mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex));
++}
++
++static int
++gc_db_show(struct seq_file *m, void *data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ gckKERNEL kernel = _GetValidKernel(device);
++ _ShowProcesses(m, kernel);
++ return 0 ;
++}
++
++static int
++gc_version_show(struct seq_file *m, void *data)
++{
++ seq_printf(m, "%s\n", gcvVERSION_STRING);
++
++ return 0 ;
++}
++
++int gc_idle_show(struct seq_file* m, void* data)
++{
++ gcsINFO_NODE *node = m->private;
++ gckGALDEVICE device = node->device;
++ gckKERNEL kernel = _GetValidKernel(device);
++ gcuDATABASE_INFO info;
++
++ gckKERNEL_QueryProcessDB(kernel, 0, gcvFALSE, gcvDB_IDLE, &info);
++
++ seq_printf(m, "GPU idle time since last query: %llu ns\n", info.time);
++
++ return 0;
++}
++
++static gcsINFO InfoList[] =
++{
++ {"info", gc_info_show},
++ {"clients", gc_clients_show},
++ {"meminfo", gc_meminfo_show},
++ {"idle", gc_idle_show},
++ {"database", gc_db_show},
++ {"version", gc_version_show},
++};
++
++static gceSTATUS
++_DebugfsInit(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gckDEBUGFS_DIR dir = &Device->debugfsDir;
++
++ gcmkONERROR(gckDEBUGFS_DIR_Init(dir, gcvNULL, "gc"));
++
++ gcmkONERROR(gckDEBUGFS_DIR_CreateFiles(dir, InfoList, gcmCOUNTOF(InfoList), Device));
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++static void
++_DebugfsCleanup(
++ IN gckGALDEVICE Device
++ )
++{
++ gckDEBUGFS_DIR dir = &Device->debugfsDir;
++
++ if (Device->debugfsDir.root)
++ {
++ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(dir, InfoList, gcmCOUNTOF(InfoList)));
++
++ gckDEBUGFS_DIR_Deinit(dir);
++ }
++}
++
++
++/******************************************************************************\
++*************************** Memory Allocation Wrappers *************************
++\******************************************************************************/
++
++static gceSTATUS
++_AllocateMemory(
++ IN gckGALDEVICE Device,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER *Logical,
++ OUT gctPHYS_ADDR *Physical,
++ OUT gctUINT32 *PhysAddr
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Bytes=%lu", Device, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++ gcmkVERIFY_ARGUMENT(Physical != NULL);
++ gcmkVERIFY_ARGUMENT(PhysAddr != NULL);
++
++ gcmkONERROR(gckOS_AllocateContiguous(
++ Device->os, gcvFALSE, &Bytes, Physical, Logical
++ ));
++
++ *PhysAddr = ((PLINUX_MDL)*Physical)->dmaHandle;
++
++ /* Success. */
++ gcmkFOOTER_ARG(
++ "*Logical=0x%x *Physical=0x%x *PhysAddr=0x%08x",
++ *Logical, *Physical, *PhysAddr
++ );
++
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++_FreeMemory(
++ IN gckGALDEVICE Device,
++ IN gctPOINTER Logical,
++ IN gctPHYS_ADDR Physical)
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x Logical=0x%x Physical=0x%x",
++ Device, Logical, Physical);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ status = gckOS_FreeContiguous(
++ Device->os, Physical, Logical,
++ ((PLINUX_MDL) Physical)->numPages * PAGE_SIZE
++ );
++
++ gcmkFOOTER();
++ return status;
++}
++
++
++
++/******************************************************************************\
++******************************* Interrupt Handler ******************************
++\******************************************************************************/
++#if gcdMULTI_GPU
++static irqreturn_t isrRoutine3D0(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR],
++ gcvCORE_3D_0_ID,
++ gcvNOTIFY_INTERRUPT,
++ gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Wake up the threadRoutine to process events. */
++ device->dataReady3D[gcvCORE_3D_0_ID] = gcvTRUE;
++ wake_up_interruptible(&device->intrWaitQueue3D[gcvCORE_3D_0_ID]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine3D0(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ /* Sleep until being awaken by the interrupt handler. */
++ wait_event_interruptible(device->intrWaitQueue3D[gcvCORE_3D_0_ID],
++ device->dataReady3D[gcvCORE_3D_0_ID] == gcvTRUE);
++ device->dataReady3D[gcvCORE_3D_0_ID] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR],
++ gcvCORE_3D_0_ID,
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++
++#if gcdMULTI_GPU > 1
++static irqreturn_t isrRoutine3D1(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR],
++ gcvCORE_3D_1_ID,
++ gcvNOTIFY_INTERRUPT,
++ gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ /* Wake up the worker thread to process events. */
++ device->dataReady3D[gcvCORE_3D_1_ID] = gcvTRUE;
++ wake_up_interruptible(&device->intrWaitQueue3D[gcvCORE_3D_1_ID]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine3D1(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ /* Sleep until being awaken by the interrupt handler. */
++ wait_event_interruptible(device->intrWaitQueue3D[gcvCORE_3D_1_ID],
++ device->dataReady3D[gcvCORE_3D_1_ID] == gcvTRUE);
++ device->dataReady3D[gcvCORE_3D_1_ID] = gcvFALSE;
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR],
++ gcvCORE_3D_1_ID,
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++#endif
++#elif gcdMULTI_GPU_AFFINITY
++static irqreturn_t isrRoutine3D0(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ up(&device->semas[gcvCORE_MAJOR]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine3D0(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_MAJOR]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR],
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutine3D1(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_OCL], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ up(&device->semas[gcvCORE_OCL]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine3D1(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_OCL]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_OCL],
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++#else
++static irqreturn_t isrRoutine(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvTRUE);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ up(&device->semas[gcvCORE_MAJOR]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_MAJOR]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++
++ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR],
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++#endif
++
++static irqreturn_t isrRoutine2D(int irq, void *ctxt)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Call kernel interrupt notification. */
++ status = gckKERNEL_Notify(device->kernels[gcvCORE_2D],
++#if gcdMULTI_GPU
++ 0,
++#endif
++ gcvNOTIFY_INTERRUPT,
++ gcvTRUE);
++ if (gcmIS_SUCCESS(status))
++ {
++ up(&device->semas[gcvCORE_2D]);
++
++ return IRQ_HANDLED;
++ }
++
++ return IRQ_NONE;
++}
++
++static int threadRoutine2D(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_2D]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++ gckKERNEL_Notify(device->kernels[gcvCORE_2D],
++#if gcdMULTI_GPU
++ 0,
++#endif
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++
++static irqreturn_t isrRoutineVG(int irq, void *ctxt)
++{
++#if gcdENABLE_VG
++ gceSTATUS status;
++ gckGALDEVICE device;
++
++ device = (gckGALDEVICE) ctxt;
++
++ /* Serve the interrupt. */
++ status = gckVGINTERRUPT_Enque(device->kernels[gcvCORE_VG]->vg->interrupt);
++
++ /* Determine the return value. */
++ return (status == gcvSTATUS_NOT_OUR_INTERRUPT)
++ ? IRQ_RETVAL(0)
++ : IRQ_RETVAL(1);
++#else
++ return IRQ_NONE;
++#endif
++}
++
++static int threadRoutineVG(void *ctxt)
++{
++ gckGALDEVICE device = (gckGALDEVICE) ctxt;
++
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "Starting isr Thread with extension=%p",
++ device);
++
++ for (;;)
++ {
++ static int down;
++
++ down = down_interruptible(&device->semas[gcvCORE_VG]);
++ if (down); /*To make gcc 4.6 happye*/
++
++ if (device->killThread == gcvTRUE)
++ {
++ /* The daemon exits. */
++ while (!kthread_should_stop())
++ {
++ gckOS_Delay(device->os, 1);
++ }
++
++ return 0;
++ }
++ gckKERNEL_Notify(device->kernels[gcvCORE_VG],
++#if gcdMULTI_GPU
++ 0,
++#endif
++ gcvNOTIFY_INTERRUPT,
++ gcvFALSE);
++ }
++}
++
++/******************************************************************************\
++******************************* gckGALDEVICE Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Construct
++**
++** Constructor.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gckGALDEVICE * Device
++** Pointer to a variable receiving the gckGALDEVICE object pointer on
++** success.
++*/
++gceSTATUS
++gckGALDEVICE_Construct(
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ IN gctINT IrqLine3D0,
++ IN gctUINT32 RegisterMemBase3D0,
++ IN gctSIZE_T RegisterMemSize3D0,
++ IN gctINT IrqLine3D1,
++ IN gctUINT32 RegisterMemBase3D1,
++ IN gctSIZE_T RegisterMemSize3D1,
++#else
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++#endif
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ IN gcsDEVICE_CONSTRUCT_ARGS * Args,
++ OUT gckGALDEVICE *Device
++ )
++{
++ gctUINT32 internalBaseAddress = 0, internalAlignment = 0;
++ gctUINT32 externalBaseAddress = 0, externalAlignment = 0;
++ gctUINT32 horizontalTileSize, verticalTileSize;
++ struct resource* mem_region;
++ gctUINT32 physAddr;
++ gctUINT32 physical;
++ gckGALDEVICE device;
++ gceSTATUS status;
++ gctINT32 i;
++#if gcdMULTI_GPU
++ gctINT32 j;
++#endif
++ gceHARDWARE_TYPE type;
++ gckDB sharedDB = gcvNULL;
++ gckKERNEL kernel = gcvNULL;
++
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ gcmkHEADER_ARG("IrqLine3D0=%d RegisterMemBase3D0=0x%08x RegisterMemSize3D0=%u "
++ "IrqLine2D=%d RegisterMemBase2D=0x%08x RegisterMemSize2D=%u "
++ "IrqLineVG=%d RegisterMemBaseVG=0x%08x RegisterMemSizeVG=%u "
++ "ContiguousBase=0x%08x ContiguousSize=%lu BankSize=%lu "
++ "FastClear=%d Compression=%d PhysBaseAddr=0x%x PhysSize=%d Signal=%d",
++ IrqLine3D0, RegisterMemBase3D0, RegisterMemSize3D0,
++ IrqLine2D, RegisterMemBase2D, RegisterMemSize2D,
++ IrqLineVG, RegisterMemBaseVG, RegisterMemSizeVG,
++ ContiguousBase, ContiguousSize, BankSize, FastClear, Compression,
++ PhysBaseAddr, PhysSize, Signal);
++#else
++ gcmkHEADER_ARG("IrqLine=%d RegisterMemBase=0x%08x RegisterMemSize=%u "
++ "IrqLine2D=%d RegisterMemBase2D=0x%08x RegisterMemSize2D=%u "
++ "IrqLineVG=%d RegisterMemBaseVG=0x%08x RegisterMemSizeVG=%u "
++ "ContiguousBase=0x%08x ContiguousSize=%lu BankSize=%lu "
++ "FastClear=%d Compression=%d PhysBaseAddr=0x%x PhysSize=%d Signal=%d",
++ IrqLine, RegisterMemBase, RegisterMemSize,
++ IrqLine2D, RegisterMemBase2D, RegisterMemSize2D,
++ IrqLineVG, RegisterMemBaseVG, RegisterMemSizeVG,
++ ContiguousBase, ContiguousSize, BankSize, FastClear, Compression,
++ PhysBaseAddr, PhysSize, Signal);
++#endif
++
++#if gcdDISABLE_CORES_2D3D
++ IrqLine = -1;
++ IrqLine2D = -1;
++#endif
++
++ /* Allocate device structure. */
++ device = kmalloc(sizeof(struct _gckGALDEVICE), GFP_KERNEL | __GFP_NOWARN);
++
++ if (!device)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ memset(device, 0, sizeof(struct _gckGALDEVICE));
++
++ device->dbgNode = gcvNULL;
++
++ device->platform = Args->platform;
++
++ gcmkONERROR(_DebugfsInit(device));
++
++ if (gckDEBUGFS_CreateNode(
++ device, LogFileSize, device->debugfsDir.root ,DEBUG_FILE, &(device->dbgNode)))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the debug file system %s/%s \n",
++ __FUNCTION__, __LINE__,
++ PARENT_FILE, DEBUG_FILE
++ );
++ }
++ else if (LogFileSize)
++ {
++ gckDEBUGFS_SetCurrentNode(device->dbgNode);
++ }
++
++#if gcdMULTI_GPU
++ if (IrqLine3D0 != -1)
++ {
++ device->requestedRegisterMemBase3D[gcvCORE_3D_0_ID] = RegisterMemBase3D0;
++ device->requestedRegisterMemSize3D[gcvCORE_3D_0_ID] = RegisterMemSize3D0;
++ }
++
++ if (IrqLine3D1 != -1)
++ {
++ device->requestedRegisterMemBase3D[gcvCORE_3D_1_ID] = RegisterMemBase3D1;
++ device->requestedRegisterMemSize3D[gcvCORE_3D_1_ID] = RegisterMemSize3D1;
++ }
++#elif gcdMULTI_GPU_AFFINITY
++ if (IrqLine3D0 != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_MAJOR] = RegisterMemBase3D0;
++ device->requestedRegisterMemSizes[gcvCORE_MAJOR] = RegisterMemSize3D0;
++ }
++
++ if (IrqLine3D1 != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_OCL] = RegisterMemBase3D1;
++ device->requestedRegisterMemSizes[gcvCORE_OCL] = RegisterMemSize3D1;
++ }
++#else
++ if (IrqLine != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_MAJOR] = RegisterMemBase;
++ device->requestedRegisterMemSizes[gcvCORE_MAJOR] = RegisterMemSize;
++ }
++#endif
++
++ if (IrqLine2D != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_2D] = RegisterMemBase2D;
++ device->requestedRegisterMemSizes[gcvCORE_2D] = RegisterMemSize2D;
++ }
++
++ if (IrqLineVG != -1)
++ {
++ device->requestedRegisterMemBases[gcvCORE_VG] = RegisterMemBaseVG;
++ device->requestedRegisterMemSizes[gcvCORE_VG] = RegisterMemSizeVG;
++ }
++
++ device->requestedContiguousBase = 0;
++ device->requestedContiguousSize = 0;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdMULTI_GPU
++ if (i == gcvCORE_MAJOR)
++ {
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ physical = device->requestedRegisterMemBase3D[j];
++
++ /* Set up register memory region. */
++ if (physical != 0)
++ {
++ mem_region = request_mem_region(physical,
++ device->requestedRegisterMemSize3D[j],
++ "galcore register region");
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %lu bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSize3D[j]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->registerBase3D[j] = (gctPOINTER) ioremap_nocache(
++ physical, device->requestedRegisterMemSize3D[j]);
++
++ if (device->registerBase3D[j] == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unable to map %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSize3D[j]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ physical += device->requestedRegisterMemSize3D[j];
++ }
++ else
++ {
++ device->registerBase3D[j] = gcvNULL;
++ }
++ }
++ }
++ else
++#endif
++ {
++ physical = device->requestedRegisterMemBases[i];
++
++ /* Set up register memory region. */
++ if (physical != 0)
++ {
++ mem_region = request_mem_region(physical,
++ device->requestedRegisterMemSizes[i],
++ "galcore register region");
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %lu bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->registerBases[i] = (gctPOINTER) ioremap_nocache(
++ physical, device->requestedRegisterMemSizes[i]);
++
++ if (device->registerBases[i] == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unable to map %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ physical, device->requestedRegisterMemSizes[i]
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ physical += device->requestedRegisterMemSizes[i];
++ }
++ }
++ }
++
++ /* Set the base address */
++ device->baseAddress = device->physBase = PhysBaseAddr;
++ device->physSize = PhysSize;
++ device->mmu = Args->mmu;
++
++ /* Construct the gckOS object. */
++ gcmkONERROR(gckOS_Construct(device, &device->os));
++
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ if (IrqLine3D0 != -1)
++#else
++ if (IrqLine != -1)
++#endif
++ {
++ /* Construct the gckKERNEL object. */
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_MAJOR, device,
++ gcvNULL, &device->kernels[gcvCORE_MAJOR]));
++
++ sharedDB = device->kernels[gcvCORE_MAJOR]->db;
++
++ /* Initialize core mapping */
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_MAJOR;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_MAJOR]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Setup_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Release_ISR,
++ device
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(
++ device->kernels[gcvCORE_MAJOR]->hardware, FastClear, Compression
++ ));
++
++ if(PowerManagement != -1)
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_MAJOR]->hardware, PowerManagement
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvTRUE
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_MAJOR]->hardware, gcvTRUE
++ ));
++ }
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gcmkONERROR(gckHARDWARE_SetMinFscaleValue(
++ device->kernels[gcvCORE_MAJOR]->hardware, Args->gpu3DMinClock
++ ));
++#endif
++
++ gcmkONERROR(gckHARDWARE_SetGpuProfiler(
++ device->kernels[gcvCORE_MAJOR]->hardware, GpuProfiler
++ ));
++
++ gcmkVERIFY_OK(gckKERNEL_SetRecovery(
++ device->kernels[gcvCORE_MAJOR], Args->recovery, Args->stuckDump
++ ));
++
++#if COMMAND_PROCESSOR_VERSION == 1
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_MAJOR]->command));
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_MAJOR] = gcvNULL;
++ }
++
++#if gcdMULTI_GPU_AFFINITY
++ if (IrqLine3D1 != -1)
++ {
++ /* Construct the gckKERNEL object. */
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_OCL, device,
++ gcvNULL, &device->kernels[gcvCORE_OCL]));
++
++ if (sharedDB == gcvNULL) sharedDB = device->kernels[gcvCORE_OCL]->db;
++
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL)
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_OCL;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_OCL] = gcvCORE_OCL;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_OCL]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Setup_ISR,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Release_ISR,
++ device
++ ));
++
++ gcmkONERROR(gckHARDWARE_SetFastClear(
++ device->kernels[gcvCORE_OCL]->hardware, FastClear, Compression
++ ));
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gcmkONERROR(gckHARDWARE_SetMinFscaleValue(
++ device->kernels[gcvCORE_OCL]->hardware, Args->gpu3DMinClock
++ ));
++#endif
++ if(PowerManagement != -1)
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_OCL]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_OCL]->hardware, PowerManagement
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_OCL]->hardware, gcvTRUE
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_OCL]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_OCL]->hardware, gcvTRUE
++ ));
++ }
++
++#if COMMAND_PROCESSOR_VERSION == 1
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_OCL]->command));
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_OCL] = gcvNULL;
++ }
++#endif
++
++ if (IrqLine2D != -1)
++ {
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_2D, device,
++ sharedDB, &device->kernels[gcvCORE_2D]));
++
++ if (sharedDB == gcvNULL) sharedDB = device->kernels[gcvCORE_2D]->db;
++
++ /* Verify the hardware type */
++ gcmkONERROR(gckHARDWARE_GetType(device->kernels[gcvCORE_2D]->hardware, &type));
++
++ if (type != gcvHARDWARE_2D)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Unexpected hardware type: %d\n",
++ __FUNCTION__, __LINE__,
++ type
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL
++#if gcdMULTI_GPU_AFFINITY
++ && device->kernels[gcvCORE_OCL] == gcvNULL
++#endif
++ )
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_2D;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_2D] = gcvCORE_2D;
++ }
++
++ /* Setup the ISR manager. */
++ gcmkONERROR(gckHARDWARE_SetIsrManager(
++ device->kernels[gcvCORE_2D]->hardware,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Setup_ISR_2D,
++ (gctISRMANAGERFUNC) gckGALDEVICE_Release_ISR_2D,
++ device
++ ));
++
++ if(PowerManagement != -1)
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_2D]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_2D]->hardware, PowerManagement
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_2D]->hardware, gcvTRUE
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckHARDWARE_SetPowerManagementLock(
++ device->kernels[gcvCORE_2D]->hardware, gcvFALSE
++ ));
++ gcmkONERROR(gckHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_2D]->hardware, gcvTRUE
++ ));
++ }
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ gcmkONERROR(gckHARDWARE_SetMinFscaleValue(
++ device->kernels[gcvCORE_2D]->hardware, 1
++ ));
++#endif
++
++ gcmkVERIFY_OK(gckKERNEL_SetRecovery(
++ device->kernels[gcvCORE_2D], Args->recovery, Args->stuckDump
++ ));
++
++#if COMMAND_PROCESSOR_VERSION == 1
++ /* Start the command queue. */
++ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_2D]->command));
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_2D] = gcvNULL;
++ }
++
++ if (IrqLineVG != -1)
++ {
++#if gcdENABLE_VG
++ gcmkONERROR(gckKERNEL_Construct(
++ device->os, gcvCORE_VG, device,
++ sharedDB, &device->kernels[gcvCORE_VG]));
++ /* Initialize core mapping */
++ if (device->kernels[gcvCORE_MAJOR] == gcvNULL
++ && device->kernels[gcvCORE_2D] == gcvNULL
++#if gcdMULTI_GPU_AFFINITY
++ && device->kernels[gcvCORE_OCL] == gcvNULL
++#endif
++ )
++ {
++ for (i = 0; i < 8; i++)
++ {
++ device->coreMapping[i] = gcvCORE_VG;
++ }
++ }
++ else
++ {
++ device->coreMapping[gcvHARDWARE_VG] = gcvCORE_VG;
++ }
++
++ if(PowerManagement != -1)
++ {
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_VG]->vg->hardware,
++ PowerManagement
++ ));
++ }
++ else
++ {
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagement(
++ device->kernels[gcvCORE_VG]->vg->hardware,
++ gcvTRUE
++ ));
++ }
++
++
++#endif
++ }
++ else
++ {
++ device->kernels[gcvCORE_VG] = gcvNULL;
++ }
++
++ /* Initialize the ISR. */
++#if gcdMULTI_GPU
++ device->irqLine3D[gcvCORE_3D_0_ID] = IrqLine3D0;
++#if gcdMULTI_GPU > 1
++ device->irqLine3D[gcvCORE_3D_1_ID] = IrqLine3D1;
++#endif
++#elif gcdMULTI_GPU_AFFINITY
++ device->irqLines[gcvCORE_MAJOR] = IrqLine3D0;
++ device->irqLines[gcvCORE_OCL] = IrqLine3D1;
++#else
++ device->irqLines[gcvCORE_MAJOR] = IrqLine;
++#endif
++ device->irqLines[gcvCORE_2D] = IrqLine2D;
++ device->irqLines[gcvCORE_VG] = IrqLineVG;
++
++ /* Initialize the kernel thread semaphores. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdMULTI_GPU
++ if (i == gcvCORE_MAJOR)
++ {
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ if (device->irqLine3D[j] != -1) init_waitqueue_head(&device->intrWaitQueue3D[j]);
++ }
++ }
++ else
++#endif
++ {
++ if (device->irqLines[i] != -1) sema_init(&device->semas[i], 0);
++ }
++ }
++
++ device->signal = Signal;
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL) break;
++ }
++
++ if (i == gcdMAX_GPU_COUNT)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckVGHARDWARE_QuerySystemMemory(
++ device->kernels[i]->vg->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++ /* query the amount of video memory */
++ gcmkONERROR(gckVGHARDWARE_QueryMemory(
++ device->kernels[i]->vg->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++ else
++#endif
++ {
++ /* Query the ceiling of the system memory. */
++ gcmkONERROR(gckHARDWARE_QuerySystemMemory(
++ device->kernels[i]->hardware,
++ &device->systemMemorySize,
++ &device->systemMemoryBaseAddress
++ ));
++
++ /* query the amount of video memory */
++ gcmkONERROR(gckHARDWARE_QueryMemory(
++ device->kernels[i]->hardware,
++ &device->internalSize, &internalBaseAddress, &internalAlignment,
++ &device->externalSize, &externalBaseAddress, &externalAlignment,
++ &horizontalTileSize, &verticalTileSize
++ ));
++ }
++
++
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdMULTI_GPU
++ if (i == gcvCORE_MAJOR)
++ {
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ if (device->irqLine3D[j] != -1)
++ {
++ kernel = device->kernels[i];
++ break;
++ }
++ }
++ }
++ else
++#endif
++ {
++ if (device->irqLines[i] != -1)
++ {
++ kernel = device->kernels[i];
++ break;
++ }
++ }
++ }
++
++ /* Set up the internal memory region. */
++ if (device->internalSize > 0)
++ {
++ status = gckVIDMEM_Construct(
++ device->os,
++ internalBaseAddress, device->internalSize, internalAlignment,
++ 0, &device->internalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->internalSize = 0;
++ }
++ else
++ {
++ /* Map internal memory. */
++ device->internalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->internalSize);
++
++ if (device->internalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->internalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->internalPhysicalName = gcmPTR_TO_NAME(device->internalPhysical);
++ physical += device->internalSize;
++ }
++ }
++
++ if (device->externalSize > 0)
++ {
++ /* create the external memory heap */
++ status = gckVIDMEM_Construct(
++ device->os,
++ externalBaseAddress, device->externalSize, externalAlignment,
++ 0, &device->externalVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable internal heap. */
++ device->externalSize = 0;
++ }
++ else
++ {
++ /* Map external memory. */
++ device->externalLogical
++ = (gctPOINTER) ioremap_nocache(physical, device->externalSize);
++
++ if (device->externalLogical == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ device->externalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical;
++ device->externalPhysicalName = gcmPTR_TO_NAME(device->externalPhysical);
++ physical += device->externalSize;
++ }
++ }
++
++ /* set up the contiguous memory */
++ device->contiguousSize = ContiguousSize;
++
++ if (ContiguousSize > 0)
++ {
++ if (ContiguousBase == 0)
++ {
++ while (device->contiguousSize > 0)
++ {
++ /* Allocate contiguous memory. */
++ status = _AllocateMemory(
++ device,
++ device->contiguousSize,
++ &device->contiguousBase,
++ &device->contiguousPhysical,
++ &physAddr
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ device->contiguousPhysicalName = gcmPTR_TO_NAME(device->contiguousPhysical);
++ status = gckVIDMEM_Construct(
++ device->os,
++ physAddr | device->systemMemoryBaseAddress,
++ device->contiguousSize,
++ 64,
++ BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++
++ gcmkONERROR(_FreeMemory(
++ device,
++ device->contiguousBase,
++ device->contiguousPhysical
++ ));
++
++ gcmRELEASE_NAME(device->contiguousPhysicalName);
++ device->contiguousBase = gcvNULL;
++ device->contiguousPhysical = gcvNULL;
++ }
++
++ if (device->contiguousSize <= (4 << 20))
++ {
++ device->contiguousSize = 0;
++ }
++ else
++ {
++ device->contiguousSize -= (4 << 20);
++ }
++ }
++ }
++ else
++ {
++ /* Create the contiguous memory heap. */
++ status = gckVIDMEM_Construct(
++ device->os,
++ ContiguousBase | device->systemMemoryBaseAddress,
++ ContiguousSize,
++ 64, BankSize,
++ &device->contiguousVidMem
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error, disable contiguous memory pool. */
++ device->contiguousVidMem = gcvNULL;
++ device->contiguousSize = 0;
++ }
++ else
++ {
++ if (Args->contiguousRequested == gcvFALSE)
++ {
++ mem_region = request_mem_region(
++ ContiguousBase, ContiguousSize, "galcore managed memory"
++ );
++
++ if (mem_region == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to claim %ld bytes @ 0x%08X\n",
++ __FUNCTION__, __LINE__,
++ ContiguousSize, ContiguousBase
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++
++ device->requestedContiguousBase = ContiguousBase;
++ device->requestedContiguousSize = ContiguousSize;
++ device->contiguousRequested = Args->contiguousRequested;
++
++ device->contiguousPhysical = gcvNULL;
++ device->contiguousPhysicalName = 0;
++ device->contiguousSize = ContiguousSize;
++ device->contiguousMapped = gcvTRUE;
++ }
++ }
++ }
++
++ /* Return pointer to the device. */
++ *Device = device;
++
++ gcmkFOOTER_ARG("*Device=0x%x", * Device);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Roll back. */
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Destroy
++**
++** Class destructor.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Destroy(
++ gckGALDEVICE Device)
++{
++ gctINT i;
++#if gcdMULTI_GPU
++ gctINT j;
++#endif
++ gckKERNEL kernel = gcvNULL;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ if (Device != gcvNULL)
++ {
++ /* Grab the first availiable kernel */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdMULTI_GPU
++ if (i == gcvCORE_MAJOR)
++ {
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ if (Device->irqLine3D[j] != -1)
++ {
++ kernel = Device->kernels[i];
++ break;
++ }
++ }
++ }
++ else
++#endif
++ {
++ if (Device->irqLines[i] != -1)
++ {
++ kernel = Device->kernels[i];
++ break;
++ }
++ }
++ }
++
++ if (Device->internalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->internalPhysicalName);
++ Device->internalPhysicalName = 0;
++ }
++ if (Device->externalPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->externalPhysicalName);
++ Device->externalPhysicalName = 0;
++ }
++ if (Device->contiguousPhysicalName != 0)
++ {
++ gcmRELEASE_NAME(Device->contiguousPhysicalName);
++ Device->contiguousPhysicalName = 0;
++ }
++
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (Device->kernels[i] != gcvNULL)
++ {
++ /* Destroy the gckKERNEL object. */
++ gcmkVERIFY_OK(gckKERNEL_Destroy(Device->kernels[i]));
++ Device->kernels[i] = gcvNULL;
++ }
++ }
++
++ if (Device->internalLogical != gcvNULL)
++ {
++ /* Unmap the internal memory. */
++ iounmap(Device->internalLogical);
++ Device->internalLogical = gcvNULL;
++ }
++
++ if (Device->internalVidMem != gcvNULL)
++ {
++ /* Destroy the internal heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->internalVidMem));
++ Device->internalVidMem = gcvNULL;
++ }
++
++ if (Device->externalLogical != gcvNULL)
++ {
++ /* Unmap the external memory. */
++ iounmap(Device->externalLogical);
++ Device->externalLogical = gcvNULL;
++ }
++
++ if (Device->externalVidMem != gcvNULL)
++ {
++ /* destroy the external heap */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->externalVidMem));
++ Device->externalVidMem = gcvNULL;
++ }
++
++ if (Device->contiguousBase != gcvNULL)
++ {
++ if (Device->contiguousMapped == gcvFALSE)
++ {
++ gcmkVERIFY_OK(_FreeMemory(
++ Device,
++ Device->contiguousBase,
++ Device->contiguousPhysical
++ ));
++ }
++
++ Device->contiguousBase = gcvNULL;
++ Device->contiguousPhysical = gcvNULL;
++ }
++
++ if (Device->requestedContiguousBase != 0
++ && Device->contiguousRequested == gcvFALSE
++ )
++ {
++ release_mem_region(Device->requestedContiguousBase, Device->requestedContiguousSize);
++ Device->requestedContiguousBase = 0;
++ Device->requestedContiguousSize = 0;
++ }
++
++ if (Device->contiguousVidMem != gcvNULL)
++ {
++ /* Destroy the contiguous heap. */
++ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->contiguousVidMem));
++ Device->contiguousVidMem = gcvNULL;
++ }
++
++ if (Device->dbgNode)
++ {
++ gckDEBUGFS_FreeNode(Device->dbgNode);
++
++ if(Device->dbgNode != gcvNULL)
++ {
++ kfree(Device->dbgNode);
++ Device->dbgNode = gcvNULL;
++ }
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdMULTI_GPU
++ if (i == gcvCORE_MAJOR)
++ {
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ if (Device->registerBase3D[j] != gcvNULL)
++ {
++ /* Unmap register memory. */
++ iounmap(Device->registerBase3D[j]);
++ if (Device->requestedRegisterMemBase3D[j] != 0)
++ {
++ release_mem_region(Device->requestedRegisterMemBase3D[j],
++ Device->requestedRegisterMemSize3D[j]);
++ }
++
++ Device->registerBase3D[j] = gcvNULL;
++ Device->requestedRegisterMemBase3D[j] = 0;
++ Device->requestedRegisterMemSize3D[j] = 0;
++ }
++ }
++ }
++ else
++#endif
++ {
++ if (Device->registerBases[i] != gcvNULL)
++ {
++ /* Unmap register memory. */
++ iounmap(Device->registerBases[i]);
++ if (Device->requestedRegisterMemBases[i] != 0)
++ {
++ release_mem_region(Device->requestedRegisterMemBases[i],
++ Device->requestedRegisterMemSizes[i]);
++ }
++
++ Device->registerBases[i] = gcvNULL;
++ Device->requestedRegisterMemBases[i] = 0;
++ Device->requestedRegisterMemSizes[i] = 0;
++ }
++ }
++ }
++
++ /* Destroy the gckOS object. */
++ if (Device->os != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_Destroy(Device->os));
++ Device->os = gcvNULL;
++ }
++
++ _DebugfsCleanup(Device);
++
++ /* Free the device. */
++ kfree(Device);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Setup_ISR
++**
++** Start the ISR routine.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Setup successfully.
++** gcvSTATUS_GENERIC_IO
++** Setup failed.
++*/
++gceSTATUS
++gckGALDEVICE_Setup_ISR(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++ gctINT ret = 0;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[gcvCORE_MAJOR] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Hook up the isr based on the irq line. */
++#ifdef FLAREON
++ gc500_handle.dev_name = "galcore interrupt service";
++ gc500_handle.dev_id = Device;
++ gc500_handle.handler = isrRoutine;
++ gc500_handle.intr_gen = GPIO_INTR_LEVEL_TRIGGER;
++ gc500_handle.intr_trig = GPIO_TRIG_HIGH_LEVEL;
++
++ ret = dove_gpio_request(
++ DOVE_GPIO0_7, &gc500_handle
++ );
++#else
++#if gcdMULTI_GPU
++ ret = request_irq(
++ Device->irqLine3D[gcvCORE_3D_0_ID], isrRoutine3D0, IRQF_DISABLED,
++ "galcore_3d_0", Device
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLine3D[gcvCORE_3D_0_ID], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Mark ISR as initialized. */
++ Device->isrInitialized3D[gcvCORE_3D_0_ID] = gcvTRUE;
++
++#if gcdMULTI_GPU > 1
++ ret = request_irq(
++ Device->irqLine3D[gcvCORE_3D_1_ID], isrRoutine3D1, IRQF_DISABLED,
++ "galcore_3d_1", Device
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLine3D[gcvCORE_3D_1_ID], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Mark ISR as initialized. */
++ Device->isrInitialized3D[gcvCORE_3D_1_ID] = gcvTRUE;
++#endif
++#elif gcdMULTI_GPU_AFFINITY
++ ret = request_irq(
++ Device->irqLines[gcvCORE_MAJOR], isrRoutine3D0, IRQF_DISABLED,
++ "galcore_3d_0", Device
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[gcvCORE_MAJOR], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[gcvCORE_MAJOR] = gcvTRUE;
++
++ ret = request_irq(
++ Device->irqLines[gcvCORE_OCL], isrRoutine3D1, IRQF_DISABLED,
++ "galcore_3d_1", Device
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[gcvCORE_OCL], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[gcvCORE_OCL] = gcvTRUE;
++#else
++ ret = request_irq(
++ Device->irqLines[gcvCORE_MAJOR], isrRoutine, IRQF_DISABLED,
++ "galcore interrupt service", Device
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[gcvCORE_MAJOR], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[gcvCORE_MAJOR] = gcvTRUE;
++#endif
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckGALDEVICE_Setup_ISR_2D(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++ gctINT ret;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[gcvCORE_2D] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Hook up the isr based on the irq line. */
++#ifdef FLAREON
++ gc500_handle.dev_name = "galcore interrupt service";
++ gc500_handle.dev_id = Device;
++ gc500_handle.handler = isrRoutine2D;
++ gc500_handle.intr_gen = GPIO_INTR_LEVEL_TRIGGER;
++ gc500_handle.intr_trig = GPIO_TRIG_HIGH_LEVEL;
++
++ ret = dove_gpio_request(
++ DOVE_GPIO0_7, &gc500_handle
++ );
++#else
++ ret = request_irq(
++ Device->irqLines[gcvCORE_2D], isrRoutine2D, IRQF_DISABLED,
++ "galcore interrupt service for 2D", Device
++ );
++#endif
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[gcvCORE_2D], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[gcvCORE_2D] = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckGALDEVICE_Setup_ISR_VG(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++ gctINT ret;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->irqLines[gcvCORE_VG] < 0)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Hook up the isr based on the irq line. */
++#ifdef FLAREON
++ gc500_handle.dev_name = "galcore interrupt service";
++ gc500_handle.dev_id = Device;
++ gc500_handle.handler = isrRoutineVG;
++ gc500_handle.intr_gen = GPIO_INTR_LEVEL_TRIGGER;
++ gc500_handle.intr_trig = GPIO_TRIG_HIGH_LEVEL;
++
++ ret = dove_gpio_request(
++ DOVE_GPIO0_7, &gc500_handle
++ );
++#else
++ ret = request_irq(
++ Device->irqLines[gcvCORE_VG], isrRoutineVG, IRQF_DISABLED,
++ "galcore interrupt service for 2D", Device
++ );
++#endif
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not register irq line %d (error=%d)\n",
++ __FUNCTION__, __LINE__,
++ Device->irqLines[gcvCORE_VG], ret
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ /* Mark ISR as initialized. */
++ Device->isrInitializeds[gcvCORE_VG] = gcvTRUE;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Release_ISR
++**
++** Release the irq line.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Release_ISR(
++ IN gckGALDEVICE Device
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++#if gcdMULTI_GPU
++ /* release the irq */
++ if (Device->isrInitialized3D[gcvCORE_3D_0_ID])
++ {
++ free_irq(Device->irqLine3D[gcvCORE_3D_0_ID], Device);
++ Device->isrInitialized3D[gcvCORE_3D_0_ID] = gcvFALSE;
++ }
++#if gcdMULTI_GPU > 1
++ /* release the irq */
++ if (Device->isrInitialized3D[gcvCORE_3D_1_ID])
++ {
++ free_irq(Device->irqLine3D[gcvCORE_3D_1_ID], Device);
++ Device->isrInitialized3D[gcvCORE_3D_1_ID] = gcvFALSE;
++ }
++#endif
++#else
++ /* release the irq */
++ if (Device->isrInitializeds[gcvCORE_MAJOR])
++ {
++#ifdef FLAREON
++ dove_gpio_free(DOVE_GPIO0_7, "galcore interrupt service");
++#else
++ free_irq(Device->irqLines[gcvCORE_MAJOR], Device);
++#endif
++ Device->isrInitializeds[gcvCORE_MAJOR] = gcvFALSE;
++ }
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckGALDEVICE_Release_ISR_2D(
++ IN gckGALDEVICE Device
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* release the irq */
++ if (Device->isrInitializeds[gcvCORE_2D])
++ {
++#ifdef FLAREON
++ dove_gpio_free(DOVE_GPIO0_7, "galcore interrupt service");
++#else
++ free_irq(Device->irqLines[gcvCORE_2D], Device);
++#endif
++
++ Device->isrInitializeds[gcvCORE_2D] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckGALDEVICE_Release_ISR_VG(
++ IN gckGALDEVICE Device
++ )
++{
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ /* release the irq */
++ if (Device->isrInitializeds[gcvCORE_VG])
++ {
++#ifdef FLAREON
++ dove_gpio_free(DOVE_GPIO0_7, "galcore interrupt service");
++#else
++ free_irq(Device->irqLines[gcvCORE_VG], Device);
++#endif
++
++ Device->isrInitializeds[gcvCORE_VG] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start_Threads
++**
++** Start the daemon threads.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++** gcvSTATUS_GENERIC_IO
++** Start failed.
++*/
++gceSTATUS
++gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++ struct task_struct * task;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++#if gcdMULTI_GPU
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine3D0, Device, "galcore_3d_0");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxt3D[gcvCORE_3D_0_ID] = task;
++ Device->threadInitialized3D[gcvCORE_3D_0_ID] = gcvTRUE;
++
++#if gcdMULTI_GPU > 1
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine3D1, Device, "galcore_3d_1");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxt3D[gcvCORE_3D_1_ID] = task;
++ Device->threadInitialized3D[gcvCORE_3D_1_ID] = gcvTRUE;
++#endif
++ }
++#elif gcdMULTI_GPU_AFFINITY
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine3D0, Device, "galcore_3d_0");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_MAJOR] = task;
++ Device->threadInitializeds[gcvCORE_MAJOR] = gcvTRUE;
++ }
++
++ if (Device->kernels[gcvCORE_OCL] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine3D1, Device, "galcore_3d_1");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_OCL] = task;
++ Device->threadInitializeds[gcvCORE_OCL] = gcvTRUE;
++ }
++#else
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine, Device, "galcore daemon thread");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_MAJOR] = task;
++ Device->threadInitializeds[gcvCORE_MAJOR] = gcvTRUE;
++ }
++#endif
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutine2D, Device, "galcore daemon thread for 2D");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_2D] = task;
++ Device->threadInitializeds[gcvCORE_2D] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_2D] = gcvFALSE;
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Start the kernel thread. */
++ task = kthread_run(threadRoutineVG, Device, "galcore daemon thread for VG");
++
++ if (IS_ERR(task))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not start the kernel thread.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ Device->threadCtxts[gcvCORE_VG] = task;
++ Device->threadInitializeds[gcvCORE_VG] = gcvTRUE;
++ }
++ else
++ {
++ Device->threadInitializeds[gcvCORE_VG] = gcvFALSE;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop_Threads
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ )
++{
++ gctINT i;
++#if gcdMULTI_GPU
++ gctINT j;
++#endif
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++#if gcdMULTI_GPU
++ if (i == gcvCORE_MAJOR)
++ {
++ for (j = 0; j < gcdMULTI_GPU; j++)
++ {
++ /* Stop the kernel threads. */
++ if (Device->threadInitialized3D[j])
++ {
++ Device->killThread = gcvTRUE;
++ Device->dataReady3D[j] = gcvTRUE;
++ wake_up_interruptible(&Device->intrWaitQueue3D[j]);
++
++ kthread_stop(Device->threadCtxt3D[j]);
++ Device->threadCtxt3D[j] = gcvNULL;
++ Device->threadInitialized3D[j] = gcvFALSE;
++ }
++ }
++ }
++ else
++#endif
++ {
++ /* Stop the kernel threads. */
++ if (Device->threadInitializeds[i])
++ {
++ Device->killThread = gcvTRUE;
++ up(&Device->semas[i]);
++
++ kthread_stop(Device->threadCtxts[i]);
++ Device->threadCtxts[i] = gcvNULL;
++ Device->threadInitializeds[i] = gcvFALSE;
++ }
++ }
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Start
++**
++** Start the gal device, including the following actions: setup the isr routine
++** and start the daemoni thread.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** gcvSTATUS_OK
++** Start successfully.
++*/
++gceSTATUS
++gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ /* Start the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Start_Threads(Device));
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR_2D(Device));
++
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Setup_ISR_VG(Device));
++
++#if gcdENABLE_VG
++ /* Switch to SUSPEND power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF_BROADCAST
++ ));
++#endif
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckGALDEVICE_Stop
++**
++** Stop the gal device, including the following actions: stop the daemon
++** thread, release the irq.
++**
++** INPUT:
++**
++** gckGALDEVICE Device
++** Pointer to an gckGALDEVICE object.
++**
++** OUTPUT:
++**
++** Nothing.
++**
++** RETURNS:
++**
++** Nothing.
++*/
++gceSTATUS
++gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Device=0x%x", Device);
++
++ gcmkVERIFY_ARGUMENT(Device != NULL);
++
++ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ {
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF
++ ));
++
++ /* Remove the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR(Device));
++ }
++
++ if (Device->kernels[gcvCORE_2D] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR_2D(Device));
++
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF
++ ));
++ }
++
++ if (Device->kernels[gcvCORE_VG] != gcvNULL)
++ {
++ /* Setup the ISR routine. */
++ gcmkONERROR(gckGALDEVICE_Release_ISR_VG(Device));
++
++#if gcdENABLE_VG
++ /* Switch to OFF power state. */
++ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState(
++ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF
++ ));
++#endif
++ }
++
++ /* Stop the kernel thread. */
++ gcmkONERROR(gckGALDEVICE_Stop_Threads(Device));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,215 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_device_h_
++#define __gc_hal_kernel_device_h_
++
++#include "gc_hal_kernel_debugfs.h"
++
++/******************************************************************************\
++******************************* gckGALDEVICE Structure *******************************
++\******************************************************************************/
++
++typedef struct _gckGALDEVICE
++{
++ /* Objects. */
++ gckOS os;
++ gckKERNEL kernels[gcdMAX_GPU_COUNT];
++
++ gcsPLATFORM* platform;
++
++ /* Attributes. */
++ gctSIZE_T internalSize;
++ gctPHYS_ADDR internalPhysical;
++ gctUINT32 internalPhysicalName;
++ gctPOINTER internalLogical;
++ gckVIDMEM internalVidMem;
++ gctSIZE_T externalSize;
++ gctPHYS_ADDR externalPhysical;
++ gctUINT32 externalPhysicalName;
++ gctPOINTER externalLogical;
++ gckVIDMEM externalVidMem;
++ gckVIDMEM contiguousVidMem;
++ gctPOINTER contiguousBase;
++ gctPHYS_ADDR contiguousPhysical;
++ gctUINT32 contiguousPhysicalName;
++ gctSIZE_T contiguousSize;
++ gctBOOL contiguousMapped;
++ gctPOINTER contiguousMappedUser;
++ gctBOOL contiguousRequested;
++ gctSIZE_T systemMemorySize;
++ gctUINT32 systemMemoryBaseAddress;
++#if gcdMULTI_GPU
++ gctPOINTER registerBase3D[gcdMULTI_GPU];
++ gctSIZE_T registerSize3D[gcdMULTI_GPU];
++#endif
++ gctPOINTER registerBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T registerSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 baseAddress;
++ gctUINT32 physBase;
++ gctUINT32 physSize;
++ gctBOOL mmu;
++#if gcdMULTI_GPU
++ gctUINT32 requestedRegisterMemBase3D[gcdMULTI_GPU];
++ gctSIZE_T requestedRegisterMemSize3D[gcdMULTI_GPU];
++#endif
++ gctUINT32 requestedRegisterMemBases[gcdMAX_GPU_COUNT];
++ gctSIZE_T requestedRegisterMemSizes[gcdMAX_GPU_COUNT];
++ gctUINT32 requestedContiguousBase;
++ gctSIZE_T requestedContiguousSize;
++
++ /* IRQ management. */
++#if gcdMULTI_GPU
++ gctINT irqLine3D[gcdMULTI_GPU];
++ gctBOOL isrInitialized3D[gcdMULTI_GPU];
++ gctBOOL dataReady3D[gcdMULTI_GPU];
++#endif
++ gctINT irqLines[gcdMAX_GPU_COUNT];
++ gctBOOL isrInitializeds[gcdMAX_GPU_COUNT];
++
++ /* Thread management. */
++#if gcdMULTI_GPU
++ struct task_struct *threadCtxt3D[gcdMULTI_GPU];
++ wait_queue_head_t intrWaitQueue3D[gcdMULTI_GPU];
++ gctBOOL threadInitialized3D[gcdMULTI_GPU];
++#endif
++ struct task_struct *threadCtxts[gcdMAX_GPU_COUNT];
++ struct semaphore semas[gcdMAX_GPU_COUNT];
++ gctBOOL threadInitializeds[gcdMAX_GPU_COUNT];
++ gctBOOL killThread;
++
++ /* Signal management. */
++ gctINT signal;
++
++ /* Core mapping */
++ gceCORE coreMapping[8];
++
++ /* States before suspend. */
++ gceCHIPPOWERSTATE statesStored[gcdMAX_GPU_COUNT];
++
++ /* Device Debug File System Entry in kernel. */
++ struct _gcsDEBUGFS_Node * dbgNode;
++
++ gcsDEBUGFS_DIR debugfsDir;
++}
++* gckGALDEVICE;
++
++typedef struct _gcsHAL_PRIVATE_DATA
++{
++ gckGALDEVICE device;
++ gctPOINTER mappedMemory;
++ gctPOINTER contiguousLogical;
++ /* The process opening the device may not be the same as the one that closes it. */
++ gctUINT32 pidOpen;
++}
++gcsHAL_PRIVATE_DATA, * gcsHAL_PRIVATE_DATA_PTR;
++
++typedef struct _gcsDEVICE_CONSTRUCT_ARGS
++{
++ gctBOOL recovery;
++ gctUINT stuckDump;
++ gctUINT gpu3DMinClock;
++
++ gctBOOL contiguousRequested;
++ gcsPLATFORM* platform;
++ gctBOOL mmu;
++}
++gcsDEVICE_CONSTRUCT_ARGS;
++
++gceSTATUS gckGALDEVICE_Setup_ISR(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Setup_ISR_2D(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Setup_ISR_VG(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Release_ISR(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Release_ISR_2D(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Release_ISR_VG(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Start_Threads(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop_Threads(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Start(
++ IN gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Stop(
++ gckGALDEVICE Device
++ );
++
++gceSTATUS gckGALDEVICE_Construct(
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ IN gctINT IrqLine3D0,
++ IN gctUINT32 RegisterMemBase3D0,
++ IN gctSIZE_T RegisterMemSize3D0,
++ IN gctINT IrqLine3D1,
++ IN gctUINT32 RegisterMemBase3D1,
++ IN gctSIZE_T RegisterMemSize3D1,
++#else
++ IN gctINT IrqLine,
++ IN gctUINT32 RegisterMemBase,
++ IN gctSIZE_T RegisterMemSize,
++#endif
++ IN gctINT IrqLine2D,
++ IN gctUINT32 RegisterMemBase2D,
++ IN gctSIZE_T RegisterMemSize2D,
++ IN gctINT IrqLineVG,
++ IN gctUINT32 RegisterMemBaseVG,
++ IN gctSIZE_T RegisterMemSizeVG,
++ IN gctUINT32 ContiguousBase,
++ IN gctSIZE_T ContiguousSize,
++ IN gctSIZE_T BankSize,
++ IN gctINT FastClear,
++ IN gctINT Compression,
++ IN gctUINT32 PhysBaseAddr,
++ IN gctUINT32 PhysSize,
++ IN gctINT Signal,
++ IN gctUINT LogFileSize,
++ IN gctINT PowerManagement,
++ IN gctINT GpuProfiler,
++ IN gcsDEVICE_CONSTRUCT_ARGS * Args,
++ OUT gckGALDEVICE *Device
++ );
++
++gceSTATUS gckGALDEVICE_Destroy(
++ IN gckGALDEVICE Device
++ );
++
++#endif /* __gc_hal_kernel_device_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_iommu.c 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,216 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_device.h"
++
++#include <linux/iommu.h>
++#include <linux/platform_device.h>
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++typedef struct _gcsIOMMU
++{
++ struct iommu_domain * domain;
++ struct device * device;
++}
++gcsIOMMU;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++static int
++_IOMMU_Fault_Handler(
++ struct iommu_domain * Domain,
++ struct device * Dev,
++ unsigned long DomainAddress,
++ int flags,
++ void * args
++ )
++#else
++static int
++_IOMMU_Fault_Handler(
++ struct iommu_domain * Domain,
++ struct device * Dev,
++ unsigned long DomainAddress,
++ int flags
++ )
++#endif
++{
++ return 0;
++}
++
++static int
++_FlatMapping(
++ IN gckIOMMU Iommu
++ )
++{
++ gceSTATUS status;
++ gctUINT32 physical;
++
++ for (physical = 0; physical < 0x80000000; physical += PAGE_SIZE)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "Map %x => %x bytes = %d",
++ physical, physical, PAGE_SIZE
++ );
++
++ gcmkONERROR(gckIOMMU_Map(Iommu, physical, physical, PAGE_SIZE));
++ }
++
++ return gcvSTATUS_OK;
++
++OnError:
++ return status;
++}
++
++void
++gckIOMMU_Destory(
++ IN gckOS Os,
++ IN gckIOMMU Iommu
++ )
++{
++ gcmkHEADER();
++
++ if (Iommu->domain && Iommu->device)
++ {
++ iommu_attach_device(Iommu->domain, Iommu->device);
++ }
++
++ if (Iommu->domain)
++ {
++ iommu_domain_free(Iommu->domain);
++ }
++
++ if (Iommu)
++ {
++ gcmkOS_SAFE_FREE(Os, Iommu);
++ }
++
++ gcmkFOOTER_NO();
++}
++
++gceSTATUS
++gckIOMMU_Construct(
++ IN gckOS Os,
++ OUT gckIOMMU * Iommu
++ )
++{
++ gceSTATUS status;
++ gckIOMMU iommu = gcvNULL;
++ struct device *dev;
++ int ret;
++
++ gcmkHEADER();
++
++ dev = &Os->device->platform->device->dev;
++
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsIOMMU), (gctPOINTER *)&iommu));
++
++ gckOS_ZeroMemory(iommu, gcmSIZEOF(gcsIOMMU));
++
++ iommu->domain = iommu_domain_alloc(&platform_bus_type);
++
++ if (!iommu->domain)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "iommu_domain_alloc() fail");
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ iommu_set_fault_handler(iommu->domain, _IOMMU_Fault_Handler, dev);
++#else
++ iommu_set_fault_handler(iommu->domain, _IOMMU_Fault_Handler);
++#endif
++
++ ret = iommu_attach_device(iommu->domain, dev);
++
++ if (ret)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS, "iommu_attach_device() fail %d", ret);
++
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ iommu->device = dev;
++
++ _FlatMapping(iommu);
++
++ *Iommu = iommu;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ gckIOMMU_Destory(Os, iommu);
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckIOMMU_Map(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes
++ )
++{
++ gceSTATUS status;
++ int ret;
++
++ gcmkHEADER_ARG("DomainAddress=%#X, Physical=%#X, Bytes=%d",
++ DomainAddress, Physical, Bytes);
++
++ ret = iommu_map(Iommu->domain, DomainAddress, Physical, Bytes, 0);
++
++ if (ret)
++ {
++ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++
++ gcmkFOOTER();
++ return status;
++
++}
++
++gceSTATUS
++gckIOMMU_Unmap(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Bytes
++ )
++{
++ gcmkHEADER();
++
++ iommu_unmap(Iommu->domain, DomainAddress, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.c 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,497 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#define _GC_OBJ_ZONE gcvZONE_KERNEL
++
++/******************************************************************************\
++******************************* gckKERNEL API Code ******************************
++\******************************************************************************/
++
++/*******************************************************************************
++**
++** gckKERNEL_QueryVideoMemory
++**
++** Query the amount of video memory.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** OUTPUT:
++**
++** gcsHAL_INTERFACE * Interface
++** Pointer to an gcsHAL_INTERFACE structure that will be filled in with
++** the memory information.
++*/
++gceSTATUS
++gckKERNEL_QueryVideoMemory(
++ IN gckKERNEL Kernel,
++ OUT gcsHAL_INTERFACE * Interface
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Interface != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Get internal memory size and physical address. */
++ Interface->u.QueryVideoMemory.internalSize = device->internalSize;
++ Interface->u.QueryVideoMemory.internalPhysical = device->internalPhysicalName;
++
++ /* Get external memory size and physical address. */
++ Interface->u.QueryVideoMemory.externalSize = device->externalSize;
++ Interface->u.QueryVideoMemory.externalPhysical = device->externalPhysicalName;
++
++ /* Get contiguous memory size and physical address. */
++ Interface->u.QueryVideoMemory.contiguousSize = device->contiguousSize;
++ Interface->u.QueryVideoMemory.contiguousPhysical = device->contiguousPhysicalName;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_GetVideoMemoryPool
++**
++** Get the gckVIDMEM object belonging to the specified pool.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gcePOOL Pool
++** Pool to query gckVIDMEM object for.
++**
++** OUTPUT:
++**
++** gckVIDMEM * VideoMemory
++** Pointer to a variable that will hold the pointer to the gckVIDMEM
++** object belonging to the requested pool.
++*/
++gceSTATUS
++gckKERNEL_GetVideoMemoryPool(
++ IN gckKERNEL Kernel,
++ IN gcePOOL Pool,
++ OUT gckVIDMEM * VideoMemory
++ )
++{
++ gckGALDEVICE device;
++ gckVIDMEM videoMemory;
++
++ gcmkHEADER_ARG("Kernel=%p Pool=%d", Kernel, Pool);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(VideoMemory != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Dispatch on pool. */
++ switch (Pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ videoMemory = device->internalVidMem;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ videoMemory = device->externalVidMem;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ videoMemory = device->contiguousVidMem;
++ break;
++
++ default:
++ /* Unknown pool. */
++ videoMemory = NULL;
++ }
++
++ /* Return pointer to the gckVIDMEM object. */
++ *VideoMemory = videoMemory;
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*VideoMemory=%p", *VideoMemory);
++ return (videoMemory == NULL) ? gcvSTATUS_OUT_OF_MEMORY : gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapMemory
++**
++** Map video memory into the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the base address of the mapped
++** memory region.
++*/
++gceSTATUS
++gckKERNEL_MapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_MapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_UnmapMemory
++**
++** Unmap video memory from the current process space.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of video memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** gctPOINTER Logical
++** Base address of the mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_UnmapMemory(
++ IN gckKERNEL Kernel,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gckKERNEL kernel = Kernel;
++ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical);
++
++ return gckOS_UnmapMemory(Kernel->os, physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemoryEx(
++ IN gckKERNEL Kernel,
++ IN gceCORE Core,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ gckGALDEVICE device = gcvNULL;
++ PLINUX_MDL mdl = gcvNULL;
++ PLINUX_MDL_MAP mdlMap = gcvNULL;
++ gcePOOL pool = gcvPOOL_UNKNOWN;
++ gctUINT32 offset = 0;
++ gctUINT32 base = 0;
++ gceSTATUS status;
++ gctPOINTER logical = gcvNULL;
++ gctUINT32 baseAddress;
++
++ gcmkHEADER_ARG("Kernel=%p InUserSpace=%d Address=%08x",
++ Kernel, InUserSpace, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Logical != NULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware, Address, &pool, &offset));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkONERROR(
++ gckHARDWARE_SplitMemory(Kernel->hardware, Address, &pool, &offset));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ if (device->contiguousMapped)
++ {
++ logical = device->contiguousBase;
++ }
++ else
++ {
++ gctINT processID;
++ gckOS_GetProcessID(&processID);
++
++ mdl = (PLINUX_MDL) device->contiguousPhysical;
++
++ mdlMap = FindMdlMap(mdl, processID);
++ gcmkASSERT(mdlMap);
++
++ logical = (gctPOINTER) mdlMap->vmaAddr;
++ }
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkVERIFY_OK(
++ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware,
++ device->contiguousVidMem->baseAddress,
++ &pool,
++ &base));
++ }
++ else
++#endif
++ {
++ gctUINT32 systemBaseAddress = 0;
++
++ if (Kernel->hardware->mmuVersion == 0)
++ {
++ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &systemBaseAddress));
++ }
++
++ gcmkVERIFY_OK(
++ gckOS_CPUPhysicalToGPUPhysical(
++ Kernel->os,
++ device->contiguousVidMem->baseAddress - systemBaseAddress,
++ &baseAddress
++ ));
++
++ gcmkVERIFY_OK(
++ gckHARDWARE_SplitMemory(Kernel->hardware,
++ baseAddress,
++ &pool,
++ &base));
++ }
++ offset -= base;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Build logical address of specified address. */
++ *Logical = (gctPOINTER) ((gctUINT8_PTR) logical + offset);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=%p", *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Retunn the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckKERNEL_MapVideoMemory
++**
++** Get the logical address for a hardware specific memory address for the
++** current process.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE to map the memory into the user space.
++**
++** gctUINT32 Address
++** Hardware specific memory address.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** specified memory address.
++*/
++gceSTATUS
++gckKERNEL_MapVideoMemory(
++ IN gckKERNEL Kernel,
++ IN gctBOOL InUserSpace,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * Logical
++ )
++{
++ return gckKERNEL_MapVideoMemoryEx(Kernel, gcvCORE_MAJOR, InUserSpace, Address, Logical);
++}
++/*******************************************************************************
++**
++** gckKERNEL_Notify
++**
++** This function iscalled by clients to notify the gckKERNRL object of an event.
++**
++** INPUT:
++**
++** gckKERNEL Kernel
++** Pointer to an gckKERNEL object.
++**
++** gceNOTIFY Notification
++** Notification event.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckKERNEL_Notify(
++ IN gckKERNEL Kernel,
++#if gcdMULTI_GPU
++ IN gctUINT CoreId,
++#endif
++ IN gceNOTIFY Notification,
++ IN gctBOOL Data
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Kernel=%p Notification=%d Data=%d",
++ Kernel, Notification, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++
++ /* Dispatch on notifcation. */
++ switch (Notification)
++ {
++ case gcvNOTIFY_INTERRUPT:
++ /* Process the interrupt. */
++#if COMMAND_PROCESSOR_VERSION > 1
++ status = gckINTERRUPT_Notify(Kernel->interrupt, Data);
++#else
++ status = gckHARDWARE_Interrupt(Kernel->hardware,
++#if gcdMULTI_GPU
++ CoreId,
++#endif
++ Data);
++#endif
++ break;
++
++ default:
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckKERNEL_QuerySettings(
++ IN gckKERNEL Kernel,
++ OUT gcsKERNEL_SETTINGS * Settings
++ )
++{
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("Kernel=%p", Kernel);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL);
++ gcmkVERIFY_ARGUMENT(Settings != gcvNULL);
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Kernel->context;
++
++ /* Fill in signal. */
++ Settings->signal = device->signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("Settings->signal=%d", Settings->signal);
++ return gcvSTATUS_OK;
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_linux.h 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,399 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_linux_h_
++#define __gc_hal_kernel_linux_h_
++
++#include <linux/version.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/fs.h>
++#include <linux/mm.h>
++#include <linux/sched.h>
++#include <linux/signal.h>
++#ifdef FLAREON
++# include <asm/arch-realview/dove_gpio_irq.h>
++#endif
++#include <linux/interrupt.h>
++#include <linux/vmalloc.h>
++#include <linux/dma-mapping.h>
++#include <linux/kthread.h>
++
++#include <linux/idr.h>
++
++#ifdef MODVERSIONS
++# include <linux/modversions.h>
++#endif
++#include <asm/io.h>
++#include <asm/uaccess.h>
++
++#if ENABLE_GPU_CLOCK_BY_DRIVER && LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
++#include <linux/clk.h>
++#endif
++
++#define NTSTRSAFE_NO_CCH_FUNCTIONS
++#include "gc_hal.h"
++#include "gc_hal_driver.h"
++#include "gc_hal_kernel.h"
++#include "gc_hal_kernel_platform.h"
++#include "gc_hal_kernel_device.h"
++#include "gc_hal_kernel_os.h"
++#include "gc_hal_kernel_debugfs.h"
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)
++#define FIND_TASK_BY_PID(x) pid_task(find_vpid(x), PIDTYPE_PID)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
++#define FIND_TASK_BY_PID(x) find_task_by_vpid(x)
++#else
++#define FIND_TASK_BY_PID(x) find_task_by_pid(x)
++#endif
++
++#define _WIDE(string) L##string
++#define WIDE(string) _WIDE(string)
++
++#define countof(a) (sizeof(a) / sizeof(a[0]))
++
++#ifndef DEVICE_NAME
++#ifdef CONFIG_DOVE_GPU
++# define DEVICE_NAME "dove_gpu"
++#else
++# define DEVICE_NAME "galcore"
++#endif
++#endif
++
++#define GetPageCount(size, offset) ((((size) + ((offset) & ~PAGE_CACHE_MASK)) + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION (3,7,0)
++#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP)
++#else
++#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_RESERVED)
++#endif
++
++/* Protection bit when mapping memroy to user sapce */
++#define gcmkPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++
++#if gcdNONPAGED_MEMORY_BUFFERABLE
++#define gcmkIOREMAP ioremap_wc
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_writecombine(x)
++#elif !gcdNONPAGED_MEMORY_CACHEABLE
++#define gcmkIOREMAP ioremap_nocache
++#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_noncached(x)
++#endif
++
++#define gcdSUPPRESS_OOM_MESSAGE 1
++
++#if gcdSUPPRESS_OOM_MESSAGE
++#define gcdNOWARN __GFP_NOWARN
++#else
++#define gcdNOWARN 0
++#endif
++
++/******************************************************************************\
++********************************** Structures **********************************
++\******************************************************************************/
++typedef struct _gcsIOMMU * gckIOMMU;
++
++typedef struct _gcsUSER_MAPPING * gcsUSER_MAPPING_PTR;
++typedef struct _gcsUSER_MAPPING
++{
++ /* Pointer to next mapping structure. */
++ gcsUSER_MAPPING_PTR next;
++
++ /* Physical address of this mapping. */
++ gctUINT32 physical;
++
++ /* Logical address of this mapping. */
++ gctPOINTER logical;
++
++ /* Number of bytes of this mapping. */
++ gctSIZE_T bytes;
++
++ /* Starting address of this mapping. */
++ gctINT8_PTR start;
++
++ /* Ending address of this mapping. */
++ gctINT8_PTR end;
++}
++gcsUSER_MAPPING;
++
++typedef struct _gcsINTEGER_DB * gcsINTEGER_DB_PTR;
++typedef struct _gcsINTEGER_DB
++{
++ struct idr idr;
++ spinlock_t lock;
++ gctINT curr;
++}
++gcsINTEGER_DB;
++
++struct _gckOS
++{
++ /* Object. */
++ gcsOBJECT object;
++
++ /* Pointer to device */
++ gckGALDEVICE device;
++
++ /* Memory management */
++ gctPOINTER memoryLock;
++ gctPOINTER memoryMapLock;
++
++ struct _LINUX_MDL *mdlHead;
++ struct _LINUX_MDL *mdlTail;
++
++ /* Kernel process ID. */
++ gctUINT32 kernelProcessID;
++
++ /* Signal management. */
++
++ /* Lock. */
++ gctPOINTER signalMutex;
++
++ /* signal id database. */
++ gcsINTEGER_DB signalDB;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /* Lock. */
++ gctPOINTER syncPointMutex;
++
++ /* sync point id database. */
++ gcsINTEGER_DB syncPointDB;
++#endif
++
++ gcsUSER_MAPPING_PTR userMap;
++ gctPOINTER debugLock;
++
++ /* workqueue for os timer. */
++ struct workqueue_struct * workqueue;
++
++ /* Allocate extra page to avoid cache overflow */
++ struct page* paddingPage;
++
++ /* Detect unfreed allocation. */
++ atomic_t allocateCount;
++
++ struct list_head allocatorList;
++
++ gcsDEBUGFS_DIR allocatorDebugfsDir;
++
++ /* Lock for register access check. */
++ struct mutex registerAccessLocks[gcdMAX_GPU_COUNT];
++
++ /* External power states. */
++ gctBOOL powerStates[gcdMAX_GPU_COUNT];
++
++ /* External clock states. */
++ gctBOOL clockStates[gcdMAX_GPU_COUNT];
++
++ /* IOMMU. */
++ gckIOMMU iommu;
++};
++
++typedef struct _gcsSIGNAL * gcsSIGNAL_PTR;
++typedef struct _gcsSIGNAL
++{
++ /* Kernel sync primitive. */
++ struct completion obj;
++
++ /* Manual reset flag. */
++ gctBOOL manualReset;
++
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* The owner of the signal. */
++ gctHANDLE process;
++
++ gckHARDWARE hardware;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSIGNAL;
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++typedef struct _gcsSYNC_POINT * gcsSYNC_POINT_PTR;
++typedef struct _gcsSYNC_POINT
++{
++ /* The reference counter. */
++ atomic_t ref;
++
++ /* State. */
++ atomic_t state;
++
++ /* timeline. */
++ struct sync_timeline * timeline;
++
++ /* ID. */
++ gctUINT32 id;
++}
++gcsSYNC_POINT;
++#endif
++
++typedef struct _gcsPageInfo * gcsPageInfo_PTR;
++typedef struct _gcsPageInfo
++{
++ struct page **pages;
++ gctUINT32_PTR pageTable;
++ gctUINT32 extraPage;
++ gctUINT32 address;
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++}
++gcsPageInfo;
++
++typedef struct _gcsOSTIMER * gcsOSTIMER_PTR;
++typedef struct _gcsOSTIMER
++{
++ struct delayed_work work;
++ gctTIMERFUNCTION function;
++ gctPOINTER data;
++} gcsOSTIMER;
++
++gceSTATUS
++gckOS_ImportAllocators(
++ gckOS Os
++ );
++
++gceSTATUS
++gckOS_FreeAllocators(
++ gckOS Os
++ );
++
++gceSTATUS
++_HandleOuterCache(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Type
++ );
++
++gceSTATUS
++_ConvertLogical2Physical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ IN PLINUX_MDL Mdl,
++ OUT gctUINT32_PTR Physical
++ );
++
++gctSTRING
++_CreateKernelVirtualMapping(
++ IN PLINUX_MDL Mdl
++ );
++
++void
++_DestoryKernelVirtualMapping(
++ IN gctSTRING Addr
++ );
++
++void
++_UnmapUserLogical(
++ IN gctPOINTER Logical,
++ IN gctUINT32 Size
++ );
++
++static inline gctINT
++_GetProcessID(
++ void
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ return task_tgid_vnr(current);
++#else
++ return current->tgid;
++#endif
++}
++
++static inline struct page *
++_NonContiguousToPage(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return Pages[Index];
++}
++
++static inline unsigned long
++_NonContiguousToPfn(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_pfn(_NonContiguousToPage(Pages, Index));
++}
++
++static inline unsigned long
++_NonContiguousToPhys(
++ IN struct page ** Pages,
++ IN gctUINT32 Index
++ )
++{
++ gcmkASSERT(Pages != gcvNULL);
++ return page_to_phys(_NonContiguousToPage(Pages, Index));
++}
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
++static inline int
++is_vmalloc_addr(
++ void *Addr
++ )
++{
++ unsigned long addr = (unsigned long)Addr;
++
++ return addr >= VMALLOC_START && addr < VMALLOC_END;
++}
++#endif
++
++#ifdef CONFIG_IOMMU_SUPPORT
++void
++gckIOMMU_Destory(
++ IN gckOS Os,
++ IN gckIOMMU Iommu
++ );
++
++gceSTATUS
++gckIOMMU_Construct(
++ IN gckOS Os,
++ OUT gckIOMMU * Iommu
++ );
++
++gceSTATUS
++gckIOMMU_Map(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Physical,
++ IN gctUINT32 Bytes
++ );
++
++gceSTATUS
++gckIOMMU_Unmap(
++ IN gckIOMMU Iommu,
++ IN gctUINT32 DomainAddress,
++ IN gctUINT32 Bytes
++ );
++#endif
++
++#endif /* __gc_hal_kernel_linux_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_math.c 2016-06-19 22:11:55.245143943 +0200
+@@ -0,0 +1,32 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++gctINT
++gckMATH_ModuloInt(
++ IN gctINT X,
++ IN gctINT Y
++ )
++{
++ if(Y ==0) {return 0;}
++ else {return X % Y;}
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,8740 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++
++#include <linux/pagemap.h>
++#include <linux/seq_file.h>
++#include <linux/mman.h>
++#include <asm/atomic.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/workqueue.h>
++#include <linux/irqflags.h>
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
++#include <linux/math64.h>
++#endif
++#include <linux/delay.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
++#include <linux/anon_inodes.h>
++#endif
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++#include <linux/file.h>
++#include "gc_hal_kernel_sync.h"
++#endif
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++#include "gc_hal_kernel_allocator.h"
++
++#define MEMORY_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryLock, \
++ gcvINFINITE))
++
++#define MEMORY_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryLock))
++
++#define MEMORY_MAP_LOCK(os) \
++ gcmkVERIFY_OK(gckOS_AcquireMutex( \
++ (os), \
++ (os)->memoryMapLock, \
++ gcvINFINITE))
++
++#define MEMORY_MAP_UNLOCK(os) \
++ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryMapLock))
++
++
++/******************************************************************************\
++******************************* Private Functions ******************************
++\******************************************************************************/
++static gctINT
++_GetThreadID(
++ void
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++ return task_pid_vnr(current);
++#else
++ return current->pid;
++#endif
++}
++
++static PLINUX_MDL
++_CreateMdl(
++ void
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER();
++
++ mdl = (PLINUX_MDL)kzalloc(sizeof(struct _LINUX_MDL), GFP_KERNEL | gcdNOWARN);
++
++ gcmkFOOTER_ARG("0x%X", mdl);
++ return mdl;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ );
++
++static gceSTATUS
++_DestroyMdl(
++ IN PLINUX_MDL Mdl
++ )
++{
++ PLINUX_MDL_MAP mdlMap, next;
++
++ gcmkHEADER_ARG("Mdl=0x%X", Mdl);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Mdl != gcvNULL);
++
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ next = mdlMap->next;
++
++ gcmkVERIFY_OK(_DestroyMdlMap(Mdl, mdlMap));
++
++ mdlMap = next;
++ }
++
++ kfree(Mdl);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++static PLINUX_MDL_MAP
++_CreateMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++
++ mdlMap = (PLINUX_MDL_MAP)kmalloc(sizeof(struct _LINUX_MDL_MAP), GFP_KERNEL | gcdNOWARN);
++ if (mdlMap == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++
++ mdlMap->pid = ProcessID;
++ mdlMap->vmaAddr = gcvNULL;
++ mdlMap->vma = gcvNULL;
++ mdlMap->count = 0;
++
++ mdlMap->next = Mdl->maps;
++ Mdl->maps = mdlMap;
++
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++}
++
++static gceSTATUS
++_DestroyMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN PLINUX_MDL_MAP MdlMap
++ )
++{
++ PLINUX_MDL_MAP prevMdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X MdlMap=0x%X", Mdl, MdlMap);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(MdlMap != gcvNULL);
++ gcmkASSERT(Mdl->maps != gcvNULL);
++
++ if (Mdl->maps == MdlMap)
++ {
++ Mdl->maps = MdlMap->next;
++ }
++ else
++ {
++ prevMdlMap = Mdl->maps;
++
++ while (prevMdlMap->next != MdlMap)
++ {
++ prevMdlMap = prevMdlMap->next;
++
++ gcmkASSERT(prevMdlMap != gcvNULL);
++ }
++
++ prevMdlMap->next = MdlMap->next;
++ }
++
++ kfree(MdlMap);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT ProcessID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++
++ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID);
++ if(Mdl == gcvNULL)
++ {
++ gcmkFOOTER_NO();
++ return gcvNULL;
++ }
++ mdlMap = Mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if (mdlMap->pid == ProcessID)
++ {
++ gcmkFOOTER_ARG("0x%X", mdlMap);
++ return mdlMap;
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvNULL;
++}
++
++/*******************************************************************************
++** Integer Id Management.
++*/
++gceSTATUS
++_AllocateIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctPOINTER KernelPointer,
++ OUT gctUINT32 *Id
++ )
++{
++ int result;
++ gctINT next;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0)
++ idr_preload(GFP_KERNEL | gcdNOWARN);
++
++ spin_lock(&Database->lock);
++
++ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
++
++ result = idr_alloc(&Database->idr, KernelPointer, next, 0, GFP_ATOMIC);
++
++ /* ID allocated should not be 0. */
++ gcmkASSERT(result != 0);
++
++ if (result > 0)
++ {
++ Database->curr = *Id = result;
++ }
++
++ spin_unlock(&Database->lock);
++
++ idr_preload_end();
++
++ if (result < 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#else
++again:
++ if (idr_pre_get(&Database->idr, GFP_KERNEL | gcdNOWARN) == 0)
++ {
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ spin_lock(&Database->lock);
++
++ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1;
++
++ /* Try to get a id greater than 0. */
++ result = idr_get_new_above(&Database->idr, KernelPointer, next, Id);
++
++ if (!result)
++ {
++ Database->curr = *Id;
++ }
++
++ spin_unlock(&Database->lock);
++
++ if (result == -EAGAIN)
++ {
++ goto again;
++ }
++
++ if (result != 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_QueryIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER pointer;
++
++ spin_lock(&Database->lock);
++
++ pointer = idr_find(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ if(pointer)
++ {
++ *KernelPointer = pointer;
++ return gcvSTATUS_OK;
++ }
++ else
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_OS,
++ "%s(%d) Id = %d is not found",
++ __FUNCTION__, __LINE__, Id);
++
++ return gcvSTATUS_NOT_FOUND;
++ }
++}
++
++gceSTATUS
++_DestroyIntegerId(
++ IN gcsINTEGER_DB_PTR Database,
++ IN gctUINT32 Id
++ )
++{
++ spin_lock(&Database->lock);
++
++ idr_remove(&Database->idr, Id);
++
++ spin_unlock(&Database->lock);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_QueryProcessPageTable(
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ spinlock_t *lock;
++ gctUINTPTR_T logical = (gctUINTPTR_T)Logical;
++ pgd_t *pgd;
++ pud_t *pud;
++ pmd_t *pmd;
++ pte_t *pte;
++
++ if (!current->mm)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pgd = pgd_offset(current->mm, logical);
++ if (pgd_none(*pgd) || pgd_bad(*pgd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pud = pud_offset(pgd, logical);
++ if (pud_none(*pud) || pud_bad(*pud))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pmd = pmd_offset(pud, logical);
++ if (pmd_none(*pmd) || pmd_bad(*pmd))
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ pte = pte_offset_map_lock(current->mm, pmd, logical, &lock);
++ if (!pte)
++ {
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ if (!pte_present(*pte))
++ {
++ pte_unmap_unlock(pte, lock);
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ *Address = (pte_pfn(*pte) << PAGE_SHIFT) | (logical & ~PAGE_MASK);
++ pte_unmap_unlock(pte, lock);
++
++ return gcvSTATUS_OK;
++}
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED && defined(CONFIG_OUTER_CACHE)
++static inline gceSTATUS
++outer_func(
++ gceCACHEOPERATION Type,
++ unsigned long Start,
++ unsigned long End
++ )
++{
++ switch (Type)
++ {
++ case gcvCACHE_CLEAN:
++ outer_clean_range(Start, End);
++ break;
++ case gcvCACHE_INVALIDATE:
++ outer_inv_range(Start, End);
++ break;
++ case gcvCACHE_FLUSH:
++ outer_flush_range(Start, End);
++ break;
++ default:
++ return gcvSTATUS_INVALID_ARGUMENT;
++ break;
++ }
++ return gcvSTATUS_OK;
++}
++
++#if gcdENABLE_OUTER_CACHE_PATCH
++/*******************************************************************************
++** _HandleOuterCache
++**
++** Handle the outer cache for the specified addresses.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Physical
++** Physical address to flush.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++**
++** gceOUTERCACHE_OPERATION Type
++** Operation need to be execute.
++*/
++gceSTATUS
++_HandleOuterCache(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Type
++ )
++{
++ gceSTATUS status;
++ unsigned long paddr;
++ gctPOINTER vaddr;
++ gctUINT32 offset, bytes, left;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu",
++ Os, Logical, Bytes);
++
++ if (Physical != gcvINVALID_ADDRESS)
++ {
++ /* Non paged memory or gcvPOOL_USER surface */
++ paddr = (unsigned long) Physical;
++ gcmkONERROR(outer_func(Type, paddr, paddr + Bytes));
++ }
++ else
++ {
++ /* Non contiguous virtual memory */
++ vaddr = Logical;
++ left = Bytes;
++
++ while (left)
++ {
++ /* Handle (part of) current page. */
++ offset = (gctUINTPTR_T)vaddr & ~PAGE_MASK;
++
++ bytes = gcmMIN(left, PAGE_SIZE - offset);
++
++ gcmkONERROR(_QueryProcessPageTable(vaddr, (gctUINT32*)&paddr));
++ gcmkONERROR(outer_func(Type, paddr, paddr + bytes));
++
++ vaddr = (gctUINT8_PTR)vaddr + bytes;
++ left -= bytes;
++ }
++ }
++
++ mb();
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++#endif
++
++gctBOOL
++_AllowAccess(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address
++ )
++{
++ gctUINT32 data;
++
++ /* Check external clock state. */
++ if (Os->clockStates[Core] == gcvFALSE)
++ {
++ gcmkPRINT("[galcore]: %s(%d) External clock off", __FUNCTION__, __LINE__);
++ return gcvFALSE;
++ }
++
++ /* Check internal clock state. */
++ if (Address == 0)
++ {
++ return gcvTRUE;
++ }
++
++#if gcdMULTI_GPU
++ if (Core == gcvCORE_MAJOR)
++ {
++ data = readl((gctUINT8 *)Os->device->registerBases[gcvCORE_3D_0_ID] + 0x0);
++ }
++ else
++#endif
++ {
++ data = readl((gctUINT8 *)Os->device->registerBases[Core] + 0x0);
++ }
++
++ if ((data & 0x3) == 0x3)
++ {
++ gcmkPRINT("[galcore]: %s(%d) Internal clock off", __FUNCTION__, __LINE__);
++ return gcvFALSE;
++ }
++
++ return gcvTRUE;
++}
++
++static gceSTATUS
++_ShrinkMemory(
++ IN gckOS Os
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->shrinkMemory)
++ {
++ platform->ops->shrinkMemory(platform);
++ }
++ else
++ {
++ gcmkFOOTER_NO();
++ return gcvSTATUS_NOT_SUPPORTED;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Construct
++**
++** Construct a new gckOS object.
++**
++** INPUT:
++**
++** gctPOINTER Context
++** Pointer to the gckGALDEVICE class.
++**
++** OUTPUT:
++**
++** gckOS * Os
++** Pointer to a variable that will hold the pointer to the gckOS object.
++*/
++gceSTATUS
++gckOS_Construct(
++ IN gctPOINTER Context,
++ OUT gckOS * Os
++ )
++{
++ gckOS os;
++ gceSTATUS status;
++ gctINT i;
++
++ gcmkHEADER_ARG("Context=0x%X", Context);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Os != gcvNULL);
++
++ /* Allocate the gckOS object. */
++ os = (gckOS) kmalloc(gcmSIZEOF(struct _gckOS), GFP_KERNEL | gcdNOWARN);
++
++ if (os == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ /* Zero the memory. */
++ gckOS_ZeroMemory(os, gcmSIZEOF(struct _gckOS));
++
++ /* Initialize the gckOS object. */
++ os->object.type = gcvOBJ_OS;
++
++ /* Set device device. */
++ os->device = Context;
++
++ /* Set allocateCount to 0, gckOS_Allocate has not been used yet. */
++ atomic_set(&os->allocateCount, 0);
++
++ /* Initialize the memory lock. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->memoryLock));
++ gcmkONERROR(gckOS_CreateMutex(os, &os->memoryMapLock));
++
++ /* Create debug lock mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->debugLock));
++
++ os->mdlHead = os->mdlTail = gcvNULL;
++
++ /* Get the kernel process ID. */
++ gcmkONERROR(gckOS_GetProcessID(&os->kernelProcessID));
++
++ /*
++ * Initialize the signal manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->signalMutex));
++
++ /* Initialize signal id database lock. */
++ spin_lock_init(&os->signalDB.lock);
++
++ /* Initialize signal id database. */
++ idr_init(&os->signalDB.idr);
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Initialize the sync point manager.
++ */
++
++ /* Initialize mutex. */
++ gcmkONERROR(gckOS_CreateMutex(os, &os->syncPointMutex));
++
++ /* Initialize sync point id database lock. */
++ spin_lock_init(&os->syncPointDB.lock);
++
++ /* Initialize sync point id database. */
++ idr_init(&os->syncPointDB.idr);
++#endif
++
++ /* Create a workqueue for os timer. */
++ os->workqueue = create_singlethread_workqueue("galcore workqueue");
++
++ if (os->workqueue == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ os->paddingPage = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN);
++ if (os->paddingPage == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++ else
++ {
++ SetPageReserved(os->paddingPage);
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ mutex_init(&os->registerAccessLocks[i]);
++ }
++
++ gckOS_ImportAllocators(os);
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (((gckGALDEVICE)(os->device))->mmu == gcvFALSE)
++ {
++ /* Only use IOMMU when internal MMU is not enabled. */
++ status = gckIOMMU_Construct(os, &os->iommu);
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Fail to setup IOMMU",
++ __FUNCTION__, __LINE__
++ );
++ }
++ }
++#endif
++
++ /* Return pointer to the gckOS object. */
++ *Os = os;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Os=0x%X", *Os);
++ return gcvSTATUS_OK;
++
++OnError:
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ if (os->syncPointMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->syncPointMutex));
++ }
++#endif
++
++ if (os->signalMutex != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->signalMutex));
++ }
++
++ if (os->memoryMapLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryMapLock));
++ }
++
++ if (os->memoryLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->memoryLock));
++ }
++
++ if (os->debugLock != gcvNULL)
++ {
++ gcmkVERIFY_OK(
++ gckOS_DeleteMutex(os, os->debugLock));
++ }
++
++ if (os->workqueue != gcvNULL)
++ {
++ destroy_workqueue(os->workqueue);
++ }
++
++ kfree(os);
++
++ /* Return the error. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Destroy
++**
++** Destroy an gckOS object.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object that needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Destroy(
++ IN gckOS Os
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ if (Os->paddingPage != gcvNULL)
++ {
++ ClearPageReserved(Os->paddingPage);
++ __free_page(Os->paddingPage);
++ Os->paddingPage = gcvNULL;
++ }
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++ /*
++ * Destroy the sync point manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->syncPointMutex));
++#endif
++
++ /*
++ * Destroy the signal manager.
++ */
++
++ /* Destroy the mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->signalMutex));
++
++ /* Destroy the memory lock. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryMapLock));
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryLock));
++
++ /* Destroy debug lock mutex. */
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->debugLock));
++
++ /* Wait for all works done. */
++ flush_workqueue(Os->workqueue);
++
++ /* Destory work queue. */
++ destroy_workqueue(Os->workqueue);
++
++ gckOS_FreeAllocators(Os);
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gckIOMMU_Destory(Os, Os->iommu);
++ }
++#endif
++
++ /* Flush the debug cache. */
++ gcmkDEBUGFLUSH(~0U);
++
++ /* Mark the gckOS object as unknown. */
++ Os->object.type = gcvOBJ_UNKNOWN;
++
++
++ /* Free the gckOS object. */
++ kfree(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ gceSTATUS status;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ gcmkHEADER();
++
++ *PageCount = mdl->numPages;
++
++ gcmkONERROR(allocator->ops->MapKernel(allocator, mdl, Logical));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_DestroyKernelVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ gcmkHEADER();
++
++ allocator->ops->UnmapKernel(allocator, mdl, Logical);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ return gckOS_LockPages(Os, Physical, Bytes, gcvFALSE, Logical, PageCount);
++}
++
++gceSTATUS
++gckOS_DestroyUserVirtualMapping(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ return gckOS_UnlockPages(Os, Physical, Bytes, Logical);
++}
++
++/*******************************************************************************
++**
++** gckOS_Allocate
++**
++** Allocate memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_Allocate(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ gcmkONERROR(gckOS_AllocateMemory(Os, Bytes, Memory));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Free
++**
++** Free allocated memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Free(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Memory=0x%X", Os, Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ gcmkONERROR(gckOS_FreeMemory(Os, Memory));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateMemory
++**
++** Allocate memory wrapper.
++**
++** INPUT:
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the allocated memory location.
++*/
++gceSTATUS
++gckOS_AllocateMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Memory
++ )
++{
++ gctPOINTER memory;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ if (Bytes > PAGE_SIZE)
++ {
++ memory = (gctPOINTER) vmalloc(Bytes);
++ }
++ else
++ {
++ memory = (gctPOINTER) kmalloc(Bytes, GFP_KERNEL | gcdNOWARN);
++ }
++
++ if (memory == gcvNULL)
++ {
++ /* Out of memory. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Increase count. */
++ atomic_inc(&Os->allocateCount);
++
++ /* Return pointer to the memory allocation. */
++ *Memory = memory;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Memory=0x%X", *Memory);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeMemory
++**
++** Free allocated memory wrapper.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory allocation to free.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeMemory(
++ IN gckOS Os,
++ IN gctPOINTER Memory
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X", Memory);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++
++ /* Free the memory from the OS pool. */
++ if (is_vmalloc_addr(Memory))
++ {
++ vfree(Memory);
++ }
++ else
++ {
++ kfree(Memory);
++ }
++
++ /* Decrease count. */
++ atomic_dec(&Os->allocateCount);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapMemory
++**
++** Map physical memory into the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Memory
++** Pointer to a variable that will hold the logical address of the
++** mapped memory.
++*/
++gceSTATUS
++gckOS_MapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (char *)vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (char *)do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): mdl->numPages: %d mdl->vmaAddr: 0x%X",
++ __FUNCTION__, __LINE__,
++ mdl->numPages,
++ mdlMap->vmaAddr
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (!mdlMap->vma)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): find_vma error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ up_write(&current->mm->mmap_sem);
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_writecombine(gcvNULL,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): dma_mmap_coherent error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#else
++#if !gcdPAGED_MEMORY_CACHEABLE
++ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++# endif
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages*PAGE_SIZE,
++ mdlMap->vma->vm_page_prot) < 0)
++ {
++ up_write(&current->mm->mmap_sem);
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): remap_pfn_range error.",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++#endif
++
++ up_write(&current->mm->mmap_sem);
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ *Logical = mdlMap->vmaAddr;
++
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemory
++**
++** Unmap physical memory out of the current process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemoryEx(Os, Physical, Bytes, Logical, _GetProcessID());
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_UnmapMemoryEx
++**
++** Unmap physical memory in the specified process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** gctUINT32 PID
++** Pid of the process that opened the device and mapped this memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapMemoryEx(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical,
++ IN gctUINT32 PID
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X PID=%d",
++ Os, Physical, Bytes, Logical, PID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PID != 0);
++
++ MEMORY_LOCK(Os);
++
++ if (Logical)
++ {
++ mdlMap = FindMdlMap(mdl, PID);
++
++ if (mdlMap == gcvNULL || mdlMap->vmaAddr == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ _UnmapUserLogical(mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE);
++
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserLogical
++**
++** Unmap user logical memory out of physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Start of physical address memory.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** gctPOINTER Memory
++** Pointer to a previously mapped memory region.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserLogical(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ gckOS_UnmapMemory(Os, Physical, Bytes, Logical);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocateNonPagedMemory
++**
++** Allocate a number of pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that holds the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that hold the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that will hold the physical address of the
++** allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that will hold the logical address of the
++** allocation.
++*/
++gceSTATUS
++gckOS_AllocateNonPagedMemory(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctSIZE_T bytes;
++ gctINT numPages;
++ PLINUX_MDL mdl = gcvNULL;
++ PLINUX_MDL_MAP mdlMap = gcvNULL;
++ gctSTRING addr;
++ gckKERNEL kernel;
++#ifdef NO_DMA_COHERENT
++ struct page * page;
++ long size, order;
++ gctPOINTER vaddr;
++#endif
++ gctBOOL locked = gcvFALSE;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Align number of bytes to page size. */
++ bytes = gcmALIGN(*Bytes, PAGE_SIZE);
++
++ /* Get total number of pages.. */
++ numPages = GetPageCount(bytes, 0);
++
++ /* Allocate mdl+vector structure */
++ mdl = _CreateMdl();
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ mdl->pagedMem = 0;
++ mdl->numPages = numPages;
++
++ MEMORY_LOCK(Os);
++ locked = gcvTRUE;
++
++#ifndef NO_DMA_COHERENT
++#ifdef CONFIG_ARM64
++ addr = dma_alloc_coherent(gcvNULL,
++#else
++ addr = dma_alloc_writecombine(gcvNULL,
++#endif
++ mdl->numPages * PAGE_SIZE,
++ &mdl->dmaHandle,
++ GFP_KERNEL | gcdNOWARN);
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ order = get_order(size);
++
++ page = alloc_pages(GFP_KERNEL | gcdNOWARN, order);
++
++ if (page == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ vaddr = (gctPOINTER)page_address(page);
++ mdl->contiguous = gcvTRUE;
++ mdl->u.contiguousPages = page;
++ addr = _CreateKernelVirtualMapping(mdl);
++ mdl->dmaHandle = virt_to_phys(vaddr);
++ mdl->kaddr = vaddr;
++
++ /* Trigger a page fault. */
++ memset(addr, 0, numPages * PAGE_SIZE);
++
++#if !defined(CONFIG_PPC)
++ /* Cache invalidate. */
++ dma_sync_single_for_device(
++ gcvNULL,
++ page_to_phys(page),
++ bytes,
++ DMA_FROM_DEVICE);
++#endif
++
++ while (size > 0)
++ {
++ SetPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++#endif
++
++ if (addr == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ kernel = Os->device->kernels[gcvCORE_MAJOR] != gcvNULL ?
++ Os->device->kernels[gcvCORE_MAJOR] : Os->device->kernels[gcvCORE_2D];
++ if (((Os->device->baseAddress & 0x80000000) != (mdl->dmaHandle & 0x80000000)) &&
++ kernel->hardware->mmuVersion == 0)
++ {
++ mdl->dmaHandle = (mdl->dmaHandle & ~0x80000000)
++ | (Os->device->baseAddress & 0x80000000);
++ }
++
++ mdl->addr = addr;
++
++ if (InUserSpace)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Only after mmap this will be valid. */
++
++ /* We need to map this to user space. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0)
++ mdlMap->vmaAddr = (gctSTRING) vm_mmap(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++#else
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vmaAddr = (gctSTRING) do_mmap_pgoff(gcvNULL,
++ 0L,
++ mdl->numPages * PAGE_SIZE,
++ PROT_READ | PROT_WRITE,
++ MAP_SHARED,
++ 0);
++
++ up_write(&current->mm->mmap_sem);
++#endif
++
++ if (IS_ERR(mdlMap->vmaAddr))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): do_mmap_pgoff error",
++ __FUNCTION__, __LINE__
++ );
++
++ mdlMap->vmaAddr = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ down_write(&current->mm->mmap_sem);
++
++ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr);
++
++ if (mdlMap->vma == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): find_vma error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#ifndef NO_DMA_COHERENT
++ if (dma_mmap_coherent(gcvNULL,
++ mdlMap->vma,
++ mdl->addr,
++ mdl->dmaHandle,
++ mdl->numPages * PAGE_SIZE) < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): dma_mmap_coherent error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#else
++#if !gcdSECURITY
++ mdlMap->vma->vm_page_prot = gcmkNONPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot);
++#endif
++ mdlMap->vma->vm_flags |= gcdVM_FLAGS;
++ mdlMap->vma->vm_pgoff = 0;
++
++ if (remap_pfn_range(mdlMap->vma,
++ mdlMap->vma->vm_start,
++ mdl->dmaHandle >> PAGE_SHIFT,
++ mdl->numPages * PAGE_SIZE,
++ mdlMap->vma->vm_page_prot))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_WARNING, gcvZONE_OS,
++ "%s(%d): remap_pfn_range error",
++ __FUNCTION__, __LINE__
++ );
++
++ up_write(&current->mm->mmap_sem);
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++#endif /* NO_DMA_COHERENT */
++
++ up_write(&current->mm->mmap_sem);
++
++ *Logical = mdlMap->vmaAddr;
++ }
++ else
++ {
++#if gcdSECURITY
++ *Logical = (gctPOINTER)mdl->kaddr;
++#else
++ *Logical = (gctPOINTER)mdl->addr;
++#endif
++ }
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to the tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Return allocated memory. */
++ *Bytes = bytes;
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdlMap != gcvNULL)
++ {
++ /* Free LINUX_MDL_MAP. */
++ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap));
++ }
++
++ if (mdl != gcvNULL)
++ {
++ /* Free LINUX_MDL. */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++ }
++ *Physical = gcvNULL;
++ *Bytes = 0;
++
++ if (locked)
++ {
++ /* Unlock memory. */
++ MEMORY_UNLOCK(Os);
++ }
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeNonPagedMemory
++**
++** Free previously allocated and mapped pages from non-paged memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes allocated.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocated memory.
++**
++** gctPOINTER Logical
++** Logical address of the allocated memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS gckOS_FreeNonPagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++#ifdef NO_DMA_COHERENT
++ unsigned size;
++ gctPOINTER vaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu Physical=0x%X Logical=0x%X",
++ Os, Bytes, Physical, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Convert physical address into a pointer to a MDL. */
++ mdl = (PLINUX_MDL) Physical;
++
++ MEMORY_LOCK(Os);
++
++#ifndef NO_DMA_COHERENT
++#ifdef CONFIG_ARM64
++ dma_free_coherent(gcvNULL,
++#else
++ dma_free_writecombine(gcvNULL,
++#endif
++ mdl->numPages * PAGE_SIZE,
++ mdl->addr,
++ mdl->dmaHandle);
++#else
++ size = mdl->numPages * PAGE_SIZE;
++ vaddr = mdl->kaddr;
++
++ while (size > 0)
++ {
++ ClearPageReserved(virt_to_page(vaddr));
++
++ vaddr += PAGE_SIZE;
++ size -= PAGE_SIZE;
++ }
++
++ free_pages((unsigned long)mdl->kaddr, get_order(mdl->numPages * PAGE_SIZE));
++
++ _DestoryKernelVirtualMapping(mdl->addr);
++#endif /* NO_DMA_COHERENT */
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ /* No mapped memory exists when free nonpaged memory */
++ gcmkASSERT(mdlMap->vmaAddr == gcvNULL);
++
++ mdlMap = mdlMap->next;
++ }
++
++ /* Remove the node from global list.. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReadRegister
++**
++** Read data from a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** OUTPUT:
++**
++** gctUINT32 * Data
++** Pointer to a variable that receives the data read from the register.
++*/
++gceSTATUS
++gckOS_ReadRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ return gckOS_ReadRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_ReadRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X", Os, Core, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++#if !gcdMULTI_GPU
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++#endif
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ if (!in_interrupt())
++ {
++ mutex_lock(&Os->registerAccessLocks[Core]);
++ }
++
++ BUG_ON(!_AllowAccess(Os, Core, Address));
++
++#if gcdMULTI_GPU
++ if (Core == gcvCORE_MAJOR)
++ {
++ *Data = readl((gctUINT8 *)Os->device->registerBase3D[gcvCORE_3D_0_ID] + Address);
++ }
++ else
++#endif
++ {
++ *Data = readl((gctUINT8 *)Os->device->registerBases[Core] + Address);
++ }
++
++ if (!in_interrupt())
++ {
++ mutex_unlock(&Os->registerAccessLocks[Core]);
++ }
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++}
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckOS_ReadRegisterByCoreId(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 CoreId,
++ IN gctUINT32 Address,
++ OUT gctUINT32 * Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d CoreId=%d Address=0x%X",
++ Os, Core, CoreId, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Data != gcvNULL);
++
++ *Data = readl((gctUINT8 *)Os->device->registerBase3D[CoreId] + Address);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Data=0x%08x", *Data);
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_WriteRegister
++**
++** Write data to a register.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Address of register.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteRegister(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ return gckOS_WriteRegisterEx(Os, gcvCORE_MAJOR, Address, Data);
++}
++
++gceSTATUS
++gckOS_WriteRegisterEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X Data=0x%08x", Os, Core, Address, Data);
++
++#if !gcdMULTI_GPU
++ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]);
++#endif
++
++ if (!in_interrupt())
++ {
++ mutex_lock(&Os->registerAccessLocks[Core]);
++ }
++
++ BUG_ON(!_AllowAccess(Os, Core, Address));
++
++#if gcdMULTI_GPU
++ if (Core == gcvCORE_MAJOR)
++ {
++ writel(Data, (gctUINT8 *)Os->device->registerBase3D[gcvCORE_3D_0_ID] + Address);
++#if gcdMULTI_GPU > 1
++ writel(Data, (gctUINT8 *)Os->device->registerBase3D[gcvCORE_3D_1_ID] + Address);
++#endif
++ }
++ else
++#endif
++ {
++ writel(Data, (gctUINT8 *)Os->device->registerBases[Core] + Address);
++ }
++
++ if (!in_interrupt())
++ {
++ mutex_unlock(&Os->registerAccessLocks[Core]);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckOS_WriteRegisterByCoreId(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 CoreId,
++ IN gctUINT32 Address,
++ IN gctUINT32 Data
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d CoreId=%d Address=0x%X Data=0x%08x",
++ Os, Core, CoreId, Address, Data);
++
++ writel(Data, (gctUINT8 *)Os->device->registerBase3D[CoreId] + Address);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_GetPageSize
++**
++** Get the system's page size.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctSIZE_T * PageSize
++** Pointer to a variable that will receive the system's page size.
++*/
++gceSTATUS gckOS_GetPageSize(
++ IN gckOS Os,
++ OUT gctSIZE_T * PageSize
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(PageSize != gcvNULL);
++
++ /* Return the page size. */
++ *PageSize = (gctSIZE_T) PAGE_SIZE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*PageSize", *PageSize);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddress
++**
++** Get the physical system address of a corresponding virtual address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ gceSTATUS status;
++ gctUINT32 processID;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X", Os, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Query page table of current process first. */
++ status = _QueryProcessPageTable(Logical, Address);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Get current process ID. */
++ processID = _GetProcessID();
++
++ /* Route through other function. */
++ gcmkONERROR(
++ gckOS_GetPhysicalAddressProcess(Os, Logical, processID, Address));
++ }
++
++ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(Os, *Address, Address));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UserLogicalToPhysical
++**
++** Get the physical system address of a corresponding user virtual address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Pointer to a variable that receives the 32-bit physical address.
++*/
++gceSTATUS gckOS_UserLogicalToPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ OUT gctUINT32 * Address
++ )
++{
++ return gckOS_GetPhysicalAddress(Os, Logical, Address);
++}
++
++#if gcdSECURE_USER
++static gceSTATUS
++gckOS_AddMapping(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gcsUSER_MAPPING_PTR map;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu",
++ Os, Physical, Logical, Bytes);
++
++ gcmkONERROR(gckOS_Allocate(Os,
++ gcmSIZEOF(gcsUSER_MAPPING),
++ (gctPOINTER *) &map));
++
++ map->next = Os->userMap;
++ map->physical = Physical - Os->device->baseAddress;
++ map->logical = Logical;
++ map->bytes = Bytes;
++ map->start = (gctINT8_PTR) Logical;
++ map->end = map->start + Bytes;
++
++ Os->userMap = map;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++static gceSTATUS
++gckOS_RemoveMapping(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++ gcsUSER_MAPPING_PTR map, prev;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes);
++
++ for (map = Os->userMap, prev = gcvNULL; map != gcvNULL; map = map->next)
++ {
++ if ((map->logical == Logical)
++ && (map->bytes == Bytes)
++ )
++ {
++ break;
++ }
++
++ prev = map;
++ }
++
++ if (map == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS);
++ }
++
++ if (prev == gcvNULL)
++ {
++ Os->userMap = map->next;
++ }
++ else
++ {
++ prev->next = map->next;
++ }
++
++ gcmkONERROR(gcmkOS_SAFE_FREE(Os, map));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++_ConvertLogical2Physical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ IN PLINUX_MDL Mdl,
++ OUT gctUINT32_PTR Physical
++ )
++{
++ gctINT8_PTR base, vBase;
++ gctUINT32 offset;
++ PLINUX_MDL_MAP map;
++ gcsUSER_MAPPING_PTR userMap;
++
++#if gcdSECURITY
++ base = (Mdl == gcvNULL) ? gcvNULL : (gctINT8_PTR) Mdl->kaddr;
++#else
++ base = (Mdl == gcvNULL) ? gcvNULL : (gctINT8_PTR) Mdl->addr;
++#endif
++
++ /* Check for the logical address match. */
++ if ((base != gcvNULL)
++ && ((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - base;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ /* paged memory is not mapped to kernel space. */
++ return gcvSTATUS_INVALID_ADDRESS;
++ }
++ else
++ {
++ *Physical = gcmPTR2INT32(virt_to_phys(base)) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++
++ /* Walk user maps. */
++ for (userMap = Os->userMap; userMap != gcvNULL; userMap = userMap->next)
++ {
++ if (((gctINT8_PTR) Logical >= userMap->start)
++ && ((gctINT8_PTR) Logical < userMap->end)
++ )
++ {
++ *Physical = userMap->physical
++ + (gctUINT32) ((gctINT8_PTR) Logical - userMap->start);
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ if (ProcessID != Os->kernelProcessID)
++ {
++ map = FindMdlMap(Mdl, (gctINT) ProcessID);
++ vBase = (map == gcvNULL) ? gcvNULL : (gctINT8_PTR) map->vmaAddr;
++
++ /* Is the given address within that range. */
++ if ((vBase != gcvNULL)
++ && ((gctINT8_PTR) Logical >= vBase)
++ && ((gctINT8_PTR) Logical < vBase + Mdl->numPages * PAGE_SIZE)
++ )
++ {
++ offset = (gctINT8_PTR) Logical - vBase;
++
++ if (Mdl->dmaHandle != 0)
++ {
++ /* The memory was from coherent area. */
++ *Physical = (gctUINT32) Mdl->dmaHandle + offset;
++ }
++ else if (Mdl->pagedMem && !Mdl->contiguous)
++ {
++ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, offset/PAGE_SIZE);
++ }
++ else
++ {
++ *Physical = page_to_phys(Mdl->u.contiguousPages) + offset;
++ }
++
++ return gcvSTATUS_OK;
++ }
++ }
++
++ /* Address not yet found. */
++ return gcvSTATUS_INVALID_ADDRESS;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetPhysicalAddressProcess
++**
++** Get the physical system address of a corresponding virtual address for a
++** given process.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctPOINTER Logical
++** Logical address.
++**
++** gctUINT32 ProcessID
++** Process ID.
++**
++** OUTPUT:
++**
++** gctUINT32 * Address
++** Poinetr to a variable that receives the 32-bit physical adress.
++*/
++gceSTATUS
++gckOS_GetPhysicalAddressProcess(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctUINT32 ProcessID,
++ OUT gctUINT32 * Address
++ )
++{
++ PLINUX_MDL mdl;
++ gctINT8_PTR base;
++ gckALLOCATOR allocator = gcvNULL;
++ gceSTATUS status = gcvSTATUS_INVALID_ADDRESS;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X ProcessID=%d", Os, Logical, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* First try the contiguous memory pool. */
++ if (Os->device->contiguousMapped)
++ {
++ base = (gctINT8_PTR) Os->device->contiguousBase;
++
++ if (((gctINT8_PTR) Logical >= base)
++ && ((gctINT8_PTR) Logical < base + Os->device->contiguousSize)
++ )
++ {
++ /* Convert logical address into physical. */
++ *Address = Os->device->contiguousVidMem->baseAddress
++ + (gctINT8_PTR) Logical - base;
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ /* Try the contiguous memory pool. */
++ mdl = (PLINUX_MDL) Os->device->contiguousPhysical;
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Walk all MDLs. */
++ for (mdl = Os->mdlHead; mdl != gcvNULL; mdl = mdl->next)
++ {
++ /* Try this MDL. */
++ allocator = mdl->allocator;
++
++ if (allocator)
++ {
++ status = allocator->ops->LogicalToPhysical(
++ allocator,
++ mdl,
++ Logical,
++ ProcessID,
++ Address
++ );
++ }
++ else
++ {
++ status = _ConvertLogical2Physical(Os,
++ Logical,
++ ProcessID,
++ mdl,
++ Address);
++ }
++
++ if (gcmIS_SUCCESS(status))
++ {
++ break;
++ }
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkONERROR(status);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Address=0x%08x", *Address);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPhysical
++**
++** Map a physical address into kernel space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Physical
++** Physical address of the memory to map.
++**
++** gctSIZE_T Bytes
++** Number of bytes to map.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the base address of the mapped
++** memory.
++*/
++gceSTATUS
++gckOS_MapPhysical(
++ IN gckOS Os,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Bytes,
++ OUT gctPOINTER * Logical
++ )
++{
++ gctPOINTER logical;
++ PLINUX_MDL mdl;
++ gctUINT32 physical = Physical;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ /* Go through our mapping to see if we know this physical address already. */
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->dmaHandle != 0)
++ {
++ if ((physical >= mdl->dmaHandle)
++ && (physical < mdl->dmaHandle + mdl->numPages * PAGE_SIZE)
++ )
++ {
++ *Logical = mdl->addr + (physical - mdl->dmaHandle);
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ if (mdl == gcvNULL)
++ {
++ struct page * page = pfn_to_page(physical >> PAGE_SHIFT);
++
++ if (pfn_valid(page_to_pfn(page)))
++ {
++ gctUINT32 offset = physical & ~PAGE_MASK;
++ struct page ** pages;
++ gctUINT numPages;
++ gctINT i;
++
++ numPages = GetPageCount(PAGE_ALIGN(offset + Bytes), 0);
++
++ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN);
++
++ if (!pages)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ for (i = 0; i < numPages; i++)
++ {
++ pages[i] = nth_page(page, i);
++ }
++
++ logical = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL));
++
++ kfree(pages);
++
++ if (logical == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Failed to vmap",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Out of resources. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ logical += offset;
++ }
++ else
++ {
++ /* Map memory as cached memory. */
++ request_mem_region(physical, Bytes, "MapRegion");
++ logical = (gctPOINTER) ioremap_nocache(physical, Bytes);
++
++ if (logical == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Failed to ioremap",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Out of resources. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES);
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++ }
++
++ /* Return pointer to mapped memory. */
++ *Logical = logical;
++ }
++
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X", *Logical);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapPhysical
++**
++** Unmap a previously mapped memory region from kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Logical
++** Pointer to the base address of the memory to unmap.
++**
++** gctSIZE_T Bytes
++** Number of bytes to unmap.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapPhysical(
++ IN gckOS Os,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl;
++
++ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ MEMORY_LOCK(Os);
++
++ mdl = Os->mdlHead;
++
++ while (mdl != gcvNULL)
++ {
++ if (mdl->addr != gcvNULL)
++ {
++ if (Logical >= (gctPOINTER)mdl->addr
++ && Logical < (gctPOINTER)((gctSTRING)mdl->addr + mdl->numPages * PAGE_SIZE))
++ {
++ break;
++ }
++ }
++
++ mdl = mdl->next;
++ }
++
++ if (mdl == gcvNULL)
++ {
++ /* Unmap the memory. */
++ vunmap((void *)((unsigned long)Logical & PAGE_MASK));
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateMutex
++**
++** Create a new mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Mutex
++** Pointer to a variable that will hold a pointer to the mutex.
++*/
++gceSTATUS
++gckOS_CreateMutex(
++ IN gckOS Os,
++ OUT gctPOINTER * Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Allocate the mutex structure. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct mutex), Mutex));
++
++ /* Initialize the mutex. */
++ mutex_init(*Mutex);
++
++ /* Return status. */
++ gcmkFOOTER_ARG("*Mutex=0x%X", *Mutex);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DeleteMutex
++**
++** Delete a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mute to be deleted.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DeleteMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%X", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Destroy the mutex. */
++ mutex_destroy((struct mutex *)Mutex);
++
++ /* Free the mutex structure. */
++ gcmkONERROR(gckOS_Free(Os, Mutex));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireMutex
++**
++** Acquire a mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be acquired.
++**
++** gctUINT32 Timeout
++** Timeout value specified in milliseconds.
++** Specify the value of gcvINFINITE to keep the thread suspended
++** until the mutex has been acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex,
++ IN gctUINT32 Timeout
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x Timeout=%u", Os, Mutex, Timeout);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ if (Timeout == gcvINFINITE)
++ {
++ /* Lock the mutex. */
++ mutex_lock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ for (;;)
++ {
++ /* Try to acquire the mutex. */
++ if (mutex_trylock(Mutex))
++ {
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ if (Timeout-- == 0)
++ {
++ break;
++ }
++
++ /* Wait for 1 millisecond. */
++ gcmkVERIFY_OK(gckOS_Delay(Os, 1));
++ }
++
++ /* Timeout. */
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_TIMEOUT);
++ return gcvSTATUS_TIMEOUT;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseMutex
++**
++** Release an acquired mutex.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Mutex
++** Pointer to the mutex to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseMutex(
++ IN gckOS Os,
++ IN gctPOINTER Mutex
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x", Os, Mutex);
++
++ /* Validate the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL);
++
++ /* Release the mutex. */
++ mutex_unlock(Mutex);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchange
++**
++** Atomically exchange a pair of 32-bit values.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctINT32_PTR Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctINT32 NewValue
++** Specifies a new value for the 32-bit value pointed to by Target.
++**
++** OUT gctINT32_PTR OldValue
++** The old value of the 32-bit value pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchange(
++ IN gckOS Os,
++ IN OUT gctUINT32_PTR Target,
++ IN gctUINT32 NewValue,
++ OUT gctUINT32_PTR OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=%u", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(OldValue != gcvNULL);
++
++ /* Exchange the pair of 32-bit values. */
++ *OldValue = (gctUINT32) atomic_xchg((atomic_t *) Target, (int) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=%u", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicExchangePtr
++**
++** Atomically exchange a pair of pointers.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** IN OUT gctPOINTER * Target
++** Pointer to the 32-bit value to exchange.
++**
++** IN gctPOINTER NewValue
++** Specifies a new value for the pointer pointed to by Target.
++**
++** OUT gctPOINTER * OldValue
++** The old value of the pointer pointed to by Target.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomicExchangePtr(
++ IN gckOS Os,
++ IN OUT gctPOINTER * Target,
++ IN gctPOINTER NewValue,
++ OUT gctPOINTER * OldValue
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=0x%X", Os, Target, NewValue);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(OldValue != gcvNULL);
++
++ /* Exchange the pair of pointers. */
++ *OldValue = (gctPOINTER)(gctUINTPTR_T) atomic_xchg((atomic_t *) Target, (int)(gctUINTPTR_T) NewValue);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*OldValue=0x%X", *OldValue);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomicSetMask
++**
++** Atomically set mask to Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to set.
++**
++** IN gctUINT32 Mask
++** Mask to set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSetMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval | Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomClearMask
++**
++** Atomically clear mask from Atom
++**
++** INPUT:
++** IN OUT gctPOINTER Atom
++** Pointer to the atom to clear.
++**
++** IN gctUINT32 Mask
++** Mask to clear.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomClearMask(
++ IN gctPOINTER Atom,
++ IN gctUINT32 Mask
++ )
++{
++ gctUINT32 oval, nval;
++
++ gcmkHEADER_ARG("Atom=0x%0x", Atom);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ do
++ {
++ oval = atomic_read((atomic_t *) Atom);
++ nval = oval & ~Mask;
++ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomConstruct
++**
++** Create an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Atom
++** Pointer to a variable receiving the constructed atom.
++*/
++gceSTATUS
++gckOS_AtomConstruct(
++ IN gckOS Os,
++ OUT gctPOINTER * Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Allocate the atom. */
++ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(atomic_t), Atom));
++
++ /* Initialize the atom. */
++ atomic_set((atomic_t *) *Atom, 0);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Atom=0x%X", *Atom);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDestroy
++**
++** Destroy an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom to destroy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomDestroy(
++ IN gckOS Os,
++ OUT gctPOINTER Atom
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Free the atom. */
++ gcmkONERROR(gcmkOS_SAFE_FREE(Os, Atom));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomGet
++**
++** Get the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable the receives the value of the atom.
++*/
++gceSTATUS
++gckOS_AtomGet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Return the current value of atom. */
++ *Value = atomic_read((atomic_t *) Atom);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomSet
++**
++** Set the 32-bit value protected by an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** gctINT32 Value
++** The value of the atom.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AtomSet(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ IN gctINT32 Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x Value=%d", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Set the current value of atom. */
++ atomic_set((atomic_t *) Atom, Value);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomIncrement
++**
++** Atomically increment the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomIncrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Increment the atom. */
++ *Value = atomic_inc_return((atomic_t *) Atom) - 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AtomDecrement
++**
++** Atomically decrement the 32-bit integer value inside an atom.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gctPOINTER Atom
++** Pointer to the atom.
++**
++** OUTPUT:
++**
++** gctINT32_PTR Value
++** Pointer to a variable that receives the original value of the atom.
++*/
++gceSTATUS
++gckOS_AtomDecrement(
++ IN gckOS Os,
++ IN gctPOINTER Atom,
++ OUT gctINT32_PTR Value
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Atom != gcvNULL);
++
++ /* Decrement the atom. */
++ *Value = atomic_dec_return((atomic_t *) Atom) + 1;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Value=%d", *Value);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_Delay
++**
++** Delay execution of the current thread for a number of milliseconds.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Delay
++** Delay to sleep, specified in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Delay(
++ IN gckOS Os,
++ IN gctUINT32 Delay
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Delay=%u", Os, Delay);
++
++ if (Delay > 0)
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28)
++ ktime_t delay = ktime_set((Delay / MSEC_PER_SEC), (Delay % MSEC_PER_SEC) * NSEC_PER_MSEC);
++ __set_current_state(TASK_UNINTERRUPTIBLE);
++ schedule_hrtimeout(&delay, HRTIMER_MODE_REL);
++#else
++ msleep(Delay);
++#endif
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTicks
++**
++** Get the number of milliseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT32_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTicks(
++ OUT gctUINT32_PTR Time
++ )
++{
++ gcmkHEADER();
++
++ *Time = jiffies_to_msecs(jiffies);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_TicksAfter
++**
++** Compare time values got from gckOS_GetTicks.
++**
++** INPUT:
++** gctUINT32 Time1
++** First time value to be compared.
++**
++** gctUINT32 Time2
++** Second time value to be compared.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR IsAfter
++** Pointer to a variable to result.
++**
++*/
++gceSTATUS
++gckOS_TicksAfter(
++ IN gctUINT32 Time1,
++ IN gctUINT32 Time2,
++ OUT gctBOOL_PTR IsAfter
++ )
++{
++ gcmkHEADER();
++
++ *IsAfter = time_after((unsigned long)Time1, (unsigned long)Time2);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetTime
++**
++** Get the number of microseconds since the system started.
++**
++** INPUT:
++**
++** OUTPUT:
++**
++** gctUINT64_PTR Time
++** Pointer to a variable to get time.
++**
++*/
++gceSTATUS
++gckOS_GetTime(
++ OUT gctUINT64_PTR Time
++ )
++{
++ struct timeval tv;
++ gcmkHEADER();
++
++ /* Return the time of day in microseconds. */
++ do_gettimeofday(&tv);
++ *Time = (tv.tv_sec * 1000000ULL) + tv.tv_usec;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MemoryBarrier
++**
++** Make sure the CPU has executed everything up to this point and the data got
++** written to the specified pointer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of memory that needs to be barriered.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MemoryBarrier(
++ IN gckOS Os,
++ IN gctPOINTER Address
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X", Os, Address);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++#if gcdNONPAGED_MEMORY_BUFFERABLE \
++ && defined (CONFIG_ARM) \
++ && (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34))
++ /* drain write buffer */
++ dsb();
++
++ /* drain outer cache's write buffer? */
++#else
++ mb();
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemory
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemory(
++ IN gckOS Os,
++ IN gctSIZE_T Bytes,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ /* Allocate the memory. */
++ gcmkONERROR(gckOS_AllocatePagedMemoryEx(Os, gcvALLOC_FLAG_NONE, Bytes, gcvNULL, Physical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AllocatePagedMemoryEx
++**
++** Allocate memory from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Flag
++** Allocation attribute.
++**
++** gctSIZE_T Bytes
++** Number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctUINT32 * Gid
++** Save the global ID for the piece of allocated memory.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocatePagedMemoryEx(
++ IN gckOS Os,
++ IN gctUINT32 Flag,
++ IN gctSIZE_T Bytes,
++ OUT gctUINT32 * Gid,
++ OUT gctPHYS_ADDR * Physical
++ )
++{
++ gctINT numPages;
++ PLINUX_MDL mdl = gcvNULL;
++ gctSIZE_T bytes;
++ gceSTATUS status = gcvSTATUS_OUT_OF_MEMORY;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Flag=%x Bytes=%lu", Os, Flag, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++
++ bytes = gcmALIGN(Bytes, PAGE_SIZE);
++
++ numPages = GetPageCount(bytes, 0);
++
++ mdl = _CreateMdl();
++ if (mdl == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Walk all allocators. */
++ list_for_each_entry(allocator, &Os->allocatorList, head)
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d) flag = %x allocator->capability = %x",
++ __FUNCTION__, __LINE__, Flag, allocator->capability);
++
++ if ((Flag & allocator->capability) != Flag)
++ {
++ continue;
++ }
++
++ status = allocator->ops->Alloc(allocator, mdl, numPages, Flag);
++
++ if (gcmIS_SUCCESS(status))
++ {
++ mdl->allocator = allocator;
++ break;
++ }
++ }
++
++ /* Check status. */
++ gcmkONERROR(status);
++
++ mdl->dmaHandle = 0;
++ mdl->addr = 0;
++ mdl->numPages = numPages;
++ mdl->pagedMem = 1;
++ mdl->contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS;
++
++ if (Gid != gcvNULL)
++ {
++ *Gid = mdl->gid;
++ }
++
++ MEMORY_LOCK(Os);
++
++ /*
++ * Add this to a global list.
++ * Will be used by get physical address
++ * and mapuser pointer functions.
++ */
++ if (!Os->mdlHead)
++ {
++ /* Initialize the queue. */
++ Os->mdlHead = Os->mdlTail = mdl;
++ }
++ else
++ {
++ /* Add to tail. */
++ mdl->prev = Os->mdlTail;
++ Os->mdlTail->next = mdl;
++ Os->mdlTail = mdl;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Return physical address. */
++ *Physical = (gctPHYS_ADDR) mdl;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Physical=0x%X", *Physical);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (mdl != gcvNULL)
++ {
++ /* Free the memory. */
++ _DestroyMdl(mdl);
++ }
++ *Physical = gcvNULL;
++
++ /* Return the status. */
++ gcmkFOOTER_ARG("Os=0x%X Flag=%x Bytes=%lu", Os, Flag, Bytes);
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreePagedMemory
++**
++** Free memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreePagedMemory(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL) Physical;
++ gckALLOCATOR allocator = (gckALLOCATOR)mdl->allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ MEMORY_LOCK(Os);
++
++ /* Remove the node from global list. */
++ if (mdl == Os->mdlHead)
++ {
++ if ((Os->mdlHead = mdl->next) == gcvNULL)
++ {
++ Os->mdlTail = gcvNULL;
++ }
++ }
++ else
++ {
++ mdl->prev->next = mdl->next;
++
++ if (mdl == Os->mdlTail)
++ {
++ Os->mdlTail = mdl->prev;
++ }
++ else
++ {
++ mdl->next->prev = mdl->prev;
++ }
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ allocator->ops->Free(allocator, mdl);
++
++ /* Free the structure... */
++ gcmkVERIFY_OK(_DestroyMdl(mdl));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_LockPages
++**
++** Lock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctBOOL Cacheable
++** Cache mode of mapping.
++**
++** OUTPUT:
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the address of the mapped
++** memory.
++**
++** gctSIZE_T * PageCount
++** Pointer to a variable that receives the number of pages required for
++** the page table according to the GPU page size.
++*/
++gceSTATUS
++gckOS_LockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctBOOL Cacheable,
++ OUT gctPOINTER * Logical,
++ OUT gctSIZE_T * PageCount
++ )
++{
++ gceSTATUS status;
++ PLINUX_MDL mdl;
++ PLINUX_MDL_MAP mdlMap;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount != gcvNULL);
++
++ mdl = (PLINUX_MDL) Physical;
++ allocator = mdl->allocator;
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = FindMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ mdlMap = _CreateMdlMap(mdl, _GetProcessID());
++
++ if (mdlMap == gcvNULL)
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++ }
++
++ if (mdlMap->vmaAddr == gcvNULL)
++ {
++ status = allocator->ops->MapUser(allocator, mdl, mdlMap, Cacheable);
++
++ if (gcmIS_ERROR(status))
++ {
++ MEMORY_UNLOCK(Os);
++
++ gcmkFOOTER_ARG("*status=%d", status);
++ return status;
++ }
++ }
++
++ mdlMap->count++;
++
++ /* Convert pointer to MDL. */
++ *Logical = mdlMap->vmaAddr;
++
++ /* Return the page number according to the GPU page size. */
++ gcmkASSERT((PAGE_SIZE % 4096) == 0);
++ gcmkASSERT((PAGE_SIZE / 4096) >= 1);
++
++ *PageCount = mdl->numPages * (PAGE_SIZE / 4096);
++
++ MEMORY_UNLOCK(Os);
++
++ gcmkVERIFY_OK(gckOS_CacheFlush(
++ Os,
++ _GetProcessID(),
++ Physical,
++ gcvINVALID_ADDRESS,
++ (gctPOINTER)mdlMap->vmaAddr,
++ mdl->numPages * PAGE_SIZE
++ ));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Logical=0x%X *PageCount=%lu", *Logical, *PageCount);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapPages
++**
++** Map paged memory into a page table.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T PageCount
++** Number of pages required for the physical address.
++**
++** gctPOINTER PageTable
++** Pointer to the page table to fill in.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_MapPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctPOINTER PageTable
++ )
++{
++ return gckOS_MapPagesEx(Os,
++ gcvCORE_MAJOR,
++ Physical,
++ PageCount,
++ 0,
++ PageTable);
++}
++
++gceSTATUS
++gckOS_MapPagesEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address,
++ IN gctPOINTER PageTable
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ PLINUX_MDL mdl;
++ gctUINT32* table;
++ gctUINT32 offset;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ gckMMU mmu;
++ PLINUX_MDL mmuMdl;
++ gctUINT32 bytes;
++ gctPHYS_ADDR pageTablePhysical;
++#endif
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckKERNEL kernel = Os->device->kernels[Core];
++ gckMMU mmu;
++#endif
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Physical=0x%X PageCount=%u PageTable=0x%X",
++ Os, Core, Physical, PageCount, PageTable);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL);
++
++ /* Convert pointer to MDL. */
++ mdl = (PLINUX_MDL)Physical;
++
++ allocator = mdl->allocator;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Physical->0x%X PageCount->0x%X PagedMemory->?%d",
++ __FUNCTION__, __LINE__,
++ (gctUINT32)(gctUINTPTR_T)Physical,
++ (gctUINT32)(gctUINTPTR_T)PageCount,
++ mdl->pagedMem
++ );
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(kernel, &mmu));
++#endif
++
++ table = (gctUINT32 *)PageTable;
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ mmu = Os->device->kernels[Core]->mmu;
++ bytes = PageCount * sizeof(*table);
++ mmuMdl = (PLINUX_MDL)mmu->pageTablePhysical;
++#endif
++
++ /* Get all the physical addresses and store them in the page table. */
++
++ offset = 0;
++ PageCount = PageCount / (PAGE_SIZE / 4096);
++
++ /* Try to get the user pages so DMA can happen. */
++ while (PageCount-- > 0)
++ {
++ gctUINT i;
++ gctUINT32 phys = ~0;
++
++ if (mdl->pagedMem && !mdl->contiguous)
++ {
++ allocator->ops->Physical(allocator, mdl, offset, &phys);
++ }
++ else
++ {
++ if (!mdl->pagedMem)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): we should not get this call for Non Paged Memory!",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ phys = page_to_phys(nth_page(mdl->u.contiguousPages, offset));
++ }
++
++ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(Os, phys, &phys));
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Setup mapping in IOMMU %x => %x",
++ __FUNCTION__, __LINE__,
++ Address + (offset * PAGE_SIZE), phys
++ );
++
++ /* When use IOMMU, GPU use system PAGE_SIZE. */
++ gcmkONERROR(gckIOMMU_Map(
++ Os->iommu, Address + (offset * PAGE_SIZE), phys, PAGE_SIZE));
++ }
++ else
++#endif
++ {
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ for (i = 0; i < (PAGE_SIZE / 4096); i++)
++ {
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ phys + (i * 4096),
++ table++));
++ }
++ }
++ else
++#endif
++ {
++ for (i = 0; i < (PAGE_SIZE / 4096); i++)
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ gctUINT32_PTR pageTableEntry;
++ gckMMU_GetPageEntry(mmu, Address + (offset * 4096), &pageTableEntry);
++ gcmkONERROR(
++ gckMMU_SetPage(mmu,
++ phys + (i * 4096),
++ pageTableEntry));
++#else
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ phys + (i * 4096),
++ table++));
++#endif
++ }
++ }
++ }
++
++ offset += 1;
++ }
++
++#if gcdNONPAGED_MEMORY_CACHEABLE
++ /* Get physical address of pageTable */
++ pageTablePhysical = (gctPHYS_ADDR)(mmuMdl->dmaHandle +
++ ((gctUINT32 *)PageTable - mmu->pageTableLogical));
++
++ /* Flush the mmu page table cache. */
++ gcmkONERROR(gckOS_CacheClean(
++ Os,
++ _GetProcessID(),
++ gcvNULL,
++ pageTablePhysical,
++ PageTable,
++ bytes
++ ));
++#endif
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_UnmapPages(
++ IN gckOS Os,
++ IN gctSIZE_T PageCount,
++ IN gctUINT32 Address
++ )
++{
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gcmkVERIFY_OK(gckIOMMU_Unmap(
++ Os->iommu, Address, PageCount * PAGE_SIZE));
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnlockPages
++**
++** Unlock memory allocated from the paged pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** gctPOINTER Logical
++** Address of the mapped memory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnlockPages(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T Bytes,
++ IN gctPOINTER Logical
++ )
++{
++ PLINUX_MDL_MAP mdlMap;
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u Logical=0x%X",
++ Os, Physical, Bytes, Logical);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ MEMORY_LOCK(Os);
++
++ mdlMap = mdl->maps;
++
++ while (mdlMap != gcvNULL)
++ {
++ if ((mdlMap->vmaAddr != gcvNULL) && (_GetProcessID() == mdlMap->pid))
++ {
++ if (--mdlMap->count == 0)
++ {
++ allocator->ops->UnmapUser(
++ allocator,
++ mdlMap->vmaAddr,
++ mdl->numPages * PAGE_SIZE);
++
++ mdlMap->vmaAddr = gcvNULL;
++ }
++ }
++
++ mdlMap = mdlMap->next;
++ }
++
++ MEMORY_UNLOCK(Os);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++
++/*******************************************************************************
++**
++** gckOS_AllocateContiguous
++**
++** Allocate memory from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL InUserSpace
++** gcvTRUE if the pages need to be mapped into user space.
++**
++** gctSIZE_T * Bytes
++** Pointer to the number of bytes to allocate.
++**
++** OUTPUT:
++**
++** gctSIZE_T * Bytes
++** Pointer to a variable that receives the number of bytes allocated.
++**
++** gctPHYS_ADDR * Physical
++** Pointer to a variable that receives the physical address of the
++** memory allocation.
++**
++** gctPOINTER * Logical
++** Pointer to a variable that receives the logical address of the
++** memory allocation.
++*/
++gceSTATUS
++gckOS_AllocateContiguous(
++ IN gckOS Os,
++ IN gctBOOL InUserSpace,
++ IN OUT gctSIZE_T * Bytes,
++ OUT gctPHYS_ADDR * Physical,
++ OUT gctPOINTER * Logical
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu",
++ Os, InUserSpace, gcmOPT_VALUE(Bytes));
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL);
++ gcmkVERIFY_ARGUMENT(*Bytes > 0);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++
++ /* Same as non-paged memory for now. */
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(Os,
++ InUserSpace,
++ Bytes,
++ Physical,
++ Logical));
++
++ /* Success. */
++ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X",
++ *Bytes, *Physical, *Logical);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_FreeContiguous
++**
++** Free memory allocated from the contiguous pool.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPHYS_ADDR Physical
++** Physical address of the allocation.
++**
++** gctPOINTER Logical
++** Logicval address of the allocation.
++**
++** gctSIZE_T Bytes
++** Number of bytes of the allocation.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FreeContiguous(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu",
++ Os, Physical, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ /* Same of non-paged memory for now. */
++ gcmkONERROR(gckOS_FreeNonPagedMemory(Os, Bytes, Physical, Logical));
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++/******************************************************************************
++**
++** gckOS_GetKernelLogical
++**
++** Return the kernel logical pointer that corresponods to the specified
++** hardware address.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 Address
++** Hardware physical address.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the pointer in kernel address space.
++*/
++gceSTATUS
++gckOS_GetKernelLogical(
++ IN gckOS Os,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ return gckOS_GetKernelLogicalEx(Os, gcvCORE_MAJOR, Address, KernelPointer);
++}
++
++gceSTATUS
++gckOS_GetKernelLogicalEx(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT32 Address,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%08x", Os, Core, Address);
++
++ do
++ {
++ gckGALDEVICE device;
++ gckKERNEL kernel;
++ gcePOOL pool;
++ gctUINT32 offset;
++ gctPOINTER logical;
++
++ /* Extract the pointer to the gckGALDEVICE class. */
++ device = (gckGALDEVICE) Os->device;
++
++ /* Kernel shortcut. */
++ kernel = device->kernels[Core];
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkERR_BREAK(gckVGHARDWARE_SplitMemory(
++ kernel->vg->hardware, Address, &pool, &offset
++ ));
++ }
++ else
++#endif
++ {
++ /* Split the memory address into a pool type and offset. */
++ gcmkERR_BREAK(gckHARDWARE_SplitMemory(
++ kernel->hardware, Address, &pool, &offset
++ ));
++ }
++
++ /* Dispatch on pool. */
++ switch (pool)
++ {
++ case gcvPOOL_LOCAL_INTERNAL:
++ /* Internal memory. */
++ logical = device->internalLogical;
++ break;
++
++ case gcvPOOL_LOCAL_EXTERNAL:
++ /* External memory. */
++ logical = device->externalLogical;
++ break;
++
++ case gcvPOOL_SYSTEM:
++ /* System memory. */
++ logical = device->contiguousBase;
++ break;
++
++ default:
++ /* Invalid memory pool. */
++ gcmkFOOTER();
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ /* Build logical address of specified address. */
++ * KernelPointer = ((gctUINT8_PTR) logical) + offset;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ /* Return status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_MapUserPointer
++**
++** Map a pointer from the user process into the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be mapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be mapped.
++**
++** OUTPUT:
++**
++** gctPOINTER * KernelPointer
++** Pointer to a variable receiving the mapped pointer in kernel address
++** space.
++*/
++gceSTATUS
++gckOS_MapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * KernelPointer
++ )
++{
++ gctPOINTER buf = gcvNULL;
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu", Os, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ buf = kmalloc(Size, GFP_KERNEL | gcdNOWARN);
++ if (buf == gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to allocate memory.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY);
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ len = copy_from_user(buf, Pointer, Size);
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data from user.",
++ __FUNCTION__, __LINE__
++ );
++
++ if (buf != gcvNULL)
++ {
++ kfree(buf);
++ }
++
++ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ *KernelPointer = buf;
++
++ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserPointer
++**
++** Unmap a user process pointer from the kernel address space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Pointer
++** Pointer in user process space that needs to be unmapped.
++**
++** gctSIZE_T Size
++** Number of bytes that need to be unmapped.
++**
++** gctPOINTER KernelPointer
++** Pointer in kernel address space that needs to be unmapped.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserPointer(
++ IN gckOS Os,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size,
++ IN gctPOINTER KernelPointer
++ )
++{
++ gctUINT32 len;
++
++ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu KernelPointer=0x%X",
++ Os, Pointer, Size, KernelPointer);
++
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++
++ len = copy_to_user(Pointer, KernelPointer, Size);
++
++ kfree(KernelPointer);
++
++ if (len != 0)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): Failed to copy data to user.",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_GENERIC_IO);
++ return gcvSTATUS_GENERIC_IO;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryNeedCopy
++**
++** Query whether the memory can be accessed or mapped directly or it has to be
++** copied.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID of the current process.
++**
++** OUTPUT:
++**
++** gctBOOL_PTR NeedCopy
++** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or
++** gcvFALSE if the memory can be accessed or mapped dircetly.
++*/
++gceSTATUS
++gckOS_QueryNeedCopy(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ OUT gctBOOL_PTR NeedCopy
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d", Os, ProcessID);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(NeedCopy != gcvNULL);
++
++ /* We need to copy data. */
++ *NeedCopy = gcvTRUE;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*NeedCopy=%d", *NeedCopy);
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyFromUserData
++**
++** Copy data from user to kernel memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyFromUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data from user. */
++ if (copy_from_user(KernelPointer, Pointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_CopyToUserData
++**
++** Copy data from kernel to user memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER KernelPointer
++** Pointer to kernel memory.
++**
++** gctPOINTER Pointer
++** Pointer to user memory.
++**
++** gctSIZE_T Size
++** Number of bytes to copy.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_CopyToUserData(
++ IN gckOS Os,
++ IN gctPOINTER KernelPointer,
++ IN gctPOINTER Pointer,
++ IN gctSIZE_T Size
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu",
++ Os, KernelPointer, Pointer, Size);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++
++ /* Copy data to user. */
++ if (copy_to_user(Pointer, KernelPointer, Size) != 0)
++ {
++ /* Could not copy all the bytes. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WriteMemory
++**
++** Write data to a memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctPOINTER Address
++** Address of the memory to write to.
++**
++** gctUINT32 Data
++** Data for register.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WriteMemory(
++ IN gckOS Os,
++ IN gctPOINTER Address,
++ IN gctUINT32 Data
++ )
++{
++ gceSTATUS status;
++ gcmkHEADER_ARG("Os=0x%X Address=0x%X Data=%u", Os, Address, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ /* Write memory. */
++ if (access_ok(VERIFY_WRITE, Address, 4))
++ {
++ /* User address. */
++ if(put_user(Data, (gctUINT32*)Address))
++ {
++ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS);
++ }
++ }
++ else
++ {
++ /* Kernel address. */
++ *(gctUINT32 *)Address = Data;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapUserMemory
++**
++** Lock down a user buffer and return an DMA'able address to be used by the
++** hardware to access it.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to lock down.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to lock down.
++**
++** OUTPUT:
++**
++** gctPOINTER * Info
++** Pointer to variable receiving the information record required by
++** gckOS_UnmapUserMemory.
++**
++** gctUINT32_PTR Address
++** Pointer to a variable that will receive the address DMA'able by the
++** hardware.
++*/
++gceSTATUS
++gckOS_MapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctUINT32 Physical,
++ IN gctSIZE_T Size,
++ OUT gctPOINTER * Info,
++ OUT gctUINT32_PTR Address
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%x Core=%d Memory=0x%x Size=%lu", Os, Core, Memory, Size);
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckOS_AddMapping(Os, *Address, Memory, Size));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++#else
++{
++ gctSIZE_T pageCount, i, j;
++ gctUINT32_PTR pageTable;
++ gctUINT32 address = 0, physical = ~0U;
++ gctUINTPTR_T start, end, memory;
++ gctUINT32 offset;
++ gctINT result = 0;
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU mmu;
++#endif
++
++ gcsPageInfo_PTR info = gcvNULL;
++ struct page **pages = gcvNULL;
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL || Physical != ~0U);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Address != gcvNULL);
++
++ do
++ {
++ gctSIZE_T extraPage;
++
++ memory = (gctUINTPTR_T) Memory;
++
++ /* Get the number of required pages. */
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ /* Allocate extra 64 bytes to avoid cache overflow */
++ extraPage = (((memory + gcmALIGN(Size + 64, 64) + PAGE_SIZE - 1) >> PAGE_SHIFT) > end) ? 1 : 0;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageCount: %d.",
++ __FUNCTION__, __LINE__,
++ pageCount
++ );
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ MEMORY_MAP_LOCK(Os);
++
++ /* Allocate the Info struct. */
++ info = (gcsPageInfo_PTR)kmalloc(sizeof(gcsPageInfo), GFP_KERNEL | gcdNOWARN);
++
++ if (info == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ info->extraPage = 0;
++
++ /* Allocate the array of page addresses. */
++ pages = (struct page **)kmalloc((pageCount + extraPage) * sizeof(struct page *), GFP_KERNEL | gcdNOWARN);
++
++ if (pages == gcvNULL)
++ {
++ status = gcvSTATUS_OUT_OF_MEMORY;
++ break;
++ }
++
++ if (Physical != ~0U)
++ {
++ for (i = 0; i < pageCount; i++)
++ {
++ pages[i] = pfn_to_page((Physical >> PAGE_SHIFT) + i);
++
++ if (pfn_valid(page_to_pfn(pages[i])))
++ {
++ get_page(pages[i]);
++ }
++ }
++ }
++ else
++ {
++ /* Get the user pages. */
++ down_read(&current->mm->mmap_sem);
++
++ result = get_user_pages(current,
++ current->mm,
++ memory & PAGE_MASK,
++ pageCount,
++ 1,
++ 0,
++ pages,
++ gcvNULL
++ );
++
++ up_read(&current->mm->mmap_sem);
++
++ if (result <=0 || result < pageCount)
++ {
++ struct vm_area_struct *vma;
++
++ /* Release the pages if any. */
++ if (result > 0)
++ {
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] == gcvNULL)
++ {
++ break;
++ }
++
++ page_cache_release(pages[i]);
++ pages[i] = gcvNULL;
++ }
++
++ result = 0;
++ }
++
++ vma = find_vma(current->mm, memory);
++
++ if (vma && (vma->vm_flags & VM_PFNMAP))
++ {
++ pte_t * pte;
++ spinlock_t * ptl;
++ gctUINTPTR_T logical = memory;
++
++ for (i = 0; i < pageCount; i++)
++ {
++ pgd_t * pgd = pgd_offset(current->mm, logical);
++ pud_t * pud = pud_offset(pgd, logical);
++
++ if (pud)
++ {
++ pmd_t * pmd = pmd_offset(pud, logical);
++ pte = pte_offset_map_lock(current->mm, pmd, logical, &ptl);
++ if (!pte)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ pages[i] = pte_page(*pte);
++ pte_unmap_unlock(pte, ptl);
++
++ /* Advance to next. */
++ logical += PAGE_SIZE;
++ }
++ }
++ else
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Check if this memory is contiguous for old mmu. */
++ if (Os->device->kernels[Core]->hardware->mmuVersion == 0)
++ {
++ for (i = 1; i < pageCount; i++)
++ {
++ if (pages[i] != nth_page(pages[0], i))
++ {
++ /* Non-contiguous. */
++ break;
++ }
++ }
++
++ if (i == pageCount)
++ {
++ /* Contiguous memory. */
++ physical = page_to_phys(pages[0]) | (memory & ~PAGE_MASK);
++
++ if (!((physical - Os->device->baseAddress) & 0x80000000))
++ {
++ kfree(pages);
++ pages = gcvNULL;
++
++ info->pages = gcvNULL;
++ info->pageTable = gcvNULL;
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ *Address = physical - Os->device->baseAddress;
++ *Info = info;
++
++ gcmkVERIFY_OK(
++ gckOS_CPUPhysicalToGPUPhysical(Os, *Address, Address));
++
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x",
++ *Info, *Address);
++
++ return gcvSTATUS_OK;
++ }
++ }
++ }
++
++ /* Reference pages. */
++ for (i = 0; i < pageCount; i++)
++ {
++ if (pfn_valid(page_to_pfn(pages[i])))
++ {
++ get_page(pages[i]);
++ }
++ }
++ }
++ }
++
++ for (i = 0; i < pageCount; i++)
++ {
++#ifdef CONFIG_ARM
++ gctUINT32 data;
++ get_user(data, (gctUINT32*)((memory & PAGE_MASK) + i * PAGE_SIZE));
++#endif
++
++ /* Flush(clean) the data cache. */
++ gcmkONERROR(gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL,
++ page_to_phys(pages[i]),
++ (gctPOINTER)(memory & PAGE_MASK) + i*PAGE_SIZE,
++ PAGE_SIZE));
++ }
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkONERROR(gckKERNEL_GetProcessMMU(Os->device->kernels[Core], &mmu));
++#endif
++
++ if (extraPage)
++ {
++ pages[pageCount++] = Os->paddingPage;
++ info->extraPage = 1;
++ }
++
++#if gcdSECURITY
++ {
++ gctPHYS_ADDR physicalArrayPhysical;
++ gctPOINTER physicalArrayLogical;
++ gctUINT32_PTR logical;
++ gctSIZE_T bytes = pageCount * gcmSIZEOF(gctUINT32);
++ pageTable = gcvNULL;
++
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ Os,
++ gcvFALSE,
++ &bytes,
++ &physicalArrayPhysical,
++ &physicalArrayLogical
++ ));
++
++ logical = physicalArrayLogical;
++
++ /* Fill the page table. */
++ for (i = 0; i < pageCount; i++)
++ {
++ gctUINT32 phys;
++ phys = page_to_phys(pages[i]);
++
++ logical[i] = phys;
++ }
++ j = 0;
++
++
++ gcmkONERROR(gckKERNEL_SecurityMapMemory(
++ Os->device->kernels[Core],
++ physicalArrayLogical,
++ pageCount,
++ &address
++ ));
++
++ gcmkONERROR(gckOS_FreeNonPagedMemory(
++ Os,
++ 1,
++ physicalArrayPhysical,
++ physicalArrayLogical
++ ));
++ }
++
++#else
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckVGMMU_AllocatePages(Os->device->kernels[Core]->vg->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++ }
++ else
++#endif
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckMMU_AllocatePages(mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++#else
++ /* Allocate pages inside the page table. */
++ gcmkERR_BREAK(gckMMU_AllocatePages(Os->device->kernels[Core]->mmu,
++ pageCount * (PAGE_SIZE/4096),
++ (gctPOINTER *) &pageTable,
++ &address));
++#endif
++ }
++
++ /* Fill the page table. */
++ for (i = 0; i < pageCount; i++)
++ {
++ gctUINT32 phys;
++ gctUINT32_PTR tab = pageTable + i * (PAGE_SIZE/4096);
++
++#if gcdPROCESS_ADDRESS_SPACE
++ gckMMU_GetPageEntry(mmu, address + i * 4096, &tab);
++#endif
++ phys = page_to_phys(pages[i]);
++
++#ifdef CONFIG_IOMMU_SUPPORT
++ if (Os->iommu)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Setup mapping in IOMMU %x => %x",
++ __FUNCTION__, __LINE__,
++ Address + (i * PAGE_SIZE), phys
++ );
++
++ gcmkONERROR(gckIOMMU_Map(
++ Os->iommu, address + i * PAGE_SIZE, phys, PAGE_SIZE));
++ }
++ else
++#endif
++ {
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkVERIFY_OK(
++ gckOS_CPUPhysicalToGPUPhysical(Os, phys, &phys));
++
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu,
++ phys,
++ tab));
++ }
++ else
++#endif
++ {
++ /* Get the physical address from page struct. */
++ gcmkONERROR(
++ gckMMU_SetPage(Os->device->kernels[Core]->mmu,
++ phys,
++ tab));
++ }
++
++ for (j = 1; j < (PAGE_SIZE/4096); j++)
++ {
++ pageTable[i * (PAGE_SIZE/4096) + j] = pageTable[i * (PAGE_SIZE/4096)] + 4096 * j;
++ }
++ }
++
++#if !gcdPROCESS_ADDRESS_SPACE
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pageTable[%d]: 0x%X 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, phys, pageTable[i]);
++#endif
++ }
++
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ gcmkONERROR(gckVGMMU_Flush(Os->device->kernels[Core]->vg->mmu));
++ }
++ else
++#endif
++ {
++#if gcdPROCESS_ADDRESS_SPACE
++ info->mmu = mmu;
++ gcmkONERROR(gckMMU_Flush(mmu));
++#else
++ gcmkONERROR(gckMMU_Flush(Os->device->kernels[Core]->mmu, gcvSURF_TYPE_UNKNOWN));
++#endif
++ }
++#endif
++ info->address = address;
++
++ /* Save pointer to page table. */
++ info->pageTable = pageTable;
++ info->pages = pages;
++
++ *Info = (gctPOINTER) info;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info->pages: 0x%X, info->pageTable: 0x%X, info: 0x%X.",
++ __FUNCTION__, __LINE__,
++ info->pages,
++ info->pageTable,
++ info
++ );
++
++ offset = (Physical != ~0U)
++ ? (Physical & ~PAGE_MASK)
++ : (memory & ~PAGE_MASK);
++
++ /* Return address. */
++ *Address = address + offset;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): Address: 0x%X.",
++ __FUNCTION__, __LINE__,
++ *Address
++ );
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++OnError:
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error occured: %d.",
++ __FUNCTION__, __LINE__,
++ status
++ );
++
++ /* Release page array. */
++ if (result > 0 && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: page table is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ for (i = 0; i < result; i++)
++ {
++ if (pages[i] == gcvNULL)
++ {
++ break;
++ }
++ page_cache_release(pages[i]);
++ }
++ }
++
++ if (info!= gcvNULL && pages != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: pages is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page table. */
++ kfree(pages);
++ info->pages = gcvNULL;
++ }
++
++ /* Release page info struct. */
++ if (info != gcvNULL)
++ {
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): error: info is freed.",
++ __FUNCTION__, __LINE__
++ );
++
++ /* Free the page info struct. */
++ kfree(info);
++ *Info = gcvNULL;
++ }
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ if (gcmIS_SUCCESS(status))
++ {
++ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x", *Info, *Address);
++ }
++ else
++ {
++ gcmkFOOTER();
++ }
++
++ return status;
++}
++#endif
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapUserMemory
++**
++** Unlock a user buffer and that was previously locked down by
++** gckOS_MapUserMemory.
++**
++** INPUT:
++**
++** gctPOINTER Memory
++** Pointer to memory to unlock.
++**
++** gctSIZE_T Size
++** Size in bytes of the memory to unlock.
++**
++** gctPOINTER Info
++** Information record returned by gckOS_MapUserMemory.
++**
++** gctUINT32_PTR Address
++** The address returned by gckOS_MapUserMemory.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UnmapUserMemory(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Size,
++ IN gctPOINTER Info,
++ IN gctUINT32 Address
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Memory=0x%X Size=%lu Info=0x%X Address0x%08x",
++ Os, Core, Memory, Size, Info, Address);
++
++#if gcdSECURE_USER
++ gcmkONERROR(gckOS_RemoveMapping(Os, Memory, Size));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++#else
++{
++ gctUINTPTR_T memory, start, end;
++ gcsPageInfo_PTR info;
++ gctSIZE_T pageCount, i;
++ struct page **pages;
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Size > 0);
++ gcmkVERIFY_ARGUMENT(Info != gcvNULL);
++
++ do
++ {
++ info = (gcsPageInfo_PTR) Info;
++
++ pages = info->pages;
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): info=0x%X, pages=0x%X.",
++ __FUNCTION__, __LINE__,
++ info, pages
++ );
++
++ /* Invalid page array. */
++ if (pages == gcvNULL && info->pageTable == gcvNULL)
++ {
++ kfree(info);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++ memory = (gctUINTPTR_T)Memory;
++ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT;
++ start = memory >> PAGE_SHIFT;
++ pageCount = end - start;
++
++ /* Overflow. */
++ if ((memory + Size) < memory)
++ {
++ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT);
++ return gcvSTATUS_INVALID_ARGUMENT;
++ }
++
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): memory: 0x%X, pageCount: %d, pageTable: 0x%X.",
++ __FUNCTION__, __LINE__,
++ memory, pageCount, info->pageTable
++ );
++
++ MEMORY_MAP_LOCK(Os);
++
++#if !gcdSECURITY
++ gcmkASSERT(info->pageTable != gcvNULL);
++#endif
++
++ if (info->extraPage)
++ {
++ pageCount += 1;
++ }
++
++#if gcdSECURITY
++ if (info->address > 0x80000000)
++ {
++ gckKERNEL_SecurityUnmapMemory(
++ Os->device->kernels[Core],
++ info->address,
++ pageCount
++ );
++ }
++ else
++ {
++ gcmkPRINT("Wrong address %s(%d) %x", __FUNCTION__, __LINE__, info->address);
++ }
++#else
++#if gcdENABLE_VG
++ if (Core == gcvCORE_VG)
++ {
++ /* Free the pages from the MMU. */
++ gcmkERR_BREAK(gckVGMMU_FreePages(Os->device->kernels[Core]->vg->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++ }
++ else
++#endif
++ {
++ /* Free the pages from the MMU. */
++#if gcdPROCESS_ADDRESS_SPACE
++ gcmkERR_BREAK(gckMMU_FreePagesEx(info->mmu,
++ info->address,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++
++#else
++ gcmkERR_BREAK(gckMMU_FreePages(Os->device->kernels[Core]->mmu,
++ info->pageTable,
++ pageCount * (PAGE_SIZE/4096)
++ ));
++#endif
++
++ gcmkERR_BREAK(gckOS_UnmapPages(
++ Os,
++ pageCount * (PAGE_SIZE/4096),
++ info->address
++ ));
++ }
++#endif
++
++ if (info->extraPage)
++ {
++ pageCount -= 1;
++ info->extraPage = 0;
++ }
++
++ /* Release the page cache. */
++ if (pages)
++ {
++ for (i = 0; i < pageCount; i++)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): pages[%d]: 0x%X.",
++ __FUNCTION__, __LINE__,
++ i, pages[i]
++ );
++
++ if (!PageReserved(pages[i]))
++ {
++ SetPageDirty(pages[i]);
++ }
++
++ if (pfn_valid(page_to_pfn(pages[i])))
++ {
++ page_cache_release(pages[i]);
++ }
++ }
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ if (info != gcvNULL)
++ {
++ /* Free the page array. */
++ if (info->pages != gcvNULL)
++ {
++ kfree(info->pages);
++ }
++
++ kfree(info);
++ }
++
++ MEMORY_MAP_UNLOCK(Os);
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++}
++
++/*******************************************************************************
++**
++** gckOS_GetBaseAddress
++**
++** Get the base address for the physical memory.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR BaseAddress
++** Pointer to a variable that will receive the base address.
++*/
++gceSTATUS
++gckOS_GetBaseAddress(
++ IN gckOS Os,
++ OUT gctUINT32_PTR BaseAddress
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL);
++
++ /* Return base address. */
++ *BaseAddress = Os->device->baseAddress;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress);
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_SuspendInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_SuspendInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ if (Core == gcvCORE_MAJOR)
++ {
++ disable_irq(Os->device->irqLine3D[gcvCORE_3D_0_ID]);
++ disable_irq(Os->device->irqLine3D[gcvCORE_3D_1_ID]);
++ }
++ else
++ {
++ disable_irq(Os->device->irqLines[Core]);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#else
++gceSTATUS
++gckOS_SuspendInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ disable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckOS_ResumeInterrupt(
++ IN gckOS Os
++ )
++{
++ return gckOS_ResumeInterruptEx(Os, gcvCORE_MAJOR);
++}
++
++#if gcdMULTI_GPU
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ if (Core == gcvCORE_MAJOR)
++ {
++ enable_irq(Os->device->irqLine3D[gcvCORE_3D_0_ID]);
++ enable_irq(Os->device->irqLine3D[gcvCORE_3D_1_ID]);
++ }
++ else
++ {
++ enable_irq(Os->device->irqLines[Core]);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#else
++gceSTATUS
++gckOS_ResumeInterruptEx(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ enable_irq(Os->device->irqLines[Core]);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++#endif
++
++gceSTATUS
++gckOS_MemCopy(
++ IN gctPOINTER Destination,
++ IN gctCONST_POINTER Source,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Destination=0x%X Source=0x%X Bytes=%lu",
++ Destination, Source, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Destination != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Source != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memcpy(Destination, Source, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_ZeroMemory(
++ IN gctPOINTER Memory,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcmkHEADER_ARG("Memory=0x%X Bytes=%lu", Memory, Bytes);
++
++ gcmkVERIFY_ARGUMENT(Memory != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ memset(Memory, 0, Bytes);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Cache Control ********************************
++*******************************************************************************/
++
++/*******************************************************************************
++** gckOS_CacheClean
++**
++** Clean the cache for the specified addresses. The GPU is going to need the
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Physical
++** Physical address to flush.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheClean(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->cache)
++ {
++ platform->ops->cache(
++ platform,
++ ProcessID,
++ Handle,
++ Physical,
++ Logical,
++ Bytes,
++ gcvCACHE_CLEAN
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++
++ /* Inner cache. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
++ dmac_map_area(Logical, Bytes, DMA_TO_DEVICE);
++# else
++ dmac_clean_range(Logical, Logical + Bytes);
++# endif
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, Physical, Logical, Bytes, gcvCACHE_CLEAN);
++#else
++ outer_clean_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++
++ dma_cache_wback((unsigned long) Logical, Bytes);
++
++#elif defined(CONFIG_PPC)
++
++ /* TODO */
++
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_TO_DEVICE);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheInvalidate
++**
++** Invalidate the cache for the specified addresses. The GPU is going to need
++** data. If the system is allocating memory as non-cachable, this function can
++** be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheInvalidate(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->cache)
++ {
++ platform->ops->cache(
++ platform,
++ ProcessID,
++ Handle,
++ Physical,
++ Logical,
++ Bytes,
++ gcvCACHE_INVALIDATE
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++
++ /* Inner cache. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)
++ dmac_map_area(Logical, Bytes, DMA_FROM_DEVICE);
++# else
++ dmac_inv_range(Logical, Logical + Bytes);
++# endif
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, Physical, Logical, Bytes, gcvCACHE_INVALIDATE);
++#else
++ outer_inv_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++ dma_cache_inv((unsigned long) Logical, Bytes);
++#elif defined(CONFIG_PPC)
++ /* TODO */
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_FROM_DEVICE);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++** gckOS_CacheFlush
++**
++** Clean the cache for the specified addresses and invalidate the lines as
++** well. The GPU is going to need and modify the data. If the system is
++** allocating memory as non-cachable, this function can be ignored.
++**
++** ARGUMENTS:
++**
++** gckOS Os
++** Pointer to gckOS object.
++**
++** gctUINT32 ProcessID
++** Process ID Logical belongs.
++**
++** gctPHYS_ADDR Handle
++** Physical address handle. If gcvNULL it is video memory.
++**
++** gctPOINTER Logical
++** Logical address to flush.
++**
++** gctSIZE_T Bytes
++** Size of the address range in bytes to flush.
++*/
++gceSTATUS
++gckOS_CacheFlush(
++ IN gckOS Os,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes
++ )
++{
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu",
++ Os, ProcessID, Handle, Logical, Bytes);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Logical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Bytes > 0);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->cache)
++ {
++ platform->ops->cache(
++ platform,
++ ProcessID,
++ Handle,
++ Physical,
++ Logical,
++ Bytes,
++ gcvCACHE_FLUSH
++ );
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++ }
++
++#if !gcdCACHE_FUNCTION_UNIMPLEMENTED
++#ifdef CONFIG_ARM
++ /* Inner cache. */
++ dmac_flush_range(Logical, Logical + Bytes);
++
++#if defined(CONFIG_OUTER_CACHE)
++ /* Outer cache. */
++#if gcdENABLE_OUTER_CACHE_PATCH
++ _HandleOuterCache(Os, Physical, Logical, Bytes, gcvCACHE_FLUSH);
++#else
++ outer_flush_range((unsigned long) Handle, (unsigned long) Handle + Bytes);
++#endif
++#endif
++
++#elif defined(CONFIG_MIPS)
++ dma_cache_wback_inv((unsigned long) Logical, Bytes);
++#elif defined(CONFIG_PPC)
++ /* TODO */
++#else
++ dma_sync_single_for_device(
++ gcvNULL,
++ (dma_addr_t)Physical,
++ Bytes,
++ DMA_BIDIRECTIONAL);
++#endif
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************* Broadcasting *********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_Broadcast
++**
++** System hook for broadcast events from the kernel driver.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gceBROADCAST Reason
++** Reason for the broadcast. Can be one of the following values:
++**
++** gcvBROADCAST_GPU_IDLE
++** Broadcasted when the kernel driver thinks the GPU might be
++** idle. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_COMMIT
++** Broadcasted when any client process commits a command
++** buffer. This can be used to handle power management.
++**
++** gcvBROADCAST_GPU_STUCK
++** Broadcasted when the kernel driver hits the timeout waiting
++** for the GPU.
++**
++** gcvBROADCAST_FIRST_PROCESS
++** First process is trying to connect to the kernel.
++**
++** gcvBROADCAST_LAST_PROCESS
++** Last process has detached from the kernel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Broadcast(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gceBROADCAST Reason
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Hardware=0x%X Reason=%d", Os, Hardware, Reason);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE);
++
++ switch (Reason)
++ {
++ case gcvBROADCAST_FIRST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "First process has attached");
++ break;
++
++ case gcvBROADCAST_LAST_PROCESS:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "Last process has detached");
++
++ /* Put GPU OFF. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++ gcvPOWER_OFF_BROADCAST));
++ break;
++
++ case gcvBROADCAST_GPU_IDLE:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "GPU idle.");
++
++ /* Put GPU IDLE. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware,
++#if gcdPOWER_SUSPEND_WHEN_IDLE
++ gcvPOWER_SUSPEND_BROADCAST));
++#else
++ gcvPOWER_IDLE_BROADCAST));
++#endif
++
++ /* Add idle process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 1,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++ break;
++
++ case gcvBROADCAST_GPU_COMMIT:
++ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "COMMIT has arrived.");
++
++ /* Add busy process DB. */
++ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel,
++ 0,
++ gcvDB_IDLE,
++ gcvNULL, gcvNULL, 0));
++
++ /* Put GPU ON. */
++ gcmkONERROR(
++ gckHARDWARE_SetPowerManagementState(Hardware, gcvPOWER_ON_AUTO));
++ break;
++
++ case gcvBROADCAST_GPU_STUCK:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_GPU_STUCK\n");
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++
++ case gcvBROADCAST_AXI_BUS_ERROR:
++ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_AXI_BUS_ERROR\n");
++ gcmkONERROR(gckHARDWARE_DumpGPUState(Hardware));
++ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel));
++ break;
++
++ case gcvBROADCAST_OUT_OF_MEMORY:
++ gcmkTRACE_N(gcvLEVEL_INFO, 0, "gcvBROADCAST_OUT_OF_MEMORY\n");
++
++ status = _ShrinkMemory(Os);
++
++ if (status == gcvSTATUS_NOT_SUPPORTED)
++ {
++ goto OnError;
++ }
++
++ gcmkONERROR(status);
++
++ break;
++
++ default:
++ /* Skip unimplemented broadcast. */
++ break;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastHurry
++**
++** The GPU is running too slow.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Urgency
++** The higher the number, the higher the urgency to speed up the GPU.
++** The maximum value is defined by the gcdDYNAMIC_EVENT_THRESHOLD.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastHurry(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Urgency
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Urgency=%u", Os, Hardware, Urgency);
++
++ /* Do whatever you need to do to speed up the GPU now. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_BroadcastCalibrateSpeed
++**
++** Calibrate the speed of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gckHARDWARE Hardware
++** Pointer to the gckHARDWARE object.
++**
++** gctUINT Idle, Time
++** Idle/Time will give the percentage the GPU is idle, so you can use
++** this to calibrate the working point of the GPU.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_BroadcastCalibrateSpeed(
++ IN gckOS Os,
++ IN gckHARDWARE Hardware,
++ IN gctUINT Idle,
++ IN gctUINT Time
++ )
++{
++ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Idle=%u Time=%u",
++ Os, Hardware, Idle, Time);
++
++ /* Do whatever you need to do to callibrate the GPU speed. */
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++********************************** Semaphores **********************************
++*******************************************************************************/
++
++/*******************************************************************************
++**
++** gckOS_CreateSemaphore
++**
++** Create a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** OUTPUT:
++**
++** gctPOINTER * Semaphore
++** Pointer to the variable that will receive the created semaphore.
++*/
++gceSTATUS
++gckOS_CreateSemaphore(
++ IN gckOS Os,
++ OUT gctPOINTER * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore *sem = gcvNULL;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Allocate the semaphore structure. */
++ sem = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (sem == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(sem, 1);
++
++ /* Return to caller. */
++ *Semaphore = (gctPOINTER) sem;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_AcquireSemaphore
++**
++** Acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_AcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%08X Semaphore=0x%08X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_interruptible((struct semaphore *) Semaphore))
++ {
++ gcmkONERROR(gcvSTATUS_INTERRUPTED);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_TryAcquireSemaphore
++**
++** Try to acquire a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be acquired.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_TryAcquireSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%x", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Acquire the semaphore. */
++ if (down_trylock((struct semaphore *) Semaphore))
++ {
++ /* Timeout. */
++ status = gcvSTATUS_TIMEOUT;
++ gcmkFOOTER();
++ return status;
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ReleaseSemaphore
++**
++** Release a previously acquired semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be released.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ReleaseSemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Release the semaphore. */
++ up((struct semaphore *) Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySemaphore
++**
++** Destroy a semaphore.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Semaphore
++** Pointer to the semaphore thet needs to be destroyed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroySemaphore(
++ IN gckOS Os,
++ IN gctPOINTER Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Free the sempahore structure. */
++ kfree(Semaphore);
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetProcessID
++**
++** Get current process ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ProcessID
++** Pointer to the variable that receives the process ID.
++*/
++gceSTATUS
++gckOS_GetProcessID(
++ OUT gctUINT32_PTR ProcessID
++ )
++{
++ /* Get process ID. */
++ if (ProcessID != gcvNULL)
++ {
++ *ProcessID = _GetProcessID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_GetThreadID
++**
++** Get current thread ID.
++**
++** INPUT:
++**
++** Nothing.
++**
++** OUTPUT:
++**
++** gctUINT32_PTR ThreadID
++** Pointer to the variable that receives the thread ID.
++*/
++gceSTATUS
++gckOS_GetThreadID(
++ OUT gctUINT32_PTR ThreadID
++ )
++{
++ /* Get thread ID. */
++ if (ThreadID != gcvNULL)
++ {
++ *ThreadID = _GetThreadID();
++ }
++
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUPower
++**
++** Set the power of the GPU on or off.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gceCORE Core
++** GPU whose power is set.
++**
++** gctBOOL Clock
++** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock.
++**
++** gctBOOL Power
++** gcvTRUE to turn on the power, or gcvFALSE to turn off the power.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUPower(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctBOOL Clock,
++ IN gctBOOL Power
++ )
++{
++ gcsPLATFORM * platform;
++
++ gctBOOL powerChange = gcvFALSE;
++ gctBOOL clockChange = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d Clock=%d Power=%d", Os, Core, Clock, Power);
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ platform = Os->device->platform;
++
++ powerChange = (Power != Os->powerStates[Core]);
++
++ clockChange = (Clock != Os->clockStates[Core]);
++
++ if (powerChange && (Power == gcvTRUE))
++ {
++ if (platform && platform->ops->setPower)
++ {
++ gcmkVERIFY_OK(platform->ops->setPower(platform, Core, Power));
++ }
++
++ Os->powerStates[Core] = Power;
++ }
++
++ if (clockChange)
++ {
++ mutex_lock(&Os->registerAccessLocks[Core]);
++
++ if (platform && platform->ops->setClock)
++ {
++ gcmkVERIFY_OK(platform->ops->setClock(platform, Core, Clock));
++ }
++
++ Os->clockStates[Core] = Clock;
++
++ mutex_unlock(&Os->registerAccessLocks[Core]);
++ }
++
++ if (powerChange && (Power == gcvFALSE))
++ {
++ if (platform && platform->ops->setPower)
++ {
++ gcmkVERIFY_OK(platform->ops->setPower(platform, Core, Power));
++ }
++
++ Os->powerStates[Core] = Power;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_ResetGPU
++**
++** Reset the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_ResetGPU(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED;
++ gcsPLATFORM * platform;
++
++ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core);
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->reset)
++ {
++ status = platform->ops->reset(platform, Core);
++ }
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_PrepareGPUFrequency
++**
++** Prepare to set GPU frequency and voltage.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage will be set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_PrepareGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_FinishGPUFrequency
++**
++** Finish GPU frequency setting.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose frequency and voltage is set.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_FinishGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_QueryGPUFrequency
++**
++** Query the current frequency of the GPU.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT32 * Frequency
++** Pointer to a gctUINT32 to obtain current frequency, in MHz.
++**
++** gctUINT8 * Scale
++** Pointer to a gctUINT8 to obtain current scale(1 - 64).
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_QueryGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ OUT gctUINT32 * Frequency,
++ OUT gctUINT8 * Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetGPUFrequency
++**
++** Set frequency and voltage of the GPU.
++**
++** 1. DVFS manager gives the target scale of full frequency, BSP must find
++** a real frequency according to this scale and board's configure.
++**
++** 2. BSP should find a suitable voltage for this frequency.
++**
++** 3. BSP must make sure setting take effect before this function returns.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to a gckOS object.
++**
++** gckCORE Core
++** GPU whose power is set.
++**
++** gctUINT8 Scale
++** Target scale of full frequency, range is [1, 64]. 1 means 1/64 of
++** full frequency and 64 means 64/64 of full frequency.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetGPUFrequency(
++ IN gckOS Os,
++ IN gceCORE Core,
++ IN gctUINT8 Scale
++ )
++{
++ return gcvSTATUS_OK;
++}
++
++/*----------------------------------------------------------------------------*/
++/*----- Profile --------------------------------------------------------------*/
++
++gceSTATUS
++gckOS_GetProfileTick(
++ OUT gctUINT64_PTR Tick
++ )
++{
++ struct timespec time;
++
++ ktime_get_ts(&time);
++
++ *Tick = time.tv_nsec + time.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_QueryProfileTickRate(
++ OUT gctUINT64_PTR TickRate
++ )
++{
++ struct timespec res;
++
++ hrtimer_get_res(CLOCK_MONOTONIC, &res);
++
++ *TickRate = res.tv_nsec + res.tv_sec * 1000000000ULL;
++
++ return gcvSTATUS_OK;
++}
++
++gctUINT32
++gckOS_ProfileToMS(
++ IN gctUINT64 Ticks
++ )
++{
++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23)
++ return div_u64(Ticks, 1000000);
++#else
++ gctUINT64 rem = Ticks;
++ gctUINT64 b = 1000000;
++ gctUINT64 res, d = 1;
++ gctUINT32 high = rem >> 32;
++
++ /* Reduce the thing a bit first */
++ res = 0;
++ if (high >= 1000000)
++ {
++ high /= 1000000;
++ res = (gctUINT64) high << 32;
++ rem -= (gctUINT64) (high * 1000000) << 32;
++ }
++
++ while (((gctINT64) b > 0) && (b < rem))
++ {
++ b <<= 1;
++ d <<= 1;
++ }
++
++ do
++ {
++ if (rem >= b)
++ {
++ rem -= b;
++ res += d;
++ }
++
++ b >>= 1;
++ d >>= 1;
++ }
++ while (d);
++
++ return (gctUINT32) res;
++#endif
++}
++
++/******************************************************************************\
++******************************* Signal Management ******************************
++\******************************************************************************/
++
++#undef _GC_OBJ_ZONE
++#define _GC_OBJ_ZONE gcvZONE_SIGNAL
++
++/*******************************************************************************
++**
++** gckOS_CreateSignal
++**
++** Create a new signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctSIGNAL * Signal
++** Pointer to a variable receiving the created gctSIGNAL.
++*/
++gceSTATUS
++gckOS_CreateSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctSIGNAL * Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X ManualReset=%d", Os, ManualReset);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ /* Create an event structure. */
++ signal = (gcsSIGNAL_PTR) kmalloc(sizeof(gcsSIGNAL), GFP_KERNEL | gcdNOWARN);
++
++ if (signal == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Save the process ID. */
++ signal->process = (gctHANDLE)(gctUINTPTR_T) _GetProcessID();
++ signal->manualReset = ManualReset;
++ signal->hardware = gcvNULL;
++ init_completion(&signal->obj);
++ atomic_set(&signal->ref, 1);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->signalDB, signal, &signal->id));
++
++ *Signal = (gctSIGNAL)(gctUINTPTR_T)signal->id;
++
++ gcmkFOOTER_ARG("*Signal=0x%X", *Signal);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (signal != gcvNULL)
++ {
++ kfree(signal);
++ }
++
++ gcmkFOOTER_NO();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalQueryHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ OUT gckHARDWARE * Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ *Hardware = signal->hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSetHardware(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gckHARDWARE Hardware
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ signal->hardware = Hardware;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroySignal
++**
++** Destroy a signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroySignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X", Os, Signal);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (atomic_dec_and_test(&signal->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->signalDB, signal->id));
++
++ /* Free the sgianl. */
++ kfree(signal);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_Signal
++**
++** Set a state of the specified signal.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_Signal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctBOOL State
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X State=%d", Os, Signal, State);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ if (State)
++ {
++ /* unbind the signal from hardware. */
++ signal->hardware = gcvNULL;
++
++ /* Set the event to a signaled state. */
++ complete(&signal->obj);
++ }
++ else
++ {
++ /* Set the event to an unsignaled state. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,13,0)
++ reinit_completion(&signal->obj);
++#else
++ INIT_COMPLETION(signal->obj);
++#endif
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_SetSignalVG(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ printk("gckOS_SetSignalVG:0x%x\n", result);
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++#endif
++
++/*******************************************************************************
++**
++** gckOS_UserSignal
++**
++** Set the specified signal which is owned by a process to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_UserSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process
++ )
++{
++ gceSTATUS status;
++ gctSIGNAL signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=%d",
++ Os, Signal, (gctINT32)(gctUINTPTR_T)Process);
++
++ /* Map the signal into kernel space. */
++ gcmkONERROR(gckOS_MapSignal(Os, Signal, Process, &signal));
++
++ /* Signal. */
++ status = gckOS_Signal(Os, signal, gcvTRUE);
++
++ /* Unmap the signal */
++ gcmkVERIFY_OK(gckOS_UnmapSignal(Os, Signal));
++
++ gcmkFOOTER();
++ return status;
++
++OnError:
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitSignal
++**
++** Wait for a signal to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctUINT32 Wait
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsSIGNAL_PTR signal;
++
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Wait=0x%08X", Os, Signal, Wait);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal);
++
++ might_sleep();
++
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ }
++ else if (Wait == 0)
++ {
++ status = gcvSTATUS_TIMEOUT;
++ }
++ else
++ {
++ /* Convert wait to milliseconds. */
++ long timeout = (Wait == gcvINFINITE)
++ ? MAX_SCHEDULE_TIMEOUT
++ : Wait * HZ / 1000;
++
++ DECLARE_WAITQUEUE(wait, current);
++ wait.flags |= WQ_FLAG_EXCLUSIVE;
++ __add_wait_queue_tail(&signal->obj.wait, &wait);
++
++ while (gcvTRUE)
++ {
++ if (signal_pending(current))
++ {
++ /* Interrupt received. */
++ status = gcvSTATUS_INTERRUPTED;
++ break;
++ }
++
++ __set_current_state(TASK_INTERRUPTIBLE);
++ spin_unlock_irq(&signal->obj.wait.lock);
++ timeout = schedule_timeout(timeout);
++ spin_lock_irq(&signal->obj.wait.lock);
++
++ if (signal->obj.done)
++ {
++ if (!signal->manualReset)
++ {
++ signal->obj.done = 0;
++ }
++
++ status = gcvSTATUS_OK;
++ break;
++ }
++
++ if (timeout == 0)
++ {
++
++ status = gcvSTATUS_TIMEOUT;
++ break;
++ }
++ }
++
++ __remove_wait_queue(&signal->obj.wait, &wait);
++ }
++
++ spin_unlock_irq(&signal->obj.wait.lock);
++
++OnError:
++ /* Return status. */
++ gcmkFOOTER_ARG("Signal=0x%X status=%d", Signal, status);
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_MapSignal
++**
++** Map a signal in to the current process space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to tha gctSIGNAL to map.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** OUTPUT:
++**
++** gctSIGNAL * MappedSignal
++** Pointer to a variable receiving the mapped gctSIGNAL.
++*/
++gceSTATUS
++gckOS_MapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal,
++ IN gctHANDLE Process,
++ OUT gctSIGNAL * MappedSignal
++ )
++{
++ gceSTATUS status;
++ gcsSIGNAL_PTR signal;
++ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=0x%X", Os, Signal, Process);
++
++ gcmkVERIFY_ARGUMENT(Signal != gcvNULL);
++ gcmkVERIFY_ARGUMENT(MappedSignal != gcvNULL);
++
++ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal));
++
++ if(atomic_inc_return(&signal->ref) <= 1)
++ {
++ /* The previous value is 0, it has been deleted. */
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ *MappedSignal = (gctSIGNAL) Signal;
++
++ /* Success. */
++ gcmkFOOTER_ARG("*MappedSignal=0x%X", *MappedSignal);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER_NO();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_UnmapSignal
++**
++** Unmap a signal .
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctSIGNAL Signal
++** Pointer to that gctSIGNAL mapped.
++*/
++gceSTATUS
++gckOS_UnmapSignal(
++ IN gckOS Os,
++ IN gctSIGNAL Signal
++ )
++{
++ return gckOS_DestroySignal(Os, Signal);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateUserSignal
++**
++** Create a new signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctBOOL ManualReset
++** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in
++** order to set the signal to nonsignaled state.
++** If set to gcvFALSE, the signal will automatically be set to
++** nonsignaled state by gckOS_WaitSignal function.
++**
++** OUTPUT:
++**
++** gctINT * SignalID
++** Pointer to a variable receiving the created signal's ID.
++*/
++gceSTATUS
++gckOS_CreateUserSignal(
++ IN gckOS Os,
++ IN gctBOOL ManualReset,
++ OUT gctINT * SignalID
++ )
++{
++ gceSTATUS status;
++ gctSIZE_T signal;
++
++ /* Create a new signal. */
++ gcmkONERROR(gckOS_CreateSignal(Os, ManualReset, (gctSIGNAL *) &signal));
++ *SignalID = (gctINT) signal;
++
++OnError:
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyUserSignal
++**
++** Destroy a signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** The signal's ID.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID
++ )
++{
++ return gckOS_DestroySignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID);
++}
++
++/*******************************************************************************
++**
++** gckOS_WaitUserSignal
++**
++** Wait for a signal used in the user mode to become signaled.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** Signal ID.
++**
++** gctUINT32 Wait
++** Number of milliseconds to wait.
++** Pass the value of gcvINFINITE for an infinite wait.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_WaitUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctUINT32 Wait
++ )
++{
++ return gckOS_WaitSignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, Wait);
++}
++
++/*******************************************************************************
++**
++** gckOS_SignalUserSignal
++**
++** Set a state of the specified signal to be used in the user space.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to an gckOS object.
++**
++** gctINT SignalID
++** SignalID.
++**
++** gctBOOL State
++** If gcvTRUE, the signal will be set to signaled state.
++** If gcvFALSE, the signal will be set to nonsignaled state.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SignalUserSignal(
++ IN gckOS Os,
++ IN gctINT SignalID,
++ IN gctBOOL State
++ )
++{
++ return gckOS_Signal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, State);
++}
++
++#if gcdENABLE_VG
++gceSTATUS
++gckOS_CreateSemaphoreVG(
++ IN gckOS Os,
++ OUT gctSEMAPHORE * Semaphore
++ )
++{
++ gceSTATUS status;
++ struct semaphore * newSemaphore;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Allocate the semaphore structure. */
++ newSemaphore = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN);
++ if (newSemaphore == gcvNULL)
++ {
++ gcmkERR_BREAK(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the semaphore. */
++ sema_init(newSemaphore, 0);
++
++ /* Set the handle. */
++ * Semaphore = (gctSEMAPHORE) newSemaphore;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++
++gceSTATUS
++gckOS_IncrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ /* Increment the semaphore's count. */
++ up((struct semaphore *) Semaphore);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DecrementSemaphore(
++ IN gckOS Os,
++ IN gctSEMAPHORE Semaphore
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++
++ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL);
++
++ do
++ {
++ /* Decrement the semaphore's count. If the count is zero, wait
++ until it gets incremented. */
++ result = down_interruptible((struct semaphore *) Semaphore);
++
++ /* Signal received? */
++ if (result != 0)
++ {
++ status = gcvSTATUS_TERMINATE;
++ break;
++ }
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_SetSignal
++**
++** Set the specified signal to signaled state.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctHANDLE Process
++** Handle of process owning the signal.
++**
++** gctSIGNAL Signal
++** Pointer to the gctSIGNAL.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_SetSignal(
++ IN gckOS Os,
++ IN gctHANDLE Process,
++ IN gctSIGNAL Signal
++ )
++{
++ gceSTATUS status;
++ gctINT result;
++ struct task_struct * userTask;
++ struct siginfo info;
++
++ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process);
++
++ if (userTask != gcvNULL)
++ {
++ info.si_signo = 48;
++ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL);
++ info.si_pid = 0;
++ info.si_uid = 0;
++ info.si_ptr = (gctPOINTER) Signal;
++
++ /* Signals with numbers between 32 and 63 are real-time,
++ send a real-time signal to the user process. */
++ result = send_sig_info(48, &info, userTask);
++
++ /* Error? */
++ if (result < 0)
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++ else
++ {
++ status = gcvSTATUS_OK;
++ }
++ }
++ else
++ {
++ status = gcvSTATUS_GENERIC_IO;
++
++ gcmkTRACE(
++ gcvLEVEL_ERROR,
++ "%s(%d): an error has occurred.\n",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ /* Return status. */
++ return status;
++}
++
++/******************************************************************************\
++******************************** Thread Object *********************************
++\******************************************************************************/
++
++gceSTATUS
++gckOS_StartThread(
++ IN gckOS Os,
++ IN gctTHREADFUNC ThreadFunction,
++ IN gctPOINTER ThreadParameter,
++ OUT gctTHREAD * Thread
++ )
++{
++ gceSTATUS status;
++ struct task_struct * thread;
++
++ gcmkHEADER_ARG("Os=0x%X ", Os);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(ThreadFunction != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ do
++ {
++ /* Create the thread. */
++ thread = kthread_create(
++ ThreadFunction,
++ ThreadParameter,
++ "Vivante Kernel Thread"
++ );
++
++ /* Failed? */
++ if (IS_ERR(thread))
++ {
++ status = gcvSTATUS_GENERIC_IO;
++ break;
++ }
++
++ /* Start the thread. */
++ wake_up_process(thread);
++
++ /* Set the thread handle. */
++ * Thread = (gctTHREAD) thread;
++
++ /* Success. */
++ status = gcvSTATUS_OK;
++ }
++ while (gcvFALSE);
++
++ gcmkFOOTER();
++ /* Return the status. */
++ return status;
++}
++
++gceSTATUS
++gckOS_StopThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ /* Thread should have already been enabled to terminate. */
++ kthread_stop((struct task_struct *) Thread);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_VerifyThread(
++ IN gckOS Os,
++ IN gctTHREAD Thread
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread);
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Thread != gcvNULL);
++
++ gcmkFOOTER_NO();
++ /* Success. */
++ return gcvSTATUS_OK;
++}
++#endif
++
++/******************************************************************************\
++******************************** Software Timer ********************************
++\******************************************************************************/
++
++void
++_TimerFunction(
++ struct work_struct * work
++ )
++{
++ gcsOSTIMER_PTR timer = (gcsOSTIMER_PTR)work;
++
++ gctTIMERFUNCTION function = timer->function;
++
++ function(timer->data);
++}
++
++/*******************************************************************************
++**
++** gckOS_CreateTimer
++**
++** Create a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctTIMERFUNCTION Function.
++** Pointer to a call back function which will be called when timer is
++** expired.
++**
++** gctPOINTER Data.
++** Private data which will be passed to call back function.
++**
++** OUTPUT:
++**
++** gctPOINTER * Timer
++** Pointer to a variable receiving the created timer.
++*/
++gceSTATUS
++gckOS_CreateTimer(
++ IN gckOS Os,
++ IN gctTIMERFUNCTION Function,
++ IN gctPOINTER Data,
++ OUT gctPOINTER * Timer
++ )
++{
++ gceSTATUS status;
++ gcsOSTIMER_PTR pointer;
++ gcmkHEADER_ARG("Os=0x%X Function=0x%X Data=0x%X", Os, Function, Data);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ gcmkONERROR(gckOS_Allocate(Os, sizeof(gcsOSTIMER), (gctPOINTER)&pointer));
++
++ pointer->function = Function;
++ pointer->data = Data;
++
++ INIT_DELAYED_WORK(&pointer->work, _TimerFunction);
++
++ *Timer = pointer;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++/*******************************************************************************
++**
++** gckOS_DestroyTimer
++**
++** Destory a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be destoryed.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_DestroyTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)
++ cancel_delayed_work_sync(&timer->work);
++#else
++ cancel_delayed_work(&timer->work);
++ flush_workqueue(Os->workqueue);
++#endif
++
++ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, Timer));
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StartTimer
++**
++** Schedule a software timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be scheduled.
++**
++** gctUINT32 Delay
++** Delay in milliseconds.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StartTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer,
++ IN gctUINT32 Delay
++ )
++{
++ gcsOSTIMER_PTR timer;
++
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X Delay=%u", Os, Timer, Delay);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++ gcmkVERIFY_ARGUMENT(Delay != 0);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)
++ mod_delayed_work(Os->workqueue, &timer->work, msecs_to_jiffies(Delay));
++#else
++ if (unlikely(delayed_work_pending(&timer->work)))
++ {
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)
++ cancel_delayed_work_sync(&timer->work);
++#else
++ cancel_delayed_work(&timer->work);
++ flush_workqueue(Os->workqueue);
++#endif
++ }
++
++ queue_delayed_work(Os->workqueue, &timer->work, msecs_to_jiffies(Delay));
++#endif
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_StopTimer
++**
++** Cancel a unscheduled timer.
++**
++** INPUT:
++**
++** gckOS Os
++** Pointer to the gckOS object.
++**
++** gctPOINTER Timer
++** Pointer to the timer to be cancel.
++**
++** OUTPUT:
++**
++** Nothing.
++*/
++gceSTATUS
++gckOS_StopTimer(
++ IN gckOS Os,
++ IN gctPOINTER Timer
++ )
++{
++ gcsOSTIMER_PTR timer;
++ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Timer != gcvNULL);
++
++ timer = (gcsOSTIMER_PTR)Timer;
++
++ cancel_delayed_work(&timer->work);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_GetProcessNameByPid(
++ IN gctINT Pid,
++ IN gctSIZE_T Length,
++ OUT gctUINT8_PTR String
++ )
++{
++ struct task_struct *task;
++
++ /* Get the task_struct of the task with pid. */
++ rcu_read_lock();
++
++ task = FIND_TASK_BY_PID(Pid);
++
++ if (task == gcvNULL)
++ {
++ rcu_read_unlock();
++ return gcvSTATUS_NOT_FOUND;
++ }
++
++ /* Get name of process. */
++ strncpy(String, task->comm, Length);
++
++ rcu_read_unlock();
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DumpCallStack(
++ IN gckOS Os
++ )
++{
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ dump_stack();
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++/*******************************************************************************
++**
++** gckOS_DetectProcessByName
++**
++** task->comm maybe part of process name, so this function
++** can only be used for debugging.
++**
++** INPUT:
++**
++** gctCONST_POINTER Name
++** Pointer to a string to hold name to be check. If the length
++** of name is longer than TASK_COMM_LEN (16), use part of name
++** to detect.
++**
++** OUTPUT:
++**
++** gcvSTATUS_TRUE if name of current process matches Name.
++**
++*/
++gceSTATUS
++gckOS_DetectProcessByName(
++ IN gctCONST_POINTER Name
++ )
++{
++ char comm[sizeof(current->comm)];
++
++ memset(comm, 0, sizeof(comm));
++
++ gcmkVERIFY_OK(
++ gckOS_GetProcessNameByPid(_GetProcessID(), sizeof(current->comm), comm));
++
++ return strstr(comm, Name) ? gcvSTATUS_TRUE
++ : gcvSTATUS_FALSE;
++}
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++gceSTATUS
++gckOS_CreateSyncPoint(
++ IN gckOS Os,
++ OUT gctSYNC_POINT * SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++
++ /* Create an sync point structure. */
++ syncPoint = (gcsSYNC_POINT_PTR) kmalloc(
++ sizeof(gcsSYNC_POINT), GFP_KERNEL | gcdNOWARN);
++
++ if (syncPoint == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Initialize the sync point. */
++ atomic_set(&syncPoint->ref, 1);
++ atomic_set(&syncPoint->state, 0);
++
++ gcmkONERROR(_AllocateIntegerId(&Os->syncPointDB, syncPoint, &syncPoint->id));
++
++ *SyncPoint = (gctSYNC_POINT)(gctUINTPTR_T)syncPoint->id;
++
++ gcmkFOOTER_ARG("*SyncPonint=%d", syncPoint->id);
++ return gcvSTATUS_OK;
++
++OnError:
++ if (syncPoint != gcvNULL)
++ {
++ kfree(syncPoint);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_ReferenceSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X", Os);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Initialize the sync point. */
++ atomic_inc(&syncPoint->ref);
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_DestroySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ if (atomic_dec_and_test(&syncPoint->ref))
++ {
++ gcmkVERIFY_OK(_DestroyIntegerId(&Os->syncPointDB, syncPoint->id));
++
++ /* Free the sgianl. */
++ syncPoint->timeline = gcvNULL;
++ kfree(syncPoint);
++ }
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_SignalSyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++ struct sync_timeline * timeline;
++ gctBOOL acquired = gcvFALSE;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE));
++ acquired = gcvTRUE;
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Set signaled state. */
++ atomic_set(&syncPoint->state, 1);
++
++ /* Get parent timeline. */
++ timeline = syncPoint->timeline;
++
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ acquired = gcvFALSE;
++
++ /* Signal timeline. */
++ if (timeline)
++ {
++ sync_timeline_signal(timeline);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ if (acquired)
++ {
++ /* Release the mutex. */
++ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex));
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_QuerySyncPoint(
++ IN gckOS Os,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctBOOL_PTR State
++ )
++{
++ gceSTATUS status;
++ gcsSYNC_POINT_PTR syncPoint;
++
++ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint);
++
++ /* Get state. */
++ *State = atomic_read(&syncPoint->state);
++
++ /* Success. */
++ gcmkFOOTER_ARG("*State=%d", *State);
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_CreateSyncTimeline(
++ IN gckOS Os,
++ OUT gctHANDLE * Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++
++ /* Create viv sync timeline. */
++ timeline = viv_sync_timeline_create("viv timeline", Os);
++
++ if (timeline == gcvNULL)
++ {
++ /* Out of memory. */
++ return gcvSTATUS_OUT_OF_MEMORY;
++ }
++
++ *Timeline = (gctHANDLE) timeline;
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_DestroySyncTimeline(
++ IN gckOS Os,
++ IN gctHANDLE Timeline
++ )
++{
++ struct viv_sync_timeline * timeline;
++ gcmkASSERT(Timeline != gcvNULL);
++
++ /* Destroy timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++ sync_timeline_destroy(&timeline->obj);
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CreateNativeFence(
++ IN gckOS Os,
++ IN gctHANDLE Timeline,
++ IN gctSYNC_POINT SyncPoint,
++ OUT gctINT * FenceFD
++ )
++{
++ int fd = -1;
++ struct viv_sync_timeline *timeline;
++ struct sync_pt * pt = gcvNULL;
++ struct sync_fence * fence;
++ char name[32];
++ gcsSYNC_POINT_PTR syncPoint;
++ gceSTATUS status;
++
++ gcmkHEADER_ARG("Os=0x%X Timeline=0x%X SyncPoint=%d",
++ Os, Timeline, (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ gcmkONERROR(
++ _QueryIntegerId(&Os->syncPointDB,
++ (gctUINT32)(gctUINTPTR_T)SyncPoint,
++ (gctPOINTER)&syncPoint));
++
++ /* Cast timeline. */
++ timeline = (struct viv_sync_timeline *) Timeline;
++
++ fd = get_unused_fd();
++
++ if (fd < 0)
++ {
++ /* Out of resources. */
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ /* Create viv_sync_pt. */
++ pt = viv_sync_pt_create(timeline, SyncPoint);
++
++ if (pt == gcvNULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Reference sync_timeline. */
++ syncPoint->timeline = &timeline->obj;
++
++ /* Build fence name. */
++ snprintf(name, 32, "viv sync_fence-%u", (gctUINT)(gctUINTPTR_T)SyncPoint);
++
++ /* Create sync_fence. */
++ fence = sync_fence_create(name, pt);
++
++ if (fence == NULL)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ /* Install fence to fd. */
++ sync_fence_install(fence, fd);
++
++ *FenceFD = fd;
++ gcmkFOOTER_ARG("*FenceFD=%d", fd);
++ return gcvSTATUS_OK;
++
++OnError:
++ /* Error roll back. */
++ if (pt)
++ {
++ sync_pt_free(pt);
++ }
++
++ if (fd > 0)
++ {
++ put_unused_fd(fd);
++ }
++
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++#if gcdSECURITY
++gceSTATUS
++gckOS_AllocatePageArray(
++ IN gckOS Os,
++ IN gctPHYS_ADDR Physical,
++ IN gctSIZE_T PageCount,
++ OUT gctPOINTER * PageArrayLogical,
++ OUT gctPHYS_ADDR * PageArrayPhysical
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ PLINUX_MDL mdl;
++ gctUINT32* table;
++ gctUINT32 offset;
++ gctSIZE_T bytes;
++ gckALLOCATOR allocator;
++
++ gcmkHEADER_ARG("Os=0x%X Physical=0x%X PageCount=%u",
++ Os, Physical, PageCount);
++
++ /* Verify the arguments. */
++ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS);
++ gcmkVERIFY_ARGUMENT(Physical != gcvNULL);
++ gcmkVERIFY_ARGUMENT(PageCount > 0);
++
++ bytes = PageCount * gcmSIZEOF(gctUINT32);
++ gcmkONERROR(gckOS_AllocateNonPagedMemory(
++ Os,
++ gcvFALSE,
++ &bytes,
++ PageArrayPhysical,
++ PageArrayLogical
++ ));
++
++ table = *PageArrayLogical;
++
++ /* Convert pointer to MDL. */
++ mdl = (PLINUX_MDL)Physical;
++
++ allocator = mdl->allocator;
++
++ /* Get all the physical addresses and store them in the page table. */
++
++ offset = 0;
++ PageCount = PageCount / (PAGE_SIZE / 4096);
++
++ /* Try to get the user pages so DMA can happen. */
++ while (PageCount-- > 0)
++ {
++ unsigned long phys = ~0;
++
++ if (mdl->pagedMem && !mdl->contiguous)
++ {
++ if (allocator)
++ {
++ gctUINT32 phys_addr;
++ allocator->ops->Physical(allocator, mdl, offset, &phys_addr);
++ phys = (unsigned long)phys_addr;
++ }
++ }
++ else
++ {
++ if (!mdl->pagedMem)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_OS,
++ "%s(%d): we should not get this call for Non Paged Memory!",
++ __FUNCTION__, __LINE__
++ );
++ }
++
++ phys = page_to_phys(nth_page(mdl->u.contiguousPages, offset));
++ }
++
++ table[offset] = phys;
++
++ offset += 1;
++ }
++
++OnError:
++
++ /* Return the status. */
++ gcmkFOOTER();
++ return status;
++}
++#endif
++
++gceSTATUS
++gckOS_CPUPhysicalToGPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 CPUPhysical,
++ IN gctUINT32_PTR GPUPhysical
++ )
++{
++ gcsPLATFORM * platform;
++ gcmkHEADER_ARG("CPUPhysical=0x%X", CPUPhysical);
++
++ platform = Os->device->platform;
++
++ if (platform && platform->ops->getGPUPhysical)
++ {
++ gcmkVERIFY_OK(
++ platform->ops->getGPUPhysical(platform, CPUPhysical, GPUPhysical));
++ }
++ else
++ {
++ *GPUPhysical = CPUPhysical;
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_GPUPhysicalToCPUPhysical(
++ IN gckOS Os,
++ IN gctUINT32 GPUPhysical,
++ IN gctUINT32_PTR CPUPhysical
++ )
++{
++ gcmkHEADER_ARG("GPUPhysical=0x%X", GPUPhysical);
++
++ *CPUPhysical = GPUPhysical;
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_PhysicalToPhysicalAddress(
++ IN gckOS Os,
++ IN gctPOINTER Physical,
++ OUT gctUINT32 * PhysicalAddress
++ )
++{
++ PLINUX_MDL mdl = (PLINUX_MDL)Physical;
++ gckALLOCATOR allocator = mdl->allocator;
++
++ if (allocator)
++ {
++ return allocator->ops->Physical(allocator, mdl, 0, PhysicalAddress);
++ }
++
++ return gcvSTATUS_NOT_SUPPORTED;
++}
++
++gceSTATUS
++gckOS_QueryOption(
++ IN gckOS Os,
++ IN gctCONST_STRING Option,
++ OUT gctUINT32 * Value
++ )
++{
++ gckGALDEVICE device = Os->device;
++
++ if (!strcmp(Option, "physBase"))
++ {
++ *Value = device->physBase;
++ return gcvSTATUS_OK;
++ }
++ else if (!strcmp(Option, "physSize"))
++ {
++ *Value = device->physSize;
++ return gcvSTATUS_OK;
++ }
++ else if (!strcmp(Option, "mmu"))
++ {
++#if gcdSECURITY
++ *Value = 0;
++#else
++ *Value = device->mmu;
++#endif
++ return gcvSTATUS_OK;
++ }
++
++ return gcvSTATUS_NOT_SUPPORTED;
++}
++
++static int
++fd_release(
++ struct inode *inode,
++ struct file *file
++ )
++{
++ gcsFDPRIVATE_PTR private = (gcsFDPRIVATE_PTR)file->private_data;
++
++ if (private && private->release)
++ {
++ return private->release(private);
++ }
++
++ return 0;
++}
++
++static const struct file_operations fd_fops = {
++ .release = fd_release,
++};
++
++gceSTATUS
++gckOS_GetFd(
++ IN gctSTRING Name,
++ IN gcsFDPRIVATE_PTR Private,
++ OUT gctINT *Fd
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
++ *Fd = anon_inode_getfd(Name, &fd_fops, Private, O_RDWR);
++
++ if (*Fd < 0)
++ {
++ return gcvSTATUS_OUT_OF_RESOURCES;
++ }
++
++ return gcvSTATUS_OK;
++#else
++ return gcvSTATUS_NOT_SUPPORTED;
++#endif
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.h 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,90 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_os_h_
++#define __gc_hal_kernel_os_h_
++
++typedef struct _LINUX_MDL_MAP
++{
++ gctINT pid;
++ gctPOINTER vmaAddr;
++ gctUINT32 count;
++ struct vm_area_struct * vma;
++ struct _LINUX_MDL_MAP * next;
++}
++LINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL_MAP * PLINUX_MDL_MAP;
++
++typedef struct _LINUX_MDL
++{
++ char * addr;
++
++ union _pages
++ {
++ /* Pointer to a array of pages. */
++ struct page * contiguousPages;
++ /* Pointer to a array of pointers to page. */
++ struct page ** nonContiguousPages;
++ }
++ u;
++
++#ifdef NO_DMA_COHERENT
++ gctPOINTER kaddr;
++#endif /* NO_DMA_COHERENT */
++
++ gctINT numPages;
++ gctINT pagedMem;
++ gctBOOL contiguous;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)
++ gctBOOL exact;
++#endif
++ dma_addr_t dmaHandle;
++ PLINUX_MDL_MAP maps;
++ struct _LINUX_MDL * prev;
++ struct _LINUX_MDL * next;
++
++ /* Pointer to allocator which allocates memory for this mdl. */
++ void * allocator;
++
++ /* Private data used by allocator. */
++ void * priv;
++
++ uint gid;
++}
++LINUX_MDL, *PLINUX_MDL;
++
++extern PLINUX_MDL_MAP
++FindMdlMap(
++ IN PLINUX_MDL Mdl,
++ IN gctINT PID
++ );
++
++typedef struct _DRIVER_ARGS
++{
++ gctUINT64 InputBuffer;
++ gctUINT64 InputBufferSize;
++ gctUINT64 OutputBuffer;
++ gctUINT64 OutputBufferSize;
++}
++DRIVER_ARGS;
++
++#endif /* __gc_hal_kernel_os_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_platform.h 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,279 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef _gc_hal_kernel_platform_h_
++#define _gc_hal_kernel_platform_h_
++#include <linux/mm.h>
++
++typedef struct _gcsMODULE_PARAMETERS
++{
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ gctINT irqLine3D0;
++ gctUINT registerMemBase3D0;
++ gctUINT registerMemSize3D0;
++ gctINT irqLine3D1;
++ gctUINT registerMemBase3D1;
++ gctUINT registerMemSize3D1;
++#else
++ gctINT irqLine;
++ gctUINT registerMemBase;
++ gctUINT registerMemSize;
++#endif
++ gctINT irqLine2D;
++ gctUINT registerMemBase2D;
++ gctUINT registerMemSize2D;
++ gctINT irqLineVG;
++ gctUINT registerMemBaseVG;
++ gctUINT registerMemSizeVG;
++ gctUINT contiguousSize;
++ gctUINT contiguousBase;
++ gctUINT contiguousRequested;
++ gctUINT bankSize;
++ gctINT fastClear;
++ gctINT compression;
++ gctINT powerManagement;
++ gctINT gpuProfiler;
++ gctINT signal;
++ gctUINT baseAddress;
++ gctUINT physSize;
++ gctUINT logFileSize;
++ gctUINT recovery;
++ gctUINT stuckDump;
++ gctUINT showArgs;
++ gctUINT gpu3DMinClock;
++}
++gcsMODULE_PARAMETERS;
++
++typedef struct _gcsPLATFORM * gckPLATFORM;
++
++typedef struct _gcsPLATFORM_OPERATIONS
++{
++ /*******************************************************************************
++ **
++ ** needAddDevice
++ **
++ ** Determine whether platform_device is created by initialization code.
++ ** If platform_device is created by BSP, return gcvFLASE here.
++ */
++ gctBOOL
++ (*needAddDevice)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustParam
++ **
++ ** Override content of arguments, if a argument is not changed here, it will
++ ** keep as default value or value set by insmod command line.
++ */
++ gceSTATUS
++ (*adjustParam)(
++ IN gckPLATFORM Platform,
++ OUT gcsMODULE_PARAMETERS *Args
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustDriver
++ **
++ ** Override content of platform_driver which will be registered.
++ */
++ gceSTATUS
++ (*adjustDriver)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** getPower
++ **
++ ** Prepare power and clock operation.
++ */
++ gceSTATUS
++ (*getPower)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** putPower
++ **
++ ** Finish power and clock operation.
++ */
++ gceSTATUS
++ (*putPower)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** allocPriv
++ **
++ ** Construct platform private data.
++ */
++ gceSTATUS
++ (*allocPriv)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** freePriv
++ **
++ ** free platform private data.
++ */
++ gceSTATUS
++ (*freePriv)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** setPower
++ **
++ ** Set power state of specified GPU.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to config.
++ **
++ ** gceBOOL Enable
++ ** Enable or disable power.
++ */
++ gceSTATUS
++ (*setPower)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ );
++
++ /*******************************************************************************
++ **
++ ** setClock
++ **
++ ** Set clock state of specified GPU.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to config.
++ **
++ ** gceBOOL Enable
++ ** Enable or disable clock.
++ */
++ gceSTATUS
++ (*setClock)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ );
++
++ /*******************************************************************************
++ **
++ ** reset
++ **
++ ** Reset GPU outside.
++ **
++ ** INPUT:
++ **
++ ** gceCORE GPU
++ ** GPU neeed to reset.
++ */
++ gceSTATUS
++ (*reset)(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU
++ );
++
++ /*******************************************************************************
++ **
++ ** getGPUPhysical
++ **
++ ** Convert CPU physical address to GPU physical address if they are
++ ** different.
++ */
++ gceSTATUS
++ (*getGPUPhysical)(
++ IN gckPLATFORM Platform,
++ IN gctUINT32 CPUPhysical,
++ OUT gctUINT32_PTR GPUPhysical
++ );
++
++ /*******************************************************************************
++ **
++ ** adjustProt
++ **
++ ** Override Prot flag when mapping paged memory to userspace.
++ */
++ gceSTATUS
++ (*adjustProt)(
++ IN struct vm_area_struct * vma
++ );
++
++ /*******************************************************************************
++ **
++ ** shrinkMemory
++ **
++ ** Do something to collect memory, eg, act as oom killer.
++ */
++ gceSTATUS
++ (*shrinkMemory)(
++ IN gckPLATFORM Platform
++ );
++
++ /*******************************************************************************
++ **
++ ** cache
++ **
++ ** Cache operation.
++ */
++ gceSTATUS
++ (*cache)(
++ IN gckPLATFORM Platform,
++ IN gctUINT32 ProcessID,
++ IN gctPHYS_ADDR Handle,
++ IN gctUINT32 Physical,
++ IN gctPOINTER Logical,
++ IN gctSIZE_T Bytes,
++ IN gceCACHEOPERATION Operation
++ );
++}
++gcsPLATFORM_OPERATIONS;
++
++typedef struct _gcsPLATFORM
++{
++ struct platform_device* device;
++ struct platform_driver* driver;
++
++ gcsPLATFORM_OPERATIONS* ops;
++
++ void* priv;
++}
++gcsPLATFORM;
++
++void
++gckPLATFORM_QueryOperations(
++ IN gcsPLATFORM_OPERATIONS ** Operations
++ );
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_probe.c 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,1347 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <linux/device.h>
++#include <linux/slab.h>
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_driver.h"
++
++#if USE_PLATFORM_DRIVER
++# include <linux/platform_device.h>
++#endif
++
++#ifdef CONFIG_PXA_DVFM
++# include <mach/dvfm.h>
++# include <mach/pxa3xx_dvfm.h>
++#endif
++
++
++/* Zone used for header/footer. */
++#define _GC_OBJ_ZONE gcvZONE_DRIVER
++
++MODULE_DESCRIPTION("Vivante Graphics Driver");
++MODULE_LICENSE("GPL");
++
++static struct class* gpuClass;
++
++static gcsPLATFORM platform;
++
++static gckGALDEVICE galDevice;
++
++static uint major = 199;
++module_param(major, uint, 0644);
++
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++static int irqLine3D0 = -1;
++module_param(irqLine3D0, int, 0644);
++
++static ulong registerMemBase3D0 = 0;
++module_param(registerMemBase3D0, ulong, 0644);
++
++static ulong registerMemSize3D0 = 2 << 10;
++module_param(registerMemSize3D0, ulong, 0644);
++
++static int irqLine3D1 = -1;
++module_param(irqLine3D1, int, 0644);
++
++static ulong registerMemBase3D1 = 0;
++module_param(registerMemBase3D1, ulong, 0644);
++
++static ulong registerMemSize3D1 = 2 << 10;
++module_param(registerMemSize3D1, ulong, 0644);
++#else
++static int irqLine = -1;
++module_param(irqLine, int, 0644);
++
++static ulong registerMemBase = 0x80000000;
++module_param(registerMemBase, ulong, 0644);
++
++static ulong registerMemSize = 2 << 10;
++module_param(registerMemSize, ulong, 0644);
++#endif
++
++static int irqLine2D = -1;
++module_param(irqLine2D, int, 0644);
++
++static ulong registerMemBase2D = 0x00000000;
++module_param(registerMemBase2D, ulong, 0644);
++
++static ulong registerMemSize2D = 2 << 10;
++module_param(registerMemSize2D, ulong, 0644);
++
++static int irqLineVG = -1;
++module_param(irqLineVG, int, 0644);
++
++static ulong registerMemBaseVG = 0x00000000;
++module_param(registerMemBaseVG, ulong, 0644);
++
++static ulong registerMemSizeVG = 2 << 10;
++module_param(registerMemSizeVG, ulong, 0644);
++
++#ifndef gcdDEFAULT_CONTIGUOUS_SIZE
++#define gcdDEFAULT_CONTIGUOUS_SIZE (4 << 20)
++#endif
++static ulong contiguousSize = gcdDEFAULT_CONTIGUOUS_SIZE;
++module_param(contiguousSize, ulong, 0644);
++
++static ulong contiguousBase = 0;
++module_param(contiguousBase, ulong, 0644);
++
++static ulong bankSize = 0;
++module_param(bankSize, ulong, 0644);
++
++static int fastClear = -1;
++module_param(fastClear, int, 0644);
++
++static int compression = -1;
++module_param(compression, int, 0644);
++
++static int powerManagement = -1;
++module_param(powerManagement, int, 0644);
++
++static int gpuProfiler = 0;
++module_param(gpuProfiler, int, 0644);
++
++static int signal = 48;
++module_param(signal, int, 0644);
++
++static ulong baseAddress = 0;
++module_param(baseAddress, ulong, 0644);
++
++static ulong physSize = 0;
++module_param(physSize, ulong, 0644);
++
++static uint logFileSize = 0;
++module_param(logFileSize,uint, 0644);
++
++static uint recovery = 1;
++module_param(recovery, uint, 0644);
++MODULE_PARM_DESC(recovery, "Recover GPU from stuck (1: Enable, 0: Disable)");
++
++/* Middle needs about 40KB buffer, Maximal may need more than 200KB buffer. */
++static uint stuckDump = 1;
++module_param(stuckDump, uint, 0644);
++MODULE_PARM_DESC(stuckDump, "Level of stuck dump content (1: Minimal, 2: Middle, 3: Maximal)");
++
++static int showArgs = 0;
++module_param(showArgs, int, 0644);
++
++static int mmu = 1;
++module_param(mmu, int, 0644);
++
++static int gpu3DMinClock = 1;
++
++static int contiguousRequested = 0;
++
++static int drv_open(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static int drv_release(
++ struct inode* inode,
++ struct file* filp
++ );
++
++static long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ );
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ );
++
++static struct file_operations driver_fops =
++{
++ .owner = THIS_MODULE,
++ .open = drv_open,
++ .release = drv_release,
++ .unlocked_ioctl = drv_ioctl,
++#ifdef HAVE_COMPAT_IOCTL
++ .compat_ioctl = drv_ioctl,
++#endif
++ .mmap = drv_mmap,
++};
++
++void
++_UpdateModuleParam(
++ gcsMODULE_PARAMETERS *Param
++ )
++{
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++#else
++ irqLine = Param->irqLine ;
++ registerMemBase = Param->registerMemBase;
++ registerMemSize = Param->registerMemSize;
++#endif
++ irqLine2D = Param->irqLine2D ;
++ registerMemBase2D = Param->registerMemBase2D;
++ registerMemSize2D = Param->registerMemSize2D;
++ irqLineVG = Param->irqLineVG;
++ registerMemBaseVG = Param->registerMemBaseVG;
++ registerMemSizeVG = Param->registerMemSizeVG;
++ contiguousSize = Param->contiguousSize;
++ contiguousBase = Param->contiguousBase;
++ bankSize = Param->bankSize;
++ fastClear = Param->fastClear;
++ compression = Param->compression;
++ powerManagement = Param->powerManagement;
++ gpuProfiler = Param->gpuProfiler;
++ signal = Param->signal;
++ baseAddress = Param->baseAddress;
++ physSize = Param->physSize;
++ logFileSize = Param->logFileSize;
++ recovery = Param->recovery;
++ stuckDump = Param->stuckDump;
++ showArgs = Param->showArgs;
++ contiguousRequested = Param->contiguousRequested;
++ gpu3DMinClock = Param->gpu3DMinClock;
++}
++
++void
++gckOS_DumpParam(
++ void
++ )
++{
++ printk("Galcore options:\n");
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ printk(" irqLine3D0 = %d\n", irqLine3D0);
++ printk(" registerMemBase3D0 = 0x%08lX\n", registerMemBase3D0);
++ printk(" registerMemSize3D0 = 0x%08lX\n", registerMemSize3D0);
++
++ if (irqLine3D1 != -1)
++ {
++ printk(" irqLine3D1 = %d\n", irqLine3D1);
++ printk(" registerMemBase3D1 = 0x%08lX\n", registerMemBase3D1);
++ printk(" registerMemSize3D1 = 0x%08lX\n", registerMemSize3D1);
++ }
++#else
++ printk(" irqLine = %d\n", irqLine);
++ printk(" registerMemBase = 0x%08lX\n", registerMemBase);
++ printk(" registerMemSize = 0x%08lX\n", registerMemSize);
++#endif
++
++ if (irqLine2D != -1)
++ {
++ printk(" irqLine2D = %d\n", irqLine2D);
++ printk(" registerMemBase2D = 0x%08lX\n", registerMemBase2D);
++ printk(" registerMemSize2D = 0x%08lX\n", registerMemSize2D);
++ }
++
++ if (irqLineVG != -1)
++ {
++ printk(" irqLineVG = %d\n", irqLineVG);
++ printk(" registerMemBaseVG = 0x%08lX\n", registerMemBaseVG);
++ printk(" registerMemSizeVG = 0x%08lX\n", registerMemSizeVG);
++ }
++
++ printk(" contiguousSize = %ld\n", contiguousSize);
++ printk(" contiguousBase = 0x%08lX\n", contiguousBase);
++ printk(" bankSize = 0x%08lX\n", bankSize);
++ printk(" fastClear = %d\n", fastClear);
++ printk(" compression = %d\n", compression);
++ printk(" signal = %d\n", signal);
++ printk(" powerManagement = %d\n", powerManagement);
++ printk(" baseAddress = 0x%08lX\n", baseAddress);
++ printk(" physSize = 0x%08lX\n", physSize);
++ printk(" logFileSize = %d KB \n", logFileSize);
++ printk(" recovery = %d\n", recovery);
++ printk(" stuckDump = %d\n", stuckDump);
++ printk(" gpuProfiler = %d\n", gpuProfiler);
++}
++
++int drv_open(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gctBOOL attached = gcvFALSE;
++ gcsHAL_PRIVATE_DATA_PTR data = gcvNULL;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = kmalloc(sizeof(gcsHAL_PRIVATE_DATA), GFP_KERNEL | __GFP_NOWARN);
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ data->device = galDevice;
++ data->mappedMemory = gcvNULL;
++ data->contiguousLogical = gcvNULL;
++ gcmkONERROR(gckOS_GetProcessID(&data->pidOpen));
++
++ /* Attached the process. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvTRUE));
++ }
++ }
++ attached = gcvTRUE;
++
++ if (!galDevice->contiguousMapped)
++ {
++ if (galDevice->contiguousPhysical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_MapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ &data->contiguousLogical
++ ));
++ }
++ }
++
++ filp->private_data = data;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ if (data != gcvNULL)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckOS_UnmapMemory(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical
++ ));
++ }
++
++ kfree(data);
++ }
++
++ if (attached)
++ {
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvFALSE));
++ }
++ }
++ }
++
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++int drv_release(
++ struct inode* inode,
++ struct file* filp
++ )
++{
++ gceSTATUS status;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++ gctINT i;
++
++ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (!device->contiguousMapped)
++ {
++ if (data->contiguousLogical != gcvNULL)
++ {
++ gcmkONERROR(gckOS_UnmapMemoryEx(
++ galDevice->os,
++ galDevice->contiguousPhysical,
++ galDevice->contiguousSize,
++ data->contiguousLogical,
++ data->pidOpen
++ ));
++
++ data->contiguousLogical = gcvNULL;
++ }
++ }
++
++ /* A process gets detached. */
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (galDevice->kernels[i] != gcvNULL)
++ {
++ gcmkONERROR(gckKERNEL_AttachProcessEx(galDevice->kernels[i], gcvFALSE, data->pidOpen));
++ }
++ }
++
++ kfree(data);
++ filp->private_data = NULL;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++long drv_ioctl(
++ struct file* filp,
++ unsigned int ioctlCode,
++ unsigned long arg
++ )
++{
++ gceSTATUS status;
++ gcsHAL_INTERFACE iface;
++ gctUINT32 copyLen;
++ DRIVER_ARGS drvArgs;
++ gckGALDEVICE device;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gctINT32 i, count;
++ gckVIDMEM_NODE nodeObject;
++
++ gcmkHEADER_ARG(
++ "filp=0x%08X ioctlCode=0x%08X arg=0x%08X",
++ filp, ioctlCode, arg
++ );
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if ((ioctlCode != IOCTL_GCHAL_INTERFACE)
++ && (ioctlCode != IOCTL_GCHAL_KERNEL_INTERFACE)
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown command %d\n",
++ __FUNCTION__, __LINE__,
++ ioctlCode
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Get the drvArgs. */
++ copyLen = copy_from_user(
++ &drvArgs, (void *) arg, sizeof(DRIVER_ARGS)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of the input arguments.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Now bring in the gcsHAL_INTERFACE structure. */
++ if ((drvArgs.InputBufferSize != sizeof(gcsHAL_INTERFACE))
++ || (drvArgs.OutputBufferSize != sizeof(gcsHAL_INTERFACE))
++ )
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): input or/and output structures are invalid.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ copyLen = copy_from_user(
++ &iface, gcmUINT64_TO_PTR(drvArgs.InputBuffer), sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of input HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ if (iface.command == gcvHAL_CHIP_INFO)
++ {
++ count = 0;
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ iface.u.ChipInfo.types[count] = gcvHARDWARE_VG;
++ }
++ else
++#endif
++ {
++ gcmkVERIFY_OK(gckHARDWARE_GetType(device->kernels[i]->hardware,
++ &iface.u.ChipInfo.types[count]));
++ }
++ count++;
++ }
++ }
++
++ iface.u.ChipInfo.count = count;
++ iface.status = status = gcvSTATUS_OK;
++ }
++ else
++ {
++ if (iface.hardwareType > 7)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): unknown hardwareType %d\n",
++ __FUNCTION__, __LINE__,
++ iface.hardwareType
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if gcdENABLE_VG
++ if (device->coreMapping[iface.hardwareType] == gcvCORE_VG)
++ {
++ status = gckVGKERNEL_Dispatch(device->kernels[gcvCORE_VG],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ else
++#endif
++ {
++ status = gckKERNEL_Dispatch(device->kernels[device->coreMapping[iface.hardwareType]],
++ (ioctlCode == IOCTL_GCHAL_INTERFACE),
++ &iface);
++ }
++ }
++
++ /* Redo system call after pending signal is handled. */
++ if (status == gcvSTATUS_INTERRUPTED)
++ {
++ gcmkFOOTER();
++ return -ERESTARTSYS;
++ }
++
++ if (gcmIS_SUCCESS(status) && (iface.command == gcvHAL_LOCK_VIDEO_MEMORY))
++ {
++ gcuVIDMEM_NODE_PTR node;
++ gctUINT32 processID;
++
++ gckOS_GetProcessID(&processID);
++
++ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(device->kernels[device->coreMapping[iface.hardwareType]],
++ processID,
++ (gctUINT32)iface.u.LockVideoMemory.node,
++ &nodeObject));
++ node = nodeObject->node;
++
++ /* Special case for mapped memory. */
++ if ((data->mappedMemory != gcvNULL)
++ && (node->VidMem.memory->object.type == gcvOBJ_VIDMEM)
++ )
++ {
++ /* Compute offset into mapped memory. */
++ gctUINT32 offset
++ = (gctUINT8 *) gcmUINT64_TO_PTR(iface.u.LockVideoMemory.memory)
++ - (gctUINT8 *) device->contiguousBase;
++
++ /* Compute offset into user-mapped region. */
++ iface.u.LockVideoMemory.memory =
++ gcmPTR_TO_UINT64((gctUINT8 *) data->mappedMemory + offset);
++ }
++ }
++
++ /* Copy data back to the user. */
++ copyLen = copy_to_user(
++ gcmUINT64_TO_PTR(drvArgs.OutputBuffer), &iface, sizeof(gcsHAL_INTERFACE)
++ );
++
++ if (copyLen != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): error copying of output HAL interface.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++static int drv_mmap(
++ struct file* filp,
++ struct vm_area_struct* vma
++ )
++{
++ gceSTATUS status = gcvSTATUS_OK;
++ gcsHAL_PRIVATE_DATA_PTR data;
++ gckGALDEVICE device;
++
++ gcmkHEADER_ARG("filp=0x%08X vma=0x%08X", filp, vma);
++
++ if (filp == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): filp is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ data = filp->private_data;
++
++ if (data == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): private_data is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ device = data->device;
++
++ if (device == gcvNULL)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): device is NULL\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++#if !gcdPAGED_MEMORY_CACHEABLE
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++ vma->vm_flags |= gcdVM_FLAGS;
++#endif
++ vma->vm_pgoff = 0;
++
++ if (device->contiguousMapped)
++ {
++ unsigned long size = vma->vm_end - vma->vm_start;
++ int ret = 0;
++
++ if (size > device->contiguousSize)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Invalid mapping size.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT);
++ }
++
++ ret = io_remap_pfn_range(
++ vma,
++ vma->vm_start,
++ device->requestedContiguousBase >> PAGE_SHIFT,
++ size,
++ vma->vm_page_prot
++ );
++
++ if (ret != 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): io_remap_pfn_range failed %d\n",
++ __FUNCTION__, __LINE__,
++ ret
++ );
++
++ data->mappedMemory = gcvNULL;
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ data->mappedMemory = (gctPOINTER) vma->vm_start;
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++ }
++
++OnError:
++ gcmkFOOTER();
++ return -ENOTTY;
++}
++
++
++#if !USE_PLATFORM_DRIVER
++static int __init drv_init(void)
++#else
++static int drv_init(void)
++#endif
++{
++ int ret;
++ int result = -EINVAL;
++ gceSTATUS status;
++ gckGALDEVICE device = gcvNULL;
++ struct class* device_class = gcvNULL;
++
++ gcsDEVICE_CONSTRUCT_ARGS args = {
++ .recovery = recovery,
++ .stuckDump = stuckDump,
++ .gpu3DMinClock = gpu3DMinClock,
++ .contiguousRequested = contiguousRequested,
++ .platform = &platform,
++ .mmu = mmu,
++ };
++
++ gcmkHEADER();
++
++ printk(KERN_INFO "Galcore version %d.%d.%d.%d\n",
++ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD);
++
++#if !VIVANTE_PROFILER_PM
++ /* when enable gpu profiler, we need to turn off gpu powerMangement */
++ if (gpuProfiler)
++ {
++ powerManagement = 0;
++ }
++#endif
++
++ if (showArgs)
++ {
++ gckOS_DumpParam();
++ }
++
++ if (logFileSize != 0)
++ {
++ gckDEBUGFS_Initialize();
++ }
++
++ /* Create the GAL device. */
++ status = gckGALDEVICE_Construct(
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ irqLine3D0,
++ registerMemBase3D0, registerMemSize3D0,
++ irqLine3D1,
++ registerMemBase3D1, registerMemSize3D1,
++#else
++ irqLine,
++ registerMemBase, registerMemSize,
++#endif
++ irqLine2D,
++ registerMemBase2D, registerMemSize2D,
++ irqLineVG,
++ registerMemBaseVG, registerMemSizeVG,
++ contiguousBase, contiguousSize,
++ bankSize, fastClear, compression, baseAddress, physSize, signal,
++ logFileSize,
++ powerManagement,
++ gpuProfiler,
++ &args,
++ &device
++ );
++
++ if (gcmIS_ERROR(status))
++ {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the GAL device: status=%d\n",
++ __FUNCTION__, __LINE__, status);
++
++ goto OnError;
++ }
++
++ /* Start the GAL device. */
++ gcmkONERROR(gckGALDEVICE_Start(device));
++
++ if ((physSize != 0)
++ && (device->kernels[gcvCORE_MAJOR] != gcvNULL)
++ && (device->kernels[gcvCORE_MAJOR]->hardware->mmuVersion != 0))
++ {
++ /* Reset the base address */
++ device->baseAddress = 0;
++ }
++
++ /* Register the character device. */
++ ret = register_chrdev(major, DEVICE_NAME, &driver_fops);
++
++ if (ret < 0)
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Could not allocate major number for mmap.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ if (major == 0)
++ {
++ major = ret;
++ }
++
++ /* Create the device class. */
++ device_class = class_create(THIS_MODULE, "graphics_class");
++
++ if (IS_ERR(device_class))
++ {
++ gcmkTRACE_ZONE(
++ gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to create the class.\n",
++ __FUNCTION__, __LINE__
++ );
++
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)
++ device_create(device_class, NULL, MKDEV(major, 0), NULL, DEVICE_NAME);
++#else
++ device_create(device_class, NULL, MKDEV(major, 0), DEVICE_NAME);
++#endif
++
++ galDevice = device;
++ gpuClass = device_class;
++
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "%s(%d): irqLine3D0=%d, contiguousSize=%lu, memBase3D0=0x%lX\n",
++ __FUNCTION__, __LINE__,
++ irqLine3D0, contiguousSize, registerMemBase3D0
++ );
++#else
++ gcmkTRACE_ZONE(
++ gcvLEVEL_INFO, gcvZONE_DRIVER,
++ "%s(%d): irqLine=%d, contiguousSize=%lu, memBase=0x%lX\n",
++ __FUNCTION__, __LINE__,
++ irqLine, contiguousSize, registerMemBase
++ );
++#endif
++
++ /* Success. */
++ gcmkFOOTER_NO();
++ return 0;
++
++OnError:
++ /* Roll back. */
++ if (device_class != gcvNULL)
++ {
++ device_destroy(device_class, MKDEV(major, 0));
++ class_destroy(device_class);
++ }
++
++ if (device != gcvNULL)
++ {
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(device));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device));
++ }
++
++ gcmkFOOTER();
++ return result;
++}
++
++#if !USE_PLATFORM_DRIVER
++static void __exit drv_exit(void)
++#else
++static void drv_exit(void)
++#endif
++{
++ gcmkHEADER();
++
++ gcmkASSERT(gpuClass != gcvNULL);
++ device_destroy(gpuClass, MKDEV(major, 0));
++ class_destroy(gpuClass);
++
++ unregister_chrdev(major, DEVICE_NAME);
++
++ gcmkVERIFY_OK(gckGALDEVICE_Stop(galDevice));
++ gcmkVERIFY_OK(gckGALDEVICE_Destroy(galDevice));
++
++ if(gckDEBUGFS_IsEnabled())
++ {
++ gckDEBUGFS_Terminate();
++ }
++
++ gcmkFOOTER_NO();
++}
++
++#if !USE_PLATFORM_DRIVER
++ module_init(drv_init);
++ module_exit(drv_exit);
++#else
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_probe(struct platform_device *pdev)
++#else
++static int __devinit gpu_probe(struct platform_device *pdev)
++#endif
++{
++ int ret = -ENODEV;
++ gcsMODULE_PARAMETERS moduleParam = {
++#if gcdMULTI_GPU || gcdMULTI_GPU_AFFINITY
++#else
++ .irqLine = irqLine,
++ .registerMemBase = registerMemBase,
++ .registerMemSize = registerMemSize,
++#endif
++ .irqLine2D = irqLine2D,
++ .registerMemBase2D = registerMemBase2D,
++ .registerMemSize2D = registerMemSize2D,
++ .irqLineVG = irqLineVG,
++ .registerMemBaseVG = registerMemBaseVG,
++ .registerMemSizeVG = registerMemSizeVG,
++ .contiguousSize = contiguousSize,
++ .contiguousBase = contiguousBase,
++ .bankSize = bankSize,
++ .fastClear = fastClear,
++ .compression = compression,
++ .powerManagement = powerManagement,
++ .gpuProfiler = gpuProfiler,
++ .signal = signal,
++ .baseAddress = baseAddress,
++ .physSize = physSize,
++ .logFileSize = logFileSize,
++ .recovery = recovery,
++ .stuckDump = stuckDump,
++ .showArgs = showArgs,
++ .gpu3DMinClock = gpu3DMinClock,
++ };
++
++ gcmkHEADER();
++
++ platform.device = pdev;
++
++ if (platform.ops->getPower)
++ {
++ if (gcmIS_ERROR(platform.ops->getPower(&platform)))
++ {
++ gcmkFOOTER_NO();
++ return ret;
++ }
++ }
++
++ if (platform.ops->adjustParam)
++ {
++ /* Override default module param. */
++ platform.ops->adjustParam(&platform, &moduleParam);
++
++ /* Update module param because drv_init() uses them directly. */
++ _UpdateModuleParam(&moduleParam);
++ }
++
++ ret = drv_init();
++
++ if (!ret)
++ {
++ platform_set_drvdata(pdev, galDevice);
++
++ gcmkFOOTER_NO();
++ return ret;
++ }
++
++ gcmkFOOTER_ARG(KERN_INFO "Failed to register gpu driver: %d\n", ret);
++ return ret;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++static int gpu_remove(struct platform_device *pdev)
++#else
++static int __devexit gpu_remove(struct platform_device *pdev)
++#endif
++{
++ gcmkHEADER();
++
++ drv_exit();
++
++ if (platform.ops->putPower)
++ {
++ platform.ops->putPower(&platform);
++ }
++
++ gcmkFOOTER_NO();
++ return 0;
++}
++
++static int gpu_suspend(struct platform_device *dev, pm_message_t state)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++
++ device = platform_get_drvdata(dev);
++
++ if (!device)
++ {
++ return -1;
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++ /* Store states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_QueryPowerManagementState(device->kernels[i]->vg->hardware, &device->statesStored[i]);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_QueryPowerManagementState(device->kernels[i]->hardware, &device->statesStored[i]);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_OFF);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_OFF);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ }
++ }
++
++ return 0;
++}
++
++static int gpu_resume(struct platform_device *dev)
++{
++ gceSTATUS status;
++ gckGALDEVICE device;
++ gctINT i;
++ gceCHIPPOWERSTATE statesStored;
++
++ device = platform_get_drvdata(dev);
++
++ if (!device)
++ {
++ return -1;
++ }
++
++ for (i = 0; i < gcdMAX_GPU_COUNT; i++)
++ {
++ if (device->kernels[i] != gcvNULL)
++ {
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_ON);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_ON);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++
++ /* Convert global state to crossponding internal state. */
++ switch(device->statesStored[i])
++ {
++ case gcvPOWER_OFF:
++ statesStored = gcvPOWER_OFF_BROADCAST;
++ break;
++ case gcvPOWER_IDLE:
++ statesStored = gcvPOWER_IDLE_BROADCAST;
++ break;
++ case gcvPOWER_SUSPEND:
++ statesStored = gcvPOWER_SUSPEND_BROADCAST;
++ break;
++ case gcvPOWER_ON:
++ statesStored = gcvPOWER_ON_AUTO;
++ break;
++ default:
++ statesStored = device->statesStored[i];
++ break;
++ }
++
++ /* Restore states. */
++#if gcdENABLE_VG
++ if (i == gcvCORE_VG)
++ {
++ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, statesStored);
++ }
++ else
++#endif
++ {
++ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, statesStored);
++ }
++
++ if (gcmIS_ERROR(status))
++ {
++ return -1;
++ }
++ }
++ }
++
++ return 0;
++}
++
++#if defined(CONFIG_PM) && LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
++#ifdef CONFIG_PM_SLEEP
++static int gpu_system_suspend(struct device *dev)
++{
++ pm_message_t state={0};
++ return gpu_suspend(to_platform_device(dev), state);
++}
++
++static int gpu_system_resume(struct device *dev)
++{
++ return gpu_resume(to_platform_device(dev));
++}
++#endif
++
++static const struct dev_pm_ops gpu_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(gpu_system_suspend, gpu_system_resume)
++};
++#endif
++
++static struct platform_driver gpu_driver = {
++ .probe = gpu_probe,
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)
++ .remove = gpu_remove,
++#else
++ .remove = __devexit_p(gpu_remove),
++#endif
++
++ .suspend = gpu_suspend,
++ .resume = gpu_resume,
++
++ .driver = {
++ .name = DEVICE_NAME,
++#if defined(CONFIG_PM) && LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
++ .pm = &gpu_pm_ops,
++#endif
++ }
++};
++
++static int __init gpu_init(void)
++{
++ int ret = 0;
++
++ memset(&platform, 0, sizeof(gcsPLATFORM));
++
++ gckPLATFORM_QueryOperations(&platform.ops);
++
++ if (platform.ops == gcvNULL)
++ {
++ printk(KERN_ERR "galcore: No platform specific operations.\n");
++ ret = -ENODEV;
++ goto out;
++ }
++
++ if (platform.ops->allocPriv)
++ {
++ /* Allocate platform private data. */
++ if (gcmIS_ERROR(platform.ops->allocPriv(&platform)))
++ {
++ ret = -ENOMEM;
++ goto out;
++ }
++ }
++
++ if (platform.ops->needAddDevice
++ && platform.ops->needAddDevice(&platform))
++ {
++ /* Allocate device */
++ platform.device = platform_device_alloc(DEVICE_NAME, -1);
++ if (!platform.device)
++ {
++ printk(KERN_ERR "galcore: platform_device_alloc failed.\n");
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Add device */
++ ret = platform_device_add(platform.device);
++ if (ret)
++ {
++ printk(KERN_ERR "galcore: platform_device_add failed.\n");
++ goto put_dev;
++ }
++ }
++
++ platform.driver = &gpu_driver;
++
++ if (platform.ops->adjustDriver)
++ {
++ /* Override default platform_driver struct. */
++ platform.ops->adjustDriver(&platform);
++ }
++
++ ret = platform_driver_register(&gpu_driver);
++ if (!ret)
++ {
++ goto out;
++ }
++
++ platform_device_del(platform.device);
++put_dev:
++ platform_device_put(platform.device);
++
++out:
++ return ret;
++}
++
++static void __exit gpu_exit(void)
++{
++ platform_driver_unregister(&gpu_driver);
++
++ if (platform.ops->needAddDevice
++ && platform.ops->needAddDevice(&platform))
++ {
++ platform_device_unregister(platform.device);
++ }
++
++ if (platform.priv)
++ {
++ /* Free platform private data. */
++ platform.ops->freePriv(&platform);
++ }
++}
++
++module_init(gpu_init);
++module_exit(gpu_exit);
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_security_channel.c 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,385 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include <linux/slab.h>
++
++#include "tee_client_api.h"
++
++#define _GC_OBJ_ZONE gcvZONE_OS
++
++#define GPU3D_UUID { 0xcc9f80ea, 0xa836, 0x11e3, { 0x9b, 0x07, 0x78, 0x2b, 0xcb, 0x5c, 0xf3, 0xe3 } }
++
++static const TEEC_UUID gpu3d_uuid = GPU3D_UUID;
++TEEC_Context teecContext;
++
++typedef struct _gcsSecurityChannel {
++ gckOS os;
++ TEEC_Session session;
++ int * virtual;
++ TEEC_SharedMemory inputBuffer;
++ gctUINT32 bytes;
++ gctPOINTER mutex;
++} gcsSecurityChannel;
++
++TEEC_SharedMemory *
++gpu3d_allocate_secure_mem(
++ gckOS Os,
++ unsigned int size
++ )
++{
++ TEEC_Result result;
++ TEEC_Context *context = &teecContext;
++ TEEC_SharedMemory *shm = NULL;
++ void *handle = NULL;
++ unsigned int phyAddr = 0xFFFFFFFF;
++ gceSTATUS status;
++ gctSIZE_T bytes = size;
++
++ shm = kmalloc(sizeof(TEEC_SharedMemory), GFP_KERNEL);
++
++ if (NULL == shm)
++ {
++ return NULL;
++ }
++
++ memset(shm, 0, sizeof(TEEC_SharedMemory));
++
++ status = gckOS_AllocatePagedMemoryEx(
++ Os,
++ gcvALLOC_FLAG_SECURITY,
++ bytes,
++ gcvNULL,
++ (gctPHYS_ADDR *)&handle);
++
++ if (gcmIS_ERROR(status))
++ {
++ kfree(shm);
++ return NULL;
++ }
++
++ status = gckOS_PhysicalToPhysicalAddress(
++ Os,
++ handle,
++ &phyAddr);
++
++ if (gcmIS_ERROR(status))
++ {
++ kfree(shm);
++ return NULL;
++ }
++
++ /* record the handle into shm->user_data */
++ shm->userdata = handle;
++
++ /* [b] Bulk input buffer. */
++ shm->size = size;
++ shm->flags = TEEC_MEM_INPUT;
++
++ /* Use TEE Client API to register the underlying memory buffer. */
++ shm->phyAddr = (void *)phyAddr;
++
++ result = TEEC_RegisterSharedMemory(
++ context,
++ shm);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gckOS_FreePagedMemory(Os, (gctPHYS_ADDR)handle, shm->size);
++ kfree(shm);
++ return NULL;
++ }
++
++ return shm;
++}
++
++void gpu3d_release_secure_mem(
++ gckOS Os,
++ void *shm_handle
++ )
++{
++ TEEC_SharedMemory *shm = shm_handle;
++ void * handle;
++
++ if (!shm)
++ {
++ return;
++ }
++
++ handle = shm->userdata;
++
++ TEEC_ReleaseSharedMemory(shm);
++ gckOS_FreePagedMemory(Os, (gctPHYS_ADDR)handle, shm->size);
++
++ kfree(shm);
++
++ return;
++}
++
++static TEEC_Result gpu3d_session_callback(
++ TEEC_Session* session,
++ uint32_t commandID,
++ TEEC_Operation* operation,
++ void* userdata
++ )
++{
++ gcsSecurityChannel *channel = userdata;
++
++ if (channel == gcvNULL)
++ {
++ return TEEC_ERROR_BAD_PARAMETERS;
++ }
++
++ switch(commandID)
++ {
++ case gcvTA_CALLBACK_ALLOC_SECURE_MEM:
++ {
++ uint32_t size = operation->params[0].value.a;
++ TEEC_SharedMemory *shm = NULL;
++
++ shm = gpu3d_allocate_secure_mem(channel->os, size);
++
++ /* use the value to save the pointer in client side */
++ operation->params[0].value.a = (uint32_t)shm;
++ operation->params[0].value.b = (uint32_t)shm->phyAddr;
++
++ break;
++ }
++ case gcvTA_CALLBACK_FREE_SECURE_MEM:
++ {
++ TEEC_SharedMemory *shm = (TEEC_SharedMemory *)operation->params[0].value.a;
++
++ gpu3d_release_secure_mem(channel->os, shm);
++ break;
++ }
++ default:
++ break;
++ }
++
++ return TEEC_SUCCESS;
++}
++
++gceSTATUS
++gckOS_OpenSecurityChannel(
++ IN gckOS Os,
++ IN gceCORE GPU,
++ OUT gctUINT32 *Channel
++ )
++{
++ gceSTATUS status;
++ TEEC_Result result;
++ static bool initialized = gcvFALSE;
++ gcsSecurityChannel *channel = gcvNULL;
++
++ TEEC_Operation operation = {0};
++
++ /* Connect to TEE. */
++ if (initialized == gcvFALSE)
++ {
++ result = TEEC_InitializeContext(NULL, &teecContext);
++
++ if (result != TEEC_SUCCESS) {
++ gcmkONERROR(gcvSTATUS_CHIP_NOT_READY);
++ }
++
++ initialized = gcvTRUE;
++ }
++
++ /* Construct channel. */
++ gcmkONERROR(
++ gckOS_Allocate(Os, gcmSIZEOF(*channel), (gctPOINTER *)&channel));
++
++ gckOS_ZeroMemory(channel, gcmSIZEOF(gcsSecurityChannel));
++
++ channel->os = Os;
++
++ gcmkONERROR(gckOS_CreateMutex(Os, &channel->mutex));
++
++ /* Allocate shared memory for passing gcTA_INTERFACE. */
++ channel->bytes = gcmSIZEOF(gcsTA_INTERFACE);
++ channel->virtual = kmalloc(channel->bytes, GFP_KERNEL | __GFP_NOWARN);
++
++ if (!channel->virtual)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY);
++ }
++
++ channel->inputBuffer.size = channel->bytes;
++ channel->inputBuffer.flags = TEEC_MEM_INPUT | TEEC_MEM_OUTPUT;
++ channel->inputBuffer.phyAddr = (void *)virt_to_phys(channel->virtual);
++
++ result = TEEC_RegisterSharedMemory(&teecContext, &channel->inputBuffer);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES);
++ }
++
++ operation.paramTypes = TEEC_PARAM_TYPES(
++ TEEC_VALUE_INPUT,
++ TEEC_NONE,
++ TEEC_NONE,
++ TEEC_NONE);
++
++ operation.params[0].value.a = GPU;
++
++ /* Open session with TEE application. */
++ result = TEEC_OpenSession(
++ &teecContext,
++ &channel->session,
++ &gpu3d_uuid,
++ TEEC_LOGIN_USER,
++ NULL,
++ &operation,
++ NULL);
++
++ /* Prepare callback. */
++ TEEC_RegisterCallback(&channel->session, gpu3d_session_callback, channel);
++
++ *Channel = (gctUINT32)channel;
++
++ return gcvSTATUS_OK;
++
++OnError:
++ if (channel)
++ {
++ if (channel->virtual)
++ {
++ }
++
++ if (channel->mutex)
++ {
++ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, channel->mutex));
++ }
++
++ gcmkVERIFY_OK(gckOS_Free(Os, channel));
++ }
++
++ return status;
++}
++
++gceSTATUS
++gckOS_CloseSecurityChannel(
++ IN gctUINT32 Channel
++ )
++{
++ /* TODO . */
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++gckOS_CallSecurityService(
++ IN gctUINT32 Channel,
++ IN gcsTA_INTERFACE *Interface
++ )
++{
++ gceSTATUS status;
++ TEEC_Result result;
++ gcsSecurityChannel *channel = (gcsSecurityChannel *)Channel;
++ TEEC_Operation operation = {0};
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(Channel != 0);
++
++ gckOS_AcquireMutex(channel->os, channel->mutex, gcvINFINITE);
++
++ gckOS_MemCopy(channel->virtual, Interface, channel->bytes);
++
++ operation.paramTypes = TEEC_PARAM_TYPES(
++ TEEC_MEMREF_PARTIAL_INPUT,
++ TEEC_NONE,
++ TEEC_NONE,
++ TEEC_NONE);
++
++ /* Note: we use the updated size in the MemRef output by the encryption. */
++ operation.params[0].memref.parent = &channel->inputBuffer;
++ operation.params[0].memref.offset = 0;
++ operation.params[0].memref.size = sizeof(gcsTA_INTERFACE);
++ operation.started = true;
++
++ /* Start the commit command within the TEE application. */
++ result = TEEC_InvokeCommand(
++ &channel->session,
++ gcvTA_COMMAND_DISPATCH,
++ &operation,
++ NULL);
++
++ gckOS_MemCopy(Interface, channel->virtual, channel->bytes);
++
++ gckOS_ReleaseMutex(channel->os, channel->mutex);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
++
++gceSTATUS
++gckOS_InitSecurityChannel(
++ IN gctUINT32 Channel
++ )
++{
++ gceSTATUS status;
++ TEEC_Result result;
++ gcsSecurityChannel *channel = (gcsSecurityChannel *)Channel;
++ TEEC_Operation operation = {0};
++
++ gcmkHEADER();
++ gcmkVERIFY_ARGUMENT(Channel != 0);
++
++ operation.paramTypes = TEEC_PARAM_TYPES(
++ TEEC_MEMREF_PARTIAL_INPUT,
++ TEEC_NONE,
++ TEEC_NONE,
++ TEEC_NONE);
++
++ /* Note: we use the updated size in the MemRef output by the encryption. */
++ operation.params[0].memref.parent = &channel->inputBuffer;
++ operation.params[0].memref.offset = 0;
++ operation.params[0].memref.size = gcmSIZEOF(gcsTA_INTERFACE);
++ operation.started = true;
++
++ /* Start the commit command within the TEE application. */
++ result = TEEC_InvokeCommand(
++ &channel->session,
++ gcvTA_COMMAND_INIT,
++ &operation,
++ NULL);
++
++ if (result != TEEC_SUCCESS)
++ {
++ gcmkONERROR(gcvSTATUS_GENERIC_IO);
++ }
++
++ gcmkFOOTER_NO();
++ return gcvSTATUS_OK;
++
++OnError:
++ gcmkFOOTER();
++ return status;
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.c 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,177 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include <gc_hal.h>
++#include <gc_hal_base.h>
++
++#if gcdANDROID_NATIVE_FENCE_SYNC
++
++#include <linux/kernel.h>
++#include <linux/file.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/module.h>
++#include <linux/syscalls.h>
++#include <linux/uaccess.h>
++
++#include "gc_hal_kernel_sync.h"
++
++static struct sync_pt *
++viv_sync_pt_dup(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt *pt;
++ struct viv_sync_pt *src;
++ struct viv_sync_timeline *obj;
++
++ src = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ /* Create the new sync_pt. */
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = src->stamp;
++ pt->sync = src->sync;
++
++ /* Reference sync point. */
++ status = gckOS_ReferenceSyncPoint(obj->os, pt->sync);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *)pt;
++}
++
++static int
++viv_sync_pt_has_signaled(
++ struct sync_pt * sync_pt
++ )
++{
++ gceSTATUS status;
++ gctBOOL state;
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *)sync_pt;
++ obj = (struct viv_sync_timeline *)sync_pt->parent;
++
++ status = gckOS_QuerySyncPoint(obj->os, pt->sync, &state);
++
++ if (gcmIS_ERROR(status))
++ {
++ /* Error. */
++ return -1;
++ }
++
++ return state;
++}
++
++static int
++viv_sync_pt_compare(
++ struct sync_pt * a,
++ struct sync_pt * b
++ )
++{
++ int ret;
++ struct viv_sync_pt * pt1 = (struct viv_sync_pt *) a;
++ struct viv_sync_pt * pt2 = (struct viv_sync_pt *) b;
++
++ ret = (pt1->stamp < pt2->stamp) ? -1
++ : (pt1->stamp == pt2->stamp) ? 0
++ : 1;
++
++ return ret;
++}
++
++static void
++viv_sync_pt_free(
++ struct sync_pt * sync_pt
++ )
++{
++ struct viv_sync_pt * pt;
++ struct viv_sync_timeline * obj;
++
++ pt = (struct viv_sync_pt *) sync_pt;
++ obj = (struct viv_sync_timeline *) sync_pt->parent;
++
++ gckOS_DestroySyncPoint(obj->os, pt->sync);
++}
++
++static struct sync_timeline_ops viv_timeline_ops =
++{
++ .driver_name = "viv_sync",
++ .dup = viv_sync_pt_dup,
++ .has_signaled = viv_sync_pt_has_signaled,
++ .compare = viv_sync_pt_compare,
++ .free_pt = viv_sync_pt_free,
++};
++
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * name,
++ gckOS os
++ )
++{
++ struct viv_sync_timeline * obj;
++
++ obj = (struct viv_sync_timeline *)
++ sync_timeline_create(&viv_timeline_ops, sizeof(struct viv_sync_timeline), name);
++
++ obj->os = os;
++ obj->stamp = 0;
++
++ return obj;
++}
++
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * obj,
++ gctSYNC_POINT SyncPoint
++ )
++{
++ gceSTATUS status;
++ struct viv_sync_pt * pt;
++
++ pt = (struct viv_sync_pt *)
++ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt));
++
++ pt->stamp = obj->stamp++;
++ pt->sync = SyncPoint;
++
++ /* Dup signal. */
++ status = gckOS_ReferenceSyncPoint(obj->os, SyncPoint);
++
++ if (gcmIS_ERROR(status))
++ {
++ sync_pt_free((struct sync_pt *)pt);
++ return NULL;
++ }
++
++ return (struct sync_pt *) pt;
++}
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_sync.h 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,72 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#ifndef __gc_hal_kernel_sync_h_
++#define __gc_hal_kernel_sync_h_
++
++#include <linux/types.h>
++
++/* sync.h is in drivers/staging/android/ for now. */
++#include <sync.h>
++
++#include <gc_hal.h>
++#include <gc_hal_base.h>
++
++struct viv_sync_timeline
++{
++ /* Parent object. */
++ struct sync_timeline obj;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++
++ /* Pointer to os struct. */
++ gckOS os;
++};
++
++
++struct viv_sync_pt
++{
++ /* Parent object. */
++ struct sync_pt pt;
++
++ /* Reference sync point*/
++ gctSYNC_POINT sync;
++
++ /* Timestamp when sync_pt is created. */
++ gctUINT stamp;
++};
++
++/* Create viv_sync_timeline object. */
++struct viv_sync_timeline *
++viv_sync_timeline_create(
++ const char * Name,
++ gckOS Os
++ );
++
++/* Create viv_sync_pt object. */
++struct sync_pt *
++viv_sync_pt_create(
++ struct viv_sync_timeline * Obj,
++ gctSYNC_POINT SyncPoint
++ );
++
++#endif /* __gc_hal_kernel_sync_h_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.c 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,880 @@
++/****************************************************************************
++*
++* Copyright (C) 2005 - 2014 by Vivante Corp.
++*
++* This program is free software; you can redistribute it and/or modify
++* it under the terms of the GNU General Public License as published by
++* the Free Software Foundation; either version 2 of the license, or
++* (at your option) any later version.
++*
++* This program is distributed in the hope that it will be useful,
++* but WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++* GNU General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not write to the Free Software
++* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++*
++*****************************************************************************/
++
++
++#include "gc_hal_kernel_linux.h"
++#include "gc_hal_kernel_platform.h"
++#include "gc_hal_kernel_device.h"
++#include "gc_hal_driver.h"
++#include <linux/slab.h>
++
++#if USE_PLATFORM_DRIVER
++# include <linux/platform_device.h>
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#include <mach/viv_gpu.h>
++#else
++#include <linux/pm_runtime.h>
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
++#include <mach/busfreq.h>
++#else
++#include <linux/busfreq-imx6.h>
++#include <linux/reset.h>
++#endif
++#endif
++
++#include <linux/clk.h>
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
++#include <mach/hardware.h>
++#endif
++#include <linux/pm_runtime.h>
++
++#include <linux/regulator/consumer.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#include <linux/device_cooling.h>
++#define REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_devfreq_cooling_notifier(a);
++#else
++extern int register_thermal_notifier(struct notifier_block *nb);
++extern int unregister_thermal_notifier(struct notifier_block *nb);
++#define REG_THERMAL_NOTIFIER(a) register_thermal_notifier(a);
++#define UNREG_THERMAL_NOTIFIER(a) unregister_thermal_notifier(a);
++#endif
++
++static int initgpu3DMinClock = 1;
++module_param(initgpu3DMinClock, int, 0644);
++
++struct platform_device *pdevice;
++
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++# include <linux/kernel.h>
++# include <linux/mm.h>
++# include <linux/oom.h>
++# include <linux/sched.h>
++
++struct task_struct *lowmem_deathpending;
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data);
++
++static struct notifier_block task_nb = {
++ .notifier_call = task_notify_func,
++};
++
++static int
++task_notify_func(struct notifier_block *self, unsigned long val, void *data)
++{
++ struct task_struct *task = data;
++
++ if (task == lowmem_deathpending)
++ lowmem_deathpending = NULL;
++
++ return NOTIFY_OK;
++}
++
++extern struct task_struct *lowmem_deathpending;
++static unsigned long lowmem_deathpending_timeout;
++
++static int force_contiguous_lowmem_shrink(IN gckKERNEL Kernel)
++{
++ struct task_struct *p;
++ struct task_struct *selected = NULL;
++ int tasksize;
++ int ret = -1;
++ int min_adj = 0;
++ int selected_tasksize = 0;
++ int selected_oom_adj;
++ /*
++ * If we already have a death outstanding, then
++ * bail out right away; indicating to vmscan
++ * that we have nothing further to offer on
++ * this pass.
++ *
++ */
++ if (lowmem_deathpending &&
++ time_before_eq(jiffies, lowmem_deathpending_timeout))
++ return 0;
++ selected_oom_adj = min_adj;
++
++ rcu_read_lock();
++ for_each_process(p) {
++ struct mm_struct *mm;
++ struct signal_struct *sig;
++ gcuDATABASE_INFO info;
++ int oom_adj;
++
++ task_lock(p);
++ mm = p->mm;
++ sig = p->signal;
++ if (!mm || !sig) {
++ task_unlock(p);
++ continue;
++ }
++ oom_adj = sig->oom_score_adj;
++ if (oom_adj < min_adj) {
++ task_unlock(p);
++ continue;
++ }
++
++ tasksize = 0;
++ task_unlock(p);
++ rcu_read_unlock();
++
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_VIDEO_MEMORY, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_CONTIGUOUS, &info) == gcvSTATUS_OK){
++ tasksize += info.counters.bytes / PAGE_SIZE;
++ }
++
++ rcu_read_lock();
++
++ if (tasksize <= 0)
++ continue;
++
++ gckOS_Print("<gpu> pid %d (%s), adj %d, size %d \n", p->pid, p->comm, oom_adj, tasksize);
++
++ if (selected) {
++ if (oom_adj < selected_oom_adj)
++ continue;
++ if (oom_adj == selected_oom_adj &&
++ tasksize <= selected_tasksize)
++ continue;
++ }
++ selected = p;
++ selected_tasksize = tasksize;
++ selected_oom_adj = oom_adj;
++ }
++ if (selected) {
++ gckOS_Print("<gpu> send sigkill to %d (%s), adj %d, size %d\n",
++ selected->pid, selected->comm,
++ selected_oom_adj, selected_tasksize);
++ lowmem_deathpending = selected;
++ lowmem_deathpending_timeout = jiffies + HZ;
++ force_sig(SIGKILL, selected);
++ ret = 0;
++ }
++ rcu_read_unlock();
++ return ret;
++}
++
++
++gceSTATUS
++_ShrinkMemory(
++ IN gckPLATFORM Platform
++ )
++{
++ struct platform_device *pdev;
++ gckGALDEVICE galDevice;
++ gckKERNEL kernel;
++
++ pdev = Platform->device;
++
++ galDevice = platform_get_drvdata(pdev);
++
++ kernel = galDevice->kernels[gcvCORE_MAJOR];
++
++ if (kernel != gcvNULL)
++ {
++ force_contiguous_lowmem_shrink(kernel);
++ }
++ else
++ {
++ gcmkPRINT("%s(%d) can't find kernel! ", __FUNCTION__, __LINE__);
++ }
++
++ return gcvSTATUS_OK;
++}
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++static int thermal_hot_pm_notify(struct notifier_block *nb, unsigned long event,
++ void *dummy)
++{
++ static gctUINT orgFscale, minFscale, maxFscale;
++ static gctBOOL bAlreadyTooHot = gcvFALSE;
++ gckHARDWARE hardware;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if (!galDevice)
++ {
++ /* GPU is not ready, so it is meaningless to change GPU freq. */
++ return NOTIFY_OK;
++ }
++
++ if (!galDevice->kernels[gcvCORE_MAJOR])
++ {
++ return NOTIFY_OK;
++ }
++
++ hardware = galDevice->kernels[gcvCORE_MAJOR]->hardware;
++
++ if (!hardware)
++ {
++ return NOTIFY_OK;
++ }
++
++ if (event && !bAlreadyTooHot) {
++ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale);
++ gckHARDWARE_SetFscaleValue(hardware, minFscale);
++ bAlreadyTooHot = gcvTRUE;
++ gckOS_Print("System is too hot. GPU3D will work at %d/64 clock.\n", minFscale);
++ } else if (!event && bAlreadyTooHot) {
++ gckHARDWARE_SetFscaleValue(hardware, orgFscale);
++ gckOS_Print("Hot alarm is canceled. GPU3D clock will return to %d/64\n", orgFscale);
++ bAlreadyTooHot = gcvFALSE;
++ }
++ return NOTIFY_OK;
++}
++
++static struct notifier_block thermal_hot_pm_notifier = {
++ .notifier_call = thermal_hot_pm_notify,
++ };
++
++static ssize_t show_gpu3DMinClock(struct device_driver *dev, char *buf)
++{
++ gctUINT currentf,minf,maxf;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ {
++ gckHARDWARE_GetFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware,
++ &currentf, &minf, &maxf);
++ }
++ snprintf(buf, PAGE_SIZE, "%d\n", minf);
++ return strlen(buf);
++}
++
++static ssize_t update_gpu3DMinClock(struct device_driver *dev, const char *buf, size_t count)
++{
++
++ gctINT fields;
++ gctUINT MinFscaleValue;
++ gckGALDEVICE galDevice;
++
++ galDevice = platform_get_drvdata(pdevice);
++ if(galDevice->kernels[gcvCORE_MAJOR])
++ {
++ fields = sscanf(buf, "%d", &MinFscaleValue);
++ if (fields < 1)
++ return -EINVAL;
++
++ gckHARDWARE_SetMinFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware,MinFscaleValue);
++ }
++
++ return count;
++}
++
++static DRIVER_ATTR(gpu3DMinClock, S_IRUGO | S_IWUSR, show_gpu3DMinClock, update_gpu3DMinClock);
++#endif
++
++
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++static const struct of_device_id mxs_gpu_dt_ids[] = {
++ { .compatible = "fsl,imx6q-gpu", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, mxs_gpu_dt_ids);
++#endif
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++struct contiguous_mem_pool {
++ struct dma_attrs attrs;
++ dma_addr_t phys;
++ void *virt;
++ size_t size;
++};
++#endif
++
++struct imx_priv {
++ /* Clock management.*/
++ struct clk *clk_3d_core;
++ struct clk *clk_3d_shader;
++ struct clk *clk_3d_axi;
++ struct clk *clk_2d_core;
++ struct clk *clk_2d_axi;
++ struct clk *clk_vg_axi;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ /*Power management.*/
++ struct regulator *gpu_regulator;
++#endif
++#endif
++ /*Run time pm*/
++ struct device *pmdev;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct contiguous_mem_pool *pool;
++ struct reset_control *rstc[gcdMAX_GPU_COUNT];
++#endif
++};
++
++static struct imx_priv imxPriv;
++
++gceSTATUS
++gckPLATFORM_AdjustParam(
++ IN gckPLATFORM Platform,
++ OUT gcsMODULE_PARAMETERS *Args
++ )
++{
++ struct resource* res;
++ struct platform_device* pdev = Platform->device;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct device_node *dn =pdev->dev.of_node;
++ const u32 *prop;
++#else
++ struct viv_gpu_platform_data *pdata;
++#endif
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phys_baseaddr");
++ if (res)
++ Args->baseAddress = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_3d");
++ if (res)
++ Args->irqLine = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_3d");
++ if (res)
++ {
++ Args->registerMemBase = res->start;
++ Args->registerMemSize = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_2d");
++ if (res)
++ Args->irqLine2D = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_2d");
++ if (res)
++ {
++ Args->registerMemBase2D = res->start;
++ Args->registerMemSize2D = res->end - res->start + 1;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_vg");
++ if (res)
++ Args->irqLineVG = res->start;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_vg");
++ if (res)
++ {
++ Args->registerMemBaseVG = res->start;
++ Args->registerMemSizeVG = res->end - res->start + 1;
++ }
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ Args->contiguousBase = 0;
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ prop = of_get_property(dn, "contiguousbase", NULL);
++ if(prop)
++ Args->contiguousBase = *prop;
++ of_property_read_u32(dn,"contiguoussize", (u32 *)&contiguousSize);
++#else
++ pdata = pdev->dev.platform_data;
++ if (pdata) {
++ Args->contiguousBase = pdata->reserved_mem_base;
++ Args->contiguousSize = pdata->reserved_mem_size;
++ }
++#endif
++ if (Args->contiguousSize == 0)
++ gckOS_Print("Warning: No contiguous memory is reserverd for gpu.!\n ");
++
++ Args->gpu3DMinClock = initgpu3DMinClock;
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_AllocPriv(
++ IN gckPLATFORM Platform
++ )
++{
++ Platform->priv = &imxPriv;
++
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ task_free_register(&task_nb);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_FreePriv(
++ IN gckPLATFORM Platform
++ )
++{
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ task_free_unregister(&task_nb);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_GetPower(
++ IN gckPLATFORM Platform
++ )
++{
++ struct device* pdev = &Platform->device->dev;
++ struct imx_priv *priv = Platform->priv;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct reset_control *rstc;
++#endif
++
++#ifdef CONFIG_PM
++ /*Init runtime pm for gpu*/
++ pm_runtime_enable(pdev);
++ priv->pmdev = pdev;
++#endif
++
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ rstc = devm_reset_control_get(pdev, "gpu3d");
++ priv->rstc[gcvCORE_MAJOR] = IS_ERR(rstc) ? NULL : rstc;
++ rstc = devm_reset_control_get(pdev, "gpu2d");
++ priv->rstc[gcvCORE_2D] = IS_ERR(rstc) ? NULL : rstc;
++ rstc = devm_reset_control_get(pdev, "gpuvg");
++ priv->rstc[gcvCORE_VG] = IS_ERR(rstc) ? NULL : rstc;
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ /*get gpu regulator*/
++ priv->gpu_regulator = regulator_get(pdev, "cpu_vddgpu");
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ priv->gpu_regulator = devm_regulator_get(pdev, "pu");
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if (IS_ERR(priv->gpu_regulator)) {
++ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER,
++ "%s(%d): Failed to get gpu regulator \n",
++ __FUNCTION__, __LINE__);
++ return gcvSTATUS_NOT_FOUND;
++ }
++#endif
++#endif
++
++ /*Initialize the clock structure*/
++ priv->clk_3d_core = clk_get(pdev, "gpu3d_clk");
++ if (!IS_ERR(priv->clk_3d_core)) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (cpu_is_mx6q()) {
++ priv->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(priv->clk_3d_shader)) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ priv->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++ }
++#else
++ priv->clk_3d_axi = clk_get(pdev, "gpu3d_axi_clk");
++ priv->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk");
++ if (IS_ERR(priv->clk_3d_shader)) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ priv->clk_3d_shader = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n");
++ }
++#endif
++ } else {
++ priv->clk_3d_core = NULL;
++ gckOS_Print("galcore: clk_get gpu3d_clk failed, disable 3d!\n");
++ }
++
++ priv->clk_2d_core = clk_get(pdev, "gpu2d_clk");
++ if (IS_ERR(priv->clk_2d_core)) {
++ priv->clk_2d_core = NULL;
++ gckOS_Print("galcore: clk_get 2d core clock failed, disable 2d/vg!\n");
++ } else {
++ priv->clk_2d_axi = clk_get(pdev, "gpu2d_axi_clk");
++ if (IS_ERR(priv->clk_2d_axi)) {
++ priv->clk_2d_axi = NULL;
++ gckOS_Print("galcore: clk_get 2d axi clock failed, disable 2d\n");
++ }
++
++ priv->clk_vg_axi = clk_get(pdev, "openvg_axi_clk");
++ if (IS_ERR(priv->clk_vg_axi)) {
++ priv->clk_vg_axi = NULL;
++ gckOS_Print("galcore: clk_get vg clock failed, disable vg!\n");
++ }
++ }
++
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ pdevice = Platform->device;
++ REG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++ {
++ int ret = 0;
++ ret = driver_create_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock);
++ if(ret)
++ dev_err(&pdevice->dev, "create gpu3DMinClock attr failed (%d)\n", ret);
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_PutPower(
++ IN gckPLATFORM Platform
++ )
++{
++ struct imx_priv *priv = Platform->priv;
++
++ /*Disable clock*/
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ if (priv->clk_3d_axi) {
++ clk_put(priv->clk_3d_axi);
++ priv->clk_3d_axi = NULL;
++ }
++#endif
++ if (priv->clk_3d_core) {
++ clk_put(priv->clk_3d_core);
++ priv->clk_3d_core = NULL;
++ }
++ if (priv->clk_3d_shader) {
++ clk_put(priv->clk_3d_shader);
++ priv->clk_3d_shader = NULL;
++ }
++ if (priv->clk_2d_core) {
++ clk_put(priv->clk_2d_core);
++ priv->clk_2d_core = NULL;
++ }
++ if (priv->clk_2d_axi) {
++ clk_put(priv->clk_2d_axi);
++ priv->clk_2d_axi = NULL;
++ }
++ if (priv->clk_vg_axi) {
++ clk_put(priv->clk_vg_axi);
++ priv->clk_vg_axi = NULL;
++ }
++
++#ifdef CONFIG_PM
++ if(priv->pmdev)
++ pm_runtime_disable(priv->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (priv->gpu_regulator) {
++ regulator_put(priv->gpu_regulator);
++ priv->gpu_regulator = NULL;
++ }
++#endif
++
++#if gcdENABLE_FSCALE_VAL_ADJUST
++ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier);
++
++ driver_remove_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock);
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_SetPower(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ )
++{
++ struct imx_priv* priv = Platform->priv;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ int ret;
++#endif
++#endif
++
++ if (Enable)
++ {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(priv->gpu_regulator)) {
++ ret = regulator_enable(priv->gpu_regulator);
++ if (ret != 0)
++ gckOS_Print("%s(%d): fail to enable pu regulator %d!\n",
++ __FUNCTION__, __LINE__, ret);
++ }
++#else
++ imx_gpc_power_up_pu(true);
++#endif
++#endif
++
++#ifdef CONFIG_PM
++ pm_runtime_get_sync(priv->pmdev);
++#endif
++ }
++ else
++ {
++#ifdef CONFIG_PM
++ pm_runtime_put_sync(priv->pmdev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ if(!IS_ERR(priv->gpu_regulator))
++ regulator_disable(priv->gpu_regulator);
++#else
++ imx_gpc_power_up_pu(false);
++#endif
++#endif
++
++ }
++
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_SetClock(
++ IN gckPLATFORM Platform,
++ IN gceCORE GPU,
++ IN gctBOOL Enable
++ )
++{
++ struct imx_priv* priv = Platform->priv;
++ struct clk *clk_3dcore = priv->clk_3d_core;
++ struct clk *clk_3dshader = priv->clk_3d_shader;
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct clk *clk_3d_axi = priv->clk_3d_axi;
++#endif
++ struct clk *clk_2dcore = priv->clk_2d_core;
++ struct clk *clk_2d_axi = priv->clk_2d_axi;
++ struct clk *clk_vg_axi = priv->clk_vg_axi;
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++ if (Enable) {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_enable(clk_3dcore);
++ if (cpu_is_mx6q())
++ clk_enable(clk_3dshader);
++ break;
++ case gcvCORE_2D:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_enable(clk_2dcore);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ } else {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ if (cpu_is_mx6q())
++ clk_disable(clk_3dshader);
++ clk_disable(clk_3dcore);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++#else
++ if (Enable) {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_prepare(clk_3dcore);
++ clk_enable(clk_3dcore);
++ clk_prepare(clk_3dshader);
++ clk_enable(clk_3dshader);
++ clk_prepare(clk_3d_axi);
++ clk_enable(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_2d_axi);
++ clk_enable(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_prepare(clk_2dcore);
++ clk_enable(clk_2dcore);
++ clk_prepare(clk_vg_axi);
++ clk_enable(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ } else {
++ switch (GPU) {
++ case gcvCORE_MAJOR:
++ clk_disable(clk_3dshader);
++ clk_unprepare(clk_3dshader);
++ clk_disable(clk_3dcore);
++ clk_unprepare(clk_3dcore);
++ clk_disable(clk_3d_axi);
++ clk_unprepare(clk_3d_axi);
++ break;
++ case gcvCORE_2D:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_2d_axi);
++ clk_unprepare(clk_2d_axi);
++ break;
++ case gcvCORE_VG:
++ clk_disable(clk_2dcore);
++ clk_unprepare(clk_2dcore);
++ clk_disable(clk_vg_axi);
++ clk_unprepare(clk_vg_axi);
++ break;
++ default:
++ break;
++ }
++ }
++#endif
++
++ return gcvSTATUS_OK;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++#ifdef CONFIG_PM
++static int gpu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int gpu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static struct dev_pm_ops gpu_pm_ops;
++#endif
++#endif
++
++gceSTATUS
++_AdjustDriver(
++ IN gckPLATFORM Platform
++ )
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ struct platform_driver * driver = Platform->driver;
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ driver->driver.of_match_table = mxs_gpu_dt_ids;
++#endif
++
++ /* Override PM callbacks to add runtime PM callbacks. */
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,5,0)
++ /* Fill local structure with original value. */
++ memcpy(&gpu_pm_ops, driver->driver.pm, sizeof(struct dev_pm_ops));
++
++ /* Add runtime PM callback. */
++#ifdef CONFIG_PM_RUNTIME
++ gpu_pm_ops.runtime_suspend = gpu_runtime_suspend;
++ gpu_pm_ops.runtime_resume = gpu_runtime_resume;
++ gpu_pm_ops.runtime_idle = NULL;
++#endif
++
++ /* Replace callbacks. */
++ driver->driver.pm = &gpu_pm_ops;
++#endif
++ return gcvSTATUS_OK;
++}
++
++gceSTATUS
++_Reset(
++ IN gckPLATFORM Platform,
++ gceCORE GPU
++ )
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0)
++#define SRC_SCR_OFFSET 0
++#define BP_SRC_SCR_GPU3D_RST 1
++#define BP_SRC_SCR_GPU2D_RST 4
++ void __iomem *src_base = IO_ADDRESS(SRC_BASE_ADDR);
++ gctUINT32 bit_offset,val;
++
++ if(GPU == gcvCORE_MAJOR) {
++ bit_offset = BP_SRC_SCR_GPU3D_RST;
++ } else if((GPU == gcvCORE_VG)
++ ||(GPU == gcvCORE_2D)) {
++ bit_offset = BP_SRC_SCR_GPU2D_RST;
++ } else {
++ return gcvSTATUS_INVALID_CONFIG;
++ }
++ val = __raw_readl(src_base + SRC_SCR_OFFSET);
++ val &= ~(1 << (bit_offset));
++ val |= (1 << (bit_offset));
++ __raw_writel(val, src_base + SRC_SCR_OFFSET);
++
++ while ((__raw_readl(src_base + SRC_SCR_OFFSET) &
++ (1 << (bit_offset))) != 0) {
++ }
++
++ return gcvSTATUS_NOT_SUPPORTED;
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)
++ struct imx_priv* priv = Platform->priv;
++ struct reset_control *rstc = priv->rstc[GPU];
++ if (rstc)
++ reset_control_reset(rstc);
++#else
++ imx_src_reset_gpu((int)GPU);
++#endif
++ return gcvSTATUS_OK;
++}
++
++gcsPLATFORM_OPERATIONS platformOperations = {
++ .adjustParam = gckPLATFORM_AdjustParam,
++ .allocPriv = _AllocPriv,
++ .freePriv = _FreePriv,
++ .getPower = _GetPower,
++ .putPower = _PutPower,
++ .setPower = _SetPower,
++ .setClock = _SetClock,
++ .adjustDriver = _AdjustDriver,
++ .reset = _Reset,
++#ifdef CONFIG_GPU_LOW_MEMORY_KILLER
++ .shrinkMemory = _ShrinkMemory,
++#endif
++};
++
++void
++gckPLATFORM_QueryOperations(
++ IN gcsPLATFORM_OPERATIONS ** Operations
++ )
++{
++ *Operations = &platformOperations;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/hal/os/linux/kernel/platform/freescale/gc_hal_kernel_platform_imx6q14.config 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,15 @@
++EXTRA_CFLAGS += -DgcdDEFAULT_CONTIGUOUS_SIZE=134217728
++
++ifneq ($(CONFIG_ANDROID),)
++# build for android
++EXTRA_CFLAGS += -DgcdANDROID_NATIVE_FENCE_SYNC=3
++
++ifeq ($(CONFIG_SYNC),)
++$(warn CONFIG_SYNC is not set in kernel config)
++$(warn Android native fence sync needs CONFIG_SYNC)
++endif
++endif
++
++EXTRA_CFLAGS += -DLINUX_CMA_FSL=1
++ALLOCATOR_ARRAY_H_LOCATION := $(OS_KERNEL_DIR)/allocator/freescale
++CUSTOMER_ALLOCATOR_OBJS := $(ALLOCATOR_ARRAY_H_LOCATION)/gc_hal_kernel_allocator_cma.o
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/Kbuild linux-3.14.72/drivers/mxc/gpu-viv/Kbuild
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/Kbuild 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/Kbuild 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,272 @@
++##############################################################################
++#
++# Copyright (C) 2005 - 2014 by Vivante Corp.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 2 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not write to the Free Software
++# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++#
++##############################################################################
++
++
++#
++# Linux build file for kernel HAL driver.
++#
++
++AQROOT := $(srctree)/drivers/mxc/gpu-viv
++
++include $(AQROOT)/config
++
++KERNEL_DIR ?= $(TOOL_DIR)/kernel
++
++OS_KERNEL_DIR := hal/os/linux/kernel
++ARCH_KERNEL_DIR := hal/kernel/arch
++ARCH_VG_KERNEL_DIR := hal/kernel/archvg
++HAL_KERNEL_DIR := hal/kernel
++
++# Check and include platform config.
++ifneq ($(PLATFORM),)
++
++# Get platform config path.
++PLATFORM_CONFIG ?= $(AQROOT)/$(OS_KERNEL_DIR)/platform/$(PLATFORM).config
++
++# Check whether it exists.
++PLATFORM_CONFIG := $(wildcard $(PLATFORM_CONFIG))
++
++# Include it if exists.
++ifneq ($(PLATFORM_CONFIG),)
++include $(PLATFORM_CONFIG)
++endif
++
++endif
++
++MODULE_NAME ?= galcore
++CUSTOMER_ALLOCATOR_OBJS ?=
++ALLOCATOR_ARRAY_H_LOCATION ?= $(OS_KERNEL_DIR)/allocator/default/
++
++EXTRA_CFLAGS += -Werror
++
++OBJS := $(OS_KERNEL_DIR)/gc_hal_kernel_device.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_linux.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_math.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_os.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_debugfs.o \
++ $(OS_KERNEL_DIR)/gc_hal_kernel_allocator.o \
++
++ifneq ($(CONFIG_IOMMU_SUPPORT),)
++OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_iommu.o
++endif
++
++ifneq ($(PLATFORM),)
++OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_probe.o
++OBJS += $(OS_KERNEL_DIR)/platform/$(PLATFORM).o
++else
++OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_driver.o
++endif
++
++OBJS += $(HAL_KERNEL_DIR)/gc_hal_kernel.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_command.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_db.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_debug.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_event.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_heap.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_mmu.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_video_memory.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_power.o
++
++OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_context.o \
++ $(ARCH_KERNEL_DIR)/gc_hal_kernel_hardware.o
++
++ifeq ($(VIVANTE_ENABLE_3D), 1)
++OBJS += $(ARCH_KERNEL_DIR)/gc_hal_kernel_recorder.o
++endif
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++OBJS +=\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_command_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_interrupt_vg.o\
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_mmu_vg.o\
++ $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_command_vg.o\
++ $(ARCH_VG_KERNEL_DIR)/gc_hal_kernel_hardware_vg.o
++endif
++
++ifneq ($(CONFIG_SYNC),)
++EXTRA_CFLAGS += -Idrivers/staging/android
++
++OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_sync.o
++endif
++
++ifeq ($(SECURITY), 1)
++OBJS += $(OS_KERNEL_DIR)/gc_hal_kernel_security_channel.o \
++ $(HAL_KERNEL_DIR)/gc_hal_kernel_security.o
++endif
++
++ifneq ($(CUSTOMER_ALLOCATOR_OBJS),)
++OBJS += $(CUSTOMER_ALLOCATOR_OBJS)
++endif
++
++ifeq ($(KERNELRELEASE), )
++
++.PHONY: all clean install
++
++# Define targets.
++all:
++ @make V=$(V) ARCH=$(ARCH_TYPE) -C $(KERNEL_DIR) SUBDIRS=`pwd` modules
++
++clean:
++ @rm -rf $(OBJS)
++ @rm -rf modules.order Module.symvers
++ @find $(AQROOT) -name ".gc_*.cmd" | xargs rm -f
++
++install: all
++ @mkdir -p $(SDK_DIR)/drivers
++
++else
++
++
++EXTRA_CFLAGS += -DLINUX -DDRIVER
++
++ifeq ($(FLAREON),1)
++EXTRA_CFLAGS += -DFLAREON
++endif
++
++ifeq ($(DEBUG), 1)
++EXTRA_CFLAGS += -DDBG=1 -DDEBUG -D_DEBUG
++else
++EXTRA_CFLAGS += -DDBG=0
++endif
++
++ifeq ($(NO_DMA_COHERENT), 1)
++EXTRA_CFLAGS += -DNO_DMA_COHERENT
++endif
++
++ifeq ($(CONFIG_DOVE_GPU), 1)
++EXTRA_CFLAGS += -DCONFIG_DOVE_GPU=1
++endif
++
++ifneq ($(USE_PLATFORM_DRIVER), 0)
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1
++else
++EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0
++endif
++
++EXTRA_CFLAGS += -DVIVANTE_PROFILER=1
++EXTRA_CFLAGS += -DVIVANTE_PROFILER_CONTEXT=1
++
++ifeq ($(ENABLE_GPU_CLOCK_BY_DRIVER), 1)
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=1
++else
++EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=0
++endif
++
++ifeq ($(USE_NEW_LINUX_SIGNAL), 1)
++EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=1
++else
++EXTRA_CFLAGS += -DUSE_NEW_LINUX_SIGNAL=0
++endif
++
++ifeq ($(FORCE_ALL_VIDEO_MEMORY_CACHED), 1)
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_CACHEABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=0
++endif
++
++ifeq ($(NONPAGED_MEMORY_BUFFERABLE), 1)
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=1
++else
++EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=0
++endif
++
++ifeq ($(CACHE_FUNCTION_UNIMPLEMENTED), 1)
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=1
++else
++EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=0
++endif
++
++ifeq ($(CONFIG_SMP), y)
++EXTRA_CFLAGS += -DgcdSMP=1
++else
++EXTRA_CFLAGS += -DgcdSMP=0
++endif
++
++ifeq ($(VIVANTE_ENABLE_3D),0)
++EXTRA_CFLAGS += -DgcdENABLE_3D=0
++else
++EXTRA_CFLAGS += -DgcdENABLE_3D=1
++endif
++
++ifeq ($(VIVANTE_ENABLE_2D),0)
++EXTRA_CFLAGS += -DgcdENABLE_2D=0
++else
++EXTRA_CFLAGS += -DgcdENABLE_2D=1
++endif
++
++ifeq ($(VIVANTE_ENABLE_VG),0)
++EXTRA_CFLAGS += -DgcdENABLE_VG=0
++else
++EXTRA_CFLAGS += -DgcdENABLE_VG=1
++endif
++
++ifeq ($(ENABLE_OUTER_CACHE_PATCH), 1)
++EXTRA_CFLAGS += -DgcdENABLE_OUTER_CACHE_PATCH=1
++else
++EXTRA_CFLAGS += -DgcdENABLE_OUTER_CACHE_PATCH=0
++endif
++
++ifeq ($(USE_BANK_ALIGNMENT), 1)
++ EXTRA_CFLAGS += -DgcdENABLE_BANK_ALIGNMENT=1
++ ifneq ($(BANK_BIT_START), 0)
++ ifneq ($(BANK_BIT_END), 0)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_START=$(BANK_BIT_START)
++ EXTRA_CFLAGS += -DgcdBANK_BIT_END=$(BANK_BIT_END)
++ endif
++ endif
++
++ ifneq ($(BANK_CHANNEL_BIT), 0)
++ EXTRA_CFLAGS += -DgcdBANK_CHANNEL_BIT=$(BANK_CHANNEL_BIT)
++ endif
++endif
++
++ifeq ($(gcdFPGA_BUILD), 1)
++EXTRA_CFLAGS += -DgcdFPGA_BUILD=1
++else
++EXTRA_CFLAGS += -DgcdFPGA_BUILD=0
++endif
++
++ifeq ($(SECURITY), 1)
++EXTRA_CFLAGS += -DgcdSECURITY=1
++endif
++
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel/inc
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel/arch
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel/inc
++EXTRA_CFLAGS += -I$(AQROOT)/hal/os/linux/kernel
++EXTRA_CFLAGS += -I$(AQROOT)/$(ALLOCATOR_ARRAY_H_LOCATION)
++
++ifeq ($(VIVANTE_ENABLE_VG), 1)
++EXTRA_CFLAGS += -I$(AQROOT)/hal/kernel/archvg
++endif
++
++obj-$(CONFIG_MXC_GPU_VIV) += galcore.o
++
++galcore-objs := $(OBJS)
++
++endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/gpu-viv/Kconfig linux-3.14.72/drivers/mxc/gpu-viv/Kconfig
+--- linux-3.14.72.orig/drivers/mxc/gpu-viv/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/gpu-viv/Kconfig 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,9 @@
++menu "MXC Vivante GPU support"
++ depends on SOC_IMX6Q && !VIVANTE_GALCORE
++
++config MXC_GPU_VIV
++ tristate "MXC Vivante GPU support"
++ ---help---
++ Say Y to get the GPU driver support.
++
++endmenu
+diff -Nur linux-3.14.72.orig/drivers/mxc/hdmi-cec/Kconfig linux-3.14.72/drivers/mxc/hdmi-cec/Kconfig
+--- linux-3.14.72.orig/drivers/mxc/hdmi-cec/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/hdmi-cec/Kconfig 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,11 @@
++
++menu "MXC HDMI CEC (Consumer Electronics Control) support"
++
++config MXC_HDMI_CEC
++ tristate "Support for MXC HDMI CEC (Consumer Electronics Control)"
++ depends on MFD_MXC_HDMI
++ depends on FB_MXC_HDMI
++ help
++ The HDMI CEC device implement low level protocol on i.MX6x platforms.
++
++endmenu
+diff -Nur linux-3.14.72.orig/drivers/mxc/hdmi-cec/Makefile linux-3.14.72/drivers/mxc/hdmi-cec/Makefile
+--- linux-3.14.72.orig/drivers/mxc/hdmi-cec/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/hdmi-cec/Makefile 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1 @@
++obj-$(CONFIG_MXC_HDMI_CEC) += mxc_hdmi-cec.o
+diff -Nur linux-3.14.72.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c linux-3.14.72/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c
+--- linux-3.14.72.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/hdmi-cec/mxc_hdmi-cec.c 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,628 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_hdmi-cec.c
++ *
++ * @brief HDMI CEC system initialization and file operation implementation
++ *
++ * @ingroup HDMI
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/fs.h>
++#include <linux/stat.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/vmalloc.h>
++#include <linux/workqueue.h>
++#include <linux/sizes.h>
++
++#include <linux/console.h>
++#include <linux/types.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/pinctrl/consumer.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "mxc_hdmi-cec.h"
++
++
++#define MAX_MESSAGE_LEN 17
++
++#define MESSAGE_TYPE_RECEIVE_SUCCESS 1
++#define MESSAGE_TYPE_NOACK 2
++#define MESSAGE_TYPE_DISCONNECTED 3
++#define MESSAGE_TYPE_CONNECTED 4
++#define MESSAGE_TYPE_SEND_SUCCESS 5
++
++#define CEC_TX_INPROGRESS -1
++#define CEC_TX_AVAIL 0
++
++struct hdmi_cec_priv {
++ int receive_error;
++ int send_error;
++ u8 Logical_address;
++ bool cec_state;
++ u8 last_msg[MAX_MESSAGE_LEN];
++ u8 msg_len;
++ int tx_answer;
++ u16 latest_cec_stat;
++ u8 link_status;
++ spinlock_t irq_lock;
++ struct delayed_work hdmi_cec_work;
++ struct mutex lock;
++};
++
++struct hdmi_cec_event {
++ int event_type;
++ int msg_len;
++ u8 msg[MAX_MESSAGE_LEN];
++ struct list_head list;
++};
++
++
++static LIST_HEAD(head);
++
++static int hdmi_cec_ready = 0;
++static int hdmi_cec_started;
++static int hdmi_cec_major;
++static struct class *hdmi_cec_class;
++static struct hdmi_cec_priv hdmi_cec_data;
++static u8 open_count;
++
++static wait_queue_head_t hdmi_cec_queue;
++static wait_queue_head_t tx_cec_queue;
++
++static irqreturn_t mxc_hdmi_cec_isr(int irq, void *data)
++{
++ struct hdmi_cec_priv *hdmi_cec = data;
++ u16 cec_stat = 0;
++ unsigned long flags;
++ u8 phy_stat0;
++
++ spin_lock_irqsave(&hdmi_cec->irq_lock, flags);
++
++ hdmi_writeb(0x7f, HDMI_IH_MUTE_CEC_STAT0);
++
++ cec_stat = hdmi_readb(HDMI_IH_CEC_STAT0);
++ hdmi_writeb(cec_stat, HDMI_IH_CEC_STAT0);
++ phy_stat0 = hdmi_readb(HDMI_PHY_STAT0) & 0x02;
++ if (hdmi_cec->link_status ^ phy_stat0) {
++ /* HPD value changed */
++ hdmi_cec->link_status = phy_stat0;
++ if (hdmi_cec->link_status)
++ cec_stat |= 0x80; /* Connected */
++ else
++ cec_stat |= 0x100; /* Disconnected */
++ }
++ if ((cec_stat & (HDMI_IH_CEC_STAT0_ERROR_INIT | \
++ HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM | \
++ HDMI_IH_CEC_STAT0_DONE | 0x180)) == 0) {
++ spin_unlock_irqrestore(&hdmi_cec->irq_lock, flags);
++ return IRQ_HANDLED;
++ }
++ pr_debug("HDMI CEC interrupt received\n");
++ /* FIXME : there is a race with latest_cec_stat */
++ hdmi_cec->latest_cec_stat = cec_stat ;
++
++ schedule_delayed_work(&(hdmi_cec->hdmi_cec_work), msecs_to_jiffies(20));
++
++ spin_unlock_irqrestore(&hdmi_cec->irq_lock, flags);
++
++ return IRQ_HANDLED;
++}
++
++void mxc_hdmi_cec_handle(u16 cec_stat)
++{
++ u8 val = 0, i = 0;
++ struct hdmi_cec_event *event = NULL;
++ /*The current transmission is successful (for initiator only).*/
++ if (!open_count)
++ return;
++
++ if (cec_stat & HDMI_IH_CEC_STAT0_DONE) {
++ hdmi_cec_data.tx_answer = cec_stat;
++ wake_up(&tx_cec_queue);
++ }
++ /*EOM is detected so that the received data is ready in the receiver data buffer*/
++ if (cec_stat & HDMI_IH_CEC_STAT0_EOM) {
++ hdmi_writeb(0x02, HDMI_IH_CEC_STAT0);
++ event = vmalloc(sizeof(struct hdmi_cec_event));
++ if (NULL == event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ memset(event, 0, sizeof(struct hdmi_cec_event));
++ event->msg_len = hdmi_readb(HDMI_CEC_RX_CNT);
++ if (!event->msg_len) {
++ pr_err("%s: Invalid CEC message length!\n", __func__);
++ return;
++ }
++ event->event_type = MESSAGE_TYPE_RECEIVE_SUCCESS;
++ for (i = 0; i < event->msg_len; i++)
++ event->msg[i] = hdmi_readb(HDMI_CEC_RX_DATA0+i);
++ hdmi_writeb(0x0, HDMI_CEC_LOCK);
++ mutex_lock(&hdmi_cec_data.lock);
++ list_add_tail(&event->list, &head);
++ mutex_unlock(&hdmi_cec_data.lock);
++ wake_up(&hdmi_cec_queue);
++ }
++ /*An error is detected on cec line (for initiator only). */
++ if (cec_stat & HDMI_IH_CEC_STAT0_ERROR_INIT) {
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.send_error++;
++ if (hdmi_cec_data.send_error > 2) {
++ pr_err("%s:Re-transmission is attempted more than 2 times!\n", __func__);
++ hdmi_cec_data.send_error = 0;
++ mutex_unlock(&hdmi_cec_data.lock);
++ hdmi_cec_data.tx_answer = cec_stat;
++ wake_up(&tx_cec_queue);
++ return;
++ }
++ for (i = 0; i < hdmi_cec_data.msg_len; i++)
++ hdmi_writeb(hdmi_cec_data.last_msg[i], HDMI_CEC_TX_DATA0+i);
++ hdmi_writeb(hdmi_cec_data.msg_len, HDMI_CEC_TX_CNT);
++ val = hdmi_readb(HDMI_CEC_CTRL);
++ val |= 0x01;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++ mutex_unlock(&hdmi_cec_data.lock);
++ }
++ /*A frame is not acknowledged in a directly addressed message. Or a frame is negatively acknowledged in
++ a broadcast message (for initiator only).*/
++ if (cec_stat & HDMI_IH_CEC_STAT0_NACK) {
++ hdmi_cec_data.tx_answer = cec_stat;
++ wake_up(&tx_cec_queue);
++ }
++ /*An error is notified by a follower. Abnormal logic data bit error (for follower).*/
++ if (cec_stat & HDMI_IH_CEC_STAT0_ERROR_FOLL) {
++ hdmi_cec_data.receive_error++;
++ }
++ /*HDMI cable connected*/
++ if (cec_stat & 0x80) {
++ pr_info("HDMI link connected\n");
++ event = vmalloc(sizeof(struct hdmi_cec_event));
++ if (NULL == event) {
++ pr_err("%s: Not enough memory\n", __func__);
++ return;
++ }
++ memset(event, 0, sizeof(struct hdmi_cec_event));
++ event->event_type = MESSAGE_TYPE_CONNECTED;
++ mutex_lock(&hdmi_cec_data.lock);
++ list_add_tail(&event->list, &head);
++ mutex_unlock(&hdmi_cec_data.lock);
++ wake_up(&hdmi_cec_queue);
++ }
++ /*HDMI cable disconnected*/
++ if (cec_stat & 0x100) {
++ pr_info("HDMI link disconnected\n");
++ event = vmalloc(sizeof(struct hdmi_cec_event));
++ if (NULL == event) {
++ pr_err("%s: Not enough memory!\n", __func__);
++ return;
++ }
++ memset(event, 0, sizeof(struct hdmi_cec_event));
++ event->event_type = MESSAGE_TYPE_DISCONNECTED;
++ mutex_lock(&hdmi_cec_data.lock);
++ list_add_tail(&event->list, &head);
++ mutex_unlock(&hdmi_cec_data.lock);
++ wake_up(&hdmi_cec_queue);
++ }
++ return;
++}
++EXPORT_SYMBOL(mxc_hdmi_cec_handle);
++static void mxc_hdmi_cec_worker(struct work_struct *work)
++{
++ u8 val;
++ mxc_hdmi_cec_handle(hdmi_cec_data.latest_cec_stat);
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ARB_LOST;
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++}
++
++/*!
++ * @brief open function for cec file operation
++ *
++ * @return 0 on success or negative error code on error
++ */
++static int hdmi_cec_open(struct inode *inode, struct file *filp)
++{
++ mutex_lock(&hdmi_cec_data.lock);
++ if (open_count) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EBUSY;
++ }
++ open_count = 1;
++ filp->private_data = (void *)(&hdmi_cec_data);
++ hdmi_cec_data.Logical_address = 15;
++ hdmi_cec_data.cec_state = false;
++ mutex_unlock(&hdmi_cec_data.lock);
++ return 0;
++}
++
++static ssize_t hdmi_cec_read(struct file *file, char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ struct hdmi_cec_event *event = NULL;
++ pr_debug("function : %s\n", __func__);
++
++ if (!open_count)
++ return -ENODEV;
++ mutex_lock(&hdmi_cec_data.lock);
++ if (false == hdmi_cec_data.cec_state) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EACCES;
++ }
++
++ if (list_empty(&head)) {
++ if (file->f_flags & O_NONBLOCK) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EAGAIN;
++ } else {
++ do {
++ mutex_unlock(&hdmi_cec_data.lock);
++ if (wait_event_interruptible(hdmi_cec_queue, (!list_empty(&head))))
++ return -ERESTARTSYS;
++ mutex_lock(&hdmi_cec_data.lock);
++ } while (list_empty(&head));
++ }
++ }
++
++ event = list_first_entry(&head, struct hdmi_cec_event, list);
++ list_del(&event->list);
++ mutex_unlock(&hdmi_cec_data.lock);
++ if (copy_to_user(buf, event,
++ sizeof(struct hdmi_cec_event) - sizeof(struct list_head))) {
++ vfree(event);
++ return -EFAULT;
++ }
++ vfree(event);
++ return (sizeof(struct hdmi_cec_event) - sizeof(struct list_head));
++}
++
++static ssize_t hdmi_cec_write(struct file *file, const char __user *buf,
++ size_t count, loff_t *ppos)
++{
++ int ret = 0 , i = 0;
++ u8 msg[MAX_MESSAGE_LEN];
++ u8 msg_len = 0, val = 0;
++
++ pr_debug("function : %s\n", __func__);
++
++ if (!open_count)
++ return -ENODEV;
++ mutex_lock(&hdmi_cec_data.lock);
++ if (false == hdmi_cec_data.cec_state) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EACCES;
++ }
++ /* Ensure that there is only one writer who is the only listener of tx_cec_queue */
++ if (hdmi_cec_data.tx_answer != CEC_TX_AVAIL) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ return -EBUSY;
++ }
++ mutex_unlock(&hdmi_cec_data.lock);
++ if (count > MAX_MESSAGE_LEN)
++ return -EINVAL;
++ memset(&msg, 0, MAX_MESSAGE_LEN);
++ ret = copy_from_user(&msg, buf, count);
++ if (ret)
++ return -EACCES;
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.send_error = 0;
++ hdmi_cec_data.tx_answer = CEC_TX_INPROGRESS;
++ msg_len = count;
++ hdmi_writeb(msg_len, HDMI_CEC_TX_CNT);
++ for (i = 0; i < msg_len; i++)
++ hdmi_writeb(msg[i], HDMI_CEC_TX_DATA0+i);
++ val = hdmi_readb(HDMI_CEC_CTRL);
++ val |= 0x01;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++ memcpy(hdmi_cec_data.last_msg, msg, msg_len);
++ hdmi_cec_data.msg_len = msg_len;
++ mutex_unlock(&hdmi_cec_data.lock);
++
++ ret = wait_event_interruptible_timeout(tx_cec_queue, hdmi_cec_data.tx_answer != CEC_TX_INPROGRESS, HZ);
++
++ if (ret < 0) {
++ ret = -ERESTARTSYS;
++ goto tx_out;
++ }
++
++ if (hdmi_cec_data.tx_answer & HDMI_IH_CEC_STAT0_DONE)
++ /* msg correctly sent */
++ ret = msg_len;
++ else
++ ret = -EIO;
++
++ tx_out:
++ hdmi_cec_data.tx_answer = CEC_TX_AVAIL;
++ return ret;
++}
++
++void hdmi_cec_start_device(void)
++{
++ u8 val;
++
++ if (!hdmi_cec_ready || hdmi_cec_started)
++ return;
++
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++ hdmi_writeb(0x02, HDMI_CEC_CTRL);
++ /* Force read unlock */
++ hdmi_writeb(0x0, HDMI_CEC_LOCK);
++ val = HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM | HDMI_IH_CEC_STAT0_DONE;
++ hdmi_writeb(val, HDMI_CEC_POLARITY);
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ARB_LOST;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_cec_data.link_status = hdmi_readb(HDMI_PHY_STAT0) & 0x02;
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.cec_state = true;
++ mutex_unlock(&hdmi_cec_data.lock);
++
++ hdmi_cec_started = 1;
++}
++EXPORT_SYMBOL(hdmi_cec_start_device);
++
++void hdmi_cec_stop_device(void)
++{
++ u8 val;
++
++ if (!hdmi_cec_ready || !hdmi_cec_started)
++ return;
++
++ hdmi_writeb(0x10, HDMI_CEC_CTRL);
++ val = HDMI_IH_CEC_STAT0_WAKEUP | HDMI_IH_CEC_STAT0_ERROR_FOLL | HDMI_IH_CEC_STAT0_ERROR_INIT | HDMI_IH_CEC_STAT0_ARB_LOST | \
++ HDMI_IH_CEC_STAT0_NACK | HDMI_IH_CEC_STAT0_EOM | HDMI_IH_CEC_STAT0_DONE;
++ hdmi_writeb(val, HDMI_CEC_MASK);
++ hdmi_writeb(val, HDMI_IH_MUTE_CEC_STAT0);
++ hdmi_writeb(0x0, HDMI_CEC_POLARITY);
++ val = hdmi_readb(HDMI_MC_CLKDIS);
++ val |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ hdmi_writeb(val, HDMI_MC_CLKDIS);
++ mutex_lock(&hdmi_cec_data.lock);
++ hdmi_cec_data.cec_state = false;
++ mutex_unlock(&hdmi_cec_data.lock);
++
++ hdmi_cec_started = 0;
++}
++EXPORT_SYMBOL(hdmi_cec_stop_device);
++
++/*!
++ * @brief IO ctrl function for vpu file operation
++ * @param cmd IO ctrl command
++ * @return 0 on success or negative error code on error
++ */
++static long hdmi_cec_ioctl(struct file *filp, u_int cmd,
++ u_long arg)
++{
++ int ret = 0, status = 0;
++ u8 val = 0, msg = 0;
++ struct mxc_edid_cfg hdmi_edid_cfg;
++ pr_debug("function : %s\n", __func__);
++ if (!open_count)
++ return -ENODEV;
++ switch (cmd) {
++ case HDMICEC_IOC_SETLOGICALADDRESS:
++ mutex_lock(&hdmi_cec_data.lock);
++ if (false == hdmi_cec_data.cec_state) {
++ mutex_unlock(&hdmi_cec_data.lock);
++ pr_err("Trying to set logical address while not started\n");
++ return -EACCES;
++ }
++ hdmi_cec_data.Logical_address = (u8)arg;
++ if (hdmi_cec_data.Logical_address <= 7) {
++ val = 1 << hdmi_cec_data.Logical_address;
++ hdmi_writeb(val, HDMI_CEC_ADDR_L);
++ hdmi_writeb(0, HDMI_CEC_ADDR_H);
++ } else if (hdmi_cec_data.Logical_address > 7 && hdmi_cec_data.Logical_address <= 15) {
++ val = 1 << (hdmi_cec_data.Logical_address - 8);
++ hdmi_writeb(val, HDMI_CEC_ADDR_H);
++ hdmi_writeb(0, HDMI_CEC_ADDR_L);
++ } else
++ ret = -EINVAL;
++ /*Send Polling message with same source and destination address*/
++ if (0 == ret && 15 != hdmi_cec_data.Logical_address) {
++ msg = (hdmi_cec_data.Logical_address << 4)|hdmi_cec_data.Logical_address;
++ hdmi_writeb(1, HDMI_CEC_TX_CNT);
++ hdmi_writeb(msg, HDMI_CEC_TX_DATA0);
++ val = hdmi_readb(HDMI_CEC_CTRL);
++ val |= 0x01;
++ hdmi_writeb(val, HDMI_CEC_CTRL);
++ }
++ mutex_unlock(&hdmi_cec_data.lock);
++ break;
++ case HDMICEC_IOC_STARTDEVICE:
++ hdmi_cec_start_device();
++ break;
++ case HDMICEC_IOC_STOPDEVICE:
++ hdmi_cec_stop_device();
++ break;
++ case HDMICEC_IOC_GETPHYADDRESS:
++ hdmi_get_edid_cfg(&hdmi_edid_cfg);
++ status = copy_to_user((void __user *)arg,
++ &hdmi_edid_cfg.physical_address,
++ 4*sizeof(u8));
++ if (status)
++ ret = -EFAULT;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++ return ret;
++}
++
++/*!
++ * @brief Release function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int hdmi_cec_release(struct inode *inode, struct file *filp)
++{
++ mutex_lock(&hdmi_cec_data.lock);
++ if (open_count) {
++ open_count = 0;
++ hdmi_cec_data.cec_state = false;
++ hdmi_cec_data.Logical_address = 15;
++ }
++ mutex_unlock(&hdmi_cec_data.lock);
++
++ return 0;
++}
++
++static unsigned int hdmi_cec_poll(struct file *file, poll_table *wait)
++{
++ unsigned int mask = 0;
++
++ pr_debug("function : %s\n", __func__);
++
++ poll_wait(file, &hdmi_cec_queue, wait);
++
++ /* Always writable */
++ mask = (POLLOUT | POLLWRNORM);
++ mutex_lock(&hdmi_cec_data.lock);
++ if (!list_empty(&head))
++ mask |= (POLLIN | POLLRDNORM);
++ mutex_unlock(&hdmi_cec_data.lock);
++ return mask;
++}
++
++
++const struct file_operations hdmi_cec_fops = {
++ .owner = THIS_MODULE,
++ .read = hdmi_cec_read,
++ .write = hdmi_cec_write,
++ .open = hdmi_cec_open,
++ .unlocked_ioctl = hdmi_cec_ioctl,
++ .release = hdmi_cec_release,
++ .poll = hdmi_cec_poll,
++};
++
++static int hdmi_cec_dev_probe(struct platform_device *pdev)
++{
++ int err = 0;
++ struct device *temp_class;
++ struct resource *res;
++ struct pinctrl *pinctrl;
++ int irq = platform_get_irq(pdev, 0);
++
++ hdmi_cec_major = register_chrdev(hdmi_cec_major, "mxc_hdmi_cec", &hdmi_cec_fops);
++ if (hdmi_cec_major < 0) {
++ dev_err(&pdev->dev, "hdmi_cec: unable to get a major for HDMI CEC\n");
++ err = -EBUSY;
++ goto out;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (unlikely(res == NULL)) {
++ dev_err(&pdev->dev, "hdmi_cec:No HDMI irq line provided\n");
++ goto err_out_chrdev;
++ }
++ spin_lock_init(&hdmi_cec_data.irq_lock);
++
++ err = devm_request_irq(&pdev->dev, irq, mxc_hdmi_cec_isr, IRQF_SHARED,
++ dev_name(&pdev->dev), &hdmi_cec_data);
++ if (err < 0) {
++ dev_err(&pdev->dev, "hdmi_cec:Unable to request irq: %d\n", err);
++ goto err_out_chrdev;
++ }
++
++ hdmi_cec_class = class_create(THIS_MODULE, "mxc_hdmi_cec");
++ if (IS_ERR(hdmi_cec_class)) {
++ err = PTR_ERR(hdmi_cec_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(hdmi_cec_class, NULL, MKDEV(hdmi_cec_major, 0),
++ NULL, "mxc_hdmi_cec");
++ if (IS_ERR(temp_class)) {
++ err = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "can't get/select CEC pinctrl\n");
++ goto err_out_class;
++ }
++
++ init_waitqueue_head(&hdmi_cec_queue);
++ init_waitqueue_head(&tx_cec_queue);
++
++ INIT_LIST_HEAD(&head);
++
++ mutex_init(&hdmi_cec_data.lock);
++ hdmi_cec_data.Logical_address = 15;
++ hdmi_cec_data.tx_answer = CEC_TX_AVAIL;
++ platform_set_drvdata(pdev, &hdmi_cec_data);
++ INIT_DELAYED_WORK(&hdmi_cec_data.hdmi_cec_work, mxc_hdmi_cec_worker);
++
++ dev_info(&pdev->dev, "HDMI CEC initialized\n");
++ hdmi_cec_ready = 1;
++ goto out;
++
++err_out_class:
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++err_out_chrdev:
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++out:
++ return err;
++}
++
++static int hdmi_cec_dev_remove(struct platform_device *pdev)
++{
++ if (hdmi_cec_data.cec_state)
++ hdmi_cec_stop_device();
++ if (hdmi_cec_major > 0) {
++ device_destroy(hdmi_cec_class, MKDEV(hdmi_cec_major, 0));
++ class_destroy(hdmi_cec_class);
++ unregister_chrdev(hdmi_cec_major, "mxc_hdmi_cec");
++ hdmi_cec_major = 0;
++}
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_cec_match[] = {
++ { .compatible = "fsl,imx6q-hdmi-cec", },
++ { .compatible = "fsl,imx6dl-hdmi-cec", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mxc_hdmi_cec_driver = {
++ .probe = hdmi_cec_dev_probe,
++ .remove = hdmi_cec_dev_remove,
++ .driver = {
++ .name = "mxc_hdmi_cec",
++ .of_match_table = imx_hdmi_cec_match,
++ },
++};
++
++module_platform_driver(mxc_hdmi_cec_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Linux HDMI CEC driver for Freescale i.MX/MXC");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:mxc_hdmi_cec");
++
+diff -Nur linux-3.14.72.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h linux-3.14.72/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h
+--- linux-3.14.72.orig/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/hdmi-cec/mxc_hdmi-cec.h 2016-06-19 22:11:55.249143681 +0200
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef _HDMICEC_H_
++#define _HDMICEC_H_
++#include <linux/ioctl.h>
++
++/*
++ * Ioctl definitions
++ */
++
++/* Use 'k' as magic number */
++#define HDMICEC_IOC_MAGIC 'H'
++/*
++ * S means "Set" through a ptr,
++ * T means "Tell" directly with the argument value
++ * G means "Get": reply by setting through a pointer
++ * Q means "Query": response is on the return value
++ * X means "eXchange": G and S atomically
++ * H means "sHift": T and Q atomically
++ */
++#define HDMICEC_IOC_SETLOGICALADDRESS \
++ _IOW(HDMICEC_IOC_MAGIC, 1, unsigned char)
++#define HDMICEC_IOC_STARTDEVICE _IO(HDMICEC_IOC_MAGIC, 2)
++#define HDMICEC_IOC_STOPDEVICE _IO(HDMICEC_IOC_MAGIC, 3)
++#define HDMICEC_IOC_GETPHYADDRESS \
++ _IOR(HDMICEC_IOC_MAGIC, 4, unsigned char[4])
++
++#endif /* !_HDMICEC_H_ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c linux-3.14.72/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_calc_stripes_sizes.c 2016-06-19 22:11:55.253143418 +0200
+@@ -0,0 +1,495 @@
++/*
++ * Copyright 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_calc_stripes_sizes.c
++ *
++ * @brief IPU IC functions
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/math64.h>
++
++#define BPP_32 0
++#define BPP_16 3
++#define BPP_8 5
++#define BPP_24 1
++#define BPP_12 4
++#define BPP_18 2
++
++static u32 truncate(u32 up, /* 0: down; else: up */
++ u64 a, /* must be non-negative */
++ u32 b)
++{
++ u32 d;
++ u64 div;
++ div = div_u64(a, b);
++ d = b * (div >> 32);
++ if (up && (a > (((u64)d) << 32)))
++ return d+b;
++ else
++ return d;
++}
++
++static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
++{/* return input_f */
++ unsigned int f_calculated = 0;
++ switch (pfs) {
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV444P:
++ f_calculated = 16;
++ break;
++
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ f_calculated = 8;
++ break;
++
++ case IPU_PIX_FMT_NV12:
++ f_calculated = 8;
++ break;
++
++ default:
++ f_calculated = 0;
++ break;
++
++ }
++ if (!f_calculated) {
++ switch (bpp) {
++ case BPP_32:
++ f_calculated = 2;
++ break;
++
++ case BPP_16:
++ f_calculated = 4;
++ break;
++
++ case BPP_8:
++ case BPP_24:
++ f_calculated = 8;
++ break;
++
++ case BPP_12:
++ f_calculated = 16;
++ break;
++
++ case BPP_18:
++ f_calculated = 32;
++ break;
++
++ default:
++ f_calculated = 0;
++ break;
++ }
++ }
++ return f_calculated;
++}
++
++
++static unsigned int m_calc(unsigned int pfs)
++{
++ unsigned int m_calculated = 0;
++ switch (pfs) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV444P:
++ m_calculated = 16;
++ break;
++
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ m_calculated = 8;
++ break;
++
++ default:
++ m_calculated = 8;
++ break;
++
++ }
++ return m_calculated;
++}
++
++static int calc_split_resize_coeffs(unsigned int inSize, unsigned int outSize,
++ unsigned int *resizeCoeff,
++ unsigned int *downsizeCoeff)
++{
++ uint32_t tempSize;
++ uint32_t tempDownsize;
++
++ if (inSize > 4096) {
++ pr_debug("IC input size(%d) cannot exceed 4096\n",
++ inSize);
++ return -EINVAL;
++ }
++
++ if (outSize > 1024) {
++ pr_debug("IC output size(%d) cannot exceed 1024\n",
++ outSize);
++ return -EINVAL;
++ }
++
++ if ((outSize << 3) < inSize) {
++ pr_debug("IC cannot downsize more than 8:1\n");
++ return -EINVAL;
++ }
++
++ /* Compute downsizing coefficient */
++ /* Output of downsizing unit cannot be more than 1024 */
++ tempDownsize = 0;
++ tempSize = inSize;
++ while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
++ (tempDownsize < 2)) {
++ tempSize >>= 1;
++ tempDownsize++;
++ }
++ *downsizeCoeff = tempDownsize;
++
++ /* compute resizing coefficient using the following equation:
++ resizeCoeff = M*(SI -1)/(SO - 1)
++ where M = 2^13, SI - input size, SO - output size */
++ *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
++ if (*resizeCoeff >= 16384L) {
++ pr_debug("Overflow on IC resize coefficient.\n");
++ return -EINVAL;
++ }
++
++ pr_debug("resizing from %u -> %u pixels, "
++ "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
++ *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
++ ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
++
++ return 0;
++}
++
++/* Stripe parameters calculator */
++/**************************************************************************
++Notes:
++MSW = the maximal width allowed for a stripe
++ i.MX31: 720, i.MX35: 800, i.MX37/51/53: 1024
++cirr = the maximal inverse resizing ratio for which overlap in the input
++ is requested; typically cirr~2
++flags
++ bit 0 - equal_stripes
++ 0 each stripe is allowed to have independent parameters
++ for maximal image quality
++ 1 the stripes are requested to have identical parameters
++ (except the base address), for maximal performance
++ bit 1 - vertical/horizontal
++ 0 horizontal
++ 1 vertical
++
++If performance is the top priority (above image quality)
++ Avoid overlap, by setting CIRR = 0
++ This will also force effectively identical_stripes = 1
++ Choose IF & OF that corresponds to the same IOX/SX for both stripes
++ Choose IFW & OFW such that
++ IFW/IM, IFW/IF, OFW/OM, OFW/OF are even integers
++ The function returns an error status:
++ 0: no error
++ 1: invalid input parameters -> aborted without result
++ Valid parameters should satisfy the following conditions
++ IFW <= OFW, otherwise downsizing is required
++ - which is not supported yet
++ 4 <= IFW,OFW, so some interpolation may be needed even without overlap
++ IM, OM, IF, OF should not vanish
++ 2*IF <= IFW
++ so the frame can be split to two equal stripes, even without overlap
++ 2*(OF+IF/irr_opt) <= OFW
++ so a valid positive INW exists even for equal stripes
++ OF <= MSW, otherwise, the left stripe cannot be sufficiently large
++ MSW < OFW, so splitting to stripes is required
++ OFW <= 2*MSW, so two stripes are sufficient
++ (this also implies that 2<=MSW)
++ 2: OF is not a multiple of OM - not fully-supported yet
++ Output is produced but OW is not guaranited to be a multiple of OM
++ 4: OFW reduced to be a multiple of OM
++ 8: CIRR > 1: truncated to 1
++ Overlap is not supported (and not needed) y for upsizing)
++**************************************************************************/
++int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
++ /* input frame width;>1 */
++ unsigned int output_frame_width, /* output frame width; >1 */
++ const unsigned int maximal_stripe_width,
++ /* the maximal width allowed for a stripe */
++ const unsigned long long cirr, /* see above */
++ const unsigned int flags, /* see above */
++ u32 input_pixelformat,/* pixel format after of read channel*/
++ u32 output_pixelformat,/* pixel format after of write channel*/
++ struct stripe_param *left,
++ struct stripe_param *right)
++{
++ const unsigned int irr_frac_bits = 13;
++ const unsigned long irr_steps = 1 << irr_frac_bits;
++ const u64 dirr = ((u64)1) << (32 - 2);
++ /* The maximum relative difference allowed between the irrs */
++ const u64 cr = ((u64)4) << 32;
++ /* The importance ratio between the two terms in the cost function below */
++
++ unsigned int status;
++ unsigned int temp;
++ unsigned int onw_min;
++ unsigned int inw = 0, onw = 0, inw_best = 0;
++ /* number of pixels in the left stripe NOT hidden by the right stripe */
++ u64 irr_opt; /* the optimal inverse resizing ratio */
++ u64 rr_opt; /* the optimal resizing ratio = 1/irr_opt*/
++ u64 dinw; /* the misalignment between the stripes */
++ /* (measured in units of input columns) */
++ u64 difwl, difwr = 0;
++ /* The number of input columns not reflected in the output */
++ /* the resizing ratio used for the right stripe is */
++ /* left->irr and right->irr respectively */
++ u64 cost, cost_min;
++ u64 div; /* result of division */
++ bool equal_stripes = (flags & 0x1) != 0;
++ bool vertical = (flags & 0x2) != 0;
++
++ unsigned int input_m, input_f, output_m, output_f; /* parameters for upsizing by stripes */
++ unsigned int resize_coeff;
++ unsigned int downsize_coeff;
++
++ status = 0;
++
++ if (vertical) {
++ input_f = 2;
++ input_m = 8;
++ output_f = 8;
++ output_m = 2;
++ } else {
++ input_f = f_calc(input_pixelformat, 0, NULL);
++ input_m = m_calc(input_pixelformat);
++ output_f = input_m;
++ output_m = m_calc(output_pixelformat);
++ }
++ if ((input_frame_width < 4) || (output_frame_width < 4))
++ return 1;
++
++ irr_opt = div_u64((((u64)(input_frame_width)) << 32),
++ (output_frame_width));
++ rr_opt = div_u64((((u64)(output_frame_width)) << 32),
++ input_frame_width);
++
++ if ((input_m == 0) || (output_m == 0) || (input_f == 0) || (output_f == 0)
++ || (input_frame_width < (2 * input_f))
++ || ((((u64)output_frame_width) << 32) <
++ (2 * ((((u64)output_f) << 32) + (input_f * rr_opt))))
++ || (maximal_stripe_width < output_f)
++ || ((output_frame_width <= maximal_stripe_width)
++ && (equal_stripes == 0))
++ || ((2 * maximal_stripe_width) < output_frame_width))
++ return 1;
++
++ if (output_f % output_m)
++ status += 2;
++
++ temp = truncate(0, (((u64)output_frame_width) << 32), output_m);
++ if (temp < output_frame_width) {
++ output_frame_width = temp;
++ status += 4;
++ }
++
++ pr_debug("---------------->\n"
++ "if = %d\n"
++ "im = %d\n"
++ "of = %d\n"
++ "om = %d\n"
++ "irr_opt = %llu\n"
++ "rr_opt = %llu\n"
++ "cirr = %llu\n"
++ "pixel in = %08x\n"
++ "pixel out = %08x\n"
++ "ifw = %d\n"
++ "ofwidth = %d\n",
++ input_f,
++ input_m,
++ output_f,
++ output_m,
++ irr_opt,
++ rr_opt,
++ cirr,
++ input_pixelformat,
++ output_pixelformat,
++ input_frame_width,
++ output_frame_width
++ );
++
++ if (equal_stripes) {
++ if ((irr_opt > cirr) /* overlap in the input is not requested */
++ && ((input_frame_width % (input_m << 1)) == 0)
++ && ((input_frame_width % (input_f << 1)) == 0)
++ && ((output_frame_width % (output_m << 1)) == 0)
++ && ((output_frame_width % (output_f << 1)) == 0)) {
++ /* without overlap */
++ left->input_width = right->input_width = right->input_column =
++ input_frame_width >> 1;
++ left->output_width = right->output_width = right->output_column =
++ output_frame_width >> 1;
++ left->input_column = 0;
++ left->output_column = 0;
++ div = div_u64(((((u64)irr_steps) << 32) *
++ (right->input_width - 1)), (right->output_width - 1));
++ left->irr = right->irr = truncate(0, div, 1);
++ } else { /* with overlap */
++ onw = truncate(0, (((u64)output_frame_width) << 32) >> 1,
++ output_f);
++ inw = truncate(0, onw * irr_opt, input_f);
++ /* this is the maximal inw which allows the same resizing ratio */
++ /* in both stripes */
++ onw = truncate(1, (inw * rr_opt), output_f);
++ div = div_u64((((u64)(irr_steps * inw)) <<
++ 32), onw);
++ left->irr = right->irr = truncate(0, div, 1);
++ left->output_width = right->output_width =
++ output_frame_width - onw;
++ /* These are valid assignments for output_width, */
++ /* assuming output_f is a multiple of output_m */
++ div = (((u64)(left->output_width-1) * (left->irr)) << 32);
++ div = (((u64)1) << 32) + div_u64(div, irr_steps);
++
++ left->input_width = right->input_width = truncate(1, div, input_m);
++
++ div = div_u64((((u64)((right->output_width - 1) * right->irr)) <<
++ 32), irr_steps);
++ difwr = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
++ div = div_u64((difwr + (((u64)input_f) << 32)), 2);
++ left->input_column = truncate(0, div, input_f);
++
++
++ /* This splits the truncated input columns evenly */
++ /* between the left and right margins */
++ right->input_column = left->input_column + inw;
++ left->output_column = 0;
++ right->output_column = onw;
++ }
++ if (left->input_width > left->output_width) {
++ if (calc_split_resize_coeffs(left->input_width,
++ left->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++
++ if (downsize_coeff > 0) {
++ left->irr = right->irr =
++ (downsize_coeff << 14) | resize_coeff;
++ }
++ }
++ pr_debug("inw %d, onw %d, ilw %d, ilc %d, olw %d,"
++ " irw %d, irc %d, orw %d, orc %d, "
++ "difwr %llu, lirr %u\n",
++ inw, onw, left->input_width,
++ left->input_column, left->output_width,
++ right->input_width, right->input_column,
++ right->output_width,
++ right->output_column, difwr, left->irr);
++ } else { /* independent stripes */
++ onw_min = output_frame_width - maximal_stripe_width;
++ /* onw is a multiple of output_f, in the range */
++ /* [max(output_f,output_frame_width-maximal_stripe_width),*/
++ /*min(output_frame_width-2,maximal_stripe_width)] */
++ /* definitely beyond the cost of any valid setting */
++ cost_min = (((u64)input_frame_width) << 32) + cr;
++ onw = truncate(0, ((u64)maximal_stripe_width), output_f);
++ if (output_frame_width - onw == 1)
++ onw -= output_f; /* => onw and output_frame_width-1-onw are positive */
++ inw = truncate(0, onw * irr_opt, input_f);
++ /* this is the maximal inw which allows the same resizing ratio */
++ /* in both stripes */
++ onw = truncate(1, inw * rr_opt, output_f);
++ do {
++ div = div_u64((((u64)(irr_steps * inw)) << 32), onw);
++ left->irr = truncate(0, div, 1);
++ div = div_u64((((u64)(onw * left->irr)) << 32),
++ irr_steps);
++ dinw = (((u64)inw) << 32) - div;
++
++ div = div_u64((((u64)((output_frame_width - 1 - onw) * left->irr)) <<
++ 32), irr_steps);
++
++ difwl = (((u64)(input_frame_width - 1 - inw)) << 32) - div;
++
++ cost = difwl + (((u64)(cr * dinw)) >> 32);
++
++ if (cost < cost_min) {
++ inw_best = inw;
++ cost_min = cost;
++ }
++
++ inw -= input_f;
++ onw = truncate(1, inw * rr_opt, output_f);
++ /* This is the minimal onw which allows the same resizing ratio */
++ /* in both stripes */
++ } while (onw >= onw_min);
++
++ inw = inw_best;
++ onw = truncate(1, inw * rr_opt, output_f);
++ div = div_u64((((u64)(irr_steps * inw)) << 32), onw);
++ left->irr = truncate(0, div, 1);
++
++ left->output_width = onw;
++ right->output_width = output_frame_width - onw;
++ /* These are valid assignments for output_width, */
++ /* assuming output_f is a multiple of output_m */
++ left->input_width = truncate(1, ((u64)(inw + 1)) << 32, input_m);
++ right->input_width = truncate(1, ((u64)(input_frame_width - inw)) <<
++ 32, input_m);
++
++ div = div_u64((((u64)(irr_steps * (input_frame_width - 1 - inw))) <<
++ 32), (right->output_width - 1));
++ right->irr = truncate(0, div, 1);
++ temp = truncate(0, ((u64)left->irr) * ((((u64)1) << 32) + dirr), 1);
++ if (temp < right->irr)
++ right->irr = temp;
++ div = div_u64(((u64)((right->output_width - 1) * right->irr) <<
++ 32), irr_steps);
++ difwr = (u64)(input_frame_width - 1 - inw) - div;
++
++
++ div = div_u64((difwr + (((u64)input_f) << 32)), 2);
++ left->input_column = truncate(0, div, input_f);
++
++ /* This splits the truncated input columns evenly */
++ /* between the left and right margins */
++ right->input_column = left->input_column + inw;
++ left->output_column = 0;
++ right->output_column = onw;
++ if (left->input_width > left->output_width) {
++ if (calc_split_resize_coeffs(left->input_width,
++ left->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++ left->irr = (downsize_coeff << 14) | resize_coeff;
++ }
++ if (right->input_width > right->output_width) {
++ if (calc_split_resize_coeffs(right->input_width,
++ right->output_width,
++ &resize_coeff,
++ &downsize_coeff) < 0)
++ return -EINVAL;
++ right->irr = (downsize_coeff << 14) | resize_coeff;
++ }
++ }
++ return status;
++}
++EXPORT_SYMBOL(ipu_calc_stripes_sizes);
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_capture.c linux-3.14.72/drivers/mxc/ipu3/ipu_capture.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_capture.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_capture.c 2016-06-19 22:11:55.253143418 +0200
+@@ -0,0 +1,888 @@
++/*
++ * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_capture.c
++ *
++ * @brief IPU capture dase functions
++ *
++ * @ingroup IPU
++ */
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include "ipu_prv.h"
++#include "ipu_regs.h"
++
++/*!
++ * _ipu_csi_mclk_set
++ *
++ * @param ipu ipu handler
++ * @param pixel_clk desired pixel clock frequency in Hz
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_mclk_set(struct ipu_soc *ipu, uint32_t pixel_clk, uint32_t csi)
++{
++ uint32_t temp;
++ uint32_t div_ratio;
++
++ div_ratio = (clk_get_rate(ipu->ipu_clk) / pixel_clk) - 1;
++
++ if (div_ratio > 0xFF || div_ratio < 0) {
++ dev_dbg(ipu->dev, "value of pixel_clk extends normal range\n");
++ return -EINVAL;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
++ temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
++ ipu_csi_write(ipu, csi, temp |
++ (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
++ CSI_SENS_CONF);
++
++ return 0;
++}
++
++/*!
++ * ipu_csi_init_interface
++ * Sets initial values for the CSI registers.
++ * The width and height of the sensor and the actual frame size will be
++ * set to the same values.
++ * @param ipu ipu handler
++ * @param width Sensor width
++ * @param height Sensor height
++ * @param pixel_fmt pixel format
++ * @param cfg_param ipu_csi_signal_cfg_t structure
++ * @param csi csi 0 or csi 1
++ *
++ * @return 0 for success, -EINVAL for error
++ */
++int32_t
++ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
++ uint32_t pixel_fmt, ipu_csi_signal_cfg_t cfg_param)
++{
++ uint32_t data = 0;
++ uint32_t csi = cfg_param.csi;
++
++ /* Set SENS_DATA_FORMAT bits (8, 9 and 10)
++ RGB or YUV444 is 0 which is current value in data so not set
++ explicitly
++ This is also the default value if attempts are made to set it to
++ something invalid. */
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_YUYV:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
++ break;
++ case IPU_PIX_FMT_UYVY:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
++ break;
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_BGR24:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB_YUV444;
++ break;
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_GENERIC_16:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
++ break;
++ case IPU_PIX_FMT_RGB565:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
++ break;
++ case IPU_PIX_FMT_RGB555:
++ cfg_param.data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
++ break;
++ default:
++ dev_dbg(ipu->dev, "%s:pixel_fmt=%x\n", __func__, pixel_fmt);
++ return -EINVAL;
++ }
++
++ /* Set the CSI_SENS_CONF register remaining fields */
++ data |= cfg_param.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
++ cfg_param.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
++ cfg_param.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
++ cfg_param.Vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
++ cfg_param.Hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
++ cfg_param.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
++ cfg_param.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
++ cfg_param.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
++ cfg_param.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
++ cfg_param.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
++ cfg_param.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu_csi_write(ipu, csi, data, CSI_SENS_CONF);
++
++ /* Setup sensor frame size */
++
++ dev_dbg(ipu->dev, "%s: %dx%d\n", __func__, width, height);
++
++ /* Set CCIR registers */
++ ipu_csi_write(ipu, csi,
++ (cfg_param.data_width == IPU_CSI_DATA_WIDTH_10) ?
++ 0x03FF00000 : 0x00FF0000, CSI_CCIR_CODE_3);
++ if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE) {
++/*
++ * bit 5-3: start of blanking line command
++ * bit 18-16: End of active line command
++ * bit 21-19: start of active line command
++ * 10 bit mode of GS2971 interleaves this streams, giving
++ * 0x3ff,0x3ff,0x000,0x000,0x000,0x000,xy,xy
++ * so, it cannot be used in 656 mode. It needs 1120 mode.
++ */
++ ipu_csi_write(ipu, csi, (6 << 3) | (4 << 16), CSI_CCIR_CODE_1);
++ } else if (cfg_param.clk_mode == IPU_CSI_CLK_MODE_CCIR656_INTERLACED) {
++ if (width == 720 && height <= 525) {
++ /* NTSC case */
++ /*
++ * Field0BlankEnd = 0x7, Field0BlankStart = 0x3,
++ * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1
++ */
++ ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1);
++ /*
++ * Field1BlankEnd = 0x6, Field1BlankStart = 0x2,
++ * Field1ActiveEnd = 0x4, Field1ActiveStart = 0
++ */
++ ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2);
++ } else if (width == 720 && height <= 625) {
++ /* PAL case */
++ /*
++ * Field0BlankEnd = 0x6, Field0BlankStart = 0x2,
++ * Field0ActiveEnd = 0x4, Field0ActiveStart = 0
++ */
++ ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1);
++ /*
++ * Field1BlankEnd = 0x7, Field1BlankStart = 0x3,
++ * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1
++ */
++ ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2);
++ } else {
++ dev_err(ipu->dev, "Unsupported CCIR656 interlaced "
++ "video mode\n");
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return -EINVAL;
++ }
++ _ipu_csi_ccir_err_detection_enable(ipu, csi);
++ } else if ((cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR) ||
++ (cfg_param.clk_mode ==
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR)) {
++ ipu_csi_write(ipu, csi, (6 << 3) | (4 << 16), CSI_CCIR_CODE_1);
++ _ipu_csi_ccir_err_detection_enable(ipu, csi);
++ } else if ((cfg_param.clk_mode == IPU_CSI_CLK_MODE_GATED_CLK) ||
++ (cfg_param.clk_mode == IPU_CSI_CLK_MODE_NONGATED_CLK)) {
++ ipu_csi_write(ipu, csi, (6 << 3) | (4 << 16), CSI_CCIR_CODE_1);
++ _ipu_csi_ccir_err_detection_disable(ipu, csi);
++ }
++
++ dev_dbg(ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
++ ipu_csi_read(ipu, csi, CSI_SENS_CONF));
++ dev_dbg(ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
++ ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_csi_init_interface);
++
++/*!
++ * ipu_csi_get_sensor_protocol
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns sensor protocol
++ */
++int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi)
++{
++ int ret;
++ _ipu_get(ipu);
++ ret = (ipu_csi_read(ipu, csi, CSI_SENS_CONF) &
++ CSI_SENS_CONF_SENS_PRTCL_MASK) >>
++ CSI_SENS_CONF_SENS_PRTCL_SHIFT;
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_csi_get_sensor_protocol);
++
++/*!
++ * ipu_csi_enable_mclk
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ * @param flag true to enable mclk, false to disable mclk
++ * @param wait true to wait 100ms make clock stable, false not wait
++ *
++ * @return Returns 0 on success
++ */
++int ipu_csi_enable_mclk(struct ipu_soc *ipu, int csi, bool flag, bool wait)
++{
++ /* Return immediately if there is no csi_clk to manage */
++ if (ipu->csi_clk[csi] == NULL)
++ return 0;
++
++ if (flag) {
++ clk_enable(ipu->csi_clk[csi]);
++ if (wait == true)
++ msleep(10);
++ } else {
++ clk_disable(ipu->csi_clk[csi]);
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_csi_enable_mclk);
++
++/*!
++ * ipu_csi_get_window_size
++ *
++ * @param ipu ipu handler
++ * @param width pointer to window width
++ * @param height pointer to window height
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi)
++{
++ uint32_t reg;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ reg = ipu_csi_read(ipu, csi, CSI_ACT_FRM_SIZE);
++ *width = (reg & 0xFFFF) + 1;
++ *height = (reg >> 16 & 0xFFFF) + 1;
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_get_window_size);
++
++/*!
++ * ipu_csi_set_window_size
++ *
++ * @param ipu ipu handler
++ * @param width window width
++ * @param height window height
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi)
++{
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_set_window_size);
++
++/*!
++ * ipu_csi_set_window_pos
++ *
++ * @param ipu ipu handler
++ * @param left uint32 window x start
++ * @param top uint32 window y start
++ * @param csi csi 0 or csi 1
++ */
++void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi)
++{
++ uint32_t temp;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
++ temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT));
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_set_window_pos);
++
++void ipu_csi_window_size_crop(struct ipu_soc *ipu, uint32_t swidth, uint32_t sheight,
++ uint32_t width, uint32_t height, uint32_t left, uint32_t top, uint32_t csi)
++{
++ uint32_t temp;
++
++ if ((left >= (1 << 13)) || (top >= (1 << 12))) {
++ pr_err("%s: Error left=%x top=%x\n", __func__, left, top);
++ left = 0;
++ top = 0;
++ swidth = width;
++ sheight = height;
++ }
++ _ipu_get(ipu);
++
++ /*
++ * sheight >= top + height
++ * swidth >= left + width, unless interlaced
++ * left = # of lines/field if interlaced
++ */
++ mutex_lock(&ipu->mutex_lock);
++ ipu_csi_write(ipu, csi, (swidth - 1) | (sheight - 1) << 16, CSI_SENS_FRM_SIZE);
++ ipu_csi_write(ipu, csi, (width - 1) | (height - 1) << 16, CSI_ACT_FRM_SIZE);
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
++ temp |= ((top << CSI_VSC_SHIFT) | (left << CSI_HSC_SHIFT));
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_csi_window_size_crop);
++
++/*!
++ * _ipu_csi_horizontal_downsize_enable
++ * Enable horizontal downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_horizontal_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp |= CSI_HORI_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_horizontal_downsize_disable
++ * Disable horizontal downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_horizontal_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~CSI_HORI_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_vertical_downsize_enable
++ * Enable vertical downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_vertical_downsize_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp |= CSI_VERT_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_vertical_downsize_disable
++ * Disable vertical downsizing(decimation) by 2.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_vertical_downsize_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_OUT_FRM_CTRL);
++ temp &= ~CSI_VERT_DOWNSIZE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_OUT_FRM_CTRL);
++}
++
++/*!
++ * _ipu_csi_set_test_generator
++ *
++ * @param ipu ipu handler
++ * @param active 1 for active and 0 for inactive
++ * @param r_value red value for the generated pattern of even pixel
++ * @param g_value green value for the generated pattern of even
++ * pixel
++ * @param b_value blue value for the generated pattern of even pixel
++ * @param pixel_clk desired pixel clock frequency in Hz
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
++ uint32_t g_value, uint32_t b_value, uint32_t pix_clk, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_TST_CTRL);
++
++ if (active == false) {
++ temp &= ~CSI_TEST_GEN_MODE_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
++ } else {
++ /* Set sensb_mclk div_ratio*/
++ _ipu_csi_mclk_set(ipu, pix_clk, csi);
++
++ temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
++ CSI_TEST_GEN_B_MASK);
++ temp |= CSI_TEST_GEN_MODE_EN;
++ temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
++ (g_value << CSI_TEST_GEN_G_SHIFT) |
++ (b_value << CSI_TEST_GEN_B_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_TST_CTRL);
++ }
++}
++
++/*!
++ * _ipu_csi_ccir_err_detection_en
++ * Enable error detection and correction for
++ * CCIR interlaced mode with protection bit.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
++ temp |= CSI_CCIR_ERR_DET_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
++
++}
++
++/*!
++ * _ipu_csi_ccir_err_detection_disable
++ * Disable error detection and correction for
++ * CCIR interlaced mode with protection bit.
++ *
++ * @param ipu ipu handler
++ * @param csi csi 0 or csi 1
++ */
++void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_csi_read(ipu, csi, CSI_CCIR_CODE_1);
++ temp &= ~CSI_CCIR_ERR_DET_EN;
++ ipu_csi_write(ipu, csi, temp, CSI_CCIR_CODE_1);
++
++}
++
++/*!
++ * _ipu_csi_set_mipi_di
++ *
++ * @param ipu ipu handler
++ * @param num MIPI data identifier 0-3 handled by CSI
++ * @param di_val data identifier value
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (di_val > 0xFFL) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_MIPI_DI);
++
++ switch (num) {
++ case IPU_CSI_MIPI_DI0:
++ temp &= ~CSI_MIPI_DI0_MASK;
++ temp |= (di_val << CSI_MIPI_DI0_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI1:
++ temp &= ~CSI_MIPI_DI1_MASK;
++ temp |= (di_val << CSI_MIPI_DI1_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI2:
++ temp &= ~CSI_MIPI_DI2_MASK;
++ temp |= (di_val << CSI_MIPI_DI2_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ case IPU_CSI_MIPI_DI3:
++ temp &= ~CSI_MIPI_DI3_MASK;
++ temp |= (di_val << CSI_MIPI_DI3_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_MIPI_DI);
++ break;
++ default:
++ retval = -EINVAL;
++ }
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_csi_set_skip_isp
++ *
++ * @param ipu ipu handler
++ * @param skip select frames to be skipped and set the
++ * correspond bits to 1
++ * @param max_ratio number of frames in a skipping set and the
++ * maximum value of max_ratio is 5
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_skip_isp(struct ipu_soc *ipu, uint32_t skip, uint32_t max_ratio, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (max_ratio > 5) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SKIP);
++ temp &= ~(CSI_MAX_RATIO_SKIP_ISP_MASK | CSI_SKIP_ISP_MASK);
++ temp |= (max_ratio << CSI_MAX_RATIO_SKIP_ISP_SHIFT) |
++ (skip << CSI_SKIP_ISP_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_SKIP);
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_csi_set_skip_smfc
++ *
++ * @param ipu ipu handler
++ * @param skip select frames to be skipped and set the
++ * correspond bits to 1
++ * @param max_ratio number of frames in a skipping set and the
++ * maximum value of max_ratio is 5
++ * @param id csi to smfc skipping id
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_set_skip_smfc(struct ipu_soc *ipu, uint32_t skip,
++ uint32_t max_ratio, uint32_t id, uint32_t csi)
++{
++ uint32_t temp;
++ int retval = 0;
++
++ if (max_ratio > 5 || id > 3) {
++ retval = -EINVAL;
++ goto err;
++ }
++
++ temp = ipu_csi_read(ipu, csi, CSI_SKIP);
++ temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
++ CSI_SKIP_SMFC_MASK);
++ temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
++ (id << CSI_ID_2_SKIP_SHIFT) |
++ (skip << CSI_SKIP_SMFC_SHIFT);
++ ipu_csi_write(ipu, csi, temp, CSI_SKIP);
++
++err:
++ return retval;
++}
++
++/*!
++ * _ipu_smfc_init
++ * Map CSI frames to IDMAC channels.
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param mipi_id mipi id number 0-3
++ * @param csi csi0 or csi1
++ */
++void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_MAP);
++
++ switch (channel) {
++ case CSI_MEM0:
++ temp &= ~SMFC_MAP_CH0_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH0_SHIFT;
++ break;
++ case CSI_MEM1:
++ temp &= ~SMFC_MAP_CH1_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH1_SHIFT;
++ break;
++ case CSI_MEM2:
++ temp &= ~SMFC_MAP_CH2_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH2_SHIFT;
++ break;
++ case CSI_MEM3:
++ temp &= ~SMFC_MAP_CH3_MASK;
++ temp |= ((csi << 2) | mipi_id) << SMFC_MAP_CH3_SHIFT;
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_MAP);
++}
++
++/*!
++ * _ipu_smfc_set_wmc
++ * Caution: The number of required channels, the enabled channels
++ * and the FIFO size per channel are configured restrictedly.
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param set set 1 or clear 0
++ * @param level water mark level when FIFO is on the
++ * relative size
++ */
++void _ipu_smfc_set_wmc(struct ipu_soc *ipu, ipu_channel_t channel, bool set, uint32_t level)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_WMC);
++
++ switch (channel) {
++ case CSI_MEM0:
++ if (set == true) {
++ temp &= ~SMFC_WM0_SET_MASK;
++ temp |= level << SMFC_WM0_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM0_CLR_MASK;
++ temp |= level << SMFC_WM0_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM1:
++ if (set == true) {
++ temp &= ~SMFC_WM1_SET_MASK;
++ temp |= level << SMFC_WM1_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM1_CLR_MASK;
++ temp |= level << SMFC_WM1_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM2:
++ if (set == true) {
++ temp &= ~SMFC_WM2_SET_MASK;
++ temp |= level << SMFC_WM2_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM2_CLR_MASK;
++ temp |= level << SMFC_WM2_CLR_SHIFT;
++ }
++ break;
++ case CSI_MEM3:
++ if (set == true) {
++ temp &= ~SMFC_WM3_SET_MASK;
++ temp |= level << SMFC_WM3_SET_SHIFT;
++ } else {
++ temp &= ~SMFC_WM3_CLR_MASK;
++ temp |= level << SMFC_WM3_CLR_SHIFT;
++ }
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_WMC);
++}
++
++/*!
++ * _ipu_smfc_set_burst_size
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel 0-3
++ * @param bs burst size of IDMAC channel,
++ * the value programmed here shoud be BURST_SIZE-1
++ */
++void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs)
++{
++ uint32_t temp;
++
++ temp = ipu_smfc_read(ipu, SMFC_BS);
++
++ switch (channel) {
++ case CSI_MEM0:
++ temp &= ~SMFC_BS0_MASK;
++ temp |= bs << SMFC_BS0_SHIFT;
++ break;
++ case CSI_MEM1:
++ temp &= ~SMFC_BS1_MASK;
++ temp |= bs << SMFC_BS1_SHIFT;
++ break;
++ case CSI_MEM2:
++ temp &= ~SMFC_BS2_MASK;
++ temp |= bs << SMFC_BS2_SHIFT;
++ break;
++ case CSI_MEM3:
++ temp &= ~SMFC_BS3_MASK;
++ temp |= bs << SMFC_BS3_SHIFT;
++ break;
++ default:
++ return;
++ }
++
++ ipu_smfc_write(ipu, temp, SMFC_BS);
++}
++
++/*!
++ * _ipu_csi_init
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel
++ * @param csi csi 0 or csi 1
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi)
++{
++ uint32_t csi_sens_conf, csi_dest;
++ int retval = 0;
++ uint32_t ctrl = ipu_csi_read(ipu, csi, CSI_CPD_CTRL) & ~0x13;
++
++ csi_sens_conf = ipu_csi_read(ipu, csi, CSI_SENS_CONF);
++ csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ csi_dest = CSI_DATA_DEST_IDMAC;
++
++ if (((csi_sens_conf >> CSI_SENS_CONF_DATA_WIDTH_SHIFT) & 0x0f) == IPU_CSI_DATA_WIDTH_10) {
++ /* Send to compander before memory to reduce to 8 bits */
++ /* y = Min[255, (y1[k] + (((x-x1[k])*slope[k])>>6 + 1))>>1] */
++ int i;
++
++ ctrl |= (1 << 4);
++ ipu_csi_write(ipu, csi, 0, CSI_CPD_OFFSET1);
++ ipu_csi_write(ipu, csi, 0, CSI_CPD_OFFSET2);
++ for (i = 0; i < 16; i += 2) {
++ uint32_t c = ((i+1) << (16 + 5)) | (i << (0 + 5));
++
++ ipu_csi_write(ipu, csi, c, CSI_CPD_RC((i >> 1)));
++ ipu_csi_write(ipu, csi, c, CSI_CPD_GRC((i >> 1)));
++ ipu_csi_write(ipu, csi, c, CSI_CPD_GBC((i >> 1)));
++ ipu_csi_write(ipu, csi, c, CSI_CPD_BC((i >> 1)));
++ }
++ for (i = 0; i < 16; i += 4) {
++ uint32_t slope = 1 << 5;
++ uint32_t s = (slope << 24) | (slope << 16) | (slope << 8) | (slope << 0);
++ ipu_csi_write(ipu, csi, s, CSI_CPD_RS((i >> 2)));
++ ipu_csi_write(ipu, csi, s, CSI_CPD_GRS((i >> 2)));
++ ipu_csi_write(ipu, csi, s, CSI_CPD_GBS((i >> 2)));
++ ipu_csi_write(ipu, csi, s, CSI_CPD_BS((i >> 2)));
++ }
++ }
++ break;
++ case CSI_PRP_ENC_MEM:
++ case CSI_PRP_VF_MEM:
++ csi_dest = CSI_DATA_DEST_IC;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++ csi_sens_conf |= csi_dest << CSI_SENS_CONF_DATA_DEST_SHIFT;
++
++ dev_dbg(ipu->dev, "%s:CSI_SENS_CONF: ipu=%p,csi=%x,data=%x\n", __func__,
++ ipu, csi, csi_sens_conf);
++ ipu_csi_write(ipu, csi, ctrl, CSI_CPD_CTRL);
++ ipu_csi_write(ipu, csi, csi_sens_conf, CSI_SENS_CONF);
++err:
++ return retval;
++}
++
++/*!
++ * csi_irq_handler
++ *
++ * @param irq interrupt id
++ * @param dev_id pointer to ipu handler
++ *
++ * @return Returns if irq is handled
++ */
++static irqreturn_t csi_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_soc *ipu = dev_id;
++ struct completion *comp = &ipu->csi_comp;
++
++ complete(comp);
++ return IRQ_HANDLED;
++}
++
++/*!
++ * _ipu_csi_wait4eof
++ *
++ * @param ipu ipu handler
++ * @param channel IDMAC channel
++ *
++ */
++void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int ret;
++ int irq = 0;
++
++ if (channel == CSI_MEM0)
++ irq = IPU_IRQ_CSI0_OUT_EOF;
++ else if (channel == CSI_MEM1)
++ irq = IPU_IRQ_CSI1_OUT_EOF;
++ else if (channel == CSI_MEM2)
++ irq = IPU_IRQ_CSI2_OUT_EOF;
++ else if (channel == CSI_MEM3)
++ irq = IPU_IRQ_CSI3_OUT_EOF;
++ else if (channel == CSI_PRP_ENC_MEM)
++ irq = IPU_IRQ_PRP_ENC_OUT_EOF;
++ else if (channel == CSI_PRP_VF_MEM)
++ irq = IPU_IRQ_PRP_VF_OUT_EOF;
++ else{
++ dev_err(ipu->dev, "Not a CSI channel\n");
++ return;
++ }
++
++ init_completion(&ipu->csi_comp);
++ ret = ipu_request_irq(ipu, irq, csi_irq_handler, 0, NULL, ipu);
++ if (ret < 0) {
++ dev_err(ipu->dev, "CSI irq %d in use\n", irq);
++ return;
++ }
++ ret = wait_for_completion_timeout(&ipu->csi_comp, msecs_to_jiffies(500));
++ ipu_free_irq(ipu, irq, ipu);
++ dev_dbg(ipu->dev, "CSI stop timeout - %d * 10ms\n", 5 - ret);
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_common.c linux-3.14.72/drivers/mxc/ipu3/ipu_common.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_common.c 2016-06-19 22:11:55.253143418 +0200
+@@ -0,0 +1,3189 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_common.c
++ *
++ * @brief This file contains the IPU driver common API functions.
++ *
++ * @ingroup IPU
++ */
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/irq.h>
++#include <linux/irqdesc.h>
++#include <linux/module.h>
++#include <linux/mod_devicetable.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include <asm/cacheflush.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM];
++int g_ipu_hw_rev;
++
++/* Static functions */
++static irqreturn_t ipu_sync_irq_handler(int irq, void *desc);
++static irqreturn_t ipu_err_irq_handler(int irq, void *desc);
++
++static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
++{
++ return ((uint32_t) ch >> (6 * type)) & 0x3F;
++};
++
++static inline int _ipu_is_ic_chan(uint32_t dma_chan)
++{
++ return (((dma_chan >= 11) && (dma_chan <= 22) && (dma_chan != 17) &&
++ (dma_chan != 18)));
++}
++
++static inline int _ipu_is_vdi_out_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 5);
++}
++
++static inline int _ipu_is_ic_graphic_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 14 || dma_chan == 15);
++}
++
++/* Either DP BG or DP FG can be graphic window */
++static inline int _ipu_is_dp_graphic_chan(uint32_t dma_chan)
++{
++ return (dma_chan == 23 || dma_chan == 27);
++}
++
++static inline int _ipu_is_irt_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 45) && (dma_chan <= 50));
++}
++
++static inline int _ipu_is_dmfc_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 23) && (dma_chan <= 29));
++}
++
++static inline int _ipu_is_smfc_chan(uint32_t dma_chan)
++{
++ return ((dma_chan >= 0) && (dma_chan <= 3));
++}
++
++static inline int _ipu_is_trb_chan(uint32_t dma_chan)
++{
++ return (((dma_chan == 8) || (dma_chan == 9) ||
++ (dma_chan == 10) || (dma_chan == 13) ||
++ (dma_chan == 21) || (dma_chan == 23) ||
++ (dma_chan == 27) || (dma_chan == 28)) &&
++ (g_ipu_hw_rev >= IPU_V3DEX));
++}
++
++/*
++ * We usually use IDMAC 23 as full plane and IDMAC 27 as partial
++ * plane.
++ * IDMAC 23/24/28/41 can drive a display respectively - primary
++ * IDMAC 27 depends on IDMAC 23 - nonprimary
++ */
++static inline int _ipu_is_primary_disp_chan(uint32_t dma_chan)
++{
++ return ((dma_chan == 23) || (dma_chan == 24) ||
++ (dma_chan == 28) || (dma_chan == 41));
++}
++
++static inline int _ipu_is_sync_irq(uint32_t irq)
++{
++ /* sync interrupt register number */
++ int reg_num = irq / 32 + 1;
++
++ return ((reg_num == 1) || (reg_num == 2) || (reg_num == 3) ||
++ (reg_num == 4) || (reg_num == 7) || (reg_num == 8) ||
++ (reg_num == 11) || (reg_num == 12) || (reg_num == 13) ||
++ (reg_num == 14) || (reg_num == 15));
++}
++
++#define idma_is_valid(ch) (ch != NO_DMA)
++#define idma_mask(ch) (idma_is_valid(ch) ? (1UL << (ch & 0x1F)) : 0)
++#define idma_is_set(ipu, reg, dma) (ipu_idmac_read(ipu, reg(dma)) & idma_mask(dma))
++#define tri_cur_buf_mask(ch) (idma_mask(ch*2) * 3)
++#define tri_cur_buf_shift(ch) (ffs(idma_mask(ch*2)) - 1)
++
++static int ipu_clk_setup_enable(struct ipu_soc *ipu,
++ struct ipu_pltfm_data *pdata)
++{
++ char pixel_clk_0[] = "ipu1_pclk_0";
++ char pixel_clk_1[] = "ipu1_pclk_1";
++ char pixel_clk_0_sel[] = "ipu1_pclk0_sel";
++ char pixel_clk_1_sel[] = "ipu1_pclk1_sel";
++ char pixel_clk_0_div[] = "ipu1_pclk0_div";
++ char pixel_clk_1_div[] = "ipu1_pclk1_div";
++ char *ipu_pixel_clk_sel[] = { "ipu1", "ipu1_di0", "ipu1_di1", };
++ char *pclk_sel;
++ struct clk *clk;
++ int ret;
++ int i;
++
++ pixel_clk_0[3] += pdata->id;
++ pixel_clk_1[3] += pdata->id;
++ pixel_clk_0_sel[3] += pdata->id;
++ pixel_clk_1_sel[3] += pdata->id;
++ pixel_clk_0_div[3] += pdata->id;
++ pixel_clk_1_div[3] += pdata->id;
++ for (i = 0; i < ARRAY_SIZE(ipu_pixel_clk_sel); i++) {
++ pclk_sel = ipu_pixel_clk_sel[i];
++ pclk_sel[3] += pdata->id;
++ }
++ dev_dbg(ipu->dev, "ipu_clk = %lu\n", clk_get_rate(ipu->ipu_clk));
++
++ clk = clk_register_mux_pix_clk(ipu->dev, pixel_clk_0_sel,
++ (const char **)ipu_pixel_clk_sel,
++ ARRAY_SIZE(ipu_pixel_clk_sel),
++ 0, pdata->id, 0, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk_register mux di0 failed");
++ return PTR_ERR(clk);
++ }
++ ipu->pixel_clk_sel[0] = clk;
++ clk = clk_register_mux_pix_clk(ipu->dev, pixel_clk_1_sel,
++ (const char **)ipu_pixel_clk_sel,
++ ARRAY_SIZE(ipu_pixel_clk_sel),
++ 0, pdata->id, 1, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk_register mux di1 failed");
++ return PTR_ERR(clk);
++ }
++ ipu->pixel_clk_sel[1] = clk;
++
++ clk = clk_register_div_pix_clk(ipu->dev, pixel_clk_0_div,
++ pixel_clk_0_sel, 0, pdata->id, 0, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk register di0 div failed");
++ return PTR_ERR(clk);
++ }
++ clk = clk_register_div_pix_clk(ipu->dev, pixel_clk_1_div,
++ pixel_clk_1_sel, CLK_SET_RATE_PARENT, pdata->id, 1, 0);
++ if (IS_ERR(clk)) {
++ dev_err(ipu->dev, "clk register di1 div failed");
++ return PTR_ERR(clk);
++ }
++
++ ipu->pixel_clk[0] = clk_register_gate_pix_clk(ipu->dev, pixel_clk_0,
++ pixel_clk_0_div, CLK_SET_RATE_PARENT,
++ pdata->id, 0, 0);
++ if (IS_ERR(ipu->pixel_clk[0])) {
++ dev_err(ipu->dev, "clk register di0 gate failed");
++ return PTR_ERR(ipu->pixel_clk[0]);
++ }
++ ipu->pixel_clk[1] = clk_register_gate_pix_clk(ipu->dev, pixel_clk_1,
++ pixel_clk_1_div, CLK_SET_RATE_PARENT,
++ pdata->id, 1, 0);
++ if (IS_ERR(ipu->pixel_clk[1])) {
++ dev_err(ipu->dev, "clk register di1 gate failed");
++ return PTR_ERR(ipu->pixel_clk[1]);
++ }
++
++ ret = clk_set_parent(ipu->pixel_clk_sel[0], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "clk set parent failed");
++ return ret;
++ }
++
++ ret = clk_set_parent(ipu->pixel_clk_sel[1], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "clk set parent failed");
++ return ret;
++ }
++
++ ipu->di_clk[0] = devm_clk_get(ipu->dev, "di0");
++ if (IS_ERR(ipu->di_clk[0])) {
++ dev_err(ipu->dev, "clk_get di0 failed");
++ return PTR_ERR(ipu->di_clk[0]);
++ }
++ ipu->di_clk[1] = devm_clk_get(ipu->dev, "di1");
++ if (IS_ERR(ipu->di_clk[1])) {
++ dev_err(ipu->dev, "clk_get di1 failed");
++ return PTR_ERR(ipu->di_clk[1]);
++ }
++
++ ipu->di_clk_sel[0] = devm_clk_get(ipu->dev, "di0_sel");
++ if (IS_ERR(ipu->di_clk_sel[0])) {
++ dev_err(ipu->dev, "clk_get di0_sel failed");
++ return PTR_ERR(ipu->di_clk_sel[0]);
++ }
++ ipu->di_clk_sel[1] = devm_clk_get(ipu->dev, "di1_sel");
++ if (IS_ERR(ipu->di_clk_sel[1])) {
++ dev_err(ipu->dev, "clk_get di1_sel failed");
++ return PTR_ERR(ipu->di_clk_sel[1]);
++ }
++
++ return 0;
++}
++
++static int ipu_mem_reset(struct ipu_soc *ipu)
++{
++ int timeout = 1000;
++
++ ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
++
++ while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
++ if (!timeout--)
++ return -ETIME;
++ msleep(1);
++ }
++
++ return 0;
++}
++
++struct ipu_soc *ipu_get_soc(int id)
++{
++ if (id >= MXC_IPU_MAX_NUM)
++ return ERR_PTR(-ENODEV);
++ else if (!ipu_array[id].online)
++ return ERR_PTR(-ENODEV);
++ else
++ return &(ipu_array[id]);
++}
++EXPORT_SYMBOL_GPL(ipu_get_soc);
++
++void _ipu_get(struct ipu_soc *ipu)
++{
++ int ret;
++
++ ret = clk_enable(ipu->ipu_clk);
++ if (ret < 0)
++ BUG();
++}
++
++void _ipu_put(struct ipu_soc *ipu)
++{
++ clk_disable(ipu->ipu_clk);
++}
++
++void ipu_disable_hsp_clk(struct ipu_soc *ipu)
++{
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_disable_hsp_clk);
++
++static struct platform_device_id imx_ipu_type[] = {
++ {
++ .name = "ipu-imx6q",
++ .driver_data = IPU_V3H,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_ipu_type);
++
++static const struct of_device_id imx_ipuv3_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ipu", .data = &imx_ipu_type[IMX6Q_IPU], },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_ipuv3_dt_ids);
++
++/*!
++ * This function is called by the driver framework to initialize the IPU
++ * hardware.
++ *
++ * @param dev The device structure for the IPU passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int ipu_probe(struct platform_device *pdev)
++{
++ struct ipu_soc *ipu;
++ struct resource *res;
++ unsigned long ipu_base;
++ const struct of_device_id *of_id =
++ of_match_device(imx_ipuv3_dt_ids, &pdev->dev);
++ struct ipu_pltfm_data *pltfm_data;
++ int ret = 0;
++ u32 bypass_reset;
++
++ dev_dbg(&pdev->dev, "<%s>\n", __func__);
++
++ pltfm_data = devm_kzalloc(&pdev->dev, sizeof(struct ipu_pltfm_data),
++ GFP_KERNEL);
++ if (!pltfm_data)
++ return -ENOMEM;
++
++ ret = of_property_read_u32(pdev->dev.of_node,
++ "bypass_reset", &bypass_reset);
++ if (ret < 0) {
++ dev_dbg(&pdev->dev, "can not get bypass_reset\n");
++ return ret;
++ }
++ pltfm_data->bypass_reset = (bool)bypass_reset;
++
++ pltfm_data->id = of_alias_get_id(pdev->dev.of_node, "ipu");
++ if (pltfm_data->id < 0) {
++ dev_dbg(&pdev->dev, "can not get alias id\n");
++ return pltfm_data->id;
++ }
++
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ pltfm_data->devtype = pdev->id_entry->driver_data;
++ g_ipu_hw_rev = pltfm_data->devtype;
++
++ ipu = &ipu_array[pltfm_data->id];
++ memset(ipu, 0, sizeof(struct ipu_soc));
++ ipu->dev = &pdev->dev;
++ ipu->pdata = pltfm_data;
++ dev_dbg(ipu->dev, "IPU rev:%d\n", g_ipu_hw_rev);
++ spin_lock_init(&ipu->int_reg_spin_lock);
++ spin_lock_init(&ipu->rdy_reg_spin_lock);
++ mutex_init(&ipu->mutex_lock);
++
++ ipu->irq_sync = platform_get_irq(pdev, 0);
++ ipu->irq_err = platform_get_irq(pdev, 1);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++ if (!res || ipu->irq_sync < 0 || ipu->irq_err < 0) {
++ dev_err(&pdev->dev, "can't get device resources\n");
++ return -ENODEV;
++ }
++
++ if (!devm_request_mem_region(&pdev->dev, res->start,
++ resource_size(res), pdev->name))
++ return -EBUSY;
++
++ ret = devm_request_irq(&pdev->dev, ipu->irq_sync,
++ ipu_sync_irq_handler, 0, pdev->name, ipu);
++ if (ret) {
++ dev_err(ipu->dev, "request SYNC interrupt failed\n");
++ return ret;
++ }
++ ret = devm_request_irq(&pdev->dev, ipu->irq_err,
++ ipu_err_irq_handler, 0, pdev->name, ipu);
++ if (ret) {
++ dev_err(ipu->dev, "request ERR interrupt failed\n");
++ return ret;
++ }
++
++ ipu_base = res->start;
++ /* base fixup */
++ if (g_ipu_hw_rev == IPU_V3H) /* IPUv3H */
++ ipu_base += IPUV3H_REG_BASE;
++ else if (g_ipu_hw_rev == IPU_V3M) /* IPUv3M */
++ ipu_base += IPUV3M_REG_BASE;
++ else /* IPUv3D, v3E, v3EX */
++ ipu_base += IPUV3DEX_REG_BASE;
++
++ ipu->cm_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CM_REG_BASE, PAGE_SIZE);
++ ipu->ic_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_IC_REG_BASE, PAGE_SIZE);
++ ipu->idmac_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_IDMAC_REG_BASE, PAGE_SIZE);
++ /* DP Registers are accessed thru the SRM */
++ ipu->dp_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_SRM_REG_BASE, PAGE_SIZE);
++ ipu->dc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DC_REG_BASE, PAGE_SIZE);
++ ipu->dmfc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DMFC_REG_BASE, PAGE_SIZE);
++ ipu->di_reg[0] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DI0_REG_BASE, PAGE_SIZE);
++ ipu->di_reg[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DI1_REG_BASE, PAGE_SIZE);
++ ipu->smfc_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_SMFC_REG_BASE, PAGE_SIZE);
++ ipu->csi_reg[0] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CSI0_REG_BASE, PAGE_SIZE);
++ ipu->csi_reg[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CSI1_REG_BASE, PAGE_SIZE);
++ ipu->cpmem_base = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_CPMEM_REG_BASE, SZ_128K);
++ ipu->tpmem_base = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_TPM_REG_BASE, SZ_64K);
++ ipu->dc_tmpl_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DC_TMPL_REG_BASE, SZ_128K);
++ ipu->vdi_reg = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_VDI_REG_BASE, PAGE_SIZE);
++ ipu->disp_base[1] = devm_ioremap(&pdev->dev,
++ ipu_base + IPU_DISP1_BASE, SZ_4K);
++ if (!ipu->cm_reg || !ipu->ic_reg || !ipu->idmac_reg ||
++ !ipu->dp_reg || !ipu->dc_reg || !ipu->dmfc_reg ||
++ !ipu->di_reg[0] || !ipu->di_reg[1] || !ipu->smfc_reg ||
++ !ipu->csi_reg[0] || !ipu->csi_reg[1] || !ipu->cpmem_base ||
++ !ipu->tpmem_base || !ipu->dc_tmpl_reg || !ipu->disp_base[1]
++ || !ipu->vdi_reg)
++ return -ENOMEM;
++
++ dev_dbg(ipu->dev, "IPU CM Regs = %p\n", ipu->cm_reg);
++ dev_dbg(ipu->dev, "IPU IC Regs = %p\n", ipu->ic_reg);
++ dev_dbg(ipu->dev, "IPU IDMAC Regs = %p\n", ipu->idmac_reg);
++ dev_dbg(ipu->dev, "IPU DP Regs = %p\n", ipu->dp_reg);
++ dev_dbg(ipu->dev, "IPU DC Regs = %p\n", ipu->dc_reg);
++ dev_dbg(ipu->dev, "IPU DMFC Regs = %p\n", ipu->dmfc_reg);
++ dev_dbg(ipu->dev, "IPU DI0 Regs = %p\n", ipu->di_reg[0]);
++ dev_dbg(ipu->dev, "IPU DI1 Regs = %p\n", ipu->di_reg[1]);
++ dev_dbg(ipu->dev, "IPU SMFC Regs = %p\n", ipu->smfc_reg);
++ dev_dbg(ipu->dev, "IPU CSI0 Regs = %p\n", ipu->csi_reg[0]);
++ dev_dbg(ipu->dev, "IPU CSI1 Regs = %p\n", ipu->csi_reg[1]);
++ dev_dbg(ipu->dev, "IPU CPMem = %p\n", ipu->cpmem_base);
++ dev_dbg(ipu->dev, "IPU TPMem = %p\n", ipu->tpmem_base);
++ dev_dbg(ipu->dev, "IPU DC Template Mem = %p\n", ipu->dc_tmpl_reg);
++ dev_dbg(ipu->dev, "IPU Display Region 1 Mem = %p\n", ipu->disp_base[1]);
++ dev_dbg(ipu->dev, "IPU VDI Regs = %p\n", ipu->vdi_reg);
++
++ ipu->ipu_clk = devm_clk_get(ipu->dev, "bus");
++ if (IS_ERR(ipu->ipu_clk)) {
++ dev_err(ipu->dev, "clk_get ipu failed");
++ return PTR_ERR(ipu->ipu_clk);
++ }
++
++ /* ipu_clk is always prepared */
++ ret = clk_prepare_enable(ipu->ipu_clk);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ipu clk enable failed\n");
++ return ret;
++ }
++
++ ipu->online = true;
++
++ platform_set_drvdata(pdev, ipu);
++
++ if (!pltfm_data->bypass_reset) {
++ ret = device_reset(&pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to reset: %d\n", ret);
++ return ret;
++ }
++
++ ipu_mem_reset(ipu);
++
++ ipu_disp_init(ipu);
++
++ /* Set MCU_T to divide MCU access window into 2 */
++ ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
++ IPU_DISP_GEN);
++ }
++
++ /* setup ipu clk tree after ipu reset */
++ ret = ipu_clk_setup_enable(ipu, pltfm_data);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ipu clk setup failed\n");
++ ipu->online = false;
++ return ret;
++ }
++
++ /* Set sync refresh channels and CSI->mem channel as high priority */
++ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
++
++ /* Enable error interrupts by default */
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
++
++ if (!pltfm_data->bypass_reset)
++ clk_disable(ipu->ipu_clk);
++
++ register_ipu_device(ipu, ipu->pdata->id);
++
++ pm_runtime_enable(&pdev->dev);
++
++ return ret;
++}
++
++int ipu_remove(struct platform_device *pdev)
++{
++ struct ipu_soc *ipu = platform_get_drvdata(pdev);
++
++ unregister_ipu_device(ipu, ipu->pdata->id);
++
++ clk_put(ipu->ipu_clk);
++
++ return 0;
++}
++
++void ipu_dump_registers(struct ipu_soc *ipu)
++{
++ dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", ipu_cm_read(ipu, IPU_CONF));
++ dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", ipu_idmac_read(ipu, IDMAC_CONF));
++ dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
++ dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
++ dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
++ dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
++ ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
++ dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
++ dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
++ if (g_ipu_hw_rev >= IPU_V3DEX) {
++ dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL0 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(0)));
++ dev_dbg(ipu->dev, "IPU_CHA_TRB_MODE_SEL1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(32)));
++ }
++ dev_dbg(ipu->dev, "DMFC_WR_CHAN = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_WR_CHAN));
++ dev_dbg(ipu->dev, "DMFC_WR_CHAN_DEF = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_WR_CHAN_DEF));
++ dev_dbg(ipu->dev, "DMFC_DP_CHAN = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_DP_CHAN));
++ dev_dbg(ipu->dev, "DMFC_DP_CHAN_DEF = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_DP_CHAN_DEF));
++ dev_dbg(ipu->dev, "DMFC_IC_CTRL = \t0x%08X\n",
++ ipu_dmfc_read(ipu, DMFC_IC_CTRL));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
++ dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
++ dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
++ ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
++ dev_dbg(ipu->dev, "IPU_VDIC_VDI_FSIZE = \t0x%08X\n",
++ ipu_vdi_read(ipu, VDI_FSIZE));
++ dev_dbg(ipu->dev, "IPU_VDIC_VDI_C = \t0x%08X\n",
++ ipu_vdi_read(ipu, VDI_C));
++ dev_dbg(ipu->dev, "IPU_IC_CONF = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_CONF));
++}
++
++/*!
++ * This function is called to initialize a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID to init.
++ *
++ * @param params Input parameter containing union of channel
++ * initialization parameters.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
++{
++ int ret = 0;
++ bool bad_pixfmt;
++ uint32_t ipu_conf, reg, in_g_pixel_fmt, sec_dma;
++
++ dev_dbg(ipu->dev, "init channel = %d\n", IPU_CHAN_ID(channel));
++
++ ret = pm_runtime_get_sync(ipu->dev);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ch = %d, pm_runtime_get failed:%d!\n",
++ IPU_CHAN_ID(channel), ret);
++ dump_stack();
++ return ret;
++ }
++ /*
++ * Here, ret could be 1 if the device's runtime PM status was
++ * already 'active', so clear it to be 0.
++ */
++ ret = 0;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* Re-enable error interrupts every time a channel is initialized */
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(5));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(6));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(9));
++ ipu_cm_write(ipu, 0xFFFFFFFF, IPU_INT_CTRL(10));
++
++ if (ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) {
++ dev_warn(ipu->dev, "Warning: channel already initialized %d\n",
++ IPU_CHAN_ID(channel));
++ }
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ if (params->csi_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ if (params->csi_mem.interlaced)
++ ipu->chan_is_interlaced[channel_2_dma(channel,
++ IPU_OUTPUT_BUFFER)] = true;
++ else
++ ipu->chan_is_interlaced[channel_2_dma(channel,
++ IPU_OUTPUT_BUFFER)] = false;
++
++ ipu->smfc_use_count++;
++ ipu->csi_channel[params->csi_mem.csi] = channel;
++
++ /*SMFC setting*/
++ if (params->csi_mem.mipi.en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_mem.csi));
++ _ipu_smfc_init(ipu, channel, params->csi_mem.mipi.vc,
++ params->csi_mem.csi);
++ _ipu_csi_set_mipi_di(ipu, params->csi_mem.mipi.vc,
++ params->csi_mem.mipi.id, params->csi_mem.csi);
++ } else {
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_mem.csi));
++ _ipu_smfc_init(ipu, channel, 0, params->csi_mem.csi);
++ }
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_mem.csi);
++ break;
++ case CSI_PRP_ENC_MEM:
++ if (params->csi_prp_enc_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++ if ((ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = CSI_PRP_ENC_MEM;
++
++ ipu->ic_use_count++;
++ ipu->csi_channel[params->csi_prp_enc_mem.csi] = channel;
++
++ if (params->csi_prp_enc_mem.mipi.en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_enc_mem.csi));
++ _ipu_csi_set_mipi_di(ipu,
++ params->csi_prp_enc_mem.mipi.vc,
++ params->csi_prp_enc_mem.mipi.id,
++ params->csi_prp_enc_mem.csi);
++ } else
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_enc_mem.csi));
++
++ /*CSI0/1 feed into IC*/
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ if (params->csi_prp_enc_mem.csi)
++ ipu_conf |= IPU_CONF_CSI_SEL;
++ else
++ ipu_conf &= ~IPU_CONF_CSI_SEL;
++
++ /*PRP skip buffer in memory, only valid when RWS_EN is true*/
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_prp_enc_mem.csi);
++ _ipu_ic_init_prpenc(ipu, params, true);
++ break;
++ case CSI_PRP_VF_MEM:
++ if (params->csi_prp_vf_mem.csi > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++ if ((ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = CSI_PRP_VF_MEM;
++
++ ipu->ic_use_count++;
++ ipu->csi_channel[params->csi_prp_vf_mem.csi] = channel;
++
++ if (params->csi_prp_vf_mem.mipi.en) {
++ ipu_conf |= (1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_vf_mem.csi));
++ _ipu_csi_set_mipi_di(ipu,
++ params->csi_prp_vf_mem.mipi.vc,
++ params->csi_prp_vf_mem.mipi.id,
++ params->csi_prp_vf_mem.csi);
++ } else
++ ipu_conf &= ~(1 << (IPU_CONF_CSI0_DATA_SOURCE_OFFSET +
++ params->csi_prp_vf_mem.csi));
++
++ /*CSI0/1 feed into IC*/
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ if (params->csi_prp_vf_mem.csi)
++ ipu_conf |= IPU_CONF_CSI_SEL;
++ else
++ ipu_conf &= ~IPU_CONF_CSI_SEL;
++
++ /*PRP skip buffer in memory, only valid when RWS_EN is true*/
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ /*CSI data (include compander) dest*/
++ _ipu_csi_init(ipu, channel, params->csi_prp_vf_mem.csi);
++ _ipu_ic_init_prpvf(ipu, params, true);
++ break;
++ case MEM_PRP_VF_MEM:
++ if (params->mem_prp_vf_mem.graphics_combine_en) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ in_g_pixel_fmt = params->mem_prp_vf_mem.in_g_pixel_fmt;
++ bad_pixfmt =
++ _ipu_ch_param_bad_alpha_pos(in_g_pixel_fmt);
++
++ if (params->mem_prp_vf_mem.alpha_chan_en) {
++ if (bad_pixfmt) {
++ dev_err(ipu->dev, "bad pixel format "
++ "for graphics plane from "
++ "ch%d\n", sec_dma);
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg | FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++
++ _ipu_ic_init_prpvf(ipu, params, false);
++ ipu->ic_use_count++;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_MEM) ||
++ (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = MEM_VDI_PRP_VF_MEM;
++ ipu->ic_use_count++;
++ ipu->vdi_use_count++;
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ reg &= ~FS_VDI_SRC_SEL_MASK;
++ ipu_cm_write(ipu, reg , IPU_FS_PROC_FLOW1);
++
++ if (params->mem_prp_vf_mem.graphics_combine_en)
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ _ipu_ic_init_prpvf(ipu, params, false);
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ case MEM_VDI_PRP_VF_MEM_N:
++ case MEM_VDI_MEM_P:
++ case MEM_VDI_MEM_N:
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_VDI_MEM:
++ if ((ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM) ||
++ (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)) {
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->using_ic_dirct_ch = MEM_VDI_MEM;
++ ipu->ic_use_count++;
++ ipu->vdi_use_count++;
++ _ipu_vdi_init(ipu, channel, params);
++ break;
++ case MEM_ROT_VF_MEM:
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ _ipu_ic_init_rotate_vf(ipu, params);
++ break;
++ case MEM_PRP_ENC_MEM:
++ ipu->ic_use_count++;
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg | FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++ _ipu_ic_init_prpenc(ipu, params, false);
++ break;
++ case MEM_ROT_ENC_MEM:
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ _ipu_ic_init_rotate_enc(ipu, params);
++ break;
++ case MEM_PP_MEM:
++ if (params->mem_pp_mem.graphics_combine_en) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ in_g_pixel_fmt = params->mem_pp_mem.in_g_pixel_fmt;
++ bad_pixfmt =
++ _ipu_ch_param_bad_alpha_pos(in_g_pixel_fmt);
++
++ if (params->mem_pp_mem.alpha_chan_en) {
++ if (bad_pixfmt) {
++ dev_err(ipu->dev, "bad pixel format "
++ "for graphics plane from "
++ "ch%d\n", sec_dma);
++ ret = -EINVAL;
++ goto err;
++ }
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = true;
++ }
++
++ _ipu_ic_init_pp(ipu, params);
++ ipu->ic_use_count++;
++ break;
++ case MEM_ROT_PP_MEM:
++ _ipu_ic_init_rotate_pp(ipu, params);
++ ipu->ic_use_count++;
++ ipu->rot_use_count++;
++ break;
++ case MEM_DC_SYNC:
++ if (params->mem_dc_sync.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[1] = params->mem_dc_sync.di;
++ _ipu_dc_init(ipu, 1, params->mem_dc_sync.di,
++ params->mem_dc_sync.interlaced,
++ params->mem_dc_sync.out_pixel_fmt);
++ ipu->di_use_count[params->mem_dc_sync.di]++;
++ ipu->dc_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case MEM_BG_SYNC:
++ if (params->mem_dp_bg_sync.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ if (params->mem_dp_bg_sync.alpha_chan_en)
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++
++ ipu->dc_di_assignment[5] = params->mem_dp_bg_sync.di;
++ _ipu_dp_init(ipu, channel, params->mem_dp_bg_sync.in_pixel_fmt,
++ params->mem_dp_bg_sync.out_pixel_fmt);
++ _ipu_dc_init(ipu, 5, params->mem_dp_bg_sync.di,
++ params->mem_dp_bg_sync.interlaced,
++ params->mem_dp_bg_sync.out_pixel_fmt);
++ ipu->di_use_count[params->mem_dp_bg_sync.di]++;
++ ipu->dc_use_count++;
++ ipu->dp_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case MEM_FG_SYNC:
++ _ipu_dp_init(ipu, channel, params->mem_dp_fg_sync.in_pixel_fmt,
++ params->mem_dp_fg_sync.out_pixel_fmt);
++
++ if (params->mem_dp_fg_sync.alpha_chan_en)
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = true;
++
++ ipu->dc_use_count++;
++ ipu->dp_use_count++;
++ ipu->dmfc_use_count++;
++ break;
++ case DIRECT_ASYNC0:
++ if (params->direct_async.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[8] = params->direct_async.di;
++ _ipu_dc_init(ipu, 8, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
++ ipu->di_use_count[params->direct_async.di]++;
++ ipu->dc_use_count++;
++ break;
++ case DIRECT_ASYNC1:
++ if (params->direct_async.di > 1) {
++ ret = -EINVAL;
++ goto err;
++ }
++
++ ipu->dc_di_assignment[9] = params->direct_async.di;
++ _ipu_dc_init(ipu, 9, params->direct_async.di, false, IPU_PIX_FMT_GENERIC);
++ ipu->di_use_count[params->direct_async.di]++;
++ ipu->dc_use_count++;
++ break;
++ default:
++ dev_err(ipu->dev, "Missing channel initialization\n");
++ break;
++ }
++
++ ipu->channel_init_mask |= 1L << IPU_CHAN_ID(channel);
++
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_init_channel);
++
++int32_t ipu_channel_request(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_channel_params_t *params, struct ipu_chan **p_ipu_chan)
++{
++ struct ipu_chan *ipu_chan;
++ unsigned channel_id = IPU_CHAN_ID(channel);
++ int32_t ret;
++
++ dev_dbg(ipu->dev, "init channel = %d\n", channel_id);
++ *p_ipu_chan = NULL;
++ if (channel_id >= ARRAY_SIZE(ipu->chan)) {
++ dev_err(ipu->dev, "%s: ch = %d is too big!\n", __func__,
++ channel_id);
++ return -ENODEV;
++ }
++ ipu_chan = &ipu->chan[channel_id];
++ if (ipu_chan->p_ipu_chan && (ipu_chan->p_ipu_chan != p_ipu_chan)) {
++ dev_err(ipu->dev, "%s: ch = %d is busy!\n", __func__,
++ channel_id);
++ return -EBUSY;
++ }
++ ipu_chan->p_ipu_chan = p_ipu_chan;
++ ipu_chan->ipu = ipu;
++ ipu_chan->channel = channel;
++ ret = ipu_init_channel(ipu, channel, params);
++ if (ret)
++ ipu_chan->p_ipu_chan = NULL;
++ else
++ *p_ipu_chan = ipu_chan;
++ return ret;
++}
++EXPORT_SYMBOL(ipu_channel_request);
++
++/*!
++ * This function is called to uninitialize a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID to uninit.
++ */
++void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t in_dma, out_dma = 0;
++ uint32_t ipu_conf;
++ uint32_t dc_chan = 0;
++ int ret;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if ((ipu->channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
++ dev_dbg(ipu->dev, "Channel already uninitialized %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return;
++ }
++
++ /* Make sure channel is disabled */
++ /* Get input and output dma channels */
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++
++ if (idma_is_set(ipu, IDMAC_CHA_EN, in_dma) ||
++ idma_is_set(ipu, IDMAC_CHA_EN, out_dma)) {
++ dev_err(ipu->dev,
++ "Channel %d is not disabled, disable first\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return;
++ }
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++
++ /* Reset the double buffer */
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(in_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_DB_MODE_SEL(in_dma));
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(out_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_DB_MODE_SEL(out_dma));
++
++ /* Reset the triple buffer */
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(in_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(in_dma), IPU_CHA_TRB_MODE_SEL(in_dma));
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(out_dma));
++ ipu_cm_write(ipu, reg & ~idma_mask(out_dma), IPU_CHA_TRB_MODE_SEL(out_dma));
++
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_dp_graphic_chan(in_dma)) {
++ ipu->sec_chan_en[IPU_CHAN_ID(channel)] = false;
++ ipu->thrd_chan_en[IPU_CHAN_ID(channel)] = false;
++ }
++
++ switch (channel) {
++ case CSI_MEM0:
++ case CSI_MEM1:
++ case CSI_MEM2:
++ case CSI_MEM3:
++ ipu->smfc_use_count--;
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case CSI_PRP_ENC_MEM:
++ ipu->ic_use_count--;
++ if (ipu->using_ic_dirct_ch == CSI_PRP_ENC_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpenc(ipu);
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case CSI_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ if (ipu->using_ic_dirct_ch == CSI_PRP_VF_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpvf(ipu);
++ if (ipu->csi_channel[0] == channel) {
++ ipu->csi_channel[0] = CHAN_NONE;
++ } else if (ipu->csi_channel[1] == channel) {
++ ipu->csi_channel[1] = CHAN_NONE;
++ }
++ break;
++ case MEM_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_prpvf(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ipu->ic_use_count--;
++ ipu->vdi_use_count--;
++ if (ipu->using_ic_dirct_ch == MEM_VDI_PRP_VF_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_ic_uninit_prpvf(ipu);
++ _ipu_vdi_uninit(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_VF_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_VDI_MEM:
++ ipu->ic_use_count--;
++ ipu->vdi_use_count--;
++ if (ipu->using_ic_dirct_ch == MEM_VDI_MEM)
++ ipu->using_ic_dirct_ch = 0;
++ _ipu_vdi_uninit(ipu);
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ case MEM_VDI_PRP_VF_MEM_N:
++ case MEM_VDI_MEM_P:
++ case MEM_VDI_MEM_N:
++ break;
++ case MEM_ROT_VF_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_vf(ipu);
++ break;
++ case MEM_PRP_ENC_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_prpenc(ipu);
++ reg = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW1);
++ break;
++ case MEM_ROT_ENC_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_enc(ipu);
++ break;
++ case MEM_PP_MEM:
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_pp(ipu);
++ break;
++ case MEM_ROT_PP_MEM:
++ ipu->rot_use_count--;
++ ipu->ic_use_count--;
++ _ipu_ic_uninit_rotate_pp(ipu);
++ break;
++ case MEM_DC_SYNC:
++ dc_chan = 1;
++ _ipu_dc_uninit(ipu, 1);
++ ipu->di_use_count[ipu->dc_di_assignment[1]]--;
++ ipu->dc_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case MEM_BG_SYNC:
++ dc_chan = 5;
++ _ipu_dp_uninit(ipu, channel);
++ _ipu_dc_uninit(ipu, 5);
++ ipu->di_use_count[ipu->dc_di_assignment[5]]--;
++ ipu->dc_use_count--;
++ ipu->dp_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case MEM_FG_SYNC:
++ _ipu_dp_uninit(ipu, channel);
++ ipu->dc_use_count--;
++ ipu->dp_use_count--;
++ ipu->dmfc_use_count--;
++ break;
++ case DIRECT_ASYNC0:
++ dc_chan = 8;
++ _ipu_dc_uninit(ipu, 8);
++ ipu->di_use_count[ipu->dc_di_assignment[8]]--;
++ ipu->dc_use_count--;
++ break;
++ case DIRECT_ASYNC1:
++ dc_chan = 9;
++ _ipu_dc_uninit(ipu, 9);
++ ipu->di_use_count[ipu->dc_di_assignment[9]]--;
++ ipu->dc_use_count--;
++ break;
++ default:
++ break;
++ }
++
++ if (ipu->ic_use_count == 0)
++ ipu_conf &= ~IPU_CONF_IC_EN;
++ if (ipu->vdi_use_count == 0) {
++ ipu_conf &= ~IPU_CONF_ISP_EN;
++ ipu_conf &= ~IPU_CONF_VDI_EN;
++ ipu_conf &= ~IPU_CONF_IC_INPUT;
++ }
++ if (ipu->rot_use_count == 0)
++ ipu_conf &= ~IPU_CONF_ROT_EN;
++ if (ipu->dc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DC_EN;
++ if (ipu->dp_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DP_EN;
++ if (ipu->dmfc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_DMFC_EN;
++ if (ipu->di_use_count[0] == 0) {
++ ipu_conf &= ~IPU_CONF_DI0_EN;
++ }
++ if (ipu->di_use_count[1] == 0) {
++ ipu_conf &= ~IPU_CONF_DI1_EN;
++ }
++ if (ipu->smfc_use_count == 0)
++ ipu_conf &= ~IPU_CONF_SMFC_EN;
++
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++ ipu->channel_init_mask &= ~(1L << IPU_CHAN_ID(channel));
++
++ /*
++ * Disable pixel clk and its parent clock(if the parent clock
++ * usecount is 1) after clearing DC/DP/DI bits in IPU_CONF
++ * register to prevent LVDS display channel starvation.
++ */
++ if (_ipu_is_primary_disp_chan(in_dma))
++ clk_disable_unprepare(ipu->pixel_clk[ipu->dc_di_assignment[dc_chan]]);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ ret = pm_runtime_put_sync_suspend(ipu->dev);
++ if (ret < 0) {
++ dev_err(ipu->dev, "ch = %d, pm_runtime_put failed:%d!\n",
++ IPU_CHAN_ID(channel), ret);
++ dump_stack();
++ }
++
++ WARN_ON(ipu->ic_use_count < 0);
++ WARN_ON(ipu->vdi_use_count < 0);
++ WARN_ON(ipu->rot_use_count < 0);
++ WARN_ON(ipu->dc_use_count < 0);
++ WARN_ON(ipu->dp_use_count < 0);
++ WARN_ON(ipu->dmfc_use_count < 0);
++ WARN_ON(ipu->smfc_use_count < 0);
++}
++EXPORT_SYMBOL(ipu_uninit_channel);
++
++void ipu_channel_free(struct ipu_chan **p_ipu_chan)
++{
++ struct ipu_chan *ipu_chan = *p_ipu_chan;
++
++ *p_ipu_chan = NULL;
++ if (ipu_chan) {
++ ipu_chan->p_ipu_chan = NULL;
++ ipu_uninit_channel(ipu_chan->ipu, ipu_chan->channel);
++ }
++}
++EXPORT_SYMBOL(ipu_channel_free);
++
++/*!
++ * This function is called to initialize buffer(s) for logical IPU channel.
++ *
++ * @param ipu ipu handler
++ *
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width Input parameter for width of buffer in pixels.
++ *
++ * @param height Input parameter for height of buffer in pixels.
++ *
++ * @param stride Input parameter for stride length of buffer
++ * in pixels.
++ *
++ * @param rot_mode Input parameter for rotation setting of buffer.
++ * A rotation setting other than
++ * IPU_ROTATE_VERT_FLIP
++ * should only be used for input buffers of
++ * rotation channels.
++ *
++ * @param phyaddr_0 Input parameter buffer 0 physical address.
++ *
++ * @param phyaddr_1 Input parameter buffer 1 physical address.
++ * Setting this to a value other than NULL enables
++ * double buffering mode.
++ *
++ * @param phyaddr_2 Input parameter buffer 2 physical address.
++ * Setting this to a value other than NULL enables
++ * triple buffering mode, phyaddr_1 should not be
++ * NULL then.
++ *
++ * @param u private u offset for additional cropping,
++ * zero if not used.
++ *
++ * @param v private v offset for additional cropping,
++ * zero if not used.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ ipu_rotate_mode_t rot_mode,
++ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
++ dma_addr_t phyaddr_2,
++ uint32_t u, uint32_t v)
++{
++ uint32_t reg;
++ uint32_t dma_chan;
++ uint32_t burst_size;
++
++ dma_chan = channel_2_dma(channel, type);
++ if (!idma_is_valid(dma_chan))
++ return -EINVAL;
++
++ if (stride < width * bytes_per_pixel(pixel_fmt))
++ stride = width * bytes_per_pixel(pixel_fmt);
++
++ if (stride % 4) {
++ dev_err(ipu->dev,
++ "Stride not 32-bit aligned, stride = %d\n", stride);
++ return -EINVAL;
++ }
++ /* IC & IRT channels' width must be multiple of 8 pixels */
++ if ((_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan))
++ && (width % 8)) {
++ dev_err(ipu->dev, "Width must be 8 pixel multiple\n");
++ return -EINVAL;
++ }
++
++ if (_ipu_is_vdi_out_chan(dma_chan) &&
++ ((width < 16) || (height < 16) || (width % 2) || (height % 4))) {
++ dev_err(ipu->dev, "vdi width/height limited err\n");
++ return -EINVAL;
++ }
++
++ /* IPUv3EX and IPUv3M support triple buffer */
++ if ((!_ipu_is_trb_chan(dma_chan)) && phyaddr_2) {
++ dev_err(ipu->dev, "Chan%d doesn't support triple buffer "
++ "mode\n", dma_chan);
++ return -EINVAL;
++ }
++ if (!phyaddr_1 && phyaddr_2) {
++ dev_err(ipu->dev, "Chan%d's buf1 physical addr is NULL for "
++ "triple buffer mode\n", dma_chan);
++ return -EINVAL;
++ }
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* Build parameter memory data for DMA channel */
++ _ipu_ch_param_init(ipu, dma_chan, pixel_fmt, width, height, stride, u, v, 0,
++ phyaddr_0, phyaddr_1, phyaddr_2);
++
++ /* Set correlative channel parameter of local alpha channel */
++ if ((_ipu_is_ic_graphic_chan(dma_chan) ||
++ _ipu_is_dp_graphic_chan(dma_chan)) &&
++ (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] == true)) {
++ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, true);
++ _ipu_ch_param_set_alpha_buffer_memory(ipu, dma_chan);
++ _ipu_ch_param_set_alpha_condition_read(ipu, dma_chan);
++ /* fix alpha width as 8 and burst size as 16*/
++ _ipu_ch_params_set_alpha_width(ipu, dma_chan, 8);
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
++ } else if (_ipu_is_ic_graphic_chan(dma_chan) &&
++ ipu_pixel_format_has_alpha(pixel_fmt))
++ _ipu_ch_param_set_alpha_use_separate_channel(ipu, dma_chan, false);
++
++ if (rot_mode)
++ _ipu_ch_param_set_rotation(ipu, dma_chan, rot_mode);
++
++ /* IC and ROT channels have restriction of 8 or 16 pix burst length */
++ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_vdi_out_chan(dma_chan)) {
++ if ((width % 16) == 0)
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 16);
++ else
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
++ } else if (_ipu_is_irt_chan(dma_chan)) {
++ _ipu_ch_param_set_burst_size(ipu, dma_chan, 8);
++ _ipu_ch_param_set_block_mode(ipu, dma_chan);
++ } else if (_ipu_is_dmfc_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ _ipu_dmfc_set_wait4eot(ipu, dma_chan, width);
++ _ipu_dmfc_set_burst_size(ipu, dma_chan, burst_size);
++ }
++
++ if (_ipu_disp_chan_is_interlaced(ipu, channel) ||
++ ipu->chan_is_interlaced[dma_chan])
++ _ipu_ch_param_set_interlaced_scan(ipu, dma_chan);
++
++ if (_ipu_is_ic_chan(dma_chan) || _ipu_is_irt_chan(dma_chan) ||
++ _ipu_is_vdi_out_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ _ipu_ic_idma_init(ipu, dma_chan, width, height, burst_size,
++ rot_mode);
++ } else if (_ipu_is_smfc_chan(dma_chan)) {
++ burst_size = _ipu_ch_param_get_burst_size(ipu, dma_chan);
++ /*
++ * This is different from IPUv3 spec, but it is confirmed
++ * in IPUforum that SMFC burst size should be NPB[6:3]
++ * when IDMAC works in 16-bit generic data mode.
++ */
++ if (pixel_fmt == IPU_PIX_FMT_GENERIC)
++ /* 8 bits per pixel */
++ burst_size = burst_size >> 4;
++ else if (pixel_fmt == IPU_PIX_FMT_GENERIC_16)
++ /* 16 bits per pixel */
++ burst_size = burst_size >> 3;
++ else
++ burst_size = burst_size >> 2;
++ _ipu_smfc_set_burst_size(ipu, channel, burst_size-1);
++ }
++
++ /* AXI-id */
++ if (idma_is_set(ipu, IDMAC_CHA_PRI, dma_chan)) {
++ unsigned reg = IDMAC_CH_LOCK_EN_1;
++ uint32_t value = 0;
++ if (ipu->pdata->devtype == IPU_V3H) {
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 0);
++ switch (dma_chan) {
++ case 5:
++ value = 0x3;
++ break;
++ case 11:
++ value = 0x3 << 2;
++ break;
++ case 12:
++ value = 0x3 << 4;
++ break;
++ case 14:
++ value = 0x3 << 6;
++ break;
++ case 15:
++ value = 0x3 << 8;
++ break;
++ case 20:
++ value = 0x3 << 10;
++ break;
++ case 21:
++ value = 0x3 << 12;
++ break;
++ case 22:
++ value = 0x3 << 14;
++ break;
++ case 23:
++ value = 0x3 << 16;
++ break;
++ case 27:
++ value = 0x3 << 18;
++ break;
++ case 28:
++ value = 0x3 << 20;
++ break;
++ case 45:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 0;
++ break;
++ case 46:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 2;
++ break;
++ case 47:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 4;
++ break;
++ case 48:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 6;
++ break;
++ case 49:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 8;
++ break;
++ case 50:
++ reg = IDMAC_CH_LOCK_EN_2;
++ value = 0x3 << 10;
++ break;
++ default:
++ break;
++ }
++ value |= ipu_idmac_read(ipu, reg);
++ ipu_idmac_write(ipu, value, reg);
++ } else
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
++ } else {
++ if (ipu->pdata->devtype == IPU_V3H)
++ _ipu_ch_param_set_axi_id(ipu, dma_chan, 1);
++ }
++
++ _ipu_ch_param_dump(ipu, dma_chan);
++
++ if (phyaddr_2 && g_ipu_hw_rev >= IPU_V3DEX) {
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
++
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ reg |= idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
++
++ /* Set IDMAC third buffer's cpmem number */
++ /* See __ipu_ch_get_third_buf_cpmem_num() for mapping */
++ ipu_idmac_write(ipu, 0x00444047L, IDMAC_SUB_ADDR_4);
++ ipu_idmac_write(ipu, 0x46004241L, IDMAC_SUB_ADDR_3);
++ ipu_idmac_write(ipu, 0x00000045L, IDMAC_SUB_ADDR_1);
++
++ /* Reset to buffer 0 */
++ ipu_cm_write(ipu, tri_cur_buf_mask(dma_chan),
++ IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
++ } else {
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_TRB_MODE_SEL(dma_chan));
++
++ reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(dma_chan));
++ if (phyaddr_1)
++ reg |= idma_mask(dma_chan);
++ else
++ reg &= ~idma_mask(dma_chan);
++ ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(dma_chan));
++
++ /* Reset to buffer 0 */
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_CUR_BUF(dma_chan));
++
++ }
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_channel_buffer);
++
++/*!
++ * This function is called to update the physical address of a buffer for
++ * a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param bufNum Input parameter for buffer number to update.
++ * 0 or 1 are the only valid values.
++ *
++ * @param phyaddr Input parameter buffer physical address.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail. This function will fail if the buffer is set to ready.
++ */
++int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum, dma_addr_t phyaddr)
++{
++ uint32_t reg;
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if (bufNum == 0)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
++
++ if ((reg & idma_mask(dma_chan)) == 0)
++ _ipu_ch_param_set_buffer(ipu, dma_chan, bufNum, phyaddr);
++ else
++ ret = -EACCES;
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_update_channel_buffer);
++
++/*!
++ * This function is called to update the band mode setting for
++ * a logical IPU channel.
++ *
++ * @param ipu ipu handler
++ *
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param band_height Input parameter for band lines:
++ * shoule be log2(4/8/16/32/64/128/256).
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t band_height)
++{
++ uint32_t reg;
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++
++ if ((2 > band_height) || (8 < band_height))
++ return -EINVAL;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ reg = ipu_idmac_read(ipu, IDMAC_BAND_EN(dma_chan));
++ reg |= 1 << (dma_chan % 32);
++ ipu_idmac_write(ipu, reg, IDMAC_BAND_EN(dma_chan));
++
++ _ipu_ch_param_set_bandmode(ipu, dma_chan, band_height);
++ dev_dbg(ipu->dev, "dma_chan:%d, band_height:%d.\n\n",
++ dma_chan, 1 << band_height);
++ mutex_unlock(&ipu->mutex_lock);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_set_channel_bandmode);
++
++/*!
++ * This function is called to initialize a buffer for logical IPU channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width Input parameter for width of buffer in pixels.
++ *
++ * @param height Input parameter for height of buffer in pixels.
++ *
++ * @param stride Input parameter for stride length of buffer
++ * in pixels.
++ *
++ * @param u predefined private u offset for additional cropping,
++ * zero if not used.
++ *
++ * @param v predefined private v offset for additional cropping,
++ * zero if not used.
++ *
++ * @param vertical_offset vertical offset for Y coordinate
++ * in the existed frame
++ *
++ *
++ * @param horizontal_offset horizontal offset for X coordinate
++ * in the existed frame
++ *
++ *
++ * @return Returns 0 on success or negative error code on fail
++ * This function will fail if any buffer is set to ready.
++ */
++
++int32_t ipu_update_channel_offset(struct ipu_soc *ipu,
++ ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t vertical_offset, uint32_t horizontal_offset)
++{
++ int ret = 0;
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if ((ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan)) & idma_mask(dma_chan)) ||
++ (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan)) & idma_mask(dma_chan)) ||
++ ((ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan)) & idma_mask(dma_chan)) &&
++ (ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan)) & idma_mask(dma_chan)) &&
++ _ipu_is_trb_chan(dma_chan)))
++ ret = -EACCES;
++ else
++ _ipu_ch_offset_update(ipu, dma_chan, pixel_fmt, width, height, stride,
++ u, v, 0, vertical_offset, horizontal_offset);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_update_channel_offset);
++
++
++/*!
++ * This function is called to set a channel's buffer as ready.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to initialize.
++ *
++ * @param bufNum Input parameter for which buffer number set to
++ * ready state.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum)
++{
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Mark buffer to be ready. */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ ipu_cm_write(ipu, idma_mask(dma_chan),
++ IPU_CHA_BUF2_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_select_buffer);
++
++/*!
++ * This function is called to set a channel's buffer as ready.
++ *
++ * @param ipu ipu handler
++ * @param bufNum Input parameter for which buffer number set to
++ * ready state.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum)
++{
++
++ uint32_t dma_chan = channel_2_dma(MEM_VDI_PRP_VF_MEM, IPU_INPUT_BUFFER);
++ uint32_t mask_bit =
++ idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_P, IPU_INPUT_BUFFER))|
++ idma_mask(dma_chan)|
++ idma_mask(channel_2_dma(MEM_VDI_PRP_VF_MEM_N, IPU_INPUT_BUFFER));
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Mark buffers to be ready. */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF0_RDY(dma_chan));
++ else
++ ipu_cm_write(ipu, mask_bit, IPU_CHA_BUF1_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_select_multi_vdi_buffer);
++
++#define NA -1
++static int proc_dest_sel[] = {
++ 0, 1, 1, 3, 5, 5, 4, 7, 8, 9, 10, 11, 12, 14, 15, 16,
++ 0, 1, 1, 5, 5, 5, 5, 5, 7, 8, 9, 10, 11, 12, 14, 31 };
++static int proc_src_sel[] = { 0, 6, 7, 6, 7, 8, 5, NA, NA, NA,
++ NA, NA, NA, NA, NA, 1, 2, 3, 4, 7, 8, NA, 8, NA };
++static int disp_src_sel[] = { 0, 6, 7, 8, 3, 4, 5, NA, NA, NA,
++ NA, NA, NA, NA, NA, 1, NA, 2, NA, 3, 4, 4, 4, 4 };
++
++
++/*!
++ * This function links 2 channels together for automatic frame
++ * synchronization. The output of the source channel is linked to the input of
++ * the destination channel.
++ *
++ * @param ipu ipu handler
++ * @param src_ch Input parameter for the logical channel ID of
++ * the source channel.
++ *
++ * @param dest_ch Input parameter for the logical channel ID of
++ * the destination channel.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
++{
++ int retval = 0;
++ uint32_t fs_proc_flow1;
++ uint32_t fs_proc_flow2;
++ uint32_t fs_proc_flow3;
++ uint32_t fs_disp_flow1;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
++ fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
++ fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
++
++ switch (src_ch) {
++ case CSI_MEM0:
++ fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC0_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM1:
++ fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC1_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM2:
++ fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC2_DEST_SEL_OFFSET;
++ break;
++ case CSI_MEM3:
++ fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
++ fs_proc_flow3 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_SMFC3_DEST_SEL_OFFSET;
++ break;
++ case CSI_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_DEST_SEL_OFFSET;
++ break;
++ case CSI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PP_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PP_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPENC_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_DEST_SEL_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
++ fs_proc_flow2 |=
++ proc_dest_sel[IPU_CHAN_ID(dest_ch)] <<
++ FS_PRPVF_ROT_DEST_SEL_OFFSET;
++ break;
++ case MEM_VDOA_MEM:
++ fs_proc_flow3 &= ~FS_VDOA_DEST_SEL_MASK;
++ if (MEM_VDI_MEM == dest_ch)
++ fs_proc_flow3 |= FS_VDOA_DEST_SEL_VDI;
++ else if (MEM_PP_MEM == dest_ch)
++ fs_proc_flow3 |= FS_VDOA_DEST_SEL_IC;
++ else {
++ retval = -EINVAL;
++ goto err;
++ }
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ switch (dest_ch) {
++ case MEM_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
++ if (MEM_VDOA_MEM == src_ch)
++ fs_proc_flow1 |= FS_PP_SRC_SEL_VDOA;
++ else
++ fs_proc_flow1 |= proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PP_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PRPENC_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] << FS_PRP_SRC_SEL_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
++ fs_proc_flow1 |=
++ proc_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_PRPVF_ROT_SRC_SEL_OFFSET;
++ break;
++ case MEM_DC_SYNC:
++ fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_BG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_SYNC0_SRC_SEL_OFFSET;
++ break;
++ case MEM_FG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_SYNC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_DC_ASYNC:
++ fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] << FS_DC2_SRC_SEL_OFFSET;
++ break;
++ case MEM_BG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_ASYNC0_SRC_SEL_OFFSET;
++ break;
++ case MEM_FG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
++ fs_disp_flow1 |=
++ disp_src_sel[IPU_CHAN_ID(src_ch)] <<
++ FS_DP_ASYNC1_SRC_SEL_OFFSET;
++ break;
++ case MEM_VDI_MEM:
++ fs_proc_flow1 &= ~FS_VDI_SRC_SEL_MASK;
++ if (MEM_VDOA_MEM == src_ch)
++ fs_proc_flow1 |= FS_VDI_SRC_SEL_VDOA;
++ else {
++ retval = -EINVAL;
++ goto err;
++ }
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
++ ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
++ ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return retval;
++}
++EXPORT_SYMBOL(ipu_link_channels);
++
++/*!
++ * This function unlinks 2 channels and disables automatic frame
++ * synchronization.
++ *
++ * @param ipu ipu handler
++ * @param src_ch Input parameter for the logical channel ID of
++ * the source channel.
++ *
++ * @param dest_ch Input parameter for the logical channel ID of
++ * the destination channel.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch)
++{
++ int retval = 0;
++ uint32_t fs_proc_flow1;
++ uint32_t fs_proc_flow2;
++ uint32_t fs_proc_flow3;
++ uint32_t fs_disp_flow1;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1);
++ fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2);
++ fs_proc_flow3 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW3);
++ fs_disp_flow1 = ipu_cm_read(ipu, IPU_FS_DISP_FLOW1);
++
++ switch (src_ch) {
++ case CSI_MEM0:
++ fs_proc_flow3 &= ~FS_SMFC0_DEST_SEL_MASK;
++ break;
++ case CSI_MEM1:
++ fs_proc_flow3 &= ~FS_SMFC1_DEST_SEL_MASK;
++ break;
++ case CSI_MEM2:
++ fs_proc_flow3 &= ~FS_SMFC2_DEST_SEL_MASK;
++ break;
++ case CSI_MEM3:
++ fs_proc_flow3 &= ~FS_SMFC3_DEST_SEL_MASK;
++ break;
++ case CSI_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ break;
++ case CSI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow2 &= ~FS_PP_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow2 &= ~FS_PRPENC_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow2 &= ~FS_PRPVF_ROT_DEST_SEL_MASK;
++ break;
++ case MEM_VDOA_MEM:
++ fs_proc_flow3 &= ~FS_VDOA_DEST_SEL_MASK;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ switch (dest_ch) {
++ case MEM_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_PP_MEM:
++ fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_PRP_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_ENC_MEM:
++ fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRP_SRC_SEL_MASK;
++ break;
++ case MEM_ROT_VF_MEM:
++ fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK;
++ break;
++ case MEM_DC_SYNC:
++ fs_disp_flow1 &= ~FS_DC1_SRC_SEL_MASK;
++ break;
++ case MEM_BG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC0_SRC_SEL_MASK;
++ break;
++ case MEM_FG_SYNC:
++ fs_disp_flow1 &= ~FS_DP_SYNC1_SRC_SEL_MASK;
++ break;
++ case MEM_DC_ASYNC:
++ fs_disp_flow1 &= ~FS_DC2_SRC_SEL_MASK;
++ break;
++ case MEM_BG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC0_SRC_SEL_MASK;
++ break;
++ case MEM_FG_ASYNC0:
++ fs_disp_flow1 &= ~FS_DP_ASYNC1_SRC_SEL_MASK;
++ break;
++ case MEM_VDI_MEM:
++ fs_proc_flow1 &= ~FS_VDI_SRC_SEL_MASK;
++ break;
++ default:
++ retval = -EINVAL;
++ goto err;
++ }
++
++ ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1);
++ ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2);
++ ipu_cm_write(ipu, fs_proc_flow3, IPU_FS_PROC_FLOW3);
++ ipu_cm_write(ipu, fs_disp_flow1, IPU_FS_DISP_FLOW1);
++
++err:
++ mutex_unlock(&ipu->mutex_lock);
++ return retval;
++}
++EXPORT_SYMBOL(ipu_unlink_channels);
++
++/*!
++ * This function check whether a logical channel was enabled.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 1 while request channel is enabled or
++ * 0 for not enabled.
++ */
++int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t in_dma;
++ uint32_t out_dma;
++
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ if (reg & idma_mask(in_dma))
++ return 1;
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ if (reg & idma_mask(out_dma))
++ return 1;
++ return 0;
++}
++EXPORT_SYMBOL(ipu_is_channel_busy);
++
++/*!
++ * This function enables a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t reg;
++ uint32_t ipu_conf;
++ uint32_t in_dma;
++ uint32_t out_dma;
++ uint32_t sec_dma;
++ uint32_t thrd_dma;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
++ dev_err(ipu->dev, "Warning: channel already enabled %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return -EACCES;
++ }
++
++ /* Get input and output dma channels */
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ ipu_conf = ipu_cm_read(ipu, IPU_CONF);
++ if (ipu->di_use_count[0] > 0) {
++ ipu_conf |= IPU_CONF_DI0_EN;
++ }
++ if (ipu->di_use_count[1] > 0) {
++ ipu_conf |= IPU_CONF_DI1_EN;
++ }
++ if (ipu->dp_use_count > 0)
++ ipu_conf |= IPU_CONF_DP_EN;
++ if (ipu->dc_use_count > 0)
++ ipu_conf |= IPU_CONF_DC_EN;
++ if (ipu->dmfc_use_count > 0)
++ ipu_conf |= IPU_CONF_DMFC_EN;
++ if (ipu->ic_use_count > 0)
++ ipu_conf |= IPU_CONF_IC_EN;
++ if (ipu->vdi_use_count > 0) {
++ ipu_conf |= IPU_CONF_ISP_EN;
++ ipu_conf |= IPU_CONF_VDI_EN;
++ ipu_conf |= IPU_CONF_IC_INPUT;
++ }
++ if (ipu->rot_use_count > 0)
++ ipu_conf |= IPU_CONF_ROT_EN;
++ if (ipu->smfc_use_count > 0)
++ ipu_conf |= IPU_CONF_SMFC_EN;
++ ipu_cm_write(ipu, ipu_conf, IPU_CONF);
++
++ if (idma_is_valid(in_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
++ }
++ if (idma_is_valid(out_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
++ }
++
++ if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
++ (channel == MEM_VDI_PRP_VF_MEM))) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
++ }
++ if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg | idma_mask(sec_dma), IDMAC_SEP_ALPHA);
++ } else if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
++ ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))) {
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_SEP_ALPHA);
++ }
++
++ if ((channel == MEM_DC_SYNC) || (channel == MEM_BG_SYNC) ||
++ (channel == MEM_FG_SYNC)) {
++ reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(in_dma), IDMAC_WM_EN(in_dma));
++
++ _ipu_dp_dc_enable(ipu, channel);
++ }
++
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
++ _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma) ||
++ _ipu_is_vdi_out_chan(out_dma))
++ _ipu_ic_enable_task(ipu, channel);
++
++ ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(channel);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_enable_channel);
++
++/*!
++ * This function check buffer ready for a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to clear.
++ *
++ * @param bufNum Input parameter for which buffer number clear
++ * ready state.
++ *
++ */
++int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ uint32_t dma_chan = channel_2_dma(channel, type);
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ if (dma_chan == IDMA_CHAN_INVALID)
++ return -EINVAL;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ if (bufNum == 0)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(dma_chan));
++ else if (bufNum == 1)
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(dma_chan));
++ else
++ reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(dma_chan));
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ if (reg & idma_mask(dma_chan))
++ return 1;
++ else
++ return 0;
++}
++EXPORT_SYMBOL(ipu_check_buffer_ready);
++
++/*!
++ * This function clear buffer ready for a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param type Input parameter which buffer to clear.
++ *
++ * @param bufNum Input parameter for which buffer number clear
++ * ready state.
++ *
++ */
++void _ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ uint32_t dma_ch = channel_2_dma(channel, type);
++
++ if (!idma_is_valid(dma_ch))
++ return;
++
++ ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
++ if (bufNum == 0)
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF0_RDY(dma_ch));
++ else if (bufNum == 1)
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF1_RDY(dma_ch));
++ else
++ ipu_cm_write(ipu, idma_mask(dma_ch),
++ IPU_CHA_BUF2_RDY(dma_ch));
++ ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
++}
++
++void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum)
++{
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ _ipu_clear_buffer_ready(ipu, channel, type, bufNum);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++}
++EXPORT_SYMBOL(ipu_clear_buffer_ready);
++
++/*!
++ * This function disables a logical channel.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param wait_for_stop Flag to set whether to wait for channel end
++ * of frame or return immediately.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop)
++{
++ uint32_t reg;
++ uint32_t in_dma;
++ uint32_t out_dma;
++ uint32_t sec_dma = NO_DMA;
++ uint32_t thrd_dma = NO_DMA;
++ uint16_t fg_pos_x, fg_pos_y;
++ unsigned long lock_flags;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if ((ipu->channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
++ dev_dbg(ipu->dev, "Channel already disabled %d\n",
++ IPU_CHAN_ID(channel));
++ mutex_unlock(&ipu->mutex_lock);
++ return -EACCES;
++ }
++
++ /* Get input and output dma channels */
++ out_dma = channel_2_dma(channel, IPU_OUTPUT_BUFFER);
++ in_dma = channel_2_dma(channel, IPU_VIDEO_IN_BUFFER);
++
++ if ((idma_is_valid(in_dma) &&
++ !idma_is_set(ipu, IDMAC_CHA_EN, in_dma))
++ && (idma_is_valid(out_dma) &&
++ !idma_is_set(ipu, IDMAC_CHA_EN, out_dma))) {
++ mutex_unlock(&ipu->mutex_lock);
++ return -EINVAL;
++ }
++
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)])
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) {
++ sec_dma = channel_2_dma(channel, IPU_GRAPH_IN_BUFFER);
++ thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);
++ }
++
++ if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
++ (channel == MEM_DC_SYNC)) {
++ if (channel == MEM_FG_SYNC) {
++ _ipu_disp_get_window_pos(ipu, channel, &fg_pos_x, &fg_pos_y);
++ _ipu_disp_set_window_pos(ipu, channel, 0, 0);
++ }
++
++ _ipu_dp_dc_disable(ipu, channel, false);
++
++ /*
++ * wait for BG channel EOF then disable FG-IDMAC,
++ * it avoid FG NFB4EOF error.
++ */
++ if ((channel == MEM_FG_SYNC) && (ipu_is_channel_busy(ipu, MEM_BG_SYNC))) {
++ int timeout = 50;
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
++ IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF));
++ while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_BG_SYNC_EOF)) &
++ IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF)) == 0) {
++ msleep(10);
++ timeout -= 10;
++ if (timeout <= 0) {
++ dev_err(ipu->dev, "warning: wait for bg sync eof timeout\n");
++ break;
++ }
++ }
++ }
++ } else if (wait_for_stop && !_ipu_is_smfc_chan(out_dma) &&
++ channel != CSI_PRP_VF_MEM && channel != CSI_PRP_ENC_MEM) {
++ while (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma) ||
++ idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma) ||
++ (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma)) ||
++ (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))) {
++ uint32_t irq = 0xffffffff;
++ int timeout = 50000;
++
++ if (idma_is_set(ipu, IDMAC_CHA_BUSY, out_dma))
++ irq = out_dma;
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, sec_dma))
++ irq = sec_dma;
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] &&
++ idma_is_set(ipu, IDMAC_CHA_BUSY, thrd_dma))
++ irq = thrd_dma;
++ if (idma_is_set(ipu, IDMAC_CHA_BUSY, in_dma))
++ irq = in_dma;
++
++ if (irq == 0xffffffff) {
++ dev_dbg(ipu->dev, "warning: no channel busy, break\n");
++ break;
++ }
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq),
++ IPUIRQ_2_STATREG(irq));
++
++ dev_dbg(ipu->dev, "warning: channel %d busy, need wait\n", irq);
++
++ while (((ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq))
++ & IPUIRQ_2_MASK(irq)) == 0) &&
++ (idma_is_set(ipu, IDMAC_CHA_BUSY, irq))) {
++ udelay(10);
++ timeout -= 10;
++ if (timeout <= 0) {
++ ipu_dump_registers(ipu);
++ dev_err(ipu->dev, "warning: disable ipu dma channel %d during its busy state\n", irq);
++ break;
++ }
++ }
++ dev_dbg(ipu->dev, "wait_time:%d\n", 50000 - timeout);
++
++ }
++ }
++
++ if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC) ||
++ (channel == MEM_DC_SYNC)) {
++ reg = ipu_idmac_read(ipu, IDMAC_WM_EN(in_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_WM_EN(in_dma));
++ }
++
++ /* Disable IC task */
++ if (_ipu_is_ic_chan(in_dma) || _ipu_is_ic_chan(out_dma) ||
++ _ipu_is_irt_chan(in_dma) || _ipu_is_irt_chan(out_dma) ||
++ _ipu_is_vdi_out_chan(out_dma))
++ _ipu_ic_disable_task(ipu, channel);
++
++ /* Disable DMA channel(s) */
++ if (idma_is_valid(in_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(in_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_CHA_EN(in_dma));
++ ipu_cm_write(ipu, idma_mask(in_dma), IPU_CHA_CUR_BUF(in_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(in_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(in_dma));
++ }
++ if (idma_is_valid(out_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(out_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(out_dma), IDMAC_CHA_EN(out_dma));
++ ipu_cm_write(ipu, idma_mask(out_dma), IPU_CHA_CUR_BUF(out_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(out_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(out_dma));
++ }
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(sec_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_CHA_EN(sec_dma));
++ ipu_cm_write(ipu, idma_mask(sec_dma), IPU_CHA_CUR_BUF(sec_dma));
++ }
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(thrd_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(thrd_dma), IDMAC_CHA_EN(thrd_dma));
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC) {
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg & ~idma_mask(in_dma), IDMAC_SEP_ALPHA);
++ } else {
++ reg = ipu_idmac_read(ipu, IDMAC_SEP_ALPHA);
++ ipu_idmac_write(ipu, reg & ~idma_mask(sec_dma), IDMAC_SEP_ALPHA);
++ }
++ ipu_cm_write(ipu, idma_mask(thrd_dma), IPU_CHA_CUR_BUF(thrd_dma));
++ }
++
++ if (channel == MEM_FG_SYNC)
++ _ipu_disp_set_window_pos(ipu, channel, fg_pos_x, fg_pos_y);
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ /* Set channel buffers NOT to be ready */
++ if (idma_is_valid(in_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 1);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_VIDEO_IN_BUFFER, 2);
++ }
++ if (idma_is_valid(out_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_OUTPUT_BUFFER, 1);
++ }
++ if (ipu->sec_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(sec_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_GRAPH_IN_BUFFER, 1);
++ }
++ if (ipu->thrd_chan_en[IPU_CHAN_ID(channel)] && idma_is_valid(thrd_dma)) {
++ _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, channel, IPU_ALPHA_IN_BUFFER, 1);
++ }
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(channel));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disable_channel);
++
++int32_t ipu_channel_disable(struct ipu_chan *ipu_chan, bool wait_for_stop)
++{
++ if (ipu_chan)
++ if (!IS_ERR(ipu_chan))
++ return ipu_disable_channel(ipu_chan->ipu, ipu_chan->channel, wait_for_stop);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_channel_disable);
++
++/*!
++ * This function enables CSI.
++ *
++ * @param ipu ipu handler
++ * @param csi csi num 0 or 1
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t reg;
++
++ if (csi > 1) {
++ dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
++ return -EINVAL;
++ }
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ipu->csi_use_count[csi]++;
++
++ if (ipu->csi_use_count[csi] == 1) {
++ reg = ipu_cm_read(ipu, IPU_CONF);
++ if (csi == 0)
++ ipu_cm_write(ipu, reg | IPU_CONF_CSI0_EN, IPU_CONF);
++ else
++ ipu_cm_write(ipu, reg | IPU_CONF_CSI1_EN, IPU_CONF);
++ }
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_enable_csi);
++
++/*!
++ * This function disables CSI.
++ *
++ * @param ipu ipu handler
++ * @param csi csi num 0 or 1
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi)
++{
++ uint32_t reg;
++
++ if (csi > 1) {
++ dev_err(ipu->dev, "Wrong csi num_%d\n", csi);
++ return -EINVAL;
++ }
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ipu->csi_use_count[csi]--;
++ if (ipu->csi_use_count[csi] == 0) {
++ _ipu_csi_wait4eof(ipu, ipu->csi_channel[csi]);
++ reg = ipu_cm_read(ipu, IPU_CONF);
++ if (csi == 0)
++ ipu_cm_write(ipu, reg & ~IPU_CONF_CSI0_EN, IPU_CONF);
++ else
++ ipu_cm_write(ipu, reg & ~IPU_CONF_CSI1_EN, IPU_CONF);
++ }
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disable_csi);
++
++static irqreturn_t ipu_sync_irq_handler(int irq, void *desc)
++{
++ struct ipu_soc *ipu = desc;
++ int i;
++ uint32_t line, bit, int_stat, int_ctrl;
++ irqreturn_t result = IRQ_NONE;
++ const int int_reg[] = { 1, 2, 3, 4, 11, 12, 13, 14, 15, 0 };
++
++ spin_lock(&ipu->int_reg_spin_lock);
++
++ for (i = 0; int_reg[i] != 0; i++) {
++ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(int_reg[i]));
++ int_ctrl = ipu_cm_read(ipu, IPU_INT_CTRL(int_reg[i]));
++ int_stat &= int_ctrl;
++ ipu_cm_write(ipu, int_stat, IPU_INT_STAT(int_reg[i]));
++ while ((line = ffs(int_stat)) != 0) {
++ bit = --line;
++ int_stat &= ~(1UL << line);
++ line += (int_reg[i] - 1) * 32;
++ result |=
++ ipu->irq_list[line].handler(line,
++ ipu->irq_list[line].
++ dev_id);
++ if (ipu->irq_list[line].flags & IPU_IRQF_ONESHOT) {
++ int_ctrl &= ~(1UL << bit);
++ ipu_cm_write(ipu, int_ctrl,
++ IPU_INT_CTRL(int_reg[i]));
++ }
++ }
++ }
++
++ spin_unlock(&ipu->int_reg_spin_lock);
++
++ return result;
++}
++
++static irqreturn_t ipu_err_irq_handler(int irq, void *desc)
++{
++ struct ipu_soc *ipu = desc;
++ int i;
++ uint32_t int_stat;
++ const int err_reg[] = { 5, 6, 9, 10, 0 };
++
++ spin_lock(&ipu->int_reg_spin_lock);
++
++ for (i = 0; err_reg[i] != 0; i++) {
++ int_stat = ipu_cm_read(ipu, IPU_INT_STAT(err_reg[i]));
++ int_stat &= ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i]));
++ if (int_stat) {
++ ipu_cm_write(ipu, int_stat, IPU_INT_STAT(err_reg[i]));
++ dev_warn(ipu->dev,
++ "IPU Warning - IPU_INT_STAT_%d = 0x%08X\n",
++ err_reg[i], int_stat);
++ /* Disable interrupts so we only get error once */
++ int_stat = ipu_cm_read(ipu, IPU_INT_CTRL(err_reg[i])) &
++ ~int_stat;
++ ipu_cm_write(ipu, int_stat, IPU_INT_CTRL(err_reg[i]));
++ }
++ }
++
++ spin_unlock(&ipu->int_reg_spin_lock);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * This function enables the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to enable interrupt for.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int ret = 0;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ /*
++ * Check sync interrupt handler only, since we do nothing for
++ * error interrupts but than print out register values in the
++ * error interrupt source handler.
++ */
++ if (_ipu_is_sync_irq(irq) && (ipu->irq_list[irq].handler == NULL)) {
++ dev_err(ipu->dev, "handler hasn't been registered on sync "
++ "irq %d\n", irq);
++ ret = -EACCES;
++ goto out;
++ }
++
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg |= IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++out:
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_enable_irq);
++
++/*!
++ * This function disables the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to disable interrupt for.
++ *
++ */
++void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg &= ~IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_disable_irq);
++
++/*!
++ * This function clears the interrupt for the specified interrupt line.
++ * The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to clear interrupt for.
++ *
++ */
++void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq)
++{
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_clear_irq);
++
++/*!
++ * This function returns the current interrupt status for the specified
++ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @return Returns true if the interrupt is pending/asserted or false if
++ * the interrupt is not pending.
++ */
++bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++ reg = ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq));
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ if (reg & IPUIRQ_2_MASK(irq))
++ return true;
++ else
++ return false;
++}
++EXPORT_SYMBOL(ipu_get_irq_status);
++
++/*!
++ * This function registers an interrupt handler function for the specified
++ * interrupt line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @param handler Input parameter for address of the handler
++ * function.
++ *
++ * @param irq_flags Flags for interrupt mode. Currently not used.
++ *
++ * @param devname Input parameter for string name of driver
++ * registering the handler.
++ *
++ * @param dev_id Input parameter for pointer of data to be
++ * passed to the handler.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
++ irqreturn_t(*handler) (int, void *),
++ uint32_t irq_flags, const char *devname, void *dev_id)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int ret = 0;
++
++ BUG_ON(irq >= IPU_IRQ_COUNT);
++
++ _ipu_get(ipu);
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ if (ipu->irq_list[irq].handler != NULL) {
++ dev_err(ipu->dev,
++ "handler already installed on irq %d\n", irq);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ /*
++ * Check sync interrupt handler only, since we do nothing for
++ * error interrupts but than print out register values in the
++ * error interrupt source handler.
++ */
++ if (_ipu_is_sync_irq(irq) && (handler == NULL)) {
++ dev_err(ipu->dev, "handler is NULL for sync irq %d\n", irq);
++ ret = -EINVAL;
++ goto out;
++ }
++
++ ipu->irq_list[irq].handler = handler;
++ ipu->irq_list[irq].flags = irq_flags;
++ ipu->irq_list[irq].dev_id = dev_id;
++ ipu->irq_list[irq].name = devname;
++
++ /* clear irq stat for previous use */
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq));
++ /* enable the interrupt */
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg |= IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++out:
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++
++ return ret;
++}
++EXPORT_SYMBOL(ipu_request_irq);
++
++/*!
++ * This function unregisters an interrupt handler for the specified interrupt
++ * line. The interrupt lines are defined in \b ipu_irq_line enum.
++ *
++ * @param ipu ipu handler
++ * @param irq Interrupt line to get status for.
++ *
++ * @param dev_id Input parameter for pointer of data to be passed
++ * to the handler. This must match value passed to
++ * ipu_request_irq().
++ *
++ */
++void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++
++ _ipu_get(ipu);
++
++ if (ipu->irq_list[irq].dev_id != dev_id)
++ return;
++
++ spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
++
++ /* disable the interrupt */
++ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
++ reg &= ~IPUIRQ_2_MASK(irq);
++ ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
++ memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq]));
++
++ spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
++
++ _ipu_put(ipu);
++}
++EXPORT_SYMBOL(ipu_free_irq);
++
++uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type)
++{
++ uint32_t reg, dma_chan;
++
++ dma_chan = channel_2_dma(channel, type);
++ if (!idma_is_valid(dma_chan))
++ return -EINVAL;
++
++ reg = ipu_cm_read(ipu, IPU_CHA_TRB_MODE_SEL(dma_chan));
++ if ((reg & idma_mask(dma_chan)) && _ipu_is_trb_chan(dma_chan)) {
++ reg = ipu_cm_read(ipu, IPU_CHA_TRIPLE_CUR_BUF(dma_chan));
++ return (reg & tri_cur_buf_mask(dma_chan)) >>
++ tri_cur_buf_shift(dma_chan);
++ } else {
++ reg = ipu_cm_read(ipu, IPU_CHA_CUR_BUF(dma_chan));
++ if (reg & idma_mask(dma_chan))
++ return 1;
++ else
++ return 0;
++ }
++}
++EXPORT_SYMBOL(ipu_get_cur_buffer_idx);
++
++uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t stat = 0;
++ uint32_t task_stat_reg = ipu_cm_read(ipu, IPU_PROC_TASK_STAT);
++
++ switch (channel) {
++ case MEM_PRP_VF_MEM:
++ stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ stat = (task_stat_reg & TSTAT_VF_MASK) >> TSTAT_VF_OFFSET;
++ break;
++ case MEM_ROT_VF_MEM:
++ stat =
++ (task_stat_reg & TSTAT_VF_ROT_MASK) >> TSTAT_VF_ROT_OFFSET;
++ break;
++ case MEM_PRP_ENC_MEM:
++ stat = (task_stat_reg & TSTAT_ENC_MASK) >> TSTAT_ENC_OFFSET;
++ break;
++ case MEM_ROT_ENC_MEM:
++ stat =
++ (task_stat_reg & TSTAT_ENC_ROT_MASK) >>
++ TSTAT_ENC_ROT_OFFSET;
++ break;
++ case MEM_PP_MEM:
++ stat = (task_stat_reg & TSTAT_PP_MASK) >> TSTAT_PP_OFFSET;
++ break;
++ case MEM_ROT_PP_MEM:
++ stat =
++ (task_stat_reg & TSTAT_PP_ROT_MASK) >> TSTAT_PP_ROT_OFFSET;
++ break;
++
++ default:
++ stat = TASK_STAT_IDLE;
++ break;
++ }
++ return stat;
++}
++
++/*!
++ * This function check for a logical channel status
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @return This function returns 0 on idle and 1 on busy.
++ *
++ */
++uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t dma_status;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ dma_status = ipu_is_channel_busy(ipu, channel);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++
++ dev_dbg(ipu->dev, "%s, dma_status:%d.\n", __func__, dma_status);
++
++ return dma_status;
++}
++EXPORT_SYMBOL(ipu_channel_status);
++
++int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch)
++{
++ uint32_t reg;
++ unsigned long lock_flags;
++ int from_dma = channel_2_dma(from_ch, IPU_INPUT_BUFFER);
++ int to_dma = channel_2_dma(to_ch, IPU_INPUT_BUFFER);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ /* enable target channel */
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(to_dma));
++ ipu_idmac_write(ipu, reg | idma_mask(to_dma), IDMAC_CHA_EN(to_dma));
++
++ ipu->channel_enable_mask |= 1L << IPU_CHAN_ID(to_ch);
++
++ /* switch dp dc */
++ _ipu_dp_dc_disable(ipu, from_ch, true);
++
++ /* disable source channel */
++ reg = ipu_idmac_read(ipu, IDMAC_CHA_EN(from_dma));
++ ipu_idmac_write(ipu, reg & ~idma_mask(from_dma), IDMAC_CHA_EN(from_dma));
++ ipu_cm_write(ipu, idma_mask(from_dma), IPU_CHA_CUR_BUF(from_dma));
++ ipu_cm_write(ipu, tri_cur_buf_mask(from_dma),
++ IPU_CHA_TRIPLE_CUR_BUF(from_dma));
++
++ ipu->channel_enable_mask &= ~(1L << IPU_CHAN_ID(from_ch));
++
++ spin_lock_irqsave(&ipu->rdy_reg_spin_lock, lock_flags);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 0);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 1);
++ _ipu_clear_buffer_ready(ipu, from_ch, IPU_VIDEO_IN_BUFFER, 2);
++ spin_unlock_irqrestore(&ipu->rdy_reg_spin_lock, lock_flags);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_swap_channel);
++
++uint32_t bytes_per_pixel(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_GENERIC: /*generic data */
++ case IPU_PIX_FMT_RGB332:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV444P:
++ return 1;
++ break;
++ case IPU_PIX_FMT_GENERIC_16: /* generic data */
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ return 2;
++ break;
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ return 3;
++ break;
++ case IPU_PIX_FMT_GENERIC_32: /*generic data */
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ return 4;
++ break;
++ default:
++ return 1;
++ break;
++ }
++ return 0;
++}
++EXPORT_SYMBOL(bytes_per_pixel);
++
++ipu_color_space_t format_to_colorspace(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_GBR24:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ case IPU_PIX_FMT_LVDS666:
++ case IPU_PIX_FMT_LVDS888:
++ return RGB;
++ break;
++
++ default:
++ return YCbCr;
++ break;
++ }
++ return RGB;
++}
++
++bool ipu_pixel_format_has_alpha(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_ABGR32:
++ return true;
++ break;
++ default:
++ return false;
++ break;
++ }
++ return false;
++}
++
++bool ipu_ch_param_bad_alpha_pos(uint32_t pixel_fmt)
++{
++ return _ipu_ch_param_bad_alpha_pos(pixel_fmt);
++}
++EXPORT_SYMBOL(ipu_ch_param_bad_alpha_pos);
++
++#ifdef CONFIG_PM
++static int ipu_suspend(struct device *dev)
++{
++ struct ipu_soc *ipu = dev_get_drvdata(dev);
++
++ /* All IDMAC channel and IPU clock should be disabled.*/
++ if (ipu->pdata->pg)
++ ipu->pdata->pg(1);
++
++ dev_dbg(dev, "ipu suspend.\n");
++ return 0;
++}
++
++static int ipu_resume(struct device *dev)
++{
++ struct ipu_soc *ipu = dev_get_drvdata(dev);
++
++ if (ipu->pdata->pg) {
++ ipu->pdata->pg(0);
++
++ _ipu_get(ipu);
++ _ipu_dmfc_init(ipu, dmfc_type_setup, 1);
++ /* Set sync refresh channels as high priority */
++ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0));
++ _ipu_put(ipu);
++ }
++ dev_dbg(dev, "ipu resume.\n");
++ return 0;
++}
++
++int ipu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high release.\n");
++
++ return 0;
++}
++
++int ipu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "ipu busfreq high requst.\n");
++
++ return 0;
++}
++
++static const struct dev_pm_ops ipu_pm_ops = {
++ SET_RUNTIME_PM_OPS(ipu_runtime_suspend, ipu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(ipu_suspend, ipu_resume)
++};
++#endif
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxcipu_driver = {
++ .driver = {
++ .name = "imx-ipuv3",
++ .of_match_table = imx_ipuv3_dt_ids,
++ #ifdef CONFIG_PM
++ .pm = &ipu_pm_ops,
++ #endif
++ },
++ .probe = ipu_probe,
++ .id_table = imx_ipu_type,
++ .remove = ipu_remove,
++};
++
++int32_t __init ipu_gen_init(void)
++{
++ int32_t ret;
++
++ ret = platform_driver_register(&mxcipu_driver);
++ return 0;
++}
++
++subsys_initcall(ipu_gen_init);
++
++static void __exit ipu_gen_uninit(void)
++{
++ platform_driver_unregister(&mxcipu_driver);
++}
++
++module_exit(ipu_gen_uninit);
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_device.c linux-3.14.72/drivers/mxc/ipu3/ipu_device.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_device.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_device.c 2016-06-19 22:11:55.253143418 +0200
+@@ -0,0 +1,3726 @@
++/*
++ * Copyright 2005-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_device.c
++ *
++ * @brief This file contains the IPUv3 driver device interface and fops functions.
++ *
++ * @ingroup IPU
++ */
++#include <linux/clk.h>
++#include <linux/cpumask.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/sched.h>
++#include <linux/sched/rt.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/time.h>
++#include <linux/types.h>
++#include <linux/vmalloc.h>
++#include <linux/wait.h>
++
++#include <asm/cacheflush.h>
++#include <asm/outercache.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++#include "vdoa.h"
++
++#define CHECK_RETCODE(cont, str, err, label, ret) \
++do { \
++ if (cont) { \
++ dev_err(t->dev, "ERR:[0x%p]-no:0x%x "#str" ret:%d," \
++ "line:%d\n", t, t->task_no, ret, __LINE__);\
++ if (ret != -EACCES) { \
++ t->state = err; \
++ goto label; \
++ } \
++ } \
++} while (0)
++
++#define CHECK_RETCODE_CONT(cont, str, err, ret) \
++do { \
++ if (cont) { \
++ dev_err(t->dev, "ERR:[0x%p]-no:0x%x"#str" ret:%d," \
++ "line:%d\n", t, t->task_no, ret, __LINE__);\
++ if (ret != -EACCES) { \
++ if (t->state == STATE_OK) \
++ t->state = err; \
++ } \
++ } \
++} while (0)
++
++#undef DBG_IPU_PERF
++#ifdef DBG_IPU_PERF
++#define CHECK_PERF(ts) \
++do { \
++ getnstimeofday(ts); \
++} while (0)
++
++#define DECLARE_PERF_VAR \
++ struct timespec ts_queue; \
++ struct timespec ts_dotask; \
++ struct timespec ts_waitirq; \
++ struct timespec ts_sche; \
++ struct timespec ts_rel; \
++ struct timespec ts_frame
++
++#define PRINT_TASK_STATISTICS \
++do { \
++ ts_queue = timespec_sub(tsk->ts_dotask, tsk->ts_queue); \
++ ts_dotask = timespec_sub(tsk->ts_waitirq, tsk->ts_dotask); \
++ ts_waitirq = timespec_sub(tsk->ts_inirq, tsk->ts_waitirq); \
++ ts_sche = timespec_sub(tsk->ts_wakeup, tsk->ts_inirq); \
++ ts_rel = timespec_sub(tsk->ts_rel, tsk->ts_wakeup); \
++ ts_frame = timespec_sub(tsk->ts_rel, tsk->ts_queue); \
++ dev_dbg(tsk->dev, "[0x%p] no-0x%x, ts_q:%ldus, ts_do:%ldus," \
++ "ts_waitirq:%ldus,ts_sche:%ldus, ts_rel:%ldus," \
++ "ts_frame: %ldus\n", tsk, tsk->task_no, \
++ ts_queue.tv_nsec / NSEC_PER_USEC + ts_queue.tv_sec * USEC_PER_SEC,\
++ ts_dotask.tv_nsec / NSEC_PER_USEC + ts_dotask.tv_sec * USEC_PER_SEC,\
++ ts_waitirq.tv_nsec / NSEC_PER_USEC + ts_waitirq.tv_sec * USEC_PER_SEC,\
++ ts_sche.tv_nsec / NSEC_PER_USEC + ts_sche.tv_sec * USEC_PER_SEC,\
++ ts_rel.tv_nsec / NSEC_PER_USEC + ts_rel.tv_sec * USEC_PER_SEC,\
++ ts_frame.tv_nsec / NSEC_PER_USEC + ts_frame.tv_sec * USEC_PER_SEC); \
++ if ((ts_frame.tv_nsec/NSEC_PER_USEC + ts_frame.tv_sec*USEC_PER_SEC) > \
++ 80000) \
++ dev_dbg(tsk->dev, "ts_frame larger than 80ms [0x%p] no-0x%x.\n"\
++ , tsk, tsk->task_no); \
++} while (0)
++#else
++#define CHECK_PERF(ts)
++#define DECLARE_PERF_VAR
++#define PRINT_TASK_STATISTICS
++#endif
++
++#define IPU_PP_CH_VF (IPU_TASK_ID_VF - 1)
++#define IPU_PP_CH_PP (IPU_TASK_ID_PP - 1)
++#define MAX_PP_CH (IPU_TASK_ID_MAX - 1)
++#define VDOA_DEF_TIMEOUT_MS (HZ/2)
++
++/* Strucutures and variables for exporting MXC IPU as device*/
++typedef enum {
++ STATE_OK = 0,
++ STATE_QUEUE,
++ STATE_IN_PROGRESS,
++ STATE_ERR,
++ STATE_TIMEOUT,
++ STATE_RES_TIMEOUT,
++ STATE_NO_IPU,
++ STATE_NO_IRQ,
++ STATE_IPU_BUSY,
++ STATE_IRQ_FAIL,
++ STATE_IRQ_TIMEOUT,
++ STATE_ENABLE_CHAN_FAIL,
++ STATE_DISABLE_CHAN_FAIL,
++ STATE_SEL_BUF_FAIL,
++ STATE_INIT_CHAN_FAIL,
++ STATE_LINK_CHAN_FAIL,
++ STATE_UNLINK_CHAN_FAIL,
++ STATE_INIT_CHAN_BUF_FAIL,
++ STATE_INIT_CHAN_BAND_FAIL,
++ STATE_SYS_NO_MEM,
++ STATE_VDOA_IRQ_TIMEOUT,
++ STATE_VDOA_IRQ_FAIL,
++ STATE_VDOA_TASK_FAIL,
++} ipu_state_t;
++
++enum {
++ INPUT_CHAN_VDI_P = 1,
++ INPUT_CHAN,
++ INPUT_CHAN_VDI_N,
++};
++
++struct ipu_state_msg {
++ int state;
++ char *msg;
++} state_msg[] = {
++ {STATE_OK, "ok"},
++ {STATE_QUEUE, "split queue"},
++ {STATE_IN_PROGRESS, "split in progress"},
++ {STATE_ERR, "error"},
++ {STATE_TIMEOUT, "split task timeout"},
++ {STATE_RES_TIMEOUT, "wait resource timeout"},
++ {STATE_NO_IPU, "no ipu found"},
++ {STATE_NO_IRQ, "no irq found for task"},
++ {STATE_IPU_BUSY, "ipu busy"},
++ {STATE_IRQ_FAIL, "request irq failed"},
++ {STATE_IRQ_TIMEOUT, "wait for irq timeout"},
++ {STATE_ENABLE_CHAN_FAIL, "ipu enable channel fail"},
++ {STATE_DISABLE_CHAN_FAIL, "ipu disable channel fail"},
++ {STATE_SEL_BUF_FAIL, "ipu select buf fail"},
++ {STATE_INIT_CHAN_FAIL, "ipu init channel fail"},
++ {STATE_LINK_CHAN_FAIL, "ipu link channel fail"},
++ {STATE_UNLINK_CHAN_FAIL, "ipu unlink channel fail"},
++ {STATE_INIT_CHAN_BUF_FAIL, "ipu init channel buffer fail"},
++ {STATE_INIT_CHAN_BAND_FAIL, "ipu init channel band mode fail"},
++ {STATE_SYS_NO_MEM, "sys no mem: -ENOMEM"},
++ {STATE_VDOA_IRQ_TIMEOUT, "wait for vdoa irq timeout"},
++ {STATE_VDOA_IRQ_FAIL, "vdoa irq fail"},
++ {STATE_VDOA_TASK_FAIL, "vdoa task fail"},
++};
++
++struct stripe_setting {
++ u32 iw;
++ u32 ih;
++ u32 ow;
++ u32 oh;
++ u32 outh_resize_ratio;
++ u32 outv_resize_ratio;
++ u32 i_left_pos;
++ u32 i_right_pos;
++ u32 i_top_pos;
++ u32 i_bottom_pos;
++ u32 o_left_pos;
++ u32 o_right_pos;
++ u32 o_top_pos;
++ u32 o_bottom_pos;
++ u32 rl_split_line;
++ u32 ud_split_line;
++};
++
++struct task_set {
++#define NULL_MODE 0x0
++#define IC_MODE 0x1
++#define ROT_MODE 0x2
++#define VDI_MODE 0x4
++#define IPU_PREPROCESS_MODE_MASK (IC_MODE | ROT_MODE | VDI_MODE)
++/* VDOA_MODE means this task use vdoa, and VDOA has two modes:
++ * BAND MODE and non-BAND MODE. Non-band mode will do transfer data
++ * to memory. BAND mode needs hareware sync with IPU, it is used default
++ * if connected to VDIC.
++ */
++#define VDOA_MODE 0x8
++#define VDOA_BAND_MODE 0x10
++ u8 mode;
++#define IC_VF 0x1
++#define IC_PP 0x2
++#define ROT_VF 0x4
++#define ROT_PP 0x8
++#define VDI_VF 0x10
++#define VDOA_ONLY 0x20
++ u8 task;
++#define NO_SPLIT 0x0
++#define RL_SPLIT 0x1
++#define UD_SPLIT 0x2
++#define LEFT_STRIPE 0x1
++#define RIGHT_STRIPE 0x2
++#define UP_STRIPE 0x4
++#define DOWN_STRIPE 0x8
++#define SPLIT_MASK 0xF
++ u8 split_mode;
++ u8 band_lines;
++ ipu_channel_t ic_chan;
++ ipu_channel_t rot_chan;
++ ipu_channel_t vdi_ic_p_chan;
++ ipu_channel_t vdi_ic_n_chan;
++
++ u32 i_off;
++ u32 i_uoff;
++ u32 i_voff;
++ u32 istride;
++
++ u32 ov_off;
++ u32 ov_uoff;
++ u32 ov_voff;
++ u32 ovstride;
++
++ u32 ov_alpha_off;
++ u32 ov_alpha_stride;
++
++ u32 o_off;
++ u32 o_uoff;
++ u32 o_voff;
++ u32 ostride;
++
++ u32 r_fmt;
++ u32 r_width;
++ u32 r_height;
++ u32 r_stride;
++ dma_addr_t r_paddr;
++
++ struct stripe_setting sp_setting;
++};
++
++struct ipu_split_task {
++ struct ipu_task task;
++ struct ipu_task_entry *parent_task;
++ struct ipu_task_entry *child_task;
++ u32 task_no;
++};
++
++struct ipu_task_entry {
++ struct ipu_input input;
++ struct ipu_output output;
++
++ bool overlay_en;
++ struct ipu_overlay overlay;
++#define DEF_TIMEOUT_MS 1000
++#define DEF_DELAY_MS 20
++ int timeout;
++ int irq;
++
++ u8 task_id;
++ u8 ipu_id;
++ u8 task_in_list;
++ u8 split_done;
++ struct mutex split_lock;
++ struct mutex vdic_lock;
++ wait_queue_head_t split_waitq;
++
++ struct list_head node;
++ struct list_head split_list;
++ struct ipu_soc *ipu;
++ struct device *dev;
++ struct task_set set;
++ wait_queue_head_t task_waitq;
++ struct completion irq_comp;
++ struct kref refcount;
++ ipu_state_t state;
++ u32 task_no;
++ atomic_t done;
++ atomic_t res_free;
++ atomic_t res_get;
++
++ struct ipu_task_entry *parent;
++ char *vditmpbuf[2];
++ u32 old_save_lines;
++ u32 old_size;
++ bool buf1filled;
++ bool buf0filled;
++
++ vdoa_handle_t vdoa_handle;
++ struct vdoa_output_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ int size;
++ } vdoa_dma;
++
++#ifdef DBG_IPU_PERF
++ struct timespec ts_queue;
++ struct timespec ts_dotask;
++ struct timespec ts_waitirq;
++ struct timespec ts_inirq;
++ struct timespec ts_wakeup;
++ struct timespec ts_rel;
++#endif
++};
++
++struct ipu_channel_tabel {
++ struct mutex lock;
++ u8 used[MXC_IPU_MAX_NUM][MAX_PP_CH];
++ u8 vdoa_used;
++};
++
++struct ipu_thread_data {
++ struct ipu_soc *ipu;
++ u32 id;
++ u32 is_vdoa;
++};
++
++struct ipu_alloc_list {
++ struct list_head list;
++ dma_addr_t phy_addr;
++ void *cpu_addr;
++ u32 size;
++ void *file_index;
++};
++
++static LIST_HEAD(ipu_alloc_list);
++static DEFINE_MUTEX(ipu_alloc_lock);
++static struct ipu_channel_tabel ipu_ch_tbl;
++static LIST_HEAD(ipu_task_list);
++static DEFINE_SPINLOCK(ipu_task_list_lock);
++static DECLARE_WAIT_QUEUE_HEAD(thread_waitq);
++static DECLARE_WAIT_QUEUE_HEAD(res_waitq);
++static atomic_t req_cnt;
++static atomic_t file_index = ATOMIC_INIT(1);
++static int major;
++static int max_ipu_no;
++static int thread_id;
++static atomic_t frame_no;
++static struct class *ipu_class;
++static struct device *ipu_dev;
++static int debug;
++module_param(debug, int, 0600);
++#ifdef DBG_IPU_PERF
++static struct timespec ts_frame_max;
++static u32 ts_frame_avg;
++static atomic_t frame_cnt;
++#endif
++
++static bool deinterlace_3_field(struct ipu_task_entry *t)
++{
++ return ((t->set.mode & VDI_MODE) &&
++ (t->input.deinterlace.motion != HIGH_MOTION));
++}
++
++static u32 tiled_filed_size(struct ipu_task_entry *t)
++{
++ u32 field_size;
++
++ /* note: page_align is required by VPU hw ouput buffer */
++ field_size = TILED_NV12_FRAME_SIZE(t->input.width, t->input.height/2);
++ return field_size;
++}
++
++static bool only_ic(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return ((mode == IC_MODE) || (mode == VDI_MODE));
++}
++
++static bool only_rot(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return (mode == ROT_MODE);
++}
++
++static bool ic_and_rot(u8 mode)
++{
++ mode = mode & IPU_PREPROCESS_MODE_MASK;
++ return ((mode == (IC_MODE | ROT_MODE)) ||
++ (mode == (VDI_MODE | ROT_MODE)));
++}
++
++static bool need_split(struct ipu_task_entry *t)
++{
++ return ((t->set.split_mode != NO_SPLIT) || (t->task_no & SPLIT_MASK));
++}
++
++unsigned int fmt_to_bpp(unsigned int pixelformat)
++{
++ u32 bpp;
++
++ switch (pixelformat) {
++ case IPU_PIX_FMT_RGB565:
++ /*interleaved 422*/
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_UYVY:
++ /*non-interleaved 422*/
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ bpp = 16;
++ break;
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_YUV444P:
++ bpp = 24;
++ break;
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_ABGR32:
++ bpp = 32;
++ break;
++ /*non-interleaved 420*/
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_NV12:
++ bpp = 12;
++ break;
++ default:
++ bpp = 8;
++ break;
++ }
++ return bpp;
++}
++EXPORT_SYMBOL_GPL(fmt_to_bpp);
++
++cs_t colorspaceofpixel(int fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_RGB666:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_ABGR32:
++ return RGB_CS;
++ break;
++ case IPU_PIX_FMT_UYVY:
++ case IPU_PIX_FMT_YUYV:
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_YUV444P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_TILED_NV12:
++ case IPU_PIX_FMT_TILED_NV12F:
++ return YUV_CS;
++ break;
++ default:
++ return NULL_CS;
++ }
++}
++EXPORT_SYMBOL_GPL(colorspaceofpixel);
++
++int need_csc(int ifmt, int ofmt)
++{
++ cs_t ics, ocs;
++
++ ics = colorspaceofpixel(ifmt);
++ ocs = colorspaceofpixel(ofmt);
++
++ if ((ics == NULL_CS) || (ocs == NULL_CS))
++ return -1;
++ else if (ics != ocs)
++ return 1;
++
++ return 0;
++}
++EXPORT_SYMBOL_GPL(need_csc);
++
++static int soc_max_in_width(u32 is_vdoa)
++{
++ return is_vdoa ? 8192 : 4096;
++}
++
++static int soc_max_vdi_in_width(void)
++{
++ return IPU_MAX_VDI_IN_WIDTH;
++}
++static int soc_max_in_height(void)
++{
++ return 4096;
++}
++
++static int soc_max_out_width(void)
++{
++ /* mx51/mx53/mx6q is 1024*/
++ return 1024;
++}
++
++static int soc_max_out_height(void)
++{
++ /* mx51/mx53/mx6q is 1024*/
++ return 1024;
++}
++
++static void dump_task_info(struct ipu_task_entry *t)
++{
++ if (!debug)
++ return;
++ dev_dbg(t->dev, "[0x%p]input:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->input.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->input.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->input.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->input.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->input.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->input.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->input.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]input buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->input.paddr);
++ dev_dbg(t->dev, "[0x%p]\ti_off = 0x%x\n", (void *)t, t->set.i_off);
++ dev_dbg(t->dev, "[0x%p]\ti_uoff = 0x%x\n", (void *)t, t->set.i_uoff);
++ dev_dbg(t->dev, "[0x%p]\ti_voff = 0x%x\n", (void *)t, t->set.i_voff);
++ dev_dbg(t->dev, "[0x%p]\tistride = %d\n", (void *)t, t->set.istride);
++ if (t->input.deinterlace.enable) {
++ dev_dbg(t->dev, "[0x%p]deinterlace enabled with:\n", (void *)t);
++ if (t->input.deinterlace.motion != HIGH_MOTION) {
++ dev_dbg(t->dev, "[0x%p]\tlow/medium motion\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr_n = 0x%x\n",
++ (void *)t, t->input.paddr_n);
++ } else
++ dev_dbg(t->dev, "[0x%p]\thigh motion\n", (void *)t);
++ }
++
++ dev_dbg(t->dev, "[0x%p]output:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->output.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->output.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->output.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n", (void *)t, t->output.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n", (void *)t, t->output.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->output.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->output.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]\trotate = %d\n", (void *)t, t->output.rotate);
++ dev_dbg(t->dev, "[0x%p]output buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->output.paddr);
++ dev_dbg(t->dev, "[0x%p]\to_off = 0x%x\n", (void *)t, t->set.o_off);
++ dev_dbg(t->dev, "[0x%p]\to_uoff = 0x%x\n", (void *)t, t->set.o_uoff);
++ dev_dbg(t->dev, "[0x%p]\to_voff = 0x%x\n", (void *)t, t->set.o_voff);
++ dev_dbg(t->dev, "[0x%p]\tostride = %d\n", (void *)t, t->set.ostride);
++
++ if (t->overlay_en) {
++ dev_dbg(t->dev, "[0x%p]overlay:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n",
++ (void *)t, t->overlay.format);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n",
++ (void *)t, t->overlay.width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n",
++ (void *)t, t->overlay.height);
++ dev_dbg(t->dev, "[0x%p]\tcrop.w = %d\n",
++ (void *)t, t->overlay.crop.w);
++ dev_dbg(t->dev, "[0x%p]\tcrop.h = %d\n",
++ (void *)t, t->overlay.crop.h);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.x = %d\n",
++ (void *)t, t->overlay.crop.pos.x);
++ dev_dbg(t->dev, "[0x%p]\tcrop.pos.y = %d\n",
++ (void *)t, t->overlay.crop.pos.y);
++ dev_dbg(t->dev, "[0x%p]overlay buffer:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
++ (void *)t, t->overlay.paddr);
++ dev_dbg(t->dev, "[0x%p]\tov_off = 0x%x\n",
++ (void *)t, t->set.ov_off);
++ dev_dbg(t->dev, "[0x%p]\tov_uoff = 0x%x\n",
++ (void *)t, t->set.ov_uoff);
++ dev_dbg(t->dev, "[0x%p]\tov_voff = 0x%x\n",
++ (void *)t, t->set.ov_voff);
++ dev_dbg(t->dev, "[0x%p]\tovstride = %d\n",
++ (void *)t, t->set.ovstride);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ dev_dbg(t->dev, "[0x%p]local alpha enabled with:\n",
++ (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n",
++ (void *)t, t->overlay.alpha.loc_alp_paddr);
++ dev_dbg(t->dev, "[0x%p]\tov_alpha_off = 0x%x\n",
++ (void *)t, t->set.ov_alpha_off);
++ dev_dbg(t->dev, "[0x%p]\tov_alpha_stride = %d\n",
++ (void *)t, t->set.ov_alpha_stride);
++ } else
++ dev_dbg(t->dev, "[0x%p]globle alpha enabled with value 0x%x\n",
++ (void *)t, t->overlay.alpha.gvalue);
++ if (t->overlay.colorkey.enable)
++ dev_dbg(t->dev, "[0x%p]colorkey enabled with value 0x%x\n",
++ (void *)t, t->overlay.colorkey.value);
++ }
++
++ dev_dbg(t->dev, "[0x%p]want task_id = %d\n", (void *)t, t->task_id);
++ dev_dbg(t->dev, "[0x%p]want task mode is 0x%x\n",
++ (void *)t, t->set.mode);
++ dev_dbg(t->dev, "[0x%p]\tIC_MODE = 0x%x\n", (void *)t, IC_MODE);
++ dev_dbg(t->dev, "[0x%p]\tROT_MODE = 0x%x\n", (void *)t, ROT_MODE);
++ dev_dbg(t->dev, "[0x%p]\tVDI_MODE = 0x%x\n", (void *)t, VDI_MODE);
++ dev_dbg(t->dev, "[0x%p]\tTask_no = 0x%x\n\n\n", (void *)t, t->task_no);
++}
++
++static void dump_check_err(struct device *dev, int err)
++{
++ switch (err) {
++ case IPU_CHECK_ERR_INPUT_CROP:
++ dev_err(dev, "input crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_OUTPUT_CROP:
++ dev_err(dev, "output crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_OVERLAY_CROP:
++ dev_err(dev, "overlay crop setting error\n");
++ break;
++ case IPU_CHECK_ERR_INPUT_OVER_LIMIT:
++ dev_err(dev, "input over limitation\n");
++ break;
++ case IPU_CHECK_ERR_OVERLAY_WITH_VDI:
++ dev_err(dev, "do not support overlay with deinterlace\n");
++ break;
++ case IPU_CHECK_ERR_OV_OUT_NO_FIT:
++ dev_err(dev,
++ "width/height of overlay and ic output should be same\n");
++ break;
++ case IPU_CHECK_ERR_PROC_NO_NEED:
++ dev_err(dev, "no ipu processing need\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_INPUTW_OVER:
++ dev_err(dev, "split mode input width overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_INPUTH_OVER:
++ dev_err(dev, "split mode input height overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER:
++ dev_err(dev, "split mode output width overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER:
++ dev_err(dev, "split mode output height overflow\n");
++ break;
++ case IPU_CHECK_ERR_SPLIT_WITH_ROT:
++ dev_err(dev, "not support split mode with rotation\n");
++ break;
++ case IPU_CHECK_ERR_W_DOWNSIZE_OVER:
++ dev_err(dev, "horizontal downsizing ratio overflow\n");
++ break;
++ case IPU_CHECK_ERR_H_DOWNSIZE_OVER:
++ dev_err(dev, "vertical downsizing ratio overflow\n");
++ break;
++ default:
++ break;
++ }
++}
++
++static void dump_check_warn(struct device *dev, int warn)
++{
++ if (warn & IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN)
++ dev_warn(dev, "input u/v offset not 8 align\n");
++ if (warn & IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN)
++ dev_warn(dev, "output u/v offset not 8 align\n");
++ if (warn & IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN)
++ dev_warn(dev, "overlay u/v offset not 8 align\n");
++}
++
++static int set_crop(struct ipu_crop *crop, int width, int height, int fmt)
++{
++ if ((width == 0) || (height == 0)) {
++ pr_err("Invalid param: width=%d, height=%d\n", width, height);
++ return -EINVAL;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == fmt) ||
++ (IPU_PIX_FMT_TILED_NV12F == fmt)) {
++ if (crop->w || crop->h) {
++ if (((crop->w + crop->pos.x) > width)
++ || ((crop->h + crop->pos.y) > height)
++ || (0 != (crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->pos.x % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->pos.y % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ ) {
++ pr_err("set_crop error MB align.\n");
++ return -EINVAL;
++ }
++ } else {
++ crop->pos.x = 0;
++ crop->pos.y = 0;
++ crop->w = width;
++ crop->h = height;
++ if ((0 != (crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN))
++ || (0 != (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN))) {
++ pr_err("set_crop error w/h MB align.\n");
++ return -EINVAL;
++ }
++ }
++ } else {
++ if (crop->w || crop->h) {
++ if (((crop->w + crop->pos.x) > (width + 16))
++ || ((crop->h + crop->pos.y) > height + 16)) {
++ pr_err("set_crop error exceeds width/height.\n");
++ return -EINVAL;
++ }
++ } else {
++ crop->pos.x = 0;
++ crop->pos.y = 0;
++ crop->w = width;
++ crop->h = height;
++ }
++ crop->w -= crop->w%8;
++ crop->h -= crop->h%8;
++ }
++
++ if ((crop->w == 0) || (crop->h == 0)) {
++ pr_err("Invalid crop param: crop.w=%d, crop.h=%d\n",
++ crop->w, crop->h);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static void update_offset(unsigned int fmt,
++ unsigned int width, unsigned int height,
++ unsigned int pos_x, unsigned int pos_y,
++ int *off, int *uoff, int *voff, int *stride)
++{
++ /* NOTE: u v offset should based on start point of off*/
++ switch (fmt) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + (width/2) * (pos_y/2) + pos_x/2;
++ /* In case height is odd, round up to even */
++ *voff = *uoff + (width/2) * ((height+1)/2);
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ *off = pos_y * width + pos_x;
++ *voff = (width * (height - pos_y) - pos_x)
++ + (width/2) * (pos_y/2) + pos_x/2;
++ /* In case height is odd, round up to even */
++ *uoff = *voff + (width/2) * ((height+1)/2);
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ *off = pos_y * width + pos_x;
++ *voff = (width * (height - pos_y) - pos_x)
++ + (width/2) * pos_y + pos_x/2;
++ *uoff = *voff + (width/2) * height;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + (width/2) * pos_y + pos_x/2;
++ *voff = *uoff + (width/2) * height;
++ break;
++ case IPU_PIX_FMT_YUV444P:
++ *off = pos_y * width + pos_x;
++ *uoff = width * height;
++ *voff = width * height * 2;
++ break;
++ case IPU_PIX_FMT_NV12:
++ *off = pos_y * width + pos_x;
++ *uoff = (width * (height - pos_y) - pos_x)
++ + width * (pos_y/2) + pos_x;
++ break;
++ case IPU_PIX_FMT_TILED_NV12:
++ /*
++ * tiled format, progressive:
++ * assuming that line is aligned with MB height (aligned to 16)
++ * offset = line * stride + (pixel / MB_width) * pixels_in_MB
++ * = line * stride + (pixel / 16) * 256
++ * = line * stride + pixel * 16
++ */
++ *off = pos_y * width + (pos_x << 4);
++ *uoff = ALIGN(width * height, SZ_4K) + (*off >> 1) - *off;
++ break;
++ case IPU_PIX_FMT_TILED_NV12F:
++ /*
++ * tiled format, interlaced:
++ * same as above, only number of pixels in MB is 128,
++ * instead of 256
++ */
++ *off = (pos_y >> 1) * width + (pos_x << 3);
++ *uoff = ALIGN(width * height/2, SZ_4K) + (*off >> 1) - *off;
++ break;
++ default:
++ *off = (pos_y * width + pos_x) * fmt_to_bpp(fmt)/8;
++ break;
++ }
++ *stride = width * bytes_per_pixel(fmt);
++ *off &= ~0x7;
++}
++
++static int update_split_setting(struct ipu_task_entry *t, bool vdi_split)
++{
++ struct stripe_param left_stripe;
++ struct stripe_param right_stripe;
++ struct stripe_param up_stripe;
++ struct stripe_param down_stripe;
++ u32 iw, ih, ow, oh;
++ u32 max_width;
++ int ret;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
++ return IPU_CHECK_ERR_SPLIT_WITH_ROT;
++
++ iw = t->input.crop.w;
++ ih = t->input.crop.h;
++
++ ow = t->output.crop.w;
++ oh = t->output.crop.h;
++
++ memset(&left_stripe, 0, sizeof(left_stripe));
++ memset(&right_stripe, 0, sizeof(right_stripe));
++ memset(&up_stripe, 0, sizeof(up_stripe));
++ memset(&down_stripe, 0, sizeof(down_stripe));
++
++ if (t->set.split_mode & RL_SPLIT) {
++ /*
++ * We do want equal strips: initialize stripes in case
++ * calc_stripes returns before actually doing the calculation
++ */
++ left_stripe.input_width = iw / 2;
++ left_stripe.output_width = ow / 2;
++ right_stripe.input_column = iw / 2;
++ right_stripe.output_column = ow / 2;
++
++ if (vdi_split)
++ max_width = soc_max_vdi_in_width();
++ else
++ max_width = soc_max_out_width();
++ ret = ipu_calc_stripes_sizes(iw,
++ ow,
++ max_width,
++ (((unsigned long long)1) << 32), /* 32bit for fractional*/
++ 1, /* equal stripes */
++ t->input.format,
++ t->output.format,
++ &left_stripe,
++ &right_stripe);
++ if (ret < 0)
++ return IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++ else if (ret)
++ dev_dbg(t->dev, "Warn: no:0x%x,calc_stripes ret:%d\n",
++ t->task_no, ret);
++ t->set.sp_setting.iw = left_stripe.input_width;
++ t->set.sp_setting.ow = left_stripe.output_width;
++ t->set.sp_setting.outh_resize_ratio = left_stripe.irr;
++ t->set.sp_setting.i_left_pos = left_stripe.input_column;
++ t->set.sp_setting.o_left_pos = left_stripe.output_column;
++ t->set.sp_setting.i_right_pos = right_stripe.input_column;
++ t->set.sp_setting.o_right_pos = right_stripe.output_column;
++ } else {
++ t->set.sp_setting.iw = iw;
++ t->set.sp_setting.ow = ow;
++ t->set.sp_setting.outh_resize_ratio = 0;
++ t->set.sp_setting.i_left_pos = 0;
++ t->set.sp_setting.o_left_pos = 0;
++ t->set.sp_setting.i_right_pos = 0;
++ t->set.sp_setting.o_right_pos = 0;
++ }
++ if ((t->set.sp_setting.iw + t->set.sp_setting.i_right_pos) > (iw+16))
++ return IPU_CHECK_ERR_SPLIT_INPUTW_OVER;
++ if (((t->set.sp_setting.ow + t->set.sp_setting.o_right_pos) > ow)
++ || (t->set.sp_setting.ow > soc_max_out_width()))
++ return IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER;
++ if (rounddown(t->set.sp_setting.ow, 8) * 8 <=
++ rounddown(t->set.sp_setting.iw, 8))
++ return IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++
++ if (t->set.split_mode & UD_SPLIT) {
++ /*
++ * We do want equal strips: initialize stripes in case
++ * calc_stripes returns before actually doing the calculation
++ */
++ up_stripe.input_width = ih / 2;
++ up_stripe.output_width = oh / 2;
++ down_stripe.input_column = ih / 2;
++ down_stripe.output_column = oh / 2;
++ ret = ipu_calc_stripes_sizes(ih,
++ oh,
++ soc_max_out_height(),
++ (((unsigned long long)1) << 32), /* 32bit for fractional*/
++ 0x1 | 0x2, /* equal stripes and vertical */
++ t->input.format,
++ t->output.format,
++ &up_stripe,
++ &down_stripe);
++ if (ret < 0)
++ return IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++ else if (ret)
++ dev_err(t->dev, "Warn: no:0x%x,calc_stripes ret:%d\n",
++ t->task_no, ret);
++ t->set.sp_setting.ih = up_stripe.input_width;
++ t->set.sp_setting.oh = up_stripe.output_width;
++ t->set.sp_setting.outv_resize_ratio = up_stripe.irr;
++ t->set.sp_setting.i_top_pos = up_stripe.input_column;
++ t->set.sp_setting.o_top_pos = up_stripe.output_column;
++ t->set.sp_setting.i_bottom_pos = down_stripe.input_column;
++ t->set.sp_setting.o_bottom_pos = down_stripe.output_column;
++ } else {
++ t->set.sp_setting.ih = ih;
++ t->set.sp_setting.oh = oh;
++ t->set.sp_setting.outv_resize_ratio = 0;
++ t->set.sp_setting.i_top_pos = 0;
++ t->set.sp_setting.o_top_pos = 0;
++ t->set.sp_setting.i_bottom_pos = 0;
++ t->set.sp_setting.o_bottom_pos = 0;
++ }
++
++ /* downscale case: enforce limits */
++ if (((t->set.sp_setting.ih + t->set.sp_setting.i_bottom_pos) > (ih))
++ && (t->set.sp_setting.ih >= t->set.sp_setting.oh))
++ return IPU_CHECK_ERR_SPLIT_INPUTH_OVER;
++ /* upscale case: relax limits because ipu_calc_stripes_sizes() may
++ create input stripe that falls just outside of the input window */
++ else if ((t->set.sp_setting.ih + t->set.sp_setting.i_bottom_pos)
++ > (ih+16))
++ return IPU_CHECK_ERR_SPLIT_INPUTH_OVER;
++ if (((t->set.sp_setting.oh + t->set.sp_setting.o_bottom_pos) > oh)
++ || (t->set.sp_setting.oh > soc_max_out_height()))
++ return IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER;
++ if (rounddown(t->set.sp_setting.oh, 8) * 8 <=
++ rounddown(t->set.sp_setting.ih, 8))
++ return IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++
++ return IPU_CHECK_OK;
++}
++
++static int check_task(struct ipu_task_entry *t)
++{
++ int tmp;
++ int ret = IPU_CHECK_OK;
++ int timeout;
++ bool vdi_split = false;
++ int ocw, och;
++
++ if ((IPU_PIX_FMT_TILED_NV12 == t->overlay.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->overlay.format) ||
++ (IPU_PIX_FMT_TILED_NV12 == t->output.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->output.format) ||
++ ((IPU_PIX_FMT_TILED_NV12F == t->input.format) &&
++ !t->input.deinterlace.enable)) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++
++ /* check input */
++ ret = set_crop(&t->input.crop, t->input.width, t->input.height,
++ t->input.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_INPUT_CROP;
++ goto done;
++ } else
++ update_offset(t->input.format, t->input.width, t->input.height,
++ t->input.crop.pos.x, t->input.crop.pos.y,
++ &t->set.i_off, &t->set.i_uoff,
++ &t->set.i_voff, &t->set.istride);
++
++ /* check output */
++ ret = set_crop(&t->output.crop, t->output.width, t->output.height,
++ t->output.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_OUTPUT_CROP;
++ goto done;
++ } else
++ update_offset(t->output.format,
++ t->output.width, t->output.height,
++ t->output.crop.pos.x, t->output.crop.pos.y,
++ &t->set.o_off, &t->set.o_uoff,
++ &t->set.o_voff, &t->set.ostride);
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*
++ * Cache output width and height and
++ * swap them so that we may check
++ * downsize overflow correctly.
++ */
++ ocw = t->output.crop.h;
++ och = t->output.crop.w;
++ } else {
++ ocw = t->output.crop.w;
++ och = t->output.crop.h;
++ }
++
++ if (ocw * 8 <= t->input.crop.w) {
++ ret = IPU_CHECK_ERR_W_DOWNSIZE_OVER;
++ goto done;
++ }
++
++ if (och * 8 <= t->input.crop.h) {
++ ret = IPU_CHECK_ERR_H_DOWNSIZE_OVER;
++ goto done;
++ }
++
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ if ((t->input.crop.w > soc_max_in_width(1)) ||
++ (t->input.crop.h > soc_max_in_height())) {
++ ret = IPU_CHECK_ERR_INPUT_OVER_LIMIT;
++ goto done;
++ }
++ /* output fmt: NV12 and YUYV, now don't support resize */
++ if (((IPU_PIX_FMT_NV12 != t->output.format) &&
++ (IPU_PIX_FMT_YUYV != t->output.format)) ||
++ (t->input.crop.w != t->output.crop.w) ||
++ (t->input.crop.h != t->output.crop.h)) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++ }
++
++ /* check overlay if there is */
++ if (t->overlay_en) {
++ if (t->input.deinterlace.enable) {
++ ret = IPU_CHECK_ERR_OVERLAY_WITH_VDI;
++ goto done;
++ }
++
++ ret = set_crop(&t->overlay.crop, t->overlay.width,
++ t->overlay.height, t->overlay.format);
++ if (ret < 0) {
++ ret = IPU_CHECK_ERR_OVERLAY_CROP;
++ goto done;
++ } else {
++ ocw = t->output.crop.w;
++ och = t->output.crop.h;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ ocw = t->output.crop.h;
++ och = t->output.crop.w;
++ }
++ if ((t->overlay.crop.w != ocw) ||
++ (t->overlay.crop.h != och)) {
++ ret = IPU_CHECK_ERR_OV_OUT_NO_FIT;
++ goto done;
++ }
++
++ update_offset(t->overlay.format,
++ t->overlay.width, t->overlay.height,
++ t->overlay.crop.pos.x, t->overlay.crop.pos.y,
++ &t->set.ov_off, &t->set.ov_uoff,
++ &t->set.ov_voff, &t->set.ovstride);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ t->set.ov_alpha_stride = t->overlay.width;
++ t->set.ov_alpha_off = t->overlay.crop.pos.y *
++ t->overlay.width + t->overlay.crop.pos.x;
++ }
++ }
++ }
++
++ /* input overflow? */
++ if (!((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format))) {
++ if ((t->input.crop.w > soc_max_in_width(0)) ||
++ (t->input.crop.h > soc_max_in_height())) {
++ ret = IPU_CHECK_ERR_INPUT_OVER_LIMIT;
++ goto done;
++ }
++ }
++
++ /* check task mode */
++ t->set.mode = NULL_MODE;
++ t->set.split_mode = NO_SPLIT;
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*output swap*/
++ tmp = t->output.crop.w;
++ t->output.crop.w = t->output.crop.h;
++ t->output.crop.h = tmp;
++ }
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT)
++ t->set.mode |= ROT_MODE;
++
++ /*need resize or CSC?*/
++ if ((t->input.crop.w != t->output.crop.w) ||
++ (t->input.crop.h != t->output.crop.h) ||
++ need_csc(t->input.format, t->output.format))
++ t->set.mode |= IC_MODE;
++
++ /*need cropping?*/
++ if ((t->input.crop.w != t->input.width) ||
++ (t->input.crop.h != t->input.height) ||
++ (t->output.crop.w != t->output.width) ||
++ (t->output.crop.h != t->output.height))
++ t->set.mode |= IC_MODE;
++
++ /*need flip?*/
++ if ((t->set.mode == NULL_MODE) && (t->output.rotate > IPU_ROTATE_NONE))
++ t->set.mode |= IC_MODE;
++
++ /*need IDMAC do format(same color space)?*/
++ if ((t->set.mode == NULL_MODE) && (t->input.format != t->output.format))
++ t->set.mode |= IC_MODE;
++
++ /*overlay support*/
++ if (t->overlay_en)
++ t->set.mode |= IC_MODE;
++
++ /*deinterlace*/
++ if (t->input.deinterlace.enable) {
++ t->set.mode &= ~IC_MODE;
++ t->set.mode |= VDI_MODE;
++ }
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ if (t->set.mode & ROT_MODE) {
++ ret = IPU_CHECK_ERR_NOT_SUPPORT;
++ goto done;
++ }
++ t->set.mode |= VDOA_MODE;
++ if (IPU_PIX_FMT_TILED_NV12F == t->input.format)
++ t->set.mode |= VDOA_BAND_MODE;
++ t->set.mode &= ~IC_MODE;
++ }
++
++ if ((t->set.mode & (IC_MODE | VDI_MODE)) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ if (t->output.crop.w > soc_max_out_width())
++ t->set.split_mode |= RL_SPLIT;
++ if (t->output.crop.h > soc_max_out_height())
++ t->set.split_mode |= UD_SPLIT;
++ if (!t->set.split_mode && (t->set.mode & VDI_MODE) &&
++ (t->input.crop.w > soc_max_vdi_in_width())) {
++ t->set.split_mode |= RL_SPLIT;
++ vdi_split = true;
++ }
++ if (t->set.split_mode) {
++ if ((t->set.split_mode == RL_SPLIT) ||
++ (t->set.split_mode == UD_SPLIT))
++ timeout = DEF_TIMEOUT_MS * 2 + DEF_DELAY_MS;
++ else
++ timeout = DEF_TIMEOUT_MS * 4 + DEF_DELAY_MS;
++ if (t->timeout < timeout)
++ t->timeout = timeout;
++
++ ret = update_split_setting(t, vdi_split);
++ if (ret > IPU_CHECK_ERR_MIN)
++ goto done;
++ }
++ }
++
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ /*output swap*/
++ tmp = t->output.crop.w;
++ t->output.crop.w = t->output.crop.h;
++ t->output.crop.h = tmp;
++ }
++
++ if (t->set.mode == NULL_MODE) {
++ ret = IPU_CHECK_ERR_PROC_NO_NEED;
++ goto done;
++ }
++
++ if ((t->set.i_uoff % 8) || (t->set.i_voff % 8))
++ ret |= IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN;
++ if ((t->set.o_uoff % 8) || (t->set.o_voff % 8))
++ ret |= IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN;
++ if (t->overlay_en && ((t->set.ov_uoff % 8) || (t->set.ov_voff % 8)))
++ ret |= IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN;
++
++done:
++ /* dump msg */
++ if (debug) {
++ if (ret > IPU_CHECK_ERR_MIN)
++ dump_check_err(t->dev, ret);
++ else if (ret != IPU_CHECK_OK)
++ dump_check_warn(t->dev, ret);
++ }
++
++ return ret;
++}
++
++static int prepare_task(struct ipu_task_entry *t)
++{
++ int ret = 0;
++
++ ret = check_task(t);
++ if (ret > IPU_CHECK_ERR_MIN)
++ return -EINVAL;
++
++ if (t->set.mode & VDI_MODE) {
++ t->task_id = IPU_TASK_ID_VF;
++ t->set.task = VDI_VF;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_VF;
++ }
++
++ if (VDOA_MODE == t->set.mode) {
++ if (t->set.task != 0) {
++ dev_err(t->dev, "ERR: vdoa only task:0x%x, [0x%p].\n",
++ t->set.task, t);
++ return -EINVAL;
++ }
++ t->set.task |= VDOA_ONLY;
++ }
++
++ if (VDOA_BAND_MODE & t->set.mode) {
++ /* to save band size: 1<<3 = 8 lines */
++ t->set.band_lines = 3;
++ }
++
++ dump_task_info(t);
++
++ return ret;
++}
++
++static uint32_t ic_vf_pp_is_busy(struct ipu_soc *ipu, bool is_vf)
++{
++ uint32_t status;
++ uint32_t status_vf;
++ uint32_t status_rot;
++
++ if (is_vf) {
++ status = ipu_channel_status(ipu, MEM_VDI_PRP_VF_MEM);
++ status_vf = ipu_channel_status(ipu, MEM_PRP_VF_MEM);
++ status_rot = ipu_channel_status(ipu, MEM_ROT_VF_MEM);
++ return status || status_vf || status_rot;
++ } else {
++ status = ipu_channel_status(ipu, MEM_PP_MEM);
++ status_rot = ipu_channel_status(ipu, MEM_ROT_PP_MEM);
++ return status || status_rot;
++ }
++}
++
++static int _get_vdoa_ipu_res(struct ipu_task_entry *t)
++{
++ int i;
++ struct ipu_soc *ipu;
++ u8 *used;
++ uint32_t found_ipu = 0;
++ uint32_t found_vdoa = 0;
++ struct ipu_channel_tabel *tbl = &ipu_ch_tbl;
++
++ mutex_lock(&tbl->lock);
++ if (t->set.mode & VDOA_MODE) {
++ if (NULL != t->vdoa_handle)
++ found_vdoa = 1;
++ else {
++ found_vdoa = tbl->vdoa_used ? 0 : 1;
++ if (found_vdoa) {
++ tbl->vdoa_used = 1;
++ vdoa_get_handle(&t->vdoa_handle);
++ } else
++ /* first get vdoa->ipu resource sequence */
++ goto out;
++ if (t->set.task & VDOA_ONLY)
++ goto out;
++ }
++ }
++
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu = ipu_get_soc(i);
++ if (IS_ERR(ipu))
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
++ t->task_no, found_vdoa, i);
++
++ used = &tbl->used[i][IPU_PP_CH_VF];
++ if (t->set.mode & VDI_MODE) {
++ if (0 == *used) {
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ } else if ((t->set.mode & IC_MODE) || only_rot(t->set.mode)) {
++ if (0 == *used) {
++ t->task_id = IPU_TASK_ID_VF;
++ if (t->set.mode & IC_MODE)
++ t->set.task |= IC_VF;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_VF;
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ } else
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, mode:0x%x\n",
++ t->task_no, found_vdoa, t->set.mode);
++ }
++ if (found_ipu)
++ goto next;
++
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu = ipu_get_soc(i);
++ if (IS_ERR(ipu))
++ dev_err(t->dev, "no:0x%x,found_vdoa:%d, ipu:%d\n",
++ t->task_no, found_vdoa, i);
++
++ if ((t->set.mode & IC_MODE) || only_rot(t->set.mode)) {
++ used = &tbl->used[i][IPU_PP_CH_PP];
++ if (0 == *used) {
++ t->task_id = IPU_TASK_ID_PP;
++ if (t->set.mode & IC_MODE)
++ t->set.task |= IC_PP;
++ if (t->set.mode & ROT_MODE)
++ t->set.task |= ROT_PP;
++ *used = 1;
++ found_ipu = 1;
++ break;
++ }
++ }
++ }
++
++next:
++ if (found_ipu) {
++ t->ipu = ipu;
++ t->ipu_id = i;
++ t->dev = ipu->dev;
++ if (atomic_inc_return(&t->res_get) == 2)
++ dev_err(t->dev,
++ "ERR no:0x%x,found_vdoa:%d,get ipu twice\n",
++ t->task_no, found_vdoa);
++ }
++out:
++ dev_dbg(t->dev,
++ "%s:no:0x%x,found_vdoa:%d, found_ipu:%d\n",
++ __func__, t->task_no, found_vdoa, found_ipu);
++ mutex_unlock(&tbl->lock);
++ if (t->set.task & VDOA_ONLY)
++ return found_vdoa;
++ else if (t->set.mode & VDOA_MODE)
++ return found_vdoa && found_ipu;
++ else
++ return found_ipu;
++}
++
++static void put_vdoa_ipu_res(struct ipu_task_entry *tsk, int vdoa_only)
++{
++ int ret;
++ int rel_vdoa = 0, rel_ipu = 0;
++ struct ipu_channel_tabel *tbl = &ipu_ch_tbl;
++
++ mutex_lock(&tbl->lock);
++ if (tsk->set.mode & VDOA_MODE) {
++ if (!tbl->vdoa_used && tsk->vdoa_handle)
++ dev_err(tsk->dev,
++ "ERR no:0x%x,vdoa not used,mode:0x%x\n",
++ tsk->task_no, tsk->set.mode);
++ if (tbl->vdoa_used && tsk->vdoa_handle) {
++ tbl->vdoa_used = 0;
++ vdoa_put_handle(&tsk->vdoa_handle);
++ if (tsk->ipu)
++ tsk->ipu->vdoa_en = 0;
++ rel_vdoa = 1;
++ if (vdoa_only || (tsk->set.task & VDOA_ONLY))
++ goto out;
++ }
++ }
++
++ tbl->used[tsk->ipu_id][tsk->task_id - 1] = 0;
++ rel_ipu = 1;
++ ret = atomic_inc_return(&tsk->res_free);
++ if (ret == 2)
++ dev_err(tsk->dev,
++ "ERR no:0x%x,rel_vdoa:%d,put ipu twice\n",
++ tsk->task_no, rel_vdoa);
++out:
++ dev_dbg(tsk->dev,
++ "%s:no:0x%x,rel_vdoa:%d, rel_ipu:%d\n",
++ __func__, tsk->task_no, rel_vdoa, rel_ipu);
++ mutex_unlock(&tbl->lock);
++}
++
++static int get_vdoa_ipu_res(struct ipu_task_entry *t)
++{
++ int ret;
++ uint32_t found = 0;
++
++ found = _get_vdoa_ipu_res(t);
++ if (!found) {
++ t->ipu_id = -1;
++ t->ipu = NULL;
++ /* blocking to get resource */
++ ret = atomic_inc_return(&req_cnt);
++ dev_dbg(t->dev,
++ "wait_res:no:0x%x,req_cnt:%d\n", t->task_no, ret);
++ ret = wait_event_timeout(res_waitq, _get_vdoa_ipu_res(t),
++ msecs_to_jiffies(t->timeout - DEF_DELAY_MS));
++ if (ret == 0) {
++ dev_err(t->dev, "ERR[0x%p,no-0x%x] wait_res timeout:%dms!\n",
++ t, t->task_no, t->timeout - DEF_DELAY_MS);
++ ret = -ETIMEDOUT;
++ t->state = STATE_RES_TIMEOUT;
++ goto out;
++ } else {
++ if (!(t->set.task & VDOA_ONLY) && (!t->ipu))
++ dev_err(t->dev,
++ "ERR[no-0x%x] can not get ipu!\n",
++ t->task_no);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0)
++ ret = atomic_dec_return(&req_cnt);
++ else
++ dev_err(t->dev,
++ "ERR[no-0x%x] req_cnt:%d mismatch!\n",
++ t->task_no, ret);
++ dev_dbg(t->dev, "no-0x%x,[0x%p],req_cnt:%d, got_res!\n",
++ t->task_no, t, ret);
++ found = 1;
++ }
++ }
++
++out:
++ return found;
++}
++
++static struct ipu_task_entry *create_task_entry(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++
++ tsk = kzalloc(sizeof(struct ipu_task_entry), GFP_KERNEL);
++ if (!tsk)
++ return ERR_PTR(-ENOMEM);
++ kref_init(&tsk->refcount);
++ tsk->state = -EINVAL;
++ tsk->ipu_id = -1;
++ tsk->dev = ipu_dev;
++ tsk->input = task->input;
++ tsk->output = task->output;
++ tsk->overlay_en = task->overlay_en;
++ if (tsk->overlay_en)
++ tsk->overlay = task->overlay;
++ if (task->timeout > DEF_TIMEOUT_MS)
++ tsk->timeout = task->timeout;
++ else
++ tsk->timeout = DEF_TIMEOUT_MS;
++
++ return tsk;
++}
++
++static void task_mem_free(struct kref *ref)
++{
++ struct ipu_task_entry *tsk =
++ container_of(ref, struct ipu_task_entry, refcount);
++ kfree(tsk);
++}
++
++int create_split_child_task(struct ipu_split_task *sp_task)
++{
++ int ret = 0;
++ struct ipu_task_entry *tsk;
++
++ tsk = create_task_entry(&sp_task->task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ sp_task->child_task = tsk;
++ tsk->task_no = sp_task->task_no;
++
++ ret = prepare_task(tsk);
++ if (ret < 0)
++ goto err;
++
++ tsk->parent = sp_task->parent_task;
++ tsk->set.sp_setting = sp_task->parent_task->set.sp_setting;
++
++ list_add(&tsk->node, &tsk->parent->split_list);
++ dev_dbg(tsk->dev, "[0x%p] sp_tsk Q list,no-0x%x\n", tsk, tsk->task_no);
++ tsk->state = STATE_QUEUE;
++ CHECK_PERF(&tsk->ts_queue);
++err:
++ return ret;
++}
++
++static inline int sp_task_check_done(struct ipu_split_task *sp_task,
++ struct ipu_task_entry *parent, int num, int *idx)
++{
++ int i;
++ int ret = 0;
++ struct ipu_task_entry *tsk;
++ struct mutex *lock = &parent->split_lock;
++
++ *idx = -EINVAL;
++ mutex_lock(lock);
++ for (i = 0; i < num; i++) {
++ tsk = sp_task[i].child_task;
++ if (tsk && tsk->split_done) {
++ *idx = i;
++ ret = 1;
++ goto out;
++ }
++ }
++
++out:
++ mutex_unlock(lock);
++ return ret;
++}
++
++static int create_split_task(
++ int stripe,
++ struct ipu_split_task *sp_task)
++{
++ struct ipu_task *task = &(sp_task->task);
++ struct ipu_task_entry *t = sp_task->parent_task;
++ int ret;
++
++ sp_task->task_no |= stripe;
++
++ task->input = t->input;
++ task->output = t->output;
++ task->overlay_en = t->overlay_en;
++ if (task->overlay_en)
++ task->overlay = t->overlay;
++ task->task_id = t->task_id;
++ if ((t->set.split_mode == RL_SPLIT) ||
++ (t->set.split_mode == UD_SPLIT))
++ task->timeout = t->timeout / 2;
++ else
++ task->timeout = t->timeout / 4;
++
++ task->input.crop.w = t->set.sp_setting.iw;
++ task->input.crop.h = t->set.sp_setting.ih;
++ if (task->overlay_en) {
++ task->overlay.crop.w = t->set.sp_setting.ow;
++ task->overlay.crop.h = t->set.sp_setting.oh;
++ }
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ task->output.crop.w = t->set.sp_setting.oh;
++ task->output.crop.h = t->set.sp_setting.ow;
++ t->set.sp_setting.rl_split_line = t->set.sp_setting.o_bottom_pos;
++ t->set.sp_setting.ud_split_line = t->set.sp_setting.o_right_pos;
++
++ } else {
++ task->output.crop.w = t->set.sp_setting.ow;
++ task->output.crop.h = t->set.sp_setting.oh;
++ t->set.sp_setting.rl_split_line = t->set.sp_setting.o_right_pos;
++ t->set.sp_setting.ud_split_line = t->set.sp_setting.o_bottom_pos;
++ }
++
++ if (stripe & LEFT_STRIPE)
++ task->input.crop.pos.x += t->set.sp_setting.i_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->input.crop.pos.x += t->set.sp_setting.i_right_pos;
++ if (stripe & UP_STRIPE)
++ task->input.crop.pos.y += t->set.sp_setting.i_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->input.crop.pos.y += t->set.sp_setting.i_bottom_pos;
++
++ if (task->overlay_en) {
++ if (stripe & LEFT_STRIPE)
++ task->overlay.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->overlay.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->overlay.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->overlay.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ }
++
++ switch (t->output.rotate) {
++ case IPU_ROTATE_NONE:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ break;
++ case IPU_ROTATE_VERT_FLIP:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_right_pos;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ break;
++ case IPU_ROTATE_HORIZ_FLIP:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_bottom_pos;
++ break;
++ case IPU_ROTATE_180:
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ break;
++ case IPU_ROTATE_90_RIGHT:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
++ break;
++ case IPU_ROTATE_90_RIGHT_HFLIP:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_left_pos;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y += t->set.sp_setting.o_right_pos;
++ break;
++ case IPU_ROTATE_90_RIGHT_VFLIP:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_top_pos - t->set.sp_setting.oh;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x =
++ t->output.crop.pos.x + t->output.crop.w
++ - t->set.sp_setting.o_bottom_pos - t->set.sp_setting.oh;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ break;
++ case IPU_ROTATE_90_LEFT:
++ if (stripe & UP_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_top_pos;
++ else if (stripe & DOWN_STRIPE)
++ task->output.crop.pos.x += t->set.sp_setting.o_bottom_pos;
++ if (stripe & LEFT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_left_pos - t->set.sp_setting.ow;
++ else if (stripe & RIGHT_STRIPE)
++ task->output.crop.pos.y =
++ t->output.crop.pos.y + t->output.crop.h
++ - t->set.sp_setting.o_right_pos - t->set.sp_setting.ow;
++ break;
++ default:
++ dev_err(t->dev, "ERR:should not be here\n");
++ break;
++ }
++
++ ret = create_split_child_task(sp_task);
++ if (ret < 0)
++ dev_err(t->dev, "ERR:create_split_child_task() ret:%d\n", ret);
++ return ret;
++}
++
++static int queue_split_task(struct ipu_task_entry *t,
++ struct ipu_split_task *sp_task, uint32_t size)
++{
++ int err[4];
++ int ret = 0;
++ int i, j;
++ struct ipu_task_entry *tsk = NULL;
++ struct mutex *lock = &t->split_lock;
++ struct mutex *vdic_lock = &t->vdic_lock;
++
++ dev_dbg(t->dev, "Split task 0x%p, no-0x%x, size:%d\n",
++ t, t->task_no, size);
++ mutex_init(lock);
++ mutex_init(vdic_lock);
++ init_waitqueue_head(&t->split_waitq);
++ INIT_LIST_HEAD(&t->split_list);
++ for (j = 0; j < size; j++) {
++ memset(&sp_task[j], 0, sizeof(*sp_task));
++ sp_task[j].parent_task = t;
++ sp_task[j].task_no = t->task_no;
++ }
++
++ if (t->set.split_mode == RL_SPLIT) {
++ i = 0;
++ err[i] = create_split_task(RIGHT_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(LEFT_STRIPE, &sp_task[i]);
++ } else if (t->set.split_mode == UD_SPLIT) {
++ i = 0;
++ err[i] = create_split_task(DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(UP_STRIPE, &sp_task[i]);
++ } else {
++ i = 0;
++ err[i] = create_split_task(RIGHT_STRIPE | DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 1;
++ err[i] = create_split_task(LEFT_STRIPE | DOWN_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 2;
++ err[i] = create_split_task(RIGHT_STRIPE | UP_STRIPE, &sp_task[i]);
++ if (err[i] < 0)
++ goto err_start;
++ i = 3;
++ err[i] = create_split_task(LEFT_STRIPE | UP_STRIPE, &sp_task[i]);
++ }
++
++err_start:
++ for (j = 0; j < (i + 1); j++) {
++ if (err[j] < 0) {
++ if (sp_task[j].child_task)
++ dev_err(t->dev,
++ "sp_task[%d],no-0x%x fail state:%d, queue err:%d.\n",
++ j, sp_task[j].child_task->task_no,
++ sp_task[j].child_task->state, err[j]);
++ goto err_exit;
++ }
++ dev_dbg(t->dev, "[0x%p] sp_task[%d], no-0x%x state:%s, queue ret:%d.\n",
++ sp_task[j].child_task, j, sp_task[j].child_task->task_no,
++ state_msg[sp_task[j].child_task->state].msg, err[j]);
++ }
++
++ return ret;
++
++err_exit:
++ for (j = 0; j < (i + 1); j++) {
++ if (err[j] < 0 && !ret)
++ ret = err[j];
++ tsk = sp_task[j].child_task;
++ if (!tsk)
++ continue;
++ kfree(tsk);
++ }
++ t->state = STATE_ERR;
++ return ret;
++
++}
++
++static int init_tiled_buf(struct ipu_soc *ipu, struct ipu_task_entry *t,
++ ipu_channel_t channel, uint32_t ch_type)
++{
++ int ret = 0;
++ int i;
++ uint32_t ipu_fmt;
++ dma_addr_t inbuf_base = 0;
++ u32 field_size;
++ struct vdoa_params param;
++ struct vdoa_ipu_buf buf;
++ struct ipu_soc *ipu_idx;
++ u32 ipu_stride, obuf_size;
++ u32 height, width;
++ ipu_buffer_t type;
++
++ if ((IPU_PIX_FMT_YUYV != t->output.format) &&
++ (IPU_PIX_FMT_NV12 != t->output.format)) {
++ dev_err(t->dev, "ERR:[0x%d] output format\n", t->task_no);
++ return -EINVAL;
++ }
++
++ memset(&param, 0, sizeof(param));
++ /* init channel tiled bufs */
++ if (deinterlace_3_field(t) &&
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ field_size = tiled_filed_size(t);
++ if (INPUT_CHAN_VDI_P == ch_type) {
++ inbuf_base = t->input.paddr + field_size;
++ param.vfield_buf.prev_veba = inbuf_base + t->set.i_off;
++ } else if (INPUT_CHAN == ch_type) {
++ inbuf_base = t->input.paddr_n;
++ param.vfield_buf.cur_veba = inbuf_base + t->set.i_off;
++ } else if (INPUT_CHAN_VDI_N == ch_type) {
++ inbuf_base = t->input.paddr_n + field_size;
++ param.vfield_buf.next_veba = inbuf_base + t->set.i_off;
++ } else
++ return -EINVAL;
++ height = t->input.crop.h >> 1; /* field format for vdoa */
++ width = t->input.crop.w;
++ param.vfield_buf.vubo = t->set.i_uoff;
++ param.interlaced = 1;
++ param.scan_order = 1;
++ type = IPU_INPUT_BUFFER;
++ } else if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) &&
++ (INPUT_CHAN == ch_type)) {
++ height = t->input.crop.h;
++ width = t->input.crop.w;
++ param.vframe_buf.veba = t->input.paddr + t->set.i_off;
++ param.vframe_buf.vubo = t->set.i_uoff;
++ type = IPU_INPUT_BUFFER;
++ } else
++ return -EINVAL;
++
++ param.band_mode = (t->set.mode & VDOA_BAND_MODE) ? 1 : 0;
++ if (param.band_mode && (t->set.band_lines != 3) &&
++ (t->set.band_lines != 4) && (t->set.band_lines != 5))
++ return -EINVAL;
++ else if (param.band_mode)
++ param.band_lines = (1 << t->set.band_lines);
++ for (i = 0; i < max_ipu_no; i++) {
++ ipu_idx = ipu_get_soc(i);
++ if (!IS_ERR(ipu_idx) && ipu_idx == ipu)
++ break;
++ }
++ if (t->set.task & VDOA_ONLY)
++ /* dummy, didn't need ipu res */
++ i = 0;
++ if (max_ipu_no == i) {
++ dev_err(t->dev, "ERR:[0x%p] get ipu num\n", t);
++ return -EINVAL;
++ }
++
++ param.ipu_num = i;
++ param.vpu_stride = t->input.width;
++ param.height = height;
++ param.width = width;
++ if (IPU_PIX_FMT_NV12 == t->output.format)
++ param.pfs = VDOA_PFS_NV12;
++ else
++ param.pfs = VDOA_PFS_YUYV;
++ ipu_fmt = (param.pfs == VDOA_PFS_YUYV) ? IPU_PIX_FMT_YUYV :
++ IPU_PIX_FMT_NV12;
++ ipu_stride = param.width * bytes_per_pixel(ipu_fmt);
++ obuf_size = PAGE_ALIGN(param.width * param.height *
++ fmt_to_bpp(ipu_fmt)/8);
++ dev_dbg(t->dev, "band_mode:%d, band_lines:%d\n",
++ param.band_mode, param.band_lines);
++ if (!param.band_mode) {
++ /* note: if only for tiled -> raster convert and
++ no other post-processing, we don't need alloc buf
++ and use output buffer directly.
++ */
++ if (t->set.task & VDOA_ONLY)
++ param.ieba0 = t->output.paddr;
++ else {
++ dev_err(t->dev, "ERR:[0x%d] vdoa task\n", t->task_no);
++ return -EINVAL;
++ }
++ } else {
++ if (IPU_PIX_FMT_TILED_NV12F != t->input.format) {
++ dev_err(t->dev, "ERR [0x%d] vdoa task\n", t->task_no);
++ return -EINVAL;
++ }
++ }
++ ret = vdoa_setup(t->vdoa_handle, &param);
++ if (ret)
++ goto done;
++ vdoa_get_output_buf(t->vdoa_handle, &buf);
++ if (t->set.task & VDOA_ONLY)
++ goto done;
++
++ ret = ipu_init_channel_buffer(ipu,
++ channel,
++ type,
++ ipu_fmt,
++ width,
++ height,
++ ipu_stride,
++ IPU_ROTATE_NONE,
++ buf.ieba0,
++ buf.ieba1,
++ 0,
++ buf.iubo,
++ 0);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ if (param.band_mode) {
++ ret = ipu_set_channel_bandmode(ipu, channel,
++ type, t->set.band_lines);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BAND_FAIL;
++ goto done;
++ }
++ }
++done:
++ return ret;
++}
++
++static int init_tiled_ch_bufs(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++
++ if (IPU_PIX_FMT_TILED_NV12 == t->input.format) {
++ ret = init_tiled_buf(ipu, t, t->set.ic_chan, INPUT_CHAN);
++ CHECK_RETCODE(ret < 0, "init tiled_ch", t->state, done, ret);
++ } else if (IPU_PIX_FMT_TILED_NV12F == t->input.format) {
++ ret = init_tiled_buf(ipu, t, t->set.ic_chan, INPUT_CHAN);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-c", t->state, done, ret);
++ ret = init_tiled_buf(ipu, t, t->set.vdi_ic_p_chan,
++ INPUT_CHAN_VDI_P);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-p", t->state, done, ret);
++ ret = init_tiled_buf(ipu, t, t->set.vdi_ic_n_chan,
++ INPUT_CHAN_VDI_N);
++ CHECK_RETCODE(ret < 0, "init tiled_ch-n", t->state, done, ret);
++ } else {
++ ret = -EINVAL;
++ dev_err(t->dev, "ERR[no-0x%x] invalid fmt:0x%x!\n",
++ t->task_no, t->input.format);
++ }
++
++done:
++ return ret;
++}
++
++static int init_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++ ipu_channel_params_t params;
++ dma_addr_t inbuf = 0, ovbuf = 0, ov_alp_buf = 0;
++ dma_addr_t inbuf_p = 0, inbuf_n = 0;
++ dma_addr_t outbuf = 0;
++ int out_uoff = 0, out_voff = 0, out_rot;
++ int out_w = 0, out_h = 0, out_stride;
++ int out_fmt;
++ u32 vdi_frame_idx = 0;
++
++ memset(&params, 0, sizeof(params));
++
++ /* is it need link a rot channel */
++ if (ic_and_rot(t->set.mode)) {
++ outbuf = t->set.r_paddr;
++ out_w = t->set.r_width;
++ out_h = t->set.r_height;
++ out_stride = t->set.r_stride;
++ out_fmt = t->set.r_fmt;
++ out_uoff = 0;
++ out_voff = 0;
++ out_rot = IPU_ROTATE_NONE;
++ } else {
++ outbuf = t->output.paddr + t->set.o_off;
++ out_w = t->output.crop.w;
++ out_h = t->output.crop.h;
++ out_stride = t->set.ostride;
++ out_fmt = t->output.format;
++ out_uoff = t->set.o_uoff;
++ out_voff = t->set.o_voff;
++ out_rot = t->output.rotate;
++ }
++
++ /* settings */
++ params.mem_prp_vf_mem.in_width = t->input.crop.w;
++ params.mem_prp_vf_mem.out_width = out_w;
++ params.mem_prp_vf_mem.in_height = t->input.crop.h;
++ params.mem_prp_vf_mem.out_height = out_h;
++ params.mem_prp_vf_mem.in_pixel_fmt = t->input.format;
++ params.mem_prp_vf_mem.out_pixel_fmt = out_fmt;
++ params.mem_prp_vf_mem.motion_sel = t->input.deinterlace.motion;
++
++ params.mem_prp_vf_mem.outh_resize_ratio =
++ t->set.sp_setting.outh_resize_ratio;
++ params.mem_prp_vf_mem.outv_resize_ratio =
++ t->set.sp_setting.outv_resize_ratio;
++
++ if (t->overlay_en) {
++ params.mem_prp_vf_mem.in_g_pixel_fmt = t->overlay.format;
++ params.mem_prp_vf_mem.graphics_combine_en = 1;
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_GLOBAL)
++ params.mem_prp_vf_mem.global_alpha_en = 1;
++ else if (t->overlay.alpha.loc_alp_paddr)
++ params.mem_prp_vf_mem.alpha_chan_en = 1;
++ /* otherwise, alpha bending per pixel is used. */
++ params.mem_prp_vf_mem.alpha = t->overlay.alpha.gvalue;
++ if (t->overlay.colorkey.enable) {
++ params.mem_prp_vf_mem.key_color_en = 1;
++ params.mem_prp_vf_mem.key_color = t->overlay.colorkey.value;
++ }
++ }
++
++ if (t->input.deinterlace.enable) {
++ if (t->input.deinterlace.field_fmt & IPU_DEINTERLACE_FIELD_MASK)
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ else
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++
++ if (t->input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN)
++ vdi_frame_idx = t->input.deinterlace.field_fmt &
++ IPU_DEINTERLACE_RATE_FRAME1;
++ }
++
++ if (t->set.mode & VDOA_MODE)
++ ipu->vdoa_en = 1;
++
++ /* init channels */
++ if (!(t->set.task & VDOA_ONLY)) {
++ ret = ipu_init_channel(ipu, t->set.ic_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ }
++
++ if (deinterlace_3_field(t)) {
++ ret = ipu_init_channel(ipu, t->set.vdi_ic_p_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ ret = ipu_init_channel(ipu, t->set.vdi_ic_n_chan, &params);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++ }
++
++ /* init channel bufs */
++ if ((IPU_PIX_FMT_TILED_NV12 == t->input.format) ||
++ (IPU_PIX_FMT_TILED_NV12F == t->input.format)) {
++ ret = init_tiled_ch_bufs(ipu, t);
++ if (ret < 0)
++ goto done;
++ } else {
++ if ((deinterlace_3_field(t)) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ if (params.mem_prp_vf_mem.field_fmt ==
++ IPU_DEINTERLACE_FIELD_TOP) {
++ if (vdi_frame_idx) {
++ inbuf_p = t->input.paddr + t->set.istride +
++ t->set.i_off;
++ inbuf = t->input.paddr_n + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.istride +
++ t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ } else {
++ inbuf_p = t->input.paddr + t->set.i_off;
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.i_off;
++ }
++ } else {
++ if (vdi_frame_idx) {
++ inbuf_p = t->input.paddr + t->set.i_off;
++ inbuf = t->input.paddr_n + t->set.istride + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++ } else {
++ inbuf_p = t->input.paddr + t->set.istride +
++ t->set.i_off;
++ inbuf = t->input.paddr + t->set.i_off;
++ inbuf_n = t->input.paddr_n + t->set.istride +
++ t->set.i_off;
++ }
++ }
++ } else {
++ if (t->input.deinterlace.enable) {
++ if (params.mem_prp_vf_mem.field_fmt ==
++ IPU_DEINTERLACE_FIELD_TOP) {
++ if (vdi_frame_idx) {
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_BOTTOM;
++ } else
++ inbuf = t->input.paddr + t->set.i_off;
++ } else {
++ if (vdi_frame_idx) {
++ inbuf = t->input.paddr + t->set.i_off;
++ params.mem_prp_vf_mem.field_fmt =
++ IPU_DEINTERLACE_FIELD_TOP;
++ } else
++ inbuf = t->input.paddr + t->set.istride + t->set.i_off;
++ }
++ } else
++ inbuf = t->input.paddr + t->set.i_off;
++ }
++
++ if (t->overlay_en)
++ ovbuf = t->overlay.paddr + t->set.ov_off;
++ }
++ if (t->overlay_en && (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL))
++ ov_alp_buf = t->overlay.alpha.loc_alp_paddr
++ + t->set.ov_alpha_off;
++
++ if ((IPU_PIX_FMT_TILED_NV12 != t->input.format) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++ if (deinterlace_3_field(t) &&
++ (IPU_PIX_FMT_TILED_NV12F != t->input.format)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.vdi_ic_p_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf_p,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.vdi_ic_n_chan,
++ IPU_INPUT_BUFFER,
++ t->input.format,
++ t->input.crop.w,
++ t->input.crop.h,
++ t->set.istride,
++ IPU_ROTATE_NONE,
++ inbuf_n,
++ 0,
++ 0,
++ t->set.i_uoff,
++ t->set.i_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (t->overlay_en) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER,
++ t->overlay.format,
++ t->overlay.crop.w,
++ t->overlay.crop.h,
++ t->set.ovstride,
++ IPU_ROTATE_NONE,
++ ovbuf,
++ 0,
++ 0,
++ t->set.ov_uoff,
++ t->set.ov_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER,
++ IPU_PIX_FMT_GENERIC,
++ t->overlay.crop.w,
++ t->overlay.crop.h,
++ t->set.ov_alpha_stride,
++ IPU_ROTATE_NONE,
++ ov_alp_buf,
++ 0,
++ 0,
++ 0, 0);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if (!(t->set.task & VDOA_ONLY)) {
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.ic_chan,
++ IPU_OUTPUT_BUFFER,
++ out_fmt,
++ out_w,
++ out_h,
++ out_stride,
++ out_rot,
++ outbuf,
++ 0,
++ 0,
++ out_uoff,
++ out_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++ }
++
++ if ((t->set.mode & VDOA_BAND_MODE) && (t->set.task & VDI_VF)) {
++ ret = ipu_link_channels(ipu, MEM_VDOA_MEM, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_link_ch vdoa_ic",
++ STATE_LINK_CHAN_FAIL, done, ret);
++ }
++
++done:
++ return ret;
++}
++
++static void uninit_ic(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret;
++
++ if ((t->set.mode & VDOA_BAND_MODE) && (t->set.task & VDI_VF)) {
++ ret = ipu_unlink_channels(ipu, MEM_VDOA_MEM, t->set.ic_chan);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_unlink_ch vdoa_ic",
++ STATE_UNLINK_CHAN_FAIL, ret);
++ }
++ ipu_uninit_channel(ipu, t->set.ic_chan);
++ if (deinterlace_3_field(t)) {
++ ipu_uninit_channel(ipu, t->set.vdi_ic_p_chan);
++ ipu_uninit_channel(ipu, t->set.vdi_ic_n_chan);
++ }
++}
++
++static int init_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ int ret = 0;
++ dma_addr_t inbuf = 0, outbuf = 0;
++ int in_uoff = 0, in_voff = 0;
++ int in_fmt, in_width, in_height, in_stride;
++
++ /* init channel */
++ ret = ipu_init_channel(ipu, t->set.rot_chan, NULL);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_FAIL;
++ goto done;
++ }
++
++ /* init channel buf */
++ /* is it need link to a ic channel */
++ if (ic_and_rot(t->set.mode)) {
++ in_fmt = t->set.r_fmt;
++ in_width = t->set.r_width;
++ in_height = t->set.r_height;
++ in_stride = t->set.r_stride;
++ inbuf = t->set.r_paddr;
++ in_uoff = 0;
++ in_voff = 0;
++ } else {
++ in_fmt = t->input.format;
++ in_width = t->input.crop.w;
++ in_height = t->input.crop.h;
++ in_stride = t->set.istride;
++ inbuf = t->input.paddr + t->set.i_off;
++ in_uoff = t->set.i_uoff;
++ in_voff = t->set.i_voff;
++ }
++ outbuf = t->output.paddr + t->set.o_off;
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.rot_chan,
++ IPU_INPUT_BUFFER,
++ in_fmt,
++ in_width,
++ in_height,
++ in_stride,
++ t->output.rotate,
++ inbuf,
++ 0,
++ 0,
++ in_uoff,
++ in_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++ ret = ipu_init_channel_buffer(ipu,
++ t->set.rot_chan,
++ IPU_OUTPUT_BUFFER,
++ t->output.format,
++ t->output.crop.w,
++ t->output.crop.h,
++ t->set.ostride,
++ IPU_ROTATE_NONE,
++ outbuf,
++ 0,
++ 0,
++ t->set.o_uoff,
++ t->set.o_voff);
++ if (ret < 0) {
++ t->state = STATE_INIT_CHAN_BUF_FAIL;
++ goto done;
++ }
++
++done:
++ return ret;
++}
++
++static void uninit_rot(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ ipu_uninit_channel(ipu, t->set.rot_chan);
++}
++
++static int get_irq(struct ipu_task_entry *t)
++{
++ int irq;
++ ipu_channel_t chan;
++
++ if (only_ic(t->set.mode))
++ chan = t->set.ic_chan;
++ else
++ chan = t->set.rot_chan;
++
++ switch (chan) {
++ case MEM_ROT_VF_MEM:
++ irq = IPU_IRQ_PRP_VF_ROT_OUT_EOF;
++ break;
++ case MEM_ROT_PP_MEM:
++ irq = IPU_IRQ_PP_ROT_OUT_EOF;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ irq = IPU_IRQ_PRP_VF_OUT_EOF;
++ break;
++ case MEM_PP_MEM:
++ irq = IPU_IRQ_PP_OUT_EOF;
++ break;
++ case MEM_VDI_MEM:
++ irq = IPU_IRQ_VDIC_OUT_EOF;
++ break;
++ default:
++ irq = -EINVAL;
++ }
++
++ return irq;
++}
++
++static irqreturn_t task_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_task_entry *prev_tsk = dev_id;
++
++ CHECK_PERF(&prev_tsk->ts_inirq);
++ complete(&prev_tsk->irq_comp);
++ dev_dbg(prev_tsk->dev, "[0x%p] no-0x%x in-irq!",
++ prev_tsk, prev_tsk->task_no);
++
++ return IRQ_HANDLED;
++}
++
++/* Fix deinterlace up&down split mode medium line */
++static void vdi_split_process(struct ipu_soc *ipu, struct ipu_task_entry *t)
++{
++ u32 vdi_size;
++ u32 vdi_save_lines;
++ u32 stripe_mode;
++ u32 task_no;
++ u32 i, offset_addr;
++ u32 line_size;
++ unsigned char *base_off;
++ struct ipu_task_entry *parent = t->parent;
++ struct mutex *lock = &parent->vdic_lock;
++
++ if (!parent) {
++ dev_err(t->dev, "ERR[0x%x]invalid parent\n", t->task_no);
++ return;
++ }
++ mutex_lock(lock);
++ stripe_mode = t->task_no & 0xf;
++ task_no = t->task_no >> 4;
++
++ /* Save both luma and chroma part for interleaved YUV(e.g. YUYV).
++ * Save luma part for non-interleaved and partial-interleaved
++ * YUV format (e.g NV12 and YV12). */
++ if (t->output.format == IPU_PIX_FMT_YUYV ||
++ t->output.format == IPU_PIX_FMT_UYVY)
++ line_size = t->output.crop.w * fmt_to_bpp(t->output.format)/8;
++ else
++ line_size = t->output.crop.w;
++
++ vdi_save_lines = (t->output.crop.h - t->set.sp_setting.ud_split_line)/2;
++ vdi_size = vdi_save_lines * line_size;
++ if (vdi_save_lines <= 0) {
++ dev_err(t->dev, "[0x%p] vdi_save_line error\n", (void *)t);
++ mutex_unlock(lock);
++ return;
++ }
++
++ /*check vditmpbuf buffer have alloced or buffer size is changed */
++ if ((vdi_save_lines != parent->old_save_lines) ||
++ (vdi_size != parent->old_size)) {
++ if (parent->vditmpbuf[0] != NULL)
++ kfree(parent->vditmpbuf[0]);
++ if (parent->vditmpbuf[1] != NULL)
++ kfree(parent->vditmpbuf[1]);
++
++ parent->vditmpbuf[0] = kmalloc(vdi_size, GFP_KERNEL);
++ if (parent->vditmpbuf[0] == NULL) {
++ dev_err(t->dev,
++ "[0x%p]Falied Alloc vditmpbuf[0]\n", (void *)t);
++ mutex_unlock(lock);
++ return;
++ }
++ memset(parent->vditmpbuf[0], 0, vdi_size);
++
++ parent->vditmpbuf[1] = kmalloc(vdi_size, GFP_KERNEL);
++ if (parent->vditmpbuf[1] == NULL) {
++ dev_err(t->dev,
++ "[0x%p]Falied Alloc vditmpbuf[1]\n", (void *)t);
++ mutex_unlock(lock);
++ return;
++ }
++ memset(parent->vditmpbuf[1], 0, vdi_size);
++
++ parent->old_save_lines = vdi_save_lines;
++ parent->old_size = vdi_size;
++ }
++
++ if (pfn_valid(t->output.paddr >> PAGE_SHIFT)) {
++ base_off = page_address(pfn_to_page(t->output.paddr >> PAGE_SHIFT));
++ base_off += t->output.paddr & ((1 << PAGE_SHIFT) - 1);
++ } else {
++ base_off = (char *)ioremap_nocache(t->output.paddr,
++ t->output.width * t->output.height *
++ fmt_to_bpp(t->output.format)/8);
++ }
++ if (base_off == NULL) {
++ dev_err(t->dev, "ERR[0x%p]Failed get virtual address\n", t);
++ mutex_unlock(lock);
++ return;
++ }
++
++ /* UP stripe or UP&LEFT stripe */
++ if ((stripe_mode == UP_STRIPE) ||
++ (stripe_mode == (UP_STRIPE | LEFT_STRIPE))) {
++ if (!parent->buf0filled) {
++ offset_addr = t->set.o_off +
++ t->set.sp_setting.ud_split_line*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[0] + i*line_size,
++ base_off + offset_addr +
++ i*t->set.ostride, line_size);
++ parent->buf0filled = true;
++ } else {
++ offset_addr = t->set.o_off + (t->output.crop.h -
++ vdi_save_lines) * t->set.ostride;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[0] + i*line_size, line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf0filled = false;
++ }
++ }
++ /*Down stripe or Down&Left stripe*/
++ else if ((stripe_mode == DOWN_STRIPE) ||
++ (stripe_mode == (DOWN_STRIPE | LEFT_STRIPE))) {
++ if (!parent->buf0filled) {
++ offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[0] + i*line_size,
++ base_off + offset_addr + i*t->set.ostride,
++ line_size);
++ parent->buf0filled = true;
++ } else {
++ offset_addr = t->set.o_off;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[0] + i*line_size,
++ line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf0filled = false;
++ }
++ }
++ /*Up&Right stripe*/
++ else if (stripe_mode == (UP_STRIPE | RIGHT_STRIPE)) {
++ if (!parent->buf1filled) {
++ offset_addr = t->set.o_off +
++ t->set.sp_setting.ud_split_line*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_size);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_size);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[1] + i*line_size,
++ base_off + offset_addr + i*t->set.ostride,
++ line_size);
++ parent->buf1filled = true;
++ } else {
++ offset_addr = t->set.o_off +
++ (t->output.crop.h - vdi_save_lines)*t->set.ostride;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[1] + i*line_size,
++ line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + i*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + i*t->set.ostride);
++ parent->buf1filled = false;
++ }
++ }
++ /*Down stripe or Down&Right stript*/
++ else if (stripe_mode == (DOWN_STRIPE | RIGHT_STRIPE)) {
++ if (!parent->buf1filled) {
++ offset_addr = t->set.o_off + vdi_save_lines*t->set.ostride;
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_save_lines*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
++
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(parent->vditmpbuf[1] + i*line_size,
++ base_off + offset_addr + i*t->set.ostride,
++ line_size);
++ parent->buf1filled = true;
++ } else {
++ offset_addr = t->set.o_off;
++ for (i = 0; i < vdi_save_lines; i++)
++ memcpy(base_off + offset_addr + i*t->set.ostride,
++ parent->vditmpbuf[1] + i*line_size,
++ line_size);
++
++ dmac_flush_range(base_off + offset_addr,
++ base_off + offset_addr + vdi_save_lines*t->set.ostride);
++ outer_flush_range(t->output.paddr + offset_addr,
++ t->output.paddr + offset_addr + vdi_save_lines*t->set.ostride);
++ parent->buf1filled = false;
++ }
++ }
++ if (!pfn_valid(t->output.paddr >> PAGE_SHIFT))
++ iounmap(base_off);
++ mutex_unlock(lock);
++}
++
++static void do_task_release(struct ipu_task_entry *t, int fail)
++{
++ int ret;
++ struct ipu_soc *ipu = t->ipu;
++
++ if (t->input.deinterlace.enable && !fail &&
++ (t->task_no & (UP_STRIPE | DOWN_STRIPE)))
++ vdi_split_process(ipu, t);
++
++ ipu_free_irq(ipu, t->irq, t);
++
++ if (t->vdoa_dma.vaddr)
++ dma_free_coherent(t->dev,
++ t->vdoa_dma.size,
++ t->vdoa_dma.vaddr,
++ t->vdoa_dma.paddr);
++
++ if (only_ic(t->set.mode)) {
++ ret = ipu_disable_channel(ipu, t->set.ic_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_p_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic_p",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_n_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_ic_n",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ }
++ } else if (only_rot(t->set.mode)) {
++ ret = ipu_disable_channel(ipu, t->set.rot_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch only_rot",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ ret = ipu_unlink_channels(ipu, t->set.ic_chan, t->set.rot_chan);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_unlink_ch",
++ STATE_UNLINK_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.rot_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch ic_and_rot-rot",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.ic_chan, true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch ic_and_rot-ic",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_p_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch icrot-ic-p",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ ret = ipu_disable_channel(ipu, t->set.vdi_ic_n_chan,
++ true);
++ CHECK_RETCODE_CONT(ret < 0, "ipu_disable_ch icrot-ic-n",
++ STATE_DISABLE_CHAN_FAIL, ret);
++ }
++ }
++
++ if (only_ic(t->set.mode))
++ uninit_ic(ipu, t);
++ else if (only_rot(t->set.mode))
++ uninit_rot(ipu, t);
++ else if (ic_and_rot(t->set.mode)) {
++ uninit_ic(ipu, t);
++ uninit_rot(ipu, t);
++ }
++
++ t->state = STATE_OK;
++ CHECK_PERF(&t->ts_rel);
++ return;
++}
++
++static void do_task_vdoa_only(struct ipu_task_entry *t)
++{
++ int ret;
++
++ ret = init_tiled_ch_bufs(NULL, t);
++ CHECK_RETCODE(ret < 0, "do_vdoa_only", STATE_ERR, out, ret);
++ ret = vdoa_start(t->vdoa_handle, VDOA_DEF_TIMEOUT_MS);
++ vdoa_stop(t->vdoa_handle);
++ CHECK_RETCODE(ret < 0, "vdoa_wait4complete, do_vdoa_only",
++ STATE_VDOA_IRQ_TIMEOUT, out, ret);
++
++ t->state = STATE_OK;
++out:
++ return;
++}
++
++static void do_task(struct ipu_task_entry *t)
++{
++ int r_size;
++ int irq;
++ int ret;
++ uint32_t busy;
++ struct ipu_soc *ipu = t->ipu;
++
++ CHECK_PERF(&t->ts_dotask);
++
++ if (!ipu) {
++ t->state = STATE_NO_IPU;
++ return;
++ }
++
++ init_completion(&t->irq_comp);
++ dev_dbg(ipu->dev, "[0x%p]Do task no:0x%x: id %d\n", (void *)t,
++ t->task_no, t->task_id);
++ dump_task_info(t);
++
++ if (t->set.task & IC_PP) {
++ t->set.ic_chan = MEM_PP_MEM;
++ dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PP_MEM\n", (void *)t);
++ } else if (t->set.task & IC_VF) {
++ t->set.ic_chan = MEM_PRP_VF_MEM;
++ dev_dbg(ipu->dev, "[0x%p]ic channel MEM_PRP_VF_MEM\n", (void *)t);
++ } else if (t->set.task & VDI_VF) {
++ if (t->set.mode & VDOA_BAND_MODE) {
++ t->set.ic_chan = MEM_VDI_MEM;
++ if (deinterlace_3_field(t)) {
++ t->set.vdi_ic_p_chan = MEM_VDI_MEM_P;
++ t->set.vdi_ic_n_chan = MEM_VDI_MEM_N;
++ }
++ dev_dbg(ipu->dev, "[0x%p]ic ch MEM_VDI_MEM\n",
++ (void *)t);
++ } else {
++ t->set.ic_chan = MEM_VDI_PRP_VF_MEM;
++ if (deinterlace_3_field(t)) {
++ t->set.vdi_ic_p_chan = MEM_VDI_PRP_VF_MEM_P;
++ t->set.vdi_ic_n_chan = MEM_VDI_PRP_VF_MEM_N;
++ }
++ dev_dbg(ipu->dev,
++ "[0x%p]ic ch MEM_VDI_PRP_VF_MEM\n", t);
++ }
++ }
++
++ if (t->set.task & ROT_PP) {
++ t->set.rot_chan = MEM_ROT_PP_MEM;
++ dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_PP_MEM\n", (void *)t);
++ } else if (t->set.task & ROT_VF) {
++ t->set.rot_chan = MEM_ROT_VF_MEM;
++ dev_dbg(ipu->dev, "[0x%p]rot channel MEM_ROT_VF_MEM\n", (void *)t);
++ }
++
++ if (t->task_id == IPU_TASK_ID_VF)
++ busy = ic_vf_pp_is_busy(ipu, true);
++ else if (t->task_id == IPU_TASK_ID_PP)
++ busy = ic_vf_pp_is_busy(ipu, false);
++ else {
++ dev_err(ipu->dev, "ERR[no:0x%x]ipu task_id:%d invalid!\n",
++ t->task_no, t->task_id);
++ return;
++ }
++ if (busy) {
++ dev_err(ipu->dev, "ERR[0x%p-no:0x%x]ipu task_id:%d busy!\n",
++ (void *)t, t->task_no, t->task_id);
++ t->state = STATE_IPU_BUSY;
++ return;
++ }
++
++ irq = get_irq(t);
++ if (irq < 0) {
++ t->state = STATE_NO_IRQ;
++ return;
++ }
++ t->irq = irq;
++
++ /* channel setup */
++ if (only_ic(t->set.mode)) {
++ dev_dbg(t->dev, "[0x%p]only ic mode\n", (void *)t);
++ ret = init_ic(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_ic only_ic",
++ t->state, chan_setup, ret);
++ } else if (only_rot(t->set.mode)) {
++ dev_dbg(t->dev, "[0x%p]only rot mode\n", (void *)t);
++ ret = init_rot(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_rot only_rot",
++ t->state, chan_setup, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ int rot_idx = (t->task_id == IPU_TASK_ID_VF) ? 0 : 1;
++
++ dev_dbg(t->dev, "[0x%p]ic + rot mode\n", (void *)t);
++ t->set.r_fmt = t->output.format;
++ if (t->output.rotate >= IPU_ROTATE_90_RIGHT) {
++ t->set.r_width = t->output.crop.h;
++ t->set.r_height = t->output.crop.w;
++ } else {
++ t->set.r_width = t->output.crop.w;
++ t->set.r_height = t->output.crop.h;
++ }
++ t->set.r_stride = t->set.r_width *
++ bytes_per_pixel(t->set.r_fmt);
++ r_size = PAGE_ALIGN(t->set.r_width * t->set.r_height
++ * fmt_to_bpp(t->set.r_fmt)/8);
++
++ if (r_size > ipu->rot_dma[rot_idx].size) {
++ dev_dbg(t->dev, "[0x%p]realloc rot buffer\n", (void *)t);
++
++ if (ipu->rot_dma[rot_idx].vaddr)
++ dma_free_coherent(t->dev,
++ ipu->rot_dma[rot_idx].size,
++ ipu->rot_dma[rot_idx].vaddr,
++ ipu->rot_dma[rot_idx].paddr);
++
++ ipu->rot_dma[rot_idx].size = r_size;
++ ipu->rot_dma[rot_idx].vaddr = dma_alloc_coherent(t->dev,
++ r_size,
++ &ipu->rot_dma[rot_idx].paddr,
++ GFP_DMA | GFP_KERNEL);
++ CHECK_RETCODE(ipu->rot_dma[rot_idx].vaddr == NULL,
++ "ic_and_rot", STATE_SYS_NO_MEM,
++ chan_setup, -ENOMEM);
++ }
++ t->set.r_paddr = ipu->rot_dma[rot_idx].paddr;
++
++ dev_dbg(t->dev, "[0x%p]rotation:\n", (void *)t);
++ dev_dbg(t->dev, "[0x%p]\tformat = 0x%x\n", (void *)t, t->set.r_fmt);
++ dev_dbg(t->dev, "[0x%p]\twidth = %d\n", (void *)t, t->set.r_width);
++ dev_dbg(t->dev, "[0x%p]\theight = %d\n", (void *)t, t->set.r_height);
++ dev_dbg(t->dev, "[0x%p]\tpaddr = 0x%x\n", (void *)t, t->set.r_paddr);
++ dev_dbg(t->dev, "[0x%p]\trstride = %d\n", (void *)t, t->set.r_stride);
++
++ ret = init_ic(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_ic ic_and_rot",
++ t->state, chan_setup, ret);
++ ret = init_rot(ipu, t);
++ CHECK_RETCODE(ret < 0, "init_rot ic_and_rot",
++ t->state, chan_setup, ret);
++ ret = ipu_link_channels(ipu, t->set.ic_chan,
++ t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_link_ch ic_and_rot",
++ STATE_LINK_CHAN_FAIL, chan_setup, ret);
++ } else {
++ dev_err(t->dev, "ERR [0x%p]do task: should not be here\n", t);
++ t->state = STATE_ERR;
++ return;
++ }
++
++ ret = ipu_request_irq(ipu, irq, task_irq_handler, 0, NULL, t);
++ CHECK_RETCODE(ret < 0, "ipu_req_irq",
++ STATE_IRQ_FAIL, chan_setup, ret);
++
++ /* enable/start channel */
++ if (only_ic(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic_p",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_ic_n",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ }
++
++ ret = ipu_select_buffer(ipu, t->set.ic_chan, IPU_OUTPUT_BUFFER,
++ 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay_en) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_g",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_a",
++ STATE_SEL_BUF_FAIL, chan_buf,
++ ret);
++ }
++ }
++ if (!(t->set.mode & VDOA_BAND_MODE)) {
++ if (deinterlace_3_field(t))
++ ipu_select_multi_vdi_buffer(ipu, 0);
++ else {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_ic_i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ }
++ }
++ } else if (only_rot(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch only_rot",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_rot_o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf only_rot_i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ } else if (ic_and_rot(t->set.mode)) {
++ ret = ipu_enable_channel(ipu, t->set.rot_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-rot",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.ic_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-ic",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ if (deinterlace_3_field(t)) {
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_p_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-p",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ ret = ipu_enable_channel(ipu, t->set.vdi_ic_n_chan);
++ CHECK_RETCODE(ret < 0, "ipu_enable_ch ic_and_rot-n",
++ STATE_ENABLE_CHAN_FAIL, chan_en, ret);
++ }
++
++ ret = ipu_select_buffer(ipu, t->set.rot_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-rot-o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay_en) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_GRAPH_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-g",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (t->overlay.alpha.mode == IPU_ALPHA_MODE_LOCAL) {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_ALPHA_IN_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf icrot-ic-a",
++ STATE_SEL_BUF_FAIL,
++ chan_buf, ret);
++ }
++ }
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_OUTPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-o",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ if (deinterlace_3_field(t))
++ ipu_select_multi_vdi_buffer(ipu, 0);
++ else {
++ ret = ipu_select_buffer(ipu, t->set.ic_chan,
++ IPU_INPUT_BUFFER, 0);
++ CHECK_RETCODE(ret < 0, "ipu_sel_buf ic_and_rot-ic-i",
++ STATE_SEL_BUF_FAIL, chan_buf, ret);
++ }
++ }
++
++ if (need_split(t))
++ t->state = STATE_IN_PROGRESS;
++
++ if (t->set.mode & VDOA_BAND_MODE) {
++ ret = vdoa_start(t->vdoa_handle, VDOA_DEF_TIMEOUT_MS);
++ CHECK_RETCODE(ret < 0, "vdoa_wait4complete, do_vdoa_band",
++ STATE_VDOA_IRQ_TIMEOUT, chan_rel, ret);
++ }
++
++ CHECK_PERF(&t->ts_waitirq);
++ ret = wait_for_completion_timeout(&t->irq_comp,
++ msecs_to_jiffies(t->timeout - DEF_DELAY_MS));
++ CHECK_PERF(&t->ts_wakeup);
++ CHECK_RETCODE(ret == 0, "wait_for_comp_timeout",
++ STATE_IRQ_TIMEOUT, chan_rel, ret);
++ dev_dbg(t->dev, "[0x%p] no-0x%x ipu irq done!", t, t->task_no);
++
++chan_rel:
++chan_buf:
++chan_en:
++chan_setup:
++ if (t->set.mode & VDOA_BAND_MODE)
++ vdoa_stop(t->vdoa_handle);
++ do_task_release(t, t->state >= STATE_ERR);
++ return;
++}
++
++static void do_task_vdoa_vdi(struct ipu_task_entry *t)
++{
++ int i;
++ int ret;
++ u32 stripe_width;
++
++ /* FIXME: crop mode not support now */
++ stripe_width = t->input.width >> 1;
++ t->input.crop.pos.x = 0;
++ t->input.crop.pos.y = 0;
++ t->input.crop.w = stripe_width;
++ t->input.crop.h = t->input.height;
++ t->output.crop.w = stripe_width;
++ t->output.crop.h = t->input.height;
++
++ for (i = 0; i < 2; i++) {
++ t->input.crop.pos.x = t->input.crop.pos.x + i * stripe_width;
++ t->output.crop.pos.x = t->output.crop.pos.x + i * stripe_width;
++ /* check input */
++ ret = set_crop(&t->input.crop, t->input.width, t->input.height,
++ t->input.format);
++ if (ret < 0) {
++ ret = STATE_ERR;
++ goto done;
++ } else
++ update_offset(t->input.format,
++ t->input.width, t->input.height,
++ t->input.crop.pos.x,
++ t->input.crop.pos.y,
++ &t->set.i_off, &t->set.i_uoff,
++ &t->set.i_voff, &t->set.istride);
++ dev_dbg(t->dev, "i_off:0x%x, i_uoff:0x%x, istride:%d.\n",
++ t->set.i_off, t->set.i_uoff, t->set.istride);
++ /* check output */
++ ret = set_crop(&t->output.crop, t->input.width,
++ t->output.height, t->output.format);
++ if (ret < 0) {
++ ret = STATE_ERR;
++ goto done;
++ } else
++ update_offset(t->output.format,
++ t->output.width, t->output.height,
++ t->output.crop.pos.x,
++ t->output.crop.pos.y,
++ &t->set.o_off, &t->set.o_uoff,
++ &t->set.o_voff, &t->set.ostride);
++
++ dev_dbg(t->dev, "o_off:0x%x, o_uoff:0x%x, ostride:%d.\n",
++ t->set.o_off, t->set.o_uoff, t->set.ostride);
++
++ do_task(t);
++ }
++
++ return;
++done:
++ dev_err(t->dev, "ERR %s set_crop.\n", __func__);
++ t->state = ret;
++ return;
++}
++
++static void get_res_do_task(struct ipu_task_entry *t)
++{
++ uint32_t found;
++ uint32_t split_child;
++ struct mutex *lock;
++
++ found = get_vdoa_ipu_res(t);
++ if (!found) {
++ dev_err(t->dev, "ERR:[0x%p] no-0x%x can not get res\n",
++ t, t->task_no);
++ return;
++ } else {
++ if (t->set.task & VDOA_ONLY)
++ do_task_vdoa_only(t);
++ else if ((IPU_PIX_FMT_TILED_NV12F == t->input.format) &&
++ (t->set.mode & VDOA_BAND_MODE) &&
++ (t->input.crop.w > soc_max_vdi_in_width()))
++ do_task_vdoa_vdi(t);
++ else
++ do_task(t);
++ put_vdoa_ipu_res(t, 0);
++ }
++ if (t->state != STATE_OK) {
++ dev_err(t->dev, "ERR:[0x%p] no-0x%x state: %s\n",
++ t, t->task_no, state_msg[t->state].msg);
++ }
++
++ split_child = need_split(t) && t->parent;
++ if (split_child) {
++ lock = &t->parent->split_lock;
++ mutex_lock(lock);
++ t->split_done = 1;
++ mutex_unlock(lock);
++ wake_up(&t->parent->split_waitq);
++ }
++
++ return;
++}
++
++static void wait_split_task_complete(struct ipu_task_entry *parent,
++ struct ipu_split_task *sp_task, uint32_t size)
++{
++ struct ipu_task_entry *tsk = NULL;
++ int ret = 0, rc;
++ int j, idx = -1;
++ unsigned long flags;
++ struct mutex *lock = &parent->split_lock;
++ int k, busy_vf, busy_pp;
++ struct ipu_soc *ipu;
++ DECLARE_PERF_VAR;
++
++ for (j = 0; j < size; j++) {
++ rc = wait_event_timeout(
++ parent->split_waitq,
++ sp_task_check_done(sp_task, parent, size, &idx),
++ msecs_to_jiffies(parent->timeout - DEF_DELAY_MS));
++ if (!rc) {
++ dev_err(parent->dev,
++ "ERR:[0x%p] no-0x%x, split_task timeout,j:%d,"
++ "size:%d.\n",
++ parent, parent->task_no, j, size);
++ ret = -ETIMEDOUT;
++ goto out;
++ } else {
++ if (idx < 0) {
++ dev_err(parent->dev,
++ "ERR:[0x%p] no-0x%x, invalid task idx:%d\n",
++ parent, parent->task_no, idx);
++ continue;
++ }
++ tsk = sp_task[idx].child_task;
++ mutex_lock(lock);
++ if (!tsk->split_done || !tsk->ipu)
++ dev_err(tsk->dev,
++ "ERR:no-0x%x,split not done:%d/null ipu:0x%p\n",
++ tsk->task_no, tsk->split_done, tsk->ipu);
++ tsk->split_done = 0;
++ mutex_unlock(lock);
++
++ dev_dbg(tsk->dev,
++ "[0x%p] no-0x%x sp_tsk[%d] done,state:%d.\n",
++ tsk, tsk->task_no, idx, tsk->state);
++ #ifdef DBG_IPU_PERF
++ CHECK_PERF(&tsk->ts_rel);
++ PRINT_TASK_STATISTICS;
++ #endif
++ }
++ }
++
++out:
++ if (ret == -ETIMEDOUT) {
++ /* debug */
++ for (k = 0; k < max_ipu_no; k++) {
++ ipu = ipu_get_soc(k);
++ if (IS_ERR(ipu)) {
++ dev_err(parent->dev, "no:0x%x, null ipu:%d\n",
++ parent->task_no, k);
++ } else {
++ busy_vf = ic_vf_pp_is_busy(ipu, true);
++ busy_pp = ic_vf_pp_is_busy(ipu, false);
++ dev_err(parent->dev,
++ "ERR:ipu[%d] busy_vf:%d, busy_pp:%d.\n",
++ k, busy_vf, busy_pp);
++ }
++ }
++ for (k = 0; k < size; k++) {
++ tsk = sp_task[k].child_task;
++ if (!tsk)
++ continue;
++ dev_err(parent->dev,
++ "ERR: sp_task[%d][0x%p] no-0x%x done:%d,"
++ "state:%s,on_list:%d, ipu:0x%p,timeout!\n",
++ k, tsk, tsk->task_no, tsk->split_done,
++ state_msg[tsk->state].msg, tsk->task_in_list,
++ tsk->ipu);
++ }
++ }
++
++ for (j = 0; j < size; j++) {
++ tsk = sp_task[j].child_task;
++ if (!tsk)
++ continue;
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ dev_dbg(tsk->dev,
++ "[0x%p] no-0x%x,id:%d sp_tsk timeout list_del.\n",
++ tsk, tsk->task_no, tsk->task_id);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++ if (!tsk->ipu)
++ continue;
++ if (tsk->state != STATE_OK) {
++ dev_err(tsk->dev,
++ "ERR:[0x%p] no-0x%x,id:%d, sp_tsk state: %s\n",
++ tsk, tsk->task_no, tsk->task_id,
++ state_msg[tsk->state].msg);
++ }
++ kref_put(&tsk->refcount, task_mem_free);
++ }
++
++ kfree(parent->vditmpbuf[0]);
++ kfree(parent->vditmpbuf[1]);
++
++ if (ret < 0)
++ parent->state = STATE_TIMEOUT;
++ else
++ parent->state = STATE_OK;
++ return;
++}
++
++static inline int find_task(struct ipu_task_entry **t, int thread_id)
++{
++ int found;
++ unsigned long flags;
++ struct ipu_task_entry *tsk;
++ struct list_head *task_list = &ipu_task_list;
++
++ *t = NULL;
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ found = !list_empty(task_list);
++ if (found) {
++ tsk = list_first_entry(task_list, struct ipu_task_entry, node);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ *t = tsk;
++ kref_get(&tsk->refcount);
++ dev_dbg(tsk->dev,
++ "thread_id:%d,[0x%p] task_no:0x%x,mode:0x%x list_del\n",
++ thread_id, tsk, tsk->task_no, tsk->set.mode);
++ } else
++ dev_err(tsk->dev,
++ "thread_id:%d,task_no:0x%x,mode:0x%x not on list_del\n",
++ thread_id, tsk->task_no, tsk->set.mode);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++
++ return found;
++}
++
++static int ipu_task_thread(void *argv)
++{
++ struct ipu_task_entry *tsk;
++ struct ipu_task_entry *sp_tsk0;
++ struct ipu_split_task sp_task[4];
++ /* priority lower than irq_thread */
++ const struct sched_param param = {
++ .sched_priority = MAX_USER_RT_PRIO/2 - 1,
++ };
++ int ret;
++ int curr_thread_id;
++ uint32_t size;
++ unsigned long flags;
++ unsigned int cpu;
++ struct cpumask cpu_mask;
++ struct ipu_thread_data *data = (struct ipu_thread_data *)argv;
++
++ thread_id++;
++ curr_thread_id = thread_id;
++ sched_setscheduler(current, SCHED_FIFO, &param);
++
++ if (!data->is_vdoa) {
++ cpu = cpumask_first(cpu_online_mask);
++ cpumask_set_cpu(cpu, &cpu_mask);
++ ret = sched_setaffinity(data->ipu->thread[data->id]->pid,
++ &cpu_mask);
++ if (ret < 0) {
++ pr_err("%s: sched_setaffinity fail:%d.\n", __func__, ret);
++ }
++ pr_debug("%s: sched_setaffinity cpu:%d.\n", __func__, cpu);
++ }
++
++ while (!kthread_should_stop()) {
++ int split_fail = 0;
++ int split_parent;
++ int split_child;
++
++ wait_event_interruptible(thread_waitq, find_task(&tsk, curr_thread_id));
++
++ if (!tsk) {
++ pr_err("thread:%d can not find task.\n",
++ curr_thread_id);
++ continue;
++ }
++
++ /* note: other threads run split child task */
++ split_parent = need_split(tsk) && !tsk->parent;
++ split_child = need_split(tsk) && tsk->parent;
++ if (split_parent) {
++ if ((tsk->set.split_mode == RL_SPLIT) ||
++ (tsk->set.split_mode == UD_SPLIT))
++ size = 2;
++ else
++ size = 4;
++ ret = queue_split_task(tsk, sp_task, size);
++ if (ret < 0) {
++ split_fail = 1;
++ } else {
++ struct list_head *pos;
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++
++ sp_tsk0 = list_first_entry(&tsk->split_list,
++ struct ipu_task_entry, node);
++ list_del(&sp_tsk0->node);
++
++ list_for_each(pos, &tsk->split_list) {
++ struct ipu_task_entry *tmp;
++
++ tmp = list_entry(pos,
++ struct ipu_task_entry, node);
++ tmp->task_in_list = 1;
++ dev_dbg(tmp->dev,
++ "[0x%p] no-0x%x,id:%d sp_tsk "
++ "add_to_list.\n", tmp,
++ tmp->task_no, tmp->task_id);
++ }
++ /* add to global list */
++ list_splice(&tsk->split_list, &ipu_task_list);
++
++ spin_unlock_irqrestore(&ipu_task_list_lock,
++ flags);
++ /* let the parent thread do the first sp_task */
++ /* FIXME: ensure the correct sequence for split
++ 4size: 5/6->9/a*/
++ if (!sp_tsk0)
++ dev_err(tsk->dev,
++ "ERR: no-0x%x,can not get split_tsk0\n",
++ tsk->task_no);
++ wake_up_interruptible(&thread_waitq);
++ get_res_do_task(sp_tsk0);
++ dev_dbg(sp_tsk0->dev,
++ "thread:%d complete tsk no:0x%x.\n",
++ curr_thread_id, sp_tsk0->task_no);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0) {
++ wake_up(&res_waitq);
++ dev_dbg(sp_tsk0->dev,
++ "sp_tsk0 sche thread:%d no:0x%x,"
++ "req_cnt:%d\n", curr_thread_id,
++ sp_tsk0->task_no, ret);
++ /* For other threads to get_res */
++ schedule();
++ }
++ }
++ } else
++ get_res_do_task(tsk);
++
++ /* wait for all 4 sp_task finished here or timeout
++ and then release all resources */
++ if (split_parent && !split_fail)
++ wait_split_task_complete(tsk, sp_task, size);
++
++ if (!split_child) {
++ atomic_inc(&tsk->done);
++ wake_up(&tsk->task_waitq);
++ }
++
++ dev_dbg(tsk->dev, "thread:%d complete tsk no:0x%x-[0x%p].\n",
++ curr_thread_id, tsk->task_no, tsk);
++ ret = atomic_read(&req_cnt);
++ if (ret > 0) {
++ wake_up(&res_waitq);
++ dev_dbg(tsk->dev, "sche thread:%d no:0x%x,req_cnt:%d\n",
++ curr_thread_id, tsk->task_no, ret);
++ /* note: give cpu to other threads to get_res */
++ schedule();
++ }
++
++ kref_put(&tsk->refcount, task_mem_free);
++ }
++
++ pr_info("ERR %s exit.\n", __func__);
++ return 0;
++}
++
++int ipu_check_task(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++ int ret = 0;
++
++ tsk = create_task_entry(task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ ret = check_task(tsk);
++
++ task->input = tsk->input;
++ task->output = tsk->output;
++ task->overlay = tsk->overlay;
++ dump_task_info(tsk);
++
++ kref_put(&tsk->refcount, task_mem_free);
++ if (ret != 0)
++ pr_debug("%s ret:%d.\n", __func__, ret);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(ipu_check_task);
++
++int ipu_queue_task(struct ipu_task *task)
++{
++ struct ipu_task_entry *tsk;
++ unsigned long flags;
++ int ret;
++ u32 tmp_task_no;
++ DECLARE_PERF_VAR;
++
++ tsk = create_task_entry(task);
++ if (IS_ERR(tsk))
++ return PTR_ERR(tsk);
++
++ CHECK_PERF(&tsk->ts_queue);
++ ret = prepare_task(tsk);
++ if (ret < 0)
++ goto done;
++
++ if (need_split(tsk)) {
++ CHECK_PERF(&tsk->ts_dotask);
++ CHECK_PERF(&tsk->ts_waitirq);
++ CHECK_PERF(&tsk->ts_inirq);
++ CHECK_PERF(&tsk->ts_wakeup);
++ }
++
++ /* task_no last four bits for split task type*/
++ tmp_task_no = atomic_inc_return(&frame_no);
++ tsk->task_no = tmp_task_no << 4;
++ init_waitqueue_head(&tsk->task_waitq);
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ list_add_tail(&tsk->node, &ipu_task_list);
++ tsk->task_in_list = 1;
++ dev_dbg(tsk->dev, "[0x%p,no-0x%x] list_add_tail\n", tsk, tsk->task_no);
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++ wake_up_interruptible(&thread_waitq);
++
++ ret = wait_event_timeout(tsk->task_waitq, atomic_read(&tsk->done),
++ msecs_to_jiffies(tsk->timeout));
++ if (0 == ret) {
++ /* note: the timeout should larger than the internal timeout!*/
++ ret = -ETIMEDOUT;
++ dev_err(tsk->dev, "ERR: [0x%p] no-0x%x, timeout:%dms!\n",
++ tsk, tsk->task_no, tsk->timeout);
++ } else {
++ if (STATE_OK != tsk->state) {
++ dev_err(tsk->dev, "ERR: [0x%p] no-0x%x,state %d: %s\n",
++ tsk, tsk->task_no, tsk->state,
++ state_msg[tsk->state].msg);
++ ret = -ECANCELED;
++ } else
++ ret = 0;
++ }
++
++ spin_lock_irqsave(&ipu_task_list_lock, flags);
++ if (tsk->task_in_list) {
++ list_del(&tsk->node);
++ tsk->task_in_list = 0;
++ dev_dbg(tsk->dev, "[0x%p] no:0x%x list_del\n",
++ tsk, tsk->task_no);
++ }
++ spin_unlock_irqrestore(&ipu_task_list_lock, flags);
++
++#ifdef DBG_IPU_PERF
++ CHECK_PERF(&tsk->ts_rel);
++ PRINT_TASK_STATISTICS;
++ if (ts_frame_avg == 0)
++ ts_frame_avg = ts_frame.tv_nsec / NSEC_PER_USEC +
++ ts_frame.tv_sec * USEC_PER_SEC;
++ else
++ ts_frame_avg = (ts_frame_avg + ts_frame.tv_nsec / NSEC_PER_USEC
++ + ts_frame.tv_sec * USEC_PER_SEC)/2;
++ if (timespec_compare(&ts_frame, &ts_frame_max) > 0)
++ ts_frame_max = ts_frame;
++
++ atomic_inc(&frame_cnt);
++
++ if ((atomic_read(&frame_cnt) % 1000) == 0)
++ pr_debug("ipu_dev: max frame time:%ldus, avg frame time:%dus,"
++ "frame_cnt:%d\n", ts_frame_max.tv_nsec / NSEC_PER_USEC
++ + ts_frame_max.tv_sec * USEC_PER_SEC,
++ ts_frame_avg, atomic_read(&frame_cnt));
++#endif
++done:
++ if (ret < 0)
++ dev_err(tsk->dev, "ERR: no-0x%x,ipu_queue_task err:%d\n",
++ tsk->task_no, ret);
++
++ kref_put(&tsk->refcount, task_mem_free);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(ipu_queue_task);
++
++static int mxc_ipu_open(struct inode *inode, struct file *file)
++{
++ file->private_data = (void *)atomic_inc_return(&file_index);
++ return 0;
++}
++
++static long mxc_ipu_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ int ret = 0;
++
++ switch (cmd) {
++ case IPU_CHECK_TASK:
++ {
++ struct ipu_task task;
++
++ if (copy_from_user
++ (&task, (struct ipu_task *) arg,
++ sizeof(struct ipu_task)))
++ return -EFAULT;
++ ret = ipu_check_task(&task);
++ if (copy_to_user((struct ipu_task *) arg,
++ &task, sizeof(struct ipu_task)))
++ return -EFAULT;
++ break;
++ }
++ case IPU_QUEUE_TASK:
++ {
++ struct ipu_task task;
++
++ if (copy_from_user
++ (&task, (struct ipu_task *) arg,
++ sizeof(struct ipu_task)))
++ return -EFAULT;
++ ret = ipu_queue_task(&task);
++ break;
++ }
++ case IPU_ALLOC:
++ {
++ int size;
++ struct ipu_alloc_list *mem;
++
++ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
++ if (mem == NULL)
++ return -ENOMEM;
++
++ if (get_user(size, argp))
++ return -EFAULT;
++
++ mem->size = PAGE_ALIGN(size);
++
++ mem->cpu_addr = dma_alloc_coherent(ipu_dev, size,
++ &mem->phy_addr,
++ GFP_DMA | GFP_KERNEL);
++ if (mem->cpu_addr == NULL) {
++ kfree(mem);
++ return -ENOMEM;
++ }
++ mem->file_index = file->private_data;
++ mutex_lock(&ipu_alloc_lock);
++ list_add(&mem->list, &ipu_alloc_list);
++ mutex_unlock(&ipu_alloc_lock);
++
++ dev_dbg(ipu_dev, "allocated %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ if (put_user(mem->phy_addr, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case IPU_FREE:
++ {
++ unsigned long offset;
++ struct ipu_alloc_list *mem;
++
++ if (get_user(offset, argp))
++ return -EFAULT;
++
++ ret = -EINVAL;
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry(mem, &ipu_alloc_list, list) {
++ if (mem->phy_addr == offset) {
++ list_del(&mem->list);
++ dma_free_coherent(ipu_dev,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ kfree(mem);
++ ret = 0;
++ break;
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ if (0 == ret)
++ dev_dbg(ipu_dev, "free %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ break;
++ }
++ default:
++ break;
++ }
++ return ret;
++}
++
++static int mxc_ipu_mmap(struct file *file, struct vm_area_struct *vma)
++{
++ bool found = false;
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++ struct ipu_alloc_list *mem;
++
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry(mem, &ipu_alloc_list, list) {
++ if (offset == mem->phy_addr) {
++ found = true;
++ len = mem->size;
++ break;
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ if (!found)
++ return -EINVAL;
++
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start,
++ vma->vm_page_prot)) {
++ printk(KERN_ERR
++ "mmap failed!\n");
++ return -ENOBUFS;
++ }
++ return 0;
++}
++
++static int mxc_ipu_release(struct inode *inode, struct file *file)
++{
++ struct ipu_alloc_list *mem;
++ struct ipu_alloc_list *n;
++
++ mutex_lock(&ipu_alloc_lock);
++ list_for_each_entry_safe(mem, n, &ipu_alloc_list, list) {
++ if ((mem->cpu_addr != 0) &&
++ (file->private_data == mem->file_index)) {
++ list_del(&mem->list);
++ dma_free_coherent(ipu_dev,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ dev_dbg(ipu_dev, "rel-free %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++ kfree(mem);
++ }
++ }
++ mutex_unlock(&ipu_alloc_lock);
++ atomic_dec(&file_index);
++
++ return 0;
++}
++
++static struct file_operations mxc_ipu_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_ipu_open,
++ .mmap = mxc_ipu_mmap,
++ .release = mxc_ipu_release,
++ .unlocked_ioctl = mxc_ipu_ioctl,
++};
++
++int register_ipu_device(struct ipu_soc *ipu, int id)
++{
++ int ret = 0;
++ static int idx;
++ static struct ipu_thread_data thread_data[5];
++
++ if (!major) {
++ major = register_chrdev(0, "mxc_ipu", &mxc_ipu_fops);
++ if (major < 0) {
++ printk(KERN_ERR "Unable to register mxc_ipu as a char device\n");
++ ret = major;
++ goto register_cdev_fail;
++ }
++
++ ipu_class = class_create(THIS_MODULE, "mxc_ipu");
++ if (IS_ERR(ipu_class)) {
++ ret = PTR_ERR(ipu_class);
++ goto ipu_class_fail;
++ }
++
++ ipu_dev = device_create(ipu_class, NULL, MKDEV(major, 0),
++ NULL, "mxc_ipu");
++ if (IS_ERR(ipu_dev)) {
++ ret = PTR_ERR(ipu_dev);
++ goto dev_create_fail;
++ }
++ ipu_dev->dma_mask = kmalloc(sizeof(*ipu_dev->dma_mask), GFP_KERNEL);
++ *ipu_dev->dma_mask = DMA_BIT_MASK(32);
++ ipu_dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ mutex_init(&ipu_ch_tbl.lock);
++ }
++ max_ipu_no = ++id;
++ ipu->rot_dma[0].size = 0;
++ ipu->rot_dma[1].size = 0;
++
++ thread_data[idx].ipu = ipu;
++ thread_data[idx].id = 0;
++ thread_data[idx].is_vdoa = 0;
++ ipu->thread[0] = kthread_run(ipu_task_thread, &thread_data[idx++],
++ "ipu%d_task", id);
++ if (IS_ERR(ipu->thread[0])) {
++ ret = PTR_ERR(ipu->thread[0]);
++ goto kthread0_fail;
++ }
++
++ thread_data[idx].ipu = ipu;
++ thread_data[idx].id = 1;
++ thread_data[idx].is_vdoa = 0;
++ ipu->thread[1] = kthread_run(ipu_task_thread, &thread_data[idx++],
++ "ipu%d_task", id);
++ if (IS_ERR(ipu->thread[1])) {
++ ret = PTR_ERR(ipu->thread[1]);
++ goto kthread1_fail;
++ }
++
++
++ return ret;
++
++kthread1_fail:
++ kthread_stop(ipu->thread[0]);
++kthread0_fail:
++ if (id == 0)
++ device_destroy(ipu_class, MKDEV(major, 0));
++dev_create_fail:
++ if (id == 0) {
++ class_destroy(ipu_class);
++ }
++ipu_class_fail:
++ if (id == 0)
++ unregister_chrdev(major, "mxc_ipu");
++register_cdev_fail:
++ return ret;
++}
++
++void unregister_ipu_device(struct ipu_soc *ipu, int id)
++{
++ int i;
++
++ kthread_stop(ipu->thread[0]);
++ kthread_stop(ipu->thread[1]);
++ for (i = 0; i < 2; i++) {
++ if (ipu->rot_dma[i].vaddr)
++ dma_free_coherent(ipu_dev,
++ ipu->rot_dma[i].size,
++ ipu->rot_dma[i].vaddr,
++ ipu->rot_dma[i].paddr);
++ }
++
++ if (major) {
++ device_destroy(ipu_class, MKDEV(major, 0));
++ class_destroy(ipu_class);
++ unregister_chrdev(major, "mxc_ipu");
++ major = 0;
++ }
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_disp.c linux-3.14.72/drivers/mxc/ipu3/ipu_disp.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_disp.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_disp.c 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,1956 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_disp.c
++ *
++ * @brief IPU display submodule API functions
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/errno.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++
++#include <asm/atomic.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++struct dp_csc_param_t {
++ int mode;
++ void *coeff;
++};
++
++#define SYNC_WAVE 0
++#define NULL_WAVE (-1)
++#define ASYNC_SER_WAVE 6
++
++/* DC display ID assignments */
++#define DC_DISP_ID_SYNC(di) (di)
++#define DC_DISP_ID_SERIAL 2
++#define DC_DISP_ID_ASYNC 3
++
++int dmfc_type_setup;
++
++void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first)
++{
++ u32 dmfc_wr_chan, dmfc_dp_chan;
++
++ if (first) {
++ if (dmfc_type_setup > dmfc_type)
++ dmfc_type = dmfc_type_setup;
++ else
++ dmfc_type_setup = dmfc_type;
++
++ /* disable DMFC-IC channel*/
++ ipu_dmfc_write(ipu, 0x2, DMFC_IC_CTRL);
++ } else if (dmfc_type_setup >= DMFC_HIGH_RESOLUTION_DC) {
++ dev_dbg(ipu->dev, "DMFC high resolution has set, will not change\n");
++ return;
++ } else
++ dmfc_type_setup = dmfc_type;
++
++ if (dmfc_type == DMFC_HIGH_RESOLUTION_DC) {
++ /* 1 - segment 0~3;
++ * 5B - segement 4, 5;
++ * 5F - segement 6, 7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC DC HIGH RESOLUTION: 1(0~3), 5B(4,5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000088;
++ dmfc_dp_chan = 0x00009694;
++ ipu->dmfc_size_28 = 256*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 128*4;
++ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_DP) {
++ /* 1 - segment 0, 1;
++ * 5B - segement 2~5;
++ * 5F - segement 6,7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC DP HIGH RESOLUTION: 1(0,1), 5B(2~5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000090;
++ dmfc_dp_chan = 0x0000968a;
++ ipu->dmfc_size_28 = 128*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 256*4;
++ } else if (dmfc_type == DMFC_HIGH_RESOLUTION_ONLY_DP) {
++ /* 5B - segement 0~3;
++ * 5F - segement 4~7;
++ * 1, 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC ONLY-DP HIGH RESOLUTION: 5B(0~3), 5F(4~7)\n");
++ dmfc_wr_chan = 0x00000000;
++ dmfc_dp_chan = 0x00008c88;
++ ipu->dmfc_size_28 = 0;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 256*4;
++ ipu->dmfc_size_23 = 256*4;
++ } else {
++ /* 1 - segment 0, 1;
++ * 5B - segement 4, 5;
++ * 5F - segement 6, 7;
++ * 1C, 2C and 6B, 6F unused;
++ */
++ dev_info(ipu->dev, "IPU DMFC NORMAL mode: 1(0~1), 5B(4,5), 5F(6,7)\n");
++ dmfc_wr_chan = 0x00000090;
++ dmfc_dp_chan = 0x00009694;
++ ipu->dmfc_size_28 = 128*4;
++ ipu->dmfc_size_29 = 0;
++ ipu->dmfc_size_24 = 0;
++ ipu->dmfc_size_27 = 128*4;
++ ipu->dmfc_size_23 = 128*4;
++ }
++ ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
++ ipu_dmfc_write(ipu, 0x202020F6, DMFC_WR_CHAN_DEF);
++ ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
++ /* Enable chan 5 watermark set at 5 bursts and clear at 7 bursts */
++ ipu_dmfc_write(ipu, 0x2020F6F6, DMFC_DP_CHAN_DEF);
++}
++
++static int __init dmfc_setup(char *options)
++{
++ get_option(&options, &dmfc_type_setup);
++ if (dmfc_type_setup > DMFC_HIGH_RESOLUTION_ONLY_DP)
++ dmfc_type_setup = DMFC_HIGH_RESOLUTION_ONLY_DP;
++ return 1;
++}
++__setup("dmfc=", dmfc_setup);
++
++void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width)
++{
++ u32 dmfc_gen1 = ipu_dmfc_read(ipu, DMFC_GENERAL1);
++
++ if (width >= HIGH_RESOLUTION_WIDTH) {
++ if (dma_chan == 23)
++ _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DP, 0);
++ else if (dma_chan == 28)
++ _ipu_dmfc_init(ipu, DMFC_HIGH_RESOLUTION_DC, 0);
++ }
++
++ if (dma_chan == 23) { /*5B*/
++ if (ipu->dmfc_size_23/width > 3)
++ dmfc_gen1 |= 1UL << 20;
++ else
++ dmfc_gen1 &= ~(1UL << 20);
++ } else if (dma_chan == 24) { /*6B*/
++ if (ipu->dmfc_size_24/width > 1)
++ dmfc_gen1 |= 1UL << 22;
++ else
++ dmfc_gen1 &= ~(1UL << 22);
++ } else if (dma_chan == 27) { /*5F*/
++ if (ipu->dmfc_size_27/width > 2)
++ dmfc_gen1 |= 1UL << 21;
++ else
++ dmfc_gen1 &= ~(1UL << 21);
++ } else if (dma_chan == 28) { /*1*/
++ if (ipu->dmfc_size_28/width > 2)
++ dmfc_gen1 |= 1UL << 16;
++ else
++ dmfc_gen1 &= ~(1UL << 16);
++ } else if (dma_chan == 29) { /*6F*/
++ if (ipu->dmfc_size_29/width > 1)
++ dmfc_gen1 |= 1UL << 23;
++ else
++ dmfc_gen1 &= ~(1UL << 23);
++ }
++
++ ipu_dmfc_write(ipu, dmfc_gen1, DMFC_GENERAL1);
++}
++
++void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size)
++{
++ u32 dmfc_wr_chan = ipu_dmfc_read(ipu, DMFC_WR_CHAN);
++ u32 dmfc_dp_chan = ipu_dmfc_read(ipu, DMFC_DP_CHAN);
++ int dmfc_bs = 0;
++
++ switch (burst_size) {
++ case 64:
++ dmfc_bs = 0x40;
++ break;
++ case 32:
++ case 20:
++ dmfc_bs = 0x80;
++ break;
++ case 16:
++ dmfc_bs = 0xc0;
++ break;
++ default:
++ dev_warn(ipu->dev, "Unsupported burst size %d\n",
++ burst_size);
++ return;
++ }
++
++ if (dma_chan == 23) { /*5B*/
++ dmfc_dp_chan &= ~(0xc0);
++ dmfc_dp_chan |= dmfc_bs;
++ } else if (dma_chan == 27) { /*5F*/
++ dmfc_dp_chan &= ~(0xc000);
++ dmfc_dp_chan |= (dmfc_bs << 8);
++ } else if (dma_chan == 28) { /*1*/
++ dmfc_wr_chan &= ~(0xc0);
++ dmfc_wr_chan |= dmfc_bs;
++ }
++
++ ipu_dmfc_write(ipu, dmfc_wr_chan, DMFC_WR_CHAN);
++ ipu_dmfc_write(ipu, dmfc_dp_chan, DMFC_DP_CHAN);
++}
++
++static void _ipu_di_data_wave_config(struct ipu_soc *ipu,
++ int di, int wave_gen,
++ int access_size, int component_size)
++{
++ u32 reg;
++ reg = (access_size << DI_DW_GEN_ACCESS_SIZE_OFFSET) |
++ (component_size << DI_DW_GEN_COMPONENT_SIZE_OFFSET);
++ ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
++}
++
++static void _ipu_di_data_pin_config(struct ipu_soc *ipu,
++ int di, int wave_gen, int di_pin, int set,
++ int up, int down)
++{
++ u32 reg;
++
++ reg = ipu_di_read(ipu, di, DI_DW_GEN(wave_gen));
++ reg &= ~(0x3 << (di_pin * 2));
++ reg |= set << (di_pin * 2);
++ ipu_di_write(ipu, di, reg, DI_DW_GEN(wave_gen));
++
++ ipu_di_write(ipu, di, (down << 16) | up, DI_DW_SET(wave_gen, set));
++}
++
++static void _ipu_di_sync_config(struct ipu_soc *ipu,
++ int di, int wave_gen,
++ int run_count, int run_src,
++ int offset_count, int offset_src,
++ int repeat_count, int cnt_clr_src,
++ int cnt_polarity_gen_en,
++ int cnt_polarity_clr_src,
++ int cnt_polarity_trigger_src,
++ int cnt_up, int cnt_down)
++{
++ u32 reg;
++
++ if ((run_count >= 0x1000) || (offset_count >= 0x1000) || (repeat_count >= 0x1000) ||
++ (cnt_up >= 0x400) || (cnt_down >= 0x400)) {
++ dev_warn(ipu->dev, "DI%d counters out of range.\n", di);
++ return;
++ }
++
++ reg = (run_count << 19) | (++run_src << 16) |
++ (offset_count << 3) | ++offset_src;
++ ipu_di_write(ipu, di, reg, DI_SW_GEN0(wave_gen));
++ reg = (cnt_polarity_gen_en << 29) | (++cnt_clr_src << 25) |
++ (++cnt_polarity_trigger_src << 12) | (++cnt_polarity_clr_src << 9);
++ reg |= (cnt_down << 16) | cnt_up;
++ if (repeat_count == 0) {
++ /* Enable auto reload */
++ reg |= 0x10000000;
++ }
++ ipu_di_write(ipu, di, reg, DI_SW_GEN1(wave_gen));
++ reg = ipu_di_read(ipu, di, DI_STP_REP(wave_gen));
++ reg &= ~(0xFFFF << (16 * ((wave_gen - 1) & 0x1)));
++ reg |= repeat_count << (16 * ((wave_gen - 1) & 0x1));
++ ipu_di_write(ipu, di, reg, DI_STP_REP(wave_gen));
++}
++
++static void _ipu_dc_map_link(struct ipu_soc *ipu,
++ int current_map,
++ int base_map_0, int buf_num_0,
++ int base_map_1, int buf_num_1,
++ int base_map_2, int buf_num_2)
++{
++ int ptr_0 = base_map_0 * 3 + buf_num_0;
++ int ptr_1 = base_map_1 * 3 + buf_num_1;
++ int ptr_2 = base_map_2 * 3 + buf_num_2;
++ int ptr;
++ u32 reg;
++ ptr = (ptr_2 << 10) + (ptr_1 << 5) + ptr_0;
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(current_map));
++ reg &= ~(0x1F << ((16 * (current_map & 0x1))));
++ reg |= ptr << ((16 * (current_map & 0x1)));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(current_map));
++}
++
++static void _ipu_dc_map_config(struct ipu_soc *ipu,
++ int map, int byte_num, int offset, int mask)
++{
++ int ptr = map * 3 + byte_num;
++ u32 reg;
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_VAL(ptr));
++ reg &= ~(0xFFFF << (16 * (ptr & 0x1)));
++ reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_VAL(ptr));
++
++ reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
++ reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte_num)));
++ reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
++ ipu_dc_write(ipu, reg, DC_MAP_CONF_PTR(map));
++}
++
++static void _ipu_dc_map_clear(struct ipu_soc *ipu, int map)
++{
++ u32 reg = ipu_dc_read(ipu, DC_MAP_CONF_PTR(map));
++ ipu_dc_write(ipu, reg & ~(0xFFFF << (16 * (map & 0x1))),
++ DC_MAP_CONF_PTR(map));
++}
++
++static void _ipu_dc_write_tmpl(struct ipu_soc *ipu,
++ int word, u32 opcode, u32 operand, int map,
++ int wave, int glue, int sync, int stop)
++{
++ u32 reg;
++
++ if (opcode == WRG) {
++ reg = sync;
++ reg |= (glue << 4);
++ reg |= (++wave << 11);
++ reg |= ((operand & 0x1FFFF) << 15);
++ ipu_dc_tmpl_write(ipu, reg, word * 8);
++
++ reg = (operand >> 17);
++ reg |= opcode << 7;
++ reg |= (stop << 9);
++ ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
++ } else {
++ reg = sync;
++ reg |= (glue << 4);
++ reg |= (++wave << 11);
++ reg |= (++map << 15);
++ reg |= (operand << 20) & 0xFFF00000;
++ ipu_dc_tmpl_write(ipu, reg, word * 8);
++
++ reg = (operand >> 12);
++ reg |= opcode << 4;
++ reg |= (stop << 9);
++ ipu_dc_tmpl_write(ipu, reg, word * 8 + 4);
++ }
++}
++
++static void _ipu_dc_link_event(struct ipu_soc *ipu,
++ int chan, int event, int addr, int priority)
++{
++ u32 reg;
++ u32 address_shift;
++ if (event < DC_EVEN_UGDE0) {
++ reg = ipu_dc_read(ipu, DC_RL_CH(chan, event));
++ reg &= ~(0xFFFF << (16 * (event & 0x1)));
++ reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
++ ipu_dc_write(ipu, reg, DC_RL_CH(chan, event));
++ } else {
++ reg = ipu_dc_read(ipu, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
++ if ((event - DC_EVEN_UGDE0) & 0x1) {
++ reg &= ~(0x2FF << 16);
++ reg |= (addr << 16);
++ reg |= priority ? (2 << 24) : 0x0;
++ } else {
++ reg &= ~0xFC00FFFF;
++ if (priority)
++ chan = (chan >> 1) +
++ ((((chan & 0x1) + ((chan & 0x2) >> 1))) | (chan >> 3));
++ else
++ chan = 0x7;
++ address_shift = ((event - DC_EVEN_UGDE0) >> 1) ? 7 : 8;
++ reg |= (addr << address_shift) | (priority << 3) | chan;
++ }
++ ipu_dc_write(ipu, reg, DC_UGDE_0((event - DC_EVEN_UGDE0) / 2));
++ }
++}
++
++/* Y = R * 1.200 + G * 2.343 + B * .453 + 0.250;
++ U = R * -.672 + G * -1.328 + B * 2.000 + 512.250.;
++ V = R * 2.000 + G * -1.672 + B * -.328 + 512.250.;*/
++static const int rgb2ycbcr_coeff[5][3] = {
++ {0x4D, 0x96, 0x1D},
++ {-0x2B, -0x55, 0x80},
++ {0x80, -0x6B, -0x15},
++ {0x0000, 0x0200, 0x0200}, /* B0, B1, B2 */
++ {0x2, 0x2, 0x2}, /* S0, S1, S2 */
++};
++
++/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
++ G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
++ B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
++static const int ycbcr2rgb_coeff[5][3] = {
++ {0x095, 0x000, 0x0CC},
++ {0x095, 0x3CE, 0x398},
++ {0x095, 0x0FF, 0x000},
++ {0x3E42, 0x010A, 0x3DD6}, /*B0,B1,B2 */
++ {0x1, 0x1, 0x1}, /*S0,S1,S2 */
++};
++
++#define mask_a(a) ((u32)(a) & 0x3FF)
++#define mask_b(b) ((u32)(b) & 0x3FFF)
++
++/* Pls keep S0, S1 and S2 as 0x2 by using this convertion */
++static int _rgb_to_yuv(int n, int red, int green, int blue)
++{
++ int c;
++ c = red * rgb2ycbcr_coeff[n][0];
++ c += green * rgb2ycbcr_coeff[n][1];
++ c += blue * rgb2ycbcr_coeff[n][2];
++ c /= 16;
++ c += rgb2ycbcr_coeff[3][n] * 4;
++ c += 8;
++ c /= 16;
++ if (c < 0)
++ c = 0;
++ if (c > 255)
++ c = 255;
++ return c;
++}
++
++/*
++ * Row is for BG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
++ * Column is for FG: RGB2YUV YUV2RGB RGB2RGB YUV2YUV CSC_NONE
++ */
++static struct dp_csc_param_t dp_csc_array[CSC_NUM][CSC_NUM] = {
++{{DP_COM_CONF_CSC_DEF_BOTH, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_BG, &rgb2ycbcr_coeff} },
++{{0, 0}, {DP_COM_CONF_CSC_DEF_BOTH, &ycbcr2rgb_coeff}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff}, {0, 0}, {DP_COM_CONF_CSC_DEF_BG, &ycbcr2rgb_coeff} },
++{{0, 0}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} },
++{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {0, 0}, {0, 0}, {0, 0}, {0, 0} },
++{{DP_COM_CONF_CSC_DEF_FG, &rgb2ycbcr_coeff}, {DP_COM_CONF_CSC_DEF_FG, &ycbcr2rgb_coeff}, {0, 0}, {0, 0}, {0, 0} }
++};
++
++void __ipu_dp_csc_setup(struct ipu_soc *ipu,
++ int dp, struct dp_csc_param_t dp_csc_param,
++ bool srm_mode_update)
++{
++ u32 reg;
++ const int (*coeff)[5][3];
++
++ if (dp_csc_param.mode >= 0) {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
++ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
++ reg |= dp_csc_param.mode;
++ ipu_dp_write(ipu, reg, DP_COM_CONF(dp));
++ }
++
++ coeff = dp_csc_param.coeff;
++
++ if (coeff) {
++ ipu_dp_write(ipu, mask_a((*coeff)[0][0]) |
++ (mask_a((*coeff)[0][1]) << 16), DP_CSC_A_0(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[0][2]) |
++ (mask_a((*coeff)[1][0]) << 16), DP_CSC_A_1(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[1][1]) |
++ (mask_a((*coeff)[1][2]) << 16), DP_CSC_A_2(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[2][0]) |
++ (mask_a((*coeff)[2][1]) << 16), DP_CSC_A_3(dp));
++ ipu_dp_write(ipu, mask_a((*coeff)[2][2]) |
++ (mask_b((*coeff)[3][0]) << 16) |
++ ((*coeff)[4][0] << 30), DP_CSC_0(dp));
++ ipu_dp_write(ipu, mask_b((*coeff)[3][1]) | ((*coeff)[4][1] << 14) |
++ (mask_b((*coeff)[3][2]) << 16) |
++ ((*coeff)[4][2] << 30), DP_CSC_1(dp));
++ }
++
++ if (srm_mode_update) {
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++}
++
++int _ipu_dp_init(struct ipu_soc *ipu,
++ ipu_channel_t channel, uint32_t in_pixel_fmt,
++ uint32_t out_pixel_fmt)
++{
++ int in_fmt, out_fmt;
++ int dp;
++ int partial = false;
++ uint32_t reg;
++
++ if (channel == MEM_FG_SYNC) {
++ dp = DP_SYNC;
++ partial = true;
++ } else if (channel == MEM_BG_SYNC) {
++ dp = DP_SYNC;
++ partial = false;
++ } else if (channel == MEM_BG_ASYNC0) {
++ dp = DP_ASYNC0;
++ partial = false;
++ } else {
++ return -EINVAL;
++ }
++
++ in_fmt = format_to_colorspace(in_pixel_fmt);
++ out_fmt = format_to_colorspace(out_pixel_fmt);
++
++ if (partial) {
++ if (in_fmt == RGB) {
++ if (out_fmt == RGB)
++ ipu->fg_csc_type = RGB2RGB;
++ else
++ ipu->fg_csc_type = RGB2YUV;
++ } else {
++ if (out_fmt == RGB)
++ ipu->fg_csc_type = YUV2RGB;
++ else
++ ipu->fg_csc_type = YUV2YUV;
++ }
++ } else {
++ if (in_fmt == RGB) {
++ if (out_fmt == RGB)
++ ipu->bg_csc_type = RGB2RGB;
++ else
++ ipu->bg_csc_type = RGB2YUV;
++ } else {
++ if (out_fmt == RGB)
++ ipu->bg_csc_type = YUV2RGB;
++ else
++ ipu->bg_csc_type = YUV2YUV;
++ }
++ }
++
++ /* Transform color key from rgb to yuv if CSC is enabled */
++ reg = ipu_dp_read(ipu, DP_COM_CONF(dp));
++ if (ipu->color_key_4rgb && (reg & DP_COM_CONF_GWCKE) &&
++ (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB)))) {
++ int red, green, blue;
++ int y, u, v;
++ uint32_t color_key = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFFFFFFL;
++
++ dev_dbg(ipu->dev, "_ipu_dp_init color key 0x%x need change to yuv fmt!\n", color_key);
++
++ red = (color_key >> 16) & 0xFF;
++ green = (color_key >> 8) & 0xFF;
++ blue = color_key & 0xFF;
++
++ y = _rgb_to_yuv(0, red, green, blue);
++ u = _rgb_to_yuv(1, red, green, blue);
++ v = _rgb_to_yuv(2, red, green, blue);
++ color_key = (y << 16) | (u << 8) | v;
++
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(dp)) & 0xFF000000L;
++ ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(dp));
++ ipu->color_key_4rgb = false;
++
++ dev_dbg(ipu->dev, "_ipu_dp_init color key change to yuv fmt 0x%x!\n", color_key);
++ }
++
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], true);
++
++ return 0;
++}
++
++void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int dp;
++ int partial = false;
++
++ if (channel == MEM_FG_SYNC) {
++ dp = DP_SYNC;
++ partial = true;
++ } else if (channel == MEM_BG_SYNC) {
++ dp = DP_SYNC;
++ partial = false;
++ } else if (channel == MEM_BG_ASYNC0) {
++ dp = DP_ASYNC0;
++ partial = false;
++ } else {
++ return;
++ }
++
++ if (partial)
++ ipu->fg_csc_type = CSC_NONE;
++ else
++ ipu->bg_csc_type = CSC_NONE;
++
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_array[ipu->bg_csc_type][ipu->fg_csc_type], false);
++}
++
++void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt)
++{
++ u32 reg = 0;
++
++ if ((dc_chan == 1) || (dc_chan == 5)) {
++ if (interlaced) {
++ if (di) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 1, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 1, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
++ }
++ } else {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
++ }
++ }
++ } else {
++ if (di) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 2, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 3, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 1, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 9, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 8, 5);
++ }
++ } else {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 5, 3);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 6, 2);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 12, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 10, 5);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 11, 5);
++ }
++ }
++ }
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
++
++ reg = 0x2;
++ reg |= DC_DISP_ID_SYNC(di) << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
++ reg |= di << 2;
++ if (interlaced)
++ reg |= DC_WR_CH_CONF_FIELD_MODE;
++ } else if ((dc_chan == 8) || (dc_chan == 9)) {
++ /* async channels */
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0x64, 1);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0x64, 1);
++
++ reg = 0x3;
++ reg |= DC_DISP_ID_SERIAL << DC_WR_CH_CONF_PROG_DISP_ID_OFFSET;
++ }
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ ipu_dc_write(ipu, 0x00000000, DC_WR_CH_ADDR(dc_chan));
++
++ ipu_dc_write(ipu, 0x00000084, DC_GEN);
++}
++
++void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan)
++{
++ if ((dc_chan == 1) || (dc_chan == 5)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NL, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOL, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOF, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_EOFIELD, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_ODD_UGDE1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVEN_UGDE1, 0, 0);
++ } else if ((dc_chan == 8) || (dc_chan == 9)) {
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_W_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_ADDR_R_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_CHAN_R_1, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_0, 0, 0);
++ _ipu_dc_link_event(ipu, dc_chan, DC_EVT_NEW_DATA_R_1, 0, 0);
++ }
++}
++
++int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ if (channel == MEM_DC_SYNC)
++ return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_1) &
++ DC_WR_CH_CONF_FIELD_MODE);
++ else if ((channel == MEM_BG_SYNC) || (channel == MEM_FG_SYNC))
++ return !!(ipu_dc_read(ipu, DC_WR_CH_CONF_5) &
++ DC_WR_CH_CONF_FIELD_MODE);
++ return 0;
++}
++
++void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ int di;
++ uint32_t reg;
++ uint32_t dc_chan;
++ int irq = 0;
++
++ if (channel == MEM_FG_SYNC)
++ irq = IPU_IRQ_DP_SF_END;
++ else if (channel == MEM_DC_SYNC)
++ dc_chan = 1;
++ else if (channel == MEM_BG_SYNC)
++ dc_chan = 5;
++ else
++ return;
++
++ if (channel == MEM_FG_SYNC) {
++ /* Enable FG channel */
++ reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_FG_EN, DP_COM_CONF(DP_SYNC));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ return;
++ } else if (channel == MEM_BG_SYNC) {
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++
++ di = ipu->dc_di_assignment[dc_chan];
++
++ /* Make sure other DC sync channel is not assigned same DI */
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(6 - dc_chan));
++ if ((di << 2) == (reg & DC_WR_CH_CONF_PROG_DI_ID)) {
++ reg &= ~DC_WR_CH_CONF_PROG_DI_ID;
++ reg |= di ? 0 : DC_WR_CH_CONF_PROG_DI_ID;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
++ }
++
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ reg |= 4 << DC_WR_CH_CONF_PROG_TYPE_OFFSET;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ clk_prepare_enable(ipu->pixel_clk[di]);
++}
++
++static irqreturn_t dc_irq_handler(int irq, void *dev_id)
++{
++ struct ipu_soc *ipu = dev_id;
++ struct completion *comp = &ipu->dc_comp;
++ uint32_t reg;
++ uint32_t dc_chan;
++
++ if (irq == IPU_IRQ_DC_FC_1)
++ dc_chan = 1;
++ else
++ dc_chan = 5;
++
++ if (!ipu->dc_swap) {
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++
++ reg = ipu_cm_read(ipu, IPU_DISP_GEN);
++ if (ipu->dc_di_assignment[dc_chan])
++ reg &= ~DI1_COUNTER_RELEASE;
++ else
++ reg &= ~DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, reg, IPU_DISP_GEN);
++ }
++
++ complete(comp);
++ return IRQ_HANDLED;
++}
++
++void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap)
++{
++ int ret;
++ uint32_t reg;
++ uint32_t csc;
++ uint32_t dc_chan;
++ int irq = 0;
++ int timeout = 50;
++
++ ipu->dc_swap = swap;
++
++ if (channel == MEM_DC_SYNC) {
++ dc_chan = 1;
++ irq = IPU_IRQ_DC_FC_1;
++ } else if (channel == MEM_BG_SYNC) {
++ dc_chan = 5;
++ irq = IPU_IRQ_DP_SF_END;
++ } else if (channel == MEM_FG_SYNC) {
++ /* Disable FG channel */
++ dc_chan = 5;
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(DP_SYNC));
++ csc = reg & DP_COM_CONF_CSC_DEF_MASK;
++ if (csc == DP_COM_CONF_CSC_DEF_FG)
++ reg &= ~DP_COM_CONF_CSC_DEF_MASK;
++
++ reg &= ~DP_COM_CONF_FG_EN;
++ ipu_dp_write(ipu, reg, DP_COM_CONF(DP_SYNC));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ if (ipu_is_channel_busy(ipu, MEM_BG_SYNC)) {
++ ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
++ IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
++ while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
++ IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
++ msleep(2);
++ timeout -= 2;
++ if (timeout <= 0)
++ break;
++ }
++ }
++ return;
++ } else {
++ return;
++ }
++
++ init_completion(&ipu->dc_comp);
++ ret = ipu_request_irq(ipu, irq, dc_irq_handler, 0, NULL, ipu);
++ if (ret < 0) {
++ dev_err(ipu->dev, "DC irq %d in use\n", irq);
++ return;
++ }
++ ret = wait_for_completion_timeout(&ipu->dc_comp, msecs_to_jiffies(50));
++ ipu_free_irq(ipu, irq, ipu);
++ dev_dbg(ipu->dev, "DC stop timeout - %d * 10ms\n", 5 - ret);
++
++ if (ipu->dc_swap) {
++ /* Swap DC channel 1 and 5 settings, and disable old dc chan */
++ reg = ipu_dc_read(ipu, DC_WR_CH_CONF(dc_chan));
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(6 - dc_chan));
++ reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
++ reg ^= DC_WR_CH_CONF_PROG_DI_ID;
++ ipu_dc_write(ipu, reg, DC_WR_CH_CONF(dc_chan));
++ }
++}
++
++void _ipu_init_dc_mappings(struct ipu_soc *ipu)
++{
++ /* IPU_PIX_FMT_RGB24 */
++ _ipu_dc_map_clear(ipu, 0);
++ _ipu_dc_map_config(ipu, 0, 0, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 0, 1, 15, 0xFF);
++ _ipu_dc_map_config(ipu, 0, 2, 23, 0xFF);
++
++ /* IPU_PIX_FMT_RGB666 */
++ _ipu_dc_map_clear(ipu, 1);
++ _ipu_dc_map_config(ipu, 1, 0, 5, 0xFC);
++ _ipu_dc_map_config(ipu, 1, 1, 11, 0xFC);
++ _ipu_dc_map_config(ipu, 1, 2, 17, 0xFC);
++
++ /* IPU_PIX_FMT_YUV444 */
++ _ipu_dc_map_clear(ipu, 2);
++ _ipu_dc_map_config(ipu, 2, 0, 15, 0xFF);
++ _ipu_dc_map_config(ipu, 2, 1, 23, 0xFF);
++ _ipu_dc_map_config(ipu, 2, 2, 7, 0xFF);
++
++ /* IPU_PIX_FMT_RGB565 */
++ _ipu_dc_map_clear(ipu, 3);
++ _ipu_dc_map_config(ipu, 3, 0, 4, 0xF8);
++ _ipu_dc_map_config(ipu, 3, 1, 10, 0xFC);
++ _ipu_dc_map_config(ipu, 3, 2, 15, 0xF8);
++
++ /* IPU_PIX_FMT_LVDS666 */
++ _ipu_dc_map_clear(ipu, 4);
++ _ipu_dc_map_config(ipu, 4, 0, 5, 0xFC);
++ _ipu_dc_map_config(ipu, 4, 1, 13, 0xFC);
++ _ipu_dc_map_config(ipu, 4, 2, 21, 0xFC);
++
++ /* IPU_PIX_FMT_VYUY 16bit width */
++ _ipu_dc_map_clear(ipu, 5);
++ _ipu_dc_map_config(ipu, 5, 0, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 5, 1, 0, 0x0);
++ _ipu_dc_map_config(ipu, 5, 2, 15, 0xFF);
++ _ipu_dc_map_clear(ipu, 6);
++ _ipu_dc_map_config(ipu, 6, 0, 0, 0x0);
++ _ipu_dc_map_config(ipu, 6, 1, 7, 0xFF);
++ _ipu_dc_map_config(ipu, 6, 2, 15, 0xFF);
++
++ /* IPU_PIX_FMT_UYUV 16bit width */
++ _ipu_dc_map_clear(ipu, 7);
++ _ipu_dc_map_link(ipu, 7, 6, 0, 6, 1, 6, 2);
++ _ipu_dc_map_clear(ipu, 8);
++ _ipu_dc_map_link(ipu, 8, 5, 0, 5, 1, 5, 2);
++
++ /* IPU_PIX_FMT_YUYV 16bit width */
++ _ipu_dc_map_clear(ipu, 9);
++ _ipu_dc_map_link(ipu, 9, 5, 2, 5, 1, 5, 0);
++ _ipu_dc_map_clear(ipu, 10);
++ _ipu_dc_map_link(ipu, 10, 5, 1, 5, 2, 5, 0);
++
++ /* IPU_PIX_FMT_YVYU 16bit width */
++ _ipu_dc_map_clear(ipu, 11);
++ _ipu_dc_map_link(ipu, 11, 5, 1, 5, 2, 5, 0);
++ _ipu_dc_map_clear(ipu, 12);
++ _ipu_dc_map_link(ipu, 12, 5, 2, 5, 1, 5, 0);
++
++ /* IPU_PIX_FMT_GBR24 */
++ /* IPU_PIX_FMT_VYU444 */
++ _ipu_dc_map_clear(ipu, 13);
++ _ipu_dc_map_link(ipu, 13, 0, 2, 0, 0, 0, 1);
++
++ /* IPU_PIX_FMT_BGR24 */
++ _ipu_dc_map_clear(ipu, 14);
++ _ipu_dc_map_link(ipu, 14, 0, 2, 0, 1, 0, 0);
++}
++
++int _ipu_pixfmt_to_map(uint32_t fmt)
++{
++ switch (fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_RGB24:
++ return 0;
++ case IPU_PIX_FMT_RGB666:
++ return 1;
++ case IPU_PIX_FMT_YUV444:
++ return 2;
++ case IPU_PIX_FMT_RGB565:
++ return 3;
++ case IPU_PIX_FMT_LVDS666:
++ return 4;
++ case IPU_PIX_FMT_VYUY:
++ return 6;
++ case IPU_PIX_FMT_UYVY:
++ return 8;
++ case IPU_PIX_FMT_YUYV:
++ return 10;
++ case IPU_PIX_FMT_YVYU:
++ return 12;
++ case IPU_PIX_FMT_GBR24:
++ case IPU_PIX_FMT_VYU444:
++ return 13;
++ case IPU_PIX_FMT_BGR24:
++ return 14;
++ }
++
++ return -1;
++}
++
++/*!
++ * This function sets the colorspace for of dp.
++ * modes.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param param If it's not NULL, update the csc table
++ * with this parameter.
++ *
++ * @return N/A
++ */
++void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
++{
++ int dp;
++ struct dp_csc_param_t dp_csc_param;
++
++ if (channel == MEM_FG_SYNC)
++ dp = DP_SYNC;
++ else if (channel == MEM_BG_SYNC)
++ dp = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0)
++ dp = DP_ASYNC0;
++ else
++ return;
++
++ dp_csc_param.mode = -1;
++ dp_csc_param.coeff = param;
++ __ipu_dp_csc_setup(ipu, dp, dp_csc_param, true);
++}
++
++void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3])
++{
++ _ipu_dp_set_csc_coefficients(ipu, channel, param);
++}
++EXPORT_SYMBOL(ipu_set_csc_coefficients);
++
++/*!
++ * This function is called to adapt synchronous LCD panel to IPU restriction.
++ *
++ */
++void adapt_panel_to_ipu_restricitions(struct ipu_soc *ipu, uint16_t *v_start_width,
++ uint16_t *v_sync_width,
++ uint16_t *v_end_width)
++{
++ if (*v_end_width < 2) {
++ uint16_t diff = 2 - *v_end_width;
++ if (*v_start_width >= diff) {
++ *v_end_width = 2;
++ *v_start_width = *v_start_width - diff;
++ } else if (*v_sync_width > diff) {
++ *v_end_width = 2;
++ *v_sync_width = *v_sync_width - diff;
++ } else
++ dev_warn(ipu->dev, "WARNING: try to adapt timming, but failed\n");
++ dev_info(ipu->dev, "WARNING: adapt panel end blank lines\n");
++ }
++}
++
++/*!
++ * This function is called to initialize a synchronous LCD panel.
++ *
++ * @param ipu ipu handler
++ * @param disp The DI the panel is attached to.
++ *
++ * @param pixel_clk Desired pixel clock frequency in Hz.
++ *
++ * @param pixel_fmt Input parameter for pixel format of buffer.
++ * Pixel format is a FOURCC ASCII code.
++ *
++ * @param width The width of panel in pixels.
++ *
++ * @param height The height of panel in pixels.
++ *
++ * @param hStartWidth The number of pixel clocks between the HSYNC
++ * signal pulse and the start of valid data.
++ *
++ * @param hSyncWidth The width of the HSYNC signal in units of pixel
++ * clocks.
++ *
++ * @param hEndWidth The number of pixel clocks between the end of
++ * valid data and the HSYNC signal for next line.
++ *
++ * @param vStartWidth The number of lines between the VSYNC
++ * signal pulse and the start of valid data.
++ *
++ * @param vSyncWidth The width of the VSYNC signal in units of lines
++ *
++ * @param vEndWidth The number of lines between the end of valid
++ * data and the VSYNC signal for next frame.
++ *
++ * @param sig Bitfield of signal polarities for LCD interface.
++ *
++ * @return This function returns 0 on success or negative error code on
++ * fail.
++ */
++int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp, uint32_t pixel_clk,
++ uint16_t width, uint16_t height,
++ uint32_t pixel_fmt,
++ uint16_t h_start_width, uint16_t h_sync_width,
++ uint16_t h_end_width, uint16_t v_start_width,
++ uint16_t v_sync_width, uint16_t v_end_width,
++ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
++{
++ uint32_t field0_offset = 0;
++ uint32_t field1_offset;
++ uint32_t reg;
++ uint32_t di_gen, vsync_cnt;
++ uint32_t div, rounded_pixel_clk;
++ uint32_t h_total, v_total;
++ int map;
++ int ret;
++ struct clk *ldb_di0_clk, *ldb_di1_clk;
++ struct clk *di_parent;
++
++ dev_dbg(ipu->dev, "panel size = %d x %d\n", width, height);
++
++ if ((v_sync_width == 0) || (h_sync_width == 0))
++ return -EINVAL;
++
++ adapt_panel_to_ipu_restricitions(ipu, &v_start_width, &v_sync_width, &v_end_width);
++ h_total = width + h_sync_width + h_start_width + h_end_width;
++ v_total = height + v_sync_width + v_start_width + v_end_width;
++
++ /* Init clocking */
++ dev_dbg(ipu->dev, "pixel clk = %d\n", pixel_clk);
++
++ di_parent = clk_get_parent(ipu->di_clk_sel[disp]);
++ if (!di_parent) {
++ dev_err(ipu->dev, "get di clk parent fail\n");
++ return -EINVAL;
++ }
++ ldb_di0_clk = clk_get(ipu->dev, "ldb_di0");
++ if (IS_ERR(ldb_di0_clk)) {
++ dev_err(ipu->dev, "clk_get di0 failed");
++ return PTR_ERR(ldb_di0_clk);
++ }
++ ldb_di1_clk = clk_get(ipu->dev, "ldb_di1");
++ if (IS_ERR(ldb_di1_clk)) {
++ dev_err(ipu->dev, "clk_get di1 failed");
++ return PTR_ERR(ldb_di1_clk);
++ }
++
++ if (ldb_di0_clk == di_parent || ldb_di1_clk == di_parent) {
++ /* if di clk parent is tve/ldb, then keep it;*/
++ dev_dbg(ipu->dev, "use special clk parent\n");
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp], ipu->di_clk[disp]);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk error:%d\n", ret);
++ return ret;
++ }
++ clk_put(ldb_di0_clk);
++ clk_put(ldb_di1_clk);
++ } else {
++ /* try ipu clk first*/
++ dev_dbg(ipu->dev, "try ipu internal clk\n");
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp], ipu->ipu_clk);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk error:%d\n", ret);
++ return ret;
++ }
++ rounded_pixel_clk = clk_round_rate(ipu->pixel_clk[disp], pixel_clk);
++ dev_dbg(ipu->dev, "rounded pix clk:%d\n", rounded_pixel_clk);
++ /*
++ * we will only use 1/2 fraction for ipu clk,
++ * so if the clk rate is not fit, try ext clk.
++ */
++ if (!sig.int_clk &&
++ ((rounded_pixel_clk >= pixel_clk + pixel_clk/200) ||
++ (rounded_pixel_clk <= pixel_clk - pixel_clk/200))) {
++ dev_dbg(ipu->dev, "try ipu ext di clk\n");
++
++ rounded_pixel_clk =
++ clk_round_rate(ipu->di_clk[disp], pixel_clk);
++ ret = clk_set_rate(ipu->di_clk[disp],
++ rounded_pixel_clk);
++ if (ret) {
++ dev_err(ipu->dev,
++ "set di clk rate error:%d\n", ret);
++ return ret;
++ }
++ dev_dbg(ipu->dev, "di clk:%d\n", rounded_pixel_clk);
++ ret = clk_set_parent(ipu->pixel_clk_sel[disp],
++ ipu->di_clk[disp]);
++ if (ret) {
++ dev_err(ipu->dev,
++ "set pixel clk parent error:%d\n", ret);
++ return ret;
++ }
++ }
++ }
++ rounded_pixel_clk = clk_round_rate(ipu->pixel_clk[disp], pixel_clk);
++ dev_dbg(ipu->dev, "round pixel clk:%d\n", rounded_pixel_clk);
++ ret = clk_set_rate(ipu->pixel_clk[disp], rounded_pixel_clk);
++ if (ret) {
++ dev_err(ipu->dev, "set pixel clk rate error:%d\n", ret);
++ return ret;
++ }
++ msleep(5);
++ /* Get integer portion of divider */
++ div = clk_get_rate(clk_get_parent(ipu->pixel_clk_sel[disp])) / rounded_pixel_clk;
++ dev_dbg(ipu->dev, "div:%d\n", div);
++ if (!div) {
++ dev_err(ipu->dev, "invalid pixel clk div = 0\n");
++ return -EINVAL;
++ }
++
++
++ mutex_lock(&ipu->mutex_lock);
++
++ _ipu_di_data_wave_config(ipu, disp, SYNC_WAVE, div - 1, div - 1);
++ _ipu_di_data_pin_config(ipu, disp, SYNC_WAVE, DI_PIN15, 3, 0, div * 2);
++
++ map = _ipu_pixfmt_to_map(pixel_fmt);
++ if (map < 0) {
++ dev_dbg(ipu->dev, "IPU_DISP: No MAP\n");
++ mutex_unlock(&ipu->mutex_lock);
++ return -EINVAL;
++ }
++
++ /*clear DI*/
++ di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
++ di_gen &= (0x3 << 20);
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ if (sig.interlaced) {
++ if (g_ipu_hw_rev >= IPU_V3DEX) {
++ /* Internal VSYNC for each frame */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_COUNT_1, /* counter */
++ v_total*2 - 1, /* run count */
++ (3 - 1), /* run_resolution, counter 1 can reference to counter 6,7,8 with run_resolution=2,3,4 */
++ 1, /* offset */
++ (3 - 1), /* offset resolution, 3=counter 7 */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* HSYNC waveform on DI_PIN02 */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_HSYNC, /* counter */
++ h_total - 1, /* run count */
++ DI_SYNC_CLK, /* run_resolution, counter 2 can reference to counter 5,7 with run_resolution=3,4 */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 1, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_CLK, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 2*h_sync_width /* COUNT DOWN */
++ );
++
++ /* VSYNC waveform on DI_PIN03 */
++ vsync_cnt = DI_SYNC_VSYNC;
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_VSYNC, /* counter */
++ v_total - 1, /* run count */
++ (4 - 1), /* run_resolution, counter 3 can reference to counter 7 with run_resolution=4 */
++ 1, /* offset */
++ (4 - 1), /* offset resolution, 4=counter 7 */
++ 2, /* repeat count */
++ DI_SYNC_COUNT_1, /* CNT_CLR_SEL */
++ 1, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ (4 - 1), /* CNT_POLARITY_TRIGGER_SEL, 4=counter 7 */
++ 0, /* COUNT UP */
++ 2*v_sync_width /* COUNT DOWN */
++ );
++
++ /* Active Field */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_AFIELD, /* counter */
++ (v_total/2 + 1) - 1, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ h_total/2, /* offset */
++ DI_SYNC_CLK, /* offset resolution */
++ 2, /* repeat count */
++ DI_SYNC_COUNT_1, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Active Line */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_ALINE, /* counter */
++ 0, /* run count */
++ DI_SYNC_HSYNC, /* run_resolution */
++ (v_start_width + v_sync_width) / 2, /* offset */
++ DI_SYNC_HSYNC, /* offset resolution */
++ height/2, /* repeat count */
++ DI_SYNC_AFIELD, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Active Pixel */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_APIXEL, /* counter */
++ 0, /* run count */
++ DI_SYNC_CLK, /* run_resolution */
++ h_start_width + h_sync_width, /* offset */
++ DI_SYNC_CLK, /* offset resolution */
++ width, /* repeat count */
++ DI_SYNC_ALINE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ /* Half line HSYNC */
++ _ipu_di_sync_config(ipu,
++ disp, /* display */
++ DI_SYNC_COUNT_7, /* counter */
++ h_total/2 - 1, /* run count */
++ DI_SYNC_CLK, /* run_resolution */
++ 0, /* offset */
++ DI_SYNC_NONE, /* offset resolution */
++ 0, /* repeat count */
++ DI_SYNC_NONE, /* CNT_CLR_SEL */
++ 0, /* CNT_POLARITY_GEN_EN */
++ DI_SYNC_NONE, /* CNT_POLARITY_CLR_SEL */
++ DI_SYNC_NONE, /* CNT_POLARITY_TRIGGER_SEL */
++ 0, /* COUNT UP */
++ 0 /* COUNT DOWN */
++ );
++
++ ipu_di_write(ipu, disp, v_total / 2 - 1, DI_SCR_CONF);
++
++ /* set y_sel = 1 */
++ di_gen |= ((DI_SYNC_HSYNC-1)<<28);
++ } else {
++ /* Internal HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_INT_HSYNC, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ field1_offset = v_sync_width + v_start_width + height / 2 +
++ v_end_width;
++ if (sig.odd_field_first) {
++ field0_offset = field1_offset - 1;
++ field1_offset = 0;
++ }
++ v_total += v_start_width + v_end_width;
++
++ /* HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
++
++ /* Field 1 VSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1, DI_SYNC_INT_HSYNC,
++ field0_offset,
++ field0_offset ? DI_SYNC_INT_HSYNC : DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, DI_SYNC_NONE, 0, 4);
++
++ /* Active Field */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_AFIELD,
++ field0_offset ?
++ field0_offset : field1_offset - 2,
++ DI_SYNC_INT_HSYNC, v_start_width + v_sync_width, DI_SYNC_INT_HSYNC,
++ 2, DI_SYNC_VSYNC, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
++
++ /* Active Line */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_ALINE, 0, DI_SYNC_INT_HSYNC,
++ 0, DI_SYNC_NONE,
++ height / 2, DI_SYNC_AFIELD, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* Active Pixel */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_APIXEL, 0, DI_SYNC_CLK,
++ h_sync_width + h_start_width, DI_SYNC_CLK,
++ width, DI_SYNC_ALINE, 0, DI_SYNC_NONE, DI_SYNC_NONE,
++ 0, 0);
++
++ /* DC VSYNC waveform */
++ vsync_cnt = DI_SYNC_COUNT_7;
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_7, 0, DI_SYNC_INT_HSYNC,
++ field1_offset,
++ field1_offset ? DI_SYNC_INT_HSYNC : DI_SYNC_NONE,
++ 1, DI_SYNC_VSYNC, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0, 0);
++
++ /* Field 0 VSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_8, v_total - 1, DI_SYNC_INT_HSYNC,
++ 0, DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* ??? */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_9, v_total - 1, (DI_SYNC_HSYNC - 1),
++ 0, DI_SYNC_NONE,
++ 0, DI_SYNC_NONE, 6, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ reg = ipu_di_read(ipu, disp, DI_SW_GEN1(9));
++ reg |= 0x8000;
++ ipu_di_write(ipu, disp, reg, DI_SW_GEN1(9));
++
++ ipu_di_write(ipu, disp, v_sync_width + v_start_width +
++ v_end_width + height / 2 - 1, DI_SCR_CONF);
++ }
++
++ /* Init template microcode */
++ if (disp) {
++ _ipu_dc_write_tmpl(ipu, 1, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
++ }
++ } else {
++ _ipu_dc_write_tmpl(ipu, 0, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
++ }
++ }
++
++ if (sig.Hsync_pol)
++ di_gen |= DI_GEN_POLARITY_2;
++ if (sig.Vsync_pol)
++ di_gen |= DI_GEN_POLARITY_3;
++ } else {
++ /* Setup internal HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_INT_HSYNC, h_total - 1, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 0, DI_SYNC_NONE, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++
++ /* Setup external (delayed) HSYNC waveform */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_HSYNC, h_total - 1,
++ DI_SYNC_CLK, div * v_to_h_sync, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE, 1, DI_SYNC_NONE,
++ DI_SYNC_CLK, 0, h_sync_width * 2);
++ /* Setup VSYNC waveform */
++ vsync_cnt = DI_SYNC_VSYNC;
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_VSYNC, v_total - 1,
++ DI_SYNC_INT_HSYNC, 0, DI_SYNC_NONE, 0,
++ DI_SYNC_NONE, 1, DI_SYNC_NONE,
++ DI_SYNC_INT_HSYNC, 0, v_sync_width * 2);
++ ipu_di_write(ipu, disp, v_total - 1, DI_SCR_CONF);
++
++ /* Setup active data waveform to sync with DC */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_ALINE, 0, DI_SYNC_HSYNC,
++ v_sync_width + v_start_width, DI_SYNC_HSYNC, height,
++ DI_SYNC_VSYNC, 0, DI_SYNC_NONE,
++ DI_SYNC_NONE, 0, 0);
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_APIXEL, 0, DI_SYNC_CLK,
++ h_sync_width + h_start_width, DI_SYNC_CLK,
++ width, DI_SYNC_ALINE, 0, DI_SYNC_NONE, DI_SYNC_NONE, 0,
++ 0);
++
++ /* set VGA delayed hsync/vsync no matter VGA enabled */
++ if (disp) {
++ /* couter 7 for VGA delay HSYNC */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_7,
++ h_total - 1, DI_SYNC_CLK,
++ 18, DI_SYNC_CLK,
++ 0, DI_SYNC_NONE,
++ 1, DI_SYNC_NONE, DI_SYNC_CLK,
++ 0, h_sync_width * 2);
++
++ /* couter 8 for VGA delay VSYNC */
++ _ipu_di_sync_config(ipu, disp, DI_SYNC_COUNT_8,
++ v_total - 1, DI_SYNC_INT_HSYNC,
++ 1, DI_SYNC_INT_HSYNC,
++ 0, DI_SYNC_NONE,
++ 1, DI_SYNC_NONE, DI_SYNC_INT_HSYNC,
++ 0, v_sync_width * 2);
++ }
++
++ /* reset all unused counters */
++ if (!disp) {
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(7));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(7));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(7));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(8));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(8));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(8));
++ }
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN0(9));
++ ipu_di_write(ipu, disp, 0, DI_SW_GEN1(9));
++ ipu_di_write(ipu, disp, 0, DI_STP_REP(9));
++
++ /* Init template microcode */
++ if (disp) {
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 8, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 9, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, (width - 1), DC_UGDE_3(disp));
++ }
++ _ipu_dc_write_tmpl(ipu, 2, WROD(0), 0, map, SYNC_WAVE, 8, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 3, WROD(0), 0, map, SYNC_WAVE, 4, DI_SYNC_APIXEL, 0);
++ _ipu_dc_write_tmpl(ipu, 4, WRG, 0, map, NULL_WAVE, 0, DI_SYNC_CLK, 1);
++ _ipu_dc_write_tmpl(ipu, 1, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++
++ } else {
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY)) {
++ _ipu_dc_write_tmpl(ipu, 10, WROD(0), 0, (map - 1), SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 11, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ /* configure user events according to DISP NUM */
++ ipu_dc_write(ipu, width - 1, DC_UGDE_3(disp));
++ }
++ _ipu_dc_write_tmpl(ipu, 5, WROD(0), 0, map, SYNC_WAVE, 8, DI_SYNC_APIXEL, 1);
++ _ipu_dc_write_tmpl(ipu, 6, WROD(0), 0, map, SYNC_WAVE, 4, DI_SYNC_APIXEL, 0);
++ _ipu_dc_write_tmpl(ipu, 7, WRG, 0, map, NULL_WAVE, 0, DI_SYNC_CLK, 1);
++ _ipu_dc_write_tmpl(ipu, 12, WROD(0), 0, map, SYNC_WAVE, 0, DI_SYNC_APIXEL, 1);
++ }
++
++ if (sig.Hsync_pol) {
++ di_gen |= DI_GEN_POLARITY_2;
++ if (disp)
++ di_gen |= DI_GEN_POLARITY_7;
++ }
++ if (sig.Vsync_pol) {
++ di_gen |= DI_GEN_POLARITY_3;
++ if (disp)
++ di_gen |= DI_GEN_POLARITY_8;
++ }
++ }
++ /* changinc DISP_CLK polarity: it can be wrong for some applications */
++ if ((pixel_fmt == IPU_PIX_FMT_YUYV) ||
++ (pixel_fmt == IPU_PIX_FMT_UYVY) ||
++ (pixel_fmt == IPU_PIX_FMT_YVYU) ||
++ (pixel_fmt == IPU_PIX_FMT_VYUY))
++ di_gen |= 0x00020000;
++
++ if (!sig.clk_pol)
++ di_gen |= DI_GEN_POLARITY_DISP_CLK;
++
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ ipu_di_write(ipu, disp, (--vsync_cnt << DI_VSYNC_SEL_OFFSET) |
++ 0x00000002, DI_SYNC_AS_GEN);
++ reg = ipu_di_read(ipu, disp, DI_POL);
++ reg &= ~(DI_POL_DRDY_DATA_POLARITY | DI_POL_DRDY_POLARITY_15);
++ if (sig.enable_pol)
++ reg |= DI_POL_DRDY_POLARITY_15;
++ if (sig.data_pol)
++ reg |= DI_POL_DRDY_DATA_POLARITY;
++ ipu_di_write(ipu, disp, reg, DI_POL);
++
++ ipu_dc_write(ipu, width, DC_DISP_CONF2(DC_DISP_ID_SYNC(disp)));
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_sync_panel);
++
++void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp)
++{
++ uint32_t reg;
++ uint32_t di_gen;
++
++ if ((disp != 0) || (disp != 1))
++ return;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ di_gen = ipu_di_read(ipu, disp, DI_GENERAL);
++ di_gen |= 0x3ff | DI_GEN_POLARITY_DISP_CLK;
++ ipu_di_write(ipu, disp, di_gen, DI_GENERAL);
++
++ reg = ipu_di_read(ipu, disp, DI_POL);
++ reg |= 0x3ffffff;
++ ipu_di_write(ipu, disp, reg, DI_POL);
++
++ mutex_unlock(&ipu->mutex_lock);
++}
++EXPORT_SYMBOL(ipu_uninit_sync_panel);
++
++int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
++ uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig)
++{
++ int map;
++ u32 ser_conf = 0;
++ u32 div;
++ u32 di_clk = clk_get_rate(ipu->ipu_clk);
++
++ /* round up cycle_time, then calcalate the divider using scaled math */
++ cycle_time += (1000000000UL / di_clk) - 1;
++ div = (cycle_time * (di_clk / 256UL)) / (1000000000UL / 256UL);
++
++ map = _ipu_pixfmt_to_map(pixel_fmt);
++ if (map < 0)
++ return -EINVAL;
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (type == IPU_PANEL_SERIAL) {
++ ipu_di_write(ipu, disp, (div << 24) | ((sig.ifc_width - 1) << 4),
++ DI_DW_GEN(ASYNC_SER_WAVE));
++
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_CS,
++ 0, 0, (div * 2) + 1);
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_CLK,
++ 1, div, div * 2);
++ _ipu_di_data_pin_config(ipu, disp, ASYNC_SER_WAVE, DI_PIN_SER_RS,
++ 2, 0, 0);
++
++ _ipu_dc_write_tmpl(ipu, 0x64, WROD(0), 0, map, ASYNC_SER_WAVE, 0, 0, 1);
++
++ /* Configure DC for serial panel */
++ ipu_dc_write(ipu, 0x14, DC_DISP_CONF1(DC_DISP_ID_SERIAL));
++
++ if (sig.clk_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_CLK_POL;
++ if (sig.data_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_DATA_POL;
++ if (sig.rs_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_RS_POL;
++ if (sig.cs_pol)
++ ser_conf |= DI_SER_CONF_SERIAL_CS_POL;
++ ipu_di_write(ipu, disp, ser_conf, DI_SER_CONF);
++ }
++
++ mutex_unlock(&ipu->mutex_lock);
++ return 0;
++}
++EXPORT_SYMBOL(ipu_init_async_panel);
++
++/*!
++ * This function sets the foreground and background plane global alpha blending
++ * modes. This function also sets the DP graphic plane according to the
++ * parameter of IPUv3 DP channel.
++ *
++ * @param ipu ipu handler
++ * @param channel IPUv3 DP channel
++ *
++ * @param enable Boolean to enable or disable global alpha
++ * blending. If disabled, local blending is used.
++ *
++ * @param alpha Global alpha value.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel,
++ bool enable, uint8_t alpha)
++{
++ uint32_t reg;
++ uint32_t flow;
++ bool bg_chan;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_BG_ASYNC0 ||
++ channel == MEM_BG_ASYNC1)
++ bg_chan = true;
++ else
++ bg_chan = false;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ if (bg_chan) {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWSEL, DP_COM_CONF(flow));
++ }
++
++ if (enable) {
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0x00FFFFFFL;
++ ipu_dp_write(ipu, reg | ((uint32_t) alpha << 24),
++ DP_GRAPH_WIND_CTRL(flow));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWAM, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWAM, DP_COM_CONF(flow));
++ }
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_global_alpha);
++
++/*!
++ * This function sets the transparent color key for SDC graphic plane.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param enable Boolean to enable or disable color key
++ *
++ * @param colorKey 24-bit RGB color for transparent color key.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel,
++ bool enable, uint32_t color_key)
++{
++ uint32_t reg, flow;
++ int y, u, v;
++ int red, green, blue;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ ipu->color_key_4rgb = true;
++ /* Transform color key from rgb to yuv if CSC is enabled */
++ if (((ipu->fg_csc_type == RGB2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == RGB2YUV)) ||
++ ((ipu->fg_csc_type == YUV2YUV) && (ipu->bg_csc_type == YUV2YUV)) ||
++ ((ipu->fg_csc_type == YUV2RGB) && (ipu->bg_csc_type == YUV2RGB))) {
++
++ dev_dbg(ipu->dev, "color key 0x%x need change to yuv fmt\n", color_key);
++
++ red = (color_key >> 16) & 0xFF;
++ green = (color_key >> 8) & 0xFF;
++ blue = color_key & 0xFF;
++
++ y = _rgb_to_yuv(0, red, green, blue);
++ u = _rgb_to_yuv(1, red, green, blue);
++ v = _rgb_to_yuv(2, red, green, blue);
++ color_key = (y << 16) | (u << 8) | v;
++
++ ipu->color_key_4rgb = false;
++
++ dev_dbg(ipu->dev, "color key change to yuv fmt 0x%x\n", color_key);
++ }
++
++ if (enable) {
++ reg = ipu_dp_read(ipu, DP_GRAPH_WIND_CTRL(flow)) & 0xFF000000L;
++ ipu_dp_write(ipu, reg | color_key, DP_GRAPH_WIND_CTRL(flow));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
++ } else {
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GWCKE, DP_COM_CONF(flow));
++ }
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_color_key);
++
++/*!
++ * This function sets the gamma correction for DP output.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param enable Boolean to enable or disable gamma correction.
++ *
++ * @param constk Gamma piecewise linear approximation constk coeff.
++ *
++ * @param slopek Gamma piecewise linear approximation slopek coeff.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable, int constk[], int slopek[])
++{
++ uint32_t reg, flow, i;
++
++ if (channel == MEM_BG_SYNC || channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_BG_ASYNC0 || channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_BG_ASYNC1 || channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ _ipu_get(ipu);
++
++ mutex_lock(&ipu->mutex_lock);
++
++ for (i = 0; i < 8; i++)
++ ipu_dp_write(ipu, (constk[2*i] & 0x1ff) | ((constk[2*i+1] & 0x1ff) << 16), DP_GAMMA_C(flow, i));
++ for (i = 0; i < 4; i++)
++ ipu_dp_write(ipu, (slopek[4*i] & 0xff) | ((slopek[4*i+1] & 0xff) << 8) |
++ ((slopek[4*i+2] & 0xff) << 16) | ((slopek[4*i+3] & 0xff) << 24), DP_GAMMA_S(flow, i));
++
++ reg = ipu_dp_read(ipu, DP_COM_CONF(flow));
++ if (enable) {
++ if ((ipu->bg_csc_type == RGB2YUV) || (ipu->bg_csc_type == YUV2YUV))
++ reg |= DP_COM_CONF_GAMMA_YUV_EN;
++ else
++ reg &= ~DP_COM_CONF_GAMMA_YUV_EN;
++ ipu_dp_write(ipu, reg | DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
++ } else
++ ipu_dp_write(ipu, reg & ~DP_COM_CONF_GAMMA_EN, DP_COM_CONF(flow));
++
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++
++ mutex_unlock(&ipu->mutex_lock);
++
++ _ipu_put(ipu);
++
++ return 0;
++}
++EXPORT_SYMBOL(ipu_disp_set_gamma_correction);
++
++/*!
++ * This function sets the window position of the foreground or background plane.
++ * modes.
++ *
++ * @param ipu ipu handler
++ * @param channel Input parameter for the logical channel ID.
++ *
++ * @param x_pos The X coordinate position to place window at.
++ * The position is relative to the top left corner.
++ *
++ * @param y_pos The Y coordinate position to place window at.
++ * The position is relative to the top left corner.
++ *
++ * @return Returns 0 on success or negative error code on fail
++ */
++int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos)
++{
++ u32 reg;
++ uint32_t flow = 0;
++ uint32_t dp_srm_shift;
++
++ if ((channel == MEM_FG_SYNC) || (channel == MEM_BG_SYNC)) {
++ flow = DP_SYNC;
++ dp_srm_shift = 3;
++ } else if (channel == MEM_FG_ASYNC0) {
++ flow = DP_ASYNC0;
++ dp_srm_shift = 5;
++ } else if (channel == MEM_FG_ASYNC1) {
++ flow = DP_ASYNC1;
++ dp_srm_shift = 7;
++ } else
++ return -EINVAL;
++
++ ipu_dp_write(ipu, (x_pos << 16) | y_pos, DP_FG_POS(flow));
++
++ if (ipu_is_channel_busy(ipu, channel)) {
++ /* controled by FSU if channel enabled */
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
++ reg |= (0x1 << dp_srm_shift);
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ } else {
++ /* disable auto swap, controled by MCU if channel disabled */
++ reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift));
++ ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
++ }
++
++ return 0;
++}
++
++int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos)
++{
++ int ret;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ret = _ipu_disp_set_window_pos(ipu, channel, x_pos, y_pos);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_disp_set_window_pos);
++
++int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos)
++{
++ u32 reg;
++ uint32_t flow = 0;
++
++ if (channel == MEM_FG_SYNC)
++ flow = DP_SYNC;
++ else if (channel == MEM_FG_ASYNC0)
++ flow = DP_ASYNC0;
++ else if (channel == MEM_FG_ASYNC1)
++ flow = DP_ASYNC1;
++ else
++ return -EINVAL;
++
++ reg = ipu_dp_read(ipu, DP_FG_POS(flow));
++
++ *x_pos = (reg >> 16) & 0x7FF;
++ *y_pos = reg & 0x7FF;
++
++ return 0;
++}
++int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos)
++{
++ int ret;
++
++ _ipu_get(ipu);
++ mutex_lock(&ipu->mutex_lock);
++ ret = _ipu_disp_get_window_pos(ipu, channel, x_pos, y_pos);
++ mutex_unlock(&ipu->mutex_lock);
++ _ipu_put(ipu);
++ return ret;
++}
++EXPORT_SYMBOL(ipu_disp_get_window_pos);
++
++void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset)
++{
++ if (channel == DIRECT_ASYNC0)
++ writel(value, ipu->disp_base[0] + offset);
++ else if (channel == DIRECT_ASYNC1)
++ writel(value, ipu->disp_base[1] + offset);
++}
++EXPORT_SYMBOL(ipu_disp_direct_write);
++
++void ipu_reset_disp_panel(struct ipu_soc *ipu)
++{
++ uint32_t tmp;
++
++ tmp = ipu_di_read(ipu, 1, DI_GENERAL);
++ ipu_di_write(ipu, 1, tmp | 0x08, DI_GENERAL);
++ msleep(10); /* tRES >= 100us */
++ tmp = ipu_di_read(ipu, 1, DI_GENERAL);
++ ipu_di_write(ipu, 1, tmp & ~0x08, DI_GENERAL);
++ msleep(60);
++
++ return;
++}
++EXPORT_SYMBOL(ipu_reset_disp_panel);
++
++void ipu_disp_init(struct ipu_soc *ipu)
++{
++ ipu->fg_csc_type = ipu->bg_csc_type = CSC_NONE;
++ ipu->color_key_4rgb = true;
++ _ipu_init_dc_mappings(ipu);
++ _ipu_dmfc_init(ipu, DMFC_NORMAL, 1);
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_ic.c linux-3.14.72/drivers/mxc/ipu3/ipu_ic.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_ic.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_ic.c 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,924 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_ic.c
++ *
++ * @brief IPU IC functions
++ *
++ * @ingroup IPU
++ */
++#include <linux/errno.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/spinlock.h>
++#include <linux/types.h>
++#include <linux/videodev2.h>
++
++#include "ipu_param_mem.h"
++#include "ipu_regs.h"
++
++enum {
++ IC_TASK_VIEWFINDER,
++ IC_TASK_ENCODER,
++ IC_TASK_POST_PROCESSOR
++};
++
++static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
++ ipu_color_space_t out_format, int csc_index);
++
++static int _calc_resize_coeffs(struct ipu_soc *ipu,
++ uint32_t inSize, uint32_t outSize,
++ uint32_t *resizeCoeff,
++ uint32_t *downsizeCoeff);
++
++void _ipu_vdi_set_top_field_man(struct ipu_soc *ipu, bool top_field_0)
++{
++ uint32_t reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ if (top_field_0)
++ reg &= ~VDI_C_TOP_FIELD_MAN_1;
++ else
++ reg |= VDI_C_TOP_FIELD_MAN_1;
++ ipu_vdi_write(ipu, reg, VDI_C);
++}
++
++void _ipu_vdi_set_motion(struct ipu_soc *ipu, ipu_motion_sel motion_sel)
++{
++ uint32_t reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ reg &= ~(VDI_C_MOT_SEL_FULL | VDI_C_MOT_SEL_MED | VDI_C_MOT_SEL_LOW);
++ if (motion_sel == HIGH_MOTION)
++ reg |= VDI_C_MOT_SEL_FULL;
++ else if (motion_sel == MED_MOTION)
++ reg |= VDI_C_MOT_SEL_MED;
++ else
++ reg |= VDI_C_MOT_SEL_LOW;
++
++ ipu_vdi_write(ipu, reg, VDI_C);
++ dev_dbg(ipu->dev, "VDI_C = \t0x%08X\n", reg);
++}
++
++void ic_dump_register(struct ipu_soc *ipu)
++{
++ printk(KERN_DEBUG "IC_CONF = \t0x%08X\n", ipu_ic_read(ipu, IC_CONF));
++ printk(KERN_DEBUG "IC_PRP_ENC_RSC = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_PRP_ENC_RSC));
++ printk(KERN_DEBUG "IC_PRP_VF_RSC = \t0x%08X\n",
++ ipu_ic_read(ipu, IC_PRP_VF_RSC));
++ printk(KERN_DEBUG "IC_PP_RSC = \t0x%08X\n", ipu_ic_read(ipu, IC_PP_RSC));
++ printk(KERN_DEBUG "IC_IDMAC_1 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_1));
++ printk(KERN_DEBUG "IC_IDMAC_2 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_2));
++ printk(KERN_DEBUG "IC_IDMAC_3 = \t0x%08X\n", ipu_ic_read(ipu, IC_IDMAC_3));
++}
++
++void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t ic_conf;
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++ switch (channel) {
++ case CSI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_MEM:
++ ic_conf |= IC_CONF_PRPVF_EN | IC_CONF_RWS_EN ;
++ break;
++ case MEM_ROT_VF_MEM:
++ ic_conf |= IC_CONF_PRPVF_ROT_EN;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case MEM_PRP_ENC_MEM:
++ ic_conf |= IC_CONF_PRPENC_EN;
++ break;
++ case MEM_ROT_ENC_MEM:
++ ic_conf |= IC_CONF_PRPENC_ROT_EN;
++ break;
++ case MEM_PP_MEM:
++ ic_conf |= IC_CONF_PP_EN;
++ break;
++ case MEM_ROT_PP_MEM:
++ ic_conf |= IC_CONF_PP_ROT_EN;
++ break;
++ default:
++ break;
++ }
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++}
++
++void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel)
++{
++ uint32_t ic_conf;
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++ switch (channel) {
++ case CSI_PRP_VF_MEM:
++ case MEM_PRP_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_PRP_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_EN;
++ break;
++ case MEM_VDI_MEM:
++ ic_conf &= ~(IC_CONF_PRPVF_EN | IC_CONF_RWS_EN);
++ break;
++ case MEM_ROT_VF_MEM:
++ ic_conf &= ~IC_CONF_PRPVF_ROT_EN;
++ break;
++ case CSI_PRP_ENC_MEM:
++ case MEM_PRP_ENC_MEM:
++ ic_conf &= ~IC_CONF_PRPENC_EN;
++ break;
++ case MEM_ROT_ENC_MEM:
++ ic_conf &= ~IC_CONF_PRPENC_ROT_EN;
++ break;
++ case MEM_PP_MEM:
++ ic_conf &= ~IC_CONF_PP_EN;
++ break;
++ case MEM_ROT_PP_MEM:
++ ic_conf &= ~IC_CONF_PP_ROT_EN;
++ break;
++ default:
++ break;
++ }
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++}
++
++void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params)
++{
++ uint32_t reg;
++ uint32_t pixel_fmt;
++ uint32_t pix_per_burst;
++
++ reg = ((params->mem_prp_vf_mem.in_height-1) << 16) |
++ (params->mem_prp_vf_mem.in_width-1);
++ ipu_vdi_write(ipu, reg, VDI_FSIZE);
++
++ /* Full motion, only vertical filter is used
++ Burst size is 4 accesses */
++ if (params->mem_prp_vf_mem.in_pixel_fmt ==
++ IPU_PIX_FMT_UYVY ||
++ params->mem_prp_vf_mem.in_pixel_fmt ==
++ IPU_PIX_FMT_YUYV) {
++ pixel_fmt = VDI_C_CH_422;
++ pix_per_burst = 32;
++ } else {
++ pixel_fmt = VDI_C_CH_420;
++ pix_per_burst = 64;
++ }
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ reg |= pixel_fmt;
++ switch (channel) {
++ case MEM_VDI_PRP_VF_MEM:
++ reg |= VDI_C_BURST_SIZE2_4;
++ break;
++ case MEM_VDI_PRP_VF_MEM_P:
++ reg |= VDI_C_BURST_SIZE1_4 | VDI_C_VWM1_SET_1 | VDI_C_VWM1_CLR_2;
++ break;
++ case MEM_VDI_PRP_VF_MEM_N:
++ reg |= VDI_C_BURST_SIZE3_4 | VDI_C_VWM3_SET_1 | VDI_C_VWM3_CLR_2;
++ break;
++
++ case MEM_VDI_MEM:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE2_OFFSET;
++ break;
++ case MEM_VDI_MEM_P:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE1_OFFSET;
++ reg |= VDI_C_VWM1_SET_2 | VDI_C_VWM1_CLR_2;
++ break;
++ case MEM_VDI_MEM_N:
++ reg |= (((pix_per_burst >> 2) - 1) & VDI_C_BURST_SIZE_MASK)
++ << VDI_C_BURST_SIZE3_OFFSET;
++ reg |= VDI_C_VWM3_SET_2 | VDI_C_VWM3_CLR_2;
++ break;
++ default:
++ break;
++ }
++ ipu_vdi_write(ipu, reg, VDI_C);
++
++ if (params->mem_prp_vf_mem.field_fmt == IPU_DEINTERLACE_FIELD_TOP)
++ _ipu_vdi_set_top_field_man(ipu, true);
++ else if (params->mem_prp_vf_mem.field_fmt == IPU_DEINTERLACE_FIELD_BOTTOM)
++ _ipu_vdi_set_top_field_man(ipu, false);
++
++ _ipu_vdi_set_motion(ipu, params->mem_prp_vf_mem.motion_sel);
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_RWS_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_vdi_uninit(struct ipu_soc *ipu)
++{
++ ipu_vdi_write(ipu, 0, VDI_FSIZE);
++ ipu_vdi_write(ipu, 0, VDI_C);
++}
++
++int _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_prp_vf_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_height,
++ params->mem_prp_vf_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpvf height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else
++ reg = (params->mem_prp_vf_mem.outv_resize_ratio) << 16;
++
++ /* Setup horizontal resizing */
++ if (!params->mem_prp_vf_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_vf_mem.in_width,
++ params->mem_prp_vf_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpvf width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else
++ reg |= params->mem_prp_vf_mem.outh_resize_ratio;
++
++ ipu_ic_write(ipu, reg, IC_PRP_VF_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_prp_vf_mem.graphics_combine_en) {
++ ic_conf |= IC_CONF_PRPVF_CMB;
++
++ if (!(ic_conf & IC_CONF_PRPVF_CSC1)) {
++ /* need transparent CSC1 conversion */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, RGB, 1);
++ ic_conf |= IC_CONF_PRPVF_CSC1; /* Enable RGB->RGB CSC */
++ }
++ in_fmt = format_to_colorspace(params->mem_prp_vf_mem.in_g_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_vf_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC2 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, RGB, out_fmt, 2);
++ ic_conf |= IC_CONF_PRPVF_CSC2;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC2 */
++ _init_csc(ipu, IC_TASK_VIEWFINDER, YCbCr, RGB, 2);
++ ic_conf |= IC_CONF_PRPVF_CSC2;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_prp_vf_mem.global_alpha_en) {
++ ic_conf |= IC_CONF_IC_GLB_LOC_A;
++ reg = ipu_ic_read(ipu, IC_CMBP_1);
++ reg &= ~(0xff);
++ reg |= params->mem_prp_vf_mem.alpha;
++ ipu_ic_write(ipu, reg, IC_CMBP_1);
++ } else
++ ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
++
++ if (params->mem_prp_vf_mem.key_color_en) {
++ ic_conf |= IC_CONF_KEY_COLOR_EN;
++ ipu_ic_write(ipu, params->mem_prp_vf_mem.key_color,
++ IC_CMBP_2);
++ } else
++ ic_conf &= ~IC_CONF_KEY_COLOR_EN;
++ } else {
++ ic_conf &= ~IC_CONF_PRPVF_CMB;
++ }
++
++ if (src_is_csi)
++ ic_conf &= ~IC_CONF_RWS_EN;
++ else
++ ic_conf |= IC_CONF_RWS_EN;
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPVF_EN | IC_CONF_PRPVF_CMB |
++ IC_CONF_PRPVF_CSC2 | IC_CONF_PRPVF_CSC1);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_PRPVF_ROT_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_prp_enc_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu,
++ params->mem_prp_enc_mem.in_height,
++ params->mem_prp_enc_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpenc height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else
++ reg = (params->mem_prp_enc_mem.outv_resize_ratio) << 16;
++
++ /* Setup horizontal resizing */
++ if (!params->mem_prp_enc_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_prp_enc_mem.in_width,
++ params->mem_prp_enc_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate prpenc width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else
++ reg |= params->mem_prp_enc_mem.outh_resize_ratio;
++
++ ipu_ic_write(ipu, reg, IC_PRP_ENC_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_prp_enc_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_prp_enc_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_ENCODER, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PRPENC_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_ENCODER, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PRPENC_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (src_is_csi)
++ ic_conf &= ~IC_CONF_RWS_EN;
++ else
++ ic_conf |= IC_CONF_RWS_EN;
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PRPENC_ROT_EN);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++ uint32_t reg, ic_conf;
++ uint32_t downsizeCoeff, resizeCoeff;
++ ipu_color_space_t in_fmt, out_fmt;
++ int ret = 0;
++
++ /* Setup vertical resizing */
++ if (!params->mem_pp_mem.outv_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_pp_mem.in_height,
++ params->mem_pp_mem.out_height,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate pp height "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg = (downsizeCoeff << 30) | (resizeCoeff << 16);
++ } else {
++ reg = (params->mem_pp_mem.outv_resize_ratio) << 16;
++ }
++
++ /* Setup horizontal resizing */
++ if (!params->mem_pp_mem.outh_resize_ratio) {
++ ret = _calc_resize_coeffs(ipu, params->mem_pp_mem.in_width,
++ params->mem_pp_mem.out_width,
++ &resizeCoeff, &downsizeCoeff);
++ if (ret < 0) {
++ dev_err(ipu->dev, "failed to calculate pp width "
++ "scaling coefficients\n");
++ return ret;
++ }
++
++ reg |= (downsizeCoeff << 14) | resizeCoeff;
++ } else {
++ reg |= params->mem_pp_mem.outh_resize_ratio;
++ }
++
++ ipu_ic_write(ipu, reg, IC_PP_RSC);
++
++ ic_conf = ipu_ic_read(ipu, IC_CONF);
++
++ /* Setup color space conversion */
++ in_fmt = format_to_colorspace(params->mem_pp_mem.in_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC1 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 1);
++ ic_conf |= IC_CONF_PP_CSC1;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC1 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 1);
++ ic_conf |= IC_CONF_PP_CSC1;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_pp_mem.graphics_combine_en) {
++ ic_conf |= IC_CONF_PP_CMB;
++
++ if (!(ic_conf & IC_CONF_PP_CSC1)) {
++ /* need transparent CSC1 conversion */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, RGB, 1);
++ ic_conf |= IC_CONF_PP_CSC1; /* Enable RGB->RGB CSC */
++ }
++
++ in_fmt = format_to_colorspace(params->mem_pp_mem.in_g_pixel_fmt);
++ out_fmt = format_to_colorspace(params->mem_pp_mem.out_pixel_fmt);
++ if (in_fmt == RGB) {
++ if ((out_fmt == YCbCr) || (out_fmt == YUV)) {
++ /* Enable RGB->YCBCR CSC2 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, RGB, out_fmt, 2);
++ ic_conf |= IC_CONF_PP_CSC2;
++ }
++ }
++ if ((in_fmt == YCbCr) || (in_fmt == YUV)) {
++ if (out_fmt == RGB) {
++ /* Enable YCBCR->RGB CSC2 */
++ _init_csc(ipu, IC_TASK_POST_PROCESSOR, YCbCr, RGB, 2);
++ ic_conf |= IC_CONF_PP_CSC2;
++ } else {
++ /* TODO: Support YUV<->YCbCr conversion? */
++ }
++ }
++
++ if (params->mem_pp_mem.global_alpha_en) {
++ ic_conf |= IC_CONF_IC_GLB_LOC_A;
++ reg = ipu_ic_read(ipu, IC_CMBP_1);
++ reg &= ~(0xff00);
++ reg |= (params->mem_pp_mem.alpha << 8);
++ ipu_ic_write(ipu, reg, IC_CMBP_1);
++ } else
++ ic_conf &= ~IC_CONF_IC_GLB_LOC_A;
++
++ if (params->mem_pp_mem.key_color_en) {
++ ic_conf |= IC_CONF_KEY_COLOR_EN;
++ ipu_ic_write(ipu, params->mem_pp_mem.key_color,
++ IC_CMBP_2);
++ } else
++ ic_conf &= ~IC_CONF_KEY_COLOR_EN;
++ } else {
++ ic_conf &= ~IC_CONF_PP_CMB;
++ }
++
++ ipu_ic_write(ipu, ic_conf, IC_CONF);
++
++ return ret;
++}
++
++void _ipu_ic_uninit_pp(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~(IC_CONF_PP_EN | IC_CONF_PP_CSC1 | IC_CONF_PP_CSC2 |
++ IC_CONF_PP_CMB);
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params)
++{
++}
++
++void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ reg = ipu_ic_read(ipu, IC_CONF);
++ reg &= ~IC_CONF_PP_ROT_EN;
++ ipu_ic_write(ipu, reg, IC_CONF);
++}
++
++int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan,
++ uint16_t width, uint16_t height,
++ int burst_size, ipu_rotate_mode_t rot)
++{
++ u32 ic_idmac_1, ic_idmac_2, ic_idmac_3;
++ u32 temp_rot = bitrev8(rot) >> 5;
++ bool need_hor_flip = false;
++
++ if ((burst_size != 8) && (burst_size != 16)) {
++ dev_dbg(ipu->dev, "Illegal burst length for IC\n");
++ return -EINVAL;
++ }
++
++ width--;
++ height--;
++
++ if (temp_rot & 0x2) /* Need horizontal flip */
++ need_hor_flip = true;
++
++ ic_idmac_1 = ipu_ic_read(ipu, IC_IDMAC_1);
++ ic_idmac_2 = ipu_ic_read(ipu, IC_IDMAC_2);
++ ic_idmac_3 = ipu_ic_read(ipu, IC_IDMAC_3);
++ if (dma_chan == 22) { /* PP output - CB2 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB2_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB2_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PP_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PP_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PP_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PP_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PP_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PP_WIDTH_OFFSET;
++ } else if (dma_chan == 11) { /* PP Input - CB5 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB5_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB5_BURST_16;
++ } else if (dma_chan == 47) { /* PP Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PP_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PP_ROT_OFFSET;
++ }
++
++ if (dma_chan == 12) { /* PRP Input - CB6 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB6_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB6_BURST_16;
++ }
++
++ if (dma_chan == 20) { /* PRP ENC output - CB0 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB0_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB0_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PRPENC_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PRPENC_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PRPENC_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PRPENC_WIDTH_OFFSET;
++
++ } else if (dma_chan == 45) { /* PRP ENC Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPENC_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPENC_ROT_OFFSET;
++ }
++
++ if (dma_chan == 21) { /* PRP VF output - CB1 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB1_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB1_BURST_16;
++
++ if (need_hor_flip)
++ ic_idmac_1 |= IC_IDMAC_1_PRPVF_FLIP_RS;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_FLIP_RS;
++
++ ic_idmac_2 &= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK;
++ ic_idmac_2 |= height << IC_IDMAC_2_PRPVF_HEIGHT_OFFSET;
++
++ ic_idmac_3 &= ~IC_IDMAC_3_PRPVF_WIDTH_MASK;
++ ic_idmac_3 |= width << IC_IDMAC_3_PRPVF_WIDTH_OFFSET;
++
++ } else if (dma_chan == 46) { /* PRP VF Rot input */
++ ic_idmac_1 &= ~IC_IDMAC_1_PRPVF_ROT_MASK;
++ ic_idmac_1 |= temp_rot << IC_IDMAC_1_PRPVF_ROT_OFFSET;
++ }
++
++ if (dma_chan == 14) { /* PRP VF graphics combining input - CB3 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB3_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB3_BURST_16;
++ } else if (dma_chan == 15) { /* PP graphics combining input - CB4 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB4_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB4_BURST_16;
++ } else if (dma_chan == 5) { /* VDIC OUTPUT - CB7 */
++ if (burst_size == 16)
++ ic_idmac_1 |= IC_IDMAC_1_CB7_BURST_16;
++ else
++ ic_idmac_1 &= ~IC_IDMAC_1_CB7_BURST_16;
++ }
++
++ ipu_ic_write(ipu, ic_idmac_1, IC_IDMAC_1);
++ ipu_ic_write(ipu, ic_idmac_2, IC_IDMAC_2);
++ ipu_ic_write(ipu, ic_idmac_3, IC_IDMAC_3);
++ return 0;
++}
++
++static void _init_csc(struct ipu_soc *ipu, uint8_t ic_task, ipu_color_space_t in_format,
++ ipu_color_space_t out_format, int csc_index)
++{
++ /*
++ * Y = 0.257 * R + 0.504 * G + 0.098 * B + 16;
++ * U = -0.148 * R - 0.291 * G + 0.439 * B + 128;
++ * V = 0.439 * R - 0.368 * G - 0.071 * B + 128;
++ */
++ static const uint32_t rgb2ycbcr_coeff[4][3] = {
++ {0x0042, 0x0081, 0x0019},
++ {0x01DA, 0x01B6, 0x0070},
++ {0x0070, 0x01A2, 0x01EE},
++ {0x0040, 0x0200, 0x0200}, /* A0, A1, A2 */
++ };
++
++ /* transparent RGB->RGB matrix for combining
++ */
++ static const uint32_t rgb2rgb_coeff[4][3] = {
++ {0x0080, 0x0000, 0x0000},
++ {0x0000, 0x0080, 0x0000},
++ {0x0000, 0x0000, 0x0080},
++ {0x0000, 0x0000, 0x0000}, /* A0, A1, A2 */
++ };
++
++/* R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
++ G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
++ B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128); */
++ static const uint32_t ycbcr2rgb_coeff[4][3] = {
++ {149, 0, 204},
++ {149, 462, 408},
++ {149, 255, 0},
++ {8192 - 446, 266, 8192 - 554}, /* A0, A1, A2 */
++ };
++
++ uint32_t param;
++ uint32_t *base = NULL;
++
++ if (ic_task == IC_TASK_ENCODER) {
++ base = (uint32_t *)ipu->tpmem_base + 0x2008 / 4;
++ } else if (ic_task == IC_TASK_VIEWFINDER) {
++ if (csc_index == 1)
++ base = (uint32_t *)ipu->tpmem_base + 0x4028 / 4;
++ else
++ base = (uint32_t *)ipu->tpmem_base + 0x4040 / 4;
++ } else if (ic_task == IC_TASK_POST_PROCESSOR) {
++ if (csc_index == 1)
++ base = (uint32_t *)ipu->tpmem_base + 0x6060 / 4;
++ else
++ base = (uint32_t *)ipu->tpmem_base + 0x6078 / 4;
++ } else {
++ BUG();
++ }
++
++ if ((in_format == YCbCr) && (out_format == RGB)) {
++ /* Init CSC (YCbCr->RGB) */
++ param = (ycbcr2rgb_coeff[3][0] << 27) |
++ (ycbcr2rgb_coeff[0][0] << 18) |
++ (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
++ writel(param, base++);
++ /* scale = 2, sat = 0 */
++ param = (ycbcr2rgb_coeff[3][0] >> 5) | (2L << (40 - 32));
++ writel(param, base++);
++
++ param = (ycbcr2rgb_coeff[3][1] << 27) |
++ (ycbcr2rgb_coeff[0][1] << 18) |
++ (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
++ writel(param, base++);
++ param = (ycbcr2rgb_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param = (ycbcr2rgb_coeff[3][2] << 27) |
++ (ycbcr2rgb_coeff[0][2] << 18) |
++ (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
++ writel(param, base++);
++ param = (ycbcr2rgb_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else if ((in_format == RGB) && (out_format == YCbCr)) {
++ /* Init CSC (RGB->YCbCr) */
++ param = (rgb2ycbcr_coeff[3][0] << 27) |
++ (rgb2ycbcr_coeff[0][0] << 18) |
++ (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
++ writel(param, base++);
++ /* scale = 1, sat = 0 */
++ param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
++ writel(param, base++);
++
++ param = (rgb2ycbcr_coeff[3][1] << 27) |
++ (rgb2ycbcr_coeff[0][1] << 18) |
++ (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
++ writel(param, base++);
++ param = (rgb2ycbcr_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param = (rgb2ycbcr_coeff[3][2] << 27) |
++ (rgb2ycbcr_coeff[0][2] << 18) |
++ (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
++ writel(param, base++);
++ param = (rgb2ycbcr_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else if ((in_format == RGB) && (out_format == RGB)) {
++ /* Init CSC */
++ param =
++ (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
++ (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
++ writel(param, base++);
++ /* scale = 2, sat = 0 */
++ param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
++ writel(param, base++);
++
++ param =
++ (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
++ (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
++ writel(param, base++);
++ param = (rgb2rgb_coeff[3][1] >> 5);
++ writel(param, base++);
++
++ param =
++ (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
++ (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
++ writel(param, base++);
++ param = (rgb2rgb_coeff[3][2] >> 5);
++ writel(param, base++);
++ } else {
++ dev_err(ipu->dev, "Unsupported color space conversion\n");
++ }
++}
++
++static int _calc_resize_coeffs(struct ipu_soc *ipu,
++ uint32_t inSize, uint32_t outSize,
++ uint32_t *resizeCoeff,
++ uint32_t *downsizeCoeff)
++{
++ uint32_t tempSize;
++ uint32_t tempDownsize;
++
++ if (inSize > 4096) {
++ dev_err(ipu->dev, "IC input size(%d) cannot exceed 4096\n",
++ inSize);
++ return -EINVAL;
++ }
++
++ if (outSize > 1024) {
++ dev_err(ipu->dev, "IC output size(%d) cannot exceed 1024\n",
++ outSize);
++ return -EINVAL;
++ }
++
++ if ((outSize << 3) < inSize) {
++ dev_err(ipu->dev, "IC cannot downsize more than 8:1\n");
++ return -EINVAL;
++ }
++
++ /* Compute downsizing coefficient */
++ /* Output of downsizing unit cannot be more than 1024 */
++ tempDownsize = 0;
++ tempSize = inSize;
++ while (((tempSize > 1024) || (tempSize >= outSize * 2)) &&
++ (tempDownsize < 2)) {
++ tempSize >>= 1;
++ tempDownsize++;
++ }
++ *downsizeCoeff = tempDownsize;
++
++ /* compute resizing coefficient using the following equation:
++ resizeCoeff = M*(SI -1)/(SO - 1)
++ where M = 2^13, SI - input size, SO - output size */
++ *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1);
++ if (*resizeCoeff >= 16384L) {
++ dev_err(ipu->dev, "Overflow on IC resize coefficient.\n");
++ return -EINVAL;
++ }
++
++ dev_dbg(ipu->dev, "resizing from %u -> %u pixels, "
++ "downsize=%u, resize=%u.%lu (reg=%u)\n", inSize, outSize,
++ *downsizeCoeff, (*resizeCoeff >= 8192L) ? 1 : 0,
++ ((*resizeCoeff & 0x1FFF) * 10000L) / 8192L, *resizeCoeff);
++
++ return 0;
++}
++
++void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu)
++{
++ uint32_t reg;
++ uint32_t mask_reg;
++
++ reg = ipu_vdi_read(ipu, VDI_C);
++ mask_reg = reg & VDI_C_TOP_FIELD_MAN_1;
++ if (mask_reg == VDI_C_TOP_FIELD_MAN_1)
++ reg &= ~VDI_C_TOP_FIELD_MAN_1;
++ else
++ reg |= VDI_C_TOP_FIELD_MAN_1;
++
++ ipu_vdi_write(ipu, reg, VDI_C);
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_param_mem.h linux-3.14.72/drivers/mxc/ipu3/ipu_param_mem.h
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_param_mem.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_param_mem.h 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,921 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __INCLUDE_IPU_PARAM_MEM_H__
++#define __INCLUDE_IPU_PARAM_MEM_H__
++
++#include <linux/bitrev.h>
++#include <linux/types.h>
++
++#include "ipu_prv.h"
++
++extern u32 *ipu_cpmem_base;
++
++struct ipu_ch_param_word {
++ uint32_t data[5];
++ uint32_t res[3];
++};
++
++struct ipu_ch_param {
++ struct ipu_ch_param_word word[2];
++};
++
++#define ipu_ch_param_addr(ipu, ch) (((struct ipu_ch_param *)ipu->cpmem_base) + (ch))
++
++#define _param_word(base, w) \
++ (((struct ipu_ch_param *)(base))->word[(w)].data)
++
++#define ipu_ch_param_set_field(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ _param_word(base, w)[i] |= (v) << off; \
++ if (((bit)+(size)-1)/32 > i) { \
++ _param_word(base, w)[i + 1] |= (v) >> (off ? (32 - off) : 0); \
++ } \
++}
++
++#define ipu_ch_param_set_field_io(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ unsigned reg_offset; \
++ u32 temp; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp |= (v) << off; \
++ writel(temp, (u32 *)base + reg_offset); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp |= (v) >> (off ? (32 - off) : 0); \
++ writel(temp, (u32 *)base + reg_offset); \
++ } \
++}
++
++#define ipu_ch_param_mod_field(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ u32 temp = _param_word(base, w)[i]; \
++ temp &= ~(mask << off); \
++ _param_word(base, w)[i] = temp | (v) << off; \
++ if (((bit)+(size)-1)/32 > i) { \
++ temp = _param_word(base, w)[i + 1]; \
++ temp &= ~(mask >> (32 - off)); \
++ _param_word(base, w)[i + 1] = \
++ temp | ((v) >> (off ? (32 - off) : 0)); \
++ } \
++}
++
++#define ipu_ch_param_mod_field_io(base, w, bit, size, v) { \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ unsigned reg_offset; \
++ u32 temp; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp &= ~(mask << off); \
++ temp |= (v) << off; \
++ writel(temp, (u32 *)base + reg_offset); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp = readl((u32 *)base + reg_offset); \
++ temp &= ~(mask >> (32 - off)); \
++ temp |= ((v) >> (off ? (32 - off) : 0)); \
++ writel(temp, (u32 *)base + reg_offset); \
++ } \
++}
++
++#define ipu_ch_param_read_field(base, w, bit, size) ({ \
++ u32 temp2; \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ u32 temp1 = _param_word(base, w)[i]; \
++ temp1 = mask & (temp1 >> off); \
++ if (((bit)+(size)-1)/32 > i) { \
++ temp2 = _param_word(base, w)[i + 1]; \
++ temp2 &= mask >> (off ? (32 - off) : 0); \
++ temp1 |= temp2 << (off ? (32 - off) : 0); \
++ } \
++ temp1; \
++})
++
++#define ipu_ch_param_read_field_io(base, w, bit, size) ({ \
++ u32 temp1, temp2; \
++ int i = (bit) / 32; \
++ int off = (bit) % 32; \
++ u32 mask = (1UL << size) - 1; \
++ unsigned reg_offset; \
++ reg_offset = sizeof(struct ipu_ch_param_word) * w / 4; \
++ reg_offset += i; \
++ temp1 = readl((u32 *)base + reg_offset); \
++ temp1 = mask & (temp1 >> off); \
++ if (((bit)+(size)-1)/32 > i) { \
++ reg_offset++; \
++ temp2 = readl((u32 *)base + reg_offset); \
++ temp2 &= mask >> (off ? (32 - off) : 0); \
++ temp1 |= temp2 << (off ? (32 - off) : 0); \
++ } \
++ temp1; \
++})
++
++static inline int __ipu_ch_get_third_buf_cpmem_num(int ch)
++{
++ switch (ch) {
++ case 8:
++ return 64;
++ case 9:
++ return 65;
++ case 10:
++ return 66;
++ case 13:
++ return 67;
++ case 21:
++ return 68;
++ case 23:
++ return 69;
++ case 27:
++ return 70;
++ case 28:
++ return 71;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static inline void _ipu_ch_params_set_packing(struct ipu_ch_param *p,
++ int red_width, int red_offset,
++ int green_width, int green_offset,
++ int blue_width, int blue_offset,
++ int alpha_width, int alpha_offset)
++{
++ /* Setup red width and offset */
++ ipu_ch_param_set_field(p, 1, 116, 3, red_width - 1);
++ ipu_ch_param_set_field(p, 1, 128, 5, red_offset);
++ /* Setup green width and offset */
++ ipu_ch_param_set_field(p, 1, 119, 3, green_width - 1);
++ ipu_ch_param_set_field(p, 1, 133, 5, green_offset);
++ /* Setup blue width and offset */
++ ipu_ch_param_set_field(p, 1, 122, 3, blue_width - 1);
++ ipu_ch_param_set_field(p, 1, 138, 5, blue_offset);
++ /* Setup alpha width and offset */
++ ipu_ch_param_set_field(p, 1, 125, 3, alpha_width - 1);
++ ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
++}
++
++static inline void _ipu_ch_param_dump(struct ipu_soc *ipu, int ch)
++{
++ struct ipu_ch_param *p = ipu_ch_param_addr(ipu, ch);
++ dev_dbg(ipu->dev, "ch %d word 0 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[0].data[0], p->word[0].data[1], p->word[0].data[2],
++ p->word[0].data[3], p->word[0].data[4]);
++ dev_dbg(ipu->dev, "ch %d word 1 - %08X %08X %08X %08X %08X\n", ch,
++ p->word[1].data[0], p->word[1].data[1], p->word[1].data[2],
++ p->word[1].data[3], p->word[1].data[4]);
++ dev_dbg(ipu->dev, "PFS 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 85, 4));
++ dev_dbg(ipu->dev, "BPP 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3));
++ dev_dbg(ipu->dev, "NPB 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7));
++
++ dev_dbg(ipu->dev, "FW %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 125, 13));
++ dev_dbg(ipu->dev, "FH %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 138, 12));
++ dev_dbg(ipu->dev, "EBA0 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 0, 29) << 3);
++ dev_dbg(ipu->dev, "EBA1 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 29, 29) << 3);
++ dev_dbg(ipu->dev, "Stride %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14));
++ dev_dbg(ipu->dev, "scan_order %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 113, 1));
++ dev_dbg(ipu->dev, "uv_stride %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 128, 14));
++ dev_dbg(ipu->dev, "u_offset 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22) << 3);
++ dev_dbg(ipu->dev, "v_offset 0x%x\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22) << 3);
++
++ dev_dbg(ipu->dev, "Width0 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 116, 3));
++ dev_dbg(ipu->dev, "Width1 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 119, 3));
++ dev_dbg(ipu->dev, "Width2 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 122, 3));
++ dev_dbg(ipu->dev, "Width3 %d+1, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3));
++ dev_dbg(ipu->dev, "Offset0 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 128, 5));
++ dev_dbg(ipu->dev, "Offset1 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 133, 5));
++ dev_dbg(ipu->dev, "Offset2 %d, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 138, 5));
++ dev_dbg(ipu->dev, "Offset3 %d\n",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 143, 5));
++}
++
++static inline void fill_cpmem(struct ipu_soc *ipu, int ch, struct ipu_ch_param *params)
++{
++ int i, w;
++ void *addr = ipu_ch_param_addr(ipu, ch);
++
++ /* 2 words, 5 valid data */
++ for (w = 0; w < 2; w++) {
++ for (i = 0; i < 5; i++) {
++ writel(params->word[w].data[i], addr);
++ addr += 4;
++ }
++ addr += 12;
++ }
++}
++
++static inline void _ipu_ch_param_init(struct ipu_soc *ipu, int ch,
++ uint32_t pixel_fmt, uint32_t width,
++ uint32_t height, uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t uv_stride, dma_addr_t addr0,
++ dma_addr_t addr1, dma_addr_t addr2)
++{
++ uint32_t u_offset = 0;
++ uint32_t v_offset = 0;
++ int32_t sub_ch = 0;
++ struct ipu_ch_param params;
++
++ memset(&params, 0, sizeof(params));
++
++ ipu_ch_param_set_field(&params, 0, 125, 13, width - 1);
++
++ if (((ch == 8) || (ch == 9) || (ch == 10)) && !ipu->vdoa_en) {
++ ipu_ch_param_set_field(&params, 0, 138, 12, (height / 2) - 1);
++ ipu_ch_param_set_field(&params, 1, 102, 14, (stride * 2) - 1);
++ } else {
++ /* note: for vdoa+vdi- ch8/9/10, always use band mode */
++ ipu_ch_param_set_field(&params, 0, 138, 12, height - 1);
++ ipu_ch_param_set_field(&params, 1, 102, 14, stride - 1);
++ }
++
++ /* EBA is 8-byte aligned */
++ ipu_ch_param_set_field(&params, 1, 0, 29, addr0 >> 3);
++ ipu_ch_param_set_field(&params, 1, 29, 29, addr1 >> 3);
++ if (addr0%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's EBA0 is not 8-byte aligned\n", ch);
++ if (addr1%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's EBA1 is not 8-byte aligned\n", ch);
++
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ /*Represents 8-bit Generic data */
++ ipu_ch_param_set_field(&params, 0, 107, 3, 5); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 63); /* burst size */
++
++ break;
++ case IPU_PIX_FMT_GENERIC_16:
++ /* Represents 16-bit generic data */
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 6); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ break;
++ case IPU_PIX_FMT_GENERIC_32:
++ /*Represents 32-bit Generic data */
++ break;
++ case IPU_PIX_FMT_RGB565:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 5, 0, 6, 5, 5, 11, 8, 16);
++ break;
++ case IPU_PIX_FMT_BGR24:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 16, 8, 8, 8, 0, 8, 24);
++ break;
++ case IPU_PIX_FMT_VYU444:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 1); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 19); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 8, 8, 0, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 8, 8, 16, 8, 24, 8, 0);
++ break;
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 24, 8, 16, 8, 8, 8, 0);
++ break;
++ case IPU_PIX_FMT_ABGR32:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 0); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 7); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++
++ _ipu_ch_params_set_packing(&params, 8, 0, 8, 8, 8, 16, 8, 24);
++ break;
++ case IPU_PIX_FMT_UYVY:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0xA); /* pix format */
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YUYV:
++ ipu_ch_param_set_field(&params, 0, 107, 3, 3); /* bits/pixel */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0x8); /* pix format */
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ if (ipu->vdoa_en) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31);
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15);
++ }
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ ipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * height;
++ v_offset = u_offset + (uv_stride * height / 2);
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ uv_stride = uv_stride*2;
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ ipu_ch_param_set_field(&params, 1, 85, 4, 2); /* pix format */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * height;
++ u_offset = v_offset + (uv_stride * height / 2);
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15); /* burst size */
++ uv_stride = uv_stride*2;
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = (v == 0) ? stride * height : v;
++ u_offset = (u == 0) ? v_offset + v_offset / 2 : u;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 1); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = (u == 0) ? stride * height : u;
++ v_offset = (v == 0) ? u_offset + u_offset / 2 : v;
++ break;
++ case IPU_PIX_FMT_YUV444P:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 0); /* pix format */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ uv_stride = stride;
++ u_offset = (u == 0) ? stride * height : u;
++ v_offset = (v == 0) ? u_offset * 2 : v;
++ break;
++ case IPU_PIX_FMT_NV12:
++ /* BPP & pixel format */
++ ipu_ch_param_set_field(&params, 1, 85, 4, 4); /* pix format */
++ uv_stride = stride;
++ u_offset = (u == 0) ? stride * height : u;
++ if ((ch == 8) || (ch == 9) || (ch == 10)) {
++ if (ipu->vdoa_en) {
++ /* one field buffer, memory width 64bits */
++ ipu_ch_param_set_field(&params, 1, 78, 7, 63);
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 15);
++ /* top/bottom field in one buffer*/
++ uv_stride = uv_stride*2;
++ }
++ } else {
++ ipu_ch_param_set_field(&params, 1, 78, 7, 31); /* burst size */
++ }
++ break;
++ default:
++ dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
++ break;
++ }
++ /*set burst size to 16*/
++
++
++ if (uv_stride)
++ ipu_ch_param_set_field(&params, 1, 128, 14, uv_stride - 1);
++
++ /* Get the uv offset from user when need cropping */
++ if (u || v) {
++ u_offset = u;
++ v_offset = v;
++ }
++
++ /* UBO and VBO are 22-bit and 8-byte aligned */
++ if (u_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset exceeds IPU limitation\n", ch);
++ if (v_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset exceeds IPU limitation\n", ch);
++ if (u_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset is not 8-byte aligned\n", ch);
++ if (v_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset is not 8-byte aligned\n", ch);
++
++ ipu_ch_param_set_field(&params, 0, 46, 22, u_offset / 8);
++ ipu_ch_param_set_field(&params, 0, 68, 22, v_offset / 8);
++
++ dev_dbg(ipu->dev, "initializing idma ch %d @ %p\n", ch, ipu_ch_param_addr(ipu, ch));
++ fill_cpmem(ipu, ch, &params);
++ if (addr2) {
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++
++ ipu_ch_param_set_field(&params, 1, 0, 29, addr2 >> 3);
++ ipu_ch_param_set_field(&params, 1, 29, 29, 0);
++ if (addr2%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's sub-CPMEM entry%d EBA0 is not "
++ "8-byte aligned\n", ch, sub_ch);
++
++ dev_dbg(ipu->dev, "initializing idma ch %d @ %p sub cpmem\n", ch,
++ ipu_ch_param_addr(ipu, sub_ch));
++ fill_cpmem(ipu, sub_ch, &params);
++ }
++};
++
++static inline void _ipu_ch_param_set_burst_size(struct ipu_soc *ipu,
++ uint32_t ch,
++ uint16_t burst_pixels)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7,
++ burst_pixels - 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 78, 7,
++ burst_pixels - 1);
++};
++
++static inline int _ipu_ch_param_get_burst_size(struct ipu_soc *ipu, uint32_t ch)
++{
++ return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 78, 7) + 1;
++};
++
++static inline int _ipu_ch_param_get_bpp(struct ipu_soc *ipu, uint32_t ch)
++{
++ return ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 107, 3);
++};
++
++static inline void _ipu_ch_param_set_buffer(struct ipu_soc *ipu, uint32_t ch,
++ int bufNum, dma_addr_t phyaddr)
++{
++ if (bufNum == 2) {
++ ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (ch <= 0)
++ return;
++ bufNum = 0;
++ }
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 29 * bufNum, 29,
++ phyaddr / 8);
++};
++
++static inline void _ipu_ch_param_set_rotation(struct ipu_soc *ipu, uint32_t ch,
++ ipu_rotate_mode_t rot)
++{
++ u32 temp_rot = bitrev8(rot) >> 5;
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 119, 3, temp_rot);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 119, 3, temp_rot);
++};
++
++static inline void _ipu_ch_param_set_block_mode(struct ipu_soc *ipu, uint32_t ch)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 117, 2, 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 117, 2, 1);
++};
++
++static inline void _ipu_ch_param_set_alpha_use_separate_channel(struct ipu_soc *ipu,
++ uint32_t ch,
++ bool option)
++{
++ int32_t sub_ch = 0;
++
++ if (option) {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 1);
++ } else {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 89, 1, 0);
++ }
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++
++ if (option) {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 1);
++ } else {
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 89, 1, 0);
++ }
++};
++
++static inline void _ipu_ch_param_set_alpha_condition_read(struct ipu_soc *ipu, uint32_t ch)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 149, 1, 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 149, 1, 1);
++};
++
++static inline void _ipu_ch_param_set_alpha_buffer_memory(struct ipu_soc *ipu, uint32_t ch)
++{
++ int alp_mem_idx;
++ int32_t sub_ch = 0;
++
++ switch (ch) {
++ case 14: /* PRP graphic */
++ alp_mem_idx = 0;
++ break;
++ case 15: /* PP graphic */
++ alp_mem_idx = 1;
++ break;
++ case 23: /* DP BG SYNC graphic */
++ alp_mem_idx = 4;
++ break;
++ case 27: /* DP FG SYNC graphic */
++ alp_mem_idx = 2;
++ break;
++ default:
++ dev_err(ipu->dev, "unsupported correlative channel of local "
++ "alpha channel\n");
++ return;
++ }
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 90, 3, alp_mem_idx);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 90, 3, alp_mem_idx);
++};
++
++static inline void _ipu_ch_param_set_interlaced_scan(struct ipu_soc *ipu, uint32_t ch)
++{
++ u32 stride;
++ int32_t sub_ch = 0;
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 0, 113, 1, 1);
++ if (sub_ch > 0)
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 113, 1, 1);
++ stride = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14) + 1;
++ /* ILO is 20-bit and 8-byte aligned */
++ if (stride/8 > 0xfffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's ILO exceeds IPU limitation\n", ch);
++ if (stride%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's ILO is not 8-byte aligned\n", ch);
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 58, 20, stride / 8);
++ if (sub_ch > 0)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 58, 20,
++ stride / 8);
++ stride *= 2;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 102, 14, stride - 1);
++ if (sub_ch > 0)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 102, 14,
++ stride - 1);
++};
++
++static inline void _ipu_ch_param_set_axi_id(struct ipu_soc *ipu, uint32_t ch, uint32_t id)
++{
++ int32_t sub_ch = 0;
++
++ id %= 4;
++
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 1, 93, 2, id);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 93, 2, id);
++};
++
++/* IDMAC U/V offset changing support */
++/* U and V input is not affected, */
++/* the update is done by new calculation according to */
++/* vertical_offset and horizontal_offset */
++static inline void _ipu_ch_offset_update(struct ipu_soc *ipu,
++ int ch,
++ uint32_t pixel_fmt,
++ uint32_t width,
++ uint32_t height,
++ uint32_t stride,
++ uint32_t u,
++ uint32_t v,
++ uint32_t uv_stride,
++ uint32_t vertical_offset,
++ uint32_t horizontal_offset)
++{
++ uint32_t u_offset = 0;
++ uint32_t v_offset = 0;
++ uint32_t old_offset = 0;
++ uint32_t u_fix = 0;
++ uint32_t v_fix = 0;
++ int32_t sub_ch = 0;
++
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_GENERIC:
++ case IPU_PIX_FMT_GENERIC_16:
++ case IPU_PIX_FMT_GENERIC_32:
++ case IPU_PIX_FMT_RGB565:
++ case IPU_PIX_FMT_BGR24:
++ case IPU_PIX_FMT_RGB24:
++ case IPU_PIX_FMT_YUV444:
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ case IPU_PIX_FMT_ABGR32:
++ case IPU_PIX_FMT_UYVY:
++ case IPU_PIX_FMT_YUYV:
++ break;
++
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YUV420P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset / 2;
++ v_offset = u_offset + (uv_stride * height / 2);
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++
++ break;
++ case IPU_PIX_FMT_YVU420P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset / 2;
++ u_offset = v_offset + (uv_stride * height / 2);
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset / 2) +
++ (horizontal_offset / 2) -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++
++ break;
++ case IPU_PIX_FMT_YVU422P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ v_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset / 2;
++ u_offset = v_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++ break;
++ case IPU_PIX_FMT_YUV422P:
++ if (uv_stride < stride / 2)
++ uv_stride = stride / 2;
++
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset / 2;
++ v_offset = u_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset / 2 -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ v_offset;
++ break;
++
++ case IPU_PIX_FMT_YUV444P:
++ uv_stride = stride;
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset) +
++ horizontal_offset;
++ v_offset = u_offset + uv_stride * height;
++ u_fix = u ? (u + (uv_stride * vertical_offset) +
++ horizontal_offset -
++ (stride * vertical_offset) -
++ (horizontal_offset)) :
++ u_offset;
++ v_fix = v ? (v + (uv_stride * vertical_offset) +
++ horizontal_offset -
++ (stride * vertical_offset) -
++ (horizontal_offset)) :
++ v_offset;
++ break;
++ case IPU_PIX_FMT_NV12:
++ uv_stride = stride;
++ u_offset = stride * (height - vertical_offset - 1) +
++ (stride - horizontal_offset) +
++ (uv_stride * vertical_offset / 2) +
++ horizontal_offset;
++ u_fix = u ? (u + (uv_stride * vertical_offset / 2) +
++ horizontal_offset -
++ (stride * vertical_offset) - (horizontal_offset)) :
++ u_offset;
++
++ break;
++ default:
++ dev_err(ipu->dev, "mxc ipu: unimplemented pixel format\n");
++ break;
++ }
++
++
++
++ if (u_fix > u_offset)
++ u_offset = u_fix;
++
++ if (v_fix > v_offset)
++ v_offset = v_fix;
++
++ /* UBO and VBO are 22-bit and 8-byte aligned */
++ if (u_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset exceeds IPU limitation\n", ch);
++ if (v_offset/8 > 0x3fffff)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset exceeds IPU limitation\n", ch);
++ if (u_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's U offset is not 8-byte aligned\n", ch);
++ if (v_offset%8)
++ dev_warn(ipu->dev,
++ "IDMAC%d's V offset is not 8-byte aligned\n", ch);
++
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22);
++ if (old_offset != u_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 46, 22, u_offset / 8);
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22);
++ if (old_offset != v_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, ch), 0, 68, 22, v_offset / 8);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22);
++ if (old_offset != u_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 46, 22, u_offset / 8);
++ old_offset = ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22);
++ if (old_offset != v_offset / 8)
++ ipu_ch_param_mod_field_io(ipu_ch_param_addr(ipu, sub_ch), 0, 68, 22, v_offset / 8);
++};
++
++static inline void _ipu_ch_params_set_alpha_width(struct ipu_soc *ipu, uint32_t ch, int alpha_width)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch), 1, 125, 3, alpha_width - 1);
++
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch), 1, 125, 3, alpha_width - 1);
++};
++
++static inline void _ipu_ch_param_set_bandmode(struct ipu_soc *ipu,
++ uint32_t ch, uint32_t band_height)
++{
++ int32_t sub_ch = 0;
++
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, ch),
++ 0, 114, 3, band_height - 1);
++ sub_ch = __ipu_ch_get_third_buf_cpmem_num(ch);
++ if (sub_ch <= 0)
++ return;
++ ipu_ch_param_set_field_io(ipu_ch_param_addr(ipu, sub_ch),
++ 0, 114, 3, band_height - 1);
++
++ dev_dbg(ipu->dev, "BNDM 0x%x, ",
++ ipu_ch_param_read_field_io(ipu_ch_param_addr(ipu, ch), 0, 114, 3));
++}
++
++/*
++ * The IPUv3 IDMAC has a bug to read 32bpp pixels from a graphics plane
++ * whose alpha component is at the most significant 8 bits. The bug only
++ * impacts on cases in which the relevant separate alpha channel is enabled.
++ *
++ * Return true on bad alpha component position, otherwise, return false.
++ */
++static inline bool _ipu_ch_param_bad_alpha_pos(uint32_t pixel_fmt)
++{
++ switch (pixel_fmt) {
++ case IPU_PIX_FMT_BGRA32:
++ case IPU_PIX_FMT_BGR32:
++ case IPU_PIX_FMT_RGBA32:
++ case IPU_PIX_FMT_RGB32:
++ return true;
++ }
++
++ return false;
++}
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_pixel_clk.c linux-3.14.72/drivers/mxc/ipu3/ipu_pixel_clk.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_pixel_clk.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_pixel_clk.c 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,317 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file ipu_pixel_clk.c
++ *
++ * @brief IPU pixel clock implementation
++ *
++ * @ingroup IPU
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ipu-v3.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++
++#include "ipu_prv.h"
++#include "ipu_regs.h"
++
++ /*
++ * muxd clock implementation
++ */
++struct clk_di_mux {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++ u8 index;
++};
++#define to_clk_di_mux(_hw) container_of(_hw, struct clk_di_mux, hw)
++
++static int _ipu_pixel_clk_set_parent(struct clk_hw *hw, u8 index)
++{
++ struct clk_di_mux *mux = to_clk_di_mux(hw);
++ struct ipu_soc *ipu = ipu_get_soc(mux->ipu_id);
++ u32 di_gen;
++
++ di_gen = ipu_di_read(ipu, mux->di_id, DI_GENERAL);
++ if (index == 0)
++ /* ipu1_clk or ipu2_clk internal clk */
++ di_gen &= ~DI_GEN_DI_CLK_EXT;
++ else
++ di_gen |= DI_GEN_DI_CLK_EXT;
++
++ ipu_di_write(ipu, mux->di_id, di_gen, DI_GENERAL);
++ mux->index = index;
++ pr_debug("ipu_pixel_clk: di_clk_ext:0x%x, di_gen reg:0x%x.\n",
++ !(di_gen & DI_GEN_DI_CLK_EXT), di_gen);
++ return 0;
++}
++
++static u8 _ipu_pixel_clk_get_parent(struct clk_hw *hw)
++{
++ struct clk_di_mux *mux = to_clk_di_mux(hw);
++
++ return mux->index;
++}
++
++const struct clk_ops clk_mux_di_ops = {
++ .get_parent = _ipu_pixel_clk_get_parent,
++ .set_parent = _ipu_pixel_clk_set_parent,
++};
++
++struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
++ const char **parent_names, u8 num_parents, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_mux_flags)
++{
++ struct clk_di_mux *mux;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ mux = kzalloc(sizeof(struct clk_di_mux), GFP_KERNEL);
++ if (!mux)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.ops = &clk_mux_di_ops;
++ init.flags = flags;
++ init.parent_names = parent_names;
++ init.num_parents = num_parents;
++
++ mux->ipu_id = ipu_id;
++ mux->di_id = di_id;
++ mux->flags = clk_mux_flags | CLK_SET_RATE_PARENT;
++ mux->hw.init = &init;
++
++ clk = clk_register(dev, &mux->hw);
++ if (IS_ERR(clk))
++ kfree(mux);
++
++ return clk;
++}
++
++/*
++ * Gated clock implementation
++ */
++struct clk_di_div {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++};
++#define to_clk_di_div(_hw) container_of(_hw, struct clk_di_div, hw)
++
++static unsigned long _ipu_pixel_clk_div_recalc_rate(struct clk_hw *hw,
++ unsigned long parent_rate)
++{
++ struct clk_di_div *di_div = to_clk_di_div(hw);
++ struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
++ u32 div;
++ u64 final_rate = (unsigned long long)parent_rate * 16;
++
++ _ipu_get(ipu);
++ div = ipu_di_read(ipu, di_div->di_id, DI_BS_CLKGEN0);
++ _ipu_put(ipu);
++ pr_debug("ipu_di%d read BS_CLKGEN0 div:%d, final_rate:%lld, prate:%ld\n",
++ di_div->di_id, div, final_rate, parent_rate);
++
++ if (div == 0)
++ return 0;
++ do_div(final_rate, div);
++
++ return (unsigned long)final_rate;
++}
++
++static long _ipu_pixel_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long *parent_clk_rate)
++{
++ u64 div, final_rate;
++ u32 remainder;
++ u64 parent_rate = (unsigned long long)(*parent_clk_rate) * 16;
++
++ /*
++ * Calculate divider
++ * Fractional part is 4 bits,
++ * so simply multiply by 2^4 to get fractional part.
++ */
++ div = parent_rate;
++ remainder = do_div(div, rate);
++ /* Round the divider value */
++ if (remainder > (rate/2))
++ div++;
++ if (div < 0x10) /* Min DI disp clock divider is 1 */
++ div = 0x10;
++ if (div & ~0xFEF)
++ div &= 0xFF8;
++ else {
++ /* Round up divider if it gets us closer to desired pix clk */
++ if ((div & 0xC) == 0xC) {
++ div += 0x10;
++ div &= ~0xF;
++ }
++ }
++ final_rate = parent_rate;
++ do_div(final_rate, div);
++
++ return final_rate;
++}
++
++static int _ipu_pixel_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
++ unsigned long parent_clk_rate)
++{
++ struct clk_di_div *di_div = to_clk_di_div(hw);
++ struct ipu_soc *ipu = ipu_get_soc(di_div->ipu_id);
++ u64 div, parent_rate;
++ u32 remainder;
++
++ parent_rate = (unsigned long long)parent_clk_rate * 16;
++ div = parent_rate;
++ remainder = do_div(div, rate);
++ /* Round the divider value */
++ if (remainder > (rate/2))
++ div++;
++
++ /* Round up divider if it gets us closer to desired pix clk */
++ if ((div & 0xC) == 0xC) {
++ div += 0x10;
++ div &= ~0xF;
++ }
++ if (div > 0x1000)
++ pr_err("Overflow, di:%d, DI_BS_CLKGEN0 div:0x%x\n",
++ di_div->di_id, (u32)div);
++ _ipu_get(ipu);
++ ipu_di_write(ipu, di_div->di_id, (u32)div, DI_BS_CLKGEN0);
++
++ /* Setup pixel clock timing */
++ /* FIXME: needs to be more flexible */
++ /* Down time is half of period */
++ ipu_di_write(ipu, di_div->di_id, ((u32)div / 16) << 16, DI_BS_CLKGEN1);
++ _ipu_put(ipu);
++
++ return 0;
++}
++
++static struct clk_ops clk_div_ops = {
++ .recalc_rate = _ipu_pixel_clk_div_recalc_rate,
++ .round_rate = _ipu_pixel_clk_div_round_rate,
++ .set_rate = _ipu_pixel_clk_div_set_rate,
++};
++
++struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_div_flags)
++{
++ struct clk_di_div *di_div;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ di_div = kzalloc(sizeof(struct clk_di_div), GFP_KERNEL);
++ if (!di_div)
++ return ERR_PTR(-ENOMEM);
++
++ /* struct clk_di_div assignments */
++ di_div->ipu_id = ipu_id;
++ di_div->di_id = di_id;
++ di_div->flags = clk_div_flags;
++
++ init.name = name;
++ init.ops = &clk_div_ops;
++ init.flags = flags | CLK_SET_RATE_PARENT;
++ init.parent_names = parent_name ? &parent_name : NULL;
++ init.num_parents = parent_name ? 1 : 0;
++
++ di_div->hw.init = &init;
++
++ clk = clk_register(dev, &di_div->hw);
++ if (IS_ERR(clk))
++ kfree(clk);
++
++ return clk;
++}
++
++/*
++ * Gated clock implementation
++ */
++struct clk_di_gate {
++ struct clk_hw hw;
++ u8 ipu_id;
++ u8 di_id;
++ u8 flags;
++};
++#define to_clk_di_gate(_hw) container_of(_hw, struct clk_di_gate, hw)
++
++static int _ipu_pixel_clk_enable(struct clk_hw *hw)
++{
++ struct clk_di_gate *gate = to_clk_di_gate(hw);
++ struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
++ u32 disp_gen;
++
++ disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
++ disp_gen |= gate->di_id ? DI1_COUNTER_RELEASE : DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
++
++ return 0;
++}
++
++static void _ipu_pixel_clk_disable(struct clk_hw *hw)
++{
++ struct clk_di_gate *gate = to_clk_di_gate(hw);
++ struct ipu_soc *ipu = ipu_get_soc(gate->ipu_id);
++ u32 disp_gen;
++
++ disp_gen = ipu_cm_read(ipu, IPU_DISP_GEN);
++ disp_gen &= gate->di_id ? ~DI1_COUNTER_RELEASE : ~DI0_COUNTER_RELEASE;
++ ipu_cm_write(ipu, disp_gen, IPU_DISP_GEN);
++
++}
++
++
++static struct clk_ops clk_gate_di_ops = {
++ .enable = _ipu_pixel_clk_enable,
++ .disable = _ipu_pixel_clk_disable,
++};
++
++struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_gate_flags)
++{
++ struct clk_di_gate *gate;
++ struct clk *clk;
++ struct clk_init_data init;
++
++ gate = kzalloc(sizeof(struct clk_di_gate), GFP_KERNEL);
++ if (!gate)
++ return ERR_PTR(-ENOMEM);
++
++ gate->ipu_id = ipu_id;
++ gate->di_id = di_id;
++ gate->flags = clk_gate_flags;
++
++ init.name = name;
++ init.ops = &clk_gate_di_ops;
++ init.flags = flags | CLK_SET_RATE_PARENT;
++ init.parent_names = parent_name ? &parent_name : NULL;
++ init.num_parents = parent_name ? 1 : 0;
++
++ gate->hw.init = &init;
++
++ clk = clk_register(dev, &gate->hw);
++ if (IS_ERR(clk))
++ kfree(clk);
++
++ return clk;
++}
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_prv.h linux-3.14.72/drivers/mxc/ipu3/ipu_prv.h
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_prv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_prv.h 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,364 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __INCLUDE_IPU_PRV_H__
++#define __INCLUDE_IPU_PRV_H__
++
++#include <linux/clkdev.h>
++#include <linux/device.h>
++#include <linux/fsl_devices.h>
++#include <linux/interrupt.h>
++#include <linux/types.h>
++
++#define MXC_IPU_MAX_NUM 2
++#define MXC_DI_NUM_PER_IPU 2
++
++/* Globals */
++extern int dmfc_type_setup;
++
++#define IDMA_CHAN_INVALID 0xFF
++#define HIGH_RESOLUTION_WIDTH 1024
++
++struct ipu_irq_node {
++ irqreturn_t(*handler) (int, void *); /*!< the ISR */
++ const char *name; /*!< device associated with the interrupt */
++ void *dev_id; /*!< some unique information for the ISR */
++ __u32 flags; /*!< not used */
++};
++
++enum csc_type_t {
++ RGB2YUV = 0,
++ YUV2RGB,
++ RGB2RGB,
++ YUV2YUV,
++ CSC_NONE,
++ CSC_NUM
++};
++
++enum imx_ipu_type {
++ IMX6Q_IPU,
++};
++
++struct ipu_pltfm_data {
++ u32 id;
++ u32 devtype;
++ int (*init) (int);
++ void (*pg) (int);
++
++ /*
++ * Bypass reset to avoid display channel being
++ * stopped by probe since it may starts to work
++ * in bootloader.
++ */
++ bool bypass_reset;
++};
++
++struct ipu_soc;
++
++struct ipu_chan {
++ struct ipu_soc *ipu;
++ ipu_channel_t channel;
++ struct ipu_chan **p_ipu_chan;
++};
++
++struct ipu_soc {
++ bool online;
++ struct ipu_pltfm_data *pdata;
++
++ /*clk*/
++ struct clk *ipu_clk;
++ struct clk *di_clk[2];
++ struct clk *di_clk_sel[2];
++ struct clk *pixel_clk[2];
++ struct clk *pixel_clk_sel[2];
++ struct clk *csi_clk[2];
++
++ /*irq*/
++ int irq_sync;
++ int irq_err;
++ struct ipu_irq_node irq_list[IPU_IRQ_COUNT];
++ struct ipu_chan chan[32];
++ /*reg*/
++ void __iomem *cm_reg;
++ void __iomem *idmac_reg;
++ void __iomem *dp_reg;
++ void __iomem *ic_reg;
++ void __iomem *dc_reg;
++ void __iomem *dc_tmpl_reg;
++ void __iomem *dmfc_reg;
++ void __iomem *di_reg[2];
++ void __iomem *smfc_reg;
++ void __iomem *csi_reg[2];
++ void __iomem *cpmem_base;
++ void __iomem *tpmem_base;
++ void __iomem *disp_base[2];
++ void __iomem *vdi_reg;
++
++ struct device *dev;
++
++ ipu_channel_t csi_channel[2];
++ ipu_channel_t using_ic_dirct_ch;
++ unsigned char dc_di_assignment[10];
++ bool sec_chan_en[24];
++ bool thrd_chan_en[24];
++ bool chan_is_interlaced[52];
++ uint32_t channel_init_mask;
++ uint32_t channel_enable_mask;
++
++ /*use count*/
++ int dc_use_count;
++ int dp_use_count;
++ int dmfc_use_count;
++ int smfc_use_count;
++ int ic_use_count;
++ int rot_use_count;
++ int vdi_use_count;
++ int di_use_count[2];
++ int csi_use_count[2];
++
++ struct mutex mutex_lock;
++ spinlock_t int_reg_spin_lock;
++ spinlock_t rdy_reg_spin_lock;
++
++ int dmfc_size_28;
++ int dmfc_size_29;
++ int dmfc_size_24;
++ int dmfc_size_27;
++ int dmfc_size_23;
++
++ enum csc_type_t fg_csc_type;
++ enum csc_type_t bg_csc_type;
++ bool color_key_4rgb;
++ bool dc_swap;
++ struct completion dc_comp;
++ struct completion csi_comp;
++
++ struct rot_mem {
++ void *vaddr;
++ dma_addr_t paddr;
++ int size;
++ } rot_dma[2];
++
++ int vdoa_en;
++ struct task_struct *thread[2];
++
++};
++
++struct ipu_channel {
++ u8 video_in_dma;
++ u8 alpha_in_dma;
++ u8 graph_in_dma;
++ u8 out_dma;
++};
++
++enum ipu_dmfc_type {
++ DMFC_NORMAL = 0,
++ DMFC_HIGH_RESOLUTION_DC,
++ DMFC_HIGH_RESOLUTION_DP,
++ DMFC_HIGH_RESOLUTION_ONLY_DP,
++};
++
++static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->cm_reg + offset);
++}
++
++static inline void ipu_cm_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->cm_reg + offset);
++}
++
++static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->idmac_reg + offset);
++}
++
++static inline void ipu_idmac_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->idmac_reg + offset);
++}
++
++static inline u32 ipu_dc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dc_reg + offset);
++}
++
++static inline void ipu_dc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dc_reg + offset);
++}
++
++static inline u32 ipu_dc_tmpl_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dc_tmpl_reg + offset);
++}
++
++static inline void ipu_dc_tmpl_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dc_tmpl_reg + offset);
++}
++
++static inline u32 ipu_dmfc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dmfc_reg + offset);
++}
++
++static inline void ipu_dmfc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dmfc_reg + offset);
++}
++
++static inline u32 ipu_dp_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->dp_reg + offset);
++}
++
++static inline void ipu_dp_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->dp_reg + offset);
++}
++
++static inline u32 ipu_di_read(struct ipu_soc *ipu, int di, unsigned offset)
++{
++ return readl(ipu->di_reg[di] + offset);
++}
++
++static inline void ipu_di_write(struct ipu_soc *ipu, int di,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->di_reg[di] + offset);
++}
++
++static inline u32 ipu_csi_read(struct ipu_soc *ipu, int csi, unsigned offset)
++{
++ return readl(ipu->csi_reg[csi] + offset);
++}
++
++static inline void ipu_csi_write(struct ipu_soc *ipu, int csi,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->csi_reg[csi] + offset);
++}
++
++static inline u32 ipu_smfc_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->smfc_reg + offset);
++}
++
++static inline void ipu_smfc_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->smfc_reg + offset);
++}
++
++static inline u32 ipu_vdi_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->vdi_reg + offset);
++}
++
++static inline void ipu_vdi_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->vdi_reg + offset);
++}
++
++static inline u32 ipu_ic_read(struct ipu_soc *ipu, unsigned offset)
++{
++ return readl(ipu->ic_reg + offset);
++}
++
++static inline void ipu_ic_write(struct ipu_soc *ipu,
++ u32 value, unsigned offset)
++{
++ writel(value, ipu->ic_reg + offset);
++}
++
++int register_ipu_device(struct ipu_soc *ipu, int id);
++void unregister_ipu_device(struct ipu_soc *ipu, int id);
++ipu_color_space_t format_to_colorspace(uint32_t fmt);
++bool ipu_pixel_format_has_alpha(uint32_t fmt);
++
++void ipu_dump_registers(struct ipu_soc *ipu);
++
++uint32_t _ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
++
++void ipu_disp_init(struct ipu_soc *ipu);
++void _ipu_init_dc_mappings(struct ipu_soc *ipu);
++int _ipu_dp_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t in_pixel_fmt,
++ uint32_t out_pixel_fmt);
++void _ipu_dp_uninit(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_dc_init(struct ipu_soc *ipu, int dc_chan, int di, bool interlaced, uint32_t pixel_fmt);
++void _ipu_dc_uninit(struct ipu_soc *ipu, int dc_chan);
++void _ipu_dp_dc_enable(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_dp_dc_disable(struct ipu_soc *ipu, ipu_channel_t channel, bool swap);
++void _ipu_dmfc_init(struct ipu_soc *ipu, int dmfc_type, int first);
++void _ipu_dmfc_set_wait4eot(struct ipu_soc *ipu, int dma_chan, int width);
++void _ipu_dmfc_set_burst_size(struct ipu_soc *ipu, int dma_chan, int burst_size);
++int _ipu_disp_chan_is_interlaced(struct ipu_soc *ipu, ipu_channel_t channel);
++
++void _ipu_ic_enable_task(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_ic_disable_task(struct ipu_soc *ipu, ipu_channel_t channel);
++int _ipu_ic_init_prpvf(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi);
++void _ipu_vdi_init(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
++void _ipu_vdi_uninit(struct ipu_soc *ipu);
++void _ipu_ic_uninit_prpvf(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_vf(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_vf(struct ipu_soc *ipu);
++void _ipu_ic_init_csi(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_csi(struct ipu_soc *ipu);
++int _ipu_ic_init_prpenc(struct ipu_soc *ipu, ipu_channel_params_t *params,
++ bool src_is_csi);
++void _ipu_ic_uninit_prpenc(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_enc(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_enc(struct ipu_soc *ipu);
++int _ipu_ic_init_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_pp(struct ipu_soc *ipu);
++void _ipu_ic_init_rotate_pp(struct ipu_soc *ipu, ipu_channel_params_t *params);
++void _ipu_ic_uninit_rotate_pp(struct ipu_soc *ipu);
++int _ipu_ic_idma_init(struct ipu_soc *ipu, int dma_chan, uint16_t width, uint16_t height,
++ int burst_size, ipu_rotate_mode_t rot);
++void _ipu_vdi_toggle_top_field_man(struct ipu_soc *ipu);
++int _ipu_csi_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t csi);
++int _ipu_csi_set_mipi_di(struct ipu_soc *ipu, uint32_t num, uint32_t di_val, uint32_t csi);
++void ipu_csi_set_test_generator(struct ipu_soc *ipu, bool active, uint32_t r_value,
++ uint32_t g_value, uint32_t b_value,
++ uint32_t pix_clk, uint32_t csi);
++void _ipu_csi_ccir_err_detection_enable(struct ipu_soc *ipu, uint32_t csi);
++void _ipu_csi_ccir_err_detection_disable(struct ipu_soc *ipu, uint32_t csi);
++void _ipu_csi_wait4eof(struct ipu_soc *ipu, ipu_channel_t channel);
++void _ipu_smfc_init(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t mipi_id, uint32_t csi);
++void _ipu_smfc_set_burst_size(struct ipu_soc *ipu, ipu_channel_t channel, uint32_t bs);
++void _ipu_dp_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
++int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t x_pos, int16_t y_pos);
++int32_t _ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel,
++ int16_t *x_pos, int16_t *y_pos);
++void _ipu_get(struct ipu_soc *ipu);
++void _ipu_put(struct ipu_soc *ipu);
++
++struct clk *clk_register_mux_pix_clk(struct device *dev, const char *name,
++ const char **parent_names, u8 num_parents, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_mux_flags);
++struct clk *clk_register_div_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_div_flags);
++struct clk *clk_register_gate_pix_clk(struct device *dev, const char *name,
++ const char *parent_name, unsigned long flags,
++ u8 ipu_id, u8 di_id, u8 clk_gate_flags);
++#endif /* __INCLUDE_IPU_PRV_H__ */
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/ipu_regs.h linux-3.14.72/drivers/mxc/ipu3/ipu_regs.h
+--- linux-3.14.72.orig/drivers/mxc/ipu3/ipu_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/ipu_regs.h 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,749 @@
++/*
++ * Copyright (C) 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*
++ * @file ipu_regs.h
++ *
++ * @brief IPU Register definitions
++ *
++ * @ingroup IPU
++ */
++#ifndef __IPU_REGS_INCLUDED__
++#define __IPU_REGS_INCLUDED__
++
++enum imx_ipu_rev {
++ IPU_V3DEX = 2,
++ IPU_V3M,
++ IPU_V3H,
++};
++
++/*
++ * hw_rev 2: IPUV3DEX
++ * hw_rev 3: IPUV3M
++ * hw_rev 4: IPUV3H
++ */
++extern int g_ipu_hw_rev;
++
++#define IPU_MAX_VDI_IN_WIDTH ({g_ipu_hw_rev >= 3 ? \
++ (968) : \
++ (720); })
++#define IPU_DISP0_BASE 0x00000000
++#define IPU_MCU_T_DEFAULT 8
++#define IPU_DISP1_BASE ({g_ipu_hw_rev < 4 ? \
++ (IPU_MCU_T_DEFAULT << 25) : \
++ (0x00000000); })
++#define IPUV3DEX_REG_BASE 0x1E000000
++#define IPUV3M_REG_BASE 0x06000000
++#define IPUV3H_REG_BASE 0x00200000
++
++#define IPU_CM_REG_BASE 0x00000000
++#define IPU_IDMAC_REG_BASE 0x00008000
++#define IPU_ISP_REG_BASE 0x00010000
++#define IPU_DP_REG_BASE 0x00018000
++#define IPU_IC_REG_BASE 0x00020000
++#define IPU_IRT_REG_BASE 0x00028000
++#define IPU_CSI0_REG_BASE 0x00030000
++#define IPU_CSI1_REG_BASE 0x00038000
++#define IPU_DI0_REG_BASE 0x00040000
++#define IPU_DI1_REG_BASE 0x00048000
++#define IPU_SMFC_REG_BASE 0x00050000
++#define IPU_DC_REG_BASE 0x00058000
++#define IPU_DMFC_REG_BASE 0x00060000
++#define IPU_VDI_REG_BASE 0x00068000
++#define IPU_CPMEM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00100000) : \
++ (0x01000000); })
++#define IPU_LUT_REG_BASE 0x01020000
++#define IPU_SRM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00140000) : \
++ (0x01040000); })
++#define IPU_TPM_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00160000) : \
++ (0x01060000); })
++#define IPU_DC_TMPL_REG_BASE ({g_ipu_hw_rev >= 4 ? \
++ (0x00180000) : \
++ (0x01080000); })
++#define IPU_ISP_TBPR_REG_BASE 0x010C0000
++
++/* Register addresses */
++/* IPU Common registers */
++#define IPU_CM_REG(offset) (offset)
++
++#define IPU_CONF IPU_CM_REG(0)
++#define IPU_SRM_PRI1 IPU_CM_REG(0x00A0)
++#define IPU_SRM_PRI2 IPU_CM_REG(0x00A4)
++#define IPU_FS_PROC_FLOW1 IPU_CM_REG(0x00A8)
++#define IPU_FS_PROC_FLOW2 IPU_CM_REG(0x00AC)
++#define IPU_FS_PROC_FLOW3 IPU_CM_REG(0x00B0)
++#define IPU_FS_DISP_FLOW1 IPU_CM_REG(0x00B4)
++#define IPU_FS_DISP_FLOW2 IPU_CM_REG(0x00B8)
++#define IPU_SKIP IPU_CM_REG(0x00BC)
++#define IPU_DISP_ALT_CONF IPU_CM_REG(0x00C0)
++#define IPU_DISP_GEN IPU_CM_REG(0x00C4)
++#define IPU_DISP_ALT1 IPU_CM_REG(0x00C8)
++#define IPU_DISP_ALT2 IPU_CM_REG(0x00CC)
++#define IPU_DISP_ALT3 IPU_CM_REG(0x00D0)
++#define IPU_DISP_ALT4 IPU_CM_REG(0x00D4)
++#define IPU_SNOOP IPU_CM_REG(0x00D8)
++#define IPU_MEM_RST IPU_CM_REG(0x00DC)
++#define IPU_PM IPU_CM_REG(0x00E0)
++#define IPU_GPR IPU_CM_REG(0x00E4)
++#define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
++#define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
++/*
++ * IPUv3D doesn't support triple buffer, so point
++ * IPU_CHA_TRB_MODE_SEL, IPU_CHA_TRIPLE_CUR_BUF and
++ * IPU_CHA_BUF2_RDY to readonly
++ * IPU_ALT_CUR_BUF0 for IPUv3D.
++ */
++#define IPU_CHA_TRB_MODE_SEL(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0178 + 4 * ((ch) / 32)) : \
++ (0x012C); })
++#define IPU_CHA_TRIPLE_CUR_BUF(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0258 + \
++ 4 * (((ch) * 2) / 32)) : \
++ (0x012C); })
++#define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0288 + 4 * ((ch) / 32)) : \
++ (0x012C); })
++#define IPU_CHA_CUR_BUF(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x023C + 4 * ((ch) / 32)) : \
++ (0x0124 + 4 * ((ch) / 32)); })
++#define IPU_ALT_CUR_BUF0 IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0244) : \
++ (0x012C); })
++#define IPU_ALT_CUR_BUF1 IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0248) : \
++ (0x0130); })
++#define IPU_SRM_STAT IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x024C) : \
++ (0x0134); })
++#define IPU_PROC_TASK_STAT IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0250) : \
++ (0x0138); })
++#define IPU_DISP_TASK_STAT IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0254) : \
++ (0x013C); })
++#define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0268 + 4 * ((ch) / 32)) : \
++ (0x0140 + 4 * ((ch) / 32)); })
++#define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0270 + 4 * ((ch) / 32)) : \
++ (0x0148 + 4 * ((ch) / 32)); })
++#define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0278 + 4 * ((ch) / 32)) : \
++ (0x0158 + 4 * ((ch) / 32)); })
++#define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0280 + 4 * ((ch) / 32)) : \
++ (0x0160 + 4 * ((ch) / 32)); })
++
++#define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * ((n) - 1))
++#define IPU_INT_STAT(n) IPU_CM_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0200 + 4 * ((n) - 1)) : \
++ (0x00E8 + 4 * ((n) - 1)); })
++
++#define IPUIRQ_2_STATREG(irq) IPU_CM_REG(IPU_INT_STAT(1) + 4 * ((irq) / 32))
++#define IPUIRQ_2_CTRLREG(irq) IPU_CM_REG(IPU_INT_CTRL(1) + 4 * ((irq) / 32))
++#define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))
++
++/* IPU VDI registers */
++#define IPU_VDI_REG(offset) (offset)
++
++#define VDI_FSIZE IPU_VDI_REG(0)
++#define VDI_C IPU_VDI_REG(0x0004)
++
++/* IPU CSI Registers */
++#define IPU_CSI_REG(offset) (offset)
++
++#define CSI_SENS_CONF IPU_CSI_REG(0)
++#define CSI_SENS_FRM_SIZE IPU_CSI_REG(0x0004)
++#define CSI_ACT_FRM_SIZE IPU_CSI_REG(0x0008)
++#define CSI_OUT_FRM_CTRL IPU_CSI_REG(0x000C)
++#define CSI_TST_CTRL IPU_CSI_REG(0x0010)
++#define CSI_CCIR_CODE_1 IPU_CSI_REG(0x0014)
++#define CSI_CCIR_CODE_2 IPU_CSI_REG(0x0018)
++#define CSI_CCIR_CODE_3 IPU_CSI_REG(0x001C)
++#define CSI_MIPI_DI IPU_CSI_REG(0x0020)
++#define CSI_SKIP IPU_CSI_REG(0x0024)
++#define CSI_CPD_CTRL IPU_CSI_REG(0x0028)
++#define CSI_CPD_RC(n) IPU_CSI_REG(0x002C + 4 * (n))
++#define CSI_CPD_RS(n) IPU_CSI_REG(0x004C + 4 * (n))
++#define CSI_CPD_GRC(n) IPU_CSI_REG(0x005C + 4 * (n))
++#define CSI_CPD_GRS(n) IPU_CSI_REG(0x007C + 4 * (n))
++#define CSI_CPD_GBC(n) IPU_CSI_REG(0x008C + 4 * (n))
++#define CSI_CPD_GBS(n) IPU_CSI_REG(0x00AC + 4 * (n))
++#define CSI_CPD_BC(n) IPU_CSI_REG(0x00BC + 4 * (n))
++#define CSI_CPD_BS(n) IPU_CSI_REG(0x00DC + 4 * (n))
++#define CSI_CPD_OFFSET1 IPU_CSI_REG(0x00EC)
++#define CSI_CPD_OFFSET2 IPU_CSI_REG(0x00F0)
++
++/* IPU SMFC Registers */
++#define IPU_SMFC_REG(offset) (offset)
++
++#define SMFC_MAP IPU_SMFC_REG(0)
++#define SMFC_WMC IPU_SMFC_REG(0x0004)
++#define SMFC_BS IPU_SMFC_REG(0x0008)
++
++/* IPU IC Registers */
++#define IPU_IC_REG(offset) (offset)
++
++#define IC_CONF IPU_IC_REG(0)
++#define IC_PRP_ENC_RSC IPU_IC_REG(0x0004)
++#define IC_PRP_VF_RSC IPU_IC_REG(0x0008)
++#define IC_PP_RSC IPU_IC_REG(0x000C)
++#define IC_CMBP_1 IPU_IC_REG(0x0010)
++#define IC_CMBP_2 IPU_IC_REG(0x0014)
++#define IC_IDMAC_1 IPU_IC_REG(0x0018)
++#define IC_IDMAC_2 IPU_IC_REG(0x001C)
++#define IC_IDMAC_3 IPU_IC_REG(0x0020)
++#define IC_IDMAC_4 IPU_IC_REG(0x0024)
++
++/* IPU IDMAC Registers */
++#define IPU_IDMAC_REG(offset) (offset)
++
++#define IDMAC_CONF IPU_IDMAC_REG(0x0000)
++#define IDMAC_CHA_EN(ch) IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
++#define IDMAC_SEP_ALPHA IPU_IDMAC_REG(0x000C)
++#define IDMAC_ALT_SEP_ALPHA IPU_IDMAC_REG(0x0010)
++#define IDMAC_CHA_PRI(ch) IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
++#define IDMAC_WM_EN(ch) IPU_IDMAC_REG(0x001C + 4 * ((ch) / 32))
++#define IDMAC_CH_LOCK_EN_1 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0024) : 0; })
++#define IDMAC_CH_LOCK_EN_2 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0028) : \
++ (0x0024); })
++#define IDMAC_SUB_ADDR_0 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x002C) : \
++ (0x0028); })
++#define IDMAC_SUB_ADDR_1 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0030) : \
++ (0x002C); })
++#define IDMAC_SUB_ADDR_2 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0034) : \
++ (0x0030); })
++/*
++ * IPUv3D doesn't support IDMAC_SUB_ADDR_3 and IDMAC_SUB_ADDR_4,
++ * so point them to readonly IDMAC_CHA_BUSY1 for IPUv3D.
++ */
++#define IDMAC_SUB_ADDR_3 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0038) : \
++ (0x0040); })
++#define IDMAC_SUB_ADDR_4 IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x003C) : \
++ (0x0040); })
++#define IDMAC_BAND_EN(ch) IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0040 + 4 * ((ch) / 32)) : \
++ (0x0034 + 4 * ((ch) / 32)); })
++#define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG({g_ipu_hw_rev >= 2 ? \
++ (0x0100 + 4 * ((ch) / 32)) : \
++ (0x0040 + 4 * ((ch) / 32)); })
++
++/* IPU DI Registers */
++#define IPU_DI_REG(offset) (offset)
++
++#define DI_GENERAL IPU_DI_REG(0)
++#define DI_BS_CLKGEN0 IPU_DI_REG(0x0004)
++#define DI_BS_CLKGEN1 IPU_DI_REG(0x0008)
++#define DI_SW_GEN0(gen) IPU_DI_REG(0x000C + 4 * ((gen) - 1))
++#define DI_SW_GEN1(gen) IPU_DI_REG(0x0030 + 4 * ((gen) - 1))
++#define DI_STP_REP(gen) IPU_DI_REG(0x0148 + 4 * (((gen) - 1) / 2))
++#define DI_SYNC_AS_GEN IPU_DI_REG(0x0054)
++#define DI_DW_GEN(gen) IPU_DI_REG(0x0058 + 4 * (gen))
++#define DI_DW_SET(gen, set) IPU_DI_REG(0x0088 + 4 * ((gen) + 0xC * (set)))
++#define DI_SER_CONF IPU_DI_REG(0x015C)
++#define DI_SSC IPU_DI_REG(0x0160)
++#define DI_POL IPU_DI_REG(0x0164)
++#define DI_AW0 IPU_DI_REG(0x0168)
++#define DI_AW1 IPU_DI_REG(0x016C)
++#define DI_SCR_CONF IPU_DI_REG(0x0170)
++#define DI_STAT IPU_DI_REG(0x0174)
++
++/* IPU DMFC Registers */
++#define IPU_DMFC_REG(offset) (offset)
++
++#define DMFC_RD_CHAN IPU_DMFC_REG(0)
++#define DMFC_WR_CHAN IPU_DMFC_REG(0x0004)
++#define DMFC_WR_CHAN_DEF IPU_DMFC_REG(0x0008)
++#define DMFC_DP_CHAN IPU_DMFC_REG(0x000C)
++#define DMFC_DP_CHAN_DEF IPU_DMFC_REG(0x0010)
++#define DMFC_GENERAL1 IPU_DMFC_REG(0x0014)
++#define DMFC_GENERAL2 IPU_DMFC_REG(0x0018)
++#define DMFC_IC_CTRL IPU_DMFC_REG(0x001C)
++#define DMFC_STAT IPU_DMFC_REG(0x0020)
++
++/* IPU DC Registers */
++#define IPU_DC_REG(offset) (offset)
++
++#define DC_MAP_CONF_PTR(n) IPU_DC_REG(0x0108 + ((n) & ~0x1) * 2)
++#define DC_MAP_CONF_VAL(n) IPU_DC_REG(0x0144 + ((n) & ~0x1) * 2)
++
++#define _RL_CH_2_OFFSET(ch) (((ch) == 0) ? 8 : ( \
++ ((ch) == 1) ? 0x24 : ( \
++ ((ch) == 2) ? 0x40 : ( \
++ ((ch) == 5) ? 0x64 : ( \
++ ((ch) == 6) ? 0x80 : ( \
++ ((ch) == 8) ? 0x9C : ( \
++ ((ch) == 9) ? 0xBC : (-1))))))))
++#define DC_RL_CH(ch, evt) IPU_DC_REG(_RL_CH_2_OFFSET(ch) + \
++ ((evt) & ~0x1) * 2)
++
++#define DC_EVT_NF 0
++#define DC_EVT_NL 1
++#define DC_EVT_EOF 2
++#define DC_EVT_NFIELD 3
++#define DC_EVT_EOL 4
++#define DC_EVT_EOFIELD 5
++#define DC_EVT_NEW_ADDR 6
++#define DC_EVT_NEW_CHAN 7
++#define DC_EVT_NEW_DATA 8
++
++#define DC_EVT_NEW_ADDR_W_0 0
++#define DC_EVT_NEW_ADDR_W_1 1
++#define DC_EVT_NEW_CHAN_W_0 2
++#define DC_EVT_NEW_CHAN_W_1 3
++#define DC_EVT_NEW_DATA_W_0 4
++#define DC_EVT_NEW_DATA_W_1 5
++#define DC_EVT_NEW_ADDR_R_0 6
++#define DC_EVT_NEW_ADDR_R_1 7
++#define DC_EVT_NEW_CHAN_R_0 8
++#define DC_EVT_NEW_CHAN_R_1 9
++#define DC_EVT_NEW_DATA_R_0 10
++#define DC_EVT_NEW_DATA_R_1 11
++#define DC_EVEN_UGDE0 12
++#define DC_ODD_UGDE0 13
++#define DC_EVEN_UGDE1 14
++#define DC_ODD_UGDE1 15
++#define DC_EVEN_UGDE2 16
++#define DC_ODD_UGDE2 17
++#define DC_EVEN_UGDE3 18
++#define DC_ODD_UGDE3 19
++
++#define dc_ch_offset(ch) \
++({ \
++ const u8 _offset[] = { \
++ 0, 0x1C, 0x38, 0x54, 0x58, 0x5C, 0x78, 0, 0x94, 0xB4}; \
++ _offset[ch]; \
++})
++#define DC_WR_CH_CONF(ch) IPU_DC_REG(dc_ch_offset(ch))
++#define DC_WR_CH_ADDR(ch) IPU_DC_REG(dc_ch_offset(ch) + 4)
++
++#define DC_WR_CH_CONF_1 IPU_DC_REG(0x001C)
++#define DC_WR_CH_ADDR_1 IPU_DC_REG(0x0020)
++#define DC_WR_CH_CONF_5 IPU_DC_REG(0x005C)
++#define DC_WR_CH_ADDR_5 IPU_DC_REG(0x0060)
++#define DC_GEN IPU_DC_REG(0x00D4)
++#define DC_DISP_CONF1(disp) IPU_DC_REG(0x00D8 + 4 * (disp))
++#define DC_DISP_CONF2(disp) IPU_DC_REG(0x00E8 + 4 * (disp))
++#define DC_STAT IPU_DC_REG(0x01C8)
++#define DC_UGDE_0(evt) IPU_DC_REG(0x0174 + 16 * (evt))
++#define DC_UGDE_1(evt) IPU_DC_REG(0x0178 + 16 * (evt))
++#define DC_UGDE_2(evt) IPU_DC_REG(0x017C + 16 * (evt))
++#define DC_UGDE_3(evt) IPU_DC_REG(0x0180 + 16 * (evt))
++
++/* IPU DP Registers */
++#define IPU_DP_REG(offset) (offset)
++
++#define DP_SYNC 0
++#define DP_ASYNC0 0x60
++#define DP_ASYNC1 0xBC
++#define DP_COM_CONF(flow) IPU_DP_REG(flow)
++#define DP_GRAPH_WIND_CTRL(flow) IPU_DP_REG(0x0004 + (flow))
++#define DP_FG_POS(flow) IPU_DP_REG(0x0008 + (flow))
++#define DP_GAMMA_C(flow, i) IPU_DP_REG(0x0014 + (flow) + 4 * (i))
++#define DP_GAMMA_S(flow, i) IPU_DP_REG(0x0034 + (flow) + 4 * (i))
++#define DP_CSC_A_0(flow) IPU_DP_REG(0x0044 + (flow))
++#define DP_CSC_A_1(flow) IPU_DP_REG(0x0048 + (flow))
++#define DP_CSC_A_2(flow) IPU_DP_REG(0x004C + (flow))
++#define DP_CSC_A_3(flow) IPU_DP_REG(0x0050 + (flow))
++#define DP_CSC_0(flow) IPU_DP_REG(0x0054 + (flow))
++#define DP_CSC_1(flow) IPU_DP_REG(0x0058 + (flow))
++
++enum {
++ IPU_CONF_CSI0_EN = 0x00000001,
++ IPU_CONF_CSI1_EN = 0x00000002,
++ IPU_CONF_IC_EN = 0x00000004,
++ IPU_CONF_ROT_EN = 0x00000008,
++ IPU_CONF_ISP_EN = 0x00000010,
++ IPU_CONF_DP_EN = 0x00000020,
++ IPU_CONF_DI0_EN = 0x00000040,
++ IPU_CONF_DI1_EN = 0x00000080,
++ IPU_CONF_DMFC_EN = 0x00000400,
++ IPU_CONF_SMFC_EN = 0x00000100,
++ IPU_CONF_DC_EN = 0x00000200,
++ IPU_CONF_VDI_EN = 0x00001000,
++ IPU_CONF_IDMAC_DIS = 0x00400000,
++ IPU_CONF_IC_DMFC_SEL = 0x02000000,
++ IPU_CONF_IC_DMFC_SYNC = 0x04000000,
++ IPU_CONF_VDI_DMFC_SYNC = 0x08000000,
++ IPU_CONF_CSI0_DATA_SOURCE = 0x10000000,
++ IPU_CONF_CSI0_DATA_SOURCE_OFFSET = 28,
++ IPU_CONF_CSI1_DATA_SOURCE = 0x20000000,
++ IPU_CONF_IC_INPUT = 0x40000000,
++ IPU_CONF_CSI_SEL = 0x80000000,
++
++ DI0_COUNTER_RELEASE = 0x01000000,
++ DI1_COUNTER_RELEASE = 0x02000000,
++
++ FS_PRPVF_ROT_SRC_SEL_MASK = 0x00000F00,
++ FS_PRPVF_ROT_SRC_SEL_OFFSET = 8,
++ FS_PRPENC_ROT_SRC_SEL_MASK = 0x0000000F,
++ FS_PRPENC_ROT_SRC_SEL_OFFSET = 0,
++ FS_PP_ROT_SRC_SEL_MASK = 0x000F0000,
++ FS_PP_ROT_SRC_SEL_OFFSET = 16,
++ FS_PP_SRC_SEL_MASK = 0x0000F000,
++ FS_PP_SRC_SEL_VDOA = 0x00008000,
++ FS_PP_SRC_SEL_OFFSET = 12,
++ FS_PRP_SRC_SEL_MASK = 0x0F000000,
++ FS_PRP_SRC_SEL_OFFSET = 24,
++ FS_VF_IN_VALID = 0x80000000,
++ FS_ENC_IN_VALID = 0x40000000,
++ FS_VDI_SRC_SEL_MASK = 0x30000000,
++ FS_VDI_SRC_SEL_VDOA = 0x20000000,
++ FS_VDOA_DEST_SEL_MASK = 0x00030000,
++ FS_VDOA_DEST_SEL_VDI = 0x00020000,
++ FS_VDOA_DEST_SEL_IC = 0x00010000,
++ FS_VDI_SRC_SEL_OFFSET = 28,
++
++
++ FS_PRPENC_DEST_SEL_MASK = 0x0000000F,
++ FS_PRPENC_DEST_SEL_OFFSET = 0,
++ FS_PRPVF_DEST_SEL_MASK = 0x000000F0,
++ FS_PRPVF_DEST_SEL_OFFSET = 4,
++ FS_PRPVF_ROT_DEST_SEL_MASK = 0x00000F00,
++ FS_PRPVF_ROT_DEST_SEL_OFFSET = 8,
++ FS_PP_DEST_SEL_MASK = 0x0000F000,
++ FS_PP_DEST_SEL_OFFSET = 12,
++ FS_PP_ROT_DEST_SEL_MASK = 0x000F0000,
++ FS_PP_ROT_DEST_SEL_OFFSET = 16,
++ FS_PRPENC_ROT_DEST_SEL_MASK = 0x00F00000,
++ FS_PRPENC_ROT_DEST_SEL_OFFSET = 20,
++
++ FS_SMFC0_DEST_SEL_MASK = 0x0000000F,
++ FS_SMFC0_DEST_SEL_OFFSET = 0,
++ FS_SMFC1_DEST_SEL_MASK = 0x00000070,
++ FS_SMFC1_DEST_SEL_OFFSET = 4,
++ FS_SMFC2_DEST_SEL_MASK = 0x00000780,
++ FS_SMFC2_DEST_SEL_OFFSET = 7,
++ FS_SMFC3_DEST_SEL_MASK = 0x00003800,
++ FS_SMFC3_DEST_SEL_OFFSET = 11,
++
++ FS_DC1_SRC_SEL_MASK = 0x00F00000,
++ FS_DC1_SRC_SEL_OFFSET = 20,
++ FS_DC2_SRC_SEL_MASK = 0x000F0000,
++ FS_DC2_SRC_SEL_OFFSET = 16,
++ FS_DP_SYNC0_SRC_SEL_MASK = 0x0000000F,
++ FS_DP_SYNC0_SRC_SEL_OFFSET = 0,
++ FS_DP_SYNC1_SRC_SEL_MASK = 0x000000F0,
++ FS_DP_SYNC1_SRC_SEL_OFFSET = 4,
++ FS_DP_ASYNC0_SRC_SEL_MASK = 0x00000F00,
++ FS_DP_ASYNC0_SRC_SEL_OFFSET = 8,
++ FS_DP_ASYNC1_SRC_SEL_MASK = 0x0000F000,
++ FS_DP_ASYNC1_SRC_SEL_OFFSET = 12,
++
++ FS_AUTO_REF_PER_MASK = 0,
++ FS_AUTO_REF_PER_OFFSET = 16,
++
++ TSTAT_VF_MASK = 0x0000000C,
++ TSTAT_VF_OFFSET = 2,
++ TSTAT_VF_ROT_MASK = 0x00000300,
++ TSTAT_VF_ROT_OFFSET = 8,
++ TSTAT_ENC_MASK = 0x00000003,
++ TSTAT_ENC_OFFSET = 0,
++ TSTAT_ENC_ROT_MASK = 0x000000C0,
++ TSTAT_ENC_ROT_OFFSET = 6,
++ TSTAT_PP_MASK = 0x00000030,
++ TSTAT_PP_OFFSET = 4,
++ TSTAT_PP_ROT_MASK = 0x00000C00,
++ TSTAT_PP_ROT_OFFSET = 10,
++
++ TASK_STAT_IDLE = 0,
++ TASK_STAT_ACTIVE = 1,
++ TASK_STAT_WAIT4READY = 2,
++
++ /* Image Converter Register bits */
++ IC_CONF_PRPENC_EN = 0x00000001,
++ IC_CONF_PRPENC_CSC1 = 0x00000002,
++ IC_CONF_PRPENC_ROT_EN = 0x00000004,
++ IC_CONF_PRPVF_EN = 0x00000100,
++ IC_CONF_PRPVF_CSC1 = 0x00000200,
++ IC_CONF_PRPVF_CSC2 = 0x00000400,
++ IC_CONF_PRPVF_CMB = 0x00000800,
++ IC_CONF_PRPVF_ROT_EN = 0x00001000,
++ IC_CONF_PP_EN = 0x00010000,
++ IC_CONF_PP_CSC1 = 0x00020000,
++ IC_CONF_PP_CSC2 = 0x00040000,
++ IC_CONF_PP_CMB = 0x00080000,
++ IC_CONF_PP_ROT_EN = 0x00100000,
++ IC_CONF_IC_GLB_LOC_A = 0x10000000,
++ IC_CONF_KEY_COLOR_EN = 0x20000000,
++ IC_CONF_RWS_EN = 0x40000000,
++ IC_CONF_CSI_MEM_WR_EN = 0x80000000,
++
++ IC_RSZ_MAX_RESIZE_RATIO = 0x00004000,
++
++ IC_IDMAC_1_CB0_BURST_16 = 0x00000001,
++ IC_IDMAC_1_CB1_BURST_16 = 0x00000002,
++ IC_IDMAC_1_CB2_BURST_16 = 0x00000004,
++ IC_IDMAC_1_CB3_BURST_16 = 0x00000008,
++ IC_IDMAC_1_CB4_BURST_16 = 0x00000010,
++ IC_IDMAC_1_CB5_BURST_16 = 0x00000020,
++ IC_IDMAC_1_CB6_BURST_16 = 0x00000040,
++ IC_IDMAC_1_CB7_BURST_16 = 0x00000080,
++ IC_IDMAC_1_PRPENC_ROT_MASK = 0x00003800,
++ IC_IDMAC_1_PRPENC_ROT_OFFSET = 11,
++ IC_IDMAC_1_PRPVF_ROT_MASK = 0x0001C000,
++ IC_IDMAC_1_PRPVF_ROT_OFFSET = 14,
++ IC_IDMAC_1_PP_ROT_MASK = 0x000E0000,
++ IC_IDMAC_1_PP_ROT_OFFSET = 17,
++ IC_IDMAC_1_PP_FLIP_RS = 0x00400000,
++ IC_IDMAC_1_PRPVF_FLIP_RS = 0x00200000,
++ IC_IDMAC_1_PRPENC_FLIP_RS = 0x00100000,
++
++ IC_IDMAC_2_PRPENC_HEIGHT_MASK = 0x000003FF,
++ IC_IDMAC_2_PRPENC_HEIGHT_OFFSET = 0,
++ IC_IDMAC_2_PRPVF_HEIGHT_MASK = 0x000FFC00,
++ IC_IDMAC_2_PRPVF_HEIGHT_OFFSET = 10,
++ IC_IDMAC_2_PP_HEIGHT_MASK = 0x3FF00000,
++ IC_IDMAC_2_PP_HEIGHT_OFFSET = 20,
++
++ IC_IDMAC_3_PRPENC_WIDTH_MASK = 0x000003FF,
++ IC_IDMAC_3_PRPENC_WIDTH_OFFSET = 0,
++ IC_IDMAC_3_PRPVF_WIDTH_MASK = 0x000FFC00,
++ IC_IDMAC_3_PRPVF_WIDTH_OFFSET = 10,
++ IC_IDMAC_3_PP_WIDTH_MASK = 0x3FF00000,
++ IC_IDMAC_3_PP_WIDTH_OFFSET = 20,
++
++ CSI_SENS_CONF_DATA_FMT_SHIFT = 8,
++ CSI_SENS_CONF_DATA_FMT_MASK = 0x00000700,
++ CSI_SENS_CONF_DATA_FMT_RGB_YUV444 = 0L,
++ CSI_SENS_CONF_DATA_FMT_YUV422_YUYV = 1L,
++ CSI_SENS_CONF_DATA_FMT_YUV422_UYVY = 2L,
++ CSI_SENS_CONF_DATA_FMT_BAYER = 3L,
++ CSI_SENS_CONF_DATA_FMT_RGB565 = 4L,
++ CSI_SENS_CONF_DATA_FMT_RGB555 = 5L,
++ CSI_SENS_CONF_DATA_FMT_RGB444 = 6L,
++ CSI_SENS_CONF_DATA_FMT_JPEG = 7L,
++
++ CSI_SENS_CONF_VSYNC_POL_SHIFT = 0,
++ CSI_SENS_CONF_HSYNC_POL_SHIFT = 1,
++ CSI_SENS_CONF_DATA_POL_SHIFT = 2,
++ CSI_SENS_CONF_PIX_CLK_POL_SHIFT = 3,
++ CSI_SENS_CONF_SENS_PRTCL_MASK = 0x00000070L,
++ CSI_SENS_CONF_SENS_PRTCL_SHIFT = 4,
++ CSI_SENS_CONF_PACK_TIGHT_SHIFT = 7,
++ CSI_SENS_CONF_DATA_WIDTH_SHIFT = 11,
++ CSI_SENS_CONF_EXT_VSYNC_SHIFT = 15,
++ CSI_SENS_CONF_DIVRATIO_SHIFT = 16,
++
++ CSI_SENS_CONF_DIVRATIO_MASK = 0x00FF0000L,
++ CSI_SENS_CONF_DATA_DEST_SHIFT = 24,
++ CSI_SENS_CONF_DATA_DEST_MASK = 0x07000000L,
++ CSI_SENS_CONF_JPEG8_EN_SHIFT = 27,
++ CSI_SENS_CONF_JPEG_EN_SHIFT = 28,
++ CSI_SENS_CONF_FORCE_EOF_SHIFT = 29,
++ CSI_SENS_CONF_DATA_EN_POL_SHIFT = 31,
++
++ CSI_DATA_DEST_ISP = 1L,
++ CSI_DATA_DEST_IC = 2L,
++ CSI_DATA_DEST_IDMAC = 4L,
++
++ CSI_CCIR_ERR_DET_EN = 0x01000000L,
++ CSI_HORI_DOWNSIZE_EN = 0x80000000L,
++ CSI_VERT_DOWNSIZE_EN = 0x40000000L,
++ CSI_TEST_GEN_MODE_EN = 0x01000000L,
++
++ CSI_HSC_MASK = 0x1FFF0000,
++ CSI_HSC_SHIFT = 16,
++ CSI_VSC_MASK = 0x00000FFF,
++ CSI_VSC_SHIFT = 0,
++
++ CSI_TEST_GEN_R_MASK = 0x000000FFL,
++ CSI_TEST_GEN_R_SHIFT = 0,
++ CSI_TEST_GEN_G_MASK = 0x0000FF00L,
++ CSI_TEST_GEN_G_SHIFT = 8,
++ CSI_TEST_GEN_B_MASK = 0x00FF0000L,
++ CSI_TEST_GEN_B_SHIFT = 16,
++
++ CSI_MIPI_DI0_MASK = 0x000000FFL,
++ CSI_MIPI_DI0_SHIFT = 0,
++ CSI_MIPI_DI1_MASK = 0x0000FF00L,
++ CSI_MIPI_DI1_SHIFT = 8,
++ CSI_MIPI_DI2_MASK = 0x00FF0000L,
++ CSI_MIPI_DI2_SHIFT = 16,
++ CSI_MIPI_DI3_MASK = 0xFF000000L,
++ CSI_MIPI_DI3_SHIFT = 24,
++
++ CSI_MAX_RATIO_SKIP_ISP_MASK = 0x00070000L,
++ CSI_MAX_RATIO_SKIP_ISP_SHIFT = 16,
++ CSI_SKIP_ISP_MASK = 0x00F80000L,
++ CSI_SKIP_ISP_SHIFT = 19,
++ CSI_MAX_RATIO_SKIP_SMFC_MASK = 0x00000007L,
++ CSI_MAX_RATIO_SKIP_SMFC_SHIFT = 0,
++ CSI_SKIP_SMFC_MASK = 0x000000F8L,
++ CSI_SKIP_SMFC_SHIFT = 3,
++ CSI_ID_2_SKIP_MASK = 0x00000300L,
++ CSI_ID_2_SKIP_SHIFT = 8,
++
++ CSI_COLOR_FIRST_ROW_MASK = 0x00000002L,
++ CSI_COLOR_FIRST_COMP_MASK = 0x00000001L,
++
++ SMFC_MAP_CH0_MASK = 0x00000007L,
++ SMFC_MAP_CH0_SHIFT = 0,
++ SMFC_MAP_CH1_MASK = 0x00000038L,
++ SMFC_MAP_CH1_SHIFT = 3,
++ SMFC_MAP_CH2_MASK = 0x000001C0L,
++ SMFC_MAP_CH2_SHIFT = 6,
++ SMFC_MAP_CH3_MASK = 0x00000E00L,
++ SMFC_MAP_CH3_SHIFT = 9,
++
++ SMFC_WM0_SET_MASK = 0x00000007L,
++ SMFC_WM0_SET_SHIFT = 0,
++ SMFC_WM1_SET_MASK = 0x000001C0L,
++ SMFC_WM1_SET_SHIFT = 6,
++ SMFC_WM2_SET_MASK = 0x00070000L,
++ SMFC_WM2_SET_SHIFT = 16,
++ SMFC_WM3_SET_MASK = 0x01C00000L,
++ SMFC_WM3_SET_SHIFT = 22,
++
++ SMFC_WM0_CLR_MASK = 0x00000038L,
++ SMFC_WM0_CLR_SHIFT = 3,
++ SMFC_WM1_CLR_MASK = 0x00000E00L,
++ SMFC_WM1_CLR_SHIFT = 9,
++ SMFC_WM2_CLR_MASK = 0x00380000L,
++ SMFC_WM2_CLR_SHIFT = 19,
++ SMFC_WM3_CLR_MASK = 0x0E000000L,
++ SMFC_WM3_CLR_SHIFT = 25,
++
++ SMFC_BS0_MASK = 0x0000000FL,
++ SMFC_BS0_SHIFT = 0,
++ SMFC_BS1_MASK = 0x000000F0L,
++ SMFC_BS1_SHIFT = 4,
++ SMFC_BS2_MASK = 0x00000F00L,
++ SMFC_BS2_SHIFT = 8,
++ SMFC_BS3_MASK = 0x0000F000L,
++ SMFC_BS3_SHIFT = 12,
++
++ PF_CONF_TYPE_MASK = 0x00000007,
++ PF_CONF_TYPE_SHIFT = 0,
++ PF_CONF_PAUSE_EN = 0x00000010,
++ PF_CONF_RESET = 0x00008000,
++ PF_CONF_PAUSE_ROW_MASK = 0x00FF0000,
++ PF_CONF_PAUSE_ROW_SHIFT = 16,
++
++ DI_DW_GEN_ACCESS_SIZE_OFFSET = 24,
++ DI_DW_GEN_COMPONENT_SIZE_OFFSET = 16,
++
++ DI_GEN_DI_CLK_EXT = 0x100000,
++ DI_GEN_POLARITY_DISP_CLK = 0x00020000,
++ DI_GEN_POLARITY_1 = 0x00000001,
++ DI_GEN_POLARITY_2 = 0x00000002,
++ DI_GEN_POLARITY_3 = 0x00000004,
++ DI_GEN_POLARITY_4 = 0x00000008,
++ DI_GEN_POLARITY_5 = 0x00000010,
++ DI_GEN_POLARITY_6 = 0x00000020,
++ DI_GEN_POLARITY_7 = 0x00000040,
++ DI_GEN_POLARITY_8 = 0x00000080,
++
++ DI_POL_DRDY_DATA_POLARITY = 0x00000080,
++ DI_POL_DRDY_POLARITY_15 = 0x00000010,
++
++ DI_VSYNC_SEL_OFFSET = 13,
++
++ DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
++ DC_WR_CH_CONF_PROG_TYPE_OFFSET = 5,
++ DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
++ DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
++ DC_WR_CH_CONF_PROG_DISP_ID_OFFSET = 3,
++ DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
++
++ DC_UGDE_0_ODD_EN = 0x02000000,
++ DC_UGDE_0_ID_CODED_MASK = 0x00000007,
++ DC_UGDE_0_ID_CODED_OFFSET = 0,
++ DC_UGDE_0_EV_PRIORITY_MASK = 0x00000078,
++ DC_UGDE_0_EV_PRIORITY_OFFSET = 3,
++
++ DP_COM_CONF_FG_EN = 0x00000001,
++ DP_COM_CONF_GWSEL = 0x00000002,
++ DP_COM_CONF_GWAM = 0x00000004,
++ DP_COM_CONF_GWCKE = 0x00000008,
++ DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
++ DP_COM_CONF_CSC_DEF_OFFSET = 8,
++ DP_COM_CONF_CSC_DEF_FG = 0x00000300,
++ DP_COM_CONF_CSC_DEF_BG = 0x00000200,
++ DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
++ DP_COM_CONF_GAMMA_EN = 0x00001000,
++ DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
++
++ DI_SER_CONF_LLA_SER_ACCESS = 0x00000020,
++ DI_SER_CONF_SERIAL_CLK_POL = 0x00000010,
++ DI_SER_CONF_SERIAL_DATA_POL = 0x00000008,
++ DI_SER_CONF_SERIAL_RS_POL = 0x00000004,
++ DI_SER_CONF_SERIAL_CS_POL = 0x00000002,
++ DI_SER_CONF_WAIT4SERIAL = 0x00000001,
++
++ VDI_C_CH_420 = 0x00000000,
++ VDI_C_CH_422 = 0x00000002,
++ VDI_C_MOT_SEL_FULL = 0x00000008,
++ VDI_C_MOT_SEL_LOW = 0x00000004,
++ VDI_C_MOT_SEL_MED = 0x00000000,
++ VDI_C_BURST_SIZE1_4 = 0x00000030,
++ VDI_C_BURST_SIZE2_4 = 0x00000300,
++ VDI_C_BURST_SIZE3_4 = 0x00003000,
++ VDI_C_BURST_SIZE_MASK = 0xF,
++ VDI_C_BURST_SIZE1_OFFSET = 4,
++ VDI_C_BURST_SIZE2_OFFSET = 8,
++ VDI_C_BURST_SIZE3_OFFSET = 12,
++ VDI_C_VWM1_SET_1 = 0x00000000,
++ VDI_C_VWM1_SET_2 = 0x00010000,
++ VDI_C_VWM1_CLR_2 = 0x00080000,
++ VDI_C_VWM3_SET_1 = 0x00000000,
++ VDI_C_VWM3_SET_2 = 0x00400000,
++ VDI_C_VWM3_CLR_2 = 0x02000000,
++ VDI_C_TOP_FIELD_MAN_1 = 0x40000000,
++ VDI_C_TOP_FIELD_AUTO_1 = 0x80000000,
++};
++
++enum di_pins {
++ DI_PIN11 = 0,
++ DI_PIN12 = 1,
++ DI_PIN13 = 2,
++ DI_PIN14 = 3,
++ DI_PIN15 = 4,
++ DI_PIN16 = 5,
++ DI_PIN17 = 6,
++ DI_PIN_CS = 7,
++
++ DI_PIN_SER_CLK = 0,
++ DI_PIN_SER_RS = 1,
++};
++
++enum di_sync_wave {
++ DI_SYNC_NONE = -1,
++ DI_SYNC_CLK = 0,
++ DI_SYNC_INT_HSYNC = 1,
++ DI_SYNC_COUNT_1 = 1,
++ DI_SYNC_HSYNC = 2,
++ DI_SYNC_VSYNC = 3,
++ DI_SYNC_AFIELD = 4,
++ DI_SYNC_ALINE = 5,
++ DI_SYNC_APIXEL = 6,
++ DI_SYNC_COUNT_7 = 7,
++ DI_SYNC_COUNT_8 = 8,
++ DI_SYNC_COUNT_9 = 9,
++};
++
++/* DC template opcodes */
++#define WROD(lf) (0x18 | (lf << 1))
++#define WRG (0x01)
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/Kconfig linux-3.14.72/drivers/mxc/ipu3/Kconfig
+--- linux-3.14.72.orig/drivers/mxc/ipu3/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/Kconfig 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,2 @@
++config MXC_IPU_V3
++ bool
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/Makefile linux-3.14.72/drivers/mxc/ipu3/Makefile
+--- linux-3.14.72.orig/drivers/mxc/ipu3/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/Makefile 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,4 @@
++obj-$(CONFIG_MXC_IPU_V3) = mxc_ipu.o
++
++mxc_ipu-objs := ipu_common.o ipu_ic.o ipu_disp.o ipu_capture.o ipu_device.o \
++ ipu_calc_stripes_sizes.o vdoa.o ipu_pixel_clk.o
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/vdoa.c linux-3.14.72/drivers/mxc/ipu3/vdoa.c
+--- linux-3.14.72.orig/drivers/mxc/ipu3/vdoa.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/vdoa.c 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,543 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ipu.h>
++#include <linux/genalloc.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++
++#include "vdoa.h"
++/* 6band(3field* double buffer) * (width*2) * bandline(8)
++ = 6x1024x2x8 = 96k or 72k(1.5byte) */
++#define MAX_VDOA_IRAM_SIZE (1024*96)
++#define VDOA_IRAM_SIZE (1024*72)
++
++#define VDOAC_BAND_HEIGHT_32LINES (32)
++#define VDOAC_BAND_HEIGHT_16LINES (16)
++#define VDOAC_BAND_HEIGHT_8LINES (8)
++#define VDOAC_THREE_FRAMES (0x1 << 2)
++#define VDOAC_SYNC_BAND_MODE (0x1 << 3)
++#define VDOAC_SCAN_ORDER_INTERLACED (0x1 << 4)
++#define VDOAC_PFS_YUYV (0x1 << 5)
++#define VDOAC_IPU_SEL_1 (0x1 << 6)
++#define VDOAFP_FH_MASK (0x1FFF)
++#define VDOAFP_FH_SHIFT (16)
++#define VDOAFP_FW_MASK (0x3FFF)
++#define VDOAFP_FW_SHIFT (0)
++#define VDOASL_VSLY_MASK (0x3FFF)
++#define VDOASL_VSLY_SHIFT (16)
++#define VDOASL_ISLY_MASK (0x7FFF)
++#define VDOASL_ISLY_SHIFT (0)
++#define VDOASRR_START_XFER (0x2)
++#define VDOASRR_SWRST (0x1)
++#define VDOAIEIST_TRANSFER_ERR (0x2)
++#define VDOAIEIST_TRANSFER_END (0x1)
++
++#define VDOAC (0x0) /* Control Register */
++#define VDOASRR (0x4) /* Start and Reset Register */
++#define VDOAIE (0x8) /* Interrupt Enable Register */
++#define VDOAIST (0xc) /* Interrupt Status Register */
++#define VDOAFP (0x10) /* Frame Parameters Register */
++#define VDOAIEBA00 (0x14) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA01 (0x18) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA02 (0x1c) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA10 (0x20) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA11 (0x24) /* External Buffer n Frame m Address Register */
++#define VDOAIEBA12 (0x28) /* External Buffer n Frame m Address Register */
++#define VDOASL (0x2c) /* IPU Stride Line Register */
++#define VDOAIUBO (0x30) /* IPU Chroma Buffer Offset Register */
++#define VDOAVEBA0 (0x34) /* External Buffer m Address Register */
++#define VDOAVEBA1 (0x38) /* External Buffer m Address Register */
++#define VDOAVEBA2 (0x3c) /* External Buffer m Address Register */
++#define VDOAVUBO (0x40) /* VPU Chroma Buffer Offset */
++#define VDOASR (0x44) /* Status Register */
++#define VDOATD (0x48) /* Test Debug Register */
++
++
++enum {
++ VDOA_INIT = 0x1,
++ VDOA_GET = 0x2,
++ VDOA_SETUP = 0x4,
++ VDOA_GET_OBUF = 0x8,
++ VDOA_START = 0x10,
++ VDOA_INIRQ = 0x20,
++ VDOA_STOP = 0x40,
++ VDOA_PUT = VDOA_INIT,
++};
++
++enum {
++ VDOA_NULL = 0,
++ VDOA_FRAME = 1,
++ VDOA_PREV_FIELD = 2,
++ VDOA_CURR_FIELD = 3,
++ VDOA_NEXT_FIELD = 4,
++};
++
++#define CHECK_STATE(expect, retcode) \
++do { \
++ if (!((expect) & vdoa->state)) { \
++ dev_err(vdoa->dev, "ERR: %s state:0x%x, expect:0x%x.\n",\
++ __func__, vdoa->state, (expect)); \
++ retcode; \
++ } \
++} while (0)
++
++#define CHECK_NULL_PTR(ptr) \
++do { \
++ pr_debug("vdoa_ptr:0x%p in %s state:0x%x.\n", \
++ vdoa, __func__, vdoa->state); \
++ if (NULL == (ptr)) { \
++ pr_err("ERR vdoa: %s state:0x%x null ptr.\n", \
++ __func__, vdoa->state); \
++ } \
++} while (0)
++
++struct vdoa_info {
++ int state;
++ struct device *dev;
++ struct clk *vdoa_clk;
++ void __iomem *reg_base;
++ struct gen_pool *iram_pool;
++ unsigned long iram_base;
++ unsigned long iram_paddr;
++ int irq;
++ int field;
++ struct completion comp;
++};
++
++static struct vdoa_info *g_vdoa;
++static unsigned long iram_size;
++static DEFINE_MUTEX(vdoa_lock);
++
++static inline void vdoa_read_register(struct vdoa_info *vdoa,
++ u32 reg, u32 *val)
++{
++ *val = ioread32(vdoa->reg_base + reg);
++ dev_dbg(vdoa->dev, "read_reg:0x%02x, val:0x%08x.\n", reg, *val);
++}
++
++static inline void vdoa_write_register(struct vdoa_info *vdoa,
++ u32 reg, u32 val)
++{
++ iowrite32(val, vdoa->reg_base + reg);
++ dev_dbg(vdoa->dev, "\t\twrite_reg:0x%02x, val:0x%08x.\n", reg, val);
++}
++
++static void dump_registers(struct vdoa_info *vdoa)
++{
++ int i;
++ u32 data;
++
++ for (i = VDOAC; i < VDOATD; i += 4)
++ vdoa_read_register(vdoa, i, &data);
++}
++
++int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params)
++{
++ int band_size;
++ int total_band_size = 0;
++ int ipu_stride;
++ u32 data;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET | VDOA_GET_OBUF | VDOA_STOP, return -EINVAL);
++ if (VDOA_GET == vdoa->state) {
++ dev_dbg(vdoa->dev, "w:%d, h:%d.\n",
++ params->width, params->height);
++ data = (params->band_lines == VDOAC_BAND_HEIGHT_32LINES) ? 2 :
++ ((params->band_lines == VDOAC_BAND_HEIGHT_16LINES) ?
++ 1 : 0);
++ data |= params->scan_order ? VDOAC_SCAN_ORDER_INTERLACED : 0;
++ data |= params->band_mode ? VDOAC_SYNC_BAND_MODE : 0;
++ data |= params->pfs ? VDOAC_PFS_YUYV : 0;
++ data |= params->ipu_num ? VDOAC_IPU_SEL_1 : 0;
++ vdoa_write_register(vdoa, VDOAC, data);
++
++ data = ((params->width & VDOAFP_FW_MASK) << VDOAFP_FW_SHIFT) |
++ ((params->height & VDOAFP_FH_MASK) << VDOAFP_FH_SHIFT);
++ vdoa_write_register(vdoa, VDOAFP, data);
++
++ ipu_stride = params->pfs ? params->width << 1 : params->width;
++ data = ((params->vpu_stride & VDOASL_VSLY_MASK) <<
++ VDOASL_VSLY_SHIFT) |
++ ((ipu_stride & VDOASL_ISLY_MASK) << VDOASL_ISLY_SHIFT);
++ vdoa_write_register(vdoa, VDOASL, data);
++
++ dev_dbg(vdoa->dev, "band_mode:%d, band_line:%d, base:0x%lx.\n",
++ params->band_mode, params->band_lines, vdoa->iram_paddr);
++ }
++ /*
++ * band size = (luma_per_line + chroma_per_line) * bandLines
++ * = width * (3/2 or 2) * bandLines
++ * double buffer mode used.
++ */
++ if (params->pfs)
++ band_size = (params->width << 1) * params->band_lines;
++ else
++ band_size = ((params->width * 3) >> 1) *
++ params->band_lines;
++ if (params->interlaced) {
++ total_band_size = 6 * band_size; /* 3 frames*double buffer */
++ if (iram_size < total_band_size) {
++ dev_err(vdoa->dev, "iram_size:0x%lx is smaller than "
++ "request:0x%x!\n", iram_size, total_band_size);
++ return -EINVAL;
++ }
++ if (params->vfield_buf.prev_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA00,
++ vdoa->iram_paddr);
++ vdoa_write_register(vdoa, VDOAIEBA10,
++ vdoa->iram_paddr + band_size);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA00,
++ params->ieba0);
++ vdoa_write_register(vdoa, VDOAVEBA0,
++ params->vfield_buf.prev_veba);
++ vdoa->field = VDOA_PREV_FIELD;
++ }
++ if (params->vfield_buf.cur_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA01,
++ vdoa->iram_paddr + band_size * 2);
++ vdoa_write_register(vdoa, VDOAIEBA11,
++ vdoa->iram_paddr + band_size * 3);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA01,
++ params->ieba1);
++ vdoa_write_register(vdoa, VDOAVEBA1,
++ params->vfield_buf.cur_veba);
++ vdoa->field = VDOA_CURR_FIELD;
++ }
++ if (params->vfield_buf.next_veba) {
++ if (params->band_mode) {
++ vdoa_write_register(vdoa, VDOAIEBA02,
++ vdoa->iram_paddr + band_size * 4);
++ vdoa_write_register(vdoa, VDOAIEBA12,
++ vdoa->iram_paddr + band_size * 5);
++ } else
++ vdoa_write_register(vdoa, VDOAIEBA02,
++ params->ieba2);
++ vdoa_write_register(vdoa, VDOAVEBA2,
++ params->vfield_buf.next_veba);
++ vdoa->field = VDOA_NEXT_FIELD;
++ vdoa_read_register(vdoa, VDOAC, &data);
++ data |= VDOAC_THREE_FRAMES;
++ vdoa_write_register(vdoa, VDOAC, data);
++ }
++
++ if (!params->pfs)
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->band_lines);
++ vdoa_write_register(vdoa, VDOAVUBO,
++ params->vfield_buf.vubo);
++ dev_dbg(vdoa->dev, "total band_size:0x%x.\n", band_size*6);
++ } else if (params->band_mode) {
++ /* used for progressive frame resize on PrP channel */
++ BUG(); /* currently not support */
++ /* progressvie frame: band mode */
++ vdoa_write_register(vdoa, VDOAIEBA00, vdoa->iram_paddr);
++ vdoa_write_register(vdoa, VDOAIEBA10,
++ vdoa->iram_paddr + band_size);
++ if (!params->pfs)
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->band_lines);
++ dev_dbg(vdoa->dev, "total band_size:0x%x\n", band_size*2);
++ } else {
++ /* progressive frame: mem->mem, non-band mode */
++ vdoa->field = VDOA_FRAME;
++ vdoa_write_register(vdoa, VDOAVEBA0, params->vframe_buf.veba);
++ vdoa_write_register(vdoa, VDOAVUBO, params->vframe_buf.vubo);
++ vdoa_write_register(vdoa, VDOAIEBA00, params->ieba0);
++ if (!params->pfs)
++ /* note: iubo is relative value, based on ieba0 */
++ vdoa_write_register(vdoa, VDOAIUBO,
++ params->width * params->height);
++ }
++ vdoa->state = VDOA_SETUP;
++ return 0;
++}
++
++void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf)
++{
++ u32 data;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_SETUP, return);
++ vdoa->state = VDOA_GET_OBUF;
++ memset(buf, 0, sizeof(*buf));
++
++ vdoa_read_register(vdoa, VDOAC, &data);
++ switch (vdoa->field) {
++ case VDOA_FRAME:
++ case VDOA_PREV_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA00, &buf->ieba0);
++ if (data & VDOAC_SYNC_BAND_MODE)
++ vdoa_read_register(vdoa, VDOAIEBA10, &buf->ieba1);
++ break;
++ case VDOA_CURR_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA01, &buf->ieba0);
++ vdoa_read_register(vdoa, VDOAIEBA11, &buf->ieba1);
++ break;
++ case VDOA_NEXT_FIELD:
++ vdoa_read_register(vdoa, VDOAIEBA02, &buf->ieba0);
++ vdoa_read_register(vdoa, VDOAIEBA12, &buf->ieba1);
++ break;
++ default:
++ BUG();
++ break;
++ }
++ if (!(data & VDOAC_PFS_YUYV))
++ vdoa_read_register(vdoa, VDOAIUBO, &buf->iubo);
++}
++
++int vdoa_start(vdoa_handle_t handle, int timeout_ms)
++{
++ int ret;
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET_OBUF, return -EINVAL);
++ vdoa->state = VDOA_START;
++ init_completion(&vdoa->comp);
++ vdoa_write_register(vdoa, VDOAIST,
++ VDOAIEIST_TRANSFER_ERR | VDOAIEIST_TRANSFER_END);
++ vdoa_write_register(vdoa, VDOAIE,
++ VDOAIEIST_TRANSFER_ERR | VDOAIEIST_TRANSFER_END);
++
++ enable_irq(vdoa->irq);
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_START_XFER);
++ dump_registers(vdoa);
++
++ ret = wait_for_completion_timeout(&vdoa->comp,
++ msecs_to_jiffies(timeout_ms));
++
++ return ret > 0 ? 0 : -ETIMEDOUT;
++}
++
++void vdoa_stop(vdoa_handle_t handle)
++{
++ struct vdoa_info *vdoa = (struct vdoa_info *)handle;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_GET | VDOA_START | VDOA_INIRQ, return);
++ vdoa->state = VDOA_STOP;
++
++ disable_irq(vdoa->irq);
++
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_SWRST);
++}
++
++void vdoa_get_handle(vdoa_handle_t *handle)
++{
++ struct vdoa_info *vdoa = g_vdoa;
++
++ CHECK_NULL_PTR(handle);
++ *handle = (vdoa_handle_t *)NULL;
++ CHECK_STATE(VDOA_INIT, return);
++ mutex_lock(&vdoa_lock);
++ clk_prepare_enable(vdoa->vdoa_clk);
++ vdoa->state = VDOA_GET;
++ vdoa->field = VDOA_NULL;
++ vdoa_write_register(vdoa, VDOASRR, VDOASRR_SWRST);
++
++ *handle = (vdoa_handle_t *)vdoa;
++}
++
++void vdoa_put_handle(vdoa_handle_t *handle)
++{
++ struct vdoa_info *vdoa = (struct vdoa_info *)(*handle);
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_STOP, return);
++ if (vdoa != g_vdoa)
++ BUG();
++
++ clk_disable_unprepare(vdoa->vdoa_clk);
++ vdoa->state = VDOA_PUT;
++ *handle = (vdoa_handle_t *)NULL;
++ mutex_unlock(&vdoa_lock);
++}
++
++static irqreturn_t vdoa_irq_handler(int irq, void *data)
++{
++ u32 status, mask, val;
++ struct vdoa_info *vdoa = data;
++
++ CHECK_NULL_PTR(vdoa);
++ CHECK_STATE(VDOA_START, return IRQ_HANDLED);
++ vdoa->state = VDOA_INIRQ;
++ vdoa_read_register(vdoa, VDOAIST, &status);
++ vdoa_read_register(vdoa, VDOAIE, &mask);
++ val = status & mask;
++ vdoa_write_register(vdoa, VDOAIST, val);
++ if (VDOAIEIST_TRANSFER_ERR & val)
++ dev_err(vdoa->dev, "vdoa Transfer err irq!\n");
++ if (VDOAIEIST_TRANSFER_END & val)
++ dev_dbg(vdoa->dev, "vdoa Transfer end irq!\n");
++ if (0 == val) {
++ dev_err(vdoa->dev, "vdoa unknown irq!\n");
++ BUG();
++ }
++
++ complete(&vdoa->comp);
++ return IRQ_HANDLED;
++}
++
++/* IRAM Size in Kbytes, example:vdoa_iram_size=64, 64KBytes */
++static int __init vdoa_iram_size_setup(char *options)
++{
++ int ret;
++
++ ret = strict_strtoul(options, 0, &iram_size);
++ if (ret)
++ iram_size = 0;
++ else
++ iram_size *= SZ_1K;
++
++ return 1;
++}
++__setup("vdoa_iram_size=", vdoa_iram_size_setup);
++
++static const struct of_device_id imx_vdoa_dt_ids[] = {
++ { .compatible = "fsl,imx6q-vdoa", },
++ { /* sentinel */ }
++};
++
++static int vdoa_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct vdoa_info *vdoa;
++ struct resource *res;
++ struct resource *res_irq;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(dev, "can't get device resources\n");
++ return -ENOENT;
++ }
++
++ res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++ if (!res_irq) {
++ dev_err(dev, "failed to get irq resource\n");
++ return -ENOENT;
++ }
++
++ vdoa = devm_kzalloc(dev, sizeof(struct vdoa_info), GFP_KERNEL);
++ if (!vdoa)
++ return -ENOMEM;
++ vdoa->dev = dev;
++
++ vdoa->reg_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (!vdoa->reg_base)
++ return -EBUSY;
++
++ vdoa->irq = res_irq->start;
++ ret = devm_request_irq(dev, vdoa->irq, vdoa_irq_handler, 0,
++ "vdoa", vdoa);
++ if (ret) {
++ dev_err(dev, "can't claim irq %d\n", vdoa->irq);
++ return ret;
++ }
++ disable_irq(vdoa->irq);
++
++ vdoa->vdoa_clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(vdoa->vdoa_clk)) {
++ dev_err(dev, "failed to get vdoa_clk\n");
++ return PTR_ERR(vdoa->vdoa_clk);
++ }
++
++ vdoa->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!vdoa->iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ return -ENOMEM;
++ }
++
++ if ((iram_size == 0) || (iram_size > MAX_VDOA_IRAM_SIZE))
++ iram_size = VDOA_IRAM_SIZE;
++
++ vdoa->iram_base = gen_pool_alloc(vdoa->iram_pool, iram_size);
++ if (!vdoa->iram_base) {
++ dev_err(&pdev->dev, "unable to alloc iram\n");
++ return -ENOMEM;
++ }
++
++ vdoa->iram_paddr = gen_pool_virt_to_phys(vdoa->iram_pool,
++ vdoa->iram_base);
++
++ dev_dbg(dev, "iram_base:0x%lx,iram_paddr:0x%lx,size:0x%lx\n",
++ vdoa->iram_base, vdoa->iram_paddr, iram_size);
++
++ vdoa->state = VDOA_INIT;
++ dev_set_drvdata(dev, vdoa);
++ g_vdoa = vdoa;
++ dev_info(dev, "i.MX Video Data Order Adapter(VDOA) driver probed\n");
++ return 0;
++}
++
++static int vdoa_remove(struct platform_device *pdev)
++{
++ struct vdoa_info *vdoa = dev_get_drvdata(&pdev->dev);
++
++ gen_pool_free(vdoa->iram_pool, vdoa->iram_base, iram_size);
++ kfree(vdoa);
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver vdoa_driver = {
++ .driver = {
++ .name = "mxc_vdoa",
++ .of_match_table = imx_vdoa_dt_ids,
++ },
++ .probe = vdoa_probe,
++ .remove = vdoa_remove,
++};
++
++static int __init vdoa_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&vdoa_driver);
++ if (err) {
++ pr_err("vdoa_driver register failed\n");
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static void __exit vdoa_cleanup(void)
++{
++ platform_driver_unregister(&vdoa_driver);
++}
++
++module_init(vdoa_init);
++module_exit(vdoa_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX Video Data Order Adapter(VDOA) driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/mxc/ipu3/vdoa.h linux-3.14.72/drivers/mxc/ipu3/vdoa.h
+--- linux-3.14.72.orig/drivers/mxc/ipu3/vdoa.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/ipu3/vdoa.h 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,69 @@
++/*
++ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __VDOA_H__
++#define __VDOA_H__
++
++#define VDOA_PFS_YUYV (1)
++#define VDOA_PFS_NV12 (0)
++
++
++struct vfield_buf {
++ u32 prev_veba;
++ u32 cur_veba;
++ u32 next_veba;
++ u32 vubo;
++};
++
++struct vframe_buf {
++ u32 veba;
++ u32 vubo;
++};
++
++struct vdoa_params {
++ u32 width;
++ u32 height;
++ int vpu_stride;
++ int interlaced;
++ int scan_order;
++ int ipu_num;
++ int band_lines;
++ int band_mode;
++ int pfs;
++ u32 ieba0;
++ u32 ieba1;
++ u32 ieba2;
++ struct vframe_buf vframe_buf;
++ struct vfield_buf vfield_buf;
++};
++struct vdoa_ipu_buf {
++ u32 ieba0;
++ u32 ieba1;
++ u32 iubo;
++};
++
++struct vdoa_info;
++typedef void *vdoa_handle_t;
++
++int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params);
++void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf);
++int vdoa_start(vdoa_handle_t handle, int timeout_ms);
++void vdoa_stop(vdoa_handle_t handle);
++void vdoa_get_handle(vdoa_handle_t *handle);
++void vdoa_put_handle(vdoa_handle_t *handle);
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/Kconfig linux-3.14.72/drivers/mxc/Kconfig
+--- linux-3.14.72.orig/drivers/mxc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/Kconfig 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,23 @@
++# drivers/mxc/Kconfig
++
++if ARCH_MXC
++
++menu "MXC support drivers"
++
++config MXC_IPU
++ bool "Image Processing Unit Driver"
++ select MXC_IPU_V3
++ help
++ If you plan to use the Image Processing unit, say
++ Y here. IPU is needed by Framebuffer and V4L2 drivers.
++
++source "drivers/mxc/gpu-viv/Kconfig"
++source "drivers/mxc/ipu3/Kconfig"
++source "drivers/mxc/vpu/Kconfig"
++source "drivers/mxc/hdmi-cec/Kconfig"
++source "drivers/mxc/mipi/Kconfig"
++source "drivers/mxc/mlb/Kconfig"
++
++endmenu
++
++endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/Makefile linux-3.14.72/drivers/mxc/Makefile
+--- linux-3.14.72.orig/drivers/mxc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/Makefile 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,6 @@
++obj-$(CONFIG_MXC_GPU_VIV) += gpu-viv/
++obj-$(CONFIG_MXC_IPU_V3) += ipu3/
++obj-$(CONFIG_MXC_VPU) += vpu/
++obj-$(CONFIG_MXC_HDMI_CEC) += hdmi-cec/
++obj-$(CONFIG_MXC_MIPI_CSI2) += mipi/
++obj-$(CONFIG_MXC_MLB) += mlb/
+diff -Nur linux-3.14.72.orig/drivers/mxc/mipi/Kconfig linux-3.14.72/drivers/mxc/mipi/Kconfig
+--- linux-3.14.72.orig/drivers/mxc/mipi/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/mipi/Kconfig 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,14 @@
++#
++# MIPI configuration
++#
++
++menu "MXC MIPI Support"
++
++config MXC_MIPI_CSI2
++ tristate "MIPI CSI2 support"
++ depends on SOC_IMX6Q
++ default n
++ ---help---
++ Say Y to get the MIPI CSI2 support.
++
++endmenu
+diff -Nur linux-3.14.72.orig/drivers/mxc/mipi/Makefile linux-3.14.72/drivers/mxc/mipi/Makefile
+--- linux-3.14.72.orig/drivers/mxc/mipi/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/mipi/Makefile 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,4 @@
++#
++# Makefile for the mipi interface driver
++#
++obj-$(CONFIG_MXC_MIPI_CSI2) += mxc_mipi_csi2.o
+diff -Nur linux-3.14.72.orig/drivers/mxc/mipi/mxc_mipi_csi2.c linux-3.14.72/drivers/mxc/mipi/mxc_mipi_csi2.c
+--- linux-3.14.72.orig/drivers/mxc/mipi/mxc_mipi_csi2.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/mipi/mxc_mipi_csi2.c 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,465 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/module.h>
++#include <linux/types.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/irqdesc.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++
++#include <linux/mipi_csi2.h>
++
++#include "mxc_mipi_csi2.h"
++
++static struct mipi_csi2_info *gmipi_csi2;
++static u8 dphy_clk;
++
++void _mipi_csi2_lock(struct mipi_csi2_info *info)
++{
++ if (!in_irq() && !in_softirq())
++ mutex_lock(&info->mutex_lock);
++}
++
++void _mipi_csi2_unlock(struct mipi_csi2_info *info)
++{
++ if (!in_irq() && !in_softirq())
++ mutex_unlock(&info->mutex_lock);
++}
++
++static inline void mipi_csi2_write(struct mipi_csi2_info *info,
++ unsigned value, unsigned offset)
++{
++ writel(value, info->mipi_csi2_base + offset);
++}
++
++static inline unsigned int mipi_csi2_read(struct mipi_csi2_info *info,
++ unsigned offset)
++{
++ return readl(info->mipi_csi2_base + offset);
++}
++
++/*!
++ * This function is called to enable the mipi csi2 interface.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++bool mipi_csi2_enable(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++
++ if (!info->mipi_en) {
++ info->mipi_en = true;
++ clk_prepare_enable(info->cfg_clk);
++ clk_prepare_enable(info->dphy_clk);
++ } else
++ mipi_dbg("mipi csi2 already enabled!\n");
++
++ status = info->mipi_en;
++
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_enable);
++
++/*!
++ * This function is called to disable the mipi csi2 interface.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++bool mipi_csi2_disable(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++
++ if (info->mipi_en) {
++ info->mipi_en = false;
++ clk_disable_unprepare(info->dphy_clk);
++ clk_disable_unprepare(info->cfg_clk);
++ } else
++ mipi_dbg("mipi csi2 already disabled!\n");
++
++ status = info->mipi_en;
++
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_disable);
++
++/*!
++ * This function is called to get mipi csi2 disable/enable status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns mipi csi2 status
++ */
++bool mipi_csi2_get_status(struct mipi_csi2_info *info)
++{
++ bool status;
++
++ _mipi_csi2_lock(info);
++ status = info->mipi_en;
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_get_status);
++
++/*!
++ * This function is called to set mipi lanes.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++int mipi_csi2_set_lanes(struct mipi_csi2_info *info, unsigned lanes)
++{
++ if (--lanes > 3)
++ return -EINVAL;
++
++ _mipi_csi2_lock(info);
++ mipi_csi2_write(info, lanes, MIPI_CSI2_N_LANES);
++ lanes = mipi_csi2_read(info, MIPI_CSI2_N_LANES);
++ _mipi_csi2_unlock(info);
++ return ++lanes;
++}
++EXPORT_SYMBOL(mipi_csi2_set_lanes);
++
++/*!
++ * This function is called to set mipi data type.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns setted value
++ */
++unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info,
++ unsigned int datatype)
++{
++ unsigned int dtype;
++
++ _mipi_csi2_lock(info);
++ info->datatype = datatype;
++ dtype = info->datatype;
++ _mipi_csi2_unlock(info);
++
++ return dtype;
++}
++EXPORT_SYMBOL(mipi_csi2_set_datatype);
++
++/*!
++ * This function is called to get mipi data type.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns mipi data type
++ */
++unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info)
++{
++ unsigned int dtype;
++
++ _mipi_csi2_lock(info);
++ dtype = info->datatype;
++ _mipi_csi2_unlock(info);
++
++ return dtype;
++}
++EXPORT_SYMBOL(mipi_csi2_get_datatype);
++
++/*!
++ * This function is called to get mipi csi2 dphy status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns dphy status
++ */
++unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info)
++{
++ unsigned int status;
++
++ _mipi_csi2_lock(info);
++ status = mipi_csi2_read(info, MIPI_CSI2_PHY_STATE);
++ _mipi_csi2_unlock(info);
++
++ return status;
++}
++EXPORT_SYMBOL(mipi_csi2_dphy_status);
++
++/*!
++ * This function is called to get mipi csi2 error1 status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns error1 value
++ */
++unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info)
++{
++ unsigned int err1;
++
++ _mipi_csi2_lock(info);
++ err1 = mipi_csi2_read(info, MIPI_CSI2_ERR1);
++ _mipi_csi2_unlock(info);
++
++ return err1;
++}
++EXPORT_SYMBOL(mipi_csi2_get_error1);
++
++/*!
++ * This function is called to get mipi csi2 error1 status.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns error1 value
++ */
++unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info)
++{
++ unsigned int err2;
++
++ _mipi_csi2_lock(info);
++ err2 = mipi_csi2_read(info, MIPI_CSI2_ERR2);
++ _mipi_csi2_unlock(info);
++
++ return err2;
++}
++EXPORT_SYMBOL(mipi_csi2_get_error2);
++
++/*!
++ * This function is called to enable mipi to ipu pixel clock.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info)
++{
++ return clk_prepare_enable(info->pixel_clk);
++}
++EXPORT_SYMBOL(mipi_csi2_pixelclk_enable);
++
++/*!
++ * This function is called to disable mipi to ipu pixel clock.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info)
++{
++ clk_disable_unprepare(info->pixel_clk);
++}
++EXPORT_SYMBOL(mipi_csi2_pixelclk_disable);
++
++/*!
++ * This function is called to power on mipi csi2.
++ *
++ * @param info mipi csi2 hander
++ * @return Returns 0 on success or negative error code on fail
++ */
++int mipi_csi2_reset(struct mipi_csi2_info *info)
++{
++ u32 tst_ctrl1 = (u32)0x0 | (u32)dphy_clk << 0;
++
++ _mipi_csi2_lock(info);
++
++ mipi_csi2_write(info, 0x0, MIPI_CSI2_PHY_SHUTDOWNZ);
++ mipi_csi2_write(info, 0x0, MIPI_CSI2_DPHY_RSTZ);
++ mipi_csi2_write(info, 0x0, MIPI_CSI2_CSI2_RESETN);
++
++ mipi_csi2_write(info, 0x00000001, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00010044, MIPI_CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, tst_ctrl1, MIPI_CSI2_PHY_TST_CTRL1);
++ mipi_csi2_write(info, 0x00000002, MIPI_CSI2_PHY_TST_CTRL0);
++ mipi_csi2_write(info, 0x00000000, MIPI_CSI2_PHY_TST_CTRL0);
++
++ mipi_csi2_write(info, 0xffffffff, MIPI_CSI2_PHY_SHUTDOWNZ);
++ mipi_csi2_write(info, 0xffffffff, MIPI_CSI2_DPHY_RSTZ);
++ mipi_csi2_write(info, 0xffffffff, MIPI_CSI2_CSI2_RESETN);
++
++ _mipi_csi2_unlock(info);
++
++ return 0;
++}
++EXPORT_SYMBOL(mipi_csi2_reset);
++
++/*!
++ * This function is called to get mipi csi2 info.
++ *
++ * @return Returns mipi csi2 info struct pointor
++ */
++struct mipi_csi2_info *mipi_csi2_get_info(void)
++{
++ return gmipi_csi2;
++}
++EXPORT_SYMBOL(mipi_csi2_get_info);
++
++/**
++ * This function is called by the driver framework to initialize the MIPI CSI2
++ * device.
++ *
++ * @param pdev The device structure for the MIPI CSI2 passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int mipi_csi2_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct resource *res;
++ u32 mipi_csi2_dphy_ver;
++ int ret;
++
++ gmipi_csi2 = kmalloc(sizeof(struct mipi_csi2_info), GFP_KERNEL);
++ if (!gmipi_csi2) {
++ ret = -ENOMEM;
++ goto alloc_failed;
++ }
++
++ /* initialize mutex */
++ mutex_init(&gmipi_csi2->mutex_lock);
++
++ /* get mipi csi2 informaiton */
++ gmipi_csi2->pdev = pdev;
++ gmipi_csi2->mipi_en = false;
++
++ gmipi_csi2->cfg_clk = devm_clk_get(dev, "cfg_clk");
++ if (IS_ERR(gmipi_csi2->cfg_clk)) {
++ dev_err(&pdev->dev, "failed to get cfg_clk\n");
++ ret = PTR_ERR(gmipi_csi2->cfg_clk);
++ goto err;
++ }
++
++ /* get mipi dphy clk */
++ gmipi_csi2->dphy_clk = devm_clk_get(dev, "dphy_clk");
++ if (IS_ERR(gmipi_csi2->dphy_clk)) {
++ dev_err(&pdev->dev, "failed to get dphy pll_ref_clk\n");
++ ret = PTR_ERR(gmipi_csi2->dphy_clk);
++ goto err;
++ }
++
++ /* get mipi to ipu pixel clk */
++ gmipi_csi2->pixel_clk = devm_clk_get(dev, "pixel_clk");
++ if (IS_ERR(gmipi_csi2->pixel_clk)) {
++ dev_err(&pdev->dev, "failed to get mipi pixel clk\n");
++ ret = PTR_ERR(gmipi_csi2->pixel_clk);
++ goto err;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ ret = -ENODEV;
++ goto err;
++ }
++
++ /* mipi register mapping */
++ gmipi_csi2->mipi_csi2_base = ioremap(res->start, PAGE_SIZE);
++ if (!gmipi_csi2->mipi_csi2_base) {
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ of_property_read_u8(np, "mipi_dphy_clk", &dphy_clk);
++ if (!dphy_clk) {
++ dphy_clk = 0x14;
++ }
++
++ /* mipi dphy clk enable for register access */
++ clk_prepare_enable(gmipi_csi2->dphy_clk);
++ /* get mipi csi2 dphy version */
++ mipi_csi2_dphy_ver = mipi_csi2_read(gmipi_csi2, MIPI_CSI2_VERSION);
++
++ clk_disable_unprepare(gmipi_csi2->dphy_clk);
++
++ platform_set_drvdata(pdev, gmipi_csi2);
++
++ dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed\n");
++ dev_info(&pdev->dev, "i.MX MIPI CSI2 dphy version is 0x%x\n",
++ mipi_csi2_dphy_ver);
++
++ return 0;
++
++err:
++ kfree(gmipi_csi2);
++alloc_failed:
++ dev_err(&pdev->dev, "i.MX MIPI CSI2 driver probed - error\n");
++ return ret;
++}
++
++static int mipi_csi2_remove(struct platform_device *pdev)
++{
++ /* unmapping mipi register */
++ iounmap(gmipi_csi2->mipi_csi2_base);
++
++ kfree(gmipi_csi2);
++
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static const struct of_device_id imx_mipi_csi2_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mipi-csi2", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver mipi_csi2_driver = {
++ .driver = {
++ .name = "mxc_mipi_csi2",
++ .of_match_table = imx_mipi_csi2_dt_ids,
++ },
++ .probe = mipi_csi2_probe,
++ .remove = mipi_csi2_remove,
++};
++
++static int __init mipi_csi2_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&mipi_csi2_driver);
++ if (err) {
++ pr_err("mipi_csi2_driver register failed\n");
++ return -ENODEV;
++ }
++
++ pr_info("MIPI CSI2 driver module loaded\n");
++
++ return 0;
++}
++
++static void __exit mipi_csi2_cleanup(void)
++{
++ platform_driver_unregister(&mipi_csi2_driver);
++}
++
++subsys_initcall(mipi_csi2_init);
++module_exit(mipi_csi2_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX MIPI CSI2 driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/mxc/mipi/mxc_mipi_csi2.h linux-3.14.72/drivers/mxc/mipi/mxc_mipi_csi2.h
+--- linux-3.14.72.orig/drivers/mxc/mipi/mxc_mipi_csi2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/mipi/mxc_mipi_csi2.h 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,42 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MXC_MIPI_CSI2_H__
++#define __MXC_MIPI_CSI2_H__
++
++#ifdef DEBUG
++#define mipi_dbg(fmt, ...) \
++ printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
++#else
++#define mipi_dbg(fmt, ...)
++#endif
++
++/* driver private data */
++struct mipi_csi2_info {
++ bool mipi_en;
++ unsigned int datatype;
++ struct clk *cfg_clk;
++ struct clk *dphy_clk;
++ struct clk *pixel_clk;
++ void __iomem *mipi_csi2_base;
++ struct platform_device *pdev;
++
++ struct mutex mutex_lock;
++};
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/mlb/Kconfig linux-3.14.72/drivers/mxc/mlb/Kconfig
+--- linux-3.14.72.orig/drivers/mxc/mlb/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/mlb/Kconfig 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,17 @@
++#
++# MLB150 configuration
++#
++
++menu "MXC Media Local Bus Driver"
++
++config MXC_MLB
++ boolean
++
++config MXC_MLB150
++ tristate "MLB150 support"
++ depends on SOC_IMX6Q
++ select MXC_MLB
++ ---help---
++ Say Y to get the MLB150 support.
++
++endmenu
+diff -Nur linux-3.14.72.orig/drivers/mxc/mlb/Makefile linux-3.14.72/drivers/mxc/mlb/Makefile
+--- linux-3.14.72.orig/drivers/mxc/mlb/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/mlb/Makefile 2016-06-19 22:11:55.257143157 +0200
+@@ -0,0 +1,5 @@
++#
++# Makefile for the i.MX6Q/DL MLB150 driver
++#
++
++obj-$(CONFIG_MXC_MLB150) += mxc_mlb.o
+diff -Nur linux-3.14.72.orig/drivers/mxc/mlb/mxc_mlb.c linux-3.14.72/drivers/mxc/mlb/mxc_mlb.c
+--- linux-3.14.72.orig/drivers/mxc/mlb/mxc_mlb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/mlb/mxc_mlb.c 2016-06-19 22:11:55.261142894 +0200
+@@ -0,0 +1,2785 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/cdev.h>
++#include <linux/circ_buf.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/fs.h>
++#include <linux/genalloc.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxc_mlb.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/uaccess.h>
++
++#define DRIVER_NAME "mxc_mlb150"
++
++/*
++ * MLB module memory map registers define
++ */
++#define REG_MLBC0 0x0
++#define MLBC0_MLBEN (0x1)
++#define MLBC0_MLBCLK_MASK (0x7 << 2)
++#define MLBC0_MLBCLK_SHIFT (2)
++#define MLBC0_MLBPEN (0x1 << 5)
++#define MLBC0_MLBLK (0x1 << 7)
++#define MLBC0_ASYRETRY (0x1 << 12)
++#define MLBC0_CTLRETRY (0x1 << 12)
++#define MLBC0_FCNT_MASK (0x7 << 15)
++#define MLBC0_FCNT_SHIFT (15)
++
++#define REG_MLBPC0 0x8
++#define MLBPC0_MCLKHYS (0x1 << 11)
++
++#define REG_MS0 0xC
++#define REG_MS1 0x14
++
++#define REG_MSS 0x20
++#define MSS_RSTSYSCMD (0x1)
++#define MSS_LKSYSCMD (0x1 << 1)
++#define MSS_ULKSYSCMD (0x1 << 2)
++#define MSS_CSSYSCMD (0x1 << 3)
++#define MSS_SWSYSCMD (0x1 << 4)
++#define MSS_SERVREQ (0x1 << 5)
++
++#define REG_MSD 0x24
++
++#define REG_MIEN 0x2C
++#define MIEN_ISOC_PE (0x1)
++#define MIEN_ISOC_BUFO (0x1 << 1)
++#define MIEN_SYNC_PE (0x1 << 16)
++#define MIEN_ARX_DONE (0x1 << 17)
++#define MIEN_ARX_PE (0x1 << 18)
++#define MIEN_ARX_BREAK (0x1 << 19)
++#define MIEN_ATX_DONE (0x1 << 20)
++#define MIEN_ATX_PE (0x1 << 21)
++#define MIEN_ATX_BREAK (0x1 << 22)
++#define MIEN_CRX_DONE (0x1 << 24)
++#define MIEN_CRX_PE (0x1 << 25)
++#define MIEN_CRX_BREAK (0x1 << 26)
++#define MIEN_CTX_DONE (0x1 << 27)
++#define MIEN_CTX_PE (0x1 << 28)
++#define MIEN_CTX_BREAK (0x1 << 29)
++
++#define REG_MLBPC2 0x34
++#define REG_MLBPC1 0x38
++#define MLBPC1_VAL (0x00000888)
++
++#define REG_MLBC1 0x3C
++#define MLBC1_LOCK (0x1 << 6)
++#define MLBC1_CLKM (0x1 << 7)
++#define MLBC1_NDA_MASK (0xFF << 8)
++#define MLBC1_NDA_SHIFT (8)
++
++#define REG_HCTL 0x80
++#define HCTL_RST0 (0x1)
++#define HCTL_RST1 (0x1 << 1)
++#define HCTL_EN (0x1 << 15)
++
++#define REG_HCMR0 0x88
++#define REG_HCMR1 0x8C
++#define REG_HCER0 0x90
++#define REG_HCER1 0x94
++#define REG_HCBR0 0x98
++#define REG_HCBR1 0x9C
++
++#define REG_MDAT0 0xC0
++#define REG_MDAT1 0xC4
++#define REG_MDAT2 0xC8
++#define REG_MDAT3 0xCC
++
++#define REG_MDWE0 0xD0
++#define REG_MDWE1 0xD4
++#define REG_MDWE2 0xD8
++#define REG_MDWE3 0xDC
++
++#define REG_MCTL 0xE0
++#define MCTL_XCMP (0x1)
++
++#define REG_MADR 0xE4
++#define MADR_WNR (0x1 << 31)
++#define MADR_TB (0x1 << 30)
++#define MADR_ADDR_MASK (0x7f << 8)
++#define MADR_ADDR_SHIFT (0)
++
++#define REG_ACTL 0x3C0
++#define ACTL_MPB (0x1 << 4)
++#define ACTL_DMAMODE (0x1 << 2)
++#define ACTL_SMX (0x1 << 1)
++#define ACTL_SCE (0x1)
++
++#define REG_ACSR0 0x3D0
++#define REG_ACSR1 0x3D4
++#define REG_ACMR0 0x3D8
++#define REG_ACMR1 0x3DC
++
++#define REG_CAT_MDATn(ch) (REG_MDAT0 + ((ch % 8) >> 1) * 4)
++#define REG_CAT_MDWEn(ch) (REG_MDWE0 + ((ch % 8) >> 1) * 4)
++
++#define INT_AHB0_CH_START (0)
++#define INT_AHB1_CH_START (32)
++
++#define LOGIC_CH_NUM (64)
++#define BUF_CDT_OFFSET (0x0)
++#define BUF_ADT_OFFSET (0x40)
++#define BUF_CAT_MLB_OFFSET (0x80)
++#define BUF_CAT_HBI_OFFSET (0x88)
++#define BUF_CTR_END_OFFSET (0x8F)
++
++#define CAT_MODE_RX (0x1 << 0)
++#define CAT_MODE_TX (0x1 << 1)
++#define CAT_MODE_INBOUND_DMA (0x1 << 8)
++#define CAT_MODE_OUTBOUND_DMA (0x1 << 9)
++
++#define CH_SYNC_DEFAULT_QUAD (1)
++#define CH_SYNC_MAX_QUAD (15)
++#define CH_SYNC_CDT_BUF_DEP (CH_SYNC_DEFAULT_QUAD * 4 * 4)
++#define CH_SYNC_ADT_BUF_MULTI (4)
++#define CH_SYNC_ADT_BUF_DEP (CH_SYNC_CDT_BUF_DEP * CH_SYNC_ADT_BUF_MULTI)
++#define CH_SYNC_BUF_SZ (CH_SYNC_MAX_QUAD * 4 * 4 * \
++ CH_SYNC_ADT_BUF_MULTI)
++#define CH_CTRL_CDT_BUF_DEP (64)
++#define CH_CTRL_ADT_BUF_DEP (CH_CTRL_CDT_BUF_DEP)
++#define CH_CTRL_BUF_SZ (CH_CTRL_ADT_BUF_DEP)
++#define CH_ASYNC_MDP_PACKET_LEN (1024)
++#define CH_ASYNC_MEP_PACKET_LEN (1536)
++#define CH_ASYNC_CDT_BUF_DEP (CH_ASYNC_MEP_PACKET_LEN)
++#define CH_ASYNC_ADT_BUF_DEP (CH_ASYNC_CDT_BUF_DEP)
++#define CH_ASYNC_BUF_SZ (CH_ASYNC_ADT_BUF_DEP)
++#define CH_ISOC_BLK_SIZE_188 (188)
++#define CH_ISOC_BLK_SIZE_196 (196)
++#define CH_ISOC_BLK_SIZE (CH_ISOC_BLK_SIZE_188)
++#define CH_ISOC_BLK_NUM (1)
++#define CH_ISOC_CDT_BUF_DEP (CH_ISOC_BLK_SIZE * CH_ISOC_BLK_NUM)
++#define CH_ISOC_ADT_BUF_DEP (CH_ISOC_CDT_BUF_DEP)
++#define CH_ISOC_BUF_SZ (1024)
++
++#define CH_SYNC_DBR_BUF_OFFSET (0x0)
++#define CH_CTRL_DBR_BUF_OFFSET (CH_SYNC_DBR_BUF_OFFSET + \
++ 2 * (CH_SYNC_MAX_QUAD * 4 * 4))
++#define CH_ASYNC_DBR_BUF_OFFSET (CH_CTRL_DBR_BUF_OFFSET + \
++ 2 * CH_CTRL_CDT_BUF_DEP)
++#define CH_ISOC_DBR_BUF_OFFSET (CH_ASYNC_DBR_BUF_OFFSET + \
++ 2 * CH_ASYNC_CDT_BUF_DEP)
++
++#define DBR_BUF_START 0x00000
++
++#define CDT_LEN (16)
++#define ADT_LEN (16)
++#define CAT_LEN (2)
++
++#define CDT_SZ (CDT_LEN * LOGIC_CH_NUM)
++#define ADT_SZ (ADT_LEN * LOGIC_CH_NUM)
++#define CAT_SZ (CAT_LEN * LOGIC_CH_NUM * 2)
++
++#define CDT_BASE(base) (base + BUF_CDT_OFFSET)
++#define ADT_BASE(base) (base + BUF_ADT_OFFSET)
++#define CAT_MLB_BASE(base) (base + BUF_CAT_MLB_OFFSET)
++#define CAT_HBI_BASE(base) (base + BUF_CAT_HBI_OFFSET)
++
++#define CDTn_ADDR(base, n) (base + BUF_CDT_OFFSET + n * CDT_LEN)
++#define ADTn_ADDR(base, n) (base + BUF_ADT_OFFSET + n * ADT_LEN)
++#define CATn_MLB_ADDR(base, n) (base + BUF_CAT_MLB_OFFSET + n * CAT_LEN)
++#define CATn_HBI_ADDR(base, n) (base + BUF_CAT_HBI_OFFSET + n * CAT_LEN)
++
++#define CAT_CL_SHIFT (0x0)
++#define CAT_CT_SHIFT (8)
++#define CAT_CE (0x1 << 11)
++#define CAT_RNW (0x1 << 12)
++#define CAT_MT (0x1 << 13)
++#define CAT_FCE (0x1 << 14)
++#define CAT_MFE (0x1 << 14)
++
++#define CDT_WSBC_SHIFT (14)
++#define CDT_WPC_SHIFT (11)
++#define CDT_RSBC_SHIFT (30)
++#define CDT_RPC_SHIFT (27)
++#define CDT_WPC_1_SHIFT (12)
++#define CDT_RPC_1_SHIFT (28)
++#define CDT_WPTR_SHIFT (0)
++#define CDT_SYNC_WSTS_MASK (0x0000f000)
++#define CDT_SYNC_WSTS_SHIFT (12)
++#define CDT_CTRL_ASYNC_WSTS_MASK (0x0000f000)
++#define CDT_CTRL_ASYNC_WSTS_SHIFT (12)
++#define CDT_ISOC_WSTS_MASK (0x0000e000)
++#define CDT_ISOC_WSTS_SHIFT (13)
++#define CDT_RPTR_SHIFT (16)
++#define CDT_SYNC_RSTS_MASK (0xf0000000)
++#define CDT_SYNC_RSTS_SHIFT (28)
++#define CDT_CTRL_ASYNC_RSTS_MASK (0xf0000000)
++#define CDT_CTRL_ASYNC_RSTS_SHIFT (28)
++#define CDT_ISOC_RSTS_MASK (0xe0000000)
++#define CDT_ISOC_RSTS_SHIFT (29)
++#define CDT_CTRL_ASYNC_WSTS_1 (0x1 << 14)
++#define CDT_CTRL_ASYNC_RSTS_1 (0x1 << 15)
++#define CDT_BD_SHIFT (0)
++#define CDT_BA_SHIFT (16)
++#define CDT_BS_SHIFT (0)
++#define CDT_BF_SHIFT (31)
++
++#define ADT_PG (0x1 << 13)
++#define ADT_LE (0x1 << 14)
++#define ADT_CE (0x1 << 15)
++#define ADT_BD1_SHIFT (0)
++#define ADT_ERR1 (0x1 << 13)
++#define ADT_DNE1 (0x1 << 14)
++#define ADT_RDY1 (0x1 << 15)
++#define ADT_BD2_SHIFT (16)
++#define ADT_ERR2 (0x1 << 29)
++#define ADT_DNE2 (0x1 << 30)
++#define ADT_RDY2 (0x1 << 31)
++#define ADT_BA1_SHIFT (0x0)
++#define ADT_BA2_SHIFT (0x0)
++#define ADT_PS1 (0x1 << 12)
++#define ADT_PS2 (0x1 << 28)
++#define ADT_MEP1 (0x1 << 11)
++#define ADT_MEP2 (0x1 << 27)
++
++#define MLB_MINOR_DEVICES 4
++#define MLB_CONTROL_DEV_NAME "ctrl"
++#define MLB_ASYNC_DEV_NAME "async"
++#define MLB_SYNC_DEV_NAME "sync"
++#define MLB_ISOC_DEV_NAME "isoc"
++
++#define TX_CHANNEL 0
++#define RX_CHANNEL 1
++
++#define TRANS_RING_NODES (1 << 3)
++#define MLB_QUIRK_MLB150 (1 << 0)
++
++enum MLB_CTYPE {
++ MLB_CTYPE_SYNC,
++ MLB_CTYPE_CTRL,
++ MLB_CTYPE_ASYNC,
++ MLB_CTYPE_ISOC,
++};
++
++enum CLK_SPEED {
++ CLK_256FS,
++ CLK_512FS,
++ CLK_1024FS,
++ CLK_2048FS,
++ CLK_3072FS,
++ CLK_4096FS,
++ CLK_6144FS,
++ CLK_8192FS,
++};
++
++enum MLB_INDEX {
++ IMX6Q_MLB = 0,
++ IMX6SX_MLB,
++};
++
++struct mlb_ringbuf {
++ s8 *virt_bufs[TRANS_RING_NODES];
++ u32 phy_addrs[TRANS_RING_NODES];
++ s32 head;
++ s32 tail;
++ s32 unit_size;
++ s32 total_size;
++ rwlock_t rb_lock ____cacheline_aligned; /* ring index lock */
++};
++
++struct mlb_channel_info {
++ /* Input MLB channel address */
++ u32 address;
++ /* Internal AHB channel label */
++ u32 cl;
++ /* DBR buf head */
++ u32 dbr_buf_head;
++};
++
++struct mlb_dev_info {
++ /* device node name */
++ const char dev_name[20];
++ /* channel type */
++ const unsigned int channel_type;
++ /* ch fps */
++ enum CLK_SPEED fps;
++ /* channel info for tx/rx */
++ struct mlb_channel_info channels[2];
++ /* ring buffer */
++ u8 *rbuf_base_virt;
++ u32 rbuf_base_phy;
++ struct mlb_ringbuf rx_rbuf;
++ struct mlb_ringbuf tx_rbuf;
++ /* exception event */
++ unsigned long ex_event;
++ /* tx busy indicator */
++ unsigned long tx_busy;
++ /* channel started up or not */
++ atomic_t on;
++ /* device open count */
++ atomic_t opencnt;
++ /* wait queue head for channel */
++ wait_queue_head_t rx_wq;
++ wait_queue_head_t tx_wq;
++ /* TX OK */
++ s32 tx_ok;
++ /* spinlock for event access */
++ spinlock_t event_lock;
++ /*
++ * Block size for isoc mode
++ * This variable can be configured in ioctl
++ */
++ u32 isoc_blksz;
++ /*
++ * Quads number for sync mode
++ * This variable can be confifured in ioctl
++ */
++ u32 sync_quad;
++ /* Buffer depth in cdt */
++ u32 cdt_buf_dep;
++ /* Buffer depth in adt */
++ u32 adt_buf_dep;
++ /* Buffer size to hold data */
++ u32 buf_size;
++};
++
++struct mlb_data {
++ struct mlb_dev_info *devinfo;
++ struct clk *clk_mlb3p;
++ struct clk *clk_mlb6p;
++ struct cdev cdev;
++ struct class *class; /* device class */
++ dev_t firstdev;
++ void __iomem *membase; /* mlb module base address */
++ struct gen_pool *iram_pool;
++ u32 iram_size;
++ u32 irq_ahb0;
++ u32 irq_ahb1;
++ u32 irq_mlb;
++ u32 quirk_flag;
++};
++
++/*
++ * For optimization, we use fixed channel label for
++ * input channels of each mode
++ * SYNC: CL = 0 for RX, CL = 64 for TX
++ * CTRL: CL = 1 for RX, CL = 65 for TX
++ * ASYNC: CL = 2 for RX, CL = 66 for TX
++ * ISOC: CL = 3 for RX, CL = 67 for TX
++ */
++#define SYNC_RX_CL_AHB0 0
++#define CTRL_RX_CL_AHB0 1
++#define ASYNC_RX_CL_AHB0 2
++#define ISOC_RX_CL_AHB0 3
++#define SYNC_TX_CL_AHB0 4
++#define CTRL_TX_CL_AHB0 5
++#define ASYNC_TX_CL_AHB0 6
++#define ISOC_TX_CL_AHB0 7
++
++#define SYNC_RX_CL_AHB1 32
++#define CTRL_RX_CL_AHB1 33
++#define ASYNC_RX_CL_AHB1 34
++#define ISOC_RX_CL_AHB1 35
++#define SYNC_TX_CL_AHB1 36
++#define CTRL_TX_CL_AHB1 37
++#define ASYNC_TX_CL_AHB1 38
++#define ISOC_TX_CL_AHB1 39
++
++#define SYNC_RX_CL SYNC_RX_CL_AHB0
++#define CTRL_RX_CL CTRL_RX_CL_AHB0
++#define ASYNC_RX_CL ASYNC_RX_CL_AHB0
++#define ISOC_RX_CL ISOC_RX_CL_AHB0
++
++#define SYNC_TX_CL SYNC_TX_CL_AHB0
++#define CTRL_TX_CL CTRL_TX_CL_AHB0
++#define ASYNC_TX_CL ASYNC_TX_CL_AHB0
++#define ISOC_TX_CL ISOC_TX_CL_AHB0
++
++static struct mlb_dev_info mlb_devinfo[MLB_MINOR_DEVICES] = {
++ {
++ .dev_name = MLB_SYNC_DEV_NAME,
++ .channel_type = MLB_CTYPE_SYNC,
++ .channels = {
++ [0] = {
++ .cl = SYNC_TX_CL,
++ .dbr_buf_head = CH_SYNC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = SYNC_RX_CL,
++ .dbr_buf_head = CH_SYNC_DBR_BUF_OFFSET
++ + CH_SYNC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_SYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[0].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_SYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[0].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_SYNC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_SYNC_ADT_BUF_DEP,
++ .buf_size = CH_SYNC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[0].event_lock),
++ },
++ {
++ .dev_name = MLB_CONTROL_DEV_NAME,
++ .channel_type = MLB_CTYPE_CTRL,
++ .channels = {
++ [0] = {
++ .cl = CTRL_TX_CL,
++ .dbr_buf_head = CH_CTRL_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = CTRL_RX_CL,
++ .dbr_buf_head = CH_CTRL_DBR_BUF_OFFSET
++ + CH_CTRL_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_CTRL_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[1].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_CTRL_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[1].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_CTRL_CDT_BUF_DEP,
++ .adt_buf_dep = CH_CTRL_ADT_BUF_DEP,
++ .buf_size = CH_CTRL_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[1].event_lock),
++ },
++ {
++ .dev_name = MLB_ASYNC_DEV_NAME,
++ .channel_type = MLB_CTYPE_ASYNC,
++ .channels = {
++ [0] = {
++ .cl = ASYNC_TX_CL,
++ .dbr_buf_head = CH_ASYNC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = ASYNC_RX_CL,
++ .dbr_buf_head = CH_ASYNC_DBR_BUF_OFFSET
++ + CH_ASYNC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_ASYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[2].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_ASYNC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[2].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_ASYNC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_ASYNC_ADT_BUF_DEP,
++ .buf_size = CH_ASYNC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[2].event_lock),
++ },
++ {
++ .dev_name = MLB_ISOC_DEV_NAME,
++ .channel_type = MLB_CTYPE_ISOC,
++ .channels = {
++ [0] = {
++ .cl = ISOC_TX_CL,
++ .dbr_buf_head = CH_ISOC_DBR_BUF_OFFSET,
++ },
++ [1] = {
++ .cl = ISOC_RX_CL,
++ .dbr_buf_head = CH_ISOC_DBR_BUF_OFFSET
++ + CH_ISOC_BUF_SZ,
++ },
++ },
++ .rx_rbuf = {
++ .unit_size = CH_ISOC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[3].rx_rbuf.rb_lock),
++ },
++ .tx_rbuf = {
++ .unit_size = CH_ISOC_BUF_SZ,
++ .rb_lock =
++ __RW_LOCK_UNLOCKED(mlb_devinfo[3].tx_rbuf.rb_lock),
++ },
++ .cdt_buf_dep = CH_ISOC_CDT_BUF_DEP,
++ .adt_buf_dep = CH_ISOC_ADT_BUF_DEP,
++ .buf_size = CH_ISOC_BUF_SZ,
++ .on = ATOMIC_INIT(0),
++ .opencnt = ATOMIC_INIT(0),
++ .event_lock = __SPIN_LOCK_UNLOCKED(mlb_devinfo[3].event_lock),
++ .isoc_blksz = CH_ISOC_BLK_SIZE_188,
++ },
++};
++
++static void __iomem *mlb_base;
++
++DEFINE_SPINLOCK(ctr_lock);
++
++#ifdef DEBUG
++#define DUMP_REG(reg) pr_debug(#reg": 0x%08x\n", __raw_readl(mlb_base + reg))
++
++static void mlb150_dev_dump_reg(void)
++{
++ pr_debug("mxc_mlb150: Dump registers:\n");
++ DUMP_REG(REG_MLBC0);
++ DUMP_REG(REG_MLBPC0);
++ DUMP_REG(REG_MS0);
++ DUMP_REG(REG_MS1);
++ DUMP_REG(REG_MSS);
++ DUMP_REG(REG_MSD);
++ DUMP_REG(REG_MIEN);
++ DUMP_REG(REG_MLBPC2);
++ DUMP_REG(REG_MLBPC1);
++ DUMP_REG(REG_MLBC1);
++ DUMP_REG(REG_HCTL);
++ DUMP_REG(REG_HCMR0);
++ DUMP_REG(REG_HCMR1);
++ DUMP_REG(REG_HCER0);
++ DUMP_REG(REG_HCER1);
++ DUMP_REG(REG_HCBR0);
++ DUMP_REG(REG_HCBR1);
++ DUMP_REG(REG_MDAT0);
++ DUMP_REG(REG_MDAT1);
++ DUMP_REG(REG_MDAT2);
++ DUMP_REG(REG_MDAT3);
++ DUMP_REG(REG_MDWE0);
++ DUMP_REG(REG_MDWE1);
++ DUMP_REG(REG_MDWE2);
++ DUMP_REG(REG_MDWE3);
++ DUMP_REG(REG_MCTL);
++ DUMP_REG(REG_MADR);
++ DUMP_REG(REG_ACTL);
++ DUMP_REG(REG_ACSR0);
++ DUMP_REG(REG_ACSR1);
++ DUMP_REG(REG_ACMR0);
++ DUMP_REG(REG_ACMR1);
++}
++
++static void mlb150_dev_dump_hex(const u8 *buf, u32 len)
++{
++ print_hex_dump(KERN_DEBUG, "CTR DUMP:",
++ DUMP_PREFIX_OFFSET, 8, 1, buf, len, 0);
++}
++#endif
++
++static inline void mlb150_dev_enable_ctr_write(u32 mdat0_bits_en,
++ u32 mdat1_bits_en, u32 mdat2_bits_en, u32 mdat3_bits_en)
++{
++ __raw_writel(mdat0_bits_en, mlb_base + REG_MDWE0);
++ __raw_writel(mdat1_bits_en, mlb_base + REG_MDWE1);
++ __raw_writel(mdat2_bits_en, mlb_base + REG_MDWE2);
++ __raw_writel(mdat3_bits_en, mlb_base + REG_MDWE3);
++}
++
++#ifdef DEBUG
++static inline u8 mlb150_dev_dbr_read(u32 dbr_addr)
++{
++ s32 timeout = 1000;
++ u8 dbr_val = 0;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(MADR_TB | dbr_addr,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (0 == timeout) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ return -ETIME;
++ }
++
++ dbr_val = __raw_readl(mlb_base + REG_MDAT0) & 0x000000ff;
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return dbr_val;
++}
++
++static inline s32 mlb150_dev_dbr_write(u32 dbr_addr, u8 dbr_val)
++{
++ s32 timeout = 1000;
++ u32 mdat0 = dbr_val & 0x000000ff;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(mdat0, mlb_base + REG_MDAT0);
++
++ __raw_writel(MADR_WNR | MADR_TB | dbr_addr,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ return -ETIME;
++ }
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_dbr_dump(u32 addr, u32 size)
++{
++ u8 *dump_buf = NULL;
++ u8 *buf_ptr = NULL;
++ s32 i;
++
++ dump_buf = kzalloc(size, GFP_KERNEL);
++ if (!dump_buf) {
++ pr_err("can't allocate enough memory\n");
++ return -ENOMEM;
++ }
++
++ for (i = 0, buf_ptr = dump_buf;
++ i < size; ++i, ++buf_ptr)
++ *buf_ptr = mlb150_dev_dbr_read(addr + i);
++
++ mlb150_dev_dump_hex(dump_buf, size);
++
++ kfree(dump_buf);
++
++ return 0;
++}
++#endif
++
++static s32 mlb150_dev_ctr_read(u32 ctr_offset, u32 *ctr_val)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(ctr_offset, mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Read CTR timeout\n");
++ return -ETIME;
++ }
++
++ ctr_val[0] = __raw_readl(mlb_base + REG_MDAT0);
++ ctr_val[1] = __raw_readl(mlb_base + REG_MDAT1);
++ ctr_val[2] = __raw_readl(mlb_base + REG_MDAT2);
++ ctr_val[3] = __raw_readl(mlb_base + REG_MDAT3);
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++ return 0;
++}
++
++static s32 mlb150_dev_ctr_write(u32 ctr_offset, const u32 *ctr_val)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++
++ __raw_writel(ctr_val[0], mlb_base + REG_MDAT0);
++ __raw_writel(ctr_val[1], mlb_base + REG_MDAT1);
++ __raw_writel(ctr_val[2], mlb_base + REG_MDAT2);
++ __raw_writel(ctr_val[3], mlb_base + REG_MDAT3);
++
++ __raw_writel(MADR_WNR | ctr_offset,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Write CTR timeout\n");
++ return -ETIME;
++ }
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++#ifdef DEBUG_CTR
++ {
++ u32 ctr_rd[4] = { 0 };
++
++ if (!mlb150_dev_ctr_read(ctr_offset, ctr_rd)) {
++ if (ctr_val[0] == ctr_rd[0] &&
++ ctr_val[1] == ctr_rd[1] &&
++ ctr_val[2] == ctr_rd[2] &&
++ ctr_val[3] == ctr_rd[3])
++ return 0;
++ else {
++ pr_debug("mxc_mlb150: ctr write failed\n");
++ pr_debug("offset: 0x%x\n", ctr_offset);
++ pr_debug("Write: 0x%x 0x%x 0x%x 0x%x\n",
++ ctr_val[3], ctr_val[2],
++ ctr_val[1], ctr_val[0]);
++ pr_debug("Read: 0x%x 0x%x 0x%x 0x%x\n",
++ ctr_rd[3], ctr_rd[2],
++ ctr_rd[1], ctr_rd[0]);
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: ctr read failed\n");
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++#ifdef DEBUG
++static s32 mlb150_dev_cat_read(u32 ctr_offset, u32 ch, u16 *cat_val)
++{
++ u16 ctr_val[8] = { 0 };
++
++ if (mlb150_dev_ctr_read(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ /*
++ * Use u16 array to get u32 array value,
++ * need to convert
++ */
++ cat_val = ctr_val[ch % 8];
++
++ return 0;
++}
++#endif
++
++static s32 mlb150_dev_cat_write(u32 ctr_offset, u32 ch, const u16 cat_val)
++{
++ u16 ctr_val[8] = { 0 };
++
++ if (mlb150_dev_ctr_read(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ ctr_val[ch % 8] = cat_val;
++ if (mlb150_dev_ctr_write(ctr_offset, (u32 *)ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++#define mlb150_dev_cat_mlb_read(ch, cat_val) \
++ mlb150_dev_cat_read(BUF_CAT_MLB_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_mlb_write(ch, cat_val) \
++ mlb150_dev_cat_write(BUF_CAT_MLB_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_hbi_read(ch, cat_val) \
++ mlb150_dev_cat_read(BUF_CAT_HBI_OFFSET + (ch >> 3), ch, cat_val)
++#define mlb150_dev_cat_hbi_write(ch, cat_val) \
++ mlb150_dev_cat_write(BUF_CAT_HBI_OFFSET + (ch >> 3), ch, cat_val)
++
++#define mlb150_dev_cdt_read(ch, cdt_val) \
++ mlb150_dev_ctr_read(BUF_CDT_OFFSET + ch, cdt_val)
++#define mlb150_dev_cdt_write(ch, cdt_val) \
++ mlb150_dev_ctr_write(BUF_CDT_OFFSET + ch, cdt_val)
++#define mlb150_dev_adt_read(ch, adt_val) \
++ mlb150_dev_ctr_read(BUF_ADT_OFFSET + ch, adt_val)
++#define mlb150_dev_adt_write(ch, adt_val) \
++ mlb150_dev_ctr_write(BUF_ADT_OFFSET + ch, adt_val)
++
++static s32 mlb150_dev_get_adt_sts(u32 ch)
++{
++ s32 timeout = 1000;
++ unsigned long flags;
++ u32 reg;
++
++ spin_lock_irqsave(&ctr_lock, flags);
++ __raw_writel(BUF_ADT_OFFSET + ch,
++ mlb_base + REG_MADR);
++
++ while ((!(__raw_readl(mlb_base + REG_MCTL)
++ & MCTL_XCMP)) &&
++ timeout--)
++ ;
++
++ if (timeout <= 0) {
++ spin_unlock_irqrestore(&ctr_lock, flags);
++ pr_debug("mxc_mlb150: Read CTR timeout\n");
++ return -ETIME;
++ }
++
++ reg = __raw_readl(mlb_base + REG_MDAT1);
++
++ __raw_writel(0, mlb_base + REG_MCTL);
++ spin_unlock_irqrestore(&ctr_lock, flags);
++
++#ifdef DEBUG_ADT
++ pr_debug("mxc_mlb150: Get ch %d adt sts: 0x%08x\n", ch, reg);
++#endif
++
++ return reg;
++}
++
++#ifdef DEBUG
++static void mlb150_dev_dump_ctr_tbl(u32 ch_start, u32 ch_end)
++{
++ u32 i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ pr_debug("mxc_mlb150: CDT Table");
++ for (i = BUF_CDT_OFFSET + ch_start;
++ i < BUF_CDT_OFFSET + ch_end;
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: ADT Table");
++ for (i = BUF_ADT_OFFSET + ch_start;
++ i < BUF_ADT_OFFSET + ch_end;
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: CAT MLB Table");
++ for (i = BUF_CAT_MLB_OFFSET + (ch_start >> 3);
++ i <= BUF_CAT_MLB_OFFSET + ((ch_end + 8) >> 3);
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++
++ pr_debug("mxc_mlb150: CAT HBI Table");
++ for (i = BUF_CAT_HBI_OFFSET + (ch_start >> 3);
++ i <= BUF_CAT_HBI_OFFSET + ((ch_end + 8) >> 3);
++ ++i) {
++ mlb150_dev_ctr_read(i, ctr_val);
++ pr_debug("CTR 0x%02x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
++ i, ctr_val[3], ctr_val[2], ctr_val[1], ctr_val[0]);
++ }
++}
++#endif
++
++/*
++ * Initial the MLB module device
++ */
++static inline void mlb150_dev_enable_dma_irq(u32 enable)
++{
++ u32 ch_rx_mask = (1 << SYNC_RX_CL_AHB0) | (1 << CTRL_RX_CL_AHB0)
++ | (1 << ASYNC_RX_CL_AHB0) | (1 << ISOC_RX_CL_AHB0)
++ | (1 << SYNC_TX_CL_AHB0) | (1 << CTRL_TX_CL_AHB0)
++ | (1 << ASYNC_TX_CL_AHB0) | (1 << ISOC_TX_CL_AHB0);
++ u32 ch_tx_mask = (1 << (SYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (SYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_TX_CL_AHB1 - INT_AHB1_CH_START));
++
++ if (enable) {
++ __raw_writel(ch_rx_mask, mlb_base + REG_ACMR0);
++ __raw_writel(ch_tx_mask, mlb_base + REG_ACMR1);
++ } else {
++ __raw_writel(0x0, mlb_base + REG_ACMR0);
++ __raw_writel(0x0, mlb_base + REG_ACMR1);
++ }
++}
++
++
++static void mlb150_dev_init_ir_amba_ahb(void)
++{
++ u32 reg = 0;
++
++ /*
++ * Step 1. Program the ACMRn registers to enable interrupts from all
++ * active DMA channels
++ */
++ mlb150_dev_enable_dma_irq(1);
++
++ /*
++ * Step 2. Select the status clear method:
++ * ACTL.SCE = 0, hardware clears on read
++ * ACTL.SCE = 1, software writes a '1' to clear
++ * We only support DMA MODE 1
++ */
++ reg = __raw_readl(mlb_base + REG_ACTL);
++ reg |= ACTL_DMAMODE;
++#ifdef MULTIPLE_PACKAGE_MODE
++ reg |= REG_ACTL_MPB;
++#endif
++
++ /*
++ * Step 3. Select 1 or 2 interrupt signals:
++ * ACTL.SMX = 0: one interrupt for channels 0 - 31 on ahb_init[0]
++ * and another interrupt for channels 32 - 63 on ahb_init[1]
++ * ACTL.SMX = 1: singel interrupt all channels on ahb_init[0]
++ */
++ reg &= ~ACTL_SMX;
++
++ __raw_writel(reg, mlb_base + REG_ACTL);
++}
++
++static inline void mlb150_dev_enable_ir_mlb(u32 enable)
++{
++ /*
++ * Step 1, Select the MSn to be cleared by software,
++ * writing a '0' to the appropriate bits
++ */
++ __raw_writel(0, mlb_base + REG_MS0);
++ __raw_writel(0, mlb_base + REG_MS1);
++
++ /*
++ * Step 1, Program MIEN to enable protocol error
++ * interrupts for all active MLB channels
++ */
++ if (enable)
++ __raw_writel(MIEN_CTX_PE |
++ MIEN_CRX_PE | MIEN_ATX_PE |
++ MIEN_ARX_PE | MIEN_SYNC_PE |
++ MIEN_ISOC_PE,
++ mlb_base + REG_MIEN);
++ else
++ __raw_writel(0, mlb_base + REG_MIEN);
++}
++
++static inline void mlb150_enable_pll(struct mlb_data *drvdata)
++{
++ u32 c0_val;
++
++ __raw_writel(MLBPC1_VAL,
++ drvdata->membase + REG_MLBPC1);
++
++ c0_val = __raw_readl(drvdata->membase + REG_MLBC0);
++ if (c0_val & MLBC0_MLBPEN) {
++ c0_val &= ~MLBC0_MLBPEN;
++ __raw_writel(c0_val,
++ drvdata->membase + REG_MLBC0);
++ }
++
++ clk_prepare_enable(drvdata->clk_mlb6p);
++
++ c0_val |= (MLBC0_MLBPEN);
++ __raw_writel(c0_val, drvdata->membase + REG_MLBC0);
++}
++
++static inline void mlb150_disable_pll(struct mlb_data *drvdata)
++{
++ u32 c0_val;
++
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ c0_val = __raw_readl(drvdata->membase + REG_MLBC0);
++
++ __raw_writel(0x0, drvdata->membase + REG_MLBPC1);
++
++ c0_val &= ~MLBC0_MLBPEN;
++ __raw_writel(c0_val, drvdata->membase + REG_MLBC0);
++}
++
++static void mlb150_dev_reset_cdt(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM); ++i)
++ mlb150_dev_ctr_write(BUF_CDT_OFFSET + i, ctr_val);
++}
++
++static s32 mlb150_dev_init_ch_cdt(struct mlb_dev_info *pdevinfo, u32 ch,
++ enum MLB_CTYPE ctype, u32 ch_func)
++{
++ u32 cdt_val[4] = { 0 };
++
++ /* a. Set the 14-bit base address (BA) */
++ pr_debug("mxc_mlb150: ctype: %d, ch: %d, dbr_buf_head: 0x%08x",
++ ctype, ch, pdevinfo->channels[ch_func].dbr_buf_head);
++ cdt_val[3] = (pdevinfo->channels[ch_func].dbr_buf_head)
++ << CDT_BA_SHIFT;
++ /*
++ * b. Set the 12-bit or 13-bit buffer depth (BD)
++ * BD = buffer depth in bytes - 1
++ * For synchronous channels: (BD + 1) = 4 * m * bpf
++ * For control channels: (BD + 1) >= max packet length (64)
++ * For asynchronous channels: (BD + 1) >= max packet length
++ * 1024 for a MOST Data packet (MDP);
++ * 1536 for a MOST Ethernet Packet (MEP)
++ * For isochronous channels: (BD + 1) mod (BS + 1) = 0
++ * BS
++ */
++ if (MLB_CTYPE_ISOC == ctype)
++ cdt_val[1] |= (pdevinfo->isoc_blksz - 1);
++ /* BD */
++ cdt_val[3] |= (pdevinfo->cdt_buf_dep - 1) << CDT_BD_SHIFT;
++
++ pr_debug("mxc_mlb150: Set CDT val of channel %d, type: %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ ch, ctype, cdt_val[3], cdt_val[2], cdt_val[1], cdt_val[0]);
++
++ if (mlb150_dev_cdt_write(ch, cdt_val))
++ return -ETIME;
++
++#ifdef DEBUG_CTR
++ {
++ u32 cdt_rd[4] = { 0 };
++ if (!mlb150_dev_cdt_read(ch, cdt_rd)) {
++ pr_debug("mxc_mlb150: CDT val of channel %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ ch, cdt_rd[3], cdt_rd[2], cdt_rd[1], cdt_rd[0]);
++ if (cdt_rd[3] == cdt_val[3] &&
++ cdt_rd[2] == cdt_val[2] &&
++ cdt_rd[1] == cdt_val[1] &&
++ cdt_rd[0] == cdt_val[0]) {
++ pr_debug("mxc_mlb150: set cdt succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set cdt failed!\n");
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: Read CDT val of channel %d failed\n",
++ ch);
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++static s32 mlb150_dev_init_ch_cat(u32 ch, u32 cl,
++ u32 cat_mode, enum MLB_CTYPE ctype)
++{
++ u16 cat_val = 0;
++#ifdef DEBUG_CTR
++ u16 cat_rd = 0;
++#endif
++
++ cat_val = CAT_CE | (ctype << CAT_CT_SHIFT) | cl;
++
++ if (cat_mode & CAT_MODE_OUTBOUND_DMA)
++ cat_val |= CAT_RNW;
++
++ if (MLB_CTYPE_SYNC == ctype)
++ cat_val |= CAT_MT;
++
++ switch (cat_mode) {
++ case CAT_MODE_RX | CAT_MODE_INBOUND_DMA:
++ case CAT_MODE_TX | CAT_MODE_OUTBOUND_DMA:
++ pr_debug("mxc_mlb150: set CAT val of channel %d, type: %d: 0x%04x\n",
++ ch, ctype, cat_val);
++
++ if (mlb150_dev_cat_mlb_write(ch, cat_val))
++ return -ETIME;
++#ifdef DEBUG_CTR
++ if (!mlb150_dev_cat_mlb_read(ch, &cat_rd))
++ pr_debug("mxc_mlb150: CAT val of mlb channel %d: 0x%04x",
++ ch, cat_rd);
++ else {
++ pr_debug("mxc_mlb150: Read CAT of mlb channel %d failed\n",
++ ch);
++ return -EBADE;
++ }
++#endif
++ break;
++ case CAT_MODE_TX | CAT_MODE_INBOUND_DMA:
++ case CAT_MODE_RX | CAT_MODE_OUTBOUND_DMA:
++ pr_debug("mxc_mlb150: set CAT val of channel %d, type: %d: 0x%04x\n",
++ cl, ctype, cat_val);
++
++ if (mlb150_dev_cat_hbi_write(cl, cat_val))
++ return -ETIME;
++#ifdef DEBUG_CTR
++ if (!mlb150_dev_cat_hbi_read(cl, &cat_rd))
++ pr_debug("mxc_mlb150: CAT val of hbi channel %d: 0x%04x",
++ cl, cat_rd);
++ else {
++ pr_debug("mxc_mlb150: Read CAT of hbi channel %d failed\n",
++ cl);
++ return -EBADE;
++ }
++#endif
++ break;
++ default:
++ return EBADRQC;
++ }
++
++#ifdef DEBUG_CTR
++ {
++ if (cat_val == cat_rd) {
++ pr_debug("mxc_mlb150: set cat succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set cat failed!\n");
++ return -EBADE;
++ }
++ }
++#endif
++ return 0;
++}
++
++static void mlb150_dev_reset_cat(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM >> 3); ++i) {
++ mlb150_dev_ctr_write(BUF_CAT_MLB_OFFSET + i, ctr_val);
++ mlb150_dev_ctr_write(BUF_CAT_HBI_OFFSET + i, ctr_val);
++ }
++}
++
++static void mlb150_dev_init_rfb(struct mlb_dev_info *pdevinfo, u32 rx_ch,
++ u32 tx_ch, enum MLB_CTYPE ctype)
++{
++ u32 rx_cl = pdevinfo->channels[RX_CHANNEL].cl;
++ u32 tx_cl = pdevinfo->channels[TX_CHANNEL].cl;
++ /* Step 1, Initialize all bits of CAT to '0' */
++ mlb150_dev_reset_cat();
++ mlb150_dev_reset_cdt();
++ /*
++ * Step 2, Initialize logical channel
++ * Step 3, Program the CDT for channel N
++ */
++ mlb150_dev_init_ch_cdt(pdevinfo, rx_cl, ctype, RX_CHANNEL);
++ mlb150_dev_init_ch_cdt(pdevinfo, tx_cl, ctype, TX_CHANNEL);
++
++ /* Step 4&5, Program the CAT for the inbound and outbound DMA */
++ mlb150_dev_init_ch_cat(rx_ch, rx_cl,
++ CAT_MODE_RX | CAT_MODE_INBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(rx_ch, rx_cl,
++ CAT_MODE_RX | CAT_MODE_OUTBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(tx_ch, tx_cl,
++ CAT_MODE_TX | CAT_MODE_INBOUND_DMA,
++ ctype);
++ mlb150_dev_init_ch_cat(tx_ch, tx_cl,
++ CAT_MODE_TX | CAT_MODE_OUTBOUND_DMA,
++ ctype);
++}
++
++static void mlb150_dev_reset_adt(void)
++{
++ int i = 0;
++ u32 ctr_val[4] = { 0 };
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++
++ for (i = 0; i < (LOGIC_CH_NUM); ++i)
++ mlb150_dev_ctr_write(BUF_ADT_OFFSET + i, ctr_val);
++}
++
++static void mlb150_dev_reset_whole_ctr(void)
++{
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++ mlb150_dev_reset_cdt();
++ mlb150_dev_reset_adt();
++ mlb150_dev_reset_cat();
++}
++
++#define CLR_REG(reg) __raw_writel(0x0, mlb_base + reg)
++
++static void mlb150_dev_reset_all_regs(void)
++{
++ CLR_REG(REG_MLBC0);
++ CLR_REG(REG_MLBPC0);
++ CLR_REG(REG_MS0);
++ CLR_REG(REG_MS1);
++ CLR_REG(REG_MSS);
++ CLR_REG(REG_MSD);
++ CLR_REG(REG_MIEN);
++ CLR_REG(REG_MLBPC2);
++ CLR_REG(REG_MLBPC1);
++ CLR_REG(REG_MLBC1);
++ CLR_REG(REG_HCTL);
++ CLR_REG(REG_HCMR0);
++ CLR_REG(REG_HCMR1);
++ CLR_REG(REG_HCER0);
++ CLR_REG(REG_HCER1);
++ CLR_REG(REG_HCBR0);
++ CLR_REG(REG_HCBR1);
++ CLR_REG(REG_MDAT0);
++ CLR_REG(REG_MDAT1);
++ CLR_REG(REG_MDAT2);
++ CLR_REG(REG_MDAT3);
++ CLR_REG(REG_MDWE0);
++ CLR_REG(REG_MDWE1);
++ CLR_REG(REG_MDWE2);
++ CLR_REG(REG_MDWE3);
++ CLR_REG(REG_MCTL);
++ CLR_REG(REG_MADR);
++ CLR_REG(REG_ACTL);
++ CLR_REG(REG_ACSR0);
++ CLR_REG(REG_ACSR1);
++ CLR_REG(REG_ACMR0);
++ CLR_REG(REG_ACMR1);
++}
++
++static inline s32 mlb150_dev_pipo_start(struct mlb_ringbuf *rbuf,
++ u32 ahb_ch, u32 buf_addr)
++{
++ u32 ctr_val[4] = { 0 };
++
++ ctr_val[1] |= ADT_RDY1;
++ ctr_val[2] = buf_addr;
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_pipo_next(u32 ahb_ch, enum MLB_CTYPE ctype,
++ u32 dne_sts, u32 buf_addr)
++{
++ u32 ctr_val[4] = { 0 };
++
++ if (MLB_CTYPE_ASYNC == ctype ||
++ MLB_CTYPE_CTRL == ctype) {
++ ctr_val[1] |= ADT_PS1;
++ ctr_val[1] |= ADT_PS2;
++ }
++
++ /*
++ * Clear DNE1 and ERR1
++ * Set the page ready bit (RDY1)
++ */
++ if (dne_sts & ADT_DNE1) {
++ ctr_val[1] |= ADT_RDY2;
++ ctr_val[3] = buf_addr;
++ } else {
++ ctr_val[1] |= ADT_RDY1;
++ ctr_val[2] = buf_addr;
++ }
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static inline s32 mlb150_dev_pipo_stop(struct mlb_ringbuf *rbuf, u32 ahb_ch)
++{
++ u32 ctr_val[4] = { 0 };
++ unsigned long flags;
++
++ write_lock_irqsave(&rbuf->rb_lock, flags);
++ rbuf->head = rbuf->tail = 0;
++ write_unlock_irqrestore(&rbuf->rb_lock, flags);
++
++ if (mlb150_dev_adt_write(ahb_ch, ctr_val))
++ return -ETIME;
++
++ return 0;
++}
++
++static s32 mlb150_dev_init_ch_amba_ahb(struct mlb_dev_info *pdevinfo,
++ struct mlb_channel_info *chinfo,
++ enum MLB_CTYPE ctype)
++{
++ u32 ctr_val[4] = { 0 };
++
++ /* a. Set the 32-bit base address (BA1) */
++ ctr_val[3] = 0;
++ ctr_val[2] = 0;
++ ctr_val[1] = (pdevinfo->adt_buf_dep - 1) << ADT_BD1_SHIFT;
++ ctr_val[1] |= (pdevinfo->adt_buf_dep - 1) << ADT_BD2_SHIFT;
++ if (MLB_CTYPE_ASYNC == ctype ||
++ MLB_CTYPE_CTRL == ctype) {
++ ctr_val[1] |= ADT_PS1;
++ ctr_val[1] |= ADT_PS2;
++ }
++
++ ctr_val[0] |= (ADT_LE | ADT_CE);
++
++ pr_debug("mxc_mlb150: Set ADT val of channel %d, ctype: %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ chinfo->cl, ctype, ctr_val[3], ctr_val[2],
++ ctr_val[1], ctr_val[0]);
++
++ if (mlb150_dev_adt_write(chinfo->cl, ctr_val))
++ return -ETIME;
++
++#ifdef DEBUG_CTR
++ {
++ u32 ctr_rd[4] = { 0 };
++ if (!mlb150_dev_adt_read(chinfo->cl, ctr_rd)) {
++ pr_debug("mxc_mlb150: ADT val of channel %d: "
++ "0x%08x 0x%08x 0x%08x 0x%08x\n",
++ chinfo->cl, ctr_rd[3], ctr_rd[2],
++ ctr_rd[1], ctr_rd[0]);
++ if (ctr_rd[3] == ctr_val[3] &&
++ ctr_rd[2] == ctr_val[2] &&
++ ctr_rd[1] == ctr_val[1] &&
++ ctr_rd[0] == ctr_val[0]) {
++ pr_debug("mxc_mlb150: set adt succeed!\n");
++ return 0;
++ } else {
++ pr_debug("mxc_mlb150: set adt failed!\n");
++ return -EBADE;
++ }
++ } else {
++ pr_debug("mxc_mlb150: Read ADT val of channel %d failed\n",
++ chinfo->cl);
++ return -EBADE;
++ }
++ }
++#endif
++
++ return 0;
++}
++
++static void mlb150_dev_init_amba_ahb(struct mlb_dev_info *pdevinfo,
++ enum MLB_CTYPE ctype)
++{
++ struct mlb_channel_info *tx_chinfo = &pdevinfo->channels[TX_CHANNEL];
++ struct mlb_channel_info *rx_chinfo = &pdevinfo->channels[RX_CHANNEL];
++
++ /* Step 1, Initialize all bits of the ADT to '0' */
++ mlb150_dev_reset_adt();
++
++ /*
++ * Step 2, Select a logic channel
++ * Step 3, Program the AMBA AHB block ping page for channel N
++ * Step 4, Program the AMBA AHB block pong page for channel N
++ */
++ mlb150_dev_init_ch_amba_ahb(pdevinfo, rx_chinfo, ctype);
++ mlb150_dev_init_ch_amba_ahb(pdevinfo, tx_chinfo, ctype);
++}
++
++static void mlb150_dev_exit(void)
++{
++ u32 c0_val, hctl_val;
++
++ /* Disable EN bits */
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~(MLBC0_MLBEN | MLBC0_MLBPEN);
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ hctl_val = __raw_readl(mlb_base + REG_HCTL);
++ hctl_val &= ~HCTL_EN;
++ __raw_writel(hctl_val, mlb_base + REG_HCTL);
++
++ __raw_writel(0x0, mlb_base + REG_HCMR0);
++ __raw_writel(0x0, mlb_base + REG_HCMR1);
++
++ mlb150_dev_enable_dma_irq(0);
++ mlb150_dev_enable_ir_mlb(0);
++}
++
++static void mlb150_dev_init(void)
++{
++ u32 c0_val;
++ u32 ch_rx_mask = (1 << SYNC_RX_CL_AHB0) | (1 << CTRL_RX_CL_AHB0)
++ | (1 << ASYNC_RX_CL_AHB0) | (1 << ISOC_RX_CL_AHB0)
++ | (1 << SYNC_TX_CL_AHB0) | (1 << CTRL_TX_CL_AHB0)
++ | (1 << ASYNC_TX_CL_AHB0) | (1 << ISOC_TX_CL_AHB0);
++ u32 ch_tx_mask = (1 << (SYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_RX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (SYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (CTRL_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ASYNC_TX_CL_AHB1 - INT_AHB1_CH_START)) |
++ (1 << (ISOC_TX_CL_AHB1 - INT_AHB1_CH_START));
++
++ /* Disable EN bits */
++ mlb150_dev_exit();
++
++ /*
++ * Step 1. Initialize CTR and registers
++ * a. Set all bit of the CTR (CAT, CDT, and ADT) to 0.
++ */
++ mlb150_dev_reset_whole_ctr();
++
++ /* a. Set all bit of the CTR (CAT, CDT, and ADT) to 0. */
++ mlb150_dev_reset_all_regs();
++
++ /*
++ * Step 2, Configure the MediaLB interface
++ * Select pin mode and clock, 3-pin and 256fs
++ */
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~(MLBC0_MLBPEN | MLBC0_MLBCLK_MASK);
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ c0_val |= MLBC0_MLBEN;
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ /* Step 3, Configure the HBI interface */
++ __raw_writel(ch_rx_mask, mlb_base + REG_HCMR0);
++ __raw_writel(ch_tx_mask, mlb_base + REG_HCMR1);
++ __raw_writel(HCTL_EN, mlb_base + REG_HCTL);
++
++ mlb150_dev_init_ir_amba_ahb();
++
++ mlb150_dev_enable_ir_mlb(1);
++}
++
++static s32 mlb150_dev_unmute_syn_ch(u32 rx_ch, u32 rx_cl, u32 tx_ch, u32 tx_cl)
++{
++ u32 timeout = 10000;
++
++ /*
++ * Check that MediaLB clock is running (MLBC1.CLKM = 0)
++ * If MLBC1.CLKM = 1, clear the register bit, wait one
++ * APB or I/O clock cycle and repeat the check
++ */
++ while ((__raw_readl(mlb_base + REG_MLBC1) & MLBC1_CLKM)
++ && --timeout)
++ __raw_writel(~MLBC1_CLKM, mlb_base + REG_MLBC1);
++
++ if (0 == timeout)
++ return -ETIME;
++
++ timeout = 10000;
++ /* Poll for MLB lock (MLBC0.MLBLK = 1) */
++ while (!(__raw_readl(mlb_base + REG_MLBC0) & MLBC0_MLBLK)
++ && --timeout)
++ ;
++
++ if (0 == timeout)
++ return -ETIME;
++
++ /* Unmute synchronous channel(s) */
++ mlb150_dev_cat_mlb_write(rx_ch, CAT_CE | rx_cl);
++ mlb150_dev_cat_mlb_write(tx_ch,
++ CAT_CE | tx_cl | CAT_RNW);
++ mlb150_dev_cat_hbi_write(rx_cl,
++ CAT_CE | rx_cl | CAT_RNW);
++ mlb150_dev_cat_hbi_write(tx_cl, CAT_CE | tx_cl);
++
++ return 0;
++}
++
++/* In case the user calls channel shutdown, but rx or tx is not completed yet */
++static s32 mlb150_trans_complete_check(struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ s32 timeout = 1024;
++
++ while (timeout--) {
++ read_lock(&tx_rbuf->rb_lock);
++ if (!CIRC_CNT(tx_rbuf->head, tx_rbuf->tail, TRANS_RING_NODES)) {
++ read_unlock(&tx_rbuf->rb_lock);
++ break;
++ } else
++ read_unlock(&tx_rbuf->rb_lock);
++ }
++
++ if (timeout <= 0) {
++ pr_debug("TX complete check timeout!\n");
++ return -ETIME;
++ }
++
++ timeout = 1024;
++ while (timeout--) {
++ read_lock(&rx_rbuf->rb_lock);
++ if (!CIRC_CNT(rx_rbuf->head, rx_rbuf->tail, TRANS_RING_NODES)) {
++ read_unlock(&rx_rbuf->rb_lock);
++ break;
++ } else
++ read_unlock(&rx_rbuf->rb_lock);
++ }
++
++ if (timeout <= 0) {
++ pr_debug("RX complete check timeout!\n");
++ return -ETIME;
++ }
++
++ /*
++ * Interrupt from TX can only inform that the data is sent
++ * to AHB bus, not mean that it is sent to MITB. Thus we add
++ * a delay here for data to be completed sent.
++ */
++ udelay(1000);
++
++ return 0;
++}
++
++/*
++ * Enable/Disable the MLB IRQ
++ */
++static void mxc_mlb150_irq_enable(struct mlb_data *drvdata, u8 enable)
++{
++ if (enable) {
++ enable_irq(drvdata->irq_ahb0);
++ enable_irq(drvdata->irq_ahb1);
++ enable_irq(drvdata->irq_mlb);
++ } else {
++ disable_irq(drvdata->irq_ahb0);
++ disable_irq(drvdata->irq_ahb1);
++ disable_irq(drvdata->irq_mlb);
++ }
++}
++
++/*
++ * Enable the MLB channel
++ */
++static s32 mlb_channel_enable(struct mlb_data *drvdata,
++ int chan_dev_id, int on)
++{
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_channel_info *tx_chinfo = &pdevinfo->channels[TX_CHANNEL];
++ struct mlb_channel_info *rx_chinfo = &pdevinfo->channels[RX_CHANNEL];
++ u32 tx_ch = tx_chinfo->address;
++ u32 rx_ch = rx_chinfo->address;
++ u32 tx_cl = tx_chinfo->cl;
++ u32 rx_cl = rx_chinfo->cl;
++ s32 ret = 0;
++
++ /*
++ * setup the direction, enable, channel type,
++ * mode select, channel address and mask buf start
++ */
++ if (on) {
++ u32 ctype = pdevinfo->channel_type;
++
++ mlb150_dev_enable_ctr_write(0xffffffff, 0xffffffff,
++ 0xffffffff, 0xffffffff);
++ mlb150_dev_init_rfb(pdevinfo, rx_ch, tx_ch, ctype);
++
++ mlb150_dev_init_amba_ahb(pdevinfo, ctype);
++
++#ifdef DEBUG
++ mlb150_dev_dump_ctr_tbl(0, tx_chinfo->cl + 1);
++#endif
++ /* Synchronize and unmute synchrouous channel */
++ if (MLB_CTYPE_SYNC == ctype) {
++ ret = mlb150_dev_unmute_syn_ch(rx_ch, rx_cl,
++ tx_ch, tx_cl);
++ if (ret)
++ return ret;
++ }
++
++ mlb150_dev_enable_ctr_write(0x0, ADT_RDY1 | ADT_DNE1 |
++ ADT_ERR1 | ADT_PS1 |
++ ADT_RDY2 | ADT_DNE2 | ADT_ERR2 | ADT_PS2,
++ 0xffffffff, 0xffffffff);
++
++ if (pdevinfo->fps >= CLK_2048FS)
++ mlb150_enable_pll(drvdata);
++
++ atomic_set(&pdevinfo->on, 1);
++
++#ifdef DEBUG
++ mlb150_dev_dump_reg();
++ mlb150_dev_dump_ctr_tbl(0, tx_chinfo->cl + 1);
++#endif
++ /* Init RX ADT */
++ mlb150_dev_pipo_start(&pdevinfo->rx_rbuf, rx_cl,
++ pdevinfo->rx_rbuf.phy_addrs[0]);
++ } else {
++ mlb150_dev_pipo_stop(&pdevinfo->rx_rbuf, rx_cl);
++
++ mlb150_dev_enable_dma_irq(0);
++ mlb150_dev_enable_ir_mlb(0);
++
++ mlb150_dev_reset_cat();
++
++ atomic_set(&pdevinfo->on, 0);
++
++ if (pdevinfo->fps >= CLK_2048FS)
++ mlb150_disable_pll(drvdata);
++ }
++
++ return 0;
++}
++
++/*
++ * MLB interrupt handler
++ */
++static void mlb_rx_isr(s32 ctype, u32 ahb_ch, struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ s32 head, tail, adt_sts;
++ u32 rx_buf_ptr;
++
++#ifdef DEBUG_RX
++ pr_debug("mxc_mlb150: mlb_rx_isr\n");
++#endif
++
++ read_lock(&rx_rbuf->rb_lock);
++
++ head = (rx_rbuf->head + 1) & (TRANS_RING_NODES - 1);
++ tail = ACCESS_ONCE(rx_rbuf->tail);
++ read_unlock(&rx_rbuf->rb_lock);
++
++ if (CIRC_SPACE(head, tail, TRANS_RING_NODES) >= 1) {
++ rx_buf_ptr = rx_rbuf->phy_addrs[head];
++
++ /* commit the item before incrementing the head */
++ smp_wmb();
++
++ write_lock(&rx_rbuf->rb_lock);
++ rx_rbuf->head = head;
++ write_unlock(&rx_rbuf->rb_lock);
++
++ /* wake up the reader */
++ wake_up_interruptible(&pdevinfo->rx_wq);
++ } else {
++ rx_buf_ptr = rx_rbuf->phy_addrs[head];
++ pr_debug("drop RX package, due to no space, (%d,%d)\n",
++ head, tail);
++ }
++
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++ /* Set ADT for RX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, rx_buf_ptr);
++}
++
++static void mlb_tx_isr(s32 ctype, u32 ahb_ch, struct mlb_dev_info *pdevinfo)
++{
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ s32 head, tail, adt_sts;
++ u32 tx_buf_ptr;
++
++ read_lock(&tx_rbuf->rb_lock);
++
++ head = ACCESS_ONCE(tx_rbuf->head);
++ tail = (tx_rbuf->tail + 1) & (TRANS_RING_NODES - 1);
++ read_unlock(&tx_rbuf->rb_lock);
++
++ smp_mb();
++ write_lock(&tx_rbuf->rb_lock);
++ tx_rbuf->tail = tail;
++ write_unlock(&tx_rbuf->rb_lock);
++
++ /* check the current tx buffer is available or not */
++ if (CIRC_CNT(head, tail, TRANS_RING_NODES) >= 1) {
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ tx_buf_ptr = tx_rbuf->phy_addrs[tail];
++
++ wake_up_interruptible(&pdevinfo->tx_wq);
++
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++ /* Set ADT for TX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, tx_buf_ptr);
++ }
++}
++
++static irqreturn_t mlb_ahb_isr(int irq, void *dev_id)
++{
++ u32 acsr0, hcer0;
++ u32 ch_mask = (1 << SYNC_RX_CL) | (1 << CTRL_RX_CL)
++ | (1 << ASYNC_RX_CL) | (1 << ISOC_RX_CL)
++ | (1 << SYNC_TX_CL) | (1 << CTRL_TX_CL)
++ | (1 << ASYNC_TX_CL) | (1 << ISOC_TX_CL);
++
++ /*
++ * Step 5, Read the ACSRn registers to determine which channel or
++ * channels are causing the interrupt
++ */
++ acsr0 = __raw_readl(mlb_base + REG_ACSR0);
++
++ hcer0 = __raw_readl(mlb_base + REG_HCER0);
++
++ /*
++ * Step 6, If ACTL.SCE = 1, write the result of step 5 back to ACSR0
++ * and ACSR1 to clear the interrupt
++ * We'll not set ACTL_SCE
++ */
++
++ if (ch_mask & hcer0)
++ pr_err("CH encounters an AHB error: 0x%x\n", hcer0);
++
++ if ((1 << SYNC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_SYNC, SYNC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_SYNC]);
++
++ if ((1 << CTRL_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_CTRL, CTRL_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_CTRL]);
++
++ if ((1 << ASYNC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_ASYNC, ASYNC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_ASYNC]);
++
++ if ((1 << ISOC_RX_CL) & acsr0)
++ mlb_rx_isr(MLB_CTYPE_ISOC, ISOC_RX_CL,
++ &mlb_devinfo[MLB_CTYPE_ISOC]);
++
++ if ((1 << SYNC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_SYNC, SYNC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_SYNC]);
++
++ if ((1 << CTRL_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_CTRL, CTRL_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_CTRL]);
++
++ if ((1 << ASYNC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_ASYNC, ASYNC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_ASYNC]);
++
++ if ((1 << ISOC_TX_CL) & acsr0)
++ mlb_tx_isr(MLB_CTYPE_ASYNC, ISOC_TX_CL,
++ &mlb_devinfo[MLB_CTYPE_ISOC]);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mlb_isr(int irq, void *dev_id)
++{
++ u32 rx_int_sts, tx_int_sts, ms0,
++ ms1, tx_cis, rx_cis, ctype;
++ int minor;
++ u32 cdt_val[4] = { 0 };
++
++ /*
++ * Step 4, Read the MSn register to determine which channel(s)
++ * are causing the interrupt
++ */
++ ms0 = __raw_readl(mlb_base + REG_MS0);
++ ms1 = __raw_readl(mlb_base + REG_MS1);
++
++ /*
++ * The MLB150_MS0, MLB150_MS1 registers need to be cleared. In
++ * the spec description, the registers should be cleared when
++ * enabling interrupt. In fact, we also should clear it in ISR.
++ */
++ __raw_writel(0, mlb_base + REG_MS0);
++ __raw_writel(0, mlb_base + REG_MS1);
++
++ pr_debug("mxc_mlb150: mlb interrupt:0x%08x 0x%08x\n",
++ (u32)ms0, (u32)ms1);
++
++ for (minor = 0; minor < MLB_MINOR_DEVICES; minor++) {
++ struct mlb_dev_info *pdevinfo = &mlb_devinfo[minor];
++ u32 rx_mlb_ch = pdevinfo->channels[RX_CHANNEL].address;
++ u32 tx_mlb_ch = pdevinfo->channels[TX_CHANNEL].address;
++ u32 rx_mlb_cl = pdevinfo->channels[RX_CHANNEL].cl;
++ u32 tx_mlb_cl = pdevinfo->channels[TX_CHANNEL].cl;
++
++ tx_cis = rx_cis = 0;
++
++ ctype = pdevinfo->channel_type;
++ rx_int_sts = (rx_mlb_ch < 31) ? ms0 : ms1;
++ tx_int_sts = (tx_mlb_ch < 31) ? ms0 : ms1;
++
++ pr_debug("mxc_mlb150: channel interrupt: "
++ "tx %d: 0x%08x, rx %d: 0x%08x\n",
++ tx_mlb_ch, (u32)tx_int_sts, rx_mlb_ch, (u32)rx_int_sts);
++
++ /* Get tx channel interrupt status */
++ if (tx_int_sts & (1 << (tx_mlb_ch % 32))) {
++ mlb150_dev_cdt_read(tx_mlb_cl, cdt_val);
++ pr_debug("mxc_mlb150: TX_CH: %d, cdt_val[3]: 0x%08x, "
++ "cdt_val[2]: 0x%08x, "
++ "cdt_val[1]: 0x%08x, "
++ "cdt_val[0]: 0x%08x\n",
++ tx_mlb_ch, cdt_val[3], cdt_val[2],
++ cdt_val[1], cdt_val[0]);
++ switch (ctype) {
++ case MLB_CTYPE_SYNC:
++ tx_cis = (cdt_val[2] & ~CDT_SYNC_WSTS_MASK)
++ >> CDT_SYNC_WSTS_SHIFT;
++ /*
++ * Clear RSTS/WSTS errors to resume
++ * channel operation
++ * a. For synchronous channels: WSTS[3] = 0
++ */
++ cdt_val[2] &= ~(0x8 << CDT_SYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_CTRL:
++ case MLB_CTYPE_ASYNC:
++ tx_cis = (cdt_val[2] &
++ ~CDT_CTRL_ASYNC_WSTS_MASK)
++ >> CDT_CTRL_ASYNC_WSTS_SHIFT;
++ tx_cis = (cdt_val[3] & CDT_CTRL_ASYNC_WSTS_1) ?
++ (tx_cis | (0x1 << 4)) : tx_cis;
++ /*
++ * b. For async and ctrl channels:
++ * RSTS[4]/WSTS[4] = 0
++ * and RSTS[2]/WSTS[2] = 0
++ */
++ cdt_val[3] &= ~CDT_CTRL_ASYNC_WSTS_1;
++ cdt_val[2] &=
++ ~(0x4 << CDT_CTRL_ASYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_ISOC:
++ tx_cis = (cdt_val[2] & ~CDT_ISOC_WSTS_MASK)
++ >> CDT_ISOC_WSTS_SHIFT;
++ /* c. For isoc channels: WSTS[2:1] = 0x00 */
++ cdt_val[2] &= ~(0x6 << CDT_ISOC_WSTS_SHIFT);
++ break;
++ default:
++ break;
++ }
++ mlb150_dev_cdt_write(tx_mlb_ch, cdt_val);
++ }
++
++ /* Get rx channel interrupt status */
++ if (rx_int_sts & (1 << (rx_mlb_ch % 32))) {
++ mlb150_dev_cdt_read(rx_mlb_cl, cdt_val);
++ pr_debug("mxc_mlb150: RX_CH: %d, cdt_val[3]: 0x%08x, "
++ "cdt_val[2]: 0x%08x, "
++ "cdt_val[1]: 0x%08x, "
++ "cdt_val[0]: 0x%08x\n",
++ rx_mlb_ch, cdt_val[3], cdt_val[2],
++ cdt_val[1], cdt_val[0]);
++ switch (ctype) {
++ case MLB_CTYPE_SYNC:
++ tx_cis = (cdt_val[2] & ~CDT_SYNC_RSTS_MASK)
++ >> CDT_SYNC_RSTS_SHIFT;
++ cdt_val[2] &= ~(0x8 << CDT_SYNC_WSTS_SHIFT);
++ break;
++ case MLB_CTYPE_CTRL:
++ case MLB_CTYPE_ASYNC:
++ tx_cis =
++ (cdt_val[2] & ~CDT_CTRL_ASYNC_RSTS_MASK)
++ >> CDT_CTRL_ASYNC_RSTS_SHIFT;
++ tx_cis = (cdt_val[3] & CDT_CTRL_ASYNC_RSTS_1) ?
++ (tx_cis | (0x1 << 4)) : tx_cis;
++ cdt_val[3] &= ~CDT_CTRL_ASYNC_RSTS_1;
++ cdt_val[2] &=
++ ~(0x4 << CDT_CTRL_ASYNC_RSTS_SHIFT);
++ break;
++ case MLB_CTYPE_ISOC:
++ tx_cis = (cdt_val[2] & ~CDT_ISOC_RSTS_MASK)
++ >> CDT_ISOC_RSTS_SHIFT;
++ cdt_val[2] &= ~(0x6 << CDT_ISOC_WSTS_SHIFT);
++ break;
++ default:
++ break;
++ }
++ mlb150_dev_cdt_write(rx_mlb_ch, cdt_val);
++ }
++
++ if (!tx_cis && !rx_cis)
++ continue;
++
++ /* fill exception event */
++ spin_lock(&pdevinfo->event_lock);
++ pdevinfo->ex_event |= (rx_cis << 16) | tx_cis;
++ spin_unlock(&pdevinfo->event_lock);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int mxc_mlb150_open(struct inode *inode, struct file *filp)
++{
++ int minor, ring_buf_size, buf_size, j, ret;
++ void __iomem *buf_addr;
++ ulong phy_addr;
++ struct mlb_dev_info *pdevinfo = NULL;
++ struct mlb_channel_info *pchinfo = NULL;
++ struct mlb_data *drvdata;
++
++ minor = MINOR(inode->i_rdev);
++ drvdata = container_of(inode->i_cdev, struct mlb_data, cdev);
++
++ if (minor < 0 || minor >= MLB_MINOR_DEVICES) {
++ pr_err("no device\n");
++ return -ENODEV;
++ }
++
++ /* open for each channel device */
++ if (atomic_cmpxchg(&mlb_devinfo[minor].opencnt, 0, 1) != 0) {
++ pr_err("busy\n");
++ return -EBUSY;
++ }
++
++ clk_prepare_enable(drvdata->clk_mlb3p);
++
++ /* initial MLB module */
++ mlb150_dev_init();
++
++ pdevinfo = &mlb_devinfo[minor];
++ pchinfo = &pdevinfo->channels[TX_CHANNEL];
++
++ ring_buf_size = pdevinfo->buf_size;
++ buf_size = ring_buf_size * (TRANS_RING_NODES * 2);
++ buf_addr = (void __iomem *)gen_pool_alloc(drvdata->iram_pool, buf_size);
++ if (buf_addr == NULL) {
++ ret = -ENOMEM;
++ pr_err("can not alloc rx/tx buffers: %d\n", buf_size);
++ return ret;
++ }
++ phy_addr = gen_pool_virt_to_phys(drvdata->iram_pool, (ulong)buf_addr);
++ pr_debug("IRAM Range: Virt 0x%p - 0x%p, Phys 0x%x - 0x%x, size: 0x%x\n",
++ buf_addr, (buf_addr + buf_size - 1), (u32)phy_addr,
++ (u32)(phy_addr + buf_size - 1), buf_size);
++ pdevinfo->rbuf_base_virt = buf_addr;
++ pdevinfo->rbuf_base_phy = phy_addr;
++ drvdata->iram_size = buf_size;
++
++ memset(buf_addr, 0, buf_size);
++
++ for (j = 0; j < (TRANS_RING_NODES);
++ ++j, buf_addr += ring_buf_size, phy_addr += ring_buf_size) {
++ pdevinfo->rx_rbuf.virt_bufs[j] = buf_addr;
++ pdevinfo->rx_rbuf.phy_addrs[j] = phy_addr;
++ pr_debug("RX Ringbuf[%d]: 0x%p 0x%x\n",
++ j, buf_addr, (u32)phy_addr);
++ }
++ pdevinfo->rx_rbuf.unit_size = ring_buf_size;
++ pdevinfo->rx_rbuf.total_size = buf_size;
++ for (j = 0; j < (TRANS_RING_NODES);
++ ++j, buf_addr += ring_buf_size, phy_addr += ring_buf_size) {
++ pdevinfo->tx_rbuf.virt_bufs[j] = buf_addr;
++ pdevinfo->tx_rbuf.phy_addrs[j] = phy_addr;
++ pr_debug("TX Ringbuf[%d]: 0x%p 0x%x\n",
++ j, buf_addr, (u32)phy_addr);
++ }
++
++ pdevinfo->tx_rbuf.unit_size = ring_buf_size;
++ pdevinfo->tx_rbuf.total_size = buf_size;
++
++ /* reset the buffer read/write ptr */
++ pdevinfo->rx_rbuf.head = pdevinfo->rx_rbuf.tail = 0;
++ pdevinfo->tx_rbuf.head = pdevinfo->tx_rbuf.tail = 0;
++ pdevinfo->ex_event = 0;
++ pdevinfo->tx_ok = 0;
++
++ init_waitqueue_head(&pdevinfo->rx_wq);
++ init_waitqueue_head(&pdevinfo->tx_wq);
++
++ drvdata = container_of(inode->i_cdev, struct mlb_data, cdev);
++ drvdata->devinfo = pdevinfo;
++ mxc_mlb150_irq_enable(drvdata, 1);
++ filp->private_data = drvdata;
++
++ return 0;
++}
++
++static int mxc_mlb150_release(struct inode *inode, struct file *filp)
++{
++ int minor;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ minor = MINOR(inode->i_rdev);
++ mxc_mlb150_irq_enable(drvdata, 0);
++
++#ifdef DEBUG
++ mlb150_dev_dump_reg();
++ mlb150_dev_dump_ctr_tbl(0, pdevinfo->channels[TX_CHANNEL].cl + 1);
++#endif
++
++ gen_pool_free(drvdata->iram_pool,
++ (ulong)pdevinfo->rbuf_base_virt, drvdata->iram_size);
++
++ mlb150_dev_exit();
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ atomic_set(&pdevinfo->on, 0);
++
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++ /* decrease the open count */
++ atomic_set(&pdevinfo->opencnt, 0);
++
++ drvdata->devinfo = NULL;
++
++ return 0;
++}
++
++static long mxc_mlb150_ioctl(struct file *filp,
++ unsigned int cmd, unsigned long arg)
++{
++ struct inode *inode = filp->f_dentry->d_inode;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ void __user *argp = (void __user *)arg;
++ unsigned long flags, event;
++ int minor;
++
++ minor = MINOR(inode->i_rdev);
++
++ switch (cmd) {
++ case MLB_CHAN_SETADDR:
++ {
++ unsigned int caddr;
++ /* get channel address from user space */
++ if (copy_from_user(&caddr, argp, sizeof(caddr))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++ pdevinfo->channels[TX_CHANNEL].address =
++ (caddr >> 16) & 0xFFFF;
++ pdevinfo->channels[RX_CHANNEL].address = caddr & 0xFFFF;
++ pr_debug("mxc_mlb150: set ch addr, tx: %d, rx: %d\n",
++ pdevinfo->channels[TX_CHANNEL].address,
++ pdevinfo->channels[RX_CHANNEL].address);
++ break;
++ }
++
++ case MLB_CHAN_STARTUP:
++ if (atomic_read(&pdevinfo->on)) {
++ pr_debug("mxc_mlb150: channel alreadly startup\n");
++ break;
++ }
++ if (mlb_channel_enable(drvdata, minor, 1))
++ return -EFAULT;
++ break;
++ case MLB_CHAN_SHUTDOWN:
++ if (atomic_read(&pdevinfo->on) == 0) {
++ pr_debug("mxc_mlb150: channel areadly shutdown\n");
++ break;
++ }
++ mlb150_trans_complete_check(pdevinfo);
++ mlb_channel_enable(drvdata, minor, 0);
++ break;
++ case MLB_CHAN_GETEVENT:
++ /* get and clear the ex_event */
++ spin_lock_irqsave(&pdevinfo->event_lock, flags);
++ event = pdevinfo->ex_event;
++ pdevinfo->ex_event = 0;
++ spin_unlock_irqrestore(&pdevinfo->event_lock, flags);
++
++ if (event) {
++ if (copy_to_user(argp, &event, sizeof(event))) {
++ pr_err("mxc_mlb150: copy to user failed\n");
++ return -EFAULT;
++ }
++ } else
++ return -EAGAIN;
++ break;
++ case MLB_SET_ISOC_BLKSIZE_188:
++ pdevinfo->isoc_blksz = 188;
++ pdevinfo->cdt_buf_dep = pdevinfo->adt_buf_dep =
++ pdevinfo->isoc_blksz * CH_ISOC_BLK_NUM;
++ break;
++ case MLB_SET_ISOC_BLKSIZE_196:
++ pdevinfo->isoc_blksz = 196;
++ pdevinfo->cdt_buf_dep = pdevinfo->adt_buf_dep =
++ pdevinfo->isoc_blksz * CH_ISOC_BLK_NUM;
++ break;
++ case MLB_SET_SYNC_QUAD:
++ {
++ u32 quad;
++
++ if (copy_from_user(&quad, argp, sizeof(quad))) {
++ pr_err("mxc_mlb150: get quad number "
++ "from user failed\n");
++ return -EFAULT;
++ }
++ if (quad <= 0 || quad > 3) {
++ pr_err("mxc_mlb150: Invalid Quadlets!"
++ "Quadlets in Sync mode can "
++ "only be 1, 2, 3\n");
++ return -EINVAL;
++ }
++ pdevinfo->sync_quad = quad;
++ /* Each quadlets is 4 bytes */
++ pdevinfo->cdt_buf_dep = quad * 4 * 4;
++ pdevinfo->adt_buf_dep =
++ pdevinfo->cdt_buf_dep * CH_SYNC_ADT_BUF_MULTI;
++ }
++ break;
++ case MLB_SET_FPS:
++ {
++ u32 fps, c0_val;
++
++ /* get fps from user space */
++ if (copy_from_user(&fps, argp, sizeof(fps))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ if ((fps > 1024) &&
++ !(drvdata->quirk_flag & MLB_QUIRK_MLB150)) {
++ pr_err("mxc_mlb150: not support fps %d\n", fps);
++ return -EINVAL;
++ }
++
++ c0_val = __raw_readl(mlb_base + REG_MLBC0);
++ c0_val &= ~MLBC0_MLBCLK_MASK;
++
++ /* check fps value */
++ switch (fps) {
++ case 256:
++ case 512:
++ case 1024:
++ pdevinfo->fps = fps >> 9;
++ c0_val &= ~MLBC0_MLBPEN;
++ c0_val |= (fps >> 9)
++ << MLBC0_MLBCLK_SHIFT;
++
++ if (1024 == fps) {
++ /*
++ * Invert output clock phase
++ * in 1024 fps
++ */
++ __raw_writel(0x1,
++ mlb_base + REG_MLBPC2);
++ }
++ break;
++ case 2048:
++ case 3072:
++ case 4096:
++ pdevinfo->fps = (fps >> 10) + 1;
++ c0_val |= ((fps >> 10) + 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ case 6144:
++ pdevinfo->fps = fps >> 10;
++ c0_val |= ((fps >> 10) + 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ case 8192:
++ pdevinfo->fps = (fps >> 10) - 1;
++ c0_val |= ((fps >> 10) - 1)
++ << MLBC0_MLBCLK_SHIFT;
++ break;
++ default:
++ pr_debug("mxc_mlb150: invalid fps argument: %d\n",
++ fps);
++ return -EINVAL;
++ }
++
++ __raw_writel(c0_val, mlb_base + REG_MLBC0);
++
++ pr_debug("mxc_mlb150: set fps to %d, MLBC0: 0x%08x\n",
++ fps,
++ (u32)__raw_readl(mlb_base + REG_MLBC0));
++
++ break;
++ }
++
++ case MLB_GET_VER:
++ {
++ u32 version;
++
++ /* get MLB device module version */
++ version = 0x03030003;
++
++ pr_debug("mxc_mlb150: get version: 0x%08x\n",
++ version);
++
++ if (copy_to_user(argp, &version, sizeof(version))) {
++ pr_err("mxc_mlb150: copy to user failed\n");
++ return -EFAULT;
++ }
++ break;
++ }
++
++ case MLB_SET_DEVADDR:
++ {
++ u32 c1_val;
++ u8 devaddr;
++
++ /* get MLB device address from user space */
++ if (copy_from_user
++ (&devaddr, argp, sizeof(unsigned char))) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ c1_val = __raw_readl(mlb_base + REG_MLBC1);
++ c1_val &= ~MLBC1_NDA_MASK;
++ c1_val |= devaddr << MLBC1_NDA_SHIFT;
++ __raw_writel(c1_val, mlb_base + REG_MLBC1);
++ pr_debug("mxc_mlb150: set dev addr, dev addr: %d, "
++ "MLBC1: 0x%08x\n", devaddr,
++ (u32)__raw_readl(mlb_base + REG_MLBC1));
++
++ break;
++ }
++
++ case MLB_IRQ_DISABLE:
++ {
++ disable_irq(drvdata->irq_mlb);
++ break;
++ }
++
++ case MLB_IRQ_ENABLE:
++ {
++ enable_irq(drvdata->irq_mlb);
++ break;
++ }
++ default:
++ pr_info("mxc_mlb150: Invalid ioctl command\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/*
++ * MLB read routine
++ * Read the current received data from queued buffer,
++ * and free this buffer for hw to fill ingress data.
++ */
++static ssize_t mxc_mlb150_read(struct file *filp, char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ int size;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++
++ head = ACCESS_ONCE(rx_rbuf->head);
++ tail = rx_rbuf->tail;
++
++ read_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ /* check the current rx buffer is available or not */
++ if (0 == CIRC_CNT(head, tail, TRANS_RING_NODES)) {
++
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++
++ do {
++ DEFINE_WAIT(__wait);
++
++ for (;;) {
++ prepare_to_wait(&pdevinfo->rx_wq,
++ &__wait, TASK_INTERRUPTIBLE);
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ if (CIRC_CNT(rx_rbuf->head, rx_rbuf->tail,
++ TRANS_RING_NODES) > 0) {
++ read_unlock_irqrestore(&rx_rbuf->rb_lock,
++ flags);
++ break;
++ }
++ read_unlock_irqrestore(&rx_rbuf->rb_lock,
++ flags);
++
++ if (!signal_pending(current)) {
++ schedule();
++ continue;
++ }
++ return -ERESTARTSYS;
++ }
++ finish_wait(&pdevinfo->rx_wq, &__wait);
++ } while (0);
++ }
++
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ size = pdevinfo->adt_buf_dep;
++ if (size > count) {
++ /* the user buffer is too small */
++ pr_warning
++ ("mxc_mlb150: received data size is bigger than "
++ "size: %d, count: %d\n", size, count);
++ return -EINVAL;
++ }
++
++ /* extract one item from the buffer */
++ if (copy_to_user(buf, rx_rbuf->virt_bufs[tail], size)) {
++ pr_err("mxc_mlb150: copy from user failed\n");
++ return -EFAULT;
++ }
++
++ /* finish reading descriptor before incrementing tail */
++ smp_mb();
++
++ write_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ rx_rbuf->tail = (tail + 1) & (TRANS_RING_NODES - 1);
++ write_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ *f_pos = 0;
++
++ return size;
++}
++
++/*
++ * MLB write routine
++ * Copy the user data to tx channel buffer,
++ * and prepare the channel current/next buffer ptr.
++ */
++static ssize_t mxc_mlb150_write(struct file *filp, const char __user *buf,
++ size_t count, loff_t *f_pos)
++{
++ s32 ret = 0;
++ struct mlb_channel_info *pchinfo = NULL;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++ /*
++ * minor = MINOR(filp->f_dentry->d_inode->i_rdev);
++ */
++ pchinfo = &pdevinfo->channels[TX_CHANNEL];
++
++ if (count > pdevinfo->buf_size) {
++ /* too many data to write */
++ pr_warning("mxc_mlb150: overflow write data\n");
++ return -EFBIG;
++ }
++
++ *f_pos = 0;
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++
++ head = tx_rbuf->head;
++ tail = ACCESS_ONCE(tx_rbuf->tail);
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ if (0 == CIRC_SPACE(head, tail, TRANS_RING_NODES)) {
++ if (filp->f_flags & O_NONBLOCK)
++ return -EAGAIN;
++ do {
++ DEFINE_WAIT(__wait);
++
++ for (;;) {
++ prepare_to_wait(&pdevinfo->tx_wq,
++ &__wait, TASK_INTERRUPTIBLE);
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ if (CIRC_SPACE(tx_rbuf->head, tx_rbuf->tail,
++ TRANS_RING_NODES) > 0) {
++ read_unlock_irqrestore(&tx_rbuf->rb_lock,
++ flags);
++ break;
++ }
++ read_unlock_irqrestore(&tx_rbuf->rb_lock,
++ flags);
++
++ if (!signal_pending(current)) {
++ schedule();
++ continue;
++ }
++ return -ERESTARTSYS;
++ }
++ finish_wait(&pdevinfo->tx_wq, &__wait);
++ } while (0);
++ }
++
++ if (copy_from_user((void *)tx_rbuf->virt_bufs[head], buf, count)) {
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++ pr_err("mxc_mlb: copy from user failed\n");
++ ret = -EFAULT;
++ goto out;
++ }
++
++ write_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ smp_wmb();
++ tx_rbuf->head = (head + 1) & (TRANS_RING_NODES - 1);
++ write_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ if (0 == CIRC_CNT(head, tail, TRANS_RING_NODES)) {
++ u32 tx_buf_ptr, ahb_ch;
++ s32 adt_sts;
++ u32 ctype = pdevinfo->channel_type;
++
++ /* read index before reading contents at that index */
++ smp_read_barrier_depends();
++
++ tx_buf_ptr = tx_rbuf->phy_addrs[tail];
++
++ ahb_ch = pdevinfo->channels[TX_CHANNEL].cl;
++ adt_sts = mlb150_dev_get_adt_sts(ahb_ch);
++
++ /* Set ADT for TX */
++ mlb150_dev_pipo_next(ahb_ch, ctype, adt_sts, tx_buf_ptr);
++ }
++
++ ret = count;
++out:
++ return ret;
++}
++
++static unsigned int mxc_mlb150_poll(struct file *filp,
++ struct poll_table_struct *wait)
++{
++ int minor;
++ unsigned int ret = 0;
++ struct mlb_data *drvdata = filp->private_data;
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++ struct mlb_ringbuf *tx_rbuf = &pdevinfo->tx_rbuf;
++ struct mlb_ringbuf *rx_rbuf = &pdevinfo->rx_rbuf;
++ int head, tail;
++ unsigned long flags;
++
++
++ minor = MINOR(filp->f_dentry->d_inode->i_rdev);
++
++ poll_wait(filp, &pdevinfo->rx_wq, wait);
++ poll_wait(filp, &pdevinfo->tx_wq, wait);
++
++ read_lock_irqsave(&tx_rbuf->rb_lock, flags);
++ head = tx_rbuf->head;
++ tail = tx_rbuf->tail;
++ read_unlock_irqrestore(&tx_rbuf->rb_lock, flags);
++
++ /* check the tx buffer is avaiable or not */
++ if (CIRC_SPACE(head, tail, TRANS_RING_NODES) >= 1)
++ ret |= POLLOUT | POLLWRNORM;
++
++ read_lock_irqsave(&rx_rbuf->rb_lock, flags);
++ head = rx_rbuf->head;
++ tail = rx_rbuf->tail;
++ read_unlock_irqrestore(&rx_rbuf->rb_lock, flags);
++
++ /* check the rx buffer filled or not */
++ if (CIRC_CNT(head, tail, TRANS_RING_NODES) >= 1)
++ ret |= POLLIN | POLLRDNORM;
++
++
++ /* check the exception event */
++ if (pdevinfo->ex_event)
++ ret |= POLLIN | POLLRDNORM;
++
++ return ret;
++}
++
++/*
++ * char dev file operations structure
++ */
++static const struct file_operations mxc_mlb150_fops = {
++
++ .owner = THIS_MODULE,
++ .open = mxc_mlb150_open,
++ .release = mxc_mlb150_release,
++ .unlocked_ioctl = mxc_mlb150_ioctl,
++ .poll = mxc_mlb150_poll,
++ .read = mxc_mlb150_read,
++ .write = mxc_mlb150_write,
++};
++
++static struct platform_device_id imx_mlb150_devtype[] = {
++ {
++ .name = "imx6q-mlb150",
++ .driver_data = MLB_QUIRK_MLB150,
++ }, {
++ .name = "imx6sx-mlb50",
++ .driver_data = 0,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_mlb150_devtype);
++
++static const struct of_device_id mlb150_imx_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mlb150",
++ .data = &imx_mlb150_devtype[IMX6Q_MLB], },
++ { .compatible = "fsl,imx6sx-mlb50",
++ .data = &imx_mlb150_devtype[IMX6SX_MLB], },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, mlb150_imx_dt_ids);
++
++/*
++ * This function is called whenever the MLB device is detected.
++ */
++static int mxc_mlb150_probe(struct platform_device *pdev)
++{
++ int ret, mlb_major, i;
++ struct mlb_data *drvdata;
++ struct resource *res;
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *of_id;
++
++ drvdata = devm_kzalloc(&pdev->dev, sizeof(struct mlb_data),
++ GFP_KERNEL);
++ if (!drvdata) {
++ dev_err(&pdev->dev, "can't allocate enough memory\n");
++ return -ENOMEM;
++ }
++
++ of_id = of_match_device(mlb150_imx_dt_ids, &pdev->dev);
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ else
++ return -EINVAL;
++ /*
++ * Register MLB lld as four character devices
++ */
++ ret = alloc_chrdev_region(&drvdata->firstdev, 0,
++ MLB_MINOR_DEVICES, "mxc_mlb150");
++ if (ret < 0) {
++ dev_err(&pdev->dev, "alloc region error\n");
++ goto err_reg;
++ }
++ mlb_major = MAJOR(drvdata->firstdev);
++ dev_dbg(&pdev->dev, "MLB device major: %d\n", mlb_major);
++
++ cdev_init(&drvdata->cdev, &mxc_mlb150_fops);
++ drvdata->cdev.owner = THIS_MODULE;
++
++ ret = cdev_add(&drvdata->cdev, drvdata->firstdev, MLB_MINOR_DEVICES);
++ if (ret) {
++ dev_err(&pdev->dev, "can't add cdev\n");
++ goto err_reg;
++ }
++
++ /* create class and device for udev information */
++ drvdata->class = class_create(THIS_MODULE, "mlb150");
++ if (IS_ERR(drvdata->class)) {
++ dev_err(&pdev->dev, "failed to create device class\n");
++ ret = -ENOMEM;
++ goto err_class;
++ }
++
++ for (i = 0; i < MLB_MINOR_DEVICES; i++) {
++ struct device *class_dev;
++
++ class_dev = device_create(drvdata->class, NULL,
++ MKDEV(mlb_major, i),
++ NULL, mlb_devinfo[i].dev_name);
++ if (IS_ERR(class_dev)) {
++ dev_err(&pdev->dev, "failed to create mlb150 %s"
++ " class device\n", mlb_devinfo[i].dev_name);
++ ret = -ENOMEM;
++ goto err_dev;
++ }
++ }
++
++ drvdata->quirk_flag = pdev->id_entry->driver_data;
++
++ /* ahb0 irq */
++ drvdata->irq_ahb0 = platform_get_irq(pdev, 1);
++ if (drvdata->irq_ahb0 < 0) {
++ dev_err(&pdev->dev, "No ahb0 irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "ahb0_irq: %d\n", drvdata->irq_ahb0);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_ahb0, mlb_ahb_isr,
++ 0, "mlb_ahb0", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_ahb0);
++ goto err_dev;
++ }
++
++ /* ahb1 irq */
++ drvdata->irq_ahb1 = platform_get_irq(pdev, 2);
++ if (drvdata->irq_ahb1 < 0) {
++ dev_err(&pdev->dev, "No ahb1 irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "ahb1_irq: %d\n", drvdata->irq_ahb1);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_ahb1, mlb_ahb_isr,
++ 0, "mlb_ahb1", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_ahb1);
++ goto err_dev;
++ }
++
++ /* mlb irq */
++ drvdata->irq_mlb = platform_get_irq(pdev, 0);
++ if (drvdata->irq_mlb < 0) {
++ dev_err(&pdev->dev, "No mlb irq line provided\n");
++ goto err_dev;
++ }
++ dev_dbg(&pdev->dev, "mlb_irq: %d\n", drvdata->irq_mlb);
++ if (devm_request_irq(&pdev->dev, drvdata->irq_mlb, mlb_isr,
++ 0, "mlb", NULL)) {
++ dev_err(&pdev->dev, "can't claim irq %d\n", drvdata->irq_mlb);
++ goto err_dev;
++ }
++
++ /* ioremap from phy mlb to kernel space */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "can't get device resources\n");
++ ret = -ENOENT;
++ goto err_dev;
++ }
++ mlb_base = devm_request_and_ioremap(&pdev->dev, res);
++ dev_dbg(&pdev->dev, "mapped base address: 0x%08x\n", (u32)mlb_base);
++ if (IS_ERR(mlb_base)) {
++ dev_err(&pdev->dev,
++ "failed to get ioremap base\n");
++ ret = PTR_ERR(mlb_base);
++ goto err_dev;
++ }
++ drvdata->membase = mlb_base;
++
++ /* enable clock */
++ drvdata->clk_mlb3p = devm_clk_get(&pdev->dev, "mlb");
++ if (IS_ERR(drvdata->clk_mlb3p)) {
++ dev_err(&pdev->dev, "unable to get mlb clock\n");
++ ret = PTR_ERR(drvdata->clk_mlb3p);
++ goto err_dev;
++ }
++
++ if (drvdata->quirk_flag & MLB_QUIRK_MLB150) {
++ drvdata->clk_mlb6p = devm_clk_get(&pdev->dev, "pll8_mlb");
++ if (IS_ERR(drvdata->clk_mlb6p)) {
++ dev_err(&pdev->dev, "unable to get mlb pll clock\n");
++ ret = PTR_ERR(drvdata->clk_mlb6p);
++ goto err_dev;
++ }
++ }
++
++ drvdata->iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!drvdata->iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ ret = -ENOMEM;
++ goto err_dev;
++ }
++
++ drvdata->devinfo = NULL;
++ mxc_mlb150_irq_enable(drvdata, 0);
++ platform_set_drvdata(pdev, drvdata);
++ return 0;
++
++err_dev:
++ for (--i; i >= 0; i--)
++ device_destroy(drvdata->class, MKDEV(mlb_major, i));
++
++ class_destroy(drvdata->class);
++err_class:
++ cdev_del(&drvdata->cdev);
++err_reg:
++ unregister_chrdev_region(drvdata->firstdev, MLB_MINOR_DEVICES);
++
++ return ret;
++}
++
++static int mxc_mlb150_remove(struct platform_device *pdev)
++{
++ int i;
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt))
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++
++ /* destroy mlb device class */
++ for (i = MLB_MINOR_DEVICES - 1; i >= 0; i--)
++ device_destroy(drvdata->class,
++ MKDEV(MAJOR(drvdata->firstdev), i));
++ class_destroy(drvdata->class);
++
++ cdev_del(&drvdata->cdev);
++
++ /* Unregister the two MLB devices */
++ unregister_chrdev_region(drvdata->firstdev, MLB_MINOR_DEVICES);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int mxc_mlb150_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->on)
++ && (pdevinfo->fps >= CLK_2048FS))
++ clk_disable_unprepare(drvdata->clk_mlb6p);
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt)) {
++ mlb150_dev_exit();
++ clk_disable_unprepare(drvdata->clk_mlb3p);
++ }
++
++ return 0;
++}
++
++static int mxc_mlb150_resume(struct platform_device *pdev)
++{
++ struct mlb_data *drvdata = platform_get_drvdata(pdev);
++ struct mlb_dev_info *pdevinfo = drvdata->devinfo;
++
++ if (pdevinfo && atomic_read(&pdevinfo->opencnt)) {
++ clk_prepare_enable(drvdata->clk_mlb3p);
++ mlb150_dev_init();
++ }
++
++ if (pdevinfo && atomic_read(&pdevinfo->on) &&
++ (pdevinfo->fps >= CLK_2048FS))
++ clk_prepare_enable(drvdata->clk_mlb6p);
++
++ return 0;
++}
++#else
++#define mxc_mlb150_suspend NULL
++#define mxc_mlb150_resume NULL
++#endif
++
++/*
++ * platform driver structure for MLB
++ */
++static struct platform_driver mxc_mlb150_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = mlb150_imx_dt_ids,
++ },
++ .probe = mxc_mlb150_probe,
++ .remove = mxc_mlb150_remove,
++ .suspend = mxc_mlb150_suspend,
++ .resume = mxc_mlb150_resume,
++ .id_table = imx_mlb150_devtype,
++};
++
++static int __init mxc_mlb150_init(void)
++{
++ return platform_driver_register(&mxc_mlb150_driver);
++}
++
++static void __exit mxc_mlb150_exit(void)
++{
++ platform_driver_unregister(&mxc_mlb150_driver);
++}
++
++module_init(mxc_mlb150_init);
++module_exit(mxc_mlb150_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MLB150 low level driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/mxc/vpu/Kconfig linux-3.14.72/drivers/mxc/vpu/Kconfig
+--- linux-3.14.72.orig/drivers/mxc/vpu/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/vpu/Kconfig 2016-06-19 22:11:55.261142894 +0200
+@@ -0,0 +1,31 @@
++#
++# Codec configuration
++#
++
++menu "MXC VPU(Video Processing Unit) support"
++
++config MXC_VPU
++ tristate "Support for MXC VPU(Video Processing Unit)"
++ depends on (SOC_IMX27 || SOC_IMX5 || SOC_IMX6Q)
++ default y
++ ---help---
++ The VPU codec device provides codec function for H.264/MPEG4/H.263,
++ as well as MPEG2/VC-1/DivX on some platforms.
++
++config MXC_VPU_DEBUG
++ bool "MXC VPU debugging"
++ depends on MXC_VPU != n
++ help
++ This is an option for the developers; most people should
++ say N here. This enables MXC VPU driver debugging.
++
++config MX6_VPU_352M
++ bool "MX6 VPU 352M"
++ depends on MXC_VPU
++ default n
++ help
++ Increase VPU frequncy to 352M, the config will disable bus frequency
++ adjust dynamic, and CPU lowest setpoint will be 352Mhz.
++ This config is used for special VPU use case.
++
++endmenu
+diff -Nur linux-3.14.72.orig/drivers/mxc/vpu/Makefile linux-3.14.72/drivers/mxc/vpu/Makefile
+--- linux-3.14.72.orig/drivers/mxc/vpu/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/vpu/Makefile 2016-06-19 22:11:55.261142894 +0200
+@@ -0,0 +1,9 @@
++#
++# Makefile for the VPU drivers.
++#
++
++obj-$(CONFIG_MXC_VPU) += mxc_vpu.o
++
++ifeq ($(CONFIG_MXC_VPU_DEBUG),y)
++EXTRA_CFLAGS += -DDEBUG
++endif
+diff -Nur linux-3.14.72.orig/drivers/mxc/vpu/mxc_vpu.c linux-3.14.72/drivers/mxc/vpu/mxc_vpu.c
+--- linux-3.14.72.orig/drivers/mxc/vpu/mxc_vpu.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/mxc/vpu/mxc_vpu.c 2016-06-19 22:11:55.261142894 +0200
+@@ -0,0 +1,1346 @@
++/*
++ * Copyright 2006-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_vpu.c
++ *
++ * @brief VPU system initialization and file operation implementation
++ *
++ * @ingroup VPU
++ */
++
++#include <linux/kernel.h>
++#include <linux/mm.h>
++#include <linux/interrupt.h>
++#include <linux/ioport.h>
++#include <linux/stat.h>
++#include <linux/platform_device.h>
++#include <linux/kdev_t.h>
++#include <linux/dma-mapping.h>
++#include <linux/wait.h>
++#include <linux/list.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/fsl_devices.h>
++#include <linux/uaccess.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/workqueue.h>
++#include <linux/sched.h>
++#include <linux/vmalloc.h>
++#include <linux/regulator/consumer.h>
++#include <linux/page-flags.h>
++#include <linux/mm_types.h>
++#include <linux/types.h>
++#include <linux/memblock.h>
++#include <linux/memory.h>
++#include <linux/version.h>
++#include <asm/page.h>
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++#include <linux/module.h>
++#include <linux/pm_runtime.h>
++#include <linux/sizes.h>
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 10, 0)
++#include <linux/iram_alloc.h>
++#include <mach/clock.h>
++#include <mach/hardware.h>
++#include <mach/mxc_vpu.h>
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++#include <linux/busfreq-imx6.h>
++#include <linux/clk.h>
++#include <linux/genalloc.h>
++#include <linux/mxc_vpu.h>
++#include <linux/of.h>
++#include <linux/reset.h>
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++#include <mach/busfreq.h>
++#include <mach/common.h>
++#else
++#include <asm/sizes.h>
++#endif
++
++/* Define one new pgprot which combined uncached and XN(never executable) */
++#define pgprot_noncachedxn(prot) \
++ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED | L_PTE_XN)
++
++struct vpu_priv {
++ struct fasync_struct *async_queue;
++ struct work_struct work;
++ struct workqueue_struct *workqueue;
++ struct mutex lock;
++};
++
++/* To track the allocated memory buffer */
++struct memalloc_record {
++ struct list_head list;
++ struct vpu_mem_desc mem;
++};
++
++struct iram_setting {
++ u32 start;
++ u32 end;
++};
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static struct gen_pool *iram_pool;
++static u32 iram_base;
++#endif
++
++static LIST_HEAD(head);
++
++static int vpu_major;
++static int vpu_clk_usercount;
++static struct class *vpu_class;
++static struct vpu_priv vpu_data;
++static u8 open_count;
++static struct clk *vpu_clk;
++static struct vpu_mem_desc bitwork_mem = { 0 };
++static struct vpu_mem_desc pic_para_mem = { 0 };
++static struct vpu_mem_desc user_data_mem = { 0 };
++static struct vpu_mem_desc share_mem = { 0 };
++static struct vpu_mem_desc vshare_mem = { 0 };
++
++static void __iomem *vpu_base;
++static int vpu_ipi_irq;
++static u32 phy_vpu_base_addr;
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++static phys_addr_t top_address_DRAM;
++static struct mxc_vpu_platform_data *vpu_plat;
++#endif
++
++static struct device *vpu_dev;
++
++/* IRAM setting */
++static struct iram_setting iram;
++
++/* implement the blocking ioctl */
++static int irq_status;
++static int codec_done;
++static wait_queue_head_t vpu_queue;
++
++#ifdef CONFIG_SOC_IMX6Q
++#define MXC_VPU_HAS_JPU
++#endif
++
++#ifdef MXC_VPU_HAS_JPU
++static int vpu_jpu_irq;
++#endif
++
++#ifdef CONFIG_PM
++static unsigned int regBk[64];
++static unsigned int pc_before_suspend;
++#endif
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static struct regulator *vpu_regulator;
++#endif
++#endif
++static atomic_t clk_cnt_from_ioc = ATOMIC_INIT(0);
++
++#define READ_REG(x) readl_relaxed(vpu_base + x)
++#define WRITE_REG(val, x) writel_relaxed(val, vpu_base + x)
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++/* redirect to static functions */
++static int cpu_is_mx6dl(void)
++{
++ int ret;
++ ret = of_machine_is_compatible("fsl,imx6dl");
++ return ret;
++}
++
++static int cpu_is_mx6q(void)
++{
++ int ret;
++ ret = of_machine_is_compatible("fsl,imx6q");
++ return ret;
++}
++#endif
++
++static void vpu_reset(void)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ device_reset(vpu_dev);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ imx_src_reset_vpu();
++#else
++ if (vpu_plat->reset)
++ vpu_plat->reset();
++#endif
++}
++
++static long vpu_power_get(bool on)
++{
++ long ret = 0;
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)
++ if (on) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ vpu_regulator = regulator_get(NULL, "cpu_vddvpu");
++ ret = IS_ERR(vpu_regulator);
++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ vpu_regulator = devm_regulator_get(vpu_dev, "pu");
++ ret = IS_ERR(vpu_regulator);
++#endif
++ } else {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (!IS_ERR(vpu_regulator))
++ regulator_put(vpu_regulator);
++#endif
++ }
++#endif
++ return ret;
++}
++
++static void vpu_power_up(bool on)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ if (on)
++ pm_runtime_get_sync(vpu_dev);
++#endif
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0) || LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ if (on) {
++ if (!IS_ERR(vpu_regulator)) {
++ if (regulator_enable(vpu_regulator))
++ dev_err(vpu_dev, "failed to power up vpu\n");
++ }
++ } else {
++ if (!IS_ERR(vpu_regulator)) {
++ if (regulator_disable(vpu_regulator))
++ dev_err(vpu_dev, "failed to power down vpu\n");
++ }
++ }
++#else
++ imx_gpc_power_up_pu(on);
++#endif
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ if (!on)
++ pm_runtime_put_sync_suspend(vpu_dev);
++#endif
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++static int cpu_is_mx53(void)
++{
++ return 0;
++}
++
++static int cpu_is_mx51(void)
++{
++ return 0;
++}
++
++#define VM_RESERVED 0
++#endif
++
++/*!
++ * Private function to alloc dma buffer
++ * @return status 0 success.
++ */
++static int vpu_alloc_dma_buffer(struct vpu_mem_desc *mem)
++{
++ mem->cpu_addr = (unsigned long)
++ dma_alloc_coherent(vpu_dev, PAGE_ALIGN(mem->size),
++ (dma_addr_t *) (&mem->phy_addr),
++ GFP_DMA | GFP_KERNEL);
++ dev_dbg(vpu_dev, "[ALLOC] mem alloc cpu_addr = 0x%x\n", mem->cpu_addr);
++ if ((void *)(mem->cpu_addr) == NULL) {
++ dev_err(vpu_dev, "Physical memory allocation error!\n");
++ return -1;
++ }
++ return 0;
++}
++
++/*!
++ * Private function to free dma buffer
++ */
++static void vpu_free_dma_buffer(struct vpu_mem_desc *mem)
++{
++ if (mem->cpu_addr != 0) {
++ dma_free_coherent(vpu_dev, PAGE_ALIGN(mem->size),
++ (void *)mem->cpu_addr, mem->phy_addr);
++ }
++}
++
++/*!
++ * Private function to free buffers
++ * @return status 0 success.
++ */
++static int vpu_free_buffers(void)
++{
++ struct memalloc_record *rec, *n;
++ struct vpu_mem_desc mem;
++
++ list_for_each_entry_safe(rec, n, &head, list) {
++ mem = rec->mem;
++ if (mem.cpu_addr != 0) {
++ vpu_free_dma_buffer(&mem);
++ dev_dbg(vpu_dev, "[FREE] freed paddr=0x%08X\n", mem.phy_addr);
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ }
++ }
++
++ return 0;
++}
++
++static inline void vpu_worker_callback(struct work_struct *w)
++{
++ struct vpu_priv *dev = container_of(w, struct vpu_priv,
++ work);
++
++ if (dev->async_queue)
++ kill_fasync(&dev->async_queue, SIGIO, POLL_IN);
++
++ irq_status = 1;
++ /*
++ * Clock is gated on when dec/enc started, gate it off when
++ * codec is done.
++ */
++ if (codec_done)
++ codec_done = 0;
++
++ wake_up_interruptible(&vpu_queue);
++}
++
++/*!
++ * @brief vpu interrupt handler
++ */
++static irqreturn_t vpu_ipi_irq_handler(int irq, void *dev_id)
++{
++ struct vpu_priv *dev = dev_id;
++ unsigned long reg;
++
++ reg = READ_REG(BIT_INT_REASON);
++ if (reg & 0x8)
++ codec_done = 1;
++ WRITE_REG(0x1, BIT_INT_CLEAR);
++
++ queue_work(dev->workqueue, &dev->work);
++
++ return IRQ_HANDLED;
++}
++
++/*!
++ * @brief vpu jpu interrupt handler
++ */
++#ifdef MXC_VPU_HAS_JPU
++static irqreturn_t vpu_jpu_irq_handler(int irq, void *dev_id)
++{
++ struct vpu_priv *dev = dev_id;
++ unsigned long reg;
++
++ reg = READ_REG(MJPEG_PIC_STATUS_REG);
++ if (reg & 0x3)
++ codec_done = 1;
++
++ queue_work(dev->workqueue, &dev->work);
++
++ return IRQ_HANDLED;
++}
++#endif
++
++/*!
++ * @brief check phy memory prepare to pass to vpu is valid or not, we
++ * already address some issue that if pass a wrong address to vpu
++ * (like virtual address), system will hang.
++ *
++ * @return true return is a valid phy memory address, false return not.
++ */
++bool vpu_is_valid_phy_memory(u32 paddr)
++{
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (paddr > top_address_DRAM)
++ return false;
++#endif
++
++ return true;
++}
++
++/*!
++ * @brief open function for vpu file operation
++ *
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_open(struct inode *inode, struct file *filp)
++{
++
++ mutex_lock(&vpu_data.lock);
++
++ if (open_count++ == 0) {
++ vpu_power_up(true);
++
++#ifdef CONFIG_SOC_IMX6Q
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_CUR_PC))
++ dev_dbg(vpu_dev, "Not power off before vpu open!\n");
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++#endif
++ }
++
++ filp->private_data = (void *)(&vpu_data);
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++/*!
++ * @brief IO ctrl function for vpu file operation
++ * @param cmd IO ctrl command
++ * @return 0 on success or negative error code on error
++ */
++static long vpu_ioctl(struct file *filp, u_int cmd,
++ u_long arg)
++{
++ int ret = 0;
++
++ switch (cmd) {
++ case VPU_IOC_PHYMEM_ALLOC:
++ {
++ struct memalloc_record *rec;
++
++ rec = kzalloc(sizeof(*rec), GFP_KERNEL);
++ if (!rec)
++ return -ENOMEM;
++
++ ret = copy_from_user(&(rec->mem),
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ kfree(rec);
++ return -EFAULT;
++ }
++
++ dev_dbg(vpu_dev, "[ALLOC] mem alloc size = 0x%x\n",
++ rec->mem.size);
++
++ ret = vpu_alloc_dma_buffer(&(rec->mem));
++ if (ret == -1) {
++ kfree(rec);
++ dev_err(vpu_dev,
++ "Physical memory allocation error!\n");
++ break;
++ }
++ ret = copy_to_user((void __user *)arg, &(rec->mem),
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ kfree(rec);
++ ret = -EFAULT;
++ break;
++ }
++
++ mutex_lock(&vpu_data.lock);
++ list_add(&rec->list, &head);
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ case VPU_IOC_PHYMEM_FREE:
++ {
++ struct memalloc_record *rec, *n;
++ struct vpu_mem_desc vpu_mem;
++
++ ret = copy_from_user(&vpu_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret)
++ return -EACCES;
++
++ dev_dbg(vpu_dev, "[FREE] mem freed cpu_addr = 0x%x\n",
++ vpu_mem.cpu_addr);
++ if ((void *)vpu_mem.cpu_addr != NULL)
++ vpu_free_dma_buffer(&vpu_mem);
++
++ mutex_lock(&vpu_data.lock);
++ list_for_each_entry_safe(rec, n, &head, list) {
++ if (rec->mem.cpu_addr == vpu_mem.cpu_addr) {
++ /* delete from list */
++ list_del(&rec->list);
++ kfree(rec);
++ break;
++ }
++ }
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ case VPU_IOC_WAIT4INT:
++ {
++ u_long timeout = (u_long) arg;
++ if (!wait_event_interruptible_timeout
++ (vpu_queue, irq_status != 0,
++ msecs_to_jiffies(timeout))) {
++ dev_warn(vpu_dev, "VPU blocking: timeout.\n");
++ ret = -ETIME;
++ } else if (signal_pending(current)) {
++ dev_warn(vpu_dev, "VPU interrupt received.\n");
++ ret = -ERESTARTSYS;
++ } else
++ irq_status = 0;
++ break;
++ }
++ case VPU_IOC_IRAM_SETTING:
++ {
++ ret = copy_to_user((void __user *)arg, &iram,
++ sizeof(struct iram_setting));
++ if (ret)
++ ret = -EFAULT;
++
++ break;
++ }
++ case VPU_IOC_CLKGATE_SETTING:
++ {
++ u32 clkgate_en;
++
++ if (get_user(clkgate_en, (u32 __user *) arg))
++ return -EFAULT;
++
++ if (clkgate_en) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ atomic_inc(&clk_cnt_from_ioc);
++ } else {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ atomic_dec(&clk_cnt_from_ioc);
++ }
++
++ break;
++ }
++ case VPU_IOC_GET_SHARE_MEM:
++ {
++ mutex_lock(&vpu_data.lock);
++ if (share_mem.cpu_addr != 0) {
++ ret = copy_to_user((void __user *)arg,
++ &share_mem,
++ sizeof(struct vpu_mem_desc));
++ mutex_unlock(&vpu_data.lock);
++ break;
++ } else {
++ if (copy_from_user(&share_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc))) {
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++ if (vpu_alloc_dma_buffer(&share_mem) == -1)
++ ret = -EFAULT;
++ else {
++ if (copy_to_user((void __user *)arg,
++ &share_mem,
++ sizeof(struct
++ vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ }
++ mutex_unlock(&vpu_data.lock);
++ break;
++ }
++ case VPU_IOC_REQ_VSHARE_MEM:
++ {
++ mutex_lock(&vpu_data.lock);
++ if (vshare_mem.cpu_addr != 0) {
++ ret = copy_to_user((void __user *)arg,
++ &vshare_mem,
++ sizeof(struct vpu_mem_desc));
++ mutex_unlock(&vpu_data.lock);
++ break;
++ } else {
++ if (copy_from_user(&vshare_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct
++ vpu_mem_desc))) {
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++ /* vmalloc shared memory if not allocated */
++ if (!vshare_mem.cpu_addr)
++ vshare_mem.cpu_addr =
++ (unsigned long)
++ vmalloc_user(vshare_mem.size);
++ if (copy_to_user
++ ((void __user *)arg, &vshare_mem,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ mutex_unlock(&vpu_data.lock);
++ break;
++ }
++ case VPU_IOC_GET_WORK_ADDR:
++ {
++ if (bitwork_mem.cpu_addr != 0) {
++ ret =
++ copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct vpu_mem_desc));
++ break;
++ } else {
++ if (copy_from_user(&bitwork_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc)))
++ return -EFAULT;
++
++ if (vpu_alloc_dma_buffer(&bitwork_mem) == -1)
++ ret = -EFAULT;
++ else if (copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct
++ vpu_mem_desc)))
++ ret = -EFAULT;
++ }
++ break;
++ }
++ /*
++ * The following two ioctl is used when user allocates working buffer
++ * and register it to vpu driver.
++ */
++ case VPU_IOC_QUERY_BITWORK_MEM:
++ {
++ if (copy_to_user((void __user *)arg,
++ &bitwork_mem,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ break;
++ }
++ case VPU_IOC_SET_BITWORK_MEM:
++ {
++ if (copy_from_user(&bitwork_mem,
++ (struct vpu_mem_desc *)arg,
++ sizeof(struct vpu_mem_desc)))
++ ret = -EFAULT;
++ break;
++ }
++ case VPU_IOC_SYS_SW_RESET:
++ {
++ vpu_reset();
++ break;
++ }
++ case VPU_IOC_REG_DUMP:
++ break;
++ case VPU_IOC_PHYMEM_DUMP:
++ break;
++ case VPU_IOC_PHYMEM_CHECK:
++ {
++ struct vpu_mem_desc check_memory;
++ ret = copy_from_user(&check_memory,
++ (void __user *)arg,
++ sizeof(struct vpu_mem_desc));
++ if (ret != 0) {
++ dev_err(vpu_dev, "copy from user failure:%d\n", ret);
++ ret = -EFAULT;
++ break;
++ }
++ ret = vpu_is_valid_phy_memory((u32)check_memory.phy_addr);
++
++ dev_dbg(vpu_dev, "vpu: memory phy:0x%x %s phy memory\n",
++ check_memory.phy_addr, (ret ? "is" : "isn't"));
++ /* borrow .size to pass back the result. */
++ check_memory.size = ret;
++ ret = copy_to_user((void __user *)arg, &check_memory,
++ sizeof(struct vpu_mem_desc));
++ if (ret) {
++ ret = -EFAULT;
++ break;
++ }
++ break;
++ }
++ case VPU_IOC_LOCK_DEV:
++ {
++ u32 lock_en;
++
++ if (get_user(lock_en, (u32 __user *) arg))
++ return -EFAULT;
++
++ if (lock_en)
++ mutex_lock(&vpu_data.lock);
++ else
++ mutex_unlock(&vpu_data.lock);
++
++ break;
++ }
++ default:
++ {
++ dev_err(vpu_dev, "No such IOCTL, cmd is %d\n", cmd);
++ ret = -EINVAL;
++ break;
++ }
++ }
++ return ret;
++}
++
++/*!
++ * @brief Release function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_release(struct inode *inode, struct file *filp)
++{
++ int i;
++ unsigned long timeout;
++
++ mutex_lock(&vpu_data.lock);
++
++ if (open_count > 0 && !(--open_count)) {
++
++ /* Wait for vpu go to idle state */
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_CUR_PC)) {
++
++ timeout = jiffies + HZ;
++ while (READ_REG(BIT_BUSY_FLAG)) {
++ msleep(1);
++ if (time_after(jiffies, timeout)) {
++ dev_warn(vpu_dev, "VPU timeout during release\n");
++ break;
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ /* Clean up interrupt */
++ cancel_work_sync(&vpu_data.work);
++ flush_workqueue(vpu_data.workqueue);
++ irq_status = 0;
++
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ if (READ_REG(BIT_BUSY_FLAG)) {
++
++ if (cpu_is_mx51() || cpu_is_mx53()) {
++ dev_err(vpu_dev,
++ "fatal error: can't gate/power off when VPU is busy\n");
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ }
++
++#ifdef CONFIG_SOC_IMX6Q
++ if (cpu_is_mx6dl() || cpu_is_mx6q()) {
++ WRITE_REG(0x11, 0x10F0);
++ timeout = jiffies + HZ;
++ while (READ_REG(0x10F4) != 0x77) {
++ msleep(1);
++ if (time_after(jiffies, timeout))
++ break;
++ }
++
++ if (READ_REG(0x10F4) != 0x77) {
++ dev_err(vpu_dev,
++ "fatal error: can't gate/power off when VPU is busy\n");
++ WRITE_REG(0x0, 0x10F0);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EFAULT;
++ } else
++ vpu_reset();
++ }
++#endif
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ vpu_free_buffers();
++
++ /* Free shared memory when vpu device is idle */
++ vpu_free_dma_buffer(&share_mem);
++ share_mem.cpu_addr = 0;
++ vfree((void *)vshare_mem.cpu_addr);
++ vshare_mem.cpu_addr = 0;
++
++ vpu_clk_usercount = atomic_read(&clk_cnt_from_ioc);
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ atomic_dec(&clk_cnt_from_ioc);
++ }
++
++ vpu_power_up(false);
++ }
++ mutex_unlock(&vpu_data.lock);
++
++ return 0;
++}
++
++/*!
++ * @brief fasync function for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_fasync(int fd, struct file *filp, int mode)
++{
++ struct vpu_priv *dev = (struct vpu_priv *)filp->private_data;
++ return fasync_helper(fd, filp, mode, &dev->async_queue);
++}
++
++/*!
++ * @brief memory map function of harware registers for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_hwregs(struct file *fp, struct vm_area_struct *vm)
++{
++ unsigned long pfn;
++
++ vm->vm_flags |= VM_IO | VM_RESERVED;
++ /*
++ * Since vpu registers have been mapped with ioremap() at probe
++ * which L_PTE_XN is 1, and the same physical address must be
++ * mapped multiple times with same type, so set L_PTE_XN to 1 here.
++ * Otherwise, there may be unexpected result in video codec.
++ */
++ vm->vm_page_prot = pgprot_noncachedxn(vm->vm_page_prot);
++ pfn = phy_vpu_base_addr >> PAGE_SHIFT;
++ dev_dbg(vpu_dev, "size=0x%x, page no.=0x%x\n",
++ (int)(vm->vm_end - vm->vm_start), (int)pfn);
++ return remap_pfn_range(vm, vm->vm_start, pfn, vm->vm_end - vm->vm_start,
++ vm->vm_page_prot) ? -EAGAIN : 0;
++}
++
++/*!
++ * @brief memory map function of memory for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_dma_mem(struct file *fp, struct vm_area_struct *vm)
++{
++ int request_size;
++ request_size = vm->vm_end - vm->vm_start;
++
++ dev_dbg(vpu_dev, "start=0x%x, pgoff=0x%x, size=0x%x\n",
++ (unsigned int)(vm->vm_start), (unsigned int)(vm->vm_pgoff),
++ request_size);
++
++ vm->vm_flags |= VM_IO | VM_RESERVED;
++ vm->vm_page_prot = pgprot_writecombine(vm->vm_page_prot);
++
++ return remap_pfn_range(vm, vm->vm_start, vm->vm_pgoff,
++ request_size, vm->vm_page_prot) ? -EAGAIN : 0;
++
++}
++
++/* !
++ * @brief memory map function of vmalloced share memory
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_map_vshare_mem(struct file *fp, struct vm_area_struct *vm)
++{
++ int ret = -EINVAL;
++
++ ret = remap_vmalloc_range(vm, (void *)(vm->vm_pgoff << PAGE_SHIFT), 0);
++ vm->vm_flags |= VM_IO;
++
++ return ret;
++}
++/*!
++ * @brief memory map interface for vpu file operation
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_mmap(struct file *fp, struct vm_area_struct *vm)
++{
++ unsigned long offset;
++
++ offset = vshare_mem.cpu_addr >> PAGE_SHIFT;
++
++ if (vm->vm_pgoff && (vm->vm_pgoff == offset))
++ return vpu_map_vshare_mem(fp, vm);
++ else if (vm->vm_pgoff)
++ return vpu_map_dma_mem(fp, vm);
++ else
++ return vpu_map_hwregs(fp, vm);
++}
++
++const struct file_operations vpu_fops = {
++ .owner = THIS_MODULE,
++ .open = vpu_open,
++ .unlocked_ioctl = vpu_ioctl,
++ .release = vpu_release,
++ .fasync = vpu_fasync,
++ .mmap = vpu_mmap,
++};
++
++/*!
++ * This function is called by the driver framework to initialize the vpu device.
++ * @param dev The device structure for the vpu passed in by the framework.
++ * @return 0 on success or negative error code on error
++ */
++static int vpu_dev_probe(struct platform_device *pdev)
++{
++ int err = 0;
++ struct device *temp_class;
++ struct resource *res;
++ unsigned long addr = 0;
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ struct device_node *np = pdev->dev.of_node;
++ u32 iramsize;
++
++ err = of_property_read_u32(np, "iramsize", (u32 *)&iramsize);
++ if (!err && iramsize)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ {
++ iram_pool = of_get_named_gen_pool(np, "iram", 0);
++ if (!iram_pool) {
++ dev_err(&pdev->dev, "iram pool not available\n");
++ return -ENOMEM;
++ }
++
++ iram_base = gen_pool_alloc(iram_pool, iramsize);
++ if (!iram_base) {
++ dev_err(&pdev->dev, "unable to alloc iram\n");
++ return -ENOMEM;
++ }
++
++ addr = gen_pool_virt_to_phys(iram_pool, iram_base);
++ }
++#else
++ iram_alloc(iramsize, &addr);
++#endif
++ if (addr == 0)
++ iram.start = iram.end = 0;
++ else {
++ iram.start = addr;
++ iram.end = addr + iramsize - 1;
++ }
++#else
++
++ vpu_plat = pdev->dev.platform_data;
++
++ if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
++ iram_alloc(vpu_plat->iram_size, &addr);
++ if (addr == 0)
++ iram.start = iram.end = 0;
++ else {
++ iram.start = addr;
++ iram.end = addr + vpu_plat->iram_size - 1;
++ }
++#endif
++
++ vpu_dev = &pdev->dev;
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu_regs");
++ if (!res) {
++ dev_err(vpu_dev, "vpu: unable to get vpu base addr\n");
++ return -ENODEV;
++ }
++ phy_vpu_base_addr = res->start;
++ vpu_base = ioremap(res->start, res->end - res->start);
++
++ vpu_major = register_chrdev(vpu_major, "mxc_vpu", &vpu_fops);
++ if (vpu_major < 0) {
++ dev_err(vpu_dev, "vpu: unable to get a major for VPU\n");
++ err = -EBUSY;
++ goto error;
++ }
++
++ vpu_class = class_create(THIS_MODULE, "mxc_vpu");
++ if (IS_ERR(vpu_class)) {
++ err = PTR_ERR(vpu_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(vpu_class, NULL, MKDEV(vpu_major, 0),
++ NULL, "mxc_vpu");
++ if (IS_ERR(temp_class)) {
++ err = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ vpu_clk = clk_get(&pdev->dev, "vpu_clk");
++ if (IS_ERR(vpu_clk)) {
++ err = -ENOENT;
++ goto err_out_class;
++ }
++
++ vpu_ipi_irq = platform_get_irq_byname(pdev, "vpu_ipi_irq");
++ if (vpu_ipi_irq < 0) {
++ dev_err(vpu_dev, "vpu: unable to get vpu interrupt\n");
++ err = -ENXIO;
++ goto err_out_class;
++ }
++ err = request_irq(vpu_ipi_irq, vpu_ipi_irq_handler, 0, "VPU_CODEC_IRQ",
++ (void *)(&vpu_data));
++ if (err)
++ goto err_out_class;
++ if (vpu_power_get(true)) {
++ if (!(cpu_is_mx51() || cpu_is_mx53())) {
++ dev_err(vpu_dev, "failed to get vpu power\n");
++ goto err_out_class;
++ } else {
++ /* regulator_get will return error on MX5x,
++ * just igore it everywhere*/
++ dev_warn(vpu_dev, "failed to get vpu power\n");
++ }
++ }
++
++#ifdef MXC_VPU_HAS_JPU
++ vpu_jpu_irq = platform_get_irq_byname(pdev, "vpu_jpu_irq");
++ if (vpu_jpu_irq < 0) {
++ dev_err(vpu_dev, "vpu: unable to get vpu jpu interrupt\n");
++ err = -ENXIO;
++ free_irq(vpu_ipi_irq, &vpu_data);
++ goto err_out_class;
++ }
++ err = request_irq(vpu_jpu_irq, vpu_jpu_irq_handler, IRQF_TRIGGER_RISING,
++ "VPU_JPG_IRQ", (void *)(&vpu_data));
++ if (err) {
++ free_irq(vpu_ipi_irq, &vpu_data);
++ goto err_out_class;
++ }
++#endif
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_enable(&pdev->dev);
++#endif
++
++ vpu_data.workqueue = create_workqueue("vpu_wq");
++ INIT_WORK(&vpu_data.work, vpu_worker_callback);
++ mutex_init(&vpu_data.lock);
++ dev_info(vpu_dev, "VPU initialized\n");
++ goto out;
++
++err_out_class:
++ device_destroy(vpu_class, MKDEV(vpu_major, 0));
++ class_destroy(vpu_class);
++err_out_chrdev:
++ unregister_chrdev(vpu_major, "mxc_vpu");
++error:
++ iounmap(vpu_base);
++out:
++ return err;
++}
++
++static int vpu_dev_remove(struct platform_device *pdev)
++{
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ pm_runtime_disable(&pdev->dev);
++#endif
++ free_irq(vpu_ipi_irq, &vpu_data);
++#ifdef MXC_VPU_HAS_JPU
++ free_irq(vpu_jpu_irq, &vpu_data);
++#endif
++ cancel_work_sync(&vpu_data.work);
++ flush_workqueue(vpu_data.workqueue);
++ destroy_workqueue(vpu_data.workqueue);
++
++ iounmap(vpu_base);
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ if (iram.start)
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)
++ gen_pool_free(iram_pool, iram_base, iram.end-iram.start+1);
++#else
++ iram_free(iram.start, iram.end-iram.start+1);
++#endif
++#else
++ if (vpu_plat && vpu_plat->iram_enable && vpu_plat->iram_size)
++ iram_free(iram.start, vpu_plat->iram_size);
++#endif
++
++ vpu_power_get(false);
++ return 0;
++}
++
++#ifdef CONFIG_PM
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_suspend(struct device *dev)
++#else
++static int vpu_suspend(struct platform_device *pdev, pm_message_t state)
++#endif
++{
++ int i;
++ unsigned long timeout;
++
++ mutex_lock(&vpu_data.lock);
++ if (open_count == 0) {
++ /* VPU is released (all instances are freed),
++ * clock is already off, context is no longer needed,
++ * power is already off on MX6,
++ * gate power on MX51 */
++ if (cpu_is_mx51()) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(1);
++#endif
++ }
++ } else {
++ /* Wait for vpu go to idle state, suspect vpu cannot be changed
++ to idle state after about 1 sec */
++ timeout = jiffies + HZ;
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ while (READ_REG(BIT_BUSY_FLAG)) {
++ msleep(1);
++ if (time_after(jiffies, timeout)) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ mutex_unlock(&vpu_data.lock);
++ return -EAGAIN;
++ }
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++
++ /* Make sure clock is disabled before suspend */
++ vpu_clk_usercount = atomic_read(&clk_cnt_from_ioc);
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++ if (cpu_is_mx53()) {
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++ }
++
++ if (bitwork_mem.cpu_addr != 0) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ /* Save 64 registers from BIT_CODE_BUF_ADDR */
++ for (i = 0; i < 64; i++)
++ regBk[i] = READ_REG(BIT_CODE_BUF_ADDR + (i * 4));
++ pc_before_suspend = READ_REG(BIT_CUR_PC);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(1);
++#endif
++
++ /* If VPU is working before suspend, disable
++ * regulator to make usecount right. */
++ vpu_power_up(false);
++ }
++
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_resume(struct device *dev)
++#else
++static int vpu_resume(struct platform_device *pdev)
++#endif
++{
++ int i;
++
++ mutex_lock(&vpu_data.lock);
++ if (open_count == 0) {
++ /* VPU is released (all instances are freed),
++ * clock should be kept off, context is no longer needed,
++ * power should be kept off on MX6,
++ * disable power gating on MX51 */
++ if (cpu_is_mx51()) {
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(0);
++#endif
++ }
++ } else {
++ if (cpu_is_mx53())
++ goto recover_clk;
++
++ /* If VPU is working before suspend, enable
++ * regulator to make usecount right. */
++ vpu_power_up(true);
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ if (vpu_plat->pg)
++ vpu_plat->pg(0);
++#endif
++
++ if (bitwork_mem.cpu_addr != 0) {
++ u32 *p = (u32 *) bitwork_mem.cpu_addr;
++ u32 data, pc;
++ u16 data_hi;
++ u16 data_lo;
++
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++
++ pc = READ_REG(BIT_CUR_PC);
++ if (pc) {
++ dev_warn(vpu_dev, "Not power off after suspend (PC=0x%x)\n", pc);
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ goto recover_clk;
++ }
++
++ /* Restore registers */
++ for (i = 0; i < 64; i++)
++ WRITE_REG(regBk[i], BIT_CODE_BUF_ADDR + (i * 4));
++
++ WRITE_REG(0x0, BIT_RESET_CTRL);
++ WRITE_REG(0x0, BIT_CODE_RUN);
++ /* MX6 RTL has a bug not to init MBC_SET_SUBBLK_EN on reset */
++#ifdef CONFIG_SOC_IMX6Q
++ WRITE_REG(0x0, MBC_SET_SUBBLK_EN);
++#endif
++
++ /*
++ * Re-load boot code, from the codebuffer in external RAM.
++ * Thankfully, we only need 4096 bytes, same for all platforms.
++ */
++ for (i = 0; i < 2048; i += 4) {
++ data = p[(i / 2) + 1];
++ data_hi = (data >> 16) & 0xFFFF;
++ data_lo = data & 0xFFFF;
++ WRITE_REG((i << 16) | data_hi, BIT_CODE_DOWN);
++ WRITE_REG(((i + 1) << 16) | data_lo,
++ BIT_CODE_DOWN);
++
++ data = p[i / 2];
++ data_hi = (data >> 16) & 0xFFFF;
++ data_lo = data & 0xFFFF;
++ WRITE_REG(((i + 2) << 16) | data_hi,
++ BIT_CODE_DOWN);
++ WRITE_REG(((i + 3) << 16) | data_lo,
++ BIT_CODE_DOWN);
++ }
++
++ if (pc_before_suspend) {
++ WRITE_REG(0x1, BIT_BUSY_FLAG);
++ WRITE_REG(0x1, BIT_CODE_RUN);
++ while (READ_REG(BIT_BUSY_FLAG))
++ ;
++ } else {
++ dev_warn(vpu_dev, "PC=0 before suspend\n");
++ }
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ }
++
++recover_clk:
++ /* Recover vpu clock */
++ for (i = 0; i < vpu_clk_usercount; i++) {
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ }
++ }
++
++ mutex_unlock(&vpu_data.lock);
++ return 0;
++}
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static int vpu_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int vpu_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static const struct dev_pm_ops vpu_pm_ops = {
++ SET_RUNTIME_PM_OPS(vpu_runtime_suspend, vpu_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(vpu_suspend, vpu_resume)
++};
++#endif
++
++#else
++#define vpu_suspend NULL
++#define vpu_resume NULL
++#endif /* !CONFIG_PM */
++
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++static const struct of_device_id vpu_of_match[] = {
++ { .compatible = "fsl,imx6-vpu", },
++ {/* sentinel */}
++};
++MODULE_DEVICE_TABLE(of, vpu_of_match);
++#endif
++
++/*! Driver definition
++ *
++ */
++static struct platform_driver mxcvpu_driver = {
++ .driver = {
++ .name = "mxc_vpu",
++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 0)
++ .of_match_table = vpu_of_match,
++#ifdef CONFIG_PM
++ .pm = &vpu_pm_ops,
++#endif
++#endif
++ },
++ .probe = vpu_dev_probe,
++ .remove = vpu_dev_remove,
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ .suspend = vpu_suspend,
++ .resume = vpu_resume,
++#endif
++};
++
++static int __init vpu_init(void)
++{
++ int ret = platform_driver_register(&mxcvpu_driver);
++
++ init_waitqueue_head(&vpu_queue);
++
++
++#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 5, 0)
++ memblock_analyze();
++ top_address_DRAM = memblock_end_of_DRAM_with_reserved();
++#endif
++
++ return ret;
++}
++
++static void __exit vpu_exit(void)
++{
++ if (vpu_major > 0) {
++ device_destroy(vpu_class, MKDEV(vpu_major, 0));
++ class_destroy(vpu_class);
++ unregister_chrdev(vpu_major, "mxc_vpu");
++ vpu_major = 0;
++ }
++
++ vpu_free_dma_buffer(&bitwork_mem);
++ vpu_free_dma_buffer(&pic_para_mem);
++ vpu_free_dma_buffer(&user_data_mem);
++
++ /* reset VPU state */
++ vpu_power_up(true);
++ clk_prepare(vpu_clk);
++ clk_enable(vpu_clk);
++ vpu_reset();
++ clk_disable(vpu_clk);
++ clk_unprepare(vpu_clk);
++ vpu_power_up(false);
++
++ clk_put(vpu_clk);
++
++ platform_driver_unregister(&mxcvpu_driver);
++ return;
++}
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Linux VPU driver for Freescale i.MX/MXC");
++MODULE_LICENSE("GPL");
++
++module_init(vpu_init);
++module_exit(vpu_exit);
+diff -Nur linux-3.14.72.orig/drivers/net/can/flexcan.c linux-3.14.72/drivers/net/can/flexcan.c
+--- linux-3.14.72.orig/drivers/net/can/flexcan.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/can/flexcan.c 2016-06-19 22:11:55.261142894 +0200
+@@ -24,6 +24,7 @@
+ #include <linux/can/dev.h>
+ #include <linux/can/error.h>
+ #include <linux/can/led.h>
++#include <linux/can/platform/flexcan.h>
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/if_arp.h>
+@@ -32,11 +33,14 @@
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/list.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/regmap.h>
+
+ #define DRV_NAME "flexcan"
+
+@@ -122,10 +126,12 @@
+ (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
+ #define FLEXCAN_ESR_ALL_INT \
+ (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
+- FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
++ FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT | \
++ FLEXCAN_ESR_WAK_INT)
+
+ /* FLEXCAN interrupt flag register (IFLAG) bits */
+-#define FLEXCAN_TX_BUF_ID 8
++#define FLEXCAN_RESERVED_BUF_ID 8
++#define FLEXCAN_TX_BUF_ID 13
+ #define FLEXCAN_IFLAG_BUF(x) BIT(x)
+ #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
+ #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
+@@ -162,6 +168,7 @@
+ */
+ #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
+ #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
++#define FLEXCAN_HAS_ERR005829 BIT(3) /* have errata ERR005829 */
+
+ /* Structure of the message buffer */
+ struct flexcan_mb {
+@@ -200,6 +207,13 @@
+ u32 features; /* hardware controller features */
+ };
+
++struct flexcan_stop_mode {
++ struct regmap *gpr;
++ u8 req_gpr;
++ u8 req_bit;
++ u8 ack_gpr;
++ u8 ack_bit;
++};
+ struct flexcan_priv {
+ struct can_priv can;
+ struct net_device *dev;
+@@ -214,6 +228,8 @@
+ struct flexcan_platform_data *pdata;
+ const struct flexcan_devtype_data *devtype_data;
+ struct regulator *reg_xceiver;
++ struct flexcan_stop_mode stm;
++ int id;
+ };
+
+ static struct flexcan_devtype_data fsl_p1010_devtype_data = {
+@@ -221,7 +237,7 @@
+ };
+ static struct flexcan_devtype_data fsl_imx28_devtype_data;
+ static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
+- .features = FLEXCAN_HAS_V10_FEATURES,
++ .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_ERR005829,
+ };
+
+ static const struct can_bittiming_const flexcan_bittiming_const = {
+@@ -264,8 +280,29 @@
+ }
+ #endif
+
++static inline void flexcan_enter_stop_mode(struct flexcan_priv *priv)
++{
++ /* enable stop request */
++ if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
++ regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
++ 1 << priv->stm.req_bit, 1 << priv->stm.req_bit);
++}
++
++static inline void flexcan_exit_stop_mode(struct flexcan_priv *priv)
++{
++ /* remove stop request */
++ if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
++ regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr,
++ 1 << priv->stm.req_bit, 0);
++}
++
+ static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv)
+ {
++ if (priv->pdata && priv->pdata->transceiver_switch) {
++ priv->pdata->transceiver_switch(1);
++ return 0;
++ }
++
+ if (!priv->reg_xceiver)
+ return 0;
+
+@@ -274,6 +311,11 @@
+
+ static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv)
+ {
++ if (priv->pdata && priv->pdata->transceiver_switch) {
++ priv->pdata->transceiver_switch(0);
++ return 0;
++ }
++
+ if (!priv->reg_xceiver)
+ return 0;
+
+@@ -428,6 +470,11 @@
+ flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
+ flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
+
++ if (priv->devtype_data->features & FLEXCAN_HAS_ERR005829) {
++ writel(0x0, &regs->cantxfg[FLEXCAN_RESERVED_BUF_ID].can_ctrl);
++ writel(0x0, &regs->cantxfg[FLEXCAN_RESERVED_BUF_ID].can_ctrl);
++ }
++
+ return NETDEV_TX_OK;
+ }
+
+@@ -704,6 +751,9 @@
+ if (reg_esr & FLEXCAN_ESR_ALL_INT)
+ flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
+
++ if (reg_esr & FLEXCAN_ESR_WAK_INT)
++ flexcan_exit_stop_mode(priv);
++
+ /*
+ * schedule NAPI in case of:
+ * - rx IRQ
+@@ -817,13 +867,14 @@
+ * enable warning int
+ * choose format C
+ * disable local echo
+- *
++ * enable self wakeup
+ */
+ reg_mcr = flexcan_read(&regs->mcr);
+ reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
+ reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
+ FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
+ FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
++ FLEXCAN_MCR_WAK_MSK | FLEXCAN_MCR_SLF_WAK |
+ FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
+ netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
+ flexcan_write(reg_mcr, &regs->mcr);
+@@ -1075,6 +1126,56 @@
+ unregister_candev(dev);
+ }
+
++static int flexcan_of_parse_stop_mode(struct platform_device *pdev)
++{
++ struct net_device *dev = platform_get_drvdata(pdev);
++ struct device_node *np = pdev->dev.of_node;
++ struct device_node *node;
++ struct flexcan_priv *priv;
++ phandle phandle;
++ u32 out_val[5];
++ int ret;
++
++ if (!np)
++ return -EINVAL;
++ /*
++ * stop mode property format is:
++ * <&gpr req_gpr req_bit ack_gpr ack_bit>.
++ */
++ ret = of_property_read_u32_array(np, "stop-mode", out_val, 5);
++ if (ret) {
++ dev_dbg(&pdev->dev, "no stop-mode property\n");
++ return ret;
++ }
++ phandle = *out_val;
++
++ node = of_find_node_by_phandle(phandle);
++ if (!node) {
++ dev_dbg(&pdev->dev, "could not find gpr node by phandle\n");
++ return PTR_ERR(node);
++ }
++
++ priv = netdev_priv(dev);
++ priv->stm.gpr = syscon_node_to_regmap(node);
++ if (IS_ERR(priv->stm.gpr)) {
++ dev_dbg(&pdev->dev, "could not find gpr regmap\n");
++ return PTR_ERR(priv->stm.gpr);
++ }
++
++ of_node_put(node);
++
++ priv->stm.req_gpr = out_val[1];
++ priv->stm.req_bit = out_val[2];
++ priv->stm.ack_gpr = out_val[3];
++ priv->stm.ack_bit = out_val[4];
++
++ dev_dbg(&pdev->dev, "gpr %s req_gpr 0x%x req_bit %u ack_gpr 0x%x ack_bit %u\n",
++ node->full_name, priv->stm.req_gpr,
++ priv->stm.req_bit, priv->stm.ack_gpr,
++ priv->stm.ack_bit);
++ return 0;
++}
++
+ static const struct of_device_id flexcan_of_match[] = {
+ { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
+ { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
+@@ -1101,6 +1202,7 @@
+ void __iomem *base;
+ int err, irq;
+ u32 clock_freq = 0;
++ int wakeup = 1;
+
+ reg_xceiver = devm_regulator_get(&pdev->dev, "xceiver");
+ if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER)
+@@ -1184,6 +1286,16 @@
+
+ devm_can_led_init(dev);
+
++ if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES) {
++ err = flexcan_of_parse_stop_mode(pdev);
++ if (err) {
++ wakeup = 0;
++ dev_dbg(&pdev->dev, "failed to parse stop-mode\n");
++ }
++ }
++
++ device_set_wakeup_capable(&pdev->dev, wakeup);
++
+ dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
+ priv->base, dev->irq);
+
+@@ -1211,32 +1323,47 @@
+ {
+ struct net_device *dev = dev_get_drvdata(device);
+ struct flexcan_priv *priv = netdev_priv(dev);
+- int err;
+-
+- err = flexcan_chip_disable(priv);
+- if (err)
+- return err;
++ int err = 0;
+
+ if (netif_running(dev)) {
+ netif_stop_queue(dev);
+ netif_device_detach(dev);
++ /*
++ * if wakeup is enabled, enter stop mode
++ * else enter disabled mode.
++ */
++ if (device_may_wakeup(device)) {
++ enable_irq_wake(dev->irq);
++ flexcan_enter_stop_mode(priv);
++ } else {
++ err = flexcan_chip_disable(priv);
++ }
+ }
+ priv->can.state = CAN_STATE_SLEEPING;
+
+- return 0;
++ return err;
+ }
+
+ static int flexcan_resume(struct device *device)
+ {
+ struct net_device *dev = dev_get_drvdata(device);
+ struct flexcan_priv *priv = netdev_priv(dev);
++ int err = 0;
+
+ priv->can.state = CAN_STATE_ERROR_ACTIVE;
+ if (netif_running(dev)) {
+ netif_device_attach(dev);
+ netif_start_queue(dev);
++
++ if (device_may_wakeup(device)) {
++ disable_irq_wake(dev->irq);
++ flexcan_exit_stop_mode(priv);
++ } else {
++ err = flexcan_chip_enable(priv);
++ }
+ }
+- return flexcan_chip_enable(priv);
++
++ return err;
+ }
+ #endif /* CONFIG_PM_SLEEP */
+
+diff -Nur linux-3.14.72.orig/drivers/net/can/Kconfig linux-3.14.72/drivers/net/can/Kconfig
+--- linux-3.14.72.orig/drivers/net/can/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/can/Kconfig 2016-06-19 22:11:55.261142894 +0200
+@@ -125,6 +125,11 @@
+ endian syntheses of the cores would need some modifications on
+ the hardware level to work.
+
++config CAN_M_CAN
++ tristate "Bosch M_CAN devices"
++ ---help---
++ Say Y here if you want to support for Bosch M_CAN controller.
++
+ source "drivers/net/can/mscan/Kconfig"
+
+ source "drivers/net/can/sja1000/Kconfig"
+diff -Nur linux-3.14.72.orig/drivers/net/can/Makefile linux-3.14.72/drivers/net/can/Makefile
+--- linux-3.14.72.orig/drivers/net/can/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/can/Makefile 2016-06-19 22:11:55.261142894 +0200
+@@ -16,6 +16,7 @@
+ obj-$(CONFIG_CAN_SJA1000) += sja1000/
+ obj-$(CONFIG_CAN_MSCAN) += mscan/
+ obj-$(CONFIG_CAN_C_CAN) += c_can/
++obj-$(CONFIG_CAN_M_CAN) += m_can.o
+ obj-$(CONFIG_CAN_CC770) += cc770/
+ obj-$(CONFIG_CAN_AT91) += at91_can.o
+ obj-$(CONFIG_CAN_TI_HECC) += ti_hecc.o
+diff -Nur linux-3.14.72.orig/drivers/net/can/m_can.c linux-3.14.72/drivers/net/can/m_can.c
+--- linux-3.14.72.orig/drivers/net/can/m_can.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/can/m_can.c 2016-06-19 22:11:55.261142894 +0200
+@@ -0,0 +1,1094 @@
++/*
++ * CAN bus driver for Bosch M_CAN controller
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ * Dong Aisheng <b29396@freescale.com>
++ *
++ * Bosch M_CAN user manual can be obtained from:
++ * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
++ * mcan_users_manual_v302.pdf
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/if_arp.h>
++#include <linux/if_ether.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/list.h>
++#include <linux/module.h>
++#include <linux/netdevice.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_device.h>
++
++#include <linux/can/dev.h>
++
++/* napi related */
++#define M_CAN_NAPI_WEIGHT 64
++
++/* registers definition */
++enum m_can_reg {
++ M_CAN_CREL = 0x0,
++ M_CAN_ENDN = 0x4,
++ M_CAN_CUST = 0x8,
++ M_CAN_FBTP = 0xc,
++ M_CAN_TEST = 0x10,
++ M_CAN_RWD = 0x14,
++ M_CAN_CCCR = 0x18,
++ M_CAN_BTP = 0x1c,
++ M_CAN_TSCC = 0x20,
++ M_CAN_TSCV = 0x24,
++ M_CAN_TOCC = 0x28,
++ M_CAN_TOCV = 0x2c,
++ M_CAN_ECR = 0x40,
++ M_CAN_PSR = 0x44,
++ M_CAN_IR = 0x50,
++ M_CAN_IE = 0x54,
++ M_CAN_ILS = 0x58,
++ M_CAN_ILE = 0x5c,
++ M_CAN_GFC = 0x80,
++ M_CAN_SIDFC = 0x84,
++ M_CAN_XIDFC = 0x88,
++ M_CAN_XIDAM = 0x90,
++ M_CAN_HPMS = 0x94,
++ M_CAN_NDAT1 = 0x98,
++ M_CAN_NDAT2 = 0x9c,
++ M_CAN_RXF0C = 0xa0,
++ M_CAN_RXF0S = 0xa4,
++ M_CAN_RXF0A = 0xa8,
++ M_CAN_RXBC = 0xac,
++ M_CAN_RXF1C = 0xb0,
++ M_CAN_RXF1S = 0xb4,
++ M_CAN_RXF1A = 0xb8,
++ M_CAN_RXESC = 0xbc,
++ M_CAN_TXBC = 0xc0,
++ M_CAN_TXFQS = 0xc4,
++ M_CAN_TXESC = 0xc8,
++ M_CAN_TXBRP = 0xcc,
++ M_CAN_TXBAR = 0xd0,
++ M_CAN_TXBCR = 0xd4,
++ M_CAN_TXBTO = 0xd8,
++ M_CAN_TXBCF = 0xdc,
++ M_CAN_TXBTIE = 0xe0,
++ M_CAN_TXBCIE = 0xe4,
++ M_CAN_TXEFC = 0xf0,
++ M_CAN_TXEFS = 0xf4,
++ M_CAN_TXEFA = 0xf8,
++};
++
++/* m_can lec values */
++enum m_can_lec_type {
++ LEC_NO_ERROR = 0,
++ LEC_STUFF_ERROR,
++ LEC_FORM_ERROR,
++ LEC_ACK_ERROR,
++ LEC_BIT1_ERROR,
++ LEC_BIT0_ERROR,
++ LEC_CRC_ERROR,
++ LEC_UNUSED,
++};
++/* Test Register (TEST) */
++#define TEST_LBCK BIT(4)
++
++/* CC Control Register(CCCR) */
++#define CCCR_TEST BIT(7)
++#define CCCR_MON BIT(5)
++#define CCCR_CCE BIT(1)
++#define CCCR_INIT BIT(0)
++
++/* Bit Timing & Prescaler Register (BTP) */
++#define BTR_BRP_MASK 0x3ff
++#define BTR_BRP_SHIFT 16
++#define BTR_TSEG1_SHIFT 8
++#define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT)
++#define BTR_TSEG2_SHIFT 4
++#define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT)
++#define BTR_SJW_SHIFT 0
++#define BTR_SJW_MASK 0xf
++
++/* Error Counter Register(ECR) */
++#define ECR_RP BIT(15)
++#define ECR_REC_SHIFT 8
++#define ECR_REC_MASK (0x7f << ECR_REC_SHIFT)
++#define ECR_TEC_SHIFT 0
++#define ECR_TEC_MASK 0xff
++
++/* Protocol Status Register(PSR) */
++#define PSR_BO BIT(7)
++#define PSR_EW BIT(6)
++#define PSR_EP BIT(5)
++#define PSR_LEC_MASK 0x7
++
++/* Interrupt Register(IR) */
++#define IR_ALL_INT 0xffffffff
++#define IR_STE BIT(31)
++#define IR_FOE BIT(30)
++#define IR_ACKE BIT(29)
++#define IR_BE BIT(28)
++#define IR_CRCE BIT(27)
++#define IR_WDI BIT(26)
++#define IR_BO BIT(25)
++#define IR_EW BIT(24)
++#define IR_EP BIT(23)
++#define IR_ELO BIT(22)
++#define IR_BEU BIT(21)
++#define IR_BEC BIT(20)
++#define IR_DRX BIT(19)
++#define IR_TOO BIT(18)
++#define IR_MRAF BIT(17)
++#define IR_TSW BIT(16)
++#define IR_TEFL BIT(15)
++#define IR_TEFF BIT(14)
++#define IR_TEFW BIT(13)
++#define IR_TEFN BIT(12)
++#define IR_TFE BIT(11)
++#define IR_TCF BIT(10)
++#define IR_TC BIT(9)
++#define IR_HPM BIT(8)
++#define IR_RF1L BIT(7)
++#define IR_RF1F BIT(6)
++#define IR_RF1W BIT(5)
++#define IR_RF1N BIT(4)
++#define IR_RF0L BIT(3)
++#define IR_RF0F BIT(2)
++#define IR_RF0W BIT(1)
++#define IR_RF0N BIT(0)
++#define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
++#define IR_ERR_BUS (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE | \
++ IR_WDI | IR_ELO | IR_BEU | IR_BEC | IR_TOO | IR_MRAF | \
++ IR_TSW | IR_TEFL | IR_RF1L | IR_RF0L)
++#define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS)
++
++/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
++#define RXFC_FWM_OFF 24
++#define RXFC_FWM_MASK 0x7f
++#define RXFC_FWM_1 (1 << RXFC_FWM_OFF)
++#define RXFC_FS_OFF 16
++#define RXFC_FS_MASK 0x7f
++
++/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
++#define RXFS_RFL BIT(25)
++#define RXFS_FF BIT(24)
++#define RXFS_FPI_OFF 16
++#define RXFS_FPI_MASK 0x3f0000
++#define RXFS_FGI_OFF 8
++#define RXFS_FGI_MASK 0x3f00
++#define RXFS_FFL_MASK 0x7f
++
++/* Tx Buffer Configuration(TXBC) */
++#define TXBC_NDTB_OFF 16
++#define TXBC_NDTB_MASK 0x3f
++
++/* Tx Buffer Element Size Configuration(TXESC) */
++#define TXESC_TBDS_8BYTES 0x0
++/* Tx Buffer Element */
++#define TX_BUF_XTD BIT(30)
++#define TX_BUF_RTR BIT(29)
++
++/* Rx Buffer Element Size Configuration(TXESC) */
++#define M_CAN_RXESC_8BYTES 0x0
++/* Tx Buffer Element */
++#define RX_BUF_ESI BIT(31)
++#define RX_BUF_XTD BIT(30)
++#define RX_BUF_RTR BIT(29)
++
++/* Message RAM Configuration (in bytes) */
++#define SIDF_ELEMENT_SIZE 4
++#define XIDF_ELEMENT_SIZE 8
++#define RXF0_ELEMENT_SIZE 16
++#define RXF1_ELEMENT_SIZE 16
++#define RXB_ELEMENT_SIZE 16
++#define TXE_ELEMENT_SIZE 8
++#define TXB_ELEMENT_SIZE 16
++
++/* m_can private data structure */
++struct m_can_priv {
++ struct can_priv can; /* must be the first member */
++ struct napi_struct napi;
++ struct net_device *dev;
++ struct device *device;
++ struct clk *clk;
++ void __iomem *base;
++ u32 irqstatus;
++
++ /* message ram configuration */
++ void __iomem *mram_base;
++ u32 mram_off;
++ u32 sidf_elems;
++ u32 sidf_off;
++ u32 xidf_elems;
++ u32 xidf_off;
++ u32 rxf0_elems;
++ u32 rxf0_off;
++ u32 rxf1_elems;
++ u32 rxf1_off;
++ u32 rxb_elems;
++ u32 rxb_off;
++ u32 txe_elems;
++ u32 txe_off;
++ u32 txb_elems;
++ u32 txb_off;
++};
++
++static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
++{
++ return readl(priv->base + reg);
++}
++
++static inline void m_can_write(const struct m_can_priv *priv,
++ enum m_can_reg reg, u32 val)
++{
++ writel(val, priv->base + reg);
++}
++
++static inline void m_can_config_endisable(const struct m_can_priv *priv,
++ bool enable)
++{
++ u32 cccr = m_can_read(priv, M_CAN_CCCR);
++ u32 timeout = 10, val;
++
++ if (enable) {
++ /* enable m_can configuration */
++ m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
++ /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
++ m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
++ } else {
++ m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
++ }
++
++ /* there's a delay for module initialization */
++ val = enable ? CCCR_INIT | CCCR_CCE : 0;
++ while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE))
++ != val) {
++ if (timeout == 0) {
++ netdev_warn(priv->dev, "Failed to init module\n");
++ return;
++ }
++ timeout--;
++ udelay(1);
++ }
++}
++
++static void m_can_enable_all_interrupts(struct m_can_priv *priv, bool enable)
++{
++ m_can_write(priv, M_CAN_ILE, enable ? 0x00000003 : 0x0);
++}
++
++static int m_can_do_rx_poll(struct net_device *dev, int quota)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++ struct net_device_stats *stats = &dev->stats;
++ struct sk_buff *skb;
++ struct can_frame *frame;
++ u32 rxfs, flags, fgi;
++ u32 num_rx_pkts = 0;
++
++ rxfs = m_can_read(priv, M_CAN_RXF0S);
++ if (!(rxfs & RXFS_FFL_MASK)) {
++ netdev_dbg(dev, "no messages in fifo0\n");
++ return 0;
++ }
++
++ while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
++ netdev_dbg(dev, "fifo0 status 0x%x\n", rxfs);
++ if (rxfs & RXFS_RFL)
++ netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
++
++ skb = alloc_can_skb(dev, &frame);
++ if (!skb) {
++ stats->rx_dropped++;
++ return -ENOMEM;
++ }
++
++ fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
++ flags = readl(priv->mram_base + priv->rxf0_off + fgi * 16);
++ if (flags & RX_BUF_XTD)
++ frame->can_id = (flags & CAN_EFF_MASK) | CAN_EFF_FLAG;
++ else
++ frame->can_id = (flags >> 18) & CAN_SFF_MASK;
++ netdev_dbg(dev, "R0 0x%x\n", flags);
++
++ if (flags & RX_BUF_RTR) {
++ frame->can_id |= CAN_RTR_FLAG;
++ } else {
++ flags = readl(priv->mram_base +
++ priv->rxf0_off + fgi * 16 + 0x4);
++ frame->can_dlc = get_can_dlc((flags >> 16) & 0x0F);
++ netdev_dbg(dev, "R1 0x%x\n", flags);
++
++ *(u32 *)(frame->data + 0) = readl(priv->mram_base +
++ priv->rxf0_off + fgi * 16 + 0x8);
++ *(u32 *)(frame->data + 4) = readl(priv->mram_base +
++ priv->rxf0_off + fgi * 16 + 0xC);
++ netdev_dbg(dev, "R2 0x%x\n", *(u32 *)(frame->data + 0));
++ netdev_dbg(dev, "R3 0x%x\n", *(u32 *)(frame->data + 4));
++ }
++
++ /* acknowledge rx fifo 0 */
++ m_can_write(priv, M_CAN_RXF0A, fgi);
++
++ netif_receive_skb(skb);
++ netdev_dbg(dev, "new packet received\n");
++
++ stats->rx_packets++;
++ stats->rx_bytes += frame->can_dlc;
++
++ can_led_event(dev, CAN_LED_EVENT_RX);
++
++ quota--;
++ num_rx_pkts++;
++ rxfs = m_can_read(priv, M_CAN_RXF0S);
++ };
++
++ return num_rx_pkts;
++}
++
++static int m_can_handle_lost_msg(struct net_device *dev)
++{
++ struct net_device_stats *stats = &dev->stats;
++ struct sk_buff *skb;
++ struct can_frame *frame;
++
++ netdev_err(dev, "msg lost in rxf0\n");
++
++ skb = alloc_can_err_skb(dev, &frame);
++ if (unlikely(!skb))
++ return 0;
++
++ frame->can_id |= CAN_ERR_CRTL;
++ frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
++ stats->rx_errors++;
++ stats->rx_over_errors++;
++
++ netif_receive_skb(skb);
++
++ return 1;
++}
++
++static int m_can_handle_bus_err(struct net_device *dev,
++ enum m_can_lec_type lec_type)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++ struct net_device_stats *stats = &dev->stats;
++ struct can_frame *cf;
++ struct sk_buff *skb;
++
++ /* early exit if no lec update */
++ if (lec_type == LEC_UNUSED)
++ return 0;
++
++ /* propagate the error condition to the CAN stack */
++ skb = alloc_can_err_skb(dev, &cf);
++ if (unlikely(!skb))
++ return 0;
++
++ /*
++ * check for 'last error code' which tells us the
++ * type of the last error to occur on the CAN bus
++ */
++ priv->can.can_stats.bus_error++;
++ stats->rx_errors++;
++ cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
++ cf->data[2] |= CAN_ERR_PROT_UNSPEC;
++
++ switch (lec_type) {
++ case LEC_STUFF_ERROR:
++ netdev_dbg(dev, "stuff error\n");
++ cf->data[2] |= CAN_ERR_PROT_STUFF;
++ break;
++ case LEC_FORM_ERROR:
++ netdev_dbg(dev, "form error\n");
++ cf->data[2] |= CAN_ERR_PROT_FORM;
++ break;
++ case LEC_ACK_ERROR:
++ netdev_dbg(dev, "ack error\n");
++ cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
++ CAN_ERR_PROT_LOC_ACK_DEL);
++ break;
++ case LEC_BIT1_ERROR:
++ netdev_dbg(dev, "bit1 error\n");
++ cf->data[2] |= CAN_ERR_PROT_BIT1;
++ break;
++ case LEC_BIT0_ERROR:
++ netdev_dbg(dev, "bit0 error\n");
++ cf->data[2] |= CAN_ERR_PROT_BIT0;
++ break;
++ case LEC_CRC_ERROR:
++ netdev_dbg(dev, "CRC error\n");
++ cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
++ CAN_ERR_PROT_LOC_CRC_DEL);
++ break;
++ default:
++ break;
++ }
++
++ netif_receive_skb(skb);
++ stats->rx_packets++;
++ stats->rx_bytes += cf->can_dlc;
++
++ return 1;
++}
++
++static int m_can_get_berr_counter(const struct net_device *dev,
++ struct can_berr_counter *bec)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++ unsigned int ecr;
++
++ ecr = m_can_read(priv, M_CAN_ECR);
++ bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
++ bec->txerr = ecr & ECR_TEC_MASK;
++
++ return 0;
++}
++
++static int m_can_handle_state_change(struct net_device *dev,
++ enum can_state new_state)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++ struct net_device_stats *stats = &dev->stats;
++ struct can_frame *cf;
++ struct sk_buff *skb;
++ struct can_berr_counter bec;
++ unsigned int ecr;
++
++ /* propagate the error condition to the CAN stack */
++ skb = alloc_can_err_skb(dev, &cf);
++ if (unlikely(!skb))
++ return 0;
++
++ m_can_get_berr_counter(dev, &bec);
++
++ switch (new_state) {
++ case CAN_STATE_ERROR_ACTIVE:
++ /* error warning state */
++ priv->can.can_stats.error_warning++;
++ priv->can.state = CAN_STATE_ERROR_WARNING;
++ cf->can_id |= CAN_ERR_CRTL;
++ cf->data[1] = (bec.txerr > bec.rxerr) ?
++ CAN_ERR_CRTL_TX_WARNING :
++ CAN_ERR_CRTL_RX_WARNING;
++ cf->data[6] = bec.txerr;
++ cf->data[7] = bec.rxerr;
++ break;
++ case CAN_STATE_ERROR_PASSIVE:
++ /* error passive state */
++ priv->can.can_stats.error_passive++;
++ priv->can.state = CAN_STATE_ERROR_PASSIVE;
++ cf->can_id |= CAN_ERR_CRTL;
++ ecr = m_can_read(priv, M_CAN_ECR);
++ if (ecr & ECR_RP)
++ cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
++ if (bec.txerr > 127)
++ cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
++ cf->data[6] = bec.txerr;
++ cf->data[7] = bec.rxerr;
++ break;
++ case CAN_STATE_BUS_OFF:
++ /* bus-off state */
++ priv->can.state = CAN_STATE_BUS_OFF;
++ cf->can_id |= CAN_ERR_BUSOFF;
++ /*
++ * disable all interrupts in bus-off mode to ensure that
++ * the CPU is not hogged down
++ */
++ m_can_enable_all_interrupts(priv, false);
++ can_bus_off(dev);
++ break;
++ default:
++ break;
++ }
++
++ netif_receive_skb(skb);
++ stats->rx_packets++;
++ stats->rx_bytes += cf->can_dlc;
++
++ return 1;
++}
++
++static int m_can_poll(struct napi_struct *napi, int quota)
++{
++ struct net_device *dev = napi->dev;
++ struct m_can_priv *priv = netdev_priv(dev);
++ u32 work_done = 0;
++ u32 irqstatus, psr;
++
++ irqstatus = m_can_read(priv, M_CAN_IR);
++ if (irqstatus)
++ netdev_dbg(dev, "irqstatus updated! new 0x%x old 0x%x rxf0s 0x%x\n",
++ irqstatus, priv->irqstatus,
++ m_can_read(priv, M_CAN_RXF0S));
++
++ irqstatus = irqstatus | priv->irqstatus;
++ if (!irqstatus)
++ goto end;
++
++ psr = m_can_read(priv, M_CAN_PSR);
++ if (irqstatus & IR_ERR_STATE) {
++ if ((psr & PSR_EW) &&
++ (priv->can.state != CAN_STATE_ERROR_WARNING)) {
++ netdev_dbg(dev, "entered error warning state\n");
++ work_done += m_can_handle_state_change(dev,
++ CAN_STATE_ERROR_WARNING);
++ }
++
++ if ((psr & PSR_EP) &&
++ (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
++ netdev_dbg(dev, "entered error warning state\n");
++ work_done += m_can_handle_state_change(dev,
++ CAN_STATE_ERROR_PASSIVE);
++ }
++
++ if ((psr & PSR_BO) &&
++ (priv->can.state != CAN_STATE_BUS_OFF)) {
++ netdev_dbg(dev, "entered error warning state\n");
++ work_done += m_can_handle_state_change(dev,
++ CAN_STATE_BUS_OFF);
++ }
++ }
++
++ if (irqstatus & IR_ERR_BUS) {
++ if (irqstatus & IR_RF0L)
++ work_done += m_can_handle_lost_msg(dev);
++
++ /* handle lec errors on the bus */
++ if (psr & LEC_UNUSED)
++ work_done += m_can_handle_bus_err(dev,
++ psr & LEC_UNUSED);
++
++ /* other unproccessed error interrupts */
++ if (irqstatus & IR_WDI)
++ netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
++ if (irqstatus & IR_TOO)
++ netdev_err(dev, "Timeout reached\n");
++ if (irqstatus & IR_MRAF)
++ netdev_err(dev, "Message RAM access failure occurred\n");
++ }
++
++ if (irqstatus & IR_RF0N)
++ /* handle events corresponding to receive message objects */
++ work_done += m_can_do_rx_poll(dev, (quota - work_done));
++
++ if (work_done < quota) {
++ napi_complete(napi);
++ /* enable all IRQs */
++ m_can_enable_all_interrupts(priv, true);
++ }
++
++end:
++ return work_done;
++}
++
++static irqreturn_t m_can_isr(int irq, void *dev_id)
++{
++ struct net_device *dev = (struct net_device *)dev_id;
++ struct m_can_priv *priv = netdev_priv(dev);
++ struct net_device_stats *stats = &dev->stats;
++ u32 ir;
++
++ ir = m_can_read(priv, M_CAN_IR);
++ if (!ir)
++ return IRQ_NONE;
++
++ netdev_dbg(dev, "ir 0x%x rxfs0 0x%x\n", ir,
++ m_can_read(priv, M_CAN_RXF0S));
++
++ /* ACK all irqs */
++ if (ir & IR_ALL_INT)
++ m_can_write(priv, M_CAN_IR, ir);
++
++ /*
++ * schedule NAPI in case of
++ * - rx IRQ
++ * - state change IRQ
++ * - bus error IRQ and bus error reporting
++ */
++ if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
++ priv->irqstatus = ir;
++ m_can_enable_all_interrupts(priv, false);
++ napi_schedule(&priv->napi);
++ }
++
++ /* transmission complete interrupt */
++ if (ir & IR_TC) {
++ netdev_dbg(dev, "tx complete\n");
++ stats->tx_bytes += can_get_echo_skb(dev, 0);
++ stats->tx_packets++;
++ can_led_event(dev, CAN_LED_EVENT_TX);
++ netif_wake_queue(dev);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static const struct can_bittiming_const m_can_bittiming_const = {
++ .name = KBUILD_MODNAME,
++ .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
++ .tseg1_max = 64,
++ .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
++ .tseg2_max = 16,
++ .sjw_max = 16,
++ .brp_min = 1,
++ .brp_max = 1024,
++ .brp_inc = 1,
++};
++
++static int m_can_set_bittiming(struct net_device *dev)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++ const struct can_bittiming *bt = &priv->can.bittiming;
++ u16 brp, sjw, tseg1, tseg2;
++ u32 reg_btp;
++
++ brp = bt->brp - 1;
++ sjw = bt->sjw - 1;
++ tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
++ tseg2 = bt->phase_seg2 - 1;
++ reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
++ (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
++ m_can_write(priv, M_CAN_BTP, reg_btp);
++ netdev_dbg(dev, "setting BTP 0x%x\n", reg_btp);
++
++ return 0;
++}
++
++/*
++ * Configure M_CAN chip:
++ * - set rx buffer/fifo element size
++ * - configure rx fifo
++ * - accept non-matching frame into fifo 0
++ * - configure tx buffer
++ * - configure mode
++ * - setup bittiming
++ */
++static void m_can_chip_config(struct net_device *dev)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++ u32 cccr, test;
++
++ m_can_config_endisable(priv, true);
++
++ /* RX Buffer/FIFO Element Size 8 bytes data field */
++ m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_8BYTES);
++
++ /* Accept Non-matching Frames Into FIFO 0 */
++ m_can_write(priv, M_CAN_GFC, 0x0);
++
++ /* only support one Tx Buffer currently */
++ m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) | priv->txb_off);
++
++ /* only support 8 bytes firstly */
++ m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_8BYTES);
++
++ m_can_write(priv, M_CAN_TXEFC, 0x00010000 | priv->txe_off);
++
++ /* rx fifo configuration, blocking mode, fifo size 1 */
++ m_can_write(priv, M_CAN_RXF0C, (priv->rxf0_elems << RXFC_FS_OFF) |
++ RXFC_FWM_1 | priv->rxf0_off);
++
++ m_can_write(priv, M_CAN_RXF1C, (priv->rxf1_elems << RXFC_FS_OFF) |
++ RXFC_FWM_1 | priv->rxf1_off);
++
++ cccr = m_can_read(priv, M_CAN_CCCR);
++ cccr &= ~(CCCR_TEST | CCCR_MON);
++ test = m_can_read(priv, M_CAN_TEST);
++ test &= ~TEST_LBCK;
++
++ if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
++ cccr |= CCCR_MON;
++
++ if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
++ cccr |= CCCR_TEST;
++ test |= TEST_LBCK;
++ }
++
++ m_can_write(priv, M_CAN_CCCR, cccr);
++ m_can_write(priv, M_CAN_TEST, test);
++
++ /* enable all interrupts */
++ m_can_write(priv, M_CAN_IR, IR_ALL_INT);
++ m_can_write(priv, M_CAN_IE, IR_ALL_INT);
++ m_can_write(priv, M_CAN_ILS, 0xFFFF0000);
++
++ /* set bittiming params */
++ m_can_set_bittiming(dev);
++
++ m_can_config_endisable(priv, false);
++}
++
++static void m_can_start(struct net_device *dev)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++
++ /* basic m_can configuration */
++ m_can_chip_config(dev);
++
++ priv->can.state = CAN_STATE_ERROR_ACTIVE;
++
++ /* enable status change, error and module interrupts */
++ m_can_enable_all_interrupts(priv, true);
++}
++
++static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
++{
++ switch (mode) {
++ case CAN_MODE_START:
++ m_can_start(dev);
++ netif_wake_queue(dev);
++ break;
++ default:
++ return -EOPNOTSUPP;
++ }
++
++ return 0;
++}
++
++static void free_m_can_dev(struct net_device *dev)
++{
++ free_candev(dev);
++}
++
++static struct net_device *alloc_m_can_dev(void)
++{
++ struct net_device *dev;
++ struct m_can_priv *priv;
++
++ dev = alloc_candev(sizeof(struct m_can_priv), 1);
++ if (!dev)
++ return NULL;
++
++ priv = netdev_priv(dev);
++ netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
++
++ priv->dev = dev;
++ priv->can.bittiming_const = &m_can_bittiming_const;
++ priv->can.do_set_mode = m_can_set_mode;
++ priv->can.do_get_berr_counter = m_can_get_berr_counter;
++ priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
++ CAN_CTRLMODE_LISTENONLY |
++ CAN_CTRLMODE_BERR_REPORTING;
++
++ return dev;
++}
++
++
++static int m_can_open(struct net_device *dev)
++{
++ int err;
++ struct m_can_priv *priv = netdev_priv(dev);
++
++ clk_prepare_enable(priv->clk);
++
++ /* open the can device */
++ err = open_candev(dev);
++ if (err) {
++ netdev_err(dev, "failed to open can device\n");
++ goto exit_open_fail;
++ }
++
++ /* register interrupt handler */
++ err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
++ dev);
++ if (err < 0) {
++ netdev_err(dev, "failed to request interrupt\n");
++ goto exit_irq_fail;
++ }
++
++ /* start the m_can controller */
++ m_can_start(dev);
++
++ can_led_event(dev, CAN_LED_EVENT_OPEN);
++ napi_enable(&priv->napi);
++ netif_start_queue(dev);
++
++ return 0;
++
++exit_irq_fail:
++ close_candev(dev);
++exit_open_fail:
++ clk_disable_unprepare(priv->clk);
++ return err;
++}
++
++static void m_can_stop(struct net_device *dev)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++
++ /* disable all interrupts */
++ m_can_enable_all_interrupts(priv, false);
++
++ /* set the state as STOPPED */
++ priv->can.state = CAN_STATE_STOPPED;
++}
++
++
++static int m_can_close(struct net_device *dev)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++
++ netif_stop_queue(dev);
++ napi_disable(&priv->napi);
++ m_can_stop(dev);
++ free_irq(dev->irq, dev);
++ close_candev(dev);
++ can_led_event(dev, CAN_LED_EVENT_STOP);
++
++ return 0;
++}
++
++static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
++ struct net_device *dev)
++{
++ struct m_can_priv *priv = netdev_priv(dev);
++ struct can_frame *frame = (struct can_frame *)skb->data;
++ u32 flags = 0, id;
++
++ if (can_dropped_invalid_skb(dev, skb))
++ return NETDEV_TX_OK;
++
++ netif_stop_queue(dev);
++
++ if (frame->can_id & CAN_RTR_FLAG)
++ flags |= TX_BUF_RTR;
++
++ if (frame->can_id & CAN_EFF_FLAG) {
++ id = frame->can_id & CAN_EFF_MASK;
++ flags |= TX_BUF_XTD;
++ } else {
++ id = ((frame->can_id & CAN_SFF_MASK) << 18);
++ }
++
++ /* message ram configuration */
++ writel(id | flags, priv->mram_base + priv->txb_off);
++ writel(frame->can_dlc << 16, priv->mram_base + priv->txb_off + 0x4);
++ writel(*(u32 *)(frame->data + 0),
++ priv->mram_base + priv->txb_off + 0x8);
++ writel(*(u32 *)(frame->data + 4),
++ priv->mram_base + priv->txb_off + 0xc);
++
++ can_put_echo_skb(skb, dev, 0);
++
++ /* enable first TX buffer to start transfer */
++ m_can_write(priv, M_CAN_TXBTIE, 0x00000001);
++ m_can_write(priv, M_CAN_TXBAR, 0x00000001);
++
++ return NETDEV_TX_OK;
++}
++
++static const struct net_device_ops m_can_netdev_ops = {
++ .ndo_open = m_can_open,
++ .ndo_stop = m_can_close,
++ .ndo_start_xmit = m_can_start_xmit,
++};
++
++static int register_m_can_dev(struct net_device *dev)
++{
++ dev->flags |= IFF_ECHO; /* we support local echo */
++ dev->netdev_ops = &m_can_netdev_ops;
++
++ return register_candev(dev);
++}
++
++static const struct of_device_id m_can_of_table[] = {
++ { .compatible = "bosch,m_can", .data = NULL },
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, m_can_of_table);
++
++static int m_can_of_parse_mram(struct platform_device *pdev,
++ struct m_can_priv *priv)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct resource *res;
++ void __iomem *addr;
++ u32 out_val[8];
++ int ret;
++
++ /* message ram could be shared */
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
++ if (!res)
++ return -ENODEV;
++
++ addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
++ if (!addr)
++ return -ENODEV;
++
++ /* get message ram configuration */
++ ret = of_property_read_u32_array(np, "mram-cfg",
++ out_val, sizeof(out_val) / 4);
++ if (ret) {
++ dev_err(&pdev->dev, "can not get message ram configuration\n");
++ return -ENODEV;
++ }
++
++ priv->mram_base = addr;
++ priv->mram_off = out_val[0];
++ priv->sidf_elems = out_val[1];
++ priv->sidf_off = priv->mram_off;
++ priv->xidf_elems = out_val[2];
++ priv->xidf_off = priv->sidf_off + priv->sidf_elems * SIDF_ELEMENT_SIZE;
++ priv->rxf0_elems = out_val[3] & RXFC_FS_MASK;
++ priv->rxf0_off = priv->xidf_off + priv->xidf_elems * XIDF_ELEMENT_SIZE;
++ priv->rxf1_elems = out_val[4] & RXFC_FS_MASK;
++ priv->rxf1_off = priv->rxf0_off + priv->rxf0_elems * RXF0_ELEMENT_SIZE;
++ priv->rxb_elems = out_val[5];
++ priv->rxb_off = priv->rxf1_off + priv->rxf1_elems * RXF1_ELEMENT_SIZE;
++ priv->txe_elems = out_val[6];
++ priv->txe_off = priv->rxb_off + priv->rxb_elems * RXB_ELEMENT_SIZE;
++ priv->txb_elems = out_val[7] & TXBC_NDTB_MASK;
++ priv->txb_off = priv->txe_off + priv->txe_elems * TXE_ELEMENT_SIZE;
++
++ dev_dbg(&pdev->dev, "mram_base =%p mram_off =0x%x "
++ "sidf %d xidf %d rxf0 %d rxf1 %d rxb %d txe %d txb %d\n",
++ priv->mram_base, priv->mram_off, priv->sidf_elems,
++ priv->xidf_elems, priv->rxf0_elems, priv->rxf1_elems,
++ priv->rxb_elems, priv->txe_elems, priv->txb_elems);
++
++ return 0;
++}
++
++static int m_can_plat_probe(struct platform_device *pdev)
++{
++ struct net_device *dev;
++ struct m_can_priv *priv;
++ struct pinctrl *pinctrl;
++ struct resource *res;
++ void __iomem *addr;
++ struct clk *clk;
++ int irq, ret;
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl))
++ dev_warn(&pdev->dev,
++ "failed to configure pins from driver\n");
++
++ clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(clk)) {
++ dev_err(&pdev->dev, "no clock find\n");
++ return PTR_ERR(clk);
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "canfd");
++ addr = devm_request_and_ioremap(&pdev->dev, res);
++ irq = platform_get_irq(pdev, 0);
++ if (!addr || irq < 0)
++ return -EINVAL;
++
++ /* allocate the m_can device */
++ dev = alloc_m_can_dev();
++ if (!dev)
++ return -ENOMEM;
++
++ priv = netdev_priv(dev);
++ dev->irq = irq;
++ priv->base = addr;
++ priv->device = &pdev->dev;
++ priv->clk = clk;
++ priv->can.clock.freq = clk_get_rate(clk);
++
++ ret = m_can_of_parse_mram(pdev, priv);
++ if (ret)
++ goto failed_free_dev;
++
++ platform_set_drvdata(pdev, dev);
++ SET_NETDEV_DEV(dev, &pdev->dev);
++
++ ret = register_m_can_dev(dev);
++ if (ret) {
++ dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
++ KBUILD_MODNAME, ret);
++ goto failed_free_dev;
++ }
++
++ devm_can_led_init(dev);
++
++ dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
++ KBUILD_MODNAME, priv->base, dev->irq);
++
++ return 0;
++
++failed_free_dev:
++ free_m_can_dev(dev);
++ return ret;
++}
++
++#ifdef CONFIG_PM
++static int m_can_suspend(struct device *dev)
++{
++ struct net_device *ndev = dev_get_drvdata(dev);
++ struct m_can_priv *priv = netdev_priv(ndev);
++
++ if (netif_running(ndev)) {
++ netif_stop_queue(ndev);
++ netif_device_detach(ndev);
++ }
++
++ /* TODO: enter low power */
++
++ priv->can.state = CAN_STATE_SLEEPING;
++
++ return 0;
++}
++
++static int m_can_resume(struct device *dev)
++{
++ struct net_device *ndev = dev_get_drvdata(dev);
++ struct m_can_priv *priv = netdev_priv(ndev);
++
++ /* TODO: exit low power */
++
++ priv->can.state = CAN_STATE_ERROR_ACTIVE;
++
++ if (netif_running(ndev)) {
++ netif_device_attach(ndev);
++ netif_start_queue(ndev);
++ }
++
++ return 0;
++}
++#endif
++
++static void unregister_m_can_dev(struct net_device *dev)
++{
++ unregister_candev(dev);
++}
++
++static int m_can_plat_remove(struct platform_device *pdev)
++{
++ struct net_device *dev = platform_get_drvdata(pdev);
++
++ unregister_m_can_dev(dev);
++ platform_set_drvdata(pdev, NULL);
++
++ free_m_can_dev(dev);
++
++ return 0;
++}
++
++static const struct dev_pm_ops m_can_pmops = {
++ SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
++};
++
++static struct platform_driver m_can_plat_driver = {
++ .driver = {
++ .name = KBUILD_MODNAME,
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(m_can_of_table),
++ .pm = &m_can_pmops,
++ },
++ .probe = m_can_plat_probe,
++ .remove = m_can_plat_remove,
++};
++
++module_platform_driver(m_can_plat_driver);
++
++MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/adi/bfin_mac.c linux-3.14.72/drivers/net/ethernet/adi/bfin_mac.c
+--- linux-3.14.72.orig/drivers/net/ethernet/adi/bfin_mac.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/adi/bfin_mac.c 2016-06-19 22:11:55.261142894 +0200
+@@ -1040,6 +1040,7 @@
+ .n_alarm = 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = bfin_ptp_adjfreq,
+ .adjtime = bfin_ptp_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/broadcom/tg3.c linux-3.14.72/drivers/net/ethernet/broadcom/tg3.c
+--- linux-3.14.72.orig/drivers/net/ethernet/broadcom/tg3.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/broadcom/tg3.c 2016-06-19 22:11:55.265142632 +0200
+@@ -6322,6 +6322,7 @@
+ .n_alarm = 0,
+ .n_ext_ts = 0,
+ .n_per_out = 1,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = tg3_ptp_adjfreq,
+ .adjtime = tg3_ptp_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/freescale/fec.h linux-3.14.72/drivers/net/ethernet/freescale/fec.h
+--- linux-3.14.72.orig/drivers/net/ethernet/freescale/fec.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/freescale/fec.h 2016-06-19 22:11:55.265142632 +0200
+@@ -27,8 +27,8 @@
+ */
+ #define FEC_IEVENT 0x004 /* Interrupt event reg */
+ #define FEC_IMASK 0x008 /* Interrupt mask reg */
+-#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
+-#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
++#define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
++#define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
+ #define FEC_ECNTRL 0x024 /* Ethernet control reg */
+ #define FEC_MII_DATA 0x040 /* MII manage frame reg */
+ #define FEC_MII_SPEED 0x044 /* MII speed control reg */
+@@ -38,6 +38,12 @@
+ #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
+ #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
+ #define FEC_OPD 0x0ec /* Opcode + Pause duration */
++#define FEC_TXIC0 0xF0 /* Tx Interrupt Coalescing for ring 0 */
++#define FEC_TXIC1 0xF4 /* Tx Interrupt Coalescing for ring 1 */
++#define FEC_TXIC2 0xF8 /* Tx Interrupt Coalescing for ring 2 */
++#define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */
++#define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */
++#define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */
+ #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
+ #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */
+ #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */
+@@ -45,14 +51,29 @@
+ #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */
+ #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */
+ #define FEC_R_FSTART 0x150 /* FIFO receive start reg */
+-#define FEC_R_DES_START 0x180 /* Receive descriptor ring */
+-#define FEC_X_DES_START 0x184 /* Transmit descriptor ring */
+-#define FEC_R_BUFF_SIZE 0x188 /* Maximum receive buff size */
++#define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */
++#define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */
++#define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */
++#define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */
++#define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */
++#define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */
++#define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */
++#define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */
++#define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */
+ #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */
+ #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */
+ #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */
+ #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */
+ #define FEC_RACC 0x1C4 /* Receive Accelerator function */
++#define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */
++#define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */
++#define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */
++#define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */
++#define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */
++#define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */
++#define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */
++#define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */
++#define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */
+ #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */
+ #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */
+
+@@ -121,8 +142,12 @@
+ #define FEC_IEVENT 0x004 /* Interrupt even reg */
+ #define FEC_IMASK 0x008 /* Interrupt mask reg */
+ #define FEC_IVEC 0x00c /* Interrupt vec status reg */
+-#define FEC_R_DES_ACTIVE 0x010 /* Receive descriptor reg */
+-#define FEC_X_DES_ACTIVE 0x014 /* Transmit descriptor reg */
++#define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */
++#define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0
++#define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0
++#define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */
++#define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0
++#define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0
+ #define FEC_MII_DATA 0x040 /* MII manage frame reg */
+ #define FEC_MII_SPEED 0x044 /* MII speed control reg */
+ #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */
+@@ -136,11 +161,29 @@
+ #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */
+ #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */
+ #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */
+-#define FEC_R_DES_START 0x3d0 /* Receive descriptor ring */
+-#define FEC_X_DES_START 0x3d4 /* Transmit descriptor ring */
+-#define FEC_R_BUFF_SIZE 0x3d8 /* Maximum receive buff size */
++#define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */
++#define FEC_R_DES_START_1 FEC_R_DES_START_0
++#define FEC_R_DES_START_2 FEC_R_DES_START_0
++#define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */
++#define FEC_X_DES_START_1 FEC_X_DES_START_0
++#define FEC_X_DES_START_2 FEC_X_DES_START_0
++#define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */
++#define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0
++#define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0
+ #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */
+-
++/* Not existed in real chip
++ * Just for pass build.
++ */
++#define FEC_RCMR_1 0xFFF
++#define FEC_RCMR_2 0xFFF
++#define FEC_DMA_CFG_1 0xFFF
++#define FEC_DMA_CFG_2 0xFFF
++#define FEC_TXIC0 0xFFF
++#define FEC_TXIC1 0xFFF
++#define FEC_TXIC2 0xFFF
++#define FEC_RXIC0 0xFFF
++#define FEC_RXIC1 0xFFF
++#define FEC_RXIC2 0xFFF
+ #endif /* CONFIG_M5272 */
+
+
+@@ -202,6 +245,7 @@
+ #define BD_ENET_RX_OV ((ushort)0x0002)
+ #define BD_ENET_RX_CL ((ushort)0x0001)
+ #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
++#define BD_ENET_RX_ERROR ((ushort)0x003f)
+
+ /* Enhanced buffer descriptor control/status used by Ethernet receive */
+ #define BD_ENET_RX_VLAN 0x00000004
+@@ -221,7 +265,7 @@
+ #define BD_ENET_TX_RCMASK ((ushort)0x003c)
+ #define BD_ENET_TX_UN ((ushort)0x0002)
+ #define BD_ENET_TX_CSL ((ushort)0x0001)
+-#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
++#define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */
+
+ /*enhanced buffer descriptor control/status used by Ethernet transmit*/
+ #define BD_ENET_TX_INT 0x40000000
+@@ -233,6 +277,47 @@
+ /* This device has up to three irqs on some platforms */
+ #define FEC_IRQ_NUM 3
+
++/* Maximum number of queues supported
++ * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
++ * User can point the queue number that is less than or equal to 3.
++ */
++#define FEC_ENET_MAX_TX_QS 3
++#define FEC_ENET_MAX_RX_QS 3
++
++#define FEC_R_DES_START(X) ((X == 1) ? FEC_R_DES_START_1 : \
++ ((X == 2) ? \
++ FEC_R_DES_START_2 : FEC_R_DES_START_0))
++#define FEC_X_DES_START(X) ((X == 1) ? FEC_X_DES_START_1 : \
++ ((X == 2) ? \
++ FEC_X_DES_START_2 : FEC_X_DES_START_0))
++#define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \
++ (((X) == 2) ? \
++ FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0))
++#define FEC_R_DES_ACTIVE(X) ((X == 1) ? FEC_R_DES_ACTIVE_1 : \
++ ((X == 2) ? \
++ FEC_R_DES_ACTIVE_2 : FEC_R_DES_ACTIVE_0))
++#define FEC_X_DES_ACTIVE(X) ((X == 1) ? FEC_X_DES_ACTIVE_1 : \
++ ((X == 2) ? \
++ FEC_X_DES_ACTIVE_2 : FEC_X_DES_ACTIVE_0))
++
++#define FEC_DMA_CFG(X) ((X == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1)
++
++#define DMA_CLASS_EN (1 << 16)
++#define FEC_RCMR(X) ((X == 2) ? FEC_RCMR_2 : FEC_RCMR_1)
++#define IDLE_SLOPE_MASK 0xFFFF
++#define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */
++#define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */
++#define IDLE_SLOPE(X) ((X == 1) ? (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \
++ (IDLE_SLOPE_2 & IDLE_SLOPE_MASK))
++#define RCMR_MATCHEN (0x1 << 16)
++#define RCMR_CMP_CFG(v, n) ((v & 0x7) << (n << 2))
++#define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \
++ RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3))
++#define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \
++ RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3))
++#define RCMR_CMP(X) ((X == 1) ? RCMR_CMP_1 : RCMR_CMP_2)
++#define FEC_TX_BD_FTYPE(X) ((X & 0xF) << 20)
++
+ /* The number of Tx and Rx buffers. These are allocated from the page
+ * pool. The code may assume these are power of two, so it it best
+ * to keep them that size.
+@@ -240,14 +325,14 @@
+ * the skbuffer directly.
+ */
+
+-#define FEC_ENET_RX_PAGES 8
++#define FEC_ENET_RX_PAGES 256
+ #define FEC_ENET_RX_FRSIZE 2048
+ #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
+ #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
+ #define FEC_ENET_TX_FRSIZE 2048
+ #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
+-#define TX_RING_SIZE 16 /* Must be power of two */
+-#define TX_RING_MOD_MASK 15 /* for this to work */
++#define TX_RING_SIZE 512 /* Must be power of two */
++#define TX_RING_MOD_MASK 511 /* for this to work */
+
+ #define BD_ENET_RX_INT 0x00800000
+ #define BD_ENET_RX_PTP ((ushort)0x0400)
+@@ -256,10 +341,126 @@
+ #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
+ #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR)
+
+-struct fec_enet_delayed_work {
+- struct delayed_work delay_work;
+- bool timeout;
+- bool trig_tx;
++#define FEC0_MII_BUS_SHARE_TRUE 1
++
++/* Interrupt events/masks. */
++#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
++#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
++#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
++#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
++#define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */
++#define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */
++#define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */
++#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
++#define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */
++#define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */
++#define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */
++#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
++#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
++#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
++#define FEC_ENET_WAKEUP ((uint)0x00020000) /* Wakeup request */
++#define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2)
++#define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2)
++#define FEC_ENET_TS_AVAIL ((uint)0x00010000)
++#define FEC_ENET_TS_TIMER ((uint)0x00008000)
++
++#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | FEC_ENET_TS_TIMER)
++#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
++
++#define FEC_ENET_ETHEREN ((uint)0x00000002)
++
++/* ENET interrupt coalescing macro define */
++#define FEC_ITR_CLK_SEL (0x1 << 30)
++#define FEC_ITR_EN (0x1 << 31)
++#define FEC_ITR_ICFT(X) ((X & 0xFF) << 20)
++#define FEC_ITR_ICTT(X) ((X) & 0xFFFF)
++#define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */
++#define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */
++
++#define FEC_VLAN_TAG_LEN 0x04
++#define FEC_ETHTYPE_LEN 0x02
++
++/* Controller is ENET-MAC */
++#define FEC_QUIRK_ENET_MAC (1 << 0)
++/* Controller needs driver to swap frame */
++#define FEC_QUIRK_SWAP_FRAME (1 << 1)
++/* Controller uses gasket */
++#define FEC_QUIRK_USE_GASKET (1 << 2)
++/* Controller has GBIT support */
++#define FEC_QUIRK_HAS_GBIT (1 << 3)
++/* Controller has extend desc buffer */
++#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
++/* Controller has hardware checksum support */
++#define FEC_QUIRK_HAS_CSUM (1 << 5)
++/* Controller has hardware vlan support */
++#define FEC_QUIRK_HAS_VLAN (1 << 6)
++/* ENET IP errata ERR006358
++ *
++ * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
++ * detected as not set during a prior frame transmission, then the
++ * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
++ * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
++ * frames not being transmitted until there is a 0-to-1 transition on
++ * ENET_TDAR[TDAR].
++ */
++#define FEC_QUIRK_ERR006358 (1 << 7)
++/* ENET IP hw AVB
++ *
++ * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
++ * - Two class indicators on receive with configurable priority
++ * - Two class indicators and line speed timer on transmit allowing
++ * implementation class credit based shapers externally
++ * - Additional DMA registers provisioned to allow managing up to 3
++ * independent rings
++ */
++#define FEC_QUIRK_HAS_AVB (1 << 8)
++/*
++ * i.MX6Q/DL ENET cannot wake up system in wait mode because ENET tx & rx
++ * interrupt signal don't connect to GPC. So use pm qos to avoid cpu enter
++ * to wait mode.
++ */
++#define FEC_QUIRK_BUG_WAITMODE (1 << 9)
++/* There is a TDAR race condition for mutliQ when the software sets TDAR
++ * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
++ * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
++ * The issue exist at i.MX6SX enet IP.
++ */
++#define FEC_QUIRK_ERR007885 (1 << 10)
++/*
++ * Incorrect behavior for ENET_ATCR[Capture and Restart Bits].
++ * These bits will always read a value zero. According to SPEC, when these
++ * bits are set to 1'b1, these should hold value 1'b1 until the counter value
++ * is capture in the register clock domain.
++ */
++#define FEC_QUIRK_TKT210590 (1 << 11)
++
++struct fec_enet_priv_tx_q {
++ int index;
++ unsigned char *tx_bounce[TX_RING_SIZE];
++ struct sk_buff *tx_skbuff[TX_RING_SIZE];
++
++ dma_addr_t bd_dma;
++ struct bufdesc *tx_bd_base;
++ uint tx_ring_size;
++
++ unsigned short tx_stop_threshold;
++ unsigned short tx_wake_threshold;
++
++ struct bufdesc *cur_tx;
++ struct bufdesc *dirty_tx;
++ char *tso_hdrs;
++ dma_addr_t tso_hdrs_dma;
++};
++
++struct fec_enet_priv_rx_q {
++ int index;
++ struct sk_buff *rx_skbuff[RX_RING_SIZE];
++
++ dma_addr_t bd_dma;
++ struct bufdesc *rx_bd_base;
++ uint rx_ring_size;
++
++ struct bufdesc *cur_rx;
+ };
+
+ /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
+@@ -278,49 +479,56 @@
+
+ struct clk *clk_ipg;
+ struct clk *clk_ahb;
++ struct clk *clk_ref;
+ struct clk *clk_enet_out;
+ struct clk *clk_ptp;
+
++ bool ptp_clk_on;
++ struct mutex ptp_clk_mutex;
++ unsigned int num_tx_queues;
++ unsigned int num_rx_queues;
++
+ /* The saved address of a sent-in-place packet/buffer, for skfree(). */
+- unsigned char *tx_bounce[TX_RING_SIZE];
+- struct sk_buff *tx_skbuff[TX_RING_SIZE];
+- struct sk_buff *rx_skbuff[RX_RING_SIZE];
++ struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS];
++ struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS];
+
+- /* CPM dual port RAM relative addresses */
+- dma_addr_t bd_dma;
+- /* Address of Rx and Tx buffers */
+- struct bufdesc *rx_bd_base;
+- struct bufdesc *tx_bd_base;
+- /* The next free ring entry */
+- struct bufdesc *cur_rx, *cur_tx;
+- /* The ring entries to be free()ed */
+- struct bufdesc *dirty_tx;
++ unsigned int total_tx_ring_size;
++ unsigned int total_rx_ring_size;
+
+- unsigned short tx_ring_size;
+- unsigned short rx_ring_size;
++ unsigned long work_tx;
++ unsigned long work_rx;
++ unsigned long work_ts;
++ unsigned long work_mdio;
++
++ unsigned short bufdesc_size;
+
+ struct platform_device *pdev;
+
+- int opened;
+ int dev_id;
+
+ /* Phylib and MDIO interface */
+ struct mii_bus *mii_bus;
+ struct phy_device *phy_dev;
+ int mii_timeout;
++ int mii_bus_share;
+ uint phy_speed;
+ phy_interface_t phy_interface;
++ struct device_node *phy_node;
+ int link;
+ int full_duplex;
+ int speed;
+ struct completion mdio_done;
+ int irq[FEC_IRQ_NUM];
+- int bufdesc_ex;
++ bool bufdesc_ex;
+ int pause_flag;
++ int wol_flag;
++ u32 quirks;
+
+ struct napi_struct napi;
+ int csum_flags;
+
++ struct work_struct tx_timeout_work;
++
+ struct ptp_clock *ptp_clock;
+ struct ptp_clock_info ptp_caps;
+ unsigned long last_overflow_check;
+@@ -332,15 +540,36 @@
+ u32 cycle_speed;
+ int hwts_rx_en;
+ int hwts_tx_en;
+- struct timer_list time_keep;
+- struct fec_enet_delayed_work delay_work;
++ struct delayed_work time_keep;
+ struct regulator *reg_phy;
++
++ unsigned int tx_align;
++ unsigned int rx_align;
++
++ /* hw interrupt coalesce */
++ unsigned int rx_pkts_itr;
++ unsigned int rx_time_itr;
++ unsigned int tx_pkts_itr;
++ unsigned int tx_time_itr;
++ unsigned int itr_clk_rate;
++
++ u32 rx_copybreak;
++
++ /* ptp clock period in ns*/
++ unsigned int ptp_inc;
++
++ /* pps */
++ int pps_channel;
++ unsigned int reload_period;
++ int pps_enable;
++ unsigned int next_counter;
+ };
+
+ void fec_ptp_init(struct platform_device *pdev);
+ void fec_ptp_start_cyclecounter(struct net_device *ndev);
+ int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr);
+ int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr);
++uint fec_ptp_check_pps_event(struct fec_enet_private *fep);
+
+ /****************************************************************************/
+ #endif /* FEC_H */
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/freescale/fec_main.c linux-3.14.72/drivers/net/ethernet/freescale/fec_main.c
+--- linux-3.14.72.orig/drivers/net/ethernet/freescale/fec_main.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/freescale/fec_main.c 2016-06-19 22:11:55.265142632 +0200
+@@ -18,7 +18,7 @@
+ * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
+ * Copyright (c) 2004-2006 Macq Electronique SA.
+ *
+- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
++ * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
+ */
+
+ #include <linux/module.h>
+@@ -36,6 +36,7 @@
+ #include <linux/in.h>
+ #include <linux/ip.h>
+ #include <net/ip.h>
++#include <net/tso.h>
+ #include <linux/tcp.h>
+ #include <linux/udp.h>
+ #include <linux/icmp.h>
+@@ -51,24 +52,27 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/of_gpio.h>
++#include <linux/of_mdio.h>
+ #include <linux/of_net.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/if_vlan.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pm_runtime.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/prefetch.h>
+
+ #include <asm/cacheflush.h>
+
+ #include "fec.h"
+
+ static void set_multicast_list(struct net_device *ndev);
+-
+-#if defined(CONFIG_ARM)
+-#define FEC_ALIGNMENT 0xf
+-#else
+-#define FEC_ALIGNMENT 0x3
+-#endif
++static void fec_enet_itr_coal_init(struct net_device *ndev);
+
+ #define DRIVER_NAME "fec"
+
++#define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
++static const u16 fec_enet_vlan_pri_to_queue[8] = {1, 1, 1, 1, 2, 2, 2, 2};
++
+ /* Pause frame feild and FIFO threshold */
+ #define FEC_ENET_FCE (1 << 5)
+ #define FEC_ENET_RSEM_V 0x84
+@@ -77,31 +81,6 @@
+ #define FEC_ENET_RAFL_V 0x8
+ #define FEC_ENET_OPD_V 0xFFF0
+
+-/* Controller is ENET-MAC */
+-#define FEC_QUIRK_ENET_MAC (1 << 0)
+-/* Controller needs driver to swap frame */
+-#define FEC_QUIRK_SWAP_FRAME (1 << 1)
+-/* Controller uses gasket */
+-#define FEC_QUIRK_USE_GASKET (1 << 2)
+-/* Controller has GBIT support */
+-#define FEC_QUIRK_HAS_GBIT (1 << 3)
+-/* Controller has extend desc buffer */
+-#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
+-/* Controller has hardware checksum support */
+-#define FEC_QUIRK_HAS_CSUM (1 << 5)
+-/* Controller has hardware vlan support */
+-#define FEC_QUIRK_HAS_VLAN (1 << 6)
+-/* ENET IP errata ERR006358
+- *
+- * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
+- * detected as not set during a prior frame transmission, then the
+- * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
+- * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
+- * frames not being transmitted until there is a 0-to-1 transition on
+- * ENET_TDAR[TDAR].
+- */
+-#define FEC_QUIRK_ERR006358 (1 << 7)
+-
+ static struct platform_device_id fec_devtype[] = {
+ {
+ /* keep it for coldfire */
+@@ -120,11 +99,18 @@
+ .name = "imx6q-fec",
+ .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
+ FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
+- FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
++ FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
++ FEC_QUIRK_BUG_WAITMODE,
+ }, {
+ .name = "mvf600-fec",
+ .driver_data = FEC_QUIRK_ENET_MAC,
+ }, {
++ .name = "imx6sx-fec",
++ .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
++ FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
++ FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
++ FEC_QUIRK_ERR007885 | FEC_QUIRK_TKT210590,
++ }, {
+ /* sentinel */
+ }
+ };
+@@ -136,6 +122,7 @@
+ IMX28_FEC,
+ IMX6Q_FEC,
+ MVF600_FEC,
++ IMX6SX_FEC,
+ };
+
+ static const struct of_device_id fec_dt_ids[] = {
+@@ -144,6 +131,7 @@
+ { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
+ { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
+ { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
++ { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, fec_dt_ids);
+@@ -172,25 +160,6 @@
+ #endif
+ #endif /* CONFIG_M5272 */
+
+-#if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
+-#error "FEC: descriptor ring size constants too large"
+-#endif
+-
+-/* Interrupt events/masks. */
+-#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
+-#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
+-#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
+-#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
+-#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
+-#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
+-#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
+-#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
+-#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
+-#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
+-
+-#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
+-#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
+-
+ /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
+ */
+ #define PKT_MAXBUF_SIZE 1522
+@@ -222,6 +191,9 @@
+ #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
+ #define FEC_MMFR_TA (2 << 16)
+ #define FEC_MMFR_DATA(v) (v & 0xffff)
++/* FEC ECR bits definition */
++#define FEC_ECR_MAGICEN (1 << 2)
++#define FEC_ECR_SLEEP (1 << 3)
+
+ #define FEC_MII_TIMEOUT 30000 /* us */
+
+@@ -230,26 +202,44 @@
+
+ #define FEC_PAUSE_FLAG_AUTONEG 0x1
+ #define FEC_PAUSE_FLAG_ENABLE 0x2
++#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
++#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
++#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
++
++#define COPYBREAK_DEFAULT 256
++
++#define TSO_HEADER_SIZE 128
++/* Max number of allowed TCP segments for software TSO */
++#define FEC_MAX_TSO_SEGS 100
++#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
++
++#define IS_TSO_HEADER(txq, addr) \
++ ((addr >= txq->tso_hdrs_dma) && \
++ (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
+
+ static int mii_cnt;
+
+ static inline
+-struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
++struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
++ struct fec_enet_private *fep,
++ int queue_id)
+ {
+ struct bufdesc *new_bd = bdp + 1;
+ struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
++ struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
++ struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
+ struct bufdesc_ex *ex_base;
+ struct bufdesc *base;
+ int ring_size;
+
+- if (bdp >= fep->tx_bd_base) {
+- base = fep->tx_bd_base;
+- ring_size = fep->tx_ring_size;
+- ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
++ if (bdp >= txq->tx_bd_base) {
++ base = txq->tx_bd_base;
++ ring_size = txq->tx_ring_size;
++ ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
+ } else {
+- base = fep->rx_bd_base;
+- ring_size = fep->rx_ring_size;
+- ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
++ base = rxq->rx_bd_base;
++ ring_size = rxq->rx_ring_size;
++ ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
+ }
+
+ if (fep->bufdesc_ex)
+@@ -261,22 +251,26 @@
+ }
+
+ static inline
+-struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
++struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
++ struct fec_enet_private *fep,
++ int queue_id)
+ {
+ struct bufdesc *new_bd = bdp - 1;
+ struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
++ struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
++ struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
+ struct bufdesc_ex *ex_base;
+ struct bufdesc *base;
+ int ring_size;
+
+- if (bdp >= fep->tx_bd_base) {
+- base = fep->tx_bd_base;
+- ring_size = fep->tx_ring_size;
+- ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
++ if (bdp >= txq->tx_bd_base) {
++ base = txq->tx_bd_base;
++ ring_size = txq->tx_ring_size;
++ ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
+ } else {
+- base = fep->rx_bd_base;
+- ring_size = fep->rx_ring_size;
+- ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
++ base = rxq->rx_bd_base;
++ ring_size = rxq->rx_ring_size;
++ ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
+ }
+
+ if (fep->bufdesc_ex)
+@@ -286,15 +280,70 @@
+ return (new_bd < base) ? (new_bd + ring_size) : new_bd;
+ }
+
+-static void *swap_buffer(void *bufaddr, int len)
++static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
++ struct fec_enet_private *fep)
++{
++ return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
++}
++
++static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
++ struct fec_enet_priv_tx_q *txq)
++{
++ int entries;
++
++ entries = ((const char *)txq->dirty_tx -
++ (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
++
++ return entries > 0 ? entries : entries + txq->tx_ring_size;
++}
++
++static void swap_buffer(void *bufaddr, int len)
+ {
+ int i;
+ unsigned int *buf = bufaddr;
+
+- for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
+- *buf = cpu_to_be32(*buf);
++ for (i = 0; i < len; i += 4, buf++)
++ swab32s(buf);
++}
++
++static void swap_buffer2(void *dst_buf, void *src_buf, int len)
++{
++ int i;
++ unsigned int *src = src_buf;
++ unsigned int *dst = dst_buf;
+
+- return bufaddr;
++ for (i = 0; i < len; i += 4, src++, dst++)
++ *dst = swab32p(src);
++}
++
++static void fec_dump(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct bufdesc *bdp;
++ struct fec_enet_priv_tx_q *txq;
++ int index = 0;
++
++ netdev_info(ndev, "TX ring dump\n");
++ pr_info("Nr SC addr len SKB\n");
++
++ txq = fep->tx_queue[0];
++ bdp = txq->tx_bd_base;
++
++ do {
++ pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
++ index,
++ bdp == txq->cur_tx ? 'S' : ' ',
++ bdp == txq->dirty_tx ? 'H' : ' ',
++ bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
++ txq->tx_skbuff[index]);
++ bdp = fec_enet_get_nextdesc(bdp, fep, 0);
++ index++;
++ } while (bdp != txq->tx_bd_base);
++}
++
++static inline bool is_ipv4_pkt(struct sk_buff *skb)
++{
++ return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
+ }
+
+ static int
+@@ -307,136 +356,447 @@
+ if (unlikely(skb_cow_head(skb, 0)))
+ return -1;
+
++ if (is_ipv4_pkt(skb))
++ ip_hdr(skb)->check = 0;
+ *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
+
+ return 0;
+ }
+
+-static netdev_tx_t
+-fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
++static int
++fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
++ struct sk_buff *skb,
++ struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- const struct platform_device_id *id_entry =
+- platform_get_device_id(fep->pdev);
+- struct bufdesc *bdp, *bdp_pre;
+- void *bufaddr;
+- unsigned short status;
++ struct bufdesc *bdp = txq->cur_tx;
++ struct bufdesc_ex *ebdp;
++ int nr_frags = skb_shinfo(skb)->nr_frags;
++ unsigned short queue = skb_get_queue_mapping(skb);
++ int frag, frag_len;
++ unsigned short status;
++ unsigned int estatus = 0;
++ skb_frag_t *this_frag;
+ unsigned int index;
++ void *bufaddr;
++ dma_addr_t addr;
++ int i;
+
+- /* Fill in a Tx ring entry */
+- bdp = fep->cur_tx;
++ for (frag = 0; frag < nr_frags; frag++) {
++ this_frag = &skb_shinfo(skb)->frags[frag];
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue);
++ ebdp = (struct bufdesc_ex *)bdp;
++
++ status = bdp->cbd_sc;
++ status &= ~BD_ENET_TX_STATS;
++ status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
++ frag_len = skb_shinfo(skb)->frags[frag].size;
++
++ /* Handle the last BD specially */
++ if (frag == nr_frags - 1) {
++ status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
++ if (fep->bufdesc_ex) {
++ estatus |= BD_ENET_TX_INT;
++ if (unlikely(skb_shinfo(skb)->tx_flags &
++ SKBTX_HW_TSTAMP && fep->hwts_tx_en))
++ estatus |= BD_ENET_TX_TS;
++ }
++ }
+
+- status = bdp->cbd_sc;
++ if (fep->bufdesc_ex) {
++ if (fep->quirks & FEC_QUIRK_HAS_AVB)
++ estatus |= FEC_TX_BD_FTYPE(queue);
++ if (skb->ip_summed == CHECKSUM_PARTIAL)
++ estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
++ ebdp->cbd_bdu = 0;
++ ebdp->cbd_esc = estatus;
++ }
+
+- if (status & BD_ENET_TX_READY) {
+- /* Ooops. All transmit buffers are full. Bail out.
+- * This should not happen, since ndev->tbusy should be set.
+- */
+- netdev_err(ndev, "tx queue full!\n");
+- return NETDEV_TX_BUSY;
++ bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
++
++ index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
++ if (((unsigned long) bufaddr) & fep->tx_align ||
++ fep->quirks & FEC_QUIRK_SWAP_FRAME) {
++ memcpy(txq->tx_bounce[index], bufaddr, frag_len);
++ bufaddr = txq->tx_bounce[index];
++
++ if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
++ swap_buffer(bufaddr, frag_len);
++ }
++
++ addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(&fep->pdev->dev, addr)) {
++ dev_kfree_skb_any(skb);
++ if (net_ratelimit())
++ netdev_err(ndev, "Tx DMA memory map failed\n");
++ goto dma_mapping_error;
++ }
++
++ bdp->cbd_bufaddr = addr;
++ bdp->cbd_datlen = frag_len;
++ bdp->cbd_sc = status;
++ }
++
++ txq->cur_tx = bdp;
++
++ return 0;
++
++dma_mapping_error:
++ bdp = txq->cur_tx;
++ for (i = 0; i < frag; i++) {
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue);
++ dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
++ bdp->cbd_datlen, DMA_TO_DEVICE);
++ }
++ return NETDEV_TX_OK;
++}
++
++static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
++ struct sk_buff *skb, struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int nr_frags = skb_shinfo(skb)->nr_frags;
++ struct bufdesc *bdp, *last_bdp;
++ void *bufaddr;
++ dma_addr_t addr;
++ unsigned short status;
++ unsigned short buflen;
++ unsigned short queue;
++ unsigned int estatus = 0;
++ unsigned int index;
++ int entries_free;
++ int ret;
++
++ entries_free = fec_enet_get_free_txdesc_num(fep, txq);
++ if (entries_free < MAX_SKB_FRAGS + 1) {
++ dev_kfree_skb_any(skb);
++ if (net_ratelimit())
++ netdev_err(ndev, "NOT enough BD for SG!\n");
++ return NETDEV_TX_OK;
+ }
+
+ /* Protocol checksum off-load for TCP and UDP. */
+ if (fec_enet_clear_csum(skb, ndev)) {
+- kfree_skb(skb);
++ dev_kfree_skb_any(skb);
+ return NETDEV_TX_OK;
+ }
+
+- /* Clear all of the status flags */
++ /* Fill in a Tx ring entry */
++ bdp = txq->cur_tx;
++ status = bdp->cbd_sc;
+ status &= ~BD_ENET_TX_STATS;
+
+ /* Set buffer length and buffer pointer */
+ bufaddr = skb->data;
+- bdp->cbd_datlen = skb->len;
++ buflen = skb_headlen(skb);
+
+- /*
+- * On some FEC implementations data must be aligned on
+- * 4-byte boundaries. Use bounce buffers to copy data
+- * and get it aligned. Ugh.
+- */
+- if (fep->bufdesc_ex)
+- index = (struct bufdesc_ex *)bdp -
+- (struct bufdesc_ex *)fep->tx_bd_base;
+- else
+- index = bdp - fep->tx_bd_base;
++ queue = skb_get_queue_mapping(skb);
++ index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
++ if (((unsigned long) bufaddr) & fep->tx_align ||
++ fep->quirks & FEC_QUIRK_SWAP_FRAME) {
++ memcpy(txq->tx_bounce[index], skb->data, buflen);
++ bufaddr = txq->tx_bounce[index];
++
++ if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
++ swap_buffer(bufaddr, buflen);
++ }
++
++ /* Push the data cache so the CPM does not get stale memory data. */
++ addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
++ if (dma_mapping_error(&fep->pdev->dev, addr)) {
++ dev_kfree_skb_any(skb);
++ if (net_ratelimit())
++ netdev_err(ndev, "Tx DMA memory map failed\n");
++ return NETDEV_TX_OK;
++ }
+
+- if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
+- memcpy(fep->tx_bounce[index], skb->data, skb->len);
+- bufaddr = fep->tx_bounce[index];
++ if (nr_frags) {
++ ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
++ if (ret)
++ return ret;
++ } else {
++ status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
++ if (fep->bufdesc_ex) {
++ estatus = BD_ENET_TX_INT;
++ if (unlikely(skb_shinfo(skb)->tx_flags &
++ SKBTX_HW_TSTAMP && fep->hwts_tx_en))
++ estatus |= BD_ENET_TX_TS;
++ }
+ }
+
+- /*
+- * Some design made an incorrect assumption on endian mode of
+- * the system that it's running on. As the result, driver has to
+- * swap every frame going to and coming from the controller.
+- */
+- if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
+- swap_buffer(bufaddr, skb->len);
++ if (fep->bufdesc_ex) {
++
++ struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
++
++ if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
++ fep->hwts_tx_en))
++ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
++
++ if (fep->quirks & FEC_QUIRK_HAS_AVB)
++ estatus |= FEC_TX_BD_FTYPE(queue);
++
++ if (skb->ip_summed == CHECKSUM_PARTIAL)
++ estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
++
++ ebdp->cbd_bdu = 0;
++ ebdp->cbd_esc = estatus;
++ }
+
++ last_bdp = txq->cur_tx;
++ index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
+ /* Save skb pointer */
+- fep->tx_skbuff[index] = skb;
++ txq->tx_skbuff[index] = skb;
+
+- /* Push the data cache so the CPM does not get stale memory
+- * data.
++ bdp->cbd_datlen = buflen;
++ bdp->cbd_bufaddr = addr;
++
++ /* Send it on its way. Tell FEC it's ready, interrupt when done,
++ * it's the last BD of the frame, and to put the CRC on the end.
+ */
+- bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
+- skb->len, DMA_TO_DEVICE);
+- if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
+- bdp->cbd_bufaddr = 0;
+- fep->tx_skbuff[index] = NULL;
++ status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
++ bdp->cbd_sc = status;
++
++ /* If this was the last BD in the ring, start at the beginning again. */
++ bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
++
++ skb_tx_timestamp(skb);
++
++ txq->cur_tx = bdp;
++
++ /* Trigger transmission start */
++ writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
++
++ return 0;
++}
++
++static int
++fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
++ struct net_device *ndev,
++ struct bufdesc *bdp, int index, char *data,
++ int size, bool last_tcp, bool is_last)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
++ unsigned short queue = skb_get_queue_mapping(skb);
++ unsigned short status;
++ unsigned int estatus = 0;
++ dma_addr_t addr;
++
++ status = bdp->cbd_sc;
++ status &= ~BD_ENET_TX_STATS;
++
++ status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
++
++ if (((unsigned long) data) & fep->tx_align ||
++ fep->quirks & FEC_QUIRK_SWAP_FRAME) {
++ memcpy(txq->tx_bounce[index], data, size);
++ data = txq->tx_bounce[index];
++
++ if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
++ swap_buffer(data, size);
++ }
++
++ addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
++ if (dma_mapping_error(&fep->pdev->dev, addr)) {
+ dev_kfree_skb_any(skb);
+ if (net_ratelimit())
+ netdev_err(ndev, "Tx DMA memory map failed\n");
+- return NETDEV_TX_OK;
++ return NETDEV_TX_BUSY;
+ }
+
+- if (fep->bufdesc_ex) {
++ bdp->cbd_datlen = size;
++ bdp->cbd_bufaddr = addr;
+
+- struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
++ if (fep->bufdesc_ex) {
++ if (fep->quirks & FEC_QUIRK_HAS_AVB)
++ estatus |= FEC_TX_BD_FTYPE(queue);
++ if (skb->ip_summed == CHECKSUM_PARTIAL)
++ estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
+ ebdp->cbd_bdu = 0;
+- if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
+- fep->hwts_tx_en)) {
+- ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
+- skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+- } else {
+- ebdp->cbd_esc = BD_ENET_TX_INT;
++ ebdp->cbd_esc = estatus;
++ }
+
+- /* Enable protocol checksum flags
+- * We do not bother with the IP Checksum bits as they
+- * are done by the kernel
+- */
+- if (skb->ip_summed == CHECKSUM_PARTIAL)
+- ebdp->cbd_esc |= BD_ENET_TX_PINS;
++ /* Handle the last BD specially */
++ if (last_tcp)
++ status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
++ if (is_last) {
++ status |= BD_ENET_TX_INTR;
++ if (fep->bufdesc_ex)
++ ebdp->cbd_esc |= BD_ENET_TX_INT;
++ }
++ mb();
++ bdp->cbd_sc = status;
++
++ return 0;
++}
++
++static int
++fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
++ struct sk_buff *skb, struct net_device *ndev,
++ struct bufdesc *bdp, int index)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
++ struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
++ unsigned short queue = skb_get_queue_mapping(skb);
++ void *bufaddr;
++ unsigned long dmabuf;
++ unsigned short status;
++ unsigned int estatus = 0;
++
++ status = bdp->cbd_sc;
++ status &= ~BD_ENET_TX_STATS;
++ status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
++
++ bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
++ dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
++ if (((unsigned long)bufaddr) & fep->tx_align ||
++ fep->quirks & FEC_QUIRK_SWAP_FRAME) {
++ memcpy(txq->tx_bounce[index], skb->data, hdr_len);
++ bufaddr = txq->tx_bounce[index];
++
++ if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
++ swap_buffer(bufaddr, hdr_len);
++
++ dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
++ hdr_len, DMA_TO_DEVICE);
++ if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
++ dev_kfree_skb_any(skb);
++ if (net_ratelimit())
++ netdev_err(ndev, "Tx DMA memory map failed\n");
++ return NETDEV_TX_BUSY;
+ }
+ }
+
+- /* Send it on its way. Tell FEC it's ready, interrupt when done,
+- * it's the last BD of the frame, and to put the CRC on the end.
+- */
+- status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
+- | BD_ENET_TX_LAST | BD_ENET_TX_TC);
++ bdp->cbd_bufaddr = dmabuf;
++ bdp->cbd_datlen = hdr_len;
++
++ if (fep->bufdesc_ex) {
++ if (fep->quirks & FEC_QUIRK_HAS_AVB)
++ estatus |= FEC_TX_BD_FTYPE(queue);
++ if (skb->ip_summed == CHECKSUM_PARTIAL)
++ estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
++ ebdp->cbd_bdu = 0;
++ ebdp->cbd_esc = estatus;
++ }
++ mb();
+ bdp->cbd_sc = status;
+
+- bdp_pre = fec_enet_get_prevdesc(bdp, fep);
+- if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
+- !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
+- fep->delay_work.trig_tx = true;
+- schedule_delayed_work(&(fep->delay_work.delay_work),
+- msecs_to_jiffies(1));
++ return 0;
++}
++
++static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
++ struct sk_buff *skb,
++ struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
++ int total_len, data_left;
++ struct bufdesc *bdp = txq->cur_tx;
++ unsigned short queue = skb_get_queue_mapping(skb);
++ struct tso_t tso;
++ unsigned int index = 0;
++ int ret;
++
++ if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
++ dev_kfree_skb_any(skb);
++ if (net_ratelimit())
++ netdev_err(ndev, "NOT enough BD for TSO!\n");
++ return NETDEV_TX_OK;
+ }
+
+- /* If this was the last BD in the ring, start at the beginning again. */
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ /* Protocol checksum off-load for TCP and UDP. */
++ if (fec_enet_clear_csum(skb, ndev)) {
++ dev_kfree_skb_any(skb);
++ return NETDEV_TX_OK;
++ }
+
+- skb_tx_timestamp(skb);
++ /* Initialize the TSO handler, and prepare the first payload */
++ tso_start(skb, &tso);
++
++ total_len = skb->len - hdr_len;
++ while (total_len > 0) {
++ char *hdr;
++
++ index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
++ data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
++ total_len -= data_left;
++
++ /* prepare packet headers: MAC + IP + TCP */
++ hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
++ tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
++ ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
++ if (ret)
++ goto err_release;
+
+- fep->cur_tx = bdp;
++ while (data_left > 0) {
++ int size;
++
++ size = min_t(int, tso.size, data_left);
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue);
++ index = fec_enet_get_bd_index(txq->tx_bd_base,
++ bdp, fep);
++ ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
++ bdp, index,
++ tso.data, size,
++ size == data_left,
++ total_len == 0);
++ if (ret)
++ goto err_release;
++
++ data_left -= size;
++ tso_build_data(skb, &tso, size);
++ }
+
+- if (fep->cur_tx == fep->dirty_tx)
+- netif_stop_queue(ndev);
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue);
++ }
++
++ /* Save skb pointer */
++ txq->tx_skbuff[index] = skb;
++
++ skb_tx_timestamp(skb);
++ txq->cur_tx = bdp;
+
+ /* Trigger transmission start */
+- writel(0, fep->hwp + FEC_X_DES_ACTIVE);
++ if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
++ !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
++ !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
++ !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
++ !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
++ writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
++
++ return 0;
++
++err_release:
++ /* TODO: Release all used data descriptors for TSO */
++ return ret;
++}
++
++static netdev_tx_t
++fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int entries_free;
++ unsigned short queue;
++ struct fec_enet_priv_tx_q *txq;
++ struct netdev_queue *nq;
++ int ret;
++
++ queue = skb_get_queue_mapping(skb);
++ txq = fep->tx_queue[queue];
++ nq = netdev_get_tx_queue(ndev, queue);
++
++ if (skb_is_gso(skb))
++ ret = fec_enet_txq_submit_tso(txq, skb, ndev);
++ else
++ ret = fec_enet_txq_submit_skb(txq, skb, ndev);
++ if (ret)
++ return ret;
++
++ entries_free = fec_enet_get_free_txdesc_num(fep, txq);
++ if (entries_free <= txq->tx_stop_threshold)
++ netif_tx_stop_queue(nq);
+
+ return NETDEV_TX_OK;
+ }
+@@ -446,112 +806,161 @@
+ static void fec_enet_bd_init(struct net_device *dev)
+ {
+ struct fec_enet_private *fep = netdev_priv(dev);
++ struct fec_enet_priv_tx_q *txq;
++ struct fec_enet_priv_rx_q *rxq;
+ struct bufdesc *bdp;
+ unsigned int i;
++ unsigned int q;
+
+- /* Initialize the receive buffer descriptors. */
+- bdp = fep->rx_bd_base;
+- for (i = 0; i < fep->rx_ring_size; i++) {
+-
+- /* Initialize the BD for every fragment in the page. */
+- if (bdp->cbd_bufaddr)
+- bdp->cbd_sc = BD_ENET_RX_EMPTY;
+- else
++ for (q = 0; q < fep->num_rx_queues; q++) {
++ /* Initialize the receive buffer descriptors. */
++ rxq = fep->rx_queue[q];
++ bdp = rxq->rx_bd_base;
++
++ for (i = 0; i < rxq->rx_ring_size; i++) {
++
++ /* Initialize the BD for every fragment in the page. */
++ if (bdp->cbd_bufaddr)
++ bdp->cbd_sc = BD_ENET_RX_EMPTY;
++ else
++ bdp->cbd_sc = 0;
++ bdp = fec_enet_get_nextdesc(bdp, fep, q);
++ }
++
++ /* Set the last buffer to wrap */
++ bdp = fec_enet_get_prevdesc(bdp, fep, q);
++ bdp->cbd_sc |= BD_SC_WRAP;
++
++ rxq->cur_rx = rxq->rx_bd_base;
++ }
++
++ for (q = 0; q < fep->num_tx_queues; q++) {
++ /* ...and the same for transmit */
++ txq = fep->tx_queue[q];
++ bdp = txq->tx_bd_base;
++ txq->cur_tx = bdp;
++
++ for (i = 0; i < txq->tx_ring_size; i++) {
++ /* Initialize the BD for every fragment in the page. */
+ bdp->cbd_sc = 0;
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ if (txq->tx_skbuff[i]) {
++ dev_kfree_skb_any(txq->tx_skbuff[i]);
++ txq->tx_skbuff[i] = NULL;
++ }
++ bdp->cbd_bufaddr = 0;
++ bdp = fec_enet_get_nextdesc(bdp, fep, q);
++ }
++
++ /* Set the last buffer to wrap */
++ bdp = fec_enet_get_prevdesc(bdp, fep, q);
++ bdp->cbd_sc |= BD_SC_WRAP;
++ txq->dirty_tx = bdp;
+ }
++}
+
+- /* Set the last buffer to wrap */
+- bdp = fec_enet_get_prevdesc(bdp, fep);
+- bdp->cbd_sc |= BD_SC_WRAP;
++static void fec_enet_active_rxring(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int i;
+
+- fep->cur_rx = fep->rx_bd_base;
++ for (i = 0; i < fep->num_rx_queues; i++)
++ writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
++}
+
+- /* ...and the same for transmit */
+- bdp = fep->tx_bd_base;
+- fep->cur_tx = bdp;
+- for (i = 0; i < fep->tx_ring_size; i++) {
++static void fec_enet_enable_ring(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct fec_enet_priv_tx_q *txq;
++ struct fec_enet_priv_rx_q *rxq;
++ int i;
+
+- /* Initialize the BD for every fragment in the page. */
+- bdp->cbd_sc = 0;
+- if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
+- dev_kfree_skb_any(fep->tx_skbuff[i]);
+- fep->tx_skbuff[i] = NULL;
+- }
+- bdp->cbd_bufaddr = 0;
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ for (i = 0; i < fep->num_rx_queues; i++) {
++ rxq = fep->rx_queue[i];
++ writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
++ writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
++
++ /* enable DMA1/2 */
++ if (i)
++ writel(RCMR_MATCHEN | RCMR_CMP(i),
++ fep->hwp + FEC_RCMR(i));
+ }
+
+- /* Set the last buffer to wrap */
+- bdp = fec_enet_get_prevdesc(bdp, fep);
+- bdp->cbd_sc |= BD_SC_WRAP;
+- fep->dirty_tx = bdp;
++ for (i = 0; i < fep->num_tx_queues; i++) {
++ txq = fep->tx_queue[i];
++ writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
++
++ /* enable DMA1/2 */
++ if (i)
++ writel(DMA_CLASS_EN | IDLE_SLOPE(i),
++ fep->hwp + FEC_DMA_CFG(i));
++ }
++}
++
++static void fec_enet_reset_skb(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct fec_enet_priv_tx_q *txq;
++ int i, j;
++
++ for (i = 0; i < fep->num_tx_queues; i++) {
++ txq = fep->tx_queue[i];
++
++ for (j = 0; j < txq->tx_ring_size; j++) {
++ if (txq->tx_skbuff[j]) {
++ dev_kfree_skb_any(txq->tx_skbuff[j]);
++ txq->tx_skbuff[j] = NULL;
++ }
++ }
++ }
+ }
+
+-/* This function is called to start or restart the FEC during a link
+- * change. This only happens when switching between half and full
+- * duplex.
++/*
++ * This function is called to start or restart the FEC during a link
++ * change, transmit timeout, or to reconfigure the FEC. The network
++ * packet processing for this device must be stopped before this call.
+ */
+ static void
+-fec_restart(struct net_device *ndev, int duplex)
++fec_restart(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- const struct platform_device_id *id_entry =
+- platform_get_device_id(fep->pdev);
+- int i;
+ u32 val;
+ u32 temp_mac[2];
+ u32 rcntl = OPT_FRAME_SIZE | 0x04;
+- u32 ecntl = 0x2; /* ETHEREN */
++ u32 ecntl = FEC_ENET_ETHEREN; /* ETHEREN */
+
+- if (netif_running(ndev)) {
+- netif_device_detach(ndev);
+- napi_disable(&fep->napi);
+- netif_stop_queue(ndev);
+- netif_tx_lock_bh(ndev);
++ /* Whack a reset. We should wait for this.
++ * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
++ * instead of reset MAC itself.
++ */
++ if (fep->quirks & FEC_QUIRK_HAS_AVB) {
++ writel(0, fep->hwp + FEC_ECNTRL);
++ } else {
++ writel(1, fep->hwp + FEC_ECNTRL);
++ udelay(10);
+ }
+
+- /* Whack a reset. We should wait for this. */
+- writel(1, fep->hwp + FEC_ECNTRL);
+- udelay(10);
+-
+ /*
+ * enet-mac reset will reset mac address registers too,
+ * so need to reconfigure it.
+ */
+- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
++ if (fep->quirks & FEC_QUIRK_ENET_MAC) {
+ memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
+ writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+ writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+ }
+
+ /* Clear any outstanding interrupt. */
+- writel(0xffc00000, fep->hwp + FEC_IEVENT);
+-
+- /* Set maximum receive buffer size. */
+- writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
++ writel(0xffffffff, fep->hwp + FEC_IEVENT);
+
+ fec_enet_bd_init(ndev);
+
+- /* Set receive and transmit descriptor base. */
+- writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
+- if (fep->bufdesc_ex)
+- writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
+- * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
+- else
+- writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
+- * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
+-
++ fec_enet_enable_ring(ndev);
+
+- for (i = 0; i <= TX_RING_MOD_MASK; i++) {
+- if (fep->tx_skbuff[i]) {
+- dev_kfree_skb_any(fep->tx_skbuff[i]);
+- fep->tx_skbuff[i] = NULL;
+- }
+- }
++ /* Reset tx SKB buffers. */
++ fec_enet_reset_skb(ndev);
+
+ /* Enable MII mode */
+- if (duplex) {
++ if (fep->full_duplex == DUPLEX_FULL) {
+ /* FD enable */
+ writel(0x04, fep->hwp + FEC_X_CNTRL);
+ } else {
+@@ -560,8 +969,6 @@
+ writel(0x0, fep->hwp + FEC_X_CNTRL);
+ }
+
+- fep->full_duplex = duplex;
+-
+ /* Set MII speed */
+ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+
+@@ -579,7 +986,7 @@
+ * The phy interface and speed need to get configured
+ * differently on enet-mac.
+ */
+- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
++ if (fep->quirks & FEC_QUIRK_ENET_MAC) {
+ /* Enable flow control and length check */
+ rcntl |= 0x40000000 | 0x00000020;
+
+@@ -602,7 +1009,7 @@
+ }
+ } else {
+ #ifdef FEC_MIIGSK_ENR
+- if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
++ if (fep->quirks & FEC_QUIRK_USE_GASKET) {
+ u32 cfgr;
+ /* disable the gasket and wait */
+ writel(0, fep->hwp + FEC_MIIGSK_ENR);
+@@ -655,7 +1062,7 @@
+ writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
+ #endif
+
+- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
++ if (fep->quirks & FEC_QUIRK_ENET_MAC) {
+ /* enable ENET endian swap */
+ ecntl |= (1 << 8);
+ /* enable ENET store and forward mode */
+@@ -672,29 +1079,29 @@
+
+ /* And last, enable the transmit and receive processing */
+ writel(ecntl, fep->hwp + FEC_ECNTRL);
+- writel(0, fep->hwp + FEC_R_DES_ACTIVE);
++ fec_enet_active_rxring(ndev);
+
+ if (fep->bufdesc_ex)
+ fec_ptp_start_cyclecounter(ndev);
+
+ /* Enable interrupts we wish to service */
+- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
++ if (fep->link)
++ writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
++ else
++ writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
++
++ /* Init the interrupt coalescing */
++ fec_enet_itr_coal_init(ndev);
+
+- if (netif_running(ndev)) {
+- netif_tx_unlock_bh(ndev);
+- netif_wake_queue(ndev);
+- napi_enable(&fep->napi);
+- netif_device_attach(ndev);
+- }
+ }
+
+ static void
+ fec_stop(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- const struct platform_device_id *id_entry =
+- platform_get_device_id(fep->pdev);
++ struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
+ u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
++ u32 val;
+
+ /* We cannot expect a graceful transmit stop without link !!! */
+ if (fep->link) {
+@@ -704,14 +1111,32 @@
+ netdev_err(ndev, "Graceful transmit stop did not complete!\n");
+ }
+
+- /* Whack a reset. We should wait for this. */
+- writel(1, fep->hwp + FEC_ECNTRL);
+- udelay(10);
++ /* Whack a reset. We should wait for this.
++ * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
++ * instead of reset MAC itself.
++ */
++ if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
++ if (fep->quirks & FEC_QUIRK_HAS_AVB) {
++ writel(0, fep->hwp + FEC_ECNTRL);
++ } else {
++ writel(1, fep->hwp + FEC_ECNTRL);
++ udelay(10);
++ }
++ writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
++ } else {
++ writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
++ val = readl(fep->hwp + FEC_ECNTRL);
++ val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
++ writel(val, fep->hwp + FEC_ECNTRL);
++
++ if (pdata && pdata->sleep_mode_enable)
++ pdata->sleep_mode_enable(true);
++ }
+ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+- writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
+
+ /* We have to keep ENET enabled to have MII interrupt stay working */
+- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
++ if (fep->quirks & FEC_QUIRK_ENET_MAC &&
++ !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
+ writel(2, fep->hwp + FEC_ECNTRL);
+ writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
+ }
+@@ -723,62 +1148,99 @@
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
++ fec_dump(ndev);
++
+ ndev->stats.tx_errors++;
+
+- fep->delay_work.timeout = true;
+- schedule_delayed_work(&(fep->delay_work.delay_work), 0);
++ schedule_work(&fep->tx_timeout_work);
+ }
+
+-static void fec_enet_work(struct work_struct *work)
++static void fec_enet_timeout_work(struct work_struct *work)
+ {
+ struct fec_enet_private *fep =
+- container_of(work,
+- struct fec_enet_private,
+- delay_work.delay_work.work);
+-
+- if (fep->delay_work.timeout) {
+- fep->delay_work.timeout = false;
+- fec_restart(fep->netdev, fep->full_duplex);
+- netif_wake_queue(fep->netdev);
+- }
++ container_of(work, struct fec_enet_private, tx_timeout_work);
++ struct net_device *ndev = fep->netdev;
+
+- if (fep->delay_work.trig_tx) {
+- fep->delay_work.trig_tx = false;
+- writel(0, fep->hwp + FEC_X_DES_ACTIVE);
++ rtnl_lock();
++ if (netif_device_present(ndev) || netif_running(ndev)) {
++ napi_disable(&fep->napi);
++ netif_tx_lock_bh(ndev);
++ fec_restart(ndev);
++ netif_wake_queue(ndev);
++ netif_tx_unlock_bh(ndev);
++ napi_enable(&fep->napi);
+ }
++ rtnl_unlock();
+ }
+
+ static void
+-fec_enet_tx(struct net_device *ndev)
++fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
++ struct skb_shared_hwtstamps *hwtstamps)
++{
++ unsigned long flags;
++ u64 ns;
++
++ spin_lock_irqsave(&fep->tmreg_lock, flags);
++ ns = timecounter_cyc2time(&fep->tc, ts);
++ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
++
++ memset(hwtstamps, 0, sizeof(*hwtstamps));
++ hwtstamps->hwtstamp = ns_to_ktime(ns);
++}
++
++static void
++fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
+ {
+ struct fec_enet_private *fep;
+- struct bufdesc *bdp;
++ struct bufdesc *bdp, *bdp_t;
+ unsigned short status;
+ struct sk_buff *skb;
++ struct fec_enet_priv_tx_q *txq;
++ struct netdev_queue *nq;
+ int index = 0;
++ int i, bdnum;
++ int entries_free;
+
+ fep = netdev_priv(ndev);
+- bdp = fep->dirty_tx;
+
++ queue_id = FEC_ENET_GET_QUQUE(queue_id);
++
++ txq = fep->tx_queue[queue_id];
+ /* get next bdp of dirty_tx */
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ nq = netdev_get_tx_queue(ndev, queue_id);
++ bdp = txq->dirty_tx;
++
++ /* get next bdp of dirty_tx */
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
+
+ while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
+
+ /* current queue is empty */
+- if (bdp == fep->cur_tx)
++ if (bdp == txq->cur_tx)
+ break;
+
+- if (fep->bufdesc_ex)
+- index = (struct bufdesc_ex *)bdp -
+- (struct bufdesc_ex *)fep->tx_bd_base;
+- else
+- index = bdp - fep->tx_bd_base;
++ bdp_t = bdp;
++ bdnum = 1;
++ index = fec_enet_get_bd_index(txq->tx_bd_base, bdp_t, fep);
++ skb = txq->tx_skbuff[index];
++ while (!skb) {
++ bdp_t = fec_enet_get_nextdesc(bdp_t, fep, queue_id);
++ index = fec_enet_get_bd_index(txq->tx_bd_base, bdp_t, fep);
++ skb = txq->tx_skbuff[index];
++ bdnum++;
++ }
++ if ((status = bdp_t->cbd_sc) & BD_ENET_TX_READY)
++ break;
+
+- skb = fep->tx_skbuff[index];
+- dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
+- DMA_TO_DEVICE);
+- bdp->cbd_bufaddr = 0;
++ for (i = 0; i < bdnum; i++) {
++ if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
++ dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
++ bdp->cbd_datlen, DMA_TO_DEVICE);
++ bdp->cbd_bufaddr = 0;
++ if (i < bdnum - 1)
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
++ }
++ txq->tx_skbuff[index] = NULL;
+
+ /* Check for errors. */
+ if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
+@@ -797,26 +1259,18 @@
+ ndev->stats.tx_carrier_errors++;
+ } else {
+ ndev->stats.tx_packets++;
+- ndev->stats.tx_bytes += bdp->cbd_datlen;
++ ndev->stats.tx_bytes += skb->len;
+ }
+
+ if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
+ fep->bufdesc_ex) {
+ struct skb_shared_hwtstamps shhwtstamps;
+- unsigned long flags;
+ struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
+
+- memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+- spin_lock_irqsave(&fep->tmreg_lock, flags);
+- shhwtstamps.hwtstamp = ns_to_ktime(
+- timecounter_cyc2time(&fep->tc, ebdp->ts));
+- spin_unlock_irqrestore(&fep->tmreg_lock, flags);
++ fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
+ skb_tstamp_tx(skb, &shhwtstamps);
+ }
+
+- if (status & BD_ENET_TX_READY)
+- netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
+-
+ /* Deferred means some collisions occurred during transmit,
+ * but we eventually sent the packet OK.
+ */
+@@ -825,23 +1279,86 @@
+
+ /* Free the sk buffer associated with this last transmit */
+ dev_kfree_skb_any(skb);
+- fep->tx_skbuff[index] = NULL;
+
+- fep->dirty_tx = bdp;
++ txq->dirty_tx = bdp;
+
+ /* Update pointer to next buffer descriptor to be transmitted */
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
+
+ /* Since we have freed up a buffer, the ring is no longer full
+ */
+- if (fep->dirty_tx != fep->cur_tx) {
+- if (netif_queue_stopped(ndev))
+- netif_wake_queue(ndev);
++ if (netif_queue_stopped(ndev)) {
++ entries_free = fec_enet_get_free_txdesc_num(fep, txq);
++ if (entries_free >= txq->tx_wake_threshold)
++ netif_tx_wake_queue(nq);
+ }
+ }
++
++ /* ERR006538: Keep the transmitter going */
++ if (bdp != txq->cur_tx &&
++ readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
++ writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
++}
++
++static void
++fec_enet_tx(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ u16 queue_id;
++ /* First process class A queue, then Class B and Best Effort queue */
++ for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
++ clear_bit(queue_id, &fep->work_tx);
++ fec_enet_tx_queue(ndev, queue_id);
++ }
+ return;
+ }
+
++static int
++fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int off;
++
++ off = ((unsigned long)skb->data) & fep->rx_align;
++ if (off)
++ skb_reserve(skb, fep->rx_align + 1 - off);
++
++ bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
++ FEC_ENET_RX_FRSIZE - fep->rx_align,
++ DMA_FROM_DEVICE);
++ if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
++ if (net_ratelimit())
++ netdev_err(ndev, "Rx DMA memory map failed\n");
++ return -ENOMEM;
++ }
++
++ return 0;
++}
++
++static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
++ struct bufdesc *bdp, u32 length, bool swap)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct sk_buff *new_skb;
++
++ if (length > fep->rx_copybreak)
++ return false;
++
++ new_skb = netdev_alloc_skb(ndev, length);
++ if (!new_skb)
++ return false;
++
++ dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
++ FEC_ENET_RX_FRSIZE - fep->rx_align,
++ DMA_FROM_DEVICE);
++ if (!swap)
++ memcpy(new_skb->data, (*skb)->data, length);
++ else
++ swap_buffer2(new_skb->data, (*skb)->data, length);
++ *skb = new_skb;
++
++ return true;
++}
+
+ /* During a receive, the cur_rx points to the current incoming buffer.
+ * When we update through the ring, if the next incoming buffer has
+@@ -849,14 +1366,14 @@
+ * effectively tossing the packet.
+ */
+ static int
+-fec_enet_rx(struct net_device *ndev, int budget)
++fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- const struct platform_device_id *id_entry =
+- platform_get_device_id(fep->pdev);
++ struct fec_enet_priv_rx_q *rxq;
+ struct bufdesc *bdp;
+ unsigned short status;
+- struct sk_buff *skb;
++ struct sk_buff *skb_new = NULL;
++ struct sk_buff *skb;
+ ushort pkt_len;
+ __u8 *data;
+ int pkt_received = 0;
+@@ -864,15 +1381,19 @@
+ bool vlan_packet_rcvd = false;
+ u16 vlan_tag;
+ int index = 0;
++ bool is_copybreak;
++ bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
+
+ #ifdef CONFIG_M532x
+ flush_cache_all();
+ #endif
++ queue_id = FEC_ENET_GET_QUQUE(queue_id);
++ rxq = fep->rx_queue[queue_id];
+
+ /* First, grab all of the stats for the incoming packet.
+ * These get messed up if we get called due to a busy condition.
+ */
+- bdp = fep->cur_rx;
++ bdp = rxq->cur_rx;
+
+ while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
+
+@@ -886,32 +1407,28 @@
+ if ((status & BD_ENET_RX_LAST) == 0)
+ netdev_err(ndev, "rcv is not +last\n");
+
+- if (!fep->opened)
+- goto rx_processing_done;
+-
+ /* Check for errors. */
+- if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
+- BD_ENET_RX_CR | BD_ENET_RX_OV)) {
++ if (status & BD_ENET_RX_ERROR) {
+ ndev->stats.rx_errors++;
+- if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
+- /* Frame too long or too short. */
+- ndev->stats.rx_length_errors++;
+- }
+- if (status & BD_ENET_RX_NO) /* Frame alignment */
+- ndev->stats.rx_frame_errors++;
+- if (status & BD_ENET_RX_CR) /* CRC Error */
+- ndev->stats.rx_crc_errors++;
+- if (status & BD_ENET_RX_OV) /* FIFO overrun */
+- ndev->stats.rx_fifo_errors++;
+- }
+
+- /* Report late collisions as a frame error.
+- * On this error, the BD is closed, but we don't know what we
+- * have in the buffer. So, just drop this frame on the floor.
+- */
+- if (status & BD_ENET_RX_CL) {
+- ndev->stats.rx_errors++;
+- ndev->stats.rx_frame_errors++;
++ /* Report late collisions as a frame error.
++ * On this error, the BD is closed, but we don't know what we
++ * have in the buffer. So, just drop this frame on the floor.
++ */
++ if (status & BD_ENET_RX_CL) {
++ ndev->stats.rx_frame_errors++;
++ } else {
++ if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
++ /* Frame too long or too short. */
++ ndev->stats.rx_length_errors++;
++ }
++ if (status & BD_ENET_RX_NO) /* Frame alignment */
++ ndev->stats.rx_frame_errors++;
++ if (status & BD_ENET_RX_CR) /* CRC Error */
++ ndev->stats.rx_crc_errors++;
++ if (status & BD_ENET_RX_OV) /* FIFO overrun */
++ ndev->stats.rx_fifo_errors++;
++ }
+ goto rx_processing_done;
+ }
+
+@@ -920,16 +1437,30 @@
+ pkt_len = bdp->cbd_datlen;
+ ndev->stats.rx_bytes += pkt_len;
+
+- if (fep->bufdesc_ex)
+- index = (struct bufdesc_ex *)bdp -
+- (struct bufdesc_ex *)fep->rx_bd_base;
+- else
+- index = bdp - fep->rx_bd_base;
+- data = fep->rx_skbuff[index]->data;
+- dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
+- FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
++ index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
++ skb = rxq->rx_skbuff[index];
+
+- if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
++ /* The packet length includes FCS, but we don't want to
++ * include that when passing upstream as it messes up
++ * bridging applications.
++ */
++ is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
++ need_swap);
++ if (!is_copybreak) {
++ skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
++ if (unlikely(!skb_new)) {
++ ndev->stats.rx_dropped++;
++ goto rx_processing_done;
++ }
++ dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
++ FEC_ENET_RX_FRSIZE - fep->rx_align,
++ DMA_FROM_DEVICE);
++ }
++
++ prefetch(skb->data - NET_IP_ALIGN);
++ skb_put(skb, pkt_len - 4);
++ data = skb->data;
++ if (!is_copybreak && need_swap)
+ swap_buffer(data, pkt_len);
+
+ /* Extract the enhanced buffer descriptor */
+@@ -940,75 +1471,53 @@
+ /* If this is a VLAN packet remove the VLAN Tag */
+ vlan_packet_rcvd = false;
+ if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
+- fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
++ fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
+ /* Push and remove the vlan tag */
+ struct vlan_hdr *vlan_header =
+ (struct vlan_hdr *) (data + ETH_HLEN);
+ vlan_tag = ntohs(vlan_header->h_vlan_TCI);
+- pkt_len -= VLAN_HLEN;
+
+ vlan_packet_rcvd = true;
+- }
+
+- /* This does 16 byte alignment, exactly what we need.
+- * The packet length includes FCS, but we don't want to
+- * include that when passing upstream as it messes up
+- * bridging applications.
+- */
+- skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
+-
+- if (unlikely(!skb)) {
+- ndev->stats.rx_dropped++;
+- } else {
+- int payload_offset = (2 * ETH_ALEN);
+- skb_reserve(skb, NET_IP_ALIGN);
+- skb_put(skb, pkt_len - 4); /* Make room */
+-
+- /* Extract the frame data without the VLAN header. */
+- skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
+- if (vlan_packet_rcvd)
+- payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
+- skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
+- data + payload_offset,
+- pkt_len - 4 - (2 * ETH_ALEN));
+-
+- skb->protocol = eth_type_trans(skb, ndev);
+-
+- /* Get receive timestamp from the skb */
+- if (fep->hwts_rx_en && fep->bufdesc_ex) {
+- struct skb_shared_hwtstamps *shhwtstamps =
+- skb_hwtstamps(skb);
+- unsigned long flags;
+-
+- memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+-
+- spin_lock_irqsave(&fep->tmreg_lock, flags);
+- shhwtstamps->hwtstamp = ns_to_ktime(
+- timecounter_cyc2time(&fep->tc, ebdp->ts));
+- spin_unlock_irqrestore(&fep->tmreg_lock, flags);
+- }
+-
+- if (fep->bufdesc_ex &&
+- (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
+- if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
+- /* don't check it */
+- skb->ip_summed = CHECKSUM_UNNECESSARY;
+- } else {
+- skb_checksum_none_assert(skb);
+- }
++ skb_copy_to_linear_data_offset(skb, VLAN_HLEN,
++ data, (2 * ETH_ALEN));
++ skb_pull(skb, VLAN_HLEN);
++ }
++
++ skb->protocol = eth_type_trans(skb, ndev);
++
++ /* Get receive timestamp from the skb */
++ if (fep->hwts_rx_en && fep->bufdesc_ex)
++ fec_enet_hwtstamp(fep, ebdp->ts,
++ skb_hwtstamps(skb));
++
++ if (fep->bufdesc_ex &&
++ (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
++ if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
++ /* don't check it */
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++ } else {
++ skb_checksum_none_assert(skb);
+ }
++ }
+
+- /* Handle received VLAN packets */
+- if (vlan_packet_rcvd)
+- __vlan_hwaccel_put_tag(skb,
+- htons(ETH_P_8021Q),
+- vlan_tag);
+-
+- napi_gro_receive(&fep->napi, skb);
++ /* Handle received VLAN packets */
++ if (vlan_packet_rcvd)
++ __vlan_hwaccel_put_tag(skb,
++ htons(ETH_P_8021Q),
++ vlan_tag);
++
++ napi_gro_receive(&fep->napi, skb);
++
++ if (is_copybreak) {
++ dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
++ FEC_ENET_RX_FRSIZE - fep->rx_align,
++ DMA_FROM_DEVICE);
++ } else {
++ rxq->rx_skbuff[index] = skb_new;
++ fec_enet_new_rxbdp(ndev, bdp, skb_new);
+ }
+
+- dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
+- FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+ rx_processing_done:
+ /* Clear the status flags for this buffer */
+ status &= ~BD_ENET_RX_STATS;
+@@ -1026,19 +1535,56 @@
+ }
+
+ /* Update BD pointer to next entry */
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
+
+ /* Doing this here will keep the FEC running while we process
+ * incoming frames. On a heavily loaded network, we should be
+ * able to keep up at the expense of system resources.
+ */
+- writel(0, fep->hwp + FEC_R_DES_ACTIVE);
++ writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
+ }
+- fep->cur_rx = bdp;
++ rxq->cur_rx = bdp;
++ return pkt_received;
++}
++
++static int
++fec_enet_rx(struct net_device *ndev, int budget)
++{
++ int pkt_received = 0;
++ u16 queue_id;
++ struct fec_enet_private *fep = netdev_priv(ndev);
+
++ for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
++ clear_bit(queue_id, &fep->work_rx);
++ pkt_received += fec_enet_rx_queue(ndev,
++ budget - pkt_received, queue_id);
++ }
+ return pkt_received;
+ }
+
++static bool
++fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
++{
++ if (int_events == 0)
++ return false;
++
++ if (int_events & FEC_ENET_RXF)
++ fep->work_rx |= (1 << 2);
++ if (int_events & FEC_ENET_RXF_1)
++ fep->work_rx |= (1 << 0);
++ if (int_events & FEC_ENET_RXF_2)
++ fep->work_rx |= (1 << 1);
++
++ if (int_events & FEC_ENET_TXF)
++ fep->work_tx |= (1 << 2);
++ if (int_events & FEC_ENET_TXF_1)
++ fep->work_tx |= (1 << 0);
++ if (int_events & FEC_ENET_TXF_2)
++ fep->work_tx |= (1 << 1);
++
++ return true;
++}
++
+ static irqreturn_t
+ fec_enet_interrupt(int irq, void *dev_id)
+ {
+@@ -1047,26 +1593,27 @@
+ uint int_events;
+ irqreturn_t ret = IRQ_NONE;
+
+- do {
+- int_events = readl(fep->hwp + FEC_IEVENT);
+- writel(int_events, fep->hwp + FEC_IEVENT);
++ int_events = readl(fep->hwp + FEC_IEVENT);
++ writel(int_events, fep->hwp + FEC_IEVENT);
++ fec_enet_collect_events(fep, int_events);
+
+- if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
+- ret = IRQ_HANDLED;
++ if ((fep->work_tx || fep->work_rx) && fep->link) {
++ ret = IRQ_HANDLED;
+
+- /* Disable the RX interrupt */
+- if (napi_schedule_prep(&fep->napi)) {
+- writel(FEC_RX_DISABLED_IMASK,
+- fep->hwp + FEC_IMASK);
+- __napi_schedule(&fep->napi);
+- }
++ if (napi_schedule_prep(&fep->napi)) {
++ /* Disable the NAPI interrupts */
++ writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
++ __napi_schedule(&fep->napi);
+ }
++ }
+
+- if (int_events & FEC_ENET_MII) {
+- ret = IRQ_HANDLED;
+- complete(&fep->mdio_done);
+- }
+- } while (int_events);
++ if (int_events & FEC_ENET_MII) {
++ ret = IRQ_HANDLED;
++ complete(&fep->mdio_done);
++ }
++
++ if (fep->bufdesc_ex)
++ fec_ptp_check_pps_event(fep);
+
+ return ret;
+ }
+@@ -1074,8 +1621,10 @@
+ static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
+ {
+ struct net_device *ndev = napi->dev;
+- int pkts = fec_enet_rx(ndev, budget);
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ int pkts;
++
++ pkts = fec_enet_rx(ndev, budget);
+
+ fec_enet_tx(ndev);
+
+@@ -1173,14 +1722,23 @@
+ return;
+ }
+
+- if (phy_dev->link) {
++ /*
++ * If the netdev is down, or is going down, we're not interested
++ * in link state events, so just mark our idea of the link as down
++ * and ignore the event.
++ */
++ if (!netif_running(ndev) || !netif_device_present(ndev)) {
++ fep->link = 0;
++ } else if (phy_dev->link) {
+ if (!fep->link) {
+ fep->link = phy_dev->link;
+ status_change = 1;
+ }
+
+- if (fep->full_duplex != phy_dev->duplex)
++ if (fep->full_duplex != phy_dev->duplex) {
++ fep->full_duplex = phy_dev->duplex;
+ status_change = 1;
++ }
+
+ if (phy_dev->speed != fep->speed) {
+ fep->speed = phy_dev->speed;
+@@ -1188,11 +1746,21 @@
+ }
+
+ /* if any of the above changed restart the FEC */
+- if (status_change)
+- fec_restart(ndev, phy_dev->duplex);
++ if (status_change) {
++ napi_disable(&fep->napi);
++ netif_tx_lock_bh(ndev);
++ fec_restart(ndev);
++ netif_wake_queue(ndev);
++ netif_tx_unlock_bh(ndev);
++ napi_enable(&fep->napi);
++ }
+ } else {
+ if (fep->link) {
++ napi_disable(&fep->napi);
++ netif_tx_lock_bh(ndev);
+ fec_stop(ndev);
++ netif_tx_unlock_bh(ndev);
++ napi_enable(&fep->napi);
+ fep->link = phy_dev->link;
+ status_change = 1;
+ }
+@@ -1255,16 +1823,84 @@
+ return 0;
+ }
+
+-static int fec_enet_mdio_reset(struct mii_bus *bus)
++static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
+ {
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int ret;
++
++ if (enable) {
++ ret = clk_prepare_enable(fep->clk_ahb);
++ if (ret)
++ return ret;
++ ret = clk_prepare_enable(fep->clk_ipg);
++ if (ret)
++ goto failed_clk_ipg;
++ if (fep->clk_enet_out) {
++ ret = clk_prepare_enable(fep->clk_enet_out);
++ if (ret)
++ goto failed_clk_enet_out;
++ }
++ if (fep->clk_ptp) {
++ mutex_lock(&fep->ptp_clk_mutex);
++ ret = clk_prepare_enable(fep->clk_ptp);
++ if (ret) {
++ mutex_unlock(&fep->ptp_clk_mutex);
++ goto failed_clk_ptp;
++ } else {
++ fep->ptp_clk_on = true;
++ }
++ mutex_unlock(&fep->ptp_clk_mutex);
++ }
++ if (fep->clk_ref) {
++ ret = clk_prepare_enable(fep->clk_ref);
++ if (ret)
++ goto failed_clk_ref;
++ }
++ } else {
++ clk_disable_unprepare(fep->clk_ahb);
++ clk_disable_unprepare(fep->clk_ipg);
++ if (fep->clk_enet_out)
++ clk_disable_unprepare(fep->clk_enet_out);
++ if (fep->clk_ptp) {
++ mutex_lock(&fep->ptp_clk_mutex);
++ clk_disable_unprepare(fep->clk_ptp);
++ fep->ptp_clk_on = false;
++ mutex_unlock(&fep->ptp_clk_mutex);
++ }
++ if (fep->clk_ref)
++ clk_disable_unprepare(fep->clk_ref);
++ }
++
+ return 0;
++
++failed_clk_ref:
++ if (fep->clk_ref)
++ clk_disable_unprepare(fep->clk_ref);
++failed_clk_ptp:
++ if (fep->clk_enet_out)
++ clk_disable_unprepare(fep->clk_enet_out);
++failed_clk_enet_out:
++ clk_disable_unprepare(fep->clk_ipg);
++failed_clk_ipg:
++ clk_disable_unprepare(fep->clk_ahb);
++
++ return ret;
++}
++
++static void fec_restore_mii_bus(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++
++ fec_enet_clk_enable(ndev, true);
++ writel(0xffc00000, fep->hwp + FEC_IEVENT);
++ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
++ writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
++ writel(FEC_ENET_ETHEREN, fep->hwp + FEC_ECNTRL);
+ }
+
+ static int fec_enet_mii_probe(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- const struct platform_device_id *id_entry =
+- platform_get_device_id(fep->pdev);
+ struct phy_device *phy_dev = NULL;
+ char mdio_bus_id[MII_BUS_ID_SIZE];
+ char phy_name[MII_BUS_ID_SIZE + 3];
+@@ -1273,37 +1909,48 @@
+
+ fep->phy_dev = NULL;
+
+- /* check for attached phy */
+- for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
+- if ((fep->mii_bus->phy_mask & (1 << phy_id)))
+- continue;
+- if (fep->mii_bus->phy_map[phy_id] == NULL)
+- continue;
+- if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
+- continue;
+- if (dev_id--)
+- continue;
+- strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
+- break;
+- }
++ if (fep->phy_node) {
++ phy_dev = of_phy_connect(ndev, fep->phy_node,
++ &fec_enet_adjust_link, 0,
++ fep->phy_interface);
++ if (!phy_dev)
++ return -ENODEV;
++ } else {
++ /* check for attached phy */
++ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
++ if ((fep->mii_bus->phy_mask & (1 << phy_id)))
++ continue;
++ if (fep->mii_bus->phy_map[phy_id] == NULL)
++ continue;
++ if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
++ continue;
++ if (dev_id--)
++ continue;
++ strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
++ break;
++ }
++
++ if (phy_id >= PHY_MAX_ADDR) {
++ netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
++ strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
++ phy_id = 0;
++ }
+
+- if (phy_id >= PHY_MAX_ADDR) {
+- netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
+- strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
+- phy_id = 0;
++ snprintf(phy_name, sizeof(phy_name),
++ PHY_ID_FMT, mdio_bus_id, phy_id);
++ phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
++ fep->phy_interface);
+ }
+
+- snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
+- phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
+- fep->phy_interface);
+ if (IS_ERR(phy_dev)) {
+ netdev_err(ndev, "could not attach to PHY\n");
+ return PTR_ERR(phy_dev);
+ }
+
+ /* mask with MAC supported features */
+- if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
++ if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
+ phy_dev->supported &= PHY_GBIT_FEATURES;
++ phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
+ #if !defined(CONFIG_M5272)
+ phy_dev->supported |= SUPPORTED_Pause;
+ #endif
+@@ -1327,10 +1974,10 @@
+ static int fec_enet_mii_init(struct platform_device *pdev)
+ {
+ static struct mii_bus *fec0_mii_bus;
++ static int *fec_mii_bus_share;
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- const struct platform_device_id *id_entry =
+- platform_get_device_id(fep->pdev);
++ struct device_node *node;
+ int err = -ENXIO, i;
+
+ /*
+@@ -1349,10 +1996,11 @@
+ * mdio interface in board design, and need to be configured by
+ * fec0 mii_bus.
+ */
+- if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
++ if ((fep->quirks & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
+ /* fec1 uses fec0 mii_bus */
+ if (mii_cnt && fec0_mii_bus) {
+ fep->mii_bus = fec0_mii_bus;
++ *fec_mii_bus_share = FEC0_MII_BUS_SHARE_TRUE;
+ mii_cnt++;
+ return 0;
+ }
+@@ -1369,8 +2017,8 @@
+ * Reference Manual has an error on this, and gets fixed on i.MX6Q
+ * document.
+ */
+- fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
+- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
++ fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
++ if (fep->quirks & FEC_QUIRK_ENET_MAC)
+ fep->phy_speed--;
+ fep->phy_speed <<= 1;
+ writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
+@@ -1384,7 +2032,6 @@
+ fep->mii_bus->name = "fec_enet_mii_bus";
+ fep->mii_bus->read = fec_enet_mdio_read;
+ fep->mii_bus->write = fec_enet_mdio_write;
+- fep->mii_bus->reset = fec_enet_mdio_reset;
+ snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
+ pdev->name, fep->dev_id + 1);
+ fep->mii_bus->priv = fep;
+@@ -1399,14 +2046,24 @@
+ for (i = 0; i < PHY_MAX_ADDR; i++)
+ fep->mii_bus->irq[i] = PHY_POLL;
+
+- if (mdiobus_register(fep->mii_bus))
++ node = of_get_child_by_name(pdev->dev.of_node, "mdio");
++ if (node) {
++ err = of_mdiobus_register(fep->mii_bus, node);
++ of_node_put(node);
++ } else {
++ err = mdiobus_register(fep->mii_bus);
++ }
++
++ if (err)
+ goto err_out_free_mdio_irq;
+
+ mii_cnt++;
+
+ /* save fec0 mii_bus */
+- if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
++ if (fep->quirks & FEC_QUIRK_ENET_MAC) {
+ fec0_mii_bus = fep->mii_bus;
++ fec_mii_bus_share = &fep->mii_bus_share;
++ }
+
+ return 0;
+
+@@ -1508,6 +2165,9 @@
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
++ if (!fep->phy_dev)
++ return -ENODEV;
++
+ if (pause->tx_pause != pause->rx_pause) {
+ netdev_info(ndev,
+ "hardware only support enable/disable both tx and rx");
+@@ -1533,8 +2193,14 @@
+ fec_stop(ndev);
+ phy_start_aneg(fep->phy_dev);
+ }
+- if (netif_running(ndev))
+- fec_restart(ndev, 0);
++ if (netif_running(ndev)) {
++ napi_disable(&fep->napi);
++ netif_tx_lock_bh(ndev);
++ fec_restart(ndev);
++ netif_wake_queue(ndev);
++ netif_tx_unlock_bh(ndev);
++ napi_enable(&fep->napi);
++ }
+
+ return 0;
+ }
+@@ -1650,22 +2316,246 @@
+ return genphy_restart_aneg(phydev);
+ }
+
++/* ITR clock source is enet system clock (clk_ahb).
++ * TCTT unit is cycle_ns * 64 cycle
++ * So, the ICTT value = X us / (cycle_ns * 64)
++ */
++static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++
++ return us * (fep->itr_clk_rate / 64000) / 1000;
++}
++
++/* Set threshold for interrupt coalescing */
++static void fec_enet_itr_coal_set(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int rx_itr, tx_itr;
++
++ if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
++ return;
++
++ /* Must be greater than zero to avoid unpredictable behavior */
++ if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
++ !fep->tx_time_itr || !fep->tx_pkts_itr)
++ return;
++
++ /* Select enet system clock as Interrupt Coalescing
++ * timer Clock Source
++ */
++ rx_itr = FEC_ITR_CLK_SEL;
++ tx_itr = FEC_ITR_CLK_SEL;
++
++ /* set ICFT and ICTT */
++ rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
++ rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
++ tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
++ tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
++
++ rx_itr |= FEC_ITR_EN;
++ tx_itr |= FEC_ITR_EN;
++
++ writel(tx_itr, fep->hwp + FEC_TXIC0);
++ writel(rx_itr, fep->hwp + FEC_RXIC0);
++ writel(tx_itr, fep->hwp + FEC_TXIC1);
++ writel(rx_itr, fep->hwp + FEC_RXIC1);
++ writel(tx_itr, fep->hwp + FEC_TXIC2);
++ writel(rx_itr, fep->hwp + FEC_RXIC2);
++}
++
++static int
++fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++
++ if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
++ return -EOPNOTSUPP;
++
++ ec->rx_coalesce_usecs = fep->rx_time_itr;
++ ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
++
++ ec->tx_coalesce_usecs = fep->tx_time_itr;
++ ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
++
++ return 0;
++}
++
++static int
++fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ unsigned int cycle;
++
++ if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
++ return -EOPNOTSUPP;
++
++ if (ec->rx_max_coalesced_frames > 255) {
++ pr_err("Rx coalesced frames exceed hardware limiation");
++ return -EINVAL;
++ }
++
++ if (ec->tx_max_coalesced_frames > 255) {
++ pr_err("Tx coalesced frame exceed hardware limiation");
++ return -EINVAL;
++ }
++
++ cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
++ if (cycle > 0xFFFF) {
++ pr_err("Rx coalesed usec exceeed hardware limiation");
++ return -EINVAL;
++ }
++
++ cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
++ if (cycle > 0xFFFF) {
++ pr_err("Rx coalesed usec exceeed hardware limiation");
++ return -EINVAL;
++ }
++
++ fep->rx_time_itr = ec->rx_coalesce_usecs;
++ fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
++
++ fep->tx_time_itr = ec->tx_coalesce_usecs;
++ fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
++
++ fec_enet_itr_coal_set(ndev);
++
++ return 0;
++}
++
++static void fec_enet_itr_coal_init(struct net_device *ndev)
++{
++ struct ethtool_coalesce ec;
++
++ ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
++ ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
++
++ ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
++ ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
++
++ fec_enet_set_coalesce(ndev, &ec);
++}
++
++static int fec_enet_get_tunable(struct net_device *netdev,
++ const struct ethtool_tunable *tuna,
++ void *data)
++{
++ struct fec_enet_private *fep = netdev_priv(netdev);
++ int ret = 0;
++
++ switch (tuna->id) {
++ case ETHTOOL_RX_COPYBREAK:
++ *(u32 *)data = fep->rx_copybreak;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++static int fec_enet_set_tunable(struct net_device *netdev,
++ const struct ethtool_tunable *tuna,
++ const void *data)
++{
++ struct fec_enet_private *fep = netdev_priv(netdev);
++ int ret = 0;
++
++ switch (tuna->id) {
++ case ETHTOOL_RX_COPYBREAK:
++ fep->rx_copybreak = *(u32 *)data;
++ break;
++ default:
++ ret = -EINVAL;
++ break;
++ }
++
++ return ret;
++}
++
++static void
++fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++
++ if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
++ wol->supported = WAKE_MAGIC;
++ wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
++ } else {
++ wol->supported = wol->wolopts = 0;
++ }
++}
++
++static int
++fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++
++ if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
++ return -EINVAL;
++
++ if (wol->wolopts & ~WAKE_MAGIC)
++ return -EINVAL;
++
++ device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
++ if (device_may_wakeup(&ndev->dev)) {
++ fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
++ if (fep->irq[0] > 0)
++ enable_irq_wake(fep->irq[0]);
++ } else {
++ fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
++ if (fep->irq[0] > 0)
++ disable_irq_wake(fep->irq[0]);
++ }
++
++ return 0;
++}
++
++static int fec_enet_get_eee(struct net_device *ndev, struct ethtool_eee *eee)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct phy_device *phydev = fep->phy_dev;
++
++ if (!phydev)
++ return -ENODEV;
++
++ return phy_ethtool_get_eee(phydev, eee);
++}
++
++static int fec_enet_set_eee(struct net_device *ndev, struct ethtool_eee *eee)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct phy_device *phydev = fep->phy_dev;
++
++ if (!phydev)
++ return -ENODEV;
++
++ return phy_ethtool_set_eee(phydev, eee);
++}
++
+ static const struct ethtool_ops fec_enet_ethtool_ops = {
+-#if !defined(CONFIG_M5272)
+- .get_pauseparam = fec_enet_get_pauseparam,
+- .set_pauseparam = fec_enet_set_pauseparam,
+-#endif
+ .get_settings = fec_enet_get_settings,
+ .set_settings = fec_enet_set_settings,
+ .get_drvinfo = fec_enet_get_drvinfo,
+- .get_link = ethtool_op_get_link,
+- .get_ts_info = fec_enet_get_ts_info,
+ .nway_reset = fec_enet_nway_reset,
++ .get_link = ethtool_op_get_link,
++ .get_coalesce = fec_enet_get_coalesce,
++ .set_coalesce = fec_enet_set_coalesce,
+ #ifndef CONFIG_M5272
+- .get_ethtool_stats = fec_enet_get_ethtool_stats,
++ .get_pauseparam = fec_enet_get_pauseparam,
++ .set_pauseparam = fec_enet_set_pauseparam,
+ .get_strings = fec_enet_get_strings,
++ .get_ethtool_stats = fec_enet_get_ethtool_stats,
+ .get_sset_count = fec_enet_get_sset_count,
+ #endif
++ .get_ts_info = fec_enet_get_ts_info,
++ .get_tunable = fec_enet_get_tunable,
++ .set_tunable = fec_enet_set_tunable,
++ .get_wol = fec_enet_get_wol,
++ .set_wol = fec_enet_set_wol,
++ .get_eee = fec_enet_get_eee,
++ .set_eee = fec_enet_set_eee,
+ };
+
+ static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
+@@ -1676,67 +2566,155 @@
+ if (!netif_running(ndev))
+ return -EINVAL;
+
+- if (!phydev)
+- return -ENODEV;
++ if (!phydev)
++ return -ENODEV;
++
++ if (fep->bufdesc_ex) {
++ if (cmd == SIOCSHWTSTAMP)
++ return fec_ptp_set(ndev, rq);
++ if (cmd == SIOCGHWTSTAMP)
++ return fec_ptp_get(ndev, rq);
++ }
++
++ return phy_mii_ioctl(phydev, rq, cmd);
++}
++
++static void fec_enet_free_buffers(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ unsigned int i;
++ struct sk_buff *skb;
++ struct bufdesc *bdp;
++ struct fec_enet_priv_tx_q *txq;
++ struct fec_enet_priv_rx_q *rxq;
++ unsigned int q;
++
++ for (q = 0; q < fep->num_rx_queues; q++) {
++ rxq = fep->rx_queue[q];
++ bdp = rxq->rx_bd_base;
++ for (i = 0; i < rxq->rx_ring_size; i++) {
++ skb = rxq->rx_skbuff[i];
++ rxq->rx_skbuff[i] = NULL;
++ if (skb) {
++ dma_unmap_single(&fep->pdev->dev,
++ bdp->cbd_bufaddr,
++ FEC_ENET_RX_FRSIZE - fep->rx_align,
++ DMA_FROM_DEVICE);
++ dev_kfree_skb(skb);
++ }
++ bdp = fec_enet_get_nextdesc(bdp, fep, q);
++ }
++ }
++
++ for (q = 0; q < fep->num_tx_queues; q++) {
++ txq = fep->tx_queue[q];
++ bdp = txq->tx_bd_base;
++ for (i = 0; i < txq->tx_ring_size; i++) {
++ kfree(txq->tx_bounce[i]);
++ txq->tx_bounce[i] = NULL;
++ skb = txq->tx_skbuff[i];
++ txq->tx_skbuff[i] = NULL;
++ dev_kfree_skb(skb);
++ }
++ }
++}
++
++static void fec_enet_free_queue(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ int i;
++ struct fec_enet_priv_tx_q *txq;
+
+- if (fep->bufdesc_ex) {
+- if (cmd == SIOCSHWTSTAMP)
+- return fec_ptp_set(ndev, rq);
+- if (cmd == SIOCGHWTSTAMP)
+- return fec_ptp_get(ndev, rq);
+- }
++ for (i = 0; i < fep->num_tx_queues; i++)
++ if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
++ txq = fep->tx_queue[i];
++ dma_free_coherent(NULL,
++ txq->tx_ring_size * TSO_HEADER_SIZE,
++ txq->tso_hdrs,
++ txq->tso_hdrs_dma);
++ }
+
+- return phy_mii_ioctl(phydev, rq, cmd);
++ for (i = 0; i < fep->num_rx_queues; i++)
++ if (fep->rx_queue[i])
++ kfree(fep->rx_queue[i]);
++
++ for (i = 0; i < fep->num_tx_queues; i++)
++ if (fep->tx_queue[i])
++ kfree(fep->tx_queue[i]);
+ }
+
+-static void fec_enet_free_buffers(struct net_device *ndev)
++static int fec_enet_alloc_queue(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- unsigned int i;
+- struct sk_buff *skb;
+- struct bufdesc *bdp;
++ int i;
++ int ret = 0;
++ struct fec_enet_priv_tx_q *txq;
++
++ for (i = 0; i < fep->num_tx_queues; i++) {
++ txq = kzalloc(sizeof(*txq), GFP_KERNEL);
++ if (!txq) {
++ ret = -ENOMEM;
++ goto alloc_failed;
++ }
+
+- bdp = fep->rx_bd_base;
+- for (i = 0; i < fep->rx_ring_size; i++) {
+- skb = fep->rx_skbuff[i];
++ fep->tx_queue[i] = txq;
++ txq->tx_ring_size = TX_RING_SIZE;
++ fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
+
+- if (bdp->cbd_bufaddr)
+- dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
+- FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+- if (skb)
+- dev_kfree_skb(skb);
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
++ txq->tx_wake_threshold =
++ (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
++
++ txq->tso_hdrs = dma_alloc_coherent(NULL,
++ txq->tx_ring_size * TSO_HEADER_SIZE,
++ &txq->tso_hdrs_dma,
++ GFP_KERNEL);
++ if (!txq->tso_hdrs) {
++ ret = -ENOMEM;
++ goto alloc_failed;
++ }
++ }
++
++ for (i = 0; i < fep->num_rx_queues; i++) {
++ fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
++ GFP_KERNEL);
++ if (!fep->rx_queue[i]) {
++ ret = -ENOMEM;
++ goto alloc_failed;
++ }
++
++ fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
++ fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
+ }
++ return ret;
+
+- bdp = fep->tx_bd_base;
+- for (i = 0; i < fep->tx_ring_size; i++)
+- kfree(fep->tx_bounce[i]);
++alloc_failed:
++ fec_enet_free_queue(ndev);
++ return ret;
+ }
+
+-static int fec_enet_alloc_buffers(struct net_device *ndev)
++static int
++fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ unsigned int i;
+ struct sk_buff *skb;
+ struct bufdesc *bdp;
++ struct fec_enet_priv_rx_q *rxq;
+
+- bdp = fep->rx_bd_base;
+- for (i = 0; i < fep->rx_ring_size; i++) {
++ rxq = fep->rx_queue[queue];
++ bdp = rxq->rx_bd_base;
++ for (i = 0; i < rxq->rx_ring_size; i++) {
+ skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
+- if (!skb) {
+- fec_enet_free_buffers(ndev);
+- return -ENOMEM;
+- }
+- fep->rx_skbuff[i] = skb;
++ if (!skb)
++ goto err_alloc;
+
+- bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
+- FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
+- if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
+- fec_enet_free_buffers(ndev);
+- if (net_ratelimit())
+- netdev_err(ndev, "Rx DMA memory map failed\n");
+- return -ENOMEM;
++ if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
++ dev_kfree_skb(skb);
++ goto err_alloc;
+ }
++
++ rxq->rx_skbuff[i] = skb;
+ bdp->cbd_sc = BD_ENET_RX_EMPTY;
+
+ if (fep->bufdesc_ex) {
+@@ -1744,16 +2722,33 @@
+ ebdp->cbd_esc = BD_ENET_RX_INT;
+ }
+
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue);
+ }
+
+ /* Set the last buffer to wrap. */
+- bdp = fec_enet_get_prevdesc(bdp, fep);
++ bdp = fec_enet_get_prevdesc(bdp, fep, queue);
+ bdp->cbd_sc |= BD_SC_WRAP;
++ return 0;
++
++ err_alloc:
++ fec_enet_free_buffers(ndev);
++ return -ENOMEM;
++}
++
++static int
++fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ unsigned int i;
++ struct bufdesc *bdp;
++ struct fec_enet_priv_tx_q *txq;
+
+- bdp = fep->tx_bd_base;
+- for (i = 0; i < fep->tx_ring_size; i++) {
+- fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
++ txq = fep->tx_queue[queue];
++ bdp = txq->tx_bd_base;
++ for (i = 0; i < txq->tx_ring_size; i++) {
++ txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
++ if (!txq->tx_bounce[i])
++ goto err_alloc;
+
+ bdp->cbd_sc = 0;
+ bdp->cbd_bufaddr = 0;
+@@ -1763,42 +2758,104 @@
+ ebdp->cbd_esc = BD_ENET_TX_INT;
+ }
+
+- bdp = fec_enet_get_nextdesc(bdp, fep);
++ bdp = fec_enet_get_nextdesc(bdp, fep, queue);
+ }
+
+ /* Set the last buffer to wrap. */
+- bdp = fec_enet_get_prevdesc(bdp, fep);
++ bdp = fec_enet_get_prevdesc(bdp, fep, queue);
+ bdp->cbd_sc |= BD_SC_WRAP;
+
+ return 0;
++
++ err_alloc:
++ fec_enet_free_buffers(ndev);
++ return -ENOMEM;
++}
++
++static int fec_enet_alloc_buffers(struct net_device *ndev)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ unsigned int i;
++
++ for (i = 0; i < fep->num_rx_queues; i++)
++ if (fec_enet_alloc_rxq_buffers(ndev, i))
++ return -ENOMEM;
++
++ for (i = 0; i < fep->num_tx_queues; i++)
++ if (fec_enet_alloc_txq_buffers(ndev, i))
++ return -ENOMEM;
++ return 0;
++}
++
++static inline bool fec_enet_irq_workaround(struct fec_enet_private *fep)
++{
++ struct device_node *np = fep->pdev->dev.of_node;
++ struct device_node *intr_node;
++
++ intr_node = of_parse_phandle(np, "interrupts-extended", 0);
++ if (intr_node && !strcmp(intr_node->name, "gpio")) {
++ /*
++ * If the interrupt controller is a GPIO node, it must have
++ * applied the workaround for WAIT mode bug.
++ */
++ return true;
++ }
++
++ return false;
+ }
+
+ static int
+ fec_enet_open(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ const struct platform_device_id *id_entry =
++ platform_get_device_id(fep->pdev);
+ int ret;
+
++ pinctrl_pm_select_default_state(&fep->pdev->dev);
++ ret = fec_enet_clk_enable(ndev, true);
++ if (ret)
++ return ret;
++
+ /* I should reset the ring buffers here, but I don't yet know
+ * a simple way to do that.
+ */
+
+ ret = fec_enet_alloc_buffers(ndev);
+ if (ret)
+- return ret;
++ goto err_enet_alloc;
+
+- /* Probe and connect to PHY when open the interface */
+- ret = fec_enet_mii_probe(ndev);
+- if (ret) {
+- fec_enet_free_buffers(ndev);
+- return ret;
++ if (!fep->phy_dev) {
++ ret = fec_enet_mii_probe(ndev);
++ if (ret)
++ goto err_enet_alloc;
+ }
+
++ fec_restart(ndev);
+ napi_enable(&fep->napi);
+ phy_start(fep->phy_dev);
+- netif_start_queue(ndev);
+- fep->opened = 1;
++ netif_tx_start_all_queues(ndev);
++
++ pm_runtime_get_sync(ndev->dev.parent);
++ if ((id_entry->driver_data & FEC_QUIRK_BUG_WAITMODE) &&
++ !fec_enet_irq_workaround(fep))
++ pm_qos_add_request(&ndev->pm_qos_req,
++ PM_QOS_CPU_DMA_LATENCY,
++ 0);
++ else
++ pm_qos_add_request(&ndev->pm_qos_req,
++ PM_QOS_CPU_DMA_LATENCY,
++ PM_QOS_DEFAULT_VALUE);
++
++ device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
++ FEC_WOL_FLAG_ENABLE);
++
+ return 0;
++
++err_enet_alloc:
++ if (!fep->mii_bus_share)
++ pinctrl_pm_select_sleep_state(&fep->pdev->dev);
++ return ret;
+ }
+
+ static int
+@@ -1806,17 +2863,21 @@
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+- /* Don't know what to do yet. */
+- napi_disable(&fep->napi);
+- fep->opened = 0;
+- netif_stop_queue(ndev);
+- fec_stop(ndev);
++ phy_stop(fep->phy_dev);
+
+- if (fep->phy_dev) {
+- phy_stop(fep->phy_dev);
+- phy_disconnect(fep->phy_dev);
++ if (netif_device_present(ndev)) {
++ napi_disable(&fep->napi);
++ netif_tx_disable(ndev);
++ fec_stop(ndev);
+ }
+
++ phy_disconnect(fep->phy_dev);
++ fep->phy_dev = NULL;
++
++ fec_enet_clk_enable(ndev, false);
++ pm_qos_remove_request(&ndev->pm_qos_req);
++ pinctrl_pm_select_sleep_state(&fep->pdev->dev);
++ pm_runtime_put_sync_suspend(ndev->dev.parent);
+ fec_enet_free_buffers(ndev);
+
+ return 0;
+@@ -1904,10 +2965,11 @@
+ struct fec_enet_private *fep = netdev_priv(ndev);
+ struct sockaddr *addr = p;
+
+- if (!is_valid_ether_addr(addr->sa_data))
+- return -EADDRNOTAVAIL;
+-
+- memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
++ if (addr) {
++ if (!is_valid_ether_addr(addr->sa_data))
++ return -EADDRNOTAVAIL;
++ memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
++ }
+
+ writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
+ (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
+@@ -1940,7 +3002,8 @@
+ }
+ #endif
+
+-static int fec_set_features(struct net_device *netdev,
++#define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
++static inline void fec_enet_set_netdev_features(struct net_device *netdev,
+ netdev_features_t features)
+ {
+ struct fec_enet_private *fep = netdev_priv(netdev);
+@@ -1954,23 +3017,67 @@
+ fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
+ else
+ fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
++ }
++}
+
+- if (netif_running(netdev)) {
+- fec_stop(netdev);
+- fec_restart(netdev, fep->phy_dev->duplex);
+- netif_wake_queue(netdev);
+- } else {
+- fec_restart(netdev, fep->phy_dev->duplex);
+- }
++static int fec_set_features(struct net_device *netdev,
++ netdev_features_t features)
++{
++ struct fec_enet_private *fep = netdev_priv(netdev);
++ netdev_features_t changed = features ^ netdev->features;
++
++ if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
++ napi_disable(&fep->napi);
++ netif_tx_lock_bh(netdev);
++ fec_stop(netdev);
++ fec_enet_set_netdev_features(netdev, features);
++ fec_restart(netdev);
++ netif_tx_wake_all_queues(netdev);
++ netif_tx_unlock_bh(netdev);
++ napi_enable(&fep->napi);
++ } else {
++ fec_enet_set_netdev_features(netdev, features);
+ }
+
+ return 0;
+ }
+
++u16 fec_enet_get_raw_vlan_tci(struct sk_buff *skb)
++{
++ struct vlan_ethhdr *vhdr;
++ unsigned short vlan_TCI = 0;
++
++ if (skb->protocol == ntohs(ETH_P_ALL)) {
++ vhdr = (struct vlan_ethhdr *)(skb->data);
++ vlan_TCI = ntohs(vhdr->h_vlan_TCI);
++ }
++
++ return vlan_TCI;
++}
++
++u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
++ void *accel_priv, select_queue_fallback_t fallback)
++{
++ struct fec_enet_private *fep = netdev_priv(ndev);
++ const struct platform_device_id *id_entry =
++ platform_get_device_id(fep->pdev);
++ u16 vlan_tag;
++
++ if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
++ return skb_tx_hash(ndev, skb);
++
++ vlan_tag = fec_enet_get_raw_vlan_tci(skb);
++ if (!vlan_tag)
++ return vlan_tag;
++
++ return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
++}
++
+ static const struct net_device_ops fec_netdev_ops = {
+ .ndo_open = fec_enet_open,
+ .ndo_stop = fec_enet_close,
+ .ndo_start_xmit = fec_enet_start_xmit,
++ .ndo_select_queue = fec_enet_select_queue,
+ .ndo_set_rx_mode = set_multicast_list,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_validate_addr = eth_validate_addr,
+@@ -1990,34 +3097,75 @@
+ static int fec_enet_init(struct net_device *ndev)
+ {
+ struct fec_enet_private *fep = netdev_priv(ndev);
+- const struct platform_device_id *id_entry =
+- platform_get_device_id(fep->pdev);
++ struct fec_enet_priv_tx_q *txq;
++ struct fec_enet_priv_rx_q *rxq;
+ struct bufdesc *cbd_base;
++ dma_addr_t bd_dma;
++ int bd_size;
++ unsigned int i;
++
++#if defined(CONFIG_ARM)
++ fep->rx_align = 0xf;
++ fep->tx_align = 0xf;
++#else
++ fep->rx_align = 0x3;
++ fep->tx_align = 0x3;
++#endif
++
++ fec_enet_alloc_queue(ndev);
++
++ if (fep->bufdesc_ex)
++ fep->bufdesc_size = sizeof(struct bufdesc_ex);
++ else
++ fep->bufdesc_size = sizeof(struct bufdesc);
++ bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
++ fep->bufdesc_size;
+
+ /* Allocate memory for buffer descriptors. */
+- cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
++ cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
+ GFP_KERNEL);
+- if (!cbd_base)
++ if (!cbd_base) {
+ return -ENOMEM;
++ }
+
+- memset(cbd_base, 0, PAGE_SIZE);
+-
+- fep->netdev = ndev;
++ memset(cbd_base, 0, bd_size);
+
+ /* Get the Ethernet address */
+ fec_get_mac(ndev);
+-
+- /* init the tx & rx ring size */
+- fep->tx_ring_size = TX_RING_SIZE;
+- fep->rx_ring_size = RX_RING_SIZE;
++ /* make sure MAC we just acquired is programmed into the hw */
++ fec_set_mac_address(ndev, NULL);
+
+ /* Set receive and transmit descriptor base. */
+- fep->rx_bd_base = cbd_base;
+- if (fep->bufdesc_ex)
+- fep->tx_bd_base = (struct bufdesc *)
+- (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
+- else
+- fep->tx_bd_base = cbd_base + fep->rx_ring_size;
++ for (i = 0; i < fep->num_rx_queues; i++) {
++ rxq = fep->rx_queue[i];
++ rxq->index = i;
++ rxq->rx_bd_base = (struct bufdesc *)cbd_base;
++ rxq->bd_dma = bd_dma;
++ if (fep->bufdesc_ex) {
++ bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
++ cbd_base = (struct bufdesc *)
++ (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
++ } else {
++ bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
++ cbd_base += rxq->rx_ring_size;
++ }
++ }
++
++ for (i = 0; i < fep->num_tx_queues; i++) {
++ txq = fep->tx_queue[i];
++ txq->index = i;
++ txq->tx_bd_base = (struct bufdesc *)cbd_base;
++ txq->bd_dma = bd_dma;
++ if (fep->bufdesc_ex) {
++ bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
++ cbd_base = (struct bufdesc *)
++ (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
++ } else {
++ bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
++ cbd_base += txq->tx_ring_size;
++ }
++ }
++
+
+ /* The FEC Ethernet specific entries in the device structure */
+ ndev->watchdog_timeo = TX_TIMEOUT;
+@@ -2027,22 +3175,27 @@
+ writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
+ netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
+
+- if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
++ if (fep->quirks & FEC_QUIRK_HAS_VLAN)
+ /* enable hw VLAN support */
+ ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
+- ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
+- }
+
+- if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
++ if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
++ ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
++
+ /* enable hw accelerator */
+ ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
+- | NETIF_F_RXCSUM);
+- ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
+- | NETIF_F_RXCSUM);
++ | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
+ fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
+ }
+
+- fec_restart(ndev, 0);
++ if (fep->quirks & FEC_QUIRK_HAS_AVB) {
++ fep->tx_align = 0;
++ fep->rx_align = 0x3f;
++ }
++
++ ndev->hw_features = ndev->features;
++
++ fec_restart(ndev);
+
+ return 0;
+ }
+@@ -2085,6 +3238,42 @@
+ }
+ #endif /* CONFIG_OF */
+
++static void
++fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++
++ *num_tx = *num_rx = 1;
++
++ if (!np || !of_device_is_available(np))
++ return;
++
++ /* parse the num of tx and rx queues */
++ err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
++ if (err)
++ *num_tx = 1;
++
++ err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
++ if (err)
++ *num_rx = 1;
++
++ if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
++ dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
++ *num_tx);
++ *num_tx = 1;
++ return;
++ }
++
++ if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
++ dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
++ *num_rx);
++ *num_rx = 1;
++ return;
++ }
++
++}
++
+ static int
+ fec_probe(struct platform_device *pdev)
+ {
+@@ -2095,13 +3284,15 @@
+ struct resource *r;
+ const struct of_device_id *of_id;
+ static int dev_id;
++ struct device_node *np = pdev->dev.of_node, *phy_node;
++ int num_tx_qs;
++ int num_rx_qs;
+
+- of_id = of_match_device(fec_dt_ids, &pdev->dev);
+- if (of_id)
+- pdev->id_entry = of_id->data;
++ fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
+
+ /* Init network device */
+- ndev = alloc_etherdev(sizeof(struct fec_enet_private));
++ ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
++ num_tx_qs, num_rx_qs);
+ if (!ndev)
+ return -ENOMEM;
+
+@@ -2110,13 +3301,24 @@
+ /* setup board info structure */
+ fep = netdev_priv(ndev);
+
++ of_id = of_match_device(fec_dt_ids, &pdev->dev);
++ if (of_id)
++ pdev->id_entry = of_id->data;
++ fep->quirks = pdev->id_entry->driver_data;
++
++ fep->netdev = ndev;
++ fep->num_rx_queues = num_rx_qs;
++ fep->num_tx_queues = num_tx_qs;
++
+ #if !defined(CONFIG_M5272)
+ /* default enable pause frame auto negotiation */
+- if (pdev->id_entry &&
+- (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
++ if (fep->quirks & FEC_QUIRK_HAS_GBIT)
+ fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
+ #endif
+
++ /* Select default pin state */
++ pinctrl_pm_select_default_state(&pdev->dev);
++
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ fep->hwp = devm_ioremap_resource(&pdev->dev, r);
+ if (IS_ERR(fep->hwp)) {
+@@ -2127,10 +3329,23 @@
+ fep->pdev = pdev;
+ fep->dev_id = dev_id++;
+
+- fep->bufdesc_ex = 0;
+-
+ platform_set_drvdata(pdev, ndev);
+
++ if (of_get_property(np, "fsl,magic-packet", NULL))
++ fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
++
++ phy_node = of_parse_phandle(np, "phy-handle", 0);
++ if (!phy_node && of_phy_is_fixed_link(np)) {
++ ret = of_phy_register_fixed_link(np);
++ if (ret < 0) {
++ dev_err(&pdev->dev,
++ "broken fixed-link specification\n");
++ goto failed_phy;
++ }
++ phy_node = of_node_get(np);
++ }
++ fep->phy_node = phy_node;
++
+ ret = of_get_phy_mode(pdev->dev.of_node);
+ if (ret < 0) {
+ pdata = dev_get_platdata(&pdev->dev);
+@@ -2154,39 +3369,33 @@
+ goto failed_clk;
+ }
+
++ fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
++
+ /* enet_out is optional, depends on board */
+ fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
+ if (IS_ERR(fep->clk_enet_out))
+ fep->clk_enet_out = NULL;
+
++ fep->ptp_clk_on = false;
++ mutex_init(&fep->ptp_clk_mutex);
++
++ /* clk_ref is optional, depends on board */
++ fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
++ if (IS_ERR(fep->clk_ref))
++ fep->clk_ref = NULL;
++
++ fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
+ fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
+- fep->bufdesc_ex =
+- pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
+ if (IS_ERR(fep->clk_ptp)) {
+ fep->clk_ptp = NULL;
+- fep->bufdesc_ex = 0;
++ fep->bufdesc_ex = false;
+ }
+
+- ret = clk_prepare_enable(fep->clk_ahb);
++ pm_runtime_enable(&pdev->dev);
++ ret = fec_enet_clk_enable(ndev, true);
+ if (ret)
+ goto failed_clk;
+
+- ret = clk_prepare_enable(fep->clk_ipg);
+- if (ret)
+- goto failed_clk_ipg;
+-
+- if (fep->clk_enet_out) {
+- ret = clk_prepare_enable(fep->clk_enet_out);
+- if (ret)
+- goto failed_clk_enet_out;
+- }
+-
+- if (fep->clk_ptp) {
+- ret = clk_prepare_enable(fep->clk_ptp);
+- if (ret)
+- goto failed_clk_ptp;
+- }
+-
+ fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
+ if (!IS_ERR(fep->reg_phy)) {
+ ret = regulator_enable(fep->reg_phy);
+@@ -2220,8 +3429,11 @@
+ 0, pdev->name, ndev);
+ if (ret)
+ goto failed_irq;
++
++ fep->irq[i] = irq;
+ }
+
++ init_completion(&fep->mdio_done);
+ ret = fec_enet_mii_init(pdev);
+ if (ret)
+ goto failed_mii_init;
+@@ -2233,30 +3445,40 @@
+ if (ret)
+ goto failed_register;
+
++ ret = fec_enet_mii_probe(ndev);
++ if (ret)
++ goto failed_mii_probe;
++
++ phy_start_aneg(fep->phy_dev);
++
++ device_init_wakeup(&ndev->dev, fep->wol_flag &
++ FEC_WOL_HAS_MAGIC_PACKET);
++
+ if (fep->bufdesc_ex && fep->ptp_clock)
+ netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
+
+- INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
++ fep->rx_copybreak = COPYBREAK_DEFAULT;
++ INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
+ return 0;
+
++failed_mii_probe:
++ unregister_netdev(ndev);
+ failed_register:
+ fec_enet_mii_remove(fep);
+ failed_mii_init:
+ failed_irq:
+ failed_init:
++ if (fep->bufdesc_ex)
++ cancel_delayed_work_sync(&fep->time_keep);
+ if (fep->reg_phy)
+ regulator_disable(fep->reg_phy);
++ if (fep->ptp_clock)
++ ptp_clock_unregister(fep->ptp_clock);
+ failed_regulator:
+- if (fep->clk_ptp)
+- clk_disable_unprepare(fep->clk_ptp);
+-failed_clk_ptp:
+- if (fep->clk_enet_out)
+- clk_disable_unprepare(fep->clk_enet_out);
+-failed_clk_enet_out:
+- clk_disable_unprepare(fep->clk_ipg);
+-failed_clk_ipg:
+- clk_disable_unprepare(fep->clk_ahb);
++ fec_enet_clk_enable(ndev, false);
+ failed_clk:
++failed_phy:
++ of_node_put(phy_node);
+ failed_ioremap:
+ free_netdev(ndev);
+
+@@ -2269,104 +3491,125 @@
+ struct net_device *ndev = platform_get_drvdata(pdev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
+- cancel_delayed_work_sync(&(fep->delay_work.delay_work));
++ if (fep->bufdesc_ex)
++ cancel_delayed_work_sync(&fep->time_keep);
++ cancel_work_sync(&fep->tx_timeout_work);
+ unregister_netdev(ndev);
+ fec_enet_mii_remove(fep);
+- del_timer_sync(&fep->time_keep);
+ if (fep->reg_phy)
+ regulator_disable(fep->reg_phy);
+- if (fep->clk_ptp)
+- clk_disable_unprepare(fep->clk_ptp);
+ if (fep->ptp_clock)
+ ptp_clock_unregister(fep->ptp_clock);
+- if (fep->clk_enet_out)
+- clk_disable_unprepare(fep->clk_enet_out);
+- clk_disable_unprepare(fep->clk_ipg);
+- clk_disable_unprepare(fep->clk_ahb);
++ fec_enet_clk_enable(ndev, false);
++ of_node_put(fep->phy_node);
+ free_netdev(ndev);
+
+ return 0;
+ }
+
+-#ifdef CONFIG_PM_SLEEP
+-static int
+-fec_suspend(struct device *dev)
++static int __maybe_unused fec_suspend(struct device *dev)
+ {
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
+
++ rtnl_lock();
+ if (netif_running(ndev)) {
+- fec_stop(ndev);
++ if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
++ fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
++ phy_stop(fep->phy_dev);
++ napi_disable(&fep->napi);
++ netif_tx_lock_bh(ndev);
+ netif_device_detach(ndev);
++ netif_tx_unlock_bh(ndev);
++ fec_stop(ndev);
++ if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
++ pinctrl_pm_select_sleep_state(&fep->pdev->dev);
++ fec_enet_clk_enable(ndev, false);
++ } else if (fep->mii_bus_share && !fep->phy_dev) {
++ fec_enet_clk_enable(ndev, false);
++ pinctrl_pm_select_sleep_state(&fep->pdev->dev);
+ }
+- if (fep->clk_ptp)
+- clk_disable_unprepare(fep->clk_ptp);
+- if (fep->clk_enet_out)
+- clk_disable_unprepare(fep->clk_enet_out);
+- clk_disable_unprepare(fep->clk_ipg);
+- clk_disable_unprepare(fep->clk_ahb);
++ rtnl_unlock();
+
+- if (fep->reg_phy)
++ if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
+ regulator_disable(fep->reg_phy);
+
++ /* SOC supply clock to phy, when clock is disabled, phy link down
++ * SOC control phy regulator, when regulator is disabled, phy link down
++ */
++ if (fep->clk_enet_out || fep->reg_phy)
++ fep->link = 0;
++
+ return 0;
+ }
+
+-static int
+-fec_resume(struct device *dev)
++static int __maybe_unused fec_resume(struct device *dev)
+ {
+ struct net_device *ndev = dev_get_drvdata(dev);
+ struct fec_enet_private *fep = netdev_priv(ndev);
++ struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
+ int ret;
++ int val;
+
+- if (fep->reg_phy) {
++ if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
+ ret = regulator_enable(fep->reg_phy);
+ if (ret)
+ return ret;
+ }
+
+- ret = clk_prepare_enable(fep->clk_ahb);
+- if (ret)
+- goto failed_clk_ahb;
+-
+- ret = clk_prepare_enable(fep->clk_ipg);
+- if (ret)
+- goto failed_clk_ipg;
+-
+- if (fep->clk_enet_out) {
+- ret = clk_prepare_enable(fep->clk_enet_out);
+- if (ret)
+- goto failed_clk_enet_out;
+- }
+-
+- if (fep->clk_ptp) {
+- ret = clk_prepare_enable(fep->clk_ptp);
+- if (ret)
+- goto failed_clk_ptp;
+- }
+-
++ rtnl_lock();
+ if (netif_running(ndev)) {
+- fec_restart(ndev, fep->full_duplex);
++ ret = fec_enet_clk_enable(ndev, true);
++ if (ret) {
++ rtnl_unlock();
++ goto failed_clk;
++ }
++ if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
++ if (pdata && pdata->sleep_mode_enable)
++ pdata->sleep_mode_enable(false);
++ val = readl(fep->hwp + FEC_ECNTRL);
++ val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
++ writel(val, fep->hwp + FEC_ECNTRL);
++ fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
++ } else {
++ pinctrl_pm_select_default_state(&fep->pdev->dev);
++ }
++ fec_restart(ndev);
++ netif_tx_lock_bh(ndev);
+ netif_device_attach(ndev);
++ netif_tx_unlock_bh(ndev);
++ napi_enable(&fep->napi);
++ phy_start(fep->phy_dev);
++ } else if (fep->mii_bus_share && !fep->phy_dev) {
++ pinctrl_pm_select_default_state(&fep->pdev->dev);
++ fec_restore_mii_bus(ndev);
+ }
++ rtnl_unlock();
+
+ return 0;
+
+-failed_clk_ptp:
+- if (fep->clk_enet_out)
+- clk_disable_unprepare(fep->clk_enet_out);
+-failed_clk_enet_out:
+- clk_disable_unprepare(fep->clk_ipg);
+-failed_clk_ipg:
+- clk_disable_unprepare(fep->clk_ahb);
+-failed_clk_ahb:
++failed_clk:
+ if (fep->reg_phy)
+ regulator_disable(fep->reg_phy);
+ return ret;
+ }
+-#endif /* CONFIG_PM_SLEEP */
+
+-static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
++static int fec_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int fec_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static const struct dev_pm_ops fec_pm_ops = {
++ SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
++};
+
+ static struct platform_driver fec_driver = {
+ .driver = {
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/freescale/fec_ptp.c linux-3.14.72/drivers/net/ethernet/freescale/fec_ptp.c
+--- linux-3.14.72.orig/drivers/net/ethernet/freescale/fec_ptp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/freescale/fec_ptp.c 2016-06-19 22:11:55.265142632 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Fast Ethernet Controller (ENET) PTP driver for MX6x.
+ *
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+@@ -61,6 +61,24 @@
+ #define FEC_T_INC_CORR_MASK 0x00007f00
+ #define FEC_T_INC_CORR_OFFSET 8
+
++#define FEC_T_CTRL_PINPER 0x00000080
++#define FEC_T_TF0_MASK 0x00000001
++#define FEC_T_TF0_OFFSET 0
++#define FEC_T_TF1_MASK 0x00000002
++#define FEC_T_TF1_OFFSET 1
++#define FEC_T_TF2_MASK 0x00000004
++#define FEC_T_TF2_OFFSET 2
++#define FEC_T_TF3_MASK 0x00000008
++#define FEC_T_TF3_OFFSET 3
++#define FEC_T_TDRE_MASK 0x00000001
++#define FEC_T_TDRE_OFFSET 0
++#define FEC_T_TMODE_MASK 0x0000003C
++#define FEC_T_TMODE_OFFSET 2
++#define FEC_T_TIE_MASK 0x00000040
++#define FEC_T_TIE_OFFSET 6
++#define FEC_T_TF_MASK 0x00000080
++#define FEC_T_TF_OFFSET 7
++
+ #define FEC_ATIME_CTRL 0x400
+ #define FEC_ATIME 0x404
+ #define FEC_ATIME_EVT_OFFSET 0x408
+@@ -69,7 +87,143 @@
+ #define FEC_ATIME_INC 0x414
+ #define FEC_TS_TIMESTAMP 0x418
+
++#define FEC_TGSR 0x604
++#define FEC_TCSR(n) (0x608 + n * 0x08)
++#define FEC_TCCR(n) (0x60C + n * 0x08)
++#define MAX_TIMER_CHANNEL 3
++#define FEC_TMODE_TOGGLE 0x05
++#define FEC_HIGH_PULSE 0x0F
++
+ #define FEC_CC_MULT (1 << 31)
++#define FEC_COUNTER_PERIOD (1 << 31)
++#define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC
++#define FEC_CHANNLE_0 0
++#define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0
++
++/**
++ * fec_ptp_enable_pps
++ * @fep: the fec_enet_private structure handle
++ * @enable: enable the channel pps output
++ *
++ * This function enble the PPS ouput on the timer channel.
++ */
++static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
++{
++ unsigned long flags;
++ u32 val, tempval;
++ int inc;
++ struct timespec ts;
++ u64 ns;
++ u32 remainder;
++ val = 0;
++
++ if (!(fep->hwts_tx_en || fep->hwts_rx_en)) {
++ dev_err(&fep->pdev->dev, "No ptp stack is running\n");
++ return -EINVAL;
++ }
++
++ if (fep->pps_enable == enable)
++ return 0;
++
++ fep->pps_channel = DEFAULT_PPS_CHANNEL;
++ fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
++ inc = fep->ptp_inc;
++
++ spin_lock_irqsave(&fep->tmreg_lock, flags);
++
++ if (enable) {
++ /* clear capture or output compare interrupt status if have.
++ */
++ writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
++
++ /* It is recommended to doulbe check the TMODE field in the
++ * TCSR register to be cleared before the first compare counter
++ * is written into TCCR register. Just add a double check.
++ */
++ val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
++ do {
++ val &= ~(FEC_T_TMODE_MASK);
++ writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
++ val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
++ } while (val & FEC_T_TMODE_MASK);
++
++ /* Dummy read counter to update the counter */
++ timecounter_read(&fep->tc);
++ /* We want to find the first compare event in the next
++ * second point. So we need to know what the ptp time
++ * is now and how many nanoseconds is ahead to get next second.
++ * The remaining nanosecond ahead before the next second would be
++ * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
++ * to current timer would be next second.
++ */
++ tempval = readl(fep->hwp + FEC_ATIME_CTRL);
++ tempval |= FEC_T_CTRL_CAPTURE;
++ writel(tempval, fep->hwp + FEC_ATIME_CTRL);
++
++ tempval = readl(fep->hwp + FEC_ATIME);
++ /* Convert the ptp local counter to 1588 timestamp */
++ ns = timecounter_cyc2time(&fep->tc, tempval);
++ ts.tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
++ ts.tv_nsec = remainder;
++
++ /* The tempval is less than 3 seconds, and so val is less than
++ * 4 seconds. No overflow for 32bit calculation.
++ */
++ val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;
++
++ /* Need to consider the situation that the current time is
++ * very close to the second point, which means NSEC_PER_SEC
++ * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
++ * is still running when we calculate the first compare event, it is
++ * possible that the remaining nanoseonds run out before the compare
++ * counter is calculated and written into TCCR register. To avoid
++ * this possibility, we will set the compare event to be the next
++ * of next second. The current setting is 31-bit timer and wrap
++ * around over 2 seconds. So it is okay to set the next of next
++ * seond for the timer.
++ */
++ val += NSEC_PER_SEC;
++
++ /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
++ * ptp counter, which maybe cause 32-bit wrap. Since the
++ * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
++ * We can ensure the wrap will not cause issue. If the offset
++ * is bigger than fep->cc.mask would be a error.
++ */
++ val &= fep->cc.mask;
++ writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
++
++ /* Calculate the second the compare event timestamp */
++ fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
++
++ /* * Enable compare event when overflow */
++ val = readl(fep->hwp + FEC_ATIME_CTRL);
++ val |= FEC_T_CTRL_PINPER;
++ writel(val, fep->hwp + FEC_ATIME_CTRL);
++
++ /* Compare channel setting. */
++ val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
++ val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
++ val &= ~(1 << FEC_T_TDRE_OFFSET);
++ val &= ~(FEC_T_TMODE_MASK);
++ val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET);
++ writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
++
++ /* Write the second compare event timestamp and calculate
++ * the third timestamp. Refer the TCCR register detail in the spec.
++ */
++ writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
++ fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
++ } else {
++ writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
++ }
++
++ fep->pps_enable = enable;
++ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
++
++ return 0;
++}
++
+ /**
+ * fec_ptp_read - read raw cycle counter (to be used by time counter)
+ * @cc: the cyclecounter structure
+@@ -82,12 +236,17 @@
+ {
+ struct fec_enet_private *fep =
+ container_of(cc, struct fec_enet_private, cc);
++ const struct platform_device_id *id_entry =
++ platform_get_device_id(fep->pdev);
+ u32 tempval;
+
+ tempval = readl(fep->hwp + FEC_ATIME_CTRL);
+ tempval |= FEC_T_CTRL_CAPTURE;
+ writel(tempval, fep->hwp + FEC_ATIME_CTRL);
+
++ if (id_entry->driver_data & FEC_QUIRK_TKT210590)
++ udelay(1);
++
+ return readl(fep->hwp + FEC_ATIME);
+ }
+
+@@ -113,14 +272,15 @@
+ /* 1ns counter */
+ writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
+
+- /* use free running count */
+- writel(0, fep->hwp + FEC_ATIME_EVT_PERIOD);
++ /* use 31-bit timer counter */
++ writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
+
+- writel(FEC_T_CTRL_ENABLE, fep->hwp + FEC_ATIME_CTRL);
++ writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
++ fep->hwp + FEC_ATIME_CTRL);
+
+ memset(&fep->cc, 0, sizeof(fep->cc));
+ fep->cc.read = fec_ptp_read;
+- fep->cc.mask = CLOCKSOURCE_MASK(32);
++ fep->cc.mask = CLOCKSOURCE_MASK(31);
+ fep->cc.shift = 31;
+ fep->cc.mult = FEC_CC_MULT;
+
+@@ -143,32 +303,59 @@
+ */
+ static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+ {
+- u64 diff;
+ unsigned long flags;
+ int neg_adj = 0;
+- u32 mult = FEC_CC_MULT;
++ u32 i, tmp;
++ u32 corr_inc, corr_period;
++ u32 corr_ns;
++ u64 lhs, rhs;
+
+ struct fec_enet_private *fep =
+ container_of(ptp, struct fec_enet_private, ptp_caps);
+
++ if (ppb == 0)
++ return 0;
++
+ if (ppb < 0) {
+ ppb = -ppb;
+ neg_adj = 1;
+ }
+
+- diff = mult;
+- diff *= ppb;
+- diff = div_u64(diff, 1000000000ULL);
++ /* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC;
++ * Try to find the corr_inc between 1 to fep->ptp_inc to
++ * meet adjustment requirement.
++ */
++ lhs = NSEC_PER_SEC;
++ rhs = (u64)ppb * (u64)fep->ptp_inc;
++ for (i = 1; i <= fep->ptp_inc; i++) {
++ if (lhs >= rhs) {
++ corr_inc = i;
++ corr_period = div_u64(lhs, rhs);
++ break;
++ }
++ lhs += NSEC_PER_SEC;
++ }
++ /* Not found? Set it to high value - double speed
++ * correct in every clock step.
++ */
++ if (i > fep->ptp_inc) {
++ corr_inc = fep->ptp_inc;
++ corr_period = 1;
++ }
++
++ if (neg_adj)
++ corr_ns = fep->ptp_inc - corr_inc;
++ else
++ corr_ns = fep->ptp_inc + corr_inc;
+
+ spin_lock_irqsave(&fep->tmreg_lock, flags);
+- /*
+- * dummy read to set cycle_last in tc to now.
+- * So use adjusted mult to calculate when next call
+- * timercounter_read.
+- */
+- timecounter_read(&fep->tc);
+
+- fep->cc.mult = neg_adj ? mult - diff : mult + diff;
++ tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
++ tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
++ writel(tmp, fep->hwp + FEC_ATIME_INC);
++ writel(corr_period, fep->hwp + FEC_ATIME_CORR);
++ /* dummy read to update the timer. */
++ timecounter_read(&fep->tc);
+
+ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
+
+@@ -188,12 +375,19 @@
+ container_of(ptp, struct fec_enet_private, ptp_caps);
+ unsigned long flags;
+ u64 now;
++ u32 counter;
+
+ spin_lock_irqsave(&fep->tmreg_lock, flags);
+
+ now = timecounter_read(&fep->tc);
+ now += delta;
+
++ /* Get the timer value based on adjusted timestamp.
++ * Update the counter with the masked value.
++ */
++ counter = now & fep->cc.mask;
++ writel(counter, fep->hwp + FEC_ATIME);
++
+ /* reset the timecounter */
+ timecounter_init(&fep->tc, &fep->cc, now);
+
+@@ -244,13 +438,27 @@
+
+ u64 ns;
+ unsigned long flags;
++ u32 counter;
++
++ mutex_lock(&fep->ptp_clk_mutex);
++ /* Check the ptp clock */
++ if (!fep->ptp_clk_on) {
++ mutex_unlock(&fep->ptp_clk_mutex);
++ return -EINVAL;
++ }
+
+ ns = ts->tv_sec * 1000000000ULL;
+ ns += ts->tv_nsec;
++ /* Get the timer value based on timestamp.
++ * Update the counter with the masked value.
++ */
++ counter = ns & fep->cc.mask;
+
+ spin_lock_irqsave(&fep->tmreg_lock, flags);
++ writel(counter, fep->hwp + FEC_ATIME);
+ timecounter_init(&fep->tc, &fep->cc, ns);
+ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
++ mutex_unlock(&fep->ptp_clk_mutex);
+ return 0;
+ }
+
+@@ -264,6 +472,15 @@
+ static int fec_ptp_enable(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *rq, int on)
+ {
++ struct fec_enet_private *fep =
++ container_of(ptp, struct fec_enet_private, ptp_caps);
++ int ret = 0;
++
++ if (rq->type == PTP_CLK_REQ_PPS) {
++ ret = fec_ptp_enable_pps(fep, on);
++
++ return ret;
++ }
+ return -EOPNOTSUPP;
+ }
+
+@@ -338,17 +555,22 @@
+ * fec_time_keep - call timecounter_read every second to avoid timer overrun
+ * because ENET just support 32bit counter, will timeout in 4s
+ */
+-static void fec_time_keep(unsigned long _data)
++static void fec_time_keep(struct work_struct *work)
+ {
+- struct fec_enet_private *fep = (struct fec_enet_private *)_data;
++ struct delayed_work *dwork = to_delayed_work(work);
++ struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
+ u64 ns;
+ unsigned long flags;
+
+- spin_lock_irqsave(&fep->tmreg_lock, flags);
+- ns = timecounter_read(&fep->tc);
+- spin_unlock_irqrestore(&fep->tmreg_lock, flags);
++ mutex_lock(&fep->ptp_clk_mutex);
++ if (fep->ptp_clk_on) {
++ spin_lock_irqsave(&fep->tmreg_lock, flags);
++ ns = timecounter_read(&fep->tc);
++ spin_unlock_irqrestore(&fep->tmreg_lock, flags);
++ }
++ mutex_unlock(&fep->ptp_clk_mutex);
+
+- mod_timer(&fep->time_keep, jiffies + HZ);
++ schedule_delayed_work(&fep->time_keep, HZ);
+ }
+
+ /**
+@@ -372,7 +594,8 @@
+ fep->ptp_caps.n_alarm = 0;
+ fep->ptp_caps.n_ext_ts = 0;
+ fep->ptp_caps.n_per_out = 0;
+- fep->ptp_caps.pps = 0;
++ fep->ptp_caps.n_pins = 0;
++ fep->ptp_caps.pps = 1;
+ fep->ptp_caps.adjfreq = fec_ptp_adjfreq;
+ fep->ptp_caps.adjtime = fec_ptp_adjtime;
+ fep->ptp_caps.gettime = fec_ptp_gettime;
+@@ -380,20 +603,52 @@
+ fep->ptp_caps.enable = fec_ptp_enable;
+
+ fep->cycle_speed = clk_get_rate(fep->clk_ptp);
++ fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
+
+ spin_lock_init(&fep->tmreg_lock);
+
+ fec_ptp_start_cyclecounter(ndev);
+
+- init_timer(&fep->time_keep);
+- fep->time_keep.data = (unsigned long)fep;
+- fep->time_keep.function = fec_time_keep;
+- fep->time_keep.expires = jiffies + HZ;
+- add_timer(&fep->time_keep);
++ INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
+
+ fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
+ if (IS_ERR(fep->ptp_clock)) {
+ fep->ptp_clock = NULL;
+ pr_err("ptp_clock_register failed\n");
+ }
++
++ schedule_delayed_work(&fep->time_keep, HZ);
++}
++
++/**
++ * fec_ptp_check_pps_event
++ * @fep: the fec_enet_private structure handle
++ *
++ * This function check the pps event and reload the timer compare counter.
++ */
++uint fec_ptp_check_pps_event(struct fec_enet_private *fep)
++{
++ u32 val;
++ u8 channel = fep->pps_channel;
++ struct ptp_clock_event event;
++
++ val = readl(fep->hwp + FEC_TCSR(channel));
++ if (val & FEC_T_TF_MASK) {
++ /* Write the next next compare(not the next according the spec)
++ * value to the register
++ */
++ writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
++ do {
++ writel(val, fep->hwp + FEC_TCSR(channel));
++ } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
++
++ /* Update the counter; */
++ fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
++
++ event.type = PTP_CLOCK_PPS;
++ ptp_clock_event(fep->ptp_clock, &event);
++ return 1;
++ }
++
++ return 0;
+ }
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/freescale/gianfar_ptp.c linux-3.14.72/drivers/net/ethernet/freescale/gianfar_ptp.c
+--- linux-3.14.72.orig/drivers/net/ethernet/freescale/gianfar_ptp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/freescale/gianfar_ptp.c 2016-06-19 22:11:55.265142632 +0200
+@@ -414,6 +414,7 @@
+ .n_alarm = 0,
+ .n_ext_ts = N_EXT_TS,
+ .n_per_out = 0,
++ .n_pins = 0,
+ .pps = 1,
+ .adjfreq = ptp_gianfar_adjfreq,
+ .adjtime = ptp_gianfar_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/intel/e1000e/ptp.c linux-3.14.72/drivers/net/ethernet/intel/e1000e/ptp.c
+--- linux-3.14.72.orig/drivers/net/ethernet/intel/e1000e/ptp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/intel/e1000e/ptp.c 2016-06-19 22:11:55.265142632 +0200
+@@ -191,6 +191,7 @@
+ .n_alarm = 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = e1000e_phc_adjfreq,
+ .adjtime = e1000e_phc_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_82575.c linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_82575.c
+--- linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_82575.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_82575.c 2016-06-19 22:11:55.269142369 +0200
+@@ -606,13 +606,25 @@
+ switch (link_mode) {
+ case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
+ hw->phy.media_type = e1000_media_type_internal_serdes;
++ if (igb_sgmii_uses_mdio_82575(hw)) {
++ u32 mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= E1000_MDICNFG_PHY_MASK;
++ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT;
++ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n",
++ hw->phy.addr);
++ } else {
++ hw_dbg("1000BASE_KX");
++ }
+ break;
+ case E1000_CTRL_EXT_LINK_MODE_SGMII:
+ /* Get phy control interface type set (MDIO vs. I2C)*/
+ if (igb_sgmii_uses_mdio_82575(hw)) {
+ hw->phy.media_type = e1000_media_type_copper;
+ dev_spec->sgmii_active = true;
++ hw_dbg("SGMII with external MDIO PHY");
+ break;
++ } else {
++ hw_dbg("SGMII with external I2C PHY");
+ }
+ /* fall through for I2C based SGMII */
+ case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
+@@ -629,8 +641,11 @@
+ hw->phy.media_type = e1000_media_type_copper;
+ dev_spec->sgmii_active = true;
+ }
++ hw_dbg("SERDES with external SFP");
+
+ break;
++ } else {
++ hw_dbg("SERDES");
+ }
+
+ /* do not change link mode for 100BaseFX */
+@@ -2142,7 +2157,7 @@
+ if (ret_val)
+ goto out;
+
+- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
++ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data);
+
+ hw->phy.ops.release(hw);
+
+@@ -2167,7 +2182,7 @@
+ if (ret_val)
+ goto out;
+
+- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data);
+
+ hw->phy.ops.release(hw);
+
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_hw.h linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_hw.h
+--- linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_hw.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_hw.h 2016-06-19 22:11:55.269142369 +0200
+@@ -32,6 +32,7 @@
+ #include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/netdevice.h>
++#include <linux/phy.h>
+
+ #include "e1000_regs.h"
+ #include "e1000_defines.h"
+@@ -553,6 +554,12 @@
+ struct e1000_mbx_info mbx;
+ struct e1000_host_mng_dhcp_cookie mng_cookie;
+
++#ifdef CONFIG_PHYLIB
++ /* Phylib and MDIO interface */
++ struct mii_bus *mii_bus;
++ struct phy_device *phy_dev;
++ phy_interface_t phy_interface;
++#endif
+ union {
+ struct e1000_dev_spec_82575 _82575;
+ } dev_spec;
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_phy.c linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_phy.c
+--- linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_phy.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_phy.c 2016-06-19 22:11:55.269142369 +0200
+@@ -136,10 +136,9 @@
+ * Reads the MDI control regsiter in the PHY at offset and stores the
+ * information read to data.
+ **/
+-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
++s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
+ {
+- struct e1000_phy_info *phy = &hw->phy;
+- u32 i, mdic = 0;
++ u32 i, mdicnfg, mdic = 0;
+ s32 ret_val = 0;
+
+ if (offset > MAX_PHY_REG_ADDRESS) {
+@@ -152,11 +151,25 @@
+ * Control register. The MAC will take care of interfacing with the
+ * PHY to retrieve the desired data.
+ */
+- mdic = ((offset << E1000_MDIC_REG_SHIFT) |
+- (phy->addr << E1000_MDIC_PHY_SHIFT) |
+- (E1000_MDIC_OP_READ));
++ switch (hw->mac.type) {
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
++ (E1000_MDIC_OP_READ));
++ break;
++ default:
++ mdic = ((offset << E1000_MDIC_REG_SHIFT) |
++ (addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_READ));
++ break;
++ }
+
+ wr32(E1000_MDIC, mdic);
++ wrfl();
+
+ /* Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+@@ -181,6 +194,18 @@
+ *data = (u16) mdic;
+
+ out:
++ switch (hw->mac.type) {
++ /* restore MDICNFG to have phy's addr */
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ break;
++ default:
++ break;
++ }
+ return ret_val;
+ }
+
+@@ -192,10 +217,9 @@
+ *
+ * Writes data to MDI control register in the PHY at offset.
+ **/
+-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
++s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
+ {
+- struct e1000_phy_info *phy = &hw->phy;
+- u32 i, mdic = 0;
++ u32 i, mdicnfg, mdic = 0;
+ s32 ret_val = 0;
+
+ if (offset > MAX_PHY_REG_ADDRESS) {
+@@ -208,12 +232,27 @@
+ * Control register. The MAC will take care of interfacing with the
+ * PHY to retrieve the desired data.
+ */
+- mdic = (((u32)data) |
+- (offset << E1000_MDIC_REG_SHIFT) |
+- (phy->addr << E1000_MDIC_PHY_SHIFT) |
+- (E1000_MDIC_OP_WRITE));
++ switch (hw->mac.type) {
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ mdic = (((u32)data) |
++ (offset << E1000_MDIC_REG_SHIFT) |
++ (E1000_MDIC_OP_WRITE));
++ break;
++ default:
++ mdic = (((u32)data) |
++ (offset << E1000_MDIC_REG_SHIFT) |
++ (addr << E1000_MDIC_PHY_SHIFT) |
++ (E1000_MDIC_OP_WRITE));
++ break;
++ }
+
+ wr32(E1000_MDIC, mdic);
++ wrfl();
+
+ /* Poll the ready bit to see if the MDI read completed
+ * Increasing the time out as testing showed failures with
+@@ -237,6 +276,18 @@
+ }
+
+ out:
++ switch (hw->mac.type) {
++ /* restore MDICNFG to have phy's addr */
++ case e1000_i210:
++ case e1000_i211:
++ mdicnfg = rd32(E1000_MDICNFG);
++ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK);
++ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT);
++ wr32(E1000_MDICNFG, mdicnfg);
++ break;
++ default:
++ break;
++ }
+ return ret_val;
+ }
+
+@@ -486,7 +537,7 @@
+ goto out;
+
+ if (offset > MAX_PHY_MULTI_PAGE_REG) {
+- ret_val = igb_write_phy_reg_mdic(hw,
++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
+ IGP01E1000_PHY_PAGE_SELECT,
+ (u16)offset);
+ if (ret_val) {
+@@ -495,8 +546,8 @@
+ }
+ }
+
+- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+- data);
++ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr,
++ MAX_PHY_REG_ADDRESS & offset, data);
+
+ hw->phy.ops.release(hw);
+
+@@ -525,7 +576,7 @@
+ goto out;
+
+ if (offset > MAX_PHY_MULTI_PAGE_REG) {
+- ret_val = igb_write_phy_reg_mdic(hw,
++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
+ IGP01E1000_PHY_PAGE_SELECT,
+ (u16)offset);
+ if (ret_val) {
+@@ -534,8 +585,8 @@
+ }
+ }
+
+- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
+- data);
++ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr,
++ MAX_PHY_REG_ADDRESS & offset, data);
+
+ hw->phy.ops.release(hw);
+
+@@ -2501,8 +2552,9 @@
+ }
+
+ /**
+- * igb_write_phy_reg_gs40g - Write GS40G PHY register
++ * igb_write_reg_gs40g - Write GS40G PHY register
+ * @hw: pointer to the HW structure
++ * @addr: phy address to write to
+ * @offset: lower half is register offset to write to
+ * upper half is page to use.
+ * @data: data to write at register offset
+@@ -2510,7 +2562,7 @@
+ * Acquires semaphore, if necessary, then writes the data to PHY register
+ * at the offset. Release any acquired semaphores before exiting.
+ **/
+-s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
++s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data)
+ {
+ s32 ret_val;
+ u16 page = offset >> GS40G_PAGE_SHIFT;
+@@ -2520,10 +2572,10 @@
+ if (ret_val)
+ return ret_val;
+
+- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
++ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
+ if (ret_val)
+ goto release;
+- ret_val = igb_write_phy_reg_mdic(hw, offset, data);
++ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data);
+
+ release:
+ hw->phy.ops.release(hw);
+@@ -2531,8 +2583,24 @@
+ }
+
+ /**
+- * igb_read_phy_reg_gs40g - Read GS40G PHY register
++ * igb_write_phy_reg_gs40g - Write GS40G PHY register
++ * @hw: pointer to the HW structure
++ * @offset: lower half is register offset to write to
++ * upper half is page to use.
++ * @data: data to write at register offset
++ *
++ * Acquires semaphore, if necessary, then writes the data to PHY register
++ * at the offset. Release any acquired semaphores before exiting.
++ **/
++s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
++{
++ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data);
++}
++
++/**
++ * igb_read_reg_gs40g - Read GS40G PHY register
+ * @hw: pointer to the HW structure
++ * @addr: phy address to read from
+ * @offset: lower half is register offset to read to
+ * upper half is page to use.
+ * @data: data to read at register offset
+@@ -2540,7 +2608,7 @@
+ * Acquires semaphore, if necessary, then reads the data in the PHY register
+ * at the offset. Release any acquired semaphores before exiting.
+ **/
+-s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
++s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data)
+ {
+ s32 ret_val;
+ u16 page = offset >> GS40G_PAGE_SHIFT;
+@@ -2550,10 +2618,10 @@
+ if (ret_val)
+ return ret_val;
+
+- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
++ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page);
+ if (ret_val)
+ goto release;
+- ret_val = igb_read_phy_reg_mdic(hw, offset, data);
++ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data);
+
+ release:
+ hw->phy.ops.release(hw);
+@@ -2561,6 +2629,21 @@
+ }
+
+ /**
++ * igb_read_phy_reg_gs40g - Read GS40G PHY register
++ * @hw: pointer to the HW structure
++ * @offset: lower half is register offset to read to
++ * upper half is page to use.
++ * @data: data to read at register offset
++ *
++ * Acquires semaphore, if necessary, then reads the data in the PHY register
++ * at the offset. Release any acquired semaphores before exiting.
++ **/
++s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
++{
++ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data);
++}
++
++/**
+ * igb_set_master_slave_mode - Setup PHY for Master/slave mode
+ * @hw: pointer to the HW structure
+ *
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_phy.h linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_phy.h
+--- linux-3.14.72.orig/drivers/net/ethernet/intel/igb/e1000_phy.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/intel/igb/e1000_phy.h 2016-06-19 22:11:55.269142369 +0200
+@@ -65,8 +65,8 @@
+ void igb_power_up_phy_copper(struct e1000_hw *hw);
+ void igb_power_down_phy_copper(struct e1000_hw *hw);
+ s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
+-s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
+-s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
++s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
++s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
+ s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
+ s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
+ s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
+@@ -77,6 +77,8 @@
+ s32 igb_get_cable_length_82580(struct e1000_hw *hw);
+ s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
+ s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
++s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data);
++s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data);
+ s32 igb_check_polarity_m88(struct e1000_hw *hw);
+
+ /* IGP01E1000 Specific Registers */
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/intel/igb/igb_main.c linux-3.14.72/drivers/net/ethernet/intel/igb/igb_main.c
+--- linux-3.14.72.orig/drivers/net/ethernet/intel/igb/igb_main.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/intel/igb/igb_main.c 2016-06-19 22:11:55.269142369 +0200
+@@ -45,6 +45,7 @@
+ #include <linux/if_vlan.h>
+ #include <linux/pci.h>
+ #include <linux/pci-aspm.h>
++#include <linux/phy.h>
+ #include <linux/delay.h>
+ #include <linux/interrupt.h>
+ #include <linux/ip.h>
+@@ -2185,6 +2186,148 @@
+ return status;
+ }
+
++#ifdef CONFIG_PHYLIB
++/*
++ * MMIO/PHYdev support
++ */
++
++static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
++{
++ struct e1000_hw *hw = bus->priv;
++ u16 out;
++ int err;
++
++ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out);
++ if (err)
++ return err;
++ return out;
++}
++
++static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
++ u16 val)
++{
++ struct e1000_hw *hw = bus->priv;
++
++ return igb_write_reg_gs40g(hw, mii_id, regnum, val);
++}
++
++static int igb_enet_mdio_reset(struct mii_bus *bus)
++{
++ udelay(300);
++ return 0;
++}
++
++static void igb_enet_mii_link(struct net_device *netdev)
++{
++}
++
++/* Probe the mdio bus for phys and connect them */
++static int igb_enet_mii_probe(struct net_device *netdev)
++{
++ struct igb_adapter *adapter = netdev_priv(netdev);
++ struct e1000_hw *hw = &adapter->hw;
++ struct phy_device *phy_dev = NULL;
++ int phy_id;
++
++ /* check for attached phy */
++ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
++ if (hw->mii_bus->phy_map[phy_id]) {
++ phy_dev = hw->mii_bus->phy_map[phy_id];
++ break;
++ }
++ }
++ if (!phy_dev) {
++ netdev_err(netdev, "no PHY found\n");
++ return -ENODEV;
++ }
++
++ hw->phy_interface = PHY_INTERFACE_MODE_RGMII;
++ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev),
++ igb_enet_mii_link, hw->phy_interface);
++ if (IS_ERR(phy_dev)) {
++ netdev_err(netdev, "could not attach to PHY\n");
++ return PTR_ERR(phy_dev);
++ }
++
++ hw->phy_dev = phy_dev;
++ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n",
++ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev));
++
++ return 0;
++}
++
++/* Create and register mdio bus */
++static int igb_enet_mii_init(struct pci_dev *pdev)
++{
++ struct mii_bus *mii_bus;
++ struct net_device *netdev = pci_get_drvdata(pdev);
++ struct igb_adapter *adapter = netdev_priv(netdev);
++ struct e1000_hw *hw = &adapter->hw;
++ int err;
++
++ mii_bus = mdiobus_alloc();
++ if (mii_bus == NULL) {
++ err = -ENOMEM;
++ goto err_out;
++ }
++
++ mii_bus->name = "igb_enet_mii_bus";
++ mii_bus->read = igb_enet_mdio_read;
++ mii_bus->write = igb_enet_mdio_write;
++ mii_bus->reset = igb_enet_mdio_reset;
++ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
++ pci_name(pdev), hw->device_id + 1);
++ mii_bus->priv = hw;
++ mii_bus->parent = &pdev->dev;
++ mii_bus->phy_mask = ~(1 << hw->phy.addr);
++
++ err = mdiobus_register(mii_bus);
++ if (err) {
++ printk(KERN_ERR "failed to register mii_bus: %d\n", err);
++ goto err_out_free_mdiobus;
++ }
++ hw->mii_bus = mii_bus;
++
++ return 0;
++
++err_out_free_mdiobus:
++ mdiobus_free(mii_bus);
++err_out:
++ return err;
++}
++
++static void igb_enet_mii_remove(struct e1000_hw *hw)
++{
++ if (hw->mii_bus) {
++ mdiobus_unregister(hw->mii_bus);
++ mdiobus_free(hw->mii_bus);
++ }
++}
++#endif /* CONFIG_PHYLIB */
++
++/**
++ * igb_read_mac_addr_dts - Read mac addres from the device tree
++ * blob
++ * @adapter: pointer to adapter structure
++ **/
++static void igb_read_mac_addr_dts(struct e1000_hw *hw)
++{
++ struct device_node *dn;
++ const uint8_t *mac;
++
++ dn = of_find_compatible_node(NULL, NULL, "intel,i211");
++
++ if (!dn)
++ return;
++
++ mac = of_get_property(dn, "local-mac-address", NULL);
++
++ if (mac)
++ memcpy(hw->mac.addr, mac, ETH_ALEN);
++
++ return;
++}
++
+ /**
+ * igb_probe - Device Initialization Routine
+ * @pdev: PCI device information struct
+@@ -2387,6 +2530,14 @@
+ if (hw->mac.ops.read_mac_addr(hw))
+ dev_err(&pdev->dev, "NVM Read Error\n");
+
++ if (!is_valid_ether_addr(hw->mac.addr))
++ igb_read_mac_addr_dts(hw);
++
++ if (!is_valid_ether_addr(hw->mac.addr)) {
++ dev_info(&pdev->dev, "Random MAC Address\n");
++ random_ether_addr(hw->mac.addr);
++ }
++
+ memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
+
+ if (!is_valid_ether_addr(netdev->dev_addr)) {
+@@ -2587,6 +2738,13 @@
+ }
+
+ pm_runtime_put_noidle(&pdev->dev);
++
++#ifdef CONFIG_PHYLIB
++ /* create and register the mdio bus if using ext phy */
++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
++ igb_enet_mii_init(pdev);
++#endif
++
+ return 0;
+
+ err_register:
+@@ -2730,6 +2888,10 @@
+ struct e1000_hw *hw = &adapter->hw;
+
+ pm_runtime_get_noresume(&pdev->dev);
++#ifdef CONFIG_PHYLIB
++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
++ igb_enet_mii_remove(hw);
++#endif
+ #ifdef CONFIG_IGB_HWMON
+ igb_sysfs_exit(adapter);
+ #endif
+@@ -3034,6 +3196,12 @@
+ if (!resuming)
+ pm_runtime_put(&pdev->dev);
+
++#ifdef CONFIG_PHYLIB
++ /* Probe and connect to PHY if using ext phy */
++ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)
++ igb_enet_mii_probe(netdev);
++#endif
++
+ /* start the watchdog. */
+ hw->mac.get_link_status = 1;
+ schedule_work(&adapter->watchdog_task);
+@@ -7089,21 +7257,41 @@
+ static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+ {
+ struct igb_adapter *adapter = netdev_priv(netdev);
++ struct e1000_hw *hw = &adapter->hw;
+ struct mii_ioctl_data *data = if_mii(ifr);
+
+- if (adapter->hw.phy.media_type != e1000_media_type_copper)
++ if (adapter->hw.phy.media_type != e1000_media_type_copper &&
++ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO))
+ return -EOPNOTSUPP;
+
+ switch (cmd) {
+ case SIOCGMIIPHY:
+- data->phy_id = adapter->hw.phy.addr;
++ data->phy_id = hw->phy.addr;
+ break;
+ case SIOCGMIIREG:
+- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
+- &data->val_out))
+- return -EIO;
++ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
++ if (igb_read_reg_gs40g(hw, data->phy_id,
++ data->reg_num & 0x1F,
++ &data->val_out))
++ return -EIO;
++ } else {
++ if (igb_read_phy_reg(hw, data->reg_num & 0x1F,
++ &data->val_out))
++ return -EIO;
++ }
+ break;
+ case SIOCSMIIREG:
++ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
++ if (igb_write_reg_gs40g(hw, data->phy_id,
++ data->reg_num & 0x1F,
++ data->val_in))
++ return -EIO;
++ } else {
++ if (igb_write_phy_reg(hw, data->reg_num & 0x1F,
++ data->val_in))
++ return -EIO;
++ }
++ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/mellanox/mlx4/en_clock.c linux-3.14.72/drivers/net/ethernet/mellanox/mlx4/en_clock.c
+--- linux-3.14.72.orig/drivers/net/ethernet/mellanox/mlx4/en_clock.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/mellanox/mlx4/en_clock.c 2016-06-19 22:11:55.269142369 +0200
+@@ -276,6 +276,7 @@
+ .n_alarm = 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = mlx4_en_phc_adjfreq,
+ .adjtime = mlx4_en_phc_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/sfc/ptp.c linux-3.14.72/drivers/net/ethernet/sfc/ptp.c
+--- linux-3.14.72.orig/drivers/net/ethernet/sfc/ptp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/sfc/ptp.c 2016-06-19 22:11:55.269142369 +0200
+@@ -1208,6 +1208,7 @@
+ .n_alarm = 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
++ .n_pins = 0,
+ .pps = 1,
+ .adjfreq = efx_phc_adjfreq,
+ .adjtime = efx_phc_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c linux-3.14.72/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c
+--- linux-3.14.72.orig/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c 2016-06-19 22:11:55.269142369 +0200
+@@ -164,6 +164,7 @@
+ .n_alarm = 0,
+ .n_ext_ts = 0,
+ .n_per_out = 0,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = stmmac_adjust_freq,
+ .adjtime = stmmac_adjust_time,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/ti/cpts.c linux-3.14.72/drivers/net/ethernet/ti/cpts.c
+--- linux-3.14.72.orig/drivers/net/ethernet/ti/cpts.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/ti/cpts.c 2016-06-19 22:11:55.269142369 +0200
+@@ -217,6 +217,7 @@
+ .name = "CTPS timer",
+ .max_adj = 1000000,
+ .n_ext_ts = 0,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = cpts_ptp_adjfreq,
+ .adjtime = cpts_ptp_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/ethernet/tile/tilegx.c linux-3.14.72/drivers/net/ethernet/tile/tilegx.c
+--- linux-3.14.72.orig/drivers/net/ethernet/tile/tilegx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/ethernet/tile/tilegx.c 2016-06-19 22:11:55.269142369 +0200
+@@ -870,6 +870,7 @@
+ .name = "mPIPE clock",
+ .max_adj = 999999999,
+ .n_ext_ts = 0,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = ptp_mpipe_adjfreq,
+ .adjtime = ptp_mpipe_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/net/phy/at803x.c linux-3.14.72/drivers/net/phy/at803x.c
+--- linux-3.14.72.orig/drivers/net/phy/at803x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/phy/at803x.c 2016-06-19 22:11:55.269142369 +0200
+@@ -27,6 +27,9 @@
+ #define AT803X_MMD_ACCESS_CONTROL 0x0D
+ #define AT803X_MMD_ACCESS_CONTROL_DATA 0x0E
+ #define AT803X_FUNC_DATA 0x4003
++#define AT803X_INER 0x0012
++#define AT803X_INER_INIT 0xec00
++#define AT803X_INSR 0x0013
+ #define AT803X_DEBUG_ADDR 0x1D
+ #define AT803X_DEBUG_DATA 0x1E
+ #define AT803X_DEBUG_SYSTEM_MODE_CTRL 0x05
+@@ -191,6 +194,31 @@
+ return 0;
+ }
+
++static int at803x_ack_interrupt(struct phy_device *phydev)
++{
++ int err;
++
++ err = phy_read(phydev, AT803X_INSR);
++
++ return (err < 0) ? err : 0;
++}
++
++static int at803x_config_intr(struct phy_device *phydev)
++{
++ int err;
++ int value;
++
++ value = phy_read(phydev, AT803X_INER);
++
++ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
++ err = phy_write(phydev, AT803X_INER,
++ value | AT803X_INER_INIT);
++ else
++ err = phy_write(phydev, AT803X_INER, 0);
++
++ return err;
++}
++
+ static struct phy_driver at803x_driver[] = {
+ {
+ /* ATHEROS 8035 */
+@@ -240,6 +268,8 @@
+ .flags = PHY_HAS_INTERRUPT,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
++ .ack_interrupt = &at803x_ack_interrupt,
++ .config_intr = &at803x_config_intr,
+ .driver = {
+ .owner = THIS_MODULE,
+ },
+diff -Nur linux-3.14.72.orig/drivers/net/phy/fixed.c linux-3.14.72/drivers/net/phy/fixed.c
+--- linux-3.14.72.orig/drivers/net/phy/fixed.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/phy/fixed.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,264 +0,0 @@
+-/*
+- * Fixed MDIO bus (MDIO bus emulation with fixed PHYs)
+- *
+- * Author: Vitaly Bordug <vbordug@ru.mvista.com>
+- * Anton Vorontsov <avorontsov@ru.mvista.com>
+- *
+- * Copyright (c) 2006-2007 MontaVista Software, Inc.
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/platform_device.h>
+-#include <linux/list.h>
+-#include <linux/mii.h>
+-#include <linux/phy.h>
+-#include <linux/phy_fixed.h>
+-#include <linux/err.h>
+-#include <linux/slab.h>
+-
+-#define MII_REGS_NUM 29
+-
+-struct fixed_mdio_bus {
+- int irqs[PHY_MAX_ADDR];
+- struct mii_bus *mii_bus;
+- struct list_head phys;
+-};
+-
+-struct fixed_phy {
+- int id;
+- u16 regs[MII_REGS_NUM];
+- struct phy_device *phydev;
+- struct fixed_phy_status status;
+- int (*link_update)(struct net_device *, struct fixed_phy_status *);
+- struct list_head node;
+-};
+-
+-static struct platform_device *pdev;
+-static struct fixed_mdio_bus platform_fmb = {
+- .phys = LIST_HEAD_INIT(platform_fmb.phys),
+-};
+-
+-static int fixed_phy_update_regs(struct fixed_phy *fp)
+-{
+- u16 bmsr = BMSR_ANEGCAPABLE;
+- u16 bmcr = 0;
+- u16 lpagb = 0;
+- u16 lpa = 0;
+-
+- if (fp->status.duplex) {
+- bmcr |= BMCR_FULLDPLX;
+-
+- switch (fp->status.speed) {
+- case 1000:
+- bmsr |= BMSR_ESTATEN;
+- bmcr |= BMCR_SPEED1000;
+- lpagb |= LPA_1000FULL;
+- break;
+- case 100:
+- bmsr |= BMSR_100FULL;
+- bmcr |= BMCR_SPEED100;
+- lpa |= LPA_100FULL;
+- break;
+- case 10:
+- bmsr |= BMSR_10FULL;
+- lpa |= LPA_10FULL;
+- break;
+- default:
+- pr_warn("fixed phy: unknown speed\n");
+- return -EINVAL;
+- }
+- } else {
+- switch (fp->status.speed) {
+- case 1000:
+- bmsr |= BMSR_ESTATEN;
+- bmcr |= BMCR_SPEED1000;
+- lpagb |= LPA_1000HALF;
+- break;
+- case 100:
+- bmsr |= BMSR_100HALF;
+- bmcr |= BMCR_SPEED100;
+- lpa |= LPA_100HALF;
+- break;
+- case 10:
+- bmsr |= BMSR_10HALF;
+- lpa |= LPA_10HALF;
+- break;
+- default:
+- pr_warn("fixed phy: unknown speed\n");
+- return -EINVAL;
+- }
+- }
+-
+- if (fp->status.link)
+- bmsr |= BMSR_LSTATUS | BMSR_ANEGCOMPLETE;
+-
+- if (fp->status.pause)
+- lpa |= LPA_PAUSE_CAP;
+-
+- if (fp->status.asym_pause)
+- lpa |= LPA_PAUSE_ASYM;
+-
+- fp->regs[MII_PHYSID1] = fp->id >> 16;
+- fp->regs[MII_PHYSID2] = fp->id;
+-
+- fp->regs[MII_BMSR] = bmsr;
+- fp->regs[MII_BMCR] = bmcr;
+- fp->regs[MII_LPA] = lpa;
+- fp->regs[MII_STAT1000] = lpagb;
+-
+- return 0;
+-}
+-
+-static int fixed_mdio_read(struct mii_bus *bus, int phy_id, int reg_num)
+-{
+- struct fixed_mdio_bus *fmb = bus->priv;
+- struct fixed_phy *fp;
+-
+- if (reg_num >= MII_REGS_NUM)
+- return -1;
+-
+- list_for_each_entry(fp, &fmb->phys, node) {
+- if (fp->id == phy_id) {
+- /* Issue callback if user registered it. */
+- if (fp->link_update) {
+- fp->link_update(fp->phydev->attached_dev,
+- &fp->status);
+- fixed_phy_update_regs(fp);
+- }
+- return fp->regs[reg_num];
+- }
+- }
+-
+- return 0xFFFF;
+-}
+-
+-static int fixed_mdio_write(struct mii_bus *bus, int phy_id, int reg_num,
+- u16 val)
+-{
+- return 0;
+-}
+-
+-/*
+- * If something weird is required to be done with link/speed,
+- * network driver is able to assign a function to implement this.
+- * May be useful for PHY's that need to be software-driven.
+- */
+-int fixed_phy_set_link_update(struct phy_device *phydev,
+- int (*link_update)(struct net_device *,
+- struct fixed_phy_status *))
+-{
+- struct fixed_mdio_bus *fmb = &platform_fmb;
+- struct fixed_phy *fp;
+-
+- if (!link_update || !phydev || !phydev->bus)
+- return -EINVAL;
+-
+- list_for_each_entry(fp, &fmb->phys, node) {
+- if (fp->id == phydev->phy_id) {
+- fp->link_update = link_update;
+- fp->phydev = phydev;
+- return 0;
+- }
+- }
+-
+- return -ENOENT;
+-}
+-EXPORT_SYMBOL_GPL(fixed_phy_set_link_update);
+-
+-int fixed_phy_add(unsigned int irq, int phy_id,
+- struct fixed_phy_status *status)
+-{
+- int ret;
+- struct fixed_mdio_bus *fmb = &platform_fmb;
+- struct fixed_phy *fp;
+-
+- fp = kzalloc(sizeof(*fp), GFP_KERNEL);
+- if (!fp)
+- return -ENOMEM;
+-
+- memset(fp->regs, 0xFF, sizeof(fp->regs[0]) * MII_REGS_NUM);
+-
+- fmb->irqs[phy_id] = irq;
+-
+- fp->id = phy_id;
+- fp->status = *status;
+-
+- ret = fixed_phy_update_regs(fp);
+- if (ret)
+- goto err_regs;
+-
+- list_add_tail(&fp->node, &fmb->phys);
+-
+- return 0;
+-
+-err_regs:
+- kfree(fp);
+- return ret;
+-}
+-EXPORT_SYMBOL_GPL(fixed_phy_add);
+-
+-static int __init fixed_mdio_bus_init(void)
+-{
+- struct fixed_mdio_bus *fmb = &platform_fmb;
+- int ret;
+-
+- pdev = platform_device_register_simple("Fixed MDIO bus", 0, NULL, 0);
+- if (IS_ERR(pdev)) {
+- ret = PTR_ERR(pdev);
+- goto err_pdev;
+- }
+-
+- fmb->mii_bus = mdiobus_alloc();
+- if (fmb->mii_bus == NULL) {
+- ret = -ENOMEM;
+- goto err_mdiobus_reg;
+- }
+-
+- snprintf(fmb->mii_bus->id, MII_BUS_ID_SIZE, "fixed-0");
+- fmb->mii_bus->name = "Fixed MDIO Bus";
+- fmb->mii_bus->priv = fmb;
+- fmb->mii_bus->parent = &pdev->dev;
+- fmb->mii_bus->read = &fixed_mdio_read;
+- fmb->mii_bus->write = &fixed_mdio_write;
+- fmb->mii_bus->irq = fmb->irqs;
+-
+- ret = mdiobus_register(fmb->mii_bus);
+- if (ret)
+- goto err_mdiobus_alloc;
+-
+- return 0;
+-
+-err_mdiobus_alloc:
+- mdiobus_free(fmb->mii_bus);
+-err_mdiobus_reg:
+- platform_device_unregister(pdev);
+-err_pdev:
+- return ret;
+-}
+-module_init(fixed_mdio_bus_init);
+-
+-static void __exit fixed_mdio_bus_exit(void)
+-{
+- struct fixed_mdio_bus *fmb = &platform_fmb;
+- struct fixed_phy *fp, *tmp;
+-
+- mdiobus_unregister(fmb->mii_bus);
+- mdiobus_free(fmb->mii_bus);
+- platform_device_unregister(pdev);
+-
+- list_for_each_entry_safe(fp, tmp, &fmb->phys, node) {
+- list_del(&fp->node);
+- kfree(fp);
+- }
+-}
+-module_exit(fixed_mdio_bus_exit);
+-
+-MODULE_DESCRIPTION("Fixed MDIO bus (MDIO bus emulation with fixed PHYs)");
+-MODULE_AUTHOR("Vitaly Bordug");
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/net/phy/fixed_phy.c linux-3.14.72/drivers/net/phy/fixed_phy.c
+--- linux-3.14.72.orig/drivers/net/phy/fixed_phy.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/phy/fixed_phy.c 2016-06-19 22:11:55.273142107 +0200
+@@ -0,0 +1,325 @@
++/*
++ * Fixed MDIO bus (MDIO bus emulation with fixed PHYs)
++ *
++ * Author: Vitaly Bordug <vbordug@ru.mvista.com>
++ * Anton Vorontsov <avorontsov@ru.mvista.com>
++ *
++ * Copyright (c) 2006-2007 MontaVista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/list.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/phy_fixed.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++
++#define MII_REGS_NUM 29
++
++struct fixed_mdio_bus {
++ int irqs[PHY_MAX_ADDR];
++ struct mii_bus *mii_bus;
++ struct list_head phys;
++};
++
++struct fixed_phy {
++ int addr;
++ u16 regs[MII_REGS_NUM];
++ struct phy_device *phydev;
++ struct fixed_phy_status status;
++ int (*link_update)(struct net_device *, struct fixed_phy_status *);
++ struct list_head node;
++};
++
++static struct platform_device *pdev;
++static struct fixed_mdio_bus platform_fmb = {
++ .phys = LIST_HEAD_INIT(platform_fmb.phys),
++};
++
++static int fixed_phy_update_regs(struct fixed_phy *fp)
++{
++ u16 bmsr = BMSR_ANEGCAPABLE;
++ u16 bmcr = 0;
++ u16 lpagb = 0;
++ u16 lpa = 0;
++
++ if (fp->status.duplex) {
++ bmcr |= BMCR_FULLDPLX;
++
++ switch (fp->status.speed) {
++ case 1000:
++ bmsr |= BMSR_ESTATEN;
++ bmcr |= BMCR_SPEED1000;
++ lpagb |= LPA_1000FULL;
++ break;
++ case 100:
++ bmsr |= BMSR_100FULL;
++ bmcr |= BMCR_SPEED100;
++ lpa |= LPA_100FULL;
++ break;
++ case 10:
++ bmsr |= BMSR_10FULL;
++ lpa |= LPA_10FULL;
++ break;
++ default:
++ pr_warn("fixed phy: unknown speed\n");
++ return -EINVAL;
++ }
++ } else {
++ switch (fp->status.speed) {
++ case 1000:
++ bmsr |= BMSR_ESTATEN;
++ bmcr |= BMCR_SPEED1000;
++ lpagb |= LPA_1000HALF;
++ break;
++ case 100:
++ bmsr |= BMSR_100HALF;
++ bmcr |= BMCR_SPEED100;
++ lpa |= LPA_100HALF;
++ break;
++ case 10:
++ bmsr |= BMSR_10HALF;
++ lpa |= LPA_10HALF;
++ break;
++ default:
++ pr_warn("fixed phy: unknown speed\n");
++ return -EINVAL;
++ }
++ }
++
++ if (fp->status.link)
++ bmsr |= BMSR_LSTATUS | BMSR_ANEGCOMPLETE;
++
++ if (fp->status.pause)
++ lpa |= LPA_PAUSE_CAP;
++
++ if (fp->status.asym_pause)
++ lpa |= LPA_PAUSE_ASYM;
++
++ fp->regs[MII_PHYSID1] = 0;
++ fp->regs[MII_PHYSID2] = 0;
++
++ fp->regs[MII_BMSR] = bmsr;
++ fp->regs[MII_BMCR] = bmcr;
++ fp->regs[MII_LPA] = lpa;
++ fp->regs[MII_STAT1000] = lpagb;
++
++ return 0;
++}
++
++static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
++{
++ struct fixed_mdio_bus *fmb = bus->priv;
++ struct fixed_phy *fp;
++
++ if (reg_num >= MII_REGS_NUM)
++ return -1;
++
++ list_for_each_entry(fp, &fmb->phys, node) {
++ if (fp->addr == phy_addr) {
++ /* Issue callback if user registered it. */
++ if (fp->link_update) {
++ fp->link_update(fp->phydev->attached_dev,
++ &fp->status);
++ fixed_phy_update_regs(fp);
++ }
++ return fp->regs[reg_num];
++ }
++ }
++
++ return 0xFFFF;
++}
++
++static int fixed_mdio_write(struct mii_bus *bus, int phy_addr, int reg_num,
++ u16 val)
++{
++ return 0;
++}
++
++/*
++ * If something weird is required to be done with link/speed,
++ * network driver is able to assign a function to implement this.
++ * May be useful for PHY's that need to be software-driven.
++ */
++int fixed_phy_set_link_update(struct phy_device *phydev,
++ int (*link_update)(struct net_device *,
++ struct fixed_phy_status *))
++{
++ struct fixed_mdio_bus *fmb = &platform_fmb;
++ struct fixed_phy *fp;
++
++ if (!phydev || !phydev->bus)
++ return -EINVAL;
++
++ list_for_each_entry(fp, &fmb->phys, node) {
++ if (fp->addr == phydev->addr) {
++ fp->link_update = link_update;
++ fp->phydev = phydev;
++ return 0;
++ }
++ }
++
++ return -ENOENT;
++}
++EXPORT_SYMBOL_GPL(fixed_phy_set_link_update);
++
++int fixed_phy_add(unsigned int irq, int phy_addr,
++ struct fixed_phy_status *status)
++{
++ int ret;
++ struct fixed_mdio_bus *fmb = &platform_fmb;
++ struct fixed_phy *fp;
++
++ fp = kzalloc(sizeof(*fp), GFP_KERNEL);
++ if (!fp)
++ return -ENOMEM;
++
++ memset(fp->regs, 0xFF, sizeof(fp->regs[0]) * MII_REGS_NUM);
++
++ fmb->irqs[phy_addr] = irq;
++
++ fp->addr = phy_addr;
++ fp->status = *status;
++
++ ret = fixed_phy_update_regs(fp);
++ if (ret)
++ goto err_regs;
++
++ list_add_tail(&fp->node, &fmb->phys);
++
++ return 0;
++
++err_regs:
++ kfree(fp);
++ return ret;
++}
++EXPORT_SYMBOL_GPL(fixed_phy_add);
++
++void fixed_phy_del(int phy_addr)
++{
++ struct fixed_mdio_bus *fmb = &platform_fmb;
++ struct fixed_phy *fp, *tmp;
++
++ list_for_each_entry_safe(fp, tmp, &fmb->phys, node) {
++ if (fp->addr == phy_addr) {
++ list_del(&fp->node);
++ kfree(fp);
++ return;
++ }
++ }
++}
++EXPORT_SYMBOL_GPL(fixed_phy_del);
++
++static int phy_fixed_addr;
++static DEFINE_SPINLOCK(phy_fixed_addr_lock);
++
++int fixed_phy_register(unsigned int irq,
++ struct fixed_phy_status *status,
++ struct device_node *np)
++{
++ struct fixed_mdio_bus *fmb = &platform_fmb;
++ struct phy_device *phy;
++ int phy_addr;
++ int ret;
++
++ /* Get the next available PHY address, up to PHY_MAX_ADDR */
++ spin_lock(&phy_fixed_addr_lock);
++ if (phy_fixed_addr == PHY_MAX_ADDR) {
++ spin_unlock(&phy_fixed_addr_lock);
++ return -ENOSPC;
++ }
++ phy_addr = phy_fixed_addr++;
++ spin_unlock(&phy_fixed_addr_lock);
++
++ ret = fixed_phy_add(PHY_POLL, phy_addr, status);
++ if (ret < 0)
++ return ret;
++
++ phy = get_phy_device(fmb->mii_bus, phy_addr, false);
++ if (!phy || IS_ERR(phy)) {
++ fixed_phy_del(phy_addr);
++ return -EINVAL;
++ }
++
++ of_node_get(np);
++ phy->dev.of_node = np;
++
++ ret = phy_device_register(phy);
++ if (ret) {
++ phy_device_free(phy);
++ of_node_put(np);
++ fixed_phy_del(phy_addr);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int __init fixed_mdio_bus_init(void)
++{
++ struct fixed_mdio_bus *fmb = &platform_fmb;
++ int ret;
++
++ pdev = platform_device_register_simple("Fixed MDIO bus", 0, NULL, 0);
++ if (IS_ERR(pdev)) {
++ ret = PTR_ERR(pdev);
++ goto err_pdev;
++ }
++
++ fmb->mii_bus = mdiobus_alloc();
++ if (fmb->mii_bus == NULL) {
++ ret = -ENOMEM;
++ goto err_mdiobus_reg;
++ }
++
++ snprintf(fmb->mii_bus->id, MII_BUS_ID_SIZE, "fixed-0");
++ fmb->mii_bus->name = "Fixed MDIO Bus";
++ fmb->mii_bus->priv = fmb;
++ fmb->mii_bus->parent = &pdev->dev;
++ fmb->mii_bus->read = &fixed_mdio_read;
++ fmb->mii_bus->write = &fixed_mdio_write;
++ fmb->mii_bus->irq = fmb->irqs;
++
++ ret = mdiobus_register(fmb->mii_bus);
++ if (ret)
++ goto err_mdiobus_alloc;
++
++ return 0;
++
++err_mdiobus_alloc:
++ mdiobus_free(fmb->mii_bus);
++err_mdiobus_reg:
++ platform_device_unregister(pdev);
++err_pdev:
++ return ret;
++}
++module_init(fixed_mdio_bus_init);
++
++static void __exit fixed_mdio_bus_exit(void)
++{
++ struct fixed_mdio_bus *fmb = &platform_fmb;
++ struct fixed_phy *fp, *tmp;
++
++ mdiobus_unregister(fmb->mii_bus);
++ mdiobus_free(fmb->mii_bus);
++ platform_device_unregister(pdev);
++
++ list_for_each_entry_safe(fp, tmp, &fmb->phys, node) {
++ list_del(&fp->node);
++ kfree(fp);
++ }
++}
++module_exit(fixed_mdio_bus_exit);
++
++MODULE_DESCRIPTION("Fixed MDIO bus (MDIO bus emulation with fixed PHYs)");
++MODULE_AUTHOR("Vitaly Bordug");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/net/phy/Kconfig linux-3.14.72/drivers/net/phy/Kconfig
+--- linux-3.14.72.orig/drivers/net/phy/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/phy/Kconfig 2016-06-19 22:11:55.273142107 +0200
+@@ -107,8 +107,8 @@
+ Supports the KSZ9021, VSC8201, KS8001 PHYs.
+
+ config FIXED_PHY
+- bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
+- depends on PHYLIB=y
++ tristate "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
++ depends on PHYLIB
+ ---help---
+ Adds the platform "fixed" MDIO Bus to cover the boards that use
+ PHYs that are not connected to the real MDIO bus.
+diff -Nur linux-3.14.72.orig/drivers/net/phy/Makefile linux-3.14.72/drivers/net/phy/Makefile
+--- linux-3.14.72.orig/drivers/net/phy/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/phy/Makefile 2016-06-19 22:11:55.273142107 +0200
+@@ -16,7 +16,7 @@
+ obj-$(CONFIG_ICPLUS_PHY) += icplus.o
+ obj-$(CONFIG_REALTEK_PHY) += realtek.o
+ obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o
+-obj-$(CONFIG_FIXED_PHY) += fixed.o
++obj-$(CONFIG_FIXED_PHY) += fixed_phy.o
+ obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
+ obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
+ obj-$(CONFIG_NATIONAL_PHY) += national.o
+diff -Nur linux-3.14.72.orig/drivers/net/phy/mdio_bus.c linux-3.14.72/drivers/net/phy/mdio_bus.c
+--- linux-3.14.72.orig/drivers/net/phy/mdio_bus.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/phy/mdio_bus.c 2016-06-19 22:11:55.273142107 +0200
+@@ -120,6 +120,50 @@
+ return d ? to_mii_bus(d) : NULL;
+ }
+ EXPORT_SYMBOL(of_mdio_find_bus);
++
++/* Walk the list of subnodes of a mdio bus and look for a node that matches the
++ * phy's address with its 'reg' property. If found, set the of_node pointer for
++ * the phy. This allows auto-probed pyh devices to be supplied with information
++ * passed in via DT.
++ */
++static void of_mdiobus_link_phydev(struct mii_bus *mdio,
++ struct phy_device *phydev)
++{
++ struct device *dev = &phydev->dev;
++ struct device_node *child;
++
++ if (dev->of_node || !mdio->dev.of_node)
++ return;
++
++ for_each_available_child_of_node(mdio->dev.of_node, child) {
++ int addr;
++ int ret;
++
++ ret = of_property_read_u32(child, "reg", &addr);
++ if (ret < 0) {
++ dev_err(dev, "%s has invalid PHY address\n",
++ child->full_name);
++ continue;
++ }
++
++ /* A PHY must have a reg property in the range [0-31] */
++ if (addr >= PHY_MAX_ADDR) {
++ dev_err(dev, "%s PHY address %i is too large\n",
++ child->full_name, addr);
++ continue;
++ }
++
++ if (addr == phydev->addr) {
++ dev->of_node = child;
++ return;
++ }
++ }
++}
++#else /* !IS_ENABLED(CONFIG_OF_MDIO) */
++static inline void of_mdiobus_link_phydev(struct mii_bus *mdio,
++ struct phy_device *phydev)
++{
++}
+ #endif
+
+ /**
+@@ -233,6 +277,12 @@
+ if (IS_ERR(phydev) || phydev == NULL)
+ return phydev;
+
++ /*
++ * For DT, see if the auto-probed phy has a correspoding child
++ * in the bus node, and set the of_node pointer in this case.
++ */
++ of_mdiobus_link_phydev(bus, phydev);
++
+ err = phy_device_register(phydev);
+ if (err) {
+ phy_device_free(phydev);
+diff -Nur linux-3.14.72.orig/drivers/net/phy/phy.c linux-3.14.72/drivers/net/phy/phy.c
+--- linux-3.14.72.orig/drivers/net/phy/phy.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/phy/phy.c 2016-06-19 22:11:55.273142107 +0200
+@@ -766,6 +766,8 @@
+ phydev->state = PHY_RUNNING;
+ netif_carrier_on(phydev->attached_dev);
+ phydev->adjust_link(phydev->attached_dev);
++ } else {
++ netif_carrier_off(phydev->attached_dev);
+ }
+ break;
+ case PHY_FORCING:
+diff -Nur linux-3.14.72.orig/drivers/net/phy/phy_device.c linux-3.14.72/drivers/net/phy/phy_device.c
+--- linux-3.14.72.orig/drivers/net/phy/phy_device.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/phy/phy_device.c 2016-06-19 22:11:55.273142107 +0200
+@@ -33,6 +33,7 @@
+ #include <linux/mdio.h>
+ #include <linux/io.h>
+ #include <linux/uaccess.h>
++#include <linux/of.h>
+
+ #include <asm/irq.h>
+
+@@ -1125,6 +1126,38 @@
+ return 0;
+ }
+
++static void of_set_phy_supported(struct phy_device *phydev)
++{
++ struct device_node *node = phydev->dev.of_node;
++ u32 max_speed;
++
++ if (!IS_ENABLED(CONFIG_OF_MDIO))
++ return;
++
++ if (!node)
++ return;
++
++ if (!of_property_read_u32(node, "max-speed", &max_speed)) {
++ /* The default values for phydev->supported are provided by the PHY
++ * driver "features" member, we want to reset to sane defaults fist
++ * before supporting higher speeds.
++ */
++ phydev->supported &= PHY_DEFAULT_FEATURES;
++
++ switch (max_speed) {
++ default:
++ return;
++
++ case SPEED_1000:
++ phydev->supported |= PHY_1000BT_FEATURES;
++ case SPEED_100:
++ phydev->supported |= PHY_100BT_FEATURES;
++ case SPEED_10:
++ phydev->supported |= PHY_10BT_FEATURES;
++ }
++ }
++}
++
+ /**
+ * phy_probe - probe and init a PHY device
+ * @dev: device to probe and init
+@@ -1159,7 +1192,8 @@
+ * or both of these values
+ */
+ phydev->supported = phydrv->features;
+- phydev->advertising = phydrv->features;
++ of_set_phy_supported(phydev);
++ phydev->advertising = phydev->supported;
+
+ /* Set the state to READY by default */
+ phydev->state = PHY_READY;
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/ath/ath6kl/cfg80211.c linux-3.14.72/drivers/net/wireless/ath/ath6kl/cfg80211.c
+--- linux-3.14.72.orig/drivers/net/wireless/ath/ath6kl/cfg80211.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/ath/ath6kl/cfg80211.c 2016-06-19 22:11:55.273142107 +0200
+@@ -790,7 +790,7 @@
+ if (nw_type & ADHOC_NETWORK) {
+ ath6kl_dbg(ATH6KL_DBG_WLAN_CFG, "ad-hoc %s selected\n",
+ nw_type & ADHOC_CREATOR ? "creator" : "joiner");
+- cfg80211_ibss_joined(vif->ndev, bssid, GFP_KERNEL);
++ cfg80211_ibss_joined(vif->ndev, bssid, chan, GFP_KERNEL);
+ cfg80211_put_bss(ar->wiphy, bss);
+ return;
+ }
+@@ -845,6 +845,7 @@
+ up(&ar->sem);
+
+ vif->sme_state = SME_DISCONNECTED;
++ cfg80211_disconnected(vif->ndev, 0, NULL, 0, GFP_KERNEL);
+
+ return 0;
+ }
+@@ -861,13 +862,9 @@
+ }
+
+ if (vif->nw_type & ADHOC_NETWORK) {
+- if (vif->wdev.iftype != NL80211_IFTYPE_ADHOC) {
++ if (vif->wdev.iftype != NL80211_IFTYPE_ADHOC)
+ ath6kl_dbg(ATH6KL_DBG_WLAN_CFG,
+ "%s: ath6k not in ibss mode\n", __func__);
+- return;
+- }
+- memset(bssid, 0, ETH_ALEN);
+- cfg80211_ibss_joined(vif->ndev, bssid, GFP_KERNEL);
+ return;
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bcdc.c 2016-06-19 22:11:55.273142107 +0200
+@@ -25,10 +25,10 @@
+ #include <brcmu_utils.h>
+ #include <brcmu_wifi.h>
+
+-#include "dhd.h"
+-#include "dhd_bus.h"
++#include "core.h"
++#include "bus.h"
+ #include "fwsignal.h"
+-#include "dhd_dbg.h"
++#include "debug.h"
+ #include "tracepoint.h"
+ #include "proto.h"
+ #include "bcdc.h"
+@@ -337,6 +337,23 @@
+ return brcmf_bus_txdata(drvr->bus_if, pktbuf);
+ }
+
++static void
++brcmf_proto_bcdc_configure_addr_mode(struct brcmf_pub *drvr, int ifidx,
++ enum proto_addr_mode addr_mode)
++{
++}
++
++static void
++brcmf_proto_bcdc_delete_peer(struct brcmf_pub *drvr, int ifidx,
++ u8 peer[ETH_ALEN])
++{
++}
++
++static void
++brcmf_proto_bcdc_add_tdls_peer(struct brcmf_pub *drvr, int ifidx,
++ u8 peer[ETH_ALEN])
++{
++}
+
+ int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr)
+ {
+@@ -356,6 +373,9 @@
+ drvr->proto->query_dcmd = brcmf_proto_bcdc_query_dcmd;
+ drvr->proto->set_dcmd = brcmf_proto_bcdc_set_dcmd;
+ drvr->proto->txdata = brcmf_proto_bcdc_txdata;
++ drvr->proto->configure_addr_mode = brcmf_proto_bcdc_configure_addr_mode;
++ drvr->proto->delete_peer = brcmf_proto_bcdc_delete_peer;
++ drvr->proto->add_tdls_peer = brcmf_proto_bcdc_add_tdls_peer;
+ drvr->proto->pd = bcdc;
+
+ drvr->hdrlen += BCDC_HEADER_LEN + BRCMF_PROT_FW_SIGNAL_MAX_TXBYTES;
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bcdc.h 2016-06-19 22:11:55.273142107 +0200
+@@ -16,9 +16,12 @@
+ #ifndef BRCMFMAC_BCDC_H
+ #define BRCMFMAC_BCDC_H
+
+-
++#ifdef CONFIG_BRCMFMAC_PROTO_BCDC
+ int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr);
+ void brcmf_proto_bcdc_detach(struct brcmf_pub *drvr);
+-
++#else
++static inline int brcmf_proto_bcdc_attach(struct brcmf_pub *drvr) { return 0; }
++static inline void brcmf_proto_bcdc_detach(struct brcmf_pub *drvr) {}
++#endif
+
+ #endif /* BRCMFMAC_BCDC_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bcmsdh.c 2016-06-19 22:11:55.273142107 +0200
+@@ -25,11 +25,11 @@
+ #include <linux/mmc/sdio.h>
+ #include <linux/mmc/core.h>
+ #include <linux/mmc/sdio_func.h>
+-#include <linux/mmc/sdio_ids.h>
+ #include <linux/mmc/card.h>
+ #include <linux/mmc/host.h>
+ #include <linux/platform_device.h>
+ #include <linux/platform_data/brcmfmac-sdio.h>
++#include <linux/pm_runtime.h>
+ #include <linux/suspend.h>
+ #include <linux/errno.h>
+ #include <linux/module.h>
+@@ -39,11 +39,13 @@
+ #include <brcm_hw_ids.h>
+ #include <brcmu_utils.h>
+ #include <brcmu_wifi.h>
++#include <chipcommon.h>
+ #include <soc.h>
+-#include "dhd_bus.h"
+-#include "dhd_dbg.h"
+-#include "sdio_host.h"
+-#include "sdio_chip.h"
++#include "chip.h"
++#include "bus.h"
++#include "debug.h"
++#include "sdio.h"
++#include "of.h"
+
+ #define SDIOH_API_ACCESS_RETRY_LIMIT 2
+
+@@ -54,6 +56,20 @@
+ /* Maximum milliseconds to wait for F2 to come up */
+ #define SDIO_WAIT_F2RDY 3000
+
++#define BRCMF_DEFAULT_TXGLOM_SIZE 32 /* max tx frames in glom chain */
++#define BRCMF_DEFAULT_RXGLOM_SIZE 32 /* max rx frames in glom chain */
++
++struct brcmf_sdiod_freezer {
++ atomic_t freezing;
++ atomic_t thread_count;
++ u32 frozen_count;
++ wait_queue_head_t thread_freeze;
++ struct completion resumed;
++};
++
++static int brcmf_sdiod_txglomsz = BRCMF_DEFAULT_TXGLOM_SIZE;
++module_param_named(txglomsz, brcmf_sdiod_txglomsz, int, 0);
++MODULE_PARM_DESC(txglomsz, "maximum tx packet chain size [SDIO]");
+
+ static irqreturn_t brcmf_sdiod_oob_irqhandler(int irq, void *dev_id)
+ {
+@@ -90,29 +106,11 @@
+ {
+ }
+
+-static bool brcmf_sdiod_pm_resume_error(struct brcmf_sdio_dev *sdiodev)
+-{
+- bool is_err = false;
+-#ifdef CONFIG_PM_SLEEP
+- is_err = atomic_read(&sdiodev->suspend);
+-#endif
+- return is_err;
+-}
+-
+-static void brcmf_sdiod_pm_resume_wait(struct brcmf_sdio_dev *sdiodev,
+- wait_queue_head_t *wq)
+-{
+-#ifdef CONFIG_PM_SLEEP
+- int retry = 0;
+- while (atomic_read(&sdiodev->suspend) && retry++ != 30)
+- wait_event_timeout(*wq, false, HZ/100);
+-#endif
+-}
+-
+ int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev)
+ {
+ int ret = 0;
+ u8 data;
++ u32 addr, gpiocontrol;
+ unsigned long flags;
+
+ if ((sdiodev->pdata) && (sdiodev->pdata->oob_irq_supported)) {
+@@ -142,6 +140,19 @@
+
+ sdio_claim_host(sdiodev->func[1]);
+
++ if (sdiodev->bus_if->chip == BRCM_CC_43362_CHIP_ID) {
++ /* assign GPIO to SDIO core */
++ addr = CORE_CC_REG(SI_ENUM_BASE, gpiocontrol);
++ gpiocontrol = brcmf_sdiod_regrl(sdiodev, addr, &ret);
++ gpiocontrol |= 0x2;
++ brcmf_sdiod_regwl(sdiodev, addr, gpiocontrol, &ret);
++
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_GPIO_SELECT, 0xf,
++ &ret);
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_GPIO_OUT, 0, &ret);
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_GPIO_EN, 0x2, &ret);
++ }
++
+ /* must configure SDIO_CCCR_IENx to enable irq */
+ data = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_IENx, &ret);
+ data |= 1 << SDIO_FUNC_1 | 1 << SDIO_FUNC_2 | 1;
+@@ -195,6 +206,30 @@
+ return 0;
+ }
+
++void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev,
++ enum brcmf_sdiod_state state)
++{
++ if (sdiodev->state == BRCMF_SDIOD_NOMEDIUM ||
++ state == sdiodev->state)
++ return;
++
++ brcmf_dbg(TRACE, "%d -> %d\n", sdiodev->state, state);
++ switch (sdiodev->state) {
++ case BRCMF_SDIOD_DATA:
++ /* any other state means bus interface is down */
++ brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_DOWN);
++ break;
++ case BRCMF_SDIOD_DOWN:
++ /* transition from DOWN to DATA means bus interface is up */
++ if (state == BRCMF_SDIOD_DATA)
++ brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_UP);
++ break;
++ default:
++ break;
++ }
++ sdiodev->state = state;
++}
++
+ static inline int brcmf_sdiod_f0_writeb(struct sdio_func *func,
+ uint regaddr, u8 byte)
+ {
+@@ -223,10 +258,6 @@
+ brcmf_dbg(SDIO, "rw=%d, func=%d, addr=0x%05x, nbytes=%d\n",
+ write, fn, addr, regsz);
+
+- brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_word_wait);
+- if (brcmf_sdiod_pm_resume_error(sdiodev))
+- return -EIO;
+-
+ /* only allow byte access on F0 */
+ if (WARN_ON(regsz > 1 && !fn))
+ return -EINVAL;
+@@ -264,30 +295,21 @@
+ break;
+ }
+
+- if (ret) {
+- /*
+- * SleepCSR register access can fail when
+- * waking up the device so reduce this noise
+- * in the logs.
+- */
+- if (addr != SBSDIO_FUNC1_SLEEPCSR)
+- brcmf_err("failed to %s data F%d@0x%05x, err: %d\n",
+- write ? "write" : "read", fn, addr, ret);
+- else
+- brcmf_dbg(SDIO, "failed to %s data F%d@0x%05x, err: %d\n",
+- write ? "write" : "read", fn, addr, ret);
+- }
++ if (ret)
++ brcmf_dbg(SDIO, "failed to %s data F%d@0x%05x, err: %d\n",
++ write ? "write" : "read", fn, addr, ret);
++
+ return ret;
+ }
+
+ static int brcmf_sdiod_regrw_helper(struct brcmf_sdio_dev *sdiodev, u32 addr,
+ u8 regsz, void *data, bool write)
+ {
+- u8 func_num;
++ u8 func;
+ s32 retry = 0;
+ int ret;
+
+- if (sdiodev->bus_if->state == BRCMF_BUS_NOMEDIUM)
++ if (sdiodev->state == BRCMF_SDIOD_NOMEDIUM)
+ return -ENOMEDIUM;
+
+ /*
+@@ -297,9 +319,9 @@
+ * The rest: function 1 silicon backplane core registers
+ */
+ if ((addr & ~REG_F0_REG_MASK) == 0)
+- func_num = SDIO_FUNC_0;
++ func = SDIO_FUNC_0;
+ else
+- func_num = SDIO_FUNC_1;
++ func = SDIO_FUNC_1;
+
+ do {
+ if (!write)
+@@ -307,16 +329,26 @@
+ /* for retry wait for 1 ms till bus get settled down */
+ if (retry)
+ usleep_range(1000, 2000);
+- ret = brcmf_sdiod_request_data(sdiodev, func_num, addr, regsz,
++ ret = brcmf_sdiod_request_data(sdiodev, func, addr, regsz,
+ data, write);
+ } while (ret != 0 && ret != -ENOMEDIUM &&
+ retry++ < SDIOH_API_ACCESS_RETRY_LIMIT);
+
+ if (ret == -ENOMEDIUM)
+- brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_NOMEDIUM);
+- else if (ret != 0)
+- brcmf_err("failed with %d\n", ret);
+-
++ brcmf_sdiod_change_state(sdiodev, BRCMF_SDIOD_NOMEDIUM);
++ else if (ret != 0) {
++ /*
++ * SleepCSR register access can fail when
++ * waking up the device so reduce this noise
++ * in the logs.
++ */
++ if (addr != SBSDIO_FUNC1_SLEEPCSR)
++ brcmf_err("failed to %s data F%d@0x%05x, err: %d\n",
++ write ? "write" : "read", func, addr, ret);
++ else
++ brcmf_dbg(SDIO, "failed to %s data F%d@0x%05x, err: %d\n",
++ write ? "write" : "read", func, addr, ret);
++ }
+ return ret;
+ }
+
+@@ -326,7 +358,7 @@
+ int err = 0, i;
+ u8 addr[3];
+
+- if (sdiodev->bus_if->state == BRCMF_BUS_NOMEDIUM)
++ if (sdiodev->state == BRCMF_SDIOD_NOMEDIUM)
+ return -ENOMEDIUM;
+
+ addr[0] = (address >> 8) & SBSDIO_SBADDRLOW_MASK;
+@@ -440,10 +472,6 @@
+ unsigned int req_sz;
+ int err;
+
+- brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_buffer_wait);
+- if (brcmf_sdiod_pm_resume_error(sdiodev))
+- return -EIO;
+-
+ /* Single skb use the standard mmc interface */
+ req_sz = pkt->len + 3;
+ req_sz &= (uint)~3;
+@@ -459,7 +487,7 @@
+ err = sdio_readsb(sdiodev->func[fn], ((u8 *)(pkt->data)), addr,
+ req_sz);
+ if (err == -ENOMEDIUM)
+- brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_NOMEDIUM);
++ brcmf_sdiod_change_state(sdiodev, BRCMF_SDIOD_NOMEDIUM);
+ return err;
+ }
+
+@@ -488,17 +516,12 @@
+ struct mmc_request mmc_req;
+ struct mmc_command mmc_cmd;
+ struct mmc_data mmc_dat;
+- struct sg_table st;
+ struct scatterlist *sgl;
+ int ret = 0;
+
+ if (!pktlist->qlen)
+ return -EINVAL;
+
+- brcmf_sdiod_pm_resume_wait(sdiodev, &sdiodev->request_buffer_wait);
+- if (brcmf_sdiod_pm_resume_error(sdiodev))
+- return -EIO;
+-
+ target_list = pktlist;
+ /* for host with broken sg support, prepare a page aligned list */
+ __skb_queue_head_init(&local_list);
+@@ -533,16 +556,11 @@
+ pkt_offset = 0;
+ pkt_next = target_list->next;
+
+- if (sg_alloc_table(&st, max_seg_cnt, GFP_KERNEL)) {
+- ret = -ENOMEM;
+- goto exit;
+- }
+-
+ memset(&mmc_req, 0, sizeof(struct mmc_request));
+ memset(&mmc_cmd, 0, sizeof(struct mmc_command));
+ memset(&mmc_dat, 0, sizeof(struct mmc_data));
+
+- mmc_dat.sg = st.sgl;
++ mmc_dat.sg = sdiodev->sgtable.sgl;
+ mmc_dat.blksz = func_blk_sz;
+ mmc_dat.flags = write ? MMC_DATA_WRITE : MMC_DATA_READ;
+ mmc_cmd.opcode = SD_IO_RW_EXTENDED;
+@@ -558,7 +576,7 @@
+ while (seg_sz) {
+ req_sz = 0;
+ sg_cnt = 0;
+- sgl = st.sgl;
++ sgl = sdiodev->sgtable.sgl;
+ /* prep sg table */
+ while (pkt_next != (struct sk_buff *)target_list) {
+ pkt_data = pkt_next->data + pkt_offset;
+@@ -604,8 +622,7 @@
+
+ ret = mmc_cmd.error ? mmc_cmd.error : mmc_dat.error;
+ if (ret == -ENOMEDIUM) {
+- brcmf_bus_change_state(sdiodev->bus_if,
+- BRCMF_BUS_NOMEDIUM);
++ brcmf_sdiod_change_state(sdiodev, BRCMF_SDIOD_NOMEDIUM);
+ break;
+ } else if (ret != 0) {
+ brcmf_err("CMD53 sg block %s failed %d\n",
+@@ -640,7 +657,7 @@
+ }
+
+ exit:
+- sg_free_table(&st);
++ sg_init_table(sdiodev->sgtable.sgl, sdiodev->sgtable.orig_nents);
+ while ((pkt_next = __skb_dequeue(&local_list)) != NULL)
+ brcmu_pkt_buf_free_skb(pkt_next);
+
+@@ -827,7 +844,7 @@
+ }
+ if (!write)
+ memcpy(data, pkt->data, dsize);
+- skb_trim(pkt, dsize);
++ skb_trim(pkt, 0);
+
+ /* Adjust for next transfer (if any) */
+ size -= dsize;
+@@ -864,6 +881,110 @@
+ return 0;
+ }
+
++static void brcmf_sdiod_sgtable_alloc(struct brcmf_sdio_dev *sdiodev)
++{
++ uint nents;
++ int err;
++
++ if (!sdiodev->sg_support)
++ return;
++
++ nents = max_t(uint, BRCMF_DEFAULT_RXGLOM_SIZE, brcmf_sdiod_txglomsz);
++ nents += (nents >> 4) + 1;
++
++ WARN_ON(nents > sdiodev->max_segment_count);
++
++ brcmf_dbg(TRACE, "nents=%d\n", nents);
++ err = sg_alloc_table(&sdiodev->sgtable, nents, GFP_KERNEL);
++ if (err < 0) {
++ brcmf_err("allocation failed: disable scatter-gather");
++ sdiodev->sg_support = false;
++ }
++
++ sdiodev->txglomsz = brcmf_sdiod_txglomsz;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int brcmf_sdiod_freezer_attach(struct brcmf_sdio_dev *sdiodev)
++{
++ sdiodev->freezer = kzalloc(sizeof(*sdiodev->freezer), GFP_KERNEL);
++ if (!sdiodev->freezer)
++ return -ENOMEM;
++ atomic_set(&sdiodev->freezer->thread_count, 0);
++ atomic_set(&sdiodev->freezer->freezing, 0);
++ init_waitqueue_head(&sdiodev->freezer->thread_freeze);
++ init_completion(&sdiodev->freezer->resumed);
++ return 0;
++}
++
++static void brcmf_sdiod_freezer_detach(struct brcmf_sdio_dev *sdiodev)
++{
++ if (sdiodev->freezer) {
++ WARN_ON(atomic_read(&sdiodev->freezer->freezing));
++ kfree(sdiodev->freezer);
++ }
++}
++
++static int brcmf_sdiod_freezer_on(struct brcmf_sdio_dev *sdiodev)
++{
++ atomic_t *expect = &sdiodev->freezer->thread_count;
++ int res = 0;
++
++ sdiodev->freezer->frozen_count = 0;
++ reinit_completion(&sdiodev->freezer->resumed);
++ atomic_set(&sdiodev->freezer->freezing, 1);
++ brcmf_sdio_trigger_dpc(sdiodev->bus);
++ wait_event(sdiodev->freezer->thread_freeze,
++ atomic_read(expect) == sdiodev->freezer->frozen_count);
++ sdio_claim_host(sdiodev->func[1]);
++ res = brcmf_sdio_sleep(sdiodev->bus, true);
++ sdio_release_host(sdiodev->func[1]);
++ return res;
++}
++
++static void brcmf_sdiod_freezer_off(struct brcmf_sdio_dev *sdiodev)
++{
++ sdio_claim_host(sdiodev->func[1]);
++ brcmf_sdio_sleep(sdiodev->bus, false);
++ sdio_release_host(sdiodev->func[1]);
++ atomic_set(&sdiodev->freezer->freezing, 0);
++ complete_all(&sdiodev->freezer->resumed);
++}
++
++bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev)
++{
++ return atomic_read(&sdiodev->freezer->freezing);
++}
++
++void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev)
++{
++ if (!brcmf_sdiod_freezing(sdiodev))
++ return;
++ sdiodev->freezer->frozen_count++;
++ wake_up(&sdiodev->freezer->thread_freeze);
++ wait_for_completion(&sdiodev->freezer->resumed);
++}
++
++void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev)
++{
++ atomic_inc(&sdiodev->freezer->thread_count);
++}
++
++void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev)
++{
++ atomic_dec(&sdiodev->freezer->thread_count);
++}
++#else
++static int brcmf_sdiod_freezer_attach(struct brcmf_sdio_dev *sdiodev)
++{
++ return 0;
++}
++
++static void brcmf_sdiod_freezer_detach(struct brcmf_sdio_dev *sdiodev)
++{
++}
++#endif /* CONFIG_PM_SLEEP */
++
+ static int brcmf_sdiod_remove(struct brcmf_sdio_dev *sdiodev)
+ {
+ if (sdiodev->bus) {
+@@ -871,6 +992,8 @@
+ sdiodev->bus = NULL;
+ }
+
++ brcmf_sdiod_freezer_detach(sdiodev);
++
+ /* Disable Function 2 */
+ sdio_claim_host(sdiodev->func[2]);
+ sdio_disable_func(sdiodev->func[2]);
+@@ -881,11 +1004,21 @@
+ sdio_disable_func(sdiodev->func[1]);
+ sdio_release_host(sdiodev->func[1]);
+
++ sg_free_table(&sdiodev->sgtable);
+ sdiodev->sbwad = 0;
+
++ pm_runtime_allow(sdiodev->func[1]->card->host->parent);
+ return 0;
+ }
+
++static void brcmf_sdiod_host_fixup(struct mmc_host *host)
++{
++ /* runtime-pm powers off the device */
++ pm_runtime_forbid(host->parent);
++ /* avoid removal detection upon resume */
++ host->caps |= MMC_CAP_NONREMOVABLE;
++}
++
+ static int brcmf_sdiod_probe(struct brcmf_sdio_dev *sdiodev)
+ {
+ struct sdio_func *func;
+@@ -936,13 +1069,22 @@
+ SG_MAX_SINGLE_ALLOC);
+ sdiodev->max_segment_size = host->max_seg_size;
+
++ /* allocate scatter-gather table. sg support
++ * will be disabled upon allocation failure.
++ */
++ brcmf_sdiod_sgtable_alloc(sdiodev);
++
++ ret = brcmf_sdiod_freezer_attach(sdiodev);
++ if (ret)
++ goto out;
++
+ /* try to attach to the target device */
+ sdiodev->bus = brcmf_sdio_probe(sdiodev);
+ if (!sdiodev->bus) {
+ ret = -ENODEV;
+ goto out;
+ }
+-
++ brcmf_sdiod_host_fixup(host);
+ out:
+ if (ret)
+ brcmf_sdiod_remove(sdiodev);
+@@ -950,17 +1092,24 @@
+ return ret;
+ }
+
++#define BRCMF_SDIO_DEVICE(dev_id) \
++ {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, dev_id)}
++
+ /* devices we support, null terminated */
+ static const struct sdio_device_id brcmf_sdmmc_ids[] = {
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43143)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43241)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4329)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4330)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_4334)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM, SDIO_DEVICE_ID_BROADCOM_43362)},
+- {SDIO_DEVICE(SDIO_VENDOR_ID_BROADCOM,
+- SDIO_DEVICE_ID_BROADCOM_4335_4339)},
+- { /* end: all zeroes */ },
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43143),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43241),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4329),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4330),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4334),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43340),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43341),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43362),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4335_4339),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_43430),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4345),
++ BRCMF_SDIO_DEVICE(SDIO_DEVICE_ID_BROADCOM_4354),
++ { /* end: all zeroes */ }
+ };
+ MODULE_DEVICE_TABLE(sdio, brcmf_sdmmc_ids);
+
+@@ -1013,9 +1162,20 @@
+ sdiodev->dev = &sdiodev->func[1]->dev;
+ sdiodev->pdata = brcmfmac_sdio_pdata;
+
+- atomic_set(&sdiodev->suspend, false);
+- init_waitqueue_head(&sdiodev->request_word_wait);
+- init_waitqueue_head(&sdiodev->request_buffer_wait);
++ if (!sdiodev->pdata)
++ brcmf_of_probe(sdiodev);
++
++#ifdef CONFIG_PM_SLEEP
++ /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
++ * is true or when platform data OOB irq is true).
++ */
++ if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
++ ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
++ (sdiodev->pdata && sdiodev->pdata->oob_irq_supported)))
++ bus_if->wowl_supported = true;
++#endif
++
++ brcmf_sdiod_change_state(sdiodev, BRCMF_SDIOD_DOWN);
+
+ brcmf_dbg(SDIO, "F2 found, calling brcmf_sdiod_probe...\n");
+ err = brcmf_sdiod_probe(sdiodev);
+@@ -1046,7 +1206,7 @@
+ brcmf_dbg(SDIO, "sdio device ID: 0x%04x\n", func->device);
+ brcmf_dbg(SDIO, "Function: %d\n", func->num);
+
+- if (func->num != 1 && func->num != 2)
++ if (func->num != 1)
+ return;
+
+ bus_if = dev_get_drvdata(&func->dev);
+@@ -1065,42 +1225,58 @@
+ brcmf_dbg(SDIO, "Exit\n");
+ }
+
+-#ifdef CONFIG_PM_SLEEP
+-static int brcmf_ops_sdio_suspend(struct device *dev)
++void brcmf_sdio_wowl_config(struct device *dev, bool enabled)
+ {
+- mmc_pm_flag_t sdio_flags;
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- int ret = 0;
+
+- brcmf_dbg(SDIO, "\n");
++ brcmf_dbg(SDIO, "Configuring WOWL, enabled=%d\n", enabled);
++ sdiodev->wowl_enabled = enabled;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int brcmf_ops_sdio_suspend(struct device *dev)
++{
++ struct sdio_func *func;
++ struct brcmf_bus *bus_if;
++ struct brcmf_sdio_dev *sdiodev;
++ mmc_pm_flag_t sdio_flags;
+
+- atomic_set(&sdiodev->suspend, true);
++ func = container_of(dev, struct sdio_func, dev);
++ brcmf_dbg(SDIO, "Enter: F%d\n", func->num);
++ if (func->num != SDIO_FUNC_1)
++ return 0;
+
+- sdio_flags = sdio_get_host_pm_caps(sdiodev->func[1]);
+- if (!(sdio_flags & MMC_PM_KEEP_POWER)) {
+- brcmf_err("Host can't keep power while suspended\n");
+- return -EINVAL;
+- }
+
+- ret = sdio_set_host_pm_flags(sdiodev->func[1], MMC_PM_KEEP_POWER);
+- if (ret) {
+- brcmf_err("Failed to set pm_flags\n");
+- return ret;
+- }
++ bus_if = dev_get_drvdata(dev);
++ sdiodev = bus_if->bus_priv.sdio;
+
++ brcmf_sdiod_freezer_on(sdiodev);
+ brcmf_sdio_wd_timer(sdiodev->bus, 0);
+
+- return ret;
++ sdio_flags = MMC_PM_KEEP_POWER;
++ if (sdiodev->wowl_enabled) {
++ if (sdiodev->pdata->oob_irq_supported)
++ enable_irq_wake(sdiodev->pdata->oob_irq_nr);
++ else
++ sdio_flags |= MMC_PM_WAKE_SDIO_IRQ;
++ }
++ if (sdio_set_host_pm_flags(sdiodev->func[1], sdio_flags))
++ brcmf_err("Failed to set pm_flags %x\n", sdio_flags);
++ return 0;
+ }
+
+ static int brcmf_ops_sdio_resume(struct device *dev)
+ {
+ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct sdio_func *func = container_of(dev, struct sdio_func, dev);
++
++ brcmf_dbg(SDIO, "Enter: F%d\n", func->num);
++ if (func->num != SDIO_FUNC_2)
++ return 0;
+
+- brcmf_sdio_wd_timer(sdiodev->bus, BRCMF_WD_POLL_MS);
+- atomic_set(&sdiodev->suspend, false);
++ brcmf_sdiod_freezer_off(sdiodev);
+ return 0;
+ }
+
+@@ -1115,14 +1291,15 @@
+ .remove = brcmf_ops_sdio_remove,
+ .name = BRCMFMAC_SDIO_PDATA_NAME,
+ .id_table = brcmf_sdmmc_ids,
+-#ifdef CONFIG_PM_SLEEP
+ .drv = {
++ .owner = THIS_MODULE,
++#ifdef CONFIG_PM_SLEEP
+ .pm = &brcmf_sdio_pm_ops,
+- },
+ #endif /* CONFIG_PM_SLEEP */
++ },
+ };
+
+-static int brcmf_sdio_pd_probe(struct platform_device *pdev)
++static int __init brcmf_sdio_pd_probe(struct platform_device *pdev)
+ {
+ brcmf_dbg(SDIO, "Enter\n");
+
+@@ -1150,7 +1327,6 @@
+ .remove = brcmf_sdio_pd_remove,
+ .driver = {
+ .name = BRCMFMAC_SDIO_PDATA_NAME,
+- .owner = THIS_MODULE,
+ }
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/btcoex.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/btcoex.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/btcoex.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/btcoex.c 2016-06-19 22:11:55.273142107 +0200
+@@ -20,13 +20,13 @@
+ #include <brcmu_wifi.h>
+ #include <brcmu_utils.h>
+ #include <defs.h>
+-#include <dhd.h>
+-#include <dhd_dbg.h>
++#include "core.h"
++#include "debug.h"
+ #include "fwil.h"
+ #include "fwil_types.h"
+ #include "btcoex.h"
+ #include "p2p.h"
+-#include "wl_cfg80211.h"
++#include "cfg80211.h"
+
+ /* T1 start SCO/eSCO priority suppression */
+ #define BRCMF_BTCOEX_OPPR_WIN_TIME 2000
+@@ -157,7 +157,7 @@
+ */
+
+ /* save current */
+- brcmf_dbg(TRACE, "new SCO/eSCO coex algo {save & override}\n");
++ brcmf_dbg(INFO, "new SCO/eSCO coex algo {save & override}\n");
+ brcmf_btcoex_params_read(ifp, 50, &btci->reg50);
+ brcmf_btcoex_params_read(ifp, 51, &btci->reg51);
+ brcmf_btcoex_params_read(ifp, 64, &btci->reg64);
+@@ -165,7 +165,7 @@
+ brcmf_btcoex_params_read(ifp, 71, &btci->reg71);
+
+ btci->saved_regs_part2 = true;
+- brcmf_dbg(TRACE,
++ brcmf_dbg(INFO,
+ "saved bt_params[50,51,64,65,71]: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ btci->reg50, btci->reg51, btci->reg64,
+ btci->reg65, btci->reg71);
+@@ -179,21 +179,21 @@
+
+ } else if (btci->saved_regs_part2) {
+ /* restore previously saved bt params */
+- brcmf_dbg(TRACE, "Do new SCO/eSCO coex algo {restore}\n");
++ brcmf_dbg(INFO, "Do new SCO/eSCO coex algo {restore}\n");
+ brcmf_btcoex_params_write(ifp, 50, btci->reg50);
+ brcmf_btcoex_params_write(ifp, 51, btci->reg51);
+ brcmf_btcoex_params_write(ifp, 64, btci->reg64);
+ brcmf_btcoex_params_write(ifp, 65, btci->reg65);
+ brcmf_btcoex_params_write(ifp, 71, btci->reg71);
+
+- brcmf_dbg(TRACE,
++ brcmf_dbg(INFO,
+ "restored bt_params[50,51,64,65,71]: 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ btci->reg50, btci->reg51, btci->reg64,
+ btci->reg65, btci->reg71);
+
+ btci->saved_regs_part2 = false;
+ } else {
+- brcmf_err("attempted to restore not saved BTCOEX params\n");
++ brcmf_dbg(INFO, "attempted to restore not saved BTCOEX params\n");
+ }
+ }
+
+@@ -219,14 +219,14 @@
+ break;
+ }
+
+- brcmf_dbg(TRACE, "sample[%d], btc_params 27:%x\n", i, param27);
++ brcmf_dbg(INFO, "sample[%d], btc_params 27:%x\n", i, param27);
+
+ if ((param27 & 0x6) == 2) { /* count both sco & esco */
+ sco_id_cnt++;
+ }
+
+ if (sco_id_cnt > 2) {
+- brcmf_dbg(TRACE,
++ brcmf_dbg(INFO,
+ "sco/esco detected, pkt id_cnt:%d samples:%d\n",
+ sco_id_cnt, i);
+ res = true;
+@@ -250,7 +250,7 @@
+ brcmf_btcoex_params_read(ifp, 41, &btci->reg41);
+ brcmf_btcoex_params_read(ifp, 68, &btci->reg68);
+ btci->saved_regs_part1 = true;
+- brcmf_dbg(TRACE,
++ brcmf_dbg(INFO,
+ "saved btc_params regs (66,41,68) 0x%x 0x%x 0x%x\n",
+ btci->reg66, btci->reg41,
+ btci->reg68);
+@@ -270,7 +270,7 @@
+ brcmf_btcoex_params_write(ifp, 66, btci->reg66);
+ brcmf_btcoex_params_write(ifp, 41, btci->reg41);
+ brcmf_btcoex_params_write(ifp, 68, btci->reg68);
+- brcmf_dbg(TRACE,
++ brcmf_dbg(INFO,
+ "restored btc_params regs {66,41,68} 0x%x 0x%x 0x%x\n",
+ btci->reg66, btci->reg41,
+ btci->reg68);
+@@ -307,7 +307,7 @@
+ /* DHCP started provide OPPORTUNITY window
+ to get DHCP address
+ */
+- brcmf_dbg(TRACE, "DHCP started\n");
++ brcmf_dbg(INFO, "DHCP started\n");
+ btci->bt_state = BRCMF_BT_DHCP_OPPR_WIN;
+ if (btci->timeout < BRCMF_BTCOEX_OPPR_WIN_TIME) {
+ mod_timer(&btci->timer, btci->timer.expires);
+@@ -322,12 +322,12 @@
+
+ case BRCMF_BT_DHCP_OPPR_WIN:
+ if (btci->dhcp_done) {
+- brcmf_dbg(TRACE, "DHCP done before T1 expiration\n");
++ brcmf_dbg(INFO, "DHCP done before T1 expiration\n");
+ goto idle;
+ }
+
+ /* DHCP is not over yet, start lowering BT priority */
+- brcmf_dbg(TRACE, "DHCP T1:%d expired\n",
++ brcmf_dbg(INFO, "DHCP T1:%d expired\n",
+ BRCMF_BTCOEX_OPPR_WIN_TIME);
+ brcmf_btcoex_boost_wifi(btci, true);
+
+@@ -339,9 +339,9 @@
+
+ case BRCMF_BT_DHCP_FLAG_FORCE_TIMEOUT:
+ if (btci->dhcp_done)
+- brcmf_dbg(TRACE, "DHCP done before T2 expiration\n");
++ brcmf_dbg(INFO, "DHCP done before T2 expiration\n");
+ else
+- brcmf_dbg(TRACE, "DHCP T2:%d expired\n",
++ brcmf_dbg(INFO, "DHCP T2:%d expired\n",
+ BRCMF_BT_DHCP_FLAG_FORCE_TIMEOUT);
+
+ goto idle;
+@@ -440,13 +440,13 @@
+ /* Stop any bt timer because DHCP session is done */
+ btci->dhcp_done = true;
+ if (btci->timer_on) {
+- brcmf_dbg(TRACE, "disable BT DHCP Timer\n");
++ brcmf_dbg(INFO, "disable BT DHCP Timer\n");
+ btci->timer_on = false;
+ del_timer_sync(&btci->timer);
+
+ /* schedule worker if transition to IDLE is needed */
+ if (btci->bt_state != BRCMF_BT_DHCP_IDLE) {
+- brcmf_dbg(TRACE, "bt_state:%d\n",
++ brcmf_dbg(INFO, "bt_state:%d\n",
+ btci->bt_state);
+ schedule_work(&btci->work);
+ }
+@@ -472,7 +472,7 @@
+
+ switch (mode) {
+ case BRCMF_BTCOEX_DISABLED:
+- brcmf_dbg(TRACE, "DHCP session starts\n");
++ brcmf_dbg(INFO, "DHCP session starts\n");
+ if (btci->bt_state != BRCMF_BT_DHCP_IDLE)
+ return -EBUSY;
+ /* Start BT timer only for SCO connection */
+@@ -484,14 +484,14 @@
+ break;
+
+ case BRCMF_BTCOEX_ENABLED:
+- brcmf_dbg(TRACE, "DHCP session ends\n");
++ brcmf_dbg(INFO, "DHCP session ends\n");
+ if (btci->bt_state != BRCMF_BT_DHCP_IDLE &&
+ vif == btci->vif) {
+ brcmf_btcoex_dhcp_end(btci);
+ }
+ break;
+ default:
+- brcmf_dbg(TRACE, "Unknown mode, ignored\n");
++ brcmf_dbg(INFO, "Unknown mode, ignored\n");
+ }
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bus.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bus.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/bus.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/bus.h 2016-06-19 22:11:55.273142107 +0200
+@@ -0,0 +1,227 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef BRCMFMAC_BUS_H
++#define BRCMFMAC_BUS_H
++
++#include "debug.h"
++
++/* IDs of the 6 default common rings of msgbuf protocol */
++#define BRCMF_H2D_MSGRING_CONTROL_SUBMIT 0
++#define BRCMF_H2D_MSGRING_RXPOST_SUBMIT 1
++#define BRCMF_D2H_MSGRING_CONTROL_COMPLETE 2
++#define BRCMF_D2H_MSGRING_TX_COMPLETE 3
++#define BRCMF_D2H_MSGRING_RX_COMPLETE 4
++
++#define BRCMF_NROF_H2D_COMMON_MSGRINGS 2
++#define BRCMF_NROF_D2H_COMMON_MSGRINGS 3
++#define BRCMF_NROF_COMMON_MSGRINGS (BRCMF_NROF_H2D_COMMON_MSGRINGS + \
++ BRCMF_NROF_D2H_COMMON_MSGRINGS)
++
++/* The level of bus communication with the dongle */
++enum brcmf_bus_state {
++ BRCMF_BUS_DOWN, /* Not ready for frame transfers */
++ BRCMF_BUS_UP /* Ready for frame transfers */
++};
++
++/* The level of bus communication with the dongle */
++enum brcmf_bus_protocol_type {
++ BRCMF_PROTO_BCDC,
++ BRCMF_PROTO_MSGBUF
++};
++
++struct brcmf_bus_dcmd {
++ char *name;
++ char *param;
++ int param_len;
++ struct list_head list;
++};
++
++/**
++ * struct brcmf_bus_ops - bus callback operations.
++ *
++ * @preinit: execute bus/device specific dongle init commands (optional).
++ * @init: prepare for communication with dongle.
++ * @stop: clear pending frames, disable data flow.
++ * @txdata: send a data frame to the dongle. When the data
++ * has been transferred, the common driver must be
++ * notified using brcmf_txcomplete(). The common
++ * driver calls this function with interrupts
++ * disabled.
++ * @txctl: transmit a control request message to dongle.
++ * @rxctl: receive a control response message from dongle.
++ * @gettxq: obtain a reference of bus transmit queue (optional).
++ * @wowl_config: specify if dongle is configured for wowl when going to suspend
++ *
++ * This structure provides an abstract interface towards the
++ * bus specific driver. For control messages to common driver
++ * will assure there is only one active transaction. Unless
++ * indicated otherwise these callbacks are mandatory.
++ */
++struct brcmf_bus_ops {
++ int (*preinit)(struct device *dev);
++ void (*stop)(struct device *dev);
++ int (*txdata)(struct device *dev, struct sk_buff *skb);
++ int (*txctl)(struct device *dev, unsigned char *msg, uint len);
++ int (*rxctl)(struct device *dev, unsigned char *msg, uint len);
++ struct pktq * (*gettxq)(struct device *dev);
++ void (*wowl_config)(struct device *dev, bool enabled);
++};
++
++
++/**
++ * struct brcmf_bus_msgbuf - bus ringbuf if in case of msgbuf.
++ *
++ * @commonrings: commonrings which are always there.
++ * @flowrings: commonrings which are dynamically created and destroyed for data.
++ * @rx_dataoffset: if set then all rx data has this this offset.
++ * @max_rxbufpost: maximum number of buffers to post for rx.
++ * @nrof_flowrings: number of flowrings.
++ */
++struct brcmf_bus_msgbuf {
++ struct brcmf_commonring *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
++ struct brcmf_commonring **flowrings;
++ u32 rx_dataoffset;
++ u32 max_rxbufpost;
++ u32 nrof_flowrings;
++};
++
++
++/**
++ * struct brcmf_bus - interface structure between common and bus layer
++ *
++ * @bus_priv: pointer to private bus device.
++ * @proto_type: protocol type, bcdc or msgbuf
++ * @dev: device pointer of bus device.
++ * @drvr: public driver information.
++ * @state: operational state of the bus interface.
++ * @maxctl: maximum size for rxctl request message.
++ * @tx_realloc: number of tx packets realloced for headroom.
++ * @dstats: dongle-based statistical data.
++ * @dcmd_list: bus/device specific dongle initialization commands.
++ * @chip: device identifier of the dongle chip.
++ * @wowl_supported: is wowl supported by bus driver.
++ * @chiprev: revision of the dongle chip.
++ */
++struct brcmf_bus {
++ union {
++ struct brcmf_sdio_dev *sdio;
++ struct brcmf_usbdev *usb;
++ struct brcmf_pciedev *pcie;
++ } bus_priv;
++ enum brcmf_bus_protocol_type proto_type;
++ struct device *dev;
++ struct brcmf_pub *drvr;
++ enum brcmf_bus_state state;
++ uint maxctl;
++ unsigned long tx_realloc;
++ u32 chip;
++ u32 chiprev;
++ bool always_use_fws_queue;
++ bool wowl_supported;
++
++ struct brcmf_bus_ops *ops;
++ struct brcmf_bus_msgbuf *msgbuf;
++};
++
++/*
++ * callback wrappers
++ */
++static inline int brcmf_bus_preinit(struct brcmf_bus *bus)
++{
++ if (!bus->ops->preinit)
++ return 0;
++ return bus->ops->preinit(bus->dev);
++}
++
++static inline void brcmf_bus_stop(struct brcmf_bus *bus)
++{
++ bus->ops->stop(bus->dev);
++}
++
++static inline int brcmf_bus_txdata(struct brcmf_bus *bus, struct sk_buff *skb)
++{
++ return bus->ops->txdata(bus->dev, skb);
++}
++
++static inline
++int brcmf_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint len)
++{
++ return bus->ops->txctl(bus->dev, msg, len);
++}
++
++static inline
++int brcmf_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint len)
++{
++ return bus->ops->rxctl(bus->dev, msg, len);
++}
++
++static inline
++struct pktq *brcmf_bus_gettxq(struct brcmf_bus *bus)
++{
++ if (!bus->ops->gettxq)
++ return ERR_PTR(-ENOENT);
++
++ return bus->ops->gettxq(bus->dev);
++}
++
++static inline
++void brcmf_bus_wowl_config(struct brcmf_bus *bus, bool enabled)
++{
++ if (bus->ops->wowl_config)
++ bus->ops->wowl_config(bus->dev, enabled);
++}
++
++/*
++ * interface functions from common layer
++ */
++
++bool brcmf_c_prec_enq(struct device *dev, struct pktq *q, struct sk_buff *pkt,
++ int prec);
++
++/* Receive frame for delivery to OS. Callee disposes of rxp. */
++void brcmf_rx_frame(struct device *dev, struct sk_buff *rxp);
++
++/* Indication from bus module regarding presence/insertion of dongle. */
++int brcmf_attach(struct device *dev);
++/* Indication from bus module regarding removal/absence of dongle */
++void brcmf_detach(struct device *dev);
++/* Indication from bus module that dongle should be reset */
++void brcmf_dev_reset(struct device *dev);
++/* Indication from bus module to change flow-control state */
++void brcmf_txflowblock(struct device *dev, bool state);
++
++/* Notify the bus has transferred the tx packet to firmware */
++void brcmf_txcomplete(struct device *dev, struct sk_buff *txp, bool success);
++
++/* Configure the "global" bus state used by upper layers */
++void brcmf_bus_change_state(struct brcmf_bus *bus, enum brcmf_bus_state state);
++
++int brcmf_bus_start(struct device *dev);
++s32 brcmf_iovar_data_set(struct device *dev, char *name, void *data, u32 len);
++void brcmf_bus_add_txhdrlen(struct device *dev, uint len);
++
++#ifdef CONFIG_BRCMFMAC_SDIO
++void brcmf_sdio_exit(void);
++void brcmf_sdio_init(void);
++void brcmf_sdio_register(void);
++#endif
++#ifdef CONFIG_BRCMFMAC_USB
++void brcmf_usb_exit(void);
++void brcmf_usb_register(void);
++#endif
++
++#endif /* BRCMFMAC_BUS_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.c 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,6188 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++/* Toplevel file. Relies on dhd_linux.c to send commands to the dongle. */
++
++#include <linux/kernel.h>
++#include <linux/etherdevice.h>
++#include <linux/module.h>
++#include <linux/vmalloc.h>
++#include <net/cfg80211.h>
++#include <net/netlink.h>
++
++#include <brcmu_utils.h>
++#include <defs.h>
++#include <brcmu_wifi.h>
++#include "core.h"
++#include "debug.h"
++#include "tracepoint.h"
++#include "fwil_types.h"
++#include "p2p.h"
++#include "btcoex.h"
++#include "cfg80211.h"
++#include "feature.h"
++#include "fwil.h"
++#include "proto.h"
++#include "vendor.h"
++#include "bus.h"
++#include "common.h"
++
++#define BRCMF_SCAN_IE_LEN_MAX 2048
++#define BRCMF_PNO_VERSION 2
++#define BRCMF_PNO_TIME 30
++#define BRCMF_PNO_REPEAT 4
++#define BRCMF_PNO_FREQ_EXPO_MAX 3
++#define BRCMF_PNO_MAX_PFN_COUNT 16
++#define BRCMF_PNO_ENABLE_ADAPTSCAN_BIT 6
++#define BRCMF_PNO_HIDDEN_BIT 2
++#define BRCMF_PNO_WPA_AUTH_ANY 0xFFFFFFFF
++#define BRCMF_PNO_SCAN_COMPLETE 1
++#define BRCMF_PNO_SCAN_INCOMPLETE 0
++
++#define BRCMF_IFACE_MAX_CNT 3
++
++#define WPA_OUI "\x00\x50\xF2" /* WPA OUI */
++#define WPA_OUI_TYPE 1
++#define RSN_OUI "\x00\x0F\xAC" /* RSN OUI */
++#define WME_OUI_TYPE 2
++#define WPS_OUI_TYPE 4
++
++#define VS_IE_FIXED_HDR_LEN 6
++#define WPA_IE_VERSION_LEN 2
++#define WPA_IE_MIN_OUI_LEN 4
++#define WPA_IE_SUITE_COUNT_LEN 2
++
++#define WPA_CIPHER_NONE 0 /* None */
++#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
++#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
++#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
++#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
++
++#define RSN_AKM_NONE 0 /* None (IBSS) */
++#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
++#define RSN_AKM_PSK 2 /* Pre-shared Key */
++#define RSN_CAP_LEN 2 /* Length of RSN capabilities */
++#define RSN_CAP_PTK_REPLAY_CNTR_MASK 0x000C
++
++#define VNDR_IE_CMD_LEN 4 /* length of the set command
++ * string :"add", "del" (+ NUL)
++ */
++#define VNDR_IE_COUNT_OFFSET 4
++#define VNDR_IE_PKTFLAG_OFFSET 8
++#define VNDR_IE_VSIE_OFFSET 12
++#define VNDR_IE_HDR_SIZE 12
++#define VNDR_IE_PARSE_LIMIT 5
++
++#define DOT11_MGMT_HDR_LEN 24 /* d11 management header len */
++#define DOT11_BCN_PRB_FIXED_LEN 12 /* beacon/probe fixed length */
++
++#define BRCMF_SCAN_JOIN_ACTIVE_DWELL_TIME_MS 320
++#define BRCMF_SCAN_JOIN_PASSIVE_DWELL_TIME_MS 400
++#define BRCMF_SCAN_JOIN_PROBE_INTERVAL_MS 20
++
++#define BRCMF_ASSOC_PARAMS_FIXED_SIZE \
++ (sizeof(struct brcmf_assoc_params_le) - sizeof(u16))
++
++static bool check_vif_up(struct brcmf_cfg80211_vif *vif)
++{
++ if (!test_bit(BRCMF_VIF_STATUS_READY, &vif->sme_state)) {
++ brcmf_dbg(INFO, "device is not ready : status (%lu)\n",
++ vif->sme_state);
++ return false;
++ }
++ return true;
++}
++
++#define RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
++#define RATETAB_ENT(_rateid, _flags) \
++ { \
++ .bitrate = RATE_TO_BASE100KBPS(_rateid), \
++ .hw_value = (_rateid), \
++ .flags = (_flags), \
++ }
++
++static struct ieee80211_rate __wl_rates[] = {
++ RATETAB_ENT(BRCM_RATE_1M, 0),
++ RATETAB_ENT(BRCM_RATE_2M, IEEE80211_RATE_SHORT_PREAMBLE),
++ RATETAB_ENT(BRCM_RATE_5M5, IEEE80211_RATE_SHORT_PREAMBLE),
++ RATETAB_ENT(BRCM_RATE_11M, IEEE80211_RATE_SHORT_PREAMBLE),
++ RATETAB_ENT(BRCM_RATE_6M, 0),
++ RATETAB_ENT(BRCM_RATE_9M, 0),
++ RATETAB_ENT(BRCM_RATE_12M, 0),
++ RATETAB_ENT(BRCM_RATE_18M, 0),
++ RATETAB_ENT(BRCM_RATE_24M, 0),
++ RATETAB_ENT(BRCM_RATE_36M, 0),
++ RATETAB_ENT(BRCM_RATE_48M, 0),
++ RATETAB_ENT(BRCM_RATE_54M, 0),
++};
++
++#define wl_g_rates (__wl_rates + 0)
++#define wl_g_rates_size ARRAY_SIZE(__wl_rates)
++#define wl_a_rates (__wl_rates + 4)
++#define wl_a_rates_size (wl_g_rates_size - 4)
++
++#define CHAN2G(_channel, _freq) { \
++ .band = IEEE80211_BAND_2GHZ, \
++ .center_freq = (_freq), \
++ .hw_value = (_channel), \
++ .flags = IEEE80211_CHAN_DISABLED, \
++ .max_antenna_gain = 0, \
++ .max_power = 30, \
++}
++
++#define CHAN5G(_channel) { \
++ .band = IEEE80211_BAND_5GHZ, \
++ .center_freq = 5000 + (5 * (_channel)), \
++ .hw_value = (_channel), \
++ .flags = IEEE80211_CHAN_DISABLED, \
++ .max_antenna_gain = 0, \
++ .max_power = 30, \
++}
++
++static struct ieee80211_channel __wl_2ghz_channels[] = {
++ CHAN2G(1, 2412), CHAN2G(2, 2417), CHAN2G(3, 2422), CHAN2G(4, 2427),
++ CHAN2G(5, 2432), CHAN2G(6, 2437), CHAN2G(7, 2442), CHAN2G(8, 2447),
++ CHAN2G(9, 2452), CHAN2G(10, 2457), CHAN2G(11, 2462), CHAN2G(12, 2467),
++ CHAN2G(13, 2472), CHAN2G(14, 2484)
++};
++
++static struct ieee80211_channel __wl_5ghz_channels[] = {
++ CHAN5G(34), CHAN5G(36), CHAN5G(38), CHAN5G(40), CHAN5G(42),
++ CHAN5G(44), CHAN5G(46), CHAN5G(48), CHAN5G(52), CHAN5G(56),
++ CHAN5G(60), CHAN5G(64), CHAN5G(100), CHAN5G(104), CHAN5G(108),
++ CHAN5G(112), CHAN5G(116), CHAN5G(120), CHAN5G(124), CHAN5G(128),
++ CHAN5G(132), CHAN5G(136), CHAN5G(140), CHAN5G(144), CHAN5G(149),
++ CHAN5G(153), CHAN5G(157), CHAN5G(161), CHAN5G(165)
++};
++
++/* Band templates duplicated per wiphy. The channel info
++ * above is added to the band during setup.
++ */
++static const struct ieee80211_supported_band __wl_band_2ghz = {
++ .band = IEEE80211_BAND_2GHZ,
++ .bitrates = wl_g_rates,
++ .n_bitrates = wl_g_rates_size,
++};
++
++static const struct ieee80211_supported_band __wl_band_5ghz = {
++ .band = IEEE80211_BAND_5GHZ,
++ .bitrates = wl_a_rates,
++ .n_bitrates = wl_a_rates_size,
++};
++
++/* This is to override regulatory domains defined in cfg80211 module (reg.c)
++ * By default world regulatory domain defined in reg.c puts the flags
++ * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
++ * With respect to these flags, wpa_supplicant doesn't * start p2p
++ * operations on 5GHz channels. All the changes in world regulatory
++ * domain are to be done here.
++ */
++static const struct ieee80211_regdomain brcmf_regdom = {
++ .n_reg_rules = 4,
++ .alpha2 = "99",
++ .reg_rules = {
++ /* IEEE 802.11b/g, channels 1..11 */
++ REG_RULE(2412-10, 2472+10, 40, 6, 20, 0),
++ /* If any */
++ /* IEEE 802.11 channel 14 - Only JP enables
++ * this and for 802.11b only
++ */
++ REG_RULE(2484-10, 2484+10, 20, 6, 20, 0),
++ /* IEEE 802.11a, channel 36..64 */
++ REG_RULE(5150-10, 5350+10, 80, 6, 20, 0),
++ /* IEEE 802.11a, channel 100..165 */
++ REG_RULE(5470-10, 5850+10, 80, 6, 20, 0), }
++};
++
++static const u32 __wl_cipher_suites[] = {
++ WLAN_CIPHER_SUITE_WEP40,
++ WLAN_CIPHER_SUITE_WEP104,
++ WLAN_CIPHER_SUITE_TKIP,
++ WLAN_CIPHER_SUITE_CCMP,
++ WLAN_CIPHER_SUITE_AES_CMAC,
++};
++
++/* Vendor specific ie. id = 221, oui and type defines exact ie */
++struct brcmf_vs_tlv {
++ u8 id;
++ u8 len;
++ u8 oui[3];
++ u8 oui_type;
++};
++
++struct parsed_vndr_ie_info {
++ u8 *ie_ptr;
++ u32 ie_len; /* total length including id & length field */
++ struct brcmf_vs_tlv vndrie;
++};
++
++struct parsed_vndr_ies {
++ u32 count;
++ struct parsed_vndr_ie_info ie_info[VNDR_IE_PARSE_LIMIT];
++};
++
++static int brcmf_roamoff;
++module_param_named(roamoff, brcmf_roamoff, int, S_IRUSR);
++MODULE_PARM_DESC(roamoff, "do not use internal roaming engine");
++
++/* Quarter dBm units to mW
++ * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
++ * Table is offset so the last entry is largest mW value that fits in
++ * a u16.
++ */
++
++#define QDBM_OFFSET 153 /* Offset for first entry */
++#define QDBM_TABLE_LEN 40 /* Table size */
++
++/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
++ * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
++ */
++#define QDBM_TABLE_LOW_BOUND 6493 /* Low bound */
++
++/* Largest mW value that will round down to the last table entry,
++ * QDBM_OFFSET + QDBM_TABLE_LEN-1.
++ * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) +
++ * mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
++ */
++#define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */
++
++static const u16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
++/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
++/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
++/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
++/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
++/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
++/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
++};
++
++static u16 brcmf_qdbm_to_mw(u8 qdbm)
++{
++ uint factor = 1;
++ int idx = qdbm - QDBM_OFFSET;
++
++ if (idx >= QDBM_TABLE_LEN)
++ /* clamp to max u16 mW value */
++ return 0xFFFF;
++
++ /* scale the qdBm index up to the range of the table 0-40
++ * where an offset of 40 qdBm equals a factor of 10 mW.
++ */
++ while (idx < 0) {
++ idx += 40;
++ factor *= 10;
++ }
++
++ /* return the mW value scaled down to the correct factor of 10,
++ * adding in factor/2 to get proper rounding.
++ */
++ return (nqdBm_to_mW_map[idx] + factor / 2) / factor;
++}
++
++static u8 brcmf_mw_to_qdbm(u16 mw)
++{
++ u8 qdbm;
++ int offset;
++ uint mw_uint = mw;
++ uint boundary;
++
++ /* handle boundary case */
++ if (mw_uint <= 1)
++ return 0;
++
++ offset = QDBM_OFFSET;
++
++ /* move mw into the range of the table */
++ while (mw_uint < QDBM_TABLE_LOW_BOUND) {
++ mw_uint *= 10;
++ offset -= 40;
++ }
++
++ for (qdbm = 0; qdbm < QDBM_TABLE_LEN - 1; qdbm++) {
++ boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm + 1] -
++ nqdBm_to_mW_map[qdbm]) / 2;
++ if (mw_uint < boundary)
++ break;
++ }
++
++ qdbm += (u8) offset;
++
++ return qdbm;
++}
++
++static u16 chandef_to_chanspec(struct brcmu_d11inf *d11inf,
++ struct cfg80211_chan_def *ch)
++{
++ struct brcmu_chan ch_inf;
++ s32 primary_offset;
++
++ brcmf_dbg(TRACE, "chandef: control %d center %d width %d\n",
++ ch->chan->center_freq, ch->center_freq1, ch->width);
++ ch_inf.chnum = ieee80211_frequency_to_channel(ch->center_freq1);
++ primary_offset = ch->center_freq1 - ch->chan->center_freq;
++ switch (ch->width) {
++ case NL80211_CHAN_WIDTH_20:
++ case NL80211_CHAN_WIDTH_20_NOHT:
++ ch_inf.bw = BRCMU_CHAN_BW_20;
++ WARN_ON(primary_offset != 0);
++ break;
++ case NL80211_CHAN_WIDTH_40:
++ ch_inf.bw = BRCMU_CHAN_BW_40;
++ if (primary_offset < 0)
++ ch_inf.sb = BRCMU_CHAN_SB_U;
++ else
++ ch_inf.sb = BRCMU_CHAN_SB_L;
++ break;
++ case NL80211_CHAN_WIDTH_80:
++ ch_inf.bw = BRCMU_CHAN_BW_80;
++ if (primary_offset < 0) {
++ if (primary_offset < -CH_10MHZ_APART)
++ ch_inf.sb = BRCMU_CHAN_SB_UU;
++ else
++ ch_inf.sb = BRCMU_CHAN_SB_UL;
++ } else {
++ if (primary_offset > CH_10MHZ_APART)
++ ch_inf.sb = BRCMU_CHAN_SB_LL;
++ else
++ ch_inf.sb = BRCMU_CHAN_SB_LU;
++ }
++ break;
++ case NL80211_CHAN_WIDTH_80P80:
++ case NL80211_CHAN_WIDTH_160:
++ case NL80211_CHAN_WIDTH_5:
++ case NL80211_CHAN_WIDTH_10:
++ default:
++ WARN_ON_ONCE(1);
++ }
++ switch (ch->chan->band) {
++ case IEEE80211_BAND_2GHZ:
++ ch_inf.band = BRCMU_CHAN_BAND_2G;
++ break;
++ case IEEE80211_BAND_5GHZ:
++ ch_inf.band = BRCMU_CHAN_BAND_5G;
++ break;
++ case IEEE80211_BAND_60GHZ:
++ default:
++ WARN_ON_ONCE(1);
++ }
++ d11inf->encchspec(&ch_inf);
++
++ return ch_inf.chspec;
++}
++
++u16 channel_to_chanspec(struct brcmu_d11inf *d11inf,
++ struct ieee80211_channel *ch)
++{
++ struct brcmu_chan ch_inf;
++
++ ch_inf.chnum = ieee80211_frequency_to_channel(ch->center_freq);
++ ch_inf.bw = BRCMU_CHAN_BW_20;
++ d11inf->encchspec(&ch_inf);
++
++ return ch_inf.chspec;
++}
++
++/* Traverse a string of 1-byte tag/1-byte length/variable-length value
++ * triples, returning a pointer to the substring whose first element
++ * matches tag
++ */
++const struct brcmf_tlv *
++brcmf_parse_tlvs(const void *buf, int buflen, uint key)
++{
++ const struct brcmf_tlv *elt = buf;
++ int totlen = buflen;
++
++ /* find tagged parameter */
++ while (totlen >= TLV_HDR_LEN) {
++ int len = elt->len;
++
++ /* validate remaining totlen */
++ if ((elt->id == key) && (totlen >= (len + TLV_HDR_LEN)))
++ return elt;
++
++ elt = (struct brcmf_tlv *)((u8 *)elt + (len + TLV_HDR_LEN));
++ totlen -= (len + TLV_HDR_LEN);
++ }
++
++ return NULL;
++}
++
++/* Is any of the tlvs the expected entry? If
++ * not update the tlvs buffer pointer/length.
++ */
++static bool
++brcmf_tlv_has_ie(const u8 *ie, const u8 **tlvs, u32 *tlvs_len,
++ const u8 *oui, u32 oui_len, u8 type)
++{
++ /* If the contents match the OUI and the type */
++ if (ie[TLV_LEN_OFF] >= oui_len + 1 &&
++ !memcmp(&ie[TLV_BODY_OFF], oui, oui_len) &&
++ type == ie[TLV_BODY_OFF + oui_len]) {
++ return true;
++ }
++
++ if (tlvs == NULL)
++ return false;
++ /* point to the next ie */
++ ie += ie[TLV_LEN_OFF] + TLV_HDR_LEN;
++ /* calculate the length of the rest of the buffer */
++ *tlvs_len -= (int)(ie - *tlvs);
++ /* update the pointer to the start of the buffer */
++ *tlvs = ie;
++
++ return false;
++}
++
++static struct brcmf_vs_tlv *
++brcmf_find_wpaie(const u8 *parse, u32 len)
++{
++ const struct brcmf_tlv *ie;
++
++ while ((ie = brcmf_parse_tlvs(parse, len, WLAN_EID_VENDOR_SPECIFIC))) {
++ if (brcmf_tlv_has_ie((const u8 *)ie, &parse, &len,
++ WPA_OUI, TLV_OUI_LEN, WPA_OUI_TYPE))
++ return (struct brcmf_vs_tlv *)ie;
++ }
++ return NULL;
++}
++
++static struct brcmf_vs_tlv *
++brcmf_find_wpsie(const u8 *parse, u32 len)
++{
++ const struct brcmf_tlv *ie;
++
++ while ((ie = brcmf_parse_tlvs(parse, len, WLAN_EID_VENDOR_SPECIFIC))) {
++ if (brcmf_tlv_has_ie((u8 *)ie, &parse, &len,
++ WPA_OUI, TLV_OUI_LEN, WPS_OUI_TYPE))
++ return (struct brcmf_vs_tlv *)ie;
++ }
++ return NULL;
++}
++
++
++static void convert_key_from_CPU(struct brcmf_wsec_key *key,
++ struct brcmf_wsec_key_le *key_le)
++{
++ key_le->index = cpu_to_le32(key->index);
++ key_le->len = cpu_to_le32(key->len);
++ key_le->algo = cpu_to_le32(key->algo);
++ key_le->flags = cpu_to_le32(key->flags);
++ key_le->rxiv.hi = cpu_to_le32(key->rxiv.hi);
++ key_le->rxiv.lo = cpu_to_le16(key->rxiv.lo);
++ key_le->iv_initialized = cpu_to_le32(key->iv_initialized);
++ memcpy(key_le->data, key->data, sizeof(key->data));
++ memcpy(key_le->ea, key->ea, sizeof(key->ea));
++}
++
++static int
++send_key_to_dongle(struct brcmf_if *ifp, struct brcmf_wsec_key *key)
++{
++ int err;
++ struct brcmf_wsec_key_le key_le;
++
++ convert_key_from_CPU(key, &key_le);
++
++ brcmf_netdev_wait_pend8021x(ifp);
++
++ err = brcmf_fil_bsscfg_data_set(ifp, "wsec_key", &key_le,
++ sizeof(key_le));
++
++ if (err)
++ brcmf_err("wsec_key error (%d)\n", err);
++ return err;
++}
++
++static s32
++brcmf_configure_arp_offload(struct brcmf_if *ifp, bool enable)
++{
++ s32 err;
++ u32 mode;
++
++ if (enable)
++ mode = BRCMF_ARP_OL_AGENT | BRCMF_ARP_OL_PEER_AUTO_REPLY;
++ else
++ mode = 0;
++
++ /* Try to set and enable ARP offload feature, this may fail, then it */
++ /* is simply not supported and err 0 will be returned */
++ err = brcmf_fil_iovar_int_set(ifp, "arp_ol", mode);
++ if (err) {
++ brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
++ mode, err);
++ err = 0;
++ } else {
++ err = brcmf_fil_iovar_int_set(ifp, "arpoe", enable);
++ if (err) {
++ brcmf_dbg(TRACE, "failed to configure (%d) ARP offload err = %d\n",
++ enable, err);
++ err = 0;
++ } else
++ brcmf_dbg(TRACE, "successfully configured (%d) ARP offload to 0x%x\n",
++ enable, mode);
++ }
++
++ return err;
++}
++
++static void
++brcmf_cfg80211_update_proto_addr_mode(struct wireless_dev *wdev)
++{
++ struct brcmf_cfg80211_vif *vif;
++ struct brcmf_if *ifp;
++
++ vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
++ ifp = vif->ifp;
++
++ if ((wdev->iftype == NL80211_IFTYPE_ADHOC) ||
++ (wdev->iftype == NL80211_IFTYPE_AP) ||
++ (wdev->iftype == NL80211_IFTYPE_P2P_GO))
++ brcmf_proto_configure_addr_mode(ifp->drvr, ifp->ifidx,
++ ADDR_DIRECT);
++ else
++ brcmf_proto_configure_addr_mode(ifp->drvr, ifp->ifidx,
++ ADDR_INDIRECT);
++}
++
++static int brcmf_cfg80211_request_ap_if(struct brcmf_if *ifp)
++{
++ struct brcmf_mbss_ssid_le mbss_ssid_le;
++ int bsscfgidx;
++ int err;
++
++ memset(&mbss_ssid_le, 0, sizeof(mbss_ssid_le));
++ bsscfgidx = brcmf_get_next_free_bsscfgidx(ifp->drvr);
++ if (bsscfgidx < 0)
++ return bsscfgidx;
++
++ mbss_ssid_le.bsscfgidx = cpu_to_le32(bsscfgidx);
++ mbss_ssid_le.SSID_len = cpu_to_le32(5);
++ sprintf(mbss_ssid_le.SSID, "ssid%d" , bsscfgidx);
++
++ err = brcmf_fil_bsscfg_data_set(ifp, "bsscfg:ssid", &mbss_ssid_le,
++ sizeof(mbss_ssid_le));
++ if (err < 0)
++ brcmf_err("setting ssid failed %d\n", err);
++
++ return err;
++}
++
++/**
++ * brcmf_ap_add_vif() - create a new AP virtual interface for multiple BSS
++ *
++ * @wiphy: wiphy device of new interface.
++ * @name: name of the new interface.
++ * @flags: not used.
++ * @params: contains mac address for AP device.
++ */
++static
++struct wireless_dev *brcmf_ap_add_vif(struct wiphy *wiphy, const char *name,
++ u32 *flags, struct vif_params *params)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
++ struct brcmf_cfg80211_vif *vif;
++ int err;
++
++ if (brcmf_cfg80211_vif_event_armed(cfg))
++ return ERR_PTR(-EBUSY);
++
++ brcmf_dbg(INFO, "Adding vif \"%s\"\n", name);
++
++ vif = brcmf_alloc_vif(cfg, NL80211_IFTYPE_AP, false);
++ if (IS_ERR(vif))
++ return (struct wireless_dev *)vif;
++
++ brcmf_cfg80211_arm_vif_event(cfg, vif);
++
++ err = brcmf_cfg80211_request_ap_if(ifp);
++ if (err) {
++ brcmf_cfg80211_arm_vif_event(cfg, NULL);
++ goto fail;
++ }
++
++ /* wait for firmware event */
++ err = brcmf_cfg80211_wait_vif_event_timeout(cfg, BRCMF_E_IF_ADD,
++ msecs_to_jiffies(1500));
++ brcmf_cfg80211_arm_vif_event(cfg, NULL);
++ if (!err) {
++ brcmf_err("timeout occurred\n");
++ err = -EIO;
++ goto fail;
++ }
++
++ /* interface created in firmware */
++ ifp = vif->ifp;
++ if (!ifp) {
++ brcmf_err("no if pointer provided\n");
++ err = -ENOENT;
++ goto fail;
++ }
++
++ strncpy(ifp->ndev->name, name, sizeof(ifp->ndev->name) - 1);
++ err = brcmf_net_attach(ifp, true);
++ if (err) {
++ brcmf_err("Registering netdevice failed\n");
++ goto fail;
++ }
++
++ return &ifp->vif->wdev;
++
++fail:
++ brcmf_free_vif(vif);
++ return ERR_PTR(err);
++}
++
++static bool brcmf_is_apmode(struct brcmf_cfg80211_vif *vif)
++{
++ enum nl80211_iftype iftype;
++
++ iftype = vif->wdev.iftype;
++ return iftype == NL80211_IFTYPE_AP || iftype == NL80211_IFTYPE_P2P_GO;
++}
++
++static bool brcmf_is_ibssmode(struct brcmf_cfg80211_vif *vif)
++{
++ return vif->wdev.iftype == NL80211_IFTYPE_ADHOC;
++}
++
++static struct wireless_dev *brcmf_cfg80211_add_iface(struct wiphy *wiphy,
++ const char *name,
++ enum nl80211_iftype type,
++ u32 *flags,
++ struct vif_params *params)
++{
++ struct wireless_dev *wdev;
++
++ brcmf_dbg(TRACE, "enter: %s type %d\n", name, type);
++ switch (type) {
++ case NL80211_IFTYPE_ADHOC:
++ case NL80211_IFTYPE_STATION:
++ case NL80211_IFTYPE_AP_VLAN:
++ case NL80211_IFTYPE_WDS:
++ case NL80211_IFTYPE_MONITOR:
++ case NL80211_IFTYPE_MESH_POINT:
++ return ERR_PTR(-EOPNOTSUPP);
++ case NL80211_IFTYPE_AP:
++ wdev = brcmf_ap_add_vif(wiphy, name, flags, params);
++ if (!IS_ERR(wdev))
++ brcmf_cfg80211_update_proto_addr_mode(wdev);
++ return wdev;
++ case NL80211_IFTYPE_P2P_CLIENT:
++ case NL80211_IFTYPE_P2P_GO:
++ case NL80211_IFTYPE_P2P_DEVICE:
++ wdev = brcmf_p2p_add_vif(wiphy, name, type, flags, params);
++ if (!IS_ERR(wdev))
++ brcmf_cfg80211_update_proto_addr_mode(wdev);
++ return wdev;
++ case NL80211_IFTYPE_UNSPECIFIED:
++ default:
++ return ERR_PTR(-EINVAL);
++ }
++}
++
++static void brcmf_scan_config_mpc(struct brcmf_if *ifp, int mpc)
++{
++ if (brcmf_feat_is_quirk_enabled(ifp, BRCMF_FEAT_QUIRK_NEED_MPC))
++ brcmf_set_mpc(ifp, mpc);
++}
++
++void brcmf_set_mpc(struct brcmf_if *ifp, int mpc)
++{
++ s32 err = 0;
++
++ if (check_vif_up(ifp->vif)) {
++ err = brcmf_fil_iovar_int_set(ifp, "mpc", mpc);
++ if (err) {
++ brcmf_err("fail to set mpc\n");
++ return;
++ }
++ brcmf_dbg(INFO, "MPC : %d\n", mpc);
++ }
++}
++
++s32 brcmf_notify_escan_complete(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_if *ifp, bool aborted,
++ bool fw_abort)
++{
++ struct brcmf_scan_params_le params_le;
++ struct cfg80211_scan_request *scan_request;
++ s32 err = 0;
++
++ brcmf_dbg(SCAN, "Enter\n");
++
++ /* clear scan request, because the FW abort can cause a second call */
++ /* to this functon and might cause a double cfg80211_scan_done */
++ scan_request = cfg->scan_request;
++ cfg->scan_request = NULL;
++
++ if (timer_pending(&cfg->escan_timeout))
++ del_timer_sync(&cfg->escan_timeout);
++
++ if (fw_abort) {
++ /* Do a scan abort to stop the driver's scan engine */
++ brcmf_dbg(SCAN, "ABORT scan in firmware\n");
++ memset(&params_le, 0, sizeof(params_le));
++ memset(params_le.bssid, 0xFF, ETH_ALEN);
++ params_le.bss_type = DOT11_BSSTYPE_ANY;
++ params_le.scan_type = 0;
++ params_le.channel_num = cpu_to_le32(1);
++ params_le.nprobes = cpu_to_le32(1);
++ params_le.active_time = cpu_to_le32(-1);
++ params_le.passive_time = cpu_to_le32(-1);
++ params_le.home_time = cpu_to_le32(-1);
++ /* Scan is aborted by setting channel_list[0] to -1 */
++ params_le.channel_list[0] = cpu_to_le16(-1);
++ /* E-Scan (or anyother type) can be aborted by SCAN */
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SCAN,
++ &params_le, sizeof(params_le));
++ if (err)
++ brcmf_err("Scan abort failed\n");
++ }
++
++ brcmf_scan_config_mpc(ifp, 1);
++
++ /*
++ * e-scan can be initiated by scheduled scan
++ * which takes precedence.
++ */
++ if (cfg->sched_escan) {
++ brcmf_dbg(SCAN, "scheduled scan completed\n");
++ cfg->sched_escan = false;
++ if (!aborted)
++ cfg80211_sched_scan_results(cfg_to_wiphy(cfg));
++ } else if (scan_request) {
++ brcmf_dbg(SCAN, "ESCAN Completed scan: %s\n",
++ aborted ? "Aborted" : "Done");
++ cfg80211_scan_done(scan_request, aborted);
++ }
++ if (!test_and_clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status))
++ brcmf_dbg(SCAN, "Scan complete, probably P2P scan\n");
++
++ return err;
++}
++
++static
++int brcmf_cfg80211_del_iface(struct wiphy *wiphy, struct wireless_dev *wdev)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
++ struct net_device *ndev = wdev->netdev;
++
++ /* vif event pending in firmware */
++ if (brcmf_cfg80211_vif_event_armed(cfg))
++ return -EBUSY;
++
++ if (ndev) {
++ if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status) &&
++ cfg->escan_info.ifp == netdev_priv(ndev))
++ brcmf_notify_escan_complete(cfg, netdev_priv(ndev),
++ true, true);
++
++ brcmf_fil_iovar_int_set(netdev_priv(ndev), "mpc", 1);
++ }
++
++ switch (wdev->iftype) {
++ case NL80211_IFTYPE_ADHOC:
++ case NL80211_IFTYPE_STATION:
++ case NL80211_IFTYPE_AP:
++ case NL80211_IFTYPE_AP_VLAN:
++ case NL80211_IFTYPE_WDS:
++ case NL80211_IFTYPE_MONITOR:
++ case NL80211_IFTYPE_MESH_POINT:
++ return -EOPNOTSUPP;
++ case NL80211_IFTYPE_P2P_CLIENT:
++ case NL80211_IFTYPE_P2P_GO:
++ case NL80211_IFTYPE_P2P_DEVICE:
++ return brcmf_p2p_del_vif(wiphy, wdev);
++ case NL80211_IFTYPE_UNSPECIFIED:
++ default:
++ return -EINVAL;
++ }
++ return -EOPNOTSUPP;
++}
++
++static s32
++brcmf_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
++ enum nl80211_iftype type, u32 *flags,
++ struct vif_params *params)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_vif *vif = ifp->vif;
++ s32 infra = 0;
++ s32 ap = 0;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter, ndev=%p, type=%d\n", ndev, type);
++
++ switch (type) {
++ case NL80211_IFTYPE_MONITOR:
++ case NL80211_IFTYPE_WDS:
++ brcmf_err("type (%d) : currently we do not support this type\n",
++ type);
++ return -EOPNOTSUPP;
++ case NL80211_IFTYPE_ADHOC:
++ infra = 0;
++ break;
++ case NL80211_IFTYPE_STATION:
++ /* Ignore change for p2p IF. Unclear why supplicant does this */
++ if ((vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) ||
++ (vif->wdev.iftype == NL80211_IFTYPE_P2P_GO)) {
++ brcmf_dbg(TRACE, "Ignoring cmd for p2p if\n");
++ /* WAR: It is unexpected to get a change of VIF for P2P
++ * IF, but it happens. The request can not be handled
++ * but returning EPERM causes a crash. Returning 0
++ * without setting ieee80211_ptr->iftype causes trace
++ * (WARN_ON) but it works with wpa_supplicant
++ */
++ return 0;
++ }
++ infra = 1;
++ break;
++ case NL80211_IFTYPE_AP:
++ case NL80211_IFTYPE_P2P_GO:
++ ap = 1;
++ break;
++ default:
++ err = -EINVAL;
++ goto done;
++ }
++
++ if (ap) {
++ if (type == NL80211_IFTYPE_P2P_GO) {
++ brcmf_dbg(INFO, "IF Type = P2P GO\n");
++ err = brcmf_p2p_ifchange(cfg, BRCMF_FIL_P2P_IF_GO);
++ }
++ if (!err) {
++ set_bit(BRCMF_VIF_STATUS_AP_CREATING, &vif->sme_state);
++ brcmf_dbg(INFO, "IF Type = AP\n");
++ }
++ } else {
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_INFRA, infra);
++ if (err) {
++ brcmf_err("WLC_SET_INFRA error (%d)\n", err);
++ err = -EAGAIN;
++ goto done;
++ }
++ brcmf_dbg(INFO, "IF Type = %s\n", brcmf_is_ibssmode(vif) ?
++ "Adhoc" : "Infra");
++ }
++ ndev->ieee80211_ptr->iftype = type;
++
++ brcmf_cfg80211_update_proto_addr_mode(&vif->wdev);
++
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++
++ return err;
++}
++
++static void brcmf_escan_prep(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_scan_params_le *params_le,
++ struct cfg80211_scan_request *request)
++{
++ u32 n_ssids;
++ u32 n_channels;
++ s32 i;
++ s32 offset;
++ u16 chanspec;
++ char *ptr;
++ struct brcmf_ssid_le ssid_le;
++
++ memset(params_le->bssid, 0xFF, ETH_ALEN);
++ params_le->bss_type = DOT11_BSSTYPE_ANY;
++ params_le->scan_type = 0;
++ params_le->channel_num = 0;
++ params_le->nprobes = cpu_to_le32(-1);
++ params_le->active_time = cpu_to_le32(-1);
++ params_le->passive_time = cpu_to_le32(-1);
++ params_le->home_time = cpu_to_le32(-1);
++ memset(&params_le->ssid_le, 0, sizeof(params_le->ssid_le));
++
++ /* if request is null exit so it will be all channel broadcast scan */
++ if (!request)
++ return;
++
++ n_ssids = request->n_ssids;
++ n_channels = request->n_channels;
++ /* Copy channel array if applicable */
++ brcmf_dbg(SCAN, "### List of channelspecs to scan ### %d\n",
++ n_channels);
++ if (n_channels > 0) {
++ for (i = 0; i < n_channels; i++) {
++ chanspec = channel_to_chanspec(&cfg->d11inf,
++ request->channels[i]);
++ brcmf_dbg(SCAN, "Chan : %d, Channel spec: %x\n",
++ request->channels[i]->hw_value, chanspec);
++ params_le->channel_list[i] = cpu_to_le16(chanspec);
++ }
++ } else {
++ brcmf_dbg(SCAN, "Scanning all channels\n");
++ }
++ /* Copy ssid array if applicable */
++ brcmf_dbg(SCAN, "### List of SSIDs to scan ### %d\n", n_ssids);
++ if (n_ssids > 0) {
++ offset = offsetof(struct brcmf_scan_params_le, channel_list) +
++ n_channels * sizeof(u16);
++ offset = roundup(offset, sizeof(u32));
++ ptr = (char *)params_le + offset;
++ for (i = 0; i < n_ssids; i++) {
++ memset(&ssid_le, 0, sizeof(ssid_le));
++ ssid_le.SSID_len =
++ cpu_to_le32(request->ssids[i].ssid_len);
++ memcpy(ssid_le.SSID, request->ssids[i].ssid,
++ request->ssids[i].ssid_len);
++ if (!ssid_le.SSID_len)
++ brcmf_dbg(SCAN, "%d: Broadcast scan\n", i);
++ else
++ brcmf_dbg(SCAN, "%d: scan for %s size =%d\n",
++ i, ssid_le.SSID, ssid_le.SSID_len);
++ memcpy(ptr, &ssid_le, sizeof(ssid_le));
++ ptr += sizeof(ssid_le);
++ }
++ } else {
++ brcmf_dbg(SCAN, "Broadcast scan %p\n", request->ssids);
++ if ((request->ssids) && request->ssids->ssid_len) {
++ brcmf_dbg(SCAN, "SSID %s len=%d\n",
++ params_le->ssid_le.SSID,
++ request->ssids->ssid_len);
++ params_le->ssid_le.SSID_len =
++ cpu_to_le32(request->ssids->ssid_len);
++ memcpy(&params_le->ssid_le.SSID, request->ssids->ssid,
++ request->ssids->ssid_len);
++ }
++ }
++ /* Adding mask to channel numbers */
++ params_le->channel_num =
++ cpu_to_le32((n_ssids << BRCMF_SCAN_PARAMS_NSSID_SHIFT) |
++ (n_channels & BRCMF_SCAN_PARAMS_COUNT_MASK));
++}
++
++static s32
++brcmf_run_escan(struct brcmf_cfg80211_info *cfg, struct brcmf_if *ifp,
++ struct cfg80211_scan_request *request, u16 action)
++{
++ s32 params_size = BRCMF_SCAN_PARAMS_FIXED_SIZE +
++ offsetof(struct brcmf_escan_params_le, params_le);
++ struct brcmf_escan_params_le *params;
++ s32 err = 0;
++
++ brcmf_dbg(SCAN, "E-SCAN START\n");
++
++ if (request != NULL) {
++ /* Allocate space for populating ssids in struct */
++ params_size += sizeof(u32) * ((request->n_channels + 1) / 2);
++
++ /* Allocate space for populating ssids in struct */
++ params_size += sizeof(struct brcmf_ssid) * request->n_ssids;
++ }
++
++ params = kzalloc(params_size, GFP_KERNEL);
++ if (!params) {
++ err = -ENOMEM;
++ goto exit;
++ }
++ BUG_ON(params_size + sizeof("escan") >= BRCMF_DCMD_MEDLEN);
++ brcmf_escan_prep(cfg, &params->params_le, request);
++ params->version = cpu_to_le32(BRCMF_ESCAN_REQ_VERSION);
++ params->action = cpu_to_le16(action);
++ params->sync_id = cpu_to_le16(0x1234);
++
++ err = brcmf_fil_iovar_data_set(ifp, "escan", params, params_size);
++ if (err) {
++ if (err == -EBUSY)
++ brcmf_dbg(INFO, "system busy : escan canceled\n");
++ else
++ brcmf_err("error (%d)\n", err);
++ }
++
++ kfree(params);
++exit:
++ return err;
++}
++
++static s32
++brcmf_do_escan(struct brcmf_cfg80211_info *cfg, struct wiphy *wiphy,
++ struct brcmf_if *ifp, struct cfg80211_scan_request *request)
++{
++ s32 err;
++ u32 passive_scan;
++ struct brcmf_scan_results *results;
++ struct escan_info *escan = &cfg->escan_info;
++
++ brcmf_dbg(SCAN, "Enter\n");
++ escan->ifp = ifp;
++ escan->wiphy = wiphy;
++ escan->escan_state = WL_ESCAN_STATE_SCANNING;
++ passive_scan = cfg->active_scan ? 0 : 1;
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PASSIVE_SCAN,
++ passive_scan);
++ if (err) {
++ brcmf_err("error (%d)\n", err);
++ return err;
++ }
++ brcmf_scan_config_mpc(ifp, 0);
++ results = (struct brcmf_scan_results *)cfg->escan_info.escan_buf;
++ results->version = 0;
++ results->count = 0;
++ results->buflen = WL_ESCAN_RESULTS_FIXED_SIZE;
++
++ err = escan->run(cfg, ifp, request, WL_ESCAN_ACTION_START);
++ if (err)
++ brcmf_scan_config_mpc(ifp, 1);
++ return err;
++}
++
++static s32
++brcmf_cfg80211_escan(struct wiphy *wiphy, struct brcmf_cfg80211_vif *vif,
++ struct cfg80211_scan_request *request,
++ struct cfg80211_ssid *this_ssid)
++{
++ struct brcmf_if *ifp = vif->ifp;
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct cfg80211_ssid *ssids;
++ struct brcmf_cfg80211_scan_req *sr = &cfg->scan_req_int;
++ u32 passive_scan;
++ bool escan_req;
++ bool spec_scan;
++ s32 err;
++ u32 SSID_len;
++
++ brcmf_dbg(SCAN, "START ESCAN\n");
++
++ if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
++ brcmf_err("Scanning already: status (%lu)\n", cfg->scan_status);
++ return -EAGAIN;
++ }
++ if (test_bit(BRCMF_SCAN_STATUS_ABORT, &cfg->scan_status)) {
++ brcmf_err("Scanning being aborted: status (%lu)\n",
++ cfg->scan_status);
++ return -EAGAIN;
++ }
++ if (test_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status)) {
++ brcmf_err("Scanning suppressed: status (%lu)\n",
++ cfg->scan_status);
++ return -EAGAIN;
++ }
++ if (test_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state)) {
++ brcmf_err("Connecting: status (%lu)\n", ifp->vif->sme_state);
++ return -EAGAIN;
++ }
++
++ /* If scan req comes for p2p0, send it over primary I/F */
++ if (vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif)
++ vif = cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif;
++
++ escan_req = false;
++ if (request) {
++ /* scan bss */
++ ssids = request->ssids;
++ escan_req = true;
++ } else {
++ /* scan in ibss */
++ /* we don't do escan in ibss */
++ ssids = this_ssid;
++ }
++
++ cfg->scan_request = request;
++ set_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
++ if (escan_req) {
++ cfg->escan_info.run = brcmf_run_escan;
++ err = brcmf_p2p_scan_prep(wiphy, request, vif);
++ if (err)
++ goto scan_out;
++
++ err = brcmf_do_escan(cfg, wiphy, vif->ifp, request);
++ if (err)
++ goto scan_out;
++ } else {
++ brcmf_dbg(SCAN, "ssid \"%s\", ssid_len (%d)\n",
++ ssids->ssid, ssids->ssid_len);
++ memset(&sr->ssid_le, 0, sizeof(sr->ssid_le));
++ SSID_len = min_t(u8, sizeof(sr->ssid_le.SSID), ssids->ssid_len);
++ sr->ssid_le.SSID_len = cpu_to_le32(0);
++ spec_scan = false;
++ if (SSID_len) {
++ memcpy(sr->ssid_le.SSID, ssids->ssid, SSID_len);
++ sr->ssid_le.SSID_len = cpu_to_le32(SSID_len);
++ spec_scan = true;
++ } else
++ brcmf_dbg(SCAN, "Broadcast scan\n");
++
++ passive_scan = cfg->active_scan ? 0 : 1;
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PASSIVE_SCAN,
++ passive_scan);
++ if (err) {
++ brcmf_err("WLC_SET_PASSIVE_SCAN error (%d)\n", err);
++ goto scan_out;
++ }
++ brcmf_scan_config_mpc(ifp, 0);
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SCAN,
++ &sr->ssid_le, sizeof(sr->ssid_le));
++ if (err) {
++ if (err == -EBUSY)
++ brcmf_dbg(INFO, "BUSY: scan for \"%s\" canceled\n",
++ sr->ssid_le.SSID);
++ else
++ brcmf_err("WLC_SCAN error (%d)\n", err);
++
++ brcmf_scan_config_mpc(ifp, 1);
++ goto scan_out;
++ }
++ }
++
++ /* Arm scan timeout timer */
++ mod_timer(&cfg->escan_timeout, jiffies +
++ WL_ESCAN_TIMER_INTERVAL_MS * HZ / 1000);
++
++ return 0;
++
++scan_out:
++ clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
++ cfg->scan_request = NULL;
++ return err;
++}
++
++static s32
++brcmf_cfg80211_scan(struct wiphy *wiphy, struct cfg80211_scan_request *request)
++{
++ struct brcmf_cfg80211_vif *vif;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ vif = container_of(request->wdev, struct brcmf_cfg80211_vif, wdev);
++ if (!check_vif_up(vif))
++ return -EIO;
++
++ err = brcmf_cfg80211_escan(wiphy, vif, request, NULL);
++
++ if (err)
++ brcmf_err("scan error (%d)\n", err);
++
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32 brcmf_set_rts(struct net_device *ndev, u32 rts_threshold)
++{
++ s32 err = 0;
++
++ err = brcmf_fil_iovar_int_set(netdev_priv(ndev), "rtsthresh",
++ rts_threshold);
++ if (err)
++ brcmf_err("Error (%d)\n", err);
++
++ return err;
++}
++
++static s32 brcmf_set_frag(struct net_device *ndev, u32 frag_threshold)
++{
++ s32 err = 0;
++
++ err = brcmf_fil_iovar_int_set(netdev_priv(ndev), "fragthresh",
++ frag_threshold);
++ if (err)
++ brcmf_err("Error (%d)\n", err);
++
++ return err;
++}
++
++static s32 brcmf_set_retry(struct net_device *ndev, u32 retry, bool l)
++{
++ s32 err = 0;
++ u32 cmd = (l ? BRCMF_C_SET_LRL : BRCMF_C_SET_SRL);
++
++ err = brcmf_fil_cmd_int_set(netdev_priv(ndev), cmd, retry);
++ if (err) {
++ brcmf_err("cmd (%d) , error (%d)\n", cmd, err);
++ return err;
++ }
++ return err;
++}
++
++static s32 brcmf_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct net_device *ndev = cfg_to_ndev(cfg);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
++ (cfg->conf->rts_threshold != wiphy->rts_threshold)) {
++ cfg->conf->rts_threshold = wiphy->rts_threshold;
++ err = brcmf_set_rts(ndev, cfg->conf->rts_threshold);
++ if (!err)
++ goto done;
++ }
++ if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
++ (cfg->conf->frag_threshold != wiphy->frag_threshold)) {
++ cfg->conf->frag_threshold = wiphy->frag_threshold;
++ err = brcmf_set_frag(ndev, cfg->conf->frag_threshold);
++ if (!err)
++ goto done;
++ }
++ if (changed & WIPHY_PARAM_RETRY_LONG
++ && (cfg->conf->retry_long != wiphy->retry_long)) {
++ cfg->conf->retry_long = wiphy->retry_long;
++ err = brcmf_set_retry(ndev, cfg->conf->retry_long, true);
++ if (!err)
++ goto done;
++ }
++ if (changed & WIPHY_PARAM_RETRY_SHORT
++ && (cfg->conf->retry_short != wiphy->retry_short)) {
++ cfg->conf->retry_short = wiphy->retry_short;
++ err = brcmf_set_retry(ndev, cfg->conf->retry_short, false);
++ if (!err)
++ goto done;
++ }
++
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static void brcmf_init_prof(struct brcmf_cfg80211_profile *prof)
++{
++ memset(prof, 0, sizeof(*prof));
++}
++
++static u16 brcmf_map_fw_linkdown_reason(const struct brcmf_event_msg *e)
++{
++ u16 reason;
++
++ switch (e->event_code) {
++ case BRCMF_E_DEAUTH:
++ case BRCMF_E_DEAUTH_IND:
++ case BRCMF_E_DISASSOC_IND:
++ reason = e->reason;
++ break;
++ case BRCMF_E_LINK:
++ default:
++ reason = 0;
++ break;
++ }
++ return reason;
++}
++
++static void brcmf_link_down(struct brcmf_cfg80211_vif *vif, u16 reason)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(vif->wdev.wiphy);
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (test_bit(BRCMF_VIF_STATUS_CONNECTED, &vif->sme_state)) {
++ brcmf_dbg(INFO, "Call WLC_DISASSOC to stop excess roaming\n ");
++ err = brcmf_fil_cmd_data_set(vif->ifp,
++ BRCMF_C_DISASSOC, NULL, 0);
++ if (err) {
++ brcmf_err("WLC_DISASSOC failed (%d)\n", err);
++ }
++ clear_bit(BRCMF_VIF_STATUS_CONNECTED, &vif->sme_state);
++ cfg80211_disconnected(vif->wdev.netdev, reason, NULL, 0,
++ GFP_KERNEL);
++
++ }
++ clear_bit(BRCMF_VIF_STATUS_CONNECTING, &vif->sme_state);
++ clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
++ brcmf_btcoex_set_mode(vif, BRCMF_BTCOEX_ENABLED, 0);
++ brcmf_dbg(TRACE, "Exit\n");
++}
++
++static s32
++brcmf_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_ibss_params *params)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct brcmf_join_params join_params;
++ size_t join_params_size = 0;
++ s32 err = 0;
++ s32 wsec = 0;
++ s32 bcnprd;
++ u16 chanspec;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ if (params->ssid)
++ brcmf_dbg(CONN, "SSID: %s\n", params->ssid);
++ else {
++ brcmf_dbg(CONN, "SSID: NULL, Not supported\n");
++ return -EOPNOTSUPP;
++ }
++
++ set_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
++
++ if (params->bssid)
++ brcmf_dbg(CONN, "BSSID: %pM\n", params->bssid);
++ else
++ brcmf_dbg(CONN, "No BSSID specified\n");
++
++ if (params->chandef.chan)
++ brcmf_dbg(CONN, "channel: %d\n",
++ params->chandef.chan->center_freq);
++ else
++ brcmf_dbg(CONN, "no channel specified\n");
++
++ if (params->channel_fixed)
++ brcmf_dbg(CONN, "fixed channel required\n");
++ else
++ brcmf_dbg(CONN, "no fixed channel required\n");
++
++ if (params->ie && params->ie_len)
++ brcmf_dbg(CONN, "ie len: %d\n", params->ie_len);
++ else
++ brcmf_dbg(CONN, "no ie specified\n");
++
++ if (params->beacon_interval)
++ brcmf_dbg(CONN, "beacon interval: %d\n",
++ params->beacon_interval);
++ else
++ brcmf_dbg(CONN, "no beacon interval specified\n");
++
++ if (params->basic_rates)
++ brcmf_dbg(CONN, "basic rates: %08X\n", params->basic_rates);
++ else
++ brcmf_dbg(CONN, "no basic rates specified\n");
++
++ if (params->privacy)
++ brcmf_dbg(CONN, "privacy required\n");
++ else
++ brcmf_dbg(CONN, "no privacy required\n");
++
++ /* Configure Privacy for starter */
++ if (params->privacy)
++ wsec |= WEP_ENABLED;
++
++ err = brcmf_fil_iovar_int_set(ifp, "wsec", wsec);
++ if (err) {
++ brcmf_err("wsec failed (%d)\n", err);
++ goto done;
++ }
++
++ /* Configure Beacon Interval for starter */
++ if (params->beacon_interval)
++ bcnprd = params->beacon_interval;
++ else
++ bcnprd = 100;
++
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_BCNPRD, bcnprd);
++ if (err) {
++ brcmf_err("WLC_SET_BCNPRD failed (%d)\n", err);
++ goto done;
++ }
++
++ /* Configure required join parameter */
++ memset(&join_params, 0, sizeof(struct brcmf_join_params));
++
++ /* SSID */
++ profile->ssid.SSID_len = min_t(u32, params->ssid_len, 32);
++ memcpy(profile->ssid.SSID, params->ssid, profile->ssid.SSID_len);
++ memcpy(join_params.ssid_le.SSID, params->ssid, profile->ssid.SSID_len);
++ join_params.ssid_le.SSID_len = cpu_to_le32(profile->ssid.SSID_len);
++ join_params_size = sizeof(join_params.ssid_le);
++
++ /* BSSID */
++ if (params->bssid) {
++ memcpy(join_params.params_le.bssid, params->bssid, ETH_ALEN);
++ join_params_size = sizeof(join_params.ssid_le) +
++ BRCMF_ASSOC_PARAMS_FIXED_SIZE;
++ memcpy(profile->bssid, params->bssid, ETH_ALEN);
++ } else {
++ memset(join_params.params_le.bssid, 0xFF, ETH_ALEN);
++ memset(profile->bssid, 0, ETH_ALEN);
++ }
++
++ /* Channel */
++ if (params->chandef.chan) {
++ u32 target_channel;
++
++ cfg->channel =
++ ieee80211_frequency_to_channel(
++ params->chandef.chan->center_freq);
++ if (params->channel_fixed) {
++ /* adding chanspec */
++ chanspec = chandef_to_chanspec(&cfg->d11inf,
++ &params->chandef);
++ join_params.params_le.chanspec_list[0] =
++ cpu_to_le16(chanspec);
++ join_params.params_le.chanspec_num = cpu_to_le32(1);
++ join_params_size += sizeof(join_params.params_le);
++ }
++
++ /* set channel for starter */
++ target_channel = cfg->channel;
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_CHANNEL,
++ target_channel);
++ if (err) {
++ brcmf_err("WLC_SET_CHANNEL failed (%d)\n", err);
++ goto done;
++ }
++ } else
++ cfg->channel = 0;
++
++ cfg->ibss_starter = false;
++
++
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
++ &join_params, join_params_size);
++ if (err) {
++ brcmf_err("WLC_SET_SSID failed (%d)\n", err);
++ goto done;
++ }
++
++done:
++ if (err)
++ clear_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ brcmf_link_down(ifp->vif, WLAN_REASON_DEAUTH_LEAVING);
++
++ brcmf_dbg(TRACE, "Exit\n");
++
++ return 0;
++}
++
++static s32 brcmf_set_wpa_version(struct net_device *ndev,
++ struct cfg80211_connect_params *sme)
++{
++ struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
++ struct brcmf_cfg80211_security *sec;
++ s32 val = 0;
++ s32 err = 0;
++
++ if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_1)
++ val = WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED;
++ else if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_2)
++ val = WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED;
++ else
++ val = WPA_AUTH_DISABLED;
++ brcmf_dbg(CONN, "setting wpa_auth to 0x%0x\n", val);
++ err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "wpa_auth", val);
++ if (err) {
++ brcmf_err("set wpa_auth failed (%d)\n", err);
++ return err;
++ }
++ sec = &profile->sec;
++ sec->wpa_versions = sme->crypto.wpa_versions;
++ return err;
++}
++
++static s32 brcmf_set_auth_type(struct net_device *ndev,
++ struct cfg80211_connect_params *sme)
++{
++ struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
++ struct brcmf_cfg80211_security *sec;
++ s32 val = 0;
++ s32 err = 0;
++
++ switch (sme->auth_type) {
++ case NL80211_AUTHTYPE_OPEN_SYSTEM:
++ val = 0;
++ brcmf_dbg(CONN, "open system\n");
++ break;
++ case NL80211_AUTHTYPE_SHARED_KEY:
++ val = 1;
++ brcmf_dbg(CONN, "shared key\n");
++ break;
++ case NL80211_AUTHTYPE_AUTOMATIC:
++ val = 2;
++ brcmf_dbg(CONN, "automatic\n");
++ break;
++ case NL80211_AUTHTYPE_NETWORK_EAP:
++ brcmf_dbg(CONN, "network eap\n");
++ default:
++ val = 2;
++ brcmf_err("invalid auth type (%d)\n", sme->auth_type);
++ break;
++ }
++
++ err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "auth", val);
++ if (err) {
++ brcmf_err("set auth failed (%d)\n", err);
++ return err;
++ }
++ sec = &profile->sec;
++ sec->auth_type = sme->auth_type;
++ return err;
++}
++
++static s32
++brcmf_set_wsec_mode(struct net_device *ndev,
++ struct cfg80211_connect_params *sme, bool mfp)
++{
++ struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
++ struct brcmf_cfg80211_security *sec;
++ s32 pval = 0;
++ s32 gval = 0;
++ s32 wsec;
++ s32 err = 0;
++
++ if (sme->crypto.n_ciphers_pairwise) {
++ switch (sme->crypto.ciphers_pairwise[0]) {
++ case WLAN_CIPHER_SUITE_WEP40:
++ case WLAN_CIPHER_SUITE_WEP104:
++ pval = WEP_ENABLED;
++ break;
++ case WLAN_CIPHER_SUITE_TKIP:
++ pval = TKIP_ENABLED;
++ break;
++ case WLAN_CIPHER_SUITE_CCMP:
++ pval = AES_ENABLED;
++ break;
++ case WLAN_CIPHER_SUITE_AES_CMAC:
++ pval = AES_ENABLED;
++ break;
++ default:
++ brcmf_err("invalid cipher pairwise (%d)\n",
++ sme->crypto.ciphers_pairwise[0]);
++ return -EINVAL;
++ }
++ }
++ if (sme->crypto.cipher_group) {
++ switch (sme->crypto.cipher_group) {
++ case WLAN_CIPHER_SUITE_WEP40:
++ case WLAN_CIPHER_SUITE_WEP104:
++ gval = WEP_ENABLED;
++ break;
++ case WLAN_CIPHER_SUITE_TKIP:
++ gval = TKIP_ENABLED;
++ break;
++ case WLAN_CIPHER_SUITE_CCMP:
++ gval = AES_ENABLED;
++ break;
++ case WLAN_CIPHER_SUITE_AES_CMAC:
++ gval = AES_ENABLED;
++ break;
++ default:
++ brcmf_err("invalid cipher group (%d)\n",
++ sme->crypto.cipher_group);
++ return -EINVAL;
++ }
++ }
++
++ brcmf_dbg(CONN, "pval (%d) gval (%d)\n", pval, gval);
++ /* In case of privacy, but no security and WPS then simulate */
++ /* setting AES. WPS-2.0 allows no security */
++ if (brcmf_find_wpsie(sme->ie, sme->ie_len) && !pval && !gval &&
++ sme->privacy)
++ pval = AES_ENABLED;
++
++ if (mfp)
++ wsec = pval | gval | MFP_CAPABLE;
++ else
++ wsec = pval | gval;
++ err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "wsec", wsec);
++ if (err) {
++ brcmf_err("error (%d)\n", err);
++ return err;
++ }
++
++ sec = &profile->sec;
++ sec->cipher_pairwise = sme->crypto.ciphers_pairwise[0];
++ sec->cipher_group = sme->crypto.cipher_group;
++
++ return err;
++}
++
++static s32
++brcmf_set_key_mgmt(struct net_device *ndev, struct cfg80211_connect_params *sme)
++{
++ struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
++ struct brcmf_cfg80211_security *sec;
++ s32 val = 0;
++ s32 err = 0;
++
++ if (sme->crypto.n_akm_suites) {
++ err = brcmf_fil_bsscfg_int_get(netdev_priv(ndev),
++ "wpa_auth", &val);
++ if (err) {
++ brcmf_err("could not get wpa_auth (%d)\n", err);
++ return err;
++ }
++ if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED)) {
++ switch (sme->crypto.akm_suites[0]) {
++ case WLAN_AKM_SUITE_8021X:
++ val = WPA_AUTH_UNSPECIFIED;
++ break;
++ case WLAN_AKM_SUITE_PSK:
++ val = WPA_AUTH_PSK;
++ break;
++ default:
++ brcmf_err("invalid cipher group (%d)\n",
++ sme->crypto.cipher_group);
++ return -EINVAL;
++ }
++ } else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED)) {
++ switch (sme->crypto.akm_suites[0]) {
++ case WLAN_AKM_SUITE_8021X:
++ val = WPA2_AUTH_UNSPECIFIED;
++ break;
++ case WLAN_AKM_SUITE_PSK:
++ val = WPA2_AUTH_PSK;
++ break;
++ default:
++ brcmf_err("invalid cipher group (%d)\n",
++ sme->crypto.cipher_group);
++ return -EINVAL;
++ }
++ }
++
++ brcmf_dbg(CONN, "setting wpa_auth to %d\n", val);
++ err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev),
++ "wpa_auth", val);
++ if (err) {
++ brcmf_err("could not set wpa_auth (%d)\n", err);
++ return err;
++ }
++ }
++ sec = &profile->sec;
++ sec->wpa_auth = sme->crypto.akm_suites[0];
++
++ return err;
++}
++
++static s32
++brcmf_set_sharedkey(struct net_device *ndev,
++ struct cfg80211_connect_params *sme)
++{
++ struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
++ struct brcmf_cfg80211_security *sec;
++ struct brcmf_wsec_key key;
++ s32 val;
++ s32 err = 0;
++
++ brcmf_dbg(CONN, "key len (%d)\n", sme->key_len);
++
++ if (sme->key_len == 0)
++ return 0;
++
++ sec = &profile->sec;
++ brcmf_dbg(CONN, "wpa_versions 0x%x cipher_pairwise 0x%x\n",
++ sec->wpa_versions, sec->cipher_pairwise);
++
++ if (sec->wpa_versions & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2))
++ return 0;
++
++ if (!(sec->cipher_pairwise &
++ (WLAN_CIPHER_SUITE_WEP40 | WLAN_CIPHER_SUITE_WEP104)))
++ return 0;
++
++ memset(&key, 0, sizeof(key));
++ key.len = (u32) sme->key_len;
++ key.index = (u32) sme->key_idx;
++ if (key.len > sizeof(key.data)) {
++ brcmf_err("Too long key length (%u)\n", key.len);
++ return -EINVAL;
++ }
++ memcpy(key.data, sme->key, key.len);
++ key.flags = BRCMF_PRIMARY_KEY;
++ switch (sec->cipher_pairwise) {
++ case WLAN_CIPHER_SUITE_WEP40:
++ key.algo = CRYPTO_ALGO_WEP1;
++ break;
++ case WLAN_CIPHER_SUITE_WEP104:
++ key.algo = CRYPTO_ALGO_WEP128;
++ break;
++ default:
++ brcmf_err("Invalid algorithm (%d)\n",
++ sme->crypto.ciphers_pairwise[0]);
++ return -EINVAL;
++ }
++ /* Set the new key/index */
++ brcmf_dbg(CONN, "key length (%d) key index (%d) algo (%d)\n",
++ key.len, key.index, key.algo);
++ brcmf_dbg(CONN, "key \"%s\"\n", key.data);
++ err = send_key_to_dongle(netdev_priv(ndev), &key);
++ if (err)
++ return err;
++
++ if (sec->auth_type == NL80211_AUTHTYPE_SHARED_KEY) {
++ brcmf_dbg(CONN, "set auth_type to shared key\n");
++ val = WL_AUTH_SHARED_KEY; /* shared key */
++ err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "auth", val);
++ if (err)
++ brcmf_err("set auth failed (%d)\n", err);
++ }
++ return err;
++}
++
++static
++enum nl80211_auth_type brcmf_war_auth_type(struct brcmf_if *ifp,
++ enum nl80211_auth_type type)
++{
++ if (type == NL80211_AUTHTYPE_AUTOMATIC &&
++ brcmf_feat_is_quirk_enabled(ifp, BRCMF_FEAT_QUIRK_AUTO_AUTH)) {
++ brcmf_dbg(CONN, "WAR: use OPEN instead of AUTO\n");
++ type = NL80211_AUTHTYPE_OPEN_SYSTEM;
++ }
++ return type;
++}
++
++static s32
++brcmf_cfg80211_connect(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_connect_params *sme)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct ieee80211_channel *chan = sme->channel;
++ struct brcmf_join_params join_params;
++ size_t join_params_size;
++ const struct brcmf_tlv *rsn_ie;
++ const struct brcmf_vs_tlv *wpa_ie;
++ const void *ie;
++ u32 ie_len;
++ struct brcmf_ext_join_params_le *ext_join_params;
++ u16 chanspec;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ if (!sme->ssid) {
++ brcmf_err("Invalid ssid\n");
++ return -EOPNOTSUPP;
++ }
++
++ if (ifp->vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif) {
++ /* A normal (non P2P) connection request setup. */
++ ie = NULL;
++ ie_len = 0;
++ /* find the WPA_IE */
++ wpa_ie = brcmf_find_wpaie((u8 *)sme->ie, sme->ie_len);
++ if (wpa_ie) {
++ ie = wpa_ie;
++ ie_len = wpa_ie->len + TLV_HDR_LEN;
++ } else {
++ /* find the RSN_IE */
++ rsn_ie = brcmf_parse_tlvs((const u8 *)sme->ie,
++ sme->ie_len,
++ WLAN_EID_RSN);
++ if (rsn_ie) {
++ ie = rsn_ie;
++ ie_len = rsn_ie->len + TLV_HDR_LEN;
++ }
++ }
++ brcmf_fil_iovar_data_set(ifp, "wpaie", ie, ie_len);
++ }
++
++ err = brcmf_vif_set_mgmt_ie(ifp->vif, BRCMF_VNDR_IE_ASSOCREQ_FLAG,
++ sme->ie, sme->ie_len);
++ if (err)
++ brcmf_err("Set Assoc REQ IE Failed\n");
++ else
++ brcmf_dbg(TRACE, "Applied Vndr IEs for Assoc request\n");
++
++ set_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
++
++ if (chan) {
++ cfg->channel =
++ ieee80211_frequency_to_channel(chan->center_freq);
++ chanspec = channel_to_chanspec(&cfg->d11inf, chan);
++ brcmf_dbg(CONN, "channel=%d, center_req=%d, chanspec=0x%04x\n",
++ cfg->channel, chan->center_freq, chanspec);
++ } else {
++ cfg->channel = 0;
++ chanspec = 0;
++ }
++
++ brcmf_dbg(INFO, "ie (%p), ie_len (%zd)\n", sme->ie, sme->ie_len);
++
++ err = brcmf_set_wpa_version(ndev, sme);
++ if (err) {
++ brcmf_err("wl_set_wpa_version failed (%d)\n", err);
++ goto done;
++ }
++
++ sme->auth_type = brcmf_war_auth_type(ifp, sme->auth_type);
++ err = brcmf_set_auth_type(ndev, sme);
++ if (err) {
++ brcmf_err("wl_set_auth_type failed (%d)\n", err);
++ goto done;
++ }
++
++ err = brcmf_set_wsec_mode(ndev, sme, sme->mfp == NL80211_MFP_REQUIRED);
++ if (err) {
++ brcmf_err("wl_set_set_cipher failed (%d)\n", err);
++ goto done;
++ }
++
++ err = brcmf_set_key_mgmt(ndev, sme);
++ if (err) {
++ brcmf_err("wl_set_key_mgmt failed (%d)\n", err);
++ goto done;
++ }
++
++ err = brcmf_set_sharedkey(ndev, sme);
++ if (err) {
++ brcmf_err("brcmf_set_sharedkey failed (%d)\n", err);
++ goto done;
++ }
++
++ profile->ssid.SSID_len = min_t(u32, (u32)sizeof(profile->ssid.SSID),
++ (u32)sme->ssid_len);
++ memcpy(&profile->ssid.SSID, sme->ssid, profile->ssid.SSID_len);
++ if (profile->ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
++ profile->ssid.SSID[profile->ssid.SSID_len] = 0;
++ brcmf_dbg(CONN, "SSID \"%s\", len (%d)\n", profile->ssid.SSID,
++ profile->ssid.SSID_len);
++ }
++
++ /* Join with specific BSSID and cached SSID
++ * If SSID is zero join based on BSSID only
++ */
++ join_params_size = offsetof(struct brcmf_ext_join_params_le, assoc_le) +
++ offsetof(struct brcmf_assoc_params_le, chanspec_list);
++ if (cfg->channel)
++ join_params_size += sizeof(u16);
++ ext_join_params = kzalloc(join_params_size, GFP_KERNEL);
++ if (ext_join_params == NULL) {
++ err = -ENOMEM;
++ goto done;
++ }
++ ext_join_params->ssid_le.SSID_len = cpu_to_le32(profile->ssid.SSID_len);
++ memcpy(&ext_join_params->ssid_le.SSID, sme->ssid,
++ profile->ssid.SSID_len);
++
++ /* Set up join scan parameters */
++ ext_join_params->scan_le.scan_type = -1;
++ ext_join_params->scan_le.home_time = cpu_to_le32(-1);
++
++ if (sme->bssid)
++ memcpy(&ext_join_params->assoc_le.bssid, sme->bssid, ETH_ALEN);
++ else
++ memset(&ext_join_params->assoc_le.bssid, 0xFF, ETH_ALEN);
++
++ if (cfg->channel) {
++ ext_join_params->assoc_le.chanspec_num = cpu_to_le32(1);
++
++ ext_join_params->assoc_le.chanspec_list[0] =
++ cpu_to_le16(chanspec);
++ /* Increase dwell time to receive probe response or detect
++ * beacon from target AP at a noisy air only during connect
++ * command.
++ */
++ ext_join_params->scan_le.active_time =
++ cpu_to_le32(BRCMF_SCAN_JOIN_ACTIVE_DWELL_TIME_MS);
++ ext_join_params->scan_le.passive_time =
++ cpu_to_le32(BRCMF_SCAN_JOIN_PASSIVE_DWELL_TIME_MS);
++ /* To sync with presence period of VSDB GO send probe request
++ * more frequently. Probe request will be stopped when it gets
++ * probe response from target AP/GO.
++ */
++ ext_join_params->scan_le.nprobes =
++ cpu_to_le32(BRCMF_SCAN_JOIN_ACTIVE_DWELL_TIME_MS /
++ BRCMF_SCAN_JOIN_PROBE_INTERVAL_MS);
++ } else {
++ ext_join_params->scan_le.active_time = cpu_to_le32(-1);
++ ext_join_params->scan_le.passive_time = cpu_to_le32(-1);
++ ext_join_params->scan_le.nprobes = cpu_to_le32(-1);
++ }
++
++ err = brcmf_fil_bsscfg_data_set(ifp, "join", ext_join_params,
++ join_params_size);
++ kfree(ext_join_params);
++ if (!err)
++ /* This is it. join command worked, we are done */
++ goto done;
++
++ /* join command failed, fallback to set ssid */
++ memset(&join_params, 0, sizeof(join_params));
++ join_params_size = sizeof(join_params.ssid_le);
++
++ memcpy(&join_params.ssid_le.SSID, sme->ssid, profile->ssid.SSID_len);
++ join_params.ssid_le.SSID_len = cpu_to_le32(profile->ssid.SSID_len);
++
++ if (sme->bssid)
++ memcpy(join_params.params_le.bssid, sme->bssid, ETH_ALEN);
++ else
++ memset(join_params.params_le.bssid, 0xFF, ETH_ALEN);
++
++ if (cfg->channel) {
++ join_params.params_le.chanspec_list[0] = cpu_to_le16(chanspec);
++ join_params.params_le.chanspec_num = cpu_to_le32(1);
++ join_params_size += sizeof(join_params.params_le);
++ }
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
++ &join_params, join_params_size);
++ if (err)
++ brcmf_err("BRCMF_C_SET_SSID failed (%d)\n", err);
++
++done:
++ if (err)
++ clear_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *ndev,
++ u16 reason_code)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct brcmf_scb_val_le scbval;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter. Reason code = %d\n", reason_code);
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ clear_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state);
++ clear_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
++ cfg80211_disconnected(ndev, reason_code, NULL, 0, GFP_KERNEL);
++
++ memcpy(&scbval.ea, &profile->bssid, ETH_ALEN);
++ scbval.val = cpu_to_le32(reason_code);
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_DISASSOC,
++ &scbval, sizeof(scbval));
++ if (err)
++ brcmf_err("error (%d)\n", err);
++
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_set_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
++ enum nl80211_tx_power_setting type, s32 mbm)
++{
++
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct net_device *ndev = cfg_to_ndev(cfg);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ u16 txpwrmw;
++ s32 err = 0;
++ s32 disable = 0;
++ s32 dbm = MBM_TO_DBM(mbm);
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ switch (type) {
++ case NL80211_TX_POWER_AUTOMATIC:
++ break;
++ case NL80211_TX_POWER_LIMITED:
++ case NL80211_TX_POWER_FIXED:
++ if (dbm < 0) {
++ brcmf_err("TX_POWER_FIXED - dbm is negative\n");
++ err = -EINVAL;
++ goto done;
++ }
++ break;
++ }
++ /* Make sure radio is off or on as far as software is concerned */
++ disable = WL_RADIO_SW_DISABLE << 16;
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_RADIO, disable);
++ if (err)
++ brcmf_err("WLC_SET_RADIO error (%d)\n", err);
++
++ if (dbm > 0xffff)
++ txpwrmw = 0xffff;
++ else
++ txpwrmw = (u16) dbm;
++ err = brcmf_fil_iovar_int_set(ifp, "qtxpower",
++ (s32)brcmf_mw_to_qdbm(txpwrmw));
++ if (err)
++ brcmf_err("qtxpower error (%d)\n", err);
++ cfg->conf->tx_power = dbm;
++
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32 brcmf_cfg80211_get_tx_power(struct wiphy *wiphy,
++ struct wireless_dev *wdev,
++ s32 *dbm)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
++ s32 txpwrdbm;
++ u8 result;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ err = brcmf_fil_iovar_int_get(ifp, "qtxpower", &txpwrdbm);
++ if (err) {
++ brcmf_err("error (%d)\n", err);
++ goto done;
++ }
++
++ result = (u8) (txpwrdbm & ~WL_TXPWR_OVERRIDE);
++ *dbm = (s32) brcmf_qdbm_to_mw(result);
++
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *ndev,
++ u8 key_idx, bool unicast, bool multicast)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ u32 index;
++ u32 wsec;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ brcmf_dbg(CONN, "key index (%d)\n", key_idx);
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ err = brcmf_fil_bsscfg_int_get(ifp, "wsec", &wsec);
++ if (err) {
++ brcmf_err("WLC_GET_WSEC error (%d)\n", err);
++ goto done;
++ }
++
++ if (wsec & WEP_ENABLED) {
++ /* Just select a new current key */
++ index = key_idx;
++ err = brcmf_fil_cmd_int_set(ifp,
++ BRCMF_C_SET_KEY_PRIMARY, index);
++ if (err)
++ brcmf_err("error (%d)\n", err);
++ }
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_add_keyext(struct wiphy *wiphy, struct net_device *ndev,
++ u8 key_idx, const u8 *mac_addr, struct key_params *params)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_wsec_key key;
++ s32 err = 0;
++ u8 keybuf[8];
++
++ memset(&key, 0, sizeof(key));
++ key.index = (u32) key_idx;
++ /* Instead of bcast for ea address for default wep keys,
++ driver needs it to be Null */
++ if (!is_multicast_ether_addr(mac_addr))
++ memcpy((char *)&key.ea, (void *)mac_addr, ETH_ALEN);
++ key.len = (u32) params->key_len;
++ /* check for key index change */
++ if (key.len == 0) {
++ /* key delete */
++ err = send_key_to_dongle(ifp, &key);
++ if (err)
++ brcmf_err("key delete error (%d)\n", err);
++ } else {
++ if (key.len > sizeof(key.data)) {
++ brcmf_err("Invalid key length (%d)\n", key.len);
++ return -EINVAL;
++ }
++
++ brcmf_dbg(CONN, "Setting the key index %d\n", key.index);
++ memcpy(key.data, params->key, key.len);
++
++ if (!brcmf_is_apmode(ifp->vif) &&
++ (params->cipher == WLAN_CIPHER_SUITE_TKIP)) {
++ brcmf_dbg(CONN, "Swapping RX/TX MIC key\n");
++ memcpy(keybuf, &key.data[24], sizeof(keybuf));
++ memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
++ memcpy(&key.data[16], keybuf, sizeof(keybuf));
++ }
++
++ /* if IW_ENCODE_EXT_RX_SEQ_VALID set */
++ if (params->seq && params->seq_len == 6) {
++ /* rx iv */
++ u8 *ivptr;
++ ivptr = (u8 *) params->seq;
++ key.rxiv.hi = (ivptr[5] << 24) | (ivptr[4] << 16) |
++ (ivptr[3] << 8) | ivptr[2];
++ key.rxiv.lo = (ivptr[1] << 8) | ivptr[0];
++ key.iv_initialized = true;
++ }
++
++ switch (params->cipher) {
++ case WLAN_CIPHER_SUITE_WEP40:
++ key.algo = CRYPTO_ALGO_WEP1;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP40\n");
++ break;
++ case WLAN_CIPHER_SUITE_WEP104:
++ key.algo = CRYPTO_ALGO_WEP128;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP104\n");
++ break;
++ case WLAN_CIPHER_SUITE_TKIP:
++ key.algo = CRYPTO_ALGO_TKIP;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_TKIP\n");
++ break;
++ case WLAN_CIPHER_SUITE_AES_CMAC:
++ key.algo = CRYPTO_ALGO_AES_CCM;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_AES_CMAC\n");
++ break;
++ case WLAN_CIPHER_SUITE_CCMP:
++ key.algo = CRYPTO_ALGO_AES_CCM;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_CCMP\n");
++ break;
++ default:
++ brcmf_err("Invalid cipher (0x%x)\n", params->cipher);
++ return -EINVAL;
++ }
++ err = send_key_to_dongle(ifp, &key);
++ if (err)
++ brcmf_err("wsec_key error (%d)\n", err);
++ }
++ return err;
++}
++
++static s32
++brcmf_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
++ u8 key_idx, bool pairwise, const u8 *mac_addr,
++ struct key_params *params)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_wsec_key *key;
++ s32 val;
++ s32 wsec;
++ s32 err = 0;
++ u8 keybuf[8];
++
++ brcmf_dbg(TRACE, "Enter\n");
++ brcmf_dbg(CONN, "key index (%d)\n", key_idx);
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ if (key_idx >= BRCMF_MAX_DEFAULT_KEYS) {
++ /* we ignore this key index in this case */
++ brcmf_err("invalid key index (%d)\n", key_idx);
++ return -EINVAL;
++ }
++
++ if (mac_addr &&
++ (params->cipher != WLAN_CIPHER_SUITE_WEP40) &&
++ (params->cipher != WLAN_CIPHER_SUITE_WEP104)) {
++ brcmf_dbg(TRACE, "Exit");
++ return brcmf_add_keyext(wiphy, ndev, key_idx, mac_addr, params);
++ }
++
++ key = &ifp->vif->profile.key[key_idx];
++ memset(key, 0, sizeof(*key));
++
++ if (params->key_len > sizeof(key->data)) {
++ brcmf_err("Too long key length (%u)\n", params->key_len);
++ err = -EINVAL;
++ goto done;
++ }
++ key->len = params->key_len;
++ key->index = key_idx;
++
++ memcpy(key->data, params->key, key->len);
++
++ key->flags = BRCMF_PRIMARY_KEY;
++ switch (params->cipher) {
++ case WLAN_CIPHER_SUITE_WEP40:
++ key->algo = CRYPTO_ALGO_WEP1;
++ val = WEP_ENABLED;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP40\n");
++ break;
++ case WLAN_CIPHER_SUITE_WEP104:
++ key->algo = CRYPTO_ALGO_WEP128;
++ val = WEP_ENABLED;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP104\n");
++ break;
++ case WLAN_CIPHER_SUITE_TKIP:
++ if (!brcmf_is_apmode(ifp->vif)) {
++ brcmf_dbg(CONN, "Swapping RX/TX MIC key\n");
++ memcpy(keybuf, &key->data[24], sizeof(keybuf));
++ memcpy(&key->data[24], &key->data[16], sizeof(keybuf));
++ memcpy(&key->data[16], keybuf, sizeof(keybuf));
++ }
++ key->algo = CRYPTO_ALGO_TKIP;
++ val = TKIP_ENABLED;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_TKIP\n");
++ break;
++ case WLAN_CIPHER_SUITE_AES_CMAC:
++ key->algo = CRYPTO_ALGO_AES_CCM;
++ val = AES_ENABLED;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_AES_CMAC\n");
++ break;
++ case WLAN_CIPHER_SUITE_CCMP:
++ key->algo = CRYPTO_ALGO_AES_CCM;
++ val = AES_ENABLED;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_CCMP\n");
++ break;
++ default:
++ brcmf_err("Invalid cipher (0x%x)\n", params->cipher);
++ err = -EINVAL;
++ goto done;
++ }
++
++ err = send_key_to_dongle(ifp, key);
++ if (err)
++ goto done;
++
++ err = brcmf_fil_bsscfg_int_get(ifp, "wsec", &wsec);
++ if (err) {
++ brcmf_err("get wsec error (%d)\n", err);
++ goto done;
++ }
++ wsec |= val;
++ err = brcmf_fil_bsscfg_int_set(ifp, "wsec", wsec);
++ if (err) {
++ brcmf_err("set wsec error (%d)\n", err);
++ goto done;
++ }
++
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
++ u8 key_idx, bool pairwise, const u8 *mac_addr)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_wsec_key key;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ if (key_idx >= BRCMF_MAX_DEFAULT_KEYS) {
++ /* we ignore this key index in this case */
++ return -EINVAL;
++ }
++
++ memset(&key, 0, sizeof(key));
++
++ key.index = (u32) key_idx;
++ key.flags = BRCMF_PRIMARY_KEY;
++ key.algo = CRYPTO_ALGO_OFF;
++
++ brcmf_dbg(CONN, "key index (%d)\n", key_idx);
++
++ /* Set the new key/index */
++ err = send_key_to_dongle(ifp, &key);
++
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_get_key(struct wiphy *wiphy, struct net_device *ndev,
++ u8 key_idx, bool pairwise, const u8 *mac_addr, void *cookie,
++ void (*callback) (void *cookie, struct key_params * params))
++{
++ struct key_params params;
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct brcmf_cfg80211_security *sec;
++ s32 wsec;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ brcmf_dbg(CONN, "key index (%d)\n", key_idx);
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ memset(&params, 0, sizeof(params));
++
++ err = brcmf_fil_bsscfg_int_get(ifp, "wsec", &wsec);
++ if (err) {
++ brcmf_err("WLC_GET_WSEC error (%d)\n", err);
++ /* Ignore this error, may happen during DISASSOC */
++ err = -EAGAIN;
++ goto done;
++ }
++ if (wsec & WEP_ENABLED) {
++ sec = &profile->sec;
++ if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP40) {
++ params.cipher = WLAN_CIPHER_SUITE_WEP40;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP40\n");
++ } else if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP104) {
++ params.cipher = WLAN_CIPHER_SUITE_WEP104;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP104\n");
++ }
++ } else if (wsec & TKIP_ENABLED) {
++ params.cipher = WLAN_CIPHER_SUITE_TKIP;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_TKIP\n");
++ } else if (wsec & AES_ENABLED) {
++ params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;
++ brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_AES_CMAC\n");
++ } else {
++ brcmf_err("Invalid algo (0x%x)\n", wsec);
++ err = -EINVAL;
++ goto done;
++ }
++ callback(cookie, &params);
++
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_config_default_mgmt_key(struct wiphy *wiphy,
++ struct net_device *ndev, u8 key_idx)
++{
++ brcmf_dbg(INFO, "Not supported\n");
++
++ return -EOPNOTSUPP;
++}
++
++static void
++brcmf_cfg80211_reconfigure_wep(struct brcmf_if *ifp)
++{
++ s32 err;
++ u8 key_idx;
++ struct brcmf_wsec_key *key;
++ s32 wsec;
++
++ for (key_idx = 0; key_idx < BRCMF_MAX_DEFAULT_KEYS; key_idx++) {
++ key = &ifp->vif->profile.key[key_idx];
++ if ((key->algo == CRYPTO_ALGO_WEP1) ||
++ (key->algo == CRYPTO_ALGO_WEP128))
++ break;
++ }
++ if (key_idx == BRCMF_MAX_DEFAULT_KEYS)
++ return;
++
++ err = send_key_to_dongle(ifp, key);
++ if (err) {
++ brcmf_err("Setting WEP key failed (%d)\n", err);
++ return;
++ }
++ err = brcmf_fil_bsscfg_int_get(ifp, "wsec", &wsec);
++ if (err) {
++ brcmf_err("get wsec error (%d)\n", err);
++ return;
++ }
++ wsec |= WEP_ENABLED;
++ err = brcmf_fil_bsscfg_int_set(ifp, "wsec", wsec);
++ if (err)
++ brcmf_err("set wsec error (%d)\n", err);
++}
++
++static s32
++brcmf_cfg80211_get_station(struct wiphy *wiphy, struct net_device *ndev,
++ u8 *mac, struct station_info *sinfo)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct brcmf_scb_val_le scb_val;
++ int rssi;
++ s32 rate;
++ s32 err = 0;
++ u8 *bssid = profile->bssid;
++ struct brcmf_sta_info_le sta_info_le;
++ u32 beacon_period;
++ u32 dtim_period;
++
++ brcmf_dbg(TRACE, "Enter, MAC %pM\n", mac);
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ if (brcmf_is_apmode(ifp->vif)) {
++ memcpy(&sta_info_le, mac, ETH_ALEN);
++ err = brcmf_fil_iovar_data_get(ifp, "sta_info",
++ &sta_info_le,
++ sizeof(sta_info_le));
++ if (err < 0) {
++ brcmf_err("GET STA INFO failed, %d\n", err);
++ goto done;
++ }
++ sinfo->filled = STATION_INFO_INACTIVE_TIME;
++ sinfo->inactive_time = le32_to_cpu(sta_info_le.idle) * 1000;
++ if (le32_to_cpu(sta_info_le.flags) & BRCMF_STA_ASSOC) {
++ sinfo->filled |= STATION_INFO_CONNECTED_TIME;
++ sinfo->connected_time = le32_to_cpu(sta_info_le.in);
++ }
++ brcmf_dbg(TRACE, "STA idle time : %d ms, connected time :%d sec\n",
++ sinfo->inactive_time, sinfo->connected_time);
++ } else if (ifp->vif->wdev.iftype == NL80211_IFTYPE_STATION) {
++ if (memcmp(mac, bssid, ETH_ALEN)) {
++ brcmf_err("Wrong Mac address cfg_mac-%pM wl_bssid-%pM\n",
++ mac, bssid);
++ err = -ENOENT;
++ goto done;
++ }
++ /* Report the current tx rate */
++ err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_RATE, &rate);
++ if (err) {
++ brcmf_err("Could not get rate (%d)\n", err);
++ goto done;
++ } else {
++ sinfo->filled |= STATION_INFO_TX_BITRATE;
++ sinfo->txrate.legacy = rate * 5;
++ brcmf_dbg(CONN, "Rate %d Mbps\n", rate / 2);
++ }
++
++ if (test_bit(BRCMF_VIF_STATUS_CONNECTED,
++ &ifp->vif->sme_state)) {
++ memset(&scb_val, 0, sizeof(scb_val));
++ err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_RSSI,
++ &scb_val, sizeof(scb_val));
++ if (err) {
++ brcmf_err("Could not get rssi (%d)\n", err);
++ goto done;
++ } else {
++ rssi = le32_to_cpu(scb_val.val);
++ sinfo->filled |= STATION_INFO_SIGNAL;
++ sinfo->signal = rssi;
++ brcmf_dbg(CONN, "RSSI %d dBm\n", rssi);
++ }
++ err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_BCNPRD,
++ &beacon_period);
++ if (err) {
++ brcmf_err("Could not get beacon period (%d)\n",
++ err);
++ goto done;
++ } else {
++ sinfo->bss_param.beacon_interval =
++ beacon_period;
++ brcmf_dbg(CONN, "Beacon peroid %d\n",
++ beacon_period);
++ }
++ err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_DTIMPRD,
++ &dtim_period);
++ if (err) {
++ brcmf_err("Could not get DTIM period (%d)\n",
++ err);
++ goto done;
++ } else {
++ sinfo->bss_param.dtim_period = dtim_period;
++ brcmf_dbg(CONN, "DTIM peroid %d\n",
++ dtim_period);
++ }
++ sinfo->filled |= STATION_INFO_BSS_PARAM;
++ }
++ } else
++ err = -EPERM;
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *ndev,
++ bool enabled, s32 timeout)
++{
++ s32 pm;
++ s32 err = 0;
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /*
++ * Powersave enable/disable request is coming from the
++ * cfg80211 even before the interface is up. In that
++ * scenario, driver will be storing the power save
++ * preference in cfg struct to apply this to
++ * FW later while initializing the dongle
++ */
++ cfg->pwr_save = enabled;
++ if (!check_vif_up(ifp->vif)) {
++
++ brcmf_dbg(INFO, "Device is not ready, storing the value in cfg_info struct\n");
++ goto done;
++ }
++
++ pm = enabled ? PM_FAST : PM_OFF;
++ /* Do not enable the power save after assoc if it is a p2p interface */
++ if (ifp->vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) {
++ brcmf_dbg(INFO, "Do not enable power save for P2P clients\n");
++ pm = PM_OFF;
++ }
++ brcmf_dbg(INFO, "power save %s\n", (pm ? "enabled" : "disabled"));
++
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, pm);
++ if (err) {
++ if (err == -ENODEV)
++ brcmf_err("net_device is not ready yet\n");
++ else
++ brcmf_err("error (%d)\n", err);
++ }
++done:
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_bss_info_le *bi)
++{
++ struct wiphy *wiphy = cfg_to_wiphy(cfg);
++ struct ieee80211_channel *notify_channel;
++ struct cfg80211_bss *bss;
++ struct ieee80211_supported_band *band;
++ struct brcmu_chan ch;
++ u16 channel;
++ u32 freq;
++ u16 notify_capability;
++ u16 notify_interval;
++ u8 *notify_ie;
++ size_t notify_ielen;
++ s32 notify_signal;
++
++ if (le32_to_cpu(bi->length) > WL_BSS_INFO_MAX) {
++ brcmf_err("Bss info is larger than buffer. Discarding\n");
++ return 0;
++ }
++
++ if (!bi->ctl_ch) {
++ ch.chspec = le16_to_cpu(bi->chanspec);
++ cfg->d11inf.decchspec(&ch);
++ bi->ctl_ch = ch.chnum;
++ }
++ channel = bi->ctl_ch;
++
++ if (channel <= CH_MAX_2G_CHANNEL)
++ band = wiphy->bands[IEEE80211_BAND_2GHZ];
++ else
++ band = wiphy->bands[IEEE80211_BAND_5GHZ];
++
++ freq = ieee80211_channel_to_frequency(channel, band->band);
++ notify_channel = ieee80211_get_channel(wiphy, freq);
++
++ notify_capability = le16_to_cpu(bi->capability);
++ notify_interval = le16_to_cpu(bi->beacon_period);
++ notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
++ notify_ielen = le32_to_cpu(bi->ie_length);
++ notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
++
++ brcmf_dbg(CONN, "bssid: %pM\n", bi->BSSID);
++ brcmf_dbg(CONN, "Channel: %d(%d)\n", channel, freq);
++ brcmf_dbg(CONN, "Capability: %X\n", notify_capability);
++ brcmf_dbg(CONN, "Beacon interval: %d\n", notify_interval);
++ brcmf_dbg(CONN, "Signal: %d\n", notify_signal);
++
++ bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)bi->BSSID,
++ 0, notify_capability, notify_interval, notify_ie,
++ notify_ielen, notify_signal, GFP_KERNEL);
++
++ if (!bss)
++ return -ENOMEM;
++
++ cfg80211_put_bss(wiphy, bss);
++
++ return 0;
++}
++
++static struct brcmf_bss_info_le *
++next_bss_le(struct brcmf_scan_results *list, struct brcmf_bss_info_le *bss)
++{
++ if (bss == NULL)
++ return list->bss_info_le;
++ return (struct brcmf_bss_info_le *)((unsigned long)bss +
++ le32_to_cpu(bss->length));
++}
++
++static s32 brcmf_inform_bss(struct brcmf_cfg80211_info *cfg)
++{
++ struct brcmf_scan_results *bss_list;
++ struct brcmf_bss_info_le *bi = NULL; /* must be initialized */
++ s32 err = 0;
++ int i;
++
++ bss_list = (struct brcmf_scan_results *)cfg->escan_info.escan_buf;
++ if (bss_list->count != 0 &&
++ bss_list->version != BRCMF_BSS_INFO_VERSION) {
++ brcmf_err("Version %d != WL_BSS_INFO_VERSION\n",
++ bss_list->version);
++ return -EOPNOTSUPP;
++ }
++ brcmf_dbg(SCAN, "scanned AP count (%d)\n", bss_list->count);
++ for (i = 0; i < bss_list->count; i++) {
++ bi = next_bss_le(bss_list, bi);
++ err = brcmf_inform_single_bss(cfg, bi);
++ if (err)
++ break;
++ }
++ return err;
++}
++
++static s32 wl_inform_ibss(struct brcmf_cfg80211_info *cfg,
++ struct net_device *ndev, const u8 *bssid)
++{
++ struct wiphy *wiphy = cfg_to_wiphy(cfg);
++ struct ieee80211_channel *notify_channel;
++ struct brcmf_bss_info_le *bi = NULL;
++ struct ieee80211_supported_band *band;
++ struct cfg80211_bss *bss;
++ struct brcmu_chan ch;
++ u8 *buf = NULL;
++ s32 err = 0;
++ u32 freq;
++ u16 notify_capability;
++ u16 notify_interval;
++ u8 *notify_ie;
++ size_t notify_ielen;
++ s32 notify_signal;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
++ if (buf == NULL) {
++ err = -ENOMEM;
++ goto CleanUp;
++ }
++
++ *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
++
++ err = brcmf_fil_cmd_data_get(netdev_priv(ndev), BRCMF_C_GET_BSS_INFO,
++ buf, WL_BSS_INFO_MAX);
++ if (err) {
++ brcmf_err("WLC_GET_BSS_INFO failed: %d\n", err);
++ goto CleanUp;
++ }
++
++ bi = (struct brcmf_bss_info_le *)(buf + 4);
++
++ ch.chspec = le16_to_cpu(bi->chanspec);
++ cfg->d11inf.decchspec(&ch);
++
++ if (ch.band == BRCMU_CHAN_BAND_2G)
++ band = wiphy->bands[IEEE80211_BAND_2GHZ];
++ else
++ band = wiphy->bands[IEEE80211_BAND_5GHZ];
++
++ freq = ieee80211_channel_to_frequency(ch.chnum, band->band);
++ notify_channel = ieee80211_get_channel(wiphy, freq);
++
++ notify_capability = le16_to_cpu(bi->capability);
++ notify_interval = le16_to_cpu(bi->beacon_period);
++ notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
++ notify_ielen = le32_to_cpu(bi->ie_length);
++ notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
++
++ brcmf_dbg(CONN, "channel: %d(%d)\n", ch.chnum, freq);
++ brcmf_dbg(CONN, "capability: %X\n", notify_capability);
++ brcmf_dbg(CONN, "beacon interval: %d\n", notify_interval);
++ brcmf_dbg(CONN, "signal: %d\n", notify_signal);
++
++ bss = cfg80211_inform_bss(wiphy, notify_channel, bssid,
++ 0, notify_capability, notify_interval,
++ notify_ie, notify_ielen, notify_signal, GFP_KERNEL);
++
++ if (!bss) {
++ err = -ENOMEM;
++ goto CleanUp;
++ }
++
++ cfg80211_put_bss(wiphy, bss);
++
++CleanUp:
++
++ kfree(buf);
++
++ brcmf_dbg(TRACE, "Exit\n");
++
++ return err;
++}
++
++static s32 brcmf_update_bss_info(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_if *ifp)
++{
++ struct brcmf_cfg80211_profile *profile = ndev_to_prof(ifp->ndev);
++ struct brcmf_bss_info_le *bi;
++ struct brcmf_ssid *ssid;
++ const struct brcmf_tlv *tim;
++ u16 beacon_interval;
++ u8 dtim_period;
++ size_t ie_len;
++ u8 *ie;
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (brcmf_is_ibssmode(ifp->vif))
++ return err;
++
++ ssid = &profile->ssid;
++
++ *(__le32 *)cfg->extra_buf = cpu_to_le32(WL_EXTRA_BUF_MAX);
++ err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSS_INFO,
++ cfg->extra_buf, WL_EXTRA_BUF_MAX);
++ if (err) {
++ brcmf_err("Could not get bss info %d\n", err);
++ goto update_bss_info_out;
++ }
++
++ bi = (struct brcmf_bss_info_le *)(cfg->extra_buf + 4);
++ err = brcmf_inform_single_bss(cfg, bi);
++ if (err)
++ goto update_bss_info_out;
++
++ ie = ((u8 *)bi) + le16_to_cpu(bi->ie_offset);
++ ie_len = le32_to_cpu(bi->ie_length);
++ beacon_interval = le16_to_cpu(bi->beacon_period);
++
++ tim = brcmf_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
++ if (tim)
++ dtim_period = tim->data[1];
++ else {
++ /*
++ * active scan was done so we could not get dtim
++ * information out of probe response.
++ * so we speficially query dtim information to dongle.
++ */
++ u32 var;
++ err = brcmf_fil_iovar_int_get(ifp, "dtim_assoc", &var);
++ if (err) {
++ brcmf_err("wl dtim_assoc failed (%d)\n", err);
++ goto update_bss_info_out;
++ }
++ dtim_period = (u8)var;
++ }
++
++update_bss_info_out:
++ brcmf_dbg(TRACE, "Exit");
++ return err;
++}
++
++void brcmf_abort_scanning(struct brcmf_cfg80211_info *cfg)
++{
++ struct escan_info *escan = &cfg->escan_info;
++
++ set_bit(BRCMF_SCAN_STATUS_ABORT, &cfg->scan_status);
++ if (cfg->scan_request) {
++ escan->escan_state = WL_ESCAN_STATE_IDLE;
++ brcmf_notify_escan_complete(cfg, escan->ifp, true, true);
++ }
++ clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
++ clear_bit(BRCMF_SCAN_STATUS_ABORT, &cfg->scan_status);
++}
++
++static void brcmf_cfg80211_escan_timeout_worker(struct work_struct *work)
++{
++ struct brcmf_cfg80211_info *cfg =
++ container_of(work, struct brcmf_cfg80211_info,
++ escan_timeout_work);
++
++ brcmf_inform_bss(cfg);
++ brcmf_notify_escan_complete(cfg, cfg->escan_info.ifp, true, true);
++}
++
++static void brcmf_escan_timeout(unsigned long data)
++{
++ struct brcmf_cfg80211_info *cfg =
++ (struct brcmf_cfg80211_info *)data;
++
++ if (cfg->scan_request) {
++ brcmf_err("timer expired\n");
++ schedule_work(&cfg->escan_timeout_work);
++ }
++}
++
++static s32
++brcmf_compare_update_same_bss(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_bss_info_le *bss,
++ struct brcmf_bss_info_le *bss_info_le)
++{
++ struct brcmu_chan ch_bss, ch_bss_info_le;
++
++ ch_bss.chspec = le16_to_cpu(bss->chanspec);
++ cfg->d11inf.decchspec(&ch_bss);
++ ch_bss_info_le.chspec = le16_to_cpu(bss_info_le->chanspec);
++ cfg->d11inf.decchspec(&ch_bss_info_le);
++
++ if (!memcmp(&bss_info_le->BSSID, &bss->BSSID, ETH_ALEN) &&
++ ch_bss.band == ch_bss_info_le.band &&
++ bss_info_le->SSID_len == bss->SSID_len &&
++ !memcmp(bss_info_le->SSID, bss->SSID, bss_info_le->SSID_len)) {
++ if ((bss->flags & BRCMF_BSS_RSSI_ON_CHANNEL) ==
++ (bss_info_le->flags & BRCMF_BSS_RSSI_ON_CHANNEL)) {
++ s16 bss_rssi = le16_to_cpu(bss->RSSI);
++ s16 bss_info_rssi = le16_to_cpu(bss_info_le->RSSI);
++
++ /* preserve max RSSI if the measurements are
++ * both on-channel or both off-channel
++ */
++ if (bss_info_rssi > bss_rssi)
++ bss->RSSI = bss_info_le->RSSI;
++ } else if ((bss->flags & BRCMF_BSS_RSSI_ON_CHANNEL) &&
++ (bss_info_le->flags & BRCMF_BSS_RSSI_ON_CHANNEL) == 0) {
++ /* preserve the on-channel rssi measurement
++ * if the new measurement is off channel
++ */
++ bss->RSSI = bss_info_le->RSSI;
++ bss->flags |= BRCMF_BSS_RSSI_ON_CHANNEL;
++ }
++ return 1;
++ }
++ return 0;
++}
++
++static s32
++brcmf_cfg80211_escan_handler(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e, void *data)
++{
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++ s32 status;
++ struct brcmf_escan_result_le *escan_result_le;
++ struct brcmf_bss_info_le *bss_info_le;
++ struct brcmf_bss_info_le *bss = NULL;
++ u32 bi_length;
++ struct brcmf_scan_results *list;
++ u32 i;
++ bool aborted;
++
++ status = e->status;
++
++ if (!test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
++ brcmf_err("scan not ready, bssidx=%d\n", ifp->bssidx);
++ return -EPERM;
++ }
++
++ if (status == BRCMF_E_STATUS_PARTIAL) {
++ brcmf_dbg(SCAN, "ESCAN Partial result\n");
++ escan_result_le = (struct brcmf_escan_result_le *) data;
++ if (!escan_result_le) {
++ brcmf_err("Invalid escan result (NULL pointer)\n");
++ goto exit;
++ }
++ if (le16_to_cpu(escan_result_le->bss_count) != 1) {
++ brcmf_err("Invalid bss_count %d: ignoring\n",
++ escan_result_le->bss_count);
++ goto exit;
++ }
++ bss_info_le = &escan_result_le->bss_info_le;
++
++ if (brcmf_p2p_scan_finding_common_channel(cfg, bss_info_le))
++ goto exit;
++
++ if (!cfg->scan_request) {
++ brcmf_dbg(SCAN, "result without cfg80211 request\n");
++ goto exit;
++ }
++
++ bi_length = le32_to_cpu(bss_info_le->length);
++ if (bi_length != (le32_to_cpu(escan_result_le->buflen) -
++ WL_ESCAN_RESULTS_FIXED_SIZE)) {
++ brcmf_err("Invalid bss_info length %d: ignoring\n",
++ bi_length);
++ goto exit;
++ }
++
++ if (!(cfg_to_wiphy(cfg)->interface_modes &
++ BIT(NL80211_IFTYPE_ADHOC))) {
++ if (le16_to_cpu(bss_info_le->capability) &
++ WLAN_CAPABILITY_IBSS) {
++ brcmf_err("Ignoring IBSS result\n");
++ goto exit;
++ }
++ }
++
++ list = (struct brcmf_scan_results *)
++ cfg->escan_info.escan_buf;
++ if (bi_length > WL_ESCAN_BUF_SIZE - list->buflen) {
++ brcmf_err("Buffer is too small: ignoring\n");
++ goto exit;
++ }
++
++ for (i = 0; i < list->count; i++) {
++ bss = bss ? (struct brcmf_bss_info_le *)
++ ((unsigned char *)bss +
++ le32_to_cpu(bss->length)) : list->bss_info_le;
++ if (brcmf_compare_update_same_bss(cfg, bss,
++ bss_info_le))
++ goto exit;
++ }
++ memcpy(&(cfg->escan_info.escan_buf[list->buflen]),
++ bss_info_le, bi_length);
++ list->version = le32_to_cpu(bss_info_le->version);
++ list->buflen += bi_length;
++ list->count++;
++ } else {
++ cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++ if (brcmf_p2p_scan_finding_common_channel(cfg, NULL))
++ goto exit;
++ if (cfg->scan_request) {
++ brcmf_inform_bss(cfg);
++ aborted = status != BRCMF_E_STATUS_SUCCESS;
++ brcmf_notify_escan_complete(cfg, ifp, aborted, false);
++ } else
++ brcmf_dbg(SCAN, "Ignored scan complete result 0x%x\n",
++ status);
++ }
++exit:
++ return 0;
++}
++
++static void brcmf_init_escan(struct brcmf_cfg80211_info *cfg)
++{
++ brcmf_fweh_register(cfg->pub, BRCMF_E_ESCAN_RESULT,
++ brcmf_cfg80211_escan_handler);
++ cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
++ /* Init scan_timeout timer */
++ init_timer(&cfg->escan_timeout);
++ cfg->escan_timeout.data = (unsigned long) cfg;
++ cfg->escan_timeout.function = brcmf_escan_timeout;
++ INIT_WORK(&cfg->escan_timeout_work,
++ brcmf_cfg80211_escan_timeout_worker);
++}
++
++static __always_inline void brcmf_delay(u32 ms)
++{
++ if (ms < 1000 / HZ) {
++ cond_resched();
++ mdelay(ms);
++ } else {
++ msleep(ms);
++ }
++}
++
++static s32 brcmf_config_wowl_pattern(struct brcmf_if *ifp, u8 cmd[4],
++ u8 *pattern, u32 patternsize, u8 *mask,
++ u32 packet_offset)
++{
++ struct brcmf_fil_wowl_pattern_le *filter;
++ u32 masksize;
++ u32 patternoffset;
++ u8 *buf;
++ u32 bufsize;
++ s32 ret;
++
++ masksize = (patternsize + 7) / 8;
++ patternoffset = sizeof(*filter) - sizeof(filter->cmd) + masksize;
++
++ bufsize = sizeof(*filter) + patternsize + masksize;
++ buf = kzalloc(bufsize, GFP_KERNEL);
++ if (!buf)
++ return -ENOMEM;
++ filter = (struct brcmf_fil_wowl_pattern_le *)buf;
++
++ memcpy(filter->cmd, cmd, 4);
++ filter->masksize = cpu_to_le32(masksize);
++ filter->offset = cpu_to_le32(packet_offset);
++ filter->patternoffset = cpu_to_le32(patternoffset);
++ filter->patternsize = cpu_to_le32(patternsize);
++ filter->type = cpu_to_le32(BRCMF_WOWL_PATTERN_TYPE_BITMAP);
++
++ if ((mask) && (masksize))
++ memcpy(buf + sizeof(*filter), mask, masksize);
++ if ((pattern) && (patternsize))
++ memcpy(buf + sizeof(*filter) + masksize, pattern, patternsize);
++
++ ret = brcmf_fil_iovar_data_set(ifp, "wowl_pattern", buf, bufsize);
++
++ kfree(buf);
++ return ret;
++}
++
++static s32 brcmf_cfg80211_resume(struct wiphy *wiphy)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct net_device *ndev = cfg_to_ndev(cfg);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (cfg->wowl_enabled) {
++ brcmf_configure_arp_offload(ifp, true);
++ brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM,
++ cfg->pre_wowl_pmmode);
++ brcmf_fil_iovar_int_set(ifp, "wowl_clear", 0);
++ brcmf_config_wowl_pattern(ifp, "clr", NULL, 0, NULL, 0);
++ cfg->wowl_enabled = false;
++ }
++ return 0;
++}
++
++static void brcmf_configure_wowl(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_if *ifp,
++ struct cfg80211_wowlan *wowl)
++{
++ u32 wowl_config;
++ u32 i;
++
++ brcmf_dbg(TRACE, "Suspend, wowl config.\n");
++
++ brcmf_configure_arp_offload(ifp, false);
++ brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_PM, &cfg->pre_wowl_pmmode);
++ brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, PM_MAX);
++
++ wowl_config = 0;
++ if (wowl->disconnect)
++ wowl_config = BRCMF_WOWL_DIS | BRCMF_WOWL_BCN | BRCMF_WOWL_RETR;
++ if (wowl->magic_pkt)
++ wowl_config |= BRCMF_WOWL_MAGIC;
++ if ((wowl->patterns) && (wowl->n_patterns)) {
++ wowl_config |= BRCMF_WOWL_NET;
++ for (i = 0; i < wowl->n_patterns; i++) {
++ brcmf_config_wowl_pattern(ifp, "add",
++ (u8 *)wowl->patterns[i].pattern,
++ wowl->patterns[i].pattern_len,
++ (u8 *)wowl->patterns[i].mask,
++ wowl->patterns[i].pkt_offset);
++ }
++ }
++ brcmf_fil_iovar_int_set(ifp, "wowl", wowl_config);
++ brcmf_fil_iovar_int_set(ifp, "wowl_activate", 1);
++ brcmf_bus_wowl_config(cfg->pub->bus_if, true);
++ cfg->wowl_enabled = true;
++}
++
++static s32 brcmf_cfg80211_suspend(struct wiphy *wiphy,
++ struct cfg80211_wowlan *wowl)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct net_device *ndev = cfg_to_ndev(cfg);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_vif *vif;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* if the primary net_device is not READY there is nothing
++ * we can do but pray resume goes smoothly.
++ */
++ if (!check_vif_up(ifp->vif))
++ goto exit;
++
++ /* end any scanning */
++ if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status))
++ brcmf_abort_scanning(cfg);
++
++ if (wowl == NULL) {
++ brcmf_bus_wowl_config(cfg->pub->bus_if, false);
++ list_for_each_entry(vif, &cfg->vif_list, list) {
++ if (!test_bit(BRCMF_VIF_STATUS_READY, &vif->sme_state))
++ continue;
++ /* While going to suspend if associated with AP
++ * disassociate from AP to save power while system is
++ * in suspended state
++ */
++ brcmf_link_down(vif, WLAN_REASON_UNSPECIFIED);
++ /* Make sure WPA_Supplicant receives all the event
++ * generated due to DISASSOC call to the fw to keep
++ * the state fw and WPA_Supplicant state consistent
++ */
++ brcmf_delay(500);
++ }
++ /* Configure MPC */
++ brcmf_set_mpc(ifp, 1);
++
++ } else {
++ /* Configure WOWL paramaters */
++ brcmf_configure_wowl(cfg, ifp, wowl);
++ }
++
++exit:
++ brcmf_dbg(TRACE, "Exit\n");
++ /* clear any scanning activity */
++ cfg->scan_status = 0;
++ return 0;
++}
++
++static __used s32
++brcmf_update_pmklist(struct net_device *ndev,
++ struct brcmf_cfg80211_pmk_list *pmk_list, s32 err)
++{
++ int i, j;
++ u32 pmkid_len;
++
++ pmkid_len = le32_to_cpu(pmk_list->pmkids.npmkid);
++
++ brcmf_dbg(CONN, "No of elements %d\n", pmkid_len);
++ for (i = 0; i < pmkid_len; i++) {
++ brcmf_dbg(CONN, "PMKID[%d]: %pM =\n", i,
++ &pmk_list->pmkids.pmkid[i].BSSID);
++ for (j = 0; j < WLAN_PMKID_LEN; j++)
++ brcmf_dbg(CONN, "%02x\n",
++ pmk_list->pmkids.pmkid[i].PMKID[j]);
++ }
++
++ if (!err)
++ brcmf_fil_iovar_data_set(netdev_priv(ndev), "pmkid_info",
++ (char *)pmk_list, sizeof(*pmk_list));
++
++ return err;
++}
++
++static s32
++brcmf_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_pmksa *pmksa)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct pmkid_list *pmkids = &cfg->pmk_list->pmkids;
++ s32 err = 0;
++ u32 pmkid_len, i;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ pmkid_len = le32_to_cpu(pmkids->npmkid);
++ for (i = 0; i < pmkid_len; i++)
++ if (!memcmp(pmksa->bssid, pmkids->pmkid[i].BSSID, ETH_ALEN))
++ break;
++ if (i < WL_NUM_PMKIDS_MAX) {
++ memcpy(pmkids->pmkid[i].BSSID, pmksa->bssid, ETH_ALEN);
++ memcpy(pmkids->pmkid[i].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
++ if (i == pmkid_len) {
++ pmkid_len++;
++ pmkids->npmkid = cpu_to_le32(pmkid_len);
++ }
++ } else
++ err = -EINVAL;
++
++ brcmf_dbg(CONN, "set_pmksa,IW_PMKSA_ADD - PMKID: %pM =\n",
++ pmkids->pmkid[pmkid_len].BSSID);
++ for (i = 0; i < WLAN_PMKID_LEN; i++)
++ brcmf_dbg(CONN, "%02x\n", pmkids->pmkid[pmkid_len].PMKID[i]);
++
++ err = brcmf_update_pmklist(ndev, cfg->pmk_list, err);
++
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_pmksa *pmksa)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct pmkid_list pmkid;
++ s32 err = 0;
++ u32 pmkid_len, i;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ memcpy(&pmkid.pmkid[0].BSSID, pmksa->bssid, ETH_ALEN);
++ memcpy(&pmkid.pmkid[0].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
++
++ brcmf_dbg(CONN, "del_pmksa,IW_PMKSA_REMOVE - PMKID: %pM =\n",
++ &pmkid.pmkid[0].BSSID);
++ for (i = 0; i < WLAN_PMKID_LEN; i++)
++ brcmf_dbg(CONN, "%02x\n", pmkid.pmkid[0].PMKID[i]);
++
++ pmkid_len = le32_to_cpu(cfg->pmk_list->pmkids.npmkid);
++ for (i = 0; i < pmkid_len; i++)
++ if (!memcmp
++ (pmksa->bssid, &cfg->pmk_list->pmkids.pmkid[i].BSSID,
++ ETH_ALEN))
++ break;
++
++ if ((pmkid_len > 0)
++ && (i < pmkid_len)) {
++ memset(&cfg->pmk_list->pmkids.pmkid[i], 0,
++ sizeof(struct pmkid));
++ for (; i < (pmkid_len - 1); i++) {
++ memcpy(&cfg->pmk_list->pmkids.pmkid[i].BSSID,
++ &cfg->pmk_list->pmkids.pmkid[i + 1].BSSID,
++ ETH_ALEN);
++ memcpy(&cfg->pmk_list->pmkids.pmkid[i].PMKID,
++ &cfg->pmk_list->pmkids.pmkid[i + 1].PMKID,
++ WLAN_PMKID_LEN);
++ }
++ cfg->pmk_list->pmkids.npmkid = cpu_to_le32(pmkid_len - 1);
++ } else
++ err = -EINVAL;
++
++ err = brcmf_update_pmklist(ndev, cfg->pmk_list, err);
++
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++
++}
++
++static s32
++brcmf_cfg80211_flush_pmksa(struct wiphy *wiphy, struct net_device *ndev)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ s32 err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ memset(cfg->pmk_list, 0, sizeof(*cfg->pmk_list));
++ err = brcmf_update_pmklist(ndev, cfg->pmk_list, err);
++
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++
++}
++
++/*
++ * PFN result doesn't have all the info which are
++ * required by the supplicant
++ * (For e.g IEs) Do a target Escan so that sched scan results are reported
++ * via wl_inform_single_bss in the required format. Escan does require the
++ * scan request in the form of cfg80211_scan_request. For timebeing, create
++ * cfg80211_scan_request one out of the received PNO event.
++ */
++static s32
++brcmf_notify_sched_scan_results(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e, void *data)
++{
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++ struct brcmf_pno_net_info_le *netinfo, *netinfo_start;
++ struct cfg80211_scan_request *request = NULL;
++ struct cfg80211_ssid *ssid = NULL;
++ struct ieee80211_channel *channel = NULL;
++ struct wiphy *wiphy = cfg_to_wiphy(cfg);
++ int err = 0;
++ int channel_req = 0;
++ int band = 0;
++ struct brcmf_pno_scanresults_le *pfn_result;
++ u32 result_count;
++ u32 status;
++
++ brcmf_dbg(SCAN, "Enter\n");
++
++ if (e->event_code == BRCMF_E_PFN_NET_LOST) {
++ brcmf_dbg(SCAN, "PFN NET LOST event. Do Nothing\n");
++ return 0;
++ }
++
++ pfn_result = (struct brcmf_pno_scanresults_le *)data;
++ result_count = le32_to_cpu(pfn_result->count);
++ status = le32_to_cpu(pfn_result->status);
++
++ /*
++ * PFN event is limited to fit 512 bytes so we may get
++ * multiple NET_FOUND events. For now place a warning here.
++ */
++ WARN_ON(status != BRCMF_PNO_SCAN_COMPLETE);
++ brcmf_dbg(SCAN, "PFN NET FOUND event. count: %d\n", result_count);
++ if (result_count > 0) {
++ int i;
++
++ request = kzalloc(sizeof(*request), GFP_KERNEL);
++ ssid = kcalloc(result_count, sizeof(*ssid), GFP_KERNEL);
++ channel = kcalloc(result_count, sizeof(*channel), GFP_KERNEL);
++ if (!request || !ssid || !channel) {
++ err = -ENOMEM;
++ goto out_err;
++ }
++
++ request->wiphy = wiphy;
++ data += sizeof(struct brcmf_pno_scanresults_le);
++ netinfo_start = (struct brcmf_pno_net_info_le *)data;
++
++ for (i = 0; i < result_count; i++) {
++ netinfo = &netinfo_start[i];
++ if (!netinfo) {
++ brcmf_err("Invalid netinfo ptr. index: %d\n",
++ i);
++ err = -EINVAL;
++ goto out_err;
++ }
++
++ brcmf_dbg(SCAN, "SSID:%s Channel:%d\n",
++ netinfo->SSID, netinfo->channel);
++ memcpy(ssid[i].ssid, netinfo->SSID, netinfo->SSID_len);
++ ssid[i].ssid_len = netinfo->SSID_len;
++ request->n_ssids++;
++
++ channel_req = netinfo->channel;
++ if (channel_req <= CH_MAX_2G_CHANNEL)
++ band = NL80211_BAND_2GHZ;
++ else
++ band = NL80211_BAND_5GHZ;
++ channel[i].center_freq =
++ ieee80211_channel_to_frequency(channel_req,
++ band);
++ channel[i].band = band;
++ channel[i].flags |= IEEE80211_CHAN_NO_HT40;
++ request->channels[i] = &channel[i];
++ request->n_channels++;
++ }
++
++ /* assign parsed ssid array */
++ if (request->n_ssids)
++ request->ssids = &ssid[0];
++
++ if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
++ /* Abort any on-going scan */
++ brcmf_abort_scanning(cfg);
++ }
++
++ set_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
++ cfg->escan_info.run = brcmf_run_escan;
++ err = brcmf_do_escan(cfg, wiphy, ifp, request);
++ if (err) {
++ clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
++ goto out_err;
++ }
++ cfg->sched_escan = true;
++ cfg->scan_request = request;
++ } else {
++ brcmf_err("FALSE PNO Event. (pfn_count == 0)\n");
++ goto out_err;
++ }
++
++ kfree(ssid);
++ kfree(channel);
++ kfree(request);
++ return 0;
++
++out_err:
++ kfree(ssid);
++ kfree(channel);
++ kfree(request);
++ cfg80211_sched_scan_stopped(wiphy);
++ return err;
++}
++
++static int brcmf_dev_pno_clean(struct net_device *ndev)
++{
++ int ret;
++
++ /* Disable pfn */
++ ret = brcmf_fil_iovar_int_set(netdev_priv(ndev), "pfn", 0);
++ if (ret == 0) {
++ /* clear pfn */
++ ret = brcmf_fil_iovar_data_set(netdev_priv(ndev), "pfnclear",
++ NULL, 0);
++ }
++ if (ret < 0)
++ brcmf_err("failed code %d\n", ret);
++
++ return ret;
++}
++
++static int brcmf_dev_pno_config(struct net_device *ndev)
++{
++ struct brcmf_pno_param_le pfn_param;
++
++ memset(&pfn_param, 0, sizeof(pfn_param));
++ pfn_param.version = cpu_to_le32(BRCMF_PNO_VERSION);
++
++ /* set extra pno params */
++ pfn_param.flags = cpu_to_le16(1 << BRCMF_PNO_ENABLE_ADAPTSCAN_BIT);
++ pfn_param.repeat = BRCMF_PNO_REPEAT;
++ pfn_param.exp = BRCMF_PNO_FREQ_EXPO_MAX;
++
++ /* set up pno scan fr */
++ pfn_param.scan_freq = cpu_to_le32(BRCMF_PNO_TIME);
++
++ return brcmf_fil_iovar_data_set(netdev_priv(ndev), "pfn_set",
++ &pfn_param, sizeof(pfn_param));
++}
++
++static int
++brcmf_cfg80211_sched_scan_start(struct wiphy *wiphy,
++ struct net_device *ndev,
++ struct cfg80211_sched_scan_request *request)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
++ struct brcmf_pno_net_param_le pfn;
++ int i;
++ int ret = 0;
++
++ brcmf_dbg(SCAN, "Enter n_match_sets:%d n_ssids:%d\n",
++ request->n_match_sets, request->n_ssids);
++ if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
++ brcmf_err("Scanning already: status (%lu)\n", cfg->scan_status);
++ return -EAGAIN;
++ }
++ if (test_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status)) {
++ brcmf_err("Scanning suppressed: status (%lu)\n",
++ cfg->scan_status);
++ return -EAGAIN;
++ }
++
++ if (!request->n_ssids || !request->n_match_sets) {
++ brcmf_dbg(SCAN, "Invalid sched scan req!! n_ssids:%d\n",
++ request->n_ssids);
++ return -EINVAL;
++ }
++
++ if (request->n_ssids > 0) {
++ for (i = 0; i < request->n_ssids; i++) {
++ /* Active scan req for ssids */
++ brcmf_dbg(SCAN, ">>> Active scan req for ssid (%s)\n",
++ request->ssids[i].ssid);
++
++ /*
++ * match_set ssids is a supert set of n_ssid list,
++ * so we need not add these set seperately.
++ */
++ }
++ }
++
++ if (request->n_match_sets > 0) {
++ /* clean up everything */
++ ret = brcmf_dev_pno_clean(ndev);
++ if (ret < 0) {
++ brcmf_err("failed error=%d\n", ret);
++ return ret;
++ }
++
++ /* configure pno */
++ ret = brcmf_dev_pno_config(ndev);
++ if (ret < 0) {
++ brcmf_err("PNO setup failed!! ret=%d\n", ret);
++ return -EINVAL;
++ }
++
++ /* configure each match set */
++ for (i = 0; i < request->n_match_sets; i++) {
++ struct cfg80211_ssid *ssid;
++ u32 ssid_len;
++
++ ssid = &request->match_sets[i].ssid;
++ ssid_len = ssid->ssid_len;
++
++ if (!ssid_len) {
++ brcmf_err("skip broadcast ssid\n");
++ continue;
++ }
++ pfn.auth = cpu_to_le32(WLAN_AUTH_OPEN);
++ pfn.wpa_auth = cpu_to_le32(BRCMF_PNO_WPA_AUTH_ANY);
++ pfn.wsec = cpu_to_le32(0);
++ pfn.infra = cpu_to_le32(1);
++ pfn.flags = cpu_to_le32(1 << BRCMF_PNO_HIDDEN_BIT);
++ pfn.ssid.SSID_len = cpu_to_le32(ssid_len);
++ memcpy(pfn.ssid.SSID, ssid->ssid, ssid_len);
++ ret = brcmf_fil_iovar_data_set(ifp, "pfn_add", &pfn,
++ sizeof(pfn));
++ brcmf_dbg(SCAN, ">>> PNO filter %s for ssid (%s)\n",
++ ret == 0 ? "set" : "failed", ssid->ssid);
++ }
++ /* Enable the PNO */
++ if (brcmf_fil_iovar_int_set(ifp, "pfn", 1) < 0) {
++ brcmf_err("PNO enable failed!! ret=%d\n", ret);
++ return -EINVAL;
++ }
++ } else {
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int brcmf_cfg80211_sched_scan_stop(struct wiphy *wiphy,
++ struct net_device *ndev)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++
++ brcmf_dbg(SCAN, "enter\n");
++ brcmf_dev_pno_clean(ndev);
++ if (cfg->sched_escan)
++ brcmf_notify_escan_complete(cfg, netdev_priv(ndev), true, true);
++ return 0;
++}
++
++static s32 brcmf_configure_opensecurity(struct brcmf_if *ifp)
++{
++ s32 err;
++
++ /* set auth */
++ err = brcmf_fil_bsscfg_int_set(ifp, "auth", 0);
++ if (err < 0) {
++ brcmf_err("auth error %d\n", err);
++ return err;
++ }
++ /* set wsec */
++ err = brcmf_fil_bsscfg_int_set(ifp, "wsec", 0);
++ if (err < 0) {
++ brcmf_err("wsec error %d\n", err);
++ return err;
++ }
++ /* set upper-layer auth */
++ err = brcmf_fil_bsscfg_int_set(ifp, "wpa_auth", WPA_AUTH_NONE);
++ if (err < 0) {
++ brcmf_err("wpa_auth error %d\n", err);
++ return err;
++ }
++
++ return 0;
++}
++
++static bool brcmf_valid_wpa_oui(u8 *oui, bool is_rsn_ie)
++{
++ if (is_rsn_ie)
++ return (memcmp(oui, RSN_OUI, TLV_OUI_LEN) == 0);
++
++ return (memcmp(oui, WPA_OUI, TLV_OUI_LEN) == 0);
++}
++
++static s32
++brcmf_configure_wpaie(struct brcmf_if *ifp,
++ const struct brcmf_vs_tlv *wpa_ie,
++ bool is_rsn_ie)
++{
++ u32 auth = 0; /* d11 open authentication */
++ u16 count;
++ s32 err = 0;
++ s32 len = 0;
++ u32 i;
++ u32 wsec;
++ u32 pval = 0;
++ u32 gval = 0;
++ u32 wpa_auth = 0;
++ u32 offset;
++ u8 *data;
++ u16 rsn_cap;
++ u32 wme_bss_disable;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (wpa_ie == NULL)
++ goto exit;
++
++ len = wpa_ie->len + TLV_HDR_LEN;
++ data = (u8 *)wpa_ie;
++ offset = TLV_HDR_LEN;
++ if (!is_rsn_ie)
++ offset += VS_IE_FIXED_HDR_LEN;
++ else
++ offset += WPA_IE_VERSION_LEN;
++
++ /* check for multicast cipher suite */
++ if (offset + WPA_IE_MIN_OUI_LEN > len) {
++ err = -EINVAL;
++ brcmf_err("no multicast cipher suite\n");
++ goto exit;
++ }
++
++ if (!brcmf_valid_wpa_oui(&data[offset], is_rsn_ie)) {
++ err = -EINVAL;
++ brcmf_err("ivalid OUI\n");
++ goto exit;
++ }
++ offset += TLV_OUI_LEN;
++
++ /* pick up multicast cipher */
++ switch (data[offset]) {
++ case WPA_CIPHER_NONE:
++ gval = 0;
++ break;
++ case WPA_CIPHER_WEP_40:
++ case WPA_CIPHER_WEP_104:
++ gval = WEP_ENABLED;
++ break;
++ case WPA_CIPHER_TKIP:
++ gval = TKIP_ENABLED;
++ break;
++ case WPA_CIPHER_AES_CCM:
++ gval = AES_ENABLED;
++ break;
++ default:
++ err = -EINVAL;
++ brcmf_err("Invalid multi cast cipher info\n");
++ goto exit;
++ }
++
++ offset++;
++ /* walk thru unicast cipher list and pick up what we recognize */
++ count = data[offset] + (data[offset + 1] << 8);
++ offset += WPA_IE_SUITE_COUNT_LEN;
++ /* Check for unicast suite(s) */
++ if (offset + (WPA_IE_MIN_OUI_LEN * count) > len) {
++ err = -EINVAL;
++ brcmf_err("no unicast cipher suite\n");
++ goto exit;
++ }
++ for (i = 0; i < count; i++) {
++ if (!brcmf_valid_wpa_oui(&data[offset], is_rsn_ie)) {
++ err = -EINVAL;
++ brcmf_err("ivalid OUI\n");
++ goto exit;
++ }
++ offset += TLV_OUI_LEN;
++ switch (data[offset]) {
++ case WPA_CIPHER_NONE:
++ break;
++ case WPA_CIPHER_WEP_40:
++ case WPA_CIPHER_WEP_104:
++ pval |= WEP_ENABLED;
++ break;
++ case WPA_CIPHER_TKIP:
++ pval |= TKIP_ENABLED;
++ break;
++ case WPA_CIPHER_AES_CCM:
++ pval |= AES_ENABLED;
++ break;
++ default:
++ brcmf_err("Ivalid unicast security info\n");
++ }
++ offset++;
++ }
++ /* walk thru auth management suite list and pick up what we recognize */
++ count = data[offset] + (data[offset + 1] << 8);
++ offset += WPA_IE_SUITE_COUNT_LEN;
++ /* Check for auth key management suite(s) */
++ if (offset + (WPA_IE_MIN_OUI_LEN * count) > len) {
++ err = -EINVAL;
++ brcmf_err("no auth key mgmt suite\n");
++ goto exit;
++ }
++ for (i = 0; i < count; i++) {
++ if (!brcmf_valid_wpa_oui(&data[offset], is_rsn_ie)) {
++ err = -EINVAL;
++ brcmf_err("ivalid OUI\n");
++ goto exit;
++ }
++ offset += TLV_OUI_LEN;
++ switch (data[offset]) {
++ case RSN_AKM_NONE:
++ brcmf_dbg(TRACE, "RSN_AKM_NONE\n");
++ wpa_auth |= WPA_AUTH_NONE;
++ break;
++ case RSN_AKM_UNSPECIFIED:
++ brcmf_dbg(TRACE, "RSN_AKM_UNSPECIFIED\n");
++ is_rsn_ie ? (wpa_auth |= WPA2_AUTH_UNSPECIFIED) :
++ (wpa_auth |= WPA_AUTH_UNSPECIFIED);
++ break;
++ case RSN_AKM_PSK:
++ brcmf_dbg(TRACE, "RSN_AKM_PSK\n");
++ is_rsn_ie ? (wpa_auth |= WPA2_AUTH_PSK) :
++ (wpa_auth |= WPA_AUTH_PSK);
++ break;
++ default:
++ brcmf_err("Ivalid key mgmt info\n");
++ }
++ offset++;
++ }
++
++ if (is_rsn_ie) {
++ wme_bss_disable = 1;
++ if ((offset + RSN_CAP_LEN) <= len) {
++ rsn_cap = data[offset] + (data[offset + 1] << 8);
++ if (rsn_cap & RSN_CAP_PTK_REPLAY_CNTR_MASK)
++ wme_bss_disable = 0;
++ }
++ /* set wme_bss_disable to sync RSN Capabilities */
++ err = brcmf_fil_bsscfg_int_set(ifp, "wme_bss_disable",
++ wme_bss_disable);
++ if (err < 0) {
++ brcmf_err("wme_bss_disable error %d\n", err);
++ goto exit;
++ }
++ }
++ /* FOR WPS , set SES_OW_ENABLED */
++ wsec = (pval | gval | SES_OW_ENABLED);
++
++ /* set auth */
++ err = brcmf_fil_bsscfg_int_set(ifp, "auth", auth);
++ if (err < 0) {
++ brcmf_err("auth error %d\n", err);
++ goto exit;
++ }
++ /* set wsec */
++ err = brcmf_fil_bsscfg_int_set(ifp, "wsec", wsec);
++ if (err < 0) {
++ brcmf_err("wsec error %d\n", err);
++ goto exit;
++ }
++ /* set upper-layer auth */
++ err = brcmf_fil_bsscfg_int_set(ifp, "wpa_auth", wpa_auth);
++ if (err < 0) {
++ brcmf_err("wpa_auth error %d\n", err);
++ goto exit;
++ }
++
++exit:
++ return err;
++}
++
++static s32
++brcmf_parse_vndr_ies(const u8 *vndr_ie_buf, u32 vndr_ie_len,
++ struct parsed_vndr_ies *vndr_ies)
++{
++ struct brcmf_vs_tlv *vndrie;
++ struct brcmf_tlv *ie;
++ struct parsed_vndr_ie_info *parsed_info;
++ s32 remaining_len;
++
++ remaining_len = (s32)vndr_ie_len;
++ memset(vndr_ies, 0, sizeof(*vndr_ies));
++
++ ie = (struct brcmf_tlv *)vndr_ie_buf;
++ while (ie) {
++ if (ie->id != WLAN_EID_VENDOR_SPECIFIC)
++ goto next;
++ vndrie = (struct brcmf_vs_tlv *)ie;
++ /* len should be bigger than OUI length + one */
++ if (vndrie->len < (VS_IE_FIXED_HDR_LEN - TLV_HDR_LEN + 1)) {
++ brcmf_err("invalid vndr ie. length is too small %d\n",
++ vndrie->len);
++ goto next;
++ }
++ /* if wpa or wme ie, do not add ie */
++ if (!memcmp(vndrie->oui, (u8 *)WPA_OUI, TLV_OUI_LEN) &&
++ ((vndrie->oui_type == WPA_OUI_TYPE) ||
++ (vndrie->oui_type == WME_OUI_TYPE))) {
++ brcmf_dbg(TRACE, "Found WPA/WME oui. Do not add it\n");
++ goto next;
++ }
++
++ parsed_info = &vndr_ies->ie_info[vndr_ies->count];
++
++ /* save vndr ie information */
++ parsed_info->ie_ptr = (char *)vndrie;
++ parsed_info->ie_len = vndrie->len + TLV_HDR_LEN;
++ memcpy(&parsed_info->vndrie, vndrie, sizeof(*vndrie));
++
++ vndr_ies->count++;
++
++ brcmf_dbg(TRACE, "** OUI %02x %02x %02x, type 0x%02x\n",
++ parsed_info->vndrie.oui[0],
++ parsed_info->vndrie.oui[1],
++ parsed_info->vndrie.oui[2],
++ parsed_info->vndrie.oui_type);
++
++ if (vndr_ies->count >= VNDR_IE_PARSE_LIMIT)
++ break;
++next:
++ remaining_len -= (ie->len + TLV_HDR_LEN);
++ if (remaining_len <= TLV_HDR_LEN)
++ ie = NULL;
++ else
++ ie = (struct brcmf_tlv *)(((u8 *)ie) + ie->len +
++ TLV_HDR_LEN);
++ }
++ return 0;
++}
++
++static u32
++brcmf_vndr_ie(u8 *iebuf, s32 pktflag, u8 *ie_ptr, u32 ie_len, s8 *add_del_cmd)
++{
++
++ strncpy(iebuf, add_del_cmd, VNDR_IE_CMD_LEN - 1);
++ iebuf[VNDR_IE_CMD_LEN - 1] = '\0';
++
++ put_unaligned_le32(1, &iebuf[VNDR_IE_COUNT_OFFSET]);
++
++ put_unaligned_le32(pktflag, &iebuf[VNDR_IE_PKTFLAG_OFFSET]);
++
++ memcpy(&iebuf[VNDR_IE_VSIE_OFFSET], ie_ptr, ie_len);
++
++ return ie_len + VNDR_IE_HDR_SIZE;
++}
++
++s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
++ const u8 *vndr_ie_buf, u32 vndr_ie_len)
++{
++ struct brcmf_if *ifp;
++ struct vif_saved_ie *saved_ie;
++ s32 err = 0;
++ u8 *iovar_ie_buf;
++ u8 *curr_ie_buf;
++ u8 *mgmt_ie_buf = NULL;
++ int mgmt_ie_buf_len;
++ u32 *mgmt_ie_len;
++ u32 del_add_ie_buf_len = 0;
++ u32 total_ie_buf_len = 0;
++ u32 parsed_ie_buf_len = 0;
++ struct parsed_vndr_ies old_vndr_ies;
++ struct parsed_vndr_ies new_vndr_ies;
++ struct parsed_vndr_ie_info *vndrie_info;
++ s32 i;
++ u8 *ptr;
++ int remained_buf_len;
++
++ if (!vif)
++ return -ENODEV;
++ ifp = vif->ifp;
++ saved_ie = &vif->saved_ie;
++
++ brcmf_dbg(TRACE, "bssidx %d, pktflag : 0x%02X\n", ifp->bssidx, pktflag);
++ iovar_ie_buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++ if (!iovar_ie_buf)
++ return -ENOMEM;
++ curr_ie_buf = iovar_ie_buf;
++ switch (pktflag) {
++ case BRCMF_VNDR_IE_PRBREQ_FLAG:
++ mgmt_ie_buf = saved_ie->probe_req_ie;
++ mgmt_ie_len = &saved_ie->probe_req_ie_len;
++ mgmt_ie_buf_len = sizeof(saved_ie->probe_req_ie);
++ break;
++ case BRCMF_VNDR_IE_PRBRSP_FLAG:
++ mgmt_ie_buf = saved_ie->probe_res_ie;
++ mgmt_ie_len = &saved_ie->probe_res_ie_len;
++ mgmt_ie_buf_len = sizeof(saved_ie->probe_res_ie);
++ break;
++ case BRCMF_VNDR_IE_BEACON_FLAG:
++ mgmt_ie_buf = saved_ie->beacon_ie;
++ mgmt_ie_len = &saved_ie->beacon_ie_len;
++ mgmt_ie_buf_len = sizeof(saved_ie->beacon_ie);
++ break;
++ case BRCMF_VNDR_IE_ASSOCREQ_FLAG:
++ mgmt_ie_buf = saved_ie->assoc_req_ie;
++ mgmt_ie_len = &saved_ie->assoc_req_ie_len;
++ mgmt_ie_buf_len = sizeof(saved_ie->assoc_req_ie);
++ break;
++ default:
++ err = -EPERM;
++ brcmf_err("not suitable type\n");
++ goto exit;
++ }
++
++ if (vndr_ie_len > mgmt_ie_buf_len) {
++ err = -ENOMEM;
++ brcmf_err("extra IE size too big\n");
++ goto exit;
++ }
++
++ /* parse and save new vndr_ie in curr_ie_buff before comparing it */
++ if (vndr_ie_buf && vndr_ie_len && curr_ie_buf) {
++ ptr = curr_ie_buf;
++ brcmf_parse_vndr_ies(vndr_ie_buf, vndr_ie_len, &new_vndr_ies);
++ for (i = 0; i < new_vndr_ies.count; i++) {
++ vndrie_info = &new_vndr_ies.ie_info[i];
++ memcpy(ptr + parsed_ie_buf_len, vndrie_info->ie_ptr,
++ vndrie_info->ie_len);
++ parsed_ie_buf_len += vndrie_info->ie_len;
++ }
++ }
++
++ if (mgmt_ie_buf && *mgmt_ie_len) {
++ if (parsed_ie_buf_len && (parsed_ie_buf_len == *mgmt_ie_len) &&
++ (memcmp(mgmt_ie_buf, curr_ie_buf,
++ parsed_ie_buf_len) == 0)) {
++ brcmf_dbg(TRACE, "Previous mgmt IE equals to current IE\n");
++ goto exit;
++ }
++
++ /* parse old vndr_ie */
++ brcmf_parse_vndr_ies(mgmt_ie_buf, *mgmt_ie_len, &old_vndr_ies);
++
++ /* make a command to delete old ie */
++ for (i = 0; i < old_vndr_ies.count; i++) {
++ vndrie_info = &old_vndr_ies.ie_info[i];
++
++ brcmf_dbg(TRACE, "DEL ID : %d, Len: %d , OUI:%02x:%02x:%02x\n",
++ vndrie_info->vndrie.id,
++ vndrie_info->vndrie.len,
++ vndrie_info->vndrie.oui[0],
++ vndrie_info->vndrie.oui[1],
++ vndrie_info->vndrie.oui[2]);
++
++ del_add_ie_buf_len = brcmf_vndr_ie(curr_ie_buf, pktflag,
++ vndrie_info->ie_ptr,
++ vndrie_info->ie_len,
++ "del");
++ curr_ie_buf += del_add_ie_buf_len;
++ total_ie_buf_len += del_add_ie_buf_len;
++ }
++ }
++
++ *mgmt_ie_len = 0;
++ /* Add if there is any extra IE */
++ if (mgmt_ie_buf && parsed_ie_buf_len) {
++ ptr = mgmt_ie_buf;
++
++ remained_buf_len = mgmt_ie_buf_len;
++
++ /* make a command to add new ie */
++ for (i = 0; i < new_vndr_ies.count; i++) {
++ vndrie_info = &new_vndr_ies.ie_info[i];
++
++ /* verify remained buf size before copy data */
++ if (remained_buf_len < (vndrie_info->vndrie.len +
++ VNDR_IE_VSIE_OFFSET)) {
++ brcmf_err("no space in mgmt_ie_buf: len left %d",
++ remained_buf_len);
++ break;
++ }
++ remained_buf_len -= (vndrie_info->ie_len +
++ VNDR_IE_VSIE_OFFSET);
++
++ brcmf_dbg(TRACE, "ADDED ID : %d, Len: %d, OUI:%02x:%02x:%02x\n",
++ vndrie_info->vndrie.id,
++ vndrie_info->vndrie.len,
++ vndrie_info->vndrie.oui[0],
++ vndrie_info->vndrie.oui[1],
++ vndrie_info->vndrie.oui[2]);
++
++ del_add_ie_buf_len = brcmf_vndr_ie(curr_ie_buf, pktflag,
++ vndrie_info->ie_ptr,
++ vndrie_info->ie_len,
++ "add");
++
++ /* save the parsed IE in wl struct */
++ memcpy(ptr + (*mgmt_ie_len), vndrie_info->ie_ptr,
++ vndrie_info->ie_len);
++ *mgmt_ie_len += vndrie_info->ie_len;
++
++ curr_ie_buf += del_add_ie_buf_len;
++ total_ie_buf_len += del_add_ie_buf_len;
++ }
++ }
++ if (total_ie_buf_len) {
++ err = brcmf_fil_bsscfg_data_set(ifp, "vndr_ie", iovar_ie_buf,
++ total_ie_buf_len);
++ if (err)
++ brcmf_err("vndr ie set error : %d\n", err);
++ }
++
++exit:
++ kfree(iovar_ie_buf);
++ return err;
++}
++
++s32 brcmf_vif_clear_mgmt_ies(struct brcmf_cfg80211_vif *vif)
++{
++ s32 pktflags[] = {
++ BRCMF_VNDR_IE_PRBREQ_FLAG,
++ BRCMF_VNDR_IE_PRBRSP_FLAG,
++ BRCMF_VNDR_IE_BEACON_FLAG
++ };
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(pktflags); i++)
++ brcmf_vif_set_mgmt_ie(vif, pktflags[i], NULL, 0);
++
++ memset(&vif->saved_ie, 0, sizeof(vif->saved_ie));
++ return 0;
++}
++
++static s32
++brcmf_config_ap_mgmt_ie(struct brcmf_cfg80211_vif *vif,
++ struct cfg80211_beacon_data *beacon)
++{
++ s32 err;
++
++ /* Set Beacon IEs to FW */
++ err = brcmf_vif_set_mgmt_ie(vif, BRCMF_VNDR_IE_BEACON_FLAG,
++ beacon->tail, beacon->tail_len);
++ if (err) {
++ brcmf_err("Set Beacon IE Failed\n");
++ return err;
++ }
++ brcmf_dbg(TRACE, "Applied Vndr IEs for Beacon\n");
++
++ /* Set Probe Response IEs to FW */
++ err = brcmf_vif_set_mgmt_ie(vif, BRCMF_VNDR_IE_PRBRSP_FLAG,
++ beacon->proberesp_ies,
++ beacon->proberesp_ies_len);
++ if (err)
++ brcmf_err("Set Probe Resp IE Failed\n");
++ else
++ brcmf_dbg(TRACE, "Applied Vndr IEs for Probe Resp\n");
++
++ return err;
++}
++
++static s32
++brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_ap_settings *settings)
++{
++ s32 ie_offset;
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ const struct brcmf_tlv *ssid_ie;
++ const struct brcmf_tlv *country_ie;
++ struct brcmf_ssid_le ssid_le;
++ s32 err = -EPERM;
++ const struct brcmf_tlv *rsn_ie;
++ const struct brcmf_vs_tlv *wpa_ie;
++ struct brcmf_join_params join_params;
++ enum nl80211_iftype dev_role;
++ struct brcmf_fil_bss_enable_le bss_enable;
++ u16 chanspec;
++ bool mbss;
++ int is_11d;
++
++ brcmf_dbg(TRACE, "ctrlchn=%d, center=%d, bw=%d, beacon_interval=%d, dtim_period=%d,\n",
++ settings->chandef.chan->hw_value,
++ settings->chandef.center_freq1, settings->chandef.width,
++ settings->beacon_interval, settings->dtim_period);
++ brcmf_dbg(TRACE, "ssid=%s(%zu), auth_type=%d, inactivity_timeout=%d\n",
++ settings->ssid, settings->ssid_len, settings->auth_type,
++ settings->inactivity_timeout);
++ dev_role = ifp->vif->wdev.iftype;
++ mbss = ifp->vif->mbss;
++
++ /* store current 11d setting */
++ brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_REGULATORY, &ifp->vif->is_11d);
++ country_ie = brcmf_parse_tlvs((u8 *)settings->beacon.tail,
++ settings->beacon.tail_len,
++ WLAN_EID_COUNTRY);
++ is_11d = country_ie ? 1 : 0;
++
++ memset(&ssid_le, 0, sizeof(ssid_le));
++ if (settings->ssid == NULL || settings->ssid_len == 0) {
++ ie_offset = DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_FIXED_LEN;
++ ssid_ie = brcmf_parse_tlvs(
++ (u8 *)&settings->beacon.head[ie_offset],
++ settings->beacon.head_len - ie_offset,
++ WLAN_EID_SSID);
++ if (!ssid_ie)
++ return -EINVAL;
++
++ memcpy(ssid_le.SSID, ssid_ie->data, ssid_ie->len);
++ ssid_le.SSID_len = cpu_to_le32(ssid_ie->len);
++ brcmf_dbg(TRACE, "SSID is (%s) in Head\n", ssid_le.SSID);
++ } else {
++ memcpy(ssid_le.SSID, settings->ssid, settings->ssid_len);
++ ssid_le.SSID_len = cpu_to_le32((u32)settings->ssid_len);
++ }
++
++ if (!mbss) {
++ brcmf_set_mpc(ifp, 0);
++ brcmf_configure_arp_offload(ifp, false);
++ }
++
++ /* find the RSN_IE */
++ rsn_ie = brcmf_parse_tlvs((u8 *)settings->beacon.tail,
++ settings->beacon.tail_len, WLAN_EID_RSN);
++
++ /* find the WPA_IE */
++ wpa_ie = brcmf_find_wpaie((u8 *)settings->beacon.tail,
++ settings->beacon.tail_len);
++
++ if ((wpa_ie != NULL || rsn_ie != NULL)) {
++ brcmf_dbg(TRACE, "WPA(2) IE is found\n");
++ if (wpa_ie != NULL) {
++ /* WPA IE */
++ err = brcmf_configure_wpaie(ifp, wpa_ie, false);
++ if (err < 0)
++ goto exit;
++ } else {
++ struct brcmf_vs_tlv *tmp_ie;
++
++ tmp_ie = (struct brcmf_vs_tlv *)rsn_ie;
++
++ /* RSN IE */
++ err = brcmf_configure_wpaie(ifp, tmp_ie, true);
++ if (err < 0)
++ goto exit;
++ }
++ } else {
++ brcmf_dbg(TRACE, "No WPA(2) IEs found\n");
++ brcmf_configure_opensecurity(ifp);
++ }
++
++ brcmf_config_ap_mgmt_ie(ifp->vif, &settings->beacon);
++
++ if (!mbss) {
++ chanspec = chandef_to_chanspec(&cfg->d11inf,
++ &settings->chandef);
++ err = brcmf_fil_iovar_int_set(ifp, "chanspec", chanspec);
++ if (err < 0) {
++ brcmf_err("Set Channel failed: chspec=%d, %d\n",
++ chanspec, err);
++ goto exit;
++ }
++
++ if (is_11d != ifp->vif->is_11d) {
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_REGULATORY,
++ is_11d);
++ if (err < 0) {
++ brcmf_err("Regulatory Set Error, %d\n", err);
++ goto exit;
++ }
++ }
++ if (settings->beacon_interval) {
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_BCNPRD,
++ settings->beacon_interval);
++ if (err < 0) {
++ brcmf_err("Beacon Interval Set Error, %d\n",
++ err);
++ goto exit;
++ }
++ }
++ if (settings->dtim_period) {
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_DTIMPRD,
++ settings->dtim_period);
++ if (err < 0) {
++ brcmf_err("DTIM Interval Set Error, %d\n", err);
++ goto exit;
++ }
++ }
++
++ if (dev_role == NL80211_IFTYPE_AP) {
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_DOWN, 1);
++ if (err < 0) {
++ brcmf_err("BRCMF_C_DOWN error %d\n", err);
++ goto exit;
++ }
++ brcmf_fil_iovar_int_set(ifp, "apsta", 0);
++ }
++
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_INFRA, 1);
++ if (err < 0) {
++ brcmf_err("SET INFRA error %d\n", err);
++ goto exit;
++ }
++ } else if (WARN_ON(is_11d != ifp->vif->is_11d)) {
++ /* Multiple-BSS should use same 11d configuration */
++ err = -EINVAL;
++ goto exit;
++ }
++ if (dev_role == NL80211_IFTYPE_AP) {
++ if ((brcmf_feat_is_enabled(ifp, BRCMF_FEAT_MBSS)) && (!mbss))
++ brcmf_fil_iovar_int_set(ifp, "mbss", 1);
++
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_AP, 1);
++ if (err < 0) {
++ brcmf_err("setting AP mode failed %d\n", err);
++ goto exit;
++ }
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 1);
++ if (err < 0) {
++ brcmf_err("BRCMF_C_UP error (%d)\n", err);
++ goto exit;
++ }
++ /* On DOWN the firmware removes the WEP keys, reconfigure
++ * them if they were set.
++ */
++ brcmf_cfg80211_reconfigure_wep(ifp);
++
++ memset(&join_params, 0, sizeof(join_params));
++ /* join parameters starts with ssid */
++ memcpy(&join_params.ssid_le, &ssid_le, sizeof(ssid_le));
++ /* create softap */
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
++ &join_params, sizeof(join_params));
++ if (err < 0) {
++ brcmf_err("SET SSID error (%d)\n", err);
++ goto exit;
++ }
++ brcmf_dbg(TRACE, "AP mode configuration complete\n");
++ } else {
++ err = brcmf_fil_bsscfg_data_set(ifp, "ssid", &ssid_le,
++ sizeof(ssid_le));
++ if (err < 0) {
++ brcmf_err("setting ssid failed %d\n", err);
++ goto exit;
++ }
++ bss_enable.bsscfg_idx = cpu_to_le32(ifp->bssidx);
++ bss_enable.enable = cpu_to_le32(1);
++ err = brcmf_fil_iovar_data_set(ifp, "bss", &bss_enable,
++ sizeof(bss_enable));
++ if (err < 0) {
++ brcmf_err("bss_enable config failed %d\n", err);
++ goto exit;
++ }
++
++ brcmf_dbg(TRACE, "GO mode configuration complete\n");
++ }
++ clear_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);
++ set_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
++
++exit:
++ if ((err) && (!mbss)) {
++ brcmf_set_mpc(ifp, 1);
++ brcmf_configure_arp_offload(ifp, true);
++ }
++ return err;
++}
++
++static int brcmf_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ s32 err;
++ struct brcmf_fil_bss_enable_le bss_enable;
++ struct brcmf_join_params join_params;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (ifp->vif->wdev.iftype == NL80211_IFTYPE_AP) {
++ /* Due to most likely deauths outstanding we sleep */
++ /* first to make sure they get processed by fw. */
++ msleep(400);
++
++ if (ifp->vif->mbss) {
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_DOWN, 1);
++ return err;
++ }
++
++ memset(&join_params, 0, sizeof(join_params));
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
++ &join_params, sizeof(join_params));
++ if (err < 0)
++ brcmf_err("SET SSID error (%d)\n", err);
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_DOWN, 1);
++ if (err < 0)
++ brcmf_err("BRCMF_C_DOWN error %d\n", err);
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_AP, 0);
++ if (err < 0)
++ brcmf_err("setting AP mode failed %d\n", err);
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_INFRA, 0);
++ if (err < 0)
++ brcmf_err("setting INFRA mode failed %d\n", err);
++ if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_MBSS))
++ brcmf_fil_iovar_int_set(ifp, "mbss", 0);
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_REGULATORY,
++ ifp->vif->is_11d);
++ if (err < 0)
++ brcmf_err("restoring REGULATORY setting failed %d\n",
++ err);
++ /* Bring device back up so it can be used again */
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 1);
++ if (err < 0)
++ brcmf_err("BRCMF_C_UP error %d\n", err);
++ } else {
++ bss_enable.bsscfg_idx = cpu_to_le32(ifp->bssidx);
++ bss_enable.enable = cpu_to_le32(0);
++ err = brcmf_fil_iovar_data_set(ifp, "bss", &bss_enable,
++ sizeof(bss_enable));
++ if (err < 0)
++ brcmf_err("bss_enable config failed %d\n", err);
++ }
++ brcmf_set_mpc(ifp, 1);
++ brcmf_configure_arp_offload(ifp, true);
++ set_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);
++ clear_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
++
++ return err;
++}
++
++static s32
++brcmf_cfg80211_change_beacon(struct wiphy *wiphy, struct net_device *ndev,
++ struct cfg80211_beacon_data *info)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ s32 err;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ err = brcmf_config_ap_mgmt_ie(ifp->vif, info);
++
++ return err;
++}
++
++static int
++brcmf_cfg80211_del_station(struct wiphy *wiphy, struct net_device *ndev,
++ u8 *mac)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_scb_val_le scbval;
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ s32 err;
++
++ if (!mac)
++ return -EFAULT;
++
++ brcmf_dbg(TRACE, "Enter %pM\n", mac);
++
++ if (ifp->vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif)
++ ifp = cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif->ifp;
++ if (!check_vif_up(ifp->vif))
++ return -EIO;
++
++ memcpy(&scbval.ea, mac, ETH_ALEN);
++ scbval.val = cpu_to_le32(WLAN_REASON_DEAUTH_LEAVING);
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SCB_DEAUTHENTICATE_FOR_REASON,
++ &scbval, sizeof(scbval));
++ if (err)
++ brcmf_err("SCB_DEAUTHENTICATE_FOR_REASON failed %d\n", err);
++
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static int
++brcmf_cfg80211_change_station(struct wiphy *wiphy, struct net_device *ndev,
++ const u8 *mac, struct station_parameters *params)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ s32 err;
++
++ brcmf_dbg(TRACE, "Enter, MAC %pM, mask 0x%04x set 0x%04x\n", mac,
++ params->sta_flags_mask, params->sta_flags_set);
++
++ /* Ignore all 00 MAC */
++ if (is_zero_ether_addr(mac))
++ return 0;
++
++ if (!(params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED)))
++ return 0;
++
++ if (params->sta_flags_set & BIT(NL80211_STA_FLAG_AUTHORIZED))
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SCB_AUTHORIZE,
++ (void *)mac, ETH_ALEN);
++ else
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SCB_DEAUTHORIZE,
++ (void *)mac, ETH_ALEN);
++ if (err < 0)
++ brcmf_err("Setting SCB (de-)authorize failed, %d\n", err);
++
++ return err;
++}
++
++static void
++brcmf_cfg80211_mgmt_frame_register(struct wiphy *wiphy,
++ struct wireless_dev *wdev,
++ u16 frame_type, bool reg)
++{
++ struct brcmf_cfg80211_vif *vif;
++ u16 mgmt_type;
++
++ brcmf_dbg(TRACE, "Enter, frame_type %04x, reg=%d\n", frame_type, reg);
++
++ mgmt_type = (frame_type & IEEE80211_FCTL_STYPE) >> 4;
++ vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
++ if (reg)
++ vif->mgmt_rx_reg |= BIT(mgmt_type);
++ else
++ vif->mgmt_rx_reg &= ~BIT(mgmt_type);
++}
++
++
++static int
++brcmf_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
++ struct cfg80211_mgmt_tx_params *params, u64 *cookie)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct ieee80211_channel *chan = params->chan;
++ const u8 *buf = params->buf;
++ size_t len = params->len;
++ const struct ieee80211_mgmt *mgmt;
++ struct brcmf_cfg80211_vif *vif;
++ s32 err = 0;
++ s32 ie_offset;
++ s32 ie_len;
++ struct brcmf_fil_action_frame_le *action_frame;
++ struct brcmf_fil_af_params_le *af_params;
++ bool ack;
++ s32 chan_nr;
++ u32 freq;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ *cookie = 0;
++
++ mgmt = (const struct ieee80211_mgmt *)buf;
++
++ if (!ieee80211_is_mgmt(mgmt->frame_control)) {
++ brcmf_err("Driver only allows MGMT packet type\n");
++ return -EPERM;
++ }
++
++ vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
++
++ if (ieee80211_is_probe_resp(mgmt->frame_control)) {
++ /* Right now the only reason to get a probe response */
++ /* is for p2p listen response or for p2p GO from */
++ /* wpa_supplicant. Unfortunately the probe is send */
++ /* on primary ndev, while dongle wants it on the p2p */
++ /* vif. Since this is only reason for a probe */
++ /* response to be sent, the vif is taken from cfg. */
++ /* If ever desired to send proberesp for non p2p */
++ /* response then data should be checked for */
++ /* "DIRECT-". Note in future supplicant will take */
++ /* dedicated p2p wdev to do this and then this 'hack'*/
++ /* is not needed anymore. */
++ ie_offset = DOT11_MGMT_HDR_LEN +
++ DOT11_BCN_PRB_FIXED_LEN;
++ ie_len = len - ie_offset;
++ if (vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif)
++ vif = cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif;
++ err = brcmf_vif_set_mgmt_ie(vif,
++ BRCMF_VNDR_IE_PRBRSP_FLAG,
++ &buf[ie_offset],
++ ie_len);
++ cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, true,
++ GFP_KERNEL);
++ } else if (ieee80211_is_action(mgmt->frame_control)) {
++ af_params = kzalloc(sizeof(*af_params), GFP_KERNEL);
++ if (af_params == NULL) {
++ brcmf_err("unable to allocate frame\n");
++ err = -ENOMEM;
++ goto exit;
++ }
++ action_frame = &af_params->action_frame;
++ /* Add the packet Id */
++ action_frame->packet_id = cpu_to_le32(*cookie);
++ /* Add BSSID */
++ memcpy(&action_frame->da[0], &mgmt->da[0], ETH_ALEN);
++ memcpy(&af_params->bssid[0], &mgmt->bssid[0], ETH_ALEN);
++ /* Add the length exepted for 802.11 header */
++ action_frame->len = cpu_to_le16(len - DOT11_MGMT_HDR_LEN);
++ /* Add the channel. Use the one specified as parameter if any or
++ * the current one (got from the firmware) otherwise
++ */
++ if (chan)
++ freq = chan->center_freq;
++ else
++ brcmf_fil_cmd_int_get(vif->ifp, BRCMF_C_GET_CHANNEL,
++ &freq);
++ chan_nr = ieee80211_frequency_to_channel(freq);
++ af_params->channel = cpu_to_le32(chan_nr);
++
++ memcpy(action_frame->data, &buf[DOT11_MGMT_HDR_LEN],
++ le16_to_cpu(action_frame->len));
++
++ brcmf_dbg(TRACE, "Action frame, cookie=%lld, len=%d, freq=%d\n",
++ *cookie, le16_to_cpu(action_frame->len), freq);
++
++ ack = brcmf_p2p_send_action_frame(cfg, cfg_to_ndev(cfg),
++ af_params);
++
++ cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack,
++ GFP_KERNEL);
++ kfree(af_params);
++ } else {
++ brcmf_dbg(TRACE, "Unhandled, fc=%04x!!\n", mgmt->frame_control);
++ brcmf_dbg_hex_dump(true, buf, len, "payload, len=%Zu\n", len);
++ }
++
++exit:
++ return err;
++}
++
++
++static int
++brcmf_cfg80211_cancel_remain_on_channel(struct wiphy *wiphy,
++ struct wireless_dev *wdev,
++ u64 cookie)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_cfg80211_vif *vif;
++ int err = 0;
++
++ brcmf_dbg(TRACE, "Enter p2p listen cancel\n");
++
++ vif = cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif;
++ if (vif == NULL) {
++ brcmf_err("No p2p device available for probe response\n");
++ err = -ENODEV;
++ goto exit;
++ }
++ brcmf_p2p_cancel_remain_on_channel(vif->ifp);
++exit:
++ return err;
++}
++
++static int brcmf_cfg80211_crit_proto_start(struct wiphy *wiphy,
++ struct wireless_dev *wdev,
++ enum nl80211_crit_proto_id proto,
++ u16 duration)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_cfg80211_vif *vif;
++
++ vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
++
++ /* only DHCP support for now */
++ if (proto != NL80211_CRIT_PROTO_DHCP)
++ return -EINVAL;
++
++ /* suppress and abort scanning */
++ set_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
++ brcmf_abort_scanning(cfg);
++
++ return brcmf_btcoex_set_mode(vif, BRCMF_BTCOEX_DISABLED, duration);
++}
++
++static void brcmf_cfg80211_crit_proto_stop(struct wiphy *wiphy,
++ struct wireless_dev *wdev)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
++ struct brcmf_cfg80211_vif *vif;
++
++ vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
++
++ brcmf_btcoex_set_mode(vif, BRCMF_BTCOEX_ENABLED, 0);
++ clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
++}
++
++static s32
++brcmf_notify_tdls_peer_event(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e, void *data)
++{
++ switch (e->reason) {
++ case BRCMF_E_REASON_TDLS_PEER_DISCOVERED:
++ brcmf_dbg(TRACE, "TDLS Peer Discovered\n");
++ break;
++ case BRCMF_E_REASON_TDLS_PEER_CONNECTED:
++ brcmf_dbg(TRACE, "TDLS Peer Connected\n");
++ brcmf_proto_add_tdls_peer(ifp->drvr, ifp->ifidx, (u8 *)e->addr);
++ break;
++ case BRCMF_E_REASON_TDLS_PEER_DISCONNECTED:
++ brcmf_dbg(TRACE, "TDLS Peer Disconnected\n");
++ brcmf_proto_delete_peer(ifp->drvr, ifp->ifidx, (u8 *)e->addr);
++ break;
++ }
++
++ return 0;
++}
++
++static int brcmf_convert_nl80211_tdls_oper(enum nl80211_tdls_operation oper)
++{
++ int ret;
++
++ switch (oper) {
++ case NL80211_TDLS_DISCOVERY_REQ:
++ ret = BRCMF_TDLS_MANUAL_EP_DISCOVERY;
++ break;
++ case NL80211_TDLS_SETUP:
++ ret = BRCMF_TDLS_MANUAL_EP_CREATE;
++ break;
++ case NL80211_TDLS_TEARDOWN:
++ ret = BRCMF_TDLS_MANUAL_EP_DELETE;
++ break;
++ default:
++ brcmf_err("unsupported operation: %d\n", oper);
++ ret = -EOPNOTSUPP;
++ }
++ return ret;
++}
++
++static int brcmf_cfg80211_tdls_oper(struct wiphy *wiphy,
++ struct net_device *ndev, u8 *peer,
++ enum nl80211_tdls_operation oper)
++{
++ struct brcmf_if *ifp;
++ struct brcmf_tdls_iovar_le info;
++ int ret = 0;
++
++ ret = brcmf_convert_nl80211_tdls_oper(oper);
++ if (ret < 0)
++ return ret;
++
++ ifp = netdev_priv(ndev);
++ memset(&info, 0, sizeof(info));
++ info.mode = (u8)ret;
++ if (peer)
++ memcpy(info.ea, peer, ETH_ALEN);
++
++ ret = brcmf_fil_iovar_data_set(ifp, "tdls_endpoint",
++ &info, sizeof(info));
++ if (ret < 0)
++ brcmf_err("tdls_endpoint iovar failed: ret=%d\n", ret);
++
++ return ret;
++}
++
++static struct cfg80211_ops wl_cfg80211_ops = {
++ .add_virtual_intf = brcmf_cfg80211_add_iface,
++ .del_virtual_intf = brcmf_cfg80211_del_iface,
++ .change_virtual_intf = brcmf_cfg80211_change_iface,
++ .scan = brcmf_cfg80211_scan,
++ .set_wiphy_params = brcmf_cfg80211_set_wiphy_params,
++ .join_ibss = brcmf_cfg80211_join_ibss,
++ .leave_ibss = brcmf_cfg80211_leave_ibss,
++ .get_station = brcmf_cfg80211_get_station,
++ .set_tx_power = brcmf_cfg80211_set_tx_power,
++ .get_tx_power = brcmf_cfg80211_get_tx_power,
++ .add_key = brcmf_cfg80211_add_key,
++ .del_key = brcmf_cfg80211_del_key,
++ .get_key = brcmf_cfg80211_get_key,
++ .set_default_key = brcmf_cfg80211_config_default_key,
++ .set_default_mgmt_key = brcmf_cfg80211_config_default_mgmt_key,
++ .set_power_mgmt = brcmf_cfg80211_set_power_mgmt,
++ .connect = brcmf_cfg80211_connect,
++ .disconnect = brcmf_cfg80211_disconnect,
++ .suspend = brcmf_cfg80211_suspend,
++ .resume = brcmf_cfg80211_resume,
++ .set_pmksa = brcmf_cfg80211_set_pmksa,
++ .del_pmksa = brcmf_cfg80211_del_pmksa,
++ .flush_pmksa = brcmf_cfg80211_flush_pmksa,
++ .start_ap = brcmf_cfg80211_start_ap,
++ .stop_ap = brcmf_cfg80211_stop_ap,
++ .change_beacon = brcmf_cfg80211_change_beacon,
++ .del_station = brcmf_cfg80211_del_station,
++ .change_station = brcmf_cfg80211_change_station,
++ .sched_scan_start = brcmf_cfg80211_sched_scan_start,
++ .sched_scan_stop = brcmf_cfg80211_sched_scan_stop,
++ .mgmt_frame_register = brcmf_cfg80211_mgmt_frame_register,
++ .mgmt_tx = brcmf_cfg80211_mgmt_tx,
++ .remain_on_channel = brcmf_p2p_remain_on_channel,
++ .cancel_remain_on_channel = brcmf_cfg80211_cancel_remain_on_channel,
++ .start_p2p_device = brcmf_p2p_start_device,
++ .stop_p2p_device = brcmf_p2p_stop_device,
++ .crit_proto_start = brcmf_cfg80211_crit_proto_start,
++ .crit_proto_stop = brcmf_cfg80211_crit_proto_stop,
++ .tdls_oper = brcmf_cfg80211_tdls_oper,
++};
++
++struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
++ enum nl80211_iftype type,
++ bool pm_block)
++{
++ struct brcmf_cfg80211_vif *vif_walk;
++ struct brcmf_cfg80211_vif *vif;
++ bool mbss;
++
++ brcmf_dbg(TRACE, "allocating virtual interface (size=%zu)\n",
++ sizeof(*vif));
++ vif = kzalloc(sizeof(*vif), GFP_KERNEL);
++ if (!vif)
++ return ERR_PTR(-ENOMEM);
++
++ vif->wdev.wiphy = cfg->wiphy;
++ vif->wdev.iftype = type;
++
++ vif->pm_block = pm_block;
++ vif->roam_off = -1;
++
++ brcmf_init_prof(&vif->profile);
++
++ if (type == NL80211_IFTYPE_AP) {
++ mbss = false;
++ list_for_each_entry(vif_walk, &cfg->vif_list, list) {
++ if (vif_walk->wdev.iftype == NL80211_IFTYPE_AP) {
++ mbss = true;
++ break;
++ }
++ }
++ vif->mbss = mbss;
++ }
++
++ list_add_tail(&vif->list, &cfg->vif_list);
++ return vif;
++}
++
++void brcmf_free_vif(struct brcmf_cfg80211_vif *vif)
++{
++ list_del(&vif->list);
++ kfree(vif);
++}
++
++void brcmf_cfg80211_free_netdev(struct net_device *ndev)
++{
++ struct brcmf_cfg80211_vif *vif;
++ struct brcmf_if *ifp;
++
++ ifp = netdev_priv(ndev);
++ vif = ifp->vif;
++
++ brcmf_free_vif(vif);
++ free_netdev(ndev);
++}
++
++static bool brcmf_is_linkup(const struct brcmf_event_msg *e)
++{
++ u32 event = e->event_code;
++ u32 status = e->status;
++
++ if (event == BRCMF_E_SET_SSID && status == BRCMF_E_STATUS_SUCCESS) {
++ brcmf_dbg(CONN, "Processing set ssid\n");
++ return true;
++ }
++
++ return false;
++}
++
++static bool brcmf_is_linkdown(const struct brcmf_event_msg *e)
++{
++ u32 event = e->event_code;
++ u16 flags = e->flags;
++
++ if ((event == BRCMF_E_DEAUTH) || (event == BRCMF_E_DEAUTH_IND) ||
++ (event == BRCMF_E_DISASSOC_IND) ||
++ ((event == BRCMF_E_LINK) && (!(flags & BRCMF_EVENT_MSG_LINK)))) {
++ brcmf_dbg(CONN, "Processing link down\n");
++ return true;
++ }
++ return false;
++}
++
++static bool brcmf_is_nonetwork(struct brcmf_cfg80211_info *cfg,
++ const struct brcmf_event_msg *e)
++{
++ u32 event = e->event_code;
++ u32 status = e->status;
++
++ if (event == BRCMF_E_LINK && status == BRCMF_E_STATUS_NO_NETWORKS) {
++ brcmf_dbg(CONN, "Processing Link %s & no network found\n",
++ e->flags & BRCMF_EVENT_MSG_LINK ? "up" : "down");
++ return true;
++ }
++
++ if (event == BRCMF_E_SET_SSID && status != BRCMF_E_STATUS_SUCCESS) {
++ brcmf_dbg(CONN, "Processing connecting & no network found\n");
++ return true;
++ }
++
++ return false;
++}
++
++static void brcmf_clear_assoc_ies(struct brcmf_cfg80211_info *cfg)
++{
++ struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
++
++ kfree(conn_info->req_ie);
++ conn_info->req_ie = NULL;
++ conn_info->req_ie_len = 0;
++ kfree(conn_info->resp_ie);
++ conn_info->resp_ie = NULL;
++ conn_info->resp_ie_len = 0;
++}
++
++static s32 brcmf_get_assoc_ies(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_if *ifp)
++{
++ struct brcmf_cfg80211_assoc_ielen_le *assoc_info;
++ struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
++ u32 req_len;
++ u32 resp_len;
++ s32 err = 0;
++
++ brcmf_clear_assoc_ies(cfg);
++
++ err = brcmf_fil_iovar_data_get(ifp, "assoc_info",
++ cfg->extra_buf, WL_ASSOC_INFO_MAX);
++ if (err) {
++ brcmf_err("could not get assoc info (%d)\n", err);
++ return err;
++ }
++ assoc_info =
++ (struct brcmf_cfg80211_assoc_ielen_le *)cfg->extra_buf;
++ req_len = le32_to_cpu(assoc_info->req_len);
++ resp_len = le32_to_cpu(assoc_info->resp_len);
++ if (req_len) {
++ err = brcmf_fil_iovar_data_get(ifp, "assoc_req_ies",
++ cfg->extra_buf,
++ WL_ASSOC_INFO_MAX);
++ if (err) {
++ brcmf_err("could not get assoc req (%d)\n", err);
++ return err;
++ }
++ conn_info->req_ie_len = req_len;
++ conn_info->req_ie =
++ kmemdup(cfg->extra_buf, conn_info->req_ie_len,
++ GFP_KERNEL);
++ } else {
++ conn_info->req_ie_len = 0;
++ conn_info->req_ie = NULL;
++ }
++ if (resp_len) {
++ err = brcmf_fil_iovar_data_get(ifp, "assoc_resp_ies",
++ cfg->extra_buf,
++ WL_ASSOC_INFO_MAX);
++ if (err) {
++ brcmf_err("could not get assoc resp (%d)\n", err);
++ return err;
++ }
++ conn_info->resp_ie_len = resp_len;
++ conn_info->resp_ie =
++ kmemdup(cfg->extra_buf, conn_info->resp_ie_len,
++ GFP_KERNEL);
++ } else {
++ conn_info->resp_ie_len = 0;
++ conn_info->resp_ie = NULL;
++ }
++ brcmf_dbg(CONN, "req len (%d) resp len (%d)\n",
++ conn_info->req_ie_len, conn_info->resp_ie_len);
++
++ return err;
++}
++
++static s32
++brcmf_bss_roaming_done(struct brcmf_cfg80211_info *cfg,
++ struct net_device *ndev,
++ const struct brcmf_event_msg *e)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
++ struct wiphy *wiphy = cfg_to_wiphy(cfg);
++ struct ieee80211_channel *notify_channel = NULL;
++ struct ieee80211_supported_band *band;
++ struct brcmf_bss_info_le *bi;
++ struct brcmu_chan ch;
++ u32 freq;
++ s32 err = 0;
++ u8 *buf;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ brcmf_get_assoc_ies(cfg, ifp);
++ memcpy(profile->bssid, e->addr, ETH_ALEN);
++ brcmf_update_bss_info(cfg, ifp);
++
++ buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
++ if (buf == NULL) {
++ err = -ENOMEM;
++ goto done;
++ }
++
++ /* data sent to dongle has to be little endian */
++ *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
++ err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSS_INFO,
++ buf, WL_BSS_INFO_MAX);
++
++ if (err)
++ goto done;
++
++ bi = (struct brcmf_bss_info_le *)(buf + 4);
++ ch.chspec = le16_to_cpu(bi->chanspec);
++ cfg->d11inf.decchspec(&ch);
++
++ if (ch.band == BRCMU_CHAN_BAND_2G)
++ band = wiphy->bands[IEEE80211_BAND_2GHZ];
++ else
++ band = wiphy->bands[IEEE80211_BAND_5GHZ];
++
++ freq = ieee80211_channel_to_frequency(ch.chnum, band->band);
++ notify_channel = ieee80211_get_channel(wiphy, freq);
++
++done:
++ kfree(buf);
++ cfg80211_roamed(ndev, notify_channel, (u8 *)profile->bssid,
++ conn_info->req_ie, conn_info->req_ie_len,
++ conn_info->resp_ie, conn_info->resp_ie_len, GFP_KERNEL);
++ brcmf_dbg(CONN, "Report roaming result\n");
++
++ set_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state);
++ brcmf_dbg(TRACE, "Exit\n");
++ return err;
++}
++
++static s32
++brcmf_bss_connect_done(struct brcmf_cfg80211_info *cfg,
++ struct net_device *ndev, const struct brcmf_event_msg *e,
++ bool completed)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (test_and_clear_bit(BRCMF_VIF_STATUS_CONNECTING,
++ &ifp->vif->sme_state)) {
++ if (completed) {
++ brcmf_get_assoc_ies(cfg, ifp);
++ memcpy(profile->bssid, e->addr, ETH_ALEN);
++ brcmf_update_bss_info(cfg, ifp);
++ set_bit(BRCMF_VIF_STATUS_CONNECTED,
++ &ifp->vif->sme_state);
++ }
++ cfg80211_connect_result(ndev,
++ (u8 *)profile->bssid,
++ conn_info->req_ie,
++ conn_info->req_ie_len,
++ conn_info->resp_ie,
++ conn_info->resp_ie_len,
++ completed ? WLAN_STATUS_SUCCESS :
++ WLAN_STATUS_AUTH_TIMEOUT,
++ GFP_KERNEL);
++ brcmf_dbg(CONN, "Report connect result - connection %s\n",
++ completed ? "succeeded" : "failed");
++ }
++ brcmf_dbg(TRACE, "Exit\n");
++ return 0;
++}
++
++static s32
++brcmf_notify_connect_status_ap(struct brcmf_cfg80211_info *cfg,
++ struct net_device *ndev,
++ const struct brcmf_event_msg *e, void *data)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ static int generation;
++ u32 event = e->event_code;
++ u32 reason = e->reason;
++ struct station_info sinfo;
++
++ brcmf_dbg(CONN, "event %d, reason %d\n", event, reason);
++ if (event == BRCMF_E_LINK && reason == BRCMF_E_REASON_LINK_BSSCFG_DIS &&
++ ndev != cfg_to_ndev(cfg)) {
++ brcmf_dbg(CONN, "AP mode link down\n");
++ complete(&cfg->vif_disabled);
++ if (ifp->vif->mbss)
++ brcmf_remove_interface(ifp->drvr, ifp->bssidx);
++ return 0;
++ }
++
++ if (((event == BRCMF_E_ASSOC_IND) || (event == BRCMF_E_REASSOC_IND)) &&
++ (reason == BRCMF_E_STATUS_SUCCESS)) {
++ memset(&sinfo, 0, sizeof(sinfo));
++ sinfo.filled = STATION_INFO_ASSOC_REQ_IES;
++ if (!data) {
++ brcmf_err("No IEs present in ASSOC/REASSOC_IND");
++ return -EINVAL;
++ }
++ sinfo.assoc_req_ies = data;
++ sinfo.assoc_req_ies_len = e->datalen;
++ generation++;
++ sinfo.generation = generation;
++ cfg80211_new_sta(ndev, e->addr, &sinfo, GFP_KERNEL);
++ } else if ((event == BRCMF_E_DISASSOC_IND) ||
++ (event == BRCMF_E_DEAUTH_IND) ||
++ (event == BRCMF_E_DEAUTH)) {
++ cfg80211_del_sta(ndev, e->addr, GFP_KERNEL);
++ }
++ return 0;
++}
++
++static s32
++brcmf_notify_connect_status(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e, void *data)
++{
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++ struct net_device *ndev = ifp->ndev;
++ struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
++ struct ieee80211_channel *chan;
++ s32 err = 0;
++
++ if ((e->event_code == BRCMF_E_DEAUTH) ||
++ (e->event_code == BRCMF_E_DEAUTH_IND) ||
++ (e->event_code == BRCMF_E_DISASSOC_IND) ||
++ ((e->event_code == BRCMF_E_LINK) && (!e->flags))) {
++ brcmf_proto_delete_peer(ifp->drvr, ifp->ifidx, (u8 *)e->addr);
++ }
++
++ if (brcmf_is_apmode(ifp->vif)) {
++ err = brcmf_notify_connect_status_ap(cfg, ndev, e, data);
++ } else if (brcmf_is_linkup(e)) {
++ brcmf_dbg(CONN, "Linkup\n");
++ if (brcmf_is_ibssmode(ifp->vif)) {
++ chan = ieee80211_get_channel(cfg->wiphy, cfg->channel);
++ memcpy(profile->bssid, e->addr, ETH_ALEN);
++ wl_inform_ibss(cfg, ndev, e->addr);
++ cfg80211_ibss_joined(ndev, e->addr, chan, GFP_KERNEL);
++ clear_bit(BRCMF_VIF_STATUS_CONNECTING,
++ &ifp->vif->sme_state);
++ set_bit(BRCMF_VIF_STATUS_CONNECTED,
++ &ifp->vif->sme_state);
++ } else
++ brcmf_bss_connect_done(cfg, ndev, e, true);
++ } else if (brcmf_is_linkdown(e)) {
++ brcmf_dbg(CONN, "Linkdown\n");
++ if (!brcmf_is_ibssmode(ifp->vif)) {
++ brcmf_bss_connect_done(cfg, ndev, e, false);
++ }
++ brcmf_link_down(ifp->vif, brcmf_map_fw_linkdown_reason(e));
++ brcmf_init_prof(ndev_to_prof(ndev));
++ if (ndev != cfg_to_ndev(cfg))
++ complete(&cfg->vif_disabled);
++ } else if (brcmf_is_nonetwork(cfg, e)) {
++ if (brcmf_is_ibssmode(ifp->vif))
++ clear_bit(BRCMF_VIF_STATUS_CONNECTING,
++ &ifp->vif->sme_state);
++ else
++ brcmf_bss_connect_done(cfg, ndev, e, false);
++ }
++
++ return err;
++}
++
++static s32
++brcmf_notify_roaming_status(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e, void *data)
++{
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++ u32 event = e->event_code;
++ u32 status = e->status;
++
++ if (event == BRCMF_E_ROAM && status == BRCMF_E_STATUS_SUCCESS) {
++ if (test_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state))
++ brcmf_bss_roaming_done(cfg, ifp->ndev, e);
++ else
++ brcmf_bss_connect_done(cfg, ifp->ndev, e, true);
++ }
++
++ return 0;
++}
++
++static s32
++brcmf_notify_mic_status(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e, void *data)
++{
++ u16 flags = e->flags;
++ enum nl80211_key_type key_type;
++
++ if (flags & BRCMF_EVENT_MSG_GROUP)
++ key_type = NL80211_KEYTYPE_GROUP;
++ else
++ key_type = NL80211_KEYTYPE_PAIRWISE;
++
++ cfg80211_michael_mic_failure(ifp->ndev, (u8 *)&e->addr, key_type, -1,
++ NULL, GFP_KERNEL);
++
++ return 0;
++}
++
++static s32 brcmf_notify_vif_event(struct brcmf_if *ifp,
++ const struct brcmf_event_msg *e, void *data)
++{
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++ struct brcmf_if_event *ifevent = (struct brcmf_if_event *)data;
++ struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
++ struct brcmf_cfg80211_vif *vif;
++
++ brcmf_dbg(TRACE, "Enter: action %u flags %u ifidx %u bsscfg %u\n",
++ ifevent->action, ifevent->flags, ifevent->ifidx,
++ ifevent->bssidx);
++
++ mutex_lock(&event->vif_event_lock);
++ event->action = ifevent->action;
++ vif = event->vif;
++
++ switch (ifevent->action) {
++ case BRCMF_E_IF_ADD:
++ /* waiting process may have timed out */
++ if (!cfg->vif_event.vif) {
++ mutex_unlock(&event->vif_event_lock);
++ return -EBADF;
++ }
++
++ ifp->vif = vif;
++ vif->ifp = ifp;
++ if (ifp->ndev) {
++ vif->wdev.netdev = ifp->ndev;
++ ifp->ndev->ieee80211_ptr = &vif->wdev;
++ SET_NETDEV_DEV(ifp->ndev, wiphy_dev(cfg->wiphy));
++ }
++ mutex_unlock(&event->vif_event_lock);
++ wake_up(&event->vif_wq);
++ return 0;
++
++ case BRCMF_E_IF_DEL:
++ mutex_unlock(&event->vif_event_lock);
++ /* event may not be upon user request */
++ if (brcmf_cfg80211_vif_event_armed(cfg))
++ wake_up(&event->vif_wq);
++ return 0;
++
++ case BRCMF_E_IF_CHANGE:
++ mutex_unlock(&event->vif_event_lock);
++ wake_up(&event->vif_wq);
++ return 0;
++
++ default:
++ mutex_unlock(&event->vif_event_lock);
++ break;
++ }
++ return -EINVAL;
++}
++
++static void brcmf_init_conf(struct brcmf_cfg80211_conf *conf)
++{
++ conf->frag_threshold = (u32)-1;
++ conf->rts_threshold = (u32)-1;
++ conf->retry_short = (u32)-1;
++ conf->retry_long = (u32)-1;
++ conf->tx_power = -1;
++}
++
++static void brcmf_register_event_handlers(struct brcmf_cfg80211_info *cfg)
++{
++ brcmf_fweh_register(cfg->pub, BRCMF_E_LINK,
++ brcmf_notify_connect_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_DEAUTH_IND,
++ brcmf_notify_connect_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_DEAUTH,
++ brcmf_notify_connect_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_DISASSOC_IND,
++ brcmf_notify_connect_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_ASSOC_IND,
++ brcmf_notify_connect_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_REASSOC_IND,
++ brcmf_notify_connect_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_ROAM,
++ brcmf_notify_roaming_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_MIC_ERROR,
++ brcmf_notify_mic_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_SET_SSID,
++ brcmf_notify_connect_status);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_PFN_NET_FOUND,
++ brcmf_notify_sched_scan_results);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_IF,
++ brcmf_notify_vif_event);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_P2P_PROBEREQ_MSG,
++ brcmf_p2p_notify_rx_mgmt_p2p_probereq);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_P2P_DISC_LISTEN_COMPLETE,
++ brcmf_p2p_notify_listen_complete);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_ACTION_FRAME_RX,
++ brcmf_p2p_notify_action_frame_rx);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_ACTION_FRAME_COMPLETE,
++ brcmf_p2p_notify_action_tx_complete);
++ brcmf_fweh_register(cfg->pub, BRCMF_E_ACTION_FRAME_OFF_CHAN_COMPLETE,
++ brcmf_p2p_notify_action_tx_complete);
++}
++
++static void brcmf_deinit_priv_mem(struct brcmf_cfg80211_info *cfg)
++{
++ kfree(cfg->conf);
++ cfg->conf = NULL;
++ kfree(cfg->escan_ioctl_buf);
++ cfg->escan_ioctl_buf = NULL;
++ kfree(cfg->extra_buf);
++ cfg->extra_buf = NULL;
++ kfree(cfg->pmk_list);
++ cfg->pmk_list = NULL;
++}
++
++static s32 brcmf_init_priv_mem(struct brcmf_cfg80211_info *cfg)
++{
++ cfg->conf = kzalloc(sizeof(*cfg->conf), GFP_KERNEL);
++ if (!cfg->conf)
++ goto init_priv_mem_out;
++ cfg->escan_ioctl_buf = kzalloc(BRCMF_DCMD_MEDLEN, GFP_KERNEL);
++ if (!cfg->escan_ioctl_buf)
++ goto init_priv_mem_out;
++ cfg->extra_buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
++ if (!cfg->extra_buf)
++ goto init_priv_mem_out;
++ cfg->pmk_list = kzalloc(sizeof(*cfg->pmk_list), GFP_KERNEL);
++ if (!cfg->pmk_list)
++ goto init_priv_mem_out;
++
++ return 0;
++
++init_priv_mem_out:
++ brcmf_deinit_priv_mem(cfg);
++
++ return -ENOMEM;
++}
++
++static s32 wl_init_priv(struct brcmf_cfg80211_info *cfg)
++{
++ s32 err = 0;
++
++ cfg->scan_request = NULL;
++ cfg->pwr_save = true;
++ cfg->active_scan = true; /* we do active scan per default */
++ cfg->dongle_up = false; /* dongle is not up yet */
++ err = brcmf_init_priv_mem(cfg);
++ if (err)
++ return err;
++ brcmf_register_event_handlers(cfg);
++ mutex_init(&cfg->usr_sync);
++ brcmf_init_escan(cfg);
++ brcmf_init_conf(cfg->conf);
++ init_completion(&cfg->vif_disabled);
++ return err;
++}
++
++static void wl_deinit_priv(struct brcmf_cfg80211_info *cfg)
++{
++ cfg->dongle_up = false; /* dongle down */
++ brcmf_abort_scanning(cfg);
++ brcmf_deinit_priv_mem(cfg);
++}
++
++static void init_vif_event(struct brcmf_cfg80211_vif_event *event)
++{
++ init_waitqueue_head(&event->vif_wq);
++ mutex_init(&event->vif_event_lock);
++}
++
++static s32
++brcmf_dongle_roam(struct brcmf_if *ifp, u32 bcn_timeout)
++{
++ s32 err = 0;
++ __le32 roamtrigger[2];
++ __le32 roam_delta[2];
++
++ /*
++ * Setup timeout if Beacons are lost and roam is
++ * off to report link down
++ */
++ if (brcmf_roamoff) {
++ err = brcmf_fil_iovar_int_set(ifp, "bcn_timeout", bcn_timeout);
++ if (err) {
++ brcmf_err("bcn_timeout error (%d)\n", err);
++ goto dongle_rom_out;
++ }
++ }
++
++ /*
++ * Enable/Disable built-in roaming to allow supplicant
++ * to take care of roaming
++ */
++ brcmf_dbg(INFO, "Internal Roaming = %s\n",
++ brcmf_roamoff ? "Off" : "On");
++ err = brcmf_fil_iovar_int_set(ifp, "roam_off", !!(brcmf_roamoff));
++ if (err) {
++ brcmf_err("roam_off error (%d)\n", err);
++ goto dongle_rom_out;
++ }
++
++ roamtrigger[0] = cpu_to_le32(WL_ROAM_TRIGGER_LEVEL);
++ roamtrigger[1] = cpu_to_le32(BRCM_BAND_ALL);
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_ROAM_TRIGGER,
++ (void *)roamtrigger, sizeof(roamtrigger));
++ if (err) {
++ brcmf_err("WLC_SET_ROAM_TRIGGER error (%d)\n", err);
++ goto dongle_rom_out;
++ }
++
++ roam_delta[0] = cpu_to_le32(WL_ROAM_DELTA);
++ roam_delta[1] = cpu_to_le32(BRCM_BAND_ALL);
++ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_ROAM_DELTA,
++ (void *)roam_delta, sizeof(roam_delta));
++ if (err) {
++ brcmf_err("WLC_SET_ROAM_DELTA error (%d)\n", err);
++ goto dongle_rom_out;
++ }
++
++dongle_rom_out:
++ return err;
++}
++
++static s32
++brcmf_dongle_scantime(struct brcmf_if *ifp, s32 scan_assoc_time,
++ s32 scan_unassoc_time, s32 scan_passive_time)
++{
++ s32 err = 0;
++
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_CHANNEL_TIME,
++ scan_assoc_time);
++ if (err) {
++ if (err == -EOPNOTSUPP)
++ brcmf_dbg(INFO, "Scan assoc time is not supported\n");
++ else
++ brcmf_err("Scan assoc time error (%d)\n", err);
++ goto dongle_scantime_out;
++ }
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_UNASSOC_TIME,
++ scan_unassoc_time);
++ if (err) {
++ if (err == -EOPNOTSUPP)
++ brcmf_dbg(INFO, "Scan unassoc time is not supported\n");
++ else
++ brcmf_err("Scan unassoc time error (%d)\n", err);
++ goto dongle_scantime_out;
++ }
++
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_PASSIVE_TIME,
++ scan_passive_time);
++ if (err) {
++ if (err == -EOPNOTSUPP)
++ brcmf_dbg(INFO, "Scan passive time is not supported\n");
++ else
++ brcmf_err("Scan passive time error (%d)\n", err);
++ goto dongle_scantime_out;
++ }
++
++dongle_scantime_out:
++ return err;
++}
++
++static void brcmf_update_bw40_channel_flag(struct ieee80211_channel *channel,
++ struct brcmu_chan *ch)
++{
++ u32 ht40_flag;
++
++ ht40_flag = channel->flags & IEEE80211_CHAN_NO_HT40;
++ if (ch->sb == BRCMU_CHAN_SB_U) {
++ if (ht40_flag == IEEE80211_CHAN_NO_HT40)
++ channel->flags &= ~IEEE80211_CHAN_NO_HT40;
++ channel->flags |= IEEE80211_CHAN_NO_HT40PLUS;
++ } else {
++ /* It should be one of
++ * IEEE80211_CHAN_NO_HT40 or
++ * IEEE80211_CHAN_NO_HT40PLUS
++ */
++ channel->flags &= ~IEEE80211_CHAN_NO_HT40;
++ if (ht40_flag == IEEE80211_CHAN_NO_HT40)
++ channel->flags |= IEEE80211_CHAN_NO_HT40MINUS;
++ }
++}
++
++static int brcmf_construct_chaninfo(struct brcmf_cfg80211_info *cfg,
++ u32 bw_cap[])
++{
++ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
++ struct ieee80211_supported_band *band;
++ struct ieee80211_channel *channel;
++ struct wiphy *wiphy;
++ struct brcmf_chanspec_list *list;
++ struct brcmu_chan ch;
++ int err;
++ u8 *pbuf;
++ u32 i, j;
++ u32 total;
++ u32 chaninfo;
++ u32 index;
++
++ pbuf = kzalloc(BRCMF_DCMD_MEDLEN, GFP_KERNEL);
++
++ if (pbuf == NULL)
++ return -ENOMEM;
++
++ list = (struct brcmf_chanspec_list *)pbuf;
++
++ err = brcmf_fil_iovar_data_get(ifp, "chanspecs", pbuf,
++ BRCMF_DCMD_MEDLEN);
++ if (err) {
++ brcmf_err("get chanspecs error (%d)\n", err);
++ goto fail_pbuf;
++ }
++
++ wiphy = cfg_to_wiphy(cfg);
++ band = wiphy->bands[IEEE80211_BAND_2GHZ];
++ if (band)
++ for (i = 0; i < band->n_channels; i++)
++ band->channels[i].flags = IEEE80211_CHAN_DISABLED;
++ band = wiphy->bands[IEEE80211_BAND_5GHZ];
++ if (band)
++ for (i = 0; i < band->n_channels; i++)
++ band->channels[i].flags = IEEE80211_CHAN_DISABLED;
++
++ total = le32_to_cpu(list->count);
++ for (i = 0; i < total; i++) {
++ ch.chspec = (u16)le32_to_cpu(list->element[i]);
++ cfg->d11inf.decchspec(&ch);
++
++ if (ch.band == BRCMU_CHAN_BAND_2G) {
++ band = wiphy->bands[IEEE80211_BAND_2GHZ];
++ } else if (ch.band == BRCMU_CHAN_BAND_5G) {
++ band = wiphy->bands[IEEE80211_BAND_5GHZ];
++ } else {
++ brcmf_err("Invalid channel Spec. 0x%x.\n", ch.chspec);
++ continue;
++ }
++ if (!band)
++ continue;
++ if (!(bw_cap[band->band] & WLC_BW_40MHZ_BIT) &&
++ ch.bw == BRCMU_CHAN_BW_40)
++ continue;
++ if (!(bw_cap[band->band] & WLC_BW_80MHZ_BIT) &&
++ ch.bw == BRCMU_CHAN_BW_80)
++ continue;
++
++ channel = band->channels;
++ index = band->n_channels;
++ for (j = 0; j < band->n_channels; j++) {
++ if (channel[j].hw_value == ch.chnum) {
++ index = j;
++ break;
++ }
++ }
++ channel[index].center_freq =
++ ieee80211_channel_to_frequency(ch.chnum, band->band);
++ channel[index].hw_value = ch.chnum;
++
++ /* assuming the chanspecs order is HT20,
++ * HT40 upper, HT40 lower, and VHT80.
++ */
++ if (ch.bw == BRCMU_CHAN_BW_80) {
++ channel[index].flags &= ~IEEE80211_CHAN_NO_80MHZ;
++ } else if (ch.bw == BRCMU_CHAN_BW_40) {
++ brcmf_update_bw40_channel_flag(&channel[index], &ch);
++ } else {
++ /* enable the channel and disable other bandwidths
++ * for now as mentioned order assure they are enabled
++ * for subsequent chanspecs.
++ */
++ channel[index].flags = IEEE80211_CHAN_NO_HT40 |
++ IEEE80211_CHAN_NO_80MHZ;
++ ch.bw = BRCMU_CHAN_BW_20;
++ cfg->d11inf.encchspec(&ch);
++ chaninfo = ch.chspec;
++ err = brcmf_fil_bsscfg_int_get(ifp, "per_chan_info",
++ &chaninfo);
++ if (!err) {
++ if (chaninfo & WL_CHAN_RADAR)
++ channel[index].flags |=
++ (IEEE80211_CHAN_RADAR |
++ IEEE80211_CHAN_NO_IR);
++ if (chaninfo & WL_CHAN_PASSIVE)
++ channel[index].flags |=
++ IEEE80211_CHAN_NO_IR;
++ }
++ }
++ }
++
++fail_pbuf:
++ kfree(pbuf);
++ return err;
++}
++
++static int brcmf_enable_bw40_2g(struct brcmf_cfg80211_info *cfg)
++{
++ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
++ struct ieee80211_supported_band *band;
++ struct brcmf_fil_bwcap_le band_bwcap;
++ struct brcmf_chanspec_list *list;
++ u8 *pbuf;
++ u32 val;
++ int err;
++ struct brcmu_chan ch;
++ u32 num_chan;
++ int i, j;
++
++ /* verify support for bw_cap command */
++ val = WLC_BAND_5G;
++ err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &val);
++
++ if (!err) {
++ /* only set 2G bandwidth using bw_cap command */
++ band_bwcap.band = cpu_to_le32(WLC_BAND_2G);
++ band_bwcap.bw_cap = cpu_to_le32(WLC_BW_CAP_40MHZ);
++ err = brcmf_fil_iovar_data_set(ifp, "bw_cap", &band_bwcap,
++ sizeof(band_bwcap));
++ } else {
++ brcmf_dbg(INFO, "fallback to mimo_bw_cap\n");
++ val = WLC_N_BW_40ALL;
++ err = brcmf_fil_iovar_int_set(ifp, "mimo_bw_cap", val);
++ }
++
++ if (!err) {
++ /* update channel info in 2G band */
++ pbuf = kzalloc(BRCMF_DCMD_MEDLEN, GFP_KERNEL);
++
++ if (pbuf == NULL)
++ return -ENOMEM;
++
++ ch.band = BRCMU_CHAN_BAND_2G;
++ ch.bw = BRCMU_CHAN_BW_40;
++ ch.sb = BRCMU_CHAN_SB_NONE;
++ ch.chnum = 0;
++ cfg->d11inf.encchspec(&ch);
++
++ /* pass encoded chanspec in query */
++ *(__le16 *)pbuf = cpu_to_le16(ch.chspec);
++
++ err = brcmf_fil_iovar_data_get(ifp, "chanspecs", pbuf,
++ BRCMF_DCMD_MEDLEN);
++ if (err) {
++ brcmf_err("get chanspecs error (%d)\n", err);
++ kfree(pbuf);
++ return err;
++ }
++
++ band = cfg_to_wiphy(cfg)->bands[IEEE80211_BAND_2GHZ];
++ list = (struct brcmf_chanspec_list *)pbuf;
++ num_chan = le32_to_cpu(list->count);
++ for (i = 0; i < num_chan; i++) {
++ ch.chspec = (u16)le32_to_cpu(list->element[i]);
++ cfg->d11inf.decchspec(&ch);
++ if (WARN_ON(ch.band != BRCMU_CHAN_BAND_2G))
++ continue;
++ if (WARN_ON(ch.bw != BRCMU_CHAN_BW_40))
++ continue;
++ for (j = 0; j < band->n_channels; j++) {
++ if (band->channels[j].hw_value == ch.chnum)
++ break;
++ }
++ if (WARN_ON(j == band->n_channels))
++ continue;
++
++ brcmf_update_bw40_channel_flag(&band->channels[j], &ch);
++ }
++ kfree(pbuf);
++ }
++ return err;
++}
++
++static void brcmf_get_bwcap(struct brcmf_if *ifp, u32 bw_cap[])
++{
++ u32 band, mimo_bwcap;
++ int err;
++
++ band = WLC_BAND_2G;
++ err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
++ if (!err) {
++ bw_cap[IEEE80211_BAND_2GHZ] = band;
++ band = WLC_BAND_5G;
++ err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
++ if (!err) {
++ bw_cap[IEEE80211_BAND_5GHZ] = band;
++ return;
++ }
++ WARN_ON(1);
++ return;
++ }
++ brcmf_dbg(INFO, "fallback to mimo_bw_cap info\n");
++ mimo_bwcap = 0;
++ err = brcmf_fil_iovar_int_get(ifp, "mimo_bw_cap", &mimo_bwcap);
++ if (err)
++ /* assume 20MHz if firmware does not give a clue */
++ mimo_bwcap = WLC_N_BW_20ALL;
++
++ switch (mimo_bwcap) {
++ case WLC_N_BW_40ALL:
++ bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_40MHZ_BIT;
++ /* fall-thru */
++ case WLC_N_BW_20IN2G_40IN5G:
++ bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_40MHZ_BIT;
++ /* fall-thru */
++ case WLC_N_BW_20ALL:
++ bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_20MHZ_BIT;
++ bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_20MHZ_BIT;
++ break;
++ default:
++ brcmf_err("invalid mimo_bw_cap value\n");
++ }
++}
++
++static void brcmf_update_ht_cap(struct ieee80211_supported_band *band,
++ u32 bw_cap[2], u32 nchain)
++{
++ band->ht_cap.ht_supported = true;
++ if (bw_cap[band->band] & WLC_BW_40MHZ_BIT) {
++ band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
++ band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
++ }
++ band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
++ band->ht_cap.cap |= IEEE80211_HT_CAP_DSSSCCK40;
++ band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
++ band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
++ memset(band->ht_cap.mcs.rx_mask, 0xff, nchain);
++ band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
++}
++
++static __le16 brcmf_get_mcs_map(u32 nchain, enum ieee80211_vht_mcs_support supp)
++{
++ u16 mcs_map;
++ int i;
++
++ for (i = 0, mcs_map = 0xFFFF; i < nchain; i++)
++ mcs_map = (mcs_map << 2) | supp;
++
++ return cpu_to_le16(mcs_map);
++}
++
++static void brcmf_update_vht_cap(struct ieee80211_supported_band *band,
++ u32 bw_cap[2], u32 nchain)
++{
++ __le16 mcs_map;
++
++ /* not allowed in 2.4G band */
++ if (band->band == IEEE80211_BAND_2GHZ)
++ return;
++
++ band->vht_cap.vht_supported = true;
++ /* 80MHz is mandatory */
++ band->vht_cap.cap |= IEEE80211_VHT_CAP_SHORT_GI_80;
++ if (bw_cap[band->band] & WLC_BW_160MHZ_BIT) {
++ band->vht_cap.cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
++ band->vht_cap.cap |= IEEE80211_VHT_CAP_SHORT_GI_160;
++ }
++ /* all support 256-QAM */
++ mcs_map = brcmf_get_mcs_map(nchain, IEEE80211_VHT_MCS_SUPPORT_0_9);
++ band->vht_cap.vht_mcs.rx_mcs_map = mcs_map;
++ band->vht_cap.vht_mcs.tx_mcs_map = mcs_map;
++}
++
++static int brcmf_setup_wiphybands(struct wiphy *wiphy)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
++ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
++ u32 nmode = 0;
++ u32 vhtmode = 0;
++ u32 bw_cap[2] = { WLC_BW_20MHZ_BIT, WLC_BW_20MHZ_BIT };
++ u32 rxchain;
++ u32 nchain;
++ int err;
++ s32 i;
++ struct ieee80211_supported_band *band;
++
++ (void)brcmf_fil_iovar_int_get(ifp, "vhtmode", &vhtmode);
++ err = brcmf_fil_iovar_int_get(ifp, "nmode", &nmode);
++ if (err) {
++ brcmf_err("nmode error (%d)\n", err);
++ } else {
++ brcmf_get_bwcap(ifp, bw_cap);
++ }
++ brcmf_dbg(INFO, "nmode=%d, vhtmode=%d, bw_cap=(%d, %d)\n",
++ nmode, vhtmode, bw_cap[IEEE80211_BAND_2GHZ],
++ bw_cap[IEEE80211_BAND_5GHZ]);
++
++ err = brcmf_fil_iovar_int_get(ifp, "rxchain", &rxchain);
++ if (err) {
++ brcmf_err("rxchain error (%d)\n", err);
++ nchain = 1;
++ } else {
++ for (nchain = 0; rxchain; nchain++)
++ rxchain = rxchain & (rxchain - 1);
++ }
++ brcmf_dbg(INFO, "nchain=%d\n", nchain);
++
++ err = brcmf_construct_chaninfo(cfg, bw_cap);
++ if (err) {
++ brcmf_err("brcmf_construct_chaninfo failed (%d)\n", err);
++ return err;
++ }
++
++ wiphy = cfg_to_wiphy(cfg);
++ for (i = 0; i < ARRAY_SIZE(wiphy->bands); i++) {
++ band = wiphy->bands[i];
++ if (band == NULL)
++ continue;
++
++ if (nmode)
++ brcmf_update_ht_cap(band, bw_cap, nchain);
++ if (vhtmode)
++ brcmf_update_vht_cap(band, bw_cap, nchain);
++ }
++
++ return 0;
++}
++
++static const struct ieee80211_iface_limit brcmf_iface_limits_mbss[] = {
++ {
++ .max = 1,
++ .types = BIT(NL80211_IFTYPE_STATION) |
++ BIT(NL80211_IFTYPE_ADHOC)
++ },
++ {
++ .max = 4,
++ .types = BIT(NL80211_IFTYPE_AP)
++ },
++ {
++ .max = 1,
++ .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
++ BIT(NL80211_IFTYPE_P2P_GO)
++ },
++ {
++ .max = 1,
++ .types = BIT(NL80211_IFTYPE_P2P_DEVICE)
++ }
++};
++
++static const struct ieee80211_iface_limit brcmf_iface_limits_sbss[] = {
++ {
++ .max = 2,
++ .types = BIT(NL80211_IFTYPE_STATION) |
++ BIT(NL80211_IFTYPE_ADHOC) |
++ BIT(NL80211_IFTYPE_AP)
++ },
++ {
++ .max = 1,
++ .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
++ BIT(NL80211_IFTYPE_P2P_GO)
++ },
++ {
++ .max = 1,
++ .types = BIT(NL80211_IFTYPE_P2P_DEVICE)
++ }
++};
++static struct ieee80211_iface_combination brcmf_iface_combos[] = {
++ {
++ .max_interfaces = BRCMF_IFACE_MAX_CNT,
++ .num_different_channels = 1,
++ .n_limits = ARRAY_SIZE(brcmf_iface_limits_sbss),
++ .limits = brcmf_iface_limits_sbss,
++ }
++};
++
++static const struct ieee80211_txrx_stypes
++brcmf_txrx_stypes[NUM_NL80211_IFTYPES] = {
++ [NL80211_IFTYPE_STATION] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++ },
++ [NL80211_IFTYPE_P2P_CLIENT] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++ },
++ [NL80211_IFTYPE_P2P_GO] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
++ BIT(IEEE80211_STYPE_DISASSOC >> 4) |
++ BIT(IEEE80211_STYPE_AUTH >> 4) |
++ BIT(IEEE80211_STYPE_DEAUTH >> 4) |
++ BIT(IEEE80211_STYPE_ACTION >> 4)
++ },
++ [NL80211_IFTYPE_P2P_DEVICE] = {
++ .tx = 0xffff,
++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
++ }
++};
++
++static void brcmf_wiphy_pno_params(struct wiphy *wiphy)
++{
++ /* scheduled scan settings */
++ wiphy->max_sched_scan_ssids = BRCMF_PNO_MAX_PFN_COUNT;
++ wiphy->max_match_sets = BRCMF_PNO_MAX_PFN_COUNT;
++ wiphy->max_sched_scan_ie_len = BRCMF_SCAN_IE_LEN_MAX;
++ wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
++}
++
++#ifdef CONFIG_PM
++static const struct wiphy_wowlan_support brcmf_wowlan_support = {
++ .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT,
++ .n_patterns = BRCMF_WOWL_MAXPATTERNS,
++ .pattern_max_len = BRCMF_WOWL_MAXPATTERNSIZE,
++ .pattern_min_len = 1,
++ .max_pkt_offset = 1500,
++};
++#endif
++
++static void brcmf_wiphy_wowl_params(struct wiphy *wiphy)
++{
++#ifdef CONFIG_PM
++ /* wowl settings */
++ wiphy->wowlan = &brcmf_wowlan_support;
++#endif
++}
++
++static int brcmf_setup_wiphy(struct wiphy *wiphy, struct brcmf_if *ifp)
++{
++ struct ieee80211_supported_band *band;
++ struct ieee80211_iface_combination ifc_combo;
++ __le32 bandlist[3];
++ u32 n_bands;
++ int err, i;
++
++ wiphy->max_scan_ssids = WL_NUM_SCAN_MAX;
++ wiphy->max_scan_ie_len = BRCMF_SCAN_IE_LEN_MAX;
++ wiphy->max_num_pmkids = WL_NUM_PMKIDS_MAX;
++ wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
++ BIT(NL80211_IFTYPE_ADHOC) |
++ BIT(NL80211_IFTYPE_AP) |
++ BIT(NL80211_IFTYPE_P2P_CLIENT) |
++ BIT(NL80211_IFTYPE_P2P_GO) |
++ BIT(NL80211_IFTYPE_P2P_DEVICE);
++ /* need VSDB firmware feature for concurrent channels */
++ ifc_combo = brcmf_iface_combos[0];
++ if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_MCHAN))
++ ifc_combo.num_different_channels = 2;
++ if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_MBSS)) {
++ ifc_combo.n_limits = ARRAY_SIZE(brcmf_iface_limits_mbss),
++ ifc_combo.limits = brcmf_iface_limits_mbss;
++ }
++ wiphy->iface_combinations = kmemdup(&ifc_combo,
++ sizeof(ifc_combo),
++ GFP_KERNEL);
++ wiphy->n_iface_combinations = ARRAY_SIZE(brcmf_iface_combos);
++ wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
++ wiphy->cipher_suites = __wl_cipher_suites;
++ wiphy->n_cipher_suites = ARRAY_SIZE(__wl_cipher_suites);
++ wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT |
++ WIPHY_FLAG_OFFCHAN_TX |
++ WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
++ WIPHY_FLAG_SUPPORTS_TDLS;
++ if (!brcmf_roamoff)
++ wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM;
++ wiphy->mgmt_stypes = brcmf_txrx_stypes;
++ wiphy->max_remain_on_channel_duration = 5000;
++ if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_PNO))
++ brcmf_wiphy_pno_params(wiphy);
++
++ /* vendor commands/events support */
++ wiphy->vendor_commands = brcmf_vendor_cmds;
++ wiphy->n_vendor_commands = BRCMF_VNDR_CMDS_LAST - 1;
++
++ if (brcmf_feat_is_enabled(ifp, BRCMF_FEAT_WOWL))
++ brcmf_wiphy_wowl_params(wiphy);
++
++ err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BANDLIST, &bandlist,
++ sizeof(bandlist));
++ if (err) {
++ brcmf_err("could not obtain band info: err=%d\n", err);
++ return err;
++ }
++ /* first entry in bandlist is number of bands */
++ n_bands = le32_to_cpu(bandlist[0]);
++ for (i = 1; i <= n_bands && i < ARRAY_SIZE(bandlist); i++) {
++ if (bandlist[i] == cpu_to_le32(WLC_BAND_2G)) {
++ band = kmemdup(&__wl_band_2ghz, sizeof(__wl_band_2ghz),
++ GFP_KERNEL);
++ if (!band)
++ return -ENOMEM;
++
++ band->channels = kmemdup(&__wl_2ghz_channels,
++ sizeof(__wl_2ghz_channels),
++ GFP_KERNEL);
++ if (!band->channels) {
++ kfree(band);
++ return -ENOMEM;
++ }
++
++ band->n_channels = ARRAY_SIZE(__wl_2ghz_channels);
++ wiphy->bands[IEEE80211_BAND_2GHZ] = band;
++ }
++ if (bandlist[i] == cpu_to_le32(WLC_BAND_5G)) {
++ band = kmemdup(&__wl_band_5ghz, sizeof(__wl_band_5ghz),
++ GFP_KERNEL);
++ if (!band)
++ return -ENOMEM;
++
++ band->channels = kmemdup(&__wl_5ghz_channels,
++ sizeof(__wl_5ghz_channels),
++ GFP_KERNEL);
++ if (!band->channels) {
++ kfree(band);
++ return -ENOMEM;
++ }
++
++ band->n_channels = ARRAY_SIZE(__wl_5ghz_channels);
++ wiphy->bands[IEEE80211_BAND_5GHZ] = band;
++ }
++ }
++ err = brcmf_setup_wiphybands(wiphy);
++ return err;
++}
++
++static s32 brcmf_config_dongle(struct brcmf_cfg80211_info *cfg)
++{
++ struct net_device *ndev;
++ struct wireless_dev *wdev;
++ struct brcmf_if *ifp;
++ s32 power_mode;
++ s32 err = 0;
++
++ if (cfg->dongle_up)
++ return err;
++
++ ndev = cfg_to_ndev(cfg);
++ wdev = ndev->ieee80211_ptr;
++ ifp = netdev_priv(ndev);
++
++ /* make sure RF is ready for work */
++ brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 0);
++
++ brcmf_dongle_scantime(ifp, WL_SCAN_CHANNEL_TIME,
++ WL_SCAN_UNASSOC_TIME, WL_SCAN_PASSIVE_TIME);
++
++ power_mode = cfg->pwr_save ? PM_FAST : PM_OFF;
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, power_mode);
++ if (err)
++ goto default_conf_out;
++ brcmf_dbg(INFO, "power save set to %s\n",
++ (power_mode ? "enabled" : "disabled"));
++
++ err = brcmf_dongle_roam(ifp, WL_BEACON_TIMEOUT);
++ if (err)
++ goto default_conf_out;
++ err = brcmf_cfg80211_change_iface(wdev->wiphy, ndev, wdev->iftype,
++ NULL, NULL);
++ if (err)
++ goto default_conf_out;
++
++ brcmf_configure_arp_offload(ifp, true);
++
++ cfg->dongle_up = true;
++default_conf_out:
++
++ return err;
++
++}
++
++static s32 __brcmf_cfg80211_up(struct brcmf_if *ifp)
++{
++ set_bit(BRCMF_VIF_STATUS_READY, &ifp->vif->sme_state);
++
++ return brcmf_config_dongle(ifp->drvr->config);
++}
++
++static s32 __brcmf_cfg80211_down(struct brcmf_if *ifp)
++{
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++
++ /*
++ * While going down, if associated with AP disassociate
++ * from AP to save power
++ */
++ if (check_vif_up(ifp->vif)) {
++ brcmf_link_down(ifp->vif, WLAN_REASON_UNSPECIFIED);
++
++ /* Make sure WPA_Supplicant receives all the event
++ generated due to DISASSOC call to the fw to keep
++ the state fw and WPA_Supplicant state consistent
++ */
++ brcmf_delay(500);
++ }
++
++ brcmf_abort_scanning(cfg);
++ clear_bit(BRCMF_VIF_STATUS_READY, &ifp->vif->sme_state);
++
++ return 0;
++}
++
++s32 brcmf_cfg80211_up(struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++ s32 err = 0;
++
++ mutex_lock(&cfg->usr_sync);
++ err = __brcmf_cfg80211_up(ifp);
++ mutex_unlock(&cfg->usr_sync);
++
++ return err;
++}
++
++s32 brcmf_cfg80211_down(struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
++ s32 err = 0;
++
++ mutex_lock(&cfg->usr_sync);
++ err = __brcmf_cfg80211_down(ifp);
++ mutex_unlock(&cfg->usr_sync);
++
++ return err;
++}
++
++enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp)
++{
++ struct wireless_dev *wdev = &ifp->vif->wdev;
++
++ return wdev->iftype;
++}
++
++bool brcmf_get_vif_state_any(struct brcmf_cfg80211_info *cfg, unsigned long state)
++{
++ struct brcmf_cfg80211_vif *vif;
++
++ list_for_each_entry(vif, &cfg->vif_list, list) {
++ if (test_bit(state, &vif->sme_state))
++ return true;
++ }
++ return false;
++}
++
++static inline bool vif_event_equals(struct brcmf_cfg80211_vif_event *event,
++ u8 action)
++{
++ u8 evt_action;
++
++ mutex_lock(&event->vif_event_lock);
++ evt_action = event->action;
++ mutex_unlock(&event->vif_event_lock);
++ return evt_action == action;
++}
++
++void brcmf_cfg80211_arm_vif_event(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_cfg80211_vif *vif)
++{
++ struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
++
++ mutex_lock(&event->vif_event_lock);
++ event->vif = vif;
++ event->action = 0;
++ mutex_unlock(&event->vif_event_lock);
++}
++
++bool brcmf_cfg80211_vif_event_armed(struct brcmf_cfg80211_info *cfg)
++{
++ struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
++ bool armed;
++
++ mutex_lock(&event->vif_event_lock);
++ armed = event->vif != NULL;
++ mutex_unlock(&event->vif_event_lock);
++
++ return armed;
++}
++int brcmf_cfg80211_wait_vif_event_timeout(struct brcmf_cfg80211_info *cfg,
++ u8 action, ulong timeout)
++{
++ struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
++
++ return wait_event_timeout(event->vif_wq,
++ vif_event_equals(event, action), timeout);
++}
++
++static void brcmf_cfg80211_reg_notifier(struct wiphy *wiphy,
++ struct regulatory_request *req)
++{
++ struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
++ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
++ struct brcmf_fil_country_le ccreq;
++ int i;
++
++ brcmf_dbg(TRACE, "enter: initiator=%d, alpha=%c%c\n", req->initiator,
++ req->alpha2[0], req->alpha2[1]);
++
++ /* ignore non-ISO3166 country codes
++ * don't report an error on 00 the world roaming
++ * designator as the firmware don't support it
++ * but there is no reason to pass that info to userspace
++ */
++
++ if (req->alpha2[0] == '0' && req->alpha2[1] == '0')
++ return;
++
++ for (i = 0; i < sizeof(req->alpha2); i++)
++ if (req->alpha2[i] < 'A' || req->alpha2[i] > 'Z') {
++ brcmf_err("not a ISO3166 code\n");
++ return;
++ }
++ memset(&ccreq, 0, sizeof(ccreq));
++ ccreq.rev = cpu_to_le32(-1);
++ memcpy(ccreq.ccode, req->alpha2, sizeof(req->alpha2));
++ if (brcmf_fil_iovar_data_set(ifp, "country", &ccreq, sizeof(ccreq))) {
++ brcmf_err("firmware rejected country setting\n");
++ return;
++ }
++ brcmf_setup_wiphybands(wiphy);
++}
++
++static void brcmf_free_wiphy(struct wiphy *wiphy)
++{
++ if (!wiphy)
++ return;
++
++ kfree(wiphy->iface_combinations);
++ if (wiphy->bands[IEEE80211_BAND_2GHZ]) {
++ kfree(wiphy->bands[IEEE80211_BAND_2GHZ]->channels);
++ kfree(wiphy->bands[IEEE80211_BAND_2GHZ]);
++ }
++ if (wiphy->bands[IEEE80211_BAND_5GHZ]) {
++ kfree(wiphy->bands[IEEE80211_BAND_5GHZ]->channels);
++ kfree(wiphy->bands[IEEE80211_BAND_5GHZ]);
++ }
++ wiphy_free(wiphy);
++}
++
++struct brcmf_cfg80211_info *brcmf_cfg80211_attach(struct brcmf_pub *drvr,
++ struct device *busdev)
++{
++ struct net_device *ndev = drvr->iflist[0]->ndev;
++ struct brcmf_cfg80211_info *cfg;
++ struct wiphy *wiphy;
++ struct brcmf_cfg80211_vif *vif;
++ struct brcmf_if *ifp;
++ s32 err = 0;
++ s32 io_type;
++ u16 *cap = NULL;
++
++ if (!ndev) {
++ brcmf_err("ndev is invalid\n");
++ return NULL;
++ }
++
++ ifp = netdev_priv(ndev);
++ wiphy = wiphy_new(&wl_cfg80211_ops, sizeof(struct brcmf_cfg80211_info));
++ if (!wiphy) {
++ brcmf_err("Could not allocate wiphy device\n");
++ return NULL;
++ }
++ set_wiphy_dev(wiphy, busdev);
++
++ cfg = wiphy_priv(wiphy);
++ cfg->wiphy = wiphy;
++ cfg->pub = drvr;
++ init_vif_event(&cfg->vif_event);
++ INIT_LIST_HEAD(&cfg->vif_list);
++
++ vif = brcmf_alloc_vif(cfg, NL80211_IFTYPE_STATION, false);
++ if (IS_ERR(vif))
++ goto wiphy_out;
++
++ vif->ifp = ifp;
++ vif->wdev.netdev = ndev;
++ ndev->ieee80211_ptr = &vif->wdev;
++ SET_NETDEV_DEV(ndev, wiphy_dev(cfg->wiphy));
++
++ err = wl_init_priv(cfg);
++ if (err) {
++ brcmf_err("Failed to init iwm_priv (%d)\n", err);
++ brcmf_free_vif(vif);
++ goto wiphy_out;
++ }
++ ifp->vif = vif;
++
++ /* determine d11 io type before wiphy setup */
++ err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_VERSION, &io_type);
++ if (err) {
++ brcmf_err("Failed to get D11 version (%d)\n", err);
++ goto priv_out;
++ }
++ cfg->d11inf.io_type = (u8)io_type;
++ brcmu_d11_attach(&cfg->d11inf);
++
++ err = brcmf_setup_wiphy(wiphy, ifp);
++ if (err < 0)
++ goto priv_out;
++
++ brcmf_dbg(INFO, "Registering custom regulatory\n");
++ wiphy->reg_notifier = brcmf_cfg80211_reg_notifier;
++ wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
++ wiphy_apply_custom_regulatory(wiphy, &brcmf_regdom);
++
++ /* firmware defaults to 40MHz disabled in 2G band. We signal
++ * cfg80211 here that we do and have it decide we can enable
++ * it. But first check if device does support 2G operation.
++ */
++ if (wiphy->bands[IEEE80211_BAND_2GHZ]) {
++ cap = &wiphy->bands[IEEE80211_BAND_2GHZ]->ht_cap.cap;
++ *cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
++ }
++ err = wiphy_register(wiphy);
++ if (err < 0) {
++ brcmf_err("Could not register wiphy device (%d)\n", err);
++ goto priv_out;
++ }
++
++ /* If cfg80211 didn't disable 40MHz HT CAP in wiphy_register(),
++ * setup 40MHz in 2GHz band and enable OBSS scanning.
++ */
++ if (cap && (*cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) {
++ err = brcmf_enable_bw40_2g(cfg);
++ if (!err)
++ err = brcmf_fil_iovar_int_set(ifp, "obss_coex",
++ BRCMF_OBSS_COEX_AUTO);
++ else
++ *cap &= ~IEEE80211_HT_CAP_SUP_WIDTH_20_40;
++ }
++
++ err = brcmf_p2p_attach(cfg);
++ if (err) {
++ brcmf_err("P2P initilisation failed (%d)\n", err);
++ goto wiphy_unreg_out;
++ }
++ err = brcmf_btcoex_attach(cfg);
++ if (err) {
++ brcmf_err("BT-coex initialisation failed (%d)\n", err);
++ brcmf_p2p_detach(&cfg->p2p);
++ goto wiphy_unreg_out;
++ }
++
++ err = brcmf_fil_iovar_int_set(ifp, "tdls_enable", 1);
++ if (err) {
++ brcmf_dbg(INFO, "TDLS not enabled (%d)\n", err);
++ wiphy->flags &= ~WIPHY_FLAG_SUPPORTS_TDLS;
++ } else {
++ brcmf_fweh_register(cfg->pub, BRCMF_E_TDLS_PEER_EVENT,
++ brcmf_notify_tdls_peer_event);
++ }
++
++ return cfg;
++
++wiphy_unreg_out:
++ wiphy_unregister(cfg->wiphy);
++priv_out:
++ wl_deinit_priv(cfg);
++ brcmf_free_vif(vif);
++wiphy_out:
++ brcmf_free_wiphy(wiphy);
++ return NULL;
++}
++
++void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg)
++{
++ if (!cfg)
++ return;
++
++ WARN_ON(!list_empty(&cfg->vif_list));
++ wiphy_unregister(cfg->wiphy);
++ brcmf_btcoex_detach(cfg);
++ brcmf_p2p_detach(&cfg->p2p);
++ wl_deinit_priv(cfg);
++ brcmf_free_wiphy(cfg->wiphy);
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/cfg80211.h 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,503 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _wl_cfg80211_h_
++#define _wl_cfg80211_h_
++
++/* for brcmu_d11inf */
++#include <brcmu_d11.h>
++
++#define WL_NUM_SCAN_MAX 10
++#define WL_NUM_PMKIDS_MAX MAXPMKID
++#define WL_TLV_INFO_MAX 1024
++#define WL_BSS_INFO_MAX 2048
++#define WL_ASSOC_INFO_MAX 512 /* assoc related fil max buf */
++#define WL_EXTRA_BUF_MAX 2048
++#define WL_ROAM_TRIGGER_LEVEL -75
++#define WL_ROAM_DELTA 20
++#define WL_BEACON_TIMEOUT 3
++
++#define WL_SCAN_CHANNEL_TIME 40
++#define WL_SCAN_UNASSOC_TIME 40
++#define WL_SCAN_PASSIVE_TIME 120
++
++#define WL_ESCAN_BUF_SIZE (1024 * 64)
++#define WL_ESCAN_TIMER_INTERVAL_MS 10000 /* E-Scan timeout */
++
++#define WL_ESCAN_ACTION_START 1
++#define WL_ESCAN_ACTION_CONTINUE 2
++#define WL_ESCAN_ACTION_ABORT 3
++
++#define WL_AUTH_SHARED_KEY 1 /* d11 shared authentication */
++#define IE_MAX_LEN 512
++
++/* IE TLV processing */
++#define TLV_LEN_OFF 1 /* length offset */
++#define TLV_HDR_LEN 2 /* header length */
++#define TLV_BODY_OFF 2 /* body offset */
++#define TLV_OUI_LEN 3 /* oui id length */
++
++/* 802.11 Mgmt Packet flags */
++#define BRCMF_VNDR_IE_BEACON_FLAG 0x1
++#define BRCMF_VNDR_IE_PRBRSP_FLAG 0x2
++#define BRCMF_VNDR_IE_ASSOCRSP_FLAG 0x4
++#define BRCMF_VNDR_IE_AUTHRSP_FLAG 0x8
++#define BRCMF_VNDR_IE_PRBREQ_FLAG 0x10
++#define BRCMF_VNDR_IE_ASSOCREQ_FLAG 0x20
++/* vendor IE in IW advertisement protocol ID field */
++#define BRCMF_VNDR_IE_IWAPID_FLAG 0x40
++/* allow custom IE id */
++#define BRCMF_VNDR_IE_CUSTOM_FLAG 0x100
++
++/* P2P Action Frames flags (spec ordered) */
++#define BRCMF_VNDR_IE_GONREQ_FLAG 0x001000
++#define BRCMF_VNDR_IE_GONRSP_FLAG 0x002000
++#define BRCMF_VNDR_IE_GONCFM_FLAG 0x004000
++#define BRCMF_VNDR_IE_INVREQ_FLAG 0x008000
++#define BRCMF_VNDR_IE_INVRSP_FLAG 0x010000
++#define BRCMF_VNDR_IE_DISREQ_FLAG 0x020000
++#define BRCMF_VNDR_IE_DISRSP_FLAG 0x040000
++#define BRCMF_VNDR_IE_PRDREQ_FLAG 0x080000
++#define BRCMF_VNDR_IE_PRDRSP_FLAG 0x100000
++
++#define BRCMF_VNDR_IE_P2PAF_SHIFT 12
++
++#define BRCMF_MAX_DEFAULT_KEYS 4
++
++
++/**
++ * enum brcmf_scan_status - scan engine status
++ *
++ * @BRCMF_SCAN_STATUS_BUSY: scanning in progress on dongle.
++ * @BRCMF_SCAN_STATUS_ABORT: scan being aborted on dongle.
++ * @BRCMF_SCAN_STATUS_SUPPRESS: scanning is suppressed in driver.
++ */
++enum brcmf_scan_status {
++ BRCMF_SCAN_STATUS_BUSY,
++ BRCMF_SCAN_STATUS_ABORT,
++ BRCMF_SCAN_STATUS_SUPPRESS,
++};
++
++/* dongle configuration */
++struct brcmf_cfg80211_conf {
++ u32 frag_threshold;
++ u32 rts_threshold;
++ u32 retry_short;
++ u32 retry_long;
++ s32 tx_power;
++ struct ieee80211_channel channel;
++};
++
++/* basic structure of scan request */
++struct brcmf_cfg80211_scan_req {
++ struct brcmf_ssid_le ssid_le;
++};
++
++/* basic structure of information element */
++struct brcmf_cfg80211_ie {
++ u16 offset;
++ u8 buf[WL_TLV_INFO_MAX];
++};
++
++/* security information with currently associated ap */
++struct brcmf_cfg80211_security {
++ u32 wpa_versions;
++ u32 auth_type;
++ u32 cipher_pairwise;
++ u32 cipher_group;
++ u32 wpa_auth;
++};
++
++/**
++ * struct brcmf_cfg80211_profile - profile information.
++ *
++ * @ssid: ssid of associated/associating ap.
++ * @bssid: bssid of joined/joining ibss.
++ * @sec: security information.
++ * @key: key information
++ */
++struct brcmf_cfg80211_profile {
++ struct brcmf_ssid ssid;
++ u8 bssid[ETH_ALEN];
++ struct brcmf_cfg80211_security sec;
++ struct brcmf_wsec_key key[BRCMF_MAX_DEFAULT_KEYS];
++};
++
++/**
++ * enum brcmf_vif_status - bit indices for vif status.
++ *
++ * @BRCMF_VIF_STATUS_READY: ready for operation.
++ * @BRCMF_VIF_STATUS_CONNECTING: connect/join in progress.
++ * @BRCMF_VIF_STATUS_CONNECTED: connected/joined succesfully.
++ * @BRCMF_VIF_STATUS_DISCONNECTING: disconnect/disable in progress.
++ * @BRCMF_VIF_STATUS_AP_CREATING: interface configured for AP operation.
++ * @BRCMF_VIF_STATUS_AP_CREATED: AP operation started.
++ */
++enum brcmf_vif_status {
++ BRCMF_VIF_STATUS_READY,
++ BRCMF_VIF_STATUS_CONNECTING,
++ BRCMF_VIF_STATUS_CONNECTED,
++ BRCMF_VIF_STATUS_DISCONNECTING,
++ BRCMF_VIF_STATUS_AP_CREATING,
++ BRCMF_VIF_STATUS_AP_CREATED
++};
++
++/**
++ * struct vif_saved_ie - holds saved IEs for a virtual interface.
++ *
++ * @probe_req_ie: IE info for probe request.
++ * @probe_res_ie: IE info for probe response.
++ * @beacon_ie: IE info for beacon frame.
++ * @probe_req_ie_len: IE info length for probe request.
++ * @probe_res_ie_len: IE info length for probe response.
++ * @beacon_ie_len: IE info length for beacon frame.
++ */
++struct vif_saved_ie {
++ u8 probe_req_ie[IE_MAX_LEN];
++ u8 probe_res_ie[IE_MAX_LEN];
++ u8 beacon_ie[IE_MAX_LEN];
++ u8 assoc_req_ie[IE_MAX_LEN];
++ u32 probe_req_ie_len;
++ u32 probe_res_ie_len;
++ u32 beacon_ie_len;
++ u32 assoc_req_ie_len;
++};
++
++/**
++ * struct brcmf_cfg80211_vif - virtual interface specific information.
++ *
++ * @ifp: lower layer interface pointer
++ * @wdev: wireless device.
++ * @profile: profile information.
++ * @roam_off: roaming state.
++ * @sme_state: SME state using enum brcmf_vif_status bits.
++ * @pm_block: power-management blocked.
++ * @list: linked list.
++ * @mgmt_rx_reg: registered rx mgmt frame types.
++ * @mbss: Multiple BSS type, set if not first AP (not relevant for P2P).
++ */
++struct brcmf_cfg80211_vif {
++ struct brcmf_if *ifp;
++ struct wireless_dev wdev;
++ struct brcmf_cfg80211_profile profile;
++ s32 roam_off;
++ unsigned long sme_state;
++ bool pm_block;
++ struct vif_saved_ie saved_ie;
++ struct list_head list;
++ u16 mgmt_rx_reg;
++ bool mbss;
++ int is_11d;
++};
++
++/* association inform */
++struct brcmf_cfg80211_connect_info {
++ u8 *req_ie;
++ s32 req_ie_len;
++ u8 *resp_ie;
++ s32 resp_ie_len;
++};
++
++/* assoc ie length */
++struct brcmf_cfg80211_assoc_ielen_le {
++ __le32 req_len;
++ __le32 resp_len;
++};
++
++/* wpa2 pmk list */
++struct brcmf_cfg80211_pmk_list {
++ struct pmkid_list pmkids;
++ struct pmkid foo[MAXPMKID - 1];
++};
++
++/* dongle escan state */
++enum wl_escan_state {
++ WL_ESCAN_STATE_IDLE,
++ WL_ESCAN_STATE_SCANNING
++};
++
++struct escan_info {
++ u32 escan_state;
++ u8 escan_buf[WL_ESCAN_BUF_SIZE];
++ struct wiphy *wiphy;
++ struct brcmf_if *ifp;
++ s32 (*run)(struct brcmf_cfg80211_info *cfg, struct brcmf_if *ifp,
++ struct cfg80211_scan_request *request, u16 action);
++};
++
++/**
++ * struct brcmf_pno_param_le - PNO scan configuration parameters
++ *
++ * @version: PNO parameters version.
++ * @scan_freq: scan frequency.
++ * @lost_network_timeout: #sec. to declare discovered network as lost.
++ * @flags: Bit field to control features of PFN such as sort criteria auto
++ * enable switch and background scan.
++ * @rssi_margin: Margin to avoid jitter for choosing a PFN based on RSSI sort
++ * criteria.
++ * @bestn: number of best networks in each scan.
++ * @mscan: number of scans recorded.
++ * @repeat: minimum number of scan intervals before scan frequency changes
++ * in adaptive scan.
++ * @exp: exponent of 2 for maximum scan interval.
++ * @slow_freq: slow scan period.
++ */
++struct brcmf_pno_param_le {
++ __le32 version;
++ __le32 scan_freq;
++ __le32 lost_network_timeout;
++ __le16 flags;
++ __le16 rssi_margin;
++ u8 bestn;
++ u8 mscan;
++ u8 repeat;
++ u8 exp;
++ __le32 slow_freq;
++};
++
++/**
++ * struct brcmf_pno_net_param_le - scan parameters per preferred network.
++ *
++ * @ssid: ssid name and its length.
++ * @flags: bit2: hidden.
++ * @infra: BSS vs IBSS.
++ * @auth: Open vs Closed.
++ * @wpa_auth: WPA type.
++ * @wsec: wsec value.
++ */
++struct brcmf_pno_net_param_le {
++ struct brcmf_ssid_le ssid;
++ __le32 flags;
++ __le32 infra;
++ __le32 auth;
++ __le32 wpa_auth;
++ __le32 wsec;
++};
++
++/**
++ * struct brcmf_pno_net_info_le - information per found network.
++ *
++ * @bssid: BSS network identifier.
++ * @channel: channel number only.
++ * @SSID_len: length of ssid.
++ * @SSID: ssid characters.
++ * @RSSI: receive signal strength (in dBm).
++ * @timestamp: age in seconds.
++ */
++struct brcmf_pno_net_info_le {
++ u8 bssid[ETH_ALEN];
++ u8 channel;
++ u8 SSID_len;
++ u8 SSID[32];
++ __le16 RSSI;
++ __le16 timestamp;
++};
++
++/**
++ * struct brcmf_pno_scanresults_le - result returned in PNO NET FOUND event.
++ *
++ * @version: PNO version identifier.
++ * @status: indicates completion status of PNO scan.
++ * @count: amount of brcmf_pno_net_info_le entries appended.
++ */
++struct brcmf_pno_scanresults_le {
++ __le32 version;
++ __le32 status;
++ __le32 count;
++};
++
++/**
++ * struct brcmf_cfg80211_vif_event - virtual interface event information.
++ *
++ * @vif_wq: waitqueue awaiting interface event from firmware.
++ * @vif_event_lock: protects other members in this structure.
++ * @vif_complete: completion for net attach.
++ * @action: either add, change, or delete.
++ * @vif: virtual interface object related to the event.
++ */
++struct brcmf_cfg80211_vif_event {
++ wait_queue_head_t vif_wq;
++ struct mutex vif_event_lock;
++ u8 action;
++ struct brcmf_cfg80211_vif *vif;
++};
++
++/**
++ * struct brcmf_cfg80211_info - dongle private data of cfg80211 interface
++ *
++ * @wiphy: wiphy object for cfg80211 interface.
++ * @conf: dongle configuration.
++ * @p2p: peer-to-peer specific information.
++ * @btcoex: Bluetooth coexistence information.
++ * @scan_request: cfg80211 scan request object.
++ * @usr_sync: mainly for dongle up/down synchronization.
++ * @bss_list: bss_list holding scanned ap information.
++ * @scan_req_int: internal scan request object.
++ * @bss_info: bss information for cfg80211 layer.
++ * @ie: information element object for internal purpose.
++ * @conn_info: association info.
++ * @pmk_list: wpa2 pmk list.
++ * @scan_status: scan activity on the dongle.
++ * @pub: common driver information.
++ * @channel: current channel.
++ * @active_scan: current scan mode.
++ * @sched_escan: e-scan for scheduled scan support running.
++ * @ibss_starter: indicates this sta is ibss starter.
++ * @pwr_save: indicate whether dongle to support power save mode.
++ * @dongle_up: indicate whether dongle up or not.
++ * @roam_on: on/off switch for dongle self-roaming.
++ * @scan_tried: indicates if first scan attempted.
++ * @dcmd_buf: dcmd buffer.
++ * @extra_buf: mainly to grab assoc information.
++ * @debugfsdir: debugfs folder for this device.
++ * @escan_info: escan information.
++ * @escan_timeout: Timer for catch scan timeout.
++ * @escan_timeout_work: scan timeout worker.
++ * @escan_ioctl_buf: dongle command buffer for escan commands.
++ * @vif_list: linked list of vif instances.
++ * @vif_cnt: number of vif instances.
++ * @vif_event: vif event signalling.
++ * @wowl_enabled; set during suspend, is wowl used.
++ * @pre_wowl_pmmode: intermediate storage of pm mode during wowl.
++ */
++struct brcmf_cfg80211_info {
++ struct wiphy *wiphy;
++ struct brcmf_cfg80211_conf *conf;
++ struct brcmf_p2p_info p2p;
++ struct brcmf_btcoex_info *btcoex;
++ struct cfg80211_scan_request *scan_request;
++ struct mutex usr_sync;
++ struct brcmf_cfg80211_scan_req scan_req_int;
++ struct wl_cfg80211_bss_info *bss_info;
++ struct brcmf_cfg80211_ie ie;
++ struct brcmf_cfg80211_connect_info conn_info;
++ struct brcmf_cfg80211_pmk_list *pmk_list;
++ unsigned long scan_status;
++ struct brcmf_pub *pub;
++ u32 channel;
++ bool active_scan;
++ bool sched_escan;
++ bool ibss_starter;
++ bool pwr_save;
++ bool dongle_up;
++ bool scan_tried;
++ u8 *dcmd_buf;
++ u8 *extra_buf;
++ struct dentry *debugfsdir;
++ struct escan_info escan_info;
++ struct timer_list escan_timeout;
++ struct work_struct escan_timeout_work;
++ u8 *escan_ioctl_buf;
++ struct list_head vif_list;
++ struct brcmf_cfg80211_vif_event vif_event;
++ struct completion vif_disabled;
++ struct brcmu_d11inf d11inf;
++ bool wowl_enabled;
++ u32 pre_wowl_pmmode;
++};
++
++/**
++ * struct brcmf_tlv - tag_ID/length/value_buffer tuple.
++ *
++ * @id: tag identifier.
++ * @len: number of bytes in value buffer.
++ * @data: value buffer.
++ */
++struct brcmf_tlv {
++ u8 id;
++ u8 len;
++ u8 data[1];
++};
++
++static inline struct wiphy *cfg_to_wiphy(struct brcmf_cfg80211_info *cfg)
++{
++ return cfg->wiphy;
++}
++
++static inline struct brcmf_cfg80211_info *wiphy_to_cfg(struct wiphy *w)
++{
++ return (struct brcmf_cfg80211_info *)(wiphy_priv(w));
++}
++
++static inline struct brcmf_cfg80211_info *wdev_to_cfg(struct wireless_dev *wd)
++{
++ return (struct brcmf_cfg80211_info *)(wdev_priv(wd));
++}
++
++static inline
++struct net_device *cfg_to_ndev(struct brcmf_cfg80211_info *cfg)
++{
++ struct brcmf_cfg80211_vif *vif;
++ vif = list_first_entry(&cfg->vif_list, struct brcmf_cfg80211_vif, list);
++ return vif->wdev.netdev;
++}
++
++static inline struct brcmf_cfg80211_info *ndev_to_cfg(struct net_device *ndev)
++{
++ return wdev_to_cfg(ndev->ieee80211_ptr);
++}
++
++static inline struct brcmf_cfg80211_profile *ndev_to_prof(struct net_device *nd)
++{
++ struct brcmf_if *ifp = netdev_priv(nd);
++ return &ifp->vif->profile;
++}
++
++static inline struct brcmf_cfg80211_vif *ndev_to_vif(struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ return ifp->vif;
++}
++
++static inline struct
++brcmf_cfg80211_connect_info *cfg_to_conn(struct brcmf_cfg80211_info *cfg)
++{
++ return &cfg->conn_info;
++}
++
++struct brcmf_cfg80211_info *brcmf_cfg80211_attach(struct brcmf_pub *drvr,
++ struct device *busdev);
++void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg);
++s32 brcmf_cfg80211_up(struct net_device *ndev);
++s32 brcmf_cfg80211_down(struct net_device *ndev);
++enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp);
++
++struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
++ enum nl80211_iftype type,
++ bool pm_block);
++void brcmf_free_vif(struct brcmf_cfg80211_vif *vif);
++
++s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
++ const u8 *vndr_ie_buf, u32 vndr_ie_len);
++s32 brcmf_vif_clear_mgmt_ies(struct brcmf_cfg80211_vif *vif);
++const struct brcmf_tlv *
++brcmf_parse_tlvs(const void *buf, int buflen, uint key);
++u16 channel_to_chanspec(struct brcmu_d11inf *d11inf,
++ struct ieee80211_channel *ch);
++bool brcmf_get_vif_state_any(struct brcmf_cfg80211_info *cfg, unsigned long state);
++void brcmf_cfg80211_arm_vif_event(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_cfg80211_vif *vif);
++bool brcmf_cfg80211_vif_event_armed(struct brcmf_cfg80211_info *cfg);
++int brcmf_cfg80211_wait_vif_event_timeout(struct brcmf_cfg80211_info *cfg,
++ u8 action, ulong timeout);
++s32 brcmf_notify_escan_complete(struct brcmf_cfg80211_info *cfg,
++ struct brcmf_if *ifp, bool aborted,
++ bool fw_abort);
++void brcmf_set_mpc(struct brcmf_if *ndev, int mpc);
++void brcmf_abort_scanning(struct brcmf_cfg80211_info *cfg);
++void brcmf_cfg80211_free_netdev(struct net_device *ndev);
++
++#endif /* _wl_cfg80211_h_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/chip.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/chip.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/chip.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/chip.c 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,1220 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/list.h>
++#include <linux/ssb/ssb_regs.h>
++#include <linux/bcma/bcma.h>
++#include <linux/bcma/bcma_regs.h>
++
++#include <defs.h>
++#include <soc.h>
++#include <brcm_hw_ids.h>
++#include <brcmu_utils.h>
++#include <chipcommon.h>
++#include "debug.h"
++#include "chip.h"
++
++/* SOC Interconnect types (aka chip types) */
++#define SOCI_SB 0
++#define SOCI_AI 1
++
++/* PL-368 DMP definitions */
++#define DMP_DESC_TYPE_MSK 0x0000000F
++#define DMP_DESC_EMPTY 0x00000000
++#define DMP_DESC_VALID 0x00000001
++#define DMP_DESC_COMPONENT 0x00000001
++#define DMP_DESC_MASTER_PORT 0x00000003
++#define DMP_DESC_ADDRESS 0x00000005
++#define DMP_DESC_ADDRSIZE_GT32 0x00000008
++#define DMP_DESC_EOT 0x0000000F
++
++#define DMP_COMP_DESIGNER 0xFFF00000
++#define DMP_COMP_DESIGNER_S 20
++#define DMP_COMP_PARTNUM 0x000FFF00
++#define DMP_COMP_PARTNUM_S 8
++#define DMP_COMP_CLASS 0x000000F0
++#define DMP_COMP_CLASS_S 4
++#define DMP_COMP_REVISION 0xFF000000
++#define DMP_COMP_REVISION_S 24
++#define DMP_COMP_NUM_SWRAP 0x00F80000
++#define DMP_COMP_NUM_SWRAP_S 19
++#define DMP_COMP_NUM_MWRAP 0x0007C000
++#define DMP_COMP_NUM_MWRAP_S 14
++#define DMP_COMP_NUM_SPORT 0x00003E00
++#define DMP_COMP_NUM_SPORT_S 9
++#define DMP_COMP_NUM_MPORT 0x000001F0
++#define DMP_COMP_NUM_MPORT_S 4
++
++#define DMP_MASTER_PORT_UID 0x0000FF00
++#define DMP_MASTER_PORT_UID_S 8
++#define DMP_MASTER_PORT_NUM 0x000000F0
++#define DMP_MASTER_PORT_NUM_S 4
++
++#define DMP_SLAVE_ADDR_BASE 0xFFFFF000
++#define DMP_SLAVE_ADDR_BASE_S 12
++#define DMP_SLAVE_PORT_NUM 0x00000F00
++#define DMP_SLAVE_PORT_NUM_S 8
++#define DMP_SLAVE_TYPE 0x000000C0
++#define DMP_SLAVE_TYPE_S 6
++#define DMP_SLAVE_TYPE_SLAVE 0
++#define DMP_SLAVE_TYPE_BRIDGE 1
++#define DMP_SLAVE_TYPE_SWRAP 2
++#define DMP_SLAVE_TYPE_MWRAP 3
++#define DMP_SLAVE_SIZE_TYPE 0x00000030
++#define DMP_SLAVE_SIZE_TYPE_S 4
++#define DMP_SLAVE_SIZE_4K 0
++#define DMP_SLAVE_SIZE_8K 1
++#define DMP_SLAVE_SIZE_16K 2
++#define DMP_SLAVE_SIZE_DESC 3
++
++/* EROM CompIdentB */
++#define CIB_REV_MASK 0xff000000
++#define CIB_REV_SHIFT 24
++
++/* ARM CR4 core specific control flag bits */
++#define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
++
++/* D11 core specific control flag bits */
++#define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
++#define D11_BCMA_IOCTL_PHYRESET 0x0008
++
++/* chip core base & ramsize */
++/* bcm4329 */
++/* SDIO device core, ID 0x829 */
++#define BCM4329_CORE_BUS_BASE 0x18011000
++/* internal memory core, ID 0x80e */
++#define BCM4329_CORE_SOCRAM_BASE 0x18003000
++/* ARM Cortex M3 core, ID 0x82a */
++#define BCM4329_CORE_ARM_BASE 0x18002000
++
++#define CORE_SB(base, field) \
++ (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
++#define SBCOREREV(sbidh) \
++ ((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
++ ((sbidh) & SSB_IDHIGH_RCLO))
++
++struct sbconfig {
++ u32 PAD[2];
++ u32 sbipsflag; /* initiator port ocp slave flag */
++ u32 PAD[3];
++ u32 sbtpsflag; /* target port ocp slave flag */
++ u32 PAD[11];
++ u32 sbtmerrloga; /* (sonics >= 2.3) */
++ u32 PAD;
++ u32 sbtmerrlog; /* (sonics >= 2.3) */
++ u32 PAD[3];
++ u32 sbadmatch3; /* address match3 */
++ u32 PAD;
++ u32 sbadmatch2; /* address match2 */
++ u32 PAD;
++ u32 sbadmatch1; /* address match1 */
++ u32 PAD[7];
++ u32 sbimstate; /* initiator agent state */
++ u32 sbintvec; /* interrupt mask */
++ u32 sbtmstatelow; /* target state */
++ u32 sbtmstatehigh; /* target state */
++ u32 sbbwa0; /* bandwidth allocation table0 */
++ u32 PAD;
++ u32 sbimconfiglow; /* initiator configuration */
++ u32 sbimconfighigh; /* initiator configuration */
++ u32 sbadmatch0; /* address match0 */
++ u32 PAD;
++ u32 sbtmconfiglow; /* target configuration */
++ u32 sbtmconfighigh; /* target configuration */
++ u32 sbbconfig; /* broadcast configuration */
++ u32 PAD;
++ u32 sbbstate; /* broadcast state */
++ u32 PAD[3];
++ u32 sbactcnfg; /* activate configuration */
++ u32 PAD[3];
++ u32 sbflagst; /* current sbflags */
++ u32 PAD[3];
++ u32 sbidlow; /* identification */
++ u32 sbidhigh; /* identification */
++};
++
++/* bankidx and bankinfo reg defines corerev >= 8 */
++#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
++#define SOCRAM_BANKINFO_SZMASK 0x0000007f
++#define SOCRAM_BANKIDX_ROM_MASK 0x00000100
++
++#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
++/* socram bankinfo memtype */
++#define SOCRAM_MEMTYPE_RAM 0
++#define SOCRAM_MEMTYPE_R0M 1
++#define SOCRAM_MEMTYPE_DEVRAM 2
++
++#define SOCRAM_BANKINFO_SZBASE 8192
++#define SRCI_LSS_MASK 0x00f00000
++#define SRCI_LSS_SHIFT 20
++#define SRCI_SRNB_MASK 0xf0
++#define SRCI_SRNB_SHIFT 4
++#define SRCI_SRBSZ_MASK 0xf
++#define SRCI_SRBSZ_SHIFT 0
++#define SR_BSZ_BASE 14
++
++struct sbsocramregs {
++ u32 coreinfo;
++ u32 bwalloc;
++ u32 extracoreinfo;
++ u32 biststat;
++ u32 bankidx;
++ u32 standbyctrl;
++
++ u32 errlogstatus; /* rev 6 */
++ u32 errlogaddr; /* rev 6 */
++ /* used for patching rev 3 & 5 */
++ u32 cambankidx;
++ u32 cambankstandbyctrl;
++ u32 cambankpatchctrl;
++ u32 cambankpatchtblbaseaddr;
++ u32 cambankcmdreg;
++ u32 cambankdatareg;
++ u32 cambankmaskreg;
++ u32 PAD[1];
++ u32 bankinfo; /* corev 8 */
++ u32 bankpda;
++ u32 PAD[14];
++ u32 extmemconfig;
++ u32 extmemparitycsr;
++ u32 extmemparityerrdata;
++ u32 extmemparityerrcnt;
++ u32 extmemwrctrlandsize;
++ u32 PAD[84];
++ u32 workaround;
++ u32 pwrctl; /* corerev >= 2 */
++ u32 PAD[133];
++ u32 sr_control; /* corerev >= 15 */
++ u32 sr_status; /* corerev >= 15 */
++ u32 sr_address; /* corerev >= 15 */
++ u32 sr_data; /* corerev >= 15 */
++};
++
++#define SOCRAMREGOFFS(_f) offsetof(struct sbsocramregs, _f)
++
++#define ARMCR4_CAP (0x04)
++#define ARMCR4_BANKIDX (0x40)
++#define ARMCR4_BANKINFO (0x44)
++#define ARMCR4_BANKPDA (0x4C)
++
++#define ARMCR4_TCBBNB_MASK 0xf0
++#define ARMCR4_TCBBNB_SHIFT 4
++#define ARMCR4_TCBANB_MASK 0xf
++#define ARMCR4_TCBANB_SHIFT 0
++
++#define ARMCR4_BSZ_MASK 0x3f
++#define ARMCR4_BSZ_MULT 8192
++
++struct brcmf_core_priv {
++ struct brcmf_core pub;
++ u32 wrapbase;
++ struct list_head list;
++ struct brcmf_chip_priv *chip;
++};
++
++struct brcmf_chip_priv {
++ struct brcmf_chip pub;
++ const struct brcmf_buscore_ops *ops;
++ void *ctx;
++ /* assured first core is chipcommon, second core is buscore */
++ struct list_head cores;
++ u16 num_cores;
++
++ bool (*iscoreup)(struct brcmf_core_priv *core);
++ void (*coredisable)(struct brcmf_core_priv *core, u32 prereset,
++ u32 reset);
++ void (*resetcore)(struct brcmf_core_priv *core, u32 prereset, u32 reset,
++ u32 postreset);
++};
++
++static void brcmf_chip_sb_corerev(struct brcmf_chip_priv *ci,
++ struct brcmf_core *core)
++{
++ u32 regdata;
++
++ regdata = ci->ops->read32(ci->ctx, CORE_SB(core->base, sbidhigh));
++ core->rev = SBCOREREV(regdata);
++}
++
++static bool brcmf_chip_sb_iscoreup(struct brcmf_core_priv *core)
++{
++ struct brcmf_chip_priv *ci;
++ u32 regdata;
++ u32 address;
++
++ ci = core->chip;
++ address = CORE_SB(core->pub.base, sbtmstatelow);
++ regdata = ci->ops->read32(ci->ctx, address);
++ regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
++ SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
++ return SSB_TMSLOW_CLOCK == regdata;
++}
++
++static bool brcmf_chip_ai_iscoreup(struct brcmf_core_priv *core)
++{
++ struct brcmf_chip_priv *ci;
++ u32 regdata;
++ bool ret;
++
++ ci = core->chip;
++ regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
++ ret = (regdata & (BCMA_IOCTL_FGC | BCMA_IOCTL_CLK)) == BCMA_IOCTL_CLK;
++
++ regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
++ ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0);
++
++ return ret;
++}
++
++static void brcmf_chip_sb_coredisable(struct brcmf_core_priv *core,
++ u32 prereset, u32 reset)
++{
++ struct brcmf_chip_priv *ci;
++ u32 val, base;
++
++ ci = core->chip;
++ base = core->pub.base;
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ if (val & SSB_TMSLOW_RESET)
++ return;
++
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ if ((val & SSB_TMSLOW_CLOCK) != 0) {
++ /*
++ * set target reject and spin until busy is clear
++ * (preserve core-specific bits)
++ */
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
++ val | SSB_TMSLOW_REJECT);
++
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ udelay(1);
++ SPINWAIT((ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh))
++ & SSB_TMSHIGH_BUSY), 100000);
++
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
++ if (val & SSB_TMSHIGH_BUSY)
++ brcmf_err("core state still busy\n");
++
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
++ if (val & SSB_IDLOW_INITIATOR) {
++ val = ci->ops->read32(ci->ctx,
++ CORE_SB(base, sbimstate));
++ val |= SSB_IMSTATE_REJECT;
++ ci->ops->write32(ci->ctx,
++ CORE_SB(base, sbimstate), val);
++ val = ci->ops->read32(ci->ctx,
++ CORE_SB(base, sbimstate));
++ udelay(1);
++ SPINWAIT((ci->ops->read32(ci->ctx,
++ CORE_SB(base, sbimstate)) &
++ SSB_IMSTATE_BUSY), 100000);
++ }
++
++ /* set reset and reject while enabling the clocks */
++ val = SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
++ SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET;
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow), val);
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ udelay(10);
++
++ /* clear the initiator reject bit */
++ val = ci->ops->read32(ci->ctx, CORE_SB(base, sbidlow));
++ if (val & SSB_IDLOW_INITIATOR) {
++ val = ci->ops->read32(ci->ctx,
++ CORE_SB(base, sbimstate));
++ val &= ~SSB_IMSTATE_REJECT;
++ ci->ops->write32(ci->ctx,
++ CORE_SB(base, sbimstate), val);
++ }
++ }
++
++ /* leave reset and reject asserted */
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
++ (SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
++ udelay(1);
++}
++
++static void brcmf_chip_ai_coredisable(struct brcmf_core_priv *core,
++ u32 prereset, u32 reset)
++{
++ struct brcmf_chip_priv *ci;
++ u32 regdata;
++
++ ci = core->chip;
++
++ /* if core is already in reset, skip reset */
++ regdata = ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL);
++ if ((regdata & BCMA_RESET_CTL_RESET) != 0)
++ goto in_reset_configure;
++
++ /* configure reset */
++ ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
++ prereset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
++ ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
++
++ /* put in reset */
++ ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL,
++ BCMA_RESET_CTL_RESET);
++ usleep_range(10, 20);
++
++ /* wait till reset is 1 */
++ SPINWAIT(ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) !=
++ BCMA_RESET_CTL_RESET, 300);
++
++in_reset_configure:
++ /* in-reset configure */
++ ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
++ reset | BCMA_IOCTL_FGC | BCMA_IOCTL_CLK);
++ ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
++}
++
++static void brcmf_chip_sb_resetcore(struct brcmf_core_priv *core, u32 prereset,
++ u32 reset, u32 postreset)
++{
++ struct brcmf_chip_priv *ci;
++ u32 regdata;
++ u32 base;
++
++ ci = core->chip;
++ base = core->pub.base;
++ /*
++ * Must do the disable sequence first to work for
++ * arbitrary current core state.
++ */
++ brcmf_chip_sb_coredisable(core, 0, 0);
++
++ /*
++ * Now do the initialization sequence.
++ * set reset while enabling the clock and
++ * forcing them on throughout the core
++ */
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
++ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
++ SSB_TMSLOW_RESET);
++ regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ udelay(1);
++
++ /* clear any serror */
++ regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatehigh));
++ if (regdata & SSB_TMSHIGH_SERR)
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0);
++
++ regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbimstate));
++ if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
++ regdata &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbimstate), regdata);
++ }
++
++ /* clear reset and allow it to propagate throughout the core */
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
++ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
++ regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ udelay(1);
++
++ /* leave clock enabled */
++ ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatelow),
++ SSB_TMSLOW_CLOCK);
++ regdata = ci->ops->read32(ci->ctx, CORE_SB(base, sbtmstatelow));
++ udelay(1);
++}
++
++static void brcmf_chip_ai_resetcore(struct brcmf_core_priv *core, u32 prereset,
++ u32 reset, u32 postreset)
++{
++ struct brcmf_chip_priv *ci;
++ int count;
++
++ ci = core->chip;
++
++ /* must disable first to work for arbitrary current core state */
++ brcmf_chip_ai_coredisable(core, prereset, reset);
++
++ count = 0;
++ while (ci->ops->read32(ci->ctx, core->wrapbase + BCMA_RESET_CTL) &
++ BCMA_RESET_CTL_RESET) {
++ ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0);
++ count++;
++ if (count > 50)
++ break;
++ usleep_range(40, 60);
++ }
++
++ ci->ops->write32(ci->ctx, core->wrapbase + BCMA_IOCTL,
++ postreset | BCMA_IOCTL_CLK);
++ ci->ops->read32(ci->ctx, core->wrapbase + BCMA_IOCTL);
++}
++
++static char *brcmf_chip_name(uint chipid, char *buf, uint len)
++{
++ const char *fmt;
++
++ fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
++ snprintf(buf, len, fmt, chipid);
++ return buf;
++}
++
++static struct brcmf_core *brcmf_chip_add_core(struct brcmf_chip_priv *ci,
++ u16 coreid, u32 base,
++ u32 wrapbase)
++{
++ struct brcmf_core_priv *core;
++
++ core = kzalloc(sizeof(*core), GFP_KERNEL);
++ if (!core)
++ return ERR_PTR(-ENOMEM);
++
++ core->pub.id = coreid;
++ core->pub.base = base;
++ core->chip = ci;
++ core->wrapbase = wrapbase;
++
++ list_add_tail(&core->list, &ci->cores);
++ return &core->pub;
++}
++
++/* safety check for chipinfo */
++static int brcmf_chip_cores_check(struct brcmf_chip_priv *ci)
++{
++ struct brcmf_core_priv *core;
++ bool need_socram = false;
++ bool has_socram = false;
++ bool cpu_found = false;
++ int idx = 1;
++
++ list_for_each_entry(core, &ci->cores, list) {
++ brcmf_dbg(INFO, " [%-2d] core 0x%x:%-2d base 0x%08x wrap 0x%08x\n",
++ idx++, core->pub.id, core->pub.rev, core->pub.base,
++ core->wrapbase);
++
++ switch (core->pub.id) {
++ case BCMA_CORE_ARM_CM3:
++ cpu_found = true;
++ need_socram = true;
++ break;
++ case BCMA_CORE_INTERNAL_MEM:
++ has_socram = true;
++ break;
++ case BCMA_CORE_ARM_CR4:
++ cpu_found = true;
++ break;
++ default:
++ break;
++ }
++ }
++
++ if (!cpu_found) {
++ brcmf_err("CPU core not detected\n");
++ return -ENXIO;
++ }
++ /* check RAM core presence for ARM CM3 core */
++ if (need_socram && !has_socram) {
++ brcmf_err("RAM core not provided with ARM CM3 core\n");
++ return -ENODEV;
++ }
++ return 0;
++}
++
++static u32 brcmf_chip_core_read32(struct brcmf_core_priv *core, u16 reg)
++{
++ return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg);
++}
++
++static void brcmf_chip_core_write32(struct brcmf_core_priv *core,
++ u16 reg, u32 val)
++{
++ core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val);
++}
++
++static bool brcmf_chip_socram_banksize(struct brcmf_core_priv *core, u8 idx,
++ u32 *banksize)
++{
++ u32 bankinfo;
++ u32 bankidx = (SOCRAM_MEMTYPE_RAM << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
++
++ bankidx |= idx;
++ brcmf_chip_core_write32(core, SOCRAMREGOFFS(bankidx), bankidx);
++ bankinfo = brcmf_chip_core_read32(core, SOCRAMREGOFFS(bankinfo));
++ *banksize = (bankinfo & SOCRAM_BANKINFO_SZMASK) + 1;
++ *banksize *= SOCRAM_BANKINFO_SZBASE;
++ return !!(bankinfo & SOCRAM_BANKINFO_RETNTRAM_MASK);
++}
++
++static void brcmf_chip_socram_ramsize(struct brcmf_core_priv *sr, u32 *ramsize,
++ u32 *srsize)
++{
++ u32 coreinfo;
++ uint nb, banksize, lss;
++ bool retent;
++ int i;
++
++ *ramsize = 0;
++ *srsize = 0;
++
++ if (WARN_ON(sr->pub.rev < 4))
++ return;
++
++ if (!brcmf_chip_iscoreup(&sr->pub))
++ brcmf_chip_resetcore(&sr->pub, 0, 0, 0);
++
++ /* Get info for determining size */
++ coreinfo = brcmf_chip_core_read32(sr, SOCRAMREGOFFS(coreinfo));
++ nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++
++ if ((sr->pub.rev <= 7) || (sr->pub.rev == 12)) {
++ banksize = (coreinfo & SRCI_SRBSZ_MASK);
++ lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
++ if (lss != 0)
++ nb--;
++ *ramsize = nb * (1 << (banksize + SR_BSZ_BASE));
++ if (lss != 0)
++ *ramsize += (1 << ((lss - 1) + SR_BSZ_BASE));
++ } else {
++ nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
++ for (i = 0; i < nb; i++) {
++ retent = brcmf_chip_socram_banksize(sr, i, &banksize);
++ *ramsize += banksize;
++ if (retent)
++ *srsize += banksize;
++ }
++ }
++
++ /* hardcoded save&restore memory sizes */
++ switch (sr->chip->pub.chip) {
++ case BRCM_CC_4334_CHIP_ID:
++ if (sr->chip->pub.chiprev < 2)
++ *srsize = (32 * 1024);
++ break;
++ case BRCM_CC_43430_CHIP_ID:
++ /* assume sr for now as we can not check
++ * firmware sr capability at this point.
++ */
++ *srsize = (64 * 1024);
++ break;
++ default:
++ break;
++ }
++}
++
++/** Return the TCM-RAM size of the ARMCR4 core. */
++static u32 brcmf_chip_tcm_ramsize(struct brcmf_core_priv *cr4)
++{
++ u32 corecap;
++ u32 memsize = 0;
++ u32 nab;
++ u32 nbb;
++ u32 totb;
++ u32 bxinfo;
++ u32 idx;
++
++ corecap = brcmf_chip_core_read32(cr4, ARMCR4_CAP);
++
++ nab = (corecap & ARMCR4_TCBANB_MASK) >> ARMCR4_TCBANB_SHIFT;
++ nbb = (corecap & ARMCR4_TCBBNB_MASK) >> ARMCR4_TCBBNB_SHIFT;
++ totb = nab + nbb;
++
++ for (idx = 0; idx < totb; idx++) {
++ brcmf_chip_core_write32(cr4, ARMCR4_BANKIDX, idx);
++ bxinfo = brcmf_chip_core_read32(cr4, ARMCR4_BANKINFO);
++ memsize += ((bxinfo & ARMCR4_BSZ_MASK) + 1) * ARMCR4_BSZ_MULT;
++ }
++
++ return memsize;
++}
++
++static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
++{
++ switch (ci->pub.chip) {
++ case BRCM_CC_4345_CHIP_ID:
++ return 0x198000;
++ case BRCM_CC_4335_CHIP_ID:
++ case BRCM_CC_4339_CHIP_ID:
++ case BRCM_CC_4354_CHIP_ID:
++ case BRCM_CC_4356_CHIP_ID:
++ case BRCM_CC_43567_CHIP_ID:
++ case BRCM_CC_43569_CHIP_ID:
++ case BRCM_CC_43570_CHIP_ID:
++ case BRCM_CC_43602_CHIP_ID:
++ return 0x180000;
++ default:
++ brcmf_err("unknown chip: %s\n", ci->pub.name);
++ break;
++ }
++ return 0;
++}
++
++static int brcmf_chip_get_raminfo(struct brcmf_chip_priv *ci)
++{
++ struct brcmf_core_priv *mem_core;
++ struct brcmf_core *mem;
++
++ mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_ARM_CR4);
++ if (mem) {
++ mem_core = container_of(mem, struct brcmf_core_priv, pub);
++ ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
++ ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
++ if (!ci->pub.rambase) {
++ brcmf_err("RAM base not provided with ARM CR4 core\n");
++ return -EINVAL;
++ }
++ } else {
++ mem = brcmf_chip_get_core(&ci->pub, BCMA_CORE_INTERNAL_MEM);
++ mem_core = container_of(mem, struct brcmf_core_priv, pub);
++ brcmf_chip_socram_ramsize(mem_core, &ci->pub.ramsize,
++ &ci->pub.srsize);
++ }
++ brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n",
++ ci->pub.rambase, ci->pub.ramsize, ci->pub.ramsize,
++ ci->pub.srsize, ci->pub.srsize);
++
++ if (!ci->pub.ramsize) {
++ brcmf_err("RAM size is undetermined\n");
++ return -ENOMEM;
++ }
++ return 0;
++}
++
++static u32 brcmf_chip_dmp_get_desc(struct brcmf_chip_priv *ci, u32 *eromaddr,
++ u8 *type)
++{
++ u32 val;
++
++ /* read next descriptor */
++ val = ci->ops->read32(ci->ctx, *eromaddr);
++ *eromaddr += 4;
++
++ if (!type)
++ return val;
++
++ /* determine descriptor type */
++ *type = (val & DMP_DESC_TYPE_MSK);
++ if ((*type & ~DMP_DESC_ADDRSIZE_GT32) == DMP_DESC_ADDRESS)
++ *type = DMP_DESC_ADDRESS;
++
++ return val;
++}
++
++static int brcmf_chip_dmp_get_regaddr(struct brcmf_chip_priv *ci, u32 *eromaddr,
++ u32 *regbase, u32 *wrapbase)
++{
++ u8 desc;
++ u32 val;
++ u8 mpnum = 0;
++ u8 stype, sztype, wraptype;
++
++ *regbase = 0;
++ *wrapbase = 0;
++
++ val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
++ if (desc == DMP_DESC_MASTER_PORT) {
++ mpnum = (val & DMP_MASTER_PORT_NUM) >> DMP_MASTER_PORT_NUM_S;
++ wraptype = DMP_SLAVE_TYPE_MWRAP;
++ } else if (desc == DMP_DESC_ADDRESS) {
++ /* revert erom address */
++ *eromaddr -= 4;
++ wraptype = DMP_SLAVE_TYPE_SWRAP;
++ } else {
++ *eromaddr -= 4;
++ return -EILSEQ;
++ }
++
++ do {
++ /* locate address descriptor */
++ do {
++ val = brcmf_chip_dmp_get_desc(ci, eromaddr, &desc);
++ /* unexpected table end */
++ if (desc == DMP_DESC_EOT) {
++ *eromaddr -= 4;
++ return -EFAULT;
++ }
++ } while (desc != DMP_DESC_ADDRESS);
++
++ /* skip upper 32-bit address descriptor */
++ if (val & DMP_DESC_ADDRSIZE_GT32)
++ brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
++
++ sztype = (val & DMP_SLAVE_SIZE_TYPE) >> DMP_SLAVE_SIZE_TYPE_S;
++
++ /* next size descriptor can be skipped */
++ if (sztype == DMP_SLAVE_SIZE_DESC) {
++ val = brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
++ /* skip upper size descriptor if present */
++ if (val & DMP_DESC_ADDRSIZE_GT32)
++ brcmf_chip_dmp_get_desc(ci, eromaddr, NULL);
++ }
++
++ /* only look for 4K register regions */
++ if (sztype != DMP_SLAVE_SIZE_4K)
++ continue;
++
++ stype = (val & DMP_SLAVE_TYPE) >> DMP_SLAVE_TYPE_S;
++
++ /* only regular slave and wrapper */
++ if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE)
++ *regbase = val & DMP_SLAVE_ADDR_BASE;
++ if (*wrapbase == 0 && stype == wraptype)
++ *wrapbase = val & DMP_SLAVE_ADDR_BASE;
++ } while (*regbase == 0 || *wrapbase == 0);
++
++ return 0;
++}
++
++static
++int brcmf_chip_dmp_erom_scan(struct brcmf_chip_priv *ci)
++{
++ struct brcmf_core *core;
++ u32 eromaddr;
++ u8 desc_type = 0;
++ u32 val;
++ u16 id;
++ u8 nmp, nsp, nmw, nsw, rev;
++ u32 base, wrap;
++ int err;
++
++ eromaddr = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, eromptr));
++
++ while (desc_type != DMP_DESC_EOT) {
++ val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
++ if (!(val & DMP_DESC_VALID))
++ continue;
++
++ if (desc_type == DMP_DESC_EMPTY)
++ continue;
++
++ /* need a component descriptor */
++ if (desc_type != DMP_DESC_COMPONENT)
++ continue;
++
++ id = (val & DMP_COMP_PARTNUM) >> DMP_COMP_PARTNUM_S;
++
++ /* next descriptor must be component as well */
++ val = brcmf_chip_dmp_get_desc(ci, &eromaddr, &desc_type);
++ if (WARN_ON((val & DMP_DESC_TYPE_MSK) != DMP_DESC_COMPONENT))
++ return -EFAULT;
++
++ /* only look at cores with master port(s) */
++ nmp = (val & DMP_COMP_NUM_MPORT) >> DMP_COMP_NUM_MPORT_S;
++ nsp = (val & DMP_COMP_NUM_SPORT) >> DMP_COMP_NUM_SPORT_S;
++ nmw = (val & DMP_COMP_NUM_MWRAP) >> DMP_COMP_NUM_MWRAP_S;
++ nsw = (val & DMP_COMP_NUM_SWRAP) >> DMP_COMP_NUM_SWRAP_S;
++ rev = (val & DMP_COMP_REVISION) >> DMP_COMP_REVISION_S;
++
++ /* need core with ports */
++ if (nmw + nsw == 0)
++ continue;
++
++ /* try to obtain register address info */
++ err = brcmf_chip_dmp_get_regaddr(ci, &eromaddr, &base, &wrap);
++ if (err)
++ continue;
++
++ /* finally a core to be added */
++ core = brcmf_chip_add_core(ci, id, base, wrap);
++ if (IS_ERR(core))
++ return PTR_ERR(core);
++
++ core->rev = rev;
++ }
++
++ return 0;
++}
++
++static int brcmf_chip_recognition(struct brcmf_chip_priv *ci)
++{
++ struct brcmf_core *core;
++ u32 regdata;
++ u32 socitype;
++ int ret;
++
++ /* Get CC core rev
++ * Chipid is assume to be at offset 0 from SI_ENUM_BASE
++ * For different chiptypes or old sdio hosts w/o chipcommon,
++ * other ways of recognition should be added here.
++ */
++ regdata = ci->ops->read32(ci->ctx, CORE_CC_REG(SI_ENUM_BASE, chipid));
++ ci->pub.chip = regdata & CID_ID_MASK;
++ ci->pub.chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
++ socitype = (regdata & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
++
++ brcmf_chip_name(ci->pub.chip, ci->pub.name, sizeof(ci->pub.name));
++ brcmf_dbg(INFO, "found %s chip: BCM%s, rev=%d\n",
++ socitype == SOCI_SB ? "SB" : "AXI", ci->pub.name,
++ ci->pub.chiprev);
++
++ if (socitype == SOCI_SB) {
++ if (ci->pub.chip != BRCM_CC_4329_CHIP_ID) {
++ brcmf_err("SB chip is not supported\n");
++ return -ENODEV;
++ }
++ ci->iscoreup = brcmf_chip_sb_iscoreup;
++ ci->coredisable = brcmf_chip_sb_coredisable;
++ ci->resetcore = brcmf_chip_sb_resetcore;
++
++ core = brcmf_chip_add_core(ci, BCMA_CORE_CHIPCOMMON,
++ SI_ENUM_BASE, 0);
++ brcmf_chip_sb_corerev(ci, core);
++ core = brcmf_chip_add_core(ci, BCMA_CORE_SDIO_DEV,
++ BCM4329_CORE_BUS_BASE, 0);
++ brcmf_chip_sb_corerev(ci, core);
++ core = brcmf_chip_add_core(ci, BCMA_CORE_INTERNAL_MEM,
++ BCM4329_CORE_SOCRAM_BASE, 0);
++ brcmf_chip_sb_corerev(ci, core);
++ core = brcmf_chip_add_core(ci, BCMA_CORE_ARM_CM3,
++ BCM4329_CORE_ARM_BASE, 0);
++ brcmf_chip_sb_corerev(ci, core);
++
++ core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0);
++ brcmf_chip_sb_corerev(ci, core);
++ } else if (socitype == SOCI_AI) {
++ ci->iscoreup = brcmf_chip_ai_iscoreup;
++ ci->coredisable = brcmf_chip_ai_coredisable;
++ ci->resetcore = brcmf_chip_ai_resetcore;
++
++ brcmf_chip_dmp_erom_scan(ci);
++ } else {
++ brcmf_err("chip backplane type %u is not supported\n",
++ socitype);
++ return -ENODEV;
++ }
++
++ ret = brcmf_chip_cores_check(ci);
++ if (ret)
++ return ret;
++
++ /* assure chip is passive for core access */
++ brcmf_chip_set_passive(&ci->pub);
++ return brcmf_chip_get_raminfo(ci);
++}
++
++static void brcmf_chip_disable_arm(struct brcmf_chip_priv *chip, u16 id)
++{
++ struct brcmf_core *core;
++ struct brcmf_core_priv *cr4;
++ u32 val;
++
++
++ core = brcmf_chip_get_core(&chip->pub, id);
++ if (!core)
++ return;
++
++ switch (id) {
++ case BCMA_CORE_ARM_CM3:
++ brcmf_chip_coredisable(core, 0, 0);
++ break;
++ case BCMA_CORE_ARM_CR4:
++ cr4 = container_of(core, struct brcmf_core_priv, pub);
++
++ /* clear all IOCTL bits except HALT bit */
++ val = chip->ops->read32(chip->ctx, cr4->wrapbase + BCMA_IOCTL);
++ val &= ARMCR4_BCMA_IOCTL_CPUHALT;
++ brcmf_chip_resetcore(core, val, ARMCR4_BCMA_IOCTL_CPUHALT,
++ ARMCR4_BCMA_IOCTL_CPUHALT);
++ break;
++ default:
++ brcmf_err("unknown id: %u\n", id);
++ break;
++ }
++}
++
++static int brcmf_chip_setup(struct brcmf_chip_priv *chip)
++{
++ struct brcmf_chip *pub;
++ struct brcmf_core_priv *cc;
++ u32 base;
++ u32 val;
++ int ret = 0;
++
++ pub = &chip->pub;
++ cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
++ base = cc->pub.base;
++
++ /* get chipcommon capabilites */
++ pub->cc_caps = chip->ops->read32(chip->ctx,
++ CORE_CC_REG(base, capabilities));
++
++ /* get pmu caps & rev */
++ if (pub->cc_caps & CC_CAP_PMU) {
++ val = chip->ops->read32(chip->ctx,
++ CORE_CC_REG(base, pmucapabilities));
++ pub->pmurev = val & PCAP_REV_MASK;
++ pub->pmucaps = val;
++ }
++
++ brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n",
++ cc->pub.rev, pub->pmurev, pub->pmucaps);
++
++ /* execute bus core specific setup */
++ if (chip->ops->setup)
++ ret = chip->ops->setup(chip->ctx, pub);
++
++ return ret;
++}
++
++struct brcmf_chip *brcmf_chip_attach(void *ctx,
++ const struct brcmf_buscore_ops *ops)
++{
++ struct brcmf_chip_priv *chip;
++ int err = 0;
++
++ if (WARN_ON(!ops->read32))
++ err = -EINVAL;
++ if (WARN_ON(!ops->write32))
++ err = -EINVAL;
++ if (WARN_ON(!ops->prepare))
++ err = -EINVAL;
++ if (WARN_ON(!ops->activate))
++ err = -EINVAL;
++ if (err < 0)
++ return ERR_PTR(-EINVAL);
++
++ chip = kzalloc(sizeof(*chip), GFP_KERNEL);
++ if (!chip)
++ return ERR_PTR(-ENOMEM);
++
++ INIT_LIST_HEAD(&chip->cores);
++ chip->num_cores = 0;
++ chip->ops = ops;
++ chip->ctx = ctx;
++
++ err = ops->prepare(ctx);
++ if (err < 0)
++ goto fail;
++
++ err = brcmf_chip_recognition(chip);
++ if (err < 0)
++ goto fail;
++
++ err = brcmf_chip_setup(chip);
++ if (err < 0)
++ goto fail;
++
++ return &chip->pub;
++
++fail:
++ brcmf_chip_detach(&chip->pub);
++ return ERR_PTR(err);
++}
++
++void brcmf_chip_detach(struct brcmf_chip *pub)
++{
++ struct brcmf_chip_priv *chip;
++ struct brcmf_core_priv *core;
++ struct brcmf_core_priv *tmp;
++
++ chip = container_of(pub, struct brcmf_chip_priv, pub);
++ list_for_each_entry_safe(core, tmp, &chip->cores, list) {
++ list_del(&core->list);
++ kfree(core);
++ }
++ kfree(chip);
++}
++
++struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *pub, u16 coreid)
++{
++ struct brcmf_chip_priv *chip;
++ struct brcmf_core_priv *core;
++
++ chip = container_of(pub, struct brcmf_chip_priv, pub);
++ list_for_each_entry(core, &chip->cores, list)
++ if (core->pub.id == coreid)
++ return &core->pub;
++
++ return NULL;
++}
++
++struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *pub)
++{
++ struct brcmf_chip_priv *chip;
++ struct brcmf_core_priv *cc;
++
++ chip = container_of(pub, struct brcmf_chip_priv, pub);
++ cc = list_first_entry(&chip->cores, struct brcmf_core_priv, list);
++ if (WARN_ON(!cc || cc->pub.id != BCMA_CORE_CHIPCOMMON))
++ return brcmf_chip_get_core(pub, BCMA_CORE_CHIPCOMMON);
++ return &cc->pub;
++}
++
++bool brcmf_chip_iscoreup(struct brcmf_core *pub)
++{
++ struct brcmf_core_priv *core;
++
++ core = container_of(pub, struct brcmf_core_priv, pub);
++ return core->chip->iscoreup(core);
++}
++
++void brcmf_chip_coredisable(struct brcmf_core *pub, u32 prereset, u32 reset)
++{
++ struct brcmf_core_priv *core;
++
++ core = container_of(pub, struct brcmf_core_priv, pub);
++ core->chip->coredisable(core, prereset, reset);
++}
++
++void brcmf_chip_resetcore(struct brcmf_core *pub, u32 prereset, u32 reset,
++ u32 postreset)
++{
++ struct brcmf_core_priv *core;
++
++ core = container_of(pub, struct brcmf_core_priv, pub);
++ core->chip->resetcore(core, prereset, reset, postreset);
++}
++
++static void
++brcmf_chip_cm3_set_passive(struct brcmf_chip_priv *chip)
++{
++ struct brcmf_core *core;
++ struct brcmf_core_priv *sr;
++
++ brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CM3);
++ core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
++ brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
++ D11_BCMA_IOCTL_PHYCLOCKEN,
++ D11_BCMA_IOCTL_PHYCLOCKEN,
++ D11_BCMA_IOCTL_PHYCLOCKEN);
++ core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
++ brcmf_chip_resetcore(core, 0, 0, 0);
++
++ /* disable bank #3 remap for this device */
++ if (chip->pub.chip == BRCM_CC_43430_CHIP_ID) {
++ sr = container_of(core, struct brcmf_core_priv, pub);
++ brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankidx), 3);
++ brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0);
++ }
++}
++
++static bool brcmf_chip_cm3_set_active(struct brcmf_chip_priv *chip)
++{
++ struct brcmf_core *core;
++
++ core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_INTERNAL_MEM);
++ if (!brcmf_chip_iscoreup(core)) {
++ brcmf_err("SOCRAM core is down after reset?\n");
++ return false;
++ }
++
++ chip->ops->activate(chip->ctx, &chip->pub, 0);
++
++ core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CM3);
++ brcmf_chip_resetcore(core, 0, 0, 0);
++
++ return true;
++}
++
++static inline void
++brcmf_chip_cr4_set_passive(struct brcmf_chip_priv *chip)
++{
++ struct brcmf_core *core;
++
++ brcmf_chip_disable_arm(chip, BCMA_CORE_ARM_CR4);
++
++ core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_80211);
++ brcmf_chip_resetcore(core, D11_BCMA_IOCTL_PHYRESET |
++ D11_BCMA_IOCTL_PHYCLOCKEN,
++ D11_BCMA_IOCTL_PHYCLOCKEN,
++ D11_BCMA_IOCTL_PHYCLOCKEN);
++}
++
++static bool brcmf_chip_cr4_set_active(struct brcmf_chip_priv *chip, u32 rstvec)
++{
++ struct brcmf_core *core;
++
++ chip->ops->activate(chip->ctx, &chip->pub, rstvec);
++
++ /* restore ARM */
++ core = brcmf_chip_get_core(&chip->pub, BCMA_CORE_ARM_CR4);
++ brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0);
++
++ return true;
++}
++
++void brcmf_chip_set_passive(struct brcmf_chip *pub)
++{
++ struct brcmf_chip_priv *chip;
++ struct brcmf_core *arm;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ chip = container_of(pub, struct brcmf_chip_priv, pub);
++ arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
++ if (arm) {
++ brcmf_chip_cr4_set_passive(chip);
++ return;
++ }
++
++ brcmf_chip_cm3_set_passive(chip);
++}
++
++bool brcmf_chip_set_active(struct brcmf_chip *pub, u32 rstvec)
++{
++ struct brcmf_chip_priv *chip;
++ struct brcmf_core *arm;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ chip = container_of(pub, struct brcmf_chip_priv, pub);
++ arm = brcmf_chip_get_core(pub, BCMA_CORE_ARM_CR4);
++ if (arm)
++ return brcmf_chip_cr4_set_active(chip, rstvec);
++
++ return brcmf_chip_cm3_set_active(chip);
++}
++
++bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
++{
++ u32 base, addr, reg, pmu_cc3_mask = ~0;
++ struct brcmf_chip_priv *chip;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* old chips with PMU version less than 17 don't support save restore */
++ if (pub->pmurev < 17)
++ return false;
++
++ base = brcmf_chip_get_chipcommon(pub)->base;
++ chip = container_of(pub, struct brcmf_chip_priv, pub);
++
++ switch (pub->chip) {
++ case BRCM_CC_4354_CHIP_ID:
++ /* explicitly check SR engine enable bit */
++ pmu_cc3_mask = BIT(2);
++ /* fall-through */
++ case BRCM_CC_43241_CHIP_ID:
++ case BRCM_CC_4335_CHIP_ID:
++ case BRCM_CC_4339_CHIP_ID:
++ /* read PMU chipcontrol register 3 */
++ addr = CORE_CC_REG(base, chipcontrol_addr);
++ chip->ops->write32(chip->ctx, addr, 3);
++ addr = CORE_CC_REG(base, chipcontrol_data);
++ reg = chip->ops->read32(chip->ctx, addr);
++ return (reg & pmu_cc3_mask) != 0;
++ case BRCM_CC_43430_CHIP_ID:
++ addr = CORE_CC_REG(base, sr_control1);
++ reg = chip->ops->read32(chip->ctx, addr);
++ return reg != 0;
++ default:
++ addr = CORE_CC_REG(base, pmucapabilities_ext);
++ reg = chip->ops->read32(chip->ctx, addr);
++ if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
++ return false;
++
++ addr = CORE_CC_REG(base, retention_ctl);
++ reg = chip->ops->read32(chip->ctx, addr);
++ return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
++ PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
++ }
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/chip.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/chip.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/chip.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/chip.h 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,93 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMF_CHIP_H
++#define BRCMF_CHIP_H
++
++#include <linux/types.h>
++
++#define CORE_CC_REG(base, field) \
++ (base + offsetof(struct chipcregs, field))
++
++/**
++ * struct brcmf_chip - chip level information.
++ *
++ * @chip: chip identifier.
++ * @chiprev: chip revision.
++ * @cc_caps: chipcommon core capabilities.
++ * @pmucaps: PMU capabilities.
++ * @pmurev: PMU revision.
++ * @rambase: RAM base address (only applicable for ARM CR4 chips).
++ * @ramsize: amount of RAM on chip including retention.
++ * @srsize: amount of retention RAM on chip.
++ * @name: string representation of the chip identifier.
++ */
++struct brcmf_chip {
++ u32 chip;
++ u32 chiprev;
++ u32 cc_caps;
++ u32 pmucaps;
++ u32 pmurev;
++ u32 rambase;
++ u32 ramsize;
++ u32 srsize;
++ char name[8];
++};
++
++/**
++ * struct brcmf_core - core related information.
++ *
++ * @id: core identifier.
++ * @rev: core revision.
++ * @base: base address of core register space.
++ */
++struct brcmf_core {
++ u16 id;
++ u16 rev;
++ u32 base;
++};
++
++/**
++ * struct brcmf_buscore_ops - buscore specific callbacks.
++ *
++ * @read32: read 32-bit value over bus.
++ * @write32: write 32-bit value over bus.
++ * @prepare: prepare bus for core configuration.
++ * @setup: bus-specific core setup.
++ * @active: chip becomes active.
++ * The callback should use the provided @rstvec when non-zero.
++ */
++struct brcmf_buscore_ops {
++ u32 (*read32)(void *ctx, u32 addr);
++ void (*write32)(void *ctx, u32 addr, u32 value);
++ int (*prepare)(void *ctx);
++ int (*setup)(void *ctx, struct brcmf_chip *chip);
++ void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec);
++};
++
++struct brcmf_chip *brcmf_chip_attach(void *ctx,
++ const struct brcmf_buscore_ops *ops);
++void brcmf_chip_detach(struct brcmf_chip *chip);
++struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid);
++struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *chip);
++bool brcmf_chip_iscoreup(struct brcmf_core *core);
++void brcmf_chip_coredisable(struct brcmf_core *core, u32 prereset, u32 reset);
++void brcmf_chip_resetcore(struct brcmf_core *core, u32 prereset, u32 reset,
++ u32 postreset);
++void brcmf_chip_set_passive(struct brcmf_chip *ci);
++bool brcmf_chip_set_active(struct brcmf_chip *ci, u32 rstvec);
++bool brcmf_chip_sr_capable(struct brcmf_chip *pub);
++
++#endif /* BRCMF_AXIDMP_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/common.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/common.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/common.c 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,198 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/netdevice.h>
++#include <brcmu_wifi.h>
++#include <brcmu_utils.h>
++#include "core.h"
++#include "bus.h"
++#include "debug.h"
++#include "fwil.h"
++#include "fwil_types.h"
++#include "tracepoint.h"
++#include "common.h"
++
++const u8 ALLFFMAC[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
++
++#define BRCMF_DEFAULT_BCN_TIMEOUT 3
++#define BRCMF_DEFAULT_SCAN_CHANNEL_TIME 40
++#define BRCMF_DEFAULT_SCAN_UNASSOC_TIME 40
++
++/* boost value for RSSI_DELTA in preferred join selection */
++#define BRCMF_JOIN_PREF_RSSI_BOOST 8
++
++int brcmf_c_preinit_dcmds(struct brcmf_if *ifp)
++{
++ s8 eventmask[BRCMF_EVENTING_MASK_LEN];
++ u8 buf[BRCMF_DCMD_SMLEN];
++ struct brcmf_join_pref_params join_pref_params[2];
++ struct brcmf_rev_info_le revinfo;
++ struct brcmf_rev_info *ri;
++ char *ptr;
++ s32 err;
++
++ /* retreive mac address */
++ err = brcmf_fil_iovar_data_get(ifp, "cur_etheraddr", ifp->mac_addr,
++ sizeof(ifp->mac_addr));
++ if (err < 0) {
++ brcmf_err("Retreiving cur_etheraddr failed, %d\n", err);
++ goto done;
++ }
++ memcpy(ifp->drvr->mac, ifp->mac_addr, sizeof(ifp->drvr->mac));
++
++ err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_REVINFO,
++ &revinfo, sizeof(revinfo));
++ ri = &ifp->drvr->revinfo;
++ if (err < 0) {
++ brcmf_err("retrieving revision info failed, %d\n", err);
++ } else {
++ ri->vendorid = le32_to_cpu(revinfo.vendorid);
++ ri->deviceid = le32_to_cpu(revinfo.deviceid);
++ ri->radiorev = le32_to_cpu(revinfo.radiorev);
++ ri->chiprev = le32_to_cpu(revinfo.chiprev);
++ ri->corerev = le32_to_cpu(revinfo.corerev);
++ ri->boardid = le32_to_cpu(revinfo.boardid);
++ ri->boardvendor = le32_to_cpu(revinfo.boardvendor);
++ ri->boardrev = le32_to_cpu(revinfo.boardrev);
++ ri->driverrev = le32_to_cpu(revinfo.driverrev);
++ ri->ucoderev = le32_to_cpu(revinfo.ucoderev);
++ ri->bus = le32_to_cpu(revinfo.bus);
++ ri->chipnum = le32_to_cpu(revinfo.chipnum);
++ ri->phytype = le32_to_cpu(revinfo.phytype);
++ ri->phyrev = le32_to_cpu(revinfo.phyrev);
++ ri->anarev = le32_to_cpu(revinfo.anarev);
++ ri->chippkg = le32_to_cpu(revinfo.chippkg);
++ ri->nvramrev = le32_to_cpu(revinfo.nvramrev);
++ }
++ ri->result = err;
++
++ /* query for 'ver' to get version info from firmware */
++ memset(buf, 0, sizeof(buf));
++ strcpy(buf, "ver");
++ err = brcmf_fil_iovar_data_get(ifp, "ver", buf, sizeof(buf));
++ if (err < 0) {
++ brcmf_err("Retreiving version information failed, %d\n",
++ err);
++ goto done;
++ }
++ ptr = (char *)buf;
++ strsep(&ptr, "\n");
++
++ /* Print fw version info */
++ brcmf_err("Firmware version = %s\n", buf);
++
++ /* locate firmware version number for ethtool */
++ ptr = strrchr(buf, ' ') + 1;
++ strlcpy(ifp->drvr->fwver, ptr, sizeof(ifp->drvr->fwver));
++
++ /* set mpc */
++ err = brcmf_fil_iovar_int_set(ifp, "mpc", 1);
++ if (err) {
++ brcmf_err("failed setting mpc\n");
++ goto done;
++ }
++
++ /*
++ * Setup timeout if Beacons are lost and roam is off to report
++ * link down
++ */
++ err = brcmf_fil_iovar_int_set(ifp, "bcn_timeout",
++ BRCMF_DEFAULT_BCN_TIMEOUT);
++ if (err) {
++ brcmf_err("bcn_timeout error (%d)\n", err);
++ goto done;
++ }
++
++ /* Enable/Disable build-in roaming to allowed ext supplicant to take
++ * of romaing
++ */
++ err = brcmf_fil_iovar_int_set(ifp, "roam_off", 1);
++ if (err) {
++ brcmf_err("roam_off error (%d)\n", err);
++ goto done;
++ }
++
++ /* Setup join_pref to select target by RSSI(with boost on 5GHz) */
++ join_pref_params[0].type = BRCMF_JOIN_PREF_RSSI_DELTA;
++ join_pref_params[0].len = 2;
++ join_pref_params[0].rssi_gain = BRCMF_JOIN_PREF_RSSI_BOOST;
++ join_pref_params[0].band = WLC_BAND_5G;
++ join_pref_params[1].type = BRCMF_JOIN_PREF_RSSI;
++ join_pref_params[1].len = 2;
++ join_pref_params[1].rssi_gain = 0;
++ join_pref_params[1].band = 0;
++ err = brcmf_fil_iovar_data_set(ifp, "join_pref", join_pref_params,
++ sizeof(join_pref_params));
++ if (err)
++ brcmf_err("Set join_pref error (%d)\n", err);
++
++ /* Setup event_msgs, enable E_IF */
++ err = brcmf_fil_iovar_data_get(ifp, "event_msgs", eventmask,
++ BRCMF_EVENTING_MASK_LEN);
++ if (err) {
++ brcmf_err("Get event_msgs error (%d)\n", err);
++ goto done;
++ }
++ setbit(eventmask, BRCMF_E_IF);
++ err = brcmf_fil_iovar_data_set(ifp, "event_msgs", eventmask,
++ BRCMF_EVENTING_MASK_LEN);
++ if (err) {
++ brcmf_err("Set event_msgs error (%d)\n", err);
++ goto done;
++ }
++
++ /* Setup default scan channel time */
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_CHANNEL_TIME,
++ BRCMF_DEFAULT_SCAN_CHANNEL_TIME);
++ if (err) {
++ brcmf_err("BRCMF_C_SET_SCAN_CHANNEL_TIME error (%d)\n",
++ err);
++ goto done;
++ }
++
++ /* Setup default scan unassoc time */
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_UNASSOC_TIME,
++ BRCMF_DEFAULT_SCAN_UNASSOC_TIME);
++ if (err) {
++ brcmf_err("BRCMF_C_SET_SCAN_UNASSOC_TIME error (%d)\n",
++ err);
++ goto done;
++ }
++
++ /* do bus specific preinit here */
++ err = brcmf_bus_preinit(ifp->drvr->bus_if);
++done:
++ return err;
++}
++
++#if defined(CONFIG_BRCM_TRACING) || defined(CONFIG_BRCMDBG)
++void __brcmf_dbg(u32 level, const char *func, const char *fmt, ...)
++{
++ struct va_format vaf = {
++ .fmt = fmt,
++ };
++ va_list args;
++
++ va_start(args, fmt);
++ vaf.va = &args;
++ if (brcmf_msg_level & level)
++ pr_debug("%s %pV", func, &vaf);
++ trace_brcmf_dbg(level, func, &vaf);
++ va_end(args);
++}
++#endif
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/common.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/common.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/common.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/common.h 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,20 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_COMMON_H
++#define BRCMFMAC_COMMON_H
++
++extern const u8 ALLFFMAC[ETH_ALEN];
++
++#endif /* BRCMFMAC_COMMON_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/commonring.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/commonring.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/commonring.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/commonring.c 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,255 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/types.h>
++#include <linux/netdevice.h>
++
++#include <brcmu_utils.h>
++#include <brcmu_wifi.h>
++
++#include "core.h"
++#include "commonring.h"
++
++void brcmf_commonring_register_cb(struct brcmf_commonring *commonring,
++ int (*cr_ring_bell)(void *ctx),
++ int (*cr_update_rptr)(void *ctx),
++ int (*cr_update_wptr)(void *ctx),
++ int (*cr_write_rptr)(void *ctx),
++ int (*cr_write_wptr)(void *ctx), void *ctx)
++{
++ commonring->cr_ring_bell = cr_ring_bell;
++ commonring->cr_update_rptr = cr_update_rptr;
++ commonring->cr_update_wptr = cr_update_wptr;
++ commonring->cr_write_rptr = cr_write_rptr;
++ commonring->cr_write_wptr = cr_write_wptr;
++ commonring->cr_ctx = ctx;
++}
++
++
++void brcmf_commonring_config(struct brcmf_commonring *commonring, u16 depth,
++ u16 item_len, void *buf_addr)
++{
++ commonring->depth = depth;
++ commonring->item_len = item_len;
++ commonring->buf_addr = buf_addr;
++ if (!commonring->inited) {
++ spin_lock_init(&commonring->lock);
++ commonring->inited = true;
++ }
++ commonring->r_ptr = 0;
++ if (commonring->cr_write_rptr)
++ commonring->cr_write_rptr(commonring->cr_ctx);
++ commonring->w_ptr = 0;
++ if (commonring->cr_write_wptr)
++ commonring->cr_write_wptr(commonring->cr_ctx);
++ commonring->f_ptr = 0;
++}
++
++
++void brcmf_commonring_lock(struct brcmf_commonring *commonring)
++ __acquires(&commonring->lock)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&commonring->lock, flags);
++ commonring->flags = flags;
++}
++
++
++void brcmf_commonring_unlock(struct brcmf_commonring *commonring)
++ __releases(&commonring->lock)
++{
++ spin_unlock_irqrestore(&commonring->lock, commonring->flags);
++}
++
++
++bool brcmf_commonring_write_available(struct brcmf_commonring *commonring)
++{
++ u16 available;
++ bool retry = true;
++
++again:
++ if (commonring->r_ptr <= commonring->w_ptr)
++ available = commonring->depth - commonring->w_ptr +
++ commonring->r_ptr;
++ else
++ available = commonring->r_ptr - commonring->w_ptr;
++
++ if (available > 1) {
++ if (!commonring->was_full)
++ return true;
++ if (available > commonring->depth / 8) {
++ commonring->was_full = false;
++ return true;
++ }
++ if (retry) {
++ if (commonring->cr_update_rptr)
++ commonring->cr_update_rptr(commonring->cr_ctx);
++ retry = false;
++ goto again;
++ }
++ return false;
++ }
++
++ if (retry) {
++ if (commonring->cr_update_rptr)
++ commonring->cr_update_rptr(commonring->cr_ctx);
++ retry = false;
++ goto again;
++ }
++
++ commonring->was_full = true;
++ return false;
++}
++
++
++void *brcmf_commonring_reserve_for_write(struct brcmf_commonring *commonring)
++{
++ void *ret_ptr;
++ u16 available;
++ bool retry = true;
++
++again:
++ if (commonring->r_ptr <= commonring->w_ptr)
++ available = commonring->depth - commonring->w_ptr +
++ commonring->r_ptr;
++ else
++ available = commonring->r_ptr - commonring->w_ptr;
++
++ if (available > 1) {
++ ret_ptr = commonring->buf_addr +
++ (commonring->w_ptr * commonring->item_len);
++ commonring->w_ptr++;
++ if (commonring->w_ptr == commonring->depth)
++ commonring->w_ptr = 0;
++ return ret_ptr;
++ }
++
++ if (retry) {
++ if (commonring->cr_update_rptr)
++ commonring->cr_update_rptr(commonring->cr_ctx);
++ retry = false;
++ goto again;
++ }
++
++ commonring->was_full = true;
++ return NULL;
++}
++
++
++void *
++brcmf_commonring_reserve_for_write_multiple(struct brcmf_commonring *commonring,
++ u16 n_items, u16 *alloced)
++{
++ void *ret_ptr;
++ u16 available;
++ bool retry = true;
++
++again:
++ if (commonring->r_ptr <= commonring->w_ptr)
++ available = commonring->depth - commonring->w_ptr +
++ commonring->r_ptr;
++ else
++ available = commonring->r_ptr - commonring->w_ptr;
++
++ if (available > 1) {
++ ret_ptr = commonring->buf_addr +
++ (commonring->w_ptr * commonring->item_len);
++ *alloced = min_t(u16, n_items, available - 1);
++ if (*alloced + commonring->w_ptr > commonring->depth)
++ *alloced = commonring->depth - commonring->w_ptr;
++ commonring->w_ptr += *alloced;
++ if (commonring->w_ptr == commonring->depth)
++ commonring->w_ptr = 0;
++ return ret_ptr;
++ }
++
++ if (retry) {
++ if (commonring->cr_update_rptr)
++ commonring->cr_update_rptr(commonring->cr_ctx);
++ retry = false;
++ goto again;
++ }
++
++ commonring->was_full = true;
++ return NULL;
++}
++
++
++int brcmf_commonring_write_complete(struct brcmf_commonring *commonring)
++{
++ void *address;
++
++ address = commonring->buf_addr;
++ address += (commonring->f_ptr * commonring->item_len);
++ if (commonring->f_ptr > commonring->w_ptr) {
++ address = commonring->buf_addr;
++ commonring->f_ptr = 0;
++ }
++
++ commonring->f_ptr = commonring->w_ptr;
++
++ if (commonring->cr_write_wptr)
++ commonring->cr_write_wptr(commonring->cr_ctx);
++ if (commonring->cr_ring_bell)
++ return commonring->cr_ring_bell(commonring->cr_ctx);
++
++ return -EIO;
++}
++
++
++void brcmf_commonring_write_cancel(struct brcmf_commonring *commonring,
++ u16 n_items)
++{
++ if (commonring->w_ptr == 0)
++ commonring->w_ptr = commonring->depth - n_items;
++ else
++ commonring->w_ptr -= n_items;
++}
++
++
++void *brcmf_commonring_get_read_ptr(struct brcmf_commonring *commonring,
++ u16 *n_items)
++{
++ void *ret_addr;
++
++ if (commonring->cr_update_wptr)
++ commonring->cr_update_wptr(commonring->cr_ctx);
++
++ *n_items = (commonring->w_ptr >= commonring->r_ptr) ?
++ (commonring->w_ptr - commonring->r_ptr) :
++ (commonring->depth - commonring->r_ptr);
++
++ if (*n_items == 0)
++ return NULL;
++
++ ret_addr = commonring->buf_addr +
++ (commonring->r_ptr * commonring->item_len);
++
++ commonring->r_ptr += *n_items;
++ if (commonring->r_ptr == commonring->depth)
++ commonring->r_ptr = 0;
++
++ return ret_addr;
++}
++
++
++int brcmf_commonring_read_complete(struct brcmf_commonring *commonring)
++{
++ if (commonring->cr_write_rptr)
++ return commonring->cr_write_rptr(commonring->cr_ctx);
++
++ return -EIO;
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/commonring.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/commonring.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/commonring.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/commonring.h 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,71 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_COMMONRING_H
++#define BRCMFMAC_COMMONRING_H
++
++
++struct brcmf_commonring {
++ u16 r_ptr;
++ u16 w_ptr;
++ u16 f_ptr;
++ u16 depth;
++ u16 item_len;
++
++ void *buf_addr;
++
++ int (*cr_ring_bell)(void *ctx);
++ int (*cr_update_rptr)(void *ctx);
++ int (*cr_update_wptr)(void *ctx);
++ int (*cr_write_rptr)(void *ctx);
++ int (*cr_write_wptr)(void *ctx);
++
++ void *cr_ctx;
++
++ spinlock_t lock;
++ unsigned long flags;
++ bool inited;
++ bool was_full;
++
++ atomic_t outstanding_tx;
++};
++
++
++void brcmf_commonring_register_cb(struct brcmf_commonring *commonring,
++ int (*cr_ring_bell)(void *ctx),
++ int (*cr_update_rptr)(void *ctx),
++ int (*cr_update_wptr)(void *ctx),
++ int (*cr_write_rptr)(void *ctx),
++ int (*cr_write_wptr)(void *ctx), void *ctx);
++void brcmf_commonring_config(struct brcmf_commonring *commonring, u16 depth,
++ u16 item_len, void *buf_addr);
++void brcmf_commonring_lock(struct brcmf_commonring *commonring);
++void brcmf_commonring_unlock(struct brcmf_commonring *commonring);
++bool brcmf_commonring_write_available(struct brcmf_commonring *commonring);
++void *brcmf_commonring_reserve_for_write(struct brcmf_commonring *commonring);
++void *
++brcmf_commonring_reserve_for_write_multiple(struct brcmf_commonring *commonring,
++ u16 n_items, u16 *alloced);
++int brcmf_commonring_write_complete(struct brcmf_commonring *commonring);
++void brcmf_commonring_write_cancel(struct brcmf_commonring *commonring,
++ u16 n_items);
++void *brcmf_commonring_get_read_ptr(struct brcmf_commonring *commonring,
++ u16 *n_items);
++int brcmf_commonring_read_complete(struct brcmf_commonring *commonring);
++
++#define brcmf_commonring_n_items(commonring) (commonring->depth)
++#define brcmf_commonring_len_item(commonring) (commonring->item_len)
++
++
++#endif /* BRCMFMAC_COMMONRING_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/core.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/core.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/core.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/core.c 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,1182 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/etherdevice.h>
++#include <linux/module.h>
++#include <net/cfg80211.h>
++#include <net/rtnetlink.h>
++#include <brcmu_utils.h>
++#include <brcmu_wifi.h>
++
++#include "core.h"
++#include "bus.h"
++#include "debug.h"
++#include "fwil_types.h"
++#include "p2p.h"
++#include "cfg80211.h"
++#include "fwil.h"
++#include "fwsignal.h"
++#include "feature.h"
++#include "proto.h"
++#include "pcie.h"
++
++MODULE_AUTHOR("Broadcom Corporation");
++MODULE_DESCRIPTION("Broadcom 802.11 wireless LAN fullmac driver.");
++MODULE_LICENSE("Dual BSD/GPL");
++
++#define MAX_WAIT_FOR_8021X_TX 50 /* msecs */
++
++/* AMPDU rx reordering definitions */
++#define BRCMF_RXREORDER_FLOWID_OFFSET 0
++#define BRCMF_RXREORDER_MAXIDX_OFFSET 2
++#define BRCMF_RXREORDER_FLAGS_OFFSET 4
++#define BRCMF_RXREORDER_CURIDX_OFFSET 6
++#define BRCMF_RXREORDER_EXPIDX_OFFSET 8
++
++#define BRCMF_RXREORDER_DEL_FLOW 0x01
++#define BRCMF_RXREORDER_FLUSH_ALL 0x02
++#define BRCMF_RXREORDER_CURIDX_VALID 0x04
++#define BRCMF_RXREORDER_EXPIDX_VALID 0x08
++#define BRCMF_RXREORDER_NEW_HOLE 0x10
++
++/* Error bits */
++int brcmf_msg_level;
++module_param_named(debug, brcmf_msg_level, int, S_IRUSR | S_IWUSR);
++MODULE_PARM_DESC(debug, "level of debug output");
++
++/* P2P0 enable */
++static int brcmf_p2p_enable;
++#ifdef CONFIG_BRCMDBG
++module_param_named(p2pon, brcmf_p2p_enable, int, 0);
++MODULE_PARM_DESC(p2pon, "enable p2p management functionality");
++#endif
++
++char *brcmf_ifname(struct brcmf_pub *drvr, int ifidx)
++{
++ if (ifidx < 0 || ifidx >= BRCMF_MAX_IFS) {
++ brcmf_err("ifidx %d out of range\n", ifidx);
++ return "<if_bad>";
++ }
++
++ if (drvr->iflist[ifidx] == NULL) {
++ brcmf_err("null i/f %d\n", ifidx);
++ return "<if_null>";
++ }
++
++ if (drvr->iflist[ifidx]->ndev)
++ return drvr->iflist[ifidx]->ndev->name;
++
++ return "<if_none>";
++}
++
++static void _brcmf_set_multicast_list(struct work_struct *work)
++{
++ struct brcmf_if *ifp;
++ struct net_device *ndev;
++ struct netdev_hw_addr *ha;
++ u32 cmd_value, cnt;
++ __le32 cnt_le;
++ char *buf, *bufp;
++ u32 buflen;
++ s32 err;
++
++ ifp = container_of(work, struct brcmf_if, multicast_work);
++
++ brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
++
++ ndev = ifp->ndev;
++
++ /* Determine initial value of allmulti flag */
++ cmd_value = (ndev->flags & IFF_ALLMULTI) ? true : false;
++
++ /* Send down the multicast list first. */
++ cnt = netdev_mc_count(ndev);
++ buflen = sizeof(cnt) + (cnt * ETH_ALEN);
++ buf = kmalloc(buflen, GFP_ATOMIC);
++ if (!buf)
++ return;
++ bufp = buf;
++
++ cnt_le = cpu_to_le32(cnt);
++ memcpy(bufp, &cnt_le, sizeof(cnt_le));
++ bufp += sizeof(cnt_le);
++
++ netdev_for_each_mc_addr(ha, ndev) {
++ if (!cnt)
++ break;
++ memcpy(bufp, ha->addr, ETH_ALEN);
++ bufp += ETH_ALEN;
++ cnt--;
++ }
++
++ err = brcmf_fil_iovar_data_set(ifp, "mcast_list", buf, buflen);
++ if (err < 0) {
++ brcmf_err("Setting mcast_list failed, %d\n", err);
++ cmd_value = cnt ? true : cmd_value;
++ }
++
++ kfree(buf);
++
++ /*
++ * Now send the allmulti setting. This is based on the setting in the
++ * net_device flags, but might be modified above to be turned on if we
++ * were trying to set some addresses and dongle rejected it...
++ */
++ err = brcmf_fil_iovar_int_set(ifp, "allmulti", cmd_value);
++ if (err < 0)
++ brcmf_err("Setting allmulti failed, %d\n", err);
++
++ /*Finally, pick up the PROMISC flag */
++ cmd_value = (ndev->flags & IFF_PROMISC) ? true : false;
++ err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PROMISC, cmd_value);
++ if (err < 0)
++ brcmf_err("Setting BRCMF_C_SET_PROMISC failed, %d\n",
++ err);
++}
++
++static void
++_brcmf_set_mac_address(struct work_struct *work)
++{
++ struct brcmf_if *ifp;
++ s32 err;
++
++ ifp = container_of(work, struct brcmf_if, setmacaddr_work);
++
++ brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
++
++ err = brcmf_fil_iovar_data_set(ifp, "cur_etheraddr", ifp->mac_addr,
++ ETH_ALEN);
++ if (err < 0) {
++ brcmf_err("Setting cur_etheraddr failed, %d\n", err);
++ } else {
++ brcmf_dbg(TRACE, "MAC address updated to %pM\n",
++ ifp->mac_addr);
++ memcpy(ifp->ndev->dev_addr, ifp->mac_addr, ETH_ALEN);
++ }
++}
++
++static int brcmf_netdev_set_mac_address(struct net_device *ndev, void *addr)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct sockaddr *sa = (struct sockaddr *)addr;
++
++ memcpy(&ifp->mac_addr, sa->sa_data, ETH_ALEN);
++ schedule_work(&ifp->setmacaddr_work);
++ return 0;
++}
++
++static void brcmf_netdev_set_multicast_list(struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++
++ schedule_work(&ifp->multicast_work);
++}
++
++static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb,
++ struct net_device *ndev)
++{
++ int ret;
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_pub *drvr = ifp->drvr;
++ struct ethhdr *eh = (struct ethhdr *)(skb->data);
++
++ brcmf_dbg(DATA, "Enter, idx=%d\n", ifp->bssidx);
++
++ /* Can the device send data? */
++ if (drvr->bus_if->state != BRCMF_BUS_UP) {
++ brcmf_err("xmit rejected state=%d\n", drvr->bus_if->state);
++ netif_stop_queue(ndev);
++ dev_kfree_skb(skb);
++ ret = -ENODEV;
++ goto done;
++ }
++
++ if (!drvr->iflist[ifp->bssidx]) {
++ brcmf_err("bad ifidx %d\n", ifp->bssidx);
++ netif_stop_queue(ndev);
++ dev_kfree_skb(skb);
++ ret = -ENODEV;
++ goto done;
++ }
++
++ /* Make sure there's enough room for any header */
++ if (skb_headroom(skb) < drvr->hdrlen) {
++ struct sk_buff *skb2;
++
++ brcmf_dbg(INFO, "%s: insufficient headroom\n",
++ brcmf_ifname(drvr, ifp->bssidx));
++ drvr->bus_if->tx_realloc++;
++ skb2 = skb_realloc_headroom(skb, drvr->hdrlen);
++ dev_kfree_skb(skb);
++ skb = skb2;
++ if (skb == NULL) {
++ brcmf_err("%s: skb_realloc_headroom failed\n",
++ brcmf_ifname(drvr, ifp->bssidx));
++ ret = -ENOMEM;
++ goto done;
++ }
++ }
++
++ /* validate length for ether packet */
++ if (skb->len < sizeof(*eh)) {
++ ret = -EINVAL;
++ dev_kfree_skb(skb);
++ goto done;
++ }
++
++ if (eh->h_proto == htons(ETH_P_PAE))
++ atomic_inc(&ifp->pend_8021x_cnt);
++
++ ret = brcmf_fws_process_skb(ifp, skb);
++
++done:
++ if (ret) {
++ ifp->stats.tx_dropped++;
++ } else {
++ ifp->stats.tx_packets++;
++ ifp->stats.tx_bytes += skb->len;
++ }
++
++ /* Return ok: we always eat the packet */
++ return NETDEV_TX_OK;
++}
++
++void brcmf_txflowblock_if(struct brcmf_if *ifp,
++ enum brcmf_netif_stop_reason reason, bool state)
++{
++ unsigned long flags;
++
++ if (!ifp || !ifp->ndev)
++ return;
++
++ brcmf_dbg(TRACE, "enter: idx=%d stop=0x%X reason=%d state=%d\n",
++ ifp->bssidx, ifp->netif_stop, reason, state);
++
++ spin_lock_irqsave(&ifp->netif_stop_lock, flags);
++ if (state) {
++ if (!ifp->netif_stop)
++ netif_stop_queue(ifp->ndev);
++ ifp->netif_stop |= reason;
++ } else {
++ ifp->netif_stop &= ~reason;
++ if (!ifp->netif_stop)
++ netif_wake_queue(ifp->ndev);
++ }
++ spin_unlock_irqrestore(&ifp->netif_stop_lock, flags);
++}
++
++void brcmf_txflowblock(struct device *dev, bool state)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ brcmf_fws_bus_blocked(drvr, state);
++}
++
++void brcmf_netif_rx(struct brcmf_if *ifp, struct sk_buff *skb)
++{
++ skb->dev = ifp->ndev;
++ skb->protocol = eth_type_trans(skb, skb->dev);
++
++ if (skb->pkt_type == PACKET_MULTICAST)
++ ifp->stats.multicast++;
++
++ /* Process special event packets */
++ brcmf_fweh_process_skb(ifp->drvr, skb);
++
++ if (!(ifp->ndev->flags & IFF_UP)) {
++ brcmu_pkt_buf_free_skb(skb);
++ return;
++ }
++
++ ifp->stats.rx_bytes += skb->len;
++ ifp->stats.rx_packets++;
++
++ brcmf_dbg(DATA, "rx proto=0x%X\n", ntohs(skb->protocol));
++ if (in_interrupt())
++ netif_rx(skb);
++ else
++ /* If the receive is not processed inside an ISR,
++ * the softirqd must be woken explicitly to service
++ * the NET_RX_SOFTIRQ. This is handled by netif_rx_ni().
++ */
++ netif_rx_ni(skb);
++}
++
++static void brcmf_rxreorder_get_skb_list(struct brcmf_ampdu_rx_reorder *rfi,
++ u8 start, u8 end,
++ struct sk_buff_head *skb_list)
++{
++ /* initialize return list */
++ __skb_queue_head_init(skb_list);
++
++ if (rfi->pend_pkts == 0) {
++ brcmf_dbg(INFO, "no packets in reorder queue\n");
++ return;
++ }
++
++ do {
++ if (rfi->pktslots[start]) {
++ __skb_queue_tail(skb_list, rfi->pktslots[start]);
++ rfi->pktslots[start] = NULL;
++ }
++ start++;
++ if (start > rfi->max_idx)
++ start = 0;
++ } while (start != end);
++ rfi->pend_pkts -= skb_queue_len(skb_list);
++}
++
++static void brcmf_rxreorder_process_info(struct brcmf_if *ifp, u8 *reorder_data,
++ struct sk_buff *pkt)
++{
++ u8 flow_id, max_idx, cur_idx, exp_idx, end_idx;
++ struct brcmf_ampdu_rx_reorder *rfi;
++ struct sk_buff_head reorder_list;
++ struct sk_buff *pnext;
++ u8 flags;
++ u32 buf_size;
++
++ flow_id = reorder_data[BRCMF_RXREORDER_FLOWID_OFFSET];
++ flags = reorder_data[BRCMF_RXREORDER_FLAGS_OFFSET];
++
++ /* validate flags and flow id */
++ if (flags == 0xFF) {
++ brcmf_err("invalid flags...so ignore this packet\n");
++ brcmf_netif_rx(ifp, pkt);
++ return;
++ }
++
++ rfi = ifp->drvr->reorder_flows[flow_id];
++ if (flags & BRCMF_RXREORDER_DEL_FLOW) {
++ brcmf_dbg(INFO, "flow-%d: delete\n",
++ flow_id);
++
++ if (rfi == NULL) {
++ brcmf_dbg(INFO, "received flags to cleanup, but no flow (%d) yet\n",
++ flow_id);
++ brcmf_netif_rx(ifp, pkt);
++ return;
++ }
++
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, rfi->exp_idx,
++ &reorder_list);
++ /* add the last packet */
++ __skb_queue_tail(&reorder_list, pkt);
++ kfree(rfi);
++ ifp->drvr->reorder_flows[flow_id] = NULL;
++ goto netif_rx;
++ }
++ /* from here on we need a flow reorder instance */
++ if (rfi == NULL) {
++ buf_size = sizeof(*rfi);
++ max_idx = reorder_data[BRCMF_RXREORDER_MAXIDX_OFFSET];
++
++ buf_size += (max_idx + 1) * sizeof(pkt);
++
++ /* allocate space for flow reorder info */
++ brcmf_dbg(INFO, "flow-%d: start, maxidx %d\n",
++ flow_id, max_idx);
++ rfi = kzalloc(buf_size, GFP_ATOMIC);
++ if (rfi == NULL) {
++ brcmf_err("failed to alloc buffer\n");
++ brcmf_netif_rx(ifp, pkt);
++ return;
++ }
++
++ ifp->drvr->reorder_flows[flow_id] = rfi;
++ rfi->pktslots = (struct sk_buff **)(rfi+1);
++ rfi->max_idx = max_idx;
++ }
++ if (flags & BRCMF_RXREORDER_NEW_HOLE) {
++ if (rfi->pend_pkts) {
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx,
++ rfi->exp_idx,
++ &reorder_list);
++ WARN_ON(rfi->pend_pkts);
++ } else {
++ __skb_queue_head_init(&reorder_list);
++ }
++ rfi->cur_idx = reorder_data[BRCMF_RXREORDER_CURIDX_OFFSET];
++ rfi->exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
++ rfi->max_idx = reorder_data[BRCMF_RXREORDER_MAXIDX_OFFSET];
++ rfi->pktslots[rfi->cur_idx] = pkt;
++ rfi->pend_pkts++;
++ brcmf_dbg(DATA, "flow-%d: new hole %d (%d), pending %d\n",
++ flow_id, rfi->cur_idx, rfi->exp_idx, rfi->pend_pkts);
++ } else if (flags & BRCMF_RXREORDER_CURIDX_VALID) {
++ cur_idx = reorder_data[BRCMF_RXREORDER_CURIDX_OFFSET];
++ exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
++
++ if ((exp_idx == rfi->exp_idx) && (cur_idx != rfi->exp_idx)) {
++ /* still in the current hole */
++ /* enqueue the current on the buffer chain */
++ if (rfi->pktslots[cur_idx] != NULL) {
++ brcmf_dbg(INFO, "HOLE: ERROR buffer pending..free it\n");
++ brcmu_pkt_buf_free_skb(rfi->pktslots[cur_idx]);
++ rfi->pktslots[cur_idx] = NULL;
++ }
++ rfi->pktslots[cur_idx] = pkt;
++ rfi->pend_pkts++;
++ rfi->cur_idx = cur_idx;
++ brcmf_dbg(DATA, "flow-%d: store pkt %d (%d), pending %d\n",
++ flow_id, cur_idx, exp_idx, rfi->pend_pkts);
++
++ /* can return now as there is no reorder
++ * list to process.
++ */
++ return;
++ }
++ if (rfi->exp_idx == cur_idx) {
++ if (rfi->pktslots[cur_idx] != NULL) {
++ brcmf_dbg(INFO, "error buffer pending..free it\n");
++ brcmu_pkt_buf_free_skb(rfi->pktslots[cur_idx]);
++ rfi->pktslots[cur_idx] = NULL;
++ }
++ rfi->pktslots[cur_idx] = pkt;
++ rfi->pend_pkts++;
++
++ /* got the expected one. flush from current to expected
++ * and update expected
++ */
++ brcmf_dbg(DATA, "flow-%d: expected %d (%d), pending %d\n",
++ flow_id, cur_idx, exp_idx, rfi->pend_pkts);
++
++ rfi->cur_idx = cur_idx;
++ rfi->exp_idx = exp_idx;
++
++ brcmf_rxreorder_get_skb_list(rfi, cur_idx, exp_idx,
++ &reorder_list);
++ brcmf_dbg(DATA, "flow-%d: freeing buffers %d, pending %d\n",
++ flow_id, skb_queue_len(&reorder_list),
++ rfi->pend_pkts);
++ } else {
++ u8 end_idx;
++
++ brcmf_dbg(DATA, "flow-%d (0x%x): both moved, old %d/%d, new %d/%d\n",
++ flow_id, flags, rfi->cur_idx, rfi->exp_idx,
++ cur_idx, exp_idx);
++ if (flags & BRCMF_RXREORDER_FLUSH_ALL)
++ end_idx = rfi->exp_idx;
++ else
++ end_idx = exp_idx;
++
++ /* flush pkts first */
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, end_idx,
++ &reorder_list);
++
++ if (exp_idx == ((cur_idx + 1) % (rfi->max_idx + 1))) {
++ __skb_queue_tail(&reorder_list, pkt);
++ } else {
++ rfi->pktslots[cur_idx] = pkt;
++ rfi->pend_pkts++;
++ }
++ rfi->exp_idx = exp_idx;
++ rfi->cur_idx = cur_idx;
++ }
++ } else {
++ /* explicity window move updating the expected index */
++ exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
++
++ brcmf_dbg(DATA, "flow-%d (0x%x): change expected: %d -> %d\n",
++ flow_id, flags, rfi->exp_idx, exp_idx);
++ if (flags & BRCMF_RXREORDER_FLUSH_ALL)
++ end_idx = rfi->exp_idx;
++ else
++ end_idx = exp_idx;
++
++ brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, end_idx,
++ &reorder_list);
++ __skb_queue_tail(&reorder_list, pkt);
++ /* set the new expected idx */
++ rfi->exp_idx = exp_idx;
++ }
++netif_rx:
++ skb_queue_walk_safe(&reorder_list, pkt, pnext) {
++ __skb_unlink(pkt, &reorder_list);
++ brcmf_netif_rx(ifp, pkt);
++ }
++}
++
++void brcmf_rx_frame(struct device *dev, struct sk_buff *skb)
++{
++ struct brcmf_if *ifp;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ struct brcmf_skb_reorder_data *rd;
++ u8 ifidx;
++ int ret;
++
++ brcmf_dbg(DATA, "Enter: %s: rxp=%p\n", dev_name(dev), skb);
++
++ /* process and remove protocol-specific header */
++ ret = brcmf_proto_hdrpull(drvr, true, &ifidx, skb);
++ ifp = drvr->iflist[ifidx];
++
++ if (ret || !ifp || !ifp->ndev) {
++ if ((ret != -ENODATA) && ifp)
++ ifp->stats.rx_errors++;
++ brcmu_pkt_buf_free_skb(skb);
++ return;
++ }
++
++ rd = (struct brcmf_skb_reorder_data *)skb->cb;
++ if (rd->reorder)
++ brcmf_rxreorder_process_info(ifp, rd->reorder, skb);
++ else
++ brcmf_netif_rx(ifp, skb);
++}
++
++void brcmf_txfinalize(struct brcmf_pub *drvr, struct sk_buff *txp, u8 ifidx,
++ bool success)
++{
++ struct brcmf_if *ifp;
++ struct ethhdr *eh;
++ u16 type;
++
++ ifp = drvr->iflist[ifidx];
++ if (!ifp)
++ goto done;
++
++ eh = (struct ethhdr *)(txp->data);
++ type = ntohs(eh->h_proto);
++
++ if (type == ETH_P_PAE) {
++ atomic_dec(&ifp->pend_8021x_cnt);
++ if (waitqueue_active(&ifp->pend_8021x_wait))
++ wake_up(&ifp->pend_8021x_wait);
++ }
++
++ if (!success)
++ ifp->stats.tx_errors++;
++done:
++ brcmu_pkt_buf_free_skb(txp);
++}
++
++void brcmf_txcomplete(struct device *dev, struct sk_buff *txp, bool success)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ u8 ifidx;
++
++ /* await txstatus signal for firmware if active */
++ if (brcmf_fws_fc_active(drvr->fws)) {
++ if (!success)
++ brcmf_fws_bustxfail(drvr->fws, txp);
++ } else {
++ if (brcmf_proto_hdrpull(drvr, false, &ifidx, txp))
++ brcmu_pkt_buf_free_skb(txp);
++ else
++ brcmf_txfinalize(drvr, txp, ifidx, success);
++ }
++}
++
++static struct net_device_stats *brcmf_netdev_get_stats(struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++
++ brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
++
++ return &ifp->stats;
++}
++
++static void brcmf_ethtool_get_drvinfo(struct net_device *ndev,
++ struct ethtool_drvinfo *info)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_pub *drvr = ifp->drvr;
++ char drev[BRCMU_DOTREV_LEN] = "n/a";
++
++ if (drvr->revinfo.result == 0)
++ brcmu_dotrev_str(drvr->revinfo.driverrev, drev);
++ strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
++ strlcpy(info->version, drev, sizeof(info->version));
++ strlcpy(info->fw_version, drvr->fwver, sizeof(info->fw_version));
++ strlcpy(info->bus_info, dev_name(drvr->bus_if->dev),
++ sizeof(info->bus_info));
++}
++
++static const struct ethtool_ops brcmf_ethtool_ops = {
++ .get_drvinfo = brcmf_ethtool_get_drvinfo,
++};
++
++static int brcmf_netdev_stop(struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++
++ brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
++
++ brcmf_cfg80211_down(ndev);
++
++ /* Set state and stop OS transmissions */
++ netif_stop_queue(ndev);
++
++ return 0;
++}
++
++static int brcmf_netdev_open(struct net_device *ndev)
++{
++ struct brcmf_if *ifp = netdev_priv(ndev);
++ struct brcmf_pub *drvr = ifp->drvr;
++ struct brcmf_bus *bus_if = drvr->bus_if;
++ u32 toe_ol;
++
++ brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
++
++ /* If bus is not ready, can't continue */
++ if (bus_if->state != BRCMF_BUS_UP) {
++ brcmf_err("failed bus is not ready\n");
++ return -EAGAIN;
++ }
++
++ atomic_set(&ifp->pend_8021x_cnt, 0);
++
++ /* Get current TOE mode from dongle */
++ if (brcmf_fil_iovar_int_get(ifp, "toe_ol", &toe_ol) >= 0
++ && (toe_ol & TOE_TX_CSUM_OL) != 0)
++ ndev->features |= NETIF_F_IP_CSUM;
++ else
++ ndev->features &= ~NETIF_F_IP_CSUM;
++
++ if (brcmf_cfg80211_up(ndev)) {
++ brcmf_err("failed to bring up cfg80211\n");
++ return -EIO;
++ }
++
++ /* Allow transmit calls */
++ netif_start_queue(ndev);
++ return 0;
++}
++
++static const struct net_device_ops brcmf_netdev_ops_pri = {
++ .ndo_open = brcmf_netdev_open,
++ .ndo_stop = brcmf_netdev_stop,
++ .ndo_get_stats = brcmf_netdev_get_stats,
++ .ndo_start_xmit = brcmf_netdev_start_xmit,
++ .ndo_set_mac_address = brcmf_netdev_set_mac_address,
++ .ndo_set_rx_mode = brcmf_netdev_set_multicast_list
++};
++
++int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked)
++{
++ struct brcmf_pub *drvr = ifp->drvr;
++ struct net_device *ndev;
++ s32 err;
++
++ brcmf_dbg(TRACE, "Enter, idx=%d mac=%pM\n", ifp->bssidx,
++ ifp->mac_addr);
++ ndev = ifp->ndev;
++
++ /* set appropriate operations */
++ ndev->netdev_ops = &brcmf_netdev_ops_pri;
++
++ ndev->hard_header_len += drvr->hdrlen;
++ ndev->ethtool_ops = &brcmf_ethtool_ops;
++
++ drvr->rxsz = ndev->mtu + ndev->hard_header_len +
++ drvr->hdrlen;
++
++ /* set the mac address */
++ memcpy(ndev->dev_addr, ifp->mac_addr, ETH_ALEN);
++
++ INIT_WORK(&ifp->setmacaddr_work, _brcmf_set_mac_address);
++ INIT_WORK(&ifp->multicast_work, _brcmf_set_multicast_list);
++
++ if (rtnl_locked)
++ err = register_netdevice(ndev);
++ else
++ err = register_netdev(ndev);
++ if (err != 0) {
++ brcmf_err("couldn't register the net device\n");
++ goto fail;
++ }
++
++ brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
++
++ ndev->destructor = brcmf_cfg80211_free_netdev;
++ return 0;
++
++fail:
++ drvr->iflist[ifp->bssidx] = NULL;
++ ndev->netdev_ops = NULL;
++ free_netdev(ndev);
++ return -EBADE;
++}
++
++static int brcmf_net_p2p_open(struct net_device *ndev)
++{
++ brcmf_dbg(TRACE, "Enter\n");
++
++ return brcmf_cfg80211_up(ndev);
++}
++
++static int brcmf_net_p2p_stop(struct net_device *ndev)
++{
++ brcmf_dbg(TRACE, "Enter\n");
++
++ return brcmf_cfg80211_down(ndev);
++}
++
++static netdev_tx_t brcmf_net_p2p_start_xmit(struct sk_buff *skb,
++ struct net_device *ndev)
++{
++ if (skb)
++ dev_kfree_skb_any(skb);
++
++ return NETDEV_TX_OK;
++}
++
++static const struct net_device_ops brcmf_netdev_ops_p2p = {
++ .ndo_open = brcmf_net_p2p_open,
++ .ndo_stop = brcmf_net_p2p_stop,
++ .ndo_start_xmit = brcmf_net_p2p_start_xmit
++};
++
++static int brcmf_net_p2p_attach(struct brcmf_if *ifp)
++{
++ struct net_device *ndev;
++
++ brcmf_dbg(TRACE, "Enter, idx=%d mac=%pM\n", ifp->bssidx,
++ ifp->mac_addr);
++ ndev = ifp->ndev;
++
++ ndev->netdev_ops = &brcmf_netdev_ops_p2p;
++
++ /* set the mac address */
++ memcpy(ndev->dev_addr, ifp->mac_addr, ETH_ALEN);
++
++ if (register_netdev(ndev) != 0) {
++ brcmf_err("couldn't register the p2p net device\n");
++ goto fail;
++ }
++
++ brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
++
++ return 0;
++
++fail:
++ ifp->drvr->iflist[ifp->bssidx] = NULL;
++ ndev->netdev_ops = NULL;
++ free_netdev(ndev);
++ return -EBADE;
++}
++
++struct brcmf_if *brcmf_add_if(struct brcmf_pub *drvr, s32 bssidx, s32 ifidx,
++ char *name, u8 *mac_addr)
++{
++ struct brcmf_if *ifp;
++ struct net_device *ndev;
++
++ brcmf_dbg(TRACE, "Enter, idx=%d, ifidx=%d\n", bssidx, ifidx);
++
++ ifp = drvr->iflist[bssidx];
++ /*
++ * Delete the existing interface before overwriting it
++ * in case we missed the BRCMF_E_IF_DEL event.
++ */
++ if (ifp) {
++ if (ifidx) {
++ brcmf_err("ERROR: netdev:%s already exists, deleting old interface\n",
++ ifp->ndev->name);
++ netif_stop_queue(ifp->ndev);
++ unregister_netdev(ifp->ndev);
++ free_netdev(ifp->ndev);
++ drvr->iflist[bssidx] = NULL;
++ } else {
++ brcmf_dbg(EVENT, "ignore IF event\n");
++ return ERR_PTR(-EINVAL);
++ }
++ }
++
++ if (!brcmf_p2p_enable && bssidx == 1) {
++ /* this is P2P_DEVICE interface */
++ brcmf_dbg(INFO, "allocate non-netdev interface\n");
++ ifp = kzalloc(sizeof(*ifp), GFP_KERNEL);
++ if (!ifp)
++ return ERR_PTR(-ENOMEM);
++ } else {
++ brcmf_dbg(INFO, "allocate netdev interface\n");
++ /* Allocate netdev, including space for private structure */
++ ndev = alloc_netdev(sizeof(*ifp), name, ether_setup);
++ if (!ndev)
++ return ERR_PTR(-ENOMEM);
++
++ ifp = netdev_priv(ndev);
++ ifp->ndev = ndev;
++ }
++
++ ifp->drvr = drvr;
++ drvr->iflist[bssidx] = ifp;
++ ifp->ifidx = ifidx;
++ ifp->bssidx = bssidx;
++
++ init_waitqueue_head(&ifp->pend_8021x_wait);
++ spin_lock_init(&ifp->netif_stop_lock);
++
++ if (mac_addr != NULL)
++ memcpy(ifp->mac_addr, mac_addr, ETH_ALEN);
++
++ brcmf_dbg(TRACE, " ==== pid:%x, if:%s (%pM) created ===\n",
++ current->pid, name, ifp->mac_addr);
++
++ return ifp;
++}
++
++static void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
++{
++ struct brcmf_if *ifp;
++
++ ifp = drvr->iflist[bssidx];
++ drvr->iflist[bssidx] = NULL;
++ if (!ifp) {
++ brcmf_err("Null interface, idx=%d\n", bssidx);
++ return;
++ }
++ brcmf_dbg(TRACE, "Enter, idx=%d, ifidx=%d\n", bssidx, ifp->ifidx);
++ if (ifp->ndev) {
++ if (bssidx == 0) {
++ if (ifp->ndev->netdev_ops == &brcmf_netdev_ops_pri) {
++ rtnl_lock();
++ brcmf_netdev_stop(ifp->ndev);
++ rtnl_unlock();
++ }
++ } else {
++ netif_stop_queue(ifp->ndev);
++ }
++
++ if (ifp->ndev->netdev_ops == &brcmf_netdev_ops_pri) {
++ cancel_work_sync(&ifp->setmacaddr_work);
++ cancel_work_sync(&ifp->multicast_work);
++ }
++ /* unregister will take care of freeing it */
++ unregister_netdev(ifp->ndev);
++ } else {
++ kfree(ifp);
++ }
++}
++
++void brcmf_remove_interface(struct brcmf_pub *drvr, u32 bssidx)
++{
++ if (drvr->iflist[bssidx]) {
++ brcmf_fws_del_interface(drvr->iflist[bssidx]);
++ brcmf_del_if(drvr, bssidx);
++ }
++}
++
++int brcmf_get_next_free_bsscfgidx(struct brcmf_pub *drvr)
++{
++ int ifidx;
++ int bsscfgidx;
++ bool available;
++ int highest;
++
++ available = false;
++ bsscfgidx = 2;
++ highest = 2;
++ for (ifidx = 0; ifidx < BRCMF_MAX_IFS; ifidx++) {
++ if (drvr->iflist[ifidx]) {
++ if (drvr->iflist[ifidx]->bssidx == bsscfgidx)
++ bsscfgidx = highest + 1;
++ else if (drvr->iflist[ifidx]->bssidx > highest)
++ highest = drvr->iflist[ifidx]->bssidx;
++ } else {
++ available = true;
++ }
++ }
++
++ return available ? bsscfgidx : -ENOMEM;
++}
++
++int brcmf_attach(struct device *dev)
++{
++ struct brcmf_pub *drvr = NULL;
++ int ret = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* Allocate primary brcmf_info */
++ drvr = kzalloc(sizeof(struct brcmf_pub), GFP_ATOMIC);
++ if (!drvr)
++ return -ENOMEM;
++
++ mutex_init(&drvr->proto_block);
++
++ /* Link to bus module */
++ drvr->hdrlen = 0;
++ drvr->bus_if = dev_get_drvdata(dev);
++ drvr->bus_if->drvr = drvr;
++
++ /* create device debugfs folder */
++ brcmf_debugfs_attach(drvr);
++
++ /* Attach and link in the protocol */
++ ret = brcmf_proto_attach(drvr);
++ if (ret != 0) {
++ brcmf_err("brcmf_prot_attach failed\n");
++ goto fail;
++ }
++
++ /* attach firmware event handler */
++ brcmf_fweh_attach(drvr);
++
++ return ret;
++
++fail:
++ brcmf_detach(dev);
++
++ return ret;
++}
++
++int brcmf_bus_start(struct device *dev)
++{
++ int ret = -1;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ struct brcmf_if *ifp;
++ struct brcmf_if *p2p_ifp;
++
++ brcmf_dbg(TRACE, "\n");
++
++ /* add primary networking interface */
++ ifp = brcmf_add_if(drvr, 0, 0, "wlan%d", NULL);
++ if (IS_ERR(ifp))
++ return PTR_ERR(ifp);
++
++ if (brcmf_p2p_enable)
++ p2p_ifp = brcmf_add_if(drvr, 1, 0, "p2p%d", NULL);
++ else
++ p2p_ifp = NULL;
++ if (IS_ERR(p2p_ifp))
++ p2p_ifp = NULL;
++
++ /* signal bus ready */
++ brcmf_bus_change_state(bus_if, BRCMF_BUS_UP);
++
++ /* Bus is ready, do any initialization */
++ ret = brcmf_c_preinit_dcmds(ifp);
++ if (ret < 0)
++ goto fail;
++
++ /* assure we have chipid before feature attach */
++ if (!bus_if->chip) {
++ bus_if->chip = drvr->revinfo.chipnum;
++ bus_if->chiprev = drvr->revinfo.chiprev;
++ brcmf_dbg(INFO, "firmware revinfo: chip %x (%d) rev %d\n",
++ bus_if->chip, bus_if->chip, bus_if->chiprev);
++ }
++ brcmf_feat_attach(drvr);
++
++ ret = brcmf_fws_init(drvr);
++ if (ret < 0)
++ goto fail;
++
++ brcmf_fws_add_interface(ifp);
++
++ drvr->config = brcmf_cfg80211_attach(drvr, bus_if->dev);
++ if (drvr->config == NULL) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ ret = brcmf_fweh_activate_events(ifp);
++ if (ret < 0)
++ goto fail;
++
++ ret = brcmf_net_attach(ifp, false);
++fail:
++ if (ret < 0) {
++ brcmf_err("failed: %d\n", ret);
++ brcmf_cfg80211_detach(drvr->config);
++ if (drvr->fws) {
++ brcmf_fws_del_interface(ifp);
++ brcmf_fws_deinit(drvr);
++ }
++ if (drvr->iflist[0]) {
++ free_netdev(ifp->ndev);
++ drvr->iflist[0] = NULL;
++ }
++ if (p2p_ifp) {
++ free_netdev(p2p_ifp->ndev);
++ drvr->iflist[1] = NULL;
++ }
++ return ret;
++ }
++ if ((brcmf_p2p_enable) && (p2p_ifp))
++ if (brcmf_net_p2p_attach(p2p_ifp) < 0)
++ brcmf_p2p_enable = 0;
++
++ return 0;
++}
++
++void brcmf_bus_add_txhdrlen(struct device *dev, uint len)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++
++ if (drvr) {
++ drvr->hdrlen += len;
++ }
++}
++
++static void brcmf_bus_detach(struct brcmf_pub *drvr)
++{
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (drvr) {
++ /* Stop the bus module */
++ brcmf_bus_stop(drvr->bus_if);
++ }
++}
++
++void brcmf_dev_reset(struct device *dev)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++
++ if (drvr == NULL)
++ return;
++
++ if (drvr->iflist[0])
++ brcmf_fil_cmd_int_set(drvr->iflist[0], BRCMF_C_TERMINATED, 1);
++}
++
++void brcmf_detach(struct device *dev)
++{
++ s32 i;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (drvr == NULL)
++ return;
++
++ /* stop firmware event handling */
++ brcmf_fweh_detach(drvr);
++
++ brcmf_bus_change_state(bus_if, BRCMF_BUS_DOWN);
++
++ /* make sure primary interface removed last */
++ for (i = BRCMF_MAX_IFS-1; i > -1; i--)
++ brcmf_remove_interface(drvr, i);
++
++ brcmf_cfg80211_detach(drvr->config);
++
++ brcmf_fws_deinit(drvr);
++
++ brcmf_bus_detach(drvr);
++
++ brcmf_proto_detach(drvr);
++
++ brcmf_debugfs_detach(drvr);
++ bus_if->drvr = NULL;
++ kfree(drvr);
++}
++
++s32 brcmf_iovar_data_set(struct device *dev, char *name, void *data, u32 len)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_if *ifp = bus_if->drvr->iflist[0];
++
++ return brcmf_fil_iovar_data_set(ifp, name, data, len);
++}
++
++static int brcmf_get_pend_8021x_cnt(struct brcmf_if *ifp)
++{
++ return atomic_read(&ifp->pend_8021x_cnt);
++}
++
++int brcmf_netdev_wait_pend8021x(struct brcmf_if *ifp)
++{
++ int err;
++
++ err = wait_event_timeout(ifp->pend_8021x_wait,
++ !brcmf_get_pend_8021x_cnt(ifp),
++ msecs_to_jiffies(MAX_WAIT_FOR_8021X_TX));
++
++ WARN_ON(!err);
++
++ return !err;
++}
++
++void brcmf_bus_change_state(struct brcmf_bus *bus, enum brcmf_bus_state state)
++{
++ struct brcmf_pub *drvr = bus->drvr;
++ struct net_device *ndev;
++ int ifidx;
++
++ brcmf_dbg(TRACE, "%d -> %d\n", bus->state, state);
++ bus->state = state;
++
++ if (state == BRCMF_BUS_UP) {
++ for (ifidx = 0; ifidx < BRCMF_MAX_IFS; ifidx++) {
++ if ((drvr->iflist[ifidx]) &&
++ (drvr->iflist[ifidx]->ndev)) {
++ ndev = drvr->iflist[ifidx]->ndev;
++ if (netif_queue_stopped(ndev))
++ netif_wake_queue(ndev);
++ }
++ }
++ }
++}
++
++static void brcmf_driver_register(struct work_struct *work)
++{
++#ifdef CONFIG_BRCMFMAC_SDIO
++ brcmf_sdio_register();
++#endif
++#ifdef CONFIG_BRCMFMAC_USB
++ brcmf_usb_register();
++#endif
++#ifdef CONFIG_BRCMFMAC_PCIE
++ brcmf_pcie_register();
++#endif
++}
++static DECLARE_WORK(brcmf_driver_work, brcmf_driver_register);
++
++static int __init brcmfmac_module_init(void)
++{
++ brcmf_debugfs_init();
++#ifdef CONFIG_BRCMFMAC_SDIO
++ brcmf_sdio_init();
++#endif
++ if (!schedule_work(&brcmf_driver_work))
++ return -EBUSY;
++
++ return 0;
++}
++
++static void __exit brcmfmac_module_exit(void)
++{
++ cancel_work_sync(&brcmf_driver_work);
++
++#ifdef CONFIG_BRCMFMAC_SDIO
++ brcmf_sdio_exit();
++#endif
++#ifdef CONFIG_BRCMFMAC_USB
++ brcmf_usb_exit();
++#endif
++#ifdef CONFIG_BRCMFMAC_PCIE
++ brcmf_pcie_exit();
++#endif
++ brcmf_debugfs_exit();
++}
++
++module_init(brcmfmac_module_init);
++module_exit(brcmfmac_module_exit);
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/core.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/core.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/core.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/core.h 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,217 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++/****************
++ * Common types *
++ */
++
++#ifndef _BRCMF_H_
++#define _BRCMF_H_
++
++#include "fweh.h"
++
++#define TOE_TX_CSUM_OL 0x00000001
++#define TOE_RX_CSUM_OL 0x00000002
++
++/* For supporting multiple interfaces */
++#define BRCMF_MAX_IFS 16
++
++/* Small, medium and maximum buffer size for dcmd
++ */
++#define BRCMF_DCMD_SMLEN 256
++#define BRCMF_DCMD_MEDLEN 1536
++#define BRCMF_DCMD_MAXLEN 8192
++
++/* IOCTL from host to device are limited in lenght. A device can only handle
++ * ethernet frame size. This limitation is to be applied by protocol layer.
++ */
++#define BRCMF_TX_IOCTL_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
++
++#define BRCMF_AMPDU_RX_REORDER_MAXFLOWS 256
++
++/* Length of firmware version string stored for
++ * ethtool driver info which uses 32 bytes as well.
++ */
++#define BRCMF_DRIVER_FIRMWARE_VERSION_LEN 32
++
++/**
++ * struct brcmf_ampdu_rx_reorder - AMPDU receive reorder info
++ *
++ * @pktslots: dynamic allocated array for ordering AMPDU packets.
++ * @flow_id: AMPDU flow identifier.
++ * @cur_idx: last AMPDU index from firmware.
++ * @exp_idx: expected next AMPDU index.
++ * @max_idx: maximum amount of packets per AMPDU.
++ * @pend_pkts: number of packets currently in @pktslots.
++ */
++struct brcmf_ampdu_rx_reorder {
++ struct sk_buff **pktslots;
++ u8 flow_id;
++ u8 cur_idx;
++ u8 exp_idx;
++ u8 max_idx;
++ u8 pend_pkts;
++};
++
++/* Forward decls for struct brcmf_pub (see below) */
++struct brcmf_proto; /* device communication protocol info */
++struct brcmf_cfg80211_dev; /* cfg80211 device info */
++struct brcmf_fws_info; /* firmware signalling info */
++
++/*
++ * struct brcmf_rev_info
++ *
++ * The result field stores the error code of the
++ * revision info request from firmware. For the
++ * other fields see struct brcmf_rev_info_le in
++ * fwil_types.h
++ */
++struct brcmf_rev_info {
++ int result;
++ u32 vendorid;
++ u32 deviceid;
++ u32 radiorev;
++ u32 chiprev;
++ u32 corerev;
++ u32 boardid;
++ u32 boardvendor;
++ u32 boardrev;
++ u32 driverrev;
++ u32 ucoderev;
++ u32 bus;
++ u32 chipnum;
++ u32 phytype;
++ u32 phyrev;
++ u32 anarev;
++ u32 chippkg;
++ u32 nvramrev;
++};
++
++/* Common structure for module and instance linkage */
++struct brcmf_pub {
++ /* Linkage ponters */
++ struct brcmf_bus *bus_if;
++ struct brcmf_proto *proto;
++ struct brcmf_cfg80211_info *config;
++
++ /* Internal brcmf items */
++ uint hdrlen; /* Total BRCMF header length (proto + bus) */
++ uint rxsz; /* Rx buffer size bus module should use */
++
++ /* Dongle media info */
++ char fwver[BRCMF_DRIVER_FIRMWARE_VERSION_LEN];
++ u8 mac[ETH_ALEN]; /* MAC address obtained from dongle */
++
++ /* Multicast data packets sent to dongle */
++ unsigned long tx_multicast;
++
++ struct brcmf_if *iflist[BRCMF_MAX_IFS];
++
++ struct mutex proto_block;
++ unsigned char proto_buf[BRCMF_DCMD_MAXLEN];
++
++ struct brcmf_fweh_info fweh;
++
++ struct brcmf_fws_info *fws;
++
++ struct brcmf_ampdu_rx_reorder
++ *reorder_flows[BRCMF_AMPDU_RX_REORDER_MAXFLOWS];
++
++ u32 feat_flags;
++ u32 chip_quirks;
++
++ struct brcmf_rev_info revinfo;
++#ifdef DEBUG
++ struct dentry *dbgfs_dir;
++#endif
++};
++
++/* forward declarations */
++struct brcmf_cfg80211_vif;
++struct brcmf_fws_mac_descriptor;
++
++/**
++ * enum brcmf_netif_stop_reason - reason for stopping netif queue.
++ *
++ * @BRCMF_NETIF_STOP_REASON_FWS_FC:
++ * netif stopped due to firmware signalling flow control.
++ * @BRCMF_NETIF_STOP_REASON_FLOW:
++ * netif stopped due to flowring full.
++ */
++enum brcmf_netif_stop_reason {
++ BRCMF_NETIF_STOP_REASON_FWS_FC = 1,
++ BRCMF_NETIF_STOP_REASON_FLOW = 2
++};
++
++/**
++ * struct brcmf_if - interface control information.
++ *
++ * @drvr: points to device related information.
++ * @vif: points to cfg80211 specific interface information.
++ * @ndev: associated network device.
++ * @stats: interface specific network statistics.
++ * @setmacaddr_work: worker object for setting mac address.
++ * @multicast_work: worker object for multicast provisioning.
++ * @fws_desc: interface specific firmware-signalling descriptor.
++ * @ifidx: interface index in device firmware.
++ * @bssidx: index of bss associated with this interface.
++ * @mac_addr: assigned mac address.
++ * @netif_stop: bitmap indicates reason why netif queues are stopped.
++ * @netif_stop_lock: spinlock for update netif_stop from multiple sources.
++ * @pend_8021x_cnt: tracks outstanding number of 802.1x frames.
++ * @pend_8021x_wait: used for signalling change in count.
++ */
++struct brcmf_if {
++ struct brcmf_pub *drvr;
++ struct brcmf_cfg80211_vif *vif;
++ struct net_device *ndev;
++ struct net_device_stats stats;
++ struct work_struct setmacaddr_work;
++ struct work_struct multicast_work;
++ struct brcmf_fws_mac_descriptor *fws_desc;
++ int ifidx;
++ s32 bssidx;
++ u8 mac_addr[ETH_ALEN];
++ u8 netif_stop;
++ spinlock_t netif_stop_lock;
++ atomic_t pend_8021x_cnt;
++ wait_queue_head_t pend_8021x_wait;
++};
++
++struct brcmf_skb_reorder_data {
++ u8 *reorder;
++};
++
++int brcmf_netdev_wait_pend8021x(struct brcmf_if *ifp);
++
++/* Return pointer to interface name */
++char *brcmf_ifname(struct brcmf_pub *drvr, int idx);
++
++int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked);
++struct brcmf_if *brcmf_add_if(struct brcmf_pub *drvr, s32 bssidx, s32 ifidx,
++ char *name, u8 *mac_addr);
++void brcmf_remove_interface(struct brcmf_pub *drvr, u32 bssidx);
++int brcmf_get_next_free_bsscfgidx(struct brcmf_pub *drvr);
++void brcmf_txflowblock_if(struct brcmf_if *ifp,
++ enum brcmf_netif_stop_reason reason, bool state);
++void brcmf_txfinalize(struct brcmf_pub *drvr, struct sk_buff *txp, u8 ifidx,
++ bool success);
++void brcmf_netif_rx(struct brcmf_if *ifp, struct sk_buff *skb);
++
++/* Sets dongle media info (drv_version, mac address). */
++int brcmf_c_preinit_dcmds(struct brcmf_if *ifp);
++
++#endif /* _BRCMF_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/debug.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/debug.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/debug.c 2016-06-19 22:11:55.277141844 +0200
+@@ -0,0 +1,117 @@
++/*
++ * Copyright (c) 2012 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#include <linux/debugfs.h>
++#include <linux/netdevice.h>
++#include <linux/module.h>
++
++#include <brcmu_wifi.h>
++#include <brcmu_utils.h>
++#include "core.h"
++#include "bus.h"
++#include "debug.h"
++
++static struct dentry *root_folder;
++
++void brcmf_debugfs_init(void)
++{
++ root_folder = debugfs_create_dir(KBUILD_MODNAME, NULL);
++ if (IS_ERR(root_folder))
++ root_folder = NULL;
++}
++
++void brcmf_debugfs_exit(void)
++{
++ if (!root_folder)
++ return;
++
++ debugfs_remove_recursive(root_folder);
++ root_folder = NULL;
++}
++
++static int brcmf_debugfs_chipinfo_read(struct seq_file *seq, void *data)
++{
++ struct brcmf_bus *bus = dev_get_drvdata(seq->private);
++
++ seq_printf(seq, "chip: %x(%u) rev %u\n",
++ bus->chip, bus->chip, bus->chiprev);
++ return 0;
++}
++
++int brcmf_debugfs_attach(struct brcmf_pub *drvr)
++{
++ struct device *dev = drvr->bus_if->dev;
++
++ if (!root_folder)
++ return -ENODEV;
++
++ drvr->dbgfs_dir = debugfs_create_dir(dev_name(dev), root_folder);
++ brcmf_debugfs_add_entry(drvr, "chipinfo", brcmf_debugfs_chipinfo_read);
++
++ return PTR_ERR_OR_ZERO(drvr->dbgfs_dir);
++}
++
++void brcmf_debugfs_detach(struct brcmf_pub *drvr)
++{
++ if (!IS_ERR_OR_NULL(drvr->dbgfs_dir))
++ debugfs_remove_recursive(drvr->dbgfs_dir);
++}
++
++struct dentry *brcmf_debugfs_get_devdir(struct brcmf_pub *drvr)
++{
++ return drvr->dbgfs_dir;
++}
++
++struct brcmf_debugfs_entry {
++ int (*read)(struct seq_file *seq, void *data);
++ struct brcmf_pub *drvr;
++};
++
++static int brcmf_debugfs_entry_open(struct inode *inode, struct file *f)
++{
++ struct brcmf_debugfs_entry *entry = inode->i_private;
++
++ return single_open(f, entry->read, entry->drvr->bus_if->dev);
++}
++
++static const struct file_operations brcmf_debugfs_def_ops = {
++ .owner = THIS_MODULE,
++ .open = brcmf_debugfs_entry_open,
++ .release = single_release,
++ .read = seq_read,
++ .llseek = seq_lseek
++};
++
++int brcmf_debugfs_add_entry(struct brcmf_pub *drvr, const char *fn,
++ int (*read_fn)(struct seq_file *seq, void *data))
++{
++ struct dentry *dentry = drvr->dbgfs_dir;
++ struct brcmf_debugfs_entry *entry;
++
++ if (IS_ERR_OR_NULL(dentry))
++ return -ENOENT;
++
++ entry = devm_kzalloc(drvr->bus_if->dev, sizeof(*entry), GFP_KERNEL);
++ if (!entry)
++ return -ENOMEM;
++
++ entry->read = read_fn;
++ entry->drvr = drvr;
++
++ dentry = debugfs_create_file(fn, S_IRUGO, dentry, entry,
++ &brcmf_debugfs_def_ops);
++
++ return PTR_ERR_OR_ZERO(dentry);
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/debug.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/debug.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/debug.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/debug.h 2016-06-19 22:11:55.281141582 +0200
+@@ -0,0 +1,136 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef BRCMFMAC_DEBUG_H
++#define BRCMFMAC_DEBUG_H
++
++/* message levels */
++#define BRCMF_TRACE_VAL 0x00000002
++#define BRCMF_INFO_VAL 0x00000004
++#define BRCMF_DATA_VAL 0x00000008
++#define BRCMF_CTL_VAL 0x00000010
++#define BRCMF_TIMER_VAL 0x00000020
++#define BRCMF_HDRS_VAL 0x00000040
++#define BRCMF_BYTES_VAL 0x00000080
++#define BRCMF_INTR_VAL 0x00000100
++#define BRCMF_GLOM_VAL 0x00000200
++#define BRCMF_EVENT_VAL 0x00000400
++#define BRCMF_BTA_VAL 0x00000800
++#define BRCMF_FIL_VAL 0x00001000
++#define BRCMF_USB_VAL 0x00002000
++#define BRCMF_SCAN_VAL 0x00004000
++#define BRCMF_CONN_VAL 0x00008000
++#define BRCMF_BCDC_VAL 0x00010000
++#define BRCMF_SDIO_VAL 0x00020000
++#define BRCMF_MSGBUF_VAL 0x00040000
++#define BRCMF_PCIE_VAL 0x00080000
++
++/* set default print format */
++#undef pr_fmt
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++/* Macro for error messages. net_ratelimit() is used when driver
++ * debugging is not selected. When debugging the driver error
++ * messages are as important as other tracing or even more so.
++ */
++#ifndef CONFIG_BRCM_TRACING
++#ifdef CONFIG_BRCMDBG
++#define brcmf_err(fmt, ...) pr_err("%s: " fmt, __func__, ##__VA_ARGS__)
++#else
++#define brcmf_err(fmt, ...) \
++ do { \
++ if (net_ratelimit()) \
++ pr_err("%s: " fmt, __func__, ##__VA_ARGS__); \
++ } while (0)
++#endif
++#else
++__printf(2, 3)
++void __brcmf_err(const char *func, const char *fmt, ...);
++#define brcmf_err(fmt, ...) \
++ __brcmf_err(__func__, fmt, ##__VA_ARGS__)
++#endif
++
++#if defined(DEBUG) || defined(CONFIG_BRCM_TRACING)
++__printf(3, 4)
++void __brcmf_dbg(u32 level, const char *func, const char *fmt, ...);
++#define brcmf_dbg(level, fmt, ...) \
++do { \
++ __brcmf_dbg(BRCMF_##level##_VAL, __func__, \
++ fmt, ##__VA_ARGS__); \
++} while (0)
++#define BRCMF_DATA_ON() (brcmf_msg_level & BRCMF_DATA_VAL)
++#define BRCMF_CTL_ON() (brcmf_msg_level & BRCMF_CTL_VAL)
++#define BRCMF_HDRS_ON() (brcmf_msg_level & BRCMF_HDRS_VAL)
++#define BRCMF_BYTES_ON() (brcmf_msg_level & BRCMF_BYTES_VAL)
++#define BRCMF_GLOM_ON() (brcmf_msg_level & BRCMF_GLOM_VAL)
++#define BRCMF_EVENT_ON() (brcmf_msg_level & BRCMF_EVENT_VAL)
++#define BRCMF_FIL_ON() (brcmf_msg_level & BRCMF_FIL_VAL)
++
++#else /* defined(DEBUG) || defined(CONFIG_BRCM_TRACING) */
++
++#define brcmf_dbg(level, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
++
++#define BRCMF_DATA_ON() 0
++#define BRCMF_CTL_ON() 0
++#define BRCMF_HDRS_ON() 0
++#define BRCMF_BYTES_ON() 0
++#define BRCMF_GLOM_ON() 0
++#define BRCMF_EVENT_ON() 0
++#define BRCMF_FIL_ON() 0
++
++#endif /* defined(DEBUG) || defined(CONFIG_BRCM_TRACING) */
++
++#define brcmf_dbg_hex_dump(test, data, len, fmt, ...) \
++do { \
++ trace_brcmf_hexdump((void *)data, len); \
++ if (test) \
++ brcmu_dbg_hex_dump(data, len, fmt, ##__VA_ARGS__); \
++} while (0)
++
++extern int brcmf_msg_level;
++
++struct brcmf_pub;
++#ifdef DEBUG
++void brcmf_debugfs_init(void);
++void brcmf_debugfs_exit(void);
++int brcmf_debugfs_attach(struct brcmf_pub *drvr);
++void brcmf_debugfs_detach(struct brcmf_pub *drvr);
++struct dentry *brcmf_debugfs_get_devdir(struct brcmf_pub *drvr);
++int brcmf_debugfs_add_entry(struct brcmf_pub *drvr, const char *fn,
++ int (*read_fn)(struct seq_file *seq, void *data));
++#else
++static inline void brcmf_debugfs_init(void)
++{
++}
++static inline void brcmf_debugfs_exit(void)
++{
++}
++static inline int brcmf_debugfs_attach(struct brcmf_pub *drvr)
++{
++ return 0;
++}
++static inline void brcmf_debugfs_detach(struct brcmf_pub *drvr)
++{
++}
++static inline
++int brcmf_debugfs_add_entry(struct brcmf_pub *drvr, const char *fn,
++ int (*read_fn)(struct seq_file *seq, void *data))
++{
++ return 0;
++}
++#endif
++
++#endif /* BRCMFMAC_DEBUG_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_bus.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,205 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#ifndef _BRCMF_BUS_H_
+-#define _BRCMF_BUS_H_
+-
+-#include "dhd_dbg.h"
+-
+-/* The level of bus communication with the dongle */
+-enum brcmf_bus_state {
+- BRCMF_BUS_UNKNOWN, /* Not determined yet */
+- BRCMF_BUS_NOMEDIUM, /* No medium access to dongle */
+- BRCMF_BUS_DOWN, /* Not ready for frame transfers */
+- BRCMF_BUS_LOAD, /* Download access only (CPU reset) */
+- BRCMF_BUS_DATA /* Ready for frame transfers */
+-};
+-
+-/* The level of bus communication with the dongle */
+-enum brcmf_bus_protocol_type {
+- BRCMF_PROTO_BCDC,
+- BRCMF_PROTO_MSGBUF
+-};
+-
+-struct brcmf_bus_dcmd {
+- char *name;
+- char *param;
+- int param_len;
+- struct list_head list;
+-};
+-
+-/**
+- * struct brcmf_bus_ops - bus callback operations.
+- *
+- * @preinit: execute bus/device specific dongle init commands (optional).
+- * @init: prepare for communication with dongle.
+- * @stop: clear pending frames, disable data flow.
+- * @txdata: send a data frame to the dongle. When the data
+- * has been transferred, the common driver must be
+- * notified using brcmf_txcomplete(). The common
+- * driver calls this function with interrupts
+- * disabled.
+- * @txctl: transmit a control request message to dongle.
+- * @rxctl: receive a control response message from dongle.
+- * @gettxq: obtain a reference of bus transmit queue (optional).
+- *
+- * This structure provides an abstract interface towards the
+- * bus specific driver. For control messages to common driver
+- * will assure there is only one active transaction. Unless
+- * indicated otherwise these callbacks are mandatory.
+- */
+-struct brcmf_bus_ops {
+- int (*preinit)(struct device *dev);
+- int (*init)(struct device *dev);
+- void (*stop)(struct device *dev);
+- int (*txdata)(struct device *dev, struct sk_buff *skb);
+- int (*txctl)(struct device *dev, unsigned char *msg, uint len);
+- int (*rxctl)(struct device *dev, unsigned char *msg, uint len);
+- struct pktq * (*gettxq)(struct device *dev);
+-};
+-
+-/**
+- * struct brcmf_bus - interface structure between common and bus layer
+- *
+- * @bus_priv: pointer to private bus device.
+- * @proto_type: protocol type, bcdc or msgbuf
+- * @dev: device pointer of bus device.
+- * @drvr: public driver information.
+- * @state: operational state of the bus interface.
+- * @maxctl: maximum size for rxctl request message.
+- * @tx_realloc: number of tx packets realloced for headroom.
+- * @dstats: dongle-based statistical data.
+- * @dcmd_list: bus/device specific dongle initialization commands.
+- * @chip: device identifier of the dongle chip.
+- * @chiprev: revision of the dongle chip.
+- */
+-struct brcmf_bus {
+- union {
+- struct brcmf_sdio_dev *sdio;
+- struct brcmf_usbdev *usb;
+- } bus_priv;
+- enum brcmf_bus_protocol_type proto_type;
+- struct device *dev;
+- struct brcmf_pub *drvr;
+- enum brcmf_bus_state state;
+- uint maxctl;
+- unsigned long tx_realloc;
+- u32 chip;
+- u32 chiprev;
+-
+- struct brcmf_bus_ops *ops;
+-};
+-
+-/*
+- * callback wrappers
+- */
+-static inline int brcmf_bus_preinit(struct brcmf_bus *bus)
+-{
+- if (!bus->ops->preinit)
+- return 0;
+- return bus->ops->preinit(bus->dev);
+-}
+-
+-static inline int brcmf_bus_init(struct brcmf_bus *bus)
+-{
+- return bus->ops->init(bus->dev);
+-}
+-
+-static inline void brcmf_bus_stop(struct brcmf_bus *bus)
+-{
+- bus->ops->stop(bus->dev);
+-}
+-
+-static inline int brcmf_bus_txdata(struct brcmf_bus *bus, struct sk_buff *skb)
+-{
+- return bus->ops->txdata(bus->dev, skb);
+-}
+-
+-static inline
+-int brcmf_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint len)
+-{
+- return bus->ops->txctl(bus->dev, msg, len);
+-}
+-
+-static inline
+-int brcmf_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint len)
+-{
+- return bus->ops->rxctl(bus->dev, msg, len);
+-}
+-
+-static inline
+-struct pktq *brcmf_bus_gettxq(struct brcmf_bus *bus)
+-{
+- if (!bus->ops->gettxq)
+- return ERR_PTR(-ENOENT);
+-
+- return bus->ops->gettxq(bus->dev);
+-}
+-
+-static inline bool brcmf_bus_ready(struct brcmf_bus *bus)
+-{
+- return bus->state == BRCMF_BUS_LOAD || bus->state == BRCMF_BUS_DATA;
+-}
+-
+-static inline void brcmf_bus_change_state(struct brcmf_bus *bus,
+- enum brcmf_bus_state new_state)
+-{
+- /* NOMEDIUM is permanent */
+- if (bus->state == BRCMF_BUS_NOMEDIUM)
+- return;
+-
+- brcmf_dbg(TRACE, "%d -> %d\n", bus->state, new_state);
+- bus->state = new_state;
+-}
+-
+-/*
+- * interface functions from common layer
+- */
+-
+-bool brcmf_c_prec_enq(struct device *dev, struct pktq *q, struct sk_buff *pkt,
+- int prec);
+-
+-/* Receive frame for delivery to OS. Callee disposes of rxp. */
+-void brcmf_rx_frame(struct device *dev, struct sk_buff *rxp);
+-
+-/* Indication from bus module regarding presence/insertion of dongle. */
+-int brcmf_attach(struct device *dev);
+-/* Indication from bus module regarding removal/absence of dongle */
+-void brcmf_detach(struct device *dev);
+-/* Indication from bus module that dongle should be reset */
+-void brcmf_dev_reset(struct device *dev);
+-/* Indication from bus module to change flow-control state */
+-void brcmf_txflowblock(struct device *dev, bool state);
+-
+-/* Notify the bus has transferred the tx packet to firmware */
+-void brcmf_txcomplete(struct device *dev, struct sk_buff *txp, bool success);
+-
+-int brcmf_bus_start(struct device *dev);
+-s32 brcmf_iovar_data_set(struct device *dev, char *name, void *data,
+- u32 len);
+-void brcmf_bus_add_txhdrlen(struct device *dev, uint len);
+-
+-#ifdef CONFIG_BRCMFMAC_SDIO
+-void brcmf_sdio_exit(void);
+-void brcmf_sdio_init(void);
+-void brcmf_sdio_register(void);
+-#endif
+-#ifdef CONFIG_BRCMFMAC_USB
+-void brcmf_usb_exit(void);
+-void brcmf_usb_register(void);
+-#endif
+-
+-#endif /* _BRCMF_BUS_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,375 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/string.h>
+-#include <linux/netdevice.h>
+-#include <brcmu_wifi.h>
+-#include <brcmu_utils.h>
+-#include "dhd.h"
+-#include "dhd_bus.h"
+-#include "dhd_dbg.h"
+-#include "fwil.h"
+-#include "fwil_types.h"
+-#include "tracepoint.h"
+-
+-#define PKTFILTER_BUF_SIZE 128
+-#define BRCMF_DEFAULT_BCN_TIMEOUT 3
+-#define BRCMF_DEFAULT_SCAN_CHANNEL_TIME 40
+-#define BRCMF_DEFAULT_SCAN_UNASSOC_TIME 40
+-#define BRCMF_DEFAULT_PACKET_FILTER "100 0 0 0 0x01 0x00"
+-
+-
+-bool brcmf_c_prec_enq(struct device *dev, struct pktq *q,
+- struct sk_buff *pkt, int prec)
+-{
+- struct sk_buff *p;
+- int eprec = -1; /* precedence to evict from */
+- bool discard_oldest;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+-
+- /* Fast case, precedence queue is not full and we are also not
+- * exceeding total queue length
+- */
+- if (!pktq_pfull(q, prec) && !pktq_full(q)) {
+- brcmu_pktq_penq(q, prec, pkt);
+- return true;
+- }
+-
+- /* Determine precedence from which to evict packet, if any */
+- if (pktq_pfull(q, prec))
+- eprec = prec;
+- else if (pktq_full(q)) {
+- p = brcmu_pktq_peek_tail(q, &eprec);
+- if (eprec > prec)
+- return false;
+- }
+-
+- /* Evict if needed */
+- if (eprec >= 0) {
+- /* Detect queueing to unconfigured precedence */
+- discard_oldest = ac_bitmap_tst(drvr->wme_dp, eprec);
+- if (eprec == prec && !discard_oldest)
+- return false; /* refuse newer (incoming) packet */
+- /* Evict packet according to discard policy */
+- p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
+- brcmu_pktq_pdeq_tail(q, eprec);
+- if (p == NULL)
+- brcmf_err("brcmu_pktq_penq() failed, oldest %d\n",
+- discard_oldest);
+-
+- brcmu_pkt_buf_free_skb(p);
+- }
+-
+- /* Enqueue */
+- p = brcmu_pktq_penq(q, prec, pkt);
+- if (p == NULL)
+- brcmf_err("brcmu_pktq_penq() failed\n");
+-
+- return p != NULL;
+-}
+-
+-/* Convert user's input in hex pattern to byte-size mask */
+-static int brcmf_c_pattern_atoh(char *src, char *dst)
+-{
+- int i;
+- if (strncmp(src, "0x", 2) != 0 && strncmp(src, "0X", 2) != 0) {
+- brcmf_err("Mask invalid format. Needs to start with 0x\n");
+- return -EINVAL;
+- }
+- src = src + 2; /* Skip past 0x */
+- if (strlen(src) % 2 != 0) {
+- brcmf_err("Mask invalid format. Length must be even.\n");
+- return -EINVAL;
+- }
+- for (i = 0; *src != '\0'; i++) {
+- unsigned long res;
+- char num[3];
+- strncpy(num, src, 2);
+- num[2] = '\0';
+- if (kstrtoul(num, 16, &res))
+- return -EINVAL;
+- dst[i] = (u8)res;
+- src += 2;
+- }
+- return i;
+-}
+-
+-static void
+-brcmf_c_pktfilter_offload_enable(struct brcmf_if *ifp, char *arg, int enable,
+- int master_mode)
+-{
+- unsigned long res;
+- char *argv;
+- char *arg_save = NULL, *arg_org = NULL;
+- s32 err;
+- struct brcmf_pkt_filter_enable_le enable_parm;
+-
+- arg_save = kstrdup(arg, GFP_ATOMIC);
+- if (!arg_save)
+- goto fail;
+-
+- arg_org = arg_save;
+-
+- argv = strsep(&arg_save, " ");
+-
+- if (argv == NULL) {
+- brcmf_err("No args provided\n");
+- goto fail;
+- }
+-
+- /* Parse packet filter id. */
+- enable_parm.id = 0;
+- if (!kstrtoul(argv, 0, &res))
+- enable_parm.id = cpu_to_le32((u32)res);
+-
+- /* Enable/disable the specified filter. */
+- enable_parm.enable = cpu_to_le32(enable);
+-
+- err = brcmf_fil_iovar_data_set(ifp, "pkt_filter_enable", &enable_parm,
+- sizeof(enable_parm));
+- if (err)
+- brcmf_err("Set pkt_filter_enable error (%d)\n", err);
+-
+- /* Control the master mode */
+- err = brcmf_fil_iovar_int_set(ifp, "pkt_filter_mode", master_mode);
+- if (err)
+- brcmf_err("Set pkt_filter_mode error (%d)\n", err);
+-
+-fail:
+- kfree(arg_org);
+-}
+-
+-static void brcmf_c_pktfilter_offload_set(struct brcmf_if *ifp, char *arg)
+-{
+- struct brcmf_pkt_filter_le *pkt_filter;
+- unsigned long res;
+- int buf_len;
+- s32 err;
+- u32 mask_size;
+- u32 pattern_size;
+- char *argv[8], *buf = NULL;
+- int i = 0;
+- char *arg_save = NULL, *arg_org = NULL;
+-
+- arg_save = kstrdup(arg, GFP_ATOMIC);
+- if (!arg_save)
+- goto fail;
+-
+- arg_org = arg_save;
+-
+- buf = kmalloc(PKTFILTER_BUF_SIZE, GFP_ATOMIC);
+- if (!buf)
+- goto fail;
+-
+- argv[i] = strsep(&arg_save, " ");
+- while (argv[i]) {
+- i++;
+- if (i >= 8) {
+- brcmf_err("Too many parameters\n");
+- goto fail;
+- }
+- argv[i] = strsep(&arg_save, " ");
+- }
+-
+- if (i != 6) {
+- brcmf_err("Not enough args provided %d\n", i);
+- goto fail;
+- }
+-
+- pkt_filter = (struct brcmf_pkt_filter_le *)buf;
+-
+- /* Parse packet filter id. */
+- pkt_filter->id = 0;
+- if (!kstrtoul(argv[0], 0, &res))
+- pkt_filter->id = cpu_to_le32((u32)res);
+-
+- /* Parse filter polarity. */
+- pkt_filter->negate_match = 0;
+- if (!kstrtoul(argv[1], 0, &res))
+- pkt_filter->negate_match = cpu_to_le32((u32)res);
+-
+- /* Parse filter type. */
+- pkt_filter->type = 0;
+- if (!kstrtoul(argv[2], 0, &res))
+- pkt_filter->type = cpu_to_le32((u32)res);
+-
+- /* Parse pattern filter offset. */
+- pkt_filter->u.pattern.offset = 0;
+- if (!kstrtoul(argv[3], 0, &res))
+- pkt_filter->u.pattern.offset = cpu_to_le32((u32)res);
+-
+- /* Parse pattern filter mask. */
+- mask_size = brcmf_c_pattern_atoh(argv[4],
+- (char *)pkt_filter->u.pattern.mask_and_pattern);
+-
+- /* Parse pattern filter pattern. */
+- pattern_size = brcmf_c_pattern_atoh(argv[5],
+- (char *)&pkt_filter->u.pattern.mask_and_pattern[mask_size]);
+-
+- if (mask_size != pattern_size) {
+- brcmf_err("Mask and pattern not the same size\n");
+- goto fail;
+- }
+-
+- pkt_filter->u.pattern.size_bytes = cpu_to_le32(mask_size);
+- buf_len = offsetof(struct brcmf_pkt_filter_le,
+- u.pattern.mask_and_pattern);
+- buf_len += mask_size + pattern_size;
+-
+- err = brcmf_fil_iovar_data_set(ifp, "pkt_filter_add", pkt_filter,
+- buf_len);
+- if (err)
+- brcmf_err("Set pkt_filter_add error (%d)\n", err);
+-
+-fail:
+- kfree(arg_org);
+-
+- kfree(buf);
+-}
+-
+-int brcmf_c_preinit_dcmds(struct brcmf_if *ifp)
+-{
+- s8 eventmask[BRCMF_EVENTING_MASK_LEN];
+- u8 buf[BRCMF_DCMD_SMLEN];
+- char *ptr;
+- s32 err;
+-
+- /* retreive mac address */
+- err = brcmf_fil_iovar_data_get(ifp, "cur_etheraddr", ifp->mac_addr,
+- sizeof(ifp->mac_addr));
+- if (err < 0) {
+- brcmf_err("Retreiving cur_etheraddr failed, %d\n",
+- err);
+- goto done;
+- }
+- memcpy(ifp->drvr->mac, ifp->mac_addr, sizeof(ifp->drvr->mac));
+-
+- /* query for 'ver' to get version info from firmware */
+- memset(buf, 0, sizeof(buf));
+- strcpy(buf, "ver");
+- err = brcmf_fil_iovar_data_get(ifp, "ver", buf, sizeof(buf));
+- if (err < 0) {
+- brcmf_err("Retreiving version information failed, %d\n",
+- err);
+- goto done;
+- }
+- ptr = (char *)buf;
+- strsep(&ptr, "\n");
+-
+- /* Print fw version info */
+- brcmf_err("Firmware version = %s\n", buf);
+-
+- /* locate firmware version number for ethtool */
+- ptr = strrchr(buf, ' ') + 1;
+- strlcpy(ifp->drvr->fwver, ptr, sizeof(ifp->drvr->fwver));
+-
+- /*
+- * Setup timeout if Beacons are lost and roam is off to report
+- * link down
+- */
+- err = brcmf_fil_iovar_int_set(ifp, "bcn_timeout",
+- BRCMF_DEFAULT_BCN_TIMEOUT);
+- if (err) {
+- brcmf_err("bcn_timeout error (%d)\n", err);
+- goto done;
+- }
+-
+- /* Enable/Disable build-in roaming to allowed ext supplicant to take
+- * of romaing
+- */
+- err = brcmf_fil_iovar_int_set(ifp, "roam_off", 1);
+- if (err) {
+- brcmf_err("roam_off error (%d)\n", err);
+- goto done;
+- }
+-
+- /* Setup event_msgs, enable E_IF */
+- err = brcmf_fil_iovar_data_get(ifp, "event_msgs", eventmask,
+- BRCMF_EVENTING_MASK_LEN);
+- if (err) {
+- brcmf_err("Get event_msgs error (%d)\n", err);
+- goto done;
+- }
+- setbit(eventmask, BRCMF_E_IF);
+- err = brcmf_fil_iovar_data_set(ifp, "event_msgs", eventmask,
+- BRCMF_EVENTING_MASK_LEN);
+- if (err) {
+- brcmf_err("Set event_msgs error (%d)\n", err);
+- goto done;
+- }
+-
+- /* Setup default scan channel time */
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_CHANNEL_TIME,
+- BRCMF_DEFAULT_SCAN_CHANNEL_TIME);
+- if (err) {
+- brcmf_err("BRCMF_C_SET_SCAN_CHANNEL_TIME error (%d)\n",
+- err);
+- goto done;
+- }
+-
+- /* Setup default scan unassoc time */
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_UNASSOC_TIME,
+- BRCMF_DEFAULT_SCAN_UNASSOC_TIME);
+- if (err) {
+- brcmf_err("BRCMF_C_SET_SCAN_UNASSOC_TIME error (%d)\n",
+- err);
+- goto done;
+- }
+-
+- /* Setup packet filter */
+- brcmf_c_pktfilter_offload_set(ifp, BRCMF_DEFAULT_PACKET_FILTER);
+- brcmf_c_pktfilter_offload_enable(ifp, BRCMF_DEFAULT_PACKET_FILTER,
+- 0, true);
+-
+- /* do bus specific preinit here */
+- err = brcmf_bus_preinit(ifp->drvr->bus_if);
+-done:
+- return err;
+-}
+-
+-#ifdef CONFIG_BRCM_TRACING
+-void __brcmf_err(const char *func, const char *fmt, ...)
+-{
+- struct va_format vaf = {
+- .fmt = fmt,
+- };
+- va_list args;
+-
+- va_start(args, fmt);
+- vaf.va = &args;
+- pr_err("%s: %pV", func, &vaf);
+- trace_brcmf_err(func, &vaf);
+- va_end(args);
+-}
+-#endif
+-#if defined(CONFIG_BRCM_TRACING) || defined(CONFIG_BRCMDBG)
+-void __brcmf_dbg(u32 level, const char *func, const char *fmt, ...)
+-{
+- struct va_format vaf = {
+- .fmt = fmt,
+- };
+- va_list args;
+-
+- va_start(args, fmt);
+- vaf.va = &args;
+- if (brcmf_msg_level & level)
+- pr_debug("%s %pV", func, &vaf);
+- trace_brcmf_dbg(level, func, &vaf);
+- va_end(args);
+-}
+-#endif
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,245 +0,0 @@
+-/*
+- * Copyright (c) 2012 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-#include <linux/debugfs.h>
+-#include <linux/netdevice.h>
+-#include <linux/module.h>
+-
+-#include <brcmu_wifi.h>
+-#include <brcmu_utils.h>
+-#include "dhd.h"
+-#include "dhd_bus.h"
+-#include "dhd_dbg.h"
+-
+-static struct dentry *root_folder;
+-
+-void brcmf_debugfs_init(void)
+-{
+- root_folder = debugfs_create_dir(KBUILD_MODNAME, NULL);
+- if (IS_ERR(root_folder))
+- root_folder = NULL;
+-}
+-
+-void brcmf_debugfs_exit(void)
+-{
+- if (!root_folder)
+- return;
+-
+- debugfs_remove_recursive(root_folder);
+- root_folder = NULL;
+-}
+-
+-static
+-ssize_t brcmf_debugfs_chipinfo_read(struct file *f, char __user *data,
+- size_t count, loff_t *ppos)
+-{
+- struct brcmf_pub *drvr = f->private_data;
+- struct brcmf_bus *bus = drvr->bus_if;
+- char buf[40];
+- int res;
+-
+- /* only allow read from start */
+- if (*ppos > 0)
+- return 0;
+-
+- res = scnprintf(buf, sizeof(buf), "chip: %x(%u) rev %u\n",
+- bus->chip, bus->chip, bus->chiprev);
+- return simple_read_from_buffer(data, count, ppos, buf, res);
+-}
+-
+-static const struct file_operations brcmf_debugfs_chipinfo_ops = {
+- .owner = THIS_MODULE,
+- .open = simple_open,
+- .read = brcmf_debugfs_chipinfo_read
+-};
+-
+-static int brcmf_debugfs_create_chipinfo(struct brcmf_pub *drvr)
+-{
+- struct dentry *dentry = drvr->dbgfs_dir;
+-
+- if (!IS_ERR_OR_NULL(dentry))
+- debugfs_create_file("chipinfo", S_IRUGO, dentry, drvr,
+- &brcmf_debugfs_chipinfo_ops);
+- return 0;
+-}
+-
+-int brcmf_debugfs_attach(struct brcmf_pub *drvr)
+-{
+- struct device *dev = drvr->bus_if->dev;
+-
+- if (!root_folder)
+- return -ENODEV;
+-
+- drvr->dbgfs_dir = debugfs_create_dir(dev_name(dev), root_folder);
+- brcmf_debugfs_create_chipinfo(drvr);
+- return PTR_ERR_OR_ZERO(drvr->dbgfs_dir);
+-}
+-
+-void brcmf_debugfs_detach(struct brcmf_pub *drvr)
+-{
+- if (!IS_ERR_OR_NULL(drvr->dbgfs_dir))
+- debugfs_remove_recursive(drvr->dbgfs_dir);
+-}
+-
+-struct dentry *brcmf_debugfs_get_devdir(struct brcmf_pub *drvr)
+-{
+- return drvr->dbgfs_dir;
+-}
+-
+-static
+-ssize_t brcmf_debugfs_sdio_counter_read(struct file *f, char __user *data,
+- size_t count, loff_t *ppos)
+-{
+- struct brcmf_sdio_count *sdcnt = f->private_data;
+- char buf[750];
+- int res;
+-
+- /* only allow read from start */
+- if (*ppos > 0)
+- return 0;
+-
+- res = scnprintf(buf, sizeof(buf),
+- "intrcount: %u\nlastintrs: %u\n"
+- "pollcnt: %u\nregfails: %u\n"
+- "tx_sderrs: %u\nfcqueued: %u\n"
+- "rxrtx: %u\nrx_toolong: %u\n"
+- "rxc_errors: %u\nrx_hdrfail: %u\n"
+- "rx_badhdr: %u\nrx_badseq: %u\n"
+- "fc_rcvd: %u\nfc_xoff: %u\n"
+- "fc_xon: %u\nrxglomfail: %u\n"
+- "rxglomframes: %u\nrxglompkts: %u\n"
+- "f2rxhdrs: %u\nf2rxdata: %u\n"
+- "f2txdata: %u\nf1regdata: %u\n"
+- "tickcnt: %u\ntx_ctlerrs: %lu\n"
+- "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
+- "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
+- sdcnt->intrcount, sdcnt->lastintrs,
+- sdcnt->pollcnt, sdcnt->regfails,
+- sdcnt->tx_sderrs, sdcnt->fcqueued,
+- sdcnt->rxrtx, sdcnt->rx_toolong,
+- sdcnt->rxc_errors, sdcnt->rx_hdrfail,
+- sdcnt->rx_badhdr, sdcnt->rx_badseq,
+- sdcnt->fc_rcvd, sdcnt->fc_xoff,
+- sdcnt->fc_xon, sdcnt->rxglomfail,
+- sdcnt->rxglomframes, sdcnt->rxglompkts,
+- sdcnt->f2rxhdrs, sdcnt->f2rxdata,
+- sdcnt->f2txdata, sdcnt->f1regdata,
+- sdcnt->tickcnt, sdcnt->tx_ctlerrs,
+- sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
+- sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
+-
+- return simple_read_from_buffer(data, count, ppos, buf, res);
+-}
+-
+-static const struct file_operations brcmf_debugfs_sdio_counter_ops = {
+- .owner = THIS_MODULE,
+- .open = simple_open,
+- .read = brcmf_debugfs_sdio_counter_read
+-};
+-
+-void brcmf_debugfs_create_sdio_count(struct brcmf_pub *drvr,
+- struct brcmf_sdio_count *sdcnt)
+-{
+- struct dentry *dentry = drvr->dbgfs_dir;
+-
+- if (!IS_ERR_OR_NULL(dentry))
+- debugfs_create_file("counters", S_IRUGO, dentry,
+- sdcnt, &brcmf_debugfs_sdio_counter_ops);
+-}
+-
+-static
+-ssize_t brcmf_debugfs_fws_stats_read(struct file *f, char __user *data,
+- size_t count, loff_t *ppos)
+-{
+- struct brcmf_fws_stats *fwstats = f->private_data;
+- char buf[650];
+- int res;
+-
+- /* only allow read from start */
+- if (*ppos > 0)
+- return 0;
+-
+- res = scnprintf(buf, sizeof(buf),
+- "header_pulls: %u\n"
+- "header_only_pkt: %u\n"
+- "tlv_parse_failed: %u\n"
+- "tlv_invalid_type: %u\n"
+- "mac_update_fails: %u\n"
+- "ps_update_fails: %u\n"
+- "if_update_fails: %u\n"
+- "pkt2bus: %u\n"
+- "generic_error: %u\n"
+- "rollback_success: %u\n"
+- "rollback_failed: %u\n"
+- "delayq_full: %u\n"
+- "supprq_full: %u\n"
+- "txs_indicate: %u\n"
+- "txs_discard: %u\n"
+- "txs_suppr_core: %u\n"
+- "txs_suppr_ps: %u\n"
+- "txs_tossed: %u\n"
+- "txs_host_tossed: %u\n"
+- "bus_flow_block: %u\n"
+- "fws_flow_block: %u\n"
+- "send_pkts: BK:%u BE:%u VO:%u VI:%u BCMC:%u\n"
+- "requested_sent: BK:%u BE:%u VO:%u VI:%u BCMC:%u\n",
+- fwstats->header_pulls,
+- fwstats->header_only_pkt,
+- fwstats->tlv_parse_failed,
+- fwstats->tlv_invalid_type,
+- fwstats->mac_update_failed,
+- fwstats->mac_ps_update_failed,
+- fwstats->if_update_failed,
+- fwstats->pkt2bus,
+- fwstats->generic_error,
+- fwstats->rollback_success,
+- fwstats->rollback_failed,
+- fwstats->delayq_full_error,
+- fwstats->supprq_full_error,
+- fwstats->txs_indicate,
+- fwstats->txs_discard,
+- fwstats->txs_supp_core,
+- fwstats->txs_supp_ps,
+- fwstats->txs_tossed,
+- fwstats->txs_host_tossed,
+- fwstats->bus_flow_block,
+- fwstats->fws_flow_block,
+- fwstats->send_pkts[0], fwstats->send_pkts[1],
+- fwstats->send_pkts[2], fwstats->send_pkts[3],
+- fwstats->send_pkts[4],
+- fwstats->requested_sent[0],
+- fwstats->requested_sent[1],
+- fwstats->requested_sent[2],
+- fwstats->requested_sent[3],
+- fwstats->requested_sent[4]);
+-
+- return simple_read_from_buffer(data, count, ppos, buf, res);
+-}
+-
+-static const struct file_operations brcmf_debugfs_fws_stats_ops = {
+- .owner = THIS_MODULE,
+- .open = simple_open,
+- .read = brcmf_debugfs_fws_stats_read
+-};
+-
+-void brcmf_debugfs_create_fws_stats(struct brcmf_pub *drvr,
+- struct brcmf_fws_stats *stats)
+-{
+- struct dentry *dentry = drvr->dbgfs_dir;
+-
+- if (!IS_ERR_OR_NULL(dentry))
+- debugfs_create_file("fws_stats", S_IRUGO, dentry,
+- stats, &brcmf_debugfs_fws_stats_ops);
+-}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_dbg.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,196 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#ifndef _BRCMF_DBG_H_
+-#define _BRCMF_DBG_H_
+-
+-/* message levels */
+-#define BRCMF_TRACE_VAL 0x00000002
+-#define BRCMF_INFO_VAL 0x00000004
+-#define BRCMF_DATA_VAL 0x00000008
+-#define BRCMF_CTL_VAL 0x00000010
+-#define BRCMF_TIMER_VAL 0x00000020
+-#define BRCMF_HDRS_VAL 0x00000040
+-#define BRCMF_BYTES_VAL 0x00000080
+-#define BRCMF_INTR_VAL 0x00000100
+-#define BRCMF_GLOM_VAL 0x00000200
+-#define BRCMF_EVENT_VAL 0x00000400
+-#define BRCMF_BTA_VAL 0x00000800
+-#define BRCMF_FIL_VAL 0x00001000
+-#define BRCMF_USB_VAL 0x00002000
+-#define BRCMF_SCAN_VAL 0x00004000
+-#define BRCMF_CONN_VAL 0x00008000
+-#define BRCMF_BCDC_VAL 0x00010000
+-#define BRCMF_SDIO_VAL 0x00020000
+-
+-/* set default print format */
+-#undef pr_fmt
+-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+-
+-/* Macro for error messages. net_ratelimit() is used when driver
+- * debugging is not selected. When debugging the driver error
+- * messages are as important as other tracing or even more so.
+- */
+-#ifndef CONFIG_BRCM_TRACING
+-#ifdef CONFIG_BRCMDBG
+-#define brcmf_err(fmt, ...) pr_err("%s: " fmt, __func__, ##__VA_ARGS__)
+-#else
+-#define brcmf_err(fmt, ...) \
+- do { \
+- if (net_ratelimit()) \
+- pr_err("%s: " fmt, __func__, ##__VA_ARGS__); \
+- } while (0)
+-#endif
+-#else
+-__printf(2, 3)
+-void __brcmf_err(const char *func, const char *fmt, ...);
+-#define brcmf_err(fmt, ...) \
+- __brcmf_err(__func__, fmt, ##__VA_ARGS__)
+-#endif
+-
+-#if defined(DEBUG) || defined(CONFIG_BRCM_TRACING)
+-__printf(3, 4)
+-void __brcmf_dbg(u32 level, const char *func, const char *fmt, ...);
+-#define brcmf_dbg(level, fmt, ...) \
+-do { \
+- __brcmf_dbg(BRCMF_##level##_VAL, __func__, \
+- fmt, ##__VA_ARGS__); \
+-} while (0)
+-#define BRCMF_DATA_ON() (brcmf_msg_level & BRCMF_DATA_VAL)
+-#define BRCMF_CTL_ON() (brcmf_msg_level & BRCMF_CTL_VAL)
+-#define BRCMF_HDRS_ON() (brcmf_msg_level & BRCMF_HDRS_VAL)
+-#define BRCMF_BYTES_ON() (brcmf_msg_level & BRCMF_BYTES_VAL)
+-#define BRCMF_GLOM_ON() (brcmf_msg_level & BRCMF_GLOM_VAL)
+-#define BRCMF_EVENT_ON() (brcmf_msg_level & BRCMF_EVENT_VAL)
+-#define BRCMF_FIL_ON() (brcmf_msg_level & BRCMF_FIL_VAL)
+-
+-#else /* defined(DEBUG) || defined(CONFIG_BRCM_TRACING) */
+-
+-#define brcmf_dbg(level, fmt, ...) no_printk(fmt, ##__VA_ARGS__)
+-
+-#define BRCMF_DATA_ON() 0
+-#define BRCMF_CTL_ON() 0
+-#define BRCMF_HDRS_ON() 0
+-#define BRCMF_BYTES_ON() 0
+-#define BRCMF_GLOM_ON() 0
+-#define BRCMF_EVENT_ON() 0
+-#define BRCMF_FIL_ON() 0
+-
+-#endif /* defined(DEBUG) || defined(CONFIG_BRCM_TRACING) */
+-
+-#define brcmf_dbg_hex_dump(test, data, len, fmt, ...) \
+-do { \
+- trace_brcmf_hexdump((void *)data, len); \
+- if (test) \
+- brcmu_dbg_hex_dump(data, len, fmt, ##__VA_ARGS__); \
+-} while (0)
+-
+-extern int brcmf_msg_level;
+-
+-/*
+- * hold counter variables used in brcmfmac sdio driver.
+- */
+-struct brcmf_sdio_count {
+- uint intrcount; /* Count of device interrupt callbacks */
+- uint lastintrs; /* Count as of last watchdog timer */
+- uint pollcnt; /* Count of active polls */
+- uint regfails; /* Count of R_REG failures */
+- uint tx_sderrs; /* Count of tx attempts with sd errors */
+- uint fcqueued; /* Tx packets that got queued */
+- uint rxrtx; /* Count of rtx requests (NAK to dongle) */
+- uint rx_toolong; /* Receive frames too long to receive */
+- uint rxc_errors; /* SDIO errors when reading control frames */
+- uint rx_hdrfail; /* SDIO errors on header reads */
+- uint rx_badhdr; /* Bad received headers (roosync?) */
+- uint rx_badseq; /* Mismatched rx sequence number */
+- uint fc_rcvd; /* Number of flow-control events received */
+- uint fc_xoff; /* Number which turned on flow-control */
+- uint fc_xon; /* Number which turned off flow-control */
+- uint rxglomfail; /* Failed deglom attempts */
+- uint rxglomframes; /* Number of glom frames (superframes) */
+- uint rxglompkts; /* Number of packets from glom frames */
+- uint f2rxhdrs; /* Number of header reads */
+- uint f2rxdata; /* Number of frame data reads */
+- uint f2txdata; /* Number of f2 frame writes */
+- uint f1regdata; /* Number of f1 register accesses */
+- uint tickcnt; /* Number of watchdog been schedule */
+- ulong tx_ctlerrs; /* Err of sending ctrl frames */
+- ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
+- ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
+- ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
+- ulong rx_readahead_cnt; /* packets where header read-ahead was used */
+-};
+-
+-struct brcmf_fws_stats {
+- u32 tlv_parse_failed;
+- u32 tlv_invalid_type;
+- u32 header_only_pkt;
+- u32 header_pulls;
+- u32 pkt2bus;
+- u32 send_pkts[5];
+- u32 requested_sent[5];
+- u32 generic_error;
+- u32 mac_update_failed;
+- u32 mac_ps_update_failed;
+- u32 if_update_failed;
+- u32 packet_request_failed;
+- u32 credit_request_failed;
+- u32 rollback_success;
+- u32 rollback_failed;
+- u32 delayq_full_error;
+- u32 supprq_full_error;
+- u32 txs_indicate;
+- u32 txs_discard;
+- u32 txs_supp_core;
+- u32 txs_supp_ps;
+- u32 txs_tossed;
+- u32 txs_host_tossed;
+- u32 bus_flow_block;
+- u32 fws_flow_block;
+-};
+-
+-struct brcmf_pub;
+-#ifdef DEBUG
+-void brcmf_debugfs_init(void);
+-void brcmf_debugfs_exit(void);
+-int brcmf_debugfs_attach(struct brcmf_pub *drvr);
+-void brcmf_debugfs_detach(struct brcmf_pub *drvr);
+-struct dentry *brcmf_debugfs_get_devdir(struct brcmf_pub *drvr);
+-void brcmf_debugfs_create_sdio_count(struct brcmf_pub *drvr,
+- struct brcmf_sdio_count *sdcnt);
+-void brcmf_debugfs_create_fws_stats(struct brcmf_pub *drvr,
+- struct brcmf_fws_stats *stats);
+-#else
+-static inline void brcmf_debugfs_init(void)
+-{
+-}
+-static inline void brcmf_debugfs_exit(void)
+-{
+-}
+-static inline int brcmf_debugfs_attach(struct brcmf_pub *drvr)
+-{
+- return 0;
+-}
+-static inline void brcmf_debugfs_detach(struct brcmf_pub *drvr)
+-{
+-}
+-static inline void brcmf_debugfs_create_fws_stats(struct brcmf_pub *drvr,
+- struct brcmf_fws_stats *stats)
+-{
+-}
+-#endif
+-
+-#endif /* _BRCMF_DBG_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,195 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-/****************
+- * Common types *
+- */
+-
+-#ifndef _BRCMF_H_
+-#define _BRCMF_H_
+-
+-#include "fweh.h"
+-
+-#define TOE_TX_CSUM_OL 0x00000001
+-#define TOE_RX_CSUM_OL 0x00000002
+-
+-/* For supporting multiple interfaces */
+-#define BRCMF_MAX_IFS 16
+-
+-#define DOT11_MAX_DEFAULT_KEYS 4
+-
+-/* Small, medium and maximum buffer size for dcmd
+- */
+-#define BRCMF_DCMD_SMLEN 256
+-#define BRCMF_DCMD_MEDLEN 1536
+-#define BRCMF_DCMD_MAXLEN 8192
+-
+-/* IOCTL from host to device are limited in lenght. A device can only handle
+- * ethernet frame size. This limitation is to be applied by protocol layer.
+- */
+-#define BRCMF_TX_IOCTL_MAX_MSG_SIZE (ETH_FRAME_LEN+ETH_FCS_LEN)
+-
+-#define BRCMF_AMPDU_RX_REORDER_MAXFLOWS 256
+-
+-/* Length of firmware version string stored for
+- * ethtool driver info which uses 32 bytes as well.
+- */
+-#define BRCMF_DRIVER_FIRMWARE_VERSION_LEN 32
+-
+-/* Bus independent dongle command */
+-struct brcmf_dcmd {
+- uint cmd; /* common dongle cmd definition */
+- void *buf; /* pointer to user buffer */
+- uint len; /* length of user buffer */
+- u8 set; /* get or set request (optional) */
+- uint used; /* bytes read or written (optional) */
+- uint needed; /* bytes needed (optional) */
+-};
+-
+-/**
+- * struct brcmf_ampdu_rx_reorder - AMPDU receive reorder info
+- *
+- * @pktslots: dynamic allocated array for ordering AMPDU packets.
+- * @flow_id: AMPDU flow identifier.
+- * @cur_idx: last AMPDU index from firmware.
+- * @exp_idx: expected next AMPDU index.
+- * @max_idx: maximum amount of packets per AMPDU.
+- * @pend_pkts: number of packets currently in @pktslots.
+- */
+-struct brcmf_ampdu_rx_reorder {
+- struct sk_buff **pktslots;
+- u8 flow_id;
+- u8 cur_idx;
+- u8 exp_idx;
+- u8 max_idx;
+- u8 pend_pkts;
+-};
+-
+-/* Forward decls for struct brcmf_pub (see below) */
+-struct brcmf_proto; /* device communication protocol info */
+-struct brcmf_cfg80211_dev; /* cfg80211 device info */
+-struct brcmf_fws_info; /* firmware signalling info */
+-
+-/* Common structure for module and instance linkage */
+-struct brcmf_pub {
+- /* Linkage ponters */
+- struct brcmf_bus *bus_if;
+- struct brcmf_proto *proto;
+- struct brcmf_cfg80211_info *config;
+-
+- /* Internal brcmf items */
+- uint hdrlen; /* Total BRCMF header length (proto + bus) */
+- uint rxsz; /* Rx buffer size bus module should use */
+- u8 wme_dp; /* wme discard priority */
+-
+- /* Dongle media info */
+- char fwver[BRCMF_DRIVER_FIRMWARE_VERSION_LEN];
+- u8 mac[ETH_ALEN]; /* MAC address obtained from dongle */
+-
+- /* Multicast data packets sent to dongle */
+- unsigned long tx_multicast;
+-
+- struct brcmf_if *iflist[BRCMF_MAX_IFS];
+-
+- struct mutex proto_block;
+- unsigned char proto_buf[BRCMF_DCMD_MAXLEN];
+-
+- struct brcmf_fweh_info fweh;
+-
+- struct brcmf_fws_info *fws;
+-
+- struct brcmf_ampdu_rx_reorder
+- *reorder_flows[BRCMF_AMPDU_RX_REORDER_MAXFLOWS];
+-#ifdef DEBUG
+- struct dentry *dbgfs_dir;
+-#endif
+-};
+-
+-/* forward declarations */
+-struct brcmf_cfg80211_vif;
+-struct brcmf_fws_mac_descriptor;
+-
+-/**
+- * enum brcmf_netif_stop_reason - reason for stopping netif queue.
+- *
+- * @BRCMF_NETIF_STOP_REASON_FWS_FC:
+- * netif stopped due to firmware signalling flow control.
+- * @BRCMF_NETIF_STOP_REASON_BLOCK_BUS:
+- * netif stopped due to bus blocking.
+- */
+-enum brcmf_netif_stop_reason {
+- BRCMF_NETIF_STOP_REASON_FWS_FC = 1,
+- BRCMF_NETIF_STOP_REASON_BLOCK_BUS = 2
+-};
+-
+-/**
+- * struct brcmf_if - interface control information.
+- *
+- * @drvr: points to device related information.
+- * @vif: points to cfg80211 specific interface information.
+- * @ndev: associated network device.
+- * @stats: interface specific network statistics.
+- * @setmacaddr_work: worker object for setting mac address.
+- * @multicast_work: worker object for multicast provisioning.
+- * @fws_desc: interface specific firmware-signalling descriptor.
+- * @ifidx: interface index in device firmware.
+- * @bssidx: index of bss associated with this interface.
+- * @mac_addr: assigned mac address.
+- * @netif_stop: bitmap indicates reason why netif queues are stopped.
+- * @netif_stop_lock: spinlock for update netif_stop from multiple sources.
+- * @pend_8021x_cnt: tracks outstanding number of 802.1x frames.
+- * @pend_8021x_wait: used for signalling change in count.
+- */
+-struct brcmf_if {
+- struct brcmf_pub *drvr;
+- struct brcmf_cfg80211_vif *vif;
+- struct net_device *ndev;
+- struct net_device_stats stats;
+- struct work_struct setmacaddr_work;
+- struct work_struct multicast_work;
+- struct brcmf_fws_mac_descriptor *fws_desc;
+- int ifidx;
+- s32 bssidx;
+- u8 mac_addr[ETH_ALEN];
+- u8 netif_stop;
+- spinlock_t netif_stop_lock;
+- atomic_t pend_8021x_cnt;
+- wait_queue_head_t pend_8021x_wait;
+-};
+-
+-struct brcmf_skb_reorder_data {
+- u8 *reorder;
+-};
+-
+-int brcmf_netdev_wait_pend8021x(struct net_device *ndev);
+-
+-/* Return pointer to interface name */
+-char *brcmf_ifname(struct brcmf_pub *drvr, int idx);
+-
+-int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked);
+-struct brcmf_if *brcmf_add_if(struct brcmf_pub *drvr, s32 bssidx, s32 ifidx,
+- char *name, u8 *mac_addr);
+-void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx);
+-void brcmf_txflowblock_if(struct brcmf_if *ifp,
+- enum brcmf_netif_stop_reason reason, bool state);
+-u32 brcmf_get_chip_info(struct brcmf_if *ifp);
+-void brcmf_txfinalize(struct brcmf_pub *drvr, struct sk_buff *txp,
+- bool success);
+-
+-/* Sets dongle media info (drv_version, mac address). */
+-int brcmf_c_preinit_dcmds(struct brcmf_if *ifp);
+-
+-#endif /* _BRCMF_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,1128 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/etherdevice.h>
+-#include <linux/module.h>
+-#include <net/cfg80211.h>
+-#include <net/rtnetlink.h>
+-#include <brcmu_utils.h>
+-#include <brcmu_wifi.h>
+-
+-#include "dhd.h"
+-#include "dhd_bus.h"
+-#include "dhd_dbg.h"
+-#include "fwil_types.h"
+-#include "p2p.h"
+-#include "wl_cfg80211.h"
+-#include "fwil.h"
+-#include "fwsignal.h"
+-#include "proto.h"
+-
+-MODULE_AUTHOR("Broadcom Corporation");
+-MODULE_DESCRIPTION("Broadcom 802.11 wireless LAN fullmac driver.");
+-MODULE_LICENSE("Dual BSD/GPL");
+-
+-#define MAX_WAIT_FOR_8021X_TX 50 /* msecs */
+-
+-/* AMPDU rx reordering definitions */
+-#define BRCMF_RXREORDER_FLOWID_OFFSET 0
+-#define BRCMF_RXREORDER_MAXIDX_OFFSET 2
+-#define BRCMF_RXREORDER_FLAGS_OFFSET 4
+-#define BRCMF_RXREORDER_CURIDX_OFFSET 6
+-#define BRCMF_RXREORDER_EXPIDX_OFFSET 8
+-
+-#define BRCMF_RXREORDER_DEL_FLOW 0x01
+-#define BRCMF_RXREORDER_FLUSH_ALL 0x02
+-#define BRCMF_RXREORDER_CURIDX_VALID 0x04
+-#define BRCMF_RXREORDER_EXPIDX_VALID 0x08
+-#define BRCMF_RXREORDER_NEW_HOLE 0x10
+-
+-/* Error bits */
+-int brcmf_msg_level;
+-module_param_named(debug, brcmf_msg_level, int, S_IRUSR | S_IWUSR);
+-MODULE_PARM_DESC(debug, "level of debug output");
+-
+-/* P2P0 enable */
+-static int brcmf_p2p_enable;
+-#ifdef CONFIG_BRCMDBG
+-module_param_named(p2pon, brcmf_p2p_enable, int, 0);
+-MODULE_PARM_DESC(p2pon, "enable p2p management functionality");
+-#endif
+-
+-char *brcmf_ifname(struct brcmf_pub *drvr, int ifidx)
+-{
+- if (ifidx < 0 || ifidx >= BRCMF_MAX_IFS) {
+- brcmf_err("ifidx %d out of range\n", ifidx);
+- return "<if_bad>";
+- }
+-
+- if (drvr->iflist[ifidx] == NULL) {
+- brcmf_err("null i/f %d\n", ifidx);
+- return "<if_null>";
+- }
+-
+- if (drvr->iflist[ifidx]->ndev)
+- return drvr->iflist[ifidx]->ndev->name;
+-
+- return "<if_none>";
+-}
+-
+-static void _brcmf_set_multicast_list(struct work_struct *work)
+-{
+- struct brcmf_if *ifp;
+- struct net_device *ndev;
+- struct netdev_hw_addr *ha;
+- u32 cmd_value, cnt;
+- __le32 cnt_le;
+- char *buf, *bufp;
+- u32 buflen;
+- s32 err;
+-
+- ifp = container_of(work, struct brcmf_if, multicast_work);
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
+-
+- ndev = ifp->ndev;
+-
+- /* Determine initial value of allmulti flag */
+- cmd_value = (ndev->flags & IFF_ALLMULTI) ? true : false;
+-
+- /* Send down the multicast list first. */
+- cnt = netdev_mc_count(ndev);
+- buflen = sizeof(cnt) + (cnt * ETH_ALEN);
+- buf = kmalloc(buflen, GFP_ATOMIC);
+- if (!buf)
+- return;
+- bufp = buf;
+-
+- cnt_le = cpu_to_le32(cnt);
+- memcpy(bufp, &cnt_le, sizeof(cnt_le));
+- bufp += sizeof(cnt_le);
+-
+- netdev_for_each_mc_addr(ha, ndev) {
+- if (!cnt)
+- break;
+- memcpy(bufp, ha->addr, ETH_ALEN);
+- bufp += ETH_ALEN;
+- cnt--;
+- }
+-
+- err = brcmf_fil_iovar_data_set(ifp, "mcast_list", buf, buflen);
+- if (err < 0) {
+- brcmf_err("Setting mcast_list failed, %d\n", err);
+- cmd_value = cnt ? true : cmd_value;
+- }
+-
+- kfree(buf);
+-
+- /*
+- * Now send the allmulti setting. This is based on the setting in the
+- * net_device flags, but might be modified above to be turned on if we
+- * were trying to set some addresses and dongle rejected it...
+- */
+- err = brcmf_fil_iovar_int_set(ifp, "allmulti", cmd_value);
+- if (err < 0)
+- brcmf_err("Setting allmulti failed, %d\n", err);
+-
+- /*Finally, pick up the PROMISC flag */
+- cmd_value = (ndev->flags & IFF_PROMISC) ? true : false;
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PROMISC, cmd_value);
+- if (err < 0)
+- brcmf_err("Setting BRCMF_C_SET_PROMISC failed, %d\n",
+- err);
+-}
+-
+-static void
+-_brcmf_set_mac_address(struct work_struct *work)
+-{
+- struct brcmf_if *ifp;
+- s32 err;
+-
+- ifp = container_of(work, struct brcmf_if, setmacaddr_work);
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
+-
+- err = brcmf_fil_iovar_data_set(ifp, "cur_etheraddr", ifp->mac_addr,
+- ETH_ALEN);
+- if (err < 0) {
+- brcmf_err("Setting cur_etheraddr failed, %d\n", err);
+- } else {
+- brcmf_dbg(TRACE, "MAC address updated to %pM\n",
+- ifp->mac_addr);
+- memcpy(ifp->ndev->dev_addr, ifp->mac_addr, ETH_ALEN);
+- }
+-}
+-
+-static int brcmf_netdev_set_mac_address(struct net_device *ndev, void *addr)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct sockaddr *sa = (struct sockaddr *)addr;
+-
+- memcpy(&ifp->mac_addr, sa->sa_data, ETH_ALEN);
+- schedule_work(&ifp->setmacaddr_work);
+- return 0;
+-}
+-
+-static void brcmf_netdev_set_multicast_list(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+-
+- schedule_work(&ifp->multicast_work);
+-}
+-
+-static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb,
+- struct net_device *ndev)
+-{
+- int ret;
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_pub *drvr = ifp->drvr;
+- struct ethhdr *eh;
+-
+- brcmf_dbg(DATA, "Enter, idx=%d\n", ifp->bssidx);
+-
+- /* Can the device send data? */
+- if (drvr->bus_if->state != BRCMF_BUS_DATA) {
+- brcmf_err("xmit rejected state=%d\n", drvr->bus_if->state);
+- netif_stop_queue(ndev);
+- dev_kfree_skb(skb);
+- ret = -ENODEV;
+- goto done;
+- }
+-
+- if (!drvr->iflist[ifp->bssidx]) {
+- brcmf_err("bad ifidx %d\n", ifp->bssidx);
+- netif_stop_queue(ndev);
+- dev_kfree_skb(skb);
+- ret = -ENODEV;
+- goto done;
+- }
+-
+- /* Make sure there's enough room for any header */
+- if (skb_headroom(skb) < drvr->hdrlen) {
+- struct sk_buff *skb2;
+-
+- brcmf_dbg(INFO, "%s: insufficient headroom\n",
+- brcmf_ifname(drvr, ifp->bssidx));
+- drvr->bus_if->tx_realloc++;
+- skb2 = skb_realloc_headroom(skb, drvr->hdrlen);
+- dev_kfree_skb(skb);
+- skb = skb2;
+- if (skb == NULL) {
+- brcmf_err("%s: skb_realloc_headroom failed\n",
+- brcmf_ifname(drvr, ifp->bssidx));
+- ret = -ENOMEM;
+- goto done;
+- }
+- }
+-
+- /* validate length for ether packet */
+- if (skb->len < sizeof(*eh)) {
+- ret = -EINVAL;
+- dev_kfree_skb(skb);
+- goto done;
+- }
+-
+- ret = brcmf_fws_process_skb(ifp, skb);
+-
+-done:
+- if (ret) {
+- ifp->stats.tx_dropped++;
+- } else {
+- ifp->stats.tx_packets++;
+- ifp->stats.tx_bytes += skb->len;
+- }
+-
+- /* Return ok: we always eat the packet */
+- return NETDEV_TX_OK;
+-}
+-
+-void brcmf_txflowblock_if(struct brcmf_if *ifp,
+- enum brcmf_netif_stop_reason reason, bool state)
+-{
+- unsigned long flags;
+-
+- if (!ifp || !ifp->ndev)
+- return;
+-
+- brcmf_dbg(TRACE, "enter: idx=%d stop=0x%X reason=%d state=%d\n",
+- ifp->bssidx, ifp->netif_stop, reason, state);
+-
+- spin_lock_irqsave(&ifp->netif_stop_lock, flags);
+- if (state) {
+- if (!ifp->netif_stop)
+- netif_stop_queue(ifp->ndev);
+- ifp->netif_stop |= reason;
+- } else {
+- ifp->netif_stop &= ~reason;
+- if (!ifp->netif_stop)
+- netif_wake_queue(ifp->ndev);
+- }
+- spin_unlock_irqrestore(&ifp->netif_stop_lock, flags);
+-}
+-
+-void brcmf_txflowblock(struct device *dev, bool state)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- brcmf_fws_bus_blocked(drvr, state);
+-}
+-
+-static void brcmf_netif_rx(struct brcmf_if *ifp, struct sk_buff *skb)
+-{
+- skb->dev = ifp->ndev;
+- skb->protocol = eth_type_trans(skb, skb->dev);
+-
+- if (skb->pkt_type == PACKET_MULTICAST)
+- ifp->stats.multicast++;
+-
+- /* Process special event packets */
+- brcmf_fweh_process_skb(ifp->drvr, skb);
+-
+- if (!(ifp->ndev->flags & IFF_UP)) {
+- brcmu_pkt_buf_free_skb(skb);
+- return;
+- }
+-
+- ifp->stats.rx_bytes += skb->len;
+- ifp->stats.rx_packets++;
+-
+- brcmf_dbg(DATA, "rx proto=0x%X\n", ntohs(skb->protocol));
+- if (in_interrupt())
+- netif_rx(skb);
+- else
+- /* If the receive is not processed inside an ISR,
+- * the softirqd must be woken explicitly to service
+- * the NET_RX_SOFTIRQ. This is handled by netif_rx_ni().
+- */
+- netif_rx_ni(skb);
+-}
+-
+-static void brcmf_rxreorder_get_skb_list(struct brcmf_ampdu_rx_reorder *rfi,
+- u8 start, u8 end,
+- struct sk_buff_head *skb_list)
+-{
+- /* initialize return list */
+- __skb_queue_head_init(skb_list);
+-
+- if (rfi->pend_pkts == 0) {
+- brcmf_dbg(INFO, "no packets in reorder queue\n");
+- return;
+- }
+-
+- do {
+- if (rfi->pktslots[start]) {
+- __skb_queue_tail(skb_list, rfi->pktslots[start]);
+- rfi->pktslots[start] = NULL;
+- }
+- start++;
+- if (start > rfi->max_idx)
+- start = 0;
+- } while (start != end);
+- rfi->pend_pkts -= skb_queue_len(skb_list);
+-}
+-
+-static void brcmf_rxreorder_process_info(struct brcmf_if *ifp, u8 *reorder_data,
+- struct sk_buff *pkt)
+-{
+- u8 flow_id, max_idx, cur_idx, exp_idx, end_idx;
+- struct brcmf_ampdu_rx_reorder *rfi;
+- struct sk_buff_head reorder_list;
+- struct sk_buff *pnext;
+- u8 flags;
+- u32 buf_size;
+-
+- flow_id = reorder_data[BRCMF_RXREORDER_FLOWID_OFFSET];
+- flags = reorder_data[BRCMF_RXREORDER_FLAGS_OFFSET];
+-
+- /* validate flags and flow id */
+- if (flags == 0xFF) {
+- brcmf_err("invalid flags...so ignore this packet\n");
+- brcmf_netif_rx(ifp, pkt);
+- return;
+- }
+-
+- rfi = ifp->drvr->reorder_flows[flow_id];
+- if (flags & BRCMF_RXREORDER_DEL_FLOW) {
+- brcmf_dbg(INFO, "flow-%d: delete\n",
+- flow_id);
+-
+- if (rfi == NULL) {
+- brcmf_dbg(INFO, "received flags to cleanup, but no flow (%d) yet\n",
+- flow_id);
+- brcmf_netif_rx(ifp, pkt);
+- return;
+- }
+-
+- brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, rfi->exp_idx,
+- &reorder_list);
+- /* add the last packet */
+- __skb_queue_tail(&reorder_list, pkt);
+- kfree(rfi);
+- ifp->drvr->reorder_flows[flow_id] = NULL;
+- goto netif_rx;
+- }
+- /* from here on we need a flow reorder instance */
+- if (rfi == NULL) {
+- buf_size = sizeof(*rfi);
+- max_idx = reorder_data[BRCMF_RXREORDER_MAXIDX_OFFSET];
+-
+- buf_size += (max_idx + 1) * sizeof(pkt);
+-
+- /* allocate space for flow reorder info */
+- brcmf_dbg(INFO, "flow-%d: start, maxidx %d\n",
+- flow_id, max_idx);
+- rfi = kzalloc(buf_size, GFP_ATOMIC);
+- if (rfi == NULL) {
+- brcmf_err("failed to alloc buffer\n");
+- brcmf_netif_rx(ifp, pkt);
+- return;
+- }
+-
+- ifp->drvr->reorder_flows[flow_id] = rfi;
+- rfi->pktslots = (struct sk_buff **)(rfi+1);
+- rfi->max_idx = max_idx;
+- }
+- if (flags & BRCMF_RXREORDER_NEW_HOLE) {
+- if (rfi->pend_pkts) {
+- brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx,
+- rfi->exp_idx,
+- &reorder_list);
+- WARN_ON(rfi->pend_pkts);
+- } else {
+- __skb_queue_head_init(&reorder_list);
+- }
+- rfi->cur_idx = reorder_data[BRCMF_RXREORDER_CURIDX_OFFSET];
+- rfi->exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
+- rfi->max_idx = reorder_data[BRCMF_RXREORDER_MAXIDX_OFFSET];
+- rfi->pktslots[rfi->cur_idx] = pkt;
+- rfi->pend_pkts++;
+- brcmf_dbg(DATA, "flow-%d: new hole %d (%d), pending %d\n",
+- flow_id, rfi->cur_idx, rfi->exp_idx, rfi->pend_pkts);
+- } else if (flags & BRCMF_RXREORDER_CURIDX_VALID) {
+- cur_idx = reorder_data[BRCMF_RXREORDER_CURIDX_OFFSET];
+- exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
+-
+- if ((exp_idx == rfi->exp_idx) && (cur_idx != rfi->exp_idx)) {
+- /* still in the current hole */
+- /* enqueue the current on the buffer chain */
+- if (rfi->pktslots[cur_idx] != NULL) {
+- brcmf_dbg(INFO, "HOLE: ERROR buffer pending..free it\n");
+- brcmu_pkt_buf_free_skb(rfi->pktslots[cur_idx]);
+- rfi->pktslots[cur_idx] = NULL;
+- }
+- rfi->pktslots[cur_idx] = pkt;
+- rfi->pend_pkts++;
+- rfi->cur_idx = cur_idx;
+- brcmf_dbg(DATA, "flow-%d: store pkt %d (%d), pending %d\n",
+- flow_id, cur_idx, exp_idx, rfi->pend_pkts);
+-
+- /* can return now as there is no reorder
+- * list to process.
+- */
+- return;
+- }
+- if (rfi->exp_idx == cur_idx) {
+- if (rfi->pktslots[cur_idx] != NULL) {
+- brcmf_dbg(INFO, "error buffer pending..free it\n");
+- brcmu_pkt_buf_free_skb(rfi->pktslots[cur_idx]);
+- rfi->pktslots[cur_idx] = NULL;
+- }
+- rfi->pktslots[cur_idx] = pkt;
+- rfi->pend_pkts++;
+-
+- /* got the expected one. flush from current to expected
+- * and update expected
+- */
+- brcmf_dbg(DATA, "flow-%d: expected %d (%d), pending %d\n",
+- flow_id, cur_idx, exp_idx, rfi->pend_pkts);
+-
+- rfi->cur_idx = cur_idx;
+- rfi->exp_idx = exp_idx;
+-
+- brcmf_rxreorder_get_skb_list(rfi, cur_idx, exp_idx,
+- &reorder_list);
+- brcmf_dbg(DATA, "flow-%d: freeing buffers %d, pending %d\n",
+- flow_id, skb_queue_len(&reorder_list),
+- rfi->pend_pkts);
+- } else {
+- u8 end_idx;
+-
+- brcmf_dbg(DATA, "flow-%d (0x%x): both moved, old %d/%d, new %d/%d\n",
+- flow_id, flags, rfi->cur_idx, rfi->exp_idx,
+- cur_idx, exp_idx);
+- if (flags & BRCMF_RXREORDER_FLUSH_ALL)
+- end_idx = rfi->exp_idx;
+- else
+- end_idx = exp_idx;
+-
+- /* flush pkts first */
+- brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, end_idx,
+- &reorder_list);
+-
+- if (exp_idx == ((cur_idx + 1) % (rfi->max_idx + 1))) {
+- __skb_queue_tail(&reorder_list, pkt);
+- } else {
+- rfi->pktslots[cur_idx] = pkt;
+- rfi->pend_pkts++;
+- }
+- rfi->exp_idx = exp_idx;
+- rfi->cur_idx = cur_idx;
+- }
+- } else {
+- /* explicity window move updating the expected index */
+- exp_idx = reorder_data[BRCMF_RXREORDER_EXPIDX_OFFSET];
+-
+- brcmf_dbg(DATA, "flow-%d (0x%x): change expected: %d -> %d\n",
+- flow_id, flags, rfi->exp_idx, exp_idx);
+- if (flags & BRCMF_RXREORDER_FLUSH_ALL)
+- end_idx = rfi->exp_idx;
+- else
+- end_idx = exp_idx;
+-
+- brcmf_rxreorder_get_skb_list(rfi, rfi->exp_idx, end_idx,
+- &reorder_list);
+- __skb_queue_tail(&reorder_list, pkt);
+- /* set the new expected idx */
+- rfi->exp_idx = exp_idx;
+- }
+-netif_rx:
+- skb_queue_walk_safe(&reorder_list, pkt, pnext) {
+- __skb_unlink(pkt, &reorder_list);
+- brcmf_netif_rx(ifp, pkt);
+- }
+-}
+-
+-void brcmf_rx_frame(struct device *dev, struct sk_buff *skb)
+-{
+- struct brcmf_if *ifp;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+- struct brcmf_skb_reorder_data *rd;
+- u8 ifidx;
+- int ret;
+-
+- brcmf_dbg(DATA, "Enter: %s: rxp=%p\n", dev_name(dev), skb);
+-
+- /* process and remove protocol-specific header */
+- ret = brcmf_proto_hdrpull(drvr, true, &ifidx, skb);
+- ifp = drvr->iflist[ifidx];
+-
+- if (ret || !ifp || !ifp->ndev) {
+- if ((ret != -ENODATA) && ifp)
+- ifp->stats.rx_errors++;
+- brcmu_pkt_buf_free_skb(skb);
+- return;
+- }
+-
+- rd = (struct brcmf_skb_reorder_data *)skb->cb;
+- if (rd->reorder)
+- brcmf_rxreorder_process_info(ifp, rd->reorder, skb);
+- else
+- brcmf_netif_rx(ifp, skb);
+-}
+-
+-void brcmf_txfinalize(struct brcmf_pub *drvr, struct sk_buff *txp,
+- bool success)
+-{
+- struct brcmf_if *ifp;
+- struct ethhdr *eh;
+- u8 ifidx;
+- u16 type;
+- int res;
+-
+- res = brcmf_proto_hdrpull(drvr, false, &ifidx, txp);
+-
+- ifp = drvr->iflist[ifidx];
+- if (!ifp)
+- goto done;
+-
+- if (res == 0) {
+- eh = (struct ethhdr *)(txp->data);
+- type = ntohs(eh->h_proto);
+-
+- if (type == ETH_P_PAE) {
+- atomic_dec(&ifp->pend_8021x_cnt);
+- if (waitqueue_active(&ifp->pend_8021x_wait))
+- wake_up(&ifp->pend_8021x_wait);
+- }
+- }
+- if (!success)
+- ifp->stats.tx_errors++;
+-done:
+- brcmu_pkt_buf_free_skb(txp);
+-}
+-
+-void brcmf_txcomplete(struct device *dev, struct sk_buff *txp, bool success)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+-
+- /* await txstatus signal for firmware if active */
+- if (brcmf_fws_fc_active(drvr->fws)) {
+- if (!success)
+- brcmf_fws_bustxfail(drvr->fws, txp);
+- } else {
+- brcmf_txfinalize(drvr, txp, success);
+- }
+-}
+-
+-static struct net_device_stats *brcmf_netdev_get_stats(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
+-
+- return &ifp->stats;
+-}
+-
+-static void brcmf_ethtool_get_drvinfo(struct net_device *ndev,
+- struct ethtool_drvinfo *info)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_pub *drvr = ifp->drvr;
+-
+- strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
+- snprintf(info->version, sizeof(info->version), "n/a");
+- strlcpy(info->fw_version, drvr->fwver, sizeof(info->fw_version));
+- strlcpy(info->bus_info, dev_name(drvr->bus_if->dev),
+- sizeof(info->bus_info));
+-}
+-
+-static const struct ethtool_ops brcmf_ethtool_ops = {
+- .get_drvinfo = brcmf_ethtool_get_drvinfo,
+-};
+-
+-static int brcmf_netdev_stop(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
+-
+- brcmf_cfg80211_down(ndev);
+-
+- /* Set state and stop OS transmissions */
+- netif_stop_queue(ndev);
+-
+- return 0;
+-}
+-
+-static int brcmf_netdev_open(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_pub *drvr = ifp->drvr;
+- struct brcmf_bus *bus_if = drvr->bus_if;
+- u32 toe_ol;
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d\n", ifp->bssidx);
+-
+- /* If bus is not ready, can't continue */
+- if (bus_if->state != BRCMF_BUS_DATA) {
+- brcmf_err("failed bus is not ready\n");
+- return -EAGAIN;
+- }
+-
+- atomic_set(&ifp->pend_8021x_cnt, 0);
+-
+- /* Get current TOE mode from dongle */
+- if (brcmf_fil_iovar_int_get(ifp, "toe_ol", &toe_ol) >= 0
+- && (toe_ol & TOE_TX_CSUM_OL) != 0)
+- ndev->features |= NETIF_F_IP_CSUM;
+- else
+- ndev->features &= ~NETIF_F_IP_CSUM;
+-
+- if (brcmf_cfg80211_up(ndev)) {
+- brcmf_err("failed to bring up cfg80211\n");
+- return -EIO;
+- }
+-
+- /* Allow transmit calls */
+- netif_start_queue(ndev);
+- return 0;
+-}
+-
+-static const struct net_device_ops brcmf_netdev_ops_pri = {
+- .ndo_open = brcmf_netdev_open,
+- .ndo_stop = brcmf_netdev_stop,
+- .ndo_get_stats = brcmf_netdev_get_stats,
+- .ndo_start_xmit = brcmf_netdev_start_xmit,
+- .ndo_set_mac_address = brcmf_netdev_set_mac_address,
+- .ndo_set_rx_mode = brcmf_netdev_set_multicast_list
+-};
+-
+-int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked)
+-{
+- struct brcmf_pub *drvr = ifp->drvr;
+- struct net_device *ndev;
+- s32 err;
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d mac=%pM\n", ifp->bssidx,
+- ifp->mac_addr);
+- ndev = ifp->ndev;
+-
+- /* set appropriate operations */
+- ndev->netdev_ops = &brcmf_netdev_ops_pri;
+-
+- ndev->hard_header_len += drvr->hdrlen;
+- ndev->ethtool_ops = &brcmf_ethtool_ops;
+-
+- drvr->rxsz = ndev->mtu + ndev->hard_header_len +
+- drvr->hdrlen;
+-
+- /* set the mac address */
+- memcpy(ndev->dev_addr, ifp->mac_addr, ETH_ALEN);
+-
+- INIT_WORK(&ifp->setmacaddr_work, _brcmf_set_mac_address);
+- INIT_WORK(&ifp->multicast_work, _brcmf_set_multicast_list);
+-
+- if (rtnl_locked)
+- err = register_netdevice(ndev);
+- else
+- err = register_netdev(ndev);
+- if (err != 0) {
+- brcmf_err("couldn't register the net device\n");
+- goto fail;
+- }
+-
+- brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
+-
+- ndev->destructor = brcmf_cfg80211_free_netdev;
+- return 0;
+-
+-fail:
+- drvr->iflist[ifp->bssidx] = NULL;
+- ndev->netdev_ops = NULL;
+- free_netdev(ndev);
+- return -EBADE;
+-}
+-
+-static int brcmf_net_p2p_open(struct net_device *ndev)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- return brcmf_cfg80211_up(ndev);
+-}
+-
+-static int brcmf_net_p2p_stop(struct net_device *ndev)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- return brcmf_cfg80211_down(ndev);
+-}
+-
+-static netdev_tx_t brcmf_net_p2p_start_xmit(struct sk_buff *skb,
+- struct net_device *ndev)
+-{
+- if (skb)
+- dev_kfree_skb_any(skb);
+-
+- return NETDEV_TX_OK;
+-}
+-
+-static const struct net_device_ops brcmf_netdev_ops_p2p = {
+- .ndo_open = brcmf_net_p2p_open,
+- .ndo_stop = brcmf_net_p2p_stop,
+- .ndo_start_xmit = brcmf_net_p2p_start_xmit
+-};
+-
+-static int brcmf_net_p2p_attach(struct brcmf_if *ifp)
+-{
+- struct net_device *ndev;
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d mac=%pM\n", ifp->bssidx,
+- ifp->mac_addr);
+- ndev = ifp->ndev;
+-
+- ndev->netdev_ops = &brcmf_netdev_ops_p2p;
+-
+- /* set the mac address */
+- memcpy(ndev->dev_addr, ifp->mac_addr, ETH_ALEN);
+-
+- if (register_netdev(ndev) != 0) {
+- brcmf_err("couldn't register the p2p net device\n");
+- goto fail;
+- }
+-
+- brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
+-
+- return 0;
+-
+-fail:
+- ifp->drvr->iflist[ifp->bssidx] = NULL;
+- ndev->netdev_ops = NULL;
+- free_netdev(ndev);
+- return -EBADE;
+-}
+-
+-struct brcmf_if *brcmf_add_if(struct brcmf_pub *drvr, s32 bssidx, s32 ifidx,
+- char *name, u8 *mac_addr)
+-{
+- struct brcmf_if *ifp;
+- struct net_device *ndev;
+-
+- brcmf_dbg(TRACE, "Enter, idx=%d, ifidx=%d\n", bssidx, ifidx);
+-
+- ifp = drvr->iflist[bssidx];
+- /*
+- * Delete the existing interface before overwriting it
+- * in case we missed the BRCMF_E_IF_DEL event.
+- */
+- if (ifp) {
+- brcmf_err("ERROR: netdev:%s already exists\n",
+- ifp->ndev->name);
+- if (ifidx) {
+- netif_stop_queue(ifp->ndev);
+- unregister_netdev(ifp->ndev);
+- free_netdev(ifp->ndev);
+- drvr->iflist[bssidx] = NULL;
+- } else {
+- brcmf_err("ignore IF event\n");
+- return ERR_PTR(-EINVAL);
+- }
+- }
+-
+- if (!brcmf_p2p_enable && bssidx == 1) {
+- /* this is P2P_DEVICE interface */
+- brcmf_dbg(INFO, "allocate non-netdev interface\n");
+- ifp = kzalloc(sizeof(*ifp), GFP_KERNEL);
+- if (!ifp)
+- return ERR_PTR(-ENOMEM);
+- } else {
+- brcmf_dbg(INFO, "allocate netdev interface\n");
+- /* Allocate netdev, including space for private structure */
+- ndev = alloc_netdev(sizeof(*ifp), name, ether_setup);
+- if (!ndev)
+- return ERR_PTR(-ENOMEM);
+-
+- ifp = netdev_priv(ndev);
+- ifp->ndev = ndev;
+- }
+-
+- ifp->drvr = drvr;
+- drvr->iflist[bssidx] = ifp;
+- ifp->ifidx = ifidx;
+- ifp->bssidx = bssidx;
+-
+- init_waitqueue_head(&ifp->pend_8021x_wait);
+- spin_lock_init(&ifp->netif_stop_lock);
+-
+- if (mac_addr != NULL)
+- memcpy(ifp->mac_addr, mac_addr, ETH_ALEN);
+-
+- brcmf_dbg(TRACE, " ==== pid:%x, if:%s (%pM) created ===\n",
+- current->pid, name, ifp->mac_addr);
+-
+- return ifp;
+-}
+-
+-void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
+-{
+- struct brcmf_if *ifp;
+-
+- ifp = drvr->iflist[bssidx];
+- drvr->iflist[bssidx] = NULL;
+- if (!ifp) {
+- brcmf_err("Null interface, idx=%d\n", bssidx);
+- return;
+- }
+- brcmf_dbg(TRACE, "Enter, idx=%d, ifidx=%d\n", bssidx, ifp->ifidx);
+- if (ifp->ndev) {
+- if (bssidx == 0) {
+- if (ifp->ndev->netdev_ops == &brcmf_netdev_ops_pri) {
+- rtnl_lock();
+- brcmf_netdev_stop(ifp->ndev);
+- rtnl_unlock();
+- }
+- } else {
+- netif_stop_queue(ifp->ndev);
+- }
+-
+- if (ifp->ndev->netdev_ops == &brcmf_netdev_ops_pri) {
+- cancel_work_sync(&ifp->setmacaddr_work);
+- cancel_work_sync(&ifp->multicast_work);
+- }
+- /* unregister will take care of freeing it */
+- unregister_netdev(ifp->ndev);
+- } else {
+- kfree(ifp);
+- }
+-}
+-
+-int brcmf_attach(struct device *dev)
+-{
+- struct brcmf_pub *drvr = NULL;
+- int ret = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* Allocate primary brcmf_info */
+- drvr = kzalloc(sizeof(struct brcmf_pub), GFP_ATOMIC);
+- if (!drvr)
+- return -ENOMEM;
+-
+- mutex_init(&drvr->proto_block);
+-
+- /* Link to bus module */
+- drvr->hdrlen = 0;
+- drvr->bus_if = dev_get_drvdata(dev);
+- drvr->bus_if->drvr = drvr;
+-
+- /* create device debugfs folder */
+- brcmf_debugfs_attach(drvr);
+-
+- /* Attach and link in the protocol */
+- ret = brcmf_proto_attach(drvr);
+- if (ret != 0) {
+- brcmf_err("brcmf_prot_attach failed\n");
+- goto fail;
+- }
+-
+- /* attach firmware event handler */
+- brcmf_fweh_attach(drvr);
+-
+- return ret;
+-
+-fail:
+- brcmf_detach(dev);
+-
+- return ret;
+-}
+-
+-int brcmf_bus_start(struct device *dev)
+-{
+- int ret = -1;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+- struct brcmf_if *ifp;
+- struct brcmf_if *p2p_ifp;
+-
+- brcmf_dbg(TRACE, "\n");
+-
+- /* Bring up the bus */
+- ret = brcmf_bus_init(bus_if);
+- if (ret != 0) {
+- brcmf_err("brcmf_sdbrcm_bus_init failed %d\n", ret);
+- return ret;
+- }
+-
+- /* add primary networking interface */
+- ifp = brcmf_add_if(drvr, 0, 0, "wlan%d", NULL);
+- if (IS_ERR(ifp))
+- return PTR_ERR(ifp);
+-
+- if (brcmf_p2p_enable)
+- p2p_ifp = brcmf_add_if(drvr, 1, 0, "p2p%d", NULL);
+- else
+- p2p_ifp = NULL;
+- if (IS_ERR(p2p_ifp))
+- p2p_ifp = NULL;
+-
+- /* signal bus ready */
+- brcmf_bus_change_state(bus_if, BRCMF_BUS_DATA);
+-
+- /* Bus is ready, do any initialization */
+- ret = brcmf_c_preinit_dcmds(ifp);
+- if (ret < 0)
+- goto fail;
+-
+- ret = brcmf_fws_init(drvr);
+- if (ret < 0)
+- goto fail;
+-
+- brcmf_fws_add_interface(ifp);
+-
+- drvr->config = brcmf_cfg80211_attach(drvr, bus_if->dev);
+- if (drvr->config == NULL) {
+- ret = -ENOMEM;
+- goto fail;
+- }
+-
+- ret = brcmf_fweh_activate_events(ifp);
+- if (ret < 0)
+- goto fail;
+-
+- ret = brcmf_net_attach(ifp, false);
+-fail:
+- if (ret < 0) {
+- brcmf_err("failed: %d\n", ret);
+- brcmf_cfg80211_detach(drvr->config);
+- if (drvr->fws) {
+- brcmf_fws_del_interface(ifp);
+- brcmf_fws_deinit(drvr);
+- }
+- if (drvr->iflist[0]) {
+- free_netdev(ifp->ndev);
+- drvr->iflist[0] = NULL;
+- }
+- if (p2p_ifp) {
+- free_netdev(p2p_ifp->ndev);
+- drvr->iflist[1] = NULL;
+- }
+- return ret;
+- }
+- if ((brcmf_p2p_enable) && (p2p_ifp))
+- if (brcmf_net_p2p_attach(p2p_ifp) < 0)
+- brcmf_p2p_enable = 0;
+-
+- return 0;
+-}
+-
+-void brcmf_bus_add_txhdrlen(struct device *dev, uint len)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+-
+- if (drvr) {
+- drvr->hdrlen += len;
+- }
+-}
+-
+-static void brcmf_bus_detach(struct brcmf_pub *drvr)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (drvr) {
+- /* Stop the bus module */
+- brcmf_bus_stop(drvr->bus_if);
+- }
+-}
+-
+-void brcmf_dev_reset(struct device *dev)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+-
+- if (drvr == NULL)
+- return;
+-
+- if (drvr->iflist[0])
+- brcmf_fil_cmd_int_set(drvr->iflist[0], BRCMF_C_TERMINATED, 1);
+-}
+-
+-void brcmf_detach(struct device *dev)
+-{
+- s32 i;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_pub *drvr = bus_if->drvr;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (drvr == NULL)
+- return;
+-
+- /* stop firmware event handling */
+- brcmf_fweh_detach(drvr);
+-
+- brcmf_bus_change_state(bus_if, BRCMF_BUS_DOWN);
+-
+- /* make sure primary interface removed last */
+- for (i = BRCMF_MAX_IFS-1; i > -1; i--)
+- if (drvr->iflist[i]) {
+- brcmf_fws_del_interface(drvr->iflist[i]);
+- brcmf_del_if(drvr, i);
+- }
+-
+- brcmf_cfg80211_detach(drvr->config);
+-
+- brcmf_bus_detach(drvr);
+-
+- brcmf_proto_detach(drvr);
+-
+- brcmf_fws_deinit(drvr);
+-
+- brcmf_debugfs_detach(drvr);
+- bus_if->drvr = NULL;
+- kfree(drvr);
+-}
+-
+-s32 brcmf_iovar_data_set(struct device *dev, char *name, void *data, u32 len)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_if *ifp = bus_if->drvr->iflist[0];
+-
+- return brcmf_fil_iovar_data_set(ifp, name, data, len);
+-}
+-
+-static int brcmf_get_pend_8021x_cnt(struct brcmf_if *ifp)
+-{
+- return atomic_read(&ifp->pend_8021x_cnt);
+-}
+-
+-int brcmf_netdev_wait_pend8021x(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- int err;
+-
+- err = wait_event_timeout(ifp->pend_8021x_wait,
+- !brcmf_get_pend_8021x_cnt(ifp),
+- msecs_to_jiffies(MAX_WAIT_FOR_8021X_TX));
+-
+- WARN_ON(!err);
+-
+- return !err;
+-}
+-
+-/*
+- * return chip id and rev of the device encoded in u32.
+- */
+-u32 brcmf_get_chip_info(struct brcmf_if *ifp)
+-{
+- struct brcmf_bus *bus = ifp->drvr->bus_if;
+-
+- return bus->chip << 4 | bus->chiprev;
+-}
+-
+-static void brcmf_driver_register(struct work_struct *work)
+-{
+-#ifdef CONFIG_BRCMFMAC_SDIO
+- brcmf_sdio_register();
+-#endif
+-#ifdef CONFIG_BRCMFMAC_USB
+- brcmf_usb_register();
+-#endif
+-}
+-static DECLARE_WORK(brcmf_driver_work, brcmf_driver_register);
+-
+-static int __init brcmfmac_module_init(void)
+-{
+- brcmf_debugfs_init();
+-#ifdef CONFIG_BRCMFMAC_SDIO
+- brcmf_sdio_init();
+-#endif
+- if (!schedule_work(&brcmf_driver_work))
+- return -EBUSY;
+-
+- return 0;
+-}
+-
+-static void __exit brcmfmac_module_exit(void)
+-{
+- cancel_work_sync(&brcmf_driver_work);
+-
+-#ifdef CONFIG_BRCMFMAC_SDIO
+- brcmf_sdio_exit();
+-#endif
+-#ifdef CONFIG_BRCMFMAC_USB
+- brcmf_usb_exit();
+-#endif
+- brcmf_debugfs_exit();
+-}
+-
+-module_init(brcmfmac_module_init);
+-module_exit(brcmfmac_module_exit);
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,4097 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#include <linux/types.h>
+-#include <linux/kernel.h>
+-#include <linux/kthread.h>
+-#include <linux/printk.h>
+-#include <linux/pci_ids.h>
+-#include <linux/netdevice.h>
+-#include <linux/interrupt.h>
+-#include <linux/sched.h>
+-#include <linux/mmc/sdio.h>
+-#include <linux/mmc/sdio_func.h>
+-#include <linux/mmc/card.h>
+-#include <linux/semaphore.h>
+-#include <linux/firmware.h>
+-#include <linux/module.h>
+-#include <linux/bcma/bcma.h>
+-#include <linux/debugfs.h>
+-#include <linux/vmalloc.h>
+-#include <linux/platform_data/brcmfmac-sdio.h>
+-#include <linux/moduleparam.h>
+-#include <asm/unaligned.h>
+-#include <defs.h>
+-#include <brcmu_wifi.h>
+-#include <brcmu_utils.h>
+-#include <brcm_hw_ids.h>
+-#include <soc.h>
+-#include "sdio_host.h"
+-#include "sdio_chip.h"
+-#include "nvram.h"
+-
+-#define DCMD_RESP_TIMEOUT 2000 /* In milli second */
+-
+-#ifdef DEBUG
+-
+-#define BRCMF_TRAP_INFO_SIZE 80
+-
+-#define CBUF_LEN (128)
+-
+-/* Device console log buffer state */
+-#define CONSOLE_BUFFER_MAX 2024
+-
+-struct rte_log_le {
+- __le32 buf; /* Can't be pointer on (64-bit) hosts */
+- __le32 buf_size;
+- __le32 idx;
+- char *_buf_compat; /* Redundant pointer for backward compat. */
+-};
+-
+-struct rte_console {
+- /* Virtual UART
+- * When there is no UART (e.g. Quickturn),
+- * the host should write a complete
+- * input line directly into cbuf and then write
+- * the length into vcons_in.
+- * This may also be used when there is a real UART
+- * (at risk of conflicting with
+- * the real UART). vcons_out is currently unused.
+- */
+- uint vcons_in;
+- uint vcons_out;
+-
+- /* Output (logging) buffer
+- * Console output is written to a ring buffer log_buf at index log_idx.
+- * The host may read the output when it sees log_idx advance.
+- * Output will be lost if the output wraps around faster than the host
+- * polls.
+- */
+- struct rte_log_le log_le;
+-
+- /* Console input line buffer
+- * Characters are read one at a time into cbuf
+- * until <CR> is received, then
+- * the buffer is processed as a command line.
+- * Also used for virtual UART.
+- */
+- uint cbuf_idx;
+- char cbuf[CBUF_LEN];
+-};
+-
+-#endif /* DEBUG */
+-#include <chipcommon.h>
+-
+-#include "dhd_bus.h"
+-#include "dhd_dbg.h"
+-#include "tracepoint.h"
+-
+-#define TXQLEN 2048 /* bulk tx queue length */
+-#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
+-#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
+-#define PRIOMASK 7
+-
+-#define TXRETRIES 2 /* # of retries for tx frames */
+-
+-#define BRCMF_RXBOUND 50 /* Default for max rx frames in
+- one scheduling */
+-
+-#define BRCMF_TXBOUND 20 /* Default for max tx frames in
+- one scheduling */
+-
+-#define BRCMF_DEFAULT_TXGLOM_SIZE 32 /* max tx frames in glom chain */
+-
+-#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
+-
+-#define MEMBLOCK 2048 /* Block size used for downloading
+- of dongle image */
+-#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
+- biggest possible glom */
+-
+-#define BRCMF_FIRSTREAD (1 << 6)
+-
+-
+-/* SBSDIO_DEVICE_CTL */
+-
+-/* 1: device will assert busy signal when receiving CMD53 */
+-#define SBSDIO_DEVCTL_SETBUSY 0x01
+-/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
+-#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
+-/* 1: mask all interrupts to host except the chipActive (rev 8) */
+-#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
+-/* 1: isolate internal sdio signals, put external pads in tri-state; requires
+- * sdio bus power cycle to clear (rev 9) */
+-#define SBSDIO_DEVCTL_PADS_ISO 0x08
+-/* Force SD->SB reset mapping (rev 11) */
+-#define SBSDIO_DEVCTL_SB_RST_CTL 0x30
+-/* Determined by CoreControl bit */
+-#define SBSDIO_DEVCTL_RST_CORECTL 0x00
+-/* Force backplane reset */
+-#define SBSDIO_DEVCTL_RST_BPRESET 0x10
+-/* Force no backplane reset */
+-#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
+-
+-/* direct(mapped) cis space */
+-
+-/* MAPPED common CIS address */
+-#define SBSDIO_CIS_BASE_COMMON 0x1000
+-/* maximum bytes in one CIS */
+-#define SBSDIO_CIS_SIZE_LIMIT 0x200
+-/* cis offset addr is < 17 bits */
+-#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
+-
+-/* manfid tuple length, include tuple, link bytes */
+-#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
+-
+-/* intstatus */
+-#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
+-#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
+-#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
+-#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
+-#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
+-#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
+-#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
+-#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
+-#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
+-#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
+-#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
+-#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
+-#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
+-#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
+-#define I_PC (1 << 10) /* descriptor error */
+-#define I_PD (1 << 11) /* data error */
+-#define I_DE (1 << 12) /* Descriptor protocol Error */
+-#define I_RU (1 << 13) /* Receive descriptor Underflow */
+-#define I_RO (1 << 14) /* Receive fifo Overflow */
+-#define I_XU (1 << 15) /* Transmit fifo Underflow */
+-#define I_RI (1 << 16) /* Receive Interrupt */
+-#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
+-#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
+-#define I_XI (1 << 24) /* Transmit Interrupt */
+-#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
+-#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
+-#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
+-#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
+-#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
+-#define I_SRESET (1 << 30) /* CCCR RES interrupt */
+-#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
+-#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
+-#define I_DMA (I_RI | I_XI | I_ERRORS)
+-
+-/* corecontrol */
+-#define CC_CISRDY (1 << 0) /* CIS Ready */
+-#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
+-#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
+-#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
+-#define CC_XMTDATAAVAIL_MODE (1 << 4)
+-#define CC_XMTDATAAVAIL_CTRL (1 << 5)
+-
+-/* SDA_FRAMECTRL */
+-#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
+-#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
+-#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
+-#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
+-
+-/*
+- * Software allocation of To SB Mailbox resources
+- */
+-
+-/* tosbmailbox bits corresponding to intstatus bits */
+-#define SMB_NAK (1 << 0) /* Frame NAK */
+-#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
+-#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
+-#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
+-
+-/* tosbmailboxdata */
+-#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
+-
+-/*
+- * Software allocation of To Host Mailbox resources
+- */
+-
+-/* intstatus bits */
+-#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
+-#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
+-#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
+-#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
+-
+-/* tohostmailboxdata */
+-#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
+-#define HMB_DATA_DEVREADY 2 /* talk to host after enable */
+-#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
+-#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
+-
+-#define HMB_DATA_FCDATA_MASK 0xff000000
+-#define HMB_DATA_FCDATA_SHIFT 24
+-
+-#define HMB_DATA_VERSION_MASK 0x00ff0000
+-#define HMB_DATA_VERSION_SHIFT 16
+-
+-/*
+- * Software-defined protocol header
+- */
+-
+-/* Current protocol version */
+-#define SDPCM_PROT_VERSION 4
+-
+-/*
+- * Shared structure between dongle and the host.
+- * The structure contains pointers to trap or assert information.
+- */
+-#define SDPCM_SHARED_VERSION 0x0003
+-#define SDPCM_SHARED_VERSION_MASK 0x00FF
+-#define SDPCM_SHARED_ASSERT_BUILT 0x0100
+-#define SDPCM_SHARED_ASSERT 0x0200
+-#define SDPCM_SHARED_TRAP 0x0400
+-
+-/* Space for header read, limit for data packets */
+-#define MAX_HDR_READ (1 << 6)
+-#define MAX_RX_DATASZ 2048
+-
+-/* Bump up limit on waiting for HT to account for first startup;
+- * if the image is doing a CRC calculation before programming the PMU
+- * for HT availability, it could take a couple hundred ms more, so
+- * max out at a 1 second (1000000us).
+- */
+-#undef PMU_MAX_TRANSITION_DLY
+-#define PMU_MAX_TRANSITION_DLY 1000000
+-
+-/* Value for ChipClockCSR during initial setup */
+-#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
+- SBSDIO_ALP_AVAIL_REQ)
+-
+-/* Flags for SDH calls */
+-#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
+-
+-#define BRCMF_IDLE_IMMEDIATE (-1) /* Enter idle immediately */
+-#define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
+- * when idle
+- */
+-#define BRCMF_IDLE_INTERVAL 1
+-
+-#define KSO_WAIT_US 50
+-#define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
+-
+-/*
+- * Conversion of 802.1D priority to precedence level
+- */
+-static uint prio2prec(u32 prio)
+-{
+- return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
+- (prio^2) : prio;
+-}
+-
+-#ifdef DEBUG
+-/* Device console log buffer state */
+-struct brcmf_console {
+- uint count; /* Poll interval msec counter */
+- uint log_addr; /* Log struct address (fixed) */
+- struct rte_log_le log_le; /* Log struct (host copy) */
+- uint bufsize; /* Size of log buffer */
+- u8 *buf; /* Log buffer (host copy) */
+- uint last; /* Last buffer read index */
+-};
+-
+-struct brcmf_trap_info {
+- __le32 type;
+- __le32 epc;
+- __le32 cpsr;
+- __le32 spsr;
+- __le32 r0; /* a1 */
+- __le32 r1; /* a2 */
+- __le32 r2; /* a3 */
+- __le32 r3; /* a4 */
+- __le32 r4; /* v1 */
+- __le32 r5; /* v2 */
+- __le32 r6; /* v3 */
+- __le32 r7; /* v4 */
+- __le32 r8; /* v5 */
+- __le32 r9; /* sb/v6 */
+- __le32 r10; /* sl/v7 */
+- __le32 r11; /* fp/v8 */
+- __le32 r12; /* ip */
+- __le32 r13; /* sp */
+- __le32 r14; /* lr */
+- __le32 pc; /* r15 */
+-};
+-#endif /* DEBUG */
+-
+-struct sdpcm_shared {
+- u32 flags;
+- u32 trap_addr;
+- u32 assert_exp_addr;
+- u32 assert_file_addr;
+- u32 assert_line;
+- u32 console_addr; /* Address of struct rte_console */
+- u32 msgtrace_addr;
+- u8 tag[32];
+- u32 brpt_addr;
+-};
+-
+-struct sdpcm_shared_le {
+- __le32 flags;
+- __le32 trap_addr;
+- __le32 assert_exp_addr;
+- __le32 assert_file_addr;
+- __le32 assert_line;
+- __le32 console_addr; /* Address of struct rte_console */
+- __le32 msgtrace_addr;
+- u8 tag[32];
+- __le32 brpt_addr;
+-};
+-
+-/* dongle SDIO bus specific header info */
+-struct brcmf_sdio_hdrinfo {
+- u8 seq_num;
+- u8 channel;
+- u16 len;
+- u16 len_left;
+- u16 len_nxtfrm;
+- u8 dat_offset;
+- bool lastfrm;
+- u16 tail_pad;
+-};
+-
+-/* misc chip info needed by some of the routines */
+-/* Private data for SDIO bus interaction */
+-struct brcmf_sdio {
+- struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
+- struct brcmf_chip *ci; /* Chip info struct */
+-
+- u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
+-
+- u32 hostintmask; /* Copy of Host Interrupt Mask */
+- atomic_t intstatus; /* Intstatus bits (events) pending */
+- atomic_t fcstate; /* State of dongle flow-control */
+-
+- uint blocksize; /* Block size of SDIO transfers */
+- uint roundup; /* Max roundup limit */
+-
+- struct pktq txq; /* Queue length used for flow-control */
+- u8 flowcontrol; /* per prio flow control bitmask */
+- u8 tx_seq; /* Transmit sequence number (next) */
+- u8 tx_max; /* Maximum transmit sequence allowed */
+-
+- u8 *hdrbuf; /* buffer for handling rx frame */
+- u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
+- u8 rx_seq; /* Receive sequence number (expected) */
+- struct brcmf_sdio_hdrinfo cur_read;
+- /* info of current read frame */
+- bool rxskip; /* Skip receive (awaiting NAK ACK) */
+- bool rxpending; /* Data frame pending in dongle */
+-
+- uint rxbound; /* Rx frames to read before resched */
+- uint txbound; /* Tx frames to send before resched */
+- uint txminmax;
+-
+- struct sk_buff *glomd; /* Packet containing glomming descriptor */
+- struct sk_buff_head glom; /* Packet list for glommed superframe */
+- uint glomerr; /* Glom packet read errors */
+-
+- u8 *rxbuf; /* Buffer for receiving control packets */
+- uint rxblen; /* Allocated length of rxbuf */
+- u8 *rxctl; /* Aligned pointer into rxbuf */
+- u8 *rxctl_orig; /* pointer for freeing rxctl */
+- uint rxlen; /* Length of valid data in buffer */
+- spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
+-
+- u8 sdpcm_ver; /* Bus protocol reported by dongle */
+-
+- bool intr; /* Use interrupts */
+- bool poll; /* Use polling */
+- atomic_t ipend; /* Device interrupt is pending */
+- uint spurious; /* Count of spurious interrupts */
+- uint pollrate; /* Ticks between device polls */
+- uint polltick; /* Tick counter */
+-
+-#ifdef DEBUG
+- uint console_interval;
+- struct brcmf_console console; /* Console output polling support */
+- uint console_addr; /* Console address from shared struct */
+-#endif /* DEBUG */
+-
+- uint clkstate; /* State of sd and backplane clock(s) */
+- bool activity; /* Activity flag for clock down */
+- s32 idletime; /* Control for activity timeout */
+- s32 idlecount; /* Activity timeout counter */
+- s32 idleclock; /* How to set bus driver when idle */
+- bool rxflow_mode; /* Rx flow control mode */
+- bool rxflow; /* Is rx flow control on */
+- bool alp_only; /* Don't use HT clock (ALP only) */
+-
+- u8 *ctrl_frame_buf;
+- u32 ctrl_frame_len;
+- bool ctrl_frame_stat;
+-
+- spinlock_t txqlock;
+- wait_queue_head_t ctrl_wait;
+- wait_queue_head_t dcmd_resp_wait;
+-
+- struct timer_list timer;
+- struct completion watchdog_wait;
+- struct task_struct *watchdog_tsk;
+- bool wd_timer_valid;
+- uint save_ms;
+-
+- struct workqueue_struct *brcmf_wq;
+- struct work_struct datawork;
+- atomic_t dpc_tskcnt;
+-
+- bool txoff; /* Transmit flow-controlled */
+- struct brcmf_sdio_count sdcnt;
+- bool sr_enabled; /* SaveRestore enabled */
+- bool sleeping; /* SDIO bus sleeping */
+-
+- u8 tx_hdrlen; /* sdio bus header length for tx packet */
+- bool txglom; /* host tx glomming enable flag */
+- u16 head_align; /* buffer pointer alignment */
+- u16 sgentry_align; /* scatter-gather buffer alignment */
+-};
+-
+-/* clkstate */
+-#define CLK_NONE 0
+-#define CLK_SDONLY 1
+-#define CLK_PENDING 2
+-#define CLK_AVAIL 3
+-
+-#ifdef DEBUG
+-static int qcount[NUMPRIO];
+-#endif /* DEBUG */
+-
+-#define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
+-
+-#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
+-
+-/* Retry count for register access failures */
+-static const uint retry_limit = 2;
+-
+-/* Limit on rounding up frames */
+-static const uint max_roundup = 512;
+-
+-#define ALIGNMENT 4
+-
+-static int brcmf_sdio_txglomsz = BRCMF_DEFAULT_TXGLOM_SIZE;
+-module_param_named(txglomsz, brcmf_sdio_txglomsz, int, 0);
+-MODULE_PARM_DESC(txglomsz, "maximum tx packet chain size [SDIO]");
+-
+-enum brcmf_sdio_frmtype {
+- BRCMF_SDIO_FT_NORMAL,
+- BRCMF_SDIO_FT_SUPER,
+- BRCMF_SDIO_FT_SUB,
+-};
+-
+-#define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
+-#define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
+-#define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
+-#define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
+-#define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
+-#define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
+-#define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
+-#define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
+-#define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
+-#define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
+-#define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
+-#define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
+-#define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
+-#define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
+-#define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
+-#define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
+-#define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
+-#define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
+-
+-MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
+-MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
+-MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
+-
+-struct brcmf_firmware_names {
+- u32 chipid;
+- u32 revmsk;
+- const char *bin;
+- const char *nv;
+-};
+-
+-enum brcmf_firmware_type {
+- BRCMF_FIRMWARE_BIN,
+- BRCMF_FIRMWARE_NVRAM
+-};
+-
+-#define BRCMF_FIRMWARE_NVRAM(name) \
+- name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
+-
+-static const struct brcmf_firmware_names brcmf_fwname_data[] = {
+- { BCM43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
+- { BCM43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
+- { BCM43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
+- { BCM4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
+- { BCM4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
+- { BCM4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
+- { BCM4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
+- { BCM43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
+- { BCM4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) }
+-};
+-
+-
+-static const struct firmware *brcmf_sdio_get_fw(struct brcmf_sdio *bus,
+- enum brcmf_firmware_type type)
+-{
+- const struct firmware *fw;
+- const char *name;
+- int err, i;
+-
+- for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
+- if (brcmf_fwname_data[i].chipid == bus->ci->chip &&
+- brcmf_fwname_data[i].revmsk & BIT(bus->ci->chiprev)) {
+- switch (type) {
+- case BRCMF_FIRMWARE_BIN:
+- name = brcmf_fwname_data[i].bin;
+- break;
+- case BRCMF_FIRMWARE_NVRAM:
+- name = brcmf_fwname_data[i].nv;
+- break;
+- default:
+- brcmf_err("invalid firmware type (%d)\n", type);
+- return NULL;
+- }
+- goto found;
+- }
+- }
+- brcmf_err("Unknown chipid %d [%d]\n",
+- bus->ci->chip, bus->ci->chiprev);
+- return NULL;
+-
+-found:
+- err = request_firmware(&fw, name, &bus->sdiodev->func[2]->dev);
+- if ((err) || (!fw)) {
+- brcmf_err("fail to request firmware %s (%d)\n", name, err);
+- return NULL;
+- }
+-
+- return fw;
+-}
+-
+-static void pkt_align(struct sk_buff *p, int len, int align)
+-{
+- uint datalign;
+- datalign = (unsigned long)(p->data);
+- datalign = roundup(datalign, (align)) - datalign;
+- if (datalign)
+- skb_pull(p, datalign);
+- __skb_trim(p, len);
+-}
+-
+-/* To check if there's window offered */
+-static bool data_ok(struct brcmf_sdio *bus)
+-{
+- return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
+- ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
+-}
+-
+-/*
+- * Reads a register in the SDIO hardware block. This block occupies a series of
+- * adresses on the 32 bit backplane bus.
+- */
+-static int
+-r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
+-{
+- u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
+- int ret;
+-
+- *regvar = brcmf_sdiod_regrl(bus->sdiodev,
+- bus->ci->c_inf[idx].base + offset, &ret);
+-
+- return ret;
+-}
+-
+-static int
+-w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
+-{
+- u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
+- int ret;
+-
+- brcmf_sdiod_regwl(bus->sdiodev,
+- bus->ci->c_inf[idx].base + reg_offset,
+- regval, &ret);
+-
+- return ret;
+-}
+-
+-static int
+-brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
+-{
+- u8 wr_val = 0, rd_val, cmp_val, bmask;
+- int err = 0;
+- int try_cnt = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
+- /* 1st KSO write goes to AOS wake up core if device is asleep */
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- wr_val, &err);
+- if (err) {
+- brcmf_err("SDIO_AOS KSO write error: %d\n", err);
+- return err;
+- }
+-
+- if (on) {
+- /* device WAKEUP through KSO:
+- * write bit 0 & read back until
+- * both bits 0 (kso bit) & 1 (dev on status) are set
+- */
+- cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
+- SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
+- bmask = cmp_val;
+- usleep_range(2000, 3000);
+- } else {
+- /* Put device to sleep, turn off KSO */
+- cmp_val = 0;
+- /* only check for bit0, bit1(dev on status) may not
+- * get cleared right away
+- */
+- bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
+- }
+-
+- do {
+- /* reliable KSO bit set/clr:
+- * the sdiod sleep write access is synced to PMU 32khz clk
+- * just one write attempt may fail,
+- * read it back until it matches written value
+- */
+- rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- &err);
+- if (((rd_val & bmask) == cmp_val) && !err)
+- break;
+- brcmf_dbg(SDIO, "KSO wr/rd retry:%d (max: %d) ERR:%x\n",
+- try_cnt, MAX_KSO_ATTEMPTS, err);
+- udelay(KSO_WAIT_US);
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- wr_val, &err);
+- } while (try_cnt++ < MAX_KSO_ATTEMPTS);
+-
+- return err;
+-}
+-
+-#define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
+-
+-#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
+-
+-/* Turn backplane clock on or off */
+-static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
+-{
+- int err;
+- u8 clkctl, clkreq, devctl;
+- unsigned long timeout;
+-
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- clkctl = 0;
+-
+- if (bus->sr_enabled) {
+- bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
+- return 0;
+- }
+-
+- if (on) {
+- /* Request HT Avail */
+- clkreq =
+- bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
+-
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- clkreq, &err);
+- if (err) {
+- brcmf_err("HT Avail request error: %d\n", err);
+- return -EBADE;
+- }
+-
+- /* Check current status */
+- clkctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
+- if (err) {
+- brcmf_err("HT Avail read error: %d\n", err);
+- return -EBADE;
+- }
+-
+- /* Go to pending and await interrupt if appropriate */
+- if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
+- /* Allow only clock-available interrupt */
+- devctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
+- if (err) {
+- brcmf_err("Devctl error setting CA: %d\n",
+- err);
+- return -EBADE;
+- }
+-
+- devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
+- brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
+- bus->clkstate = CLK_PENDING;
+-
+- return 0;
+- } else if (bus->clkstate == CLK_PENDING) {
+- /* Cancel CA-only interrupt filter */
+- devctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
+- devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
+- }
+-
+- /* Otherwise, wait here (polling) for HT Avail */
+- timeout = jiffies +
+- msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
+- while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
+- clkctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR,
+- &err);
+- if (time_after(jiffies, timeout))
+- break;
+- else
+- usleep_range(5000, 10000);
+- }
+- if (err) {
+- brcmf_err("HT Avail request error: %d\n", err);
+- return -EBADE;
+- }
+- if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
+- brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
+- PMU_MAX_TRANSITION_DLY, clkctl);
+- return -EBADE;
+- }
+-
+- /* Mark clock available */
+- bus->clkstate = CLK_AVAIL;
+- brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
+-
+-#if defined(DEBUG)
+- if (!bus->alp_only) {
+- if (SBSDIO_ALPONLY(clkctl))
+- brcmf_err("HT Clock should be on\n");
+- }
+-#endif /* defined (DEBUG) */
+-
+- bus->activity = true;
+- } else {
+- clkreq = 0;
+-
+- if (bus->clkstate == CLK_PENDING) {
+- /* Cancel CA-only interrupt filter */
+- devctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
+- devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
+- }
+-
+- bus->clkstate = CLK_SDONLY;
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- clkreq, &err);
+- brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
+- if (err) {
+- brcmf_err("Failed access turning clock off: %d\n",
+- err);
+- return -EBADE;
+- }
+- }
+- return 0;
+-}
+-
+-/* Change idle/active SD state */
+-static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
+-{
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- if (on)
+- bus->clkstate = CLK_SDONLY;
+- else
+- bus->clkstate = CLK_NONE;
+-
+- return 0;
+-}
+-
+-/* Transition SD and backplane clock readiness */
+-static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
+-{
+-#ifdef DEBUG
+- uint oldstate = bus->clkstate;
+-#endif /* DEBUG */
+-
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- /* Early exit if we're already there */
+- if (bus->clkstate == target) {
+- if (target == CLK_AVAIL) {
+- brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+- bus->activity = true;
+- }
+- return 0;
+- }
+-
+- switch (target) {
+- case CLK_AVAIL:
+- /* Make sure SD clock is available */
+- if (bus->clkstate == CLK_NONE)
+- brcmf_sdio_sdclk(bus, true);
+- /* Now request HT Avail on the backplane */
+- brcmf_sdio_htclk(bus, true, pendok);
+- brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+- bus->activity = true;
+- break;
+-
+- case CLK_SDONLY:
+- /* Remove HT request, or bring up SD clock */
+- if (bus->clkstate == CLK_NONE)
+- brcmf_sdio_sdclk(bus, true);
+- else if (bus->clkstate == CLK_AVAIL)
+- brcmf_sdio_htclk(bus, false, false);
+- else
+- brcmf_err("request for %d -> %d\n",
+- bus->clkstate, target);
+- brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+- break;
+-
+- case CLK_NONE:
+- /* Make sure to remove HT request */
+- if (bus->clkstate == CLK_AVAIL)
+- brcmf_sdio_htclk(bus, false, false);
+- /* Now remove the SD clock */
+- brcmf_sdio_sdclk(bus, false);
+- brcmf_sdio_wd_timer(bus, 0);
+- break;
+- }
+-#ifdef DEBUG
+- brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
+-#endif /* DEBUG */
+-
+- return 0;
+-}
+-
+-static int
+-brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
+-{
+- int err = 0;
+- brcmf_dbg(TRACE, "Enter\n");
+- brcmf_dbg(SDIO, "request %s currently %s\n",
+- (sleep ? "SLEEP" : "WAKE"),
+- (bus->sleeping ? "SLEEP" : "WAKE"));
+-
+- /* If SR is enabled control bus state with KSO */
+- if (bus->sr_enabled) {
+- /* Done if we're already in the requested state */
+- if (sleep == bus->sleeping)
+- goto end;
+-
+- /* Going to sleep */
+- if (sleep) {
+- /* Don't sleep if something is pending */
+- if (atomic_read(&bus->intstatus) ||
+- atomic_read(&bus->ipend) > 0 ||
+- (!atomic_read(&bus->fcstate) &&
+- brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
+- data_ok(bus)))
+- return -EBUSY;
+- err = brcmf_sdio_kso_control(bus, false);
+- /* disable watchdog */
+- if (!err)
+- brcmf_sdio_wd_timer(bus, 0);
+- } else {
+- bus->idlecount = 0;
+- err = brcmf_sdio_kso_control(bus, true);
+- }
+- if (!err) {
+- /* Change state */
+- bus->sleeping = sleep;
+- brcmf_dbg(SDIO, "new state %s\n",
+- (sleep ? "SLEEP" : "WAKE"));
+- } else {
+- brcmf_err("error while changing bus sleep state %d\n",
+- err);
+- return err;
+- }
+- }
+-
+-end:
+- /* control clocks */
+- if (sleep) {
+- if (!bus->sr_enabled)
+- brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
+- } else {
+- brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
+- }
+-
+- return err;
+-
+-}
+-
+-static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
+-{
+- u32 intstatus = 0;
+- u32 hmb_data;
+- u8 fcbits;
+- int ret;
+-
+- brcmf_dbg(SDIO, "Enter\n");
+-
+- /* Read mailbox data and ack that we did so */
+- ret = r_sdreg32(bus, &hmb_data,
+- offsetof(struct sdpcmd_regs, tohostmailboxdata));
+-
+- if (ret == 0)
+- w_sdreg32(bus, SMB_INT_ACK,
+- offsetof(struct sdpcmd_regs, tosbmailbox));
+- bus->sdcnt.f1regdata += 2;
+-
+- /* Dongle recomposed rx frames, accept them again */
+- if (hmb_data & HMB_DATA_NAKHANDLED) {
+- brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
+- bus->rx_seq);
+- if (!bus->rxskip)
+- brcmf_err("unexpected NAKHANDLED!\n");
+-
+- bus->rxskip = false;
+- intstatus |= I_HMB_FRAME_IND;
+- }
+-
+- /*
+- * DEVREADY does not occur with gSPI.
+- */
+- if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
+- bus->sdpcm_ver =
+- (hmb_data & HMB_DATA_VERSION_MASK) >>
+- HMB_DATA_VERSION_SHIFT;
+- if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
+- brcmf_err("Version mismatch, dongle reports %d, "
+- "expecting %d\n",
+- bus->sdpcm_ver, SDPCM_PROT_VERSION);
+- else
+- brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
+- bus->sdpcm_ver);
+- }
+-
+- /*
+- * Flow Control has been moved into the RX headers and this out of band
+- * method isn't used any more.
+- * remaining backward compatible with older dongles.
+- */
+- if (hmb_data & HMB_DATA_FC) {
+- fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
+- HMB_DATA_FCDATA_SHIFT;
+-
+- if (fcbits & ~bus->flowcontrol)
+- bus->sdcnt.fc_xoff++;
+-
+- if (bus->flowcontrol & ~fcbits)
+- bus->sdcnt.fc_xon++;
+-
+- bus->sdcnt.fc_rcvd++;
+- bus->flowcontrol = fcbits;
+- }
+-
+- /* Shouldn't be any others */
+- if (hmb_data & ~(HMB_DATA_DEVREADY |
+- HMB_DATA_NAKHANDLED |
+- HMB_DATA_FC |
+- HMB_DATA_FWREADY |
+- HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
+- brcmf_err("Unknown mailbox data content: 0x%02x\n",
+- hmb_data);
+-
+- return intstatus;
+-}
+-
+-static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
+-{
+- uint retries = 0;
+- u16 lastrbc;
+- u8 hi, lo;
+- int err;
+-
+- brcmf_err("%sterminate frame%s\n",
+- abort ? "abort command, " : "",
+- rtx ? ", send NAK" : "");
+-
+- if (abort)
+- brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
+-
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_RF_TERM, &err);
+- bus->sdcnt.f1regdata++;
+-
+- /* Wait until the packet has been flushed (device/FIFO stable) */
+- for (lastrbc = retries = 0xffff; retries > 0; retries--) {
+- hi = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_RFRAMEBCHI, &err);
+- lo = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_RFRAMEBCLO, &err);
+- bus->sdcnt.f1regdata += 2;
+-
+- if ((hi == 0) && (lo == 0))
+- break;
+-
+- if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
+- brcmf_err("count growing: last 0x%04x now 0x%04x\n",
+- lastrbc, (hi << 8) + lo);
+- }
+- lastrbc = (hi << 8) + lo;
+- }
+-
+- if (!retries)
+- brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
+- else
+- brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
+-
+- if (rtx) {
+- bus->sdcnt.rxrtx++;
+- err = w_sdreg32(bus, SMB_NAK,
+- offsetof(struct sdpcmd_regs, tosbmailbox));
+-
+- bus->sdcnt.f1regdata++;
+- if (err == 0)
+- bus->rxskip = true;
+- }
+-
+- /* Clear partial in any case */
+- bus->cur_read.len = 0;
+-}
+-
+-/* return total length of buffer chain */
+-static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
+-{
+- struct sk_buff *p;
+- uint total;
+-
+- total = 0;
+- skb_queue_walk(&bus->glom, p)
+- total += p->len;
+- return total;
+-}
+-
+-static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
+-{
+- struct sk_buff *cur, *next;
+-
+- skb_queue_walk_safe(&bus->glom, cur, next) {
+- skb_unlink(cur, &bus->glom);
+- brcmu_pkt_buf_free_skb(cur);
+- }
+-}
+-
+-/**
+- * brcmfmac sdio bus specific header
+- * This is the lowest layer header wrapped on the packets transmitted between
+- * host and WiFi dongle which contains information needed for SDIO core and
+- * firmware
+- *
+- * It consists of 3 parts: hardware header, hardware extension header and
+- * software header
+- * hardware header (frame tag) - 4 bytes
+- * Byte 0~1: Frame length
+- * Byte 2~3: Checksum, bit-wise inverse of frame length
+- * hardware extension header - 8 bytes
+- * Tx glom mode only, N/A for Rx or normal Tx
+- * Byte 0~1: Packet length excluding hw frame tag
+- * Byte 2: Reserved
+- * Byte 3: Frame flags, bit 0: last frame indication
+- * Byte 4~5: Reserved
+- * Byte 6~7: Tail padding length
+- * software header - 8 bytes
+- * Byte 0: Rx/Tx sequence number
+- * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
+- * Byte 2: Length of next data frame, reserved for Tx
+- * Byte 3: Data offset
+- * Byte 4: Flow control bits, reserved for Tx
+- * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
+- * Byte 6~7: Reserved
+- */
+-#define SDPCM_HWHDR_LEN 4
+-#define SDPCM_HWEXT_LEN 8
+-#define SDPCM_SWHDR_LEN 8
+-#define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
+-/* software header */
+-#define SDPCM_SEQ_MASK 0x000000ff
+-#define SDPCM_SEQ_WRAP 256
+-#define SDPCM_CHANNEL_MASK 0x00000f00
+-#define SDPCM_CHANNEL_SHIFT 8
+-#define SDPCM_CONTROL_CHANNEL 0 /* Control */
+-#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
+-#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
+-#define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
+-#define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
+-#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
+-#define SDPCM_NEXTLEN_MASK 0x00ff0000
+-#define SDPCM_NEXTLEN_SHIFT 16
+-#define SDPCM_DOFFSET_MASK 0xff000000
+-#define SDPCM_DOFFSET_SHIFT 24
+-#define SDPCM_FCMASK_MASK 0x000000ff
+-#define SDPCM_WINDOW_MASK 0x0000ff00
+-#define SDPCM_WINDOW_SHIFT 8
+-
+-static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
+-{
+- u32 hdrvalue;
+- hdrvalue = *(u32 *)swheader;
+- return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
+-}
+-
+-static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
+- struct brcmf_sdio_hdrinfo *rd,
+- enum brcmf_sdio_frmtype type)
+-{
+- u16 len, checksum;
+- u8 rx_seq, fc, tx_seq_max;
+- u32 swheader;
+-
+- trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
+-
+- /* hw header */
+- len = get_unaligned_le16(header);
+- checksum = get_unaligned_le16(header + sizeof(u16));
+- /* All zero means no more to read */
+- if (!(len | checksum)) {
+- bus->rxpending = false;
+- return -ENODATA;
+- }
+- if ((u16)(~(len ^ checksum))) {
+- brcmf_err("HW header checksum error\n");
+- bus->sdcnt.rx_badhdr++;
+- brcmf_sdio_rxfail(bus, false, false);
+- return -EIO;
+- }
+- if (len < SDPCM_HDRLEN) {
+- brcmf_err("HW header length error\n");
+- return -EPROTO;
+- }
+- if (type == BRCMF_SDIO_FT_SUPER &&
+- (roundup(len, bus->blocksize) != rd->len)) {
+- brcmf_err("HW superframe header length error\n");
+- return -EPROTO;
+- }
+- if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
+- brcmf_err("HW subframe header length error\n");
+- return -EPROTO;
+- }
+- rd->len = len;
+-
+- /* software header */
+- header += SDPCM_HWHDR_LEN;
+- swheader = le32_to_cpu(*(__le32 *)header);
+- if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
+- brcmf_err("Glom descriptor found in superframe head\n");
+- rd->len = 0;
+- return -EINVAL;
+- }
+- rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
+- rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
+- if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
+- type != BRCMF_SDIO_FT_SUPER) {
+- brcmf_err("HW header length too long\n");
+- bus->sdcnt.rx_toolong++;
+- brcmf_sdio_rxfail(bus, false, false);
+- rd->len = 0;
+- return -EPROTO;
+- }
+- if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
+- brcmf_err("Wrong channel for superframe\n");
+- rd->len = 0;
+- return -EINVAL;
+- }
+- if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
+- rd->channel != SDPCM_EVENT_CHANNEL) {
+- brcmf_err("Wrong channel for subframe\n");
+- rd->len = 0;
+- return -EINVAL;
+- }
+- rd->dat_offset = brcmf_sdio_getdatoffset(header);
+- if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
+- brcmf_err("seq %d: bad data offset\n", rx_seq);
+- bus->sdcnt.rx_badhdr++;
+- brcmf_sdio_rxfail(bus, false, false);
+- rd->len = 0;
+- return -ENXIO;
+- }
+- if (rd->seq_num != rx_seq) {
+- brcmf_err("seq %d: sequence number error, expect %d\n",
+- rx_seq, rd->seq_num);
+- bus->sdcnt.rx_badseq++;
+- rd->seq_num = rx_seq;
+- }
+- /* no need to check the reset for subframe */
+- if (type == BRCMF_SDIO_FT_SUB)
+- return 0;
+- rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
+- if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
+- /* only warm for NON glom packet */
+- if (rd->channel != SDPCM_GLOM_CHANNEL)
+- brcmf_err("seq %d: next length error\n", rx_seq);
+- rd->len_nxtfrm = 0;
+- }
+- swheader = le32_to_cpu(*(__le32 *)(header + 4));
+- fc = swheader & SDPCM_FCMASK_MASK;
+- if (bus->flowcontrol != fc) {
+- if (~bus->flowcontrol & fc)
+- bus->sdcnt.fc_xoff++;
+- if (bus->flowcontrol & ~fc)
+- bus->sdcnt.fc_xon++;
+- bus->sdcnt.fc_rcvd++;
+- bus->flowcontrol = fc;
+- }
+- tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
+- if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
+- brcmf_err("seq %d: max tx seq number error\n", rx_seq);
+- tx_seq_max = bus->tx_seq + 2;
+- }
+- bus->tx_max = tx_seq_max;
+-
+- return 0;
+-}
+-
+-static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
+-{
+- *(__le16 *)header = cpu_to_le16(frm_length);
+- *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
+-}
+-
+-static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
+- struct brcmf_sdio_hdrinfo *hd_info)
+-{
+- u32 hdrval;
+- u8 hdr_offset;
+-
+- brcmf_sdio_update_hwhdr(header, hd_info->len);
+- hdr_offset = SDPCM_HWHDR_LEN;
+-
+- if (bus->txglom) {
+- hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
+- *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
+- hdrval = (u16)hd_info->tail_pad << 16;
+- *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
+- hdr_offset += SDPCM_HWEXT_LEN;
+- }
+-
+- hdrval = hd_info->seq_num;
+- hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
+- SDPCM_CHANNEL_MASK;
+- hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
+- SDPCM_DOFFSET_MASK;
+- *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
+- *(((__le32 *)(header + hdr_offset)) + 1) = 0;
+- trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
+-}
+-
+-static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
+-{
+- u16 dlen, totlen;
+- u8 *dptr, num = 0;
+- u16 sublen;
+- struct sk_buff *pfirst, *pnext;
+-
+- int errcode;
+- u8 doff, sfdoff;
+-
+- struct brcmf_sdio_hdrinfo rd_new;
+-
+- /* If packets, issue read(s) and send up packet chain */
+- /* Return sequence numbers consumed? */
+-
+- brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
+- bus->glomd, skb_peek(&bus->glom));
+-
+- /* If there's a descriptor, generate the packet chain */
+- if (bus->glomd) {
+- pfirst = pnext = NULL;
+- dlen = (u16) (bus->glomd->len);
+- dptr = bus->glomd->data;
+- if (!dlen || (dlen & 1)) {
+- brcmf_err("bad glomd len(%d), ignore descriptor\n",
+- dlen);
+- dlen = 0;
+- }
+-
+- for (totlen = num = 0; dlen; num++) {
+- /* Get (and move past) next length */
+- sublen = get_unaligned_le16(dptr);
+- dlen -= sizeof(u16);
+- dptr += sizeof(u16);
+- if ((sublen < SDPCM_HDRLEN) ||
+- ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
+- brcmf_err("descriptor len %d bad: %d\n",
+- num, sublen);
+- pnext = NULL;
+- break;
+- }
+- if (sublen % bus->sgentry_align) {
+- brcmf_err("sublen %d not multiple of %d\n",
+- sublen, bus->sgentry_align);
+- }
+- totlen += sublen;
+-
+- /* For last frame, adjust read len so total
+- is a block multiple */
+- if (!dlen) {
+- sublen +=
+- (roundup(totlen, bus->blocksize) - totlen);
+- totlen = roundup(totlen, bus->blocksize);
+- }
+-
+- /* Allocate/chain packet for next subframe */
+- pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
+- if (pnext == NULL) {
+- brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
+- num, sublen);
+- break;
+- }
+- skb_queue_tail(&bus->glom, pnext);
+-
+- /* Adhere to start alignment requirements */
+- pkt_align(pnext, sublen, bus->sgentry_align);
+- }
+-
+- /* If all allocations succeeded, save packet chain
+- in bus structure */
+- if (pnext) {
+- brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
+- totlen, num);
+- if (BRCMF_GLOM_ON() && bus->cur_read.len &&
+- totlen != bus->cur_read.len) {
+- brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
+- bus->cur_read.len, totlen, rxseq);
+- }
+- pfirst = pnext = NULL;
+- } else {
+- brcmf_sdio_free_glom(bus);
+- num = 0;
+- }
+-
+- /* Done with descriptor packet */
+- brcmu_pkt_buf_free_skb(bus->glomd);
+- bus->glomd = NULL;
+- bus->cur_read.len = 0;
+- }
+-
+- /* Ok -- either we just generated a packet chain,
+- or had one from before */
+- if (!skb_queue_empty(&bus->glom)) {
+- if (BRCMF_GLOM_ON()) {
+- brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
+- skb_queue_walk(&bus->glom, pnext) {
+- brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
+- pnext, (u8 *) (pnext->data),
+- pnext->len, pnext->len);
+- }
+- }
+-
+- pfirst = skb_peek(&bus->glom);
+- dlen = (u16) brcmf_sdio_glom_len(bus);
+-
+- /* Do an SDIO read for the superframe. Configurable iovar to
+- * read directly into the chained packet, or allocate a large
+- * packet and and copy into the chain.
+- */
+- sdio_claim_host(bus->sdiodev->func[1]);
+- errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
+- &bus->glom, dlen);
+- sdio_release_host(bus->sdiodev->func[1]);
+- bus->sdcnt.f2rxdata++;
+-
+- /* On failure, kill the superframe, allow a couple retries */
+- if (errcode < 0) {
+- brcmf_err("glom read of %d bytes failed: %d\n",
+- dlen, errcode);
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+- if (bus->glomerr++ < 3) {
+- brcmf_sdio_rxfail(bus, true, true);
+- } else {
+- bus->glomerr = 0;
+- brcmf_sdio_rxfail(bus, true, false);
+- bus->sdcnt.rxglomfail++;
+- brcmf_sdio_free_glom(bus);
+- }
+- sdio_release_host(bus->sdiodev->func[1]);
+- return 0;
+- }
+-
+- brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
+- pfirst->data, min_t(int, pfirst->len, 48),
+- "SUPERFRAME:\n");
+-
+- rd_new.seq_num = rxseq;
+- rd_new.len = dlen;
+- sdio_claim_host(bus->sdiodev->func[1]);
+- errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
+- BRCMF_SDIO_FT_SUPER);
+- sdio_release_host(bus->sdiodev->func[1]);
+- bus->cur_read.len = rd_new.len_nxtfrm << 4;
+-
+- /* Remove superframe header, remember offset */
+- skb_pull(pfirst, rd_new.dat_offset);
+- sfdoff = rd_new.dat_offset;
+- num = 0;
+-
+- /* Validate all the subframe headers */
+- skb_queue_walk(&bus->glom, pnext) {
+- /* leave when invalid subframe is found */
+- if (errcode)
+- break;
+-
+- rd_new.len = pnext->len;
+- rd_new.seq_num = rxseq++;
+- sdio_claim_host(bus->sdiodev->func[1]);
+- errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
+- BRCMF_SDIO_FT_SUB);
+- sdio_release_host(bus->sdiodev->func[1]);
+- brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
+- pnext->data, 32, "subframe:\n");
+-
+- num++;
+- }
+-
+- if (errcode) {
+- /* Terminate frame on error, request
+- a couple retries */
+- sdio_claim_host(bus->sdiodev->func[1]);
+- if (bus->glomerr++ < 3) {
+- /* Restore superframe header space */
+- skb_push(pfirst, sfdoff);
+- brcmf_sdio_rxfail(bus, true, true);
+- } else {
+- bus->glomerr = 0;
+- brcmf_sdio_rxfail(bus, true, false);
+- bus->sdcnt.rxglomfail++;
+- brcmf_sdio_free_glom(bus);
+- }
+- sdio_release_host(bus->sdiodev->func[1]);
+- bus->cur_read.len = 0;
+- return 0;
+- }
+-
+- /* Basic SD framing looks ok - process each packet (header) */
+-
+- skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
+- dptr = (u8 *) (pfirst->data);
+- sublen = get_unaligned_le16(dptr);
+- doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
+-
+- brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
+- dptr, pfirst->len,
+- "Rx Subframe Data:\n");
+-
+- __skb_trim(pfirst, sublen);
+- skb_pull(pfirst, doff);
+-
+- if (pfirst->len == 0) {
+- skb_unlink(pfirst, &bus->glom);
+- brcmu_pkt_buf_free_skb(pfirst);
+- continue;
+- }
+-
+- brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
+- pfirst->data,
+- min_t(int, pfirst->len, 32),
+- "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
+- bus->glom.qlen, pfirst, pfirst->data,
+- pfirst->len, pfirst->next,
+- pfirst->prev);
+- skb_unlink(pfirst, &bus->glom);
+- brcmf_rx_frame(bus->sdiodev->dev, pfirst);
+- bus->sdcnt.rxglompkts++;
+- }
+-
+- bus->sdcnt.rxglomframes++;
+- }
+- return num;
+-}
+-
+-static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
+- bool *pending)
+-{
+- DECLARE_WAITQUEUE(wait, current);
+- int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
+-
+- /* Wait until control frame is available */
+- add_wait_queue(&bus->dcmd_resp_wait, &wait);
+- set_current_state(TASK_INTERRUPTIBLE);
+-
+- while (!(*condition) && (!signal_pending(current) && timeout))
+- timeout = schedule_timeout(timeout);
+-
+- if (signal_pending(current))
+- *pending = true;
+-
+- set_current_state(TASK_RUNNING);
+- remove_wait_queue(&bus->dcmd_resp_wait, &wait);
+-
+- return timeout;
+-}
+-
+-static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
+-{
+- if (waitqueue_active(&bus->dcmd_resp_wait))
+- wake_up_interruptible(&bus->dcmd_resp_wait);
+-
+- return 0;
+-}
+-static void
+-brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
+-{
+- uint rdlen, pad;
+- u8 *buf = NULL, *rbuf;
+- int sdret;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (bus->rxblen)
+- buf = vzalloc(bus->rxblen);
+- if (!buf)
+- goto done;
+-
+- rbuf = bus->rxbuf;
+- pad = ((unsigned long)rbuf % bus->head_align);
+- if (pad)
+- rbuf += (bus->head_align - pad);
+-
+- /* Copy the already-read portion over */
+- memcpy(buf, hdr, BRCMF_FIRSTREAD);
+- if (len <= BRCMF_FIRSTREAD)
+- goto gotpkt;
+-
+- /* Raise rdlen to next SDIO block to avoid tail command */
+- rdlen = len - BRCMF_FIRSTREAD;
+- if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
+- pad = bus->blocksize - (rdlen % bus->blocksize);
+- if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
+- ((len + pad) < bus->sdiodev->bus_if->maxctl))
+- rdlen += pad;
+- } else if (rdlen % bus->head_align) {
+- rdlen += bus->head_align - (rdlen % bus->head_align);
+- }
+-
+- /* Drop if the read is too big or it exceeds our maximum */
+- if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
+- brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
+- rdlen, bus->sdiodev->bus_if->maxctl);
+- brcmf_sdio_rxfail(bus, false, false);
+- goto done;
+- }
+-
+- if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
+- brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
+- len, len - doff, bus->sdiodev->bus_if->maxctl);
+- bus->sdcnt.rx_toolong++;
+- brcmf_sdio_rxfail(bus, false, false);
+- goto done;
+- }
+-
+- /* Read remain of frame body */
+- sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
+- bus->sdcnt.f2rxdata++;
+-
+- /* Control frame failures need retransmission */
+- if (sdret < 0) {
+- brcmf_err("read %d control bytes failed: %d\n",
+- rdlen, sdret);
+- bus->sdcnt.rxc_errors++;
+- brcmf_sdio_rxfail(bus, true, true);
+- goto done;
+- } else
+- memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
+-
+-gotpkt:
+-
+- brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
+- buf, len, "RxCtrl:\n");
+-
+- /* Point to valid data and indicate its length */
+- spin_lock_bh(&bus->rxctl_lock);
+- if (bus->rxctl) {
+- brcmf_err("last control frame is being processed.\n");
+- spin_unlock_bh(&bus->rxctl_lock);
+- vfree(buf);
+- goto done;
+- }
+- bus->rxctl = buf + doff;
+- bus->rxctl_orig = buf;
+- bus->rxlen = len - doff;
+- spin_unlock_bh(&bus->rxctl_lock);
+-
+-done:
+- /* Awake any waiters */
+- brcmf_sdio_dcmd_resp_wake(bus);
+-}
+-
+-/* Pad read to blocksize for efficiency */
+-static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
+-{
+- if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
+- *pad = bus->blocksize - (*rdlen % bus->blocksize);
+- if (*pad <= bus->roundup && *pad < bus->blocksize &&
+- *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
+- *rdlen += *pad;
+- } else if (*rdlen % bus->head_align) {
+- *rdlen += bus->head_align - (*rdlen % bus->head_align);
+- }
+-}
+-
+-static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
+-{
+- struct sk_buff *pkt; /* Packet for event or data frames */
+- u16 pad; /* Number of pad bytes to read */
+- uint rxleft = 0; /* Remaining number of frames allowed */
+- int ret; /* Return code from calls */
+- uint rxcount = 0; /* Total frames read */
+- struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
+- u8 head_read = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* Not finished unless we encounter no more frames indication */
+- bus->rxpending = true;
+-
+- for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
+- !bus->rxskip && rxleft && brcmf_bus_ready(bus->sdiodev->bus_if);
+- rd->seq_num++, rxleft--) {
+-
+- /* Handle glomming separately */
+- if (bus->glomd || !skb_queue_empty(&bus->glom)) {
+- u8 cnt;
+- brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
+- bus->glomd, skb_peek(&bus->glom));
+- cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
+- brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
+- rd->seq_num += cnt - 1;
+- rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
+- continue;
+- }
+-
+- rd->len_left = rd->len;
+- /* read header first for unknow frame length */
+- sdio_claim_host(bus->sdiodev->func[1]);
+- if (!rd->len) {
+- ret = brcmf_sdiod_recv_buf(bus->sdiodev,
+- bus->rxhdr, BRCMF_FIRSTREAD);
+- bus->sdcnt.f2rxhdrs++;
+- if (ret < 0) {
+- brcmf_err("RXHEADER FAILED: %d\n",
+- ret);
+- bus->sdcnt.rx_hdrfail++;
+- brcmf_sdio_rxfail(bus, true, true);
+- sdio_release_host(bus->sdiodev->func[1]);
+- continue;
+- }
+-
+- brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
+- bus->rxhdr, SDPCM_HDRLEN,
+- "RxHdr:\n");
+-
+- if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
+- BRCMF_SDIO_FT_NORMAL)) {
+- sdio_release_host(bus->sdiodev->func[1]);
+- if (!bus->rxpending)
+- break;
+- else
+- continue;
+- }
+-
+- if (rd->channel == SDPCM_CONTROL_CHANNEL) {
+- brcmf_sdio_read_control(bus, bus->rxhdr,
+- rd->len,
+- rd->dat_offset);
+- /* prepare the descriptor for the next read */
+- rd->len = rd->len_nxtfrm << 4;
+- rd->len_nxtfrm = 0;
+- /* treat all packet as event if we don't know */
+- rd->channel = SDPCM_EVENT_CHANNEL;
+- sdio_release_host(bus->sdiodev->func[1]);
+- continue;
+- }
+- rd->len_left = rd->len > BRCMF_FIRSTREAD ?
+- rd->len - BRCMF_FIRSTREAD : 0;
+- head_read = BRCMF_FIRSTREAD;
+- }
+-
+- brcmf_sdio_pad(bus, &pad, &rd->len_left);
+-
+- pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
+- bus->head_align);
+- if (!pkt) {
+- /* Give up on data, request rtx of events */
+- brcmf_err("brcmu_pkt_buf_get_skb failed\n");
+- brcmf_sdio_rxfail(bus, false,
+- RETRYCHAN(rd->channel));
+- sdio_release_host(bus->sdiodev->func[1]);
+- continue;
+- }
+- skb_pull(pkt, head_read);
+- pkt_align(pkt, rd->len_left, bus->head_align);
+-
+- ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
+- bus->sdcnt.f2rxdata++;
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- if (ret < 0) {
+- brcmf_err("read %d bytes from channel %d failed: %d\n",
+- rd->len, rd->channel, ret);
+- brcmu_pkt_buf_free_skb(pkt);
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_rxfail(bus, true,
+- RETRYCHAN(rd->channel));
+- sdio_release_host(bus->sdiodev->func[1]);
+- continue;
+- }
+-
+- if (head_read) {
+- skb_push(pkt, head_read);
+- memcpy(pkt->data, bus->rxhdr, head_read);
+- head_read = 0;
+- } else {
+- memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
+- rd_new.seq_num = rd->seq_num;
+- sdio_claim_host(bus->sdiodev->func[1]);
+- if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
+- BRCMF_SDIO_FT_NORMAL)) {
+- rd->len = 0;
+- brcmu_pkt_buf_free_skb(pkt);
+- }
+- bus->sdcnt.rx_readahead_cnt++;
+- if (rd->len != roundup(rd_new.len, 16)) {
+- brcmf_err("frame length mismatch:read %d, should be %d\n",
+- rd->len,
+- roundup(rd_new.len, 16) >> 4);
+- rd->len = 0;
+- brcmf_sdio_rxfail(bus, true, true);
+- sdio_release_host(bus->sdiodev->func[1]);
+- brcmu_pkt_buf_free_skb(pkt);
+- continue;
+- }
+- sdio_release_host(bus->sdiodev->func[1]);
+- rd->len_nxtfrm = rd_new.len_nxtfrm;
+- rd->channel = rd_new.channel;
+- rd->dat_offset = rd_new.dat_offset;
+-
+- brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
+- BRCMF_DATA_ON()) &&
+- BRCMF_HDRS_ON(),
+- bus->rxhdr, SDPCM_HDRLEN,
+- "RxHdr:\n");
+-
+- if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
+- brcmf_err("readahead on control packet %d?\n",
+- rd_new.seq_num);
+- /* Force retry w/normal header read */
+- rd->len = 0;
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_rxfail(bus, false, true);
+- sdio_release_host(bus->sdiodev->func[1]);
+- brcmu_pkt_buf_free_skb(pkt);
+- continue;
+- }
+- }
+-
+- brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
+- pkt->data, rd->len, "Rx Data:\n");
+-
+- /* Save superframe descriptor and allocate packet frame */
+- if (rd->channel == SDPCM_GLOM_CHANNEL) {
+- if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
+- brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
+- rd->len);
+- brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
+- pkt->data, rd->len,
+- "Glom Data:\n");
+- __skb_trim(pkt, rd->len);
+- skb_pull(pkt, SDPCM_HDRLEN);
+- bus->glomd = pkt;
+- } else {
+- brcmf_err("%s: glom superframe w/o "
+- "descriptor!\n", __func__);
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_rxfail(bus, false, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+- }
+- /* prepare the descriptor for the next read */
+- rd->len = rd->len_nxtfrm << 4;
+- rd->len_nxtfrm = 0;
+- /* treat all packet as event if we don't know */
+- rd->channel = SDPCM_EVENT_CHANNEL;
+- continue;
+- }
+-
+- /* Fill in packet len and prio, deliver upward */
+- __skb_trim(pkt, rd->len);
+- skb_pull(pkt, rd->dat_offset);
+-
+- /* prepare the descriptor for the next read */
+- rd->len = rd->len_nxtfrm << 4;
+- rd->len_nxtfrm = 0;
+- /* treat all packet as event if we don't know */
+- rd->channel = SDPCM_EVENT_CHANNEL;
+-
+- if (pkt->len == 0) {
+- brcmu_pkt_buf_free_skb(pkt);
+- continue;
+- }
+-
+- brcmf_rx_frame(bus->sdiodev->dev, pkt);
+- }
+-
+- rxcount = maxframes - rxleft;
+- /* Message if we hit the limit */
+- if (!rxleft)
+- brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
+- else
+- brcmf_dbg(DATA, "processed %d frames\n", rxcount);
+- /* Back off rxseq if awaiting rtx, update rx_seq */
+- if (bus->rxskip)
+- rd->seq_num--;
+- bus->rx_seq = rd->seq_num;
+-
+- return rxcount;
+-}
+-
+-static void
+-brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
+-{
+- if (waitqueue_active(&bus->ctrl_wait))
+- wake_up_interruptible(&bus->ctrl_wait);
+- return;
+-}
+-
+-static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
+-{
+- u16 head_pad;
+- u8 *dat_buf;
+-
+- dat_buf = (u8 *)(pkt->data);
+-
+- /* Check head padding */
+- head_pad = ((unsigned long)dat_buf % bus->head_align);
+- if (head_pad) {
+- if (skb_headroom(pkt) < head_pad) {
+- bus->sdiodev->bus_if->tx_realloc++;
+- head_pad = 0;
+- if (skb_cow(pkt, head_pad))
+- return -ENOMEM;
+- }
+- skb_push(pkt, head_pad);
+- dat_buf = (u8 *)(pkt->data);
+- memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
+- }
+- return head_pad;
+-}
+-
+-/**
+- * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
+- * bus layer usage.
+- */
+-/* flag marking a dummy skb added for DMA alignment requirement */
+-#define ALIGN_SKB_FLAG 0x8000
+-/* bit mask of data length chopped from the previous packet */
+-#define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
+-
+-static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
+- struct sk_buff_head *pktq,
+- struct sk_buff *pkt, u16 total_len)
+-{
+- struct brcmf_sdio_dev *sdiodev;
+- struct sk_buff *pkt_pad;
+- u16 tail_pad, tail_chop, chain_pad;
+- unsigned int blksize;
+- bool lastfrm;
+- int ntail, ret;
+-
+- sdiodev = bus->sdiodev;
+- blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
+- /* sg entry alignment should be a divisor of block size */
+- WARN_ON(blksize % bus->sgentry_align);
+-
+- /* Check tail padding */
+- lastfrm = skb_queue_is_last(pktq, pkt);
+- tail_pad = 0;
+- tail_chop = pkt->len % bus->sgentry_align;
+- if (tail_chop)
+- tail_pad = bus->sgentry_align - tail_chop;
+- chain_pad = (total_len + tail_pad) % blksize;
+- if (lastfrm && chain_pad)
+- tail_pad += blksize - chain_pad;
+- if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
+- pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
+- bus->head_align);
+- if (pkt_pad == NULL)
+- return -ENOMEM;
+- ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
+- if (unlikely(ret < 0)) {
+- kfree_skb(pkt_pad);
+- return ret;
+- }
+- memcpy(pkt_pad->data,
+- pkt->data + pkt->len - tail_chop,
+- tail_chop);
+- *(u32 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
+- skb_trim(pkt, pkt->len - tail_chop);
+- skb_trim(pkt_pad, tail_pad + tail_chop);
+- __skb_queue_after(pktq, pkt, pkt_pad);
+- } else {
+- ntail = pkt->data_len + tail_pad -
+- (pkt->end - pkt->tail);
+- if (skb_cloned(pkt) || ntail > 0)
+- if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
+- return -ENOMEM;
+- if (skb_linearize(pkt))
+- return -ENOMEM;
+- __skb_put(pkt, tail_pad);
+- }
+-
+- return tail_pad;
+-}
+-
+-/**
+- * brcmf_sdio_txpkt_prep - packet preparation for transmit
+- * @bus: brcmf_sdio structure pointer
+- * @pktq: packet list pointer
+- * @chan: virtual channel to transmit the packet
+- *
+- * Processes to be applied to the packet
+- * - Align data buffer pointer
+- * - Align data buffer length
+- * - Prepare header
+- * Return: negative value if there is error
+- */
+-static int
+-brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
+- uint chan)
+-{
+- u16 head_pad, total_len;
+- struct sk_buff *pkt_next;
+- u8 txseq;
+- int ret;
+- struct brcmf_sdio_hdrinfo hd_info = {0};
+-
+- txseq = bus->tx_seq;
+- total_len = 0;
+- skb_queue_walk(pktq, pkt_next) {
+- /* alignment packet inserted in previous
+- * loop cycle can be skipped as it is
+- * already properly aligned and does not
+- * need an sdpcm header.
+- */
+- if (*(u32 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
+- continue;
+-
+- /* align packet data pointer */
+- ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
+- if (ret < 0)
+- return ret;
+- head_pad = (u16)ret;
+- if (head_pad)
+- memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
+-
+- total_len += pkt_next->len;
+-
+- hd_info.len = pkt_next->len;
+- hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
+- if (bus->txglom && pktq->qlen > 1) {
+- ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
+- pkt_next, total_len);
+- if (ret < 0)
+- return ret;
+- hd_info.tail_pad = (u16)ret;
+- total_len += (u16)ret;
+- }
+-
+- hd_info.channel = chan;
+- hd_info.dat_offset = head_pad + bus->tx_hdrlen;
+- hd_info.seq_num = txseq++;
+-
+- /* Now fill the header */
+- brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
+-
+- if (BRCMF_BYTES_ON() &&
+- ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
+- (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
+- brcmf_dbg_hex_dump(true, pkt_next, hd_info.len,
+- "Tx Frame:\n");
+- else if (BRCMF_HDRS_ON())
+- brcmf_dbg_hex_dump(true, pkt_next,
+- head_pad + bus->tx_hdrlen,
+- "Tx Header:\n");
+- }
+- /* Hardware length tag of the first packet should be total
+- * length of the chain (including padding)
+- */
+- if (bus->txglom)
+- brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
+- return 0;
+-}
+-
+-/**
+- * brcmf_sdio_txpkt_postp - packet post processing for transmit
+- * @bus: brcmf_sdio structure pointer
+- * @pktq: packet list pointer
+- *
+- * Processes to be applied to the packet
+- * - Remove head padding
+- * - Remove tail padding
+- */
+-static void
+-brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
+-{
+- u8 *hdr;
+- u32 dat_offset;
+- u16 tail_pad;
+- u32 dummy_flags, chop_len;
+- struct sk_buff *pkt_next, *tmp, *pkt_prev;
+-
+- skb_queue_walk_safe(pktq, pkt_next, tmp) {
+- dummy_flags = *(u32 *)(pkt_next->cb);
+- if (dummy_flags & ALIGN_SKB_FLAG) {
+- chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
+- if (chop_len) {
+- pkt_prev = pkt_next->prev;
+- skb_put(pkt_prev, chop_len);
+- }
+- __skb_unlink(pkt_next, pktq);
+- brcmu_pkt_buf_free_skb(pkt_next);
+- } else {
+- hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
+- dat_offset = le32_to_cpu(*(__le32 *)hdr);
+- dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
+- SDPCM_DOFFSET_SHIFT;
+- skb_pull(pkt_next, dat_offset);
+- if (bus->txglom) {
+- tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
+- skb_trim(pkt_next, pkt_next->len - tail_pad);
+- }
+- }
+- }
+-}
+-
+-/* Writes a HW/SW header into the packet and sends it. */
+-/* Assumes: (a) header space already there, (b) caller holds lock */
+-static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
+- uint chan)
+-{
+- int ret;
+- int i;
+- struct sk_buff *pkt_next, *tmp;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
+- if (ret)
+- goto done;
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+- ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
+- bus->sdcnt.f2txdata++;
+-
+- if (ret < 0) {
+- /* On failure, abort the command and terminate the frame */
+- brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
+- ret);
+- bus->sdcnt.tx_sderrs++;
+-
+- brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_WF_TERM, NULL);
+- bus->sdcnt.f1regdata++;
+-
+- for (i = 0; i < 3; i++) {
+- u8 hi, lo;
+- hi = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCHI, NULL);
+- lo = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCLO, NULL);
+- bus->sdcnt.f1regdata += 2;
+- if ((hi == 0) && (lo == 0))
+- break;
+- }
+- }
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+-done:
+- brcmf_sdio_txpkt_postp(bus, pktq);
+- if (ret == 0)
+- bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
+- skb_queue_walk_safe(pktq, pkt_next, tmp) {
+- __skb_unlink(pkt_next, pktq);
+- brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
+- }
+- return ret;
+-}
+-
+-static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
+-{
+- struct sk_buff *pkt;
+- struct sk_buff_head pktq;
+- u32 intstatus = 0;
+- int ret = 0, prec_out, i;
+- uint cnt = 0;
+- u8 tx_prec_map, pkt_num;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- tx_prec_map = ~bus->flowcontrol;
+-
+- /* Send frames until the limit or some other event */
+- for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
+- pkt_num = 1;
+- __skb_queue_head_init(&pktq);
+- if (bus->txglom)
+- pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
+- brcmf_sdio_txglomsz);
+- pkt_num = min_t(u32, pkt_num,
+- brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
+- spin_lock_bh(&bus->txqlock);
+- for (i = 0; i < pkt_num; i++) {
+- pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
+- &prec_out);
+- if (pkt == NULL)
+- break;
+- __skb_queue_tail(&pktq, pkt);
+- }
+- spin_unlock_bh(&bus->txqlock);
+- if (i == 0)
+- break;
+-
+- ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
+- cnt += i;
+-
+- /* In poll mode, need to check for other events */
+- if (!bus->intr && cnt) {
+- /* Check device status, signal pending interrupt */
+- sdio_claim_host(bus->sdiodev->func[1]);
+- ret = r_sdreg32(bus, &intstatus,
+- offsetof(struct sdpcmd_regs,
+- intstatus));
+- sdio_release_host(bus->sdiodev->func[1]);
+- bus->sdcnt.f2txdata++;
+- if (ret != 0)
+- break;
+- if (intstatus & bus->hostintmask)
+- atomic_set(&bus->ipend, 1);
+- }
+- }
+-
+- /* Deflow-control stack if needed */
+- if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) &&
+- bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
+- bus->txoff = false;
+- brcmf_txflowblock(bus->sdiodev->dev, false);
+- }
+-
+- return cnt;
+-}
+-
+-static void brcmf_sdio_bus_stop(struct device *dev)
+-{
+- u32 local_hostintmask;
+- u8 saveclk;
+- int err;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- struct brcmf_sdio *bus = sdiodev->bus;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (bus->watchdog_tsk) {
+- send_sig(SIGTERM, bus->watchdog_tsk, 1);
+- kthread_stop(bus->watchdog_tsk);
+- bus->watchdog_tsk = NULL;
+- }
+-
+- if (bus_if->state == BRCMF_BUS_DOWN) {
+- sdio_claim_host(sdiodev->func[1]);
+-
+- /* Enable clock for device interrupts */
+- brcmf_sdio_bus_sleep(bus, false, false);
+-
+- /* Disable and clear interrupts at the chip level also */
+- w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
+- local_hostintmask = bus->hostintmask;
+- bus->hostintmask = 0;
+-
+- /* Force backplane clocks to assure F2 interrupt propagates */
+- saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- &err);
+- if (!err)
+- brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- (saveclk | SBSDIO_FORCE_HT), &err);
+- if (err)
+- brcmf_err("Failed to force clock for F2: err %d\n",
+- err);
+-
+- /* Turn off the bus (F2), free any pending packets */
+- brcmf_dbg(INTR, "disable SDIO interrupts\n");
+- sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
+-
+- /* Clear any pending interrupts now that F2 is disabled */
+- w_sdreg32(bus, local_hostintmask,
+- offsetof(struct sdpcmd_regs, intstatus));
+-
+- sdio_release_host(sdiodev->func[1]);
+- }
+- /* Clear the data packet queues */
+- brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
+-
+- /* Clear any held glomming stuff */
+- if (bus->glomd)
+- brcmu_pkt_buf_free_skb(bus->glomd);
+- brcmf_sdio_free_glom(bus);
+-
+- /* Clear rx control and wake any waiters */
+- spin_lock_bh(&bus->rxctl_lock);
+- bus->rxlen = 0;
+- spin_unlock_bh(&bus->rxctl_lock);
+- brcmf_sdio_dcmd_resp_wake(bus);
+-
+- /* Reset some F2 state stuff */
+- bus->rxskip = false;
+- bus->tx_seq = bus->rx_seq = 0;
+-}
+-
+-static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
+-{
+- unsigned long flags;
+-
+- if (bus->sdiodev->oob_irq_requested) {
+- spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
+- if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
+- enable_irq(bus->sdiodev->pdata->oob_irq_nr);
+- bus->sdiodev->irq_en = true;
+- }
+- spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
+- }
+-}
+-
+-static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
+-{
+- u8 idx;
+- u32 addr;
+- unsigned long val;
+- int n, ret;
+-
+- idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
+- addr = bus->ci->c_inf[idx].base +
+- offsetof(struct sdpcmd_regs, intstatus);
+-
+- val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
+- bus->sdcnt.f1regdata++;
+- if (ret != 0)
+- val = 0;
+-
+- val &= bus->hostintmask;
+- atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
+-
+- /* Clear interrupts */
+- if (val) {
+- brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
+- bus->sdcnt.f1regdata++;
+- }
+-
+- if (ret) {
+- atomic_set(&bus->intstatus, 0);
+- } else if (val) {
+- for_each_set_bit(n, &val, 32)
+- set_bit(n, (unsigned long *)&bus->intstatus.counter);
+- }
+-
+- return ret;
+-}
+-
+-static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
+-{
+- u32 newstatus = 0;
+- unsigned long intstatus;
+- uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
+- uint txlimit = bus->txbound; /* Tx frames to send before resched */
+- uint framecnt = 0; /* Temporary counter of tx/rx frames */
+- int err = 0, n;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+-
+- /* If waiting for HTAVAIL, check status */
+- if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
+- u8 clkctl, devctl = 0;
+-
+-#ifdef DEBUG
+- /* Check for inconsistent device control */
+- devctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
+-#endif /* DEBUG */
+-
+- /* Read CSR, if clock on switch to AVAIL, else ignore */
+- clkctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
+-
+- brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
+- devctl, clkctl);
+-
+- if (SBSDIO_HTAV(clkctl)) {
+- devctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_DEVICE_CTL, &err);
+- devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
+- devctl, &err);
+- bus->clkstate = CLK_AVAIL;
+- }
+- }
+-
+- /* Make sure backplane clock is on */
+- brcmf_sdio_bus_sleep(bus, false, true);
+-
+- /* Pending interrupt indicates new device status */
+- if (atomic_read(&bus->ipend) > 0) {
+- atomic_set(&bus->ipend, 0);
+- err = brcmf_sdio_intr_rstatus(bus);
+- }
+-
+- /* Start with leftover status bits */
+- intstatus = atomic_xchg(&bus->intstatus, 0);
+-
+- /* Handle flow-control change: read new state in case our ack
+- * crossed another change interrupt. If change still set, assume
+- * FC ON for safety, let next loop through do the debounce.
+- */
+- if (intstatus & I_HMB_FC_CHANGE) {
+- intstatus &= ~I_HMB_FC_CHANGE;
+- err = w_sdreg32(bus, I_HMB_FC_CHANGE,
+- offsetof(struct sdpcmd_regs, intstatus));
+-
+- err = r_sdreg32(bus, &newstatus,
+- offsetof(struct sdpcmd_regs, intstatus));
+- bus->sdcnt.f1regdata += 2;
+- atomic_set(&bus->fcstate,
+- !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
+- intstatus |= (newstatus & bus->hostintmask);
+- }
+-
+- /* Handle host mailbox indication */
+- if (intstatus & I_HMB_HOST_INT) {
+- intstatus &= ~I_HMB_HOST_INT;
+- intstatus |= brcmf_sdio_hostmail(bus);
+- }
+-
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- /* Generally don't ask for these, can get CRC errors... */
+- if (intstatus & I_WR_OOSYNC) {
+- brcmf_err("Dongle reports WR_OOSYNC\n");
+- intstatus &= ~I_WR_OOSYNC;
+- }
+-
+- if (intstatus & I_RD_OOSYNC) {
+- brcmf_err("Dongle reports RD_OOSYNC\n");
+- intstatus &= ~I_RD_OOSYNC;
+- }
+-
+- if (intstatus & I_SBINT) {
+- brcmf_err("Dongle reports SBINT\n");
+- intstatus &= ~I_SBINT;
+- }
+-
+- /* Would be active due to wake-wlan in gSPI */
+- if (intstatus & I_CHIPACTIVE) {
+- brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
+- intstatus &= ~I_CHIPACTIVE;
+- }
+-
+- /* Ignore frame indications if rxskip is set */
+- if (bus->rxskip)
+- intstatus &= ~I_HMB_FRAME_IND;
+-
+- /* On frame indication, read available frames */
+- if (PKT_AVAILABLE() && bus->clkstate == CLK_AVAIL) {
+- framecnt = brcmf_sdio_readframes(bus, rxlimit);
+- if (!bus->rxpending)
+- intstatus &= ~I_HMB_FRAME_IND;
+- rxlimit -= min(framecnt, rxlimit);
+- }
+-
+- /* Keep still-pending events for next scheduling */
+- if (intstatus) {
+- for_each_set_bit(n, &intstatus, 32)
+- set_bit(n, (unsigned long *)&bus->intstatus.counter);
+- }
+-
+- brcmf_sdio_clrintr(bus);
+-
+- if (data_ok(bus) && bus->ctrl_frame_stat &&
+- (bus->clkstate == CLK_AVAIL)) {
+- int i;
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+- err = brcmf_sdiod_send_buf(bus->sdiodev, bus->ctrl_frame_buf,
+- (u32)bus->ctrl_frame_len);
+-
+- if (err < 0) {
+- /* On failure, abort the command and
+- terminate the frame */
+- brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
+- err);
+- bus->sdcnt.tx_sderrs++;
+-
+- brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
+-
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_WF_TERM, &err);
+- bus->sdcnt.f1regdata++;
+-
+- for (i = 0; i < 3; i++) {
+- u8 hi, lo;
+- hi = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCHI,
+- &err);
+- lo = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCLO,
+- &err);
+- bus->sdcnt.f1regdata += 2;
+- if ((hi == 0) && (lo == 0))
+- break;
+- }
+-
+- } else {
+- bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
+- }
+- sdio_release_host(bus->sdiodev->func[1]);
+- bus->ctrl_frame_stat = false;
+- brcmf_sdio_wait_event_wakeup(bus);
+- }
+- /* Send queued frames (limit 1 if rx may still be pending) */
+- else if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
+- brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
+- && data_ok(bus)) {
+- framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
+- txlimit;
+- framecnt = brcmf_sdio_sendfromq(bus, framecnt);
+- txlimit -= framecnt;
+- }
+-
+- if (!brcmf_bus_ready(bus->sdiodev->bus_if) || (err != 0)) {
+- brcmf_err("failed backplane access over SDIO, halting operation\n");
+- atomic_set(&bus->intstatus, 0);
+- } else if (atomic_read(&bus->intstatus) ||
+- atomic_read(&bus->ipend) > 0 ||
+- (!atomic_read(&bus->fcstate) &&
+- brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
+- data_ok(bus)) || PKT_AVAILABLE()) {
+- atomic_inc(&bus->dpc_tskcnt);
+- }
+-
+- /* If we're done for now, turn off clock request. */
+- if ((bus->clkstate != CLK_PENDING)
+- && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
+- bus->activity = false;
+- brcmf_dbg(SDIO, "idle state\n");
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_bus_sleep(bus, true, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+- }
+-}
+-
+-static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- struct brcmf_sdio *bus = sdiodev->bus;
+-
+- return &bus->txq;
+-}
+-
+-static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
+-{
+- int ret = -EBADE;
+- uint datalen, prec;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- struct brcmf_sdio *bus = sdiodev->bus;
+- ulong flags;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- datalen = pkt->len;
+-
+- /* Add space for the header */
+- skb_push(pkt, bus->tx_hdrlen);
+- /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
+-
+- prec = prio2prec((pkt->priority & PRIOMASK));
+-
+- /* Check for existing queue, current flow-control,
+- pending event, or pending clock */
+- brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
+- bus->sdcnt.fcqueued++;
+-
+- /* Priority based enq */
+- spin_lock_irqsave(&bus->txqlock, flags);
+- if (!brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec)) {
+- skb_pull(pkt, bus->tx_hdrlen);
+- brcmf_err("out of bus->txq !!!\n");
+- ret = -ENOSR;
+- } else {
+- ret = 0;
+- }
+-
+- if (pktq_len(&bus->txq) >= TXHI) {
+- bus->txoff = true;
+- brcmf_txflowblock(bus->sdiodev->dev, true);
+- }
+- spin_unlock_irqrestore(&bus->txqlock, flags);
+-
+-#ifdef DEBUG
+- if (pktq_plen(&bus->txq, prec) > qcount[prec])
+- qcount[prec] = pktq_plen(&bus->txq, prec);
+-#endif
+-
+- if (atomic_read(&bus->dpc_tskcnt) == 0) {
+- atomic_inc(&bus->dpc_tskcnt);
+- queue_work(bus->brcmf_wq, &bus->datawork);
+- }
+-
+- return ret;
+-}
+-
+-#ifdef DEBUG
+-#define CONSOLE_LINE_MAX 192
+-
+-static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
+-{
+- struct brcmf_console *c = &bus->console;
+- u8 line[CONSOLE_LINE_MAX], ch;
+- u32 n, idx, addr;
+- int rv;
+-
+- /* Don't do anything until FWREADY updates console address */
+- if (bus->console_addr == 0)
+- return 0;
+-
+- /* Read console log struct */
+- addr = bus->console_addr + offsetof(struct rte_console, log_le);
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
+- sizeof(c->log_le));
+- if (rv < 0)
+- return rv;
+-
+- /* Allocate console buffer (one time only) */
+- if (c->buf == NULL) {
+- c->bufsize = le32_to_cpu(c->log_le.buf_size);
+- c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
+- if (c->buf == NULL)
+- return -ENOMEM;
+- }
+-
+- idx = le32_to_cpu(c->log_le.idx);
+-
+- /* Protect against corrupt value */
+- if (idx > c->bufsize)
+- return -EBADE;
+-
+- /* Skip reading the console buffer if the index pointer
+- has not moved */
+- if (idx == c->last)
+- return 0;
+-
+- /* Read the console buffer */
+- addr = le32_to_cpu(c->log_le.buf);
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
+- if (rv < 0)
+- return rv;
+-
+- while (c->last != idx) {
+- for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
+- if (c->last == idx) {
+- /* This would output a partial line.
+- * Instead, back up
+- * the buffer pointer and output this
+- * line next time around.
+- */
+- if (c->last >= n)
+- c->last -= n;
+- else
+- c->last = c->bufsize - n;
+- goto break2;
+- }
+- ch = c->buf[c->last];
+- c->last = (c->last + 1) % c->bufsize;
+- if (ch == '\n')
+- break;
+- line[n] = ch;
+- }
+-
+- if (n > 0) {
+- if (line[n - 1] == '\r')
+- n--;
+- line[n] = 0;
+- pr_debug("CONSOLE: %s\n", line);
+- }
+- }
+-break2:
+-
+- return 0;
+-}
+-#endif /* DEBUG */
+-
+-static int brcmf_sdio_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
+-{
+- int i;
+- int ret;
+-
+- bus->ctrl_frame_stat = false;
+- ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
+-
+- if (ret < 0) {
+- /* On failure, abort the command and terminate the frame */
+- brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
+- ret);
+- bus->sdcnt.tx_sderrs++;
+-
+- brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
+-
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
+- SFC_WF_TERM, NULL);
+- bus->sdcnt.f1regdata++;
+-
+- for (i = 0; i < 3; i++) {
+- u8 hi, lo;
+- hi = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCHI, NULL);
+- lo = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_WFRAMEBCLO, NULL);
+- bus->sdcnt.f1regdata += 2;
+- if (hi == 0 && lo == 0)
+- break;
+- }
+- return ret;
+- }
+-
+- bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
+-
+- return ret;
+-}
+-
+-static int
+-brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
+-{
+- u8 *frame;
+- u16 len, pad;
+- uint retries = 0;
+- u8 doff = 0;
+- int ret = -1;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- struct brcmf_sdio *bus = sdiodev->bus;
+- struct brcmf_sdio_hdrinfo hd_info = {0};
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* Back the pointer to make a room for bus header */
+- frame = msg - bus->tx_hdrlen;
+- len = (msglen += bus->tx_hdrlen);
+-
+- /* Add alignment padding (optional for ctl frames) */
+- doff = ((unsigned long)frame % bus->head_align);
+- if (doff) {
+- frame -= doff;
+- len += doff;
+- msglen += doff;
+- memset(frame, 0, doff + bus->tx_hdrlen);
+- }
+- /* precondition: doff < bus->head_align */
+- doff += bus->tx_hdrlen;
+-
+- /* Round send length to next SDIO block */
+- pad = 0;
+- if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
+- pad = bus->blocksize - (len % bus->blocksize);
+- if ((pad > bus->roundup) || (pad >= bus->blocksize))
+- pad = 0;
+- } else if (len % bus->head_align) {
+- pad = bus->head_align - (len % bus->head_align);
+- }
+- len += pad;
+-
+- /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
+-
+- /* Make sure backplane clock is on */
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_bus_sleep(bus, false, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- hd_info.len = (u16)msglen;
+- hd_info.channel = SDPCM_CONTROL_CHANNEL;
+- hd_info.dat_offset = doff;
+- hd_info.seq_num = bus->tx_seq;
+- hd_info.lastfrm = true;
+- hd_info.tail_pad = pad;
+- brcmf_sdio_hdpack(bus, frame, &hd_info);
+-
+- if (bus->txglom)
+- brcmf_sdio_update_hwhdr(frame, len);
+-
+- if (!data_ok(bus)) {
+- brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
+- bus->tx_max, bus->tx_seq);
+- bus->ctrl_frame_stat = true;
+- /* Send from dpc */
+- bus->ctrl_frame_buf = frame;
+- bus->ctrl_frame_len = len;
+-
+- wait_event_interruptible_timeout(bus->ctrl_wait,
+- !bus->ctrl_frame_stat,
+- msecs_to_jiffies(2000));
+-
+- if (!bus->ctrl_frame_stat) {
+- brcmf_dbg(SDIO, "ctrl_frame_stat == false\n");
+- ret = 0;
+- } else {
+- brcmf_dbg(SDIO, "ctrl_frame_stat == true\n");
+- ret = -1;
+- }
+- }
+-
+- if (ret == -1) {
+- brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
+- frame, len, "Tx Frame:\n");
+- brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
+- BRCMF_HDRS_ON(),
+- frame, min_t(u16, len, 16), "TxHdr:\n");
+-
+- do {
+- sdio_claim_host(bus->sdiodev->func[1]);
+- ret = brcmf_sdio_tx_frame(bus, frame, len);
+- sdio_release_host(bus->sdiodev->func[1]);
+- } while (ret < 0 && retries++ < TXRETRIES);
+- }
+-
+- if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) &&
+- atomic_read(&bus->dpc_tskcnt) == 0) {
+- bus->activity = false;
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_dbg(INFO, "idle\n");
+- brcmf_sdio_clkctl(bus, CLK_NONE, true);
+- sdio_release_host(bus->sdiodev->func[1]);
+- }
+-
+- if (ret)
+- bus->sdcnt.tx_ctlerrs++;
+- else
+- bus->sdcnt.tx_ctlpkts++;
+-
+- return ret ? -EIO : 0;
+-}
+-
+-#ifdef DEBUG
+-static inline bool brcmf_sdio_valid_shared_address(u32 addr)
+-{
+- return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
+-}
+-
+-static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
+- struct sdpcm_shared *sh)
+-{
+- u32 addr;
+- int rv;
+- u32 shaddr = 0;
+- struct sdpcm_shared_le sh_le;
+- __le32 addr_le;
+-
+- shaddr = bus->ci->rambase + bus->ramsize - 4;
+-
+- /*
+- * Read last word in socram to determine
+- * address of sdpcm_shared structure
+- */
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_bus_sleep(bus, false, false);
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, (u8 *)&addr_le, 4);
+- sdio_release_host(bus->sdiodev->func[1]);
+- if (rv < 0)
+- return rv;
+-
+- addr = le32_to_cpu(addr_le);
+-
+- brcmf_dbg(SDIO, "sdpcm_shared address 0x%08X\n", addr);
+-
+- /*
+- * Check if addr is valid.
+- * NVRAM length at the end of memory should have been overwritten.
+- */
+- if (!brcmf_sdio_valid_shared_address(addr)) {
+- brcmf_err("invalid sdpcm_shared address 0x%08X\n",
+- addr);
+- return -EINVAL;
+- }
+-
+- /* Read hndrte_shared structure */
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
+- sizeof(struct sdpcm_shared_le));
+- if (rv < 0)
+- return rv;
+-
+- /* Endianness */
+- sh->flags = le32_to_cpu(sh_le.flags);
+- sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
+- sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
+- sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
+- sh->assert_line = le32_to_cpu(sh_le.assert_line);
+- sh->console_addr = le32_to_cpu(sh_le.console_addr);
+- sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
+-
+- if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
+- brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
+- SDPCM_SHARED_VERSION,
+- sh->flags & SDPCM_SHARED_VERSION_MASK);
+- return -EPROTO;
+- }
+-
+- return 0;
+-}
+-
+-static int brcmf_sdio_dump_console(struct brcmf_sdio *bus,
+- struct sdpcm_shared *sh, char __user *data,
+- size_t count)
+-{
+- u32 addr, console_ptr, console_size, console_index;
+- char *conbuf = NULL;
+- __le32 sh_val;
+- int rv;
+- loff_t pos = 0;
+- int nbytes = 0;
+-
+- /* obtain console information from device memory */
+- addr = sh->console_addr + offsetof(struct rte_console, log_le);
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
+- (u8 *)&sh_val, sizeof(u32));
+- if (rv < 0)
+- return rv;
+- console_ptr = le32_to_cpu(sh_val);
+-
+- addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
+- (u8 *)&sh_val, sizeof(u32));
+- if (rv < 0)
+- return rv;
+- console_size = le32_to_cpu(sh_val);
+-
+- addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
+- (u8 *)&sh_val, sizeof(u32));
+- if (rv < 0)
+- return rv;
+- console_index = le32_to_cpu(sh_val);
+-
+- /* allocate buffer for console data */
+- if (console_size <= CONSOLE_BUFFER_MAX)
+- conbuf = vzalloc(console_size+1);
+-
+- if (!conbuf)
+- return -ENOMEM;
+-
+- /* obtain the console data from device */
+- conbuf[console_size] = '\0';
+- rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
+- console_size);
+- if (rv < 0)
+- goto done;
+-
+- rv = simple_read_from_buffer(data, count, &pos,
+- conbuf + console_index,
+- console_size - console_index);
+- if (rv < 0)
+- goto done;
+-
+- nbytes = rv;
+- if (console_index > 0) {
+- pos = 0;
+- rv = simple_read_from_buffer(data+nbytes, count, &pos,
+- conbuf, console_index - 1);
+- if (rv < 0)
+- goto done;
+- rv += nbytes;
+- }
+-done:
+- vfree(conbuf);
+- return rv;
+-}
+-
+-static int brcmf_sdio_trap_info(struct brcmf_sdio *bus, struct sdpcm_shared *sh,
+- char __user *data, size_t count)
+-{
+- int error, res;
+- char buf[350];
+- struct brcmf_trap_info tr;
+- loff_t pos = 0;
+-
+- if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
+- brcmf_dbg(INFO, "no trap in firmware\n");
+- return 0;
+- }
+-
+- error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
+- sizeof(struct brcmf_trap_info));
+- if (error < 0)
+- return error;
+-
+- res = scnprintf(buf, sizeof(buf),
+- "dongle trap info: type 0x%x @ epc 0x%08x\n"
+- " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
+- " lr 0x%08x pc 0x%08x offset 0x%x\n"
+- " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
+- " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
+- le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
+- le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
+- le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
+- le32_to_cpu(tr.pc), sh->trap_addr,
+- le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
+- le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
+- le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
+- le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
+-
+- return simple_read_from_buffer(data, count, &pos, buf, res);
+-}
+-
+-static int brcmf_sdio_assert_info(struct brcmf_sdio *bus,
+- struct sdpcm_shared *sh, char __user *data,
+- size_t count)
+-{
+- int error = 0;
+- char buf[200];
+- char file[80] = "?";
+- char expr[80] = "<???>";
+- int res;
+- loff_t pos = 0;
+-
+- if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
+- brcmf_dbg(INFO, "firmware not built with -assert\n");
+- return 0;
+- } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
+- brcmf_dbg(INFO, "no assert in dongle\n");
+- return 0;
+- }
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+- if (sh->assert_file_addr != 0) {
+- error = brcmf_sdiod_ramrw(bus->sdiodev, false,
+- sh->assert_file_addr, (u8 *)file, 80);
+- if (error < 0)
+- return error;
+- }
+- if (sh->assert_exp_addr != 0) {
+- error = brcmf_sdiod_ramrw(bus->sdiodev, false,
+- sh->assert_exp_addr, (u8 *)expr, 80);
+- if (error < 0)
+- return error;
+- }
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- res = scnprintf(buf, sizeof(buf),
+- "dongle assert: %s:%d: assert(%s)\n",
+- file, sh->assert_line, expr);
+- return simple_read_from_buffer(data, count, &pos, buf, res);
+-}
+-
+-static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
+-{
+- int error;
+- struct sdpcm_shared sh;
+-
+- error = brcmf_sdio_readshared(bus, &sh);
+-
+- if (error < 0)
+- return error;
+-
+- if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
+- brcmf_dbg(INFO, "firmware not built with -assert\n");
+- else if (sh.flags & SDPCM_SHARED_ASSERT)
+- brcmf_err("assertion in dongle\n");
+-
+- if (sh.flags & SDPCM_SHARED_TRAP)
+- brcmf_err("firmware trap in dongle\n");
+-
+- return 0;
+-}
+-
+-static int brcmf_sdio_died_dump(struct brcmf_sdio *bus, char __user *data,
+- size_t count, loff_t *ppos)
+-{
+- int error = 0;
+- struct sdpcm_shared sh;
+- int nbytes = 0;
+- loff_t pos = *ppos;
+-
+- if (pos != 0)
+- return 0;
+-
+- error = brcmf_sdio_readshared(bus, &sh);
+- if (error < 0)
+- goto done;
+-
+- error = brcmf_sdio_assert_info(bus, &sh, data, count);
+- if (error < 0)
+- goto done;
+- nbytes = error;
+-
+- error = brcmf_sdio_trap_info(bus, &sh, data+nbytes, count);
+- if (error < 0)
+- goto done;
+- nbytes += error;
+-
+- error = brcmf_sdio_dump_console(bus, &sh, data+nbytes, count);
+- if (error < 0)
+- goto done;
+- nbytes += error;
+-
+- error = nbytes;
+- *ppos += nbytes;
+-done:
+- return error;
+-}
+-
+-static ssize_t brcmf_sdio_forensic_read(struct file *f, char __user *data,
+- size_t count, loff_t *ppos)
+-{
+- struct brcmf_sdio *bus = f->private_data;
+- int res;
+-
+- res = brcmf_sdio_died_dump(bus, data, count, ppos);
+- if (res > 0)
+- *ppos += res;
+- return (ssize_t)res;
+-}
+-
+-static const struct file_operations brcmf_sdio_forensic_ops = {
+- .owner = THIS_MODULE,
+- .open = simple_open,
+- .read = brcmf_sdio_forensic_read
+-};
+-
+-static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
+-{
+- struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
+- struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
+-
+- if (IS_ERR_OR_NULL(dentry))
+- return;
+-
+- debugfs_create_file("forensics", S_IRUGO, dentry, bus,
+- &brcmf_sdio_forensic_ops);
+- brcmf_debugfs_create_sdio_count(drvr, &bus->sdcnt);
+-}
+-#else
+-static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
+-{
+- return 0;
+-}
+-
+-static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
+-{
+-}
+-#endif /* DEBUG */
+-
+-static int
+-brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
+-{
+- int timeleft;
+- uint rxlen = 0;
+- bool pending;
+- u8 *buf;
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- struct brcmf_sdio *bus = sdiodev->bus;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* Wait until control frame is available */
+- timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
+-
+- spin_lock_bh(&bus->rxctl_lock);
+- rxlen = bus->rxlen;
+- memcpy(msg, bus->rxctl, min(msglen, rxlen));
+- bus->rxctl = NULL;
+- buf = bus->rxctl_orig;
+- bus->rxctl_orig = NULL;
+- bus->rxlen = 0;
+- spin_unlock_bh(&bus->rxctl_lock);
+- vfree(buf);
+-
+- if (rxlen) {
+- brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
+- rxlen, msglen);
+- } else if (timeleft == 0) {
+- brcmf_err("resumed on timeout\n");
+- brcmf_sdio_checkdied(bus);
+- } else if (pending) {
+- brcmf_dbg(CTL, "cancelled\n");
+- return -ERESTARTSYS;
+- } else {
+- brcmf_dbg(CTL, "resumed for unknown reason?\n");
+- brcmf_sdio_checkdied(bus);
+- }
+-
+- if (rxlen)
+- bus->sdcnt.rx_ctlpkts++;
+- else
+- bus->sdcnt.rx_ctlerrs++;
+-
+- return rxlen ? (int)rxlen : -ETIMEDOUT;
+-}
+-
+-#ifdef DEBUG
+-static bool
+-brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
+- u8 *ram_data, uint ram_sz)
+-{
+- char *ram_cmp;
+- int err;
+- bool ret = true;
+- int address;
+- int offset;
+- int len;
+-
+- /* read back and verify */
+- brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
+- ram_sz);
+- ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
+- /* do not proceed while no memory but */
+- if (!ram_cmp)
+- return true;
+-
+- address = ram_addr;
+- offset = 0;
+- while (offset < ram_sz) {
+- len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
+- ram_sz - offset;
+- err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
+- if (err) {
+- brcmf_err("error %d on reading %d membytes at 0x%08x\n",
+- err, len, address);
+- ret = false;
+- break;
+- } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
+- brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
+- offset, len);
+- ret = false;
+- break;
+- }
+- offset += len;
+- address += len;
+- }
+-
+- kfree(ram_cmp);
+-
+- return ret;
+-}
+-#else /* DEBUG */
+-static bool
+-brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
+- u8 *ram_data, uint ram_sz)
+-{
+- return true;
+-}
+-#endif /* DEBUG */
+-
+-static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
+- const struct firmware *fw)
+-{
+- int err;
+- int offset;
+- int address;
+- int len;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- err = 0;
+- offset = 0;
+- address = bus->ci->rambase;
+- while (offset < fw->size) {
+- len = ((offset + MEMBLOCK) < fw->size) ? MEMBLOCK :
+- fw->size - offset;
+- err = brcmf_sdiod_ramrw(bus->sdiodev, true, address,
+- (u8 *)&fw->data[offset], len);
+- if (err) {
+- brcmf_err("error %d on writing %d membytes at 0x%08x\n",
+- err, len, address);
+- return err;
+- }
+- offset += len;
+- address += len;
+- }
+- if (!err)
+- if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
+- (u8 *)fw->data, fw->size))
+- err = -EIO;
+-
+- return err;
+-}
+-
+-static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
+- const struct firmware *nv)
+-{
+- void *vars;
+- u32 varsz;
+- int address;
+- int err;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- vars = brcmf_nvram_strip(nv, &varsz);
+-
+- if (vars == NULL)
+- return -EINVAL;
+-
+- address = bus->ci->ramsize - varsz + bus->ci->rambase;
+- err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
+- if (err)
+- brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
+- err, varsz, address);
+- else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
+- err = -EIO;
+-
+- brcmf_nvram_free(vars);
+-
+- return err;
+-}
+-
+-static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus)
+-{
+- int bcmerror = -EFAULT;
+- const struct firmware *fw;
+- u32 rstvec;
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
+-
+- /* Keep arm in reset */
+- brcmf_sdio_chip_enter_download(bus->sdiodev, bus->ci);
+-
+- fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_BIN);
+- if (fw == NULL) {
+- bcmerror = -ENOENT;
+- goto err;
+- }
+-
+- rstvec = get_unaligned_le32(fw->data);
+- brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
+-
+- bcmerror = brcmf_sdio_download_code_file(bus, fw);
+- release_firmware(fw);
+- if (bcmerror) {
+- brcmf_err("dongle image file download failed\n");
+- goto err;
+- }
+-
+- fw = brcmf_sdio_get_fw(bus, BRCMF_FIRMWARE_NVRAM);
+- if (fw == NULL) {
+- bcmerror = -ENOENT;
+- goto err;
+- }
+-
+- bcmerror = brcmf_sdio_download_nvram(bus, fw);
+- release_firmware(fw);
+- if (bcmerror) {
+- brcmf_err("dongle nvram file download failed\n");
+- goto err;
+- }
+-
+- /* Take arm out of reset */
+- if (!brcmf_sdio_chip_exit_download(bus->sdiodev, bus->ci, rstvec)) {
+- brcmf_err("error getting out of ARM core reset\n");
+- goto err;
+- }
+-
+- /* Allow HT Clock now that the ARM is running. */
+- brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_LOAD);
+- bcmerror = 0;
+-
+-err:
+- brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+- return bcmerror;
+-}
+-
+-static bool brcmf_sdio_sr_capable(struct brcmf_sdio *bus)
+-{
+- u32 addr, reg, pmu_cc3_mask = ~0;
+- int err;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* old chips with PMU version less than 17 don't support save restore */
+- if (bus->ci->pmurev < 17)
+- return false;
+-
+- switch (bus->ci->chip) {
+- case BCM43241_CHIP_ID:
+- case BCM4335_CHIP_ID:
+- case BCM4339_CHIP_ID:
+- /* read PMU chipcontrol register 3 */
+- addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_addr);
+- brcmf_sdiod_regwl(bus->sdiodev, addr, 3, NULL);
+- addr = CORE_CC_REG(bus->ci->c_inf[0].base, chipcontrol_data);
+- reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
+- return (reg & pmu_cc3_mask) != 0;
+- default:
+- addr = CORE_CC_REG(bus->ci->c_inf[0].base, pmucapabilities_ext);
+- reg = brcmf_sdiod_regrl(bus->sdiodev, addr, &err);
+- if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0)
+- return false;
+-
+- addr = CORE_CC_REG(bus->ci->c_inf[0].base, retention_ctl);
+- reg = brcmf_sdiod_regrl(bus->sdiodev, addr, NULL);
+- return (reg & (PMU_RCTL_MACPHY_DISABLE_MASK |
+- PMU_RCTL_LOGIC_DISABLE_MASK)) == 0;
+- }
+-}
+-
+-static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
+-{
+- int err = 0;
+- u8 val;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
+- if (err) {
+- brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
+- return;
+- }
+-
+- val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
+- if (err) {
+- brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
+- return;
+- }
+-
+- /* Add CMD14 Support */
+- brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
+- (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
+- SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
+- &err);
+- if (err) {
+- brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
+- return;
+- }
+-
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- SBSDIO_FORCE_HT, &err);
+- if (err) {
+- brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
+- return;
+- }
+-
+- /* set flag */
+- bus->sr_enabled = true;
+- brcmf_dbg(INFO, "SR enabled\n");
+-}
+-
+-/* enable KSO bit */
+-static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
+-{
+- u8 val;
+- int err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* KSO bit added in SDIO core rev 12 */
+- if (bus->ci->c_inf[1].rev < 12)
+- return 0;
+-
+- val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
+- if (err) {
+- brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
+- return err;
+- }
+-
+- if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
+- val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
+- SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
+- val, &err);
+- if (err) {
+- brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
+- return err;
+- }
+- }
+-
+- return 0;
+-}
+-
+-
+-static int brcmf_sdio_bus_preinit(struct device *dev)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- struct brcmf_sdio *bus = sdiodev->bus;
+- uint pad_size;
+- u32 value;
+- u8 idx;
+- int err;
+-
+- /* the commands below use the terms tx and rx from
+- * a device perspective, ie. bus:txglom affects the
+- * bus transfers from device to host.
+- */
+- idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
+- if (bus->ci->c_inf[idx].rev < 12) {
+- /* for sdio core rev < 12, disable txgloming */
+- value = 0;
+- err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
+- sizeof(u32));
+- } else {
+- /* otherwise, set txglomalign */
+- value = 4;
+- if (sdiodev->pdata)
+- value = sdiodev->pdata->sd_sgentry_align;
+- /* SDIO ADMA requires at least 32 bit alignment */
+- value = max_t(u32, value, 4);
+- err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
+- sizeof(u32));
+- }
+-
+- if (err < 0)
+- goto done;
+-
+- bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
+- if (sdiodev->sg_support) {
+- bus->txglom = false;
+- value = 1;
+- pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
+- err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
+- &value, sizeof(u32));
+- if (err < 0) {
+- /* bus:rxglom is allowed to fail */
+- err = 0;
+- } else {
+- bus->txglom = true;
+- bus->tx_hdrlen += SDPCM_HWEXT_LEN;
+- }
+- }
+- brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
+-
+-done:
+- return err;
+-}
+-
+-static int brcmf_sdio_bus_init(struct device *dev)
+-{
+- struct brcmf_bus *bus_if = dev_get_drvdata(dev);
+- struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
+- struct brcmf_sdio *bus = sdiodev->bus;
+- int err, ret = 0;
+- u8 saveclk;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* try to download image and nvram to the dongle */
+- if (bus_if->state == BRCMF_BUS_DOWN) {
+- bus->alp_only = true;
+- err = brcmf_sdio_download_firmware(bus);
+- if (err)
+- return err;
+- bus->alp_only = false;
+- }
+-
+- if (!bus->sdiodev->bus_if->drvr)
+- return 0;
+-
+- /* Start the watchdog timer */
+- bus->sdcnt.tickcnt = 0;
+- brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+-
+- /* Make sure backplane clock is on, needed to generate F2 interrupt */
+- brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
+- if (bus->clkstate != CLK_AVAIL)
+- goto exit;
+-
+- /* Force clocks on backplane to be sure F2 interrupt propagates */
+- saveclk = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
+- if (!err) {
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- (saveclk | SBSDIO_FORCE_HT), &err);
+- }
+- if (err) {
+- brcmf_err("Failed to force clock for F2: err %d\n", err);
+- goto exit;
+- }
+-
+- /* Enable function 2 (frame transfers) */
+- w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
+- offsetof(struct sdpcmd_regs, tosbmailboxdata));
+- err = sdio_enable_func(bus->sdiodev->func[SDIO_FUNC_2]);
+-
+-
+- brcmf_dbg(INFO, "enable F2: err=%d\n", err);
+-
+- /* If F2 successfully enabled, set core and enable interrupts */
+- if (!err) {
+- /* Set up the interrupt mask and enable interrupts */
+- bus->hostintmask = HOSTINTMASK;
+- w_sdreg32(bus, bus->hostintmask,
+- offsetof(struct sdpcmd_regs, hostintmask));
+-
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_WATERMARK, 8, &err);
+- } else {
+- /* Disable F2 again */
+- sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
+- ret = -ENODEV;
+- }
+-
+- if (brcmf_sdio_sr_capable(bus)) {
+- brcmf_sdio_sr_init(bus);
+- } else {
+- /* Restore previous clock setting */
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- saveclk, &err);
+- }
+-
+- if (ret == 0) {
+- ret = brcmf_sdiod_intr_register(bus->sdiodev);
+- if (ret != 0)
+- brcmf_err("intr register failed:%d\n", ret);
+- }
+-
+- /* If we didn't come up, turn off backplane clock */
+- if (ret != 0)
+- brcmf_sdio_clkctl(bus, CLK_NONE, false);
+-
+-exit:
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- return ret;
+-}
+-
+-void brcmf_sdio_isr(struct brcmf_sdio *bus)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (!bus) {
+- brcmf_err("bus is null pointer, exiting\n");
+- return;
+- }
+-
+- if (!brcmf_bus_ready(bus->sdiodev->bus_if)) {
+- brcmf_err("bus is down. we have nothing to do\n");
+- return;
+- }
+- /* Count the interrupt call */
+- bus->sdcnt.intrcount++;
+- if (in_interrupt())
+- atomic_set(&bus->ipend, 1);
+- else
+- if (brcmf_sdio_intr_rstatus(bus)) {
+- brcmf_err("failed backplane access\n");
+- }
+-
+- /* Disable additional interrupts (is this needed now)? */
+- if (!bus->intr)
+- brcmf_err("isr w/o interrupt configured!\n");
+-
+- atomic_inc(&bus->dpc_tskcnt);
+- queue_work(bus->brcmf_wq, &bus->datawork);
+-}
+-
+-static bool brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
+-{
+-#ifdef DEBUG
+- struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
+-#endif /* DEBUG */
+-
+- brcmf_dbg(TIMER, "Enter\n");
+-
+- /* Poll period: check device if appropriate. */
+- if (!bus->sr_enabled &&
+- bus->poll && (++bus->polltick >= bus->pollrate)) {
+- u32 intstatus = 0;
+-
+- /* Reset poll tick */
+- bus->polltick = 0;
+-
+- /* Check device if no interrupts */
+- if (!bus->intr ||
+- (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
+-
+- if (atomic_read(&bus->dpc_tskcnt) == 0) {
+- u8 devpend;
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+- devpend = brcmf_sdiod_regrb(bus->sdiodev,
+- SDIO_CCCR_INTx,
+- NULL);
+- sdio_release_host(bus->sdiodev->func[1]);
+- intstatus =
+- devpend & (INTR_STATUS_FUNC1 |
+- INTR_STATUS_FUNC2);
+- }
+-
+- /* If there is something, make like the ISR and
+- schedule the DPC */
+- if (intstatus) {
+- bus->sdcnt.pollcnt++;
+- atomic_set(&bus->ipend, 1);
+-
+- atomic_inc(&bus->dpc_tskcnt);
+- queue_work(bus->brcmf_wq, &bus->datawork);
+- }
+- }
+-
+- /* Update interrupt tracking */
+- bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
+- }
+-#ifdef DEBUG
+- /* Poll for console output periodically */
+- if (bus_if && bus_if->state == BRCMF_BUS_DATA &&
+- bus->console_interval != 0) {
+- bus->console.count += BRCMF_WD_POLL_MS;
+- if (bus->console.count >= bus->console_interval) {
+- bus->console.count -= bus->console_interval;
+- sdio_claim_host(bus->sdiodev->func[1]);
+- /* Make sure backplane clock is on */
+- brcmf_sdio_bus_sleep(bus, false, false);
+- if (brcmf_sdio_readconsole(bus) < 0)
+- /* stop on error */
+- bus->console_interval = 0;
+- sdio_release_host(bus->sdiodev->func[1]);
+- }
+- }
+-#endif /* DEBUG */
+-
+- /* On idle timeout clear activity flag and/or turn off clock */
+- if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
+- if (++bus->idlecount >= bus->idletime) {
+- bus->idlecount = 0;
+- if (bus->activity) {
+- bus->activity = false;
+- brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
+- } else {
+- brcmf_dbg(SDIO, "idle\n");
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_bus_sleep(bus, true, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+- }
+- }
+- }
+-
+- return (atomic_read(&bus->ipend) > 0);
+-}
+-
+-static void brcmf_sdio_dataworker(struct work_struct *work)
+-{
+- struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
+- datawork);
+-
+- while (atomic_read(&bus->dpc_tskcnt)) {
+- brcmf_sdio_dpc(bus);
+- atomic_dec(&bus->dpc_tskcnt);
+- }
+-}
+-
+-static bool
+-brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
+-{
+- u8 clkctl = 0;
+- int err = 0;
+- int reg_addr;
+- u32 reg_val;
+- u32 drivestrength;
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+-
+- pr_debug("F1 signature read @0x18000000=0x%4x\n",
+- brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
+-
+- /*
+- * Force PLL off until brcmf_sdio_chip_attach()
+- * programs PLL control regs
+- */
+-
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
+- BRCMF_INIT_CLKCTL1, &err);
+- if (!err)
+- clkctl = brcmf_sdiod_regrb(bus->sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, &err);
+-
+- if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
+- brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
+- err, BRCMF_INIT_CLKCTL1, clkctl);
+- goto fail;
+- }
+-
+- /* SDIO register access works so moving
+- * state from UNKNOWN to DOWN.
+- */
+- brcmf_bus_change_state(bus->sdiodev->bus_if, BRCMF_BUS_DOWN);
+-
+- if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci)) {
+- brcmf_err("brcmf_sdio_chip_attach failed!\n");
+- goto fail;
+- }
+-
+- if (brcmf_sdio_kso_init(bus)) {
+- brcmf_err("error enabling KSO\n");
+- goto fail;
+- }
+-
+- if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
+- drivestrength = bus->sdiodev->pdata->drive_strength;
+- else
+- drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
+- brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
+-
+- /* Get info on the SOCRAM cores... */
+- bus->ramsize = bus->ci->ramsize;
+- if (!(bus->ramsize)) {
+- brcmf_err("failed to find SOCRAM memory!\n");
+- goto fail;
+- }
+-
+- /* Set card control so an SDIO card reset does a WLAN backplane reset */
+- reg_val = brcmf_sdiod_regrb(bus->sdiodev,
+- SDIO_CCCR_BRCM_CARDCTRL, &err);
+- if (err)
+- goto fail;
+-
+- reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
+-
+- brcmf_sdiod_regwb(bus->sdiodev,
+- SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
+- if (err)
+- goto fail;
+-
+- /* set PMUControl so a backplane reset does PMU state reload */
+- reg_addr = CORE_CC_REG(bus->ci->c_inf[0].base,
+- pmucontrol);
+- reg_val = brcmf_sdiod_regrl(bus->sdiodev,
+- reg_addr,
+- &err);
+- if (err)
+- goto fail;
+-
+- reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
+-
+- brcmf_sdiod_regwl(bus->sdiodev,
+- reg_addr,
+- reg_val,
+- &err);
+- if (err)
+- goto fail;
+-
+-
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
+-
+- /* allocate header buffer */
+- bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
+- if (!bus->hdrbuf)
+- return false;
+- /* Locate an appropriately-aligned portion of hdrbuf */
+- bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
+- bus->head_align);
+-
+- /* Set the poll and/or interrupt flags */
+- bus->intr = true;
+- bus->poll = false;
+- if (bus->poll)
+- bus->pollrate = 1;
+-
+- return true;
+-
+-fail:
+- sdio_release_host(bus->sdiodev->func[1]);
+- return false;
+-}
+-
+-static int
+-brcmf_sdio_watchdog_thread(void *data)
+-{
+- struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
+-
+- allow_signal(SIGTERM);
+- /* Run until signal received */
+- while (1) {
+- if (kthread_should_stop())
+- break;
+- if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
+- brcmf_sdio_bus_watchdog(bus);
+- /* Count the tick for reference */
+- bus->sdcnt.tickcnt++;
+- } else
+- break;
+- }
+- return 0;
+-}
+-
+-static void
+-brcmf_sdio_watchdog(unsigned long data)
+-{
+- struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
+-
+- if (bus->watchdog_tsk) {
+- complete(&bus->watchdog_wait);
+- /* Reschedule the watchdog */
+- if (bus->wd_timer_valid)
+- mod_timer(&bus->timer,
+- jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
+- }
+-}
+-
+-static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
+- .stop = brcmf_sdio_bus_stop,
+- .preinit = brcmf_sdio_bus_preinit,
+- .init = brcmf_sdio_bus_init,
+- .txdata = brcmf_sdio_bus_txdata,
+- .txctl = brcmf_sdio_bus_txctl,
+- .rxctl = brcmf_sdio_bus_rxctl,
+- .gettxq = brcmf_sdio_bus_gettxq,
+-};
+-
+-struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
+-{
+- int ret;
+- struct brcmf_sdio *bus;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /* Allocate private bus interface state */
+- bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
+- if (!bus)
+- goto fail;
+-
+- bus->sdiodev = sdiodev;
+- sdiodev->bus = bus;
+- skb_queue_head_init(&bus->glom);
+- bus->txbound = BRCMF_TXBOUND;
+- bus->rxbound = BRCMF_RXBOUND;
+- bus->txminmax = BRCMF_TXMINMAX;
+- bus->tx_seq = SDPCM_SEQ_WRAP - 1;
+-
+- /* platform specific configuration:
+- * alignments must be at least 4 bytes for ADMA
+- */
+- bus->head_align = ALIGNMENT;
+- bus->sgentry_align = ALIGNMENT;
+- if (sdiodev->pdata) {
+- if (sdiodev->pdata->sd_head_align > ALIGNMENT)
+- bus->head_align = sdiodev->pdata->sd_head_align;
+- if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
+- bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
+- }
+-
+- INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
+- bus->brcmf_wq = create_singlethread_workqueue("brcmf_wq");
+- if (bus->brcmf_wq == NULL) {
+- brcmf_err("insufficient memory to create txworkqueue\n");
+- goto fail;
+- }
+-
+- /* attempt to attach to the dongle */
+- if (!(brcmf_sdio_probe_attach(bus))) {
+- brcmf_err("brcmf_sdio_probe_attach failed\n");
+- goto fail;
+- }
+-
+- spin_lock_init(&bus->rxctl_lock);
+- spin_lock_init(&bus->txqlock);
+- init_waitqueue_head(&bus->ctrl_wait);
+- init_waitqueue_head(&bus->dcmd_resp_wait);
+-
+- /* Set up the watchdog timer */
+- init_timer(&bus->timer);
+- bus->timer.data = (unsigned long)bus;
+- bus->timer.function = brcmf_sdio_watchdog;
+-
+- /* Initialize watchdog thread */
+- init_completion(&bus->watchdog_wait);
+- bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
+- bus, "brcmf_watchdog");
+- if (IS_ERR(bus->watchdog_tsk)) {
+- pr_warn("brcmf_watchdog thread failed to start\n");
+- bus->watchdog_tsk = NULL;
+- }
+- /* Initialize DPC thread */
+- atomic_set(&bus->dpc_tskcnt, 0);
+-
+- /* Assign bus interface call back */
+- bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
+- bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
+- bus->sdiodev->bus_if->chip = bus->ci->chip;
+- bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
+-
+- /* default sdio bus header length for tx packet */
+- bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
+-
+- /* Attach to the common layer, reserve hdr space */
+- ret = brcmf_attach(bus->sdiodev->dev);
+- if (ret != 0) {
+- brcmf_err("brcmf_attach failed\n");
+- goto fail;
+- }
+-
+- /* Allocate buffers */
+- if (bus->sdiodev->bus_if->maxctl) {
+- bus->rxblen =
+- roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
+- ALIGNMENT) + bus->head_align;
+- bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
+- if (!(bus->rxbuf)) {
+- brcmf_err("rxbuf allocation failed\n");
+- goto fail;
+- }
+- }
+-
+- sdio_claim_host(bus->sdiodev->func[1]);
+-
+- /* Disable F2 to clear any intermediate frame state on the dongle */
+- sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
+-
+- bus->rxflow = false;
+-
+- /* Done with backplane-dependent accesses, can drop clock... */
+- brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
+-
+- sdio_release_host(bus->sdiodev->func[1]);
+-
+- /* ...and initialize clock/power states */
+- bus->clkstate = CLK_SDONLY;
+- bus->idletime = BRCMF_IDLE_INTERVAL;
+- bus->idleclock = BRCMF_IDLE_ACTIVE;
+-
+- /* Query the F2 block size, set roundup accordingly */
+- bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
+- bus->roundup = min(max_roundup, bus->blocksize);
+-
+- /* SR state */
+- bus->sleeping = false;
+- bus->sr_enabled = false;
+-
+- brcmf_sdio_debugfs_create(bus);
+- brcmf_dbg(INFO, "completed!!\n");
+-
+- /* if firmware path present try to download and bring up bus */
+- ret = brcmf_bus_start(bus->sdiodev->dev);
+- if (ret != 0) {
+- brcmf_err("dongle is not responding\n");
+- goto fail;
+- }
+-
+- return bus;
+-
+-fail:
+- brcmf_sdio_remove(bus);
+- return NULL;
+-}
+-
+-/* Detach and free everything */
+-void brcmf_sdio_remove(struct brcmf_sdio *bus)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (bus) {
+- /* De-register interrupt handler */
+- brcmf_sdiod_intr_unregister(bus->sdiodev);
+-
+- cancel_work_sync(&bus->datawork);
+- if (bus->brcmf_wq)
+- destroy_workqueue(bus->brcmf_wq);
+-
+- if (bus->sdiodev->bus_if->drvr) {
+- brcmf_detach(bus->sdiodev->dev);
+- }
+-
+- if (bus->ci) {
+- if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
+- sdio_claim_host(bus->sdiodev->func[1]);
+- brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
+- /* Leave the device in state where it is
+- * 'quiet'. This is done by putting it in
+- * download_state which essentially resets
+- * all necessary cores.
+- */
+- msleep(20);
+- brcmf_sdio_chip_enter_download(bus->sdiodev,
+- bus->ci);
+- brcmf_sdio_clkctl(bus, CLK_NONE, false);
+- sdio_release_host(bus->sdiodev->func[1]);
+- }
+- brcmf_sdio_chip_detach(&bus->ci);
+- }
+-
+- kfree(bus->rxbuf);
+- kfree(bus->hdrbuf);
+- kfree(bus);
+- }
+-
+- brcmf_dbg(TRACE, "Disconnected\n");
+-}
+-
+-void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
+-{
+- /* Totally stop the timer */
+- if (!wdtick && bus->wd_timer_valid) {
+- del_timer_sync(&bus->timer);
+- bus->wd_timer_valid = false;
+- bus->save_ms = wdtick;
+- return;
+- }
+-
+- /* don't start the wd until fw is loaded */
+- if (bus->sdiodev->bus_if->state != BRCMF_BUS_DATA)
+- return;
+-
+- if (wdtick) {
+- if (bus->save_ms != BRCMF_WD_POLL_MS) {
+- if (bus->wd_timer_valid)
+- /* Stop timer and restart at new value */
+- del_timer_sync(&bus->timer);
+-
+- /* Create timer again when watchdog period is
+- dynamically changed or in the first instance
+- */
+- bus->timer.expires =
+- jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
+- add_timer(&bus->timer);
+-
+- } else {
+- /* Re arm the timer, at last watchdog period */
+- mod_timer(&bus->timer,
+- jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
+- }
+-
+- bus->wd_timer_valid = true;
+- bus->save_ms = wdtick;
+- }
+-}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/feature.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/feature.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/feature.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/feature.c 2016-06-19 22:11:55.281141582 +0200
+@@ -0,0 +1,159 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/netdevice.h>
++
++#include <brcm_hw_ids.h>
++#include "core.h"
++#include "bus.h"
++#include "debug.h"
++#include "fwil.h"
++#include "feature.h"
++
++/*
++ * expand feature list to array of feature strings.
++ */
++#define BRCMF_FEAT_DEF(_f) \
++ #_f,
++static const char *brcmf_feat_names[] = {
++ BRCMF_FEAT_LIST
++};
++#undef BRCMF_FEAT_DEF
++
++#ifdef DEBUG
++/*
++ * expand quirk list to array of quirk strings.
++ */
++#define BRCMF_QUIRK_DEF(_q) \
++ #_q,
++static const char * const brcmf_quirk_names[] = {
++ BRCMF_QUIRK_LIST
++};
++#undef BRCMF_QUIRK_DEF
++
++/**
++ * brcmf_feat_debugfs_read() - expose feature info to debugfs.
++ *
++ * @seq: sequence for debugfs entry.
++ * @data: raw data pointer.
++ */
++static int brcmf_feat_debugfs_read(struct seq_file *seq, void *data)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
++ u32 feats = bus_if->drvr->feat_flags;
++ u32 quirks = bus_if->drvr->chip_quirks;
++ int id;
++
++ seq_printf(seq, "Features: %08x\n", feats);
++ for (id = 0; id < BRCMF_FEAT_LAST; id++)
++ if (feats & BIT(id))
++ seq_printf(seq, "\t%s\n", brcmf_feat_names[id]);
++ seq_printf(seq, "\nQuirks: %08x\n", quirks);
++ for (id = 0; id < BRCMF_FEAT_QUIRK_LAST; id++)
++ if (quirks & BIT(id))
++ seq_printf(seq, "\t%s\n", brcmf_quirk_names[id]);
++ return 0;
++}
++#else
++static int brcmf_feat_debugfs_read(struct seq_file *seq, void *data)
++{
++ return 0;
++}
++#endif /* DEBUG */
++
++/**
++ * brcmf_feat_iovar_int_get() - determine feature through iovar query.
++ *
++ * @ifp: interface to query.
++ * @id: feature id.
++ * @name: iovar name.
++ */
++static void brcmf_feat_iovar_int_get(struct brcmf_if *ifp,
++ enum brcmf_feat_id id, char *name)
++{
++ u32 data;
++ int err;
++
++ err = brcmf_fil_iovar_int_get(ifp, name, &data);
++ if (err == 0) {
++ brcmf_dbg(INFO, "enabling feature: %s\n", brcmf_feat_names[id]);
++ ifp->drvr->feat_flags |= BIT(id);
++ } else {
++ brcmf_dbg(TRACE, "%s feature check failed: %d\n",
++ brcmf_feat_names[id], err);
++ }
++}
++
++/**
++ * brcmf_feat_iovar_int_set() - determine feature through iovar set.
++ *
++ * @ifp: interface to query.
++ * @id: feature id.
++ * @name: iovar name.
++ */
++static void brcmf_feat_iovar_int_set(struct brcmf_if *ifp,
++ enum brcmf_feat_id id, char *name, u32 val)
++{
++ int err;
++
++ err = brcmf_fil_iovar_int_set(ifp, name, val);
++ if (err == 0) {
++ brcmf_dbg(INFO, "enabling feature: %s\n", brcmf_feat_names[id]);
++ ifp->drvr->feat_flags |= BIT(id);
++ } else {
++ brcmf_dbg(TRACE, "%s feature check failed: %d\n",
++ brcmf_feat_names[id], err);
++ }
++}
++
++void brcmf_feat_attach(struct brcmf_pub *drvr)
++{
++ struct brcmf_if *ifp = drvr->iflist[0];
++
++ brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_MCHAN, "mchan");
++ brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_PNO, "pfn");
++ if (drvr->bus_if->wowl_supported)
++ brcmf_feat_iovar_int_get(ifp, BRCMF_FEAT_WOWL, "wowl");
++ if ((drvr->bus_if->chip != BRCM_CC_43362_CHIP_ID) &&
++ (drvr->bus_if->chip != BRCM_CC_4330_CHIP_ID))
++ brcmf_feat_iovar_int_set(ifp, BRCMF_FEAT_MBSS, "mbss", 0);
++
++ /* set chip related quirks */
++ switch (drvr->bus_if->chip) {
++ case BRCM_CC_43236_CHIP_ID:
++ drvr->chip_quirks |= BIT(BRCMF_FEAT_QUIRK_AUTO_AUTH);
++ break;
++ case BRCM_CC_4329_CHIP_ID:
++ drvr->chip_quirks |= BIT(BRCMF_FEAT_QUIRK_NEED_MPC);
++ break;
++ default:
++ /* no quirks */
++ break;
++ }
++
++ brcmf_debugfs_add_entry(drvr, "features", brcmf_feat_debugfs_read);
++}
++
++bool brcmf_feat_is_enabled(struct brcmf_if *ifp, enum brcmf_feat_id id)
++{
++ return (ifp->drvr->feat_flags & BIT(id));
++}
++
++bool brcmf_feat_is_quirk_enabled(struct brcmf_if *ifp,
++ enum brcmf_feat_quirk quirk)
++{
++ return (ifp->drvr->chip_quirks & BIT(quirk));
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/feature.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/feature.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/feature.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/feature.h 2016-06-19 22:11:55.281141582 +0200
+@@ -0,0 +1,92 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef _BRCMF_FEATURE_H
++#define _BRCMF_FEATURE_H
++
++/*
++ * Features:
++ *
++ * MBSS: multiple BSSID support (eg. guest network in AP mode).
++ * MCHAN: multi-channel for concurrent P2P.
++ * PNO: preferred network offload.
++ * WOWL: Wake-On-WLAN.
++ */
++#define BRCMF_FEAT_LIST \
++ BRCMF_FEAT_DEF(MBSS) \
++ BRCMF_FEAT_DEF(MCHAN) \
++ BRCMF_FEAT_DEF(PNO) \
++ BRCMF_FEAT_DEF(WOWL)
++/*
++ * Quirks:
++ *
++ * AUTO_AUTH: workaround needed for automatic authentication type.
++ * NEED_MPC: driver needs to disable MPC during scanning operation.
++ */
++#define BRCMF_QUIRK_LIST \
++ BRCMF_QUIRK_DEF(AUTO_AUTH) \
++ BRCMF_QUIRK_DEF(NEED_MPC)
++
++#define BRCMF_FEAT_DEF(_f) \
++ BRCMF_FEAT_ ## _f,
++/*
++ * expand feature list to enumeration.
++ */
++enum brcmf_feat_id {
++ BRCMF_FEAT_LIST
++ BRCMF_FEAT_LAST
++};
++#undef BRCMF_FEAT_DEF
++
++#define BRCMF_QUIRK_DEF(_q) \
++ BRCMF_FEAT_QUIRK_ ## _q,
++/*
++ * expand quirk list to enumeration.
++ */
++enum brcmf_feat_quirk {
++ BRCMF_QUIRK_LIST
++ BRCMF_FEAT_QUIRK_LAST
++};
++#undef BRCMF_QUIRK_DEF
++
++/**
++ * brcmf_feat_attach() - determine features and quirks.
++ *
++ * @drvr: driver instance.
++ */
++void brcmf_feat_attach(struct brcmf_pub *drvr);
++
++/**
++ * brcmf_feat_is_enabled() - query feature.
++ *
++ * @ifp: interface instance.
++ * @id: feature id to check.
++ *
++ * Return: true is feature is enabled; otherwise false.
++ */
++bool brcmf_feat_is_enabled(struct brcmf_if *ifp, enum brcmf_feat_id id);
++
++/**
++ * brcmf_feat_is_quirk_enabled() - query chip quirk.
++ *
++ * @ifp: interface instance.
++ * @quirk: quirk id to check.
++ *
++ * Return: true is quirk is enabled; otherwise false.
++ */
++bool brcmf_feat_is_quirk_enabled(struct brcmf_if *ifp,
++ enum brcmf_feat_quirk quirk);
++
++#endif /* _BRCMF_FEATURE_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/firmware.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/firmware.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/firmware.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/firmware.c 2016-06-19 22:11:55.281141582 +0200
+@@ -0,0 +1,513 @@
++/*
++ * Copyright (c) 2013 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/firmware.h>
++#include <linux/module.h>
++
++#include "debug.h"
++#include "firmware.h"
++
++#define BRCMF_FW_MAX_NVRAM_SIZE 64000
++#define BRCMF_FW_NVRAM_DEVPATH_LEN 19 /* devpath0=pcie/1/4/ */
++#define BRCMF_FW_NVRAM_PCIEDEV_LEN 9 /* pcie/1/4/ */
++
++char brcmf_firmware_path[BRCMF_FW_PATH_LEN];
++module_param_string(firmware_path, brcmf_firmware_path,
++ BRCMF_FW_PATH_LEN, 0440);
++
++enum nvram_parser_state {
++ IDLE,
++ KEY,
++ VALUE,
++ COMMENT,
++ END
++};
++
++/**
++ * struct nvram_parser - internal info for parser.
++ *
++ * @state: current parser state.
++ * @fwnv: input buffer being parsed.
++ * @nvram: output buffer with parse result.
++ * @nvram_len: lenght of parse result.
++ * @line: current line.
++ * @column: current column in line.
++ * @pos: byte offset in input buffer.
++ * @entry: start position of key,value entry.
++ * @multi_dev_v1: detect pcie multi device v1 (compressed).
++ * @multi_dev_v2: detect pcie multi device v2.
++ */
++struct nvram_parser {
++ enum nvram_parser_state state;
++ const struct firmware *fwnv;
++ u8 *nvram;
++ u32 nvram_len;
++ u32 line;
++ u32 column;
++ u32 pos;
++ u32 entry;
++ bool multi_dev_v1;
++ bool multi_dev_v2;
++};
++
++static bool is_nvram_char(char c)
++{
++ /* comment marker excluded */
++ if (c == '#')
++ return false;
++
++ /* key and value may have any other readable character */
++ return (c > 0x20 && c < 0x7f);
++}
++
++static bool is_whitespace(char c)
++{
++ return (c == ' ' || c == '\r' || c == '\n' || c == '\t');
++}
++
++static enum nvram_parser_state brcmf_nvram_handle_idle(struct nvram_parser *nvp)
++{
++ char c;
++
++ c = nvp->fwnv->data[nvp->pos];
++ if (c == '\n')
++ return COMMENT;
++ if (is_whitespace(c))
++ goto proceed;
++ if (c == '#')
++ return COMMENT;
++ if (is_nvram_char(c)) {
++ nvp->entry = nvp->pos;
++ return KEY;
++ }
++ brcmf_dbg(INFO, "warning: ln=%d:col=%d: ignoring invalid character\n",
++ nvp->line, nvp->column);
++proceed:
++ nvp->column++;
++ nvp->pos++;
++ return IDLE;
++}
++
++static enum nvram_parser_state brcmf_nvram_handle_key(struct nvram_parser *nvp)
++{
++ enum nvram_parser_state st = nvp->state;
++ char c;
++
++ c = nvp->fwnv->data[nvp->pos];
++ if (c == '=') {
++ /* ignore RAW1 by treating as comment */
++ if (strncmp(&nvp->fwnv->data[nvp->entry], "RAW1", 4) == 0)
++ st = COMMENT;
++ else
++ st = VALUE;
++ if (strncmp(&nvp->fwnv->data[nvp->entry], "devpath", 7) == 0)
++ nvp->multi_dev_v1 = true;
++ if (strncmp(&nvp->fwnv->data[nvp->entry], "pcie/", 5) == 0)
++ nvp->multi_dev_v2 = true;
++ } else if (!is_nvram_char(c)) {
++ brcmf_dbg(INFO, "warning: ln=%d:col=%d: '=' expected, skip invalid key entry\n",
++ nvp->line, nvp->column);
++ return COMMENT;
++ }
++
++ nvp->column++;
++ nvp->pos++;
++ return st;
++}
++
++static enum nvram_parser_state
++brcmf_nvram_handle_value(struct nvram_parser *nvp)
++{
++ char c;
++ char *skv;
++ char *ekv;
++ u32 cplen;
++
++ c = nvp->fwnv->data[nvp->pos];
++ if (!is_nvram_char(c)) {
++ /* key,value pair complete */
++ ekv = (u8 *)&nvp->fwnv->data[nvp->pos];
++ skv = (u8 *)&nvp->fwnv->data[nvp->entry];
++ cplen = ekv - skv;
++ if (nvp->nvram_len + cplen + 1 >= BRCMF_FW_MAX_NVRAM_SIZE)
++ return END;
++ /* copy to output buffer */
++ memcpy(&nvp->nvram[nvp->nvram_len], skv, cplen);
++ nvp->nvram_len += cplen;
++ nvp->nvram[nvp->nvram_len] = '\0';
++ nvp->nvram_len++;
++ return IDLE;
++ }
++ nvp->pos++;
++ nvp->column++;
++ return VALUE;
++}
++
++static enum nvram_parser_state
++brcmf_nvram_handle_comment(struct nvram_parser *nvp)
++{
++ char *eol, *sol;
++
++ sol = (char *)&nvp->fwnv->data[nvp->pos];
++ eol = strchr(sol, '\n');
++ if (eol == NULL)
++ return END;
++
++ /* eat all moving to next line */
++ nvp->line++;
++ nvp->column = 1;
++ nvp->pos += (eol - sol) + 1;
++ return IDLE;
++}
++
++static enum nvram_parser_state brcmf_nvram_handle_end(struct nvram_parser *nvp)
++{
++ /* final state */
++ return END;
++}
++
++static enum nvram_parser_state
++(*nv_parser_states[])(struct nvram_parser *nvp) = {
++ brcmf_nvram_handle_idle,
++ brcmf_nvram_handle_key,
++ brcmf_nvram_handle_value,
++ brcmf_nvram_handle_comment,
++ brcmf_nvram_handle_end
++};
++
++static int brcmf_init_nvram_parser(struct nvram_parser *nvp,
++ const struct firmware *nv)
++{
++ size_t size;
++
++ memset(nvp, 0, sizeof(*nvp));
++ nvp->fwnv = nv;
++ /* Limit size to MAX_NVRAM_SIZE, some files contain lot of comment */
++ if (nv->size > BRCMF_FW_MAX_NVRAM_SIZE)
++ size = BRCMF_FW_MAX_NVRAM_SIZE;
++ else
++ size = nv->size;
++ /* Alloc for extra 0 byte + roundup by 4 + length field */
++ size += 1 + 3 + sizeof(u32);
++ nvp->nvram = kzalloc(size, GFP_KERNEL);
++ if (!nvp->nvram)
++ return -ENOMEM;
++
++ nvp->line = 1;
++ nvp->column = 1;
++ return 0;
++}
++
++/* brcmf_fw_strip_multi_v1 :Some nvram files contain settings for multiple
++ * devices. Strip it down for one device, use domain_nr/bus_nr to determine
++ * which data is to be returned. v1 is the version where nvram is stored
++ * compressed and "devpath" maps to index for valid entries.
++ */
++static void brcmf_fw_strip_multi_v1(struct nvram_parser *nvp, u16 domain_nr,
++ u16 bus_nr)
++{
++ u32 i, j;
++ bool found;
++ u8 *nvram;
++ u8 id;
++
++ nvram = kzalloc(nvp->nvram_len + 1 + 3 + sizeof(u32), GFP_KERNEL);
++ if (!nvram)
++ goto fail;
++
++ /* min length: devpath0=pcie/1/4/ + 0:x=y */
++ if (nvp->nvram_len < BRCMF_FW_NVRAM_DEVPATH_LEN + 6)
++ goto fail;
++
++ /* First search for the devpathX and see if it is the configuration
++ * for domain_nr/bus_nr. Search complete nvp
++ */
++ found = false;
++ i = 0;
++ while (i < nvp->nvram_len - BRCMF_FW_NVRAM_DEVPATH_LEN) {
++ /* Format: devpathX=pcie/Y/Z/
++ * Y = domain_nr, Z = bus_nr, X = virtual ID
++ */
++ if ((strncmp(&nvp->nvram[i], "devpath", 7) == 0) &&
++ (strncmp(&nvp->nvram[i + 8], "=pcie/", 6) == 0)) {
++ if (((nvp->nvram[i + 14] - '0') == domain_nr) &&
++ ((nvp->nvram[i + 16] - '0') == bus_nr)) {
++ id = nvp->nvram[i + 7] - '0';
++ found = true;
++ break;
++ }
++ }
++ while (nvp->nvram[i] != 0)
++ i++;
++ i++;
++ }
++ if (!found)
++ goto fail;
++
++ /* Now copy all valid entries, release old nvram and assign new one */
++ i = 0;
++ j = 0;
++ while (i < nvp->nvram_len) {
++ if ((nvp->nvram[i] - '0' == id) && (nvp->nvram[i + 1] == ':')) {
++ i += 2;
++ while (nvp->nvram[i] != 0) {
++ nvram[j] = nvp->nvram[i];
++ i++;
++ j++;
++ }
++ nvram[j] = 0;
++ j++;
++ }
++ while (nvp->nvram[i] != 0)
++ i++;
++ i++;
++ }
++ kfree(nvp->nvram);
++ nvp->nvram = nvram;
++ nvp->nvram_len = j;
++ return;
++
++fail:
++ kfree(nvram);
++ nvp->nvram_len = 0;
++}
++
++/* brcmf_fw_strip_multi_v2 :Some nvram files contain settings for multiple
++ * devices. Strip it down for one device, use domain_nr/bus_nr to determine
++ * which data is to be returned. v2 is the version where nvram is stored
++ * uncompressed, all relevant valid entries are identified by
++ * pcie/domain_nr/bus_nr:
++ */
++static void brcmf_fw_strip_multi_v2(struct nvram_parser *nvp, u16 domain_nr,
++ u16 bus_nr)
++{
++ u32 i, j;
++ u8 *nvram;
++
++ nvram = kzalloc(nvp->nvram_len + 1 + 3 + sizeof(u32), GFP_KERNEL);
++ if (!nvram)
++ goto fail;
++
++ /* Copy all valid entries, release old nvram and assign new one.
++ * Valid entries are of type pcie/X/Y/ where X = domain_nr and
++ * Y = bus_nr.
++ */
++ i = 0;
++ j = 0;
++ while (i < nvp->nvram_len - BRCMF_FW_NVRAM_PCIEDEV_LEN) {
++ if ((strncmp(&nvp->nvram[i], "pcie/", 5) == 0) &&
++ (nvp->nvram[i + 6] == '/') && (nvp->nvram[i + 8] == '/') &&
++ ((nvp->nvram[i + 5] - '0') == domain_nr) &&
++ ((nvp->nvram[i + 7] - '0') == bus_nr)) {
++ i += BRCMF_FW_NVRAM_PCIEDEV_LEN;
++ while (nvp->nvram[i] != 0) {
++ nvram[j] = nvp->nvram[i];
++ i++;
++ j++;
++ }
++ nvram[j] = 0;
++ j++;
++ }
++ while (nvp->nvram[i] != 0)
++ i++;
++ i++;
++ }
++ kfree(nvp->nvram);
++ nvp->nvram = nvram;
++ nvp->nvram_len = j;
++ return;
++fail:
++ kfree(nvram);
++ nvp->nvram_len = 0;
++}
++
++/* brcmf_nvram_strip :Takes a buffer of "<var>=<value>\n" lines read from a fil
++ * and ending in a NUL. Removes carriage returns, empty lines, comment lines,
++ * and converts newlines to NULs. Shortens buffer as needed and pads with NULs.
++ * End of buffer is completed with token identifying length of buffer.
++ */
++static void *brcmf_fw_nvram_strip(const struct firmware *nv, u32 *new_length,
++ u16 domain_nr, u16 bus_nr)
++{
++ struct nvram_parser nvp;
++ u32 pad;
++ u32 token;
++ __le32 token_le;
++
++ if (brcmf_init_nvram_parser(&nvp, nv) < 0)
++ return NULL;
++
++ while (nvp.pos < nv->size) {
++ nvp.state = nv_parser_states[nvp.state](&nvp);
++ if (nvp.state == END)
++ break;
++ }
++ if (nvp.multi_dev_v1)
++ brcmf_fw_strip_multi_v1(&nvp, domain_nr, bus_nr);
++ else if (nvp.multi_dev_v2)
++ brcmf_fw_strip_multi_v2(&nvp, domain_nr, bus_nr);
++
++ if (nvp.nvram_len == 0) {
++ kfree(nvp.nvram);
++ return NULL;
++ }
++
++ pad = nvp.nvram_len;
++ *new_length = roundup(nvp.nvram_len + 1, 4);
++ while (pad != *new_length) {
++ nvp.nvram[pad] = 0;
++ pad++;
++ }
++
++ token = *new_length / 4;
++ token = (~token << 16) | (token & 0x0000FFFF);
++ token_le = cpu_to_le32(token);
++
++ memcpy(&nvp.nvram[*new_length], &token_le, sizeof(token_le));
++ *new_length += sizeof(token_le);
++
++ return nvp.nvram;
++}
++
++void brcmf_fw_nvram_free(void *nvram)
++{
++ kfree(nvram);
++}
++
++struct brcmf_fw {
++ struct device *dev;
++ u16 flags;
++ const struct firmware *code;
++ const char *nvram_name;
++ u16 domain_nr;
++ u16 bus_nr;
++ void (*done)(struct device *dev, const struct firmware *fw,
++ void *nvram_image, u32 nvram_len);
++};
++
++static void brcmf_fw_request_nvram_done(const struct firmware *fw, void *ctx)
++{
++ struct brcmf_fw *fwctx = ctx;
++ u32 nvram_length = 0;
++ void *nvram = NULL;
++
++ brcmf_dbg(TRACE, "enter: dev=%s\n", dev_name(fwctx->dev));
++ if (!fw && !(fwctx->flags & BRCMF_FW_REQ_NV_OPTIONAL))
++ goto fail;
++
++ if (fw) {
++ nvram = brcmf_fw_nvram_strip(fw, &nvram_length,
++ fwctx->domain_nr, fwctx->bus_nr);
++ release_firmware(fw);
++ if (!nvram && !(fwctx->flags & BRCMF_FW_REQ_NV_OPTIONAL))
++ goto fail;
++ }
++
++ fwctx->done(fwctx->dev, fwctx->code, nvram, nvram_length);
++ kfree(fwctx);
++ return;
++
++fail:
++ brcmf_dbg(TRACE, "failed: dev=%s\n", dev_name(fwctx->dev));
++ release_firmware(fwctx->code);
++ device_release_driver(fwctx->dev);
++ kfree(fwctx);
++}
++
++static void brcmf_fw_request_code_done(const struct firmware *fw, void *ctx)
++{
++ struct brcmf_fw *fwctx = ctx;
++ int ret;
++
++ brcmf_dbg(TRACE, "enter: dev=%s\n", dev_name(fwctx->dev));
++ if (!fw)
++ goto fail;
++
++ /* only requested code so done here */
++ if (!(fwctx->flags & BRCMF_FW_REQUEST_NVRAM)) {
++ fwctx->done(fwctx->dev, fw, NULL, 0);
++ kfree(fwctx);
++ return;
++ }
++ fwctx->code = fw;
++ ret = request_firmware_nowait(THIS_MODULE, true, fwctx->nvram_name,
++ fwctx->dev, GFP_KERNEL, fwctx,
++ brcmf_fw_request_nvram_done);
++
++ if (!ret)
++ return;
++
++ /* when nvram is optional call .done() callback here */
++ if (fwctx->flags & BRCMF_FW_REQ_NV_OPTIONAL) {
++ fwctx->done(fwctx->dev, fw, NULL, 0);
++ kfree(fwctx);
++ return;
++ }
++
++ /* failed nvram request */
++ release_firmware(fw);
++fail:
++ brcmf_dbg(TRACE, "failed: dev=%s\n", dev_name(fwctx->dev));
++ device_release_driver(fwctx->dev);
++ kfree(fwctx);
++}
++
++int brcmf_fw_get_firmwares_pcie(struct device *dev, u16 flags,
++ const char *code, const char *nvram,
++ void (*fw_cb)(struct device *dev,
++ const struct firmware *fw,
++ void *nvram_image, u32 nvram_len),
++ u16 domain_nr, u16 bus_nr)
++{
++ struct brcmf_fw *fwctx;
++
++ brcmf_dbg(TRACE, "enter: dev=%s\n", dev_name(dev));
++ if (!fw_cb || !code)
++ return -EINVAL;
++
++ if ((flags & BRCMF_FW_REQUEST_NVRAM) && !nvram)
++ return -EINVAL;
++
++ fwctx = kzalloc(sizeof(*fwctx), GFP_KERNEL);
++ if (!fwctx)
++ return -ENOMEM;
++
++ fwctx->dev = dev;
++ fwctx->flags = flags;
++ fwctx->done = fw_cb;
++ if (flags & BRCMF_FW_REQUEST_NVRAM)
++ fwctx->nvram_name = nvram;
++ fwctx->domain_nr = domain_nr;
++ fwctx->bus_nr = bus_nr;
++
++ return request_firmware_nowait(THIS_MODULE, true, code, dev,
++ GFP_KERNEL, fwctx,
++ brcmf_fw_request_code_done);
++}
++
++int brcmf_fw_get_firmwares(struct device *dev, u16 flags,
++ const char *code, const char *nvram,
++ void (*fw_cb)(struct device *dev,
++ const struct firmware *fw,
++ void *nvram_image, u32 nvram_len))
++{
++ return brcmf_fw_get_firmwares_pcie(dev, flags, code, nvram, fw_cb, 0,
++ 0);
++}
++
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/firmware.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/firmware.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/firmware.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/firmware.h 2016-06-19 22:11:55.281141582 +0200
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (c) 2013 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_FIRMWARE_H
++#define BRCMFMAC_FIRMWARE_H
++
++#define BRCMF_FW_REQUEST 0x000F
++#define BRCMF_FW_REQUEST_NVRAM 0x0001
++#define BRCMF_FW_REQ_FLAGS 0x00F0
++#define BRCMF_FW_REQ_NV_OPTIONAL 0x0010
++
++#define BRCMF_FW_PATH_LEN 256
++#define BRCMF_FW_NAME_LEN 32
++
++extern char brcmf_firmware_path[];
++
++void brcmf_fw_nvram_free(void *nvram);
++/*
++ * Request firmware(s) asynchronously. When the asynchronous request
++ * fails it will not use the callback, but call device_release_driver()
++ * instead which will call the driver .remove() callback.
++ */
++int brcmf_fw_get_firmwares_pcie(struct device *dev, u16 flags,
++ const char *code, const char *nvram,
++ void (*fw_cb)(struct device *dev,
++ const struct firmware *fw,
++ void *nvram_image, u32 nvram_len),
++ u16 domain_nr, u16 bus_nr);
++int brcmf_fw_get_firmwares(struct device *dev, u16 flags,
++ const char *code, const char *nvram,
++ void (*fw_cb)(struct device *dev,
++ const struct firmware *fw,
++ void *nvram_image, u32 nvram_len));
++
++#endif /* BRCMFMAC_FIRMWARE_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/flowring.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/flowring.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/flowring.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/flowring.c 2016-06-19 22:11:55.285141319 +0200
+@@ -0,0 +1,500 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++
++#include <linux/types.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <brcmu_utils.h>
++
++#include "core.h"
++#include "debug.h"
++#include "bus.h"
++#include "proto.h"
++#include "flowring.h"
++#include "msgbuf.h"
++#include "common.h"
++
++
++#define BRCMF_FLOWRING_HIGH 1024
++#define BRCMF_FLOWRING_LOW (BRCMF_FLOWRING_HIGH - 256)
++#define BRCMF_FLOWRING_INVALID_IFIDX 0xff
++
++#define BRCMF_FLOWRING_HASH_AP(da, fifo, ifidx) (da[5] + fifo + ifidx * 16)
++#define BRCMF_FLOWRING_HASH_STA(fifo, ifidx) (fifo + ifidx * 16)
++
++static const u8 brcmf_flowring_prio2fifo[] = {
++ 1,
++ 0,
++ 0,
++ 1,
++ 2,
++ 2,
++ 3,
++ 3
++};
++
++
++static bool
++brcmf_flowring_is_tdls_mac(struct brcmf_flowring *flow, u8 mac[ETH_ALEN])
++{
++ struct brcmf_flowring_tdls_entry *search;
++
++ search = flow->tdls_entry;
++
++ while (search) {
++ if (memcmp(search->mac, mac, ETH_ALEN) == 0)
++ return true;
++ search = search->next;
++ }
++
++ return false;
++}
++
++
++u32 brcmf_flowring_lookup(struct brcmf_flowring *flow, u8 da[ETH_ALEN],
++ u8 prio, u8 ifidx)
++{
++ struct brcmf_flowring_hash *hash;
++ u8 hash_idx;
++ u32 i;
++ bool found;
++ bool sta;
++ u8 fifo;
++ u8 *mac;
++
++ fifo = brcmf_flowring_prio2fifo[prio];
++ sta = (flow->addr_mode[ifidx] == ADDR_INDIRECT);
++ mac = da;
++ if ((!sta) && (is_multicast_ether_addr(da))) {
++ mac = (u8 *)ALLFFMAC;
++ fifo = 0;
++ }
++ if ((sta) && (flow->tdls_active) &&
++ (brcmf_flowring_is_tdls_mac(flow, da))) {
++ sta = false;
++ }
++ hash_idx = sta ? BRCMF_FLOWRING_HASH_STA(fifo, ifidx) :
++ BRCMF_FLOWRING_HASH_AP(mac, fifo, ifidx);
++ found = false;
++ hash = flow->hash;
++ for (i = 0; i < BRCMF_FLOWRING_HASHSIZE; i++) {
++ if ((sta || (memcmp(hash[hash_idx].mac, mac, ETH_ALEN) == 0)) &&
++ (hash[hash_idx].fifo == fifo) &&
++ (hash[hash_idx].ifidx == ifidx)) {
++ found = true;
++ break;
++ }
++ hash_idx++;
++ }
++ if (found)
++ return hash[hash_idx].flowid;
++
++ return BRCMF_FLOWRING_INVALID_ID;
++}
++
++
++u32 brcmf_flowring_create(struct brcmf_flowring *flow, u8 da[ETH_ALEN],
++ u8 prio, u8 ifidx)
++{
++ struct brcmf_flowring_ring *ring;
++ struct brcmf_flowring_hash *hash;
++ u8 hash_idx;
++ u32 i;
++ bool found;
++ u8 fifo;
++ bool sta;
++ u8 *mac;
++
++ fifo = brcmf_flowring_prio2fifo[prio];
++ sta = (flow->addr_mode[ifidx] == ADDR_INDIRECT);
++ mac = da;
++ if ((!sta) && (is_multicast_ether_addr(da))) {
++ mac = (u8 *)ALLFFMAC;
++ fifo = 0;
++ }
++ if ((sta) && (flow->tdls_active) &&
++ (brcmf_flowring_is_tdls_mac(flow, da))) {
++ sta = false;
++ }
++ hash_idx = sta ? BRCMF_FLOWRING_HASH_STA(fifo, ifidx) :
++ BRCMF_FLOWRING_HASH_AP(mac, fifo, ifidx);
++ found = false;
++ hash = flow->hash;
++ for (i = 0; i < BRCMF_FLOWRING_HASHSIZE; i++) {
++ if ((hash[hash_idx].ifidx == BRCMF_FLOWRING_INVALID_IFIDX) &&
++ (is_zero_ether_addr(hash[hash_idx].mac))) {
++ found = true;
++ break;
++ }
++ hash_idx++;
++ }
++ if (found) {
++ for (i = 0; i < flow->nrofrings; i++) {
++ if (flow->rings[i] == NULL)
++ break;
++ }
++ if (i == flow->nrofrings)
++ return -ENOMEM;
++
++ ring = kzalloc(sizeof(*ring), GFP_ATOMIC);
++ if (!ring)
++ return -ENOMEM;
++
++ memcpy(hash[hash_idx].mac, mac, ETH_ALEN);
++ hash[hash_idx].fifo = fifo;
++ hash[hash_idx].ifidx = ifidx;
++ hash[hash_idx].flowid = i;
++
++ ring->hash_id = hash_idx;
++ ring->status = RING_CLOSED;
++ skb_queue_head_init(&ring->skblist);
++ flow->rings[i] = ring;
++
++ return i;
++ }
++ return BRCMF_FLOWRING_INVALID_ID;
++}
++
++
++u8 brcmf_flowring_tid(struct brcmf_flowring *flow, u8 flowid)
++{
++ struct brcmf_flowring_ring *ring;
++
++ ring = flow->rings[flowid];
++
++ return flow->hash[ring->hash_id].fifo;
++}
++
++
++static void brcmf_flowring_block(struct brcmf_flowring *flow, u8 flowid,
++ bool blocked)
++{
++ struct brcmf_flowring_ring *ring;
++ struct brcmf_bus *bus_if;
++ struct brcmf_pub *drvr;
++ struct brcmf_if *ifp;
++ bool currently_blocked;
++ int i;
++ u8 ifidx;
++ unsigned long flags;
++
++ spin_lock_irqsave(&flow->block_lock, flags);
++
++ ring = flow->rings[flowid];
++ ifidx = brcmf_flowring_ifidx_get(flow, flowid);
++
++ currently_blocked = false;
++ for (i = 0; i < flow->nrofrings; i++) {
++ if (flow->rings[i]) {
++ ring = flow->rings[i];
++ if ((ring->status == RING_OPEN) &&
++ (brcmf_flowring_ifidx_get(flow, i) == ifidx)) {
++ if (ring->blocked) {
++ currently_blocked = true;
++ break;
++ }
++ }
++ }
++ }
++ ring->blocked = blocked;
++ if (currently_blocked == blocked) {
++ spin_unlock_irqrestore(&flow->block_lock, flags);
++ return;
++ }
++
++ bus_if = dev_get_drvdata(flow->dev);
++ drvr = bus_if->drvr;
++ ifp = drvr->iflist[ifidx];
++ brcmf_txflowblock_if(ifp, BRCMF_NETIF_STOP_REASON_FLOW, blocked);
++
++ spin_unlock_irqrestore(&flow->block_lock, flags);
++}
++
++
++void brcmf_flowring_delete(struct brcmf_flowring *flow, u8 flowid)
++{
++ struct brcmf_flowring_ring *ring;
++ u8 hash_idx;
++ struct sk_buff *skb;
++
++ ring = flow->rings[flowid];
++ if (!ring)
++ return;
++ brcmf_flowring_block(flow, flowid, false);
++ hash_idx = ring->hash_id;
++ flow->hash[hash_idx].ifidx = BRCMF_FLOWRING_INVALID_IFIDX;
++ memset(flow->hash[hash_idx].mac, 0, ETH_ALEN);
++ flow->rings[flowid] = NULL;
++
++ skb = skb_dequeue(&ring->skblist);
++ while (skb) {
++ brcmu_pkt_buf_free_skb(skb);
++ skb = skb_dequeue(&ring->skblist);
++ }
++
++ kfree(ring);
++}
++
++
++u32 brcmf_flowring_enqueue(struct brcmf_flowring *flow, u8 flowid,
++ struct sk_buff *skb)
++{
++ struct brcmf_flowring_ring *ring;
++
++ ring = flow->rings[flowid];
++
++ skb_queue_tail(&ring->skblist, skb);
++
++ if (!ring->blocked &&
++ (skb_queue_len(&ring->skblist) > BRCMF_FLOWRING_HIGH)) {
++ brcmf_flowring_block(flow, flowid, true);
++ brcmf_dbg(MSGBUF, "Flowcontrol: BLOCK for ring %d\n", flowid);
++ /* To prevent (work around) possible race condition, check
++ * queue len again. It is also possible to use locking to
++ * protect, but that is undesirable for every enqueue and
++ * dequeue. This simple check will solve a possible race
++ * condition if it occurs.
++ */
++ if (skb_queue_len(&ring->skblist) < BRCMF_FLOWRING_LOW)
++ brcmf_flowring_block(flow, flowid, false);
++ }
++ return skb_queue_len(&ring->skblist);
++}
++
++
++struct sk_buff *brcmf_flowring_dequeue(struct brcmf_flowring *flow, u8 flowid)
++{
++ struct brcmf_flowring_ring *ring;
++ struct sk_buff *skb;
++
++ ring = flow->rings[flowid];
++ if (ring->status != RING_OPEN)
++ return NULL;
++
++ skb = skb_dequeue(&ring->skblist);
++
++ if (ring->blocked &&
++ (skb_queue_len(&ring->skblist) < BRCMF_FLOWRING_LOW)) {
++ brcmf_flowring_block(flow, flowid, false);
++ brcmf_dbg(MSGBUF, "Flowcontrol: OPEN for ring %d\n", flowid);
++ }
++
++ return skb;
++}
++
++
++void brcmf_flowring_reinsert(struct brcmf_flowring *flow, u8 flowid,
++ struct sk_buff *skb)
++{
++ struct brcmf_flowring_ring *ring;
++
++ ring = flow->rings[flowid];
++
++ skb_queue_head(&ring->skblist, skb);
++}
++
++
++u32 brcmf_flowring_qlen(struct brcmf_flowring *flow, u8 flowid)
++{
++ struct brcmf_flowring_ring *ring;
++
++ ring = flow->rings[flowid];
++ if (!ring)
++ return 0;
++
++ if (ring->status != RING_OPEN)
++ return 0;
++
++ return skb_queue_len(&ring->skblist);
++}
++
++
++void brcmf_flowring_open(struct brcmf_flowring *flow, u8 flowid)
++{
++ struct brcmf_flowring_ring *ring;
++
++ ring = flow->rings[flowid];
++ if (!ring) {
++ brcmf_err("Ring NULL, for flowid %d\n", flowid);
++ return;
++ }
++
++ ring->status = RING_OPEN;
++}
++
++
++u8 brcmf_flowring_ifidx_get(struct brcmf_flowring *flow, u8 flowid)
++{
++ struct brcmf_flowring_ring *ring;
++ u8 hash_idx;
++
++ ring = flow->rings[flowid];
++ hash_idx = ring->hash_id;
++
++ return flow->hash[hash_idx].ifidx;
++}
++
++
++struct brcmf_flowring *brcmf_flowring_attach(struct device *dev, u16 nrofrings)
++{
++ struct brcmf_flowring *flow;
++ u32 i;
++
++ flow = kzalloc(sizeof(*flow), GFP_KERNEL);
++ if (flow) {
++ flow->dev = dev;
++ flow->nrofrings = nrofrings;
++ spin_lock_init(&flow->block_lock);
++ for (i = 0; i < ARRAY_SIZE(flow->addr_mode); i++)
++ flow->addr_mode[i] = ADDR_INDIRECT;
++ for (i = 0; i < ARRAY_SIZE(flow->hash); i++)
++ flow->hash[i].ifidx = BRCMF_FLOWRING_INVALID_IFIDX;
++ flow->rings = kcalloc(nrofrings, sizeof(*flow->rings),
++ GFP_KERNEL);
++ if (!flow->rings) {
++ kfree(flow);
++ flow = NULL;
++ }
++ }
++
++ return flow;
++}
++
++
++void brcmf_flowring_detach(struct brcmf_flowring *flow)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(flow->dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ struct brcmf_flowring_tdls_entry *search;
++ struct brcmf_flowring_tdls_entry *remove;
++ u8 flowid;
++
++ for (flowid = 0; flowid < flow->nrofrings; flowid++) {
++ if (flow->rings[flowid])
++ brcmf_msgbuf_delete_flowring(drvr, flowid);
++ }
++
++ search = flow->tdls_entry;
++ while (search) {
++ remove = search;
++ search = search->next;
++ kfree(remove);
++ }
++ kfree(flow->rings);
++ kfree(flow);
++}
++
++
++void brcmf_flowring_configure_addr_mode(struct brcmf_flowring *flow, int ifidx,
++ enum proto_addr_mode addr_mode)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(flow->dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ u32 i;
++ u8 flowid;
++
++ if (flow->addr_mode[ifidx] != addr_mode) {
++ for (i = 0; i < ARRAY_SIZE(flow->hash); i++) {
++ if (flow->hash[i].ifidx == ifidx) {
++ flowid = flow->hash[i].flowid;
++ if (flow->rings[flowid]->status != RING_OPEN)
++ continue;
++ flow->rings[flowid]->status = RING_CLOSING;
++ brcmf_msgbuf_delete_flowring(drvr, flowid);
++ }
++ }
++ flow->addr_mode[ifidx] = addr_mode;
++ }
++}
++
++
++void brcmf_flowring_delete_peer(struct brcmf_flowring *flow, int ifidx,
++ u8 peer[ETH_ALEN])
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(flow->dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ struct brcmf_flowring_hash *hash;
++ struct brcmf_flowring_tdls_entry *prev;
++ struct brcmf_flowring_tdls_entry *search;
++ u32 i;
++ u8 flowid;
++ bool sta;
++
++ sta = (flow->addr_mode[ifidx] == ADDR_INDIRECT);
++
++ search = flow->tdls_entry;
++ prev = NULL;
++ while (search) {
++ if (memcmp(search->mac, peer, ETH_ALEN) == 0) {
++ sta = false;
++ break;
++ }
++ prev = search;
++ search = search->next;
++ }
++
++ hash = flow->hash;
++ for (i = 0; i < BRCMF_FLOWRING_HASHSIZE; i++) {
++ if ((sta || (memcmp(hash[i].mac, peer, ETH_ALEN) == 0)) &&
++ (hash[i].ifidx == ifidx)) {
++ flowid = flow->hash[i].flowid;
++ if (flow->rings[flowid]->status == RING_OPEN) {
++ flow->rings[flowid]->status = RING_CLOSING;
++ brcmf_msgbuf_delete_flowring(drvr, flowid);
++ }
++ }
++ }
++
++ if (search) {
++ if (prev)
++ prev->next = search->next;
++ else
++ flow->tdls_entry = search->next;
++ kfree(search);
++ if (flow->tdls_entry == NULL)
++ flow->tdls_active = false;
++ }
++}
++
++
++void brcmf_flowring_add_tdls_peer(struct brcmf_flowring *flow, int ifidx,
++ u8 peer[ETH_ALEN])
++{
++ struct brcmf_flowring_tdls_entry *tdls_entry;
++ struct brcmf_flowring_tdls_entry *search;
++
++ tdls_entry = kzalloc(sizeof(*tdls_entry), GFP_ATOMIC);
++ if (tdls_entry == NULL)
++ return;
++
++ memcpy(tdls_entry->mac, peer, ETH_ALEN);
++ tdls_entry->next = NULL;
++ if (flow->tdls_entry == NULL) {
++ flow->tdls_entry = tdls_entry;
++ } else {
++ search = flow->tdls_entry;
++ if (memcmp(search->mac, peer, ETH_ALEN) == 0)
++ return;
++ while (search->next) {
++ search = search->next;
++ if (memcmp(search->mac, peer, ETH_ALEN) == 0)
++ return;
++ }
++ search->next = tdls_entry;
++ }
++
++ flow->tdls_active = true;
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/flowring.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/flowring.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/flowring.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/flowring.h 2016-06-19 22:11:55.285141319 +0200
+@@ -0,0 +1,84 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_FLOWRING_H
++#define BRCMFMAC_FLOWRING_H
++
++
++#define BRCMF_FLOWRING_HASHSIZE 256
++#define BRCMF_FLOWRING_INVALID_ID 0xFFFFFFFF
++
++
++struct brcmf_flowring_hash {
++ u8 mac[ETH_ALEN];
++ u8 fifo;
++ u8 ifidx;
++ u8 flowid;
++};
++
++enum ring_status {
++ RING_CLOSED,
++ RING_CLOSING,
++ RING_OPEN
++};
++
++struct brcmf_flowring_ring {
++ u8 hash_id;
++ bool blocked;
++ enum ring_status status;
++ struct sk_buff_head skblist;
++};
++
++struct brcmf_flowring_tdls_entry {
++ u8 mac[ETH_ALEN];
++ struct brcmf_flowring_tdls_entry *next;
++};
++
++struct brcmf_flowring {
++ struct device *dev;
++ struct brcmf_flowring_hash hash[BRCMF_FLOWRING_HASHSIZE];
++ struct brcmf_flowring_ring **rings;
++ spinlock_t block_lock;
++ enum proto_addr_mode addr_mode[BRCMF_MAX_IFS];
++ u16 nrofrings;
++ bool tdls_active;
++ struct brcmf_flowring_tdls_entry *tdls_entry;
++};
++
++
++u32 brcmf_flowring_lookup(struct brcmf_flowring *flow, u8 da[ETH_ALEN],
++ u8 prio, u8 ifidx);
++u32 brcmf_flowring_create(struct brcmf_flowring *flow, u8 da[ETH_ALEN],
++ u8 prio, u8 ifidx);
++void brcmf_flowring_delete(struct brcmf_flowring *flow, u8 flowid);
++void brcmf_flowring_open(struct brcmf_flowring *flow, u8 flowid);
++u8 brcmf_flowring_tid(struct brcmf_flowring *flow, u8 flowid);
++u32 brcmf_flowring_enqueue(struct brcmf_flowring *flow, u8 flowid,
++ struct sk_buff *skb);
++struct sk_buff *brcmf_flowring_dequeue(struct brcmf_flowring *flow, u8 flowid);
++void brcmf_flowring_reinsert(struct brcmf_flowring *flow, u8 flowid,
++ struct sk_buff *skb);
++u32 brcmf_flowring_qlen(struct brcmf_flowring *flow, u8 flowid);
++u8 brcmf_flowring_ifidx_get(struct brcmf_flowring *flow, u8 flowid);
++struct brcmf_flowring *brcmf_flowring_attach(struct device *dev, u16 nrofrings);
++void brcmf_flowring_detach(struct brcmf_flowring *flow);
++void brcmf_flowring_configure_addr_mode(struct brcmf_flowring *flow, int ifidx,
++ enum proto_addr_mode addr_mode);
++void brcmf_flowring_delete_peer(struct brcmf_flowring *flow, int ifidx,
++ u8 peer[ETH_ALEN]);
++void brcmf_flowring_add_tdls_peer(struct brcmf_flowring *flow, int ifidx,
++ u8 peer[ETH_ALEN]);
++
++
++#endif /* BRCMFMAC_FLOWRING_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fweh.c 2016-06-19 22:11:55.285141319 +0200
+@@ -18,8 +18,8 @@
+ #include "brcmu_wifi.h"
+ #include "brcmu_utils.h"
+
+-#include "dhd.h"
+-#include "dhd_dbg.h"
++#include "core.h"
++#include "debug.h"
+ #include "tracepoint.h"
+ #include "fwsignal.h"
+ #include "fweh.h"
+@@ -221,10 +221,8 @@
+
+ err = brcmf_fweh_call_event_handler(ifp, emsg->event_code, emsg, data);
+
+- if (ifp && ifevent->action == BRCMF_E_IF_DEL) {
+- brcmf_fws_del_interface(ifp);
+- brcmf_del_if(drvr, ifevent->bssidx);
+- }
++ if (ifp && ifevent->action == BRCMF_E_IF_DEL)
++ brcmf_remove_interface(drvr, ifevent->bssidx);
+ }
+
+ /**
+@@ -299,7 +297,11 @@
+ goto event_free;
+ }
+
+- ifp = drvr->iflist[emsg.bsscfgidx];
++ if ((event->code == BRCMF_E_TDLS_PEER_EVENT) &&
++ (emsg.bsscfgidx == 1))
++ ifp = drvr->iflist[0];
++ else
++ ifp = drvr->iflist[emsg.bsscfgidx];
+ err = brcmf_fweh_call_event_handler(ifp, event->code, &emsg,
+ event->data);
+ if (err) {
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fweh.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fweh.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fweh.h 2016-06-19 22:11:55.285141319 +0200
+@@ -102,6 +102,7 @@
+ BRCMF_ENUM_DEF(DCS_REQUEST, 73) \
+ BRCMF_ENUM_DEF(FIFO_CREDIT_MAP, 74) \
+ BRCMF_ENUM_DEF(ACTION_FRAME_RX, 75) \
++ BRCMF_ENUM_DEF(TDLS_PEER_EVENT, 92) \
+ BRCMF_ENUM_DEF(BCMC_CREDIT_SUPPORT, 127) \
+ BRCMF_ENUM_DEF(PSTA_PRIMARY_INTF_IND, 128)
+
+@@ -155,6 +156,10 @@
+ #define BRCMF_E_REASON_TSPEC_REJECTED 7
+ #define BRCMF_E_REASON_BETTER_AP 8
+
++#define BRCMF_E_REASON_TDLS_PEER_DISCOVERED 0
++#define BRCMF_E_REASON_TDLS_PEER_CONNECTED 1
++#define BRCMF_E_REASON_TDLS_PEER_DISCONNECTED 2
++
+ /* action field values for brcmf_ifevent */
+ #define BRCMF_E_IF_ADD 1
+ #define BRCMF_E_IF_DEL 2
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwil.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwil.c 2016-06-19 22:11:55.285141319 +0200
+@@ -22,9 +22,9 @@
+ #include <linux/netdevice.h>
+ #include <brcmu_utils.h>
+ #include <brcmu_wifi.h>
+-#include "dhd.h"
+-#include "dhd_bus.h"
+-#include "dhd_dbg.h"
++#include "core.h"
++#include "bus.h"
++#include "debug.h"
+ #include "tracepoint.h"
+ #include "fwil.h"
+ #include "proto.h"
+@@ -32,6 +32,76 @@
+
+ #define MAX_HEX_DUMP_LEN 64
+
++#ifdef DEBUG
++static const char * const brcmf_fil_errstr[] = {
++ "BCME_OK",
++ "BCME_ERROR",
++ "BCME_BADARG",
++ "BCME_BADOPTION",
++ "BCME_NOTUP",
++ "BCME_NOTDOWN",
++ "BCME_NOTAP",
++ "BCME_NOTSTA",
++ "BCME_BADKEYIDX",
++ "BCME_RADIOOFF",
++ "BCME_NOTBANDLOCKED",
++ "BCME_NOCLK",
++ "BCME_BADRATESET",
++ "BCME_BADBAND",
++ "BCME_BUFTOOSHORT",
++ "BCME_BUFTOOLONG",
++ "BCME_BUSY",
++ "BCME_NOTASSOCIATED",
++ "BCME_BADSSIDLEN",
++ "BCME_OUTOFRANGECHAN",
++ "BCME_BADCHAN",
++ "BCME_BADADDR",
++ "BCME_NORESOURCE",
++ "BCME_UNSUPPORTED",
++ "BCME_BADLEN",
++ "BCME_NOTREADY",
++ "BCME_EPERM",
++ "BCME_NOMEM",
++ "BCME_ASSOCIATED",
++ "BCME_RANGE",
++ "BCME_NOTFOUND",
++ "BCME_WME_NOT_ENABLED",
++ "BCME_TSPEC_NOTFOUND",
++ "BCME_ACM_NOTSUPPORTED",
++ "BCME_NOT_WME_ASSOCIATION",
++ "BCME_SDIO_ERROR",
++ "BCME_DONGLE_DOWN",
++ "BCME_VERSION",
++ "BCME_TXFAIL",
++ "BCME_RXFAIL",
++ "BCME_NODEVICE",
++ "BCME_NMODE_DISABLED",
++ "BCME_NONRESIDENT",
++ "BCME_SCANREJECT",
++ "BCME_USAGE_ERROR",
++ "BCME_IOCTL_ERROR",
++ "BCME_SERIAL_PORT_ERR",
++ "BCME_DISABLED",
++ "BCME_DECERR",
++ "BCME_ENCERR",
++ "BCME_MICERR",
++ "BCME_REPLAY",
++ "BCME_IE_NOTFOUND",
++};
++
++static const char *brcmf_fil_get_errstr(u32 err)
++{
++ if (err >= ARRAY_SIZE(brcmf_fil_errstr))
++ return "(unknown)";
++
++ return brcmf_fil_errstr[err];
++}
++#else
++static const char *brcmf_fil_get_errstr(u32 err)
++{
++ return "";
++}
++#endif /* DEBUG */
+
+ static s32
+ brcmf_fil_cmd_data(struct brcmf_if *ifp, u32 cmd, void *data, u32 len, bool set)
+@@ -39,7 +109,7 @@
+ struct brcmf_pub *drvr = ifp->drvr;
+ s32 err;
+
+- if (drvr->bus_if->state != BRCMF_BUS_DATA) {
++ if (drvr->bus_if->state != BRCMF_BUS_UP) {
+ brcmf_err("bus is down. we have nothing to do.\n");
+ return -EIO;
+ }
+@@ -52,11 +122,11 @@
+ err = brcmf_proto_query_dcmd(drvr, ifp->ifidx, cmd, data, len);
+
+ if (err >= 0)
+- err = 0;
+- else
+- brcmf_err("Failed err=%d\n", err);
++ return 0;
+
+- return err;
++ brcmf_dbg(FIL, "Failed: %s (%d)\n",
++ brcmf_fil_get_errstr((u32)(-err)), err);
++ return -EBADE;
+ }
+
+ s32
+@@ -66,7 +136,7 @@
+
+ mutex_lock(&ifp->drvr->proto_block);
+
+- brcmf_dbg(FIL, "cmd=%d, len=%d\n", cmd, len);
++ brcmf_dbg(FIL, "ifidx=%d, cmd=%d, len=%d\n", ifp->ifidx, cmd, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+@@ -84,7 +154,7 @@
+ mutex_lock(&ifp->drvr->proto_block);
+ err = brcmf_fil_cmd_data(ifp, cmd, data, len, false);
+
+- brcmf_dbg(FIL, "cmd=%d, len=%d\n", cmd, len);
++ brcmf_dbg(FIL, "ifidx=%d, cmd=%d, len=%d\n", ifp->ifidx, cmd, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+@@ -101,7 +171,7 @@
+ __le32 data_le = cpu_to_le32(data);
+
+ mutex_lock(&ifp->drvr->proto_block);
+- brcmf_dbg(FIL, "cmd=%d, value=%d\n", cmd, data);
++ brcmf_dbg(FIL, "ifidx=%d, cmd=%d, value=%d\n", ifp->ifidx, cmd, data);
+ err = brcmf_fil_cmd_data(ifp, cmd, &data_le, sizeof(data_le), true);
+ mutex_unlock(&ifp->drvr->proto_block);
+
+@@ -118,13 +188,14 @@
+ err = brcmf_fil_cmd_data(ifp, cmd, &data_le, sizeof(data_le), false);
+ mutex_unlock(&ifp->drvr->proto_block);
+ *data = le32_to_cpu(data_le);
+- brcmf_dbg(FIL, "cmd=%d, value=%d\n", cmd, *data);
++ brcmf_dbg(FIL, "ifidx=%d, cmd=%d, value=%d\n", ifp->ifidx, cmd, *data);
+
+ return err;
+ }
+
+ static u32
+-brcmf_create_iovar(char *name, char *data, u32 datalen, char *buf, u32 buflen)
++brcmf_create_iovar(char *name, const char *data, u32 datalen,
++ char *buf, u32 buflen)
+ {
+ u32 len;
+
+@@ -144,7 +215,7 @@
+
+
+ s32
+-brcmf_fil_iovar_data_set(struct brcmf_if *ifp, char *name, void *data,
++brcmf_fil_iovar_data_set(struct brcmf_if *ifp, char *name, const void *data,
+ u32 len)
+ {
+ struct brcmf_pub *drvr = ifp->drvr;
+@@ -153,7 +224,7 @@
+
+ mutex_lock(&drvr->proto_block);
+
+- brcmf_dbg(FIL, "name=%s, len=%d\n", name, len);
++ brcmf_dbg(FIL, "ifidx=%d, name=%s, len=%d\n", ifp->ifidx, name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+@@ -193,7 +264,7 @@
+ brcmf_err("Creating iovar failed\n");
+ }
+
+- brcmf_dbg(FIL, "name=%s, len=%d\n", name, len);
++ brcmf_dbg(FIL, "ifidx=%d, name=%s, len=%d\n", ifp->ifidx, name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+@@ -276,7 +347,8 @@
+
+ mutex_lock(&drvr->proto_block);
+
+- brcmf_dbg(FIL, "bssidx=%d, name=%s, len=%d\n", ifp->bssidx, name, len);
++ brcmf_dbg(FIL, "ifidx=%d, bssidx=%d, name=%s, len=%d\n", ifp->ifidx,
++ ifp->bssidx, name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+@@ -315,7 +387,8 @@
+ err = -EPERM;
+ brcmf_err("Creating bsscfg failed\n");
+ }
+- brcmf_dbg(FIL, "bssidx=%d, name=%s, len=%d\n", ifp->bssidx, name, len);
++ brcmf_dbg(FIL, "ifidx=%d, bssidx=%d, name=%s, len=%d\n", ifp->ifidx,
++ ifp->bssidx, name, len);
+ brcmf_dbg_hex_dump(BRCMF_FIL_ON(), data,
+ min_t(uint, len, MAX_HEX_DUMP_LEN), "data\n");
+
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwil.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwil.h 2016-06-19 22:11:55.285141319 +0200
+@@ -43,6 +43,8 @@
+ #define BRCMF_C_SET_RADIO 38
+ #define BRCMF_C_GET_PHYTYPE 39
+ #define BRCMF_C_SET_KEY 45
++#define BRCMF_C_GET_REGULATORY 46
++#define BRCMF_C_SET_REGULATORY 47
+ #define BRCMF_C_SET_PASSIVE_SCAN 49
+ #define BRCMF_C_SCAN 50
+ #define BRCMF_C_SCAN_RESULTS 51
+@@ -57,9 +59,12 @@
+ #define BRCMF_C_SET_COUNTRY 84
+ #define BRCMF_C_GET_PM 85
+ #define BRCMF_C_SET_PM 86
++#define BRCMF_C_GET_REVINFO 98
+ #define BRCMF_C_GET_CURR_RATESET 114
+ #define BRCMF_C_GET_AP 117
+ #define BRCMF_C_SET_AP 118
++#define BRCMF_C_SET_SCB_AUTHORIZE 121
++#define BRCMF_C_SET_SCB_DEAUTHORIZE 122
+ #define BRCMF_C_GET_RSSI 127
+ #define BRCMF_C_GET_WSEC 133
+ #define BRCMF_C_SET_WSEC 134
+@@ -83,7 +88,7 @@
+ s32 brcmf_fil_cmd_int_set(struct brcmf_if *ifp, u32 cmd, u32 data);
+ s32 brcmf_fil_cmd_int_get(struct brcmf_if *ifp, u32 cmd, u32 *data);
+
+-s32 brcmf_fil_iovar_data_set(struct brcmf_if *ifp, char *name, void *data,
++s32 brcmf_fil_iovar_data_set(struct brcmf_if *ifp, char *name, const void *data,
+ u32 len);
+ s32 brcmf_fil_iovar_data_get(struct brcmf_if *ifp, char *name, void *data,
+ u32 len);
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h 2016-06-19 22:11:55.285141319 +0200
+@@ -48,6 +48,80 @@
+
+ #define BRCMF_MAXRATES_IN_SET 16 /* max # of rates in rateset */
+
++/* OBSS Coex Auto/On/Off */
++#define BRCMF_OBSS_COEX_AUTO (-1)
++#define BRCMF_OBSS_COEX_OFF 0
++#define BRCMF_OBSS_COEX_ON 1
++
++/* WOWL bits */
++/* Wakeup on Magic packet: */
++#define BRCMF_WOWL_MAGIC (1 << 0)
++/* Wakeup on Netpattern */
++#define BRCMF_WOWL_NET (1 << 1)
++/* Wakeup on loss-of-link due to Disassoc/Deauth: */
++#define BRCMF_WOWL_DIS (1 << 2)
++/* Wakeup on retrograde TSF: */
++#define BRCMF_WOWL_RETR (1 << 3)
++/* Wakeup on loss of beacon: */
++#define BRCMF_WOWL_BCN (1 << 4)
++/* Wakeup after test: */
++#define BRCMF_WOWL_TST (1 << 5)
++/* Wakeup after PTK refresh: */
++#define BRCMF_WOWL_M1 (1 << 6)
++/* Wakeup after receipt of EAP-Identity Req: */
++#define BRCMF_WOWL_EAPID (1 << 7)
++/* Wakeind via PME(0) or GPIO(1): */
++#define BRCMF_WOWL_PME_GPIO (1 << 8)
++/* need tkip phase 1 key to be updated by the driver: */
++#define BRCMF_WOWL_NEEDTKIP1 (1 << 9)
++/* enable wakeup if GTK fails: */
++#define BRCMF_WOWL_GTK_FAILURE (1 << 10)
++/* support extended magic packets: */
++#define BRCMF_WOWL_EXTMAGPAT (1 << 11)
++/* support ARP/NS/keepalive offloading: */
++#define BRCMF_WOWL_ARPOFFLOAD (1 << 12)
++/* read protocol version for EAPOL frames: */
++#define BRCMF_WOWL_WPA2 (1 << 13)
++/* If the bit is set, use key rotaton: */
++#define BRCMF_WOWL_KEYROT (1 << 14)
++/* If the bit is set, frm received was bcast frame: */
++#define BRCMF_WOWL_BCAST (1 << 15)
++/* If the bit is set, scan offload is enabled: */
++#define BRCMF_WOWL_SCANOL (1 << 16)
++/* Wakeup on tcpkeep alive timeout: */
++#define BRCMF_WOWL_TCPKEEP_TIME (1 << 17)
++/* Wakeup on mDNS Conflict Resolution: */
++#define BRCMF_WOWL_MDNS_CONFLICT (1 << 18)
++/* Wakeup on mDNS Service Connect: */
++#define BRCMF_WOWL_MDNS_SERVICE (1 << 19)
++/* tcp keepalive got data: */
++#define BRCMF_WOWL_TCPKEEP_DATA (1 << 20)
++/* Firmware died in wowl mode: */
++#define BRCMF_WOWL_FW_HALT (1 << 21)
++/* Enable detection of radio button changes: */
++#define BRCMF_WOWL_ENAB_HWRADIO (1 << 22)
++/* Offloads detected MIC failure(s): */
++#define BRCMF_WOWL_MIC_FAIL (1 << 23)
++/* Wakeup in Unassociated state (Net/Magic Pattern): */
++#define BRCMF_WOWL_UNASSOC (1 << 24)
++/* Wakeup if received matched secured pattern: */
++#define BRCMF_WOWL_SECURE (1 << 25)
++/* Link Down indication in WoWL mode: */
++#define BRCMF_WOWL_LINKDOWN (1 << 31)
++
++#define BRCMF_WOWL_MAXPATTERNS 8
++#define BRCMF_WOWL_MAXPATTERNSIZE 128
++
++#define BRCMF_COUNTRY_BUF_SZ 4
++
++/* join preference types for join_pref iovar */
++enum brcmf_join_pref_types {
++ BRCMF_JOIN_PREF_RSSI = 1,
++ BRCMF_JOIN_PREF_WPA,
++ BRCMF_JOIN_PREF_BAND,
++ BRCMF_JOIN_PREF_RSSI_DELTA,
++};
++
+ enum brcmf_fil_p2p_if_types {
+ BRCMF_FIL_P2P_IF_CLIENT,
+ BRCMF_FIL_P2P_IF_GO,
+@@ -55,6 +129,12 @@
+ BRCMF_FIL_P2P_IF_DEV,
+ };
+
++enum brcmf_wowl_pattern_type {
++ BRCMF_WOWL_PATTERN_TYPE_BITMAP = 0,
++ BRCMF_WOWL_PATTERN_TYPE_ARP,
++ BRCMF_WOWL_PATTERN_TYPE_NA
++};
++
+ struct brcmf_fil_p2p_if_le {
+ u8 addr[ETH_ALEN];
+ __le16 type;
+@@ -87,6 +167,11 @@
+ __le32 enable;
+ };
+
++struct brcmf_fil_bwcap_le {
++ __le32 band;
++ __le32 bw_cap;
++};
++
+ /**
+ * struct tdls_iovar - common structure for tdls iovars.
+ *
+@@ -272,6 +357,22 @@
+ __le16 chanspec_list[1];
+ };
+
++/**
++ * struct join_pref params - parameters for preferred join selection.
++ *
++ * @type: preference type (see enum brcmf_join_pref_types).
++ * @len: length of bytes following (currently always 2).
++ * @rssi_gain: signal gain for selection (only when @type is RSSI_DELTA).
++ * @band: band to which selection preference applies.
++ * This is used if @type is BAND or RSSI_DELTA.
++ */
++struct brcmf_join_pref_params {
++ u8 type;
++ u8 len;
++ u8 rssi_gain;
++ u8 band;
++};
++
+ /* used for join with or without a specific bssid and channel list */
+ struct brcmf_join_params {
+ struct brcmf_ssid_le ssid_le;
+@@ -394,4 +495,89 @@
+ __be32 rate;
+ };
+
++/**
++ * struct brcmf_fil_wowl_pattern_le - wowl pattern configuration struct.
++ *
++ * @cmd: "add", "del" or "clr".
++ * @masksize: Size of the mask in #of bytes
++ * @offset: Pattern byte offset in packet
++ * @patternoffset: Offset of start of pattern. Starting from field masksize.
++ * @patternsize: Size of the pattern itself in #of bytes
++ * @id: id
++ * @reasonsize: Size of the wakeup reason code
++ * @type: Type of pattern (enum brcmf_wowl_pattern_type)
++ */
++struct brcmf_fil_wowl_pattern_le {
++ u8 cmd[4];
++ __le32 masksize;
++ __le32 offset;
++ __le32 patternoffset;
++ __le32 patternsize;
++ __le32 id;
++ __le32 reasonsize;
++ __le32 type;
++ /* u8 mask[] - Mask follows the structure above */
++ /* u8 pattern[] - Pattern follows the mask is at 'patternoffset' */
++};
++
++struct brcmf_mbss_ssid_le {
++ __le32 bsscfgidx;
++ __le32 SSID_len;
++ unsigned char SSID[32];
++};
++
++/**
++ * struct brcmf_fil_country_le - country configuration structure.
++ *
++ * @country_abbrev: null-terminated country code used in the country IE.
++ * @rev: revision specifier for ccode. on set, -1 indicates unspecified.
++ * @ccode: null-terminated built-in country code.
++ */
++struct brcmf_fil_country_le {
++ char country_abbrev[BRCMF_COUNTRY_BUF_SZ];
++ __le32 rev;
++ char ccode[BRCMF_COUNTRY_BUF_SZ];
++};
++
++/**
++ * struct brcmf_rev_info_le - device revision info.
++ *
++ * @vendorid: PCI vendor id.
++ * @deviceid: device id of chip.
++ * @radiorev: radio revision.
++ * @chiprev: chip revision.
++ * @corerev: core revision.
++ * @boardid: board identifier (usu. PCI sub-device id).
++ * @boardvendor: board vendor (usu. PCI sub-vendor id).
++ * @boardrev: board revision.
++ * @driverrev: driver version.
++ * @ucoderev: microcode version.
++ * @bus: bus type.
++ * @chipnum: chip number.
++ * @phytype: phy type.
++ * @phyrev: phy revision.
++ * @anarev: anacore rev.
++ * @chippkg: chip package info.
++ * @nvramrev: nvram revision number.
++ */
++struct brcmf_rev_info_le {
++ __le32 vendorid;
++ __le32 deviceid;
++ __le32 radiorev;
++ __le32 chiprev;
++ __le32 corerev;
++ __le32 boardid;
++ __le32 boardvendor;
++ __le32 boardrev;
++ __le32 driverrev;
++ __le32 ucoderev;
++ __le32 bus;
++ __le32 chipnum;
++ __le32 phytype;
++ __le32 phyrev;
++ __le32 anarev;
++ __le32 chippkg;
++ __le32 nvramrev;
++};
++
+ #endif /* FWIL_TYPES_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/fwsignal.c 2016-06-19 22:11:55.285141319 +0200
+@@ -26,15 +26,15 @@
+
+ #include <brcmu_utils.h>
+ #include <brcmu_wifi.h>
+-#include "dhd.h"
+-#include "dhd_dbg.h"
+-#include "dhd_bus.h"
++#include "core.h"
++#include "debug.h"
++#include "bus.h"
+ #include "fwil.h"
+ #include "fwil_types.h"
+ #include "fweh.h"
+ #include "fwsignal.h"
+ #include "p2p.h"
+-#include "wl_cfg80211.h"
++#include "cfg80211.h"
+ #include "proto.h"
+
+ /**
+@@ -454,6 +454,34 @@
+ struct brcmf_fws_mac_descriptor other;
+ };
+
++struct brcmf_fws_stats {
++ u32 tlv_parse_failed;
++ u32 tlv_invalid_type;
++ u32 header_only_pkt;
++ u32 header_pulls;
++ u32 pkt2bus;
++ u32 send_pkts[5];
++ u32 requested_sent[5];
++ u32 generic_error;
++ u32 mac_update_failed;
++ u32 mac_ps_update_failed;
++ u32 if_update_failed;
++ u32 packet_request_failed;
++ u32 credit_request_failed;
++ u32 rollback_success;
++ u32 rollback_failed;
++ u32 delayq_full_error;
++ u32 supprq_full_error;
++ u32 txs_indicate;
++ u32 txs_discard;
++ u32 txs_supp_core;
++ u32 txs_supp_ps;
++ u32 txs_tossed;
++ u32 txs_host_tossed;
++ u32 bus_flow_block;
++ u32 fws_flow_block;
++};
++
+ struct brcmf_fws_info {
+ struct brcmf_pub *drvr;
+ spinlock_t spinlock;
+@@ -476,6 +504,7 @@
+ bool bus_flow_blocked;
+ bool creditmap_received;
+ u8 mode;
++ bool avoid_queueing;
+ };
+
+ /*
+@@ -606,7 +635,7 @@
+ return 0;
+ }
+
+-static int brcmf_fws_hanger_poppkt(struct brcmf_fws_hanger *h,
++static inline int brcmf_fws_hanger_poppkt(struct brcmf_fws_hanger *h,
+ u32 slot_id, struct sk_buff **pktout,
+ bool remove_item)
+ {
+@@ -1369,13 +1398,12 @@
+ }
+
+ static int brcmf_fws_txstatus_suppressed(struct brcmf_fws_info *fws, int fifo,
+- struct sk_buff *skb, u32 genbit,
+- u16 seq)
++ struct sk_buff *skb, u8 ifidx,
++ u32 genbit, u16 seq)
+ {
+ struct brcmf_fws_mac_descriptor *entry = brcmf_skbcb(skb)->mac;
+ u32 hslot;
+ int ret;
+- u8 ifidx;
+
+ hslot = brcmf_skb_htod_tag_get_field(skb, HSLOT);
+
+@@ -1389,29 +1417,21 @@
+
+ entry->generation = genbit;
+
+- ret = brcmf_proto_hdrpull(fws->drvr, false, &ifidx, skb);
+- if (ret == 0) {
+- brcmf_skb_htod_tag_set_field(skb, GENERATION, genbit);
+- brcmf_skbcb(skb)->htod_seq = seq;
+- if (brcmf_skb_htod_seq_get_field(skb, FROMFW)) {
+- brcmf_skb_htod_seq_set_field(skb, FROMDRV, 1);
+- brcmf_skb_htod_seq_set_field(skb, FROMFW, 0);
+- } else {
+- brcmf_skb_htod_seq_set_field(skb, FROMDRV, 0);
+- }
+- ret = brcmf_fws_enq(fws, BRCMF_FWS_SKBSTATE_SUPPRESSED, fifo,
+- skb);
++ brcmf_skb_htod_tag_set_field(skb, GENERATION, genbit);
++ brcmf_skbcb(skb)->htod_seq = seq;
++ if (brcmf_skb_htod_seq_get_field(skb, FROMFW)) {
++ brcmf_skb_htod_seq_set_field(skb, FROMDRV, 1);
++ brcmf_skb_htod_seq_set_field(skb, FROMFW, 0);
++ } else {
++ brcmf_skb_htod_seq_set_field(skb, FROMDRV, 0);
+ }
++ ret = brcmf_fws_enq(fws, BRCMF_FWS_SKBSTATE_SUPPRESSED, fifo, skb);
+
+ if (ret != 0) {
+- /* suppress q is full or hdrpull failed, drop this packet */
+- brcmf_fws_hanger_poppkt(&fws->hanger, hslot, &skb,
+- true);
++ /* suppress q is full drop this packet */
++ brcmf_fws_hanger_poppkt(&fws->hanger, hslot, &skb, true);
+ } else {
+- /*
+- * Mark suppressed to avoid a double free during
+- * wlfc cleanup
+- */
++ /* Mark suppressed to avoid a double free during wlfc cleanup */
+ brcmf_fws_hanger_mark_suppressed(&fws->hanger, hslot);
+ }
+
+@@ -1428,6 +1448,7 @@
+ struct sk_buff *skb;
+ struct brcmf_skbuff_cb *skcb;
+ struct brcmf_fws_mac_descriptor *entry = NULL;
++ u8 ifidx;
+
+ brcmf_dbg(DATA, "flags %d\n", flags);
+
+@@ -1476,12 +1497,15 @@
+ }
+ brcmf_fws_macdesc_return_req_credit(skb);
+
++ if (brcmf_proto_hdrpull(fws->drvr, false, &ifidx, skb)) {
++ brcmu_pkt_buf_free_skb(skb);
++ return -EINVAL;
++ }
+ if (!remove_from_hanger)
+- ret = brcmf_fws_txstatus_suppressed(fws, fifo, skb, genbit,
+- seq);
+-
++ ret = brcmf_fws_txstatus_suppressed(fws, fifo, skb, ifidx,
++ genbit, seq);
+ if (remove_from_hanger || ret)
+- brcmf_txfinalize(fws->drvr, skb, true);
++ brcmf_txfinalize(fws->drvr, skb, ifidx, true);
+
+ return 0;
+ }
+@@ -1612,7 +1636,7 @@
+ if (!signal_len)
+ return 0;
+ /* if flow control disabled, skip to packet data and leave */
+- if (!fws->fw_signals) {
++ if ((!fws) || (!fws->fw_signals)) {
+ skb_pull(skb, signal_len);
+ return 0;
+ }
+@@ -1868,7 +1892,7 @@
+ struct ethhdr *eh = (struct ethhdr *)(skb->data);
+ int fifo = BRCMF_FWS_FIFO_BCMC;
+ bool multicast = is_multicast_ether_addr(eh->h_dest);
+- bool pae = eh->h_proto == htons(ETH_P_PAE);
++ int rc = 0;
+
+ brcmf_dbg(DATA, "tx proto=0x%X\n", ntohs(eh->h_proto));
+ /* determine the priority */
+@@ -1876,8 +1900,13 @@
+ skb->priority = cfg80211_classify8021d(skb, NULL);
+
+ drvr->tx_multicast += !!multicast;
+- if (pae)
+- atomic_inc(&ifp->pend_8021x_cnt);
++
++ if (fws->avoid_queueing) {
++ rc = brcmf_proto_txdata(drvr, ifp->ifidx, 0, skb);
++ if (rc < 0)
++ brcmf_txfinalize(drvr, skb, ifp->ifidx, false);
++ return rc;
++ }
+
+ /* set control buffer information */
+ skcb->if_flags = 0;
+@@ -1899,15 +1928,12 @@
+ brcmf_fws_schedule_deq(fws);
+ } else {
+ brcmf_err("drop skb: no hanger slot\n");
+- if (pae) {
+- atomic_dec(&ifp->pend_8021x_cnt);
+- if (waitqueue_active(&ifp->pend_8021x_wait))
+- wake_up(&ifp->pend_8021x_wait);
+- }
+- brcmu_pkt_buf_free_skb(skb);
++ brcmf_txfinalize(drvr, skb, ifp->ifidx, false);
++ rc = -ENOMEM;
+ }
+ brcmf_fws_unlock(fws);
+- return 0;
++
++ return rc;
+ }
+
+ void brcmf_fws_reset_interface(struct brcmf_if *ifp)
+@@ -1982,7 +2008,8 @@
+ ret = brcmf_proto_txdata(drvr, ifidx, 0, skb);
+ brcmf_fws_lock(fws);
+ if (ret < 0)
+- brcmf_txfinalize(drvr, skb, false);
++ brcmf_txfinalize(drvr, skb, ifidx,
++ false);
+ if (fws->bus_flow_blocked)
+ break;
+ }
+@@ -2018,6 +2045,75 @@
+ brcmf_fws_unlock(fws);
+ }
+
++#ifdef DEBUG
++static int brcmf_debugfs_fws_stats_read(struct seq_file *seq, void *data)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
++ struct brcmf_fws_stats *fwstats = &bus_if->drvr->fws->stats;
++
++ seq_printf(seq,
++ "header_pulls: %u\n"
++ "header_only_pkt: %u\n"
++ "tlv_parse_failed: %u\n"
++ "tlv_invalid_type: %u\n"
++ "mac_update_fails: %u\n"
++ "ps_update_fails: %u\n"
++ "if_update_fails: %u\n"
++ "pkt2bus: %u\n"
++ "generic_error: %u\n"
++ "rollback_success: %u\n"
++ "rollback_failed: %u\n"
++ "delayq_full: %u\n"
++ "supprq_full: %u\n"
++ "txs_indicate: %u\n"
++ "txs_discard: %u\n"
++ "txs_suppr_core: %u\n"
++ "txs_suppr_ps: %u\n"
++ "txs_tossed: %u\n"
++ "txs_host_tossed: %u\n"
++ "bus_flow_block: %u\n"
++ "fws_flow_block: %u\n"
++ "send_pkts: BK:%u BE:%u VO:%u VI:%u BCMC:%u\n"
++ "requested_sent: BK:%u BE:%u VO:%u VI:%u BCMC:%u\n",
++ fwstats->header_pulls,
++ fwstats->header_only_pkt,
++ fwstats->tlv_parse_failed,
++ fwstats->tlv_invalid_type,
++ fwstats->mac_update_failed,
++ fwstats->mac_ps_update_failed,
++ fwstats->if_update_failed,
++ fwstats->pkt2bus,
++ fwstats->generic_error,
++ fwstats->rollback_success,
++ fwstats->rollback_failed,
++ fwstats->delayq_full_error,
++ fwstats->supprq_full_error,
++ fwstats->txs_indicate,
++ fwstats->txs_discard,
++ fwstats->txs_supp_core,
++ fwstats->txs_supp_ps,
++ fwstats->txs_tossed,
++ fwstats->txs_host_tossed,
++ fwstats->bus_flow_block,
++ fwstats->fws_flow_block,
++ fwstats->send_pkts[0], fwstats->send_pkts[1],
++ fwstats->send_pkts[2], fwstats->send_pkts[3],
++ fwstats->send_pkts[4],
++ fwstats->requested_sent[0],
++ fwstats->requested_sent[1],
++ fwstats->requested_sent[2],
++ fwstats->requested_sent[3],
++ fwstats->requested_sent[4]);
++
++ return 0;
++}
++#else
++static int brcmf_debugfs_fws_stats_read(struct seq_file *seq, void *data)
++{
++ return 0;
++}
++#endif
++
+ int brcmf_fws_init(struct brcmf_pub *drvr)
+ {
+ struct brcmf_fws_info *fws;
+@@ -2039,6 +2135,13 @@
+ fws->drvr = drvr;
+ fws->fcmode = fcmode;
+
++ if ((drvr->bus_if->always_use_fws_queue == false) &&
++ (fcmode == BRCMF_FWS_FCMODE_NONE)) {
++ fws->avoid_queueing = true;
++ brcmf_dbg(INFO, "FWS queueing will be avoided\n");
++ return 0;
++ }
++
+ fws->fws_wq = create_singlethread_workqueue("brcmf_fws_wq");
+ if (fws->fws_wq == NULL) {
+ brcmf_err("workqueue creation failed\n");
+@@ -2101,7 +2204,8 @@
+ BRCMF_FWS_PSQ_LEN);
+
+ /* create debugfs file for statistics */
+- brcmf_debugfs_create_fws_stats(drvr, &fws->stats);
++ brcmf_debugfs_add_entry(drvr, "fws_stats",
++ brcmf_debugfs_fws_stats_read);
+
+ brcmf_dbg(INFO, "%s bdcv2 tlv signaling [%x]\n",
+ fws->fw_signals ? "enabled" : "disabled", tlv);
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/Makefile linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/Makefile
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/Makefile 2016-06-19 22:11:55.285141319 +0200
+@@ -23,24 +23,35 @@
+
+ obj-$(CONFIG_BRCMFMAC) += brcmfmac.o
+ brcmfmac-objs += \
+- wl_cfg80211.o \
++ cfg80211.o \
++ chip.o \
+ fwil.o \
+ fweh.o \
+ fwsignal.o \
+ p2p.o \
+ proto.o \
+- bcdc.o \
+- dhd_common.o \
+- dhd_linux.o \
+- nvram.o \
+- btcoex.o
++ common.o \
++ core.o \
++ firmware.o \
++ feature.o \
++ btcoex.o \
++ vendor.o
++brcmfmac-$(CONFIG_BRCMFMAC_PROTO_BCDC) += \
++ bcdc.o
++brcmfmac-$(CONFIG_BRCMFMAC_PROTO_MSGBUF) += \
++ commonring.o \
++ flowring.o \
++ msgbuf.o
+ brcmfmac-$(CONFIG_BRCMFMAC_SDIO) += \
+- dhd_sdio.o \
+- bcmsdh.o \
+- sdio_chip.o
++ sdio.o \
++ bcmsdh.o
+ brcmfmac-$(CONFIG_BRCMFMAC_USB) += \
+ usb.o
++brcmfmac-$(CONFIG_BRCMFMAC_PCIE) += \
++ pcie.o
+ brcmfmac-$(CONFIG_BRCMDBG) += \
+- dhd_dbg.o
++ debug.o
+ brcmfmac-$(CONFIG_BRCM_TRACING) += \
+ tracepoint.o
++brcmfmac-$(CONFIG_OF) += \
++ of.o
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.c 2016-06-19 22:11:55.285141319 +0200
+@@ -0,0 +1,1502 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++/*******************************************************************************
++ * Communicates with the dongle by using dcmd codes.
++ * For certain dcmd codes, the dongle interprets string data from the host.
++ ******************************************************************************/
++
++#include <linux/types.h>
++#include <linux/netdevice.h>
++
++#include <brcmu_utils.h>
++#include <brcmu_wifi.h>
++
++#include "core.h"
++#include "debug.h"
++#include "proto.h"
++#include "msgbuf.h"
++#include "commonring.h"
++#include "flowring.h"
++#include "bus.h"
++#include "tracepoint.h"
++
++
++#define MSGBUF_IOCTL_RESP_TIMEOUT 2000
++
++#define MSGBUF_TYPE_GEN_STATUS 0x1
++#define MSGBUF_TYPE_RING_STATUS 0x2
++#define MSGBUF_TYPE_FLOW_RING_CREATE 0x3
++#define MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT 0x4
++#define MSGBUF_TYPE_FLOW_RING_DELETE 0x5
++#define MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT 0x6
++#define MSGBUF_TYPE_FLOW_RING_FLUSH 0x7
++#define MSGBUF_TYPE_FLOW_RING_FLUSH_CMPLT 0x8
++#define MSGBUF_TYPE_IOCTLPTR_REQ 0x9
++#define MSGBUF_TYPE_IOCTLPTR_REQ_ACK 0xA
++#define MSGBUF_TYPE_IOCTLRESP_BUF_POST 0xB
++#define MSGBUF_TYPE_IOCTL_CMPLT 0xC
++#define MSGBUF_TYPE_EVENT_BUF_POST 0xD
++#define MSGBUF_TYPE_WL_EVENT 0xE
++#define MSGBUF_TYPE_TX_POST 0xF
++#define MSGBUF_TYPE_TX_STATUS 0x10
++#define MSGBUF_TYPE_RXBUF_POST 0x11
++#define MSGBUF_TYPE_RX_CMPLT 0x12
++#define MSGBUF_TYPE_LPBK_DMAXFER 0x13
++#define MSGBUF_TYPE_LPBK_DMAXFER_CMPLT 0x14
++
++#define NR_TX_PKTIDS 2048
++#define NR_RX_PKTIDS 1024
++
++#define BRCMF_IOCTL_REQ_PKTID 0xFFFE
++
++#define BRCMF_MSGBUF_MAX_PKT_SIZE 2048
++#define BRCMF_MSGBUF_RXBUFPOST_THRESHOLD 32
++#define BRCMF_MSGBUF_MAX_IOCTLRESPBUF_POST 8
++#define BRCMF_MSGBUF_MAX_EVENTBUF_POST 8
++
++#define BRCMF_MSGBUF_PKT_FLAGS_FRAME_802_3 0x01
++#define BRCMF_MSGBUF_PKT_FLAGS_PRIO_SHIFT 5
++
++#define BRCMF_MSGBUF_TX_FLUSH_CNT1 32
++#define BRCMF_MSGBUF_TX_FLUSH_CNT2 96
++
++#define BRCMF_MSGBUF_DELAY_TXWORKER_THRS 96
++#define BRCMF_MSGBUF_TRICKLE_TXWORKER_THRS 32
++
++struct msgbuf_common_hdr {
++ u8 msgtype;
++ u8 ifidx;
++ u8 flags;
++ u8 rsvd0;
++ __le32 request_id;
++};
++
++struct msgbuf_buf_addr {
++ __le32 low_addr;
++ __le32 high_addr;
++};
++
++struct msgbuf_ioctl_req_hdr {
++ struct msgbuf_common_hdr msg;
++ __le32 cmd;
++ __le16 trans_id;
++ __le16 input_buf_len;
++ __le16 output_buf_len;
++ __le16 rsvd0[3];
++ struct msgbuf_buf_addr req_buf_addr;
++ __le32 rsvd1[2];
++};
++
++struct msgbuf_tx_msghdr {
++ struct msgbuf_common_hdr msg;
++ u8 txhdr[ETH_HLEN];
++ u8 flags;
++ u8 seg_cnt;
++ struct msgbuf_buf_addr metadata_buf_addr;
++ struct msgbuf_buf_addr data_buf_addr;
++ __le16 metadata_buf_len;
++ __le16 data_len;
++ __le32 rsvd0;
++};
++
++struct msgbuf_rx_bufpost {
++ struct msgbuf_common_hdr msg;
++ __le16 metadata_buf_len;
++ __le16 data_buf_len;
++ __le32 rsvd0;
++ struct msgbuf_buf_addr metadata_buf_addr;
++ struct msgbuf_buf_addr data_buf_addr;
++};
++
++struct msgbuf_rx_ioctl_resp_or_event {
++ struct msgbuf_common_hdr msg;
++ __le16 host_buf_len;
++ __le16 rsvd0[3];
++ struct msgbuf_buf_addr host_buf_addr;
++ __le32 rsvd1[4];
++};
++
++struct msgbuf_completion_hdr {
++ __le16 status;
++ __le16 flow_ring_id;
++};
++
++struct msgbuf_rx_event {
++ struct msgbuf_common_hdr msg;
++ struct msgbuf_completion_hdr compl_hdr;
++ __le16 event_data_len;
++ __le16 seqnum;
++ __le16 rsvd0[4];
++};
++
++struct msgbuf_ioctl_resp_hdr {
++ struct msgbuf_common_hdr msg;
++ struct msgbuf_completion_hdr compl_hdr;
++ __le16 resp_len;
++ __le16 trans_id;
++ __le32 cmd;
++ __le32 rsvd0;
++};
++
++struct msgbuf_tx_status {
++ struct msgbuf_common_hdr msg;
++ struct msgbuf_completion_hdr compl_hdr;
++ __le16 metadata_len;
++ __le16 tx_status;
++};
++
++struct msgbuf_rx_complete {
++ struct msgbuf_common_hdr msg;
++ struct msgbuf_completion_hdr compl_hdr;
++ __le16 metadata_len;
++ __le16 data_len;
++ __le16 data_offset;
++ __le16 flags;
++ __le32 rx_status_0;
++ __le32 rx_status_1;
++ __le32 rsvd0;
++};
++
++struct msgbuf_tx_flowring_create_req {
++ struct msgbuf_common_hdr msg;
++ u8 da[ETH_ALEN];
++ u8 sa[ETH_ALEN];
++ u8 tid;
++ u8 if_flags;
++ __le16 flow_ring_id;
++ u8 tc;
++ u8 priority;
++ __le16 int_vector;
++ __le16 max_items;
++ __le16 len_item;
++ struct msgbuf_buf_addr flow_ring_addr;
++};
++
++struct msgbuf_tx_flowring_delete_req {
++ struct msgbuf_common_hdr msg;
++ __le16 flow_ring_id;
++ __le16 reason;
++ __le32 rsvd0[7];
++};
++
++struct msgbuf_flowring_create_resp {
++ struct msgbuf_common_hdr msg;
++ struct msgbuf_completion_hdr compl_hdr;
++ __le32 rsvd0[3];
++};
++
++struct msgbuf_flowring_delete_resp {
++ struct msgbuf_common_hdr msg;
++ struct msgbuf_completion_hdr compl_hdr;
++ __le32 rsvd0[3];
++};
++
++struct msgbuf_flowring_flush_resp {
++ struct msgbuf_common_hdr msg;
++ struct msgbuf_completion_hdr compl_hdr;
++ __le32 rsvd0[3];
++};
++
++struct brcmf_msgbuf_work_item {
++ struct list_head queue;
++ u32 flowid;
++ int ifidx;
++ u8 sa[ETH_ALEN];
++ u8 da[ETH_ALEN];
++};
++
++struct brcmf_msgbuf {
++ struct brcmf_pub *drvr;
++
++ struct brcmf_commonring **commonrings;
++ struct brcmf_commonring **flowrings;
++ dma_addr_t *flowring_dma_handle;
++ u16 nrof_flowrings;
++
++ u16 rx_dataoffset;
++ u32 max_rxbufpost;
++ u16 rx_metadata_offset;
++ u32 rxbufpost;
++
++ u32 max_ioctlrespbuf;
++ u32 cur_ioctlrespbuf;
++ u32 max_eventbuf;
++ u32 cur_eventbuf;
++
++ void *ioctbuf;
++ dma_addr_t ioctbuf_handle;
++ u32 ioctbuf_phys_hi;
++ u32 ioctbuf_phys_lo;
++ int ioctl_resp_status;
++ u32 ioctl_resp_ret_len;
++ u32 ioctl_resp_pktid;
++
++ u16 data_seq_no;
++ u16 ioctl_seq_no;
++ u32 reqid;
++ wait_queue_head_t ioctl_resp_wait;
++ bool ctl_completed;
++
++ struct brcmf_msgbuf_pktids *tx_pktids;
++ struct brcmf_msgbuf_pktids *rx_pktids;
++ struct brcmf_flowring *flow;
++
++ struct workqueue_struct *txflow_wq;
++ struct work_struct txflow_work;
++ unsigned long *flow_map;
++ unsigned long *txstatus_done_map;
++
++ struct work_struct flowring_work;
++ spinlock_t flowring_work_lock;
++ struct list_head work_queue;
++};
++
++struct brcmf_msgbuf_pktid {
++ atomic_t allocated;
++ u16 data_offset;
++ struct sk_buff *skb;
++ dma_addr_t physaddr;
++};
++
++struct brcmf_msgbuf_pktids {
++ u32 array_size;
++ u32 last_allocated_idx;
++ enum dma_data_direction direction;
++ struct brcmf_msgbuf_pktid *array;
++};
++
++static void brcmf_msgbuf_rxbuf_ioctlresp_post(struct brcmf_msgbuf *msgbuf);
++
++
++static struct brcmf_msgbuf_pktids *
++brcmf_msgbuf_init_pktids(u32 nr_array_entries,
++ enum dma_data_direction direction)
++{
++ struct brcmf_msgbuf_pktid *array;
++ struct brcmf_msgbuf_pktids *pktids;
++
++ array = kcalloc(nr_array_entries, sizeof(*array), GFP_KERNEL);
++ if (!array)
++ return NULL;
++
++ pktids = kzalloc(sizeof(*pktids), GFP_KERNEL);
++ if (!pktids) {
++ kfree(array);
++ return NULL;
++ }
++ pktids->array = array;
++ pktids->array_size = nr_array_entries;
++
++ return pktids;
++}
++
++
++static int
++brcmf_msgbuf_alloc_pktid(struct device *dev,
++ struct brcmf_msgbuf_pktids *pktids,
++ struct sk_buff *skb, u16 data_offset,
++ dma_addr_t *physaddr, u32 *idx)
++{
++ struct brcmf_msgbuf_pktid *array;
++ u32 count;
++
++ array = pktids->array;
++
++ *physaddr = dma_map_single(dev, skb->data + data_offset,
++ skb->len - data_offset, pktids->direction);
++
++ if (dma_mapping_error(dev, *physaddr)) {
++ brcmf_err("dma_map_single failed !!\n");
++ return -ENOMEM;
++ }
++
++ *idx = pktids->last_allocated_idx;
++
++ count = 0;
++ do {
++ (*idx)++;
++ if (*idx == pktids->array_size)
++ *idx = 0;
++ if (array[*idx].allocated.counter == 0)
++ if (atomic_cmpxchg(&array[*idx].allocated, 0, 1) == 0)
++ break;
++ count++;
++ } while (count < pktids->array_size);
++
++ if (count == pktids->array_size)
++ return -ENOMEM;
++
++ array[*idx].data_offset = data_offset;
++ array[*idx].physaddr = *physaddr;
++ array[*idx].skb = skb;
++
++ pktids->last_allocated_idx = *idx;
++
++ return 0;
++}
++
++
++static struct sk_buff *
++brcmf_msgbuf_get_pktid(struct device *dev, struct brcmf_msgbuf_pktids *pktids,
++ u32 idx)
++{
++ struct brcmf_msgbuf_pktid *pktid;
++ struct sk_buff *skb;
++
++ if (idx >= pktids->array_size) {
++ brcmf_err("Invalid packet id %d (max %d)\n", idx,
++ pktids->array_size);
++ return NULL;
++ }
++ if (pktids->array[idx].allocated.counter) {
++ pktid = &pktids->array[idx];
++ dma_unmap_single(dev, pktid->physaddr,
++ pktid->skb->len - pktid->data_offset,
++ pktids->direction);
++ skb = pktid->skb;
++ pktid->allocated.counter = 0;
++ return skb;
++ } else {
++ brcmf_err("Invalid packet id %d (not in use)\n", idx);
++ }
++
++ return NULL;
++}
++
++
++static void
++brcmf_msgbuf_release_array(struct device *dev,
++ struct brcmf_msgbuf_pktids *pktids)
++{
++ struct brcmf_msgbuf_pktid *array;
++ struct brcmf_msgbuf_pktid *pktid;
++ u32 count;
++
++ array = pktids->array;
++ count = 0;
++ do {
++ if (array[count].allocated.counter) {
++ pktid = &array[count];
++ dma_unmap_single(dev, pktid->physaddr,
++ pktid->skb->len - pktid->data_offset,
++ pktids->direction);
++ brcmu_pkt_buf_free_skb(pktid->skb);
++ }
++ count++;
++ } while (count < pktids->array_size);
++
++ kfree(array);
++ kfree(pktids);
++}
++
++
++static void brcmf_msgbuf_release_pktids(struct brcmf_msgbuf *msgbuf)
++{
++ if (msgbuf->rx_pktids)
++ brcmf_msgbuf_release_array(msgbuf->drvr->bus_if->dev,
++ msgbuf->rx_pktids);
++ if (msgbuf->tx_pktids)
++ brcmf_msgbuf_release_array(msgbuf->drvr->bus_if->dev,
++ msgbuf->tx_pktids);
++}
++
++
++static int brcmf_msgbuf_tx_ioctl(struct brcmf_pub *drvr, int ifidx,
++ uint cmd, void *buf, uint len)
++{
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++ struct brcmf_commonring *commonring;
++ struct msgbuf_ioctl_req_hdr *request;
++ u16 buf_len;
++ void *ret_ptr;
++ int err;
++
++ commonring = msgbuf->commonrings[BRCMF_H2D_MSGRING_CONTROL_SUBMIT];
++ brcmf_commonring_lock(commonring);
++ ret_ptr = brcmf_commonring_reserve_for_write(commonring);
++ if (!ret_ptr) {
++ brcmf_err("Failed to reserve space in commonring\n");
++ brcmf_commonring_unlock(commonring);
++ return -ENOMEM;
++ }
++
++ msgbuf->reqid++;
++
++ request = (struct msgbuf_ioctl_req_hdr *)ret_ptr;
++ request->msg.msgtype = MSGBUF_TYPE_IOCTLPTR_REQ;
++ request->msg.ifidx = (u8)ifidx;
++ request->msg.flags = 0;
++ request->msg.request_id = cpu_to_le32(BRCMF_IOCTL_REQ_PKTID);
++ request->cmd = cpu_to_le32(cmd);
++ request->output_buf_len = cpu_to_le16(len);
++ request->trans_id = cpu_to_le16(msgbuf->reqid);
++
++ buf_len = min_t(u16, len, BRCMF_TX_IOCTL_MAX_MSG_SIZE);
++ request->input_buf_len = cpu_to_le16(buf_len);
++ request->req_buf_addr.high_addr = cpu_to_le32(msgbuf->ioctbuf_phys_hi);
++ request->req_buf_addr.low_addr = cpu_to_le32(msgbuf->ioctbuf_phys_lo);
++ if (buf)
++ memcpy(msgbuf->ioctbuf, buf, buf_len);
++ else
++ memset(msgbuf->ioctbuf, 0, buf_len);
++
++ err = brcmf_commonring_write_complete(commonring);
++ brcmf_commonring_unlock(commonring);
++
++ return err;
++}
++
++
++static int brcmf_msgbuf_ioctl_resp_wait(struct brcmf_msgbuf *msgbuf)
++{
++ return wait_event_timeout(msgbuf->ioctl_resp_wait,
++ msgbuf->ctl_completed,
++ msecs_to_jiffies(MSGBUF_IOCTL_RESP_TIMEOUT));
++}
++
++
++static void brcmf_msgbuf_ioctl_resp_wake(struct brcmf_msgbuf *msgbuf)
++{
++ msgbuf->ctl_completed = true;
++ if (waitqueue_active(&msgbuf->ioctl_resp_wait))
++ wake_up(&msgbuf->ioctl_resp_wait);
++}
++
++
++static int brcmf_msgbuf_query_dcmd(struct brcmf_pub *drvr, int ifidx,
++ uint cmd, void *buf, uint len)
++{
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++ struct sk_buff *skb = NULL;
++ int timeout;
++ int err;
++
++ brcmf_dbg(MSGBUF, "ifidx=%d, cmd=%d, len=%d\n", ifidx, cmd, len);
++ msgbuf->ctl_completed = false;
++ err = brcmf_msgbuf_tx_ioctl(drvr, ifidx, cmd, buf, len);
++ if (err)
++ return err;
++
++ timeout = brcmf_msgbuf_ioctl_resp_wait(msgbuf);
++ if (!timeout) {
++ brcmf_err("Timeout on response for query command\n");
++ return -EIO;
++ }
++
++ skb = brcmf_msgbuf_get_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->rx_pktids,
++ msgbuf->ioctl_resp_pktid);
++ if (msgbuf->ioctl_resp_ret_len != 0) {
++ if (!skb)
++ return -EBADF;
++
++ memcpy(buf, skb->data, (len < msgbuf->ioctl_resp_ret_len) ?
++ len : msgbuf->ioctl_resp_ret_len);
++ }
++ brcmu_pkt_buf_free_skb(skb);
++
++ return msgbuf->ioctl_resp_status;
++}
++
++
++static int brcmf_msgbuf_set_dcmd(struct brcmf_pub *drvr, int ifidx,
++ uint cmd, void *buf, uint len)
++{
++ return brcmf_msgbuf_query_dcmd(drvr, ifidx, cmd, buf, len);
++}
++
++
++static int brcmf_msgbuf_hdrpull(struct brcmf_pub *drvr, bool do_fws,
++ u8 *ifidx, struct sk_buff *skb)
++{
++ return -ENODEV;
++}
++
++
++static void
++brcmf_msgbuf_remove_flowring(struct brcmf_msgbuf *msgbuf, u16 flowid)
++{
++ u32 dma_sz;
++ void *dma_buf;
++
++ brcmf_dbg(MSGBUF, "Removing flowring %d\n", flowid);
++
++ dma_sz = BRCMF_H2D_TXFLOWRING_MAX_ITEM * BRCMF_H2D_TXFLOWRING_ITEMSIZE;
++ dma_buf = msgbuf->flowrings[flowid]->buf_addr;
++ dma_free_coherent(msgbuf->drvr->bus_if->dev, dma_sz, dma_buf,
++ msgbuf->flowring_dma_handle[flowid]);
++
++ brcmf_flowring_delete(msgbuf->flow, flowid);
++}
++
++
++static struct brcmf_msgbuf_work_item *
++brcmf_msgbuf_dequeue_work(struct brcmf_msgbuf *msgbuf)
++{
++ struct brcmf_msgbuf_work_item *work = NULL;
++ ulong flags;
++
++ spin_lock_irqsave(&msgbuf->flowring_work_lock, flags);
++ if (!list_empty(&msgbuf->work_queue)) {
++ work = list_first_entry(&msgbuf->work_queue,
++ struct brcmf_msgbuf_work_item, queue);
++ list_del(&work->queue);
++ }
++ spin_unlock_irqrestore(&msgbuf->flowring_work_lock, flags);
++
++ return work;
++}
++
++
++static u32
++brcmf_msgbuf_flowring_create_worker(struct brcmf_msgbuf *msgbuf,
++ struct brcmf_msgbuf_work_item *work)
++{
++ struct msgbuf_tx_flowring_create_req *create;
++ struct brcmf_commonring *commonring;
++ void *ret_ptr;
++ u32 flowid;
++ void *dma_buf;
++ u32 dma_sz;
++ u64 address;
++ int err;
++
++ flowid = work->flowid;
++ dma_sz = BRCMF_H2D_TXFLOWRING_MAX_ITEM * BRCMF_H2D_TXFLOWRING_ITEMSIZE;
++ dma_buf = dma_alloc_coherent(msgbuf->drvr->bus_if->dev, dma_sz,
++ &msgbuf->flowring_dma_handle[flowid],
++ GFP_KERNEL);
++ if (!dma_buf) {
++ brcmf_err("dma_alloc_coherent failed\n");
++ brcmf_flowring_delete(msgbuf->flow, flowid);
++ return BRCMF_FLOWRING_INVALID_ID;
++ }
++
++ brcmf_commonring_config(msgbuf->flowrings[flowid],
++ BRCMF_H2D_TXFLOWRING_MAX_ITEM,
++ BRCMF_H2D_TXFLOWRING_ITEMSIZE, dma_buf);
++
++ commonring = msgbuf->commonrings[BRCMF_H2D_MSGRING_CONTROL_SUBMIT];
++ brcmf_commonring_lock(commonring);
++ ret_ptr = brcmf_commonring_reserve_for_write(commonring);
++ if (!ret_ptr) {
++ brcmf_err("Failed to reserve space in commonring\n");
++ brcmf_commonring_unlock(commonring);
++ brcmf_msgbuf_remove_flowring(msgbuf, flowid);
++ return BRCMF_FLOWRING_INVALID_ID;
++ }
++
++ create = (struct msgbuf_tx_flowring_create_req *)ret_ptr;
++ create->msg.msgtype = MSGBUF_TYPE_FLOW_RING_CREATE;
++ create->msg.ifidx = work->ifidx;
++ create->msg.request_id = 0;
++ create->tid = brcmf_flowring_tid(msgbuf->flow, flowid);
++ create->flow_ring_id = cpu_to_le16(flowid +
++ BRCMF_NROF_H2D_COMMON_MSGRINGS);
++ memcpy(create->sa, work->sa, ETH_ALEN);
++ memcpy(create->da, work->da, ETH_ALEN);
++ address = (u64)msgbuf->flowring_dma_handle[flowid];
++ create->flow_ring_addr.high_addr = cpu_to_le32(address >> 32);
++ create->flow_ring_addr.low_addr = cpu_to_le32(address & 0xffffffff);
++ create->max_items = cpu_to_le16(BRCMF_H2D_TXFLOWRING_MAX_ITEM);
++ create->len_item = cpu_to_le16(BRCMF_H2D_TXFLOWRING_ITEMSIZE);
++
++ brcmf_dbg(MSGBUF, "Send Flow Create Req flow ID %d for peer %pM prio %d ifindex %d\n",
++ flowid, work->da, create->tid, work->ifidx);
++
++ err = brcmf_commonring_write_complete(commonring);
++ brcmf_commonring_unlock(commonring);
++ if (err) {
++ brcmf_err("Failed to write commonring\n");
++ brcmf_msgbuf_remove_flowring(msgbuf, flowid);
++ return BRCMF_FLOWRING_INVALID_ID;
++ }
++
++ return flowid;
++}
++
++
++static void brcmf_msgbuf_flowring_worker(struct work_struct *work)
++{
++ struct brcmf_msgbuf *msgbuf;
++ struct brcmf_msgbuf_work_item *create;
++
++ msgbuf = container_of(work, struct brcmf_msgbuf, flowring_work);
++
++ while ((create = brcmf_msgbuf_dequeue_work(msgbuf))) {
++ brcmf_msgbuf_flowring_create_worker(msgbuf, create);
++ kfree(create);
++ }
++}
++
++
++static u32 brcmf_msgbuf_flowring_create(struct brcmf_msgbuf *msgbuf, int ifidx,
++ struct sk_buff *skb)
++{
++ struct brcmf_msgbuf_work_item *create;
++ struct ethhdr *eh = (struct ethhdr *)(skb->data);
++ u32 flowid;
++ ulong flags;
++
++ create = kzalloc(sizeof(*create), GFP_ATOMIC);
++ if (create == NULL)
++ return BRCMF_FLOWRING_INVALID_ID;
++
++ flowid = brcmf_flowring_create(msgbuf->flow, eh->h_dest,
++ skb->priority, ifidx);
++ if (flowid == BRCMF_FLOWRING_INVALID_ID) {
++ kfree(create);
++ return flowid;
++ }
++
++ create->flowid = flowid;
++ create->ifidx = ifidx;
++ memcpy(create->sa, eh->h_source, ETH_ALEN);
++ memcpy(create->da, eh->h_dest, ETH_ALEN);
++
++ spin_lock_irqsave(&msgbuf->flowring_work_lock, flags);
++ list_add_tail(&create->queue, &msgbuf->work_queue);
++ spin_unlock_irqrestore(&msgbuf->flowring_work_lock, flags);
++ schedule_work(&msgbuf->flowring_work);
++
++ return flowid;
++}
++
++
++static void brcmf_msgbuf_txflow(struct brcmf_msgbuf *msgbuf, u8 flowid)
++{
++ struct brcmf_flowring *flow = msgbuf->flow;
++ struct brcmf_commonring *commonring;
++ void *ret_ptr;
++ u32 count;
++ struct sk_buff *skb;
++ dma_addr_t physaddr;
++ u32 pktid;
++ struct msgbuf_tx_msghdr *tx_msghdr;
++ u64 address;
++
++ commonring = msgbuf->flowrings[flowid];
++ if (!brcmf_commonring_write_available(commonring))
++ return;
++
++ brcmf_commonring_lock(commonring);
++
++ count = BRCMF_MSGBUF_TX_FLUSH_CNT2 - BRCMF_MSGBUF_TX_FLUSH_CNT1;
++ while (brcmf_flowring_qlen(flow, flowid)) {
++ skb = brcmf_flowring_dequeue(flow, flowid);
++ if (skb == NULL) {
++ brcmf_err("No SKB, but qlen %d\n",
++ brcmf_flowring_qlen(flow, flowid));
++ break;
++ }
++ skb_orphan(skb);
++ if (brcmf_msgbuf_alloc_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->tx_pktids, skb, ETH_HLEN,
++ &physaddr, &pktid)) {
++ brcmf_flowring_reinsert(flow, flowid, skb);
++ brcmf_err("No PKTID available !!\n");
++ break;
++ }
++ ret_ptr = brcmf_commonring_reserve_for_write(commonring);
++ if (!ret_ptr) {
++ brcmf_msgbuf_get_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->tx_pktids, pktid);
++ brcmf_flowring_reinsert(flow, flowid, skb);
++ break;
++ }
++ count++;
++
++ tx_msghdr = (struct msgbuf_tx_msghdr *)ret_ptr;
++
++ tx_msghdr->msg.msgtype = MSGBUF_TYPE_TX_POST;
++ tx_msghdr->msg.request_id = cpu_to_le32(pktid);
++ tx_msghdr->msg.ifidx = brcmf_flowring_ifidx_get(flow, flowid);
++ tx_msghdr->flags = BRCMF_MSGBUF_PKT_FLAGS_FRAME_802_3;
++ tx_msghdr->flags |= (skb->priority & 0x07) <<
++ BRCMF_MSGBUF_PKT_FLAGS_PRIO_SHIFT;
++ tx_msghdr->seg_cnt = 1;
++ memcpy(tx_msghdr->txhdr, skb->data, ETH_HLEN);
++ tx_msghdr->data_len = cpu_to_le16(skb->len - ETH_HLEN);
++ address = (u64)physaddr;
++ tx_msghdr->data_buf_addr.high_addr = cpu_to_le32(address >> 32);
++ tx_msghdr->data_buf_addr.low_addr =
++ cpu_to_le32(address & 0xffffffff);
++ tx_msghdr->metadata_buf_len = 0;
++ tx_msghdr->metadata_buf_addr.high_addr = 0;
++ tx_msghdr->metadata_buf_addr.low_addr = 0;
++ atomic_inc(&commonring->outstanding_tx);
++ if (count >= BRCMF_MSGBUF_TX_FLUSH_CNT2) {
++ brcmf_commonring_write_complete(commonring);
++ count = 0;
++ }
++ }
++ if (count)
++ brcmf_commonring_write_complete(commonring);
++ brcmf_commonring_unlock(commonring);
++}
++
++
++static void brcmf_msgbuf_txflow_worker(struct work_struct *worker)
++{
++ struct brcmf_msgbuf *msgbuf;
++ u32 flowid;
++
++ msgbuf = container_of(worker, struct brcmf_msgbuf, txflow_work);
++ for_each_set_bit(flowid, msgbuf->flow_map, msgbuf->nrof_flowrings) {
++ clear_bit(flowid, msgbuf->flow_map);
++ brcmf_msgbuf_txflow(msgbuf, flowid);
++ }
++}
++
++
++static int brcmf_msgbuf_schedule_txdata(struct brcmf_msgbuf *msgbuf, u32 flowid,
++ bool force)
++{
++ struct brcmf_commonring *commonring;
++
++ set_bit(flowid, msgbuf->flow_map);
++ commonring = msgbuf->flowrings[flowid];
++ if ((force) || (atomic_read(&commonring->outstanding_tx) <
++ BRCMF_MSGBUF_DELAY_TXWORKER_THRS))
++ queue_work(msgbuf->txflow_wq, &msgbuf->txflow_work);
++
++ return 0;
++}
++
++
++static int brcmf_msgbuf_txdata(struct brcmf_pub *drvr, int ifidx,
++ u8 offset, struct sk_buff *skb)
++{
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++ struct brcmf_flowring *flow = msgbuf->flow;
++ struct ethhdr *eh = (struct ethhdr *)(skb->data);
++ u32 flowid;
++ u32 queue_count;
++ bool force;
++
++ flowid = brcmf_flowring_lookup(flow, eh->h_dest, skb->priority, ifidx);
++ if (flowid == BRCMF_FLOWRING_INVALID_ID) {
++ flowid = brcmf_msgbuf_flowring_create(msgbuf, ifidx, skb);
++ if (flowid == BRCMF_FLOWRING_INVALID_ID)
++ return -ENOMEM;
++ }
++ queue_count = brcmf_flowring_enqueue(flow, flowid, skb);
++ force = ((queue_count % BRCMF_MSGBUF_TRICKLE_TXWORKER_THRS) == 0);
++ brcmf_msgbuf_schedule_txdata(msgbuf, flowid, force);
++
++ return 0;
++}
++
++
++static void
++brcmf_msgbuf_configure_addr_mode(struct brcmf_pub *drvr, int ifidx,
++ enum proto_addr_mode addr_mode)
++{
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++
++ brcmf_flowring_configure_addr_mode(msgbuf->flow, ifidx, addr_mode);
++}
++
++
++static void
++brcmf_msgbuf_delete_peer(struct brcmf_pub *drvr, int ifidx, u8 peer[ETH_ALEN])
++{
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++
++ brcmf_flowring_delete_peer(msgbuf->flow, ifidx, peer);
++}
++
++
++static void
++brcmf_msgbuf_add_tdls_peer(struct brcmf_pub *drvr, int ifidx, u8 peer[ETH_ALEN])
++{
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++
++ brcmf_flowring_add_tdls_peer(msgbuf->flow, ifidx, peer);
++}
++
++
++static void
++brcmf_msgbuf_process_ioctl_complete(struct brcmf_msgbuf *msgbuf, void *buf)
++{
++ struct msgbuf_ioctl_resp_hdr *ioctl_resp;
++
++ ioctl_resp = (struct msgbuf_ioctl_resp_hdr *)buf;
++
++ msgbuf->ioctl_resp_status =
++ (s16)le16_to_cpu(ioctl_resp->compl_hdr.status);
++ msgbuf->ioctl_resp_ret_len = le16_to_cpu(ioctl_resp->resp_len);
++ msgbuf->ioctl_resp_pktid = le32_to_cpu(ioctl_resp->msg.request_id);
++
++ brcmf_msgbuf_ioctl_resp_wake(msgbuf);
++
++ if (msgbuf->cur_ioctlrespbuf)
++ msgbuf->cur_ioctlrespbuf--;
++ brcmf_msgbuf_rxbuf_ioctlresp_post(msgbuf);
++}
++
++
++static void
++brcmf_msgbuf_process_txstatus(struct brcmf_msgbuf *msgbuf, void *buf)
++{
++ struct brcmf_commonring *commonring;
++ struct msgbuf_tx_status *tx_status;
++ u32 idx;
++ struct sk_buff *skb;
++ u16 flowid;
++
++ tx_status = (struct msgbuf_tx_status *)buf;
++ idx = le32_to_cpu(tx_status->msg.request_id);
++ flowid = le16_to_cpu(tx_status->compl_hdr.flow_ring_id);
++ flowid -= BRCMF_NROF_H2D_COMMON_MSGRINGS;
++ skb = brcmf_msgbuf_get_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->tx_pktids, idx);
++ if (!skb)
++ return;
++
++ set_bit(flowid, msgbuf->txstatus_done_map);
++ commonring = msgbuf->flowrings[flowid];
++ atomic_dec(&commonring->outstanding_tx);
++
++ brcmf_txfinalize(msgbuf->drvr, skb, tx_status->msg.ifidx, true);
++}
++
++
++static u32 brcmf_msgbuf_rxbuf_data_post(struct brcmf_msgbuf *msgbuf, u32 count)
++{
++ struct brcmf_commonring *commonring;
++ void *ret_ptr;
++ struct sk_buff *skb;
++ u16 alloced;
++ u32 pktlen;
++ dma_addr_t physaddr;
++ struct msgbuf_rx_bufpost *rx_bufpost;
++ u64 address;
++ u32 pktid;
++ u32 i;
++
++ commonring = msgbuf->commonrings[BRCMF_H2D_MSGRING_RXPOST_SUBMIT];
++ ret_ptr = brcmf_commonring_reserve_for_write_multiple(commonring,
++ count,
++ &alloced);
++ if (!ret_ptr) {
++ brcmf_dbg(MSGBUF, "Failed to reserve space in commonring\n");
++ return 0;
++ }
++
++ for (i = 0; i < alloced; i++) {
++ rx_bufpost = (struct msgbuf_rx_bufpost *)ret_ptr;
++ memset(rx_bufpost, 0, sizeof(*rx_bufpost));
++
++ skb = brcmu_pkt_buf_get_skb(BRCMF_MSGBUF_MAX_PKT_SIZE);
++
++ if (skb == NULL) {
++ brcmf_err("Failed to alloc SKB\n");
++ brcmf_commonring_write_cancel(commonring, alloced - i);
++ break;
++ }
++
++ pktlen = skb->len;
++ if (brcmf_msgbuf_alloc_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->rx_pktids, skb, 0,
++ &physaddr, &pktid)) {
++ dev_kfree_skb_any(skb);
++ brcmf_err("No PKTID available !!\n");
++ brcmf_commonring_write_cancel(commonring, alloced - i);
++ break;
++ }
++
++ if (msgbuf->rx_metadata_offset) {
++ address = (u64)physaddr;
++ rx_bufpost->metadata_buf_len =
++ cpu_to_le16(msgbuf->rx_metadata_offset);
++ rx_bufpost->metadata_buf_addr.high_addr =
++ cpu_to_le32(address >> 32);
++ rx_bufpost->metadata_buf_addr.low_addr =
++ cpu_to_le32(address & 0xffffffff);
++
++ skb_pull(skb, msgbuf->rx_metadata_offset);
++ pktlen = skb->len;
++ physaddr += msgbuf->rx_metadata_offset;
++ }
++ rx_bufpost->msg.msgtype = MSGBUF_TYPE_RXBUF_POST;
++ rx_bufpost->msg.request_id = cpu_to_le32(pktid);
++
++ address = (u64)physaddr;
++ rx_bufpost->data_buf_len = cpu_to_le16((u16)pktlen);
++ rx_bufpost->data_buf_addr.high_addr =
++ cpu_to_le32(address >> 32);
++ rx_bufpost->data_buf_addr.low_addr =
++ cpu_to_le32(address & 0xffffffff);
++
++ ret_ptr += brcmf_commonring_len_item(commonring);
++ }
++
++ if (i)
++ brcmf_commonring_write_complete(commonring);
++
++ return i;
++}
++
++
++static void
++brcmf_msgbuf_rxbuf_data_fill(struct brcmf_msgbuf *msgbuf)
++{
++ u32 fillbufs;
++ u32 retcount;
++
++ fillbufs = msgbuf->max_rxbufpost - msgbuf->rxbufpost;
++
++ while (fillbufs) {
++ retcount = brcmf_msgbuf_rxbuf_data_post(msgbuf, fillbufs);
++ if (!retcount)
++ break;
++ msgbuf->rxbufpost += retcount;
++ fillbufs -= retcount;
++ }
++}
++
++
++static void
++brcmf_msgbuf_update_rxbufpost_count(struct brcmf_msgbuf *msgbuf, u16 rxcnt)
++{
++ msgbuf->rxbufpost -= rxcnt;
++ if (msgbuf->rxbufpost <= (msgbuf->max_rxbufpost -
++ BRCMF_MSGBUF_RXBUFPOST_THRESHOLD))
++ brcmf_msgbuf_rxbuf_data_fill(msgbuf);
++}
++
++
++static u32
++brcmf_msgbuf_rxbuf_ctrl_post(struct brcmf_msgbuf *msgbuf, bool event_buf,
++ u32 count)
++{
++ struct brcmf_commonring *commonring;
++ void *ret_ptr;
++ struct sk_buff *skb;
++ u16 alloced;
++ u32 pktlen;
++ dma_addr_t physaddr;
++ struct msgbuf_rx_ioctl_resp_or_event *rx_bufpost;
++ u64 address;
++ u32 pktid;
++ u32 i;
++
++ commonring = msgbuf->commonrings[BRCMF_H2D_MSGRING_CONTROL_SUBMIT];
++ brcmf_commonring_lock(commonring);
++ ret_ptr = brcmf_commonring_reserve_for_write_multiple(commonring,
++ count,
++ &alloced);
++ if (!ret_ptr) {
++ brcmf_err("Failed to reserve space in commonring\n");
++ brcmf_commonring_unlock(commonring);
++ return 0;
++ }
++
++ for (i = 0; i < alloced; i++) {
++ rx_bufpost = (struct msgbuf_rx_ioctl_resp_or_event *)ret_ptr;
++ memset(rx_bufpost, 0, sizeof(*rx_bufpost));
++
++ skb = brcmu_pkt_buf_get_skb(BRCMF_MSGBUF_MAX_PKT_SIZE);
++
++ if (skb == NULL) {
++ brcmf_err("Failed to alloc SKB\n");
++ brcmf_commonring_write_cancel(commonring, alloced - i);
++ break;
++ }
++
++ pktlen = skb->len;
++ if (brcmf_msgbuf_alloc_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->rx_pktids, skb, 0,
++ &physaddr, &pktid)) {
++ dev_kfree_skb_any(skb);
++ brcmf_err("No PKTID available !!\n");
++ brcmf_commonring_write_cancel(commonring, alloced - i);
++ break;
++ }
++ if (event_buf)
++ rx_bufpost->msg.msgtype = MSGBUF_TYPE_EVENT_BUF_POST;
++ else
++ rx_bufpost->msg.msgtype =
++ MSGBUF_TYPE_IOCTLRESP_BUF_POST;
++ rx_bufpost->msg.request_id = cpu_to_le32(pktid);
++
++ address = (u64)physaddr;
++ rx_bufpost->host_buf_len = cpu_to_le16((u16)pktlen);
++ rx_bufpost->host_buf_addr.high_addr =
++ cpu_to_le32(address >> 32);
++ rx_bufpost->host_buf_addr.low_addr =
++ cpu_to_le32(address & 0xffffffff);
++
++ ret_ptr += brcmf_commonring_len_item(commonring);
++ }
++
++ if (i)
++ brcmf_commonring_write_complete(commonring);
++
++ brcmf_commonring_unlock(commonring);
++
++ return i;
++}
++
++
++static void brcmf_msgbuf_rxbuf_ioctlresp_post(struct brcmf_msgbuf *msgbuf)
++{
++ u32 count;
++
++ count = msgbuf->max_ioctlrespbuf - msgbuf->cur_ioctlrespbuf;
++ count = brcmf_msgbuf_rxbuf_ctrl_post(msgbuf, false, count);
++ msgbuf->cur_ioctlrespbuf += count;
++}
++
++
++static void brcmf_msgbuf_rxbuf_event_post(struct brcmf_msgbuf *msgbuf)
++{
++ u32 count;
++
++ count = msgbuf->max_eventbuf - msgbuf->cur_eventbuf;
++ count = brcmf_msgbuf_rxbuf_ctrl_post(msgbuf, true, count);
++ msgbuf->cur_eventbuf += count;
++}
++
++
++static void
++brcmf_msgbuf_rx_skb(struct brcmf_msgbuf *msgbuf, struct sk_buff *skb,
++ u8 ifidx)
++{
++ struct brcmf_if *ifp;
++
++ /* The ifidx is the idx to map to matching netdev/ifp. When receiving
++ * events this is easy because it contains the bssidx which maps
++ * 1-on-1 to the netdev/ifp. But for data frames the ifidx is rcvd.
++ * bssidx 1 is used for p2p0 and no data can be received or
++ * transmitted on it. Therefor bssidx is ifidx + 1 if ifidx > 0
++ */
++ if (ifidx)
++ (ifidx)++;
++ ifp = msgbuf->drvr->iflist[ifidx];
++ if (!ifp || !ifp->ndev) {
++ brcmf_err("Received pkt for invalid ifidx %d\n", ifidx);
++ brcmu_pkt_buf_free_skb(skb);
++ return;
++ }
++ brcmf_netif_rx(ifp, skb);
++}
++
++
++static void brcmf_msgbuf_process_event(struct brcmf_msgbuf *msgbuf, void *buf)
++{
++ struct msgbuf_rx_event *event;
++ u32 idx;
++ u16 buflen;
++ struct sk_buff *skb;
++
++ event = (struct msgbuf_rx_event *)buf;
++ idx = le32_to_cpu(event->msg.request_id);
++ buflen = le16_to_cpu(event->event_data_len);
++
++ if (msgbuf->cur_eventbuf)
++ msgbuf->cur_eventbuf--;
++ brcmf_msgbuf_rxbuf_event_post(msgbuf);
++
++ skb = brcmf_msgbuf_get_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->rx_pktids, idx);
++ if (!skb)
++ return;
++
++ if (msgbuf->rx_dataoffset)
++ skb_pull(skb, msgbuf->rx_dataoffset);
++
++ skb_trim(skb, buflen);
++
++ brcmf_msgbuf_rx_skb(msgbuf, skb, event->msg.ifidx);
++}
++
++
++static void
++brcmf_msgbuf_process_rx_complete(struct brcmf_msgbuf *msgbuf, void *buf)
++{
++ struct msgbuf_rx_complete *rx_complete;
++ struct sk_buff *skb;
++ u16 data_offset;
++ u16 buflen;
++ u32 idx;
++
++ brcmf_msgbuf_update_rxbufpost_count(msgbuf, 1);
++
++ rx_complete = (struct msgbuf_rx_complete *)buf;
++ data_offset = le16_to_cpu(rx_complete->data_offset);
++ buflen = le16_to_cpu(rx_complete->data_len);
++ idx = le32_to_cpu(rx_complete->msg.request_id);
++
++ skb = brcmf_msgbuf_get_pktid(msgbuf->drvr->bus_if->dev,
++ msgbuf->rx_pktids, idx);
++ if (!skb)
++ return;
++
++ if (data_offset)
++ skb_pull(skb, data_offset);
++ else if (msgbuf->rx_dataoffset)
++ skb_pull(skb, msgbuf->rx_dataoffset);
++
++ skb_trim(skb, buflen);
++
++ brcmf_msgbuf_rx_skb(msgbuf, skb, rx_complete->msg.ifidx);
++}
++
++
++static void
++brcmf_msgbuf_process_flow_ring_create_response(struct brcmf_msgbuf *msgbuf,
++ void *buf)
++{
++ struct msgbuf_flowring_create_resp *flowring_create_resp;
++ u16 status;
++ u16 flowid;
++
++ flowring_create_resp = (struct msgbuf_flowring_create_resp *)buf;
++
++ flowid = le16_to_cpu(flowring_create_resp->compl_hdr.flow_ring_id);
++ flowid -= BRCMF_NROF_H2D_COMMON_MSGRINGS;
++ status = le16_to_cpu(flowring_create_resp->compl_hdr.status);
++
++ if (status) {
++ brcmf_err("Flowring creation failed, code %d\n", status);
++ brcmf_msgbuf_remove_flowring(msgbuf, flowid);
++ return;
++ }
++ brcmf_dbg(MSGBUF, "Flowring %d Create response status %d\n", flowid,
++ status);
++
++ brcmf_flowring_open(msgbuf->flow, flowid);
++
++ brcmf_msgbuf_schedule_txdata(msgbuf, flowid, true);
++}
++
++
++static void
++brcmf_msgbuf_process_flow_ring_delete_response(struct brcmf_msgbuf *msgbuf,
++ void *buf)
++{
++ struct msgbuf_flowring_delete_resp *flowring_delete_resp;
++ u16 status;
++ u16 flowid;
++
++ flowring_delete_resp = (struct msgbuf_flowring_delete_resp *)buf;
++
++ flowid = le16_to_cpu(flowring_delete_resp->compl_hdr.flow_ring_id);
++ flowid -= BRCMF_NROF_H2D_COMMON_MSGRINGS;
++ status = le16_to_cpu(flowring_delete_resp->compl_hdr.status);
++
++ if (status) {
++ brcmf_err("Flowring deletion failed, code %d\n", status);
++ brcmf_flowring_delete(msgbuf->flow, flowid);
++ return;
++ }
++ brcmf_dbg(MSGBUF, "Flowring %d Delete response status %d\n", flowid,
++ status);
++
++ brcmf_msgbuf_remove_flowring(msgbuf, flowid);
++}
++
++
++static void brcmf_msgbuf_process_msgtype(struct brcmf_msgbuf *msgbuf, void *buf)
++{
++ struct msgbuf_common_hdr *msg;
++
++ msg = (struct msgbuf_common_hdr *)buf;
++ switch (msg->msgtype) {
++ case MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT:
++ brcmf_dbg(MSGBUF, "MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT\n");
++ brcmf_msgbuf_process_flow_ring_create_response(msgbuf, buf);
++ break;
++ case MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT:
++ brcmf_dbg(MSGBUF, "MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT\n");
++ brcmf_msgbuf_process_flow_ring_delete_response(msgbuf, buf);
++ break;
++ case MSGBUF_TYPE_IOCTLPTR_REQ_ACK:
++ brcmf_dbg(MSGBUF, "MSGBUF_TYPE_IOCTLPTR_REQ_ACK\n");
++ break;
++ case MSGBUF_TYPE_IOCTL_CMPLT:
++ brcmf_dbg(MSGBUF, "MSGBUF_TYPE_IOCTL_CMPLT\n");
++ brcmf_msgbuf_process_ioctl_complete(msgbuf, buf);
++ break;
++ case MSGBUF_TYPE_WL_EVENT:
++ brcmf_dbg(MSGBUF, "MSGBUF_TYPE_WL_EVENT\n");
++ brcmf_msgbuf_process_event(msgbuf, buf);
++ break;
++ case MSGBUF_TYPE_TX_STATUS:
++ brcmf_dbg(MSGBUF, "MSGBUF_TYPE_TX_STATUS\n");
++ brcmf_msgbuf_process_txstatus(msgbuf, buf);
++ break;
++ case MSGBUF_TYPE_RX_CMPLT:
++ brcmf_dbg(MSGBUF, "MSGBUF_TYPE_RX_CMPLT\n");
++ brcmf_msgbuf_process_rx_complete(msgbuf, buf);
++ break;
++ default:
++ brcmf_err("Unsupported msgtype %d\n", msg->msgtype);
++ break;
++ }
++}
++
++
++static void brcmf_msgbuf_process_rx(struct brcmf_msgbuf *msgbuf,
++ struct brcmf_commonring *commonring)
++{
++ void *buf;
++ u16 count;
++
++again:
++ buf = brcmf_commonring_get_read_ptr(commonring, &count);
++ if (buf == NULL)
++ return;
++
++ while (count) {
++ brcmf_msgbuf_process_msgtype(msgbuf,
++ buf + msgbuf->rx_dataoffset);
++ buf += brcmf_commonring_len_item(commonring);
++ count--;
++ }
++ brcmf_commonring_read_complete(commonring);
++
++ if (commonring->r_ptr == 0)
++ goto again;
++}
++
++
++int brcmf_proto_msgbuf_rx_trigger(struct device *dev)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pub *drvr = bus_if->drvr;
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++ struct brcmf_commonring *commonring;
++ void *buf;
++ u32 flowid;
++ int qlen;
++
++ buf = msgbuf->commonrings[BRCMF_D2H_MSGRING_RX_COMPLETE];
++ brcmf_msgbuf_process_rx(msgbuf, buf);
++ buf = msgbuf->commonrings[BRCMF_D2H_MSGRING_TX_COMPLETE];
++ brcmf_msgbuf_process_rx(msgbuf, buf);
++ buf = msgbuf->commonrings[BRCMF_D2H_MSGRING_CONTROL_COMPLETE];
++ brcmf_msgbuf_process_rx(msgbuf, buf);
++
++ for_each_set_bit(flowid, msgbuf->txstatus_done_map,
++ msgbuf->nrof_flowrings) {
++ clear_bit(flowid, msgbuf->txstatus_done_map);
++ commonring = msgbuf->flowrings[flowid];
++ qlen = brcmf_flowring_qlen(msgbuf->flow, flowid);
++ if ((qlen > BRCMF_MSGBUF_TRICKLE_TXWORKER_THRS) ||
++ ((qlen) && (atomic_read(&commonring->outstanding_tx) <
++ BRCMF_MSGBUF_TRICKLE_TXWORKER_THRS)))
++ brcmf_msgbuf_schedule_txdata(msgbuf, flowid, true);
++ }
++
++ return 0;
++}
++
++
++void brcmf_msgbuf_delete_flowring(struct brcmf_pub *drvr, u8 flowid)
++{
++ struct brcmf_msgbuf *msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++ struct msgbuf_tx_flowring_delete_req *delete;
++ struct brcmf_commonring *commonring;
++ void *ret_ptr;
++ u8 ifidx;
++ int err;
++
++ commonring = msgbuf->commonrings[BRCMF_H2D_MSGRING_CONTROL_SUBMIT];
++ brcmf_commonring_lock(commonring);
++ ret_ptr = brcmf_commonring_reserve_for_write(commonring);
++ if (!ret_ptr) {
++ brcmf_err("FW unaware, flowring will be removed !!\n");
++ brcmf_commonring_unlock(commonring);
++ brcmf_msgbuf_remove_flowring(msgbuf, flowid);
++ return;
++ }
++
++ delete = (struct msgbuf_tx_flowring_delete_req *)ret_ptr;
++
++ ifidx = brcmf_flowring_ifidx_get(msgbuf->flow, flowid);
++
++ delete->msg.msgtype = MSGBUF_TYPE_FLOW_RING_DELETE;
++ delete->msg.ifidx = ifidx;
++ delete->msg.request_id = 0;
++
++ delete->flow_ring_id = cpu_to_le16(flowid +
++ BRCMF_NROF_H2D_COMMON_MSGRINGS);
++ delete->reason = 0;
++
++ brcmf_dbg(MSGBUF, "Send Flow Delete Req flow ID %d, ifindex %d\n",
++ flowid, ifidx);
++
++ err = brcmf_commonring_write_complete(commonring);
++ brcmf_commonring_unlock(commonring);
++ if (err) {
++ brcmf_err("Failed to submit RING_DELETE, flowring will be removed\n");
++ brcmf_msgbuf_remove_flowring(msgbuf, flowid);
++ }
++}
++
++
++int brcmf_proto_msgbuf_attach(struct brcmf_pub *drvr)
++{
++ struct brcmf_bus_msgbuf *if_msgbuf;
++ struct brcmf_msgbuf *msgbuf;
++ u64 address;
++ u32 count;
++
++ if_msgbuf = drvr->bus_if->msgbuf;
++ msgbuf = kzalloc(sizeof(*msgbuf), GFP_KERNEL);
++ if (!msgbuf)
++ goto fail;
++
++ msgbuf->txflow_wq = create_singlethread_workqueue("msgbuf_txflow");
++ if (msgbuf->txflow_wq == NULL) {
++ brcmf_err("workqueue creation failed\n");
++ goto fail;
++ }
++ INIT_WORK(&msgbuf->txflow_work, brcmf_msgbuf_txflow_worker);
++ count = BITS_TO_LONGS(if_msgbuf->nrof_flowrings);
++ count = count * sizeof(unsigned long);
++ msgbuf->flow_map = kzalloc(count, GFP_KERNEL);
++ if (!msgbuf->flow_map)
++ goto fail;
++
++ msgbuf->txstatus_done_map = kzalloc(count, GFP_KERNEL);
++ if (!msgbuf->txstatus_done_map)
++ goto fail;
++
++ msgbuf->drvr = drvr;
++ msgbuf->ioctbuf = dma_alloc_coherent(drvr->bus_if->dev,
++ BRCMF_TX_IOCTL_MAX_MSG_SIZE,
++ &msgbuf->ioctbuf_handle,
++ GFP_KERNEL);
++ if (!msgbuf->ioctbuf)
++ goto fail;
++ address = (u64)msgbuf->ioctbuf_handle;
++ msgbuf->ioctbuf_phys_hi = address >> 32;
++ msgbuf->ioctbuf_phys_lo = address & 0xffffffff;
++
++ drvr->proto->hdrpull = brcmf_msgbuf_hdrpull;
++ drvr->proto->query_dcmd = brcmf_msgbuf_query_dcmd;
++ drvr->proto->set_dcmd = brcmf_msgbuf_set_dcmd;
++ drvr->proto->txdata = brcmf_msgbuf_txdata;
++ drvr->proto->configure_addr_mode = brcmf_msgbuf_configure_addr_mode;
++ drvr->proto->delete_peer = brcmf_msgbuf_delete_peer;
++ drvr->proto->add_tdls_peer = brcmf_msgbuf_add_tdls_peer;
++ drvr->proto->pd = msgbuf;
++
++ init_waitqueue_head(&msgbuf->ioctl_resp_wait);
++
++ msgbuf->commonrings =
++ (struct brcmf_commonring **)if_msgbuf->commonrings;
++ msgbuf->flowrings = (struct brcmf_commonring **)if_msgbuf->flowrings;
++ msgbuf->nrof_flowrings = if_msgbuf->nrof_flowrings;
++ msgbuf->flowring_dma_handle = kzalloc(msgbuf->nrof_flowrings *
++ sizeof(*msgbuf->flowring_dma_handle), GFP_KERNEL);
++ if (!msgbuf->flowring_dma_handle)
++ goto fail;
++
++ msgbuf->rx_dataoffset = if_msgbuf->rx_dataoffset;
++ msgbuf->max_rxbufpost = if_msgbuf->max_rxbufpost;
++
++ msgbuf->max_ioctlrespbuf = BRCMF_MSGBUF_MAX_IOCTLRESPBUF_POST;
++ msgbuf->max_eventbuf = BRCMF_MSGBUF_MAX_EVENTBUF_POST;
++
++ msgbuf->tx_pktids = brcmf_msgbuf_init_pktids(NR_TX_PKTIDS,
++ DMA_TO_DEVICE);
++ if (!msgbuf->tx_pktids)
++ goto fail;
++ msgbuf->rx_pktids = brcmf_msgbuf_init_pktids(NR_RX_PKTIDS,
++ DMA_FROM_DEVICE);
++ if (!msgbuf->rx_pktids)
++ goto fail;
++
++ msgbuf->flow = brcmf_flowring_attach(drvr->bus_if->dev,
++ if_msgbuf->nrof_flowrings);
++ if (!msgbuf->flow)
++ goto fail;
++
++
++ brcmf_dbg(MSGBUF, "Feeding buffers, rx data %d, rx event %d, rx ioctl resp %d\n",
++ msgbuf->max_rxbufpost, msgbuf->max_eventbuf,
++ msgbuf->max_ioctlrespbuf);
++ count = 0;
++ do {
++ brcmf_msgbuf_rxbuf_data_fill(msgbuf);
++ if (msgbuf->max_rxbufpost != msgbuf->rxbufpost)
++ msleep(10);
++ else
++ break;
++ count++;
++ } while (count < 10);
++ brcmf_msgbuf_rxbuf_event_post(msgbuf);
++ brcmf_msgbuf_rxbuf_ioctlresp_post(msgbuf);
++
++ INIT_WORK(&msgbuf->flowring_work, brcmf_msgbuf_flowring_worker);
++ spin_lock_init(&msgbuf->flowring_work_lock);
++ INIT_LIST_HEAD(&msgbuf->work_queue);
++
++ return 0;
++
++fail:
++ if (msgbuf) {
++ kfree(msgbuf->flow_map);
++ kfree(msgbuf->txstatus_done_map);
++ brcmf_msgbuf_release_pktids(msgbuf);
++ kfree(msgbuf->flowring_dma_handle);
++ if (msgbuf->ioctbuf)
++ dma_free_coherent(drvr->bus_if->dev,
++ BRCMF_TX_IOCTL_MAX_MSG_SIZE,
++ msgbuf->ioctbuf,
++ msgbuf->ioctbuf_handle);
++ kfree(msgbuf);
++ }
++ return -ENOMEM;
++}
++
++
++void brcmf_proto_msgbuf_detach(struct brcmf_pub *drvr)
++{
++ struct brcmf_msgbuf *msgbuf;
++ struct brcmf_msgbuf_work_item *work;
++
++ brcmf_dbg(TRACE, "Enter\n");
++ if (drvr->proto->pd) {
++ msgbuf = (struct brcmf_msgbuf *)drvr->proto->pd;
++ cancel_work_sync(&msgbuf->flowring_work);
++ while (!list_empty(&msgbuf->work_queue)) {
++ work = list_first_entry(&msgbuf->work_queue,
++ struct brcmf_msgbuf_work_item,
++ queue);
++ list_del(&work->queue);
++ kfree(work);
++ }
++ kfree(msgbuf->flow_map);
++ kfree(msgbuf->txstatus_done_map);
++ if (msgbuf->txflow_wq)
++ destroy_workqueue(msgbuf->txflow_wq);
++
++ brcmf_flowring_detach(msgbuf->flow);
++ dma_free_coherent(drvr->bus_if->dev,
++ BRCMF_TX_IOCTL_MAX_MSG_SIZE,
++ msgbuf->ioctbuf, msgbuf->ioctbuf_handle);
++ brcmf_msgbuf_release_pktids(msgbuf);
++ kfree(msgbuf->flowring_dma_handle);
++ kfree(msgbuf);
++ drvr->proto->pd = NULL;
++ }
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/msgbuf.h 2016-06-19 22:11:55.285141319 +0200
+@@ -0,0 +1,47 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_MSGBUF_H
++#define BRCMFMAC_MSGBUF_H
++
++#ifdef CONFIG_BRCMFMAC_PROTO_MSGBUF
++
++#define BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM 64
++#define BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM 512
++#define BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM 64
++#define BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM 1024
++#define BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM 512
++#define BRCMF_H2D_TXFLOWRING_MAX_ITEM 512
++
++#define BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE 40
++#define BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE 32
++#define BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE 24
++#define BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE 16
++#define BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE 32
++#define BRCMF_H2D_TXFLOWRING_ITEMSIZE 48
++
++
++int brcmf_proto_msgbuf_rx_trigger(struct device *dev);
++void brcmf_msgbuf_delete_flowring(struct brcmf_pub *drvr, u8 flowid);
++int brcmf_proto_msgbuf_attach(struct brcmf_pub *drvr);
++void brcmf_proto_msgbuf_detach(struct brcmf_pub *drvr);
++#else
++static inline int brcmf_proto_msgbuf_attach(struct brcmf_pub *drvr)
++{
++ return 0;
++}
++static inline void brcmf_proto_msgbuf_detach(struct brcmf_pub *drvr) {}
++#endif
++
++#endif /* BRCMFMAC_MSGBUF_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/nvram.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/nvram.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,94 +0,0 @@
+-/*
+- * Copyright (c) 2013 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/slab.h>
+-#include <linux/firmware.h>
+-
+-#include "nvram.h"
+-
+-/* brcmf_nvram_strip :Takes a buffer of "<var>=<value>\n" lines read from a file
+- * and ending in a NUL. Removes carriage returns, empty lines, comment lines,
+- * and converts newlines to NULs. Shortens buffer as needed and pads with NULs.
+- * End of buffer is completed with token identifying length of buffer.
+- */
+-void *brcmf_nvram_strip(const struct firmware *nv, u32 *new_length)
+-{
+- u8 *nvram;
+- u32 i;
+- u32 len;
+- u32 column;
+- u8 val;
+- bool comment;
+- u32 token;
+- __le32 token_le;
+-
+- /* Alloc for extra 0 byte + roundup by 4 + length field */
+- nvram = kmalloc(nv->size + 1 + 3 + sizeof(token_le), GFP_KERNEL);
+- if (!nvram)
+- return NULL;
+-
+- len = 0;
+- column = 0;
+- comment = false;
+- for (i = 0; i < nv->size; i++) {
+- val = nv->data[i];
+- if (val == 0)
+- break;
+- if (val == '\r')
+- continue;
+- if (comment && (val != '\n'))
+- continue;
+- comment = false;
+- if (val == '#') {
+- comment = true;
+- continue;
+- }
+- if (val == '\n') {
+- if (column == 0)
+- continue;
+- nvram[len] = 0;
+- len++;
+- column = 0;
+- continue;
+- }
+- nvram[len] = val;
+- len++;
+- column++;
+- }
+- column = len;
+- *new_length = roundup(len + 1, 4);
+- while (column != *new_length) {
+- nvram[column] = 0;
+- column++;
+- }
+-
+- token = *new_length / 4;
+- token = (~token << 16) | (token & 0x0000FFFF);
+- token_le = cpu_to_le32(token);
+-
+- memcpy(&nvram[*new_length], &token_le, sizeof(token_le));
+- *new_length += sizeof(token_le);
+-
+- return nvram;
+-}
+-
+-void brcmf_nvram_free(void *nvram)
+-{
+- kfree(nvram);
+-}
+-
+-
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/nvram.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/nvram.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/nvram.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,24 +0,0 @@
+-/*
+- * Copyright (c) 2013 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-#ifndef BRCMFMAC_NVRAM_H
+-#define BRCMFMAC_NVRAM_H
+-
+-
+-void *brcmf_nvram_strip(const struct firmware *nv, u32 *new_length);
+-void brcmf_nvram_free(void *nvram);
+-
+-
+-#endif /* BRCMFMAC_NVRAM_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/of.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/of.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/of.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/of.c 2016-06-19 22:11:55.285141319 +0200
+@@ -0,0 +1,59 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#include <linux/init.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/mmc/card.h>
++#include <linux/platform_data/brcmfmac-sdio.h>
++#include <linux/mmc/sdio_func.h>
++
++#include <defs.h>
++#include "debug.h"
++#include "sdio.h"
++
++void brcmf_of_probe(struct brcmf_sdio_dev *sdiodev)
++{
++ struct device *dev = sdiodev->dev;
++ struct device_node *np = dev->of_node;
++ int irq;
++ u32 irqf;
++ u32 val;
++
++ if (!np || !of_device_is_compatible(np, "brcm,bcm4329-fmac"))
++ return;
++
++ sdiodev->pdata = devm_kzalloc(dev, sizeof(*sdiodev->pdata), GFP_KERNEL);
++ if (!sdiodev->pdata)
++ return;
++
++ if (of_property_read_u32(np, "brcm,drive-strength", &val) == 0)
++ sdiodev->pdata->drive_strength = val;
++
++ /* make sure there are interrupts defined in the node */
++ if (!of_find_property(np, "interrupts", NULL))
++ return;
++
++ irq = irq_of_parse_and_map(np, 0);
++ if (!irq) {
++ brcmf_err("interrupt could not be mapped\n");
++ return;
++ }
++ irqf = irqd_get_trigger_type(irq_get_irq_data(irq));
++
++ sdiodev->pdata->oob_irq_supported = true;
++ sdiodev->pdata->oob_irq_nr = irq;
++ sdiodev->pdata->oob_irq_flags = irqf;
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/of.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/of.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/of.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/of.h 2016-06-19 22:11:55.285141319 +0200
+@@ -0,0 +1,22 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifdef CONFIG_OF
++void brcmf_of_probe(struct brcmf_sdio_dev *sdiodev);
++#else
++static void brcmf_of_probe(struct brcmf_sdio_dev *sdiodev)
++{
++}
++#endif /* CONFIG_OF */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/p2p.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/p2p.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/p2p.c 2016-06-19 22:11:55.285141319 +0200
+@@ -21,12 +21,12 @@
+ #include <brcmu_wifi.h>
+ #include <brcmu_utils.h>
+ #include <defs.h>
+-#include <dhd.h>
+-#include <dhd_dbg.h>
++#include "core.h"
++#include "debug.h"
+ #include "fwil.h"
+ #include "fwil_types.h"
+ #include "p2p.h"
+-#include "wl_cfg80211.h"
++#include "cfg80211.h"
+
+ /* parameters used for p2p escan */
+ #define P2PAPI_SCAN_NPROBES 1
+@@ -440,8 +440,11 @@
+
+ /* In case of COB type, firmware has default mac address
+ * After Initializing firmware, we have to set current mac address to
+- * firmware for P2P device address
++ * firmware for P2P device address. This must be done with discovery
++ * disabled.
+ */
++ brcmf_fil_iovar_int_set(ifp, "p2p_disc", 0);
++
+ ret = brcmf_fil_iovar_data_set(ifp, "p2p_da_override", p2p_mac,
+ ETH_ALEN);
+ if (ret)
+@@ -708,7 +711,7 @@
+ active = P2PAPI_SCAN_SOCIAL_DWELL_TIME_MS;
+ else if (num_chans == AF_PEER_SEARCH_CNT)
+ active = P2PAPI_SCAN_AF_SEARCH_DWELL_TIME_MS;
+- else if (wl_get_vif_state_all(p2p->cfg, BRCMF_VIF_STATUS_CONNECTED))
++ else if (brcmf_get_vif_state_any(p2p->cfg, BRCMF_VIF_STATUS_CONNECTED))
+ active = -1;
+ else
+ active = P2PAPI_SCAN_DWELL_TIME_MS;
+@@ -797,7 +800,8 @@
+ /* SOCIAL CHANNELS 1, 6, 11 */
+ search_state = WL_P2P_DISC_ST_SEARCH;
+ brcmf_dbg(INFO, "P2P SEARCH PHASE START\n");
+- } else if (dev != NULL && vif->mode == WL_MODE_AP) {
++ } else if (dev != NULL &&
++ vif->wdev.iftype == NL80211_IFTYPE_P2P_GO) {
+ /* If you are already a GO, then do SEARCH only */
+ brcmf_dbg(INFO, "Already a GO. Do SEARCH Only\n");
+ search_state = WL_P2P_DISC_ST_SEARCH;
+@@ -2256,7 +2260,6 @@
+ struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
+ struct brcmf_cfg80211_vif *vif;
+ enum brcmf_fil_p2p_if_types iftype;
+- enum wl_mode mode;
+ int err;
+
+ if (brcmf_cfg80211_vif_event_armed(cfg))
+@@ -2267,11 +2270,9 @@
+ switch (type) {
+ case NL80211_IFTYPE_P2P_CLIENT:
+ iftype = BRCMF_FIL_P2P_IF_CLIENT;
+- mode = WL_MODE_BSS;
+ break;
+ case NL80211_IFTYPE_P2P_GO:
+ iftype = BRCMF_FIL_P2P_IF_GO;
+- mode = WL_MODE_AP;
+ break;
+ case NL80211_IFTYPE_P2P_DEVICE:
+ return brcmf_p2p_create_p2pdev(&cfg->p2p, wiphy,
+@@ -2366,7 +2367,6 @@
+ return 0;
+ default:
+ return -ENOTSUPP;
+- break;
+ }
+
+ clear_bit(BRCMF_P2P_STATUS_GO_NEG_PHASE, &p2p->status);
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/pcie.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/pcie.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/pcie.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/pcie.c 2016-06-19 22:11:55.289141057 +0200
+@@ -0,0 +1,1977 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/firmware.h>
++#include <linux/pci.h>
++#include <linux/vmalloc.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/bcma/bcma.h>
++#include <linux/sched.h>
++#include <asm/unaligned.h>
++
++#include <soc.h>
++#include <chipcommon.h>
++#include <brcmu_utils.h>
++#include <brcmu_wifi.h>
++#include <brcm_hw_ids.h>
++
++#include "debug.h"
++#include "bus.h"
++#include "commonring.h"
++#include "msgbuf.h"
++#include "pcie.h"
++#include "firmware.h"
++#include "chip.h"
++
++
++enum brcmf_pcie_state {
++ BRCMFMAC_PCIE_STATE_DOWN,
++ BRCMFMAC_PCIE_STATE_UP
++};
++
++
++#define BRCMF_PCIE_43602_FW_NAME "brcm/brcmfmac43602-pcie.bin"
++#define BRCMF_PCIE_43602_NVRAM_NAME "brcm/brcmfmac43602-pcie.txt"
++#define BRCMF_PCIE_4356_FW_NAME "brcm/brcmfmac4356-pcie.bin"
++#define BRCMF_PCIE_4356_NVRAM_NAME "brcm/brcmfmac4356-pcie.txt"
++#define BRCMF_PCIE_43570_FW_NAME "brcm/brcmfmac43570-pcie.bin"
++#define BRCMF_PCIE_43570_NVRAM_NAME "brcm/brcmfmac43570-pcie.txt"
++
++#define BRCMF_PCIE_FW_UP_TIMEOUT 2000 /* msec */
++
++#define BRCMF_PCIE_TCM_MAP_SIZE (4096 * 1024)
++#define BRCMF_PCIE_REG_MAP_SIZE (32 * 1024)
++
++/* backplane addres space accessed by BAR0 */
++#define BRCMF_PCIE_BAR0_WINDOW 0x80
++#define BRCMF_PCIE_BAR0_REG_SIZE 0x1000
++#define BRCMF_PCIE_BAR0_WRAPPERBASE 0x70
++
++#define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET 0x1000
++#define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET 0x2000
++
++#define BRCMF_PCIE_ARMCR4REG_BANKIDX 0x40
++#define BRCMF_PCIE_ARMCR4REG_BANKPDA 0x4C
++
++#define BRCMF_PCIE_REG_INTSTATUS 0x90
++#define BRCMF_PCIE_REG_INTMASK 0x94
++#define BRCMF_PCIE_REG_SBMBX 0x98
++
++#define BRCMF_PCIE_PCIE2REG_INTMASK 0x24
++#define BRCMF_PCIE_PCIE2REG_MAILBOXINT 0x48
++#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK 0x4C
++#define BRCMF_PCIE_PCIE2REG_CONFIGADDR 0x120
++#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
++#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
++
++#define BRCMF_PCIE_GENREV1 1
++#define BRCMF_PCIE_GENREV2 2
++
++#define BRCMF_PCIE2_INTA 0x01
++#define BRCMF_PCIE2_INTB 0x02
++
++#define BRCMF_PCIE_INT_0 0x01
++#define BRCMF_PCIE_INT_1 0x02
++#define BRCMF_PCIE_INT_DEF (BRCMF_PCIE_INT_0 | \
++ BRCMF_PCIE_INT_1)
++
++#define BRCMF_PCIE_MB_INT_FN0_0 0x0100
++#define BRCMF_PCIE_MB_INT_FN0_1 0x0200
++#define BRCMF_PCIE_MB_INT_D2H0_DB0 0x10000
++#define BRCMF_PCIE_MB_INT_D2H0_DB1 0x20000
++#define BRCMF_PCIE_MB_INT_D2H1_DB0 0x40000
++#define BRCMF_PCIE_MB_INT_D2H1_DB1 0x80000
++#define BRCMF_PCIE_MB_INT_D2H2_DB0 0x100000
++#define BRCMF_PCIE_MB_INT_D2H2_DB1 0x200000
++#define BRCMF_PCIE_MB_INT_D2H3_DB0 0x400000
++#define BRCMF_PCIE_MB_INT_D2H3_DB1 0x800000
++
++#define BRCMF_PCIE_MB_INT_D2H_DB (BRCMF_PCIE_MB_INT_D2H0_DB0 | \
++ BRCMF_PCIE_MB_INT_D2H0_DB1 | \
++ BRCMF_PCIE_MB_INT_D2H1_DB0 | \
++ BRCMF_PCIE_MB_INT_D2H1_DB1 | \
++ BRCMF_PCIE_MB_INT_D2H2_DB0 | \
++ BRCMF_PCIE_MB_INT_D2H2_DB1 | \
++ BRCMF_PCIE_MB_INT_D2H3_DB0 | \
++ BRCMF_PCIE_MB_INT_D2H3_DB1)
++
++#define BRCMF_PCIE_MIN_SHARED_VERSION 5
++#define BRCMF_PCIE_MAX_SHARED_VERSION 5
++#define BRCMF_PCIE_SHARED_VERSION_MASK 0x00FF
++#define BRCMF_PCIE_SHARED_DMA_INDEX 0x10000
++#define BRCMF_PCIE_SHARED_DMA_2B_IDX 0x100000
++
++#define BRCMF_PCIE_FLAGS_HTOD_SPLIT 0x4000
++#define BRCMF_PCIE_FLAGS_DTOH_SPLIT 0x8000
++
++#define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET 34
++#define BRCMF_SHARED_RING_BASE_OFFSET 52
++#define BRCMF_SHARED_RX_DATAOFFSET_OFFSET 36
++#define BRCMF_SHARED_CONSOLE_ADDR_OFFSET 20
++#define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET 40
++#define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET 44
++#define BRCMF_SHARED_RING_INFO_ADDR_OFFSET 48
++#define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET 52
++#define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET 56
++#define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET 64
++#define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET 68
++
++#define BRCMF_RING_H2D_RING_COUNT_OFFSET 0
++#define BRCMF_RING_D2H_RING_COUNT_OFFSET 1
++#define BRCMF_RING_H2D_RING_MEM_OFFSET 4
++#define BRCMF_RING_H2D_RING_STATE_OFFSET 8
++
++#define BRCMF_RING_MEM_BASE_ADDR_OFFSET 8
++#define BRCMF_RING_MAX_ITEM_OFFSET 4
++#define BRCMF_RING_LEN_ITEMS_OFFSET 6
++#define BRCMF_RING_MEM_SZ 16
++#define BRCMF_RING_STATE_SZ 8
++
++#define BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET 4
++#define BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET 8
++#define BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET 12
++#define BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET 16
++#define BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET 20
++#define BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET 28
++#define BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET 36
++#define BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET 44
++#define BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET 0
++#define BRCMF_SHARED_RING_MAX_SUB_QUEUES 52
++
++#define BRCMF_DEF_MAX_RXBUFPOST 255
++
++#define BRCMF_CONSOLE_BUFADDR_OFFSET 8
++#define BRCMF_CONSOLE_BUFSIZE_OFFSET 12
++#define BRCMF_CONSOLE_WRITEIDX_OFFSET 16
++
++#define BRCMF_DMA_D2H_SCRATCH_BUF_LEN 8
++#define BRCMF_DMA_D2H_RINGUPD_BUF_LEN 1024
++
++#define BRCMF_D2H_DEV_D3_ACK 0x00000001
++#define BRCMF_D2H_DEV_DS_ENTER_REQ 0x00000002
++#define BRCMF_D2H_DEV_DS_EXIT_NOTE 0x00000004
++
++#define BRCMF_H2D_HOST_D3_INFORM 0x00000001
++#define BRCMF_H2D_HOST_DS_ACK 0x00000002
++#define BRCMF_H2D_HOST_D0_INFORM_IN_USE 0x00000008
++#define BRCMF_H2D_HOST_D0_INFORM 0x00000010
++
++#define BRCMF_PCIE_MBDATA_TIMEOUT 2000
++
++#define BRCMF_PCIE_CFGREG_STATUS_CMD 0x4
++#define BRCMF_PCIE_CFGREG_PM_CSR 0x4C
++#define BRCMF_PCIE_CFGREG_MSI_CAP 0x58
++#define BRCMF_PCIE_CFGREG_MSI_ADDR_L 0x5C
++#define BRCMF_PCIE_CFGREG_MSI_ADDR_H 0x60
++#define BRCMF_PCIE_CFGREG_MSI_DATA 0x64
++#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL 0xBC
++#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2 0xDC
++#define BRCMF_PCIE_CFGREG_RBAR_CTRL 0x228
++#define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1 0x248
++#define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG 0x4E0
++#define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG 0x4F4
++#define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB 3
++
++
++MODULE_FIRMWARE(BRCMF_PCIE_43602_FW_NAME);
++MODULE_FIRMWARE(BRCMF_PCIE_43602_NVRAM_NAME);
++MODULE_FIRMWARE(BRCMF_PCIE_4356_FW_NAME);
++MODULE_FIRMWARE(BRCMF_PCIE_4356_NVRAM_NAME);
++MODULE_FIRMWARE(BRCMF_PCIE_43570_FW_NAME);
++MODULE_FIRMWARE(BRCMF_PCIE_43570_NVRAM_NAME);
++
++
++struct brcmf_pcie_console {
++ u32 base_addr;
++ u32 buf_addr;
++ u32 bufsize;
++ u32 read_idx;
++ u8 log_str[256];
++ u8 log_idx;
++};
++
++struct brcmf_pcie_shared_info {
++ u32 tcm_base_address;
++ u32 flags;
++ struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
++ struct brcmf_pcie_ringbuf *flowrings;
++ u16 max_rxbufpost;
++ u32 nrof_flowrings;
++ u32 rx_dataoffset;
++ u32 htod_mb_data_addr;
++ u32 dtoh_mb_data_addr;
++ u32 ring_info_addr;
++ struct brcmf_pcie_console console;
++ void *scratch;
++ dma_addr_t scratch_dmahandle;
++ void *ringupd;
++ dma_addr_t ringupd_dmahandle;
++};
++
++struct brcmf_pcie_core_info {
++ u32 base;
++ u32 wrapbase;
++};
++
++struct brcmf_pciedev_info {
++ enum brcmf_pcie_state state;
++ bool in_irq;
++ bool irq_requested;
++ struct pci_dev *pdev;
++ char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
++ char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
++ void __iomem *regs;
++ void __iomem *tcm;
++ u32 tcm_size;
++ u32 ram_base;
++ u32 ram_size;
++ struct brcmf_chip *ci;
++ u32 coreid;
++ u32 generic_corerev;
++ struct brcmf_pcie_shared_info shared;
++ void (*ringbell)(struct brcmf_pciedev_info *devinfo);
++ wait_queue_head_t mbdata_resp_wait;
++ bool mbdata_completed;
++ bool irq_allocated;
++ bool wowl_enabled;
++ u8 dma_idx_sz;
++ void *idxbuf;
++ u32 idxbuf_sz;
++ dma_addr_t idxbuf_dmahandle;
++ u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
++ void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ u16 value);
++};
++
++struct brcmf_pcie_ringbuf {
++ struct brcmf_commonring commonring;
++ dma_addr_t dma_handle;
++ u32 w_idx_addr;
++ u32 r_idx_addr;
++ struct brcmf_pciedev_info *devinfo;
++ u8 id;
++};
++
++
++static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
++ BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
++ BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
++ BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
++ BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
++ BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
++};
++
++static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
++ BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
++ BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
++ BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
++ BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
++ BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
++};
++
++
++static u32
++brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
++{
++ void __iomem *address = devinfo->regs + reg_offset;
++
++ return (ioread32(address));
++}
++
++
++static void
++brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
++ u32 value)
++{
++ void __iomem *address = devinfo->regs + reg_offset;
++
++ iowrite32(value, address);
++}
++
++
++static u8
++brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
++{
++ void __iomem *address = devinfo->tcm + mem_offset;
++
++ return (ioread8(address));
++}
++
++
++static u16
++brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
++{
++ void __iomem *address = devinfo->tcm + mem_offset;
++
++ return (ioread16(address));
++}
++
++
++static void
++brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ u16 value)
++{
++ void __iomem *address = devinfo->tcm + mem_offset;
++
++ iowrite16(value, address);
++}
++
++
++static u16
++brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
++{
++ u16 *address = devinfo->idxbuf + mem_offset;
++
++ return (*(address));
++}
++
++
++static void
++brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ u16 value)
++{
++ u16 *address = devinfo->idxbuf + mem_offset;
++
++ *(address) = value;
++}
++
++
++static u32
++brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
++{
++ void __iomem *address = devinfo->tcm + mem_offset;
++
++ return (ioread32(address));
++}
++
++
++static void
++brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ u32 value)
++{
++ void __iomem *address = devinfo->tcm + mem_offset;
++
++ iowrite32(value, address);
++}
++
++
++static u32
++brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
++{
++ void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
++
++ return (ioread32(addr));
++}
++
++
++static void
++brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ u32 value)
++{
++ void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
++
++ iowrite32(value, addr);
++}
++
++
++static void
++brcmf_pcie_copy_mem_todev(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
++ void *srcaddr, u32 len)
++{
++ void __iomem *address = devinfo->tcm + mem_offset;
++ __le32 *src32;
++ __le16 *src16;
++ u8 *src8;
++
++ if (((ulong)address & 4) || ((ulong)srcaddr & 4) || (len & 4)) {
++ if (((ulong)address & 2) || ((ulong)srcaddr & 2) || (len & 2)) {
++ src8 = (u8 *)srcaddr;
++ while (len) {
++ iowrite8(*src8, address);
++ address++;
++ src8++;
++ len--;
++ }
++ } else {
++ len = len / 2;
++ src16 = (__le16 *)srcaddr;
++ while (len) {
++ iowrite16(le16_to_cpu(*src16), address);
++ address += 2;
++ src16++;
++ len--;
++ }
++ }
++ } else {
++ len = len / 4;
++ src32 = (__le32 *)srcaddr;
++ while (len) {
++ iowrite32(le32_to_cpu(*src32), address);
++ address += 4;
++ src32++;
++ len--;
++ }
++ }
++}
++
++
++#define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
++ CHIPCREGOFFS(reg), value)
++
++
++static void
++brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
++{
++ const struct pci_dev *pdev = devinfo->pdev;
++ struct brcmf_core *core;
++ u32 bar0_win;
++
++ core = brcmf_chip_get_core(devinfo->ci, coreid);
++ if (core) {
++ bar0_win = core->base;
++ pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
++ if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
++ &bar0_win) == 0) {
++ if (bar0_win != core->base) {
++ bar0_win = core->base;
++ pci_write_config_dword(pdev,
++ BRCMF_PCIE_BAR0_WINDOW,
++ bar0_win);
++ }
++ }
++ } else {
++ brcmf_err("Unsupported core selected %x\n", coreid);
++ }
++}
++
++
++static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
++{
++ u16 cfg_offset[] = { BRCMF_PCIE_CFGREG_STATUS_CMD,
++ BRCMF_PCIE_CFGREG_PM_CSR,
++ BRCMF_PCIE_CFGREG_MSI_CAP,
++ BRCMF_PCIE_CFGREG_MSI_ADDR_L,
++ BRCMF_PCIE_CFGREG_MSI_ADDR_H,
++ BRCMF_PCIE_CFGREG_MSI_DATA,
++ BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
++ BRCMF_PCIE_CFGREG_RBAR_CTRL,
++ BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
++ BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
++ BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG };
++ u32 i;
++ u32 val;
++ u32 lsc;
++
++ if (!devinfo->ci)
++ return;
++
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
++ BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
++ lsc = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
++ val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, val);
++
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
++ WRITECC32(devinfo, watchdog, 4);
++ msleep(100);
++
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
++ BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, lsc);
++
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
++ for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR,
++ cfg_offset[i]);
++ val = brcmf_pcie_read_reg32(devinfo,
++ BRCMF_PCIE_PCIE2REG_CONFIGDATA);
++ brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
++ cfg_offset[i], val);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA,
++ val);
++ }
++}
++
++
++static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
++{
++ u32 config;
++
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
++ if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_INTMASK) != 0)
++ brcmf_pcie_reset_device(devinfo);
++ /* BAR1 window may not be sized properly */
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
++ config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
++
++ device_wakeup_enable(&devinfo->pdev->dev);
++}
++
++
++static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
++{
++ if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
++ 5);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
++ 0);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
++ 7);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
++ 0);
++ }
++ return 0;
++}
++
++
++static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
++ u32 resetintr)
++{
++ struct brcmf_core *core;
++
++ if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
++ core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
++ brcmf_chip_resetcore(core, 0, 0, 0);
++ }
++
++ return !brcmf_chip_set_active(devinfo->ci, resetintr);
++}
++
++
++static int
++brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
++{
++ struct brcmf_pcie_shared_info *shared;
++ u32 addr;
++ u32 cur_htod_mb_data;
++ u32 i;
++
++ shared = &devinfo->shared;
++ addr = shared->htod_mb_data_addr;
++ cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ if (cur_htod_mb_data != 0)
++ brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
++ cur_htod_mb_data);
++
++ i = 0;
++ while (cur_htod_mb_data != 0) {
++ msleep(10);
++ i++;
++ if (i > 100)
++ return -EIO;
++ cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
++ }
++
++ brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
++ pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
++ pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
++
++ return 0;
++}
++
++
++static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
++{
++ struct brcmf_pcie_shared_info *shared;
++ u32 addr;
++ u32 dtoh_mb_data;
++
++ shared = &devinfo->shared;
++ addr = shared->dtoh_mb_data_addr;
++ dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ if (!dtoh_mb_data)
++ return;
++
++ brcmf_pcie_write_tcm32(devinfo, addr, 0);
++
++ brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
++ if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ) {
++ brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
++ brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
++ brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
++ }
++ if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
++ brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
++ if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
++ brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
++ if (waitqueue_active(&devinfo->mbdata_resp_wait)) {
++ devinfo->mbdata_completed = true;
++ wake_up(&devinfo->mbdata_resp_wait);
++ }
++ }
++}
++
++
++static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
++{
++ struct brcmf_pcie_shared_info *shared;
++ struct brcmf_pcie_console *console;
++ u32 addr;
++
++ shared = &devinfo->shared;
++ console = &shared->console;
++ addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
++ console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
++ console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
++ addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
++ console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ brcmf_dbg(PCIE, "Console: base %x, buf %x, size %d\n",
++ console->base_addr, console->buf_addr, console->bufsize);
++}
++
++
++static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
++{
++ struct brcmf_pcie_console *console;
++ u32 addr;
++ u8 ch;
++ u32 newidx;
++
++ console = &devinfo->shared.console;
++ addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
++ newidx = brcmf_pcie_read_tcm32(devinfo, addr);
++ while (newidx != console->read_idx) {
++ addr = console->buf_addr + console->read_idx;
++ ch = brcmf_pcie_read_tcm8(devinfo, addr);
++ console->read_idx++;
++ if (console->read_idx == console->bufsize)
++ console->read_idx = 0;
++ if (ch == '\r')
++ continue;
++ console->log_str[console->log_idx] = ch;
++ console->log_idx++;
++ if ((ch != '\n') &&
++ (console->log_idx == (sizeof(console->log_str) - 2))) {
++ ch = '\n';
++ console->log_str[console->log_idx] = ch;
++ console->log_idx++;
++ }
++ if (ch == '\n') {
++ console->log_str[console->log_idx] = 0;
++ brcmf_dbg(PCIE, "CONSOLE: %s", console->log_str);
++ console->log_idx = 0;
++ }
++ }
++}
++
++
++static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
++{
++ u32 reg_value;
++
++ brcmf_dbg(PCIE, "RING !\n");
++ reg_value = brcmf_pcie_read_reg32(devinfo,
++ BRCMF_PCIE_PCIE2REG_MAILBOXINT);
++ reg_value |= BRCMF_PCIE2_INTB;
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
++ reg_value);
++}
++
++
++static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
++{
++ brcmf_dbg(PCIE, "RING !\n");
++ /* Any arbitrary value will do, lets use 1 */
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
++}
++
++
++static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
++{
++ if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
++ pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
++ 0);
++ else
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
++ 0);
++}
++
++
++static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
++{
++ if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
++ pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
++ BRCMF_PCIE_INT_DEF);
++ else
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
++ BRCMF_PCIE_MB_INT_D2H_DB |
++ BRCMF_PCIE_MB_INT_FN0_0 |
++ BRCMF_PCIE_MB_INT_FN0_1);
++}
++
++
++static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
++ u32 status;
++
++ status = 0;
++ pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
++ if (status) {
++ brcmf_pcie_intr_disable(devinfo);
++ brcmf_dbg(PCIE, "Enter\n");
++ return IRQ_WAKE_THREAD;
++ }
++ return IRQ_NONE;
++}
++
++
++static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
++
++ if (brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT)) {
++ brcmf_pcie_intr_disable(devinfo);
++ brcmf_dbg(PCIE, "Enter\n");
++ return IRQ_WAKE_THREAD;
++ }
++ return IRQ_NONE;
++}
++
++
++static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
++ const struct pci_dev *pdev = devinfo->pdev;
++ u32 status;
++
++ devinfo->in_irq = true;
++ status = 0;
++ pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
++ brcmf_dbg(PCIE, "Enter %x\n", status);
++ if (status) {
++ pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
++ if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
++ brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
++ }
++ if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
++ brcmf_pcie_intr_enable(devinfo);
++ devinfo->in_irq = false;
++ return IRQ_HANDLED;
++}
++
++
++static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
++ u32 status;
++
++ devinfo->in_irq = true;
++ status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
++ brcmf_dbg(PCIE, "Enter %x\n", status);
++ if (status) {
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
++ status);
++ if (status & (BRCMF_PCIE_MB_INT_FN0_0 |
++ BRCMF_PCIE_MB_INT_FN0_1))
++ brcmf_pcie_handle_mb_data(devinfo);
++ if (status & BRCMF_PCIE_MB_INT_D2H_DB) {
++ if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
++ brcmf_proto_msgbuf_rx_trigger(
++ &devinfo->pdev->dev);
++ }
++ }
++ brcmf_pcie_bus_console_read(devinfo);
++ if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
++ brcmf_pcie_intr_enable(devinfo);
++ devinfo->in_irq = false;
++ return IRQ_HANDLED;
++}
++
++
++static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
++{
++ struct pci_dev *pdev;
++
++ pdev = devinfo->pdev;
++
++ brcmf_pcie_intr_disable(devinfo);
++
++ brcmf_dbg(PCIE, "Enter\n");
++ /* is it a v1 or v2 implementation */
++ devinfo->irq_requested = false;
++ pci_enable_msi(pdev);
++ if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
++ if (request_threaded_irq(pdev->irq,
++ brcmf_pcie_quick_check_isr_v1,
++ brcmf_pcie_isr_thread_v1,
++ IRQF_SHARED, "brcmf_pcie_intr",
++ devinfo)) {
++ pci_disable_msi(pdev);
++ brcmf_err("Failed to request IRQ %d\n", pdev->irq);
++ return -EIO;
++ }
++ } else {
++ if (request_threaded_irq(pdev->irq,
++ brcmf_pcie_quick_check_isr_v2,
++ brcmf_pcie_isr_thread_v2,
++ IRQF_SHARED, "brcmf_pcie_intr",
++ devinfo)) {
++ pci_disable_msi(pdev);
++ brcmf_err("Failed to request IRQ %d\n", pdev->irq);
++ return -EIO;
++ }
++ }
++ devinfo->irq_requested = true;
++ devinfo->irq_allocated = true;
++ return 0;
++}
++
++
++static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
++{
++ struct pci_dev *pdev;
++ u32 status;
++ u32 count;
++
++ if (!devinfo->irq_allocated)
++ return;
++
++ pdev = devinfo->pdev;
++
++ brcmf_pcie_intr_disable(devinfo);
++ if (!devinfo->irq_requested)
++ return;
++ devinfo->irq_requested = false;
++ free_irq(pdev->irq, devinfo);
++ pci_disable_msi(pdev);
++
++ msleep(50);
++ count = 0;
++ while ((devinfo->in_irq) && (count < 20)) {
++ msleep(50);
++ count++;
++ }
++ if (devinfo->in_irq)
++ brcmf_err("Still in IRQ (processing) !!!\n");
++
++ if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
++ status = 0;
++ pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
++ pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
++ } else {
++ status = brcmf_pcie_read_reg32(devinfo,
++ BRCMF_PCIE_PCIE2REG_MAILBOXINT);
++ brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
++ status);
++ }
++ devinfo->irq_allocated = false;
++}
++
++
++static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
++{
++ struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
++ struct brcmf_pciedev_info *devinfo = ring->devinfo;
++ struct brcmf_commonring *commonring = &ring->commonring;
++
++ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
++ return -EIO;
++
++ brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
++ commonring->w_ptr, ring->id);
++
++ devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
++
++ return 0;
++}
++
++
++static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
++{
++ struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
++ struct brcmf_pciedev_info *devinfo = ring->devinfo;
++ struct brcmf_commonring *commonring = &ring->commonring;
++
++ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
++ return -EIO;
++
++ brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
++ commonring->r_ptr, ring->id);
++
++ devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
++
++ return 0;
++}
++
++
++static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
++{
++ struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
++ struct brcmf_pciedev_info *devinfo = ring->devinfo;
++
++ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
++ return -EIO;
++
++ devinfo->ringbell(devinfo);
++
++ return 0;
++}
++
++
++static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
++{
++ struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
++ struct brcmf_pciedev_info *devinfo = ring->devinfo;
++ struct brcmf_commonring *commonring = &ring->commonring;
++
++ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
++ return -EIO;
++
++ commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
++
++ brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
++ commonring->w_ptr, ring->id);
++
++ return 0;
++}
++
++
++static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
++{
++ struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
++ struct brcmf_pciedev_info *devinfo = ring->devinfo;
++ struct brcmf_commonring *commonring = &ring->commonring;
++
++ if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
++ return -EIO;
++
++ commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
++
++ brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
++ commonring->r_ptr, ring->id);
++
++ return 0;
++}
++
++
++static void *
++brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
++ u32 size, u32 tcm_dma_phys_addr,
++ dma_addr_t *dma_handle)
++{
++ void *ring;
++ u64 address;
++
++ ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
++ GFP_KERNEL);
++ if (!ring)
++ return NULL;
++
++ address = (u64)*dma_handle;
++ brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
++ address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
++
++ memset(ring, 0, size);
++
++ return (ring);
++}
++
++
++static struct brcmf_pcie_ringbuf *
++brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
++ u32 tcm_ring_phys_addr)
++{
++ void *dma_buf;
++ dma_addr_t dma_handle;
++ struct brcmf_pcie_ringbuf *ring;
++ u32 size;
++ u32 addr;
++
++ size = brcmf_ring_max_item[ring_id] * brcmf_ring_itemsize[ring_id];
++ dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
++ tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
++ &dma_handle);
++ if (!dma_buf)
++ return NULL;
++
++ addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
++ brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
++ addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
++ brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_itemsize[ring_id]);
++
++ ring = kzalloc(sizeof(*ring), GFP_KERNEL);
++ if (!ring) {
++ dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
++ dma_handle);
++ return NULL;
++ }
++ brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
++ brcmf_ring_itemsize[ring_id], dma_buf);
++ ring->dma_handle = dma_handle;
++ ring->devinfo = devinfo;
++ brcmf_commonring_register_cb(&ring->commonring,
++ brcmf_pcie_ring_mb_ring_bell,
++ brcmf_pcie_ring_mb_update_rptr,
++ brcmf_pcie_ring_mb_update_wptr,
++ brcmf_pcie_ring_mb_write_rptr,
++ brcmf_pcie_ring_mb_write_wptr, ring);
++
++ return (ring);
++}
++
++
++static void brcmf_pcie_release_ringbuffer(struct device *dev,
++ struct brcmf_pcie_ringbuf *ring)
++{
++ void *dma_buf;
++ u32 size;
++
++ if (!ring)
++ return;
++
++ dma_buf = ring->commonring.buf_addr;
++ if (dma_buf) {
++ size = ring->commonring.depth * ring->commonring.item_len;
++ dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
++ }
++ kfree(ring);
++}
++
++
++static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
++{
++ u32 i;
++
++ for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
++ brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
++ devinfo->shared.commonrings[i]);
++ devinfo->shared.commonrings[i] = NULL;
++ }
++ kfree(devinfo->shared.flowrings);
++ devinfo->shared.flowrings = NULL;
++ if (devinfo->idxbuf) {
++ dma_free_coherent(&devinfo->pdev->dev,
++ devinfo->idxbuf_sz,
++ devinfo->idxbuf,
++ devinfo->idxbuf_dmahandle);
++ devinfo->idxbuf = NULL;
++ }
++}
++
++
++static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
++{
++ struct brcmf_pcie_ringbuf *ring;
++ struct brcmf_pcie_ringbuf *rings;
++ u32 ring_addr;
++ u32 d2h_w_idx_ptr;
++ u32 d2h_r_idx_ptr;
++ u32 h2d_w_idx_ptr;
++ u32 h2d_r_idx_ptr;
++ u32 addr;
++ u32 ring_mem_ptr;
++ u32 i;
++ u64 address;
++ u32 bufsz;
++ u16 max_sub_queues;
++ u8 idx_offset;
++
++ ring_addr = devinfo->shared.ring_info_addr;
++ brcmf_dbg(PCIE, "Base ring addr = 0x%08x\n", ring_addr);
++ addr = ring_addr + BRCMF_SHARED_RING_MAX_SUB_QUEUES;
++ max_sub_queues = brcmf_pcie_read_tcm16(devinfo, addr);
++
++ if (devinfo->dma_idx_sz != 0) {
++ bufsz = (BRCMF_NROF_D2H_COMMON_MSGRINGS + max_sub_queues) *
++ devinfo->dma_idx_sz * 2;
++ devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
++ &devinfo->idxbuf_dmahandle,
++ GFP_KERNEL);
++ if (!devinfo->idxbuf)
++ devinfo->dma_idx_sz = 0;
++ }
++
++ if (devinfo->dma_idx_sz == 0) {
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_W_IDX_PTR_OFFSET;
++ d2h_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_R_IDX_PTR_OFFSET;
++ d2h_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_W_IDX_PTR_OFFSET;
++ h2d_w_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_R_IDX_PTR_OFFSET;
++ h2d_r_idx_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++ idx_offset = sizeof(u32);
++ devinfo->write_ptr = brcmf_pcie_write_tcm16;
++ devinfo->read_ptr = brcmf_pcie_read_tcm16;
++ brcmf_dbg(PCIE, "Using TCM indices\n");
++ } else {
++ memset(devinfo->idxbuf, 0, bufsz);
++ devinfo->idxbuf_sz = bufsz;
++ idx_offset = devinfo->dma_idx_sz;
++ devinfo->write_ptr = brcmf_pcie_write_idx;
++ devinfo->read_ptr = brcmf_pcie_read_idx;
++
++ h2d_w_idx_ptr = 0;
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_WP_HADDR_OFFSET;
++ address = (u64)devinfo->idxbuf_dmahandle;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++
++ h2d_r_idx_ptr = h2d_w_idx_ptr + max_sub_queues * idx_offset;
++ addr = ring_addr + BRCMF_SHARED_RING_H2D_RP_HADDR_OFFSET;
++ address += max_sub_queues * idx_offset;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++
++ d2h_w_idx_ptr = h2d_r_idx_ptr + max_sub_queues * idx_offset;
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_WP_HADDR_OFFSET;
++ address += max_sub_queues * idx_offset;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++
++ d2h_r_idx_ptr = d2h_w_idx_ptr +
++ BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
++ addr = ring_addr + BRCMF_SHARED_RING_D2H_RP_HADDR_OFFSET;
++ address += BRCMF_NROF_D2H_COMMON_MSGRINGS * idx_offset;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++ brcmf_dbg(PCIE, "Using host memory indices\n");
++ }
++
++ addr = ring_addr + BRCMF_SHARED_RING_TCM_MEMLOC_OFFSET;
++ ring_mem_ptr = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
++ ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
++ if (!ring)
++ goto fail;
++ ring->w_idx_addr = h2d_w_idx_ptr;
++ ring->r_idx_addr = h2d_r_idx_ptr;
++ ring->id = i;
++ devinfo->shared.commonrings[i] = ring;
++
++ h2d_w_idx_ptr += idx_offset;
++ h2d_r_idx_ptr += idx_offset;
++ ring_mem_ptr += BRCMF_RING_MEM_SZ;
++ }
++
++ for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
++ i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
++ ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
++ if (!ring)
++ goto fail;
++ ring->w_idx_addr = d2h_w_idx_ptr;
++ ring->r_idx_addr = d2h_r_idx_ptr;
++ ring->id = i;
++ devinfo->shared.commonrings[i] = ring;
++
++ d2h_w_idx_ptr += idx_offset;
++ d2h_r_idx_ptr += idx_offset;
++ ring_mem_ptr += BRCMF_RING_MEM_SZ;
++ }
++
++ devinfo->shared.nrof_flowrings =
++ max_sub_queues - BRCMF_NROF_H2D_COMMON_MSGRINGS;
++ rings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*ring),
++ GFP_KERNEL);
++ if (!rings)
++ goto fail;
++
++ brcmf_dbg(PCIE, "Nr of flowrings is %d\n",
++ devinfo->shared.nrof_flowrings);
++
++ for (i = 0; i < devinfo->shared.nrof_flowrings; i++) {
++ ring = &rings[i];
++ ring->devinfo = devinfo;
++ ring->id = i + BRCMF_NROF_COMMON_MSGRINGS;
++ brcmf_commonring_register_cb(&ring->commonring,
++ brcmf_pcie_ring_mb_ring_bell,
++ brcmf_pcie_ring_mb_update_rptr,
++ brcmf_pcie_ring_mb_update_wptr,
++ brcmf_pcie_ring_mb_write_rptr,
++ brcmf_pcie_ring_mb_write_wptr,
++ ring);
++ ring->w_idx_addr = h2d_w_idx_ptr;
++ ring->r_idx_addr = h2d_r_idx_ptr;
++ h2d_w_idx_ptr += idx_offset;
++ h2d_r_idx_ptr += idx_offset;
++ }
++ devinfo->shared.flowrings = rings;
++
++ return 0;
++
++fail:
++ brcmf_err("Allocating ring buffers failed\n");
++ brcmf_pcie_release_ringbuffers(devinfo);
++ return -ENOMEM;
++}
++
++
++static void
++brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
++{
++ if (devinfo->shared.scratch)
++ dma_free_coherent(&devinfo->pdev->dev,
++ BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
++ devinfo->shared.scratch,
++ devinfo->shared.scratch_dmahandle);
++ if (devinfo->shared.ringupd)
++ dma_free_coherent(&devinfo->pdev->dev,
++ BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
++ devinfo->shared.ringupd,
++ devinfo->shared.ringupd_dmahandle);
++}
++
++static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
++{
++ u64 address;
++ u32 addr;
++
++ devinfo->shared.scratch = dma_alloc_coherent(&devinfo->pdev->dev,
++ BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
++ &devinfo->shared.scratch_dmahandle, GFP_KERNEL);
++ if (!devinfo->shared.scratch)
++ goto fail;
++
++ memset(devinfo->shared.scratch, 0, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
++
++ addr = devinfo->shared.tcm_base_address +
++ BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
++ address = (u64)devinfo->shared.scratch_dmahandle;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++ addr = devinfo->shared.tcm_base_address +
++ BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
++ brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
++
++ devinfo->shared.ringupd = dma_alloc_coherent(&devinfo->pdev->dev,
++ BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
++ &devinfo->shared.ringupd_dmahandle, GFP_KERNEL);
++ if (!devinfo->shared.ringupd)
++ goto fail;
++
++ memset(devinfo->shared.ringupd, 0, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
++
++ addr = devinfo->shared.tcm_base_address +
++ BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
++ address = (u64)devinfo->shared.ringupd_dmahandle;
++ brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
++ brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
++ addr = devinfo->shared.tcm_base_address +
++ BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
++ brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
++ return 0;
++
++fail:
++ brcmf_err("Allocating scratch buffers failed\n");
++ brcmf_pcie_release_scratchbuffers(devinfo);
++ return -ENOMEM;
++}
++
++
++static void brcmf_pcie_down(struct device *dev)
++{
++}
++
++
++static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
++{
++ return 0;
++}
++
++
++static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
++ uint len)
++{
++ return 0;
++}
++
++
++static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
++ uint len)
++{
++ return 0;
++}
++
++
++static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
++ struct brcmf_pciedev_info *devinfo = buspub->devinfo;
++
++ brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
++ devinfo->wowl_enabled = enabled;
++ if (enabled)
++ device_set_wakeup_enable(&devinfo->pdev->dev, true);
++ else
++ device_set_wakeup_enable(&devinfo->pdev->dev, false);
++}
++
++
++static struct brcmf_bus_ops brcmf_pcie_bus_ops = {
++ .txdata = brcmf_pcie_tx,
++ .stop = brcmf_pcie_down,
++ .txctl = brcmf_pcie_tx_ctlpkt,
++ .rxctl = brcmf_pcie_rx_ctlpkt,
++ .wowl_config = brcmf_pcie_wowl_config,
++};
++
++
++static int
++brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
++ u32 sharedram_addr)
++{
++ struct brcmf_pcie_shared_info *shared;
++ u32 addr;
++ u32 version;
++
++ shared = &devinfo->shared;
++ shared->tcm_base_address = sharedram_addr;
++
++ shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
++ version = shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK;
++ brcmf_dbg(PCIE, "PCIe protocol version %d\n", version);
++ if ((version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
++ (version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
++ brcmf_err("Unsupported PCIE version %d\n", version);
++ return -EINVAL;
++ }
++
++ /* check firmware support dma indicies */
++ if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
++ if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
++ devinfo->dma_idx_sz = sizeof(u16);
++ else
++ devinfo->dma_idx_sz = sizeof(u32);
++ }
++
++ addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
++ shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
++ if (shared->max_rxbufpost == 0)
++ shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
++
++ addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
++ shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
++ shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
++ shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
++ shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
++
++ brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
++ shared->max_rxbufpost, shared->rx_dataoffset);
++
++ brcmf_pcie_bus_console_init(devinfo);
++
++ return 0;
++}
++
++
++static int brcmf_pcie_get_fwnames(struct brcmf_pciedev_info *devinfo)
++{
++ char *fw_name;
++ char *nvram_name;
++ uint fw_len, nv_len;
++ char end;
++
++ brcmf_dbg(PCIE, "Enter, chip 0x%04x chiprev %d\n", devinfo->ci->chip,
++ devinfo->ci->chiprev);
++
++ switch (devinfo->ci->chip) {
++ case BRCM_CC_43602_CHIP_ID:
++ fw_name = BRCMF_PCIE_43602_FW_NAME;
++ nvram_name = BRCMF_PCIE_43602_NVRAM_NAME;
++ break;
++ case BRCM_CC_4356_CHIP_ID:
++ fw_name = BRCMF_PCIE_4356_FW_NAME;
++ nvram_name = BRCMF_PCIE_4356_NVRAM_NAME;
++ break;
++ case BRCM_CC_43567_CHIP_ID:
++ case BRCM_CC_43569_CHIP_ID:
++ case BRCM_CC_43570_CHIP_ID:
++ fw_name = BRCMF_PCIE_43570_FW_NAME;
++ nvram_name = BRCMF_PCIE_43570_NVRAM_NAME;
++ break;
++ default:
++ brcmf_err("Unsupported chip 0x%04x\n", devinfo->ci->chip);
++ return -ENODEV;
++ }
++
++ fw_len = sizeof(devinfo->fw_name) - 1;
++ nv_len = sizeof(devinfo->nvram_name) - 1;
++ /* check if firmware path is provided by module parameter */
++ if (brcmf_firmware_path[0] != '\0') {
++ strncpy(devinfo->fw_name, brcmf_firmware_path, fw_len);
++ strncpy(devinfo->nvram_name, brcmf_firmware_path, nv_len);
++ fw_len -= strlen(devinfo->fw_name);
++ nv_len -= strlen(devinfo->nvram_name);
++
++ end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
++ if (end != '/') {
++ strncat(devinfo->fw_name, "/", fw_len);
++ strncat(devinfo->nvram_name, "/", nv_len);
++ fw_len--;
++ nv_len--;
++ }
++ }
++ strncat(devinfo->fw_name, fw_name, fw_len);
++ strncat(devinfo->nvram_name, nvram_name, nv_len);
++
++ return 0;
++}
++
++
++static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
++ const struct firmware *fw, void *nvram,
++ u32 nvram_len)
++{
++ u32 sharedram_addr;
++ u32 sharedram_addr_written;
++ u32 loop_counter;
++ int err;
++ u32 address;
++ u32 resetintr;
++
++ devinfo->ringbell = brcmf_pcie_ringbell_v2;
++ devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
++
++ brcmf_dbg(PCIE, "Halt ARM.\n");
++ err = brcmf_pcie_enter_download_state(devinfo);
++ if (err)
++ return err;
++
++ brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
++ brcmf_pcie_copy_mem_todev(devinfo, devinfo->ci->rambase,
++ (void *)fw->data, fw->size);
++
++ resetintr = get_unaligned_le32(fw->data);
++ release_firmware(fw);
++
++ /* reset last 4 bytes of RAM address. to be used for shared
++ * area. This identifies when FW is running
++ */
++ brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
++
++ if (nvram) {
++ brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
++ address = devinfo->ci->rambase + devinfo->ci->ramsize -
++ nvram_len;
++ brcmf_pcie_copy_mem_todev(devinfo, address, nvram, nvram_len);
++ brcmf_fw_nvram_free(nvram);
++ } else {
++ brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
++ devinfo->nvram_name);
++ }
++
++ sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
++ devinfo->ci->ramsize -
++ 4);
++ brcmf_dbg(PCIE, "Bring ARM in running state\n");
++ err = brcmf_pcie_exit_download_state(devinfo, resetintr);
++ if (err)
++ return err;
++
++ brcmf_dbg(PCIE, "Wait for FW init\n");
++ sharedram_addr = sharedram_addr_written;
++ loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
++ while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
++ msleep(50);
++ sharedram_addr = brcmf_pcie_read_ram32(devinfo,
++ devinfo->ci->ramsize -
++ 4);
++ loop_counter--;
++ }
++ if (sharedram_addr == sharedram_addr_written) {
++ brcmf_err("FW failed to initialize\n");
++ return -ENODEV;
++ }
++ brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
++
++ return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
++}
++
++
++static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
++{
++ struct pci_dev *pdev;
++ int err;
++ phys_addr_t bar0_addr, bar1_addr;
++ ulong bar1_size;
++
++ pdev = devinfo->pdev;
++
++ err = pci_enable_device(pdev);
++ if (err) {
++ brcmf_err("pci_enable_device failed err=%d\n", err);
++ return err;
++ }
++
++ pci_set_master(pdev);
++
++ /* Bar-0 mapped address */
++ bar0_addr = pci_resource_start(pdev, 0);
++ /* Bar-1 mapped address */
++ bar1_addr = pci_resource_start(pdev, 2);
++ /* read Bar-1 mapped memory range */
++ bar1_size = pci_resource_len(pdev, 2);
++ if ((bar1_size == 0) || (bar1_addr == 0)) {
++ brcmf_err("BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
++ bar1_size, (unsigned long long)bar1_addr);
++ return -EINVAL;
++ }
++
++ devinfo->regs = ioremap_nocache(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
++ devinfo->tcm = ioremap_nocache(bar1_addr, BRCMF_PCIE_TCM_MAP_SIZE);
++ devinfo->tcm_size = BRCMF_PCIE_TCM_MAP_SIZE;
++
++ if (!devinfo->regs || !devinfo->tcm) {
++ brcmf_err("ioremap() failed (%p,%p)\n", devinfo->regs,
++ devinfo->tcm);
++ return -EINVAL;
++ }
++ brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
++ devinfo->regs, (unsigned long long)bar0_addr);
++ brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx\n",
++ devinfo->tcm, (unsigned long long)bar1_addr);
++
++ return 0;
++}
++
++
++static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
++{
++ if (devinfo->tcm)
++ iounmap(devinfo->tcm);
++ if (devinfo->regs)
++ iounmap(devinfo->regs);
++
++ pci_disable_device(devinfo->pdev);
++}
++
++
++static int brcmf_pcie_attach_bus(struct device *dev)
++{
++ int ret;
++
++ /* Attach to the common driver interface */
++ ret = brcmf_attach(dev);
++ if (ret) {
++ brcmf_err("brcmf_attach failed\n");
++ } else {
++ ret = brcmf_bus_start(dev);
++ if (ret)
++ brcmf_err("dongle is not responding\n");
++ }
++
++ return ret;
++}
++
++
++static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
++{
++ u32 ret_addr;
++
++ ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
++ addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
++ pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
++
++ return ret_addr;
++}
++
++
++static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
++
++ addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
++ return brcmf_pcie_read_reg32(devinfo, addr);
++}
++
++
++static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
++
++ addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
++ brcmf_pcie_write_reg32(devinfo, addr, value);
++}
++
++
++static int brcmf_pcie_buscoreprep(void *ctx)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
++ int err;
++
++ err = brcmf_pcie_get_resource(devinfo);
++ if (err == 0) {
++ /* Set CC watchdog to reset all the cores on the chip to bring
++ * back dongle to a sane state.
++ */
++ brcmf_pcie_buscore_write32(ctx, CORE_CC_REG(SI_ENUM_BASE,
++ watchdog), 4);
++ msleep(100);
++ }
++
++ return err;
++}
++
++
++static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
++ u32 rstvec)
++{
++ struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
++
++ brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
++}
++
++
++static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
++ .prepare = brcmf_pcie_buscoreprep,
++ .activate = brcmf_pcie_buscore_activate,
++ .read32 = brcmf_pcie_buscore_read32,
++ .write32 = brcmf_pcie_buscore_write32,
++};
++
++static void brcmf_pcie_setup(struct device *dev, const struct firmware *fw,
++ void *nvram, u32 nvram_len)
++{
++ struct brcmf_bus *bus = dev_get_drvdata(dev);
++ struct brcmf_pciedev *pcie_bus_dev = bus->bus_priv.pcie;
++ struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
++ struct brcmf_commonring **flowrings;
++ int ret;
++ u32 i;
++
++ brcmf_pcie_attach(devinfo);
++
++ ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
++ if (ret)
++ goto fail;
++
++ devinfo->state = BRCMFMAC_PCIE_STATE_UP;
++
++ ret = brcmf_pcie_init_ringbuffers(devinfo);
++ if (ret)
++ goto fail;
++
++ ret = brcmf_pcie_init_scratchbuffers(devinfo);
++ if (ret)
++ goto fail;
++
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
++ ret = brcmf_pcie_request_irq(devinfo);
++ if (ret)
++ goto fail;
++
++ /* hook the commonrings in the bus structure. */
++ for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
++ bus->msgbuf->commonrings[i] =
++ &devinfo->shared.commonrings[i]->commonring;
++
++ flowrings = kcalloc(devinfo->shared.nrof_flowrings, sizeof(*flowrings),
++ GFP_KERNEL);
++ if (!flowrings)
++ goto fail;
++
++ for (i = 0; i < devinfo->shared.nrof_flowrings; i++)
++ flowrings[i] = &devinfo->shared.flowrings[i].commonring;
++ bus->msgbuf->flowrings = flowrings;
++
++ bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
++ bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
++ bus->msgbuf->nrof_flowrings = devinfo->shared.nrof_flowrings;
++
++ init_waitqueue_head(&devinfo->mbdata_resp_wait);
++
++ brcmf_pcie_intr_enable(devinfo);
++ if (brcmf_pcie_attach_bus(bus->dev) == 0)
++ return;
++
++ brcmf_pcie_bus_console_read(devinfo);
++
++fail:
++ device_release_driver(dev);
++}
++
++static int
++brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
++{
++ int ret;
++ struct brcmf_pciedev_info *devinfo;
++ struct brcmf_pciedev *pcie_bus_dev;
++ struct brcmf_bus *bus;
++ u16 domain_nr;
++ u16 bus_nr;
++
++ domain_nr = pci_domain_nr(pdev->bus) + 1;
++ bus_nr = pdev->bus->number;
++ brcmf_dbg(PCIE, "Enter %x:%x (%d/%d)\n", pdev->vendor, pdev->device,
++ domain_nr, bus_nr);
++
++ ret = -ENOMEM;
++ devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
++ if (devinfo == NULL)
++ return ret;
++
++ devinfo->pdev = pdev;
++ pcie_bus_dev = NULL;
++ devinfo->ci = brcmf_chip_attach(devinfo, &brcmf_pcie_buscore_ops);
++ if (IS_ERR(devinfo->ci)) {
++ ret = PTR_ERR(devinfo->ci);
++ devinfo->ci = NULL;
++ goto fail;
++ }
++
++ pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
++ if (pcie_bus_dev == NULL) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ bus = kzalloc(sizeof(*bus), GFP_KERNEL);
++ if (!bus) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++ bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
++ if (!bus->msgbuf) {
++ ret = -ENOMEM;
++ kfree(bus);
++ goto fail;
++ }
++
++ /* hook it all together. */
++ pcie_bus_dev->devinfo = devinfo;
++ pcie_bus_dev->bus = bus;
++ bus->dev = &pdev->dev;
++ bus->bus_priv.pcie = pcie_bus_dev;
++ bus->ops = &brcmf_pcie_bus_ops;
++ bus->proto_type = BRCMF_PROTO_MSGBUF;
++ bus->chip = devinfo->coreid;
++ bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
++ dev_set_drvdata(&pdev->dev, bus);
++
++ ret = brcmf_pcie_get_fwnames(devinfo);
++ if (ret)
++ goto fail_bus;
++
++ ret = brcmf_fw_get_firmwares_pcie(bus->dev, BRCMF_FW_REQUEST_NVRAM |
++ BRCMF_FW_REQ_NV_OPTIONAL,
++ devinfo->fw_name, devinfo->nvram_name,
++ brcmf_pcie_setup, domain_nr, bus_nr);
++ if (ret == 0)
++ return 0;
++fail_bus:
++ kfree(bus->msgbuf);
++ kfree(bus);
++fail:
++ brcmf_err("failed %x:%x\n", pdev->vendor, pdev->device);
++ brcmf_pcie_release_resource(devinfo);
++ if (devinfo->ci)
++ brcmf_chip_detach(devinfo->ci);
++ kfree(pcie_bus_dev);
++ kfree(devinfo);
++ return ret;
++}
++
++
++static void
++brcmf_pcie_remove(struct pci_dev *pdev)
++{
++ struct brcmf_pciedev_info *devinfo;
++ struct brcmf_bus *bus;
++
++ brcmf_dbg(PCIE, "Enter\n");
++
++ bus = dev_get_drvdata(&pdev->dev);
++ if (bus == NULL)
++ return;
++
++ devinfo = bus->bus_priv.pcie->devinfo;
++
++ devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
++ if (devinfo->ci)
++ brcmf_pcie_intr_disable(devinfo);
++
++ brcmf_detach(&pdev->dev);
++
++ kfree(bus->bus_priv.pcie);
++ kfree(bus->msgbuf->flowrings);
++ kfree(bus->msgbuf);
++ kfree(bus);
++
++ brcmf_pcie_release_irq(devinfo);
++ brcmf_pcie_release_scratchbuffers(devinfo);
++ brcmf_pcie_release_ringbuffers(devinfo);
++ brcmf_pcie_reset_device(devinfo);
++ brcmf_pcie_release_resource(devinfo);
++
++ if (devinfo->ci)
++ brcmf_chip_detach(devinfo->ci);
++
++ kfree(devinfo);
++ dev_set_drvdata(&pdev->dev, NULL);
++}
++
++
++#ifdef CONFIG_PM
++
++
++static int brcmf_pcie_suspend(struct pci_dev *pdev, pm_message_t state)
++{
++ struct brcmf_pciedev_info *devinfo;
++ struct brcmf_bus *bus;
++ int err;
++
++ brcmf_dbg(PCIE, "Enter, state=%d, pdev=%p\n", state.event, pdev);
++
++ bus = dev_get_drvdata(&pdev->dev);
++ devinfo = bus->bus_priv.pcie->devinfo;
++
++ brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
++
++ devinfo->mbdata_completed = false;
++ brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
++
++ wait_event_timeout(devinfo->mbdata_resp_wait,
++ devinfo->mbdata_completed,
++ msecs_to_jiffies(BRCMF_PCIE_MBDATA_TIMEOUT));
++ if (!devinfo->mbdata_completed) {
++ brcmf_err("Timeout on response for entering D3 substate\n");
++ return -EIO;
++ }
++ brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM_IN_USE);
++
++ err = pci_save_state(pdev);
++ if (err)
++ brcmf_err("pci_save_state failed, err=%d\n", err);
++ if ((err) || (!devinfo->wowl_enabled)) {
++ brcmf_chip_detach(devinfo->ci);
++ devinfo->ci = NULL;
++ brcmf_pcie_remove(pdev);
++ return 0;
++ }
++
++ return pci_prepare_to_sleep(pdev);
++}
++
++static int brcmf_pcie_resume(struct pci_dev *pdev)
++{
++ struct brcmf_pciedev_info *devinfo;
++ struct brcmf_bus *bus;
++ int err;
++
++ bus = dev_get_drvdata(&pdev->dev);
++ brcmf_dbg(PCIE, "Enter, pdev=%p, bus=%p\n", pdev, bus);
++
++ err = pci_set_power_state(pdev, PCI_D0);
++ if (err) {
++ brcmf_err("pci_set_power_state failed, err=%d\n", err);
++ goto cleanup;
++ }
++ pci_restore_state(pdev);
++ pci_enable_wake(pdev, PCI_D3hot, false);
++ pci_enable_wake(pdev, PCI_D3cold, false);
++
++ /* Check if device is still up and running, if so we are ready */
++ if (bus) {
++ devinfo = bus->bus_priv.pcie->devinfo;
++ if (brcmf_pcie_read_reg32(devinfo,
++ BRCMF_PCIE_PCIE2REG_INTMASK) != 0) {
++ if (brcmf_pcie_send_mb_data(devinfo,
++ BRCMF_H2D_HOST_D0_INFORM))
++ goto cleanup;
++ brcmf_dbg(PCIE, "Hot resume, continue....\n");
++ brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
++ brcmf_bus_change_state(bus, BRCMF_BUS_UP);
++ brcmf_pcie_intr_enable(devinfo);
++ return 0;
++ }
++ }
++
++cleanup:
++ if (bus) {
++ devinfo = bus->bus_priv.pcie->devinfo;
++ brcmf_chip_detach(devinfo->ci);
++ devinfo->ci = NULL;
++ brcmf_pcie_remove(pdev);
++ }
++ err = brcmf_pcie_probe(pdev, NULL);
++ if (err)
++ brcmf_err("probe after resume failed, err=%d\n", err);
++
++ return err;
++}
++
++
++#endif /* CONFIG_PM */
++
++
++#define BRCMF_PCIE_DEVICE(dev_id) { BRCM_PCIE_VENDOR_ID_BROADCOM, dev_id,\
++ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, 0 }
++
++static struct pci_device_id brcmf_pcie_devid_table[] = {
++ BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID),
++ BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID),
++ BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID),
++ BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID),
++ BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID),
++ BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID),
++ { /* end: all zeroes */ }
++};
++
++
++MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
++
++
++static struct pci_driver brcmf_pciedrvr = {
++ .node = {},
++ .name = KBUILD_MODNAME,
++ .id_table = brcmf_pcie_devid_table,
++ .probe = brcmf_pcie_probe,
++ .remove = brcmf_pcie_remove,
++#ifdef CONFIG_PM
++ .suspend = brcmf_pcie_suspend,
++ .resume = brcmf_pcie_resume
++#endif /* CONFIG_PM */
++};
++
++
++void brcmf_pcie_register(void)
++{
++ int err;
++
++ brcmf_dbg(PCIE, "Enter\n");
++ err = pci_register_driver(&brcmf_pciedrvr);
++ if (err)
++ brcmf_err("PCIE driver registration failed, err=%d\n", err);
++}
++
++
++void brcmf_pcie_exit(void)
++{
++ brcmf_dbg(PCIE, "Enter\n");
++ pci_unregister_driver(&brcmf_pciedrvr);
++}
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/pcie.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/pcie.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/pcie.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/pcie.h 2016-06-19 22:11:55.289141057 +0200
+@@ -0,0 +1,29 @@
++/* Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++#ifndef BRCMFMAC_PCIE_H
++#define BRCMFMAC_PCIE_H
++
++
++struct brcmf_pciedev {
++ struct brcmf_bus *bus;
++ struct brcmf_pciedev_info *devinfo;
++};
++
++
++void brcmf_pcie_exit(void);
++void brcmf_pcie_register(void);
++
++
++#endif /* BRCMFMAC_PCIE_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/proto.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/proto.c 2016-06-19 22:11:55.289141057 +0200
+@@ -20,27 +20,41 @@
+ #include <linux/netdevice.h>
+
+ #include <brcmu_wifi.h>
+-#include "dhd.h"
+-#include "dhd_dbg.h"
++#include "core.h"
++#include "bus.h"
++#include "debug.h"
+ #include "proto.h"
+ #include "bcdc.h"
++#include "msgbuf.h"
+
+
+ int brcmf_proto_attach(struct brcmf_pub *drvr)
+ {
+ struct brcmf_proto *proto;
+
++ brcmf_dbg(TRACE, "Enter\n");
++
+ proto = kzalloc(sizeof(*proto), GFP_ATOMIC);
+ if (!proto)
+ goto fail;
+
+ drvr->proto = proto;
+- /* BCDC protocol is only protocol supported for the moment */
+- if (brcmf_proto_bcdc_attach(drvr))
+- goto fail;
+
++ if (drvr->bus_if->proto_type == BRCMF_PROTO_BCDC) {
++ if (brcmf_proto_bcdc_attach(drvr))
++ goto fail;
++ } else if (drvr->bus_if->proto_type == BRCMF_PROTO_MSGBUF) {
++ if (brcmf_proto_msgbuf_attach(drvr))
++ goto fail;
++ } else {
++ brcmf_err("Unsupported proto type %d\n",
++ drvr->bus_if->proto_type);
++ goto fail;
++ }
+ if ((proto->txdata == NULL) || (proto->hdrpull == NULL) ||
+- (proto->query_dcmd == NULL) || (proto->set_dcmd == NULL)) {
++ (proto->query_dcmd == NULL) || (proto->set_dcmd == NULL) ||
++ (proto->configure_addr_mode == NULL) ||
++ (proto->delete_peer == NULL) || (proto->add_tdls_peer == NULL)) {
+ brcmf_err("Not all proto handlers have been installed\n");
+ goto fail;
+ }
+@@ -54,8 +68,13 @@
+
+ void brcmf_proto_detach(struct brcmf_pub *drvr)
+ {
++ brcmf_dbg(TRACE, "Enter\n");
++
+ if (drvr->proto) {
+- brcmf_proto_bcdc_detach(drvr);
++ if (drvr->bus_if->proto_type == BRCMF_PROTO_BCDC)
++ brcmf_proto_bcdc_detach(drvr);
++ else if (drvr->bus_if->proto_type == BRCMF_PROTO_MSGBUF)
++ brcmf_proto_msgbuf_detach(drvr);
+ kfree(drvr->proto);
+ drvr->proto = NULL;
+ }
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/proto.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/proto.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/proto.h 2016-06-19 22:11:55.289141057 +0200
+@@ -16,6 +16,13 @@
+ #ifndef BRCMFMAC_PROTO_H
+ #define BRCMFMAC_PROTO_H
+
++
++enum proto_addr_mode {
++ ADDR_INDIRECT = 0,
++ ADDR_DIRECT
++};
++
++
+ struct brcmf_proto {
+ int (*hdrpull)(struct brcmf_pub *drvr, bool do_fws, u8 *ifidx,
+ struct sk_buff *skb);
+@@ -25,6 +32,12 @@
+ uint len);
+ int (*txdata)(struct brcmf_pub *drvr, int ifidx, u8 offset,
+ struct sk_buff *skb);
++ void (*configure_addr_mode)(struct brcmf_pub *drvr, int ifidx,
++ enum proto_addr_mode addr_mode);
++ void (*delete_peer)(struct brcmf_pub *drvr, int ifidx,
++ u8 peer[ETH_ALEN]);
++ void (*add_tdls_peer)(struct brcmf_pub *drvr, int ifidx,
++ u8 peer[ETH_ALEN]);
+ void *pd;
+ };
+
+@@ -48,10 +61,26 @@
+ return drvr->proto->set_dcmd(drvr, ifidx, cmd, buf, len);
+ }
+ static inline int brcmf_proto_txdata(struct brcmf_pub *drvr, int ifidx,
+- u8 offset, struct sk_buff *skb)
++ u8 offset, struct sk_buff *skb)
+ {
+ return drvr->proto->txdata(drvr, ifidx, offset, skb);
+ }
++static inline void
++brcmf_proto_configure_addr_mode(struct brcmf_pub *drvr, int ifidx,
++ enum proto_addr_mode addr_mode)
++{
++ drvr->proto->configure_addr_mode(drvr, ifidx, addr_mode);
++}
++static inline void
++brcmf_proto_delete_peer(struct brcmf_pub *drvr, int ifidx, u8 peer[ETH_ALEN])
++{
++ drvr->proto->delete_peer(drvr, ifidx, peer);
++}
++static inline void
++brcmf_proto_add_tdls_peer(struct brcmf_pub *drvr, int ifidx, u8 peer[ETH_ALEN])
++{
++ drvr->proto->add_tdls_peer(drvr, ifidx, peer);
++}
+
+
+ #endif /* BRCMFMAC_PROTO_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio.c 2016-06-19 22:11:55.289141057 +0200
+@@ -0,0 +1,4323 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/kthread.h>
++#include <linux/printk.h>
++#include <linux/pci_ids.h>
++#include <linux/netdevice.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/mmc/sdio.h>
++#include <linux/mmc/sdio_ids.h>
++#include <linux/mmc/sdio_func.h>
++#include <linux/mmc/card.h>
++#include <linux/semaphore.h>
++#include <linux/firmware.h>
++#include <linux/module.h>
++#include <linux/bcma/bcma.h>
++#include <linux/debugfs.h>
++#include <linux/vmalloc.h>
++#include <linux/platform_data/brcmfmac-sdio.h>
++#include <linux/moduleparam.h>
++#include <asm/unaligned.h>
++#include <defs.h>
++#include <brcmu_wifi.h>
++#include <brcmu_utils.h>
++#include <brcm_hw_ids.h>
++#include <soc.h>
++#include "sdio.h"
++#include "chip.h"
++#include "firmware.h"
++
++#define DCMD_RESP_TIMEOUT 2000 /* In milli second */
++#define CTL_DONE_TIMEOUT 2000 /* In milli second */
++
++#ifdef DEBUG
++
++#define BRCMF_TRAP_INFO_SIZE 80
++
++#define CBUF_LEN (128)
++
++/* Device console log buffer state */
++#define CONSOLE_BUFFER_MAX 2024
++
++struct rte_log_le {
++ __le32 buf; /* Can't be pointer on (64-bit) hosts */
++ __le32 buf_size;
++ __le32 idx;
++ char *_buf_compat; /* Redundant pointer for backward compat. */
++};
++
++struct rte_console {
++ /* Virtual UART
++ * When there is no UART (e.g. Quickturn),
++ * the host should write a complete
++ * input line directly into cbuf and then write
++ * the length into vcons_in.
++ * This may also be used when there is a real UART
++ * (at risk of conflicting with
++ * the real UART). vcons_out is currently unused.
++ */
++ uint vcons_in;
++ uint vcons_out;
++
++ /* Output (logging) buffer
++ * Console output is written to a ring buffer log_buf at index log_idx.
++ * The host may read the output when it sees log_idx advance.
++ * Output will be lost if the output wraps around faster than the host
++ * polls.
++ */
++ struct rte_log_le log_le;
++
++ /* Console input line buffer
++ * Characters are read one at a time into cbuf
++ * until <CR> is received, then
++ * the buffer is processed as a command line.
++ * Also used for virtual UART.
++ */
++ uint cbuf_idx;
++ char cbuf[CBUF_LEN];
++};
++
++#endif /* DEBUG */
++#include <chipcommon.h>
++
++#include "bus.h"
++#include "debug.h"
++#include "tracepoint.h"
++
++#define TXQLEN 2048 /* bulk tx queue length */
++#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
++#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
++#define PRIOMASK 7
++
++#define TXRETRIES 2 /* # of retries for tx frames */
++
++#define BRCMF_RXBOUND 50 /* Default for max rx frames in
++ one scheduling */
++
++#define BRCMF_TXBOUND 20 /* Default for max tx frames in
++ one scheduling */
++
++#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
++
++#define MEMBLOCK 2048 /* Block size used for downloading
++ of dongle image */
++#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
++ biggest possible glom */
++
++#define BRCMF_FIRSTREAD (1 << 6)
++
++
++/* SBSDIO_DEVICE_CTL */
++
++/* 1: device will assert busy signal when receiving CMD53 */
++#define SBSDIO_DEVCTL_SETBUSY 0x01
++/* 1: assertion of sdio interrupt is synchronous to the sdio clock */
++#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
++/* 1: mask all interrupts to host except the chipActive (rev 8) */
++#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
++/* 1: isolate internal sdio signals, put external pads in tri-state; requires
++ * sdio bus power cycle to clear (rev 9) */
++#define SBSDIO_DEVCTL_PADS_ISO 0x08
++/* Force SD->SB reset mapping (rev 11) */
++#define SBSDIO_DEVCTL_SB_RST_CTL 0x30
++/* Determined by CoreControl bit */
++#define SBSDIO_DEVCTL_RST_CORECTL 0x00
++/* Force backplane reset */
++#define SBSDIO_DEVCTL_RST_BPRESET 0x10
++/* Force no backplane reset */
++#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
++
++/* direct(mapped) cis space */
++
++/* MAPPED common CIS address */
++#define SBSDIO_CIS_BASE_COMMON 0x1000
++/* maximum bytes in one CIS */
++#define SBSDIO_CIS_SIZE_LIMIT 0x200
++/* cis offset addr is < 17 bits */
++#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
++
++/* manfid tuple length, include tuple, link bytes */
++#define SBSDIO_CIS_MANFID_TUPLE_LEN 6
++
++#define CORE_BUS_REG(base, field) \
++ (base + offsetof(struct sdpcmd_regs, field))
++
++/* SDIO function 1 register CHIPCLKCSR */
++/* Force ALP request to backplane */
++#define SBSDIO_FORCE_ALP 0x01
++/* Force HT request to backplane */
++#define SBSDIO_FORCE_HT 0x02
++/* Force ILP request to backplane */
++#define SBSDIO_FORCE_ILP 0x04
++/* Make ALP ready (power up xtal) */
++#define SBSDIO_ALP_AVAIL_REQ 0x08
++/* Make HT ready (power up PLL) */
++#define SBSDIO_HT_AVAIL_REQ 0x10
++/* Squelch clock requests from HW */
++#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
++/* Status: ALP is ready */
++#define SBSDIO_ALP_AVAIL 0x40
++/* Status: HT is ready */
++#define SBSDIO_HT_AVAIL 0x80
++#define SBSDIO_CSR_MASK 0x1F
++#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
++#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
++#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
++#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
++#define SBSDIO_CLKAV(regval, alponly) \
++ (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
++
++/* intstatus */
++#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
++#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
++#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
++#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
++#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
++#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
++#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
++#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
++#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
++#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
++#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
++#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
++#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
++#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
++#define I_PC (1 << 10) /* descriptor error */
++#define I_PD (1 << 11) /* data error */
++#define I_DE (1 << 12) /* Descriptor protocol Error */
++#define I_RU (1 << 13) /* Receive descriptor Underflow */
++#define I_RO (1 << 14) /* Receive fifo Overflow */
++#define I_XU (1 << 15) /* Transmit fifo Underflow */
++#define I_RI (1 << 16) /* Receive Interrupt */
++#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
++#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
++#define I_XI (1 << 24) /* Transmit Interrupt */
++#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
++#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
++#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
++#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
++#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
++#define I_SRESET (1 << 30) /* CCCR RES interrupt */
++#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
++#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
++#define I_DMA (I_RI | I_XI | I_ERRORS)
++
++/* corecontrol */
++#define CC_CISRDY (1 << 0) /* CIS Ready */
++#define CC_BPRESEN (1 << 1) /* CCCR RES signal */
++#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
++#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
++#define CC_XMTDATAAVAIL_MODE (1 << 4)
++#define CC_XMTDATAAVAIL_CTRL (1 << 5)
++
++/* SDA_FRAMECTRL */
++#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
++#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
++#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
++#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
++
++/*
++ * Software allocation of To SB Mailbox resources
++ */
++
++/* tosbmailbox bits corresponding to intstatus bits */
++#define SMB_NAK (1 << 0) /* Frame NAK */
++#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
++#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
++#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
++
++/* tosbmailboxdata */
++#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
++
++/*
++ * Software allocation of To Host Mailbox resources
++ */
++
++/* intstatus bits */
++#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
++#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
++#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
++#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
++
++/* tohostmailboxdata */
++#define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
++#define HMB_DATA_DEVREADY 2 /* talk to host after enable */
++#define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
++#define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
++
++#define HMB_DATA_FCDATA_MASK 0xff000000
++#define HMB_DATA_FCDATA_SHIFT 24
++
++#define HMB_DATA_VERSION_MASK 0x00ff0000
++#define HMB_DATA_VERSION_SHIFT 16
++
++/*
++ * Software-defined protocol header
++ */
++
++/* Current protocol version */
++#define SDPCM_PROT_VERSION 4
++
++/*
++ * Shared structure between dongle and the host.
++ * The structure contains pointers to trap or assert information.
++ */
++#define SDPCM_SHARED_VERSION 0x0003
++#define SDPCM_SHARED_VERSION_MASK 0x00FF
++#define SDPCM_SHARED_ASSERT_BUILT 0x0100
++#define SDPCM_SHARED_ASSERT 0x0200
++#define SDPCM_SHARED_TRAP 0x0400
++
++/* Space for header read, limit for data packets */
++#define MAX_HDR_READ (1 << 6)
++#define MAX_RX_DATASZ 2048
++
++/* Bump up limit on waiting for HT to account for first startup;
++ * if the image is doing a CRC calculation before programming the PMU
++ * for HT availability, it could take a couple hundred ms more, so
++ * max out at a 1 second (1000000us).
++ */
++#undef PMU_MAX_TRANSITION_DLY
++#define PMU_MAX_TRANSITION_DLY 1000000
++
++/* Value for ChipClockCSR during initial setup */
++#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
++ SBSDIO_ALP_AVAIL_REQ)
++
++/* Flags for SDH calls */
++#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
++
++#define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
++ * when idle
++ */
++#define BRCMF_IDLE_INTERVAL 1
++
++#define KSO_WAIT_US 50
++#define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
++
++/*
++ * Conversion of 802.1D priority to precedence level
++ */
++static uint prio2prec(u32 prio)
++{
++ return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
++ (prio^2) : prio;
++}
++
++#ifdef DEBUG
++/* Device console log buffer state */
++struct brcmf_console {
++ uint count; /* Poll interval msec counter */
++ uint log_addr; /* Log struct address (fixed) */
++ struct rte_log_le log_le; /* Log struct (host copy) */
++ uint bufsize; /* Size of log buffer */
++ u8 *buf; /* Log buffer (host copy) */
++ uint last; /* Last buffer read index */
++};
++
++struct brcmf_trap_info {
++ __le32 type;
++ __le32 epc;
++ __le32 cpsr;
++ __le32 spsr;
++ __le32 r0; /* a1 */
++ __le32 r1; /* a2 */
++ __le32 r2; /* a3 */
++ __le32 r3; /* a4 */
++ __le32 r4; /* v1 */
++ __le32 r5; /* v2 */
++ __le32 r6; /* v3 */
++ __le32 r7; /* v4 */
++ __le32 r8; /* v5 */
++ __le32 r9; /* sb/v6 */
++ __le32 r10; /* sl/v7 */
++ __le32 r11; /* fp/v8 */
++ __le32 r12; /* ip */
++ __le32 r13; /* sp */
++ __le32 r14; /* lr */
++ __le32 pc; /* r15 */
++};
++#endif /* DEBUG */
++
++struct sdpcm_shared {
++ u32 flags;
++ u32 trap_addr;
++ u32 assert_exp_addr;
++ u32 assert_file_addr;
++ u32 assert_line;
++ u32 console_addr; /* Address of struct rte_console */
++ u32 msgtrace_addr;
++ u8 tag[32];
++ u32 brpt_addr;
++};
++
++struct sdpcm_shared_le {
++ __le32 flags;
++ __le32 trap_addr;
++ __le32 assert_exp_addr;
++ __le32 assert_file_addr;
++ __le32 assert_line;
++ __le32 console_addr; /* Address of struct rte_console */
++ __le32 msgtrace_addr;
++ u8 tag[32];
++ __le32 brpt_addr;
++};
++
++/* dongle SDIO bus specific header info */
++struct brcmf_sdio_hdrinfo {
++ u8 seq_num;
++ u8 channel;
++ u16 len;
++ u16 len_left;
++ u16 len_nxtfrm;
++ u8 dat_offset;
++ bool lastfrm;
++ u16 tail_pad;
++};
++
++/*
++ * hold counter variables
++ */
++struct brcmf_sdio_count {
++ uint intrcount; /* Count of device interrupt callbacks */
++ uint lastintrs; /* Count as of last watchdog timer */
++ uint pollcnt; /* Count of active polls */
++ uint regfails; /* Count of R_REG failures */
++ uint tx_sderrs; /* Count of tx attempts with sd errors */
++ uint fcqueued; /* Tx packets that got queued */
++ uint rxrtx; /* Count of rtx requests (NAK to dongle) */
++ uint rx_toolong; /* Receive frames too long to receive */
++ uint rxc_errors; /* SDIO errors when reading control frames */
++ uint rx_hdrfail; /* SDIO errors on header reads */
++ uint rx_badhdr; /* Bad received headers (roosync?) */
++ uint rx_badseq; /* Mismatched rx sequence number */
++ uint fc_rcvd; /* Number of flow-control events received */
++ uint fc_xoff; /* Number which turned on flow-control */
++ uint fc_xon; /* Number which turned off flow-control */
++ uint rxglomfail; /* Failed deglom attempts */
++ uint rxglomframes; /* Number of glom frames (superframes) */
++ uint rxglompkts; /* Number of packets from glom frames */
++ uint f2rxhdrs; /* Number of header reads */
++ uint f2rxdata; /* Number of frame data reads */
++ uint f2txdata; /* Number of f2 frame writes */
++ uint f1regdata; /* Number of f1 register accesses */
++ uint tickcnt; /* Number of watchdog been schedule */
++ ulong tx_ctlerrs; /* Err of sending ctrl frames */
++ ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
++ ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
++ ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
++ ulong rx_readahead_cnt; /* packets where header read-ahead was used */
++};
++
++/* misc chip info needed by some of the routines */
++/* Private data for SDIO bus interaction */
++struct brcmf_sdio {
++ struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
++ struct brcmf_chip *ci; /* Chip info struct */
++
++ u32 hostintmask; /* Copy of Host Interrupt Mask */
++ atomic_t intstatus; /* Intstatus bits (events) pending */
++ atomic_t fcstate; /* State of dongle flow-control */
++
++ uint blocksize; /* Block size of SDIO transfers */
++ uint roundup; /* Max roundup limit */
++
++ struct pktq txq; /* Queue length used for flow-control */
++ u8 flowcontrol; /* per prio flow control bitmask */
++ u8 tx_seq; /* Transmit sequence number (next) */
++ u8 tx_max; /* Maximum transmit sequence allowed */
++
++ u8 *hdrbuf; /* buffer for handling rx frame */
++ u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
++ u8 rx_seq; /* Receive sequence number (expected) */
++ struct brcmf_sdio_hdrinfo cur_read;
++ /* info of current read frame */
++ bool rxskip; /* Skip receive (awaiting NAK ACK) */
++ bool rxpending; /* Data frame pending in dongle */
++
++ uint rxbound; /* Rx frames to read before resched */
++ uint txbound; /* Tx frames to send before resched */
++ uint txminmax;
++
++ struct sk_buff *glomd; /* Packet containing glomming descriptor */
++ struct sk_buff_head glom; /* Packet list for glommed superframe */
++ uint glomerr; /* Glom packet read errors */
++
++ u8 *rxbuf; /* Buffer for receiving control packets */
++ uint rxblen; /* Allocated length of rxbuf */
++ u8 *rxctl; /* Aligned pointer into rxbuf */
++ u8 *rxctl_orig; /* pointer for freeing rxctl */
++ uint rxlen; /* Length of valid data in buffer */
++ spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
++
++ u8 sdpcm_ver; /* Bus protocol reported by dongle */
++
++ bool intr; /* Use interrupts */
++ bool poll; /* Use polling */
++ atomic_t ipend; /* Device interrupt is pending */
++ uint spurious; /* Count of spurious interrupts */
++ uint pollrate; /* Ticks between device polls */
++ uint polltick; /* Tick counter */
++
++#ifdef DEBUG
++ uint console_interval;
++ struct brcmf_console console; /* Console output polling support */
++ uint console_addr; /* Console address from shared struct */
++#endif /* DEBUG */
++
++ uint clkstate; /* State of sd and backplane clock(s) */
++ s32 idletime; /* Control for activity timeout */
++ s32 idlecount; /* Activity timeout counter */
++ s32 idleclock; /* How to set bus driver when idle */
++ bool rxflow_mode; /* Rx flow control mode */
++ bool rxflow; /* Is rx flow control on */
++ bool alp_only; /* Don't use HT clock (ALP only) */
++
++ u8 *ctrl_frame_buf;
++ u16 ctrl_frame_len;
++ bool ctrl_frame_stat;
++ int ctrl_frame_err;
++
++ spinlock_t txq_lock; /* protect bus->txq */
++ wait_queue_head_t ctrl_wait;
++ wait_queue_head_t dcmd_resp_wait;
++
++ struct timer_list timer;
++ struct completion watchdog_wait;
++ struct task_struct *watchdog_tsk;
++ bool wd_timer_valid;
++ uint save_ms;
++
++ struct workqueue_struct *brcmf_wq;
++ struct work_struct datawork;
++ bool dpc_triggered;
++ bool dpc_running;
++
++ bool txoff; /* Transmit flow-controlled */
++ struct brcmf_sdio_count sdcnt;
++ bool sr_enabled; /* SaveRestore enabled */
++ bool sleeping;
++
++ u8 tx_hdrlen; /* sdio bus header length for tx packet */
++ bool txglom; /* host tx glomming enable flag */
++ u16 head_align; /* buffer pointer alignment */
++ u16 sgentry_align; /* scatter-gather buffer alignment */
++};
++
++/* clkstate */
++#define CLK_NONE 0
++#define CLK_SDONLY 1
++#define CLK_PENDING 2
++#define CLK_AVAIL 3
++
++#ifdef DEBUG
++static int qcount[NUMPRIO];
++#endif /* DEBUG */
++
++#define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
++
++#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
++
++/* Retry count for register access failures */
++static const uint retry_limit = 2;
++
++/* Limit on rounding up frames */
++static const uint max_roundup = 512;
++
++#define ALIGNMENT 4
++
++enum brcmf_sdio_frmtype {
++ BRCMF_SDIO_FT_NORMAL,
++ BRCMF_SDIO_FT_SUPER,
++ BRCMF_SDIO_FT_SUB,
++};
++
++#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
++
++/* SDIO Pad drive strength to select value mappings */
++struct sdiod_drive_str {
++ u8 strength; /* Pad Drive Strength in mA */
++ u8 sel; /* Chip-specific select value */
++};
++
++/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
++static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
++ {32, 0x6},
++ {26, 0x7},
++ {22, 0x4},
++ {16, 0x5},
++ {12, 0x2},
++ {8, 0x3},
++ {4, 0x0},
++ {0, 0x1}
++};
++
++/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
++static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
++ {6, 0x7},
++ {5, 0x6},
++ {4, 0x5},
++ {3, 0x4},
++ {2, 0x2},
++ {1, 0x1},
++ {0, 0x0}
++};
++
++/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
++static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
++ {3, 0x3},
++ {2, 0x2},
++ {1, 0x1},
++ {0, 0x0} };
++
++/* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
++static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
++ {16, 0x7},
++ {12, 0x5},
++ {8, 0x3},
++ {4, 0x1}
++};
++
++#define BCM43143_FIRMWARE_NAME "brcm/brcmfmac43143-sdio.bin"
++#define BCM43143_NVRAM_NAME "brcm/brcmfmac43143-sdio.txt"
++#define BCM43241B0_FIRMWARE_NAME "brcm/brcmfmac43241b0-sdio.bin"
++#define BCM43241B0_NVRAM_NAME "brcm/brcmfmac43241b0-sdio.txt"
++#define BCM43241B4_FIRMWARE_NAME "brcm/brcmfmac43241b4-sdio.bin"
++#define BCM43241B4_NVRAM_NAME "brcm/brcmfmac43241b4-sdio.txt"
++#define BCM4329_FIRMWARE_NAME "brcm/brcmfmac4329-sdio.bin"
++#define BCM4329_NVRAM_NAME "brcm/brcmfmac4329-sdio.txt"
++#define BCM4330_FIRMWARE_NAME "brcm/brcmfmac4330-sdio.bin"
++#define BCM4330_NVRAM_NAME "brcm/brcmfmac4330-sdio.txt"
++#define BCM4334_FIRMWARE_NAME "brcm/brcmfmac4334-sdio.bin"
++#define BCM4334_NVRAM_NAME "brcm/brcmfmac4334-sdio.txt"
++#define BCM43340_FIRMWARE_NAME "brcm/brcmfmac43340-sdio.bin"
++#define BCM43340_NVRAM_NAME "brcm/brcmfmac43340-sdio.txt"
++#define BCM4335_FIRMWARE_NAME "brcm/brcmfmac4335-sdio.bin"
++#define BCM4335_NVRAM_NAME "brcm/brcmfmac4335-sdio.txt"
++#define BCM43362_FIRMWARE_NAME "brcm/brcmfmac43362-sdio.bin"
++#define BCM43362_NVRAM_NAME "brcm/brcmfmac43362-sdio.txt"
++#define BCM4339_FIRMWARE_NAME "brcm/brcmfmac4339-sdio.bin"
++#define BCM4339_NVRAM_NAME "brcm/brcmfmac4339-sdio.txt"
++#define BCM43430_FIRMWARE_NAME "brcm/brcmfmac43430-sdio.bin"
++#define BCM43430_NVRAM_NAME "brcm/brcmfmac43430-sdio.txt"
++#define BCM43455_FIRMWARE_NAME "brcm/brcmfmac43455-sdio.bin"
++#define BCM43455_NVRAM_NAME "brcm/brcmfmac43455-sdio.txt"
++#define BCM4354_FIRMWARE_NAME "brcm/brcmfmac4354-sdio.bin"
++#define BCM4354_NVRAM_NAME "brcm/brcmfmac4354-sdio.txt"
++
++MODULE_FIRMWARE(BCM43143_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43143_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43241B0_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43241B0_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43241B4_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43241B4_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4329_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4329_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4330_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4330_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4334_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4334_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43340_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43340_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4335_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4335_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43362_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43362_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4339_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4339_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43430_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43430_NVRAM_NAME);
++MODULE_FIRMWARE(BCM43455_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM43455_NVRAM_NAME);
++MODULE_FIRMWARE(BCM4354_FIRMWARE_NAME);
++MODULE_FIRMWARE(BCM4354_NVRAM_NAME);
++
++struct brcmf_firmware_names {
++ u32 chipid;
++ u32 revmsk;
++ const char *bin;
++ const char *nv;
++};
++
++enum brcmf_firmware_type {
++ BRCMF_FIRMWARE_BIN,
++ BRCMF_FIRMWARE_NVRAM
++};
++
++#define BRCMF_FIRMWARE_NVRAM(name) \
++ name ## _FIRMWARE_NAME, name ## _NVRAM_NAME
++
++static const struct brcmf_firmware_names brcmf_fwname_data[] = {
++ { BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43143) },
++ { BRCM_CC_43241_CHIP_ID, 0x0000001F, BRCMF_FIRMWARE_NVRAM(BCM43241B0) },
++ { BRCM_CC_43241_CHIP_ID, 0xFFFFFFE0, BRCMF_FIRMWARE_NVRAM(BCM43241B4) },
++ { BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4329) },
++ { BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4330) },
++ { BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4334) },
++ { BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43340) },
++ { BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4335) },
++ { BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, BRCMF_FIRMWARE_NVRAM(BCM43362) },
++ { BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4339) },
++ { BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM43430) },
++ { BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, BRCMF_FIRMWARE_NVRAM(BCM43455) },
++ { BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, BRCMF_FIRMWARE_NVRAM(BCM4354) }
++};
++
++static int brcmf_sdio_get_fwnames(struct brcmf_chip *ci,
++ struct brcmf_sdio_dev *sdiodev)
++{
++ int i;
++ char end;
++
++ for (i = 0; i < ARRAY_SIZE(brcmf_fwname_data); i++) {
++ if (brcmf_fwname_data[i].chipid == ci->chip &&
++ brcmf_fwname_data[i].revmsk & BIT(ci->chiprev))
++ break;
++ }
++
++ if (i == ARRAY_SIZE(brcmf_fwname_data)) {
++ brcmf_err("Unknown chipid %d [%d]\n", ci->chip, ci->chiprev);
++ return -ENODEV;
++ }
++
++ /* check if firmware path is provided by module parameter */
++ if (brcmf_firmware_path[0] != '\0') {
++ strlcpy(sdiodev->fw_name, brcmf_firmware_path,
++ sizeof(sdiodev->fw_name));
++ strlcpy(sdiodev->nvram_name, brcmf_firmware_path,
++ sizeof(sdiodev->nvram_name));
++
++ end = brcmf_firmware_path[strlen(brcmf_firmware_path) - 1];
++ if (end != '/') {
++ strlcat(sdiodev->fw_name, "/",
++ sizeof(sdiodev->fw_name));
++ strlcat(sdiodev->nvram_name, "/",
++ sizeof(sdiodev->nvram_name));
++ }
++ }
++ strlcat(sdiodev->fw_name, brcmf_fwname_data[i].bin,
++ sizeof(sdiodev->fw_name));
++ strlcat(sdiodev->nvram_name, brcmf_fwname_data[i].nv,
++ sizeof(sdiodev->nvram_name));
++
++ return 0;
++}
++
++static void pkt_align(struct sk_buff *p, int len, int align)
++{
++ uint datalign;
++ datalign = (unsigned long)(p->data);
++ datalign = roundup(datalign, (align)) - datalign;
++ if (datalign)
++ skb_pull(p, datalign);
++ __skb_trim(p, len);
++}
++
++/* To check if there's window offered */
++static bool data_ok(struct brcmf_sdio *bus)
++{
++ return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
++ ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
++}
++
++/*
++ * Reads a register in the SDIO hardware block. This block occupies a series of
++ * adresses on the 32 bit backplane bus.
++ */
++static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
++{
++ struct brcmf_core *core;
++ int ret;
++
++ core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
++ *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
++
++ return ret;
++}
++
++static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
++{
++ struct brcmf_core *core;
++ int ret;
++
++ core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
++ brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
++
++ return ret;
++}
++
++static int
++brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
++{
++ u8 wr_val = 0, rd_val, cmp_val, bmask;
++ int err = 0;
++ int try_cnt = 0;
++
++ brcmf_dbg(TRACE, "Enter: on=%d\n", on);
++
++ wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
++ /* 1st KSO write goes to AOS wake up core if device is asleep */
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ wr_val, &err);
++
++ if (on) {
++ /* device WAKEUP through KSO:
++ * write bit 0 & read back until
++ * both bits 0 (kso bit) & 1 (dev on status) are set
++ */
++ cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
++ SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
++ bmask = cmp_val;
++ usleep_range(2000, 3000);
++ } else {
++ /* Put device to sleep, turn off KSO */
++ cmp_val = 0;
++ /* only check for bit0, bit1(dev on status) may not
++ * get cleared right away
++ */
++ bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
++ }
++
++ do {
++ /* reliable KSO bit set/clr:
++ * the sdiod sleep write access is synced to PMU 32khz clk
++ * just one write attempt may fail,
++ * read it back until it matches written value
++ */
++ rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ &err);
++ if (((rd_val & bmask) == cmp_val) && !err)
++ break;
++
++ udelay(KSO_WAIT_US);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ wr_val, &err);
++ } while (try_cnt++ < MAX_KSO_ATTEMPTS);
++
++ if (try_cnt > 2)
++ brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
++ rd_val, err);
++
++ if (try_cnt > MAX_KSO_ATTEMPTS)
++ brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
++
++ return err;
++}
++
++#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
++
++/* Turn backplane clock on or off */
++static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
++{
++ int err;
++ u8 clkctl, clkreq, devctl;
++ unsigned long timeout;
++
++ brcmf_dbg(SDIO, "Enter\n");
++
++ clkctl = 0;
++
++ if (bus->sr_enabled) {
++ bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
++ return 0;
++ }
++
++ if (on) {
++ /* Request HT Avail */
++ clkreq =
++ bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
++
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ clkreq, &err);
++ if (err) {
++ brcmf_err("HT Avail request error: %d\n", err);
++ return -EBADE;
++ }
++
++ /* Check current status */
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, &err);
++ if (err) {
++ brcmf_err("HT Avail read error: %d\n", err);
++ return -EBADE;
++ }
++
++ /* Go to pending and await interrupt if appropriate */
++ if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
++ /* Allow only clock-available interrupt */
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
++ if (err) {
++ brcmf_err("Devctl error setting CA: %d\n",
++ err);
++ return -EBADE;
++ }
++
++ devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
++ brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
++ bus->clkstate = CLK_PENDING;
++
++ return 0;
++ } else if (bus->clkstate == CLK_PENDING) {
++ /* Cancel CA-only interrupt filter */
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
++ devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
++ }
++
++ /* Otherwise, wait here (polling) for HT Avail */
++ timeout = jiffies +
++ msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
++ while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR,
++ &err);
++ if (time_after(jiffies, timeout))
++ break;
++ else
++ usleep_range(5000, 10000);
++ }
++ if (err) {
++ brcmf_err("HT Avail request error: %d\n", err);
++ return -EBADE;
++ }
++ if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
++ brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
++ PMU_MAX_TRANSITION_DLY, clkctl);
++ return -EBADE;
++ }
++
++ /* Mark clock available */
++ bus->clkstate = CLK_AVAIL;
++ brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
++
++#if defined(DEBUG)
++ if (!bus->alp_only) {
++ if (SBSDIO_ALPONLY(clkctl))
++ brcmf_err("HT Clock should be on\n");
++ }
++#endif /* defined (DEBUG) */
++
++ } else {
++ clkreq = 0;
++
++ if (bus->clkstate == CLK_PENDING) {
++ /* Cancel CA-only interrupt filter */
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
++ devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
++ }
++
++ bus->clkstate = CLK_SDONLY;
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ clkreq, &err);
++ brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
++ if (err) {
++ brcmf_err("Failed access turning clock off: %d\n",
++ err);
++ return -EBADE;
++ }
++ }
++ return 0;
++}
++
++/* Change idle/active SD state */
++static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
++{
++ brcmf_dbg(SDIO, "Enter\n");
++
++ if (on)
++ bus->clkstate = CLK_SDONLY;
++ else
++ bus->clkstate = CLK_NONE;
++
++ return 0;
++}
++
++/* Transition SD and backplane clock readiness */
++static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
++{
++#ifdef DEBUG
++ uint oldstate = bus->clkstate;
++#endif /* DEBUG */
++
++ brcmf_dbg(SDIO, "Enter\n");
++
++ /* Early exit if we're already there */
++ if (bus->clkstate == target)
++ return 0;
++
++ switch (target) {
++ case CLK_AVAIL:
++ /* Make sure SD clock is available */
++ if (bus->clkstate == CLK_NONE)
++ brcmf_sdio_sdclk(bus, true);
++ /* Now request HT Avail on the backplane */
++ brcmf_sdio_htclk(bus, true, pendok);
++ break;
++
++ case CLK_SDONLY:
++ /* Remove HT request, or bring up SD clock */
++ if (bus->clkstate == CLK_NONE)
++ brcmf_sdio_sdclk(bus, true);
++ else if (bus->clkstate == CLK_AVAIL)
++ brcmf_sdio_htclk(bus, false, false);
++ else
++ brcmf_err("request for %d -> %d\n",
++ bus->clkstate, target);
++ break;
++
++ case CLK_NONE:
++ /* Make sure to remove HT request */
++ if (bus->clkstate == CLK_AVAIL)
++ brcmf_sdio_htclk(bus, false, false);
++ /* Now remove the SD clock */
++ brcmf_sdio_sdclk(bus, false);
++ break;
++ }
++#ifdef DEBUG
++ brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
++#endif /* DEBUG */
++
++ return 0;
++}
++
++static int
++brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
++{
++ int err = 0;
++ u8 clkcsr;
++
++ brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
++ (sleep ? "SLEEP" : "WAKE"),
++ (bus->sleeping ? "SLEEP" : "WAKE"));
++
++ /* If SR is enabled control bus state with KSO */
++ if (bus->sr_enabled) {
++ /* Done if we're already in the requested state */
++ if (sleep == bus->sleeping)
++ goto end;
++
++ /* Going to sleep */
++ if (sleep) {
++ clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR,
++ &err);
++ if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
++ brcmf_dbg(SDIO, "no clock, set ALP\n");
++ brcmf_sdiod_regwb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR,
++ SBSDIO_ALP_AVAIL_REQ, &err);
++ }
++ err = brcmf_sdio_kso_control(bus, false);
++ } else {
++ err = brcmf_sdio_kso_control(bus, true);
++ }
++ if (err) {
++ brcmf_err("error while changing bus sleep state %d\n",
++ err);
++ goto done;
++ }
++ }
++
++end:
++ /* control clocks */
++ if (sleep) {
++ if (!bus->sr_enabled)
++ brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
++ } else {
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
++ brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
++ }
++ bus->sleeping = sleep;
++ brcmf_dbg(SDIO, "new state %s\n",
++ (sleep ? "SLEEP" : "WAKE"));
++done:
++ brcmf_dbg(SDIO, "Exit: err=%d\n", err);
++ return err;
++
++}
++
++#ifdef DEBUG
++static inline bool brcmf_sdio_valid_shared_address(u32 addr)
++{
++ return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
++}
++
++static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
++ struct sdpcm_shared *sh)
++{
++ u32 addr = 0;
++ int rv;
++ u32 shaddr = 0;
++ struct sdpcm_shared_le sh_le;
++ __le32 addr_le;
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_bus_sleep(bus, false, false);
++
++ /*
++ * Read last word in socram to determine
++ * address of sdpcm_shared structure
++ */
++ shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
++ if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
++ shaddr -= bus->ci->srsize;
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
++ (u8 *)&addr_le, 4);
++ if (rv < 0)
++ goto fail;
++
++ /*
++ * Check if addr is valid.
++ * NVRAM length at the end of memory should have been overwritten.
++ */
++ addr = le32_to_cpu(addr_le);
++ if (!brcmf_sdio_valid_shared_address(addr)) {
++ brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
++ rv = -EINVAL;
++ goto fail;
++ }
++
++ brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
++
++ /* Read hndrte_shared structure */
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
++ sizeof(struct sdpcm_shared_le));
++ if (rv < 0)
++ goto fail;
++
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ /* Endianness */
++ sh->flags = le32_to_cpu(sh_le.flags);
++ sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
++ sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
++ sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
++ sh->assert_line = le32_to_cpu(sh_le.assert_line);
++ sh->console_addr = le32_to_cpu(sh_le.console_addr);
++ sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
++
++ if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
++ brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
++ SDPCM_SHARED_VERSION,
++ sh->flags & SDPCM_SHARED_VERSION_MASK);
++ return -EPROTO;
++ }
++ return 0;
++
++fail:
++ brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
++ rv, addr);
++ sdio_release_host(bus->sdiodev->func[1]);
++ return rv;
++}
++
++static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
++{
++ struct sdpcm_shared sh;
++
++ if (brcmf_sdio_readshared(bus, &sh) == 0)
++ bus->console_addr = sh.console_addr;
++}
++#else
++static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
++{
++}
++#endif /* DEBUG */
++
++static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
++{
++ u32 intstatus = 0;
++ u32 hmb_data;
++ u8 fcbits;
++ int ret;
++
++ brcmf_dbg(SDIO, "Enter\n");
++
++ /* Read mailbox data and ack that we did so */
++ ret = r_sdreg32(bus, &hmb_data,
++ offsetof(struct sdpcmd_regs, tohostmailboxdata));
++
++ if (ret == 0)
++ w_sdreg32(bus, SMB_INT_ACK,
++ offsetof(struct sdpcmd_regs, tosbmailbox));
++ bus->sdcnt.f1regdata += 2;
++
++ /* Dongle recomposed rx frames, accept them again */
++ if (hmb_data & HMB_DATA_NAKHANDLED) {
++ brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
++ bus->rx_seq);
++ if (!bus->rxskip)
++ brcmf_err("unexpected NAKHANDLED!\n");
++
++ bus->rxskip = false;
++ intstatus |= I_HMB_FRAME_IND;
++ }
++
++ /*
++ * DEVREADY does not occur with gSPI.
++ */
++ if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
++ bus->sdpcm_ver =
++ (hmb_data & HMB_DATA_VERSION_MASK) >>
++ HMB_DATA_VERSION_SHIFT;
++ if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
++ brcmf_err("Version mismatch, dongle reports %d, "
++ "expecting %d\n",
++ bus->sdpcm_ver, SDPCM_PROT_VERSION);
++ else
++ brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
++ bus->sdpcm_ver);
++
++ /*
++ * Retrieve console state address now that firmware should have
++ * updated it.
++ */
++ brcmf_sdio_get_console_addr(bus);
++ }
++
++ /*
++ * Flow Control has been moved into the RX headers and this out of band
++ * method isn't used any more.
++ * remaining backward compatible with older dongles.
++ */
++ if (hmb_data & HMB_DATA_FC) {
++ fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
++ HMB_DATA_FCDATA_SHIFT;
++
++ if (fcbits & ~bus->flowcontrol)
++ bus->sdcnt.fc_xoff++;
++
++ if (bus->flowcontrol & ~fcbits)
++ bus->sdcnt.fc_xon++;
++
++ bus->sdcnt.fc_rcvd++;
++ bus->flowcontrol = fcbits;
++ }
++
++ /* Shouldn't be any others */
++ if (hmb_data & ~(HMB_DATA_DEVREADY |
++ HMB_DATA_NAKHANDLED |
++ HMB_DATA_FC |
++ HMB_DATA_FWREADY |
++ HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
++ brcmf_err("Unknown mailbox data content: 0x%02x\n",
++ hmb_data);
++
++ return intstatus;
++}
++
++static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
++{
++ uint retries = 0;
++ u16 lastrbc;
++ u8 hi, lo;
++ int err;
++
++ brcmf_err("%sterminate frame%s\n",
++ abort ? "abort command, " : "",
++ rtx ? ", send NAK" : "");
++
++ if (abort)
++ brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
++
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
++ SFC_RF_TERM, &err);
++ bus->sdcnt.f1regdata++;
++
++ /* Wait until the packet has been flushed (device/FIFO stable) */
++ for (lastrbc = retries = 0xffff; retries > 0; retries--) {
++ hi = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_RFRAMEBCHI, &err);
++ lo = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_RFRAMEBCLO, &err);
++ bus->sdcnt.f1regdata += 2;
++
++ if ((hi == 0) && (lo == 0))
++ break;
++
++ if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
++ brcmf_err("count growing: last 0x%04x now 0x%04x\n",
++ lastrbc, (hi << 8) + lo);
++ }
++ lastrbc = (hi << 8) + lo;
++ }
++
++ if (!retries)
++ brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
++ else
++ brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
++
++ if (rtx) {
++ bus->sdcnt.rxrtx++;
++ err = w_sdreg32(bus, SMB_NAK,
++ offsetof(struct sdpcmd_regs, tosbmailbox));
++
++ bus->sdcnt.f1regdata++;
++ if (err == 0)
++ bus->rxskip = true;
++ }
++
++ /* Clear partial in any case */
++ bus->cur_read.len = 0;
++}
++
++static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
++{
++ struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
++ u8 i, hi, lo;
++
++ /* On failure, abort the command and terminate the frame */
++ brcmf_err("sdio error, abort command and terminate frame\n");
++ bus->sdcnt.tx_sderrs++;
++
++ brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
++ bus->sdcnt.f1regdata++;
++
++ for (i = 0; i < 3; i++) {
++ hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
++ lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
++ bus->sdcnt.f1regdata += 2;
++ if ((hi == 0) && (lo == 0))
++ break;
++ }
++}
++
++/* return total length of buffer chain */
++static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
++{
++ struct sk_buff *p;
++ uint total;
++
++ total = 0;
++ skb_queue_walk(&bus->glom, p)
++ total += p->len;
++ return total;
++}
++
++static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
++{
++ struct sk_buff *cur, *next;
++
++ skb_queue_walk_safe(&bus->glom, cur, next) {
++ skb_unlink(cur, &bus->glom);
++ brcmu_pkt_buf_free_skb(cur);
++ }
++}
++
++/**
++ * brcmfmac sdio bus specific header
++ * This is the lowest layer header wrapped on the packets transmitted between
++ * host and WiFi dongle which contains information needed for SDIO core and
++ * firmware
++ *
++ * It consists of 3 parts: hardware header, hardware extension header and
++ * software header
++ * hardware header (frame tag) - 4 bytes
++ * Byte 0~1: Frame length
++ * Byte 2~3: Checksum, bit-wise inverse of frame length
++ * hardware extension header - 8 bytes
++ * Tx glom mode only, N/A for Rx or normal Tx
++ * Byte 0~1: Packet length excluding hw frame tag
++ * Byte 2: Reserved
++ * Byte 3: Frame flags, bit 0: last frame indication
++ * Byte 4~5: Reserved
++ * Byte 6~7: Tail padding length
++ * software header - 8 bytes
++ * Byte 0: Rx/Tx sequence number
++ * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
++ * Byte 2: Length of next data frame, reserved for Tx
++ * Byte 3: Data offset
++ * Byte 4: Flow control bits, reserved for Tx
++ * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
++ * Byte 6~7: Reserved
++ */
++#define SDPCM_HWHDR_LEN 4
++#define SDPCM_HWEXT_LEN 8
++#define SDPCM_SWHDR_LEN 8
++#define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
++/* software header */
++#define SDPCM_SEQ_MASK 0x000000ff
++#define SDPCM_SEQ_WRAP 256
++#define SDPCM_CHANNEL_MASK 0x00000f00
++#define SDPCM_CHANNEL_SHIFT 8
++#define SDPCM_CONTROL_CHANNEL 0 /* Control */
++#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
++#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
++#define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
++#define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
++#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
++#define SDPCM_NEXTLEN_MASK 0x00ff0000
++#define SDPCM_NEXTLEN_SHIFT 16
++#define SDPCM_DOFFSET_MASK 0xff000000
++#define SDPCM_DOFFSET_SHIFT 24
++#define SDPCM_FCMASK_MASK 0x000000ff
++#define SDPCM_WINDOW_MASK 0x0000ff00
++#define SDPCM_WINDOW_SHIFT 8
++
++static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
++{
++ u32 hdrvalue;
++ hdrvalue = *(u32 *)swheader;
++ return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
++}
++
++static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
++ struct brcmf_sdio_hdrinfo *rd,
++ enum brcmf_sdio_frmtype type)
++{
++ u16 len, checksum;
++ u8 rx_seq, fc, tx_seq_max;
++ u32 swheader;
++
++ trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
++
++ /* hw header */
++ len = get_unaligned_le16(header);
++ checksum = get_unaligned_le16(header + sizeof(u16));
++ /* All zero means no more to read */
++ if (!(len | checksum)) {
++ bus->rxpending = false;
++ return -ENODATA;
++ }
++ if ((u16)(~(len ^ checksum))) {
++ brcmf_err("HW header checksum error\n");
++ bus->sdcnt.rx_badhdr++;
++ brcmf_sdio_rxfail(bus, false, false);
++ return -EIO;
++ }
++ if (len < SDPCM_HDRLEN) {
++ brcmf_err("HW header length error\n");
++ return -EPROTO;
++ }
++ if (type == BRCMF_SDIO_FT_SUPER &&
++ (roundup(len, bus->blocksize) != rd->len)) {
++ brcmf_err("HW superframe header length error\n");
++ return -EPROTO;
++ }
++ if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
++ brcmf_err("HW subframe header length error\n");
++ return -EPROTO;
++ }
++ rd->len = len;
++
++ /* software header */
++ header += SDPCM_HWHDR_LEN;
++ swheader = le32_to_cpu(*(__le32 *)header);
++ if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
++ brcmf_err("Glom descriptor found in superframe head\n");
++ rd->len = 0;
++ return -EINVAL;
++ }
++ rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
++ rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
++ if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
++ type != BRCMF_SDIO_FT_SUPER) {
++ brcmf_err("HW header length too long\n");
++ bus->sdcnt.rx_toolong++;
++ brcmf_sdio_rxfail(bus, false, false);
++ rd->len = 0;
++ return -EPROTO;
++ }
++ if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
++ brcmf_err("Wrong channel for superframe\n");
++ rd->len = 0;
++ return -EINVAL;
++ }
++ if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
++ rd->channel != SDPCM_EVENT_CHANNEL) {
++ brcmf_err("Wrong channel for subframe\n");
++ rd->len = 0;
++ return -EINVAL;
++ }
++ rd->dat_offset = brcmf_sdio_getdatoffset(header);
++ if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
++ brcmf_err("seq %d: bad data offset\n", rx_seq);
++ bus->sdcnt.rx_badhdr++;
++ brcmf_sdio_rxfail(bus, false, false);
++ rd->len = 0;
++ return -ENXIO;
++ }
++ if (rd->seq_num != rx_seq) {
++ brcmf_err("seq %d: sequence number error, expect %d\n",
++ rx_seq, rd->seq_num);
++ bus->sdcnt.rx_badseq++;
++ rd->seq_num = rx_seq;
++ }
++ /* no need to check the reset for subframe */
++ if (type == BRCMF_SDIO_FT_SUB)
++ return 0;
++ rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
++ if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
++ /* only warm for NON glom packet */
++ if (rd->channel != SDPCM_GLOM_CHANNEL)
++ brcmf_err("seq %d: next length error\n", rx_seq);
++ rd->len_nxtfrm = 0;
++ }
++ swheader = le32_to_cpu(*(__le32 *)(header + 4));
++ fc = swheader & SDPCM_FCMASK_MASK;
++ if (bus->flowcontrol != fc) {
++ if (~bus->flowcontrol & fc)
++ bus->sdcnt.fc_xoff++;
++ if (bus->flowcontrol & ~fc)
++ bus->sdcnt.fc_xon++;
++ bus->sdcnt.fc_rcvd++;
++ bus->flowcontrol = fc;
++ }
++ tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
++ if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
++ brcmf_err("seq %d: max tx seq number error\n", rx_seq);
++ tx_seq_max = bus->tx_seq + 2;
++ }
++ bus->tx_max = tx_seq_max;
++
++ return 0;
++}
++
++static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
++{
++ *(__le16 *)header = cpu_to_le16(frm_length);
++ *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
++}
++
++static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
++ struct brcmf_sdio_hdrinfo *hd_info)
++{
++ u32 hdrval;
++ u8 hdr_offset;
++
++ brcmf_sdio_update_hwhdr(header, hd_info->len);
++ hdr_offset = SDPCM_HWHDR_LEN;
++
++ if (bus->txglom) {
++ hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
++ *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
++ hdrval = (u16)hd_info->tail_pad << 16;
++ *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
++ hdr_offset += SDPCM_HWEXT_LEN;
++ }
++
++ hdrval = hd_info->seq_num;
++ hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
++ SDPCM_CHANNEL_MASK;
++ hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
++ SDPCM_DOFFSET_MASK;
++ *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
++ *(((__le32 *)(header + hdr_offset)) + 1) = 0;
++ trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
++}
++
++static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
++{
++ u16 dlen, totlen;
++ u8 *dptr, num = 0;
++ u16 sublen;
++ struct sk_buff *pfirst, *pnext;
++
++ int errcode;
++ u8 doff, sfdoff;
++
++ struct brcmf_sdio_hdrinfo rd_new;
++
++ /* If packets, issue read(s) and send up packet chain */
++ /* Return sequence numbers consumed? */
++
++ brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
++ bus->glomd, skb_peek(&bus->glom));
++
++ /* If there's a descriptor, generate the packet chain */
++ if (bus->glomd) {
++ pfirst = pnext = NULL;
++ dlen = (u16) (bus->glomd->len);
++ dptr = bus->glomd->data;
++ if (!dlen || (dlen & 1)) {
++ brcmf_err("bad glomd len(%d), ignore descriptor\n",
++ dlen);
++ dlen = 0;
++ }
++
++ for (totlen = num = 0; dlen; num++) {
++ /* Get (and move past) next length */
++ sublen = get_unaligned_le16(dptr);
++ dlen -= sizeof(u16);
++ dptr += sizeof(u16);
++ if ((sublen < SDPCM_HDRLEN) ||
++ ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
++ brcmf_err("descriptor len %d bad: %d\n",
++ num, sublen);
++ pnext = NULL;
++ break;
++ }
++ if (sublen % bus->sgentry_align) {
++ brcmf_err("sublen %d not multiple of %d\n",
++ sublen, bus->sgentry_align);
++ }
++ totlen += sublen;
++
++ /* For last frame, adjust read len so total
++ is a block multiple */
++ if (!dlen) {
++ sublen +=
++ (roundup(totlen, bus->blocksize) - totlen);
++ totlen = roundup(totlen, bus->blocksize);
++ }
++
++ /* Allocate/chain packet for next subframe */
++ pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
++ if (pnext == NULL) {
++ brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
++ num, sublen);
++ break;
++ }
++ skb_queue_tail(&bus->glom, pnext);
++
++ /* Adhere to start alignment requirements */
++ pkt_align(pnext, sublen, bus->sgentry_align);
++ }
++
++ /* If all allocations succeeded, save packet chain
++ in bus structure */
++ if (pnext) {
++ brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
++ totlen, num);
++ if (BRCMF_GLOM_ON() && bus->cur_read.len &&
++ totlen != bus->cur_read.len) {
++ brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
++ bus->cur_read.len, totlen, rxseq);
++ }
++ pfirst = pnext = NULL;
++ } else {
++ brcmf_sdio_free_glom(bus);
++ num = 0;
++ }
++
++ /* Done with descriptor packet */
++ brcmu_pkt_buf_free_skb(bus->glomd);
++ bus->glomd = NULL;
++ bus->cur_read.len = 0;
++ }
++
++ /* Ok -- either we just generated a packet chain,
++ or had one from before */
++ if (!skb_queue_empty(&bus->glom)) {
++ if (BRCMF_GLOM_ON()) {
++ brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
++ skb_queue_walk(&bus->glom, pnext) {
++ brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
++ pnext, (u8 *) (pnext->data),
++ pnext->len, pnext->len);
++ }
++ }
++
++ pfirst = skb_peek(&bus->glom);
++ dlen = (u16) brcmf_sdio_glom_len(bus);
++
++ /* Do an SDIO read for the superframe. Configurable iovar to
++ * read directly into the chained packet, or allocate a large
++ * packet and and copy into the chain.
++ */
++ sdio_claim_host(bus->sdiodev->func[1]);
++ errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
++ &bus->glom, dlen);
++ sdio_release_host(bus->sdiodev->func[1]);
++ bus->sdcnt.f2rxdata++;
++
++ /* On failure, kill the superframe, allow a couple retries */
++ if (errcode < 0) {
++ brcmf_err("glom read of %d bytes failed: %d\n",
++ dlen, errcode);
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (bus->glomerr++ < 3) {
++ brcmf_sdio_rxfail(bus, true, true);
++ } else {
++ bus->glomerr = 0;
++ brcmf_sdio_rxfail(bus, true, false);
++ bus->sdcnt.rxglomfail++;
++ brcmf_sdio_free_glom(bus);
++ }
++ sdio_release_host(bus->sdiodev->func[1]);
++ return 0;
++ }
++
++ brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
++ pfirst->data, min_t(int, pfirst->len, 48),
++ "SUPERFRAME:\n");
++
++ rd_new.seq_num = rxseq;
++ rd_new.len = dlen;
++ sdio_claim_host(bus->sdiodev->func[1]);
++ errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
++ BRCMF_SDIO_FT_SUPER);
++ sdio_release_host(bus->sdiodev->func[1]);
++ bus->cur_read.len = rd_new.len_nxtfrm << 4;
++
++ /* Remove superframe header, remember offset */
++ skb_pull(pfirst, rd_new.dat_offset);
++ sfdoff = rd_new.dat_offset;
++ num = 0;
++
++ /* Validate all the subframe headers */
++ skb_queue_walk(&bus->glom, pnext) {
++ /* leave when invalid subframe is found */
++ if (errcode)
++ break;
++
++ rd_new.len = pnext->len;
++ rd_new.seq_num = rxseq++;
++ sdio_claim_host(bus->sdiodev->func[1]);
++ errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
++ BRCMF_SDIO_FT_SUB);
++ sdio_release_host(bus->sdiodev->func[1]);
++ brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
++ pnext->data, 32, "subframe:\n");
++
++ num++;
++ }
++
++ if (errcode) {
++ /* Terminate frame on error, request
++ a couple retries */
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (bus->glomerr++ < 3) {
++ /* Restore superframe header space */
++ skb_push(pfirst, sfdoff);
++ brcmf_sdio_rxfail(bus, true, true);
++ } else {
++ bus->glomerr = 0;
++ brcmf_sdio_rxfail(bus, true, false);
++ bus->sdcnt.rxglomfail++;
++ brcmf_sdio_free_glom(bus);
++ }
++ sdio_release_host(bus->sdiodev->func[1]);
++ bus->cur_read.len = 0;
++ return 0;
++ }
++
++ /* Basic SD framing looks ok - process each packet (header) */
++
++ skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
++ dptr = (u8 *) (pfirst->data);
++ sublen = get_unaligned_le16(dptr);
++ doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
++
++ brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
++ dptr, pfirst->len,
++ "Rx Subframe Data:\n");
++
++ __skb_trim(pfirst, sublen);
++ skb_pull(pfirst, doff);
++
++ if (pfirst->len == 0) {
++ skb_unlink(pfirst, &bus->glom);
++ brcmu_pkt_buf_free_skb(pfirst);
++ continue;
++ }
++
++ brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
++ pfirst->data,
++ min_t(int, pfirst->len, 32),
++ "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
++ bus->glom.qlen, pfirst, pfirst->data,
++ pfirst->len, pfirst->next,
++ pfirst->prev);
++ skb_unlink(pfirst, &bus->glom);
++ brcmf_rx_frame(bus->sdiodev->dev, pfirst);
++ bus->sdcnt.rxglompkts++;
++ }
++
++ bus->sdcnt.rxglomframes++;
++ }
++ return num;
++}
++
++static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
++ bool *pending)
++{
++ DECLARE_WAITQUEUE(wait, current);
++ int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
++
++ /* Wait until control frame is available */
++ add_wait_queue(&bus->dcmd_resp_wait, &wait);
++ set_current_state(TASK_INTERRUPTIBLE);
++
++ while (!(*condition) && (!signal_pending(current) && timeout))
++ timeout = schedule_timeout(timeout);
++
++ if (signal_pending(current))
++ *pending = true;
++
++ set_current_state(TASK_RUNNING);
++ remove_wait_queue(&bus->dcmd_resp_wait, &wait);
++
++ return timeout;
++}
++
++static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
++{
++ if (waitqueue_active(&bus->dcmd_resp_wait))
++ wake_up_interruptible(&bus->dcmd_resp_wait);
++
++ return 0;
++}
++static void
++brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
++{
++ uint rdlen, pad;
++ u8 *buf = NULL, *rbuf;
++ int sdret;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (bus->rxblen)
++ buf = vzalloc(bus->rxblen);
++ if (!buf)
++ goto done;
++
++ rbuf = bus->rxbuf;
++ pad = ((unsigned long)rbuf % bus->head_align);
++ if (pad)
++ rbuf += (bus->head_align - pad);
++
++ /* Copy the already-read portion over */
++ memcpy(buf, hdr, BRCMF_FIRSTREAD);
++ if (len <= BRCMF_FIRSTREAD)
++ goto gotpkt;
++
++ /* Raise rdlen to next SDIO block to avoid tail command */
++ rdlen = len - BRCMF_FIRSTREAD;
++ if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
++ pad = bus->blocksize - (rdlen % bus->blocksize);
++ if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
++ ((len + pad) < bus->sdiodev->bus_if->maxctl))
++ rdlen += pad;
++ } else if (rdlen % bus->head_align) {
++ rdlen += bus->head_align - (rdlen % bus->head_align);
++ }
++
++ /* Drop if the read is too big or it exceeds our maximum */
++ if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
++ brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
++ rdlen, bus->sdiodev->bus_if->maxctl);
++ brcmf_sdio_rxfail(bus, false, false);
++ goto done;
++ }
++
++ if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
++ brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
++ len, len - doff, bus->sdiodev->bus_if->maxctl);
++ bus->sdcnt.rx_toolong++;
++ brcmf_sdio_rxfail(bus, false, false);
++ goto done;
++ }
++
++ /* Read remain of frame body */
++ sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
++ bus->sdcnt.f2rxdata++;
++
++ /* Control frame failures need retransmission */
++ if (sdret < 0) {
++ brcmf_err("read %d control bytes failed: %d\n",
++ rdlen, sdret);
++ bus->sdcnt.rxc_errors++;
++ brcmf_sdio_rxfail(bus, true, true);
++ goto done;
++ } else
++ memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
++
++gotpkt:
++
++ brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
++ buf, len, "RxCtrl:\n");
++
++ /* Point to valid data and indicate its length */
++ spin_lock_bh(&bus->rxctl_lock);
++ if (bus->rxctl) {
++ brcmf_err("last control frame is being processed.\n");
++ spin_unlock_bh(&bus->rxctl_lock);
++ vfree(buf);
++ goto done;
++ }
++ bus->rxctl = buf + doff;
++ bus->rxctl_orig = buf;
++ bus->rxlen = len - doff;
++ spin_unlock_bh(&bus->rxctl_lock);
++
++done:
++ /* Awake any waiters */
++ brcmf_sdio_dcmd_resp_wake(bus);
++}
++
++/* Pad read to blocksize for efficiency */
++static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
++{
++ if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
++ *pad = bus->blocksize - (*rdlen % bus->blocksize);
++ if (*pad <= bus->roundup && *pad < bus->blocksize &&
++ *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
++ *rdlen += *pad;
++ } else if (*rdlen % bus->head_align) {
++ *rdlen += bus->head_align - (*rdlen % bus->head_align);
++ }
++}
++
++static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
++{
++ struct sk_buff *pkt; /* Packet for event or data frames */
++ u16 pad; /* Number of pad bytes to read */
++ uint rxleft = 0; /* Remaining number of frames allowed */
++ int ret; /* Return code from calls */
++ uint rxcount = 0; /* Total frames read */
++ struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
++ u8 head_read = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* Not finished unless we encounter no more frames indication */
++ bus->rxpending = true;
++
++ for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
++ !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
++ rd->seq_num++, rxleft--) {
++
++ /* Handle glomming separately */
++ if (bus->glomd || !skb_queue_empty(&bus->glom)) {
++ u8 cnt;
++ brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
++ bus->glomd, skb_peek(&bus->glom));
++ cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
++ brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
++ rd->seq_num += cnt - 1;
++ rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
++ continue;
++ }
++
++ rd->len_left = rd->len;
++ /* read header first for unknow frame length */
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (!rd->len) {
++ ret = brcmf_sdiod_recv_buf(bus->sdiodev,
++ bus->rxhdr, BRCMF_FIRSTREAD);
++ bus->sdcnt.f2rxhdrs++;
++ if (ret < 0) {
++ brcmf_err("RXHEADER FAILED: %d\n",
++ ret);
++ bus->sdcnt.rx_hdrfail++;
++ brcmf_sdio_rxfail(bus, true, true);
++ sdio_release_host(bus->sdiodev->func[1]);
++ continue;
++ }
++
++ brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
++ bus->rxhdr, SDPCM_HDRLEN,
++ "RxHdr:\n");
++
++ if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
++ BRCMF_SDIO_FT_NORMAL)) {
++ sdio_release_host(bus->sdiodev->func[1]);
++ if (!bus->rxpending)
++ break;
++ else
++ continue;
++ }
++
++ if (rd->channel == SDPCM_CONTROL_CHANNEL) {
++ brcmf_sdio_read_control(bus, bus->rxhdr,
++ rd->len,
++ rd->dat_offset);
++ /* prepare the descriptor for the next read */
++ rd->len = rd->len_nxtfrm << 4;
++ rd->len_nxtfrm = 0;
++ /* treat all packet as event if we don't know */
++ rd->channel = SDPCM_EVENT_CHANNEL;
++ sdio_release_host(bus->sdiodev->func[1]);
++ continue;
++ }
++ rd->len_left = rd->len > BRCMF_FIRSTREAD ?
++ rd->len - BRCMF_FIRSTREAD : 0;
++ head_read = BRCMF_FIRSTREAD;
++ }
++
++ brcmf_sdio_pad(bus, &pad, &rd->len_left);
++
++ pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
++ bus->head_align);
++ if (!pkt) {
++ /* Give up on data, request rtx of events */
++ brcmf_err("brcmu_pkt_buf_get_skb failed\n");
++ brcmf_sdio_rxfail(bus, false,
++ RETRYCHAN(rd->channel));
++ sdio_release_host(bus->sdiodev->func[1]);
++ continue;
++ }
++ skb_pull(pkt, head_read);
++ pkt_align(pkt, rd->len_left, bus->head_align);
++
++ ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
++ bus->sdcnt.f2rxdata++;
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ if (ret < 0) {
++ brcmf_err("read %d bytes from channel %d failed: %d\n",
++ rd->len, rd->channel, ret);
++ brcmu_pkt_buf_free_skb(pkt);
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_rxfail(bus, true,
++ RETRYCHAN(rd->channel));
++ sdio_release_host(bus->sdiodev->func[1]);
++ continue;
++ }
++
++ if (head_read) {
++ skb_push(pkt, head_read);
++ memcpy(pkt->data, bus->rxhdr, head_read);
++ head_read = 0;
++ } else {
++ memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
++ rd_new.seq_num = rd->seq_num;
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
++ BRCMF_SDIO_FT_NORMAL)) {
++ rd->len = 0;
++ brcmu_pkt_buf_free_skb(pkt);
++ }
++ bus->sdcnt.rx_readahead_cnt++;
++ if (rd->len != roundup(rd_new.len, 16)) {
++ brcmf_err("frame length mismatch:read %d, should be %d\n",
++ rd->len,
++ roundup(rd_new.len, 16) >> 4);
++ rd->len = 0;
++ brcmf_sdio_rxfail(bus, true, true);
++ sdio_release_host(bus->sdiodev->func[1]);
++ brcmu_pkt_buf_free_skb(pkt);
++ continue;
++ }
++ sdio_release_host(bus->sdiodev->func[1]);
++ rd->len_nxtfrm = rd_new.len_nxtfrm;
++ rd->channel = rd_new.channel;
++ rd->dat_offset = rd_new.dat_offset;
++
++ brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
++ BRCMF_DATA_ON()) &&
++ BRCMF_HDRS_ON(),
++ bus->rxhdr, SDPCM_HDRLEN,
++ "RxHdr:\n");
++
++ if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
++ brcmf_err("readahead on control packet %d?\n",
++ rd_new.seq_num);
++ /* Force retry w/normal header read */
++ rd->len = 0;
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_rxfail(bus, false, true);
++ sdio_release_host(bus->sdiodev->func[1]);
++ brcmu_pkt_buf_free_skb(pkt);
++ continue;
++ }
++ }
++
++ brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
++ pkt->data, rd->len, "Rx Data:\n");
++
++ /* Save superframe descriptor and allocate packet frame */
++ if (rd->channel == SDPCM_GLOM_CHANNEL) {
++ if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
++ brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
++ rd->len);
++ brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
++ pkt->data, rd->len,
++ "Glom Data:\n");
++ __skb_trim(pkt, rd->len);
++ skb_pull(pkt, SDPCM_HDRLEN);
++ bus->glomd = pkt;
++ } else {
++ brcmf_err("%s: glom superframe w/o "
++ "descriptor!\n", __func__);
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_rxfail(bus, false, false);
++ sdio_release_host(bus->sdiodev->func[1]);
++ }
++ /* prepare the descriptor for the next read */
++ rd->len = rd->len_nxtfrm << 4;
++ rd->len_nxtfrm = 0;
++ /* treat all packet as event if we don't know */
++ rd->channel = SDPCM_EVENT_CHANNEL;
++ continue;
++ }
++
++ /* Fill in packet len and prio, deliver upward */
++ __skb_trim(pkt, rd->len);
++ skb_pull(pkt, rd->dat_offset);
++
++ /* prepare the descriptor for the next read */
++ rd->len = rd->len_nxtfrm << 4;
++ rd->len_nxtfrm = 0;
++ /* treat all packet as event if we don't know */
++ rd->channel = SDPCM_EVENT_CHANNEL;
++
++ if (pkt->len == 0) {
++ brcmu_pkt_buf_free_skb(pkt);
++ continue;
++ }
++
++ brcmf_rx_frame(bus->sdiodev->dev, pkt);
++ }
++
++ rxcount = maxframes - rxleft;
++ /* Message if we hit the limit */
++ if (!rxleft)
++ brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
++ else
++ brcmf_dbg(DATA, "processed %d frames\n", rxcount);
++ /* Back off rxseq if awaiting rtx, update rx_seq */
++ if (bus->rxskip)
++ rd->seq_num--;
++ bus->rx_seq = rd->seq_num;
++
++ return rxcount;
++}
++
++static void
++brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
++{
++ if (waitqueue_active(&bus->ctrl_wait))
++ wake_up_interruptible(&bus->ctrl_wait);
++ return;
++}
++
++static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
++{
++ u16 head_pad;
++ u8 *dat_buf;
++
++ dat_buf = (u8 *)(pkt->data);
++
++ /* Check head padding */
++ head_pad = ((unsigned long)dat_buf % bus->head_align);
++ if (head_pad) {
++ if (skb_headroom(pkt) < head_pad) {
++ bus->sdiodev->bus_if->tx_realloc++;
++ head_pad = 0;
++ if (skb_cow(pkt, head_pad))
++ return -ENOMEM;
++ }
++ skb_push(pkt, head_pad);
++ dat_buf = (u8 *)(pkt->data);
++ memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
++ }
++ return head_pad;
++}
++
++/**
++ * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
++ * bus layer usage.
++ */
++/* flag marking a dummy skb added for DMA alignment requirement */
++#define ALIGN_SKB_FLAG 0x8000
++/* bit mask of data length chopped from the previous packet */
++#define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
++
++static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
++ struct sk_buff_head *pktq,
++ struct sk_buff *pkt, u16 total_len)
++{
++ struct brcmf_sdio_dev *sdiodev;
++ struct sk_buff *pkt_pad;
++ u16 tail_pad, tail_chop, chain_pad;
++ unsigned int blksize;
++ bool lastfrm;
++ int ntail, ret;
++
++ sdiodev = bus->sdiodev;
++ blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
++ /* sg entry alignment should be a divisor of block size */
++ WARN_ON(blksize % bus->sgentry_align);
++
++ /* Check tail padding */
++ lastfrm = skb_queue_is_last(pktq, pkt);
++ tail_pad = 0;
++ tail_chop = pkt->len % bus->sgentry_align;
++ if (tail_chop)
++ tail_pad = bus->sgentry_align - tail_chop;
++ chain_pad = (total_len + tail_pad) % blksize;
++ if (lastfrm && chain_pad)
++ tail_pad += blksize - chain_pad;
++ if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
++ pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
++ bus->head_align);
++ if (pkt_pad == NULL)
++ return -ENOMEM;
++ ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
++ if (unlikely(ret < 0)) {
++ kfree_skb(pkt_pad);
++ return ret;
++ }
++ memcpy(pkt_pad->data,
++ pkt->data + pkt->len - tail_chop,
++ tail_chop);
++ *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
++ skb_trim(pkt, pkt->len - tail_chop);
++ skb_trim(pkt_pad, tail_pad + tail_chop);
++ __skb_queue_after(pktq, pkt, pkt_pad);
++ } else {
++ ntail = pkt->data_len + tail_pad -
++ (pkt->end - pkt->tail);
++ if (skb_cloned(pkt) || ntail > 0)
++ if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
++ return -ENOMEM;
++ if (skb_linearize(pkt))
++ return -ENOMEM;
++ __skb_put(pkt, tail_pad);
++ }
++
++ return tail_pad;
++}
++
++/**
++ * brcmf_sdio_txpkt_prep - packet preparation for transmit
++ * @bus: brcmf_sdio structure pointer
++ * @pktq: packet list pointer
++ * @chan: virtual channel to transmit the packet
++ *
++ * Processes to be applied to the packet
++ * - Align data buffer pointer
++ * - Align data buffer length
++ * - Prepare header
++ * Return: negative value if there is error
++ */
++static int
++brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
++ uint chan)
++{
++ u16 head_pad, total_len;
++ struct sk_buff *pkt_next;
++ u8 txseq;
++ int ret;
++ struct brcmf_sdio_hdrinfo hd_info = {0};
++
++ txseq = bus->tx_seq;
++ total_len = 0;
++ skb_queue_walk(pktq, pkt_next) {
++ /* alignment packet inserted in previous
++ * loop cycle can be skipped as it is
++ * already properly aligned and does not
++ * need an sdpcm header.
++ */
++ if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
++ continue;
++
++ /* align packet data pointer */
++ ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
++ if (ret < 0)
++ return ret;
++ head_pad = (u16)ret;
++ if (head_pad)
++ memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
++
++ total_len += pkt_next->len;
++
++ hd_info.len = pkt_next->len;
++ hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
++ if (bus->txglom && pktq->qlen > 1) {
++ ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
++ pkt_next, total_len);
++ if (ret < 0)
++ return ret;
++ hd_info.tail_pad = (u16)ret;
++ total_len += (u16)ret;
++ }
++
++ hd_info.channel = chan;
++ hd_info.dat_offset = head_pad + bus->tx_hdrlen;
++ hd_info.seq_num = txseq++;
++
++ /* Now fill the header */
++ brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
++
++ if (BRCMF_BYTES_ON() &&
++ ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
++ (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
++ brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
++ "Tx Frame:\n");
++ else if (BRCMF_HDRS_ON())
++ brcmf_dbg_hex_dump(true, pkt_next->data,
++ head_pad + bus->tx_hdrlen,
++ "Tx Header:\n");
++ }
++ /* Hardware length tag of the first packet should be total
++ * length of the chain (including padding)
++ */
++ if (bus->txglom)
++ brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
++ return 0;
++}
++
++/**
++ * brcmf_sdio_txpkt_postp - packet post processing for transmit
++ * @bus: brcmf_sdio structure pointer
++ * @pktq: packet list pointer
++ *
++ * Processes to be applied to the packet
++ * - Remove head padding
++ * - Remove tail padding
++ */
++static void
++brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
++{
++ u8 *hdr;
++ u32 dat_offset;
++ u16 tail_pad;
++ u16 dummy_flags, chop_len;
++ struct sk_buff *pkt_next, *tmp, *pkt_prev;
++
++ skb_queue_walk_safe(pktq, pkt_next, tmp) {
++ dummy_flags = *(u16 *)(pkt_next->cb);
++ if (dummy_flags & ALIGN_SKB_FLAG) {
++ chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
++ if (chop_len) {
++ pkt_prev = pkt_next->prev;
++ skb_put(pkt_prev, chop_len);
++ }
++ __skb_unlink(pkt_next, pktq);
++ brcmu_pkt_buf_free_skb(pkt_next);
++ } else {
++ hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
++ dat_offset = le32_to_cpu(*(__le32 *)hdr);
++ dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
++ SDPCM_DOFFSET_SHIFT;
++ skb_pull(pkt_next, dat_offset);
++ if (bus->txglom) {
++ tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
++ skb_trim(pkt_next, pkt_next->len - tail_pad);
++ }
++ }
++ }
++}
++
++/* Writes a HW/SW header into the packet and sends it. */
++/* Assumes: (a) header space already there, (b) caller holds lock */
++static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
++ uint chan)
++{
++ int ret;
++ struct sk_buff *pkt_next, *tmp;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
++ if (ret)
++ goto done;
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++ ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
++ bus->sdcnt.f2txdata++;
++
++ if (ret < 0)
++ brcmf_sdio_txfail(bus);
++
++ sdio_release_host(bus->sdiodev->func[1]);
++
++done:
++ brcmf_sdio_txpkt_postp(bus, pktq);
++ if (ret == 0)
++ bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
++ skb_queue_walk_safe(pktq, pkt_next, tmp) {
++ __skb_unlink(pkt_next, pktq);
++ brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
++ }
++ return ret;
++}
++
++static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
++{
++ struct sk_buff *pkt;
++ struct sk_buff_head pktq;
++ u32 intstatus = 0;
++ int ret = 0, prec_out, i;
++ uint cnt = 0;
++ u8 tx_prec_map, pkt_num;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ tx_prec_map = ~bus->flowcontrol;
++
++ /* Send frames until the limit or some other event */
++ for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
++ pkt_num = 1;
++ if (bus->txglom)
++ pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
++ bus->sdiodev->txglomsz);
++ pkt_num = min_t(u32, pkt_num,
++ brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
++ __skb_queue_head_init(&pktq);
++ spin_lock_bh(&bus->txq_lock);
++ for (i = 0; i < pkt_num; i++) {
++ pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
++ &prec_out);
++ if (pkt == NULL)
++ break;
++ __skb_queue_tail(&pktq, pkt);
++ }
++ spin_unlock_bh(&bus->txq_lock);
++ if (i == 0)
++ break;
++
++ ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
++
++ cnt += i;
++
++ /* In poll mode, need to check for other events */
++ if (!bus->intr) {
++ /* Check device status, signal pending interrupt */
++ sdio_claim_host(bus->sdiodev->func[1]);
++ ret = r_sdreg32(bus, &intstatus,
++ offsetof(struct sdpcmd_regs,
++ intstatus));
++ sdio_release_host(bus->sdiodev->func[1]);
++ bus->sdcnt.f2txdata++;
++ if (ret != 0)
++ break;
++ if (intstatus & bus->hostintmask)
++ atomic_set(&bus->ipend, 1);
++ }
++ }
++
++ /* Deflow-control stack if needed */
++ if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
++ bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
++ bus->txoff = false;
++ brcmf_txflowblock(bus->sdiodev->dev, false);
++ }
++
++ return cnt;
++}
++
++static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
++{
++ u8 doff;
++ u16 pad;
++ uint retries = 0;
++ struct brcmf_sdio_hdrinfo hd_info = {0};
++ int ret;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* Back the pointer to make room for bus header */
++ frame -= bus->tx_hdrlen;
++ len += bus->tx_hdrlen;
++
++ /* Add alignment padding (optional for ctl frames) */
++ doff = ((unsigned long)frame % bus->head_align);
++ if (doff) {
++ frame -= doff;
++ len += doff;
++ memset(frame + bus->tx_hdrlen, 0, doff);
++ }
++
++ /* Round send length to next SDIO block */
++ pad = 0;
++ if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
++ pad = bus->blocksize - (len % bus->blocksize);
++ if ((pad > bus->roundup) || (pad >= bus->blocksize))
++ pad = 0;
++ } else if (len % bus->head_align) {
++ pad = bus->head_align - (len % bus->head_align);
++ }
++ len += pad;
++
++ hd_info.len = len - pad;
++ hd_info.channel = SDPCM_CONTROL_CHANNEL;
++ hd_info.dat_offset = doff + bus->tx_hdrlen;
++ hd_info.seq_num = bus->tx_seq;
++ hd_info.lastfrm = true;
++ hd_info.tail_pad = pad;
++ brcmf_sdio_hdpack(bus, frame, &hd_info);
++
++ if (bus->txglom)
++ brcmf_sdio_update_hwhdr(frame, len);
++
++ brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
++ frame, len, "Tx Frame:\n");
++ brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
++ BRCMF_HDRS_ON(),
++ frame, min_t(u16, len, 16), "TxHdr:\n");
++
++ do {
++ ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
++
++ if (ret < 0)
++ brcmf_sdio_txfail(bus);
++ else
++ bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
++ } while (ret < 0 && retries++ < TXRETRIES);
++
++ return ret;
++}
++
++static void brcmf_sdio_bus_stop(struct device *dev)
++{
++ u32 local_hostintmask;
++ u8 saveclk;
++ int err;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (bus->watchdog_tsk) {
++ send_sig(SIGTERM, bus->watchdog_tsk, 1);
++ kthread_stop(bus->watchdog_tsk);
++ bus->watchdog_tsk = NULL;
++ }
++
++ if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
++ sdio_claim_host(sdiodev->func[1]);
++
++ /* Enable clock for device interrupts */
++ brcmf_sdio_bus_sleep(bus, false, false);
++
++ /* Disable and clear interrupts at the chip level also */
++ w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
++ local_hostintmask = bus->hostintmask;
++ bus->hostintmask = 0;
++
++ /* Force backplane clocks to assure F2 interrupt propagates */
++ saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ &err);
++ if (!err)
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ (saveclk | SBSDIO_FORCE_HT), &err);
++ if (err)
++ brcmf_err("Failed to force clock for F2: err %d\n",
++ err);
++
++ /* Turn off the bus (F2), free any pending packets */
++ brcmf_dbg(INTR, "disable SDIO interrupts\n");
++ sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
++
++ /* Clear any pending interrupts now that F2 is disabled */
++ w_sdreg32(bus, local_hostintmask,
++ offsetof(struct sdpcmd_regs, intstatus));
++
++ sdio_release_host(sdiodev->func[1]);
++ }
++ /* Clear the data packet queues */
++ brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
++
++ /* Clear any held glomming stuff */
++ brcmu_pkt_buf_free_skb(bus->glomd);
++ brcmf_sdio_free_glom(bus);
++
++ /* Clear rx control and wake any waiters */
++ spin_lock_bh(&bus->rxctl_lock);
++ bus->rxlen = 0;
++ spin_unlock_bh(&bus->rxctl_lock);
++ brcmf_sdio_dcmd_resp_wake(bus);
++
++ /* Reset some F2 state stuff */
++ bus->rxskip = false;
++ bus->tx_seq = bus->rx_seq = 0;
++}
++
++static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
++{
++ unsigned long flags;
++
++ if (bus->sdiodev->oob_irq_requested) {
++ spin_lock_irqsave(&bus->sdiodev->irq_en_lock, flags);
++ if (!bus->sdiodev->irq_en && !atomic_read(&bus->ipend)) {
++ enable_irq(bus->sdiodev->pdata->oob_irq_nr);
++ bus->sdiodev->irq_en = true;
++ }
++ spin_unlock_irqrestore(&bus->sdiodev->irq_en_lock, flags);
++ }
++}
++
++static void atomic_orr(int val, atomic_t *v)
++{
++ int old_val;
++
++ old_val = atomic_read(v);
++ while (atomic_cmpxchg(v, old_val, val | old_val) != old_val)
++ old_val = atomic_read(v);
++}
++
++static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
++{
++ struct brcmf_core *buscore;
++ u32 addr;
++ unsigned long val;
++ int ret;
++
++ buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
++ addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
++
++ val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
++ bus->sdcnt.f1regdata++;
++ if (ret != 0)
++ return ret;
++
++ val &= bus->hostintmask;
++ atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
++
++ /* Clear interrupts */
++ if (val) {
++ brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
++ bus->sdcnt.f1regdata++;
++ atomic_orr(val, &bus->intstatus);
++ }
++
++ return ret;
++}
++
++static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
++{
++ u32 newstatus = 0;
++ unsigned long intstatus;
++ uint txlimit = bus->txbound; /* Tx frames to send before resched */
++ uint framecnt; /* Temporary counter of tx/rx frames */
++ int err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++
++ /* If waiting for HTAVAIL, check status */
++ if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
++ u8 clkctl, devctl = 0;
++
++#ifdef DEBUG
++ /* Check for inconsistent device control */
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
++#endif /* DEBUG */
++
++ /* Read CSR, if clock on switch to AVAIL, else ignore */
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, &err);
++
++ brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
++ devctl, clkctl);
++
++ if (SBSDIO_HTAV(clkctl)) {
++ devctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_DEVICE_CTL, &err);
++ devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
++ devctl, &err);
++ bus->clkstate = CLK_AVAIL;
++ }
++ }
++
++ /* Make sure backplane clock is on */
++ brcmf_sdio_bus_sleep(bus, false, true);
++
++ /* Pending interrupt indicates new device status */
++ if (atomic_read(&bus->ipend) > 0) {
++ atomic_set(&bus->ipend, 0);
++ err = brcmf_sdio_intr_rstatus(bus);
++ }
++
++ /* Start with leftover status bits */
++ intstatus = atomic_xchg(&bus->intstatus, 0);
++
++ /* Handle flow-control change: read new state in case our ack
++ * crossed another change interrupt. If change still set, assume
++ * FC ON for safety, let next loop through do the debounce.
++ */
++ if (intstatus & I_HMB_FC_CHANGE) {
++ intstatus &= ~I_HMB_FC_CHANGE;
++ err = w_sdreg32(bus, I_HMB_FC_CHANGE,
++ offsetof(struct sdpcmd_regs, intstatus));
++
++ err = r_sdreg32(bus, &newstatus,
++ offsetof(struct sdpcmd_regs, intstatus));
++ bus->sdcnt.f1regdata += 2;
++ atomic_set(&bus->fcstate,
++ !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
++ intstatus |= (newstatus & bus->hostintmask);
++ }
++
++ /* Handle host mailbox indication */
++ if (intstatus & I_HMB_HOST_INT) {
++ intstatus &= ~I_HMB_HOST_INT;
++ intstatus |= brcmf_sdio_hostmail(bus);
++ }
++
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ /* Generally don't ask for these, can get CRC errors... */
++ if (intstatus & I_WR_OOSYNC) {
++ brcmf_err("Dongle reports WR_OOSYNC\n");
++ intstatus &= ~I_WR_OOSYNC;
++ }
++
++ if (intstatus & I_RD_OOSYNC) {
++ brcmf_err("Dongle reports RD_OOSYNC\n");
++ intstatus &= ~I_RD_OOSYNC;
++ }
++
++ if (intstatus & I_SBINT) {
++ brcmf_err("Dongle reports SBINT\n");
++ intstatus &= ~I_SBINT;
++ }
++
++ /* Would be active due to wake-wlan in gSPI */
++ if (intstatus & I_CHIPACTIVE) {
++ brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
++ intstatus &= ~I_CHIPACTIVE;
++ }
++
++ /* Ignore frame indications if rxskip is set */
++ if (bus->rxskip)
++ intstatus &= ~I_HMB_FRAME_IND;
++
++ /* On frame indication, read available frames */
++ if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
++ brcmf_sdio_readframes(bus, bus->rxbound);
++ if (!bus->rxpending)
++ intstatus &= ~I_HMB_FRAME_IND;
++ }
++
++ /* Keep still-pending events for next scheduling */
++ if (intstatus)
++ atomic_orr(intstatus, &bus->intstatus);
++
++ brcmf_sdio_clrintr(bus);
++
++ if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
++ data_ok(bus)) {
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (bus->ctrl_frame_stat) {
++ err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
++ bus->ctrl_frame_len);
++ bus->ctrl_frame_err = err;
++ wmb();
++ bus->ctrl_frame_stat = false;
++ }
++ sdio_release_host(bus->sdiodev->func[1]);
++ brcmf_sdio_wait_event_wakeup(bus);
++ }
++ /* Send queued frames (limit 1 if rx may still be pending) */
++ if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
++ brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
++ data_ok(bus)) {
++ framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
++ txlimit;
++ brcmf_sdio_sendfromq(bus, framecnt);
++ }
++
++ if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
++ brcmf_err("failed backplane access over SDIO, halting operation\n");
++ atomic_set(&bus->intstatus, 0);
++ if (bus->ctrl_frame_stat) {
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (bus->ctrl_frame_stat) {
++ bus->ctrl_frame_err = -ENODEV;
++ wmb();
++ bus->ctrl_frame_stat = false;
++ brcmf_sdio_wait_event_wakeup(bus);
++ }
++ sdio_release_host(bus->sdiodev->func[1]);
++ }
++ } else if (atomic_read(&bus->intstatus) ||
++ atomic_read(&bus->ipend) > 0 ||
++ (!atomic_read(&bus->fcstate) &&
++ brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
++ data_ok(bus))) {
++ bus->dpc_triggered = true;
++ }
++}
++
++static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++
++ return &bus->txq;
++}
++
++static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
++{
++ struct sk_buff *p;
++ int eprec = -1; /* precedence to evict from */
++
++ /* Fast case, precedence queue is not full and we are also not
++ * exceeding total queue length
++ */
++ if (!pktq_pfull(q, prec) && !pktq_full(q)) {
++ brcmu_pktq_penq(q, prec, pkt);
++ return true;
++ }
++
++ /* Determine precedence from which to evict packet, if any */
++ if (pktq_pfull(q, prec)) {
++ eprec = prec;
++ } else if (pktq_full(q)) {
++ p = brcmu_pktq_peek_tail(q, &eprec);
++ if (eprec > prec)
++ return false;
++ }
++
++ /* Evict if needed */
++ if (eprec >= 0) {
++ /* Detect queueing to unconfigured precedence */
++ if (eprec == prec)
++ return false; /* refuse newer (incoming) packet */
++ /* Evict packet according to discard policy */
++ p = brcmu_pktq_pdeq_tail(q, eprec);
++ if (p == NULL)
++ brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
++ brcmu_pkt_buf_free_skb(p);
++ }
++
++ /* Enqueue */
++ p = brcmu_pktq_penq(q, prec, pkt);
++ if (p == NULL)
++ brcmf_err("brcmu_pktq_penq() failed\n");
++
++ return p != NULL;
++}
++
++static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
++{
++ int ret = -EBADE;
++ uint prec;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++
++ brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
++
++ /* Add space for the header */
++ skb_push(pkt, bus->tx_hdrlen);
++ /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
++
++ prec = prio2prec((pkt->priority & PRIOMASK));
++
++ /* Check for existing queue, current flow-control,
++ pending event, or pending clock */
++ brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
++ bus->sdcnt.fcqueued++;
++
++ /* Priority based enq */
++ spin_lock_bh(&bus->txq_lock);
++ /* reset bus_flags in packet cb */
++ *(u16 *)(pkt->cb) = 0;
++ if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
++ skb_pull(pkt, bus->tx_hdrlen);
++ brcmf_err("out of bus->txq !!!\n");
++ ret = -ENOSR;
++ } else {
++ ret = 0;
++ }
++
++ if (pktq_len(&bus->txq) >= TXHI) {
++ bus->txoff = true;
++ brcmf_txflowblock(dev, true);
++ }
++ spin_unlock_bh(&bus->txq_lock);
++
++#ifdef DEBUG
++ if (pktq_plen(&bus->txq, prec) > qcount[prec])
++ qcount[prec] = pktq_plen(&bus->txq, prec);
++#endif
++
++ brcmf_sdio_trigger_dpc(bus);
++ return ret;
++}
++
++#ifdef DEBUG
++#define CONSOLE_LINE_MAX 192
++
++static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
++{
++ struct brcmf_console *c = &bus->console;
++ u8 line[CONSOLE_LINE_MAX], ch;
++ u32 n, idx, addr;
++ int rv;
++
++ /* Don't do anything until FWREADY updates console address */
++ if (bus->console_addr == 0)
++ return 0;
++
++ /* Read console log struct */
++ addr = bus->console_addr + offsetof(struct rte_console, log_le);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
++ sizeof(c->log_le));
++ if (rv < 0)
++ return rv;
++
++ /* Allocate console buffer (one time only) */
++ if (c->buf == NULL) {
++ c->bufsize = le32_to_cpu(c->log_le.buf_size);
++ c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
++ if (c->buf == NULL)
++ return -ENOMEM;
++ }
++
++ idx = le32_to_cpu(c->log_le.idx);
++
++ /* Protect against corrupt value */
++ if (idx > c->bufsize)
++ return -EBADE;
++
++ /* Skip reading the console buffer if the index pointer
++ has not moved */
++ if (idx == c->last)
++ return 0;
++
++ /* Read the console buffer */
++ addr = le32_to_cpu(c->log_le.buf);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
++ if (rv < 0)
++ return rv;
++
++ while (c->last != idx) {
++ for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
++ if (c->last == idx) {
++ /* This would output a partial line.
++ * Instead, back up
++ * the buffer pointer and output this
++ * line next time around.
++ */
++ if (c->last >= n)
++ c->last -= n;
++ else
++ c->last = c->bufsize - n;
++ goto break2;
++ }
++ ch = c->buf[c->last];
++ c->last = (c->last + 1) % c->bufsize;
++ if (ch == '\n')
++ break;
++ line[n] = ch;
++ }
++
++ if (n > 0) {
++ if (line[n - 1] == '\r')
++ n--;
++ line[n] = 0;
++ pr_debug("CONSOLE: %s\n", line);
++ }
++ }
++break2:
++
++ return 0;
++}
++#endif /* DEBUG */
++
++static int
++brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++ int ret;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* Send from dpc */
++ bus->ctrl_frame_buf = msg;
++ bus->ctrl_frame_len = msglen;
++ wmb();
++ bus->ctrl_frame_stat = true;
++
++ brcmf_sdio_trigger_dpc(bus);
++ wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
++ msecs_to_jiffies(CTL_DONE_TIMEOUT));
++ ret = 0;
++ if (bus->ctrl_frame_stat) {
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (bus->ctrl_frame_stat) {
++ brcmf_dbg(SDIO, "ctrl_frame timeout\n");
++ bus->ctrl_frame_stat = false;
++ ret = -ETIMEDOUT;
++ }
++ sdio_release_host(bus->sdiodev->func[1]);
++ }
++ if (!ret) {
++ brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
++ bus->ctrl_frame_err);
++ rmb();
++ ret = bus->ctrl_frame_err;
++ }
++
++ if (ret)
++ bus->sdcnt.tx_ctlerrs++;
++ else
++ bus->sdcnt.tx_ctlpkts++;
++
++ return ret;
++}
++
++#ifdef DEBUG
++static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
++ struct sdpcm_shared *sh)
++{
++ u32 addr, console_ptr, console_size, console_index;
++ char *conbuf = NULL;
++ __le32 sh_val;
++ int rv;
++
++ /* obtain console information from device memory */
++ addr = sh->console_addr + offsetof(struct rte_console, log_le);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
++ (u8 *)&sh_val, sizeof(u32));
++ if (rv < 0)
++ return rv;
++ console_ptr = le32_to_cpu(sh_val);
++
++ addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
++ (u8 *)&sh_val, sizeof(u32));
++ if (rv < 0)
++ return rv;
++ console_size = le32_to_cpu(sh_val);
++
++ addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
++ (u8 *)&sh_val, sizeof(u32));
++ if (rv < 0)
++ return rv;
++ console_index = le32_to_cpu(sh_val);
++
++ /* allocate buffer for console data */
++ if (console_size <= CONSOLE_BUFFER_MAX)
++ conbuf = vzalloc(console_size+1);
++
++ if (!conbuf)
++ return -ENOMEM;
++
++ /* obtain the console data from device */
++ conbuf[console_size] = '\0';
++ rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
++ console_size);
++ if (rv < 0)
++ goto done;
++
++ rv = seq_write(seq, conbuf + console_index,
++ console_size - console_index);
++ if (rv < 0)
++ goto done;
++
++ if (console_index > 0)
++ rv = seq_write(seq, conbuf, console_index - 1);
++
++done:
++ vfree(conbuf);
++ return rv;
++}
++
++static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
++ struct sdpcm_shared *sh)
++{
++ int error;
++ struct brcmf_trap_info tr;
++
++ if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
++ brcmf_dbg(INFO, "no trap in firmware\n");
++ return 0;
++ }
++
++ error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
++ sizeof(struct brcmf_trap_info));
++ if (error < 0)
++ return error;
++
++ seq_printf(seq,
++ "dongle trap info: type 0x%x @ epc 0x%08x\n"
++ " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
++ " lr 0x%08x pc 0x%08x offset 0x%x\n"
++ " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
++ " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
++ le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
++ le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
++ le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
++ le32_to_cpu(tr.pc), sh->trap_addr,
++ le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
++ le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
++ le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
++ le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
++
++ return 0;
++}
++
++static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
++ struct sdpcm_shared *sh)
++{
++ int error = 0;
++ char file[80] = "?";
++ char expr[80] = "<???>";
++
++ if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
++ brcmf_dbg(INFO, "firmware not built with -assert\n");
++ return 0;
++ } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
++ brcmf_dbg(INFO, "no assert in dongle\n");
++ return 0;
++ }
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++ if (sh->assert_file_addr != 0) {
++ error = brcmf_sdiod_ramrw(bus->sdiodev, false,
++ sh->assert_file_addr, (u8 *)file, 80);
++ if (error < 0)
++ return error;
++ }
++ if (sh->assert_exp_addr != 0) {
++ error = brcmf_sdiod_ramrw(bus->sdiodev, false,
++ sh->assert_exp_addr, (u8 *)expr, 80);
++ if (error < 0)
++ return error;
++ }
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
++ file, sh->assert_line, expr);
++ return 0;
++}
++
++static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
++{
++ int error;
++ struct sdpcm_shared sh;
++
++ error = brcmf_sdio_readshared(bus, &sh);
++
++ if (error < 0)
++ return error;
++
++ if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
++ brcmf_dbg(INFO, "firmware not built with -assert\n");
++ else if (sh.flags & SDPCM_SHARED_ASSERT)
++ brcmf_err("assertion in dongle\n");
++
++ if (sh.flags & SDPCM_SHARED_TRAP)
++ brcmf_err("firmware trap in dongle\n");
++
++ return 0;
++}
++
++static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
++{
++ int error = 0;
++ struct sdpcm_shared sh;
++
++ error = brcmf_sdio_readshared(bus, &sh);
++ if (error < 0)
++ goto done;
++
++ error = brcmf_sdio_assert_info(seq, bus, &sh);
++ if (error < 0)
++ goto done;
++
++ error = brcmf_sdio_trap_info(seq, bus, &sh);
++ if (error < 0)
++ goto done;
++
++ error = brcmf_sdio_dump_console(seq, bus, &sh);
++
++done:
++ return error;
++}
++
++static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
++ struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
++
++ return brcmf_sdio_died_dump(seq, bus);
++}
++
++static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
++
++ seq_printf(seq,
++ "intrcount: %u\nlastintrs: %u\n"
++ "pollcnt: %u\nregfails: %u\n"
++ "tx_sderrs: %u\nfcqueued: %u\n"
++ "rxrtx: %u\nrx_toolong: %u\n"
++ "rxc_errors: %u\nrx_hdrfail: %u\n"
++ "rx_badhdr: %u\nrx_badseq: %u\n"
++ "fc_rcvd: %u\nfc_xoff: %u\n"
++ "fc_xon: %u\nrxglomfail: %u\n"
++ "rxglomframes: %u\nrxglompkts: %u\n"
++ "f2rxhdrs: %u\nf2rxdata: %u\n"
++ "f2txdata: %u\nf1regdata: %u\n"
++ "tickcnt: %u\ntx_ctlerrs: %lu\n"
++ "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
++ "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
++ sdcnt->intrcount, sdcnt->lastintrs,
++ sdcnt->pollcnt, sdcnt->regfails,
++ sdcnt->tx_sderrs, sdcnt->fcqueued,
++ sdcnt->rxrtx, sdcnt->rx_toolong,
++ sdcnt->rxc_errors, sdcnt->rx_hdrfail,
++ sdcnt->rx_badhdr, sdcnt->rx_badseq,
++ sdcnt->fc_rcvd, sdcnt->fc_xoff,
++ sdcnt->fc_xon, sdcnt->rxglomfail,
++ sdcnt->rxglomframes, sdcnt->rxglompkts,
++ sdcnt->f2rxhdrs, sdcnt->f2rxdata,
++ sdcnt->f2txdata, sdcnt->f1regdata,
++ sdcnt->tickcnt, sdcnt->tx_ctlerrs,
++ sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
++ sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
++
++ return 0;
++}
++
++static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
++{
++ struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
++ struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
++
++ if (IS_ERR_OR_NULL(dentry))
++ return;
++
++ brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
++ brcmf_debugfs_add_entry(drvr, "counters",
++ brcmf_debugfs_sdio_count_read);
++ debugfs_create_u32("console_interval", 0644, dentry,
++ &bus->console_interval);
++}
++#else
++static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
++{
++ return 0;
++}
++
++static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
++{
++}
++#endif /* DEBUG */
++
++static int
++brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
++{
++ int timeleft;
++ uint rxlen = 0;
++ bool pending;
++ u8 *buf;
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* Wait until control frame is available */
++ timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
++
++ spin_lock_bh(&bus->rxctl_lock);
++ rxlen = bus->rxlen;
++ memcpy(msg, bus->rxctl, min(msglen, rxlen));
++ bus->rxctl = NULL;
++ buf = bus->rxctl_orig;
++ bus->rxctl_orig = NULL;
++ bus->rxlen = 0;
++ spin_unlock_bh(&bus->rxctl_lock);
++ vfree(buf);
++
++ if (rxlen) {
++ brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
++ rxlen, msglen);
++ } else if (timeleft == 0) {
++ brcmf_err("resumed on timeout\n");
++ brcmf_sdio_checkdied(bus);
++ } else if (pending) {
++ brcmf_dbg(CTL, "cancelled\n");
++ return -ERESTARTSYS;
++ } else {
++ brcmf_dbg(CTL, "resumed for unknown reason?\n");
++ brcmf_sdio_checkdied(bus);
++ }
++
++ if (rxlen)
++ bus->sdcnt.rx_ctlpkts++;
++ else
++ bus->sdcnt.rx_ctlerrs++;
++
++ return rxlen ? (int)rxlen : -ETIMEDOUT;
++}
++
++#ifdef DEBUG
++static bool
++brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
++ u8 *ram_data, uint ram_sz)
++{
++ char *ram_cmp;
++ int err;
++ bool ret = true;
++ int address;
++ int offset;
++ int len;
++
++ /* read back and verify */
++ brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
++ ram_sz);
++ ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
++ /* do not proceed while no memory but */
++ if (!ram_cmp)
++ return true;
++
++ address = ram_addr;
++ offset = 0;
++ while (offset < ram_sz) {
++ len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
++ ram_sz - offset;
++ err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
++ if (err) {
++ brcmf_err("error %d on reading %d membytes at 0x%08x\n",
++ err, len, address);
++ ret = false;
++ break;
++ } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
++ brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
++ offset, len);
++ ret = false;
++ break;
++ }
++ offset += len;
++ address += len;
++ }
++
++ kfree(ram_cmp);
++
++ return ret;
++}
++#else /* DEBUG */
++static bool
++brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
++ u8 *ram_data, uint ram_sz)
++{
++ return true;
++}
++#endif /* DEBUG */
++
++static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
++ const struct firmware *fw)
++{
++ int err;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
++ (u8 *)fw->data, fw->size);
++ if (err)
++ brcmf_err("error %d on writing %d membytes at 0x%08x\n",
++ err, (int)fw->size, bus->ci->rambase);
++ else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
++ (u8 *)fw->data, fw->size))
++ err = -EIO;
++
++ return err;
++}
++
++static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
++ void *vars, u32 varsz)
++{
++ int address;
++ int err;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ address = bus->ci->ramsize - varsz + bus->ci->rambase;
++ err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
++ if (err)
++ brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
++ err, varsz, address);
++ else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
++ err = -EIO;
++
++ return err;
++}
++
++static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
++ const struct firmware *fw,
++ void *nvram, u32 nvlen)
++{
++ int bcmerror = -EFAULT;
++ u32 rstvec;
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
++
++ rstvec = get_unaligned_le32(fw->data);
++ brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
++
++ bcmerror = brcmf_sdio_download_code_file(bus, fw);
++ release_firmware(fw);
++ if (bcmerror) {
++ brcmf_err("dongle image file download failed\n");
++ brcmf_fw_nvram_free(nvram);
++ goto err;
++ }
++
++ bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
++ brcmf_fw_nvram_free(nvram);
++ if (bcmerror) {
++ brcmf_err("dongle nvram file download failed\n");
++ goto err;
++ }
++
++ /* Take arm out of reset */
++ if (!brcmf_chip_set_active(bus->ci, rstvec)) {
++ brcmf_err("error getting out of ARM core reset\n");
++ goto err;
++ }
++
++ /* Allow full data communication using DPC from now on. */
++ brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
++ bcmerror = 0;
++
++err:
++ brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
++ sdio_release_host(bus->sdiodev->func[1]);
++ return bcmerror;
++}
++
++static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
++{
++ int err = 0;
++ u8 val;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
++ if (err) {
++ brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
++ return;
++ }
++
++ val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
++ if (err) {
++ brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
++ return;
++ }
++
++ /* Add CMD14 Support */
++ brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
++ (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
++ SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
++ &err);
++ if (err) {
++ brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
++ return;
++ }
++
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ SBSDIO_FORCE_HT, &err);
++ if (err) {
++ brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
++ return;
++ }
++
++ /* set flag */
++ bus->sr_enabled = true;
++ brcmf_dbg(INFO, "SR enabled\n");
++}
++
++/* enable KSO bit */
++static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
++{
++ u8 val;
++ int err = 0;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* KSO bit added in SDIO core rev 12 */
++ if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
++ return 0;
++
++ val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
++ if (err) {
++ brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
++ return err;
++ }
++
++ if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
++ val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
++ SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
++ val, &err);
++ if (err) {
++ brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
++ return err;
++ }
++ }
++
++ return 0;
++}
++
++
++static int brcmf_sdio_bus_preinit(struct device *dev)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++ uint pad_size;
++ u32 value;
++ int err;
++
++ /* the commands below use the terms tx and rx from
++ * a device perspective, ie. bus:txglom affects the
++ * bus transfers from device to host.
++ */
++ if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
++ /* for sdio core rev < 12, disable txgloming */
++ value = 0;
++ err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
++ sizeof(u32));
++ } else {
++ /* otherwise, set txglomalign */
++ value = 4;
++ if (sdiodev->pdata)
++ value = sdiodev->pdata->sd_sgentry_align;
++ /* SDIO ADMA requires at least 32 bit alignment */
++ value = max_t(u32, value, 4);
++ err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
++ sizeof(u32));
++ }
++
++ if (err < 0)
++ goto done;
++
++ bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
++ if (sdiodev->sg_support) {
++ bus->txglom = false;
++ value = 1;
++ pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
++ err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
++ &value, sizeof(u32));
++ if (err < 0) {
++ /* bus:rxglom is allowed to fail */
++ err = 0;
++ } else {
++ bus->txglom = true;
++ bus->tx_hdrlen += SDPCM_HWEXT_LEN;
++ }
++ }
++ brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
++
++done:
++ return err;
++}
++
++void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
++{
++ if (!bus->dpc_triggered) {
++ bus->dpc_triggered = true;
++ queue_work(bus->brcmf_wq, &bus->datawork);
++ }
++}
++
++void brcmf_sdio_isr(struct brcmf_sdio *bus)
++{
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (!bus) {
++ brcmf_err("bus is null pointer, exiting\n");
++ return;
++ }
++
++ /* Count the interrupt call */
++ bus->sdcnt.intrcount++;
++ if (in_interrupt())
++ atomic_set(&bus->ipend, 1);
++ else
++ if (brcmf_sdio_intr_rstatus(bus)) {
++ brcmf_err("failed backplane access\n");
++ }
++
++ /* Disable additional interrupts (is this needed now)? */
++ if (!bus->intr)
++ brcmf_err("isr w/o interrupt configured!\n");
++
++ bus->dpc_triggered = true;
++ queue_work(bus->brcmf_wq, &bus->datawork);
++}
++
++static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
++{
++ brcmf_dbg(TIMER, "Enter\n");
++
++ /* Poll period: check device if appropriate. */
++ if (!bus->sr_enabled &&
++ bus->poll && (++bus->polltick >= bus->pollrate)) {
++ u32 intstatus = 0;
++
++ /* Reset poll tick */
++ bus->polltick = 0;
++
++ /* Check device if no interrupts */
++ if (!bus->intr ||
++ (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
++
++ if (!bus->dpc_triggered) {
++ u8 devpend;
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++ devpend = brcmf_sdiod_regrb(bus->sdiodev,
++ SDIO_CCCR_INTx,
++ NULL);
++ sdio_release_host(bus->sdiodev->func[1]);
++ intstatus = devpend & (INTR_STATUS_FUNC1 |
++ INTR_STATUS_FUNC2);
++ }
++
++ /* If there is something, make like the ISR and
++ schedule the DPC */
++ if (intstatus) {
++ bus->sdcnt.pollcnt++;
++ atomic_set(&bus->ipend, 1);
++
++ bus->dpc_triggered = true;
++ queue_work(bus->brcmf_wq, &bus->datawork);
++ }
++ }
++
++ /* Update interrupt tracking */
++ bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
++ }
++#ifdef DEBUG
++ /* Poll for console output periodically */
++ if (bus->sdiodev->state == BRCMF_SDIOD_DATA &&
++ bus->console_interval != 0) {
++ bus->console.count += BRCMF_WD_POLL_MS;
++ if (bus->console.count >= bus->console_interval) {
++ bus->console.count -= bus->console_interval;
++ sdio_claim_host(bus->sdiodev->func[1]);
++ /* Make sure backplane clock is on */
++ brcmf_sdio_bus_sleep(bus, false, false);
++ if (brcmf_sdio_readconsole(bus) < 0)
++ /* stop on error */
++ bus->console_interval = 0;
++ sdio_release_host(bus->sdiodev->func[1]);
++ }
++ }
++#endif /* DEBUG */
++
++ /* On idle timeout clear activity flag and/or turn off clock */
++ if (!bus->dpc_triggered) {
++ rmb();
++ if ((!bus->dpc_running) && (bus->idletime > 0) &&
++ (bus->clkstate == CLK_AVAIL)) {
++ bus->idlecount++;
++ if (bus->idlecount > bus->idletime) {
++ brcmf_dbg(SDIO, "idle\n");
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_wd_timer(bus, 0);
++ bus->idlecount = 0;
++ brcmf_sdio_bus_sleep(bus, true, false);
++ sdio_release_host(bus->sdiodev->func[1]);
++ }
++ } else {
++ bus->idlecount = 0;
++ }
++ } else {
++ bus->idlecount = 0;
++ }
++}
++
++static void brcmf_sdio_dataworker(struct work_struct *work)
++{
++ struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
++ datawork);
++
++ bus->dpc_running = true;
++ wmb();
++ while (ACCESS_ONCE(bus->dpc_triggered)) {
++ bus->dpc_triggered = false;
++ brcmf_sdio_dpc(bus);
++ bus->idlecount = 0;
++ }
++ bus->dpc_running = false;
++ if (brcmf_sdiod_freezing(bus->sdiodev)) {
++ brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
++ brcmf_sdiod_try_freeze(bus->sdiodev);
++ brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
++ }
++}
++
++static void
++brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
++ struct brcmf_chip *ci, u32 drivestrength)
++{
++ const struct sdiod_drive_str *str_tab = NULL;
++ u32 str_mask;
++ u32 str_shift;
++ u32 base;
++ u32 i;
++ u32 drivestrength_sel = 0;
++ u32 cc_data_temp;
++ u32 addr;
++
++ if (!(ci->cc_caps & CC_CAP_PMU))
++ return;
++
++ switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
++ case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
++ str_tab = sdiod_drvstr_tab1_1v8;
++ str_mask = 0x00003800;
++ str_shift = 11;
++ break;
++ case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
++ str_tab = sdiod_drvstr_tab6_1v8;
++ str_mask = 0x00001800;
++ str_shift = 11;
++ break;
++ case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
++ /* note: 43143 does not support tristate */
++ i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
++ if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
++ str_tab = sdiod_drvstr_tab2_3v3;
++ str_mask = 0x00000007;
++ str_shift = 0;
++ } else
++ brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
++ ci->name, drivestrength);
++ break;
++ case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
++ str_tab = sdiod_drive_strength_tab5_1v8;
++ str_mask = 0x00003800;
++ str_shift = 11;
++ break;
++ default:
++ brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
++ ci->name, ci->chiprev, ci->pmurev);
++ break;
++ }
++
++ if (str_tab != NULL) {
++ for (i = 0; str_tab[i].strength != 0; i++) {
++ if (drivestrength >= str_tab[i].strength) {
++ drivestrength_sel = str_tab[i].sel;
++ break;
++ }
++ }
++ base = brcmf_chip_get_chipcommon(ci)->base;
++ addr = CORE_CC_REG(base, chipcontrol_addr);
++ brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
++ cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
++ cc_data_temp &= ~str_mask;
++ drivestrength_sel <<= str_shift;
++ cc_data_temp |= drivestrength_sel;
++ brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
++
++ brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
++ str_tab[i].strength, drivestrength, cc_data_temp);
++ }
++}
++
++static int brcmf_sdio_buscoreprep(void *ctx)
++{
++ struct brcmf_sdio_dev *sdiodev = ctx;
++ int err = 0;
++ u8 clkval, clkset;
++
++ /* Try forcing SDIO core to do ALPAvail request only */
++ clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
++ if (err) {
++ brcmf_err("error writing for HT off\n");
++ return err;
++ }
++
++ /* If register supported, wait for ALPAvail and then force ALP */
++ /* This may take up to 15 milliseconds */
++ clkval = brcmf_sdiod_regrb(sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, NULL);
++
++ if ((clkval & ~SBSDIO_AVBITS) != clkset) {
++ brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
++ clkset, clkval);
++ return -EACCES;
++ }
++
++ SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
++ !SBSDIO_ALPAV(clkval)),
++ PMU_MAX_TRANSITION_DLY);
++ if (!SBSDIO_ALPAV(clkval)) {
++ brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
++ clkval);
++ return -EBUSY;
++ }
++
++ clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
++ udelay(65);
++
++ /* Also, disable the extra SDIO pull-ups */
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
++
++ return 0;
++}
++
++static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
++ u32 rstvec)
++{
++ struct brcmf_sdio_dev *sdiodev = ctx;
++ struct brcmf_core *core;
++ u32 reg_addr;
++
++ /* clear all interrupts */
++ core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
++ reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
++ brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
++
++ if (rstvec)
++ /* Write reset vector to address 0 */
++ brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
++ sizeof(rstvec));
++}
++
++static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
++{
++ struct brcmf_sdio_dev *sdiodev = ctx;
++ u32 val, rev;
++
++ val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
++ if (sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 &&
++ addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
++ rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
++ if (rev >= 2) {
++ val &= ~CID_ID_MASK;
++ val |= BRCM_CC_4339_CHIP_ID;
++ }
++ }
++ return val;
++}
++
++static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
++{
++ struct brcmf_sdio_dev *sdiodev = ctx;
++
++ brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
++}
++
++static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
++ .prepare = brcmf_sdio_buscoreprep,
++ .activate = brcmf_sdio_buscore_activate,
++ .read32 = brcmf_sdio_buscore_read32,
++ .write32 = brcmf_sdio_buscore_write32,
++};
++
++static bool
++brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
++{
++ u8 clkctl = 0;
++ int err = 0;
++ int reg_addr;
++ u32 reg_val;
++ u32 drivestrength;
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++
++ pr_debug("F1 signature read @0x18000000=0x%4x\n",
++ brcmf_sdiod_regrl(bus->sdiodev, SI_ENUM_BASE, NULL));
++
++ /*
++ * Force PLL off until brcmf_chip_attach()
++ * programs PLL control regs
++ */
++
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ BRCMF_INIT_CLKCTL1, &err);
++ if (!err)
++ clkctl = brcmf_sdiod_regrb(bus->sdiodev,
++ SBSDIO_FUNC1_CHIPCLKCSR, &err);
++
++ if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
++ brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
++ err, BRCMF_INIT_CLKCTL1, clkctl);
++ goto fail;
++ }
++
++ bus->ci = brcmf_chip_attach(bus->sdiodev, &brcmf_sdio_buscore_ops);
++ if (IS_ERR(bus->ci)) {
++ brcmf_err("brcmf_chip_attach failed!\n");
++ bus->ci = NULL;
++ goto fail;
++ }
++
++ if (brcmf_sdio_kso_init(bus)) {
++ brcmf_err("error enabling KSO\n");
++ goto fail;
++ }
++
++ if ((bus->sdiodev->pdata) && (bus->sdiodev->pdata->drive_strength))
++ drivestrength = bus->sdiodev->pdata->drive_strength;
++ else
++ drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
++ brcmf_sdio_drivestrengthinit(bus->sdiodev, bus->ci, drivestrength);
++
++ /* Set card control so an SDIO card reset does a WLAN backplane reset */
++ reg_val = brcmf_sdiod_regrb(bus->sdiodev,
++ SDIO_CCCR_BRCM_CARDCTRL, &err);
++ if (err)
++ goto fail;
++
++ reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
++
++ brcmf_sdiod_regwb(bus->sdiodev,
++ SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
++ if (err)
++ goto fail;
++
++ /* set PMUControl so a backplane reset does PMU state reload */
++ reg_addr = CORE_CC_REG(brcmf_chip_get_chipcommon(bus->ci)->base,
++ pmucontrol);
++ reg_val = brcmf_sdiod_regrl(bus->sdiodev, reg_addr, &err);
++ if (err)
++ goto fail;
++
++ reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
++
++ brcmf_sdiod_regwl(bus->sdiodev, reg_addr, reg_val, &err);
++ if (err)
++ goto fail;
++
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
++
++ /* allocate header buffer */
++ bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
++ if (!bus->hdrbuf)
++ return false;
++ /* Locate an appropriately-aligned portion of hdrbuf */
++ bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
++ bus->head_align);
++
++ /* Set the poll and/or interrupt flags */
++ bus->intr = true;
++ bus->poll = false;
++ if (bus->poll)
++ bus->pollrate = 1;
++
++ return true;
++
++fail:
++ sdio_release_host(bus->sdiodev->func[1]);
++ return false;
++}
++
++static int
++brcmf_sdio_watchdog_thread(void *data)
++{
++ struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
++ int wait;
++
++ allow_signal(SIGTERM);
++ /* Run until signal received */
++ brcmf_sdiod_freezer_count(bus->sdiodev);
++ while (1) {
++ if (kthread_should_stop())
++ break;
++ brcmf_sdiod_freezer_uncount(bus->sdiodev);
++ wait = wait_for_completion_interruptible(&bus->watchdog_wait);
++ brcmf_sdiod_freezer_count(bus->sdiodev);
++ brcmf_sdiod_try_freeze(bus->sdiodev);
++ if (!wait) {
++ brcmf_sdio_bus_watchdog(bus);
++ /* Count the tick for reference */
++ bus->sdcnt.tickcnt++;
++ reinit_completion(&bus->watchdog_wait);
++ } else
++ break;
++ }
++ return 0;
++}
++
++static void
++brcmf_sdio_watchdog(unsigned long data)
++{
++ struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
++
++ if (bus->watchdog_tsk) {
++ complete(&bus->watchdog_wait);
++ /* Reschedule the watchdog */
++ if (bus->wd_timer_valid)
++ mod_timer(&bus->timer,
++ jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
++ }
++}
++
++static struct brcmf_bus_ops brcmf_sdio_bus_ops = {
++ .stop = brcmf_sdio_bus_stop,
++ .preinit = brcmf_sdio_bus_preinit,
++ .txdata = brcmf_sdio_bus_txdata,
++ .txctl = brcmf_sdio_bus_txctl,
++ .rxctl = brcmf_sdio_bus_rxctl,
++ .gettxq = brcmf_sdio_bus_gettxq,
++ .wowl_config = brcmf_sdio_wowl_config
++};
++
++static void brcmf_sdio_firmware_callback(struct device *dev,
++ const struct firmware *code,
++ void *nvram, u32 nvram_len)
++{
++ struct brcmf_bus *bus_if = dev_get_drvdata(dev);
++ struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
++ struct brcmf_sdio *bus = sdiodev->bus;
++ int err = 0;
++ u8 saveclk;
++
++ brcmf_dbg(TRACE, "Enter: dev=%s\n", dev_name(dev));
++
++ if (!bus_if->drvr)
++ return;
++
++ /* try to download image and nvram to the dongle */
++ bus->alp_only = true;
++ err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
++ if (err)
++ goto fail;
++ bus->alp_only = false;
++
++ /* Start the watchdog timer */
++ bus->sdcnt.tickcnt = 0;
++ brcmf_sdio_wd_timer(bus, BRCMF_WD_POLL_MS);
++
++ sdio_claim_host(sdiodev->func[1]);
++
++ /* Make sure backplane clock is on, needed to generate F2 interrupt */
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
++ if (bus->clkstate != CLK_AVAIL)
++ goto release;
++
++ /* Force clocks on backplane to be sure F2 interrupt propagates */
++ saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
++ if (!err) {
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ (saveclk | SBSDIO_FORCE_HT), &err);
++ }
++ if (err) {
++ brcmf_err("Failed to force clock for F2: err %d\n", err);
++ goto release;
++ }
++
++ /* Enable function 2 (frame transfers) */
++ w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
++ offsetof(struct sdpcmd_regs, tosbmailboxdata));
++ err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
++
++
++ brcmf_dbg(INFO, "enable F2: err=%d\n", err);
++
++ /* If F2 successfully enabled, set core and enable interrupts */
++ if (!err) {
++ /* Set up the interrupt mask and enable interrupts */
++ bus->hostintmask = HOSTINTMASK;
++ w_sdreg32(bus, bus->hostintmask,
++ offsetof(struct sdpcmd_regs, hostintmask));
++
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
++ } else {
++ /* Disable F2 again */
++ sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
++ goto release;
++ }
++
++ if (brcmf_chip_sr_capable(bus->ci)) {
++ brcmf_sdio_sr_init(bus);
++ } else {
++ /* Restore previous clock setting */
++ brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
++ saveclk, &err);
++ }
++
++ if (err == 0) {
++ err = brcmf_sdiod_intr_register(sdiodev);
++ if (err != 0)
++ brcmf_err("intr register failed:%d\n", err);
++ }
++
++ /* If we didn't come up, turn off backplane clock */
++ if (err != 0)
++ brcmf_sdio_clkctl(bus, CLK_NONE, false);
++
++ sdio_release_host(sdiodev->func[1]);
++
++ err = brcmf_bus_start(dev);
++ if (err != 0) {
++ brcmf_err("dongle is not responding\n");
++ goto fail;
++ }
++ return;
++
++release:
++ sdio_release_host(sdiodev->func[1]);
++fail:
++ brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
++ device_release_driver(dev);
++}
++
++struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
++{
++ int ret;
++ struct brcmf_sdio *bus;
++ struct workqueue_struct *wq;
++
++ brcmf_dbg(TRACE, "Enter\n");
++
++ /* Allocate private bus interface state */
++ bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
++ if (!bus)
++ goto fail;
++
++ bus->sdiodev = sdiodev;
++ sdiodev->bus = bus;
++ skb_queue_head_init(&bus->glom);
++ bus->txbound = BRCMF_TXBOUND;
++ bus->rxbound = BRCMF_RXBOUND;
++ bus->txminmax = BRCMF_TXMINMAX;
++ bus->tx_seq = SDPCM_SEQ_WRAP - 1;
++
++ /* platform specific configuration:
++ * alignments must be at least 4 bytes for ADMA
++ */
++ bus->head_align = ALIGNMENT;
++ bus->sgentry_align = ALIGNMENT;
++ if (sdiodev->pdata) {
++ if (sdiodev->pdata->sd_head_align > ALIGNMENT)
++ bus->head_align = sdiodev->pdata->sd_head_align;
++ if (sdiodev->pdata->sd_sgentry_align > ALIGNMENT)
++ bus->sgentry_align = sdiodev->pdata->sd_sgentry_align;
++ }
++
++ /* single-threaded workqueue */
++ wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
++ dev_name(&sdiodev->func[1]->dev));
++ if (!wq) {
++ brcmf_err("insufficient memory to create txworkqueue\n");
++ goto fail;
++ }
++ brcmf_sdiod_freezer_count(sdiodev);
++ INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
++ bus->brcmf_wq = wq;
++
++ /* attempt to attach to the dongle */
++ if (!(brcmf_sdio_probe_attach(bus))) {
++ brcmf_err("brcmf_sdio_probe_attach failed\n");
++ goto fail;
++ }
++
++ spin_lock_init(&bus->rxctl_lock);
++ spin_lock_init(&bus->txq_lock);
++ init_waitqueue_head(&bus->ctrl_wait);
++ init_waitqueue_head(&bus->dcmd_resp_wait);
++
++ /* Set up the watchdog timer */
++ init_timer(&bus->timer);
++ bus->timer.data = (unsigned long)bus;
++ bus->timer.function = brcmf_sdio_watchdog;
++
++ /* Initialize watchdog thread */
++ init_completion(&bus->watchdog_wait);
++ bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
++ bus, "brcmf_wdog/%s",
++ dev_name(&sdiodev->func[1]->dev));
++ if (IS_ERR(bus->watchdog_tsk)) {
++ pr_warn("brcmf_watchdog thread failed to start\n");
++ bus->watchdog_tsk = NULL;
++ }
++ /* Initialize DPC thread */
++ bus->dpc_triggered = false;
++ bus->dpc_running = false;
++
++ /* Assign bus interface call back */
++ bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
++ bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
++ bus->sdiodev->bus_if->chip = bus->ci->chip;
++ bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
++
++ /* default sdio bus header length for tx packet */
++ bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
++
++ /* Attach to the common layer, reserve hdr space */
++ ret = brcmf_attach(bus->sdiodev->dev);
++ if (ret != 0) {
++ brcmf_err("brcmf_attach failed\n");
++ goto fail;
++ }
++
++ /* Query the F2 block size, set roundup accordingly */
++ bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
++ bus->roundup = min(max_roundup, bus->blocksize);
++
++ /* Allocate buffers */
++ if (bus->sdiodev->bus_if->maxctl) {
++ bus->sdiodev->bus_if->maxctl += bus->roundup;
++ bus->rxblen =
++ roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
++ ALIGNMENT) + bus->head_align;
++ bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
++ if (!(bus->rxbuf)) {
++ brcmf_err("rxbuf allocation failed\n");
++ goto fail;
++ }
++ }
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++
++ /* Disable F2 to clear any intermediate frame state on the dongle */
++ sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
++
++ bus->rxflow = false;
++
++ /* Done with backplane-dependent accesses, can drop clock... */
++ brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
++
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ /* ...and initialize clock/power states */
++ bus->clkstate = CLK_SDONLY;
++ bus->idletime = BRCMF_IDLE_INTERVAL;
++ bus->idleclock = BRCMF_IDLE_ACTIVE;
++
++ /* SR state */
++ bus->sr_enabled = false;
++
++ brcmf_sdio_debugfs_create(bus);
++ brcmf_dbg(INFO, "completed!!\n");
++
++ ret = brcmf_sdio_get_fwnames(bus->ci, sdiodev);
++ if (ret)
++ goto fail;
++
++ ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
++ sdiodev->fw_name, sdiodev->nvram_name,
++ brcmf_sdio_firmware_callback);
++ if (ret != 0) {
++ brcmf_err("async firmware request failed: %d\n", ret);
++ goto fail;
++ }
++
++ return bus;
++
++fail:
++ brcmf_sdio_remove(bus);
++ return NULL;
++}
++
++/* Detach and free everything */
++void brcmf_sdio_remove(struct brcmf_sdio *bus)
++{
++ brcmf_dbg(TRACE, "Enter\n");
++
++ if (bus) {
++ /* De-register interrupt handler */
++ brcmf_sdiod_intr_unregister(bus->sdiodev);
++
++ brcmf_detach(bus->sdiodev->dev);
++
++ cancel_work_sync(&bus->datawork);
++ if (bus->brcmf_wq)
++ destroy_workqueue(bus->brcmf_wq);
++
++ if (bus->ci) {
++ if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
++ sdio_claim_host(bus->sdiodev->func[1]);
++ brcmf_sdio_wd_timer(bus, 0);
++ brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
++ /* Leave the device in state where it is
++ * 'passive'. This is done by resetting all
++ * necessary cores.
++ */
++ msleep(20);
++ brcmf_chip_set_passive(bus->ci);
++ brcmf_sdio_clkctl(bus, CLK_NONE, false);
++ sdio_release_host(bus->sdiodev->func[1]);
++ }
++ brcmf_chip_detach(bus->ci);
++ }
++
++ kfree(bus->rxbuf);
++ kfree(bus->hdrbuf);
++ kfree(bus);
++ }
++
++ brcmf_dbg(TRACE, "Disconnected\n");
++}
++
++void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick)
++{
++ /* Totally stop the timer */
++ if (!wdtick && bus->wd_timer_valid) {
++ del_timer_sync(&bus->timer);
++ bus->wd_timer_valid = false;
++ bus->save_ms = wdtick;
++ return;
++ }
++
++ /* don't start the wd until fw is loaded */
++ if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
++ return;
++
++ if (wdtick) {
++ if (bus->save_ms != BRCMF_WD_POLL_MS) {
++ if (bus->wd_timer_valid)
++ /* Stop timer and restart at new value */
++ del_timer_sync(&bus->timer);
++
++ /* Create timer again when watchdog period is
++ dynamically changed or in the first instance
++ */
++ bus->timer.expires =
++ jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS);
++ add_timer(&bus->timer);
++
++ } else {
++ /* Re arm the timer, at last watchdog period */
++ mod_timer(&bus->timer,
++ jiffies + msecs_to_jiffies(BRCMF_WD_POLL_MS));
++ }
++
++ bus->wd_timer_valid = true;
++ bus->save_ms = wdtick;
++ }
++}
++
++int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
++{
++ int ret;
++
++ sdio_claim_host(bus->sdiodev->func[1]);
++ ret = brcmf_sdio_bus_sleep(bus, sleep, false);
++ sdio_release_host(bus->sdiodev->func[1]);
++
++ return ret;
++}
++
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.c 2016-06-19 22:11:55.289141057 +0200
+@@ -73,50 +73,6 @@
+ #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
+ #define D11_BCMA_IOCTL_PHYRESET 0x0008
+
+-#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
+-/* SDIO Pad drive strength to select value mappings */
+-struct sdiod_drive_str {
+- u8 strength; /* Pad Drive Strength in mA */
+- u8 sel; /* Chip-specific select value */
+-};
+-/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
+-static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
+- {32, 0x6},
+- {26, 0x7},
+- {22, 0x4},
+- {16, 0x5},
+- {12, 0x2},
+- {8, 0x3},
+- {4, 0x0},
+- {0, 0x1}
+-};
+-
+-/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
+-static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
+- {6, 0x7},
+- {5, 0x6},
+- {4, 0x5},
+- {3, 0x4},
+- {2, 0x2},
+- {1, 0x1},
+- {0, 0x0}
+-};
+-
+-/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
+-static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
+- {3, 0x3},
+- {2, 0x2},
+- {1, 0x1},
+- {0, 0x0} };
+-
+-/* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
+-static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
+- {16, 0x7},
+- {12, 0x5},
+- {8, 0x3},
+- {4, 0x1}
+-};
+-
+ u8
+ brcmf_sdio_chip_getinfidx(struct brcmf_chip *ci, u16 coreid)
+ {
+@@ -662,51 +618,6 @@
+ return brcmf_sdio_chip_cichk(ci);
+ }
+
+-static int
+-brcmf_sdio_chip_buscoreprep(struct brcmf_sdio_dev *sdiodev)
+-{
+- int err = 0;
+- u8 clkval, clkset;
+-
+- /* Try forcing SDIO core to do ALPAvail request only */
+- clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
+- brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
+- if (err) {
+- brcmf_err("error writing for HT off\n");
+- return err;
+- }
+-
+- /* If register supported, wait for ALPAvail and then force ALP */
+- /* This may take up to 15 milliseconds */
+- clkval = brcmf_sdiod_regrb(sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, NULL);
+-
+- if ((clkval & ~SBSDIO_AVBITS) != clkset) {
+- brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
+- clkset, clkval);
+- return -EACCES;
+- }
+-
+- SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
+- SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
+- !SBSDIO_ALPAV(clkval)),
+- PMU_MAX_TRANSITION_DLY);
+- if (!SBSDIO_ALPAV(clkval)) {
+- brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
+- clkval);
+- return -EBUSY;
+- }
+-
+- clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
+- brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
+- udelay(65);
+-
+- /* Also, disable the extra SDIO pull-ups */
+- brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
+-
+- return 0;
+-}
+-
+ static void
+ brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
+ struct brcmf_chip *ci)
+@@ -755,7 +666,7 @@
+ if (!ci)
+ return -ENOMEM;
+
+- ret = brcmf_sdio_chip_buscoreprep(sdiodev);
++ ret = brcmf_sdio_buscoreprep(sdiodev);
+ if (ret != 0)
+ goto err;
+
+@@ -787,87 +698,6 @@
+ *ci_ptr = NULL;
+ }
+
+-static char *brcmf_sdio_chip_name(uint chipid, char *buf, uint len)
+-{
+- const char *fmt;
+-
+- fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
+- snprintf(buf, len, fmt, chipid);
+- return buf;
+-}
+-
+-void
+-brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
+- struct brcmf_chip *ci, u32 drivestrength)
+-{
+- const struct sdiod_drive_str *str_tab = NULL;
+- u32 str_mask;
+- u32 str_shift;
+- char chn[8];
+- u32 base = ci->c_inf[0].base;
+- u32 i;
+- u32 drivestrength_sel = 0;
+- u32 cc_data_temp;
+- u32 addr;
+-
+- if (!(ci->c_inf[0].caps & CC_CAP_PMU))
+- return;
+-
+- switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
+- case SDIOD_DRVSTR_KEY(BCM4330_CHIP_ID, 12):
+- str_tab = sdiod_drvstr_tab1_1v8;
+- str_mask = 0x00003800;
+- str_shift = 11;
+- break;
+- case SDIOD_DRVSTR_KEY(BCM4334_CHIP_ID, 17):
+- str_tab = sdiod_drvstr_tab6_1v8;
+- str_mask = 0x00001800;
+- str_shift = 11;
+- break;
+- case SDIOD_DRVSTR_KEY(BCM43143_CHIP_ID, 17):
+- /* note: 43143 does not support tristate */
+- i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
+- if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
+- str_tab = sdiod_drvstr_tab2_3v3;
+- str_mask = 0x00000007;
+- str_shift = 0;
+- } else
+- brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
+- brcmf_sdio_chip_name(ci->chip, chn, 8),
+- drivestrength);
+- break;
+- case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
+- str_tab = sdiod_drive_strength_tab5_1v8;
+- str_mask = 0x00003800;
+- str_shift = 11;
+- break;
+- default:
+- brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
+- brcmf_sdio_chip_name(ci->chip, chn, 8),
+- ci->chiprev, ci->pmurev);
+- break;
+- }
+-
+- if (str_tab != NULL) {
+- for (i = 0; str_tab[i].strength != 0; i++) {
+- if (drivestrength >= str_tab[i].strength) {
+- drivestrength_sel = str_tab[i].sel;
+- break;
+- }
+- }
+- addr = CORE_CC_REG(base, chipcontrol_addr);
+- brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
+- cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
+- cc_data_temp &= ~str_mask;
+- drivestrength_sel <<= str_shift;
+- cc_data_temp |= drivestrength_sel;
+- brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
+-
+- brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
+- str_tab[i].strength, drivestrength, cc_data_temp);
+- }
+-}
+-
+ static void
+ brcmf_sdio_chip_cm3_enterdl(struct brcmf_sdio_dev *sdiodev,
+ struct brcmf_chip *ci)
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio_chip.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,231 +0,0 @@
+-/*
+- * Copyright (c) 2011 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#ifndef _BRCMFMAC_SDIO_CHIP_H_
+-#define _BRCMFMAC_SDIO_CHIP_H_
+-
+-/*
+- * Core reg address translation.
+- * Both macro's returns a 32 bits byte address on the backplane bus.
+- */
+-#define CORE_CC_REG(base, field) \
+- (base + offsetof(struct chipcregs, field))
+-#define CORE_BUS_REG(base, field) \
+- (base + offsetof(struct sdpcmd_regs, field))
+-#define CORE_SB(base, field) \
+- (base + SBCONFIGOFF + offsetof(struct sbconfig, field))
+-
+-/* SDIO function 1 register CHIPCLKCSR */
+-/* Force ALP request to backplane */
+-#define SBSDIO_FORCE_ALP 0x01
+-/* Force HT request to backplane */
+-#define SBSDIO_FORCE_HT 0x02
+-/* Force ILP request to backplane */
+-#define SBSDIO_FORCE_ILP 0x04
+-/* Make ALP ready (power up xtal) */
+-#define SBSDIO_ALP_AVAIL_REQ 0x08
+-/* Make HT ready (power up PLL) */
+-#define SBSDIO_HT_AVAIL_REQ 0x10
+-/* Squelch clock requests from HW */
+-#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
+-/* Status: ALP is ready */
+-#define SBSDIO_ALP_AVAIL 0x40
+-/* Status: HT is ready */
+-#define SBSDIO_HT_AVAIL 0x80
+-#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
+-#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
+-#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
+-#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
+-#define SBSDIO_CLKAV(regval, alponly) \
+- (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
+-
+-#define BRCMF_MAX_CORENUM 6
+-
+-struct brcmf_core {
+- u16 id;
+- u16 rev;
+- u32 base;
+- u32 wrapbase;
+- u32 caps;
+- u32 cib;
+-};
+-
+-struct brcmf_chip {
+- u32 chip;
+- u32 chiprev;
+- /* core info */
+- /* always put chipcommon core at 0, bus core at 1 */
+- struct brcmf_core c_inf[BRCMF_MAX_CORENUM];
+- u32 pmurev;
+- u32 pmucaps;
+- u32 ramsize;
+- u32 rambase;
+- u32 rst_vec; /* reset vertor for ARM CR4 core */
+-
+- bool (*iscoreup)(struct brcmf_sdio_dev *sdiodev, struct brcmf_chip *ci,
+- u16 coreid);
+- u32 (*corerev)(struct brcmf_sdio_dev *sdiodev, struct brcmf_chip *ci,
+- u16 coreid);
+- void (*coredisable)(struct brcmf_sdio_dev *sdiodev,
+- struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
+- u32 in_resetbits);
+- void (*resetcore)(struct brcmf_sdio_dev *sdiodev,
+- struct brcmf_chip *ci, u16 coreid, u32 pre_resetbits,
+- u32 in_resetbits, u32 post_resetbits);
+-};
+-
+-struct sbconfig {
+- u32 PAD[2];
+- u32 sbipsflag; /* initiator port ocp slave flag */
+- u32 PAD[3];
+- u32 sbtpsflag; /* target port ocp slave flag */
+- u32 PAD[11];
+- u32 sbtmerrloga; /* (sonics >= 2.3) */
+- u32 PAD;
+- u32 sbtmerrlog; /* (sonics >= 2.3) */
+- u32 PAD[3];
+- u32 sbadmatch3; /* address match3 */
+- u32 PAD;
+- u32 sbadmatch2; /* address match2 */
+- u32 PAD;
+- u32 sbadmatch1; /* address match1 */
+- u32 PAD[7];
+- u32 sbimstate; /* initiator agent state */
+- u32 sbintvec; /* interrupt mask */
+- u32 sbtmstatelow; /* target state */
+- u32 sbtmstatehigh; /* target state */
+- u32 sbbwa0; /* bandwidth allocation table0 */
+- u32 PAD;
+- u32 sbimconfiglow; /* initiator configuration */
+- u32 sbimconfighigh; /* initiator configuration */
+- u32 sbadmatch0; /* address match0 */
+- u32 PAD;
+- u32 sbtmconfiglow; /* target configuration */
+- u32 sbtmconfighigh; /* target configuration */
+- u32 sbbconfig; /* broadcast configuration */
+- u32 PAD;
+- u32 sbbstate; /* broadcast state */
+- u32 PAD[3];
+- u32 sbactcnfg; /* activate configuration */
+- u32 PAD[3];
+- u32 sbflagst; /* current sbflags */
+- u32 PAD[3];
+- u32 sbidlow; /* identification */
+- u32 sbidhigh; /* identification */
+-};
+-
+-/* sdio core registers */
+-struct sdpcmd_regs {
+- u32 corecontrol; /* 0x00, rev8 */
+- u32 corestatus; /* rev8 */
+- u32 PAD[1];
+- u32 biststatus; /* rev8 */
+-
+- /* PCMCIA access */
+- u16 pcmciamesportaladdr; /* 0x010, rev8 */
+- u16 PAD[1];
+- u16 pcmciamesportalmask; /* rev8 */
+- u16 PAD[1];
+- u16 pcmciawrframebc; /* rev8 */
+- u16 PAD[1];
+- u16 pcmciaunderflowtimer; /* rev8 */
+- u16 PAD[1];
+-
+- /* interrupt */
+- u32 intstatus; /* 0x020, rev8 */
+- u32 hostintmask; /* rev8 */
+- u32 intmask; /* rev8 */
+- u32 sbintstatus; /* rev8 */
+- u32 sbintmask; /* rev8 */
+- u32 funcintmask; /* rev4 */
+- u32 PAD[2];
+- u32 tosbmailbox; /* 0x040, rev8 */
+- u32 tohostmailbox; /* rev8 */
+- u32 tosbmailboxdata; /* rev8 */
+- u32 tohostmailboxdata; /* rev8 */
+-
+- /* synchronized access to registers in SDIO clock domain */
+- u32 sdioaccess; /* 0x050, rev8 */
+- u32 PAD[3];
+-
+- /* PCMCIA frame control */
+- u8 pcmciaframectrl; /* 0x060, rev8 */
+- u8 PAD[3];
+- u8 pcmciawatermark; /* rev8 */
+- u8 PAD[155];
+-
+- /* interrupt batching control */
+- u32 intrcvlazy; /* 0x100, rev8 */
+- u32 PAD[3];
+-
+- /* counters */
+- u32 cmd52rd; /* 0x110, rev8 */
+- u32 cmd52wr; /* rev8 */
+- u32 cmd53rd; /* rev8 */
+- u32 cmd53wr; /* rev8 */
+- u32 abort; /* rev8 */
+- u32 datacrcerror; /* rev8 */
+- u32 rdoutofsync; /* rev8 */
+- u32 wroutofsync; /* rev8 */
+- u32 writebusy; /* rev8 */
+- u32 readwait; /* rev8 */
+- u32 readterm; /* rev8 */
+- u32 writeterm; /* rev8 */
+- u32 PAD[40];
+- u32 clockctlstatus; /* rev8 */
+- u32 PAD[7];
+-
+- u32 PAD[128]; /* DMA engines */
+-
+- /* SDIO/PCMCIA CIS region */
+- char cis[512]; /* 0x400-0x5ff, rev6 */
+-
+- /* PCMCIA function control registers */
+- char pcmciafcr[256]; /* 0x600-6ff, rev6 */
+- u16 PAD[55];
+-
+- /* PCMCIA backplane access */
+- u16 backplanecsr; /* 0x76E, rev6 */
+- u16 backplaneaddr0; /* rev6 */
+- u16 backplaneaddr1; /* rev6 */
+- u16 backplaneaddr2; /* rev6 */
+- u16 backplaneaddr3; /* rev6 */
+- u16 backplanedata0; /* rev6 */
+- u16 backplanedata1; /* rev6 */
+- u16 backplanedata2; /* rev6 */
+- u16 backplanedata3; /* rev6 */
+- u16 PAD[31];
+-
+- /* sprom "size" & "blank" info */
+- u16 spromstatus; /* 0x7BE, rev2 */
+- u32 PAD[464];
+-
+- u16 PAD[0x80];
+-};
+-
+-int brcmf_sdio_chip_attach(struct brcmf_sdio_dev *sdiodev,
+- struct brcmf_chip **ci_ptr);
+-void brcmf_sdio_chip_detach(struct brcmf_chip **ci_ptr);
+-void brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
+- struct brcmf_chip *ci,
+- u32 drivestrength);
+-u8 brcmf_sdio_chip_getinfidx(struct brcmf_chip *ci, u16 coreid);
+-void brcmf_sdio_chip_enter_download(struct brcmf_sdio_dev *sdiodev,
+- struct brcmf_chip *ci);
+-bool brcmf_sdio_chip_exit_download(struct brcmf_sdio_dev *sdiodev,
+- struct brcmf_chip *ci, u32 rstvec);
+-
+-#endif /* _BRCMFMAC_SDIO_CHIP_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio.h 2016-06-19 22:11:55.289141057 +0200
+@@ -0,0 +1,377 @@
++/*
++ * Copyright (c) 2010 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _BRCM_SDH_H_
++#define _BRCM_SDH_H_
++
++#include <linux/skbuff.h>
++#include <linux/firmware.h>
++#include "firmware.h"
++
++#define SDIO_FUNC_0 0
++#define SDIO_FUNC_1 1
++#define SDIO_FUNC_2 2
++
++#define SDIOD_FBR_SIZE 0x100
++
++/* io_en */
++#define SDIO_FUNC_ENABLE_1 0x02
++#define SDIO_FUNC_ENABLE_2 0x04
++
++/* io_rdys */
++#define SDIO_FUNC_READY_1 0x02
++#define SDIO_FUNC_READY_2 0x04
++
++/* intr_status */
++#define INTR_STATUS_FUNC1 0x2
++#define INTR_STATUS_FUNC2 0x4
++
++/* Maximum number of I/O funcs */
++#define SDIOD_MAX_IOFUNCS 7
++
++/* mask of register map */
++#define REG_F0_REG_MASK 0x7FF
++#define REG_F1_MISC_MASK 0x1FFFF
++
++/* as of sdiod rev 0, supports 3 functions */
++#define SBSDIO_NUM_FUNCTION 3
++
++/* function 0 vendor specific CCCR registers */
++#define SDIO_CCCR_BRCM_CARDCAP 0xf0
++#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
++#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
++#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
++#define SDIO_CCCR_BRCM_CARDCTRL 0xf1
++#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
++#define SDIO_CCCR_BRCM_SEPINT 0xf2
++
++#define SDIO_SEPINT_MASK 0x01
++#define SDIO_SEPINT_OE 0x02
++#define SDIO_SEPINT_ACT_HI 0x04
++
++/* function 1 miscellaneous registers */
++
++/* sprom command and status */
++#define SBSDIO_SPROM_CS 0x10000
++/* sprom info register */
++#define SBSDIO_SPROM_INFO 0x10001
++/* sprom indirect access data byte 0 */
++#define SBSDIO_SPROM_DATA_LOW 0x10002
++/* sprom indirect access data byte 1 */
++#define SBSDIO_SPROM_DATA_HIGH 0x10003
++/* sprom indirect access addr byte 0 */
++#define SBSDIO_SPROM_ADDR_LOW 0x10004
++/* gpio select */
++#define SBSDIO_GPIO_SELECT 0x10005
++/* gpio output */
++#define SBSDIO_GPIO_OUT 0x10006
++/* gpio enable */
++#define SBSDIO_GPIO_EN 0x10007
++/* rev < 7, watermark for sdio device */
++#define SBSDIO_WATERMARK 0x10008
++/* control busy signal generation */
++#define SBSDIO_DEVICE_CTL 0x10009
++
++/* SB Address Window Low (b15) */
++#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
++/* SB Address Window Mid (b23:b16) */
++#define SBSDIO_FUNC1_SBADDRMID 0x1000B
++/* SB Address Window High (b31:b24) */
++#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
++/* Frame Control (frame term/abort) */
++#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
++/* ChipClockCSR (ALP/HT ctl/status) */
++#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
++/* SdioPullUp (on cmd, d0-d2) */
++#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
++/* Write Frame Byte Count Low */
++#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
++/* Write Frame Byte Count High */
++#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
++/* Read Frame Byte Count Low */
++#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
++/* Read Frame Byte Count High */
++#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
++/* MesBusyCtl (rev 11) */
++#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
++/* Sdio Core Rev 12 */
++#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
++#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
++#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
++#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
++#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
++#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
++#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
++#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
++#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
++#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
++#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
++
++#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
++#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
++
++/* function 1 OCP space */
++
++/* sb offset addr is <= 15 bits, 32k */
++#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
++#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
++/* with b15, maps to 32-bit SB access */
++#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
++
++/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
++
++#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
++#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
++#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
++/* Address bits from SBADDR regs */
++#define SBSDIO_SBWINDOW_MASK 0xffff8000
++
++#define SDIOH_READ 0 /* Read request */
++#define SDIOH_WRITE 1 /* Write request */
++
++#define SDIOH_DATA_FIX 0 /* Fixed addressing */
++#define SDIOH_DATA_INC 1 /* Incremental addressing */
++
++/* internal return code */
++#define SUCCESS 0
++#define ERROR 1
++
++/* Packet alignment for most efficient SDIO (can change based on platform) */
++#define BRCMF_SDALIGN (1 << 6)
++
++/* watchdog polling interval in ms */
++#define BRCMF_WD_POLL_MS 10
++
++/**
++ * enum brcmf_sdiod_state - the state of the bus.
++ *
++ * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC.
++ * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled.
++ * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible.
++ */
++enum brcmf_sdiod_state {
++ BRCMF_SDIOD_DOWN,
++ BRCMF_SDIOD_DATA,
++ BRCMF_SDIOD_NOMEDIUM
++};
++
++struct brcmf_sdreg {
++ int func;
++ int offset;
++ int value;
++};
++
++struct brcmf_sdio;
++struct brcmf_sdiod_freezer;
++
++struct brcmf_sdio_dev {
++ struct sdio_func *func[SDIO_MAX_FUNCS];
++ u8 num_funcs; /* Supported funcs on client */
++ u32 sbwad; /* Save backplane window address */
++ struct brcmf_sdio *bus;
++ struct device *dev;
++ struct brcmf_bus *bus_if;
++ struct brcmfmac_sdio_platform_data *pdata;
++ bool oob_irq_requested;
++ bool irq_en; /* irq enable flags */
++ spinlock_t irq_en_lock;
++ bool irq_wake; /* irq wake enable flags */
++ bool sg_support;
++ uint max_request_size;
++ ushort max_segment_count;
++ uint max_segment_size;
++ uint txglomsz;
++ struct sg_table sgtable;
++ char fw_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
++ char nvram_name[BRCMF_FW_PATH_LEN + BRCMF_FW_NAME_LEN];
++ bool wowl_enabled;
++ enum brcmf_sdiod_state state;
++ struct brcmf_sdiod_freezer *freezer;
++};
++
++/* sdio core registers */
++struct sdpcmd_regs {
++ u32 corecontrol; /* 0x00, rev8 */
++ u32 corestatus; /* rev8 */
++ u32 PAD[1];
++ u32 biststatus; /* rev8 */
++
++ /* PCMCIA access */
++ u16 pcmciamesportaladdr; /* 0x010, rev8 */
++ u16 PAD[1];
++ u16 pcmciamesportalmask; /* rev8 */
++ u16 PAD[1];
++ u16 pcmciawrframebc; /* rev8 */
++ u16 PAD[1];
++ u16 pcmciaunderflowtimer; /* rev8 */
++ u16 PAD[1];
++
++ /* interrupt */
++ u32 intstatus; /* 0x020, rev8 */
++ u32 hostintmask; /* rev8 */
++ u32 intmask; /* rev8 */
++ u32 sbintstatus; /* rev8 */
++ u32 sbintmask; /* rev8 */
++ u32 funcintmask; /* rev4 */
++ u32 PAD[2];
++ u32 tosbmailbox; /* 0x040, rev8 */
++ u32 tohostmailbox; /* rev8 */
++ u32 tosbmailboxdata; /* rev8 */
++ u32 tohostmailboxdata; /* rev8 */
++
++ /* synchronized access to registers in SDIO clock domain */
++ u32 sdioaccess; /* 0x050, rev8 */
++ u32 PAD[3];
++
++ /* PCMCIA frame control */
++ u8 pcmciaframectrl; /* 0x060, rev8 */
++ u8 PAD[3];
++ u8 pcmciawatermark; /* rev8 */
++ u8 PAD[155];
++
++ /* interrupt batching control */
++ u32 intrcvlazy; /* 0x100, rev8 */
++ u32 PAD[3];
++
++ /* counters */
++ u32 cmd52rd; /* 0x110, rev8 */
++ u32 cmd52wr; /* rev8 */
++ u32 cmd53rd; /* rev8 */
++ u32 cmd53wr; /* rev8 */
++ u32 abort; /* rev8 */
++ u32 datacrcerror; /* rev8 */
++ u32 rdoutofsync; /* rev8 */
++ u32 wroutofsync; /* rev8 */
++ u32 writebusy; /* rev8 */
++ u32 readwait; /* rev8 */
++ u32 readterm; /* rev8 */
++ u32 writeterm; /* rev8 */
++ u32 PAD[40];
++ u32 clockctlstatus; /* rev8 */
++ u32 PAD[7];
++
++ u32 PAD[128]; /* DMA engines */
++
++ /* SDIO/PCMCIA CIS region */
++ char cis[512]; /* 0x400-0x5ff, rev6 */
++
++ /* PCMCIA function control registers */
++ char pcmciafcr[256]; /* 0x600-6ff, rev6 */
++ u16 PAD[55];
++
++ /* PCMCIA backplane access */
++ u16 backplanecsr; /* 0x76E, rev6 */
++ u16 backplaneaddr0; /* rev6 */
++ u16 backplaneaddr1; /* rev6 */
++ u16 backplaneaddr2; /* rev6 */
++ u16 backplaneaddr3; /* rev6 */
++ u16 backplanedata0; /* rev6 */
++ u16 backplanedata1; /* rev6 */
++ u16 backplanedata2; /* rev6 */
++ u16 backplanedata3; /* rev6 */
++ u16 PAD[31];
++
++ /* sprom "size" & "blank" info */
++ u16 spromstatus; /* 0x7BE, rev2 */
++ u32 PAD[464];
++
++ u16 PAD[0x80];
++};
++
++/* Register/deregister interrupt handler. */
++int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
++int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
++
++/* sdio device register access interface */
++u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
++u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
++void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
++ int *ret);
++void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
++ int *ret);
++
++/* Buffer transfer to/from device (client) core via cmd53.
++ * fn: function number
++ * flags: backplane width, address increment, sync/async
++ * buf: pointer to memory data buffer
++ * nbytes: number of bytes to transfer to/from buf
++ * pkt: pointer to packet associated with buf (if any)
++ * complete: callback function for command completion (async only)
++ * handle: handle for completion callback (first arg in callback)
++ * Returns 0 or error code.
++ * NOTE: Async operation is not currently supported.
++ */
++int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
++ struct sk_buff_head *pktq);
++int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
++
++int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
++int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
++int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
++ struct sk_buff_head *pktq, uint totlen);
++
++/* Flags bits */
++
++/* Four-byte target (backplane) width (vs. two-byte) */
++#define SDIO_REQ_4BYTE 0x1
++/* Fixed address (FIFO) (vs. incrementing address) */
++#define SDIO_REQ_FIXED 0x2
++
++/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
++ * rw: read or write (0/1)
++ * addr: direct SDIO address
++ * buf: pointer to memory data buffer
++ * nbytes: number of bytes to transfer to/from buf
++ * Returns 0 or error code.
++ */
++int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
++ u8 *data, uint size);
++
++/* Issue an abort to the specified function */
++int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
++void brcmf_sdiod_change_state(struct brcmf_sdio_dev *sdiodev,
++ enum brcmf_sdiod_state state);
++#ifdef CONFIG_PM_SLEEP
++bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev);
++void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev);
++void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev);
++void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev);
++#else
++static inline bool brcmf_sdiod_freezing(struct brcmf_sdio_dev *sdiodev)
++{
++ return false;
++}
++static inline void brcmf_sdiod_try_freeze(struct brcmf_sdio_dev *sdiodev)
++{
++}
++static inline void brcmf_sdiod_freezer_count(struct brcmf_sdio_dev *sdiodev)
++{
++}
++static inline void brcmf_sdiod_freezer_uncount(struct brcmf_sdio_dev *sdiodev)
++{
++}
++#endif /* CONFIG_PM_SLEEP */
++
++struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
++void brcmf_sdio_remove(struct brcmf_sdio *bus);
++void brcmf_sdio_isr(struct brcmf_sdio *bus);
++
++void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick);
++void brcmf_sdio_wowl_config(struct device *dev, bool enabled);
++int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep);
++void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus);
++
++#endif /* _BRCM_SDH_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/sdio_host.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,243 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#ifndef _BRCM_SDH_H_
+-#define _BRCM_SDH_H_
+-
+-#include <linux/skbuff.h>
+-
+-#define SDIO_FUNC_0 0
+-#define SDIO_FUNC_1 1
+-#define SDIO_FUNC_2 2
+-
+-#define SDIOD_FBR_SIZE 0x100
+-
+-/* io_en */
+-#define SDIO_FUNC_ENABLE_1 0x02
+-#define SDIO_FUNC_ENABLE_2 0x04
+-
+-/* io_rdys */
+-#define SDIO_FUNC_READY_1 0x02
+-#define SDIO_FUNC_READY_2 0x04
+-
+-/* intr_status */
+-#define INTR_STATUS_FUNC1 0x2
+-#define INTR_STATUS_FUNC2 0x4
+-
+-/* Maximum number of I/O funcs */
+-#define SDIOD_MAX_IOFUNCS 7
+-
+-/* mask of register map */
+-#define REG_F0_REG_MASK 0x7FF
+-#define REG_F1_MISC_MASK 0x1FFFF
+-
+-/* as of sdiod rev 0, supports 3 functions */
+-#define SBSDIO_NUM_FUNCTION 3
+-
+-/* function 0 vendor specific CCCR registers */
+-#define SDIO_CCCR_BRCM_CARDCAP 0xf0
+-#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02
+-#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04
+-#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08
+-#define SDIO_CCCR_BRCM_CARDCTRL 0xf1
+-#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02
+-#define SDIO_CCCR_BRCM_SEPINT 0xf2
+-
+-#define SDIO_SEPINT_MASK 0x01
+-#define SDIO_SEPINT_OE 0x02
+-#define SDIO_SEPINT_ACT_HI 0x04
+-
+-/* function 1 miscellaneous registers */
+-
+-/* sprom command and status */
+-#define SBSDIO_SPROM_CS 0x10000
+-/* sprom info register */
+-#define SBSDIO_SPROM_INFO 0x10001
+-/* sprom indirect access data byte 0 */
+-#define SBSDIO_SPROM_DATA_LOW 0x10002
+-/* sprom indirect access data byte 1 */
+-#define SBSDIO_SPROM_DATA_HIGH 0x10003
+-/* sprom indirect access addr byte 0 */
+-#define SBSDIO_SPROM_ADDR_LOW 0x10004
+-/* sprom indirect access addr byte 0 */
+-#define SBSDIO_SPROM_ADDR_HIGH 0x10005
+-/* xtal_pu (gpio) output */
+-#define SBSDIO_CHIP_CTRL_DATA 0x10006
+-/* xtal_pu (gpio) enable */
+-#define SBSDIO_CHIP_CTRL_EN 0x10007
+-/* rev < 7, watermark for sdio device */
+-#define SBSDIO_WATERMARK 0x10008
+-/* control busy signal generation */
+-#define SBSDIO_DEVICE_CTL 0x10009
+-
+-/* SB Address Window Low (b15) */
+-#define SBSDIO_FUNC1_SBADDRLOW 0x1000A
+-/* SB Address Window Mid (b23:b16) */
+-#define SBSDIO_FUNC1_SBADDRMID 0x1000B
+-/* SB Address Window High (b31:b24) */
+-#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C
+-/* Frame Control (frame term/abort) */
+-#define SBSDIO_FUNC1_FRAMECTRL 0x1000D
+-/* ChipClockCSR (ALP/HT ctl/status) */
+-#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E
+-/* SdioPullUp (on cmd, d0-d2) */
+-#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F
+-/* Write Frame Byte Count Low */
+-#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019
+-/* Write Frame Byte Count High */
+-#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A
+-/* Read Frame Byte Count Low */
+-#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B
+-/* Read Frame Byte Count High */
+-#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C
+-/* MesBusyCtl (rev 11) */
+-#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D
+-/* Sdio Core Rev 12 */
+-#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
+-#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1
+-#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0
+-#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2
+-#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1
+-#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
+-#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
+-#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
+-#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
+-#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
+-#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
+-
+-#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
+-#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */
+-
+-/* function 1 OCP space */
+-
+-/* sb offset addr is <= 15 bits, 32k */
+-#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF
+-#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
+-/* with b15, maps to 32-bit SB access */
+-#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000
+-
+-/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
+-
+-#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
+-#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
+-#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
+-/* Address bits from SBADDR regs */
+-#define SBSDIO_SBWINDOW_MASK 0xffff8000
+-
+-#define SDIOH_READ 0 /* Read request */
+-#define SDIOH_WRITE 1 /* Write request */
+-
+-#define SDIOH_DATA_FIX 0 /* Fixed addressing */
+-#define SDIOH_DATA_INC 1 /* Incremental addressing */
+-
+-/* internal return code */
+-#define SUCCESS 0
+-#define ERROR 1
+-
+-/* Packet alignment for most efficient SDIO (can change based on platform) */
+-#define BRCMF_SDALIGN (1 << 6)
+-
+-/* watchdog polling interval in ms */
+-#define BRCMF_WD_POLL_MS 10
+-
+-struct brcmf_sdreg {
+- int func;
+- int offset;
+- int value;
+-};
+-
+-struct brcmf_sdio;
+-
+-struct brcmf_sdio_dev {
+- struct sdio_func *func[SDIO_MAX_FUNCS];
+- u8 num_funcs; /* Supported funcs on client */
+- u32 sbwad; /* Save backplane window address */
+- struct brcmf_sdio *bus;
+- atomic_t suspend; /* suspend flag */
+- wait_queue_head_t request_word_wait;
+- wait_queue_head_t request_buffer_wait;
+- struct device *dev;
+- struct brcmf_bus *bus_if;
+- struct brcmfmac_sdio_platform_data *pdata;
+- bool oob_irq_requested;
+- bool irq_en; /* irq enable flags */
+- spinlock_t irq_en_lock;
+- bool irq_wake; /* irq wake enable flags */
+- bool sg_support;
+- uint max_request_size;
+- ushort max_segment_count;
+- uint max_segment_size;
+-};
+-
+-/* Register/deregister interrupt handler. */
+-int brcmf_sdiod_intr_register(struct brcmf_sdio_dev *sdiodev);
+-int brcmf_sdiod_intr_unregister(struct brcmf_sdio_dev *sdiodev);
+-
+-/* sdio device register access interface */
+-u8 brcmf_sdiod_regrb(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
+-u32 brcmf_sdiod_regrl(struct brcmf_sdio_dev *sdiodev, u32 addr, int *ret);
+-void brcmf_sdiod_regwb(struct brcmf_sdio_dev *sdiodev, u32 addr, u8 data,
+- int *ret);
+-void brcmf_sdiod_regwl(struct brcmf_sdio_dev *sdiodev, u32 addr, u32 data,
+- int *ret);
+-
+-/* Buffer transfer to/from device (client) core via cmd53.
+- * fn: function number
+- * flags: backplane width, address increment, sync/async
+- * buf: pointer to memory data buffer
+- * nbytes: number of bytes to transfer to/from buf
+- * pkt: pointer to packet associated with buf (if any)
+- * complete: callback function for command completion (async only)
+- * handle: handle for completion callback (first arg in callback)
+- * Returns 0 or error code.
+- * NOTE: Async operation is not currently supported.
+- */
+-int brcmf_sdiod_send_pkt(struct brcmf_sdio_dev *sdiodev,
+- struct sk_buff_head *pktq);
+-int brcmf_sdiod_send_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
+-
+-int brcmf_sdiod_recv_pkt(struct brcmf_sdio_dev *sdiodev, struct sk_buff *pkt);
+-int brcmf_sdiod_recv_buf(struct brcmf_sdio_dev *sdiodev, u8 *buf, uint nbytes);
+-int brcmf_sdiod_recv_chain(struct brcmf_sdio_dev *sdiodev,
+- struct sk_buff_head *pktq, uint totlen);
+-
+-/* Flags bits */
+-
+-/* Four-byte target (backplane) width (vs. two-byte) */
+-#define SDIO_REQ_4BYTE 0x1
+-/* Fixed address (FIFO) (vs. incrementing address) */
+-#define SDIO_REQ_FIXED 0x2
+-
+-/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
+- * rw: read or write (0/1)
+- * addr: direct SDIO address
+- * buf: pointer to memory data buffer
+- * nbytes: number of bytes to transfer to/from buf
+- * Returns 0 or error code.
+- */
+-int brcmf_sdiod_ramrw(struct brcmf_sdio_dev *sdiodev, bool write, u32 address,
+- u8 *data, uint size);
+-
+-/* Issue an abort to the specified function */
+-int brcmf_sdiod_abort(struct brcmf_sdio_dev *sdiodev, uint fn);
+-
+-struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev);
+-void brcmf_sdio_remove(struct brcmf_sdio *bus);
+-void brcmf_sdio_isr(struct brcmf_sdio *bus);
+-
+-void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, uint wdtick);
+-
+-#endif /* _BRCM_SDH_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/tracepoint.c 2016-06-19 22:11:55.289141057 +0200
+@@ -19,4 +19,19 @@
+ #ifndef __CHECKER__
+ #define CREATE_TRACE_POINTS
+ #include "tracepoint.h"
++
++void __brcmf_err(const char *func, const char *fmt, ...)
++{
++ struct va_format vaf = {
++ .fmt = fmt,
++ };
++ va_list args;
++
++ va_start(args, fmt);
++ vaf.va = &args;
++ pr_err("%s: %pV", func, &vaf);
++ trace_brcmf_err(func, &vaf);
++ va_end(args);
++}
++
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/usb.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/usb.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/usb.c 2016-06-19 22:11:55.293140794 +0200
+@@ -21,39 +21,97 @@
+ #include <linux/vmalloc.h>
+
+ #include <brcmu_utils.h>
++#include <brcm_hw_ids.h>
+ #include <brcmu_wifi.h>
+-#include <dhd_bus.h>
+-#include <dhd_dbg.h>
+-
+-#include "usb_rdl.h"
++#include "bus.h"
++#include "debug.h"
++#include "firmware.h"
+ #include "usb.h"
+
+-#define IOCTL_RESP_TIMEOUT 2000
++
++#define IOCTL_RESP_TIMEOUT 2000
+
+ #define BRCMF_USB_RESET_GETVER_SPINWAIT 100 /* in unit of ms */
+ #define BRCMF_USB_RESET_GETVER_LOOP_CNT 10
+
+ #define BRCMF_POSTBOOT_ID 0xA123 /* ID to detect if dongle
+ has boot up */
+-#define BRCMF_USB_NRXQ 50
+-#define BRCMF_USB_NTXQ 50
++#define BRCMF_USB_NRXQ 50
++#define BRCMF_USB_NTXQ 50
++
++#define BRCMF_USB_CBCTL_WRITE 0
++#define BRCMF_USB_CBCTL_READ 1
++#define BRCMF_USB_MAX_PKT_SIZE 1600
++
++#define BRCMF_USB_43143_FW_NAME "brcm/brcmfmac43143.bin"
++#define BRCMF_USB_43236_FW_NAME "brcm/brcmfmac43236b.bin"
++#define BRCMF_USB_43242_FW_NAME "brcm/brcmfmac43242a.bin"
++#define BRCMF_USB_43569_FW_NAME "brcm/brcmfmac43569.bin"
++
++#define TRX_MAGIC 0x30524448 /* "HDR0" */
++#define TRX_MAX_OFFSET 3 /* Max number of file offsets */
++#define TRX_UNCOMP_IMAGE 0x20 /* Trx holds uncompressed img */
++#define TRX_RDL_CHUNK 1500 /* size of each dl transfer */
++#define TRX_OFFSETS_DLFWLEN_IDX 0
++
++/* Control messages: bRequest values */
++#define DL_GETSTATE 0 /* returns the rdl_state_t struct */
++#define DL_CHECK_CRC 1 /* currently unused */
++#define DL_GO 2 /* execute downloaded image */
++#define DL_START 3 /* initialize dl state */
++#define DL_REBOOT 4 /* reboot the device in 2 seconds */
++#define DL_GETVER 5 /* returns the bootrom_id_t struct */
++#define DL_GO_PROTECTED 6 /* execute the downloaded code and set reset
++ * event to occur in 2 seconds. It is the
++ * responsibility of the downloaded code to
++ * clear this event
++ */
++#define DL_EXEC 7 /* jump to a supplied address */
++#define DL_RESETCFG 8 /* To support single enum on dongle
++ * - Not used by bootloader
++ */
++#define DL_DEFER_RESP_OK 9 /* Potentially defer the response to setup
++ * if resp unavailable
++ */
++
++/* states */
++#define DL_WAITING 0 /* waiting to rx first pkt */
++#define DL_READY 1 /* hdr was good, waiting for more of the
++ * compressed image
++ */
++#define DL_BAD_HDR 2 /* hdr was corrupted */
++#define DL_BAD_CRC 3 /* compressed image was corrupted */
++#define DL_RUNNABLE 4 /* download was successful,waiting for go cmd */
++#define DL_START_FAIL 5 /* failed to initialize correctly */
++#define DL_NVRAM_TOOBIG 6 /* host specified nvram data exceeds DL_NVRAM
++ * value
++ */
++#define DL_IMAGE_TOOBIG 7 /* firmware image too big */
++
++
++struct trx_header_le {
++ __le32 magic; /* "HDR0" */
++ __le32 len; /* Length of file including header */
++ __le32 crc32; /* CRC from flag_version to end of file */
++ __le32 flag_version; /* 0:15 flags, 16:31 version */
++ __le32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of
++ * header
++ */
++};
+
+-#define CONFIGDESC(usb) (&((usb)->actconfig)->desc)
+-#define IFPTR(usb, idx) ((usb)->actconfig->interface[(idx)])
+-#define IFALTS(usb, idx) (IFPTR((usb), (idx))->altsetting[0])
+-#define IFDESC(usb, idx) IFALTS((usb), (idx)).desc
+-#define IFEPDESC(usb, idx, ep) (IFALTS((usb), (idx)).endpoint[(ep)]).desc
+-
+-#define CONTROL_IF 0
+-#define BULK_IF 0
+-
+-#define BRCMF_USB_CBCTL_WRITE 0
+-#define BRCMF_USB_CBCTL_READ 1
+-#define BRCMF_USB_MAX_PKT_SIZE 1600
+-
+-#define BRCMF_USB_43143_FW_NAME "brcm/brcmfmac43143.bin"
+-#define BRCMF_USB_43236_FW_NAME "brcm/brcmfmac43236b.bin"
+-#define BRCMF_USB_43242_FW_NAME "brcm/brcmfmac43242a.bin"
++struct rdl_state_le {
++ __le32 state;
++ __le32 bytes;
++};
++
++struct bootrom_id_le {
++ __le32 chip; /* Chip id */
++ __le32 chiprev; /* Chip rev */
++ __le32 ramsize; /* Size of RAM */
++ __le32 remapbase; /* Current remap base address */
++ __le32 boardtype; /* Type of board */
++ __le32 boardrev; /* Board revision */
++};
+
+ struct brcmf_usb_image {
+ struct list_head list;
+@@ -61,12 +119,6 @@
+ u8 *image;
+ int image_len;
+ };
+-static struct list_head fw_image_list;
+-
+-struct intr_transfer_buf {
+- u32 notification;
+- u32 reserved;
+-};
+
+ struct brcmf_usbdev_info {
+ struct brcmf_usbdev bus_pub; /* MUST BE FIRST */
+@@ -75,7 +127,7 @@
+ struct list_head rx_postq;
+ struct list_head tx_freeq;
+ struct list_head tx_postq;
+- uint rx_pipe, tx_pipe, intr_pipe, rx_pipe2;
++ uint rx_pipe, tx_pipe;
+
+ int rx_low_watermark;
+ int tx_low_watermark;
+@@ -87,7 +139,7 @@
+ struct brcmf_usbreq *tx_reqs;
+ struct brcmf_usbreq *rx_reqs;
+
+- u8 *image; /* buffer for combine fw and nvram */
++ const u8 *image; /* buffer for combine fw and nvram */
+ int image_len;
+
+ struct usb_device *usbdev;
+@@ -102,12 +154,11 @@
+ int ctl_completed;
+ wait_queue_head_t ioctl_resp_wait;
+ ulong ctl_op;
++ u8 ifnum;
+
+ struct urb *bulk_urb; /* used for FW download */
+- struct urb *intr_urb; /* URB for interrupt endpoint */
+- int intr_size; /* Size of interrupt message */
+- int interval; /* Interrupt polling interval */
+- struct intr_transfer_buf intr; /* Data buffer for interrupt endpoint */
++
++ bool wowl_enabled;
+ };
+
+ static void brcmf_usb_rx_refill(struct brcmf_usbdev_info *devinfo,
+@@ -370,7 +421,7 @@
+ brcmf_err("fail!\n");
+ while (!list_empty(q)) {
+ req = list_entry(q->next, struct brcmf_usbreq, list);
+- if (req && req->urb)
++ if (req)
+ usb_free_urb(req->urb);
+ list_del(q->next);
+ }
+@@ -525,45 +576,12 @@
+ brcmf_bus_change_state(bcmf_bus, BRCMF_BUS_DOWN);
+ } else if (state == BRCMFMAC_USB_STATE_UP) {
+ brcmf_dbg(USB, "DBUS is up\n");
+- brcmf_bus_change_state(bcmf_bus, BRCMF_BUS_DATA);
++ brcmf_bus_change_state(bcmf_bus, BRCMF_BUS_UP);
+ } else {
+ brcmf_dbg(USB, "DBUS current state=%d\n", state);
+ }
+ }
+
+-static void
+-brcmf_usb_intr_complete(struct urb *urb)
+-{
+- struct brcmf_usbdev_info *devinfo =
+- (struct brcmf_usbdev_info *)urb->context;
+- int err;
+-
+- brcmf_dbg(USB, "Enter, urb->status=%d\n", urb->status);
+-
+- if (devinfo == NULL)
+- return;
+-
+- if (unlikely(urb->status)) {
+- if (urb->status == -ENOENT ||
+- urb->status == -ESHUTDOWN ||
+- urb->status == -ENODEV) {
+- brcmf_usb_state_change(devinfo,
+- BRCMFMAC_USB_STATE_DOWN);
+- }
+- }
+-
+- if (devinfo->bus_pub.state == BRCMFMAC_USB_STATE_DOWN) {
+- brcmf_err("intr cb when DBUS down, ignoring\n");
+- return;
+- }
+-
+- if (devinfo->bus_pub.state == BRCMFMAC_USB_STATE_UP) {
+- err = usb_submit_urb(devinfo->intr_urb, GFP_ATOMIC);
+- if (err)
+- brcmf_err("usb_submit_urb, err=%d\n", err);
+- }
+-}
+-
+ static int brcmf_usb_tx(struct device *dev, struct sk_buff *skb)
+ {
+ struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
+@@ -618,8 +636,6 @@
+ static int brcmf_usb_up(struct device *dev)
+ {
+ struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
+- u16 ifnum;
+- int ret;
+
+ brcmf_dbg(USB, "Enter\n");
+ if (devinfo->bus_pub.state == BRCMFMAC_USB_STATE_UP)
+@@ -628,47 +644,38 @@
+ /* Success, indicate devinfo is fully up */
+ brcmf_usb_state_change(devinfo, BRCMFMAC_USB_STATE_UP);
+
+- if (devinfo->intr_urb) {
+- usb_fill_int_urb(devinfo->intr_urb, devinfo->usbdev,
+- devinfo->intr_pipe,
+- &devinfo->intr,
+- devinfo->intr_size,
+- (usb_complete_t)brcmf_usb_intr_complete,
+- devinfo,
+- devinfo->interval);
+-
+- ret = usb_submit_urb(devinfo->intr_urb, GFP_ATOMIC);
+- if (ret) {
+- brcmf_err("USB_SUBMIT_URB failed with status %d\n",
+- ret);
+- return -EINVAL;
+- }
+- }
+-
+ if (devinfo->ctl_urb) {
+ devinfo->ctl_in_pipe = usb_rcvctrlpipe(devinfo->usbdev, 0);
+ devinfo->ctl_out_pipe = usb_sndctrlpipe(devinfo->usbdev, 0);
+
+- ifnum = IFDESC(devinfo->usbdev, CONTROL_IF).bInterfaceNumber;
+-
+ /* CTL Write */
+ devinfo->ctl_write.bRequestType =
+ USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
+ devinfo->ctl_write.bRequest = 0;
+ devinfo->ctl_write.wValue = cpu_to_le16(0);
+- devinfo->ctl_write.wIndex = cpu_to_le16p(&ifnum);
++ devinfo->ctl_write.wIndex = cpu_to_le16(devinfo->ifnum);
+
+ /* CTL Read */
+ devinfo->ctl_read.bRequestType =
+ USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE;
+ devinfo->ctl_read.bRequest = 1;
+ devinfo->ctl_read.wValue = cpu_to_le16(0);
+- devinfo->ctl_read.wIndex = cpu_to_le16p(&ifnum);
++ devinfo->ctl_read.wIndex = cpu_to_le16(devinfo->ifnum);
+ }
+ brcmf_usb_rx_fill_all(devinfo);
+ return 0;
+ }
+
++static void brcmf_cancel_all_urbs(struct brcmf_usbdev_info *devinfo)
++{
++ if (devinfo->ctl_urb)
++ usb_kill_urb(devinfo->ctl_urb);
++ if (devinfo->bulk_urb)
++ usb_kill_urb(devinfo->bulk_urb);
++ brcmf_usb_free_q(&devinfo->tx_postq, true);
++ brcmf_usb_free_q(&devinfo->rx_postq, true);
++}
++
+ static void brcmf_usb_down(struct device *dev)
+ {
+ struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
+@@ -681,17 +688,8 @@
+ return;
+
+ brcmf_usb_state_change(devinfo, BRCMFMAC_USB_STATE_DOWN);
+- if (devinfo->intr_urb)
+- usb_kill_urb(devinfo->intr_urb);
+-
+- if (devinfo->ctl_urb)
+- usb_kill_urb(devinfo->ctl_urb);
+
+- if (devinfo->bulk_urb)
+- usb_kill_urb(devinfo->bulk_urb);
+- brcmf_usb_free_q(&devinfo->tx_postq, true);
+-
+- brcmf_usb_free_q(&devinfo->rx_postq, true);
++ brcmf_cancel_all_urbs(devinfo);
+ }
+
+ static void
+@@ -704,19 +702,19 @@
+ brcmf_usb_ioctl_resp_wake(devinfo);
+ }
+
+-static bool brcmf_usb_dl_cmd(struct brcmf_usbdev_info *devinfo, u8 cmd,
+- void *buffer, int buflen)
++static int brcmf_usb_dl_cmd(struct brcmf_usbdev_info *devinfo, u8 cmd,
++ void *buffer, int buflen)
+ {
+- int ret = 0;
++ int ret;
+ char *tmpbuf;
+ u16 size;
+
+ if ((!devinfo) || (devinfo->ctl_urb == NULL))
+- return false;
++ return -EINVAL;
+
+ tmpbuf = kmalloc(buflen, GFP_ATOMIC);
+ if (!tmpbuf)
+- return false;
++ return -ENOMEM;
+
+ size = buflen;
+ devinfo->ctl_urb->transfer_buffer_length = size;
+@@ -737,14 +735,18 @@
+ ret = usb_submit_urb(devinfo->ctl_urb, GFP_ATOMIC);
+ if (ret < 0) {
+ brcmf_err("usb_submit_urb failed %d\n", ret);
+- kfree(tmpbuf);
+- return false;
++ goto finalize;
+ }
+
+- ret = brcmf_usb_ioctl_resp_wait(devinfo);
+- memcpy(buffer, tmpbuf, buflen);
+- kfree(tmpbuf);
++ if (!brcmf_usb_ioctl_resp_wait(devinfo)) {
++ usb_kill_urb(devinfo->ctl_urb);
++ ret = -ETIMEDOUT;
++ } else {
++ memcpy(buffer, tmpbuf, buflen);
++ }
+
++finalize:
++ kfree(tmpbuf);
+ return ret;
+ }
+
+@@ -786,6 +788,7 @@
+ {
+ struct bootrom_id_le id;
+ u32 loop_cnt;
++ int err;
+
+ brcmf_dbg(USB, "Enter\n");
+
+@@ -794,7 +797,9 @@
+ mdelay(BRCMF_USB_RESET_GETVER_SPINWAIT);
+ loop_cnt++;
+ id.chip = cpu_to_le32(0xDEAD); /* Get the ID */
+- brcmf_usb_dl_cmd(devinfo, DL_GETVER, &id, sizeof(id));
++ err = brcmf_usb_dl_cmd(devinfo, DL_GETVER, &id, sizeof(id));
++ if ((err) && (err != -ETIMEDOUT))
++ return err;
+ if (id.chip == cpu_to_le32(BRCMF_POSTBOOT_ID))
+ break;
+ } while (loop_cnt < BRCMF_USB_RESET_GETVER_LOOP_CNT);
+@@ -849,15 +854,14 @@
+
+ brcmf_dbg(USB, "Enter, fw %p, len %d\n", fw, fwlen);
+
+- bulkchunk = kmalloc(RDL_CHUNK, GFP_ATOMIC);
++ bulkchunk = kmalloc(TRX_RDL_CHUNK, GFP_ATOMIC);
+ if (bulkchunk == NULL) {
+ err = -ENOMEM;
+ goto fail;
+ }
+
+ /* 1) Prepare USB boot loader for runtime image */
+- brcmf_usb_dl_cmd(devinfo, DL_START, &state,
+- sizeof(struct rdl_state_le));
++ brcmf_usb_dl_cmd(devinfo, DL_START, &state, sizeof(state));
+
+ rdlstate = le32_to_cpu(state.state);
+ rdlbytes = le32_to_cpu(state.bytes);
+@@ -877,10 +881,10 @@
+ /* Wait until the usb device reports it received all
+ * the bytes we sent */
+ if ((rdlbytes == sent) && (rdlbytes != dllen)) {
+- if ((dllen-sent) < RDL_CHUNK)
++ if ((dllen-sent) < TRX_RDL_CHUNK)
+ sendlen = dllen-sent;
+ else
+- sendlen = RDL_CHUNK;
++ sendlen = TRX_RDL_CHUNK;
+
+ /* simply avoid having to send a ZLP by ensuring we
+ * never have an even
+@@ -901,10 +905,10 @@
+ dlpos += sendlen;
+ sent += sendlen;
+ }
+- if (!brcmf_usb_dl_cmd(devinfo, DL_GETSTATE, &state,
+- sizeof(struct rdl_state_le))) {
+- brcmf_err("DL_GETSTATE Failed xxxx\n");
+- err = -EINVAL;
++ err = brcmf_usb_dl_cmd(devinfo, DL_GETSTATE, &state,
++ sizeof(state));
++ if (err) {
++ brcmf_err("DL_GETSTATE Failed\n");
+ goto fail;
+ }
+
+@@ -960,13 +964,12 @@
+ return -EINVAL;
+
+ /* Check we are runnable */
+- brcmf_usb_dl_cmd(devinfo, DL_GETSTATE, &state,
+- sizeof(struct rdl_state_le));
++ state.state = 0;
++ brcmf_usb_dl_cmd(devinfo, DL_GETSTATE, &state, sizeof(state));
+
+ /* Start the image */
+ if (state.state == cpu_to_le32(DL_RUNNABLE)) {
+- if (!brcmf_usb_dl_cmd(devinfo, DL_GO, &state,
+- sizeof(struct rdl_state_le)))
++ if (brcmf_usb_dl_cmd(devinfo, DL_GO, &state, sizeof(state)))
+ return -ENODEV;
+ if (brcmf_usb_resetcfg(devinfo))
+ return -ENODEV;
+@@ -982,13 +985,16 @@
+ static bool brcmf_usb_chip_support(int chipid, int chiprev)
+ {
+ switch(chipid) {
+- case 43143:
++ case BRCM_CC_43143_CHIP_ID:
+ return true;
+- case 43235:
+- case 43236:
+- case 43238:
++ case BRCM_CC_43235_CHIP_ID:
++ case BRCM_CC_43236_CHIP_ID:
++ case BRCM_CC_43238_CHIP_ID:
+ return (chiprev == 3);
+- case 43242:
++ case BRCM_CC_43242_CHIP_ID:
++ return true;
++ case BRCM_CC_43566_CHIP_ID:
++ case BRCM_CC_43569_CHIP_ID:
+ return true;
+ default:
+ break;
+@@ -1021,7 +1027,7 @@
+ }
+
+ err = brcmf_usb_dlstart(devinfo,
+- devinfo->image, devinfo->image_len);
++ (u8 *)devinfo->image, devinfo->image_len);
+ if (err == 0)
+ err = brcmf_usb_dlrun(devinfo);
+ return err;
+@@ -1036,7 +1042,6 @@
+ brcmf_usb_free_q(&devinfo->rx_freeq, false);
+ brcmf_usb_free_q(&devinfo->tx_freeq, false);
+
+- usb_free_urb(devinfo->intr_urb);
+ usb_free_urb(devinfo->ctl_urb);
+ usb_free_urb(devinfo->bulk_urb);
+
+@@ -1044,21 +1049,6 @@
+ kfree(devinfo->rx_reqs);
+ }
+
+-#define TRX_MAGIC 0x30524448 /* "HDR0" */
+-#define TRX_VERSION 1 /* Version 1 */
+-#define TRX_MAX_LEN 0x3B0000 /* Max length */
+-#define TRX_NO_HEADER 1 /* Do not write TRX header */
+-#define TRX_MAX_OFFSET 3 /* Max number of individual files */
+-#define TRX_UNCOMP_IMAGE 0x20 /* Trx contains uncompressed image */
+-
+-struct trx_header_le {
+- __le32 magic; /* "HDR0" */
+- __le32 len; /* Length of file including header */
+- __le32 crc32; /* CRC from flag_version to end of file */
+- __le32 flag_version; /* 0:15 flags, 16:31 version */
+- __le32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of
+- * header */
+-};
+
+ static int check_file(const u8 *headers)
+ {
+@@ -1080,68 +1070,23 @@
+ return -1;
+ }
+
+-static int brcmf_usb_get_fw(struct brcmf_usbdev_info *devinfo)
++static const char *brcmf_usb_get_fwname(struct brcmf_usbdev_info *devinfo)
+ {
+- s8 *fwname;
+- const struct firmware *fw;
+- struct brcmf_usb_image *fw_image;
+- int err;
+-
+- brcmf_dbg(USB, "Enter\n");
+ switch (devinfo->bus_pub.devid) {
+- case 43143:
+- fwname = BRCMF_USB_43143_FW_NAME;
+- break;
+- case 43235:
+- case 43236:
+- case 43238:
+- fwname = BRCMF_USB_43236_FW_NAME;
+- break;
+- case 43242:
+- fwname = BRCMF_USB_43242_FW_NAME;
+- break;
++ case BRCM_CC_43143_CHIP_ID:
++ return BRCMF_USB_43143_FW_NAME;
++ case BRCM_CC_43235_CHIP_ID:
++ case BRCM_CC_43236_CHIP_ID:
++ case BRCM_CC_43238_CHIP_ID:
++ return BRCMF_USB_43236_FW_NAME;
++ case BRCM_CC_43242_CHIP_ID:
++ return BRCMF_USB_43242_FW_NAME;
++ case BRCM_CC_43566_CHIP_ID:
++ case BRCM_CC_43569_CHIP_ID:
++ return BRCMF_USB_43569_FW_NAME;
+ default:
+- return -EINVAL;
+- break;
+- }
+- brcmf_dbg(USB, "Loading FW %s\n", fwname);
+- list_for_each_entry(fw_image, &fw_image_list, list) {
+- if (fw_image->fwname == fwname) {
+- devinfo->image = fw_image->image;
+- devinfo->image_len = fw_image->image_len;
+- return 0;
+- }
+- }
+- /* fw image not yet loaded. Load it now and add to list */
+- err = request_firmware(&fw, fwname, devinfo->dev);
+- if (!fw) {
+- brcmf_err("fail to request firmware %s\n", fwname);
+- return err;
+- }
+- if (check_file(fw->data) < 0) {
+- brcmf_err("invalid firmware %s\n", fwname);
+- return -EINVAL;
++ return NULL;
+ }
+-
+- fw_image = kzalloc(sizeof(*fw_image), GFP_ATOMIC);
+- if (!fw_image)
+- return -ENOMEM;
+- INIT_LIST_HEAD(&fw_image->list);
+- list_add_tail(&fw_image->list, &fw_image_list);
+- fw_image->fwname = fwname;
+- fw_image->image = vmalloc(fw->size);
+- if (!fw_image->image)
+- return -ENOMEM;
+-
+- memcpy(fw_image->image, fw->data, fw->size);
+- fw_image->image_len = fw->size;
+-
+- release_firmware(fw);
+-
+- devinfo->image = fw_image->image;
+- devinfo->image_len = fw_image->image_len;
+-
+- return 0;
+ }
+
+
+@@ -1186,11 +1131,6 @@
+ goto error;
+ devinfo->tx_freecount = ntxq;
+
+- devinfo->intr_urb = usb_alloc_urb(0, GFP_ATOMIC);
+- if (!devinfo->intr_urb) {
+- brcmf_err("usb_alloc_urb (intr) failed\n");
+- goto error;
+- }
+ devinfo->ctl_urb = usb_alloc_urb(0, GFP_ATOMIC);
+ if (!devinfo->ctl_urb) {
+ brcmf_err("usb_alloc_urb (ctl) failed\n");
+@@ -1202,16 +1142,6 @@
+ goto error;
+ }
+
+- if (!brcmf_usb_dlneeded(devinfo))
+- return &devinfo->bus_pub;
+-
+- brcmf_dbg(USB, "Start fw downloading\n");
+- if (brcmf_usb_get_fw(devinfo))
+- goto error;
+-
+- if (brcmf_usb_fw_download(devinfo))
+- goto error;
+-
+ return &devinfo->bus_pub;
+
+ error:
+@@ -1220,20 +1150,92 @@
+ return NULL;
+ }
+
++static void brcmf_usb_wowl_config(struct device *dev, bool enabled)
++{
++ struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(dev);
++
++ brcmf_dbg(USB, "Configuring WOWL, enabled=%d\n", enabled);
++ devinfo->wowl_enabled = enabled;
++ if (enabled)
++ device_set_wakeup_enable(devinfo->dev, true);
++ else
++ device_set_wakeup_enable(devinfo->dev, false);
++}
++
+ static struct brcmf_bus_ops brcmf_usb_bus_ops = {
+ .txdata = brcmf_usb_tx,
+- .init = brcmf_usb_up,
+ .stop = brcmf_usb_down,
+ .txctl = brcmf_usb_tx_ctlpkt,
+ .rxctl = brcmf_usb_rx_ctlpkt,
++ .wowl_config = brcmf_usb_wowl_config,
+ };
+
++static int brcmf_usb_bus_setup(struct brcmf_usbdev_info *devinfo)
++{
++ int ret;
++
++ /* Attach to the common driver interface */
++ ret = brcmf_attach(devinfo->dev);
++ if (ret) {
++ brcmf_err("brcmf_attach failed\n");
++ return ret;
++ }
++
++ ret = brcmf_usb_up(devinfo->dev);
++ if (ret)
++ goto fail;
++
++ ret = brcmf_bus_start(devinfo->dev);
++ if (ret)
++ goto fail;
++
++ return 0;
++fail:
++ brcmf_detach(devinfo->dev);
++ return ret;
++}
++
++static void brcmf_usb_probe_phase2(struct device *dev,
++ const struct firmware *fw,
++ void *nvram, u32 nvlen)
++{
++ struct brcmf_bus *bus = dev_get_drvdata(dev);
++ struct brcmf_usbdev_info *devinfo;
++ int ret;
++
++ brcmf_dbg(USB, "Start fw downloading\n");
++ ret = check_file(fw->data);
++ if (ret < 0) {
++ brcmf_err("invalid firmware\n");
++ release_firmware(fw);
++ goto error;
++ }
++
++ devinfo = bus->bus_priv.usb->devinfo;
++ devinfo->image = fw->data;
++ devinfo->image_len = fw->size;
++
++ ret = brcmf_usb_fw_download(devinfo);
++ release_firmware(fw);
++ if (ret)
++ goto error;
++
++ ret = brcmf_usb_bus_setup(devinfo);
++ if (ret)
++ goto error;
++
++ return;
++error:
++ brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), ret);
++ device_release_driver(dev);
++}
++
+ static int brcmf_usb_probe_cb(struct brcmf_usbdev_info *devinfo)
+ {
+ struct brcmf_bus *bus = NULL;
+ struct brcmf_usbdev *bus_pub = NULL;
+- int ret;
+ struct device *dev = devinfo->dev;
++ int ret;
+
+ brcmf_dbg(USB, "Enter\n");
+ bus_pub = brcmf_usb_attach(devinfo, BRCMF_USB_NRXQ, BRCMF_USB_NTXQ);
+@@ -1251,25 +1253,32 @@
+ bus->bus_priv.usb = bus_pub;
+ dev_set_drvdata(dev, bus);
+ bus->ops = &brcmf_usb_bus_ops;
+- bus->chip = bus_pub->devid;
+- bus->chiprev = bus_pub->chiprev;
+ bus->proto_type = BRCMF_PROTO_BCDC;
+-
+- /* Attach to the common driver interface */
+- ret = brcmf_attach(dev);
+- if (ret) {
+- brcmf_err("brcmf_attach failed\n");
+- goto fail;
++ bus->always_use_fws_queue = true;
++#ifdef CONFIG_PM
++ bus->wowl_supported = true;
++#endif
++
++ if (!brcmf_usb_dlneeded(devinfo)) {
++ ret = brcmf_usb_bus_setup(devinfo);
++ if (ret)
++ goto fail;
++ /* we are done */
++ return 0;
+ }
++ bus->chip = bus_pub->devid;
++ bus->chiprev = bus_pub->chiprev;
+
+- ret = brcmf_bus_start(dev);
++ /* request firmware here */
++ ret = brcmf_fw_get_firmwares(dev, 0, brcmf_usb_get_fwname(devinfo),
++ NULL, brcmf_usb_probe_phase2);
+ if (ret) {
+- brcmf_err("dongle is not responding\n");
+- brcmf_detach(dev);
++ brcmf_err("firmware request failed: %d\n", ret);
+ goto fail;
+ }
+
+ return 0;
++
+ fail:
+ /* Release resources in reverse order */
+ kfree(bus);
+@@ -1292,15 +1301,15 @@
+ static int
+ brcmf_usb_probe(struct usb_interface *intf, const struct usb_device_id *id)
+ {
+- int ep;
+- struct usb_endpoint_descriptor *endpoint;
+- int ret = 0;
+ struct usb_device *usb = interface_to_usbdev(intf);
+- int num_of_eps;
+- u8 endpoint_num;
+ struct brcmf_usbdev_info *devinfo;
++ struct usb_interface_descriptor *desc;
++ struct usb_endpoint_descriptor *endpoint;
++ int ret = 0;
++ u32 num_of_eps;
++ u8 endpoint_num, ep;
+
+- brcmf_dbg(USB, "Enter\n");
++ brcmf_dbg(USB, "Enter 0x%04x:0x%04x\n", id->idVendor, id->idProduct);
+
+ devinfo = kzalloc(sizeof(*devinfo), GFP_ATOMIC);
+ if (devinfo == NULL)
+@@ -1308,102 +1317,71 @@
+
+ devinfo->usbdev = usb;
+ devinfo->dev = &usb->dev;
+-
+ usb_set_intfdata(intf, devinfo);
+
+ /* Check that the device supports only one configuration */
+ if (usb->descriptor.bNumConfigurations != 1) {
+- ret = -1;
++ brcmf_err("Number of configurations: %d not supported\n",
++ usb->descriptor.bNumConfigurations);
++ ret = -ENODEV;
+ goto fail;
+ }
+
+- if (usb->descriptor.bDeviceClass != USB_CLASS_VENDOR_SPEC) {
+- ret = -1;
++ if ((usb->descriptor.bDeviceClass != USB_CLASS_VENDOR_SPEC) &&
++ (usb->descriptor.bDeviceClass != USB_CLASS_MISC) &&
++ (usb->descriptor.bDeviceClass != USB_CLASS_WIRELESS_CONTROLLER)) {
++ brcmf_err("Device class: 0x%x not supported\n",
++ usb->descriptor.bDeviceClass);
++ ret = -ENODEV;
+ goto fail;
+ }
+
+- /*
+- * Only the BDC interface configuration is supported:
+- * Device class: USB_CLASS_VENDOR_SPEC
+- * if0 class: USB_CLASS_VENDOR_SPEC
+- * if0/ep0: control
+- * if0/ep1: bulk in
+- * if0/ep2: bulk out (ok if swapped with bulk in)
+- */
+- if (CONFIGDESC(usb)->bNumInterfaces != 1) {
+- ret = -1;
++ desc = &intf->altsetting[0].desc;
++ if ((desc->bInterfaceClass != USB_CLASS_VENDOR_SPEC) ||
++ (desc->bInterfaceSubClass != 2) ||
++ (desc->bInterfaceProtocol != 0xff)) {
++ brcmf_err("non WLAN interface %d: 0x%x:0x%x:0x%x\n",
++ desc->bInterfaceNumber, desc->bInterfaceClass,
++ desc->bInterfaceSubClass, desc->bInterfaceProtocol);
++ ret = -ENODEV;
+ goto fail;
+ }
+
+- /* Check interface */
+- if (IFDESC(usb, CONTROL_IF).bInterfaceClass != USB_CLASS_VENDOR_SPEC ||
+- IFDESC(usb, CONTROL_IF).bInterfaceSubClass != 2 ||
+- IFDESC(usb, CONTROL_IF).bInterfaceProtocol != 0xff) {
+- brcmf_err("invalid control interface: class %d, subclass %d, proto %d\n",
+- IFDESC(usb, CONTROL_IF).bInterfaceClass,
+- IFDESC(usb, CONTROL_IF).bInterfaceSubClass,
+- IFDESC(usb, CONTROL_IF).bInterfaceProtocol);
+- ret = -1;
+- goto fail;
+- }
+-
+- /* Check control endpoint */
+- endpoint = &IFEPDESC(usb, CONTROL_IF, 0);
+- if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK)
+- != USB_ENDPOINT_XFER_INT) {
+- brcmf_err("invalid control endpoint %d\n",
+- endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK);
+- ret = -1;
+- goto fail;
+- }
+-
+- endpoint_num = endpoint->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+- devinfo->intr_pipe = usb_rcvintpipe(usb, endpoint_num);
+-
+- devinfo->rx_pipe = 0;
+- devinfo->rx_pipe2 = 0;
+- devinfo->tx_pipe = 0;
+- num_of_eps = IFDESC(usb, BULK_IF).bNumEndpoints - 1;
+-
+- /* Check data endpoints and get pipes */
+- for (ep = 1; ep <= num_of_eps; ep++) {
+- endpoint = &IFEPDESC(usb, BULK_IF, ep);
+- if ((endpoint->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) !=
+- USB_ENDPOINT_XFER_BULK) {
+- brcmf_err("invalid data endpoint %d\n", ep);
+- ret = -1;
+- goto fail;
+- }
+-
+- endpoint_num = endpoint->bEndpointAddress &
+- USB_ENDPOINT_NUMBER_MASK;
+- if ((endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
+- == USB_DIR_IN) {
+- if (!devinfo->rx_pipe) {
++ num_of_eps = desc->bNumEndpoints;
++ for (ep = 0; ep < num_of_eps; ep++) {
++ endpoint = &intf->altsetting[0].endpoint[ep].desc;
++ endpoint_num = usb_endpoint_num(endpoint);
++ if (!usb_endpoint_xfer_bulk(endpoint))
++ continue;
++ if (usb_endpoint_dir_in(endpoint)) {
++ if (!devinfo->rx_pipe)
+ devinfo->rx_pipe =
+ usb_rcvbulkpipe(usb, endpoint_num);
+- } else {
+- devinfo->rx_pipe2 =
+- usb_rcvbulkpipe(usb, endpoint_num);
+- }
+ } else {
+- devinfo->tx_pipe = usb_sndbulkpipe(usb, endpoint_num);
++ if (!devinfo->tx_pipe)
++ devinfo->tx_pipe =
++ usb_sndbulkpipe(usb, endpoint_num);
+ }
+ }
++ if (devinfo->rx_pipe == 0) {
++ brcmf_err("No RX (in) Bulk EP found\n");
++ ret = -ENODEV;
++ goto fail;
++ }
++ if (devinfo->tx_pipe == 0) {
++ brcmf_err("No TX (out) Bulk EP found\n");
++ ret = -ENODEV;
++ goto fail;
++ }
+
+- /* Allocate interrupt URB and data buffer */
+- /* RNDIS says 8-byte intr, our old drivers used 4-byte */
+- if (IFEPDESC(usb, CONTROL_IF, 0).wMaxPacketSize == cpu_to_le16(16))
+- devinfo->intr_size = 8;
+- else
+- devinfo->intr_size = 4;
+-
+- devinfo->interval = IFEPDESC(usb, CONTROL_IF, 0).bInterval;
++ devinfo->ifnum = desc->bInterfaceNumber;
+
+- if (usb->speed == USB_SPEED_HIGH)
+- brcmf_dbg(USB, "Broadcom high speed USB wireless device detected\n");
++ if (usb->speed == USB_SPEED_SUPER)
++ brcmf_dbg(USB, "Broadcom super speed USB WLAN interface detected\n");
++ else if (usb->speed == USB_SPEED_HIGH)
++ brcmf_dbg(USB, "Broadcom high speed USB WLAN interface detected\n");
+ else
+- brcmf_dbg(USB, "Broadcom full speed USB wireless device detected\n");
++ brcmf_dbg(USB, "Broadcom full speed USB WLAN interface detected\n");
+
+ ret = brcmf_usb_probe_cb(devinfo);
+ if (ret)
+@@ -1413,11 +1391,9 @@
+ return 0;
+
+ fail:
+- brcmf_err("failed with errno %d\n", ret);
+ kfree(devinfo);
+ usb_set_intfdata(intf, NULL);
+ return ret;
+-
+ }
+
+ static void
+@@ -1442,7 +1418,10 @@
+
+ brcmf_dbg(USB, "Enter\n");
+ devinfo->bus_pub.state = BRCMFMAC_USB_STATE_SLEEP;
+- brcmf_detach(&usb->dev);
++ if (devinfo->wowl_enabled)
++ brcmf_cancel_all_urbs(devinfo);
++ else
++ brcmf_detach(&usb->dev);
+ return 0;
+ }
+
+@@ -1455,9 +1434,11 @@
+ struct brcmf_usbdev_info *devinfo = brcmf_usb_get_businfo(&usb->dev);
+
+ brcmf_dbg(USB, "Enter\n");
+- if (!brcmf_attach(devinfo->dev))
+- return brcmf_bus_start(&usb->dev);
++ if (!devinfo->wowl_enabled)
++ return brcmf_usb_bus_setup(devinfo);
+
++ devinfo->bus_pub.state = BRCMFMAC_USB_STATE_UP;
++ brcmf_usb_rx_fill_all(devinfo);
+ return 0;
+ }
+
+@@ -1468,31 +1449,29 @@
+
+ brcmf_dbg(USB, "Enter\n");
+
+- if (!brcmf_usb_fw_download(devinfo))
+- return brcmf_usb_resume(intf);
+-
+- return -EIO;
++ return brcmf_fw_get_firmwares(&usb->dev, 0,
++ brcmf_usb_get_fwname(devinfo), NULL,
++ brcmf_usb_probe_phase2);
+ }
+
+-#define BRCMF_USB_VENDOR_ID_BROADCOM 0x0a5c
+-#define BRCMF_USB_DEVICE_ID_43143 0xbd1e
+-#define BRCMF_USB_DEVICE_ID_43236 0xbd17
+-#define BRCMF_USB_DEVICE_ID_43242 0xbd1f
+-#define BRCMF_USB_DEVICE_ID_BCMFW 0x0bdc
++#define BRCMF_USB_DEVICE(dev_id) \
++ { USB_DEVICE(BRCM_USB_VENDOR_ID_BROADCOM, dev_id) }
+
+ static struct usb_device_id brcmf_usb_devid_table[] = {
+- { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_43143) },
+- { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_43236) },
+- { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_43242) },
++ BRCMF_USB_DEVICE(BRCM_USB_43143_DEVICE_ID),
++ BRCMF_USB_DEVICE(BRCM_USB_43236_DEVICE_ID),
++ BRCMF_USB_DEVICE(BRCM_USB_43242_DEVICE_ID),
++ BRCMF_USB_DEVICE(BRCM_USB_43569_DEVICE_ID),
+ /* special entry for device with firmware loaded and running */
+- { USB_DEVICE(BRCMF_USB_VENDOR_ID_BROADCOM, BRCMF_USB_DEVICE_ID_BCMFW) },
+- { }
++ BRCMF_USB_DEVICE(BRCM_USB_BCMFW_DEVICE_ID),
++ { /* end: all zeroes */ }
+ };
+
+ MODULE_DEVICE_TABLE(usb, brcmf_usb_devid_table);
+ MODULE_FIRMWARE(BRCMF_USB_43143_FW_NAME);
+ MODULE_FIRMWARE(BRCMF_USB_43236_FW_NAME);
+ MODULE_FIRMWARE(BRCMF_USB_43242_FW_NAME);
++MODULE_FIRMWARE(BRCMF_USB_43569_FW_NAME);
+
+ static struct usb_driver brcmf_usbdrvr = {
+ .name = KBUILD_MODNAME,
+@@ -1506,16 +1485,6 @@
+ .disable_hub_initiated_lpm = 1,
+ };
+
+-static void brcmf_release_fw(struct list_head *q)
+-{
+- struct brcmf_usb_image *fw_image, *next;
+-
+- list_for_each_entry_safe(fw_image, next, q, list) {
+- vfree(fw_image->image);
+- list_del_init(&fw_image->list);
+- }
+-}
+-
+ static int brcmf_usb_reset_device(struct device *dev, void *notused)
+ {
+ /* device past is the usb interface so we
+@@ -1534,12 +1503,10 @@
+ ret = driver_for_each_device(drv, NULL, NULL,
+ brcmf_usb_reset_device);
+ usb_deregister(&brcmf_usbdrvr);
+- brcmf_release_fw(&fw_image_list);
+ }
+
+ void brcmf_usb_register(void)
+ {
+ brcmf_dbg(USB, "Enter\n");
+- INIT_LIST_HEAD(&fw_image_list);
+ usb_register(&brcmf_usbdrvr);
+ }
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/usb_rdl.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/usb_rdl.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/usb_rdl.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/usb_rdl.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,75 +0,0 @@
+-/*
+- * Copyright (c) 2011 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#ifndef _USB_RDL_H
+-#define _USB_RDL_H
+-
+-/* Control messages: bRequest values */
+-#define DL_GETSTATE 0 /* returns the rdl_state_t struct */
+-#define DL_CHECK_CRC 1 /* currently unused */
+-#define DL_GO 2 /* execute downloaded image */
+-#define DL_START 3 /* initialize dl state */
+-#define DL_REBOOT 4 /* reboot the device in 2 seconds */
+-#define DL_GETVER 5 /* returns the bootrom_id_t struct */
+-#define DL_GO_PROTECTED 6 /* execute the downloaded code and set reset
+- * event to occur in 2 seconds. It is the
+- * responsibility of the downloaded code to
+- * clear this event
+- */
+-#define DL_EXEC 7 /* jump to a supplied address */
+-#define DL_RESETCFG 8 /* To support single enum on dongle
+- * - Not used by bootloader
+- */
+-#define DL_DEFER_RESP_OK 9 /* Potentially defer the response to setup
+- * if resp unavailable
+- */
+-
+-/* states */
+-#define DL_WAITING 0 /* waiting to rx first pkt */
+-#define DL_READY 1 /* hdr was good, waiting for more of the
+- * compressed image */
+-#define DL_BAD_HDR 2 /* hdr was corrupted */
+-#define DL_BAD_CRC 3 /* compressed image was corrupted */
+-#define DL_RUNNABLE 4 /* download was successful,waiting for go cmd */
+-#define DL_START_FAIL 5 /* failed to initialize correctly */
+-#define DL_NVRAM_TOOBIG 6 /* host specified nvram data exceeds DL_NVRAM
+- * value */
+-#define DL_IMAGE_TOOBIG 7 /* download image too big (exceeds DATA_START
+- * for rdl) */
+-
+-struct rdl_state_le {
+- __le32 state;
+- __le32 bytes;
+-};
+-
+-struct bootrom_id_le {
+- __le32 chip; /* Chip id */
+- __le32 chiprev; /* Chip rev */
+- __le32 ramsize; /* Size of RAM */
+- __le32 remapbase; /* Current remap base address */
+- __le32 boardtype; /* Type of board */
+- __le32 boardrev; /* Board revision */
+-};
+-
+-#define RDL_CHUNK 1500 /* size of each dl transfer */
+-
+-#define TRX_OFFSETS_DLFWLEN_IDX 0
+-#define TRX_OFFSETS_JUMPTO_IDX 1
+-#define TRX_OFFSETS_NVM_LEN_IDX 2
+-
+-#define TRX_OFFSETS_DLBASE_IDX 0
+-
+-#endif /* _USB_RDL_H */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/vendor.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/vendor.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/vendor.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/vendor.c 2016-06-19 22:11:55.293140794 +0200
+@@ -0,0 +1,127 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#include <linux/vmalloc.h>
++#include <net/cfg80211.h>
++#include <net/netlink.h>
++
++#include <brcmu_wifi.h>
++#include "fwil_types.h"
++#include "core.h"
++#include "p2p.h"
++#include "debug.h"
++#include "cfg80211.h"
++#include "vendor.h"
++#include "fwil.h"
++
++static int brcmf_cfg80211_vndr_cmds_dcmd_handler(struct wiphy *wiphy,
++ struct wireless_dev *wdev,
++ const void *data, int len)
++{
++ struct brcmf_cfg80211_vif *vif;
++ struct brcmf_if *ifp;
++ const struct brcmf_vndr_dcmd_hdr *cmdhdr = data;
++ struct sk_buff *reply;
++ int ret, payload, ret_len;
++ void *dcmd_buf = NULL, *wr_pointer;
++ u16 msglen, maxmsglen = PAGE_SIZE - 0x100;
++
++ if (len < sizeof(*cmdhdr)) {
++ brcmf_err("vendor command too short: %d\n", len);
++ return -EINVAL;
++ }
++
++ vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
++ ifp = vif->ifp;
++
++ brcmf_dbg(TRACE, "ifidx=%d, cmd=%d\n", ifp->ifidx, cmdhdr->cmd);
++
++ if (cmdhdr->offset > len) {
++ brcmf_err("bad buffer offset %d > %d\n", cmdhdr->offset, len);
++ return -EINVAL;
++ }
++
++ len -= cmdhdr->offset;
++ ret_len = cmdhdr->len;
++ if (ret_len > 0 || len > 0) {
++ if (len > BRCMF_DCMD_MAXLEN) {
++ brcmf_err("oversize input buffer %d\n", len);
++ len = BRCMF_DCMD_MAXLEN;
++ }
++ if (ret_len > BRCMF_DCMD_MAXLEN) {
++ brcmf_err("oversize return buffer %d\n", ret_len);
++ ret_len = BRCMF_DCMD_MAXLEN;
++ }
++ payload = max(ret_len, len) + 1;
++ dcmd_buf = vzalloc(payload);
++ if (NULL == dcmd_buf)
++ return -ENOMEM;
++
++ memcpy(dcmd_buf, (void *)cmdhdr + cmdhdr->offset, len);
++ *(char *)(dcmd_buf + len) = '\0';
++ }
++
++ if (cmdhdr->set)
++ ret = brcmf_fil_cmd_data_set(ifp, cmdhdr->cmd, dcmd_buf,
++ ret_len);
++ else
++ ret = brcmf_fil_cmd_data_get(ifp, cmdhdr->cmd, dcmd_buf,
++ ret_len);
++ if (ret != 0)
++ goto exit;
++
++ wr_pointer = dcmd_buf;
++ while (ret_len > 0) {
++ msglen = ret_len > maxmsglen ? maxmsglen : ret_len;
++ ret_len -= msglen;
++ payload = msglen + sizeof(msglen);
++ reply = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, payload);
++ if (NULL == reply) {
++ ret = -ENOMEM;
++ break;
++ }
++
++ if (nla_put(reply, BRCMF_NLATTR_DATA, msglen, wr_pointer) ||
++ nla_put_u16(reply, BRCMF_NLATTR_LEN, msglen)) {
++ kfree_skb(reply);
++ ret = -ENOBUFS;
++ break;
++ }
++
++ ret = cfg80211_vendor_cmd_reply(reply);
++ if (ret)
++ break;
++
++ wr_pointer += msglen;
++ }
++
++exit:
++ vfree(dcmd_buf);
++
++ return ret;
++}
++
++const struct wiphy_vendor_command brcmf_vendor_cmds[] = {
++ {
++ {
++ .vendor_id = BROADCOM_OUI,
++ .subcmd = BRCMF_VNDR_CMDS_DCMD
++ },
++ .flags = WIPHY_VENDOR_CMD_NEED_WDEV |
++ WIPHY_VENDOR_CMD_NEED_NETDEV,
++ .doit = brcmf_cfg80211_vndr_cmds_dcmd_handler
++ },
++};
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/vendor.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/vendor.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/vendor.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/vendor.h 2016-06-19 22:11:55.293140794 +0200
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (c) 2014 Broadcom Corporation
++ *
++ * Permission to use, copy, modify, and/or distribute this software for any
++ * purpose with or without fee is hereby granted, provided that the above
++ * copyright notice and this permission notice appear in all copies.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
++ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
++ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
++ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
++ */
++
++#ifndef _vendor_h_
++#define _vendor_h_
++
++#define BROADCOM_OUI 0x001018
++
++enum brcmf_vndr_cmds {
++ BRCMF_VNDR_CMDS_UNSPEC,
++ BRCMF_VNDR_CMDS_DCMD,
++ BRCMF_VNDR_CMDS_LAST
++};
++
++/**
++ * enum brcmf_nlattrs - nl80211 message attributes
++ *
++ * @BRCMF_NLATTR_LEN: message body length
++ * @BRCMF_NLATTR_DATA: message body
++ */
++enum brcmf_nlattrs {
++ BRCMF_NLATTR_UNSPEC,
++
++ BRCMF_NLATTR_LEN,
++ BRCMF_NLATTR_DATA,
++
++ __BRCMF_NLATTR_AFTER_LAST,
++ BRCMF_NLATTR_MAX = __BRCMF_NLATTR_AFTER_LAST - 1
++};
++
++/**
++ * struct brcmf_vndr_dcmd_hdr - message header for cfg80211 vendor command dcmd
++ * support
++ *
++ * @cmd: common dongle cmd definition
++ * @len: length of expecting return buffer
++ * @offset: offset of data buffer
++ * @set: get or set request(optional)
++ * @magic: magic number for verification
++ */
++struct brcmf_vndr_dcmd_hdr {
++ uint cmd;
++ int len;
++ uint offset;
++ uint set;
++ uint magic;
++};
++
++extern const struct wiphy_vendor_command brcmf_vendor_cmds[];
++
++#endif /* _vendor_h_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,5521 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-/* Toplevel file. Relies on dhd_linux.c to send commands to the dongle. */
+-
+-#include <linux/kernel.h>
+-#include <linux/etherdevice.h>
+-#include <net/cfg80211.h>
+-#include <net/netlink.h>
+-
+-#include <brcmu_utils.h>
+-#include <defs.h>
+-#include <brcmu_wifi.h>
+-#include "dhd.h"
+-#include "dhd_dbg.h"
+-#include "tracepoint.h"
+-#include "fwil_types.h"
+-#include "p2p.h"
+-#include "btcoex.h"
+-#include "wl_cfg80211.h"
+-#include "fwil.h"
+-
+-#define BRCMF_SCAN_IE_LEN_MAX 2048
+-#define BRCMF_PNO_VERSION 2
+-#define BRCMF_PNO_TIME 30
+-#define BRCMF_PNO_REPEAT 4
+-#define BRCMF_PNO_FREQ_EXPO_MAX 3
+-#define BRCMF_PNO_MAX_PFN_COUNT 16
+-#define BRCMF_PNO_ENABLE_ADAPTSCAN_BIT 6
+-#define BRCMF_PNO_HIDDEN_BIT 2
+-#define BRCMF_PNO_WPA_AUTH_ANY 0xFFFFFFFF
+-#define BRCMF_PNO_SCAN_COMPLETE 1
+-#define BRCMF_PNO_SCAN_INCOMPLETE 0
+-
+-#define BRCMF_IFACE_MAX_CNT 3
+-
+-#define WPA_OUI "\x00\x50\xF2" /* WPA OUI */
+-#define WPA_OUI_TYPE 1
+-#define RSN_OUI "\x00\x0F\xAC" /* RSN OUI */
+-#define WME_OUI_TYPE 2
+-#define WPS_OUI_TYPE 4
+-
+-#define VS_IE_FIXED_HDR_LEN 6
+-#define WPA_IE_VERSION_LEN 2
+-#define WPA_IE_MIN_OUI_LEN 4
+-#define WPA_IE_SUITE_COUNT_LEN 2
+-
+-#define WPA_CIPHER_NONE 0 /* None */
+-#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
+-#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
+-#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
+-#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
+-
+-#define RSN_AKM_NONE 0 /* None (IBSS) */
+-#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
+-#define RSN_AKM_PSK 2 /* Pre-shared Key */
+-#define RSN_CAP_LEN 2 /* Length of RSN capabilities */
+-#define RSN_CAP_PTK_REPLAY_CNTR_MASK 0x000C
+-
+-#define VNDR_IE_CMD_LEN 4 /* length of the set command
+- * string :"add", "del" (+ NUL)
+- */
+-#define VNDR_IE_COUNT_OFFSET 4
+-#define VNDR_IE_PKTFLAG_OFFSET 8
+-#define VNDR_IE_VSIE_OFFSET 12
+-#define VNDR_IE_HDR_SIZE 12
+-#define VNDR_IE_PARSE_LIMIT 5
+-
+-#define DOT11_MGMT_HDR_LEN 24 /* d11 management header len */
+-#define DOT11_BCN_PRB_FIXED_LEN 12 /* beacon/probe fixed length */
+-
+-#define BRCMF_SCAN_JOIN_ACTIVE_DWELL_TIME_MS 320
+-#define BRCMF_SCAN_JOIN_PASSIVE_DWELL_TIME_MS 400
+-#define BRCMF_SCAN_JOIN_PROBE_INTERVAL_MS 20
+-
+-#define BRCMF_ASSOC_PARAMS_FIXED_SIZE \
+- (sizeof(struct brcmf_assoc_params_le) - sizeof(u16))
+-
+-static bool check_vif_up(struct brcmf_cfg80211_vif *vif)
+-{
+- if (!test_bit(BRCMF_VIF_STATUS_READY, &vif->sme_state)) {
+- brcmf_dbg(INFO, "device is not ready : status (%lu)\n",
+- vif->sme_state);
+- return false;
+- }
+- return true;
+-}
+-
+-#define CHAN2G(_channel, _freq, _flags) { \
+- .band = IEEE80211_BAND_2GHZ, \
+- .center_freq = (_freq), \
+- .hw_value = (_channel), \
+- .flags = (_flags), \
+- .max_antenna_gain = 0, \
+- .max_power = 30, \
+-}
+-
+-#define CHAN5G(_channel, _flags) { \
+- .band = IEEE80211_BAND_5GHZ, \
+- .center_freq = 5000 + (5 * (_channel)), \
+- .hw_value = (_channel), \
+- .flags = (_flags), \
+- .max_antenna_gain = 0, \
+- .max_power = 30, \
+-}
+-
+-#define RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
+-#define RATETAB_ENT(_rateid, _flags) \
+- { \
+- .bitrate = RATE_TO_BASE100KBPS(_rateid), \
+- .hw_value = (_rateid), \
+- .flags = (_flags), \
+- }
+-
+-static struct ieee80211_rate __wl_rates[] = {
+- RATETAB_ENT(BRCM_RATE_1M, 0),
+- RATETAB_ENT(BRCM_RATE_2M, IEEE80211_RATE_SHORT_PREAMBLE),
+- RATETAB_ENT(BRCM_RATE_5M5, IEEE80211_RATE_SHORT_PREAMBLE),
+- RATETAB_ENT(BRCM_RATE_11M, IEEE80211_RATE_SHORT_PREAMBLE),
+- RATETAB_ENT(BRCM_RATE_6M, 0),
+- RATETAB_ENT(BRCM_RATE_9M, 0),
+- RATETAB_ENT(BRCM_RATE_12M, 0),
+- RATETAB_ENT(BRCM_RATE_18M, 0),
+- RATETAB_ENT(BRCM_RATE_24M, 0),
+- RATETAB_ENT(BRCM_RATE_36M, 0),
+- RATETAB_ENT(BRCM_RATE_48M, 0),
+- RATETAB_ENT(BRCM_RATE_54M, 0),
+-};
+-
+-#define wl_a_rates (__wl_rates + 4)
+-#define wl_a_rates_size 8
+-#define wl_g_rates (__wl_rates + 0)
+-#define wl_g_rates_size 12
+-
+-static struct ieee80211_channel __wl_2ghz_channels[] = {
+- CHAN2G(1, 2412, 0),
+- CHAN2G(2, 2417, 0),
+- CHAN2G(3, 2422, 0),
+- CHAN2G(4, 2427, 0),
+- CHAN2G(5, 2432, 0),
+- CHAN2G(6, 2437, 0),
+- CHAN2G(7, 2442, 0),
+- CHAN2G(8, 2447, 0),
+- CHAN2G(9, 2452, 0),
+- CHAN2G(10, 2457, 0),
+- CHAN2G(11, 2462, 0),
+- CHAN2G(12, 2467, 0),
+- CHAN2G(13, 2472, 0),
+- CHAN2G(14, 2484, 0),
+-};
+-
+-static struct ieee80211_channel __wl_5ghz_a_channels[] = {
+- CHAN5G(34, 0), CHAN5G(36, 0),
+- CHAN5G(38, 0), CHAN5G(40, 0),
+- CHAN5G(42, 0), CHAN5G(44, 0),
+- CHAN5G(46, 0), CHAN5G(48, 0),
+- CHAN5G(52, 0), CHAN5G(56, 0),
+- CHAN5G(60, 0), CHAN5G(64, 0),
+- CHAN5G(100, 0), CHAN5G(104, 0),
+- CHAN5G(108, 0), CHAN5G(112, 0),
+- CHAN5G(116, 0), CHAN5G(120, 0),
+- CHAN5G(124, 0), CHAN5G(128, 0),
+- CHAN5G(132, 0), CHAN5G(136, 0),
+- CHAN5G(140, 0), CHAN5G(149, 0),
+- CHAN5G(153, 0), CHAN5G(157, 0),
+- CHAN5G(161, 0), CHAN5G(165, 0),
+- CHAN5G(184, 0), CHAN5G(188, 0),
+- CHAN5G(192, 0), CHAN5G(196, 0),
+- CHAN5G(200, 0), CHAN5G(204, 0),
+- CHAN5G(208, 0), CHAN5G(212, 0),
+- CHAN5G(216, 0),
+-};
+-
+-static struct ieee80211_supported_band __wl_band_2ghz = {
+- .band = IEEE80211_BAND_2GHZ,
+- .channels = __wl_2ghz_channels,
+- .n_channels = ARRAY_SIZE(__wl_2ghz_channels),
+- .bitrates = wl_g_rates,
+- .n_bitrates = wl_g_rates_size,
+-};
+-
+-static struct ieee80211_supported_band __wl_band_5ghz_a = {
+- .band = IEEE80211_BAND_5GHZ,
+- .channels = __wl_5ghz_a_channels,
+- .n_channels = ARRAY_SIZE(__wl_5ghz_a_channels),
+- .bitrates = wl_a_rates,
+- .n_bitrates = wl_a_rates_size,
+-};
+-
+-/* This is to override regulatory domains defined in cfg80211 module (reg.c)
+- * By default world regulatory domain defined in reg.c puts the flags
+- * NL80211_RRF_NO_IR for 5GHz channels (for * 36..48 and 149..165).
+- * With respect to these flags, wpa_supplicant doesn't * start p2p
+- * operations on 5GHz channels. All the changes in world regulatory
+- * domain are to be done here.
+- */
+-static const struct ieee80211_regdomain brcmf_regdom = {
+- .n_reg_rules = 4,
+- .alpha2 = "99",
+- .reg_rules = {
+- /* IEEE 802.11b/g, channels 1..11 */
+- REG_RULE(2412-10, 2472+10, 40, 6, 20, 0),
+- /* If any */
+- /* IEEE 802.11 channel 14 - Only JP enables
+- * this and for 802.11b only
+- */
+- REG_RULE(2484-10, 2484+10, 20, 6, 20, 0),
+- /* IEEE 802.11a, channel 36..64 */
+- REG_RULE(5150-10, 5350+10, 40, 6, 20, 0),
+- /* IEEE 802.11a, channel 100..165 */
+- REG_RULE(5470-10, 5850+10, 40, 6, 20, 0), }
+-};
+-
+-static const u32 __wl_cipher_suites[] = {
+- WLAN_CIPHER_SUITE_WEP40,
+- WLAN_CIPHER_SUITE_WEP104,
+- WLAN_CIPHER_SUITE_TKIP,
+- WLAN_CIPHER_SUITE_CCMP,
+- WLAN_CIPHER_SUITE_AES_CMAC,
+-};
+-
+-/* Vendor specific ie. id = 221, oui and type defines exact ie */
+-struct brcmf_vs_tlv {
+- u8 id;
+- u8 len;
+- u8 oui[3];
+- u8 oui_type;
+-};
+-
+-struct parsed_vndr_ie_info {
+- u8 *ie_ptr;
+- u32 ie_len; /* total length including id & length field */
+- struct brcmf_vs_tlv vndrie;
+-};
+-
+-struct parsed_vndr_ies {
+- u32 count;
+- struct parsed_vndr_ie_info ie_info[VNDR_IE_PARSE_LIMIT];
+-};
+-
+-/* Quarter dBm units to mW
+- * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
+- * Table is offset so the last entry is largest mW value that fits in
+- * a u16.
+- */
+-
+-#define QDBM_OFFSET 153 /* Offset for first entry */
+-#define QDBM_TABLE_LEN 40 /* Table size */
+-
+-/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
+- * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
+- */
+-#define QDBM_TABLE_LOW_BOUND 6493 /* Low bound */
+-
+-/* Largest mW value that will round down to the last table entry,
+- * QDBM_OFFSET + QDBM_TABLE_LEN-1.
+- * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) +
+- * mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
+- */
+-#define QDBM_TABLE_HIGH_BOUND 64938 /* High bound */
+-
+-static const u16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
+-/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
+-/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
+-/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
+-/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
+-/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
+-/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
+-};
+-
+-static u16 brcmf_qdbm_to_mw(u8 qdbm)
+-{
+- uint factor = 1;
+- int idx = qdbm - QDBM_OFFSET;
+-
+- if (idx >= QDBM_TABLE_LEN)
+- /* clamp to max u16 mW value */
+- return 0xFFFF;
+-
+- /* scale the qdBm index up to the range of the table 0-40
+- * where an offset of 40 qdBm equals a factor of 10 mW.
+- */
+- while (idx < 0) {
+- idx += 40;
+- factor *= 10;
+- }
+-
+- /* return the mW value scaled down to the correct factor of 10,
+- * adding in factor/2 to get proper rounding.
+- */
+- return (nqdBm_to_mW_map[idx] + factor / 2) / factor;
+-}
+-
+-static u8 brcmf_mw_to_qdbm(u16 mw)
+-{
+- u8 qdbm;
+- int offset;
+- uint mw_uint = mw;
+- uint boundary;
+-
+- /* handle boundary case */
+- if (mw_uint <= 1)
+- return 0;
+-
+- offset = QDBM_OFFSET;
+-
+- /* move mw into the range of the table */
+- while (mw_uint < QDBM_TABLE_LOW_BOUND) {
+- mw_uint *= 10;
+- offset -= 40;
+- }
+-
+- for (qdbm = 0; qdbm < QDBM_TABLE_LEN - 1; qdbm++) {
+- boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm + 1] -
+- nqdBm_to_mW_map[qdbm]) / 2;
+- if (mw_uint < boundary)
+- break;
+- }
+-
+- qdbm += (u8) offset;
+-
+- return qdbm;
+-}
+-
+-u16 channel_to_chanspec(struct brcmu_d11inf *d11inf,
+- struct ieee80211_channel *ch)
+-{
+- struct brcmu_chan ch_inf;
+-
+- ch_inf.chnum = ieee80211_frequency_to_channel(ch->center_freq);
+- ch_inf.bw = BRCMU_CHAN_BW_20;
+- d11inf->encchspec(&ch_inf);
+-
+- return ch_inf.chspec;
+-}
+-
+-/* Traverse a string of 1-byte tag/1-byte length/variable-length value
+- * triples, returning a pointer to the substring whose first element
+- * matches tag
+- */
+-struct brcmf_tlv *brcmf_parse_tlvs(void *buf, int buflen, uint key)
+-{
+- struct brcmf_tlv *elt;
+- int totlen;
+-
+- elt = (struct brcmf_tlv *)buf;
+- totlen = buflen;
+-
+- /* find tagged parameter */
+- while (totlen >= TLV_HDR_LEN) {
+- int len = elt->len;
+-
+- /* validate remaining totlen */
+- if ((elt->id == key) && (totlen >= (len + TLV_HDR_LEN)))
+- return elt;
+-
+- elt = (struct brcmf_tlv *)((u8 *)elt + (len + TLV_HDR_LEN));
+- totlen -= (len + TLV_HDR_LEN);
+- }
+-
+- return NULL;
+-}
+-
+-/* Is any of the tlvs the expected entry? If
+- * not update the tlvs buffer pointer/length.
+- */
+-static bool
+-brcmf_tlv_has_ie(u8 *ie, u8 **tlvs, u32 *tlvs_len,
+- u8 *oui, u32 oui_len, u8 type)
+-{
+- /* If the contents match the OUI and the type */
+- if (ie[TLV_LEN_OFF] >= oui_len + 1 &&
+- !memcmp(&ie[TLV_BODY_OFF], oui, oui_len) &&
+- type == ie[TLV_BODY_OFF + oui_len]) {
+- return true;
+- }
+-
+- if (tlvs == NULL)
+- return false;
+- /* point to the next ie */
+- ie += ie[TLV_LEN_OFF] + TLV_HDR_LEN;
+- /* calculate the length of the rest of the buffer */
+- *tlvs_len -= (int)(ie - *tlvs);
+- /* update the pointer to the start of the buffer */
+- *tlvs = ie;
+-
+- return false;
+-}
+-
+-static struct brcmf_vs_tlv *
+-brcmf_find_wpaie(u8 *parse, u32 len)
+-{
+- struct brcmf_tlv *ie;
+-
+- while ((ie = brcmf_parse_tlvs(parse, len, WLAN_EID_VENDOR_SPECIFIC))) {
+- if (brcmf_tlv_has_ie((u8 *)ie, &parse, &len,
+- WPA_OUI, TLV_OUI_LEN, WPA_OUI_TYPE))
+- return (struct brcmf_vs_tlv *)ie;
+- }
+- return NULL;
+-}
+-
+-static struct brcmf_vs_tlv *
+-brcmf_find_wpsie(u8 *parse, u32 len)
+-{
+- struct brcmf_tlv *ie;
+-
+- while ((ie = brcmf_parse_tlvs(parse, len, WLAN_EID_VENDOR_SPECIFIC))) {
+- if (brcmf_tlv_has_ie((u8 *)ie, &parse, &len,
+- WPA_OUI, TLV_OUI_LEN, WPS_OUI_TYPE))
+- return (struct brcmf_vs_tlv *)ie;
+- }
+- return NULL;
+-}
+-
+-
+-static void convert_key_from_CPU(struct brcmf_wsec_key *key,
+- struct brcmf_wsec_key_le *key_le)
+-{
+- key_le->index = cpu_to_le32(key->index);
+- key_le->len = cpu_to_le32(key->len);
+- key_le->algo = cpu_to_le32(key->algo);
+- key_le->flags = cpu_to_le32(key->flags);
+- key_le->rxiv.hi = cpu_to_le32(key->rxiv.hi);
+- key_le->rxiv.lo = cpu_to_le16(key->rxiv.lo);
+- key_le->iv_initialized = cpu_to_le32(key->iv_initialized);
+- memcpy(key_le->data, key->data, sizeof(key->data));
+- memcpy(key_le->ea, key->ea, sizeof(key->ea));
+-}
+-
+-static int
+-send_key_to_dongle(struct net_device *ndev, struct brcmf_wsec_key *key)
+-{
+- int err;
+- struct brcmf_wsec_key_le key_le;
+-
+- convert_key_from_CPU(key, &key_le);
+-
+- brcmf_netdev_wait_pend8021x(ndev);
+-
+- err = brcmf_fil_bsscfg_data_set(netdev_priv(ndev), "wsec_key", &key_le,
+- sizeof(key_le));
+-
+- if (err)
+- brcmf_err("wsec_key error (%d)\n", err);
+- return err;
+-}
+-
+-static s32
+-brcmf_configure_arp_offload(struct brcmf_if *ifp, bool enable)
+-{
+- s32 err;
+- u32 mode;
+-
+- if (enable)
+- mode = BRCMF_ARP_OL_AGENT | BRCMF_ARP_OL_PEER_AUTO_REPLY;
+- else
+- mode = 0;
+-
+- /* Try to set and enable ARP offload feature, this may fail, then it */
+- /* is simply not supported and err 0 will be returned */
+- err = brcmf_fil_iovar_int_set(ifp, "arp_ol", mode);
+- if (err) {
+- brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
+- mode, err);
+- err = 0;
+- } else {
+- err = brcmf_fil_iovar_int_set(ifp, "arpoe", enable);
+- if (err) {
+- brcmf_dbg(TRACE, "failed to configure (%d) ARP offload err = %d\n",
+- enable, err);
+- err = 0;
+- } else
+- brcmf_dbg(TRACE, "successfully configured (%d) ARP offload to 0x%x\n",
+- enable, mode);
+- }
+-
+- return err;
+-}
+-
+-static struct wireless_dev *brcmf_cfg80211_add_iface(struct wiphy *wiphy,
+- const char *name,
+- enum nl80211_iftype type,
+- u32 *flags,
+- struct vif_params *params)
+-{
+- brcmf_dbg(TRACE, "enter: %s type %d\n", name, type);
+- switch (type) {
+- case NL80211_IFTYPE_ADHOC:
+- case NL80211_IFTYPE_STATION:
+- case NL80211_IFTYPE_AP:
+- case NL80211_IFTYPE_AP_VLAN:
+- case NL80211_IFTYPE_WDS:
+- case NL80211_IFTYPE_MONITOR:
+- case NL80211_IFTYPE_MESH_POINT:
+- return ERR_PTR(-EOPNOTSUPP);
+- case NL80211_IFTYPE_P2P_CLIENT:
+- case NL80211_IFTYPE_P2P_GO:
+- case NL80211_IFTYPE_P2P_DEVICE:
+- return brcmf_p2p_add_vif(wiphy, name, type, flags, params);
+- case NL80211_IFTYPE_UNSPECIFIED:
+- default:
+- return ERR_PTR(-EINVAL);
+- }
+-}
+-
+-void brcmf_set_mpc(struct brcmf_if *ifp, int mpc)
+-{
+- s32 err = 0;
+-
+- if (check_vif_up(ifp->vif)) {
+- err = brcmf_fil_iovar_int_set(ifp, "mpc", mpc);
+- if (err) {
+- brcmf_err("fail to set mpc\n");
+- return;
+- }
+- brcmf_dbg(INFO, "MPC : %d\n", mpc);
+- }
+-}
+-
+-s32 brcmf_notify_escan_complete(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_if *ifp, bool aborted,
+- bool fw_abort)
+-{
+- struct brcmf_scan_params_le params_le;
+- struct cfg80211_scan_request *scan_request;
+- s32 err = 0;
+-
+- brcmf_dbg(SCAN, "Enter\n");
+-
+- /* clear scan request, because the FW abort can cause a second call */
+- /* to this functon and might cause a double cfg80211_scan_done */
+- scan_request = cfg->scan_request;
+- cfg->scan_request = NULL;
+-
+- if (timer_pending(&cfg->escan_timeout))
+- del_timer_sync(&cfg->escan_timeout);
+-
+- if (fw_abort) {
+- /* Do a scan abort to stop the driver's scan engine */
+- brcmf_dbg(SCAN, "ABORT scan in firmware\n");
+- memset(&params_le, 0, sizeof(params_le));
+- memset(params_le.bssid, 0xFF, ETH_ALEN);
+- params_le.bss_type = DOT11_BSSTYPE_ANY;
+- params_le.scan_type = 0;
+- params_le.channel_num = cpu_to_le32(1);
+- params_le.nprobes = cpu_to_le32(1);
+- params_le.active_time = cpu_to_le32(-1);
+- params_le.passive_time = cpu_to_le32(-1);
+- params_le.home_time = cpu_to_le32(-1);
+- /* Scan is aborted by setting channel_list[0] to -1 */
+- params_le.channel_list[0] = cpu_to_le16(-1);
+- /* E-Scan (or anyother type) can be aborted by SCAN */
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SCAN,
+- &params_le, sizeof(params_le));
+- if (err)
+- brcmf_err("Scan abort failed\n");
+- }
+- /*
+- * e-scan can be initiated by scheduled scan
+- * which takes precedence.
+- */
+- if (cfg->sched_escan) {
+- brcmf_dbg(SCAN, "scheduled scan completed\n");
+- cfg->sched_escan = false;
+- if (!aborted)
+- cfg80211_sched_scan_results(cfg_to_wiphy(cfg));
+- brcmf_set_mpc(ifp, 1);
+- } else if (scan_request) {
+- brcmf_dbg(SCAN, "ESCAN Completed scan: %s\n",
+- aborted ? "Aborted" : "Done");
+- cfg80211_scan_done(scan_request, aborted);
+- brcmf_set_mpc(ifp, 1);
+- }
+- if (!test_and_clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status))
+- brcmf_dbg(SCAN, "Scan complete, probably P2P scan\n");
+-
+- return err;
+-}
+-
+-static
+-int brcmf_cfg80211_del_iface(struct wiphy *wiphy, struct wireless_dev *wdev)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
+- struct net_device *ndev = wdev->netdev;
+-
+- /* vif event pending in firmware */
+- if (brcmf_cfg80211_vif_event_armed(cfg))
+- return -EBUSY;
+-
+- if (ndev) {
+- if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status) &&
+- cfg->escan_info.ifp == netdev_priv(ndev))
+- brcmf_notify_escan_complete(cfg, netdev_priv(ndev),
+- true, true);
+-
+- brcmf_fil_iovar_int_set(netdev_priv(ndev), "mpc", 1);
+- }
+-
+- switch (wdev->iftype) {
+- case NL80211_IFTYPE_ADHOC:
+- case NL80211_IFTYPE_STATION:
+- case NL80211_IFTYPE_AP:
+- case NL80211_IFTYPE_AP_VLAN:
+- case NL80211_IFTYPE_WDS:
+- case NL80211_IFTYPE_MONITOR:
+- case NL80211_IFTYPE_MESH_POINT:
+- return -EOPNOTSUPP;
+- case NL80211_IFTYPE_P2P_CLIENT:
+- case NL80211_IFTYPE_P2P_GO:
+- case NL80211_IFTYPE_P2P_DEVICE:
+- return brcmf_p2p_del_vif(wiphy, wdev);
+- case NL80211_IFTYPE_UNSPECIFIED:
+- default:
+- return -EINVAL;
+- }
+- return -EOPNOTSUPP;
+-}
+-
+-static s32
+-brcmf_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
+- enum nl80211_iftype type, u32 *flags,
+- struct vif_params *params)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_vif *vif = ifp->vif;
+- s32 infra = 0;
+- s32 ap = 0;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter, ndev=%p, type=%d\n", ndev, type);
+-
+- switch (type) {
+- case NL80211_IFTYPE_MONITOR:
+- case NL80211_IFTYPE_WDS:
+- brcmf_err("type (%d) : currently we do not support this type\n",
+- type);
+- return -EOPNOTSUPP;
+- case NL80211_IFTYPE_ADHOC:
+- vif->mode = WL_MODE_IBSS;
+- infra = 0;
+- break;
+- case NL80211_IFTYPE_STATION:
+- /* Ignore change for p2p IF. Unclear why supplicant does this */
+- if ((vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) ||
+- (vif->wdev.iftype == NL80211_IFTYPE_P2P_GO)) {
+- brcmf_dbg(TRACE, "Ignoring cmd for p2p if\n");
+- /* WAR: It is unexpected to get a change of VIF for P2P
+- * IF, but it happens. The request can not be handled
+- * but returning EPERM causes a crash. Returning 0
+- * without setting ieee80211_ptr->iftype causes trace
+- * (WARN_ON) but it works with wpa_supplicant
+- */
+- return 0;
+- }
+- vif->mode = WL_MODE_BSS;
+- infra = 1;
+- break;
+- case NL80211_IFTYPE_AP:
+- case NL80211_IFTYPE_P2P_GO:
+- vif->mode = WL_MODE_AP;
+- ap = 1;
+- break;
+- default:
+- err = -EINVAL;
+- goto done;
+- }
+-
+- if (ap) {
+- if (type == NL80211_IFTYPE_P2P_GO) {
+- brcmf_dbg(INFO, "IF Type = P2P GO\n");
+- err = brcmf_p2p_ifchange(cfg, BRCMF_FIL_P2P_IF_GO);
+- }
+- if (!err) {
+- set_bit(BRCMF_VIF_STATUS_AP_CREATING, &vif->sme_state);
+- brcmf_dbg(INFO, "IF Type = AP\n");
+- }
+- } else {
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_INFRA, infra);
+- if (err) {
+- brcmf_err("WLC_SET_INFRA error (%d)\n", err);
+- err = -EAGAIN;
+- goto done;
+- }
+- brcmf_dbg(INFO, "IF Type = %s\n", (vif->mode == WL_MODE_IBSS) ?
+- "Adhoc" : "Infra");
+- }
+- ndev->ieee80211_ptr->iftype = type;
+-
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+-
+- return err;
+-}
+-
+-static void brcmf_escan_prep(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_scan_params_le *params_le,
+- struct cfg80211_scan_request *request)
+-{
+- u32 n_ssids;
+- u32 n_channels;
+- s32 i;
+- s32 offset;
+- u16 chanspec;
+- char *ptr;
+- struct brcmf_ssid_le ssid_le;
+-
+- memset(params_le->bssid, 0xFF, ETH_ALEN);
+- params_le->bss_type = DOT11_BSSTYPE_ANY;
+- params_le->scan_type = 0;
+- params_le->channel_num = 0;
+- params_le->nprobes = cpu_to_le32(-1);
+- params_le->active_time = cpu_to_le32(-1);
+- params_le->passive_time = cpu_to_le32(-1);
+- params_le->home_time = cpu_to_le32(-1);
+- memset(&params_le->ssid_le, 0, sizeof(params_le->ssid_le));
+-
+- /* if request is null exit so it will be all channel broadcast scan */
+- if (!request)
+- return;
+-
+- n_ssids = request->n_ssids;
+- n_channels = request->n_channels;
+- /* Copy channel array if applicable */
+- brcmf_dbg(SCAN, "### List of channelspecs to scan ### %d\n",
+- n_channels);
+- if (n_channels > 0) {
+- for (i = 0; i < n_channels; i++) {
+- chanspec = channel_to_chanspec(&cfg->d11inf,
+- request->channels[i]);
+- brcmf_dbg(SCAN, "Chan : %d, Channel spec: %x\n",
+- request->channels[i]->hw_value, chanspec);
+- params_le->channel_list[i] = cpu_to_le16(chanspec);
+- }
+- } else {
+- brcmf_dbg(SCAN, "Scanning all channels\n");
+- }
+- /* Copy ssid array if applicable */
+- brcmf_dbg(SCAN, "### List of SSIDs to scan ### %d\n", n_ssids);
+- if (n_ssids > 0) {
+- offset = offsetof(struct brcmf_scan_params_le, channel_list) +
+- n_channels * sizeof(u16);
+- offset = roundup(offset, sizeof(u32));
+- ptr = (char *)params_le + offset;
+- for (i = 0; i < n_ssids; i++) {
+- memset(&ssid_le, 0, sizeof(ssid_le));
+- ssid_le.SSID_len =
+- cpu_to_le32(request->ssids[i].ssid_len);
+- memcpy(ssid_le.SSID, request->ssids[i].ssid,
+- request->ssids[i].ssid_len);
+- if (!ssid_le.SSID_len)
+- brcmf_dbg(SCAN, "%d: Broadcast scan\n", i);
+- else
+- brcmf_dbg(SCAN, "%d: scan for %s size =%d\n",
+- i, ssid_le.SSID, ssid_le.SSID_len);
+- memcpy(ptr, &ssid_le, sizeof(ssid_le));
+- ptr += sizeof(ssid_le);
+- }
+- } else {
+- brcmf_dbg(SCAN, "Broadcast scan %p\n", request->ssids);
+- if ((request->ssids) && request->ssids->ssid_len) {
+- brcmf_dbg(SCAN, "SSID %s len=%d\n",
+- params_le->ssid_le.SSID,
+- request->ssids->ssid_len);
+- params_le->ssid_le.SSID_len =
+- cpu_to_le32(request->ssids->ssid_len);
+- memcpy(&params_le->ssid_le.SSID, request->ssids->ssid,
+- request->ssids->ssid_len);
+- }
+- }
+- /* Adding mask to channel numbers */
+- params_le->channel_num =
+- cpu_to_le32((n_ssids << BRCMF_SCAN_PARAMS_NSSID_SHIFT) |
+- (n_channels & BRCMF_SCAN_PARAMS_COUNT_MASK));
+-}
+-
+-static s32
+-brcmf_run_escan(struct brcmf_cfg80211_info *cfg, struct brcmf_if *ifp,
+- struct cfg80211_scan_request *request, u16 action)
+-{
+- s32 params_size = BRCMF_SCAN_PARAMS_FIXED_SIZE +
+- offsetof(struct brcmf_escan_params_le, params_le);
+- struct brcmf_escan_params_le *params;
+- s32 err = 0;
+-
+- brcmf_dbg(SCAN, "E-SCAN START\n");
+-
+- if (request != NULL) {
+- /* Allocate space for populating ssids in struct */
+- params_size += sizeof(u32) * ((request->n_channels + 1) / 2);
+-
+- /* Allocate space for populating ssids in struct */
+- params_size += sizeof(struct brcmf_ssid) * request->n_ssids;
+- }
+-
+- params = kzalloc(params_size, GFP_KERNEL);
+- if (!params) {
+- err = -ENOMEM;
+- goto exit;
+- }
+- BUG_ON(params_size + sizeof("escan") >= BRCMF_DCMD_MEDLEN);
+- brcmf_escan_prep(cfg, &params->params_le, request);
+- params->version = cpu_to_le32(BRCMF_ESCAN_REQ_VERSION);
+- params->action = cpu_to_le16(action);
+- params->sync_id = cpu_to_le16(0x1234);
+-
+- err = brcmf_fil_iovar_data_set(ifp, "escan", params, params_size);
+- if (err) {
+- if (err == -EBUSY)
+- brcmf_dbg(INFO, "system busy : escan canceled\n");
+- else
+- brcmf_err("error (%d)\n", err);
+- }
+-
+- kfree(params);
+-exit:
+- return err;
+-}
+-
+-static s32
+-brcmf_do_escan(struct brcmf_cfg80211_info *cfg, struct wiphy *wiphy,
+- struct brcmf_if *ifp, struct cfg80211_scan_request *request)
+-{
+- s32 err;
+- u32 passive_scan;
+- struct brcmf_scan_results *results;
+- struct escan_info *escan = &cfg->escan_info;
+-
+- brcmf_dbg(SCAN, "Enter\n");
+- escan->ifp = ifp;
+- escan->wiphy = wiphy;
+- escan->escan_state = WL_ESCAN_STATE_SCANNING;
+- passive_scan = cfg->active_scan ? 0 : 1;
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PASSIVE_SCAN,
+- passive_scan);
+- if (err) {
+- brcmf_err("error (%d)\n", err);
+- return err;
+- }
+- brcmf_set_mpc(ifp, 0);
+- results = (struct brcmf_scan_results *)cfg->escan_info.escan_buf;
+- results->version = 0;
+- results->count = 0;
+- results->buflen = WL_ESCAN_RESULTS_FIXED_SIZE;
+-
+- err = escan->run(cfg, ifp, request, WL_ESCAN_ACTION_START);
+- if (err)
+- brcmf_set_mpc(ifp, 1);
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_escan(struct wiphy *wiphy, struct brcmf_cfg80211_vif *vif,
+- struct cfg80211_scan_request *request,
+- struct cfg80211_ssid *this_ssid)
+-{
+- struct brcmf_if *ifp = vif->ifp;
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct cfg80211_ssid *ssids;
+- struct brcmf_cfg80211_scan_req *sr = &cfg->scan_req_int;
+- u32 passive_scan;
+- bool escan_req;
+- bool spec_scan;
+- s32 err;
+- u32 SSID_len;
+-
+- brcmf_dbg(SCAN, "START ESCAN\n");
+-
+- if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
+- brcmf_err("Scanning already: status (%lu)\n", cfg->scan_status);
+- return -EAGAIN;
+- }
+- if (test_bit(BRCMF_SCAN_STATUS_ABORT, &cfg->scan_status)) {
+- brcmf_err("Scanning being aborted: status (%lu)\n",
+- cfg->scan_status);
+- return -EAGAIN;
+- }
+- if (test_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status)) {
+- brcmf_err("Scanning suppressed: status (%lu)\n",
+- cfg->scan_status);
+- return -EAGAIN;
+- }
+- if (test_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state)) {
+- brcmf_err("Connecting: status (%lu)\n", ifp->vif->sme_state);
+- return -EAGAIN;
+- }
+-
+- /* If scan req comes for p2p0, send it over primary I/F */
+- if (vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif)
+- vif = cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif;
+-
+- /* Arm scan timeout timer */
+- mod_timer(&cfg->escan_timeout, jiffies +
+- WL_ESCAN_TIMER_INTERVAL_MS * HZ / 1000);
+-
+- escan_req = false;
+- if (request) {
+- /* scan bss */
+- ssids = request->ssids;
+- escan_req = true;
+- } else {
+- /* scan in ibss */
+- /* we don't do escan in ibss */
+- ssids = this_ssid;
+- }
+-
+- cfg->scan_request = request;
+- set_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
+- if (escan_req) {
+- cfg->escan_info.run = brcmf_run_escan;
+- err = brcmf_p2p_scan_prep(wiphy, request, vif);
+- if (err)
+- goto scan_out;
+-
+- err = brcmf_do_escan(cfg, wiphy, vif->ifp, request);
+- if (err)
+- goto scan_out;
+- } else {
+- brcmf_dbg(SCAN, "ssid \"%s\", ssid_len (%d)\n",
+- ssids->ssid, ssids->ssid_len);
+- memset(&sr->ssid_le, 0, sizeof(sr->ssid_le));
+- SSID_len = min_t(u8, sizeof(sr->ssid_le.SSID), ssids->ssid_len);
+- sr->ssid_le.SSID_len = cpu_to_le32(0);
+- spec_scan = false;
+- if (SSID_len) {
+- memcpy(sr->ssid_le.SSID, ssids->ssid, SSID_len);
+- sr->ssid_le.SSID_len = cpu_to_le32(SSID_len);
+- spec_scan = true;
+- } else
+- brcmf_dbg(SCAN, "Broadcast scan\n");
+-
+- passive_scan = cfg->active_scan ? 0 : 1;
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PASSIVE_SCAN,
+- passive_scan);
+- if (err) {
+- brcmf_err("WLC_SET_PASSIVE_SCAN error (%d)\n", err);
+- goto scan_out;
+- }
+- brcmf_set_mpc(ifp, 0);
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SCAN,
+- &sr->ssid_le, sizeof(sr->ssid_le));
+- if (err) {
+- if (err == -EBUSY)
+- brcmf_dbg(INFO, "BUSY: scan for \"%s\" canceled\n",
+- sr->ssid_le.SSID);
+- else
+- brcmf_err("WLC_SCAN error (%d)\n", err);
+-
+- brcmf_set_mpc(ifp, 1);
+- goto scan_out;
+- }
+- }
+-
+- return 0;
+-
+-scan_out:
+- clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
+- if (timer_pending(&cfg->escan_timeout))
+- del_timer_sync(&cfg->escan_timeout);
+- cfg->scan_request = NULL;
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_scan(struct wiphy *wiphy, struct cfg80211_scan_request *request)
+-{
+- struct brcmf_cfg80211_vif *vif;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- vif = container_of(request->wdev, struct brcmf_cfg80211_vif, wdev);
+- if (!check_vif_up(vif))
+- return -EIO;
+-
+- err = brcmf_cfg80211_escan(wiphy, vif, request, NULL);
+-
+- if (err)
+- brcmf_err("scan error (%d)\n", err);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32 brcmf_set_rts(struct net_device *ndev, u32 rts_threshold)
+-{
+- s32 err = 0;
+-
+- err = brcmf_fil_iovar_int_set(netdev_priv(ndev), "rtsthresh",
+- rts_threshold);
+- if (err)
+- brcmf_err("Error (%d)\n", err);
+-
+- return err;
+-}
+-
+-static s32 brcmf_set_frag(struct net_device *ndev, u32 frag_threshold)
+-{
+- s32 err = 0;
+-
+- err = brcmf_fil_iovar_int_set(netdev_priv(ndev), "fragthresh",
+- frag_threshold);
+- if (err)
+- brcmf_err("Error (%d)\n", err);
+-
+- return err;
+-}
+-
+-static s32 brcmf_set_retry(struct net_device *ndev, u32 retry, bool l)
+-{
+- s32 err = 0;
+- u32 cmd = (l ? BRCMF_C_SET_LRL : BRCMF_C_SET_SRL);
+-
+- err = brcmf_fil_cmd_int_set(netdev_priv(ndev), cmd, retry);
+- if (err) {
+- brcmf_err("cmd (%d) , error (%d)\n", cmd, err);
+- return err;
+- }
+- return err;
+-}
+-
+-static s32 brcmf_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct net_device *ndev = cfg_to_ndev(cfg);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
+- (cfg->conf->rts_threshold != wiphy->rts_threshold)) {
+- cfg->conf->rts_threshold = wiphy->rts_threshold;
+- err = brcmf_set_rts(ndev, cfg->conf->rts_threshold);
+- if (!err)
+- goto done;
+- }
+- if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
+- (cfg->conf->frag_threshold != wiphy->frag_threshold)) {
+- cfg->conf->frag_threshold = wiphy->frag_threshold;
+- err = brcmf_set_frag(ndev, cfg->conf->frag_threshold);
+- if (!err)
+- goto done;
+- }
+- if (changed & WIPHY_PARAM_RETRY_LONG
+- && (cfg->conf->retry_long != wiphy->retry_long)) {
+- cfg->conf->retry_long = wiphy->retry_long;
+- err = brcmf_set_retry(ndev, cfg->conf->retry_long, true);
+- if (!err)
+- goto done;
+- }
+- if (changed & WIPHY_PARAM_RETRY_SHORT
+- && (cfg->conf->retry_short != wiphy->retry_short)) {
+- cfg->conf->retry_short = wiphy->retry_short;
+- err = brcmf_set_retry(ndev, cfg->conf->retry_short, false);
+- if (!err)
+- goto done;
+- }
+-
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static void brcmf_init_prof(struct brcmf_cfg80211_profile *prof)
+-{
+- memset(prof, 0, sizeof(*prof));
+-}
+-
+-static void brcmf_link_down(struct brcmf_cfg80211_vif *vif)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(vif->wdev.wiphy);
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (test_bit(BRCMF_VIF_STATUS_CONNECTED, &vif->sme_state)) {
+- brcmf_dbg(INFO, "Call WLC_DISASSOC to stop excess roaming\n ");
+- err = brcmf_fil_cmd_data_set(vif->ifp,
+- BRCMF_C_DISASSOC, NULL, 0);
+- if (err) {
+- brcmf_err("WLC_DISASSOC failed (%d)\n", err);
+- }
+- clear_bit(BRCMF_VIF_STATUS_CONNECTED, &vif->sme_state);
+- cfg80211_disconnected(vif->wdev.netdev, 0, NULL, 0, GFP_KERNEL);
+-
+- }
+- clear_bit(BRCMF_VIF_STATUS_CONNECTING, &vif->sme_state);
+- clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
+- brcmf_btcoex_set_mode(vif, BRCMF_BTCOEX_ENABLED, 0);
+- brcmf_dbg(TRACE, "Exit\n");
+-}
+-
+-static s32
+-brcmf_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *ndev,
+- struct cfg80211_ibss_params *params)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- struct brcmf_join_params join_params;
+- size_t join_params_size = 0;
+- s32 err = 0;
+- s32 wsec = 0;
+- s32 bcnprd;
+- u16 chanspec;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- if (params->ssid)
+- brcmf_dbg(CONN, "SSID: %s\n", params->ssid);
+- else {
+- brcmf_dbg(CONN, "SSID: NULL, Not supported\n");
+- return -EOPNOTSUPP;
+- }
+-
+- set_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
+-
+- if (params->bssid)
+- brcmf_dbg(CONN, "BSSID: %pM\n", params->bssid);
+- else
+- brcmf_dbg(CONN, "No BSSID specified\n");
+-
+- if (params->chandef.chan)
+- brcmf_dbg(CONN, "channel: %d\n",
+- params->chandef.chan->center_freq);
+- else
+- brcmf_dbg(CONN, "no channel specified\n");
+-
+- if (params->channel_fixed)
+- brcmf_dbg(CONN, "fixed channel required\n");
+- else
+- brcmf_dbg(CONN, "no fixed channel required\n");
+-
+- if (params->ie && params->ie_len)
+- brcmf_dbg(CONN, "ie len: %d\n", params->ie_len);
+- else
+- brcmf_dbg(CONN, "no ie specified\n");
+-
+- if (params->beacon_interval)
+- brcmf_dbg(CONN, "beacon interval: %d\n",
+- params->beacon_interval);
+- else
+- brcmf_dbg(CONN, "no beacon interval specified\n");
+-
+- if (params->basic_rates)
+- brcmf_dbg(CONN, "basic rates: %08X\n", params->basic_rates);
+- else
+- brcmf_dbg(CONN, "no basic rates specified\n");
+-
+- if (params->privacy)
+- brcmf_dbg(CONN, "privacy required\n");
+- else
+- brcmf_dbg(CONN, "no privacy required\n");
+-
+- /* Configure Privacy for starter */
+- if (params->privacy)
+- wsec |= WEP_ENABLED;
+-
+- err = brcmf_fil_iovar_int_set(ifp, "wsec", wsec);
+- if (err) {
+- brcmf_err("wsec failed (%d)\n", err);
+- goto done;
+- }
+-
+- /* Configure Beacon Interval for starter */
+- if (params->beacon_interval)
+- bcnprd = params->beacon_interval;
+- else
+- bcnprd = 100;
+-
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_BCNPRD, bcnprd);
+- if (err) {
+- brcmf_err("WLC_SET_BCNPRD failed (%d)\n", err);
+- goto done;
+- }
+-
+- /* Configure required join parameter */
+- memset(&join_params, 0, sizeof(struct brcmf_join_params));
+-
+- /* SSID */
+- profile->ssid.SSID_len = min_t(u32, params->ssid_len, 32);
+- memcpy(profile->ssid.SSID, params->ssid, profile->ssid.SSID_len);
+- memcpy(join_params.ssid_le.SSID, params->ssid, profile->ssid.SSID_len);
+- join_params.ssid_le.SSID_len = cpu_to_le32(profile->ssid.SSID_len);
+- join_params_size = sizeof(join_params.ssid_le);
+-
+- /* BSSID */
+- if (params->bssid) {
+- memcpy(join_params.params_le.bssid, params->bssid, ETH_ALEN);
+- join_params_size = sizeof(join_params.ssid_le) +
+- BRCMF_ASSOC_PARAMS_FIXED_SIZE;
+- memcpy(profile->bssid, params->bssid, ETH_ALEN);
+- } else {
+- memset(join_params.params_le.bssid, 0xFF, ETH_ALEN);
+- memset(profile->bssid, 0, ETH_ALEN);
+- }
+-
+- /* Channel */
+- if (params->chandef.chan) {
+- u32 target_channel;
+-
+- cfg->channel =
+- ieee80211_frequency_to_channel(
+- params->chandef.chan->center_freq);
+- if (params->channel_fixed) {
+- /* adding chanspec */
+- chanspec = channel_to_chanspec(&cfg->d11inf,
+- params->chandef.chan);
+- join_params.params_le.chanspec_list[0] =
+- cpu_to_le16(chanspec);
+- join_params.params_le.chanspec_num = cpu_to_le32(1);
+- join_params_size += sizeof(join_params.params_le);
+- }
+-
+- /* set channel for starter */
+- target_channel = cfg->channel;
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_CHANNEL,
+- target_channel);
+- if (err) {
+- brcmf_err("WLC_SET_CHANNEL failed (%d)\n", err);
+- goto done;
+- }
+- } else
+- cfg->channel = 0;
+-
+- cfg->ibss_starter = false;
+-
+-
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
+- &join_params, join_params_size);
+- if (err) {
+- brcmf_err("WLC_SET_SSID failed (%d)\n", err);
+- goto done;
+- }
+-
+-done:
+- if (err)
+- clear_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_leave_ibss(struct wiphy *wiphy, struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- brcmf_link_down(ifp->vif);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+-
+- return err;
+-}
+-
+-static s32 brcmf_set_wpa_version(struct net_device *ndev,
+- struct cfg80211_connect_params *sme)
+-{
+- struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
+- struct brcmf_cfg80211_security *sec;
+- s32 val = 0;
+- s32 err = 0;
+-
+- if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_1)
+- val = WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED;
+- else if (sme->crypto.wpa_versions & NL80211_WPA_VERSION_2)
+- val = WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED;
+- else
+- val = WPA_AUTH_DISABLED;
+- brcmf_dbg(CONN, "setting wpa_auth to 0x%0x\n", val);
+- err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "wpa_auth", val);
+- if (err) {
+- brcmf_err("set wpa_auth failed (%d)\n", err);
+- return err;
+- }
+- sec = &profile->sec;
+- sec->wpa_versions = sme->crypto.wpa_versions;
+- return err;
+-}
+-
+-static s32 brcmf_set_auth_type(struct net_device *ndev,
+- struct cfg80211_connect_params *sme)
+-{
+- struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
+- struct brcmf_cfg80211_security *sec;
+- s32 val = 0;
+- s32 err = 0;
+-
+- switch (sme->auth_type) {
+- case NL80211_AUTHTYPE_OPEN_SYSTEM:
+- val = 0;
+- brcmf_dbg(CONN, "open system\n");
+- break;
+- case NL80211_AUTHTYPE_SHARED_KEY:
+- val = 1;
+- brcmf_dbg(CONN, "shared key\n");
+- break;
+- case NL80211_AUTHTYPE_AUTOMATIC:
+- val = 2;
+- brcmf_dbg(CONN, "automatic\n");
+- break;
+- case NL80211_AUTHTYPE_NETWORK_EAP:
+- brcmf_dbg(CONN, "network eap\n");
+- default:
+- val = 2;
+- brcmf_err("invalid auth type (%d)\n", sme->auth_type);
+- break;
+- }
+-
+- err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "auth", val);
+- if (err) {
+- brcmf_err("set auth failed (%d)\n", err);
+- return err;
+- }
+- sec = &profile->sec;
+- sec->auth_type = sme->auth_type;
+- return err;
+-}
+-
+-static s32
+-brcmf_set_set_cipher(struct net_device *ndev,
+- struct cfg80211_connect_params *sme)
+-{
+- struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
+- struct brcmf_cfg80211_security *sec;
+- s32 pval = 0;
+- s32 gval = 0;
+- s32 err = 0;
+-
+- if (sme->crypto.n_ciphers_pairwise) {
+- switch (sme->crypto.ciphers_pairwise[0]) {
+- case WLAN_CIPHER_SUITE_WEP40:
+- case WLAN_CIPHER_SUITE_WEP104:
+- pval = WEP_ENABLED;
+- break;
+- case WLAN_CIPHER_SUITE_TKIP:
+- pval = TKIP_ENABLED;
+- break;
+- case WLAN_CIPHER_SUITE_CCMP:
+- pval = AES_ENABLED;
+- break;
+- case WLAN_CIPHER_SUITE_AES_CMAC:
+- pval = AES_ENABLED;
+- break;
+- default:
+- brcmf_err("invalid cipher pairwise (%d)\n",
+- sme->crypto.ciphers_pairwise[0]);
+- return -EINVAL;
+- }
+- }
+- if (sme->crypto.cipher_group) {
+- switch (sme->crypto.cipher_group) {
+- case WLAN_CIPHER_SUITE_WEP40:
+- case WLAN_CIPHER_SUITE_WEP104:
+- gval = WEP_ENABLED;
+- break;
+- case WLAN_CIPHER_SUITE_TKIP:
+- gval = TKIP_ENABLED;
+- break;
+- case WLAN_CIPHER_SUITE_CCMP:
+- gval = AES_ENABLED;
+- break;
+- case WLAN_CIPHER_SUITE_AES_CMAC:
+- gval = AES_ENABLED;
+- break;
+- default:
+- brcmf_err("invalid cipher group (%d)\n",
+- sme->crypto.cipher_group);
+- return -EINVAL;
+- }
+- }
+-
+- brcmf_dbg(CONN, "pval (%d) gval (%d)\n", pval, gval);
+- /* In case of privacy, but no security and WPS then simulate */
+- /* setting AES. WPS-2.0 allows no security */
+- if (brcmf_find_wpsie(sme->ie, sme->ie_len) && !pval && !gval &&
+- sme->privacy)
+- pval = AES_ENABLED;
+- err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "wsec", pval | gval);
+- if (err) {
+- brcmf_err("error (%d)\n", err);
+- return err;
+- }
+-
+- sec = &profile->sec;
+- sec->cipher_pairwise = sme->crypto.ciphers_pairwise[0];
+- sec->cipher_group = sme->crypto.cipher_group;
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_set_key_mgmt(struct net_device *ndev, struct cfg80211_connect_params *sme)
+-{
+- struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
+- struct brcmf_cfg80211_security *sec;
+- s32 val = 0;
+- s32 err = 0;
+-
+- if (sme->crypto.n_akm_suites) {
+- err = brcmf_fil_bsscfg_int_get(netdev_priv(ndev),
+- "wpa_auth", &val);
+- if (err) {
+- brcmf_err("could not get wpa_auth (%d)\n", err);
+- return err;
+- }
+- if (val & (WPA_AUTH_PSK | WPA_AUTH_UNSPECIFIED)) {
+- switch (sme->crypto.akm_suites[0]) {
+- case WLAN_AKM_SUITE_8021X:
+- val = WPA_AUTH_UNSPECIFIED;
+- break;
+- case WLAN_AKM_SUITE_PSK:
+- val = WPA_AUTH_PSK;
+- break;
+- default:
+- brcmf_err("invalid cipher group (%d)\n",
+- sme->crypto.cipher_group);
+- return -EINVAL;
+- }
+- } else if (val & (WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED)) {
+- switch (sme->crypto.akm_suites[0]) {
+- case WLAN_AKM_SUITE_8021X:
+- val = WPA2_AUTH_UNSPECIFIED;
+- break;
+- case WLAN_AKM_SUITE_PSK:
+- val = WPA2_AUTH_PSK;
+- break;
+- default:
+- brcmf_err("invalid cipher group (%d)\n",
+- sme->crypto.cipher_group);
+- return -EINVAL;
+- }
+- }
+-
+- brcmf_dbg(CONN, "setting wpa_auth to %d\n", val);
+- err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev),
+- "wpa_auth", val);
+- if (err) {
+- brcmf_err("could not set wpa_auth (%d)\n", err);
+- return err;
+- }
+- }
+- sec = &profile->sec;
+- sec->wpa_auth = sme->crypto.akm_suites[0];
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_set_sharedkey(struct net_device *ndev,
+- struct cfg80211_connect_params *sme)
+-{
+- struct brcmf_cfg80211_profile *profile = ndev_to_prof(ndev);
+- struct brcmf_cfg80211_security *sec;
+- struct brcmf_wsec_key key;
+- s32 val;
+- s32 err = 0;
+-
+- brcmf_dbg(CONN, "key len (%d)\n", sme->key_len);
+-
+- if (sme->key_len == 0)
+- return 0;
+-
+- sec = &profile->sec;
+- brcmf_dbg(CONN, "wpa_versions 0x%x cipher_pairwise 0x%x\n",
+- sec->wpa_versions, sec->cipher_pairwise);
+-
+- if (sec->wpa_versions & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2))
+- return 0;
+-
+- if (!(sec->cipher_pairwise &
+- (WLAN_CIPHER_SUITE_WEP40 | WLAN_CIPHER_SUITE_WEP104)))
+- return 0;
+-
+- memset(&key, 0, sizeof(key));
+- key.len = (u32) sme->key_len;
+- key.index = (u32) sme->key_idx;
+- if (key.len > sizeof(key.data)) {
+- brcmf_err("Too long key length (%u)\n", key.len);
+- return -EINVAL;
+- }
+- memcpy(key.data, sme->key, key.len);
+- key.flags = BRCMF_PRIMARY_KEY;
+- switch (sec->cipher_pairwise) {
+- case WLAN_CIPHER_SUITE_WEP40:
+- key.algo = CRYPTO_ALGO_WEP1;
+- break;
+- case WLAN_CIPHER_SUITE_WEP104:
+- key.algo = CRYPTO_ALGO_WEP128;
+- break;
+- default:
+- brcmf_err("Invalid algorithm (%d)\n",
+- sme->crypto.ciphers_pairwise[0]);
+- return -EINVAL;
+- }
+- /* Set the new key/index */
+- brcmf_dbg(CONN, "key length (%d) key index (%d) algo (%d)\n",
+- key.len, key.index, key.algo);
+- brcmf_dbg(CONN, "key \"%s\"\n", key.data);
+- err = send_key_to_dongle(ndev, &key);
+- if (err)
+- return err;
+-
+- if (sec->auth_type == NL80211_AUTHTYPE_SHARED_KEY) {
+- brcmf_dbg(CONN, "set auth_type to shared key\n");
+- val = WL_AUTH_SHARED_KEY; /* shared key */
+- err = brcmf_fil_bsscfg_int_set(netdev_priv(ndev), "auth", val);
+- if (err)
+- brcmf_err("set auth failed (%d)\n", err);
+- }
+- return err;
+-}
+-
+-static
+-enum nl80211_auth_type brcmf_war_auth_type(struct brcmf_if *ifp,
+- enum nl80211_auth_type type)
+-{
+- u32 ci;
+- if (type == NL80211_AUTHTYPE_AUTOMATIC) {
+- /* shift to ignore chip revision */
+- ci = brcmf_get_chip_info(ifp) >> 4;
+- switch (ci) {
+- case 43236:
+- brcmf_dbg(CONN, "43236 WAR: use OPEN instead of AUTO\n");
+- return NL80211_AUTHTYPE_OPEN_SYSTEM;
+- default:
+- break;
+- }
+- }
+- return type;
+-}
+-
+-static s32
+-brcmf_cfg80211_connect(struct wiphy *wiphy, struct net_device *ndev,
+- struct cfg80211_connect_params *sme)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- struct ieee80211_channel *chan = sme->channel;
+- struct brcmf_join_params join_params;
+- size_t join_params_size;
+- struct brcmf_tlv *rsn_ie;
+- struct brcmf_vs_tlv *wpa_ie;
+- void *ie;
+- u32 ie_len;
+- struct brcmf_ext_join_params_le *ext_join_params;
+- u16 chanspec;
+-
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- if (!sme->ssid) {
+- brcmf_err("Invalid ssid\n");
+- return -EOPNOTSUPP;
+- }
+-
+- if (ifp->vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif) {
+- /* A normal (non P2P) connection request setup. */
+- ie = NULL;
+- ie_len = 0;
+- /* find the WPA_IE */
+- wpa_ie = brcmf_find_wpaie((u8 *)sme->ie, sme->ie_len);
+- if (wpa_ie) {
+- ie = wpa_ie;
+- ie_len = wpa_ie->len + TLV_HDR_LEN;
+- } else {
+- /* find the RSN_IE */
+- rsn_ie = brcmf_parse_tlvs((u8 *)sme->ie, sme->ie_len,
+- WLAN_EID_RSN);
+- if (rsn_ie) {
+- ie = rsn_ie;
+- ie_len = rsn_ie->len + TLV_HDR_LEN;
+- }
+- }
+- brcmf_fil_iovar_data_set(ifp, "wpaie", ie, ie_len);
+- }
+-
+- err = brcmf_vif_set_mgmt_ie(ifp->vif, BRCMF_VNDR_IE_ASSOCREQ_FLAG,
+- sme->ie, sme->ie_len);
+- if (err)
+- brcmf_err("Set Assoc REQ IE Failed\n");
+- else
+- brcmf_dbg(TRACE, "Applied Vndr IEs for Assoc request\n");
+-
+- set_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
+-
+- if (chan) {
+- cfg->channel =
+- ieee80211_frequency_to_channel(chan->center_freq);
+- chanspec = channel_to_chanspec(&cfg->d11inf, chan);
+- brcmf_dbg(CONN, "channel=%d, center_req=%d, chanspec=0x%04x\n",
+- cfg->channel, chan->center_freq, chanspec);
+- } else {
+- cfg->channel = 0;
+- chanspec = 0;
+- }
+-
+- brcmf_dbg(INFO, "ie (%p), ie_len (%zd)\n", sme->ie, sme->ie_len);
+-
+- err = brcmf_set_wpa_version(ndev, sme);
+- if (err) {
+- brcmf_err("wl_set_wpa_version failed (%d)\n", err);
+- goto done;
+- }
+-
+- sme->auth_type = brcmf_war_auth_type(ifp, sme->auth_type);
+- err = brcmf_set_auth_type(ndev, sme);
+- if (err) {
+- brcmf_err("wl_set_auth_type failed (%d)\n", err);
+- goto done;
+- }
+-
+- err = brcmf_set_set_cipher(ndev, sme);
+- if (err) {
+- brcmf_err("wl_set_set_cipher failed (%d)\n", err);
+- goto done;
+- }
+-
+- err = brcmf_set_key_mgmt(ndev, sme);
+- if (err) {
+- brcmf_err("wl_set_key_mgmt failed (%d)\n", err);
+- goto done;
+- }
+-
+- err = brcmf_set_sharedkey(ndev, sme);
+- if (err) {
+- brcmf_err("brcmf_set_sharedkey failed (%d)\n", err);
+- goto done;
+- }
+-
+- profile->ssid.SSID_len = min_t(u32, (u32)sizeof(profile->ssid.SSID),
+- (u32)sme->ssid_len);
+- memcpy(&profile->ssid.SSID, sme->ssid, profile->ssid.SSID_len);
+- if (profile->ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
+- profile->ssid.SSID[profile->ssid.SSID_len] = 0;
+- brcmf_dbg(CONN, "SSID \"%s\", len (%d)\n", profile->ssid.SSID,
+- profile->ssid.SSID_len);
+- }
+-
+- /* Join with specific BSSID and cached SSID
+- * If SSID is zero join based on BSSID only
+- */
+- join_params_size = offsetof(struct brcmf_ext_join_params_le, assoc_le) +
+- offsetof(struct brcmf_assoc_params_le, chanspec_list);
+- if (cfg->channel)
+- join_params_size += sizeof(u16);
+- ext_join_params = kzalloc(join_params_size, GFP_KERNEL);
+- if (ext_join_params == NULL) {
+- err = -ENOMEM;
+- goto done;
+- }
+- ext_join_params->ssid_le.SSID_len = cpu_to_le32(profile->ssid.SSID_len);
+- memcpy(&ext_join_params->ssid_le.SSID, sme->ssid,
+- profile->ssid.SSID_len);
+- /*increase dwell time to receive probe response or detect Beacon
+- * from target AP at a noisy air only during connect command
+- */
+- ext_join_params->scan_le.active_time =
+- cpu_to_le32(BRCMF_SCAN_JOIN_ACTIVE_DWELL_TIME_MS);
+- ext_join_params->scan_le.passive_time =
+- cpu_to_le32(BRCMF_SCAN_JOIN_PASSIVE_DWELL_TIME_MS);
+- /* Set up join scan parameters */
+- ext_join_params->scan_le.scan_type = -1;
+- /* to sync with presence period of VSDB GO.
+- * Send probe request more frequently. Probe request will be stopped
+- * when it gets probe response from target AP/GO.
+- */
+- ext_join_params->scan_le.nprobes =
+- cpu_to_le32(BRCMF_SCAN_JOIN_ACTIVE_DWELL_TIME_MS /
+- BRCMF_SCAN_JOIN_PROBE_INTERVAL_MS);
+- ext_join_params->scan_le.home_time = cpu_to_le32(-1);
+-
+- if (sme->bssid)
+- memcpy(&ext_join_params->assoc_le.bssid, sme->bssid, ETH_ALEN);
+- else
+- memset(&ext_join_params->assoc_le.bssid, 0xFF, ETH_ALEN);
+-
+- if (cfg->channel) {
+- ext_join_params->assoc_le.chanspec_num = cpu_to_le32(1);
+-
+- ext_join_params->assoc_le.chanspec_list[0] =
+- cpu_to_le16(chanspec);
+- }
+-
+- err = brcmf_fil_bsscfg_data_set(ifp, "join", ext_join_params,
+- join_params_size);
+- kfree(ext_join_params);
+- if (!err)
+- /* This is it. join command worked, we are done */
+- goto done;
+-
+- /* join command failed, fallback to set ssid */
+- memset(&join_params, 0, sizeof(join_params));
+- join_params_size = sizeof(join_params.ssid_le);
+-
+- memcpy(&join_params.ssid_le.SSID, sme->ssid, profile->ssid.SSID_len);
+- join_params.ssid_le.SSID_len = cpu_to_le32(profile->ssid.SSID_len);
+-
+- if (sme->bssid)
+- memcpy(join_params.params_le.bssid, sme->bssid, ETH_ALEN);
+- else
+- memset(join_params.params_le.bssid, 0xFF, ETH_ALEN);
+-
+- if (cfg->channel) {
+- join_params.params_le.chanspec_list[0] = cpu_to_le16(chanspec);
+- join_params.params_le.chanspec_num = cpu_to_le32(1);
+- join_params_size += sizeof(join_params.params_le);
+- }
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
+- &join_params, join_params_size);
+- if (err)
+- brcmf_err("BRCMF_C_SET_SSID failed (%d)\n", err);
+-
+-done:
+- if (err)
+- clear_bit(BRCMF_VIF_STATUS_CONNECTING, &ifp->vif->sme_state);
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_disconnect(struct wiphy *wiphy, struct net_device *ndev,
+- u16 reason_code)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- struct brcmf_scb_val_le scbval;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter. Reason code = %d\n", reason_code);
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- clear_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state);
+- cfg80211_disconnected(ndev, reason_code, NULL, 0, GFP_KERNEL);
+-
+- memcpy(&scbval.ea, &profile->bssid, ETH_ALEN);
+- scbval.val = cpu_to_le32(reason_code);
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_DISASSOC,
+- &scbval, sizeof(scbval));
+- if (err)
+- brcmf_err("error (%d)\n", err);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_set_tx_power(struct wiphy *wiphy, struct wireless_dev *wdev,
+- enum nl80211_tx_power_setting type, s32 mbm)
+-{
+-
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct net_device *ndev = cfg_to_ndev(cfg);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- u16 txpwrmw;
+- s32 err = 0;
+- s32 disable = 0;
+- s32 dbm = MBM_TO_DBM(mbm);
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- switch (type) {
+- case NL80211_TX_POWER_AUTOMATIC:
+- break;
+- case NL80211_TX_POWER_LIMITED:
+- case NL80211_TX_POWER_FIXED:
+- if (dbm < 0) {
+- brcmf_err("TX_POWER_FIXED - dbm is negative\n");
+- err = -EINVAL;
+- goto done;
+- }
+- break;
+- }
+- /* Make sure radio is off or on as far as software is concerned */
+- disable = WL_RADIO_SW_DISABLE << 16;
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_RADIO, disable);
+- if (err)
+- brcmf_err("WLC_SET_RADIO error (%d)\n", err);
+-
+- if (dbm > 0xffff)
+- txpwrmw = 0xffff;
+- else
+- txpwrmw = (u16) dbm;
+- err = brcmf_fil_iovar_int_set(ifp, "qtxpower",
+- (s32)brcmf_mw_to_qdbm(txpwrmw));
+- if (err)
+- brcmf_err("qtxpower error (%d)\n", err);
+- cfg->conf->tx_power = dbm;
+-
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32 brcmf_cfg80211_get_tx_power(struct wiphy *wiphy,
+- struct wireless_dev *wdev,
+- s32 *dbm)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
+- s32 txpwrdbm;
+- u8 result;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- err = brcmf_fil_iovar_int_get(ifp, "qtxpower", &txpwrdbm);
+- if (err) {
+- brcmf_err("error (%d)\n", err);
+- goto done;
+- }
+-
+- result = (u8) (txpwrdbm & ~WL_TXPWR_OVERRIDE);
+- *dbm = (s32) brcmf_qdbm_to_mw(result);
+-
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *ndev,
+- u8 key_idx, bool unicast, bool multicast)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- u32 index;
+- u32 wsec;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- brcmf_dbg(CONN, "key index (%d)\n", key_idx);
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- err = brcmf_fil_bsscfg_int_get(ifp, "wsec", &wsec);
+- if (err) {
+- brcmf_err("WLC_GET_WSEC error (%d)\n", err);
+- goto done;
+- }
+-
+- if (wsec & WEP_ENABLED) {
+- /* Just select a new current key */
+- index = key_idx;
+- err = brcmf_fil_cmd_int_set(ifp,
+- BRCMF_C_SET_KEY_PRIMARY, index);
+- if (err)
+- brcmf_err("error (%d)\n", err);
+- }
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_add_keyext(struct wiphy *wiphy, struct net_device *ndev,
+- u8 key_idx, const u8 *mac_addr, struct key_params *params)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_wsec_key key;
+- s32 err = 0;
+- u8 keybuf[8];
+-
+- memset(&key, 0, sizeof(key));
+- key.index = (u32) key_idx;
+- /* Instead of bcast for ea address for default wep keys,
+- driver needs it to be Null */
+- if (!is_multicast_ether_addr(mac_addr))
+- memcpy((char *)&key.ea, (void *)mac_addr, ETH_ALEN);
+- key.len = (u32) params->key_len;
+- /* check for key index change */
+- if (key.len == 0) {
+- /* key delete */
+- err = send_key_to_dongle(ndev, &key);
+- if (err)
+- brcmf_err("key delete error (%d)\n", err);
+- } else {
+- if (key.len > sizeof(key.data)) {
+- brcmf_err("Invalid key length (%d)\n", key.len);
+- return -EINVAL;
+- }
+-
+- brcmf_dbg(CONN, "Setting the key index %d\n", key.index);
+- memcpy(key.data, params->key, key.len);
+-
+- if ((ifp->vif->mode != WL_MODE_AP) &&
+- (params->cipher == WLAN_CIPHER_SUITE_TKIP)) {
+- brcmf_dbg(CONN, "Swapping RX/TX MIC key\n");
+- memcpy(keybuf, &key.data[24], sizeof(keybuf));
+- memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
+- memcpy(&key.data[16], keybuf, sizeof(keybuf));
+- }
+-
+- /* if IW_ENCODE_EXT_RX_SEQ_VALID set */
+- if (params->seq && params->seq_len == 6) {
+- /* rx iv */
+- u8 *ivptr;
+- ivptr = (u8 *) params->seq;
+- key.rxiv.hi = (ivptr[5] << 24) | (ivptr[4] << 16) |
+- (ivptr[3] << 8) | ivptr[2];
+- key.rxiv.lo = (ivptr[1] << 8) | ivptr[0];
+- key.iv_initialized = true;
+- }
+-
+- switch (params->cipher) {
+- case WLAN_CIPHER_SUITE_WEP40:
+- key.algo = CRYPTO_ALGO_WEP1;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP40\n");
+- break;
+- case WLAN_CIPHER_SUITE_WEP104:
+- key.algo = CRYPTO_ALGO_WEP128;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP104\n");
+- break;
+- case WLAN_CIPHER_SUITE_TKIP:
+- key.algo = CRYPTO_ALGO_TKIP;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_TKIP\n");
+- break;
+- case WLAN_CIPHER_SUITE_AES_CMAC:
+- key.algo = CRYPTO_ALGO_AES_CCM;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_AES_CMAC\n");
+- break;
+- case WLAN_CIPHER_SUITE_CCMP:
+- key.algo = CRYPTO_ALGO_AES_CCM;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_CCMP\n");
+- break;
+- default:
+- brcmf_err("Invalid cipher (0x%x)\n", params->cipher);
+- return -EINVAL;
+- }
+- err = send_key_to_dongle(ndev, &key);
+- if (err)
+- brcmf_err("wsec_key error (%d)\n", err);
+- }
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_add_key(struct wiphy *wiphy, struct net_device *ndev,
+- u8 key_idx, bool pairwise, const u8 *mac_addr,
+- struct key_params *params)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_wsec_key key;
+- s32 val;
+- s32 wsec;
+- s32 err = 0;
+- u8 keybuf[8];
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- brcmf_dbg(CONN, "key index (%d)\n", key_idx);
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- if (mac_addr) {
+- brcmf_dbg(TRACE, "Exit");
+- return brcmf_add_keyext(wiphy, ndev, key_idx, mac_addr, params);
+- }
+- memset(&key, 0, sizeof(key));
+-
+- key.len = (u32) params->key_len;
+- key.index = (u32) key_idx;
+-
+- if (key.len > sizeof(key.data)) {
+- brcmf_err("Too long key length (%u)\n", key.len);
+- err = -EINVAL;
+- goto done;
+- }
+- memcpy(key.data, params->key, key.len);
+-
+- key.flags = BRCMF_PRIMARY_KEY;
+- switch (params->cipher) {
+- case WLAN_CIPHER_SUITE_WEP40:
+- key.algo = CRYPTO_ALGO_WEP1;
+- val = WEP_ENABLED;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP40\n");
+- break;
+- case WLAN_CIPHER_SUITE_WEP104:
+- key.algo = CRYPTO_ALGO_WEP128;
+- val = WEP_ENABLED;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP104\n");
+- break;
+- case WLAN_CIPHER_SUITE_TKIP:
+- if (ifp->vif->mode != WL_MODE_AP) {
+- brcmf_dbg(CONN, "Swapping RX/TX MIC key\n");
+- memcpy(keybuf, &key.data[24], sizeof(keybuf));
+- memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
+- memcpy(&key.data[16], keybuf, sizeof(keybuf));
+- }
+- key.algo = CRYPTO_ALGO_TKIP;
+- val = TKIP_ENABLED;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_TKIP\n");
+- break;
+- case WLAN_CIPHER_SUITE_AES_CMAC:
+- key.algo = CRYPTO_ALGO_AES_CCM;
+- val = AES_ENABLED;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_AES_CMAC\n");
+- break;
+- case WLAN_CIPHER_SUITE_CCMP:
+- key.algo = CRYPTO_ALGO_AES_CCM;
+- val = AES_ENABLED;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_CCMP\n");
+- break;
+- default:
+- brcmf_err("Invalid cipher (0x%x)\n", params->cipher);
+- err = -EINVAL;
+- goto done;
+- }
+-
+- err = send_key_to_dongle(ndev, &key);
+- if (err)
+- goto done;
+-
+- err = brcmf_fil_bsscfg_int_get(ifp, "wsec", &wsec);
+- if (err) {
+- brcmf_err("get wsec error (%d)\n", err);
+- goto done;
+- }
+- wsec |= val;
+- err = brcmf_fil_bsscfg_int_set(ifp, "wsec", wsec);
+- if (err) {
+- brcmf_err("set wsec error (%d)\n", err);
+- goto done;
+- }
+-
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
+- u8 key_idx, bool pairwise, const u8 *mac_addr)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_wsec_key key;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- if (key_idx >= DOT11_MAX_DEFAULT_KEYS) {
+- /* we ignore this key index in this case */
+- brcmf_err("invalid key index (%d)\n", key_idx);
+- return -EINVAL;
+- }
+-
+- memset(&key, 0, sizeof(key));
+-
+- key.index = (u32) key_idx;
+- key.flags = BRCMF_PRIMARY_KEY;
+- key.algo = CRYPTO_ALGO_OFF;
+-
+- brcmf_dbg(CONN, "key index (%d)\n", key_idx);
+-
+- /* Set the new key/index */
+- err = send_key_to_dongle(ndev, &key);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_get_key(struct wiphy *wiphy, struct net_device *ndev,
+- u8 key_idx, bool pairwise, const u8 *mac_addr, void *cookie,
+- void (*callback) (void *cookie, struct key_params * params))
+-{
+- struct key_params params;
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- struct brcmf_cfg80211_security *sec;
+- s32 wsec;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- brcmf_dbg(CONN, "key index (%d)\n", key_idx);
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- memset(&params, 0, sizeof(params));
+-
+- err = brcmf_fil_bsscfg_int_get(ifp, "wsec", &wsec);
+- if (err) {
+- brcmf_err("WLC_GET_WSEC error (%d)\n", err);
+- /* Ignore this error, may happen during DISASSOC */
+- err = -EAGAIN;
+- goto done;
+- }
+- if (wsec & WEP_ENABLED) {
+- sec = &profile->sec;
+- if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP40) {
+- params.cipher = WLAN_CIPHER_SUITE_WEP40;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP40\n");
+- } else if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP104) {
+- params.cipher = WLAN_CIPHER_SUITE_WEP104;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_WEP104\n");
+- }
+- } else if (wsec & TKIP_ENABLED) {
+- params.cipher = WLAN_CIPHER_SUITE_TKIP;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_TKIP\n");
+- } else if (wsec & AES_ENABLED) {
+- params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;
+- brcmf_dbg(CONN, "WLAN_CIPHER_SUITE_AES_CMAC\n");
+- } else {
+- brcmf_err("Invalid algo (0x%x)\n", wsec);
+- err = -EINVAL;
+- goto done;
+- }
+- callback(cookie, &params);
+-
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_config_default_mgmt_key(struct wiphy *wiphy,
+- struct net_device *ndev, u8 key_idx)
+-{
+- brcmf_dbg(INFO, "Not supported\n");
+-
+- return -EOPNOTSUPP;
+-}
+-
+-static s32
+-brcmf_cfg80211_get_station(struct wiphy *wiphy, struct net_device *ndev,
+- u8 *mac, struct station_info *sinfo)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- struct brcmf_scb_val_le scb_val;
+- int rssi;
+- s32 rate;
+- s32 err = 0;
+- u8 *bssid = profile->bssid;
+- struct brcmf_sta_info_le sta_info_le;
+-
+- brcmf_dbg(TRACE, "Enter, MAC %pM\n", mac);
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- if (ifp->vif->mode == WL_MODE_AP) {
+- memcpy(&sta_info_le, mac, ETH_ALEN);
+- err = brcmf_fil_iovar_data_get(ifp, "sta_info",
+- &sta_info_le,
+- sizeof(sta_info_le));
+- if (err < 0) {
+- brcmf_err("GET STA INFO failed, %d\n", err);
+- goto done;
+- }
+- sinfo->filled = STATION_INFO_INACTIVE_TIME;
+- sinfo->inactive_time = le32_to_cpu(sta_info_le.idle) * 1000;
+- if (le32_to_cpu(sta_info_le.flags) & BRCMF_STA_ASSOC) {
+- sinfo->filled |= STATION_INFO_CONNECTED_TIME;
+- sinfo->connected_time = le32_to_cpu(sta_info_le.in);
+- }
+- brcmf_dbg(TRACE, "STA idle time : %d ms, connected time :%d sec\n",
+- sinfo->inactive_time, sinfo->connected_time);
+- } else if (ifp->vif->mode == WL_MODE_BSS) {
+- if (memcmp(mac, bssid, ETH_ALEN)) {
+- brcmf_err("Wrong Mac address cfg_mac-%pM wl_bssid-%pM\n",
+- mac, bssid);
+- err = -ENOENT;
+- goto done;
+- }
+- /* Report the current tx rate */
+- err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_RATE, &rate);
+- if (err) {
+- brcmf_err("Could not get rate (%d)\n", err);
+- goto done;
+- } else {
+- sinfo->filled |= STATION_INFO_TX_BITRATE;
+- sinfo->txrate.legacy = rate * 5;
+- brcmf_dbg(CONN, "Rate %d Mbps\n", rate / 2);
+- }
+-
+- if (test_bit(BRCMF_VIF_STATUS_CONNECTED,
+- &ifp->vif->sme_state)) {
+- memset(&scb_val, 0, sizeof(scb_val));
+- err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_RSSI,
+- &scb_val, sizeof(scb_val));
+- if (err) {
+- brcmf_err("Could not get rssi (%d)\n", err);
+- goto done;
+- } else {
+- rssi = le32_to_cpu(scb_val.val);
+- sinfo->filled |= STATION_INFO_SIGNAL;
+- sinfo->signal = rssi;
+- brcmf_dbg(CONN, "RSSI %d dBm\n", rssi);
+- }
+- }
+- } else
+- err = -EPERM;
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *ndev,
+- bool enabled, s32 timeout)
+-{
+- s32 pm;
+- s32 err = 0;
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /*
+- * Powersave enable/disable request is coming from the
+- * cfg80211 even before the interface is up. In that
+- * scenario, driver will be storing the power save
+- * preference in cfg struct to apply this to
+- * FW later while initializing the dongle
+- */
+- cfg->pwr_save = enabled;
+- if (!check_vif_up(ifp->vif)) {
+-
+- brcmf_dbg(INFO, "Device is not ready, storing the value in cfg_info struct\n");
+- goto done;
+- }
+-
+- pm = enabled ? PM_FAST : PM_OFF;
+- /* Do not enable the power save after assoc if it is a p2p interface */
+- if (ifp->vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) {
+- brcmf_dbg(INFO, "Do not enable power save for P2P clients\n");
+- pm = PM_OFF;
+- }
+- brcmf_dbg(INFO, "power save %s\n", (pm ? "enabled" : "disabled"));
+-
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, pm);
+- if (err) {
+- if (err == -ENODEV)
+- brcmf_err("net_device is not ready yet\n");
+- else
+- brcmf_err("error (%d)\n", err);
+- }
+-done:
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_bss_info_le *bi)
+-{
+- struct wiphy *wiphy = cfg_to_wiphy(cfg);
+- struct ieee80211_channel *notify_channel;
+- struct cfg80211_bss *bss;
+- struct ieee80211_supported_band *band;
+- struct brcmu_chan ch;
+- s32 err = 0;
+- u16 channel;
+- u32 freq;
+- u16 notify_capability;
+- u16 notify_interval;
+- u8 *notify_ie;
+- size_t notify_ielen;
+- s32 notify_signal;
+-
+- if (le32_to_cpu(bi->length) > WL_BSS_INFO_MAX) {
+- brcmf_err("Bss info is larger than buffer. Discarding\n");
+- return 0;
+- }
+-
+- if (!bi->ctl_ch) {
+- ch.chspec = le16_to_cpu(bi->chanspec);
+- cfg->d11inf.decchspec(&ch);
+- bi->ctl_ch = ch.chnum;
+- }
+- channel = bi->ctl_ch;
+-
+- if (channel <= CH_MAX_2G_CHANNEL)
+- band = wiphy->bands[IEEE80211_BAND_2GHZ];
+- else
+- band = wiphy->bands[IEEE80211_BAND_5GHZ];
+-
+- freq = ieee80211_channel_to_frequency(channel, band->band);
+- notify_channel = ieee80211_get_channel(wiphy, freq);
+-
+- notify_capability = le16_to_cpu(bi->capability);
+- notify_interval = le16_to_cpu(bi->beacon_period);
+- notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
+- notify_ielen = le32_to_cpu(bi->ie_length);
+- notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
+-
+- brcmf_dbg(CONN, "bssid: %pM\n", bi->BSSID);
+- brcmf_dbg(CONN, "Channel: %d(%d)\n", channel, freq);
+- brcmf_dbg(CONN, "Capability: %X\n", notify_capability);
+- brcmf_dbg(CONN, "Beacon interval: %d\n", notify_interval);
+- brcmf_dbg(CONN, "Signal: %d\n", notify_signal);
+-
+- bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)bi->BSSID,
+- 0, notify_capability, notify_interval, notify_ie,
+- notify_ielen, notify_signal, GFP_KERNEL);
+-
+- if (!bss)
+- return -ENOMEM;
+-
+- cfg80211_put_bss(wiphy, bss);
+-
+- return err;
+-}
+-
+-static struct brcmf_bss_info_le *
+-next_bss_le(struct brcmf_scan_results *list, struct brcmf_bss_info_le *bss)
+-{
+- if (bss == NULL)
+- return list->bss_info_le;
+- return (struct brcmf_bss_info_le *)((unsigned long)bss +
+- le32_to_cpu(bss->length));
+-}
+-
+-static s32 brcmf_inform_bss(struct brcmf_cfg80211_info *cfg)
+-{
+- struct brcmf_scan_results *bss_list;
+- struct brcmf_bss_info_le *bi = NULL; /* must be initialized */
+- s32 err = 0;
+- int i;
+-
+- bss_list = cfg->bss_list;
+- if (bss_list->count != 0 &&
+- bss_list->version != BRCMF_BSS_INFO_VERSION) {
+- brcmf_err("Version %d != WL_BSS_INFO_VERSION\n",
+- bss_list->version);
+- return -EOPNOTSUPP;
+- }
+- brcmf_dbg(SCAN, "scanned AP count (%d)\n", bss_list->count);
+- for (i = 0; i < bss_list->count; i++) {
+- bi = next_bss_le(bss_list, bi);
+- err = brcmf_inform_single_bss(cfg, bi);
+- if (err)
+- break;
+- }
+- return err;
+-}
+-
+-static s32 wl_inform_ibss(struct brcmf_cfg80211_info *cfg,
+- struct net_device *ndev, const u8 *bssid)
+-{
+- struct wiphy *wiphy = cfg_to_wiphy(cfg);
+- struct ieee80211_channel *notify_channel;
+- struct brcmf_bss_info_le *bi = NULL;
+- struct ieee80211_supported_band *band;
+- struct cfg80211_bss *bss;
+- struct brcmu_chan ch;
+- u8 *buf = NULL;
+- s32 err = 0;
+- u32 freq;
+- u16 notify_capability;
+- u16 notify_interval;
+- u8 *notify_ie;
+- size_t notify_ielen;
+- s32 notify_signal;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
+- if (buf == NULL) {
+- err = -ENOMEM;
+- goto CleanUp;
+- }
+-
+- *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
+-
+- err = brcmf_fil_cmd_data_get(netdev_priv(ndev), BRCMF_C_GET_BSS_INFO,
+- buf, WL_BSS_INFO_MAX);
+- if (err) {
+- brcmf_err("WLC_GET_BSS_INFO failed: %d\n", err);
+- goto CleanUp;
+- }
+-
+- bi = (struct brcmf_bss_info_le *)(buf + 4);
+-
+- ch.chspec = le16_to_cpu(bi->chanspec);
+- cfg->d11inf.decchspec(&ch);
+-
+- if (ch.band == BRCMU_CHAN_BAND_2G)
+- band = wiphy->bands[IEEE80211_BAND_2GHZ];
+- else
+- band = wiphy->bands[IEEE80211_BAND_5GHZ];
+-
+- freq = ieee80211_channel_to_frequency(ch.chnum, band->band);
+- notify_channel = ieee80211_get_channel(wiphy, freq);
+-
+- notify_capability = le16_to_cpu(bi->capability);
+- notify_interval = le16_to_cpu(bi->beacon_period);
+- notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
+- notify_ielen = le32_to_cpu(bi->ie_length);
+- notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
+-
+- brcmf_dbg(CONN, "channel: %d(%d)\n", ch.chnum, freq);
+- brcmf_dbg(CONN, "capability: %X\n", notify_capability);
+- brcmf_dbg(CONN, "beacon interval: %d\n", notify_interval);
+- brcmf_dbg(CONN, "signal: %d\n", notify_signal);
+-
+- bss = cfg80211_inform_bss(wiphy, notify_channel, bssid,
+- 0, notify_capability, notify_interval,
+- notify_ie, notify_ielen, notify_signal, GFP_KERNEL);
+-
+- if (!bss) {
+- err = -ENOMEM;
+- goto CleanUp;
+- }
+-
+- cfg80211_put_bss(wiphy, bss);
+-
+-CleanUp:
+-
+- kfree(buf);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+-
+- return err;
+-}
+-
+-static bool brcmf_is_ibssmode(struct brcmf_cfg80211_vif *vif)
+-{
+- return vif->mode == WL_MODE_IBSS;
+-}
+-
+-static s32 brcmf_update_bss_info(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_if *ifp)
+-{
+- struct brcmf_cfg80211_profile *profile = ndev_to_prof(ifp->ndev);
+- struct brcmf_bss_info_le *bi;
+- struct brcmf_ssid *ssid;
+- struct brcmf_tlv *tim;
+- u16 beacon_interval;
+- u8 dtim_period;
+- size_t ie_len;
+- u8 *ie;
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (brcmf_is_ibssmode(ifp->vif))
+- return err;
+-
+- ssid = &profile->ssid;
+-
+- *(__le32 *)cfg->extra_buf = cpu_to_le32(WL_EXTRA_BUF_MAX);
+- err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSS_INFO,
+- cfg->extra_buf, WL_EXTRA_BUF_MAX);
+- if (err) {
+- brcmf_err("Could not get bss info %d\n", err);
+- goto update_bss_info_out;
+- }
+-
+- bi = (struct brcmf_bss_info_le *)(cfg->extra_buf + 4);
+- err = brcmf_inform_single_bss(cfg, bi);
+- if (err)
+- goto update_bss_info_out;
+-
+- ie = ((u8 *)bi) + le16_to_cpu(bi->ie_offset);
+- ie_len = le32_to_cpu(bi->ie_length);
+- beacon_interval = le16_to_cpu(bi->beacon_period);
+-
+- tim = brcmf_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
+- if (tim)
+- dtim_period = tim->data[1];
+- else {
+- /*
+- * active scan was done so we could not get dtim
+- * information out of probe response.
+- * so we speficially query dtim information to dongle.
+- */
+- u32 var;
+- err = brcmf_fil_iovar_int_get(ifp, "dtim_assoc", &var);
+- if (err) {
+- brcmf_err("wl dtim_assoc failed (%d)\n", err);
+- goto update_bss_info_out;
+- }
+- dtim_period = (u8)var;
+- }
+-
+-update_bss_info_out:
+- brcmf_dbg(TRACE, "Exit");
+- return err;
+-}
+-
+-void brcmf_abort_scanning(struct brcmf_cfg80211_info *cfg)
+-{
+- struct escan_info *escan = &cfg->escan_info;
+-
+- set_bit(BRCMF_SCAN_STATUS_ABORT, &cfg->scan_status);
+- if (cfg->scan_request) {
+- escan->escan_state = WL_ESCAN_STATE_IDLE;
+- brcmf_notify_escan_complete(cfg, escan->ifp, true, true);
+- }
+- clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
+- clear_bit(BRCMF_SCAN_STATUS_ABORT, &cfg->scan_status);
+-}
+-
+-static void brcmf_cfg80211_escan_timeout_worker(struct work_struct *work)
+-{
+- struct brcmf_cfg80211_info *cfg =
+- container_of(work, struct brcmf_cfg80211_info,
+- escan_timeout_work);
+-
+- brcmf_notify_escan_complete(cfg, cfg->escan_info.ifp, true, true);
+-}
+-
+-static void brcmf_escan_timeout(unsigned long data)
+-{
+- struct brcmf_cfg80211_info *cfg =
+- (struct brcmf_cfg80211_info *)data;
+-
+- if (cfg->scan_request) {
+- brcmf_err("timer expired\n");
+- schedule_work(&cfg->escan_timeout_work);
+- }
+-}
+-
+-static s32
+-brcmf_compare_update_same_bss(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_bss_info_le *bss,
+- struct brcmf_bss_info_le *bss_info_le)
+-{
+- struct brcmu_chan ch_bss, ch_bss_info_le;
+-
+- ch_bss.chspec = le16_to_cpu(bss->chanspec);
+- cfg->d11inf.decchspec(&ch_bss);
+- ch_bss_info_le.chspec = le16_to_cpu(bss_info_le->chanspec);
+- cfg->d11inf.decchspec(&ch_bss_info_le);
+-
+- if (!memcmp(&bss_info_le->BSSID, &bss->BSSID, ETH_ALEN) &&
+- ch_bss.band == ch_bss_info_le.band &&
+- bss_info_le->SSID_len == bss->SSID_len &&
+- !memcmp(bss_info_le->SSID, bss->SSID, bss_info_le->SSID_len)) {
+- if ((bss->flags & BRCMF_BSS_RSSI_ON_CHANNEL) ==
+- (bss_info_le->flags & BRCMF_BSS_RSSI_ON_CHANNEL)) {
+- s16 bss_rssi = le16_to_cpu(bss->RSSI);
+- s16 bss_info_rssi = le16_to_cpu(bss_info_le->RSSI);
+-
+- /* preserve max RSSI if the measurements are
+- * both on-channel or both off-channel
+- */
+- if (bss_info_rssi > bss_rssi)
+- bss->RSSI = bss_info_le->RSSI;
+- } else if ((bss->flags & BRCMF_BSS_RSSI_ON_CHANNEL) &&
+- (bss_info_le->flags & BRCMF_BSS_RSSI_ON_CHANNEL) == 0) {
+- /* preserve the on-channel rssi measurement
+- * if the new measurement is off channel
+- */
+- bss->RSSI = bss_info_le->RSSI;
+- bss->flags |= BRCMF_BSS_RSSI_ON_CHANNEL;
+- }
+- return 1;
+- }
+- return 0;
+-}
+-
+-static s32
+-brcmf_cfg80211_escan_handler(struct brcmf_if *ifp,
+- const struct brcmf_event_msg *e, void *data)
+-{
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+- s32 status;
+- s32 err = 0;
+- struct brcmf_escan_result_le *escan_result_le;
+- struct brcmf_bss_info_le *bss_info_le;
+- struct brcmf_bss_info_le *bss = NULL;
+- u32 bi_length;
+- struct brcmf_scan_results *list;
+- u32 i;
+- bool aborted;
+-
+- status = e->status;
+-
+- if (!test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
+- brcmf_err("scan not ready, bssidx=%d\n", ifp->bssidx);
+- return -EPERM;
+- }
+-
+- if (status == BRCMF_E_STATUS_PARTIAL) {
+- brcmf_dbg(SCAN, "ESCAN Partial result\n");
+- escan_result_le = (struct brcmf_escan_result_le *) data;
+- if (!escan_result_le) {
+- brcmf_err("Invalid escan result (NULL pointer)\n");
+- goto exit;
+- }
+- if (le16_to_cpu(escan_result_le->bss_count) != 1) {
+- brcmf_err("Invalid bss_count %d: ignoring\n",
+- escan_result_le->bss_count);
+- goto exit;
+- }
+- bss_info_le = &escan_result_le->bss_info_le;
+-
+- if (brcmf_p2p_scan_finding_common_channel(cfg, bss_info_le))
+- goto exit;
+-
+- if (!cfg->scan_request) {
+- brcmf_dbg(SCAN, "result without cfg80211 request\n");
+- goto exit;
+- }
+-
+- bi_length = le32_to_cpu(bss_info_le->length);
+- if (bi_length != (le32_to_cpu(escan_result_le->buflen) -
+- WL_ESCAN_RESULTS_FIXED_SIZE)) {
+- brcmf_err("Invalid bss_info length %d: ignoring\n",
+- bi_length);
+- goto exit;
+- }
+-
+- if (!(cfg_to_wiphy(cfg)->interface_modes &
+- BIT(NL80211_IFTYPE_ADHOC))) {
+- if (le16_to_cpu(bss_info_le->capability) &
+- WLAN_CAPABILITY_IBSS) {
+- brcmf_err("Ignoring IBSS result\n");
+- goto exit;
+- }
+- }
+-
+- list = (struct brcmf_scan_results *)
+- cfg->escan_info.escan_buf;
+- if (bi_length > WL_ESCAN_BUF_SIZE - list->buflen) {
+- brcmf_err("Buffer is too small: ignoring\n");
+- goto exit;
+- }
+-
+- for (i = 0; i < list->count; i++) {
+- bss = bss ? (struct brcmf_bss_info_le *)
+- ((unsigned char *)bss +
+- le32_to_cpu(bss->length)) : list->bss_info_le;
+- if (brcmf_compare_update_same_bss(cfg, bss,
+- bss_info_le))
+- goto exit;
+- }
+- memcpy(&(cfg->escan_info.escan_buf[list->buflen]),
+- bss_info_le, bi_length);
+- list->version = le32_to_cpu(bss_info_le->version);
+- list->buflen += bi_length;
+- list->count++;
+- } else {
+- cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
+- if (brcmf_p2p_scan_finding_common_channel(cfg, NULL))
+- goto exit;
+- if (cfg->scan_request) {
+- cfg->bss_list = (struct brcmf_scan_results *)
+- cfg->escan_info.escan_buf;
+- brcmf_inform_bss(cfg);
+- aborted = status != BRCMF_E_STATUS_SUCCESS;
+- brcmf_notify_escan_complete(cfg, ifp, aborted,
+- false);
+- } else
+- brcmf_dbg(SCAN, "Ignored scan complete result 0x%x\n",
+- status);
+- }
+-exit:
+- return err;
+-}
+-
+-static void brcmf_init_escan(struct brcmf_cfg80211_info *cfg)
+-{
+- brcmf_fweh_register(cfg->pub, BRCMF_E_ESCAN_RESULT,
+- brcmf_cfg80211_escan_handler);
+- cfg->escan_info.escan_state = WL_ESCAN_STATE_IDLE;
+- /* Init scan_timeout timer */
+- init_timer(&cfg->escan_timeout);
+- cfg->escan_timeout.data = (unsigned long) cfg;
+- cfg->escan_timeout.function = brcmf_escan_timeout;
+- INIT_WORK(&cfg->escan_timeout_work,
+- brcmf_cfg80211_escan_timeout_worker);
+-}
+-
+-static __always_inline void brcmf_delay(u32 ms)
+-{
+- if (ms < 1000 / HZ) {
+- cond_resched();
+- mdelay(ms);
+- } else {
+- msleep(ms);
+- }
+-}
+-
+-static s32 brcmf_cfg80211_resume(struct wiphy *wiphy)
+-{
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- return 0;
+-}
+-
+-static s32 brcmf_cfg80211_suspend(struct wiphy *wiphy,
+- struct cfg80211_wowlan *wow)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct net_device *ndev = cfg_to_ndev(cfg);
+- struct brcmf_cfg80211_vif *vif;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- /*
+- * if the primary net_device is not READY there is nothing
+- * we can do but pray resume goes smoothly.
+- */
+- vif = ((struct brcmf_if *)netdev_priv(ndev))->vif;
+- if (!check_vif_up(vif))
+- goto exit;
+-
+- list_for_each_entry(vif, &cfg->vif_list, list) {
+- if (!test_bit(BRCMF_VIF_STATUS_READY, &vif->sme_state))
+- continue;
+- /*
+- * While going to suspend if associated with AP disassociate
+- * from AP to save power while system is in suspended state
+- */
+- brcmf_link_down(vif);
+-
+- /* Make sure WPA_Supplicant receives all the event
+- * generated due to DISASSOC call to the fw to keep
+- * the state fw and WPA_Supplicant state consistent
+- */
+- brcmf_delay(500);
+- }
+-
+- /* end any scanning */
+- if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status))
+- brcmf_abort_scanning(cfg);
+-
+- /* Turn off watchdog timer */
+- brcmf_set_mpc(netdev_priv(ndev), 1);
+-
+-exit:
+- brcmf_dbg(TRACE, "Exit\n");
+- /* clear any scanning activity */
+- cfg->scan_status = 0;
+- return 0;
+-}
+-
+-static __used s32
+-brcmf_update_pmklist(struct net_device *ndev,
+- struct brcmf_cfg80211_pmk_list *pmk_list, s32 err)
+-{
+- int i, j;
+- int pmkid_len;
+-
+- pmkid_len = le32_to_cpu(pmk_list->pmkids.npmkid);
+-
+- brcmf_dbg(CONN, "No of elements %d\n", pmkid_len);
+- for (i = 0; i < pmkid_len; i++) {
+- brcmf_dbg(CONN, "PMKID[%d]: %pM =\n", i,
+- &pmk_list->pmkids.pmkid[i].BSSID);
+- for (j = 0; j < WLAN_PMKID_LEN; j++)
+- brcmf_dbg(CONN, "%02x\n",
+- pmk_list->pmkids.pmkid[i].PMKID[j]);
+- }
+-
+- if (!err)
+- brcmf_fil_iovar_data_set(netdev_priv(ndev), "pmkid_info",
+- (char *)pmk_list, sizeof(*pmk_list));
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_set_pmksa(struct wiphy *wiphy, struct net_device *ndev,
+- struct cfg80211_pmksa *pmksa)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct pmkid_list *pmkids = &cfg->pmk_list->pmkids;
+- s32 err = 0;
+- int i;
+- int pmkid_len;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- pmkid_len = le32_to_cpu(pmkids->npmkid);
+- for (i = 0; i < pmkid_len; i++)
+- if (!memcmp(pmksa->bssid, pmkids->pmkid[i].BSSID, ETH_ALEN))
+- break;
+- if (i < WL_NUM_PMKIDS_MAX) {
+- memcpy(pmkids->pmkid[i].BSSID, pmksa->bssid, ETH_ALEN);
+- memcpy(pmkids->pmkid[i].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
+- if (i == pmkid_len) {
+- pmkid_len++;
+- pmkids->npmkid = cpu_to_le32(pmkid_len);
+- }
+- } else
+- err = -EINVAL;
+-
+- brcmf_dbg(CONN, "set_pmksa,IW_PMKSA_ADD - PMKID: %pM =\n",
+- pmkids->pmkid[pmkid_len].BSSID);
+- for (i = 0; i < WLAN_PMKID_LEN; i++)
+- brcmf_dbg(CONN, "%02x\n", pmkids->pmkid[pmkid_len].PMKID[i]);
+-
+- err = brcmf_update_pmklist(ndev, cfg->pmk_list, err);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_del_pmksa(struct wiphy *wiphy, struct net_device *ndev,
+- struct cfg80211_pmksa *pmksa)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct pmkid_list pmkid;
+- s32 err = 0;
+- int i, pmkid_len;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- memcpy(&pmkid.pmkid[0].BSSID, pmksa->bssid, ETH_ALEN);
+- memcpy(&pmkid.pmkid[0].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
+-
+- brcmf_dbg(CONN, "del_pmksa,IW_PMKSA_REMOVE - PMKID: %pM =\n",
+- &pmkid.pmkid[0].BSSID);
+- for (i = 0; i < WLAN_PMKID_LEN; i++)
+- brcmf_dbg(CONN, "%02x\n", pmkid.pmkid[0].PMKID[i]);
+-
+- pmkid_len = le32_to_cpu(cfg->pmk_list->pmkids.npmkid);
+- for (i = 0; i < pmkid_len; i++)
+- if (!memcmp
+- (pmksa->bssid, &cfg->pmk_list->pmkids.pmkid[i].BSSID,
+- ETH_ALEN))
+- break;
+-
+- if ((pmkid_len > 0)
+- && (i < pmkid_len)) {
+- memset(&cfg->pmk_list->pmkids.pmkid[i], 0,
+- sizeof(struct pmkid));
+- for (; i < (pmkid_len - 1); i++) {
+- memcpy(&cfg->pmk_list->pmkids.pmkid[i].BSSID,
+- &cfg->pmk_list->pmkids.pmkid[i + 1].BSSID,
+- ETH_ALEN);
+- memcpy(&cfg->pmk_list->pmkids.pmkid[i].PMKID,
+- &cfg->pmk_list->pmkids.pmkid[i + 1].PMKID,
+- WLAN_PMKID_LEN);
+- }
+- cfg->pmk_list->pmkids.npmkid = cpu_to_le32(pmkid_len - 1);
+- } else
+- err = -EINVAL;
+-
+- err = brcmf_update_pmklist(ndev, cfg->pmk_list, err);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-
+-}
+-
+-static s32
+-brcmf_cfg80211_flush_pmksa(struct wiphy *wiphy, struct net_device *ndev)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- memset(cfg->pmk_list, 0, sizeof(*cfg->pmk_list));
+- err = brcmf_update_pmklist(ndev, cfg->pmk_list, err);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-
+-}
+-
+-/*
+- * PFN result doesn't have all the info which are
+- * required by the supplicant
+- * (For e.g IEs) Do a target Escan so that sched scan results are reported
+- * via wl_inform_single_bss in the required format. Escan does require the
+- * scan request in the form of cfg80211_scan_request. For timebeing, create
+- * cfg80211_scan_request one out of the received PNO event.
+- */
+-static s32
+-brcmf_notify_sched_scan_results(struct brcmf_if *ifp,
+- const struct brcmf_event_msg *e, void *data)
+-{
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+- struct brcmf_pno_net_info_le *netinfo, *netinfo_start;
+- struct cfg80211_scan_request *request = NULL;
+- struct cfg80211_ssid *ssid = NULL;
+- struct ieee80211_channel *channel = NULL;
+- struct wiphy *wiphy = cfg_to_wiphy(cfg);
+- int err = 0;
+- int channel_req = 0;
+- int band = 0;
+- struct brcmf_pno_scanresults_le *pfn_result;
+- u32 result_count;
+- u32 status;
+-
+- brcmf_dbg(SCAN, "Enter\n");
+-
+- if (e->event_code == BRCMF_E_PFN_NET_LOST) {
+- brcmf_dbg(SCAN, "PFN NET LOST event. Do Nothing\n");
+- return 0;
+- }
+-
+- pfn_result = (struct brcmf_pno_scanresults_le *)data;
+- result_count = le32_to_cpu(pfn_result->count);
+- status = le32_to_cpu(pfn_result->status);
+-
+- /*
+- * PFN event is limited to fit 512 bytes so we may get
+- * multiple NET_FOUND events. For now place a warning here.
+- */
+- WARN_ON(status != BRCMF_PNO_SCAN_COMPLETE);
+- brcmf_dbg(SCAN, "PFN NET FOUND event. count: %d\n", result_count);
+- if (result_count > 0) {
+- int i;
+-
+- request = kzalloc(sizeof(*request), GFP_KERNEL);
+- ssid = kcalloc(result_count, sizeof(*ssid), GFP_KERNEL);
+- channel = kcalloc(result_count, sizeof(*channel), GFP_KERNEL);
+- if (!request || !ssid || !channel) {
+- err = -ENOMEM;
+- goto out_err;
+- }
+-
+- request->wiphy = wiphy;
+- data += sizeof(struct brcmf_pno_scanresults_le);
+- netinfo_start = (struct brcmf_pno_net_info_le *)data;
+-
+- for (i = 0; i < result_count; i++) {
+- netinfo = &netinfo_start[i];
+- if (!netinfo) {
+- brcmf_err("Invalid netinfo ptr. index: %d\n",
+- i);
+- err = -EINVAL;
+- goto out_err;
+- }
+-
+- brcmf_dbg(SCAN, "SSID:%s Channel:%d\n",
+- netinfo->SSID, netinfo->channel);
+- memcpy(ssid[i].ssid, netinfo->SSID, netinfo->SSID_len);
+- ssid[i].ssid_len = netinfo->SSID_len;
+- request->n_ssids++;
+-
+- channel_req = netinfo->channel;
+- if (channel_req <= CH_MAX_2G_CHANNEL)
+- band = NL80211_BAND_2GHZ;
+- else
+- band = NL80211_BAND_5GHZ;
+- channel[i].center_freq =
+- ieee80211_channel_to_frequency(channel_req,
+- band);
+- channel[i].band = band;
+- channel[i].flags |= IEEE80211_CHAN_NO_HT40;
+- request->channels[i] = &channel[i];
+- request->n_channels++;
+- }
+-
+- /* assign parsed ssid array */
+- if (request->n_ssids)
+- request->ssids = &ssid[0];
+-
+- if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
+- /* Abort any on-going scan */
+- brcmf_abort_scanning(cfg);
+- }
+-
+- set_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
+- cfg->escan_info.run = brcmf_run_escan;
+- err = brcmf_do_escan(cfg, wiphy, ifp, request);
+- if (err) {
+- clear_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status);
+- goto out_err;
+- }
+- cfg->sched_escan = true;
+- cfg->scan_request = request;
+- } else {
+- brcmf_err("FALSE PNO Event. (pfn_count == 0)\n");
+- goto out_err;
+- }
+-
+- kfree(ssid);
+- kfree(channel);
+- kfree(request);
+- return 0;
+-
+-out_err:
+- kfree(ssid);
+- kfree(channel);
+- kfree(request);
+- cfg80211_sched_scan_stopped(wiphy);
+- return err;
+-}
+-
+-static int brcmf_dev_pno_clean(struct net_device *ndev)
+-{
+- int ret;
+-
+- /* Disable pfn */
+- ret = brcmf_fil_iovar_int_set(netdev_priv(ndev), "pfn", 0);
+- if (ret == 0) {
+- /* clear pfn */
+- ret = brcmf_fil_iovar_data_set(netdev_priv(ndev), "pfnclear",
+- NULL, 0);
+- }
+- if (ret < 0)
+- brcmf_err("failed code %d\n", ret);
+-
+- return ret;
+-}
+-
+-static int brcmf_dev_pno_config(struct net_device *ndev)
+-{
+- struct brcmf_pno_param_le pfn_param;
+-
+- memset(&pfn_param, 0, sizeof(pfn_param));
+- pfn_param.version = cpu_to_le32(BRCMF_PNO_VERSION);
+-
+- /* set extra pno params */
+- pfn_param.flags = cpu_to_le16(1 << BRCMF_PNO_ENABLE_ADAPTSCAN_BIT);
+- pfn_param.repeat = BRCMF_PNO_REPEAT;
+- pfn_param.exp = BRCMF_PNO_FREQ_EXPO_MAX;
+-
+- /* set up pno scan fr */
+- pfn_param.scan_freq = cpu_to_le32(BRCMF_PNO_TIME);
+-
+- return brcmf_fil_iovar_data_set(netdev_priv(ndev), "pfn_set",
+- &pfn_param, sizeof(pfn_param));
+-}
+-
+-static int
+-brcmf_cfg80211_sched_scan_start(struct wiphy *wiphy,
+- struct net_device *ndev,
+- struct cfg80211_sched_scan_request *request)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_info *cfg = wiphy_priv(wiphy);
+- struct brcmf_pno_net_param_le pfn;
+- int i;
+- int ret = 0;
+-
+- brcmf_dbg(SCAN, "Enter n_match_sets:%d n_ssids:%d\n",
+- request->n_match_sets, request->n_ssids);
+- if (test_bit(BRCMF_SCAN_STATUS_BUSY, &cfg->scan_status)) {
+- brcmf_err("Scanning already: status (%lu)\n", cfg->scan_status);
+- return -EAGAIN;
+- }
+- if (test_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status)) {
+- brcmf_err("Scanning suppressed: status (%lu)\n",
+- cfg->scan_status);
+- return -EAGAIN;
+- }
+-
+- if (!request->n_ssids || !request->n_match_sets) {
+- brcmf_err("Invalid sched scan req!! n_ssids:%d\n",
+- request->n_ssids);
+- return -EINVAL;
+- }
+-
+- if (request->n_ssids > 0) {
+- for (i = 0; i < request->n_ssids; i++) {
+- /* Active scan req for ssids */
+- brcmf_dbg(SCAN, ">>> Active scan req for ssid (%s)\n",
+- request->ssids[i].ssid);
+-
+- /*
+- * match_set ssids is a supert set of n_ssid list,
+- * so we need not add these set seperately.
+- */
+- }
+- }
+-
+- if (request->n_match_sets > 0) {
+- /* clean up everything */
+- ret = brcmf_dev_pno_clean(ndev);
+- if (ret < 0) {
+- brcmf_err("failed error=%d\n", ret);
+- return ret;
+- }
+-
+- /* configure pno */
+- ret = brcmf_dev_pno_config(ndev);
+- if (ret < 0) {
+- brcmf_err("PNO setup failed!! ret=%d\n", ret);
+- return -EINVAL;
+- }
+-
+- /* configure each match set */
+- for (i = 0; i < request->n_match_sets; i++) {
+- struct cfg80211_ssid *ssid;
+- u32 ssid_len;
+-
+- ssid = &request->match_sets[i].ssid;
+- ssid_len = ssid->ssid_len;
+-
+- if (!ssid_len) {
+- brcmf_err("skip broadcast ssid\n");
+- continue;
+- }
+- pfn.auth = cpu_to_le32(WLAN_AUTH_OPEN);
+- pfn.wpa_auth = cpu_to_le32(BRCMF_PNO_WPA_AUTH_ANY);
+- pfn.wsec = cpu_to_le32(0);
+- pfn.infra = cpu_to_le32(1);
+- pfn.flags = cpu_to_le32(1 << BRCMF_PNO_HIDDEN_BIT);
+- pfn.ssid.SSID_len = cpu_to_le32(ssid_len);
+- memcpy(pfn.ssid.SSID, ssid->ssid, ssid_len);
+- ret = brcmf_fil_iovar_data_set(ifp, "pfn_add", &pfn,
+- sizeof(pfn));
+- brcmf_dbg(SCAN, ">>> PNO filter %s for ssid (%s)\n",
+- ret == 0 ? "set" : "failed", ssid->ssid);
+- }
+- /* Enable the PNO */
+- if (brcmf_fil_iovar_int_set(ifp, "pfn", 1) < 0) {
+- brcmf_err("PNO enable failed!! ret=%d\n", ret);
+- return -EINVAL;
+- }
+- } else {
+- return -EINVAL;
+- }
+-
+- return 0;
+-}
+-
+-static int brcmf_cfg80211_sched_scan_stop(struct wiphy *wiphy,
+- struct net_device *ndev)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+-
+- brcmf_dbg(SCAN, "enter\n");
+- brcmf_dev_pno_clean(ndev);
+- if (cfg->sched_escan)
+- brcmf_notify_escan_complete(cfg, netdev_priv(ndev), true, true);
+- return 0;
+-}
+-
+-#ifdef CONFIG_NL80211_TESTMODE
+-static int brcmf_cfg80211_testmode(struct wiphy *wiphy,
+- struct wireless_dev *wdev,
+- void *data, int len)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct net_device *ndev = cfg_to_ndev(cfg);
+- struct brcmf_dcmd *dcmd = data;
+- struct sk_buff *reply;
+- int ret;
+-
+- brcmf_dbg(TRACE, "cmd %x set %d buf %p len %d\n", dcmd->cmd, dcmd->set,
+- dcmd->buf, dcmd->len);
+-
+- if (dcmd->set)
+- ret = brcmf_fil_cmd_data_set(netdev_priv(ndev), dcmd->cmd,
+- dcmd->buf, dcmd->len);
+- else
+- ret = brcmf_fil_cmd_data_get(netdev_priv(ndev), dcmd->cmd,
+- dcmd->buf, dcmd->len);
+- if (ret == 0) {
+- reply = cfg80211_testmode_alloc_reply_skb(wiphy, sizeof(*dcmd));
+- nla_put(reply, NL80211_ATTR_TESTDATA, sizeof(*dcmd), dcmd);
+- ret = cfg80211_testmode_reply(reply);
+- }
+- return ret;
+-}
+-#endif
+-
+-static s32 brcmf_configure_opensecurity(struct brcmf_if *ifp)
+-{
+- s32 err;
+-
+- /* set auth */
+- err = brcmf_fil_bsscfg_int_set(ifp, "auth", 0);
+- if (err < 0) {
+- brcmf_err("auth error %d\n", err);
+- return err;
+- }
+- /* set wsec */
+- err = brcmf_fil_bsscfg_int_set(ifp, "wsec", 0);
+- if (err < 0) {
+- brcmf_err("wsec error %d\n", err);
+- return err;
+- }
+- /* set upper-layer auth */
+- err = brcmf_fil_bsscfg_int_set(ifp, "wpa_auth", WPA_AUTH_NONE);
+- if (err < 0) {
+- brcmf_err("wpa_auth error %d\n", err);
+- return err;
+- }
+-
+- return 0;
+-}
+-
+-static bool brcmf_valid_wpa_oui(u8 *oui, bool is_rsn_ie)
+-{
+- if (is_rsn_ie)
+- return (memcmp(oui, RSN_OUI, TLV_OUI_LEN) == 0);
+-
+- return (memcmp(oui, WPA_OUI, TLV_OUI_LEN) == 0);
+-}
+-
+-static s32
+-brcmf_configure_wpaie(struct net_device *ndev, struct brcmf_vs_tlv *wpa_ie,
+- bool is_rsn_ie)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- u32 auth = 0; /* d11 open authentication */
+- u16 count;
+- s32 err = 0;
+- s32 len = 0;
+- u32 i;
+- u32 wsec;
+- u32 pval = 0;
+- u32 gval = 0;
+- u32 wpa_auth = 0;
+- u32 offset;
+- u8 *data;
+- u16 rsn_cap;
+- u32 wme_bss_disable;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+- if (wpa_ie == NULL)
+- goto exit;
+-
+- len = wpa_ie->len + TLV_HDR_LEN;
+- data = (u8 *)wpa_ie;
+- offset = TLV_HDR_LEN;
+- if (!is_rsn_ie)
+- offset += VS_IE_FIXED_HDR_LEN;
+- else
+- offset += WPA_IE_VERSION_LEN;
+-
+- /* check for multicast cipher suite */
+- if (offset + WPA_IE_MIN_OUI_LEN > len) {
+- err = -EINVAL;
+- brcmf_err("no multicast cipher suite\n");
+- goto exit;
+- }
+-
+- if (!brcmf_valid_wpa_oui(&data[offset], is_rsn_ie)) {
+- err = -EINVAL;
+- brcmf_err("ivalid OUI\n");
+- goto exit;
+- }
+- offset += TLV_OUI_LEN;
+-
+- /* pick up multicast cipher */
+- switch (data[offset]) {
+- case WPA_CIPHER_NONE:
+- gval = 0;
+- break;
+- case WPA_CIPHER_WEP_40:
+- case WPA_CIPHER_WEP_104:
+- gval = WEP_ENABLED;
+- break;
+- case WPA_CIPHER_TKIP:
+- gval = TKIP_ENABLED;
+- break;
+- case WPA_CIPHER_AES_CCM:
+- gval = AES_ENABLED;
+- break;
+- default:
+- err = -EINVAL;
+- brcmf_err("Invalid multi cast cipher info\n");
+- goto exit;
+- }
+-
+- offset++;
+- /* walk thru unicast cipher list and pick up what we recognize */
+- count = data[offset] + (data[offset + 1] << 8);
+- offset += WPA_IE_SUITE_COUNT_LEN;
+- /* Check for unicast suite(s) */
+- if (offset + (WPA_IE_MIN_OUI_LEN * count) > len) {
+- err = -EINVAL;
+- brcmf_err("no unicast cipher suite\n");
+- goto exit;
+- }
+- for (i = 0; i < count; i++) {
+- if (!brcmf_valid_wpa_oui(&data[offset], is_rsn_ie)) {
+- err = -EINVAL;
+- brcmf_err("ivalid OUI\n");
+- goto exit;
+- }
+- offset += TLV_OUI_LEN;
+- switch (data[offset]) {
+- case WPA_CIPHER_NONE:
+- break;
+- case WPA_CIPHER_WEP_40:
+- case WPA_CIPHER_WEP_104:
+- pval |= WEP_ENABLED;
+- break;
+- case WPA_CIPHER_TKIP:
+- pval |= TKIP_ENABLED;
+- break;
+- case WPA_CIPHER_AES_CCM:
+- pval |= AES_ENABLED;
+- break;
+- default:
+- brcmf_err("Ivalid unicast security info\n");
+- }
+- offset++;
+- }
+- /* walk thru auth management suite list and pick up what we recognize */
+- count = data[offset] + (data[offset + 1] << 8);
+- offset += WPA_IE_SUITE_COUNT_LEN;
+- /* Check for auth key management suite(s) */
+- if (offset + (WPA_IE_MIN_OUI_LEN * count) > len) {
+- err = -EINVAL;
+- brcmf_err("no auth key mgmt suite\n");
+- goto exit;
+- }
+- for (i = 0; i < count; i++) {
+- if (!brcmf_valid_wpa_oui(&data[offset], is_rsn_ie)) {
+- err = -EINVAL;
+- brcmf_err("ivalid OUI\n");
+- goto exit;
+- }
+- offset += TLV_OUI_LEN;
+- switch (data[offset]) {
+- case RSN_AKM_NONE:
+- brcmf_dbg(TRACE, "RSN_AKM_NONE\n");
+- wpa_auth |= WPA_AUTH_NONE;
+- break;
+- case RSN_AKM_UNSPECIFIED:
+- brcmf_dbg(TRACE, "RSN_AKM_UNSPECIFIED\n");
+- is_rsn_ie ? (wpa_auth |= WPA2_AUTH_UNSPECIFIED) :
+- (wpa_auth |= WPA_AUTH_UNSPECIFIED);
+- break;
+- case RSN_AKM_PSK:
+- brcmf_dbg(TRACE, "RSN_AKM_PSK\n");
+- is_rsn_ie ? (wpa_auth |= WPA2_AUTH_PSK) :
+- (wpa_auth |= WPA_AUTH_PSK);
+- break;
+- default:
+- brcmf_err("Ivalid key mgmt info\n");
+- }
+- offset++;
+- }
+-
+- if (is_rsn_ie) {
+- wme_bss_disable = 1;
+- if ((offset + RSN_CAP_LEN) <= len) {
+- rsn_cap = data[offset] + (data[offset + 1] << 8);
+- if (rsn_cap & RSN_CAP_PTK_REPLAY_CNTR_MASK)
+- wme_bss_disable = 0;
+- }
+- /* set wme_bss_disable to sync RSN Capabilities */
+- err = brcmf_fil_bsscfg_int_set(ifp, "wme_bss_disable",
+- wme_bss_disable);
+- if (err < 0) {
+- brcmf_err("wme_bss_disable error %d\n", err);
+- goto exit;
+- }
+- }
+- /* FOR WPS , set SES_OW_ENABLED */
+- wsec = (pval | gval | SES_OW_ENABLED);
+-
+- /* set auth */
+- err = brcmf_fil_bsscfg_int_set(ifp, "auth", auth);
+- if (err < 0) {
+- brcmf_err("auth error %d\n", err);
+- goto exit;
+- }
+- /* set wsec */
+- err = brcmf_fil_bsscfg_int_set(ifp, "wsec", wsec);
+- if (err < 0) {
+- brcmf_err("wsec error %d\n", err);
+- goto exit;
+- }
+- /* set upper-layer auth */
+- err = brcmf_fil_bsscfg_int_set(ifp, "wpa_auth", wpa_auth);
+- if (err < 0) {
+- brcmf_err("wpa_auth error %d\n", err);
+- goto exit;
+- }
+-
+-exit:
+- return err;
+-}
+-
+-static s32
+-brcmf_parse_vndr_ies(const u8 *vndr_ie_buf, u32 vndr_ie_len,
+- struct parsed_vndr_ies *vndr_ies)
+-{
+- s32 err = 0;
+- struct brcmf_vs_tlv *vndrie;
+- struct brcmf_tlv *ie;
+- struct parsed_vndr_ie_info *parsed_info;
+- s32 remaining_len;
+-
+- remaining_len = (s32)vndr_ie_len;
+- memset(vndr_ies, 0, sizeof(*vndr_ies));
+-
+- ie = (struct brcmf_tlv *)vndr_ie_buf;
+- while (ie) {
+- if (ie->id != WLAN_EID_VENDOR_SPECIFIC)
+- goto next;
+- vndrie = (struct brcmf_vs_tlv *)ie;
+- /* len should be bigger than OUI length + one */
+- if (vndrie->len < (VS_IE_FIXED_HDR_LEN - TLV_HDR_LEN + 1)) {
+- brcmf_err("invalid vndr ie. length is too small %d\n",
+- vndrie->len);
+- goto next;
+- }
+- /* if wpa or wme ie, do not add ie */
+- if (!memcmp(vndrie->oui, (u8 *)WPA_OUI, TLV_OUI_LEN) &&
+- ((vndrie->oui_type == WPA_OUI_TYPE) ||
+- (vndrie->oui_type == WME_OUI_TYPE))) {
+- brcmf_dbg(TRACE, "Found WPA/WME oui. Do not add it\n");
+- goto next;
+- }
+-
+- parsed_info = &vndr_ies->ie_info[vndr_ies->count];
+-
+- /* save vndr ie information */
+- parsed_info->ie_ptr = (char *)vndrie;
+- parsed_info->ie_len = vndrie->len + TLV_HDR_LEN;
+- memcpy(&parsed_info->vndrie, vndrie, sizeof(*vndrie));
+-
+- vndr_ies->count++;
+-
+- brcmf_dbg(TRACE, "** OUI %02x %02x %02x, type 0x%02x\n",
+- parsed_info->vndrie.oui[0],
+- parsed_info->vndrie.oui[1],
+- parsed_info->vndrie.oui[2],
+- parsed_info->vndrie.oui_type);
+-
+- if (vndr_ies->count >= VNDR_IE_PARSE_LIMIT)
+- break;
+-next:
+- remaining_len -= (ie->len + TLV_HDR_LEN);
+- if (remaining_len <= TLV_HDR_LEN)
+- ie = NULL;
+- else
+- ie = (struct brcmf_tlv *)(((u8 *)ie) + ie->len +
+- TLV_HDR_LEN);
+- }
+- return err;
+-}
+-
+-static u32
+-brcmf_vndr_ie(u8 *iebuf, s32 pktflag, u8 *ie_ptr, u32 ie_len, s8 *add_del_cmd)
+-{
+-
+- __le32 iecount_le;
+- __le32 pktflag_le;
+-
+- strncpy(iebuf, add_del_cmd, VNDR_IE_CMD_LEN - 1);
+- iebuf[VNDR_IE_CMD_LEN - 1] = '\0';
+-
+- iecount_le = cpu_to_le32(1);
+- memcpy(&iebuf[VNDR_IE_COUNT_OFFSET], &iecount_le, sizeof(iecount_le));
+-
+- pktflag_le = cpu_to_le32(pktflag);
+- memcpy(&iebuf[VNDR_IE_PKTFLAG_OFFSET], &pktflag_le, sizeof(pktflag_le));
+-
+- memcpy(&iebuf[VNDR_IE_VSIE_OFFSET], ie_ptr, ie_len);
+-
+- return ie_len + VNDR_IE_HDR_SIZE;
+-}
+-
+-s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
+- const u8 *vndr_ie_buf, u32 vndr_ie_len)
+-{
+- struct brcmf_if *ifp;
+- struct vif_saved_ie *saved_ie;
+- s32 err = 0;
+- u8 *iovar_ie_buf;
+- u8 *curr_ie_buf;
+- u8 *mgmt_ie_buf = NULL;
+- int mgmt_ie_buf_len;
+- u32 *mgmt_ie_len;
+- u32 del_add_ie_buf_len = 0;
+- u32 total_ie_buf_len = 0;
+- u32 parsed_ie_buf_len = 0;
+- struct parsed_vndr_ies old_vndr_ies;
+- struct parsed_vndr_ies new_vndr_ies;
+- struct parsed_vndr_ie_info *vndrie_info;
+- s32 i;
+- u8 *ptr;
+- int remained_buf_len;
+-
+- if (!vif)
+- return -ENODEV;
+- ifp = vif->ifp;
+- saved_ie = &vif->saved_ie;
+-
+- brcmf_dbg(TRACE, "bssidx %d, pktflag : 0x%02X\n", ifp->bssidx, pktflag);
+- iovar_ie_buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
+- if (!iovar_ie_buf)
+- return -ENOMEM;
+- curr_ie_buf = iovar_ie_buf;
+- switch (pktflag) {
+- case BRCMF_VNDR_IE_PRBREQ_FLAG:
+- mgmt_ie_buf = saved_ie->probe_req_ie;
+- mgmt_ie_len = &saved_ie->probe_req_ie_len;
+- mgmt_ie_buf_len = sizeof(saved_ie->probe_req_ie);
+- break;
+- case BRCMF_VNDR_IE_PRBRSP_FLAG:
+- mgmt_ie_buf = saved_ie->probe_res_ie;
+- mgmt_ie_len = &saved_ie->probe_res_ie_len;
+- mgmt_ie_buf_len = sizeof(saved_ie->probe_res_ie);
+- break;
+- case BRCMF_VNDR_IE_BEACON_FLAG:
+- mgmt_ie_buf = saved_ie->beacon_ie;
+- mgmt_ie_len = &saved_ie->beacon_ie_len;
+- mgmt_ie_buf_len = sizeof(saved_ie->beacon_ie);
+- break;
+- case BRCMF_VNDR_IE_ASSOCREQ_FLAG:
+- mgmt_ie_buf = saved_ie->assoc_req_ie;
+- mgmt_ie_len = &saved_ie->assoc_req_ie_len;
+- mgmt_ie_buf_len = sizeof(saved_ie->assoc_req_ie);
+- break;
+- default:
+- err = -EPERM;
+- brcmf_err("not suitable type\n");
+- goto exit;
+- }
+-
+- if (vndr_ie_len > mgmt_ie_buf_len) {
+- err = -ENOMEM;
+- brcmf_err("extra IE size too big\n");
+- goto exit;
+- }
+-
+- /* parse and save new vndr_ie in curr_ie_buff before comparing it */
+- if (vndr_ie_buf && vndr_ie_len && curr_ie_buf) {
+- ptr = curr_ie_buf;
+- brcmf_parse_vndr_ies(vndr_ie_buf, vndr_ie_len, &new_vndr_ies);
+- for (i = 0; i < new_vndr_ies.count; i++) {
+- vndrie_info = &new_vndr_ies.ie_info[i];
+- memcpy(ptr + parsed_ie_buf_len, vndrie_info->ie_ptr,
+- vndrie_info->ie_len);
+- parsed_ie_buf_len += vndrie_info->ie_len;
+- }
+- }
+-
+- if (mgmt_ie_buf && *mgmt_ie_len) {
+- if (parsed_ie_buf_len && (parsed_ie_buf_len == *mgmt_ie_len) &&
+- (memcmp(mgmt_ie_buf, curr_ie_buf,
+- parsed_ie_buf_len) == 0)) {
+- brcmf_dbg(TRACE, "Previous mgmt IE equals to current IE\n");
+- goto exit;
+- }
+-
+- /* parse old vndr_ie */
+- brcmf_parse_vndr_ies(mgmt_ie_buf, *mgmt_ie_len, &old_vndr_ies);
+-
+- /* make a command to delete old ie */
+- for (i = 0; i < old_vndr_ies.count; i++) {
+- vndrie_info = &old_vndr_ies.ie_info[i];
+-
+- brcmf_dbg(TRACE, "DEL ID : %d, Len: %d , OUI:%02x:%02x:%02x\n",
+- vndrie_info->vndrie.id,
+- vndrie_info->vndrie.len,
+- vndrie_info->vndrie.oui[0],
+- vndrie_info->vndrie.oui[1],
+- vndrie_info->vndrie.oui[2]);
+-
+- del_add_ie_buf_len = brcmf_vndr_ie(curr_ie_buf, pktflag,
+- vndrie_info->ie_ptr,
+- vndrie_info->ie_len,
+- "del");
+- curr_ie_buf += del_add_ie_buf_len;
+- total_ie_buf_len += del_add_ie_buf_len;
+- }
+- }
+-
+- *mgmt_ie_len = 0;
+- /* Add if there is any extra IE */
+- if (mgmt_ie_buf && parsed_ie_buf_len) {
+- ptr = mgmt_ie_buf;
+-
+- remained_buf_len = mgmt_ie_buf_len;
+-
+- /* make a command to add new ie */
+- for (i = 0; i < new_vndr_ies.count; i++) {
+- vndrie_info = &new_vndr_ies.ie_info[i];
+-
+- /* verify remained buf size before copy data */
+- if (remained_buf_len < (vndrie_info->vndrie.len +
+- VNDR_IE_VSIE_OFFSET)) {
+- brcmf_err("no space in mgmt_ie_buf: len left %d",
+- remained_buf_len);
+- break;
+- }
+- remained_buf_len -= (vndrie_info->ie_len +
+- VNDR_IE_VSIE_OFFSET);
+-
+- brcmf_dbg(TRACE, "ADDED ID : %d, Len: %d, OUI:%02x:%02x:%02x\n",
+- vndrie_info->vndrie.id,
+- vndrie_info->vndrie.len,
+- vndrie_info->vndrie.oui[0],
+- vndrie_info->vndrie.oui[1],
+- vndrie_info->vndrie.oui[2]);
+-
+- del_add_ie_buf_len = brcmf_vndr_ie(curr_ie_buf, pktflag,
+- vndrie_info->ie_ptr,
+- vndrie_info->ie_len,
+- "add");
+-
+- /* save the parsed IE in wl struct */
+- memcpy(ptr + (*mgmt_ie_len), vndrie_info->ie_ptr,
+- vndrie_info->ie_len);
+- *mgmt_ie_len += vndrie_info->ie_len;
+-
+- curr_ie_buf += del_add_ie_buf_len;
+- total_ie_buf_len += del_add_ie_buf_len;
+- }
+- }
+- if (total_ie_buf_len) {
+- err = brcmf_fil_bsscfg_data_set(ifp, "vndr_ie", iovar_ie_buf,
+- total_ie_buf_len);
+- if (err)
+- brcmf_err("vndr ie set error : %d\n", err);
+- }
+-
+-exit:
+- kfree(iovar_ie_buf);
+- return err;
+-}
+-
+-s32 brcmf_vif_clear_mgmt_ies(struct brcmf_cfg80211_vif *vif)
+-{
+- s32 pktflags[] = {
+- BRCMF_VNDR_IE_PRBREQ_FLAG,
+- BRCMF_VNDR_IE_PRBRSP_FLAG,
+- BRCMF_VNDR_IE_BEACON_FLAG
+- };
+- int i;
+-
+- for (i = 0; i < ARRAY_SIZE(pktflags); i++)
+- brcmf_vif_set_mgmt_ie(vif, pktflags[i], NULL, 0);
+-
+- memset(&vif->saved_ie, 0, sizeof(vif->saved_ie));
+- return 0;
+-}
+-
+-static s32
+-brcmf_config_ap_mgmt_ie(struct brcmf_cfg80211_vif *vif,
+- struct cfg80211_beacon_data *beacon)
+-{
+- s32 err;
+-
+- /* Set Beacon IEs to FW */
+- err = brcmf_vif_set_mgmt_ie(vif, BRCMF_VNDR_IE_BEACON_FLAG,
+- beacon->tail, beacon->tail_len);
+- if (err) {
+- brcmf_err("Set Beacon IE Failed\n");
+- return err;
+- }
+- brcmf_dbg(TRACE, "Applied Vndr IEs for Beacon\n");
+-
+- /* Set Probe Response IEs to FW */
+- err = brcmf_vif_set_mgmt_ie(vif, BRCMF_VNDR_IE_PRBRSP_FLAG,
+- beacon->proberesp_ies,
+- beacon->proberesp_ies_len);
+- if (err)
+- brcmf_err("Set Probe Resp IE Failed\n");
+- else
+- brcmf_dbg(TRACE, "Applied Vndr IEs for Probe Resp\n");
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_set_channel(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_if *ifp,
+- struct ieee80211_channel *channel)
+-{
+- u16 chanspec;
+- s32 err;
+-
+- brcmf_dbg(TRACE, "band=%d, center_freq=%d\n", channel->band,
+- channel->center_freq);
+-
+- chanspec = channel_to_chanspec(&cfg->d11inf, channel);
+- err = brcmf_fil_iovar_int_set(ifp, "chanspec", chanspec);
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
+- struct cfg80211_ap_settings *settings)
+-{
+- s32 ie_offset;
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_tlv *ssid_ie;
+- struct brcmf_ssid_le ssid_le;
+- s32 err = -EPERM;
+- struct brcmf_tlv *rsn_ie;
+- struct brcmf_vs_tlv *wpa_ie;
+- struct brcmf_join_params join_params;
+- enum nl80211_iftype dev_role;
+- struct brcmf_fil_bss_enable_le bss_enable;
+-
+- brcmf_dbg(TRACE, "channel_type=%d, beacon_interval=%d, dtim_period=%d,\n",
+- cfg80211_get_chandef_type(&settings->chandef),
+- settings->beacon_interval,
+- settings->dtim_period);
+- brcmf_dbg(TRACE, "ssid=%s(%zu), auth_type=%d, inactivity_timeout=%d\n",
+- settings->ssid, settings->ssid_len, settings->auth_type,
+- settings->inactivity_timeout);
+-
+- dev_role = ifp->vif->wdev.iftype;
+-
+- memset(&ssid_le, 0, sizeof(ssid_le));
+- if (settings->ssid == NULL || settings->ssid_len == 0) {
+- ie_offset = DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_FIXED_LEN;
+- ssid_ie = brcmf_parse_tlvs(
+- (u8 *)&settings->beacon.head[ie_offset],
+- settings->beacon.head_len - ie_offset,
+- WLAN_EID_SSID);
+- if (!ssid_ie)
+- return -EINVAL;
+-
+- memcpy(ssid_le.SSID, ssid_ie->data, ssid_ie->len);
+- ssid_le.SSID_len = cpu_to_le32(ssid_ie->len);
+- brcmf_dbg(TRACE, "SSID is (%s) in Head\n", ssid_le.SSID);
+- } else {
+- memcpy(ssid_le.SSID, settings->ssid, settings->ssid_len);
+- ssid_le.SSID_len = cpu_to_le32((u32)settings->ssid_len);
+- }
+-
+- brcmf_set_mpc(ifp, 0);
+- brcmf_configure_arp_offload(ifp, false);
+-
+- /* find the RSN_IE */
+- rsn_ie = brcmf_parse_tlvs((u8 *)settings->beacon.tail,
+- settings->beacon.tail_len, WLAN_EID_RSN);
+-
+- /* find the WPA_IE */
+- wpa_ie = brcmf_find_wpaie((u8 *)settings->beacon.tail,
+- settings->beacon.tail_len);
+-
+- if ((wpa_ie != NULL || rsn_ie != NULL)) {
+- brcmf_dbg(TRACE, "WPA(2) IE is found\n");
+- if (wpa_ie != NULL) {
+- /* WPA IE */
+- err = brcmf_configure_wpaie(ndev, wpa_ie, false);
+- if (err < 0)
+- goto exit;
+- } else {
+- /* RSN IE */
+- err = brcmf_configure_wpaie(ndev,
+- (struct brcmf_vs_tlv *)rsn_ie, true);
+- if (err < 0)
+- goto exit;
+- }
+- } else {
+- brcmf_dbg(TRACE, "No WPA(2) IEs found\n");
+- brcmf_configure_opensecurity(ifp);
+- }
+-
+- brcmf_config_ap_mgmt_ie(ifp->vif, &settings->beacon);
+-
+- err = brcmf_cfg80211_set_channel(cfg, ifp, settings->chandef.chan);
+- if (err < 0) {
+- brcmf_err("Set Channel failed, %d\n", err);
+- goto exit;
+- }
+-
+- if (settings->beacon_interval) {
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_BCNPRD,
+- settings->beacon_interval);
+- if (err < 0) {
+- brcmf_err("Beacon Interval Set Error, %d\n", err);
+- goto exit;
+- }
+- }
+- if (settings->dtim_period) {
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_DTIMPRD,
+- settings->dtim_period);
+- if (err < 0) {
+- brcmf_err("DTIM Interval Set Error, %d\n", err);
+- goto exit;
+- }
+- }
+-
+- if (dev_role == NL80211_IFTYPE_AP) {
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_DOWN, 1);
+- if (err < 0) {
+- brcmf_err("BRCMF_C_DOWN error %d\n", err);
+- goto exit;
+- }
+- brcmf_fil_iovar_int_set(ifp, "apsta", 0);
+- }
+-
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_INFRA, 1);
+- if (err < 0) {
+- brcmf_err("SET INFRA error %d\n", err);
+- goto exit;
+- }
+- if (dev_role == NL80211_IFTYPE_AP) {
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_AP, 1);
+- if (err < 0) {
+- brcmf_err("setting AP mode failed %d\n", err);
+- goto exit;
+- }
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 1);
+- if (err < 0) {
+- brcmf_err("BRCMF_C_UP error (%d)\n", err);
+- goto exit;
+- }
+-
+- memset(&join_params, 0, sizeof(join_params));
+- /* join parameters starts with ssid */
+- memcpy(&join_params.ssid_le, &ssid_le, sizeof(ssid_le));
+- /* create softap */
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
+- &join_params, sizeof(join_params));
+- if (err < 0) {
+- brcmf_err("SET SSID error (%d)\n", err);
+- goto exit;
+- }
+- brcmf_dbg(TRACE, "AP mode configuration complete\n");
+- } else {
+- err = brcmf_fil_bsscfg_data_set(ifp, "ssid", &ssid_le,
+- sizeof(ssid_le));
+- if (err < 0) {
+- brcmf_err("setting ssid failed %d\n", err);
+- goto exit;
+- }
+- bss_enable.bsscfg_idx = cpu_to_le32(ifp->bssidx);
+- bss_enable.enable = cpu_to_le32(1);
+- err = brcmf_fil_iovar_data_set(ifp, "bss", &bss_enable,
+- sizeof(bss_enable));
+- if (err < 0) {
+- brcmf_err("bss_enable config failed %d\n", err);
+- goto exit;
+- }
+-
+- brcmf_dbg(TRACE, "GO mode configuration complete\n");
+- }
+- clear_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);
+- set_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
+-
+-exit:
+- if (err) {
+- brcmf_set_mpc(ifp, 1);
+- brcmf_configure_arp_offload(ifp, true);
+- }
+- return err;
+-}
+-
+-static int brcmf_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- s32 err;
+- struct brcmf_fil_bss_enable_le bss_enable;
+- struct brcmf_join_params join_params;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (ifp->vif->wdev.iftype == NL80211_IFTYPE_AP) {
+- /* Due to most likely deauths outstanding we sleep */
+- /* first to make sure they get processed by fw. */
+- msleep(400);
+-
+- memset(&join_params, 0, sizeof(join_params));
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_SSID,
+- &join_params, sizeof(join_params));
+- if (err < 0)
+- brcmf_err("SET SSID error (%d)\n", err);
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 0);
+- if (err < 0)
+- brcmf_err("BRCMF_C_UP error %d\n", err);
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_AP, 0);
+- if (err < 0)
+- brcmf_err("setting AP mode failed %d\n", err);
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_INFRA, 0);
+- if (err < 0)
+- brcmf_err("setting INFRA mode failed %d\n", err);
+- } else {
+- bss_enable.bsscfg_idx = cpu_to_le32(ifp->bssidx);
+- bss_enable.enable = cpu_to_le32(0);
+- err = brcmf_fil_iovar_data_set(ifp, "bss", &bss_enable,
+- sizeof(bss_enable));
+- if (err < 0)
+- brcmf_err("bss_enable config failed %d\n", err);
+- }
+- brcmf_set_mpc(ifp, 1);
+- brcmf_configure_arp_offload(ifp, true);
+- set_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);
+- clear_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_cfg80211_change_beacon(struct wiphy *wiphy, struct net_device *ndev,
+- struct cfg80211_beacon_data *info)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- s32 err;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- err = brcmf_config_ap_mgmt_ie(ifp->vif, info);
+-
+- return err;
+-}
+-
+-static int
+-brcmf_cfg80211_del_station(struct wiphy *wiphy, struct net_device *ndev,
+- u8 *mac)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_scb_val_le scbval;
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- s32 err;
+-
+- if (!mac)
+- return -EFAULT;
+-
+- brcmf_dbg(TRACE, "Enter %pM\n", mac);
+-
+- if (ifp->vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif)
+- ifp = cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif->ifp;
+- if (!check_vif_up(ifp->vif))
+- return -EIO;
+-
+- memcpy(&scbval.ea, mac, ETH_ALEN);
+- scbval.val = cpu_to_le32(WLAN_REASON_DEAUTH_LEAVING);
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SCB_DEAUTHENTICATE_FOR_REASON,
+- &scbval, sizeof(scbval));
+- if (err)
+- brcmf_err("SCB_DEAUTHENTICATE_FOR_REASON failed %d\n", err);
+-
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-
+-static void
+-brcmf_cfg80211_mgmt_frame_register(struct wiphy *wiphy,
+- struct wireless_dev *wdev,
+- u16 frame_type, bool reg)
+-{
+- struct brcmf_cfg80211_vif *vif;
+- u16 mgmt_type;
+-
+- brcmf_dbg(TRACE, "Enter, frame_type %04x, reg=%d\n", frame_type, reg);
+-
+- mgmt_type = (frame_type & IEEE80211_FCTL_STYPE) >> 4;
+- vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
+- if (reg)
+- vif->mgmt_rx_reg |= BIT(mgmt_type);
+- else
+- vif->mgmt_rx_reg &= ~BIT(mgmt_type);
+-}
+-
+-
+-static int
+-brcmf_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
+- struct cfg80211_mgmt_tx_params *params, u64 *cookie)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct ieee80211_channel *chan = params->chan;
+- const u8 *buf = params->buf;
+- size_t len = params->len;
+- const struct ieee80211_mgmt *mgmt;
+- struct brcmf_cfg80211_vif *vif;
+- s32 err = 0;
+- s32 ie_offset;
+- s32 ie_len;
+- struct brcmf_fil_action_frame_le *action_frame;
+- struct brcmf_fil_af_params_le *af_params;
+- bool ack;
+- s32 chan_nr;
+- u32 freq;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- *cookie = 0;
+-
+- mgmt = (const struct ieee80211_mgmt *)buf;
+-
+- if (!ieee80211_is_mgmt(mgmt->frame_control)) {
+- brcmf_err("Driver only allows MGMT packet type\n");
+- return -EPERM;
+- }
+-
+- vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
+-
+- if (ieee80211_is_probe_resp(mgmt->frame_control)) {
+- /* Right now the only reason to get a probe response */
+- /* is for p2p listen response or for p2p GO from */
+- /* wpa_supplicant. Unfortunately the probe is send */
+- /* on primary ndev, while dongle wants it on the p2p */
+- /* vif. Since this is only reason for a probe */
+- /* response to be sent, the vif is taken from cfg. */
+- /* If ever desired to send proberesp for non p2p */
+- /* response then data should be checked for */
+- /* "DIRECT-". Note in future supplicant will take */
+- /* dedicated p2p wdev to do this and then this 'hack'*/
+- /* is not needed anymore. */
+- ie_offset = DOT11_MGMT_HDR_LEN +
+- DOT11_BCN_PRB_FIXED_LEN;
+- ie_len = len - ie_offset;
+- if (vif == cfg->p2p.bss_idx[P2PAPI_BSSCFG_PRIMARY].vif)
+- vif = cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif;
+- err = brcmf_vif_set_mgmt_ie(vif,
+- BRCMF_VNDR_IE_PRBRSP_FLAG,
+- &buf[ie_offset],
+- ie_len);
+- cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, true,
+- GFP_KERNEL);
+- } else if (ieee80211_is_action(mgmt->frame_control)) {
+- af_params = kzalloc(sizeof(*af_params), GFP_KERNEL);
+- if (af_params == NULL) {
+- brcmf_err("unable to allocate frame\n");
+- err = -ENOMEM;
+- goto exit;
+- }
+- action_frame = &af_params->action_frame;
+- /* Add the packet Id */
+- action_frame->packet_id = cpu_to_le32(*cookie);
+- /* Add BSSID */
+- memcpy(&action_frame->da[0], &mgmt->da[0], ETH_ALEN);
+- memcpy(&af_params->bssid[0], &mgmt->bssid[0], ETH_ALEN);
+- /* Add the length exepted for 802.11 header */
+- action_frame->len = cpu_to_le16(len - DOT11_MGMT_HDR_LEN);
+- /* Add the channel. Use the one specified as parameter if any or
+- * the current one (got from the firmware) otherwise
+- */
+- if (chan)
+- freq = chan->center_freq;
+- else
+- brcmf_fil_cmd_int_get(vif->ifp, BRCMF_C_GET_CHANNEL,
+- &freq);
+- chan_nr = ieee80211_frequency_to_channel(freq);
+- af_params->channel = cpu_to_le32(chan_nr);
+-
+- memcpy(action_frame->data, &buf[DOT11_MGMT_HDR_LEN],
+- le16_to_cpu(action_frame->len));
+-
+- brcmf_dbg(TRACE, "Action frame, cookie=%lld, len=%d, freq=%d\n",
+- *cookie, le16_to_cpu(action_frame->len), freq);
+-
+- ack = brcmf_p2p_send_action_frame(cfg, cfg_to_ndev(cfg),
+- af_params);
+-
+- cfg80211_mgmt_tx_status(wdev, *cookie, buf, len, ack,
+- GFP_KERNEL);
+- kfree(af_params);
+- } else {
+- brcmf_dbg(TRACE, "Unhandled, fc=%04x!!\n", mgmt->frame_control);
+- brcmf_dbg_hex_dump(true, buf, len, "payload, len=%Zu\n", len);
+- }
+-
+-exit:
+- return err;
+-}
+-
+-
+-static int
+-brcmf_cfg80211_cancel_remain_on_channel(struct wiphy *wiphy,
+- struct wireless_dev *wdev,
+- u64 cookie)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_cfg80211_vif *vif;
+- int err = 0;
+-
+- brcmf_dbg(TRACE, "Enter p2p listen cancel\n");
+-
+- vif = cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif;
+- if (vif == NULL) {
+- brcmf_err("No p2p device available for probe response\n");
+- err = -ENODEV;
+- goto exit;
+- }
+- brcmf_p2p_cancel_remain_on_channel(vif->ifp);
+-exit:
+- return err;
+-}
+-
+-static int brcmf_cfg80211_crit_proto_start(struct wiphy *wiphy,
+- struct wireless_dev *wdev,
+- enum nl80211_crit_proto_id proto,
+- u16 duration)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_cfg80211_vif *vif;
+-
+- vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
+-
+- /* only DHCP support for now */
+- if (proto != NL80211_CRIT_PROTO_DHCP)
+- return -EINVAL;
+-
+- /* suppress and abort scanning */
+- set_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
+- brcmf_abort_scanning(cfg);
+-
+- return brcmf_btcoex_set_mode(vif, BRCMF_BTCOEX_DISABLED, duration);
+-}
+-
+-static void brcmf_cfg80211_crit_proto_stop(struct wiphy *wiphy,
+- struct wireless_dev *wdev)
+-{
+- struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
+- struct brcmf_cfg80211_vif *vif;
+-
+- vif = container_of(wdev, struct brcmf_cfg80211_vif, wdev);
+-
+- brcmf_btcoex_set_mode(vif, BRCMF_BTCOEX_ENABLED, 0);
+- clear_bit(BRCMF_SCAN_STATUS_SUPPRESS, &cfg->scan_status);
+-}
+-
+-static int brcmf_convert_nl80211_tdls_oper(enum nl80211_tdls_operation oper)
+-{
+- int ret;
+-
+- switch (oper) {
+- case NL80211_TDLS_DISCOVERY_REQ:
+- ret = BRCMF_TDLS_MANUAL_EP_DISCOVERY;
+- break;
+- case NL80211_TDLS_SETUP:
+- ret = BRCMF_TDLS_MANUAL_EP_CREATE;
+- break;
+- case NL80211_TDLS_TEARDOWN:
+- ret = BRCMF_TDLS_MANUAL_EP_DELETE;
+- break;
+- default:
+- brcmf_err("unsupported operation: %d\n", oper);
+- ret = -EOPNOTSUPP;
+- }
+- return ret;
+-}
+-
+-static int brcmf_cfg80211_tdls_oper(struct wiphy *wiphy,
+- struct net_device *ndev, u8 *peer,
+- enum nl80211_tdls_operation oper)
+-{
+- struct brcmf_if *ifp;
+- struct brcmf_tdls_iovar_le info;
+- int ret = 0;
+-
+- ret = brcmf_convert_nl80211_tdls_oper(oper);
+- if (ret < 0)
+- return ret;
+-
+- ifp = netdev_priv(ndev);
+- memset(&info, 0, sizeof(info));
+- info.mode = (u8)ret;
+- if (peer)
+- memcpy(info.ea, peer, ETH_ALEN);
+-
+- ret = brcmf_fil_iovar_data_set(ifp, "tdls_endpoint",
+- &info, sizeof(info));
+- if (ret < 0)
+- brcmf_err("tdls_endpoint iovar failed: ret=%d\n", ret);
+-
+- return ret;
+-}
+-
+-static struct cfg80211_ops wl_cfg80211_ops = {
+- .add_virtual_intf = brcmf_cfg80211_add_iface,
+- .del_virtual_intf = brcmf_cfg80211_del_iface,
+- .change_virtual_intf = brcmf_cfg80211_change_iface,
+- .scan = brcmf_cfg80211_scan,
+- .set_wiphy_params = brcmf_cfg80211_set_wiphy_params,
+- .join_ibss = brcmf_cfg80211_join_ibss,
+- .leave_ibss = brcmf_cfg80211_leave_ibss,
+- .get_station = brcmf_cfg80211_get_station,
+- .set_tx_power = brcmf_cfg80211_set_tx_power,
+- .get_tx_power = brcmf_cfg80211_get_tx_power,
+- .add_key = brcmf_cfg80211_add_key,
+- .del_key = brcmf_cfg80211_del_key,
+- .get_key = brcmf_cfg80211_get_key,
+- .set_default_key = brcmf_cfg80211_config_default_key,
+- .set_default_mgmt_key = brcmf_cfg80211_config_default_mgmt_key,
+- .set_power_mgmt = brcmf_cfg80211_set_power_mgmt,
+- .connect = brcmf_cfg80211_connect,
+- .disconnect = brcmf_cfg80211_disconnect,
+- .suspend = brcmf_cfg80211_suspend,
+- .resume = brcmf_cfg80211_resume,
+- .set_pmksa = brcmf_cfg80211_set_pmksa,
+- .del_pmksa = brcmf_cfg80211_del_pmksa,
+- .flush_pmksa = brcmf_cfg80211_flush_pmksa,
+- .start_ap = brcmf_cfg80211_start_ap,
+- .stop_ap = brcmf_cfg80211_stop_ap,
+- .change_beacon = brcmf_cfg80211_change_beacon,
+- .del_station = brcmf_cfg80211_del_station,
+- .sched_scan_start = brcmf_cfg80211_sched_scan_start,
+- .sched_scan_stop = brcmf_cfg80211_sched_scan_stop,
+- .mgmt_frame_register = brcmf_cfg80211_mgmt_frame_register,
+- .mgmt_tx = brcmf_cfg80211_mgmt_tx,
+- .remain_on_channel = brcmf_p2p_remain_on_channel,
+- .cancel_remain_on_channel = brcmf_cfg80211_cancel_remain_on_channel,
+- .start_p2p_device = brcmf_p2p_start_device,
+- .stop_p2p_device = brcmf_p2p_stop_device,
+- .crit_proto_start = brcmf_cfg80211_crit_proto_start,
+- .crit_proto_stop = brcmf_cfg80211_crit_proto_stop,
+- .tdls_oper = brcmf_cfg80211_tdls_oper,
+- CFG80211_TESTMODE_CMD(brcmf_cfg80211_testmode)
+-};
+-
+-static s32 brcmf_nl80211_iftype_to_mode(enum nl80211_iftype type)
+-{
+- switch (type) {
+- case NL80211_IFTYPE_AP_VLAN:
+- case NL80211_IFTYPE_WDS:
+- case NL80211_IFTYPE_MONITOR:
+- case NL80211_IFTYPE_MESH_POINT:
+- return -ENOTSUPP;
+- case NL80211_IFTYPE_ADHOC:
+- return WL_MODE_IBSS;
+- case NL80211_IFTYPE_STATION:
+- case NL80211_IFTYPE_P2P_CLIENT:
+- return WL_MODE_BSS;
+- case NL80211_IFTYPE_AP:
+- case NL80211_IFTYPE_P2P_GO:
+- return WL_MODE_AP;
+- case NL80211_IFTYPE_P2P_DEVICE:
+- return WL_MODE_P2P;
+- case NL80211_IFTYPE_UNSPECIFIED:
+- default:
+- break;
+- }
+-
+- return -EINVAL;
+-}
+-
+-static void brcmf_wiphy_pno_params(struct wiphy *wiphy)
+-{
+- /* scheduled scan settings */
+- wiphy->max_sched_scan_ssids = BRCMF_PNO_MAX_PFN_COUNT;
+- wiphy->max_match_sets = BRCMF_PNO_MAX_PFN_COUNT;
+- wiphy->max_sched_scan_ie_len = BRCMF_SCAN_IE_LEN_MAX;
+- wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN;
+-}
+-
+-static const struct ieee80211_iface_limit brcmf_iface_limits[] = {
+- {
+- .max = 2,
+- .types = BIT(NL80211_IFTYPE_STATION) |
+- BIT(NL80211_IFTYPE_ADHOC) |
+- BIT(NL80211_IFTYPE_AP)
+- },
+- {
+- .max = 1,
+- .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
+- BIT(NL80211_IFTYPE_P2P_GO)
+- },
+- {
+- .max = 1,
+- .types = BIT(NL80211_IFTYPE_P2P_DEVICE)
+- }
+-};
+-static const struct ieee80211_iface_combination brcmf_iface_combos[] = {
+- {
+- .max_interfaces = BRCMF_IFACE_MAX_CNT,
+- .num_different_channels = 2,
+- .n_limits = ARRAY_SIZE(brcmf_iface_limits),
+- .limits = brcmf_iface_limits
+- }
+-};
+-
+-static const struct ieee80211_txrx_stypes
+-brcmf_txrx_stypes[NUM_NL80211_IFTYPES] = {
+- [NL80211_IFTYPE_STATION] = {
+- .tx = 0xffff,
+- .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
+- BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
+- },
+- [NL80211_IFTYPE_P2P_CLIENT] = {
+- .tx = 0xffff,
+- .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
+- BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
+- },
+- [NL80211_IFTYPE_P2P_GO] = {
+- .tx = 0xffff,
+- .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) |
+- BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) |
+- BIT(IEEE80211_STYPE_PROBE_REQ >> 4) |
+- BIT(IEEE80211_STYPE_DISASSOC >> 4) |
+- BIT(IEEE80211_STYPE_AUTH >> 4) |
+- BIT(IEEE80211_STYPE_DEAUTH >> 4) |
+- BIT(IEEE80211_STYPE_ACTION >> 4)
+- },
+- [NL80211_IFTYPE_P2P_DEVICE] = {
+- .tx = 0xffff,
+- .rx = BIT(IEEE80211_STYPE_ACTION >> 4) |
+- BIT(IEEE80211_STYPE_PROBE_REQ >> 4)
+- }
+-};
+-
+-static struct wiphy *brcmf_setup_wiphy(struct device *phydev)
+-{
+- struct wiphy *wiphy;
+- s32 err = 0;
+-
+- wiphy = wiphy_new(&wl_cfg80211_ops, sizeof(struct brcmf_cfg80211_info));
+- if (!wiphy) {
+- brcmf_err("Could not allocate wiphy device\n");
+- return ERR_PTR(-ENOMEM);
+- }
+- set_wiphy_dev(wiphy, phydev);
+- wiphy->max_scan_ssids = WL_NUM_SCAN_MAX;
+- wiphy->max_scan_ie_len = BRCMF_SCAN_IE_LEN_MAX;
+- wiphy->max_num_pmkids = WL_NUM_PMKIDS_MAX;
+- wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
+- BIT(NL80211_IFTYPE_ADHOC) |
+- BIT(NL80211_IFTYPE_AP) |
+- BIT(NL80211_IFTYPE_P2P_CLIENT) |
+- BIT(NL80211_IFTYPE_P2P_GO) |
+- BIT(NL80211_IFTYPE_P2P_DEVICE);
+- wiphy->iface_combinations = brcmf_iface_combos;
+- wiphy->n_iface_combinations = ARRAY_SIZE(brcmf_iface_combos);
+- wiphy->bands[IEEE80211_BAND_2GHZ] = &__wl_band_2ghz;
+- wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
+- wiphy->cipher_suites = __wl_cipher_suites;
+- wiphy->n_cipher_suites = ARRAY_SIZE(__wl_cipher_suites);
+- wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT |
+- WIPHY_FLAG_OFFCHAN_TX |
+- WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
+- WIPHY_FLAG_SUPPORTS_TDLS;
+- wiphy->mgmt_stypes = brcmf_txrx_stypes;
+- wiphy->max_remain_on_channel_duration = 5000;
+- brcmf_wiphy_pno_params(wiphy);
+- brcmf_dbg(INFO, "Registering custom regulatory\n");
+- wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG;
+- wiphy_apply_custom_regulatory(wiphy, &brcmf_regdom);
+- err = wiphy_register(wiphy);
+- if (err < 0) {
+- brcmf_err("Could not register wiphy device (%d)\n", err);
+- wiphy_free(wiphy);
+- return ERR_PTR(err);
+- }
+- return wiphy;
+-}
+-
+-struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
+- enum nl80211_iftype type,
+- bool pm_block)
+-{
+- struct brcmf_cfg80211_vif *vif;
+-
+- brcmf_dbg(TRACE, "allocating virtual interface (size=%zu)\n",
+- sizeof(*vif));
+- vif = kzalloc(sizeof(*vif), GFP_KERNEL);
+- if (!vif)
+- return ERR_PTR(-ENOMEM);
+-
+- vif->wdev.wiphy = cfg->wiphy;
+- vif->wdev.iftype = type;
+-
+- vif->mode = brcmf_nl80211_iftype_to_mode(type);
+- vif->pm_block = pm_block;
+- vif->roam_off = -1;
+-
+- brcmf_init_prof(&vif->profile);
+-
+- list_add_tail(&vif->list, &cfg->vif_list);
+- return vif;
+-}
+-
+-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif)
+-{
+- list_del(&vif->list);
+- kfree(vif);
+-}
+-
+-void brcmf_cfg80211_free_netdev(struct net_device *ndev)
+-{
+- struct brcmf_cfg80211_vif *vif;
+- struct brcmf_if *ifp;
+-
+- ifp = netdev_priv(ndev);
+- vif = ifp->vif;
+-
+- brcmf_free_vif(vif);
+- free_netdev(ndev);
+-}
+-
+-static bool brcmf_is_linkup(const struct brcmf_event_msg *e)
+-{
+- u32 event = e->event_code;
+- u32 status = e->status;
+-
+- if (event == BRCMF_E_SET_SSID && status == BRCMF_E_STATUS_SUCCESS) {
+- brcmf_dbg(CONN, "Processing set ssid\n");
+- return true;
+- }
+-
+- return false;
+-}
+-
+-static bool brcmf_is_linkdown(const struct brcmf_event_msg *e)
+-{
+- u32 event = e->event_code;
+- u16 flags = e->flags;
+-
+- if (event == BRCMF_E_LINK && (!(flags & BRCMF_EVENT_MSG_LINK))) {
+- brcmf_dbg(CONN, "Processing link down\n");
+- return true;
+- }
+- return false;
+-}
+-
+-static bool brcmf_is_nonetwork(struct brcmf_cfg80211_info *cfg,
+- const struct brcmf_event_msg *e)
+-{
+- u32 event = e->event_code;
+- u32 status = e->status;
+-
+- if (event == BRCMF_E_LINK && status == BRCMF_E_STATUS_NO_NETWORKS) {
+- brcmf_dbg(CONN, "Processing Link %s & no network found\n",
+- e->flags & BRCMF_EVENT_MSG_LINK ? "up" : "down");
+- return true;
+- }
+-
+- if (event == BRCMF_E_SET_SSID && status != BRCMF_E_STATUS_SUCCESS) {
+- brcmf_dbg(CONN, "Processing connecting & no network found\n");
+- return true;
+- }
+-
+- return false;
+-}
+-
+-static void brcmf_clear_assoc_ies(struct brcmf_cfg80211_info *cfg)
+-{
+- struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
+-
+- kfree(conn_info->req_ie);
+- conn_info->req_ie = NULL;
+- conn_info->req_ie_len = 0;
+- kfree(conn_info->resp_ie);
+- conn_info->resp_ie = NULL;
+- conn_info->resp_ie_len = 0;
+-}
+-
+-static s32 brcmf_get_assoc_ies(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_if *ifp)
+-{
+- struct brcmf_cfg80211_assoc_ielen_le *assoc_info;
+- struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
+- u32 req_len;
+- u32 resp_len;
+- s32 err = 0;
+-
+- brcmf_clear_assoc_ies(cfg);
+-
+- err = brcmf_fil_iovar_data_get(ifp, "assoc_info",
+- cfg->extra_buf, WL_ASSOC_INFO_MAX);
+- if (err) {
+- brcmf_err("could not get assoc info (%d)\n", err);
+- return err;
+- }
+- assoc_info =
+- (struct brcmf_cfg80211_assoc_ielen_le *)cfg->extra_buf;
+- req_len = le32_to_cpu(assoc_info->req_len);
+- resp_len = le32_to_cpu(assoc_info->resp_len);
+- if (req_len) {
+- err = brcmf_fil_iovar_data_get(ifp, "assoc_req_ies",
+- cfg->extra_buf,
+- WL_ASSOC_INFO_MAX);
+- if (err) {
+- brcmf_err("could not get assoc req (%d)\n", err);
+- return err;
+- }
+- conn_info->req_ie_len = req_len;
+- conn_info->req_ie =
+- kmemdup(cfg->extra_buf, conn_info->req_ie_len,
+- GFP_KERNEL);
+- } else {
+- conn_info->req_ie_len = 0;
+- conn_info->req_ie = NULL;
+- }
+- if (resp_len) {
+- err = brcmf_fil_iovar_data_get(ifp, "assoc_resp_ies",
+- cfg->extra_buf,
+- WL_ASSOC_INFO_MAX);
+- if (err) {
+- brcmf_err("could not get assoc resp (%d)\n", err);
+- return err;
+- }
+- conn_info->resp_ie_len = resp_len;
+- conn_info->resp_ie =
+- kmemdup(cfg->extra_buf, conn_info->resp_ie_len,
+- GFP_KERNEL);
+- } else {
+- conn_info->resp_ie_len = 0;
+- conn_info->resp_ie = NULL;
+- }
+- brcmf_dbg(CONN, "req len (%d) resp len (%d)\n",
+- conn_info->req_ie_len, conn_info->resp_ie_len);
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_bss_roaming_done(struct brcmf_cfg80211_info *cfg,
+- struct net_device *ndev,
+- const struct brcmf_event_msg *e)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
+- struct wiphy *wiphy = cfg_to_wiphy(cfg);
+- struct ieee80211_channel *notify_channel = NULL;
+- struct ieee80211_supported_band *band;
+- struct brcmf_bss_info_le *bi;
+- struct brcmu_chan ch;
+- u32 freq;
+- s32 err = 0;
+- u8 *buf;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- brcmf_get_assoc_ies(cfg, ifp);
+- memcpy(profile->bssid, e->addr, ETH_ALEN);
+- brcmf_update_bss_info(cfg, ifp);
+-
+- buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
+- if (buf == NULL) {
+- err = -ENOMEM;
+- goto done;
+- }
+-
+- /* data sent to dongle has to be little endian */
+- *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
+- err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSS_INFO,
+- buf, WL_BSS_INFO_MAX);
+-
+- if (err)
+- goto done;
+-
+- bi = (struct brcmf_bss_info_le *)(buf + 4);
+- ch.chspec = le16_to_cpu(bi->chanspec);
+- cfg->d11inf.decchspec(&ch);
+-
+- if (ch.band == BRCMU_CHAN_BAND_2G)
+- band = wiphy->bands[IEEE80211_BAND_2GHZ];
+- else
+- band = wiphy->bands[IEEE80211_BAND_5GHZ];
+-
+- freq = ieee80211_channel_to_frequency(ch.chnum, band->band);
+- notify_channel = ieee80211_get_channel(wiphy, freq);
+-
+-done:
+- kfree(buf);
+- cfg80211_roamed(ndev, notify_channel, (u8 *)profile->bssid,
+- conn_info->req_ie, conn_info->req_ie_len,
+- conn_info->resp_ie, conn_info->resp_ie_len, GFP_KERNEL);
+- brcmf_dbg(CONN, "Report roaming result\n");
+-
+- set_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state);
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_bss_connect_done(struct brcmf_cfg80211_info *cfg,
+- struct net_device *ndev, const struct brcmf_event_msg *e,
+- bool completed)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- struct brcmf_cfg80211_connect_info *conn_info = cfg_to_conn(cfg);
+- s32 err = 0;
+-
+- brcmf_dbg(TRACE, "Enter\n");
+-
+- if (test_and_clear_bit(BRCMF_VIF_STATUS_CONNECTING,
+- &ifp->vif->sme_state)) {
+- if (completed) {
+- brcmf_get_assoc_ies(cfg, ifp);
+- memcpy(profile->bssid, e->addr, ETH_ALEN);
+- brcmf_update_bss_info(cfg, ifp);
+- set_bit(BRCMF_VIF_STATUS_CONNECTED,
+- &ifp->vif->sme_state);
+- }
+- cfg80211_connect_result(ndev,
+- (u8 *)profile->bssid,
+- conn_info->req_ie,
+- conn_info->req_ie_len,
+- conn_info->resp_ie,
+- conn_info->resp_ie_len,
+- completed ? WLAN_STATUS_SUCCESS :
+- WLAN_STATUS_AUTH_TIMEOUT,
+- GFP_KERNEL);
+- brcmf_dbg(CONN, "Report connect result - connection %s\n",
+- completed ? "succeeded" : "failed");
+- }
+- brcmf_dbg(TRACE, "Exit\n");
+- return err;
+-}
+-
+-static s32
+-brcmf_notify_connect_status_ap(struct brcmf_cfg80211_info *cfg,
+- struct net_device *ndev,
+- const struct brcmf_event_msg *e, void *data)
+-{
+- static int generation;
+- u32 event = e->event_code;
+- u32 reason = e->reason;
+- struct station_info sinfo;
+-
+- brcmf_dbg(CONN, "event %d, reason %d\n", event, reason);
+- if (event == BRCMF_E_LINK && reason == BRCMF_E_REASON_LINK_BSSCFG_DIS &&
+- ndev != cfg_to_ndev(cfg)) {
+- brcmf_dbg(CONN, "AP mode link down\n");
+- complete(&cfg->vif_disabled);
+- return 0;
+- }
+-
+- if (((event == BRCMF_E_ASSOC_IND) || (event == BRCMF_E_REASSOC_IND)) &&
+- (reason == BRCMF_E_STATUS_SUCCESS)) {
+- memset(&sinfo, 0, sizeof(sinfo));
+- sinfo.filled = STATION_INFO_ASSOC_REQ_IES;
+- if (!data) {
+- brcmf_err("No IEs present in ASSOC/REASSOC_IND");
+- return -EINVAL;
+- }
+- sinfo.assoc_req_ies = data;
+- sinfo.assoc_req_ies_len = e->datalen;
+- generation++;
+- sinfo.generation = generation;
+- cfg80211_new_sta(ndev, e->addr, &sinfo, GFP_KERNEL);
+- } else if ((event == BRCMF_E_DISASSOC_IND) ||
+- (event == BRCMF_E_DEAUTH_IND) ||
+- (event == BRCMF_E_DEAUTH)) {
+- cfg80211_del_sta(ndev, e->addr, GFP_KERNEL);
+- }
+- return 0;
+-}
+-
+-static s32
+-brcmf_notify_connect_status(struct brcmf_if *ifp,
+- const struct brcmf_event_msg *e, void *data)
+-{
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+- struct net_device *ndev = ifp->ndev;
+- struct brcmf_cfg80211_profile *profile = &ifp->vif->profile;
+- s32 err = 0;
+-
+- if (ifp->vif->mode == WL_MODE_AP) {
+- err = brcmf_notify_connect_status_ap(cfg, ndev, e, data);
+- } else if (brcmf_is_linkup(e)) {
+- brcmf_dbg(CONN, "Linkup\n");
+- if (brcmf_is_ibssmode(ifp->vif)) {
+- memcpy(profile->bssid, e->addr, ETH_ALEN);
+- wl_inform_ibss(cfg, ndev, e->addr);
+- cfg80211_ibss_joined(ndev, e->addr, GFP_KERNEL);
+- clear_bit(BRCMF_VIF_STATUS_CONNECTING,
+- &ifp->vif->sme_state);
+- set_bit(BRCMF_VIF_STATUS_CONNECTED,
+- &ifp->vif->sme_state);
+- } else
+- brcmf_bss_connect_done(cfg, ndev, e, true);
+- } else if (brcmf_is_linkdown(e)) {
+- brcmf_dbg(CONN, "Linkdown\n");
+- if (!brcmf_is_ibssmode(ifp->vif)) {
+- brcmf_bss_connect_done(cfg, ndev, e, false);
+- if (test_and_clear_bit(BRCMF_VIF_STATUS_CONNECTED,
+- &ifp->vif->sme_state))
+- cfg80211_disconnected(ndev, 0, NULL, 0,
+- GFP_KERNEL);
+- }
+- brcmf_link_down(ifp->vif);
+- brcmf_init_prof(ndev_to_prof(ndev));
+- if (ndev != cfg_to_ndev(cfg))
+- complete(&cfg->vif_disabled);
+- } else if (brcmf_is_nonetwork(cfg, e)) {
+- if (brcmf_is_ibssmode(ifp->vif))
+- clear_bit(BRCMF_VIF_STATUS_CONNECTING,
+- &ifp->vif->sme_state);
+- else
+- brcmf_bss_connect_done(cfg, ndev, e, false);
+- }
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_notify_roaming_status(struct brcmf_if *ifp,
+- const struct brcmf_event_msg *e, void *data)
+-{
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+- s32 err = 0;
+- u32 event = e->event_code;
+- u32 status = e->status;
+-
+- if (event == BRCMF_E_ROAM && status == BRCMF_E_STATUS_SUCCESS) {
+- if (test_bit(BRCMF_VIF_STATUS_CONNECTED, &ifp->vif->sme_state))
+- brcmf_bss_roaming_done(cfg, ifp->ndev, e);
+- else
+- brcmf_bss_connect_done(cfg, ifp->ndev, e, true);
+- }
+-
+- return err;
+-}
+-
+-static s32
+-brcmf_notify_mic_status(struct brcmf_if *ifp,
+- const struct brcmf_event_msg *e, void *data)
+-{
+- u16 flags = e->flags;
+- enum nl80211_key_type key_type;
+-
+- if (flags & BRCMF_EVENT_MSG_GROUP)
+- key_type = NL80211_KEYTYPE_GROUP;
+- else
+- key_type = NL80211_KEYTYPE_PAIRWISE;
+-
+- cfg80211_michael_mic_failure(ifp->ndev, (u8 *)&e->addr, key_type, -1,
+- NULL, GFP_KERNEL);
+-
+- return 0;
+-}
+-
+-static s32 brcmf_notify_vif_event(struct brcmf_if *ifp,
+- const struct brcmf_event_msg *e, void *data)
+-{
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+- struct brcmf_if_event *ifevent = (struct brcmf_if_event *)data;
+- struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
+- struct brcmf_cfg80211_vif *vif;
+-
+- brcmf_dbg(TRACE, "Enter: action %u flags %u ifidx %u bsscfg %u\n",
+- ifevent->action, ifevent->flags, ifevent->ifidx,
+- ifevent->bssidx);
+-
+- mutex_lock(&event->vif_event_lock);
+- event->action = ifevent->action;
+- vif = event->vif;
+-
+- switch (ifevent->action) {
+- case BRCMF_E_IF_ADD:
+- /* waiting process may have timed out */
+- if (!cfg->vif_event.vif) {
+- mutex_unlock(&event->vif_event_lock);
+- return -EBADF;
+- }
+-
+- ifp->vif = vif;
+- vif->ifp = ifp;
+- if (ifp->ndev) {
+- vif->wdev.netdev = ifp->ndev;
+- ifp->ndev->ieee80211_ptr = &vif->wdev;
+- SET_NETDEV_DEV(ifp->ndev, wiphy_dev(cfg->wiphy));
+- }
+- mutex_unlock(&event->vif_event_lock);
+- wake_up(&event->vif_wq);
+- return 0;
+-
+- case BRCMF_E_IF_DEL:
+- mutex_unlock(&event->vif_event_lock);
+- /* event may not be upon user request */
+- if (brcmf_cfg80211_vif_event_armed(cfg))
+- wake_up(&event->vif_wq);
+- return 0;
+-
+- case BRCMF_E_IF_CHANGE:
+- mutex_unlock(&event->vif_event_lock);
+- wake_up(&event->vif_wq);
+- return 0;
+-
+- default:
+- mutex_unlock(&event->vif_event_lock);
+- break;
+- }
+- return -EINVAL;
+-}
+-
+-static void brcmf_init_conf(struct brcmf_cfg80211_conf *conf)
+-{
+- conf->frag_threshold = (u32)-1;
+- conf->rts_threshold = (u32)-1;
+- conf->retry_short = (u32)-1;
+- conf->retry_long = (u32)-1;
+- conf->tx_power = -1;
+-}
+-
+-static void brcmf_register_event_handlers(struct brcmf_cfg80211_info *cfg)
+-{
+- brcmf_fweh_register(cfg->pub, BRCMF_E_LINK,
+- brcmf_notify_connect_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_DEAUTH_IND,
+- brcmf_notify_connect_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_DEAUTH,
+- brcmf_notify_connect_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_DISASSOC_IND,
+- brcmf_notify_connect_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_ASSOC_IND,
+- brcmf_notify_connect_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_REASSOC_IND,
+- brcmf_notify_connect_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_ROAM,
+- brcmf_notify_roaming_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_MIC_ERROR,
+- brcmf_notify_mic_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_SET_SSID,
+- brcmf_notify_connect_status);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_PFN_NET_FOUND,
+- brcmf_notify_sched_scan_results);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_IF,
+- brcmf_notify_vif_event);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_P2P_PROBEREQ_MSG,
+- brcmf_p2p_notify_rx_mgmt_p2p_probereq);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_P2P_DISC_LISTEN_COMPLETE,
+- brcmf_p2p_notify_listen_complete);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_ACTION_FRAME_RX,
+- brcmf_p2p_notify_action_frame_rx);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_ACTION_FRAME_COMPLETE,
+- brcmf_p2p_notify_action_tx_complete);
+- brcmf_fweh_register(cfg->pub, BRCMF_E_ACTION_FRAME_OFF_CHAN_COMPLETE,
+- brcmf_p2p_notify_action_tx_complete);
+-}
+-
+-static void brcmf_deinit_priv_mem(struct brcmf_cfg80211_info *cfg)
+-{
+- kfree(cfg->conf);
+- cfg->conf = NULL;
+- kfree(cfg->escan_ioctl_buf);
+- cfg->escan_ioctl_buf = NULL;
+- kfree(cfg->extra_buf);
+- cfg->extra_buf = NULL;
+- kfree(cfg->pmk_list);
+- cfg->pmk_list = NULL;
+-}
+-
+-static s32 brcmf_init_priv_mem(struct brcmf_cfg80211_info *cfg)
+-{
+- cfg->conf = kzalloc(sizeof(*cfg->conf), GFP_KERNEL);
+- if (!cfg->conf)
+- goto init_priv_mem_out;
+- cfg->escan_ioctl_buf = kzalloc(BRCMF_DCMD_MEDLEN, GFP_KERNEL);
+- if (!cfg->escan_ioctl_buf)
+- goto init_priv_mem_out;
+- cfg->extra_buf = kzalloc(WL_EXTRA_BUF_MAX, GFP_KERNEL);
+- if (!cfg->extra_buf)
+- goto init_priv_mem_out;
+- cfg->pmk_list = kzalloc(sizeof(*cfg->pmk_list), GFP_KERNEL);
+- if (!cfg->pmk_list)
+- goto init_priv_mem_out;
+-
+- return 0;
+-
+-init_priv_mem_out:
+- brcmf_deinit_priv_mem(cfg);
+-
+- return -ENOMEM;
+-}
+-
+-static s32 wl_init_priv(struct brcmf_cfg80211_info *cfg)
+-{
+- s32 err = 0;
+-
+- cfg->scan_request = NULL;
+- cfg->pwr_save = true;
+- cfg->roam_on = true; /* roam on & off switch.
+- we enable roam per default */
+- cfg->active_scan = true; /* we do active scan for
+- specific scan per default */
+- cfg->dongle_up = false; /* dongle is not up yet */
+- err = brcmf_init_priv_mem(cfg);
+- if (err)
+- return err;
+- brcmf_register_event_handlers(cfg);
+- mutex_init(&cfg->usr_sync);
+- brcmf_init_escan(cfg);
+- brcmf_init_conf(cfg->conf);
+- init_completion(&cfg->vif_disabled);
+- return err;
+-}
+-
+-static void wl_deinit_priv(struct brcmf_cfg80211_info *cfg)
+-{
+- cfg->dongle_up = false; /* dongle down */
+- brcmf_abort_scanning(cfg);
+- brcmf_deinit_priv_mem(cfg);
+-}
+-
+-static void init_vif_event(struct brcmf_cfg80211_vif_event *event)
+-{
+- init_waitqueue_head(&event->vif_wq);
+- mutex_init(&event->vif_event_lock);
+-}
+-
+-struct brcmf_cfg80211_info *brcmf_cfg80211_attach(struct brcmf_pub *drvr,
+- struct device *busdev)
+-{
+- struct net_device *ndev = drvr->iflist[0]->ndev;
+- struct brcmf_cfg80211_info *cfg;
+- struct wiphy *wiphy;
+- struct brcmf_cfg80211_vif *vif;
+- struct brcmf_if *ifp;
+- s32 err = 0;
+- s32 io_type;
+-
+- if (!ndev) {
+- brcmf_err("ndev is invalid\n");
+- return NULL;
+- }
+-
+- ifp = netdev_priv(ndev);
+- wiphy = brcmf_setup_wiphy(busdev);
+- if (IS_ERR(wiphy))
+- return NULL;
+-
+- cfg = wiphy_priv(wiphy);
+- cfg->wiphy = wiphy;
+- cfg->pub = drvr;
+- init_vif_event(&cfg->vif_event);
+- INIT_LIST_HEAD(&cfg->vif_list);
+-
+- vif = brcmf_alloc_vif(cfg, NL80211_IFTYPE_STATION, false);
+- if (IS_ERR(vif)) {
+- wiphy_free(wiphy);
+- return NULL;
+- }
+-
+- vif->ifp = ifp;
+- vif->wdev.netdev = ndev;
+- ndev->ieee80211_ptr = &vif->wdev;
+- SET_NETDEV_DEV(ndev, wiphy_dev(cfg->wiphy));
+-
+- err = wl_init_priv(cfg);
+- if (err) {
+- brcmf_err("Failed to init iwm_priv (%d)\n", err);
+- goto cfg80211_attach_out;
+- }
+- ifp->vif = vif;
+-
+- err = brcmf_p2p_attach(cfg);
+- if (err) {
+- brcmf_err("P2P initilisation failed (%d)\n", err);
+- goto cfg80211_p2p_attach_out;
+- }
+- err = brcmf_btcoex_attach(cfg);
+- if (err) {
+- brcmf_err("BT-coex initialisation failed (%d)\n", err);
+- brcmf_p2p_detach(&cfg->p2p);
+- goto cfg80211_p2p_attach_out;
+- }
+-
+- err = brcmf_fil_iovar_int_set(ifp, "tdls_enable", 1);
+- if (err) {
+- brcmf_dbg(INFO, "TDLS not enabled (%d)\n", err);
+- wiphy->flags &= ~WIPHY_FLAG_SUPPORTS_TDLS;
+- }
+-
+- err = brcmf_fil_cmd_int_get(ifp, BRCMF_C_GET_VERSION,
+- &io_type);
+- if (err) {
+- brcmf_err("Failed to get D11 version (%d)\n", err);
+- goto cfg80211_p2p_attach_out;
+- }
+- cfg->d11inf.io_type = (u8)io_type;
+- brcmu_d11_attach(&cfg->d11inf);
+-
+- return cfg;
+-
+-cfg80211_p2p_attach_out:
+- wl_deinit_priv(cfg);
+-
+-cfg80211_attach_out:
+- brcmf_free_vif(vif);
+- return NULL;
+-}
+-
+-void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg)
+-{
+- if (!cfg)
+- return;
+-
+- WARN_ON(!list_empty(&cfg->vif_list));
+- wiphy_unregister(cfg->wiphy);
+- brcmf_btcoex_detach(cfg);
+- wl_deinit_priv(cfg);
+- wiphy_free(cfg->wiphy);
+-}
+-
+-static s32
+-brcmf_dongle_roam(struct brcmf_if *ifp, u32 roamvar, u32 bcn_timeout)
+-{
+- s32 err = 0;
+- __le32 roamtrigger[2];
+- __le32 roam_delta[2];
+-
+- /*
+- * Setup timeout if Beacons are lost and roam is
+- * off to report link down
+- */
+- if (roamvar) {
+- err = brcmf_fil_iovar_int_set(ifp, "bcn_timeout", bcn_timeout);
+- if (err) {
+- brcmf_err("bcn_timeout error (%d)\n", err);
+- goto dongle_rom_out;
+- }
+- }
+-
+- /*
+- * Enable/Disable built-in roaming to allow supplicant
+- * to take care of roaming
+- */
+- brcmf_dbg(INFO, "Internal Roaming = %s\n", roamvar ? "Off" : "On");
+- err = brcmf_fil_iovar_int_set(ifp, "roam_off", roamvar);
+- if (err) {
+- brcmf_err("roam_off error (%d)\n", err);
+- goto dongle_rom_out;
+- }
+-
+- roamtrigger[0] = cpu_to_le32(WL_ROAM_TRIGGER_LEVEL);
+- roamtrigger[1] = cpu_to_le32(BRCM_BAND_ALL);
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_ROAM_TRIGGER,
+- (void *)roamtrigger, sizeof(roamtrigger));
+- if (err) {
+- brcmf_err("WLC_SET_ROAM_TRIGGER error (%d)\n", err);
+- goto dongle_rom_out;
+- }
+-
+- roam_delta[0] = cpu_to_le32(WL_ROAM_DELTA);
+- roam_delta[1] = cpu_to_le32(BRCM_BAND_ALL);
+- err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_ROAM_DELTA,
+- (void *)roam_delta, sizeof(roam_delta));
+- if (err) {
+- brcmf_err("WLC_SET_ROAM_DELTA error (%d)\n", err);
+- goto dongle_rom_out;
+- }
+-
+-dongle_rom_out:
+- return err;
+-}
+-
+-static s32
+-brcmf_dongle_scantime(struct brcmf_if *ifp, s32 scan_assoc_time,
+- s32 scan_unassoc_time, s32 scan_passive_time)
+-{
+- s32 err = 0;
+-
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_CHANNEL_TIME,
+- scan_assoc_time);
+- if (err) {
+- if (err == -EOPNOTSUPP)
+- brcmf_dbg(INFO, "Scan assoc time is not supported\n");
+- else
+- brcmf_err("Scan assoc time error (%d)\n", err);
+- goto dongle_scantime_out;
+- }
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_UNASSOC_TIME,
+- scan_unassoc_time);
+- if (err) {
+- if (err == -EOPNOTSUPP)
+- brcmf_dbg(INFO, "Scan unassoc time is not supported\n");
+- else
+- brcmf_err("Scan unassoc time error (%d)\n", err);
+- goto dongle_scantime_out;
+- }
+-
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_SCAN_PASSIVE_TIME,
+- scan_passive_time);
+- if (err) {
+- if (err == -EOPNOTSUPP)
+- brcmf_dbg(INFO, "Scan passive time is not supported\n");
+- else
+- brcmf_err("Scan passive time error (%d)\n", err);
+- goto dongle_scantime_out;
+- }
+-
+-dongle_scantime_out:
+- return err;
+-}
+-
+-
+-static s32 brcmf_construct_reginfo(struct brcmf_cfg80211_info *cfg,
+- u32 bw_cap[])
+-{
+- struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
+- struct ieee80211_channel *band_chan_arr;
+- struct brcmf_chanspec_list *list;
+- struct brcmu_chan ch;
+- s32 err;
+- u8 *pbuf;
+- u32 i, j;
+- u32 total;
+- enum ieee80211_band band;
+- u32 channel;
+- u32 *n_cnt;
+- u32 index;
+- u32 ht40_flag;
+- bool update;
+- u32 array_size;
+-
+- pbuf = kzalloc(BRCMF_DCMD_MEDLEN, GFP_KERNEL);
+-
+- if (pbuf == NULL)
+- return -ENOMEM;
+-
+- list = (struct brcmf_chanspec_list *)pbuf;
+-
+- err = brcmf_fil_iovar_data_get(ifp, "chanspecs", pbuf,
+- BRCMF_DCMD_MEDLEN);
+- if (err) {
+- brcmf_err("get chanspecs error (%d)\n", err);
+- goto exit;
+- }
+-
+- __wl_band_2ghz.n_channels = 0;
+- __wl_band_5ghz_a.n_channels = 0;
+-
+- total = le32_to_cpu(list->count);
+- for (i = 0; i < total; i++) {
+- ch.chspec = (u16)le32_to_cpu(list->element[i]);
+- cfg->d11inf.decchspec(&ch);
+-
+- if (ch.band == BRCMU_CHAN_BAND_2G) {
+- band_chan_arr = __wl_2ghz_channels;
+- array_size = ARRAY_SIZE(__wl_2ghz_channels);
+- n_cnt = &__wl_band_2ghz.n_channels;
+- band = IEEE80211_BAND_2GHZ;
+- } else if (ch.band == BRCMU_CHAN_BAND_5G) {
+- band_chan_arr = __wl_5ghz_a_channels;
+- array_size = ARRAY_SIZE(__wl_5ghz_a_channels);
+- n_cnt = &__wl_band_5ghz_a.n_channels;
+- band = IEEE80211_BAND_5GHZ;
+- } else {
+- brcmf_err("Invalid channel Spec. 0x%x.\n", ch.chspec);
+- continue;
+- }
+- if (!(bw_cap[band] & WLC_BW_40MHZ_BIT) &&
+- ch.bw == BRCMU_CHAN_BW_40)
+- continue;
+- update = false;
+- for (j = 0; (j < *n_cnt && (*n_cnt < array_size)); j++) {
+- if (band_chan_arr[j].hw_value == ch.chnum) {
+- update = true;
+- break;
+- }
+- }
+- if (update)
+- index = j;
+- else
+- index = *n_cnt;
+- if (index < array_size) {
+- band_chan_arr[index].center_freq =
+- ieee80211_channel_to_frequency(ch.chnum, band);
+- band_chan_arr[index].hw_value = ch.chnum;
+-
+- brcmf_err("channel %d: f=%d bw=%d sb=%d\n",
+- ch.chnum, band_chan_arr[index].center_freq,
+- ch.bw, ch.sb);
+- if (ch.bw == BRCMU_CHAN_BW_40) {
+- /* assuming the order is HT20, HT40 Upper,
+- * HT40 lower from chanspecs
+- */
+- ht40_flag = band_chan_arr[index].flags &
+- IEEE80211_CHAN_NO_HT40;
+- if (ch.sb == BRCMU_CHAN_SB_U) {
+- if (ht40_flag == IEEE80211_CHAN_NO_HT40)
+- band_chan_arr[index].flags &=
+- ~IEEE80211_CHAN_NO_HT40;
+- band_chan_arr[index].flags |=
+- IEEE80211_CHAN_NO_HT40PLUS;
+- } else {
+- /* It should be one of
+- * IEEE80211_CHAN_NO_HT40 or
+- * IEEE80211_CHAN_NO_HT40PLUS
+- */
+- band_chan_arr[index].flags &=
+- ~IEEE80211_CHAN_NO_HT40;
+- if (ht40_flag == IEEE80211_CHAN_NO_HT40)
+- band_chan_arr[index].flags |=
+- IEEE80211_CHAN_NO_HT40MINUS;
+- }
+- } else {
+- band_chan_arr[index].flags =
+- IEEE80211_CHAN_NO_HT40;
+- ch.bw = BRCMU_CHAN_BW_20;
+- cfg->d11inf.encchspec(&ch);
+- channel = ch.chspec;
+- err = brcmf_fil_bsscfg_int_get(ifp,
+- "per_chan_info",
+- &channel);
+- if (!err) {
+- if (channel & WL_CHAN_RADAR)
+- band_chan_arr[index].flags |=
+- (IEEE80211_CHAN_RADAR |
+- IEEE80211_CHAN_NO_IR);
+- if (channel & WL_CHAN_PASSIVE)
+- band_chan_arr[index].flags |=
+- IEEE80211_CHAN_NO_IR;
+- }
+- }
+- if (!update)
+- (*n_cnt)++;
+- }
+- }
+-exit:
+- kfree(pbuf);
+- return err;
+-}
+-
+-static void brcmf_get_bwcap(struct brcmf_if *ifp, u32 bw_cap[])
+-{
+- u32 band, mimo_bwcap;
+- int err;
+-
+- band = WLC_BAND_2G;
+- err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
+- if (!err) {
+- bw_cap[IEEE80211_BAND_2GHZ] = band;
+- band = WLC_BAND_5G;
+- err = brcmf_fil_iovar_int_get(ifp, "bw_cap", &band);
+- if (!err) {
+- bw_cap[IEEE80211_BAND_5GHZ] = band;
+- return;
+- }
+- WARN_ON(1);
+- return;
+- }
+- brcmf_dbg(INFO, "fallback to mimo_bw_cap info\n");
+- mimo_bwcap = 0;
+- err = brcmf_fil_iovar_int_get(ifp, "mimo_bw_cap", &mimo_bwcap);
+- if (err)
+- /* assume 20MHz if firmware does not give a clue */
+- mimo_bwcap = WLC_N_BW_20ALL;
+-
+- switch (mimo_bwcap) {
+- case WLC_N_BW_40ALL:
+- bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_40MHZ_BIT;
+- /* fall-thru */
+- case WLC_N_BW_20IN2G_40IN5G:
+- bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_40MHZ_BIT;
+- /* fall-thru */
+- case WLC_N_BW_20ALL:
+- bw_cap[IEEE80211_BAND_2GHZ] |= WLC_BW_20MHZ_BIT;
+- bw_cap[IEEE80211_BAND_5GHZ] |= WLC_BW_20MHZ_BIT;
+- break;
+- default:
+- brcmf_err("invalid mimo_bw_cap value\n");
+- }
+-}
+-
+-static s32 brcmf_update_wiphybands(struct brcmf_cfg80211_info *cfg)
+-{
+- struct brcmf_if *ifp = netdev_priv(cfg_to_ndev(cfg));
+- struct wiphy *wiphy;
+- s32 phy_list;
+- u32 band_list[3];
+- u32 nmode;
+- u32 bw_cap[2] = { 0, 0 };
+- s8 phy;
+- s32 err;
+- u32 nband;
+- s32 i;
+- struct ieee80211_supported_band *bands[2] = { NULL, NULL };
+- struct ieee80211_supported_band *band;
+-
+- err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_PHYLIST,
+- &phy_list, sizeof(phy_list));
+- if (err) {
+- brcmf_err("BRCMF_C_GET_PHYLIST error (%d)\n", err);
+- return err;
+- }
+-
+- phy = ((char *)&phy_list)[0];
+- brcmf_dbg(INFO, "BRCMF_C_GET_PHYLIST reported: %c phy\n", phy);
+-
+-
+- err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BANDLIST,
+- &band_list, sizeof(band_list));
+- if (err) {
+- brcmf_err("BRCMF_C_GET_BANDLIST error (%d)\n", err);
+- return err;
+- }
+- brcmf_dbg(INFO, "BRCMF_C_GET_BANDLIST reported: 0x%08x 0x%08x 0x%08x phy\n",
+- band_list[0], band_list[1], band_list[2]);
+-
+- err = brcmf_fil_iovar_int_get(ifp, "nmode", &nmode);
+- if (err) {
+- brcmf_err("nmode error (%d)\n", err);
+- } else {
+- brcmf_get_bwcap(ifp, bw_cap);
+- }
+- brcmf_dbg(INFO, "nmode=%d, bw_cap=(%d, %d)\n", nmode,
+- bw_cap[IEEE80211_BAND_2GHZ], bw_cap[IEEE80211_BAND_5GHZ]);
+-
+- err = brcmf_construct_reginfo(cfg, bw_cap);
+- if (err) {
+- brcmf_err("brcmf_construct_reginfo failed (%d)\n", err);
+- return err;
+- }
+-
+- nband = band_list[0];
+-
+- for (i = 1; i <= nband && i < ARRAY_SIZE(band_list); i++) {
+- band = NULL;
+- if ((band_list[i] == WLC_BAND_5G) &&
+- (__wl_band_5ghz_a.n_channels > 0))
+- band = &__wl_band_5ghz_a;
+- else if ((band_list[i] == WLC_BAND_2G) &&
+- (__wl_band_2ghz.n_channels > 0))
+- band = &__wl_band_2ghz;
+- else
+- continue;
+-
+- if (bw_cap[band->band] & WLC_BW_40MHZ_BIT) {
+- band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
+- band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
+- }
+- band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
+- band->ht_cap.cap |= IEEE80211_HT_CAP_DSSSCCK40;
+- band->ht_cap.ht_supported = true;
+- band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
+- band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
+- /* An HT shall support all EQM rates for one spatial
+- * stream
+- */
+- band->ht_cap.mcs.rx_mask[0] = 0xff;
+- band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
+- bands[band->band] = band;
+- }
+-
+- wiphy = cfg_to_wiphy(cfg);
+- wiphy->bands[IEEE80211_BAND_2GHZ] = bands[IEEE80211_BAND_2GHZ];
+- wiphy->bands[IEEE80211_BAND_5GHZ] = bands[IEEE80211_BAND_5GHZ];
+- wiphy_apply_custom_regulatory(wiphy, &brcmf_regdom);
+-
+- return err;
+-}
+-
+-
+-static s32 brcmf_dongle_probecap(struct brcmf_cfg80211_info *cfg)
+-{
+- return brcmf_update_wiphybands(cfg);
+-}
+-
+-static s32 brcmf_config_dongle(struct brcmf_cfg80211_info *cfg)
+-{
+- struct net_device *ndev;
+- struct wireless_dev *wdev;
+- struct brcmf_if *ifp;
+- s32 power_mode;
+- s32 err = 0;
+-
+- if (cfg->dongle_up)
+- return err;
+-
+- ndev = cfg_to_ndev(cfg);
+- wdev = ndev->ieee80211_ptr;
+- ifp = netdev_priv(ndev);
+-
+- /* make sure RF is ready for work */
+- brcmf_fil_cmd_int_set(ifp, BRCMF_C_UP, 0);
+-
+- brcmf_dongle_scantime(ifp, WL_SCAN_CHANNEL_TIME,
+- WL_SCAN_UNASSOC_TIME, WL_SCAN_PASSIVE_TIME);
+-
+- power_mode = cfg->pwr_save ? PM_FAST : PM_OFF;
+- err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, power_mode);
+- if (err)
+- goto default_conf_out;
+- brcmf_dbg(INFO, "power save set to %s\n",
+- (power_mode ? "enabled" : "disabled"));
+-
+- err = brcmf_dongle_roam(ifp, (cfg->roam_on ? 0 : 1), WL_BEACON_TIMEOUT);
+- if (err)
+- goto default_conf_out;
+- err = brcmf_cfg80211_change_iface(wdev->wiphy, ndev, wdev->iftype,
+- NULL, NULL);
+- if (err)
+- goto default_conf_out;
+- err = brcmf_dongle_probecap(cfg);
+- if (err)
+- goto default_conf_out;
+-
+- brcmf_configure_arp_offload(ifp, true);
+-
+- cfg->dongle_up = true;
+-default_conf_out:
+-
+- return err;
+-
+-}
+-
+-static s32 __brcmf_cfg80211_up(struct brcmf_if *ifp)
+-{
+- set_bit(BRCMF_VIF_STATUS_READY, &ifp->vif->sme_state);
+-
+- return brcmf_config_dongle(ifp->drvr->config);
+-}
+-
+-static s32 __brcmf_cfg80211_down(struct brcmf_if *ifp)
+-{
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+-
+- /*
+- * While going down, if associated with AP disassociate
+- * from AP to save power
+- */
+- if (check_vif_up(ifp->vif)) {
+- brcmf_link_down(ifp->vif);
+-
+- /* Make sure WPA_Supplicant receives all the event
+- generated due to DISASSOC call to the fw to keep
+- the state fw and WPA_Supplicant state consistent
+- */
+- brcmf_delay(500);
+- }
+-
+- brcmf_abort_scanning(cfg);
+- clear_bit(BRCMF_VIF_STATUS_READY, &ifp->vif->sme_state);
+-
+- return 0;
+-}
+-
+-s32 brcmf_cfg80211_up(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+- s32 err = 0;
+-
+- mutex_lock(&cfg->usr_sync);
+- err = __brcmf_cfg80211_up(ifp);
+- mutex_unlock(&cfg->usr_sync);
+-
+- return err;
+-}
+-
+-s32 brcmf_cfg80211_down(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- struct brcmf_cfg80211_info *cfg = ifp->drvr->config;
+- s32 err = 0;
+-
+- mutex_lock(&cfg->usr_sync);
+- err = __brcmf_cfg80211_down(ifp);
+- mutex_unlock(&cfg->usr_sync);
+-
+- return err;
+-}
+-
+-enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp)
+-{
+- struct wireless_dev *wdev = &ifp->vif->wdev;
+-
+- return wdev->iftype;
+-}
+-
+-u32 wl_get_vif_state_all(struct brcmf_cfg80211_info *cfg, unsigned long state)
+-{
+- struct brcmf_cfg80211_vif *vif;
+- bool result = 0;
+-
+- list_for_each_entry(vif, &cfg->vif_list, list) {
+- if (test_bit(state, &vif->sme_state))
+- result++;
+- }
+- return result;
+-}
+-
+-static inline bool vif_event_equals(struct brcmf_cfg80211_vif_event *event,
+- u8 action)
+-{
+- u8 evt_action;
+-
+- mutex_lock(&event->vif_event_lock);
+- evt_action = event->action;
+- mutex_unlock(&event->vif_event_lock);
+- return evt_action == action;
+-}
+-
+-void brcmf_cfg80211_arm_vif_event(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_cfg80211_vif *vif)
+-{
+- struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
+-
+- mutex_lock(&event->vif_event_lock);
+- event->vif = vif;
+- event->action = 0;
+- mutex_unlock(&event->vif_event_lock);
+-}
+-
+-bool brcmf_cfg80211_vif_event_armed(struct brcmf_cfg80211_info *cfg)
+-{
+- struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
+- bool armed;
+-
+- mutex_lock(&event->vif_event_lock);
+- armed = event->vif != NULL;
+- mutex_unlock(&event->vif_event_lock);
+-
+- return armed;
+-}
+-int brcmf_cfg80211_wait_vif_event_timeout(struct brcmf_cfg80211_info *cfg,
+- u8 action, ulong timeout)
+-{
+- struct brcmf_cfg80211_vif_event *event = &cfg->vif_event;
+-
+- return wait_event_timeout(event->vif_wq,
+- vif_event_equals(event, action), timeout);
+-}
+-
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h 1970-01-01 01:00:00.000000000 +0100
+@@ -1,510 +0,0 @@
+-/*
+- * Copyright (c) 2010 Broadcom Corporation
+- *
+- * Permission to use, copy, modify, and/or distribute this software for any
+- * purpose with or without fee is hereby granted, provided that the above
+- * copyright notice and this permission notice appear in all copies.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+- */
+-
+-#ifndef _wl_cfg80211_h_
+-#define _wl_cfg80211_h_
+-
+-/* for brcmu_d11inf */
+-#include <brcmu_d11.h>
+-
+-#define WL_NUM_SCAN_MAX 10
+-#define WL_NUM_PMKIDS_MAX MAXPMKID
+-#define WL_TLV_INFO_MAX 1024
+-#define WL_BSS_INFO_MAX 2048
+-#define WL_ASSOC_INFO_MAX 512 /* assoc related fil max buf */
+-#define WL_EXTRA_BUF_MAX 2048
+-#define WL_ROAM_TRIGGER_LEVEL -75
+-#define WL_ROAM_DELTA 20
+-#define WL_BEACON_TIMEOUT 3
+-
+-#define WL_SCAN_CHANNEL_TIME 40
+-#define WL_SCAN_UNASSOC_TIME 40
+-#define WL_SCAN_PASSIVE_TIME 120
+-
+-#define WL_ESCAN_BUF_SIZE (1024 * 64)
+-#define WL_ESCAN_TIMER_INTERVAL_MS 8000 /* E-Scan timeout */
+-
+-#define WL_ESCAN_ACTION_START 1
+-#define WL_ESCAN_ACTION_CONTINUE 2
+-#define WL_ESCAN_ACTION_ABORT 3
+-
+-#define WL_AUTH_SHARED_KEY 1 /* d11 shared authentication */
+-#define IE_MAX_LEN 512
+-
+-/* IE TLV processing */
+-#define TLV_LEN_OFF 1 /* length offset */
+-#define TLV_HDR_LEN 2 /* header length */
+-#define TLV_BODY_OFF 2 /* body offset */
+-#define TLV_OUI_LEN 3 /* oui id length */
+-
+-/* 802.11 Mgmt Packet flags */
+-#define BRCMF_VNDR_IE_BEACON_FLAG 0x1
+-#define BRCMF_VNDR_IE_PRBRSP_FLAG 0x2
+-#define BRCMF_VNDR_IE_ASSOCRSP_FLAG 0x4
+-#define BRCMF_VNDR_IE_AUTHRSP_FLAG 0x8
+-#define BRCMF_VNDR_IE_PRBREQ_FLAG 0x10
+-#define BRCMF_VNDR_IE_ASSOCREQ_FLAG 0x20
+-/* vendor IE in IW advertisement protocol ID field */
+-#define BRCMF_VNDR_IE_IWAPID_FLAG 0x40
+-/* allow custom IE id */
+-#define BRCMF_VNDR_IE_CUSTOM_FLAG 0x100
+-
+-/* P2P Action Frames flags (spec ordered) */
+-#define BRCMF_VNDR_IE_GONREQ_FLAG 0x001000
+-#define BRCMF_VNDR_IE_GONRSP_FLAG 0x002000
+-#define BRCMF_VNDR_IE_GONCFM_FLAG 0x004000
+-#define BRCMF_VNDR_IE_INVREQ_FLAG 0x008000
+-#define BRCMF_VNDR_IE_INVRSP_FLAG 0x010000
+-#define BRCMF_VNDR_IE_DISREQ_FLAG 0x020000
+-#define BRCMF_VNDR_IE_DISRSP_FLAG 0x040000
+-#define BRCMF_VNDR_IE_PRDREQ_FLAG 0x080000
+-#define BRCMF_VNDR_IE_PRDRSP_FLAG 0x100000
+-
+-#define BRCMF_VNDR_IE_P2PAF_SHIFT 12
+-
+-
+-/**
+- * enum brcmf_scan_status - scan engine status
+- *
+- * @BRCMF_SCAN_STATUS_BUSY: scanning in progress on dongle.
+- * @BRCMF_SCAN_STATUS_ABORT: scan being aborted on dongle.
+- * @BRCMF_SCAN_STATUS_SUPPRESS: scanning is suppressed in driver.
+- */
+-enum brcmf_scan_status {
+- BRCMF_SCAN_STATUS_BUSY,
+- BRCMF_SCAN_STATUS_ABORT,
+- BRCMF_SCAN_STATUS_SUPPRESS,
+-};
+-
+-/**
+- * enum wl_mode - driver mode of virtual interface.
+- *
+- * @WL_MODE_BSS: connects to BSS.
+- * @WL_MODE_IBSS: operate as ad-hoc.
+- * @WL_MODE_AP: operate as access-point.
+- * @WL_MODE_P2P: provide P2P discovery.
+- */
+-enum wl_mode {
+- WL_MODE_BSS,
+- WL_MODE_IBSS,
+- WL_MODE_AP,
+- WL_MODE_P2P
+-};
+-
+-/* dongle configuration */
+-struct brcmf_cfg80211_conf {
+- u32 frag_threshold;
+- u32 rts_threshold;
+- u32 retry_short;
+- u32 retry_long;
+- s32 tx_power;
+- struct ieee80211_channel channel;
+-};
+-
+-/* basic structure of scan request */
+-struct brcmf_cfg80211_scan_req {
+- struct brcmf_ssid_le ssid_le;
+-};
+-
+-/* basic structure of information element */
+-struct brcmf_cfg80211_ie {
+- u16 offset;
+- u8 buf[WL_TLV_INFO_MAX];
+-};
+-
+-/* security information with currently associated ap */
+-struct brcmf_cfg80211_security {
+- u32 wpa_versions;
+- u32 auth_type;
+- u32 cipher_pairwise;
+- u32 cipher_group;
+- u32 wpa_auth;
+-};
+-
+-/**
+- * struct brcmf_cfg80211_profile - profile information.
+- *
+- * @ssid: ssid of associated/associating ap.
+- * @bssid: bssid of joined/joining ibss.
+- * @sec: security information.
+- */
+-struct brcmf_cfg80211_profile {
+- struct brcmf_ssid ssid;
+- u8 bssid[ETH_ALEN];
+- struct brcmf_cfg80211_security sec;
+-};
+-
+-/**
+- * enum brcmf_vif_status - bit indices for vif status.
+- *
+- * @BRCMF_VIF_STATUS_READY: ready for operation.
+- * @BRCMF_VIF_STATUS_CONNECTING: connect/join in progress.
+- * @BRCMF_VIF_STATUS_CONNECTED: connected/joined succesfully.
+- * @BRCMF_VIF_STATUS_DISCONNECTING: disconnect/disable in progress.
+- * @BRCMF_VIF_STATUS_AP_CREATING: interface configured for AP operation.
+- * @BRCMF_VIF_STATUS_AP_CREATED: AP operation started.
+- */
+-enum brcmf_vif_status {
+- BRCMF_VIF_STATUS_READY,
+- BRCMF_VIF_STATUS_CONNECTING,
+- BRCMF_VIF_STATUS_CONNECTED,
+- BRCMF_VIF_STATUS_DISCONNECTING,
+- BRCMF_VIF_STATUS_AP_CREATING,
+- BRCMF_VIF_STATUS_AP_CREATED
+-};
+-
+-/**
+- * struct vif_saved_ie - holds saved IEs for a virtual interface.
+- *
+- * @probe_req_ie: IE info for probe request.
+- * @probe_res_ie: IE info for probe response.
+- * @beacon_ie: IE info for beacon frame.
+- * @probe_req_ie_len: IE info length for probe request.
+- * @probe_res_ie_len: IE info length for probe response.
+- * @beacon_ie_len: IE info length for beacon frame.
+- */
+-struct vif_saved_ie {
+- u8 probe_req_ie[IE_MAX_LEN];
+- u8 probe_res_ie[IE_MAX_LEN];
+- u8 beacon_ie[IE_MAX_LEN];
+- u8 assoc_req_ie[IE_MAX_LEN];
+- u32 probe_req_ie_len;
+- u32 probe_res_ie_len;
+- u32 beacon_ie_len;
+- u32 assoc_req_ie_len;
+-};
+-
+-/**
+- * struct brcmf_cfg80211_vif - virtual interface specific information.
+- *
+- * @ifp: lower layer interface pointer
+- * @wdev: wireless device.
+- * @profile: profile information.
+- * @mode: operating mode.
+- * @roam_off: roaming state.
+- * @sme_state: SME state using enum brcmf_vif_status bits.
+- * @pm_block: power-management blocked.
+- * @list: linked list.
+- * @mgmt_rx_reg: registered rx mgmt frame types.
+- */
+-struct brcmf_cfg80211_vif {
+- struct brcmf_if *ifp;
+- struct wireless_dev wdev;
+- struct brcmf_cfg80211_profile profile;
+- s32 mode;
+- s32 roam_off;
+- unsigned long sme_state;
+- bool pm_block;
+- struct vif_saved_ie saved_ie;
+- struct list_head list;
+- u16 mgmt_rx_reg;
+-};
+-
+-/* association inform */
+-struct brcmf_cfg80211_connect_info {
+- u8 *req_ie;
+- s32 req_ie_len;
+- u8 *resp_ie;
+- s32 resp_ie_len;
+-};
+-
+-/* assoc ie length */
+-struct brcmf_cfg80211_assoc_ielen_le {
+- __le32 req_len;
+- __le32 resp_len;
+-};
+-
+-/* wpa2 pmk list */
+-struct brcmf_cfg80211_pmk_list {
+- struct pmkid_list pmkids;
+- struct pmkid foo[MAXPMKID - 1];
+-};
+-
+-/* dongle escan state */
+-enum wl_escan_state {
+- WL_ESCAN_STATE_IDLE,
+- WL_ESCAN_STATE_SCANNING
+-};
+-
+-struct escan_info {
+- u32 escan_state;
+- u8 escan_buf[WL_ESCAN_BUF_SIZE];
+- struct wiphy *wiphy;
+- struct brcmf_if *ifp;
+- s32 (*run)(struct brcmf_cfg80211_info *cfg, struct brcmf_if *ifp,
+- struct cfg80211_scan_request *request, u16 action);
+-};
+-
+-/**
+- * struct brcmf_pno_param_le - PNO scan configuration parameters
+- *
+- * @version: PNO parameters version.
+- * @scan_freq: scan frequency.
+- * @lost_network_timeout: #sec. to declare discovered network as lost.
+- * @flags: Bit field to control features of PFN such as sort criteria auto
+- * enable switch and background scan.
+- * @rssi_margin: Margin to avoid jitter for choosing a PFN based on RSSI sort
+- * criteria.
+- * @bestn: number of best networks in each scan.
+- * @mscan: number of scans recorded.
+- * @repeat: minimum number of scan intervals before scan frequency changes
+- * in adaptive scan.
+- * @exp: exponent of 2 for maximum scan interval.
+- * @slow_freq: slow scan period.
+- */
+-struct brcmf_pno_param_le {
+- __le32 version;
+- __le32 scan_freq;
+- __le32 lost_network_timeout;
+- __le16 flags;
+- __le16 rssi_margin;
+- u8 bestn;
+- u8 mscan;
+- u8 repeat;
+- u8 exp;
+- __le32 slow_freq;
+-};
+-
+-/**
+- * struct brcmf_pno_net_param_le - scan parameters per preferred network.
+- *
+- * @ssid: ssid name and its length.
+- * @flags: bit2: hidden.
+- * @infra: BSS vs IBSS.
+- * @auth: Open vs Closed.
+- * @wpa_auth: WPA type.
+- * @wsec: wsec value.
+- */
+-struct brcmf_pno_net_param_le {
+- struct brcmf_ssid_le ssid;
+- __le32 flags;
+- __le32 infra;
+- __le32 auth;
+- __le32 wpa_auth;
+- __le32 wsec;
+-};
+-
+-/**
+- * struct brcmf_pno_net_info_le - information per found network.
+- *
+- * @bssid: BSS network identifier.
+- * @channel: channel number only.
+- * @SSID_len: length of ssid.
+- * @SSID: ssid characters.
+- * @RSSI: receive signal strength (in dBm).
+- * @timestamp: age in seconds.
+- */
+-struct brcmf_pno_net_info_le {
+- u8 bssid[ETH_ALEN];
+- u8 channel;
+- u8 SSID_len;
+- u8 SSID[32];
+- __le16 RSSI;
+- __le16 timestamp;
+-};
+-
+-/**
+- * struct brcmf_pno_scanresults_le - result returned in PNO NET FOUND event.
+- *
+- * @version: PNO version identifier.
+- * @status: indicates completion status of PNO scan.
+- * @count: amount of brcmf_pno_net_info_le entries appended.
+- */
+-struct brcmf_pno_scanresults_le {
+- __le32 version;
+- __le32 status;
+- __le32 count;
+-};
+-
+-/**
+- * struct brcmf_cfg80211_vif_event - virtual interface event information.
+- *
+- * @vif_wq: waitqueue awaiting interface event from firmware.
+- * @vif_event_lock: protects other members in this structure.
+- * @vif_complete: completion for net attach.
+- * @action: either add, change, or delete.
+- * @vif: virtual interface object related to the event.
+- */
+-struct brcmf_cfg80211_vif_event {
+- wait_queue_head_t vif_wq;
+- struct mutex vif_event_lock;
+- u8 action;
+- struct brcmf_cfg80211_vif *vif;
+-};
+-
+-/**
+- * struct brcmf_cfg80211_info - dongle private data of cfg80211 interface
+- *
+- * @wiphy: wiphy object for cfg80211 interface.
+- * @conf: dongle configuration.
+- * @p2p: peer-to-peer specific information.
+- * @btcoex: Bluetooth coexistence information.
+- * @scan_request: cfg80211 scan request object.
+- * @usr_sync: mainly for dongle up/down synchronization.
+- * @bss_list: bss_list holding scanned ap information.
+- * @scan_req_int: internal scan request object.
+- * @bss_info: bss information for cfg80211 layer.
+- * @ie: information element object for internal purpose.
+- * @conn_info: association info.
+- * @pmk_list: wpa2 pmk list.
+- * @scan_status: scan activity on the dongle.
+- * @pub: common driver information.
+- * @channel: current channel.
+- * @active_scan: current scan mode.
+- * @sched_escan: e-scan for scheduled scan support running.
+- * @ibss_starter: indicates this sta is ibss starter.
+- * @pwr_save: indicate whether dongle to support power save mode.
+- * @dongle_up: indicate whether dongle up or not.
+- * @roam_on: on/off switch for dongle self-roaming.
+- * @scan_tried: indicates if first scan attempted.
+- * @dcmd_buf: dcmd buffer.
+- * @extra_buf: mainly to grab assoc information.
+- * @debugfsdir: debugfs folder for this device.
+- * @escan_info: escan information.
+- * @escan_timeout: Timer for catch scan timeout.
+- * @escan_timeout_work: scan timeout worker.
+- * @escan_ioctl_buf: dongle command buffer for escan commands.
+- * @vif_list: linked list of vif instances.
+- * @vif_cnt: number of vif instances.
+- * @vif_event: vif event signalling.
+- */
+-struct brcmf_cfg80211_info {
+- struct wiphy *wiphy;
+- struct brcmf_cfg80211_conf *conf;
+- struct brcmf_p2p_info p2p;
+- struct brcmf_btcoex_info *btcoex;
+- struct cfg80211_scan_request *scan_request;
+- struct mutex usr_sync;
+- struct brcmf_scan_results *bss_list;
+- struct brcmf_cfg80211_scan_req scan_req_int;
+- struct wl_cfg80211_bss_info *bss_info;
+- struct brcmf_cfg80211_ie ie;
+- struct brcmf_cfg80211_connect_info conn_info;
+- struct brcmf_cfg80211_pmk_list *pmk_list;
+- unsigned long scan_status;
+- struct brcmf_pub *pub;
+- u32 channel;
+- bool active_scan;
+- bool sched_escan;
+- bool ibss_starter;
+- bool pwr_save;
+- bool dongle_up;
+- bool roam_on;
+- bool scan_tried;
+- u8 *dcmd_buf;
+- u8 *extra_buf;
+- struct dentry *debugfsdir;
+- struct escan_info escan_info;
+- struct timer_list escan_timeout;
+- struct work_struct escan_timeout_work;
+- u8 *escan_ioctl_buf;
+- struct list_head vif_list;
+- struct brcmf_cfg80211_vif_event vif_event;
+- struct completion vif_disabled;
+- struct brcmu_d11inf d11inf;
+-};
+-
+-/**
+- * struct brcmf_tlv - tag_ID/length/value_buffer tuple.
+- *
+- * @id: tag identifier.
+- * @len: number of bytes in value buffer.
+- * @data: value buffer.
+- */
+-struct brcmf_tlv {
+- u8 id;
+- u8 len;
+- u8 data[1];
+-};
+-
+-static inline struct wiphy *cfg_to_wiphy(struct brcmf_cfg80211_info *cfg)
+-{
+- return cfg->wiphy;
+-}
+-
+-static inline struct brcmf_cfg80211_info *wiphy_to_cfg(struct wiphy *w)
+-{
+- return (struct brcmf_cfg80211_info *)(wiphy_priv(w));
+-}
+-
+-static inline struct brcmf_cfg80211_info *wdev_to_cfg(struct wireless_dev *wd)
+-{
+- return (struct brcmf_cfg80211_info *)(wdev_priv(wd));
+-}
+-
+-static inline
+-struct net_device *cfg_to_ndev(struct brcmf_cfg80211_info *cfg)
+-{
+- struct brcmf_cfg80211_vif *vif;
+- vif = list_first_entry(&cfg->vif_list, struct brcmf_cfg80211_vif, list);
+- return vif->wdev.netdev;
+-}
+-
+-static inline struct brcmf_cfg80211_info *ndev_to_cfg(struct net_device *ndev)
+-{
+- return wdev_to_cfg(ndev->ieee80211_ptr);
+-}
+-
+-static inline struct brcmf_cfg80211_profile *ndev_to_prof(struct net_device *nd)
+-{
+- struct brcmf_if *ifp = netdev_priv(nd);
+- return &ifp->vif->profile;
+-}
+-
+-static inline struct brcmf_cfg80211_vif *ndev_to_vif(struct net_device *ndev)
+-{
+- struct brcmf_if *ifp = netdev_priv(ndev);
+- return ifp->vif;
+-}
+-
+-static inline struct
+-brcmf_cfg80211_connect_info *cfg_to_conn(struct brcmf_cfg80211_info *cfg)
+-{
+- return &cfg->conn_info;
+-}
+-
+-struct brcmf_cfg80211_info *brcmf_cfg80211_attach(struct brcmf_pub *drvr,
+- struct device *busdev);
+-void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg);
+-s32 brcmf_cfg80211_up(struct net_device *ndev);
+-s32 brcmf_cfg80211_down(struct net_device *ndev);
+-enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp);
+-
+-struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
+- enum nl80211_iftype type,
+- bool pm_block);
+-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif);
+-
+-s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
+- const u8 *vndr_ie_buf, u32 vndr_ie_len);
+-s32 brcmf_vif_clear_mgmt_ies(struct brcmf_cfg80211_vif *vif);
+-struct brcmf_tlv *brcmf_parse_tlvs(void *buf, int buflen, uint key);
+-u16 channel_to_chanspec(struct brcmu_d11inf *d11inf,
+- struct ieee80211_channel *ch);
+-u32 wl_get_vif_state_all(struct brcmf_cfg80211_info *cfg, unsigned long state);
+-void brcmf_cfg80211_arm_vif_event(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_cfg80211_vif *vif);
+-bool brcmf_cfg80211_vif_event_armed(struct brcmf_cfg80211_info *cfg);
+-int brcmf_cfg80211_wait_vif_event_timeout(struct brcmf_cfg80211_info *cfg,
+- u8 action, ulong timeout);
+-s32 brcmf_notify_escan_complete(struct brcmf_cfg80211_info *cfg,
+- struct brcmf_if *ifp, bool aborted,
+- bool fw_abort);
+-void brcmf_set_mpc(struct brcmf_if *ndev, int mpc);
+-void brcmf_abort_scanning(struct brcmf_cfg80211_info *cfg);
+-void brcmf_cfg80211_free_netdev(struct net_device *ndev);
+-
+-#endif /* _wl_cfg80211_h_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmsmac/main.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmsmac/main.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmsmac/main.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmsmac/main.c 2016-06-19 22:11:55.297140532 +0200
+@@ -1009,8 +1009,7 @@
+ if (txh)
+ trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
+ sizeof(*txh));
+- if (p)
+- brcmu_pkt_buf_free_skb(p);
++ brcmu_pkt_buf_free_skb(p);
+ }
+
+ if (dma && queue < NFIFO) {
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c 2016-06-19 22:11:55.297140532 +0200
+@@ -1538,11 +1538,7 @@
+ wlc_user_txpwr_antport_to_rfport(struct brcms_phy *pi, uint chan, u32 band,
+ u8 rate)
+ {
+- s8 offset = 0;
+-
+- if (!pi->user_txpwr_at_rfport)
+- return offset;
+- return offset;
++ return 0;
+ }
+
+ void wlc_phy_txpower_recalc_target(struct brcms_phy *pi)
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c 2016-06-19 22:11:55.301140269 +0200
+@@ -22916,7 +22916,6 @@
+ break;
+ default:
+ return;
+- break;
+ }
+
+ classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmutil/utils.c linux-3.14.72/drivers/net/wireless/brcm80211/brcmutil/utils.c
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/brcmutil/utils.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/brcmutil/utils.c 2016-06-19 22:11:55.301140269 +0200
+@@ -261,6 +261,33 @@
+ }
+ EXPORT_SYMBOL(brcmu_pktq_mdeq);
+
++char *brcmu_dotrev_str(u32 dotrev, char *buf)
++{
++ u8 dotval[4];
++
++ if (!dotrev) {
++ snprintf(buf, BRCMU_DOTREV_LEN, "unknown");
++ return buf;
++ }
++ dotval[0] = (dotrev >> 24) & 0xFF;
++ dotval[1] = (dotrev >> 16) & 0xFF;
++ dotval[2] = (dotrev >> 8) & 0xFF;
++ dotval[3] = dotrev & 0xFF;
++
++ if (dotval[3])
++ snprintf(buf, BRCMU_DOTREV_LEN, "%d.%d.%d.%d", dotval[0],
++ dotval[1], dotval[2], dotval[3]);
++ else if (dotval[2])
++ snprintf(buf, BRCMU_DOTREV_LEN, "%d.%d.%d", dotval[0],
++ dotval[1], dotval[2]);
++ else
++ snprintf(buf, BRCMU_DOTREV_LEN, "%d.%d", dotval[0],
++ dotval[1]);
++
++ return buf;
++}
++EXPORT_SYMBOL(brcmu_dotrev_str);
++
+ #if defined(DEBUG)
+ /* pretty hex print a pkt buffer chain */
+ void brcmu_prpkt(const char *msg, struct sk_buff *p0)
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h linux-3.14.72/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/include/brcm_hw_ids.h 2016-06-19 22:11:55.301140269 +0200
+@@ -17,31 +17,61 @@
+ #ifndef _BRCM_HW_IDS_H_
+ #define _BRCM_HW_IDS_H_
+
+-#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
++#include <linux/pci_ids.h>
++#include <linux/mmc/sdio_ids.h>
++
++#define BRCM_USB_VENDOR_ID_BROADCOM 0x0a5c
++#define BRCM_PCIE_VENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
++
++/* Chipcommon Core Chip IDs */
++#define BRCM_CC_43143_CHIP_ID 43143
++#define BRCM_CC_43235_CHIP_ID 43235
++#define BRCM_CC_43236_CHIP_ID 43236
++#define BRCM_CC_43238_CHIP_ID 43238
++#define BRCM_CC_43241_CHIP_ID 0x4324
++#define BRCM_CC_43242_CHIP_ID 43242
++#define BRCM_CC_4329_CHIP_ID 0x4329
++#define BRCM_CC_4330_CHIP_ID 0x4330
++#define BRCM_CC_4334_CHIP_ID 0x4334
++#define BRCM_CC_43340_CHIP_ID 43340
++#define BRCM_CC_43362_CHIP_ID 43362
++#define BRCM_CC_4335_CHIP_ID 0x4335
++#define BRCM_CC_4339_CHIP_ID 0x4339
++#define BRCM_CC_43430_CHIP_ID 43430
++#define BRCM_CC_4345_CHIP_ID 0x4345
++#define BRCM_CC_4354_CHIP_ID 0x4354
++#define BRCM_CC_4356_CHIP_ID 0x4356
++#define BRCM_CC_43566_CHIP_ID 43566
++#define BRCM_CC_43567_CHIP_ID 43567
++#define BRCM_CC_43569_CHIP_ID 43569
++#define BRCM_CC_43570_CHIP_ID 43570
++#define BRCM_CC_43602_CHIP_ID 43602
++
++/* USB Device IDs */
++#define BRCM_USB_43143_DEVICE_ID 0xbd1e
++#define BRCM_USB_43236_DEVICE_ID 0xbd17
++#define BRCM_USB_43242_DEVICE_ID 0xbd1f
++#define BRCM_USB_43569_DEVICE_ID 0xbd27
++#define BRCM_USB_BCMFW_DEVICE_ID 0x0bdc
++
++/* PCIE Device IDs */
++#define BRCM_PCIE_4354_DEVICE_ID 0x43df
++#define BRCM_PCIE_4356_DEVICE_ID 0x43ec
++#define BRCM_PCIE_43567_DEVICE_ID 0x43d3
++#define BRCM_PCIE_43570_DEVICE_ID 0x43d9
++#define BRCM_PCIE_43602_DEVICE_ID 0x43ba
++#define BRCM_PCIE_43602_2G_DEVICE_ID 0x43bb
++#define BRCM_PCIE_43602_5G_DEVICE_ID 0x43bc
+
++/* brcmsmac IDs */
++#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
+ #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
+ #define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db */
+-
+ #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
+-
+ #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
+ #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
+
+-/* Chipcommon Core Chip IDs */
+ #define BCM4313_CHIP_ID 0x4313
+-#define BCM43143_CHIP_ID 43143
+ #define BCM43224_CHIP_ID 43224
+-#define BCM43225_CHIP_ID 43225
+-#define BCM43235_CHIP_ID 43235
+-#define BCM43236_CHIP_ID 43236
+-#define BCM43238_CHIP_ID 43238
+-#define BCM43241_CHIP_ID 0x4324
+-#define BCM4329_CHIP_ID 0x4329
+-#define BCM4330_CHIP_ID 0x4330
+-#define BCM4331_CHIP_ID 0x4331
+-#define BCM4334_CHIP_ID 0x4334
+-#define BCM4335_CHIP_ID 0x4335
+-#define BCM43362_CHIP_ID 43362
+-#define BCM4339_CHIP_ID 0x4339
+
+ #endif /* _BRCM_HW_IDS_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/brcmu_utils.h linux-3.14.72/drivers/net/wireless/brcm80211/include/brcmu_utils.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/brcmu_utils.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/include/brcmu_utils.h 2016-06-19 22:11:55.301140269 +0200
+@@ -218,4 +218,8 @@
+ }
+ #endif
+
++#define BRCMU_DOTREV_LEN 16
++
++char *brcmu_dotrev_str(u32 dotrev, char *buf);
++
+ #endif /* _BRCMU_UTILS_H_ */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/brcmu_wifi.h linux-3.14.72/drivers/net/wireless/brcm80211/include/brcmu_wifi.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/brcmu_wifi.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/include/brcmu_wifi.h 2016-06-19 22:11:55.301140269 +0200
+@@ -217,6 +217,9 @@
+ #define WSEC_SWFLAG 0x0008
+ /* to go into transition mode without setting wep */
+ #define SES_OW_ENABLED 0x0040
++/* MFP */
++#define MFP_CAPABLE 0x0200
++#define MFP_REQUIRED 0x0400
+
+ /* WPA authentication mode bitvec */
+ #define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/chipcommon.h linux-3.14.72/drivers/net/wireless/brcm80211/include/chipcommon.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/chipcommon.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/include/chipcommon.h 2016-06-19 22:11:55.301140269 +0200
+@@ -183,7 +183,14 @@
+ u8 uart1lsr;
+ u8 uart1msr;
+ u8 uart1scratch;
+- u32 PAD[126];
++ u32 PAD[62];
++
++ /* save/restore, corerev >= 48 */
++ u32 sr_capability; /* 0x500 */
++ u32 sr_control0; /* 0x504 */
++ u32 sr_control1; /* 0x508 */
++ u32 gpio_control; /* 0x50C */
++ u32 PAD[60];
+
+ /* PMU registers (corerev >= 20) */
+ u32 pmucontrol; /* 0x600 */
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/defs.h linux-3.14.72/drivers/net/wireless/brcm80211/include/defs.h
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/include/defs.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/include/defs.h 2016-06-19 22:11:55.301140269 +0200
+@@ -74,10 +74,6 @@
+ #define BRCM_BAND_2G 2 /* 2.4 Ghz */
+ #define BRCM_BAND_ALL 3 /* all bands */
+
+-/* Values for PM */
+-#define PM_OFF 0
+-#define PM_MAX 1
+-
+ /* Debug levels */
+ #define BRCM_DL_INFO 0x00000001
+ #define BRCM_DL_MAC80211 0x00000002
+@@ -87,6 +83,7 @@
+ #define BRCM_DL_DMA 0x00000020
+ #define BRCM_DL_HT 0x00000040
+
++/* Values for PM */
+ #define PM_OFF 0
+ #define PM_MAX 1
+ #define PM_FAST 2
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/brcm80211/Kconfig linux-3.14.72/drivers/net/wireless/brcm80211/Kconfig
+--- linux-3.14.72.orig/drivers/net/wireless/brcm80211/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/brcm80211/Kconfig 2016-06-19 22:11:55.301140269 +0200
+@@ -27,10 +27,17 @@
+ one of the bus interface support. If you choose to build a module,
+ it'll be called brcmfmac.ko.
+
++config BRCMFMAC_PROTO_BCDC
++ bool
++
++config BRCMFMAC_PROTO_MSGBUF
++ bool
++
+ config BRCMFMAC_SDIO
+ bool "SDIO bus interface support for FullMAC driver"
+ depends on (MMC = y || MMC = BRCMFMAC)
+ depends on BRCMFMAC
++ select BRCMFMAC_PROTO_BCDC
+ select FW_LOADER
+ default y
+ ---help---
+@@ -42,12 +49,25 @@
+ bool "USB bus interface support for FullMAC driver"
+ depends on (USB = y || USB = BRCMFMAC)
+ depends on BRCMFMAC
++ select BRCMFMAC_PROTO_BCDC
+ select FW_LOADER
+ ---help---
+ This option enables the USB bus interface support for Broadcom
+ IEEE802.11n embedded FullMAC WLAN driver. Say Y if you want to
+ use the driver for an USB wireless card.
+
++config BRCMFMAC_PCIE
++ bool "PCIE bus interface support for FullMAC driver"
++ depends on BRCMFMAC
++ depends on PCI
++ depends on HAS_DMA
++ select BRCMFMAC_PROTO_MSGBUF
++ select FW_LOADER
++ ---help---
++ This option enables the PCIE bus interface support for Broadcom
++ IEEE802.11ac embedded FullMAC WLAN driver. Say Y if you want to
++ use the driver for an PCIE wireless card.
++
+ config BRCM_TRACING
+ bool "Broadcom device tracing"
+ depends on BRCMSMAC || BRCMFMAC
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/libertas/cfg.c linux-3.14.72/drivers/net/wireless/libertas/cfg.c
+--- linux-3.14.72.orig/drivers/net/wireless/libertas/cfg.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/libertas/cfg.c 2016-06-19 22:11:55.301140269 +0200
+@@ -1766,7 +1766,8 @@
+ memcpy(priv->wdev->ssid, params->ssid, params->ssid_len);
+ priv->wdev->ssid_len = params->ssid_len;
+
+- cfg80211_ibss_joined(priv->dev, bssid, GFP_KERNEL);
++ cfg80211_ibss_joined(priv->dev, bssid, params->chandef.chan,
++ GFP_KERNEL);
+
+ /* TODO: consider doing this at MACREG_INT_CODE_LINK_SENSED time */
+ priv->connect_status = LBS_CONNECTED;
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/mwifiex/cfg80211.c linux-3.14.72/drivers/net/wireless/mwifiex/cfg80211.c
+--- linux-3.14.72.orig/drivers/net/wireless/mwifiex/cfg80211.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/mwifiex/cfg80211.c 2016-06-19 22:11:55.301140269 +0200
+@@ -1881,7 +1881,8 @@
+ params->privacy);
+ done:
+ if (!ret) {
+- cfg80211_ibss_joined(priv->netdev, priv->cfg_bssid, GFP_KERNEL);
++ cfg80211_ibss_joined(priv->netdev, priv->cfg_bssid,
++ params->chandef.chan, GFP_KERNEL);
+ dev_dbg(priv->adapter->dev,
+ "info: joined/created adhoc network with bssid"
+ " %pM successfully\n", priv->cfg_bssid);
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/mwifiex/main.h linux-3.14.72/drivers/net/wireless/mwifiex/main.h
+--- linux-3.14.72.orig/drivers/net/wireless/mwifiex/main.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/mwifiex/main.h 2016-06-19 22:11:55.301140269 +0200
+@@ -1078,7 +1078,7 @@
+ const u8 *key, int key_len, u8 key_index,
+ const u8 *mac_addr, int disable);
+
+-int mwifiex_set_gen_ie(struct mwifiex_private *priv, u8 *ie, int ie_len);
++int mwifiex_set_gen_ie(struct mwifiex_private *priv, const u8 *ie, int ie_len);
+
+ int mwifiex_get_ver_ext(struct mwifiex_private *priv);
+
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/mwifiex/sta_ioctl.c linux-3.14.72/drivers/net/wireless/mwifiex/sta_ioctl.c
+--- linux-3.14.72.orig/drivers/net/wireless/mwifiex/sta_ioctl.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/mwifiex/sta_ioctl.c 2016-06-19 22:11:55.301140269 +0200
+@@ -1391,7 +1391,7 @@
+ * with requisite parameters and calls the IOCTL handler.
+ */
+ int
+-mwifiex_set_gen_ie(struct mwifiex_private *priv, u8 *ie, int ie_len)
++mwifiex_set_gen_ie(struct mwifiex_private *priv, const u8 *ie, int ie_len)
+ {
+ struct mwifiex_ds_misc_gen_ie gen_ie;
+
+diff -Nur linux-3.14.72.orig/drivers/net/wireless/rndis_wlan.c linux-3.14.72/drivers/net/wireless/rndis_wlan.c
+--- linux-3.14.72.orig/drivers/net/wireless/rndis_wlan.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/net/wireless/rndis_wlan.c 2016-06-19 22:11:55.301140269 +0200
+@@ -2835,7 +2835,9 @@
+ bssid, req_ie, req_ie_len,
+ resp_ie, resp_ie_len, GFP_KERNEL);
+ } else if (priv->infra_mode == NDIS_80211_INFRA_ADHOC)
+- cfg80211_ibss_joined(usbdev->net, bssid, GFP_KERNEL);
++ cfg80211_ibss_joined(usbdev->net, bssid,
++ get_current_channel(usbdev, NULL),
++ GFP_KERNEL);
+
+ kfree(info);
+
+diff -Nur linux-3.14.72.orig/drivers/of/base.c linux-3.14.72/drivers/of/base.c
+--- linux-3.14.72.orig/drivers/of/base.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/of/base.c 2016-06-19 22:11:55.305140007 +0200
+@@ -1756,6 +1756,35 @@
+ ap->alias, ap->stem, ap->id, of_node_full_name(np));
+ }
+
++/*
++ * of_alias_max_index() - get the maximum index for a given alias stem
++ * @stem: The alias stem for which the maximum index is searched for
++ *
++ * Given an alias stem (the alias without the number) this function
++ * returns the maximum number for which an alias exists.
++ *
++ * Return: The maximum existing alias index or -ENODEV if no alias
++ * exists for this stem.
++ */
++int of_alias_max_index(const char *stem)
++{
++ struct alias_prop *app;
++ int max = -ENODEV;
++
++ mutex_lock(&of_aliases_mutex);
++
++ list_for_each_entry(app, &aliases_lookup, link) {
++ if (strcmp(app->stem, stem))
++ continue;
++ if (app->id > max)
++ max = app->id;
++ }
++
++ mutex_unlock(&of_aliases_mutex);
++
++ return max;
++}
++
+ /**
+ * of_alias_scan - Scan all properties of 'aliases' node
+ *
+diff -Nur linux-3.14.72.orig/drivers/of/of_mdio.c linux-3.14.72/drivers/of/of_mdio.c
+--- linux-3.14.72.orig/drivers/of/of_mdio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/of/of_mdio.c 2016-06-19 22:11:55.305140007 +0200
+@@ -14,6 +14,7 @@
+ #include <linux/netdevice.h>
+ #include <linux/err.h>
+ #include <linux/phy.h>
++#include <linux/phy_fixed.h>
+ #include <linux/of.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_mdio.h>
+@@ -22,25 +23,21 @@
+ MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
+ MODULE_LICENSE("GPL");
+
+-static void of_set_phy_supported(struct phy_device *phydev, u32 max_speed)
++/* Extract the clause 22 phy ID from the compatible string of the form
++ * ethernet-phy-idAAAA.BBBB */
++static int of_get_phy_id(struct device_node *device, u32 *phy_id)
+ {
+- /* The default values for phydev->supported are provided by the PHY
+- * driver "features" member, we want to reset to sane defaults fist
+- * before supporting higher speeds.
+- */
+- phydev->supported &= PHY_DEFAULT_FEATURES;
+-
+- switch (max_speed) {
+- default:
+- return;
+-
+- case SPEED_1000:
+- phydev->supported |= PHY_1000BT_FEATURES;
+- case SPEED_100:
+- phydev->supported |= PHY_100BT_FEATURES;
+- case SPEED_10:
+- phydev->supported |= PHY_10BT_FEATURES;
++ struct property *prop;
++ const char *cp;
++ unsigned int upper, lower;
++
++ of_property_for_each_string(device, "compatible", prop, cp) {
++ if (sscanf(cp, "ethernet-phy-id%4x.%4x", &upper, &lower) == 2) {
++ *phy_id = ((upper & 0xFFFF) << 16) | (lower & 0xFFFF);
++ return 0;
++ }
+ }
++ return -EINVAL;
+ }
+
+ static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *child,
+@@ -49,12 +46,15 @@
+ struct phy_device *phy;
+ bool is_c45;
+ int rc;
+- u32 max_speed = 0;
++ u32 phy_id;
+
+ is_c45 = of_device_is_compatible(child,
+ "ethernet-phy-ieee802.3-c45");
+
+- phy = get_phy_device(mdio, addr, is_c45);
++ if (!is_c45 && !of_get_phy_id(child, &phy_id))
++ phy = phy_device_create(mdio, addr, phy_id, 0, NULL);
++ else
++ phy = get_phy_device(mdio, addr, is_c45);
+ if (!phy || IS_ERR(phy))
+ return 1;
+
+@@ -82,17 +82,33 @@
+ return 1;
+ }
+
+- /* Set phydev->supported based on the "max-speed" property
+- * if present */
+- if (!of_property_read_u32(child, "max-speed", &max_speed))
+- of_set_phy_supported(phy, max_speed);
+-
+ dev_dbg(&mdio->dev, "registered phy %s at address %i\n",
+ child->name, addr);
+
+ return 0;
+ }
+
++static int of_mdio_parse_addr(struct device *dev, const struct device_node *np)
++{
++ u32 addr;
++ int ret;
++
++ ret = of_property_read_u32(np, "reg", &addr);
++ if (ret < 0) {
++ dev_err(dev, "%s has invalid PHY address\n", np->full_name);
++ return ret;
++ }
++
++ /* A PHY must have a reg property in the range [0-31] */
++ if (addr >= PHY_MAX_ADDR) {
++ dev_err(dev, "%s PHY address %i is too large\n",
++ np->full_name, addr);
++ return -EINVAL;
++ }
++
++ return addr;
++}
++
+ /**
+ * of_mdiobus_register - Register mii_bus and create PHYs from the device tree
+ * @mdio: pointer to mii_bus structure
+@@ -105,9 +121,8 @@
+ {
+ struct device_node *child;
+ const __be32 *paddr;
+- u32 addr;
+ bool scanphys = false;
+- int rc, i, len;
++ int addr, rc, i;
+
+ /* Mask out all PHYs from auto probing. Instead the PHYs listed in
+ * the device tree are populated after the bus has been registered */
+@@ -127,19 +142,9 @@
+
+ /* Loop over the child nodes and register a phy_device for each one */
+ for_each_available_child_of_node(np, child) {
+- /* A PHY must have a reg property in the range [0-31] */
+- paddr = of_get_property(child, "reg", &len);
+- if (!paddr || len < sizeof(*paddr)) {
++ addr = of_mdio_parse_addr(&mdio->dev, child);
++ if (addr < 0) {
+ scanphys = true;
+- dev_err(&mdio->dev, "%s has invalid PHY address\n",
+- child->full_name);
+- continue;
+- }
+-
+- addr = be32_to_cpup(paddr);
+- if (addr >= PHY_MAX_ADDR) {
+- dev_err(&mdio->dev, "%s PHY address %i is too large\n",
+- child->full_name, addr);
+ continue;
+ }
+
+@@ -154,7 +159,7 @@
+ /* auto scan for PHYs with empty reg property */
+ for_each_available_child_of_node(np, child) {
+ /* Skip PHYs with reg property set */
+- paddr = of_get_property(child, "reg", &len);
++ paddr = of_get_property(child, "reg", NULL);
+ if (paddr)
+ continue;
+
+@@ -224,44 +229,6 @@
+ EXPORT_SYMBOL(of_phy_connect);
+
+ /**
+- * of_phy_connect_fixed_link - Parse fixed-link property and return a dummy phy
+- * @dev: pointer to net_device claiming the phy
+- * @hndlr: Link state callback for the network device
+- * @iface: PHY data interface type
+- *
+- * This function is a temporary stop-gap and will be removed soon. It is
+- * only to support the fs_enet, ucc_geth and gianfar Ethernet drivers. Do
+- * not call this function from new drivers.
+- */
+-struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
+- void (*hndlr)(struct net_device *),
+- phy_interface_t iface)
+-{
+- struct device_node *net_np;
+- char bus_id[MII_BUS_ID_SIZE + 3];
+- struct phy_device *phy;
+- const __be32 *phy_id;
+- int sz;
+-
+- if (!dev->dev.parent)
+- return NULL;
+-
+- net_np = dev->dev.parent->of_node;
+- if (!net_np)
+- return NULL;
+-
+- phy_id = of_get_property(net_np, "fixed-link", &sz);
+- if (!phy_id || sz < sizeof(*phy_id))
+- return NULL;
+-
+- sprintf(bus_id, PHY_ID_FMT, "fixed-0", be32_to_cpu(phy_id[0]));
+-
+- phy = phy_connect(dev, bus_id, hndlr, iface);
+- return IS_ERR(phy) ? NULL : phy;
+-}
+-EXPORT_SYMBOL(of_phy_connect_fixed_link);
+-
+-/**
+ * of_phy_attach - Attach to a PHY without starting the state machine
+ * @dev: pointer to net_device claiming the phy
+ * @phy_np: Node pointer for the PHY
+@@ -280,3 +247,71 @@
+ return phy_attach_direct(dev, phy, flags, iface) ? NULL : phy;
+ }
+ EXPORT_SYMBOL(of_phy_attach);
++
++#if defined(CONFIG_FIXED_PHY)
++/*
++ * of_phy_is_fixed_link() and of_phy_register_fixed_link() must
++ * support two DT bindings:
++ * - the old DT binding, where 'fixed-link' was a property with 5
++ * cells encoding various informations about the fixed PHY
++ * - the new DT binding, where 'fixed-link' is a sub-node of the
++ * Ethernet device.
++ */
++bool of_phy_is_fixed_link(struct device_node *np)
++{
++ struct device_node *dn;
++ int len;
++
++ /* New binding */
++ dn = of_get_child_by_name(np, "fixed-link");
++ if (dn) {
++ of_node_put(dn);
++ return true;
++ }
++
++ /* Old binding */
++ if (of_get_property(np, "fixed-link", &len) &&
++ len == (5 * sizeof(__be32)))
++ return true;
++
++ return false;
++}
++EXPORT_SYMBOL(of_phy_is_fixed_link);
++
++int of_phy_register_fixed_link(struct device_node *np)
++{
++ struct fixed_phy_status status = {};
++ struct device_node *fixed_link_node;
++ const __be32 *fixed_link_prop;
++ int len;
++
++ /* New binding */
++ fixed_link_node = of_get_child_by_name(np, "fixed-link");
++ if (fixed_link_node) {
++ status.link = 1;
++ status.duplex = of_property_read_bool(fixed_link_node,
++ "full-duplex");
++ if (of_property_read_u32(fixed_link_node, "speed", &status.speed))
++ return -EINVAL;
++ status.pause = of_property_read_bool(fixed_link_node, "pause");
++ status.asym_pause = of_property_read_bool(fixed_link_node,
++ "asym-pause");
++ of_node_put(fixed_link_node);
++ return fixed_phy_register(PHY_POLL, &status, np);
++ }
++
++ /* Old binding */
++ fixed_link_prop = of_get_property(np, "fixed-link", &len);
++ if (fixed_link_prop && len == (5 * sizeof(__be32))) {
++ status.link = 1;
++ status.duplex = be32_to_cpu(fixed_link_prop[1]);
++ status.speed = be32_to_cpu(fixed_link_prop[2]);
++ status.pause = be32_to_cpu(fixed_link_prop[3]);
++ status.asym_pause = be32_to_cpu(fixed_link_prop[4]);
++ return fixed_phy_register(PHY_POLL, &status, np);
++ }
++
++ return -ENODEV;
++}
++EXPORT_SYMBOL(of_phy_register_fixed_link);
++#endif
+diff -Nur linux-3.14.72.orig/drivers/pci/host/Kconfig linux-3.14.72/drivers/pci/host/Kconfig
+--- linux-3.14.72.orig/drivers/pci/host/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pci/host/Kconfig 2016-06-19 22:11:55.305140007 +0200
+@@ -1,9 +1,18 @@
+ menu "PCI host controller drivers"
+ depends on PCI
+
++config PCI_DRA7XX
++ bool "TI DRA7xx PCIe controller"
++ select PCIE_DW
++ depends on OF && HAS_IOMEM && TI_PIPE3
++ help
++ Enables support for the PCIe controller in the DRA7xx SoC. There
++ are two instances of PCIe controller in DRA7xx. This controller can
++ act both as EP and RC. This reuses the Designware core.
++
+ config PCI_MVEBU
+ bool "Marvell EBU PCIe controller"
+- depends on ARCH_MVEBU || ARCH_DOVE || ARCH_KIRKWOOD
++ depends on ARCH_MVEBU || ARCH_DOVE
+ depends on OF
+
+ config PCIE_DW
+@@ -21,16 +30,60 @@
+ select PCIEPORTBUS
+ select PCIE_DW
+
++config PCI_IMX6SX_EXTREMELY_PWR_SAVE
++ bool "Freescale i.MX6SX PCIe controller extremely power save mode"
++ depends on PCI_IMX6 && SOC_IMX6SX
++ help
++ If you want extremely power save on iMX6SX PCIe, you can enable
++ the ultra low power mode during suspend/resume here. Note: iMX6SX
++ PCIe maybe powered off compeltely during suspend, and would be
++ re-initialized again during resume. Some behaviors of the PCIe EP
++ device would be impacted.
++
++config EP_MODE_IN_EP_RC_SYS
++ bool "PCI Express EP mode in the IMX6 RC/EP interconnection system"
++ depends on PCI_IMX6
++
++config RC_MODE_IN_EP_RC_SYS
++ bool "PCI Express RC mode in the IMX6 RC/EP interconnection system"
++ depends on PCI_IMX6 && EP_MODE_IN_EP_RC_SYS!=y
++
++config PCI_IMX_EP_DRV
++ bool "i.MX6 PCI Express EP skeleton driver"
++ depends on RC_MODE_IN_EP_RC_SYS
++ default y
++
+ config PCI_TEGRA
+ bool "NVIDIA Tegra PCIe controller"
+ depends on ARCH_TEGRA
+
+ config PCI_RCAR_GEN2
+ bool "Renesas R-Car Gen2 Internal PCI controller"
+- depends on ARM && (ARCH_R8A7790 || ARCH_R8A7791 || COMPILE_TEST)
++ depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
+ help
+ Say Y here if you want internal PCI support on R-Car Gen2 SoC.
+ There are 3 internal PCI controllers available with a single
+ built-in EHCI/OHCI host controller present on each one.
+
++config PCI_RCAR_GEN2_PCIE
++ bool "Renesas R-Car PCIe controller"
++ depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
++ help
++ Say Y here if you want PCIe controller support on R-Car Gen2 SoCs.
++
++config PCI_HOST_GENERIC
++ bool "Generic PCI host controller"
++ depends on ARM && OF
++ help
++ Say Y here if you want to support a simple generic PCI host
++ controller, such as the one emulated by kvmtool.
++
++config PCIE_SPEAR13XX
++ tristate "STMicroelectronics SPEAr PCIe controller"
++ depends on ARCH_SPEAR13XX
++ select PCIEPORTBUS
++ select PCIE_DW
++ help
++ Say Y here if you want PCIe support on SPEAr13XX SoCs.
++
+ endmenu
+diff -Nur linux-3.14.72.orig/drivers/pci/host/Makefile linux-3.14.72/drivers/pci/host/Makefile
+--- linux-3.14.72.orig/drivers/pci/host/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pci/host/Makefile 2016-06-19 22:11:55.305140007 +0200
+@@ -1,6 +1,11 @@
+ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
++obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
+ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
++obj-$(CONFIG_PCI_IMX_EP_DRV) += pci-imx6-ep-driver.o
+ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
+ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
+ obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
++obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
++obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
++obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pci-dra7xx.c linux-3.14.72/drivers/pci/host/pci-dra7xx.c
+--- linux-3.14.72.orig/drivers/pci/host/pci-dra7xx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/pci/host/pci-dra7xx.c 2016-06-19 22:11:55.305140007 +0200
+@@ -0,0 +1,460 @@
++/*
++ * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
++ *
++ * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
++ *
++ * Authors: Kishon Vijay Abraham I <kishon@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/irqdomain.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/pci.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/resource.h>
++#include <linux/types.h>
++
++#include "pcie-designware.h"
++
++/* PCIe controller wrapper DRA7XX configuration registers */
++
++#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
++#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
++#define ERR_SYS BIT(0)
++#define ERR_FATAL BIT(1)
++#define ERR_NONFATAL BIT(2)
++#define ERR_COR BIT(3)
++#define ERR_AXI BIT(4)
++#define ERR_ECRC BIT(5)
++#define PME_TURN_OFF BIT(8)
++#define PME_TO_ACK BIT(9)
++#define PM_PME BIT(10)
++#define LINK_REQ_RST BIT(11)
++#define LINK_UP_EVT BIT(12)
++#define CFG_BME_EVT BIT(13)
++#define CFG_MSE_EVT BIT(14)
++#define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
++ ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
++ LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
++
++#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
++#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
++#define INTA BIT(0)
++#define INTB BIT(1)
++#define INTC BIT(2)
++#define INTD BIT(3)
++#define MSI BIT(4)
++#define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
++
++#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
++#define LTSSM_EN 0x1
++
++#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
++#define LINK_UP BIT(16)
++
++struct dra7xx_pcie {
++ void __iomem *base;
++ struct phy **phy;
++ int phy_count;
++ struct device *dev;
++ struct pcie_port pp;
++};
++
++#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
++
++static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
++{
++ return readl(pcie->base + offset);
++}
++
++static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
++ u32 value)
++{
++ writel(value, pcie->base + offset);
++}
++
++static int dra7xx_pcie_link_up(struct pcie_port *pp)
++{
++ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
++ u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
++
++ return !!(reg & LINK_UP);
++}
++
++static int dra7xx_pcie_establish_link(struct pcie_port *pp)
++{
++ u32 reg;
++ unsigned int retries = 1000;
++ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
++
++ if (dw_pcie_link_up(pp)) {
++ dev_err(pp->dev, "link is already up\n");
++ return 0;
++ }
++
++ reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
++ reg |= LTSSM_EN;
++ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
++
++ while (retries--) {
++ reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
++ if (reg & LINK_UP)
++ break;
++ usleep_range(10, 20);
++ }
++
++ if (retries == 0) {
++ dev_err(pp->dev, "link is not up\n");
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
++{
++ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
++
++ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
++ ~INTERRUPTS);
++ dra7xx_pcie_writel(dra7xx,
++ PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
++ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
++ ~LEG_EP_INTERRUPTS & ~MSI);
++
++ if (IS_ENABLED(CONFIG_PCI_MSI))
++ dra7xx_pcie_writel(dra7xx,
++ PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
++ else
++ dra7xx_pcie_writel(dra7xx,
++ PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
++ LEG_EP_INTERRUPTS);
++}
++
++static int dra7xx_pcie_host_init(struct pcie_port *pp)
++{
++ dw_pcie_setup_rc(pp);
++ dra7xx_pcie_establish_link(pp);
++ if (IS_ENABLED(CONFIG_PCI_MSI))
++ dw_pcie_msi_init(pp);
++ dra7xx_pcie_enable_interrupts(pp);
++
++ return 0;
++}
++
++static struct pcie_host_ops dra7xx_pcie_host_ops = {
++ .link_up = dra7xx_pcie_link_up,
++ .host_init = dra7xx_pcie_host_init,
++};
++
++static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
++ irq_hw_number_t hwirq)
++{
++ irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
++ irq_set_chip_data(irq, domain->host_data);
++ set_irq_flags(irq, IRQF_VALID);
++
++ return 0;
++}
++
++static const struct irq_domain_ops intx_domain_ops = {
++ .map = dra7xx_pcie_intx_map,
++};
++
++static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
++{
++ struct device *dev = pp->dev;
++ struct device_node *node = dev->of_node;
++ struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
++
++ if (!pcie_intc_node) {
++ dev_err(dev, "No PCIe Intc node found\n");
++ return PTR_ERR(pcie_intc_node);
++ }
++
++ pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
++ &intx_domain_ops, pp);
++ if (!pp->irq_domain) {
++ dev_err(dev, "Failed to get a INTx IRQ domain\n");
++ return PTR_ERR(pp->irq_domain);
++ }
++
++ return 0;
++}
++
++static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
++{
++ struct pcie_port *pp = arg;
++ struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
++ u32 reg;
++
++ reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
++
++ switch (reg) {
++ case MSI:
++ dw_handle_msi_irq(pp);
++ break;
++ case INTA:
++ case INTB:
++ case INTC:
++ case INTD:
++ generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
++ break;
++ }
++
++ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
++
++ return IRQ_HANDLED;
++}
++
++
++static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
++{
++ struct dra7xx_pcie *dra7xx = arg;
++ u32 reg;
++
++ reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
++
++ if (reg & ERR_SYS)
++ dev_dbg(dra7xx->dev, "System Error\n");
++
++ if (reg & ERR_FATAL)
++ dev_dbg(dra7xx->dev, "Fatal Error\n");
++
++ if (reg & ERR_NONFATAL)
++ dev_dbg(dra7xx->dev, "Non Fatal Error\n");
++
++ if (reg & ERR_COR)
++ dev_dbg(dra7xx->dev, "Correctable Error\n");
++
++ if (reg & ERR_AXI)
++ dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n");
++
++ if (reg & ERR_ECRC)
++ dev_dbg(dra7xx->dev, "ECRC Error\n");
++
++ if (reg & PME_TURN_OFF)
++ dev_dbg(dra7xx->dev,
++ "Power Management Event Turn-Off message received\n");
++
++ if (reg & PME_TO_ACK)
++ dev_dbg(dra7xx->dev,
++ "Power Management Turn-Off Ack message received\n");
++
++ if (reg & PM_PME)
++ dev_dbg(dra7xx->dev,
++ "PM Power Management Event message received\n");
++
++ if (reg & LINK_REQ_RST)
++ dev_dbg(dra7xx->dev, "Link Request Reset\n");
++
++ if (reg & LINK_UP_EVT)
++ dev_dbg(dra7xx->dev, "Link-up state change\n");
++
++ if (reg & CFG_BME_EVT)
++ dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n");
++
++ if (reg & CFG_MSE_EVT)
++ dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n");
++
++ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
++
++ return IRQ_HANDLED;
++}
++
++static int add_pcie_port(struct dra7xx_pcie *dra7xx,
++ struct platform_device *pdev)
++{
++ int ret;
++ struct pcie_port *pp;
++ struct resource *res;
++ struct device *dev = &pdev->dev;
++
++ pp = &dra7xx->pp;
++ pp->dev = dev;
++ pp->ops = &dra7xx_pcie_host_ops;
++
++ pp->irq = platform_get_irq(pdev, 1);
++ if (pp->irq < 0) {
++ dev_err(dev, "missing IRQ resource\n");
++ return -EINVAL;
++ }
++
++ ret = devm_request_irq(&pdev->dev, pp->irq,
++ dra7xx_pcie_msi_irq_handler, IRQF_SHARED,
++ "dra7-pcie-msi", pp);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request irq\n");
++ return ret;
++ }
++
++ if (!IS_ENABLED(CONFIG_PCI_MSI)) {
++ ret = dra7xx_pcie_init_irq_domain(pp);
++ if (ret < 0)
++ return ret;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
++ pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
++ if (!pp->dbi_base)
++ return -ENOMEM;
++
++ ret = dw_pcie_host_init(pp);
++ if (ret) {
++ dev_err(dra7xx->dev, "failed to initialize host\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static int __init dra7xx_pcie_probe(struct platform_device *pdev)
++{
++ u32 reg;
++ int ret;
++ int irq;
++ int i;
++ int phy_count;
++ struct phy **phy;
++ void __iomem *base;
++ struct resource *res;
++ struct dra7xx_pcie *dra7xx;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ char name[10];
++
++ dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
++ if (!dra7xx)
++ return -ENOMEM;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(dev, "missing IRQ resource\n");
++ return -EINVAL;
++ }
++
++ ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
++ IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
++ if (ret) {
++ dev_err(dev, "failed to request irq\n");
++ return ret;
++ }
++
++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
++ base = devm_ioremap_nocache(dev, res->start, resource_size(res));
++ if (!base)
++ return -ENOMEM;
++
++ phy_count = of_property_count_strings(np, "phy-names");
++ if (phy_count < 0) {
++ dev_err(dev, "unable to find the strings\n");
++ return phy_count;
++ }
++
++ phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
++ if (!phy)
++ return -ENOMEM;
++
++ for (i = 0; i < phy_count; i++) {
++ snprintf(name, sizeof(name), "pcie-phy%d", i);
++ phy[i] = devm_phy_get(dev, name);
++ if (IS_ERR(phy[i]))
++ return PTR_ERR(phy[i]);
++
++ ret = phy_init(phy[i]);
++ if (ret < 0)
++ goto err_phy;
++
++ ret = phy_power_on(phy[i]);
++ if (ret < 0) {
++ phy_exit(phy[i]);
++ goto err_phy;
++ }
++ }
++
++ dra7xx->base = base;
++ dra7xx->phy = phy;
++ dra7xx->dev = dev;
++ dra7xx->phy_count = phy_count;
++
++ pm_runtime_enable(dev);
++ ret = pm_runtime_get_sync(dev);
++ if (IS_ERR_VALUE(ret)) {
++ dev_err(dev, "pm_runtime_get_sync failed\n");
++ goto err_phy;
++ }
++
++ reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
++ reg &= ~LTSSM_EN;
++ dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
++
++ platform_set_drvdata(pdev, dra7xx);
++
++ ret = add_pcie_port(dra7xx, pdev);
++ if (ret < 0)
++ goto err_add_port;
++
++ return 0;
++
++err_add_port:
++ pm_runtime_put(dev);
++ pm_runtime_disable(dev);
++
++err_phy:
++ while (--i >= 0) {
++ phy_power_off(phy[i]);
++ phy_exit(phy[i]);
++ }
++
++ return ret;
++}
++
++static int __exit dra7xx_pcie_remove(struct platform_device *pdev)
++{
++ struct dra7xx_pcie *dra7xx = platform_get_drvdata(pdev);
++ struct pcie_port *pp = &dra7xx->pp;
++ struct device *dev = &pdev->dev;
++ int count = dra7xx->phy_count;
++
++ if (pp->irq_domain)
++ irq_domain_remove(pp->irq_domain);
++ pm_runtime_put(dev);
++ pm_runtime_disable(dev);
++ while (count--) {
++ phy_power_off(dra7xx->phy[count]);
++ phy_exit(dra7xx->phy[count]);
++ }
++
++ return 0;
++}
++
++static const struct of_device_id of_dra7xx_pcie_match[] = {
++ { .compatible = "ti,dra7-pcie", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, of_dra7xx_pcie_match);
++
++static struct platform_driver dra7xx_pcie_driver = {
++ .remove = __exit_p(dra7xx_pcie_remove),
++ .driver = {
++ .name = "dra7-pcie",
++ .owner = THIS_MODULE,
++ .of_match_table = of_dra7xx_pcie_match,
++ },
++};
++
++module_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
++
++MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
++MODULE_DESCRIPTION("TI PCIe controller driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pcie-designware.c linux-3.14.72/drivers/pci/host/pcie-designware.c
+--- linux-3.14.72.orig/drivers/pci/host/pcie-designware.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pci/host/pcie-designware.c 2016-06-19 22:11:55.305140007 +0200
+@@ -17,8 +17,10 @@
+ #include <linux/module.h>
+ #include <linux/msi.h>
+ #include <linux/of_address.h>
++#include <linux/of_pci.h>
+ #include <linux/pci.h>
+ #include <linux/pci_regs.h>
++#include <linux/platform_device.h>
+ #include <linux/types.h>
+
+ #include "pcie-designware.h"
+@@ -155,15 +157,17 @@
+ };
+
+ /* MSI int handler */
+-void dw_handle_msi_irq(struct pcie_port *pp)
++irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
+ {
+ unsigned long val;
+ int i, pos, irq;
++ irqreturn_t ret = IRQ_NONE;
+
+ for (i = 0; i < MAX_MSI_CTRLS; i++) {
+ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
+ (u32 *)&val);
+ if (val) {
++ ret = IRQ_HANDLED;
+ pos = 0;
+ while ((pos = find_next_bit(&val, 32, pos)) != 32) {
+ irq = irq_find_mapping(pp->irq_domain,
+@@ -176,6 +180,8 @@
+ }
+ }
+ }
++
++ return ret;
+ }
+
+ void dw_pcie_msi_init(struct pcie_port *pp)
+@@ -188,6 +194,19 @@
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
+ }
+
++void dw_pcie_msi_cfg_store(struct pcie_port *pp)
++{
++ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &pp->msi_enable);
++}
++
++void dw_pcie_msi_cfg_restore(struct pcie_port *pp)
++{
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
++ virt_to_phys((void *)pp->msi_data));
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, pp->msi_enable);
++}
++
+ static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
+ {
+ int flag = 1;
+@@ -212,27 +231,47 @@
+ return 0;
+ }
+
++static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
++{
++ unsigned int res, bit, val;
++
++ res = (irq / 32) * 12;
++ bit = irq % 32;
++ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
++ val &= ~(1 << bit);
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
++}
++
+ static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
+ unsigned int nvec, unsigned int pos)
+ {
+- unsigned int i, res, bit, val;
++ unsigned int i;
+
+ for (i = 0; i < nvec; i++) {
+ irq_set_msi_desc_off(irq_base, i, NULL);
+ clear_bit(pos + i, pp->msi_irq_in_use);
+ /* Disable corresponding interrupt on MSI controller */
+- res = ((pos + i) / 32) * 12;
+- bit = (pos + i) % 32;
+- dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
+- val &= ~(1 << bit);
+- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
++ if (pp->ops->msi_clear_irq)
++ pp->ops->msi_clear_irq(pp, pos + i);
++ else
++ dw_pcie_msi_clear_irq(pp, pos + i);
+ }
+ }
+
++static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
++{
++ unsigned int res, bit, val;
++
++ res = (irq / 32) * 12;
++ bit = irq % 32;
++ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
++ val |= 1 << bit;
++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
++}
++
+ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
+ {
+- int res, bit, irq, pos0, pos1, i;
+- u32 val;
++ int irq, pos0, pos1, i;
+ struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
+
+ if (!pp) {
+@@ -276,11 +315,10 @@
+ }
+ set_bit(pos0 + i, pp->msi_irq_in_use);
+ /*Enable corresponding interrupt in MSI interrupt controller */
+- res = ((pos0 + i) / 32) * 12;
+- bit = (pos0 + i) % 32;
+- dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
+- val |= 1 << bit;
+- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
++ if (pp->ops->msi_set_irq)
++ pp->ops->msi_set_irq(pp, pos0 + i);
++ else
++ dw_pcie_msi_set_irq(pp, pos0 + i);
+ }
+
+ *pos = pos0;
+@@ -294,14 +332,12 @@
+ static void clear_irq(unsigned int irq)
+ {
+ unsigned int pos, nvec;
+- struct irq_desc *desc;
+ struct msi_desc *msi;
+ struct pcie_port *pp;
+ struct irq_data *data = irq_get_irq_data(irq);
+
+ /* get the port structure */
+- desc = irq_to_desc(irq);
+- msi = irq_desc_get_msi_desc(desc);
++ msi = irq_data_get_msi(data);
+ pp = sys_to_pcie(msi->dev->bus->sysdata);
+ if (!pp) {
+ BUG();
+@@ -350,7 +386,10 @@
+ */
+ desc->msi_attrib.multiple = msgvec;
+
+- msg.address_lo = virt_to_phys((void *)pp->msi_data);
++ if (pp->ops->get_msi_data)
++ msg.address_lo = pp->ops->get_msi_data(pp);
++ else
++ msg.address_lo = virt_to_phys((void *)pp->msi_data);
+ msg.address_hi = 0x0;
+ msg.data = pos;
+ write_msi_msg(irq, &msg);
+@@ -393,10 +432,36 @@
+ int __init dw_pcie_host_init(struct pcie_port *pp)
+ {
+ struct device_node *np = pp->dev->of_node;
++ struct platform_device *pdev = to_platform_device(pp->dev);
+ struct of_pci_range range;
+ struct of_pci_range_parser parser;
+- u32 val;
+- int i;
++ struct resource *cfg_res;
++ u32 val, na, ns;
++ const __be32 *addrp;
++ int i, index, ret;
++
++ /* Find the address cell size and the number of cells in order to get
++ * the untranslated address.
++ */
++ of_property_read_u32(np, "#address-cells", &na);
++ ns = of_n_size_cells(np);
++
++ cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
++ if (cfg_res) {
++ pp->config.cfg0_size = resource_size(cfg_res)/2;
++ pp->config.cfg1_size = resource_size(cfg_res)/2;
++ pp->cfg.start = cfg_res->start;
++ pp->cfg0_base = cfg_res->start;
++ pp->cfg1_base = cfg_res->start + pp->config.cfg0_size;
++
++ /* Find the untranslated configuration space address */
++ index = of_property_match_string(np, "reg-names", "config");
++ addrp = of_get_address(np, index, false, false);
++ pp->cfg0_mod_base = of_read_number(addrp, ns);
++ pp->cfg1_mod_base = pp->cfg0_mod_base + pp->config.cfg0_size;
++ } else {
++ dev_err(pp->dev, "missing *config* reg space\n");
++ }
+
+ if (of_pci_range_parser_init(&parser, np)) {
+ dev_err(pp->dev, "missing ranges property\n");
+@@ -419,20 +484,46 @@
+ pp->config.io_size = resource_size(&pp->io);
+ pp->config.io_bus_addr = range.pci_addr;
+ pp->io_base = range.cpu_addr;
++
++ /* Find the untranslated IO space address */
++ pp->io_mod_base = of_read_number(parser.range -
++ parser.np + na, ns);
+ }
+ if (restype == IORESOURCE_MEM) {
+ of_pci_range_to_resource(&range, np, &pp->mem);
+ pp->mem.name = "MEM";
+ pp->config.mem_size = resource_size(&pp->mem);
+ pp->config.mem_bus_addr = range.pci_addr;
++
++ /* Find the untranslated MEM space address */
++ pp->mem_mod_base = of_read_number(parser.range -
++ parser.np + na, ns);
+ }
+ if (restype == 0) {
+ of_pci_range_to_resource(&range, np, &pp->cfg);
+ pp->config.cfg0_size = resource_size(&pp->cfg)/2;
+ pp->config.cfg1_size = resource_size(&pp->cfg)/2;
++ pp->cfg0_base = pp->cfg.start;
++ pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
++
++ /* Find the untranslated configuration space address */
++ pp->cfg0_mod_base = of_read_number(parser.range -
++ parser.np + na, ns);
++ pp->cfg1_mod_base = pp->cfg0_mod_base +
++ pp->config.cfg0_size;
+ }
+ }
+
++ ret = of_pci_parse_bus_range(np, &pp->busn);
++ if (ret < 0) {
++ pp->busn.name = np->name;
++ pp->busn.start = 0;
++ pp->busn.end = 0xff;
++ pp->busn.flags = IORESOURCE_BUS;
++ dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
++ ret, &pp->busn);
++ }
++
+ if (!pp->dbi_base) {
+ pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
+ resource_size(&pp->cfg));
+@@ -442,21 +533,26 @@
+ }
+ }
+
+- pp->cfg0_base = pp->cfg.start;
+- pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
+ pp->mem_base = pp->mem.start;
+
+- pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
+- pp->config.cfg0_size);
+ if (!pp->va_cfg0_base) {
+- dev_err(pp->dev, "error with ioremap in function\n");
+- return -ENOMEM;
++ pp->cfg0_base = pp->cfg.start;
++ pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
++ pp->config.cfg0_size);
++ if (!pp->va_cfg0_base) {
++ dev_err(pp->dev, "error with ioremap in function\n");
++ return -ENOMEM;
++ }
+ }
+- pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
+- pp->config.cfg1_size);
++
+ if (!pp->va_cfg1_base) {
+- dev_err(pp->dev, "error with ioremap\n");
+- return -ENOMEM;
++ pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
++ pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
++ pp->config.cfg1_size);
++ if (!pp->va_cfg1_base) {
++ dev_err(pp->dev, "error with ioremap\n");
++ return -ENOMEM;
++ }
+ }
+
+ if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
+@@ -465,26 +561,32 @@
+ }
+
+ if (IS_ENABLED(CONFIG_PCI_MSI)) {
+- pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
+- MAX_MSI_IRQS, &msi_domain_ops,
+- &dw_pcie_msi_chip);
+- if (!pp->irq_domain) {
+- dev_err(pp->dev, "irq domain init failed\n");
+- return -ENXIO;
+- }
++ if (!pp->ops->msi_host_init) {
++ pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
++ MAX_MSI_IRQS, &msi_domain_ops,
++ &dw_pcie_msi_chip);
++ if (!pp->irq_domain) {
++ dev_err(pp->dev, "irq domain init failed\n");
++ return -ENXIO;
++ }
+
+- for (i = 0; i < MAX_MSI_IRQS; i++)
+- irq_create_mapping(pp->irq_domain, i);
++ for (i = 0; i < MAX_MSI_IRQS; i++)
++ irq_create_mapping(pp->irq_domain, i);
++ } else {
++ ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
++ if (ret < 0)
++ return ret;
++ }
+ }
+
+- if (pp->ops->host_init)
+- pp->ops->host_init(pp);
++ if (pp->ops->host_init) {
++ ret = pp->ops->host_init(pp);
++ if (ret < 0)
++ return ret;
++ }
+
+ dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+
+- /* program correct class for RC */
+- dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+-
+ dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+@@ -492,8 +594,7 @@
+ dw_pci.nr_controllers = 1;
+ dw_pci.private_data = (void **)&pp;
+
+- pci_common_init(&dw_pci);
+- pci_assign_unassigned_resources();
++ pci_common_init_dev(pp->dev, &dw_pci);
+ #ifdef CONFIG_PCI_DOMAINS
+ dw_pci.domain++;
+ #endif
+@@ -506,9 +607,9 @@
+ /* Program viewport 0 : OUTBOUND : CFG0 */
+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_VIEWPORT);
+- dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
+- dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
+- dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
++ dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
++ dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
++ dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->config.cfg0_size - 1,
+ PCIE_ATU_LIMIT);
+ dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
+ dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+@@ -522,9 +623,9 @@
+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_VIEWPORT);
+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
+- dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
+- dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
+- dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
++ dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
++ dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
++ dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->config.cfg1_size - 1,
+ PCIE_ATU_LIMIT);
+ dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
+ dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
+@@ -537,9 +638,9 @@
+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_VIEWPORT);
+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
+- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
+- dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
+- dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
++ dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
++ dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
++ dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->config.mem_size - 1,
+ PCIE_ATU_LIMIT);
+ dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
+ dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
+@@ -553,9 +654,9 @@
+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
+ PCIE_ATU_VIEWPORT);
+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
+- dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
+- dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
+- dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
++ dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
++ dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
++ dw_pcie_writel_rc(pp, pp->io_mod_base + pp->config.io_size - 1,
+ PCIE_ATU_LIMIT);
+ dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
+ dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
+@@ -577,7 +678,9 @@
+ dw_pcie_prog_viewport_cfg0(pp, busdev);
+ ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
+ val);
+- dw_pcie_prog_viewport_mem_outbound(pp);
++ if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
++ && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
++ dw_pcie_prog_viewport_mem_outbound(pp);
+ } else {
+ dw_pcie_prog_viewport_cfg1(pp, busdev);
+ ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
+@@ -602,7 +705,9 @@
+ dw_pcie_prog_viewport_cfg0(pp, busdev);
+ ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
+ val);
+- dw_pcie_prog_viewport_mem_outbound(pp);
++ if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
++ && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
++ dw_pcie_prog_viewport_mem_outbound(pp);
+ } else {
+ dw_pcie_prog_viewport_cfg1(pp, busdev);
+ ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
+@@ -640,7 +745,6 @@
+ int size, u32 *val)
+ {
+ struct pcie_port *pp = sys_to_pcie(bus->sysdata);
+- unsigned long flags;
+ int ret;
+
+ if (!pp) {
+@@ -653,13 +757,15 @@
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
+- spin_lock_irqsave(&pp->conf_lock, flags);
+ if (bus->number != pp->root_bus_nr)
+- ret = dw_pcie_rd_other_conf(pp, bus, devfn,
++ if (pp->ops->rd_other_conf)
++ ret = pp->ops->rd_other_conf(pp, bus, devfn,
++ where, size, val);
++ else
++ ret = dw_pcie_rd_other_conf(pp, bus, devfn,
+ where, size, val);
+ else
+ ret = dw_pcie_rd_own_conf(pp, where, size, val);
+- spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+ }
+@@ -668,7 +774,6 @@
+ int where, int size, u32 val)
+ {
+ struct pcie_port *pp = sys_to_pcie(bus->sysdata);
+- unsigned long flags;
+ int ret;
+
+ if (!pp) {
+@@ -679,13 +784,15 @@
+ if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+- spin_lock_irqsave(&pp->conf_lock, flags);
+ if (bus->number != pp->root_bus_nr)
+- ret = dw_pcie_wr_other_conf(pp, bus, devfn,
++ if (pp->ops->wr_other_conf)
++ ret = pp->ops->wr_other_conf(pp, bus, devfn,
++ where, size, val);
++ else
++ ret = dw_pcie_wr_other_conf(pp, bus, devfn,
+ where, size, val);
+ else
+ ret = dw_pcie_wr_own_conf(pp, where, size, val);
+- spin_unlock_irqrestore(&pp->conf_lock, flags);
+
+ return ret;
+ }
+@@ -714,6 +821,7 @@
+
+ sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
+ pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
++ pci_add_resource(&sys->resources, &pp->busn);
+
+ return 1;
+ }
+@@ -723,14 +831,16 @@
+ struct pci_bus *bus;
+ struct pcie_port *pp = sys_to_pcie(sys);
+
+- if (pp) {
+- pp->root_bus_nr = sys->busnr;
+- bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
+- sys, &sys->resources);
+- } else {
+- bus = NULL;
+- BUG();
+- }
++ pp->root_bus_nr = sys->busnr;
++ bus = pci_create_root_bus(pp->dev, sys->busnr,
++ &dw_pcie_ops, sys, &sys->resources);
++ if (!bus)
++ return NULL;
++
++ pci_scan_child_bus(bus);
++
++ if (bus && pp->ops->scan_bus)
++ pp->ops->scan_bus(pp);
+
+ return bus;
+ }
+@@ -738,8 +848,13 @@
+ static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+ {
+ struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
++ int irq;
++
++ irq = of_irq_parse_and_map_pci(dev, slot, pin);
++ if (!irq)
++ irq = pp->irq;
+
+- return pp->irq;
++ return irq;
+ }
+
+ static void dw_pcie_add_bus(struct pci_bus *bus)
+@@ -766,7 +881,7 @@
+ u32 membase;
+ u32 memlimit;
+
+- /* set the number of lines as 4 */
++ /* set the number of lanes */
+ dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
+ val &= ~PORT_LINK_MODE_MASK;
+ switch (pp->lanes) {
+@@ -820,6 +935,11 @@
+ val = memlimit | membase;
+ dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
+
++ /* program correct class for RC */
++ dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val);
++ val |= PCI_CLASS_BRIDGE_PCI << 16;
++ dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION);
++
+ /* setup command register */
+ dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pcie-designware.h linux-3.14.72/drivers/pci/host/pcie-designware.h
+--- linux-3.14.72.orig/drivers/pci/host/pcie-designware.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pci/host/pcie-designware.h 2016-06-19 22:11:55.305140007 +0200
+@@ -36,15 +36,19 @@
+ u8 root_bus_nr;
+ void __iomem *dbi_base;
+ u64 cfg0_base;
++ u64 cfg0_mod_base;
+ void __iomem *va_cfg0_base;
+ u64 cfg1_base;
++ u64 cfg1_mod_base;
+ void __iomem *va_cfg1_base;
+ u64 io_base;
++ u64 io_mod_base;
+ u64 mem_base;
+- spinlock_t conf_lock;
++ u64 mem_mod_base;
+ struct resource cfg;
+ struct resource io;
+ struct resource mem;
++ struct resource busn;
+ struct pcie_port_info config;
+ int irq;
+ u32 lanes;
+@@ -52,6 +56,7 @@
+ int msi_irq;
+ struct irq_domain *irq_domain;
+ unsigned long msi_data;
++ unsigned int msi_enable;
+ DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
+ };
+
+@@ -62,14 +67,25 @@
+ u32 val, void __iomem *dbi_base);
+ int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
+ int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
++ int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
++ unsigned int devfn, int where, int size, u32 *val);
++ int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus,
++ unsigned int devfn, int where, int size, u32 val);
+ int (*link_up)(struct pcie_port *pp);
+- void (*host_init)(struct pcie_port *pp);
++ int (*host_init)(struct pcie_port *pp);
++ void (*msi_set_irq)(struct pcie_port *pp, int irq);
++ void (*msi_clear_irq)(struct pcie_port *pp, int irq);
++ u32 (*get_msi_data)(struct pcie_port *pp);
++ void (*scan_bus)(struct pcie_port *pp);
++ int (*msi_host_init)(struct pcie_port *pp, struct msi_chip *chip);
+ };
+
+ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
+ int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
+-void dw_handle_msi_irq(struct pcie_port *pp);
++irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
+ void dw_pcie_msi_init(struct pcie_port *pp);
++void dw_pcie_msi_cfg_store(struct pcie_port *pp);
++void dw_pcie_msi_cfg_restore(struct pcie_port *pp);
+ int dw_pcie_link_up(struct pcie_port *pp);
+ void dw_pcie_setup_rc(struct pcie_port *pp);
+ int dw_pcie_host_init(struct pcie_port *pp);
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pcie-rcar.c linux-3.14.72/drivers/pci/host/pcie-rcar.c
+--- linux-3.14.72.orig/drivers/pci/host/pcie-rcar.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/pci/host/pcie-rcar.c 2016-06-19 22:11:55.305140007 +0200
+@@ -0,0 +1,768 @@
++/*
++ * PCIe driver for Renesas R-Car SoCs
++ * Copyright (C) 2014 Renesas Electronics Europe Ltd
++ *
++ * Based on:
++ * arch/sh/drivers/pci/pcie-sh7786.c
++ * arch/sh/drivers/pci/ops-sh7786.c
++ * Copyright (C) 2009 - 2011 Paul Mundt
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++#include <linux/of_platform.h>
++#include <linux/pci.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++
++#define DRV_NAME "rcar-pcie"
++
++#define PCIECAR 0x000010
++#define PCIECCTLR 0x000018
++#define CONFIG_SEND_ENABLE (1 << 31)
++#define TYPE0 (0 << 8)
++#define TYPE1 (1 << 8)
++#define PCIECDR 0x000020
++#define PCIEMSR 0x000028
++#define PCIEINTXR 0x000400
++
++/* Transfer control */
++#define PCIETCTLR 0x02000
++#define CFINIT 1
++#define PCIETSTR 0x02004
++#define DATA_LINK_ACTIVE 1
++#define PCIEERRFR 0x02020
++#define UNSUPPORTED_REQUEST (1 << 4)
++
++/* root port address */
++#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
++
++/* local address reg & mask */
++#define PCIELAR(x) (0x02200 + ((x) * 0x20))
++#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
++#define LAM_PREFETCH (1 << 3)
++#define LAM_64BIT (1 << 2)
++#define LAR_ENABLE (1 << 1)
++
++/* PCIe address reg & mask */
++#define PCIEPARL(x) (0x03400 + ((x) * 0x20))
++#define PCIEPARH(x) (0x03404 + ((x) * 0x20))
++#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
++#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
++#define PAR_ENABLE (1 << 31)
++#define IO_SPACE (1 << 8)
++
++/* Configuration */
++#define PCICONF(x) (0x010000 + ((x) * 0x4))
++#define PMCAP(x) (0x010040 + ((x) * 0x4))
++#define EXPCAP(x) (0x010070 + ((x) * 0x4))
++#define VCCAP(x) (0x010100 + ((x) * 0x4))
++
++/* link layer */
++#define IDSETR1 0x011004
++#define TLCTLR 0x011048
++#define MACSR 0x011054
++#define MACCTLR 0x011058
++#define SCRAMBLE_DISABLE (1 << 27)
++
++/* R-Car H1 PHY */
++#define H1_PCIEPHYADRR 0x04000c
++#define WRITE_CMD (1 << 16)
++#define PHY_ACK (1 << 24)
++#define RATE_POS 12
++#define LANE_POS 8
++#define ADR_POS 0
++#define H1_PCIEPHYDOUTR 0x040014
++#define H1_PCIEPHYSR 0x040018
++
++#define RCONF(x) (PCICONF(0)+(x))
++#define RPMCAP(x) (PMCAP(0)+(x))
++#define REXPCAP(x) (EXPCAP(0)+(x))
++#define RVCCAP(x) (VCCAP(0)+(x))
++
++#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
++#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
++#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
++
++#define PCI_MAX_RESOURCES 4
++#define MAX_NR_INBOUND_MAPS 6
++
++/* Structure representing the PCIe interface */
++struct rcar_pcie {
++ struct device *dev;
++ void __iomem *base;
++ struct resource res[PCI_MAX_RESOURCES];
++ struct resource busn;
++ int root_bus_nr;
++ struct clk *clk;
++ struct clk *bus_clk;
++};
++
++static inline struct rcar_pcie *sys_to_pcie(struct pci_sys_data *sys)
++{
++ return sys->private_data;
++}
++
++static void pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
++ unsigned long reg)
++{
++ writel(val, pcie->base + reg);
++}
++
++static unsigned long pci_read_reg(struct rcar_pcie *pcie, unsigned long reg)
++{
++ return readl(pcie->base + reg);
++}
++
++enum {
++ PCI_ACCESS_READ,
++ PCI_ACCESS_WRITE,
++};
++
++static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
++{
++ int shift = 8 * (where & 3);
++ u32 val = pci_read_reg(pcie, where & ~3);
++
++ val &= ~(mask << shift);
++ val |= data << shift;
++ pci_write_reg(pcie, val, where & ~3);
++}
++
++static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
++{
++ int shift = 8 * (where & 3);
++ u32 val = pci_read_reg(pcie, where & ~3);
++
++ return val >> shift;
++}
++
++/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
++static int rcar_pcie_config_access(struct rcar_pcie *pcie,
++ unsigned char access_type, struct pci_bus *bus,
++ unsigned int devfn, int where, u32 *data)
++{
++ int dev, func, reg, index;
++
++ dev = PCI_SLOT(devfn);
++ func = PCI_FUNC(devfn);
++ reg = where & ~3;
++ index = reg / 4;
++
++ /*
++ * While each channel has its own memory-mapped extended config
++ * space, it's generally only accessible when in endpoint mode.
++ * When in root complex mode, the controller is unable to target
++ * itself with either type 0 or type 1 accesses, and indeed, any
++ * controller initiated target transfer to its own config space
++ * result in a completer abort.
++ *
++ * Each channel effectively only supports a single device, but as
++ * the same channel <-> device access works for any PCI_SLOT()
++ * value, we cheat a bit here and bind the controller's config
++ * space to devfn 0 in order to enable self-enumeration. In this
++ * case the regular ECAR/ECDR path is sidelined and the mangled
++ * config access itself is initiated as an internal bus transaction.
++ */
++ if (pci_is_root_bus(bus)) {
++ if (dev != 0)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (access_type == PCI_ACCESS_READ) {
++ *data = pci_read_reg(pcie, PCICONF(index));
++ } else {
++ /* Keep an eye out for changes to the root bus number */
++ if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
++ pcie->root_bus_nr = *data & 0xff;
++
++ pci_write_reg(pcie, *data, PCICONF(index));
++ }
++
++ return PCIBIOS_SUCCESSFUL;
++ }
++
++ if (pcie->root_bus_nr < 0)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /* Clear errors */
++ pci_write_reg(pcie, pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
++
++ /* Set the PIO address */
++ pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | PCIE_CONF_DEV(dev) |
++ PCIE_CONF_FUNC(func) | reg, PCIECAR);
++
++ /* Enable the configuration access */
++ if (bus->parent->number == pcie->root_bus_nr)
++ pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
++ else
++ pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
++
++ /* Check for errors */
++ if (pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ /* Check for master and target aborts */
++ if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
++ (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
++ return PCIBIOS_DEVICE_NOT_FOUND;
++
++ if (access_type == PCI_ACCESS_READ)
++ *data = pci_read_reg(pcie, PCIECDR);
++ else
++ pci_write_reg(pcie, *data, PCIECDR);
++
++ /* Disable the configuration access */
++ pci_write_reg(pcie, 0, PCIECCTLR);
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 *val)
++{
++ struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
++ int ret;
++
++ if ((size == 2) && (where & 1))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ else if ((size == 4) && (where & 3))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
++ bus, devfn, where, val);
++ if (ret != PCIBIOS_SUCCESSFUL) {
++ *val = 0xffffffff;
++ return ret;
++ }
++
++ if (size == 1)
++ *val = (*val >> (8 * (where & 3))) & 0xff;
++ else if (size == 2)
++ *val = (*val >> (8 * (where & 2))) & 0xffff;
++
++ dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x "
++ "where=0x%04x size=%d val=0x%08lx\n", bus->number,
++ devfn, where, size, (unsigned long)*val);
++
++ return ret;
++}
++
++/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
++static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 val)
++{
++ struct rcar_pcie *pcie = sys_to_pcie(bus->sysdata);
++ int shift, ret;
++ u32 data;
++
++ if ((size == 2) && (where & 1))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++ else if ((size == 4) && (where & 3))
++ return PCIBIOS_BAD_REGISTER_NUMBER;
++
++ ret = rcar_pcie_config_access(pcie, PCI_ACCESS_READ,
++ bus, devfn, where, &data);
++ if (ret != PCIBIOS_SUCCESSFUL)
++ return ret;
++
++ dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x "
++ "where=0x%04x size=%d val=0x%08lx\n", bus->number,
++ devfn, where, size, (unsigned long)val);
++
++ if (size == 1) {
++ shift = 8 * (where & 3);
++ data &= ~(0xff << shift);
++ data |= ((val & 0xff) << shift);
++ } else if (size == 2) {
++ shift = 8 * (where & 2);
++ data &= ~(0xffff << shift);
++ data |= ((val & 0xffff) << shift);
++ } else
++ data = val;
++
++ ret = rcar_pcie_config_access(pcie, PCI_ACCESS_WRITE,
++ bus, devfn, where, &data);
++
++ return ret;
++}
++
++static struct pci_ops rcar_pcie_ops = {
++ .read = rcar_pcie_read_conf,
++ .write = rcar_pcie_write_conf,
++};
++
++static void rcar_pcie_setup_window(int win, struct resource *res,
++ struct rcar_pcie *pcie)
++{
++ /* Setup PCIe address space mappings for each resource */
++ resource_size_t size;
++ u32 mask;
++
++ pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
++
++ /*
++ * The PAMR mask is calculated in units of 128Bytes, which
++ * keeps things pretty simple.
++ */
++ size = resource_size(res);
++ mask = (roundup_pow_of_two(size) / SZ_128) - 1;
++ pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
++
++ pci_write_reg(pcie, upper_32_bits(res->start), PCIEPARH(win));
++ pci_write_reg(pcie, lower_32_bits(res->start), PCIEPARL(win));
++
++ /* First resource is for IO */
++ mask = PAR_ENABLE;
++ if (res->flags & IORESOURCE_IO)
++ mask |= IO_SPACE;
++
++ pci_write_reg(pcie, mask, PCIEPTCTLR(win));
++}
++
++static int rcar_pcie_setup(int nr, struct pci_sys_data *sys)
++{
++ struct rcar_pcie *pcie = sys_to_pcie(sys);
++ struct resource *res;
++ int i;
++
++ pcie->root_bus_nr = -1;
++
++ /* Setup PCI resources */
++ for (i = 0; i < PCI_MAX_RESOURCES; i++) {
++
++ res = &pcie->res[i];
++ if (!res->flags)
++ continue;
++
++ rcar_pcie_setup_window(i, res, pcie);
++
++ if (res->flags & IORESOURCE_IO)
++ pci_ioremap_io(nr * SZ_64K, res->start);
++ else
++ pci_add_resource(&sys->resources, res);
++ }
++ pci_add_resource(&sys->resources, &pcie->busn);
++
++ return 1;
++}
++
++struct hw_pci rcar_pci = {
++ .setup = rcar_pcie_setup,
++ .map_irq = of_irq_parse_and_map_pci,
++ .ops = &rcar_pcie_ops,
++};
++
++static void rcar_pcie_enable(struct rcar_pcie *pcie)
++{
++ struct platform_device *pdev = to_platform_device(pcie->dev);
++
++ rcar_pci.nr_controllers = 1;
++ rcar_pci.private_data = (void **)&pcie;
++
++ pci_common_init_dev(&pdev->dev, &rcar_pci);
++#ifdef CONFIG_PCI_DOMAINS
++ rcar_pci.domain++;
++#endif
++}
++
++static int phy_wait_for_ack(struct rcar_pcie *pcie)
++{
++ unsigned int timeout = 100;
++
++ while (timeout--) {
++ if (pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
++ return 0;
++
++ udelay(100);
++ }
++
++ dev_err(pcie->dev, "Access to PCIe phy timed out\n");
++
++ return -ETIMEDOUT;
++}
++
++static void phy_write_reg(struct rcar_pcie *pcie,
++ unsigned int rate, unsigned int addr,
++ unsigned int lane, unsigned int data)
++{
++ unsigned long phyaddr;
++
++ phyaddr = WRITE_CMD |
++ ((rate & 1) << RATE_POS) |
++ ((lane & 0xf) << LANE_POS) |
++ ((addr & 0xff) << ADR_POS);
++
++ /* Set write data */
++ pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
++ pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
++
++ /* Ignore errors as they will be dealt with if the data link is down */
++ phy_wait_for_ack(pcie);
++
++ /* Clear command */
++ pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
++ pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
++
++ /* Ignore errors as they will be dealt with if the data link is down */
++ phy_wait_for_ack(pcie);
++}
++
++static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
++{
++ unsigned int timeout = 10;
++
++ while (timeout--) {
++ if ((pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
++ return 0;
++
++ msleep(5);
++ }
++
++ return -ETIMEDOUT;
++}
++
++static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
++{
++ int err;
++
++ /* Begin initialization */
++ pci_write_reg(pcie, 0, PCIETCTLR);
++
++ /* Set mode */
++ pci_write_reg(pcie, 1, PCIEMSR);
++
++ /*
++ * Initial header for port config space is type 1, set the device
++ * class to match. Hardware takes care of propagating the IDSETR
++ * settings, so there is no need to bother with a quirk.
++ */
++ pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
++
++ /*
++ * Setup Secondary Bus Number & Subordinate Bus Number, even though
++ * they aren't used, to avoid bridge being detected as broken.
++ */
++ rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
++ rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
++
++ /* Initialize default capabilities. */
++ rcar_rmw32(pcie, REXPCAP(0), 0, PCI_CAP_ID_EXP);
++ rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
++ PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
++ rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
++ PCI_HEADER_TYPE_BRIDGE);
++
++ /* Enable data link layer active state reporting */
++ rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), 0, PCI_EXP_LNKCAP_DLLLARC);
++
++ /* Write out the physical slot number = 0 */
++ rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
++
++ /* Set the completion timer timeout to the maximum 50ms. */
++ rcar_rmw32(pcie, TLCTLR+1, 0x3f, 50);
++
++ /* Terminate list of capabilities (Next Capability Offset=0) */
++ rcar_rmw32(pcie, RVCCAP(0), 0xfff0, 0);
++
++ /* Enable MAC data scrambling. */
++ rcar_rmw32(pcie, MACCTLR, SCRAMBLE_DISABLE, 0);
++
++ /* Finish initialization - establish a PCI Express link */
++ pci_write_reg(pcie, CFINIT, PCIETCTLR);
++
++ /* This will timeout if we don't have a link. */
++ err = rcar_pcie_wait_for_dl(pcie);
++ if (err)
++ return err;
++
++ /* Enable INTx interrupts */
++ rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
++
++ /* Enable slave Bus Mastering */
++ rcar_rmw32(pcie, RCONF(PCI_STATUS), PCI_STATUS_DEVSEL_MASK,
++ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
++ PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST);
++
++ wmb();
++
++ return 0;
++}
++
++static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
++{
++ unsigned int timeout = 10;
++
++ /* Initialize the phy */
++ phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
++ phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
++ phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
++ phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
++ phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
++ phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
++ phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
++ phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
++ phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
++ phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
++ phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
++ phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
++
++ phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
++ phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
++ phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
++
++ while (timeout--) {
++ if (pci_read_reg(pcie, H1_PCIEPHYSR))
++ return rcar_pcie_hw_init(pcie);
++
++ msleep(5);
++ }
++
++ return -ETIMEDOUT;
++}
++
++static int rcar_pcie_get_resources(struct platform_device *pdev,
++ struct rcar_pcie *pcie)
++{
++ struct resource res;
++ int err;
++
++ err = of_address_to_resource(pdev->dev.of_node, 0, &res);
++ if (err)
++ return err;
++
++ pcie->clk = devm_clk_get(&pdev->dev, "pcie");
++ if (IS_ERR(pcie->clk)) {
++ dev_err(pcie->dev, "cannot get platform clock\n");
++ return PTR_ERR(pcie->clk);
++ }
++ err = clk_prepare_enable(pcie->clk);
++ if (err)
++ goto fail_clk;
++
++ pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
++ if (IS_ERR(pcie->bus_clk)) {
++ dev_err(pcie->dev, "cannot get pcie bus clock\n");
++ err = PTR_ERR(pcie->bus_clk);
++ goto fail_clk;
++ }
++ err = clk_prepare_enable(pcie->bus_clk);
++ if (err)
++ goto err_map_reg;
++
++ pcie->base = devm_ioremap_resource(&pdev->dev, &res);
++ if (IS_ERR(pcie->base)) {
++ err = PTR_ERR(pcie->base);
++ goto err_map_reg;
++ }
++
++ return 0;
++
++err_map_reg:
++ clk_disable_unprepare(pcie->bus_clk);
++fail_clk:
++ clk_disable_unprepare(pcie->clk);
++
++ return err;
++}
++
++static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
++ struct of_pci_range *range,
++ int *index)
++{
++ u64 restype = range->flags;
++ u64 cpu_addr = range->cpu_addr;
++ u64 cpu_end = range->cpu_addr + range->size;
++ u64 pci_addr = range->pci_addr;
++ u32 flags = LAM_64BIT | LAR_ENABLE;
++ u64 mask;
++ u64 size;
++ int idx = *index;
++
++ if (restype & IORESOURCE_PREFETCH)
++ flags |= LAM_PREFETCH;
++
++ /*
++ * If the size of the range is larger than the alignment of the start
++ * address, we have to use multiple entries to perform the mapping.
++ */
++ if (cpu_addr > 0) {
++ unsigned long nr_zeros = __ffs64(cpu_addr);
++ u64 alignment = 1ULL << nr_zeros;
++ size = min(range->size, alignment);
++ } else {
++ size = range->size;
++ }
++ /* Hardware supports max 4GiB inbound region */
++ size = min(size, 1ULL << 32);
++
++ mask = roundup_pow_of_two(size) - 1;
++ mask &= ~0xf;
++
++ while (cpu_addr < cpu_end) {
++ /*
++ * Set up 64-bit inbound regions as the range parser doesn't
++ * distinguish between 32 and 64-bit types.
++ */
++ pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
++ pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
++ pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
++
++ pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
++ pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
++ pci_write_reg(pcie, 0, PCIELAMR(idx+1));
++
++ pci_addr += size;
++ cpu_addr += size;
++ idx += 2;
++
++ if (idx > MAX_NR_INBOUND_MAPS) {
++ dev_err(pcie->dev, "Failed to map inbound regions!\n");
++ return -EINVAL;
++ }
++ }
++ *index = idx;
++
++ return 0;
++}
++
++static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
++ struct device_node *node)
++{
++ const int na = 3, ns = 2;
++ int rlen;
++
++ parser->node = node;
++ parser->pna = of_n_addr_cells(node);
++ parser->np = parser->pna + na + ns;
++
++ parser->range = of_get_property(node, "dma-ranges", &rlen);
++ if (!parser->range)
++ return -ENOENT;
++
++ parser->end = parser->range + rlen / sizeof(__be32);
++ return 0;
++}
++
++static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
++ struct device_node *np)
++{
++ struct of_pci_range range;
++ struct of_pci_range_parser parser;
++ int index = 0;
++ int err;
++
++ if (pci_dma_range_parser_init(&parser, np))
++ return -EINVAL;
++
++ /* Get the dma-ranges from DT */
++ for_each_of_pci_range(&parser, &range) {
++ u64 end = range.cpu_addr + range.size - 1;
++ dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
++ range.flags, range.cpu_addr, end, range.pci_addr);
++
++ err = rcar_pcie_inbound_ranges(pcie, &range, &index);
++ if (err)
++ return err;
++ }
++
++ return 0;
++}
++
++static const struct of_device_id rcar_pcie_of_match[] = {
++ { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
++ { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init },
++ { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
++
++static int rcar_pcie_probe(struct platform_device *pdev)
++{
++ struct rcar_pcie *pcie;
++ unsigned int data;
++ struct of_pci_range range;
++ struct of_pci_range_parser parser;
++ const struct of_device_id *of_id;
++ int err, win = 0;
++ int (*hw_init_fn)(struct rcar_pcie *);
++
++ pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
++ if (!pcie)
++ return -ENOMEM;
++
++ pcie->dev = &pdev->dev;
++ platform_set_drvdata(pdev, pcie);
++
++ /* Get the bus range */
++ if (of_pci_parse_bus_range(pdev->dev.of_node, &pcie->busn)) {
++ dev_err(&pdev->dev, "failed to parse bus-range property\n");
++ return -EINVAL;
++ }
++
++ if (of_pci_range_parser_init(&parser, pdev->dev.of_node)) {
++ dev_err(&pdev->dev, "missing ranges property\n");
++ return -EINVAL;
++ }
++
++ err = rcar_pcie_get_resources(pdev, pcie);
++ if (err < 0) {
++ dev_err(&pdev->dev, "failed to request resources: %d\n", err);
++ return err;
++ }
++
++ for_each_of_pci_range(&parser, &range) {
++ of_pci_range_to_resource(&range, pdev->dev.of_node,
++ &pcie->res[win++]);
++
++ if (win > PCI_MAX_RESOURCES)
++ break;
++ }
++
++ err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
++ if (err)
++ return err;
++
++ of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
++ if (!of_id || !of_id->data)
++ return -EINVAL;
++ hw_init_fn = of_id->data;
++
++ /* Failure to get a link might just be that no cards are inserted */
++ err = hw_init_fn(pcie);
++ if (err) {
++ dev_info(&pdev->dev, "PCIe link down\n");
++ return 0;
++ }
++
++ data = pci_read_reg(pcie, MACSR);
++ dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
++
++ rcar_pcie_enable(pcie);
++
++ return 0;
++}
++
++static struct platform_driver rcar_pcie_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = rcar_pcie_of_match,
++ .suppress_bind_attrs = true,
++ },
++ .probe = rcar_pcie_probe,
++};
++module_platform_driver(rcar_pcie_driver);
++
++MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
++MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
++MODULE_LICENSE("GPLv2");
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pcie-spear13xx.c linux-3.14.72/drivers/pci/host/pcie-spear13xx.c
+--- linux-3.14.72.orig/drivers/pci/host/pcie-spear13xx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/pci/host/pcie-spear13xx.c 2016-06-19 22:11:55.305140007 +0200
+@@ -0,0 +1,407 @@
++/*
++ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
++ *
++ * SPEAr13xx PCIe Glue Layer Source Code
++ *
++ * Copyright (C) 2010-2014 ST Microelectronics
++ * Pratyush Anand <pratyush.anand@st.com>
++ * Mohit Kumar <mohit.kumar@st.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/pci.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/resource.h>
++
++#include "pcie-designware.h"
++
++struct spear13xx_pcie {
++ void __iomem *app_base;
++ struct phy *phy;
++ struct clk *clk;
++ struct pcie_port pp;
++ bool is_gen1;
++};
++
++struct pcie_app_reg {
++ u32 app_ctrl_0; /* cr0 */
++ u32 app_ctrl_1; /* cr1 */
++ u32 app_status_0; /* cr2 */
++ u32 app_status_1; /* cr3 */
++ u32 msg_status; /* cr4 */
++ u32 msg_payload; /* cr5 */
++ u32 int_sts; /* cr6 */
++ u32 int_clr; /* cr7 */
++ u32 int_mask; /* cr8 */
++ u32 mst_bmisc; /* cr9 */
++ u32 phy_ctrl; /* cr10 */
++ u32 phy_status; /* cr11 */
++ u32 cxpl_debug_info_0; /* cr12 */
++ u32 cxpl_debug_info_1; /* cr13 */
++ u32 ven_msg_ctrl_0; /* cr14 */
++ u32 ven_msg_ctrl_1; /* cr15 */
++ u32 ven_msg_data_0; /* cr16 */
++ u32 ven_msg_data_1; /* cr17 */
++ u32 ven_msi_0; /* cr18 */
++ u32 ven_msi_1; /* cr19 */
++ u32 mst_rmisc; /* cr20 */
++};
++
++/* CR0 ID */
++#define RX_LANE_FLIP_EN_ID 0
++#define TX_LANE_FLIP_EN_ID 1
++#define SYS_AUX_PWR_DET_ID 2
++#define APP_LTSSM_ENABLE_ID 3
++#define SYS_ATTEN_BUTTON_PRESSED_ID 4
++#define SYS_MRL_SENSOR_STATE_ID 5
++#define SYS_PWR_FAULT_DET_ID 6
++#define SYS_MRL_SENSOR_CHGED_ID 7
++#define SYS_PRE_DET_CHGED_ID 8
++#define SYS_CMD_CPLED_INT_ID 9
++#define APP_INIT_RST_0_ID 11
++#define APP_REQ_ENTR_L1_ID 12
++#define APP_READY_ENTR_L23_ID 13
++#define APP_REQ_EXIT_L1_ID 14
++#define DEVICE_TYPE_EP (0 << 25)
++#define DEVICE_TYPE_LEP (1 << 25)
++#define DEVICE_TYPE_RC (4 << 25)
++#define SYS_INT_ID 29
++#define MISCTRL_EN_ID 30
++#define REG_TRANSLATION_ENABLE 31
++
++/* CR1 ID */
++#define APPS_PM_XMT_TURNOFF_ID 2
++#define APPS_PM_XMT_PME_ID 5
++
++/* CR3 ID */
++#define XMLH_LTSSM_STATE_DETECT_QUIET 0x00
++#define XMLH_LTSSM_STATE_DETECT_ACT 0x01
++#define XMLH_LTSSM_STATE_POLL_ACTIVE 0x02
++#define XMLH_LTSSM_STATE_POLL_COMPLIANCE 0x03
++#define XMLH_LTSSM_STATE_POLL_CONFIG 0x04
++#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET 0x05
++#define XMLH_LTSSM_STATE_DETECT_WAIT 0x06
++#define XMLH_LTSSM_STATE_CFG_LINKWD_START 0x07
++#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT 0x08
++#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT 0x09
++#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT 0x0A
++#define XMLH_LTSSM_STATE_CFG_COMPLETE 0x0B
++#define XMLH_LTSSM_STATE_CFG_IDLE 0x0C
++#define XMLH_LTSSM_STATE_RCVRY_LOCK 0x0D
++#define XMLH_LTSSM_STATE_RCVRY_SPEED 0x0E
++#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG 0x0F
++#define XMLH_LTSSM_STATE_RCVRY_IDLE 0x10
++#define XMLH_LTSSM_STATE_L0 0x11
++#define XMLH_LTSSM_STATE_L0S 0x12
++#define XMLH_LTSSM_STATE_L123_SEND_EIDLE 0x13
++#define XMLH_LTSSM_STATE_L1_IDLE 0x14
++#define XMLH_LTSSM_STATE_L2_IDLE 0x15
++#define XMLH_LTSSM_STATE_L2_WAKE 0x16
++#define XMLH_LTSSM_STATE_DISABLED_ENTRY 0x17
++#define XMLH_LTSSM_STATE_DISABLED_IDLE 0x18
++#define XMLH_LTSSM_STATE_DISABLED 0x19
++#define XMLH_LTSSM_STATE_LPBK_ENTRY 0x1A
++#define XMLH_LTSSM_STATE_LPBK_ACTIVE 0x1B
++#define XMLH_LTSSM_STATE_LPBK_EXIT 0x1C
++#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT 0x1D
++#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY 0x1E
++#define XMLH_LTSSM_STATE_HOT_RESET 0x1F
++#define XMLH_LTSSM_STATE_MASK 0x3F
++#define XMLH_LINK_UP (1 << 6)
++
++/* CR4 ID */
++#define CFG_MSI_EN_ID 18
++
++/* CR6 */
++#define INTA_CTRL_INT (1 << 7)
++#define INTB_CTRL_INT (1 << 8)
++#define INTC_CTRL_INT (1 << 9)
++#define INTD_CTRL_INT (1 << 10)
++#define MSI_CTRL_INT (1 << 26)
++
++/* CR19 ID */
++#define VEN_MSI_REQ_ID 11
++#define VEN_MSI_FUN_NUM_ID 8
++#define VEN_MSI_TC_ID 5
++#define VEN_MSI_VECTOR_ID 0
++#define VEN_MSI_REQ_EN ((u32)0x1 << VEN_MSI_REQ_ID)
++#define VEN_MSI_FUN_NUM_MASK ((u32)0x7 << VEN_MSI_FUN_NUM_ID)
++#define VEN_MSI_TC_MASK ((u32)0x7 << VEN_MSI_TC_ID)
++#define VEN_MSI_VECTOR_MASK ((u32)0x1F << VEN_MSI_VECTOR_ID)
++
++#define EXP_CAP_ID_OFFSET 0x70
++
++#define to_spear13xx_pcie(x) container_of(x, struct spear13xx_pcie, pp)
++
++static int spear13xx_pcie_establish_link(struct pcie_port *pp)
++{
++ u32 val;
++ int count = 0;
++ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
++ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
++ u32 exp_cap_off = EXP_CAP_ID_OFFSET;
++
++ if (dw_pcie_link_up(pp)) {
++ dev_err(pp->dev, "link already up\n");
++ return 0;
++ }
++
++ dw_pcie_setup_rc(pp);
++
++ /*
++ * this controller support only 128 bytes read size, however its
++ * default value in capability register is 512 bytes. So force
++ * it to 128 here.
++ */
++ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
++ val &= ~PCI_EXP_DEVCTL_READRQ;
++ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
++
++ dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
++ dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
++
++ /*
++ * if is_gen1 is set then handle it, so that some buggy card
++ * also works
++ */
++ if (spear13xx_pcie->is_gen1) {
++ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
++ &val);
++ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
++ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
++ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
++ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
++ PCI_EXP_LNKCAP, 4, val);
++ }
++
++ dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
++ &val);
++ if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
++ val &= ~((u32)PCI_EXP_LNKCAP_SLS);
++ val |= PCI_EXP_LNKCAP_SLS_2_5GB;
++ dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
++ PCI_EXP_LNKCTL2, 4, val);
++ }
++ }
++
++ /* enable ltssm */
++ writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
++ | (1 << APP_LTSSM_ENABLE_ID)
++ | ((u32)1 << REG_TRANSLATION_ENABLE),
++ &app_reg->app_ctrl_0);
++
++ /* check if the link is up or not */
++ while (!dw_pcie_link_up(pp)) {
++ mdelay(100);
++ count++;
++ if (count == 10) {
++ dev_err(pp->dev, "link Fail\n");
++ return -EINVAL;
++ }
++ }
++ dev_info(pp->dev, "link up\n");
++
++ return 0;
++}
++
++static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
++{
++ struct pcie_port *pp = arg;
++ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
++ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
++ unsigned int status;
++
++ status = readl(&app_reg->int_sts);
++
++ if (status & MSI_CTRL_INT) {
++ if (!IS_ENABLED(CONFIG_PCI_MSI))
++ BUG();
++ dw_handle_msi_irq(pp);
++ }
++
++ writel(status, &app_reg->int_clr);
++
++ return IRQ_HANDLED;
++}
++
++static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
++{
++ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
++ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
++
++ /* Enable MSI interrupt */
++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
++ dw_pcie_msi_init(pp);
++ writel(readl(&app_reg->int_mask) |
++ MSI_CTRL_INT, &app_reg->int_mask);
++ }
++}
++
++static int spear13xx_pcie_link_up(struct pcie_port *pp)
++{
++ struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
++ struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
++
++ if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
++ return 1;
++
++ return 0;
++}
++
++static int spear13xx_pcie_host_init(struct pcie_port *pp)
++{
++ spear13xx_pcie_establish_link(pp);
++ spear13xx_pcie_enable_interrupts(pp);
++
++ return 0;
++}
++
++static struct pcie_host_ops spear13xx_pcie_host_ops = {
++ .link_up = spear13xx_pcie_link_up,
++ .host_init = spear13xx_pcie_host_init,
++};
++
++static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ int ret;
++
++ pp->irq = platform_get_irq(pdev, 0);
++ if (!pp->irq) {
++ dev_err(dev, "failed to get irq\n");
++ return -ENODEV;
++ }
++ ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
++ IRQF_SHARED, "spear1340-pcie", pp);
++ if (ret) {
++ dev_err(dev, "failed to request irq %d\n", pp->irq);
++ return ret;
++ }
++
++ pp->root_bus_nr = -1;
++ pp->ops = &spear13xx_pcie_host_ops;
++
++ ret = dw_pcie_host_init(pp);
++ if (ret) {
++ dev_err(dev, "failed to initialize host\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static int __init spear13xx_pcie_probe(struct platform_device *pdev)
++{
++ struct spear13xx_pcie *spear13xx_pcie;
++ struct pcie_port *pp;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = pdev->dev.of_node;
++ struct resource *dbi_base;
++ int ret;
++
++ spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
++ if (!spear13xx_pcie) {
++ dev_err(dev, "no memory for SPEAr13xx pcie\n");
++ return -ENOMEM;
++ }
++
++ spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
++ if (IS_ERR(spear13xx_pcie->phy)) {
++ ret = PTR_ERR(spear13xx_pcie->phy);
++ if (ret == -EPROBE_DEFER)
++ dev_info(dev, "probe deferred\n");
++ else
++ dev_err(dev, "couldn't get pcie-phy\n");
++ return ret;
++ }
++
++ phy_init(spear13xx_pcie->phy);
++
++ spear13xx_pcie->clk = devm_clk_get(dev, NULL);
++ if (IS_ERR(spear13xx_pcie->clk)) {
++ dev_err(dev, "couldn't get clk for pcie\n");
++ return PTR_ERR(spear13xx_pcie->clk);
++ }
++ ret = clk_prepare_enable(spear13xx_pcie->clk);
++ if (ret) {
++ dev_err(dev, "couldn't enable clk for pcie\n");
++ return ret;
++ }
++
++ pp = &spear13xx_pcie->pp;
++
++ pp->dev = dev;
++
++ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
++ if (IS_ERR(pp->dbi_base)) {
++ dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
++ ret = PTR_ERR(pp->dbi_base);
++ goto fail_clk;
++ }
++ spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
++
++ if (of_property_read_bool(np, "st,pcie-is-gen1"))
++ spear13xx_pcie->is_gen1 = true;
++
++ ret = add_pcie_port(pp, pdev);
++ if (ret < 0)
++ goto fail_clk;
++
++ platform_set_drvdata(pdev, spear13xx_pcie);
++ return 0;
++
++fail_clk:
++ clk_disable_unprepare(spear13xx_pcie->clk);
++
++ return ret;
++}
++
++static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
++{
++ struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
++
++ clk_disable_unprepare(spear13xx_pcie->clk);
++
++ phy_exit(spear13xx_pcie->phy);
++
++ return 0;
++}
++
++static const struct of_device_id spear13xx_pcie_of_match[] = {
++ { .compatible = "st,spear1340-pcie", },
++ {},
++};
++MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
++
++static struct platform_driver spear13xx_pcie_driver = {
++ .probe = spear13xx_pcie_probe,
++ .remove = spear13xx_pcie_remove,
++ .driver = {
++ .name = "spear-pcie",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
++ },
++};
++
++/* SPEAr13xx PCIe driver does not allow module unload */
++
++static int __init pcie_init(void)
++{
++ return platform_driver_register(&spear13xx_pcie_driver);
++}
++module_init(pcie_init);
++
++MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
++MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pci-exynos.c linux-3.14.72/drivers/pci/host/pci-exynos.c
+--- linux-3.14.72.orig/drivers/pci/host/pci-exynos.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pci/host/pci-exynos.c 2016-06-19 22:11:55.305140007 +0200
+@@ -415,9 +415,7 @@
+ {
+ struct pcie_port *pp = arg;
+
+- dw_handle_msi_irq(pp);
+-
+- return IRQ_HANDLED;
++ return dw_handle_msi_irq(pp);
+ }
+
+ static void exynos_pcie_msi_init(struct pcie_port *pp)
+@@ -496,10 +494,12 @@
+ return 0;
+ }
+
+-static void exynos_pcie_host_init(struct pcie_port *pp)
++static int exynos_pcie_host_init(struct pcie_port *pp)
+ {
+ exynos_pcie_establish_link(pp);
+ exynos_pcie_enable_interrupts(pp);
++
++ return 0;
+ }
+
+ static struct pcie_host_ops exynos_pcie_host_ops = {
+@@ -511,7 +511,8 @@
+ .host_init = exynos_pcie_host_init,
+ };
+
+-static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
++static int __init add_pcie_port(struct pcie_port *pp,
++ struct platform_device *pdev)
+ {
+ int ret;
+
+@@ -546,7 +547,6 @@
+ pp->root_bus_nr = -1;
+ pp->ops = &exynos_pcie_host_ops;
+
+- spin_lock_init(&pp->conf_lock);
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to initialize host\n");
+@@ -568,10 +568,8 @@
+
+ exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie),
+ GFP_KERNEL);
+- if (!exynos_pcie) {
+- dev_err(&pdev->dev, "no memory for exynos pcie\n");
++ if (!exynos_pcie)
+ return -ENOMEM;
+- }
+
+ pp = &exynos_pcie->pp;
+
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pci-host-generic.c linux-3.14.72/drivers/pci/host/pci-host-generic.c
+--- linux-3.14.72.orig/drivers/pci/host/pci-host-generic.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/pci/host/pci-host-generic.c 2016-06-19 22:11:55.305140007 +0200
+@@ -0,0 +1,388 @@
++/*
++ * Simple, generic PCI host controller driver targetting firmware-initialised
++ * systems and virtual machines (e.g. the PCI emulation provided by kvmtool).
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * Copyright (C) 2014 ARM Limited
++ *
++ * Author: Will Deacon <will.deacon@arm.com>
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_address.h>
++#include <linux/of_pci.h>
++#include <linux/platform_device.h>
++
++struct gen_pci_cfg_bus_ops {
++ u32 bus_shift;
++ void __iomem *(*map_bus)(struct pci_bus *, unsigned int, int);
++};
++
++struct gen_pci_cfg_windows {
++ struct resource res;
++ struct resource bus_range;
++ void __iomem **win;
++
++ const struct gen_pci_cfg_bus_ops *ops;
++};
++
++struct gen_pci {
++ struct pci_host_bridge host;
++ struct gen_pci_cfg_windows cfg;
++ struct list_head resources;
++};
++
++static void __iomem *gen_pci_map_cfg_bus_cam(struct pci_bus *bus,
++ unsigned int devfn,
++ int where)
++{
++ struct pci_sys_data *sys = bus->sysdata;
++ struct gen_pci *pci = sys->private_data;
++ resource_size_t idx = bus->number - pci->cfg.bus_range.start;
++
++ return pci->cfg.win[idx] + ((devfn << 8) | where);
++}
++
++static struct gen_pci_cfg_bus_ops gen_pci_cfg_cam_bus_ops = {
++ .bus_shift = 16,
++ .map_bus = gen_pci_map_cfg_bus_cam,
++};
++
++static void __iomem *gen_pci_map_cfg_bus_ecam(struct pci_bus *bus,
++ unsigned int devfn,
++ int where)
++{
++ struct pci_sys_data *sys = bus->sysdata;
++ struct gen_pci *pci = sys->private_data;
++ resource_size_t idx = bus->number - pci->cfg.bus_range.start;
++
++ return pci->cfg.win[idx] + ((devfn << 12) | where);
++}
++
++static struct gen_pci_cfg_bus_ops gen_pci_cfg_ecam_bus_ops = {
++ .bus_shift = 20,
++ .map_bus = gen_pci_map_cfg_bus_ecam,
++};
++
++static int gen_pci_config_read(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 *val)
++{
++ void __iomem *addr;
++ struct pci_sys_data *sys = bus->sysdata;
++ struct gen_pci *pci = sys->private_data;
++
++ addr = pci->cfg.ops->map_bus(bus, devfn, where);
++
++ switch (size) {
++ case 1:
++ *val = readb(addr);
++ break;
++ case 2:
++ *val = readw(addr);
++ break;
++ default:
++ *val = readl(addr);
++ }
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static int gen_pci_config_write(struct pci_bus *bus, unsigned int devfn,
++ int where, int size, u32 val)
++{
++ void __iomem *addr;
++ struct pci_sys_data *sys = bus->sysdata;
++ struct gen_pci *pci = sys->private_data;
++
++ addr = pci->cfg.ops->map_bus(bus, devfn, where);
++
++ switch (size) {
++ case 1:
++ writeb(val, addr);
++ break;
++ case 2:
++ writew(val, addr);
++ break;
++ default:
++ writel(val, addr);
++ }
++
++ return PCIBIOS_SUCCESSFUL;
++}
++
++static struct pci_ops gen_pci_ops = {
++ .read = gen_pci_config_read,
++ .write = gen_pci_config_write,
++};
++
++static const struct of_device_id gen_pci_of_match[] = {
++ { .compatible = "pci-host-cam-generic",
++ .data = &gen_pci_cfg_cam_bus_ops },
++
++ { .compatible = "pci-host-ecam-generic",
++ .data = &gen_pci_cfg_ecam_bus_ops },
++
++ { },
++};
++MODULE_DEVICE_TABLE(of, gen_pci_of_match);
++
++static int gen_pci_calc_io_offset(struct device *dev,
++ struct of_pci_range *range,
++ struct resource *res,
++ resource_size_t *offset)
++{
++ static atomic_t wins = ATOMIC_INIT(0);
++ int err, idx, max_win;
++ unsigned int window;
++
++ if (!PAGE_ALIGNED(range->cpu_addr))
++ return -EINVAL;
++
++ max_win = (IO_SPACE_LIMIT + 1) / SZ_64K;
++ idx = atomic_inc_return(&wins);
++ if (idx > max_win)
++ return -ENOSPC;
++
++ window = (idx - 1) * SZ_64K;
++ err = pci_ioremap_io(window, range->cpu_addr);
++ if (err)
++ return err;
++
++ of_pci_range_to_resource(range, dev->of_node, res);
++ res->start = window;
++ res->end = res->start + range->size - 1;
++ *offset = window - range->pci_addr;
++ return 0;
++}
++
++static int gen_pci_calc_mem_offset(struct device *dev,
++ struct of_pci_range *range,
++ struct resource *res,
++ resource_size_t *offset)
++{
++ of_pci_range_to_resource(range, dev->of_node, res);
++ *offset = range->cpu_addr - range->pci_addr;
++ return 0;
++}
++
++static void gen_pci_release_of_pci_ranges(struct gen_pci *pci)
++{
++ struct pci_host_bridge_window *win;
++
++ list_for_each_entry(win, &pci->resources, list)
++ release_resource(win->res);
++
++ pci_free_resource_list(&pci->resources);
++}
++
++static int gen_pci_parse_request_of_pci_ranges(struct gen_pci *pci)
++{
++ struct of_pci_range range;
++ struct of_pci_range_parser parser;
++ int err, res_valid = 0;
++ struct device *dev = pci->host.dev.parent;
++ struct device_node *np = dev->of_node;
++
++ if (of_pci_range_parser_init(&parser, np)) {
++ dev_err(dev, "missing \"ranges\" property\n");
++ return -EINVAL;
++ }
++
++ for_each_of_pci_range(&parser, &range) {
++ struct resource *parent, *res;
++ resource_size_t offset;
++ u32 restype = range.flags & IORESOURCE_TYPE_BITS;
++
++ res = devm_kmalloc(dev, sizeof(*res), GFP_KERNEL);
++ if (!res) {
++ err = -ENOMEM;
++ goto out_release_res;
++ }
++
++ switch (restype) {
++ case IORESOURCE_IO:
++ parent = &ioport_resource;
++ err = gen_pci_calc_io_offset(dev, &range, res, &offset);
++ break;
++ case IORESOURCE_MEM:
++ parent = &iomem_resource;
++ err = gen_pci_calc_mem_offset(dev, &range, res, &offset);
++ res_valid |= !(res->flags & IORESOURCE_PREFETCH || err);
++ break;
++ default:
++ err = -EINVAL;
++ continue;
++ }
++
++ if (err) {
++ dev_warn(dev,
++ "error %d: failed to add resource [type 0x%x, %lld bytes]\n",
++ err, restype, range.size);
++ continue;
++ }
++
++ err = request_resource(parent, res);
++ if (err)
++ goto out_release_res;
++
++ pci_add_resource_offset(&pci->resources, res, offset);
++ }
++
++ if (!res_valid) {
++ dev_err(dev, "non-prefetchable memory resource required\n");
++ err = -EINVAL;
++ goto out_release_res;
++ }
++
++ return 0;
++
++out_release_res:
++ gen_pci_release_of_pci_ranges(pci);
++ return err;
++}
++
++static int gen_pci_parse_map_cfg_windows(struct gen_pci *pci)
++{
++ int err;
++ u8 bus_max;
++ resource_size_t busn;
++ struct resource *bus_range;
++ struct device *dev = pci->host.dev.parent;
++ struct device_node *np = dev->of_node;
++
++ if (of_pci_parse_bus_range(np, &pci->cfg.bus_range))
++ pci->cfg.bus_range = (struct resource) {
++ .name = np->name,
++ .start = 0,
++ .end = 0xff,
++ .flags = IORESOURCE_BUS,
++ };
++
++ err = of_address_to_resource(np, 0, &pci->cfg.res);
++ if (err) {
++ dev_err(dev, "missing \"reg\" property\n");
++ return err;
++ }
++
++ pci->cfg.win = devm_kcalloc(dev, resource_size(&pci->cfg.bus_range),
++ sizeof(*pci->cfg.win), GFP_KERNEL);
++ if (!pci->cfg.win)
++ return -ENOMEM;
++
++ /* Limit the bus-range to fit within reg */
++ bus_max = pci->cfg.bus_range.start +
++ (resource_size(&pci->cfg.res) >> pci->cfg.ops->bus_shift) - 1;
++ pci->cfg.bus_range.end = min_t(resource_size_t, pci->cfg.bus_range.end,
++ bus_max);
++
++ /* Map our Configuration Space windows */
++ if (!devm_request_mem_region(dev, pci->cfg.res.start,
++ resource_size(&pci->cfg.res),
++ "Configuration Space"))
++ return -ENOMEM;
++
++ bus_range = &pci->cfg.bus_range;
++ for (busn = bus_range->start; busn <= bus_range->end; ++busn) {
++ u32 idx = busn - bus_range->start;
++ u32 sz = 1 << pci->cfg.ops->bus_shift;
++
++ pci->cfg.win[idx] = devm_ioremap(dev,
++ pci->cfg.res.start + busn * sz,
++ sz);
++ if (!pci->cfg.win[idx])
++ return -ENOMEM;
++ }
++
++ /* Register bus resource */
++ pci_add_resource(&pci->resources, bus_range);
++ return 0;
++}
++
++static int gen_pci_setup(int nr, struct pci_sys_data *sys)
++{
++ struct gen_pci *pci = sys->private_data;
++ list_splice_init(&pci->resources, &sys->resources);
++ return 1;
++}
++
++static int gen_pci_probe(struct platform_device *pdev)
++{
++ int err;
++ const char *type;
++ const struct of_device_id *of_id;
++ const int *prop;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct gen_pci *pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
++ struct hw_pci hw = {
++ .nr_controllers = 1,
++ .private_data = (void **)&pci,
++ .setup = gen_pci_setup,
++ .map_irq = of_irq_parse_and_map_pci,
++ .ops = &gen_pci_ops,
++ };
++
++ if (!pci)
++ return -ENOMEM;
++
++ type = of_get_property(np, "device_type", NULL);
++ if (!type || strcmp(type, "pci")) {
++ dev_err(dev, "invalid \"device_type\" %s\n", type);
++ return -EINVAL;
++ }
++
++ prop = of_get_property(of_chosen, "linux,pci-probe-only", NULL);
++ if (prop) {
++ if (*prop)
++ pci_add_flags(PCI_PROBE_ONLY);
++ else
++ pci_clear_flags(PCI_PROBE_ONLY);
++ }
++
++ of_id = of_match_node(gen_pci_of_match, np);
++ pci->cfg.ops = of_id->data;
++ pci->host.dev.parent = dev;
++ INIT_LIST_HEAD(&pci->host.windows);
++ INIT_LIST_HEAD(&pci->resources);
++
++ /* Parse our PCI ranges and request their resources */
++ err = gen_pci_parse_request_of_pci_ranges(pci);
++ if (err)
++ return err;
++
++ /* Parse and map our Configuration Space windows */
++ err = gen_pci_parse_map_cfg_windows(pci);
++ if (err) {
++ gen_pci_release_of_pci_ranges(pci);
++ return err;
++ }
++
++ pci_common_init_dev(dev, &hw);
++ return 0;
++}
++
++static struct platform_driver gen_pci_driver = {
++ .driver = {
++ .name = "pci-host-generic",
++ .owner = THIS_MODULE,
++ .of_match_table = gen_pci_of_match,
++ },
++ .probe = gen_pci_probe,
++};
++module_platform_driver(gen_pci_driver);
++
++MODULE_DESCRIPTION("Generic PCI host driver");
++MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
++MODULE_LICENSE("GPLv2");
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pci-imx6.c linux-3.14.72/drivers/pci/host/pci-imx6.c
+--- linux-3.14.72.orig/drivers/pci/host/pci-imx6.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pci/host/pci-imx6.c 2016-06-19 22:31:16.726729837 +0200
+@@ -1,6 +1,7 @@
+ /*
+ * PCIe host controller driver for Freescale i.MX6 SoCs
+ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2013 Kosagi
+ * http://www.kosagi.com
+ *
+@@ -14,33 +15,46 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/gpio.h>
++#include <linux/interrupt.h>
+ #include <linux/kernel.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+ #include <linux/module.h>
+ #include <linux/of_gpio.h>
++#include <linux/of_address.h>
+ #include <linux/pci.h>
++#include <linux/pci_regs.h>
+ #include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+-#include <linux/resource.h>
+-#include <linux/signal.h>
+-#include <linux/types.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/regulator/consumer.h>
+
+ #include "pcie-designware.h"
+
+ #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
+
++/*
++ * The default value of the reserved ddr memory
++ * used to verify EP/RC memory space access operations.
++ * The layout of the 1G ddr on SD boards
++ * [others]0x1000_0000 ~ 0x4FFF_FFFF
++ * [imx6sx]0x8000_0000 ~ 0xBFFF_FFFF
++ *
++ */
++static u32 ddr_test_region = 0, test_region_size = SZ_2M;
++
+ struct imx6_pcie {
+ int reset_gpio;
+ int power_on_gpio;
+- int wake_up_gpio;
+- int disable_gpio;
+- struct clk *lvds_gate;
+- struct clk *sata_ref_100m;
+- struct clk *pcie_ref_125m;
+- struct clk *pcie_axi;
++ struct clk *pcie_bus;
++ struct clk *pcie_phy;
++ struct clk *pcie_inbound_axi;
++ struct clk *ref_100m;
++ struct clk *pcie;
+ struct pcie_port pp;
+ struct regmap *iomuxc_gpr;
++ struct regulator *pcie_phy_regulator;
+ void __iomem *mem_base;
+ };
+
+@@ -52,6 +66,9 @@
+
+ /* PCIe Port Logic registers (memory-mapped) */
+ #define PL_OFFSET 0x700
++#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
++#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
++#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
+ #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
+ #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
+ #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
+@@ -77,6 +94,14 @@
+ #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
+ #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
+
++static inline bool is_imx6sx_pcie(struct imx6_pcie *imx6_pcie)
++{
++ struct pcie_port *pp = &imx6_pcie->pp;
++ struct device_node *np = pp->dev->of_node;
++
++ return of_device_is_compatible(np, "fsl,imx6sx-pcie");
++}
++
+ static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
+ {
+ u32 val;
+@@ -217,11 +242,53 @@
+ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
+ {
+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++ u32 val, gpr1, gpr12;
++
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6SX_GPR12_PCIE_TEST_PD,
++ IMX6SX_GPR12_PCIE_TEST_PD);
++ /* Force PCIe PHY reset */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
++ IMX6SX_GPR5_PCIE_BTNRST,
++ IMX6SX_GPR5_PCIE_BTNRST);
++ } else {
++ /*
++ * If the bootloader already enabled the link we need
++ * some special handling to get the core back into a
++ * state where it is safe to touch it for configuration.
++ * As there is no dedicated reset signal wired up for
++ * MX6QDL, we need to manually force LTSSM into "detect"
++ * state before completely disabling LTSSM, which is a
++ * prerequisite for core configuration.
++ *
++ * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we
++ * have a strong indication that the bootloader
++ * activated the link.
++ */
++ regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
++ regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
++
++ if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
++ (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
++ val = readl(pp->dbi_base + PCIE_PL_PFLR);
++ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
++ val |= PCIE_PL_PFLR_FORCE_LINK;
++ writel(val, pp->dbi_base + PCIE_PL_PFLR);
++
++ usleep_range(30, 50);
++
++ /* clear GPR12.10: APP_LTSSM_ENABLE - hold LTSSM in detect state */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_PCIE_CTL_2, 0);
++ }
+
+- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+- IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
+- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+- IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_PCIE_TEST_PD,
++ IMX6Q_GPR1_PCIE_TEST_PD);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
++ }
+
+ return 0;
+ }
+@@ -234,69 +301,130 @@
+ if (gpio_is_valid(imx6_pcie->power_on_gpio))
+ gpio_set_value(imx6_pcie->power_on_gpio, 1);
+
+- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+- IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
+- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
+- IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
+-
+- ret = clk_prepare_enable(imx6_pcie->sata_ref_100m);
++ request_bus_freq(BUS_FREQ_HIGH);
++ ret = clk_prepare_enable(imx6_pcie->pcie_phy);
+ if (ret) {
+- dev_err(pp->dev, "unable to enable sata_ref_100m\n");
+- goto err_sata_ref;
++ dev_err(pp->dev, "unable to enable pcie_phy clock\n");
++ goto err_pcie_phy;
+ }
+
+- ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m);
+- if (ret) {
+- dev_err(pp->dev, "unable to enable pcie_ref_125m\n");
+- goto err_pcie_ref;
++ if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
++ && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS)) {
++ ret = clk_prepare_enable(imx6_pcie->pcie_bus);
++ if (ret) {
++ dev_err(pp->dev, "unable to enable pcie_bus clock\n");
++ goto err_pcie_bus;
++ }
+ }
+
+- ret = clk_prepare_enable(imx6_pcie->lvds_gate);
++ ret = clk_prepare_enable(imx6_pcie->pcie);
+ if (ret) {
+- dev_err(pp->dev, "unable to enable lvds_gate\n");
+- goto err_lvds_gate;
++ dev_err(pp->dev, "unable to enable pcie clock\n");
++ goto err_pcie;
+ }
+
+- ret = clk_prepare_enable(imx6_pcie->pcie_axi);
+- if (ret) {
+- dev_err(pp->dev, "unable to enable pcie_axi\n");
+- goto err_pcie_axi;
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
++ if (ret) {
++ dev_err(pp->dev, "unable to enable pcie clock\n");
++ goto err_inbound_axi;
++ }
++
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6SX_GPR12_PCIE_TEST_PD, 0);
++ } else {
++ /* power up core phy and enable ref clock */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_PCIE_TEST_PD, 0);
++
++ /* sata_ref is not used by pcie on imx6sx */
++ ret = clk_prepare_enable(imx6_pcie->ref_100m);
++ if (ret) {
++ dev_err(pp->dev, "unable to enable ref_100m\n");
++ goto err_inbound_axi;
++ }
++ /*
++ * the async reset input need ref clock to sync internally,
++ * when the ref clock comes after reset, internal synced
++ * reset time is too short , cannot meet the requirement.
++ * add one ~10us delay here.
++ */
++ udelay(10);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
++ IMX6Q_GPR1_PCIE_REF_CLK_EN,
++ IMX6Q_GPR1_PCIE_REF_CLK_EN);
+ }
+
+ /* allow the clocks to stabilize */
+- usleep_range(200, 500);
++ udelay(200);
+
+ /* Some boards don't have PCIe reset GPIO. */
+ if (gpio_is_valid(imx6_pcie->reset_gpio)) {
+- gpio_set_value(imx6_pcie->reset_gpio, 0);
+- msleep(100);
+- gpio_set_value(imx6_pcie->reset_gpio, 1);
++ gpio_set_value_cansleep(imx6_pcie->reset_gpio, 0);
++ mdelay(100);
++ gpio_set_value_cansleep(imx6_pcie->reset_gpio, 1);
+ }
++
++ /*
++ * Release the PCIe PHY reset here, that we have set in
++ * imx6_pcie_init_phy() now
++ */
++ if (is_imx6sx_pcie(imx6_pcie))
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
++ IMX6SX_GPR5_PCIE_BTNRST, 0);
++
+ return 0;
+
+-err_pcie_axi:
+- clk_disable_unprepare(imx6_pcie->lvds_gate);
+-err_lvds_gate:
+- clk_disable_unprepare(imx6_pcie->pcie_ref_125m);
+-err_pcie_ref:
+- clk_disable_unprepare(imx6_pcie->sata_ref_100m);
+-err_sata_ref:
++err_inbound_axi:
++ clk_disable_unprepare(imx6_pcie->pcie);
++err_pcie:
++ if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
++ && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
++ clk_disable_unprepare(imx6_pcie->pcie_bus);
++err_pcie_bus:
++ clk_disable_unprepare(imx6_pcie->pcie_phy);
++err_pcie_phy:
+ return ret;
+
+ }
+
+-static void imx6_pcie_init_phy(struct pcie_port *pp)
++static int imx6_pcie_init_phy(struct pcie_port *pp)
+ {
+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
++ int ret;
++
++ /* Power up the separate domain available on i.MX6SX */
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ /* Force PCIe PHY reset */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
++ IMX6SX_GPR5_PCIE_BTNRST,
++ IMX6SX_GPR5_PCIE_BTNRST);
++
++ regulator_set_voltage(imx6_pcie->pcie_phy_regulator,
++ 1100000, 1100000);
++ ret = regulator_enable(imx6_pcie->pcie_phy_regulator);
++ if (ret) {
++ dev_err(pp->dev, "failed to enable pcie regulator.\n");
++ return ret;
++ }
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6SX_GPR12_RX_EQ_MASK, IMX6SX_GPR12_RX_EQ_2);
++ }
+
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+ IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
+
+ /* configure constant input signal to the pcie ctrl and phy */
++ if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS))
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_DEVICE_TYPE,
++ PCI_EXP_TYPE_ENDPOINT << 12);
++ else
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_DEVICE_TYPE,
++ PCI_EXP_TYPE_ROOT_PORT << 12);
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+- IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
+- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+- IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
++ IMX6Q_GPR12_LOS_LEVEL, IMX6Q_GPR12_LOS_LEVEL_9);
+
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
+@@ -308,6 +436,8 @@
+ IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
+ IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
++
++ return 0;
+ }
+
+ static int imx6_pcie_wait_for_link(struct pcie_port *pp)
+@@ -315,11 +445,11 @@
+ int count = 200;
+
+ while (!dw_pcie_link_up(pp)) {
+- usleep_range(100, 1000);
++ udelay(100);
+ if (--count)
+ continue;
+
+- dev_err(pp->dev, "phy link never came up\n");
++ dev_info(pp->dev, "phy link never came up\n");
+ dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
+@@ -329,6 +459,13 @@
+ return 0;
+ }
+
++static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
++{
++ struct pcie_port *pp = arg;
++
++ return dw_handle_msi_irq(pp);
++}
++
+ static int imx6_pcie_start_link(struct pcie_port *pp)
+ {
+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+@@ -347,11 +484,12 @@
+
+ /* Start LTSSM. */
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
+- IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
++ IMX6Q_GPR12_PCIE_CTL_2,
++ IMX6Q_GPR12_PCIE_CTL_2);
+
+ ret = imx6_pcie_wait_for_link(pp);
+ if (ret)
+- return ret;
++ goto out;
+
+ /* Allow Gen2 mode after the link is up. */
+ tmp = readl(pp->dbi_base + PCIE_RC_LCR);
+@@ -373,7 +511,7 @@
+ /* Test if the speed change finished. */
+ if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
+ break;
+- usleep_range(100, 1000);
++ udelay(100);
+ }
+
+ /* Make sure link training is finished as well! */
+@@ -382,8 +520,28 @@
+ else
+ ret = -EINVAL;
+
++out:
+ if (ret) {
+- dev_err(pp->dev, "Failed to bring link up!\n");
++ dev_info(pp->dev, "Failed to bring link up!\n");
++ if (IS_ENABLED(CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE)) {
++ clk_disable_unprepare(imx6_pcie->pcie);
++ if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
++ && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
++ clk_disable_unprepare(imx6_pcie->pcie_bus);
++ clk_disable_unprepare(imx6_pcie->pcie_phy);
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ /* Disable clks and power down PCIe PHY */
++ clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
++
++ /*
++ * Power down PCIe PHY.
++ */
++ regulator_disable(imx6_pcie->pcie_phy_regulator);
++ } else {
++ clk_disable_unprepare(imx6_pcie->ref_100m);
++ }
++ }
++ release_bus_freq(BUS_FREQ_HIGH);
+ } else {
+ tmp = readl(pp->dbi_base + 0x80);
+ dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
+@@ -392,17 +550,33 @@
+ return ret;
+ }
+
+-static void imx6_pcie_host_init(struct pcie_port *pp)
++static int imx6_pcie_host_init(struct pcie_port *pp)
+ {
++ int ret;
++
++ /* enable disp_mix power domain */
++ pm_runtime_get_sync(pp->dev);
++
+ imx6_pcie_assert_core_reset(pp);
+
+- imx6_pcie_init_phy(pp);
++ ret = imx6_pcie_init_phy(pp);
++ if (ret < 0)
++ return ret;
+
+- imx6_pcie_deassert_core_reset(pp);
++ ret = imx6_pcie_deassert_core_reset(pp);
++ if (ret < 0)
++ return ret;
+
+ dw_pcie_setup_rc(pp);
+
+- imx6_pcie_start_link(pp);
++ ret = imx6_pcie_start_link(pp);
++ if (ret < 0)
++ return ret;
++
++ if (IS_ENABLED(CONFIG_PCI_MSI))
++ dw_pcie_msi_init(pp);
++
++ return 0;
+ }
+
+ static void imx6_pcie_reset_phy(struct pcie_port *pp)
+@@ -414,7 +588,7 @@
+ PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+ pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
+
+- usleep_range(2000, 3000);
++ udelay(2000);
+
+ pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
+ temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
+@@ -425,7 +599,7 @@
+ static int imx6_pcie_link_up(struct pcie_port *pp)
+ {
+ u32 rc, debug_r0, rx_valid;
+- int count = 5;
++ int count = 500;
+
+ /*
+ * Test if the PHY reports that the link is up and also that the LTSSM
+@@ -456,7 +630,7 @@
+ * Wait a little bit, then re-check if the link finished
+ * the training.
+ */
+- usleep_range(1000, 2000);
++ udelay(10);
+ }
+ /*
+ * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
+@@ -474,7 +648,7 @@
+ if ((debug_r0 & 0x3f) != 0x0d)
+ return 0;
+
+- dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
++ dev_warn(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
+ dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
+
+ imx6_pcie_reset_phy(pp);
+@@ -487,30 +661,355 @@
+ .host_init = imx6_pcie_host_init,
+ };
+
+-static int imx6_add_pcie_port(struct pcie_port *pp,
++static int __init imx6_add_pcie_port(struct pcie_port *pp,
+ struct platform_device *pdev)
+ {
+ int ret;
+
+- pp->irq = platform_get_irq(pdev, 0);
+- if (!pp->irq) {
+- dev_err(&pdev->dev, "failed to get irq\n");
+- return -ENODEV;
++ if (IS_ENABLED(CONFIG_PCI_MSI)) {
++ pp->msi_irq = platform_get_irq_byname(pdev, "msi");
++ if (pp->msi_irq <= 0) {
++ dev_err(&pdev->dev, "failed to get MSI irq\n");
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, pp->msi_irq,
++ imx6_pcie_msi_handler,
++ IRQF_SHARED, "mx6-pcie-msi", pp);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request MSI irq\n");
++ return -ENODEV;
++ }
+ }
+
+ pp->root_bus_nr = -1;
+ pp->ops = &imx6_pcie_host_ops;
+
+- spin_lock_init(&pp->conf_lock);
+ ret = dw_pcie_host_init(pp);
+ if (ret) {
+- dev_err(&pdev->dev, "failed to initialize host\n");
++ dev_warn(&pdev->dev, "failed to initialize host\n");
+ return ret;
+ }
+
+ return 0;
+ }
+
++static ssize_t imx_pcie_bar0_addr_info(struct device *dev,
++ struct device_attribute *devattr, char *buf)
++{
++ struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
++ struct pcie_port *pp = &imx6_pcie->pp;
++
++ return sprintf(buf, "imx-pcie-bar0-addr-info start 0x%08x\n",
++ readl(pp->dbi_base + PCI_BASE_ADDRESS_0));
++}
++
++static ssize_t imx_pcie_bar0_addr_start(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ u32 bar_start;
++ struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
++ struct pcie_port *pp = &imx6_pcie->pp;
++
++ sscanf(buf, "%x\n", &bar_start);
++ writel(bar_start, pp->dbi_base + PCI_BASE_ADDRESS_0);
++
++ return count;
++}
++
++static void imx_pcie_regions_setup(struct device *dev)
++{
++ struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
++ struct pcie_port *pp = &imx6_pcie->pp;
++
++ if (is_imx6sx_pcie(imx6_pcie) && ddr_test_region == 0)
++ ddr_test_region = 0xb0000000;
++ else if (ddr_test_region == 0)
++ ddr_test_region = 0x40000000;
++
++ /*
++ * region2 outbound used to access rc/ep mem
++ * in imx6 pcie ep/rc validation system
++ */
++ writel(2, pp->dbi_base + 0x900);
++ writel(pp->mem_base, pp->dbi_base + 0x90c);
++ writel(0, pp->dbi_base + 0x910);
++ writel(pp->mem_base + test_region_size, pp->dbi_base + 0x914);
++
++ writel(ddr_test_region, pp->dbi_base + 0x918);
++ writel(0, pp->dbi_base + 0x91c);
++ writel(0, pp->dbi_base + 0x904);
++ writel(1 << 31, pp->dbi_base + 0x908);
++}
++
++static ssize_t imx_pcie_memw_info(struct device *dev,
++ struct device_attribute *devattr, char *buf)
++{
++ return sprintf(buf, "imx-pcie-rc-memw-info start 0x%08x, size 0x%08x\n",
++ ddr_test_region, test_region_size);
++}
++
++static ssize_t
++imx_pcie_memw_start(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ u32 memw_start;
++ struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
++
++ sscanf(buf, "%x\n", &memw_start);
++
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ if (memw_start < 0x80000000 || memw_start > 0xb0000000) {
++ dev_err(dev, "Invalid imx6sx sdb memory start addr.\n");
++ dev_info(dev, "e.x: echo 0xb1000000 > /sys/...");
++ return -1;
++ }
++ } else {
++ if (memw_start < 0x10000000 || memw_start > 0x40000000) {
++ dev_err(dev, "Invalid imx6q sd memory start addr.\n");
++ dev_info(dev, "e.x: echo 0xb1000000 > /sys/...");
++ return -1;
++ }
++ }
++
++ if (ddr_test_region != memw_start) {
++ ddr_test_region = memw_start;
++ imx_pcie_regions_setup(dev);
++ }
++
++ return count;
++}
++
++static ssize_t
++imx_pcie_memw_size(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ u32 memw_size;
++
++ sscanf(buf, "%x\n", &memw_size);
++
++ if ((memw_size > (SZ_16M - SZ_1M)) || (memw_size < SZ_64K)) {
++ dev_err(dev, "Invalid, should be [SZ_64K,SZ_16M - SZ_1MB].\n");
++ dev_info(dev, "For example: echo 0x800000 > /sys/...");
++ return -1;
++ }
++
++ if (test_region_size != memw_size) {
++ test_region_size = memw_size;
++ imx_pcie_regions_setup(dev);
++ }
++
++ return count;
++}
++
++static DEVICE_ATTR(memw_info, S_IRUGO, imx_pcie_memw_info, NULL);
++static DEVICE_ATTR(memw_start_set, S_IWUGO, NULL, imx_pcie_memw_start);
++static DEVICE_ATTR(memw_size_set, S_IWUGO, NULL, imx_pcie_memw_size);
++static DEVICE_ATTR(ep_bar0_addr, S_IRWXUGO, imx_pcie_bar0_addr_info,
++ imx_pcie_bar0_addr_start);
++
++static struct attribute *imx_pcie_attrs[] = {
++ /*
++ * The start address, and the limitation (64KB ~ (16MB - 1MB))
++ * of the ddr mem window reserved by RC, and used for EP to access.
++ * BTW, these attrs are only configured at EP side.
++ */
++ &dev_attr_memw_info.attr,
++ &dev_attr_memw_start_set.attr,
++ &dev_attr_memw_size_set.attr,
++ &dev_attr_ep_bar0_addr.attr,
++ NULL
++};
++
++static struct attribute_group imx_pcie_attrgroup = {
++ .attrs = imx_pcie_attrs,
++};
++
++static void imx6_pcie_setup_ep(struct pcie_port *pp)
++{
++ /* CMD reg:I/O space, MEM space, and Bus Master Enable */
++ writel(readl(pp->dbi_base + PCI_COMMAND)
++ | PCI_COMMAND_IO
++ | PCI_COMMAND_MEMORY
++ | PCI_COMMAND_MASTER,
++ pp->dbi_base + PCI_COMMAND);
++
++ /*
++ * configure the class_rev(emaluate one memory ram ep device),
++ * bar0 and bar1 of ep
++ */
++ writel(0xdeadbeaf, pp->dbi_base + PCI_VENDOR_ID);
++ writel(readl(pp->dbi_base + PCI_CLASS_REVISION)
++ | (PCI_CLASS_MEMORY_RAM << 16),
++ pp->dbi_base + PCI_CLASS_REVISION);
++ writel(0xdeadbeaf, pp->dbi_base
++ + PCI_SUBSYSTEM_VENDOR_ID);
++
++ /* 32bit none-prefetchable 8M bytes memory on bar0 */
++ writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_0);
++ writel(SZ_8M - 1, pp->dbi_base + (1 << 12)
++ + PCI_BASE_ADDRESS_0);
++
++ /* None used bar1 */
++ writel(0x0, pp->dbi_base + PCI_BASE_ADDRESS_1);
++ writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_1);
++
++ /* 4K bytes IO on bar2 */
++ writel(0x1, pp->dbi_base + PCI_BASE_ADDRESS_2);
++ writel(SZ_4K - 1, pp->dbi_base + (1 << 12) +
++ PCI_BASE_ADDRESS_2);
++
++ /*
++ * 32bit prefetchable 1M bytes memory on bar3
++ * FIXME BAR MASK3 is not changable, the size
++ * is fixed to 256 bytes.
++ */
++ writel(0x8, pp->dbi_base + PCI_BASE_ADDRESS_3);
++ writel(SZ_1M - 1, pp->dbi_base + (1 << 12)
++ + PCI_BASE_ADDRESS_3);
++
++ /*
++ * 64bit prefetchable 1M bytes memory on bar4-5.
++ * FIXME BAR4,5 are not enabled yet
++ */
++ writel(0xc, pp->dbi_base + PCI_BASE_ADDRESS_4);
++ writel(SZ_1M - 1, pp->dbi_base + (1 << 12)
++ + PCI_BASE_ADDRESS_4);
++ writel(0, pp->dbi_base + (1 << 12) + PCI_BASE_ADDRESS_5);
++}
++
++static int pci_imx_suspend_noirq(struct device *dev)
++{
++ struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
++ struct pcie_port *pp = &imx6_pcie->pp;
++
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ if (IS_ENABLED(CONFIG_PCI_MSI))
++ dw_pcie_msi_cfg_store(pp);
++
++ if (IS_ENABLED(CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE)) {
++ /* PM_TURN_OFF */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6SX_GPR12_PCIE_PM_TURN_OFF,
++ IMX6SX_GPR12_PCIE_PM_TURN_OFF);
++ udelay(10);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
++ /* Disable clks and power down PCIe PHY */
++ clk_disable_unprepare(imx6_pcie->pcie);
++ if (!IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)
++ && !IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
++ clk_disable_unprepare(imx6_pcie->pcie_bus);
++ clk_disable_unprepare(imx6_pcie->pcie_phy);
++ clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
++ release_bus_freq(BUS_FREQ_HIGH);
++
++ /*
++ * Power down PCIe PHY.
++ */
++ regulator_disable(imx6_pcie->pcie_phy_regulator);
++ } else {
++ /* PM_TURN_OFF */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6SX_GPR12_PCIE_PM_TURN_OFF,
++ IMX6SX_GPR12_PCIE_PM_TURN_OFF);
++ udelay(10);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
++ clk_disable_unprepare(imx6_pcie->pcie);
++ clk_disable_unprepare(imx6_pcie->pcie_bus);
++ clk_disable_unprepare(imx6_pcie->pcie_phy);
++ clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
++ release_bus_freq(BUS_FREQ_HIGH);
++ }
++ } else {
++ /*
++ * L2 can exit by 'reset' or Inband beacon (from remote EP)
++ * toggling phy_powerdown has same effect as 'inband beacon'
++ * So, toggle bit18 of GPR1, used as a workaround of errata
++ * "PCIe PCIe does not support L2 Power Down"
++ */
++ imx6_pcie_assert_core_reset(pp);
++ }
++
++ return 0;
++}
++
++static int pci_imx_resume_noirq(struct device *dev)
++{
++ int ret = 0;
++ struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
++ struct pcie_port *pp = &imx6_pcie->pp;
++
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ if (IS_ENABLED(CONFIG_PCI_IMX6SX_EXTREMELY_PWR_SAVE)) {
++ imx6_pcie_assert_core_reset(pp);
++
++ ret = imx6_pcie_init_phy(pp);
++ if (ret < 0)
++ return ret;
++
++ ret = imx6_pcie_deassert_core_reset(pp);
++ if (ret < 0)
++ return ret;
++
++ if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS))
++ imx6_pcie_setup_ep(pp);
++ else
++ dw_pcie_setup_rc(pp);
++
++ if (IS_ENABLED(CONFIG_PCI_MSI))
++ dw_pcie_msi_cfg_restore(pp);
++
++ /* Start LTSSM. */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_PCIE_CTL_2,
++ IMX6Q_GPR12_PCIE_CTL_2);
++ } else {
++ request_bus_freq(BUS_FREQ_HIGH);
++ clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
++ clk_prepare_enable(imx6_pcie->pcie_bus);
++ clk_prepare_enable(imx6_pcie->pcie_phy);
++ clk_prepare_enable(imx6_pcie->pcie);
++
++ /* Reset iMX6SX PCIe */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
++ IMX6SX_GPR5_PCIE_PERST,
++ IMX6SX_GPR5_PCIE_PERST);
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
++ IMX6SX_GPR5_PCIE_PERST, 0);
++ /*
++ * controller maybe turn off, re-configure again
++ */
++ dw_pcie_setup_rc(pp);
++
++ if (IS_ENABLED(CONFIG_PCI_MSI))
++ dw_pcie_msi_cfg_restore(pp);
++ }
++ } else {
++ /*
++ * L2 can exit by 'reset' or Inband beacon (from remote EP)
++ * toggling phy_powerdown has same effect as 'inband beacon'
++ * So, toggle bit18 of GPR1, used as a workaround of errata
++ * "PCIe PCIe does not support L2 Power Down"
++ */
++ ret = imx6_pcie_deassert_core_reset(pp);
++ if (ret < 0)
++ return ret;
++ }
++
++ return 0;
++}
++
++static const struct dev_pm_ops pci_imx_pm_ops = {
++ .suspend_noirq = pci_imx_suspend_noirq,
++ .resume_noirq = pci_imx_resume_noirq,
++ .freeze_noirq = pci_imx_suspend_noirq,
++ .thaw_noirq = pci_imx_resume_noirq,
++ .poweroff_noirq = pci_imx_suspend_noirq,
++ .restore_noirq = pci_imx_resume_noirq,
++};
++
+ static int __init imx6_pcie_probe(struct platform_device *pdev)
+ {
+ struct imx6_pcie *imx6_pcie;
+@@ -526,6 +1025,13 @@
+ pp = &imx6_pcie->pp;
+ pp->dev = &pdev->dev;
+
++ if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
++ /* add attributes for device */
++ ret = sysfs_create_group(&pdev->dev.kobj, &imx_pcie_attrgroup);
++ if (ret)
++ return -EINVAL;
++ }
++
+ /* Added for PCI abort handling */
+ hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
+ "imprecise external abort");
+@@ -558,77 +1064,223 @@
+ }
+ }
+
+- imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0);
+- if (gpio_is_valid(imx6_pcie->wake_up_gpio)) {
+- ret = devm_gpio_request_one(&pdev->dev,
+- imx6_pcie->wake_up_gpio,
+- GPIOF_IN,
+- "PCIe wake up");
+- if (ret) {
+- dev_err(&pdev->dev, "unable to get wake-up gpio\n");
+- return ret;
+- }
+- }
+-
+- imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0);
+- if (gpio_is_valid(imx6_pcie->disable_gpio)) {
+- ret = devm_gpio_request_one(&pdev->dev,
+- imx6_pcie->disable_gpio,
+- GPIOF_OUT_INIT_HIGH,
+- "PCIe disable endpoint");
+- if (ret) {
+- dev_err(&pdev->dev, "unable to get disable-ep gpio\n");
+- return ret;
+- }
+- }
+-
+ /* Fetch clocks */
+- imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate");
+- if (IS_ERR(imx6_pcie->lvds_gate)) {
++ imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
++ if (IS_ERR(imx6_pcie->pcie_phy)) {
+ dev_err(&pdev->dev,
+- "lvds_gate clock select missing or invalid\n");
+- return PTR_ERR(imx6_pcie->lvds_gate);
++ "pcie_phy clock source missing or invalid\n");
++ return PTR_ERR(imx6_pcie->pcie_phy);
+ }
+
+- imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m");
+- if (IS_ERR(imx6_pcie->sata_ref_100m)) {
++ imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
++ if (IS_ERR(imx6_pcie->pcie_bus)) {
+ dev_err(&pdev->dev,
+- "sata_ref_100m clock source missing or invalid\n");
+- return PTR_ERR(imx6_pcie->sata_ref_100m);
++ "pcie_bus clock source missing or invalid\n");
++ return PTR_ERR(imx6_pcie->pcie_bus);
+ }
+
+- imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m");
+- if (IS_ERR(imx6_pcie->pcie_ref_125m)) {
++ imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
++ if (IS_ERR(imx6_pcie->pcie)) {
+ dev_err(&pdev->dev,
+- "pcie_ref_125m clock source missing or invalid\n");
+- return PTR_ERR(imx6_pcie->pcie_ref_125m);
++ "pcie clock source missing or invalid\n");
++ return PTR_ERR(imx6_pcie->pcie);
+ }
+
+- imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi");
+- if (IS_ERR(imx6_pcie->pcie_axi)) {
+- dev_err(&pdev->dev,
+- "pcie_axi clock source missing or invalid\n");
+- return PTR_ERR(imx6_pcie->pcie_axi);
+- }
++ if (is_imx6sx_pcie(imx6_pcie)) {
++ imx6_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev,
++ "pcie_inbound_axi");
++ if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
++ dev_err(&pdev->dev,
++ "pcie clock source missing or invalid\n");
++ return PTR_ERR(imx6_pcie->pcie_inbound_axi);
++ }
++
++ imx6_pcie->pcie_phy_regulator = devm_regulator_get(pp->dev,
++ "pcie-phy");
++
++ imx6_pcie->iomuxc_gpr =
++ syscon_regmap_lookup_by_compatible
++ ("fsl,imx6sx-iomuxc-gpr");
++ } else {
++ /* sata_ref is not used by pcie on imx6sx */
++ imx6_pcie->ref_100m = devm_clk_get(&pdev->dev, "ref_100m");
++ if (IS_ERR(imx6_pcie->ref_100m)) {
++ dev_err(&pdev->dev,
++ "ref_100m clock source missing or invalid\n");
++ return PTR_ERR(imx6_pcie->ref_100m);
++ }
+
+- /* Grab GPR config register range */
+- imx6_pcie->iomuxc_gpr =
+- syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
++ imx6_pcie->iomuxc_gpr =
++ syscon_regmap_lookup_by_compatible
++ ("fsl,imx6q-iomuxc-gpr");
++ }
+ if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
+ dev_err(&pdev->dev, "unable to find iomuxc registers\n");
+ return PTR_ERR(imx6_pcie->iomuxc_gpr);
+ }
+
+- ret = imx6_add_pcie_port(pp, pdev);
+- if (ret < 0)
+- return ret;
++ if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) {
++ int i;
++ void *test_reg1, *test_reg2;
++ void __iomem *pcie_arb_base_addr;
++ struct timeval tv1, tv2, tv3;
++ u32 tv_count1, tv_count2;
++ struct device_node *np = pp->dev->of_node;
++ struct of_pci_range range;
++ struct of_pci_range_parser parser;
++ unsigned long restype;
++
++ if (of_pci_range_parser_init(&parser, np)) {
++ dev_err(pp->dev, "missing ranges property\n");
++ return -EINVAL;
++ }
++
++ /* Get the memory ranges from DT */
++ for_each_of_pci_range(&parser, &range) {
++ restype = range.flags & IORESOURCE_TYPE_BITS;
++ if (restype == IORESOURCE_MEM) {
++ of_pci_range_to_resource(&range,
++ np, &pp->mem);
++ pp->mem.name = "MEM";
++ }
++ }
++
++ pp->mem_base = pp->mem.start;
++
++ imx6_pcie_assert_core_reset(pp);
++ ret = imx6_pcie_init_phy(pp);
++ ret |= imx6_pcie_deassert_core_reset(pp);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "unable to init pcie ep.\n");
++ return ret;
++ }
++
++ /*
++ * iMX6SX PCIe has the stand-alone power domain.
++ * refer to the initialization for iMX6SX PCIe,
++ * release the PCIe PHY reset here,
++ * before LTSSM enable is set
++ * .
++ */
++ if (is_imx6sx_pcie(imx6_pcie))
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
++ BIT(19), 0 << 19);
++
++ /* assert LTSSM enable */
++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
++ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
++
++ dev_info(&pdev->dev, "PCIe EP: waiting for link up...\n");
++
++ platform_set_drvdata(pdev, imx6_pcie);
++ /* link is indicated by the bit4 of DB_R1 register */
++ do {
++ usleep_range(10, 20);
++ } while ((readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & 0x10) == 0);
++
++ imx6_pcie_setup_ep(pp);
++
++ imx_pcie_regions_setup(&pdev->dev);
++
++ /* self io test */
++ test_reg1 = devm_kzalloc(&pdev->dev,
++ test_region_size, GFP_KERNEL);
++ if (!test_reg1) {
++ pr_err("pcie ep: can't alloc the test reg1.\n");
++ ret = PTR_ERR(test_reg1);
++ goto err;
++ }
++
++ test_reg2 = devm_kzalloc(&pdev->dev,
++ test_region_size, GFP_KERNEL);
++ if (!test_reg2) {
++ pr_err("pcie ep: can't alloc the test reg2.\n");
++ ret = PTR_ERR(test_reg1);
++ goto err;
++ }
++
++ pcie_arb_base_addr = ioremap_cache(pp->mem_base,
++ test_region_size);
++
++ if (!pcie_arb_base_addr) {
++ pr_err("error with ioremap in ep selftest\n");
++ ret = PTR_ERR(pcie_arb_base_addr);
++ goto err;
++ }
++
++ for (i = 0; i < test_region_size; i = i + 4) {
++ writel(0xE6600D00 + i, test_reg1 + i);
++ writel(0xDEADBEAF, test_reg2 + i);
++ }
++
++ /* PCIe EP start the data transfer after link up */
++ pr_info("pcie ep: Starting data transfer...\n");
++ do_gettimeofday(&tv1);
++
++ memcpy((unsigned long *)pcie_arb_base_addr,
++ (unsigned long *)test_reg1,
++ test_region_size);
++
++ do_gettimeofday(&tv2);
++
++ memcpy((unsigned long *)test_reg2,
++ (unsigned long *)pcie_arb_base_addr,
++ test_region_size);
++
++ do_gettimeofday(&tv3);
++
++ if (memcmp(test_reg2, test_reg1, test_region_size) == 0) {
++ tv_count1 = (tv2.tv_sec - tv1.tv_sec)
++ * USEC_PER_SEC
++ + tv2.tv_usec - tv1.tv_usec;
++ tv_count2 = (tv3.tv_sec - tv2.tv_sec)
++ * USEC_PER_SEC
++ + tv3.tv_usec - tv2.tv_usec;
++
++ pr_info("pcie ep: Data transfer is successful."
++ " tv_count1 %dus,"
++ " tv_count2 %dus.\n",
++ tv_count1, tv_count2);
++ pr_info("pcie ep: Data write speed:%ldMB/s.\n",
++ ((test_region_size/1024)
++ * MSEC_PER_SEC)
++ /(tv_count1));
++ pr_info("pcie ep: Data read speed:%ldMB/s.\n",
++ ((test_region_size/1024)
++ * MSEC_PER_SEC)
++ /(tv_count2));
++ } else {
++ pr_info("pcie ep: Data transfer is failed.\n");
++ } /* end of self io test. */
++ } else {
++ ret = imx6_add_pcie_port(pp, pdev);
++ if (ret < 0)
++ goto err;
++
++ platform_set_drvdata(pdev, imx6_pcie);
++
++ if (IS_ENABLED(CONFIG_RC_MODE_IN_EP_RC_SYS))
++ imx_pcie_regions_setup(&pdev->dev);
++ }
+
+- platform_set_drvdata(pdev, imx6_pcie);
+ return 0;
++err:
++ /* bring down link, so bootloader gets clean state in case of reboot */
++ imx6_pcie_assert_core_reset(&imx6_pcie->pp);
++ return ret;
++}
++
++static void imx6_pcie_shutdown(struct platform_device *pdev)
++{
++ struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
++
++ /* bring down link, so bootloader gets clean state in case of reboot */
++ imx6_pcie_assert_core_reset(&imx6_pcie->pp);
+ }
+
+ static const struct of_device_id imx6_pcie_of_match[] = {
+ { .compatible = "fsl,imx6q-pcie", },
++ { .compatible = "fsl,imx6sx-pcie", },
+ {},
+ };
+ MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
+@@ -638,7 +1290,9 @@
+ .name = "imx6q-pcie",
+ .owner = THIS_MODULE,
+ .of_match_table = imx6_pcie_of_match,
++ .pm = &pci_imx_pm_ops,
+ },
++ .shutdown = imx6_pcie_shutdown,
+ };
+
+ /* Freescale PCIe driver does not allow module unload */
+@@ -647,7 +1301,7 @@
+ {
+ return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
+ }
+-fs_initcall(imx6_pcie_init);
++module_init(imx6_pcie_init);
+
+ MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
+ MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
+diff -Nur linux-3.14.72.orig/drivers/pci/host/pci-imx6-ep-driver.c linux-3.14.72/drivers/pci/host/pci-imx6-ep-driver.c
+--- linux-3.14.72.orig/drivers/pci/host/pci-imx6-ep-driver.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/pci/host/pci-imx6-ep-driver.c 2016-06-19 22:11:55.305140007 +0200
+@@ -0,0 +1,167 @@
++/*
++ * PCIe endpoint skeleton driver for IMX6 SOCs
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/pci.h>
++#include <linux/pci-aspm.h>
++#include <linux/slab.h>
++#include <linux/dma-mapping.h>
++#include <linux/delay.h>
++#include <linux/sched.h>
++#include <linux/interrupt.h>
++
++#define DRV_DESCRIPTION "i.MX PCIE endpoint device driver"
++#define DRV_VERSION "version 0.1"
++#define DRV_NAME "imx_pcie_ep"
++
++struct imx_pcie_ep_priv {
++ struct pci_dev *pci_dev;
++ void __iomem *hw_base;
++};
++
++/**
++ * imx_pcie_ep_probe - Device Initialization Routine
++ * @pdev: PCI device information struct
++ * @id: entry in id_tbl
++ *
++ * Returns 0 on success, negative on failure
++ **/
++static int imx_pcie_ep_probe(struct pci_dev *pdev,
++ const struct pci_device_id *id)
++{
++ int ret = 0;
++ unsigned int msi_addr = 0;
++ struct device *dev = &pdev->dev;
++ struct imx_pcie_ep_priv *priv;
++
++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv) {
++ dev_err(dev, "can't alloc imx pcie priv\n");
++ return -ENOMEM;
++ }
++
++ priv->pci_dev = pdev;
++
++ if (pci_enable_device(pdev)) {
++ ret = -ENODEV;
++ goto out;
++ }
++ pci_set_master(pdev);
++
++ pci_set_drvdata(pdev, priv);
++
++ priv->hw_base = pci_iomap(pdev, 0, 0);
++ if (!priv->hw_base) {
++ ret = -ENODEV;
++ goto out;
++ }
++
++ pr_info("pci_resource_len = 0x%08llx\n",
++ (unsigned long long) pci_resource_len(pdev, 0));
++ pr_info("pci_resource_base = %p\n", priv->hw_base);
++
++ ret = pci_enable_msi(priv->pci_dev);
++ if (ret < 0) {
++ dev_err(dev, "can't enable msi\n");
++ return ret;
++ }
++
++ /*
++ * Force to use 0x01FF8000 on iMX6q SD board and 0x08FF8000
++ * on iMX6sx SDB board as the MSI address, to do the MSI demo
++ */
++ if (*(unsigned int *)priv->hw_base > 0x4FFFFFFF)
++ /* iMX6sx SDB board, DDR layout [0x8000_0000 ~ 0xBFFF_FFFF] */
++ msi_addr = 0x08FF8000;
++ else
++ /* iMX6q SD board, DDR layout [0x1000_0000 ~ 0x4FFF_FFFF] */
++ msi_addr = 0x01FF8000;
++ pr_info("pci_msi_addr = 0x%08x\n", msi_addr);
++ pci_bus_write_config_dword(pdev->bus, 0, 0x54, msi_addr);
++ pci_bus_write_config_dword(pdev->bus->parent, 0, 0x820, msi_addr);
++
++ /* configure rc's msi cap */
++ pci_bus_read_config_dword(pdev->bus->parent, 0, 0x50, &ret);
++ ret |= (PCI_MSI_FLAGS_ENABLE << 16);
++ pci_bus_write_config_dword(pdev->bus->parent, 0, 0x50, ret);
++ pci_bus_write_config_dword(pdev->bus->parent, 0, 0x828, 0x1);
++ pci_bus_write_config_dword(pdev->bus->parent, 0, 0x82C, 0xFFFFFFFE);
++
++ return 0;
++
++out:
++ return ret;
++}
++
++static void imx_pcie_ep_remove(struct pci_dev *pdev)
++{
++ struct imx_pcie_ep_priv *priv = pci_get_drvdata(pdev);
++
++ if (!priv)
++ return;
++ pr_info("***imx pcie ep driver unload***\n");
++}
++
++static struct pci_device_id imx_pcie_ep_ids[] = {
++ {
++ .class = PCI_CLASS_MEMORY_RAM << 8,
++ .class_mask = ~0,
++ .vendor = 0xbeaf,
++ .device = 0xdead,
++ .subvendor = PCI_ANY_ID,
++ .subdevice = PCI_ANY_ID,
++ },
++ { } /* terminate list */
++};
++MODULE_DEVICE_TABLE(pci, imx_pcie_ep_ids);
++
++static struct pci_driver imx_pcie_ep_driver = {
++ .name = DRV_NAME,
++ .id_table = imx_pcie_ep_ids,
++ .probe = imx_pcie_ep_probe,
++ .remove = imx_pcie_ep_remove,
++};
++
++static int __init imx_pcie_ep_init(void)
++{
++ int ret;
++ pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
++
++ ret = pci_register_driver(&imx_pcie_ep_driver);
++ if (ret)
++ pr_err("Unable to initialize PCI module\n");
++
++ return ret;
++}
++
++static void __exit imx_pcie_ep_exit(void)
++{
++ pci_unregister_driver(&imx_pcie_ep_driver);
++}
++
++module_exit(imx_pcie_ep_exit);
++module_init(imx_pcie_ep_init);
++
++MODULE_DESCRIPTION(DRV_DESCRIPTION);
++MODULE_VERSION(DRV_VERSION);
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("imx_pcie_ep");
+diff -Nur linux-3.14.72.orig/drivers/pci/quirks.c linux-3.14.72/drivers/pci/quirks.c
+--- linux-3.14.72.orig/drivers/pci/quirks.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pci/quirks.c 2016-06-19 22:11:55.305140007 +0200
+@@ -2800,6 +2800,14 @@
+ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
+ PCI_CLASS_NOT_DEFINED, 0, fixup_ti816x_class);
+
++static void fixup_tw6869_class(struct pci_dev* dev)
++{
++ dev_info(&dev->dev, "Setting PCI class for tw6868 PCIe device\n");
++ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
++}
++DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869,
++ PCI_CLASS_NOT_DEFINED, 0, fixup_tw6869_class);
++
+ /* Some PCIe devices do not work reliably with the claimed maximum
+ * payload size supported.
+ */
+diff -Nur linux-3.14.72.orig/drivers/phy/phy-omap-usb2.c linux-3.14.72/drivers/phy/phy-omap-usb2.c
+--- linux-3.14.72.orig/drivers/phy/phy-omap-usb2.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/phy/phy-omap-usb2.c 2016-06-19 22:11:55.309139744 +0200
+@@ -57,7 +57,7 @@
+
+ static int omap_usb_set_vbus(struct usb_otg *otg, bool enabled)
+ {
+- struct omap_usb *phy = phy_to_omapusb(otg->phy);
++ struct omap_usb *phy = phy_to_omapusb(otg->usb_phy);
+
+ if (!phy->comparator)
+ return -ENODEV;
+@@ -67,7 +67,7 @@
+
+ static int omap_usb_start_srp(struct usb_otg *otg)
+ {
+- struct omap_usb *phy = phy_to_omapusb(otg->phy);
++ struct omap_usb *phy = phy_to_omapusb(otg->usb_phy);
+
+ if (!phy->comparator)
+ return -ENODEV;
+@@ -77,11 +77,9 @@
+
+ static int omap_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
+ {
+- struct usb_phy *phy = otg->phy;
+-
+ otg->host = host;
+ if (!host)
+- phy->state = OTG_STATE_UNDEFINED;
++ otg->state = OTG_STATE_UNDEFINED;
+
+ return 0;
+ }
+@@ -89,11 +87,9 @@
+ static int omap_usb_set_peripheral(struct usb_otg *otg,
+ struct usb_gadget *gadget)
+ {
+- struct usb_phy *phy = otg->phy;
+-
+ otg->gadget = gadget;
+ if (!gadget)
+- phy->state = OTG_STATE_UNDEFINED;
++ otg->state = OTG_STATE_UNDEFINED;
+
+ return 0;
+ }
+@@ -198,7 +194,7 @@
+ otg->set_peripheral = omap_usb_set_peripheral;
+ otg->set_vbus = omap_usb_set_vbus;
+ otg->start_srp = omap_usb_start_srp;
+- otg->phy = &phy->phy;
++ otg->usb_phy = &phy->phy;
+
+ platform_set_drvdata(pdev, phy);
+ pm_runtime_enable(phy->dev);
+diff -Nur linux-3.14.72.orig/drivers/pinctrl/devicetree.c linux-3.14.72/drivers/pinctrl/devicetree.c
+--- linux-3.14.72.orig/drivers/pinctrl/devicetree.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pinctrl/devicetree.c 2016-06-19 22:11:55.309139744 +0200
+@@ -18,6 +18,7 @@
+
+ #include <linux/device.h>
+ #include <linux/of.h>
++#include <linux/of_gpio.h>
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/slab.h>
+
+@@ -172,6 +173,43 @@
+ return dt_remember_or_free_map(p, statename, NULL, map, 1);
+ }
+
++static int dt_gpio_assert_pinctrl(struct pinctrl *p)
++{
++ struct device_node *np = p->dev->of_node;
++ enum of_gpio_flags flags;
++ int gpio;
++ int index = 0;
++ int ret;
++
++ if (!of_find_property(np, "pinctrl-assert-gpios", NULL))
++ return 0; /* Missing the property, so nothing to be done */
++
++ for (;; index++) {
++ gpio = of_get_named_gpio_flags(np, "pinctrl-assert-gpios",
++ index, &flags);
++ if (gpio < 0)
++ break; /* End of the phandle list */
++
++ if (!gpio_is_valid(gpio))
++ return -EINVAL;
++
++ ret = devm_gpio_request_one(p->dev, gpio, GPIOF_OUT_INIT_LOW,
++ NULL);
++ if (ret < 0)
++ return ret;
++
++ if (flags & OF_GPIO_ACTIVE_LOW)
++ continue;
++
++ if (gpio_cansleep(gpio))
++ gpio_set_value_cansleep(gpio, 1);
++ else
++ gpio_set_value(gpio, 1);
++ }
++
++ return 0;
++}
++
+ int pinctrl_dt_to_map(struct pinctrl *p)
+ {
+ struct device_node *np = p->dev->of_node;
+@@ -190,6 +228,12 @@
+ return 0;
+ }
+
++ ret = dt_gpio_assert_pinctrl(p);
++ if (ret) {
++ dev_dbg(p->dev, "failed to assert pinctrl setting: %d\n", ret);
++ return ret;
++ }
++
+ /* We may store pointers to property names within the node */
+ of_node_get(np);
+
+diff -Nur linux-3.14.72.orig/drivers/pinctrl/Kconfig linux-3.14.72/drivers/pinctrl/Kconfig
+--- linux-3.14.72.orig/drivers/pinctrl/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pinctrl/Kconfig 2016-06-19 22:11:55.309139744 +0200
+@@ -185,6 +185,13 @@
+ help
+ Say Y here to enable the imx6sl pinctrl driver
+
++config PINCTRL_IMX6SX
++ bool "IMX6SX pinctrl driver"
++ depends on SOC_IMX6SX
++ select PINCTRL_IMX
++ help
++ Say Y here to enable the imx6sx pinctrl driver
++
+ config PINCTRL_VF610
+ bool "Freescale Vybrid VF610 pinctrl driver"
+ depends on SOC_VF610
+diff -Nur linux-3.14.72.orig/drivers/pinctrl/Makefile linux-3.14.72/drivers/pinctrl/Makefile
+--- linux-3.14.72.orig/drivers/pinctrl/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pinctrl/Makefile 2016-06-19 22:11:55.309139744 +0200
+@@ -32,6 +32,7 @@
+ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
+ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
+ obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
++obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
+ obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
+ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
+ obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
+diff -Nur linux-3.14.72.orig/drivers/pinctrl/pinctrl-imx6sx.c linux-3.14.72/drivers/pinctrl/pinctrl-imx6sx.c
+--- linux-3.14.72.orig/drivers/pinctrl/pinctrl-imx6sx.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/pinctrl/pinctrl-imx6sx.c 2016-06-19 22:11:55.309139744 +0200
+@@ -0,0 +1,407 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/pinctrl.h>
++
++#include "pinctrl-imx.h"
++
++enum imx6sx_pads {
++ MX6Sx_PAD_RESERVE0 = 0,
++ MX6Sx_PAD_RESERVE1 = 1,
++ MX6Sx_PAD_RESERVE2 = 2,
++ MX6Sx_PAD_RESERVE3 = 3,
++ MX6Sx_PAD_RESERVE4 = 4,
++ MX6SX_PAD_GPIO1_IO00 = 5,
++ MX6SX_PAD_GPIO1_IO01 = 6,
++ MX6SX_PAD_GPIO1_IO02 = 7,
++ MX6SX_PAD_GPIO1_IO03 = 8,
++ MX6SX_PAD_GPIO1_IO04 = 9,
++ MX6SX_PAD_GPIO1_IO05 = 10,
++ MX6SX_PAD_GPIO1_IO06 = 11,
++ MX6SX_PAD_GPIO1_IO07 = 12,
++ MX6SX_PAD_GPIO1_IO08 = 13,
++ MX6SX_PAD_GPIO1_IO09 = 14,
++ MX6SX_PAD_GPIO1_IO10 = 15,
++ MX6SX_PAD_GPIO1_IO11 = 16,
++ MX6SX_PAD_GPIO1_IO12 = 17,
++ MX6SX_PAD_GPIO1_IO13 = 18,
++ MX6SX_PAD_CSI_DATA00 = 19,
++ MX6SX_PAD_CSI_DATA01 = 20,
++ MX6SX_PAD_CSI_DATA02 = 21,
++ MX6SX_PAD_CSI_DATA03 = 22,
++ MX6SX_PAD_CSI_DATA04 = 23,
++ MX6SX_PAD_CSI_DATA05 = 24,
++ MX6SX_PAD_CSI_DATA06 = 25,
++ MX6SX_PAD_CSI_DATA07 = 26,
++ MX6SX_PAD_CSI_HSYNC = 27,
++ MX6SX_PAD_CSI_MCLK = 28,
++ MX6SX_PAD_CSI_PIXCLK = 29,
++ MX6SX_PAD_CSI_VSYNC = 30,
++ MX6SX_PAD_ENET1_COL = 31,
++ MX6SX_PAD_ENET1_CRS = 32,
++ MX6SX_PAD_ENET1_MDC = 33,
++ MX6SX_PAD_ENET1_MDIO = 34,
++ MX6SX_PAD_ENET1_RX_CLK = 35,
++ MX6SX_PAD_ENET1_TX_CLK = 36,
++ MX6SX_PAD_ENET2_COL = 37,
++ MX6SX_PAD_ENET2_CRS = 38,
++ MX6SX_PAD_ENET2_RX_CLK = 39,
++ MX6SX_PAD_ENET2_TX_CLK = 40,
++ MX6SX_PAD_KEY_COL0 = 41,
++ MX6SX_PAD_KEY_COL1 = 42,
++ MX6SX_PAD_KEY_COL2 = 43,
++ MX6SX_PAD_KEY_COL3 = 44,
++ MX6SX_PAD_KEY_COL4 = 45,
++ MX6SX_PAD_KEY_ROW0 = 46,
++ MX6SX_PAD_KEY_ROW1 = 47,
++ MX6SX_PAD_KEY_ROW2 = 48,
++ MX6SX_PAD_KEY_ROW3 = 49,
++ MX6SX_PAD_KEY_ROW4 = 50,
++ MX6SX_PAD_LCD1_CLK = 51,
++ MX6SX_PAD_LCD1_DATA00 = 52,
++ MX6SX_PAD_LCD1_DATA01 = 53,
++ MX6SX_PAD_LCD1_DATA02 = 54,
++ MX6SX_PAD_LCD1_DATA03 = 55,
++ MX6SX_PAD_LCD1_DATA04 = 56,
++ MX6SX_PAD_LCD1_DATA05 = 57,
++ MX6SX_PAD_LCD1_DATA06 = 58,
++ MX6SX_PAD_LCD1_DATA07 = 59,
++ MX6SX_PAD_LCD1_DATA08 = 60,
++ MX6SX_PAD_LCD1_DATA09 = 61,
++ MX6SX_PAD_LCD1_DATA10 = 62,
++ MX6SX_PAD_LCD1_DATA11 = 63,
++ MX6SX_PAD_LCD1_DATA12 = 64,
++ MX6SX_PAD_LCD1_DATA13 = 65,
++ MX6SX_PAD_LCD1_DATA14 = 66,
++ MX6SX_PAD_LCD1_DATA15 = 67,
++ MX6SX_PAD_LCD1_DATA16 = 68,
++ MX6SX_PAD_LCD1_DATA17 = 69,
++ MX6SX_PAD_LCD1_DATA18 = 70,
++ MX6SX_PAD_LCD1_DATA19 = 71,
++ MX6SX_PAD_LCD1_DATA20 = 72,
++ MX6SX_PAD_LCD1_DATA21 = 73,
++ MX6SX_PAD_LCD1_DATA22 = 74,
++ MX6SX_PAD_LCD1_DATA23 = 75,
++ MX6SX_PAD_LCD1_ENABLE = 76,
++ MX6SX_PAD_LCD1_HSYNC = 77,
++ MX6SX_PAD_LCD1_RESET = 78,
++ MX6SX_PAD_LCD1_VSYNC = 79,
++ MX6SX_PAD_NAND_ALE = 80,
++ MX6SX_PAD_NAND_CE0_B = 81,
++ MX6SX_PAD_NAND_CE1_B = 82,
++ MX6SX_PAD_NAND_CLE = 83,
++ MX6SX_PAD_NAND_DATA00 = 84 ,
++ MX6SX_PAD_NAND_DATA01 = 85,
++ MX6SX_PAD_NAND_DATA02 = 86,
++ MX6SX_PAD_NAND_DATA03 = 87,
++ MX6SX_PAD_NAND_DATA04 = 88,
++ MX6SX_PAD_NAND_DATA05 = 89,
++ MX6SX_PAD_NAND_DATA06 = 90,
++ MX6SX_PAD_NAND_DATA07 = 91,
++ MX6SX_PAD_NAND_RE_B = 92,
++ MX6SX_PAD_NAND_READY_B = 93,
++ MX6SX_PAD_NAND_WE_B = 94,
++ MX6SX_PAD_NAND_WP_B = 95,
++ MX6SX_PAD_QSPI1A_DATA0 = 96,
++ MX6SX_PAD_QSPI1A_DATA1 = 97,
++ MX6SX_PAD_QSPI1A_DATA2 = 98,
++ MX6SX_PAD_QSPI1A_DATA3 = 99,
++ MX6SX_PAD_QSPI1A_DQS = 100,
++ MX6SX_PAD_QSPI1A_SCLK = 101,
++ MX6SX_PAD_QSPI1A_SS0_B = 102,
++ MX6SX_PAD_QSPI1A_SS1_B = 103,
++ MX6SX_PAD_QSPI1B_DATA0 = 104,
++ MX6SX_PAD_QSPI1B_DATA1 = 105,
++ MX6SX_PAD_QSPI1B_DATA2 = 106,
++ MX6SX_PAD_QSPI1B_DATA3 = 107,
++ MX6SX_PAD_QSPI1B_DQS = 108,
++ MX6SX_PAD_QSPI1B_SCLK = 109,
++ MX6SX_PAD_QSPI1B_SS0_B = 110,
++ MX6SX_PAD_QSPI1B_SS1_B = 111,
++ MX6SX_PAD_RGMII1_RD0 = 112,
++ MX6SX_PAD_RGMII1_RD1 = 113,
++ MX6SX_PAD_RGMII1_RD2 = 114,
++ MX6SX_PAD_RGMII1_RD3 = 115,
++ MX6SX_PAD_RGMII1_RX_CTL = 116,
++ MX6SX_PAD_RGMII1_RXC = 117,
++ MX6SX_PAD_RGMII1_TD0 = 118,
++ MX6SX_PAD_RGMII1_TD1 = 119,
++ MX6SX_PAD_RGMII1_TD2 = 120,
++ MX6SX_PAD_RGMII1_TD3 = 121,
++ MX6SX_PAD_RGMII1_TX_CTL = 122,
++ MX6SX_PAD_RGMII1_TXC = 123,
++ MX6SX_PAD_RGMII2_RD0 = 124,
++ MX6SX_PAD_RGMII2_RD1 = 125,
++ MX6SX_PAD_RGMII2_RD2 = 126,
++ MX6SX_PAD_RGMII2_RD3 = 127,
++ MX6SX_PAD_RGMII2_RX_CTL = 128,
++ MX6SX_PAD_RGMII2_RXC = 129,
++ MX6SX_PAD_RGMII2_TD0 = 130,
++ MX6SX_PAD_RGMII2_TD1 = 131,
++ MX6SX_PAD_RGMII2_TD2 = 132,
++ MX6SX_PAD_RGMII2_TD3 = 133,
++ MX6SX_PAD_RGMII2_TX_CTL = 134,
++ MX6SX_PAD_RGMII2_TXC = 135,
++ MX6SX_PAD_SD1_CLK = 136,
++ MX6SX_PAD_SD1_CMD = 137,
++ MX6SX_PAD_SD1_DATA0 = 138,
++ MX6SX_PAD_SD1_DATA1 = 139,
++ MX6SX_PAD_SD1_DATA2 = 140,
++ MX6SX_PAD_SD1_DATA3 = 141,
++ MX6SX_PAD_SD2_CLK = 142,
++ MX6SX_PAD_SD2_CMD = 143,
++ MX6SX_PAD_SD2_DATA0 = 144,
++ MX6SX_PAD_SD2_DATA1 = 145,
++ MX6SX_PAD_SD2_DATA2 = 146,
++ MX6SX_PAD_SD2_DATA3 = 147,
++ MX6SX_PAD_SD3_CLK = 148,
++ MX6SX_PAD_SD3_CMD = 149,
++ MX6SX_PAD_SD3_DATA0 = 150,
++ MX6SX_PAD_SD3_DATA1 = 151,
++ MX6SX_PAD_SD3_DATA2 = 152,
++ MX6SX_PAD_SD3_DATA3 = 153,
++ MX6SX_PAD_SD3_DATA4 = 154,
++ MX6SX_PAD_SD3_DATA5 = 155,
++ MX6SX_PAD_SD3_DATA6 = 156,
++ MX6SX_PAD_SD3_DATA7 = 157,
++ MX6SX_PAD_SD4_CLK = 158,
++ MX6SX_PAD_SD4_CMD = 159,
++ MX6SX_PAD_SD4_DATA0 = 160,
++ MX6SX_PAD_SD4_DATA1 = 161,
++ MX6SX_PAD_SD4_DATA2 = 162,
++ MX6SX_PAD_SD4_DATA3 = 163,
++ MX6SX_PAD_SD4_DATA4 = 164,
++ MX6SX_PAD_SD4_DATA5 = 165,
++ MX6SX_PAD_SD4_DATA6 = 166,
++ MX6SX_PAD_SD4_DATA7 = 167,
++ MX6SX_PAD_SD4_RESET_B = 168,
++ MX6SX_PAD_USB_H_DATA = 169,
++ MX6SX_PAD_USB_H_STROBE = 170,
++};
++
++/* Pad names for the pinmux subsystem */
++static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
++ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
++ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
++ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
++ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
++ IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
++ IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
++ IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
++ IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
++ IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
++ IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
++ IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
++};
++
++static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
++ .pins = imx6sx_pinctrl_pads,
++ .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
++};
++
++static struct of_device_id imx6sx_pinctrl_of_match[] = {
++ { .compatible = "fsl,imx6sx-iomuxc", },
++ { /* sentinel */ }
++};
++
++static int imx6sx_pinctrl_probe(struct platform_device *pdev)
++{
++ return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
++}
++
++static struct platform_driver imx6sx_pinctrl_driver = {
++ .driver = {
++ .name = "imx6sx-pinctrl",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
++ },
++ .probe = imx6sx_pinctrl_probe,
++ .remove = imx_pinctrl_remove,
++};
++
++static int __init imx6sx_pinctrl_init(void)
++{
++ return platform_driver_register(&imx6sx_pinctrl_driver);
++}
++arch_initcall(imx6sx_pinctrl_init);
++
++static void __exit imx6sx_pinctrl_exit(void)
++{
++ platform_driver_unregister(&imx6sx_pinctrl_driver);
++}
++module_exit(imx6sx_pinctrl_exit);
++
++MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
++MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/power/imx6_usb_charger.c linux-3.14.72/drivers/power/imx6_usb_charger.c
+--- linux-3.14.72.orig/drivers/power/imx6_usb_charger.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/power/imx6_usb_charger.c 2016-06-19 22:11:55.309139744 +0200
+@@ -0,0 +1,287 @@
++/*
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/power/imx6_usb_charger.h>
++#include <linux/regmap.h>
++
++#define HW_ANADIG_USB1_CHRG_DETECT_SET (0x000001b4)
++#define HW_ANADIG_USB1_CHRG_DETECT_CLR (0x000001b8)
++
++#define BM_ANADIG_USB1_CHRG_DETECT_EN_B 0x00100000
++#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B 0x00080000
++#define BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT 0x00040000
++
++#define HW_ANADIG_USB1_VBUS_DET_STAT (0x000001c0)
++
++#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID 0x00000008
++
++#define HW_ANADIG_USB1_CHRG_DET_STAT (0x000001d0)
++
++#define BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE 0x00000004
++#define BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED 0x00000002
++#define BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT 0x00000001
++
++static char *imx6_usb_charger_supplied_to[] = {
++ "imx6_usb_charger",
++};
++
++static enum power_supply_property imx6_usb_charger_power_props[] = {
++ POWER_SUPPLY_PROP_PRESENT, /* Charger detected */
++ POWER_SUPPLY_PROP_ONLINE, /* VBUS online */
++ POWER_SUPPLY_PROP_CURRENT_MAX, /* Maximum current in mA */
++};
++
++static int imx6_usb_charger_get_property(struct power_supply *psy,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct usb_charger *charger =
++ container_of(psy, struct usb_charger, psy);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_PRESENT:
++ val->intval = charger->present;
++ break;
++ case POWER_SUPPLY_PROP_ONLINE:
++ val->intval = charger->online;
++ break;
++ case POWER_SUPPLY_PROP_CURRENT_MAX:
++ val->intval = charger->max_current;
++ break;
++ default:
++ return -EINVAL;
++ }
++ return 0;
++}
++
++static void disable_charger_detector(struct regmap *regmap)
++{
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_SET,
++ BM_ANADIG_USB1_CHRG_DETECT_EN_B |
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
++}
++
++/* Return value if the charger is present */
++static int imx6_usb_charger_detect(struct usb_charger *charger)
++{
++ struct regmap *regmap = charger->anatop;
++ u32 val;
++ int i, data_pin_contact_count = 0;
++
++ /* check if vbus is valid */
++ regmap_read(regmap, HW_ANADIG_USB1_VBUS_DET_STAT, &val);
++ if (!(val & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)) {
++ dev_err(charger->dev, "vbus is error\n");
++ return -EINVAL;
++ }
++
++ /* Enable charger detector */
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_CLR,
++ BM_ANADIG_USB1_CHRG_DETECT_EN_B);
++ /*
++ * - Do not check whether a charger is connected to the USB port
++ * - Check whether the USB plug has been in contact with each other
++ */
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_SET,
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT |
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
++
++ /* Check if plug is connected */
++ for (i = 0; i < 100; i = i + 1) {
++ regmap_read(regmap, HW_ANADIG_USB1_CHRG_DET_STAT, &val);
++ if (val & BM_ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT) {
++ if (data_pin_contact_count++ > 5)
++ /* Data pin makes contact */
++ break;
++ else
++ usleep_range(5000, 10000);
++ } else {
++ data_pin_contact_count = 0;
++ msleep(20);
++ }
++ }
++
++ if (i == 100) {
++ dev_err(charger->dev,
++ "VBUS is coming from a dedicated power supply.\n");
++ disable_charger_detector(regmap);
++ return -ENXIO;
++ }
++
++ /*
++ * - Do check whether a charger is connected to the USB port
++ * - Do not Check whether the USB plug has been in contact with
++ * each other
++ */
++ regmap_write(regmap, HW_ANADIG_USB1_CHRG_DETECT_CLR,
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CONTACT |
++ BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B);
++ msleep(100);
++
++ /* Check if it is a charger */
++ regmap_read(regmap, HW_ANADIG_USB1_CHRG_DET_STAT, &val);
++ if (!(val & BM_ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED)) {
++ dev_dbg(charger->dev, "It is a stardard downstream port\n");
++ charger->psy.type = POWER_SUPPLY_TYPE_USB;
++ charger->max_current = 500;
++ disable_charger_detector(regmap);
++ } else {
++ /* It is a charger */
++ disable_charger_detector(regmap);
++ msleep(45);
++ }
++
++ return 0;
++}
++
++static void usb_charger_is_present(struct usb_charger *charger, bool present)
++{
++ if (present)
++ charger->present = 1;
++ else
++ charger->present = 0;
++
++ power_supply_changed(&charger->psy);
++ sysfs_notify(&charger->psy.dev->kobj, NULL, "present");
++}
++
++/*
++ * imx6_usb_vbus_connect - inform about VBUS connection
++ * @charger: the usb charger
++ *
++ * Inform the charger VBUS is connected, vbus detect supplier should call it.
++ * Besides, the USB device controller is expected to keep the dataline
++ * pullups disabled.
++ */
++int imx6_usb_vbus_connect(struct usb_charger *charger)
++{
++ int ret;
++
++ charger->online = 1;
++
++ mutex_lock(&charger->lock);
++
++ /* Start the 1st period charger detection. */
++ ret = imx6_usb_charger_detect(charger);
++ if (ret) {
++ dev_err(charger->dev,
++ "Error occurs during detection: %d\n",
++ ret);
++ } else {
++ if (charger->psy.type == POWER_SUPPLY_TYPE_USB)
++ usb_charger_is_present(charger, true);
++ }
++
++ mutex_unlock(&charger->lock);
++
++ return ret;
++}
++EXPORT_SYMBOL(imx6_usb_vbus_connect);
++
++/*
++ * It must be called after dp is pulled up (from USB controller driver),
++ * That is used to differentiate DCP and CDP
++ */
++int imx6_usb_charger_detect_post(struct usb_charger *charger)
++{
++ struct regmap *regmap = charger->anatop;
++ int val;
++
++ mutex_lock(&charger->lock);
++
++ msleep(40);
++
++ regmap_read(regmap, HW_ANADIG_USB1_CHRG_DET_STAT, &val);
++ if (val & BM_ANADIG_USB1_CHRG_DET_STAT_DM_STATE) {
++ dev_dbg(charger->dev, "It is a dedicate charging port\n");
++ charger->psy.type = POWER_SUPPLY_TYPE_USB_DCP;
++ charger->max_current = 1500;
++ } else {
++ dev_dbg(charger->dev, "It is a charging downstream port\n");
++ charger->psy.type = POWER_SUPPLY_TYPE_USB_CDP;
++ charger->max_current = 900;
++ }
++
++ usb_charger_is_present(charger, true);
++ mutex_unlock(&charger->lock);
++
++ return 0;
++}
++EXPORT_SYMBOL(imx6_usb_charger_detect_post);
++
++/*
++ * imx6_usb_vbus_disconnect - inform about VBUS disconnection
++ * @charger: the usb charger
++ *
++ * Inform the charger that VBUS is disconnected. The charging will be
++ * stopped and the charger properties cleared.
++ */
++int imx6_usb_vbus_disconnect(struct usb_charger *charger)
++{
++ charger->online = 0;
++ charger->max_current = 0;
++ charger->psy.type = POWER_SUPPLY_TYPE_MAINS;
++
++ usb_charger_is_present(charger, false);
++
++ return 0;
++}
++EXPORT_SYMBOL(imx6_usb_vbus_disconnect);
++
++/*
++ * imx6_usb_create_charger - create a USB charger
++ * @charger: the charger to be initialized
++ * @name: name for the power supply
++
++ * Registers a power supply for the charger. The USB Controller
++ * driver will call this after filling struct usb_charger.
++ */
++int imx6_usb_create_charger(struct usb_charger *charger,
++ const char *name)
++{
++ struct power_supply *psy = &charger->psy;
++
++ if (!charger->dev)
++ return -EINVAL;
++
++ if (name)
++ psy->name = name;
++ else
++ psy->name = "imx6_usb_charger";
++
++ charger->bc = BATTERY_CHARGING_SPEC_1_2;
++ mutex_init(&charger->lock);
++
++ psy->type = POWER_SUPPLY_TYPE_MAINS;
++ psy->properties = imx6_usb_charger_power_props;
++ psy->num_properties = ARRAY_SIZE(imx6_usb_charger_power_props);
++ psy->get_property = imx6_usb_charger_get_property;
++ psy->supplied_to = imx6_usb_charger_supplied_to;
++ psy->num_supplicants = sizeof(imx6_usb_charger_supplied_to)
++ / sizeof(char *);
++
++ return power_supply_register(charger->dev, psy);
++}
++EXPORT_SYMBOL(imx6_usb_create_charger);
++
++/*
++ * imx6_usb_remove_charger - remove a USB charger
++ * @charger: the charger to be removed
++ *
++ * Unregister the chargers power supply.
++ */
++void imx6_usb_remove_charger(struct usb_charger *charger)
++{
++ power_supply_unregister(&charger->psy);
++}
++EXPORT_SYMBOL(imx6_usb_remove_charger);
+diff -Nur linux-3.14.72.orig/drivers/power/Kconfig linux-3.14.72/drivers/power/Kconfig
+--- linux-3.14.72.orig/drivers/power/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/power/Kconfig 2016-06-19 22:11:55.309139744 +0200
+@@ -276,6 +276,14 @@
+ pins based on the status of charger connections with interrupt
+ handlers.
+
++config SABRESD_MAX8903
++ tristate "Sabresd Board Battery DC-DC Charger for USB and Adapter Power"
++ depends on TOUCHSCREEN_MAX11801
++ help
++ Say Y to enable support for the MAX8903 DC-DC charger and sysfs on
++ sabresd board.The driver supports controlling charger and battery
++ based on the status of charger connections with interrupt handlers.
++
+ config CHARGER_TWL4030
+ tristate "OMAP TWL4030 BCI charger driver"
+ depends on TWL4030_CORE
+@@ -389,6 +397,12 @@
+ Say Y to enable support for the battery and AC power in the
+ Goldfish emulator.
+
++config IMX6_USB_CHARGER
++ bool "Freescale imx6 USB Charger"
++ depends on SOC_IMX6Q || SOC_IMX6SL || SOC_IMX6SX
++ help
++ Say Y to enable Freescale imx6 USB Charger Detect.
++
+ source "drivers/power/reset/Kconfig"
+
+ endif # POWER_SUPPLY
+diff -Nur linux-3.14.72.orig/drivers/power/Makefile linux-3.14.72/drivers/power/Makefile
+--- linux-3.14.72.orig/drivers/power/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/power/Makefile 2016-06-19 22:11:55.309139744 +0200
+@@ -43,6 +43,7 @@
+ obj-$(CONFIG_AB8500_BM) += ab8500_bmdata.o ab8500_charger.o ab8500_fg.o ab8500_btemp.o abx500_chargalg.o pm2301_charger.o
+ obj-$(CONFIG_CHARGER_ISP1704) += isp1704_charger.o
+ obj-$(CONFIG_CHARGER_MAX8903) += max8903_charger.o
++obj-$(CONFIG_SABRESD_MAX8903) += sabresd_battery.o
+ obj-$(CONFIG_CHARGER_TWL4030) += twl4030_charger.o
+ obj-$(CONFIG_CHARGER_LP8727) += lp8727_charger.o
+ obj-$(CONFIG_CHARGER_LP8788) += lp8788-charger.o
+@@ -58,3 +59,4 @@
+ obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o
+ obj-$(CONFIG_CHARGER_TPS65090) += tps65090-charger.o
+ obj-$(CONFIG_POWER_RESET) += reset/
++obj-$(CONFIG_IMX6_USB_CHARGER) += imx6_usb_charger.o
+diff -Nur linux-3.14.72.orig/drivers/power/reset/Kconfig linux-3.14.72/drivers/power/reset/Kconfig
+--- linux-3.14.72.orig/drivers/power/reset/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/power/reset/Kconfig 2016-06-19 22:11:55.309139744 +0200
+@@ -43,6 +43,14 @@
+ Instead they restart, and u-boot holds the SoC until the
+ user presses a key. u-boot then boots into Linux.
+
++config POWER_RESET_SNVS
++ bool "Freescale SNVS RTC power-off driver"
++ depends on ARM
++ depends on RTC_DRV_SNVS
++ help
++ Power off support for Freescale SOCs that rely on the SNVS
++ RTC to poweroff the SOC.
++
+ config POWER_RESET_VEXPRESS
+ bool "ARM Versatile Express power-off and reset driver"
+ depends on ARM || ARM64
+diff -Nur linux-3.14.72.orig/drivers/power/reset/Makefile linux-3.14.72/drivers/power/reset/Makefile
+--- linux-3.14.72.orig/drivers/power/reset/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/power/reset/Makefile 2016-06-19 22:11:55.309139744 +0200
+@@ -3,5 +3,6 @@
+ obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
+ obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
+ obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
++obj-$(CONFIG_POWER_RESET_SNVS) += snvs-poweroff.o
+ obj-$(CONFIG_POWER_RESET_VEXPRESS) += vexpress-poweroff.o
+ obj-$(CONFIG_POWER_RESET_XGENE) += xgene-reboot.o
+diff -Nur linux-3.14.72.orig/drivers/power/reset/snvs-poweroff.c linux-3.14.72/drivers/power/reset/snvs-poweroff.c
+--- linux-3.14.72.orig/drivers/power/reset/snvs-poweroff.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/power/reset/snvs-poweroff.c 2016-06-19 22:11:55.309139744 +0200
+@@ -0,0 +1,59 @@
++/*
++ * Power off by restarting and let u-boot keep hold of the machine
++ * until the user presses a button for example.
++ *
++ * Andrew Lunn <andrew@lunn.ch>
++ *
++ * Copyright (C) 2012 Andrew Lunn
++ * Copyright (C) 2015 Jon Nettleton
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/of_platform.h>
++#include <linux/module.h>
++#include <linux/reboot.h>
++#include <asm/system_misc.h>
++
++extern void snvs_poweroff(void);
++
++static int snvs_poweroff_probe(struct platform_device *pdev)
++{
++ /*
++ * if no specific power off function in board file, power off system by
++ * SNVS
++ */
++ if (!pm_power_off)
++ pm_power_off = snvs_poweroff;
++
++ return 0;
++}
++
++static int snvs_poweroff_remove(struct platform_device *pdev)
++{
++ if (pm_power_off == &snvs_poweroff)
++ pm_power_off = NULL;
++
++ return 0;
++}
++
++static const struct of_device_id of_snvs_poweroff_match[] = {
++ { .compatible = "fsl,snvs-poweroff", },
++ {},
++};
++
++static struct platform_driver snvs_poweroff_driver = {
++ .probe = snvs_poweroff_probe,
++ .remove = snvs_poweroff_remove,
++ .driver = {
++ .name = "snvs-poweroff",
++ .owner = THIS_MODULE,
++ .of_match_table = of_snvs_poweroff_match,
++ },
++};
++module_platform_driver(snvs_poweroff_driver);
+diff -Nur linux-3.14.72.orig/drivers/power/sabresd_battery.c linux-3.14.72/drivers/power/sabresd_battery.c
+--- linux-3.14.72.orig/drivers/power/sabresd_battery.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/power/sabresd_battery.c 2016-06-19 22:11:55.309139744 +0200
+@@ -0,0 +1,998 @@
++/*
++ * sabresd_battery.c - Maxim 8903 USB/Adapter Charger Driver
++ *
++ * Copyright (C) 2011 Samsung Electronics
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ * Based on max8903_charger.c
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_gpio.h>
++#include <linux/power_supply.h>
++#include <linux/platform_device.h>
++#include <linux/power/sabresd_battery.h>
++#include <linux/slab.h>
++
++#define BATTERY_UPDATE_INTERVAL 5 /*seconds*/
++#define LOW_VOLT_THRESHOLD 2800000
++#define HIGH_VOLT_THRESHOLD 4200000
++#define ADC_SAMPLE_COUNT 6
++
++struct max8903_data {
++ struct max8903_pdata *pdata;
++ struct device *dev;
++ struct power_supply psy;
++ struct power_supply usb;
++ bool fault;
++ bool usb_in;
++ bool ta_in;
++ bool chg_state;
++ struct delayed_work work;
++ unsigned int interval;
++ unsigned short thermal_raw;
++ int voltage_uV;
++ int current_uA;
++ int battery_status;
++ int charger_online;
++ int charger_voltage_uV;
++ int real_capacity;
++ int percent;
++ int old_percent;
++ int usb_charger_online;
++ int first_delay_count;
++ struct power_supply bat;
++ struct power_supply detect_usb;
++};
++
++typedef struct {
++ u32 voltage;
++ u32 percent;
++} battery_capacity , *pbattery_capacity;
++
++static int offset_discharger;
++static int offset_charger;
++static int offset_usb_charger;
++
++static battery_capacity chargingTable[] = {
++ {4050, 99},
++ {4040, 98},
++ {4020, 97},
++ {4010, 96},
++ {3990, 95},
++ {3980, 94},
++ {3970, 93},
++ {3960, 92},
++ {3950, 91},
++ {3940, 90},
++ {3930, 85},
++ {3920, 81},
++ {3910, 77},
++ {3900, 73},
++ {3890, 70},
++ {3860, 65},
++ {3830, 60},
++ {3780, 55},
++ {3760, 50},
++ {3740, 45},
++ {3720, 40},
++ {3700, 35},
++ {3680, 30},
++ {3660, 25},
++ {3640, 20},
++ {3620, 17},
++ {3600, 14},
++ {3580, 13},
++ {3560, 12},
++ {3540, 11},
++ {3520, 10},
++ {3500, 9},
++ {3480, 8},
++ {3460, 7},
++ {3440, 6},
++ {3430, 5},
++ {3420, 4},
++ {3020, 0},
++};
++
++static battery_capacity dischargingTable[] = {
++ {4050, 100},
++ {4035, 99},
++ {4020, 98},
++ {4010, 97},
++ {4000, 96},
++ {3990, 96},
++ {3980, 95},
++ {3970, 92},
++ {3960, 91},
++ {3950, 90},
++ {3940, 88},
++ {3930, 86},
++ {3920, 84},
++ {3910, 82},
++ {3900, 80},
++ {3890, 74},
++ {3860, 69},
++ {3830, 64},
++ {3780, 59},
++ {3760, 54},
++ {3740, 49},
++ {3720, 44},
++ {3700, 39},
++ {3680, 34},
++ {3660, 29},
++ {3640, 24},
++ {3620, 19},
++ {3600, 14},
++ {3580, 13},
++ {3560, 12},
++ {3540, 11},
++ {3520, 10},
++ {3500, 9},
++ {3480, 8},
++ {3460, 7},
++ {3440, 6},
++ {3430, 5},
++ {3420, 4},
++ {3020, 0},
++};
++
++u32 calibrate_battery_capability_percent(struct max8903_data *data)
++{
++ u8 i;
++ pbattery_capacity pTable;
++ u32 tableSize;
++
++ if (data->battery_status == POWER_SUPPLY_STATUS_DISCHARGING) {
++ pTable = dischargingTable;
++ tableSize = sizeof(dischargingTable)/
++ sizeof(dischargingTable[0]);
++ } else {
++ pTable = chargingTable;
++ tableSize = sizeof(chargingTable)/
++ sizeof(chargingTable[0]);
++ }
++ for (i = 0; i < tableSize; i++) {
++ if (data->voltage_uV >= pTable[i].voltage)
++ return pTable[i].percent;
++ }
++
++ return 0;
++}
++
++static enum power_supply_property max8903_charger_props[] = {
++ POWER_SUPPLY_PROP_ONLINE,
++};
++
++static enum power_supply_property max8903_battery_props[] = {
++ POWER_SUPPLY_PROP_VOLTAGE_NOW,
++ POWER_SUPPLY_PROP_STATUS,
++ POWER_SUPPLY_PROP_PRESENT,
++ POWER_SUPPLY_PROP_CAPACITY,
++ POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
++ POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
++ POWER_SUPPLY_PROP_HEALTH,
++ POWER_SUPPLY_PROP_CAPACITY_LEVEL,
++};
++
++extern u32 max11801_read_adc(void);
++
++static void max8903_charger_update_status(struct max8903_data *data)
++{
++ if (data->ta_in) {
++ data->charger_online = 1;
++ } else if (data->usb_in) {
++ data->usb_charger_online = 1;
++ } else {
++ data->charger_online = 0;
++ data->usb_charger_online = 0;
++ }
++
++ if (!data->charger_online && !data->usb_charger_online) {
++ data->battery_status = POWER_SUPPLY_STATUS_DISCHARGING;
++ } else if (gpio_get_value(data->pdata->chg) == 0) {
++ data->battery_status = POWER_SUPPLY_STATUS_CHARGING;
++ } else if ((data->ta_in || data->usb_in) &&
++ gpio_get_value(data->pdata->chg) > 0) {
++ if (!data->pdata->feature_flag) {
++ if (data->percent >= 99)
++ data->battery_status = POWER_SUPPLY_STATUS_FULL;
++ else
++ data->battery_status =
++ POWER_SUPPLY_STATUS_NOT_CHARGING;
++ } else {
++ data->battery_status = POWER_SUPPLY_STATUS_FULL;
++ }
++ }
++}
++
++u32 calibration_voltage(struct max8903_data *data)
++{
++ u32 voltage_data = 0;
++ int i;
++ int offset;
++
++ if (!data->charger_online && !data->usb_charger_online)
++ offset = offset_discharger;
++ else if (data->usb_charger_online)
++ offset = offset_usb_charger;
++ else if (data->charger_online)
++ offset = offset_charger;
++
++ /* simple average */
++ for (i = 0; i < ADC_SAMPLE_COUNT; i++)
++ voltage_data += max11801_read_adc()-offset;
++ voltage_data = voltage_data / ADC_SAMPLE_COUNT;
++ dev_dbg(data->dev, "volt: %d\n", voltage_data);
++
++ return voltage_data;
++}
++
++static void max8903_battery_update_status(struct max8903_data *data)
++{
++ if (!data->pdata->feature_flag) {
++ data->voltage_uV = calibration_voltage(data);
++ data->percent = calibrate_battery_capability_percent(data);
++ if (data->percent != data->old_percent) {
++ data->old_percent = data->percent;
++ power_supply_changed(&data->bat);
++ }
++ /*
++ * because boot time gap between led framwork and charger
++ * framwork,when system boots with charger attatched,
++ * charger led framwork loses the first charger online event,
++ * add once extra power_supply_changed can fix this issure
++ */
++ if (data->first_delay_count < 200) {
++ data->first_delay_count = data->first_delay_count + 1;
++ power_supply_changed(&data->bat);
++ }
++ }
++}
++
++static int max8903_battery_get_property(struct power_supply *bat,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct max8903_data *di = container_of(bat, struct max8903_data, bat);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_STATUS:
++ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
++ if (gpio_get_value(di->pdata->chg) == 0) {
++ di->battery_status = POWER_SUPPLY_STATUS_CHARGING;
++ } else if ((di->ta_in || di->usb_in) &&
++ gpio_get_value(di->pdata->chg) > 0) {
++ if (!di->pdata->feature_flag) {
++ if (di->percent >= 99)
++ di->battery_status =
++ POWER_SUPPLY_STATUS_FULL;
++ else
++ di->battery_status =
++ POWER_SUPPLY_STATUS_NOT_CHARGING;
++ } else {
++ di->battery_status = POWER_SUPPLY_STATUS_FULL;
++ }
++ }
++ val->intval = di->battery_status;
++ return 0;
++ default:
++ break;
++ }
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_VOLTAGE_NOW:
++ val->intval = di->voltage_uV;
++ break;
++ case POWER_SUPPLY_PROP_CHARGE_NOW:
++ val->intval = 0;
++ break;
++ case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
++ val->intval = HIGH_VOLT_THRESHOLD;
++ break;
++ case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN:
++ val->intval = LOW_VOLT_THRESHOLD;
++ break;
++ case POWER_SUPPLY_PROP_PRESENT:
++ val->intval = 1;
++ break;
++ case POWER_SUPPLY_PROP_CAPACITY:
++ val->intval = di->percent < 0 ? 0 :
++ (di->percent > 100 ? 100 : di->percent);
++ break;
++ case POWER_SUPPLY_PROP_HEALTH:
++ val->intval = POWER_SUPPLY_HEALTH_GOOD;
++ if (di->fault)
++ val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE;
++ break;
++ case POWER_SUPPLY_PROP_CAPACITY_LEVEL:
++ if (di->battery_status == POWER_SUPPLY_STATUS_FULL)
++ val->intval = POWER_SUPPLY_CAPACITY_LEVEL_FULL;
++ else if (di->percent <= 15)
++ val->intval = POWER_SUPPLY_CAPACITY_LEVEL_LOW;
++ else
++ val->intval = POWER_SUPPLY_CAPACITY_LEVEL_NORMAL;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int max8903_get_property(struct power_supply *psy,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct max8903_data *data = container_of(psy,
++ struct max8903_data, psy);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_ONLINE:
++ val->intval = 0;
++ if (data->ta_in)
++ val->intval = 1;
++ data->charger_online = val->intval;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int max8903_get_usb_property(struct power_supply *usb,
++ enum power_supply_property psp,
++ union power_supply_propval *val)
++{
++ struct max8903_data *data = container_of(usb,
++ struct max8903_data, usb);
++
++ switch (psp) {
++ case POWER_SUPPLY_PROP_ONLINE:
++ val->intval = 0;
++ if (data->usb_in)
++ val->intval = 1;
++ data->usb_charger_online = val->intval;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static irqreturn_t max8903_dcin(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ bool ta_in = false;
++
++ if (pdata->dok)
++ ta_in = gpio_get_value(pdata->dok) ? false : true;
++
++ if (ta_in == data->ta_in)
++ return IRQ_HANDLED;
++
++ data->ta_in = ta_in;
++ dev_info(data->dev, "TA(DC-IN) Charger %s.\n", ta_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ power_supply_changed(&data->bat);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t max8903_usbin(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ bool usb_in = false;
++
++ if (pdata->uok)
++ usb_in = gpio_get_value(pdata->uok) ? false : true;
++ if (usb_in == data->usb_in)
++ return IRQ_HANDLED;
++ data->usb_in = usb_in;
++ dev_info(data->dev, "USB Charger %s.\n", usb_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->bat);
++ power_supply_changed(&data->usb);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t max8903_fault(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ bool fault;
++
++ fault = gpio_get_value(pdata->flt) ? false : true;
++
++ if (fault == data->fault)
++ return IRQ_HANDLED;
++ data->fault = fault;
++
++ if (fault)
++ dev_err(data->dev, "Charger suffers a fault and stops.\n");
++ else
++ dev_err(data->dev, "Charger recovered from a fault.\n");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ power_supply_changed(&data->bat);
++ power_supply_changed(&data->usb);
++
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t max8903_chg(int irq, void *_data)
++{
++ struct max8903_data *data = _data;
++ struct max8903_pdata *pdata = data->pdata;
++ int chg_state;
++
++ chg_state = gpio_get_value(pdata->chg) ? false : true;
++
++ if (chg_state == data->chg_state)
++ return IRQ_HANDLED;
++ data->chg_state = chg_state;
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ power_supply_changed(&data->bat);
++ power_supply_changed(&data->usb);
++
++ return IRQ_HANDLED;
++}
++
++static void max8903_battery_work(struct work_struct *work)
++{
++ struct max8903_data *data;
++
++ data = container_of(work, struct max8903_data, work.work);
++ data->interval = HZ * BATTERY_UPDATE_INTERVAL;
++
++ max8903_charger_update_status(data);
++ max8903_battery_update_status(data);
++ dev_dbg(data->dev, "battery voltage: %4d mV\n", data->voltage_uV);
++ dev_dbg(data->dev, "charger online status: %d\n",
++ data->charger_online);
++ dev_dbg(data->dev, "battery status : %d\n" , data->battery_status);
++ dev_dbg(data->dev, "battery capacity percent: %3d\n", data->percent);
++ dev_dbg(data->dev, "data->usb_in: %x , data->ta_in: %x\n",
++ data->usb_in, data->ta_in);
++ /* reschedule for the next time */
++ schedule_delayed_work(&data->work, data->interval);
++}
++
++static ssize_t max8903_voltage_offset_discharger_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "read offset_discharger:%04d\n",
++ offset_discharger);
++}
++
++static ssize_t max8903_voltage_offset_discharger_store(struct device *dev,
++ struct device_attribute *attr, const char *buf,
++ size_t count)
++{
++ int ret;
++ unsigned long data;
++
++ ret = strict_strtoul(buf, 10, &data);
++ offset_discharger = (int)data;
++ pr_info("read offset_discharger:%04d\n", offset_discharger);
++
++ return count;
++}
++
++static ssize_t max8903_voltage_offset_charger_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "read offset_charger:%04d\n",
++ offset_charger);
++}
++
++static ssize_t max8903_voltage_offset_charger_store(struct device *dev,
++ struct device_attribute *attr, const char *buf,
++ size_t count)
++{
++ int ret;
++ unsigned long data;
++
++ ret = strict_strtoul(buf, 10, &data);
++ offset_charger = (int)data;
++ pr_info("read offset_charger:%04d\n", offset_charger);
++ return count;
++}
++
++static ssize_t max8903_voltage_offset_usb_charger_show(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ return sprintf(buf, "read offset_usb_charger:%04d\n",
++ offset_usb_charger);
++}
++
++static ssize_t max8903_voltage_offset_usb_charger_store(struct device *dev,
++ struct device_attribute *attr, const char *buf,
++ size_t count)
++{
++ int ret;
++ unsigned long data;
++
++ ret = strict_strtoul(buf, 10, &data);
++ offset_usb_charger = (int)data;
++ pr_info("read offset_charger:%04d\n", offset_usb_charger);
++
++ return count;
++}
++
++static struct device_attribute max8903_discharger_dev_attr = {
++ .attr = {
++ .name = "max8903_ctl_offset_discharger",
++ .mode = S_IRUSR | S_IWUSR,
++ },
++ .show = max8903_voltage_offset_discharger_show,
++ .store = max8903_voltage_offset_discharger_store,
++};
++
++static struct device_attribute max8903_charger_dev_attr = {
++ .attr = {
++ .name = "max8903_ctl_offset_charger",
++ .mode = S_IRUSR | S_IWUSR,
++ },
++ .show = max8903_voltage_offset_charger_show,
++ .store = max8903_voltage_offset_charger_store,
++};
++
++static struct device_attribute max8903_usb_charger_dev_attr = {
++ .attr = {
++ .name = "max8903_ctl_offset_usb_charger",
++ .mode = S_IRUSR | S_IWUSR,
++ },
++ .show = max8903_voltage_offset_usb_charger_show,
++ .store = max8903_voltage_offset_usb_charger_store,
++};
++
++#if defined(CONFIG_OF)
++static const struct of_device_id max8903_dt_ids[] = {
++ { .compatible = "fsl,max8903-charger", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, max8903_dt_ids);
++
++static struct max8903_pdata *max8903_of_populate_pdata(
++ struct device *dev)
++{
++ struct device_node *of_node = dev->of_node;
++ struct max8903_pdata *pdata = dev->platform_data;
++
++ if (!of_node || pdata)
++ return pdata;
++
++ pdata = devm_kzalloc(dev, sizeof(struct max8903_pdata),
++ GFP_KERNEL);
++ if (!pdata)
++ return pdata;
++
++ if (of_get_property(of_node, "fsl,dcm_always_high", NULL))
++ pdata->dcm_always_high = true;
++ if (of_get_property(of_node, "fsl,dc_valid", NULL))
++ pdata->dc_valid = true;
++ if (of_get_property(of_node, "fsl,usb_valid", NULL))
++ pdata->usb_valid = true;
++ if (of_get_property(of_node, "fsl,adc_disable", NULL))
++ pdata->feature_flag = true;
++
++ if (pdata->dc_valid) {
++ pdata->dok = of_get_named_gpio(of_node, "dok_input", 0);
++ if (!gpio_is_valid(pdata->dok)) {
++ dev_err(dev, "pin pdata->dok: invalid gpio %d\n", pdata->dok);
++ return NULL;
++ }
++ }
++ if (pdata->usb_valid) {
++ pdata->uok = of_get_named_gpio(of_node, "uok_input", 0);
++ if (!gpio_is_valid(pdata->uok)) {
++ dev_err(dev, "pin pdata->uok: invalid gpio %d\n", pdata->uok);
++ return NULL;
++ }
++ }
++ pdata->chg = of_get_named_gpio(of_node, "chg_input", 0);
++ if (!gpio_is_valid(pdata->chg)) {
++ dev_err(dev, "pin pdata->chg: invalid gpio %d\n", pdata->chg);
++ return NULL;
++ }
++ pdata->flt = of_get_named_gpio(of_node, "flt_input", 0);
++ if (!gpio_is_valid(pdata->flt)) {
++ dev_err(dev, "pin pdata->flt: invalid gpio %d\n", pdata->flt);
++ return NULL;
++ }
++ /* no need check offset without adc converter */
++ if (!pdata->feature_flag) {
++ if (of_property_read_u32(of_node, "offset-charger",
++ &offset_charger))
++ dev_err(dev, "Not setting offset-charger in dts!\n");
++
++ if (of_property_read_u32(of_node, "offset-discharger",
++ &offset_discharger))
++ dev_err(dev, "Not setting offset-discharger in dts!\n");
++
++ if (of_property_read_u32(of_node, "offset-usb-charger",
++ &offset_usb_charger))
++ dev_err(dev, "Not setting offset-usb-charger in dts!\n");
++ }
++
++ return pdata;
++}
++#endif
++
++static int max8903_probe(struct platform_device *pdev)
++{
++ struct max8903_data *data;
++ struct device *dev = &pdev->dev;
++ struct max8903_pdata *pdata = pdev->dev.platform_data;
++ int ret = 0;
++ int gpio = 0;
++ int ta_in = 0;
++ int usb_in = 0;
++ int retval;
++
++ data = devm_kzalloc(dev, sizeof(struct max8903_data), GFP_KERNEL);
++ if (!data)
++ return -ENOMEM;
++
++ pdata = pdev->dev.platform_data;
++ if (!pdata) {
++ pdata = max8903_of_populate_pdata(&pdev->dev);
++ if (!pdata)
++ return -EINVAL;
++ }
++
++ data->first_delay_count = 0;
++ data->pdata = pdata;
++ data->dev = dev;
++ data->usb_in = 0;
++ data->ta_in = 0;
++ platform_set_drvdata(pdev, data);
++
++ if (pdata->dc_valid == false && pdata->usb_valid == false) {
++ dev_err(dev, "No valid power sources.\n");
++ ret = -EINVAL;
++ goto err;
++ }
++ if (pdata->dc_valid) {
++ if (pdata->dok && pdata->dcm_always_high) {
++ gpio = pdata->dok;
++ ret = gpio_request_one(gpio, GPIOF_IN, "max8903-DOK");
++ if (ret) {
++ dev_err(dev, "request max8903-DOK error!!\n");
++ goto err;
++ }
++ ta_in = gpio_get_value(gpio) ? 0 : 1;
++ } else {
++ dev_err(dev, "When DC is wired, DOK and DCM should be"
++ " wired as well or set dcm always high!\n");
++ ret = -EINVAL;
++ goto err;
++ }
++ }
++
++ if (pdata->usb_valid) {
++ if (pdata->uok) {
++ gpio = pdata->uok;
++ ret = gpio_request_one(gpio, GPIOF_IN, "max8903-UOK");
++ if (ret) {
++ dev_err(dev, "request max8903-UOK error!!\n");
++ goto err;
++ }
++ usb_in = gpio_get_value(gpio) ? 0 : 1;
++ } else {
++ dev_err(dev, "When USB is wired, UOK should be wired"
++ " as well.\n");
++ ret = -EINVAL;
++ goto err;
++ }
++ }
++
++ if (pdata->chg) {
++ ret = gpio_request_one(pdata->chg, GPIOF_IN, "max8903-CHG");
++ if (ret) {
++ dev_err(dev, "request max8903-CHG error!!\n");
++ goto err;
++ }
++ }
++
++ if (pdata->flt) {
++ ret = gpio_request_one(pdata->flt, GPIOF_IN, "max8903-FLT");
++ if (ret) {
++ dev_err(dev, "request max8903-FLT error!!\n");
++ goto err;
++ }
++ }
++
++ data->fault = false;
++ data->ta_in = ta_in;
++ data->usb_in = usb_in;
++ data->psy.name = "max8903-ac";
++ data->psy.type = POWER_SUPPLY_TYPE_MAINS;
++ data->psy.get_property = max8903_get_property;
++ data->psy.properties = max8903_charger_props;
++ data->psy.num_properties = ARRAY_SIZE(max8903_charger_props);
++ ret = power_supply_register(dev, &data->psy);
++ if (ret) {
++ dev_err(dev, "failed: power supply register.\n");
++ goto err_psy;
++ }
++
++ data->usb.name = "max8903-usb";
++ data->usb.type = POWER_SUPPLY_TYPE_USB;
++ data->usb.get_property = max8903_get_usb_property;
++ data->usb.properties = max8903_charger_props;
++ data->usb.num_properties = ARRAY_SIZE(max8903_charger_props);
++ ret = power_supply_register(dev, &data->usb);
++ if (ret) {
++ dev_err(dev, "failed: power supply register.\n");
++ goto err_psy;
++ }
++
++ data->bat.name = "max8903-charger";
++ data->bat.type = POWER_SUPPLY_TYPE_BATTERY;
++ data->bat.properties = max8903_battery_props;
++ data->bat.num_properties = ARRAY_SIZE(max8903_battery_props);
++ data->bat.get_property = max8903_battery_get_property;
++ data->bat.use_for_apm = 1;
++ retval = power_supply_register(&pdev->dev, &data->bat);
++ if (retval) {
++ dev_err(data->dev, "failed to register battery\n");
++ goto battery_failed;
++ }
++
++ INIT_DELAYED_WORK(&data->work, max8903_battery_work);
++ schedule_delayed_work(&data->work, data->interval);
++
++ if (pdata->dc_valid) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->dok), NULL,
++ max8903_dcin, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 DC IN",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for DC (%d)\n",
++ gpio_to_irq(pdata->dok), ret);
++ goto err_dc_irq;
++ }
++ }
++
++ if (pdata->usb_valid) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->uok), NULL,
++ max8903_usbin, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 USB IN",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for USB (%d)\n",
++ gpio_to_irq(pdata->uok), ret);
++ goto err_usb_irq;
++ }
++ }
++
++ if (pdata->flt) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->flt), NULL,
++ max8903_fault, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 Fault",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for Fault (%d)\n",
++ gpio_to_irq(pdata->flt), ret);
++ goto err_flt_irq;
++ }
++ }
++
++ if (pdata->chg) {
++ ret = request_threaded_irq(gpio_to_irq(pdata->chg), NULL,
++ max8903_chg, IRQF_TRIGGER_FALLING |
++ IRQF_TRIGGER_RISING | IRQF_ONESHOT, "MAX8903 Status",
++ data);
++ if (ret) {
++ dev_err(dev, "Cannot request irq %d for Status (%d)\n",
++ gpio_to_irq(pdata->flt), ret);
++ goto err_chg_irq;
++ }
++ }
++
++ ret = device_create_file(&pdev->dev, &max8903_discharger_dev_attr);
++ if (ret)
++ dev_err(&pdev->dev, "create device file failed!\n");
++ ret = device_create_file(&pdev->dev, &max8903_charger_dev_attr);
++ if (ret)
++ dev_err(&pdev->dev, "create device file failed!\n");
++ ret = device_create_file(&pdev->dev, &max8903_usb_charger_dev_attr);
++ if (ret)
++ dev_err(&pdev->dev, "create device file failed!\n");
++
++ device_set_wakeup_capable(&pdev->dev, true);
++
++ max8903_charger_update_status(data);
++ max8903_battery_update_status(data);
++
++ return 0;
++err_psy:
++ power_supply_unregister(&data->psy);
++battery_failed:
++ power_supply_unregister(&data->bat);
++err_usb_irq:
++ if (pdata->usb_valid)
++ free_irq(gpio_to_irq(pdata->uok), data);
++ cancel_delayed_work(&data->work);
++err_dc_irq:
++ if (pdata->dc_valid)
++ free_irq(gpio_to_irq(pdata->dok), data);
++ cancel_delayed_work(&data->work);
++err_flt_irq:
++ if (pdata->usb_valid)
++ free_irq(gpio_to_irq(pdata->uok), data);
++ cancel_delayed_work(&data->work);
++err_chg_irq:
++ if (pdata->dc_valid)
++ free_irq(gpio_to_irq(pdata->dok), data);
++ cancel_delayed_work(&data->work);
++err:
++ if (pdata->uok)
++ gpio_free(pdata->uok);
++ if (pdata->dok)
++ gpio_free(pdata->dok);
++ if (pdata->flt)
++ gpio_free(pdata->flt);
++ if (pdata->chg)
++ gpio_free(pdata->chg);
++ return ret;
++}
++
++static int max8903_remove(struct platform_device *pdev)
++{
++ struct max8903_data *data = platform_get_drvdata(pdev);
++ if (data) {
++ struct max8903_pdata *pdata = data->pdata;
++
++ cancel_delayed_work_sync(&data->work);
++ power_supply_unregister(&data->psy);
++ power_supply_unregister(&data->usb);
++ power_supply_unregister(&data->bat);
++
++ if (pdata->flt) {
++ free_irq(gpio_to_irq(pdata->flt), data);
++ gpio_free(pdata->flt);
++ }
++ if (pdata->usb_valid && pdata->uok) {
++ free_irq(gpio_to_irq(pdata->uok), data);
++ gpio_free(pdata->uok);
++ }
++ if (pdata->dc_valid) {
++ if (pdata->dok) {
++ free_irq(gpio_to_irq(pdata->dok), data);
++ gpio_free(pdata->dok);
++ } else if (pdata->chg) {
++ free_irq(gpio_to_irq(pdata->chg), data);
++ gpio_free(pdata->chg);
++ }
++ }
++
++ device_remove_file(&pdev->dev, &max8903_discharger_dev_attr);
++ device_remove_file(&pdev->dev, &max8903_charger_dev_attr);
++ device_remove_file(&pdev->dev, &max8903_usb_charger_dev_attr);
++
++ platform_set_drvdata(pdev, NULL);
++ kfree(data);
++ }
++
++ return 0;
++}
++
++static int max8903_suspend(struct platform_device *pdev,
++ pm_message_t state)
++{
++ struct max8903_data *data = platform_get_drvdata(pdev);
++ int irq;
++ if (data) {
++ struct max8903_pdata *pdata = data->pdata;
++ if (pdata) {
++ if (pdata->dc_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->dok);
++ enable_irq_wake(irq);
++ }
++
++ if (pdata->usb_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->uok);
++ enable_irq_wake(irq);
++ }
++ cancel_delayed_work(&data->work);
++ }
++ }
++ return 0;
++}
++
++static int max8903_resume(struct platform_device *pdev)
++{
++ struct max8903_data *data = platform_get_drvdata(pdev);
++ bool ta_in = false;
++ bool usb_in = false;
++ int irq;
++
++ if (data) {
++ struct max8903_pdata *pdata = data->pdata;
++
++ if (pdata) {
++ if (pdata->dok)
++ ta_in = gpio_get_value(pdata->dok) ? false : true;
++ if (pdata->uok)
++ usb_in = gpio_get_value(pdata->uok) ? false : true;
++
++ if (ta_in != data->ta_in) {
++ data->ta_in = ta_in;
++ dev_info(data->dev, "TA(DC-IN) Charger %s.\n", ta_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->psy);
++ }
++
++ if (usb_in != data->usb_in) {
++ data->usb_in = usb_in;
++ dev_info(data->dev, "USB Charger %s.\n", usb_in ?
++ "Connected" : "Disconnected");
++ max8903_charger_update_status(data);
++ power_supply_changed(&data->usb);
++ }
++
++ if (pdata->dc_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->dok);
++ disable_irq_wake(irq);
++ }
++ if (pdata->usb_valid && device_may_wakeup(&pdev->dev)) {
++ irq = gpio_to_irq(pdata->uok);
++ disable_irq_wake(irq);
++ }
++
++ schedule_delayed_work(&data->work,
++ BATTERY_UPDATE_INTERVAL);
++ }
++ }
++
++ return 0;
++}
++
++static struct platform_driver max8903_driver = {
++ .probe = max8903_probe,
++ .remove = max8903_remove,
++ .suspend = max8903_suspend,
++ .resume = max8903_resume,
++ .driver = {
++ .name = "max8903-charger",
++ .owner = THIS_MODULE,
++ .of_match_table = max8903_dt_ids,
++ },
++};
++module_platform_driver(max8903_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Sabresd Battery Driver");
++MODULE_ALIAS("sabresd_battery");
+diff -Nur linux-3.14.72.orig/drivers/ptp/ptp_chardev.c linux-3.14.72/drivers/ptp/ptp_chardev.c
+--- linux-3.14.72.orig/drivers/ptp/ptp_chardev.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ptp/ptp_chardev.c 2016-06-19 22:11:55.309139744 +0200
+@@ -25,6 +25,96 @@
+
+ #include "ptp_private.h"
+
++static int ptp_disable_pinfunc(struct ptp_clock_info *ops,
++ enum ptp_pin_function func, unsigned int chan)
++{
++ struct ptp_clock_request rq;
++ int err = 0;
++
++ memset(&rq, 0, sizeof(rq));
++
++ switch (func) {
++ case PTP_PF_NONE:
++ break;
++ case PTP_PF_EXTTS:
++ rq.type = PTP_CLK_REQ_EXTTS;
++ rq.extts.index = chan;
++ err = ops->enable(ops, &rq, 0);
++ break;
++ case PTP_PF_PEROUT:
++ rq.type = PTP_CLK_REQ_PEROUT;
++ rq.perout.index = chan;
++ err = ops->enable(ops, &rq, 0);
++ break;
++ case PTP_PF_PHYSYNC:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return err;
++}
++
++int ptp_set_pinfunc(struct ptp_clock *ptp, unsigned int pin,
++ enum ptp_pin_function func, unsigned int chan)
++{
++ struct ptp_clock_info *info = ptp->info;
++ struct ptp_pin_desc *pin1 = NULL, *pin2 = &info->pin_config[pin];
++ unsigned int i;
++
++ /* Check to see if any other pin previously had this function. */
++ for (i = 0; i < info->n_pins; i++) {
++ if (info->pin_config[i].func == func &&
++ info->pin_config[i].chan == chan) {
++ pin1 = &info->pin_config[i];
++ break;
++ }
++ }
++ if (pin1 && i == pin)
++ return 0;
++
++ /* Check the desired function and channel. */
++ switch (func) {
++ case PTP_PF_NONE:
++ break;
++ case PTP_PF_EXTTS:
++ if (chan >= info->n_ext_ts)
++ return -EINVAL;
++ break;
++ case PTP_PF_PEROUT:
++ if (chan >= info->n_per_out)
++ return -EINVAL;
++ break;
++ case PTP_PF_PHYSYNC:
++ pr_err("sorry, cannot reassign the calibration pin\n");
++ return -EINVAL;
++ default:
++ return -EINVAL;
++ }
++
++ if (pin2->func == PTP_PF_PHYSYNC) {
++ pr_err("sorry, cannot reprogram the calibration pin\n");
++ return -EINVAL;
++ }
++
++ if (info->verify(info, pin, func, chan)) {
++ pr_err("driver cannot use function %u on pin %u\n", func, chan);
++ return -EOPNOTSUPP;
++ }
++
++ /* Disable whatever function was previously assigned. */
++ if (pin1) {
++ ptp_disable_pinfunc(info, func, chan);
++ pin1->func = PTP_PF_NONE;
++ pin1->chan = 0;
++ }
++ ptp_disable_pinfunc(info, pin2->func, pin2->chan);
++ pin2->func = func;
++ pin2->chan = chan;
++
++ return 0;
++}
++
+ int ptp_open(struct posix_clock *pc, fmode_t fmode)
+ {
+ return 0;
+@@ -35,12 +125,13 @@
+ struct ptp_clock_caps caps;
+ struct ptp_clock_request req;
+ struct ptp_sys_offset *sysoff = NULL;
++ struct ptp_pin_desc pd;
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ struct ptp_clock_info *ops = ptp->info;
+ struct ptp_clock_time *pct;
+ struct timespec ts;
+ int enable, err = 0;
+- unsigned int i;
++ unsigned int i, pin_index;
+
+ switch (cmd) {
+
+@@ -51,6 +142,7 @@
+ caps.n_ext_ts = ptp->info->n_ext_ts;
+ caps.n_per_out = ptp->info->n_per_out;
+ caps.pps = ptp->info->pps;
++ caps.n_pins = ptp->info->n_pins;
+ if (copy_to_user((void __user *)arg, &caps, sizeof(caps)))
+ err = -EFAULT;
+ break;
+@@ -126,6 +218,40 @@
+ err = -EFAULT;
+ break;
+
++ case PTP_PIN_GETFUNC:
++ if (copy_from_user(&pd, (void __user *)arg, sizeof(pd))) {
++ err = -EFAULT;
++ break;
++ }
++ pin_index = pd.index;
++ if (pin_index >= ops->n_pins) {
++ err = -EINVAL;
++ break;
++ }
++ if (mutex_lock_interruptible(&ptp->pincfg_mux))
++ return -ERESTARTSYS;
++ pd = ops->pin_config[pin_index];
++ mutex_unlock(&ptp->pincfg_mux);
++ if (!err && copy_to_user((void __user *)arg, &pd, sizeof(pd)))
++ err = -EFAULT;
++ break;
++
++ case PTP_PIN_SETFUNC:
++ if (copy_from_user(&pd, (void __user *)arg, sizeof(pd))) {
++ err = -EFAULT;
++ break;
++ }
++ pin_index = pd.index;
++ if (pin_index >= ops->n_pins) {
++ err = -EINVAL;
++ break;
++ }
++ if (mutex_lock_interruptible(&ptp->pincfg_mux))
++ return -ERESTARTSYS;
++ err = ptp_set_pinfunc(ptp, pin_index, pd.func, pd.chan);
++ mutex_unlock(&ptp->pincfg_mux);
++ break;
++
+ default:
+ err = -ENOTTY;
+ break;
+diff -Nur linux-3.14.72.orig/drivers/ptp/ptp_clock.c linux-3.14.72/drivers/ptp/ptp_clock.c
+--- linux-3.14.72.orig/drivers/ptp/ptp_clock.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ptp/ptp_clock.c 2016-06-19 22:11:55.309139744 +0200
+@@ -169,6 +169,7 @@
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+
+ mutex_destroy(&ptp->tsevq_mux);
++ mutex_destroy(&ptp->pincfg_mux);
+ ida_simple_remove(&ptp_clocks_map, ptp->index);
+ kfree(ptp);
+ }
+@@ -203,6 +204,7 @@
+ ptp->index = index;
+ spin_lock_init(&ptp->tsevq.lock);
+ mutex_init(&ptp->tsevq_mux);
++ mutex_init(&ptp->pincfg_mux);
+ init_waitqueue_head(&ptp->tsev_wq);
+
+ /* Create a new device in our class. */
+@@ -249,6 +251,7 @@
+ device_destroy(ptp_class, ptp->devid);
+ no_device:
+ mutex_destroy(&ptp->tsevq_mux);
++ mutex_destroy(&ptp->pincfg_mux);
+ no_slot:
+ kfree(ptp);
+ no_memory:
+@@ -305,6 +308,26 @@
+ }
+ EXPORT_SYMBOL(ptp_clock_index);
+
++int ptp_find_pin(struct ptp_clock *ptp,
++ enum ptp_pin_function func, unsigned int chan)
++{
++ struct ptp_pin_desc *pin = NULL;
++ int i;
++
++ mutex_lock(&ptp->pincfg_mux);
++ for (i = 0; i < ptp->info->n_pins; i++) {
++ if (ptp->info->pin_config[i].func == func &&
++ ptp->info->pin_config[i].chan == chan) {
++ pin = &ptp->info->pin_config[i];
++ break;
++ }
++ }
++ mutex_unlock(&ptp->pincfg_mux);
++
++ return pin ? i : -1;
++}
++EXPORT_SYMBOL(ptp_find_pin);
++
+ /* module operations */
+
+ static void __exit ptp_exit(void)
+diff -Nur linux-3.14.72.orig/drivers/ptp/ptp_ixp46x.c linux-3.14.72/drivers/ptp/ptp_ixp46x.c
+--- linux-3.14.72.orig/drivers/ptp/ptp_ixp46x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ptp/ptp_ixp46x.c 2016-06-19 22:11:55.309139744 +0200
+@@ -244,6 +244,7 @@
+ .name = "IXP46X timer",
+ .max_adj = 66666655,
+ .n_ext_ts = N_EXT_TS,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = ptp_ixp_adjfreq,
+ .adjtime = ptp_ixp_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/ptp/ptp_pch.c linux-3.14.72/drivers/ptp/ptp_pch.c
+--- linux-3.14.72.orig/drivers/ptp/ptp_pch.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ptp/ptp_pch.c 2016-06-19 22:11:55.309139744 +0200
+@@ -514,6 +514,7 @@
+ .name = "PCH timer",
+ .max_adj = 50000000,
+ .n_ext_ts = N_EXT_TS,
++ .n_pins = 0,
+ .pps = 0,
+ .adjfreq = ptp_pch_adjfreq,
+ .adjtime = ptp_pch_adjtime,
+diff -Nur linux-3.14.72.orig/drivers/ptp/ptp_private.h linux-3.14.72/drivers/ptp/ptp_private.h
+--- linux-3.14.72.orig/drivers/ptp/ptp_private.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/ptp/ptp_private.h 2016-06-19 22:11:55.309139744 +0200
+@@ -48,6 +48,7 @@
+ long dialed_frequency; /* remembers the frequency adjustment */
+ struct timestamp_event_queue tsevq; /* simple fifo for time stamps */
+ struct mutex tsevq_mux; /* one process at a time reading the fifo */
++ struct mutex pincfg_mux; /* protect concurrent info->pin_config access */
+ wait_queue_head_t tsev_wq;
+ int defunct; /* tells readers to go away when clock is being removed */
+ };
+@@ -69,6 +70,10 @@
+ * see ptp_chardev.c
+ */
+
++/* caller must hold pincfg_mux */
++int ptp_set_pinfunc(struct ptp_clock *ptp, unsigned int pin,
++ enum ptp_pin_function func, unsigned int chan);
++
+ long ptp_ioctl(struct posix_clock *pc,
+ unsigned int cmd, unsigned long arg);
+
+diff -Nur linux-3.14.72.orig/drivers/pwm/pwm-imx.c linux-3.14.72/drivers/pwm/pwm-imx.c
+--- linux-3.14.72.orig/drivers/pwm/pwm-imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/pwm/pwm-imx.c 2016-06-19 22:11:55.309139744 +0200
+@@ -14,6 +14,7 @@
+ #include <linux/slab.h>
+ #include <linux/err.h>
+ #include <linux/clk.h>
++#include <linux/delay.h>
+ #include <linux/io.h>
+ #include <linux/pwm.h>
+ #include <linux/of.h>
+@@ -21,24 +22,30 @@
+
+ /* i.MX1 and i.MX21 share the same PWM function block: */
+
+-#define MX1_PWMC 0x00 /* PWM Control Register */
+-#define MX1_PWMS 0x04 /* PWM Sample Register */
+-#define MX1_PWMP 0x08 /* PWM Period Register */
++#define MX1_PWMC 0x00 /* PWM Control Register */
++#define MX1_PWMS 0x04 /* PWM Sample Register */
++#define MX1_PWMP 0x08 /* PWM Period Register */
+
+-#define MX1_PWMC_EN (1 << 4)
++#define MX1_PWMC_EN (1 << 4)
+
+ /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
+
+-#define MX3_PWMCR 0x00 /* PWM Control Register */
+-#define MX3_PWMSAR 0x0C /* PWM Sample Register */
+-#define MX3_PWMPR 0x10 /* PWM Period Register */
+-#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+-#define MX3_PWMCR_DOZEEN (1 << 24)
+-#define MX3_PWMCR_WAITEN (1 << 23)
++#define MX3_PWMCR 0x00 /* PWM Control Register */
++#define MX3_PWMSR 0x04 /* PWM Status Register */
++#define MX3_PWMSAR 0x0C /* PWM Sample Register */
++#define MX3_PWMPR 0x10 /* PWM Period Register */
++#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
++#define MX3_PWMCR_DOZEEN (1 << 24)
++#define MX3_PWMCR_WAITEN (1 << 23)
+ #define MX3_PWMCR_DBGEN (1 << 22)
+-#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+-#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
+-#define MX3_PWMCR_EN (1 << 0)
++#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
++#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
++#define MX3_PWMCR_SWR (1 << 3)
++#define MX3_PWMCR_EN (1 << 0)
++#define MX3_PWMSR_FIFOAV_4WORDS 0x4
++#define MX3_PWMSR_FIFOAV_MASK 0x7
++
++#define MX3_PWM_SWR_LOOP 5
+
+ struct imx_chip {
+ struct clk *clk_per;
+@@ -103,9 +110,43 @@
+ struct pwm_device *pwm, int duty_ns, int period_ns)
+ {
+ struct imx_chip *imx = to_imx_chip(chip);
++ struct device *dev = chip->dev;
+ unsigned long long c;
+ unsigned long period_cycles, duty_cycles, prescale;
+- u32 cr;
++ unsigned int period_ms;
++ bool enable = test_bit(PWMF_ENABLED, &pwm->flags);
++ int wait_count = 0, fifoav;
++ u32 cr, sr;
++
++ /*
++ * i.MX PWMv2 has a 4-word sample FIFO.
++ * In order to avoid FIFO overflow issue, we do software reset
++ * to clear all sample FIFO if the controller is disabled or
++ * wait for a full PWM cycle to get a relinquished FIFO slot
++ * when the controller is enabled and the FIFO is fully loaded.
++ */
++ if (enable) {
++ sr = readl(imx->mmio_base + MX3_PWMSR);
++ fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
++ if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
++ period_ms = DIV_ROUND_UP(pwm->period, NSEC_PER_MSEC);
++ msleep(period_ms);
++
++ sr = readl(imx->mmio_base + MX3_PWMSR);
++ if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
++ dev_warn(dev, "there is no free FIFO slot\n");
++ }
++ } else {
++ writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
++ do {
++ usleep_range(200, 1000);
++ cr = readl(imx->mmio_base + MX3_PWMCR);
++ } while ((cr & MX3_PWMCR_SWR) &&
++ (wait_count++ < MX3_PWM_SWR_LOOP));
++
++ if (cr & MX3_PWMCR_SWR)
++ dev_warn(dev, "software reset timeout\n");
++ }
+
+ c = clk_get_rate(imx->clk_per);
+ c = c * period_ns;
+@@ -135,7 +176,7 @@
+ MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
+ MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
+
+- if (test_bit(PWMF_ENABLED, &pwm->flags))
++ if (enable)
+ cr |= MX3_PWMCR_EN;
+
+ writel(cr, imx->mmio_base + MX3_PWMCR);
+@@ -264,6 +305,7 @@
+ imx->chip.dev = &pdev->dev;
+ imx->chip.base = -1;
+ imx->chip.npwm = 1;
++ imx->chip.can_sleep = true;
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
+diff -Nur linux-3.14.72.orig/drivers/regulator/anatop-regulator.c linux-3.14.72/drivers/regulator/anatop-regulator.c
+--- linux-3.14.72.orig/drivers/regulator/anatop-regulator.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/regulator/anatop-regulator.c 2016-06-19 22:11:55.309139744 +0200
+@@ -34,6 +34,9 @@
+ #define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
+ #define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
+
++#define LDO_POWER_GATE 0x00
++#define LDO_FET_FULL_ON 0x1f
++
+ struct anatop_regulator {
+ const char *name;
+ u32 control_reg;
+@@ -48,18 +51,12 @@
+ int max_voltage;
+ struct regulator_desc rdesc;
+ struct regulator_init_data *initdata;
++ bool bypass;
++ int sel;
+ };
+
+-static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg,
+- unsigned selector)
+-{
+- struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+-
+- if (!anatop_reg->control_reg)
+- return -ENOTSUPP;
+-
+- return regulator_set_voltage_sel_regmap(reg, selector);
+-}
++static struct anatop_regulator *vddpu;
++static struct anatop_regulator *vddsoc;
+
+ static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
+ unsigned int old_sel,
+@@ -87,22 +84,106 @@
+ return ret;
+ }
+
+-static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
++static int anatop_regmap_enable(struct regulator_dev *reg)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++ int sel;
++
++ /*
++ * The vddpu has to stay at the same voltage level as vddsoc
++ * whenever it's about to be enabled.
++ */
++ if (anatop_reg == vddpu && vddsoc)
++ anatop_reg->sel = vddsoc->sel;
++
++ sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
++ return regulator_set_voltage_sel_regmap(reg, sel);
++}
++
++static int anatop_regmap_disable(struct regulator_dev *reg)
++{
++ return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
++}
++
++static int anatop_regmap_is_enabled(struct regulator_dev *reg)
++{
++ return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
++}
++
++static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
++ unsigned selector)
+ {
+ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++ int ret;
+
+- if (!anatop_reg->control_reg)
+- return -ENOTSUPP;
++ if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
++ anatop_reg->sel = selector;
++ return 0;
++ }
++
++ ret = regulator_set_voltage_sel_regmap(reg, selector);
++ if (!ret)
++ anatop_reg->sel = selector;
++ return ret;
++}
++
++static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++
++ if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
++ return anatop_reg->sel;
+
+ return regulator_get_voltage_sel_regmap(reg);
+ }
+
++static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++ int sel;
++
++ sel = regulator_get_voltage_sel_regmap(reg);
++ if (sel == LDO_FET_FULL_ON)
++ WARN_ON(!anatop_reg->bypass);
++ else if (sel != LDO_POWER_GATE)
++ WARN_ON(anatop_reg->bypass);
++
++ *enable = anatop_reg->bypass;
++ return 0;
++}
++
++static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
++{
++ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
++ int sel;
++
++ if (enable == anatop_reg->bypass)
++ return 0;
++
++ sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
++ anatop_reg->bypass = enable;
++
++ return regulator_set_voltage_sel_regmap(reg, sel);
++}
++
+ static struct regulator_ops anatop_rops = {
+- .set_voltage_sel = anatop_regmap_set_voltage_sel,
++ .set_voltage_sel = regulator_set_voltage_sel_regmap,
++ .get_voltage_sel = regulator_get_voltage_sel_regmap,
++ .list_voltage = regulator_list_voltage_linear,
++ .map_voltage = regulator_map_voltage_linear,
++};
++
++static struct regulator_ops anatop_core_rops = {
++ .enable = anatop_regmap_enable,
++ .disable = anatop_regmap_disable,
++ .is_enabled = anatop_regmap_is_enabled,
++ .set_voltage_sel = anatop_regmap_core_set_voltage_sel,
+ .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
+- .get_voltage_sel = anatop_regmap_get_voltage_sel,
++ .get_voltage_sel = anatop_regmap_core_get_voltage_sel,
+ .list_voltage = regulator_list_voltage_linear,
+ .map_voltage = regulator_map_voltage_linear,
++ .get_bypass = anatop_regmap_get_bypass,
++ .set_bypass = anatop_regmap_set_bypass,
+ };
+
+ static int anatop_regulator_probe(struct platform_device *pdev)
+@@ -116,6 +197,7 @@
+ struct regulator_init_data *initdata;
+ struct regulator_config config = { };
+ int ret = 0;
++ u32 val;
+
+ initdata = of_get_regulator_init_data(dev, np);
+ sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
+@@ -125,10 +207,14 @@
+ sreg->name = of_get_property(np, "regulator-name", NULL);
+ rdesc = &sreg->rdesc;
+ rdesc->name = sreg->name;
+- rdesc->ops = &anatop_rops;
+ rdesc->type = REGULATOR_VOLTAGE;
+ rdesc->owner = THIS_MODULE;
+
++ if (strcmp(sreg->name, "vddpu") == 0)
++ vddpu = sreg;
++ else if (strcmp(sreg->name, "vddsoc") == 0)
++ vddsoc = sreg;
++
+ anatop_np = of_get_parent(np);
+ if (!anatop_np)
+ return -ENODEV;
+@@ -197,6 +283,25 @@
+ config.of_node = pdev->dev.of_node;
+ config.regmap = sreg->anatop;
+
++ /* Only core regulators have the ramp up delay configuration. */
++ if (sreg->control_reg && sreg->delay_bit_width) {
++ rdesc->ops = &anatop_core_rops;
++
++ ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
++ if (ret) {
++ dev_err(dev, "failed to read initial state\n");
++ return ret;
++ }
++
++ sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
++ if (sreg->sel == LDO_FET_FULL_ON) {
++ sreg->sel = 0;
++ sreg->bypass = true;
++ }
++ } else {
++ rdesc->ops = &anatop_rops;
++ }
++
+ /* register regulator */
+ rdev = devm_regulator_register(dev, rdesc, &config);
+ if (IS_ERR(rdev)) {
+diff -Nur linux-3.14.72.orig/drivers/regulator/core.c linux-3.14.72/drivers/regulator/core.c
+--- linux-3.14.72.orig/drivers/regulator/core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/regulator/core.c 2016-06-19 22:11:55.309139744 +0200
+@@ -844,13 +844,22 @@
+ /* do we need to apply the constraint voltage */
+ if (rdev->constraints->apply_uV &&
+ rdev->constraints->min_uV == rdev->constraints->max_uV) {
+- ret = _regulator_do_set_voltage(rdev,
+- rdev->constraints->min_uV,
+- rdev->constraints->max_uV);
+- if (ret < 0) {
+- rdev_err(rdev, "failed to apply %duV constraint\n",
+- rdev->constraints->min_uV);
+- return ret;
++ int current_uV = _regulator_get_voltage(rdev);
++ if (current_uV < 0) {
++ rdev_err(rdev, "failed to get the current voltage\n");
++ return current_uV;
++ }
++ if (current_uV < rdev->constraints->min_uV ||
++ current_uV > rdev->constraints->max_uV) {
++ ret = _regulator_do_set_voltage(
++ rdev, rdev->constraints->min_uV,
++ rdev->constraints->max_uV);
++ if (ret < 0) {
++ rdev_err(rdev,
++ "failed to apply %duV constraint\n",
++ rdev->constraints->min_uV);
++ return ret;
++ }
+ }
+ }
+
+@@ -1752,6 +1761,7 @@
+ {
+ int ret, delay;
+
++ _notifier_call_chain(rdev, REGULATOR_EVENT_PRE_ENABLE, NULL);
+ /* Query before enabling in case configuration dependent. */
+ ret = _regulator_get_enable_time(rdev);
+ if (ret >= 0) {
+@@ -1896,6 +1906,7 @@
+ {
+ int ret;
+
++ _notifier_call_chain(rdev, REGULATOR_EVENT_PRE_DISABLE, NULL);
+ trace_regulator_disable(rdev_get_name(rdev));
+
+ if (rdev->ena_pin) {
+diff -Nur linux-3.14.72.orig/drivers/regulator/Kconfig linux-3.14.72/drivers/regulator/Kconfig
+--- linux-3.14.72.orig/drivers/regulator/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/regulator/Kconfig 2016-06-19 22:11:55.313139482 +0200
+@@ -264,6 +264,13 @@
+ This driver controls a Maxim 14577 regulator via I2C bus.
+ The regulators include safeout LDO and current regulator 'CHARGER'.
+
++config REGULATOR_LTC3676
++ tristate "LTC3676 regulator driver"
++ depends on I2C
++ select REGMAP_I2C
++ help
++ Say y here to support for the LTC3676 regulators controlled via I2C.
++
+ config REGULATOR_MAX1586
+ tristate "Maxim 1586/1587 voltage regulator"
+ depends on I2C
+@@ -272,6 +279,10 @@
+ regulator via I2C bus. The provided regulator is suitable
+ for PXA27x chips to control VCC_CORE and VCC_USIM voltages.
+
++config REGULATOR_MAX17135
++ tristate "Maxim MAX17135 Regulator Support"
++ depends on MFD_MAX17135
++
+ config REGULATOR_MAX8649
+ tristate "Maxim 8649 voltage regulator"
+ depends on I2C
+@@ -399,12 +410,12 @@
+ on PCF50633
+
+ config REGULATOR_PFUZE100
+- tristate "Freescale PFUZE100 regulator driver"
++ tristate "Freescale PFUZE100/PFUZE200 regulator driver"
+ depends on I2C
+ select REGMAP_I2C
+ help
+- Say y here to support the regulators found on the Freescale PFUZE100
+- PMIC.
++ Say y here to support the regulators found on the Freescale
++ PFUZE100/PFUZE200 PMIC.
+
+ config REGULATOR_RC5T583
+ tristate "RICOH RC5T583 Power regulators"
+diff -Nur linux-3.14.72.orig/drivers/regulator/ltc3676.c linux-3.14.72/drivers/regulator/ltc3676.c
+--- linux-3.14.72.orig/drivers/regulator/ltc3676.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/regulator/ltc3676.c 2016-06-19 22:11:55.313139482 +0200
+@@ -0,0 +1,497 @@
++/*
++ * Copyright (C) 2014 Gateworks Corporation, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/of.h>
++#include <linux/regmap.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/of_regulator.h>
++
++#define DRIVER_NAME "ltc3676"
++
++/* LTC3676 Registers */
++#define LTC3676_BUCK1 0x01
++#define LTC3676_BUCK2 0x02
++#define LTC3676_BUCK3 0x03
++#define LTC3676_BUCK4 0x04
++#define LTC3676_LDOA 0x05
++#define LTC3676_LDOB 0x06
++#define LTC3676_SQD1 0x07
++#define LTC3676_SQD2 0x08
++#define LTC3676_CNTRL 0x09
++#define LTC3676_DVB1A 0x0A
++#define LTC3676_DVB1B 0x0B
++#define LTC3676_DVB2A 0x0C
++#define LTC3676_DVB2B 0x0D
++#define LTC3676_DVB3A 0x0E
++#define LTC3676_DVB3B 0x0F
++#define LTC3676_DVB4A 0x10
++#define LTC3676_DVB4B 0x11
++#define LTC3676_MSKIRQ 0x12
++#define LTC3676_MSKPG 0x13
++#define LTC3676_USER 0x14
++#define LTC3676_IRQSTAT 0x15
++#define LTC3676_PGSTATL 0x16
++#define LTC3676_PGSTATRT 0x17
++#define LTC3676_HRST 0x1E
++#define LTC3676_CLIRQ 0x1F
++
++#define LTC3676_IRQSTAT_PGOOD_TIMEOUT BIT(3)
++#define LTC3676_IRQSTAT_UNDERVOLT_WARN BIT(4)
++#define LTC3676_IRQSTAT_UNDERVOLT_FAULT BIT(5)
++#define LTC3676_IRQSTAT_THERMAL_WARN BIT(6)
++#define LTC3676_IRQSTAT_THERMAL_FAULT BIT(7)
++
++enum ltc3676_reg {
++ LTC3676_SW1,
++ LTC3676_SW2,
++ LTC3676_SW3,
++ LTC3676_SW4,
++ LTC3676_LDO1,
++ LTC3676_LDO2,
++ LTC3676_LDO3,
++ LTC3676_LDO4,
++ LTC3676_NUM_REGULATORS,
++};
++
++struct ltc3676_regulator {
++ struct regulator_desc desc;
++ struct device_node *np;
++
++ /* External feedback voltage divider */
++ unsigned int r1;
++ unsigned int r2;
++};
++
++struct ltc3676 {
++ struct regmap *regmap;
++ struct device *dev;
++ struct ltc3676_regulator regulator_descs[LTC3676_NUM_REGULATORS];
++ struct regulator_dev *regulators[LTC3676_NUM_REGULATORS];
++};
++
++static int ltc3676_set_suspend_voltage(struct regulator_dev *rdev, int uV)
++{
++ struct ltc3676 *ltc3676 = rdev_get_drvdata(rdev);
++ struct device *dev = ltc3676->dev;
++ int dcdc = rdev_get_id(rdev);
++ int sel;
++
++ dev_dbg(dev, "%s id=%d uV=%d\n", __func__, dcdc, uV);
++ sel = regulator_map_voltage_linear(rdev, uV, uV);
++ if (sel < 0)
++ return sel;
++
++ /* DVBB register follows right after the corresponding DVBA register */
++ return regmap_update_bits(ltc3676->regmap, rdev->desc->vsel_reg + 1,
++ rdev->desc->vsel_mask, sel);
++}
++
++static int ltc3676_set_suspend_mode(struct regulator_dev *rdev,
++ unsigned int mode)
++{
++ struct ltc3676 *ltc3676= rdev_get_drvdata(rdev);
++ struct device *dev = ltc3676->dev;
++ int mask, bit = 0;
++ int dcdc = rdev_get_id(rdev);
++
++ dev_dbg(dev, "%s id=%d mode=%d\n", __func__, dcdc, mode);
++
++ /* DVB reference select is bit5 of DVBA reg */
++ mask = 1 << 5;
++
++ if (mode != REGULATOR_MODE_STANDBY)
++ bit = mask; /* Select DVBB */
++
++ return regmap_update_bits(ltc3676->regmap, rdev->desc->vsel_reg,
++ mask, bit);
++}
++
++/* SW1, SW2, SW3, SW4 linear 0.8V-3.3V with scalar via R1/R2 feeback res */
++static struct regulator_ops ltc3676_linear_regulator_ops =
++{
++ .enable = regulator_enable_regmap,
++ .disable = regulator_disable_regmap,
++ .is_enabled = regulator_is_enabled_regmap,
++ .list_voltage = regulator_list_voltage_linear,
++ .set_voltage_sel = regulator_set_voltage_sel_regmap,
++ .get_voltage_sel = regulator_get_voltage_sel_regmap,
++ .set_suspend_voltage = ltc3676_set_suspend_voltage,
++ .set_suspend_mode = ltc3676_set_suspend_mode,
++};
++
++/* always on fixed regulators */
++static struct regulator_ops ltc3676_fixed_standby_regulator_ops = {
++};
++
++#define LTC3676_REG(_name, _ops, en_reg, en_bit, dvba_reg, dvb_mask) \
++ [LTC3676_ ## _name] = { \
++ .desc = { \
++ .name = #_name, \
++ .n_voltages = (dvb_mask) + 1, \
++ .min_uV = (dvba_reg) ? 412500 : 0, \
++ .uV_step = (dvba_reg) ? 12500 : 0, \
++ .ramp_delay = (dvba_reg) ? 800 : 0, \
++ .fixed_uV = (dvb_mask) ? 0 : 725000, \
++ .ops = &ltc3676_ ## _ops ## _regulator_ops, \
++ .type = REGULATOR_VOLTAGE, \
++ .id = LTC3676_ ## _name, \
++ .owner = THIS_MODULE, \
++ .vsel_reg = (dvba_reg), \
++ .vsel_mask = (dvb_mask), \
++ .enable_reg = (en_reg), \
++ .enable_mask = (1 << en_bit), \
++ }, \
++ }
++
++#define LTC3676_LINEAR_REG(_name, _en, _dvba) \
++ LTC3676_REG(_name, linear, \
++ LTC3676_ ## _en, 7, \
++ LTC3676_ ## _dvba, 0x1f)
++
++#define LTC3676_FIXED_REG(_name) \
++ LTC3676_REG(_name, fixed_standby, 0, 0, 0, 0)
++
++static struct ltc3676_regulator ltc3676_regulators[LTC3676_NUM_REGULATORS] = {
++ LTC3676_LINEAR_REG(SW1, BUCK1, DVB1A),
++ LTC3676_LINEAR_REG(SW2, BUCK2, DVB2A),
++ LTC3676_LINEAR_REG(SW3, BUCK3, DVB3A),
++ LTC3676_LINEAR_REG(SW4, BUCK4, DVB4A),
++ LTC3676_FIXED_REG(LDO1),
++ LTC3676_FIXED_REG(LDO2),
++ LTC3676_FIXED_REG(LDO3),
++ LTC3676_FIXED_REG(LDO4),
++};
++
++#ifdef CONFIG_OF
++static struct of_regulator_match ltc3676_matches[] = {
++ { .name = "sw1", },
++ { .name = "sw2", },
++ { .name = "sw3", },
++ { .name = "sw4", },
++ { .name = "ldo1", },
++ { .name = "ldo2", },
++ { .name = "ldo3", },
++ { .name = "ldo4", },
++};
++
++static int ltc3676_parse_regulators_dt(struct ltc3676 *ltc3676)
++{
++ struct device *dev = ltc3676->dev;
++ struct device_node *node;
++ int i, ret;
++
++ node = of_find_node_by_name(dev->of_node, "regulators");
++ if (!node) {
++ dev_err(dev, "regulators node not found\n");
++ return -EINVAL;
++ }
++
++ ret = of_regulator_match(dev, node, ltc3676_matches,
++ ARRAY_SIZE(ltc3676_matches));
++ of_node_put(node);
++ if (ret < 0) {
++ dev_err(dev, "Error parsing regulator init data: %d\n", ret);
++ return -EINVAL;
++ }
++
++ /* parse feedback voltage deviders: LDO3 doesn't have them */
++ for (i = 0; i < LTC3676_NUM_REGULATORS; i++) {
++ struct ltc3676_regulator *rdesc = &ltc3676->regulator_descs[i];
++ struct device_node *np = ltc3676_matches[i].of_node;
++ u32 vdiv[2];
++
++ rdesc->np = ltc3676_matches[i].of_node;
++ if (i == LTC3676_LDO3 || !rdesc->np)
++ continue;
++ ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider",
++ vdiv, 2);
++ if (ret) {
++ dev_err(dev, "Failed to parse voltage divider: %d\n",
++ ret);
++ return ret;
++ }
++
++ rdesc->r1 = vdiv[0];
++ rdesc->r2 = vdiv[1];
++ }
++
++ return 0;
++}
++
++static inline struct regulator_init_data *match_init_data(int index)
++{
++ return ltc3676_matches[index].init_data;
++}
++
++static inline struct device_node *match_of_node(int index)
++{
++ return ltc3676_matches[index].of_node;
++}
++#else
++static int ltc3676_parse_regulators_dt(struct ltc3676_chip *chip)
++{
++ return 0;
++}
++
++static inline struct regulator_init_data *match_init_data(int index)
++{
++ return NULL;
++}
++
++static inline struct device_node *match_of_node(int index)
++{
++ return NULL;
++}
++#endif
++
++static bool ltc3676_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case LTC3676_IRQSTAT:
++ case LTC3676_BUCK1:
++ case LTC3676_BUCK2:
++ case LTC3676_BUCK3:
++ case LTC3676_BUCK4:
++ case LTC3676_LDOA:
++ case LTC3676_LDOB:
++ case LTC3676_SQD1:
++ case LTC3676_SQD2:
++ case LTC3676_CNTRL:
++ case LTC3676_DVB1A:
++ case LTC3676_DVB1B:
++ case LTC3676_DVB2A:
++ case LTC3676_DVB2B:
++ case LTC3676_DVB3A:
++ case LTC3676_DVB3B:
++ case LTC3676_DVB4A:
++ case LTC3676_DVB4B:
++ case LTC3676_MSKIRQ:
++ case LTC3676_MSKPG:
++ case LTC3676_USER:
++ case LTC3676_HRST:
++ case LTC3676_CLIRQ:
++ return true;
++ }
++ return false;
++}
++
++static bool ltc3676_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case LTC3676_IRQSTAT:
++ case LTC3676_BUCK1:
++ case LTC3676_BUCK2:
++ case LTC3676_BUCK3:
++ case LTC3676_BUCK4:
++ case LTC3676_LDOA:
++ case LTC3676_LDOB:
++ case LTC3676_SQD1:
++ case LTC3676_SQD2:
++ case LTC3676_CNTRL:
++ case LTC3676_DVB1A:
++ case LTC3676_DVB1B:
++ case LTC3676_DVB2A:
++ case LTC3676_DVB2B:
++ case LTC3676_DVB3A:
++ case LTC3676_DVB3B:
++ case LTC3676_DVB4A:
++ case LTC3676_DVB4B:
++ case LTC3676_MSKIRQ:
++ case LTC3676_MSKPG:
++ case LTC3676_USER:
++ case LTC3676_HRST:
++ case LTC3676_CLIRQ:
++ return true;
++ }
++ return false;
++}
++
++static bool ltc3676_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case LTC3676_IRQSTAT:
++ case LTC3676_PGSTATL:
++ case LTC3676_PGSTATRT:
++ return true;
++ }
++ return false;
++}
++
++static const struct regmap_config ltc3676_regmap_config = {
++ .reg_bits = 8,
++ .val_bits = 8,
++ .writeable_reg = ltc3676_writeable_reg,
++ .readable_reg = ltc3676_readable_reg,
++ .volatile_reg = ltc3676_volatile_reg,
++ .max_register = LTC3676_CLIRQ,
++ .use_single_rw = true,
++ .cache_type = REGCACHE_RBTREE,
++};
++
++static irqreturn_t ltc3676_isr(int irq, void *dev_id)
++{
++ struct ltc3676 *ltc3676 = dev_id;
++ struct device *dev = ltc3676->dev;
++ unsigned int i, irqstat, event;
++
++ regmap_read(ltc3676->regmap, LTC3676_IRQSTAT, &irqstat);
++
++ dev_dbg(dev, "irq%d irqstat=0x%02x\n", irq, irqstat);
++ if (irqstat & LTC3676_IRQSTAT_THERMAL_WARN) {
++ dev_info(dev, "Over-temperature Warning\n");
++ event = REGULATOR_EVENT_OVER_TEMP;
++ for (i = 0; i < LTC3676_NUM_REGULATORS; i++)
++ regulator_notifier_call_chain(ltc3676->regulators[i],
++ event, NULL);
++ }
++
++ if (irqstat & LTC3676_IRQSTAT_UNDERVOLT_WARN) {
++ dev_info(dev, "Undervoltage Warning\n");
++ event = REGULATOR_EVENT_UNDER_VOLTAGE;
++ for (i = 0; i < LTC3676_NUM_REGULATORS; i++)
++ regulator_notifier_call_chain(ltc3676->regulators[i],
++ event, NULL);
++ }
++
++ /* Clear warning condition */
++ regmap_write(ltc3676->regmap, LTC3676_CLIRQ, 0);
++
++ return IRQ_HANDLED;
++}
++
++static inline unsigned int ltc3676_scale(unsigned int uV, u32 r1, u32 r2)
++{
++ uint64_t tmp;
++ if (uV == 0)
++ return 0;
++ tmp = (uint64_t)uV * r1;
++ do_div(tmp, r2);
++ return uV + (unsigned int)tmp;
++}
++
++static void ltc3676_apply_fb_voltage_divider(struct ltc3676_regulator *rdesc)
++{
++ struct regulator_desc *desc = &rdesc->desc;
++
++ if (!rdesc->r1 || !rdesc->r2)
++ return;
++
++ desc->min_uV = ltc3676_scale(desc->min_uV, rdesc->r1, rdesc->r2);
++ desc->uV_step = ltc3676_scale(desc->uV_step, rdesc->r1, rdesc->r2);
++ desc->fixed_uV = ltc3676_scale(desc->fixed_uV, rdesc->r1, rdesc->r2);
++}
++
++static int ltc3676_regulator_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct device *dev = &client->dev;
++ struct ltc3676_regulator *descs;
++ struct ltc3676 *ltc3676;
++ int i, ret;
++
++ ltc3676 = devm_kzalloc(dev, sizeof(*ltc3676), GFP_KERNEL);
++ if (!ltc3676)
++ return -ENOMEM;
++
++ i2c_set_clientdata(client, ltc3676);
++ ltc3676->dev = dev;
++
++ descs = ltc3676->regulator_descs;
++ memcpy(descs, ltc3676_regulators, sizeof(ltc3676_regulators));
++ descs[LTC3676_LDO3].desc.fixed_uV = 1800000;
++
++ ltc3676->regmap = devm_regmap_init_i2c(client, &ltc3676_regmap_config);
++ if (IS_ERR(ltc3676->regmap)) {
++ ret = PTR_ERR(ltc3676->regmap);
++ dev_err(dev, "failed to initialize regmap: %d\n", ret);
++ return ret;
++ }
++
++ ret = ltc3676_parse_regulators_dt(ltc3676);
++ if (ret)
++ return ret;
++
++ for (i = 0; i < LTC3676_NUM_REGULATORS; i++) {
++ struct ltc3676_regulator *rdesc = &ltc3676->regulator_descs[i];
++ struct regulator_desc *desc = &rdesc->desc;
++ struct regulator_init_data *init_data;
++ struct regulator_config config = { };
++
++ init_data = match_init_data(i);
++
++ if (!rdesc->np)
++ continue;
++
++ if (i != LTC3676_LDO3) {
++ /* skip unused (defined by r1=r2=0) */
++ if (rdesc->r1 == 0 && rdesc->r2 == 0)
++ continue;
++ ltc3676_apply_fb_voltage_divider(rdesc);
++ }
++
++ config.dev = dev;
++ config.init_data = init_data;
++ config.driver_data = ltc3676;
++ config.of_node = match_of_node(i);
++
++ ltc3676->regulators[i] = regulator_register(desc, &config);
++ if (IS_ERR(ltc3676->regulators[i])) {
++ ret = PTR_ERR(ltc3676->regulators[i]);
++ dev_err(dev, "failed to register regulator %s: %d\n",
++ desc->name, ret);
++ return ret;
++ }
++ }
++
++ regmap_write(ltc3676->regmap, LTC3676_CLIRQ, 0);
++ ret = devm_request_threaded_irq(dev, client->irq, NULL, ltc3676_isr,
++ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
++ client->name, ltc3676);
++ if (ret) {
++ dev_err(dev, "Failed to request IRQ: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static const struct i2c_device_id ltc3676_i2c_id[] = {
++ { "ltc3676" },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, ltc3676_i2c_id);
++
++static struct i2c_driver ltc3676_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ },
++ .probe = ltc3676_regulator_probe,
++ .id_table = ltc3676_i2c_id,
++};
++module_i2c_driver(ltc3676_driver);
++
++MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
++MODULE_DESCRIPTION("Regulator Driver for Linear Technology LTC1376");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("i2c:ltc3676");
+diff -Nur linux-3.14.72.orig/drivers/regulator/Makefile linux-3.14.72/drivers/regulator/Makefile
+--- linux-3.14.72.orig/drivers/regulator/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/regulator/Makefile 2016-06-19 22:11:55.313139482 +0200
+@@ -37,7 +37,9 @@
+ obj-$(CONFIG_REGULATOR_LP8788) += lp8788-ldo.o
+ obj-$(CONFIG_REGULATOR_LP8755) += lp8755.o
+ obj-$(CONFIG_REGULATOR_MAX14577) += max14577.o
++obj-$(CONFIG_REGULATOR_LTC3676) += ltc3676.o
+ obj-$(CONFIG_REGULATOR_MAX1586) += max1586.o
++obj-$(CONFIG_REGULATOR_MAX17135) += max17135-regulator.o
+ obj-$(CONFIG_REGULATOR_MAX8649) += max8649.o
+ obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
+ obj-$(CONFIG_REGULATOR_MAX8907) += max8907-regulator.o
+diff -Nur linux-3.14.72.orig/drivers/regulator/max17135-regulator.c linux-3.14.72/drivers/regulator/max17135-regulator.c
+--- linux-3.14.72.orig/drivers/regulator/max17135-regulator.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/regulator/max17135-regulator.c 2016-06-19 22:11:55.313139482 +0200
+@@ -0,0 +1,838 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/slab.h>
++#include <linux/i2c.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/machine.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/mfd/max17135.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++
++/*
++ * Regulator definitions
++ * *_MIN_uV - minimum microvolt for regulator
++ * *_MAX_uV - maximum microvolt for regulator
++ * *_STEP_uV - microvolts between regulator output levels
++ * *_MIN_VAL - minimum register field value for regulator
++ * *_MAX_VAL - maximum register field value for regulator
++ */
++#define MAX17135_HVINP_MIN_uV 5000000
++#define MAX17135_HVINP_MAX_uV 20000000
++#define MAX17135_HVINP_STEP_uV 1000000
++#define MAX17135_HVINP_MIN_VAL 0
++#define MAX17135_HVINP_MAX_VAL 12
++
++#define MAX17135_HVINN_MIN_uV 5000000
++#define MAX17135_HVINN_MAX_uV 20000000
++#define MAX17135_HVINN_STEP_uV 1000000
++#define MAX17135_HVINN_MIN_VAL 0
++#define MAX17135_HVINN_MAX_VAL 1
++
++#define MAX17135_GVDD_MIN_uV 5000000
++#define MAX17135_GVDD_MAX_uV 20000000
++#define MAX17135_GVDD_STEP_uV 1000000
++#define MAX17135_GVDD_MIN_VAL 0
++#define MAX17135_GVDD_MAX_VAL 1
++
++#define MAX17135_GVEE_MIN_uV 5000000
++#define MAX17135_GVEE_MAX_uV 20000000
++#define MAX17135_GVEE_STEP_uV 1000000
++#define MAX17135_GVEE_MIN_VAL 0
++#define MAX17135_GVEE_MAX_VAL 1
++
++#define MAX17135_VCOM_MIN_VAL 0
++#define MAX17135_VCOM_MAX_VAL 255
++
++#define MAX17135_VNEG_MIN_uV 5000000
++#define MAX17135_VNEG_MAX_uV 20000000
++#define MAX17135_VNEG_STEP_uV 1000000
++#define MAX17135_VNEG_MIN_VAL 0
++#define MAX17135_VNEG_MAX_VAL 1
++
++#define MAX17135_VPOS_MIN_uV 5000000
++#define MAX17135_VPOS_MAX_uV 20000000
++#define MAX17135_VPOS_STEP_uV 1000000
++#define MAX17135_VPOS_MIN_VAL 0
++#define MAX17135_VPOS_MAX_VAL 1
++
++struct max17135_vcom_programming_data {
++ int vcom_min_uV;
++ int vcom_max_uV;
++ int vcom_step_uV;
++};
++
++struct max17135_data {
++ int num_regulators;
++ struct max17135 *max17135;
++ struct regulator_dev **rdev;
++};
++
++static long unsigned int max17135_pass_num = { 1 };
++static int max17135_vcom = { -1250000 };
++
++struct max17135_vcom_programming_data vcom_data[2] = {
++ {
++ -4325000,
++ -500000,
++ 15000,
++ },
++ {
++ -3050000,
++ -500000,
++ 10000,
++ },
++};
++
++static int max17135_is_power_good(struct max17135 *max17135);
++
++/*
++ * Regulator operations
++ */
++static int max17135_hvinp_set_voltage(struct regulator_dev *reg,
++ int minuV, int uV, unsigned *selector)
++{
++ unsigned int reg_val;
++ unsigned int fld_val;
++
++ if ((uV >= MAX17135_HVINP_MIN_uV) &&
++ (uV <= MAX17135_HVINP_MAX_uV))
++ fld_val = (uV - MAX17135_HVINP_MIN_uV) /
++ MAX17135_HVINP_STEP_uV;
++ else
++ return -EINVAL;
++
++ max17135_reg_read(REG_MAX17135_HVINP, &reg_val);
++
++ reg_val &= ~BITFMASK(HVINP);
++ reg_val |= BITFVAL(HVINP, fld_val); /* shift to correct bit */
++
++ return max17135_reg_write(REG_MAX17135_HVINP, reg_val);
++}
++
++static int max17135_hvinp_get_voltage(struct regulator_dev *reg)
++{
++ unsigned int reg_val;
++ unsigned int fld_val;
++ int volt;
++
++ max17135_reg_read(REG_MAX17135_HVINP, &reg_val);
++
++ fld_val = (reg_val & BITFMASK(HVINP)) >> HVINP_LSH;
++
++ if ((fld_val >= MAX17135_HVINP_MIN_VAL) &&
++ (fld_val <= MAX17135_HVINP_MAX_VAL)) {
++ volt = (fld_val * MAX17135_HVINP_STEP_uV) +
++ MAX17135_HVINP_MIN_uV;
++ } else {
++ printk(KERN_ERR "MAX17135: HVINP voltage is out of range\n");
++ volt = 0;
++ }
++ return volt;
++}
++
++static int max17135_hvinp_enable(struct regulator_dev *reg)
++{
++ return 0;
++}
++
++static int max17135_hvinp_disable(struct regulator_dev *reg)
++{
++ return 0;
++}
++
++/* Convert uV to the VCOM register bitfield setting */
++static inline int vcom_uV_to_rs(int uV, int pass_num)
++{
++ return (vcom_data[pass_num].vcom_max_uV - uV)
++ / vcom_data[pass_num].vcom_step_uV;
++}
++
++/* Convert the VCOM register bitfield setting to uV */
++static inline int vcom_rs_to_uV(int rs, int pass_num)
++{
++ return vcom_data[pass_num].vcom_max_uV
++ - (vcom_data[pass_num].vcom_step_uV * rs);
++}
++
++static int max17135_vcom_set_voltage(struct regulator_dev *reg,
++ int minuV, int uV, unsigned *selector)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ unsigned int reg_val;
++ int vcom_read;
++
++ if ((uV < vcom_data[max17135->pass_num-1].vcom_min_uV)
++ || (uV > vcom_data[max17135->pass_num-1].vcom_max_uV))
++ return -EINVAL;
++
++ max17135_reg_read(REG_MAX17135_DVR, &reg_val);
++
++ /*
++ * Only program VCOM if it is not set to the desired value.
++ * Programming VCOM excessively degrades ability to keep
++ * DVR register value persistent.
++ */
++ vcom_read = vcom_rs_to_uV(reg_val, max17135->pass_num-1);
++ if (vcom_read != max17135->vcom_uV) {
++ reg_val &= ~BITFMASK(DVR);
++ reg_val |= BITFVAL(DVR, vcom_uV_to_rs(uV,
++ max17135->pass_num-1));
++ max17135_reg_write(REG_MAX17135_DVR, reg_val);
++
++ reg_val = BITFVAL(CTRL_DVR, true); /* shift to correct bit */
++ return max17135_reg_write(REG_MAX17135_PRGM_CTRL, reg_val);
++ }
++
++ return 0;
++}
++
++static int max17135_vcom_get_voltage(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_DVR, &reg_val);
++ return vcom_rs_to_uV(BITFEXT(reg_val, DVR), max17135->pass_num-1);
++}
++
++static int max17135_vcom_enable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ /*
++ * Check to see if we need to set the VCOM voltage.
++ * Should only be done one time. And, we can
++ * only change vcom voltage if we have been enabled.
++ */
++ if (!max17135->vcom_setup && max17135_is_power_good(max17135)) {
++ max17135_vcom_set_voltage(reg,
++ max17135->vcom_uV,
++ max17135->vcom_uV,
++ NULL);
++ max17135->vcom_setup = true;
++ }
++
++ /* enable VCOM regulator output */
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 1);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(VCOM_ENABLE);
++ reg_val |= BITFVAL(VCOM_ENABLE, 1); /* shift to correct bit */
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ return 0;
++}
++
++static int max17135_vcom_disable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_vcom_ctrl, 0);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(VCOM_ENABLE);
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ return 0;
++}
++
++static int max17135_vcom_is_enabled(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ /* read VCOM regulator enable setting */
++ if (max17135->pass_num == 1) {
++ int gpio = gpio_get_value(max17135->gpio_pmic_vcom_ctrl);
++ if (gpio == 0)
++ return 0;
++ else
++ return 1;
++ } else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= BITFMASK(VCOM_ENABLE);
++ if (reg_val != 0)
++ return 1;
++ else
++ return 0;
++ }
++}
++
++static int max17135_is_power_good(struct max17135 *max17135)
++{
++ unsigned int reg_val;
++ unsigned int fld_val;
++
++ max17135_reg_read(REG_MAX17135_FAULT, &reg_val);
++ fld_val = (reg_val & BITFMASK(FAULT_POK)) >> FAULT_POK_LSH;
++
++ /* Check the POK bit */
++ return fld_val;
++}
++
++static int max17135_wait_power_good(struct max17135 *max17135)
++{
++ int i;
++
++ for (i = 0; i < max17135->max_wait * 3; i++) {
++ if (max17135_is_power_good(max17135))
++ return 0;
++
++ msleep(1);
++ }
++
++ return -ETIMEDOUT;
++}
++
++static int max17135_display_enable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ /* The Pass 1 parts cannot turn on the PMIC via I2C. */
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_wakeup, 1);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(ENABLE);
++ reg_val |= BITFVAL(ENABLE, 1);
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ return max17135_wait_power_good(max17135);
++}
++
++static int max17135_display_disable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ if (max17135->pass_num == 1)
++ gpio_set_value(max17135->gpio_pmic_wakeup, 0);
++ else {
++ unsigned int reg_val;
++
++ max17135_reg_read(REG_MAX17135_ENABLE, &reg_val);
++ reg_val &= ~BITFMASK(ENABLE);
++ max17135_reg_write(REG_MAX17135_ENABLE, reg_val);
++ }
++
++ msleep(max17135->max_wait);
++
++ return 0;
++}
++
++static int max17135_display_is_enabled(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ int gpio = gpio_get_value(max17135->gpio_pmic_wakeup);
++
++ if (gpio == 0)
++ return 0;
++ else
++ return 1;
++}
++
++static int max17135_v3p3_enable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ gpio_set_value(max17135->gpio_pmic_v3p3, 1);
++ return 0;
++}
++
++static int max17135_v3p3_disable(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++
++ gpio_set_value(max17135->gpio_pmic_v3p3, 0);
++ return 0;
++}
++
++static int max17135_v3p3_is_enabled(struct regulator_dev *reg)
++{
++ struct max17135 *max17135 = rdev_get_drvdata(reg);
++ int gpio = gpio_get_value(max17135->gpio_pmic_v3p3);
++
++ if (gpio == 0)
++ return 0;
++ else
++ return 1;
++}
++
++/*
++ * Regulator operations
++ */
++
++static struct regulator_ops max17135_display_ops = {
++ .enable = max17135_display_enable,
++ .disable = max17135_display_disable,
++ .is_enabled = max17135_display_is_enabled,
++};
++
++static struct regulator_ops max17135_gvdd_ops = {
++};
++
++static struct regulator_ops max17135_gvee_ops = {
++};
++
++static struct regulator_ops max17135_hvinn_ops = {
++};
++
++static struct regulator_ops max17135_hvinp_ops = {
++ .enable = max17135_hvinp_enable,
++ .disable = max17135_hvinp_disable,
++ .get_voltage = max17135_hvinp_get_voltage,
++ .set_voltage = max17135_hvinp_set_voltage,
++};
++
++static struct regulator_ops max17135_vcom_ops = {
++ .enable = max17135_vcom_enable,
++ .disable = max17135_vcom_disable,
++ .get_voltage = max17135_vcom_get_voltage,
++ .set_voltage = max17135_vcom_set_voltage,
++ .is_enabled = max17135_vcom_is_enabled,
++};
++
++static struct regulator_ops max17135_vneg_ops = {
++};
++
++static struct regulator_ops max17135_vpos_ops = {
++};
++
++static struct regulator_ops max17135_v3p3_ops = {
++ .enable = max17135_v3p3_enable,
++ .disable = max17135_v3p3_disable,
++ .is_enabled = max17135_v3p3_is_enabled,
++};
++
++
++/*
++ * Regulator descriptors
++ */
++static struct regulator_desc max17135_reg[MAX17135_NUM_REGULATORS] = {
++{
++ .name = "DISPLAY",
++ .id = MAX17135_DISPLAY,
++ .ops = &max17135_display_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "GVDD",
++ .id = MAX17135_GVDD,
++ .ops = &max17135_gvdd_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "GVEE",
++ .id = MAX17135_GVEE,
++ .ops = &max17135_gvee_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "HVINN",
++ .id = MAX17135_HVINN,
++ .ops = &max17135_hvinn_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "HVINP",
++ .id = MAX17135_HVINP,
++ .ops = &max17135_hvinp_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "VCOM",
++ .id = MAX17135_VCOM,
++ .ops = &max17135_vcom_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "VNEG",
++ .id = MAX17135_VNEG,
++ .ops = &max17135_vneg_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "VPOS",
++ .id = MAX17135_VPOS,
++ .ops = &max17135_vpos_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++{
++ .name = "V3P3",
++ .id = MAX17135_V3P3,
++ .ops = &max17135_v3p3_ops,
++ .type = REGULATOR_VOLTAGE,
++ .owner = THIS_MODULE,
++},
++};
++
++static void max17135_setup_timings(struct max17135 *max17135)
++{
++ unsigned int reg_val;
++
++ int timing1, timing2, timing3, timing4,
++ timing5, timing6, timing7, timing8;
++
++ max17135_reg_read(REG_MAX17135_TIMING1, &timing1);
++ max17135_reg_read(REG_MAX17135_TIMING2, &timing2);
++ max17135_reg_read(REG_MAX17135_TIMING3, &timing3);
++ max17135_reg_read(REG_MAX17135_TIMING4, &timing4);
++ max17135_reg_read(REG_MAX17135_TIMING5, &timing5);
++ max17135_reg_read(REG_MAX17135_TIMING6, &timing6);
++ max17135_reg_read(REG_MAX17135_TIMING7, &timing7);
++ max17135_reg_read(REG_MAX17135_TIMING8, &timing8);
++
++ if ((timing1 != max17135->gvee_pwrup) ||
++ (timing2 != max17135->vneg_pwrup) ||
++ (timing3 != max17135->vpos_pwrup) ||
++ (timing4 != max17135->gvdd_pwrup) ||
++ (timing5 != max17135->gvdd_pwrdn) ||
++ (timing6 != max17135->vpos_pwrdn) ||
++ (timing7 != max17135->vneg_pwrdn) ||
++ (timing8 != max17135->gvee_pwrdn)) {
++ max17135_reg_write(REG_MAX17135_TIMING1, max17135->gvee_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING2, max17135->vneg_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING3, max17135->vpos_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING4, max17135->gvdd_pwrup);
++ max17135_reg_write(REG_MAX17135_TIMING5, max17135->gvdd_pwrdn);
++ max17135_reg_write(REG_MAX17135_TIMING6, max17135->vpos_pwrdn);
++ max17135_reg_write(REG_MAX17135_TIMING7, max17135->vneg_pwrdn);
++ max17135_reg_write(REG_MAX17135_TIMING8, max17135->gvee_pwrdn);
++
++ reg_val = BITFVAL(CTRL_TIMING, true); /* shift to correct bit */
++ max17135_reg_write(REG_MAX17135_PRGM_CTRL, reg_val);
++ }
++}
++
++#define CHECK_PROPERTY_ERROR_KFREE(prop) \
++do { \
++ int ret = of_property_read_u32(max17135->dev->of_node, \
++ #prop, &max17135->prop); \
++ if (ret < 0) { \
++ return ret; \
++ } \
++} while (0);
++
++#ifdef CONFIG_OF
++static int max17135_pmic_dt_parse_pdata(struct platform_device *pdev,
++ struct max17135_platform_data *pdata)
++{
++ struct max17135 *max17135 = dev_get_drvdata(pdev->dev.parent);
++ struct device_node *pmic_np, *regulators_np, *reg_np;
++ struct max17135_regulator_data *rdata;
++ int i, ret;
++
++ pmic_np = of_node_get(max17135->dev->of_node);
++ if (!pmic_np) {
++ dev_err(&pdev->dev, "could not find pmic sub-node\n");
++ return -ENODEV;
++ }
++
++ regulators_np = of_find_node_by_name(pmic_np, "regulators");
++ if (!regulators_np) {
++ dev_err(&pdev->dev, "could not find regulators sub-node\n");
++ return -EINVAL;
++ }
++
++ pdata->num_regulators = of_get_child_count(regulators_np);
++ dev_dbg(&pdev->dev, "num_regulators %d\n", pdata->num_regulators);
++
++ rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) *
++ pdata->num_regulators, GFP_KERNEL);
++ if (!rdata) {
++ of_node_put(regulators_np);
++ dev_err(&pdev->dev, "could not allocate memory for"
++ "regulator data\n");
++ return -ENOMEM;
++ }
++
++ pdata->regulators = rdata;
++ for_each_child_of_node(regulators_np, reg_np) {
++ for (i = 0; i < ARRAY_SIZE(max17135_reg); i++)
++ if (!of_node_cmp(reg_np->name, max17135_reg[i].name))
++ break;
++
++ if (i == ARRAY_SIZE(max17135_reg)) {
++ dev_warn(&pdev->dev, "don't know how to configure"
++ "regulator %s\n", reg_np->name);
++ continue;
++ }
++
++ rdata->id = i;
++ rdata->initdata = of_get_regulator_init_data(&pdev->dev,
++ reg_np);
++ rdata->reg_node = reg_np;
++ rdata++;
++ }
++ of_node_put(regulators_np);
++
++ CHECK_PROPERTY_ERROR_KFREE(vneg_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(gvee_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(vpos_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(gvdd_pwrup);
++ CHECK_PROPERTY_ERROR_KFREE(gvdd_pwrdn);
++ CHECK_PROPERTY_ERROR_KFREE(vpos_pwrdn);
++ CHECK_PROPERTY_ERROR_KFREE(gvee_pwrdn);
++ CHECK_PROPERTY_ERROR_KFREE(vneg_pwrdn);
++
++ dev_dbg(&pdev->dev, "vneg_pwrup %d, vneg_pwrdn %d, vpos_pwrup %d,"
++ "vpos_pwrdn %d, gvdd_pwrup %d, gvdd_pwrdn %d, gvee_pwrup %d,"
++ "gvee_pwrdn %d\n", max17135->vneg_pwrup, max17135->vneg_pwrdn,
++ max17135->vpos_pwrup, max17135->vpos_pwrdn,
++ max17135->gvdd_pwrup, max17135->gvdd_pwrdn,
++ max17135->gvee_pwrup, max17135->gvee_pwrdn);
++
++ max17135->max_wait = max17135->vpos_pwrup + max17135->vneg_pwrup +
++ max17135->gvdd_pwrup + max17135->gvee_pwrup;
++
++ max17135->gpio_pmic_wakeup = of_get_named_gpio(pmic_np,
++ "gpio_pmic_wakeup", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_wakeup)) {
++ dev_err(&pdev->dev, "no epdc pmic wakeup pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_wakeup,
++ GPIOF_OUT_INIT_LOW, "epdc-pmic-wake");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_vcom_ctrl = of_get_named_gpio(pmic_np,
++ "gpio_pmic_vcom_ctrl", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_vcom_ctrl)) {
++ dev_err(&pdev->dev, "no epdc pmic vcom_ctrl pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_vcom_ctrl,
++ GPIOF_OUT_INIT_LOW, "epdc-vcom");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_v3p3 = of_get_named_gpio(pmic_np,
++ "gpio_pmic_v3p3", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_v3p3)) {
++ dev_err(&pdev->dev, "no epdc pmic v3p3 pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_v3p3,
++ GPIOF_OUT_INIT_LOW, "epdc-v3p3");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_intr = of_get_named_gpio(pmic_np,
++ "gpio_pmic_intr", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_intr)) {
++ dev_err(&pdev->dev, "no epdc pmic intr pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_intr,
++ GPIOF_IN, "epdc-pmic-int");
++ if (ret < 0)
++ goto err;
++
++ max17135->gpio_pmic_pwrgood = of_get_named_gpio(pmic_np,
++ "gpio_pmic_pwrgood", 0);
++ if (!gpio_is_valid(max17135->gpio_pmic_pwrgood)) {
++ dev_err(&pdev->dev, "no epdc pmic pwrgood pin available\n");
++ goto err;
++ }
++ ret = devm_gpio_request_one(&pdev->dev, max17135->gpio_pmic_pwrgood,
++ GPIOF_IN, "epdc-pwrstat");
++ if (ret < 0)
++ goto err;
++
++err:
++ return 0;
++
++}
++#else
++static int max17135_pmic_dt_parse_pdata(struct platform_device *pdev,
++ struct max17135 *max17135)
++{
++ return 0;
++}
++#endif /* !CONFIG_OF */
++
++/*
++ * Regulator init/probing/exit functions
++ */
++static int max17135_regulator_probe(struct platform_device *pdev)
++{
++ struct max17135 *max17135 = dev_get_drvdata(pdev->dev.parent);
++ struct max17135_platform_data *pdata = max17135->pdata;
++ struct max17135_data *priv;
++ struct regulator_dev **rdev;
++ struct regulator_config config = { };
++ int size, i, ret = 0;
++
++ if (max17135->dev->of_node) {
++ ret = max17135_pmic_dt_parse_pdata(pdev, pdata);
++ if (ret)
++ return ret;
++ }
++ priv = devm_kzalloc(&pdev->dev, sizeof(struct max17135_data),
++ GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ size = sizeof(struct regulator_dev *) * pdata->num_regulators;
++ priv->rdev = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
++ if (!priv->rdev)
++ return -ENOMEM;
++
++ rdev = priv->rdev;
++ priv->num_regulators = pdata->num_regulators;
++ platform_set_drvdata(pdev, priv);
++
++ max17135->vcom_setup = false;
++ max17135->pass_num = max17135_pass_num;
++ max17135->vcom_uV = max17135_vcom;
++
++ for (i = 0; i < pdata->num_regulators; i++) {
++ int id = pdata->regulators[i].id;
++
++ config.dev = max17135->dev;
++ config.init_data = pdata->regulators[i].initdata;
++ config.driver_data = max17135;
++ config.of_node = pdata->regulators[i].reg_node;
++
++ rdev[i] = regulator_register(&max17135_reg[id], &config);
++ if (IS_ERR(rdev[i])) {
++ ret = PTR_ERR(rdev[i]);
++ dev_err(&pdev->dev, "regulator init failed for %d\n",
++ id);
++ rdev[i] = NULL;
++ goto err;
++ }
++ }
++
++ /*
++ * Set up PMIC timing values.
++ * Should only be done one time! Timing values may only be
++ * changed a limited number of times according to spec.
++ */
++ max17135_setup_timings(max17135);
++
++ return 0;
++err:
++ while (--i >= 0)
++ regulator_unregister(rdev[i]);
++ return ret;
++}
++
++static int max17135_regulator_remove(struct platform_device *pdev)
++{
++ struct max17135_data *priv = platform_get_drvdata(pdev);
++ struct regulator_dev **rdev = priv->rdev;
++ int i;
++
++ for (i = 0; i < priv->num_regulators; i++)
++ regulator_unregister(rdev[i]);
++ return 0;
++}
++
++static const struct platform_device_id max17135_pmic_id[] = {
++ { "max17135-pmic", 0},
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(platform, max17135_pmic_id);
++
++static struct platform_driver max17135_regulator_driver = {
++ .probe = max17135_regulator_probe,
++ .remove = max17135_regulator_remove,
++ .id_table = max17135_pmic_id,
++ .driver = {
++ .name = "max17135-pmic",
++ },
++};
++
++static int __init max17135_regulator_init(void)
++{
++ return platform_driver_register(&max17135_regulator_driver);
++}
++subsys_initcall_sync(max17135_regulator_init);
++
++static void __exit max17135_regulator_exit(void)
++{
++ platform_driver_unregister(&max17135_regulator_driver);
++}
++module_exit(max17135_regulator_exit);
++
++/*
++ * Parse user specified options (`max17135:')
++ * example:
++ * max17135:pass=2,vcom=-1250000
++ */
++static int __init max17135_setup(char *options)
++{
++ int ret;
++ char *opt;
++ while ((opt = strsep(&options, ",")) != NULL) {
++ if (!*opt)
++ continue;
++ if (!strncmp(opt, "pass=", 5)) {
++ ret = strict_strtoul(opt + 5, 0, &max17135_pass_num);
++ if (ret < 0)
++ return ret;
++ }
++ if (!strncmp(opt, "vcom=", 5)) {
++ int offs = 5;
++ if (opt[5] == '-')
++ offs = 6;
++ ret = strict_strtoul(opt + offs, 0,
++ (long *)&max17135_vcom);
++ if (ret < 0)
++ return ret;
++ max17135_vcom = -max17135_vcom;
++ }
++ }
++
++ return 1;
++}
++
++__setup("max17135:", max17135_setup);
++
++/* Module information */
++MODULE_DESCRIPTION("MAX17135 regulator driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/regulator/pfuze100-regulator.c linux-3.14.72/drivers/regulator/pfuze100-regulator.c
+--- linux-3.14.72.orig/drivers/regulator/pfuze100-regulator.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/regulator/pfuze100-regulator.c 2016-06-19 22:11:55.313139482 +0200
+@@ -56,6 +56,8 @@
+ #define PFUZE100_VGEN5VOL 0x70
+ #define PFUZE100_VGEN6VOL 0x71
+
++enum chips { PFUZE100, PFUZE200 };
++
+ struct pfuze_regulator {
+ struct regulator_desc desc;
+ unsigned char stby_reg;
+@@ -63,6 +65,7 @@
+ };
+
+ struct pfuze_chip {
++ int chip_id;
+ struct regmap *regmap;
+ struct device *dev;
+ struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
+@@ -78,21 +81,23 @@
+ };
+
+ static const struct i2c_device_id pfuze_device_id[] = {
+- {.name = "pfuze100"},
+- {},
++ {.name = "pfuze100", .driver_data = PFUZE100},
++ {.name = "pfuze200", .driver_data = PFUZE200},
++ { }
+ };
+ MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
+
+ static const struct of_device_id pfuze_dt_ids[] = {
+- { .compatible = "fsl,pfuze100" },
+- {},
++ { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
++ { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
++ { }
+ };
+ MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
+
+ static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
+ {
+ struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
+- int id = rdev->desc->id;
++ int id = rdev_get_id(rdev);
+ unsigned int ramp_bits;
+ int ret;
+
+@@ -139,14 +144,14 @@
+
+ };
+
+-#define PFUZE100_FIXED_REG(_name, base, voltage) \
+- [PFUZE100_ ## _name] = { \
++#define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
++ [_chip ## _ ## _name] = { \
+ .desc = { \
+ .name = #_name, \
+ .n_voltages = 1, \
+ .ops = &pfuze100_fixed_regulator_ops, \
+ .type = REGULATOR_VOLTAGE, \
+- .id = PFUZE100_ ## _name, \
++ .id = _chip ## _ ## _name, \
+ .owner = THIS_MODULE, \
+ .min_uV = (voltage), \
+ .enable_reg = (base), \
+@@ -154,14 +159,14 @@
+ }, \
+ }
+
+-#define PFUZE100_SW_REG(_name, base, min, max, step) \
+- [PFUZE100_ ## _name] = { \
++#define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
++ [_chip ## _ ## _name] = { \
+ .desc = { \
+ .name = #_name,\
+ .n_voltages = ((max) - (min)) / (step) + 1, \
+ .ops = &pfuze100_sw_regulator_ops, \
+ .type = REGULATOR_VOLTAGE, \
+- .id = PFUZE100_ ## _name, \
++ .id = _chip ## _ ## _name, \
+ .owner = THIS_MODULE, \
+ .min_uV = (min), \
+ .uV_step = (step), \
+@@ -172,14 +177,14 @@
+ .stby_mask = 0x3f, \
+ }
+
+-#define PFUZE100_SWB_REG(_name, base, mask, voltages) \
+- [PFUZE100_ ## _name] = { \
++#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
++ [_chip ## _ ## _name] = { \
+ .desc = { \
+ .name = #_name, \
+ .n_voltages = ARRAY_SIZE(voltages), \
+ .ops = &pfuze100_swb_regulator_ops, \
+ .type = REGULATOR_VOLTAGE, \
+- .id = PFUZE100_ ## _name, \
++ .id = _chip ## _ ## _name, \
+ .owner = THIS_MODULE, \
+ .volt_table = voltages, \
+ .vsel_reg = (base), \
+@@ -187,14 +192,14 @@
+ }, \
+ }
+
+-#define PFUZE100_VGEN_REG(_name, base, min, max, step) \
+- [PFUZE100_ ## _name] = { \
++#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
++ [_chip ## _ ## _name] = { \
+ .desc = { \
+ .name = #_name, \
+ .n_voltages = ((max) - (min)) / (step) + 1, \
+ .ops = &pfuze100_ldo_regulator_ops, \
+ .type = REGULATOR_VOLTAGE, \
+- .id = PFUZE100_ ## _name, \
++ .id = _chip ## _ ## _name, \
+ .owner = THIS_MODULE, \
+ .min_uV = (min), \
+ .uV_step = (step), \
+@@ -207,25 +212,45 @@
+ .stby_mask = 0x20, \
+ }
+
++/* PFUZE100 */
+ static struct pfuze_regulator pfuze100_regulators[] = {
+- PFUZE100_SW_REG(SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
+- PFUZE100_SW_REG(SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
+- PFUZE100_SW_REG(SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
+- PFUZE100_SW_REG(SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
+- PFUZE100_SW_REG(SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
+- PFUZE100_SW_REG(SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
+- PFUZE100_SWB_REG(SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
+- PFUZE100_SWB_REG(VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
+- PFUZE100_FIXED_REG(VREFDDR, PFUZE100_VREFDDRCON, 750000),
+- PFUZE100_VGEN_REG(VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
+- PFUZE100_VGEN_REG(VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
+- PFUZE100_VGEN_REG(VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
+- PFUZE100_VGEN_REG(VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
+- PFUZE100_VGEN_REG(VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
+- PFUZE100_VGEN_REG(VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
++ PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
++ PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
++ PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
++ PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
++ PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
++ PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
++ PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
++ PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
++ PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
++};
++
++static struct pfuze_regulator pfuze200_regulators[] = {
++ PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
++ PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
++ PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
++ PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
++ PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
++ PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
++ PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
++ PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
++ PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
++ PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
+ };
+
++static struct pfuze_regulator *pfuze_regulators;
++
+ #ifdef CONFIG_OF
++/* PFUZE100 */
+ static struct of_regulator_match pfuze100_matches[] = {
+ { .name = "sw1ab", },
+ { .name = "sw1c", },
+@@ -244,24 +269,56 @@
+ { .name = "vgen6", },
+ };
+
++/* PFUZE200 */
++static struct of_regulator_match pfuze200_matches[] = {
++
++ { .name = "sw1ab", },
++ { .name = "sw2", },
++ { .name = "sw3a", },
++ { .name = "sw3b", },
++ { .name = "swbst", },
++ { .name = "vsnvs", },
++ { .name = "vrefddr", },
++ { .name = "vgen1", },
++ { .name = "vgen2", },
++ { .name = "vgen3", },
++ { .name = "vgen4", },
++ { .name = "vgen5", },
++ { .name = "vgen6", },
++};
++
++static struct of_regulator_match *pfuze_matches;
++
+ static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
+ {
+ struct device *dev = chip->dev;
+ struct device_node *np, *parent;
+ int ret;
+
+- np = of_node_get(dev->parent->of_node);
++ np = of_node_get(dev->of_node);
+ if (!np)
+- return 0;
++ return -EINVAL;
+
+- parent = of_find_node_by_name(np, "regulators");
++ parent = of_get_child_by_name(np, "regulators");
+ if (!parent) {
+ dev_err(dev, "regulators node not found\n");
+ return -EINVAL;
+ }
+
+- ret = of_regulator_match(dev, parent, pfuze100_matches,
+- ARRAY_SIZE(pfuze100_matches));
++ switch (chip->chip_id) {
++ case PFUZE200:
++ pfuze_matches = pfuze200_matches;
++ ret = of_regulator_match(dev, parent, pfuze200_matches,
++ ARRAY_SIZE(pfuze200_matches));
++ break;
++
++ case PFUZE100:
++ default:
++ pfuze_matches = pfuze100_matches;
++ ret = of_regulator_match(dev, parent, pfuze100_matches,
++ ARRAY_SIZE(pfuze100_matches));
++ break;
++ }
+
+ of_node_put(parent);
+ if (ret < 0) {
+@@ -275,12 +332,12 @@
+
+ static inline struct regulator_init_data *match_init_data(int index)
+ {
+- return pfuze100_matches[index].init_data;
++ return pfuze_matches[index].init_data;
+ }
+
+ static inline struct device_node *match_of_node(int index)
+ {
+- return pfuze100_matches[index].of_node;
++ return pfuze_matches[index].of_node;
+ }
+ #else
+ static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
+@@ -308,16 +365,14 @@
+ if (ret)
+ return ret;
+
+- switch (value & 0x0f) {
+- /*
+- * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
+- * as ID=8
+- */
+- case 0x8:
++ if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
++ /*
++ * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
++ * as ID=8 in PFUZE100
++ */
+ dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
+- case 0x0:
+- break;
+- default:
++ } else if ((value & 0x0f) != pfuze_chip->chip_id) {
++ /* device id NOT match with your setting */
+ dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
+ return -ENODEV;
+ }
+@@ -353,17 +408,31 @@
+ dev_get_platdata(&client->dev);
+ struct regulator_config config = { };
+ int i, ret;
++ const struct of_device_id *match;
++ u32 regulator_num;
++ u32 sw_check_start, sw_check_end;
+
+ pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
+ GFP_KERNEL);
+ if (!pfuze_chip)
+ return -ENOMEM;
+
+- i2c_set_clientdata(client, pfuze_chip);
+-
+- memcpy(pfuze_chip->regulator_descs, pfuze100_regulators,
+- sizeof(pfuze_chip->regulator_descs));
++ if (client->dev.of_node) {
++ match = of_match_device(of_match_ptr(pfuze_dt_ids),
++ &client->dev);
++ if (!match) {
++ dev_err(&client->dev, "Error: No device match found\n");
++ return -ENODEV;
++ }
++ pfuze_chip->chip_id = (int)(long)match->data;
++ } else if (id) {
++ pfuze_chip->chip_id = id->driver_data;
++ } else {
++ dev_err(&client->dev, "No dts match or id table match found\n");
++ return -ENODEV;
++ }
+
++ i2c_set_clientdata(client, pfuze_chip);
+ pfuze_chip->dev = &client->dev;
+
+ pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
+@@ -380,11 +449,34 @@
+ return ret;
+ }
+
++ /* use the right regulators after identify the right device */
++ switch (pfuze_chip->chip_id) {
++ case PFUZE200:
++ pfuze_regulators = pfuze200_regulators;
++ regulator_num = ARRAY_SIZE(pfuze200_regulators);
++ sw_check_start = PFUZE200_SW2;
++ sw_check_end = PFUZE200_SW3B;
++ break;
++
++ case PFUZE100:
++ default:
++ pfuze_regulators = pfuze100_regulators;
++ regulator_num = ARRAY_SIZE(pfuze100_regulators);
++ sw_check_start = PFUZE100_SW2;
++ sw_check_end = PFUZE100_SW4;
++ break;
++ }
++ dev_info(&client->dev, "pfuze%s found.\n",
++ (pfuze_chip->chip_id == PFUZE100) ? "100" : "200");
++
++ memcpy(pfuze_chip->regulator_descs, pfuze_regulators,
++ sizeof(pfuze_chip->regulator_descs));
++
+ ret = pfuze_parse_regulators_dt(pfuze_chip);
+ if (ret)
+ return ret;
+
+- for (i = 0; i < PFUZE100_MAX_REGULATOR; i++) {
++ for (i = 0; i < regulator_num; i++) {
+ struct regulator_init_data *init_data;
+ struct regulator_desc *desc;
+ int val;
+@@ -397,7 +489,7 @@
+ init_data = match_init_data(i);
+
+ /* SW2~SW4 high bit check and modify the voltage value table */
+- if (i > PFUZE100_SW1C && i < PFUZE100_SWBST) {
++ if (i >= sw_check_start && i <= sw_check_end) {
+ regmap_read(pfuze_chip->regmap, desc->vsel_reg, &val);
+ if (val & 0x40) {
+ desc->min_uV = 800000;
+@@ -415,7 +507,7 @@
+ devm_regulator_register(&client->dev, desc, &config);
+ if (IS_ERR(pfuze_chip->regulators[i])) {
+ dev_err(&client->dev, "register regulator%s failed\n",
+- pfuze100_regulators[i].desc.name);
++ pfuze_regulators[i].desc.name);
+ return PTR_ERR(pfuze_chip->regulators[i]);
+ }
+ }
+@@ -435,6 +527,6 @@
+ module_i2c_driver(pfuze_driver);
+
+ MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
+-MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100 PMIC");
++MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/PFUZE200 PMIC");
+ MODULE_LICENSE("GPL v2");
+ MODULE_ALIAS("i2c:pfuze100-regulator");
+diff -Nur linux-3.14.72.orig/drivers/regulator/s2mps11.c linux-3.14.72/drivers/regulator/s2mps11.c
+--- linux-3.14.72.orig/drivers/regulator/s2mps11.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/regulator/s2mps11.c 2016-06-19 22:11:55.313139482 +0200
+@@ -65,7 +65,7 @@
+ unsigned int ramp_delay = 0;
+ int old_volt, new_volt;
+
+- switch (rdev->desc->id) {
++ switch (rdev_get_id(rdev)) {
+ case S2MPS11_BUCK2:
+ ramp_delay = s2mps11->ramp_delay2;
+ break;
+@@ -105,7 +105,7 @@
+ unsigned int ramp_enable = 1, enable_shift = 0;
+ int ret;
+
+- switch (rdev->desc->id) {
++ switch (rdev_get_id(rdev)) {
+ case S2MPS11_BUCK1:
+ if (ramp_delay > s2mps11->ramp_delay16)
+ s2mps11->ramp_delay16 = ramp_delay;
+diff -Nur linux-3.14.72.orig/drivers/reset/gpio-reset.c linux-3.14.72/drivers/reset/gpio-reset.c
+--- linux-3.14.72.orig/drivers/reset/gpio-reset.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/reset/gpio-reset.c 2016-06-19 22:11:55.313139482 +0200
+@@ -0,0 +1,184 @@
++/*
++ * GPIO Reset Controller driver
++ *
++ * Copyright 2013 Philipp Zabel, Pengutronix
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/gpio.h>
++#include <linux/module.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++
++struct gpio_reset_data {
++ struct reset_controller_dev rcdev;
++ unsigned int gpio;
++ bool active_low;
++ s32 delay_us;
++};
++
++static void gpio_reset_set(struct reset_controller_dev *rcdev, int asserted)
++{
++ struct gpio_reset_data *drvdata = container_of(rcdev,
++ struct gpio_reset_data, rcdev);
++ int value = asserted;
++
++ if (drvdata->active_low)
++ value = !value;
++
++ gpio_set_value(drvdata->gpio, value);
++}
++
++static int gpio_reset(struct reset_controller_dev *rcdev, unsigned long id)
++{
++ struct gpio_reset_data *drvdata = container_of(rcdev,
++ struct gpio_reset_data, rcdev);
++
++ if (drvdata->delay_us < 0)
++ return -ENOSYS;
++
++ gpio_reset_set(rcdev, 1);
++ udelay(drvdata->delay_us);
++ gpio_reset_set(rcdev, 0);
++
++ return 0;
++}
++
++static int gpio_reset_assert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ gpio_reset_set(rcdev, 1);
++
++ return 0;
++}
++
++static int gpio_reset_deassert(struct reset_controller_dev *rcdev,
++ unsigned long id)
++{
++ gpio_reset_set(rcdev, 0);
++
++ return 0;
++}
++
++static struct reset_control_ops gpio_reset_ops = {
++ .reset = gpio_reset,
++ .assert = gpio_reset_assert,
++ .deassert = gpio_reset_deassert,
++};
++
++static int of_gpio_reset_xlate(struct reset_controller_dev *rcdev,
++ const struct of_phandle_args *reset_spec)
++{
++ if (WARN_ON(reset_spec->args_count != 0))
++ return -EINVAL;
++
++ return 0;
++}
++
++static int gpio_reset_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct gpio_reset_data *drvdata;
++ enum of_gpio_flags flags;
++ unsigned long gpio_flags;
++ bool initially_in_reset;
++ int ret;
++
++ drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
++ if (drvdata == NULL)
++ return -ENOMEM;
++
++ if (of_gpio_named_count(np, "reset-gpios") != 1) {
++ dev_err(&pdev->dev,
++ "reset-gpios property missing, or not a single gpio\n");
++ return -EINVAL;
++ }
++
++ drvdata->gpio = of_get_named_gpio_flags(np, "reset-gpios", 0, &flags);
++ if (drvdata->gpio == -EPROBE_DEFER) {
++ return drvdata->gpio;
++ } else if (!gpio_is_valid(drvdata->gpio)) {
++ dev_err(&pdev->dev, "invalid reset gpio: %d\n", drvdata->gpio);
++ return drvdata->gpio;
++ }
++
++ drvdata->active_low = flags & OF_GPIO_ACTIVE_LOW;
++
++ ret = of_property_read_u32(np, "reset-delay-us", &drvdata->delay_us);
++ if (ret < 0)
++ drvdata->delay_us = -1;
++ else if (drvdata->delay_us < 0)
++ dev_warn(&pdev->dev, "reset delay too high\n");
++
++ initially_in_reset = of_property_read_bool(np, "initially-in-reset");
++ if (drvdata->active_low ^ initially_in_reset)
++ gpio_flags = GPIOF_OUT_INIT_HIGH;
++ else
++ gpio_flags = GPIOF_OUT_INIT_LOW;
++
++ ret = devm_gpio_request_one(&pdev->dev, drvdata->gpio, gpio_flags, NULL);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to request gpio %d: %d\n",
++ drvdata->gpio, ret);
++ return ret;
++ }
++
++ platform_set_drvdata(pdev, drvdata);
++
++ drvdata->rcdev.of_node = np;
++ drvdata->rcdev.owner = THIS_MODULE;
++ drvdata->rcdev.nr_resets = 1;
++ drvdata->rcdev.ops = &gpio_reset_ops;
++ drvdata->rcdev.of_xlate = of_gpio_reset_xlate;
++ reset_controller_register(&drvdata->rcdev);
++
++ return 0;
++}
++
++static int gpio_reset_remove(struct platform_device *pdev)
++{
++ struct gpio_reset_data *drvdata = platform_get_drvdata(pdev);
++
++ reset_controller_unregister(&drvdata->rcdev);
++
++ return 0;
++}
++
++static struct of_device_id gpio_reset_dt_ids[] = {
++ { .compatible = "gpio-reset" },
++ { }
++};
++
++static struct platform_driver gpio_reset_driver = {
++ .probe = gpio_reset_probe,
++ .remove = gpio_reset_remove,
++ .driver = {
++ .name = "gpio-reset",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(gpio_reset_dt_ids),
++ },
++};
++
++static int __init gpio_reset_init(void)
++{
++ return platform_driver_register(&gpio_reset_driver);
++}
++arch_initcall(gpio_reset_init);
++
++static void __exit gpio_reset_exit(void)
++{
++ platform_driver_unregister(&gpio_reset_driver);
++}
++module_exit(gpio_reset_exit);
++
++MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
++MODULE_DESCRIPTION("gpio reset controller");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:gpio-reset");
++MODULE_DEVICE_TABLE(of, gpio_reset_dt_ids);
+diff -Nur linux-3.14.72.orig/drivers/reset/Kconfig linux-3.14.72/drivers/reset/Kconfig
+--- linux-3.14.72.orig/drivers/reset/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/reset/Kconfig 2016-06-19 22:11:55.313139482 +0200
+@@ -11,3 +11,15 @@
+ via GPIOs or SoC-internal reset controller modules.
+
+ If unsure, say no.
++
++if RESET_CONTROLLER
++
++config RESET_GPIO
++ tristate "GPIO reset controller support"
++ default y
++ depends on GPIOLIB && OF
++ help
++ This driver provides support for reset lines that are controlled
++ directly by GPIOs.
++
++endif
+diff -Nur linux-3.14.72.orig/drivers/reset/Makefile linux-3.14.72/drivers/reset/Makefile
+--- linux-3.14.72.orig/drivers/reset/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/reset/Makefile 2016-06-19 22:11:55.313139482 +0200
+@@ -1,2 +1,3 @@
+ obj-$(CONFIG_RESET_CONTROLLER) += core.o
++obj-$(CONFIG_RESET_GPIO) += gpio-reset.o
+ obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
+diff -Nur linux-3.14.72.orig/drivers/rtc/rtc-pcf8523.c linux-3.14.72/drivers/rtc/rtc-pcf8523.c
+--- linux-3.14.72.orig/drivers/rtc/rtc-pcf8523.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/rtc/rtc-pcf8523.c 2016-06-19 22:11:55.313139482 +0200
+@@ -7,6 +7,7 @@
+ */
+
+ #include <linux/bcd.h>
++#include <linux/delay.h>
+ #include <linux/i2c.h>
+ #include <linux/module.h>
+ #include <linux/rtc.h>
+@@ -82,24 +83,107 @@
+ return 0;
+ }
+
+-static int pcf8523_select_capacitance(struct i2c_client *client, bool high)
++static int pcf8523_rtc_check_oscillator(struct i2c_client *client)
+ {
+ u8 value;
+ int err;
+
+- err = pcf8523_read(client, REG_CONTROL1, &value);
++ err = pcf8523_read(client, REG_SECONDS, &value);
+ if (err < 0)
+ return err;
+
+- if (!high)
+- value &= ~REG_CONTROL1_CAP_SEL;
+- else
+- value |= REG_CONTROL1_CAP_SEL;
++ if (value & REG_SECONDS_OS) {
++ /*
++ * If the oscillator was stopped, try to clear the flag. Upon
++ * power-up the flag is always set, but if we cannot clear it
++ * the oscillator isn't running properly for some reason. The
++ * sensible thing therefore is to return an error, signalling
++ * that the clock cannot be assumed to be correct.
++ */
++
++ value &= ~REG_SECONDS_OS;
++
++ err = pcf8523_write(client, REG_SECONDS, value);
++ if (err < 0)
++ return err;
++
++ err = pcf8523_read(client, REG_SECONDS, &value);
++ if (err < 0)
++ return err;
++
++ if (value & REG_SECONDS_OS)
++ return -EAGAIN;
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_OF
++static int pcf8523_set_12p5_pf(struct i2c_client *client)
++{
++ u8 value;
++ int err;
++
++ err = pcf8523_read(client, REG_CONTROL1, &value);
++ if (err < 0)
++ goto out;
++
++ if (value & REG_CONTROL1_CAP_SEL)
++ return 0;
++
++ value |= REG_CONTROL1_CAP_SEL;
+
+ err = pcf8523_write(client, REG_CONTROL1, value);
++
++out:
++ return err;
++}
++#endif
++
++static int pcf8523_switch_capacitance(struct i2c_client *client)
++{
++ u8 value;
++ int err;
++
++ err = pcf8523_read(client, REG_CONTROL1, &value);
+ if (err < 0)
+- return err;
++ goto out;
++
++ value ^= REG_CONTROL1_CAP_SEL;
+
++ err = pcf8523_write(client, REG_CONTROL1, value);
++
++out:
++ return err;
++}
++
++static int pcf8523_enable_oscillator(struct i2c_client *client)
++{
++ int err, loop;
++
++ loop = 0;
++ while (loop < 200) {
++ err = pcf8523_rtc_check_oscillator(client);
++ if (!err)
++ return 0;
++ loop++;
++ msleep(10);
++ }
++
++ err = pcf8523_switch_capacitance(client);
++ if (err < 0)
++ goto out;
++
++ loop = 0;
++ while (loop < 200) {
++ err = pcf8523_rtc_check_oscillator(client);
++ if (!err)
++ return 0;
++ loop++;
++ msleep(10);
++ }
++
++out:
+ return err;
+ }
+
+@@ -206,7 +290,7 @@
+ tm->tm_hour = bcd2bin(regs[2] & 0x3f);
+ tm->tm_mday = bcd2bin(regs[3] & 0x3f);
+ tm->tm_wday = regs[4] & 0x7;
+- tm->tm_mon = bcd2bin(regs[5] & 0x1f);
++ tm->tm_mon = bcd2bin(regs[5] & 0x1f) - 1;
+ tm->tm_year = bcd2bin(regs[6]) + 100;
+
+ return rtc_valid_tm(tm);
+@@ -229,7 +313,7 @@
+ regs[3] = bin2bcd(tm->tm_hour);
+ regs[4] = bin2bcd(tm->tm_mday);
+ regs[5] = tm->tm_wday;
+- regs[6] = bin2bcd(tm->tm_mon);
++ regs[6] = bin2bcd(tm->tm_mon + 1);
+ regs[7] = bin2bcd(tm->tm_year - 100);
+
+ msg.addr = client->addr;
+@@ -289,7 +373,11 @@
+ static int pcf8523_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+ {
++#ifdef CONFIG_OF
++ struct device_node *np = client->dev.of_node;
++#endif
+ struct pcf8523 *pcf;
++ u8 value;
+ int err;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
+@@ -299,10 +387,27 @@
+ if (!pcf)
+ return -ENOMEM;
+
+- err = pcf8523_select_capacitance(client, true);
++ /* Check whether the RTC reports battery low */
++ err = pcf8523_read(client, REG_CONTROL3, &value);
+ if (err < 0)
+ return err;
+
++ if (value & REG_CONTROL3_BLF)
++ dev_warn(&client->dev, "RTC reports battery is low\n");
++
++#ifdef CONFIG_OF
++ if (of_property_read_bool(np, "nxp,12p5_pf")) {
++ dev_info(&client->dev, "starting calibration at 12.5 pf\n");
++ pcf8523_set_12p5_pf(client);
++ }
++#endif
++
++ err = pcf8523_enable_oscillator(client);
++ if (err < 0) {
++ dev_warn(&client->dev, "RTC reports oscillator is not running\n");
++ return err;
++ }
++
+ err = pcf8523_set_pm(client, 0);
+ if (err < 0)
+ return err;
+diff -Nur linux-3.14.72.orig/drivers/rtc/rtc-snvs.c linux-3.14.72/drivers/rtc/rtc-snvs.c
+--- linux-3.14.72.orig/drivers/rtc/rtc-snvs.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/rtc/rtc-snvs.c 2016-06-19 22:11:55.313139482 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -41,6 +41,10 @@
+ spinlock_t lock;
+ };
+
++static void __iomem *snvs_base;
++
++void snvs_poweroff(void);
++
+ static u32 rtc_read_lp_counter(void __iomem *ioaddr)
+ {
+ u64 read1, read2;
+@@ -241,6 +245,15 @@
+ return events ? IRQ_HANDLED : IRQ_NONE;
+ }
+
++void snvs_poweroff(void)
++{
++ u32 value;
++
++ value = readl(snvs_base + SNVS_LPCR);
++ /* set TOP and DP_EN bit */
++ writel(value | 0x60, snvs_base + SNVS_LPCR);
++}
++
+ static int snvs_rtc_probe(struct platform_device *pdev)
+ {
+ struct snvs_rtc_data *data;
+@@ -270,13 +283,15 @@
+ /* Clear interrupt status */
+ writel(0xffffffff, data->ioaddr + SNVS_LPSR);
+
++ snvs_base = data->ioaddr;
+ /* Enable RTC */
+ snvs_rtc_enable(data, true);
+
+ device_init_wakeup(&pdev->dev, true);
+
+ ret = devm_request_irq(&pdev->dev, data->irq, snvs_rtc_irq_handler,
+- IRQF_SHARED, "rtc alarm", &pdev->dev);
++ IRQF_SHARED | IRQF_NO_SUSPEND,
++ "rtc alarm", &pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request irq %d: %d\n",
+ data->irq, ret);
+diff -Nur linux-3.14.72.orig/drivers/scsi/libsas/sas_ata.c linux-3.14.72/drivers/scsi/libsas/sas_ata.c
+--- linux-3.14.72.orig/drivers/scsi/libsas/sas_ata.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/scsi/libsas/sas_ata.c 2016-06-19 22:11:55.313139482 +0200
+@@ -700,46 +700,26 @@
+
+ }
+
+-static bool sas_ata_flush_pm_eh(struct asd_sas_port *port, const char *func)
++static void sas_ata_flush_pm_eh(struct asd_sas_port *port, const char *func)
+ {
+ struct domain_device *dev, *n;
+- bool retry = false;
+
+ list_for_each_entry_safe(dev, n, &port->dev_list, dev_list_node) {
+- int rc;
+-
+ if (!dev_is_sata(dev))
+ continue;
+
+ sas_ata_wait_eh(dev);
+- rc = dev->sata_dev.pm_result;
+- if (rc == -EAGAIN)
+- retry = true;
+- else if (rc) {
+- /* since we don't have a
+- * ->port_{suspend|resume} routine in our
+- * ata_port ops, and no entanglements with
+- * acpi, suspend should just be mechanical trip
+- * through eh, catch cases where these
+- * assumptions are invalidated
+- */
+- WARN_ONCE(1, "failed %s %s error: %d\n", func,
+- dev_name(&dev->rphy->dev), rc);
+- }
+
+ /* if libata failed to power manage the device, tear it down */
+ if (ata_dev_disabled(sas_to_ata_dev(dev)))
+ sas_fail_probe(dev, func, -ENODEV);
+ }
+-
+- return retry;
+ }
+
+ void sas_suspend_sata(struct asd_sas_port *port)
+ {
+ struct domain_device *dev;
+
+- retry:
+ mutex_lock(&port->ha->disco_mutex);
+ list_for_each_entry(dev, &port->dev_list, dev_list_node) {
+ struct sata_device *sata;
+@@ -751,20 +731,17 @@
+ if (sata->ap->pm_mesg.event == PM_EVENT_SUSPEND)
+ continue;
+
+- sata->pm_result = -EIO;
+- ata_sas_port_async_suspend(sata->ap, &sata->pm_result);
++ ata_sas_port_suspend(sata->ap);
+ }
+ mutex_unlock(&port->ha->disco_mutex);
+
+- if (sas_ata_flush_pm_eh(port, __func__))
+- goto retry;
++ sas_ata_flush_pm_eh(port, __func__);
+ }
+
+ void sas_resume_sata(struct asd_sas_port *port)
+ {
+ struct domain_device *dev;
+
+- retry:
+ mutex_lock(&port->ha->disco_mutex);
+ list_for_each_entry(dev, &port->dev_list, dev_list_node) {
+ struct sata_device *sata;
+@@ -776,13 +753,11 @@
+ if (sata->ap->pm_mesg.event == PM_EVENT_ON)
+ continue;
+
+- sata->pm_result = -EIO;
+- ata_sas_port_async_resume(sata->ap, &sata->pm_result);
++ ata_sas_port_resume(sata->ap);
+ }
+ mutex_unlock(&port->ha->disco_mutex);
+
+- if (sas_ata_flush_pm_eh(port, __func__))
+- goto retry;
++ sas_ata_flush_pm_eh(port, __func__);
+ }
+
+ /**
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-altera.c linux-3.14.72/drivers/spi/spi-altera.c
+--- linux-3.14.72.orig/drivers/spi/spi-altera.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-altera.c 2016-06-19 22:11:55.313139482 +0200
+@@ -13,7 +13,6 @@
+ * published by the Free Software Foundation.
+ */
+
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/errno.h>
+ #include <linux/module.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-ath79.c linux-3.14.72/drivers/spi/spi-ath79.c
+--- linux-3.14.72.orig/drivers/spi/spi-ath79.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-ath79.c 2016-06-19 22:11:55.313139482 +0200
+@@ -14,7 +14,6 @@
+
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/spinlock.h>
+ #include <linux/workqueue.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-atmel.c linux-3.14.72/drivers/spi/spi-atmel.c
+--- linux-3.14.72.orig/drivers/spi/spi-atmel.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-atmel.c 2016-06-19 22:11:55.313139482 +0200
+@@ -9,7 +9,6 @@
+ */
+
+ #include <linux/kernel.h>
+-#include <linux/init.h>
+ #include <linux/clk.h>
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-bcm63xx.c linux-3.14.72/drivers/spi/spi-bcm63xx.c
+--- linux-3.14.72.orig/drivers/spi/spi-bcm63xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-bcm63xx.c 2016-06-19 22:11:55.313139482 +0200
+@@ -20,7 +20,6 @@
+ */
+
+ #include <linux/kernel.h>
+-#include <linux/init.h>
+ #include <linux/clk.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+@@ -169,7 +168,7 @@
+ transfer_list);
+ }
+
+- init_completion(&bs->done);
++ reinit_completion(&bs->done);
+
+ /* Fill in the Message control register */
+ msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
+@@ -353,6 +352,7 @@
+ }
+
+ bs = spi_master_get_devdata(master);
++ init_completion(&bs->done);
+
+ platform_set_drvdata(pdev, master);
+ bs->pdev = pdev;
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-bfin-sport.c linux-3.14.72/drivers/spi/spi-bfin-sport.c
+--- linux-3.14.72.orig/drivers/spi/spi-bfin-sport.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-bfin-sport.c 2016-06-19 22:11:55.313139482 +0200
+@@ -8,7 +8,6 @@
+ * Licensed under the GPL-2 or later.
+ */
+
+-#include <linux/init.h>
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-bitbang.c linux-3.14.72/drivers/spi/spi-bitbang.c
+--- linux-3.14.72.orig/drivers/spi/spi-bitbang.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-bitbang.c 2016-06-19 22:11:55.313139482 +0200
+@@ -16,7 +16,6 @@
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+-#include <linux/init.h>
+ #include <linux/spinlock.h>
+ #include <linux/workqueue.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi.c linux-3.14.72/drivers/spi/spi.c
+--- linux-3.14.72.orig/drivers/spi/spi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi.c 2016-06-19 22:11:55.313139482 +0200
+@@ -24,9 +24,12 @@
+ #include <linux/device.h>
+ #include <linux/init.h>
+ #include <linux/cache.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmaengine.h>
+ #include <linux/mutex.h>
+ #include <linux/of_device.h>
+ #include <linux/of_irq.h>
++#include <linux/clk/clk-conf.h>
+ #include <linux/slab.h>
+ #include <linux/mod_devicetable.h>
+ #include <linux/spi/spi.h>
+@@ -255,13 +258,16 @@
+ static int spi_drv_probe(struct device *dev)
+ {
+ const struct spi_driver *sdrv = to_spi_driver(dev->driver);
+- struct spi_device *spi = to_spi_device(dev);
+ int ret;
+
+- acpi_dev_pm_attach(&spi->dev, true);
+- ret = sdrv->probe(spi);
++ ret = of_clk_set_defaults(dev->of_node, false);
+ if (ret)
+- acpi_dev_pm_detach(&spi->dev, true);
++ return ret;
++
++ acpi_dev_pm_attach(dev, true);
++ ret = sdrv->probe(to_spi_device(dev));
++ if (ret)
++ acpi_dev_pm_detach(dev, true);
+
+ return ret;
+ }
+@@ -269,11 +275,10 @@
+ static int spi_drv_remove(struct device *dev)
+ {
+ const struct spi_driver *sdrv = to_spi_driver(dev->driver);
+- struct spi_device *spi = to_spi_device(dev);
+ int ret;
+
+- ret = sdrv->remove(spi);
+- acpi_dev_pm_detach(&spi->dev, true);
++ ret = sdrv->remove(to_spi_device(dev));
++ acpi_dev_pm_detach(dev, true);
+
+ return ret;
+ }
+@@ -345,14 +350,12 @@
+ struct spi_device *spi_alloc_device(struct spi_master *master)
+ {
+ struct spi_device *spi;
+- struct device *dev = master->dev.parent;
+
+ if (!spi_master_get(master))
+ return NULL;
+
+ spi = kzalloc(sizeof(*spi), GFP_KERNEL);
+ if (!spi) {
+- dev_err(dev, "cannot alloc spi_device\n");
+ spi_master_put(master);
+ return NULL;
+ }
+@@ -580,6 +583,192 @@
+ spi->master->set_cs(spi, !enable);
+ }
+
++#ifdef CONFIG_HAS_DMA
++static int spi_map_buf(struct spi_master *master, struct device *dev,
++ struct sg_table *sgt, void *buf, size_t len,
++ enum dma_data_direction dir)
++{
++ const bool vmalloced_buf = is_vmalloc_addr(buf);
++ const int desc_len = vmalloced_buf ? PAGE_SIZE : master->max_dma_len;
++ const int sgs = DIV_ROUND_UP(len, desc_len);
++ struct page *vm_page;
++ void *sg_buf;
++ size_t min;
++ int i, ret;
++
++ ret = sg_alloc_table(sgt, sgs, GFP_KERNEL);
++ if (ret != 0)
++ return ret;
++
++ for (i = 0; i < sgs; i++) {
++ min = min_t(size_t, len, desc_len);
++
++ if (vmalloced_buf) {
++ vm_page = vmalloc_to_page(buf);
++ if (!vm_page) {
++ sg_free_table(sgt);
++ return -ENOMEM;
++ }
++ sg_set_page(&sgt->sgl[i], vm_page,
++ min, offset_in_page(buf));
++ } else {
++ sg_buf = buf;
++ sg_set_buf(&sgt->sgl[i], sg_buf, min);
++ }
++
++
++ buf += min;
++ len -= min;
++ }
++
++ ret = dma_map_sg(dev, sgt->sgl, sgt->nents, dir);
++ if (!ret)
++ ret = -ENOMEM;
++ if (ret < 0) {
++ sg_free_table(sgt);
++ return ret;
++ }
++
++ sgt->nents = ret;
++
++ return 0;
++}
++
++static void spi_unmap_buf(struct spi_master *master, struct device *dev,
++ struct sg_table *sgt, enum dma_data_direction dir)
++{
++ if (sgt->orig_nents) {
++ dma_unmap_sg(dev, sgt->sgl, sgt->orig_nents, dir);
++ sg_free_table(sgt);
++ }
++}
++
++static int __spi_map_msg(struct spi_master *master, struct spi_message *msg)
++{
++ struct device *tx_dev, *rx_dev;
++ struct spi_transfer *xfer;
++ int ret;
++
++ if (!master->can_dma)
++ return 0;
++
++ tx_dev = master->dma_tx->device->dev;
++ rx_dev = master->dma_rx->device->dev;
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ if (!master->can_dma(master, msg->spi, xfer))
++ continue;
++
++ if (xfer->tx_buf != NULL) {
++ ret = spi_map_buf(master, tx_dev, &xfer->tx_sg,
++ (void *)xfer->tx_buf, xfer->len,
++ DMA_TO_DEVICE);
++ if (ret != 0)
++ return ret;
++ }
++
++ if (xfer->rx_buf != NULL) {
++ ret = spi_map_buf(master, rx_dev, &xfer->rx_sg,
++ xfer->rx_buf, xfer->len,
++ DMA_FROM_DEVICE);
++ if (ret != 0) {
++ spi_unmap_buf(master, tx_dev, &xfer->tx_sg,
++ DMA_TO_DEVICE);
++ return ret;
++ }
++ }
++ }
++
++ master->cur_msg_mapped = true;
++
++ return 0;
++}
++
++static int spi_unmap_msg(struct spi_master *master, struct spi_message *msg)
++{
++ struct spi_transfer *xfer;
++ struct device *tx_dev, *rx_dev;
++
++ if (!master->cur_msg_mapped || !master->can_dma)
++ return 0;
++
++ tx_dev = master->dma_tx->device->dev;
++ rx_dev = master->dma_rx->device->dev;
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ if (!master->can_dma(master, msg->spi, xfer))
++ continue;
++
++ spi_unmap_buf(master, rx_dev, &xfer->rx_sg, DMA_FROM_DEVICE);
++ spi_unmap_buf(master, tx_dev, &xfer->tx_sg, DMA_TO_DEVICE);
++ }
++
++ return 0;
++}
++#else /* !CONFIG_HAS_DMA */
++static inline int __spi_map_msg(struct spi_master *master,
++ struct spi_message *msg)
++{
++ return 0;
++}
++
++static inline int spi_unmap_msg(struct spi_master *master,
++ struct spi_message *msg)
++{
++ return 0;
++}
++#endif /* !CONFIG_HAS_DMA */
++
++static int spi_map_msg(struct spi_master *master, struct spi_message *msg)
++{
++ struct spi_transfer *xfer;
++ void *tmp;
++ unsigned int max_tx, max_rx;
++
++ if (master->flags & (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX)) {
++ max_tx = 0;
++ max_rx = 0;
++
++ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
++ if ((master->flags & SPI_MASTER_MUST_TX) &&
++ !xfer->tx_buf)
++ max_tx = max(xfer->len, max_tx);
++ if ((master->flags & SPI_MASTER_MUST_RX) &&
++ !xfer->rx_buf)
++ max_rx = max(xfer->len, max_rx);
++ }
++
++ if (max_tx) {
++ tmp = krealloc(master->dummy_tx, max_tx,
++ GFP_KERNEL | GFP_DMA);
++ if (!tmp)
++ return -ENOMEM;
++ master->dummy_tx = tmp;
++ memset(tmp, 0, max_tx);
++ }
++
++ if (max_rx) {
++ tmp = krealloc(master->dummy_rx, max_rx,
++ GFP_KERNEL | GFP_DMA);
++ if (!tmp)
++ return -ENOMEM;
++ master->dummy_rx = tmp;
++ }
++
++ if (max_tx || max_rx) {
++ list_for_each_entry(xfer, &msg->transfers,
++ transfer_list) {
++ if (!xfer->tx_buf)
++ xfer->tx_buf = master->dummy_tx;
++ if (!xfer->rx_buf)
++ xfer->rx_buf = master->dummy_rx;
++ }
++ }
++ }
++
++ return __spi_map_msg(master, msg);
++}
++
+ /*
+ * spi_transfer_one_message - Default implementation of transfer_one_message()
+ *
+@@ -591,9 +780,9 @@
+ struct spi_message *msg)
+ {
+ struct spi_transfer *xfer;
+- bool cur_cs = true;
+ bool keep_cs = false;
+ int ret = 0;
++ int ms = 1;
+
+ spi_set_cs(msg->spi, true);
+
+@@ -611,7 +800,16 @@
+
+ if (ret > 0) {
+ ret = 0;
+- wait_for_completion(&master->xfer_completion);
++ ms = xfer->len * 8 * 1000 / xfer->speed_hz;
++ ms += ms + 100; /* some tolerance */
++
++ ms = wait_for_completion_timeout(&master->xfer_completion,
++ msecs_to_jiffies(ms));
++ }
++
++ if (ms == 0) {
++ dev_err(&msg->spi->dev, "SPI transfer timed out\n");
++ msg->status = -ETIMEDOUT;
+ }
+
+ trace_spi_transfer_stop(msg, xfer);
+@@ -627,8 +825,9 @@
+ &msg->transfers)) {
+ keep_cs = true;
+ } else {
+- cur_cs = !cur_cs;
+- spi_set_cs(msg->spi, cur_cs);
++ spi_set_cs(msg->spi, false);
++ udelay(10);
++ spi_set_cs(msg->spi, true);
+ }
+ }
+
+@@ -686,6 +885,10 @@
+ }
+ master->busy = false;
+ spin_unlock_irqrestore(&master->queue_lock, flags);
++ kfree(master->dummy_rx);
++ master->dummy_rx = NULL;
++ kfree(master->dummy_tx);
++ master->dummy_tx = NULL;
+ if (master->unprepare_transfer_hardware &&
+ master->unprepare_transfer_hardware(master))
+ dev_err(&master->dev,
+@@ -752,6 +955,13 @@
+ master->cur_msg_prepared = true;
+ }
+
++ ret = spi_map_msg(master, master->cur_msg);
++ if (ret) {
++ master->cur_msg->status = ret;
++ spi_finalize_current_message(master);
++ return;
++ }
++
+ ret = master->transfer_one_message(master, master->cur_msg);
+ if (ret) {
+ dev_err(&master->dev,
+@@ -836,6 +1046,8 @@
+ mesg = master->cur_msg;
+ spin_unlock_irqrestore(&master->queue_lock, flags);
+
++ spi_unmap_msg(master, mesg);
++
+ if (master->cur_msg_prepared && master->unprepare_message) {
+ ret = master->unprepare_message(master, mesg);
+ if (ret) {
+@@ -894,7 +1106,7 @@
+ */
+ while ((!list_empty(&master->queue) || master->busy) && limit--) {
+ spin_unlock_irqrestore(&master->queue_lock, flags);
+- msleep(10);
++ usleep_range(10000, 11000);
+ spin_lock_irqsave(&master->queue_lock, flags);
+ }
+
+@@ -967,7 +1179,6 @@
+ {
+ int ret;
+
+- master->queued = true;
+ master->transfer = spi_queued_transfer;
+ if (!master->transfer_one_message)
+ master->transfer_one_message = spi_transfer_one_message;
+@@ -978,6 +1189,7 @@
+ dev_err(&master->dev, "problem initializing queue\n");
+ goto err_init_queue;
+ }
++ master->queued = true;
+ ret = spi_start_queue(master);
+ if (ret) {
+ dev_err(&master->dev, "problem starting queue\n");
+@@ -987,8 +1199,8 @@
+ return 0;
+
+ err_start_queue:
+-err_init_queue:
+ spi_destroy_queue(master);
++err_init_queue:
+ return ret;
+ }
+
+@@ -1050,6 +1262,8 @@
+ spi->mode |= SPI_CS_HIGH;
+ if (of_find_property(nc, "spi-3wire", NULL))
+ spi->mode |= SPI_3WIRE;
++ if (of_find_property(nc, "spi-lsb-first", NULL))
++ spi->mode |= SPI_LSB_FIRST;
+
+ /* Device DUAL/QUAD mode */
+ if (!of_property_read_u32(nc, "spi-tx-bus-width", &value)) {
+@@ -1063,11 +1277,10 @@
+ spi->mode |= SPI_TX_QUAD;
+ break;
+ default:
+- dev_err(&master->dev,
+- "spi-tx-bus-width %d not supported\n",
+- value);
+- spi_dev_put(spi);
+- continue;
++ dev_warn(&master->dev,
++ "spi-tx-bus-width %d not supported\n",
++ value);
++ break;
+ }
+ }
+
+@@ -1082,11 +1295,10 @@
+ spi->mode |= SPI_RX_QUAD;
+ break;
+ default:
+- dev_err(&master->dev,
+- "spi-rx-bus-width %d not supported\n",
+- value);
+- spi_dev_put(spi);
+- continue;
++ dev_warn(&master->dev,
++ "spi-rx-bus-width %d not supported\n",
++ value);
++ break;
+ }
+ }
+
+@@ -1373,6 +1585,8 @@
+ mutex_init(&master->bus_lock_mutex);
+ master->bus_lock_flag = 0;
+ init_completion(&master->xfer_completion);
++ if (!master->max_dma_len)
++ master->max_dma_len = INT_MAX;
+
+ /* register the device, then userspace will see it.
+ * registration fails if the bus ID is in use.
+@@ -1607,6 +1821,9 @@
+ if (!spi->bits_per_word)
+ spi->bits_per_word = 8;
+
++ if (!spi->max_speed_hz)
++ spi->max_speed_hz = spi->master->max_speed_hz;
++
+ if (spi->master->setup)
+ status = spi->master->setup(spi);
+
+@@ -1627,11 +1844,10 @@
+ {
+ struct spi_master *master = spi->master;
+ struct spi_transfer *xfer;
++ int w_size;
+
+ if (list_empty(&message->transfers))
+ return -EINVAL;
+- if (!message->complete)
+- return -EINVAL;
+
+ /* Half-duplex links include original MicroWire, and ones with
+ * only one data pin like SPI_3WIRE (switches direction) or where
+@@ -1662,12 +1878,13 @@
+ message->frame_length += xfer->len;
+ if (!xfer->bits_per_word)
+ xfer->bits_per_word = spi->bits_per_word;
+- if (!xfer->speed_hz) {
++
++ if (!xfer->speed_hz)
+ xfer->speed_hz = spi->max_speed_hz;
+- if (master->max_speed_hz &&
+- xfer->speed_hz > master->max_speed_hz)
+- xfer->speed_hz = master->max_speed_hz;
+- }
++
++ if (master->max_speed_hz &&
++ xfer->speed_hz > master->max_speed_hz)
++ xfer->speed_hz = master->max_speed_hz;
+
+ if (master->bits_per_word_mask) {
+ /* Only 32 bits fit in the mask */
+@@ -1678,12 +1895,24 @@
+ return -EINVAL;
+ }
+
++ /*
++ * SPI transfer length should be multiple of SPI word size
++ * where SPI word size should be power-of-two multiple
++ */
++ if (xfer->bits_per_word <= 8)
++ w_size = 1;
++ else if (xfer->bits_per_word <= 16)
++ w_size = 2;
++ else
++ w_size = 4;
++
++ /* No partial transfers accepted */
++ if (xfer->len % w_size)
++ return -EINVAL;
++
+ if (xfer->speed_hz && master->min_speed_hz &&
+ xfer->speed_hz < master->min_speed_hz)
+ return -EINVAL;
+- if (xfer->speed_hz && master->max_speed_hz &&
+- xfer->speed_hz > master->max_speed_hz)
+- return -EINVAL;
+
+ if (xfer->tx_buf && !xfer->tx_nbits)
+ xfer->tx_nbits = SPI_NBITS_SINGLE;
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-clps711x.c linux-3.14.72/drivers/spi/spi-clps711x.c
+--- linux-3.14.72.orig/drivers/spi/spi-clps711x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-clps711x.c 2016-06-19 22:11:55.313139482 +0200
+@@ -11,7 +11,6 @@
+
+ #include <linux/io.h>
+ #include <linux/clk.h>
+-#include <linux/init.h>
+ #include <linux/gpio.h>
+ #include <linux/delay.h>
+ #include <linux/module.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-gpio.c linux-3.14.72/drivers/spi/spi-gpio.c
+--- linux-3.14.72.orig/drivers/spi/spi-gpio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-gpio.c 2016-06-19 22:11:55.317139219 +0200
+@@ -19,7 +19,6 @@
+ */
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/platform_device.h>
+ #include <linux/gpio.h>
+ #include <linux/of.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-imx.c linux-3.14.72/drivers/spi/spi-imx.c
+--- linux-3.14.72.orig/drivers/spi/spi-imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-imx.c 2016-06-19 22:11:55.317139219 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2007, 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 Juergen Beisert
+ *
+ * This program is free software; you can redistribute it and/or
+@@ -21,9 +21,10 @@
+ #include <linux/clk.h>
+ #include <linux/completion.h>
+ #include <linux/delay.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
+ #include <linux/err.h>
+ #include <linux/gpio.h>
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/irq.h>
+@@ -38,6 +39,7 @@
+ #include <linux/of_device.h>
+ #include <linux/of_gpio.h>
+
++#include <linux/platform_data/dma-imx.h>
+ #include <linux/platform_data/spi-imx.h>
+
+ #define DRIVER_NAME "spi_imx"
+@@ -52,6 +54,12 @@
+ #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
+ #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
+
++/* The maximum bytes that a sdma BD can transfer.*/
++#define MAX_SDMA_BD_BYTES (1 << 15)
++/* 3 Sec for 1MB or less than 1MB, else change with the transfer length */
++#define IMX_DEFAULT_DMA_TIMEOUT (msecs_to_jiffies(3000))
++#define IMX_DMA_TIMEOUT(len) ((len < 0x100000) ? IMX_DEFAULT_DMA_TIMEOUT : \
++ len * IMX_DEFAULT_DMA_TIMEOUT / 0x100000)
+ struct spi_imx_config {
+ unsigned int speed_hz;
+ unsigned int bpw;
+@@ -96,6 +104,16 @@
+ const void *tx_buf;
+ unsigned int txfifo; /* number of words pushed in tx FIFO */
+
++ /* DMA */
++ unsigned int dma_is_inited;
++ unsigned int dma_finished;
++ bool usedma;
++ u32 rx_wml;
++ u32 tx_wml;
++ u32 rxt_wml;
++ struct completion dma_rx_completion;
++ struct completion dma_tx_completion;
++
+ const struct spi_imx_devtype_data *devtype_data;
+ int chipselect[0];
+ };
+@@ -182,9 +200,22 @@
+ return 7;
+ }
+
++static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
++ struct spi_transfer *transfer)
++{
++ struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
++
++ if (spi_imx->dma_is_inited &&
++ (transfer->len > spi_imx_get_fifosize(spi_imx)) &&
++ (transfer->len > spi_imx_get_fifosize(spi_imx)))
++ return true;
++ return false;
++}
++
+ #define MX51_ECSPI_CTRL 0x08
+ #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
+ #define MX51_ECSPI_CTRL_XCH (1 << 2)
++#define MX51_ECSPI_CTRL_SMC (1 << 3)
+ #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
+ #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
+ #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
+@@ -202,6 +233,18 @@
+ #define MX51_ECSPI_INT_TEEN (1 << 0)
+ #define MX51_ECSPI_INT_RREN (1 << 3)
+
++#define MX51_ECSPI_DMA 0x14
++#define MX51_ECSPI_DMA_TX_WML_OFFSET 0
++#define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
++#define MX51_ECSPI_DMA_RX_WML_OFFSET 16
++#define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
++#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
++#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
++
++#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
++#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
++#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
++
+ #define MX51_ECSPI_STAT 0x18
+ #define MX51_ECSPI_STAT_RR (1 << 3)
+
+@@ -258,17 +301,22 @@
+
+ static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
+ {
+- u32 reg;
++ u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
+
+- reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
+- reg |= MX51_ECSPI_CTRL_XCH;
++ if (!spi_imx->usedma)
++ reg |= MX51_ECSPI_CTRL_XCH;
++ else if (!spi_imx->dma_finished)
++ reg |= MX51_ECSPI_CTRL_SMC;
++ else
++ reg &= ~MX51_ECSPI_CTRL_SMC;
+ writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
+ }
+
+ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
+ struct spi_imx_config *config)
+ {
+- u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
++ u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
++ u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
+ u32 clk = config->speed_hz, delay;
+
+ /*
+@@ -320,6 +368,30 @@
+ else /* SCLK is _very_ slow */
+ usleep_range(delay, delay + 10);
+
++ /*
++ * Configure the DMA register: setup the watermark
++ * and enable DMA request.
++ */
++ if (spi_imx->dma_is_inited) {
++ dma = readl(spi_imx->base + MX51_ECSPI_DMA);
++
++ spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 4;
++ spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
++ spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
++ rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
++ tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
++ rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
++ dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
++ & ~MX51_ECSPI_DMA_RX_WML_MASK
++ & ~MX51_ECSPI_DMA_RXT_WML_MASK)
++ | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
++ |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
++ |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
++ |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
++
++ writel(dma, spi_imx->base + MX51_ECSPI_DMA);
++ }
++
+ return 0;
+ }
+
+@@ -731,7 +803,196 @@
+ return 0;
+ }
+
+-static int spi_imx_transfer(struct spi_device *spi,
++static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
++{
++ struct spi_master *master = spi_imx->bitbang.master;
++
++ if (master->dma_rx) {
++ dma_release_channel(master->dma_rx);
++ master->dma_rx = NULL;
++ }
++
++ if (master->dma_tx) {
++ dma_release_channel(master->dma_tx);
++ master->dma_tx = NULL;
++ }
++
++ spi_imx->dma_is_inited = 0;
++}
++
++static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
++ struct spi_master *master,
++ const struct resource *res)
++{
++ struct dma_slave_config slave_config = {};
++ int ret;
++
++ /* Prepare for TX DMA: */
++ master->dma_tx = dma_request_slave_channel(dev, "tx");
++ if (!master->dma_tx) {
++ dev_err(dev, "cannot get the TX DMA channel!\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ slave_config.direction = DMA_MEM_TO_DEV;
++ slave_config.dst_addr = res->start + MXC_CSPITXDATA;
++ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++ slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 4;
++ ret = dmaengine_slave_config(master->dma_tx, &slave_config);
++ if (ret) {
++ dev_err(dev, "error in TX dma configuration.\n");
++ goto err;
++ }
++
++ /* Prepare for RX : */
++ master->dma_rx = dma_request_slave_channel(dev, "rx");
++ if (!master->dma_rx) {
++ dev_dbg(dev, "cannot get the DMA channel.\n");
++ ret = -EINVAL;
++ goto err;
++ }
++
++ slave_config.direction = DMA_DEV_TO_MEM;
++ slave_config.src_addr = res->start + MXC_CSPIRXDATA;
++ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
++ slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
++ ret = dmaengine_slave_config(master->dma_rx, &slave_config);
++ if (ret) {
++ dev_err(dev, "error in RX dma configuration.\n");
++ goto err;
++ }
++
++ init_completion(&spi_imx->dma_rx_completion);
++ init_completion(&spi_imx->dma_tx_completion);
++ master->can_dma = spi_imx_can_dma;
++ master->max_dma_len = MAX_SDMA_BD_BYTES;
++ spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
++ SPI_MASTER_MUST_TX;
++ spi_imx->dma_is_inited = 1;
++
++ return 0;
++err:
++ spi_imx_sdma_exit(spi_imx);
++ return ret;
++}
++
++static void spi_imx_dma_rx_callback(void *cookie)
++{
++ struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
++
++ complete(&spi_imx->dma_rx_completion);
++}
++
++static void spi_imx_dma_tx_callback(void *cookie)
++{
++ struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
++
++ complete(&spi_imx->dma_tx_completion);
++}
++
++static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
++ struct spi_transfer *transfer)
++{
++ struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
++ int ret;
++ int left = 0;
++ struct spi_master *master = spi_imx->bitbang.master;
++ struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
++
++ if (tx) {
++ desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
++ tx->sgl, tx->nents, DMA_TO_DEVICE,
++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++ if (!desc_tx)
++ goto no_dma;
++
++ desc_tx->callback = spi_imx_dma_tx_callback;
++ desc_tx->callback_param = (void *)spi_imx;
++ dmaengine_submit(desc_tx);
++ }
++
++ if (rx) {
++ struct scatterlist *sgl_last = &rx->sgl[rx->nents - 1];
++ unsigned int orig_length = sgl_last->length;
++ int wml_mask = ~(spi_imx->rx_wml - 1);
++ /*
++ * Adjust the transfer lenth of the last scattlist if there are
++ * some tail data, use PIO read to get the tail data since DMA
++ * sometimes miss the last tail interrupt.
++ */
++ left = transfer->len % spi_imx->rx_wml;
++ if (left)
++ sgl_last->length = orig_length & wml_mask;
++
++ desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
++ rx->sgl, rx->nents, DMA_FROM_DEVICE,
++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
++ if (!desc_rx)
++ goto no_dma;
++
++ desc_rx->callback = spi_imx_dma_rx_callback;
++ desc_rx->callback_param = (void *)spi_imx;
++ dmaengine_submit(desc_rx);
++ }
++
++ reinit_completion(&spi_imx->dma_rx_completion);
++ reinit_completion(&spi_imx->dma_tx_completion);
++
++ /* Trigger the cspi module. */
++ spi_imx->dma_finished = 0;
++
++ spi_imx->devtype_data->trigger(spi_imx);
++
++ dma_async_issue_pending(master->dma_tx);
++ dma_async_issue_pending(master->dma_rx);
++ /* Wait SDMA to finish the data transfer.*/
++ ret = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
++ IMX_DMA_TIMEOUT(transfer->len));
++ if (!ret) {
++ pr_warn("%s %s: I/O Error in DMA TX:%x\n",
++ dev_driver_string(&master->dev),
++ dev_name(&master->dev), transfer->len);
++ dmaengine_terminate_all(master->dma_tx);
++ } else {
++ ret = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
++ IMX_DMA_TIMEOUT(transfer->len));
++ if (!ret) {
++ pr_warn("%s %s: I/O Error in DMA RX:%x\n",
++ dev_driver_string(&master->dev),
++ dev_name(&master->dev), transfer->len);
++ spi_imx->devtype_data->reset(spi_imx);
++ dmaengine_terminate_all(master->dma_rx);
++ } else if (left) {
++ /* read the tail data by PIO */
++ void *tmpbuf = transfer->rx_buf + transfer->len - left;
++
++ while (readl(spi_imx->base + MX51_ECSPI_STAT) & 0x8) {
++ *(char *)tmpbuf =
++ readl(spi_imx->base + MXC_CSPIRXDATA);
++ tmpbuf++;
++ }
++ }
++ }
++
++ spi_imx->dma_finished = 1;
++ spi_imx->devtype_data->trigger(spi_imx);
++
++ if (!ret)
++ ret = -ETIMEDOUT;
++ else if (ret > 0)
++ ret = transfer->len;
++
++ return ret;
++
++no_dma:
++ pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
++ dev_driver_string(&master->dev),
++ dev_name(&master->dev));
++ return -EAGAIN;
++}
++
++static int spi_imx_pio_transfer(struct spi_device *spi,
+ struct spi_transfer *transfer)
+ {
+ struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
+@@ -741,7 +1002,7 @@
+ spi_imx->count = transfer->len;
+ spi_imx->txfifo = 0;
+
+- init_completion(&spi_imx->xfer_done);
++ reinit_completion(&spi_imx->xfer_done);
+
+ spi_imx_push(spi_imx);
+
+@@ -752,6 +1013,24 @@
+ return transfer->len;
+ }
+
++static int spi_imx_transfer(struct spi_device *spi,
++ struct spi_transfer *transfer)
++{
++ int ret;
++ struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
++
++ if (spi_imx->bitbang.master->can_dma &&
++ spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
++ spi_imx->usedma = true;
++ ret = spi_imx_dma_transfer(spi_imx, transfer);
++ if (ret != -EAGAIN)
++ return ret;
++ }
++ spi_imx->usedma = false;
++
++ return spi_imx_pio_transfer(spi, transfer);
++}
++
+ static int spi_imx_setup(struct spi_device *spi)
+ {
+ struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
+@@ -778,13 +1057,13 @@
+ struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
+ int ret;
+
+- ret = clk_enable(spi_imx->clk_per);
++ ret = clk_prepare_enable(spi_imx->clk_per);
+ if (ret)
+ return ret;
+
+- ret = clk_enable(spi_imx->clk_ipg);
++ ret = clk_prepare_enable(spi_imx->clk_ipg);
+ if (ret) {
+- clk_disable(spi_imx->clk_per);
++ clk_disable_unprepare(spi_imx->clk_per);
+ return ret;
+ }
+
+@@ -796,8 +1075,8 @@
+ {
+ struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
+
+- clk_disable(spi_imx->clk_ipg);
+- clk_disable(spi_imx->clk_per);
++ clk_disable_unprepare(spi_imx->clk_ipg);
++ clk_disable_unprepare(spi_imx->clk_per);
+ return 0;
+ }
+
+@@ -880,12 +1159,12 @@
+
+ spi_imx->irq = platform_get_irq(pdev, 0);
+ if (spi_imx->irq < 0) {
+- ret = -EINVAL;
++ ret = spi_imx->irq;
+ goto out_master_put;
+ }
+
+ ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
+- DRIVER_NAME, spi_imx);
++ dev_name(&pdev->dev), spi_imx);
+ if (ret) {
+ dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
+ goto out_master_put;
+@@ -912,6 +1191,13 @@
+ goto out_put_per;
+
+ spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
++ /*
++ * Only validated on i.mx6 now, can remove the constrain if validated on
++ * other chips.
++ */
++ if (spi_imx->devtype_data == &imx51_ecspi_devtype_data
++ && spi_imx_sdma_init(&pdev->dev, spi_imx, master, res))
++ dev_err(&pdev->dev, "dma setup error,use pio instead\n");
+
+ spi_imx->devtype_data->reset(spi_imx);
+
+@@ -926,8 +1212,8 @@
+
+ dev_info(&pdev->dev, "probed\n");
+
+- clk_disable(spi_imx->clk_ipg);
+- clk_disable(spi_imx->clk_per);
++ clk_disable_unprepare(spi_imx->clk_ipg);
++ clk_disable_unprepare(spi_imx->clk_per);
+ return ret;
+
+ out_clk_put:
+@@ -950,6 +1236,7 @@
+ writel(0, spi_imx->base + MXC_CSPICTRL);
+ clk_unprepare(spi_imx->clk_ipg);
+ clk_unprepare(spi_imx->clk_per);
++ spi_imx_sdma_exit(spi_imx);
+ spi_master_put(master);
+
+ return 0;
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-mpc512x-psc.c linux-3.14.72/drivers/spi/spi-mpc512x-psc.c
+--- linux-3.14.72.orig/drivers/spi/spi-mpc512x-psc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-mpc512x-psc.c 2016-06-19 22:11:55.317139219 +0200
+@@ -16,7 +16,6 @@
+
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+-#include <linux/init.h>
+ #include <linux/errno.h>
+ #include <linux/interrupt.h>
+ #include <linux/of_address.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-mpc52xx.c linux-3.14.72/drivers/spi/spi-mpc52xx.c
+--- linux-3.14.72.orig/drivers/spi/spi-mpc52xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-mpc52xx.c 2016-06-19 22:11:55.317139219 +0200
+@@ -12,7 +12,6 @@
+ */
+
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/errno.h>
+ #include <linux/of_platform.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-mpc52xx-psc.c linux-3.14.72/drivers/spi/spi-mpc52xx-psc.c
+--- linux-3.14.72.orig/drivers/spi/spi-mpc52xx-psc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-mpc52xx-psc.c 2016-06-19 22:11:55.317139219 +0200
+@@ -12,7 +12,6 @@
+ */
+
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/types.h>
+ #include <linux/errno.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-mxs.c linux-3.14.72/drivers/spi/spi-mxs.c
+--- linux-3.14.72.orig/drivers/spi/spi-mxs.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-mxs.c 2016-06-19 22:11:55.317139219 +0200
+@@ -29,7 +29,6 @@
+ */
+
+ #include <linux/kernel.h>
+-#include <linux/init.h>
+ #include <linux/ioport.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-nuc900.c linux-3.14.72/drivers/spi/spi-nuc900.c
+--- linux-3.14.72.orig/drivers/spi/spi-nuc900.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-nuc900.c 2016-06-19 22:11:55.317139219 +0200
+@@ -9,7 +9,6 @@
+ */
+
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/spinlock.h>
+ #include <linux/workqueue.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-octeon.c linux-3.14.72/drivers/spi/spi-octeon.c
+--- linux-3.14.72.orig/drivers/spi/spi-octeon.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-octeon.c 2016-06-19 22:11:55.317139219 +0200
+@@ -11,7 +11,6 @@
+ #include <linux/spi/spi.h>
+ #include <linux/module.h>
+ #include <linux/delay.h>
+-#include <linux/init.h>
+ #include <linux/io.h>
+ #include <linux/of.h>
+
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-oc-tiny.c linux-3.14.72/drivers/spi/spi-oc-tiny.c
+--- linux-3.14.72.orig/drivers/spi/spi-oc-tiny.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-oc-tiny.c 2016-06-19 22:11:55.317139219 +0200
+@@ -15,7 +15,6 @@
+ * published by the Free Software Foundation.
+ */
+
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/errno.h>
+ #include <linux/module.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-omap2-mcspi.c linux-3.14.72/drivers/spi/spi-omap2-mcspi.c
+--- linux-3.14.72.orig/drivers/spi/spi-omap2-mcspi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-omap2-mcspi.c 2016-06-19 22:11:55.317139219 +0200
+@@ -22,7 +22,6 @@
+ */
+
+ #include <linux/kernel.h>
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/module.h>
+ #include <linux/device.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-orion.c linux-3.14.72/drivers/spi/spi-orion.c
+--- linux-3.14.72.orig/drivers/spi/spi-orion.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-orion.c 2016-06-19 22:11:55.317139219 +0200
+@@ -9,7 +9,6 @@
+ * published by the Free Software Foundation.
+ */
+
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+ #include <linux/platform_device.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-ppc4xx.c linux-3.14.72/drivers/spi/spi-ppc4xx.c
+--- linux-3.14.72.orig/drivers/spi/spi-ppc4xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-ppc4xx.c 2016-06-19 22:11:55.317139219 +0200
+@@ -24,7 +24,6 @@
+ */
+
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
+ #include <linux/errno.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-pxa2xx-dma.c linux-3.14.72/drivers/spi/spi-pxa2xx-dma.c
+--- linux-3.14.72.orig/drivers/spi/spi-pxa2xx-dma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-pxa2xx-dma.c 2016-06-19 22:11:55.317139219 +0200
+@@ -9,7 +9,6 @@
+ * published by the Free Software Foundation.
+ */
+
+-#include <linux/init.h>
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/dmaengine.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-pxa2xx-pxadma.c linux-3.14.72/drivers/spi/spi-pxa2xx-pxadma.c
+--- linux-3.14.72.orig/drivers/spi/spi-pxa2xx-pxadma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-pxa2xx-pxadma.c 2016-06-19 22:11:55.317139219 +0200
+@@ -18,7 +18,6 @@
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+-#include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-s3c24xx.c linux-3.14.72/drivers/spi/spi-s3c24xx.c
+--- linux-3.14.72.orig/drivers/spi/spi-s3c24xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-s3c24xx.c 2016-06-19 22:11:55.317139219 +0200
+@@ -9,7 +9,6 @@
+ *
+ */
+
+-#include <linux/init.h>
+ #include <linux/spinlock.h>
+ #include <linux/workqueue.h>
+ #include <linux/interrupt.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-s3c64xx.c linux-3.14.72/drivers/spi/spi-s3c64xx.c
+--- linux-3.14.72.orig/drivers/spi/spi-s3c64xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-s3c64xx.c 2016-06-19 22:11:55.317139219 +0200
+@@ -381,7 +381,7 @@
+ #else
+
+ static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
+- unsigned len, dma_addr_t buf)
++ struct sg_table *sgt)
+ {
+ struct s3c64xx_spi_driver_data *sdd;
+ struct dma_slave_config config;
+@@ -407,8 +407,8 @@
+ dmaengine_slave_config(dma->ch, &config);
+ }
+
+- desc = dmaengine_prep_slave_single(dma->ch, buf, len,
+- dma->direction, DMA_PREP_INTERRUPT);
++ desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
++ dma->direction, DMA_PREP_INTERRUPT);
+
+ desc->callback = s3c64xx_spi_dmacb;
+ desc->callback_param = dma;
+@@ -515,7 +515,11 @@
+ chcfg |= S3C64XX_SPI_CH_TXCH_ON;
+ if (dma_mode) {
+ modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
++#ifndef CONFIG_S3C_DMA
++ prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
++#else
+ prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma);
++#endif
+ } else {
+ switch (sdd->cur_bpw) {
+ case 32:
+@@ -547,7 +551,11 @@
+ writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
+ | S3C64XX_SPI_PACKET_CNT_EN,
+ regs + S3C64XX_SPI_PACKET_CNT);
++#ifndef CONFIG_S3C_DMA
++ prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
++#else
+ prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma);
++#endif
+ }
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-sh-msiof.c linux-3.14.72/drivers/spi/spi-sh-msiof.c
+--- linux-3.14.72.orig/drivers/spi/spi-sh-msiof.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-sh-msiof.c 2016-06-19 22:11:55.317139219 +0200
+@@ -15,7 +15,6 @@
+ #include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/gpio.h>
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-sh-sci.c linux-3.14.72/drivers/spi/spi-sh-sci.c
+--- linux-3.14.72.orig/drivers/spi/spi-sh-sci.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-sh-sci.c 2016-06-19 22:11:55.317139219 +0200
+@@ -14,7 +14,6 @@
+ */
+
+ #include <linux/kernel.h>
+-#include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/spinlock.h>
+ #include <linux/workqueue.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-tegra114.c linux-3.14.72/drivers/spi/spi-tegra114.c
+--- linux-3.14.72.orig/drivers/spi/spi-tegra114.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-tegra114.c 2016-06-19 22:11:55.317139219 +0200
+@@ -23,7 +23,6 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/dmapool.h>
+ #include <linux/err.h>
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-tegra20-sflash.c linux-3.14.72/drivers/spi/spi-tegra20-sflash.c
+--- linux-3.14.72.orig/drivers/spi/spi-tegra20-sflash.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-tegra20-sflash.c 2016-06-19 22:11:55.317139219 +0200
+@@ -22,7 +22,6 @@
+ #include <linux/completion.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-tegra20-slink.c linux-3.14.72/drivers/spi/spi-tegra20-slink.c
+--- linux-3.14.72.orig/drivers/spi/spi-tegra20-slink.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-tegra20-slink.c 2016-06-19 22:11:55.321138957 +0200
+@@ -23,7 +23,6 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/dmapool.h>
+ #include <linux/err.h>
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-xcomm.c linux-3.14.72/drivers/spi/spi-xcomm.c
+--- linux-3.14.72.orig/drivers/spi/spi-xcomm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-xcomm.c 2016-06-19 22:11:55.321138957 +0200
+@@ -8,7 +8,6 @@
+ */
+
+ #include <linux/kernel.h>
+-#include <linux/init.h>
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/i2c.h>
+diff -Nur linux-3.14.72.orig/drivers/spi/spi-xilinx.c linux-3.14.72/drivers/spi/spi-xilinx.c
+--- linux-3.14.72.orig/drivers/spi/spi-xilinx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/spi/spi-xilinx.c 2016-06-19 22:11:55.321138957 +0200
+@@ -14,7 +14,6 @@
+ */
+
+ #include <linux/module.h>
+-#include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+diff -Nur linux-3.14.72.orig/drivers/staging/media/lirc/Kconfig linux-3.14.72/drivers/staging/media/lirc/Kconfig
+--- linux-3.14.72.orig/drivers/staging/media/lirc/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/staging/media/lirc/Kconfig 2016-06-19 22:11:55.321138957 +0200
+@@ -38,6 +38,12 @@
+ help
+ Driver for Homebrew Parallel Port Receivers
+
++config LIRC_GPIO
++ tristate "Homebrew GPIO Port Receiver/Transmitter"
++ depends on LIRC
++ help
++ Driver for Homebrew GPIO Port Receiver/Transmitter
++
+ config LIRC_SASEM
+ tristate "Sasem USB IR Remote"
+ depends on LIRC && USB
+diff -Nur linux-3.14.72.orig/drivers/staging/media/lirc/lirc_gpio.c linux-3.14.72/drivers/staging/media/lirc/lirc_gpio.c
+--- linux-3.14.72.orig/drivers/staging/media/lirc/lirc_gpio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/staging/media/lirc/lirc_gpio.c 2016-06-19 22:11:55.321138957 +0200
+@@ -0,0 +1,782 @@
++/*
++ * lirc_gpio.c
++ *
++ * lirc_gpio - Device driver that records pulse- and pause-lengths
++ * (space-lengths) (just like the lirc_serial driver does)
++ * between GPIO interrupt events on GPIO capable devices.
++ * Lots of code has been taken from the lirc_serial and the
++ * lirc_rpi modules so I would like say thanks to the authors.
++ *
++ * Copyright (C) 2014 CurlyMo <curlymoo1@gmail.com>
++ * Aron Robert Szabo <aron@reon.hu>,
++ * Michael Bishop <cleverca22@gmail.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++/*
++ lirc_gpio {
++ compatible = "lirc_gpio";
++ gpios = <&gpio3 6 1 &gpio3 7 2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_hummingboard_gpio3_6>;
++ pinctrl-1 = <&pinctrl_hummingboard_gpio3_7>;
++ linux,sense = <-1>;
++ linux,softcarrier = <1>;
++ linux,validgpios = <1 73 72 71 70 194 195 67>;
++ };
++ */
++
++
++#include <linux/module.h>
++#include <linux/errno.h>
++#include <linux/interrupt.h>
++#include <linux/sched.h>
++#include <linux/kernel.h>
++#include <linux/time.h>
++#include <linux/string.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/irq.h>
++#include <linux/spinlock.h>
++#include <media/lirc.h>
++#include <media/lirc_dev.h>
++#include <linux/gpio.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++
++#define LIRC_DRIVER_NAME "lirc_gpio"
++#define RBUF_LEN 256
++#define LIRC_TRANSMITTER_LATENCY 256
++
++#ifndef MAX_UDELAY_MS
++#define MAX_UDELAY_US 5000
++#else
++#define MAX_UDELAY_US (MAX_UDELAY_MS*1000)
++#endif
++
++static ssize_t lirc_write(struct file *file, const char *buf, size_t n, loff_t *ppos);
++static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
++static int set_use_inc(void *data);
++static void set_use_dec(void *data);
++static int lirc_gpio_probe(struct platform_device *pdev);
++static int lirc_gpio_remove(struct platform_device *pdev);
++
++struct lirc_gpio_platform_data {
++ int gpio_rx_nr;
++ int gpio_tx_nr;
++ bool active_rx_low;
++ bool active_tx_low;
++ u64 allowed_rx_protos;
++ u64 allowed_tx_protos;
++ int sense;
++ int softcarrier;
++ int validgpios[255];
++};
++
++struct lirc_gpio_dev {
++ int gpio_rx_nr;
++ int gpio_tx_nr;
++ int sense;
++ int softcarrier;
++ int validgpios[255];
++};
++
++struct lirc_gpio_dev *gpio_dev;
++
++static const struct file_operations lirc_fops = {
++ .owner = THIS_MODULE,
++ .write = lirc_write,
++ .unlocked_ioctl = lirc_ioctl,
++ .read = lirc_dev_fop_read,
++ .poll = lirc_dev_fop_poll,
++ .open = lirc_dev_fop_open,
++ .release = lirc_dev_fop_close,
++ .llseek = no_llseek,
++};
++
++struct irq_chip *irqchip;
++struct irq_data *irqdata;
++
++static struct timeval lasttv = { 0, 0 };
++static struct lirc_buffer rbuf;
++static spinlock_t lock;
++
++/* set the default GPIO input pin */
++static int gpio_in_pin = -1;
++/* set the default GPIO output pin */
++static int gpio_out_pin = -1;
++/* -1 = auto, 0 = active high, 1 = active low */
++static int sense = -2;
++/* use softcarrier by default */
++static int softcarrier = -1;
++
++/* initialized/set in init_timing_params() */
++static unsigned int freq = 38000;
++static unsigned int duty_cycle = 50;
++static unsigned long period;
++static unsigned long pulse_width;
++static unsigned long space_width;
++
++static struct lirc_driver driver = {
++ .name = LIRC_DRIVER_NAME,
++ .minor = -1,
++ .code_length = 1,
++ .sample_rate = 0,
++ .data = NULL,
++ .add_to_buf = NULL,
++ .rbuf = &rbuf,
++ .set_use_inc = set_use_inc,
++ .set_use_dec = set_use_dec,
++ .fops = &lirc_fops,
++ .dev = NULL,
++ .owner = THIS_MODULE,
++};
++
++static struct of_device_id lirc_gpio_of_match[] = {
++ { .compatible = "lirc_gpio", },
++ {}
++};
++
++static struct platform_driver lirc_gpio_driver = {
++ .probe = lirc_gpio_probe,
++ .remove = lirc_gpio_remove,
++ .driver = {
++ .name = LIRC_DRIVER_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = lirc_gpio_of_match,
++ },
++};
++
++static void safe_udelay(unsigned long usecs) {
++ while (usecs > MAX_UDELAY_US) {
++ udelay(MAX_UDELAY_US);
++ usecs -= MAX_UDELAY_US;
++ }
++ udelay(usecs);
++}
++
++static int init_timing_params(unsigned int new_duty_cycle, unsigned int new_freq) {
++ /*
++ * period, pulse/space width are kept with 8 binary places -
++ * IE multiplied by 256.
++ */
++ if(256 * 1000000L / new_freq * new_duty_cycle / 100 <=
++ LIRC_TRANSMITTER_LATENCY)
++ return -EINVAL;
++ if(256 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <=
++ LIRC_TRANSMITTER_LATENCY)
++ return -EINVAL;
++ duty_cycle = new_duty_cycle;
++ freq = new_freq;
++ period = 256 * 1000000L / freq;
++ pulse_width = period * duty_cycle / 100;
++ space_width = period - pulse_width;
++ return 0;
++}
++
++
++static long send_pulse_softcarrier(unsigned long length) {
++ int flag;
++ unsigned long actual, target, d;
++
++ if(gpio_dev->gpio_tx_nr >= 0) {
++ length <<= 8;
++
++ actual = 0; target = 0; flag = 0;
++ while(actual < length) {
++ if(flag) {
++ gpio_set_value(gpio_dev->gpio_tx_nr, 0);
++ target += space_width;
++ } else {
++ gpio_set_value(gpio_dev->gpio_tx_nr, 1);
++ target += pulse_width;
++ }
++ d = (target - actual - LIRC_TRANSMITTER_LATENCY + 128) >> 8;
++ /*
++ * Note - we've checked in ioctl that the pulse/space
++ * widths are big enough so that d is > 0
++ */
++ udelay(d);
++ actual += (d << 8) + LIRC_TRANSMITTER_LATENCY;
++ flag = !flag;
++ }
++ return (actual-length) >> 8;
++ }
++ return 0;
++}
++
++static long send_pulse(unsigned long length) {
++ if(length <= 0)
++ return 0;
++
++ if(gpio_dev->gpio_tx_nr >= 0) {
++ if(gpio_dev->softcarrier) {
++ return send_pulse_softcarrier(length);
++ } else {
++ gpio_set_value(gpio_dev->gpio_tx_nr, 1);
++ safe_udelay(length);
++ return 0;
++ }
++ }
++ return 0;
++}
++
++static void send_space(long length) {
++ if(gpio_dev->gpio_tx_nr >= 0) {
++ gpio_set_value(gpio_dev->gpio_tx_nr, 0);
++ if(length <= 0)
++ return;
++ safe_udelay(length);
++ }
++}
++
++static void rbwrite(int l) {
++ if (lirc_buffer_full(&rbuf)) {
++ /* no new signals will be accepted */
++ return;
++ }
++ lirc_buffer_write(&rbuf, (void *)&l);
++}
++
++static void frbwrite(int l) {
++ /* simple noise filter */
++ static int pulse, space;
++ static unsigned int ptr;
++
++ if(ptr > 0 && (l & PULSE_BIT)) {
++ pulse += l & PULSE_MASK;
++ if(pulse > 250) {
++ rbwrite(space);
++ rbwrite(pulse | PULSE_BIT);
++ ptr = 0;
++ pulse = 0;
++ }
++ return;
++ }
++ if(!(l & PULSE_BIT)) {
++ if(ptr == 0) {
++ if (l > 20000) {
++ space = l;
++ ptr++;
++ return;
++ }
++ } else {
++ if(l > 20000) {
++ space += pulse;
++ if (space > PULSE_MASK)
++ space = PULSE_MASK;
++ space += l;
++ if (space > PULSE_MASK)
++ space = PULSE_MASK;
++ pulse = 0;
++ return;
++ }
++ rbwrite(space);
++ rbwrite(pulse | PULSE_BIT);
++ ptr = 0;
++ pulse = 0;
++ }
++ }
++ rbwrite(l);
++}
++
++static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs) {
++ struct timeval tv;
++ long deltv;
++ int data;
++ int signal;
++
++ /* use the GPIO signal level */
++ signal = gpio_get_value(gpio_dev->gpio_rx_nr);
++
++ /* unmask the irq */
++ irqchip->irq_unmask(irqdata);
++
++ if(gpio_dev->sense != -1) {
++ /* The HB GPIO input acts like it is an analogue input.
++ Therefor a high signal is 256 and a low signal is 1.
++ For Lirc to properly interpret the spaces and pulses,
++ we need to transform these to ones and zeros. To be
++ on the safe side, every signal higher then 128 will
++ be interpreted as a high and vice versa. */
++ if (signal > 128) {
++ signal = 1;
++ } else {
++ signal = 0;
++ }
++ /* get current time */
++ do_gettimeofday(&tv);
++
++ /* calc time since last interrupt in microseconds */
++ deltv = tv.tv_sec-lasttv.tv_sec;
++ if(tv.tv_sec < lasttv.tv_sec ||
++ (tv.tv_sec == lasttv.tv_sec &&
++ tv.tv_usec < lasttv.tv_usec)) {
++ printk(KERN_WARNING LIRC_DRIVER_NAME
++ ": AIEEEE: your clock just jumped backwards\n");
++ printk(KERN_WARNING LIRC_DRIVER_NAME
++ ": %d %d %lx %lx %lx %lx\n", signal, gpio_dev->sense,
++ tv.tv_sec, lasttv.tv_sec,
++ tv.tv_usec, lasttv.tv_usec);
++ data = PULSE_MASK;
++ } else if (deltv > 15) {
++ data = PULSE_MASK; /* really long time */
++ if(!(signal^gpio_dev->sense)) {
++ /* sanity check */
++ printk(KERN_WARNING LIRC_DRIVER_NAME
++ ": AIEEEE: %d %d %lx %lx %lx %lx\n",
++ signal, gpio_dev->sense, tv.tv_sec, lasttv.tv_sec,
++ tv.tv_usec, lasttv.tv_usec);
++ /*
++ * detecting pulse while this
++ * MUST be a space!
++ */
++ gpio_dev->sense = gpio_dev->sense ? 0 : 1;
++ }
++ } else {
++ data = (int) (deltv*1000000 +
++ (tv.tv_usec - lasttv.tv_usec));
++ }
++ frbwrite(signal^gpio_dev->sense ? data : (data|PULSE_BIT));
++ lasttv = tv;
++ wake_up_interruptible(&rbuf.wait_poll);
++ }
++
++ return IRQ_HANDLED;
++}
++
++// called when the character device is opened
++static int set_use_inc(void *data) {
++ int result;
++ unsigned long flags;
++
++ /* initialize timestamp */
++ do_gettimeofday(&lasttv);
++
++ if(gpio_dev->gpio_rx_nr >= 0) {
++ result = request_irq(gpio_to_irq(gpio_dev->gpio_rx_nr),
++ (irq_handler_t) irq_handler, 0,
++ LIRC_DRIVER_NAME, (void*) 0);
++
++ switch (result) {
++ case -EBUSY:
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": IRQ %d is busy\n",
++ gpio_to_irq(gpio_dev->gpio_rx_nr));
++ return -EBUSY;
++ case -EINVAL:
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": Bad irq number or handler\n");
++ return -EINVAL;
++ default:
++ break;
++ };
++
++ /* initialize pulse/space widths */
++ init_timing_params(duty_cycle, freq);
++
++ spin_lock_irqsave(&lock, flags);
++
++ /* GPIO Pin Falling/Rising Edge Detect Enable */
++ irqchip->irq_set_type(irqdata,
++ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING);
++
++ /* unmask the irq */
++ irqchip->irq_unmask(irqdata);
++
++ spin_unlock_irqrestore(&lock, flags);
++ }
++
++ return 0;
++}
++
++static void set_use_dec(void *data) {
++ unsigned long flags;
++ if(gpio_dev->gpio_rx_nr >= 0) {
++ spin_lock_irqsave(&lock, flags);
++
++ /* GPIO Pin Falling/Rising Edge Detect Disable */
++ irqchip->irq_set_type(irqdata, 0);
++ irqchip->irq_mask(irqdata);
++
++ spin_unlock_irqrestore(&lock, flags);
++
++ free_irq(gpio_to_irq(gpio_dev->gpio_rx_nr), (void *) 0);
++ }
++}
++
++static ssize_t lirc_write(struct file *file, const char *buf, size_t n, loff_t *ppos) {
++ int i, count;
++ unsigned long flags;
++ long delta = 0;
++ int *wbuf;
++
++ if(gpio_dev->gpio_tx_nr >= 0) {
++ count = n / sizeof(int);
++ if(n % sizeof(int) || count % 2 == 0)
++ return -EINVAL;
++ wbuf = memdup_user(buf, n);
++ if(IS_ERR(wbuf))
++ return PTR_ERR(wbuf);
++ spin_lock_irqsave(&lock, flags);
++
++ for(i = 0; i < count; i++) {
++ if(i%2)
++ send_space(wbuf[i] - delta);
++ else
++ delta = send_pulse(wbuf[i]);
++ }
++ gpio_set_value(gpio_dev->gpio_tx_nr, 0);
++
++ spin_unlock_irqrestore(&lock, flags);
++ kfree(wbuf);
++ return n;
++ }
++ return 0;
++}
++
++
++static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) {
++ int result;
++ __u32 value;
++
++ switch(cmd) {
++ case LIRC_GET_SEND_MODE:
++ return -ENOIOCTLCMD;
++ break;
++
++ case LIRC_SET_SEND_MODE:
++ result = get_user(value, (__u32 *) arg);
++ if(result)
++ return result;
++ /* only LIRC_MODE_PULSE supported */
++ if(value != LIRC_MODE_PULSE)
++ return -ENOSYS;
++ break;
++
++ case LIRC_GET_LENGTH:
++ return -ENOSYS;
++ break;
++
++ case LIRC_SET_SEND_DUTY_CYCLE:
++ result = get_user(value, (__u32 *) arg);
++ if (result)
++ return result;
++ if (value <= 0 || value > 100)
++ return -EINVAL;
++ return init_timing_params(value, freq);
++ break;
++
++ case LIRC_SET_SEND_CARRIER:
++ result = get_user(value, (__u32 *) arg);
++ if(result)
++ return result;
++ if(value > 500000 || value < 20000)
++ return -EINVAL;
++ return init_timing_params(duty_cycle, value);
++ break;
++
++ default:
++ return lirc_dev_fop_ioctl(filep, cmd, arg);
++ }
++ return 0;
++}
++
++static int lirc_gpio_get_devtree_pdata(struct device *dev, struct lirc_gpio_platform_data *pdata) {
++ struct device_node *np = dev->of_node;
++ enum of_gpio_flags flags;
++ struct property *prop;
++ const __be32 *cur;
++ int gpio = -1;
++ int ret = 0;
++ int i = 0;
++
++ if(np) {
++ gpio = of_get_gpio_flags(np, 0, &flags);
++ if(gpio < 0) {
++ if(gpio != -EPROBE_DEFER)
++ dev_err(dev, "RX gpio not defined (%d)\n", gpio);
++
++ pdata->gpio_rx_nr = -1;
++ pdata->active_rx_low = 0;
++ pdata->allowed_rx_protos = 0;
++ } else {
++ pdata->gpio_rx_nr = gpio;
++ pdata->active_rx_low = (flags & OF_GPIO_ACTIVE_LOW);
++ pdata->allowed_rx_protos = 0;
++ }
++
++ gpio = of_get_gpio_flags(np, 1, &flags);
++ if(gpio < 0) {
++ if(gpio != -EPROBE_DEFER)
++ dev_err(dev, "TX gpio not defined (%d)\n", gpio);
++
++ pdata->gpio_tx_nr = -1;
++ pdata->active_tx_low = 0;
++ pdata->allowed_tx_protos = 0;
++ } else {
++ pdata->gpio_tx_nr = gpio;
++ pdata->active_tx_low = (flags & OF_GPIO_ACTIVE_LOW);
++ pdata->allowed_tx_protos = 0;
++ }
++ ret = of_property_read_u32(np, "linux,sense", &pdata->sense);
++ if(ret) {
++ pdata->sense = -1;
++ }
++ ret = of_property_read_u32(np, "linux,softcarrier", &pdata->softcarrier);
++ if(ret) {
++ pdata->softcarrier = 1;
++ }
++ i = 0;
++ printk(KERN_DEBUG LIRC_DRIVER_NAME ": valid gpios");
++ of_property_for_each_u32(np, "linux,validgpios", prop, cur, gpio) {
++ printk(" %d", gpio);
++ pdata->validgpios[i++] = gpio;
++ }
++ printk("\n");
++ pdata->validgpios[i] = -1;
++ }
++
++ return 0;
++}
++
++static int init_port(void) {
++ int i, nlow, nhigh, ret, irq;
++
++ if(gpio_dev->gpio_tx_nr >= 0) {
++ if(gpio_request(gpio_dev->gpio_tx_nr, LIRC_DRIVER_NAME " ir/out")) {
++ printk(KERN_ALERT LIRC_DRIVER_NAME ": cant claim gpio pin %d\n", gpio_dev->gpio_tx_nr);
++ ret = -ENODEV;
++ goto exit_init_port;
++ }
++ }
++
++ if(gpio_dev->gpio_rx_nr >= 0) {
++ if(gpio_request(gpio_dev->gpio_rx_nr, LIRC_DRIVER_NAME " ir/in")) {
++ printk(KERN_ALERT LIRC_DRIVER_NAME ": cant claim gpio pin %d\n", gpio_dev->gpio_rx_nr);
++ ret = -ENODEV;
++ goto exit_gpio_free_out_pin;
++ }
++ }
++
++ if(gpio_dev->gpio_rx_nr >= 0) {
++ gpio_direction_input(gpio_dev->gpio_rx_nr);
++ }
++ if(gpio_dev->gpio_tx_nr >= 0) {
++ gpio_direction_output(gpio_dev->gpio_tx_nr, 1);
++ gpio_set_value(gpio_dev->gpio_tx_nr, 0);
++ }
++
++ if(gpio_dev->gpio_rx_nr >= 0) {
++ irq = gpio_to_irq(gpio_dev->gpio_rx_nr);
++ irqdata = irq_get_irq_data(irq);
++
++ if(irqdata && irqdata->chip) {
++ irqchip = irqdata->chip;
++ } else {
++ ret = -ENODEV;
++ goto exit_gpio_free_in_pin;
++ }
++
++ /* if pin is high, then this must be an active low receiver. */
++ if(gpio_dev->sense == -1) {
++ /* wait 1/2 sec for the power supply */
++ msleep(500);
++
++ /*
++ * probe 9 times every 0.04s, collect "votes" for
++ * active high/low
++ */
++ nlow = 0;
++ nhigh = 0;
++ for(i = 0; i < 9; i++) {
++ if(gpio_get_value(gpio_dev->gpio_rx_nr))
++ nlow++;
++ else
++ nhigh++;
++ msleep(40);
++ }
++ gpio_dev->sense = (nlow >= nhigh ? 1 : 0);
++ printk(KERN_INFO LIRC_DRIVER_NAME ": auto-detected active %s receiver on GPIO pin %d\n",
++ gpio_dev->sense ? "low" : "high", gpio_dev->gpio_rx_nr);
++ } else {
++ printk(KERN_INFO LIRC_DRIVER_NAME ": manually using active %s receiver on GPIO pin %d\n",
++ gpio_dev->sense ? "low" : "high", gpio_dev->gpio_rx_nr);
++ }
++ }
++
++ return 0;
++
++exit_gpio_free_in_pin:
++ gpio_free(gpio_dev->gpio_rx_nr);
++
++exit_gpio_free_out_pin:
++ gpio_free(gpio_dev->gpio_tx_nr);
++
++exit_init_port:
++ return ret;
++}
++
++static void lirc_gpio_exit(void) {
++ if(gpio_dev->gpio_tx_nr >= 0) {
++ gpio_free(gpio_dev->gpio_tx_nr);
++ }
++ if(gpio_dev->gpio_rx_nr >= 0) {
++ gpio_free(gpio_dev->gpio_rx_nr);
++ }
++
++ lirc_unregister_driver(driver.minor);
++ lirc_buffer_free(&rbuf);
++}
++
++static int lirc_gpio_probe(struct platform_device *pdev) {
++ const struct lirc_gpio_platform_data *pdata =
++ pdev->dev.platform_data;
++ int rc;
++ int result = 0;
++ int match = 0;
++ int i = 0;
++
++ if(pdev->dev.of_node) {
++ struct lirc_gpio_platform_data *dtpdata = devm_kzalloc(&pdev->dev, sizeof(*dtpdata), GFP_KERNEL);
++ if(!dtpdata)
++ return -ENOMEM;
++ rc = lirc_gpio_get_devtree_pdata(&pdev->dev, dtpdata);
++ if(rc)
++ return rc;
++ pdata = dtpdata;
++ }
++
++ if(!pdata)
++ return -EINVAL;
++
++ gpio_dev = kzalloc(sizeof(struct lirc_gpio_dev), GFP_KERNEL);
++ if(!gpio_dev)
++ return -ENOMEM;
++
++ gpio_dev->gpio_rx_nr = pdata->gpio_rx_nr;
++ gpio_dev->gpio_tx_nr = pdata->gpio_tx_nr;
++ gpio_dev->sense = pdata->sense;
++ gpio_dev->softcarrier = pdata->softcarrier;
++ memcpy(gpio_dev->validgpios, pdata->validgpios, 255);
++
++ if(gpio_in_pin != gpio_out_pin) {
++ match = 0;
++ for(i = 0; (i < ARRAY_SIZE(gpio_dev->validgpios)) && (!match) && (gpio_dev->validgpios[i] != -1); i++) {
++ if(gpio_in_pin == gpio_dev->validgpios[i]) {
++ match = 1;
++ break;
++ }
++ }
++ if(gpio_in_pin > -1) {
++ if(!match) {
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": invalid RX GPIO pin specified!\n");
++ return -EINVAL;
++ } else {
++ gpio_dev->gpio_rx_nr = gpio_in_pin;
++ }
++ }
++ match = 0;
++ for(i = 0; (i < ARRAY_SIZE(gpio_dev->validgpios)) && (!match) && (gpio_dev->validgpios[i] != -1); i++) {
++ if(gpio_out_pin == gpio_dev->validgpios[i]) {
++ match = 1;
++ break;
++ }
++ }
++ if(gpio_out_pin > -1) {
++ if(!match) {
++ printk(KERN_ERR LIRC_DRIVER_NAME
++ ": invalid TX GPIO pin specified!\n");
++ return -EINVAL;
++ } else {
++ gpio_dev->gpio_tx_nr = gpio_out_pin;
++ }
++ }
++ }
++ if(sense > -2) {
++ gpio_dev->sense = sense;
++ }
++ if(softcarrier >= 0) {
++ gpio_dev->softcarrier = softcarrier;
++ }
++
++ printk(KERN_DEBUG LIRC_DRIVER_NAME ": rx %d, tx %d, sense %d, softcarrier %d\n",
++ gpio_dev->gpio_rx_nr, gpio_dev->gpio_tx_nr, gpio_dev->sense, gpio_dev->softcarrier);
++
++ platform_set_drvdata(pdev, gpio_dev);
++
++ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN);
++ if(result < 0)
++ return -ENOMEM;
++
++ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE |
++ LIRC_CAN_SET_SEND_CARRIER |
++ LIRC_CAN_SEND_PULSE |
++ LIRC_CAN_REC_MODE2;
++
++ driver.dev = &pdev->dev;
++ driver.minor = lirc_register_driver(&driver);
++
++ if(driver.minor < 0) {
++ printk(KERN_ERR LIRC_DRIVER_NAME ": device registration failed with %d\n", result);
++ result = -EIO;
++ goto exit_gpio;
++ }
++
++ result = init_port();
++ if(result < 0)
++ goto exit_gpio;
++
++ return 0;
++
++exit_gpio:
++ lirc_gpio_exit();
++
++ return result;
++}
++
++static int lirc_gpio_remove(struct platform_device *pdev) {
++ struct lirc_gpio_dev *gpio_dev = platform_get_drvdata(pdev);
++
++ lirc_gpio_exit();
++
++ kfree(gpio_dev);
++
++ return 0;
++}
++
++MODULE_DEVICE_TABLE(of, lirc_gpio_of_match);
++module_platform_driver(lirc_gpio_driver);
++
++MODULE_DESCRIPTION("Infra-red GPIO receiver and blaster driver.");
++MODULE_AUTHOR("CurlyMo <development@xbian.org>");
++MODULE_AUTHOR("Aron Robert Szabo <aron@reon.hu>");
++MODULE_AUTHOR("Michael Bishop <cleverca22@gmail.com>");
++MODULE_LICENSE("GPL");
++
++module_param(gpio_out_pin, int, S_IRUGO);
++MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number");
++
++module_param(gpio_in_pin, int, S_IRUGO);
++MODULE_PARM_DESC(gpio_in_pin, "GPIO input/receiver pin number.");
++
++module_param(sense, int, S_IRUGO);
++MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit"
++ " (0 = active high, 1 = active low )");
++
++module_param(softcarrier, int, S_IRUGO);
++MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)");
++
+diff -Nur linux-3.14.72.orig/drivers/staging/media/omap24xx/v4l2-int-device.h linux-3.14.72/drivers/staging/media/omap24xx/v4l2-int-device.h
+--- linux-3.14.72.orig/drivers/staging/media/omap24xx/v4l2-int-device.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/staging/media/omap24xx/v4l2-int-device.h 2016-06-19 22:11:55.321138957 +0200
+@@ -112,6 +112,12 @@
+ * on certain image sensors.
+ */
+ V4L2_IF_TYPE_BT656,
++ V4L2_IF_TYPE_BT1120_PROGRESSIVE_DDR,
++ V4L2_IF_TYPE_BT1120_PROGRESSIVE_SDR,
++ V4L2_IF_TYPE_BT1120_INTERLACED_DDR,
++ V4L2_IF_TYPE_BT1120_INTERLACED_SDR,
++ V4L2_IF_TYPE_BT656_PROGRESSIVE,
++ V4L2_IF_TYPE_BT656_INTERLACED,
+ };
+
+ enum v4l2_if_type_bt656_mode {
+@@ -187,6 +193,7 @@
+ vidioc_int_querystd_num,
+ vidioc_int_s_std_num,
+ vidioc_int_s_video_routing_num,
++ vidioc_int_send_command_num,
+
+ /*
+ *
+@@ -220,6 +227,8 @@
+ vidioc_int_reset_num,
+ /* VIDIOC_INT_INIT */
+ vidioc_int_init_num,
++ /* VIDIOC_DBG_G_CHIP_IDENT */
++ vidioc_int_g_chip_ident_num,
+
+ /*
+ *
+@@ -289,6 +298,7 @@
+ V4L2_INT_WRAPPER_1(querystd, v4l2_std_id, *);
+ V4L2_INT_WRAPPER_1(s_std, v4l2_std_id, *);
+ V4L2_INT_WRAPPER_1(s_video_routing, struct v4l2_routing, *);
++V4L2_INT_WRAPPER_1(send_command, struct v4l2_send_command_control, *);
+
+ V4L2_INT_WRAPPER_0(dev_init);
+ V4L2_INT_WRAPPER_0(dev_exit);
+@@ -301,5 +311,6 @@
+
+ V4L2_INT_WRAPPER_0(reset);
+ V4L2_INT_WRAPPER_0(init);
++V4L2_INT_WRAPPER_1(g_chip_ident, int, *);
+
+ #endif
+diff -Nur linux-3.14.72.orig/drivers/thermal/device_cooling.c linux-3.14.72/drivers/thermal/device_cooling.c
+--- linux-3.14.72.orig/drivers/thermal/device_cooling.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/thermal/device_cooling.c 2016-06-19 22:11:55.321138957 +0200
+@@ -0,0 +1,157 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/thermal.h>
++#include <linux/err.h>
++#include <linux/slab.h>
++
++struct devfreq_cooling_device {
++ int id;
++ struct thermal_cooling_device *cool_dev;
++ unsigned int devfreq_state;
++ unsigned int max_state;
++};
++
++static DEFINE_IDR(devfreq_idr);
++static DEFINE_MUTEX(devfreq_cooling_lock);
++
++static BLOCKING_NOTIFIER_HEAD(devfreq_cooling_chain_head);
++
++int register_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return blocking_notifier_chain_register(
++ &devfreq_cooling_chain_head, nb);
++}
++EXPORT_SYMBOL_GPL(register_devfreq_cooling_notifier);
++
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return blocking_notifier_chain_unregister(
++ &devfreq_cooling_chain_head, nb);
++}
++EXPORT_SYMBOL_GPL(unregister_devfreq_cooling_notifier);
++
++static int devfreq_cooling_notifier_call_chain(unsigned long val)
++{
++ return (blocking_notifier_call_chain(
++ &devfreq_cooling_chain_head, val, NULL)
++ == NOTIFY_BAD) ? -EINVAL : 0;
++}
++
++static int devfreq_set_cur_state(struct thermal_cooling_device *cdev,
++ unsigned long state)
++{
++ struct devfreq_cooling_device *devfreq_device = cdev->devdata;
++ int ret;
++ unsigned long notify_state;
++
++ if (state >= devfreq_device->max_state)
++ notify_state = 5;
++ else
++ notify_state = state;
++ ret = devfreq_cooling_notifier_call_chain(notify_state);
++ if (ret)
++ return -EINVAL;
++ devfreq_device->devfreq_state = state;
++
++ return 0;
++}
++
++static int devfreq_get_max_state(struct thermal_cooling_device *cdev,
++ unsigned long *state)
++{
++ struct devfreq_cooling_device *devfreq_device = cdev->devdata;
++ *state = devfreq_device->max_state;
++
++ return 0;
++}
++
++static int devfreq_get_cur_state(struct thermal_cooling_device *cdev,
++ unsigned long *state)
++{
++ struct devfreq_cooling_device *devfreq_device = cdev->devdata;
++
++ *state = devfreq_device->devfreq_state;
++
++ return 0;
++}
++
++static struct thermal_cooling_device_ops const devfreq_cooling_ops = {
++ .get_max_state = devfreq_get_max_state,
++ .get_cur_state = devfreq_get_cur_state,
++ .set_cur_state = devfreq_set_cur_state,
++};
++
++static int get_idr(struct idr *idr, int *id)
++{
++ int ret;
++
++ mutex_lock(&devfreq_cooling_lock);
++ ret = idr_alloc(idr, NULL, 0, 0, GFP_KERNEL);
++ mutex_unlock(&devfreq_cooling_lock);
++ if (unlikely(ret < 0))
++ return ret;
++ *id = ret;
++
++ return 0;
++}
++
++static void release_idr(struct idr *idr, int id)
++{
++ mutex_lock(&devfreq_cooling_lock);
++ idr_remove(idr, id);
++ mutex_unlock(&devfreq_cooling_lock);
++}
++
++struct thermal_cooling_device *devfreq_cooling_register(unsigned long max_state)
++{
++ struct thermal_cooling_device *cool_dev;
++ struct devfreq_cooling_device *devfreq_dev = NULL;
++ char dev_name[THERMAL_NAME_LENGTH];
++ int ret = 0;
++
++ devfreq_dev = kzalloc(sizeof(struct devfreq_cooling_device),
++ GFP_KERNEL);
++ if (!devfreq_dev)
++ return ERR_PTR(-ENOMEM);
++
++ ret = get_idr(&devfreq_idr, &devfreq_dev->id);
++ if (ret) {
++ kfree(devfreq_dev);
++ return ERR_PTR(-EINVAL);
++ }
++
++ snprintf(dev_name, sizeof(dev_name), "thermal-devfreq-%d",
++ devfreq_dev->id);
++
++ cool_dev = thermal_cooling_device_register(dev_name, devfreq_dev,
++ &devfreq_cooling_ops);
++ if (!cool_dev) {
++ release_idr(&devfreq_idr, devfreq_dev->id);
++ kfree(devfreq_dev);
++ return ERR_PTR(-EINVAL);
++ }
++ devfreq_dev->cool_dev = cool_dev;
++ devfreq_dev->devfreq_state = 0;
++ devfreq_dev->max_state = max_state;
++
++ return cool_dev;
++}
++EXPORT_SYMBOL_GPL(devfreq_cooling_register);
++
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev)
++{
++ struct devfreq_cooling_device *devfreq_dev = cdev->devdata;
++
++ thermal_cooling_device_unregister(devfreq_dev->cool_dev);
++ release_idr(&devfreq_idr, devfreq_dev->id);
++ kfree(devfreq_dev);
++}
++EXPORT_SYMBOL_GPL(devfreq_cooling_unregister);
+diff -Nur linux-3.14.72.orig/drivers/thermal/imx_thermal.c linux-3.14.72/drivers/thermal/imx_thermal.c
+--- linux-3.14.72.orig/drivers/thermal/imx_thermal.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/thermal/imx_thermal.c 2016-06-19 22:11:55.321138957 +0200
+@@ -1,17 +1,19 @@
+ /*
+- * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+-
++#include <linux/busfreq-imx6.h>
+ #include <linux/clk.h>
+ #include <linux/cpu_cooling.h>
+ #include <linux/cpufreq.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
++#include <linux/device_cooling.h>
++#include <linux/fsl_otp.h>
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+@@ -19,6 +21,7 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/slab.h>
+@@ -31,6 +34,10 @@
+
+ #define MISC0 0x0150
+ #define MISC0_REFTOP_SELBIASOFF (1 << 3)
++#define MISC1 0x0160
++#define MISC1_IRQ_TEMPHIGH (1 << 29)
++#define MISC1_IRQ_TEMPLOW (1 << 28)
++#define MISC1_IRQ_TEMPPANIC (1 << 27)
+
+ #define TEMPSENSE0 0x0180
+ #define TEMPSENSE0_ALARM_VALUE_SHIFT 20
+@@ -43,40 +50,86 @@
+
+ #define TEMPSENSE1 0x0190
+ #define TEMPSENSE1_MEASURE_FREQ 0xffff
++#define TEMPSENSE2 0x0290
++#define TEMPSENSE2_LOW_VALUE_SHIFT 0
++#define TEMPSENSE2_LOW_VALUE_MASK 0xfff
++#define TEMPSENSE2_PANIC_VALUE_SHIFT 16
++#define TEMPSENSE2_PANIC_VALUE_MASK 0xfff0000
+
+ #define OCOTP_ANA1 0x04e0
+
+-/* The driver supports 1 passive trip point and 1 critical trip point */
+-enum imx_thermal_trip {
+- IMX_TRIP_PASSIVE,
+- IMX_TRIP_CRITICAL,
+- IMX_TRIP_NUM,
+-};
++#define OCOTP_TEMP_GRADE 0x480
++#define OCOTP_TEMP_GRADE_SHIFT 5
++#define OCOTP_TEMP_GRADE_AUT 0x3
++#define OCOTP_TEMP_GRADE_IND 0x2
++#define OCOTP_TEMP_GRADE_EXT 0x1
++#define OCOTP_TEMP_GRADE_COM 0x0
+
+ /*
+ * It defines the temperature in millicelsius for passive trip point
+ * that will trigger cooling action when crossed.
+ */
+-#define IMX_TEMP_PASSIVE 85000
++#define IMX_TRIP_PASSIVE 0
++
++#define IMX_TEMP_MAX_PASSIVE 85000
++#define IMX_TEMP_MIN_TRIP_DELTA 6000
++
++#define IMX_POLLING_DELAY 3000 /* millisecond */
++#define IMX_PASSIVE_DELAY 2000
++
++#define FACTOR0 10000000
++#define FACTOR1 15976
++#define FACTOR2 4297157
++
++#define TEMPMON_V1 1
++#define TEMPMON_V2 2
++
++struct thermal_soc_data {
++ u32 version;
++};
++
++static struct thermal_soc_data thermal_imx6q_data = {
++ .version = TEMPMON_V1,
++};
+
+-#define IMX_POLLING_DELAY 2000 /* millisecond */
+-#define IMX_PASSIVE_DELAY 1000
++static struct thermal_soc_data thermal_imx6sx_data = {
++ .version = TEMPMON_V2,
++};
++
++#define IMX_TRIP_PASSIVE 0
+
+ struct imx_thermal_data {
+ struct thermal_zone_device *tz;
+- struct thermal_cooling_device *cdev;
++ struct thermal_cooling_device *cdev[2];
+ enum thermal_device_mode mode;
+ struct regmap *tempmon;
+- int c1, c2; /* See formula in imx_get_sensor_data() */
++ u32 c1, c2; /* See formula in imx_get_sensor_data() */
+ unsigned long temp_passive;
+ unsigned long temp_critical;
++ unsigned long num_passive_trips;
++ unsigned long temp_zone_delta;
+ unsigned long alarm_temp;
+ unsigned long last_temp;
+ bool irq_enabled;
+ int irq;
+ struct clk *thermal_clk;
++ const struct thermal_soc_data *socdata;
+ };
+
++static struct imx_thermal_data *imx_thermal_data;
++
++static void imx_set_panic_temp(struct imx_thermal_data *data,
++ signed long panic_temp)
++{
++ struct regmap *map = data->tempmon;
++ int critical_value;
++
++ critical_value = (data->c2 - panic_temp) / data->c1;
++ regmap_write(map, TEMPSENSE2 + REG_CLR, TEMPSENSE2_PANIC_VALUE_MASK);
++ regmap_write(map, TEMPSENSE2 + REG_SET, critical_value <<
++ TEMPSENSE2_PANIC_VALUE_SHIFT);
++}
++
+ static void imx_set_alarm_temp(struct imx_thermal_data *data,
+ signed long alarm_temp)
+ {
+@@ -84,7 +137,7 @@
+ int alarm_value;
+
+ data->alarm_temp = alarm_temp;
+- alarm_value = (alarm_temp - data->c2) / data->c1;
++ alarm_value = (data->c2 - alarm_temp) / data->c1;
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_ALARM_VALUE_MASK);
+ regmap_write(map, TEMPSENSE0 + REG_SET, alarm_value <<
+ TEMPSENSE0_ALARM_VALUE_SHIFT);
+@@ -95,6 +148,7 @@
+ struct imx_thermal_data *data = tz->devdata;
+ struct regmap *map = data->tempmon;
+ unsigned int n_meas;
++ unsigned long cur_state;
+ bool wait;
+ u32 val;
+
+@@ -108,6 +162,7 @@
+ * temperature sensor, enable measurements, take a reading,
+ * disable measurements, power off the temperature sensor.
+ */
++ clk_prepare_enable(data->thermal_clk);
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+
+@@ -118,14 +173,15 @@
+ * According to the temp sensor designers, it may require up to ~17us
+ * to complete a measurement.
+ */
+- if (wait)
++ if (wait) {
+ usleep_range(20, 50);
+-
+- regmap_read(map, TEMPSENSE0, &val);
++ regmap_read(map, TEMPSENSE0, &val);
++ }
+
+ if (data->mode != THERMAL_DEVICE_ENABLED) {
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
++ clk_disable_unprepare(data->thermal_clk);
+ }
+
+ if ((val & TEMPSENSE0_FINISHED) == 0) {
+@@ -136,12 +192,23 @@
+ n_meas = (val & TEMPSENSE0_TEMP_CNT_MASK) >> TEMPSENSE0_TEMP_CNT_SHIFT;
+
+ /* See imx_get_sensor_data() for formula derivation */
+- *temp = data->c2 + data->c1 * n_meas;
++ *temp = data->c2 - n_meas * data->c1;
++
++ data->cdev[0]->ops->get_cur_state(data->cdev[0], &cur_state);
+
+ /* Update alarm value to next higher trip point */
+- if (data->alarm_temp == data->temp_passive && *temp >= data->temp_passive)
++ if ((data->temp_passive < data->alarm_temp) &&
++ (data->alarm_temp < data->temp_critical) &&
++ (cur_state < data->num_passive_trips)) {
++ imx_set_alarm_temp(data, data->temp_passive + ((cur_state + 1) * data->temp_zone_delta));
++ dev_dbg(&tz->device, "thermal alarm on: T < %lu\n",
++ data->alarm_temp / 1000);
++ }
++
++ if (data->alarm_temp < data->temp_critical && *temp >= data->temp_passive + (data->num_passive_trips * data->temp_zone_delta))
+ imx_set_alarm_temp(data, data->temp_critical);
+- if (data->alarm_temp == data->temp_critical && *temp < data->temp_passive) {
++
++ if (data->alarm_temp > data->temp_passive && *temp < data->temp_passive) {
+ imx_set_alarm_temp(data, data->temp_passive);
+ dev_dbg(&tz->device, "thermal alarm off: T < %lu\n",
+ data->alarm_temp / 1000);
+@@ -210,7 +277,8 @@
+ static int imx_get_trip_type(struct thermal_zone_device *tz, int trip,
+ enum thermal_trip_type *type)
+ {
+- *type = (trip == IMX_TRIP_PASSIVE) ? THERMAL_TRIP_PASSIVE :
++ struct imx_thermal_data *data = tz->devdata;
++ *type = (trip < data->num_passive_trips) ? THERMAL_TRIP_PASSIVE :
+ THERMAL_TRIP_CRITICAL;
+ return 0;
+ }
+@@ -229,8 +297,9 @@
+ {
+ struct imx_thermal_data *data = tz->devdata;
+
+- *temp = (trip == IMX_TRIP_PASSIVE) ? data->temp_passive :
+- data->temp_critical;
++ *temp = (trip < data->num_passive_trips) ?
++ data->temp_passive + (trip * data->temp_zone_delta) :
++ data->temp_critical;
+ return 0;
+ }
+
+@@ -239,15 +308,52 @@
+ {
+ struct imx_thermal_data *data = tz->devdata;
+
+- if (trip == IMX_TRIP_CRITICAL)
+- return -EPERM;
++ if (trip > IMX_TRIP_PASSIVE) {
++ if (data->socdata->version == TEMPMON_V2) {
++ data->temp_critical = temp;
++ imx_set_panic_temp(data, temp);
++ } else
++ return -EPERM;
++ }
+
+- if (temp > IMX_TEMP_PASSIVE)
+- return -EINVAL;
++ if (trip == IMX_TRIP_PASSIVE) {
++ if (temp > IMX_TEMP_MAX_PASSIVE)
++ return -EINVAL;
++ data->temp_passive = temp;
++ imx_set_alarm_temp(data, temp);
++ data->temp_zone_delta = (data->temp_critical - data->temp_passive) / data->num_passive_trips;
++ }
+
+- data->temp_passive = temp;
++ return 0;
++}
++
++static int imx_get_trend(struct thermal_zone_device *tz,
++ int trip, enum thermal_trend *trend)
++{
++ struct imx_thermal_data *data = tz->devdata;
++ int ret;
++ unsigned long trip_temp, cur_state;
++
++ ret = imx_get_trip_temp(tz, trip, &trip_temp);
++ if (ret < 0)
++ return ret;
+
+- imx_set_alarm_temp(data, temp);
++ data->cdev[0]->ops->get_cur_state(data->cdev[0], &cur_state);
++
++ if (tz->temperature > tz->last_temperature &&
++ tz->temperature > (data->temp_passive + (cur_state * data->temp_zone_delta))) {
++ *trend = THERMAL_TREND_RAISING;
++ } else if (tz->temperature < tz->last_temperature && cur_state) {
++ if (tz->temperature <= (data->temp_passive - data->temp_zone_delta))
++ *trend = THERMAL_TREND_DROP_FULL;
++ else if (tz->temperature <= (data->temp_passive +
++ ((cur_state - 1) * data->temp_zone_delta)))
++ *trend = THERMAL_TREND_DROPPING;
++ else
++ *trend = THERMAL_TREND_STABLE;
++ } else {
++ *trend = THERMAL_TREND_STABLE;
++ }
+
+ return 0;
+ }
+@@ -296,6 +402,7 @@
+ .get_trip_temp = imx_get_trip_temp,
+ .get_crit_temp = imx_get_crit_temp,
+ .set_trip_temp = imx_set_trip_temp,
++ .get_trend = imx_get_trend,
+ };
+
+ static int imx_get_sensor_data(struct platform_device *pdev)
+@@ -305,6 +412,7 @@
+ int t1, t2, n1, n2;
+ int ret;
+ u32 val;
++ u64 temp64;
+
+ map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "fsl,tempmon-data");
+@@ -330,6 +438,8 @@
+ * [31:20] - sensor value @ 25C
+ * [19:8] - sensor value of hot
+ * [7:0] - hot temperature value
++ * Use universal formula now and only need sensor value @ 25C
++ * slope = 0.4297157 - (0.0015976 * 25C fuse)
+ */
+ n1 = val >> 20;
+ n2 = (val & 0xfff00) >> 8;
+@@ -337,36 +447,79 @@
+ t1 = 25; /* t1 always 25C */
+
+ /*
+- * Derived from linear interpolation,
+- * Tmeas = T2 + (Nmeas - N2) * (T1 - T2) / (N1 - N2)
++ * Derived from linear interpolation:
++ * slope = 0.4297157 - (0.0015976 * 25C fuse)
++ * slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
++ * (Nmeas - n1) / (Tmeas - t1) = slope
+ * We want to reduce this down to the minimum computation necessary
+ * for each temperature read. Also, we want Tmeas in millicelsius
+ * and we don't want to lose precision from integer division. So...
+- * milli_Tmeas = 1000 * T2 + 1000 * (Nmeas - N2) * (T1 - T2) / (N1 - N2)
+- * Let constant c1 = 1000 * (T1 - T2) / (N1 - N2)
+- * milli_Tmeas = (1000 * T2) + c1 * (Nmeas - N2)
+- * milli_Tmeas = (1000 * T2) + (c1 * Nmeas) - (c1 * N2)
+- * Let constant c2 = (1000 * T2) - (c1 * N2)
+- * milli_Tmeas = c2 + (c1 * Nmeas)
++ * Tmeas = (Nmeas - n1) / slope + t1
++ * milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
++ * milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
++ * Let constant c1 = (-1000 / slope)
++ * milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
++ * Let constant c2 = n1 *c1 + 1000 * t1
++ * milli_Tmeas = c2 - Nmeas * c1
+ */
+- data->c1 = 1000 * (t1 - t2) / (n1 - n2);
+- data->c2 = 1000 * t2 - data->c1 * n2;
++ temp64 = FACTOR0;
++ temp64 *= 1000;
++ do_div(temp64, FACTOR1 * n1 - FACTOR2);
++ data->c1 = temp64;
++ data->c2 = n1 * data->c1 + 1000 * t1;
+
+- /*
+- * Set the default passive cooling trip point to 20 °C below the
+- * maximum die temperature. Can be changed from userspace.
+- */
+- data->temp_passive = 1000 * (t2 - 20);
++ return 0;
++}
+
+- /*
+- * The maximum die temperature is t2, let's give 5 °C cushion
+- * for noise and possible temperature rise between measurements.
+- */
+- data->temp_critical = 1000 * (t2 - 5);
++static void imx_set_thermal_defaults(struct imx_thermal_data *data)
++{
++ int ret;
++ u32 val;
+
+- return 0;
++ ret = fsl_otp_readl(OCOTP_TEMP_GRADE, &val);
++
++ if (ret) {
++ /*
++ * Set the default passive cooling trip point,
++ * can be changed from userspace.
++ */
++ data->temp_passive = IMX_TEMP_MAX_PASSIVE;
++
++ /*
++ * The maximum die temperature set to 20 C higher than
++ * IMX_TEMP_MAX_PASSIVE.
++ */
++ data->temp_critical = 1000 * 20 + data->temp_passive;
++ data->temp_zone_delta = (data->temp_critical - data->temp_passive) / data->num_passive_trips;
++ } else {
++ val >>= OCOTP_TEMP_GRADE_SHIFT;
++ val &= 0x3;
++
++ switch (val) {
++ case OCOTP_TEMP_GRADE_AUT:
++ data->temp_critical = 125000;
++ break;
++ case OCOTP_TEMP_GRADE_IND:
++ case OCOTP_TEMP_GRADE_EXT:
++ data->temp_critical = 105000;
++ break;
++ case OCOTP_TEMP_GRADE_COM:
++ default:
++ data->temp_critical = 95000;
++ break;
++ }
++ data->temp_passive = data->temp_critical - (IMX_TEMP_MIN_TRIP_DELTA * data->num_passive_trips);
++ data->temp_zone_delta = IMX_TEMP_MIN_TRIP_DELTA;
++ }
++
++ pr_debug("THERMAL DEFAULTS: passive: %lu \
++ critical %lu trip_points: %lu \
++ zone_delta: %lu\n",
++ data->temp_passive, data->temp_critical,
++ data->num_passive_trips, data->temp_zone_delta);
+ }
+
++
+ static irqreturn_t imx_thermal_alarm_irq(int irq, void *dev)
+ {
+ struct imx_thermal_data *data = dev;
+@@ -389,8 +542,54 @@
+ return IRQ_HANDLED;
+ }
+
++static const struct of_device_id of_imx_thermal_match[] = {
++ { .compatible = "fsl,imx6q-tempmon", .data = &thermal_imx6q_data, },
++ { .compatible = "fsl,imx6sx-tempmon", .data = &thermal_imx6sx_data, },
++ { /* end */ }
++};
++MODULE_DEVICE_TABLE(of, of_imx_thermal_match);
++
++static int thermal_notifier_event(struct notifier_block *this,
++ unsigned long event, void *ptr)
++{
++ struct regmap *map = imx_thermal_data->tempmon;
++
++ switch (event) {
++ /*
++ * In low_bus_freq_mode, the thermal sensor auto measurement
++ * can be disabled to low the power consumption.
++ */
++ case LOW_BUSFREQ_ENTER:
++ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
++ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
++ imx_thermal_data->mode = THERMAL_DEVICE_DISABLED;
++ disable_irq(imx_thermal_data->irq);
++ clk_disable_unprepare(imx_thermal_data->thermal_clk);
++ break;
++
++ /* Enabled thermal auto measurement when exiting low_bus_freq_mode */
++ case LOW_BUSFREQ_EXIT:
++ clk_prepare_enable(imx_thermal_data->thermal_clk);
++ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
++ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
++ imx_thermal_data->mode = THERMAL_DEVICE_ENABLED;
++ enable_irq(imx_thermal_data->irq);
++ break;
++
++ default:
++ break;
++ }
++ return NOTIFY_OK;
++}
++
++static struct notifier_block thermal_notifier = {
++ .notifier_call = thermal_notifier_event,
++};
++
+ static int imx_thermal_probe(struct platform_device *pdev)
+ {
++ const struct of_device_id *of_id =
++ of_match_device(of_imx_thermal_match, &pdev->dev);
+ struct imx_thermal_data *data;
+ struct cpumask clip_cpus;
+ struct regmap *map;
+@@ -400,6 +599,7 @@
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
++ imx_thermal_data = data;
+
+ map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "fsl,tempmon");
+ if (IS_ERR(map)) {
+@@ -409,18 +609,41 @@
+ }
+ data->tempmon = map;
+
++ data->socdata = of_id->data;
++
++ data->thermal_clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(data->thermal_clk)) {
++ dev_warn(&pdev->dev, "failed to get thermal clk!\n");
++ } else {
++ /*
++ * Thermal sensor needs clk on to get correct value, normally
++ * we should enable its clk before taking measurement and disable
++ * clk after measurement is done, but if alarm function is enabled,
++ * hardware will auto measure the temperature periodically, so we
++ * need to keep the clk always on for alarm function.
++ */
++ ret = clk_prepare_enable(data->thermal_clk);
++ if (ret)
++ dev_warn(&pdev->dev, "failed to enable thermal clk: %d\n", ret);
++ }
++
++ /* make sure the IRQ flag is clear before enable irq */
++ regmap_write(map, MISC1 + REG_CLR, MISC1_IRQ_TEMPHIGH);
++ if (data->socdata->version == TEMPMON_V2) {
++ /*
++ * reset value of LOW ALARM is incorrect, set it to lowest
++ * value to avoid false trigger of low alarm.
++ */
++ regmap_write(map, TEMPSENSE2 + REG_SET,
++ TEMPSENSE2_LOW_VALUE_MASK);
++ regmap_write(map, MISC1 + REG_CLR, MISC1_IRQ_TEMPLOW |
++ MISC1_IRQ_TEMPPANIC);
++ }
++
+ data->irq = platform_get_irq(pdev, 0);
+ if (data->irq < 0)
+ return data->irq;
+
+- ret = devm_request_threaded_irq(&pdev->dev, data->irq,
+- imx_thermal_alarm_irq, imx_thermal_alarm_irq_thread,
+- 0, "imx_thermal", data);
+- if (ret < 0) {
+- dev_err(&pdev->dev, "failed to request alarm irq: %d\n", ret);
+- return ret;
+- }
+-
+ platform_set_drvdata(pdev, data);
+
+ ret = imx_get_sensor_data(pdev);
+@@ -437,16 +660,28 @@
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
+
+ cpumask_set_cpu(0, &clip_cpus);
+- data->cdev = cpufreq_cooling_register(&clip_cpus);
+- if (IS_ERR(data->cdev)) {
+- ret = PTR_ERR(data->cdev);
++ data->cdev[0] = cpufreq_cooling_register(&clip_cpus);
++ if (IS_ERR(data->cdev[0])) {
++ ret = PTR_ERR(data->cdev[0]);
+ dev_err(&pdev->dev,
+ "failed to register cpufreq cooling device: %d\n", ret);
+ return ret;
+ }
+
++ data->cdev[0]->ops->get_max_state(data->cdev[0], &data->num_passive_trips);
++
++ data->cdev[1] = devfreq_cooling_register(data->num_passive_trips + 1);
++ if (IS_ERR(data->cdev[1])) {
++ ret = PTR_ERR(data->cdev[1]);
++ dev_err(&pdev->dev,
++ "failed to register devfreq cooling device: %d\n", ret);
++ return ret;
++ }
++
++ imx_set_thermal_defaults(data);
++
+ data->tz = thermal_zone_device_register("imx_thermal_zone",
+- IMX_TRIP_NUM,
++ data->num_passive_trips + 1,
+ BIT(IMX_TRIP_PASSIVE), data,
+ &imx_tz_ops, NULL,
+ IMX_PASSIVE_DELAY,
+@@ -455,36 +690,34 @@
+ ret = PTR_ERR(data->tz);
+ dev_err(&pdev->dev,
+ "failed to register thermal zone device %d\n", ret);
+- cpufreq_cooling_unregister(data->cdev);
++ cpufreq_cooling_unregister(data->cdev[0]);
++ devfreq_cooling_unregister(data->cdev[1]);
+ return ret;
+ }
+
+- data->thermal_clk = devm_clk_get(&pdev->dev, NULL);
+- if (IS_ERR(data->thermal_clk)) {
+- dev_warn(&pdev->dev, "failed to get thermal clk!\n");
+- } else {
+- /*
+- * Thermal sensor needs clk on to get correct value, normally
+- * we should enable its clk before taking measurement and disable
+- * clk after measurement is done, but if alarm function is enabled,
+- * hardware will auto measure the temperature periodically, so we
+- * need to keep the clk always on for alarm function.
+- */
+- ret = clk_prepare_enable(data->thermal_clk);
+- if (ret)
+- dev_warn(&pdev->dev, "failed to enable thermal clk: %d\n", ret);
+- }
+-
+ /* Enable measurements at ~ 10 Hz */
+ regmap_write(map, TEMPSENSE1 + REG_CLR, TEMPSENSE1_MEASURE_FREQ);
+ measure_freq = DIV_ROUND_UP(32768, 10); /* 10 Hz */
+ regmap_write(map, TEMPSENSE1 + REG_SET, measure_freq);
+ imx_set_alarm_temp(data, data->temp_passive);
++
++ if (data->socdata->version == TEMPMON_V2)
++ imx_set_panic_temp(data, data->temp_critical);
++
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+
++ ret = devm_request_threaded_irq(&pdev->dev, data->irq,
++ imx_thermal_alarm_irq, imx_thermal_alarm_irq_thread,
++ 0, "imx_thermal", data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to request alarm irq: %d\n", ret);
++ return ret;
++ }
+ data->irq_enabled = true;
+ data->mode = THERMAL_DEVICE_ENABLED;
++ /* register the busfreq notifier called in low bus freq */
++ register_busfreq_notifier(&thermal_notifier);
+
+ return 0;
+ }
+@@ -494,13 +727,15 @@
+ struct imx_thermal_data *data = platform_get_drvdata(pdev);
+ struct regmap *map = data->tempmon;
+
++ unregister_busfreq_notifier(&thermal_notifier);
+ /* Disable measurements */
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
+ if (!IS_ERR(data->thermal_clk))
+ clk_disable_unprepare(data->thermal_clk);
+
+ thermal_zone_device_unregister(data->tz);
+- cpufreq_cooling_unregister(data->cdev);
++ cpufreq_cooling_unregister(data->cdev[0]);
++ devfreq_cooling_unregister(data->cdev[1]);
+
+ return 0;
+ }
+@@ -520,6 +755,8 @@
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
+ data->mode = THERMAL_DEVICE_DISABLED;
++ disable_irq(data->irq);
++ clk_disable_unprepare(data->thermal_clk);
+
+ return 0;
+ }
+@@ -530,9 +767,11 @@
+ struct regmap *map = data->tempmon;
+
+ /* Enabled thermal sensor after resume */
++ clk_prepare_enable(data->thermal_clk);
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+ data->mode = THERMAL_DEVICE_ENABLED;
++ enable_irq(data->irq);
+
+ return 0;
+ }
+@@ -541,12 +780,6 @@
+ static SIMPLE_DEV_PM_OPS(imx_thermal_pm_ops,
+ imx_thermal_suspend, imx_thermal_resume);
+
+-static const struct of_device_id of_imx_thermal_match[] = {
+- { .compatible = "fsl,imx6q-tempmon", },
+- { /* end */ }
+-};
+-MODULE_DEVICE_TABLE(of, of_imx_thermal_match);
+-
+ static struct platform_driver imx_thermal = {
+ .driver = {
+ .name = "imx_thermal",
+@@ -557,7 +790,13 @@
+ .probe = imx_thermal_probe,
+ .remove = imx_thermal_remove,
+ };
+-module_platform_driver(imx_thermal);
++
++static int __init imx_thermal_init(void)
++{
++ return platform_driver_register(&imx_thermal);
++}
++
++late_initcall(imx_thermal_init);
+
+ MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+ MODULE_DESCRIPTION("Thermal driver for Freescale i.MX SoCs");
+diff -Nur linux-3.14.72.orig/drivers/thermal/Kconfig linux-3.14.72/drivers/thermal/Kconfig
+--- linux-3.14.72.orig/drivers/thermal/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/thermal/Kconfig 2016-06-19 22:11:55.321138957 +0200
+@@ -119,12 +119,20 @@
+ depends on CPU_THERMAL
+ depends on MFD_SYSCON
+ depends on OF
++ select FSL_OTP
+ help
+ Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs.
+ It supports one critical trip point and one passive trip point. The
+ cpufreq is used as the cooling device to throttle CPUs when the
+ passive trip is crossed.
+
++config DEVICE_THERMAL
++ tristate "generic device cooling support"
++ help
++ Support for device cooling.
++ It supports notification of crossing passive trip for devices,
++ devices need to do their own actions to cool down the SOC.
++
+ config SPEAR_THERMAL
+ bool "SPEAr thermal sensor driver"
+ depends on PLAT_SPEAR
+diff -Nur linux-3.14.72.orig/drivers/thermal/Makefile linux-3.14.72/drivers/thermal/Makefile
+--- linux-3.14.72.orig/drivers/thermal/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/thermal/Makefile 2016-06-19 22:11:55.321138957 +0200
+@@ -26,6 +26,7 @@
+ obj-$(CONFIG_DB8500_THERMAL) += db8500_thermal.o
+ obj-$(CONFIG_ARMADA_THERMAL) += armada_thermal.o
+ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
++obj-$(CONFIG_DEVICE_THERMAL) += device_cooling.o
+ obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
+ obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
+ obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
+diff -Nur linux-3.14.72.orig/drivers/thermal/step_wise.c linux-3.14.72/drivers/thermal/step_wise.c
+--- linux-3.14.72.orig/drivers/thermal/step_wise.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/thermal/step_wise.c 2016-06-19 22:11:55.321138957 +0200
+@@ -70,10 +70,12 @@
+ if (next_target < instance->lower)
+ next_target = instance->lower;
+ }
++ dev_dbg(&cdev->device, "THERMAL_TREND_RAISING: next_target=%ld\n", next_target);
+ break;
+ case THERMAL_TREND_RAISE_FULL:
+ if (throttle)
+ next_target = instance->upper;
++ dev_dbg(&cdev->device, "THERMAL_TREND_RAISE_FULL: next_target=%ld\n", next_target);
+ break;
+ case THERMAL_TREND_DROPPING:
+ if (cur_state <= instance->lower) {
+@@ -84,6 +86,7 @@
+ if (next_target > instance->upper)
+ next_target = instance->upper;
+ }
++ dev_dbg(&cdev->device, "THERMAL_TREND_DROPPING: next_target=%ld\n", next_target);
+ break;
+ case THERMAL_TREND_DROP_FULL:
+ if (cur_state == instance->lower) {
+@@ -91,6 +94,7 @@
+ next_target = THERMAL_NO_TARGET;
+ } else
+ next_target = instance->lower;
++ dev_dbg(&cdev->device, "THERMAL_TREND_DROP_FULL: next_target=%ld\n", next_target);
+ break;
+ default:
+ break;
+@@ -117,7 +121,7 @@
+ enum thermal_trend trend;
+ struct thermal_instance *instance;
+ bool throttle = false;
+- int old_target;
++ unsigned long old_target;
+
+ if (trip == THERMAL_TRIPS_NONE) {
+ trip_temp = tz->forced_passive;
+@@ -143,8 +147,8 @@
+
+ old_target = instance->target;
+ instance->target = get_target_state(instance, trend, throttle);
+- dev_dbg(&instance->cdev->device, "old_target=%d, target=%d\n",
+- old_target, (int)instance->target);
++ dev_dbg(&instance->cdev->device, "old_target=%ld, target=%ld\n",
++ old_target, instance->target);
+
+ /* Activate a passive thermal instance */
+ if (old_target == THERMAL_NO_TARGET &&
+diff -Nur linux-3.14.72.orig/drivers/tty/serial/imx.c linux-3.14.72/drivers/tty/serial/imx.c
+--- linux-3.14.72.orig/drivers/tty/serial/imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/tty/serial/imx.c 2016-06-19 22:11:55.321138957 +0200
+@@ -116,7 +116,7 @@
+ #define UCR3_DSR (1<<10) /* Data set ready */
+ #define UCR3_DCD (1<<9) /* Data carrier detect */
+ #define UCR3_RI (1<<8) /* Ring indicator */
+-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
++#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
+ #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+ #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+ #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+@@ -147,6 +147,7 @@
+ #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+ #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+ #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
++#define USR1_AGTIM (1<<8) /* Ageing timer interrfupt flag */
+ #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+ #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+ #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+@@ -186,6 +187,7 @@
+ #define DRIVER_NAME "IMX-uart"
+
+ #define UART_NR 8
++#define IMX_RXBD_NUM 20
+
+ /* i.mx21 type uart runs on all i.mx except i.mx1 */
+ enum imx_uart_type {
+@@ -200,6 +202,23 @@
+ enum imx_uart_type devtype;
+ };
+
++struct imx_dma_bufinfo {
++ bool filled;
++ unsigned int rx_bytes;
++};
++
++struct imx_dma_rxbuf {
++ unsigned int periods;
++ unsigned int period_len;
++ unsigned int buf_len;
++
++ void *buf;
++ dma_addr_t dmaaddr;
++ unsigned int cur_idx;
++ unsigned int last_completed_idx;
++ struct imx_dma_bufinfo buf_info[IMX_RXBD_NUM];
++};
++
+ struct imx_port {
+ struct uart_port port;
+ struct timer_list timer;
+@@ -221,11 +240,16 @@
+ unsigned int dma_is_rxing:1;
+ unsigned int dma_is_txing:1;
+ struct dma_chan *dma_chan_rx, *dma_chan_tx;
+- struct scatterlist rx_sgl, tx_sgl[2];
+- void *rx_buf;
++ struct scatterlist tx_sgl[2];
++ struct imx_dma_rxbuf rx_buf;
+ unsigned int tx_bytes;
+ unsigned int dma_tx_nents;
++ struct delayed_work tsk_dma_tx;
++ struct work_struct tsk_dma_rx;
+ wait_queue_head_t dma_wait;
++ unsigned int saved_reg[11];
++#define DMA_TX_IS_WORKING 1
++ unsigned long flags;
+ };
+
+ struct imx_port_ucrs {
+@@ -435,15 +459,21 @@
+ struct imx_port *sport = (struct imx_port *)port;
+ unsigned long temp;
+
+- /*
+- * We are maybe in the SMP context, so if the DMA TX thread is running
+- * on other cpu, we have to wait for it to finish.
+- */
+- if (sport->dma_is_enabled && sport->dma_is_rxing)
+- return;
++ if (sport->dma_is_enabled && sport->dma_is_rxing) {
++ if (sport->port.suspended) {
++ dmaengine_terminate_all(sport->dma_chan_rx);
++ sport->dma_is_rxing = 0;
++ } else {
++ return;
++ }
++ }
+
+ temp = readl(sport->port.membase + UCR2);
+ writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
++
++ /* disable the `Receiver Ready Interrrupt` */
++ temp = readl(sport->port.membase + UCR1);
++ writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
+ }
+
+ /*
+@@ -496,8 +526,11 @@
+
+ dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
+
+- if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+- uart_write_wakeup(&sport->port);
++ clear_bit(DMA_TX_IS_WORKING, &sport->flags);
++ smp_mb__after_clear_bit();
++ uart_write_wakeup(&sport->port);
++
++ schedule_delayed_work(&sport->tsk_dma_tx, msecs_to_jiffies(1));
+
+ if (waitqueue_active(&sport->dma_wait)) {
+ wake_up(&sport->dma_wait);
+@@ -506,54 +539,63 @@
+ }
+ }
+
+-static void imx_dma_tx(struct imx_port *sport)
++static void dma_tx_work(struct work_struct *w)
+ {
++ struct delayed_work *delay_work = to_delayed_work(w);
++ struct imx_port *sport = container_of(delay_work, struct imx_port, tsk_dma_tx);
+ struct circ_buf *xmit = &sport->port.state->xmit;
+ struct scatterlist *sgl = sport->tx_sgl;
+ struct dma_async_tx_descriptor *desc;
+ struct dma_chan *chan = sport->dma_chan_tx;
+ struct device *dev = sport->port.dev;
+- enum dma_status status;
++ unsigned long flags;
+ int ret;
+
+- status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
+- if (DMA_IN_PROGRESS == status)
++ if (test_and_set_bit(DMA_TX_IS_WORKING, &sport->flags))
+ return;
+
++ spin_lock_irqsave(&sport->port.lock, flags);
+ sport->tx_bytes = uart_circ_chars_pending(xmit);
+
+- if (xmit->tail > xmit->head && xmit->head > 0) {
+- sport->dma_tx_nents = 2;
+- sg_init_table(sgl, 2);
+- sg_set_buf(sgl, xmit->buf + xmit->tail,
+- UART_XMIT_SIZE - xmit->tail);
+- sg_set_buf(sgl + 1, xmit->buf, xmit->head);
+- } else {
+- sport->dma_tx_nents = 1;
+- sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
+- }
++ if (sport->tx_bytes > 0) {
++ if (xmit->tail > xmit->head && xmit->head > 0) {
++ sport->dma_tx_nents = 2;
++ sg_init_table(sgl, 2);
++ sg_set_buf(sgl, xmit->buf + xmit->tail,
++ UART_XMIT_SIZE - xmit->tail);
++ sg_set_buf(sgl + 1, xmit->buf, xmit->head);
++ } else {
++ sport->dma_tx_nents = 1;
++ sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
++ }
++ spin_unlock_irqrestore(&sport->port.lock, flags);
+
+- ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
+- if (ret == 0) {
+- dev_err(dev, "DMA mapping error for TX.\n");
+- return;
+- }
+- desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
+- DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
+- if (!desc) {
+- dev_err(dev, "We cannot prepare for the TX slave dma!\n");
++ ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
++ if (ret == 0) {
++ dev_err(dev, "DMA mapping error for TX.\n");
++ goto err_out;
++ }
++ desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
++ DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
++ if (!desc) {
++ dev_err(dev, "We cannot prepare for the TX slave dma!\n");
++ goto err_out;
++ }
++ desc->callback = dma_tx_callback;
++ desc->callback_param = sport;
++
++ dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
++ uart_circ_chars_pending(xmit));
++ /* fire it */
++ sport->dma_is_txing = 1;
++ dmaengine_submit(desc);
++ dma_async_issue_pending(chan);
+ return;
+ }
+- desc->callback = dma_tx_callback;
+- desc->callback_param = sport;
+-
+- dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
+- uart_circ_chars_pending(xmit));
+- /* fire it */
+- sport->dma_is_txing = 1;
+- dmaengine_submit(desc);
+- dma_async_issue_pending(chan);
+- return;
++ spin_unlock_irqrestore(&sport->port.lock, flags);
++err_out:
++ clear_bit(DMA_TX_IS_WORKING, &sport->flags);
++ smp_mb__after_clear_bit();
+ }
+
+ /*
+@@ -598,7 +640,7 @@
+ }
+
+ if (sport->dma_is_enabled) {
+- imx_dma_tx(sport);
++ schedule_delayed_work(&sport->tsk_dma_tx, 0);
+ return;
+ }
+
+@@ -717,29 +759,6 @@
+ return IRQ_HANDLED;
+ }
+
+-static int start_rx_dma(struct imx_port *sport);
+-/*
+- * If the RXFIFO is filled with some data, and then we
+- * arise a DMA operation to receive them.
+- */
+-static void imx_dma_rxint(struct imx_port *sport)
+-{
+- unsigned long temp;
+-
+- temp = readl(sport->port.membase + USR2);
+- if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
+- sport->dma_is_rxing = 1;
+-
+- /* disable the `Recerver Ready Interrrupt` */
+- temp = readl(sport->port.membase + UCR1);
+- temp &= ~(UCR1_RRDYEN);
+- writel(temp, sport->port.membase + UCR1);
+-
+- /* tell the DMA to receive the data. */
+- start_rx_dma(sport);
+- }
+-}
+-
+ static irqreturn_t imx_int(int irq, void *dev_id)
+ {
+ struct imx_port *sport = dev_id;
+@@ -748,11 +767,11 @@
+
+ sts = readl(sport->port.membase + USR1);
+
+- if (sts & USR1_RRDY) {
+- if (sport->dma_is_enabled)
+- imx_dma_rxint(sport);
+- else
+- imx_rxint(irq, dev_id);
++ if ((sts & USR1_RRDY || sts & USR1_AGTIM) &&
++ !sport->dma_is_enabled) {
++ if (sts & USR1_AGTIM)
++ writel(USR1_AGTIM, sport->port.membase + USR1);
++ imx_rxint(irq, dev_id);
+ }
+
+ if (sts & USR1_TRDY &&
+@@ -765,6 +784,9 @@
+ if (sts & USR1_AWAKE)
+ writel(USR1_AWAKE, sport->port.membase + USR1);
+
++ if (sts & USR1_AIRINT)
++ writel(USR1_AIRINT, sport->port.membase + USR1);
++
+ sts2 = readl(sport->port.membase + USR2);
+ if (sts2 & USR2_ORE) {
+ dev_err(sport->port.dev, "Rx FIFO overrun\n");
+@@ -817,11 +839,9 @@
+ struct imx_port *sport = (struct imx_port *)port;
+ unsigned long temp;
+
+- temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
+-
++ temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
+ if (mctrl & TIOCM_RTS)
+- if (!sport->dma_is_enabled)
+- temp |= UCR2_CTS;
++ temp |= UCR2_CTS | UCR2_CTSC;
+
+ writel(temp, sport->port.membase + UCR2);
+
+@@ -852,29 +872,67 @@
+ }
+
+ #define TXTL 2 /* reset default */
+-#define RXTL 1 /* reset default */
++#define RXTL 1 /* For console port */
++#define RXTL_UART 16 /* For uart */
+
+ static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
+ {
+ unsigned int val;
++ unsigned int rx_fifo_trig;
++
++ if (uart_console(&sport->port))
++ rx_fifo_trig = RXTL;
++ else
++ rx_fifo_trig = RXTL_UART;
+
+ /* set receiver / transmitter trigger level */
+ val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
+- val |= TXTL << UFCR_TXTL_SHF | RXTL;
++ val |= TXTL << UFCR_TXTL_SHF | rx_fifo_trig;
+ writel(val, sport->port.membase + UFCR);
+ return 0;
+ }
+
+ #define RX_BUF_SIZE (PAGE_SIZE)
+-static void imx_rx_dma_done(struct imx_port *sport)
++static int start_rx_dma(struct imx_port *sport);
++
++static void dma_rx_push_data(struct imx_port *sport, struct tty_struct *tty,
++ unsigned int start, unsigned int end)
+ {
+- unsigned long temp;
++ unsigned int i;
++ struct tty_port *port = &sport->port.state->port;
+
+- /* Enable this interrupt when the RXFIFO is empty. */
+- temp = readl(sport->port.membase + UCR1);
+- temp |= UCR1_RRDYEN;
+- writel(temp, sport->port.membase + UCR1);
++ for (i = start; i < end; i++) {
++ if (sport->rx_buf.buf_info[i].filled) {
++ tty_insert_flip_string(port, sport->rx_buf.buf + (i
++ * RX_BUF_SIZE), sport->rx_buf.buf_info[i].rx_bytes);
++ tty_flip_buffer_push(port);
++ sport->rx_buf.buf_info[i].filled = false;
++ sport->rx_buf.last_completed_idx++;
++ sport->rx_buf.last_completed_idx %= IMX_RXBD_NUM;
++ sport->port.icount.rx += sport->rx_buf.buf_info[i].rx_bytes;
++ }
++ }
++}
++
++static void dma_rx_work(struct work_struct *w)
++{
++ struct imx_port *sport = container_of(w, struct imx_port, tsk_dma_rx);
++ struct tty_struct *tty = sport->port.state->port.tty;
++ unsigned int cur_idx = sport->rx_buf.cur_idx;
++
++ if (sport->rx_buf.last_completed_idx < cur_idx) {
++ dma_rx_push_data(sport, tty, sport->rx_buf.last_completed_idx + 1, cur_idx);
++ } else if (sport->rx_buf.last_completed_idx == (IMX_RXBD_NUM - 1)) {
++ dma_rx_push_data(sport, tty, 0, cur_idx);
++ } else {
++ dma_rx_push_data(sport, tty, sport->rx_buf.last_completed_idx + 1,
++ IMX_RXBD_NUM);
++ dma_rx_push_data(sport, tty, 0, cur_idx);
++ }
++}
+
++static void imx_rx_dma_done(struct imx_port *sport)
++{
+ sport->dma_is_rxing = 0;
+
+ /* Is the shutdown waiting for us? */
+@@ -896,17 +954,23 @@
+ {
+ struct imx_port *sport = data;
+ struct dma_chan *chan = sport->dma_chan_rx;
+- struct scatterlist *sgl = &sport->rx_sgl;
+- struct tty_port *port = &sport->port.state->port;
++ struct tty_struct *tty = sport->port.state->port.tty;
+ struct dma_tx_state state;
+ enum dma_status status;
+ unsigned int count;
+
+- /* unmap it first */
+- dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
++ /* If we have finish the reading. we will not accept any more data. */
++ if (tty->closing) {
++ imx_rx_dma_done(sport);
++ return;
++ }
+
+ status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
+ count = RX_BUF_SIZE - state.residue;
++ sport->rx_buf.buf_info[sport->rx_buf.cur_idx].filled = true;
++ sport->rx_buf.buf_info[sport->rx_buf.cur_idx].rx_bytes = count;
++ sport->rx_buf.cur_idx++;
++ sport->rx_buf.cur_idx %= IMX_RXBD_NUM;
+
+ if (readl(sport->port.membase + USR2) & USR2_IDLE) {
+ /* In condition [3] the SDMA counted up too early */
+@@ -917,41 +981,39 @@
+
+ dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
+
+- if (count) {
+- tty_insert_flip_string(port, sport->rx_buf, count);
+- tty_flip_buffer_push(port);
++ if (sport->rx_buf.cur_idx == sport->rx_buf.last_completed_idx)
++ dev_err(sport->port.dev, "overwrite!\n");
+
+- start_rx_dma(sport);
+- } else
+- imx_rx_dma_done(sport);
++ if (count)
++ schedule_work(&sport->tsk_dma_rx);
+ }
+
+ static int start_rx_dma(struct imx_port *sport)
+ {
+- struct scatterlist *sgl = &sport->rx_sgl;
+ struct dma_chan *chan = sport->dma_chan_rx;
+- struct device *dev = sport->port.dev;
+ struct dma_async_tx_descriptor *desc;
+- int ret;
+
+- sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
+- ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
+- if (ret == 0) {
+- dev_err(dev, "DMA mapping error for RX.\n");
+- return -EINVAL;
+- }
+- desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
+- DMA_PREP_INTERRUPT);
++ sport->rx_buf.periods = IMX_RXBD_NUM;
++ sport->rx_buf.period_len = RX_BUF_SIZE;
++ sport->rx_buf.buf_len = IMX_RXBD_NUM * RX_BUF_SIZE;
++ sport->rx_buf.cur_idx = 0;
++ sport->rx_buf.last_completed_idx = -1;
++ desc = dmaengine_prep_dma_cyclic(chan, sport->rx_buf.dmaaddr,
++ sport->rx_buf.buf_len, sport->rx_buf.period_len,
++ DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
+ if (!desc) {
+- dev_err(dev, "We cannot prepare for the RX slave dma!\n");
++ dev_err(sport->port.dev, "Prepare for the RX slave dma failed!\n");
+ return -EINVAL;
+ }
++
+ desc->callback = dma_rx_callback;
+ desc->callback_param = sport;
+
+- dev_dbg(dev, "RX: prepare for the DMA.\n");
++ dev_dbg(sport->port.dev, "RX: prepare for the DMA.\n");
+ dmaengine_submit(desc);
+ dma_async_issue_pending(chan);
++
++ sport->dma_is_rxing = 1;
+ return 0;
+ }
+
+@@ -961,8 +1023,10 @@
+ dma_release_channel(sport->dma_chan_rx);
+ sport->dma_chan_rx = NULL;
+
+- kfree(sport->rx_buf);
+- sport->rx_buf = NULL;
++ dma_free_coherent(NULL, IMX_RXBD_NUM * RX_BUF_SIZE,
++ (void *)sport->rx_buf.buf,
++ sport->rx_buf.dmaaddr);
++ sport->rx_buf.buf = NULL;
+ }
+
+ if (sport->dma_chan_tx) {
+@@ -977,7 +1041,7 @@
+ {
+ struct dma_slave_config slave_config = {};
+ struct device *dev = sport->port.dev;
+- int ret;
++ int ret, i;
+
+ /* Prepare for RX : */
+ sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
+@@ -990,20 +1054,26 @@
+ slave_config.direction = DMA_DEV_TO_MEM;
+ slave_config.src_addr = sport->port.mapbase + URXD0;
+ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+- slave_config.src_maxburst = RXTL;
++ slave_config.src_maxburst = RXTL_UART;
+ ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
+ if (ret) {
+ dev_err(dev, "error in RX dma configuration.\n");
+ goto err;
+ }
+
+- sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+- if (!sport->rx_buf) {
++ sport->rx_buf.buf = dma_alloc_coherent(NULL, IMX_RXBD_NUM * RX_BUF_SIZE,
++ &sport->rx_buf.dmaaddr, GFP_KERNEL);
++ if (!sport->rx_buf.buf) {
+ dev_err(dev, "cannot alloc DMA buffer.\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
++ for (i = 0; i < IMX_RXBD_NUM; i++) {
++ sport->rx_buf.buf_info[i].rx_bytes = 0;
++ sport->rx_buf.buf_info[i].filled = false;
++ }
++
+ /* Prepare for TX : */
+ sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
+ if (!sport->dma_chan_tx) {
+@@ -1035,6 +1105,7 @@
+ unsigned long temp;
+
+ init_waitqueue_head(&sport->dma_wait);
++ sport->flags = 0;
+
+ /* set UCR1 */
+ temp = readl(sport->port.membase + UCR1);
+@@ -1079,7 +1150,7 @@
+ static int imx_startup(struct uart_port *port)
+ {
+ struct imx_port *sport = (struct imx_port *)port;
+- int retval;
++ int retval, i;
+ unsigned long flags, temp;
+
+ retval = clk_prepare_enable(sport->clk_per);
+@@ -1107,17 +1178,15 @@
+
+ writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
+
+- if (USE_IRDA(sport)) {
+- /* reset fifo's and state machines */
+- int i = 100;
+- temp = readl(sport->port.membase + UCR2);
+- temp &= ~UCR2_SRST;
+- writel(temp, sport->port.membase + UCR2);
+- while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
+- (--i > 0)) {
+- udelay(1);
+- }
+- }
++ /* Reset fifo's and state machines */
++ i = 100;
++
++ temp = readl(sport->port.membase + UCR2);
++ temp &= ~UCR2_SRST;
++ writel(temp, sport->port.membase + UCR2);
++
++ while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
++ udelay(1);
+
+ /*
+ * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
+@@ -1125,31 +1194,41 @@
+ */
+ if (sport->txirq > 0) {
+ retval = request_irq(sport->rxirq, imx_rxint, 0,
+- DRIVER_NAME, sport);
++ dev_name(port->dev), sport);
+ if (retval)
+ goto error_out1;
+
+ retval = request_irq(sport->txirq, imx_txint, 0,
+- DRIVER_NAME, sport);
++ dev_name(port->dev), sport);
+ if (retval)
+ goto error_out2;
+
+ /* do not use RTS IRQ on IrDA */
+ if (!USE_IRDA(sport)) {
+ retval = request_irq(sport->rtsirq, imx_rtsint, 0,
+- DRIVER_NAME, sport);
++ dev_name(port->dev), sport);
+ if (retval)
+ goto error_out3;
+ }
+ } else {
+ retval = request_irq(sport->port.irq, imx_int, 0,
+- DRIVER_NAME, sport);
++ dev_name(port->dev), sport);
+ if (retval) {
+ free_irq(sport->port.irq, sport);
+ goto error_out1;
+ }
+ }
+
++ /* Can we enable the DMA support? */
++ if (is_imx6q_uart(sport) && !uart_console(port)
++ && !sport->dma_is_inited)
++ imx_uart_dma_init(sport);
++
++ if (sport->dma_is_inited) {
++ INIT_DELAYED_WORK(&sport->tsk_dma_tx, dma_tx_work);
++ INIT_WORK(&sport->tsk_dma_rx, dma_rx_work);
++ }
++
+ spin_lock_irqsave(&sport->port.lock, flags);
+ /*
+ * Finally, clear and enable interrupts
+@@ -1157,7 +1236,9 @@
+ writel(USR1_RTSD, sport->port.membase + USR1);
+
+ temp = readl(sport->port.membase + UCR1);
+- temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
++ if (!sport->dma_is_inited)
++ temp |= UCR1_RRDYEN;
++ temp |= UCR1_RTSDEN | UCR1_UARTEN;
+
+ if (USE_IRDA(sport)) {
+ temp |= UCR1_IREN;
+@@ -1172,18 +1253,9 @@
+ temp |= UCR2_IRTS;
+ writel(temp, sport->port.membase + UCR2);
+
+- if (USE_IRDA(sport)) {
+- /* clear RX-FIFO */
+- int i = 64;
+- while ((--i > 0) &&
+- (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
+- barrier();
+- }
+- }
+-
+ if (!is_imx1_uart(sport)) {
+ temp = readl(sport->port.membase + UCR3);
+- temp |= IMX21_UCR3_RXDMUXSEL;
++ temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
+ writel(temp, sport->port.membase + UCR3);
+ }
+
+@@ -1238,9 +1310,34 @@
+ unsigned long flags;
+
+ if (sport->dma_is_enabled) {
++ int ret;
++
++ /*
++ * Before DMA finish, we have to disable flow control, otherwise
++ * there have one corner issue like:
++ * Flow control enable, RTS always is high while there have no uart
++ * terminal connect to imx uart, and then user transmit data by the
++ * uart, after some time, TX FIFO is _FULL_, SDMA still don't complete
++ * the current transcation, so hold on. There no SDMA interrupt generate,
++ * the "dma_wait" event cannot be waked up.
++ */
++ if (sport->have_rtscts) {
++ temp = readl(sport->port.membase + UCR2) & ~UCR2_CTSC;
++ temp |= UCR2_CTS;
++ writel(temp, sport->port.membase + UCR2);
++ }
++
+ /* We have to wait for the DMA to finish. */
+- wait_event(sport->dma_wait,
+- !sport->dma_is_rxing && !sport->dma_is_txing);
++ ret = wait_event_interruptible_timeout(sport->dma_wait,
++ !sport->dma_is_rxing && !sport->dma_is_txing,
++ msecs_to_jiffies(1));
++ if (ret <= 0) {
++ sport->dma_is_rxing = 0;
++ sport->dma_is_txing = 0;
++ dmaengine_terminate_all(sport->dma_chan_tx);
++ dmaengine_terminate_all(sport->dma_chan_rx);
++ }
++ imx_stop_tx(port);
+ imx_stop_rx(port);
+ imx_disable_dma(sport);
+ imx_uart_dma_exit(sport);
+@@ -1294,12 +1391,42 @@
+
+ static void imx_flush_buffer(struct uart_port *port)
+ {
++ int i, temp;
+ struct imx_port *sport = (struct imx_port *)port;
+
+ if (sport->dma_is_enabled) {
+ sport->tx_bytes = 0;
+ dmaengine_terminate_all(sport->dma_chan_tx);
+ }
++
++ /* For console port, it is not necessary flush buffer and reset FIFO */
++ if (uart_console(port))
++ return;
++
++ /*
++ * UCR2_SRST will reset the transmit and receive state machines,
++ * all FIFOs and register UBIR, UBMR, UBRC,
++ * and UTS[6-3], so save the required registers
++ */
++ sport->saved_reg[0] = readl(sport->port.membase + UBIR);
++ sport->saved_reg[1] = readl(sport->port.membase + UBMR);
++ sport->saved_reg[2] = readl(sport->port.membase + UBRC);
++ sport->saved_reg[3] = readl(sport->port.membase + IMX21_UTS);
++
++ i = 100;
++
++ temp = readl(sport->port.membase + UCR2);
++ temp &= ~UCR2_SRST;
++ writel(temp, sport->port.membase + UCR2);
++
++ while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
++ udelay(1);
++
++ /* Restore the registers */
++ writel(sport->saved_reg[0], sport->port.membase + UBIR);
++ writel(sport->saved_reg[1], sport->port.membase + UBMR);
++ writel(sport->saved_reg[2], sport->port.membase + UBRC);
++ writel(sport->saved_reg[3], sport->port.membase + IMX21_UTS);
+ }
+
+ static void
+@@ -1342,11 +1469,6 @@
+ if (sport->have_rtscts) {
+ ucr2 &= ~UCR2_IRTS;
+ ucr2 |= UCR2_CTSC;
+-
+- /* Can we enable the DMA support? */
+- if (is_imx6q_uart(sport) && !uart_console(port)
+- && !sport->dma_is_inited)
+- imx_uart_dma_init(sport);
+ } else {
+ termios->c_cflag &= ~CRTSCTS;
+ }
+@@ -1465,8 +1587,16 @@
+ if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
+ imx_enable_ms(&sport->port);
+
+- if (sport->dma_is_inited && !sport->dma_is_enabled)
++ if (sport->dma_is_inited && !sport->dma_is_enabled) {
+ imx_enable_dma(sport);
++ start_rx_dma(sport);
++ }
++
++ if (!sport->dma_is_enabled) {
++ ucr2 = readl(sport->port.membase + UCR2);
++ writel(ucr2 | UCR2_ATEN, sport->port.membase + UCR2);
++ }
++
+ spin_unlock_irqrestore(&sport->port.lock, flags);
+ }
+
+@@ -1478,44 +1608,13 @@
+ }
+
+ /*
+- * Release the memory region(s) being used by 'port'.
+- */
+-static void imx_release_port(struct uart_port *port)
+-{
+- struct platform_device *pdev = to_platform_device(port->dev);
+- struct resource *mmres;
+-
+- mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- release_mem_region(mmres->start, resource_size(mmres));
+-}
+-
+-/*
+- * Request the memory region(s) being used by 'port'.
+- */
+-static int imx_request_port(struct uart_port *port)
+-{
+- struct platform_device *pdev = to_platform_device(port->dev);
+- struct resource *mmres;
+- void *ret;
+-
+- mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!mmres)
+- return -ENODEV;
+-
+- ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
+-
+- return ret ? 0 : -EBUSY;
+-}
+-
+-/*
+ * Configure/autoconfigure the port.
+ */
+ static void imx_config_port(struct uart_port *port, int flags)
+ {
+ struct imx_port *sport = (struct imx_port *)port;
+
+- if (flags & UART_CONFIG_TYPE &&
+- imx_request_port(&sport->port) == 0)
++ if (flags & UART_CONFIG_TYPE)
+ sport->port.type = PORT_IMX;
+ }
+
+@@ -1625,8 +1724,6 @@
+ .flush_buffer = imx_flush_buffer,
+ .set_termios = imx_set_termios,
+ .type = imx_type,
+- .release_port = imx_release_port,
+- .request_port = imx_request_port,
+ .config_port = imx_config_port,
+ .verify_port = imx_verify_port,
+ #if defined(CONFIG_CONSOLE_POLL)
+@@ -1854,11 +1951,27 @@
+
+ /* enable wakeup from i.MX UART */
+ val = readl(sport->port.membase + UCR3);
+- val |= UCR3_AWAKEN;
++ if (USE_IRDA(sport))
++ val |= UCR3_AIRINTEN;
++ else
++ val |= UCR3_AWAKEN;
+ writel(val, sport->port.membase + UCR3);
+
+ uart_suspend_port(&imx_reg, &sport->port);
+
++ /* Save necessary regs */
++ sport->saved_reg[0] = readl(sport->port.membase + UCR1);
++ sport->saved_reg[1] = readl(sport->port.membase + UCR2);
++ sport->saved_reg[2] = readl(sport->port.membase + UCR3);
++ sport->saved_reg[3] = readl(sport->port.membase + UCR4);
++ sport->saved_reg[4] = readl(sport->port.membase + UFCR);
++ sport->saved_reg[5] = readl(sport->port.membase + UESC);
++ sport->saved_reg[6] = readl(sport->port.membase + UTIM);
++ sport->saved_reg[7] = readl(sport->port.membase + UBIR);
++ sport->saved_reg[8] = readl(sport->port.membase + UBMR);
++ sport->saved_reg[9] = readl(sport->port.membase + UBRC);
++ sport->saved_reg[10] = readl(sport->port.membase + IMX21_UTS);
++
+ return 0;
+ }
+
+@@ -1867,9 +1980,21 @@
+ struct imx_port *sport = platform_get_drvdata(dev);
+ unsigned int val;
+
++ writel(sport->saved_reg[4], sport->port.membase + UFCR);
++ writel(sport->saved_reg[5], sport->port.membase + UESC);
++ writel(sport->saved_reg[6], sport->port.membase + UTIM);
++ writel(sport->saved_reg[7], sport->port.membase + UBIR);
++ writel(sport->saved_reg[8], sport->port.membase + UBMR);
++ writel(sport->saved_reg[9], sport->port.membase + UBRC);
++ writel(sport->saved_reg[10], sport->port.membase + IMX21_UTS);
++ writel(sport->saved_reg[0], sport->port.membase + UCR1);
++ writel(sport->saved_reg[1] | 0x1, sport->port.membase + UCR2);
++ writel(sport->saved_reg[2], sport->port.membase + UCR3);
++ writel(sport->saved_reg[3], sport->port.membase + UCR4);
++
+ /* disable wakeup from i.MX UART */
+ val = readl(sport->port.membase + UCR3);
+- val &= ~UCR3_AWAKEN;
++ val &= ~(UCR3_AWAKEN | UCR3_AIRINTEN);
+ writel(val, sport->port.membase + UCR3);
+
+ uart_resume_port(&imx_reg, &sport->port);
+@@ -1943,7 +2068,6 @@
+ static int serial_imx_probe(struct platform_device *pdev)
+ {
+ struct imx_port *sport;
+- struct imxuart_platform_data *pdata;
+ void __iomem *base;
+ int ret = 0;
+ struct resource *res;
+@@ -1959,12 +2083,9 @@
+ return ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- if (!res)
+- return -ENODEV;
+-
+- base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
+- if (!base)
+- return -ENOMEM;
++ base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
+
+ sport->port.dev = &pdev->dev;
+ sport->port.mapbase = res->start;
+@@ -2000,38 +2121,16 @@
+
+ imx_ports[sport->port.line] = sport;
+
+- pdata = dev_get_platdata(&pdev->dev);
+- if (pdata && pdata->init) {
+- ret = pdata->init(pdev);
+- if (ret)
+- return ret;
+- }
+-
+- ret = uart_add_one_port(&imx_reg, &sport->port);
+- if (ret)
+- goto deinit;
+ platform_set_drvdata(pdev, sport);
+
+- return 0;
+-deinit:
+- if (pdata && pdata->exit)
+- pdata->exit(pdev);
+- return ret;
++ return uart_add_one_port(&imx_reg, &sport->port);
+ }
+
+ static int serial_imx_remove(struct platform_device *pdev)
+ {
+- struct imxuart_platform_data *pdata;
+ struct imx_port *sport = platform_get_drvdata(pdev);
+
+- pdata = dev_get_platdata(&pdev->dev);
+-
+- uart_remove_one_port(&imx_reg, &sport->port);
+-
+- if (pdata && pdata->exit)
+- pdata->exit(pdev);
+-
+- return 0;
++ return uart_remove_one_port(&imx_reg, &sport->port);
+ }
+
+ static struct platform_driver serial_imx_driver = {
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/bits.h linux-3.14.72/drivers/usb/chipidea/bits.h
+--- linux-3.14.72.orig/drivers/usb/chipidea/bits.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/bits.h 2016-06-19 22:11:55.321138957 +0200
+@@ -15,6 +15,18 @@
+
+ #include <linux/usb/ehci_def.h>
+
++/*
++ * ID
++ * For 1.x revision, bit24 - bit31 are reserved
++ * For 2.x revision, bit25 - bit28 are 0x2
++ */
++#define TAG (0x1F << 16)
++#define REVISION (0xF << 21)
++#define VERSION (0xF << 25)
++#define CIVERSION (0x7 << 29)
++
++/* SBUSCFG */
++#define SBUSCFG_AHBBRST (BIT(0) | BIT(1) | BIT(2))
+ /* HCCPARAMS */
+ #define HCCPARAMS_LEN BIT(17)
+
+@@ -43,19 +55,33 @@
+ #define DEVICEADDR_USBADRA BIT(24)
+ #define DEVICEADDR_USBADR (0x7FUL << 25)
+
++/* BURSTSIZE */
++#define BURST_BITS 0xffff
++
+ /* PORTSC */
++#define PORTSC_CCS BIT(0)
++#define PORTSC_CSC BIT(1)
++#define PORTSC_PEC BIT(3)
++#define PORTSC_OCC BIT(5)
+ #define PORTSC_FPR BIT(6)
+ #define PORTSC_SUSP BIT(7)
+ #define PORTSC_HSP BIT(9)
++#define PORTSC_PP BIT(12)
+ #define PORTSC_PTC (0x0FUL << 16)
++#define PORTSC_WKCN BIT(20)
+ #define PORTSC_PHCD(d) ((d) ? BIT(22) : BIT(23))
+ /* PTS and PTW for non lpm version only */
++#define PORTSC_PFSC BIT(24)
+ #define PORTSC_PTS(d) \
+ (u32)((((d) & 0x3) << 30) | (((d) & 0x4) ? BIT(25) : 0))
+ #define PORTSC_PTW BIT(28)
+ #define PORTSC_STS BIT(29)
+
++#define PORTSC_W1C_BITS \
++ (PORTSC_CSC | PORTSC_PEC | PORTSC_OCC)
++
+ /* DEVLC */
++#define DEVLC_PFSC BIT(23)
+ #define DEVLC_PSPD (0x03UL << 25)
+ #define DEVLC_PSPD_HS (0x02UL << 25)
+ #define DEVLC_PTW BIT(27)
+@@ -70,6 +96,8 @@
+
+ /* OTGSC */
+ #define OTGSC_IDPU BIT(5)
++#define OTGSC_HADP BIT(6)
++#define OTGSC_HABA BIT(7)
+ #define OTGSC_ID BIT(8)
+ #define OTGSC_AVV BIT(9)
+ #define OTGSC_ASV BIT(10)
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/ci.h linux-3.14.72/drivers/usb/chipidea/ci.h
+--- linux-3.14.72.orig/drivers/usb/chipidea/ci.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/ci.h 2016-06-19 22:11:55.321138957 +0200
+@@ -17,6 +17,7 @@
+ #include <linux/irqreturn.h>
+ #include <linux/usb.h>
+ #include <linux/usb/gadget.h>
++#include <linux/usb/otg-fsm.h>
+
+ /******************************************************************************
+ * DEFINE
+@@ -28,6 +29,15 @@
+ /******************************************************************************
+ * REGISTERS
+ *****************************************************************************/
++/* Identification Registers */
++#define ID_ID 0x0
++#define ID_HWGENERAL 0x4
++#define ID_HWHOST 0x8
++#define ID_HWDEVICE 0xc
++#define ID_HWTXBUF 0x10
++#define ID_HWRXBUF 0x14
++#define ID_SBUSCFG 0x90
++
+ /* register indices */
+ enum ci_hw_regs {
+ CAP_CAPLENGTH,
+@@ -41,6 +51,7 @@
+ OP_DEVICEADDR,
+ OP_ENDPTLISTADDR,
+ OP_PORTSC,
++ OP_BURSTSIZE,
+ OP_DEVLC,
+ OP_OTGSC,
+ OP_USBMODE,
+@@ -96,17 +107,33 @@
+ CI_ROLE_END,
+ };
+
++enum ci_revision {
++ CI_REVISION_1X = 10, /* Revision 1.x */
++ CI_REVISION_20 = 20, /* Revision 2.0 */
++ CI_REVISION_21, /* Revision 2.1 */
++ CI_REVISION_22, /* Revision 2.2 */
++ CI_REVISION_23, /* Revision 2.3 */
++ CI_REVISION_24, /* Revision 2.4 */
++ CI_REVISION_25, /* Revision 2.5 */
++ CI_REVISION_25_PLUS, /* Revision above than 2.5 */
++ CI_REVISION_UNKNOWN = 99, /* Unknown Revision */
++};
++
+ /**
+ * struct ci_role_driver - host/gadget role driver
+- * start: start this role
+- * stop: stop this role
+- * irq: irq handler for this role
+- * name: role name string (host/gadget)
++ * @start: start this role
++ * @stop: stop this role
++ * @irq: irq handler for this role
++ * @suspend: system suspend handler for this role
++ * @resume: system resume handler for this role
++ * @name: role name string (host/gadget)
+ */
+ struct ci_role_driver {
+ int (*start)(struct ci_hdrc *);
+ void (*stop)(struct ci_hdrc *);
+ irqreturn_t (*irq)(struct ci_hdrc *);
++ void (*suspend)(struct ci_hdrc *);
++ void (*resume)(struct ci_hdrc *, bool power_lost);
+ const char *name;
+ };
+
+@@ -139,6 +166,9 @@
+ * @roles: array of supported roles for this controller
+ * @role: current role
+ * @is_otg: if the device is otg-capable
++ * @fsm: otg finite state machine
++ * @fsm_timer: pointer to timer list of otg fsm
++ * @hnp_polling_work: work for hnp polling
+ * @work: work for role changing
+ * @wq: workqueue thread
+ * @qh_pool: allocation pool for queue heads
+@@ -158,13 +188,19 @@
+ * @test_mode: the selected test mode
+ * @platdata: platform specific information supplied by parent device
+ * @vbus_active: is VBUS active
+- * @transceiver: pointer to USB PHY, if any
++ * @phy: pointer to PHY, if any
++ * @usb_phy: pointer to USB PHY, if any and if using the USB PHY framework
+ * @hcd: pointer to usb_hcd for ehci host driver
+ * @debugfs: root dentry for this controller in debugfs
+ * @id_event: indicates there is an id event, and handled at ci_otg_work
+ * @b_sess_valid_event: indicates there is a vbus event, and handled
++ * @vbus_glitch_check_event: check if vbus change is a glitch
+ * at ci_otg_work
+ * @imx28_write_fix: Freescale imx28 needs swp instruction for writing
++ * @supports_runtime_pm: if runtime pm is supported
++ * @in_lpm: if the core in low power mode
++ * @wakeup_int: if wakeup interrupt occur
++ * @rev: The revision number for controller
+ */
+ struct ci_hdrc {
+ struct device *dev;
+@@ -174,6 +210,11 @@
+ struct ci_role_driver *roles[CI_ROLE_END];
+ enum ci_role role;
+ bool is_otg;
++ struct usb_otg otg;
++ struct otg_fsm fsm;
++ struct ci_otg_fsm_timer_list *fsm_timer;
++ struct timer_list hnp_polling_timer;
++ struct work_struct hnp_polling_work;
+ struct work_struct work;
+ struct workqueue_struct *wq;
+
+@@ -196,14 +237,31 @@
+
+ struct ci_hdrc_platform_data *platdata;
+ int vbus_active;
+- /* FIXME: some day, we'll not use global phy */
+- bool global_phy;
+- struct usb_phy *transceiver;
++ struct phy *phy;
++ /* old usb_phy interface */
++ struct usb_phy *usb_phy;
+ struct usb_hcd *hcd;
+ struct dentry *debugfs;
+ bool id_event;
+ bool b_sess_valid_event;
++ bool vbus_glitch_check_event;
+ bool imx28_write_fix;
++ bool supports_runtime_pm;
++ bool in_lpm;
++ bool wakeup_int;
++ enum ci_revision rev;
++ /* register save area for suspend&resume */
++ u32 pm_command;
++ u32 pm_status;
++ u32 pm_intr_enable;
++ u32 pm_frame_index;
++ u32 pm_segment;
++ u32 pm_frame_list;
++ u32 pm_async_next;
++ u32 pm_configured_flag;
++ u32 pm_portsc;
++ u32 pm_usbmode;
++ struct work_struct power_lost_work;
+ };
+
+ static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci)
+@@ -241,7 +299,38 @@
+ }
+
+ /**
++ * hw_read_id_reg: reads from a identification register
++ * @ci: the controller
++ * @offset: offset from the beginning of identification registers region
++ * @mask: bitfield mask
++ *
++ * This function returns register contents
++ */
++static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
++{
++ return ioread32(ci->hw_bank.abs + offset) & mask;
++}
++
++/**
++ * hw_write_id_reg: writes to a identification register
++ * @ci: the controller
++ * @offset: offset from the beginning of identification registers region
++ * @mask: bitfield mask
++ * @data: new value
++ */
++static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
++ u32 mask, u32 data)
++{
++ if (~mask)
++ data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
++ | (data & mask);
++
++ iowrite32(data, ci->hw_bank.abs + offset);
++}
++
++/**
+ * hw_read: reads from a hw register
++ * @ci: the controller
+ * @reg: register index
+ * @mask: bitfield mask
+ *
+@@ -274,6 +363,7 @@
+
+ /**
+ * hw_write: writes to a hw register
++ * @ci: the controller
+ * @reg: register index
+ * @mask: bitfield mask
+ * @data: new value
+@@ -290,6 +380,7 @@
+
+ /**
+ * hw_test_and_clear: tests & clears a hw register
++ * @ci: the controller
+ * @reg: register index
+ * @mask: bitfield mask
+ *
+@@ -306,6 +397,7 @@
+
+ /**
+ * hw_test_and_write: tests & writes a hw register
++ * @ci: the controller
+ * @reg: register index
+ * @mask: bitfield mask
+ * @data: new value
+@@ -321,7 +413,27 @@
+ return (val & mask) >> __ffs(mask);
+ }
+
+-int hw_device_reset(struct ci_hdrc *ci, u32 mode);
++/**
++ * ci_otg_is_fsm_mode: runtime check if otg controller
++ * is in otg fsm mode.
++ *
++ * @ci: chipidea device
++ */
++static inline bool ci_otg_is_fsm_mode(struct ci_hdrc *ci)
++{
++#ifdef CONFIG_USB_OTG_FSM
++ return ci->is_otg && ci->roles[CI_ROLE_HOST] &&
++ ci->roles[CI_ROLE_GADGET];
++#else
++ return false;
++#endif
++}
++
++u32 hw_read_intr_enable(struct ci_hdrc *ci);
++
++u32 hw_read_intr_status(struct ci_hdrc *ci);
++
++int hw_device_reset(struct ci_hdrc *ci);
+
+ int hw_port_test_set(struct ci_hdrc *ci, u8 mode);
+
+@@ -330,4 +442,7 @@
+ int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
+ u32 value, unsigned int timeout_ms);
+
++int hw_controller_reset(struct ci_hdrc *ci);
++void ci_hdrc_ahb_config(struct ci_hdrc *ci);
++
+ #endif /* __DRIVERS_USB_CHIPIDEA_CI_H */
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_imx.c linux-3.14.72/drivers/usb/chipidea/ci_hdrc_imx.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/ci_hdrc_imx.c 2016-06-19 22:11:55.321138957 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+@@ -19,26 +19,71 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/usb/chipidea.h>
+ #include <linux/clk.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
++#include <linux/power/imx6_usb_charger.h>
++#include <linux/busfreq-imx6.h>
++#include <linux/regulator/consumer.h>
+
+ #include "ci.h"
+ #include "ci_hdrc_imx.h"
+
+-#define CI_HDRC_IMX_IMX28_WRITE_FIX BIT(0)
+-
+ struct ci_hdrc_imx_platform_flag {
+ unsigned int flags;
++ bool runtime_pm;
++ u32 ahbburst_config;
++ u32 burst_length;
+ };
+
+ static const struct ci_hdrc_imx_platform_flag imx27_usb_data = {
+ };
+
+ static const struct ci_hdrc_imx_platform_flag imx28_usb_data = {
+- .flags = CI_HDRC_IMX_IMX28_WRITE_FIX,
++ .flags = CI_HDRC_IMX28_WRITE_FIX |
++ CI_HDRC_IMX_EHCI_QUIRK |
++ CI_HDRC_DISABLE_STREAMING,
++};
++
++static const struct ci_hdrc_imx_platform_flag imx6q_usb_data = {
++ .flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
++ CI_HDRC_IMX_EHCI_QUIRK |
++ CI_HDRC_DISABLE_STREAMING |
++ CI_HDRC_OVERRIDE_AHB_BURST |
++ CI_HDRC_OVERRIDE_BURST_LENGTH |
++ CI_HDRC_IMX_VBUS_EARLY_ON,
++ .ahbburst_config = 0, /*bit0 - bit2 at $BASE + 0x90 */
++ .burst_length = 0x1010, /*bit0 - bit15 at $BASE + 0x160 */
++};
++
++static const struct ci_hdrc_imx_platform_flag imx6sl_usb_data = {
++ .flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
++ CI_HDRC_IMX_EHCI_QUIRK |
++ CI_HDRC_DISABLE_HOST_STREAMING |
++ CI_HDRC_OVERRIDE_AHB_BURST |
++ CI_HDRC_OVERRIDE_BURST_LENGTH |
++ CI_HDRC_IMX_VBUS_EARLY_ON,
++ .ahbburst_config = 0,
++ .burst_length = 0x1010,
++};
++
++static const struct ci_hdrc_imx_platform_flag imx6sx_usb_data = {
++ .flags = CI_HDRC_SUPPORTS_RUNTIME_PM |
++ CI_HDRC_IMX_EHCI_QUIRK |
++ CI_HDRC_DISABLE_HOST_STREAMING |
++ CI_HDRC_OVERRIDE_AHB_BURST |
++ CI_HDRC_OVERRIDE_BURST_LENGTH |
++ CI_HDRC_IMX_VBUS_EARLY_ON,
++ .ahbburst_config = 0,
++ .burst_length = 0x1010,
+ };
+
+ static const struct of_device_id ci_hdrc_imx_dt_ids[] = {
+ { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
+ { .compatible = "fsl,imx27-usb", .data = &imx27_usb_data},
++ { .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data},
++ { .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data},
++ { .compatible = "fsl,imx6sx-usb", .data = &imx6sx_usb_data},
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, ci_hdrc_imx_dt_ids);
+@@ -48,12 +93,43 @@
+ struct platform_device *ci_pdev;
+ struct clk *clk;
+ struct imx_usbmisc_data *usbmisc_data;
++ bool supports_runtime_pm;
++ bool in_lpm;
++ bool imx6_usb_charger_detection;
++ struct usb_charger charger;
++ struct regmap *anatop;
++ struct pinctrl *pinctrl;
++ struct pinctrl_state *pinctrl_hsic_active;
++ struct regulator *hsic_pad_regulator;
++ const struct ci_hdrc_imx_platform_flag *data;
+ };
+
++static inline bool is_imx6q_con(struct ci_hdrc_imx_data *imx_data)
++{
++ return imx_data->data == &imx6q_usb_data;
++}
++
++static inline bool is_imx6sl_con(struct ci_hdrc_imx_data *imx_data)
++{
++ return imx_data->data == &imx6sl_usb_data;
++}
++
++static inline bool is_imx6sx_con(struct ci_hdrc_imx_data *imx_data)
++{
++ return imx_data->data == &imx6sx_usb_data;
++}
++
++static inline bool imx_has_hsic_con(struct ci_hdrc_imx_data *imx_data)
++{
++ return is_imx6q_con(imx_data) || is_imx6sl_con(imx_data)
++ || is_imx6sx_con(imx_data);
++}
++
+ /* Common functions shared by usbmisc drivers */
+
+ static struct imx_usbmisc_data *usbmisc_get_init_data(struct device *dev)
+ {
++ struct platform_device *misc_pdev;
+ struct device_node *np = dev->of_node;
+ struct of_phandle_args args;
+ struct imx_usbmisc_data *data;
+@@ -79,43 +155,155 @@
+ }
+
+ data->index = args.args[0];
++
++ misc_pdev = of_find_device_by_node(args.np);
+ of_node_put(args.np);
+
++ if (!misc_pdev)
++ return ERR_PTR(-EPROBE_DEFER);
++
++ data->dev = &misc_pdev->dev;
++
+ if (of_find_property(np, "disable-over-current", NULL))
+ data->disable_oc = 1;
+
+ if (of_find_property(np, "external-vbus-divider", NULL))
+ data->evdo = 1;
+
++ if (of_find_property(np, "osc-clkgate-delay", NULL)) {
++ ret = of_property_read_u32(np, "osc-clkgate-delay",
++ &data->osc_clkgate_delay);
++ if (ret) {
++ dev_err(dev,
++ "failed to get osc-clkgate-delay value\n");
++ return ERR_PTR(ret);
++ }
++ /*
++ * 0 <= osc_clkgate_delay <=7
++ * - 0x0 (default) is 0.5ms,
++ * - 0x1-0x7: 1-7ms
++ */
++ if (data->osc_clkgate_delay > 7) {
++ dev_err(dev,
++ "value of osc-clkgate-delay is incorrect\n");
++ return ERR_PTR(-EINVAL);
++ }
++ }
++
+ return data;
+ }
+
+ /* End of common functions shared by usbmisc drivers*/
+
++static int ci_hdrc_imx_notify_event(struct ci_hdrc *ci, unsigned event)
++{
++ struct device *dev = ci->dev->parent;
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret = 0;
++
++ switch (event) {
++ case CI_HDRC_CONTROLLER_VBUS_EVENT:
++ if (data->usbmisc_data && ci->vbus_active) {
++ if (data->imx6_usb_charger_detection) {
++ ret = imx6_usb_vbus_connect(&data->charger);
++ if (!ret && data->charger.psy.type !=
++ POWER_SUPPLY_TYPE_USB)
++ ret = CI_HDRC_NOTIFY_RET_DEFER_EVENT;
++ }
++ } else if (data->usbmisc_data && !ci->vbus_active) {
++ if (data->imx6_usb_charger_detection)
++ ret = imx6_usb_vbus_disconnect(&data->charger);
++ }
++ break;
++ case CI_HDRC_CONTROLLER_CHARGER_POST_EVENT:
++ if (!data->imx6_usb_charger_detection)
++ return ret;
++ imx6_usb_charger_detect_post(&data->charger);
++ break;
++ case CI_HDRC_IMX_HSIC_ACTIVE_EVENT:
++ if (!IS_ERR(data->pinctrl) &&
++ !IS_ERR(data->pinctrl_hsic_active)) {
++ ret = pinctrl_select_state(data->pinctrl,
++ data->pinctrl_hsic_active);
++ if (ret)
++ dev_err(dev,
++ "hsic_active select failed, err=%d\n",
++ ret);
++ return ret;
++ }
++ break;
++ case CI_HDRC_IMX_HSIC_SUSPEND_EVENT:
++ if (data->usbmisc_data) {
++ ret = imx_usbmisc_hsic_set_connect(data->usbmisc_data);
++ if (ret)
++ dev_err(dev,
++ "hsic_set_connect failed, err=%d\n",
++ ret);
++ return ret;
++ }
++ break;
++ default:
++ dev_dbg(dev, "unknown event\n");
++ }
++
++ return ret;
++}
++
+ static int ci_hdrc_imx_probe(struct platform_device *pdev)
+ {
+ struct ci_hdrc_imx_data *data;
+ struct ci_hdrc_platform_data pdata = {
+- .name = "ci_hdrc_imx",
++ .name = dev_name(&pdev->dev),
+ .capoffset = DEF_CAPOFFSET,
+- .flags = CI_HDRC_REQUIRE_TRANSCEIVER |
+- CI_HDRC_DISABLE_STREAMING,
++ .notify_event = ci_hdrc_imx_notify_event,
+ };
+ int ret;
+ const struct of_device_id *of_id =
+ of_match_device(ci_hdrc_imx_dt_ids, &pdev->dev);
+ const struct ci_hdrc_imx_platform_flag *imx_platform_flag = of_id->data;
++ struct device_node *np = pdev->dev.of_node;
++ struct pinctrl_state *pinctrl_hsic_idle;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+- if (!data) {
+- dev_err(&pdev->dev, "Failed to allocate ci_hdrc-imx data!\n");
++ if (!data)
+ return -ENOMEM;
+- }
+
++ platform_set_drvdata(pdev, data);
++
++ data->data = imx_platform_flag;
+ data->usbmisc_data = usbmisc_get_init_data(&pdev->dev);
+ if (IS_ERR(data->usbmisc_data))
+ return PTR_ERR(data->usbmisc_data);
+
++ data->pinctrl = devm_pinctrl_get(&pdev->dev);
++ if (IS_ERR(data->pinctrl)) {
++ dev_dbg(&pdev->dev, "pinctrl get failed, err=%ld\n",
++ PTR_ERR(data->pinctrl));
++ } else {
++ pinctrl_hsic_idle = pinctrl_lookup_state(data->pinctrl, "idle");
++ if (IS_ERR(pinctrl_hsic_idle)) {
++ dev_dbg(&pdev->dev,
++ "pinctrl_hsic_idle lookup failed, err=%ld\n",
++ PTR_ERR(pinctrl_hsic_idle));
++ } else {
++ ret = pinctrl_select_state(data->pinctrl,
++ pinctrl_hsic_idle);
++ if (ret) {
++ dev_err(&pdev->dev,
++ "hsic_idle select failed, err=%d\n",
++ ret);
++ return ret;
++ }
++ }
++
++ data->pinctrl_hsic_active = pinctrl_lookup_state(data->pinctrl,
++ "active");
++ if (IS_ERR(data->pinctrl_hsic_active))
++ dev_dbg(&pdev->dev,
++ "pinctrl_hsic_active lookup failed, err=%ld\n",
++ PTR_ERR(data->pinctrl_hsic_active));
++ }
++
+ data->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(data->clk)) {
+ dev_err(&pdev->dev,
+@@ -123,8 +311,10 @@
+ return PTR_ERR(data->clk);
+ }
+
++ request_bus_freq(BUS_FREQ_HIGH);
+ ret = clk_prepare_enable(data->clk);
+ if (ret) {
++ release_bus_freq(BUS_FREQ_HIGH);
+ dev_err(&pdev->dev,
+ "Failed to prepare or enable clock, err=%d\n", ret);
+ return ret;
+@@ -133,27 +323,88 @@
+ data->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "fsl,usbphy", 0);
+ if (IS_ERR(data->phy)) {
+ ret = PTR_ERR(data->phy);
++ /* Return -EINVAL if no usbphy is available */
++ if (ret == -ENODEV)
++ ret = -EINVAL;
+ goto err_clk;
+ }
+
+- pdata.phy = data->phy;
+-
+- if (imx_platform_flag->flags & CI_HDRC_IMX_IMX28_WRITE_FIX)
+- pdata.flags |= CI_HDRC_IMX28_WRITE_FIX;
++ pdata.usb_phy = data->phy;
++ pdata.flags |= imx_platform_flag->flags;
++ if (pdata.flags & CI_HDRC_SUPPORTS_RUNTIME_PM)
++ data->supports_runtime_pm = true;
+
+ ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret)
+ goto err_clk;
+
+- if (data->usbmisc_data) {
+- ret = imx_usbmisc_init(data->usbmisc_data);
+- if (ret) {
+- dev_err(&pdev->dev, "usbmisc init failed, ret=%d\n",
+- ret);
++ if (data->usbmisc_data->index > 1 && (imx_has_hsic_con(data))) {
++ pdata.flags |= CI_HDRC_IMX_IS_HSIC;
++ data->hsic_pad_regulator = devm_regulator_get(&pdev->dev,
++ "pad");
++ if (PTR_ERR(data->hsic_pad_regulator) == -EPROBE_DEFER) {
++ ret = -EPROBE_DEFER;
++ goto err_clk;
++ } else if (PTR_ERR(data->hsic_pad_regulator) == -ENODEV) {
++ /* no pad regualator is needed */
++ data->hsic_pad_regulator = NULL;
++ } else if (IS_ERR(data->hsic_pad_regulator)) {
++ dev_err(&pdev->dev,
++ "Get hsic pad regulator error: %ld\n",
++ PTR_ERR(data->hsic_pad_regulator));
++ ret = PTR_ERR(data->hsic_pad_regulator);
+ goto err_clk;
+ }
++
++ if (data->hsic_pad_regulator) {
++ ret = regulator_enable(data->hsic_pad_regulator);
++ if (ret) {
++ dev_err(&pdev->dev,
++ "Fail to enable hsic pad regulator\n");
++ goto err_clk;
++ }
++ }
++ }
++
++ if (of_find_property(np, "imx6-usb-charger-detection", NULL))
++ data->imx6_usb_charger_detection = true;
++
++ if (of_find_property(np, "fsl,anatop", NULL)) {
++ data->anatop = syscon_regmap_lookup_by_phandle(np,
++ "fsl,anatop");
++ if (IS_ERR(data->anatop)) {
++ dev_dbg(&pdev->dev,
++ "failed to find regmap for anatop\n");
++ ret = PTR_ERR(data->anatop);
++ goto disable_hsic_regulator;
++ }
++ if (data->usbmisc_data)
++ data->usbmisc_data->anatop = data->anatop;
++ if (data->imx6_usb_charger_detection) {
++ data->charger.anatop = data->anatop;
++ data->charger.dev = &pdev->dev;
++ ret = imx6_usb_create_charger(&data->charger,
++ "imx6_usb_charger");
++ if (ret && ret != -ENODEV)
++ goto disable_hsic_regulator;
++ if (!ret)
++ dev_dbg(&pdev->dev,
++ "USB Charger is created\n");
++ }
+ }
+
++ ret = imx_usbmisc_init(data->usbmisc_data);
++ if (ret) {
++ dev_err(&pdev->dev, "usbmisc init failed, ret=%d\n", ret);
++ goto remove_charger;
++ }
++
++ if (imx_platform_flag->flags & CI_HDRC_OVERRIDE_AHB_BURST)
++ pdata.ahbburst_config = imx_platform_flag->ahbburst_config;
++
++ if (imx_platform_flag->flags & CI_HDRC_OVERRIDE_BURST_LENGTH)
++ pdata.burst_length = imx_platform_flag->burst_length;
++
+ data->ci_pdev = ci_hdrc_add_device(&pdev->dev,
+ pdev->resource, pdev->num_resources,
+ &pdata);
+@@ -162,29 +413,45 @@
+ dev_err(&pdev->dev,
+ "Can't register ci_hdrc platform device, err=%d\n",
+ ret);
+- goto err_clk;
++ goto remove_charger;
+ }
+
+- if (data->usbmisc_data) {
+- ret = imx_usbmisc_init_post(data->usbmisc_data);
+- if (ret) {
+- dev_err(&pdev->dev, "usbmisc post failed, ret=%d\n",
+- ret);
+- goto disable_device;
+- }
++ ret = imx_usbmisc_init_post(data->usbmisc_data);
++ if (ret) {
++ dev_err(&pdev->dev, "usbmisc post failed, ret=%d\n", ret);
++ goto disable_device;
+ }
+
+- platform_set_drvdata(pdev, data);
++ ret = imx_usbmisc_set_wakeup(data->usbmisc_data, false);
++ if (ret) {
++ dev_err(&pdev->dev, "usbmisc set_wakeup failed, ret=%d\n", ret);
++ goto disable_device;
++ }
+
+- pm_runtime_no_callbacks(&pdev->dev);
+- pm_runtime_enable(&pdev->dev);
++ /* usbmisc needs to know dr mode to choose wakeup setting */
++ data->usbmisc_data->available_role =
++ ci_hdrc_query_available_role(data->ci_pdev);
++
++ if (data->supports_runtime_pm) {
++ pm_runtime_set_active(&pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++ }
++
++ device_set_wakeup_capable(&pdev->dev, true);
+
+ return 0;
+
+ disable_device:
+ ci_hdrc_remove_device(data->ci_pdev);
++remove_charger:
++ if (data->imx6_usb_charger_detection)
++ imx6_usb_remove_charger(&data->charger);
++disable_hsic_regulator:
++ if (data->hsic_pad_regulator)
++ ret = regulator_disable(data->hsic_pad_regulator);
+ err_clk:
+ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
+ return ret;
+ }
+
+@@ -192,13 +459,172 @@
+ {
+ struct ci_hdrc_imx_data *data = platform_get_drvdata(pdev);
+
+- pm_runtime_disable(&pdev->dev);
++ if (data->supports_runtime_pm) {
++ pm_runtime_get_sync(&pdev->dev);
++ pm_runtime_disable(&pdev->dev);
++ pm_runtime_put_noidle(&pdev->dev);
++ }
+ ci_hdrc_remove_device(data->ci_pdev);
+ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ if (data->imx6_usb_charger_detection)
++ imx6_usb_remove_charger(&data->charger);
++ if (data->hsic_pad_regulator)
++ regulator_disable(data->hsic_pad_regulator);
+
+ return 0;
+ }
+
++#ifdef CONFIG_PM
++static int imx_controller_suspend(struct device *dev)
++{
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret;
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (data->usbmisc_data) {
++ ret = imx_usbmisc_hsic_set_clk(data->usbmisc_data, false);
++ if (ret) {
++ dev_err(dev,
++ "usbmisc hsic_set_clk failed, ret=%d\n", ret);
++ return ret;
++ }
++ }
++
++ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++ data->in_lpm = true;
++
++ return 0;
++}
++
++static int imx_controller_resume(struct device *dev)
++{
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret = 0;
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (!data->in_lpm) {
++ WARN_ON(1);
++ return 0;
++ }
++
++ request_bus_freq(BUS_FREQ_HIGH);
++ ret = clk_prepare_enable(data->clk);
++ if (ret) {
++ release_bus_freq(BUS_FREQ_HIGH);
++ return ret;
++ }
++
++ data->in_lpm = false;
++
++ ret = imx_usbmisc_power_lost_check(data->usbmisc_data);
++ /* re-init if resume from power lost */
++ if (ret > 0) {
++ ret = imx_usbmisc_init(data->usbmisc_data);
++ if (ret) {
++ dev_err(dev, "usbmisc init failed, ret=%d\n", ret);
++ goto clk_disable;
++ }
++ }
++
++ ret = imx_usbmisc_set_wakeup(data->usbmisc_data, false);
++ if (ret) {
++ dev_err(dev, "usbmisc set_wakeup failed, ret=%d\n", ret);
++ goto clk_disable;
++ }
++
++ ret = imx_usbmisc_hsic_set_clk(data->usbmisc_data, true);
++ if (ret) {
++ dev_err(dev, "usbmisc hsic_set_clk failed, ret=%d\n", ret);
++ goto hsic_set_clk_fail;
++ }
++
++ return 0;
++
++hsic_set_clk_fail:
++ imx_usbmisc_set_wakeup(data->usbmisc_data, true);
++clk_disable:
++ clk_disable_unprepare(data->clk);
++ release_bus_freq(BUS_FREQ_HIGH);
++
++ return ret;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int ci_hdrc_imx_suspend(struct device *dev)
++{
++ int ret;
++
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++
++ if (data->in_lpm)
++ /* The core's suspend doesn't run */
++ return 0;
++
++ if (device_may_wakeup(dev)) {
++ ret = imx_usbmisc_set_wakeup(data->usbmisc_data, true);
++ if (ret) {
++ dev_err(dev, "usbmisc set_wakeup failed, ret=%d\n",
++ ret);
++ return ret;
++ }
++ }
++
++ return imx_controller_suspend(dev);
++}
++
++static int ci_hdrc_imx_resume(struct device *dev)
++{
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret;
++
++ ret = imx_controller_resume(dev);
++ if (!ret && data->supports_runtime_pm) {
++ pm_runtime_disable(dev);
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ }
++
++ return ret;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++#ifdef CONFIG_PM_RUNTIME
++static int ci_hdrc_imx_runtime_suspend(struct device *dev)
++{
++ struct ci_hdrc_imx_data *data = dev_get_drvdata(dev);
++ int ret;
++
++ if (data->in_lpm) {
++ WARN_ON(1);
++ return 0;
++ }
++
++ ret = imx_usbmisc_set_wakeup(data->usbmisc_data, true);
++ if (ret) {
++ dev_err(dev, "usbmisc set_wakeup failed, ret=%d\n", ret);
++ return ret;
++ }
++
++ return imx_controller_suspend(dev);
++}
++
++static int ci_hdrc_imx_runtime_resume(struct device *dev)
++{
++ return imx_controller_resume(dev);
++}
++#endif /* CONFIG_PM_RUNTIME */
++
++#endif /* CONFIG_PM */
++
++static const struct dev_pm_ops ci_hdrc_imx_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(ci_hdrc_imx_suspend, ci_hdrc_imx_resume)
++ SET_RUNTIME_PM_OPS(ci_hdrc_imx_runtime_suspend,
++ ci_hdrc_imx_runtime_resume, NULL)
++};
+ static struct platform_driver ci_hdrc_imx_driver = {
+ .probe = ci_hdrc_imx_probe,
+ .remove = ci_hdrc_imx_remove,
+@@ -206,6 +632,7 @@
+ .name = "imx_usb",
+ .owner = THIS_MODULE,
+ .of_match_table = ci_hdrc_imx_dt_ids,
++ .pm = &ci_hdrc_imx_pm_ops,
+ },
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_imx.h linux-3.14.72/drivers/usb/chipidea/ci_hdrc_imx.h
+--- linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_imx.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/ci_hdrc_imx.h 2016-06-19 22:11:55.321138957 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2015 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -12,14 +12,28 @@
+ #ifndef __DRIVER_USB_CHIPIDEA_CI_HDRC_IMX_H
+ #define __DRIVER_USB_CHIPIDEA_CI_HDRC_IMX_H
+
++#include <linux/usb/otg.h>
++
+ struct imx_usbmisc_data {
++ struct device *dev;
+ int index;
+
+ unsigned int disable_oc:1; /* over current detect disabled */
+ unsigned int evdo:1; /* set external vbus divider option */
++ /*
++ * Specifies the delay between powering up the xtal 24MHz clock
++ * and release the clock to the digital logic inside the analog block
++ */
++ unsigned int osc_clkgate_delay;
++ struct regmap *anatop;
++ enum usb_dr_mode available_role;
+ };
+
+ int imx_usbmisc_init(struct imx_usbmisc_data *);
+ int imx_usbmisc_init_post(struct imx_usbmisc_data *);
++int imx_usbmisc_set_wakeup(struct imx_usbmisc_data *, bool);
++int imx_usbmisc_power_lost_check(struct imx_usbmisc_data *);
++int imx_usbmisc_hsic_set_connect(struct imx_usbmisc_data *);
++int imx_usbmisc_hsic_set_clk(struct imx_usbmisc_data *, bool);
+
+ #endif /* __DRIVER_USB_CHIPIDEA_CI_HDRC_IMX_H */
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_msm.c linux-3.14.72/drivers/usb/chipidea/ci_hdrc_msm.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_msm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/ci_hdrc_msm.c 2016-06-19 22:11:55.325138694 +0200
+@@ -17,7 +17,7 @@
+
+ #define MSM_USB_BASE (ci->hw_bank.abs)
+
+-static void ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
++static int ci_hdrc_msm_notify_event(struct ci_hdrc *ci, unsigned event)
+ {
+ struct device *dev = ci->gadget.dev.parent;
+
+@@ -26,26 +26,28 @@
+ dev_dbg(dev, "CI_HDRC_CONTROLLER_RESET_EVENT received\n");
+ writel(0, USB_AHBBURST);
+ writel(0, USB_AHBMODE);
+- usb_phy_init(ci->transceiver);
++ usb_phy_init(ci->usb_phy);
+ break;
+ case CI_HDRC_CONTROLLER_STOPPED_EVENT:
+ dev_dbg(dev, "CI_HDRC_CONTROLLER_STOPPED_EVENT received\n");
+ /*
+- * Put the transceiver in non-driving mode. Otherwise host
++ * Put the phy in non-driving mode. Otherwise host
+ * may not detect soft-disconnection.
+ */
+- usb_phy_notify_disconnect(ci->transceiver, USB_SPEED_UNKNOWN);
++ usb_phy_notify_disconnect(ci->usb_phy, USB_SPEED_UNKNOWN);
+ break;
+ default:
+ dev_dbg(dev, "unknown ci_hdrc event\n");
+ break;
+ }
++
++ return 0;
+ }
+
+ static struct ci_hdrc_platform_data ci_hdrc_msm_platdata = {
+ .name = "ci_hdrc_msm",
++ .capoffset = DEF_CAPOFFSET,
+ .flags = CI_HDRC_REGS_SHARED |
+- CI_HDRC_REQUIRE_TRANSCEIVER |
+ CI_HDRC_DISABLE_STREAMING,
+
+ .notify_event = ci_hdrc_msm_notify_event,
+@@ -54,9 +56,21 @@
+ static int ci_hdrc_msm_probe(struct platform_device *pdev)
+ {
+ struct platform_device *plat_ci;
++ struct usb_phy *phy;
+
+ dev_dbg(&pdev->dev, "ci_hdrc_msm_probe\n");
+
++ /*
++ * OTG(PHY) driver takes care of PHY initialization, clock management,
++ * powering up VBUS, mapping of registers address space and power
++ * management.
++ */
++ phy = devm_usb_get_phy_by_phandle(&pdev->dev, "usb-phy", 0);
++ if (IS_ERR(phy))
++ return PTR_ERR(phy);
++
++ ci_hdrc_msm_platdata.usb_phy = phy;
++
+ plat_ci = ci_hdrc_add_device(&pdev->dev,
+ pdev->resource, pdev->num_resources,
+ &ci_hdrc_msm_platdata);
+@@ -83,10 +97,19 @@
+ return 0;
+ }
+
++static const struct of_device_id msm_ci_dt_match[] = {
++ { .compatible = "qcom,ci-hdrc", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, msm_ci_dt_match);
++
+ static struct platform_driver ci_hdrc_msm_driver = {
+ .probe = ci_hdrc_msm_probe,
+ .remove = ci_hdrc_msm_remove,
+- .driver = { .name = "msm_hsusb", },
++ .driver = {
++ .name = "msm_hsusb",
++ .of_match_table = msm_ci_dt_match,
++ },
+ };
+
+ module_platform_driver(ci_hdrc_msm_driver);
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_zevio.c linux-3.14.72/drivers/usb/chipidea/ci_hdrc_zevio.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/ci_hdrc_zevio.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/chipidea/ci_hdrc_zevio.c 2016-06-19 22:11:55.325138694 +0200
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2, as
++ * published by the Free Software Foundation.
++ *
++ * Based off drivers/usb/chipidea/ci_hdrc_msm.c
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/chipidea.h>
++
++#include "ci.h"
++
++static struct ci_hdrc_platform_data ci_hdrc_zevio_platdata = {
++ .name = "ci_hdrc_zevio",
++ .flags = CI_HDRC_REGS_SHARED,
++ .capoffset = DEF_CAPOFFSET,
++};
++
++static int ci_hdrc_zevio_probe(struct platform_device *pdev)
++{
++ struct platform_device *ci_pdev;
++
++ dev_dbg(&pdev->dev, "ci_hdrc_zevio_probe\n");
++
++ ci_pdev = ci_hdrc_add_device(&pdev->dev,
++ pdev->resource, pdev->num_resources,
++ &ci_hdrc_zevio_platdata);
++
++ if (IS_ERR(ci_pdev)) {
++ dev_err(&pdev->dev, "ci_hdrc_add_device failed!\n");
++ return PTR_ERR(ci_pdev);
++ }
++
++ platform_set_drvdata(pdev, ci_pdev);
++
++ return 0;
++}
++
++static int ci_hdrc_zevio_remove(struct platform_device *pdev)
++{
++ struct platform_device *ci_pdev = platform_get_drvdata(pdev);
++
++ ci_hdrc_remove_device(ci_pdev);
++
++ return 0;
++}
++
++static const struct of_device_id ci_hdrc_zevio_dt_ids[] = {
++ { .compatible = "lsi,zevio-usb", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver ci_hdrc_zevio_driver = {
++ .probe = ci_hdrc_zevio_probe,
++ .remove = ci_hdrc_zevio_remove,
++ .driver = {
++ .name = "zevio_usb",
++ .owner = THIS_MODULE,
++ .of_match_table = ci_hdrc_zevio_dt_ids,
++ },
++};
++
++MODULE_DEVICE_TABLE(of, ci_hdrc_zevio_dt_ids);
++module_platform_driver(ci_hdrc_zevio_driver);
++
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/core.c linux-3.14.72/drivers/usb/chipidea/core.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/core.c 2016-06-19 22:11:55.325138694 +0200
+@@ -23,7 +23,7 @@
+ * - BUS: bus glue code, bus abstraction layer
+ *
+ * Compile Options
+- * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
++ * - CONFIG_USB_CHIPIDEA_DEBUG: enable debug facilities
+ * - STALL_IN: non-empty bulk-in pipes cannot be halted
+ * if defined mass storage compliance succeeds but with warnings
+ * => case 4: Hi > Dn
+@@ -42,15 +42,12 @@
+ * - Not Supported: 15 & 16 (ISO)
+ *
+ * TODO List
+- * - OTG
+- * - Interrupt Traffic
+- * - GET_STATUS(device) - always reports 0
+- * - Gadget API (majority of optional features)
+ * - Suspend & Remote Wakeup
+ */
+ #include <linux/delay.h>
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
++#include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+ #include <linux/module.h>
+ #include <linux/idr.h>
+@@ -64,6 +61,7 @@
+ #include <linux/usb/otg.h>
+ #include <linux/usb/chipidea.h>
+ #include <linux/usb/of.h>
++#include <linux/of.h>
+ #include <linux/phy.h>
+ #include <linux/regulator/consumer.h>
+
+@@ -73,6 +71,7 @@
+ #include "host.h"
+ #include "debug.h"
+ #include "otg.h"
++#include "otg_fsm.h"
+
+ /* Controller register map */
+ static const u8 ci_regs_nolpm[] = {
+@@ -85,6 +84,7 @@
+ [OP_USBINTR] = 0x08U,
+ [OP_DEVICEADDR] = 0x14U,
+ [OP_ENDPTLISTADDR] = 0x18U,
++ [OP_BURSTSIZE] = 0x20U,
+ [OP_PORTSC] = 0x44U,
+ [OP_DEVLC] = 0x84U,
+ [OP_OTGSC] = 0x64U,
+@@ -107,6 +107,7 @@
+ [OP_USBINTR] = 0x08U,
+ [OP_DEVICEADDR] = 0x14U,
+ [OP_ENDPTLISTADDR] = 0x18U,
++ [OP_BURSTSIZE] = 0x20U,
+ [OP_PORTSC] = 0x44U,
+ [OP_DEVLC] = 0x84U,
+ [OP_OTGSC] = 0xC4U,
+@@ -138,6 +139,46 @@
+ return 0;
+ }
+
++static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
++{
++ int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
++ enum ci_revision rev = CI_REVISION_UNKNOWN;
++
++ if (ver == 0x2) {
++ rev = hw_read_id_reg(ci, ID_ID, REVISION)
++ >> __ffs(REVISION);
++ rev += CI_REVISION_20;
++ } else if (ver == 0x0) {
++ rev = CI_REVISION_1X;
++ }
++
++ return rev;
++}
++
++/**
++ * hw_read_intr_enable: returns interrupt enable register
++ *
++ * @ci: the controller
++ *
++ * This function returns register data
++ */
++u32 hw_read_intr_enable(struct ci_hdrc *ci)
++{
++ return hw_read(ci, OP_USBINTR, ~0);
++}
++
++/**
++ * hw_read_intr_status: returns interrupt status register
++ *
++ * @ci: the controller
++ *
++ * This function returns register data
++ */
++u32 hw_read_intr_status(struct ci_hdrc *ci)
++{
++ return hw_read(ci, OP_USBSTS, ~0);
++}
++
+ /**
+ * hw_port_test_set: writes port test mode (execute without interruption)
+ * @mode: new value
+@@ -158,6 +199,8 @@
+ /**
+ * hw_port_test_get: reads port test mode value
+ *
++ * @ci: the controller
++ *
+ * This function returns port test mode value
+ */
+ u8 hw_port_test_get(struct ci_hdrc *ci)
+@@ -165,25 +208,29 @@
+ return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
+ }
+
++static void hw_wait_phy_stable(void)
++{
++ /*
++ * The phy needs some delay to output the stable status from low
++ * power mode. And for OTGSC, the status inputs are debounced
++ * using a 1 ms time constant, so, delay 2ms for controller to get
++ * the stable status, like vbus and id when the phy leaves low power.
++ */
++ usleep_range(2000, 2500);
++}
++
+ /* The PHY enters/leaves low power mode */
+ static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
+ {
+ enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
+ bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
+
+- if (enable && !lpm) {
++ if (enable && !lpm)
+ hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
+ PORTSC_PHCD(ci->hw_bank.lpm));
+- } else if (!enable && lpm) {
++ else if (!enable && lpm)
+ hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
+ 0);
+- /*
+- * The controller needs at least 1ms to reflect
+- * PHY's status, the PHY also needs some time (less
+- * than 1ms) to leave low power mode.
+- */
+- usleep_range(1500, 2000);
+- }
+ }
+
+ static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
+@@ -222,8 +269,11 @@
+ /* Clear all interrupts status bits*/
+ hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
+
+- dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
+- ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
++ ci->rev = ci_get_revision(ci);
++
++ dev_dbg(ci->dev,
++ "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
++ ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
+
+ /* setup lock mode ? */
+
+@@ -276,36 +326,180 @@
+ }
+
+ /**
+- * hw_device_reset: resets chip (execute without interruption)
++ * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
++ * interfaces
++ * @ci: the controller
++ *
++ * This function returns an error code if the phy failed to init
++ */
++static int _ci_usb_phy_init(struct ci_hdrc *ci)
++{
++ int ret;
++
++ if (ci->phy) {
++ ret = phy_init(ci->phy);
++ if (ret)
++ return ret;
++
++ ret = phy_power_on(ci->phy);
++ if (ret) {
++ phy_exit(ci->phy);
++ return ret;
++ }
++ } else {
++ ret = usb_phy_init(ci->usb_phy);
++ }
++
++ return ret;
++}
++
++/**
++ * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
++ * interfaces
++ * @ci: the controller
++ */
++static void ci_usb_phy_exit(struct ci_hdrc *ci)
++{
++ if (ci->phy) {
++ phy_power_off(ci->phy);
++ phy_exit(ci->phy);
++ } else {
++ usb_phy_shutdown(ci->usb_phy);
++ }
++}
++
++/**
++ * ci_usb_phy_init: initialize phy according to different phy type
++ * @ci: the controller
++ *
++ * This function returns an error code if usb_phy_init has failed
++ */
++static int ci_usb_phy_init(struct ci_hdrc *ci)
++{
++ int ret;
++
++ switch (ci->platdata->phy_mode) {
++ case USBPHY_INTERFACE_MODE_UTMI:
++ case USBPHY_INTERFACE_MODE_UTMIW:
++ case USBPHY_INTERFACE_MODE_HSIC:
++ ret = _ci_usb_phy_init(ci);
++ if (!ret)
++ hw_wait_phy_stable();
++ else
++ return ret;
++ hw_phymode_configure(ci);
++ break;
++ case USBPHY_INTERFACE_MODE_ULPI:
++ case USBPHY_INTERFACE_MODE_SERIAL:
++ hw_phymode_configure(ci);
++ ret = _ci_usb_phy_init(ci);
++ if (ret)
++ return ret;
++ break;
++ default:
++ ret = _ci_usb_phy_init(ci);
++ if (!ret)
++ hw_wait_phy_stable();
++ }
++
++ return ret;
++}
++
++/**
++ * hw_controller_reset: do controller reset
+ * @ci: the controller
+ *
+ * This function returns an error code
+ */
+-int hw_device_reset(struct ci_hdrc *ci, u32 mode)
++int hw_controller_reset(struct ci_hdrc *ci)
++{
++ int count = 0;
++
++ hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
++ while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
++ udelay(10);
++ if (count++ > 1000)
++ return -ETIMEDOUT;
++ }
++
++ return 0;
++}
++
++/**
++ * ci_hrdc_ahb_config: override default AHB configuration
++ * @ci: the controller
++ */
++void ci_hdrc_ahb_config(struct ci_hdrc *ci)
++{
++ u32 value;
++ u8 ahb_burst;
++
++ /* AHB configuration */
++ if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST) {
++ value = ioread32(ci->hw_bank.abs + ID_SBUSCFG);
++ value &= ~SBUSCFG_AHBBRST;
++ value |= ci->platdata->ahbburst_config & SBUSCFG_AHBBRST;
++ iowrite32(value, ci->hw_bank.abs + ID_SBUSCFG);
++ }
++
++ ahb_burst = ioread32(ci->hw_bank.abs + ID_SBUSCFG) & SBUSCFG_AHBBRST;
++
++ /* Change RX/TX burst size */
++ if (ahb_burst == 0 &&
++ ci->platdata->flags & CI_HDRC_OVERRIDE_BURST_LENGTH)
++ hw_write(ci, OP_BURSTSIZE, BURST_BITS,
++ ci->platdata->burst_length & BURST_BITS);
++}
++
++/**
++ * hw_device_reset: resets chip (execute without interruption)
++ * @ci: the controller
++ *
++ * This function returns an error code
++ */
++int hw_device_reset(struct ci_hdrc *ci)
+ {
++ int ret;
++
+ /* should flush & stop before reset */
+ hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
+ hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
+
+- hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
+- while (hw_read(ci, OP_USBCMD, USBCMD_RST))
+- udelay(10); /* not RTOS friendly */
++ ret = hw_controller_reset(ci);
++ if (ret) {
++ dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
++ return ret;
++ }
+
+ if (ci->platdata->notify_event)
+ ci->platdata->notify_event(ci,
+ CI_HDRC_CONTROLLER_RESET_EVENT);
+
+- if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
++ if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
+ hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
+
++ if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
++ if (ci->hw_bank.lpm)
++ hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
++ else
++ hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
++ }
++
+ /* USBMODE should be configured step by step */
+ hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
+- hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
++ hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
+ /* HW >= 2.3 */
+ hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
+
+- if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
+- pr_err("cannot enter in %s mode", ci_role(ci)->name);
++ ci_hdrc_ahb_config(ci);
++ /*
++ * Set interrupt interval for device mode as 0 (immediately),
++ * ehci core will set it to 1 (1 Micro-frame) by default for host mode.
++ */
++ hw_write(ci, OP_USBCMD, 0xff0000, 0);
++
++ if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
++ pr_err("cannot enter in %s device mode", ci_role(ci)->name);
+ pr_err("lpm = %i", ci->hw_bank.lpm);
+ return -ENODEV;
+ }
+@@ -351,8 +545,21 @@
+ irqreturn_t ret = IRQ_NONE;
+ u32 otgsc = 0;
+
+- if (ci->is_otg)
+- otgsc = hw_read(ci, OP_OTGSC, ~0);
++ if (ci->in_lpm) {
++ disable_irq_nosync(irq);
++ ci->wakeup_int = true;
++ pm_runtime_get(ci->dev);
++ return IRQ_HANDLED;
++ }
++
++ if (ci->is_otg) {
++ otgsc = hw_read_otgsc(ci, ~0);
++ if (ci_otg_is_fsm_mode(ci)) {
++ ret = ci_otg_fsm_irq(ci);
++ if (ret == IRQ_HANDLED)
++ return ret;
++ }
++ }
+
+ /*
+ * Handle id change interrupt, it indicates device/host function
+@@ -360,9 +567,9 @@
+ */
+ if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
+ ci->id_event = true;
+- ci_clear_otg_interrupt(ci, OTGSC_IDIS);
+- disable_irq_nosync(ci->irq);
+- queue_work(ci->wq, &ci->work);
++ /* Clear ID change irq status */
++ hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
++ ci_otg_queue_work(ci);
+ return IRQ_HANDLED;
+ }
+
+@@ -371,10 +578,10 @@
+ * and disconnection events.
+ */
+ if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
+- ci->b_sess_valid_event = true;
+- ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
+- disable_irq_nosync(ci->irq);
+- queue_work(ci->wq, &ci->work);
++ ci->vbus_glitch_check_event = true;
++ /* Clear BSV irq */
++ hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
++ ci_otg_queue_work(ci);
+ return IRQ_HANDLED;
+ }
+
+@@ -403,15 +610,22 @@
+ if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
+ return -EPROBE_DEFER;
+ } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
+- /* no vbus regualator is needed */
++ /* no vbus regulator is needed */
+ platdata->reg_vbus = NULL;
+ } else if (IS_ERR(platdata->reg_vbus)) {
+ dev_err(dev, "Getting regulator error: %ld\n",
+ PTR_ERR(platdata->reg_vbus));
+ return PTR_ERR(platdata->reg_vbus);
+ }
++ /* Get TPL support */
++ if (!platdata->tpl_support)
++ platdata->tpl_support =
++ of_usb_host_tpl_support(dev->of_node);
+ }
+
++ if (of_usb_get_maximum_speed(dev->of_node) == USB_SPEED_FULL)
++ platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
++
+ return 0;
+ }
+
+@@ -473,6 +687,33 @@
+ }
+ EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
+
++/**
++ * ci_hdrc_query_available_role: get runtime available operation mode
++ *
++ * The glue layer can get current operation mode (host/peripheral/otg)
++ * This function should be called after ci core device has created.
++ *
++ * @pdev: the platform device of ci core.
++ *
++ * Return USB_DR_MODE_XXX.
++ */
++enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev)
++{
++ struct ci_hdrc *ci = platform_get_drvdata(pdev);
++
++ if (!ci)
++ return USB_DR_MODE_UNKNOWN;
++ if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])
++ return USB_DR_MODE_OTG;
++ else if (ci->roles[CI_ROLE_HOST])
++ return USB_DR_MODE_HOST;
++ else if (ci->roles[CI_ROLE_GADGET])
++ return USB_DR_MODE_PERIPHERAL;
++ else
++ return USB_DR_MODE_UNKNOWN;
++}
++EXPORT_SYMBOL_GPL(ci_hdrc_query_available_role);
++
+ static inline void ci_role_destroy(struct ci_hdrc *ci)
+ {
+ ci_hdrc_gadget_destroy(ci);
+@@ -491,36 +732,56 @@
+ == (DCCPARAMS_DC | DCCPARAMS_HC));
+ if (ci->is_otg) {
+ dev_dbg(ci->dev, "It is OTG capable controller\n");
+- ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
+- ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
++ /* Disable and clear all OTG irq */
++ hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
++ OTGSC_INT_STATUS_BITS);
+ }
+ }
+
+-static int ci_usb_phy_init(struct ci_hdrc *ci)
++static enum ci_role ci_get_role(struct ci_hdrc *ci)
+ {
+- if (ci->platdata->phy) {
+- ci->transceiver = ci->platdata->phy;
+- return usb_phy_init(ci->transceiver);
++ if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
++ if (ci->is_otg) {
++ hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
++ return ci_otg_role(ci);
++ } else {
++ /*
++ * If the controller is not OTG capable, but support
++ * role switch, the defalt role is gadget, and the
++ * user can switch it through debugfs.
++ */
++ return CI_ROLE_GADGET;
++ }
+ } else {
+- ci->global_phy = true;
+- ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+- if (IS_ERR(ci->transceiver))
+- ci->transceiver = NULL;
+-
+- return 0;
++ return ci->roles[CI_ROLE_HOST]
++ ? CI_ROLE_HOST
++ : CI_ROLE_GADGET;
+ }
+ }
+
+-static void ci_usb_phy_destroy(struct ci_hdrc *ci)
++static void ci_start_new_role(struct ci_hdrc *ci)
+ {
+- if (!ci->transceiver)
+- return;
++ enum ci_role role = ci_get_role(ci);
++
++ if (ci->role != role)
++ ci_handle_id_switch(ci);
++
++ if (role == CI_ROLE_GADGET)
++ ci_handle_vbus_connected(ci);
++}
++
++static void ci_power_lost_work(struct work_struct *work)
++{
++ struct ci_hdrc *ci = container_of(work, struct ci_hdrc,
++ power_lost_work);
+
+- otg_set_peripheral(ci->transceiver->otg, NULL);
+- if (ci->global_phy)
+- usb_put_phy(ci->transceiver);
++ pm_runtime_get_sync(ci->dev);
++ if (!ci_otg_is_fsm_mode(ci))
++ ci_start_new_role(ci);
+ else
+- usb_phy_shutdown(ci->transceiver);
++ ci_hdrc_otg_fsm_restart(ci);
++ pm_runtime_put_sync(ci->dev);
++ enable_irq(ci->irq);
+ }
+
+ static int ci_hdrc_probe(struct platform_device *pdev)
+@@ -532,7 +793,7 @@
+ int ret;
+ enum usb_dr_mode dr_mode;
+
+- if (!dev->platform_data) {
++ if (!dev_get_platdata(dev)) {
+ dev_err(dev, "platform data missing\n");
+ return -ENODEV;
+ }
+@@ -543,15 +804,15 @@
+ return PTR_ERR(base);
+
+ ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
+- if (!ci) {
+- dev_err(dev, "can't allocate device\n");
++ if (!ci)
+ return -ENOMEM;
+- }
+
+ ci->dev = dev;
+- ci->platdata = dev->platform_data;
++ ci->platdata = dev_get_platdata(dev);
+ ci->imx28_write_fix = !!(ci->platdata->flags &
+ CI_HDRC_IMX28_WRITE_FIX);
++ ci->supports_runtime_pm = !!(ci->platdata->flags &
++ CI_HDRC_SUPPORTS_RUNTIME_PM);
+
+ ret = hw_device_init(ci, base);
+ if (ret < 0) {
+@@ -559,7 +820,27 @@
+ return -ENODEV;
+ }
+
+- hw_phymode_configure(ci);
++ if (ci->platdata->phy) {
++ ci->phy = ci->platdata->phy;
++ } else if (ci->platdata->usb_phy) {
++ ci->usb_phy = ci->platdata->usb_phy;
++ } else {
++ ci->phy = devm_phy_get(dev->parent, "usb-phy");
++ ci->usb_phy = devm_usb_get_phy(dev->parent, USB_PHY_TYPE_USB2);
++
++ /* if both generic PHY and USB PHY layers aren't enabled */
++ if (PTR_ERR(ci->phy) == -ENOSYS &&
++ PTR_ERR(ci->usb_phy) == -ENXIO)
++ return -ENXIO;
++
++ if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy))
++ return -EPROBE_DEFER;
++
++ if (IS_ERR(ci->phy))
++ ci->phy = NULL;
++ else if (IS_ERR(ci->usb_phy))
++ ci->usb_phy = NULL;
++ }
+
+ ret = ci_usb_phy_init(ci);
+ if (ret) {
+@@ -572,8 +853,8 @@
+ ci->irq = platform_get_irq(pdev, 0);
+ if (ci->irq < 0) {
+ dev_err(dev, "missing IRQ\n");
+- ret = -ENODEV;
+- goto destroy_phy;
++ ret = ci->irq;
++ goto deinit_phy;
+ }
+
+ ci_get_otg_capable(ci);
+@@ -590,26 +871,15 @@
+ ret = ci_hdrc_gadget_init(ci);
+ if (ret)
+ dev_info(dev, "doesn't support gadget\n");
+- if (!ret && ci->transceiver) {
+- ret = otg_set_peripheral(ci->transceiver->otg,
+- &ci->gadget);
+- /*
+- * If we implement all USB functions using chipidea drivers,
+- * it doesn't need to call above API, meanwhile, if we only
+- * use gadget function, calling above API is useless.
+- */
+- if (ret && ret != -ENOTSUPP)
+- goto destroy_phy;
+- }
+ }
+
+ if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
+ dev_err(dev, "no supported roles\n");
+ ret = -ENODEV;
+- goto destroy_phy;
++ goto deinit_phy;
+ }
+
+- if (ci->is_otg) {
++ if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
+ ret = ci_hdrc_otg_init(ci);
+ if (ret) {
+ dev_err(dev, "init otg fails, ret = %d\n", ret);
+@@ -617,54 +887,50 @@
+ }
+ }
+
+- if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
+- if (ci->is_otg) {
+- /*
+- * ID pin needs 1ms debouce time,
+- * we delay 2ms for safe.
+- */
+- mdelay(2);
+- ci->role = ci_otg_role(ci);
+- ci_enable_otg_interrupt(ci, OTGSC_IDIE);
+- } else {
+- /*
+- * If the controller is not OTG capable, but support
+- * role switch, the defalt role is gadget, and the
+- * user can switch it through debugfs.
+- */
+- ci->role = CI_ROLE_GADGET;
+- }
+- } else {
+- ci->role = ci->roles[CI_ROLE_HOST]
+- ? CI_ROLE_HOST
+- : CI_ROLE_GADGET;
+- }
+-
++ ci->role = ci_get_role(ci);
+ /* only update vbus status for peripheral */
+ if (ci->role == CI_ROLE_GADGET)
+- ci_handle_vbus_change(ci);
++ ci_handle_vbus_connected(ci);
+
+- ret = ci_role_start(ci, ci->role);
+- if (ret) {
+- dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
+- goto stop;
++ if (!ci_otg_is_fsm_mode(ci)) {
++ ret = ci_role_start(ci, ci->role);
++ if (ret) {
++ dev_err(dev, "can't start %s role\n",
++ ci_role(ci)->name);
++ goto stop;
++ }
+ }
+
+ platform_set_drvdata(pdev, ci);
+- ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
+- ci);
++ ret = devm_request_irq(dev, ci->irq, ci_irq, IRQF_SHARED,
++ ci->platdata->name, ci);
+ if (ret)
+ goto stop;
+
++ if (ci->supports_runtime_pm) {
++ pm_runtime_set_active(&pdev->dev);
++ pm_runtime_enable(&pdev->dev);
++ pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
++ pm_runtime_mark_last_busy(ci->dev);
++ pm_runtime_use_autosuspend(&pdev->dev);
++ }
++
++ if (ci_otg_is_fsm_mode(ci))
++ ci_hdrc_otg_fsm_start(ci);
++
++ device_set_wakeup_capable(&pdev->dev, true);
++
++ /* Init workqueue for controller power lost handling */
++ INIT_WORK(&ci->power_lost_work, ci_power_lost_work);
++
+ ret = dbg_create_files(ci);
+ if (!ret)
+ return 0;
+
+- free_irq(ci->irq, ci);
+ stop:
+ ci_role_destroy(ci);
+-destroy_phy:
+- ci_usb_phy_destroy(ci);
++deinit_phy:
++ ci_usb_phy_exit(ci);
+
+ return ret;
+ }
+@@ -673,20 +939,213 @@
+ {
+ struct ci_hdrc *ci = platform_get_drvdata(pdev);
+
++ if (ci->supports_runtime_pm) {
++ pm_runtime_get_sync(&pdev->dev);
++ pm_runtime_disable(&pdev->dev);
++ pm_runtime_put_noidle(&pdev->dev);
++ }
++
+ dbg_remove_files(ci);
+- free_irq(ci->irq, ci);
+ ci_role_destroy(ci);
+ ci_hdrc_enter_lpm(ci, true);
+- ci_usb_phy_destroy(ci);
++ ci_usb_phy_exit(ci);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++/* Prepare wakeup by SRP before suspend */
++static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
++{
++ if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
++ !hw_read_otgsc(ci, OTGSC_ID)) {
++ hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
++ PORTSC_PP);
++ hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
++ PORTSC_WKCN);
++ }
++}
++
++/* Handle SRP when wakeup by data pulse */
++static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
++{
++ /*
++ * if a_idle wakeup by data pulse,
++ * handle it like normal SRP
++ */
++ if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
++ (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
++ if (!hw_read_otgsc(ci, OTGSC_ID))
++ otg_add_timer(&ci->fsm, A_DP_END);
++ else
++ ci->fsm.id = 1;
++ }
++}
++
++static void ci_controller_suspend(struct ci_hdrc *ci)
++{
++ disable_irq(ci->irq);
++ ci_hdrc_enter_lpm(ci, true);
++ usb_phy_set_suspend(ci->usb_phy, 1);
++ ci->in_lpm = true;
++ enable_irq(ci->irq);
++}
++
++static int ci_controller_resume(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (!ci->in_lpm) {
++ WARN_ON(1);
++ return 0;
++ }
++
++ ci_hdrc_enter_lpm(ci, false);
++ if (ci->usb_phy) {
++ usb_phy_set_suspend(ci->usb_phy, 0);
++ usb_phy_set_wakeup(ci->usb_phy, false);
++ hw_wait_phy_stable();
++ }
++
++ ci->in_lpm = false;
++ if (ci->wakeup_int) {
++ ci->wakeup_int = false;
++ pm_runtime_mark_last_busy(ci->dev);
++ pm_runtime_put_autosuspend(ci->dev);
++ enable_irq(ci->irq);
++ if (ci_otg_is_fsm_mode(ci))
++ ci_otg_fsm_wakeup_by_srp(ci);
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int ci_suspend(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ if (ci->wq)
++ flush_workqueue(ci->wq);
++ /*
++ * Controller needs to be active during suspend, otherwise the core
++ * may run resume when the parent is at suspend if other driver's
++ * suspend fails, it occurs before parent's suspend has not started,
++ * but the core suspend has finished.
++ */
++ if (ci->in_lpm)
++ pm_runtime_resume(dev);
++
++ if (ci->in_lpm) {
++ WARN_ON(1);
++ return 0;
++ }
++
++ /* Extra routine per role before system suspend */
++ if (ci->role != CI_ROLE_END && ci_role(ci)->suspend)
++ ci_role(ci)->suspend(ci);
++
++ if (device_may_wakeup(dev)) {
++ if (ci_otg_is_fsm_mode(ci))
++ ci_otg_fsm_suspend_for_srp(ci);
++ usb_phy_set_wakeup(ci->usb_phy, true);
++ enable_irq_wake(ci->irq);
++ }
++
++ ci_controller_suspend(ci);
+
+ return 0;
+ }
+
++static int ci_resume(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++ bool power_lost = false;
++ u32 sample_reg_val;
++ int ret;
++
++ /* Check if controller resume from power lost */
++ sample_reg_val = hw_read(ci, OP_ENDPTLISTADDR, ~0);
++ if (sample_reg_val == 0)
++ power_lost = true;
++ else if (sample_reg_val == 0xFFFFFFFF)
++ /* Restore value 0 if it was set for power lost check */
++ hw_write(ci, OP_ENDPTLISTADDR, ~0, 0);
++
++ if (device_may_wakeup(dev))
++ disable_irq_wake(ci->irq);
++
++ ret = ci_controller_resume(dev);
++ if (ret)
++ return ret;
++
++ if (power_lost) {
++ /* shutdown and re-init for phy */
++ ci_usb_phy_exit(ci);
++ ci_usb_phy_init(ci);
++ }
++
++ /* Extra routine per role after system resume */
++ if (ci->role != CI_ROLE_END && ci_role(ci)->resume)
++ ci_role(ci)->resume(ci, power_lost);
++
++ if (power_lost) {
++ disable_irq_nosync(ci->irq);
++ schedule_work(&ci->power_lost_work);
++ }
++
++ if (ci->supports_runtime_pm) {
++ pm_runtime_disable(dev);
++ pm_runtime_set_active(dev);
++ pm_runtime_enable(dev);
++ }
++
++ return ret;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++#ifdef CONFIG_PM_RUNTIME
++static int ci_runtime_suspend(struct device *dev)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ dev_dbg(dev, "at %s\n", __func__);
++
++ if (ci->in_lpm) {
++ WARN_ON(1);
++ return 0;
++ }
++
++ if (ci_otg_is_fsm_mode(ci))
++ ci_otg_fsm_suspend_for_srp(ci);
++
++ usb_phy_set_wakeup(ci->usb_phy, true);
++ ci_controller_suspend(ci);
++
++ return 0;
++}
++
++static int ci_runtime_resume(struct device *dev)
++{
++ return ci_controller_resume(dev);
++}
++#endif /* CONFIG_PM_RUNTIME */
++
++#endif /* CONFIG_PM */
++static const struct dev_pm_ops ci_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
++ SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
++};
++
+ static struct platform_driver ci_hdrc_driver = {
+ .probe = ci_hdrc_probe,
+ .remove = ci_hdrc_remove,
+ .driver = {
+ .name = "ci_hdrc",
++ .pm = &ci_pm_ops,
++ .owner = THIS_MODULE,
+ },
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/debug.c linux-3.14.72/drivers/usb/chipidea/debug.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/debug.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/debug.c 2016-06-19 22:11:55.325138694 +0200
+@@ -7,11 +7,15 @@
+ #include <linux/uaccess.h>
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
++#include <linux/usb/phy.h>
++#include <linux/usb/otg.h>
++#include <linux/usb/otg-fsm.h>
+
+ #include "ci.h"
+ #include "udc.h"
+ #include "bits.h"
+ #include "debug.h"
++#include "otg.h"
+
+ /**
+ * ci_device_show: prints information about device capabilities and status
+@@ -204,6 +208,80 @@
+ .release = single_release,
+ };
+
++static int ci_otg_show(struct seq_file *s, void *unused)
++{
++ struct ci_hdrc *ci = s->private;
++ struct otg_fsm *fsm;
++
++ if (!ci || !ci_otg_is_fsm_mode(ci))
++ return 0;
++
++ fsm = &ci->fsm;
++
++ /* ------ State ----- */
++ seq_printf(s, "OTG state: %s\n\n",
++ usb_otg_state_string(ci->otg.state));
++
++ /* ------ State Machine Variables ----- */
++ seq_printf(s, "a_bus_drop: %d\n", fsm->a_bus_drop);
++
++ seq_printf(s, "a_bus_req: %d\n", fsm->a_bus_req);
++
++ seq_printf(s, "a_srp_det: %d\n", fsm->a_srp_det);
++
++ seq_printf(s, "a_vbus_vld: %d\n", fsm->a_vbus_vld);
++
++ seq_printf(s, "b_conn: %d\n", fsm->b_conn);
++
++ seq_printf(s, "adp_change: %d\n", fsm->adp_change);
++
++ seq_printf(s, "power_up: %d\n", fsm->power_up);
++
++ seq_printf(s, "a_bus_resume: %d\n", fsm->a_bus_resume);
++
++ seq_printf(s, "a_bus_suspend: %d\n", fsm->a_bus_suspend);
++
++ seq_printf(s, "a_conn: %d\n", fsm->a_conn);
++
++ seq_printf(s, "b_bus_req: %d\n", fsm->b_bus_req);
++
++ seq_printf(s, "b_bus_suspend: %d\n", fsm->b_bus_suspend);
++
++ seq_printf(s, "b_se0_srp: %d\n", fsm->b_se0_srp);
++
++ seq_printf(s, "b_ssend_srp: %d\n", fsm->b_ssend_srp);
++
++ seq_printf(s, "b_sess_vld: %d\n", fsm->b_sess_vld);
++
++ seq_printf(s, "b_srp_done: %d\n", fsm->b_srp_done);
++
++ seq_printf(s, "drv_vbus: %d\n", fsm->drv_vbus);
++
++ seq_printf(s, "loc_conn: %d\n", fsm->loc_conn);
++
++ seq_printf(s, "loc_sof: %d\n", fsm->loc_sof);
++
++ seq_printf(s, "adp_prb: %d\n", fsm->adp_prb);
++
++ seq_printf(s, "id: %d\n", fsm->id);
++
++ seq_printf(s, "protocol: %d\n", fsm->protocol);
++
++ return 0;
++}
++
++static int ci_otg_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, ci_otg_show, inode->i_private);
++}
++
++static const struct file_operations ci_otg_fops = {
++ .open = ci_otg_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
+ static int ci_role_show(struct seq_file *s, void *data)
+ {
+ struct ci_hdrc *ci = s->private;
+@@ -253,6 +331,50 @@
+ .release = single_release,
+ };
+
++static int ci_registers_show(struct seq_file *s, void *unused)
++{
++ struct ci_hdrc *ci = s->private;
++ u32 tmp_reg;
++
++ if (!ci)
++ return 0;
++
++ /* ------ Registers ----- */
++ tmp_reg = hw_read_intr_enable(ci);
++ seq_printf(s, "USBINTR reg: %08x\n", tmp_reg);
++
++ tmp_reg = hw_read_intr_status(ci);
++ seq_printf(s, "USBSTS reg: %08x\n", tmp_reg);
++
++ tmp_reg = hw_read(ci, OP_USBMODE, ~0);
++ seq_printf(s, "USBMODE reg: %08x\n", tmp_reg);
++
++ tmp_reg = hw_read(ci, OP_USBCMD, ~0);
++ seq_printf(s, "USBCMD reg: %08x\n", tmp_reg);
++
++ tmp_reg = hw_read(ci, OP_PORTSC, ~0);
++ seq_printf(s, "PORTSC reg: %08x\n", tmp_reg);
++
++ if (ci->is_otg) {
++ tmp_reg = hw_read_otgsc(ci, ~0);
++ seq_printf(s, "OTGSC reg: %08x\n", tmp_reg);
++ }
++
++ return 0;
++}
++
++static int ci_registers_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, ci_registers_show, inode->i_private);
++}
++
++static const struct file_operations ci_registers_fops = {
++ .open = ci_registers_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
+ /**
+ * dbg_create_files: initializes the attribute interface
+ * @ci: device
+@@ -287,8 +409,21 @@
+ if (!dent)
+ goto err;
+
++ if (ci_otg_is_fsm_mode(ci)) {
++ dent = debugfs_create_file("otg", S_IRUGO, ci->debugfs, ci,
++ &ci_otg_fops);
++ if (!dent)
++ goto err;
++ }
++
+ dent = debugfs_create_file("role", S_IRUGO | S_IWUSR, ci->debugfs, ci,
+ &ci_role_fops);
++ if (!dent)
++ goto err;
++
++ dent = debugfs_create_file("registers", S_IRUGO, ci->debugfs, ci,
++ &ci_registers_fops);
++
+ if (dent)
+ return 0;
+ err:
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/host.c linux-3.14.72/drivers/usb/chipidea/host.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/host.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/host.c 2016-06-19 22:11:55.325138694 +0200
+@@ -25,6 +25,7 @@
+ #include <linux/usb/hcd.h>
+ #include <linux/usb/chipidea.h>
+ #include <linux/regulator/consumer.h>
++#include <linux/imx_gpc.h>
+
+ #include "../host/ehci.h"
+
+@@ -33,6 +34,182 @@
+ #include "host.h"
+
+ static struct hc_driver __read_mostly ci_ehci_hc_driver;
++static int (*orig_bus_suspend)(struct usb_hcd *hcd);
++static int (*orig_bus_resume)(struct usb_hcd *hcd);
++static int (*orig_hub_control)(struct usb_hcd *hcd,
++ u16 typeReq, u16 wValue, u16 wIndex,
++ char *buf, u16 wLength);
++
++struct ehci_ci_priv {
++ struct regulator *reg_vbus;
++};
++
++/* This function is used to override WKCN, WKDN, and WKOC */
++static void ci_ehci_override_wakeup_flag(struct ehci_hcd *ehci,
++ u32 __iomem *reg, u32 flags, bool set)
++{
++ u32 val = ehci_readl(ehci, reg);
++
++ if (set)
++ val |= flags;
++ else
++ val &= ~flags;
++
++ ehci_writel(ehci, val, reg);
++}
++
++static int ehci_ci_portpower(struct usb_hcd *hcd, int portnum, bool enable)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ struct ehci_ci_priv *priv = (struct ehci_ci_priv *)ehci->priv;
++ struct device *dev = hcd->self.controller;
++ int ret = 0;
++ int port = HCS_N_PORTS(ehci->hcs_params);
++
++ if (priv->reg_vbus) {
++ if (port > 1) {
++ dev_warn(dev,
++ "Not support multi-port regulator control\n");
++ return 0;
++ }
++ if (enable)
++ ret = regulator_enable(priv->reg_vbus);
++ else
++ ret = regulator_disable(priv->reg_vbus);
++ if (ret) {
++ dev_err(dev,
++ "Failed to %s vbus regulator, ret=%d\n",
++ enable ? "enable" : "disable", ret);
++ return ret;
++ }
++ }
++ return 0;
++};
++
++static const struct ehci_driver_overrides ehci_ci_overrides = {
++ .extra_priv_size = sizeof(struct ehci_ci_priv),
++ .port_power = ehci_ci_portpower,
++};
++
++static int ci_imx_ehci_bus_resume(struct usb_hcd *hcd)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ int port;
++
++ int ret = orig_bus_resume(hcd);
++
++ if (ret)
++ return ret;
++
++ port = HCS_N_PORTS(ehci->hcs_params);
++ while (port--) {
++ u32 __iomem *reg = &ehci->regs->port_status[port];
++ u32 portsc = ehci_readl(ehci, reg);
++ /*
++ * Notify PHY after resume signal has finished, it is
++ * for global suspend case.
++ */
++ if (hcd->usb_phy
++ && test_bit(port, &ehci->bus_suspended)
++ && (portsc & PORT_CONNECT)
++ && (ehci_port_speed(ehci, portsc) ==
++ USB_PORT_STAT_HIGH_SPEED))
++ /* notify the USB PHY */
++ usb_phy_notify_resume(hcd->usb_phy, USB_SPEED_HIGH);
++ }
++
++ return 0;
++}
++
++/* The below code is based on tegra ehci driver */
++static int ci_imx_ehci_hub_control(
++ struct usb_hcd *hcd,
++ u16 typeReq,
++ u16 wValue,
++ u16 wIndex,
++ char *buf,
++ u16 wLength
++)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ u32 __iomem *status_reg;
++ u32 temp;
++ unsigned long flags;
++ int retval = 0;
++ struct device *dev = hcd->self.controller;
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
++
++ spin_lock_irqsave(&ehci->lock, flags);
++
++ if (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_SUSPEND) {
++ temp = ehci_readl(ehci, status_reg);
++ if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) {
++ retval = -EPIPE;
++ goto done;
++ }
++
++ temp &= ~(PORT_RWC_BITS | PORT_WKCONN_E);
++ temp |= PORT_WKDISC_E | PORT_WKOC_E;
++ ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
++
++ /*
++ * If a transaction is in progress, there may be a delay in
++ * suspending the port. Poll until the port is suspended.
++ */
++ if (ehci_handshake(ehci, status_reg, PORT_SUSPEND,
++ PORT_SUSPEND, 5000))
++ ehci_err(ehci, "timeout waiting for SUSPEND\n");
++
++ if (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC) {
++ if (ci->platdata->notify_event)
++ ci->platdata->notify_event
++ (ci, CI_HDRC_IMX_HSIC_SUSPEND_EVENT);
++ ci_ehci_override_wakeup_flag(ehci, status_reg,
++ PORT_WKDISC_E | PORT_WKCONN_E, false);
++ }
++
++ spin_unlock_irqrestore(&ehci->lock, flags);
++ if (ehci_port_speed(ehci, temp) ==
++ USB_PORT_STAT_HIGH_SPEED && hcd->usb_phy) {
++ /* notify the USB PHY */
++ usb_phy_notify_suspend(hcd->usb_phy, USB_SPEED_HIGH);
++ }
++ spin_lock_irqsave(&ehci->lock, flags);
++
++ set_bit((wIndex & 0xff) - 1, &ehci->suspended_ports);
++ goto done;
++ }
++
++ /*
++ * After resume has finished, it needs do some post resume
++ * operation for some SoCs.
++ */
++ else if (typeReq == ClearPortFeature &&
++ wValue == USB_PORT_FEAT_C_SUSPEND) {
++
++ /* Make sure the resume has finished, it should be finished */
++ if (ehci_handshake(ehci, status_reg, PORT_RESUME, 0, 25000))
++ ehci_err(ehci, "timeout waiting for resume\n");
++
++ temp = ehci_readl(ehci, status_reg);
++
++ if (ehci_port_speed(ehci, temp) ==
++ USB_PORT_STAT_HIGH_SPEED && hcd->usb_phy) {
++ /* notify the USB PHY */
++ usb_phy_notify_resume(hcd->usb_phy, USB_SPEED_HIGH);
++ }
++ }
++
++ spin_unlock_irqrestore(&ehci->lock, flags);
++
++ /* Handle the hub control events here */
++ return orig_hub_control(hcd, typeReq, wValue, wIndex, buf, wLength);
++done:
++ spin_unlock_irqrestore(&ehci->lock, flags);
++ return retval;
++}
+
+ static irqreturn_t host_irq(struct ci_hdrc *ci)
+ {
+@@ -43,6 +220,7 @@
+ {
+ struct usb_hcd *hcd;
+ struct ehci_hcd *ehci;
++ struct ehci_ci_priv *priv;
+ int ret;
+
+ if (usb_disabled())
+@@ -59,7 +237,11 @@
+ hcd->has_tt = 1;
+
+ hcd->power_budget = ci->platdata->power_budget;
+- hcd->phy = ci->transceiver;
++ hcd->tpl_support = ci->platdata->tpl_support;
++ if (ci->phy)
++ hcd->phy = ci->phy;
++ else
++ hcd->usb_phy = ci->usb_phy;
+
+ ehci = hcd_to_ehci(hcd);
+ ehci->caps = ci->hw_bank.cap;
+@@ -67,31 +249,60 @@
+ ehci->has_tdi_phy_lpm = ci->hw_bank.lpm;
+ ehci->imx28_write_fix = ci->imx28_write_fix;
+
+- if (ci->platdata->reg_vbus) {
+- ret = regulator_enable(ci->platdata->reg_vbus);
+- if (ret) {
+- dev_err(ci->dev,
++ priv = (struct ehci_ci_priv *)ehci->priv;
++ priv->reg_vbus = NULL;
++
++ if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci)) {
++ if (ci->platdata->flags & CI_HDRC_IMX_VBUS_EARLY_ON) {
++ ret = regulator_enable(ci->platdata->reg_vbus);
++ if (ret) {
++ dev_err(ci->dev,
+ "Failed to enable vbus regulator, ret=%d\n",
+- ret);
+- goto put_hcd;
++ ret);
++ goto put_hcd;
++ }
++ } else {
++ priv->reg_vbus = ci->platdata->reg_vbus;
+ }
+ }
+
+ ret = usb_add_hcd(hcd, 0, 0);
+- if (ret)
++ if (ret) {
+ goto disable_reg;
+- else
++ } else {
++ struct usb_otg *otg = &ci->otg;
++
+ ci->hcd = hcd;
+
++ if (ci_otg_is_fsm_mode(ci)) {
++ hcd->self.otg_fsm = &ci->fsm;
++ otg->host = &hcd->self;
++ hcd->self.otg_port = 1;
++ }
++ }
++
+ if (ci->platdata->flags & CI_HDRC_DISABLE_STREAMING)
+ hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
+
++ if (ci->platdata->notify_event &&
++ (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC))
++ ci->platdata->notify_event
++ (ci, CI_HDRC_IMX_HSIC_ACTIVE_EVENT);
++
++ if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
++ hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
++
++ if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED)
++ hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
++
++ ci_hdrc_ahb_config(ci);
++
+ return ret;
+
+ disable_reg:
+- if (ci->platdata->reg_vbus)
++ if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
++ (ci->platdata->flags & CI_HDRC_IMX_VBUS_EARLY_ON))
+ regulator_disable(ci->platdata->reg_vbus);
+-
+ put_hcd:
+ usb_put_hcd(hcd);
+
+@@ -105,11 +316,102 @@
+ if (hcd) {
+ usb_remove_hcd(hcd);
+ usb_put_hcd(hcd);
+- if (ci->platdata->reg_vbus)
+- regulator_disable(ci->platdata->reg_vbus);
++ if (ci->platdata->reg_vbus && !ci_otg_is_fsm_mode(ci) &&
++ (ci->platdata->flags & CI_HDRC_IMX_VBUS_EARLY_ON))
++ regulator_disable(ci->platdata->reg_vbus);
+ }
++ ci->hcd = NULL;
+ }
+
++bool ci_hdrc_host_has_device(struct ci_hdrc *ci)
++{
++ struct usb_device *roothub;
++ int i;
++
++ if ((ci->role == CI_ROLE_HOST) && ci->hcd) {
++ roothub = ci->hcd->self.root_hub;
++ for (i = 0; i < roothub->maxchild; ++i) {
++ if (usb_hub_find_child(roothub, (i + 1)))
++ return true;
++ }
++ }
++ return false;
++}
++
++static void ci_hdrc_host_save_for_power_lost(struct ci_hdrc *ci)
++{
++ struct ehci_hcd *ehci;
++
++ if (!ci->hcd)
++ return;
++
++ ehci = hcd_to_ehci(ci->hcd);
++ /* save EHCI registers */
++ ci->pm_usbmode = ehci_readl(ehci, &ehci->regs->usbmode);
++ ci->pm_command = ehci_readl(ehci, &ehci->regs->command);
++ ci->pm_command &= ~CMD_RUN;
++ ci->pm_status = ehci_readl(ehci, &ehci->regs->status);
++ ci->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
++ ci->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
++ ci->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
++ ci->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
++ ci->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
++ ci->pm_configured_flag =
++ ehci_readl(ehci, &ehci->regs->configured_flag);
++ ci->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
++}
++
++static void ci_hdrc_host_restore_from_power_lost(struct ci_hdrc *ci)
++{
++ struct ehci_hcd *ehci;
++ unsigned long flags;
++ u32 tmp;
++
++ if (!ci->hcd)
++ return;
++
++ hw_controller_reset(ci);
++
++ ehci = hcd_to_ehci(ci->hcd);
++ spin_lock_irqsave(&ehci->lock, flags);
++ /* Restore EHCI registers */
++ ehci_writel(ehci, ci->pm_usbmode, &ehci->regs->usbmode);
++ ehci_writel(ehci, ci->pm_portsc, &ehci->regs->port_status[0]);
++ ehci_writel(ehci, ci->pm_command, &ehci->regs->command);
++ ehci_writel(ehci, ci->pm_intr_enable, &ehci->regs->intr_enable);
++ ehci_writel(ehci, ci->pm_frame_index, &ehci->regs->frame_index);
++ ehci_writel(ehci, ci->pm_segment, &ehci->regs->segment);
++ ehci_writel(ehci, ci->pm_frame_list, &ehci->regs->frame_list);
++ ehci_writel(ehci, ci->pm_async_next, &ehci->regs->async_next);
++ ehci_writel(ehci, ci->pm_configured_flag,
++ &ehci->regs->configured_flag);
++ /* Restore the PHY's connect notifier setting */
++ if (ci->pm_portsc & PORTSC_HSP)
++ usb_phy_notify_connect(ci->usb_phy, USB_SPEED_HIGH);
++
++ ci_hdrc_ahb_config(ci);
++
++ tmp = ehci_readl(ehci, &ehci->regs->command);
++ tmp |= CMD_RUN;
++ ehci_writel(ehci, tmp, &ehci->regs->command);
++ spin_unlock_irqrestore(&ehci->lock, flags);
++}
++
++static void ci_hdrc_host_suspend(struct ci_hdrc *ci)
++{
++ if (ci_hdrc_host_has_device(ci))
++ imx_gpc_mf_request_on(ci->irq, 1);
++
++ ci_hdrc_host_save_for_power_lost(ci);
++}
++
++static void ci_hdrc_host_resume(struct ci_hdrc *ci, bool power_lost)
++{
++ imx_gpc_mf_request_on(ci->irq, 0);
++
++ if (power_lost)
++ ci_hdrc_host_restore_from_power_lost(ci);
++}
+
+ void ci_hdrc_host_destroy(struct ci_hdrc *ci)
+ {
+@@ -117,6 +419,71 @@
+ host_stop(ci);
+ }
+
++static int ci_ehci_bus_suspend(struct usb_hcd *hcd)
++{
++ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
++ int port;
++ u32 tmp;
++ struct device *dev = hcd->self.controller;
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ int ret = orig_bus_suspend(hcd);
++
++ if (ret)
++ return ret;
++
++ port = HCS_N_PORTS(ehci->hcs_params);
++ while (port--) {
++ u32 __iomem *reg = &ehci->regs->port_status[port];
++ u32 portsc = ehci_readl(ehci, reg);
++
++ if (portsc & PORT_CONNECT) {
++ /*
++ * For chipidea, the resume signal will be ended
++ * automatically, so for remote wakeup case, the
++ * usbcmd.rs may not be set before the resume has
++ * ended if other resume paths consumes too much
++ * time (~24ms), in that case, the SOF will not
++ * send out within 3ms after resume ends, then the
++ * high speed device will enter full speed mode.
++ */
++
++ tmp = ehci_readl(ehci, &ehci->regs->command);
++ tmp |= CMD_RUN;
++ ehci_writel(ehci, tmp, &ehci->regs->command);
++ /*
++ * It needs a short delay between set RS bit and PHCD.
++ */
++ usleep_range(150, 200);
++
++ /*
++ * If a transaction is in progress, there may be a delay in
++ * suspending the port. Poll until the port is suspended.
++ */
++ if (ehci_handshake(ehci, reg, PORT_SUSPEND,
++ PORT_SUSPEND, 5000))
++ ehci_err(ehci, "timeout waiting for SUSPEND\n");
++
++ if (ci->platdata->flags & CI_HDRC_IMX_IS_HSIC)
++ ci_ehci_override_wakeup_flag(ehci, reg,
++ PORT_WKDISC_E | PORT_WKCONN_E, false);
++
++ if (hcd->usb_phy && test_bit(port, &ehci->bus_suspended)
++ && (ehci_port_speed(ehci, portsc) ==
++ USB_PORT_STAT_HIGH_SPEED))
++ /*
++ * notify the USB PHY, it is for global
++ * suspend case.
++ */
++ usb_phy_notify_suspend(hcd->usb_phy,
++ USB_SPEED_HIGH);
++ break;
++ }
++ }
++
++ return 0;
++}
++
+ int ci_hdrc_host_init(struct ci_hdrc *ci)
+ {
+ struct ci_role_driver *rdrv;
+@@ -131,10 +498,21 @@
+ rdrv->start = host_start;
+ rdrv->stop = host_stop;
+ rdrv->irq = host_irq;
++ rdrv->suspend = ci_hdrc_host_suspend;
++ rdrv->resume = ci_hdrc_host_resume;
+ rdrv->name = "host";
+ ci->roles[CI_ROLE_HOST] = rdrv;
+
+- ehci_init_driver(&ci_ehci_hc_driver, NULL);
++ ehci_init_driver(&ci_ehci_hc_driver, &ehci_ci_overrides);
++ orig_bus_suspend = ci_ehci_hc_driver.bus_suspend;
++ orig_bus_resume = ci_ehci_hc_driver.bus_resume;
++ orig_hub_control = ci_ehci_hc_driver.hub_control;
++
++ ci_ehci_hc_driver.bus_suspend = ci_ehci_bus_suspend;
++ if (ci->platdata->flags & CI_HDRC_IMX_EHCI_QUIRK) {
++ ci_ehci_hc_driver.bus_resume = ci_imx_ehci_bus_resume;
++ ci_ehci_hc_driver.hub_control = ci_imx_ehci_hub_control;
++ }
+
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/host.h linux-3.14.72/drivers/usb/chipidea/host.h
+--- linux-3.14.72.orig/drivers/usb/chipidea/host.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/host.h 2016-06-19 22:11:55.325138694 +0200
+@@ -5,6 +5,7 @@
+
+ int ci_hdrc_host_init(struct ci_hdrc *ci);
+ void ci_hdrc_host_destroy(struct ci_hdrc *ci);
++bool ci_hdrc_host_has_device(struct ci_hdrc *ci);
+
+ #else
+
+@@ -18,6 +19,11 @@
+
+ }
+
++static inline bool ci_hdrc_host_has_device(struct ci_hdrc *ci)
++{
++ return false;
++}
++
+ #endif
+
+ #endif /* __DRIVERS_USB_CHIPIDEA_HOST_H */
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/Makefile linux-3.14.72/drivers/usb/chipidea/Makefile
+--- linux-3.14.72.orig/drivers/usb/chipidea/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/Makefile 2016-06-19 22:11:55.325138694 +0200
+@@ -6,10 +6,12 @@
+ ci_hdrc-$(CONFIG_USB_CHIPIDEA_UDC) += udc.o
+ ci_hdrc-$(CONFIG_USB_CHIPIDEA_HOST) += host.o
+ ci_hdrc-$(CONFIG_USB_CHIPIDEA_DEBUG) += debug.o
++ci_hdrc-$(CONFIG_USB_OTG_FSM) += otg_fsm.o
+
+ # Glue/Bridge layers go here
+
+ obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_msm.o
++obj-$(CONFIG_USB_CHIPIDEA) += ci_hdrc_zevio.o
+
+ # PCI doesn't provide stubs, need to check
+ ifneq ($(CONFIG_PCI),)
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/otg.c linux-3.14.72/drivers/usb/chipidea/otg.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/otg.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/otg.c 2016-06-19 22:11:55.325138694 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * otg.c - ChipIdea USB IP core OTG driver
+ *
+- * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Peter Chen
+ *
+@@ -11,8 +11,8 @@
+ */
+
+ /*
+- * This file mainly handles otgsc register, it may include OTG operation
+- * in the future.
++ * This file mainly handles otgsc register, OTG fsm operations for HNP and SRP
++ * are also included.
+ */
+
+ #include <linux/usb/otg.h>
+@@ -22,6 +22,27 @@
+ #include "ci.h"
+ #include "bits.h"
+ #include "otg.h"
++#include "otg_fsm.h"
++#include "host.h"
++
++/**
++ * hw_read_otgsc returns otgsc register bits value.
++ * @mask: bitfield mask
++ */
++u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask)
++{
++ return hw_read(ci, OP_OTGSC, mask);
++}
++
++/**
++ * hw_write_otgsc updates target bits of OTGSC register.
++ * @mask: bitfield mask
++ * @data: to be written
++ */
++void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data)
++{
++ hw_write(ci, OP_OTGSC, mask | OTGSC_INT_STATUS_BITS, data);
++}
+
+ /**
+ * ci_otg_role - pick role based on ID pin state
+@@ -29,31 +50,65 @@
+ */
+ enum ci_role ci_otg_role(struct ci_hdrc *ci)
+ {
+- u32 sts = hw_read(ci, OP_OTGSC, ~0);
+- enum ci_role role = sts & OTGSC_ID
++ enum ci_role role = hw_read_otgsc(ci, OTGSC_ID)
+ ? CI_ROLE_GADGET
+ : CI_ROLE_HOST;
+
+ return role;
+ }
+
+-void ci_handle_vbus_change(struct ci_hdrc *ci)
++/*
++ * Handling vbus glitch
++ * We only need to consider glitch for without usb connection,
++ * With usb connection, we consider it as real disconnection.
++ *
++ * If the vbus can't be kept above B session valid for timeout value,
++ * we think it is a vbus glitch, otherwise it's a valid vbus.
++ */
++#define CI_VBUS_CONNECT_TIMEOUT_MS 300
++static int ci_is_vbus_glitch(struct ci_hdrc *ci)
+ {
+- u32 otgsc;
++ int i;
++ for (i = 0; i < CI_VBUS_CONNECT_TIMEOUT_MS/20; i++) {
++ if (hw_read_otgsc(ci, OTGSC_AVV)) {
++ return 0;
++ } else if (!hw_read_otgsc(ci, OTGSC_BSV)) {
++ dev_warn(ci->dev, "there is a vbus glitch\n");
++ return 1;
++ }
++ msleep(20);
++ }
++
++ return 0;
++}
+
++void ci_handle_vbus_connected(struct ci_hdrc *ci)
++{
++ /*
++ * TODO: if the platform does not supply 5v to udc, or use other way
++ * to supply 5v, it needs to use other conditions to call
++ * usb_gadget_vbus_connect.
++ */
+ if (!ci->is_otg)
+ return;
+
+- otgsc = hw_read(ci, OP_OTGSC, ~0);
++ if (hw_read_otgsc(ci, OTGSC_BSV) && !ci_is_vbus_glitch(ci))
++ usb_gadget_vbus_connect(&ci->gadget);
++}
++
++void ci_handle_vbus_change(struct ci_hdrc *ci)
++{
++ if (!ci->is_otg)
++ return;
+
+- if (otgsc & OTGSC_BSV)
++ if (hw_read_otgsc(ci, OTGSC_BSV))
+ usb_gadget_vbus_connect(&ci->gadget);
+ else
+ usb_gadget_vbus_disconnect(&ci->gadget);
+ }
+
+ #define CI_VBUS_STABLE_TIMEOUT_MS 5000
+-static void ci_handle_id_switch(struct ci_hdrc *ci)
++void ci_handle_id_switch(struct ci_hdrc *ci)
+ {
+ enum ci_role role = ci_otg_role(ci);
+
+@@ -61,6 +116,12 @@
+ dev_dbg(ci->dev, "switching from %s to %s\n",
+ ci_role(ci)->name, ci->roles[role]->name);
+
++ while (ci_hdrc_host_has_device(ci)) {
++ enable_irq(ci->irq);
++ usleep_range(10000, 15000);
++ disable_irq_nosync(ci->irq);
++ }
++
+ ci_role_stop(ci);
+ /* wait vbus lower than OTGSC_BSV */
+ hw_wait_reg(ci, OP_OTGSC, OTGSC_BSV, 0,
+@@ -68,6 +129,32 @@
+ ci_role_start(ci, role);
+ }
+ }
++
++static void ci_handle_vbus_glitch(struct ci_hdrc *ci)
++{
++ bool valid_vbus_change = false;
++
++ if (hw_read_otgsc(ci, OTGSC_BSV)) {
++ if (!ci_is_vbus_glitch(ci)) {
++ if (ci_otg_is_fsm_mode(ci)) {
++ ci->fsm.b_sess_vld = 1;
++ ci->fsm.b_ssend_srp = 0;
++ otg_del_timer(&ci->fsm, B_SSEND_SRP);
++ otg_del_timer(&ci->fsm, B_SRP_FAIL);
++ }
++ valid_vbus_change = true;
++ }
++ } else {
++ if (ci->vbus_active && !ci_otg_is_fsm_mode(ci))
++ valid_vbus_change = true;
++ }
++
++ if (valid_vbus_change) {
++ ci->b_sess_valid_event = true;
++ ci_otg_queue_work(ci);
++ }
++}
++
+ /**
+ * ci_otg_work - perform otg (vbus/id) event handle
+ * @work: work struct
+@@ -76,6 +163,21 @@
+ {
+ struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work);
+
++ if (ci->vbus_glitch_check_event) {
++ ci->vbus_glitch_check_event = false;
++ pm_runtime_get_sync(ci->dev);
++ ci_handle_vbus_glitch(ci);
++ pm_runtime_put_sync(ci->dev);
++ enable_irq(ci->irq);
++ return;
++ }
++
++ if (ci_otg_is_fsm_mode(ci) && !ci_otg_fsm_work(ci)) {
++ enable_irq(ci->irq);
++ return;
++ }
++
++ pm_runtime_get_sync(ci->dev);
+ if (ci->id_event) {
+ ci->id_event = false;
+ ci_handle_id_switch(ci);
+@@ -84,6 +186,7 @@
+ ci_handle_vbus_change(ci);
+ } else
+ dev_err(ci->dev, "unexpected event occurs at %s\n", __func__);
++ pm_runtime_put_sync(ci->dev);
+
+ enable_irq(ci->irq);
+ }
+@@ -102,6 +205,9 @@
+ return -ENODEV;
+ }
+
++ if (ci_otg_is_fsm_mode(ci))
++ return ci_hdrc_otg_fsm_init(ci);
++
+ return 0;
+ }
+
+@@ -115,6 +221,9 @@
+ flush_workqueue(ci->wq);
+ destroy_workqueue(ci->wq);
+ }
+- ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
+- ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
++ /* Disable all OTG irq and clear status */
++ hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
++ OTGSC_INT_STATUS_BITS);
++ if (ci_otg_is_fsm_mode(ci))
++ ci_hdrc_otg_fsm_remove(ci);
+ }
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/otg_fsm.c linux-3.14.72/drivers/usb/chipidea/otg_fsm.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/otg_fsm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/chipidea/otg_fsm.c 2016-06-19 22:11:55.325138694 +0200
+@@ -0,0 +1,937 @@
++/*
++ * otg_fsm.c - ChipIdea USB IP core OTG FSM driver
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Author: Jun Li
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/*
++ * This file mainly handles OTG fsm, it includes OTG fsm operations
++ * for HNP and SRP.
++ *
++ * TODO List
++ * - ADP
++ * - OTG test device
++ */
++
++#include <linux/usb/otg.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/hcd.h>
++#include <linux/usb/chipidea.h>
++#include <linux/regulator/consumer.h>
++
++#include "ci.h"
++#include "bits.h"
++#include "otg.h"
++#include "otg_fsm.h"
++#include "udc.h"
++#include "host.h"
++
++static struct ci_otg_fsm_timer *otg_timer_initializer
++(struct ci_hdrc *ci, void (*function)(void *, unsigned long),
++ unsigned long expires, unsigned long data)
++{
++ struct ci_otg_fsm_timer *timer;
++
++ timer = devm_kzalloc(ci->dev, sizeof(struct ci_otg_fsm_timer),
++ GFP_KERNEL);
++ if (!timer)
++ return NULL;
++ timer->function = function;
++ timer->expires = expires;
++ timer->data = data;
++ return timer;
++}
++
++/* Add for otg: interact with user space app */
++static ssize_t
++get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ char *next;
++ unsigned size, t;
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ next = buf;
++ size = PAGE_SIZE;
++ t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_req);
++ size -= t;
++ next += t;
++
++ return PAGE_SIZE - size;
++}
++
++static ssize_t
++set_a_bus_req(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ if (count > 2)
++ return -1;
++
++ mutex_lock(&ci->fsm.lock);
++ if (buf[0] == '0') {
++ ci->fsm.a_bus_req = 0;
++ } else if (buf[0] == '1') {
++ /* If a_bus_drop is TRUE, a_bus_req can't be set */
++ if (ci->fsm.a_bus_drop) {
++ mutex_unlock(&ci->fsm.lock);
++ return count;
++ }
++ ci->fsm.a_bus_req = 1;
++ if (ci->fsm.otg->state == OTG_STATE_A_PERIPHERAL) {
++ ci->gadget.host_request_flag = 1;
++ mutex_unlock(&ci->fsm.lock);
++ return count;
++ }
++ }
++
++ ci_otg_queue_work(ci);
++ mutex_unlock(&ci->fsm.lock);
++
++ return count;
++}
++static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req);
++
++static ssize_t
++get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ char *next;
++ unsigned size, t;
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ next = buf;
++ size = PAGE_SIZE;
++ t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_drop);
++ size -= t;
++ next += t;
++
++ return PAGE_SIZE - size;
++}
++
++static ssize_t
++set_a_bus_drop(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ if (count > 2)
++ return -1;
++
++ mutex_lock(&ci->fsm.lock);
++ if (buf[0] == '0') {
++ ci->fsm.a_bus_drop = 0;
++ } else if (buf[0] == '1') {
++ ci->fsm.a_bus_drop = 1;
++ ci->fsm.a_bus_req = 0;
++ }
++
++ ci_otg_queue_work(ci);
++ mutex_unlock(&ci->fsm.lock);
++
++ return count;
++}
++static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop,
++ set_a_bus_drop);
++
++static ssize_t
++get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
++{
++ char *next;
++ unsigned size, t;
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ next = buf;
++ size = PAGE_SIZE;
++ t = scnprintf(next, size, "%d\n", ci->fsm.b_bus_req);
++ size -= t;
++ next += t;
++
++ return PAGE_SIZE - size;
++}
++
++static ssize_t
++set_b_bus_req(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ if (count > 2)
++ return -1;
++
++ mutex_lock(&ci->fsm.lock);
++ if (buf[0] == '0')
++ ci->fsm.b_bus_req = 0;
++ else if (buf[0] == '1') {
++ ci->fsm.b_bus_req = 1;
++ if (ci->fsm.otg->state == OTG_STATE_B_PERIPHERAL) {
++ ci->gadget.host_request_flag = 1;
++ mutex_unlock(&ci->fsm.lock);
++ return count;
++ }
++ }
++
++ ci_otg_queue_work(ci);
++ mutex_unlock(&ci->fsm.lock);
++
++ return count;
++}
++static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req);
++
++static ssize_t
++set_a_clr_err(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct ci_hdrc *ci = dev_get_drvdata(dev);
++
++ if (count > 2)
++ return -1;
++
++ mutex_lock(&ci->fsm.lock);
++ if (buf[0] == '1')
++ ci->fsm.a_clr_err = 1;
++
++ ci_otg_queue_work(ci);
++ mutex_unlock(&ci->fsm.lock);
++
++ return count;
++}
++static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
++
++static struct attribute *inputs_attrs[] = {
++ &dev_attr_a_bus_req.attr,
++ &dev_attr_a_bus_drop.attr,
++ &dev_attr_b_bus_req.attr,
++ &dev_attr_a_clr_err.attr,
++ NULL,
++};
++
++static struct attribute_group inputs_attr_group = {
++ .name = "inputs",
++ .attrs = inputs_attrs,
++};
++
++/*
++ * Add timer to active timer list
++ */
++static void ci_otg_add_timer(struct ci_hdrc *ci, enum ci_otg_fsm_timer_index t)
++{
++ struct ci_otg_fsm_timer *tmp_timer;
++ struct ci_otg_fsm_timer *timer = ci->fsm_timer->timer_list[t];
++ struct list_head *active_timers = &ci->fsm_timer->active_timers;
++
++ if (t >= NUM_CI_OTG_FSM_TIMERS)
++ return;
++
++ /*
++ * Check if the timer is already in the active list,
++ * if so update timer count
++ */
++ list_for_each_entry(tmp_timer, active_timers, list)
++ if (tmp_timer == timer) {
++ timer->count = timer->expires;
++ return;
++ }
++
++ if (list_empty(active_timers))
++ pm_runtime_get(ci->dev);
++
++ timer->count = timer->expires;
++ list_add_tail(&timer->list, active_timers);
++
++ /* Enable 1ms irq */
++ if (!(hw_read_otgsc(ci, OTGSC_1MSIE)))
++ hw_write_otgsc(ci, OTGSC_1MSIE, OTGSC_1MSIE);
++}
++
++/*
++ * Remove timer from active timer list
++ */
++static void ci_otg_del_timer(struct ci_hdrc *ci, enum ci_otg_fsm_timer_index t)
++{
++ struct ci_otg_fsm_timer *tmp_timer, *del_tmp;
++ struct ci_otg_fsm_timer *timer = ci->fsm_timer->timer_list[t];
++ struct list_head *active_timers = &ci->fsm_timer->active_timers;
++ int flag = 0;
++
++ if (t >= NUM_CI_OTG_FSM_TIMERS)
++ return;
++
++ list_for_each_entry_safe(tmp_timer, del_tmp, active_timers, list)
++ if (tmp_timer == timer) {
++ list_del(&timer->list);
++ flag = 1;
++ }
++
++ /* Disable 1ms irq if there is no any active timer */
++ if (list_empty(active_timers) && (flag == 1)) {
++ hw_write_otgsc(ci, OTGSC_1MSIE, 0);
++ pm_runtime_put(ci->dev);
++ }
++}
++
++/*
++ * Reduce timer count by 1, and find timeout conditions.
++ * Called by otg 1ms timer interrupt
++ */
++static inline int ci_otg_tick_timer(struct ci_hdrc *ci)
++{
++ struct ci_otg_fsm_timer *tmp_timer, *del_tmp;
++ struct list_head *active_timers = &ci->fsm_timer->active_timers;
++ int expired = 0;
++
++ list_for_each_entry_safe(tmp_timer, del_tmp, active_timers, list) {
++ tmp_timer->count--;
++ /* check if timer expires */
++ if (!tmp_timer->count) {
++ list_del(&tmp_timer->list);
++ tmp_timer->function(ci, tmp_timer->data);
++ expired = 1;
++ }
++ }
++
++ /* disable 1ms irq if there is no any timer active */
++ if ((expired == 1) && list_empty(active_timers)) {
++ hw_write_otgsc(ci, OTGSC_1MSIE, 0);
++ pm_runtime_put(ci->dev);
++ }
++
++ return expired;
++}
++
++/* The timeout callback function to set time out bit */
++static void set_tmout(void *ptr, unsigned long indicator)
++{
++ *(int *)indicator = 1;
++}
++
++static void set_tmout_and_fsm(void *ptr, unsigned long indicator)
++{
++ struct ci_hdrc *ci = (struct ci_hdrc *)ptr;
++
++ set_tmout(ci, indicator);
++
++ ci_otg_queue_work(ci);
++}
++
++static void a_wait_vfall_tmout_func(void *ptr, unsigned long indicator)
++{
++ struct ci_hdrc *ci = (struct ci_hdrc *)ptr;
++
++ set_tmout(ci, indicator);
++ /* Disable port power */
++ hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP, 0);
++ /* Clear existing DP irq */
++ hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
++ /* Enable data pulse irq */
++ hw_write_otgsc(ci, OTGSC_DPIE, OTGSC_DPIE);
++ ci_otg_queue_work(ci);
++}
++
++static void b_ssend_srp_tmout_func(void *ptr, unsigned long indicator)
++{
++ struct ci_hdrc *ci = (struct ci_hdrc *)ptr;
++
++ set_tmout(ci, indicator);
++
++ /* only vbus fall below B_sess_vld in b_idle state */
++ if (ci->fsm.otg->state == OTG_STATE_B_IDLE)
++ ci_otg_queue_work(ci);
++}
++
++static void b_data_pulse_end(void *ptr, unsigned long indicator)
++{
++ struct ci_hdrc *ci = (struct ci_hdrc *)ptr;
++
++ ci->fsm.b_srp_done = 1;
++ ci->fsm.b_bus_req = 0;
++ if (ci->fsm.power_up)
++ ci->fsm.power_up = 0;
++
++ hw_write_otgsc(ci, OTGSC_HABA, 0);
++
++ ci_otg_queue_work(ci);
++}
++
++/*
++ * Timer for A-device to turn on Vbus
++ * after detecting data pulse from B-device
++ */
++static void a_wait_dp_end_tmout_func(void *ptr, unsigned long indicator)
++{
++ struct ci_hdrc *ci = (struct ci_hdrc *)ptr;
++
++ ci->fsm.a_bus_drop = 0;
++ ci->fsm.a_srp_det = 1;
++ ci_otg_queue_work(ci);
++}
++
++static void hnp_polling_timer_work(unsigned long arg)
++{
++ struct ci_hdrc *ci = (struct ci_hdrc *)arg;
++
++ schedule_work(&ci->hnp_polling_work);
++}
++
++static void ci_hnp_polling_work(struct work_struct *work)
++{
++ struct ci_hdrc *ci = container_of(work, struct ci_hdrc,
++ hnp_polling_work);
++
++ pm_runtime_get_sync(ci->dev);
++ if (otg_hnp_polling(&ci->fsm) == HOST_REQUEST_FLAG)
++ ci_otg_queue_work(ci);
++ pm_runtime_put_sync(ci->dev);
++}
++
++/* Initialize timers */
++static int ci_otg_init_timers(struct ci_hdrc *ci)
++{
++ struct otg_fsm *fsm = &ci->fsm;
++
++ /* FSM used timers */
++ ci->fsm_timer->timer_list[A_WAIT_VRISE] =
++ otg_timer_initializer(ci, &set_tmout_and_fsm, TA_WAIT_VRISE,
++ (unsigned long)&fsm->a_wait_vrise_tmout);
++ if (ci->fsm_timer->timer_list[A_WAIT_VRISE] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[A_WAIT_VFALL] =
++ otg_timer_initializer(ci, &a_wait_vfall_tmout_func,
++ TA_WAIT_VFALL, (unsigned long)&fsm->a_wait_vfall_tmout);
++ if (ci->fsm_timer->timer_list[A_WAIT_VFALL] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[A_WAIT_BCON] =
++ otg_timer_initializer(ci, &set_tmout_and_fsm, TA_WAIT_BCON,
++ (unsigned long)&fsm->a_wait_bcon_tmout);
++ if (ci->fsm_timer->timer_list[A_WAIT_BCON] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[A_AIDL_BDIS] =
++ otg_timer_initializer(ci, &set_tmout_and_fsm, TA_AIDL_BDIS,
++ (unsigned long)&fsm->a_aidl_bdis_tmout);
++ if (ci->fsm_timer->timer_list[A_AIDL_BDIS] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[A_BIDL_ADIS] =
++ otg_timer_initializer(ci, &set_tmout_and_fsm, TA_BIDL_ADIS,
++ (unsigned long)&fsm->a_bidl_adis_tmout);
++ if (ci->fsm_timer->timer_list[A_BIDL_ADIS] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[B_ASE0_BRST] =
++ otg_timer_initializer(ci, &set_tmout_and_fsm, TB_ASE0_BRST,
++ (unsigned long)&fsm->b_ase0_brst_tmout);
++ if (ci->fsm_timer->timer_list[B_ASE0_BRST] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[B_SE0_SRP] =
++ otg_timer_initializer(ci, &set_tmout_and_fsm, TB_SE0_SRP,
++ (unsigned long)&fsm->b_se0_srp);
++ if (ci->fsm_timer->timer_list[B_SE0_SRP] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[B_SSEND_SRP] =
++ otg_timer_initializer(ci, &b_ssend_srp_tmout_func, TB_SSEND_SRP,
++ (unsigned long)&fsm->b_ssend_srp);
++ if (ci->fsm_timer->timer_list[B_SSEND_SRP] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[B_SRP_FAIL] =
++ otg_timer_initializer(ci, &set_tmout, TB_SRP_FAIL,
++ (unsigned long)&fsm->b_srp_done);
++ if (ci->fsm_timer->timer_list[B_SRP_FAIL] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[B_DATA_PLS] =
++ otg_timer_initializer(ci, &b_data_pulse_end, TB_DATA_PLS, 0);
++ if (ci->fsm_timer->timer_list[B_DATA_PLS] == NULL)
++ return -ENOMEM;
++
++ ci->fsm_timer->timer_list[A_DP_END] = otg_timer_initializer(ci,
++ &a_wait_dp_end_tmout_func, TA_DP_END, 0);
++ if (ci->fsm_timer->timer_list[A_DP_END] == NULL)
++ return -ENOMEM;
++
++ setup_timer(&ci->hnp_polling_timer, hnp_polling_timer_work,
++ (unsigned long)ci);
++ return 0;
++}
++
++static void ci_otg_add_hnp_polling_timer(struct ci_hdrc *ci)
++{
++ mod_timer(&ci->hnp_polling_timer,
++ jiffies + msecs_to_jiffies(T_HOST_REQ_POLL));
++}
++
++/* -------------------------------------------------------------*/
++/* Operations that will be called from OTG Finite State Machine */
++/* -------------------------------------------------------------*/
++static void ci_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
++{
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++
++ if (t < NUM_OTG_FSM_TIMERS) {
++ if (t == HNP_POLLING)
++ ci_otg_add_hnp_polling_timer(ci);
++ else
++ ci_otg_add_timer(ci, t);
++ }
++ return;
++}
++
++static void ci_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
++{
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++
++ if (t < NUM_OTG_FSM_TIMERS)
++ ci_otg_del_timer(ci, t);
++ return;
++}
++
++/*
++ * A-device drive vbus: turn on vbus regulator and enable port power
++ * Data pulse irq should be disabled while vbus is on.
++ */
++static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on)
++{
++ int ret;
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++
++ if (on) {
++ /* Enable power power */
++ hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
++ PORTSC_PP);
++ if (ci->platdata->reg_vbus) {
++ ret = regulator_enable(ci->platdata->reg_vbus);
++ if (ret) {
++ dev_err(ci->dev,
++ "Failed to enable vbus regulator, ret=%d\n",
++ ret);
++ return;
++ }
++ }
++ /* Disable data pulse irq */
++ hw_write_otgsc(ci, OTGSC_DPIE, 0);
++
++ fsm->a_srp_det = 0;
++ fsm->power_up = 0;
++ } else {
++ if (ci->platdata->reg_vbus)
++ regulator_disable(ci->platdata->reg_vbus);
++
++ fsm->a_bus_drop = 1;
++ fsm->a_bus_req = 0;
++ }
++}
++
++/*
++ * Control data line by Run Stop bit.
++ */
++static void ci_otg_loc_conn(struct otg_fsm *fsm, int on)
++{
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++
++ if (on)
++ hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
++ else
++ hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
++}
++
++/*
++ * Generate SOF by host.
++ * This is controlled through suspend/resume the port.
++ * In host mode, controller will automatically send SOF.
++ * Suspend will block the data on the port.
++ */
++static void ci_otg_loc_sof(struct otg_fsm *fsm, int on)
++{
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++
++ if (on)
++ hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_FPR,
++ PORTSC_FPR);
++ else
++ hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_SUSP,
++ PORTSC_SUSP);
++}
++
++/*
++ * Start SRP pulsing by data-line pulsing,
++ * no v-bus pulsing followed
++ */
++static void ci_otg_start_pulse(struct otg_fsm *fsm)
++{
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++
++ /* Hardware Assistant Data pulse */
++ hw_write_otgsc(ci, OTGSC_HADP, OTGSC_HADP);
++
++ ci_otg_add_timer(ci, B_DATA_PLS);
++}
++
++static int ci_otg_start_host(struct otg_fsm *fsm, int on)
++{
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++
++ mutex_unlock(&fsm->lock);
++ if (on) {
++ ci_role_stop(ci);
++ ci_role_start(ci, CI_ROLE_HOST);
++ } else {
++ ci_role_stop(ci);
++ hw_device_reset(ci);
++ ci_role_start(ci, CI_ROLE_GADGET);
++ }
++ mutex_lock(&fsm->lock);
++ return 0;
++}
++
++static int ci_otg_start_gadget(struct otg_fsm *fsm, int on)
++{
++ struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
++ unsigned long flags;
++ int gadget_ready = 0;
++
++ mutex_unlock(&fsm->lock);
++ spin_lock_irqsave(&ci->lock, flags);
++ ci->vbus_active = on;
++ if (ci->driver)
++ gadget_ready = 1;
++ spin_unlock_irqrestore(&ci->lock, flags);
++ if (gadget_ready)
++ ci_hdrc_gadget_connect(&ci->gadget, on);
++ mutex_lock(&fsm->lock);
++
++ return 0;
++}
++
++static struct otg_fsm_ops ci_otg_ops = {
++ .drv_vbus = ci_otg_drv_vbus,
++ .loc_conn = ci_otg_loc_conn,
++ .loc_sof = ci_otg_loc_sof,
++ .start_pulse = ci_otg_start_pulse,
++ .add_timer = ci_otg_fsm_add_timer,
++ .del_timer = ci_otg_fsm_del_timer,
++ .start_host = ci_otg_start_host,
++ .start_gadget = ci_otg_start_gadget,
++};
++
++int ci_otg_fsm_work(struct ci_hdrc *ci)
++{
++ if (ci->fsm.id && ci->fsm.otg->state < OTG_STATE_A_IDLE) {
++ unsigned long flags;
++
++ /* Charger detection */
++ spin_lock_irqsave(&ci->lock, flags);
++ if (ci->b_sess_valid_event) {
++ ci->b_sess_valid_event = false;
++ ci->vbus_active = ci->fsm.b_sess_vld;
++ spin_unlock_irqrestore(&ci->lock, flags);
++ ci_usb_charger_connect(ci, ci->fsm.b_sess_vld);
++ spin_lock_irqsave(&ci->lock, flags);
++ }
++ spin_unlock_irqrestore(&ci->lock, flags);
++ /*
++ * Don't do fsm transition for B device if gadget
++ * driver is not binded.
++ */
++ if (!ci->driver)
++ return 0;
++ }
++
++ pm_runtime_get_sync(ci->dev);
++ if (otg_statemachine(&ci->fsm)) {
++ if (ci->fsm.otg->state == OTG_STATE_A_IDLE) {
++ /*
++ * Further state change for cases:
++ * a_idle to b_idle; or
++ * a_idle to a_wait_vrise due to ID change(1->0), so
++ * B-dev becomes A-dev can try to start new session
++ * consequently; or
++ * a_idle to a_wait_vrise when power up
++ */
++ if ((ci->fsm.id) || (ci->id_event) ||
++ (ci->fsm.power_up))
++ ci_otg_queue_work(ci);
++ if (ci->id_event)
++ ci->id_event = false;
++ } else if (ci->fsm.otg->state == OTG_STATE_B_IDLE) {
++ if (ci->fsm.b_sess_vld) {
++ ci->fsm.power_up = 0;
++ /*
++ * Further transite to b_periphearl state
++ * when register gadget driver with vbus on
++ */
++ ci_otg_queue_work(ci);
++ }
++ } else if (ci->fsm.otg->state == OTG_STATE_A_HOST) {
++ pm_runtime_mark_last_busy(ci->dev);
++ pm_runtime_put_autosuspend(ci->dev);
++ return 0;
++ }
++ }
++ pm_runtime_put_sync(ci->dev);
++ return 0;
++}
++
++/*
++ * Update fsm variables in each state if catching expected interrupts,
++ * called by otg fsm isr.
++ */
++static void ci_otg_fsm_event(struct ci_hdrc *ci)
++{
++ u32 intr_sts, otg_bsess_vld, port_conn;
++ struct otg_fsm *fsm = &ci->fsm;
++
++ intr_sts = hw_read_intr_status(ci);
++ otg_bsess_vld = hw_read_otgsc(ci, OTGSC_BSV);
++ port_conn = hw_read(ci, OP_PORTSC, PORTSC_CCS);
++
++ switch (ci->fsm.otg->state) {
++ case OTG_STATE_A_WAIT_BCON:
++ if (port_conn) {
++ fsm->b_conn = 1;
++ fsm->a_bus_req = 1;
++ ci_otg_queue_work(ci);
++ }
++ break;
++ case OTG_STATE_B_IDLE:
++ if (otg_bsess_vld && (intr_sts & USBi_PCI) && port_conn) {
++ fsm->b_sess_vld = 1;
++ ci_otg_queue_work(ci);
++ }
++ break;
++ case OTG_STATE_B_PERIPHERAL:
++ if ((intr_sts & USBi_SLI) && port_conn && otg_bsess_vld) {
++ fsm->a_bus_suspend = 1;
++ ci_otg_queue_work(ci);
++ } else if (intr_sts & USBi_PCI) {
++ if (fsm->a_bus_suspend == 1)
++ fsm->a_bus_suspend = 0;
++ }
++ break;
++ case OTG_STATE_B_HOST:
++ if ((intr_sts & USBi_PCI) && !port_conn) {
++ fsm->a_conn = 0;
++ fsm->b_bus_req = 0;
++ ci_otg_queue_work(ci);
++ }
++ break;
++ case OTG_STATE_A_PERIPHERAL:
++ if (intr_sts & USBi_SLI) {
++ fsm->b_bus_suspend = 1;
++ /*
++ * Init a timer to know how long this suspend
++ * will continue, if time out, indicates B no longer
++ * wants to be host role
++ */
++ ci_otg_add_timer(ci, A_BIDL_ADIS);
++ }
++
++ if (intr_sts & USBi_URI)
++ ci_otg_del_timer(ci, A_BIDL_ADIS);
++
++ if (intr_sts & USBi_PCI) {
++ if (fsm->b_bus_suspend == 1) {
++ ci_otg_del_timer(ci, A_BIDL_ADIS);
++ fsm->b_bus_suspend = 0;
++ }
++ }
++ break;
++ case OTG_STATE_A_SUSPEND:
++ if ((intr_sts & USBi_PCI) && !port_conn) {
++ fsm->b_conn = 0;
++
++ /* if gadget driver is binded */
++ if (ci->driver) {
++ /* A device to be peripheral mode */
++ ci->gadget.is_a_peripheral = 1;
++ }
++ ci_otg_queue_work(ci);
++ }
++ break;
++ case OTG_STATE_A_HOST:
++ if ((intr_sts & USBi_PCI) && !port_conn) {
++ fsm->b_conn = 0;
++ ci_otg_queue_work(ci);
++ }
++ break;
++ case OTG_STATE_B_WAIT_ACON:
++ if ((intr_sts & USBi_PCI) && port_conn) {
++ fsm->a_conn = 1;
++ ci_otg_queue_work(ci);
++ }
++ break;
++ default:
++ break;
++ }
++}
++
++/*
++ * ci_otg_irq - otg fsm related irq handling
++ * and also update otg fsm variable by monitoring usb host and udc
++ * state change interrupts.
++ * @ci: ci_hdrc
++ */
++irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci)
++{
++ irqreturn_t retval = IRQ_NONE;
++ u32 otgsc, otg_int_src = 0;
++ struct otg_fsm *fsm = &ci->fsm;
++
++ otgsc = hw_read_otgsc(ci, ~0);
++ otg_int_src = otgsc & OTGSC_INT_STATUS_BITS & (otgsc >> 8);
++ fsm->id = (otgsc & OTGSC_ID) ? 1 : 0;
++
++ if (otg_int_src) {
++ if (otg_int_src & OTGSC_1MSIS) {
++ hw_write_otgsc(ci, OTGSC_1MSIS, OTGSC_1MSIS);
++ retval = ci_otg_tick_timer(ci);
++ return IRQ_HANDLED;
++ } else if (otg_int_src & OTGSC_DPIS) {
++ hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
++ ci_otg_add_timer(ci, A_DP_END);
++ } else if (otg_int_src & OTGSC_IDIS) {
++ hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
++ if (fsm->id == 0) {
++ fsm->a_bus_drop = 0;
++ fsm->a_bus_req = 1;
++ ci->id_event = true;
++ }
++ } else if (otg_int_src & OTGSC_BSVIS) {
++ hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
++ if (!(otgsc & OTGSC_BSV) && fsm->b_sess_vld) {
++ ci->b_sess_valid_event = true;
++ fsm->b_sess_vld = 0;
++ if (fsm->id)
++ ci_otg_add_timer(ci, B_SSEND_SRP);
++ if (fsm->b_bus_req)
++ fsm->b_bus_req = 0;
++ } else {
++ ci->vbus_glitch_check_event = true;
++ }
++ } else if (otg_int_src & OTGSC_AVVIS) {
++ hw_write_otgsc(ci, OTGSC_AVVIS, OTGSC_AVVIS);
++ if (otgsc & OTGSC_AVV) {
++ fsm->a_vbus_vld = 1;
++ } else {
++ fsm->a_vbus_vld = 0;
++ fsm->b_conn = 0;
++ }
++ }
++ ci_otg_queue_work(ci);
++ return IRQ_HANDLED;
++ }
++
++ ci_otg_fsm_event(ci);
++
++ return retval;
++}
++
++void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci)
++{
++ ci_otg_queue_work(ci);
++}
++
++int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci)
++{
++ int retval = 0;
++
++ if (ci->phy)
++ ci->otg.phy = ci->phy;
++ else
++ ci->otg.usb_phy = ci->usb_phy;
++
++ ci->otg.gadget = &ci->gadget;
++ ci->fsm.otg = &ci->otg;
++ ci->fsm.power_up = 1;
++ ci->fsm.id = hw_read_otgsc(ci, OTGSC_ID) ? 1 : 0;
++ ci->fsm.otg->state = OTG_STATE_UNDEFINED;
++ ci->fsm.ops = &ci_otg_ops;
++
++ mutex_init(&ci->fsm.lock);
++
++ ci->fsm_timer = devm_kzalloc(ci->dev,
++ sizeof(struct ci_otg_fsm_timer_list), GFP_KERNEL);
++ if (!ci->fsm_timer)
++ return -ENOMEM;
++
++ INIT_LIST_HEAD(&ci->fsm_timer->active_timers);
++ retval = ci_otg_init_timers(ci);
++ if (retval) {
++ dev_err(ci->dev, "Couldn't init OTG timers\n");
++ return retval;
++ }
++
++ retval = sysfs_create_group(&ci->dev->kobj, &inputs_attr_group);
++ if (retval < 0) {
++ dev_dbg(ci->dev,
++ "Can't register sysfs attr group: %d\n", retval);
++ return retval;
++ }
++
++ INIT_WORK(&ci->hnp_polling_work, ci_hnp_polling_work);
++
++ /* Enable A vbus valid irq */
++ hw_write_otgsc(ci, OTGSC_AVVIE, OTGSC_AVVIE);
++
++ if (ci->fsm.id) {
++ ci->fsm.b_ssend_srp =
++ hw_read_otgsc(ci, OTGSC_BSV) ? 0 : 1;
++ ci->fsm.b_sess_vld =
++ hw_read_otgsc(ci, OTGSC_BSV) ? 1 : 0;
++ /* Enable BSV irq */
++ hw_write_otgsc(ci, OTGSC_BSVIE, OTGSC_BSVIE);
++ }
++
++ return 0;
++}
++
++void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci)
++{
++ sysfs_remove_group(&ci->dev->kobj, &inputs_attr_group);
++ del_timer_sync(&ci->hnp_polling_timer);
++}
++
++/* Restart OTG fsm if resume from power lost */
++void ci_hdrc_otg_fsm_restart(struct ci_hdrc *ci)
++{
++ struct otg_fsm *fsm = &ci->fsm;
++ int id_status = fsm->id;
++
++ /* Update fsm if power lost in peripheral state */
++ if (ci->fsm.otg->state == OTG_STATE_B_PERIPHERAL) {
++ fsm->b_sess_vld = 0;
++ otg_statemachine(fsm);
++ }
++
++ hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
++ hw_write_otgsc(ci, OTGSC_AVVIE, OTGSC_AVVIE);
++
++ /* Update fsm variables for restart */
++ fsm->id = hw_read_otgsc(ci, OTGSC_ID) ? 1 : 0;
++ if (fsm->id) {
++ fsm->b_ssend_srp =
++ hw_read_otgsc(ci, OTGSC_BSV) ? 0 : 1;
++ fsm->b_sess_vld =
++ hw_read_otgsc(ci, OTGSC_BSV) ? 1 : 0;
++ } else if (fsm->id != id_status) {
++ /* ID changes to be 0 */
++ fsm->a_bus_drop = 0;
++ fsm->a_bus_req = 1;
++ ci->id_event = true;
++ }
++
++ if (ci_hdrc_host_has_device(ci) &&
++ !hw_read(ci, OP_PORTSC, PORTSC_CCS))
++ fsm->b_conn = 0;
++
++ ci_otg_fsm_work(ci);
++}
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/otg_fsm.h linux-3.14.72/drivers/usb/chipidea/otg_fsm.h
+--- linux-3.14.72.orig/drivers/usb/chipidea/otg_fsm.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/chipidea/otg_fsm.h 2016-06-19 22:11:55.325138694 +0200
+@@ -0,0 +1,135 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Author: Jun Li
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __DRIVERS_USB_CHIPIDEA_OTG_FSM_H
++#define __DRIVERS_USB_CHIPIDEA_OTG_FSM_H
++
++#include <linux/usb/otg-fsm.h>
++
++/*
++ * A-DEVICE timing constants
++ */
++
++/* Wait for VBUS Rise */
++#define TA_WAIT_VRISE (100) /* a_wait_vrise: section 7.1.2
++ * a_wait_vrise_tmr: section 7.4.5.1
++ * TA_VBUS_RISE <= 100ms, section 4.4
++ * Table 4-1: Electrical Characteristics
++ * ->DC Electrical Timing
++ */
++/* Wait for VBUS Fall */
++#define TA_WAIT_VFALL (1000) /* a_wait_vfall: section 7.1.7
++ * a_wait_vfall_tmr: section: 7.4.5.2
++ */
++/* Wait for B-Connect */
++#define TA_WAIT_BCON (10000) /* a_wait_bcon: section 7.1.3
++ * TA_WAIT_BCON: should be between 1100
++ * and 30000 ms, section 5.5, Table 5-1
++ */
++/* A-Idle to B-Disconnect */
++#define TA_AIDL_BDIS (5000) /* a_suspend min 200 ms, section 5.2.1
++ * TA_AIDL_BDIS: section 5.5, Table 5-1
++ */
++/* B-Idle to A-Disconnect */
++#define TA_BIDL_ADIS (500) /* TA_BIDL_ADIS: section 5.2.1
++ * 500ms is used for B switch to host
++ * for safe
++ */
++
++#define TA_DP_END (200)
++/*
++ * B-device timing constants
++ */
++
++/* Data-Line Pulse Time*/
++#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms
++ * section:5.1.3
++ */
++/* SRP Fail Time */
++#define TB_SRP_FAIL (6000) /* b_srp_init,fail time 5~6s
++ * section:5.1.6
++ */
++/* A-SE0 to B-Reset */
++#define TB_ASE0_BRST (155) /* minimum 155 ms, section:5.3.1 */
++/* SE0 Time Before SRP */
++#define TB_SE0_SRP (1000) /* b_idle,minimum 1s, section:5.1.2 */
++/* SSEND time before SRP */
++#define TB_SSEND_SRP (1500) /* minimum 1.5 sec, section:5.1.2 */
++
++#define T_HOST_REQ_POLL (1500) /* HNP polling interval 1s~2s */
++
++enum ci_otg_fsm_timer_index {
++ /*
++ * CI specific timers, start from the end
++ * of standard and auxiliary OTG timers
++ */
++ B_DATA_PLS = NUM_OTG_FSM_TIMERS,
++ B_SSEND_SRP,
++
++ NUM_CI_OTG_FSM_TIMERS,
++};
++
++struct ci_otg_fsm_timer {
++ unsigned long expires; /* Number of count increase to timeout */
++ unsigned long count; /* Tick counter */
++ void (*function)(void *, unsigned long); /* Timeout function */
++ unsigned long data; /* Data passed to function */
++ struct list_head list;
++};
++
++struct ci_otg_fsm_timer_list {
++ struct ci_otg_fsm_timer *timer_list[NUM_CI_OTG_FSM_TIMERS];
++ struct list_head active_timers;
++};
++
++#ifdef CONFIG_USB_OTG_FSM
++
++int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci);
++int ci_otg_fsm_work(struct ci_hdrc *ci);
++irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci);
++void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci);
++void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci);
++void ci_hdrc_otg_fsm_restart(struct ci_hdrc *ci);
++
++#else
++
++static inline int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci)
++{
++ return 0;
++}
++
++static inline int ci_otg_fsm_work(struct ci_hdrc *ci)
++{
++ return -ENXIO;
++}
++
++static inline irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci)
++{
++ return IRQ_NONE;
++}
++
++static inline void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci)
++{
++
++}
++
++static inline void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci)
++{
++
++}
++
++static inline void ci_hdrc_otg_fsm_restart(struct ci_hdrc *ci)
++{
++
++}
++
++#endif
++
++#endif /* __DRIVERS_USB_CHIPIDEA_OTG_FSM_H */
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/otg.h linux-3.14.72/drivers/usb/chipidea/otg.h
+--- linux-3.14.72.orig/drivers/usb/chipidea/otg.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/otg.h 2016-06-19 22:11:55.325138694 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * Author: Peter Chen
+ *
+@@ -11,25 +11,18 @@
+ #ifndef __DRIVERS_USB_CHIPIDEA_OTG_H
+ #define __DRIVERS_USB_CHIPIDEA_OTG_H
+
+-static inline void ci_clear_otg_interrupt(struct ci_hdrc *ci, u32 bits)
+-{
+- /* Only clear request bits */
+- hw_write(ci, OP_OTGSC, OTGSC_INT_STATUS_BITS, bits);
+-}
+-
+-static inline void ci_enable_otg_interrupt(struct ci_hdrc *ci, u32 bits)
+-{
+- hw_write(ci, OP_OTGSC, bits | OTGSC_INT_STATUS_BITS, bits);
+-}
+-
+-static inline void ci_disable_otg_interrupt(struct ci_hdrc *ci, u32 bits)
+-{
+- hw_write(ci, OP_OTGSC, bits | OTGSC_INT_STATUS_BITS, 0);
+-}
+-
++u32 hw_read_otgsc(struct ci_hdrc *ci, u32 mask);
++void hw_write_otgsc(struct ci_hdrc *ci, u32 mask, u32 data);
+ int ci_hdrc_otg_init(struct ci_hdrc *ci);
+ void ci_hdrc_otg_destroy(struct ci_hdrc *ci);
+ enum ci_role ci_otg_role(struct ci_hdrc *ci);
+ void ci_handle_vbus_change(struct ci_hdrc *ci);
++void ci_handle_id_switch(struct ci_hdrc *ci);
++void ci_handle_vbus_connected(struct ci_hdrc *ci);
++static inline void ci_otg_queue_work(struct ci_hdrc *ci)
++{
++ disable_irq_nosync(ci->irq);
++ queue_work(ci->wq, &ci->work);
++}
+
+ #endif /* __DRIVERS_USB_CHIPIDEA_OTG_H */
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/udc.c linux-3.14.72/drivers/usb/chipidea/udc.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/udc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/udc.c 2016-06-19 22:11:55.325138694 +0200
+@@ -20,6 +20,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/usb/ch9.h>
+ #include <linux/usb/gadget.h>
++#include <linux/usb/otg-fsm.h>
+ #include <linux/usb/chipidea.h>
+
+ #include "ci.h"
+@@ -27,6 +28,7 @@
+ #include "bits.h"
+ #include "debug.h"
+ #include "otg.h"
++#include "otg_fsm.h"
+
+ /* control endpoint description */
+ static const struct usb_endpoint_descriptor
+@@ -178,19 +180,6 @@
+ }
+
+ /**
+- * hw_test_and_clear_setup_status: test & clear setup status (execute without
+- * interruption)
+- * @n: endpoint number
+- *
+- * This function returns setup status
+- */
+-static int hw_test_and_clear_setup_status(struct ci_hdrc *ci, int n)
+-{
+- n = ep_to_bit(ci, n);
+- return hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(n));
+-}
+-
+-/**
+ * hw_ep_prime: primes endpoint (execute without interruption)
+ * @num: endpoint number
+ * @dir: endpoint direction
+@@ -255,26 +244,6 @@
+ }
+
+ /**
+- * hw_read_intr_enable: returns interrupt enable register
+- *
+- * This function returns register data
+- */
+-static u32 hw_read_intr_enable(struct ci_hdrc *ci)
+-{
+- return hw_read(ci, OP_USBINTR, ~0);
+-}
+-
+-/**
+- * hw_read_intr_status: returns interrupt status register
+- *
+- * This function returns register data
+- */
+-static u32 hw_read_intr_status(struct ci_hdrc *ci)
+-{
+- return hw_read(ci, OP_USBSTS, ~0);
+-}
+-
+-/**
+ * hw_test_and_clear_complete: test & clear complete status (execute without
+ * interruption)
+ * @n: endpoint number
+@@ -553,6 +522,20 @@
+ kfree(pending);
+ }
+
++static int reprime_dtd(struct ci_hdrc *ci, struct ci_hw_ep *hwep,
++ struct td_node *node)
++{
++ hwep->qh.ptr->td.next = node->dma;
++ hwep->qh.ptr->td.token &=
++ cpu_to_le32(~(TD_STATUS_HALTED | TD_STATUS_ACTIVE));
++
++ /* Synchronize before ep prime */
++ wmb();
++
++ return hw_ep_prime(ci, hwep->num, hwep->dir,
++ hwep->type == USB_ENDPOINT_XFER_CONTROL);
++}
++
+ /**
+ * _hardware_dequeue: handles a request at hardware level
+ * @gadget: gadget
+@@ -566,6 +549,7 @@
+ struct td_node *node, *tmpnode;
+ unsigned remaining_length;
+ unsigned actual = hwreq->req.length;
++ struct ci_hdrc *ci = hwep->ci;
+
+ if (hwreq->req.status != -EALREADY)
+ return -EINVAL;
+@@ -575,6 +559,11 @@
+ list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
+ tmptoken = le32_to_cpu(node->ptr->token);
+ if ((TD_STATUS_ACTIVE & tmptoken) != 0) {
++ int n = hw_ep_bit(hwep->num, hwep->dir);
++
++ if (ci->rev == CI_REVISION_24)
++ if (!hw_read(ci, OP_ENDPTSTAT, BIT(n)))
++ reprime_dtd(ci, hwep, node);
+ hwreq->req.status = -EALREADY;
+ return -EBUSY;
+ }
+@@ -681,12 +670,6 @@
+ struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
+ unsigned long flags;
+
+- spin_lock_irqsave(&ci->lock, flags);
+- ci->gadget.speed = USB_SPEED_UNKNOWN;
+- ci->remote_wakeup = 0;
+- ci->suspended = 0;
+- spin_unlock_irqrestore(&ci->lock, flags);
+-
+ /* flush all endpoints */
+ gadget_for_each_ep(ep, gadget) {
+ usb_ep_fifo_flush(ep);
+@@ -704,6 +687,12 @@
+ ci->status = NULL;
+ }
+
++ spin_lock_irqsave(&ci->lock, flags);
++ ci->gadget.speed = USB_SPEED_UNKNOWN;
++ ci->remote_wakeup = 0;
++ ci->suspended = 0;
++ spin_unlock_irqrestore(&ci->lock, flags);
++
+ return 0;
+ }
+
+@@ -740,6 +729,8 @@
+ if (ci->status == NULL)
+ retval = -ENOMEM;
+
++ usb_gadget_set_state(&ci->gadget, USB_STATE_DEFAULT);
++
+ done:
+ spin_lock(&ci->lock);
+
+@@ -844,7 +835,10 @@
+ return -ENOMEM;
+
+ req->complete = isr_get_status_complete;
+- req->length = 2;
++ if (setup->wIndex == OTG_STS_SELECTOR)
++ req->length = 1;
++ else
++ req->length = 2;
+ req->buf = kzalloc(req->length, gfp_flags);
+ if (req->buf == NULL) {
+ retval = -ENOMEM;
+@@ -852,9 +846,16 @@
+ }
+
+ if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
+- /* Assume that device is bus powered for now. */
+- *(u16 *)req->buf = ci->remote_wakeup << 1;
+- retval = 0;
++ if ((setup->wIndex == OTG_STS_SELECTOR) &&
++ ci_otg_is_fsm_mode(ci)) {
++ if (ci->gadget.host_request_flag)
++ *(u8 *)req->buf = HOST_REQUEST_FLAG;
++ else
++ *(u8 *)req->buf = 0;
++ } else {
++ /* Assume that device is bus powered for now. */
++ *(u16 *)req->buf = ci->remote_wakeup << 1;
++ }
+ } else if ((setup->bRequestType & USB_RECIP_MASK) \
+ == USB_RECIP_ENDPOINT) {
+ dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
+@@ -896,6 +897,8 @@
+ if (ci->setaddr) {
+ hw_usb_set_address(ci, ci->address);
+ ci->setaddr = false;
++ if (ci->address)
++ usb_gadget_set_state(&ci->gadget, USB_STATE_ADDRESS);
+ }
+
+ spin_lock_irqsave(&ci->lock, flags);
+@@ -962,6 +965,165 @@
+ }
+
+ /**
++ * isr_setup_packet_handler: setup packet handler
++ * @ci: UDC descriptor
++ *
++ * This function handles setup packet
++ */
++static void isr_setup_packet_handler(struct ci_hdrc *ci)
++__releases(ci->lock)
++__acquires(ci->lock)
++{
++ struct ci_hw_ep *hwep = &ci->ci_hw_ep[0];
++ struct usb_ctrlrequest req;
++ int type, num, dir, err = -EINVAL;
++ u8 tmode = 0;
++
++ /*
++ * Flush data and handshake transactions of previous
++ * setup packet.
++ */
++ _ep_nuke(ci->ep0out);
++ _ep_nuke(ci->ep0in);
++
++ /* read_setup_packet */
++ do {
++ hw_test_and_set_setup_guard(ci);
++ memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
++ } while (!hw_test_and_clear_setup_guard(ci));
++
++ type = req.bRequestType;
++
++ ci->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
++
++ switch (req.bRequest) {
++ case USB_REQ_CLEAR_FEATURE:
++ if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
++ le16_to_cpu(req.wValue) ==
++ USB_ENDPOINT_HALT) {
++ if (req.wLength != 0)
++ break;
++ num = le16_to_cpu(req.wIndex);
++ dir = num & USB_ENDPOINT_DIR_MASK;
++ num &= USB_ENDPOINT_NUMBER_MASK;
++ if (dir) /* TX */
++ num += ci->hw_ep_max / 2;
++ if (!ci->ci_hw_ep[num].wedge) {
++ spin_unlock(&ci->lock);
++ err = usb_ep_clear_halt(
++ &ci->ci_hw_ep[num].ep);
++ spin_lock(&ci->lock);
++ if (err)
++ break;
++ }
++ err = isr_setup_status_phase(ci);
++ } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
++ le16_to_cpu(req.wValue) ==
++ USB_DEVICE_REMOTE_WAKEUP) {
++ if (req.wLength != 0)
++ break;
++ ci->remote_wakeup = 0;
++ err = isr_setup_status_phase(ci);
++ } else {
++ goto delegate;
++ }
++ break;
++ case USB_REQ_GET_STATUS:
++ if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
++ type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
++ type != (USB_DIR_IN|USB_RECIP_INTERFACE))
++ goto delegate;
++ if ((le16_to_cpu(req.wLength) != 2 &&
++ le16_to_cpu(req.wLength) != 1) ||
++ le16_to_cpu(req.wValue) != 0)
++ break;
++ err = isr_get_status_response(ci, &req);
++ break;
++ case USB_REQ_SET_ADDRESS:
++ if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
++ goto delegate;
++ if (le16_to_cpu(req.wLength) != 0 ||
++ le16_to_cpu(req.wIndex) != 0)
++ break;
++ ci->address = (u8)le16_to_cpu(req.wValue);
++ ci->setaddr = true;
++ err = isr_setup_status_phase(ci);
++ break;
++ case USB_REQ_SET_FEATURE:
++ if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
++ le16_to_cpu(req.wValue) ==
++ USB_ENDPOINT_HALT) {
++ if (req.wLength != 0)
++ break;
++ num = le16_to_cpu(req.wIndex);
++ dir = num & USB_ENDPOINT_DIR_MASK;
++ num &= USB_ENDPOINT_NUMBER_MASK;
++ if (dir) /* TX */
++ num += ci->hw_ep_max / 2;
++
++ spin_unlock(&ci->lock);
++ err = usb_ep_set_halt(&ci->ci_hw_ep[num].ep);
++ spin_lock(&ci->lock);
++ if (!err)
++ isr_setup_status_phase(ci);
++ } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
++ if (req.wLength != 0)
++ break;
++ switch (le16_to_cpu(req.wValue)) {
++ case USB_DEVICE_REMOTE_WAKEUP:
++ ci->remote_wakeup = 1;
++ err = isr_setup_status_phase(ci);
++ break;
++ case USB_DEVICE_TEST_MODE:
++ tmode = le16_to_cpu(req.wIndex) >> 8;
++ switch (tmode) {
++ case TEST_J:
++ case TEST_K:
++ case TEST_SE0_NAK:
++ case TEST_PACKET:
++ case TEST_FORCE_EN:
++ ci->test_mode = tmode;
++ err = isr_setup_status_phase(
++ ci);
++ break;
++ default:
++ break;
++ }
++ break;
++ case USB_DEVICE_B_HNP_ENABLE:
++ if (ci_otg_is_fsm_mode(ci)) {
++ ci->gadget.b_hnp_enable = 1;
++ err = isr_setup_status_phase(
++ ci);
++ }
++ break;
++ default:
++ goto delegate;
++ }
++ } else {
++ goto delegate;
++ }
++ break;
++ default:
++delegate:
++ if (req.wLength == 0) /* no data phase */
++ ci->ep0_dir = TX;
++
++ spin_unlock(&ci->lock);
++ err = ci->driver->setup(&ci->gadget, &req);
++ spin_lock(&ci->lock);
++ break;
++ }
++
++ if (err < 0) {
++ spin_unlock(&ci->lock);
++ if (usb_ep_set_halt(&hwep->ep))
++ dev_err(ci->dev, "error: ep_set_halt\n");
++ spin_lock(&ci->lock);
++ }
++}
++
++/**
+ * isr_tr_complete_handler: transaction complete interrupt handler
+ * @ci: UDC descriptor
+ *
+@@ -972,12 +1134,10 @@
+ __acquires(ci->lock)
+ {
+ unsigned i;
+- u8 tmode = 0;
++ int err;
+
+ for (i = 0; i < ci->hw_ep_max; i++) {
+ struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
+- int type, num, dir, err = -EINVAL;
+- struct usb_ctrlrequest req;
+
+ if (hwep->ep.desc == NULL)
+ continue; /* not configured */
+@@ -997,148 +1157,10 @@
+ }
+ }
+
+- if (hwep->type != USB_ENDPOINT_XFER_CONTROL ||
+- !hw_test_and_clear_setup_status(ci, i))
+- continue;
+-
+- if (i != 0) {
+- dev_warn(ci->dev, "ctrl traffic at endpoint %d\n", i);
+- continue;
+- }
+-
+- /*
+- * Flush data and handshake transactions of previous
+- * setup packet.
+- */
+- _ep_nuke(ci->ep0out);
+- _ep_nuke(ci->ep0in);
+-
+- /* read_setup_packet */
+- do {
+- hw_test_and_set_setup_guard(ci);
+- memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
+- } while (!hw_test_and_clear_setup_guard(ci));
+-
+- type = req.bRequestType;
+-
+- ci->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
+-
+- switch (req.bRequest) {
+- case USB_REQ_CLEAR_FEATURE:
+- if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
+- le16_to_cpu(req.wValue) ==
+- USB_ENDPOINT_HALT) {
+- if (req.wLength != 0)
+- break;
+- num = le16_to_cpu(req.wIndex);
+- dir = num & USB_ENDPOINT_DIR_MASK;
+- num &= USB_ENDPOINT_NUMBER_MASK;
+- if (dir) /* TX */
+- num += ci->hw_ep_max/2;
+- if (!ci->ci_hw_ep[num].wedge) {
+- spin_unlock(&ci->lock);
+- err = usb_ep_clear_halt(
+- &ci->ci_hw_ep[num].ep);
+- spin_lock(&ci->lock);
+- if (err)
+- break;
+- }
+- err = isr_setup_status_phase(ci);
+- } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
+- le16_to_cpu(req.wValue) ==
+- USB_DEVICE_REMOTE_WAKEUP) {
+- if (req.wLength != 0)
+- break;
+- ci->remote_wakeup = 0;
+- err = isr_setup_status_phase(ci);
+- } else {
+- goto delegate;
+- }
+- break;
+- case USB_REQ_GET_STATUS:
+- if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
+- type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
+- type != (USB_DIR_IN|USB_RECIP_INTERFACE))
+- goto delegate;
+- if (le16_to_cpu(req.wLength) != 2 ||
+- le16_to_cpu(req.wValue) != 0)
+- break;
+- err = isr_get_status_response(ci, &req);
+- break;
+- case USB_REQ_SET_ADDRESS:
+- if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
+- goto delegate;
+- if (le16_to_cpu(req.wLength) != 0 ||
+- le16_to_cpu(req.wIndex) != 0)
+- break;
+- ci->address = (u8)le16_to_cpu(req.wValue);
+- ci->setaddr = true;
+- err = isr_setup_status_phase(ci);
+- break;
+- case USB_REQ_SET_FEATURE:
+- if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
+- le16_to_cpu(req.wValue) ==
+- USB_ENDPOINT_HALT) {
+- if (req.wLength != 0)
+- break;
+- num = le16_to_cpu(req.wIndex);
+- dir = num & USB_ENDPOINT_DIR_MASK;
+- num &= USB_ENDPOINT_NUMBER_MASK;
+- if (dir) /* TX */
+- num += ci->hw_ep_max/2;
+-
+- spin_unlock(&ci->lock);
+- err = usb_ep_set_halt(&ci->ci_hw_ep[num].ep);
+- spin_lock(&ci->lock);
+- if (!err)
+- isr_setup_status_phase(ci);
+- } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
+- if (req.wLength != 0)
+- break;
+- switch (le16_to_cpu(req.wValue)) {
+- case USB_DEVICE_REMOTE_WAKEUP:
+- ci->remote_wakeup = 1;
+- err = isr_setup_status_phase(ci);
+- break;
+- case USB_DEVICE_TEST_MODE:
+- tmode = le16_to_cpu(req.wIndex) >> 8;
+- switch (tmode) {
+- case TEST_J:
+- case TEST_K:
+- case TEST_SE0_NAK:
+- case TEST_PACKET:
+- case TEST_FORCE_EN:
+- ci->test_mode = tmode;
+- err = isr_setup_status_phase(
+- ci);
+- break;
+- default:
+- break;
+- }
+- default:
+- goto delegate;
+- }
+- } else {
+- goto delegate;
+- }
+- break;
+- default:
+-delegate:
+- if (req.wLength == 0) /* no data phase */
+- ci->ep0_dir = TX;
+-
+- spin_unlock(&ci->lock);
+- err = ci->driver->setup(&ci->gadget, &req);
+- spin_lock(&ci->lock);
+- break;
+- }
+-
+- if (err < 0) {
+- spin_unlock(&ci->lock);
+- if (usb_ep_set_halt(&hwep->ep))
+- dev_err(ci->dev, "error: ep_set_halt\n");
+- spin_lock(&ci->lock);
+- }
++ /* Only handle setup packet below */
++ if (i == 0 &&
++ hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(0)))
++ isr_setup_packet_handler(ci);
+ }
+ }
+
+@@ -1165,10 +1187,13 @@
+
+ /* only internal SW should enable ctrl endpts */
+
+- hwep->ep.desc = desc;
+-
+- if (!list_empty(&hwep->qh.queue))
++ if (!list_empty(&hwep->qh.queue)) {
+ dev_warn(hwep->ci->dev, "enabling a non-empty endpoint!\n");
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return -EBUSY;
++ }
++
++ hwep->ep.desc = desc;
+
+ hwep->dir = usb_endpoint_dir_in(desc) ? TX : RX;
+ hwep->num = usb_endpoint_num(desc);
+@@ -1193,6 +1218,11 @@
+
+ hwep->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
+
++ if (hwep->num != 0 && hwep->type == USB_ENDPOINT_XFER_CONTROL) {
++ dev_err(hwep->ci->dev, "Set control xfer at non-ep0\n");
++ retval = -EINVAL;
++ }
++
+ /*
+ * Enable endpoints in the HW other than ep0 as ep0
+ * is always enabled
+@@ -1222,6 +1252,10 @@
+ return -EBUSY;
+
+ spin_lock_irqsave(hwep->lock, flags);
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return 0;
++ }
+
+ /* only internal SW should disable ctrl endpts */
+
+@@ -1311,6 +1345,10 @@
+ return -EINVAL;
+
+ spin_lock_irqsave(hwep->lock, flags);
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return 0;
++ }
+ retval = _ep_queue(ep, req, gfp_flags);
+ spin_unlock_irqrestore(hwep->lock, flags);
+ return retval;
+@@ -1334,8 +1372,8 @@
+ return -EINVAL;
+
+ spin_lock_irqsave(hwep->lock, flags);
+-
+- hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
++ if (hwep->ci->gadget.speed != USB_SPEED_UNKNOWN)
++ hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
+
+ list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
+ dma_pool_free(hwep->td_pool, node->ptr, node->dma);
+@@ -1379,6 +1417,10 @@
+
+ spin_lock_irqsave(hwep->lock, flags);
+
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return 0;
++ }
+ #ifndef STALL_IN
+ /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
+ if (value && hwep->type == USB_ENDPOINT_XFER_BULK && hwep->dir == TX &&
+@@ -1440,6 +1482,10 @@
+ }
+
+ spin_lock_irqsave(hwep->lock, flags);
++ if (hwep->ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(hwep->lock, flags);
++ return;
++ }
+
+ hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
+
+@@ -1477,24 +1523,11 @@
+ gadget_ready = 1;
+ spin_unlock_irqrestore(&ci->lock, flags);
+
+- if (gadget_ready) {
+- if (is_active) {
+- pm_runtime_get_sync(&_gadget->dev);
+- hw_device_reset(ci, USBMODE_CM_DC);
+- hw_device_state(ci, ci->ep0out->qh.dma);
+- dev_dbg(ci->dev, "Connected to host\n");
+- } else {
+- if (ci->driver)
+- ci->driver->disconnect(&ci->gadget);
+- hw_device_state(ci, 0);
+- if (ci->platdata->notify_event)
+- ci->platdata->notify_event(ci,
+- CI_HDRC_CONTROLLER_STOPPED_EVENT);
+- _gadget_stop_activity(&ci->gadget);
+- pm_runtime_put_sync(&_gadget->dev);
+- dev_dbg(ci->dev, "Disconnected from host\n");
+- }
+- }
++ /* Charger Detection */
++ ci_usb_charger_connect(ci, is_active);
++
++ if (gadget_ready)
++ ci_hdrc_gadget_connect(_gadget, is_active);
+
+ return 0;
+ }
+@@ -1506,6 +1539,10 @@
+ int ret = 0;
+
+ spin_lock_irqsave(&ci->lock, flags);
++ if (ci->gadget.speed == USB_SPEED_UNKNOWN) {
++ spin_unlock_irqrestore(&ci->lock, flags);
++ return 0;
++ }
+ if (!ci->remote_wakeup) {
+ ret = -EOPNOTSUPP;
+ goto out;
+@@ -1524,8 +1561,8 @@
+ {
+ struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
+
+- if (ci->transceiver)
+- return usb_phy_set_power(ci->transceiver, ma);
++ if (ci->usb_phy)
++ return usb_phy_set_power(ci->usb_phy, ma);
+ return -ENOTSUPP;
+ }
+
+@@ -1642,7 +1679,6 @@
+ struct usb_gadget_driver *driver)
+ {
+ struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
+- unsigned long flags;
+ int retval = -ENOMEM;
+
+ if (driver->disconnect == NULL)
+@@ -1660,19 +1696,16 @@
+ return retval;
+
+ ci->driver = driver;
+- pm_runtime_get_sync(&ci->gadget.dev);
+- if (ci->vbus_active) {
+- spin_lock_irqsave(&ci->lock, flags);
+- hw_device_reset(ci, USBMODE_CM_DC);
+- } else {
+- pm_runtime_put_sync(&ci->gadget.dev);
++
++ /* Start otg fsm for B-device */
++ if (ci_otg_is_fsm_mode(ci)) {
++ if (ci->fsm.id)
++ ci_hdrc_otg_fsm_start(ci);
+ return retval;
+ }
+
+- retval = hw_device_state(ci, ci->ep0out->qh.dma);
+- spin_unlock_irqrestore(&ci->lock, flags);
+- if (retval)
+- pm_runtime_put_sync(&ci->gadget.dev);
++ if (ci->vbus_active)
++ ci_hdrc_gadget_connect(&ci->gadget, 1);
+
+ return retval;
+ }
+@@ -1758,6 +1791,8 @@
+ ci->suspended = 1;
+ spin_unlock(&ci->lock);
+ ci->driver->suspend(&ci->gadget);
++ usb_gadget_set_state(&ci->gadget,
++ USB_STATE_SUSPENDED);
+ spin_lock(&ci->lock);
+ }
+ }
+@@ -1784,7 +1819,7 @@
+ ci->gadget.ops = &usb_gadget_ops;
+ ci->gadget.speed = USB_SPEED_UNKNOWN;
+ ci->gadget.max_speed = USB_SPEED_HIGH;
+- ci->gadget.is_otg = 0;
++ ci->gadget.is_otg = ci->is_otg ? 1 : 0;
+ ci->gadget.name = ci->platdata->name;
+
+ INIT_LIST_HEAD(&ci->gadget.ep_list);
+@@ -1844,30 +1879,133 @@
+
+ dma_pool_destroy(ci->td_pool);
+ dma_pool_destroy(ci->qh_pool);
++}
++
++int ci_usb_charger_connect(struct ci_hdrc *ci, int is_active)
++{
++ int ret = 0;
+
+- if (ci->transceiver) {
+- otg_set_peripheral(ci->transceiver->otg, NULL);
+- if (ci->global_phy)
+- usb_put_phy(ci->transceiver);
++ if (is_active)
++ pm_runtime_get_sync(ci->dev);
++
++ if (ci->platdata->notify_event) {
++ if (is_active)
++ hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
++
++ ret = ci->platdata->notify_event(ci,
++ CI_HDRC_CONTROLLER_VBUS_EVENT);
++ if (ret == CI_HDRC_NOTIFY_RET_DEFER_EVENT) {
++ hw_device_reset(ci);
++ /* Pull up dp */
++ hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
++ ci->platdata->notify_event(ci,
++ CI_HDRC_CONTROLLER_CHARGER_POST_EVENT);
++ /* Pull down dp */
++ hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
++ }
+ }
++
++ if (!is_active)
++ pm_runtime_put_sync(ci->dev);
++
++ return ret;
+ }
+
+-static int udc_id_switch_for_device(struct ci_hdrc *ci)
++/**
++ * ci_hdrc_gadget_connect: caller make sure gadget driver is binded
++ */
++void ci_hdrc_gadget_connect(struct usb_gadget *gadget, int is_active)
+ {
+- if (ci->is_otg) {
+- ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
+- ci_enable_otg_interrupt(ci, OTGSC_BSVIE);
++ struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
++
++ if (is_active) {
++ pm_runtime_get_sync(&gadget->dev);
++ hw_device_reset(ci);
++ hw_device_state(ci, ci->ep0out->qh.dma);
++ usb_gadget_set_state(gadget, USB_STATE_POWERED);
++ } else {
++ if (ci->driver)
++ ci->driver->disconnect(gadget);
++ hw_device_state(ci, 0);
++ if (ci->platdata->notify_event)
++ ci->platdata->notify_event(ci,
++ CI_HDRC_CONTROLLER_STOPPED_EVENT);
++ _gadget_stop_activity(gadget);
++ pm_runtime_put_sync(&gadget->dev);
++ usb_gadget_set_state(gadget, USB_STATE_NOTATTACHED);
+ }
++}
++
++static int udc_id_switch_for_device(struct ci_hdrc *ci)
++{
++ if (!ci->is_otg)
++ return 0;
++
++ /*
++ * Clear and enable BSV irq for A-device switch to B-device
++ * (in otg fsm mode, means A_IDLE->B_DILE) due to ID change.
++ */
++ if (!ci_otg_is_fsm_mode(ci) ||
++ ci->fsm.otg->state == OTG_STATE_A_IDLE)
++ hw_write_otgsc(ci, OTGSC_BSVIS | OTGSC_BSVIE,
++ OTGSC_BSVIS | OTGSC_BSVIE);
+
+ return 0;
+ }
+
+ static void udc_id_switch_for_host(struct ci_hdrc *ci)
+ {
+- if (ci->is_otg) {
+- /* host doesn't care B_SESSION_VALID event */
+- ci_clear_otg_interrupt(ci, OTGSC_BSVIS);
+- ci_disable_otg_interrupt(ci, OTGSC_BSVIE);
++ if (!ci->is_otg)
++ return;
++
++ /*
++ * Clear and disbale BSV irq for B-device switch to A-device
++ * (in otg fsm mode, means B_IDLE->A_IDLE) due to ID change.
++ */
++ if (!ci_otg_is_fsm_mode(ci) ||
++ ci->fsm.otg->state == OTG_STATE_B_IDLE)
++ hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS);
++}
++
++static void udc_suspend_for_power_lost(struct ci_hdrc *ci)
++{
++ /*
++ * Set OP_ENDPTLISTADDR to be non-zero for
++ * checking if controller resume from power lost
++ * in non-host mode.
++ */
++ if (hw_read(ci, OP_ENDPTLISTADDR, ~0) == 0)
++ hw_write(ci, OP_ENDPTLISTADDR, ~0, ~0);
++}
++
++/* Power lost with device mode */
++static void udc_resume_from_power_lost(struct ci_hdrc *ci)
++{
++ /* Force disconnect if power lost with vbus on */
++ if (!ci_otg_is_fsm_mode(ci) && ci->vbus_active)
++ usb_gadget_vbus_disconnect(&ci->gadget);
++
++ if (ci->is_otg)
++ hw_write_otgsc(ci, OTGSC_BSVIS | OTGSC_BSVIE,
++ OTGSC_BSVIS | OTGSC_BSVIE);
++}
++
++static void udc_suspend(struct ci_hdrc *ci)
++{
++ udc_suspend_for_power_lost(ci);
++
++ if (ci->driver && ci->vbus_active &&
++ (ci->gadget.state != USB_STATE_SUSPENDED))
++ usb_gadget_disconnect(&ci->gadget);
++}
++
++static void udc_resume(struct ci_hdrc *ci, bool power_lost)
++{
++ if (power_lost) {
++ udc_resume_from_power_lost(ci);
++ } else {
++ if (ci->driver && ci->vbus_active)
++ usb_gadget_connect(&ci->gadget);
+ }
+ }
+
+@@ -1891,6 +2029,8 @@
+ rdrv->start = udc_id_switch_for_device;
+ rdrv->stop = udc_id_switch_for_host;
+ rdrv->irq = udc_irq;
++ rdrv->suspend = udc_suspend;
++ rdrv->resume = udc_resume;
+ rdrv->name = "gadget";
+ ci->roles[CI_ROLE_GADGET] = rdrv;
+
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/udc.h linux-3.14.72/drivers/usb/chipidea/udc.h
+--- linux-3.14.72.orig/drivers/usb/chipidea/udc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/udc.h 2016-06-19 22:11:55.325138694 +0200
+@@ -85,6 +85,8 @@
+
+ int ci_hdrc_gadget_init(struct ci_hdrc *ci);
+ void ci_hdrc_gadget_destroy(struct ci_hdrc *ci);
++int ci_usb_charger_connect(struct ci_hdrc *ci, int is_active);
++void ci_hdrc_gadget_connect(struct usb_gadget *gadget, int is_active);
+
+ #else
+
+@@ -97,6 +99,17 @@
+ {
+
+ }
++
++static inline int ci_usb_charger_connect(struct ci_hdrc *ci, int is_active)
++{
++ return 0;
++}
++
++static inline void ci_hdrc_gadget_connect(struct usb_gadget *gadget,
++ int is_active)
++{
++
++}
+
+ #endif
+
+diff -Nur linux-3.14.72.orig/drivers/usb/chipidea/usbmisc_imx.c linux-3.14.72/drivers/usb/chipidea/usbmisc_imx.c
+--- linux-3.14.72.orig/drivers/usb/chipidea/usbmisc_imx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/chipidea/usbmisc_imx.c 2016-06-19 22:11:55.325138694 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2015 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -11,47 +11,145 @@
+
+ #include <linux/module.h>
+ #include <linux/of_platform.h>
+-#include <linux/clk.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
+ #include <linux/delay.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
+
+ #include "ci_hdrc_imx.h"
+
+ #define MX25_USB_PHY_CTRL_OFFSET 0x08
+ #define MX25_BM_EXTERNAL_VBUS_DIVIDER BIT(23)
+
++#define MX25_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
++#define MX25_EHCI_INTERFACE_DIFF_UNI (0 << 0)
++#define MX25_EHCI_INTERFACE_MASK (0xf)
++
++#define MX25_OTG_SIC_SHIFT 29
++#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
++#define MX25_OTG_PM_BIT BIT(24)
++#define MX25_OTG_PP_BIT BIT(11)
++#define MX25_OTG_OCPOL_BIT BIT(3)
++
++#define MX25_H1_SIC_SHIFT 21
++#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
++#define MX25_H1_PP_BIT BIT(18)
++#define MX25_H1_PM_BIT BIT(16)
++#define MX25_H1_IPPUE_UP_BIT BIT(7)
++#define MX25_H1_IPPUE_DOWN_BIT BIT(6)
++#define MX25_H1_TLL_BIT BIT(5)
++#define MX25_H1_USBTE_BIT BIT(4)
++#define MX25_H1_OCPOL_BIT BIT(2)
++
+ #define MX27_H1_PM_BIT BIT(8)
+ #define MX27_H2_PM_BIT BIT(16)
+ #define MX27_OTG_PM_BIT BIT(24)
+
+ #define MX53_USB_OTG_PHY_CTRL_0_OFFSET 0x08
++#define MX53_USB_OTG_PHY_CTRL_1_OFFSET 0x0c
+ #define MX53_USB_UH2_CTRL_OFFSET 0x14
+ #define MX53_USB_UH3_CTRL_OFFSET 0x18
+ #define MX53_BM_OVER_CUR_DIS_H1 BIT(5)
+ #define MX53_BM_OVER_CUR_DIS_OTG BIT(8)
+ #define MX53_BM_OVER_CUR_DIS_UHx BIT(30)
++#define MX53_USB_PHYCTRL1_PLLDIV_MASK 0x3
++#define MX53_USB_PLL_DIV_24_MHZ 0x01
+
++#define MX6_BM_UNBURST_SETTING BIT(1)
+ #define MX6_BM_OVER_CUR_DIS BIT(7)
++#define MX6_BM_WAKEUP_ENABLE BIT(10)
++#define MX6_BM_UTMI_ON_CLOCK BIT(13)
++#define MX6_BM_ID_WAKEUP BIT(16)
++#define MX6_BM_VBUS_WAKEUP BIT(17)
++#define MX6SX_BM_DPDM_WAKEUP_EN BIT(29)
++#define MX6_BM_WAKEUP_INTR BIT(31)
++
++#define MX6_USB_HSIC_CTRL_OFFSET 0x10
++/* Send resume signal without 480Mhz PHY clock */
++#define MX6SX_BM_HSIC_AUTO_RESUME BIT(23)
++/* set before portsc.suspendM = 1 */
++#define MX6_BM_HSIC_DEV_CONN BIT(21)
++/* HSIC enable */
++#define MX6_BM_HSIC_EN BIT(12)
++/* Force HSIC module 480M clock on, even when in Host is in suspend mode */
++#define MX6_BM_HSIC_CLK_ON BIT(11)
++
++#define MX6_USB_OTG1_PHY_CTRL 0x18
++/* For imx6dql, it is host-only controller, for later imx6, it is otg's */
++#define MX6_USB_OTG2_PHY_CTRL 0x1c
++#define MX6SX_USB_VBUS_WAKEUP_SOURCE(v) (v << 8)
++#define MX6SX_USB_VBUS_WAKEUP_SOURCE_VBUS MX6SX_USB_VBUS_WAKEUP_SOURCE(0)
++#define MX6SX_USB_VBUS_WAKEUP_SOURCE_AVALID MX6SX_USB_VBUS_WAKEUP_SOURCE(1)
++#define MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID MX6SX_USB_VBUS_WAKEUP_SOURCE(2)
++#define MX6SX_USB_VBUS_WAKEUP_SOURCE_SESS_END MX6SX_USB_VBUS_WAKEUP_SOURCE(3)
++
++#define VF610_OVER_CUR_DIS BIT(7)
++
++#define ANADIG_ANA_MISC0 0x150
++#define ANADIG_ANA_MISC0_SET 0x154
++#define ANADIG_ANA_MISC0_CLK_DELAY(x) ((x >> 26) & 0x7)
+
+ struct usbmisc_ops {
+ /* It's called once when probe a usb device */
+ int (*init)(struct imx_usbmisc_data *data);
+ /* It's called once after adding a usb device */
+ int (*post)(struct imx_usbmisc_data *data);
++ /* It's called when we need to enable/disable usb wakeup */
++ int (*set_wakeup)(struct imx_usbmisc_data *data, bool enabled);
++ /* It's called when system resume from usb power lost */
++ int (*power_lost_check)(struct imx_usbmisc_data *data);
++ /* It's called before setting portsc.suspendM */
++ int (*hsic_set_connect)(struct imx_usbmisc_data *data);
++ /* It's called during suspend/resume */
++ int (*hsic_set_clk)(struct imx_usbmisc_data *data, bool enabled);
+ };
+
+ struct imx_usbmisc {
+ void __iomem *base;
+ spinlock_t lock;
+- struct clk *clk;
+ const struct usbmisc_ops *ops;
+ };
+
+-static struct imx_usbmisc *usbmisc;
++static struct regulator *vbus_wakeup_reg;
++
++static int usbmisc_imx25_init(struct imx_usbmisc_data *data)
++{
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
++ unsigned long flags;
++ u32 val = 0;
++
++ if (data->index > 1)
++ return -EINVAL;
++
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ switch (data->index) {
++ case 0:
++ val = readl(usbmisc->base);
++ val &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PP_BIT);
++ val |= (MX25_EHCI_INTERFACE_DIFF_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
++ val |= (MX25_OTG_PM_BIT | MX25_OTG_OCPOL_BIT);
++ writel(val, usbmisc->base);
++ break;
++ case 1:
++ val = readl(usbmisc->base);
++ val &= ~(MX25_H1_SIC_MASK | MX25_H1_PP_BIT | MX25_H1_IPPUE_UP_BIT);
++ val |= (MX25_EHCI_INTERFACE_SINGLE_UNI & MX25_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
++ val |= (MX25_H1_PM_BIT | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
++ MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT);
++
++ writel(val, usbmisc->base);
++
++ break;
++ }
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++
++ return 0;
++}
+
+ static int usbmisc_imx25_post(struct imx_usbmisc_data *data)
+ {
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
+ void __iomem *reg;
+ unsigned long flags;
+ u32 val;
+@@ -59,10 +157,9 @@
+ if (data->index > 2)
+ return -EINVAL;
+
+- reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET;
+-
+ if (data->evdo) {
+ spin_lock_irqsave(&usbmisc->lock, flags);
++ reg = usbmisc->base + MX25_USB_PHY_CTRL_OFFSET;
+ val = readl(reg);
+ writel(val | MX25_BM_EXTERNAL_VBUS_DIVIDER, reg);
+ spin_unlock_irqrestore(&usbmisc->lock, flags);
+@@ -74,6 +171,7 @@
+
+ static int usbmisc_imx27_init(struct imx_usbmisc_data *data)
+ {
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
+ unsigned long flags;
+ u32 val;
+
+@@ -104,6 +202,7 @@
+
+ static int usbmisc_imx53_init(struct imx_usbmisc_data *data)
+ {
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
+ void __iomem *reg = NULL;
+ unsigned long flags;
+ u32 val = 0;
+@@ -111,6 +210,12 @@
+ if (data->index > 3)
+ return -EINVAL;
+
++ /* Select a 24 MHz reference clock for the PHY */
++ val = readl(usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
++ val &= ~MX53_USB_PHYCTRL1_PLLDIV_MASK;
++ val |= MX53_USB_PLL_DIV_24_MHZ;
++ writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET);
++
+ if (data->disable_oc) {
+ spin_lock_irqsave(&usbmisc->lock, flags);
+ switch (data->index) {
+@@ -139,26 +244,216 @@
+ return 0;
+ }
+
++static int usbmisc_imx6_hsic_set_connect(struct imx_usbmisc_data *data)
++{
++ unsigned long flags;
++ u32 val;
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
++
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ if (data->index == 2 || data->index == 3) {
++ val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET
++ + (data->index - 2) * 4);
++ if (!(val & MX6_BM_HSIC_DEV_CONN))
++ writel(val | MX6_BM_HSIC_DEV_CONN,
++ usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET
++ + (data->index - 2) * 4);
++ }
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++
++ return 0;
++}
++
++static int usbmisc_imx6_hsic_set_clk(struct imx_usbmisc_data *data, bool on)
++{
++ unsigned long flags;
++ u32 val;
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
++
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ if (data->index == 2 || data->index == 3) {
++ val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET
++ + (data->index - 2) * 4);
++ val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON;
++ if (on)
++ val |= MX6_BM_HSIC_CLK_ON;
++ else
++ val &= ~MX6_BM_HSIC_CLK_ON;
++ writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET
++ + (data->index - 2) * 4);
++ }
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++
++ return 0;
++}
++
++static u32 imx6q_finalize_wakeup_setting(struct imx_usbmisc_data *data)
++{
++ if (data->available_role == USB_DR_MODE_PERIPHERAL)
++ return MX6_BM_VBUS_WAKEUP;
++ else if (data->available_role == USB_DR_MODE_OTG)
++ return MX6_BM_VBUS_WAKEUP | MX6_BM_ID_WAKEUP;
++
++ return 0;
++}
++
++static int usbmisc_imx6q_set_wakeup
++ (struct imx_usbmisc_data *data, bool enabled)
++{
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
++ unsigned long flags;
++ u32 val;
++ u32 wakeup_setting = MX6_BM_WAKEUP_ENABLE;
++ int ret = 0;
++
++ if (data->index > 3)
++ return -EINVAL;
++
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ val = readl(usbmisc->base + data->index * 4);
++ if (enabled) {
++ wakeup_setting |= imx6q_finalize_wakeup_setting(data);
++ writel(val | wakeup_setting, usbmisc->base + data->index * 4);
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++ if (vbus_wakeup_reg)
++ ret = regulator_enable(vbus_wakeup_reg);
++ } else {
++ if (val & MX6_BM_WAKEUP_INTR)
++ pr_debug("wakeup int at ci_hdrc.%d\n", data->index);
++ wakeup_setting |= MX6_BM_VBUS_WAKEUP | MX6_BM_ID_WAKEUP;
++ writel(val & ~wakeup_setting, usbmisc->base + data->index * 4);
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++ if (vbus_wakeup_reg && regulator_is_enabled(vbus_wakeup_reg))
++ regulator_disable(vbus_wakeup_reg);
++ }
++
++ return ret;
++}
++
+ static int usbmisc_imx6q_init(struct imx_usbmisc_data *data)
+ {
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
+ unsigned long flags;
+ u32 reg;
+
+ if (data->index > 3)
+ return -EINVAL;
+
++ spin_lock_irqsave(&usbmisc->lock, flags);
++
+ if (data->disable_oc) {
+- spin_lock_irqsave(&usbmisc->lock, flags);
+ reg = readl(usbmisc->base + data->index * 4);
+ writel(reg | MX6_BM_OVER_CUR_DIS,
+ usbmisc->base + data->index * 4);
++ }
++
++ /* SoC unburst setting */
++ reg = readl(usbmisc->base + data->index * 4);
++ writel(reg | MX6_BM_UNBURST_SETTING,
++ usbmisc->base + data->index * 4);
++
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++
++ usbmisc_imx6q_set_wakeup(data, false);
++
++ return 0;
++}
++
++static int usbmisc_imx6sx_init(struct imx_usbmisc_data *data)
++{
++ void __iomem *reg = NULL;
++ unsigned long flags;
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
++ u32 val;
++ int ret = 0;
++
++ usbmisc_imx6q_init(data);
++
++ if (data->index == 0 || data->index == 1) {
++ reg = usbmisc->base + MX6_USB_OTG1_PHY_CTRL + data->index * 4;
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ /* Set vbus wakeup source as bvalid */
++ val = readl(reg);
++ writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg);
++ /*
++ * Disable dp/dm wakeup in device mode when vbus is
++ * not there.
++ */
++ val = readl(usbmisc->base + data->index * 4);
++ writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN,
++ usbmisc->base + data->index * 4);
+ spin_unlock_irqrestore(&usbmisc->lock, flags);
+ }
+
++ /* For HSIC controller */
++ if (data->index == 2) {
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ val = readl(usbmisc->base + data->index * 4);
++ writel(val | MX6_BM_UTMI_ON_CLOCK,
++ usbmisc->base + data->index * 4);
++ val = readl(usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET
++ + (data->index - 2) * 4);
++ val |= MX6_BM_HSIC_EN | MX6_BM_HSIC_CLK_ON |
++ MX6SX_BM_HSIC_AUTO_RESUME;
++ writel(val, usbmisc->base + MX6_USB_HSIC_CTRL_OFFSET
++ + (data->index - 2) * 4);
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++
++ /*
++ * Need to add delay to wait 24M OSC to be stable,
++ * it's board specific.
++ */
++ regmap_read(data->anatop, ANADIG_ANA_MISC0, &val);
++ /* 0 <= data->osc_clkgate_delay <= 7 */
++ if (data->osc_clkgate_delay > ANADIG_ANA_MISC0_CLK_DELAY(val))
++ regmap_write(data->anatop, ANADIG_ANA_MISC0_SET,
++ (data->osc_clkgate_delay) << 26);
++ }
++
++ return ret;
++}
++
++static int usbmisc_vf610_init(struct imx_usbmisc_data *data)
++{
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
++ u32 reg;
++
++ /*
++ * Vybrid only has one misc register set, but in two different
++ * areas. These is reflected in two instances of this driver.
++ */
++ if (data->index >= 1)
++ return -EINVAL;
++
++ if (data->disable_oc) {
++ reg = readl(usbmisc->base);
++ writel(reg | VF610_OVER_CUR_DIS, usbmisc->base);
++ }
++
+ return 0;
+ }
+
++static int usbmisc_imx6sx_power_lost_check(struct imx_usbmisc_data *data)
++{
++ struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
++ unsigned long flags;
++ u32 val;
++
++ spin_lock_irqsave(&usbmisc->lock, flags);
++ val = readl(usbmisc->base + data->index * 4);
++ spin_unlock_irqrestore(&usbmisc->lock, flags);
++ /*
++ * Here use a power on reset value to judge
++ * if the controller experienced a power lost
++ */
++ if (val == 0x30001000)
++ return 1;
++ else
++ return 0;
++}
++
+ static const struct usbmisc_ops imx25_usbmisc_ops = {
++ .init = usbmisc_imx25_init,
+ .post = usbmisc_imx25_post,
+ };
+
+@@ -171,13 +466,32 @@
+ };
+
+ static const struct usbmisc_ops imx6q_usbmisc_ops = {
++ .set_wakeup = usbmisc_imx6q_set_wakeup,
+ .init = usbmisc_imx6q_init,
++ .hsic_set_connect = usbmisc_imx6_hsic_set_connect,
++ .hsic_set_clk = usbmisc_imx6_hsic_set_clk,
++};
++
++static const struct usbmisc_ops vf610_usbmisc_ops = {
++ .init = usbmisc_vf610_init,
++};
++
++static const struct usbmisc_ops imx6sx_usbmisc_ops = {
++ .set_wakeup = usbmisc_imx6q_set_wakeup,
++ .init = usbmisc_imx6sx_init,
++ .power_lost_check = usbmisc_imx6sx_power_lost_check,
++ .hsic_set_connect = usbmisc_imx6_hsic_set_connect,
++ .hsic_set_clk = usbmisc_imx6_hsic_set_clk,
+ };
+
+ int imx_usbmisc_init(struct imx_usbmisc_data *data)
+ {
+- if (!usbmisc)
+- return -EPROBE_DEFER;
++ struct imx_usbmisc *usbmisc;
++
++ if (!data)
++ return 0;
++
++ usbmisc = dev_get_drvdata(data->dev);
+ if (!usbmisc->ops->init)
+ return 0;
+ return usbmisc->ops->init(data);
+@@ -186,20 +500,84 @@
+
+ int imx_usbmisc_init_post(struct imx_usbmisc_data *data)
+ {
+- if (!usbmisc)
+- return -EPROBE_DEFER;
++ struct imx_usbmisc *usbmisc;
++
++ if (!data)
++ return 0;
++
++ usbmisc = dev_get_drvdata(data->dev);
+ if (!usbmisc->ops->post)
+ return 0;
+ return usbmisc->ops->post(data);
+ }
+ EXPORT_SYMBOL_GPL(imx_usbmisc_init_post);
+
++int imx_usbmisc_set_wakeup(struct imx_usbmisc_data *data, bool enabled)
++{
++ struct imx_usbmisc *usbmisc;
++
++ if (!data)
++ return 0;
++
++ usbmisc = dev_get_drvdata(data->dev);
++ if (!usbmisc->ops->set_wakeup)
++ return 0;
++ return usbmisc->ops->set_wakeup(data, enabled);
++}
++EXPORT_SYMBOL_GPL(imx_usbmisc_set_wakeup);
++
++int imx_usbmisc_power_lost_check(struct imx_usbmisc_data *data)
++{
++ struct imx_usbmisc *usbmisc;
++
++ if (!data)
++ return 0;
++
++ usbmisc = dev_get_drvdata(data->dev);
++ if (!usbmisc->ops->power_lost_check)
++ return 0;
++ return usbmisc->ops->power_lost_check(data);
++}
++EXPORT_SYMBOL_GPL(imx_usbmisc_power_lost_check);
++
++int imx_usbmisc_hsic_set_connect(struct imx_usbmisc_data *data)
++{
++ struct imx_usbmisc *usbmisc;
++
++ if (!data)
++ return 0;
++
++ usbmisc = dev_get_drvdata(data->dev);
++ if (!usbmisc->ops->hsic_set_connect)
++ return 0;
++ return usbmisc->ops->hsic_set_connect(data);
++}
++EXPORT_SYMBOL_GPL(imx_usbmisc_hsic_set_connect);
++
++int imx_usbmisc_hsic_set_clk(struct imx_usbmisc_data *data, bool on)
++{
++ struct imx_usbmisc *usbmisc;
++
++ if (!data)
++ return 0;
++
++ usbmisc = dev_get_drvdata(data->dev);
++ if (!usbmisc->ops->hsic_set_clk)
++ return 0;
++ return usbmisc->ops->hsic_set_clk(data, on);
++}
++EXPORT_SYMBOL_GPL(imx_usbmisc_hsic_set_clk);
++
+ static const struct of_device_id usbmisc_imx_dt_ids[] = {
+ {
+ .compatible = "fsl,imx25-usbmisc",
+ .data = &imx25_usbmisc_ops,
+ },
+ {
++ .compatible = "fsl,imx35-usbmisc",
++ .data = &imx25_usbmisc_ops,
++ },
++ {
+ .compatible = "fsl,imx27-usbmisc",
+ .data = &imx27_usbmisc_ops,
+ },
+@@ -215,6 +593,14 @@
+ .compatible = "fsl,imx6q-usbmisc",
+ .data = &imx6q_usbmisc_ops,
+ },
++ {
++ .compatible = "fsl,vf610-usbmisc",
++ .data = &vf610_usbmisc_ops,
++ },
++ {
++ .compatible = "fsl,imx6sx-usbmisc",
++ .data = &imx6sx_usbmisc_ops,
++ },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, usbmisc_imx_dt_ids);
+@@ -223,12 +609,8 @@
+ {
+ struct resource *res;
+ struct imx_usbmisc *data;
+- int ret;
+ struct of_device_id *tmp_dev;
+
+- if (usbmisc)
+- return -EBUSY;
+-
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+@@ -240,32 +622,28 @@
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+- data->clk = devm_clk_get(&pdev->dev, NULL);
+- if (IS_ERR(data->clk)) {
+- dev_err(&pdev->dev,
+- "failed to get clock, err=%ld\n", PTR_ERR(data->clk));
+- return PTR_ERR(data->clk);
+- }
+-
+- ret = clk_prepare_enable(data->clk);
+- if (ret) {
+- dev_err(&pdev->dev,
+- "clk_prepare_enable failed, err=%d\n", ret);
+- return ret;
+- }
+-
+ tmp_dev = (struct of_device_id *)
+ of_match_device(usbmisc_imx_dt_ids, &pdev->dev);
+ data->ops = (const struct usbmisc_ops *)tmp_dev->data;
+- usbmisc = data;
++ platform_set_drvdata(pdev, data);
++
++ vbus_wakeup_reg = devm_regulator_get(&pdev->dev, "vbus-wakeup");
++ if (PTR_ERR(vbus_wakeup_reg) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
++ else if (PTR_ERR(vbus_wakeup_reg) == -ENODEV)
++ /* no vbus regualator is needed */
++ vbus_wakeup_reg = NULL;
++ else if (IS_ERR(vbus_wakeup_reg)) {
++ dev_err(&pdev->dev, "Getting regulator error: %ld\n",
++ PTR_ERR(vbus_wakeup_reg));
++ return PTR_ERR(vbus_wakeup_reg);
++ }
+
+ return 0;
+ }
+
+ static int usbmisc_imx_remove(struct platform_device *pdev)
+ {
+- clk_disable_unprepare(usbmisc->clk);
+- usbmisc = NULL;
+ return 0;
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/usb/class/cdc-acm.c linux-3.14.72/drivers/usb/class/cdc-acm.c
+--- linux-3.14.72.orig/drivers/usb/class/cdc-acm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/class/cdc-acm.c 2016-06-19 22:11:55.329138432 +0200
+@@ -350,7 +350,7 @@
+ }
+ exit:
+ retval = usb_submit_urb(urb, GFP_ATOMIC);
+- if (retval)
++ if (retval && retval != -EPERM)
+ dev_err(&acm->control->dev, "%s - usb_submit_urb failed: %d\n",
+ __func__, retval);
+ }
+@@ -407,23 +407,31 @@
+ struct acm_rb *rb = urb->context;
+ struct acm *acm = rb->instance;
+ unsigned long flags;
++ int status = urb->status;
+
+ dev_vdbg(&acm->data->dev, "%s - urb %d, len %d\n", __func__,
+ rb->index, urb->actual_length);
+- set_bit(rb->index, &acm->read_urbs_free);
+
+ if (!acm->dev) {
++ set_bit(rb->index, &acm->read_urbs_free);
+ dev_dbg(&acm->data->dev, "%s - disconnected\n", __func__);
+ return;
+ }
+ usb_mark_last_busy(acm->dev);
+
+- if (urb->status) {
++ if (status) {
++ set_bit(rb->index, &acm->read_urbs_free);
+ dev_dbg(&acm->data->dev, "%s - non-zero urb status: %d\n",
+- __func__, urb->status);
++ __func__, status);
+ return;
+ }
+ acm_process_read_urb(acm, urb);
++ /*
++ * Unthrottle may run on another CPU which needs to see events
++ * in the same order. Submission has an implict barrier
++ */
++ smp_mb__before_clear_bit();
++ set_bit(rb->index, &acm->read_urbs_free);
+
+ /* throttle device if requested by tty */
+ spin_lock_irqsave(&acm->read_lock, flags);
+@@ -442,13 +450,14 @@
+ struct acm_wb *wb = urb->context;
+ struct acm *acm = wb->instance;
+ unsigned long flags;
++ int status = urb->status;
+
+- if (urb->status || (urb->actual_length != urb->transfer_buffer_length))
++ if (status || (urb->actual_length != urb->transfer_buffer_length))
+ dev_vdbg(&acm->data->dev, "%s - len %d/%d, status %d\n",
+ __func__,
+ urb->actual_length,
+ urb->transfer_buffer_length,
+- urb->status);
++ status);
+
+ spin_lock_irqsave(&acm->write_lock, flags);
+ acm_write_done(acm, wb);
+@@ -1063,6 +1072,7 @@
+ unsigned long quirks;
+ int num_rx_buf;
+ int i;
++ unsigned int elength = 0;
+ int combined_interfaces = 0;
+ struct device *tty_dev;
+ int rv = -ENOMEM;
+@@ -1107,6 +1117,12 @@
+ }
+
+ while (buflen > 0) {
++ elength = buffer[0];
++ if (!elength) {
++ dev_err(&intf->dev, "skipping garbage byte\n");
++ elength = 1;
++ goto next_desc;
++ }
+ if (buffer[1] != USB_DT_CS_INTERFACE) {
+ dev_err(&intf->dev, "skipping garbage\n");
+ goto next_desc;
+@@ -1114,6 +1130,8 @@
+
+ switch (buffer[2]) {
+ case USB_CDC_UNION_TYPE: /* we've found it */
++ if (elength < sizeof(struct usb_cdc_union_desc))
++ goto next_desc;
+ if (union_header) {
+ dev_err(&intf->dev, "More than one "
+ "union descriptor, skipping ...\n");
+@@ -1122,31 +1140,38 @@
+ union_header = (struct usb_cdc_union_desc *)buffer;
+ break;
+ case USB_CDC_COUNTRY_TYPE: /* export through sysfs*/
++ if (elength < sizeof(struct usb_cdc_country_functional_desc))
++ goto next_desc;
+ cfd = (struct usb_cdc_country_functional_desc *)buffer;
+ break;
+ case USB_CDC_HEADER_TYPE: /* maybe check version */
+ break; /* for now we ignore it */
+ case USB_CDC_ACM_TYPE:
++ if (elength < 4)
++ goto next_desc;
+ ac_management_function = buffer[3];
+ break;
+ case USB_CDC_CALL_MANAGEMENT_TYPE:
++ if (elength < 5)
++ goto next_desc;
+ call_management_function = buffer[3];
+ call_interface_num = buffer[4];
+ if ((quirks & NOT_A_MODEM) == 0 && (call_management_function & 3) != 3)
+ dev_err(&intf->dev, "This device cannot do calls on its own. It is not a modem.\n");
+ break;
+ default:
+- /* there are LOTS more CDC descriptors that
++ /*
++ * there are LOTS more CDC descriptors that
+ * could legitimately be found here.
+ */
+ dev_dbg(&intf->dev, "Ignoring descriptor: "
+- "type %02x, length %d\n",
+- buffer[2], buffer[0]);
++ "type %02x, length %ud\n",
++ buffer[2], elength);
+ break;
+ }
+ next_desc:
+- buflen -= buffer[0];
+- buffer += buffer[0];
++ buflen -= elength;
++ buffer += elength;
+ }
+
+ if (!union_header) {
+@@ -1264,10 +1289,8 @@
+ dev_dbg(&intf->dev, "interfaces are valid\n");
+
+ acm = kzalloc(sizeof(struct acm), GFP_KERNEL);
+- if (acm == NULL) {
+- dev_err(&intf->dev, "out of memory (acm kzalloc)\n");
++ if (acm == NULL)
+ goto alloc_fail;
+- }
+
+ minor = acm_alloc_minor(acm);
+ if (minor == ACM_TTY_MINORS) {
+@@ -1305,42 +1328,32 @@
+ init_usb_anchor(&acm->delayed);
+
+ buf = usb_alloc_coherent(usb_dev, ctrlsize, GFP_KERNEL, &acm->ctrl_dma);
+- if (!buf) {
+- dev_err(&intf->dev, "out of memory (ctrl buffer alloc)\n");
++ if (!buf)
+ goto alloc_fail2;
+- }
+ acm->ctrl_buffer = buf;
+
+- if (acm_write_buffers_alloc(acm) < 0) {
+- dev_err(&intf->dev, "out of memory (write buffer alloc)\n");
++ if (acm_write_buffers_alloc(acm) < 0)
+ goto alloc_fail4;
+- }
+
+ acm->ctrlurb = usb_alloc_urb(0, GFP_KERNEL);
+- if (!acm->ctrlurb) {
+- dev_err(&intf->dev, "out of memory (ctrlurb kmalloc)\n");
++ if (!acm->ctrlurb)
+ goto alloc_fail5;
+- }
++
+ for (i = 0; i < num_rx_buf; i++) {
+ struct acm_rb *rb = &(acm->read_buffers[i]);
+ struct urb *urb;
+
+ rb->base = usb_alloc_coherent(acm->dev, readsize, GFP_KERNEL,
+ &rb->dma);
+- if (!rb->base) {
+- dev_err(&intf->dev, "out of memory "
+- "(read bufs usb_alloc_coherent)\n");
++ if (!rb->base)
+ goto alloc_fail6;
+- }
+ rb->index = i;
+ rb->instance = acm;
+
+ urb = usb_alloc_urb(0, GFP_KERNEL);
+- if (!urb) {
+- dev_err(&intf->dev,
+- "out of memory (read urbs usb_alloc_urb)\n");
++ if (!urb)
+ goto alloc_fail6;
+- }
++
+ urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+ urb->transfer_dma = rb->dma;
+ if (acm->is_int_ep) {
+@@ -1365,11 +1378,8 @@
+ struct acm_wb *snd = &(acm->wb[i]);
+
+ snd->urb = usb_alloc_urb(0, GFP_KERNEL);
+- if (snd->urb == NULL) {
+- dev_err(&intf->dev,
+- "out of memory (write urbs usb_alloc_urb)\n");
++ if (snd->urb == NULL)
+ goto alloc_fail7;
+- }
+
+ if (usb_endpoint_xfer_int(epwrite))
+ usb_fill_int_urb(snd->urb, usb_dev,
+diff -Nur linux-3.14.72.orig/drivers/usb/common/Makefile linux-3.14.72/drivers/usb/common/Makefile
+--- linux-3.14.72.orig/drivers/usb/common/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/common/Makefile 2016-06-19 22:11:55.329138432 +0200
+@@ -0,0 +1,6 @@
++#
++# Makefile for the usb common parts.
++#
++
++obj-$(CONFIG_USB_COMMON) += usb-common.o
++obj-$(CONFIG_USB_OTG_FSM) += usb-otg-fsm.o
+diff -Nur linux-3.14.72.orig/drivers/usb/common/usb-common.c linux-3.14.72/drivers/usb/common/usb-common.c
+--- linux-3.14.72.orig/drivers/usb/common/usb-common.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/common/usb-common.c 2016-06-19 22:11:55.329138432 +0200
+@@ -0,0 +1,159 @@
++/*
++ * Provides code common for host and device side USB.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation, version 2.
++ *
++ * If either host side (ie. CONFIG_USB=y) or device side USB stack
++ * (ie. CONFIG_USB_GADGET=y) is compiled in the kernel, this module is
++ * compiled-in as well. Otherwise, if either of the two stacks is
++ * compiled as module, this file is compiled as module as well.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/usb/ch9.h>
++#include <linux/usb/of.h>
++#include <linux/usb/otg.h>
++
++const char *usb_otg_state_string(enum usb_otg_state state)
++{
++ static const char *const names[] = {
++ [OTG_STATE_A_IDLE] = "a_idle",
++ [OTG_STATE_A_WAIT_VRISE] = "a_wait_vrise",
++ [OTG_STATE_A_WAIT_BCON] = "a_wait_bcon",
++ [OTG_STATE_A_HOST] = "a_host",
++ [OTG_STATE_A_SUSPEND] = "a_suspend",
++ [OTG_STATE_A_PERIPHERAL] = "a_peripheral",
++ [OTG_STATE_A_WAIT_VFALL] = "a_wait_vfall",
++ [OTG_STATE_A_VBUS_ERR] = "a_vbus_err",
++ [OTG_STATE_B_IDLE] = "b_idle",
++ [OTG_STATE_B_SRP_INIT] = "b_srp_init",
++ [OTG_STATE_B_PERIPHERAL] = "b_peripheral",
++ [OTG_STATE_B_WAIT_ACON] = "b_wait_acon",
++ [OTG_STATE_B_HOST] = "b_host",
++ };
++
++ if (state < 0 || state >= ARRAY_SIZE(names))
++ return "UNDEFINED";
++
++ return names[state];
++}
++EXPORT_SYMBOL_GPL(usb_otg_state_string);
++
++static const char *const speed_names[] = {
++ [USB_SPEED_UNKNOWN] = "UNKNOWN",
++ [USB_SPEED_LOW] = "low-speed",
++ [USB_SPEED_FULL] = "full-speed",
++ [USB_SPEED_HIGH] = "high-speed",
++ [USB_SPEED_WIRELESS] = "wireless",
++ [USB_SPEED_SUPER] = "super-speed",
++};
++
++const char *usb_speed_string(enum usb_device_speed speed)
++{
++ if (speed < 0 || speed >= ARRAY_SIZE(speed_names))
++ speed = USB_SPEED_UNKNOWN;
++ return speed_names[speed];
++}
++EXPORT_SYMBOL_GPL(usb_speed_string);
++
++const char *usb_state_string(enum usb_device_state state)
++{
++ static const char *const names[] = {
++ [USB_STATE_NOTATTACHED] = "not attached",
++ [USB_STATE_ATTACHED] = "attached",
++ [USB_STATE_POWERED] = "powered",
++ [USB_STATE_RECONNECTING] = "reconnecting",
++ [USB_STATE_UNAUTHENTICATED] = "unauthenticated",
++ [USB_STATE_DEFAULT] = "default",
++ [USB_STATE_ADDRESS] = "addresssed",
++ [USB_STATE_CONFIGURED] = "configured",
++ [USB_STATE_SUSPENDED] = "suspended",
++ };
++
++ if (state < 0 || state >= ARRAY_SIZE(names))
++ return "UNKNOWN";
++
++ return names[state];
++}
++EXPORT_SYMBOL_GPL(usb_state_string);
++
++#ifdef CONFIG_OF
++static const char *const usb_dr_modes[] = {
++ [USB_DR_MODE_UNKNOWN] = "",
++ [USB_DR_MODE_HOST] = "host",
++ [USB_DR_MODE_PERIPHERAL] = "peripheral",
++ [USB_DR_MODE_OTG] = "otg",
++};
++
++/**
++ * of_usb_get_dr_mode - Get dual role mode for given device_node
++ * @np: Pointer to the given device_node
++ *
++ * The function gets phy interface string from property 'dr_mode',
++ * and returns the correspondig enum usb_dr_mode
++ */
++enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
++{
++ const char *dr_mode;
++ int err, i;
++
++ err = of_property_read_string(np, "dr_mode", &dr_mode);
++ if (err < 0)
++ return USB_DR_MODE_UNKNOWN;
++
++ for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
++ if (!strcmp(dr_mode, usb_dr_modes[i]))
++ return i;
++
++ return USB_DR_MODE_UNKNOWN;
++}
++EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
++
++/**
++ * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
++ * controller.
++ * @np: Pointer to the given device_node
++ *
++ * The function gets the maximum speed string from property "maximum-speed",
++ * and returns the corresponding enum usb_device_speed.
++ */
++enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
++{
++ const char *maximum_speed;
++ int err;
++ int i;
++
++ err = of_property_read_string(np, "maximum-speed", &maximum_speed);
++ if (err < 0)
++ return USB_SPEED_UNKNOWN;
++
++ for (i = 0; i < ARRAY_SIZE(speed_names); i++)
++ if (strcmp(maximum_speed, speed_names[i]) == 0)
++ return i;
++
++ return USB_SPEED_UNKNOWN;
++}
++EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
++
++/**
++ * of_usb_host_tpl_support - to get if Targeted Peripheral List is supported
++ * for given targeted hosts (non-PC hosts)
++ * @np: Pointer to the given device_node
++ *
++ * The function gets if the targeted hosts support TPL or not
++ */
++bool of_usb_host_tpl_support(struct device_node *np)
++{
++ if (of_find_property(np, "tpl-support", NULL))
++ return true;
++
++ return false;
++}
++EXPORT_SYMBOL_GPL(of_usb_host_tpl_support);
++#endif
++
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/usb/common/usb-otg-fsm.c linux-3.14.72/drivers/usb/common/usb-otg-fsm.c
+--- linux-3.14.72.orig/drivers/usb/common/usb-otg-fsm.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/common/usb-otg-fsm.c 2016-06-19 22:11:55.329138432 +0200
+@@ -0,0 +1,458 @@
++/*
++ * OTG Finite State Machine from OTG spec
++ *
++ * Copyright (C) 2007-2015 Freescale Semiconductor, Inc.
++ *
++ * Author: Li Yang <LeoLi@freescale.com>
++ * Jerry Huang <Chang-Ming.Huang@freescale.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ */
++
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/usb.h>
++#include <linux/usb/gadget.h>
++#include <linux/usb/otg.h>
++#include <linux/usb/otg-fsm.h>
++
++/* Change USB protocol when there is a protocol change */
++static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
++{
++ int ret = 0;
++
++ if (fsm->protocol != protocol) {
++ VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
++ fsm->protocol, protocol);
++ /* stop old protocol */
++ if (fsm->protocol == PROTO_HOST)
++ ret = otg_start_host(fsm, 0);
++ else if (fsm->protocol == PROTO_GADGET)
++ ret = otg_start_gadget(fsm, 0);
++ if (ret)
++ return ret;
++
++ /* start new protocol */
++ if (protocol == PROTO_HOST)
++ ret = otg_start_host(fsm, 1);
++ else if (protocol == PROTO_GADGET)
++ ret = otg_start_gadget(fsm, 1);
++ if (ret)
++ return ret;
++
++ fsm->protocol = protocol;
++ return 0;
++ }
++
++ return 0;
++}
++
++static int state_changed;
++
++/* Called when leaving a state. Do state clean up jobs here */
++static void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
++{
++ switch (old_state) {
++ case OTG_STATE_B_IDLE:
++ otg_del_timer(fsm, B_SE0_SRP);
++ fsm->b_se0_srp = 0;
++ fsm->adp_sns = 0;
++ fsm->adp_prb = 0;
++ break;
++ case OTG_STATE_B_SRP_INIT:
++ fsm->data_pulse = 0;
++ fsm->b_srp_done = 0;
++ break;
++ case OTG_STATE_B_PERIPHERAL:
++ if (fsm->otg->gadget)
++ fsm->otg->gadget->host_request_flag = 0;
++ break;
++ case OTG_STATE_B_WAIT_ACON:
++ otg_del_timer(fsm, B_ASE0_BRST);
++ fsm->b_ase0_brst_tmout = 0;
++ break;
++ case OTG_STATE_B_HOST:
++ break;
++ case OTG_STATE_A_IDLE:
++ fsm->adp_prb = 0;
++ break;
++ case OTG_STATE_A_WAIT_VRISE:
++ otg_del_timer(fsm, A_WAIT_VRISE);
++ fsm->a_wait_vrise_tmout = 0;
++ break;
++ case OTG_STATE_A_WAIT_BCON:
++ otg_del_timer(fsm, A_WAIT_BCON);
++ fsm->a_wait_bcon_tmout = 0;
++ break;
++ case OTG_STATE_A_HOST:
++ otg_del_timer(fsm, A_WAIT_ENUM);
++ break;
++ case OTG_STATE_A_SUSPEND:
++ otg_del_timer(fsm, A_AIDL_BDIS);
++ fsm->a_aidl_bdis_tmout = 0;
++ fsm->a_suspend_req_inf = 0;
++ break;
++ case OTG_STATE_A_PERIPHERAL:
++ otg_del_timer(fsm, A_BIDL_ADIS);
++ fsm->a_bidl_adis_tmout = 0;
++ if (fsm->otg->gadget)
++ fsm->otg->gadget->host_request_flag = 0;
++ break;
++ case OTG_STATE_A_WAIT_VFALL:
++ otg_del_timer(fsm, A_WAIT_VFALL);
++ fsm->a_wait_vfall_tmout = 0;
++ otg_del_timer(fsm, A_WAIT_VRISE);
++ break;
++ case OTG_STATE_A_VBUS_ERR:
++ break;
++ default:
++ break;
++ }
++}
++
++/* Called when entering a state */
++static int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
++{
++ state_changed = 1;
++ if (fsm->otg->state == new_state)
++ return 0;
++ VDBG("Set state: %s\n", usb_otg_state_string(new_state));
++ otg_leave_state(fsm, fsm->otg->state);
++ switch (new_state) {
++ case OTG_STATE_B_IDLE:
++ otg_drv_vbus(fsm, 0);
++ otg_chrg_vbus(fsm, 0);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ /*
++ * Driver is responsible for starting ADP probing
++ * if ADP sensing times out.
++ */
++ otg_start_adp_sns(fsm);
++ otg_set_protocol(fsm, PROTO_UNDEF);
++ otg_add_timer(fsm, B_SE0_SRP);
++ break;
++ case OTG_STATE_B_SRP_INIT:
++ otg_start_pulse(fsm);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_UNDEF);
++ otg_add_timer(fsm, B_SRP_FAIL);
++ break;
++ case OTG_STATE_B_PERIPHERAL:
++ otg_chrg_vbus(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_GADGET);
++ otg_loc_conn(fsm, 1);
++ break;
++ case OTG_STATE_B_WAIT_ACON:
++ otg_chrg_vbus(fsm, 0);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_HOST);
++ otg_add_timer(fsm, B_ASE0_BRST);
++ fsm->a_bus_suspend = 0;
++ break;
++ case OTG_STATE_B_HOST:
++ otg_chrg_vbus(fsm, 0);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 1);
++ otg_set_protocol(fsm, PROTO_HOST);
++ usb_bus_start_enum(fsm->otg->host,
++ fsm->otg->host->otg_port);
++ otg_add_timer(fsm, HNP_POLLING);
++ break;
++ case OTG_STATE_A_IDLE:
++ otg_drv_vbus(fsm, 0);
++ otg_chrg_vbus(fsm, 0);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_start_adp_prb(fsm);
++ otg_set_protocol(fsm, PROTO_HOST);
++ break;
++ case OTG_STATE_A_WAIT_VRISE:
++ otg_drv_vbus(fsm, 1);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_HOST);
++ otg_add_timer(fsm, A_WAIT_VRISE);
++ break;
++ case OTG_STATE_A_WAIT_BCON:
++ otg_drv_vbus(fsm, 1);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_HOST);
++ otg_add_timer(fsm, A_WAIT_BCON);
++ break;
++ case OTG_STATE_A_HOST:
++ otg_drv_vbus(fsm, 1);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 1);
++ otg_set_protocol(fsm, PROTO_HOST);
++ /*
++ * When HNP is triggered while a_bus_req = 0, a_host will
++ * suspend too fast to complete a_set_b_hnp_en
++ */
++ if (!fsm->a_bus_req || fsm->a_suspend_req_inf)
++ otg_add_timer(fsm, A_WAIT_ENUM);
++ otg_add_timer(fsm, HNP_POLLING);
++ break;
++ case OTG_STATE_A_SUSPEND:
++ otg_drv_vbus(fsm, 1);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_HOST);
++ otg_add_timer(fsm, A_AIDL_BDIS);
++
++ break;
++ case OTG_STATE_A_PERIPHERAL:
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_GADGET);
++ otg_drv_vbus(fsm, 1);
++ otg_loc_conn(fsm, 1);
++ otg_add_timer(fsm, A_BIDL_ADIS);
++ break;
++ case OTG_STATE_A_WAIT_VFALL:
++ otg_drv_vbus(fsm, 0);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_HOST);
++ otg_add_timer(fsm, A_WAIT_VFALL);
++ break;
++ case OTG_STATE_A_VBUS_ERR:
++ otg_drv_vbus(fsm, 0);
++ otg_loc_conn(fsm, 0);
++ otg_loc_sof(fsm, 0);
++ otg_set_protocol(fsm, PROTO_UNDEF);
++ break;
++ default:
++ break;
++ }
++
++ fsm->otg->state = new_state;
++ return 0;
++}
++
++/* State change judgement */
++int otg_statemachine(struct otg_fsm *fsm)
++{
++ enum usb_otg_state state;
++
++ mutex_lock(&fsm->lock);
++
++ state = fsm->otg->state;
++ state_changed = 0;
++ /* State machine state change judgement */
++
++ switch (state) {
++ case OTG_STATE_UNDEFINED:
++ VDBG("fsm->id = %d\n", fsm->id);
++ if (fsm->id)
++ otg_set_state(fsm, OTG_STATE_B_IDLE);
++ else
++ otg_set_state(fsm, OTG_STATE_A_IDLE);
++ break;
++ case OTG_STATE_B_IDLE:
++ if (!fsm->id)
++ otg_set_state(fsm, OTG_STATE_A_IDLE);
++ else if (fsm->b_sess_vld && fsm->otg->gadget)
++ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
++ else if ((fsm->b_bus_req || fsm->adp_change || fsm->power_up) &&
++ fsm->b_ssend_srp && fsm->b_se0_srp)
++ otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
++ break;
++ case OTG_STATE_B_SRP_INIT:
++ if (!fsm->id || fsm->b_srp_done)
++ otg_set_state(fsm, OTG_STATE_B_IDLE);
++ break;
++ case OTG_STATE_B_PERIPHERAL:
++ if (!fsm->id || !fsm->b_sess_vld)
++ otg_set_state(fsm, OTG_STATE_B_IDLE);
++ else if (fsm->b_bus_req && fsm->otg->
++ gadget->b_hnp_enable && fsm->a_bus_suspend)
++ otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
++ break;
++ case OTG_STATE_B_WAIT_ACON:
++ if (fsm->a_conn)
++ otg_set_state(fsm, OTG_STATE_B_HOST);
++ else if (!fsm->id || !fsm->b_sess_vld)
++ otg_set_state(fsm, OTG_STATE_B_IDLE);
++ else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
++ fsm->b_ase0_brst_tmout = 0;
++ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
++ }
++ break;
++ case OTG_STATE_B_HOST:
++ if (!fsm->id || !fsm->b_sess_vld)
++ otg_set_state(fsm, OTG_STATE_B_IDLE);
++ else if (!fsm->b_bus_req || !fsm->a_conn || fsm->test_device)
++ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
++ break;
++ case OTG_STATE_A_IDLE:
++ if (fsm->id)
++ otg_set_state(fsm, OTG_STATE_B_IDLE);
++ else if (!fsm->a_bus_drop && (fsm->a_bus_req ||
++ fsm->a_srp_det || fsm->adp_change || fsm->power_up))
++ otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
++ break;
++ case OTG_STATE_A_WAIT_VRISE:
++ if (fsm->a_vbus_vld)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
++ else if (fsm->id || fsm->a_bus_drop ||
++ fsm->a_wait_vrise_tmout)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
++ break;
++ case OTG_STATE_A_WAIT_BCON:
++ if (!fsm->a_vbus_vld)
++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
++ else if (fsm->b_conn)
++ otg_set_state(fsm, OTG_STATE_A_HOST);
++ else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
++ break;
++ case OTG_STATE_A_HOST:
++ if (fsm->id || fsm->a_bus_drop)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
++ else if ((!fsm->a_bus_req || fsm->a_suspend_req_inf) &&
++ fsm->otg->host->b_hnp_enable)
++ otg_set_state(fsm, OTG_STATE_A_SUSPEND);
++ else if (!fsm->b_conn)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
++ else if (!fsm->a_vbus_vld)
++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
++ break;
++ case OTG_STATE_A_SUSPEND:
++ if (!fsm->b_conn && fsm->otg->host->b_hnp_enable)
++ otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
++ else if (!fsm->b_conn && !fsm->otg->host->b_hnp_enable)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
++ else if (fsm->a_bus_req || fsm->b_bus_resume)
++ otg_set_state(fsm, OTG_STATE_A_HOST);
++ else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
++ else if (!fsm->a_vbus_vld)
++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
++ break;
++ case OTG_STATE_A_PERIPHERAL:
++ if (fsm->id || fsm->a_bus_drop)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
++ else if (fsm->a_bidl_adis_tmout || fsm->b_bus_suspend)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
++ else if (!fsm->a_vbus_vld)
++ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
++ break;
++ case OTG_STATE_A_WAIT_VFALL:
++ if (fsm->a_wait_vfall_tmout)
++ otg_set_state(fsm, OTG_STATE_A_IDLE);
++ break;
++ case OTG_STATE_A_VBUS_ERR:
++ if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
++ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
++ break;
++ default:
++ break;
++ }
++ mutex_unlock(&fsm->lock);
++
++ VDBG("quit statemachine, changed = %d\n", state_changed);
++ return state_changed;
++}
++EXPORT_SYMBOL_GPL(otg_statemachine);
++
++static int otg_handle_role_switch(struct otg_fsm *fsm, struct usb_device *udev)
++{
++ int err;
++ enum usb_otg_state state = fsm->otg->state;
++
++ if (state == OTG_STATE_A_HOST) {
++ /* Set b_hnp_enable */
++ if (!fsm->a_set_b_hnp_en) {
++ err = usb_control_msg(udev,
++ usb_sndctrlpipe(udev, 0),
++ USB_REQ_SET_FEATURE, 0,
++ USB_DEVICE_B_HNP_ENABLE,
++ 0, NULL, 0,
++ USB_CTRL_SET_TIMEOUT);
++ if (err < 0) {
++ /* Continue polling */
++ otg_add_timer(fsm, HNP_POLLING);
++ return 0;
++ } else {
++ fsm->a_set_b_hnp_en = 1;
++ }
++ }
++ fsm->a_bus_req = 0;
++ return HOST_REQUEST_FLAG;
++ } else if (state == OTG_STATE_B_HOST) {
++ fsm->b_bus_req = 0;
++ return HOST_REQUEST_FLAG;
++ }
++
++ return -EINVAL;
++}
++
++/*
++ * Called by host to poll peripheral if it wants to be host
++ * Return value:
++ * - host request flag(1) if the device wants to be host,
++ * - host request flag(0) if the device keeps peripheral role,
++ * - otherwise, error code.
++ */
++int otg_hnp_polling(struct otg_fsm *fsm)
++{
++ struct usb_device *udev;
++ u8 host_req_flag;
++ int retval;
++ enum usb_otg_state state = fsm->otg->state;
++
++ if (state != OTG_STATE_A_HOST && state != OTG_STATE_B_HOST)
++ return -EINVAL;
++
++ udev = usb_hub_find_child(fsm->otg->host->root_hub, 1);
++ if (!udev) {
++ dev_err(fsm->otg->host->controller,
++ "no usb dev connected, can't start HNP polling\n");
++ return -ENODEV;
++ }
++
++ /* Get host request flag from connected USB device */
++ retval = usb_control_msg(udev,
++ usb_rcvctrlpipe(udev, 0),
++ USB_REQ_GET_STATUS,
++ USB_DIR_IN | USB_RECIP_DEVICE,
++ 0,
++ OTG_STS_SELECTOR,
++ &host_req_flag,
++ 1,
++ USB_CTRL_GET_TIMEOUT);
++ if (retval == 1) {
++ if (host_req_flag == HOST_REQUEST_FLAG) {
++ retval = otg_handle_role_switch(fsm, udev);
++ } else if (host_req_flag == 0) {
++ /* Continue polling */
++ otg_add_timer(fsm, HNP_POLLING);
++ retval = 0;
++ } else {
++ dev_err(&udev->dev, "host request flag is invalid\n");
++ retval = -EINVAL;
++ }
++ } else {
++ dev_err(&udev->dev, "Get one byte OTG status failed\n");
++ retval = -EIO;
++ }
++ return retval;
++}
++EXPORT_SYMBOL_GPL(otg_hnp_polling);
+diff -Nur linux-3.14.72.orig/drivers/usb/core/hcd.c linux-3.14.72/drivers/usb/core/hcd.c
+--- linux-3.14.72.orig/drivers/usb/core/hcd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/core/hcd.c 2016-06-19 22:11:55.329138432 +0200
+@@ -42,6 +42,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/types.h>
+
++#include <linux/phy/phy.h>
+ #include <linux/usb.h>
+ #include <linux/usb/hcd.h>
+ #include <linux/usb/phy.h>
+@@ -2590,7 +2591,7 @@
+ int retval;
+ struct usb_device *rhdev;
+
+- if (IS_ENABLED(CONFIG_USB_PHY) && !hcd->phy) {
++ if (IS_ENABLED(CONFIG_USB_PHY) && !hcd->usb_phy) {
+ struct usb_phy *phy = usb_get_phy_dev(hcd->self.controller, 0);
+
+ if (IS_ERR(phy)) {
+@@ -2603,6 +2604,30 @@
+ usb_put_phy(phy);
+ return retval;
+ }
++ hcd->usb_phy = phy;
++ hcd->remove_phy = 1;
++ }
++ }
++
++ if (IS_ENABLED(CONFIG_GENERIC_PHY) && !hcd->phy) {
++ struct phy *phy = phy_get(hcd->self.controller, "usb");
++
++ if (IS_ERR(phy)) {
++ retval = PTR_ERR(phy);
++ if (retval == -EPROBE_DEFER)
++ goto err_phy;
++ } else {
++ retval = phy_init(phy);
++ if (retval) {
++ phy_put(phy);
++ goto err_phy;
++ }
++ retval = phy_power_on(phy);
++ if (retval) {
++ phy_exit(phy);
++ phy_put(phy);
++ goto err_phy;
++ }
+ hcd->phy = phy;
+ hcd->remove_phy = 1;
+ }
+@@ -2623,7 +2648,7 @@
+ */
+ if ((retval = hcd_buffer_create(hcd)) != 0) {
+ dev_dbg(hcd->self.controller, "pool alloc failed\n");
+- goto err_remove_phy;
++ goto err_create_buf;
+ }
+
+ if ((retval = usb_register_bus(&hcd->self)) < 0)
+@@ -2748,12 +2773,19 @@
+ usb_deregister_bus(&hcd->self);
+ err_register_bus:
+ hcd_buffer_destroy(hcd);
+-err_remove_phy:
+- if (hcd->remove_phy && hcd->phy) {
+- usb_phy_shutdown(hcd->phy);
+- usb_put_phy(hcd->phy);
++err_create_buf:
++ if (IS_ENABLED(CONFIG_GENERIC_PHY) && hcd->remove_phy && hcd->phy) {
++ phy_power_off(hcd->phy);
++ phy_exit(hcd->phy);
++ phy_put(hcd->phy);
+ hcd->phy = NULL;
+ }
++err_phy:
++ if (hcd->remove_phy && hcd->usb_phy) {
++ usb_phy_shutdown(hcd->usb_phy);
++ usb_put_phy(hcd->usb_phy);
++ hcd->usb_phy = NULL;
++ }
+ return retval;
+ }
+ EXPORT_SYMBOL_GPL(usb_add_hcd);
+@@ -2826,11 +2858,18 @@
+ usb_put_dev(hcd->self.root_hub);
+ usb_deregister_bus(&hcd->self);
+ hcd_buffer_destroy(hcd);
+- if (hcd->remove_phy && hcd->phy) {
+- usb_phy_shutdown(hcd->phy);
+- usb_put_phy(hcd->phy);
++
++ if (IS_ENABLED(CONFIG_GENERIC_PHY) && hcd->remove_phy && hcd->phy) {
++ phy_power_off(hcd->phy);
++ phy_exit(hcd->phy);
++ phy_put(hcd->phy);
+ hcd->phy = NULL;
+ }
++ if (hcd->remove_phy && hcd->usb_phy) {
++ usb_phy_shutdown(hcd->usb_phy);
++ usb_put_phy(hcd->usb_phy);
++ hcd->usb_phy = NULL;
++ }
+ }
+ EXPORT_SYMBOL_GPL(usb_remove_hcd);
+
+diff -Nur linux-3.14.72.orig/drivers/usb/core/hub.c linux-3.14.72/drivers/usb/core/hub.c
+--- linux-3.14.72.orig/drivers/usb/core/hub.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/core/hub.c 2016-06-19 22:11:55.329138432 +0200
+@@ -32,6 +32,7 @@
+ #include <asm/byteorder.h>
+
+ #include "hub.h"
++#include "otg_whitelist.h"
+
+ #define USB_VENDOR_GENESYS_LOGIC 0x05e3
+ #define HUB_QUIRK_CHECK_PORT_AUTOSUSPEND 0x01
+@@ -2161,9 +2162,6 @@
+ static inline void announce_device(struct usb_device *udev) { }
+ #endif
+
+-#ifdef CONFIG_USB_OTG
+-#include "otg_whitelist.h"
+-#endif
+
+ /**
+ * usb_enumerate_device_otg - FIXME (usbcore-internal)
+@@ -2223,21 +2221,6 @@
+ }
+ }
+ }
+-
+- if (!is_targeted(udev)) {
+-
+- /* Maybe it can talk to us, though we can't talk to it.
+- * (Includes HNP test device.)
+- */
+- if (udev->bus->b_hnp_enable || udev->bus->is_b_host) {
+- err = usb_port_suspend(udev, PMSG_SUSPEND);
+- if (err < 0)
+- dev_dbg(&udev->dev, "HNP fail, %d\n", err);
+- }
+- err = -ENOTSUPP;
+- goto fail;
+- }
+-fail:
+ #endif
+ return err;
+ }
+@@ -2260,6 +2243,7 @@
+ static int usb_enumerate_device(struct usb_device *udev)
+ {
+ int err;
++ struct usb_hcd *hcd = bus_to_hcd(udev->bus);
+
+ if (udev->config == NULL) {
+ err = usb_get_configuration(udev);
+@@ -2281,6 +2265,20 @@
+ if (err < 0)
+ return err;
+
++ if (IS_ENABLED(CONFIG_USB_OTG_WHITELIST) && hcd->tpl_support &&
++ !is_targeted(udev)) {
++ /* Maybe it can talk to us, though we can't talk to it.
++ * (Includes HNP test device.)
++ */
++ if (IS_ENABLED(CONFIG_USB_OTG) && (udev->bus->b_hnp_enable
++ || udev->bus->is_b_host)) {
++ err = usb_port_suspend(udev, PMSG_AUTO_SUSPEND);
++ if (err < 0)
++ dev_dbg(&udev->dev, "HNP fail, %d\n", err);
++ }
++ return -ENOTSUPP;
++ }
++
+ usb_detect_interface_quirks(udev);
+
+ return 0;
+@@ -4311,9 +4309,6 @@
+ if (retval)
+ goto fail;
+
+- if (hcd->phy && !hdev->parent)
+- usb_phy_notify_connect(hcd->phy, udev->speed);
+-
+ /*
+ * Some superspeed devices have finished the link training process
+ * and attached to a superspeed hub port, but the device descriptor
+@@ -4524,9 +4519,8 @@
+
+ /* Disconnect any existing devices under this port */
+ if (udev) {
+- if (hcd->phy && !hdev->parent &&
+- !(portstatus & USB_PORT_STAT_CONNECTION))
+- usb_phy_notify_disconnect(hcd->phy, udev->speed);
++ if (hcd->usb_phy && !hdev->parent)
++ usb_phy_notify_disconnect(hcd->usb_phy, udev->speed);
+ usb_disconnect(&hub->ports[port1 - 1]->child);
+ }
+ clear_bit(port1, hub->change_bits);
+@@ -4670,6 +4664,10 @@
+ spin_lock_irq(&device_state_lock);
+ hub->ports[port1 - 1]->child = NULL;
+ spin_unlock_irq(&device_state_lock);
++ } else {
++ if (hcd->usb_phy && !hdev->parent)
++ usb_phy_notify_connect(hcd->usb_phy,
++ udev->speed);
+ }
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/usb/core/Kconfig linux-3.14.72/drivers/usb/core/Kconfig
+--- linux-3.14.72.orig/drivers/usb/core/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/core/Kconfig 2016-06-19 22:11:55.329138432 +0200
+@@ -64,22 +64,16 @@
+ connector.
+
+ config USB_OTG_WHITELIST
+- bool "Rely on OTG Targeted Peripherals List"
+- depends on USB_OTG || EXPERT
+- default y if USB_OTG
++ bool "Rely on OTG and EH Targeted Peripherals List"
++ depends on USB
+ help
+ If you say Y here, the "otg_whitelist.h" file will be used as a
+ product whitelist, so USB peripherals not listed there will be
+ rejected during enumeration. This behavior is required by the
+- USB OTG specification for all devices not on your product's
++ USB OTG and EH specification for all devices not on your product's
+ "Targeted Peripherals List". "Embedded Hosts" are likewise
+ allowed to support only a limited number of peripherals.
+
+- Otherwise, peripherals not listed there will only generate a
+- warning and enumeration will continue. That's more like what
+- normal Linux-USB hosts do (other than the warning), and is
+- convenient for many stages of product development.
+-
+ config USB_OTG_BLACKLIST_HUB
+ bool "Disable external hubs"
+ depends on USB_OTG || EXPERT
+@@ -89,3 +83,12 @@
+ and software costs by not supporting external hubs. So
+ are "Embedded Hosts" that don't offer OTG support.
+
++config USB_OTG_FSM
++ tristate "USB 2.0 OTG FSM implementation"
++ depends on USB
++ select USB_OTG
++ select USB_PHY
++ help
++ Implements OTG Finite State Machine as specified in On-The-Go
++ and Embedded Host Supplement to the USB Revision 2.0 Specification.
++
+diff -Nur linux-3.14.72.orig/drivers/usb/core/otg_whitelist.h linux-3.14.72/drivers/usb/core/otg_whitelist.h
+--- linux-3.14.72.orig/drivers/usb/core/otg_whitelist.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/core/otg_whitelist.h 2016-06-19 22:11:55.329138432 +0200
+@@ -10,50 +10,73 @@
+ */
+
+ /*
+- * This OTG Whitelist is the OTG "Targeted Peripheral List". It should
+- * mostly use of USB_DEVICE() or USB_DEVICE_VER() entries..
++ * This OTG and Embedded Host Whitelist is "Targeted Peripheral List".
++ * It should mostly use of USB_DEVICE() or USB_DEVICE_VER() entries..
+ *
+ * YOU _SHOULD_ CHANGE THIS LIST TO MATCH YOUR PRODUCT AND ITS TESTING!
+ */
+
+ static struct usb_device_id whitelist_table [] = {
+-
+-/* hubs are optional in OTG, but very handy ... */
+-{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), },
+-{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), },
+-
+-#ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */
+-/* FIXME actually, printers are NOT supposed to use device classes;
+- * they're supposed to use interface classes...
+- */
+-{ USB_DEVICE_INFO(7, 1, 1) },
+-{ USB_DEVICE_INFO(7, 1, 2) },
+-{ USB_DEVICE_INFO(7, 1, 3) },
++/* Add FSL i.mx whitelist, the default list is for USB Compliance Test */
++#if defined(CONFIG_USB_EHSET_TEST_FIXTURE) \
++ || defined(CONFIG_USB_EHSET_TEST_FIXTURE_MODULE)
++#define TEST_SE0_NAK_PID 0x0101
++#define TEST_J_PID 0x0102
++#define TEST_K_PID 0x0103
++#define TEST_PACKET_PID 0x0104
++#define TEST_HS_HOST_PORT_SUSPEND_RESUME 0x0106
++#define TEST_SINGLE_STEP_GET_DEV_DESC 0x0107
++#define TEST_SINGLE_STEP_SET_FEATURE 0x0108
++{ USB_DEVICE(0x1a0a, TEST_SE0_NAK_PID) },
++{ USB_DEVICE(0x1a0a, TEST_J_PID) },
++{ USB_DEVICE(0x1a0a, TEST_K_PID) },
++{ USB_DEVICE(0x1a0a, TEST_PACKET_PID) },
++{ USB_DEVICE(0x1a0a, TEST_HS_HOST_PORT_SUSPEND_RESUME) },
++{ USB_DEVICE(0x1a0a, TEST_SINGLE_STEP_GET_DEV_DESC) },
++{ USB_DEVICE(0x1a0a, TEST_SINGLE_STEP_SET_FEATURE) },
+ #endif
+
+-#ifdef CONFIG_USB_NET_CDCETHER
+-/* Linux-USB CDC Ethernet gadget */
+-{ USB_DEVICE(0x0525, 0xa4a1), },
+-/* Linux-USB CDC Ethernet + RNDIS gadget */
+-{ USB_DEVICE(0x0525, 0xa4a2), },
++#define USB_INTERFACE_CLASS_INFO(cl) \
++ .match_flags = USB_DEVICE_ID_MATCH_INT_CLASS, \
++ .bInterfaceClass = (cl)
++
++{USB_INTERFACE_CLASS_INFO(USB_CLASS_HUB) },
++#if defined(CONFIG_USB_STORAGE) || defined(CONFIG_USB_STORAGE_MODULE)
++{USB_INTERFACE_CLASS_INFO(USB_CLASS_MASS_STORAGE) },
+ #endif
+-
+-#if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE)
+-/* gadget zero, for testing */
+-{ USB_DEVICE(0x0525, 0xa4a0), },
++#if defined(CONFIG_USB_HID) || defined(CONFIG_USB_HID_MODULE)
++{USB_INTERFACE_CLASS_INFO(USB_CLASS_HID) },
+ #endif
+
+ { } /* Terminating entry */
+ };
+
++static bool match_int_class(struct usb_device_id *id, struct usb_device *udev)
++{
++ struct usb_host_config *c;
++ int num_configs, i;
++
++ /* Copy the code from generic.c */
++ c = udev->config;
++ num_configs = udev->descriptor.bNumConfigurations;
++ for (i = 0; i < num_configs; (i++, c++)) {
++ struct usb_interface_descriptor *desc = NULL;
++
++ /* It's possible that a config has no interfaces! */
++ if (c->desc.bNumInterfaces > 0)
++ desc = &c->intf_cache[0]->altsetting->desc;
++
++ if (desc && (desc->bInterfaceClass == id->bInterfaceClass))
++ return true;
++ }
++
++ return false;
++}
++
+ static int is_targeted(struct usb_device *dev)
+ {
+ struct usb_device_id *id = whitelist_table;
+
+- /* possible in developer configs only! */
+- if (!dev->bus->otg_port)
+- return 1;
+-
+ /* HNP test device is _never_ targeted (see OTG spec 6.6.6) */
+ if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a &&
+ le16_to_cpu(dev->descriptor.idProduct) == 0xbadd))
+@@ -93,6 +116,10 @@
+ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol))
+ continue;
+
++ if ((id->match_flags & USB_DEVICE_ID_MATCH_INT_CLASS) &&
++ (!match_int_class(id, dev)))
++ continue;
++
+ return 1;
+ }
+
+@@ -103,10 +130,7 @@
+ dev_err(&dev->dev, "device v%04x p%04x is not supported\n",
+ le16_to_cpu(dev->descriptor.idVendor),
+ le16_to_cpu(dev->descriptor.idProduct));
+-#ifdef CONFIG_USB_OTG_WHITELIST
++
+ return 0;
+-#else
+- return 1;
+-#endif
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/acm_ms.c linux-3.14.72/drivers/usb/gadget/acm_ms.c
+--- linux-3.14.72.orig/drivers/usb/gadget/acm_ms.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/acm_ms.c 2016-06-19 22:11:55.329138432 +0200
+@@ -275,7 +275,7 @@
+ {
+ return usb_composite_probe(&acm_ms_driver);
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/audio.c linux-3.14.72/drivers/usb/gadget/audio.c
+--- linux-3.14.72.orig/drivers/usb/gadget/audio.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/audio.c 2016-06-19 22:11:55.329138432 +0200
+@@ -176,7 +176,7 @@
+ {
+ return usb_composite_probe(&audio_driver);
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/cdc2.c linux-3.14.72/drivers/usb/gadget/cdc2.c
+--- linux-3.14.72.orig/drivers/usb/gadget/cdc2.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/cdc2.c 2016-06-19 22:11:55.329138432 +0200
+@@ -239,7 +239,7 @@
+ {
+ return usb_composite_probe(&cdc_driver);
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/composite.c linux-3.14.72/drivers/usb/gadget/composite.c
+--- linux-3.14.72.orig/drivers/usb/gadget/composite.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/composite.c 2016-06-19 22:11:55.329138432 +0200
+@@ -634,6 +634,7 @@
+ if (!c)
+ goto done;
+
++ usb_gadget_set_state(gadget, USB_STATE_CONFIGURED);
+ cdev->config = c;
+
+ /* Initialize all interfaces by setting them to altsetting zero. */
+@@ -1648,6 +1649,7 @@
+ }
+ if (cdev->req) {
+ kfree(cdev->req->buf);
++ usb_ep_dequeue(cdev->gadget->ep0, cdev->req);
+ usb_ep_free_request(cdev->gadget->ep0, cdev->req);
+ }
+ cdev->next_string_id = 0;
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/configfs.c linux-3.14.72/drivers/usb/gadget/configfs.c
+--- linux-3.14.72.orig/drivers/usb/gadget/configfs.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/configfs.c 2016-06-19 22:11:55.329138432 +0200
+@@ -794,7 +794,7 @@
+ ret = -EINVAL;
+
+ if (list_empty(&gi->cdev.configs)) {
+- pr_err("Need atleast one configuration in %s.\n",
++ pr_err("Need at least one configuration in %s.\n",
+ gi->composite.name);
+ goto err_comp_cleanup;
+ }
+@@ -805,7 +805,7 @@
+
+ cfg = container_of(c, struct config_usb_cfg, c);
+ if (list_empty(&cfg->func_list)) {
+- pr_err("Config %s/%d of %s needs atleast one function.\n",
++ pr_err("Config %s/%d of %s needs at least one function.\n",
+ c->label, c->bConfigurationValue,
+ gi->composite.name);
+ goto err_comp_cleanup;
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/ether.c linux-3.14.72/drivers/usb/gadget/ether.c
+--- linux-3.14.72.orig/drivers/usb/gadget/ether.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/ether.c 2016-06-19 22:11:55.329138432 +0200
+@@ -179,6 +179,7 @@
+ * it would not be called "OTG" ...
+ */
+ .bmAttributes = USB_OTG_SRP | USB_OTG_HNP,
++ .bcdOTG = cpu_to_le16(0x0200),
+ };
+
+ static const struct usb_descriptor_header *otg_desc[] = {
+@@ -483,7 +484,7 @@
+ {
+ return usb_composite_probe(&eth_driver);
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/f_mass_storage.c linux-3.14.72/drivers/usb/gadget/f_mass_storage.c
+--- linux-3.14.72.orig/drivers/usb/gadget/f_mass_storage.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/f_mass_storage.c 2016-06-19 22:11:55.333138169 +0200
+@@ -336,8 +336,15 @@
+
+ struct usb_ep *bulk_in;
+ struct usb_ep *bulk_out;
++#ifdef CONFIG_FSL_UTP
++ void *utp;
++#endif
+ };
+
++#ifdef CONFIG_FSL_UTP
++#include "fsl_updater.h"
++#endif
++
+ static inline int __fsg_is_set(struct fsg_common *common,
+ const char *func, unsigned line)
+ {
+@@ -1131,6 +1138,13 @@
+ }
+ #endif
+
++#ifdef CONFIG_FSL_UTP
++ if (utp_get_sense(common->fsg) == 0) { /* got the sense from the UTP */
++ sd = UTP_CTX(common->fsg)->sd;
++ sdinfo = UTP_CTX(common->fsg)->sdinfo;
++ valid = 0;
++ } else
++#endif
+ if (!curlun) { /* Unsupported LUNs are okay */
+ common->bad_lun_okay = 1;
+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED;
+@@ -1152,6 +1166,9 @@
+ buf[7] = 18 - 8; /* Additional sense length */
+ buf[12] = ASC(sd);
+ buf[13] = ASCQ(sd);
++#ifdef CONFIG_FSL_UTP
++ put_unaligned_be32(UTP_CTX(common->fsg)->sdinfo_h, &buf[8]);
++#endif
+ return 18;
+ }
+
+@@ -1645,7 +1662,18 @@
+ sd = SS_INVALID_COMMAND;
+ } else if (sd != SS_NO_SENSE) {
+ DBG(common, "sending command-failure status\n");
++#ifdef CONFIG_FSL_UTP
++/*
++ * mfgtool host frequently reset bus during transfer
++ * - the response in csw to request sense will be 1 due to UTP change
++ * some storage information
++ * - host will reset the bus if response to request sense is 1
++ * - change the response to 0 if CONFIG_FSL_UTP is defined
++ */
++ status = US_BULK_STAT_OK;
++#else
+ status = US_BULK_STAT_FAIL;
++#endif
+ VDBG(common, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;"
+ " info x%x\n",
+ SK(sd), ASC(sd), ASCQ(sd), sdinfo);
+@@ -1836,6 +1864,13 @@
+ common->phase_error = 0;
+ common->short_packet_received = 0;
+
++#ifdef CONFIG_FSL_UTP
++ reply = utp_handle_message(common->fsg, common->cmnd, reply);
++
++ if (reply != -EINVAL)
++ return reply;
++#endif
++
+ down_read(&common->filesem); /* We're using the backing file */
+ switch (common->cmnd[0]) {
+
+@@ -2502,12 +2537,14 @@
+ /* Allow the thread to be frozen */
+ set_freezable();
+
++#ifndef CONFIG_FSL_UTP
+ /*
+ * Arrange for userspace references to be interpreted as kernel
+ * pointers. That way we can pass a kernel pointer to a routine
+ * that expects a __user pointer and it will work okay.
+ */
+ set_fs(get_ds());
++#endif
+
+ /* The main loop */
+ while (common->state != FSG_STATE_TERMINATED) {
+@@ -3096,6 +3133,10 @@
+
+ /*-------------------------------------------------------------------------*/
+
++#ifdef CONFIG_FSL_UTP
++#include "fsl_updater.c"
++#endif
++
+ static int fsg_bind(struct usb_configuration *c, struct usb_function *f)
+ {
+ struct fsg_dev *fsg = fsg_from_func(f);
+@@ -3127,6 +3168,10 @@
+ fsg_intf_desc.bInterfaceNumber = i;
+ fsg->interface_number = i;
+
++#ifdef CONFIG_FSL_UTP
++ utp_init(fsg);
++#endif
++
+ /* Find all the endpoints we will use */
+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc);
+ if (!ep)
+@@ -3185,6 +3230,11 @@
+ }
+
+ usb_free_all_descriptors(&fsg->function);
++
++#ifdef CONFIG_FSL_UTP
++ utp_exit(fsg);
++#endif
++
+ }
+
+ static inline struct fsg_lun_opts *to_fsg_lun_opts(struct config_item *item)
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/fsl_updater.c linux-3.14.72/drivers/usb/gadget/fsl_updater.c
+--- linux-3.14.72.orig/drivers/usb/gadget/fsl_updater.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/gadget/fsl_updater.c 2016-06-19 22:11:55.333138169 +0200
+@@ -0,0 +1,594 @@
++/*
++ * Freescale UUT driver
++ *
++ * Copyright 2008-2014 Freescale Semiconductor, Inc.
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++static u64 get_be64(u8 *buf)
++{
++ return ((u64)get_unaligned_be32(buf) << 32) |
++ get_unaligned_be32(buf + 4);
++}
++
++static int utp_init(struct fsg_dev *fsg)
++{
++ init_waitqueue_head(&utp_context.wq);
++ init_waitqueue_head(&utp_context.list_full_wq);
++
++ INIT_LIST_HEAD(&utp_context.read);
++ INIT_LIST_HEAD(&utp_context.write);
++ mutex_init(&utp_context.lock);
++
++ /* the max message is 64KB */
++ utp_context.buffer = vmalloc(0x10000);
++ if (!utp_context.buffer)
++ return -EIO;
++ utp_context.utp_version = 0x1ull;
++ fsg->utp = &utp_context;
++ return misc_register(&utp_dev);
++}
++
++static void utp_exit(struct fsg_dev *fsg)
++{
++ vfree(utp_context.buffer);
++ misc_deregister(&utp_dev);
++}
++
++static struct utp_user_data *utp_user_data_alloc(size_t size)
++{
++ struct utp_user_data *uud;
++
++ uud = vmalloc(size + sizeof(*uud));
++ if (!uud)
++ return uud;
++ memset(uud, 0, size + sizeof(*uud));
++ uud->data.size = size + sizeof(uud->data);
++ INIT_LIST_HEAD(&uud->link);
++ return uud;
++}
++
++static void utp_user_data_free(struct utp_user_data *uud)
++{
++ mutex_lock(&utp_context.lock);
++ list_del(&uud->link);
++ mutex_unlock(&utp_context.lock);
++ vfree(uud);
++}
++
++/* Get the number of element for list */
++static u32 count_list(struct list_head *l)
++{
++ u32 count = 0;
++ struct list_head *tmp;
++
++ mutex_lock(&utp_context.lock);
++ list_for_each(tmp, l) {
++ count++;
++ }
++ mutex_unlock(&utp_context.lock);
++
++ return count;
++}
++/* The routine will not go on if utp_context.queue is empty */
++#define WAIT_ACTIVITY(queue) \
++ wait_event_interruptible(utp_context.wq, !list_empty(&utp_context.queue))
++
++/* Called by userspace program (uuc) */
++static ssize_t utp_file_read(struct file *file,
++ char __user *buf,
++ size_t size,
++ loff_t *off)
++{
++ struct utp_user_data *uud;
++ size_t size_to_put;
++ int free = 0;
++
++ WAIT_ACTIVITY(read);
++
++ mutex_lock(&utp_context.lock);
++ uud = list_first_entry(&utp_context.read, struct utp_user_data, link);
++ mutex_unlock(&utp_context.lock);
++ size_to_put = uud->data.size;
++
++ if (size >= size_to_put)
++ free = !0;
++ if (copy_to_user(buf, &uud->data, size_to_put)) {
++ printk(KERN_INFO "[ %s ] copy error\n", __func__);
++ return -EACCES;
++ }
++ if (free)
++ utp_user_data_free(uud);
++ else {
++ pr_info("sizeof = %d, size = %d\n",
++ sizeof(uud->data),
++ uud->data.size);
++
++ pr_err("Will not free utp_user_data, because buffer size = %d,"
++ "need to put %d\n", size, size_to_put);
++ }
++
++ /*
++ * The user program has already finished data process,
++ * go on getting data from the host
++ */
++ wake_up(&utp_context.list_full_wq);
++
++ return size_to_put;
++}
++
++static ssize_t utp_file_write(struct file *file, const char __user *buf,
++ size_t size, loff_t *off)
++{
++ struct utp_user_data *uud;
++
++ if (size < sizeof(uud->data))
++ return -EINVAL;
++ uud = utp_user_data_alloc(size);
++ if (uud == NULL)
++ return -ENOMEM;
++ if (copy_from_user(&uud->data, buf, size)) {
++ printk(KERN_INFO "[ %s ] copy error!\n", __func__);
++ vfree(uud);
++ return -EACCES;
++ }
++ mutex_lock(&utp_context.lock);
++ list_add_tail(&uud->link, &utp_context.write);
++ /* Go on EXEC routine process */
++ wake_up(&utp_context.wq);
++ mutex_unlock(&utp_context.lock);
++ return size;
++}
++
++/*
++ * uuc should change to use soc bus infrastructure to soc information
++ * /sys/devices/soc0/soc_id
++ * this function can be removed.
++ */
++static long
++utp_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ int cpu_id = 0;
++
++ switch (cmd) {
++ case UTP_GET_CPU_ID:
++ return put_user(cpu_id, (int __user *)arg);
++ default:
++ return -ENOIOCTLCMD;
++ }
++}
++
++/* Will be called when the host wants to get the sense data */
++static int utp_get_sense(struct fsg_dev *fsg)
++{
++ if (UTP_CTX(fsg)->processed == 0)
++ return -1;
++
++ UTP_CTX(fsg)->processed = 0;
++ return 0;
++}
++
++static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size)
++{
++ struct fsg_buffhd *bh;
++ int rc;
++ u32 amount_left;
++ unsigned int amount;
++
++ /* Get the starting Logical Block Address and check that it's
++ * not too big */
++
++ amount_left = size;
++ if (unlikely(amount_left == 0))
++ return -EIO; /* No default reply*/
++
++ pr_debug("%s: sending %d\n", __func__, size);
++ for (;;) {
++ /* Figure out how much we need to read:
++ * Try to read the remaining amount.
++ * But don't read more than the buffer size.
++ * And don't try to read past the end of the file.
++ * Finally, if we're not at a page boundary, don't read past
++ * the next page.
++ * If this means reading 0 then we were asked to read past
++ * the end of file. */
++ amount = min((unsigned int) amount_left, FSG_BUFLEN);
++
++ /* Wait for the next buffer to become available */
++ bh = fsg->common->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg->common, true);
++ if (rc)
++ return rc;
++ }
++
++ /* If we were asked to read past the end of file,
++ * end with an empty buffer. */
++ if (amount == 0) {
++ bh->inreq->length = 0;
++ bh->state = BUF_STATE_FULL;
++ break;
++ }
++
++ /* Perform the read */
++ pr_info("Copied to %p, %d bytes started from %d\n",
++ bh->buf, amount, size - amount_left);
++ /* from upt buffer to file_storeage buffer */
++ memcpy(bh->buf, data + size - amount_left, amount);
++ amount_left -= amount;
++ fsg->common->residue -= amount;
++
++ bh->inreq->length = amount;
++ bh->state = BUF_STATE_FULL;
++
++ /* Send this buffer and go read some more */
++ bh->inreq->zero = 0;
++
++ /* USB Physical transfer: Data from device to host */
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++
++ fsg->common->next_buffhd_to_fill = bh->next;
++
++ if (amount_left <= 0)
++ break;
++ }
++
++ return size - amount_left;
++}
++
++static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size)
++{
++ struct fsg_buffhd *bh;
++ int get_some_more;
++ u32 amount_left_to_req, amount_left_to_write;
++ unsigned int amount;
++ int rc;
++ loff_t offset;
++
++ /* Carry out the file writes */
++ get_some_more = 1;
++ amount_left_to_req = amount_left_to_write = size;
++
++ if (unlikely(amount_left_to_write == 0))
++ return -EIO;
++
++ offset = 0;
++ while (amount_left_to_write > 0) {
++
++ /* Queue a request for more data from the host */
++ bh = fsg->common->next_buffhd_to_fill;
++ if (bh->state == BUF_STATE_EMPTY && get_some_more) {
++
++ /* Figure out how much we want to get:
++ * Try to get the remaining amount.
++ * But don't get more than the buffer size.
++ * And don't try to go past the end of the file.
++ * If we're not at a page boundary,
++ * don't go past the next page.
++ * If this means getting 0, then we were asked
++ * to write past the end of file.
++ * Finally, round down to a block boundary. */
++ amount = min(amount_left_to_req, FSG_BUFLEN);
++
++ if (amount == 0) {
++ get_some_more = 0;
++ /* cry now */
++ continue;
++ }
++
++ /* Get the next buffer */
++ amount_left_to_req -= amount;
++ if (amount_left_to_req == 0)
++ get_some_more = 0;
++
++ /* amount is always divisible by 512, hence by
++ * the bulk-out maxpacket size */
++ bh->outreq->length = bh->bulk_out_intended_length =
++ amount;
++ bh->outreq->short_not_ok = 1;
++ start_transfer(fsg, fsg->bulk_out, bh->outreq,
++ &bh->outreq_busy, &bh->state);
++ fsg->common->next_buffhd_to_fill = bh->next;
++ continue;
++ }
++
++ /* Write the received data to the backing file */
++ bh = fsg->common->next_buffhd_to_drain;
++ if (bh->state == BUF_STATE_EMPTY && !get_some_more)
++ break; /* We stopped early */
++ if (bh->state == BUF_STATE_FULL) {
++ smp_rmb();
++ fsg->common->next_buffhd_to_drain = bh->next;
++ bh->state = BUF_STATE_EMPTY;
++
++ /* Did something go wrong with the transfer? */
++ if (bh->outreq->status != 0)
++ /* cry again, COMMUNICATION_FAILURE */
++ break;
++
++ amount = bh->outreq->actual;
++
++ /* Perform the write */
++ memcpy(data + offset, bh->buf, amount);
++
++ offset += amount;
++ if (signal_pending(current))
++ return -EINTR; /* Interrupted!*/
++ amount_left_to_write -= amount;
++ fsg->common->residue -= amount;
++
++ /* Did the host decide to stop early? */
++ if (bh->outreq->actual != bh->outreq->length) {
++ fsg->common->short_packet_received = 1;
++ break;
++ }
++ continue;
++ }
++
++ /* Wait for something to happen */
++ rc = sleep_thread(fsg->common, true);
++ if (rc)
++ return rc;
++ }
++
++ return -EIO;
++}
++
++static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply)
++{
++ UTP_CTX(fsg)->processed = true;
++ UTP_CTX(fsg)->sdinfo = reply & 0xFFFFFFFF;
++ UTP_CTX(fsg)->sdinfo_h = (reply >> 32) & 0xFFFFFFFF;
++ UTP_CTX(fsg)->sd = (UTP_SENSE_KEY << 16) | code;
++}
++
++static void utp_poll(struct fsg_dev *fsg)
++{
++ struct utp_context *ctx = UTP_CTX(fsg);
++ struct utp_user_data *uud = NULL;
++
++ mutex_lock(&ctx->lock);
++ if (!list_empty(&ctx->write))
++ uud = list_first_entry(&ctx->write, struct utp_user_data, link);
++ mutex_unlock(&ctx->lock);
++
++ if (uud) {
++ if (uud->data.flags & UTP_FLAG_STATUS) {
++ printk(KERN_WARNING "%s: exit with status %d\n",
++ __func__, uud->data.status);
++ UTP_SS_EXIT(fsg, uud->data.status);
++ } else if (uud->data.flags & UTP_FLAG_REPORT_BUSY) {
++ UTP_SS_BUSY(fsg, --ctx->counter);
++ } else {
++ printk("%s: pass returned.\n", __func__);
++ UTP_SS_PASS(fsg);
++ }
++ utp_user_data_free(uud);
++ } else {
++ if (utp_context.cur_state & UTP_FLAG_DATA) {
++ if (count_list(&ctx->read) < 7) {
++ pr_debug("%s: pass returned in POLL stage. \n", __func__);
++ UTP_SS_PASS(fsg);
++ utp_context.cur_state = 0;
++ return;
++ }
++ }
++ UTP_SS_BUSY(fsg, --ctx->counter);
++ }
++}
++
++static int utp_exec(struct fsg_dev *fsg,
++ char *command,
++ int cmdsize,
++ unsigned long long payload)
++{
++ struct utp_user_data *uud = NULL, *uud2r;
++ struct utp_context *ctx = UTP_CTX(fsg);
++
++ ctx->counter = 0xFFFF;
++ uud2r = utp_user_data_alloc(cmdsize + 1);
++ if (!uud2r)
++ return -ENOMEM;
++ uud2r->data.flags = UTP_FLAG_COMMAND;
++ uud2r->data.payload = payload;
++ strncpy(uud2r->data.command, command, cmdsize);
++
++ mutex_lock(&ctx->lock);
++ list_add_tail(&uud2r->link, &ctx->read);
++ mutex_unlock(&ctx->lock);
++ /* wake up the read routine */
++ wake_up(&ctx->wq);
++
++ if (command[0] == '!') /* there will be no response */
++ return 0;
++
++ /*
++ * the user program (uuc) will return utp_message
++ * and add list to write list
++ */
++ WAIT_ACTIVITY(write);
++
++ mutex_lock(&ctx->lock);
++ if (!list_empty(&ctx->write)) {
++ uud = list_first_entry(&ctx->write, struct utp_user_data, link);
++#ifdef DEBUG
++ pr_info("UUD:\n\tFlags = %02X\n", uud->data.flags);
++ if (uud->data.flags & UTP_FLAG_DATA) {
++ pr_info("\tbufsize = %d\n", uud->data.bufsize);
++ print_hex_dump(KERN_DEBUG, "\t", DUMP_PREFIX_NONE,
++ 16, 2, uud->data.data, uud->data.bufsize, true);
++ }
++ if (uud->data.flags & UTP_FLAG_REPORT_BUSY)
++ pr_info("\tBUSY\n");
++#endif
++ }
++ mutex_unlock(&ctx->lock);
++
++ if (uud->data.flags & UTP_FLAG_DATA) {
++ memcpy(ctx->buffer, uud->data.data, uud->data.bufsize);
++ UTP_SS_SIZE(fsg, uud->data.bufsize);
++ } else if (uud->data.flags & UTP_FLAG_REPORT_BUSY) {
++ UTP_SS_BUSY(fsg, ctx->counter);
++ } else if (uud->data.flags & UTP_FLAG_STATUS) {
++ printk(KERN_WARNING "%s: exit with status %d\n", __func__,
++ uud->data.status);
++ UTP_SS_EXIT(fsg, uud->data.status);
++ } else {
++ pr_debug("%s: pass returned in EXEC stage. \n", __func__);
++ UTP_SS_PASS(fsg);
++ }
++ utp_user_data_free(uud);
++ return 0;
++}
++
++static int utp_send_status(struct fsg_dev *fsg)
++{
++ struct fsg_buffhd *bh;
++ u8 status = US_BULK_STAT_OK;
++ struct bulk_cs_wrap *csw;
++ int rc;
++
++ /* Wait for the next buffer to become available */
++ bh = fsg->common->next_buffhd_to_fill;
++ while (bh->state != BUF_STATE_EMPTY) {
++ rc = sleep_thread(fsg->common, true);
++ if (rc)
++ return rc;
++ }
++
++ if (fsg->common->phase_error) {
++ DBG(fsg, "sending phase-error status\n");
++ status = US_BULK_STAT_PHASE;
++
++ } else if ((UTP_CTX(fsg)->sd & 0xFFFF) != UTP_REPLY_PASS) {
++ status = US_BULK_STAT_FAIL;
++ }
++
++ csw = bh->buf;
++
++ /* Store and send the Bulk-only CSW */
++ csw->Signature = __constant_cpu_to_le32(US_BULK_CS_SIGN);
++ csw->Tag = fsg->common->tag;
++ csw->Residue = cpu_to_le32(fsg->common->residue);
++ csw->Status = status;
++
++ bh->inreq->length = US_BULK_CS_WRAP_LEN;
++ bh->inreq->zero = 0;
++ start_transfer(fsg, fsg->bulk_in, bh->inreq,
++ &bh->inreq_busy, &bh->state);
++ fsg->common->next_buffhd_to_fill = bh->next;
++ return 0;
++}
++
++static int utp_handle_message(struct fsg_dev *fsg,
++ char *cdb_data,
++ int default_reply)
++{
++ struct utp_msg *m = (struct utp_msg *)cdb_data;
++ void *data = NULL;
++ int r;
++ struct utp_user_data *uud2r;
++ unsigned long long param;
++ unsigned long tag;
++
++ if (m->f0 != 0xF0)
++ return default_reply;
++
++ tag = get_unaligned_be32((void *)&m->utp_msg_tag);
++ param = get_be64((void *)&m->param);
++ pr_debug("Type 0x%x, tag 0x%08lx, param %llx\n",
++ m->utp_msg_type, tag, param);
++
++ switch ((enum utp_msg_type)m->utp_msg_type) {
++
++ case UTP_POLL:
++ if (get_be64((void *)&m->param) == 1) {
++ pr_debug("%s: version request\n", __func__);
++ UTP_SS_EXIT(fsg, UTP_CTX(fsg)->utp_version);
++ break;
++ }
++ utp_poll(fsg);
++ break;
++ case UTP_EXEC:
++ pr_debug("%s: EXEC\n", __func__);
++ data = vmalloc(fsg->common->data_size);
++ memset(data, 0, fsg->common->data_size);
++ /* copy data from usb buffer to utp buffer */
++ utp_do_write(fsg, data, fsg->common->data_size);
++ utp_exec(fsg, data, fsg->common->data_size, param);
++ vfree(data);
++ break;
++ case UTP_GET: /* data from device to host */
++ pr_debug("%s: GET, %d bytes\n", __func__,
++ fsg->common->data_size);
++ r = utp_do_read(fsg, UTP_CTX(fsg)->buffer,
++ fsg->common->data_size);
++ UTP_SS_PASS(fsg);
++ break;
++ case UTP_PUT:
++ utp_context.cur_state = UTP_FLAG_DATA;
++ pr_debug("%s: PUT, Received %d bytes\n", __func__, fsg->common->data_size);/* data from host to device */
++ uud2r = utp_user_data_alloc(fsg->common->data_size);
++ if (!uud2r)
++ return -ENOMEM;
++ uud2r->data.bufsize = fsg->common->data_size;
++ uud2r->data.flags = UTP_FLAG_DATA;
++ utp_do_write(fsg, uud2r->data.data, fsg->common->data_size);
++ /* don't know what will be written */
++ mutex_lock(&UTP_CTX(fsg)->lock);
++ list_add_tail(&uud2r->link, &UTP_CTX(fsg)->read);
++ mutex_unlock(&UTP_CTX(fsg)->lock);
++ wake_up(&UTP_CTX(fsg)->wq);
++ /*
++ * Return PASS or FAIL according to uuc's status
++ * Please open it if need to check uuc's status
++ * and use another version uuc
++ */
++#if 0
++ struct utp_user_data *uud = NULL;
++ struct utp_context *ctx;
++ WAIT_ACTIVITY(write);
++ ctx = UTP_CTX(fsg);
++ mutex_lock(&ctx->lock);
++
++ if (!list_empty(&ctx->write))
++ uud = list_first_entry(&ctx->write,
++ struct utp_user_data, link);
++
++ mutex_unlock(&ctx->lock);
++ if (uud) {
++ if (uud->data.flags & UTP_FLAG_STATUS) {
++ printk(KERN_WARNING "%s: exit with status %d\n",
++ __func__, uud->data.status);
++ UTP_SS_EXIT(fsg, uud->data.status);
++ } else {
++ pr_debug("%s: pass\n", __func__);
++ UTP_SS_PASS(fsg);
++ }
++ utp_user_data_free(uud);
++ } else{
++ UTP_SS_PASS(fsg);
++ }
++#endif
++ if (count_list(&UTP_CTX(fsg)->read) < 7) {
++ utp_context.cur_state = 0;
++ UTP_SS_PASS(fsg);
++ } else
++ UTP_SS_BUSY(fsg, UTP_CTX(fsg)->counter);
++
++ break;
++ }
++
++ utp_send_status(fsg);
++ return -1;
++}
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/fsl_updater.h linux-3.14.72/drivers/usb/gadget/fsl_updater.h
+--- linux-3.14.72.orig/drivers/usb/gadget/fsl_updater.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/gadget/fsl_updater.h 2016-06-19 22:11:55.333138169 +0200
+@@ -0,0 +1,150 @@
++/*
++ * Freescale UUT driver
++ *
++ * Copyright 2008-2014 Freescale Semiconductor, Inc.
++ * Copyright 2008-2009 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef __FSL_UPDATER_H
++#define __FSL_UPDATER_H
++
++#include <linux/miscdevice.h>
++#include <linux/list.h>
++#include <linux/vmalloc.h>
++#include <linux/ioctl.h>
++/* #include <mach/hardware.h> */
++
++static int utp_init(struct fsg_dev *fsg);
++static void utp_exit(struct fsg_dev *fsg);
++static ssize_t utp_file_read(struct file *file,
++ char __user *buf,
++ size_t size,
++ loff_t *off);
++
++static ssize_t utp_file_write(struct file *file,
++ const char __user *buf,
++ size_t size,
++ loff_t *off);
++
++static long utp_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg);
++static struct utp_user_data *utp_user_data_alloc(size_t size);
++static void utp_user_data_free(struct utp_user_data *uud);
++static int utp_get_sense(struct fsg_dev *fsg);
++static int utp_do_read(struct fsg_dev *fsg, void *data, size_t size);
++static int utp_do_write(struct fsg_dev *fsg, void *data, size_t size);
++static inline void utp_set_sense(struct fsg_dev *fsg, u16 code, u64 reply);
++static int utp_handle_message(struct fsg_dev *fsg,
++ char *cdb_data,
++ int default_reply);
++
++#define UTP_REPLY_PASS 0
++#define UTP_REPLY_EXIT 0x8001
++#define UTP_REPLY_BUSY 0x8002
++#define UTP_REPLY_SIZE 0x8003
++#define UTP_SENSE_KEY 9
++
++#define UTP_MINOR 222
++/* MISC_DYNAMIC_MINOR would be better, but... */
++
++#define UTP_COMMAND_SIZE 80
++
++#define UTP_SS_EXIT(fsg, r) utp_set_sense(fsg, UTP_REPLY_EXIT, (u64)r)
++#define UTP_SS_PASS(fsg) utp_set_sense(fsg, UTP_REPLY_PASS, 0)
++#define UTP_SS_BUSY(fsg, r) utp_set_sense(fsg, UTP_REPLY_BUSY, (u64)r)
++#define UTP_SS_SIZE(fsg, r) utp_set_sense(fsg, UTP_REPLY_SIZE, (u64)r)
++
++#define UTP_IOCTL_BASE 'U'
++#define UTP_GET_CPU_ID _IOR(UTP_IOCTL_BASE, 0, int)
++/* the structure of utp message which is mapped to 16-byte SCSI CBW's CDB */
++#pragma pack(1)
++struct utp_msg {
++ u8 f0;
++ u8 utp_msg_type;
++ u32 utp_msg_tag;
++ union {
++ struct {
++ u32 param_lsb;
++ u32 param_msb;
++ };
++ u64 param;
++ };
++};
++
++enum utp_msg_type {
++ UTP_POLL = 0,
++ UTP_EXEC,
++ UTP_GET,
++ UTP_PUT,
++};
++
++static struct utp_context {
++ wait_queue_head_t wq;
++ wait_queue_head_t list_full_wq;
++ struct mutex lock;
++ struct list_head read;
++ struct list_head write;
++ u32 sd, sdinfo, sdinfo_h; /* sense data */
++ int processed;
++ u8 *buffer;
++ u32 counter;
++ u64 utp_version;
++ u32 cur_state;
++} utp_context;
++
++static const struct file_operations utp_fops = {
++ .open = nonseekable_open,
++ .read = utp_file_read,
++ .write = utp_file_write,
++ /* .ioctl = utp_ioctl, */
++ .unlocked_ioctl = utp_ioctl,
++};
++
++static struct miscdevice utp_dev = {
++ .minor = UTP_MINOR,
++ .name = "utp",
++ .fops = &utp_fops,
++};
++
++#define UTP_FLAG_COMMAND 0x00000001
++#define UTP_FLAG_DATA 0x00000002
++#define UTP_FLAG_STATUS 0x00000004
++#define UTP_FLAG_REPORT_BUSY 0x10000000
++struct utp_message {
++ u32 flags;
++ size_t size;
++ union {
++ struct {
++ u64 payload;
++ char command[1];
++ };
++ struct {
++ size_t bufsize;
++ u8 data[1];
++ };
++ u32 status;
++ };
++};
++
++struct utp_user_data {
++ struct list_head link;
++ struct utp_message data;
++};
++#pragma pack()
++
++static inline struct utp_context *UTP_CTX(struct fsg_dev *fsg)
++{
++ return (struct utp_context *)fsg->utp;
++}
++
++#endif /* __FSL_UPDATER_H */
++
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/gmidi.c linux-3.14.72/drivers/usb/gadget/gmidi.c
+--- linux-3.14.72.orig/drivers/usb/gadget/gmidi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/gmidi.c 2016-06-19 22:11:55.333138169 +0200
+@@ -167,7 +167,7 @@
+ {
+ return usb_composite_probe(&midi_driver);
+ }
+-module_init(midi_init);
++late_initcall(midi_init);
+
+ static void __exit midi_cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/hid.c linux-3.14.72/drivers/usb/gadget/hid.c
+--- linux-3.14.72.orig/drivers/usb/gadget/hid.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/hid.c 2016-06-19 22:11:55.333138169 +0200
+@@ -256,7 +256,7 @@
+
+ return status;
+ }
+-module_init(hidg_init);
++late_initcall(hidg_init);
+
+ static void __exit hidg_cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/inode.c linux-3.14.72/drivers/usb/gadget/inode.c
+--- linux-3.14.72.orig/drivers/usb/gadget/inode.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/inode.c 2016-06-19 22:11:55.333138169 +0200
+@@ -1497,6 +1497,7 @@
+ */
+ if (value == 0) {
+ INFO (dev, "configuration #%d\n", dev->current_config);
++ usb_gadget_set_state(gadget, USB_STATE_CONFIGURED);
+ if (dev->usermode_setup) {
+ dev->setup_can_stall = 0;
+ goto delegate;
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/Kconfig linux-3.14.72/drivers/usb/gadget/Kconfig
+--- linux-3.14.72.orig/drivers/usb/gadget/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/Kconfig 2016-06-19 22:11:55.333138169 +0200
+@@ -953,6 +953,12 @@
+ Say "y" to link the driver statically, or "m" to build
+ a dynamically linked module called "g_mass_storage".
+
++config FSL_UTP
++ bool "UTP over Storage Gadget"
++ depends on USB_MASS_STORAGE
++ help
++ Freescale's extension to MSC protocol
++
+ config USB_GADGET_TARGET
+ tristate "USB Gadget Target Fabric Module"
+ depends on TARGET_CORE
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/mass_storage.c linux-3.14.72/drivers/usb/gadget/mass_storage.c
+--- linux-3.14.72.orig/drivers/usb/gadget/mass_storage.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/mass_storage.c 2016-06-19 22:11:55.333138169 +0200
+@@ -73,6 +73,7 @@
+ * it would not be called "OTG" ...
+ */
+ .bmAttributes = USB_OTG_SRP | USB_OTG_HNP,
++ .bcdOTG = cpu_to_le16(0x0200),
+ };
+
+ static const struct usb_descriptor_header *otg_desc[] = {
+@@ -266,7 +267,7 @@
+ {
+ return usb_composite_probe(&msg_driver);
+ }
+-module_init(msg_init);
++late_initcall(msg_init);
+
+ static void msg_cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/multi.c linux-3.14.72/drivers/usb/gadget/multi.c
+--- linux-3.14.72.orig/drivers/usb/gadget/multi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/multi.c 2016-06-19 22:11:55.333138169 +0200
+@@ -512,7 +512,7 @@
+ {
+ return usb_composite_probe(&multi_driver);
+ }
+-module_init(multi_init);
++late_initcall(multi_init);
+
+ static void __exit multi_exit(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/ncm.c linux-3.14.72/drivers/usb/gadget/ncm.c
+--- linux-3.14.72.orig/drivers/usb/gadget/ncm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/ncm.c 2016-06-19 22:11:55.333138169 +0200
+@@ -212,7 +212,7 @@
+ {
+ return usb_composite_probe(&ncm_driver);
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/nokia.c linux-3.14.72/drivers/usb/gadget/nokia.c
+--- linux-3.14.72.orig/drivers/usb/gadget/nokia.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/nokia.c 2016-06-19 22:11:55.333138169 +0200
+@@ -351,7 +351,7 @@
+ {
+ return usb_composite_probe(&nokia_driver);
+ }
+-module_init(nokia_init);
++late_initcall(nokia_init);
+
+ static void __exit nokia_cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/printer.c linux-3.14.72/drivers/usb/gadget/printer.c
+--- linux-3.14.72.orig/drivers/usb/gadget/printer.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/printer.c 2016-06-19 22:11:55.333138169 +0200
+@@ -1290,7 +1290,7 @@
+
+ return status;
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit
+ cleanup(void)
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/serial.c linux-3.14.72/drivers/usb/gadget/serial.c
+--- linux-3.14.72.orig/drivers/usb/gadget/serial.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/serial.c 2016-06-19 22:11:55.333138169 +0200
+@@ -87,6 +87,7 @@
+ * it would not be called "OTG" ...
+ */
+ .bmAttributes = USB_OTG_SRP | USB_OTG_HNP,
++ .bcdOTG = cpu_to_le16(0x0200),
+ };
+
+ static const struct usb_descriptor_header *otg_desc[] = {
+@@ -267,7 +268,7 @@
+
+ return usb_composite_probe(&gserial_driver);
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/udc-core.c linux-3.14.72/drivers/usb/gadget/udc-core.c
+--- linux-3.14.72.orig/drivers/usb/gadget/udc-core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/udc-core.c 2016-06-19 22:11:55.333138169 +0200
+@@ -428,6 +428,8 @@
+ list_for_each_entry(udc, &udc_list, list)
+ if (udc->driver == driver) {
+ usb_gadget_remove_driver(udc);
++ usb_gadget_set_state(udc->gadget,
++ USB_STATE_NOTATTACHED);
+ ret = 0;
+ break;
+ }
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/webcam.c linux-3.14.72/drivers/usb/gadget/webcam.c
+--- linux-3.14.72.orig/drivers/usb/gadget/webcam.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/webcam.c 2016-06-19 22:11:55.333138169 +0200
+@@ -402,7 +402,7 @@
+ usb_composite_unregister(&webcam_driver);
+ }
+
+-module_init(webcam_init);
++late_initcall(webcam_init);
+ module_exit(webcam_cleanup);
+
+ MODULE_AUTHOR("Laurent Pinchart");
+diff -Nur linux-3.14.72.orig/drivers/usb/gadget/zero.c linux-3.14.72/drivers/usb/gadget/zero.c
+--- linux-3.14.72.orig/drivers/usb/gadget/zero.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/gadget/zero.c 2016-06-19 22:11:55.333138169 +0200
+@@ -418,7 +418,7 @@
+ {
+ return usb_composite_probe(&zero_driver);
+ }
+-module_init(init);
++late_initcall(init);
+
+ static void __exit cleanup(void)
+ {
+diff -Nur linux-3.14.72.orig/drivers/usb/host/ehci-fsl.c linux-3.14.72/drivers/usb/host/ehci-fsl.c
+--- linux-3.14.72.orig/drivers/usb/host/ehci-fsl.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/host/ehci-fsl.c 2016-06-19 22:11:55.333138169 +0200
+@@ -136,15 +136,15 @@
+ if (pdata->operating_mode == FSL_USB2_DR_OTG) {
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+- hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
++ hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
+ dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
+- hcd, ehci, hcd->phy);
++ hcd, ehci, hcd->usb_phy);
+
+- if (!IS_ERR_OR_NULL(hcd->phy)) {
+- retval = otg_set_host(hcd->phy->otg,
++ if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
++ retval = otg_set_host(hcd->usb_phy->otg,
+ &ehci_to_hcd(ehci)->self);
+ if (retval) {
+- usb_put_phy(hcd->phy);
++ usb_put_phy(hcd->usb_phy);
+ goto err2;
+ }
+ } else {
+@@ -181,9 +181,9 @@
+ {
+ struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
+
+- if (!IS_ERR_OR_NULL(hcd->phy)) {
+- otg_set_host(hcd->phy->otg, NULL);
+- usb_put_phy(hcd->phy);
++ if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
++ otg_set_host(hcd->usb_phy->otg, NULL);
++ usb_put_phy(hcd->usb_phy);
+ }
+
+ usb_remove_hcd(hcd);
+diff -Nur linux-3.14.72.orig/drivers/usb/host/ehci.h linux-3.14.72/drivers/usb/host/ehci.h
+--- linux-3.14.72.orig/drivers/usb/host/ehci.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/host/ehci.h 2016-06-19 22:11:55.333138169 +0200
+@@ -859,6 +859,8 @@
+ struct ehci_driver_overrides {
+ size_t extra_priv_size;
+ int (*reset)(struct usb_hcd *hcd);
++ int (*port_power)(struct usb_hcd *hcd,
++ int portnum, bool enable);
+ };
+
+ extern void ehci_init_driver(struct hc_driver *drv,
+diff -Nur linux-3.14.72.orig/drivers/usb/host/ehci-hcd.c linux-3.14.72/drivers/usb/host/ehci-hcd.c
+--- linux-3.14.72.orig/drivers/usb/host/ehci-hcd.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/host/ehci-hcd.c 2016-06-19 22:11:55.337137907 +0200
+@@ -93,7 +93,7 @@
+ MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
+
+ /* initial park setting: slower than hw default */
+-static unsigned park = 0;
++static unsigned park = 3;
+ module_param (park, uint, S_IRUGO);
+ MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
+
+@@ -311,6 +311,7 @@
+ static void ehci_work(struct ehci_hcd *ehci);
+ static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
+ static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
++static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable);
+
+ #include "ehci-timer.c"
+ #include "ehci-hub.c"
+@@ -329,9 +330,13 @@
+ {
+ int port = HCS_N_PORTS(ehci->hcs_params);
+
+- while (port--)
++ while (port--) {
+ ehci_writel(ehci, PORT_RWC_BITS,
+ &ehci->regs->port_status[port]);
++ spin_unlock_irq(&ehci->lock);
++ ehci_port_power(ehci, port, false);
++ spin_lock_irq(&ehci->lock);
++ }
+ }
+
+ /*
+@@ -1233,6 +1238,8 @@
+ drv->hcd_priv_size += over->extra_priv_size;
+ if (over->reset)
+ drv->reset = over->reset;
++ if (over->port_power)
++ drv->port_power = over->port_power;
+ }
+ }
+ EXPORT_SYMBOL_GPL(ehci_init_driver);
+diff -Nur linux-3.14.72.orig/drivers/usb/host/ehci-hub.c linux-3.14.72/drivers/usb/host/ehci-hub.c
+--- linux-3.14.72.orig/drivers/usb/host/ehci-hub.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/host/ehci-hub.c 2016-06-19 22:11:55.337137907 +0200
+@@ -78,10 +78,8 @@
+ if (test_bit(port, &ehci->owned_ports)) {
+ reg = &ehci->regs->port_status[port];
+ status = ehci_readl(ehci, reg) & ~PORT_RWC_BITS;
+- if (!(status & PORT_POWER)) {
+- status |= PORT_POWER;
+- ehci_writel(ehci, status, reg);
+- }
++ if (!(status & PORT_POWER))
++ ehci_port_power(ehci, port, true);
+ }
+ }
+
+@@ -934,7 +932,7 @@
+ #ifdef CONFIG_USB_OTG
+ if ((hcd->self.otg_port == (wIndex + 1))
+ && hcd->self.b_hnp_enable) {
+- otg_start_hnp(hcd->phy->otg);
++ otg_start_hnp(hcd->usb_phy->otg);
+ break;
+ }
+ #endif
+@@ -964,9 +962,11 @@
+ clear_bit(wIndex, &ehci->port_c_suspend);
+ break;
+ case USB_PORT_FEAT_POWER:
+- if (HCS_PPC (ehci->hcs_params))
+- ehci_writel(ehci, temp & ~PORT_POWER,
+- status_reg);
++ if (HCS_PPC(ehci->hcs_params)) {
++ spin_unlock_irqrestore(&ehci->lock, flags);
++ ehci_port_power(ehci, wIndex, false);
++ spin_lock_irqsave(&ehci->lock, flags);
++ }
+ break;
+ case USB_PORT_FEAT_C_CONNECTION:
+ ehci_writel(ehci, temp | PORT_CSC, status_reg);
+@@ -1016,9 +1016,9 @@
+ */
+ if (((temp & PORT_OC) || (ehci->need_oc_pp_cycle))
+ && HCS_PPC(ehci->hcs_params)) {
+- ehci_writel(ehci,
+- temp & ~(PORT_RWC_BITS | PORT_POWER),
+- status_reg);
++ spin_unlock_irqrestore(&ehci->lock, flags);
++ ehci_port_power(ehci, wIndex, false);
++ spin_lock_irqsave(&ehci->lock, flags);
+ temp = ehci_readl(ehci, status_reg);
+ }
+ }
+@@ -1199,9 +1199,11 @@
+ set_bit(wIndex, &ehci->suspended_ports);
+ break;
+ case USB_PORT_FEAT_POWER:
+- if (HCS_PPC (ehci->hcs_params))
+- ehci_writel(ehci, temp | PORT_POWER,
+- status_reg);
++ if (HCS_PPC(ehci->hcs_params)) {
++ spin_unlock_irqrestore(&ehci->lock, flags);
++ ehci_port_power(ehci, wIndex, true);
++ spin_lock_irqsave(&ehci->lock, flags);
++ }
+ break;
+ case USB_PORT_FEAT_RESET:
+ if (temp & (PORT_SUSPEND|PORT_RESUME))
+@@ -1308,3 +1310,20 @@
+ reg = &ehci->regs->port_status[portnum - 1];
+ return ehci_readl(ehci, reg) & PORT_OWNER;
+ }
++
++static int ehci_port_power(struct ehci_hcd *ehci, int portnum, bool enable)
++{
++ struct usb_hcd *hcd = ehci_to_hcd(ehci);
++ u32 __iomem *status_reg = &ehci->regs->port_status[portnum];
++ u32 temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
++
++ if (enable)
++ ehci_writel(ehci, temp | PORT_POWER, status_reg);
++ else
++ ehci_writel(ehci, temp & ~PORT_POWER, status_reg);
++
++ if (hcd->driver->port_power)
++ hcd->driver->port_power(hcd, portnum, enable);
++
++ return 0;
++}
+diff -Nur linux-3.14.72.orig/drivers/usb/host/ehci-msm.c linux-3.14.72/drivers/usb/host/ehci-msm.c
+--- linux-3.14.72.orig/drivers/usb/host/ehci-msm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/host/ehci-msm.c 2016-06-19 22:11:55.337137907 +0200
+@@ -125,7 +125,7 @@
+ goto put_hcd;
+ }
+
+- hcd->phy = phy;
++ hcd->usb_phy = phy;
+ device_init_wakeup(&pdev->dev, 1);
+ /*
+ * OTG device parent of HCD takes care of putting
+@@ -152,7 +152,7 @@
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+
+- otg_set_host(hcd->phy->otg, NULL);
++ otg_set_host(hcd->usb_phy->otg, NULL);
+
+ /* FIXME: need to call usb_remove_hcd() here? */
+
+diff -Nur linux-3.14.72.orig/drivers/usb/host/ehci-tegra.c linux-3.14.72/drivers/usb/host/ehci-tegra.c
+--- linux-3.14.72.orig/drivers/usb/host/ehci-tegra.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/host/ehci-tegra.c 2016-06-19 22:11:55.337137907 +0200
+@@ -158,7 +158,7 @@
+ if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
+ /* Resume completed, re-enable disconnect detection */
+ tegra->port_resuming = 0;
+- tegra_usb_phy_postresume(hcd->phy);
++ tegra_usb_phy_postresume(hcd->usb_phy);
+ }
+ }
+
+@@ -211,7 +211,7 @@
+ goto done;
+
+ /* Disable disconnect detection during port resume */
+- tegra_usb_phy_preresume(hcd->phy);
++ tegra_usb_phy_preresume(hcd->usb_phy);
+
+ ehci->reset_done[wIndex-1] = jiffies + msecs_to_jiffies(25);
+
+@@ -406,7 +406,7 @@
+ err = PTR_ERR(u_phy);
+ goto cleanup_clk_en;
+ }
+- hcd->phy = u_phy;
++ hcd->usb_phy = u_phy;
+
+ tegra->needs_double_reset = of_property_read_bool(pdev->dev.of_node,
+ "nvidia,needs-double-reset");
+@@ -428,7 +428,7 @@
+ ehci->caps = hcd->regs + 0x100;
+ ehci->has_hostpc = soc_config->has_hostpc;
+
+- err = usb_phy_init(hcd->phy);
++ err = usb_phy_init(hcd->usb_phy);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to initialize phy\n");
+ goto cleanup_clk_en;
+@@ -443,7 +443,7 @@
+ }
+ u_phy->otg->host = hcd_to_bus(hcd);
+
+- err = usb_phy_set_suspend(hcd->phy, 0);
++ err = usb_phy_set_suspend(hcd->usb_phy, 0);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to power on the phy\n");
+ goto cleanup_phy;
+@@ -470,7 +470,7 @@
+ cleanup_otg_set_host:
+ otg_set_host(u_phy->otg, NULL);
+ cleanup_phy:
+- usb_phy_shutdown(hcd->phy);
++ usb_phy_shutdown(hcd->usb_phy);
+ cleanup_clk_en:
+ clk_disable_unprepare(tegra->clk);
+ cleanup_hcd_create:
+@@ -484,9 +484,9 @@
+ struct tegra_ehci_hcd *tegra =
+ (struct tegra_ehci_hcd *)hcd_to_ehci(hcd)->priv;
+
+- otg_set_host(hcd->phy->otg, NULL);
++ otg_set_host(hcd->usb_phy->otg, NULL);
+
+- usb_phy_shutdown(hcd->phy);
++ usb_phy_shutdown(hcd->usb_phy);
+ usb_remove_hcd(hcd);
+ usb_put_hcd(hcd);
+
+diff -Nur linux-3.14.72.orig/drivers/usb/host/ohci-omap.c linux-3.14.72/drivers/usb/host/ohci-omap.c
+--- linux-3.14.72.orig/drivers/usb/host/ohci-omap.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/host/ohci-omap.c 2016-06-19 22:11:55.337137907 +0200
+@@ -180,10 +180,10 @@
+ unsigned long flags;
+ u32 l;
+
+- otg_start_hnp(hcd->phy->otg);
++ otg_start_hnp(hcd->usb_phy->otg);
+
+ local_irq_save(flags);
+- hcd->phy->state = OTG_STATE_A_SUSPEND;
++ hcd->usb_phy->otg.state = OTG_STATE_A_SUSPEND;
+ writel (RH_PS_PSS, &ohci->regs->roothub.portstatus [port]);
+ l = omap_readl(OTG_CTRL);
+ l &= ~OTG_A_BUSREQ;
+@@ -220,14 +220,14 @@
+
+ #ifdef CONFIG_USB_OTG
+ if (need_transceiver) {
+- hcd->phy = usb_get_phy(USB_PHY_TYPE_USB2);
+- if (!IS_ERR_OR_NULL(hcd->phy)) {
+- int status = otg_set_host(hcd->phy->otg,
++ hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
++ if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
++ int status = otg_set_host(hcd->usb_phy->otg,
+ &ohci_to_hcd(ohci)->self);
+ dev_dbg(hcd->self.controller, "init %s phy, status %d\n",
+- hcd->phy->label, status);
++ hcd->usb_phy->label, status);
+ if (status) {
+- usb_put_phy(hcd->phy);
++ usb_put_phy(hcd->usb_phy);
+ return status;
+ }
+ } else {
+@@ -399,9 +399,9 @@
+ dev_dbg(hcd->self.controller, "stopping USB Controller\n");
+ usb_remove_hcd(hcd);
+ omap_ohci_clock_power(0);
+- if (!IS_ERR_OR_NULL(hcd->phy)) {
+- (void) otg_set_host(hcd->phy->otg, 0);
+- usb_put_phy(hcd->phy);
++ if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
++ (void) otg_set_host(hcd->usb_phy->otg, 0);
++ usb_put_phy(hcd->usb_phy);
+ }
+ if (machine_is_omap_osk())
+ gpio_free(9);
+diff -Nur linux-3.14.72.orig/drivers/usb/Makefile linux-3.14.72/drivers/usb/Makefile
+--- linux-3.14.72.orig/drivers/usb/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/Makefile 2016-06-19 22:11:55.337137907 +0200
+@@ -58,4 +58,4 @@
+ obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs/
+ obj-$(CONFIG_USB_GADGET) += gadget/
+
+-obj-$(CONFIG_USB_COMMON) += usb-common.o
++obj-$(CONFIG_USB_COMMON) += common/
+diff -Nur linux-3.14.72.orig/drivers/usb/misc/lvstest.c linux-3.14.72/drivers/usb/misc/lvstest.c
+--- linux-3.14.72.orig/drivers/usb/misc/lvstest.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/usb/misc/lvstest.c 2016-06-19 22:11:55.337137907 +0200
+@@ -0,0 +1,460 @@
++/*
++ * drivers/usb/misc/lvstest.c
++ *
++ * Test pattern generation for Link Layer Validation System Tests
++ *
++ * Copyright (C) 2014 ST Microelectronics
++ * Pratyush Anand <pratyush.anand@st.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/usb.h>
++#include <linux/usb/ch11.h>
++#include <linux/usb/hcd.h>
++#include <linux/usb/phy.h>
++
++struct lvs_rh {
++ /* root hub interface */
++ struct usb_interface *intf;
++ /* if lvs device connected */
++ bool present;
++ /* port no at which lvs device is present */
++ int portnum;
++ /* urb buffer */
++ u8 buffer[8];
++ /* class descriptor */
++ struct usb_hub_descriptor descriptor;
++ /* urb for polling interrupt pipe */
++ struct urb *urb;
++ /* LVS RH work queue */
++ struct workqueue_struct *rh_queue;
++ /* LVH RH work */
++ struct work_struct rh_work;
++ /* RH port status */
++ struct usb_port_status port_status;
++};
++
++static struct usb_device *create_lvs_device(struct usb_interface *intf)
++{
++ struct usb_device *udev, *hdev;
++ struct usb_hcd *hcd;
++ struct lvs_rh *lvs = usb_get_intfdata(intf);
++
++ if (!lvs->present) {
++ dev_err(&intf->dev, "No LVS device is present\n");
++ return NULL;
++ }
++
++ hdev = interface_to_usbdev(intf);
++ hcd = bus_to_hcd(hdev->bus);
++
++ udev = usb_alloc_dev(hdev, hdev->bus, lvs->portnum);
++ if (!udev) {
++ dev_err(&intf->dev, "Could not allocate lvs udev\n");
++ return NULL;
++ }
++ udev->speed = USB_SPEED_SUPER;
++ udev->ep0.desc.wMaxPacketSize = cpu_to_le16(512);
++ usb_set_device_state(udev, USB_STATE_DEFAULT);
++
++ if (hcd->driver->enable_device) {
++ if (hcd->driver->enable_device(hcd, udev) < 0) {
++ dev_err(&intf->dev, "Failed to enable\n");
++ usb_put_dev(udev);
++ return NULL;
++ }
++ }
++
++ return udev;
++}
++
++static void destroy_lvs_device(struct usb_device *udev)
++{
++ struct usb_device *hdev = udev->parent;
++ struct usb_hcd *hcd = bus_to_hcd(hdev->bus);
++
++ if (hcd->driver->free_dev)
++ hcd->driver->free_dev(hcd, udev);
++
++ usb_put_dev(udev);
++}
++
++static int lvs_rh_clear_port_feature(struct usb_device *hdev,
++ int port1, int feature)
++{
++ return usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_CLEAR_FEATURE, USB_RT_PORT, feature, port1,
++ NULL, 0, 1000);
++}
++
++static int lvs_rh_set_port_feature(struct usb_device *hdev,
++ int port1, int feature)
++{
++ return usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0),
++ USB_REQ_SET_FEATURE, USB_RT_PORT, feature, port1,
++ NULL, 0, 1000);
++}
++
++static ssize_t u3_entry_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct usb_interface *intf = to_usb_interface(dev);
++ struct usb_device *hdev = interface_to_usbdev(intf);
++ struct lvs_rh *lvs = usb_get_intfdata(intf);
++ struct usb_device *udev;
++ int ret;
++
++ udev = create_lvs_device(intf);
++ if (!udev) {
++ dev_err(dev, "failed to create lvs device\n");
++ return -ENOMEM;
++ }
++
++ ret = lvs_rh_set_port_feature(hdev, lvs->portnum,
++ USB_PORT_FEAT_SUSPEND);
++ if (ret < 0)
++ dev_err(dev, "can't issue U3 entry %d\n", ret);
++
++ destroy_lvs_device(udev);
++
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++static DEVICE_ATTR_WO(u3_entry);
++
++static ssize_t u3_exit_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct usb_interface *intf = to_usb_interface(dev);
++ struct usb_device *hdev = interface_to_usbdev(intf);
++ struct lvs_rh *lvs = usb_get_intfdata(intf);
++ struct usb_device *udev;
++ int ret;
++
++ udev = create_lvs_device(intf);
++ if (!udev) {
++ dev_err(dev, "failed to create lvs device\n");
++ return -ENOMEM;
++ }
++
++ ret = lvs_rh_clear_port_feature(hdev, lvs->portnum,
++ USB_PORT_FEAT_SUSPEND);
++ if (ret < 0)
++ dev_err(dev, "can't issue U3 exit %d\n", ret);
++
++ destroy_lvs_device(udev);
++
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++static DEVICE_ATTR_WO(u3_exit);
++
++static ssize_t hot_reset_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct usb_interface *intf = to_usb_interface(dev);
++ struct usb_device *hdev = interface_to_usbdev(intf);
++ struct lvs_rh *lvs = usb_get_intfdata(intf);
++ int ret;
++
++ ret = lvs_rh_set_port_feature(hdev, lvs->portnum,
++ USB_PORT_FEAT_RESET);
++ if (ret < 0) {
++ dev_err(dev, "can't issue hot reset %d\n", ret);
++ return ret;
++ }
++
++ return count;
++}
++static DEVICE_ATTR_WO(hot_reset);
++
++static ssize_t u2_timeout_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct usb_interface *intf = to_usb_interface(dev);
++ struct usb_device *hdev = interface_to_usbdev(intf);
++ struct lvs_rh *lvs = usb_get_intfdata(intf);
++ unsigned long val;
++ int ret;
++
++ ret = kstrtoul(buf, 10, &val);
++ if (ret < 0) {
++ dev_err(dev, "couldn't parse string %d\n", ret);
++ return ret;
++ }
++
++ if (val < 0 || val > 127)
++ return -EINVAL;
++
++ ret = lvs_rh_set_port_feature(hdev, lvs->portnum | (val << 8),
++ USB_PORT_FEAT_U2_TIMEOUT);
++ if (ret < 0) {
++ dev_err(dev, "Error %d while setting U2 timeout %ld\n", ret, val);
++ return ret;
++ }
++
++ return count;
++}
++static DEVICE_ATTR_WO(u2_timeout);
++
++static ssize_t u1_timeout_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct usb_interface *intf = to_usb_interface(dev);
++ struct usb_device *hdev = interface_to_usbdev(intf);
++ struct lvs_rh *lvs = usb_get_intfdata(intf);
++ unsigned long val;
++ int ret;
++
++ ret = kstrtoul(buf, 10, &val);
++ if (ret < 0) {
++ dev_err(dev, "couldn't parse string %d\n", ret);
++ return ret;
++ }
++
++ if (val < 0 || val > 127)
++ return -EINVAL;
++
++ ret = lvs_rh_set_port_feature(hdev, lvs->portnum | (val << 8),
++ USB_PORT_FEAT_U1_TIMEOUT);
++ if (ret < 0) {
++ dev_err(dev, "Error %d while setting U1 timeout %ld\n", ret, val);
++ return ret;
++ }
++
++ return count;
++}
++static DEVICE_ATTR_WO(u1_timeout);
++
++static ssize_t get_dev_desc_store(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct usb_interface *intf = to_usb_interface(dev);
++ struct usb_device *udev;
++ struct usb_device_descriptor *descriptor;
++ int ret;
++
++ descriptor = kmalloc(sizeof(*descriptor), GFP_KERNEL);
++ if (!descriptor) {
++ dev_err(dev, "failed to allocate descriptor memory\n");
++ return -ENOMEM;
++ }
++
++ udev = create_lvs_device(intf);
++ if (!udev) {
++ dev_err(dev, "failed to create lvs device\n");
++ ret = -ENOMEM;
++ goto free_desc;
++ }
++
++ ret = usb_control_msg(udev, (PIPE_CONTROL << 30) | USB_DIR_IN,
++ USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, USB_DT_DEVICE << 8,
++ 0, descriptor, sizeof(*descriptor),
++ USB_CTRL_GET_TIMEOUT);
++ if (ret < 0)
++ dev_err(dev, "can't read device descriptor %d\n", ret);
++
++ destroy_lvs_device(udev);
++
++free_desc:
++ kfree(descriptor);
++
++ if (ret < 0)
++ return ret;
++
++ return count;
++}
++static DEVICE_ATTR_WO(get_dev_desc);
++
++static struct attribute *lvs_attributes[] = {
++ &dev_attr_get_dev_desc.attr,
++ &dev_attr_u1_timeout.attr,
++ &dev_attr_u2_timeout.attr,
++ &dev_attr_hot_reset.attr,
++ &dev_attr_u3_entry.attr,
++ &dev_attr_u3_exit.attr,
++ NULL
++};
++
++static const struct attribute_group lvs_attr_group = {
++ .attrs = lvs_attributes,
++};
++
++static void lvs_rh_work(struct work_struct *work)
++{
++ struct lvs_rh *lvs = container_of(work, struct lvs_rh, rh_work);
++ struct usb_interface *intf = lvs->intf;
++ struct usb_device *hdev = interface_to_usbdev(intf);
++ struct usb_hcd *hcd = bus_to_hcd(hdev->bus);
++ struct usb_hub_descriptor *descriptor = &lvs->descriptor;
++ struct usb_port_status *port_status = &lvs->port_status;
++ int i, ret = 0;
++ u16 portchange;
++
++ /* Examine each root port */
++ for (i = 1; i <= descriptor->bNbrPorts; i++) {
++ ret = usb_control_msg(hdev, usb_rcvctrlpipe(hdev, 0),
++ USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, i,
++ port_status, sizeof(*port_status), 1000);
++ if (ret < 4)
++ continue;
++
++ portchange = le16_to_cpu(port_status->wPortChange);
++
++ if (portchange & USB_PORT_STAT_C_LINK_STATE)
++ lvs_rh_clear_port_feature(hdev, i,
++ USB_PORT_FEAT_C_PORT_LINK_STATE);
++ if (portchange & USB_PORT_STAT_C_ENABLE)
++ lvs_rh_clear_port_feature(hdev, i,
++ USB_PORT_FEAT_C_ENABLE);
++ if (portchange & USB_PORT_STAT_C_RESET)
++ lvs_rh_clear_port_feature(hdev, i,
++ USB_PORT_FEAT_C_RESET);
++ if (portchange & USB_PORT_STAT_C_BH_RESET)
++ lvs_rh_clear_port_feature(hdev, i,
++ USB_PORT_FEAT_C_BH_PORT_RESET);
++ if (portchange & USB_PORT_STAT_C_CONNECTION) {
++ lvs_rh_clear_port_feature(hdev, i,
++ USB_PORT_FEAT_C_CONNECTION);
++
++ if (le16_to_cpu(port_status->wPortStatus) &
++ USB_PORT_STAT_CONNECTION) {
++ lvs->present = true;
++ lvs->portnum = i;
++ if (hcd->usb_phy)
++ usb_phy_notify_connect(hcd->usb_phy,
++ USB_SPEED_SUPER);
++ } else {
++ lvs->present = false;
++ if (hcd->usb_phy)
++ usb_phy_notify_disconnect(hcd->usb_phy,
++ USB_SPEED_SUPER);
++ }
++ break;
++ }
++ }
++
++ ret = usb_submit_urb(lvs->urb, GFP_KERNEL);
++ if (ret != 0 && ret != -ENODEV && ret != -EPERM)
++ dev_err(&intf->dev, "urb resubmit error %d\n", ret);
++}
++
++static void lvs_rh_irq(struct urb *urb)
++{
++ struct lvs_rh *lvs = urb->context;
++
++ queue_work(lvs->rh_queue, &lvs->rh_work);
++}
++
++static int lvs_rh_probe(struct usb_interface *intf,
++ const struct usb_device_id *id)
++{
++ struct usb_device *hdev;
++ struct usb_host_interface *desc;
++ struct usb_endpoint_descriptor *endpoint;
++ struct lvs_rh *lvs;
++ unsigned int pipe;
++ int ret, maxp;
++
++ hdev = interface_to_usbdev(intf);
++ desc = intf->cur_altsetting;
++ endpoint = &desc->endpoint[0].desc;
++
++ /* valid only for SS root hub */
++ if (hdev->descriptor.bDeviceProtocol != USB_HUB_PR_SS || hdev->parent) {
++ dev_err(&intf->dev, "Bind LVS driver with SS root Hub only\n");
++ return -EINVAL;
++ }
++
++ lvs = devm_kzalloc(&intf->dev, sizeof(*lvs), GFP_KERNEL);
++ if (!lvs)
++ return -ENOMEM;
++
++ lvs->intf = intf;
++ usb_set_intfdata(intf, lvs);
++
++ /* how many number of ports this root hub has */
++ ret = usb_control_msg(hdev, usb_rcvctrlpipe(hdev, 0),
++ USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB,
++ USB_DT_SS_HUB << 8, 0, &lvs->descriptor,
++ USB_DT_SS_HUB_SIZE, USB_CTRL_GET_TIMEOUT);
++ if (ret < (USB_DT_HUB_NONVAR_SIZE + 2)) {
++ dev_err(&hdev->dev, "wrong root hub descriptor read %d\n", ret);
++ return ret;
++ }
++
++ /* submit urb to poll interrupt endpoint */
++ lvs->urb = usb_alloc_urb(0, GFP_KERNEL);
++ if (!lvs->urb) {
++ dev_err(&intf->dev, "couldn't allocate lvs urb\n");
++ return -ENOMEM;
++ }
++
++ lvs->rh_queue = create_singlethread_workqueue("lvs_rh_queue");
++ if (!lvs->rh_queue) {
++ dev_err(&intf->dev, "couldn't create workqueue\n");
++ ret = -ENOMEM;
++ goto free_urb;
++ }
++
++ INIT_WORK(&lvs->rh_work, lvs_rh_work);
++
++ ret = sysfs_create_group(&intf->dev.kobj, &lvs_attr_group);
++ if (ret < 0) {
++ dev_err(&intf->dev, "Failed to create sysfs node %d\n", ret);
++ goto destroy_queue;
++ }
++
++ pipe = usb_rcvintpipe(hdev, endpoint->bEndpointAddress);
++ maxp = usb_maxpacket(hdev, pipe, usb_pipeout(pipe));
++ usb_fill_int_urb(lvs->urb, hdev, pipe, &lvs->buffer[0], maxp,
++ lvs_rh_irq, lvs, endpoint->bInterval);
++
++ ret = usb_submit_urb(lvs->urb, GFP_KERNEL);
++ if (ret < 0) {
++ dev_err(&intf->dev, "couldn't submit lvs urb %d\n", ret);
++ goto sysfs_remove;
++ }
++
++ return ret;
++
++sysfs_remove:
++ sysfs_remove_group(&intf->dev.kobj, &lvs_attr_group);
++destroy_queue:
++ destroy_workqueue(lvs->rh_queue);
++free_urb:
++ usb_free_urb(lvs->urb);
++ return ret;
++}
++
++static void lvs_rh_disconnect(struct usb_interface *intf)
++{
++ struct lvs_rh *lvs = usb_get_intfdata(intf);
++
++ sysfs_remove_group(&intf->dev.kobj, &lvs_attr_group);
++ destroy_workqueue(lvs->rh_queue);
++ usb_free_urb(lvs->urb);
++}
++
++static struct usb_driver lvs_driver = {
++ .name = "lvs",
++ .probe = lvs_rh_probe,
++ .disconnect = lvs_rh_disconnect,
++};
++
++module_usb_driver(lvs_driver);
++
++MODULE_DESCRIPTION("Link Layer Validation System Driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/am35x.c linux-3.14.72/drivers/usb/musb/am35x.c
+--- linux-3.14.72.orig/drivers/usb/musb/am35x.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/am35x.c 2016-06-19 22:11:55.337137907 +0200
+@@ -147,25 +147,25 @@
+ */
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
+ dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+
+ spin_lock_irqsave(&musb->lock, flags);
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_BCON:
+ devctl &= ~MUSB_DEVCTL_SESSION;
+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ if (devctl & MUSB_DEVCTL_BDEVICE) {
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ MUSB_DEV_MODE(musb);
+ } else {
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ MUSB_HST_MODE(musb);
+ }
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
+ MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
+ break;
+@@ -174,7 +174,7 @@
+ if (devctl & MUSB_DEVCTL_BDEVICE)
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ else
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ break;
+ default:
+ break;
+@@ -191,9 +191,9 @@
+
+ /* Never idle if active, or when VBUS timeout is not set as host */
+ if (musb->is_active || (musb->a_wait_bcon == 0 &&
+- musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
++ musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ del_timer(&otg_workaround);
+ last_timer = jiffies;
+ return;
+@@ -206,7 +206,7 @@
+ last_timer = timeout;
+
+ dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ jiffies_to_msecs(timeout - jiffies));
+ mod_timer(&otg_workaround, timeout);
+ }
+@@ -276,27 +276,27 @@
+ * devctl.
+ */
+ musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ WARNING("VBUS error workaround (delay coming)\n");
+ } else if (drvvbus) {
+ MUSB_HST_MODE(musb);
+ otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ portstate(musb->port1_status |= USB_PORT_STAT_POWER);
+ del_timer(&otg_workaround);
+ } else {
+ musb->is_active = 0;
+ MUSB_DEV_MODE(musb);
+ otg->default_a = 0;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
+ }
+
+ /* NOTE: this must complete power-on within 100 ms. */
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
+ drvvbus ? "on" : "off",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ err ? " ERROR" : "",
+ devctl);
+ ret = IRQ_HANDLED;
+@@ -322,7 +322,7 @@
+ }
+
+ /* Poll for ID change */
+- if (musb->xceiv->state == OTG_STATE_B_IDLE)
++ if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+
+ spin_unlock_irqrestore(&musb->lock, flags);
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/blackfin.c linux-3.14.72/drivers/usb/musb/blackfin.c
+--- linux-3.14.72.orig/drivers/usb/musb/blackfin.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/blackfin.c 2016-06-19 22:11:55.337137907 +0200
+@@ -184,8 +184,8 @@
+ }
+
+ /* Start sampling ID pin, when plug is removed from MUSB */
+- if ((musb->xceiv->state == OTG_STATE_B_IDLE
+- || musb->xceiv->state == OTG_STATE_A_WAIT_BCON) ||
++ if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
++ || musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
+ (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
+ mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
+ musb->a_wait_bcon = TIMER_DELAY;
+@@ -204,7 +204,7 @@
+ static u8 toggle;
+
+ spin_lock_irqsave(&musb->lock, flags);
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_IDLE:
+ case OTG_STATE_A_WAIT_BCON:
+ /* Start a new session */
+@@ -218,7 +218,7 @@
+
+ if (!(val & MUSB_DEVCTL_BDEVICE)) {
+ gpio_set_value(musb->config->gpio_vrsel, 1);
+- musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
+ } else {
+ gpio_set_value(musb->config->gpio_vrsel, 0);
+ /* Ignore VBUSERROR and SUSPEND IRQ */
+@@ -228,7 +228,7 @@
+
+ val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
+ musb_writeb(musb->mregs, MUSB_INTRUSB, val);
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ }
+ mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
+ break;
+@@ -244,7 +244,7 @@
+
+ if (!(val & MUSB_DEVCTL_BDEVICE)) {
+ gpio_set_value(musb->config->gpio_vrsel, 1);
+- musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
+ } else {
+ gpio_set_value(musb->config->gpio_vrsel, 0);
+
+@@ -279,13 +279,13 @@
+ break;
+ default:
+ dev_dbg(musb->controller, "%s state not handled\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ break;
+ }
+ spin_unlock_irqrestore(&musb->lock, flags);
+
+ dev_dbg(musb->controller, "state is %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+
+ static void bfin_musb_enable(struct musb *musb)
+@@ -306,7 +306,7 @@
+
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x "
+ /* otg %3x conf %08x prcm %08x */ "\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ musb_readb(musb->mregs, MUSB_DEVCTL));
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/da8xx.c linux-3.14.72/drivers/usb/musb/da8xx.c
+--- linux-3.14.72.orig/drivers/usb/musb/da8xx.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/da8xx.c 2016-06-19 22:11:55.337137907 +0200
+@@ -197,20 +197,20 @@
+ */
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
+ dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+
+ spin_lock_irqsave(&musb->lock, flags);
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_BCON:
+ devctl &= ~MUSB_DEVCTL_SESSION;
+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ if (devctl & MUSB_DEVCTL_BDEVICE) {
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ MUSB_DEV_MODE(musb);
+ } else {
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ MUSB_HST_MODE(musb);
+ }
+ break;
+@@ -225,7 +225,7 @@
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ break;
+ }
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
+ MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
+ break;
+@@ -247,7 +247,7 @@
+ if (devctl & MUSB_DEVCTL_BDEVICE)
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ else
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ break;
+ default:
+ break;
+@@ -264,9 +264,9 @@
+
+ /* Never idle if active, or when VBUS timeout is not set as host */
+ if (musb->is_active || (musb->a_wait_bcon == 0 &&
+- musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
++ musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ del_timer(&otg_workaround);
+ last_timer = jiffies;
+ return;
+@@ -279,7 +279,7 @@
+ last_timer = timeout;
+
+ dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ jiffies_to_msecs(timeout - jiffies));
+ mod_timer(&otg_workaround, timeout);
+ }
+@@ -340,26 +340,26 @@
+ * devctl.
+ */
+ musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ WARNING("VBUS error workaround (delay coming)\n");
+ } else if (drvvbus) {
+ MUSB_HST_MODE(musb);
+ otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ portstate(musb->port1_status |= USB_PORT_STAT_POWER);
+ del_timer(&otg_workaround);
+ } else {
+ musb->is_active = 0;
+ MUSB_DEV_MODE(musb);
+ otg->default_a = 0;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
+ }
+
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
+ drvvbus ? "on" : "off",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ err ? " ERROR" : "",
+ devctl);
+ ret = IRQ_HANDLED;
+@@ -374,7 +374,7 @@
+ musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
+
+ /* Poll for ID change */
+- if (musb->xceiv->state == OTG_STATE_B_IDLE)
++ if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+
+ spin_unlock_irqrestore(&musb->lock, flags);
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/davinci.c linux-3.14.72/drivers/usb/musb/davinci.c
+--- linux-3.14.72.orig/drivers/usb/musb/davinci.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/davinci.c 2016-06-19 22:11:55.337137907 +0200
+@@ -214,10 +214,10 @@
+ */
+ devctl = musb_readb(mregs, MUSB_DEVCTL);
+ dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+
+ spin_lock_irqsave(&musb->lock, flags);
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_VFALL:
+ /* Wait till VBUS falls below SessionEnd (~0.2V); the 1.3 RTL
+ * seems to mis-handle session "start" otherwise (or in our
+@@ -228,7 +228,7 @@
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ break;
+ }
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ musb_writel(musb->ctrl_base, DAVINCI_USB_INT_SET_REG,
+ MUSB_INTR_VBUSERROR << DAVINCI_USB_USBINT_SHIFT);
+ break;
+@@ -251,7 +251,7 @@
+ if (devctl & MUSB_DEVCTL_BDEVICE)
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ else
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ break;
+ default:
+ break;
+@@ -325,20 +325,20 @@
+ * to stop registering in devctl.
+ */
+ musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+ WARNING("VBUS error workaround (delay coming)\n");
+ } else if (drvvbus) {
+ MUSB_HST_MODE(musb);
+ otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ portstate(musb->port1_status |= USB_PORT_STAT_POWER);
+ del_timer(&otg_workaround);
+ } else {
+ musb->is_active = 0;
+ MUSB_DEV_MODE(musb);
+ otg->default_a = 0;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
+ }
+
+@@ -348,7 +348,7 @@
+ davinci_musb_source_power(musb, drvvbus, 0);
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
+ drvvbus ? "on" : "off",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ err ? " ERROR" : "",
+ devctl);
+ retval = IRQ_HANDLED;
+@@ -361,7 +361,7 @@
+ musb_writel(tibase, DAVINCI_USB_EOI_REG, 0);
+
+ /* poll for ID change */
+- if (musb->xceiv->state == OTG_STATE_B_IDLE)
++ if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
+ mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
+
+ spin_unlock_irqrestore(&musb->lock, flags);
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/musb_core.c linux-3.14.72/drivers/usb/musb/musb_core.c
+--- linux-3.14.72.orig/drivers/usb/musb/musb_core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/musb_core.c 2016-06-19 22:11:55.337137907 +0200
+@@ -361,23 +361,23 @@
+ unsigned long flags;
+
+ spin_lock_irqsave(&musb->lock, flags);
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_B_WAIT_ACON:
+ dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
+ musb_g_disconnect(musb);
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ musb->is_active = 0;
+ break;
+ case OTG_STATE_A_SUSPEND:
+ case OTG_STATE_A_WAIT_BCON:
+ dev_dbg(musb->controller, "HNP: %s timeout\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ musb_platform_set_vbus(musb, 0);
+- musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
+ break;
+ default:
+ dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ spin_unlock_irqrestore(&musb->lock, flags);
+ }
+@@ -392,19 +392,19 @@
+ u8 reg;
+
+ dev_dbg(musb->controller, "HNP: stop from %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_PERIPHERAL:
+ musb_g_disconnect(musb);
+ dev_dbg(musb->controller, "HNP: back to %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ break;
+ case OTG_STATE_B_HOST:
+ dev_dbg(musb->controller, "HNP: Disabling HR\n");
+ if (hcd)
+ hcd->self.is_b_host = 0;
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ MUSB_DEV_MODE(musb);
+ reg = musb_readb(mbase, MUSB_POWER);
+ reg |= MUSB_POWER_SUSPENDM;
+@@ -413,7 +413,7 @@
+ break;
+ default:
+ dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+
+ /*
+@@ -450,13 +450,13 @@
+ */
+ if (int_usb & MUSB_INTR_RESUME) {
+ handled = IRQ_HANDLED;
+- dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->state));
++ dev_dbg(musb->controller, "RESUME (%s)\n", usb_otg_state_string(musb->xceiv->otg->state));
+
+ if (devctl & MUSB_DEVCTL_HM) {
+ void __iomem *mbase = musb->mregs;
+ u8 power;
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_SUSPEND:
+ /* remote wakeup? later, GetPortStatus
+ * will stop RESUME signaling
+@@ -484,25 +484,25 @@
+ &musb->finish_resume_work,
+ msecs_to_jiffies(USB_RESUME_TIMEOUT));
+
+- musb->xceiv->state = OTG_STATE_A_HOST;
++ musb->xceiv->otg->state = OTG_STATE_A_HOST;
+ musb->is_active = 1;
+ musb_host_resume_root_hub(musb);
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ musb->is_active = 1;
+ MUSB_DEV_MODE(musb);
+ break;
+ default:
+ WARNING("bogus %s RESUME (%s)\n",
+ "host",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ } else {
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_SUSPEND:
+ /* possibly DISCONNECT is upcoming */
+- musb->xceiv->state = OTG_STATE_A_HOST;
++ musb->xceiv->otg->state = OTG_STATE_A_HOST;
+ musb_host_resume_root_hub(musb);
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+@@ -525,7 +525,7 @@
+ default:
+ WARNING("bogus %s RESUME (%s)\n",
+ "peripheral",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ }
+ }
+@@ -541,7 +541,7 @@
+ }
+
+ dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+
+ /* IRQ arrives from ID pin sense or (later, if VBUS power
+ * is removed) SRP. responses are time critical:
+@@ -552,7 +552,7 @@
+ */
+ musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
+ musb->ep0_stage = MUSB_EP0_START;
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ MUSB_HST_MODE(musb);
+ musb_platform_set_vbus(musb, 1);
+
+@@ -578,7 +578,7 @@
+ * REVISIT: do delays from lots of DEBUG_KERNEL checks
+ * make trouble here, keeping VBUS < 4.4V ?
+ */
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_HOST:
+ /* recovery is dicey once we've gotten past the
+ * initial stages of enumeration, but if VBUS
+@@ -607,7 +607,7 @@
+
+ dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
+ "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ devctl,
+ ({ char *s;
+ switch (devctl & MUSB_DEVCTL_VBUS) {
+@@ -632,10 +632,10 @@
+
+ if (int_usb & MUSB_INTR_SUSPEND) {
+ dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x\n",
+- usb_otg_state_string(musb->xceiv->state), devctl);
++ usb_otg_state_string(musb->xceiv->otg->state), devctl);
+ handled = IRQ_HANDLED;
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_PERIPHERAL:
+ /* We also come here if the cable is removed, since
+ * this silicon doesn't report ID-no-longer-grounded.
+@@ -659,7 +659,7 @@
+ musb_g_suspend(musb);
+ musb->is_active = musb->g.b_hnp_enable;
+ if (musb->is_active) {
+- musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
++ musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
+ dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
+ mod_timer(&musb->otg_timer, jiffies
+ + msecs_to_jiffies(
+@@ -672,7 +672,7 @@
+ + msecs_to_jiffies(musb->a_wait_bcon));
+ break;
+ case OTG_STATE_A_HOST:
+- musb->xceiv->state = OTG_STATE_A_SUSPEND;
++ musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
+ musb->is_active = musb->hcd->self.b_hnp_enable;
+ break;
+ case OTG_STATE_B_HOST:
+@@ -715,7 +715,7 @@
+ musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
+
+ /* indicate new connection to OTG machine */
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_B_PERIPHERAL:
+ if (int_usb & MUSB_INTR_SUSPEND) {
+ dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
+@@ -727,7 +727,7 @@
+ case OTG_STATE_B_WAIT_ACON:
+ dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
+ b_host:
+- musb->xceiv->state = OTG_STATE_B_HOST;
++ musb->xceiv->otg->state = OTG_STATE_B_HOST;
+ if (musb->hcd)
+ musb->hcd->self.is_b_host = 1;
+ del_timer(&musb->otg_timer);
+@@ -735,7 +735,7 @@
+ default:
+ if ((devctl & MUSB_DEVCTL_VBUS)
+ == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
+- musb->xceiv->state = OTG_STATE_A_HOST;
++ musb->xceiv->otg->state = OTG_STATE_A_HOST;
+ if (hcd)
+ hcd->self.is_b_host = 0;
+ }
+@@ -745,16 +745,16 @@
+ musb_host_poke_root_hub(musb);
+
+ dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
+- usb_otg_state_string(musb->xceiv->state), devctl);
++ usb_otg_state_string(musb->xceiv->otg->state), devctl);
+ }
+
+ if (int_usb & MUSB_INTR_DISCONNECT) {
+ dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ MUSB_MODE(musb), devctl);
+ handled = IRQ_HANDLED;
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_HOST:
+ case OTG_STATE_A_SUSPEND:
+ musb_host_resume_root_hub(musb);
+@@ -772,7 +772,7 @@
+ musb_root_disconnect(musb);
+ if (musb->hcd)
+ musb->hcd->self.is_b_host = 0;
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ MUSB_DEV_MODE(musb);
+ musb_g_disconnect(musb);
+ break;
+@@ -788,7 +788,7 @@
+ break;
+ default:
+ WARNING("unhandled DISCONNECT transition (%s)\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ break;
+ }
+ }
+@@ -814,15 +814,15 @@
+ }
+ } else {
+ dev_dbg(musb->controller, "BUS RESET as %s\n",
+- usb_otg_state_string(musb->xceiv->state));
+- switch (musb->xceiv->state) {
++ usb_otg_state_string(musb->xceiv->otg->state));
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_SUSPEND:
+ musb_g_reset(musb);
+ /* FALLTHROUGH */
+ case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
+ /* never use invalid T(a_wait_bcon) */
+ dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ TA_WAIT_BCON(musb));
+ mod_timer(&musb->otg_timer, jiffies
+ + msecs_to_jiffies(TA_WAIT_BCON(musb)));
+@@ -833,19 +833,19 @@
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+ dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
+- usb_otg_state_string(musb->xceiv->state));
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ usb_otg_state_string(musb->xceiv->otg->state));
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ musb_g_reset(musb);
+ break;
+ case OTG_STATE_B_IDLE:
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ /* FALLTHROUGH */
+ case OTG_STATE_B_PERIPHERAL:
+ musb_g_reset(musb);
+ break;
+ default:
+ dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ }
+ }
+@@ -1629,7 +1629,7 @@
+ int ret = -EINVAL;
+
+ spin_lock_irqsave(&musb->lock, flags);
+- ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->state));
++ ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
+ spin_unlock_irqrestore(&musb->lock, flags);
+
+ return ret;
+@@ -1674,7 +1674,7 @@
+ spin_lock_irqsave(&musb->lock, flags);
+ /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
+ musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
+- if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
++ if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
+ musb->is_active = 0;
+ musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
+ spin_unlock_irqrestore(&musb->lock, flags);
+@@ -1742,8 +1742,8 @@
+ {
+ struct musb *musb = container_of(data, struct musb, irq_work);
+
+- if (musb->xceiv->state != musb->xceiv_old_state) {
+- musb->xceiv_old_state = musb->xceiv->state;
++ if (musb->xceiv->otg->state != musb->xceiv_old_state) {
++ musb->xceiv_old_state = musb->xceiv->otg->state;
+ sysfs_notify(&musb->controller->kobj, NULL, "mode");
+ }
+ }
+@@ -1951,10 +1951,10 @@
+
+ if (musb->xceiv->otg->default_a) {
+ MUSB_HST_MODE(musb);
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ } else {
+ MUSB_DEV_MODE(musb);
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ }
+
+ switch (musb->port_mode) {
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/musb_dsps.c linux-3.14.72/drivers/usb/musb/musb_dsps.c
+--- linux-3.14.72.orig/drivers/usb/musb/musb_dsps.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/musb_dsps.c 2016-06-19 22:11:55.337137907 +0200
+@@ -148,9 +148,9 @@
+
+ /* Never idle if active, or when VBUS timeout is not set as host */
+ if (musb->is_active || (musb->a_wait_bcon == 0 &&
+- musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
++ musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ del_timer(&glue->timer);
+ glue->last_timer = jiffies;
+ return;
+@@ -170,7 +170,7 @@
+ glue->last_timer = timeout;
+
+ dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ jiffies_to_msecs(timeout - jiffies));
+ mod_timer(&glue->timer, timeout);
+ }
+@@ -234,10 +234,10 @@
+ */
+ devctl = dsps_readb(mregs, MUSB_DEVCTL);
+ dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+
+ spin_lock_irqsave(&musb->lock, flags);
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_BCON:
+ dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
+ skip_session = 1;
+@@ -246,10 +246,10 @@
+ case OTG_STATE_A_IDLE:
+ case OTG_STATE_B_IDLE:
+ if (devctl & MUSB_DEVCTL_BDEVICE) {
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ MUSB_DEV_MODE(musb);
+ } else {
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ MUSB_HST_MODE(musb);
+ }
+ if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
+@@ -257,7 +257,7 @@
+ mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ dsps_writel(musb->ctrl_base, wrp->coreintr_set,
+ MUSB_INTR_VBUSERROR << wrp->usb_shift);
+ break;
+@@ -330,26 +330,26 @@
+ * devctl.
+ */
+ musb->int_usb &= ~MUSB_INTR_VBUSERROR;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
+ mod_timer(&glue->timer,
+ jiffies + wrp->poll_seconds * HZ);
+ WARNING("VBUS error workaround (delay coming)\n");
+ } else if (drvvbus) {
+ MUSB_HST_MODE(musb);
+ musb->xceiv->otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ del_timer(&glue->timer);
+ } else {
+ musb->is_active = 0;
+ MUSB_DEV_MODE(musb);
+ musb->xceiv->otg->default_a = 0;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ }
+
+ /* NOTE: this must complete power-on within 100 ms. */
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
+ drvvbus ? "on" : "off",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ err ? " ERROR" : "",
+ devctl);
+ ret = IRQ_HANDLED;
+@@ -359,7 +359,7 @@
+ ret |= musb_interrupt(musb);
+
+ /* Poll for ID change in OTG port mode */
+- if (musb->xceiv->state == OTG_STATE_B_IDLE &&
++ if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
+ musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
+ mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
+ out:
+@@ -733,7 +733,7 @@
+ dsps_writel(mbase, wrp->mode, glue->context.mode);
+ dsps_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
+ dsps_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
+- if (musb->xceiv->state == OTG_STATE_B_IDLE &&
++ if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
+ musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
+ mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
+
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/musb_gadget.c linux-3.14.72/drivers/usb/musb/musb_gadget.c
+--- linux-3.14.72.orig/drivers/usb/musb/musb_gadget.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/musb_gadget.c 2016-06-19 22:11:55.337137907 +0200
+@@ -1546,7 +1546,7 @@
+
+ spin_lock_irqsave(&musb->lock, flags);
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_B_PERIPHERAL:
+ /* NOTE: OTG state machine doesn't include B_SUSPENDED;
+ * that's part of the standard usb 1.1 state machine, and
+@@ -1587,7 +1587,7 @@
+ goto done;
+ default:
+ dev_dbg(musb->controller, "Unhandled wake: %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ goto done;
+ }
+
+@@ -1792,7 +1792,7 @@
+
+ MUSB_DEV_MODE(musb);
+ musb->xceiv->otg->default_a = 0;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+
+ /* this "gadget" abstracts/virtualizes the controller */
+ musb->g.name = musb_driver_name;
+@@ -1860,7 +1860,7 @@
+ musb->is_active = 1;
+
+ otg_set_peripheral(otg, &musb->g);
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ spin_unlock_irqrestore(&musb->lock, flags);
+
+ musb_start(musb);
+@@ -1945,7 +1945,7 @@
+
+ (void) musb_gadget_vbus_draw(&musb->g, 0);
+
+- musb->xceiv->state = OTG_STATE_UNDEFINED;
++ musb->xceiv->otg->state = OTG_STATE_UNDEFINED;
+ stop_activity(musb, driver);
+ otg_set_peripheral(musb->xceiv->otg, NULL);
+
+@@ -1975,7 +1975,7 @@
+ void musb_g_resume(struct musb *musb)
+ {
+ musb->is_suspended = 0;
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_B_IDLE:
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+@@ -1989,7 +1989,7 @@
+ break;
+ default:
+ WARNING("unhandled RESUME transition (%s)\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ }
+
+@@ -2001,10 +2001,10 @@
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_B_IDLE:
+ if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ break;
+ case OTG_STATE_B_PERIPHERAL:
+ musb->is_suspended = 1;
+@@ -2019,7 +2019,7 @@
+ * A_PERIPHERAL may need care too
+ */
+ WARNING("unhandled SUSPEND transition (%s)\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ }
+
+@@ -2050,22 +2050,22 @@
+ spin_lock(&musb->lock);
+ }
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ default:
+ dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
+- usb_otg_state_string(musb->xceiv->state));
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ usb_otg_state_string(musb->xceiv->otg->state));
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ MUSB_HST_MODE(musb);
+ break;
+ case OTG_STATE_A_PERIPHERAL:
+- musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
+ MUSB_HST_MODE(musb);
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+ case OTG_STATE_B_HOST:
+ case OTG_STATE_B_PERIPHERAL:
+ case OTG_STATE_B_IDLE:
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ break;
+ case OTG_STATE_B_SRP_INIT:
+ break;
+@@ -2125,13 +2125,13 @@
+ * In that case, do not rely on devctl for setting
+ * peripheral mode.
+ */
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ musb->g.is_a_peripheral = 0;
+ } else if (devctl & MUSB_DEVCTL_BDEVICE) {
+- musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
+ musb->g.is_a_peripheral = 0;
+ } else {
+- musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
+ musb->g.is_a_peripheral = 1;
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/musb_host.c linux-3.14.72/drivers/usb/musb/musb_host.c
+--- linux-3.14.72.orig/drivers/usb/musb/musb_host.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/musb_host.c 2016-06-19 22:11:55.337137907 +0200
+@@ -2440,7 +2440,7 @@
+ if (!is_host_active(musb))
+ return 0;
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_SUSPEND:
+ return 0;
+ case OTG_STATE_A_WAIT_VRISE:
+@@ -2450,7 +2450,7 @@
+ */
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
+- musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
+ break;
+ default:
+ break;
+@@ -2458,7 +2458,7 @@
+
+ if (musb->is_active) {
+ WARNING("trying to suspend as %s while active\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ return -EBUSY;
+ } else
+ return 0;
+@@ -2654,7 +2654,7 @@
+
+ MUSB_HST_MODE(musb);
+ musb->xceiv->otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+
+ otg_set_host(musb->xceiv->otg, &hcd->self);
+ hcd->self.otg_port = 1;
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/musb_virthub.c linux-3.14.72/drivers/usb/musb/musb_virthub.c
+--- linux-3.14.72.orig/drivers/usb/musb/musb_virthub.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/musb_virthub.c 2016-06-19 22:11:55.341137644 +0200
+@@ -69,7 +69,7 @@
+ musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
+ usb_hcd_poll_rh_status(musb->hcd);
+ /* NOTE: it might really be A_WAIT_BCON ... */
+- musb->xceiv->state = OTG_STATE_A_HOST;
++ musb->xceiv->otg->state = OTG_STATE_A_HOST;
+
+ spin_unlock_irqrestore(&musb->lock, flags);
+ }
+@@ -107,9 +107,9 @@
+ dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
+
+ musb->port1_status |= USB_PORT_STAT_SUSPEND;
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_HOST:
+- musb->xceiv->state = OTG_STATE_A_SUSPEND;
++ musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
+ musb->is_active = otg->host->b_hnp_enable;
+ if (musb->is_active)
+ mod_timer(&musb->otg_timer, jiffies
+@@ -118,13 +118,13 @@
+ musb_platform_try_idle(musb, 0);
+ break;
+ case OTG_STATE_B_HOST:
+- musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
++ musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
+ musb->is_active = otg->host->b_hnp_enable;
+ musb_platform_try_idle(musb, 0);
+ break;
+ default:
+ dev_dbg(musb->controller, "bogus rh suspend? %s\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ } else if (power & MUSB_POWER_SUSPENDM) {
+ power &= ~MUSB_POWER_SUSPENDM;
+@@ -145,7 +145,7 @@
+ u8 power;
+ void __iomem *mbase = musb->mregs;
+
+- if (musb->xceiv->state == OTG_STATE_B_IDLE) {
++ if (musb->xceiv->otg->state == OTG_STATE_B_IDLE) {
+ dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
+ musb->port1_status &= ~USB_PORT_STAT_RESET;
+ return;
+@@ -224,24 +224,24 @@
+ usb_hcd_poll_rh_status(musb->hcd);
+ musb->is_active = 0;
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_SUSPEND:
+ if (otg->host->b_hnp_enable) {
+- musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
++ musb->xceiv->otg->state = OTG_STATE_A_PERIPHERAL;
+ musb->g.is_a_peripheral = 1;
+ break;
+ }
+ /* FALLTHROUGH */
+ case OTG_STATE_A_HOST:
+- musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
+ musb->is_active = 0;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ break;
+ default:
+ dev_dbg(musb->controller, "host disconnect (%s)\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ }
+
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/omap2430.c linux-3.14.72/drivers/usb/musb/omap2430.c
+--- linux-3.14.72.orig/drivers/usb/musb/omap2430.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/omap2430.c 2016-06-19 22:11:55.341137644 +0200
+@@ -65,15 +65,15 @@
+
+ spin_lock_irqsave(&musb->lock, flags);
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_BCON:
+
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ if (devctl & MUSB_DEVCTL_BDEVICE) {
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ MUSB_DEV_MODE(musb);
+ } else {
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ MUSB_HST_MODE(musb);
+ }
+ break;
+@@ -90,15 +90,15 @@
+ musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
+ usb_hcd_poll_rh_status(musb->hcd);
+ /* NOTE: it might really be A_WAIT_BCON ... */
+- musb->xceiv->state = OTG_STATE_A_HOST;
++ musb->xceiv->otg->state = OTG_STATE_A_HOST;
+ }
+ break;
+ case OTG_STATE_A_HOST:
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+ if (devctl & MUSB_DEVCTL_BDEVICE)
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ else
+- musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
+ default:
+ break;
+ }
+@@ -116,9 +116,9 @@
+
+ /* Never idle if active, or when VBUS timeout is not set as host */
+ if (musb->is_active || ((musb->a_wait_bcon == 0)
+- && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
++ && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ del_timer(&musb_idle_timer);
+ last_timer = jiffies;
+ return;
+@@ -135,7 +135,7 @@
+ last_timer = timeout;
+
+ dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ (unsigned long)jiffies_to_msecs(timeout - jiffies));
+ mod_timer(&musb_idle_timer, timeout);
+ }
+@@ -153,7 +153,7 @@
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+
+ if (is_on) {
+- if (musb->xceiv->state == OTG_STATE_A_IDLE) {
++ if (musb->xceiv->otg->state == OTG_STATE_A_IDLE) {
+ int loops = 100;
+ /* start the session */
+ devctl |= MUSB_DEVCTL_SESSION;
+@@ -179,7 +179,7 @@
+ } else {
+ musb->is_active = 1;
+ otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ devctl |= MUSB_DEVCTL_SESSION;
+ MUSB_HST_MODE(musb);
+ }
+@@ -191,7 +191,7 @@
+ */
+
+ otg->default_a = 0;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ devctl &= ~MUSB_DEVCTL_SESSION;
+
+ MUSB_DEV_MODE(musb);
+@@ -200,7 +200,7 @@
+
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x "
+ /* otg %3x conf %08x prcm %08x */ "\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ musb_readb(musb->mregs, MUSB_DEVCTL));
+ }
+
+@@ -265,7 +265,7 @@
+ dev_dbg(dev, "ID GND\n");
+
+ otg->default_a = true;
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ musb->xceiv->last_event = USB_EVENT_ID;
+ if (musb->gadget_driver) {
+ pm_runtime_get_sync(dev);
+@@ -279,7 +279,7 @@
+ dev_dbg(dev, "VBUS Connect\n");
+
+ otg->default_a = false;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ musb->xceiv->last_event = USB_EVENT_VBUS;
+ if (musb->gadget_driver)
+ pm_runtime_get_sync(dev);
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/tusb6010.c linux-3.14.72/drivers/usb/musb/tusb6010.c
+--- linux-3.14.72.orig/drivers/usb/musb/tusb6010.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/tusb6010.c 2016-06-19 22:11:55.341137644 +0200
+@@ -416,13 +416,13 @@
+
+ spin_lock_irqsave(&musb->lock, flags);
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_BCON:
+ if ((musb->a_wait_bcon != 0)
+ && (musb->idle_timeout == 0
+ || time_after(jiffies, musb->idle_timeout))) {
+ dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ }
+ /* FALLTHROUGH */
+ case OTG_STATE_A_IDLE:
+@@ -475,9 +475,9 @@
+
+ /* Never idle if active, or when VBUS timeout is not set as host */
+ if (musb->is_active || ((musb->a_wait_bcon == 0)
+- && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
++ && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+- usb_otg_state_string(musb->xceiv->state));
++ usb_otg_state_string(musb->xceiv->otg->state));
+ del_timer(&musb_idle_timer);
+ last_timer = jiffies;
+ return;
+@@ -494,7 +494,7 @@
+ last_timer = timeout;
+
+ dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ (unsigned long)jiffies_to_msecs(timeout - jiffies));
+ mod_timer(&musb_idle_timer, timeout);
+ }
+@@ -525,7 +525,7 @@
+ if (is_on) {
+ timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
+ otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ devctl |= MUSB_DEVCTL_SESSION;
+
+ conf |= TUSB_DEV_CONF_USB_HOST_MODE;
+@@ -538,16 +538,16 @@
+ /* If ID pin is grounded, we want to be a_idle */
+ otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
+ if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_VRISE:
+ case OTG_STATE_A_WAIT_BCON:
+- musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ break;
+ default:
+- musb->xceiv->state = OTG_STATE_A_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_A_IDLE;
+ }
+ musb->is_active = 0;
+ otg->default_a = 1;
+@@ -555,7 +555,7 @@
+ } else {
+ musb->is_active = 0;
+ otg->default_a = 0;
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ MUSB_DEV_MODE(musb);
+ }
+
+@@ -570,7 +570,7 @@
+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ musb_readb(musb->mregs, MUSB_DEVCTL),
+ musb_readl(tbase, TUSB_DEV_OTG_STAT),
+ conf, prcm);
+@@ -669,23 +669,23 @@
+
+ if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
+ dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
+- if (musb->xceiv->state != OTG_STATE_B_IDLE) {
++ if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
+ /* INTR_DISCONNECT can hide... */
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ musb->int_usb |= MUSB_INTR_DISCONNECT;
+ }
+ musb->is_active = 0;
+ }
+ dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
+- usb_otg_state_string(musb->xceiv->state), otg_stat);
++ usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
+ idle_timeout = jiffies + (1 * HZ);
+ schedule_work(&musb->irq_work);
+
+ } else /* A-dev state machine */ {
+ dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
+- usb_otg_state_string(musb->xceiv->state), otg_stat);
++ usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_IDLE:
+ dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
+ musb_platform_set_vbus(musb, 1);
+@@ -732,9 +732,9 @@
+ u8 devctl;
+
+ dev_dbg(musb->controller, "%s timer, %03x\n",
+- usb_otg_state_string(musb->xceiv->state), otg_stat);
++ usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
+
+- switch (musb->xceiv->state) {
++ switch (musb->xceiv->otg->state) {
+ case OTG_STATE_A_WAIT_VRISE:
+ /* VBUS has probably been valid for a while now,
+ * but may well have bounced out of range a bit
+@@ -746,7 +746,7 @@
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
+ break;
+ }
+- musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
+ musb->is_active = 0;
+ idle_timeout = jiffies
+ + msecs_to_jiffies(musb->a_wait_bcon);
+diff -Nur linux-3.14.72.orig/drivers/usb/musb/ux500.c linux-3.14.72/drivers/usb/musb/ux500.c
+--- linux-3.14.72.orig/drivers/usb/musb/ux500.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/musb/ux500.c 2016-06-19 22:11:55.341137644 +0200
+@@ -56,7 +56,7 @@
+ devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
+
+ if (is_on) {
+- if (musb->xceiv->state == OTG_STATE_A_IDLE) {
++ if (musb->xceiv->otg->state == OTG_STATE_A_IDLE) {
+ /* start the session */
+ devctl |= MUSB_DEVCTL_SESSION;
+ musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+@@ -76,7 +76,7 @@
+ } else {
+ musb->is_active = 1;
+ musb->xceiv->otg->default_a = 1;
+- musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
++ musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
+ devctl |= MUSB_DEVCTL_SESSION;
+ MUSB_HST_MODE(musb);
+ }
+@@ -102,7 +102,7 @@
+ mdelay(200);
+
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x\n",
+- usb_otg_state_string(musb->xceiv->state),
++ usb_otg_state_string(musb->xceiv->otg->state),
+ musb_readb(musb->mregs, MUSB_DEVCTL));
+ }
+
+@@ -112,7 +112,7 @@
+ struct musb *musb = container_of(nb, struct musb, nb);
+
+ dev_dbg(musb->controller, "musb_otg_notifications %ld %s\n",
+- event, usb_otg_state_string(musb->xceiv->state));
++ event, usb_otg_state_string(musb->xceiv->otg->state));
+
+ switch (event) {
+ case UX500_MUSB_ID:
+@@ -127,7 +127,7 @@
+ if (is_host_active(musb))
+ ux500_musb_set_vbus(musb, 0);
+ else
+- musb->xceiv->state = OTG_STATE_B_IDLE;
++ musb->xceiv->otg->state = OTG_STATE_B_IDLE;
+ break;
+ default:
+ dev_dbg(musb->controller, "ID float\n");
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/Kconfig linux-3.14.72/drivers/usb/phy/Kconfig
+--- linux-3.14.72.orig/drivers/usb/phy/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/Kconfig 2016-06-19 22:11:55.341137644 +0200
+@@ -6,15 +6,6 @@
+ config USB_PHY
+ def_bool n
+
+-config USB_OTG_FSM
+- tristate "USB 2.0 OTG FSM implementation"
+- depends on USB
+- select USB_OTG
+- select USB_PHY
+- help
+- Implements OTG Final State Machine as specified in On-The-Go
+- and Embedded Host Supplement to the USB Revision 2.0 Specification.
+-
+ #
+ # USB Transceiver Drivers
+ #
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/Makefile linux-3.14.72/drivers/usb/phy/Makefile
+--- linux-3.14.72.orig/drivers/usb/phy/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/Makefile 2016-06-19 22:11:55.341137644 +0200
+@@ -3,7 +3,6 @@
+ #
+ obj-$(CONFIG_USB_PHY) += phy.o
+ obj-$(CONFIG_OF) += of.o
+-obj-$(CONFIG_USB_OTG_FSM) += phy-fsm-usb.o
+
+ # transceiver drivers, keep the list sorted
+
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-ab8500-usb.c linux-3.14.72/drivers/usb/phy/phy-ab8500-usb.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-ab8500-usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-ab8500-usb.c 2016-06-19 22:11:55.341137644 +0200
+@@ -446,7 +446,7 @@
+ if (event != UX500_MUSB_RIDB)
+ event = UX500_MUSB_NONE;
+ /* Fallback to default B_IDLE as nothing is connected. */
+- ab->phy.state = OTG_STATE_B_IDLE;
++ ab->phy.otg->state = OTG_STATE_B_IDLE;
+ break;
+
+ case USB_LINK_ACA_RID_C_NM_9540:
+@@ -584,7 +584,7 @@
+ * Fallback to default B_IDLE as nothing
+ * is connected
+ */
+- ab->phy.state = OTG_STATE_B_IDLE;
++ ab->phy.otg->state = OTG_STATE_B_IDLE;
+ break;
+
+ case USB_LINK_ACA_RID_C_NM_8540:
+@@ -693,7 +693,7 @@
+ * Fallback to default B_IDLE as nothing
+ * is connected
+ */
+- ab->phy.state = OTG_STATE_B_IDLE;
++ ab->phy.otg->state = OTG_STATE_B_IDLE;
+ break;
+
+ case USB_LINK_ACA_RID_C_NM_8505:
+@@ -776,7 +776,7 @@
+ if (event != UX500_MUSB_RIDB)
+ event = UX500_MUSB_NONE;
+ /* Fallback to default B_IDLE as nothing is connected */
+- ab->phy.state = OTG_STATE_B_IDLE;
++ ab->phy.otg->state = OTG_STATE_B_IDLE;
+ break;
+
+ case USB_LINK_ACA_RID_C_NM_8500:
+@@ -1056,7 +1056,7 @@
+ if (!otg)
+ return -ENODEV;
+
+- ab = phy_to_ab(otg->phy);
++ ab = phy_to_ab(otg->usb_phy);
+
+ ab->phy.otg->gadget = gadget;
+
+@@ -1080,7 +1080,7 @@
+ if (!otg)
+ return -ENODEV;
+
+- ab = phy_to_ab(otg->phy);
++ ab = phy_to_ab(otg->usb_phy);
+
+ ab->phy.otg->host = host;
+
+@@ -1380,9 +1380,9 @@
+ ab->phy.label = "ab8500";
+ ab->phy.set_suspend = ab8500_usb_set_suspend;
+ ab->phy.set_power = ab8500_usb_set_power;
+- ab->phy.state = OTG_STATE_UNDEFINED;
++ ab->phy.otg->state = OTG_STATE_UNDEFINED;
+
+- otg->phy = &ab->phy;
++ otg->usb_phy = &ab->phy;
+ otg->set_host = ab8500_usb_set_host;
+ otg->set_peripheral = ab8500_usb_set_peripheral;
+
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy.c linux-3.14.72/drivers/usb/phy/phy.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy.c 2016-06-19 22:11:55.341137644 +0200
+@@ -190,7 +190,9 @@
+
+ phy = __of_usb_find_phy(node);
+ if (IS_ERR(phy) || !try_module_get(phy->dev->driver->owner)) {
+- phy = ERR_PTR(-EPROBE_DEFER);
++ if (!IS_ERR(phy))
++ phy = ERR_PTR(-EPROBE_DEFER);
++
+ devres_free(ptr);
+ goto err1;
+ }
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-fsl-usb.c linux-3.14.72/drivers/usb/phy/phy-fsl-usb.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-fsl-usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-fsl-usb.c 2016-06-19 22:11:55.341137644 +0200
+@@ -274,7 +274,7 @@
+ fsl_otg_dischrg_vbus(0);
+ srp_wait_done = 1;
+
+- if ((fsl_otg_dev->phy.state == OTG_STATE_B_SRP_INIT) &&
++ if ((fsl_otg_dev->phy.otg->state == OTG_STATE_B_SRP_INIT) &&
+ fsl_otg_dev->fsm.b_sess_vld)
+ fsl_otg_dev->fsm.b_srp_done = 1;
+ }
+@@ -499,7 +499,8 @@
+ {
+ struct usb_otg *otg = fsm->otg;
+ struct device *dev;
+- struct fsl_otg *otg_dev = container_of(otg->phy, struct fsl_otg, phy);
++ struct fsl_otg *otg_dev =
++ container_of(otg->usb_phy, struct fsl_otg, phy);
+ u32 retval = 0;
+
+ if (!otg->host)
+@@ -594,7 +595,7 @@
+ if (!otg)
+ return -ENODEV;
+
+- otg_dev = container_of(otg->phy, struct fsl_otg, phy);
++ otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
+ if (otg_dev != fsl_otg_dev)
+ return -ENODEV;
+
+@@ -623,7 +624,7 @@
+ /* Mini-A cable connected */
+ struct otg_fsm *fsm = &otg_dev->fsm;
+
+- otg->phy->state = OTG_STATE_UNDEFINED;
++ otg->state = OTG_STATE_UNDEFINED;
+ fsm->protocol = PROTO_UNDEF;
+ }
+ }
+@@ -644,7 +645,7 @@
+ if (!otg)
+ return -ENODEV;
+
+- otg_dev = container_of(otg->phy, struct fsl_otg, phy);
++ otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
+ VDBG("otg_dev 0x%x\n", (int)otg_dev);
+ VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
+ if (otg_dev != fsl_otg_dev)
+@@ -681,7 +682,7 @@
+ {
+ if (!fsl_otg_dev)
+ return -ENODEV;
+- if (phy->state == OTG_STATE_B_PERIPHERAL)
++ if (phy->otg->state == OTG_STATE_B_PERIPHERAL)
+ pr_info("FSL OTG: Draw %d mA\n", mA);
+
+ return 0;
+@@ -714,10 +715,10 @@
+ {
+ struct fsl_otg *otg_dev;
+
+- if (!otg || otg->phy->state != OTG_STATE_B_IDLE)
++ if (!otg || otg->state != OTG_STATE_B_IDLE)
+ return -ENODEV;
+
+- otg_dev = container_of(otg->phy, struct fsl_otg, phy);
++ otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
+ if (otg_dev != fsl_otg_dev)
+ return -ENODEV;
+
+@@ -735,7 +736,7 @@
+ if (!otg)
+ return -ENODEV;
+
+- otg_dev = container_of(otg->phy, struct fsl_otg, phy);
++ otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
+ if (otg_dev != fsl_otg_dev)
+ return -ENODEV;
+
+@@ -857,7 +858,7 @@
+ fsl_otg_tc->phy.dev = &pdev->dev;
+ fsl_otg_tc->phy.set_power = fsl_otg_set_power;
+
+- fsl_otg_tc->phy.otg->phy = &fsl_otg_tc->phy;
++ fsl_otg_tc->phy.otg->usb_phy = &fsl_otg_tc->phy;
+ fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host;
+ fsl_otg_tc->phy.otg->set_peripheral = fsl_otg_set_peripheral;
+ fsl_otg_tc->phy.otg->start_hnp = fsl_otg_start_hnp;
+@@ -989,10 +990,10 @@
+ * Also: record initial state of ID pin
+ */
+ if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
+- p_otg->phy.state = OTG_STATE_UNDEFINED;
++ p_otg->phy.otg->state = OTG_STATE_UNDEFINED;
+ p_otg->fsm.id = 1;
+ } else {
+- p_otg->phy.state = OTG_STATE_A_IDLE;
++ p_otg->phy.otg->state = OTG_STATE_A_IDLE;
+ p_otg->fsm.id = 0;
+ }
+
+@@ -1047,7 +1048,7 @@
+ /* State */
+ t = scnprintf(next, size,
+ "OTG state: %s\n\n",
+- usb_otg_state_string(fsl_otg_dev->phy.state));
++ usb_otg_state_string(fsl_otg_dev->phy.otg->state));
+ size -= t;
+ next += t;
+
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-fsl-usb.h linux-3.14.72/drivers/usb/phy/phy-fsl-usb.h
+--- linux-3.14.72.orig/drivers/usb/phy/phy-fsl-usb.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-fsl-usb.h 2016-06-19 22:11:55.341137644 +0200
+@@ -298,7 +298,7 @@
+ /* SE0 Time Before SRP */
+ #define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
+
+-#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
++#define SET_OTG_STATE(phy, newstate) ((phy)->otg->state = newstate)
+
+ struct usb_dr_mmap {
+ /* Capability register */
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-fsm-usb.c linux-3.14.72/drivers/usb/phy/phy-fsm-usb.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-fsm-usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-fsm-usb.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,364 +0,0 @@
+-/*
+- * OTG Finite State Machine from OTG spec
+- *
+- * Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
+- *
+- * Author: Li Yang <LeoLi@freescale.com>
+- * Jerry Huang <Chang-Ming.Huang@freescale.com>
+- *
+- * This program is free software; you can redistribute it and/or modify it
+- * under the terms of the GNU General Public License as published by the
+- * Free Software Foundation; either version 2 of the License, or (at your
+- * option) any later version.
+- *
+- * This program is distributed in the hope that it will be useful, but
+- * WITHOUT ANY WARRANTY; without even the implied warranty of
+- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+- * General Public License for more details.
+- *
+- * You should have received a copy of the GNU General Public License along
+- * with this program; if not, write to the Free Software Foundation, Inc.,
+- * 675 Mass Ave, Cambridge, MA 02139, USA.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/types.h>
+-#include <linux/mutex.h>
+-#include <linux/delay.h>
+-#include <linux/usb.h>
+-#include <linux/usb/gadget.h>
+-#include <linux/usb/otg.h>
+-#include <linux/usb/otg-fsm.h>
+-
+-/* Change USB protocol when there is a protocol change */
+-static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
+-{
+- int ret = 0;
+-
+- if (fsm->protocol != protocol) {
+- VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
+- fsm->protocol, protocol);
+- /* stop old protocol */
+- if (fsm->protocol == PROTO_HOST)
+- ret = otg_start_host(fsm, 0);
+- else if (fsm->protocol == PROTO_GADGET)
+- ret = otg_start_gadget(fsm, 0);
+- if (ret)
+- return ret;
+-
+- /* start new protocol */
+- if (protocol == PROTO_HOST)
+- ret = otg_start_host(fsm, 1);
+- else if (protocol == PROTO_GADGET)
+- ret = otg_start_gadget(fsm, 1);
+- if (ret)
+- return ret;
+-
+- fsm->protocol = protocol;
+- return 0;
+- }
+-
+- return 0;
+-}
+-
+-static int state_changed;
+-
+-/* Called when leaving a state. Do state clean up jobs here */
+-static void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
+-{
+- switch (old_state) {
+- case OTG_STATE_B_IDLE:
+- otg_del_timer(fsm, B_SE0_SRP);
+- fsm->b_se0_srp = 0;
+- fsm->adp_sns = 0;
+- fsm->adp_prb = 0;
+- break;
+- case OTG_STATE_B_SRP_INIT:
+- fsm->data_pulse = 0;
+- fsm->b_srp_done = 0;
+- break;
+- case OTG_STATE_B_PERIPHERAL:
+- break;
+- case OTG_STATE_B_WAIT_ACON:
+- otg_del_timer(fsm, B_ASE0_BRST);
+- fsm->b_ase0_brst_tmout = 0;
+- break;
+- case OTG_STATE_B_HOST:
+- break;
+- case OTG_STATE_A_IDLE:
+- fsm->adp_prb = 0;
+- break;
+- case OTG_STATE_A_WAIT_VRISE:
+- otg_del_timer(fsm, A_WAIT_VRISE);
+- fsm->a_wait_vrise_tmout = 0;
+- break;
+- case OTG_STATE_A_WAIT_BCON:
+- otg_del_timer(fsm, A_WAIT_BCON);
+- fsm->a_wait_bcon_tmout = 0;
+- break;
+- case OTG_STATE_A_HOST:
+- otg_del_timer(fsm, A_WAIT_ENUM);
+- break;
+- case OTG_STATE_A_SUSPEND:
+- otg_del_timer(fsm, A_AIDL_BDIS);
+- fsm->a_aidl_bdis_tmout = 0;
+- fsm->a_suspend_req_inf = 0;
+- break;
+- case OTG_STATE_A_PERIPHERAL:
+- otg_del_timer(fsm, A_BIDL_ADIS);
+- fsm->a_bidl_adis_tmout = 0;
+- break;
+- case OTG_STATE_A_WAIT_VFALL:
+- otg_del_timer(fsm, A_WAIT_VFALL);
+- fsm->a_wait_vfall_tmout = 0;
+- otg_del_timer(fsm, A_WAIT_VRISE);
+- break;
+- case OTG_STATE_A_VBUS_ERR:
+- break;
+- default:
+- break;
+- }
+-}
+-
+-/* Called when entering a state */
+-static int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
+-{
+- state_changed = 1;
+- if (fsm->otg->phy->state == new_state)
+- return 0;
+- VDBG("Set state: %s\n", usb_otg_state_string(new_state));
+- otg_leave_state(fsm, fsm->otg->phy->state);
+- switch (new_state) {
+- case OTG_STATE_B_IDLE:
+- otg_drv_vbus(fsm, 0);
+- otg_chrg_vbus(fsm, 0);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- /*
+- * Driver is responsible for starting ADP probing
+- * if ADP sensing times out.
+- */
+- otg_start_adp_sns(fsm);
+- otg_set_protocol(fsm, PROTO_UNDEF);
+- otg_add_timer(fsm, B_SE0_SRP);
+- break;
+- case OTG_STATE_B_SRP_INIT:
+- otg_start_pulse(fsm);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_UNDEF);
+- otg_add_timer(fsm, B_SRP_FAIL);
+- break;
+- case OTG_STATE_B_PERIPHERAL:
+- otg_chrg_vbus(fsm, 0);
+- otg_loc_conn(fsm, 1);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_GADGET);
+- break;
+- case OTG_STATE_B_WAIT_ACON:
+- otg_chrg_vbus(fsm, 0);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_HOST);
+- otg_add_timer(fsm, B_ASE0_BRST);
+- fsm->a_bus_suspend = 0;
+- break;
+- case OTG_STATE_B_HOST:
+- otg_chrg_vbus(fsm, 0);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 1);
+- otg_set_protocol(fsm, PROTO_HOST);
+- usb_bus_start_enum(fsm->otg->host,
+- fsm->otg->host->otg_port);
+- break;
+- case OTG_STATE_A_IDLE:
+- otg_drv_vbus(fsm, 0);
+- otg_chrg_vbus(fsm, 0);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- otg_start_adp_prb(fsm);
+- otg_set_protocol(fsm, PROTO_HOST);
+- break;
+- case OTG_STATE_A_WAIT_VRISE:
+- otg_drv_vbus(fsm, 1);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_HOST);
+- otg_add_timer(fsm, A_WAIT_VRISE);
+- break;
+- case OTG_STATE_A_WAIT_BCON:
+- otg_drv_vbus(fsm, 1);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_HOST);
+- otg_add_timer(fsm, A_WAIT_BCON);
+- break;
+- case OTG_STATE_A_HOST:
+- otg_drv_vbus(fsm, 1);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 1);
+- otg_set_protocol(fsm, PROTO_HOST);
+- /*
+- * When HNP is triggered while a_bus_req = 0, a_host will
+- * suspend too fast to complete a_set_b_hnp_en
+- */
+- if (!fsm->a_bus_req || fsm->a_suspend_req_inf)
+- otg_add_timer(fsm, A_WAIT_ENUM);
+- break;
+- case OTG_STATE_A_SUSPEND:
+- otg_drv_vbus(fsm, 1);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_HOST);
+- otg_add_timer(fsm, A_AIDL_BDIS);
+-
+- break;
+- case OTG_STATE_A_PERIPHERAL:
+- otg_loc_conn(fsm, 1);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_GADGET);
+- otg_drv_vbus(fsm, 1);
+- otg_add_timer(fsm, A_BIDL_ADIS);
+- break;
+- case OTG_STATE_A_WAIT_VFALL:
+- otg_drv_vbus(fsm, 0);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_HOST);
+- otg_add_timer(fsm, A_WAIT_VFALL);
+- break;
+- case OTG_STATE_A_VBUS_ERR:
+- otg_drv_vbus(fsm, 0);
+- otg_loc_conn(fsm, 0);
+- otg_loc_sof(fsm, 0);
+- otg_set_protocol(fsm, PROTO_UNDEF);
+- break;
+- default:
+- break;
+- }
+-
+- fsm->otg->phy->state = new_state;
+- return 0;
+-}
+-
+-/* State change judgement */
+-int otg_statemachine(struct otg_fsm *fsm)
+-{
+- enum usb_otg_state state;
+-
+- mutex_lock(&fsm->lock);
+-
+- state = fsm->otg->phy->state;
+- state_changed = 0;
+- /* State machine state change judgement */
+-
+- switch (state) {
+- case OTG_STATE_UNDEFINED:
+- VDBG("fsm->id = %d\n", fsm->id);
+- if (fsm->id)
+- otg_set_state(fsm, OTG_STATE_B_IDLE);
+- else
+- otg_set_state(fsm, OTG_STATE_A_IDLE);
+- break;
+- case OTG_STATE_B_IDLE:
+- if (!fsm->id)
+- otg_set_state(fsm, OTG_STATE_A_IDLE);
+- else if (fsm->b_sess_vld && fsm->otg->gadget)
+- otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+- else if ((fsm->b_bus_req || fsm->adp_change || fsm->power_up) &&
+- fsm->b_ssend_srp && fsm->b_se0_srp)
+- otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
+- break;
+- case OTG_STATE_B_SRP_INIT:
+- if (!fsm->id || fsm->b_srp_done)
+- otg_set_state(fsm, OTG_STATE_B_IDLE);
+- break;
+- case OTG_STATE_B_PERIPHERAL:
+- if (!fsm->id || !fsm->b_sess_vld)
+- otg_set_state(fsm, OTG_STATE_B_IDLE);
+- else if (fsm->b_bus_req && fsm->otg->
+- gadget->b_hnp_enable && fsm->a_bus_suspend)
+- otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
+- break;
+- case OTG_STATE_B_WAIT_ACON:
+- if (fsm->a_conn)
+- otg_set_state(fsm, OTG_STATE_B_HOST);
+- else if (!fsm->id || !fsm->b_sess_vld)
+- otg_set_state(fsm, OTG_STATE_B_IDLE);
+- else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
+- fsm->b_ase0_brst_tmout = 0;
+- otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+- }
+- break;
+- case OTG_STATE_B_HOST:
+- if (!fsm->id || !fsm->b_sess_vld)
+- otg_set_state(fsm, OTG_STATE_B_IDLE);
+- else if (!fsm->b_bus_req || !fsm->a_conn || fsm->test_device)
+- otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+- break;
+- case OTG_STATE_A_IDLE:
+- if (fsm->id)
+- otg_set_state(fsm, OTG_STATE_B_IDLE);
+- else if (!fsm->a_bus_drop && (fsm->a_bus_req ||
+- fsm->a_srp_det || fsm->adp_change || fsm->power_up))
+- otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
+- break;
+- case OTG_STATE_A_WAIT_VRISE:
+- if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
+- fsm->a_wait_vrise_tmout) {
+- otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+- }
+- break;
+- case OTG_STATE_A_WAIT_BCON:
+- if (!fsm->a_vbus_vld)
+- otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+- else if (fsm->b_conn)
+- otg_set_state(fsm, OTG_STATE_A_HOST);
+- else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
+- otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+- break;
+- case OTG_STATE_A_HOST:
+- if ((!fsm->a_bus_req || fsm->a_suspend_req_inf) &&
+- fsm->otg->host->b_hnp_enable)
+- otg_set_state(fsm, OTG_STATE_A_SUSPEND);
+- else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
+- otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+- else if (!fsm->a_vbus_vld)
+- otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+- break;
+- case OTG_STATE_A_SUSPEND:
+- if (!fsm->b_conn && fsm->otg->host->b_hnp_enable)
+- otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
+- else if (!fsm->b_conn && !fsm->otg->host->b_hnp_enable)
+- otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+- else if (fsm->a_bus_req || fsm->b_bus_resume)
+- otg_set_state(fsm, OTG_STATE_A_HOST);
+- else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
+- otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+- else if (!fsm->a_vbus_vld)
+- otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+- break;
+- case OTG_STATE_A_PERIPHERAL:
+- if (fsm->id || fsm->a_bus_drop)
+- otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+- else if (fsm->a_bidl_adis_tmout || fsm->b_bus_suspend)
+- otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+- else if (!fsm->a_vbus_vld)
+- otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+- break;
+- case OTG_STATE_A_WAIT_VFALL:
+- if (fsm->a_wait_vfall_tmout || fsm->id || fsm->a_bus_req ||
+- (!fsm->a_sess_vld && !fsm->b_conn))
+- otg_set_state(fsm, OTG_STATE_A_IDLE);
+- break;
+- case OTG_STATE_A_VBUS_ERR:
+- if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
+- otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+- break;
+- default:
+- break;
+- }
+- mutex_unlock(&fsm->lock);
+-
+- VDBG("quit statemachine, changed = %d\n", state_changed);
+- return state_changed;
+-}
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-generic.c linux-3.14.72/drivers/usb/phy/phy-generic.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-generic.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-generic.c 2016-06-19 22:11:55.341137644 +0200
+@@ -65,6 +65,16 @@
+
+ static int nop_set_suspend(struct usb_phy *x, int suspend)
+ {
++ struct usb_phy_gen_xceiv *nop = dev_get_drvdata(x->dev);
++
++ if (IS_ERR(nop->clk))
++ return 0;
++
++ if (suspend)
++ clk_disable_unprepare(nop->clk);
++ else
++ clk_prepare_enable(nop->clk);
++
+ return 0;
+ }
+
+@@ -132,7 +142,7 @@
+ }
+
+ otg->gadget = gadget;
+- otg->phy->state = OTG_STATE_B_IDLE;
++ otg->state = OTG_STATE_B_IDLE;
+ return 0;
+ }
+
+@@ -234,10 +244,10 @@
+ nop->phy.dev = nop->dev;
+ nop->phy.label = "nop-xceiv";
+ nop->phy.set_suspend = nop_set_suspend;
+- nop->phy.state = OTG_STATE_UNDEFINED;
+ nop->phy.type = type;
+
+- nop->phy.otg->phy = &nop->phy;
++ nop->phy.otg->state = OTG_STATE_UNDEFINED;
++ nop->phy.otg->usb_phy = &nop->phy;
+ nop->phy.otg->set_host = nop_set_host;
+ nop->phy.otg->set_peripheral = nop_set_peripheral;
+
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-gpio-vbus-usb.c linux-3.14.72/drivers/usb/phy/phy-gpio-vbus-usb.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-gpio-vbus-usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-gpio-vbus-usb.c 2016-06-19 22:11:55.341137644 +0200
+@@ -121,7 +121,7 @@
+
+ if (vbus) {
+ status = USB_EVENT_VBUS;
+- gpio_vbus->phy.state = OTG_STATE_B_PERIPHERAL;
++ gpio_vbus->phy.otg->state = OTG_STATE_B_PERIPHERAL;
+ gpio_vbus->phy.last_event = status;
+ usb_gadget_vbus_connect(gpio_vbus->phy.otg->gadget);
+
+@@ -143,7 +143,7 @@
+
+ usb_gadget_vbus_disconnect(gpio_vbus->phy.otg->gadget);
+ status = USB_EVENT_NONE;
+- gpio_vbus->phy.state = OTG_STATE_B_IDLE;
++ gpio_vbus->phy.otg->state = OTG_STATE_B_IDLE;
+ gpio_vbus->phy.last_event = status;
+
+ atomic_notifier_call_chain(&gpio_vbus->phy.notifier,
+@@ -180,7 +180,7 @@
+ struct platform_device *pdev;
+ int gpio;
+
+- gpio_vbus = container_of(otg->phy, struct gpio_vbus_data, phy);
++ gpio_vbus = container_of(otg->usb_phy, struct gpio_vbus_data, phy);
+ pdev = to_platform_device(gpio_vbus->dev);
+ pdata = dev_get_platdata(gpio_vbus->dev);
+ gpio = pdata->gpio_pullup;
+@@ -196,7 +196,7 @@
+ set_vbus_draw(gpio_vbus, 0);
+
+ usb_gadget_vbus_disconnect(otg->gadget);
+- otg->phy->state = OTG_STATE_UNDEFINED;
++ otg->state = OTG_STATE_UNDEFINED;
+
+ otg->gadget = NULL;
+ return 0;
+@@ -218,7 +218,7 @@
+
+ gpio_vbus = container_of(phy, struct gpio_vbus_data, phy);
+
+- if (phy->state == OTG_STATE_B_PERIPHERAL)
++ if (phy->otg->state == OTG_STATE_B_PERIPHERAL)
+ set_vbus_draw(gpio_vbus, mA);
+ return 0;
+ }
+@@ -269,9 +269,9 @@
+ gpio_vbus->phy.dev = gpio_vbus->dev;
+ gpio_vbus->phy.set_power = gpio_vbus_set_power;
+ gpio_vbus->phy.set_suspend = gpio_vbus_set_suspend;
+- gpio_vbus->phy.state = OTG_STATE_UNDEFINED;
+
+- gpio_vbus->phy.otg->phy = &gpio_vbus->phy;
++ gpio_vbus->phy.otg->state = OTG_STATE_UNDEFINED;
++ gpio_vbus->phy.otg->usb_phy = &gpio_vbus->phy;
+ gpio_vbus->phy.otg->set_peripheral = gpio_vbus_set_peripheral;
+
+ err = gpio_request(gpio, "vbus_detect");
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-isp1301-omap.c linux-3.14.72/drivers/usb/phy/phy-isp1301-omap.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-isp1301-omap.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-isp1301-omap.c 2016-06-19 22:11:55.341137644 +0200
+@@ -234,7 +234,7 @@
+
+ static inline const char *state_name(struct isp1301 *isp)
+ {
+- return usb_otg_state_string(isp->phy.state);
++ return usb_otg_state_string(isp->phy.otg->state);
+ }
+
+ /*-------------------------------------------------------------------------*/
+@@ -249,7 +249,7 @@
+
+ static void power_down(struct isp1301 *isp)
+ {
+- isp->phy.state = OTG_STATE_UNDEFINED;
++ isp->phy.otg->state = OTG_STATE_UNDEFINED;
+
+ // isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_SUSPEND);
+@@ -339,7 +339,7 @@
+ {
+ u32 l;
+
+- if (isp->phy.state == OTG_STATE_A_IDLE)
++ if (isp->phy.otg->state == OTG_STATE_A_IDLE)
+ return;
+
+ isp->phy.otg->default_a = 1;
+@@ -351,7 +351,7 @@
+ isp->phy.otg->gadget->is_a_peripheral = 1;
+ gadget_suspend(isp);
+ }
+- isp->phy.state = OTG_STATE_A_IDLE;
++ isp->phy.otg->state = OTG_STATE_A_IDLE;
+ l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+ omap_writel(l, OTG_CTRL);
+ isp->last_otg_ctrl = l;
+@@ -363,7 +363,7 @@
+ {
+ u32 l;
+
+- if (isp->phy.state == OTG_STATE_B_IDLE)
++ if (isp->phy.otg->state == OTG_STATE_B_IDLE)
+ return;
+
+ isp->phy.otg->default_a = 0;
+@@ -375,7 +375,7 @@
+ isp->phy.otg->gadget->is_a_peripheral = 0;
+ gadget_suspend(isp);
+ }
+- isp->phy.state = OTG_STATE_B_IDLE;
++ isp->phy.otg->state = OTG_STATE_B_IDLE;
+ l = omap_readl(OTG_CTRL) & OTG_XCEIV_OUTPUTS;
+ omap_writel(l, OTG_CTRL);
+ isp->last_otg_ctrl = l;
+@@ -474,7 +474,7 @@
+ default:
+ break;
+ }
+- if (isp->phy.state == state && !extra)
++ if (isp->phy.otg->state == state && !extra)
+ return;
+ pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
+ usb_otg_state_string(state), fsm, state_name(isp),
+@@ -498,23 +498,23 @@
+
+ if (int_src & INTR_SESS_VLD)
+ otg_ctrl |= OTG_ASESSVLD;
+- else if (isp->phy.state == OTG_STATE_A_WAIT_VFALL) {
++ else if (isp->phy.otg->state == OTG_STATE_A_WAIT_VFALL) {
+ a_idle(isp, "vfall");
+ otg_ctrl &= ~OTG_CTRL_BITS;
+ }
+ if (int_src & INTR_VBUS_VLD)
+ otg_ctrl |= OTG_VBUSVLD;
+ if (int_src & INTR_ID_GND) { /* default-A */
+- if (isp->phy.state == OTG_STATE_B_IDLE
+- || isp->phy.state
++ if (isp->phy.otg->state == OTG_STATE_B_IDLE
++ || isp->phy.otg->state
+ == OTG_STATE_UNDEFINED) {
+ a_idle(isp, "init");
+ return;
+ }
+ } else { /* default-B */
+ otg_ctrl |= OTG_ID;
+- if (isp->phy.state == OTG_STATE_A_IDLE
+- || isp->phy.state == OTG_STATE_UNDEFINED) {
++ if (isp->phy.otg->state == OTG_STATE_A_IDLE
++ || isp->phy.otg->state == OTG_STATE_UNDEFINED) {
+ b_idle(isp, "init");
+ return;
+ }
+@@ -548,14 +548,14 @@
+ isp->last_otg_ctrl = otg_ctrl;
+ otg_ctrl = otg_ctrl & OTG_XCEIV_INPUTS;
+
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_B_IDLE:
+ case OTG_STATE_B_PERIPHERAL:
+ case OTG_STATE_B_SRP_INIT:
+ if (!(otg_ctrl & OTG_PULLUP)) {
+ // if (otg_ctrl & OTG_B_HNPEN) {
+ if (isp->phy.otg->gadget->b_hnp_enable) {
+- isp->phy.state = OTG_STATE_B_WAIT_ACON;
++ isp->phy.otg->state = OTG_STATE_B_WAIT_ACON;
+ pr_debug(" --> b_wait_acon\n");
+ }
+ goto pulldown;
+@@ -585,7 +585,7 @@
+ if (!(isp->phy.otg->host))
+ otg_ctrl &= ~OTG_DRV_VBUS;
+
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_A_SUSPEND:
+ if (otg_ctrl & OTG_DRV_VBUS) {
+ set |= OTG1_VBUS_DRV;
+@@ -596,7 +596,7 @@
+
+ /* FALLTHROUGH */
+ case OTG_STATE_A_VBUS_ERR:
+- isp->phy.state = OTG_STATE_A_WAIT_VFALL;
++ isp->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
+ pr_debug(" --> a_wait_vfall\n");
+ /* FALLTHROUGH */
+ case OTG_STATE_A_WAIT_VFALL:
+@@ -605,7 +605,7 @@
+ break;
+ case OTG_STATE_A_IDLE:
+ if (otg_ctrl & OTG_DRV_VBUS) {
+- isp->phy.state = OTG_STATE_A_WAIT_VRISE;
++ isp->phy.otg->state = OTG_STATE_A_WAIT_VRISE;
+ pr_debug(" --> a_wait_vrise\n");
+ }
+ /* FALLTHROUGH */
+@@ -625,17 +625,17 @@
+ if (otg_change & OTG_PULLUP) {
+ u32 l;
+
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_B_IDLE:
+ if (clr & OTG1_DP_PULLUP)
+ break;
+- isp->phy.state = OTG_STATE_B_PERIPHERAL;
++ isp->phy.otg->state = OTG_STATE_B_PERIPHERAL;
+ pr_debug(" --> b_peripheral\n");
+ break;
+ case OTG_STATE_A_SUSPEND:
+ if (clr & OTG1_DP_PULLUP)
+ break;
+- isp->phy.state = OTG_STATE_A_PERIPHERAL;
++ isp->phy.otg->state = OTG_STATE_A_PERIPHERAL;
+ pr_debug(" --> a_peripheral\n");
+ break;
+ default:
+@@ -673,7 +673,7 @@
+ * remote wakeup (SRP, normal) using their own timer
+ * to give "check cable and A-device" messages.
+ */
+- if (isp->phy.state == OTG_STATE_B_SRP_INIT)
++ if (isp->phy.otg->state == OTG_STATE_B_SRP_INIT)
+ b_idle(isp, "srp_timeout");
+
+ omap_writew(B_SRP_TMROUT, OTG_IRQ_SRC);
+@@ -691,7 +691,7 @@
+ omap_writel(otg_ctrl, OTG_CTRL);
+
+ /* subset of b_peripheral()... */
+- isp->phy.state = OTG_STATE_B_PERIPHERAL;
++ isp->phy.otg->state = OTG_STATE_B_PERIPHERAL;
+ pr_debug(" --> b_peripheral\n");
+
+ omap_writew(B_HNP_FAIL, OTG_IRQ_SRC);
+@@ -703,7 +703,7 @@
+ state_name(isp), omap_readl(OTG_CTRL));
+
+ isp1301_defer_work(isp, WORK_UPDATE_OTG);
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_A_IDLE:
+ if (!otg->host)
+ break;
+@@ -734,7 +734,7 @@
+ otg_ctrl |= OTG_BUSDROP;
+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
+ omap_writel(otg_ctrl, OTG_CTRL);
+- isp->phy.state = OTG_STATE_A_WAIT_VFALL;
++ isp->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
+
+ omap_writew(A_REQ_TMROUT, OTG_IRQ_SRC);
+ ret = IRQ_HANDLED;
+@@ -748,7 +748,7 @@
+ otg_ctrl |= OTG_BUSDROP;
+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK & ~OTG_XCEIV_INPUTS;
+ omap_writel(otg_ctrl, OTG_CTRL);
+- isp->phy.state = OTG_STATE_A_VBUS_ERR;
++ isp->phy.otg->state = OTG_STATE_A_VBUS_ERR;
+
+ omap_writew(A_VBUS_ERR, OTG_IRQ_SRC);
+ ret = IRQ_HANDLED;
+@@ -769,7 +769,7 @@
+
+ /* role is peripheral */
+ if (otg_ctrl & OTG_DRIVER_SEL) {
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_A_IDLE:
+ b_idle(isp, __func__);
+ break;
+@@ -786,18 +786,18 @@
+ }
+
+ if (otg->host) {
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_B_WAIT_ACON:
+- isp->phy.state = OTG_STATE_B_HOST;
++ isp->phy.otg->state = OTG_STATE_B_HOST;
+ pr_debug(" --> b_host\n");
+ kick = 1;
+ break;
+ case OTG_STATE_A_WAIT_BCON:
+- isp->phy.state = OTG_STATE_A_HOST;
++ isp->phy.otg->state = OTG_STATE_A_HOST;
+ pr_debug(" --> a_host\n");
+ break;
+ case OTG_STATE_A_PERIPHERAL:
+- isp->phy.state = OTG_STATE_A_WAIT_BCON;
++ isp->phy.otg->state = OTG_STATE_A_WAIT_BCON;
+ pr_debug(" --> a_wait_bcon\n");
+ break;
+ default:
+@@ -937,7 +937,7 @@
+ /* UDC driver just set OTG_BSESSVLD */
+ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLUP);
+ isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLDOWN);
+- isp->phy.state = OTG_STATE_B_PERIPHERAL;
++ isp->phy.otg->state = OTG_STATE_B_PERIPHERAL;
+ pr_debug(" --> b_peripheral\n");
+ dump_regs(isp, "2periph");
+ #endif
+@@ -947,7 +947,7 @@
+ {
+ struct usb_otg *otg = isp->phy.otg;
+ u8 isp_stat, isp_bstat;
+- enum usb_otg_state state = isp->phy.state;
++ enum usb_otg_state state = isp->phy.otg->state;
+
+ if (stat & INTR_BDIS_ACON)
+ pr_debug("OTG: BDIS_ACON, %s\n", state_name(isp));
+@@ -970,7 +970,7 @@
+ * when HNP is used.
+ */
+ if (isp_stat & INTR_VBUS_VLD)
+- isp->phy.state = OTG_STATE_A_HOST;
++ isp->phy.otg->state = OTG_STATE_A_HOST;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ if (!(isp_stat & INTR_SESS_VLD))
+@@ -978,7 +978,7 @@
+ break;
+ default:
+ if (!(isp_stat & INTR_VBUS_VLD))
+- isp->phy.state = OTG_STATE_A_VBUS_ERR;
++ isp->phy.otg->state = OTG_STATE_A_VBUS_ERR;
+ break;
+ }
+ isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
+@@ -1007,7 +1007,7 @@
+ if (otg->default_a) {
+ switch (state) {
+ default:
+- isp->phy.state = OTG_STATE_A_WAIT_VFALL;
++ isp->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ state = OTG_STATE_A_IDLE;
+@@ -1020,7 +1020,7 @@
+ host_suspend(isp);
+ isp1301_clear_bits(isp, ISP1301_MODE_CONTROL_1,
+ MC1_BDIS_ACON_EN);
+- isp->phy.state = OTG_STATE_B_IDLE;
++ isp->phy.otg->state = OTG_STATE_B_IDLE;
+ l = omap_readl(OTG_CTRL) & OTG_CTRL_MASK;
+ l &= ~OTG_CTRL_BITS;
+ omap_writel(l, OTG_CTRL);
+@@ -1031,7 +1031,7 @@
+ }
+ isp_bstat = isp1301_get_u8(isp, ISP1301_OTG_STATUS);
+
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_B_PERIPHERAL:
+ case OTG_STATE_B_WAIT_ACON:
+ case OTG_STATE_B_HOST:
+@@ -1071,7 +1071,7 @@
+ }
+ }
+
+- if (state != isp->phy.state)
++ if (state != isp->phy.otg->state)
+ pr_debug(" isp, %s -> %s\n",
+ usb_otg_state_string(state), state_name(isp));
+
+@@ -1129,10 +1129,10 @@
+ * skip A_WAIT_VRISE; hc transitions invisibly
+ * skip A_WAIT_BCON; same.
+ */
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_A_WAIT_BCON:
+ case OTG_STATE_A_WAIT_VRISE:
+- isp->phy.state = OTG_STATE_A_HOST;
++ isp->phy.otg->state = OTG_STATE_A_HOST;
+ pr_debug(" --> a_host\n");
+ otg_ctrl = omap_readl(OTG_CTRL);
+ otg_ctrl |= OTG_A_BUSREQ;
+@@ -1141,7 +1141,7 @@
+ omap_writel(otg_ctrl, OTG_CTRL);
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+- isp->phy.state = OTG_STATE_B_HOST;
++ isp->phy.otg->state = OTG_STATE_B_HOST;
+ pr_debug(" --> b_host (acon)\n");
+ break;
+ case OTG_STATE_B_HOST:
+@@ -1275,7 +1275,7 @@
+ static int
+ isp1301_set_host(struct usb_otg *otg, struct usb_bus *host)
+ {
+- struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
++ struct isp1301 *isp = container_of(otg->usb_phy, struct isp1301, phy);
+
+ if (isp != the_transceiver)
+ return -ENODEV;
+@@ -1331,7 +1331,7 @@
+ static int
+ isp1301_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget)
+ {
+- struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
++ struct isp1301 *isp = container_of(otg->usb_phy, struct isp1301, phy);
+
+ if (isp != the_transceiver)
+ return -ENODEV;
+@@ -1368,7 +1368,7 @@
+ }
+
+ power_up(isp);
+- isp->phy.state = OTG_STATE_B_IDLE;
++ isp->phy.otg->state = OTG_STATE_B_IDLE;
+
+ if (machine_is_omap_h2() || machine_is_omap_h3())
+ isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0);
+@@ -1403,7 +1403,7 @@
+ {
+ if (!the_transceiver)
+ return -ENODEV;
+- if (dev->state == OTG_STATE_B_PERIPHERAL)
++ if (dev->otg->state == OTG_STATE_B_PERIPHERAL)
+ enable_vbus_draw(the_transceiver, mA);
+ return 0;
+ }
+@@ -1411,10 +1411,10 @@
+ static int
+ isp1301_start_srp(struct usb_otg *otg)
+ {
+- struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
++ struct isp1301 *isp = container_of(otg->usb_phy, struct isp1301, phy);
+ u32 otg_ctrl;
+
+- if (isp != the_transceiver || isp->phy.state != OTG_STATE_B_IDLE)
++ if (isp != the_transceiver || isp->phy.otg->state != OTG_STATE_B_IDLE)
+ return -ENODEV;
+
+ otg_ctrl = omap_readl(OTG_CTRL);
+@@ -1424,7 +1424,7 @@
+ otg_ctrl |= OTG_B_BUSREQ;
+ otg_ctrl &= ~OTG_A_BUSREQ & OTG_CTRL_MASK;
+ omap_writel(otg_ctrl, OTG_CTRL);
+- isp->phy.state = OTG_STATE_B_SRP_INIT;
++ isp->phy.otg->state = OTG_STATE_B_SRP_INIT;
+
+ pr_debug("otg: SRP, %s ... %06x\n", state_name(isp),
+ omap_readl(OTG_CTRL));
+@@ -1438,7 +1438,7 @@
+ isp1301_start_hnp(struct usb_otg *otg)
+ {
+ #ifdef CONFIG_USB_OTG
+- struct isp1301 *isp = container_of(otg->phy, struct isp1301, phy);
++ struct isp1301 *isp = container_of(otg->usb_phy, struct isp1301, phy);
+ u32 l;
+
+ if (isp != the_transceiver)
+@@ -1452,9 +1452,9 @@
+ /* We want hardware to manage most HNP protocol timings.
+ * So do this part as early as possible...
+ */
+- switch (isp->phy.state) {
++ switch (isp->phy.otg->state) {
+ case OTG_STATE_B_HOST:
+- isp->phy.state = OTG_STATE_B_PERIPHERAL;
++ isp->phy.otg->state = OTG_STATE_B_PERIPHERAL;
+ /* caller will suspend next */
+ break;
+ case OTG_STATE_A_HOST:
+@@ -1583,7 +1583,7 @@
+ isp->phy.label = DRIVER_NAME;
+ isp->phy.set_power = isp1301_set_power,
+
+- isp->phy.otg->phy = &isp->phy;
++ isp->phy.otg->usb_phy = &isp->phy;
+ isp->phy.otg->set_host = isp1301_set_host,
+ isp->phy.otg->set_peripheral = isp1301_set_peripheral,
+ isp->phy.otg->start_srp = isp1301_start_srp,
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-msm-usb.c linux-3.14.72/drivers/usb/phy/phy-msm-usb.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-msm-usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-msm-usb.c 2016-06-19 22:11:55.341137644 +0200
+@@ -680,7 +680,7 @@
+
+ static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
+ {
+- struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
++ struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
+ struct usb_hcd *hcd;
+
+ /*
+@@ -688,16 +688,16 @@
+ * only peripheral configuration.
+ */
+ if (motg->pdata->mode == USB_PERIPHERAL) {
+- dev_info(otg->phy->dev, "Host mode is not supported\n");
++ dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
+ return -ENODEV;
+ }
+
+ if (!host) {
+- if (otg->phy->state == OTG_STATE_A_HOST) {
+- pm_runtime_get_sync(otg->phy->dev);
+- msm_otg_start_host(otg->phy, 0);
++ if (otg->state == OTG_STATE_A_HOST) {
++ pm_runtime_get_sync(otg->usb_phy->dev);
++ msm_otg_start_host(otg->usb_phy, 0);
+ otg->host = NULL;
+- otg->phy->state = OTG_STATE_UNDEFINED;
++ otg->state = OTG_STATE_UNDEFINED;
+ schedule_work(&motg->sm_work);
+ } else {
+ otg->host = NULL;
+@@ -710,14 +710,14 @@
+ hcd->power_budget = motg->pdata->power_budget;
+
+ otg->host = host;
+- dev_dbg(otg->phy->dev, "host driver registered w/ tranceiver\n");
++ dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
+
+ /*
+ * Kick the state machine work, if peripheral is not supported
+ * or peripheral is already registered with us.
+ */
+ if (motg->pdata->mode == USB_HOST || otg->gadget) {
+- pm_runtime_get_sync(otg->phy->dev);
++ pm_runtime_get_sync(otg->usb_phy->dev);
+ schedule_work(&motg->sm_work);
+ }
+
+@@ -754,23 +754,23 @@
+ static int msm_otg_set_peripheral(struct usb_otg *otg,
+ struct usb_gadget *gadget)
+ {
+- struct msm_otg *motg = container_of(otg->phy, struct msm_otg, phy);
++ struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
+
+ /*
+ * Fail peripheral registration if this board can support
+ * only host configuration.
+ */
+ if (motg->pdata->mode == USB_HOST) {
+- dev_info(otg->phy->dev, "Peripheral mode is not supported\n");
++ dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
+ return -ENODEV;
+ }
+
+ if (!gadget) {
+- if (otg->phy->state == OTG_STATE_B_PERIPHERAL) {
+- pm_runtime_get_sync(otg->phy->dev);
+- msm_otg_start_peripheral(otg->phy, 0);
++ if (otg->state == OTG_STATE_B_PERIPHERAL) {
++ pm_runtime_get_sync(otg->usb_phy->dev);
++ msm_otg_start_peripheral(otg->usb_phy, 0);
+ otg->gadget = NULL;
+- otg->phy->state = OTG_STATE_UNDEFINED;
++ otg->state = OTG_STATE_UNDEFINED;
+ schedule_work(&motg->sm_work);
+ } else {
+ otg->gadget = NULL;
+@@ -779,14 +779,15 @@
+ return 0;
+ }
+ otg->gadget = gadget;
+- dev_dbg(otg->phy->dev, "peripheral driver registered w/ tranceiver\n");
++ dev_dbg(otg->usb_phy->dev,
++ "peripheral driver registered w/ tranceiver\n");
+
+ /*
+ * Kick the state machine work, if host is not supported
+ * or host is already registered with us.
+ */
+ if (motg->pdata->mode == USB_PERIPHERAL || otg->host) {
+- pm_runtime_get_sync(otg->phy->dev);
++ pm_runtime_get_sync(otg->usb_phy->dev);
+ schedule_work(&motg->sm_work);
+ }
+
+@@ -1149,20 +1150,20 @@
+ struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
+ struct usb_otg *otg = motg->phy.otg;
+
+- switch (otg->phy->state) {
++ switch (otg->state) {
+ case OTG_STATE_UNDEFINED:
+- dev_dbg(otg->phy->dev, "OTG_STATE_UNDEFINED state\n");
+- msm_otg_reset(otg->phy);
++ dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
++ msm_otg_reset(otg->usb_phy);
+ msm_otg_init_sm(motg);
+- otg->phy->state = OTG_STATE_B_IDLE;
++ otg->state = OTG_STATE_B_IDLE;
+ /* FALL THROUGH */
+ case OTG_STATE_B_IDLE:
+- dev_dbg(otg->phy->dev, "OTG_STATE_B_IDLE state\n");
++ dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
+ if (!test_bit(ID, &motg->inputs) && otg->host) {
+ /* disable BSV bit */
+ writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
+- msm_otg_start_host(otg->phy, 1);
+- otg->phy->state = OTG_STATE_A_HOST;
++ msm_otg_start_host(otg->usb_phy, 1);
++ otg->state = OTG_STATE_A_HOST;
+ } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
+ switch (motg->chg_state) {
+ case USB_CHG_STATE_UNDEFINED:
+@@ -1177,14 +1178,16 @@
+ case USB_CDP_CHARGER:
+ msm_otg_notify_charger(motg,
+ IDEV_CHG_MAX);
+- msm_otg_start_peripheral(otg->phy, 1);
+- otg->phy->state
++ msm_otg_start_peripheral(otg->usb_phy,
++ 1);
++ otg->state
+ = OTG_STATE_B_PERIPHERAL;
+ break;
+ case USB_SDP_CHARGER:
+ msm_otg_notify_charger(motg, IUNIT);
+- msm_otg_start_peripheral(otg->phy, 1);
+- otg->phy->state
++ msm_otg_start_peripheral(otg->usb_phy,
++ 1);
++ otg->state
+ = OTG_STATE_B_PERIPHERAL;
+ break;
+ default:
+@@ -1201,34 +1204,34 @@
+ * is incremented in charger detection work.
+ */
+ if (cancel_delayed_work_sync(&motg->chg_work)) {
+- pm_runtime_put_sync(otg->phy->dev);
+- msm_otg_reset(otg->phy);
++ pm_runtime_put_sync(otg->usb_phy->dev);
++ msm_otg_reset(otg->usb_phy);
+ }
+ msm_otg_notify_charger(motg, 0);
+ motg->chg_state = USB_CHG_STATE_UNDEFINED;
+ motg->chg_type = USB_INVALID_CHARGER;
+ }
+- pm_runtime_put_sync(otg->phy->dev);
++ pm_runtime_put_sync(otg->usb_phy->dev);
+ break;
+ case OTG_STATE_B_PERIPHERAL:
+- dev_dbg(otg->phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
++ dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
+ if (!test_bit(B_SESS_VLD, &motg->inputs) ||
+ !test_bit(ID, &motg->inputs)) {
+ msm_otg_notify_charger(motg, 0);
+- msm_otg_start_peripheral(otg->phy, 0);
++ msm_otg_start_peripheral(otg->usb_phy, 0);
+ motg->chg_state = USB_CHG_STATE_UNDEFINED;
+ motg->chg_type = USB_INVALID_CHARGER;
+- otg->phy->state = OTG_STATE_B_IDLE;
+- msm_otg_reset(otg->phy);
++ otg->state = OTG_STATE_B_IDLE;
++ msm_otg_reset(otg->usb_phy);
+ schedule_work(w);
+ }
+ break;
+ case OTG_STATE_A_HOST:
+- dev_dbg(otg->phy->dev, "OTG_STATE_A_HOST state\n");
++ dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
+ if (test_bit(ID, &motg->inputs)) {
+- msm_otg_start_host(otg->phy, 0);
+- otg->phy->state = OTG_STATE_B_IDLE;
+- msm_otg_reset(otg->phy);
++ msm_otg_start_host(otg->usb_phy, 0);
++ otg->state = OTG_STATE_B_IDLE;
++ msm_otg_reset(otg->usb_phy);
+ schedule_work(w);
+ }
+ break;
+@@ -1280,7 +1283,7 @@
+ struct msm_otg *motg = s->private;
+ struct usb_otg *otg = motg->phy.otg;
+
+- switch (otg->phy->state) {
++ switch (otg->state) {
+ case OTG_STATE_A_HOST:
+ seq_printf(s, "host\n");
+ break;
+@@ -1330,7 +1333,7 @@
+
+ switch (req_mode) {
+ case USB_NONE:
+- switch (otg->phy->state) {
++ switch (otg->state) {
+ case OTG_STATE_A_HOST:
+ case OTG_STATE_B_PERIPHERAL:
+ set_bit(ID, &motg->inputs);
+@@ -1341,7 +1344,7 @@
+ }
+ break;
+ case USB_PERIPHERAL:
+- switch (otg->phy->state) {
++ switch (otg->state) {
+ case OTG_STATE_B_IDLE:
+ case OTG_STATE_A_HOST:
+ set_bit(ID, &motg->inputs);
+@@ -1352,7 +1355,7 @@
+ }
+ break;
+ case USB_HOST:
+- switch (otg->phy->state) {
++ switch (otg->state) {
+ case OTG_STATE_B_IDLE:
+ case OTG_STATE_B_PERIPHERAL:
+ clear_bit(ID, &motg->inputs);
+@@ -1365,7 +1368,7 @@
+ goto out;
+ }
+
+- pm_runtime_get_sync(otg->phy->dev);
++ pm_runtime_get_sync(otg->usb_phy->dev);
+ schedule_work(&motg->sm_work);
+ out:
+ return status;
+@@ -1546,7 +1549,7 @@
+
+ phy->io_ops = &msm_otg_io_ops;
+
+- phy->otg->phy = &motg->phy;
++ phy->otg->usb_phy = &motg->phy;
+ phy->otg->set_host = msm_otg_set_host;
+ phy->otg->set_peripheral = msm_otg_set_peripheral;
+
+@@ -1677,7 +1680,7 @@
+ * This 1 sec delay also prevents entering into LPM immediately
+ * after asynchronous interrupt.
+ */
+- if (otg->phy->state != OTG_STATE_UNDEFINED)
++ if (otg->state != OTG_STATE_UNDEFINED)
+ pm_schedule_suspend(dev, 1000);
+
+ return -EAGAIN;
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-mv-usb.c linux-3.14.72/drivers/usb/phy/phy-mv-usb.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-mv-usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-mv-usb.c 2016-06-19 22:11:55.345137382 +0200
+@@ -56,7 +56,7 @@
+
+ static int mv_otg_set_vbus(struct usb_otg *otg, bool on)
+ {
+- struct mv_otg *mvotg = container_of(otg->phy, struct mv_otg, phy);
++ struct mv_otg *mvotg = container_of(otg->usb_phy, struct mv_otg, phy);
+ if (mvotg->pdata->set_vbus == NULL)
+ return -ENODEV;
+
+@@ -339,68 +339,68 @@
+ {
+ struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
+ struct usb_phy *phy = &mvotg->phy;
+- int old_state = phy->state;
++ int old_state = mvotg->phy.otg->state;
+
+ switch (old_state) {
+ case OTG_STATE_UNDEFINED:
+- phy->state = OTG_STATE_B_IDLE;
++ mvotg->phy.otg->state = OTG_STATE_B_IDLE;
+ /* FALL THROUGH */
+ case OTG_STATE_B_IDLE:
+ if (otg_ctrl->id == 0)
+- phy->state = OTG_STATE_A_IDLE;
++ mvotg->phy.otg->state = OTG_STATE_A_IDLE;
+ else if (otg_ctrl->b_sess_vld)
+- phy->state = OTG_STATE_B_PERIPHERAL;
++ mvotg->phy.otg->state = OTG_STATE_B_PERIPHERAL;
+ break;
+ case OTG_STATE_B_PERIPHERAL:
+ if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
+- phy->state = OTG_STATE_B_IDLE;
++ mvotg->phy.otg->state = OTG_STATE_B_IDLE;
+ break;
+ case OTG_STATE_A_IDLE:
+ if (otg_ctrl->id)
+- phy->state = OTG_STATE_B_IDLE;
++ mvotg->phy.otg->state = OTG_STATE_B_IDLE;
+ else if (!(otg_ctrl->a_bus_drop) &&
+ (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
+- phy->state = OTG_STATE_A_WAIT_VRISE;
++ mvotg->phy.otg->state = OTG_STATE_A_WAIT_VRISE;
+ break;
+ case OTG_STATE_A_WAIT_VRISE:
+ if (otg_ctrl->a_vbus_vld)
+- phy->state = OTG_STATE_A_WAIT_BCON;
++ mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
+ break;
+ case OTG_STATE_A_WAIT_BCON:
+ if (otg_ctrl->id || otg_ctrl->a_bus_drop
+ || otg_ctrl->a_wait_bcon_timeout) {
+ mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
+ mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
+- phy->state = OTG_STATE_A_WAIT_VFALL;
++ mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
+ otg_ctrl->a_bus_req = 0;
+ } else if (!otg_ctrl->a_vbus_vld) {
+ mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
+ mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
+- phy->state = OTG_STATE_A_VBUS_ERR;
++ mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
+ } else if (otg_ctrl->b_conn) {
+ mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
+ mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
+- phy->state = OTG_STATE_A_HOST;
++ mvotg->phy.otg->state = OTG_STATE_A_HOST;
+ }
+ break;
+ case OTG_STATE_A_HOST:
+ if (otg_ctrl->id || !otg_ctrl->b_conn
+ || otg_ctrl->a_bus_drop)
+- phy->state = OTG_STATE_A_WAIT_BCON;
++ mvotg->phy.otg->state = OTG_STATE_A_WAIT_BCON;
+ else if (!otg_ctrl->a_vbus_vld)
+- phy->state = OTG_STATE_A_VBUS_ERR;
++ mvotg->phy.otg->state = OTG_STATE_A_VBUS_ERR;
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ if (otg_ctrl->id
+ || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
+ || otg_ctrl->a_bus_req)
+- phy->state = OTG_STATE_A_IDLE;
++ mvotg->phy.otg->state = OTG_STATE_A_IDLE;
+ break;
+ case OTG_STATE_A_VBUS_ERR:
+ if (otg_ctrl->id || otg_ctrl->a_clr_err
+ || otg_ctrl->a_bus_drop) {
+ otg_ctrl->a_clr_err = 0;
+- phy->state = OTG_STATE_A_WAIT_VFALL;
++ mvotg->phy.otg->state = OTG_STATE_A_WAIT_VFALL;
+ }
+ break;
+ default:
+@@ -420,8 +420,8 @@
+ run:
+ /* work queue is single thread, or we need spin_lock to protect */
+ phy = &mvotg->phy;
+- otg = phy->otg;
+- old_state = phy->state;
++ otg = mvotg->phy.otg;
++ old_state = otg->state;
+
+ if (!mvotg->active)
+ return;
+@@ -429,12 +429,12 @@
+ mv_otg_update_inputs(mvotg);
+ mv_otg_update_state(mvotg);
+
+- if (old_state != phy->state) {
++ if (old_state != mvotg->phy.otg->state) {
+ dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
+ state_string[old_state],
+- state_string[phy->state]);
++ state_string[mvotg->phy.otg->state]);
+
+- switch (phy->state) {
++ switch (mvotg->phy.otg->state) {
+ case OTG_STATE_B_IDLE:
+ otg->default_a = 0;
+ if (old_state == OTG_STATE_B_PERIPHERAL)
+@@ -545,8 +545,8 @@
+ return -1;
+
+ /* We will use this interface to change to A device */
+- if (mvotg->phy.state != OTG_STATE_B_IDLE
+- && mvotg->phy.state != OTG_STATE_A_IDLE)
++ if (mvotg->phy.otg->state != OTG_STATE_B_IDLE
++ && mvotg->phy.otg->state != OTG_STATE_A_IDLE)
+ return -1;
+
+ /* The clock may disabled and we need to set irq for ID detected */
+@@ -717,9 +717,9 @@
+ mvotg->phy.dev = &pdev->dev;
+ mvotg->phy.otg = otg;
+ mvotg->phy.label = driver_name;
+- mvotg->phy.state = OTG_STATE_UNDEFINED;
+
+- otg->phy = &mvotg->phy;
++ otg->state = OTG_STATE_UNDEFINED;
++ otg->usb_phy = &mvotg->phy;
+ otg->set_host = mv_otg_set_host;
+ otg->set_peripheral = mv_otg_set_peripheral;
+ otg->set_vbus = mv_otg_set_vbus;
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-mxs-usb.c linux-3.14.72/drivers/usb/phy/phy-mxs-usb.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-mxs-usb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-mxs-usb.c 2016-06-19 22:11:55.345137382 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ * on behalf of DENX Software Engineering GmbH
+ *
+@@ -20,6 +20,9 @@
+ #include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/io.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <linux/mfd/syscon.h>
+
+ #define DRIVER_NAME "mxs_phy"
+
+@@ -28,18 +31,154 @@
+ #define HW_USBPHY_CTRL_SET 0x34
+ #define HW_USBPHY_CTRL_CLR 0x38
+
++#define HW_USBPHY_DEBUG_SET 0x54
++#define HW_USBPHY_DEBUG_CLR 0x58
++
++#define HW_USBPHY_IP 0x90
++#define HW_USBPHY_IP_SET 0x94
++#define HW_USBPHY_IP_CLR 0x98
++
+ #define BM_USBPHY_CTRL_SFTRST BIT(31)
+ #define BM_USBPHY_CTRL_CLKGATE BIT(30)
++#define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
++#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
++#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
++#define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
++#define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
++#define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
++#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
++#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
++#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
+ #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
+ #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
+ #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
+
++#define BM_USBPHY_IP_FIX (BIT(17) | BIT(18))
++
++#define BM_USBPHY_DEBUG_CLKGATE BIT(30)
++
++/* Anatop Registers */
++#define ANADIG_ANA_MISC0 0x150
++#define ANADIG_ANA_MISC0_SET 0x154
++#define ANADIG_ANA_MISC0_CLR 0x158
++
++#define ANADIG_USB1_VBUS_DET_STAT 0x1c0
++#define ANADIG_USB2_VBUS_DET_STAT 0x220
++
++#define ANADIG_USB1_LOOPBACK_SET 0x1e4
++#define ANADIG_USB1_LOOPBACK_CLR 0x1e8
++#define ANADIG_USB2_LOOPBACK_SET 0x244
++#define ANADIG_USB2_LOOPBACK_CLR 0x248
++
++#define ANADIG_USB1_MISC 0x1f0
++#define ANADIG_USB2_MISC 0x250
++
++#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
++#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
++
++#define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
++#define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
++
++#define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2)
++#define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5)
++#define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
++#define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
++
++#define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29)
++#define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28)
++#define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29)
++#define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28)
++
++#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
++
++/* Do disconnection between PHY and controller without vbus */
++#define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0)
++
++/*
++ * The PHY will be in messy if there is a wakeup after putting
++ * bus to suspend (set portsc.suspendM) but before setting PHY to low
++ * power mode (set portsc.phcd).
++ */
++#define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1)
++
++/*
++ * The SOF sends too fast after resuming, it will cause disconnection
++ * between host and high speed device.
++ */
++#define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2)
++
++/*
++ * IC has bug fixes logic, they include
++ * MXS_PHY_ABNORMAL_IN_SUSPEND and MXS_PHY_SENDING_SOF_TOO_FAST
++ * which are described at above flags, the RTL will handle it
++ * according to different versions.
++ */
++#define MXS_PHY_NEED_IP_FIX BIT(3)
++
++struct mxs_phy_data {
++ unsigned int flags;
++};
++
++static const struct mxs_phy_data imx23_phy_data = {
++ .flags = MXS_PHY_ABNORMAL_IN_SUSPEND | MXS_PHY_SENDING_SOF_TOO_FAST,
++};
++
++static const struct mxs_phy_data imx6q_phy_data = {
++ .flags = MXS_PHY_SENDING_SOF_TOO_FAST |
++ MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
++ MXS_PHY_NEED_IP_FIX,
++};
++
++static const struct mxs_phy_data imx6sl_phy_data = {
++ .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
++ MXS_PHY_NEED_IP_FIX,
++};
++
++static const struct mxs_phy_data vf610_phy_data = {
++ .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS |
++ MXS_PHY_NEED_IP_FIX,
++};
++
++static const struct mxs_phy_data imx6sx_phy_data = {
++ .flags = MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS,
++};
++
++static const struct of_device_id mxs_phy_dt_ids[] = {
++ { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
++ { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
++ { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
++ { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
++ { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
++
+ struct mxs_phy {
+ struct usb_phy phy;
+ struct clk *clk;
++ const struct mxs_phy_data *data;
++ struct regmap *regmap_anatop;
++ int port_id;
+ };
+
+-#define to_mxs_phy(p) container_of((p), struct mxs_phy, phy)
++static inline bool is_imx6q_phy(struct mxs_phy *mxs_phy)
++{
++ return mxs_phy->data == &imx6q_phy_data;
++}
++
++static inline bool is_imx6sl_phy(struct mxs_phy *mxs_phy)
++{
++ return mxs_phy->data == &imx6sl_phy_data;
++}
++
++/*
++ * PHY needs some 32K cycles to switch from 32K clock to
++ * bus (such as AHB/AXI, etc) clock.
++ */
++static void mxs_phy_clock_switch_delay(void)
++{
++ usleep_range(300, 400);
++}
+
+ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
+ {
+@@ -53,19 +192,117 @@
+ /* Power up the PHY */
+ writel(0, base + HW_USBPHY_PWD);
+
+- /* enable FS/LS device */
+- writel(BM_USBPHY_CTRL_ENUTMILEVEL2 |
+- BM_USBPHY_CTRL_ENUTMILEVEL3,
++ /*
++ * USB PHY Ctrl Setting
++ * - Auto clock/power on
++ * - Enable full/low speed support
++ */
++ writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
++ BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
++ BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
++ BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
++ BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
++ BM_USBPHY_CTRL_ENUTMILEVEL2 |
++ BM_USBPHY_CTRL_ENUTMILEVEL3,
+ base + HW_USBPHY_CTRL_SET);
+
++ if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX)
++ writel(BM_USBPHY_IP_FIX, base + HW_USBPHY_IP_SET);
++
+ return 0;
+ }
+
++/* Return true if the vbus is there */
++static bool mxs_phy_get_vbus_status(struct mxs_phy *mxs_phy)
++{
++ unsigned int vbus_value;
++
++ if (mxs_phy->port_id == 0)
++ regmap_read(mxs_phy->regmap_anatop,
++ ANADIG_USB1_VBUS_DET_STAT,
++ &vbus_value);
++ else if (mxs_phy->port_id == 1)
++ regmap_read(mxs_phy->regmap_anatop,
++ ANADIG_USB2_VBUS_DET_STAT,
++ &vbus_value);
++
++ if (vbus_value & BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID)
++ return true;
++ else
++ return false;
++}
++
++static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect)
++{
++ void __iomem *base = mxs_phy->phy.io_priv;
++ u32 reg;
++
++ if (disconnect)
++ writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
++ base + HW_USBPHY_DEBUG_SET);
++
++ if (mxs_phy->port_id == 0) {
++ reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
++ : ANADIG_USB1_LOOPBACK_CLR;
++ regmap_write(mxs_phy->regmap_anatop, reg,
++ BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 |
++ BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN);
++ } else if (mxs_phy->port_id == 1) {
++ reg = disconnect ? ANADIG_USB2_LOOPBACK_SET
++ : ANADIG_USB2_LOOPBACK_CLR;
++ regmap_write(mxs_phy->regmap_anatop, reg,
++ BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 |
++ BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN);
++ }
++
++ if (!disconnect)
++ writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
++ base + HW_USBPHY_DEBUG_CLR);
++
++ /* Delay some time, and let Linestate be SE0 for controller */
++ if (disconnect)
++ usleep_range(500, 1000);
++}
++
++static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy)
++{
++ void __iomem *base = mxs_phy->phy.io_priv;
++ u32 phyctrl = readl(base + HW_USBPHY_CTRL);
++
++ if (IS_ENABLED(CONFIG_USB_OTG) &&
++ !(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE))
++ return true;
++
++ return false;
++}
++
++static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on)
++{
++ bool vbus_is_on = false;
++
++ /* If the SoCs don't need to disconnect line without vbus, quit */
++ if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS))
++ return;
++
++ /* If the SoCs don't have anatop, quit */
++ if (!mxs_phy->regmap_anatop)
++ return;
++
++ vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
++
++ if (on && !vbus_is_on && !mxs_phy_is_otg_host(mxs_phy))
++ __mxs_phy_disconnect_line(mxs_phy, true);
++ else
++ __mxs_phy_disconnect_line(mxs_phy, false);
++
++}
++
+ static int mxs_phy_init(struct usb_phy *phy)
+ {
+ int ret;
+ struct mxs_phy *mxs_phy = to_mxs_phy(phy);
+
++ mxs_phy_clock_switch_delay();
+ ret = clk_prepare_enable(mxs_phy->clk);
+ if (ret)
+ return ret;
+@@ -76,6 +313,17 @@
+ static void mxs_phy_shutdown(struct usb_phy *phy)
+ {
+ struct mxs_phy *mxs_phy = to_mxs_phy(phy);
++ u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
++ BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
++ BM_USBPHY_CTRL_ENIDCHG_WKUP |
++ BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
++ BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
++ BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
++ BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
++ BM_USBPHY_CTRL_ENAUTO_PWRON_PLL;
++
++ writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR);
++ writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
+
+ writel(BM_USBPHY_CTRL_CLKGATE,
+ phy->io_priv + HW_USBPHY_CTRL_SET);
+@@ -83,17 +331,61 @@
+ clk_disable_unprepare(mxs_phy->clk);
+ }
+
++static bool mxs_phy_is_low_speed_connection(struct mxs_phy *mxs_phy)
++{
++ unsigned int line_state;
++ /* bit definition is the same for all controllers */
++ unsigned int dp_bit = BM_ANADIG_USB1_MISC_RX_VPIN_FS,
++ dm_bit = BM_ANADIG_USB1_MISC_RX_VMIN_FS;
++ unsigned int reg = ANADIG_USB1_MISC;
++
++ /* If the SoCs don't have anatop, quit */
++ if (!mxs_phy->regmap_anatop)
++ return false;
++
++ if (mxs_phy->port_id == 0)
++ reg = ANADIG_USB1_MISC;
++ else if (mxs_phy->port_id == 1)
++ reg = ANADIG_USB2_MISC;
++
++ regmap_read(mxs_phy->regmap_anatop, reg, &line_state);
++
++ if ((line_state & (dp_bit | dm_bit)) == dm_bit)
++ return true;
++ else
++ return false;
++}
++
+ static int mxs_phy_suspend(struct usb_phy *x, int suspend)
+ {
+ int ret;
+ struct mxs_phy *mxs_phy = to_mxs_phy(x);
++ bool low_speed_connection, vbus_is_on;
++
++ low_speed_connection = mxs_phy_is_low_speed_connection(mxs_phy);
++ vbus_is_on = mxs_phy_get_vbus_status(mxs_phy);
+
+ if (suspend) {
+- writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
++ /*
++ * FIXME: Do not power down RXPWD1PT1 bit for low speed
++ * connect. The low speed connection will have problem at
++ * very rare cases during usb suspend and resume process.
++ */
++ if (low_speed_connection & vbus_is_on) {
++ /*
++ * If value to be set as pwd value is not 0xffffffff,
++ * several 32Khz cycles are needed.
++ */
++ mxs_phy_clock_switch_delay();
++ writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
++ } else {
++ writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
++ }
+ writel(BM_USBPHY_CTRL_CLKGATE,
+ x->io_priv + HW_USBPHY_CTRL_SET);
+ clk_disable_unprepare(mxs_phy->clk);
+ } else {
++ mxs_phy_clock_switch_delay();
+ ret = clk_prepare_enable(mxs_phy->clk);
+ if (ret)
+ return ret;
+@@ -105,11 +397,28 @@
+ return 0;
+ }
+
++static int mxs_phy_set_wakeup(struct usb_phy *x, bool enabled)
++{
++ struct mxs_phy *mxs_phy = to_mxs_phy(x);
++ u32 value = BM_USBPHY_CTRL_ENVBUSCHG_WKUP |
++ BM_USBPHY_CTRL_ENDPDMCHG_WKUP |
++ BM_USBPHY_CTRL_ENIDCHG_WKUP;
++ if (enabled) {
++ mxs_phy_disconnect_line(mxs_phy, true);
++ writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET);
++ } else {
++ writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR);
++ mxs_phy_disconnect_line(mxs_phy, false);
++ }
++
++ return 0;
++}
++
+ static int mxs_phy_on_connect(struct usb_phy *phy,
+ enum usb_device_speed speed)
+ {
+- dev_dbg(phy->dev, "%s speed device has connected\n",
+- (speed == USB_SPEED_HIGH) ? "high" : "non-high");
++ dev_dbg(phy->dev, "%s device has connected\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
+
+ if (speed == USB_SPEED_HIGH)
+ writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+@@ -121,16 +430,60 @@
+ static int mxs_phy_on_disconnect(struct usb_phy *phy,
+ enum usb_device_speed speed)
+ {
+- dev_dbg(phy->dev, "%s speed device has disconnected\n",
+- (speed == USB_SPEED_HIGH) ? "high" : "non-high");
++ dev_dbg(phy->dev, "%s device has disconnected\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
+
+- if (speed == USB_SPEED_HIGH)
++ /* Sometimes, the speed is not high speed when the error occurs */
++ if (readl(phy->io_priv + HW_USBPHY_CTRL) &
++ BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
+ writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
+ phy->io_priv + HW_USBPHY_CTRL_CLR);
+
+ return 0;
+ }
+
++static int mxs_phy_on_suspend(struct usb_phy *phy,
++ enum usb_device_speed speed)
++{
++ struct mxs_phy *mxs_phy = to_mxs_phy(phy);
++
++ dev_dbg(phy->dev, "%s device has suspended\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
++
++ /* delay 4ms to wait bus entering idle */
++ usleep_range(4000, 5000);
++
++ if (mxs_phy->data->flags & MXS_PHY_ABNORMAL_IN_SUSPEND) {
++ writel_relaxed(0xffffffff, phy->io_priv + HW_USBPHY_PWD);
++ writel_relaxed(0, phy->io_priv + HW_USBPHY_PWD);
++ }
++
++ if (speed == USB_SPEED_HIGH)
++ writel_relaxed(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
++ phy->io_priv + HW_USBPHY_CTRL_CLR);
++
++ return 0;
++}
++
++/*
++ * The resume signal must be finished here.
++ */
++static int mxs_phy_on_resume(struct usb_phy *phy,
++ enum usb_device_speed speed)
++{
++ dev_dbg(phy->dev, "%s device has resumed\n",
++ (speed == USB_SPEED_HIGH) ? "HS" : "FS/LS");
++
++ if (speed == USB_SPEED_HIGH) {
++ /* Make sure the device has switched to High-Speed mode */
++ udelay(500);
++ writel_relaxed(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
++ phy->io_priv + HW_USBPHY_CTRL_SET);
++ }
++
++ return 0;
++}
++
+ static int mxs_phy_probe(struct platform_device *pdev)
+ {
+ struct resource *res;
+@@ -138,6 +491,9 @@
+ struct clk *clk;
+ struct mxs_phy *mxs_phy;
+ int ret;
++ const struct of_device_id *of_id =
++ of_match_device(mxs_phy_dt_ids, &pdev->dev);
++ struct device_node *np = pdev->dev.of_node;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+@@ -157,6 +513,24 @@
+ return -ENOMEM;
+ }
+
++ /* Some SoCs don't have anatop registers */
++ if (of_get_property(np, "fsl,anatop", NULL)) {
++ mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle
++ (np, "fsl,anatop");
++ if (IS_ERR(mxs_phy->regmap_anatop)) {
++ dev_dbg(&pdev->dev,
++ "failed to find regmap for anatop\n");
++ return PTR_ERR(mxs_phy->regmap_anatop);
++ }
++ }
++
++ ret = of_alias_get_id(np, "usbphy");
++ if (ret < 0)
++ dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret);
++ mxs_phy->port_id = ret;
++ mxs_phy->clk = clk;
++ mxs_phy->data = of_id->data;
++
+ mxs_phy->phy.io_priv = base;
+ mxs_phy->phy.dev = &pdev->dev;
+ mxs_phy->phy.label = DRIVER_NAME;
+@@ -166,11 +540,16 @@
+ mxs_phy->phy.notify_connect = mxs_phy_on_connect;
+ mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect;
+ mxs_phy->phy.type = USB_PHY_TYPE_USB2;
+-
+- mxs_phy->clk = clk;
++ mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup;
++ if (mxs_phy->data->flags & MXS_PHY_SENDING_SOF_TOO_FAST) {
++ mxs_phy->phy.notify_suspend = mxs_phy_on_suspend;
++ mxs_phy->phy.notify_resume = mxs_phy_on_resume;
++ }
+
+ platform_set_drvdata(pdev, mxs_phy);
+
++ device_set_wakeup_capable(&pdev->dev, true);
++
+ ret = usb_add_phy_dev(&mxs_phy->phy);
+ if (ret)
+ return ret;
+@@ -187,11 +566,46 @@
+ return 0;
+ }
+
+-static const struct of_device_id mxs_phy_dt_ids[] = {
+- { .compatible = "fsl,imx23-usbphy", },
+- { /* sentinel */ }
+-};
+-MODULE_DEVICE_TABLE(of, mxs_phy_dt_ids);
++#ifdef CONFIG_PM_SLEEP
++static void mxs_phy_enable_ldo_in_suspend(struct mxs_phy *mxs_phy, bool on)
++{
++ unsigned int reg = on ? ANADIG_ANA_MISC0_SET : ANADIG_ANA_MISC0_CLR;
++
++ /* If the SoCs don't have anatop, quit */
++ if (!mxs_phy->regmap_anatop)
++ return;
++
++ if (is_imx6q_phy(mxs_phy))
++ regmap_write(mxs_phy->regmap_anatop, reg,
++ BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG);
++ else if (is_imx6sl_phy(mxs_phy))
++ regmap_write(mxs_phy->regmap_anatop,
++ reg, BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL);
++}
++
++static int mxs_phy_system_suspend(struct device *dev)
++{
++ struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
++
++ if (device_may_wakeup(dev))
++ mxs_phy_enable_ldo_in_suspend(mxs_phy, true);
++
++ return 0;
++}
++
++static int mxs_phy_system_resume(struct device *dev)
++{
++ struct mxs_phy *mxs_phy = dev_get_drvdata(dev);
++
++ if (device_may_wakeup(dev))
++ mxs_phy_enable_ldo_in_suspend(mxs_phy, false);
++
++ return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static SIMPLE_DEV_PM_OPS(mxs_phy_pm, mxs_phy_system_suspend,
++ mxs_phy_system_resume);
+
+ static struct platform_driver mxs_phy_driver = {
+ .probe = mxs_phy_probe,
+@@ -200,6 +614,7 @@
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = mxs_phy_dt_ids,
++ .pm = &mxs_phy_pm,
+ },
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-tahvo.c linux-3.14.72/drivers/usb/phy/phy-tahvo.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-tahvo.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-tahvo.c 2016-06-19 22:11:55.345137382 +0200
+@@ -81,33 +81,33 @@
+
+ reg = retu_read(rdev, TAHVO_REG_IDSR);
+ if (reg & TAHVO_STAT_VBUS) {
+- switch (tu->phy.state) {
++ switch (tu->phy.otg->state) {
+ case OTG_STATE_B_IDLE:
+ /* Enable the gadget driver */
+ if (tu->phy.otg->gadget)
+ usb_gadget_vbus_connect(tu->phy.otg->gadget);
+- tu->phy.state = OTG_STATE_B_PERIPHERAL;
++ tu->phy.otg->state = OTG_STATE_B_PERIPHERAL;
+ break;
+ case OTG_STATE_A_IDLE:
+ /*
+ * Session is now valid assuming the USB hub is driving
+ * Vbus.
+ */
+- tu->phy.state = OTG_STATE_A_HOST;
++ tu->phy.otg->state = OTG_STATE_A_HOST;
+ break;
+ default:
+ break;
+ }
+ dev_info(&tu->pt_dev->dev, "USB cable connected\n");
+ } else {
+- switch (tu->phy.state) {
++ switch (tu->phy.otg->state) {
+ case OTG_STATE_B_PERIPHERAL:
+ if (tu->phy.otg->gadget)
+ usb_gadget_vbus_disconnect(tu->phy.otg->gadget);
+- tu->phy.state = OTG_STATE_B_IDLE;
++ tu->phy.otg->state = OTG_STATE_B_IDLE;
+ break;
+ case OTG_STATE_A_HOST:
+- tu->phy.state = OTG_STATE_A_IDLE;
++ tu->phy.otg->state = OTG_STATE_A_IDLE;
+ break;
+ default:
+ break;
+@@ -132,14 +132,14 @@
+ /* Power up the transceiver in USB host mode */
+ retu_write(rdev, TAHVO_REG_USBR, USBR_REGOUT | USBR_NSUSPEND |
+ USBR_MASTER_SW2 | USBR_MASTER_SW1);
+- tu->phy.state = OTG_STATE_A_IDLE;
++ tu->phy.otg->state = OTG_STATE_A_IDLE;
+
+ check_vbus_state(tu);
+ }
+
+ static void tahvo_usb_stop_host(struct tahvo_usb *tu)
+ {
+- tu->phy.state = OTG_STATE_A_IDLE;
++ tu->phy.otg->state = OTG_STATE_A_IDLE;
+ }
+
+ static void tahvo_usb_become_peripheral(struct tahvo_usb *tu)
+@@ -151,7 +151,7 @@
+ /* Power up transceiver and set it in USB peripheral mode */
+ retu_write(rdev, TAHVO_REG_USBR, USBR_SLAVE_CONTROL | USBR_REGOUT |
+ USBR_NSUSPEND | USBR_SLAVE_SW);
+- tu->phy.state = OTG_STATE_B_IDLE;
++ tu->phy.otg->state = OTG_STATE_B_IDLE;
+
+ check_vbus_state(tu);
+ }
+@@ -160,7 +160,7 @@
+ {
+ if (tu->phy.otg->gadget)
+ usb_gadget_vbus_disconnect(tu->phy.otg->gadget);
+- tu->phy.state = OTG_STATE_B_IDLE;
++ tu->phy.otg->state = OTG_STATE_B_IDLE;
+ }
+
+ static void tahvo_usb_power_off(struct tahvo_usb *tu)
+@@ -173,7 +173,7 @@
+
+ /* Power off transceiver */
+ retu_write(rdev, TAHVO_REG_USBR, 0);
+- tu->phy.state = OTG_STATE_UNDEFINED;
++ tu->phy.otg->state = OTG_STATE_UNDEFINED;
+ }
+
+ static int tahvo_usb_set_suspend(struct usb_phy *dev, int suspend)
+@@ -196,7 +196,8 @@
+
+ static int tahvo_usb_set_host(struct usb_otg *otg, struct usb_bus *host)
+ {
+- struct tahvo_usb *tu = container_of(otg->phy, struct tahvo_usb, phy);
++ struct tahvo_usb *tu = container_of(otg->usb_phy, struct tahvo_usb,
++ phy);
+
+ dev_dbg(&tu->pt_dev->dev, "%s %p\n", __func__, host);
+
+@@ -225,7 +226,8 @@
+ static int tahvo_usb_set_peripheral(struct usb_otg *otg,
+ struct usb_gadget *gadget)
+ {
+- struct tahvo_usb *tu = container_of(otg->phy, struct tahvo_usb, phy);
++ struct tahvo_usb *tu = container_of(otg->usb_phy, struct tahvo_usb,
++ phy);
+
+ dev_dbg(&tu->pt_dev->dev, "%s %p\n", __func__, gadget);
+
+@@ -379,11 +381,11 @@
+ /* Create OTG interface */
+ tahvo_usb_power_off(tu);
+ tu->phy.dev = &pdev->dev;
+- tu->phy.state = OTG_STATE_UNDEFINED;
++ tu->phy.otg->state = OTG_STATE_UNDEFINED;
+ tu->phy.label = DRIVER_NAME;
+ tu->phy.set_suspend = tahvo_usb_set_suspend;
+
+- tu->phy.otg->phy = &tu->phy;
++ tu->phy.otg->usb_phy = &tu->phy;
+ tu->phy.otg->set_host = tahvo_usb_set_host;
+ tu->phy.otg->set_peripheral = tahvo_usb_set_peripheral;
+
+diff -Nur linux-3.14.72.orig/drivers/usb/phy/phy-ulpi.c linux-3.14.72/drivers/usb/phy/phy-ulpi.c
+--- linux-3.14.72.orig/drivers/usb/phy/phy-ulpi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/phy/phy-ulpi.c 2016-06-19 22:11:55.345137382 +0200
+@@ -210,7 +210,7 @@
+
+ static int ulpi_set_host(struct usb_otg *otg, struct usb_bus *host)
+ {
+- struct usb_phy *phy = otg->phy;
++ struct usb_phy *phy = otg->usb_phy;
+ unsigned int flags = usb_phy_io_read(phy, ULPI_IFC_CTRL);
+
+ if (!host) {
+@@ -236,7 +236,7 @@
+
+ static int ulpi_set_vbus(struct usb_otg *otg, bool on)
+ {
+- struct usb_phy *phy = otg->phy;
++ struct usb_phy *phy = otg->usb_phy;
+ unsigned int flags = usb_phy_io_read(phy, ULPI_OTG_CTRL);
+
+ flags &= ~(ULPI_OTG_CTRL_DRVVBUS | ULPI_OTG_CTRL_DRVVBUS_EXT);
+@@ -275,7 +275,7 @@
+ phy->otg = otg;
+ phy->init = ulpi_init;
+
+- otg->phy = phy;
++ otg->usb_phy = phy;
+ otg->set_host = ulpi_set_host;
+ otg->set_vbus = ulpi_set_vbus;
+
+diff -Nur linux-3.14.72.orig/drivers/usb/usb-common.c linux-3.14.72/drivers/usb/usb-common.c
+--- linux-3.14.72.orig/drivers/usb/usb-common.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/usb/usb-common.c 1970-01-01 01:00:00.000000000 +0100
+@@ -1,144 +0,0 @@
+-/*
+- * Provides code common for host and device side USB.
+- *
+- * This program is free software; you can redistribute it and/or
+- * modify it under the terms of the GNU General Public License as
+- * published by the Free Software Foundation, version 2.
+- *
+- * If either host side (ie. CONFIG_USB=y) or device side USB stack
+- * (ie. CONFIG_USB_GADGET=y) is compiled in the kernel, this module is
+- * compiled-in as well. Otherwise, if either of the two stacks is
+- * compiled as module, this file is compiled as module as well.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/of.h>
+-#include <linux/usb/ch9.h>
+-#include <linux/usb/of.h>
+-#include <linux/usb/otg.h>
+-
+-const char *usb_otg_state_string(enum usb_otg_state state)
+-{
+- static const char *const names[] = {
+- [OTG_STATE_A_IDLE] = "a_idle",
+- [OTG_STATE_A_WAIT_VRISE] = "a_wait_vrise",
+- [OTG_STATE_A_WAIT_BCON] = "a_wait_bcon",
+- [OTG_STATE_A_HOST] = "a_host",
+- [OTG_STATE_A_SUSPEND] = "a_suspend",
+- [OTG_STATE_A_PERIPHERAL] = "a_peripheral",
+- [OTG_STATE_A_WAIT_VFALL] = "a_wait_vfall",
+- [OTG_STATE_A_VBUS_ERR] = "a_vbus_err",
+- [OTG_STATE_B_IDLE] = "b_idle",
+- [OTG_STATE_B_SRP_INIT] = "b_srp_init",
+- [OTG_STATE_B_PERIPHERAL] = "b_peripheral",
+- [OTG_STATE_B_WAIT_ACON] = "b_wait_acon",
+- [OTG_STATE_B_HOST] = "b_host",
+- };
+-
+- if (state < 0 || state >= ARRAY_SIZE(names))
+- return "UNDEFINED";
+-
+- return names[state];
+-}
+-EXPORT_SYMBOL_GPL(usb_otg_state_string);
+-
+-static const char *const speed_names[] = {
+- [USB_SPEED_UNKNOWN] = "UNKNOWN",
+- [USB_SPEED_LOW] = "low-speed",
+- [USB_SPEED_FULL] = "full-speed",
+- [USB_SPEED_HIGH] = "high-speed",
+- [USB_SPEED_WIRELESS] = "wireless",
+- [USB_SPEED_SUPER] = "super-speed",
+-};
+-
+-const char *usb_speed_string(enum usb_device_speed speed)
+-{
+- if (speed < 0 || speed >= ARRAY_SIZE(speed_names))
+- speed = USB_SPEED_UNKNOWN;
+- return speed_names[speed];
+-}
+-EXPORT_SYMBOL_GPL(usb_speed_string);
+-
+-const char *usb_state_string(enum usb_device_state state)
+-{
+- static const char *const names[] = {
+- [USB_STATE_NOTATTACHED] = "not attached",
+- [USB_STATE_ATTACHED] = "attached",
+- [USB_STATE_POWERED] = "powered",
+- [USB_STATE_RECONNECTING] = "reconnecting",
+- [USB_STATE_UNAUTHENTICATED] = "unauthenticated",
+- [USB_STATE_DEFAULT] = "default",
+- [USB_STATE_ADDRESS] = "addresssed",
+- [USB_STATE_CONFIGURED] = "configured",
+- [USB_STATE_SUSPENDED] = "suspended",
+- };
+-
+- if (state < 0 || state >= ARRAY_SIZE(names))
+- return "UNKNOWN";
+-
+- return names[state];
+-}
+-EXPORT_SYMBOL_GPL(usb_state_string);
+-
+-#ifdef CONFIG_OF
+-static const char *const usb_dr_modes[] = {
+- [USB_DR_MODE_UNKNOWN] = "",
+- [USB_DR_MODE_HOST] = "host",
+- [USB_DR_MODE_PERIPHERAL] = "peripheral",
+- [USB_DR_MODE_OTG] = "otg",
+-};
+-
+-/**
+- * of_usb_get_dr_mode - Get dual role mode for given device_node
+- * @np: Pointer to the given device_node
+- *
+- * The function gets phy interface string from property 'dr_mode',
+- * and returns the correspondig enum usb_dr_mode
+- */
+-enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
+-{
+- const char *dr_mode;
+- int err, i;
+-
+- err = of_property_read_string(np, "dr_mode", &dr_mode);
+- if (err < 0)
+- return USB_DR_MODE_UNKNOWN;
+-
+- for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
+- if (!strcmp(dr_mode, usb_dr_modes[i]))
+- return i;
+-
+- return USB_DR_MODE_UNKNOWN;
+-}
+-EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
+-
+-/**
+- * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
+- * controller.
+- * @np: Pointer to the given device_node
+- *
+- * The function gets the maximum speed string from property "maximum-speed",
+- * and returns the corresponding enum usb_device_speed.
+- */
+-enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
+-{
+- const char *maximum_speed;
+- int err;
+- int i;
+-
+- err = of_property_read_string(np, "maximum-speed", &maximum_speed);
+- if (err < 0)
+- return USB_SPEED_UNKNOWN;
+-
+- for (i = 0; i < ARRAY_SIZE(speed_names); i++)
+- if (strcmp(maximum_speed, speed_names[i]) == 0)
+- return i;
+-
+- return USB_SPEED_UNKNOWN;
+-}
+-EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
+-
+-#endif
+-
+-MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/video/backlight/backlight.c linux-3.14.72/drivers/video/backlight/backlight.c
+--- linux-3.14.72.orig/drivers/video/backlight/backlight.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/video/backlight/backlight.c 2016-06-19 22:11:55.345137382 +0200
+@@ -41,6 +41,8 @@
+ {
+ struct backlight_device *bd;
+ struct fb_event *evdata = data;
++ int node = evdata->info->node;
++ int fb_blank = 0;
+
+ /* If we aren't interested in this event, skip it immediately ... */
+ if (event != FB_EVENT_BLANK && event != FB_EVENT_CONBLANK)
+@@ -51,12 +53,24 @@
+ if (bd->ops)
+ if (!bd->ops->check_fb ||
+ bd->ops->check_fb(bd, evdata->info)) {
+- bd->props.fb_blank = *(int *)evdata->data;
+- if (bd->props.fb_blank == FB_BLANK_UNBLANK)
+- bd->props.state &= ~BL_CORE_FBBLANK;
+- else
+- bd->props.state |= BL_CORE_FBBLANK;
+- backlight_update_status(bd);
++ fb_blank = *(int *)evdata->data;
++ if (fb_blank == FB_BLANK_UNBLANK &&
++ !bd->fb_bl_on[node]) {
++ bd->fb_bl_on[node] = true;
++ if (!bd->use_count++) {
++ bd->props.state &= ~BL_CORE_FBBLANK;
++ bd->props.fb_blank = FB_BLANK_UNBLANK;
++ backlight_update_status(bd);
++ }
++ } else if (fb_blank != FB_BLANK_UNBLANK &&
++ bd->fb_bl_on[node]) {
++ bd->fb_bl_on[node] = false;
++ if (!(--bd->use_count)) {
++ bd->props.state |= BL_CORE_FBBLANK;
++ bd->props.fb_blank = FB_BLANK_POWERDOWN;
++ backlight_update_status(bd);
++ }
++ }
+ }
+ mutex_unlock(&bd->ops_lock);
+ return 0;
+diff -Nur linux-3.14.72.orig/drivers/video/console/fbcon.c linux-3.14.72/drivers/video/console/fbcon.c
+--- linux-3.14.72.orig/drivers/video/console/fbcon.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/video/console/fbcon.c 2016-06-19 22:11:55.345137382 +0200
+@@ -3180,6 +3180,8 @@
+ if (!fb_display[i].mode)
+ continue;
+ vc = vc_cons[i].d;
++ if (!vc)
++ continue;
+ display_to_var(&var, &fb_display[i]);
+ mode = fb_find_nearest_mode(fb_display[i].mode,
+ &info->modelist);
+diff -Nur linux-3.14.72.orig/drivers/video/fbmem.c linux-3.14.72/drivers/video/fbmem.c
+--- linux-3.14.72.orig/drivers/video/fbmem.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/video/fbmem.c 2016-06-19 22:11:55.345137382 +0200
+@@ -1032,12 +1032,13 @@
+ !list_empty(&info->modelist))
+ ret = fb_add_videomode(&mode, &info->modelist);
+
+- if (!ret && (flags & FBINFO_MISC_USEREVENT)) {
++ if (!(ret < 0) && (flags & FBINFO_MISC_USEREVENT)) {
+ struct fb_event event;
+ int evnt = (activate & FB_ACTIVATE_ALL) ?
+ FB_EVENT_MODE_CHANGE_ALL :
+ FB_EVENT_MODE_CHANGE;
+
++ ret = 0;
+ info->flags &= ~FBINFO_MISC_USEREVENT;
+ event.info = info;
+ event.data = &mode;
+diff -Nur linux-3.14.72.orig/drivers/video/Kconfig linux-3.14.72/drivers/video/Kconfig
+--- linux-3.14.72.orig/drivers/video/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/video/Kconfig 2016-06-19 22:11:55.345137382 +0200
+@@ -21,6 +21,8 @@
+
+ source "drivers/gpu/host1x/Kconfig"
+
++source "drivers/gpu/galcore/Kconfig"
++
+ source "drivers/gpu/drm/Kconfig"
+
+ config VGASTATE
+@@ -2276,6 +2278,11 @@
+
+ If unsure, say N.
+
++config FB_VIRTUAL_PHYMEM
++ tristate "Virtual Frame Buffer with contiguous physical memory regions support"
++ depends on FB
++ default n
++
+ config XEN_FBDEV_FRONTEND
+ tristate "Xen virtual frame buffer support"
+ depends on FB && XEN
+@@ -2440,7 +2447,7 @@
+
+ config FB_MXS
+ tristate "MXS LCD framebuffer support"
+- depends on FB && ARCH_MXS
++ depends on FB && (ARCH_MXS || ARCH_MXC)
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+@@ -2491,6 +2498,10 @@
+ source "drivers/video/mmp/Kconfig"
+ source "drivers/video/backlight/Kconfig"
+
++if ARCH_MXC
++source "drivers/video/mxc/Kconfig"
++endif
++
+ if VT
+ source "drivers/video/console/Kconfig"
+ endif
+diff -Nur linux-3.14.72.orig/drivers/video/Makefile linux-3.14.72/drivers/video/Makefile
+--- linux-3.14.72.orig/drivers/video/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/video/Makefile 2016-06-19 22:11:55.345137382 +0200
+@@ -53,6 +53,7 @@
+ obj-$(CONFIG_FB_SAVAGE) += savage/
+ obj-$(CONFIG_FB_GEODE) += geode/
+ obj-$(CONFIG_FB_MBX) += mbx/
++obj-$(CONFIG_FB_MXC) += mxc/
+ obj-$(CONFIG_FB_NEOMAGIC) += neofb.o
+ obj-$(CONFIG_FB_3DFX) += tdfxfb.o
+ obj-$(CONFIG_FB_CONTROL) += controlfb.o
+@@ -171,6 +172,7 @@
+
+ # the test framebuffer is last
+ obj-$(CONFIG_FB_VIRTUAL) += vfb.o
++obj-$(CONFIG_FB_VIRTUAL_PHYMEM) += vfb_phymem.o
+
+ #video output switch sysfs driver
+ obj-$(CONFIG_VIDEO_OUTPUT_CONTROL) += output.o
+diff -Nur linux-3.14.72.orig/drivers/video/modedb.c linux-3.14.72/drivers/video/modedb.c
+--- linux-3.14.72.orig/drivers/video/modedb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/video/modedb.c 2016-06-19 22:11:55.345137382 +0200
+@@ -1003,7 +1003,7 @@
+ modelist->mode = *mode;
+ list_add(&modelist->list, head);
+ }
+- return 0;
++ return found;
+ }
+
+ /**
+@@ -1060,7 +1060,7 @@
+ INIT_LIST_HEAD(head);
+
+ for (i = 0; i < num; i++) {
+- if (fb_add_videomode(&modedb[i], head))
++ if (fb_add_videomode(&modedb[i], head) < 0)
+ return;
+ }
+ }
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/crtc.h linux-3.14.72/drivers/video/mxc/crtc.h
+--- linux-3.14.72.orig/drivers/video/mxc/crtc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/crtc.h 2016-06-19 22:11:55.345137382 +0200
+@@ -0,0 +1,57 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __CRTC__
++#define __CRTC__
++
++enum crtc {
++ CRTC_IPU_DI0,
++ CRTC_IPU_DI1,
++ CRTC_IPU1_DI0,
++ CRTC_IPU1_DI1,
++ CRTC_IPU2_DI0,
++ CRTC_IPU2_DI1,
++ CRTC_LCDIF,
++ CRTC_LCDIF1,
++ CRTC_LCDIF2,
++ CRTC_MAX,
++};
++
++struct ipu_di_crtc_map {
++ enum crtc crtc;
++ int ipu_id;
++ int ipu_di;
++};
++
++static const struct ipu_di_crtc_map ipu_di_crtc_maps[] = {
++ {CRTC_IPU1_DI0, 0 , 0}, {CRTC_IPU1_DI1, 0 , 1},
++ {CRTC_IPU2_DI0, 1 , 0}, {CRTC_IPU2_DI1, 1 , 1},
++};
++
++static inline int ipu_di_to_crtc(struct device *dev, int ipu_id,
++ int ipu_di, enum crtc *crtc)
++{
++ int i = 0;
++
++ for (; i < ARRAY_SIZE(ipu_di_crtc_maps); i++)
++ if (ipu_di_crtc_maps[i].ipu_id == ipu_id &&
++ ipu_di_crtc_maps[i].ipu_di == ipu_di) {
++ *crtc = ipu_di_crtc_maps[i].crtc;
++ return 0;
++ }
++
++ dev_err(dev, "failed to get valid ipu di crtc "
++ "ipu_id %d, ipu_di %d\n", ipu_id, ipu_di);
++ return -EINVAL;
++}
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/epdc_regs.h linux-3.14.72/drivers/video/mxc/epdc_regs.h
+--- linux-3.14.72.orig/drivers/video/mxc/epdc_regs.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/epdc_regs.h 2016-06-19 22:11:55.345137382 +0200
+@@ -0,0 +1,442 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef __EPDC_REGS_INCLUDED__
++#define __EPDC_REGS_INCLUDED__
++
++extern void __iomem *epdc_base;
++
++/*************************************
++ * Register addresses
++ **************************************/
++
++#define EPDC_CTRL (epdc_base + 0x000)
++#define EPDC_CTRL_SET (epdc_base + 0x004)
++#define EPDC_CTRL_CLEAR (epdc_base + 0x008)
++#define EPDC_CTRL_TOGGLE (epdc_base + 0x00C)
++#define EPDC_WVADDR (epdc_base + 0x020)
++#define EPDC_WB_ADDR (epdc_base + 0x030)
++#define EPDC_RES (epdc_base + 0x040)
++#define EPDC_FORMAT (epdc_base + 0x050)
++#define EPDC_FORMAT_SET (epdc_base + 0x054)
++#define EPDC_FORMAT_CLEAR (epdc_base + 0x058)
++#define EPDC_FORMAT_TOGGLE (epdc_base + 0x05C)
++#define EPDC_FIFOCTRL (epdc_base + 0x0A0)
++#define EPDC_FIFOCTRL_SET (epdc_base + 0x0A4)
++#define EPDC_FIFOCTRL_CLEAR (epdc_base + 0x0A8)
++#define EPDC_FIFOCTRL_TOGGLE (epdc_base + 0x0AC)
++#define EPDC_UPD_ADDR (epdc_base + 0x100)
++#define EPDC_UPD_STRIDE (epdc_base + 0x110)
++#define EPDC_UPD_CORD (epdc_base + 0x120)
++#define EPDC_UPD_SIZE (epdc_base + 0x140)
++#define EPDC_UPD_CTRL (epdc_base + 0x160)
++#define EPDC_UPD_FIXED (epdc_base + 0x180)
++#define EPDC_TEMP (epdc_base + 0x1A0)
++#define EPDC_AUTOWV_LUT (epdc_base + 0x1C0)
++#define EPDC_TCE_CTRL (epdc_base + 0x200)
++#define EPDC_TCE_SDCFG (epdc_base + 0x220)
++#define EPDC_TCE_GDCFG (epdc_base + 0x240)
++#define EPDC_TCE_HSCAN1 (epdc_base + 0x260)
++#define EPDC_TCE_HSCAN2 (epdc_base + 0x280)
++#define EPDC_TCE_VSCAN (epdc_base + 0x2A0)
++#define EPDC_TCE_OE (epdc_base + 0x2C0)
++#define EPDC_TCE_POLARITY (epdc_base + 0x2E0)
++#define EPDC_TCE_TIMING1 (epdc_base + 0x300)
++#define EPDC_TCE_TIMING2 (epdc_base + 0x310)
++#define EPDC_TCE_TIMING3 (epdc_base + 0x320)
++#define EPDC_PIGEON_CTRL0 (epdc_base + 0x380)
++#define EPDC_PIGEON_CTRL1 (epdc_base + 0x390)
++#define EPDC_IRQ_MASK1 (epdc_base + 0x3C0)
++#define EPDC_IRQ_MASK1_SET (epdc_base + 0x3C4)
++#define EPDC_IRQ_MASK1_CLEAR (epdc_base + 0x3C8)
++#define EPDC_IRQ_MASK1_TOGGLE (epdc_base + 0x3CC)
++#define EPDC_IRQ_MASK2 (epdc_base + 0x3D0)
++#define EPDC_IRQ_MASK2_SET (epdc_base + 0x3D4)
++#define EPDC_IRQ_MASK2_CLEAR (epdc_base + 0x3D8)
++#define EPDC_IRQ_MASK2_TOGGLE (epdc_base + 0x3DC)
++#define EPDC_IRQ1 (epdc_base + 0x3E0)
++#define EPDC_IRQ1_SET (epdc_base + 0x3E4)
++#define EPDC_IRQ1_CLEAR (epdc_base + 0x3E8)
++#define EPDC_IRQ1_TOGGLE (epdc_base + 0x3EC)
++#define EPDC_IRQ2 (epdc_base + 0x3F0)
++#define EPDC_IRQ2_SET (epdc_base + 0x3F4)
++#define EPDC_IRQ2_CLEAR (epdc_base + 0x3F8)
++#define EPDC_IRQ2_TOGGLE (epdc_base + 0x3FC)
++#define EPDC_IRQ_MASK (epdc_base + 0x400)
++#define EPDC_IRQ_MASK_SET (epdc_base + 0x404)
++#define EPDC_IRQ_MASK_CLEAR (epdc_base + 0x408)
++#define EPDC_IRQ_MASK_TOGGLE (epdc_base + 0x40C)
++#define EPDC_IRQ (epdc_base + 0x420)
++#define EPDC_IRQ_SET (epdc_base + 0x424)
++#define EPDC_IRQ_CLEAR (epdc_base + 0x428)
++#define EPDC_IRQ_TOGGLE (epdc_base + 0x42C)
++#define EPDC_STATUS_LUTS (epdc_base + 0x440)
++#define EPDC_STATUS_LUTS_SET (epdc_base + 0x444)
++#define EPDC_STATUS_LUTS_CLEAR (epdc_base + 0x448)
++#define EPDC_STATUS_LUTS_TOGGLE (epdc_base + 0x44C)
++#define EPDC_STATUS_LUTS2 (epdc_base + 0x450)
++#define EPDC_STATUS_LUTS2_SET (epdc_base + 0x454)
++#define EPDC_STATUS_LUTS2_CLEAR (epdc_base + 0x458)
++#define EPDC_STATUS_LUTS2_TOGGLE (epdc_base + 0x45C)
++#define EPDC_STATUS_NEXTLUT (epdc_base + 0x460)
++#define EPDC_STATUS_COL (epdc_base + 0x480)
++#define EPDC_STATUS_COL2 (epdc_base + 0x490)
++#define EPDC_STATUS (epdc_base + 0x4A0)
++#define EPDC_STATUS_SET (epdc_base + 0x4A4)
++#define EPDC_STATUS_CLEAR (epdc_base + 0x4A8)
++#define EPDC_STATUS_TOGGLE (epdc_base + 0x4AC)
++#define EPDC_UPD_COL_CORD (epdc_base + 0x4C0)
++#define EPDC_UPD_COL_SIZE (epdc_base + 0x4E0)
++#define EPDC_DEBUG (epdc_base + 0x500)
++#define EPDC_DEBUG_LUT (epdc_base + 0x530)
++#define EPDC_HIST1_PARAM (epdc_base + 0x600)
++#define EPDC_HIST2_PARAM (epdc_base + 0x610)
++#define EPDC_HIST4_PARAM (epdc_base + 0x620)
++#define EPDC_HIST8_PARAM0 (epdc_base + 0x630)
++#define EPDC_HIST8_PARAM1 (epdc_base + 0x640)
++#define EPDC_HIST16_PARAM0 (epdc_base + 0x650)
++#define EPDC_HIST16_PARAM1 (epdc_base + 0x660)
++#define EPDC_HIST16_PARAM2 (epdc_base + 0x670)
++#define EPDC_HIST16_PARAM3 (epdc_base + 0x680)
++#define EPDC_GPIO (epdc_base + 0x700)
++#define EPDC_VERSION (epdc_base + 0x7F0)
++#define EPDC_PIGEON_0_0 (epdc_base + 0x800)
++#define EPDC_PIGEON_0_1 (epdc_base + 0x810)
++#define EPDC_PIGEON_0_2 (epdc_base + 0x820)
++#define EPDC_PIGEON_1_0 (epdc_base + 0x840)
++#define EPDC_PIGEON_1_1 (epdc_base + 0x850)
++#define EPDC_PIGEON_1_2 (epdc_base + 0x860)
++#define EPDC_PIGEON_2_0 (epdc_base + 0x880)
++#define EPDC_PIGEON_2_1 (epdc_base + 0x890)
++#define EPDC_PIGEON_2_2 (epdc_base + 0x8A0)
++#define EPDC_PIGEON_3_0 (epdc_base + 0x8C0)
++#define EPDC_PIGEON_3_1 (epdc_base + 0x8D0)
++#define EPDC_PIGEON_3_2 (epdc_base + 0x8E0)
++#define EPDC_PIGEON_4_0 (epdc_base + 0x900)
++#define EPDC_PIGEON_4_1 (epdc_base + 0x910)
++#define EPDC_PIGEON_4_2 (epdc_base + 0x920)
++#define EPDC_PIGEON_5_0 (epdc_base + 0x940)
++#define EPDC_PIGEON_5_1 (epdc_base + 0x950)
++#define EPDC_PIGEON_5_2 (epdc_base + 0x960)
++#define EPDC_PIGEON_6_0 (epdc_base + 0x980)
++#define EPDC_PIGEON_6_1 (epdc_base + 0x990)
++#define EPDC_PIGEON_6_2 (epdc_base + 0x9A0)
++#define EPDC_PIGEON_7_0 (epdc_base + 0x9C0)
++#define EPDC_PIGEON_7_1 (epdc_base + 0x9D0)
++#define EPDC_PIGEON_7_2 (epdc_base + 0x9E0)
++#define EPDC_PIGEON_8_0 (epdc_base + 0xA00)
++#define EPDC_PIGEON_8_1 (epdc_base + 0xA10)
++#define EPDC_PIGEON_8_2 (epdc_base + 0xA20)
++#define EPDC_PIGEON_9_0 (epdc_base + 0xA40)
++#define EPDC_PIGEON_9_1 (epdc_base + 0xA50)
++#define EPDC_PIGEON_9_2 (epdc_base + 0xA60)
++#define EPDC_PIGEON_10_0 (epdc_base + 0xA80)
++#define EPDC_PIGEON_10_1 (epdc_base + 0xA90)
++#define EPDC_PIGEON_10_2 (epdc_base + 0xAA0)
++#define EPDC_PIGEON_11_0 (epdc_base + 0xAC0)
++#define EPDC_PIGEON_11_1 (epdc_base + 0xAD0)
++#define EPDC_PIGEON_11_2 (epdc_base + 0xAE0)
++#define EPDC_PIGEON_12_0 (epdc_base + 0xB00)
++#define EPDC_PIGEON_12_1 (epdc_base + 0xB10)
++#define EPDC_PIGEON_12_2 (epdc_base + 0xB20)
++#define EPDC_PIGEON_13_0 (epdc_base + 0xB40)
++#define EPDC_PIGEON_13_1 (epdc_base + 0xB50)
++#define EPDC_PIGEON_13_2 (epdc_base + 0xB60)
++#define EPDC_PIGEON_14_0 (epdc_base + 0xB80)
++#define EPDC_PIGEON_14_1 (epdc_base + 0xB90)
++#define EPDC_PIGEON_14_2 (epdc_base + 0xBA0)
++#define EPDC_PIGEON_15_0 (epdc_base + 0xBC0)
++#define EPDC_PIGEON_15_1 (epdc_base + 0xBD0)
++#define EPDC_PIGEON_15_2 (epdc_base + 0xBE0)
++#define EPDC_WB_ADDR_TCE (epdc_base + 0xC10)
++
++/*
++ * Register field definitions
++ */
++
++enum {
++/* EPDC_CTRL field values */
++ EPDC_CTRL_SFTRST = 0x80000000,
++ EPDC_CTRL_CLKGATE = 0x40000000,
++ EPDC_CTRL_SRAM_POWERDOWN = 0x100,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80,
++ EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20,
++ EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30,
++ EPDC_CTRL_BURST_LEN_8_8 = 0x1,
++ EPDC_CTRL_BURST_LEN_8_16 = 0,
++
++/* EPDC_RES field values */
++ EPDC_RES_VERTICAL_MASK = 0x1FFF0000,
++ EPDC_RES_VERTICAL_OFFSET = 16,
++ EPDC_RES_HORIZONTAL_MASK = 0x1FFF,
++ EPDC_RES_HORIZONTAL_OFFSET = 0,
++
++/* EPDC_FORMAT field values */
++ EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000,
++ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000,
++ EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK = 0x700,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400,
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2,
++ EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3,
++
++/* EPDC_FIFOCTRL field values */
++ EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000,
++ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000,
++ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16,
++ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00,
++ EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8,
++ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF,
++ EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0,
++
++/* EPDC_UPD_CORD field values */
++ EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000,
++ EPDC_UPD_CORD_YCORD_OFFSET = 16,
++ EPDC_UPD_CORD_XCORD_MASK = 0x1FFF,
++ EPDC_UPD_CORD_XCORD_OFFSET = 0,
++
++/* EPDC_UPD_SIZE field values */
++ EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000,
++ EPDC_UPD_SIZE_HEIGHT_OFFSET = 16,
++ EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF,
++ EPDC_UPD_SIZE_WIDTH_OFFSET = 0,
++
++/* EPDC_UPD_CTRL field values */
++ EPDC_UPD_CTRL_USE_FIXED = 0x80000000,
++ EPDC_UPD_CTRL_LUT_SEL_MASK = 0x3F0000,
++ EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16,
++ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00,
++ EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8,
++ EPDC_UPD_CTRL_AUTOWV_PAUSE = 0x8,
++ EPDC_UPD_CTRL_AUTOWV = 0x4,
++ EPDC_UPD_CTRL_DRY_RUN = 0x2,
++ EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1,
++
++/* EPDC_UPD_FIXED field values */
++ EPDC_UPD_FIXED_FIXNP_EN = 0x80000000,
++ EPDC_UPD_FIXED_FIXCP_EN = 0x40000000,
++ EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00,
++ EPDC_UPD_FIXED_FIXNP_OFFSET = 8,
++ EPDC_UPD_FIXED_FIXCP_MASK = 0xFF,
++ EPDC_UPD_FIXED_FIXCP_OFFSET = 0,
++
++/* EPDC_AUTOWV_LUT field values */
++ EPDC_AUTOWV_LUT_DATA_MASK = 0xFF0000,
++ EPDC_AUTOWV_LUT_DATA_OFFSET = 16,
++ EPDC_AUTOWV_LUT_ADDR_MASK = 0xFF,
++ EPDC_AUTOWV_LUT_ADDR_OFFSET = 0,
++
++/* EPDC_TCE_CTRL field values */
++ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000,
++ EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16,
++ EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00,
++ EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10,
++ EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200,
++ EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000,
++ EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100,
++ EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80,
++ EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40,
++ EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20,
++ EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10,
++ EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8,
++ EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4,
++ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1,
++ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2,
++ EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3,
++
++/* EPDC_TCE_SDCFG field values */
++ EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000,
++ EPDC_TCE_SDCFG_SDSHR = 0x100000,
++ EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000,
++ EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16,
++ EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0,
++ EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000,
++ EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000,
++ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF,
++ EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0,
++
++/* EPDC_TCE_GDCFG field values */
++ EPDC_TCE_SDCFG_GDRL = 0x10,
++ EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2,
++ EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1,
++ EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0,
++
++/* EPDC_TCE_HSCAN1 field values */
++ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000,
++ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16,
++ EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF,
++ EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0,
++
++/* EPDC_TCE_HSCAN2 field values */
++ EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000,
++ EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16,
++ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF,
++ EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0,
++
++/* EPDC_TCE_VSCAN field values */
++ EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000,
++ EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16,
++ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00,
++ EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8,
++ EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF,
++ EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0,
++
++/* EPDC_TCE_OE field values */
++ EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000,
++ EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24,
++ EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000,
++ EPDC_TCE_OE_SDOED_DLY_OFFSET = 16,
++ EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00,
++ EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8,
++ EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF,
++ EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0,
++
++/* EPDC_TCE_POLARITY field values */
++ EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10,
++ EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8,
++ EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4,
++ EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2,
++ EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1,
++
++/* EPDC_TCE_TIMING1 field values */
++ EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00,
++ EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10,
++ EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20,
++ EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30,
++ EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2,
++ EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3,
++
++/* EPDC_TCE_TIMING2 field values */
++ EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000,
++ EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16,
++ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF,
++ EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0,
++
++/* EPDC_TCE_TIMING3 field values */
++ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000,
++ EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16,
++ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF,
++ EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0,
++
++/* EPDC_IRQ_MASK/EPDC_IRQ field values */
++ EPDC_IRQ_WB_CMPLT_IRQ = 0x10000,
++ EPDC_IRQ_LUT_COL_IRQ = 0x20000,
++ EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000,
++ EPDC_IRQ_FRAME_END_IRQ = 0x80000,
++ EPDC_IRQ_BUS_ERROR_IRQ = 0x100000,
++ EPDC_IRQ_TCE_IDLE_IRQ = 0x200000,
++ EPDC_IRQ_UPD_DONE_IRQ = 0x400000,
++ EPDC_IRQ_PWR_IRQ = 0x800000,
++
++/* EPDC_STATUS_NEXTLUT field values */
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100,
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0x3F,
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0,
++
++/* EPDC_STATUS field values */
++ EPDC_STATUS_HISTOGRAM_CP_MASK = 0x1F0000,
++ EPDC_STATUS_HISTOGRAM_CP_OFFSET = 16,
++ EPDC_STATUS_HISTOGRAM_NP_MASK = 0x1F00,
++ EPDC_STATUS_HISTOGRAM_NP_OFFSET = 8,
++ EPDC_STATUS_UPD_VOID = 0x8,
++ EPDC_STATUS_LUTS_UNDERRUN = 0x4,
++ EPDC_STATUS_LUTS_BUSY = 0x2,
++ EPDC_STATUS_WB_BUSY = 0x1,
++
++/* EPDC_UPD_COL_CORD field values */
++ EPDC_UPD_COL_CORD_YCORD_MASK = 0x1FFF0000,
++ EPDC_UPD_COL_CORD_YCORD_OFFSET = 16,
++ EPDC_UPD_COL_CORD_XCORD_MASK = 0x1FFF,
++ EPDC_UPD_COL_CORD_XCORD_OFFSET = 0,
++
++/* EPDC_UPD_COL_SIZE field values */
++ EPDC_UPD_COL_SIZE_HEIGHT_MASK = 0x1FFF0000,
++ EPDC_UPD_COL_SIZE_HEIGHT_OFFSET = 16,
++ EPDC_UPD_COL_SIZE_WIDTH_MASK = 0x1FFF,
++ EPDC_UPD_COL_SIZE_WIDTH_OFFSET = 0,
++
++/* EPDC_DEBUG field values */
++ EPDC_DEBUG_UNDERRUN_RECOVER = 0x2,
++ EPDC_DEBUG_COLLISION_OFF = 0x1,
++
++/* EPDC_HISTx_PARAM field values */
++ EPDC_HIST_PARAM_VALUE0_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE0_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE1_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE1_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE2_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE2_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE3_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE3_OFFSET = 24,
++ EPDC_HIST_PARAM_VALUE4_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE4_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE5_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE5_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE6_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE6_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE7_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE7_OFFSET = 24,
++ EPDC_HIST_PARAM_VALUE8_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE8_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE9_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE9_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE10_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE10_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE11_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE11_OFFSET = 24,
++ EPDC_HIST_PARAM_VALUE12_MASK = 0x1F,
++ EPDC_HIST_PARAM_VALUE12_OFFSET = 0,
++ EPDC_HIST_PARAM_VALUE13_MASK = 0x1F00,
++ EPDC_HIST_PARAM_VALUE13_OFFSET = 8,
++ EPDC_HIST_PARAM_VALUE14_MASK = 0x1F0000,
++ EPDC_HIST_PARAM_VALUE14_OFFSET = 16,
++ EPDC_HIST_PARAM_VALUE15_MASK = 0x1F000000,
++ EPDC_HIST_PARAM_VALUE15_OFFSET = 24,
++
++/* EPDC_GPIO field values */
++ EPDC_GPIO_PWRCOM = 0x40,
++ EPDC_GPIO_PWRCTRL_MASK = 0x3C,
++ EPDC_GPIO_PWRCTRL_OFFSET = 2,
++ EPDC_GPIO_BDR_MASK = 0x3,
++ EPDC_GPIO_BDR_OFFSET = 0,
++
++/* EPDC_VERSION field values */
++ EPDC_VERSION_MAJOR_MASK = 0xFF000000,
++ EPDC_VERSION_MAJOR_OFFSET = 24,
++ EPDC_VERSION_MINOR_MASK = 0xFF0000,
++ EPDC_VERSION_MINOR_OFFSET = 16,
++ EPDC_VERSION_STEP_MASK = 0xFFFF,
++ EPDC_VERSION_STEP_OFFSET = 0,
++};
++
++#endif /* __EPDC_REGS_INCLUDED__ */
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/hannstar_cabc.c linux-3.14.72/drivers/video/mxc/hannstar_cabc.c
+--- linux-3.14.72.orig/drivers/video/mxc/hannstar_cabc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/hannstar_cabc.c 2016-06-19 22:11:55.345137382 +0200
+@@ -0,0 +1,89 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++
++#define DRIVER_NAME "hannstar-cabc"
++
++static const struct of_device_id cabc_dt_ids[] = {
++ { .compatible = "hannstar,cabc", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, cabc_dt_ids);
++
++static int cabc_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node, *pp;
++ int cabc_gpio, ret = 0;
++ bool cabc_enable;
++ unsigned long gpio_flag;
++ enum of_gpio_flags flags;
++
++ for_each_child_of_node(np, pp) {
++ if (!of_find_property(pp, "gpios", NULL)) {
++ dev_warn(&pdev->dev, "Found interface without "
++ "gpios\n");
++ continue;
++ }
++
++ cabc_gpio = of_get_gpio_flags(pp, 0, &flags);
++ if (!gpio_is_valid(cabc_gpio)) {
++ ret = cabc_gpio;
++ if (ret != -EPROBE_DEFER)
++ dev_err(&pdev->dev,
++ "Failed to get gpio flags, "
++ "error: %d\n", ret);
++ return ret;
++ }
++
++ cabc_enable = of_property_read_bool(pp, "cabc-enable");
++
++ if (flags & OF_GPIO_ACTIVE_LOW)
++ gpio_flag = cabc_enable ?
++ GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
++ else
++ gpio_flag = cabc_enable ?
++ GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++
++ devm_gpio_request_one(&pdev->dev, cabc_gpio,
++ gpio_flag, "hannstar-cabc");
++ }
++
++ return ret;
++}
++
++static struct platform_driver cabc_driver = {
++ .probe = cabc_probe,
++ .driver = {
++ .of_match_table = cabc_dt_ids,
++ .name = DRIVER_NAME,
++ .owner = THIS_MODULE,
++ },
++};
++module_platform_driver(cabc_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Hannstar CABC driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/Kconfig linux-3.14.72/drivers/video/mxc/Kconfig
+--- linux-3.14.72.orig/drivers/video/mxc/Kconfig 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/Kconfig 2016-06-19 22:11:55.345137382 +0200
+@@ -0,0 +1,82 @@
++config FB_MXC
++ tristate "MXC Framebuffer support"
++ depends on FB
++ select FB_CFB_FILLRECT
++ select FB_CFB_COPYAREA
++ select FB_CFB_IMAGEBLIT
++ select FB_MODE_HELPERS
++ default y
++ help
++ This is a framebuffer device for the MXC LCD Controller.
++ See <http://www.linux-fbdev.org/> for information on framebuffer
++ devices.
++
++ If you plan to use the LCD display with your MXC system, say
++ Y here.
++
++config FB_MXC_SYNC_PANEL
++ depends on FB_MXC
++ tristate "Synchronous Panel Framebuffer"
++
++config FB_MXC_TVOUT_ADV739X
++ tristate "ADV7390/7391 TV Out Encoder"
++ depends on FB_MXC_SYNC_PANEL && I2C
++
++config FB_MXC_LDB
++ tristate "MXC LDB"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3 || FB_MXS
++ select VIDEOMODE_HELPERS
++
++config FB_MXC_MIPI_DSI
++ tristate "MXC MIPI_DSI"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3
++
++config FB_MXC_TRULY_WVGA_SYNC_PANEL
++ tristate "TRULY WVGA Panel"
++ depends on FB_MXC_SYNC_PANEL
++ depends on FB_MXC_MIPI_DSI
++
++config FB_MXC_HDMI
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3
++ depends on I2C
++ tristate "MXC HDMI driver support"
++ select MFD_MXC_HDMI
++ help
++ Driver for the on-chip MXC HDMI controller.
++
++config FB_MXC_EDID
++ depends on FB_MXC && I2C
++ tristate "MXC EDID support"
++ default y
++
++config FB_MXC_EINK_PANEL
++ depends on FB_MXC
++ depends on DMA_ENGINE
++ select FB_DEFERRED_IO
++ tristate "E-Ink Panel Framebuffer"
++
++config FB_MXC_EINK_AUTO_UPDATE_MODE
++ bool "E-Ink Auto-update Mode Support"
++ default n
++ depends on FB_MXC_EINK_PANEL
++
++config FB_MXS_SII902X
++ tristate "Si Image SII9022 DVI/HDMI Interface Chip"
++ depends on FB_MXS && I2C
++
++config FB_MXC_DCIC
++ tristate "MXC DCIC"
++ depends on FB_MXC_SYNC_PANEL
++ depends on MXC_IPU_V3 || FB_MXS
++ select VIDEOMODE_HELPERS
++
++config HANNSTAR_CABC
++ tristate "Hannstar CABC function"
++ help
++ Say yes here to support switching on/off Hannstar CABC
++ function. This function turns backlight density of a
++ display panel automatically according to the content
++ shown on the panel.
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/ldb.c linux-3.14.72/drivers/video/mxc/ldb.c
+--- linux-3.14.72.orig/drivers/video/mxc/ldb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/ldb.c 2016-06-19 22:11:55.345137382 +0200
+@@ -0,0 +1,892 @@
++/*
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/types.h>
++#include <video/of_videomode.h>
++#include <video/of_display_timing.h>
++#include <video/videomode.h>
++#include "mxc_dispdrv.h"
++
++#define DRIVER_NAME "ldb"
++
++#define LDB_BGREF_RMODE_INT (0x1 << 15)
++
++#define LDB_DI1_VS_POL_ACT_LOW (0x1 << 10)
++#define LDB_DI0_VS_POL_ACT_LOW (0x1 << 9)
++
++#define LDB_BIT_MAP_CH1_JEIDA (0x1 << 8)
++#define LDB_BIT_MAP_CH0_JEIDA (0x1 << 6)
++
++#define LDB_DATA_WIDTH_CH1_24 (0x1 << 7)
++#define LDB_DATA_WIDTH_CH0_24 (0x1 << 5)
++
++#define LDB_CH1_MODE_MASK (0x3 << 2)
++#define LDB_CH1_MODE_EN_TO_DI1 (0x3 << 2)
++#define LDB_CH1_MODE_EN_TO_DI0 (0x1 << 2)
++#define LDB_CH0_MODE_MASK (0x3 << 0)
++#define LDB_CH0_MODE_EN_TO_DI1 (0x3 << 0)
++#define LDB_CH0_MODE_EN_TO_DI0 (0x1 << 0)
++
++#define LDB_SPLIT_MODE_EN (0x1 << 4)
++
++#define INVALID_BUS_REG (~0UL)
++
++struct crtc_mux {
++ enum crtc crtc;
++ u32 val;
++};
++
++struct bus_mux {
++ int reg;
++ int shift;
++ int mask;
++ int crtc_mux_num;
++ const struct crtc_mux *crtcs;
++};
++
++struct ldb_info {
++ bool split_cap;
++ bool dual_cap;
++ bool ext_bgref_cap;
++ int ctrl_reg;
++ int bus_mux_num;
++ const struct bus_mux *buses;
++};
++
++struct ldb_data;
++
++struct ldb_chan {
++ struct ldb_data *ldb;
++ struct fb_info *fbi;
++ struct videomode vm;
++ enum crtc crtc;
++ int chno;
++ bool is_used;
++ bool online;
++};
++
++struct ldb_data {
++ struct regmap *regmap;
++ struct device *dev;
++ struct mxc_dispdrv_handle *mddh;
++ struct ldb_chan chan[2];
++ int bus_mux_num;
++ const struct bus_mux *buses;
++ int primary_chno;
++ int ctrl_reg;
++ u32 ctrl;
++ bool spl_mode;
++ bool dual_mode;
++ struct clk *di_clk[4];
++ struct clk *ldb_di_clk[2];
++ struct clk *div_3_5_clk[2];
++ struct clk *div_7_clk[2];
++ struct clk *div_sel_clk[2];
++};
++
++static const struct crtc_mux imx6q_lvds0_crtc_mux[] = {
++ {
++ .crtc = CRTC_IPU1_DI0,
++ .val = IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0,
++ }, {
++ .crtc = CRTC_IPU1_DI1,
++ .val = IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1,
++ }, {
++ .crtc = CRTC_IPU2_DI0,
++ .val = IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0,
++ }, {
++ .crtc = CRTC_IPU2_DI1,
++ .val = IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1,
++ }
++};
++
++static const struct crtc_mux imx6q_lvds1_crtc_mux[] = {
++ {
++ .crtc = CRTC_IPU1_DI0,
++ .val = IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0,
++ }, {
++ .crtc = CRTC_IPU1_DI1,
++ .val = IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1,
++ }, {
++ .crtc = CRTC_IPU2_DI0,
++ .val = IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0,
++ }, {
++ .crtc = CRTC_IPU2_DI1,
++ .val = IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1,
++ }
++};
++
++static const struct bus_mux imx6q_ldb_buses[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .shift = 6,
++ .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
++ .crtc_mux_num = ARRAY_SIZE(imx6q_lvds0_crtc_mux),
++ .crtcs = imx6q_lvds0_crtc_mux,
++ }, {
++ .reg = IOMUXC_GPR3,
++ .shift = 8,
++ .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
++ .crtc_mux_num = ARRAY_SIZE(imx6q_lvds1_crtc_mux),
++ .crtcs = imx6q_lvds1_crtc_mux,
++ }
++};
++
++static const struct ldb_info imx6q_ldb_info = {
++ .split_cap = true,
++ .dual_cap = true,
++ .ext_bgref_cap = false,
++ .ctrl_reg = IOMUXC_GPR2,
++ .bus_mux_num = ARRAY_SIZE(imx6q_ldb_buses),
++ .buses = imx6q_ldb_buses,
++};
++
++static const struct crtc_mux imx6dl_lvds0_crtc_mux[] = {
++ {
++ .crtc = CRTC_IPU1_DI0,
++ .val = IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0,
++ }, {
++ .crtc = CRTC_IPU1_DI1,
++ .val = IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1,
++ }, {
++ .crtc = CRTC_LCDIF1,
++ .val = IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF,
++ }
++};
++
++static const struct crtc_mux imx6dl_lvds1_crtc_mux[] = {
++ {
++ .crtc = CRTC_IPU1_DI0,
++ .val = IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0,
++ }, {
++ .crtc = CRTC_IPU1_DI1,
++ .val = IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1,
++ }, {
++ .crtc = CRTC_LCDIF1,
++ .val = IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF,
++ }
++};
++
++static const struct bus_mux imx6dl_ldb_buses[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .shift = 6,
++ .mask = IMX6DL_GPR3_LVDS0_MUX_CTL_MASK,
++ .crtc_mux_num = ARRAY_SIZE(imx6dl_lvds0_crtc_mux),
++ .crtcs = imx6dl_lvds0_crtc_mux,
++ }, {
++ .reg = IOMUXC_GPR3,
++ .shift = 8,
++ .mask = IMX6DL_GPR3_LVDS1_MUX_CTL_MASK,
++ .crtc_mux_num = ARRAY_SIZE(imx6dl_lvds1_crtc_mux),
++ .crtcs = imx6dl_lvds1_crtc_mux,
++ }
++};
++
++static const struct ldb_info imx6dl_ldb_info = {
++ .split_cap = true,
++ .dual_cap = true,
++ .ext_bgref_cap = false,
++ .ctrl_reg = IOMUXC_GPR2,
++ .bus_mux_num = ARRAY_SIZE(imx6dl_ldb_buses),
++ .buses = imx6dl_ldb_buses,
++};
++
++static const struct crtc_mux imx6sx_lvds_crtc_mux[] = {
++ {
++ .crtc = CRTC_LCDIF1,
++ .val = IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1,
++ }, {
++ .crtc = CRTC_LCDIF2,
++ .val = IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2,
++ }
++};
++
++static const struct bus_mux imx6sx_ldb_buses[] = {
++ {
++ .reg = IOMUXC_GPR5,
++ .shift = 3,
++ .mask = IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK,
++ .crtc_mux_num = ARRAY_SIZE(imx6sx_lvds_crtc_mux),
++ .crtcs = imx6sx_lvds_crtc_mux,
++ }
++};
++
++static const struct ldb_info imx6sx_ldb_info = {
++ .split_cap = false,
++ .dual_cap = false,
++ .ext_bgref_cap = false,
++ .ctrl_reg = IOMUXC_GPR6,
++ .bus_mux_num = ARRAY_SIZE(imx6sx_ldb_buses),
++ .buses = imx6sx_ldb_buses,
++};
++
++static const struct crtc_mux imx53_lvds0_crtc_mux[] = {
++ { .crtc = CRTC_IPU1_DI0, },
++};
++
++static const struct crtc_mux imx53_lvds1_crtc_mux[] = {
++ { .crtc = CRTC_IPU1_DI1, }
++};
++
++static const struct bus_mux imx53_ldb_buses[] = {
++ {
++ .reg = INVALID_BUS_REG,
++ .crtc_mux_num = ARRAY_SIZE(imx53_lvds0_crtc_mux),
++ .crtcs = imx53_lvds0_crtc_mux,
++ }, {
++ .reg = INVALID_BUS_REG,
++ .crtc_mux_num = ARRAY_SIZE(imx53_lvds1_crtc_mux),
++ .crtcs = imx53_lvds1_crtc_mux,
++ }
++};
++
++static const struct ldb_info imx53_ldb_info = {
++ .split_cap = true,
++ .dual_cap = false,
++ .ext_bgref_cap = true,
++ .ctrl_reg = IOMUXC_GPR2,
++ .bus_mux_num = ARRAY_SIZE(imx53_ldb_buses),
++ .buses = imx53_ldb_buses,
++};
++
++static const struct of_device_id ldb_dt_ids[] = {
++ { .compatible = "fsl,imx6q-ldb", .data = &imx6q_ldb_info, },
++ { .compatible = "fsl,imx6dl-ldb", .data = &imx6dl_ldb_info, },
++ { .compatible = "fsl,imx6sx-ldb", .data = &imx6sx_ldb_info, },
++ { .compatible = "fsl,imx53-ldb", .data = &imx53_ldb_info, },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ldb_dt_ids);
++
++static int ldb_init(struct mxc_dispdrv_handle *mddh,
++ struct mxc_dispdrv_setting *setting)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(mddh);
++ struct device *dev = ldb->dev;
++ struct fb_info *fbi = setting->fbi;
++ struct ldb_chan *chan;
++ struct fb_videomode fb_vm;
++ int chno;
++
++ chno = ldb->chan[ldb->primary_chno].is_used ?
++ !ldb->primary_chno : ldb->primary_chno;
++
++ chan = &ldb->chan[chno];
++
++ if (chan->is_used) {
++ dev_err(dev, "LVDS channel%d is already used\n", chno);
++ return -EBUSY;
++ }
++ if (!chan->online) {
++ dev_err(dev, "LVDS channel%d is not online\n", chno);
++ return -ENODEV;
++ }
++
++ chan->is_used = true;
++
++ chan->fbi = fbi;
++
++ fb_videomode_from_videomode(&chan->vm, &fb_vm);
++
++ INIT_LIST_HEAD(&fbi->modelist);
++ fb_add_videomode(&fb_vm, &fbi->modelist);
++ fb_videomode_to_var(&fbi->var, &fb_vm);
++
++ setting->crtc = chan->crtc;
++
++ return 0;
++}
++
++static int get_di_clk_id(struct ldb_chan chan, int *id)
++{
++ struct ldb_data *ldb = chan.ldb;
++ int i = 0, chno = chan.chno, mask, shift;
++ enum crtc crtc;
++ u32 val;
++
++ /* no pre-muxing, such as mx53 */
++ if (ldb->buses[chno].reg == INVALID_BUS_REG) {
++ *id = chno;
++ return 0;
++ }
++
++ for (; i < ldb->buses[chno].crtc_mux_num; i++) {
++ crtc = ldb->buses[chno].crtcs[i].crtc;
++ val = ldb->buses[chno].crtcs[i].val;
++ mask = ldb->buses[chno].mask;
++ shift = ldb->buses[chno].shift;
++ if (chan.crtc == crtc) {
++ *id = (val & mask) >> shift;
++ return 0;
++ }
++ }
++
++ return -EINVAL;
++}
++
++static int get_mux_val(struct bus_mux bus_mux, enum crtc crtc,
++ u32 *mux_val)
++{
++ int i = 0;
++
++ for (; i < bus_mux.crtc_mux_num; i++)
++ if (bus_mux.crtcs[i].crtc == crtc) {
++ *mux_val = bus_mux.crtcs[i].val;
++ return 0;
++ }
++
++ return -EINVAL;
++}
++
++static int find_ldb_chno(struct ldb_data *ldb,
++ struct fb_info *fbi, int *chno)
++{
++ struct device *dev = ldb->dev;
++ int i = 0;
++
++ for (; i < 2; i++)
++ if (ldb->chan[i].fbi == fbi) {
++ *chno = ldb->chan[i].chno;
++ return 0;
++ }
++ dev_err(dev, "failed to find channel number\n");
++ return -EINVAL;
++}
++
++static void ldb_disable(struct mxc_dispdrv_handle *mddh,
++ struct fb_info *fbi);
++
++static int ldb_setup(struct mxc_dispdrv_handle *mddh,
++ struct fb_info *fbi)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(mddh);
++ struct ldb_chan chan;
++ struct device *dev = ldb->dev;
++ struct clk *ldb_di_parent, *ldb_di_sel, *ldb_di_sel_parent;
++ struct clk *other_ldb_di_sel = NULL;
++ struct bus_mux bus_mux;
++ int ret = 0, id = 0, chno, other_chno;
++ unsigned long serial_clk;
++ u32 mux_val;
++
++ ret = find_ldb_chno(ldb, fbi, &chno);
++ if (ret < 0)
++ return ret;
++
++ other_chno = chno ? 0 : 1;
++
++ chan = ldb->chan[chno];
++
++ bus_mux = ldb->buses[chno];
++
++ ret = get_di_clk_id(chan, &id);
++ if (ret < 0) {
++ dev_err(dev, "failed to get ch%d di clk id\n",
++ chan.chno);
++ return ret;
++ }
++
++ ret = get_mux_val(bus_mux, chan.crtc, &mux_val);
++ if (ret < 0) {
++ dev_err(dev, "failed to get ch%d mux val\n",
++ chan.chno);
++ return ret;
++ }
++
++ /*
++ * ldb_di_sel_parent(plls) -> ldb_di_sel ->
++ *
++ * -> div_3_5[chno] ->
++ * -> | |-> div_sel[chno] ->
++ * -> div_7[chno] ->
++ *
++ * -> ldb_di[chno] -> di[id]
++ */
++ clk_set_parent(ldb->di_clk[id], ldb->ldb_di_clk[chno]);
++ ldb_di_parent = ldb->spl_mode ? ldb->div_3_5_clk[chno] :
++ ldb->div_7_clk[chno];
++ clk_set_parent(ldb->div_sel_clk[chno], ldb_di_parent);
++ ldb_di_sel = clk_get_parent(ldb_di_parent);
++ ldb_di_sel_parent = clk_get_parent(ldb_di_sel);
++ serial_clk = ldb->spl_mode ? chan.vm.pixelclock * 7 / 2 :
++ chan.vm.pixelclock * 7;
++ clk_set_rate(ldb_di_sel_parent, serial_clk);
++
++ /*
++ * split mode or dual mode:
++ * clock tree for the other channel
++ */
++ if (ldb->spl_mode) {
++ clk_set_parent(ldb->div_sel_clk[other_chno],
++ ldb->div_3_5_clk[other_chno]);
++ other_ldb_di_sel =
++ clk_get_parent(ldb->div_3_5_clk[other_chno]);;
++ }
++
++ if (ldb->dual_mode) {
++ clk_set_parent(ldb->div_sel_clk[other_chno],
++ ldb->div_7_clk[other_chno]);
++ other_ldb_di_sel =
++ clk_get_parent(ldb->div_7_clk[other_chno]);;
++ }
++
++ if (ldb->spl_mode || ldb->dual_mode)
++ clk_set_parent(other_ldb_di_sel, ldb_di_sel_parent);
++
++ if (!(chan.fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)) {
++ if (ldb->spl_mode && bus_mux.reg == INVALID_BUS_REG)
++ /* no pre-muxing, such as mx53 */
++ ldb->ctrl |= (id == 0 ? LDB_DI0_VS_POL_ACT_LOW :
++ LDB_DI1_VS_POL_ACT_LOW);
++ else
++ ldb->ctrl |= (chno == 0 ? LDB_DI0_VS_POL_ACT_LOW :
++ LDB_DI1_VS_POL_ACT_LOW);
++ }
++
++ if (bus_mux.reg != INVALID_BUS_REG)
++ regmap_update_bits(ldb->regmap, bus_mux.reg,
++ bus_mux.mask, mux_val);
++
++ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ctrl);
++
++ /* disable channel for correct sequence */
++ ldb_disable(mddh, fbi);
++
++ return ret;
++}
++
++static int ldb_enable(struct mxc_dispdrv_handle *mddh,
++ struct fb_info *fbi)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(mddh);
++ struct ldb_chan chan;
++ struct device *dev = ldb->dev;
++ struct bus_mux bus_mux;
++ int ret = 0, id = 0, chno, other_chno;
++
++ ret = find_ldb_chno(ldb, fbi, &chno);
++ if (ret < 0)
++ return ret;
++
++ chan = ldb->chan[chno];
++
++ bus_mux = ldb->buses[chno];
++
++ if (ldb->spl_mode || ldb->dual_mode) {
++ other_chno = chno ? 0 : 1;
++ clk_prepare_enable(ldb->ldb_di_clk[other_chno]);
++ }
++
++ if ((ldb->spl_mode || ldb->dual_mode) &&
++ bus_mux.reg == INVALID_BUS_REG) {
++ /* no pre-muxing, such as mx53 */
++ ret = get_di_clk_id(chan, &id);
++ if (ret < 0) {
++ dev_err(dev, "failed to get ch%d di clk id\n",
++ chan.chno);
++ return ret;
++ }
++
++ ldb->ctrl |= id ?
++ (LDB_CH0_MODE_EN_TO_DI1 | LDB_CH1_MODE_EN_TO_DI1) :
++ (LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0);
++ } else {
++ if (ldb->spl_mode || ldb->dual_mode)
++ ldb->ctrl |= LDB_CH0_MODE_EN_TO_DI0 |
++ LDB_CH1_MODE_EN_TO_DI0;
++ else
++ ldb->ctrl |= chno ? LDB_CH1_MODE_EN_TO_DI1 :
++ LDB_CH0_MODE_EN_TO_DI0;
++ }
++
++ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ctrl);
++ return 0;
++}
++
++static void ldb_disable(struct mxc_dispdrv_handle *mddh,
++ struct fb_info *fbi)
++{
++ struct ldb_data *ldb = mxc_dispdrv_getdata(mddh);
++ int ret, chno, other_chno;
++
++ ret = find_ldb_chno(ldb, fbi, &chno);
++ if (ret < 0)
++ return;
++
++ if (ldb->spl_mode || ldb->dual_mode) {
++ ldb->ctrl &= ~(LDB_CH1_MODE_MASK | LDB_CH0_MODE_MASK);
++ other_chno = chno ? 0 : 1;
++ clk_disable_unprepare(ldb->ldb_di_clk[other_chno]);
++ } else {
++ ldb->ctrl &= ~(chno ? LDB_CH1_MODE_MASK :
++ LDB_CH0_MODE_MASK);
++ }
++
++ regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ctrl);
++ return;
++}
++
++static struct mxc_dispdrv_driver ldb_drv = {
++ .name = DRIVER_NAME,
++ .init = ldb_init,
++ .setup = ldb_setup,
++ .enable = ldb_enable,
++ .disable = ldb_disable
++};
++
++enum {
++ LVDS_BIT_MAP_SPWG,
++ LVDS_BIT_MAP_JEIDA,
++};
++
++static const char *ldb_bit_mappings[] = {
++ [LVDS_BIT_MAP_SPWG] = "spwg",
++ [LVDS_BIT_MAP_JEIDA] = "jeida",
++};
++
++static int of_get_data_mapping(struct device_node *np)
++{
++ const char *bm;
++ int ret, i;
++
++ ret = of_property_read_string(np, "fsl,data-mapping", &bm);
++ if (ret < 0)
++ return ret;
++
++ for (i = 0; i < ARRAY_SIZE(ldb_bit_mappings); i++)
++ if (!strcasecmp(bm, ldb_bit_mappings[i]))
++ return i;
++
++ return -EINVAL;
++}
++
++static const char *ldb_crtc_mappings[] = {
++ [CRTC_IPU_DI0] = "ipu-di0",
++ [CRTC_IPU_DI1] = "ipu-di1",
++ [CRTC_IPU1_DI0] = "ipu1-di0",
++ [CRTC_IPU1_DI1] = "ipu1-di1",
++ [CRTC_IPU2_DI0] = "ipu2-di0",
++ [CRTC_IPU2_DI1] = "ipu2-di1",
++ [CRTC_LCDIF] = "lcdif",
++ [CRTC_LCDIF1] = "lcdif1",
++ [CRTC_LCDIF2] = "lcdif2",
++};
++
++static enum crtc of_get_crtc_mapping(struct device_node *np)
++{
++ const char *cm;
++ enum crtc i;
++ int ret;
++
++ ret = of_property_read_string(np, "crtc", &cm);
++ if (ret < 0)
++ return ret;
++
++ for (i = 0; i < ARRAY_SIZE(ldb_crtc_mappings); i++)
++ if (!strcasecmp(cm, ldb_crtc_mappings[i])) {
++ switch (i) {
++ case CRTC_IPU_DI0:
++ i = CRTC_IPU1_DI0;
++ break;
++ case CRTC_IPU_DI1:
++ i = CRTC_IPU1_DI1;
++ break;
++ case CRTC_LCDIF:
++ i = CRTC_LCDIF1;
++ break;
++ default:
++ break;
++ }
++ return i;
++ }
++
++ return -EINVAL;
++}
++
++static int mux_count(struct ldb_data *ldb)
++{
++ int i, j, count = 0;
++ bool should_count[CRTC_MAX];
++ enum crtc crtc;
++
++ for (i = 0; i < CRTC_MAX; i++)
++ should_count[i] = true;
++
++ for (i = 0; i < ldb->bus_mux_num; i++) {
++ for (j = 0; j < ldb->buses[i].crtc_mux_num; j++) {
++ crtc = ldb->buses[i].crtcs[j].crtc;
++ if (should_count[crtc]) {
++ count++;
++ should_count[crtc] = false;
++ }
++ }
++ }
++
++ return count;
++}
++
++static bool is_valid_crtc(struct ldb_data *ldb, enum crtc crtc,
++ int chno)
++{
++ int i = 0;
++
++ if (chno > ldb->bus_mux_num - 1)
++ return false;
++
++ for (; i < ldb->buses[chno].crtc_mux_num; i++)
++ if (ldb->buses[chno].crtcs[i].crtc == crtc)
++ return true;
++
++ return false;
++}
++
++static int ldb_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ const struct of_device_id *of_id =
++ of_match_device(ldb_dt_ids, dev);
++ const struct ldb_info *ldb_info =
++ (const struct ldb_info *)of_id->data;
++ struct device_node *np = dev->of_node, *child;
++ struct ldb_data *ldb;
++ bool ext_ref;
++ int i, data_width, mapping, child_count = 0;
++ char clkname[16];
++
++ ldb = devm_kzalloc(dev, sizeof(*ldb), GFP_KERNEL);
++ if (!ldb)
++ return -ENOMEM;
++
++ ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(ldb->regmap)) {
++ dev_err(dev, "failed to get parent regmap\n");
++ return PTR_ERR(ldb->regmap);
++ }
++
++ ldb->dev = dev;
++ ldb->bus_mux_num = ldb_info->bus_mux_num;
++ ldb->buses = ldb_info->buses;
++ ldb->ctrl_reg = ldb_info->ctrl_reg;
++ ldb->primary_chno = -1;
++
++ ext_ref = of_property_read_bool(np, "ext-ref");
++ if (!ext_ref && ldb_info->ext_bgref_cap)
++ ldb->ctrl |= LDB_BGREF_RMODE_INT;
++
++ ldb->spl_mode = of_property_read_bool(np, "split-mode");
++ if (ldb->spl_mode) {
++ if (ldb_info->split_cap) {
++ ldb->ctrl |= LDB_SPLIT_MODE_EN;
++ dev_info(dev, "split mode\n");
++ } else {
++ dev_err(dev, "cannot support split mode\n");
++ return -EINVAL;
++ }
++ }
++
++ ldb->dual_mode = of_property_read_bool(np, "dual-mode");
++ if (ldb->dual_mode) {
++ if (ldb_info->dual_cap) {
++ dev_info(dev, "dual mode\n");
++ } else {
++ dev_err(dev, "cannot support dual mode\n");
++ return -EINVAL;
++ }
++ }
++
++ if (ldb->dual_mode && ldb->spl_mode) {
++ dev_err(dev, "cannot support dual mode and split mode "
++ "simultaneously\n");
++ return -EINVAL;
++ }
++
++ for (i = 0; i < mux_count(ldb); i++) {
++ sprintf(clkname, "di%d_sel", i);
++ ldb->di_clk[i] = devm_clk_get(dev, clkname);
++ if (IS_ERR(ldb->di_clk[i])) {
++ dev_err(dev, "failed to get clk %s\n", clkname);
++ return PTR_ERR(ldb->di_clk[i]);
++ }
++ }
++
++ for_each_child_of_node(np, child) {
++ struct ldb_chan *chan;
++ enum crtc crtc;
++ bool is_primary;
++ int ret;
++
++ ret = of_property_read_u32(child, "reg", &i);
++ if (ret || i < 0 || i > 1 || i >= ldb->bus_mux_num) {
++ dev_err(dev, "wrong LVDS channel number\n");
++ return -EINVAL;
++ }
++
++ if ((ldb->spl_mode || ldb->dual_mode) && i > 0) {
++ dev_warn(dev, "split mode or dual mode, ignoring "
++ "second output\n");
++ continue;
++ }
++
++ if (!of_device_is_available(child))
++ continue;
++
++ if (++child_count > ldb->bus_mux_num) {
++ dev_err(dev, "too many LVDS channels\n");
++ return -EINVAL;
++ }
++
++ chan = &ldb->chan[i];
++ chan->chno = i;
++ chan->ldb = ldb;
++ chan->online = true;
++
++ is_primary = of_property_read_bool(child, "primary");
++
++ if (ldb->bus_mux_num == 1 || (ldb->primary_chno == -1 &&
++ (is_primary || ldb->spl_mode || ldb->dual_mode)))
++ ldb->primary_chno = chan->chno;
++
++ ret = of_property_read_u32(child, "fsl,data-width",
++ &data_width);
++ if (ret || (data_width != 18 && data_width != 24)) {
++ dev_err(dev, "data width not specified or invalid\n");
++ return -EINVAL;
++ }
++
++ mapping = of_get_data_mapping(child);
++ switch (mapping) {
++ case LVDS_BIT_MAP_SPWG:
++ if (data_width == 24) {
++ if (i == 0 || ldb->spl_mode || ldb->dual_mode)
++ ldb->ctrl |= LDB_DATA_WIDTH_CH0_24;
++ if (i == 1 || ldb->spl_mode || ldb->dual_mode)
++ ldb->ctrl |= LDB_DATA_WIDTH_CH1_24;
++ }
++ break;
++ case LVDS_BIT_MAP_JEIDA:
++ if (data_width == 18) {
++ dev_err(dev, "JEIDA only support 24bit\n");
++ return -EINVAL;
++ }
++ if (i == 0 || ldb->spl_mode || ldb->dual_mode)
++ ldb->ctrl |= LDB_DATA_WIDTH_CH0_24 |
++ LDB_BIT_MAP_CH0_JEIDA;
++ if (i == 1 || ldb->spl_mode || ldb->dual_mode)
++ ldb->ctrl |= LDB_DATA_WIDTH_CH1_24 |
++ LDB_BIT_MAP_CH1_JEIDA;
++ break;
++ default:
++ dev_err(dev, "data mapping not specified or invalid\n");
++ return -EINVAL;
++ }
++
++ crtc = of_get_crtc_mapping(child);
++ if (is_valid_crtc(ldb, crtc, chan->chno)) {
++ ldb->chan[i].crtc = crtc;
++ } else {
++ dev_err(dev, "crtc not specified or invalid\n");
++ return -EINVAL;
++ }
++
++ ret = of_get_videomode(child, &chan->vm, OF_USE_NATIVE_MODE);
++ if (ret)
++ return -EINVAL;
++
++ sprintf(clkname, "ldb_di%d", i);
++ ldb->ldb_di_clk[i] = devm_clk_get(dev, clkname);
++ if (IS_ERR(ldb->ldb_di_clk[i])) {
++ dev_err(dev, "failed to get clk %s\n", clkname);
++ return PTR_ERR(ldb->ldb_di_clk[i]);
++ }
++
++ sprintf(clkname, "ldb_di%d_div_3_5", i);
++ ldb->div_3_5_clk[i] = devm_clk_get(dev, clkname);
++ if (IS_ERR(ldb->div_3_5_clk[i])) {
++ dev_err(dev, "failed to get clk %s\n", clkname);
++ return PTR_ERR(ldb->div_3_5_clk[i]);
++ }
++
++ sprintf(clkname, "ldb_di%d_div_7", i);
++ ldb->div_7_clk[i] = devm_clk_get(dev, clkname);
++ if (IS_ERR(ldb->div_7_clk[i])) {
++ dev_err(dev, "failed to get clk %s\n", clkname);
++ return PTR_ERR(ldb->div_7_clk[i]);
++ }
++
++ sprintf(clkname, "ldb_di%d_div_sel", i);
++ ldb->div_sel_clk[i] = devm_clk_get(dev, clkname);
++ if (IS_ERR(ldb->div_sel_clk[i])) {
++ dev_err(dev, "failed to get clk %s\n", clkname);
++ return PTR_ERR(ldb->div_sel_clk[i]);
++ }
++ }
++
++ if (child_count == 0) {
++ dev_err(dev, "failed to find valid LVDS channel\n");
++ return -EINVAL;
++ }
++
++ if (ldb->primary_chno == -1) {
++ dev_err(dev, "failed to know primary channel\n");
++ return -EINVAL;
++ }
++
++ ldb->mddh = mxc_dispdrv_register(&ldb_drv);
++ mxc_dispdrv_setdata(ldb->mddh, ldb);
++ dev_set_drvdata(&pdev->dev, ldb);
++
++ return 0;
++}
++
++static int ldb_remove(struct platform_device *pdev)
++{
++ struct ldb_data *ldb = dev_get_drvdata(&pdev->dev);
++
++ mxc_dispdrv_puthandle(ldb->mddh);
++ mxc_dispdrv_unregister(ldb->mddh);
++ return 0;
++}
++
++static struct platform_driver ldb_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .of_match_table = ldb_dt_ids,
++ },
++ .probe = ldb_probe,
++ .remove = ldb_remove,
++};
++
++module_platform_driver(ldb_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("LDB driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/Makefile linux-3.14.72/drivers/video/mxc/Makefile
+--- linux-3.14.72.orig/drivers/video/mxc/Makefile 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/Makefile 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,11 @@
++obj-$(CONFIG_FB_MXC_LDB) += ldb.o
++obj-$(CONFIG_FB_MXC_MIPI_DSI) += mipi_dsi.o
++obj-$(CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL) += mxcfb_hx8369_wvga.o
++obj-$(CONFIG_FB_MXC_TVOUT_ADV739X) += mxcfb_adv739x.o
++obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o
++obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o
++obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_dispdrv.o mxc_lcdif.o mxc_ipuv3_fb.o
++obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o
++obj-$(CONFIG_FB_MXS_SII902X) += mxsfb_sii902x.o
++obj-$(CONFIG_FB_MXC_DCIC) += mxc_dcic.o
++obj-$(CONFIG_HANNSTAR_CABC) += hannstar_cabc.o
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mipi_dsi.c linux-3.14.72/drivers/video/mxc/mipi_dsi.c
+--- linux-3.14.72.orig/drivers/video/mxc/mipi_dsi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mipi_dsi.c 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,989 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/ipu.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/mipi_dsi.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/backlight.h>
++#include <linux/of_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/reset.h>
++#include <linux/spinlock.h>
++#include <linux/delay.h>
++#include <video/mipi_display.h>
++
++#include "mipi_dsi.h"
++
++#define DISPDRV_MIPI "mipi_dsi"
++#define ROUND_UP(x) ((x)+1)
++#define NS2PS_RATIO (1000)
++#define NUMBER_OF_CHUNKS (0x8)
++#define NULL_PKT_SIZE (0x8)
++#define PHY_BTA_MAXTIME (0xd00)
++#define PHY_LP2HS_MAXTIME (0x40)
++#define PHY_HS2LP_MAXTIME (0x40)
++#define PHY_STOP_WAIT_TIME (0x20)
++#define DSI_CLKMGR_CFG_CLK_DIV (0x107)
++#define DSI_GEN_PLD_DATA_BUF_ENTRY (0x10)
++#define MIPI_MUX_CTRL(v) (((v) & 0x3) << 4)
++#define MIPI_LCD_SLEEP_MODE_DELAY (120)
++#define MIPI_DSI_REG_RW_TIMEOUT (20)
++#define MIPI_DSI_PHY_TIMEOUT (10)
++
++static struct mipi_dsi_match_lcd mipi_dsi_lcd_db[] = {
++#ifdef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++ {
++ "TRULY-WVGA",
++ {mipid_hx8369_get_lcd_videomode, mipid_hx8369_lcd_setup}
++ },
++#endif
++ {
++ "", {NULL, NULL}
++ }
++};
++
++struct _mipi_dsi_phy_pll_clk {
++ u32 max_phy_clk;
++ u32 config;
++};
++
++/* configure data for DPHY PLL 27M reference clk out */
++static const struct _mipi_dsi_phy_pll_clk mipi_dsi_phy_pll_clk_table[] = {
++ {1000, 0x74}, /* 950-1000MHz */
++ {950, 0x54}, /* 900-950Mhz */
++ {900, 0x34}, /* 850-900Mhz */
++ {850, 0x14}, /* 800-850MHz */
++ {800, 0x32}, /* 750-800MHz */
++ {750, 0x12}, /* 700-750Mhz */
++ {700, 0x30}, /* 650-700Mhz */
++ {650, 0x10}, /* 600-650MHz */
++ {600, 0x2e}, /* 550-600MHz */
++ {550, 0x0e}, /* 500-550Mhz */
++ {500, 0x2c}, /* 450-500Mhz */
++ {450, 0x0c}, /* 400-450MHz */
++ {400, 0x4a}, /* 360-400MHz */
++ {360, 0x2a}, /* 330-360Mhz */
++ {330, 0x48}, /* 300-330Mhz */
++ {300, 0x28}, /* 270-300MHz */
++ {270, 0x08}, /* 250-270MHz */
++ {250, 0x46}, /* 240-250Mhz */
++ {240, 0x26}, /* 210-240Mhz */
++ {210, 0x06}, /* 200-210MHz */
++ {200, 0x44}, /* 180-200MHz */
++ {180, 0x24}, /* 160-180MHz */
++ {160, 0x04}, /* 150-160MHz */
++};
++
++static int valid_mode(int pixel_fmt)
++{
++ return ((pixel_fmt == IPU_PIX_FMT_RGB24) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR24) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB565) ||
++ (pixel_fmt == IPU_PIX_FMT_BGR666) ||
++ (pixel_fmt == IPU_PIX_FMT_RGB332));
++}
++
++static inline void mipi_dsi_read_register(struct mipi_dsi_info *mipi_dsi,
++ u32 reg, u32 *val)
++{
++ *val = ioread32(mipi_dsi->mmio_base + reg);
++ dev_dbg(&mipi_dsi->pdev->dev, "read_reg:0x%02x, val:0x%08x.\n",
++ reg, *val);
++}
++
++static inline void mipi_dsi_write_register(struct mipi_dsi_info *mipi_dsi,
++ u32 reg, u32 val)
++{
++ iowrite32(val, mipi_dsi->mmio_base + reg);
++ dev_dbg(&mipi_dsi->pdev->dev, "\t\twrite_reg:0x%02x, val:0x%08x.\n",
++ reg, val);
++}
++
++int mipi_dsi_pkt_write(struct mipi_dsi_info *mipi_dsi,
++ u8 data_type, const u32 *buf, int len)
++{
++ u32 val;
++ u32 status = 0;
++ int write_len = len;
++ uint32_t timeout = 0;
++
++ if (len) {
++ /* generic long write command */
++ while (len / DSI_GEN_PLD_DATA_BUF_SIZE) {
++ mipi_dsi_write_register(mipi_dsi,
++ MIPI_DSI_GEN_PLD_DATA, *buf);
++ buf++;
++ len -= DSI_GEN_PLD_DATA_BUF_SIZE;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ }
++ }
++ /* write the remainder bytes */
++ if (len > 0) {
++ while ((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi,
++ MIPI_DSI_CMD_PKT_STATUS, &status);
++ }
++ mipi_dsi_write_register(mipi_dsi,
++ MIPI_DSI_GEN_PLD_DATA, *buf);
++ }
++
++ val = data_type | ((write_len & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ } else {
++ /* generic short write command */
++ val = data_type | ((*buf & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ }
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
++ while ((status & DSI_CMD_PKT_STATUS_GEN_CMD_FULL) ==
++ DSI_CMD_PKT_STATUS_GEN_CMD_FULL) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &status);
++ }
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &status);
++ while (!((status & DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ==
++ DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY) ||
++ !((status & DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY) ==
++ DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY)) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &status);
++ }
++
++ return 0;
++}
++
++int mipi_dsi_pkt_read(struct mipi_dsi_info *mipi_dsi,
++ u8 data_type, u32 *buf, int len)
++{
++ u32 val;
++ int read_len = 0;
++ uint32_t timeout = 0;
++
++ if (!len) {
++ mipi_dbg("%s, len = 0 invalid error!\n", __func__);
++ return -EINVAL;
++ }
++
++ val = data_type | ((*buf & DSI_GEN_HDR_DATA_MASK)
++ << DSI_GEN_HDR_DATA_SHIFT);
++ memset(buf, 0, len);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_GEN_HDR, val);
++
++ /* wait for cmd to sent out */
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
++ while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) !=
++ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ }
++ /* wait for entire response stroed in FIFO */
++ while ((val & DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) ==
++ DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_REG_RW_TIMEOUT)
++ return -EIO;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ }
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS, &val);
++ while (!(val & DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY)) {
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_GEN_PLD_DATA, buf);
++ read_len += DSI_GEN_PLD_DATA_BUF_SIZE;
++ buf++;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_PKT_STATUS,
++ &val);
++ if (read_len == (DSI_GEN_PLD_DATA_BUF_ENTRY *
++ DSI_GEN_PLD_DATA_BUF_SIZE))
++ break;
++ }
++
++ if ((len <= read_len) &&
++ ((len + DSI_GEN_PLD_DATA_BUF_SIZE) >= read_len))
++ return 0;
++ else {
++ dev_err(&mipi_dsi->pdev->dev,
++ "actually read_len:%d != len:%d.\n", read_len, len);
++ return -ERANGE;
++ }
++}
++
++int mipi_dsi_dcs_cmd(struct mipi_dsi_info *mipi_dsi,
++ u8 cmd, const u32 *param, int num)
++{
++ int err = 0;
++ u32 buf[DSI_CMD_BUF_MAXSIZE];
++
++ switch (cmd) {
++ case MIPI_DCS_EXIT_SLEEP_MODE:
++ case MIPI_DCS_ENTER_SLEEP_MODE:
++ case MIPI_DCS_SET_DISPLAY_ON:
++ case MIPI_DCS_SET_DISPLAY_OFF:
++ buf[0] = cmd;
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_DCS_SHORT_WRITE, buf, 0);
++ break;
++
++ default:
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command:0x%x Not supported!\n", cmd);
++ break;
++ }
++
++ return err;
++}
++
++static void mipi_dsi_dphy_init(struct mipi_dsi_info *mipi_dsi,
++ u32 cmd, u32 data)
++{
++ u32 val;
++ u32 timeout = 0;
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP, DSI_PWRUP_POWERUP);
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL1,
++ (0x10000 | cmd));
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 2);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL1, (0 | data));
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 2);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TST_CTRL0, 0);
++ val = DSI_PHY_RSTZ_EN_CLK | DSI_PHY_RSTZ_DISABLE_RST |
++ DSI_PHY_RSTZ_DISABLE_SHUTDOWN;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ while ((val & DSI_PHY_STATUS_LOCK) != DSI_PHY_STATUS_LOCK) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "Error: phy lock timeout!\n");
++ break;
++ }
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ }
++ timeout = 0;
++ while ((val & DSI_PHY_STATUS_STOPSTATE_CLK_LANE) !=
++ DSI_PHY_STATUS_STOPSTATE_CLK_LANE) {
++ msleep(1);
++ timeout++;
++ if (timeout == MIPI_DSI_PHY_TIMEOUT) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "Error: phy lock lane timeout!\n");
++ break;
++ }
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_PHY_STATUS, &val);
++ }
++}
++
++static void mipi_dsi_enable_controller(struct mipi_dsi_info *mipi_dsi,
++ bool init)
++{
++ u32 val;
++ u32 lane_byte_clk_period;
++ struct fb_videomode *mode = mipi_dsi->mode;
++ struct mipi_lcd_config *lcd_config = mipi_dsi->lcd_config;
++
++ if (init) {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ,
++ DSI_PHY_RSTZ_RST);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CLKMGR_CFG,
++ DSI_CLKMGR_CFG_CLK_DIV);
++
++ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
++ val = DSI_DPI_CFG_VSYNC_ACT_LOW;
++ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
++ val |= DSI_DPI_CFG_HSYNC_ACT_LOW;
++ if ((mode->sync & FB_SYNC_OE_LOW_ACT))
++ val |= DSI_DPI_CFG_DATAEN_ACT_LOW;
++ if (MIPI_RGB666_LOOSELY == lcd_config->dpi_fmt)
++ val |= DSI_DPI_CFG_EN18LOOSELY;
++ val |= (lcd_config->dpi_fmt & DSI_DPI_CFG_COLORCODE_MASK)
++ << DSI_DPI_CFG_COLORCODE_SHIFT;
++ val |= (lcd_config->virtual_ch & DSI_DPI_CFG_VID_MASK)
++ << DSI_DPI_CFG_VID_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_DPI_CFG, val);
++
++ val = DSI_PCKHDL_CFG_EN_BTA |
++ DSI_PCKHDL_CFG_EN_ECC_RX |
++ DSI_PCKHDL_CFG_EN_CRC_RX;
++
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PCKHDL_CFG, val);
++
++ val = (mode->xres & DSI_VID_PKT_CFG_VID_PKT_SZ_MASK)
++ << DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT;
++ val |= (NUMBER_OF_CHUNKS & DSI_VID_PKT_CFG_NUM_CHUNKS_MASK)
++ << DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT;
++ val |= (NULL_PKT_SIZE & DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK)
++ << DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_PKT_CFG, val);
++
++ /* enable LP mode when TX DCS cmd and enable DSI command mode */
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG,
++ MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER);
++
++ /* mipi lane byte clk period in ns unit */
++ lane_byte_clk_period = NS2PS_RATIO /
++ (lcd_config->max_phy_clk / BITS_PER_BYTE);
++ val = ROUND_UP(mode->hsync_len * mode->pixclock /
++ NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HSA_TIME_SHIFT;
++ val |= ROUND_UP(mode->left_margin * mode->pixclock /
++ NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HBP_TIME_SHIFT;
++ val |= ROUND_UP((mode->left_margin + mode->right_margin +
++ mode->hsync_len + mode->xres) * mode->pixclock
++ / NS2PS_RATIO / lane_byte_clk_period)
++ << DSI_TME_LINE_CFG_HLINE_TIME_SHIFT;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_TMR_LINE_CFG, val);
++
++ val = ((mode->vsync_len & DSI_VTIMING_CFG_VSA_LINES_MASK)
++ << DSI_VTIMING_CFG_VSA_LINES_SHIFT);
++ val |= ((mode->upper_margin & DSI_VTIMING_CFG_VBP_LINES_MASK)
++ << DSI_VTIMING_CFG_VBP_LINES_SHIFT);
++ val |= ((mode->lower_margin & DSI_VTIMING_CFG_VFP_LINES_MASK)
++ << DSI_VTIMING_CFG_VFP_LINES_SHIFT);
++ val |= ((mode->yres & DSI_VTIMING_CFG_V_ACT_LINES_MASK)
++ << DSI_VTIMING_CFG_V_ACT_LINES_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VTIMING_CFG, val);
++
++ val = ((PHY_BTA_MAXTIME & DSI_PHY_TMR_CFG_BTA_TIME_MASK)
++ << DSI_PHY_TMR_CFG_BTA_TIME_SHIFT);
++ val |= ((PHY_LP2HS_MAXTIME & DSI_PHY_TMR_CFG_LP2HS_TIME_MASK)
++ << DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT);
++ val |= ((PHY_HS2LP_MAXTIME & DSI_PHY_TMR_CFG_HS2LP_TIME_MASK)
++ << DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_TMR_CFG, val);
++
++ val = (((lcd_config->data_lane_num - 1) &
++ DSI_PHY_IF_CFG_N_LANES_MASK)
++ << DSI_PHY_IF_CFG_N_LANES_SHIFT);
++ val |= ((PHY_STOP_WAIT_TIME & DSI_PHY_IF_CFG_WAIT_TIME_MASK)
++ << DSI_PHY_IF_CFG_WAIT_TIME_SHIFT);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CFG, val);
++
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST0, &val);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST1, &val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_ERROR_MSK0, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_ERROR_MSK1, 0);
++
++ mipi_dsi_dphy_init(mipi_dsi, DSI_PHY_CLK_INIT_COMMAND,
++ mipi_dsi->dphy_pll_config);
++ } else {
++ mipi_dsi_dphy_init(mipi_dsi, DSI_PHY_CLK_INIT_COMMAND,
++ mipi_dsi->dphy_pll_config);
++ }
++}
++
++static void mipi_dsi_disable_controller(struct mipi_dsi_info *mipi_dsi)
++{
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP, DSI_PWRUP_RESET);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_RSTZ, DSI_PHY_RSTZ_RST);
++}
++
++static irqreturn_t mipi_dsi_irq_handler(int irq, void *data)
++{
++ u32 mask0;
++ u32 mask1;
++ u32 status0;
++ u32 status1;
++ struct mipi_dsi_info *mipi_dsi;
++
++ mipi_dsi = (struct mipi_dsi_info *)data;
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST0, &status0);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_ST1, &status1);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_MSK0, &mask0);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_ERROR_MSK1, &mask1);
++
++ if ((status0 & (~mask0)) || (status1 & (~mask1))) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "mipi_dsi IRQ status0:0x%x, status1:0x%x!\n",
++ status0, status1);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static inline void mipi_dsi_set_mode(struct mipi_dsi_info *mipi_dsi,
++ bool cmd_mode)
++{
++ u32 val;
++
++ if (cmd_mode) {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, &val);
++ val |= MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_MODE_CFG, 0);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_POWERUP);
++ } else {
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_RESET);
++ /* Disable Command mode when tranfering video data */
++ mipi_dsi_read_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, &val);
++ val &= ~MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_CMD_MODE_CFG, val);
++ val = DSI_VID_MODE_CFG_EN | DSI_VID_MODE_CFG_EN_BURSTMODE |
++ DSI_VID_MODE_CFG_EN_LP_MODE;
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_VID_MODE_CFG, val);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PWR_UP,
++ DSI_PWRUP_POWERUP);
++ mipi_dsi_write_register(mipi_dsi, MIPI_DSI_PHY_IF_CTRL,
++ DSI_PHY_IF_CTRL_TX_REQ_CLK_HS);
++ }
++}
++
++static int mipi_dsi_power_on(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (!mipi_dsi->dsi_power_on) {
++ clk_prepare_enable(mipi_dsi->dphy_clk);
++ clk_prepare_enable(mipi_dsi->cfg_clk);
++ mipi_dsi_enable_controller(mipi_dsi, false);
++ mipi_dsi_set_mode(mipi_dsi, false);
++ /* host send pclk/hsync/vsync for two frames before sleep-out */
++ msleep((1000/mipi_dsi->mode->refresh + 1) << 1);
++ mipi_dsi_set_mode(mipi_dsi, true);
++ err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_EXIT_SLEEP_MODE,
++ NULL, 0);
++ if (err) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command sleep-in error!\n");
++ }
++ msleep(MIPI_LCD_SLEEP_MODE_DELAY);
++ mipi_dsi_set_mode(mipi_dsi, false);
++ mipi_dsi->dsi_power_on = 1;
++ }
++
++ return 0;
++}
++
++void mipi_dsi_power_off(struct mxc_dispdrv_handle *disp)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (mipi_dsi->dsi_power_on) {
++ mipi_dsi_set_mode(mipi_dsi, true);
++ err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_ENTER_SLEEP_MODE,
++ NULL, 0);
++ if (err) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "MIPI DSI DCS Command display on error!\n");
++ }
++ /* To allow time for the supply voltages
++ * and clock circuits to stabilize.
++ */
++ msleep(5);
++ /* video stream timing on */
++ mipi_dsi_set_mode(mipi_dsi, false);
++ msleep(MIPI_LCD_SLEEP_MODE_DELAY);
++
++ mipi_dsi_set_mode(mipi_dsi, true);
++ mipi_dsi_disable_controller(mipi_dsi);
++ mipi_dsi->dsi_power_on = 0;
++ clk_disable_unprepare(mipi_dsi->dphy_clk);
++ clk_disable_unprepare(mipi_dsi->cfg_clk);
++ }
++}
++
++static int mipi_dsi_lcd_init(struct mipi_dsi_info *mipi_dsi,
++ struct mxc_dispdrv_setting *setting)
++{
++ int err;
++ int size;
++ int i;
++ struct fb_videomode *mipi_lcd_modedb;
++ struct fb_videomode mode;
++ struct device *dev = &mipi_dsi->pdev->dev;
++
++ for (i = 0; i < ARRAY_SIZE(mipi_dsi_lcd_db); i++) {
++ if (!strcmp(mipi_dsi->lcd_panel,
++ mipi_dsi_lcd_db[i].lcd_panel)) {
++ mipi_dsi->lcd_callback =
++ &mipi_dsi_lcd_db[i].lcd_callback;
++ break;
++ }
++ }
++ if (i == ARRAY_SIZE(mipi_dsi_lcd_db)) {
++ dev_err(dev, "failed to find supported lcd panel.\n");
++ return -EINVAL;
++ }
++ /* get the videomode in the order: cmdline->platform data->driver */
++ mipi_dsi->lcd_callback->get_mipi_lcd_videomode(&mipi_lcd_modedb, &size,
++ &mipi_dsi->lcd_config);
++ err = fb_find_mode(&setting->fbi->var, setting->fbi,
++ setting->dft_mode_str,
++ mipi_lcd_modedb, size, NULL,
++ setting->default_bpp);
++ if (err != 1)
++ fb_videomode_to_var(&setting->fbi->var, mipi_lcd_modedb);
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < size; i++) {
++ fb_var_to_videomode(&mode, &setting->fbi->var);
++ if (fb_mode_is_equal(&mode, mipi_lcd_modedb + i)) {
++ err = fb_add_videomode(mipi_lcd_modedb + i,
++ &setting->fbi->modelist);
++ /* Note: only support fb mode from driver */
++ mipi_dsi->mode = mipi_lcd_modedb + i;
++ break;
++ }
++ }
++ if ((err < 0) || (size == i)) {
++ dev_err(dev, "failed to add videomode.\n");
++ return err;
++ }
++
++ for (i = 0; i < ARRAY_SIZE(mipi_dsi_phy_pll_clk_table); i++) {
++ if (mipi_dsi_phy_pll_clk_table[i].max_phy_clk <
++ mipi_dsi->lcd_config->max_phy_clk)
++ break;
++ }
++ if ((i == ARRAY_SIZE(mipi_dsi_phy_pll_clk_table)) ||
++ (mipi_dsi->lcd_config->max_phy_clk >
++ mipi_dsi_phy_pll_clk_table[0].max_phy_clk)) {
++ dev_err(dev, "failed to find data in"
++ "mipi_dsi_phy_pll_clk_table.\n");
++ return -EINVAL;
++ }
++ mipi_dsi->dphy_pll_config = mipi_dsi_phy_pll_clk_table[--i].config;
++ dev_dbg(dev, "dphy_pll_config:0x%x.\n", mipi_dsi->dphy_pll_config);
++
++ return 0;
++}
++
++static int mipi_dsi_enable(struct mxc_dispdrv_handle *disp,
++ struct fb_info *fbi)
++{
++ int err;
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ if (!mipi_dsi->lcd_inited) {
++ err = clk_prepare_enable(mipi_dsi->dphy_clk);
++ err |= clk_prepare_enable(mipi_dsi->cfg_clk);
++ if (err)
++ dev_err(&mipi_dsi->pdev->dev,
++ "clk enable error:%d!\n", err);
++ mipi_dsi_enable_controller(mipi_dsi, true);
++ err = mipi_dsi->lcd_callback->mipi_lcd_setup(
++ mipi_dsi);
++ if (err < 0) {
++ dev_err(&mipi_dsi->pdev->dev,
++ "failed to init mipi lcd.");
++ clk_disable_unprepare(mipi_dsi->dphy_clk);
++ clk_disable_unprepare(mipi_dsi->cfg_clk);
++ return err;
++ }
++ mipi_dsi_set_mode(mipi_dsi, false);
++ mipi_dsi->dsi_power_on = 1;
++ mipi_dsi->lcd_inited = 1;
++ }
++ mipi_dsi_power_on(mipi_dsi->disp_mipi);
++
++ return 0;
++}
++
++static void mipi_dsi_disable(struct mxc_dispdrv_handle *disp,
++ struct fb_info *fbi)
++{
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ mipi_dsi_power_off(mipi_dsi->disp_mipi);
++}
++
++static int mipi_dsi_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++ struct device *dev = &mipi_dsi->pdev->dev;
++ int ret = 0;
++
++ if (!valid_mode(setting->if_fmt)) {
++ dev_warn(dev, "Input pixel format not valid"
++ "use default RGB24\n");
++ setting->if_fmt = IPU_PIX_FMT_RGB24;
++ }
++
++ ret = ipu_di_to_crtc(dev, mipi_dsi->dev_id,
++ mipi_dsi->disp_id, &setting->crtc);
++ if (ret < 0)
++ return ret;
++
++ ret = mipi_dsi_lcd_init(mipi_dsi, setting);
++ if (ret) {
++ dev_err(dev, "failed to init mipi dsi lcd\n");
++ return ret;
++ }
++
++ dev_dbg(dev, "MIPI DSI dispdrv inited!\n");
++ return ret;
++}
++
++static void mipi_dsi_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct mipi_dsi_info *mipi_dsi;
++
++ mipi_dsi = mxc_dispdrv_getdata(disp);
++
++ mipi_dsi_power_off(mipi_dsi->disp_mipi);
++ if (mipi_dsi->bl)
++ backlight_device_unregister(mipi_dsi->bl);
++}
++
++static int mipi_dsi_setup(struct mxc_dispdrv_handle *disp,
++ struct fb_info *fbi)
++{
++ struct mipi_dsi_info *mipi_dsi = mxc_dispdrv_getdata(disp);
++ int xres_virtual = fbi->var.xres_virtual;
++ int yres_virtual = fbi->var.yres_virtual;
++ int xoffset = fbi->var.xoffset;
++ int yoffset = fbi->var.yoffset;
++ int pixclock = fbi->var.pixclock;
++
++ if (!mipi_dsi->mode)
++ return 0;
++
++ /* set the mode back to var in case userspace changes it */
++ fb_videomode_to_var(&fbi->var, mipi_dsi->mode);
++
++ /* restore some var entries cached */
++ fbi->var.xres_virtual = xres_virtual;
++ fbi->var.yres_virtual = yres_virtual;
++ fbi->var.xoffset = xoffset;
++ fbi->var.yoffset = yoffset;
++ fbi->var.pixclock = pixclock;
++ return 0;
++}
++
++static struct mxc_dispdrv_driver mipi_dsi_drv = {
++ .name = DISPDRV_MIPI,
++ .init = mipi_dsi_disp_init,
++ .deinit = mipi_dsi_disp_deinit,
++ .enable = mipi_dsi_enable,
++ .disable = mipi_dsi_disable,
++ .setup = mipi_dsi_setup,
++};
++
++static int imx6q_mipi_dsi_get_mux(int dev_id, int disp_id)
++{
++ if (dev_id > 1 || disp_id > 1)
++ return -EINVAL;
++
++ return (dev_id << 5) | (disp_id << 4);
++}
++
++static struct mipi_dsi_bus_mux imx6q_mipi_dsi_mux[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .mask = IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
++ .get_mux = imx6q_mipi_dsi_get_mux,
++ },
++};
++
++static int imx6dl_mipi_dsi_get_mux(int dev_id, int disp_id)
++{
++ if (dev_id > 1 || disp_id > 1)
++ return -EINVAL;
++
++ /* MIPI DSI source is LCDIF */
++ if (dev_id)
++ disp_id = 0;
++
++ return (dev_id << 5) | (disp_id << 4);
++}
++
++static struct mipi_dsi_bus_mux imx6dl_mipi_dsi_mux[] = {
++ {
++ .reg = IOMUXC_GPR3,
++ .mask = IMX6Q_GPR3_MIPI_MUX_CTL_MASK,
++ .get_mux = imx6dl_mipi_dsi_get_mux,
++ },
++};
++
++static const struct of_device_id imx_mipi_dsi_dt_ids[] = {
++ { .compatible = "fsl,imx6q-mipi-dsi", .data = imx6q_mipi_dsi_mux, },
++ { .compatible = "fsl,imx6dl-mipi-dsi", .data = imx6dl_mipi_dsi_mux, },
++ { }
++};
++MODULE_DEVICE_TABLE(of, imx_mipi_dsi_dt_ids);
++
++/**
++ * This function is called by the driver framework to initialize the MIPI DSI
++ * device.
++ *
++ * @param pdev The device structure for the MIPI DSI passed in by the
++ * driver framework.
++ *
++ * @return Returns 0 on success or negative error code on error
++ */
++static int mipi_dsi_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *of_id =
++ of_match_device(of_match_ptr(imx_mipi_dsi_dt_ids),
++ &pdev->dev);
++ struct mipi_dsi_info *mipi_dsi;
++ struct resource *res;
++ u32 dev_id, disp_id;
++ const char *lcd_panel;
++ unsigned int mux;
++ int ret = 0;
++
++ mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
++ if (!mipi_dsi)
++ return -ENOMEM;
++
++ ret = of_property_read_string(np, "lcd_panel", &lcd_panel);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property lcd_panel\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "dev_id", &dev_id);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property dev_id\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "disp_id", &disp_id);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to read of property disp_id\n");
++ return ret;
++ }
++ mipi_dsi->dev_id = dev_id;
++ mipi_dsi->disp_id = disp_id;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "failed to get platform resource 0\n");
++ return -ENODEV;
++ }
++
++ if (!devm_request_mem_region(&pdev->dev, res->start,
++ resource_size(res), pdev->name))
++ return -EBUSY;
++
++ mipi_dsi->mmio_base = devm_ioremap(&pdev->dev, res->start,
++ resource_size(res));
++ if (!mipi_dsi->mmio_base)
++ return -EBUSY;
++
++ mipi_dsi->irq = platform_get_irq(pdev, 0);
++ if (mipi_dsi->irq < 0) {
++ dev_err(&pdev->dev, "failed get device irq\n");
++ return -ENODEV;
++ }
++
++ ret = devm_request_irq(&pdev->dev, mipi_dsi->irq,
++ mipi_dsi_irq_handler,
++ 0, "mipi_dsi", mipi_dsi);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to request irq\n");
++ return ret;
++ }
++
++ mipi_dsi->dphy_clk = devm_clk_get(&pdev->dev, "mipi_pllref_clk");
++ if (IS_ERR(mipi_dsi->dphy_clk)) {
++ dev_err(&pdev->dev, "failed to get dphy pll_ref_clk\n");
++ return PTR_ERR(mipi_dsi->dphy_clk);
++ }
++
++ mipi_dsi->cfg_clk = devm_clk_get(&pdev->dev, "mipi_cfg_clk");
++ if (IS_ERR(mipi_dsi->cfg_clk)) {
++ dev_err(&pdev->dev, "failed to get cfg_clk\n");
++ return PTR_ERR(mipi_dsi->cfg_clk);
++ }
++
++ mipi_dsi->disp_power_on = devm_regulator_get(&pdev->dev,
++ "disp-power-on");
++ if (!IS_ERR(mipi_dsi->disp_power_on)) {
++ ret = regulator_enable(mipi_dsi->disp_power_on);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to enable display "
++ "power regulator, err=%d\n", ret);
++ return ret;
++ }
++ } else {
++ mipi_dsi->disp_power_on = NULL;
++ }
++
++ ret = device_reset(&pdev->dev);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to reset: %d\n", ret);
++ goto dev_reset_fail;
++ }
++
++ if (of_id)
++ mipi_dsi->bus_mux = of_id->data;
++
++ mipi_dsi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(mipi_dsi->regmap)) {
++ dev_err(&pdev->dev, "failed to get parent regmap\n");
++ ret = PTR_ERR(mipi_dsi->regmap);
++ goto get_parent_regmap_fail;
++ }
++
++ mux = mipi_dsi->bus_mux->get_mux(dev_id, disp_id);
++ if (mux >= 0)
++ regmap_update_bits(mipi_dsi->regmap, mipi_dsi->bus_mux->reg,
++ mipi_dsi->bus_mux->mask, mux);
++ else
++ dev_warn(&pdev->dev, "invalid dev_id or disp_id muxing\n");
++
++ mipi_dsi->lcd_panel = kstrdup(lcd_panel, GFP_KERNEL);
++ if (!mipi_dsi->lcd_panel) {
++ dev_err(&pdev->dev, "failed to allocate lcd panel name\n");
++ ret = -ENOMEM;
++ goto kstrdup_fail;
++ }
++
++ mipi_dsi->pdev = pdev;
++ mipi_dsi->disp_mipi = mxc_dispdrv_register(&mipi_dsi_drv);
++ if (IS_ERR(mipi_dsi->disp_mipi)) {
++ dev_err(&pdev->dev, "mxc_dispdrv_register error\n");
++ ret = PTR_ERR(mipi_dsi->disp_mipi);
++ goto dispdrv_reg_fail;
++ }
++
++ mxc_dispdrv_setdata(mipi_dsi->disp_mipi, mipi_dsi);
++ dev_set_drvdata(&pdev->dev, mipi_dsi);
++
++ dev_info(&pdev->dev, "i.MX MIPI DSI driver probed\n");
++ return ret;
++
++dispdrv_reg_fail:
++ kfree(mipi_dsi->lcd_panel);
++kstrdup_fail:
++get_parent_regmap_fail:
++dev_reset_fail:
++ if (mipi_dsi->disp_power_on)
++ regulator_disable(mipi_dsi->disp_power_on);
++ return ret;
++}
++
++static void mipi_dsi_shutdown(struct platform_device *pdev)
++{
++ struct mipi_dsi_info *mipi_dsi = dev_get_drvdata(&pdev->dev);
++
++ mipi_dsi_power_off(mipi_dsi->disp_mipi);
++}
++
++static int mipi_dsi_remove(struct platform_device *pdev)
++{
++ struct mipi_dsi_info *mipi_dsi = dev_get_drvdata(&pdev->dev);
++
++ mxc_dispdrv_puthandle(mipi_dsi->disp_mipi);
++ mxc_dispdrv_unregister(mipi_dsi->disp_mipi);
++
++ if (mipi_dsi->disp_power_on)
++ regulator_disable(mipi_dsi->disp_power_on);
++
++ kfree(mipi_dsi->lcd_panel);
++ dev_set_drvdata(&pdev->dev, NULL);
++
++ return 0;
++}
++
++static struct platform_driver mipi_dsi_driver = {
++ .driver = {
++ .of_match_table = imx_mipi_dsi_dt_ids,
++ .name = "mxc_mipi_dsi",
++ },
++ .probe = mipi_dsi_probe,
++ .remove = mipi_dsi_remove,
++ .shutdown = mipi_dsi_shutdown,
++};
++
++static int __init mipi_dsi_init(void)
++{
++ int err;
++
++ err = platform_driver_register(&mipi_dsi_driver);
++ if (err) {
++ pr_err("mipi_dsi_driver register failed\n");
++ return -ENODEV;
++ }
++ pr_info("MIPI DSI driver module loaded\n");
++ return 0;
++}
++
++static void __exit mipi_dsi_cleanup(void)
++{
++ platform_driver_unregister(&mipi_dsi_driver);
++}
++
++module_init(mipi_dsi_init);
++module_exit(mipi_dsi_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX MIPI DSI driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mipi_dsi.h linux-3.14.72/drivers/video/mxc/mipi_dsi.h
+--- linux-3.14.72.orig/drivers/video/mxc/mipi_dsi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mipi_dsi.h 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,113 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MIPI_DSI_H__
++#define __MIPI_DSI_H__
++
++#include <linux/regmap.h>
++#include "mxc_dispdrv.h"
++
++#ifdef DEBUG
++#define mipi_dbg(fmt, ...) printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
++#else
++#define mipi_dbg(fmt, ...)
++#endif
++
++#define DSI_CMD_BUF_MAXSIZE (32)
++
++/* DPI interface pixel color coding map */
++enum mipi_dsi_dpi_fmt {
++ MIPI_RGB565_PACKED = 0,
++ MIPI_RGB565_LOOSELY,
++ MIPI_RGB565_CONFIG3,
++ MIPI_RGB666_PACKED,
++ MIPI_RGB666_LOOSELY,
++ MIPI_RGB888,
++};
++
++struct mipi_lcd_config {
++ u32 virtual_ch;
++ u32 data_lane_num;
++ /* device max DPHY clock in MHz unit */
++ u32 max_phy_clk;
++ enum mipi_dsi_dpi_fmt dpi_fmt;
++};
++
++struct mipi_dsi_info;
++struct mipi_dsi_lcd_callback {
++ /* callback for lcd panel operation */
++ void (*get_mipi_lcd_videomode)(struct fb_videomode **, int *,
++ struct mipi_lcd_config **);
++ int (*mipi_lcd_setup)(struct mipi_dsi_info *);
++
++};
++
++struct mipi_dsi_match_lcd {
++ char *lcd_panel;
++ struct mipi_dsi_lcd_callback lcd_callback;
++};
++
++struct mipi_dsi_bus_mux {
++ int reg;
++ int mask;
++ int (*get_mux) (int dev_id, int disp_id);
++};
++
++/* driver private data */
++struct mipi_dsi_info {
++ struct platform_device *pdev;
++ void __iomem *mmio_base;
++ struct regmap *regmap;
++ const struct mipi_dsi_bus_mux *bus_mux;
++ int dsi_power_on;
++ int lcd_inited;
++ u32 dphy_pll_config;
++ int dev_id;
++ int disp_id;
++ char *lcd_panel;
++ int irq;
++ struct clk *dphy_clk;
++ struct clk *cfg_clk;
++ struct mxc_dispdrv_handle *disp_mipi;
++ struct fb_videomode *mode;
++ struct regulator *disp_power_on;
++ struct mipi_lcd_config *lcd_config;
++ /* board related power control */
++ struct backlight_device *bl;
++ /* callback for lcd panel operation */
++ struct mipi_dsi_lcd_callback *lcd_callback;
++};
++
++int mipi_dsi_pkt_write(struct mipi_dsi_info *mipi,
++ u8 data_type, const u32 *buf, int len);
++int mipi_dsi_pkt_read(struct mipi_dsi_info *mipi,
++ u8 data_type, u32 *buf, int len);
++int mipi_dsi_dcs_cmd(struct mipi_dsi_info *mipi,
++ u8 cmd, const u32 *param, int num);
++
++#ifdef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size,
++ struct mipi_lcd_config **data);
++int mipid_hx8369_lcd_setup(struct mipi_dsi_info *);
++#endif
++
++#ifndef CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL
++#error "Please configure MIPI LCD panel, we cannot find one!"
++#endif
++
++#endif
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_dcic.c linux-3.14.72/drivers/video/mxc/mxc_dcic.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_dcic.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_dcic.c 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,663 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++#include <linux/clk.h>
++#include <linux/cdev.h>
++#include <linux/delay.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/ioctl.h>
++#include <linux/interrupt.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/module.h>
++#include <linux/mxc_dcic.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/types.h>
++#include <linux/uaccess.h>
++#include <video/videomode.h>
++#include <video/of_videomode.h>
++
++#define DRIVER_NAME "mxc_dcic"
++
++#define DCIC_IPU1_DI0 "dcic-ipu1-di0"
++#define DCIC_IPU1_DI1 "dcic-ipu1-di1"
++#define DCIC_IPU2_DI0 "dcic-ipu2-di0"
++#define DCIC_IPU2_DI1 "dcic-ipu2-di1"
++#define DCIC_LCDIF "dcic-lcdif"
++#define DCIC_LCDIF1 "dcic-lcdif1"
++#define DCIC_LCDIF2 "dcic-lcdif2"
++#define DCIC_LVDS "dcic-lvds"
++#define DCIC_LVDS0 "dcic-lvds0"
++#define DCIC_LVDS1 "dcic-lvds1"
++#define DCIC_HDMI "dcic-hdmi"
++
++#define DCIC0_DEV_NAME "mxc_dcic0"
++#define DCIC1_DEV_NAME "mxc_dcic1"
++
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
++
++static wait_queue_head_t mxc_dcic_wait;
++static int mxc_dcic_vsync;
++static int mxc_dcic_irq;
++static unsigned long mxc_dcic_counter;
++
++static const struct dcic_mux imx6q_dcic0_mux[] = {
++ {
++ .dcic = DCIC_IPU1_DI0,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0,
++ }, {
++ .dcic = DCIC_LVDS0,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0,
++ }, {
++ .dcic = DCIC_LVDS1,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1,
++ }, {
++ .dcic = DCIC_HDMI,
++ .val = IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI,
++ }
++};
++
++static const struct dcic_mux imx6q_dcic1_mux[] = {
++ {
++ .dcic = DCIC_IPU1_DI1,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1,
++ }, {
++ .dcic = DCIC_LVDS0,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0,
++ }, {
++ .dcic = DCIC_LVDS1,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1,
++ }, {
++ .dcic = DCIC_HDMI,
++ .val = IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI,
++ }
++};
++
++static const struct bus_mux imx6q_dcic_buses[] = {
++ {
++ .name = DCIC0_DEV_NAME,
++ .reg = IOMUXC_GPR10,
++ .shift = 0,
++ .mask = IMX6Q_GPR10_DCIC1_MUX_CTL_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6q_dcic0_mux),
++ .dcics = imx6q_dcic0_mux,
++ }, {
++ .name = DCIC1_DEV_NAME,
++ .reg = IOMUXC_GPR10,
++ .shift = 2,
++ .mask = IMX6Q_GPR10_DCIC2_MUX_CTL_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6q_dcic1_mux),
++ .dcics = imx6q_dcic1_mux,
++ }
++};
++
++static const struct dcic_info imx6q_dcic_info = {
++ .bus_mux_num = ARRAY_SIZE(imx6q_dcic_buses),
++ .buses = imx6q_dcic_buses,
++};
++
++static const struct dcic_mux imx6sx_dcic0_mux[] = {
++ {
++ .dcic = DCIC_LCDIF1,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1,
++ }, {
++ .dcic = DCIC_LVDS,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS,
++ }
++};
++
++static const struct dcic_mux imx6sx_dcic1_mux[] = {
++ {
++ .dcic = DCIC_LCDIF2,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2,
++ }, {
++ .dcic = DCIC_LVDS,
++ .val = IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS,
++ }
++};
++
++static const struct bus_mux imx6sx_dcic_buses[] = {
++ {
++ .name = DCIC0_DEV_NAME,
++ .reg = IOMUXC_GPR5,
++ .shift = 1,
++ .mask = IMX6SX_GPR5_DISP_MUX_DCIC1_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6sx_dcic0_mux),
++ .dcics = imx6sx_dcic0_mux,
++ }, {
++ .name = DCIC1_DEV_NAME,
++ .reg = IOMUXC_GPR5,
++ .shift = 2,
++ .mask = IMX6SX_GPR5_DISP_MUX_DCIC2_MASK,
++ .dcic_mux_num = ARRAY_SIZE(imx6sx_dcic1_mux),
++ .dcics = imx6sx_dcic1_mux,
++ }
++};
++
++static const struct dcic_info imx6sx_dcic_info = {
++ .bus_mux_num = ARRAY_SIZE(imx6sx_dcic_buses),
++ .buses = imx6sx_dcic_buses,
++};
++
++static const struct of_device_id dcic_dt_ids[] = {
++ { .compatible = "fsl,imx6q-dcic", .data = &imx6q_dcic_info, },
++ { .compatible = "fsl,imx6sx-dcic", .data = &imx6sx_dcic_info, },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, dcic_dt_ids);
++
++static int of_get_dcic_val(struct device_node *np, struct dcic_data *dcic)
++{
++ const char *mux;
++ int ret;
++ u32 i, dcic_id;
++
++ ret = of_property_read_string(np, "dcic_mux", &mux);
++ if (ret < 0) {
++ dev_err(dcic->dev, "Can not get dcic_mux\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "dcic_id", &dcic_id);
++ if (ret < 0) {
++ dev_err(dcic->dev, "Can not get dcic_id\n");
++ return ret;
++ }
++
++ dcic->bus_n = dcic_id;
++
++ for (i = 0; i < dcic->buses[dcic_id].dcic_mux_num; i++)
++ if (!strcmp(mux, dcic->buses[dcic_id].dcics[i].dcic)) {
++ dcic->mux_n = i;
++ return dcic->buses[dcic_id].dcics[i].val;
++ }
++
++ return -EINVAL;
++}
++
++static void dcic_enable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ val = readl(&dcic->regs->dcicc);
++ val |= DCICC_IC_ENABLE;
++ writel(val, &dcic->regs->dcicc);
++}
++
++void dcic_disable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ val = readl(&dcic->regs->dcicc);
++ val &= ~DCICC_IC_MASK;
++ val |= DCICC_IC_DISABLE;
++ writel(val, &dcic->regs->dcicc);
++}
++
++static void roi_enable(struct dcic_data *dcic, struct roi_params *roi_param)
++{
++ u32 val;
++ u32 roi_n = roi_param->roi_n;
++
++ val = readl(&dcic->regs->ROI[roi_n].dcicrc);
++ val |= DCICRC_ROI_ENABLE;
++ if (roi_param->freeze)
++ val |= DCICRC_ROI_FROZEN;
++ writel(val, &dcic->regs->ROI[roi_n].dcicrc);
++}
++
++static void roi_disable(struct dcic_data *dcic, u32 roi_n)
++{
++ u32 val;
++
++ val = readl(&dcic->regs->ROI[roi_n].dcicrc);
++ val &= ~DCICRC_ROI_ENABLE;
++ writel(val, &dcic->regs->ROI[roi_n].dcicrc);
++}
++
++static bool roi_configure(struct dcic_data *dcic, struct roi_params *roi_param)
++{
++ struct roi_regs *roi_reg;
++ u32 val;
++
++ if (roi_param->roi_n < 0 || roi_param->roi_n >= 16) {
++ pr_err("Error, Wrong ROI number %d\n", roi_param->roi_n);
++ return false;
++ }
++
++ if (roi_param->end_x <= roi_param->start_x ||
++ roi_param->end_y <= roi_param->start_y) {
++ pr_err("Error, Wrong ROI\n");
++ return false;
++ }
++
++ roi_reg = (struct roi_regs *) &dcic->regs->ROI[roi_param->roi_n];
++
++ /* init roi block size */
++ val = roi_param->start_y << 16 | roi_param->start_x;
++ writel(val, &roi_reg->dcicrc);
++
++ val = roi_param->end_y << 16 | roi_param->end_x;
++ writel(val, &roi_reg->dcicrs);
++
++ writel(roi_param->ref_sig, &roi_reg->dcicrrs);
++
++ roi_enable(dcic, roi_param);
++ return true;
++}
++
++static void dcic_int_enable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ /* Clean pending interrupt before enable int */
++ writel(DCICS_FI_STAT_PENDING, &dcic->regs->dcics);
++ writel(0xffffffff, &dcic->regs->dcics);
++
++ /* Enable function interrupt */
++ val = readl(&dcic->regs->dcicic);
++ val &= ~DCICIC_FUN_INT_MASK;
++ val |= DCICIC_FUN_INT_ENABLE;
++ writel(val, &dcic->regs->dcicic);
++}
++
++static void dcic_int_disable(struct dcic_data *dcic)
++{
++ u32 val;
++
++ /* Disable both function and error interrupt */
++ val = readl(&dcic->regs->dcicic);
++ val = DCICIC_ERROR_INT_DISABLE | DCICIC_FUN_INT_DISABLE;
++ writel(val, &dcic->regs->dcicic);
++}
++
++static irqreturn_t dcic_irq_handler(int irq, void *data)
++{
++ u32 i;
++
++ struct dcic_data *dcic = data;
++ u32 dcics = readl(&dcic->regs->dcics);
++
++ dcic->result = dcics & 0xffff;
++
++ if (!mxc_dcic_vsync)
++ dcic_int_disable(dcic);
++ else {
++ mxc_dcic_irq = 1;
++ mxc_dcic_counter++;
++ }
++
++ /* clean dcic interrupt state */
++ writel(DCICS_FI_STAT_PENDING, &dcic->regs->dcics);
++ writel(dcics, &dcic->regs->dcics);
++
++ if (mxc_dcic_vsync) {
++ wake_up(&mxc_dcic_wait);
++ return IRQ_HANDLED;
++ }
++
++ for (i = 0; i < 16; i++) {
++ pr_debug("ROI=%d,crcRS=0x%x, crcCS=0x%x\n", i,
++ readl(&dcic->regs->ROI[i].dcicrrs),
++ readl(&dcic->regs->ROI[i].dcicrcs));
++ }
++ complete(&dcic->roi_crc_comp);
++
++ return IRQ_HANDLED;
++}
++
++static int dcic_configure(struct dcic_data *dcic, unsigned int sync)
++{
++ u32 val;
++ val = 0;
++
++ /* vsync, hsync, DE, clk_pol */
++ if (!(sync & FB_SYNC_HOR_HIGH_ACT))
++ val |= DCICC_HSYNC_POL_ACTIVE_LOW;
++ if (!(sync & FB_SYNC_VERT_HIGH_ACT))
++ val |= DCICC_VSYNC_POL_ACTIVE_LOW;
++ if (sync & FB_SYNC_OE_LOW_ACT)
++ val |= DCICC_DE_ACTIVE_LOW;
++ if (sync & FB_SYNC_CLK_LAT_FALL)
++ val |= DCICC_CLK_POL_INVERTED;
++
++ writel(val, &dcic->regs->dcicc);
++ return 0;
++}
++
++static int dcic_open(struct inode *inode, struct file *file)
++{
++ struct dcic_data *dcic;
++
++ dcic = container_of(inode->i_cdev, struct dcic_data, cdev);
++
++ mutex_lock(&dcic->lock);
++
++ clk_prepare_enable(dcic->disp_axi_clk);
++ clk_prepare_enable(dcic->dcic_clk);
++
++ file->private_data = dcic;
++ mutex_unlock(&dcic->lock);
++ return 0;
++}
++
++static int dcic_release(struct inode *inode, struct file *file)
++{
++ struct dcic_data *dcic = file->private_data;
++ u32 i;
++
++ mutex_lock(&dcic->lock);
++
++ for (i = 0; i < 16; i++)
++ roi_disable(dcic, i);
++
++ clk_disable_unprepare(dcic->dcic_clk);
++ clk_disable_unprepare(dcic->disp_axi_clk);
++
++ mutex_unlock(&dcic->lock);
++ return 0;
++}
++
++static int dcic_init(struct device_node *np, struct dcic_data *dcic)
++{
++ u32 val, bus;
++
++ val = of_get_dcic_val(np, dcic);
++ if (val < 0) {
++ pr_err("Error incorrect\n");
++ return -1;
++ }
++
++ bus = dcic->bus_n;
++
++ regmap_update_bits(dcic->regmap, dcic->buses[bus].reg ,
++ dcic->buses[bus].mask, val);
++
++ return 0;
++}
++
++static long dcic_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ struct dcic_data *dcic = file->private_data;
++ struct roi_params roi_param;
++ unsigned int sync;
++ int ret = 0;
++
++ switch (cmd) {
++ case DCIC_IOC_CONFIG_DCIC:
++ if (!copy_from_user(&sync, argp, sizeof(unsigned int)))
++ dcic_configure(dcic, sync);
++ break;
++ case DCIC_IOC_CONFIG_ROI:
++ if (copy_from_user(&roi_param, argp, sizeof(roi_param)))
++ return -EFAULT;
++ else
++ if (!roi_configure(dcic, &roi_param))
++ return -EINVAL;
++ break;
++ case DCIC_IOC_GET_RESULT:
++ init_completion(&dcic->roi_crc_comp);
++
++ dcic_enable(dcic);
++
++ dcic->result = 0;
++ msleep(25);
++
++ dcic_int_enable(dcic);
++
++ ret = wait_for_completion_interruptible_timeout(
++ &dcic->roi_crc_comp, 1 * HZ);
++ if (ret == 0) {
++ dev_err(dcic->dev,
++ "dcic wait for roi crc cal timeout\n");
++ ret = -ETIME;
++ } else if (ret > 0) {
++ if (copy_to_user(argp, &dcic->result, sizeof(dcic->result)))
++ return -EFAULT;
++ ret = 0;
++ }
++ dcic_disable(dcic);
++ break;
++ case DCIC_IOC_START_VSYNC:
++ mxc_dcic_vsync = 1;
++ mxc_dcic_irq = 0;
++ mxc_dcic_counter = 0;
++
++ // configure minimum roi block
++ roi_param.roi_n = 0;
++ roi_param.end_x = 1;
++ roi_param.start_x = 0;
++ roi_param.end_y = 1;
++ roi_param.start_y = 0;
++ roi_configure(dcic, &roi_param);
++
++ dcic_enable(dcic);
++ dcic_int_enable(dcic);
++ break;
++ case DCIC_IOC_STOP_VSYNC:
++ mxc_dcic_vsync = 0;
++ mxc_dcic_irq = 0;
++ init_completion(&dcic->roi_crc_comp);
++ wait_for_completion_interruptible_timeout(&dcic->roi_crc_comp, 1 * HZ);
++ dcic_disable(dcic);
++ break;
++ default:
++ pr_err("%s, Unsupport cmd %d\n", __func__, cmd);
++ break;
++ }
++ return ret;
++}
++
++static ssize_t dcic_read(struct file *file, char __user *buf, size_t count,
++ loff_t *ppos)
++{
++ int ret = 0;
++
++ do {
++ if (mxc_dcic_irq) {
++ count = min(sizeof(unsigned long), count);
++ ret = copy_to_user(buf, &mxc_dcic_counter, count) ? -EFAULT : count;
++ mxc_dcic_irq = 0;
++ break;
++ }
++ if (file->f_flags & O_NONBLOCK) {
++ ret = -EAGAIN;
++ }
++ else if (wait_event_interruptible(mxc_dcic_wait, mxc_dcic_irq))
++ ret = -ERESTARTSYS;
++ } while(!ret);
++
++ return ret;
++}
++
++static const struct file_operations mxc_dcic_fops = {
++ .owner = THIS_MODULE,
++ .open = dcic_open,
++ .release = dcic_release,
++ .unlocked_ioctl = dcic_ioctl,
++ .read = dcic_read,
++};
++
++static int dcic_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ const struct of_device_id *of_id =
++ of_match_device(dcic_dt_ids, dev);
++ const struct dcic_info *dcic_info =
++ (const struct dcic_info *)of_id->data;
++ struct device_node *np = dev->of_node;
++ struct dcic_data *dcic;
++ struct resource *res;
++ const char *name;
++ dev_t devt;
++ int ret = 0;
++ int irq;
++
++ dcic = devm_kzalloc(&pdev->dev,
++ sizeof(struct dcic_data),
++ GFP_KERNEL);
++ if (!dcic) {
++ dev_err(&pdev->dev, "Cannot allocate device data\n");
++ ret = -ENOMEM;
++ goto ealloc;
++ }
++
++ platform_set_drvdata(pdev, dcic);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "No dcic base address found.\n");
++ ret = -ENODEV;
++ goto ealloc;
++ }
++
++ dcic->regs = (struct dcic_regs *) devm_ioremap(&pdev->dev, res->start, resource_size(res));
++ if (!dcic->regs) {
++ dev_err(&pdev->dev, "ioremap failed with dcic base\n");
++ ret = -ENOMEM;
++ goto ealloc;
++ }
++
++ dcic->dev = dev;
++ dcic->buses = dcic_info->buses;
++
++ dcic->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
++ if (IS_ERR(dcic->regmap)) {
++ dev_err(dev, "failed to get parent regmap\n");
++ ret = PTR_ERR(dcic->regmap);
++ goto ealloc;
++ }
++
++ /* clock */
++ dcic->disp_axi_clk = devm_clk_get(&pdev->dev, "disp-axi");
++ if (IS_ERR(dcic->disp_axi_clk)) {
++ dev_err(&pdev->dev, "get disp-axi clock failed\n");
++ ret = PTR_ERR(dcic->disp_axi_clk);
++ goto ealloc;
++ }
++
++ dcic->dcic_clk = devm_clk_get(&pdev->dev, "dcic");
++ if (IS_ERR(dcic->dcic_clk)) {
++ dev_err(&pdev->dev, "get dcic clk failed\n");
++ ret = PTR_ERR(dcic->dcic_clk);
++ goto ealloc;
++ }
++
++ mutex_init(&dcic->lock);
++ ret = dcic_init(np, dcic);
++ if (ret < 0) {
++ pr_err("Failed init dcic\n");
++ goto ealloc;
++ }
++
++ /* register device */
++ name = dcic->buses[dcic->bus_n].name;
++ dcic->major = register_chrdev(0, name, &mxc_dcic_fops);
++ if (dcic->major < 0) {
++ pr_err("DCIC: unable to get a major for dcic\n");
++ ret = -EBUSY;
++ goto ealloc;
++ }
++
++ dcic->class = class_create(THIS_MODULE, name);
++ if (IS_ERR(dcic->class)) {
++ ret = PTR_ERR(dcic->class);
++ goto err_out_chrdev;
++ }
++
++ /* create char device */
++ devt = MKDEV(dcic->major, 0);
++ dcic->devt = devt;
++
++ cdev_init(&dcic->cdev, &mxc_dcic_fops);
++ dcic->cdev.owner = THIS_MODULE;
++ ret = cdev_add(&dcic->cdev, devt, 1);
++ if (ret)
++ goto err_out_class;
++
++ device_create(dcic->class, NULL, devt,
++ NULL, name);
++
++ /* IRQ */
++ irq = platform_get_irq(pdev, 0);
++
++ ret = devm_request_irq(&pdev->dev, irq, dcic_irq_handler, 0,
++ dev_name(&pdev->dev), dcic);
++ if (ret) {
++ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
++ irq, ret);
++ goto err_out_cdev;
++ }
++
++ init_waitqueue_head(&mxc_dcic_wait);
++ mxc_dcic_vsync = 0;
++ mxc_dcic_irq = 0;
++
++ return 0;
++
++err_out_cdev:
++ cdev_del(&dcic->cdev);
++err_out_class:
++ device_destroy(dcic->class, devt);
++ class_destroy(dcic->class);
++err_out_chrdev:
++ unregister_chrdev(dcic->major, name);
++ealloc:
++ return ret;
++}
++
++static int dcic_remove(struct platform_device *pdev)
++{
++ struct dcic_data *dcic = platform_get_drvdata(pdev);
++ const char *name;
++
++ name = dcic->buses[dcic->bus_n].name;
++
++ device_destroy(dcic->class, dcic->devt);
++ cdev_del(&dcic->cdev);
++ class_destroy(dcic->class);
++ unregister_chrdev(dcic->major, name);
++ mutex_destroy(&dcic->lock);
++
++ return 0;
++}
++
++static struct platform_driver dcic_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .of_match_table = dcic_dt_ids,
++ },
++ .probe = dcic_probe,
++ .remove = dcic_remove,
++};
++
++module_platform_driver(dcic_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC DCIC driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRIVER_NAME);
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_dispdrv.c linux-3.14.72/drivers/video/mxc/mxc_dispdrv.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_dispdrv.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_dispdrv.c 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,148 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_dispdrv.c
++ * @brief mxc display driver framework.
++ *
++ * A display device driver could call mxc_dispdrv_register(drv) in its dev_probe() function.
++ * Move all dev_probe() things into mxc_dispdrv_driver->init(), init() function should init
++ * and feedback setting;
++ * Move all dev_remove() things into mxc_dispdrv_driver->deinit();
++ * Move all dev_suspend() things into fb_notifier for SUSPEND, if there is;
++ * Move all dev_resume() things into fb_notifier for RESUME, if there is;
++ *
++ * mxc fb driver could call mxc_dispdrv_gethandle(name, setting) before a fb
++ * need be added, with fbi param passing by setting, after
++ * mxc_dispdrv_gethandle() return, FB driver should get the basic setting
++ * about fbi info and crtc.
++ *
++ * @ingroup Framebuffer
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/string.h>
++#include "mxc_dispdrv.h"
++
++static LIST_HEAD(dispdrv_list);
++static DEFINE_MUTEX(dispdrv_lock);
++
++struct mxc_dispdrv_entry {
++ /* Note: drv always the first element */
++ struct mxc_dispdrv_driver *drv;
++ bool active;
++ void *priv;
++ struct list_head list;
++};
++
++struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv)
++{
++ struct mxc_dispdrv_entry *new;
++
++ mutex_lock(&dispdrv_lock);
++
++ new = kzalloc(sizeof(struct mxc_dispdrv_entry), GFP_KERNEL);
++ if (!new) {
++ mutex_unlock(&dispdrv_lock);
++ return ERR_PTR(-ENOMEM);
++ }
++
++ new->drv = drv;
++ list_add_tail(&new->list, &dispdrv_list);
++
++ mutex_unlock(&dispdrv_lock);
++
++ return (struct mxc_dispdrv_handle *)new;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_register);
++
++int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ mutex_lock(&dispdrv_lock);
++ list_del(&entry->list);
++ mutex_unlock(&dispdrv_lock);
++ kfree(entry);
++ return 0;
++ } else
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_unregister);
++
++struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret, found = 0;
++ struct mxc_dispdrv_entry *entry;
++
++ mutex_lock(&dispdrv_lock);
++ list_for_each_entry(entry, &dispdrv_list, list) {
++ if (!strcmp(entry->drv->name, name) && (entry->drv->init)) {
++ ret = entry->drv->init((struct mxc_dispdrv_handle *)
++ entry, setting);
++ if (ret >= 0) {
++ entry->active = true;
++ found = 1;
++ break;
++ }
++ }
++ }
++ mutex_unlock(&dispdrv_lock);
++
++ return found ? (struct mxc_dispdrv_handle *)entry:ERR_PTR(-ENODEV);
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_gethandle);
++
++void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ mutex_lock(&dispdrv_lock);
++ if (entry && entry->active && entry->drv->deinit) {
++ entry->drv->deinit(handle);
++ entry->active = false;
++ }
++ mutex_unlock(&dispdrv_lock);
++
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_puthandle);
++
++int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ entry->priv = data;
++ return 0;
++ } else
++ return -EINVAL;
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_setdata);
++
++void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle)
++{
++ struct mxc_dispdrv_entry *entry = (struct mxc_dispdrv_entry *)handle;
++
++ if (entry) {
++ return entry->priv;
++ } else
++ return ERR_PTR(-EINVAL);
++}
++EXPORT_SYMBOL_GPL(mxc_dispdrv_getdata);
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_dispdrv.h linux-3.14.72/drivers/video/mxc/mxc_dispdrv.h
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_dispdrv.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_dispdrv.h 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,52 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#ifndef __MXC_DISPDRV_H__
++#define __MXC_DISPDRV_H__
++#include <linux/fb.h>
++#include "crtc.h"
++
++struct mxc_dispdrv_handle {
++ struct mxc_dispdrv_driver *drv;
++};
++
++struct mxc_dispdrv_setting {
++ /*input-feedback parameter*/
++ struct fb_info *fbi;
++ int if_fmt;
++ int default_bpp;
++ char *dft_mode_str;
++
++ /* feedback parameter */
++ enum crtc crtc;
++};
++
++struct mxc_dispdrv_driver {
++ const char *name;
++ int (*init) (struct mxc_dispdrv_handle *, struct mxc_dispdrv_setting *);
++ void (*deinit) (struct mxc_dispdrv_handle *);
++ /* display driver enable function for extension */
++ int (*enable) (struct mxc_dispdrv_handle *, struct fb_info *);
++ /* display driver disable function, called at early part of fb_blank */
++ void (*disable) (struct mxc_dispdrv_handle *, struct fb_info *);
++ /* display driver setup function, called at early part of fb_set_par */
++ int (*setup) (struct mxc_dispdrv_handle *, struct fb_info *fbi);
++};
++
++struct mxc_dispdrv_handle *mxc_dispdrv_register(struct mxc_dispdrv_driver *drv);
++int mxc_dispdrv_unregister(struct mxc_dispdrv_handle *handle);
++struct mxc_dispdrv_handle *mxc_dispdrv_gethandle(char *name,
++ struct mxc_dispdrv_setting *setting);
++void mxc_dispdrv_puthandle(struct mxc_dispdrv_handle *handle);
++int mxc_dispdrv_setdata(struct mxc_dispdrv_handle *handle, void *data);
++void *mxc_dispdrv_getdata(struct mxc_dispdrv_handle *handle);
++#endif
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_edid.c linux-3.14.72/drivers/video/mxc/mxc_edid.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_edid.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_edid.c 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,864 @@
++/*
++ * Copyright 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxc_edid.c
++ *
++ * @brief MXC EDID driver
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/i2c.h>
++#include <linux/fb.h>
++#include <video/mxc_edid.h>
++#include "../edid.h"
++
++#undef DEBUG /* define this for verbose EDID parsing output */
++#ifdef DEBUG
++#define DPRINTK(fmt, args...) printk(fmt, ## args)
++#else
++#define DPRINTK(fmt, args...)
++#endif
++
++const struct fb_videomode mxc_cea_mode[64] = {
++ /* #1: 640x480p@59.94/60Hz 4:3 */
++ [1] = {
++ NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #2: 720x480p@59.94/60Hz 4:3 */
++ [2] = {
++ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #3: 720x480p@59.94/60Hz 16:9 */
++ [3] = {
++ NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #4: 1280x720p@59.94/60Hz 16:9 */
++ [4] = {
++ NULL, 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++ /* #5: 1920x1080i@59.94/60Hz 16:9 */
++ [5] = {
++ NULL, 60, 1920, 1080, 13468, 88, 148, 4, 31, 44, 10,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #6: 720(1440)x480iH@59.94/60Hz 4:3 */
++ [6] = {
++ NULL, 60, 1440, 480, 37037, 38, 114, 8, 31, 124, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #7: 720(1440)x480iH@59.94/60Hz 16:9 */
++ [7] = {
++ NULL, 60, 1440, 480, 37037, 38, 114, 8, 31, 124, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #8: 720(1440)x240pH@59.94/60Hz 4:3 */
++ [8] = {
++ NULL, 60, 1440, 240, 37108, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #9: 720(1440)x240pH@59.94/60Hz 16:9 */
++ [9] = {
++ NULL, 60, 1440, 240, 37108, 114, 38, 15, 4, 124, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #14: 1440x480p@59.94/60Hz 4:3 */
++ [14] = {
++ NULL, 60, 1440, 480, 18500, 120, 32, 30, 9, 124, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #15: 1440x480p@59.94/60Hz 16:9 */
++ [15] = {
++ NULL, 60, 1440, 480, 18500, 120, 32, 30, 9, 124, 6, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #16: 1920x1080p@60Hz 16:9 */
++ [16] = {
++ NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #17: 720x576pH@50Hz 4:3 */
++ [17] = {
++ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #18: 720x576pH@50Hz 16:9 */
++ [18] = {
++ NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #19: 1280x720p@50Hz */
++ [19] = {
++ NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #20: 1920x1080i@50Hz */
++ [20] = {
++ NULL, 50, 1920, 1080, 13468, 528, 148, 4, 31, 44, 10,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #21: 720(1440)x576i@50Hz */
++ [21] = {
++ NULL, 50, 1440, 576, 37037, 24, 138, 4, 39, 126, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #22: 720(1440)x576i@50Hz */
++ [22] = {
++ NULL, 50, 1440, 576, 37037, 24, 138, 4, 39, 126, 6, 0,
++ FB_VMODE_INTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #23: 720(1440)x288pH@50Hz 4:3 */
++ [23] = {
++ NULL, 50, 1440, 288, 37037, 138, 24, 19, 2, 126, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #24: 720(1440)x288pH@50Hz 16:9 */
++ [24] = {
++ NULL, 50, 1440, 288, 37037, 138, 24, 19, 2, 126, 3, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #29: 720(1440)x576pH@50Hz 4:3 */
++ [29] = {
++ NULL, 50, 1440, 576, 18518, 136, 24, 39, 5, 128, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, 0,
++ },
++ /* #30: 720(1440)x576pH@50Hz 16:9 */
++ [30] = {
++ NULL, 50, 1440, 576, 18518, 136, 24, 39, 5, 128, 5, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #31: 1920x1080p@50Hz */
++ [31] = {
++ NULL, 50, 1920, 1080, 6734, 148, 528, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #32: 1920x1080p@23.98/24Hz */
++ [32] = {
++ NULL, 24, 1920, 1080, 13468, 148, 638, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #33: 1920x1080p@25Hz */
++ [33] = {
++ NULL, 25, 1920, 1080, 13468, 148, 528, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #34: 1920x1080p@30Hz */
++ [34] = {
++ NULL, 30, 1920, 1080, 13468, 148, 88, 36, 4, 44, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0,
++ },
++ /* #41: 1280x720p@100Hz 16:9 */
++ [41] = {
++ NULL, 100, 1280, 720, 6734, 220, 440, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++ /* #47: 1280x720p@119.88/120Hz 16:9 */
++ [47] = {
++ NULL, 120, 1280, 720, 6734, 220, 110, 20, 5, 40, 5,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_16_9, 0
++ },
++};
++
++#define FB_VMODE_MASK_SIMPLE (FB_VMODE_NONINTERLACED | FB_VMODE_INTERLACED | \
++ FB_VMODE_FRACTIONAL | FB_VMODE_ASPECT_MASK)
++
++int mxc_fb_mode_is_equal_res(const struct fb_videomode *mode1,
++ const struct fb_videomode *mode2)
++{
++ return (mode1->xres == mode2->xres &&
++ mode1->yres == mode2->yres &&
++ mode1->refresh == mode2->refresh &&
++ (mode1->vmode & FB_VMODE_MASK_SIMPLE) ==
++ (mode2->vmode & FB_VMODE_MASK_SIMPLE));
++}
++EXPORT_SYMBOL(mxc_fb_mode_is_equal_res);
++
++/*
++ * We have a special version of fb_mode_is_equal that ignores
++ * pixclock, since for many CEA modes, 2 frequencies are supported
++ * e.g. 640x480 @ 60Hz or 59.94Hz
++ */
++int mxc_edid_fb_mode_is_equal(bool use_aspect,
++ const struct fb_videomode *mode1,
++ const struct fb_videomode *mode2)
++{
++ u32 mask;
++
++ if (use_aspect)
++ mask = ~0;
++ else
++ mask = ~FB_VMODE_ASPECT_MASK;
++
++ return (mode1->xres == mode2->xres &&
++ mode1->yres == mode2->yres &&
++ mode1->hsync_len == mode2->hsync_len &&
++ mode1->vsync_len == mode2->vsync_len &&
++ mode1->left_margin == mode2->left_margin &&
++ mode1->right_margin == mode2->right_margin &&
++ mode1->upper_margin == mode2->upper_margin &&
++ mode1->lower_margin == mode2->lower_margin &&
++ mode1->sync == mode2->sync &&
++ /* refresh check, 59.94Hz and 60Hz have the same parameter
++ * in struct of mxc_cea_mode */
++ abs(mode1->refresh - mode2->refresh) <= 1 &&
++ (mode1->vmode & mask) == (mode2->vmode & mask));
++}
++
++static void get_detailed_timing(unsigned char *block,
++ struct fb_videomode *mode)
++{
++ mode->xres = H_ACTIVE;
++ mode->yres = V_ACTIVE;
++ mode->pixclock = PIXEL_CLOCK;
++ mode->pixclock /= 1000;
++ mode->pixclock = KHZ2PICOS(mode->pixclock);
++ mode->right_margin = H_SYNC_OFFSET;
++ mode->left_margin = (H_ACTIVE + H_BLANKING) -
++ (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
++ mode->upper_margin = V_BLANKING - V_SYNC_OFFSET -
++ V_SYNC_WIDTH;
++ mode->lower_margin = V_SYNC_OFFSET;
++ mode->hsync_len = H_SYNC_WIDTH;
++ mode->vsync_len = V_SYNC_WIDTH;
++ if (HSYNC_POSITIVE)
++ mode->sync |= FB_SYNC_HOR_HIGH_ACT;
++ if (VSYNC_POSITIVE)
++ mode->sync |= FB_SYNC_VERT_HIGH_ACT;
++ mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) *
++ (V_ACTIVE + V_BLANKING));
++ if (INTERLACED) {
++ mode->yres *= 2;
++ mode->upper_margin *= 2;
++ mode->lower_margin *= 2;
++ mode->vsync_len *= 2;
++ mode->vmode |= FB_VMODE_INTERLACED;
++ }
++ mode->flag = FB_MODE_IS_DETAILED;
++
++ if ((H_SIZE / 16) == (V_SIZE / 9))
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ else if ((H_SIZE / 4) == (V_SIZE / 3))
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++ else if ((mode->xres / 16) == (mode->yres / 9))
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ else if ((mode->xres / 4) == (mode->yres / 3))
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++
++ if (mode->vmode & FB_VMODE_ASPECT_16_9)
++ DPRINTK("Aspect ratio: 16:9\n");
++ if (mode->vmode & FB_VMODE_ASPECT_4_3)
++ DPRINTK("Aspect ratio: 4:3\n");
++ DPRINTK(" %d MHz ", PIXEL_CLOCK/1000000);
++ DPRINTK("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET,
++ H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING);
++ DPRINTK("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET,
++ V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING);
++ DPRINTK("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-",
++ (VSYNC_POSITIVE) ? "+" : "-");
++}
++
++int mxc_edid_parse_ext_blk(unsigned char *edid,
++ struct mxc_edid_cfg *cfg,
++ struct fb_monspecs *specs)
++{
++ char detail_timing_desc_offset;
++ struct fb_videomode *mode, *m;
++ unsigned char index = 0x0;
++ unsigned char *block;
++ int i, num = 0, revision;
++
++ if (edid[index++] != 0x2) /* only support cea ext block now */
++ return 0;
++ revision = edid[index++];
++ DPRINTK("cea extent revision %d\n", revision);
++ mode = kzalloc(50 * sizeof(struct fb_videomode), GFP_KERNEL);
++ if (mode == NULL)
++ return -1;
++
++ detail_timing_desc_offset = edid[index++];
++
++ memset(cfg->sample_rates, 0, sizeof(cfg->sample_rates));
++ memset(cfg->sample_sizes, 0, sizeof(cfg->sample_sizes));
++
++ if (revision >= 2) {
++ cfg->cea_underscan = (edid[index] >> 7) & 0x1;
++ cfg->cea_basicaudio = (edid[index] >> 6) & 0x1;
++ cfg->cea_ycbcr444 = (edid[index] >> 5) & 0x1;
++ cfg->cea_ycbcr422 = (edid[index] >> 4) & 0x1;
++
++ if (cfg->cea_basicaudio) {
++ cfg->sample_rates[0] = 0x07;
++ cfg->sample_sizes[0] = 0x01;
++ }
++
++ DPRINTK("CEA underscan %d\n", cfg->cea_underscan);
++ DPRINTK("CEA basicaudio %d\n", cfg->cea_basicaudio);
++ DPRINTK("CEA ycbcr444 %d\n", cfg->cea_ycbcr444);
++ DPRINTK("CEA ycbcr422 %d\n", cfg->cea_ycbcr422);
++ }
++
++ if (revision >= 3) {
++ /* short desc */
++ DPRINTK("CEA Short desc timmings\n");
++ index++;
++ while (index < detail_timing_desc_offset) {
++ unsigned char tagcode, blklen;
++
++ tagcode = (edid[index] >> 5) & 0x7;
++ blklen = (edid[index]) & 0x1f;
++
++ DPRINTK("Tagcode %x Len %d\n", tagcode, blklen);
++
++ switch (tagcode) {
++ case 0x2: /*Video data block*/
++ {
++ int cea_idx;
++ i = 0;
++ while (i < blklen) {
++ index++;
++ cea_idx = edid[index] & 0x7f;
++ if (cea_idx < ARRAY_SIZE(mxc_cea_mode) &&
++ (mxc_cea_mode[cea_idx].xres)) {
++ DPRINTK("Support CEA Format #%d\n", cea_idx);
++ mode[num] = mxc_cea_mode[cea_idx];
++ mode[num].flag |= FB_MODE_IS_STANDARD;
++ num++;
++ }
++ i++;
++ }
++ break;
++ }
++ case 0x3: /*Vendor specific data*/
++ {
++ unsigned char IEEE_reg_iden[3];
++ unsigned char deep_color;
++ unsigned char latency_present;
++ unsigned char I_latency_present;
++ unsigned char hdmi_video_present;
++ unsigned char hdmi_3d_present;
++ unsigned char hdmi_3d_multi_present;
++ unsigned char hdmi_vic_len;
++ unsigned char hdmi_3d_len;
++ unsigned char index_inc = 0;
++ unsigned char vsd_end;
++
++ vsd_end = index + blklen;
++
++ IEEE_reg_iden[0] = edid[index+1];
++ IEEE_reg_iden[1] = edid[index+2];
++ IEEE_reg_iden[2] = edid[index+3];
++ cfg->physical_address[0] = (edid[index+4] & 0xf0) >> 4;
++ cfg->physical_address[1] = (edid[index+4] & 0x0f);
++ cfg->physical_address[2] = (edid[index+5] & 0xf0) >> 4;
++ cfg->physical_address[3] = (edid[index+5] & 0x0f);
++
++ if ((IEEE_reg_iden[0] == 0x03) &&
++ (IEEE_reg_iden[1] == 0x0c) &&
++ (IEEE_reg_iden[2] == 0x00))
++ cfg->hdmi_cap = 1;
++
++ if (blklen > 5) {
++ deep_color = edid[index+6];
++ if (deep_color & 0x80)
++ cfg->vsd_support_ai = true;
++ if (deep_color & 0x40)
++ cfg->vsd_dc_48bit = true;
++ if (deep_color & 0x20)
++ cfg->vsd_dc_36bit = true;
++ if (deep_color & 0x10)
++ cfg->vsd_dc_30bit = true;
++ if (deep_color & 0x08)
++ cfg->vsd_dc_y444 = true;
++ if (deep_color & 0x01)
++ cfg->vsd_dvi_dual = true;
++ }
++
++ DPRINTK("VSD hdmi capability %d\n", cfg->hdmi_cap);
++ DPRINTK("VSD support ai %d\n", cfg->vsd_support_ai);
++ DPRINTK("VSD support deep color 48bit %d\n", cfg->vsd_dc_48bit);
++ DPRINTK("VSD support deep color 36bit %d\n", cfg->vsd_dc_36bit);
++ DPRINTK("VSD support deep color 30bit %d\n", cfg->vsd_dc_30bit);
++ DPRINTK("VSD support deep color y444 %d\n", cfg->vsd_dc_y444);
++ DPRINTK("VSD support dvi dual %d\n", cfg->vsd_dvi_dual);
++
++ if (blklen > 6)
++ cfg->vsd_max_tmdsclk_rate = edid[index+7] * 5;
++ DPRINTK("VSD MAX TMDS CLOCK RATE %d\n", cfg->vsd_max_tmdsclk_rate);
++
++ if (blklen > 7) {
++ latency_present = edid[index+8] >> 7;
++ I_latency_present = (edid[index+8] & 0x40) >> 6;
++ hdmi_video_present = (edid[index+8] & 0x20) >> 5;
++ cfg->vsd_cnc3 = (edid[index+8] & 0x8) >> 3;
++ cfg->vsd_cnc2 = (edid[index+8] & 0x4) >> 2;
++ cfg->vsd_cnc1 = (edid[index+8] & 0x2) >> 1;
++ cfg->vsd_cnc0 = edid[index+8] & 0x1;
++
++ DPRINTK("VSD cnc0 %d\n", cfg->vsd_cnc0);
++ DPRINTK("VSD cnc1 %d\n", cfg->vsd_cnc1);
++ DPRINTK("VSD cnc2 %d\n", cfg->vsd_cnc2);
++ DPRINTK("VSD cnc3 %d\n", cfg->vsd_cnc3);
++ DPRINTK("latency_present %d\n", latency_present);
++ DPRINTK("I_latency_present %d\n", I_latency_present);
++ DPRINTK("hdmi_video_present %d\n", hdmi_video_present);
++
++ } else {
++ index += blklen;
++ break;
++ }
++
++ index += 9;
++
++ /*latency present */
++ if (latency_present) {
++ cfg->vsd_video_latency = edid[index++];
++ cfg->vsd_audio_latency = edid[index++];
++
++ if (I_latency_present) {
++ cfg->vsd_I_video_latency = edid[index++];
++ cfg->vsd_I_audio_latency = edid[index++];
++ } else {
++ cfg->vsd_I_video_latency = cfg->vsd_video_latency;
++ cfg->vsd_I_audio_latency = cfg->vsd_audio_latency;
++ }
++
++ DPRINTK("VSD latency video_latency %d\n", cfg->vsd_video_latency);
++ DPRINTK("VSD latency audio_latency %d\n", cfg->vsd_audio_latency);
++ DPRINTK("VSD latency I_video_latency %d\n", cfg->vsd_I_video_latency);
++ DPRINTK("VSD latency I_audio_latency %d\n", cfg->vsd_I_audio_latency);
++ }
++
++ if (hdmi_video_present) {
++ hdmi_3d_present = edid[index] >> 7;
++ hdmi_3d_multi_present = (edid[index] & 0x60) >> 5;
++ index++;
++ hdmi_vic_len = (edid[index] & 0xe0) >> 5;
++ hdmi_3d_len = edid[index] & 0x1f;
++ index++;
++
++ DPRINTK("hdmi_3d_present %d\n", hdmi_3d_present);
++ DPRINTK("hdmi_3d_multi_present %d\n", hdmi_3d_multi_present);
++ DPRINTK("hdmi_vic_len %d\n", hdmi_vic_len);
++ DPRINTK("hdmi_3d_len %d\n", hdmi_3d_len);
++
++ if (hdmi_vic_len > 0) {
++ for (i = 0; i < hdmi_vic_len; i++) {
++ cfg->hdmi_vic[i] = edid[index++];
++ DPRINTK("HDMI_vic=%d\n", cfg->hdmi_vic[i]);
++ }
++ }
++
++ if (hdmi_3d_len > 0) {
++ if (hdmi_3d_present) {
++ if (hdmi_3d_multi_present == 0x1) {
++ cfg->hdmi_3d_struct_all = (edid[index] << 8) | edid[index+1];
++ index_inc = 2;
++ } else if (hdmi_3d_multi_present == 0x2) {
++ cfg->hdmi_3d_struct_all = (edid[index] << 8) | edid[index+1];
++ cfg->hdmi_3d_mask_all = (edid[index+2] << 8) | edid[index+3];
++ index_inc = 4;
++ } else
++ index_inc = 0;
++ }
++
++ DPRINTK("HDMI 3d struct all =0x%x\n", cfg->hdmi_3d_struct_all);
++ DPRINTK("HDMI 3d mask all =0x%x\n", cfg->hdmi_3d_mask_all);
++
++ /* Read 2D vic 3D_struct */
++ if ((hdmi_3d_len - index_inc) > 0) {
++ DPRINTK("Support 3D video format\n");
++ i = 0;
++ while ((hdmi_3d_len - index_inc) > 0) {
++
++ cfg->hdmi_3d_format[i].vic_order_2d = edid[index+index_inc] >> 4;
++ cfg->hdmi_3d_format[i].struct_3d = edid[index+index_inc] & 0x0f;
++ index_inc++;
++
++ if (cfg->hdmi_3d_format[i].struct_3d == 8) {
++ cfg->hdmi_3d_format[i].detail_3d = edid[index+index_inc] >> 4;
++ index_inc++;
++ } else if (cfg->hdmi_3d_format[i].struct_3d > 8) {
++ cfg->hdmi_3d_format[i].detail_3d = 0;
++ index_inc++;
++ }
++
++ DPRINTK("vic_order_2d=%d, 3d_struct=%d, 3d_detail=0x%x\n",
++ cfg->hdmi_3d_format[i].vic_order_2d,
++ cfg->hdmi_3d_format[i].struct_3d,
++ cfg->hdmi_3d_format[i].detail_3d);
++ i++;
++ }
++ }
++ index += index_inc;
++ }
++ }
++
++ index = vsd_end;
++
++ break;
++ }
++ case 0x1: /*Audio data block*/
++ {
++ u8 audio_format, byte1, byte2, byte3;
++ int ch_idx;
++
++ i = 0;
++ while (i < blklen) {
++ byte1 = edid[index + 1];
++ byte2 = edid[index + 2];
++ byte3 = edid[index + 3];
++ index += 3;
++ i += 3;
++
++ audio_format = (byte1 & 0x7f) >> 3;
++
++ DPRINTK("Audio Format Descriptor : %2d\n", audio_format);
++ DPRINTK("Max Number of Channels : %2d\n", (byte1 & 0x07) + 1);
++ DPRINTK("Sample Rates : %02x\n", byte2 & 0x7f);
++
++ /* ALSA can't specify specific compressed
++ * formats, so only care about PCM for now. */
++ if (audio_format == AUDIO_CODING_TYPE_LPCM) {
++ for (ch_idx = (byte1 & 0x07) / 2; ch_idx >= 0; ch_idx--) {
++ cfg->sample_rates[ch_idx] |= byte2 & 0x7f;
++ cfg->sample_sizes[ch_idx] |= byte3 & 0x7;
++ }
++ DPRINTK("Sample Sizes : %02x\n",
++ byte3 & 0x7);
++ }
++
++ /* HD-audio: pretend to support 192kHz/16bit in 8ch mode to
++ * allow HD passthrough on sinks that report only 6ch LPCM */
++ if (audio_format == AUDIO_CODING_TYPE_MLP ||
++ audio_format == AUDIO_CODING_TYPE_DTS_HD) {
++ cfg->sample_rates[3] |= 0x40;
++ cfg->sample_sizes[3] |= 0x01;
++ }
++ }
++ break;
++ }
++ case 0x4: /*Speaker allocation block*/
++ {
++ i = 0;
++ while (i < blklen) {
++ cfg->speaker_alloc = edid[index + 1] & 0x7f;
++ index += 3;
++ i += 3;
++ DPRINTK("Speaker Alloc : %02x\n", cfg->speaker_alloc);
++ }
++ break;
++ }
++ case 0x7: /*User extended block*/
++ if (blklen >= 2 && edid[index + 1] == 0) { /*Video Capability Data Block*/
++ u8 data = edid[index + 2];
++
++ cfg->cea_scan_mode_ce = (data >> 0) & 3;
++ cfg->cea_scan_mode_it = (data >> 2) & 3;
++ cfg->cea_scan_mode_pt = (data >> 4) & 3;
++ cfg->cea_rgb_range_selectable = (data >> 6) & 1;
++
++ DPRINTK("VCDB over/underscan behavior (CE) %d\n", cfg->cea_scan_mode_ce);
++ DPRINTK("VCDB over/underscan behavior (IT) %d\n", cfg->cea_scan_mode_it);
++ DPRINTK("VCDB over/underscan behavior (PT) %d\n", cfg->cea_scan_mode_pt);
++ DPRINTK("VCDB RGB quant. range selectable %d\n", cfg->cea_rgb_range_selectable);
++
++ index += blklen;
++ break;
++ }
++ default:
++ /* skip */
++ DPRINTK("Not handle block, tagcode = 0x%x\n", tagcode);
++ index += blklen;
++ break;
++ }
++
++ index++;
++ }
++ }
++
++ /* long desc */
++ DPRINTK("CEA long desc timmings\n");
++ index = detail_timing_desc_offset;
++ block = edid + index;
++ while (index < (EDID_LENGTH - DETAILED_TIMING_DESCRIPTION_SIZE)) {
++ if (!(block[0] == 0x00 && block[1] == 0x00)) {
++ get_detailed_timing(block, &mode[num]);
++ num++;
++ }
++ block += DETAILED_TIMING_DESCRIPTION_SIZE;
++ index += DETAILED_TIMING_DESCRIPTION_SIZE;
++ }
++
++ if (!num) {
++ kfree(mode);
++ return 0;
++ }
++
++ m = kmalloc((num + specs->modedb_len) *
++ sizeof(struct fb_videomode), GFP_KERNEL);
++ if (!m)
++ return 0;
++
++ if (specs->modedb_len) {
++ memmove(m, specs->modedb,
++ specs->modedb_len * sizeof(struct fb_videomode));
++ kfree(specs->modedb);
++ }
++ memmove(m+specs->modedb_len, mode,
++ num * sizeof(struct fb_videomode));
++ kfree(mode);
++
++ specs->modedb_len += num;
++ specs->modedb = m;
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_edid_parse_ext_blk);
++
++static int mxc_edid_readblk(struct i2c_adapter *adp,
++ unsigned short addr, unsigned char *edid)
++{
++ int ret = 0, extblknum = 0;
++ unsigned char regaddr = 0x0;
++ struct i2c_msg msg[2] = {
++ {
++ .addr = addr,
++ .flags = 0,
++ .len = 1,
++ .buf = &regaddr,
++ }, {
++ .addr = addr,
++ .flags = I2C_M_RD,
++ .len = EDID_LENGTH,
++ .buf = edid,
++ },
++ };
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++
++ if (edid[1] == 0x00)
++ return -ENOENT;
++
++ extblknum = edid[0x7E];
++
++ if (extblknum) {
++ regaddr = 128;
++ msg[1].buf = edid + EDID_LENGTH;
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID ext block\n");
++ return -EIO;
++ }
++ }
++
++ return extblknum;
++}
++
++static int mxc_edid_readsegblk(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, int seg_num)
++{
++ int ret = 0;
++ unsigned char segment = 0x1, regaddr = 0;
++ struct i2c_msg msg[3] = {
++ {
++ .addr = 0x30,
++ .flags = 0,
++ .len = 1,
++ .buf = &segment,
++ }, {
++ .addr = addr,
++ .flags = 0,
++ .len = 1,
++ .buf = &regaddr,
++ }, {
++ .addr = addr,
++ .flags = I2C_M_RD,
++ .len = EDID_LENGTH,
++ .buf = edid,
++ },
++ };
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++
++ if (seg_num == 2) {
++ regaddr = 128;
++ msg[2].buf = edid + EDID_LENGTH;
++
++ ret = i2c_transfer(adp, msg, ARRAY_SIZE(msg));
++ if (ret != ARRAY_SIZE(msg)) {
++ DPRINTK("unable to read EDID block\n");
++ return -EIO;
++ }
++ }
++
++ return ret;
++}
++
++int mxc_edid_var_to_vic(struct fb_var_screeninfo *var)
++{
++ int i;
++ struct fb_videomode m;
++
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ fb_var_to_videomode(&m, var);
++ if (mxc_edid_fb_mode_is_equal(false, &m, &mxc_cea_mode[i]))
++ break;
++ }
++
++ if (i == ARRAY_SIZE(mxc_cea_mode))
++ return 0;
++
++ return i;
++}
++EXPORT_SYMBOL(mxc_edid_var_to_vic);
++
++int mxc_edid_mode_to_vic(const struct fb_videomode *mode)
++{
++ int i;
++ bool use_aspect = (mode->vmode & FB_VMODE_ASPECT_MASK);
++
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ if (mxc_edid_fb_mode_is_equal(use_aspect, mode, &mxc_cea_mode[i]))
++ break;
++ }
++
++ if (i == ARRAY_SIZE(mxc_cea_mode))
++ return 0;
++
++ return i;
++}
++EXPORT_SYMBOL(mxc_edid_mode_to_vic);
++
++/* make sure edid has 512 bytes*/
++int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi)
++{
++ int ret = 0, extblknum;
++ if (!adp || !edid || !cfg || !fbi)
++ return -EINVAL;
++
++ memset(edid, 0, EDID_LENGTH*4);
++ memset(cfg, 0, sizeof(struct mxc_edid_cfg));
++
++ extblknum = mxc_edid_readblk(adp, addr, edid);
++ if (extblknum < 0)
++ return extblknum;
++
++ /* edid first block parsing */
++ memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
++ fb_edid_to_monspecs(edid, &fbi->monspecs);
++
++ if (extblknum) {
++ int i;
++
++ /* FIXME: mxc_edid_readsegblk() won't read more than 2 blocks
++ * and the for-loop will read past the end of the buffer! :-( */
++ BUG_ON(extblknum > 3);
++
++ /* need read segment block? */
++ if (extblknum > 1) {
++ ret = mxc_edid_readsegblk(adp, addr,
++ edid + EDID_LENGTH*2, extblknum - 1);
++ if (ret < 0)
++ return ret;
++ }
++
++ for (i = 1; i <= extblknum; i++)
++ /* edid ext block parsing */
++ mxc_edid_parse_ext_blk(edid + i*EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_edid_read);
++
++const struct fb_videomode *mxc_fb_find_nearest_mode(const struct fb_videomode *mode,
++ struct list_head *head, bool relax)
++{
++ struct list_head *pos;
++ struct fb_modelist *modelist;
++ struct fb_videomode *cmode;
++ static struct fb_videomode *best;
++ static u32 diff, diff_refresh;
++ u32 mask = relax ? FB_VMODE_MASK_SIMPLE | FB_VMODE_ASPECT_MASK : ~0;
++
++ if (!relax) {
++ diff = -1;
++ diff_refresh = -1;
++ best = NULL;
++ }
++
++ list_for_each(pos, head) {
++ u32 d;
++
++ modelist = list_entry(pos, struct fb_modelist, list);
++ cmode = &modelist->mode;
++
++ if ((mode->vmode ^ cmode->vmode) & mask)
++ continue;
++
++ d = abs(cmode->xres - mode->xres) +
++ abs(cmode->yres - mode->yres);
++ if (diff > d) {
++ diff = d;
++ diff_refresh = abs(cmode->refresh - mode->refresh);
++ best = cmode;
++ } else if (diff == d) {
++ d = abs(cmode->refresh - mode->refresh);
++ if (diff_refresh > d) {
++ diff_refresh = d;
++ best = cmode;
++ }
++ }
++ }
++
++ if ((!relax && (diff_refresh || diff)) || !best)
++ mxc_fb_find_nearest_mode(mode, head, true);
++
++ return best;
++}
++EXPORT_SYMBOL(mxc_fb_find_nearest_mode);
++
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_epdc_fb.c linux-3.14.72/drivers/video/mxc/mxc_epdc_fb.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_epdc_fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_epdc_fb.c 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,5577 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * Based on STMP378X LCDIF
++ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
++ */
++
++#include <linux/busfreq-imx6.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/uaccess.h>
++#include <linux/cpufreq.h>
++#include <linux/firmware.h>
++#include <linux/kthread.h>
++#include <linux/dmaengine.h>
++#include <linux/pxp_dma.h>
++#include <linux/pm_runtime.h>
++#include <linux/mxcfb.h>
++#include <linux/mxcfb_epdc.h>
++#include <linux/gpio.h>
++#include <linux/regulator/driver.h>
++#include <linux/fsl_devices.h>
++#include <linux/bitops.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_data/dma-imx.h>
++#include <asm/cacheflush.h>
++
++#include "epdc_regs.h"
++
++/*
++ * Enable this define to have a default panel
++ * loaded during driver initialization
++ */
++/*#define DEFAULT_PANEL_HW_INIT*/
++
++#define NUM_SCREENS_MIN 2
++
++#define EPDC_V1_NUM_LUTS 16
++#define EPDC_V1_MAX_NUM_UPDATES 20
++#define EPDC_V2_NUM_LUTS 64
++#define EPDC_V2_MAX_NUM_UPDATES 64
++#define EPDC_MAX_NUM_BUFFERS 2
++#define INVALID_LUT (-1)
++#define DRY_RUN_NO_LUT 100
++
++/* Maximum update buffer image width due to v2.0 and v2.1 errata ERR005313. */
++#define EPDC_V2_MAX_UPDATE_WIDTH 2047
++#define EPDC_V2_ROTATION_ALIGNMENT 8
++
++#define DEFAULT_TEMP_INDEX 0
++#define DEFAULT_TEMP 20 /* room temp in deg Celsius */
++
++#define INIT_UPDATE_MARKER 0x12345678
++#define PAN_UPDATE_MARKER 0x12345679
++
++#define POWER_STATE_OFF 0
++#define POWER_STATE_ON 1
++
++#define MERGE_OK 0
++#define MERGE_FAIL 1
++#define MERGE_BLOCK 2
++
++static unsigned long default_bpp = 16;
++DEFINE_MUTEX(hard_lock);
++
++struct update_marker_data {
++ struct list_head full_list;
++ struct list_head upd_list;
++ u32 update_marker;
++ struct completion update_completion;
++ int lut_num;
++ bool collision_test;
++ bool waiting;
++};
++
++struct update_desc_list {
++ struct list_head list;
++ struct mxcfb_update_data upd_data;/* Update parameters */
++ u32 epdc_offs; /* Added to buffer ptr to resolve alignment */
++ u32 epdc_stride; /* Depends on rotation & whether we skip PxP */
++ struct list_head upd_marker_list; /* List of markers for this update */
++ u32 update_order; /* Numeric ordering value for update */
++};
++
++/* This structure represents a list node containing both
++ * a memory region allocated as an output buffer for the PxP
++ * update processing task, and the update description (mode, region, etc.) */
++struct update_data_list {
++ struct list_head list;
++ dma_addr_t phys_addr; /* Pointer to phys address of processed Y buf */
++ void *virt_addr;
++ struct update_desc_list *update_desc;
++ int lut_num; /* Assigned before update is processed into working buffer */
++ u64 collision_mask; /* Set when update creates collision */
++ /* Mask of the LUTs the update collides with */
++};
++
++struct mxc_epdc_fb_data {
++ struct fb_info info;
++ struct fb_var_screeninfo epdc_fb_var; /* Internal copy of screeninfo
++ so we can sync changes to it */
++ u32 pseudo_palette[16];
++ char fw_str[24];
++ struct list_head list;
++ struct imx_epdc_fb_mode *cur_mode;
++ struct imx_epdc_fb_platform_data *pdata;
++ int blank;
++ u32 max_pix_size;
++ ssize_t map_size;
++ dma_addr_t phys_start;
++ u32 fb_offset;
++ int default_bpp;
++ int native_width;
++ int native_height;
++ int num_screens;
++ int epdc_irq;
++ struct device *dev;
++ int power_state;
++ int wait_for_powerdown;
++ struct completion powerdown_compl;
++ struct clk *epdc_clk_axi;
++ struct clk *epdc_clk_pix;
++ struct regulator *display_regulator;
++ struct regulator *vcom_regulator;
++ struct regulator *v3p3_regulator;
++ bool fw_default_load;
++ int rev;
++
++ /* FB elements related to EPDC updates */
++ int num_luts;
++ int max_num_updates;
++ bool in_init;
++ bool hw_ready;
++ bool hw_initializing;
++ bool waiting_for_idle;
++ u32 auto_mode;
++ u32 upd_scheme;
++ struct list_head upd_pending_list;
++ struct list_head upd_buf_queue;
++ struct list_head upd_buf_free_list;
++ struct list_head upd_buf_collision_list;
++ struct update_data_list *cur_update;
++ struct mutex queue_mutex;
++ int trt_entries;
++ int temp_index;
++ u8 *temp_range_bounds;
++ struct mxcfb_waveform_modes wv_modes;
++ bool wv_modes_update;
++ u32 *waveform_buffer_virt;
++ u32 waveform_buffer_phys;
++ u32 waveform_buffer_size;
++ u32 *working_buffer_virt;
++ u32 working_buffer_phys;
++ u32 working_buffer_size;
++ dma_addr_t *phys_addr_updbuf;
++ void **virt_addr_updbuf;
++ u32 upd_buffer_num;
++ u32 max_num_buffers;
++ dma_addr_t phys_addr_copybuf; /* Phys address of copied update data */
++ void *virt_addr_copybuf; /* Used for PxP SW workaround */
++ u32 order_cnt;
++ struct list_head full_marker_list;
++ u32 *lut_update_order; /* Array size = number of luts */
++ u64 epdc_colliding_luts;
++ u64 luts_complete_wb;
++ struct completion updates_done;
++ struct delayed_work epdc_done_work;
++ struct workqueue_struct *epdc_submit_workqueue;
++ struct work_struct epdc_submit_work;
++ struct workqueue_struct *epdc_intr_workqueue;
++ struct work_struct epdc_intr_work;
++ bool waiting_for_wb;
++ bool waiting_for_lut;
++ bool waiting_for_lut15;
++ struct completion update_res_free;
++ struct completion lut15_free;
++ struct completion eof_event;
++ int eof_sync_period;
++ struct mutex power_mutex;
++ bool powering_down;
++ bool updates_active;
++ int pwrdown_delay;
++ unsigned long tce_prevent;
++ bool restrict_width; /* work around rev >=2.0 width and
++ stride restriction */
++
++ /* FB elements related to PxP DMA */
++ struct completion pxp_tx_cmpl;
++ struct pxp_channel *pxp_chan;
++ struct pxp_config_data pxp_conf;
++ struct dma_async_tx_descriptor *txd;
++ dma_cookie_t cookie;
++ struct scatterlist sg[2];
++ struct mutex pxp_mutex; /* protects access to PxP */
++};
++
++struct waveform_data_header {
++ unsigned int wi0;
++ unsigned int wi1;
++ unsigned int wi2;
++ unsigned int wi3;
++ unsigned int wi4;
++ unsigned int wi5;
++ unsigned int wi6;
++ unsigned int xwia:24;
++ unsigned int cs1:8;
++ unsigned int wmta:24;
++ unsigned int fvsn:8;
++ unsigned int luts:8;
++ unsigned int mc:8;
++ unsigned int trc:8;
++ unsigned int reserved0_0:8;
++ unsigned int eb:8;
++ unsigned int sb:8;
++ unsigned int reserved0_1:8;
++ unsigned int reserved0_2:8;
++ unsigned int reserved0_3:8;
++ unsigned int reserved0_4:8;
++ unsigned int reserved0_5:8;
++ unsigned int cs2:8;
++};
++
++struct mxcfb_waveform_data_file {
++ struct waveform_data_header wdh;
++ u32 *data; /* Temperature Range Table + Waveform Data */
++};
++
++static struct fb_videomode e60_v110_mode = {
++ .name = "E60_V110",
++ .refresh = 50,
++ .xres = 800,
++ .yres = 600,
++ .pixclock = 18604700,
++ .left_margin = 8,
++ .right_margin = 178,
++ .upper_margin = 4,
++ .lower_margin = 10,
++ .hsync_len = 20,
++ .vsync_len = 4,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct fb_videomode e60_v220_mode = {
++ .name = "E60_V220",
++ .refresh = 85,
++ .xres = 800,
++ .yres = 600,
++ .pixclock = 30000000,
++ .left_margin = 8,
++ .right_margin = 164,
++ .upper_margin = 4,
++ .lower_margin = 8,
++ .hsync_len = 4,
++ .vsync_len = 1,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct fb_videomode e060scm_mode = {
++ .name = "E060SCM",
++ .refresh = 85,
++ .xres = 800,
++ .yres = 600,
++ .pixclock = 26666667,
++ .left_margin = 8,
++ .right_margin = 100,
++ .upper_margin = 4,
++ .lower_margin = 8,
++ .hsync_len = 4,
++ .vsync_len = 1,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct fb_videomode e97_v110_mode = {
++ .name = "E97_V110",
++ .refresh = 50,
++ .xres = 1200,
++ .yres = 825,
++ .pixclock = 32000000,
++ .left_margin = 12,
++ .right_margin = 128,
++ .upper_margin = 4,
++ .lower_margin = 10,
++ .hsync_len = 20,
++ .vsync_len = 4,
++ .sync = 0,
++ .vmode = FB_VMODE_NONINTERLACED,
++ .flag = 0,
++};
++
++static struct imx_epdc_fb_mode panel_modes[] = {
++ {
++ &e60_v110_mode,
++ 4, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 428, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 1, /* gdclk_offs */
++ 1, /* num_ce */
++ },
++ {
++ &e60_v220_mode,
++ 4, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 465, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 9, /* gdclk_offs */
++ 1, /* num_ce */
++ },
++ {
++ &e060scm_mode,
++ 4, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 419, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 5, /* gdclk_offs */
++ 1, /* num_ce */
++ },
++ {
++ &e97_v110_mode,
++ 8, /* vscan_holdoff */
++ 10, /* sdoed_width */
++ 20, /* sdoed_delay */
++ 10, /* sdoez_width */
++ 20, /* sdoez_delay */
++ 632, /* gdclk_hp_offs */
++ 20, /* gdsp_offs */
++ 0, /* gdoe_offs */
++ 1, /* gdclk_offs */
++ 3, /* num_ce */
++ }
++};
++
++static struct imx_epdc_fb_platform_data epdc_data = {
++ .epdc_mode = panel_modes,
++ .num_modes = ARRAY_SIZE(panel_modes),
++};
++
++void __iomem *epdc_base;
++
++struct mxc_epdc_fb_data *g_fb_data;
++
++/* forward declaration */
++static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data,
++ int temp);
++static void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data);
++static int mxc_epdc_fb_blank(int blank, struct fb_info *info);
++static int mxc_epdc_fb_init_hw(struct fb_info *info);
++static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
++ u32 src_width, u32 src_height,
++ struct mxcfb_rect *update_region);
++static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat);
++
++static void draw_mode0(struct mxc_epdc_fb_data *fb_data);
++static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data);
++
++static void do_dithering_processing_Y1_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist);
++static void do_dithering_processing_Y4_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist);
++
++#ifdef DEBUG
++static void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
++ struct pxp_config_data *pxp_conf)
++{
++ dev_info(fb_data->dev, "S0 fmt 0x%x",
++ pxp_conf->s0_param.pixel_fmt);
++ dev_info(fb_data->dev, "S0 width 0x%x",
++ pxp_conf->s0_param.width);
++ dev_info(fb_data->dev, "S0 height 0x%x",
++ pxp_conf->s0_param.height);
++ dev_info(fb_data->dev, "S0 ckey 0x%x",
++ pxp_conf->s0_param.color_key);
++ dev_info(fb_data->dev, "S0 ckey en 0x%x",
++ pxp_conf->s0_param.color_key_enable);
++
++ dev_info(fb_data->dev, "OL0 combine en 0x%x",
++ pxp_conf->ol_param[0].combine_enable);
++ dev_info(fb_data->dev, "OL0 fmt 0x%x",
++ pxp_conf->ol_param[0].pixel_fmt);
++ dev_info(fb_data->dev, "OL0 width 0x%x",
++ pxp_conf->ol_param[0].width);
++ dev_info(fb_data->dev, "OL0 height 0x%x",
++ pxp_conf->ol_param[0].height);
++ dev_info(fb_data->dev, "OL0 ckey 0x%x",
++ pxp_conf->ol_param[0].color_key);
++ dev_info(fb_data->dev, "OL0 ckey en 0x%x",
++ pxp_conf->ol_param[0].color_key_enable);
++ dev_info(fb_data->dev, "OL0 alpha 0x%x",
++ pxp_conf->ol_param[0].global_alpha);
++ dev_info(fb_data->dev, "OL0 alpha en 0x%x",
++ pxp_conf->ol_param[0].global_alpha_enable);
++ dev_info(fb_data->dev, "OL0 local alpha en 0x%x",
++ pxp_conf->ol_param[0].local_alpha_enable);
++
++ dev_info(fb_data->dev, "Out fmt 0x%x",
++ pxp_conf->out_param.pixel_fmt);
++ dev_info(fb_data->dev, "Out width 0x%x",
++ pxp_conf->out_param.width);
++ dev_info(fb_data->dev, "Out height 0x%x",
++ pxp_conf->out_param.height);
++
++ dev_info(fb_data->dev,
++ "drect left 0x%x right 0x%x width 0x%x height 0x%x",
++ pxp_conf->proc_data.drect.left, pxp_conf->proc_data.drect.top,
++ pxp_conf->proc_data.drect.width,
++ pxp_conf->proc_data.drect.height);
++ dev_info(fb_data->dev,
++ "srect left 0x%x right 0x%x width 0x%x height 0x%x",
++ pxp_conf->proc_data.srect.left, pxp_conf->proc_data.srect.top,
++ pxp_conf->proc_data.srect.width,
++ pxp_conf->proc_data.srect.height);
++ dev_info(fb_data->dev, "Scaling en 0x%x", pxp_conf->proc_data.scaling);
++ dev_info(fb_data->dev, "HFlip en 0x%x", pxp_conf->proc_data.hflip);
++ dev_info(fb_data->dev, "VFlip en 0x%x", pxp_conf->proc_data.vflip);
++ dev_info(fb_data->dev, "Rotation 0x%x", pxp_conf->proc_data.rotate);
++ dev_info(fb_data->dev, "BG Color 0x%x", pxp_conf->proc_data.bgcolor);
++}
++
++static void dump_epdc_reg(void)
++{
++ printk(KERN_DEBUG "\n\n");
++ printk(KERN_DEBUG "EPDC_CTRL 0x%x\n", __raw_readl(EPDC_CTRL));
++ printk(KERN_DEBUG "EPDC_WVADDR 0x%x\n", __raw_readl(EPDC_WVADDR));
++ printk(KERN_DEBUG "EPDC_WB_ADDR 0x%x\n", __raw_readl(EPDC_WB_ADDR));
++ printk(KERN_DEBUG "EPDC_RES 0x%x\n", __raw_readl(EPDC_RES));
++ printk(KERN_DEBUG "EPDC_FORMAT 0x%x\n", __raw_readl(EPDC_FORMAT));
++ printk(KERN_DEBUG "EPDC_FIFOCTRL 0x%x\n", __raw_readl(EPDC_FIFOCTRL));
++ printk(KERN_DEBUG "EPDC_UPD_ADDR 0x%x\n", __raw_readl(EPDC_UPD_ADDR));
++ printk(KERN_DEBUG "EPDC_UPD_STRIDE 0x%x\n", __raw_readl(EPDC_UPD_STRIDE));
++ printk(KERN_DEBUG "EPDC_UPD_FIXED 0x%x\n", __raw_readl(EPDC_UPD_FIXED));
++ printk(KERN_DEBUG "EPDC_UPD_CORD 0x%x\n", __raw_readl(EPDC_UPD_CORD));
++ printk(KERN_DEBUG "EPDC_UPD_SIZE 0x%x\n", __raw_readl(EPDC_UPD_SIZE));
++ printk(KERN_DEBUG "EPDC_UPD_CTRL 0x%x\n", __raw_readl(EPDC_UPD_CTRL));
++ printk(KERN_DEBUG "EPDC_TEMP 0x%x\n", __raw_readl(EPDC_TEMP));
++ printk(KERN_DEBUG "EPDC_AUTOWV_LUT 0x%x\n", __raw_readl(EPDC_AUTOWV_LUT));
++ printk(KERN_DEBUG "EPDC_TCE_CTRL 0x%x\n", __raw_readl(EPDC_TCE_CTRL));
++ printk(KERN_DEBUG "EPDC_TCE_SDCFG 0x%x\n", __raw_readl(EPDC_TCE_SDCFG));
++ printk(KERN_DEBUG "EPDC_TCE_GDCFG 0x%x\n", __raw_readl(EPDC_TCE_GDCFG));
++ printk(KERN_DEBUG "EPDC_TCE_HSCAN1 0x%x\n", __raw_readl(EPDC_TCE_HSCAN1));
++ printk(KERN_DEBUG "EPDC_TCE_HSCAN2 0x%x\n", __raw_readl(EPDC_TCE_HSCAN2));
++ printk(KERN_DEBUG "EPDC_TCE_VSCAN 0x%x\n", __raw_readl(EPDC_TCE_VSCAN));
++ printk(KERN_DEBUG "EPDC_TCE_OE 0x%x\n", __raw_readl(EPDC_TCE_OE));
++ printk(KERN_DEBUG "EPDC_TCE_POLARITY 0x%x\n", __raw_readl(EPDC_TCE_POLARITY));
++ printk(KERN_DEBUG "EPDC_TCE_TIMING1 0x%x\n", __raw_readl(EPDC_TCE_TIMING1));
++ printk(KERN_DEBUG "EPDC_TCE_TIMING2 0x%x\n", __raw_readl(EPDC_TCE_TIMING2));
++ printk(KERN_DEBUG "EPDC_TCE_TIMING3 0x%x\n", __raw_readl(EPDC_TCE_TIMING3));
++ printk(KERN_DEBUG "EPDC_PIGEON_CTRL0 0x%x\n", __raw_readl(EPDC_PIGEON_CTRL0));
++ printk(KERN_DEBUG "EPDC_PIGEON_CTRL1 0x%x\n", __raw_readl(EPDC_PIGEON_CTRL1));
++ printk(KERN_DEBUG "EPDC_IRQ_MASK1 0x%x\n", __raw_readl(EPDC_IRQ_MASK1));
++ printk(KERN_DEBUG "EPDC_IRQ_MASK2 0x%x\n", __raw_readl(EPDC_IRQ_MASK2));
++ printk(KERN_DEBUG "EPDC_IRQ1 0x%x\n", __raw_readl(EPDC_IRQ1));
++ printk(KERN_DEBUG "EPDC_IRQ2 0x%x\n", __raw_readl(EPDC_IRQ2));
++ printk(KERN_DEBUG "EPDC_IRQ_MASK 0x%x\n", __raw_readl(EPDC_IRQ_MASK));
++ printk(KERN_DEBUG "EPDC_IRQ 0x%x\n", __raw_readl(EPDC_IRQ));
++ printk(KERN_DEBUG "EPDC_STATUS_LUTS 0x%x\n", __raw_readl(EPDC_STATUS_LUTS));
++ printk(KERN_DEBUG "EPDC_STATUS_LUTS2 0x%x\n", __raw_readl(EPDC_STATUS_LUTS2));
++ printk(KERN_DEBUG "EPDC_STATUS_NEXTLUT 0x%x\n", __raw_readl(EPDC_STATUS_NEXTLUT));
++ printk(KERN_DEBUG "EPDC_STATUS_COL1 0x%x\n", __raw_readl(EPDC_STATUS_COL));
++ printk(KERN_DEBUG "EPDC_STATUS_COL2 0x%x\n", __raw_readl(EPDC_STATUS_COL2));
++ printk(KERN_DEBUG "EPDC_STATUS 0x%x\n", __raw_readl(EPDC_STATUS));
++ printk(KERN_DEBUG "EPDC_UPD_COL_CORD 0x%x\n", __raw_readl(EPDC_UPD_COL_CORD));
++ printk(KERN_DEBUG "EPDC_UPD_COL_SIZE 0x%x\n", __raw_readl(EPDC_UPD_COL_SIZE));
++ printk(KERN_DEBUG "EPDC_DEBUG 0x%x\n", __raw_readl(EPDC_DEBUG));
++ printk(KERN_DEBUG "EPDC_DEBUG_LUT 0x%x\n", __raw_readl(EPDC_DEBUG_LUT));
++ printk(KERN_DEBUG "EPDC_HIST1_PARAM 0x%x\n", __raw_readl(EPDC_HIST1_PARAM));
++ printk(KERN_DEBUG "EPDC_HIST2_PARAM 0x%x\n", __raw_readl(EPDC_HIST2_PARAM));
++ printk(KERN_DEBUG "EPDC_HIST4_PARAM 0x%x\n", __raw_readl(EPDC_HIST4_PARAM));
++ printk(KERN_DEBUG "EPDC_HIST8_PARAM0 0x%x\n", __raw_readl(EPDC_HIST8_PARAM0));
++ printk(KERN_DEBUG "EPDC_HIST8_PARAM1 0x%x\n", __raw_readl(EPDC_HIST8_PARAM1));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM0 0x%x\n", __raw_readl(EPDC_HIST16_PARAM0));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM1 0x%x\n", __raw_readl(EPDC_HIST16_PARAM1));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM2 0x%x\n", __raw_readl(EPDC_HIST16_PARAM2));
++ printk(KERN_DEBUG "EPDC_HIST16_PARAM3 0x%x\n", __raw_readl(EPDC_HIST16_PARAM3));
++ printk(KERN_DEBUG "EPDC_GPIO 0x%x\n", __raw_readl(EPDC_GPIO));
++ printk(KERN_DEBUG "EPDC_VERSION 0x%x\n", __raw_readl(EPDC_VERSION));
++ printk(KERN_DEBUG "\n\n");
++}
++
++static void dump_update_data(struct device *dev,
++ struct update_data_list *upd_data_list)
++{
++ dev_info(dev,
++ "X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
++ "LUT = %d, Coll Mask = 0x%llx, order = %d\n",
++ upd_data_list->update_desc->upd_data.update_region.left,
++ upd_data_list->update_desc->upd_data.update_region.top,
++ upd_data_list->update_desc->upd_data.update_region.width,
++ upd_data_list->update_desc->upd_data.update_region.height,
++ upd_data_list->update_desc->upd_data.waveform_mode,
++ upd_data_list->lut_num,
++ upd_data_list->collision_mask,
++ upd_data_list->update_desc->update_order);
++}
++
++static void dump_collision_list(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_data_list *plist;
++
++ dev_info(fb_data->dev, "Collision List:\n");
++ if (list_empty(&fb_data->upd_buf_collision_list))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_buf_collision_list, list) {
++ dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
++ (u32)plist->virt_addr, plist->phys_addr);
++ dump_update_data(fb_data->dev, plist);
++ }
++}
++
++static void dump_free_list(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_data_list *plist;
++
++ dev_info(fb_data->dev, "Free List:\n");
++ if (list_empty(&fb_data->upd_buf_free_list))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
++ dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
++ (u32)plist->virt_addr, plist->phys_addr);
++}
++
++static void dump_queue(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_data_list *plist;
++
++ dev_info(fb_data->dev, "Queue:\n");
++ if (list_empty(&fb_data->upd_buf_queue))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_buf_queue, list) {
++ dev_info(fb_data->dev, "Virt Addr = 0x%x, Phys Addr = 0x%x ",
++ (u32)plist->virt_addr, plist->phys_addr);
++ dump_update_data(fb_data->dev, plist);
++ }
++}
++
++static void dump_desc_data(struct device *dev,
++ struct update_desc_list *upd_desc_list)
++{
++ dev_info(dev,
++ "X = %d, Y = %d, Width = %d, Height = %d, WaveMode = %d, "
++ "order = %d\n",
++ upd_desc_list->upd_data.update_region.left,
++ upd_desc_list->upd_data.update_region.top,
++ upd_desc_list->upd_data.update_region.width,
++ upd_desc_list->upd_data.update_region.height,
++ upd_desc_list->upd_data.waveform_mode,
++ upd_desc_list->update_order);
++}
++
++static void dump_pending_list(struct mxc_epdc_fb_data *fb_data)
++{
++ struct update_desc_list *plist;
++
++ dev_info(fb_data->dev, "Queue:\n");
++ if (list_empty(&fb_data->upd_pending_list))
++ dev_info(fb_data->dev, "Empty");
++ list_for_each_entry(plist, &fb_data->upd_pending_list, list)
++ dump_desc_data(fb_data->dev, plist);
++}
++
++static void dump_all_updates(struct mxc_epdc_fb_data *fb_data)
++{
++ dump_free_list(fb_data);
++ dump_queue(fb_data);
++ dump_collision_list(fb_data);
++ dev_info(fb_data->dev, "Current update being processed:\n");
++ if (fb_data->cur_update == NULL)
++ dev_info(fb_data->dev, "No current update\n");
++ else
++ dump_update_data(fb_data->dev, fb_data->cur_update);
++}
++#else
++static inline void dump_pxp_config(struct mxc_epdc_fb_data *fb_data,
++ struct pxp_config_data *pxp_conf) {}
++static inline void dump_epdc_reg(void) {}
++static inline void dump_update_data(struct device *dev,
++ struct update_data_list *upd_data_list) {}
++static inline void dump_collision_list(struct mxc_epdc_fb_data *fb_data) {}
++static inline void dump_free_list(struct mxc_epdc_fb_data *fb_data) {}
++static inline void dump_queue(struct mxc_epdc_fb_data *fb_data) {}
++static inline void dump_all_updates(struct mxc_epdc_fb_data *fb_data) {}
++
++#endif
++
++
++/********************************************************
++ * Start Low-Level EPDC Functions
++ ********************************************************/
++
++static inline void epdc_lut_complete_intr(int rev, u32 lut_num, bool enable)
++{
++ if (rev < 20) {
++ if (enable)
++ __raw_writel(1 << lut_num, EPDC_IRQ_MASK_SET);
++ else
++ __raw_writel(1 << lut_num, EPDC_IRQ_MASK_CLEAR);
++ } else {
++ if (enable) {
++ if (lut_num < 32)
++ __raw_writel(1 << lut_num, EPDC_IRQ_MASK1_SET);
++ else
++ __raw_writel(1 << (lut_num - 32),
++ EPDC_IRQ_MASK2_SET);
++ } else {
++ if (lut_num < 32)
++ __raw_writel(1 << lut_num,
++ EPDC_IRQ_MASK1_CLEAR);
++ else
++ __raw_writel(1 << (lut_num - 32),
++ EPDC_IRQ_MASK2_CLEAR);
++ }
++ }
++}
++
++static inline void epdc_working_buf_intr(bool enable)
++{
++ if (enable)
++ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_SET);
++ else
++ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ, EPDC_IRQ_MASK_CLEAR);
++}
++
++static inline void epdc_clear_working_buf_irq(void)
++{
++ __raw_writel(EPDC_IRQ_WB_CMPLT_IRQ | EPDC_IRQ_LUT_COL_IRQ,
++ EPDC_IRQ_CLEAR);
++}
++
++static inline void epdc_eof_intr(bool enable)
++{
++ if (enable)
++ __raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_SET);
++ else
++ __raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_MASK_CLEAR);
++}
++
++static inline void epdc_clear_eof_irq(void)
++{
++ __raw_writel(EPDC_IRQ_FRAME_END_IRQ, EPDC_IRQ_CLEAR);
++}
++
++static inline bool epdc_signal_eof(void)
++{
++ return (__raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ)
++ & EPDC_IRQ_FRAME_END_IRQ) ? true : false;
++}
++
++static inline void epdc_set_temp(u32 temp)
++{
++ __raw_writel(temp, EPDC_TEMP);
++}
++
++static inline void epdc_set_screen_res(u32 width, u32 height)
++{
++ u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width;
++ __raw_writel(val, EPDC_RES);
++}
++
++static inline void epdc_set_update_addr(u32 addr)
++{
++ __raw_writel(addr, EPDC_UPD_ADDR);
++}
++
++static inline void epdc_set_update_coord(u32 x, u32 y)
++{
++ u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x;
++ __raw_writel(val, EPDC_UPD_CORD);
++}
++
++static inline void epdc_set_update_dimensions(u32 width, u32 height)
++{
++ u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width;
++ __raw_writel(val, EPDC_UPD_SIZE);
++}
++
++static void epdc_set_update_waveform(struct mxcfb_waveform_modes *wv_modes)
++{
++ u32 val;
++
++ /* Configure the auto-waveform look-up table based on waveform modes */
++
++ /* Entry 1 = DU, 2 = GC4, 3 = GC8, etc. */
++ val = (wv_modes->mode_du << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (0 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_du << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (1 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc4 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (2 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc8 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (3 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc16 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (4 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++ val = (wv_modes->mode_gc32 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (5 << EPDC_AUTOWV_LUT_ADDR_OFFSET);
++ __raw_writel(val, EPDC_AUTOWV_LUT);
++}
++
++static void epdc_set_update_stride(u32 stride)
++{
++ __raw_writel(stride, EPDC_UPD_STRIDE);
++}
++
++static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode,
++ bool use_dry_run, bool use_test_mode, u32 np_val)
++{
++ u32 reg_val = 0;
++
++ if (use_test_mode) {
++ reg_val |=
++ ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) &
++ EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN;
++
++ __raw_writel(reg_val, EPDC_UPD_FIXED);
++
++ reg_val = EPDC_UPD_CTRL_USE_FIXED;
++ } else {
++ __raw_writel(reg_val, EPDC_UPD_FIXED);
++ }
++
++ if (waveform_mode == WAVEFORM_MODE_AUTO)
++ reg_val |= EPDC_UPD_CTRL_AUTOWV;
++ else
++ reg_val |= ((waveform_mode <<
++ EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) &
++ EPDC_UPD_CTRL_WAVEFORM_MODE_MASK);
++
++ reg_val |= (use_dry_run ? EPDC_UPD_CTRL_DRY_RUN : 0) |
++ ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) &
++ EPDC_UPD_CTRL_LUT_SEL_MASK) |
++ update_mode;
++
++ __raw_writel(reg_val, EPDC_UPD_CTRL);
++}
++
++static inline bool epdc_is_lut_complete(int rev, u32 lut_num)
++{
++ u32 val;
++ bool is_compl;
++ if (rev < 20) {
++ val = __raw_readl(EPDC_IRQ);
++ is_compl = val & (1 << lut_num) ? true : false;
++ } else if (lut_num < 32) {
++ val = __raw_readl(EPDC_IRQ1);
++ is_compl = val & (1 << lut_num) ? true : false;
++ } else {
++ val = __raw_readl(EPDC_IRQ2);
++ is_compl = val & (1 << (lut_num - 32)) ? true : false;
++ }
++
++ return is_compl;
++}
++
++static inline void epdc_clear_lut_complete_irq(int rev, u32 lut_num)
++{
++ if (rev < 20)
++ __raw_writel(1 << lut_num, EPDC_IRQ_CLEAR);
++ else if (lut_num < 32)
++ __raw_writel(1 << lut_num, EPDC_IRQ1_CLEAR);
++ else
++ __raw_writel(1 << (lut_num - 32), EPDC_IRQ2_CLEAR);
++}
++
++static inline bool epdc_is_lut_active(u32 lut_num)
++{
++ u32 val;
++ bool is_active;
++
++ if (lut_num < 32) {
++ val = __raw_readl(EPDC_STATUS_LUTS);
++ is_active = val & (1 << lut_num) ? true : false;
++ } else {
++ val = __raw_readl(EPDC_STATUS_LUTS2);
++ is_active = val & (1 << (lut_num - 32)) ? true : false;
++ }
++
++ return is_active;
++}
++
++static inline bool epdc_any_luts_active(int rev)
++{
++ bool any_active;
++
++ if (rev < 20)
++ any_active = __raw_readl(EPDC_STATUS_LUTS) ? true : false;
++ else
++ any_active = (__raw_readl(EPDC_STATUS_LUTS) |
++ __raw_readl(EPDC_STATUS_LUTS2)) ? true : false;
++
++ return any_active;
++}
++
++static inline bool epdc_any_luts_available(void)
++{
++ bool luts_available =
++ (__raw_readl(EPDC_STATUS_NEXTLUT) &
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID) ? true : false;
++ return luts_available;
++}
++
++static inline int epdc_get_next_lut(void)
++{
++ u32 val =
++ __raw_readl(EPDC_STATUS_NEXTLUT) &
++ EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK;
++ return val;
++}
++
++static int epdc_choose_next_lut(int rev, int *next_lut)
++{
++ u64 luts_status, unprocessed_luts, used_luts;
++ /* Available LUTs are reduced to 16 in 5-bit waveform mode */
++ bool format_p5n = ((__raw_readl(EPDC_FORMAT) &
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK) ==
++ EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N);
++
++ luts_status = __raw_readl(EPDC_STATUS_LUTS);
++ if ((rev < 20) || format_p5n)
++ luts_status &= 0xFFFF;
++ else
++ luts_status |= ((u64)__raw_readl(EPDC_STATUS_LUTS2) << 32);
++
++ if (rev < 20) {
++ unprocessed_luts = __raw_readl(EPDC_IRQ) & 0xFFFF;
++ } else {
++ unprocessed_luts = __raw_readl(EPDC_IRQ1) |
++ ((u64)__raw_readl(EPDC_IRQ2) << 32);
++ if (format_p5n)
++ unprocessed_luts &= 0xFFFF;
++ }
++
++ /*
++ * Note on unprocessed_luts: There is a race condition
++ * where a LUT completes, but has not been processed by
++ * IRQ handler workqueue, and then a new update request
++ * attempts to use that LUT. We prevent that here by
++ * ensuring that the LUT we choose doesn't have its IRQ
++ * bit set (indicating it has completed but not yet been
++ * processed).
++ */
++ used_luts = luts_status | unprocessed_luts;
++
++ /*
++ * Selecting a LUT to minimize incidence of TCE Underrun Error
++ * --------------------------------------------------------
++ * We want to find the lowest order LUT that is of greater
++ * order than all other active LUTs. If highest order LUT
++ * is active, then we want to choose the lowest order
++ * available LUT.
++ *
++ * NOTE: For EPDC version 2.0 and later, TCE Underrun error
++ * bug is fixed, so it doesn't matter which LUT is used.
++ */
++
++ if ((rev < 20) || format_p5n) {
++ *next_lut = fls64(used_luts);
++ if (*next_lut > 15)
++ *next_lut = ffz(used_luts);
++ } else {
++ if ((u32)used_luts != ~0UL)
++ *next_lut = ffz((u32)used_luts);
++ else if ((u32)(used_luts >> 32) != ~0UL)
++ *next_lut = ffz((u32)(used_luts >> 32)) + 32;
++ else
++ *next_lut = INVALID_LUT;
++ }
++
++ if (used_luts & 0x8000)
++ return 1;
++ else
++ return 0;
++}
++
++static inline bool epdc_is_working_buffer_busy(void)
++{
++ u32 val = __raw_readl(EPDC_STATUS);
++ bool is_busy = (val & EPDC_STATUS_WB_BUSY) ? true : false;
++
++ return is_busy;
++}
++
++static inline bool epdc_is_working_buffer_complete(void)
++{
++ u32 val = __raw_readl(EPDC_IRQ);
++ bool is_compl = (val & EPDC_IRQ_WB_CMPLT_IRQ) ? true : false;
++
++ return is_compl;
++}
++
++static inline bool epdc_is_lut_cancelled(void)
++{
++ u32 val = __raw_readl(EPDC_STATUS);
++ bool is_void = (val & EPDC_STATUS_UPD_VOID) ? true : false;
++
++ return is_void;
++}
++
++static inline bool epdc_is_collision(void)
++{
++ u32 val = __raw_readl(EPDC_IRQ);
++ return (val & EPDC_IRQ_LUT_COL_IRQ) ? true : false;
++}
++
++static inline u64 epdc_get_colliding_luts(int rev)
++{
++ u32 val = __raw_readl(EPDC_STATUS_COL);
++ if (rev >= 20)
++ val |= (u64)__raw_readl(EPDC_STATUS_COL2) << 32;
++ return val;
++}
++
++static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end,
++ u32 hsync_width, u32 hsync_line_length)
++{
++ u32 reg_val =
++ ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) &
++ EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK)
++ | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) &
++ EPDC_TCE_HSCAN1_LINE_SYNC_MASK);
++ __raw_writel(reg_val, EPDC_TCE_HSCAN1);
++
++ reg_val =
++ ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) &
++ EPDC_TCE_HSCAN2_LINE_BEGIN_MASK)
++ | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) &
++ EPDC_TCE_HSCAN2_LINE_END_MASK);
++ __raw_writel(reg_val, EPDC_TCE_HSCAN2);
++}
++
++static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end,
++ u32 vsync_width)
++{
++ u32 reg_val =
++ ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) &
++ EPDC_TCE_VSCAN_FRAME_BEGIN_MASK)
++ | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) &
++ EPDC_TCE_VSCAN_FRAME_END_MASK)
++ | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) &
++ EPDC_TCE_VSCAN_FRAME_SYNC_MASK);
++ __raw_writel(reg_val, EPDC_TCE_VSCAN);
++}
++
++static void epdc_init_settings(struct mxc_epdc_fb_data *fb_data)
++{
++ struct imx_epdc_fb_mode *epdc_mode = fb_data->cur_mode;
++ struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
++ u32 reg_val;
++ int num_ce;
++ int i;
++
++ /* Enable clocks to access EPDC regs */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++
++ /* Reset */
++ __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_SET);
++ while (!(__raw_readl(EPDC_CTRL) & EPDC_CTRL_CLKGATE))
++ ;
++ __raw_writel(EPDC_CTRL_SFTRST, EPDC_CTRL_CLEAR);
++
++ /* Enable clock gating (clear to enable) */
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
++ while (__raw_readl(EPDC_CTRL) & (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
++ ;
++
++ /* EPDC_CTRL */
++ reg_val = __raw_readl(EPDC_CTRL);
++ reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK;
++ reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP;
++ reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK;
++ reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP;
++ __raw_writel(reg_val, EPDC_CTRL_SET);
++
++ /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */
++ reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT
++ | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N
++ | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) &
++ EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK);
++ __raw_writel(reg_val, EPDC_FORMAT);
++
++ /* EPDC_FIFOCTRL (disabled) */
++ reg_val =
++ ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) &
++ EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK)
++ | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) &
++ EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK)
++ | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) &
++ EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK);
++ __raw_writel(reg_val, EPDC_FIFOCTRL);
++
++ /* EPDC_TEMP - Use default temp to get index */
++ epdc_set_temp(mxc_epdc_fb_get_temp_index(fb_data, DEFAULT_TEMP));
++
++ /* EPDC_RES */
++ epdc_set_screen_res(epdc_mode->vmode->xres, epdc_mode->vmode->yres);
++
++ /* EPDC_AUTOWV_LUT */
++ /* Initialize all auto-wavefrom look-up values to 2 - GC16 */
++ for (i = 0; i < 8; i++)
++ __raw_writel((2 << EPDC_AUTOWV_LUT_DATA_OFFSET) |
++ (i << EPDC_AUTOWV_LUT_ADDR_OFFSET), EPDC_AUTOWV_LUT);
++
++ /*
++ * EPDC_TCE_CTRL
++ * VSCAN_HOLDOFF = 4
++ * VCOM_MODE = MANUAL
++ * VCOM_VAL = 0
++ * DDR_MODE = DISABLED
++ * LVDS_MODE_CE = DISABLED
++ * LVDS_MODE = DISABLED
++ * DUAL_SCAN = DISABLED
++ * SDDO_WIDTH = 8bit
++ * PIXELS_PER_SDCLK = 4
++ */
++ reg_val =
++ ((epdc_mode->vscan_holdoff << EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) &
++ EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK)
++ | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4;
++ __raw_writel(reg_val, EPDC_TCE_CTRL);
++
++ /* EPDC_TCE_HSCAN */
++ epdc_set_horizontal_timing(screeninfo->left_margin,
++ screeninfo->right_margin,
++ screeninfo->hsync_len,
++ screeninfo->hsync_len);
++
++ /* EPDC_TCE_VSCAN */
++ epdc_set_vertical_timing(screeninfo->upper_margin,
++ screeninfo->lower_margin,
++ screeninfo->vsync_len);
++
++ /* EPDC_TCE_OE */
++ reg_val =
++ ((epdc_mode->sdoed_width << EPDC_TCE_OE_SDOED_WIDTH_OFFSET) &
++ EPDC_TCE_OE_SDOED_WIDTH_MASK)
++ | ((epdc_mode->sdoed_delay << EPDC_TCE_OE_SDOED_DLY_OFFSET) &
++ EPDC_TCE_OE_SDOED_DLY_MASK)
++ | ((epdc_mode->sdoez_width << EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) &
++ EPDC_TCE_OE_SDOEZ_WIDTH_MASK)
++ | ((epdc_mode->sdoez_delay << EPDC_TCE_OE_SDOEZ_DLY_OFFSET) &
++ EPDC_TCE_OE_SDOEZ_DLY_MASK);
++ __raw_writel(reg_val, EPDC_TCE_OE);
++
++ /* EPDC_TCE_TIMING1 */
++ __raw_writel(0x0, EPDC_TCE_TIMING1);
++
++ /* EPDC_TCE_TIMING2 */
++ reg_val =
++ ((epdc_mode->gdclk_hp_offs << EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) &
++ EPDC_TCE_TIMING2_GDCLK_HP_MASK)
++ | ((epdc_mode->gdsp_offs << EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) &
++ EPDC_TCE_TIMING2_GDSP_OFFSET_MASK);
++ __raw_writel(reg_val, EPDC_TCE_TIMING2);
++
++ /* EPDC_TCE_TIMING3 */
++ reg_val =
++ ((epdc_mode->gdoe_offs << EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) &
++ EPDC_TCE_TIMING3_GDOE_OFFSET_MASK)
++ | ((epdc_mode->gdclk_offs << EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) &
++ EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK);
++ __raw_writel(reg_val, EPDC_TCE_TIMING3);
++
++ /*
++ * EPDC_TCE_SDCFG
++ * SDCLK_HOLD = 1
++ * SDSHR = 1
++ * NUM_CE = 1
++ * SDDO_REFORMAT = FLIP_PIXELS
++ * SDDO_INVERT = DISABLED
++ * PIXELS_PER_CE = display horizontal resolution
++ */
++ num_ce = epdc_mode->num_ce;
++ if (num_ce == 0)
++ num_ce = 1;
++ reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR
++ | ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) &
++ EPDC_TCE_SDCFG_NUM_CE_MASK)
++ | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS
++ | ((epdc_mode->vmode->xres/num_ce << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) &
++ EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK);
++ __raw_writel(reg_val, EPDC_TCE_SDCFG);
++
++ /*
++ * EPDC_TCE_GDCFG
++ * GDRL = 1
++ * GDOE_MODE = 0;
++ * GDSP_MODE = 0;
++ */
++ reg_val = EPDC_TCE_SDCFG_GDRL;
++ __raw_writel(reg_val, EPDC_TCE_GDCFG);
++
++ /*
++ * EPDC_TCE_POLARITY
++ * SDCE_POL = ACTIVE LOW
++ * SDLE_POL = ACTIVE HIGH
++ * SDOE_POL = ACTIVE HIGH
++ * GDOE_POL = ACTIVE HIGH
++ * GDSP_POL = ACTIVE LOW
++ */
++ reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH
++ | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH
++ | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH;
++ __raw_writel(reg_val, EPDC_TCE_POLARITY);
++
++ /* EPDC_IRQ_MASK */
++ __raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_MASK);
++
++ /*
++ * EPDC_GPIO
++ * PWRCOM = ?
++ * PWRCTRL = ?
++ * BDR = ?
++ */
++ reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK)
++ | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK);
++ __raw_writel(reg_val, EPDC_GPIO);
++
++ __raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR);
++ __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR);
++ __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR_TCE);
++
++ /* Disable clock */
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++}
++
++static void epdc_powerup(struct mxc_epdc_fb_data *fb_data)
++{
++ int ret = 0;
++ mutex_lock(&fb_data->power_mutex);
++
++ /*
++ * If power down request is pending, clear
++ * powering_down to cancel the request.
++ */
++ if (fb_data->powering_down)
++ fb_data->powering_down = false;
++
++ if (fb_data->power_state == POWER_STATE_ON) {
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ dev_dbg(fb_data->dev, "EPDC Powerup\n");
++
++ fb_data->updates_active = true;
++
++ /* Enable the v3p3 regulator */
++ ret = regulator_enable(fb_data->v3p3_regulator);
++ if (IS_ERR((void *)ret)) {
++ dev_err(fb_data->dev, "Unable to enable V3P3 regulator."
++ "err = 0x%x\n", ret);
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ msleep(1);
++
++ pm_runtime_get_sync(fb_data->dev);
++
++ /* Enable clocks to EPDC */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_CLEAR);
++
++ /* Enable power to the EPD panel */
++ ret = regulator_enable(fb_data->display_regulator);
++ if (IS_ERR((void *)ret)) {
++ dev_err(fb_data->dev, "Unable to enable DISPLAY regulator."
++ "err = 0x%x\n", ret);
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++ ret = regulator_enable(fb_data->vcom_regulator);
++ if (IS_ERR((void *)ret)) {
++ dev_err(fb_data->dev, "Unable to enable VCOM regulator."
++ "err = 0x%x\n", ret);
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ fb_data->power_state = POWER_STATE_ON;
++
++ mutex_unlock(&fb_data->power_mutex);
++}
++
++static void epdc_powerdown(struct mxc_epdc_fb_data *fb_data)
++{
++ mutex_lock(&fb_data->power_mutex);
++
++ /* If powering_down has been cleared, a powerup
++ * request is pre-empting this powerdown request.
++ */
++ if (!fb_data->powering_down
++ || (fb_data->power_state == POWER_STATE_OFF)) {
++ mutex_unlock(&fb_data->power_mutex);
++ return;
++ }
++
++ dev_dbg(fb_data->dev, "EPDC Powerdown\n");
++
++ /* Disable power to the EPD panel */
++ regulator_disable(fb_data->vcom_regulator);
++ regulator_disable(fb_data->display_regulator);
++
++ /* Disable clocks to EPDC */
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++
++ pm_runtime_put_sync_suspend(fb_data->dev);
++
++ /* turn off the V3p3 */
++ regulator_disable(fb_data->v3p3_regulator);
++
++ fb_data->power_state = POWER_STATE_OFF;
++ fb_data->powering_down = false;
++
++ if (fb_data->wait_for_powerdown) {
++ fb_data->wait_for_powerdown = false;
++ complete(&fb_data->powerdown_compl);
++ }
++
++ mutex_unlock(&fb_data->power_mutex);
++}
++
++static void epdc_init_sequence(struct mxc_epdc_fb_data *fb_data)
++{
++ /* Initialize EPDC, passing pointer to EPDC registers */
++ epdc_init_settings(fb_data);
++ fb_data->in_init = true;
++ epdc_powerup(fb_data);
++ draw_mode0(fb_data);
++ /* Force power down event */
++ fb_data->powering_down = true;
++ epdc_powerdown(fb_data);
++ fb_data->updates_active = false;
++}
++
++static int mxc_epdc_fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
++{
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++
++ if (offset < info->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = info->fix.smem_len - offset;
++ vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else
++ return -EINVAL;
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(info->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
++ return 0;
++}
++
++static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf->length;
++ return chan << bf->offset;
++}
++
++static int mxc_epdc_fb_setcolreg(u_int regno, u_int red, u_int green,
++ u_int blue, u_int transp, struct fb_info *info)
++{
++ unsigned int val;
++ int ret = 1;
++
++ /*
++ * If greyscale is true, then we convert the RGB value
++ * to greyscale no matter what visual we are using.
++ */
++ if (info->var.grayscale)
++ red = green = blue = (19595 * red + 38470 * green +
++ 7471 * blue) >> 16;
++ switch (info->fix.visual) {
++ case FB_VISUAL_TRUECOLOR:
++ /*
++ * 16-bit True Colour. We encode the RGB value
++ * according to the RGB bitfield information.
++ */
++ if (regno < 16) {
++ u32 *pal = info->pseudo_palette;
++
++ val = _chan_to_field(red, &info->var.red);
++ val |= _chan_to_field(green, &info->var.green);
++ val |= _chan_to_field(blue, &info->var.blue);
++
++ pal[regno] = val;
++ ret = 0;
++ }
++ break;
++
++ case FB_VISUAL_STATIC_PSEUDOCOLOR:
++ case FB_VISUAL_PSEUDOCOLOR:
++ break;
++ }
++
++ return ret;
++}
++
++static int mxc_epdc_fb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
++{
++ int count, index, r;
++ u16 *red, *green, *blue, *transp;
++ u16 trans = 0xffff;
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ int i;
++
++ dev_dbg(fb_data->dev, "setcmap\n");
++
++ if (info->fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) {
++ /* Only support an 8-bit, 256 entry lookup */
++ if (cmap->len != 256)
++ return 1;
++
++ mxc_epdc_fb_flush_updates(fb_data);
++
++ mutex_lock(&fb_data->pxp_mutex);
++ /*
++ * Store colormap in pxp_conf structure for later transmit
++ * to PxP during update process to convert gray pixels.
++ *
++ * Since red=blue=green for pseudocolor visuals, we can
++ * just use red values.
++ */
++ for (i = 0; i < 256; i++)
++ fb_data->pxp_conf.proc_data.lut_map[i] = cmap->red[i] & 0xFF;
++
++ fb_data->pxp_conf.proc_data.lut_map_updated = true;
++
++ mutex_unlock(&fb_data->pxp_mutex);
++ } else {
++ red = cmap->red;
++ green = cmap->green;
++ blue = cmap->blue;
++ transp = cmap->transp;
++ index = cmap->start;
++
++ for (count = 0; count < cmap->len; count++) {
++ if (transp)
++ trans = *transp++;
++ r = mxc_epdc_fb_setcolreg(index++, *red++, *green++, *blue++,
++ trans, info);
++ if (r != 0)
++ return r;
++ }
++ }
++
++ return 0;
++}
++
++static void adjust_coordinates(u32 xres, u32 yres, u32 rotation,
++ struct mxcfb_rect *update_region, struct mxcfb_rect *adj_update_region)
++{
++ u32 temp;
++
++ /* If adj_update_region == NULL, pass result back in update_region */
++ /* If adj_update_region == valid, use it to pass back result */
++ if (adj_update_region)
++ switch (rotation) {
++ case FB_ROTATE_UR:
++ adj_update_region->top = update_region->top;
++ adj_update_region->left = update_region->left;
++ adj_update_region->width = update_region->width;
++ adj_update_region->height = update_region->height;
++ break;
++ case FB_ROTATE_CW:
++ adj_update_region->top = update_region->left;
++ adj_update_region->left = yres -
++ (update_region->top + update_region->height);
++ adj_update_region->width = update_region->height;
++ adj_update_region->height = update_region->width;
++ break;
++ case FB_ROTATE_UD:
++ adj_update_region->width = update_region->width;
++ adj_update_region->height = update_region->height;
++ adj_update_region->top = yres -
++ (update_region->top + update_region->height);
++ adj_update_region->left = xres -
++ (update_region->left + update_region->width);
++ break;
++ case FB_ROTATE_CCW:
++ adj_update_region->left = update_region->top;
++ adj_update_region->top = xres -
++ (update_region->left + update_region->width);
++ adj_update_region->width = update_region->height;
++ adj_update_region->height = update_region->width;
++ break;
++ }
++ else
++ switch (rotation) {
++ case FB_ROTATE_UR:
++ /* No adjustment needed */
++ break;
++ case FB_ROTATE_CW:
++ temp = update_region->top;
++ update_region->top = update_region->left;
++ update_region->left = yres -
++ (temp + update_region->height);
++ temp = update_region->width;
++ update_region->width = update_region->height;
++ update_region->height = temp;
++ break;
++ case FB_ROTATE_UD:
++ update_region->top = yres -
++ (update_region->top + update_region->height);
++ update_region->left = xres -
++ (update_region->left + update_region->width);
++ break;
++ case FB_ROTATE_CCW:
++ temp = update_region->left;
++ update_region->left = update_region->top;
++ update_region->top = xres -
++ (temp + update_region->width);
++ temp = update_region->width;
++ update_region->width = update_region->height;
++ update_region->height = temp;
++ break;
++ }
++}
++
++/*
++ * Set fixed framebuffer parameters based on variable settings.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxc_epdc_fb_set_fix(struct fb_info *info)
++{
++ struct fb_fix_screeninfo *fix = &info->fix;
++ struct fb_var_screeninfo *var = &info->var;
++
++ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
++
++ fix->type = FB_TYPE_PACKED_PIXELS;
++ fix->accel = FB_ACCEL_NONE;
++ if (var->grayscale)
++ fix->visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
++ else
++ fix->visual = FB_VISUAL_TRUECOLOR;
++ fix->xpanstep = 1;
++ fix->ypanstep = 1;
++
++ return 0;
++}
++
++/*
++ * This routine actually sets the video mode. It's in here where we
++ * the hardware state info->par and fix which can be affected by the
++ * change in par. For this driver it doesn't do much.
++ *
++ */
++static int mxc_epdc_fb_set_par(struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
++ struct pxp_proc_data *proc_data = &pxp_conf->proc_data;
++ struct fb_var_screeninfo *screeninfo = &fb_data->info.var;
++ struct imx_epdc_fb_mode *epdc_modes = fb_data->pdata->epdc_mode;
++ int i;
++ int ret;
++ __u32 xoffset_old, yoffset_old;
++
++ /*
++ * Can't change the FB parameters until current updates have completed.
++ * This function returns when all active updates are done.
++ */
++ mxc_epdc_fb_flush_updates(fb_data);
++
++ mutex_lock(&fb_data->queue_mutex);
++ /*
++ * Set all screeninfo except for xoffset/yoffset
++ * Subsequent call to pan_display will handle those.
++ */
++ xoffset_old = fb_data->epdc_fb_var.xoffset;
++ yoffset_old = fb_data->epdc_fb_var.yoffset;
++ fb_data->epdc_fb_var = *screeninfo;
++ fb_data->epdc_fb_var.xoffset = xoffset_old;
++ fb_data->epdc_fb_var.yoffset = yoffset_old;
++ mutex_unlock(&fb_data->queue_mutex);
++
++ mutex_lock(&fb_data->pxp_mutex);
++
++ /*
++ * Update PxP config data (used to process FB regions for updates)
++ * based on FB info and processing tasks required
++ */
++
++ /* Initialize non-channel-specific PxP parameters */
++ proc_data->drect.left = proc_data->srect.left = 0;
++ proc_data->drect.top = proc_data->srect.top = 0;
++ proc_data->drect.width = proc_data->srect.width = screeninfo->xres;
++ proc_data->drect.height = proc_data->srect.height = screeninfo->yres;
++ proc_data->scaling = 0;
++ proc_data->hflip = 0;
++ proc_data->vflip = 0;
++ proc_data->rotate = screeninfo->rotate;
++ proc_data->bgcolor = 0;
++ proc_data->overlay_state = 0;
++ proc_data->lut_transform = PXP_LUT_NONE;
++
++ /*
++ * configure S0 channel parameters
++ * Parameters should match FB format/width/height
++ */
++ if (screeninfo->grayscale)
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_GREY;
++ else {
++ switch (screeninfo->bits_per_pixel) {
++ case 16:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++ break;
++ case 24:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB24;
++ break;
++ case 32:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB32;
++ break;
++ default:
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++ break;
++ }
++ }
++ pxp_conf->s0_param.width = screeninfo->xres_virtual;
++ pxp_conf->s0_param.height = screeninfo->yres;
++ pxp_conf->s0_param.color_key = -1;
++ pxp_conf->s0_param.color_key_enable = false;
++
++ /*
++ * Initialize Output channel parameters
++ * Output is Y-only greyscale
++ * Output width/height will vary based on update region size
++ */
++ pxp_conf->out_param.width = screeninfo->xres;
++ pxp_conf->out_param.height = screeninfo->yres;
++ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
++
++ mutex_unlock(&fb_data->pxp_mutex);
++
++ /*
++ * If HW not yet initialized, check to see if we are being sent
++ * an initialization request.
++ */
++ if (!fb_data->hw_ready) {
++ struct fb_videomode mode;
++ u32 xres_temp;
++
++ fb_var_to_videomode(&mode, screeninfo);
++
++ /* When comparing requested fb mode,
++ we need to use unrotated dimensions */
++ if ((screeninfo->rotate == FB_ROTATE_CW) ||
++ (screeninfo->rotate == FB_ROTATE_CCW)) {
++ xres_temp = mode.xres;
++ mode.xres = mode.yres;
++ mode.yres = xres_temp;
++ }
++
++ /*
++ * If requested video mode does not match current video
++ * mode, search for a matching panel.
++ */
++ if (fb_data->cur_mode &&
++ !fb_mode_is_equal(fb_data->cur_mode->vmode,
++ &mode)) {
++ bool found_match = false;
++
++ /* Match videomode against epdc modes */
++ for (i = 0; i < fb_data->pdata->num_modes; i++) {
++ if (!fb_mode_is_equal(epdc_modes[i].vmode,
++ &mode))
++ continue;
++ fb_data->cur_mode = &epdc_modes[i];
++ found_match = true;
++ break;
++ }
++
++ if (!found_match) {
++ dev_err(fb_data->dev,
++ "Failed to match requested "
++ "video mode\n");
++ return EINVAL;
++ }
++ }
++
++ /* Found a match - Grab timing params */
++ screeninfo->left_margin = mode.left_margin;
++ screeninfo->right_margin = mode.right_margin;
++ screeninfo->upper_margin = mode.upper_margin;
++ screeninfo->lower_margin = mode.lower_margin;
++ screeninfo->hsync_len = mode.hsync_len;
++ screeninfo->vsync_len = mode.vsync_len;
++
++ fb_data->hw_initializing = true;
++
++ /* Initialize EPDC settings and init panel */
++ ret =
++ mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
++ if (ret) {
++ dev_err(fb_data->dev,
++ "Failed to load panel waveform data\n");
++ return ret;
++ }
++ }
++
++ /*
++ * EOF sync delay (in us) should be equal to the vscan holdoff time
++ * VSCAN_HOLDOFF time = (VSCAN_HOLDOFF value + 1) * Vertical lines
++ * Add 25us for additional margin
++ */
++ fb_data->eof_sync_period = (fb_data->cur_mode->vscan_holdoff + 1) *
++ 1000000/(fb_data->cur_mode->vmode->refresh *
++ (fb_data->cur_mode->vmode->upper_margin +
++ fb_data->cur_mode->vmode->yres +
++ fb_data->cur_mode->vmode->lower_margin +
++ fb_data->cur_mode->vmode->vsync_len)) + 25;
++
++ mxc_epdc_fb_set_fix(info);
++
++ return 0;
++}
++
++static int mxc_epdc_fb_check_var(struct fb_var_screeninfo *var,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++
++ if (!var->xres)
++ var->xres = 1;
++ if (!var->yres)
++ var->yres = 1;
++
++ if (var->xres_virtual < var->xoffset + var->xres)
++ var->xres_virtual = var->xoffset + var->xres;
++ if (var->yres_virtual < var->yoffset + var->yres)
++ var->yres_virtual = var->yoffset + var->yres;
++
++ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
++ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8))
++ var->bits_per_pixel = default_bpp;
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ if (var->grayscale != 0) {
++ /*
++ * For 8-bit grayscale, R, G, and B offset are equal.
++ *
++ */
++ var->red.length = 8;
++ var->red.offset = 0;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 0;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ } else {
++ var->red.length = 3;
++ var->red.offset = 5;
++ var->red.msb_right = 0;
++
++ var->green.length = 3;
++ var->green.offset = 2;
++ var->green.msb_right = 0;
++
++ var->blue.length = 2;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ }
++ break;
++ case 16:
++ var->red.length = 5;
++ var->red.offset = 11;
++ var->red.msb_right = 0;
++
++ var->green.length = 6;
++ var->green.offset = 5;
++ var->green.msb_right = 0;
++
++ var->blue.length = 5;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ break;
++ case 24:
++ var->red.length = 8;
++ var->red.offset = 16;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 8;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ break;
++ case 32:
++ var->red.length = 8;
++ var->red.offset = 16;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 8;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 8;
++ var->transp.offset = 24;
++ var->transp.msb_right = 0;
++ break;
++ }
++
++ switch (var->rotate) {
++ case FB_ROTATE_UR:
++ case FB_ROTATE_UD:
++ var->xres = fb_data->native_width;
++ var->yres = fb_data->native_height;
++ break;
++ case FB_ROTATE_CW:
++ case FB_ROTATE_CCW:
++ var->xres = fb_data->native_height;
++ var->yres = fb_data->native_width;
++ break;
++ default:
++ /* Invalid rotation value */
++ var->rotate = 0;
++ dev_dbg(fb_data->dev, "Invalid rotation request\n");
++ return -EINVAL;
++ }
++
++ var->xres_virtual = ALIGN(var->xres, 32);
++ var->yres_virtual = ALIGN(var->yres, 128) * fb_data->num_screens;
++
++ var->height = -1;
++ var->width = -1;
++
++ return 0;
++}
++
++void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ mutex_lock(&fb_data->queue_mutex);
++
++ memcpy(&fb_data->wv_modes, modes, sizeof(struct mxcfb_waveform_modes));
++
++ /* Set flag to ensure that new waveform modes
++ * are programmed into EPDC before next update */
++ fb_data->wv_modes_update = true;
++
++ mutex_unlock(&fb_data->queue_mutex);
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_waveform_modes);
++
++static int mxc_epdc_fb_get_temp_index(struct mxc_epdc_fb_data *fb_data, int temp)
++{
++ int i;
++ int index = -1;
++
++ if (fb_data->trt_entries == 0) {
++ dev_err(fb_data->dev,
++ "No TRT exists...using default temp index\n");
++ return DEFAULT_TEMP_INDEX;
++ }
++
++ /* Search temperature ranges for a match */
++ for (i = 0; i < fb_data->trt_entries - 1; i++) {
++ if ((temp >= fb_data->temp_range_bounds[i])
++ && (temp < fb_data->temp_range_bounds[i+1])) {
++ index = i;
++ break;
++ }
++ }
++
++ if (index < 0) {
++ dev_err(fb_data->dev,
++ "No TRT index match...using default temp index\n");
++ return DEFAULT_TEMP_INDEX;
++ }
++
++ dev_dbg(fb_data->dev, "Using temperature index %d\n", index);
++
++ return index;
++}
++
++int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ /* Store temp index. Used later when configuring updates. */
++ mutex_lock(&fb_data->queue_mutex);
++ fb_data->temp_index = mxc_epdc_fb_get_temp_index(fb_data, temperature);
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_temperature);
++
++int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ dev_dbg(fb_data->dev, "Setting auto update mode to %d\n", auto_mode);
++
++ if ((auto_mode == AUTO_UPDATE_MODE_AUTOMATIC_MODE)
++ || (auto_mode == AUTO_UPDATE_MODE_REGION_MODE))
++ fb_data->auto_mode = auto_mode;
++ else {
++ dev_err(fb_data->dev, "Invalid auto update mode parameter.\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_auto_update);
++
++int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ dev_dbg(fb_data->dev, "Setting optimization level to %d\n", upd_scheme);
++
++ /*
++ * Can't change the scheme until current updates have completed.
++ * This function returns when all active updates are done.
++ */
++ mxc_epdc_fb_flush_updates(fb_data);
++
++ if ((upd_scheme == UPDATE_SCHEME_SNAPSHOT)
++ || (upd_scheme == UPDATE_SCHEME_QUEUE)
++ || (upd_scheme == UPDATE_SCHEME_QUEUE_AND_MERGE))
++ fb_data->upd_scheme = upd_scheme;
++ else {
++ dev_err(fb_data->dev, "Invalid update scheme specified.\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_upd_scheme);
++
++static void copy_before_process(struct mxc_epdc_fb_data *fb_data,
++ struct update_data_list *upd_data_list)
++{
++ struct mxcfb_update_data *upd_data =
++ &upd_data_list->update_desc->upd_data;
++ int i;
++ unsigned char *temp_buf_ptr = fb_data->virt_addr_copybuf;
++ unsigned char *src_ptr;
++ struct mxcfb_rect *src_upd_region;
++ int temp_buf_stride;
++ int src_stride;
++ int bpp = fb_data->epdc_fb_var.bits_per_pixel;
++ int left_offs, right_offs;
++ int x_trailing_bytes, y_trailing_bytes;
++ int alt_buf_offset;
++
++ /* Set source buf pointer based on input source, panning, etc. */
++ if (upd_data->flags & EPDC_FLAG_USE_ALT_BUFFER) {
++ src_upd_region = &upd_data->alt_buffer_data.alt_update_region;
++ src_stride =
++ upd_data->alt_buffer_data.width * bpp/8;
++ alt_buf_offset = upd_data->alt_buffer_data.phys_addr -
++ fb_data->info.fix.smem_start;
++ src_ptr = fb_data->info.screen_base + alt_buf_offset
++ + src_upd_region->top * src_stride;
++ } else {
++ src_upd_region = &upd_data->update_region;
++ src_stride = fb_data->epdc_fb_var.xres_virtual * bpp/8;
++ src_ptr = fb_data->info.screen_base + fb_data->fb_offset
++ + src_upd_region->top * src_stride;
++ }
++
++ temp_buf_stride = ALIGN(src_upd_region->width, 8) * bpp/8;
++ left_offs = src_upd_region->left * bpp/8;
++ right_offs = src_upd_region->width * bpp/8;
++ x_trailing_bytes = (ALIGN(src_upd_region->width, 8)
++ - src_upd_region->width) * bpp/8;
++
++ for (i = 0; i < src_upd_region->height; i++) {
++ /* Copy the full line */
++ memcpy(temp_buf_ptr, src_ptr + left_offs,
++ src_upd_region->width * bpp/8);
++
++ /* Clear any unwanted pixels at the end of each line */
++ if (src_upd_region->width & 0x7) {
++ memset(temp_buf_ptr + right_offs, 0x0,
++ x_trailing_bytes);
++ }
++
++ temp_buf_ptr += temp_buf_stride;
++ src_ptr += src_stride;
++ }
++
++ /* Clear any unwanted pixels at the bottom of the end of each line */
++ if (src_upd_region->height & 0x7) {
++ y_trailing_bytes = (ALIGN(src_upd_region->height, 8)
++ - src_upd_region->height) *
++ ALIGN(src_upd_region->width, 8) * bpp/8;
++ memset(temp_buf_ptr, 0x0, y_trailing_bytes);
++ }
++}
++
++static int epdc_process_update(struct update_data_list *upd_data_list,
++ struct mxc_epdc_fb_data *fb_data)
++{
++ struct mxcfb_rect *src_upd_region; /* Region of src buffer for update */
++ struct mxcfb_rect pxp_upd_region;
++ u32 src_width, src_height;
++ u32 offset_from_4, bytes_per_pixel;
++ u32 post_rotation_xcoord, post_rotation_ycoord, width_pxp_blocks;
++ u32 pxp_input_offs, pxp_output_offs, pxp_output_shift;
++ u32 hist_stat = 0;
++ int width_unaligned, height_unaligned;
++ bool input_unaligned = false;
++ bool line_overflow = false;
++ int pix_per_line_added;
++ bool use_temp_buf = false;
++ struct mxcfb_rect temp_buf_upd_region;
++ struct update_desc_list *upd_desc_list = upd_data_list->update_desc;
++
++ int ret;
++
++ /*
++ * Gotta do a whole bunch of buffer ptr manipulation to
++ * work around HW restrictions for PxP & EPDC
++ * Note: Applies to pre-2.0 versions of EPDC/PxP
++ */
++
++ /*
++ * Are we using FB or an alternate (overlay)
++ * buffer for source of update?
++ */
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER) {
++ src_width = upd_desc_list->upd_data.alt_buffer_data.width;
++ src_height = upd_desc_list->upd_data.alt_buffer_data.height;
++ src_upd_region = &upd_desc_list->upd_data.alt_buffer_data.alt_update_region;
++ } else {
++ src_width = fb_data->epdc_fb_var.xres_virtual;
++ src_height = fb_data->epdc_fb_var.yres;
++ src_upd_region = &upd_desc_list->upd_data.update_region;
++ }
++
++ bytes_per_pixel = fb_data->epdc_fb_var.bits_per_pixel/8;
++
++ /*
++ * SW workaround for PxP limitation (for pre-v2.0 HW)
++ *
++ * There are 3 cases where we cannot process the update data
++ * directly from the input buffer:
++ *
++ * 1) PxP must process 8x8 pixel blocks, and all pixels in each block
++ * are considered for auto-waveform mode selection. If the
++ * update region is not 8x8 aligned, additional unwanted pixels
++ * will be considered in auto-waveform mode selection.
++ *
++ * 2) PxP input must be 32-bit aligned, so any update
++ * address not 32-bit aligned must be shifted to meet the
++ * 32-bit alignment. The PxP will thus end up processing pixels
++ * outside of the update region to satisfy this alignment restriction,
++ * which can affect auto-waveform mode selection.
++ *
++ * 3) If input fails 32-bit alignment, and the resulting expansion
++ * of the processed region would add at least 8 pixels more per
++ * line than the original update line width, the EPDC would
++ * cause screen artifacts by incorrectly handling the 8+ pixels
++ * at the end of each line.
++ *
++ * Workaround is to copy from source buffer into a temporary
++ * buffer, which we pad with zeros to match the 8x8 alignment
++ * requirement. This temp buffer becomes the input to the PxP.
++ */
++ width_unaligned = src_upd_region->width & 0x7;
++ height_unaligned = src_upd_region->height & 0x7;
++
++ offset_from_4 = src_upd_region->left & 0x3;
++ input_unaligned = ((offset_from_4 * bytes_per_pixel % 4) != 0) ?
++ true : false;
++
++ pix_per_line_added = (offset_from_4 * bytes_per_pixel % 4)
++ / bytes_per_pixel;
++ if ((((fb_data->epdc_fb_var.rotate == FB_ROTATE_UR) ||
++ fb_data->epdc_fb_var.rotate == FB_ROTATE_UD)) &&
++ (ALIGN(src_upd_region->width, 8) <
++ ALIGN(src_upd_region->width + pix_per_line_added, 8)))
++ line_overflow = true;
++
++ /* Grab pxp_mutex here so that we protect access
++ * to copybuf in addition to the PxP structures */
++ mutex_lock(&fb_data->pxp_mutex);
++
++ if (((((width_unaligned || height_unaligned || input_unaligned) &&
++ (upd_desc_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO))
++ || line_overflow) && (fb_data->rev < 20)) ||
++ fb_data->restrict_width) {
++ dev_dbg(fb_data->dev, "Copying update before processing.\n");
++
++ /* Update to reflect what the new source buffer will be */
++ src_width = ALIGN(src_upd_region->width, 8);
++ src_height = ALIGN(src_upd_region->height, 8);
++
++ copy_before_process(fb_data, upd_data_list);
++
++ /*
++ * src_upd_region should now describe
++ * the new update buffer attributes.
++ */
++ temp_buf_upd_region.left = 0;
++ temp_buf_upd_region.top = 0;
++ temp_buf_upd_region.width = src_upd_region->width;
++ temp_buf_upd_region.height = src_upd_region->height;
++ src_upd_region = &temp_buf_upd_region;
++
++ use_temp_buf = true;
++ }
++
++ /*
++ * For pre-2.0 HW, input address must be 32-bit aligned
++ * Compute buffer offset to account for this PxP limitation
++ */
++ offset_from_4 = src_upd_region->left & 0x3;
++ input_unaligned = ((offset_from_4 * bytes_per_pixel % 4) != 0) ?
++ true : false;
++ if ((fb_data->rev < 20) && input_unaligned) {
++ /* Leave a gap between PxP input addr and update region pixels */
++ pxp_input_offs =
++ (src_upd_region->top * src_width + src_upd_region->left)
++ * bytes_per_pixel & 0xFFFFFFFC;
++ /* Update region left changes to reflect relative position to input ptr */
++ pxp_upd_region.left = (offset_from_4 * bytes_per_pixel % 4)
++ / bytes_per_pixel;
++ } else {
++ pxp_input_offs =
++ (src_upd_region->top * src_width + src_upd_region->left)
++ * bytes_per_pixel;
++ pxp_upd_region.left = 0;
++ }
++
++ pxp_upd_region.top = 0;
++
++ /*
++ * For version 2.0 and later of EPDC & PxP, if no rotation, we don't
++ * need to align width & height (rotation always requires 8-pixel
++ * width & height alignment, per PxP limitations)
++ */
++ if ((fb_data->epdc_fb_var.rotate == 0) && (fb_data->rev >= 20)) {
++ pxp_upd_region.width = src_upd_region->width;
++ pxp_upd_region.height = src_upd_region->height;
++ } else {
++ /* Update region dimensions to meet 8x8 pixel requirement */
++ pxp_upd_region.width = ALIGN(src_upd_region->width + pxp_upd_region.left, 8);
++ pxp_upd_region.height = ALIGN(src_upd_region->height, 8);
++ }
++
++ switch (fb_data->epdc_fb_var.rotate) {
++ case FB_ROTATE_UR:
++ default:
++ post_rotation_xcoord = pxp_upd_region.left;
++ post_rotation_ycoord = pxp_upd_region.top;
++ width_pxp_blocks = pxp_upd_region.width;
++ break;
++ case FB_ROTATE_CW:
++ width_pxp_blocks = pxp_upd_region.height;
++ post_rotation_xcoord = width_pxp_blocks - src_upd_region->height;
++ post_rotation_ycoord = pxp_upd_region.left;
++ break;
++ case FB_ROTATE_UD:
++ width_pxp_blocks = pxp_upd_region.width;
++ post_rotation_xcoord = width_pxp_blocks - src_upd_region->width - pxp_upd_region.left;
++ post_rotation_ycoord = pxp_upd_region.height - src_upd_region->height - pxp_upd_region.top;
++ break;
++ case FB_ROTATE_CCW:
++ width_pxp_blocks = pxp_upd_region.height;
++ post_rotation_xcoord = pxp_upd_region.top;
++ post_rotation_ycoord = pxp_upd_region.width - src_upd_region->width - pxp_upd_region.left;
++ break;
++ }
++
++ /* Update region start coord to force PxP to process full 8x8 regions */
++ pxp_upd_region.top &= ~0x7;
++ pxp_upd_region.left &= ~0x7;
++
++ if (fb_data->rev < 20) {
++ pxp_output_shift = ALIGN(post_rotation_xcoord, 8)
++ - post_rotation_xcoord;
++
++ pxp_output_offs = post_rotation_ycoord * width_pxp_blocks
++ + pxp_output_shift;
++
++ upd_desc_list->epdc_offs = ALIGN(pxp_output_offs, 8);
++ } else {
++ pxp_output_shift = 0;
++ pxp_output_offs = post_rotation_ycoord * width_pxp_blocks
++ + post_rotation_xcoord;
++
++ upd_desc_list->epdc_offs = pxp_output_offs;
++ }
++
++ upd_desc_list->epdc_stride = width_pxp_blocks;
++
++ /* Source address either comes from alternate buffer
++ provided in update data, or from the framebuffer. */
++ if (use_temp_buf)
++ sg_dma_address(&fb_data->sg[0]) =
++ fb_data->phys_addr_copybuf;
++ else if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER)
++ sg_dma_address(&fb_data->sg[0]) =
++ upd_desc_list->upd_data.alt_buffer_data.phys_addr
++ + pxp_input_offs;
++ else {
++ sg_dma_address(&fb_data->sg[0]) =
++ fb_data->info.fix.smem_start + fb_data->fb_offset
++ + pxp_input_offs;
++ sg_set_page(&fb_data->sg[0],
++ virt_to_page(fb_data->info.screen_base),
++ fb_data->info.fix.smem_len,
++ offset_in_page(fb_data->info.screen_base));
++ }
++
++ /* Update sg[1] to point to output of PxP proc task */
++ sg_dma_address(&fb_data->sg[1]) = upd_data_list->phys_addr
++ + pxp_output_shift;
++ sg_set_page(&fb_data->sg[1], virt_to_page(upd_data_list->virt_addr),
++ fb_data->max_pix_size,
++ offset_in_page(upd_data_list->virt_addr));
++
++ /*
++ * Set PxP LUT transform type based on update flags.
++ */
++ fb_data->pxp_conf.proc_data.lut_transform = 0;
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_ENABLE_INVERSION)
++ fb_data->pxp_conf.proc_data.lut_transform |= PXP_LUT_INVERT;
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_FORCE_MONOCHROME)
++ fb_data->pxp_conf.proc_data.lut_transform |=
++ PXP_LUT_BLACK_WHITE;
++ if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_CMAP)
++ fb_data->pxp_conf.proc_data.lut_transform |=
++ PXP_LUT_USE_CMAP;
++
++ /*
++ * Toggle inversion processing if 8-bit
++ * inverted is the current pixel format.
++ */
++ if (fb_data->epdc_fb_var.grayscale == GRAYSCALE_8BIT_INVERTED)
++ fb_data->pxp_conf.proc_data.lut_transform ^= PXP_LUT_INVERT;
++
++ /* This is a blocking call, so upon return PxP tx should be done */
++ ret = pxp_process_update(fb_data, src_width, src_height,
++ &pxp_upd_region);
++ if (ret) {
++ dev_err(fb_data->dev, "Unable to submit PxP update task.\n");
++ mutex_unlock(&fb_data->pxp_mutex);
++ return ret;
++ }
++
++ /* If needed, enable EPDC HW while ePxP is processing */
++ if ((fb_data->power_state == POWER_STATE_OFF)
++ || fb_data->powering_down) {
++ epdc_powerup(fb_data);
++ }
++
++ /* This is a blocking call, so upon return PxP tx should be done */
++ ret = pxp_complete_update(fb_data, &hist_stat);
++ if (ret) {
++ dev_err(fb_data->dev, "Unable to complete PxP update task.\n");
++ mutex_unlock(&fb_data->pxp_mutex);
++ return ret;
++ }
++
++ mutex_unlock(&fb_data->pxp_mutex);
++
++ /* Update waveform mode from PxP histogram results */
++ if ((fb_data->rev <= 20) &&
++ (upd_desc_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO)) {
++ if (hist_stat & 0x1)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_du;
++ else if (hist_stat & 0x2)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc4;
++ else if (hist_stat & 0x4)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc8;
++ else if (hist_stat & 0x8)
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc16;
++ else
++ upd_desc_list->upd_data.waveform_mode =
++ fb_data->wv_modes.mode_gc32;
++
++ dev_dbg(fb_data->dev, "hist_stat = 0x%x, new waveform = 0x%x\n",
++ hist_stat, upd_desc_list->upd_data.waveform_mode);
++ }
++
++ return 0;
++}
++
++static int epdc_submit_merge(struct update_desc_list *upd_desc_list,
++ struct update_desc_list *update_to_merge,
++ struct mxc_epdc_fb_data *fb_data)
++{
++ struct mxcfb_update_data *a, *b;
++ struct mxcfb_rect *arect, *brect;
++ struct mxcfb_rect combine;
++ bool use_flags = false;
++
++ a = &upd_desc_list->upd_data;
++ b = &update_to_merge->upd_data;
++ arect = &upd_desc_list->upd_data.update_region;
++ brect = &update_to_merge->upd_data.update_region;
++
++ /* Do not merge a dry-run collision test update */
++ if ((a->flags & EPDC_FLAG_TEST_COLLISION) ||
++ (b->flags & EPDC_FLAG_TEST_COLLISION))
++ return MERGE_BLOCK;
++
++ /*
++ * Updates with different flags must be executed sequentially.
++ * Halt the merge process to ensure this.
++ */
++ if (a->flags != b->flags) {
++ /*
++ * Special exception: if update regions are identical,
++ * we may be able to merge them.
++ */
++ if ((arect->left != brect->left) ||
++ (arect->top != brect->top) ||
++ (arect->width != brect->width) ||
++ (arect->height != brect->height))
++ return MERGE_BLOCK;
++
++ use_flags = true;
++ }
++
++ if (a->update_mode != b->update_mode)
++ a->update_mode = UPDATE_MODE_FULL;
++
++ if (a->waveform_mode != b->waveform_mode)
++ a->waveform_mode = WAVEFORM_MODE_AUTO;
++
++ if (arect->left > (brect->left + brect->width) ||
++ brect->left > (arect->left + arect->width) ||
++ arect->top > (brect->top + brect->height) ||
++ brect->top > (arect->top + arect->height))
++ return MERGE_FAIL;
++
++ combine.left = arect->left < brect->left ? arect->left : brect->left;
++ combine.top = arect->top < brect->top ? arect->top : brect->top;
++ combine.width = (arect->left + arect->width) >
++ (brect->left + brect->width) ?
++ (arect->left + arect->width - combine.left) :
++ (brect->left + brect->width - combine.left);
++ combine.height = (arect->top + arect->height) >
++ (brect->top + brect->height) ?
++ (arect->top + arect->height - combine.top) :
++ (brect->top + brect->height - combine.top);
++
++ /* Don't merge if combined width exceeds max width */
++ if (fb_data->restrict_width) {
++ u32 max_width = EPDC_V2_MAX_UPDATE_WIDTH;
++ u32 combined_width = combine.width;
++ if (fb_data->epdc_fb_var.rotate != FB_ROTATE_UR)
++ max_width -= EPDC_V2_ROTATION_ALIGNMENT;
++ if ((fb_data->epdc_fb_var.rotate == FB_ROTATE_CW) ||
++ (fb_data->epdc_fb_var.rotate == FB_ROTATE_CCW))
++ combined_width = combine.height;
++ if (combined_width > max_width)
++ return MERGE_FAIL;
++ }
++
++ *arect = combine;
++
++ /* Use flags of the later update */
++ if (use_flags)
++ a->flags = b->flags;
++
++ /* Merge markers */
++ list_splice_tail(&update_to_merge->upd_marker_list,
++ &upd_desc_list->upd_marker_list);
++
++ /* Merged update should take on the earliest order */
++ upd_desc_list->update_order =
++ (upd_desc_list->update_order > update_to_merge->update_order) ?
++ upd_desc_list->update_order : update_to_merge->update_order;
++
++ return MERGE_OK;
++}
++
++static void epdc_submit_work_func(struct work_struct *work)
++{
++ int temp_index;
++ struct update_data_list *next_update, *temp_update;
++ struct update_desc_list *next_desc, *temp_desc;
++ struct update_marker_data *next_marker, *temp_marker;
++ struct mxc_epdc_fb_data *fb_data =
++ container_of(work, struct mxc_epdc_fb_data, epdc_submit_work);
++ struct update_data_list *upd_data_list = NULL;
++ struct mxcfb_rect adj_update_region, *upd_region;
++ bool end_merge = false;
++ bool is_transform;
++ u32 update_addr;
++ int *err_dist;
++ int ret;
++
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * Are any of our collision updates able to go now?
++ * Go through all updates in the collision list and check to see
++ * if the collision mask has been fully cleared
++ */
++ list_for_each_entry_safe(next_update, temp_update,
++ &fb_data->upd_buf_collision_list, list) {
++
++ if (next_update->collision_mask != 0)
++ continue;
++
++ dev_dbg(fb_data->dev, "A collision update is ready to go!\n");
++
++ /* Force waveform mode to auto for resubmitted collisions */
++ next_update->update_desc->upd_data.waveform_mode =
++ WAVEFORM_MODE_AUTO;
++
++ /*
++ * We have a collision cleared, so select it for resubmission.
++ * If an update is already selected, attempt to merge.
++ */
++ if (!upd_data_list) {
++ upd_data_list = next_update;
++ list_del_init(&next_update->list);
++ if (fb_data->upd_scheme == UPDATE_SCHEME_QUEUE)
++ /* If not merging, we have our update */
++ break;
++ } else {
++ switch (epdc_submit_merge(upd_data_list->update_desc,
++ next_update->update_desc,
++ fb_data)) {
++ case MERGE_OK:
++ dev_dbg(fb_data->dev,
++ "Update merged [collision]\n");
++ list_del_init(&next_update->update_desc->list);
++ kfree(next_update->update_desc);
++ next_update->update_desc = NULL;
++ list_del_init(&next_update->list);
++ /* Add to free buffer list */
++ list_add_tail(&next_update->list,
++ &fb_data->upd_buf_free_list);
++ break;
++ case MERGE_FAIL:
++ dev_dbg(fb_data->dev,
++ "Update not merged [collision]\n");
++ break;
++ case MERGE_BLOCK:
++ dev_dbg(fb_data->dev,
++ "Merge blocked [collision]\n");
++ end_merge = true;
++ break;
++ }
++
++ if (end_merge) {
++ end_merge = false;
++ break;
++ }
++ }
++ }
++
++ /*
++ * Skip pending update list only if we found a collision
++ * update and we are not merging
++ */
++ if (!((fb_data->upd_scheme == UPDATE_SCHEME_QUEUE) &&
++ upd_data_list)) {
++ /*
++ * If we didn't find a collision update ready to go, we
++ * need to get a free buffer and match it to a pending update.
++ */
++
++ /*
++ * Can't proceed if there are no free buffers (and we don't
++ * already have a collision update selected)
++ */
++ if (!upd_data_list &&
++ list_empty(&fb_data->upd_buf_free_list)) {
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ list_for_each_entry_safe(next_desc, temp_desc,
++ &fb_data->upd_pending_list, list) {
++
++ dev_dbg(fb_data->dev, "Found a pending update!\n");
++
++ if (!upd_data_list) {
++ if (list_empty(&fb_data->upd_buf_free_list))
++ break;
++ upd_data_list =
++ list_entry(fb_data->upd_buf_free_list.next,
++ struct update_data_list, list);
++ list_del_init(&upd_data_list->list);
++ upd_data_list->update_desc = next_desc;
++ list_del_init(&next_desc->list);
++ if (fb_data->upd_scheme == UPDATE_SCHEME_QUEUE)
++ /* If not merging, we have an update */
++ break;
++ } else {
++ switch (epdc_submit_merge(upd_data_list->update_desc,
++ next_desc, fb_data)) {
++ case MERGE_OK:
++ dev_dbg(fb_data->dev,
++ "Update merged [queue]\n");
++ list_del_init(&next_desc->list);
++ kfree(next_desc);
++ break;
++ case MERGE_FAIL:
++ dev_dbg(fb_data->dev,
++ "Update not merged [queue]\n");
++ break;
++ case MERGE_BLOCK:
++ dev_dbg(fb_data->dev,
++ "Merge blocked [collision]\n");
++ end_merge = true;
++ break;
++ }
++
++ if (end_merge)
++ break;
++ }
++ }
++ }
++
++ /* Is update list empty? */
++ if (!upd_data_list) {
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /*
++ * If no processing required, skip update processing
++ * No processing means:
++ * - FB unrotated
++ * - FB pixel format = 8-bit grayscale
++ * - No look-up transformations (inversion, posterization, etc.)
++ *
++ * Note: A bug with EPDC stride prevents us from skipping
++ * PxP in versions 2.0 and earlier of EPDC.
++ */
++ is_transform = upd_data_list->update_desc->upd_data.flags &
++ (EPDC_FLAG_ENABLE_INVERSION | EPDC_FLAG_USE_DITHERING_Y1 |
++ EPDC_FLAG_USE_DITHERING_Y4 | EPDC_FLAG_FORCE_MONOCHROME |
++ EPDC_FLAG_USE_CMAP) ? true : false;
++
++ if ((fb_data->epdc_fb_var.rotate == FB_ROTATE_UR) &&
++ (fb_data->epdc_fb_var.grayscale == GRAYSCALE_8BIT) &&
++ !is_transform && (fb_data->rev > 20) &&
++ !fb_data->restrict_width) {
++
++ /* If needed, enable EPDC HW while ePxP is processing */
++ if ((fb_data->power_state == POWER_STATE_OFF)
++ || fb_data->powering_down)
++ epdc_powerup(fb_data);
++
++ /*
++ * Set update buffer pointer to the start of
++ * the update region in the frame buffer.
++ */
++ upd_region = &upd_data_list->update_desc->upd_data.update_region;
++ update_addr = fb_data->info.fix.smem_start +
++ ((upd_region->top * fb_data->info.var.xres_virtual) +
++ upd_region->left) * fb_data->info.var.bits_per_pixel/8;
++ upd_data_list->update_desc->epdc_stride =
++ fb_data->info.var.xres_virtual *
++ fb_data->info.var.bits_per_pixel/8;
++ } else {
++ /* Select from PxP output buffers */
++ upd_data_list->phys_addr =
++ fb_data->phys_addr_updbuf[fb_data->upd_buffer_num];
++ upd_data_list->virt_addr =
++ fb_data->virt_addr_updbuf[fb_data->upd_buffer_num];
++ fb_data->upd_buffer_num++;
++ if (fb_data->upd_buffer_num > fb_data->max_num_buffers-1)
++ fb_data->upd_buffer_num = 0;
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /* Perform PXP processing - EPDC power will also be enabled */
++ if (epdc_process_update(upd_data_list, fb_data)) {
++ dev_dbg(fb_data->dev, "PXP processing error.\n");
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++ list_del_init(&upd_data_list->update_desc->list);
++ kfree(upd_data_list->update_desc);
++ upd_data_list->update_desc = NULL;
++ /* Add to free buffer list */
++ list_add_tail(&upd_data_list->list,
++ &fb_data->upd_buf_free_list);
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++
++ update_addr = upd_data_list->phys_addr
++ + upd_data_list->update_desc->epdc_offs;
++ }
++
++ /* Get rotation-adjusted coordinates */
++ adjust_coordinates(fb_data->epdc_fb_var.xres,
++ fb_data->epdc_fb_var.yres, fb_data->epdc_fb_var.rotate,
++ &upd_data_list->update_desc->upd_data.update_region,
++ &adj_update_region);
++
++ /*
++ * Is the working buffer idle?
++ * If the working buffer is busy, we must wait for the resource
++ * to become free. The IST will signal this event.
++ */
++ if (fb_data->cur_update != NULL) {
++ dev_dbg(fb_data->dev, "working buf busy!\n");
++
++ /* Initialize event signalling an update resource is free */
++ init_completion(&fb_data->update_res_free);
++
++ fb_data->waiting_for_wb = true;
++
++ /* Leave spinlock while waiting for WB to complete */
++ mutex_unlock(&fb_data->queue_mutex);
++ wait_for_completion(&fb_data->update_res_free);
++ mutex_lock(&fb_data->queue_mutex);
++ }
++
++ /*
++ * Dithering Processing (Version 1.0 - for i.MX508 and i.MX6SL)
++ */
++ if (upd_data_list->update_desc->upd_data.flags &
++ EPDC_FLAG_USE_DITHERING_Y1) {
++
++ err_dist = kzalloc((fb_data->info.var.xres_virtual + 3) * 3
++ * sizeof(int), GFP_KERNEL);
++
++ /* Dithering Y8 -> Y1 */
++ do_dithering_processing_Y1_v1_0(
++ (uint8_t *)(upd_data_list->virt_addr +
++ upd_data_list->update_desc->epdc_offs),
++ &adj_update_region,
++ (fb_data->rev < 20) ?
++ ALIGN(adj_update_region.width, 8) :
++ adj_update_region.width,
++ err_dist);
++
++ kfree(err_dist);
++ } else if (upd_data_list->update_desc->upd_data.flags &
++ EPDC_FLAG_USE_DITHERING_Y4) {
++
++ err_dist = kzalloc((fb_data->info.var.xres_virtual + 3) * 3
++ * sizeof(int), GFP_KERNEL);
++
++ /* Dithering Y8 -> Y1 */
++ do_dithering_processing_Y4_v1_0(
++ (uint8_t *)(upd_data_list->virt_addr +
++ upd_data_list->update_desc->epdc_offs),
++ &adj_update_region,
++ (fb_data->rev < 20) ?
++ ALIGN(adj_update_region.width, 8) :
++ adj_update_region.width,
++ err_dist);
++
++ kfree(err_dist);
++ }
++
++ /*
++ * If there are no LUTs available,
++ * then we must wait for the resource to become free.
++ * The IST will signal this event.
++ */
++ if (!epdc_any_luts_available()) {
++ dev_dbg(fb_data->dev, "no luts available!\n");
++
++ /* Initialize event signalling an update resource is free */
++ init_completion(&fb_data->update_res_free);
++
++ fb_data->waiting_for_lut = true;
++
++ /* Leave spinlock while waiting for LUT to free up */
++ mutex_unlock(&fb_data->queue_mutex);
++ wait_for_completion(&fb_data->update_res_free);
++ mutex_lock(&fb_data->queue_mutex);
++ }
++
++ ret = epdc_choose_next_lut(fb_data->rev, &upd_data_list->lut_num);
++ /*
++ * If LUT15 is in use (for pre-EPDC v2.0 hardware):
++ * - Wait for LUT15 to complete is if TCE underrun prevent is enabled
++ * - If we go ahead with update, sync update submission with EOF
++ */
++ if (ret && fb_data->tce_prevent && (fb_data->rev < 20)) {
++ dev_dbg(fb_data->dev, "Waiting for LUT15\n");
++
++ /* Initialize event signalling that lut15 is free */
++ init_completion(&fb_data->lut15_free);
++
++ fb_data->waiting_for_lut15 = true;
++
++ /* Leave spinlock while waiting for LUT to free up */
++ mutex_unlock(&fb_data->queue_mutex);
++ wait_for_completion(&fb_data->lut15_free);
++ mutex_lock(&fb_data->queue_mutex);
++
++ epdc_choose_next_lut(fb_data->rev, &upd_data_list->lut_num);
++ } else if (ret && (fb_data->rev < 20)) {
++ /* Synchronize update submission time to reduce
++ chances of TCE underrun */
++ init_completion(&fb_data->eof_event);
++
++ epdc_eof_intr(true);
++
++ /* Leave spinlock while waiting for EOF event */
++ mutex_unlock(&fb_data->queue_mutex);
++ ret = wait_for_completion_timeout(&fb_data->eof_event,
++ msecs_to_jiffies(1000));
++ if (!ret) {
++ dev_err(fb_data->dev, "Missed EOF event!\n");
++ epdc_eof_intr(false);
++ }
++ udelay(fb_data->eof_sync_period);
++ mutex_lock(&fb_data->queue_mutex);
++
++ }
++
++ /* LUTs are available, so we get one here */
++ fb_data->cur_update = upd_data_list;
++
++ /* Reset mask for LUTS that have completed during WB processing */
++ fb_data->luts_complete_wb = 0;
++
++ /* If we are just testing for collision, we don't assign a LUT,
++ * so we don't need to update LUT-related resources. */
++ if (!(upd_data_list->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION)) {
++ /* Associate LUT with update marker */
++ list_for_each_entry_safe(next_marker, temp_marker,
++ &upd_data_list->update_desc->upd_marker_list, upd_list)
++ next_marker->lut_num = fb_data->cur_update->lut_num;
++
++ /* Mark LUT with order */
++ fb_data->lut_update_order[upd_data_list->lut_num] =
++ upd_data_list->update_desc->update_order;
++
++ epdc_lut_complete_intr(fb_data->rev, upd_data_list->lut_num,
++ true);
++ }
++
++ /* Enable Collision and WB complete IRQs */
++ epdc_working_buf_intr(true);
++
++ /* Program EPDC update to process buffer */
++ if (upd_data_list->update_desc->upd_data.temp != TEMP_USE_AMBIENT) {
++ temp_index = mxc_epdc_fb_get_temp_index(fb_data,
++ upd_data_list->update_desc->upd_data.temp);
++ epdc_set_temp(temp_index);
++ } else
++ epdc_set_temp(fb_data->temp_index);
++ epdc_set_update_addr(update_addr);
++ epdc_set_update_coord(adj_update_region.left, adj_update_region.top);
++ epdc_set_update_dimensions(adj_update_region.width,
++ adj_update_region.height);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(upd_data_list->update_desc->epdc_stride);
++ if (fb_data->wv_modes_update &&
++ (upd_data_list->update_desc->upd_data.waveform_mode
++ == WAVEFORM_MODE_AUTO)) {
++ epdc_set_update_waveform(&fb_data->wv_modes);
++ fb_data->wv_modes_update = false;
++ }
++
++ epdc_submit_update(upd_data_list->lut_num,
++ upd_data_list->update_desc->upd_data.waveform_mode,
++ upd_data_list->update_desc->upd_data.update_mode,
++ (upd_data_list->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION) ? true : false,
++ false, 0);
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++}
++
++static int mxc_epdc_fb_send_single_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++ struct update_data_list *upd_data_list = NULL;
++ struct mxcfb_rect *screen_upd_region; /* Region on screen to update */
++ int temp_index;
++ int ret;
++ struct update_desc_list *upd_desc;
++ struct update_marker_data *marker_data, *next_marker, *temp_marker;
++
++ /* Has EPDC HW been initialized? */
++ if (!fb_data->hw_ready) {
++ /* Throw message if we are not mid-initialization */
++ if (!fb_data->hw_initializing)
++ dev_err(fb_data->dev, "Display HW not properly"
++ "initialized. Aborting update.\n");
++ return -EPERM;
++ }
++
++ /* Check validity of update params */
++ if ((upd_data->update_mode != UPDATE_MODE_PARTIAL) &&
++ (upd_data->update_mode != UPDATE_MODE_FULL)) {
++ dev_err(fb_data->dev,
++ "Update mode 0x%x is invalid. Aborting update.\n",
++ upd_data->update_mode);
++ return -EINVAL;
++ }
++ if ((upd_data->waveform_mode > 255) &&
++ (upd_data->waveform_mode != WAVEFORM_MODE_AUTO)) {
++ dev_err(fb_data->dev,
++ "Update waveform mode 0x%x is invalid."
++ " Aborting update.\n",
++ upd_data->waveform_mode);
++ return -EINVAL;
++ }
++
++ mutex_lock(&fb_data->queue_mutex);
++ if ((upd_data->update_region.left + upd_data->update_region.width > fb_data->epdc_fb_var.xres) ||
++ (upd_data->update_region.top + upd_data->update_region.height > fb_data->epdc_fb_var.yres)) {
++ mutex_unlock(&fb_data->queue_mutex);
++ dev_err(fb_data->dev,
++ "Update region is outside bounds of framebuffer."
++ "Aborting update.\n");
++ return -EINVAL;
++ }
++ mutex_unlock(&fb_data->queue_mutex);
++
++ if (upd_data->flags & EPDC_FLAG_USE_ALT_BUFFER) {
++ if ((upd_data->update_region.width !=
++ upd_data->alt_buffer_data.alt_update_region.width) ||
++ (upd_data->update_region.height !=
++ upd_data->alt_buffer_data.alt_update_region.height)) {
++ dev_err(fb_data->dev,
++ "Alternate update region dimensions must "
++ "match screen update region dimensions.\n");
++ return -EINVAL;
++ }
++ /* Validate physical address parameter */
++ if ((upd_data->alt_buffer_data.phys_addr <
++ fb_data->info.fix.smem_start) ||
++ (upd_data->alt_buffer_data.phys_addr >
++ fb_data->info.fix.smem_start + fb_data->map_size)) {
++ dev_err(fb_data->dev,
++ "Invalid physical address for alternate "
++ "buffer. Aborting update...\n");
++ return -EINVAL;
++ }
++ }
++
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * If we are waiting to go into suspend, or the FB is blanked,
++ * we do not accept new updates
++ */
++ if ((fb_data->waiting_for_idle) ||
++ (fb_data->blank != FB_BLANK_UNBLANK)) {
++ dev_dbg(fb_data->dev, "EPDC not active."
++ "Update request abort.\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return -EPERM;
++ }
++
++ if (fb_data->upd_scheme == UPDATE_SCHEME_SNAPSHOT) {
++ int count = 0;
++ struct update_data_list *plist;
++
++ /*
++ * If next update is a FULL mode update, then we must
++ * ensure that all pending & active updates are complete
++ * before submitting the update. Otherwise, the FULL
++ * mode update may cause an endless collision loop with
++ * other updates. Block here until updates are flushed.
++ */
++ if (upd_data->update_mode == UPDATE_MODE_FULL) {
++ mutex_unlock(&fb_data->queue_mutex);
++ mxc_epdc_fb_flush_updates(fb_data);
++ mutex_lock(&fb_data->queue_mutex);
++ }
++
++ /* Count buffers in free buffer list */
++ list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
++ count++;
++
++ /* Use count to determine if we have enough
++ * free buffers to handle this update request */
++ if (count + fb_data->max_num_buffers
++ <= fb_data->max_num_updates) {
++ dev_err(fb_data->dev,
++ "No free intermediate buffers available.\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return -ENOMEM;
++ }
++
++ /* Grab first available buffer and delete from the free list */
++ upd_data_list =
++ list_entry(fb_data->upd_buf_free_list.next,
++ struct update_data_list, list);
++
++ list_del_init(&upd_data_list->list);
++ }
++
++ /*
++ * Create new update data structure, fill it with new update
++ * data and add it to the list of pending updates
++ */
++ upd_desc = kzalloc(sizeof(struct update_desc_list), GFP_KERNEL);
++ if (!upd_desc) {
++ dev_err(fb_data->dev,
++ "Insufficient system memory for update! Aborting.\n");
++ if (fb_data->upd_scheme == UPDATE_SCHEME_SNAPSHOT) {
++ list_add(&upd_data_list->list,
++ &fb_data->upd_buf_free_list);
++ }
++ mutex_unlock(&fb_data->queue_mutex);
++ return -EPERM;
++ }
++ /* Initialize per-update marker list */
++ INIT_LIST_HEAD(&upd_desc->upd_marker_list);
++ upd_desc->upd_data = *upd_data;
++ upd_desc->update_order = fb_data->order_cnt++;
++ list_add_tail(&upd_desc->list, &fb_data->upd_pending_list);
++
++ /* If marker specified, associate it with a completion */
++ if (upd_data->update_marker != 0) {
++ /* Allocate new update marker and set it up */
++ marker_data = kzalloc(sizeof(struct update_marker_data),
++ GFP_KERNEL);
++ if (!marker_data) {
++ dev_err(fb_data->dev, "No memory for marker!\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return -ENOMEM;
++ }
++ list_add_tail(&marker_data->upd_list,
++ &upd_desc->upd_marker_list);
++ marker_data->update_marker = upd_data->update_marker;
++ if (upd_desc->upd_data.flags & EPDC_FLAG_TEST_COLLISION)
++ marker_data->lut_num = DRY_RUN_NO_LUT;
++ else
++ marker_data->lut_num = INVALID_LUT;
++ init_completion(&marker_data->update_completion);
++ /* Add marker to master marker list */
++ list_add_tail(&marker_data->full_list,
++ &fb_data->full_marker_list);
++ }
++
++ if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) {
++ /* Queued update scheme processing */
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /* Signal workqueue to handle new update */
++ queue_work(fb_data->epdc_submit_workqueue,
++ &fb_data->epdc_submit_work);
++
++ return 0;
++ }
++
++ /* Snapshot update scheme processing */
++
++ /* Set descriptor for current update, delete from pending list */
++ upd_data_list->update_desc = upd_desc;
++ list_del_init(&upd_desc->list);
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /*
++ * Hold on to original screen update region, which we
++ * will ultimately use when telling EPDC where to update on panel
++ */
++ screen_upd_region = &upd_desc->upd_data.update_region;
++
++ /* Select from PxP output buffers */
++ upd_data_list->phys_addr =
++ fb_data->phys_addr_updbuf[fb_data->upd_buffer_num];
++ upd_data_list->virt_addr =
++ fb_data->virt_addr_updbuf[fb_data->upd_buffer_num];
++ fb_data->upd_buffer_num++;
++ if (fb_data->upd_buffer_num > fb_data->max_num_buffers-1)
++ fb_data->upd_buffer_num = 0;
++
++ ret = epdc_process_update(upd_data_list, fb_data);
++ if (ret) {
++ mutex_unlock(&fb_data->pxp_mutex);
++ return ret;
++ }
++
++ /* Pass selected waveform mode back to user */
++ upd_data->waveform_mode = upd_desc->upd_data.waveform_mode;
++
++ /* Get rotation-adjusted coordinates */
++ adjust_coordinates(fb_data->epdc_fb_var.xres,
++ fb_data->epdc_fb_var.yres, fb_data->epdc_fb_var.rotate,
++ &upd_desc->upd_data.update_region, NULL);
++
++ /* Grab lock for queue manipulation and update submission */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * Is the working buffer idle?
++ * If either the working buffer is busy, or there are no LUTs available,
++ * then we return and let the ISR handle the update later
++ */
++ if ((fb_data->cur_update != NULL) || !epdc_any_luts_available()) {
++ /* Add processed Y buffer to update list */
++ list_add_tail(&upd_data_list->list, &fb_data->upd_buf_queue);
++
++ /* Return and allow the update to be submitted by the ISR. */
++ mutex_unlock(&fb_data->queue_mutex);
++ return 0;
++ }
++
++ /* LUTs are available, so we get one here */
++ ret = epdc_choose_next_lut(fb_data->rev, &upd_data_list->lut_num);
++ if (ret && fb_data->tce_prevent && (fb_data->rev < 20)) {
++ dev_dbg(fb_data->dev, "Must wait for LUT15\n");
++ /* Add processed Y buffer to update list */
++ list_add_tail(&upd_data_list->list, &fb_data->upd_buf_queue);
++
++ /* Return and allow the update to be submitted by the ISR. */
++ mutex_unlock(&fb_data->queue_mutex);
++ return 0;
++ }
++
++ if (!(upd_data_list->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION)) {
++
++ /* Save current update */
++ fb_data->cur_update = upd_data_list;
++
++ /* Reset mask for LUTS that have completed during WB processing */
++ fb_data->luts_complete_wb = 0;
++
++ /* Associate LUT with update marker */
++ list_for_each_entry_safe(next_marker, temp_marker,
++ &upd_data_list->update_desc->upd_marker_list, upd_list)
++ next_marker->lut_num = upd_data_list->lut_num;
++
++ /* Mark LUT as containing new update */
++ fb_data->lut_update_order[upd_data_list->lut_num] =
++ upd_desc->update_order;
++
++ epdc_lut_complete_intr(fb_data->rev, upd_data_list->lut_num,
++ true);
++ }
++
++ /* Clear status and Enable LUT complete and WB complete IRQs */
++ epdc_working_buf_intr(true);
++
++ /* Program EPDC update to process buffer */
++ epdc_set_update_addr(upd_data_list->phys_addr + upd_desc->epdc_offs);
++ epdc_set_update_coord(screen_upd_region->left, screen_upd_region->top);
++ epdc_set_update_dimensions(screen_upd_region->width,
++ screen_upd_region->height);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(upd_desc->epdc_stride);
++ if (upd_desc->upd_data.temp != TEMP_USE_AMBIENT) {
++ temp_index = mxc_epdc_fb_get_temp_index(fb_data,
++ upd_desc->upd_data.temp);
++ epdc_set_temp(temp_index);
++ } else
++ epdc_set_temp(fb_data->temp_index);
++ if (fb_data->wv_modes_update &&
++ (upd_desc->upd_data.waveform_mode == WAVEFORM_MODE_AUTO)) {
++ epdc_set_update_waveform(&fb_data->wv_modes);
++ fb_data->wv_modes_update = false;
++ }
++
++ epdc_submit_update(upd_data_list->lut_num,
++ upd_desc->upd_data.waveform_mode,
++ upd_desc->upd_data.update_mode,
++ (upd_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION) ? true : false,
++ false, 0);
++
++ mutex_unlock(&fb_data->queue_mutex);
++ return 0;
++}
++
++int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ if (!fb_data->restrict_width) {
++ /* No width restriction, send entire update region */
++ return mxc_epdc_fb_send_single_update(upd_data, info);
++ } else {
++ int ret;
++ __u32 width, left;
++ __u32 marker;
++ __u32 *region_width, *region_left;
++ u32 max_upd_width = EPDC_V2_MAX_UPDATE_WIDTH;
++
++ /* Further restrict max width due to pxp rotation
++ * alignment requirement
++ */
++ if (fb_data->epdc_fb_var.rotate != FB_ROTATE_UR)
++ max_upd_width -= EPDC_V2_ROTATION_ALIGNMENT;
++
++ /* Select split of width or height based on rotation */
++ if ((fb_data->epdc_fb_var.rotate == FB_ROTATE_UR) ||
++ (fb_data->epdc_fb_var.rotate == FB_ROTATE_UD)) {
++ region_width = &upd_data->update_region.width;
++ region_left = &upd_data->update_region.left;
++ } else {
++ region_width = &upd_data->update_region.height;
++ region_left = &upd_data->update_region.top;
++ }
++
++ if (*region_width <= max_upd_width)
++ return mxc_epdc_fb_send_single_update(upd_data, info);
++
++ width = *region_width;
++ left = *region_left;
++ marker = upd_data->update_marker;
++ upd_data->update_marker = 0;
++
++ do {
++ *region_width = max_upd_width;
++ *region_left = left;
++ ret = mxc_epdc_fb_send_single_update(upd_data, info);
++ if (ret)
++ return ret;
++ width -= max_upd_width;
++ left += max_upd_width;
++ } while (width > max_upd_width);
++
++ *region_width = width;
++ *region_left = left;
++ upd_data->update_marker = marker;
++ return mxc_epdc_fb_send_single_update(upd_data, info);
++ }
++}
++EXPORT_SYMBOL(mxc_epdc_fb_send_update);
++
++int mxc_epdc_fb_wait_update_complete(struct mxcfb_update_marker_data *marker_data,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++ struct update_marker_data *next_marker;
++ struct update_marker_data *temp;
++ bool marker_found = false;
++ int ret = 0;
++
++ /* 0 is an invalid update_marker value */
++ if (marker_data->update_marker == 0)
++ return -EINVAL;
++
++ /*
++ * Find completion associated with update_marker requested.
++ * Note: If update completed already, marker will have been
++ * cleared, it won't be found, and function will just return.
++ */
++
++ /* Grab queue lock to protect access to marker list */
++ mutex_lock(&fb_data->queue_mutex);
++
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->full_marker_list, full_list) {
++ if (next_marker->update_marker == marker_data->update_marker) {
++ dev_dbg(fb_data->dev, "Waiting for marker %d\n",
++ marker_data->update_marker);
++ next_marker->waiting = true;
++ marker_found = true;
++ break;
++ }
++ }
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ /*
++ * If marker not found, it has either been signalled already
++ * or the update request failed. In either case, just return.
++ */
++ if (!marker_found)
++ return ret;
++
++ ret = wait_for_completion_timeout(&next_marker->update_completion,
++ msecs_to_jiffies(5000));
++ if (!ret) {
++ dev_err(fb_data->dev,
++ "Timed out waiting for update completion\n");
++ return -ETIMEDOUT;
++ }
++
++ marker_data->collision_test = next_marker->collision_test;
++
++ /* Free update marker object */
++ kfree(next_marker);
++
++ return ret;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_wait_update_complete);
++
++int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ fb_data->pwrdown_delay = pwrdown_delay;
++
++ return 0;
++}
++EXPORT_SYMBOL(mxc_epdc_fb_set_pwrdown_delay);
++
++int mxc_epdc_get_pwrdown_delay(struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++
++ return fb_data->pwrdown_delay;
++}
++EXPORT_SYMBOL(mxc_epdc_get_pwrdown_delay);
++
++static int mxc_epdc_fb_ioctl(struct fb_info *info, unsigned int cmd,
++ unsigned long arg)
++{
++ void __user *argp = (void __user *)arg;
++ int ret = -EINVAL;
++
++ switch (cmd) {
++ case MXCFB_SET_WAVEFORM_MODES:
++ {
++ struct mxcfb_waveform_modes modes;
++ if (!copy_from_user(&modes, argp, sizeof(modes))) {
++ mxc_epdc_fb_set_waveform_modes(&modes, info);
++ ret = 0;
++ }
++ break;
++ }
++ case MXCFB_SET_TEMPERATURE:
++ {
++ int temperature;
++ if (!get_user(temperature, (int32_t __user *) arg))
++ ret = mxc_epdc_fb_set_temperature(temperature,
++ info);
++ break;
++ }
++ case MXCFB_SET_AUTO_UPDATE_MODE:
++ {
++ u32 auto_mode = 0;
++ if (!get_user(auto_mode, (__u32 __user *) arg))
++ ret = mxc_epdc_fb_set_auto_update(auto_mode,
++ info);
++ break;
++ }
++ case MXCFB_SET_UPDATE_SCHEME:
++ {
++ u32 upd_scheme = 0;
++ if (!get_user(upd_scheme, (__u32 __user *) arg))
++ ret = mxc_epdc_fb_set_upd_scheme(upd_scheme,
++ info);
++ break;
++ }
++ case MXCFB_SEND_UPDATE:
++ {
++ struct mxcfb_update_data upd_data;
++
++ if (mutex_lock_interruptible(&hard_lock) < 0)
++ return -ERESTARTSYS;
++
++ if (!copy_from_user(&upd_data, argp,
++ sizeof(upd_data))) {
++ ret = mxc_epdc_fb_send_update(&upd_data, info);
++ if (ret == 0 && copy_to_user(argp, &upd_data,
++ sizeof(upd_data)))
++ ret = -EFAULT;
++ } else {
++ ret = -EFAULT;
++ }
++
++ mutex_unlock(&hard_lock);
++
++ break;
++ }
++ case MXCFB_WAIT_FOR_UPDATE_COMPLETE:
++ {
++ struct mxcfb_update_marker_data upd_marker_data;
++ if (!copy_from_user(&upd_marker_data, argp,
++ sizeof(upd_marker_data))) {
++ ret = mxc_epdc_fb_wait_update_complete(
++ &upd_marker_data, info);
++ if (copy_to_user(argp, &upd_marker_data,
++ sizeof(upd_marker_data)))
++ ret = -EFAULT;
++ } else {
++ ret = -EFAULT;
++ }
++
++ break;
++ }
++
++ case MXCFB_SET_PWRDOWN_DELAY:
++ {
++ int delay = 0;
++ if (!get_user(delay, (__u32 __user *) arg))
++ ret =
++ mxc_epdc_fb_set_pwrdown_delay(delay, info);
++ break;
++ }
++
++ case MXCFB_GET_PWRDOWN_DELAY:
++ {
++ int pwrdown_delay = mxc_epdc_get_pwrdown_delay(info);
++ if (put_user(pwrdown_delay,
++ (int __user *)argp))
++ ret = -EFAULT;
++ ret = 0;
++ break;
++ }
++
++ case MXCFB_GET_WORK_BUFFER:
++ {
++ /* copy the epdc working buffer to the user space */
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++ flush_cache_all();
++ outer_flush_all();
++ if (copy_to_user((void __user *)arg,
++ (const void *) fb_data->working_buffer_virt,
++ fb_data->working_buffer_size))
++ ret = -EFAULT;
++ else
++ ret = 0;
++ flush_cache_all();
++ outer_flush_all();
++ break;
++ }
++
++ case MXCFB_DISABLE_EPDC_ACCESS:
++ {
++ struct mxc_epdc_fb_data *fb_data = info ?
++ (struct mxc_epdc_fb_data *)info:g_fb_data;
++ mxc_epdc_fb_flush_updates(fb_data);
++ /* disable handling any user update request */
++ mutex_lock(&hard_lock);
++ ret = 0;
++ break;
++ }
++
++ case MXCFB_ENABLE_EPDC_ACCESS:
++ {
++ /* enable user update handling again */
++ mutex_unlock(&hard_lock);
++ ret = 0;
++ break;
++ }
++
++ default:
++ break;
++ }
++ return ret;
++}
++
++static void mxc_epdc_fb_update_pages(struct mxc_epdc_fb_data *fb_data,
++ u16 y1, u16 y2)
++{
++ struct mxcfb_update_data update;
++
++ /* Do partial screen update, Update full horizontal lines */
++ update.update_region.left = 0;
++ update.update_region.width = fb_data->epdc_fb_var.xres;
++ update.update_region.top = y1;
++ update.update_region.height = y2 - y1;
++ update.waveform_mode = WAVEFORM_MODE_AUTO;
++ update.update_mode = UPDATE_MODE_FULL;
++ update.update_marker = 0;
++ update.temp = TEMP_USE_AMBIENT;
++ update.flags = 0;
++
++ mxc_epdc_fb_send_update(&update, &fb_data->info);
++}
++
++/* this is called back from the deferred io workqueue */
++static void mxc_epdc_fb_deferred_io(struct fb_info *info,
++ struct list_head *pagelist)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ struct page *page;
++ unsigned long beg, end;
++ int y1, y2, miny, maxy;
++
++ if (fb_data->auto_mode != AUTO_UPDATE_MODE_AUTOMATIC_MODE)
++ return;
++
++ miny = INT_MAX;
++ maxy = 0;
++ list_for_each_entry(page, pagelist, lru) {
++ beg = page->index << PAGE_SHIFT;
++ end = beg + PAGE_SIZE - 1;
++ y1 = beg / info->fix.line_length;
++ y2 = end / info->fix.line_length;
++ if (y2 >= fb_data->epdc_fb_var.yres)
++ y2 = fb_data->epdc_fb_var.yres - 1;
++ if (miny > y1)
++ miny = y1;
++ if (maxy < y2)
++ maxy = y2;
++ }
++
++ mxc_epdc_fb_update_pages(fb_data, miny, maxy);
++}
++
++void mxc_epdc_fb_flush_updates(struct mxc_epdc_fb_data *fb_data)
++{
++ int ret;
++
++ if (fb_data->in_init)
++ return;
++
++ /* Grab queue lock to prevent any new updates from being submitted */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /*
++ * 3 places to check for updates that are active or pending:
++ * 1) Updates in the pending list
++ * 2) Update buffers in use (e.g., PxP processing)
++ * 3) Active updates to panel - We can key off of EPDC
++ * power state to know if we have active updates.
++ */
++ if (!list_empty(&fb_data->upd_pending_list) ||
++ !is_free_list_full(fb_data) ||
++ (fb_data->updates_active == true)) {
++ /* Initialize event signalling updates are done */
++ init_completion(&fb_data->updates_done);
++ fb_data->waiting_for_idle = true;
++
++ mutex_unlock(&fb_data->queue_mutex);
++ /* Wait for any currently active updates to complete */
++ ret = wait_for_completion_timeout(&fb_data->updates_done,
++ msecs_to_jiffies(8000));
++ if (!ret)
++ dev_err(fb_data->dev,
++ "Flush updates timeout! ret = 0x%x\n", ret);
++
++ mutex_lock(&fb_data->queue_mutex);
++ fb_data->waiting_for_idle = false;
++ }
++
++ mutex_unlock(&fb_data->queue_mutex);
++}
++
++static int mxc_epdc_fb_blank(int blank, struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ int ret;
++
++ dev_dbg(fb_data->dev, "blank = %d\n", blank);
++
++ if (fb_data->blank == blank)
++ return 0;
++
++ fb_data->blank = blank;
++
++ switch (blank) {
++ case FB_BLANK_POWERDOWN:
++ mxc_epdc_fb_flush_updates(fb_data);
++ /* Wait for powerdown */
++ mutex_lock(&fb_data->power_mutex);
++ if ((fb_data->power_state == POWER_STATE_ON) &&
++ (fb_data->pwrdown_delay == FB_POWERDOWN_DISABLE)) {
++
++ /* Powerdown disabled, so we disable EPDC manually */
++ int count = 0;
++ int sleep_ms = 10;
++
++ mutex_unlock(&fb_data->power_mutex);
++
++ /* If any active updates, wait for them to complete */
++ while (fb_data->updates_active) {
++ /* Timeout after 1 sec */
++ if ((count * sleep_ms) > 1000)
++ break;
++ msleep(sleep_ms);
++ count++;
++ }
++
++ fb_data->powering_down = true;
++ epdc_powerdown(fb_data);
++ } else if (fb_data->power_state != POWER_STATE_OFF) {
++ fb_data->wait_for_powerdown = true;
++ init_completion(&fb_data->powerdown_compl);
++ mutex_unlock(&fb_data->power_mutex);
++ ret = wait_for_completion_timeout(&fb_data->powerdown_compl,
++ msecs_to_jiffies(5000));
++ if (!ret) {
++ dev_err(fb_data->dev,
++ "No powerdown received!\n");
++ return -ETIMEDOUT;
++ }
++ } else
++ mutex_unlock(&fb_data->power_mutex);
++ break;
++ case FB_BLANK_VSYNC_SUSPEND:
++ case FB_BLANK_HSYNC_SUSPEND:
++ case FB_BLANK_NORMAL:
++ mxc_epdc_fb_flush_updates(fb_data);
++ break;
++ }
++ return 0;
++}
++
++static int mxc_epdc_fb_pan_display(struct fb_var_screeninfo *var,
++ struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ u_int y_bottom;
++
++ dev_dbg(info->device, "%s: var->yoffset %d, info->var.yoffset %d\n",
++ __func__, var->yoffset, info->var.yoffset);
++ /* check if var is valid; also, xpan is not supported */
++ if (!var || (var->xoffset != info->var.xoffset) ||
++ (var->yoffset + var->yres > var->yres_virtual)) {
++ dev_dbg(info->device, "x panning not supported\n");
++ return -EINVAL;
++ }
++
++ if ((fb_data->epdc_fb_var.xoffset == var->xoffset) &&
++ (fb_data->epdc_fb_var.yoffset == var->yoffset))
++ return 0; /* No change, do nothing */
++
++ y_bottom = var->yoffset;
++
++ if (!(var->vmode & FB_VMODE_YWRAP))
++ y_bottom += var->yres;
++
++ if (y_bottom > info->var.yres_virtual)
++ return -EINVAL;
++
++ mutex_lock(&fb_data->queue_mutex);
++
++ fb_data->fb_offset = (var->yoffset * var->xres_virtual + var->xoffset)
++ * (var->bits_per_pixel) / 8;
++
++ fb_data->epdc_fb_var.xoffset = var->xoffset;
++ fb_data->epdc_fb_var.yoffset = var->yoffset;
++
++ if (var->vmode & FB_VMODE_YWRAP)
++ info->var.vmode |= FB_VMODE_YWRAP;
++ else
++ info->var.vmode &= ~FB_VMODE_YWRAP;
++
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return 0;
++}
++
++static struct fb_ops mxc_epdc_fb_ops = {
++ .owner = THIS_MODULE,
++ .fb_check_var = mxc_epdc_fb_check_var,
++ .fb_set_par = mxc_epdc_fb_set_par,
++ .fb_setcmap = mxc_epdc_fb_setcmap,
++ .fb_setcolreg = mxc_epdc_fb_setcolreg,
++ .fb_pan_display = mxc_epdc_fb_pan_display,
++ .fb_ioctl = mxc_epdc_fb_ioctl,
++ .fb_mmap = mxc_epdc_fb_mmap,
++ .fb_blank = mxc_epdc_fb_blank,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++};
++
++static struct fb_deferred_io mxc_epdc_fb_defio = {
++ .delay = HZ,
++ .deferred_io = mxc_epdc_fb_deferred_io,
++};
++
++static void epdc_done_work_func(struct work_struct *work)
++{
++ struct mxc_epdc_fb_data *fb_data =
++ container_of(work, struct mxc_epdc_fb_data,
++ epdc_done_work.work);
++ epdc_powerdown(fb_data);
++}
++
++static bool is_free_list_full(struct mxc_epdc_fb_data *fb_data)
++{
++ int count = 0;
++ struct update_data_list *plist;
++
++ /* Count buffers in free buffer list */
++ list_for_each_entry(plist, &fb_data->upd_buf_free_list, list)
++ count++;
++
++ /* Check to see if all buffers are in this list */
++ if (count == fb_data->max_num_updates)
++ return true;
++ else
++ return false;
++}
++
++static irqreturn_t mxc_epdc_irq_handler(int irq, void *dev_id)
++{
++ struct mxc_epdc_fb_data *fb_data = dev_id;
++ u32 ints_fired, luts1_ints_fired, luts2_ints_fired;
++
++ /*
++ * If we just completed one-time panel init, bypass
++ * queue handling, clear interrupt and return
++ */
++ if (fb_data->in_init) {
++ if (epdc_is_working_buffer_complete()) {
++ epdc_working_buf_intr(false);
++ epdc_clear_working_buf_irq();
++ dev_dbg(fb_data->dev, "Cleared WB for init update\n");
++ }
++
++ if (epdc_is_lut_complete(fb_data->rev, 0)) {
++ epdc_lut_complete_intr(fb_data->rev, 0, false);
++ epdc_clear_lut_complete_irq(fb_data->rev, 0);
++ fb_data->in_init = false;
++ dev_dbg(fb_data->dev, "Cleared LUT complete for init update\n");
++ }
++
++ return IRQ_HANDLED;
++ }
++
++ ints_fired = __raw_readl(EPDC_IRQ_MASK) & __raw_readl(EPDC_IRQ);
++ if (fb_data->rev < 20) {
++ luts1_ints_fired = 0;
++ luts2_ints_fired = 0;
++ } else {
++ luts1_ints_fired = __raw_readl(EPDC_IRQ_MASK1) & __raw_readl(EPDC_IRQ1);
++ luts2_ints_fired = __raw_readl(EPDC_IRQ_MASK2) & __raw_readl(EPDC_IRQ2);
++ }
++
++ if (!(ints_fired || luts1_ints_fired || luts2_ints_fired))
++ return IRQ_HANDLED;
++
++ if (__raw_readl(EPDC_IRQ) & EPDC_IRQ_TCE_UNDERRUN_IRQ) {
++ dev_err(fb_data->dev,
++ "TCE underrun! Will continue to update panel\n");
++ /* Clear TCE underrun IRQ */
++ __raw_writel(EPDC_IRQ_TCE_UNDERRUN_IRQ, EPDC_IRQ_CLEAR);
++ }
++
++ /* Check if we are waiting on EOF to sync a new update submission */
++ if (epdc_signal_eof()) {
++ epdc_eof_intr(false);
++ epdc_clear_eof_irq();
++ complete(&fb_data->eof_event);
++ }
++
++ /*
++ * Workaround for EPDC v2.0/v2.1 errata: Must read collision status
++ * before clearing IRQ, or else collision status for bits 16:63
++ * will be automatically cleared. So we read it here, and there is
++ * no conflict with using it in epdc_intr_work_func since the
++ * working buffer processing flow is strictly sequential (i.e.,
++ * only one WB processing done at a time, so the data grabbed
++ * here should be up-to-date and accurate when the WB processing
++ * completes. Also, note that there is no impact to other versions
++ * of EPDC by reading LUT status here.
++ */
++ if (fb_data->cur_update != NULL)
++ fb_data->epdc_colliding_luts = epdc_get_colliding_luts(fb_data->rev);
++
++ /* Clear the interrupt mask for any interrupts signalled */
++ __raw_writel(ints_fired, EPDC_IRQ_MASK_CLEAR);
++ __raw_writel(luts1_ints_fired, EPDC_IRQ_MASK1_CLEAR);
++ __raw_writel(luts2_ints_fired, EPDC_IRQ_MASK2_CLEAR);
++
++ dev_dbg(fb_data->dev, "EPDC interrupts fired = 0x%x, "
++ "LUTS1 fired = 0x%x, LUTS2 fired = 0x%x\n",
++ ints_fired, luts1_ints_fired, luts2_ints_fired);
++
++ queue_work(fb_data->epdc_intr_workqueue,
++ &fb_data->epdc_intr_work);
++
++ return IRQ_HANDLED;
++}
++
++static void epdc_intr_work_func(struct work_struct *work)
++{
++ struct mxc_epdc_fb_data *fb_data =
++ container_of(work, struct mxc_epdc_fb_data, epdc_intr_work);
++ struct update_data_list *collision_update;
++ struct mxcfb_rect *next_upd_region;
++ struct update_marker_data *next_marker;
++ struct update_marker_data *temp;
++ int temp_index;
++ u64 temp_mask;
++ u32 lut;
++ bool ignore_collision = false;
++ int i;
++ bool wb_lut_done = false;
++ bool free_update = true;
++ int next_lut, epdc_next_lut_15;
++ u32 epdc_luts_active, epdc_wb_busy, epdc_luts_avail, epdc_lut_cancelled;
++ u32 epdc_collision;
++ u64 epdc_irq_stat;
++ bool epdc_waiting_on_wb;
++ u32 coll_coord, coll_size;
++ struct mxcfb_rect coll_region;
++
++ /* Protect access to buffer queues and to update HW */
++ mutex_lock(&fb_data->queue_mutex);
++
++ /* Capture EPDC status one time to limit exposure to race conditions */
++ epdc_luts_active = epdc_any_luts_active(fb_data->rev);
++ epdc_wb_busy = epdc_is_working_buffer_busy();
++ epdc_lut_cancelled = epdc_is_lut_cancelled();
++ epdc_luts_avail = epdc_any_luts_available();
++ epdc_collision = epdc_is_collision();
++ if (fb_data->rev < 20)
++ epdc_irq_stat = __raw_readl(EPDC_IRQ);
++ else
++ epdc_irq_stat = (u64)__raw_readl(EPDC_IRQ1) |
++ ((u64)__raw_readl(EPDC_IRQ2) << 32);
++ epdc_waiting_on_wb = (fb_data->cur_update != NULL) ? true : false;
++
++ /* Free any LUTs that have completed */
++ for (i = 0; i < fb_data->num_luts; i++) {
++ if ((epdc_irq_stat & (1ULL << i)) == 0)
++ continue;
++
++ dev_dbg(fb_data->dev, "LUT %d completed\n", i);
++
++ /* Disable IRQ for completed LUT */
++ epdc_lut_complete_intr(fb_data->rev, i, false);
++
++ /*
++ * Go through all updates in the collision list and
++ * unmask any updates that were colliding with
++ * the completed LUT.
++ */
++ list_for_each_entry(collision_update,
++ &fb_data->upd_buf_collision_list, list) {
++ collision_update->collision_mask =
++ collision_update->collision_mask & ~(1 << i);
++ }
++
++ epdc_clear_lut_complete_irq(fb_data->rev, i);
++
++ fb_data->luts_complete_wb |= 1ULL << i;
++
++ fb_data->lut_update_order[i] = 0;
++
++ /* Signal completion if submit workqueue needs a LUT */
++ if (fb_data->waiting_for_lut) {
++ complete(&fb_data->update_res_free);
++ fb_data->waiting_for_lut = false;
++ }
++
++ /* Signal completion if LUT15 free and is needed */
++ if (fb_data->waiting_for_lut15 && (i == 15)) {
++ complete(&fb_data->lut15_free);
++ fb_data->waiting_for_lut15 = false;
++ }
++
++ /* Detect race condition where WB and its LUT complete
++ (i.e. full update completes) in one swoop */
++ if (epdc_waiting_on_wb &&
++ (i == fb_data->cur_update->lut_num))
++ wb_lut_done = true;
++
++ /* Signal completion if anyone waiting on this LUT */
++ if (!wb_lut_done)
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->full_marker_list,
++ full_list) {
++ if (next_marker->lut_num != i)
++ continue;
++
++ /* Found marker to signal - remove from list */
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev, "Signaling marker %d\n",
++ next_marker->update_marker);
++ if (next_marker->waiting)
++ complete(&next_marker->update_completion);
++ else
++ kfree(next_marker);
++ }
++ }
++
++ /* Check to see if all updates have completed */
++ if (list_empty(&fb_data->upd_pending_list) &&
++ is_free_list_full(fb_data) &&
++ !epdc_waiting_on_wb &&
++ !epdc_luts_active) {
++
++ fb_data->updates_active = false;
++
++ if (fb_data->pwrdown_delay != FB_POWERDOWN_DISABLE) {
++ /*
++ * Set variable to prevent overlapping
++ * enable/disable requests
++ */
++ fb_data->powering_down = true;
++
++ /* Schedule task to disable EPDC HW until next update */
++ schedule_delayed_work(&fb_data->epdc_done_work,
++ msecs_to_jiffies(fb_data->pwrdown_delay));
++
++ /* Reset counter to reduce chance of overflow */
++ fb_data->order_cnt = 0;
++ }
++
++ if (fb_data->waiting_for_idle)
++ complete(&fb_data->updates_done);
++ }
++
++ /* Is Working Buffer busy? */
++ if (epdc_wb_busy) {
++ /* Can't submit another update until WB is done */
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /*
++ * Were we waiting on working buffer?
++ * If so, update queues and check for collisions
++ */
++ if (epdc_waiting_on_wb) {
++ dev_dbg(fb_data->dev, "\nWorking buffer completed\n");
++
++ /* Signal completion if submit workqueue was waiting on WB */
++ if (fb_data->waiting_for_wb) {
++ complete(&fb_data->update_res_free);
++ fb_data->waiting_for_wb = false;
++ }
++
++ if (fb_data->cur_update->update_desc->upd_data.flags
++ & EPDC_FLAG_TEST_COLLISION) {
++ /* This was a dry run to test for collision */
++
++ /* Signal marker */
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->full_marker_list,
++ full_list) {
++ if (next_marker->lut_num != DRY_RUN_NO_LUT)
++ continue;
++
++ if (epdc_collision)
++ next_marker->collision_test = true;
++ else
++ next_marker->collision_test = false;
++
++ dev_dbg(fb_data->dev,
++ "In IRQ, collision_test = %d\n",
++ next_marker->collision_test);
++
++ /* Found marker to signal - remove from list */
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev, "Signaling marker "
++ "for dry-run - %d\n",
++ next_marker->update_marker);
++ complete(&next_marker->update_completion);
++ }
++ } else if (epdc_lut_cancelled && !epdc_collision) {
++ /*
++ * Note: The update may be cancelled (void) if all
++ * pixels collided. In that case we handle it as a
++ * collision, not a cancel.
++ */
++
++ /* Clear LUT status (might be set if no AUTOWV used) */
++
++ /*
++ * Disable and clear IRQ for the LUT used.
++ * Even though LUT is cancelled in HW, the LUT
++ * complete bit may be set if AUTOWV not used.
++ */
++ epdc_lut_complete_intr(fb_data->rev,
++ fb_data->cur_update->lut_num, false);
++ epdc_clear_lut_complete_irq(fb_data->rev,
++ fb_data->cur_update->lut_num);
++
++ fb_data->lut_update_order[fb_data->cur_update->lut_num] = 0;
++
++ /* Signal completion if submit workqueue needs a LUT */
++ if (fb_data->waiting_for_lut) {
++ complete(&fb_data->update_res_free);
++ fb_data->waiting_for_lut = false;
++ }
++
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list,
++ upd_list) {
++
++ /* Del from per-update & full list */
++ list_del_init(&next_marker->upd_list);
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev,
++ "Signaling marker (cancelled) %d\n",
++ next_marker->update_marker);
++ if (next_marker->waiting)
++ complete(&next_marker->update_completion);
++ else
++ kfree(next_marker);
++ }
++ } else if (epdc_collision) {
++ /* Real update (no dry-run), collision occurred */
++
++ /* Check list of colliding LUTs, and add to our collision mask */
++ fb_data->cur_update->collision_mask =
++ fb_data->epdc_colliding_luts;
++
++ /* Clear collisions that completed since WB began */
++ fb_data->cur_update->collision_mask &=
++ ~fb_data->luts_complete_wb;
++
++ dev_dbg(fb_data->dev, "Collision mask = 0x%llx\n",
++ fb_data->epdc_colliding_luts);
++
++ /* For EPDC 2.0 and later, minimum collision bounds
++ are provided by HW. Recompute new bounds here. */
++ if ((fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT)
++ && (fb_data->rev >= 20)) {
++ u32 xres, yres, rotate;
++ struct mxcfb_rect *cur_upd_rect =
++ &fb_data->cur_update->update_desc->upd_data.update_region;
++
++ /* Get collision region coords from EPDC */
++ coll_coord = __raw_readl(EPDC_UPD_COL_CORD);
++ coll_size = __raw_readl(EPDC_UPD_COL_SIZE);
++ coll_region.left =
++ (coll_coord & EPDC_UPD_COL_CORD_XCORD_MASK)
++ >> EPDC_UPD_COL_CORD_XCORD_OFFSET;
++ coll_region.top =
++ (coll_coord & EPDC_UPD_COL_CORD_YCORD_MASK)
++ >> EPDC_UPD_COL_CORD_YCORD_OFFSET;
++ coll_region.width =
++ (coll_size & EPDC_UPD_COL_SIZE_WIDTH_MASK)
++ >> EPDC_UPD_COL_SIZE_WIDTH_OFFSET;
++ coll_region.height =
++ (coll_size & EPDC_UPD_COL_SIZE_HEIGHT_MASK)
++ >> EPDC_UPD_COL_SIZE_HEIGHT_OFFSET;
++ dev_dbg(fb_data->dev, "Coll region: l = %d, "
++ "t = %d, w = %d, h = %d\n",
++ coll_region.left, coll_region.top,
++ coll_region.width, coll_region.height);
++
++ /* Convert coords back to orig orientation */
++ switch (fb_data->epdc_fb_var.rotate) {
++ case FB_ROTATE_CW:
++ xres = fb_data->epdc_fb_var.yres;
++ yres = fb_data->epdc_fb_var.xres;
++ rotate = FB_ROTATE_CCW;
++ break;
++ case FB_ROTATE_UD:
++ xres = fb_data->epdc_fb_var.xres;
++ yres = fb_data->epdc_fb_var.yres;
++ rotate = FB_ROTATE_UD;
++ break;
++ case FB_ROTATE_CCW:
++ xres = fb_data->epdc_fb_var.yres;
++ yres = fb_data->epdc_fb_var.xres;
++ rotate = FB_ROTATE_CW;
++ break;
++ default:
++ xres = fb_data->epdc_fb_var.xres;
++ yres = fb_data->epdc_fb_var.yres;
++ rotate = FB_ROTATE_UR;
++ break;
++ }
++ adjust_coordinates(xres, yres, rotate,
++ &coll_region, cur_upd_rect);
++
++ dev_dbg(fb_data->dev, "Adj coll region: l = %d, "
++ "t = %d, w = %d, h = %d\n",
++ cur_upd_rect->left, cur_upd_rect->top,
++ cur_upd_rect->width,
++ cur_upd_rect->height);
++ }
++
++ /*
++ * If we collide with newer updates, then
++ * we don't need to re-submit the update. The
++ * idea is that the newer updates should take
++ * precedence anyways, so we don't want to
++ * overwrite them.
++ */
++ for (temp_mask = fb_data->cur_update->collision_mask, lut = 0;
++ temp_mask != 0;
++ lut++, temp_mask = temp_mask >> 1) {
++ if (!(temp_mask & 0x1))
++ continue;
++
++ if (fb_data->lut_update_order[lut] >=
++ fb_data->cur_update->update_desc->update_order) {
++ dev_dbg(fb_data->dev,
++ "Ignoring collision with"
++ "newer update.\n");
++ ignore_collision = true;
++ break;
++ }
++ }
++
++ if (!ignore_collision) {
++ free_update = false;
++ /*
++ * If update has markers, clear the LUTs to
++ * avoid signalling that they have completed.
++ */
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list,
++ upd_list)
++ next_marker->lut_num = INVALID_LUT;
++
++ /* Move to collision list */
++ list_add_tail(&fb_data->cur_update->list,
++ &fb_data->upd_buf_collision_list);
++ }
++ }
++
++ /* Do we need to free the current update descriptor? */
++ if (free_update) {
++ /* Handle condition where WB & LUT are both complete */
++ if (wb_lut_done)
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list,
++ upd_list) {
++
++ /* Del from per-update & full list */
++ list_del_init(&next_marker->upd_list);
++ list_del_init(&next_marker->full_list);
++
++ /* Signal completion of update */
++ dev_dbg(fb_data->dev,
++ "Signaling marker (wb) %d\n",
++ next_marker->update_marker);
++ if (next_marker->waiting)
++ complete(&next_marker->update_completion);
++ else
++ kfree(next_marker);
++ }
++
++ /* Free marker list and update descriptor */
++ kfree(fb_data->cur_update->update_desc);
++
++ /* Add to free buffer list */
++ list_add_tail(&fb_data->cur_update->list,
++ &fb_data->upd_buf_free_list);
++
++ /* Check to see if all updates have completed */
++ if (list_empty(&fb_data->upd_pending_list) &&
++ is_free_list_full(fb_data) &&
++ !epdc_luts_active) {
++
++ fb_data->updates_active = false;
++
++ if (fb_data->pwrdown_delay !=
++ FB_POWERDOWN_DISABLE) {
++ /*
++ * Set variable to prevent overlapping
++ * enable/disable requests
++ */
++ fb_data->powering_down = true;
++
++ /* Schedule EPDC disable */
++ schedule_delayed_work(&fb_data->epdc_done_work,
++ msecs_to_jiffies(fb_data->pwrdown_delay));
++
++ /* Reset counter to reduce chance of overflow */
++ fb_data->order_cnt = 0;
++ }
++
++ if (fb_data->waiting_for_idle)
++ complete(&fb_data->updates_done);
++ }
++ }
++
++ /* Clear current update */
++ fb_data->cur_update = NULL;
++
++ /* Clear IRQ for working buffer */
++ epdc_working_buf_intr(false);
++ epdc_clear_working_buf_irq();
++ }
++
++ if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) {
++ /* Queued update scheme processing */
++
++ /* Schedule task to submit collision and pending update */
++ if (!fb_data->powering_down)
++ queue_work(fb_data->epdc_submit_workqueue,
++ &fb_data->epdc_submit_work);
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return;
++ }
++
++ /* Snapshot update scheme processing */
++
++ /* Check to see if any LUTs are free */
++ if (!epdc_luts_avail) {
++ dev_dbg(fb_data->dev, "No luts available.\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ epdc_next_lut_15 = epdc_choose_next_lut(fb_data->rev, &next_lut);
++ /* Check to see if there is a valid LUT to use */
++ if (epdc_next_lut_15 && fb_data->tce_prevent && (fb_data->rev < 20)) {
++ dev_dbg(fb_data->dev, "Must wait for LUT15\n");
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ }
++
++ /*
++ * Are any of our collision updates able to go now?
++ * Go through all updates in the collision list and check to see
++ * if the collision mask has been fully cleared
++ */
++ list_for_each_entry(collision_update,
++ &fb_data->upd_buf_collision_list, list) {
++
++ if (collision_update->collision_mask != 0)
++ continue;
++
++ dev_dbg(fb_data->dev, "A collision update is ready to go!\n");
++ /*
++ * We have a collision cleared, so select it
++ * and we will retry the update
++ */
++ fb_data->cur_update = collision_update;
++ list_del_init(&fb_data->cur_update->list);
++ break;
++ }
++
++ /*
++ * If we didn't find a collision update ready to go,
++ * we try to grab one from the update queue
++ */
++ if (fb_data->cur_update == NULL) {
++ /* Is update list empty? */
++ if (list_empty(&fb_data->upd_buf_queue)) {
++ dev_dbg(fb_data->dev, "No pending updates.\n");
++
++ /* No updates pending, so we are done */
++ mutex_unlock(&fb_data->queue_mutex);
++ return;
++ } else {
++ dev_dbg(fb_data->dev, "Found a pending update!\n");
++
++ /* Process next item in update list */
++ fb_data->cur_update =
++ list_entry(fb_data->upd_buf_queue.next,
++ struct update_data_list, list);
++ list_del_init(&fb_data->cur_update->list);
++ }
++ }
++
++ /* Use LUT selected above */
++ fb_data->cur_update->lut_num = next_lut;
++
++ /* Associate LUT with update markers */
++ list_for_each_entry_safe(next_marker, temp,
++ &fb_data->cur_update->update_desc->upd_marker_list, upd_list)
++ next_marker->lut_num = fb_data->cur_update->lut_num;
++
++ /* Mark LUT as containing new update */
++ fb_data->lut_update_order[fb_data->cur_update->lut_num] =
++ fb_data->cur_update->update_desc->update_order;
++
++ /* Enable Collision and WB complete IRQs */
++ epdc_working_buf_intr(true);
++ epdc_lut_complete_intr(fb_data->rev, fb_data->cur_update->lut_num, true);
++
++ /* Program EPDC update to process buffer */
++ next_upd_region =
++ &fb_data->cur_update->update_desc->upd_data.update_region;
++ if (fb_data->cur_update->update_desc->upd_data.temp
++ != TEMP_USE_AMBIENT) {
++ temp_index = mxc_epdc_fb_get_temp_index(fb_data,
++ fb_data->cur_update->update_desc->upd_data.temp);
++ epdc_set_temp(temp_index);
++ } else
++ epdc_set_temp(fb_data->temp_index);
++ epdc_set_update_addr(fb_data->cur_update->phys_addr +
++ fb_data->cur_update->update_desc->epdc_offs);
++ epdc_set_update_coord(next_upd_region->left, next_upd_region->top);
++ epdc_set_update_dimensions(next_upd_region->width,
++ next_upd_region->height);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(fb_data->cur_update->update_desc->epdc_stride);
++ if (fb_data->wv_modes_update &&
++ (fb_data->cur_update->update_desc->upd_data.waveform_mode
++ == WAVEFORM_MODE_AUTO)) {
++ epdc_set_update_waveform(&fb_data->wv_modes);
++ fb_data->wv_modes_update = false;
++ }
++
++ epdc_submit_update(fb_data->cur_update->lut_num,
++ fb_data->cur_update->update_desc->upd_data.waveform_mode,
++ fb_data->cur_update->update_desc->upd_data.update_mode,
++ false, false, 0);
++
++ /* Release buffer queues */
++ mutex_unlock(&fb_data->queue_mutex);
++
++ return;
++}
++
++static void draw_mode0(struct mxc_epdc_fb_data *fb_data)
++{
++ u32 *upd_buf_ptr;
++ int i;
++ struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
++ u32 xres, yres;
++
++ upd_buf_ptr = (u32 *)fb_data->info.screen_base;
++
++ epdc_working_buf_intr(true);
++ epdc_lut_complete_intr(fb_data->rev, 0, true);
++
++ /* Use unrotated (native) width/height */
++ if ((screeninfo->rotate == FB_ROTATE_CW) ||
++ (screeninfo->rotate == FB_ROTATE_CCW)) {
++ xres = screeninfo->yres;
++ yres = screeninfo->xres;
++ } else {
++ xres = screeninfo->xres;
++ yres = screeninfo->yres;
++ }
++
++ /* Program EPDC update to process buffer */
++ epdc_set_update_addr(fb_data->phys_start);
++ epdc_set_update_coord(0, 0);
++ epdc_set_update_dimensions(xres, yres);
++ if (fb_data->rev > 20)
++ epdc_set_update_stride(0);
++ epdc_submit_update(0, fb_data->wv_modes.mode_init, UPDATE_MODE_FULL,
++ false, true, 0xFF);
++
++ dev_dbg(fb_data->dev, "Mode0 update - Waiting for LUT to complete...\n");
++
++ /* Will timeout after ~4-5 seconds */
++
++ for (i = 0; i < 40; i++) {
++ if (!epdc_is_lut_active(0)) {
++ dev_dbg(fb_data->dev, "Mode0 init complete\n");
++ return;
++ }
++ msleep(100);
++ }
++
++ dev_err(fb_data->dev, "Mode0 init failed!\n");
++
++ return;
++}
++
++
++static void mxc_epdc_fb_fw_handler(const struct firmware *fw,
++ void *context)
++{
++ struct mxc_epdc_fb_data *fb_data = context;
++ int ret;
++ struct mxcfb_waveform_data_file *wv_file;
++ int wv_data_offs;
++ int i;
++ struct mxcfb_update_data update;
++ struct mxcfb_update_marker_data upd_marker_data;
++ struct fb_var_screeninfo *screeninfo = &fb_data->epdc_fb_var;
++ u32 xres, yres;
++ struct clk *epdc_parent;
++ unsigned long rounded_parent_rate, epdc_pix_rate,
++ rounded_pix_clk, target_pix_clk;
++
++ if (fw == NULL) {
++ /* If default FW file load failed, we give up */
++ if (fb_data->fw_default_load)
++ return;
++
++ /* Try to load default waveform */
++ dev_dbg(fb_data->dev,
++ "Can't find firmware. Trying fallback fw\n");
++ fb_data->fw_default_load = true;
++ ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
++ "imx/epdc.fw", fb_data->dev, GFP_KERNEL, fb_data,
++ mxc_epdc_fb_fw_handler);
++ if (ret)
++ dev_err(fb_data->dev,
++ "Failed request_firmware_nowait err %d\n", ret);
++
++ return;
++ }
++
++ wv_file = (struct mxcfb_waveform_data_file *)fw->data;
++
++ /* Get size and allocate temperature range table */
++ fb_data->trt_entries = wv_file->wdh.trc + 1;
++ fb_data->temp_range_bounds = kzalloc(fb_data->trt_entries, GFP_KERNEL);
++
++ for (i = 0; i < fb_data->trt_entries; i++)
++ dev_dbg(fb_data->dev, "trt entry #%d = 0x%x\n", i, *((u8 *)&wv_file->data + i));
++
++ /* Copy TRT data */
++ memcpy(fb_data->temp_range_bounds, &wv_file->data, fb_data->trt_entries);
++
++ /* Set default temperature index using TRT and room temp */
++ fb_data->temp_index = mxc_epdc_fb_get_temp_index(fb_data, DEFAULT_TEMP);
++
++ /* Get offset and size for waveform data */
++ wv_data_offs = sizeof(wv_file->wdh) + fb_data->trt_entries + 1;
++ fb_data->waveform_buffer_size = fw->size - wv_data_offs;
++
++ /* Allocate memory for waveform data */
++ fb_data->waveform_buffer_virt = dma_alloc_coherent(fb_data->dev,
++ fb_data->waveform_buffer_size,
++ &fb_data->waveform_buffer_phys,
++ GFP_DMA | GFP_KERNEL);
++ if (fb_data->waveform_buffer_virt == NULL) {
++ dev_err(fb_data->dev, "Can't allocate mem for waveform!\n");
++ return;
++ }
++
++ memcpy(fb_data->waveform_buffer_virt, (u8 *)(fw->data) + wv_data_offs,
++ fb_data->waveform_buffer_size);
++
++ release_firmware(fw);
++
++ /* Enable clocks to access EPDC regs */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++
++ target_pix_clk = fb_data->cur_mode->vmode->pixclock;
++ /* Enable pix clk for EPDC */
++ rounded_pix_clk = clk_round_rate(fb_data->epdc_clk_pix, target_pix_clk);
++
++ if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) ||
++ (rounded_pix_clk <= target_pix_clk - target_pix_clk/100))) {
++ /* Can't get close enough without changing parent clk */
++ epdc_parent = clk_get_parent(fb_data->epdc_clk_pix);
++ rounded_parent_rate = clk_round_rate(epdc_parent, target_pix_clk);
++
++ epdc_pix_rate = target_pix_clk;
++ while (epdc_pix_rate < rounded_parent_rate)
++ epdc_pix_rate *= 2;
++ clk_set_rate(epdc_parent, epdc_pix_rate);
++
++ rounded_pix_clk = clk_round_rate(fb_data->epdc_clk_pix, target_pix_clk);
++ if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) ||
++ (rounded_pix_clk <= target_pix_clk - target_pix_clk/100)))
++ /* Still can't get a good clock, provide warning */
++ dev_err(fb_data->dev, "Unable to get an accurate EPDC pix clk"
++ "desired = %lu, actual = %lu\n", target_pix_clk,
++ rounded_pix_clk);
++ }
++
++ clk_set_rate(fb_data->epdc_clk_pix, rounded_pix_clk);
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++
++ epdc_init_sequence(fb_data);
++
++ /* Disable clocks */
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++
++ fb_data->hw_ready = true;
++ fb_data->hw_initializing = false;
++
++ /* Use unrotated (native) width/height */
++ if ((screeninfo->rotate == FB_ROTATE_CW) ||
++ (screeninfo->rotate == FB_ROTATE_CCW)) {
++ xres = screeninfo->yres;
++ yres = screeninfo->xres;
++ } else {
++ xres = screeninfo->xres;
++ yres = screeninfo->yres;
++ }
++
++ update.update_region.left = 0;
++ update.update_region.width = xres;
++ update.update_region.top = 0;
++ update.update_region.height = yres;
++ update.update_mode = UPDATE_MODE_FULL;
++ update.waveform_mode = WAVEFORM_MODE_AUTO;
++ update.update_marker = INIT_UPDATE_MARKER;
++ update.temp = TEMP_USE_AMBIENT;
++ update.flags = 0;
++
++ upd_marker_data.update_marker = update.update_marker;
++
++ mxc_epdc_fb_send_update(&update, &fb_data->info);
++
++ /* Block on initial update */
++ ret = mxc_epdc_fb_wait_update_complete(&upd_marker_data,
++ &fb_data->info);
++ if (ret < 0)
++ dev_err(fb_data->dev,
++ "Wait for initial update complete failed."
++ " Error = 0x%x", ret);
++}
++
++static int mxc_epdc_fb_init_hw(struct fb_info *info)
++{
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++ int ret;
++
++ /*
++ * Create fw search string based on ID string in selected videomode.
++ * Format is "imx/epdc_[panel string].fw"
++ */
++ if (fb_data->cur_mode) {
++ strcat(fb_data->fw_str, "imx/epdc_");
++ strcat(fb_data->fw_str, fb_data->cur_mode->vmode->name);
++ strcat(fb_data->fw_str, ".fw");
++ }
++
++ fb_data->fw_default_load = false;
++
++ ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
++ fb_data->fw_str, fb_data->dev, GFP_KERNEL,
++ fb_data, mxc_epdc_fb_fw_handler);
++ if (ret)
++ dev_dbg(fb_data->dev,
++ "Failed request_firmware_nowait err %d\n", ret);
++
++ return ret;
++}
++
++static ssize_t store_update(struct device *device,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct mxcfb_update_data update;
++ struct fb_info *info = dev_get_drvdata(device);
++ struct mxc_epdc_fb_data *fb_data = (struct mxc_epdc_fb_data *)info;
++
++ if (strncmp(buf, "direct", 6) == 0)
++ update.waveform_mode = fb_data->wv_modes.mode_du;
++ else if (strncmp(buf, "gc16", 4) == 0)
++ update.waveform_mode = fb_data->wv_modes.mode_gc16;
++ else if (strncmp(buf, "gc4", 3) == 0)
++ update.waveform_mode = fb_data->wv_modes.mode_gc4;
++
++ /* Now, request full screen update */
++ update.update_region.left = 0;
++ update.update_region.width = fb_data->epdc_fb_var.xres;
++ update.update_region.top = 0;
++ update.update_region.height = fb_data->epdc_fb_var.yres;
++ update.update_mode = UPDATE_MODE_FULL;
++ update.temp = TEMP_USE_AMBIENT;
++ update.update_marker = 0;
++ update.flags = 0;
++
++ mxc_epdc_fb_send_update(&update, info);
++
++ return count;
++}
++
++static struct device_attribute fb_attrs[] = {
++ __ATTR(update, S_IRUGO|S_IWUSR, NULL, store_update),
++};
++
++static const struct of_device_id imx_epdc_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-epdc", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_epdc_dt_ids);
++
++int mxc_epdc_fb_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++ struct pinctrl *pinctrl;
++ struct mxc_epdc_fb_data *fb_data;
++ struct resource *res;
++ struct fb_info *info;
++ char *options, *opt;
++ char *panel_str = NULL;
++ char name[] = "mxcepdcfb";
++ struct fb_videomode *vmode;
++ int xres_virt, yres_virt, buf_size;
++ int xres_virt_rot, yres_virt_rot, pix_size_rot;
++ struct fb_var_screeninfo *var_info;
++ struct fb_fix_screeninfo *fix_info;
++ struct pxp_config_data *pxp_conf;
++ struct pxp_proc_data *proc_data;
++ struct scatterlist *sg;
++ struct update_data_list *upd_list;
++ struct update_data_list *plist, *temp_list;
++ int i;
++ unsigned long x_mem_size = 0;
++ u32 val;
++ int irq;
++
++ fb_data = (struct mxc_epdc_fb_data *)framebuffer_alloc(
++ sizeof(struct mxc_epdc_fb_data), &pdev->dev);
++ if (fb_data == NULL) {
++ ret = -ENOMEM;
++ goto out;
++ }
++
++ /* Get platform data and check validity */
++ fb_data->pdata = &epdc_data;
++ if ((fb_data->pdata == NULL) || (fb_data->pdata->num_modes < 1)
++ || (fb_data->pdata->epdc_mode == NULL)
++ || (fb_data->pdata->epdc_mode->vmode == NULL)) {
++ ret = -EINVAL;
++ goto out_fbdata;
++ }
++
++ if (fb_get_options(name, &options)) {
++ ret = -ENODEV;
++ goto out_fbdata;
++ }
++
++ fb_data->tce_prevent = 0;
++
++ if (options)
++ while ((opt = strsep(&options, ",")) != NULL) {
++ if (!*opt)
++ continue;
++
++ if (!strncmp(opt, "bpp=", 4))
++ fb_data->default_bpp =
++ simple_strtoul(opt + 4, NULL, 0);
++ else if (!strncmp(opt, "x_mem=", 6))
++ x_mem_size = memparse(opt + 6, NULL);
++ else if (!strncmp(opt, "tce_prevent", 11))
++ fb_data->tce_prevent = 1;
++ else
++ panel_str = opt;
++ }
++
++ fb_data->dev = &pdev->dev;
++
++ if (!fb_data->default_bpp)
++ fb_data->default_bpp = 16;
++
++ /* Set default (first defined mode) before searching for a match */
++ fb_data->cur_mode = &fb_data->pdata->epdc_mode[0];
++
++ if (panel_str)
++ for (i = 0; i < fb_data->pdata->num_modes; i++)
++ if (!strcmp(fb_data->pdata->epdc_mode[i].vmode->name,
++ panel_str)) {
++ fb_data->cur_mode =
++ &fb_data->pdata->epdc_mode[i];
++ break;
++ }
++
++ vmode = fb_data->cur_mode->vmode;
++
++ platform_set_drvdata(pdev, fb_data);
++ info = &fb_data->info;
++
++ /* Allocate color map for the FB */
++ ret = fb_alloc_cmap(&info->cmap, 256, 0);
++ if (ret)
++ goto out_fbdata;
++
++ dev_dbg(&pdev->dev, "resolution %dx%d, bpp %d\n",
++ vmode->xres, vmode->yres, fb_data->default_bpp);
++
++ /*
++ * GPU alignment restrictions dictate framebuffer parameters:
++ * - 32-byte alignment for buffer width
++ * - 128-byte alignment for buffer height
++ * => 4K buffer alignment for buffer start
++ */
++ xres_virt = ALIGN(vmode->xres, 32);
++ yres_virt = ALIGN(vmode->yres, 128);
++ fb_data->max_pix_size = PAGE_ALIGN(xres_virt * yres_virt);
++
++ /*
++ * Have to check to see if aligned buffer size when rotated
++ * is bigger than when not rotated, and use the max
++ */
++ xres_virt_rot = ALIGN(vmode->yres, 32);
++ yres_virt_rot = ALIGN(vmode->xres, 128);
++ pix_size_rot = PAGE_ALIGN(xres_virt_rot * yres_virt_rot);
++ fb_data->max_pix_size = (fb_data->max_pix_size > pix_size_rot) ?
++ fb_data->max_pix_size : pix_size_rot;
++
++ buf_size = fb_data->max_pix_size * fb_data->default_bpp/8;
++
++ /* Compute the number of screens needed based on X memory requested */
++ if (x_mem_size > 0) {
++ fb_data->num_screens = DIV_ROUND_UP(x_mem_size, buf_size);
++ if (fb_data->num_screens < NUM_SCREENS_MIN)
++ fb_data->num_screens = NUM_SCREENS_MIN;
++ else if (buf_size * fb_data->num_screens > SZ_16M)
++ fb_data->num_screens = SZ_16M / buf_size;
++ } else
++ fb_data->num_screens = NUM_SCREENS_MIN;
++
++ fb_data->map_size = buf_size * fb_data->num_screens;
++ dev_dbg(&pdev->dev, "memory to allocate: %d\n", fb_data->map_size);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res == NULL) {
++ ret = -ENODEV;
++ goto out_cmap;
++ }
++
++ epdc_base = devm_request_and_ioremap(&pdev->dev, res);
++ if (epdc_base == NULL) {
++ ret = -ENOMEM;
++ goto out_cmap;
++ }
++
++ /* Allocate FB memory */
++ info->screen_base = dma_alloc_writecombine(&pdev->dev,
++ fb_data->map_size,
++ &fb_data->phys_start,
++ GFP_DMA | GFP_KERNEL);
++
++ if (info->screen_base == NULL) {
++ ret = -ENOMEM;
++ goto out_cmap;
++ }
++ dev_dbg(&pdev->dev, "allocated at %p:0x%x\n", info->screen_base,
++ fb_data->phys_start);
++
++ var_info = &info->var;
++ var_info->activate = FB_ACTIVATE_TEST;
++ var_info->bits_per_pixel = fb_data->default_bpp;
++ var_info->xres = vmode->xres;
++ var_info->yres = vmode->yres;
++ var_info->xres_virtual = xres_virt;
++ /* Additional screens allow for panning and buffer flipping */
++ var_info->yres_virtual = yres_virt * fb_data->num_screens;
++
++ var_info->pixclock = vmode->pixclock;
++ var_info->left_margin = vmode->left_margin;
++ var_info->right_margin = vmode->right_margin;
++ var_info->upper_margin = vmode->upper_margin;
++ var_info->lower_margin = vmode->lower_margin;
++ var_info->hsync_len = vmode->hsync_len;
++ var_info->vsync_len = vmode->vsync_len;
++ var_info->vmode = FB_VMODE_NONINTERLACED;
++
++ switch (fb_data->default_bpp) {
++ case 32:
++ case 24:
++ var_info->red.offset = 16;
++ var_info->red.length = 8;
++ var_info->green.offset = 8;
++ var_info->green.length = 8;
++ var_info->blue.offset = 0;
++ var_info->blue.length = 8;
++ break;
++
++ case 16:
++ var_info->red.offset = 11;
++ var_info->red.length = 5;
++ var_info->green.offset = 5;
++ var_info->green.length = 6;
++ var_info->blue.offset = 0;
++ var_info->blue.length = 5;
++ break;
++
++ case 8:
++ /*
++ * For 8-bit grayscale, R, G, and B offset are equal.
++ *
++ */
++ var_info->grayscale = GRAYSCALE_8BIT;
++
++ var_info->red.length = 8;
++ var_info->red.offset = 0;
++ var_info->red.msb_right = 0;
++ var_info->green.length = 8;
++ var_info->green.offset = 0;
++ var_info->green.msb_right = 0;
++ var_info->blue.length = 8;
++ var_info->blue.offset = 0;
++ var_info->blue.msb_right = 0;
++ break;
++
++ default:
++ dev_err(&pdev->dev, "unsupported bitwidth %d\n",
++ fb_data->default_bpp);
++ ret = -EINVAL;
++ goto out_dma_fb;
++ }
++
++ fix_info = &info->fix;
++
++ strcpy(fix_info->id, "mxc_epdc_fb");
++ fix_info->type = FB_TYPE_PACKED_PIXELS;
++ fix_info->visual = FB_VISUAL_TRUECOLOR;
++ fix_info->xpanstep = 0;
++ fix_info->ypanstep = 0;
++ fix_info->ywrapstep = 0;
++ fix_info->accel = FB_ACCEL_NONE;
++ fix_info->smem_start = fb_data->phys_start;
++ fix_info->smem_len = fb_data->map_size;
++ fix_info->ypanstep = 0;
++
++ fb_data->native_width = vmode->xres;
++ fb_data->native_height = vmode->yres;
++
++ info->fbops = &mxc_epdc_fb_ops;
++ info->var.activate = FB_ACTIVATE_NOW;
++ info->pseudo_palette = fb_data->pseudo_palette;
++ info->screen_size = info->fix.smem_len;
++ info->flags = FBINFO_FLAG_DEFAULT;
++
++ mxc_epdc_fb_set_fix(info);
++
++ fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE;
++ fb_data->upd_scheme = UPDATE_SCHEME_QUEUE_AND_MERGE;
++
++ /* Initialize our internal copy of the screeninfo */
++ fb_data->epdc_fb_var = *var_info;
++ fb_data->fb_offset = 0;
++ fb_data->eof_sync_period = 0;
++
++ fb_data->epdc_clk_axi = clk_get(fb_data->dev, "epdc_axi");
++ if (IS_ERR(fb_data->epdc_clk_axi)) {
++ dev_err(&pdev->dev, "Unable to get EPDC AXI clk."
++ "err = %d\n", (int)fb_data->epdc_clk_axi);
++ ret = -ENODEV;
++ goto out_dma_fb;
++ }
++ fb_data->epdc_clk_pix = clk_get(fb_data->dev, "epdc_pix");
++ if (IS_ERR(fb_data->epdc_clk_pix)) {
++ dev_err(&pdev->dev, "Unable to get EPDC pix clk."
++ "err = %d\n", (int)fb_data->epdc_clk_pix);
++ ret = -ENODEV;
++ goto out_dma_fb;
++ }
++
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ val = __raw_readl(EPDC_VERSION);
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++ fb_data->rev = ((val & EPDC_VERSION_MAJOR_MASK) >>
++ EPDC_VERSION_MAJOR_OFFSET) * 10
++ + ((val & EPDC_VERSION_MINOR_MASK) >>
++ EPDC_VERSION_MINOR_OFFSET);
++ dev_dbg(&pdev->dev, "EPDC version = %d\n", fb_data->rev);
++
++ if (fb_data->rev < 20) {
++ fb_data->num_luts = EPDC_V1_NUM_LUTS;
++ fb_data->max_num_updates = EPDC_V1_MAX_NUM_UPDATES;
++ } else {
++ fb_data->num_luts = EPDC_V2_NUM_LUTS;
++ fb_data->max_num_updates = EPDC_V2_MAX_NUM_UPDATES;
++ if (vmode->xres > EPDC_V2_MAX_UPDATE_WIDTH)
++ fb_data->restrict_width = true;
++ }
++ fb_data->max_num_buffers = EPDC_MAX_NUM_BUFFERS;
++
++ /*
++ * Initialize lists for pending updates,
++ * active update requests, update collisions,
++ * and freely available updates.
++ */
++ INIT_LIST_HEAD(&fb_data->upd_pending_list);
++ INIT_LIST_HEAD(&fb_data->upd_buf_queue);
++ INIT_LIST_HEAD(&fb_data->upd_buf_free_list);
++ INIT_LIST_HEAD(&fb_data->upd_buf_collision_list);
++
++ /* Allocate update buffers and add them to the list */
++ for (i = 0; i < fb_data->max_num_updates; i++) {
++ upd_list = kzalloc(sizeof(*upd_list), GFP_KERNEL);
++ if (upd_list == NULL) {
++ ret = -ENOMEM;
++ goto out_upd_lists;
++ }
++
++ /* Add newly allocated buffer to free list */
++ list_add(&upd_list->list, &fb_data->upd_buf_free_list);
++ }
++
++ fb_data->virt_addr_updbuf =
++ kzalloc(sizeof(void *) * fb_data->max_num_buffers, GFP_KERNEL);
++ fb_data->phys_addr_updbuf =
++ kzalloc(sizeof(dma_addr_t) * fb_data->max_num_buffers,
++ GFP_KERNEL);
++ for (i = 0; i < fb_data->max_num_buffers; i++) {
++ /*
++ * Allocate memory for PxP output buffer.
++ * Each update buffer is 1 byte per pixel, and can
++ * be as big as the full-screen frame buffer
++ */
++ fb_data->virt_addr_updbuf[i] =
++ kmalloc(fb_data->max_pix_size, GFP_KERNEL);
++ fb_data->phys_addr_updbuf[i] =
++ virt_to_phys(fb_data->virt_addr_updbuf[i]);
++ if (fb_data->virt_addr_updbuf[i] == NULL) {
++ ret = -ENOMEM;
++ goto out_upd_buffers;
++ }
++
++ dev_dbg(fb_data->info.device, "allocated %d bytes @ 0x%08X\n",
++ fb_data->max_pix_size, fb_data->phys_addr_updbuf[i]);
++ }
++
++ /* Counter indicating which update buffer should be used next. */
++ fb_data->upd_buffer_num = 0;
++
++ /*
++ * Allocate memory for PxP SW workaround buffer
++ * These buffers are used to hold copy of the update region,
++ * before sending it to PxP for processing.
++ */
++ fb_data->virt_addr_copybuf =
++ dma_alloc_coherent(fb_data->info.device, fb_data->max_pix_size*2,
++ &fb_data->phys_addr_copybuf,
++ GFP_DMA | GFP_KERNEL);
++ if (fb_data->virt_addr_copybuf == NULL) {
++ ret = -ENOMEM;
++ goto out_upd_buffers;
++ }
++
++ fb_data->working_buffer_size = vmode->yres * vmode->xres * 2;
++ /* Allocate memory for EPDC working buffer */
++ fb_data->working_buffer_virt =
++ dma_alloc_coherent(&pdev->dev, fb_data->working_buffer_size,
++ &fb_data->working_buffer_phys,
++ GFP_DMA | GFP_KERNEL);
++ if (fb_data->working_buffer_virt == NULL) {
++ dev_err(&pdev->dev, "Can't allocate mem for working buf!\n");
++ ret = -ENOMEM;
++ goto out_copybuffer;
++ }
++
++ /* Initialize EPDC pins */
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "can't get/select pinctrl\n");
++ ret = PTR_ERR(pinctrl);
++ goto out_copybuffer;
++ }
++
++ fb_data->in_init = false;
++
++ fb_data->hw_ready = false;
++ fb_data->hw_initializing = false;
++
++ /*
++ * Set default waveform mode values.
++ * Should be overwritten via ioctl.
++ */
++ fb_data->wv_modes.mode_init = 0;
++ fb_data->wv_modes.mode_du = 1;
++ fb_data->wv_modes.mode_gc4 = 3;
++ fb_data->wv_modes.mode_gc8 = 2;
++ fb_data->wv_modes.mode_gc16 = 2;
++ fb_data->wv_modes.mode_gc32 = 2;
++ fb_data->wv_modes_update = true;
++
++ /* Initialize marker list */
++ INIT_LIST_HEAD(&fb_data->full_marker_list);
++
++ /* Initialize all LUTs to inactive */
++ fb_data->lut_update_order =
++ kzalloc(fb_data->num_luts * sizeof(u32 *), GFP_KERNEL);
++ for (i = 0; i < fb_data->num_luts; i++)
++ fb_data->lut_update_order[i] = 0;
++
++ INIT_DELAYED_WORK(&fb_data->epdc_done_work, epdc_done_work_func);
++ fb_data->epdc_submit_workqueue = alloc_workqueue("EPDC Submit",
++ WQ_MEM_RECLAIM | WQ_HIGHPRI |
++ WQ_CPU_INTENSIVE | WQ_UNBOUND, 1);
++ INIT_WORK(&fb_data->epdc_submit_work, epdc_submit_work_func);
++ fb_data->epdc_intr_workqueue = alloc_workqueue("EPDC Interrupt",
++ WQ_MEM_RECLAIM | WQ_HIGHPRI |
++ WQ_CPU_INTENSIVE | WQ_UNBOUND, 1);
++ INIT_WORK(&fb_data->epdc_intr_work, epdc_intr_work_func);
++
++ /* Retrieve EPDC IRQ num */
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "cannot get IRQ resource\n");
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++ fb_data->epdc_irq = irq;
++
++ /* Register IRQ handler */
++ ret = devm_request_irq(&pdev->dev, fb_data->epdc_irq,
++ mxc_epdc_irq_handler, 0, "epdc", fb_data);
++ if (ret) {
++ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
++ fb_data->epdc_irq, ret);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++
++ info->fbdefio = &mxc_epdc_fb_defio;
++#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
++ fb_deferred_io_init(info);
++#endif
++
++ /* get pmic regulators */
++ fb_data->display_regulator = devm_regulator_get(&pdev->dev, "DISPLAY");
++ if (IS_ERR(fb_data->display_regulator)) {
++ dev_err(&pdev->dev, "Unable to get display PMIC regulator."
++ "err = 0x%x\n", (int)fb_data->display_regulator);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++ fb_data->vcom_regulator = devm_regulator_get(&pdev->dev, "VCOM");
++ if (IS_ERR(fb_data->vcom_regulator)) {
++ dev_err(&pdev->dev, "Unable to get VCOM regulator."
++ "err = 0x%x\n", (int)fb_data->vcom_regulator);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++ fb_data->v3p3_regulator = devm_regulator_get(&pdev->dev, "V3P3");
++ if (IS_ERR(fb_data->v3p3_regulator)) {
++ dev_err(&pdev->dev, "Unable to get V3P3 regulator."
++ "err = 0x%x\n", (int)fb_data->vcom_regulator);
++ ret = -ENODEV;
++ goto out_dma_work_buf;
++ }
++
++ if (device_create_file(info->dev, &fb_attrs[0]))
++ dev_err(&pdev->dev, "Unable to create file from fb_attrs\n");
++
++ fb_data->cur_update = NULL;
++
++ mutex_init(&fb_data->queue_mutex);
++ mutex_init(&fb_data->pxp_mutex);
++ mutex_init(&fb_data->power_mutex);
++
++ /*
++ * Fill out PxP config data structure based on FB info and
++ * processing tasks required
++ */
++ pxp_conf = &fb_data->pxp_conf;
++ proc_data = &pxp_conf->proc_data;
++
++ /* Initialize non-channel-specific PxP parameters */
++ proc_data->drect.left = proc_data->srect.left = 0;
++ proc_data->drect.top = proc_data->srect.top = 0;
++ proc_data->drect.width = proc_data->srect.width = fb_data->info.var.xres;
++ proc_data->drect.height = proc_data->srect.height = fb_data->info.var.yres;
++ proc_data->scaling = 0;
++ proc_data->hflip = 0;
++ proc_data->vflip = 0;
++ proc_data->rotate = 0;
++ proc_data->bgcolor = 0;
++ proc_data->overlay_state = 0;
++ proc_data->lut_transform = PXP_LUT_NONE;
++ proc_data->lut_map = NULL;
++
++ /*
++ * We initially configure PxP for RGB->YUV conversion,
++ * and only write out Y component of the result.
++ */
++
++ /*
++ * Initialize S0 channel parameters
++ * Parameters should match FB format/width/height
++ */
++ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565;
++ pxp_conf->s0_param.width = fb_data->info.var.xres_virtual;
++ pxp_conf->s0_param.height = fb_data->info.var.yres;
++ pxp_conf->s0_param.color_key = -1;
++ pxp_conf->s0_param.color_key_enable = false;
++
++ /*
++ * Initialize OL0 channel parameters
++ * No overlay will be used for PxP operation
++ */
++ for (i = 0; i < 8; i++) {
++ pxp_conf->ol_param[i].combine_enable = false;
++ pxp_conf->ol_param[i].width = 0;
++ pxp_conf->ol_param[i].height = 0;
++ pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565;
++ pxp_conf->ol_param[i].color_key_enable = false;
++ pxp_conf->ol_param[i].color_key = -1;
++ pxp_conf->ol_param[i].global_alpha_enable = false;
++ pxp_conf->ol_param[i].global_alpha = 0;
++ pxp_conf->ol_param[i].local_alpha_enable = false;
++ }
++
++ /*
++ * Initialize Output channel parameters
++ * Output is Y-only greyscale
++ * Output width/height will vary based on update region size
++ */
++ pxp_conf->out_param.width = fb_data->info.var.xres;
++ pxp_conf->out_param.height = fb_data->info.var.yres;
++ pxp_conf->out_param.stride = pxp_conf->out_param.width;
++ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GREY;
++
++ /* Initialize color map for conversion of 8-bit gray pixels */
++ fb_data->pxp_conf.proc_data.lut_map = kmalloc(256, GFP_KERNEL);
++ if (fb_data->pxp_conf.proc_data.lut_map == NULL) {
++ dev_err(&pdev->dev, "Can't allocate mem for lut map!\n");
++ ret = -ENOMEM;
++ goto out_dma_work_buf;
++ }
++ for (i = 0; i < 256; i++)
++ fb_data->pxp_conf.proc_data.lut_map[i] = i;
++
++ fb_data->pxp_conf.proc_data.lut_map_updated = true;
++
++ /*
++ * Ensure this is set to NULL here...we will initialize pxp_chan
++ * later in our thread.
++ */
++ fb_data->pxp_chan = NULL;
++
++ /* Initialize Scatter-gather list containing 2 buffer addresses. */
++ sg = fb_data->sg;
++ sg_init_table(sg, 2);
++
++ /*
++ * For use in PxP transfers:
++ * sg[0] holds the FB buffer pointer
++ * sg[1] holds the Output buffer pointer (configured before TX request)
++ */
++ sg_dma_address(&sg[0]) = info->fix.smem_start;
++ sg_set_page(&sg[0], virt_to_page(info->screen_base),
++ info->fix.smem_len, offset_in_page(info->screen_base));
++
++ fb_data->order_cnt = 0;
++ fb_data->waiting_for_wb = false;
++ fb_data->waiting_for_lut = false;
++ fb_data->waiting_for_lut15 = false;
++ fb_data->waiting_for_idle = false;
++ fb_data->blank = FB_BLANK_UNBLANK;
++ fb_data->power_state = POWER_STATE_OFF;
++ fb_data->powering_down = false;
++ fb_data->wait_for_powerdown = false;
++ fb_data->updates_active = false;
++ fb_data->pwrdown_delay = 0;
++
++ /* Register FB */
++ ret = register_framebuffer(info);
++ if (ret) {
++ dev_err(&pdev->dev,
++ "register_framebuffer failed with error %d\n", ret);
++ goto out_lutmap;
++ }
++
++ g_fb_data = fb_data;
++
++ pm_runtime_enable(fb_data->dev);
++
++#ifdef DEFAULT_PANEL_HW_INIT
++ ret = mxc_epdc_fb_init_hw((struct fb_info *)fb_data);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to initialize HW!\n");
++ }
++#endif
++
++ goto out;
++
++out_lutmap:
++ kfree(fb_data->pxp_conf.proc_data.lut_map);
++out_dma_work_buf:
++ dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
++ fb_data->working_buffer_virt, fb_data->working_buffer_phys);
++out_copybuffer:
++ dma_free_writecombine(&pdev->dev, fb_data->max_pix_size*2,
++ fb_data->virt_addr_copybuf,
++ fb_data->phys_addr_copybuf);
++out_upd_buffers:
++ for (i = 0; i < fb_data->max_num_buffers; i++)
++ if (fb_data->virt_addr_updbuf[i] != NULL)
++ kfree(fb_data->virt_addr_updbuf[i]);
++ if (fb_data->virt_addr_updbuf != NULL)
++ kfree(fb_data->virt_addr_updbuf);
++ if (fb_data->phys_addr_updbuf != NULL)
++ kfree(fb_data->phys_addr_updbuf);
++out_upd_lists:
++ list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list,
++ list) {
++ list_del(&plist->list);
++ kfree(plist);
++ }
++out_dma_fb:
++ dma_free_writecombine(&pdev->dev, fb_data->map_size, info->screen_base,
++ fb_data->phys_start);
++
++out_cmap:
++ fb_dealloc_cmap(&info->cmap);
++out_fbdata:
++ kfree(fb_data);
++out:
++ return ret;
++}
++
++static int mxc_epdc_fb_remove(struct platform_device *pdev)
++{
++ struct update_data_list *plist, *temp_list;
++ struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
++ int i;
++
++ mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info);
++
++ flush_workqueue(fb_data->epdc_submit_workqueue);
++ destroy_workqueue(fb_data->epdc_submit_workqueue);
++
++ unregister_framebuffer(&fb_data->info);
++
++ for (i = 0; i < fb_data->max_num_buffers; i++)
++ if (fb_data->virt_addr_updbuf[i] != NULL)
++ kfree(fb_data->virt_addr_updbuf[i]);
++ if (fb_data->virt_addr_updbuf != NULL)
++ kfree(fb_data->virt_addr_updbuf);
++ if (fb_data->phys_addr_updbuf != NULL)
++ kfree(fb_data->phys_addr_updbuf);
++
++ dma_free_writecombine(&pdev->dev, fb_data->working_buffer_size,
++ fb_data->working_buffer_virt,
++ fb_data->working_buffer_phys);
++ if (fb_data->waveform_buffer_virt != NULL)
++ dma_free_writecombine(&pdev->dev, fb_data->waveform_buffer_size,
++ fb_data->waveform_buffer_virt,
++ fb_data->waveform_buffer_phys);
++ if (fb_data->virt_addr_copybuf != NULL)
++ dma_free_writecombine(&pdev->dev, fb_data->max_pix_size*2,
++ fb_data->virt_addr_copybuf,
++ fb_data->phys_addr_copybuf);
++ list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list,
++ list) {
++ list_del(&plist->list);
++ kfree(plist);
++ }
++#ifdef CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE
++ fb_deferred_io_cleanup(&fb_data->info);
++#endif
++
++ dma_free_writecombine(&pdev->dev, fb_data->map_size, fb_data->info.screen_base,
++ fb_data->phys_start);
++
++ /* Release PxP-related resources */
++ if (fb_data->pxp_chan != NULL)
++ dma_release_channel(&fb_data->pxp_chan->dma_chan);
++
++ fb_dealloc_cmap(&fb_data->info.cmap);
++
++ framebuffer_release(&fb_data->info);
++ platform_set_drvdata(pdev, NULL);
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_SLEEP
++static int mxc_epdc_fb_suspend(struct device *dev)
++{
++ struct mxc_epdc_fb_data *data = dev_get_drvdata(dev);
++ int ret;
++
++ data->pwrdown_delay = FB_POWERDOWN_DISABLE;
++ ret = mxc_epdc_fb_blank(FB_BLANK_POWERDOWN, &data->info);
++ if (ret)
++ goto out;
++
++out:
++ return ret;
++}
++
++static int mxc_epdc_fb_resume(struct device *dev)
++{
++ struct mxc_epdc_fb_data *data = dev_get_drvdata(dev);
++
++ mxc_epdc_fb_blank(FB_BLANK_UNBLANK, &data->info);
++ epdc_init_settings(data);
++ data->updates_active = false;
++
++ return 0;
++}
++#else
++#define mxc_epdc_fb_suspend NULL
++#define mxc_epdc_fb_resume NULL
++#endif
++
++#ifdef CONFIG_PM_RUNTIME
++static int mxc_epdc_fb_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "epdc busfreq high release.\n");
++
++ return 0;
++}
++
++static int mxc_epdc_fb_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "epdc busfreq high request.\n");
++
++ return 0;
++}
++#else
++#define mxc_epdc_fb_runtime_suspend NULL
++#define mxc_epdc_fb_runtime_resume NULL
++#endif
++
++static const struct dev_pm_ops mxc_epdc_fb_pm_ops = {
++ SET_RUNTIME_PM_OPS(mxc_epdc_fb_runtime_suspend,
++ mxc_epdc_fb_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(mxc_epdc_fb_suspend, mxc_epdc_fb_resume)
++};
++
++static void mxc_epdc_fb_shutdown(struct platform_device *pdev)
++{
++ struct mxc_epdc_fb_data *fb_data = platform_get_drvdata(pdev);
++
++ /* Disable power to the EPD panel */
++ if (regulator_is_enabled(fb_data->vcom_regulator))
++ regulator_disable(fb_data->vcom_regulator);
++ if (regulator_is_enabled(fb_data->display_regulator))
++ regulator_disable(fb_data->display_regulator);
++
++ /* Disable clocks to EPDC */
++ clk_prepare_enable(fb_data->epdc_clk_axi);
++ clk_prepare_enable(fb_data->epdc_clk_pix);
++ __raw_writel(EPDC_CTRL_CLKGATE, EPDC_CTRL_SET);
++ clk_disable_unprepare(fb_data->epdc_clk_pix);
++ clk_disable_unprepare(fb_data->epdc_clk_axi);
++
++ /* turn off the V3p3 */
++ if (regulator_is_enabled(fb_data->v3p3_regulator))
++ regulator_disable(fb_data->v3p3_regulator);
++}
++
++static struct platform_driver mxc_epdc_fb_driver = {
++ .probe = mxc_epdc_fb_probe,
++ .remove = mxc_epdc_fb_remove,
++ .shutdown = mxc_epdc_fb_shutdown,
++ .driver = {
++ .name = "imx_epdc_fb",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(imx_epdc_dt_ids),
++ .pm = &mxc_epdc_fb_pm_ops,
++ },
++};
++
++/* Callback function triggered after PxP receives an EOF interrupt */
++static void pxp_dma_done(void *arg)
++{
++ struct pxp_tx_desc *tx_desc = to_tx_desc(arg);
++ struct dma_chan *chan = tx_desc->txd.chan;
++ struct pxp_channel *pxp_chan = to_pxp_channel(chan);
++ struct mxc_epdc_fb_data *fb_data = pxp_chan->client;
++
++ /* This call will signal wait_for_completion_timeout() in send_buffer_to_pxp */
++ complete(&fb_data->pxp_tx_cmpl);
++}
++
++static bool chan_filter(struct dma_chan *chan, void *arg)
++{
++ if (imx_dma_is_pxp(chan))
++ return true;
++ else
++ return false;
++}
++
++/* Function to request PXP DMA channel */
++static int pxp_chan_init(struct mxc_epdc_fb_data *fb_data)
++{
++ dma_cap_mask_t mask;
++ struct dma_chan *chan;
++
++ /*
++ * Request a free channel
++ */
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_PRIVATE, mask);
++ chan = dma_request_channel(mask, chan_filter, NULL);
++ if (!chan) {
++ dev_err(fb_data->dev, "Unsuccessfully received channel!!!!\n");
++ return -EBUSY;
++ }
++
++ fb_data->pxp_chan = to_pxp_channel(chan);
++ fb_data->pxp_chan->client = fb_data;
++
++ init_completion(&fb_data->pxp_tx_cmpl);
++
++ return 0;
++}
++
++/*
++ * Function to call PxP DMA driver and send our latest FB update region
++ * through the PxP and out to an intermediate buffer.
++ * Note: This is a blocking call, so upon return the PxP tx should be complete.
++ */
++static int pxp_process_update(struct mxc_epdc_fb_data *fb_data,
++ u32 src_width, u32 src_height,
++ struct mxcfb_rect *update_region)
++{
++ dma_cookie_t cookie;
++ struct scatterlist *sg = fb_data->sg;
++ struct dma_chan *dma_chan;
++ struct pxp_tx_desc *desc;
++ struct dma_async_tx_descriptor *txd;
++ struct pxp_config_data *pxp_conf = &fb_data->pxp_conf;
++ struct pxp_proc_data *proc_data = &fb_data->pxp_conf.proc_data;
++ int i, ret;
++ int length;
++
++ dev_dbg(fb_data->dev, "Starting PxP Send Buffer\n");
++
++ /* First, check to see that we have acquired a PxP Channel object */
++ if (fb_data->pxp_chan == NULL) {
++ /*
++ * PxP Channel has not yet been created and initialized,
++ * so let's go ahead and try
++ */
++ ret = pxp_chan_init(fb_data);
++ if (ret) {
++ /*
++ * PxP channel init failed, and we can't use the
++ * PxP until the PxP DMA driver has loaded, so we abort
++ */
++ dev_err(fb_data->dev, "PxP chan init failed\n");
++ return -ENODEV;
++ }
++ }
++
++ /*
++ * Init completion, so that we
++ * can be properly informed of the completion
++ * of the PxP task when it is done.
++ */
++ init_completion(&fb_data->pxp_tx_cmpl);
++
++ dma_chan = &fb_data->pxp_chan->dma_chan;
++
++ txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2,
++ DMA_TO_DEVICE,
++ DMA_PREP_INTERRUPT,
++ NULL);
++ if (!txd) {
++ dev_err(fb_data->info.device,
++ "Error preparing a DMA transaction descriptor.\n");
++ return -EIO;
++ }
++
++ txd->callback_param = txd;
++ txd->callback = pxp_dma_done;
++
++ /*
++ * Configure PxP for processing of new update region
++ * The rest of our config params were set up in
++ * probe() and should not need to be changed.
++ */
++ pxp_conf->s0_param.width = src_width;
++ pxp_conf->s0_param.height = src_height;
++ proc_data->srect.top = update_region->top;
++ proc_data->srect.left = update_region->left;
++ proc_data->srect.width = update_region->width;
++ proc_data->srect.height = update_region->height;
++
++ /*
++ * Because only YUV/YCbCr image can be scaled, configure
++ * drect equivalent to srect, as such do not perform scaling.
++ */
++ proc_data->drect.top = 0;
++ proc_data->drect.left = 0;
++
++ /* PXP expects rotation in terms of degrees */
++ proc_data->rotate = fb_data->epdc_fb_var.rotate * 90;
++ if (proc_data->rotate > 270)
++ proc_data->rotate = 0;
++
++ /* Just as V4L2 PXP, we should pass the rotated values to PXP */
++ if ((proc_data->rotate == 90) || (proc_data->rotate == 270)) {
++ proc_data->drect.width = proc_data->srect.height;
++ proc_data->drect.height = proc_data->srect.width;
++ pxp_conf->out_param.width = update_region->height;
++ pxp_conf->out_param.height = update_region->width;
++ pxp_conf->out_param.stride = update_region->height;
++ } else {
++ proc_data->drect.width = proc_data->srect.width;
++ proc_data->drect.height = proc_data->srect.height;
++ pxp_conf->out_param.width = update_region->width;
++ pxp_conf->out_param.height = update_region->height;
++ pxp_conf->out_param.stride = update_region->width;
++ }
++
++ /* For EPDC v2.0, we need output to be 64-bit
++ * aligned since EPDC stride does not work. */
++ if (fb_data->rev <= 20)
++ pxp_conf->out_param.stride = ALIGN(pxp_conf->out_param.stride, 8);
++
++
++ desc = to_tx_desc(txd);
++ length = desc->len;
++ for (i = 0; i < length; i++) {
++ if (i == 0) {/* S0 */
++ memcpy(&desc->proc_data, proc_data, sizeof(struct pxp_proc_data));
++ pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]);
++ memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param,
++ sizeof(struct pxp_layer_param));
++ } else if (i == 1) {
++ pxp_conf->out_param.paddr = sg_dma_address(&sg[1]);
++ memcpy(&desc->layer_param.out_param, &pxp_conf->out_param,
++ sizeof(struct pxp_layer_param));
++ }
++ /* TODO: OverLay */
++
++ desc = desc->next;
++ }
++
++ /* Submitting our TX starts the PxP processing task */
++ cookie = txd->tx_submit(txd);
++ if (cookie < 0) {
++ dev_err(fb_data->info.device, "Error sending FB through PxP\n");
++ return -EIO;
++ }
++
++ fb_data->txd = txd;
++
++ /* trigger ePxP */
++ dma_async_issue_pending(dma_chan);
++
++ return 0;
++}
++
++static int pxp_complete_update(struct mxc_epdc_fb_data *fb_data, u32 *hist_stat)
++{
++ int ret;
++ /*
++ * Wait for completion event, which will be set
++ * through our TX callback function.
++ */
++ ret = wait_for_completion_timeout(&fb_data->pxp_tx_cmpl, HZ / 10);
++ if (ret <= 0) {
++ dev_info(fb_data->info.device,
++ "PxP operation failed due to %s\n",
++ ret < 0 ? "user interrupt" : "timeout");
++ dma_release_channel(&fb_data->pxp_chan->dma_chan);
++ fb_data->pxp_chan = NULL;
++ return ret ? : -ETIMEDOUT;
++ }
++
++ if ((fb_data->pxp_conf.proc_data.lut_transform & EPDC_FLAG_USE_CMAP) &&
++ fb_data->pxp_conf.proc_data.lut_map_updated)
++ fb_data->pxp_conf.proc_data.lut_map_updated = false;
++
++ *hist_stat = to_tx_desc(fb_data->txd)->hist_status;
++ dma_release_channel(&fb_data->pxp_chan->dma_chan);
++ fb_data->pxp_chan = NULL;
++
++ dev_dbg(fb_data->dev, "TX completed\n");
++
++ return 0;
++}
++
++/*
++ * Different dithering algorithm can be used. We chose
++ * to implement Bill Atkinson's algorithm as an example
++ * Thanks Bill Atkinson for his dithering algorithm.
++ */
++
++/*
++ * Dithering algorithm implementation - Y8->Y1 version 1.0 for i.MX
++ */
++static void do_dithering_processing_Y1_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist)
++{
++
++ /* create a temp error distribution array */
++ int bwPix;
++ int y;
++ int col;
++ int *err_dist_l0, *err_dist_l1, *err_dist_l2, distrib_error;
++ int width_3 = update_region->width + 3;
++ char *y8buf;
++ int x_offset = 0;
++
++ /* prime a few elements the error distribution array */
++ for (y = 0; y < update_region->height; y++) {
++ /* Dithering the Y8 in sbuf to BW suitable for A2 waveform */
++ err_dist_l0 = err_dist + (width_3) * (y % 3);
++ err_dist_l1 = err_dist + (width_3) * ((y + 1) % 3);
++ err_dist_l2 = err_dist + (width_3) * ((y + 2) % 3);
++
++ y8buf = update_region_ptr + x_offset;
++
++ /* scan the line and convert the Y8 to BW */
++ for (col = 1; col <= update_region->width; col++) {
++ bwPix = *(err_dist_l0 + col) + *y8buf;
++
++ if (bwPix >= 128) {
++ *y8buf++ = 0xff;
++ distrib_error = (bwPix - 255) >> 3;
++ } else {
++ *y8buf++ = 0;
++ distrib_error = bwPix >> 3;
++ }
++
++ /* modify the error distribution buffer */
++ *(err_dist_l0 + col + 2) += distrib_error;
++ *(err_dist_l1 + col + 1) += distrib_error;
++ *(err_dist_l0 + col + 1) += distrib_error;
++ *(err_dist_l1 + col - 1) += distrib_error;
++ *(err_dist_l1 + col) += distrib_error;
++ *(err_dist_l2 + col) = distrib_error;
++ }
++ x_offset += update_region_stride;
++ }
++
++ flush_cache_all();
++ outer_flush_all();
++}
++
++/*
++ * Dithering algorithm implementation - Y8->Y4 version 1.0 for i.MX
++ */
++
++static void do_dithering_processing_Y4_v1_0(
++ unsigned char *update_region_ptr,
++ struct mxcfb_rect *update_region,
++ unsigned long update_region_stride,
++ int *err_dist)
++{
++
++ /* create a temp error distribution array */
++ int gcPix;
++ int y;
++ int col;
++ int *err_dist_l0, *err_dist_l1, *err_dist_l2, distrib_error;
++ int width_3 = update_region->width + 3;
++ char *y8buf;
++ int x_offset = 0;
++
++ /* prime a few elements the error distribution array */
++ for (y = 0; y < update_region->height; y++) {
++ /* Dithering the Y8 in sbuf to Y4 */
++ err_dist_l0 = err_dist + (width_3) * (y % 3);
++ err_dist_l1 = err_dist + (width_3) * ((y + 1) % 3);
++ err_dist_l2 = err_dist + (width_3) * ((y + 2) % 3);
++
++ y8buf = update_region_ptr + x_offset;
++
++ /* scan the line and convert the Y8 to Y4 */
++ for (col = 1; col <= update_region->width; col++) {
++ gcPix = *(err_dist_l0 + col) + *y8buf;
++
++ if (gcPix > 255)
++ gcPix = 255;
++ else if (gcPix < 0)
++ gcPix = 0;
++
++ distrib_error = (*y8buf - (gcPix & 0xf0)) >> 3;
++
++ *y8buf++ = gcPix & 0xf0;
++
++ /* modify the error distribution buffer */
++ *(err_dist_l0 + col + 2) += distrib_error;
++ *(err_dist_l1 + col + 1) += distrib_error;
++ *(err_dist_l0 + col + 1) += distrib_error;
++ *(err_dist_l1 + col - 1) += distrib_error;
++ *(err_dist_l1 + col) += distrib_error;
++ *(err_dist_l2 + col) = distrib_error;
++ }
++ x_offset += update_region_stride;
++ }
++
++ flush_cache_all();
++ outer_flush_all();
++}
++
++module_platform_driver(mxc_epdc_fb_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC EPDC framebuffer driver");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("fb");
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxcfb_adv739x.c linux-3.14.72/drivers/video/mxc/mxcfb_adv739x.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxcfb_adv739x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxcfb_adv739x.c 2016-06-19 22:11:55.349137119 +0200
+@@ -0,0 +1,397 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++#include <linux/delay.h>
++#include <linux/ipu.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/mxcfb.h>
++
++#include "mxc_dispdrv.h"
++#include "crtc.h"
++
++#define DISPDRV_ADV739X "adv739x"
++
++#define ADV739X_MODE_NTSC 0
++#define ADV739X_MODE_PAL 1
++
++
++struct adv739x_data {
++ struct platform_device *pdev;
++ struct i2c_client *client;
++ struct mxc_dispdrv_handle *disp_adv739x;
++ struct fb_info *fbi;
++
++ int ipu_id;
++ int disp_id;
++ int default_ifmt;
++
++ int cur_mode;
++ int enabled;
++ struct notifier_block nb;
++};
++
++/*
++ * left_margin: used for field0 vStart width in lines
++ *
++ * right_margin: used for field0 vEnd width in lines
++ *
++ * up_margin: used for field1 vStart width in lines
++ *
++ * down_margin: used for field1 vEnd width in lines
++ *
++ * hsync_len: EAV Code + Blanking Video + SAV Code (in pixel clock count)
++ * For BT656 NTSC, it is 4 + 67*4 + 4 = 276.
++ * For BT1120 NTSC, it is 4 + 67*2 + 4 = 142.
++ * For BT656 PAL, it is 4 + 70*4 + 4 = 288.
++ * For BT1120 PAL, it is 4 + 70*2 + 4 = 148.
++ *
++ * vsync_len: not used, set to 1
++ */
++static struct fb_videomode adv739x_modedb[] = {
++ {
++ /* NTSC Interlaced output */
++ "BT656-NTSC", 60, 720, 480, 37037,
++ 19, 3,
++ 20, 3,
++ 276, 1,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED,
++ FB_MODE_IS_DETAILED,},
++ {
++ /* PAL Interlaced output */
++ "BT656-PAL", 50, 720, 576, 37037,
++ 22, 2,
++ 23, 2,
++ 288, 1,
++ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
++ FB_VMODE_INTERLACED,
++ FB_MODE_IS_DETAILED,},
++};
++static int adv739x_modedb_sz = ARRAY_SIZE(adv739x_modedb);
++
++static int adv739x_write(struct i2c_client *client, u8 reg, u8 data)
++{
++ int ret = 0;
++ ret = i2c_smbus_write_byte_data(client, reg, data);
++
++ return ret;
++}
++
++/*
++static int adv739x_read(struct i2c_client *client, u8 reg)
++{
++ int data = 0;
++ data = i2c_smbus_read_byte_data(client, reg);
++
++ return data;
++}
++*/
++
++static void adv739x_setmode(struct adv739x_data *adv739x, int mode)
++{
++ struct i2c_client *client = adv739x->client;
++
++ if(adv739x->enabled == 0)
++ return;
++
++ dev_dbg(&adv739x->client->dev, "adv739x_setmode: mode = %d.\n", mode);
++ switch (mode) {
++ case ADV739X_MODE_NTSC:
++ // Reg 0x17: reset
++ adv739x_write(client, 0x17, 0x02);
++
++ mdelay(20);
++
++ // Reg 0x00: DAC1~3 power on
++ adv739x_write(client, 0x00, 0x1C);
++
++ // Reg 0x01: SD input
++ adv739x_write(client, 0x01, 0x00);
++
++ //NTSC
++ // Reg 0x80: SD, NTSC
++ adv739x_write(client, 0x80, 0x10);
++
++ // Reg 0x82: SD, CVBS
++ adv739x_write(client, 0x82, 0xCB);
++ break;
++
++ case ADV739X_MODE_PAL:
++ // Reg 0x17: reset
++ adv739x_write(client, 0x17, 0x02);
++
++ mdelay(20);
++
++ // Reg 0x00: DAC1~3 power on
++ adv739x_write(client, 0x00, 0x1C);
++
++ // Reg 0x01: SD input
++ adv739x_write(client, 0x01, 0x00);
++
++ // Reg 0x80: SD, PAL
++ adv739x_write(client, 0x80, 0x11);
++
++ // Reg 0x82: SD, CVBS
++ adv739x_write(client, 0x82, 0xC3);
++ adv739x_write(client, 0x8C, 0xCB);
++ adv739x_write(client, 0x8D, 0x8A);
++ adv739x_write(client, 0x8E, 0x09);
++ adv739x_write(client, 0x8F, 0x2A);
++ break;
++
++ default:
++ dev_err(&adv739x->client->dev, "unsupported mode.\n");
++ break;
++ }
++}
++
++static void adv739x_poweroff(struct adv739x_data *adv739x)
++{
++ if (adv739x->enabled != 0) {
++ dev_dbg(&adv739x->client->dev, "adv739x_poweroff.\n");
++
++ /* power off the adv739x */
++ adv739x_write(adv739x->client, 0x00, 0x1F);
++
++ adv739x->enabled = 0;
++ }
++}
++
++static void adv739x_poweron(struct adv739x_data *adv739x)
++{
++ if (adv739x->enabled == 0) {
++ dev_dbg(&adv739x->client->dev, "adv739x_poweron.\n");
++
++ adv739x->enabled = 1;
++ adv739x_setmode(adv739x, adv739x->cur_mode);
++ }
++}
++
++int adv739x_fb_event(struct notifier_block *nb, unsigned long val, void *v)
++{
++ struct fb_event *event = v;
++ struct fb_info *fbi = event->info;
++ struct adv739x_data *adv739x = container_of(nb, struct adv739x_data, nb);
++
++ if (strcmp(event->info->fix.id, adv739x->fbi->fix.id))
++ return 0;
++
++ dev_dbg(&adv739x->client->dev, "%s\n", __func__);
++
++ fbi->mode = (struct fb_videomode *)fb_match_mode(&fbi->var,
++ &fbi->modelist);
++ if (!fbi->mode) {
++ dev_warn(&adv739x->pdev->dev,
++ "adv739x: can not find mode for xres=%d, yres=%d\n",
++ fbi->var.xres, fbi->var.yres);
++ return 0;
++ }
++
++ switch (val) {
++ case FB_EVENT_MODE_CHANGE:
++ if(strcmp(fbi->mode->name, "BT656-NTSC") == 0)
++ adv739x->cur_mode = ADV739X_MODE_NTSC;
++ else if(strcmp(fbi->mode->name, "BT656-PAL") == 0)
++ adv739x->cur_mode = ADV739X_MODE_PAL;
++ adv739x_setmode(adv739x, adv739x->cur_mode);
++ break;
++ case FB_EVENT_BLANK:
++ if (*((int *)event->data) == FB_BLANK_UNBLANK)
++ adv739x_poweron(adv739x);
++ else
++ adv739x_poweroff(adv739x);
++ break;
++ }
++ return 0;
++}
++
++static int adv739x_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret = 0, i;
++ struct adv739x_data *adv739x = mxc_dispdrv_getdata(disp);
++ struct fb_videomode *modedb = adv739x_modedb;
++ int modedb_sz = adv739x_modedb_sz;
++ static bool inited = false;
++
++ dev_dbg(&adv739x->client->dev, "%s\n", __func__);
++ if (inited)
++ return -EBUSY;
++
++ inited = true;
++
++ ret = ipu_di_to_crtc(&adv739x->pdev->dev, adv739x->ipu_id,
++ adv739x->disp_id, &setting->crtc);
++ if (ret < 0)
++ return ret;
++/*
++ setting->dev_id = adv739x->ipu_id;
++ setting->disp_id = adv739x->disp_id;
++*/
++
++ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
++ modedb, modedb_sz, NULL, setting->default_bpp);
++ if (!ret) {
++ fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
++ setting->if_fmt = adv739x->default_ifmt;
++ }
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < modedb_sz; i++) {
++ fb_add_videomode(&modedb[i],
++ &setting->fbi->modelist);
++ }
++
++ adv739x->fbi = setting->fbi;
++ adv739x->enabled = 0;
++ adv739x->cur_mode = ADV739X_MODE_NTSC; //default mode
++
++ adv739x->pdev = platform_device_register_simple("mxc_adv739x", 0, NULL, 0);
++ if (IS_ERR(adv739x->pdev)) {
++ dev_err(&adv739x->client->dev,
++ "Unable to register adv739x as a platform device\n");
++ ret = PTR_ERR(adv739x->pdev);
++ goto register_pltdev_failed;
++ }
++
++ adv739x->nb.notifier_call = adv739x_fb_event;
++ ret = fb_register_client(&adv739x->nb);
++ if (ret < 0)
++ goto reg_fbclient_failed;
++
++ return ret;
++
++reg_fbclient_failed:
++ platform_device_unregister(adv739x->pdev);
++register_pltdev_failed:
++ return ret;
++}
++
++static void adv739x_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct adv739x_data *adv739x = mxc_dispdrv_getdata(disp);
++
++ dev_dbg(&adv739x->client->dev, "%s\n", __func__);
++ if (adv739x->client->irq)
++ free_irq(adv739x->client->irq, adv739x);
++
++ fb_unregister_client(&adv739x->nb);
++
++ adv739x_poweroff(adv739x);
++
++ platform_device_unregister(adv739x->pdev);
++}
++
++static struct mxc_dispdrv_driver adv739x_drv = {
++ .name = DISPDRV_ADV739X,
++ .init = adv739x_disp_init,
++ .deinit = adv739x_disp_deinit,
++};
++
++static int adv739x_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ struct adv739x_data *adv739x;
++ struct device_node *np = client->dev.of_node;
++ int ret = 0;
++
++ if (!i2c_check_functionality(client->adapter,
++ I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA))
++ return -ENODEV;
++
++ adv739x = kzalloc(sizeof(struct adv739x_data), GFP_KERNEL);
++ if (!adv739x) {
++ ret = -ENOMEM;
++ goto alloc_failed;
++ }
++
++ adv739x->client = client;
++
++ ret = of_property_read_u32(np, "ipu_id", &adv739x->ipu_id);
++ if (ret) {
++ dev_err(&client->dev, "get of property ipu_id fail\n");
++ goto prop_failed;
++ }
++ ret = of_property_read_u32(np, "disp_id", &adv739x->disp_id);
++ if (ret) {
++ dev_err(&client->dev, "get of property disp_id fail\n");
++ goto prop_failed;
++ }
++ adv739x->default_ifmt = IPU_PIX_FMT_BT656;
++
++ adv739x->disp_adv739x = mxc_dispdrv_register(&adv739x_drv);
++ mxc_dispdrv_setdata(adv739x->disp_adv739x, adv739x);
++
++ i2c_set_clientdata(client, adv739x);
++
++ return 0;
++
++prop_failed:
++ kfree(adv739x);
++alloc_failed:
++ return ret;
++
++}
++
++static int adv739x_remove(struct i2c_client *client)
++{
++ struct adv739x_data *adv739x = i2c_get_clientdata(client);
++
++ mxc_dispdrv_puthandle(adv739x->disp_adv739x);
++ mxc_dispdrv_unregister(adv739x->disp_adv739x);
++ kfree(adv739x);
++ return 0;
++}
++
++static const struct i2c_device_id adv739x_id[] = {
++ { "mxc_adv739x", 0 },
++};
++
++MODULE_DEVICE_TABLE(i2c, adv739x_id);
++
++static struct of_device_id adv739x_dt_ids[] = {
++ { .compatible = "adi,adv7393", },
++ { /* sentinel */ }
++};
++
++static struct i2c_driver adv739x_i2c_driver = {
++ .driver = {
++ .name = "mxc_adv739x",
++ .of_match_table = adv739x_dt_ids,
++ },
++ .probe = adv739x_probe,
++ .remove = adv739x_remove,
++ .id_table = adv739x_id,
++};
++
++static int __init adv739x_i2c_init(void)
++{
++ return i2c_add_driver(&adv739x_i2c_driver);
++}
++
++static void __exit adv739x_i2c_exit(void)
++{
++ i2c_del_driver(&adv739x_i2c_driver);
++}
++
++module_init(adv739x_i2c_init);
++module_exit(adv739x_i2c_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("ADV739x TV encoder driver");
++MODULE_LICENSE("GPL");
++
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxcfb_hx8369_wvga.c linux-3.14.72/drivers/video/mxc/mxcfb_hx8369_wvga.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxcfb_hx8369_wvga.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxcfb_hx8369_wvga.c 2016-06-19 22:11:55.353136857 +0200
+@@ -0,0 +1,449 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/types.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/platform_device.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/bitops.h>
++#include <linux/spinlock.h>
++#include <linux/mipi_dsi.h>
++#include <linux/mxcfb.h>
++#include <linux/backlight.h>
++#include <video/mipi_display.h>
++
++#include "mipi_dsi.h"
++
++#define MIPI_DSI_MAX_RET_PACK_SIZE (0x4)
++
++#define HX8369BL_MAX_BRIGHT (255)
++#define HX8369BL_DEF_BRIGHT (255)
++
++#define HX8369_MAX_DPHY_CLK (800)
++#define HX8369_ONE_DATA_LANE (0x1)
++#define HX8369_TWO_DATA_LANE (0x2)
++
++#define HX8369_CMD_SETEXTC (0xB9)
++#define HX8369_CMD_SETEXTC_LEN (0x4)
++#define HX8369_CMD_SETEXTC_PARAM_1 (0x6983ff)
++
++#define HX8369_CMD_GETHXID (0xF4)
++#define HX8369_CMD_GETHXID_LEN (0x4)
++#define HX8369_ID (0x69)
++#define HX8369_ID_MASK (0xFF)
++
++#define HX8369_CMD_SETDISP (0xB2)
++#define HX8369_CMD_SETDISP_LEN (16)
++#define HX8369_CMD_SETDISP_1_HALT (0x00)
++#define HX8369_CMD_SETDISP_2_RES_MODE (0x23)
++#define HX8369_CMD_SETDISP_3_BP (0x03)
++#define HX8369_CMD_SETDISP_4_FP (0x03)
++#define HX8369_CMD_SETDISP_5_SAP (0x70)
++#define HX8369_CMD_SETDISP_6_GENON (0x00)
++#define HX8369_CMD_SETDISP_7_GENOFF (0xff)
++#define HX8369_CMD_SETDISP_8_RTN (0x00)
++#define HX8369_CMD_SETDISP_9_TEI (0x00)
++#define HX8369_CMD_SETDISP_10_TEP_UP (0x00)
++#define HX8369_CMD_SETDISP_11_TEP_LOW (0x00)
++#define HX8369_CMD_SETDISP_12_BP_PE (0x03)
++#define HX8369_CMD_SETDISP_13_FP_PE (0x03)
++#define HX8369_CMD_SETDISP_14_RTN_PE (0x00)
++#define HX8369_CMD_SETDISP_15_GON (0x01)
++
++#define HX8369_CMD_SETCYC (0xB4)
++#define HX8369_CMD_SETCYC_LEN (6)
++#define HX8369_CMD_SETCYC_PARAM_1 (0x5f1d00)
++#define HX8369_CMD_SETCYC_PARAM_2 (0x060e)
++
++#define HX8369_CMD_SETGIP (0xD5)
++#define HX8369_CMD_SETGIP_LEN (27)
++#define HX8369_CMD_SETGIP_PARAM_1 (0x030400)
++#define HX8369_CMD_SETGIP_PARAM_2 (0x1c050100)
++#define HX8369_CMD_SETGIP_PARAM_3 (0x00030170)
++#define HX8369_CMD_SETGIP_PARAM_4 (0x51064000)
++#define HX8369_CMD_SETGIP_PARAM_5 (0x41000007)
++#define HX8369_CMD_SETGIP_PARAM_6 (0x07075006)
++#define HX8369_CMD_SETGIP_PARAM_7 (0x040f)
++
++#define HX8369_CMD_SETPOWER (0xB1)
++#define HX8369_CMD_SETPOWER_LEN (20)
++#define HX8369_CMD_SETPOWER_PARAM_1 (0x340001)
++#define HX8369_CMD_SETPOWER_PARAM_2 (0x0f0f0006)
++#define HX8369_CMD_SETPOWER_PARAM_3 (0x3f3f322a)
++#define HX8369_CMD_SETPOWER_PARAM_4 (0xe6013a07)
++#define HX8369_CMD_SETPOWER_PARAM_5 (0xe6e6e6e6)
++
++#define HX8369_CMD_SETVCOM (0xB6)
++#define HX8369_CMD_SETVCOM_LEN (3)
++#define HX8369_CMD_SETVCOM_PARAM_1 (0x5656)
++
++#define HX8369_CMD_SETPANEL (0xCC)
++#define HX8369_CMD_SETPANEL_PARAM_1 (0x02)
++
++#define HX8369_CMD_SETGAMMA (0xE0)
++#define HX8369_CMD_SETGAMMA_LEN (35)
++#define HX8369_CMD_SETGAMMA_PARAM_1 (0x221d00)
++#define HX8369_CMD_SETGAMMA_PARAM_2 (0x2e3f3d38)
++#define HX8369_CMD_SETGAMMA_PARAM_3 (0x0f0d064a)
++#define HX8369_CMD_SETGAMMA_PARAM_4 (0x16131513)
++#define HX8369_CMD_SETGAMMA_PARAM_5 (0x1d001910)
++#define HX8369_CMD_SETGAMMA_PARAM_6 (0x3f3d3822)
++#define HX8369_CMD_SETGAMMA_PARAM_7 (0x0d064a2e)
++#define HX8369_CMD_SETGAMMA_PARAM_8 (0x1315130f)
++#define HX8369_CMD_SETGAMMA_PARAM_9 (0x191016)
++
++#define HX8369_CMD_SETMIPI (0xBA)
++#define HX8369_CMD_SETMIPI_LEN (14)
++#define HX8369_CMD_SETMIPI_PARAM_1 (0xc6a000)
++#define HX8369_CMD_SETMIPI_PARAM_2 (0x10000a00)
++#define HX8369_CMD_SETMIPI_ONELANE (0x10 << 24)
++#define HX8369_CMD_SETMIPI_TWOLANE (0x11 << 24)
++#define HX8369_CMD_SETMIPI_PARAM_3 (0x00026f30)
++#define HX8369_CMD_SETMIPI_PARAM_4 (0x4018)
++
++#define HX8369_CMD_SETPIXEL_FMT (0x3A)
++#define HX8369_CMD_SETPIXEL_FMT_24BPP (0x77)
++#define HX8369_CMD_SETPIXEL_FMT_18BPP (0x66)
++#define HX8369_CMD_SETPIXEL_FMT_16BPP (0x55)
++
++#define HX8369_CMD_SETCLUMN_ADDR (0x2A)
++#define HX8369_CMD_SETCLUMN_ADDR_LEN (5)
++#define HX8369_CMD_SETCLUMN_ADDR_PARAM_1 (0xdf0000)
++#define HX8369_CMD_SETCLUMN_ADDR_PARAM_2 (0x01)
++
++#define HX8369_CMD_SETPAGE_ADDR (0x2B)
++#define HX8369_CMD_SETPAGE_ADDR_LEN (5)
++#define HX8369_CMD_SETPAGE_ADDR_PARAM_1 (0x1f0000)
++#define HX8369_CMD_SETPAGE_ADDR_PARAM_2 (0x03)
++
++#define HX8369_CMD_WRT_DISP_BRIGHT (0x51)
++#define HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 (0xFF)
++
++#define HX8369_CMD_WRT_CABC_MIN_BRIGHT (0x5E)
++#define HX8369_CMD_WRT_CABC_MIN_BRIGHT_PARAM_1 (0x20)
++
++#define HX8369_CMD_WRT_CABC_CTRL (0x55)
++#define HX8369_CMD_WRT_CABC_CTRL_PARAM_1 (0x1)
++
++#define HX8369_CMD_WRT_CTRL_DISP (0x53)
++#define HX8369_CMD_WRT_CTRL_DISP_PARAM_1 (0x24)
++
++#define CHECK_RETCODE(ret) \
++do { \
++ if (ret < 0) { \
++ dev_err(&mipi_dsi->pdev->dev, \
++ "%s ERR: ret:%d, line:%d.\n", \
++ __func__, ret, __LINE__); \
++ return ret; \
++ } \
++} while (0)
++
++static int hx8369bl_brightness;
++static int mipid_init_backlight(struct mipi_dsi_info *mipi_dsi);
++
++static struct fb_videomode truly_lcd_modedb[] = {
++ {
++ "TRULY-WVGA", 64, 480, 800, 37880,
++ 8, 8,
++ 6, 6,
++ 8, 6,
++ FB_SYNC_OE_LOW_ACT,
++ FB_VMODE_NONINTERLACED,
++ 0,
++ },
++};
++
++static struct mipi_lcd_config lcd_config = {
++ .virtual_ch = 0x0,
++ .data_lane_num = HX8369_TWO_DATA_LANE,
++ .max_phy_clk = HX8369_MAX_DPHY_CLK,
++ .dpi_fmt = MIPI_RGB888,
++};
++void mipid_hx8369_get_lcd_videomode(struct fb_videomode **mode, int *size,
++ struct mipi_lcd_config **data)
++{
++ *mode = &truly_lcd_modedb[0];
++ *size = ARRAY_SIZE(truly_lcd_modedb);
++ *data = &lcd_config;
++}
++
++int mipid_hx8369_lcd_setup(struct mipi_dsi_info *mipi_dsi)
++{
++ u32 buf[DSI_CMD_BUF_MAXSIZE];
++ int err;
++
++ dev_dbg(&mipi_dsi->pdev->dev, "MIPI DSI LCD setup.\n");
++ buf[0] = HX8369_CMD_SETEXTC | (HX8369_CMD_SETEXTC_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETEXTC_LEN);
++ CHECK_RETCODE(err);
++ buf[0] = MIPI_DSI_MAX_RET_PACK_SIZE;
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
++ buf, 0);
++ CHECK_RETCODE(err);
++ buf[0] = HX8369_CMD_GETHXID;
++ err = mipi_dsi_pkt_read(mipi_dsi,
++ MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM,
++ buf, HX8369_CMD_GETHXID_LEN);
++ if (!err && ((buf[0] & HX8369_ID_MASK) == HX8369_ID)) {
++ dev_info(&mipi_dsi->pdev->dev,
++ "MIPI DSI LCD ID:0x%x.\n", buf[0]);
++ } else {
++ dev_err(&mipi_dsi->pdev->dev,
++ "mipi_dsi_pkt_read err:%d, data:0x%x.\n",
++ err, buf[0]);
++ dev_info(&mipi_dsi->pdev->dev,
++ "MIPI DSI LCD not detected!\n");
++ return err;
++ }
++
++ /* set LCD resolution as 480RGBx800, DPI interface,
++ * display operation mode: RGB data bypass GRAM mode.
++ */
++ buf[0] = HX8369_CMD_SETDISP | (HX8369_CMD_SETDISP_1_HALT << 8) |
++ (HX8369_CMD_SETDISP_2_RES_MODE << 16) |
++ (HX8369_CMD_SETDISP_3_BP << 24);
++ buf[1] = HX8369_CMD_SETDISP_4_FP | (HX8369_CMD_SETDISP_5_SAP << 8) |
++ (HX8369_CMD_SETDISP_6_GENON << 16) |
++ (HX8369_CMD_SETDISP_7_GENOFF << 24);
++ buf[2] = HX8369_CMD_SETDISP_8_RTN | (HX8369_CMD_SETDISP_9_TEI << 8) |
++ (HX8369_CMD_SETDISP_10_TEP_UP << 16) |
++ (HX8369_CMD_SETDISP_11_TEP_LOW << 24);
++ buf[3] = HX8369_CMD_SETDISP_12_BP_PE |
++ (HX8369_CMD_SETDISP_13_FP_PE << 8) |
++ (HX8369_CMD_SETDISP_14_RTN_PE << 16) |
++ (HX8369_CMD_SETDISP_15_GON << 24);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETDISP_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set display waveform cycle */
++ buf[0] = HX8369_CMD_SETCYC | (HX8369_CMD_SETCYC_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETCYC_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETCYC_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set GIP timing output control */
++ buf[0] = HX8369_CMD_SETGIP | (HX8369_CMD_SETGIP_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETGIP_PARAM_2;
++ buf[2] = HX8369_CMD_SETGIP_PARAM_3;
++ buf[3] = HX8369_CMD_SETGIP_PARAM_4;
++ buf[4] = HX8369_CMD_SETGIP_PARAM_5;
++ buf[5] = HX8369_CMD_SETGIP_PARAM_6;
++ buf[6] = HX8369_CMD_SETGIP_PARAM_7;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETGIP_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set power: standby, DC etc. */
++ buf[0] = HX8369_CMD_SETPOWER | (HX8369_CMD_SETPOWER_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETPOWER_PARAM_2;
++ buf[2] = HX8369_CMD_SETPOWER_PARAM_3;
++ buf[3] = HX8369_CMD_SETPOWER_PARAM_4;
++ buf[4] = HX8369_CMD_SETPOWER_PARAM_5;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETPOWER_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set VCOM voltage. */
++ buf[0] = HX8369_CMD_SETVCOM | (HX8369_CMD_SETVCOM_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETVCOM_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set Panel: BGR/RGB or Inversion. */
++ buf[0] = HX8369_CMD_SETPANEL | (HX8369_CMD_SETPANEL_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi,
++ MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM, buf, 0);
++ CHECK_RETCODE(err);
++
++ /* Set gamma curve related setting */
++ buf[0] = HX8369_CMD_SETGAMMA | (HX8369_CMD_SETGAMMA_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETGAMMA_PARAM_2;
++ buf[2] = HX8369_CMD_SETGAMMA_PARAM_3;
++ buf[3] = HX8369_CMD_SETGAMMA_PARAM_4;
++ buf[4] = HX8369_CMD_SETGAMMA_PARAM_5;
++ buf[5] = HX8369_CMD_SETGAMMA_PARAM_6;
++ buf[7] = HX8369_CMD_SETGAMMA_PARAM_7;
++ buf[7] = HX8369_CMD_SETGAMMA_PARAM_8;
++ buf[8] = HX8369_CMD_SETGAMMA_PARAM_9;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETGAMMA_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set MIPI: DPHYCMD & DSICMD, data lane number */
++ buf[0] = HX8369_CMD_SETMIPI | (HX8369_CMD_SETMIPI_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETMIPI_PARAM_2;
++ buf[2] = HX8369_CMD_SETMIPI_PARAM_3;
++ if (lcd_config.data_lane_num == HX8369_ONE_DATA_LANE)
++ buf[2] |= HX8369_CMD_SETMIPI_ONELANE;
++ else
++ buf[2] |= HX8369_CMD_SETMIPI_TWOLANE;
++ buf[3] = HX8369_CMD_SETMIPI_PARAM_4;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE, buf,
++ HX8369_CMD_SETMIPI_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set pixel format:24bpp */
++ buf[0] = HX8369_CMD_SETPIXEL_FMT;
++ switch (lcd_config.dpi_fmt) {
++ case MIPI_RGB565_PACKED:
++ case MIPI_RGB565_LOOSELY:
++ case MIPI_RGB565_CONFIG3:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_16BPP << 8);
++ break;
++
++ case MIPI_RGB666_LOOSELY:
++ case MIPI_RGB666_PACKED:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_18BPP << 8);
++ break;
++
++ case MIPI_RGB888:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_24BPP << 8);
++ break;
++
++ default:
++ buf[0] |= (HX8369_CMD_SETPIXEL_FMT_24BPP << 8);
++ break;
++ }
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ /* Set column address: 0~479 */
++ buf[0] = HX8369_CMD_SETCLUMN_ADDR |
++ (HX8369_CMD_SETCLUMN_ADDR_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETCLUMN_ADDR_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETCLUMN_ADDR_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set page address: 0~799 */
++ buf[0] = HX8369_CMD_SETPAGE_ADDR |
++ (HX8369_CMD_SETPAGE_ADDR_PARAM_1 << 8);
++ buf[1] = HX8369_CMD_SETPAGE_ADDR_PARAM_2;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_LONG_WRITE,
++ buf, HX8369_CMD_SETPAGE_ADDR_LEN);
++ CHECK_RETCODE(err);
++
++ /* Set display brightness related */
++ buf[0] = HX8369_CMD_WRT_DISP_BRIGHT |
++ (HX8369_CMD_WRT_DISP_BRIGHT_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ buf[0] = HX8369_CMD_WRT_CABC_CTRL |
++ (HX8369_CMD_WRT_CABC_CTRL_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ buf[0] = HX8369_CMD_WRT_CTRL_DISP |
++ (HX8369_CMD_WRT_CTRL_DISP_PARAM_1 << 8);
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ /* exit sleep mode and set display on */
++ buf[0] = MIPI_DCS_EXIT_SLEEP_MODE;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++ /* To allow time for the supply voltages
++ * and clock circuits to stabilize.
++ */
++ msleep(5);
++ buf[0] = MIPI_DCS_SET_DISPLAY_ON;
++ err = mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM,
++ buf, 0);
++ CHECK_RETCODE(err);
++
++ err = mipid_init_backlight(mipi_dsi);
++ return err;
++}
++
++static int mipid_bl_update_status(struct backlight_device *bl)
++{
++ u32 buf;
++ int brightness = bl->props.brightness;
++ struct mipi_dsi_info *mipi_dsi = bl_get_data(bl);
++
++ if (bl->props.power != FB_BLANK_UNBLANK ||
++ bl->props.fb_blank != FB_BLANK_UNBLANK)
++ brightness = 0;
++
++ buf = HX8369_CMD_WRT_DISP_BRIGHT |
++ ((brightness & HX8369BL_MAX_BRIGHT) << 8);
++ mipi_dsi_pkt_write(mipi_dsi, MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM,
++ &buf, 0);
++
++ hx8369bl_brightness = brightness & HX8369BL_MAX_BRIGHT;
++
++ dev_dbg(&bl->dev, "mipid backlight bringtness:%d.\n", brightness);
++ return 0;
++}
++
++static int mipid_bl_get_brightness(struct backlight_device *bl)
++{
++ return hx8369bl_brightness;
++}
++
++static int mipi_bl_check_fb(struct backlight_device *bl, struct fb_info *fbi)
++{
++ return 0;
++}
++
++static const struct backlight_ops mipid_lcd_bl_ops = {
++ .update_status = mipid_bl_update_status,
++ .get_brightness = mipid_bl_get_brightness,
++ .check_fb = mipi_bl_check_fb,
++};
++
++static int mipid_init_backlight(struct mipi_dsi_info *mipi_dsi)
++{
++ struct backlight_properties props;
++ struct backlight_device *bl;
++
++ if (mipi_dsi->bl) {
++ pr_debug("mipid backlight already init!\n");
++ return 0;
++ }
++ memset(&props, 0, sizeof(struct backlight_properties));
++ props.max_brightness = HX8369BL_MAX_BRIGHT;
++ props.type = BACKLIGHT_RAW;
++ bl = backlight_device_register("mipid-bl", &mipi_dsi->pdev->dev,
++ mipi_dsi, &mipid_lcd_bl_ops, &props);
++ if (IS_ERR(bl)) {
++ pr_err("error %ld on backlight register\n", PTR_ERR(bl));
++ return PTR_ERR(bl);
++ }
++ mipi_dsi->bl = bl;
++ bl->props.power = FB_BLANK_UNBLANK;
++ bl->props.fb_blank = FB_BLANK_UNBLANK;
++ bl->props.brightness = HX8369BL_DEF_BRIGHT;
++
++ mipid_bl_update_status(bl);
++ return 0;
++}
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_hdmi.c linux-3.14.72/drivers/video/mxc/mxc_hdmi.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_hdmi.c 2016-06-19 22:11:55.353136857 +0200
+@@ -0,0 +1,3192 @@
++/*
++ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++/*
++ * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
++ * for SLISHDMI13T and SLIPHDMIT IP cores
++ *
++ * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/io.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/list.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++#include <linux/uaccess.h>
++#include <linux/cpufreq.h>
++#include <linux/firmware.h>
++#include <linux/kthread.h>
++#include <linux/regulator/driver.h>
++#include <linux/fsl_devices.h>
++#include <linux/ipu.h>
++#include <linux/regmap.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/of_device.h>
++
++#include <linux/console.h>
++#include <linux/types.h>
++
++#include "../edid.h"
++#include <video/mxc_edid.h>
++#include <video/mxc_hdmi.h>
++#include "mxc_dispdrv.h"
++
++#include <linux/mfd/mxc-hdmi-core.h>
++
++#define DISPDRV_HDMI "hdmi"
++#define HDMI_EDID_LEN 512
++
++/* status codes for reading edid */
++#define HDMI_EDID_SUCCESS 0
++#define HDMI_EDID_FAIL -1
++#define HDMI_EDID_SAME -2
++#define HDMI_EDID_NO_MODES -3
++
++#define NUM_CEA_VIDEO_MODES 64
++#define DEFAULT_VIDEO_MODE 16 /* 1080P */
++
++#define RGB 0
++#define YCBCR444 1
++#define YCBCR422_16BITS 2
++#define YCBCR422_8BITS 3
++#define XVYCC444 4
++
++/*
++ * We follow a flowchart which is in the "Synopsys DesignWare Courses
++ * HDMI Transmitter Controller User Guide, 1.30a", section 3.1
++ * (dwc_hdmi_tx_user.pdf)
++ *
++ * Below are notes that say "HDMI Initialization Step X"
++ * These correspond to the flowchart.
++ */
++
++/*
++ * We are required to configure VGA mode before reading edid
++ * in HDMI Initialization Step B
++ */
++static const struct fb_videomode vga_mode = {
++ /* 640x480 @ 60 Hz, 31.5 kHz hsync */
++ NULL, 60, 640, 480, 39721, 48, 16, 33, 10, 96, 2, 0,
++ FB_VMODE_NONINTERLACED | FB_VMODE_ASPECT_4_3, FB_MODE_IS_VESA,
++};
++
++enum hdmi_datamap {
++ RGB444_8B = 0x01,
++ RGB444_10B = 0x03,
++ RGB444_12B = 0x05,
++ RGB444_16B = 0x07,
++ YCbCr444_8B = 0x09,
++ YCbCr444_10B = 0x0B,
++ YCbCr444_12B = 0x0D,
++ YCbCr444_16B = 0x0F,
++ YCbCr422_8B = 0x16,
++ YCbCr422_10B = 0x14,
++ YCbCr422_12B = 0x12,
++};
++
++enum hdmi_colorimetry {
++ eITU601,
++ eITU709,
++};
++
++struct hdmi_vmode {
++ bool mDVI;
++ bool mHSyncPolarity;
++ bool mVSyncPolarity;
++ bool mInterlaced;
++ bool mDataEnablePolarity;
++
++ unsigned int mPixelClock;
++ unsigned int mPixelRepetitionInput;
++ unsigned int mPixelRepetitionOutput;
++};
++
++struct hdmi_data_info {
++ unsigned int enc_in_format;
++ unsigned int enc_out_format;
++ unsigned int enc_color_depth;
++ unsigned int colorimetry;
++ unsigned int pix_repet_factor;
++ unsigned int hdcp_enable;
++ unsigned int rgb_out_enable;
++ unsigned int rgb_quant_range;
++ struct hdmi_vmode video_mode;
++};
++
++struct hdmi_phy_reg_config {
++ /* HDMI PHY register config for pass HCT */
++ u16 reg_vlev;
++ u16 reg_cksymtx;
++};
++
++enum hotplug_state {
++ HDMI_HOTPLUG_DISCONNECTED,
++ HDMI_HOTPLUG_CONNECTED_HDMI,
++ HDMI_HOTPLUG_CONNECTED_DVI,
++ HDMI_HOTPLUG_CONNECTED_NO_EDID,
++};
++
++struct mxc_hdmi {
++ struct platform_device *pdev;
++ struct platform_device *core_pdev;
++ struct mxc_dispdrv_handle *disp_mxc_hdmi;
++ struct fb_info *fbi;
++ struct clk *hdmi_isfr_clk;
++ struct clk *hdmi_iahb_clk;
++ struct clk *mipi_core_clk;
++ struct timer_list jitter_timer;
++ struct work_struct hotplug_work;
++ struct delayed_work hdcp_hdp_work;
++
++ struct notifier_block nb;
++
++ struct hdmi_data_info hdmi_data;
++ int vic;
++ struct mxc_edid_cfg edid_cfg;
++ u8 edid[HDMI_EDID_LEN];
++ bool fb_reg;
++ enum hotplug_state hp_state;
++ u8 blank;
++ bool dft_mode_set;
++ char *dft_mode_str;
++ int default_bpp;
++ u8 latest_intr_stat;
++ u8 plug_event;
++ u8 plug_mask;
++ spinlock_t irq_lock;
++ bool phy_enabled;
++ struct fb_videomode default_mode;
++ struct fb_videomode previous_non_vga_mode;
++ struct prev_virtual_t {
++ u32 xres_virtual;
++ u32 yres_virtual;
++ } prev_virtual;
++
++ int *gpr_base;
++ int *gpr_hdmi_base;
++ int *gpr_sdma_base;
++ int cpu_type;
++ int cpu_version;
++ struct hdmi_phy_reg_config phy_config;
++
++ struct pinctrl *pinctrl;
++};
++
++static int hdmi_major;
++static struct class *hdmi_class;
++
++struct i2c_client *hdmi_i2c;
++struct mxc_hdmi *g_hdmi;
++
++static bool hdmi_inited;
++static bool hdcp_init;
++
++extern const struct fb_videomode mxc_cea_mode[64];
++extern void mxc_hdmi_cec_handle(u16 cec_stat);
++
++extern int mxcfb_blank(int blank, struct fb_info *info);
++
++static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event);
++static void hdmi_enable_overflow_interrupts(void);
++static void hdmi_disable_overflow_interrupts(void);
++static unsigned int getRGBQuantRange(struct mxc_hdmi *hdmi);
++
++static char *rgb_quant_range = "auto";
++module_param(rgb_quant_range, charp, S_IRUGO);
++MODULE_PARM_DESC(rgb_quant_range, "RGB Quant Range (auto, default, limited, full)");
++
++static bool ignore_edid = 0;
++module_param(ignore_edid, bool, S_IRUGO);
++MODULE_PARM_DESC(ignore_edid, "Ignore EDID (default=0)");
++
++static struct platform_device_id imx_hdmi_devtype[] = {
++ {
++ .name = "hdmi-imx6DL",
++ .driver_data = IMX6DL_HDMI,
++ }, {
++ .name = "hdmi-imx6Q",
++ .driver_data = IMX6Q_HDMI,
++ }, {
++ /* sentinel */
++ }
++};
++MODULE_DEVICE_TABLE(platform, imx_hdmi_devtype);
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-hdmi-video", .data = &imx_hdmi_devtype[IMX6DL_HDMI], },
++ { .compatible = "fsl,imx6q-hdmi-video", .data = &imx_hdmi_devtype[IMX6Q_HDMI], },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
++
++static inline int cpu_is_imx6dl(struct mxc_hdmi *hdmi)
++{
++ return hdmi->cpu_type == IMX6DL_HDMI;
++}
++#ifdef DEBUG
++static void dump_fb_videomode(struct fb_videomode *m)
++{
++ pr_debug("fb_videomode = %d %d %d %d %d %d %d %d %d %d %d %d %d\n",
++ m->refresh, m->xres, m->yres, m->pixclock, m->left_margin,
++ m->right_margin, m->upper_margin, m->lower_margin,
++ m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
++}
++#else
++static void dump_fb_videomode(struct fb_videomode *m)
++{}
++#endif
++
++static ssize_t mxc_hdmi_show_name(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ strcpy(buf, hdmi->fbi->fix.id);
++ sprintf(buf+strlen(buf), "\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(fb_name, S_IRUGO, mxc_hdmi_show_name, NULL);
++
++static ssize_t mxc_hdmi_show_state(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ switch (hdmi->hp_state)
++ {
++ case HDMI_HOTPLUG_CONNECTED_HDMI:
++ strcpy(buf, "plugin HDMI\n");
++ break;
++ case HDMI_HOTPLUG_CONNECTED_DVI:
++ strcpy(buf, "plugin DVI\n");
++ break;
++ case HDMI_HOTPLUG_CONNECTED_NO_EDID:
++ strcpy(buf, "plugin NO EDID\n");
++ break;
++ case HDMI_HOTPLUG_DISCONNECTED:
++ default:
++ strcpy(buf, "plugout\n");
++ }
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(cable_state, S_IRUGO, mxc_hdmi_show_state, NULL);
++
++static ssize_t mxc_hdmi_show_edid(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int j;
++
++ for (j = 0; j < HDMI_EDID_LEN; j++)
++ buf[j] = hdmi->edid[j];
++
++ return HDMI_EDID_LEN;
++}
++
++static DEVICE_ATTR(edid, S_IRUGO, mxc_hdmi_show_edid, NULL);
++
++static ssize_t mxc_hdmi_show_rgb_out_enable(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->hdmi_data.rgb_out_enable == true)
++ strcpy(buf, "RGB out\n");
++ else
++ strcpy(buf, "YCbCr out\n");
++
++ return strlen(buf);
++}
++
++static ssize_t mxc_hdmi_store_rgb_out_enable(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ unsigned long value;
++ int ret;
++
++ ret = strict_strtoul(buf, 10, &value);
++ if (ret)
++ return ret;
++
++ hdmi->hdmi_data.rgb_out_enable = value;
++
++ /* Reconfig HDMI for output color space change */
++ mxc_hdmi_setup(hdmi, 0);
++
++ return count;
++}
++
++static DEVICE_ATTR(rgb_out_enable, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_rgb_out_enable,
++ mxc_hdmi_store_rgb_out_enable);
++
++static ssize_t mxc_hdmi_show_rgb_quant_range(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int n;
++
++ switch (getRGBQuantRange(hdmi)) {
++ case HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE:
++ strcpy(buf, "limited\n");
++ break;
++ case HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE:
++ strcpy(buf, "full\n");
++ break;
++ case HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT:
++ default:
++ strcpy(buf, "default\n");
++ break;
++ };
++
++ n = strlen(buf);
++
++ if (hdmi->hdmi_data.rgb_quant_range == HDMI_FC_AVICONF2_RGB_QUANT_MASK) {
++ strcpy(buf + n - 1, " (auto)\n");
++ n += 7;
++ }
++
++ return n;
++}
++
++static ssize_t mxc_hdmi_store_rgb_quant_range(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ int ret = count;
++
++ if (sysfs_streq("limited", buf)) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE;
++ } else if (sysfs_streq("full", buf)) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE;
++ } else if (sysfs_streq("default", buf)) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT;
++ } else if (sysfs_streq("auto", buf)) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_MASK;
++ } else {
++ ret = -EINVAL;
++ goto out;
++ }
++
++ /* Reconfig HDMI for output RGB Quant Range change if using RGB out */
++ if(hdmi->hdmi_data.rgb_out_enable)
++ mxc_hdmi_setup(hdmi, 0);
++out:
++ return ret;
++}
++
++static DEVICE_ATTR(rgb_quant_range, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_rgb_quant_range,
++ mxc_hdmi_store_rgb_quant_range);
++
++static ssize_t mxc_hdmi_show_hdcp_enable(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++
++ if (hdmi->hdmi_data.hdcp_enable == false)
++ strcpy(buf, "hdcp disable\n");
++ else
++ strcpy(buf, "hdcp enable\n");
++
++ return strlen(buf);
++
++}
++
++static ssize_t mxc_hdmi_store_hdcp_enable(struct device *dev,
++ struct device_attribute *attr, const char *buf, size_t count)
++{
++ struct mxc_hdmi *hdmi = dev_get_drvdata(dev);
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++ unsigned long value;
++ int ret;
++
++ ret = strict_strtoul(buf, 10, &value);
++ if (ret)
++ return ret;
++
++ hdmi->hdmi_data.hdcp_enable = value;
++
++ /* Reconfig HDMI for HDCP */
++ mxc_hdmi_setup(hdmi, 0);
++
++ if (hdmi->hdmi_data.hdcp_enable == false) {
++ sprintf(event_string, "EVENT=hdcpdisable");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++ } else {
++ sprintf(event_string, "EVENT=hdcpenable");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++ }
++
++ return count;
++
++}
++
++static DEVICE_ATTR(hdcp_enable, S_IRUGO | S_IWUSR,
++ mxc_hdmi_show_hdcp_enable, mxc_hdmi_store_hdcp_enable);
++
++/*!
++ * this submodule is responsible for the video data synchronization.
++ * for example, for RGB 4:4:4 input, the data map is defined as
++ * pin{47~40} <==> R[7:0]
++ * pin{31~24} <==> G[7:0]
++ * pin{15~8} <==> B[7:0]
++ */
++static void hdmi_video_sample(struct mxc_hdmi *hdmi)
++{
++ int color_format = 0;
++ u8 val;
++
++ if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x01;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x03;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x05;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x07;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x09;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x0B;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x0D;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_format = 0x0F;
++ else
++ return;
++ } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_format = 0x16;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_format = 0x14;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_format = 0x12;
++ else
++ return;
++ }
++
++ val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
++ ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
++ hdmi_writeb(val, HDMI_TX_INVID0);
++
++ /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
++ val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
++ hdmi_writeb(val, HDMI_TX_INSTUFFING);
++ hdmi_writeb(0x0, HDMI_TX_GYDATA0);
++ hdmi_writeb(0x0, HDMI_TX_GYDATA1);
++ hdmi_writeb(0x0, HDMI_TX_RCRDATA0);
++ hdmi_writeb(0x0, HDMI_TX_RCRDATA1);
++ hdmi_writeb(0x0, HDMI_TX_BCBDATA0);
++ hdmi_writeb(0x0, HDMI_TX_BCBDATA1);
++}
++
++static unsigned int getRGBQuantRange(struct mxc_hdmi *hdmi)
++{
++ if (hdmi->hdmi_data.rgb_quant_range != HDMI_FC_AVICONF2_RGB_QUANT_MASK)
++ return hdmi->hdmi_data.rgb_quant_range;
++
++ return hdmi->edid_cfg.cea_rgb_range_selectable ?
++ HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE : HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT;
++}
++
++static int isColorSpaceConversion(struct mxc_hdmi *hdmi)
++{
++ unsigned int rgb_quant_range = getRGBQuantRange(hdmi);
++
++ return (hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format) ||
++ (hdmi->hdmi_data.enc_out_format == RGB &&
++ ((rgb_quant_range == HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE) ||
++ (rgb_quant_range == HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT && hdmi->vic > 1)));
++}
++
++static int isColorSpaceDecimation(struct mxc_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_in_format == RGB ||
++ hdmi->hdmi_data.enc_in_format == YCBCR444));
++}
++
++static int isColorSpaceInterpolation(struct mxc_hdmi *hdmi)
++{
++ return ((hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) &&
++ (hdmi->hdmi_data.enc_out_format == RGB
++ || hdmi->hdmi_data.enc_out_format == YCBCR444));
++}
++
++/*!
++ * update the color space conversion coefficients.
++ */
++static void update_csc_coeffs(struct mxc_hdmi *hdmi)
++{
++ unsigned short csc_coeff[3][4];
++ unsigned int csc_scale = 1;
++ u8 val;
++ bool coeff_selected = false;
++
++ if (isColorSpaceConversion(hdmi)) { /* csc needed */
++ if (hdmi->hdmi_data.enc_out_format == RGB) {
++ if (hdmi->hdmi_data.enc_in_format == RGB) {
++ csc_coeff[0][0] = 0x1b80;
++ csc_coeff[0][1] = 0x0000;
++ csc_coeff[0][2] = 0x0000;
++ csc_coeff[0][3] = 0x0020;
++
++ csc_coeff[1][0] = 0x0000;
++ csc_coeff[1][1] = 0x1b80;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x0020;
++
++ csc_coeff[2][0] = 0x0000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x1b80;
++ csc_coeff[2][3] = 0x0020;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU601) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x6926;
++ csc_coeff[0][2] = 0x74fd;
++ csc_coeff[0][3] = 0x010e;
++
++ csc_coeff[1][0] = 0x2000;
++ csc_coeff[1][1] = 0x2cdd;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x7e9a;
++
++ csc_coeff[2][0] = 0x2000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x38b4;
++ csc_coeff[2][3] = 0x7e3b;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x7106;
++ csc_coeff[0][2] = 0x7a02;
++ csc_coeff[0][3] = 0x00a7;
++
++ csc_coeff[1][0] = 0x2000;
++ csc_coeff[1][1] = 0x3264;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x7e6d;
++
++ csc_coeff[2][0] = 0x2000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x3b61;
++ csc_coeff[2][3] = 0x7e25;
++
++ csc_scale = 1;
++ coeff_selected = true;
++ }
++ } else if (hdmi->hdmi_data.enc_in_format == RGB) {
++ if (hdmi->hdmi_data.colorimetry == eITU601) {
++ csc_coeff[0][0] = 0x2591;
++ csc_coeff[0][1] = 0x1322;
++ csc_coeff[0][2] = 0x074b;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x6535;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x7acc;
++ csc_coeff[1][3] = 0x0200;
++
++ csc_coeff[2][0] = 0x6acd;
++ csc_coeff[2][1] = 0x7534;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0200;
++
++ csc_scale = 0;
++ coeff_selected = true;
++ } else if (hdmi->hdmi_data.colorimetry == eITU709) {
++ csc_coeff[0][0] = 0x2dc5;
++ csc_coeff[0][1] = 0x0d9b;
++ csc_coeff[0][2] = 0x049e;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x62f0;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x7d11;
++ csc_coeff[1][3] = 0x0200;
++
++ csc_coeff[2][0] = 0x6756;
++ csc_coeff[2][1] = 0x78ab;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0200;
++
++ csc_scale = 0;
++ coeff_selected = true;
++ }
++ }
++ }
++
++ if (!coeff_selected) {
++ csc_coeff[0][0] = 0x2000;
++ csc_coeff[0][1] = 0x0000;
++ csc_coeff[0][2] = 0x0000;
++ csc_coeff[0][3] = 0x0000;
++
++ csc_coeff[1][0] = 0x0000;
++ csc_coeff[1][1] = 0x2000;
++ csc_coeff[1][2] = 0x0000;
++ csc_coeff[1][3] = 0x0000;
++
++ csc_coeff[2][0] = 0x0000;
++ csc_coeff[2][1] = 0x0000;
++ csc_coeff[2][2] = 0x2000;
++ csc_coeff[2][3] = 0x0000;
++
++ csc_scale = 1;
++ }
++
++ /* Update CSC parameters in HDMI CSC registers */
++ hdmi_writeb((unsigned char)(csc_coeff[0][0] & 0xFF),
++ HDMI_CSC_COEF_A1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][0] >> 8),
++ HDMI_CSC_COEF_A1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][1] & 0xFF),
++ HDMI_CSC_COEF_A2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][1] >> 8),
++ HDMI_CSC_COEF_A2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][2] & 0xFF),
++ HDMI_CSC_COEF_A3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][2] >> 8),
++ HDMI_CSC_COEF_A3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][3] & 0xFF),
++ HDMI_CSC_COEF_A4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[0][3] >> 8),
++ HDMI_CSC_COEF_A4_MSB);
++
++ hdmi_writeb((unsigned char)(csc_coeff[1][0] & 0xFF),
++ HDMI_CSC_COEF_B1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][0] >> 8),
++ HDMI_CSC_COEF_B1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][1] & 0xFF),
++ HDMI_CSC_COEF_B2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][1] >> 8),
++ HDMI_CSC_COEF_B2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][2] & 0xFF),
++ HDMI_CSC_COEF_B3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][2] >> 8),
++ HDMI_CSC_COEF_B3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][3] & 0xFF),
++ HDMI_CSC_COEF_B4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[1][3] >> 8),
++ HDMI_CSC_COEF_B4_MSB);
++
++ hdmi_writeb((unsigned char)(csc_coeff[2][0] & 0xFF),
++ HDMI_CSC_COEF_C1_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][0] >> 8),
++ HDMI_CSC_COEF_C1_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][1] & 0xFF),
++ HDMI_CSC_COEF_C2_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][1] >> 8),
++ HDMI_CSC_COEF_C2_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][2] & 0xFF),
++ HDMI_CSC_COEF_C3_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][2] >> 8),
++ HDMI_CSC_COEF_C3_MSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][3] & 0xFF),
++ HDMI_CSC_COEF_C4_LSB);
++ hdmi_writeb((unsigned char)(csc_coeff[2][3] >> 8),
++ HDMI_CSC_COEF_C4_MSB);
++
++ val = hdmi_readb(HDMI_CSC_SCALE);
++ val &= ~HDMI_CSC_SCALE_CSCSCALE_MASK;
++ val |= csc_scale & HDMI_CSC_SCALE_CSCSCALE_MASK;
++ hdmi_writeb(val, HDMI_CSC_SCALE);
++}
++
++static void hdmi_video_csc(struct mxc_hdmi *hdmi)
++{
++ int color_depth = 0;
++ int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
++ int decimation = HDMI_CSC_CFG_DECMODE_DISABLE;
++ u8 val;
++
++ /* YCC422 interpolation to 444 mode */
++ if (isColorSpaceInterpolation(hdmi))
++ interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
++ else if (isColorSpaceDecimation(hdmi))
++ decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
++
++ if (hdmi->hdmi_data.enc_color_depth == 8)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 10)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 12)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
++ else if (hdmi->hdmi_data.enc_color_depth == 16)
++ color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
++ else
++ return;
++
++ /*configure the CSC registers */
++ hdmi_writeb(interpolation | decimation, HDMI_CSC_CFG);
++ val = hdmi_readb(HDMI_CSC_SCALE);
++ val &= ~HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK;
++ val |= color_depth;
++ hdmi_writeb(val, HDMI_CSC_SCALE);
++
++ update_csc_coeffs(hdmi);
++}
++
++/*!
++ * HDMI video packetizer is used to packetize the data.
++ * for example, if input is YCC422 mode or repeater is used,
++ * data should be repacked this module can be bypassed.
++ */
++static void hdmi_video_packetize(struct mxc_hdmi *hdmi)
++{
++ unsigned int color_depth = 0;
++ unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
++ struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
++ u8 val;
++
++ if (hdmi_data->enc_out_format == RGB
++ || hdmi_data->enc_out_format == YCBCR444) {
++ if (hdmi_data->enc_color_depth == 0)
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ else if (hdmi_data->enc_color_depth == 8) {
++ color_depth = 4;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
++ } else if (hdmi_data->enc_color_depth == 10)
++ color_depth = 5;
++ else if (hdmi_data->enc_color_depth == 12)
++ color_depth = 6;
++ else if (hdmi_data->enc_color_depth == 16)
++ color_depth = 7;
++ else
++ return;
++ } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
++ if (hdmi_data->enc_color_depth == 0 ||
++ hdmi_data->enc_color_depth == 8)
++ remap_size = HDMI_VP_REMAP_YCC422_16bit;
++ else if (hdmi_data->enc_color_depth == 10)
++ remap_size = HDMI_VP_REMAP_YCC422_20bit;
++ else if (hdmi_data->enc_color_depth == 12)
++ remap_size = HDMI_VP_REMAP_YCC422_24bit;
++ else
++ return;
++ output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
++ } else
++ return;
++
++ /* HDMI not support deep color,
++ * because IPU MAX support color depth is 24bit */
++ color_depth = 0;
++
++ /* set the packetizer registers */
++ val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
++ ((hdmi_data->pix_repet_factor <<
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
++ hdmi_writeb(val, HDMI_VP_PR_CD);
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~HDMI_VP_STUFF_PR_STUFFING_MASK;
++ val |= HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ /* Data from pixel repeater block */
++ if (hdmi_data->pix_repet_factor > 1) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
++ HDMI_VP_CONF_BYPASS_SELECT_MASK);
++ val |= HDMI_VP_CONF_PR_EN_ENABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else { /* data from packetizer block */
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_PR_EN_MASK |
++ HDMI_VP_CONF_BYPASS_SELECT_MASK);
++ val |= HDMI_VP_CONF_PR_EN_DISABLE |
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ }
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~HDMI_VP_STUFF_IDEFAULT_PHASE_MASK;
++ val |= 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ hdmi_writeb(remap_size, HDMI_VP_REMAP);
++
++ if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_ENABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_DISABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_ENABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~(HDMI_VP_CONF_BYPASS_EN_MASK |
++ HDMI_VP_CONF_PP_EN_ENMASK |
++ HDMI_VP_CONF_YCC422_EN_MASK);
++ val |= HDMI_VP_CONF_BYPASS_EN_ENABLE |
++ HDMI_VP_CONF_PP_EN_DISABLE |
++ HDMI_VP_CONF_YCC422_EN_DISABLE;
++ hdmi_writeb(val, HDMI_VP_CONF);
++ } else {
++ return;
++ }
++
++ val = hdmi_readb(HDMI_VP_STUFF);
++ val &= ~(HDMI_VP_STUFF_PP_STUFFING_MASK |
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK);
++ val |= HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE;
++ hdmi_writeb(val, HDMI_VP_STUFF);
++
++ val = hdmi_readb(HDMI_VP_CONF);
++ val &= ~HDMI_VP_CONF_OUTPUT_SELECTOR_MASK;
++ val |= output_select;
++ hdmi_writeb(val, HDMI_VP_CONF);
++}
++
++#if 0
++/* Force a fixed color screen */
++static void hdmi_video_force_output(struct mxc_hdmi *hdmi, unsigned char force)
++{
++ u8 val;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (force) {
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
++ hdmi_writeb(0xFF, HDMI_FC_DBGTMDS0); /* B */
++ val = hdmi_readb(HDMI_FC_DBGFORCE);
++ val |= HDMI_FC_DBGFORCE_FORCEVIDEO;
++ hdmi_writeb(val, HDMI_FC_DBGFORCE);
++ } else {
++ val = hdmi_readb(HDMI_FC_DBGFORCE);
++ val &= ~HDMI_FC_DBGFORCE_FORCEVIDEO;
++ hdmi_writeb(val, HDMI_FC_DBGFORCE);
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS2); /* R */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS1); /* G */
++ hdmi_writeb(0x00, HDMI_FC_DBGTMDS0); /* B */
++ }
++}
++#endif
++
++static inline void hdmi_phy_test_clear(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTCLR_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTCLR_OFFSET) &
++ HDMI_PHY_TST0_TSTCLR_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_enable(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTEN_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTEN_OFFSET) &
++ HDMI_PHY_TST0_TSTEN_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_clock(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ u8 val = hdmi_readb(HDMI_PHY_TST0);
++ val &= ~HDMI_PHY_TST0_TSTCLK_MASK;
++ val |= (bit << HDMI_PHY_TST0_TSTCLK_OFFSET) &
++ HDMI_PHY_TST0_TSTCLK_MASK;
++ hdmi_writeb(val, HDMI_PHY_TST0);
++}
++
++static inline void hdmi_phy_test_din(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(bit, HDMI_PHY_TST1);
++}
++
++static inline void hdmi_phy_test_dout(struct mxc_hdmi *hdmi,
++ unsigned char bit)
++{
++ hdmi_writeb(bit, HDMI_PHY_TST2);
++}
++
++static bool hdmi_phy_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
++{
++ unsigned char val = 0;
++ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ while (val == 0) {
++ udelay(1000);
++ if (msec-- == 0)
++ return false;
++ val = hdmi_readb(HDMI_IH_I2CMPHY_STAT0) & 0x3;
++ }
++ return true;
++}
++
++static void hdmi_phy_i2c_write(struct mxc_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
++ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
++ hdmi_writeb((unsigned char)(data >> 8),
++ HDMI_PHY_I2CM_DATAO_1_ADDR);
++ hdmi_writeb((unsigned char)(data >> 0),
++ HDMI_PHY_I2CM_DATAO_0_ADDR);
++ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
++ HDMI_PHY_I2CM_OPERATION_ADDR);
++ hdmi_phy_wait_i2c_done(hdmi, 1000);
++}
++
++#if 0
++static unsigned short hdmi_phy_i2c_read(struct mxc_hdmi *hdmi,
++ unsigned char addr)
++{
++ unsigned short data;
++ unsigned char msb = 0, lsb = 0;
++ hdmi_writeb(0xFF, HDMI_IH_I2CMPHY_STAT0);
++ hdmi_writeb(addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
++ hdmi_writeb(HDMI_PHY_I2CM_OPERATION_ADDR_READ,
++ HDMI_PHY_I2CM_OPERATION_ADDR);
++ hdmi_phy_wait_i2c_done(hdmi, 1000);
++ msb = hdmi_readb(HDMI_PHY_I2CM_DATAI_1_ADDR);
++ lsb = hdmi_readb(HDMI_PHY_I2CM_DATAI_0_ADDR);
++ data = (msb << 8) | lsb;
++ return data;
++}
++
++static int hdmi_phy_i2c_write_verify(struct mxc_hdmi *hdmi, unsigned short data,
++ unsigned char addr)
++{
++ unsigned short val = 0;
++ hdmi_phy_i2c_write(hdmi, data, addr);
++ val = hdmi_phy_i2c_read(hdmi, addr);
++ return (val == data);
++}
++#endif
++
++static bool hdmi_edid_wait_i2c_done(struct mxc_hdmi *hdmi, int msec)
++{
++ unsigned char val = 0;
++ val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
++ while (val == 0) {
++
++ udelay(1000);
++ if (msec-- == 0) {
++ dev_dbg(&hdmi->pdev->dev,
++ "HDMI EDID i2c operation time out!!\n");
++ return false;
++ }
++ val = hdmi_readb(HDMI_IH_I2CM_STAT0) & 0x2;
++ }
++ return true;
++}
++
++static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi,
++ u8 addr, u8 blockno)
++{
++ u8 spointer = blockno / 2;
++ u8 edidaddress = ((blockno % 2) * 0x80) + addr;
++ u8 data;
++
++ hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
++ hdmi_writeb(edidaddress, HDMI_I2CM_ADDRESS);
++ hdmi_writeb(spointer, HDMI_I2CM_SEGADDR);
++ if (spointer == 0)
++ hdmi_writeb(HDMI_I2CM_OPERATION_READ,
++ HDMI_I2CM_OPERATION);
++ else
++ hdmi_writeb(HDMI_I2CM_OPERATION_READ_EXT,
++ HDMI_I2CM_OPERATION);
++
++ hdmi_edid_wait_i2c_done(hdmi, 30);
++ data = hdmi_readb(HDMI_I2CM_DATAI);
++ hdmi_writeb(0xFF, HDMI_IH_I2CM_STAT0);
++ return data;
++}
++
++
++/* "Power-down enable (active low)"
++ * That mean that power up == 1! */
++static void mxc_hdmi_phy_enable_power(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_PDZ_OFFSET,
++ HDMI_PHY_CONF0_PDZ_MASK);
++}
++
++static void mxc_hdmi_phy_enable_tmds(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET,
++ HDMI_PHY_CONF0_ENTMDS_MASK);
++}
++
++static void mxc_hdmi_phy_gen2_pddq(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
++}
++
++static void mxc_hdmi_phy_gen2_txpwron(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
++}
++
++#if 0
++static void mxc_hdmi_phy_gen2_enhpdrxsense(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK);
++}
++#endif
++
++static void mxc_hdmi_phy_sel_data_en_pol(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK);
++}
++
++static void mxc_hdmi_phy_sel_interface_control(u8 enable)
++{
++ hdmi_mask_writeb(enable, HDMI_PHY_CONF0,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET,
++ HDMI_PHY_CONF0_SELDIPIF_MASK);
++}
++
++static int hdmi_phy_configure(struct mxc_hdmi *hdmi, unsigned char pRep,
++ unsigned char cRes, int cscOn)
++{
++ u8 val;
++ u8 msec;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* color resolution 0 is 8 bit colour depth */
++ if (cRes == 0)
++ cRes = 8;
++
++ if (pRep != 0)
++ return false;
++ else if (cRes != 8 && cRes != 12)
++ return false;
++
++ /* Enable csc path */
++ if (cscOn)
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
++ else
++ val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
++
++ hdmi_writeb(val, HDMI_MC_FLOWCTRL);
++
++ /* gen2 tx power off */
++ mxc_hdmi_phy_gen2_txpwron(0);
++
++ /* gen2 pddq */
++ mxc_hdmi_phy_gen2_pddq(1);
++
++ /* PHY reset */
++ hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
++ hdmi_writeb(HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
++
++ hdmi_writeb(HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
++
++ hdmi_phy_test_clear(hdmi, 1);
++ hdmi_writeb(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
++ HDMI_PHY_I2CM_SLAVE_ADDR);
++ hdmi_phy_test_clear(hdmi, 0);
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock < 0) {
++ dev_dbg(&hdmi->pdev->dev, "Pixel clock (%d) must be positive\n",
++ hdmi->hdmi_data.video_mode.mPixelClock);
++ return false;
++ }
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock <= 45250000) {
++ switch (cRes) {
++ case 8:
++ /* PLL/MPLL Cfg */
++ hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); /* GMPCTRL */
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x21e1, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x41e2, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x15);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 92500000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x0140, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x2141, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x4142, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x15);
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 148500000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x20a1, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x40a2, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ default:
++ return false;
++ }
++ } else {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x00a0, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000a, 0x15);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x2001, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x4002, 0x06);
++ hdmi_phy_i2c_write(hdmi, 0x000f, 0x15);
++ default:
++ return false;
++ }
++ }
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock <= 54000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10); /* CURRCTRL */
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 58400000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 72000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 74250000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 118800000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else if (hdmi->hdmi_data.video_mode.mPixelClock <= 216000000) {
++ switch (cRes) {
++ case 8:
++ hdmi_phy_i2c_write(hdmi, 0x06dc, 0x10);
++ break;
++ case 10:
++ hdmi_phy_i2c_write(hdmi, 0x0b5c, 0x10);
++ break;
++ case 12:
++ hdmi_phy_i2c_write(hdmi, 0x091c, 0x10);
++ break;
++ default:
++ return false;
++ }
++ } else {
++ dev_err(&hdmi->pdev->dev,
++ "Pixel clock %d - unsupported by HDMI\n",
++ hdmi->hdmi_data.video_mode.mPixelClock);
++ return false;
++ }
++
++ hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
++ hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
++ /* RESISTANCE TERM 133Ohm Cfg */
++ hdmi_phy_i2c_write(hdmi, 0x0005, 0x19); /* TXTERM */
++ /* PREEMP Cgf 0.00 */
++ hdmi_phy_i2c_write(hdmi, 0x800d, 0x09); /* CKSYMTXCTRL */
++ /* TX/CK LVL 10 */
++ hdmi_phy_i2c_write(hdmi, 0x01ad, 0x0E); /* VLEVCTRL */
++
++ /* Board specific setting for PHY register 0x09, 0x0e to pass HCT */
++ if (hdmi->phy_config.reg_cksymtx != 0)
++ hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_cksymtx, 0x09);
++
++ if (hdmi->phy_config.reg_vlev != 0)
++ hdmi_phy_i2c_write(hdmi, hdmi->phy_config.reg_vlev, 0x0E);
++
++ /* REMOVE CLK TERM */
++ hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
++
++ if (hdmi->hdmi_data.video_mode.mPixelClock > 148500000) {
++ hdmi_phy_i2c_write(hdmi, 0x800b, 0x09);
++ hdmi_phy_i2c_write(hdmi, 0x0129, 0x0E);
++ }
++
++ mxc_hdmi_phy_enable_power(1);
++
++ /* toggle TMDS enable */
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_tmds(1);
++
++ /* gen2 tx power on */
++ mxc_hdmi_phy_gen2_txpwron(1);
++ mxc_hdmi_phy_gen2_pddq(0);
++
++ /*Wait for PHY PLL lock */
++ msec = 4;
++ val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
++ while (val == 0) {
++ udelay(1000);
++ if (msec-- == 0) {
++ dev_dbg(&hdmi->pdev->dev, "PHY PLL not locked\n");
++ return false;
++ }
++ val = hdmi_readb(HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
++ }
++
++ return true;
++}
++
++static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi)
++{
++ int i;
++ bool cscon = false;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Never do phy init if pixel clock is gated.
++ * Otherwise HDMI PHY will get messed up and generate an overflow
++ * interrupt that can't be cleared or detected by accessing the
++ * status register. */
++ if (!hdmi->fb_reg ||
++ hdmi->hp_state == HDMI_HOTPLUG_DISCONNECTED ||
++ hdmi->blank != FB_BLANK_UNBLANK)
++ return;
++
++ /*check csc whether needed activated in HDMI mode */
++ cscon = (isColorSpaceConversion(hdmi) &&
++ (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_HDMI));
++
++ /* HDMI Phy spec says to do the phy initialization sequence twice */
++ for (i = 0 ; i < 2 ; i++) {
++ mxc_hdmi_phy_sel_data_en_pol(1);
++ mxc_hdmi_phy_sel_interface_control(0);
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_power(0);
++
++ /* Enable CSC */
++ hdmi_phy_configure(hdmi, 0, 8, cscon);
++ }
++
++ hdmi->phy_enabled = true;
++ if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_HDMI)
++ hdmi_enable_overflow_interrupts();
++}
++
++static void hdmi_config_AVI(struct mxc_hdmi *hdmi)
++{
++ u8 val;
++ u8 pix_fmt;
++ u8 under_scan;
++ u8 act_ratio, coded_ratio, colorimetry, ext_colorimetry;
++ struct fb_videomode mode;
++ const struct fb_videomode *edid_mode;
++ bool aspect_16_9;
++
++ dev_dbg(&hdmi->pdev->dev, "set up AVI frame\n");
++
++ fb_var_to_videomode(&mode, &hdmi->fbi->var);
++ /* Use mode from list extracted from EDID to get aspect ratio */
++ if (!list_empty(&hdmi->fbi->modelist)) {
++ edid_mode = fb_find_nearest_mode(&mode, &hdmi->fbi->modelist);
++ if (edid_mode->vmode & FB_VMODE_ASPECT_16_9)
++ aspect_16_9 = true;
++ else
++ aspect_16_9 = false;
++ } else
++ aspect_16_9 = false;
++
++ /********************************************
++ * AVI Data Byte 1
++ ********************************************/
++ if (hdmi->hdmi_data.enc_out_format == YCBCR444)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR444;
++ else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_YCBCR422;
++ else
++ pix_fmt = HDMI_FC_AVICONF0_PIX_FMT_RGB;
++
++ if (hdmi->edid_cfg.cea_underscan)
++ under_scan = HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN;
++ else
++ under_scan = HDMI_FC_AVICONF0_SCAN_INFO_NODATA;
++
++ /*
++ * Active format identification data is present in the AVI InfoFrame.
++ * Under scan info, no bar data
++ */
++ val = pix_fmt | under_scan |
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT |
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA;
++
++ hdmi_writeb(val, HDMI_FC_AVICONF0);
++
++ /********************************************
++ * AVI Data Byte 2
++ ********************************************/
++
++ /* Set the Aspect Ratio */
++ if (aspect_16_9) {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9;
++ } else {
++ act_ratio = HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3;
++ coded_ratio = HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3;
++ }
++
++ /* Set up colorimetry */
++ if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO;
++ if (hdmi->hdmi_data.colorimetry == eITU601)
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ else /* hdmi->hdmi_data.colorimetry == eITU709 */
++ ext_colorimetry =
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709;
++ } else if (hdmi->hdmi_data.enc_out_format != RGB) {
++ if (hdmi->hdmi_data.colorimetry == eITU601)
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_SMPTE;
++ else /* hdmi->hdmi_data.colorimetry == eITU709 */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_ITUR;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ } else { /* Carries no data */
++ colorimetry = HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA;
++ ext_colorimetry = HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601;
++ }
++
++ val = colorimetry | coded_ratio | act_ratio;
++ hdmi_writeb(val, HDMI_FC_AVICONF1);
++
++ /********************************************
++ * AVI Data Byte 3
++ ********************************************/
++
++ val = HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA | ext_colorimetry |
++ getRGBQuantRange(hdmi) | HDMI_FC_AVICONF2_SCALING_NONE;
++ hdmi_writeb(val, HDMI_FC_AVICONF2);
++
++ /********************************************
++ * AVI Data Byte 4
++ ********************************************/
++ hdmi_writeb(hdmi->vic, HDMI_FC_AVIVID);
++
++ /********************************************
++ * AVI Data Byte 5
++ ********************************************/
++
++ /* Set up input and output pixel repetition */
++ val = (((hdmi->hdmi_data.video_mode.mPixelRepetitionInput + 1) <<
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
++ ((hdmi->hdmi_data.video_mode.mPixelRepetitionOutput <<
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
++ hdmi_writeb(val, HDMI_FC_PRCONF);
++
++ /* IT Content and quantization range = don't care */
++ val = HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS |
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED;
++ hdmi_writeb(val, HDMI_FC_AVICONF3);
++
++ /********************************************
++ * AVI Data Bytes 6-13
++ ********************************************/
++ hdmi_writeb(0, HDMI_FC_AVIETB0);
++ hdmi_writeb(0, HDMI_FC_AVIETB1);
++ hdmi_writeb(0, HDMI_FC_AVISBB0);
++ hdmi_writeb(0, HDMI_FC_AVISBB1);
++ hdmi_writeb(0, HDMI_FC_AVIELB0);
++ hdmi_writeb(0, HDMI_FC_AVIELB1);
++ hdmi_writeb(0, HDMI_FC_AVISRB0);
++ hdmi_writeb(0, HDMI_FC_AVISRB1);
++}
++
++/*!
++ * this submodule is responsible for the video/audio data composition.
++ */
++static void hdmi_av_composer(struct mxc_hdmi *hdmi)
++{
++ u8 inv_val;
++ struct fb_info *fbi = hdmi->fbi;
++ struct fb_videomode fb_mode;
++ struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
++ int hblank, vblank;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_var_to_videomode(&fb_mode, &fbi->var);
++
++ vmode->mHSyncPolarity = ((fb_mode.sync & FB_SYNC_HOR_HIGH_ACT) != 0);
++ vmode->mVSyncPolarity = ((fb_mode.sync & FB_SYNC_VERT_HIGH_ACT) != 0);
++ vmode->mInterlaced = ((fb_mode.vmode & FB_VMODE_INTERLACED) != 0);
++ vmode->mPixelClock = (u32) (mxcPICOS2KHZ(fb_mode.pixclock, fb_mode.vmode) * 1000UL);
++
++ dev_dbg(&hdmi->pdev->dev, "final pixclk = %d\n", vmode->mPixelClock);
++
++ /* Set up HDMI_FC_INVIDCONF */
++ inv_val = (vmode->mVSyncPolarity ?
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mHSyncPolarity ?
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
++
++ inv_val |= (vmode->mDataEnablePolarity ?
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
++
++ if (hdmi->vic == 39)
++ inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
++ else
++ inv_val |= (vmode->mInterlaced ?
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
++
++ inv_val |= (vmode->mInterlaced ?
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
++
++ inv_val |= ((hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_DVI) ?
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
++
++ hdmi_writeb(inv_val, HDMI_FC_INVIDCONF);
++
++ /* Set up horizontal active pixel region width */
++ hdmi_writeb(fb_mode.xres >> 8, HDMI_FC_INHACTV1);
++ hdmi_writeb(fb_mode.xres, HDMI_FC_INHACTV0);
++
++ /* Set up vertical blanking pixel region width */
++ if (vmode->mInterlaced) {
++ hdmi_writeb((fb_mode.yres/2) >> 8, HDMI_FC_INVACTV1);
++ hdmi_writeb((fb_mode.yres/2), HDMI_FC_INVACTV0);
++ } else {
++ hdmi_writeb(fb_mode.yres >> 8, HDMI_FC_INVACTV1);
++ hdmi_writeb(fb_mode.yres, HDMI_FC_INVACTV0);
++ }
++
++ /* Set up horizontal blanking pixel region width */
++ hblank = fb_mode.left_margin + fb_mode.right_margin +
++ fb_mode.hsync_len;
++ hdmi_writeb(hblank >> 8, HDMI_FC_INHBLANK1);
++ hdmi_writeb(hblank, HDMI_FC_INHBLANK0);
++
++ /* Set up vertical blanking pixel region width */
++ vblank = fb_mode.upper_margin + fb_mode.lower_margin +
++ fb_mode.vsync_len;
++ if (vmode->mInterlaced)
++ hdmi_writeb(vblank/2, HDMI_FC_INVBLANK);
++ else
++ hdmi_writeb(vblank, HDMI_FC_INVBLANK);
++
++ /* Set up HSYNC active edge delay width (in pixel clks) */
++ hdmi_writeb(fb_mode.right_margin >> 8, HDMI_FC_HSYNCINDELAY1);
++ hdmi_writeb(fb_mode.right_margin, HDMI_FC_HSYNCINDELAY0);
++
++ /* Set up VSYNC active edge delay (in pixel clks) */
++ if (vmode->mInterlaced)
++ hdmi_writeb(fb_mode.lower_margin / 2, HDMI_FC_VSYNCINDELAY);
++ else
++ hdmi_writeb(fb_mode.lower_margin, HDMI_FC_VSYNCINDELAY);
++
++ /* Set up HSYNC active pulse width (in pixel clks) */
++ hdmi_writeb(fb_mode.hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
++ hdmi_writeb(fb_mode.hsync_len, HDMI_FC_HSYNCINWIDTH0);
++
++ /* Set up VSYNC active edge delay (in pixel clks) */
++ if (vmode->mInterlaced)
++ hdmi_writeb(fb_mode.vsync_len / 2, HDMI_FC_VSYNCINWIDTH);
++ else
++ hdmi_writeb(fb_mode.vsync_len, HDMI_FC_VSYNCINWIDTH);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static int mxc_edid_read_internal(struct mxc_hdmi *hdmi, unsigned char *edid,
++ struct mxc_edid_cfg *cfg, struct fb_info *fbi)
++{
++ int extblknum;
++ int i, ret;
++ unsigned char *ediddata = edid;
++ unsigned char tmpedid[EDID_LENGTH];
++
++ dev_info(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (!edid || !cfg || !fbi)
++ return -EINVAL;
++
++ /* init HDMI I2CM for read edid*/
++ hdmi_writeb(0x0, HDMI_I2CM_DIV);
++ hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
++ hdmi_writeb(0x79, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
++ hdmi_writeb(0x00, HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
++ hdmi_writeb(0x91, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
++
++ hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_HCNT_1_ADDR);
++ hdmi_writeb(0x0F, HDMI_I2CM_FS_SCL_HCNT_0_ADDR);
++ hdmi_writeb(0x00, HDMI_I2CM_FS_SCL_LCNT_1_ADDR);
++ hdmi_writeb(0x21, HDMI_I2CM_FS_SCL_LCNT_0_ADDR);
++
++ hdmi_writeb(0x50, HDMI_I2CM_SLAVE);
++ hdmi_writeb(0x30, HDMI_I2CM_SEGADDR);
++
++ /* Umask edid interrupt */
++ hdmi_writeb(HDMI_I2CM_INT_DONE_POL,
++ HDMI_I2CM_INT);
++
++ hdmi_writeb(HDMI_I2CM_CTLINT_NAC_POL |
++ HDMI_I2CM_CTLINT_ARBITRATION_POL,
++ HDMI_I2CM_CTLINT);
++
++ /* reset edid data zero */
++ memset(edid, 0, EDID_LENGTH*4);
++ memset(cfg, 0, sizeof(struct mxc_edid_cfg));
++
++ /* Check first three byte of EDID head */
++ if (!(hdmi_edid_i2c_read(hdmi, 0, 0) == 0x00) ||
++ !(hdmi_edid_i2c_read(hdmi, 1, 0) == 0xFF) ||
++ !(hdmi_edid_i2c_read(hdmi, 2, 0) == 0xFF)) {
++ dev_info(&hdmi->pdev->dev, "EDID head check failed!");
++ return -ENOENT;
++ }
++
++ for (i = 0; i < 128; i++) {
++ *ediddata = hdmi_edid_i2c_read(hdmi, i, 0);
++ ediddata++;
++ }
++
++ extblknum = edid[0x7E];
++
++ if (extblknum < 0) {
++ return extblknum;
++ } else {
++ ediddata = edid + EDID_LENGTH;
++ for (i = 0; i < 128; i++) {
++ *ediddata = hdmi_edid_i2c_read(hdmi, i, 1);
++ ediddata++;
++ }
++ }
++
++ /* edid first block parsing */
++ memset(&fbi->monspecs, 0, sizeof(fbi->monspecs));
++ fb_edid_to_monspecs(edid, &fbi->monspecs);
++
++ ret = mxc_edid_parse_ext_blk(edid + EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ if (ret < 0) {
++ fb_edid_add_monspecs(edid + EDID_LENGTH, &fbi->monspecs);
++ if (fbi->monspecs.modedb_len > 0)
++ hdmi->edid_cfg.hdmi_cap = false;
++ else
++ return -ENOENT;
++ }
++
++ /* need read segment block? */
++ if (extblknum > 1) {
++ int j;
++ for (j = 1; j <= extblknum; j++) {
++ for (i = 0; i < 128; i++)
++ *(tmpedid + 1) = hdmi_edid_i2c_read(hdmi, i, j);
++
++ /* edid ext block parsing */
++ ret = mxc_edid_parse_ext_blk(tmpedid + EDID_LENGTH,
++ cfg, &fbi->monspecs);
++ if (ret < 0)
++ return -ENOENT;
++ }
++ }
++
++ return 0;
++}
++
++static int mxc_hdmi_read_edid(struct mxc_hdmi *hdmi)
++{
++ int ret;
++ u8 edid_old[HDMI_EDID_LEN];
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* save old edid */
++ memcpy(edid_old, hdmi->edid, HDMI_EDID_LEN);
++
++ /* Read EDID via HDMI DDC when HDCP Enable */
++ if (!hdcp_init)
++ ret = mxc_edid_read(hdmi_i2c->adapter, hdmi_i2c->addr,
++ hdmi->edid, &hdmi->edid_cfg, hdmi->fbi);
++ else {
++
++ /* Disable HDCP clk */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++
++ ret = mxc_edid_read_internal(hdmi, hdmi->edid,
++ &hdmi->edid_cfg, hdmi->fbi);
++
++ /* Enable HDCP clk */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis &= ~HDMI_MC_CLKDIS_HDCPCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++
++ }
++
++ if (ret < 0)
++ return HDMI_EDID_FAIL;
++
++ if (memcmp(edid_old, hdmi->edid, HDMI_EDID_LEN) == 0) {
++ dev_info(&hdmi->pdev->dev, "same edid\n");
++ return HDMI_EDID_SAME;
++ }
++
++ if (hdmi->fbi->monspecs.modedb_len == 0) {
++ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
++ return HDMI_EDID_NO_MODES;
++ }
++
++ return HDMI_EDID_SUCCESS;
++}
++
++static void mxc_hdmi_phy_disable(struct mxc_hdmi *hdmi)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ if (!hdmi->phy_enabled)
++ return;
++
++ hdmi_disable_overflow_interrupts();
++
++ /* Setting PHY to reset status */
++ hdmi_writeb(HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
++
++ /* Power down PHY */
++ mxc_hdmi_phy_enable_tmds(0);
++ mxc_hdmi_phy_enable_power(0);
++ mxc_hdmi_phy_gen2_txpwron(0);
++ mxc_hdmi_phy_gen2_pddq(1);
++
++ hdmi->phy_enabled = false;
++ dev_dbg(&hdmi->pdev->dev, "%s - exit\n", __func__);
++}
++
++/* HDMI Initialization Step B.4 */
++static void mxc_hdmi_enable_video_path(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* control period minimum duration */
++ hdmi_writeb(12, HDMI_FC_CTRLDUR);
++ hdmi_writeb(32, HDMI_FC_EXCTRLDUR);
++ hdmi_writeb(1, HDMI_FC_EXCTRLSPAC);
++
++ /* Set to fill TMDS data channels */
++ hdmi_writeb(0x0B, HDMI_FC_CH0PREAM);
++ hdmi_writeb(0x16, HDMI_FC_CH1PREAM);
++ hdmi_writeb(0x21, HDMI_FC_CH2PREAM);
++
++ /* Save CEC clock */
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ clkdis |= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++
++ /* Enable pixel clock and tmds data path */
++ clkdis = 0x7F & clkdis;
++ clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++
++ clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++
++ /* Enable csc path */
++ if (isColorSpaceConversion(hdmi) &&
++ (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_HDMI)) {
++ clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++ }
++}
++
++static void hdmi_enable_audio_clk(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS);
++ clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
++ hdmi_writeb(clkdis, HDMI_MC_CLKDIS);
++}
++
++/* Workaround to clear the overflow condition */
++static void mxc_hdmi_clear_overflow(struct mxc_hdmi *hdmi)
++{
++ int count;
++ u8 val;
++
++ /* TMDS software reset */
++ hdmi_writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
++
++ val = hdmi_readb(HDMI_FC_INVIDCONF);
++
++ if (cpu_is_imx6dl(hdmi)) {
++ hdmi_writeb(val, HDMI_FC_INVIDCONF);
++ return;
++ }
++
++ for (count = 0 ; count < 5 ; count++)
++ hdmi_writeb(val, HDMI_FC_INVIDCONF);
++}
++
++static void hdmi_enable_overflow_interrupts(void)
++{
++ pr_debug("%s\n", __func__);
++ hdmi_writeb(0, HDMI_FC_MASK2);
++ hdmi_writeb(0, HDMI_IH_MUTE_FC_STAT2);
++}
++
++static void hdmi_disable_overflow_interrupts(void)
++{
++ pr_debug("%s\n", __func__);
++ hdmi_writeb(HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
++ HDMI_IH_MUTE_FC_STAT2);
++ hdmi_writeb(0xff, HDMI_FC_MASK2);
++}
++
++static void mxc_hdmi_notify_fb(struct mxc_hdmi *hdmi, bool force_all)
++{
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Don't notify if we aren't registered yet */
++ WARN_ON(!hdmi->fb_reg);
++
++ /* disable the phy before ipu changes mode */
++ mxc_hdmi_phy_disable(hdmi);
++
++ /*
++ * Note that fb_set_var will block. During this time,
++ * FB_EVENT_MODE_CHANGE callback will happen.
++ * So by the end of this function, mxc_hdmi_setup()
++ * will be done.
++ */
++ hdmi->fbi->var.activate |= FB_ACTIVATE_FORCE;
++
++ /* If new screen was attached and resolutions
++ * reconfigured to best fit it, force reconf all consoles
++ */
++ if (force_all)
++ hdmi->fbi->var.activate |= FB_ACTIVATE_ALL;
++
++ console_lock();
++ hdmi->fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_set_var(hdmi->fbi, &hdmi->fbi->var);
++ hdmi->fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
++{
++ int i, vic;
++ struct fb_videomode *mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++ fb_add_videomode(&vga_mode, &hdmi->fbi->modelist);
++
++ for (i = 0; i < hdmi->fbi->monspecs.modedb_len; i++) {
++ /*
++ * We might check here if mode is supported by HDMI.
++ * We do not currently support interlaced modes.
++ * And add CEA modes in the modelist.
++ */
++ mode = &hdmi->fbi->monspecs.modedb[i];
++
++ vic = mxc_edid_mode_to_vic(mode);
++ if (hdmi->edid_cfg.hdmi_cap &&
++ (vic == 0))
++ continue;
++
++ if (!(mode->vmode & FB_VMODE_ASPECT_MASK)) {
++ if (mode->yres == (mode->xres * 3)/4)
++ mode->vmode |= FB_VMODE_ASPECT_4_3;
++ else
++ mode->vmode |= FB_VMODE_ASPECT_16_9;
++ }
++
++ if (fb_add_videomode(mode, &hdmi->fbi->modelist))
++ continue;
++
++ dev_dbg(&hdmi->pdev->dev, "Added mode: %d, vic: %d", i, vic);
++ dev_dbg(&hdmi->pdev->dev,
++ "xres = %d, yres = %d, ratio = %s, freq = %d, vmode = %d, flag = %d\n",
++ hdmi->fbi->monspecs.modedb[i].xres,
++ hdmi->fbi->monspecs.modedb[i].yres,
++ mode->vmode & FB_VMODE_ASPECT_4_3 ? "4/3" :
++ mode->vmode & FB_VMODE_ASPECT_16_9 ? "16/9" : "n/a",
++ hdmi->fbi->monspecs.modedb[i].refresh,
++ hdmi->fbi->monspecs.modedb[i].vmode,
++ hdmi->fbi->monspecs.modedb[i].flag);
++ }
++
++ fb_new_modelist(hdmi->fbi);
++
++ console_unlock();
++}
++
++static void mxc_hdmi_default_edid_cfg(struct mxc_hdmi *hdmi)
++{
++ /* Default setting HDMI working in HDMI mode */
++ hdmi->edid_cfg.hdmi_cap = true;
++}
++
++static void mxc_hdmi_default_modelist(struct mxc_hdmi *hdmi)
++{
++ u32 i;
++ struct fb_videomode mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* If not EDID data read, set up default modelist */
++ dev_info(&hdmi->pdev->dev, "No modes read from edid\n");
++ dev_info(&hdmi->pdev->dev, "create default modelist\n");
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++
++ /*Add all no interlaced CEA mode to default modelist */
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ mode = mxc_cea_mode[i];
++ if (mode.xres != 0) {
++ if (ignore_edid)
++ mode.flag |= FB_MODE_IS_STANDARD;
++ fb_add_videomode(&mode, &hdmi->fbi->modelist);
++ }
++ }
++
++ fb_new_modelist(hdmi->fbi);
++
++ console_unlock();
++}
++
++static void mxc_hdmi_set_mode(struct mxc_hdmi *hdmi, int edid_status)
++{
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++ struct fb_var_screeninfo var;
++ bool new_screen = false;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Set the default mode only once. */
++ if (!hdmi->dft_mode_set) {
++ fb_videomode_to_var(&var, &hdmi->default_mode);
++ hdmi->dft_mode_set = true;
++ } else {
++ fb_videomode_to_var(&var, &hdmi->previous_non_vga_mode);
++ }
++
++ /* check for active xBuffer, look for similar (x/y/hz/vmode) mode
++ * otherwise be nice looking for best (new) display mode */
++ if (edid_status == HDMI_EDID_SUCCESS && !hdmi->prev_virtual.xres_virtual) {
++ dev_dbg(&hdmi->pdev->dev,
++ "xBuffer not active, trying new best display mode\n");
++ if ((mode = fb_find_best_display(&hdmi->fbi->monspecs, &hdmi->fbi->modelist)))
++ fb_videomode_to_var(&var, mode);
++ }
++
++ fb_var_to_videomode(&m, &var);
++ dump_fb_videomode(&m);
++ mode = mxc_fb_find_nearest_mode(&m, &hdmi->fbi->modelist, false);
++
++ if (mode) {
++ hdmi->fbi->mode = (struct fb_videomode *)mode;
++ fb_videomode_to_var(&hdmi->fbi->var, mode);
++ } else {
++ pr_err("%s: could not find mode in modelist\n", __func__);
++ return;
++ }
++
++ /* restore xBuffer if dimension match */
++ if ((edid_status == HDMI_EDID_SAME && fb_mode_is_equal(&hdmi->previous_non_vga_mode, mode)) ||
++ (edid_status != HDMI_EDID_SAME && mxc_fb_mode_is_equal_res(&hdmi->previous_non_vga_mode, mode))) {
++ dev_dbg(&hdmi->pdev->dev,
++ "%s: Video mode %ssame as previous\n", __func__, edid_status == HDMI_EDID_SAME ? "+ EDID " : "");
++ if (hdmi->prev_virtual.xres_virtual)
++ memcpy(&hdmi->fbi->var.xres_virtual, &hdmi->prev_virtual, sizeof(hdmi->prev_virtual));
++ } else {
++ dev_dbg(&hdmi->pdev->dev, "%s: New video mode\n", __func__);
++ new_screen = true;
++ }
++
++ hdmi_set_cable_state(1);
++
++ /* apply previously set hdmi->fbi->var */
++ console_lock();
++ fb_blank(hdmi->fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++
++ if (edid_status != HDMI_EDID_SAME)
++ mxc_hdmi_notify_fb(hdmi, new_screen);
++}
++
++static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
++{
++ int edid_status;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ hdmi->hp_state = HDMI_HOTPLUG_CONNECTED_NO_EDID;
++
++ /* HDMI Initialization Step C */
++ if (ignore_edid) {
++ edid_status = HDMI_EDID_FAIL;
++ } else {
++ edid_status = mxc_hdmi_read_edid(hdmi);
++
++ /* Read EDID again if first EDID read failed */
++ if (edid_status == HDMI_EDID_NO_MODES ||
++ edid_status == HDMI_EDID_FAIL) {
++ int retry_status;
++ dev_warn(&hdmi->pdev->dev, "Read EDID again\n");
++ msleep(200);
++ retry_status = mxc_hdmi_read_edid(hdmi);
++ /* If we get NO_MODES on the 1st and SAME on the 2nd attempt we
++ * want NO_MODES as final result. */
++ if (retry_status != HDMI_EDID_SAME)
++ edid_status = retry_status;
++ }
++ }
++
++ /* HDMI Initialization Steps D, E, F */
++ switch (edid_status) {
++ case HDMI_EDID_SUCCESS:
++ mxc_hdmi_edid_rebuild_modelist(hdmi);
++ break;
++
++ /* Nothing to do if EDID same */
++ case HDMI_EDID_SAME:
++ break;
++
++ case HDMI_EDID_FAIL:
++ mxc_hdmi_default_edid_cfg(hdmi);
++ /* No break here */
++ case HDMI_EDID_NO_MODES:
++ default:
++ mxc_hdmi_default_modelist(hdmi);
++ break;
++ }
++
++ dev_info(&hdmi->pdev->dev, "%s reports %s mode\n", __func__, hdmi->edid_cfg.hdmi_cap ? "HDMI" : "DVI");
++ hdmi->hp_state = hdmi->edid_cfg.hdmi_cap ? HDMI_HOTPLUG_CONNECTED_HDMI : HDMI_HOTPLUG_CONNECTED_DVI;
++ hdmi->plug_event = hdmi->edid_cfg.hdmi_cap ? HDMI_IH_PHY_STAT0_HPD : HDMI_DVI_IH_STAT;
++ hdmi->plug_mask = hdmi->edid_cfg.hdmi_cap ? HDMI_PHY_HPD : HDMI_DVI_STAT;
++
++ /* Save edid cfg for audio driver */
++ hdmi_set_edid_cfg(edid_status, &hdmi->edid_cfg);
++
++ /* Setting video mode */
++ mxc_hdmi_set_mode(hdmi, edid_status);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++}
++
++static int mxc_hdmi_power_on(struct mxc_dispdrv_handle *disp,
++ struct fb_info *fbi)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++ mxc_hdmi_phy_init(hdmi);
++ hdmi_clk_regenerator_update_pixel_clock(fbi->var.pixclock, fbi->var.vmode);
++ return 0;
++}
++
++static void mxc_hdmi_power_off(struct mxc_dispdrv_handle *disp,
++ struct fb_info *fbi)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++ mxc_hdmi_phy_disable(hdmi);
++}
++
++static void mxc_hdmi_cable_disconnected(struct mxc_hdmi *hdmi)
++{
++ u8 clkdis;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Save CEC clock */
++ clkdis = hdmi_readb(HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;
++ clkdis |= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
++
++ /* Disable All HDMI clock */
++ hdmi_writeb(0xff & clkdis, HDMI_MC_CLKDIS);
++
++ mxc_hdmi_phy_disable(hdmi);
++
++ hdmi_disable_overflow_interrupts();
++
++ hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
++
++ console_lock();
++ fb_blank(hdmi->fbi, FB_BLANK_POWERDOWN);
++ console_unlock();
++}
++
++static void hotplug_worker(struct work_struct *work)
++{
++ struct mxc_hdmi *hdmi =
++ container_of(work, struct mxc_hdmi, hotplug_work);
++ u32 hdmi_phy_stat0, hdmi_phy_pol0, hdmi_phy_mask0;
++ unsigned long flags;
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++
++ hdmi_phy_stat0 = hdmi_readb(HDMI_PHY_STAT0);
++ hdmi_phy_pol0 = hdmi_readb(HDMI_PHY_POL0);
++
++ if (hdmi->latest_intr_stat & hdmi->plug_event) {
++ /* Make HPD intr active low to capture unplug event or
++ * active high to capture plugin event */
++ hdmi_writeb((hdmi->plug_mask & ~hdmi_phy_pol0), HDMI_PHY_POL0);
++
++ /* check cable status */
++ if (hdmi_phy_stat0 & hdmi->plug_mask) {
++ /* Plugin event */
++ dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
++ mxc_hdmi_cable_connected(hdmi);
++
++ sprintf(event_string, "EVENT=plugin");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++#ifdef CONFIG_MXC_HDMI_CEC
++ mxc_hdmi_cec_handle(0x80);
++#endif
++ } else {
++ /* Plugout event */
++ dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
++ hdmi_set_cable_state(0);
++ mxc_hdmi_abort_stream();
++ mxc_hdmi_cable_disconnected(hdmi);
++
++ sprintf(event_string, "EVENT=plugout");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++#ifdef CONFIG_MXC_HDMI_CEC
++ mxc_hdmi_cec_handle(0x100);
++#endif
++ }
++ }
++
++ /* Lock here to ensure full powerdown sequence
++ * completed before next interrupt processed */
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ /* Re-enable HPD interrupts */
++ hdmi_phy_mask0 = hdmi_readb(HDMI_PHY_MASK0);
++ hdmi_phy_mask0 &= ~hdmi->plug_mask;
++ hdmi_writeb(hdmi_phy_mask0, HDMI_PHY_MASK0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~hdmi->plug_event, HDMI_IH_MUTE_PHY_STAT0);
++
++ if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
++ mxc_hdmi_clear_overflow(hdmi);
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++}
++
++static void hotplug_work_launch(unsigned long data)
++{
++ struct mxc_hdmi *hdmi = (struct mxc_hdmi *)data;
++ pr_debug("%s\n", __func__);
++ schedule_work(&hdmi->hotplug_work);
++}
++
++static void hdcp_hdp_worker(struct work_struct *work)
++{
++ struct delayed_work *delay_work = to_delayed_work(work);
++ struct mxc_hdmi *hdmi =
++ container_of(delay_work, struct mxc_hdmi, hdcp_hdp_work);
++ char event_string[32];
++ char *envp[] = { event_string, NULL };
++
++ /* HDCP interrupt */
++ sprintf(event_string, "EVENT=hdcpint");
++ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
++
++ /* Unmute interrupts in HDCP application*/
++}
++
++static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
++{
++ struct mxc_hdmi *hdmi = data;
++ u8 val, intr_stat;
++ unsigned long flags;
++
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ /* Check and clean packet overflow interrupt.*/
++ if (hdmi_readb(HDMI_IH_FC_STAT2) &
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK) {
++ mxc_hdmi_clear_overflow(hdmi);
++
++ dev_dbg(&hdmi->pdev->dev, "Overflow interrupt received\n");
++ /* clear irq status */
++ hdmi_writeb(HDMI_IH_FC_STAT2_OVERFLOW_MASK,
++ HDMI_IH_FC_STAT2);
++ }
++
++ /*
++ * We could not disable the irq. Probably the audio driver
++ * has enabled it. Masking off the HDMI interrupts using
++ * HDMI registers.
++ */
++ /* Capture status - used in hotplug_worker ISR */
++ intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
++ if (intr_stat & hdmi->plug_event) {
++
++ dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
++ dev_dbg(&hdmi->pdev->dev, "intr_stat 0x%x plug_event 0x%x\n", intr_stat, hdmi->plug_event);
++ hdmi->latest_intr_stat = intr_stat;
++
++ /* Mute interrupts until handled */
++
++ val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
++ val |= hdmi->plug_event;
++ hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
++
++ val = hdmi_readb(HDMI_PHY_MASK0);
++ val |= hdmi->plug_mask;
++ hdmi_writeb(val, HDMI_PHY_MASK0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi->plug_event, HDMI_IH_PHY_STAT0);
++
++ if(hdmi_inited) {
++ mod_timer(&hdmi->jitter_timer, jiffies + HZ);
++ }
++ }
++
++ /* Check HDCP interrupt state */
++ if (hdmi->hdmi_data.hdcp_enable) {
++ val = hdmi_readb(HDMI_A_APIINTSTAT);
++ if (val != 0) {
++ /* Mute interrupts until interrupt handled */
++ val = 0xFF;
++ hdmi_writeb(val, HDMI_A_APIINTMSK);
++ schedule_delayed_work(&(hdmi->hdcp_hdp_work), msecs_to_jiffies(50));
++ }
++ }
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++ return IRQ_HANDLED;
++}
++
++static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event)
++{
++ struct fb_videomode m;
++ const struct fb_videomode *edid_mode;
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_var_to_videomode(&m, &hdmi->fbi->var);
++ dump_fb_videomode(&m);
++
++ dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__);
++
++ hdmi->vic = 0;
++ {
++ /* Save mode if this isn't the result of requesting
++ * vga default. */
++ memcpy(&hdmi->previous_non_vga_mode, &m,
++ sizeof(struct fb_videomode));
++ /* Save any double/tripple buffer configuration (if active) */
++ if (hdmi->fbi->var.yres_virtual != hdmi->fbi->var.yres)
++ memcpy(&hdmi->prev_virtual, &hdmi->fbi->var.xres_virtual, sizeof(hdmi->prev_virtual));
++ else
++ memset(&hdmi->prev_virtual, 0, sizeof(hdmi->prev_virtual));
++ if (!list_empty(&hdmi->fbi->modelist)) {
++ edid_mode = mxc_fb_find_nearest_mode(&m, &hdmi->fbi->modelist, false);
++ pr_debug("edid mode ");
++ /* update fbi mode */
++ hdmi->fbi->mode = (struct fb_videomode *)edid_mode;
++ hdmi->vic = mxc_edid_mode_to_vic(edid_mode);
++ }
++ }
++
++ if (hdmi->blank != FB_BLANK_UNBLANK)
++ return;
++
++ hdmi_disable_overflow_interrupts();
++
++ if ((hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_HDMI) ||
++ (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_NO_EDID)) {
++ dev_dbg(&hdmi->pdev->dev, "CEA mode used vic=%d\n", hdmi->vic);
++ hdmi_set_dvi_mode(0);
++ } else {
++ dev_dbg(&hdmi->pdev->dev, "VESA mode used vic=%d\n", hdmi->vic);
++ hdmi_set_dvi_mode(1);
++ }
++
++ if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
++ (hdmi->vic == 21) || (hdmi->vic == 22) ||
++ (hdmi->vic == 2) || (hdmi->vic == 3) ||
++ (hdmi->vic == 17) || (hdmi->vic == 18))
++ hdmi->hdmi_data.colorimetry = eITU601;
++ else
++ hdmi->hdmi_data.colorimetry = eITU709;
++
++ if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
++ (hdmi->vic == 12) || (hdmi->vic == 13) ||
++ (hdmi->vic == 14) || (hdmi->vic == 15) ||
++ (hdmi->vic == 25) || (hdmi->vic == 26) ||
++ (hdmi->vic == 27) || (hdmi->vic == 28) ||
++ (hdmi->vic == 29) || (hdmi->vic == 30) ||
++ (hdmi->vic == 35) || (hdmi->vic == 36) ||
++ (hdmi->vic == 37) || (hdmi->vic == 38))
++ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 1;
++ else
++ hdmi->hdmi_data.video_mode.mPixelRepetitionOutput = 0;
++
++ hdmi->hdmi_data.video_mode.mPixelRepetitionInput = 0;
++
++ /* TODO: Get input format from IPU (via FB driver iface) */
++ hdmi->hdmi_data.enc_in_format = RGB;
++
++ hdmi->hdmi_data.enc_out_format = RGB;
++
++ /* YCbCr only enabled in HDMI mode */
++ if ((hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_HDMI) &&
++ !hdmi->hdmi_data.rgb_out_enable) {
++ if (hdmi->edid_cfg.cea_ycbcr444)
++ hdmi->hdmi_data.enc_out_format = YCBCR444;
++ else if (hdmi->edid_cfg.cea_ycbcr422)
++ hdmi->hdmi_data.enc_out_format = YCBCR422_8BITS;
++ }
++
++ /* IPU not support depth color output */
++ hdmi->hdmi_data.enc_color_depth = 8;
++ hdmi->hdmi_data.pix_repet_factor = 0;
++ hdmi->hdmi_data.video_mode.mDataEnablePolarity = true;
++
++ /* HDMI Initialization Step B.1 */
++ hdmi_av_composer(hdmi);
++
++ /* HDMI Initialization Step B.2 */
++ mxc_hdmi_phy_init(hdmi);
++
++ /* HDMI Initialization Step B.3 */
++ mxc_hdmi_enable_video_path(hdmi);
++
++ /* not for DVI mode */
++ if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_HDMI) {
++ dev_dbg(&hdmi->pdev->dev, "%s CEA mode\n", __func__);
++
++ /* HDMI Initialization Step E - Configure audio */
++ hdmi_enable_audio_clk(hdmi);
++
++ /* HDMI Initialization Step F - Configure AVI InfoFrame */
++ hdmi_config_AVI(hdmi);
++ } else {
++ dev_dbg(&hdmi->pdev->dev, "%s DVI mode\n", __func__);
++ }
++
++ hdmi_video_packetize(hdmi);
++ hdmi_video_csc(hdmi);
++ hdmi_video_sample(hdmi);
++
++ mxc_hdmi_clear_overflow(hdmi);
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n\n", __func__);
++
++}
++
++/* Wait until we are registered to enable interrupts */
++static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi)
++{
++ unsigned long flags;
++
++ if (hdmi->fb_reg)
++ return;
++
++ mxcfb_blank(FB_BLANK_POWERDOWN, hdmi->fbi);
++
++ spin_lock_irqsave(&hdmi->irq_lock, flags);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ hdmi_writeb(HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
++ HDMI_PHY_I2CM_INT_ADDR);
++
++ hdmi_writeb(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
++ HDMI_PHY_I2CM_CTLINT_ADDR);
++
++ /* enable cable hot plug irq */
++ hdmi_writeb(~hdmi->plug_mask, HDMI_PHY_MASK0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi->plug_event, HDMI_IH_PHY_STAT0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~hdmi->plug_event, HDMI_IH_MUTE_PHY_STAT0);
++
++ hdmi->fb_reg = true;
++
++ spin_unlock_irqrestore(&hdmi->irq_lock, flags);
++
++}
++
++static int mxc_hdmi_fb_event(struct notifier_block *nb,
++ unsigned long val, void *v)
++{
++ struct fb_event *event = v;
++ struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb);
++
++ if (strcmp(event->info->fix.id, hdmi->fbi->fix.id))
++ return 0;
++
++ switch (val) {
++ case FB_EVENT_FB_REGISTERED:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_REGISTERED\n");
++ mxc_hdmi_fb_registered(hdmi);
++ hdmi_set_registered(1);
++ break;
++
++ case FB_EVENT_FB_UNREGISTERED:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_FB_UNREGISTERED\n");
++ hdmi->fb_reg = false;
++ hdmi_set_registered(0);
++ break;
++
++ case FB_EVENT_MODE_CHANGE:
++ dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n");
++ if (hdmi->fb_reg)
++ mxc_hdmi_setup(hdmi, val);
++ break;
++
++ case FB_EVENT_BLANK:
++ if (!hdmi->fb_reg || (hdmi->hp_state == HDMI_HOTPLUG_DISCONNECTED && *((int *)event->data) == FB_BLANK_UNBLANK)) {
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_BLANK - NOOP\n");
++ break;
++ }
++
++ if ((*((int *)event->data) == FB_BLANK_UNBLANK) &&
++ (*((int *)event->data) != hdmi->blank)) {
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_BLANK - UNBLANK\n");
++
++ hdmi->blank = *((int *)event->data);
++
++ /* Re-enable HPD interrupts */
++ val = hdmi_readb(HDMI_PHY_MASK0);
++ val &= ~hdmi->plug_mask;
++ hdmi_writeb(val, HDMI_PHY_MASK0);
++
++ /* Unmute interrupts */
++ hdmi_writeb(~hdmi->plug_event, HDMI_IH_MUTE_PHY_STAT0);
++
++ hdmi_set_blank_state(1);
++ if (check_hdmi_state())
++ mxc_hdmi_setup(hdmi, val);
++ } else if (*((int *)event->data) != hdmi->blank) {
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_BLANK - BLANK\n");
++ hdmi_set_blank_state(0);
++ mxc_hdmi_abort_stream();
++
++ mxc_hdmi_phy_disable(hdmi);
++
++ if(hdmi->hp_state == HDMI_HOTPLUG_CONNECTED_DVI) {
++ u8 val;
++ pr_debug("In DVI Mode, disabling hotplug interrupts until unblanked\n");
++ val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
++ val |= hdmi->plug_event;
++ hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
++
++ val = hdmi_readb(HDMI_PHY_MASK0);
++ val |= hdmi->plug_mask;
++ hdmi_writeb(val, HDMI_PHY_MASK0);
++
++ hdmi_set_dvi_mode(1);
++ }
++
++ hdmi->blank = *((int *)event->data);
++ } else
++ dev_dbg(&hdmi->pdev->dev,
++ "FB BLANK state no changed!\n");
++
++ break;
++
++ case FB_EVENT_SUSPEND:
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_SUSPEND\n");
++
++ if (hdmi->blank == FB_BLANK_UNBLANK) {
++ mxc_hdmi_phy_disable(hdmi);
++ clk_disable(hdmi->hdmi_iahb_clk);
++ clk_disable(hdmi->hdmi_isfr_clk);
++ clk_disable(hdmi->mipi_core_clk);
++ }
++ break;
++
++ case FB_EVENT_RESUME:
++ dev_dbg(&hdmi->pdev->dev,
++ "event=FB_EVENT_RESUME\n");
++
++ if (hdmi->blank == FB_BLANK_UNBLANK) {
++ clk_enable(hdmi->mipi_core_clk);
++ clk_enable(hdmi->hdmi_iahb_clk);
++ clk_enable(hdmi->hdmi_isfr_clk);
++ mxc_hdmi_phy_init(hdmi);
++ }
++ break;
++
++ }
++ return 0;
++}
++
++static void hdmi_init_route(struct mxc_hdmi *hdmi)
++{
++ uint32_t hdmi_mux_setting, reg;
++ int ipu_id, disp_id;
++
++ ipu_id = mxc_hdmi_ipu_id;
++ disp_id = mxc_hdmi_disp_id;
++
++ if ((ipu_id > 1) || (ipu_id < 0)) {
++ pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
++ ipu_id = 0;
++ }
++
++ if ((disp_id > 1) || (disp_id < 0)) {
++ pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
++ disp_id = 0;
++ }
++
++ reg = readl(hdmi->gpr_hdmi_base);
++
++ /* Configure the connection between IPU1/2 and HDMI */
++ hdmi_mux_setting = 2*ipu_id + disp_id;
++
++ /* GPR3, bits 2-3 = HDMI_MUX_CTL */
++ reg &= ~0xd;
++ reg |= hdmi_mux_setting << 2;
++
++ writel(reg, hdmi->gpr_hdmi_base);
++
++ /* Set HDMI event as SDMA event2 for HDMI audio */
++ reg = readl(hdmi->gpr_sdma_base);
++ reg |= 0x1;
++ writel(reg, hdmi->gpr_sdma_base);
++}
++
++static void hdmi_hdcp_get_property(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++
++ /* Check hdcp enable by dts.*/
++ hdcp_init = of_property_read_bool(np, "fsl,hdcp");
++ if (hdcp_init)
++ dev_dbg(&pdev->dev, "hdcp enable\n");
++ else
++ dev_dbg(&pdev->dev, "hdcp disable\n");
++}
++
++static void hdmi_get_of_property(struct mxc_hdmi *hdmi)
++{
++ struct platform_device *pdev = hdmi->pdev;
++ struct device_node *np = pdev->dev.of_node;
++ const struct of_device_id *of_id =
++ of_match_device(imx_hdmi_dt_ids, &pdev->dev);
++ int ret;
++ u32 phy_reg_vlev = 0, phy_reg_cksymtx = 0;
++
++ if (of_id) {
++ pdev->id_entry = of_id->data;
++ hdmi->cpu_type = pdev->id_entry->driver_data;
++ }
++
++ /* HDMI PHY register vlev and cksymtx preperty is optional.
++ * It is for specific board to pass HCT electrical part.
++ * Default value will been setting in HDMI PHY config function
++ * if it is not define in device tree.
++ */
++ ret = of_property_read_u32(np, "fsl,phy_reg_vlev", &phy_reg_vlev);
++ if (ret)
++ dev_dbg(&pdev->dev, "No board specific HDMI PHY vlev\n");
++
++ ret = of_property_read_u32(np, "fsl,phy_reg_cksymtx", &phy_reg_cksymtx);
++ if (ret)
++ dev_dbg(&pdev->dev, "No board specific HDMI PHY cksymtx\n");
++
++ /* Specific phy config */
++ hdmi->phy_config.reg_cksymtx = phy_reg_cksymtx;
++ hdmi->phy_config.reg_vlev = phy_reg_vlev;
++
++}
++
++/* HDMI Initialization Step A */
++static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret = 0;
++ u32 i;
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++ int irq = platform_get_irq(hdmi->pdev, 0);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ /* Check hdmi disp init once */
++ if (hdmi_inited) {
++ dev_err(&hdmi->pdev->dev,
++ "Error only one HDMI output support now!\n");
++ return -1;
++ }
++
++ hdmi_get_of_property(hdmi);
++
++ if (irq < 0)
++ return -ENODEV;
++
++ /* Setting HDMI default to blank state */
++ hdmi->blank = FB_BLANK_POWERDOWN;
++
++ ret = ipu_di_to_crtc(&hdmi->pdev->dev, mxc_hdmi_ipu_id,
++ mxc_hdmi_disp_id, &setting->crtc);
++ if (ret < 0)
++ return ret;
++
++ setting->if_fmt = IPU_PIX_FMT_RGB24;
++
++ hdmi->dft_mode_str = setting->dft_mode_str;
++ hdmi->default_bpp = setting->default_bpp;
++ dev_dbg(&hdmi->pdev->dev, "%s - default mode %s bpp=%d\n",
++ __func__, hdmi->dft_mode_str, hdmi->default_bpp);
++
++ hdmi->fbi = setting->fbi;
++
++ hdmi_init_route(hdmi);
++
++ hdmi->mipi_core_clk = clk_get(&hdmi->pdev->dev, "mipi_core");
++ if (IS_ERR(hdmi->mipi_core_clk)) {
++ ret = PTR_ERR(hdmi->mipi_core_clk);
++ dev_err(&hdmi->pdev->dev,
++ "Unable to get mipi core clk: %d\n", ret);
++ goto egetclk;
++ }
++
++ ret = clk_prepare_enable(hdmi->mipi_core_clk);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Cannot enable mipi core clock: %d\n", ret);
++ goto erate;
++ }
++
++ hdmi->hdmi_isfr_clk = clk_get(&hdmi->pdev->dev, "hdmi_isfr");
++ if (IS_ERR(hdmi->hdmi_isfr_clk)) {
++ ret = PTR_ERR(hdmi->hdmi_isfr_clk);
++ dev_err(&hdmi->pdev->dev,
++ "Unable to get HDMI clk: %d\n", ret);
++ goto egetclk1;
++ }
++
++ ret = clk_prepare_enable(hdmi->hdmi_isfr_clk);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Cannot enable HDMI isfr clock: %d\n", ret);
++ goto erate1;
++ }
++
++ hdmi->hdmi_iahb_clk = clk_get(&hdmi->pdev->dev, "hdmi_iahb");
++ if (IS_ERR(hdmi->hdmi_iahb_clk)) {
++ ret = PTR_ERR(hdmi->hdmi_iahb_clk);
++ dev_err(&hdmi->pdev->dev,
++ "Unable to get HDMI clk: %d\n", ret);
++ goto egetclk2;
++ }
++
++ ret = clk_prepare_enable(hdmi->hdmi_iahb_clk);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Cannot enable HDMI iahb clock: %d\n", ret);
++ goto erate2;
++ }
++
++ dev_dbg(&hdmi->pdev->dev, "Enabled HDMI clocks\n");
++
++ /* Init DDC pins for HDCP */
++ if (hdcp_init) {
++ hdmi->pinctrl = devm_pinctrl_get_select_default(&hdmi->pdev->dev);
++ if (IS_ERR(hdmi->pinctrl)) {
++ dev_err(&hdmi->pdev->dev, "can't get/select DDC pinctrl\n");
++ goto erate2;
++ }
++ }
++
++ /* Product and revision IDs */
++ dev_info(&hdmi->pdev->dev,
++ "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
++ hdmi_readb(HDMI_DESIGN_ID),
++ hdmi_readb(HDMI_REVISION_ID),
++ hdmi_readb(HDMI_PRODUCT_ID0),
++ hdmi_readb(HDMI_PRODUCT_ID1));
++
++ /* To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
++ * N and cts values before enabling phy */
++ hdmi_init_clk_regenerator();
++
++ INIT_LIST_HEAD(&hdmi->fbi->modelist);
++
++ spin_lock_init(&hdmi->irq_lock);
++
++ /* Set the default mode and modelist when disp init. */
++ fb_find_mode(&hdmi->fbi->var, hdmi->fbi,
++ hdmi->dft_mode_str, NULL, 0, NULL,
++ hdmi->default_bpp);
++
++ console_lock();
++
++ fb_destroy_modelist(&hdmi->fbi->modelist);
++
++ /*Add all no interlaced CEA mode to default modelist */
++ for (i = 0; i < ARRAY_SIZE(mxc_cea_mode); i++) {
++ mode = &mxc_cea_mode[i];
++ if (mode->xres != 0) {
++ struct fb_videomode m = *mode;
++ m.flag |= FB_MODE_IS_STANDARD;
++ fb_add_videomode(&m, &hdmi->fbi->modelist);
++ }
++ }
++
++ console_unlock();
++
++ /* Find a nearest mode in default modelist */
++ fb_var_to_videomode(&m, &hdmi->fbi->var);
++ hdmi->dft_mode_set = false;
++
++ mode = fb_find_nearest_mode(&m, &hdmi->fbi->modelist);
++ if (!mode) {
++ pr_err("%s: could not find mode in modelist\n", __func__);
++ return -1;
++ }
++ dump_fb_videomode((struct fb_videomode *)mode);
++ /* Save default video mode */
++ memcpy(&hdmi->default_mode, mode, sizeof(struct fb_videomode));
++
++ fb_videomode_to_var(&hdmi->fbi->var, mode);
++ memcpy(&hdmi->prev_virtual, &hdmi->fbi->var.xres_virtual, sizeof(hdmi->prev_virtual));
++
++ /* update fbi mode */
++ hdmi->fbi->mode = (struct fb_videomode *)mode;
++
++ /* Default setting HDMI working in HDMI mode*/
++ hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
++
++ hdmi->plug_event = HDMI_DVI_IH_STAT;
++ hdmi->plug_mask = HDMI_DVI_STAT;
++
++ setup_timer(&hdmi->jitter_timer, hotplug_work_launch, (unsigned long)hdmi);
++ INIT_WORK(&hdmi->hotplug_work, hotplug_worker);
++ INIT_DELAYED_WORK(&hdmi->hdcp_hdp_work, hdcp_hdp_worker);
++
++ /* Configure registers related to HDMI interrupt
++ * generation before registering IRQ. */
++ hdmi_writeb(hdmi->plug_mask, HDMI_PHY_POL0);
++
++ /* Clear Hotplug interrupts */
++ hdmi_writeb(hdmi->plug_event, HDMI_IH_PHY_STAT0);
++
++ hdmi->nb.notifier_call = mxc_hdmi_fb_event;
++ ret = fb_register_client(&hdmi->nb);
++ if (ret < 0)
++ goto efbclient;
++
++ memset(&hdmi->hdmi_data, 0, sizeof(struct hdmi_data_info));
++
++ /* Default HDMI working in RGB mode */
++ hdmi->hdmi_data.rgb_out_enable = true;
++
++ if (!strcasecmp(rgb_quant_range, "limited")) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE;
++ } else if (!strcasecmp(rgb_quant_range, "full")) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE;
++ } else if (!strcasecmp(rgb_quant_range, "default")) {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT;
++ } else {
++ hdmi->hdmi_data.rgb_quant_range = HDMI_FC_AVICONF2_RGB_QUANT_MASK;
++ }
++
++ ret = devm_request_irq(&hdmi->pdev->dev, irq, mxc_hdmi_hotplug, IRQF_SHARED,
++ dev_name(&hdmi->pdev->dev), hdmi);
++ if (ret < 0) {
++ dev_err(&hdmi->pdev->dev,
++ "Unable to request irq: %d\n", ret);
++ goto ereqirq;
++ }
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_fb_name);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for fb name\n");
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_cable_state);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for cable state\n");
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_edid);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for edid\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_rgb_out_enable);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for rgb out enable\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_rgb_quant_range);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for rgb quant range\n");
++
++ ret = device_create_file(&hdmi->pdev->dev, &dev_attr_hdcp_enable);
++ if (ret < 0)
++ dev_warn(&hdmi->pdev->dev,
++ "cound not create sys node for hdcp enable\n");
++
++ dev_dbg(&hdmi->pdev->dev, "%s exit\n", __func__);
++
++ hdmi_inited = true;
++
++ return ret;
++
++efbclient:
++ free_irq(irq, hdmi);
++ereqirq:
++ clk_disable_unprepare(hdmi->hdmi_iahb_clk);
++erate2:
++ clk_put(hdmi->hdmi_iahb_clk);
++egetclk2:
++ clk_disable_unprepare(hdmi->hdmi_isfr_clk);
++erate1:
++ clk_put(hdmi->hdmi_isfr_clk);
++egetclk1:
++ clk_disable_unprepare(hdmi->mipi_core_clk);
++erate:
++ clk_put(hdmi->mipi_core_clk);
++egetclk:
++ dev_dbg(&hdmi->pdev->dev, "%s error exit\n", __func__);
++
++ return ret;
++}
++
++static void mxc_hdmi_disp_deinit(struct mxc_dispdrv_handle *disp)
++{
++ struct mxc_hdmi *hdmi = mxc_dispdrv_getdata(disp);
++
++ dev_dbg(&hdmi->pdev->dev, "%s\n", __func__);
++
++ fb_unregister_client(&hdmi->nb);
++
++ clk_disable_unprepare(hdmi->hdmi_isfr_clk);
++ clk_put(hdmi->hdmi_isfr_clk);
++ clk_disable_unprepare(hdmi->hdmi_iahb_clk);
++ clk_put(hdmi->hdmi_iahb_clk);
++ clk_disable_unprepare(hdmi->mipi_core_clk);
++ clk_put(hdmi->mipi_core_clk);
++
++ platform_device_unregister(hdmi->pdev);
++
++ hdmi_inited = false;
++}
++
++static struct mxc_dispdrv_driver mxc_hdmi_drv = {
++ .name = DISPDRV_HDMI,
++ .init = mxc_hdmi_disp_init,
++ .deinit = mxc_hdmi_disp_deinit,
++ .enable = mxc_hdmi_power_on,
++ .disable = mxc_hdmi_power_off,
++};
++
++
++static int mxc_hdmi_open(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static long mxc_hdmi_ioctl(struct file *file,
++ unsigned int cmd, unsigned long arg)
++{
++ int __user *argp = (void __user *)arg;
++ int ret = 0;
++
++ switch (cmd) {
++ case HDMI_IOC_GET_RESOURCE:
++ ret = copy_to_user(argp, &g_hdmi->hdmi_data,
++ sizeof(g_hdmi->hdmi_data)) ? -EFAULT : 0;
++ break;
++ case HDMI_IOC_GET_CPU_TYPE:
++ *argp = g_hdmi->cpu_type;
++ break;
++ default:
++ pr_debug("Unsupport cmd %d\n", cmd);
++ break;
++ }
++ return ret;
++}
++
++static int mxc_hdmi_release(struct inode *inode, struct file *file)
++{
++ return 0;
++}
++
++static const struct file_operations mxc_hdmi_fops = {
++ .owner = THIS_MODULE,
++ .open = mxc_hdmi_open,
++ .release = mxc_hdmi_release,
++ .unlocked_ioctl = mxc_hdmi_ioctl,
++};
++
++
++static int mxc_hdmi_probe(struct platform_device *pdev)
++{
++ struct mxc_hdmi *hdmi;
++ struct device *temp_class;
++ struct resource *res;
++ int ret = 0;
++
++ /* Check I2C driver is loaded and available
++ * check hdcp function is enable by dts */
++ hdmi_hdcp_get_property(pdev);
++ if (!hdmi_i2c && !hdcp_init)
++ return -ENODEV;
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res)
++ return -ENOENT;
++
++ hdmi = devm_kzalloc(&pdev->dev,
++ sizeof(struct mxc_hdmi),
++ GFP_KERNEL);
++ if (!hdmi) {
++ dev_err(&pdev->dev, "Cannot allocate device data\n");
++ ret = -ENOMEM;
++ goto ealloc;
++ }
++ g_hdmi = hdmi;
++
++ hdmi_major = register_chrdev(hdmi_major, "mxc_hdmi", &mxc_hdmi_fops);
++ if (hdmi_major < 0) {
++ printk(KERN_ERR "HDMI: unable to get a major for HDMI\n");
++ ret = -EBUSY;
++ goto ealloc;
++ }
++
++ hdmi_class = class_create(THIS_MODULE, "mxc_hdmi");
++ if (IS_ERR(hdmi_class)) {
++ ret = PTR_ERR(hdmi_class);
++ goto err_out_chrdev;
++ }
++
++ temp_class = device_create(hdmi_class, NULL, MKDEV(hdmi_major, 0),
++ NULL, "mxc_hdmi");
++ if (IS_ERR(temp_class)) {
++ ret = PTR_ERR(temp_class);
++ goto err_out_class;
++ }
++
++ hdmi->pdev = pdev;
++
++ hdmi->core_pdev = platform_device_alloc("mxc_hdmi_core", -1);
++ if (!hdmi->core_pdev) {
++ pr_err("%s failed platform_device_alloc for hdmi core\n",
++ __func__);
++ ret = -ENOMEM;
++ goto ecore;
++ }
++
++ hdmi->gpr_base = ioremap(res->start, resource_size(res));
++ if (!hdmi->gpr_base) {
++ dev_err(&pdev->dev, "ioremap failed\n");
++ ret = -ENOMEM;
++ goto eiomap;
++ }
++
++ hdmi->gpr_hdmi_base = hdmi->gpr_base + 3;
++ hdmi->gpr_sdma_base = hdmi->gpr_base;
++
++ hdmi_inited = false;
++
++ hdmi->disp_mxc_hdmi = mxc_dispdrv_register(&mxc_hdmi_drv);
++ if (IS_ERR(hdmi->disp_mxc_hdmi)) {
++ dev_err(&pdev->dev, "Failed to register dispdrv - 0x%x\n",
++ (int)hdmi->disp_mxc_hdmi);
++ ret = (int)hdmi->disp_mxc_hdmi;
++ goto edispdrv;
++ }
++ mxc_dispdrv_setdata(hdmi->disp_mxc_hdmi, hdmi);
++
++ platform_set_drvdata(pdev, hdmi);
++
++ return 0;
++edispdrv:
++ iounmap(hdmi->gpr_base);
++eiomap:
++ platform_device_put(hdmi->core_pdev);
++ecore:
++ kfree(hdmi);
++err_out_class:
++ device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
++ class_destroy(hdmi_class);
++err_out_chrdev:
++ unregister_chrdev(hdmi_major, "mxc_hdmi");
++ealloc:
++ return ret;
++}
++
++static int mxc_hdmi_remove(struct platform_device *pdev)
++{
++ struct mxc_hdmi *hdmi = platform_get_drvdata(pdev);
++ int irq = platform_get_irq(pdev, 0);
++
++ fb_unregister_client(&hdmi->nb);
++
++ mxc_dispdrv_puthandle(hdmi->disp_mxc_hdmi);
++ mxc_dispdrv_unregister(hdmi->disp_mxc_hdmi);
++ iounmap(hdmi->gpr_base);
++ /* No new work will be scheduled, wait for running ISR */
++ free_irq(irq, hdmi);
++ kfree(hdmi);
++ g_hdmi = NULL;
++
++ return 0;
++}
++
++static struct platform_driver mxc_hdmi_driver = {
++ .probe = mxc_hdmi_probe,
++ .remove = mxc_hdmi_remove,
++ .driver = {
++ .name = "mxc_hdmi",
++ .of_match_table = imx_hdmi_dt_ids,
++ .owner = THIS_MODULE,
++ },
++};
++
++static int __init mxc_hdmi_init(void)
++{
++ return platform_driver_register(&mxc_hdmi_driver);
++}
++module_init(mxc_hdmi_init);
++
++static void __exit mxc_hdmi_exit(void)
++{
++ if (hdmi_major > 0) {
++ device_destroy(hdmi_class, MKDEV(hdmi_major, 0));
++ class_destroy(hdmi_class);
++ unregister_chrdev(hdmi_major, "mxc_hdmi");
++ hdmi_major = 0;
++ }
++
++ platform_driver_unregister(&mxc_hdmi_driver);
++}
++module_exit(mxc_hdmi_exit);
++
++static int mxc_hdmi_i2c_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ if (!i2c_check_functionality(client->adapter,
++ I2C_FUNC_SMBUS_BYTE | I2C_FUNC_I2C))
++ return -ENODEV;
++
++ hdmi_i2c = client;
++
++ return 0;
++}
++
++static int mxc_hdmi_i2c_remove(struct i2c_client *client)
++{
++ hdmi_i2c = NULL;
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_i2c_match[] = {
++ { .compatible = "fsl,imx6-hdmi-i2c", },
++ { /* sentinel */ }
++};
++
++static const struct i2c_device_id mxc_hdmi_i2c_id[] = {
++ { "mxc_hdmi_i2c", 0 },
++ {},
++};
++MODULE_DEVICE_TABLE(i2c, mxc_hdmi_i2c_id);
++
++static struct i2c_driver mxc_hdmi_i2c_driver = {
++ .driver = {
++ .name = "mxc_hdmi_i2c",
++ .of_match_table = imx_hdmi_i2c_match,
++ },
++ .probe = mxc_hdmi_i2c_probe,
++ .remove = mxc_hdmi_i2c_remove,
++ .id_table = mxc_hdmi_i2c_id,
++};
++
++static int __init mxc_hdmi_i2c_init(void)
++{
++ return i2c_add_driver(&mxc_hdmi_i2c_driver);
++}
++
++static void __exit mxc_hdmi_i2c_exit(void)
++{
++ i2c_del_driver(&mxc_hdmi_i2c_driver);
++}
++
++module_init(mxc_hdmi_i2c_init);
++module_exit(mxc_hdmi_i2c_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_ipuv3_fb.c linux-3.14.72/drivers/video/mxc/mxc_ipuv3_fb.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_ipuv3_fb.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_ipuv3_fb.c 2016-06-19 22:11:55.353136857 +0200
+@@ -0,0 +1,2633 @@
++/*
++ * Copyright 2004-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxcfb.c
++ *
++ * @brief MXC Frame buffer driver for SDC
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/errno.h>
++#include <linux/fb.h>
++#include <linux/fsl_devices.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/ipu.h>
++#include <linux/ipu-v3.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++#include <linux/string.h>
++#include <linux/uaccess.h>
++
++#include "mxc_dispdrv.h"
++
++/*
++ * Driver name
++ */
++#define MXCFB_NAME "mxc_sdc_fb"
++
++/* Display port number */
++#define MXCFB_PORT_NUM 2
++/*!
++ * Structure containing the MXC specific framebuffer information.
++ */
++struct mxcfb_info {
++ int default_bpp;
++ int cur_blank;
++ int next_blank;
++ ipu_channel_t ipu_ch;
++ int ipu_id;
++ int ipu_di;
++ u32 ipu_di_pix_fmt;
++ bool ipu_int_clk;
++ bool overlay;
++ bool alpha_chan_en;
++ bool late_init;
++ bool first_set_par;
++ dma_addr_t alpha_phy_addr0;
++ dma_addr_t alpha_phy_addr1;
++ void *alpha_virt_addr0;
++ void *alpha_virt_addr1;
++ uint32_t alpha_mem_len;
++ uint32_t ipu_ch_irq;
++ uint32_t ipu_ch_nf_irq;
++ uint32_t ipu_alp_ch_irq;
++ uint32_t cur_ipu_buf;
++ uint32_t cur_ipu_alpha_buf;
++
++ u32 pseudo_palette[16];
++
++ bool mode_found;
++ struct completion flip_complete;
++ struct completion alpha_flip_complete;
++ struct completion vsync_complete;
++
++ void *ipu;
++ struct fb_info *ovfbi;
++
++ struct mxc_dispdrv_handle *dispdrv;
++
++ struct fb_var_screeninfo cur_var;
++};
++
++struct mxcfb_pfmt {
++ u32 fb_pix_fmt;
++ int bpp;
++ struct fb_bitfield red;
++ struct fb_bitfield green;
++ struct fb_bitfield blue;
++ struct fb_bitfield transp;
++};
++
++static const struct mxcfb_pfmt mxcfb_pfmts[] = {
++ /* pixel bpp red green blue transp */
++ {IPU_PIX_FMT_RGB565, 16, {11, 5, 0}, { 5, 6, 0}, { 0, 5, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_RGB24, 24, { 0, 8, 0}, { 8, 8, 0}, {16, 8, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_BGR24, 24, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, { 0, 0, 0} },
++ {IPU_PIX_FMT_RGB32, 32, { 0, 8, 0}, { 8, 8, 0}, {16, 8, 0}, {24, 8, 0} },
++ {IPU_PIX_FMT_BGR32, 32, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0}, {24, 8, 0} },
++ {IPU_PIX_FMT_ABGR32, 32, {24, 8, 0}, {16, 8, 0}, { 8, 8, 0}, { 0, 8, 0} },
++};
++
++struct mxcfb_alloc_list {
++ struct list_head list;
++ dma_addr_t phy_addr;
++ void *cpu_addr;
++ u32 size;
++};
++
++enum {
++ BOTH_ON,
++ SRC_ON,
++ TGT_ON,
++ BOTH_OFF
++};
++
++static bool g_dp_in_use[2];
++LIST_HEAD(fb_alloc_list);
++
++/* Return default standard(RGB) pixel format */
++static uint32_t bpp_to_pixfmt(int bpp)
++{
++ uint32_t pixfmt = 0;
++
++ switch (bpp) {
++ case 24:
++ pixfmt = IPU_PIX_FMT_BGR24;
++ break;
++ case 32:
++ pixfmt = IPU_PIX_FMT_BGR32;
++ break;
++ case 16:
++ pixfmt = IPU_PIX_FMT_RGB565;
++ break;
++ }
++ return pixfmt;
++}
++
++static inline int bitfield_is_equal(struct fb_bitfield f1,
++ struct fb_bitfield f2)
++{
++ return !memcmp(&f1, &f2, sizeof(f1));
++}
++
++static int pixfmt_to_var(uint32_t pixfmt, struct fb_var_screeninfo *var)
++{
++ int i, ret = -1;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (pixfmt == mxcfb_pfmts[i].fb_pix_fmt) {
++ var->red = mxcfb_pfmts[i].red;
++ var->green = mxcfb_pfmts[i].green;
++ var->blue = mxcfb_pfmts[i].blue;
++ var->transp = mxcfb_pfmts[i].transp;
++ var->bits_per_pixel = mxcfb_pfmts[i].bpp;
++ ret = 0;
++ break;
++ }
++ }
++ return ret;
++}
++
++static int bpp_to_var(int bpp, struct fb_var_screeninfo *var)
++{
++ uint32_t pixfmt = 0;
++
++ pixfmt = bpp_to_pixfmt(bpp);
++ if (pixfmt)
++ return pixfmt_to_var(pixfmt, var);
++ else
++ return -1;
++}
++
++static int check_var_pixfmt(struct fb_var_screeninfo *var)
++{
++ int i, ret = -1;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (bitfield_is_equal(var->red, mxcfb_pfmts[i].red) &&
++ bitfield_is_equal(var->green, mxcfb_pfmts[i].green) &&
++ bitfield_is_equal(var->blue, mxcfb_pfmts[i].blue) &&
++ bitfield_is_equal(var->transp, mxcfb_pfmts[i].transp) &&
++ var->bits_per_pixel == mxcfb_pfmts[i].bpp) {
++ ret = 0;
++ break;
++ }
++ }
++ return ret;
++}
++
++static uint32_t fbi_to_pixfmt(struct fb_info *fbi)
++{
++ int i;
++ uint32_t pixfmt = 0;
++
++ if (fbi->var.nonstd)
++ return fbi->var.nonstd;
++
++ for (i = 0; i < ARRAY_SIZE(mxcfb_pfmts); i++) {
++ if (bitfield_is_equal(fbi->var.red, mxcfb_pfmts[i].red) &&
++ bitfield_is_equal(fbi->var.green, mxcfb_pfmts[i].green) &&
++ bitfield_is_equal(fbi->var.blue, mxcfb_pfmts[i].blue) &&
++ bitfield_is_equal(fbi->var.transp, mxcfb_pfmts[i].transp)) {
++ pixfmt = mxcfb_pfmts[i].fb_pix_fmt;
++ break;
++ }
++ }
++
++ if (pixfmt == 0)
++ dev_err(fbi->device, "cannot get pixel format\n");
++
++ return pixfmt;
++}
++
++static struct fb_info *found_registered_fb(ipu_channel_t ipu_ch, int ipu_id)
++{
++ int i;
++ struct mxcfb_info *mxc_fbi;
++ struct fb_info *fbi = NULL;
++
++ for (i = 0; i < num_registered_fb; i++) {
++ mxc_fbi =
++ ((struct mxcfb_info *)(registered_fb[i]->par));
++
++ if ((mxc_fbi->ipu_ch == ipu_ch) &&
++ (mxc_fbi->ipu_id == ipu_id)) {
++ fbi = registered_fb[i];
++ break;
++ }
++ }
++ return fbi;
++}
++
++static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id);
++static irqreturn_t mxcfb_nf_irq_handler(int irq, void *dev_id);
++int mxcfb_blank(int blank, struct fb_info *info);
++static int mxcfb_map_video_memory(struct fb_info *fbi);
++static int mxcfb_unmap_video_memory(struct fb_info *fbi);
++
++/*
++ * Set fixed framebuffer parameters based on variable settings.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_set_fix(struct fb_info *info)
++{
++ struct fb_fix_screeninfo *fix = &info->fix;
++ struct fb_var_screeninfo *var = &info->var;
++
++ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
++
++ fix->type = FB_TYPE_PACKED_PIXELS;
++ fix->accel = FB_ACCEL_NONE;
++ fix->visual = FB_VISUAL_TRUECOLOR;
++ fix->xpanstep = 1;
++ fix->ywrapstep = 1;
++ fix->ypanstep = 1;
++
++ return 0;
++}
++
++static int _setup_disp_channel1(struct fb_info *fbi)
++{
++ ipu_channel_params_t params;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ memset(&params, 0, sizeof(params));
++
++ if (mxc_fbi->ipu_ch == MEM_DC_SYNC) {
++ params.mem_dc_sync.di = mxc_fbi->ipu_di;
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ params.mem_dc_sync.interlaced = true;
++ params.mem_dc_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ params.mem_dc_sync.in_pixel_fmt = fbi_to_pixfmt(fbi);
++ } else {
++ params.mem_dp_bg_sync.di = mxc_fbi->ipu_di;
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ params.mem_dp_bg_sync.interlaced = true;
++ params.mem_dp_bg_sync.out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ params.mem_dp_bg_sync.in_pixel_fmt = fbi_to_pixfmt(fbi);
++ if (mxc_fbi->alpha_chan_en)
++ params.mem_dp_bg_sync.alpha_chan_en = true;
++ }
++ ipu_init_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, &params);
++
++ return 0;
++}
++
++static int _setup_disp_channel2(struct fb_info *fbi)
++{
++ int retval = 0;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++ int fb_stride;
++ unsigned long base;
++ unsigned int fr_xoff, fr_yoff, fr_w, fr_h;
++
++ switch (fbi_to_pixfmt(fbi)) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YUV444P:
++ fb_stride = fbi->var.xres_virtual;
++ break;
++ default:
++ fb_stride = fbi->fix.line_length;
++ }
++
++ base = fbi->fix.smem_start;
++ fr_xoff = fbi->var.xoffset;
++ fr_w = fbi->var.xres_virtual;
++ if (!(fbi->var.vmode & FB_VMODE_YWRAP)) {
++ dev_dbg(fbi->device, "Y wrap disabled\n");
++ fr_yoff = fbi->var.yoffset % fbi->var.yres;
++ fr_h = fbi->var.yres;
++ base += fbi->fix.line_length * fbi->var.yres *
++ (fbi->var.yoffset / fbi->var.yres);
++ } else {
++ dev_dbg(fbi->device, "Y wrap enabled\n");
++ fr_yoff = fbi->var.yoffset;
++ fr_h = fbi->var.yres_virtual;
++ }
++ base += fr_yoff * fb_stride + fr_xoff;
++
++ mxc_fbi->cur_ipu_buf = 2;
++ init_completion(&mxc_fbi->flip_complete);
++ /*
++ * We don't need to wait for vsync at the first time
++ * we do pan display after fb is initialized, as IPU will
++ * switch to the newly selected buffer automatically,
++ * so we call complete() for both mxc_fbi->flip_complete
++ * and mxc_fbi->alpha_flip_complete.
++ */
++ complete(&mxc_fbi->flip_complete);
++ if (mxc_fbi->alpha_chan_en) {
++ mxc_fbi->cur_ipu_alpha_buf = 1;
++ init_completion(&mxc_fbi->alpha_flip_complete);
++ complete(&mxc_fbi->alpha_flip_complete);
++ }
++
++ retval = ipu_init_channel_buffer(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(fbi),
++ fbi->var.xres, fbi->var.yres,
++ fb_stride,
++ fbi->var.rotate,
++ base,
++ base,
++ fbi->var.accel_flags &
++ FB_ACCEL_DOUBLE_FLAG ? 0 : base,
++ 0, 0);
++ if (retval) {
++ dev_err(fbi->device,
++ "ipu_init_channel_buffer error %d\n", retval);
++ return retval;
++ }
++
++ /* update u/v offset */
++ ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(fbi),
++ fr_w,
++ fr_h,
++ fr_w,
++ 0, 0,
++ fr_yoff,
++ fr_xoff);
++
++ if (mxc_fbi->alpha_chan_en) {
++ retval = ipu_init_channel_buffer(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ IPU_PIX_FMT_GENERIC,
++ fbi->var.xres, fbi->var.yres,
++ fbi->var.xres,
++ fbi->var.rotate,
++ mxc_fbi->alpha_phy_addr1,
++ mxc_fbi->alpha_phy_addr0,
++ 0,
++ 0, 0);
++ if (retval) {
++ dev_err(fbi->device,
++ "ipu_init_channel_buffer error %d\n", retval);
++ return retval;
++ }
++ }
++
++ return retval;
++}
++
++static bool mxcfb_need_to_set_par(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ if ((fbi->var.activate & FB_ACTIVATE_FORCE) &&
++ (fbi->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
++ return true;
++
++ /*
++ * Ignore xoffset and yoffset update,
++ * because pan display handles this case.
++ */
++ mxc_fbi->cur_var.xoffset = fbi->var.xoffset;
++ mxc_fbi->cur_var.yoffset = fbi->var.yoffset;
++
++ return !!memcmp(&mxc_fbi->cur_var, &fbi->var,
++ sizeof(struct fb_var_screeninfo));
++}
++
++static struct fb_videomode *mxc_match_mode(const struct fb_var_screeninfo *var,
++ struct list_head *head)
++{
++ struct list_head *pos;
++ struct fb_modelist *modelist;
++ struct fb_videomode *m, mode;
++
++ fb_var_to_videomode(&mode, var);
++ list_for_each(pos, head) {
++ modelist = list_entry(pos, struct fb_modelist, list);
++ m = &modelist->mode;
++
++ mode.sync &= ~FB_MXC_SYNC_MASK;
++ mode.sync |= m->sync & FB_MXC_SYNC_MASK;
++
++ if (fb_mode_is_equal(m, &mode))
++ return m;
++ }
++
++ return NULL;
++}
++
++/*
++ * Set framebuffer parameters and change the operating mode.
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_set_par(struct fb_info *fbi)
++{
++ int retval = 0;
++ u32 mem_len, alpha_mem_len;
++ ipu_di_signal_cfg_t sig_cfg;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ int16_t ov_pos_x = 0, ov_pos_y = 0;
++ int ov_pos_ret = 0;
++ struct mxcfb_info *mxc_fbi_fg = NULL;
++ bool ovfbi_enable = false;
++
++ if (ipu_ch_param_bad_alpha_pos(fbi_to_pixfmt(fbi)) &&
++ mxc_fbi->alpha_chan_en) {
++ dev_err(fbi->device, "Bad pixel format for "
++ "graphics plane fb\n");
++ return -EINVAL;
++ }
++
++ if (mxc_fbi->ovfbi)
++ mxc_fbi_fg = (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++
++ if (mxc_fbi->ovfbi && mxc_fbi_fg)
++ if (mxc_fbi_fg->next_blank == FB_BLANK_UNBLANK)
++ ovfbi_enable = true;
++
++ if (!mxcfb_need_to_set_par(fbi))
++ return 0;
++
++ dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
++
++ if (fbi->var.xres == 0 || fbi->var.yres == 0)
++ return 0;
++
++ if (ovfbi_enable) {
++ ov_pos_ret = ipu_disp_get_window_pos(
++ mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch,
++ &ov_pos_x, &ov_pos_y);
++ if (ov_pos_ret < 0)
++ dev_err(fbi->device, "Get overlay pos failed, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++
++ ipu_clear_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_irq);
++ ipu_disable_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_nf_irq);
++ ipu_disable_irq(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch_nf_irq);
++ ipu_disable_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++ }
++
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++
++ /*
++ * Disable IPU hsp clock if it is enabled for an
++ * additional time in ipu common driver.
++ */
++ if (mxc_fbi->first_set_par && mxc_fbi->late_init)
++ ipu_disable_hsp_clk(mxc_fbi->ipu);
++
++ mxcfb_set_fix(fbi);
++
++ mem_len = ALIGN(fbi->var.yres_virtual, 16) * fbi->fix.line_length;
++ if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
++ if (fbi->fix.smem_start)
++ mxcfb_unmap_video_memory(fbi);
++
++ if (mxcfb_map_video_memory(fbi) < 0)
++ return -ENOMEM;
++ }
++
++ if (mxc_fbi->first_set_par) {
++ /*
++ * Clear the screen in case uboot fb pixel format is not
++ * the same to kernel fb pixel format.
++ */
++ if (mxc_fbi->late_init)
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ mxc_fbi->first_set_par = false;
++ }
++
++ if (mxc_fbi->alpha_chan_en) {
++ alpha_mem_len = fbi->var.xres * fbi->var.yres;
++ if ((!mxc_fbi->alpha_phy_addr0 && !mxc_fbi->alpha_phy_addr1) ||
++ (alpha_mem_len > mxc_fbi->alpha_mem_len)) {
++ if (mxc_fbi->alpha_phy_addr0)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr0,
++ mxc_fbi->alpha_phy_addr0);
++ if (mxc_fbi->alpha_phy_addr1)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr1,
++ mxc_fbi->alpha_phy_addr1);
++
++ mxc_fbi->alpha_virt_addr0 =
++ dma_alloc_coherent(fbi->device,
++ alpha_mem_len,
++ &mxc_fbi->alpha_phy_addr0,
++ GFP_DMA | GFP_KERNEL);
++
++ mxc_fbi->alpha_virt_addr1 =
++ dma_alloc_coherent(fbi->device,
++ alpha_mem_len,
++ &mxc_fbi->alpha_phy_addr1,
++ GFP_DMA | GFP_KERNEL);
++ if (mxc_fbi->alpha_virt_addr0 == NULL ||
++ mxc_fbi->alpha_virt_addr1 == NULL) {
++ dev_err(fbi->device, "mxcfb: dma alloc for"
++ " alpha buffer failed.\n");
++ if (mxc_fbi->alpha_virt_addr0)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr0,
++ mxc_fbi->alpha_phy_addr0);
++ if (mxc_fbi->alpha_virt_addr1)
++ dma_free_coherent(fbi->device,
++ mxc_fbi->alpha_mem_len,
++ mxc_fbi->alpha_virt_addr1,
++ mxc_fbi->alpha_phy_addr1);
++ return -ENOMEM;
++ }
++ mxc_fbi->alpha_mem_len = alpha_mem_len;
++ }
++ }
++
++ if (mxc_fbi->next_blank != FB_BLANK_UNBLANK)
++ return retval;
++
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->setup) {
++ retval = mxc_fbi->dispdrv->drv->setup(mxc_fbi->dispdrv, fbi);
++ if (retval < 0) {
++ dev_err(fbi->device, "setup error, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++ return -EINVAL;
++ }
++ }
++
++ _setup_disp_channel1(fbi);
++ if (ovfbi_enable)
++ _setup_disp_channel1(mxc_fbi->ovfbi);
++
++ if (!mxc_fbi->overlay) {
++ uint32_t out_pixel_fmt;
++ struct fb_videomode *sync_mode;
++
++ memset(&sig_cfg, 0, sizeof(sig_cfg));
++ if (fbi->var.vmode & FB_VMODE_INTERLACED)
++ sig_cfg.interlaced = true;
++ out_pixel_fmt = mxc_fbi->ipu_di_pix_fmt;
++ if (fbi->var.vmode & FB_VMODE_ODD_FLD_FIRST) /* PAL */
++ sig_cfg.odd_field_first = true;
++ if (mxc_fbi->ipu_int_clk)
++ sig_cfg.int_clk = true;
++ if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
++ sig_cfg.Hsync_pol = true;
++ if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
++ sig_cfg.Vsync_pol = true;
++
++ /*
++ * Try to find matching all parameters, except
++ * FB_MXC_SYNC_MASK bits in the .sync field.
++ */
++ sync_mode = mxc_match_mode(&fbi->var, &fbi->modelist);
++ /*
++ * If entry exists in the mode list and FB_MXC_SYNC_MASK
++ * bits are empty in the fbi->var.sync (most probably cleared
++ * by the user space application) then copy it from the found
++ * mode list entry.
++ */
++ if (sync_mode && !(fbi->var.sync & FB_MXC_SYNC_MASK))
++ fbi->var.sync = sync_mode->sync;
++
++ if (!(fbi->var.sync & FB_SYNC_CLK_LAT_FALL))
++ sig_cfg.clk_pol = true;
++ if (fbi->var.sync & FB_SYNC_DATA_INVERT)
++ sig_cfg.data_pol = true;
++ if (!(fbi->var.sync & FB_SYNC_OE_LOW_ACT))
++ sig_cfg.enable_pol = true;
++ if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
++ sig_cfg.clkidle_en = true;
++
++ dev_dbg(fbi->device, "pixclock = %ul Hz\n",
++ (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
++
++ if (ipu_init_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di,
++ (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
++ fbi->var.xres, fbi->var.yres,
++ out_pixel_fmt,
++ fbi->var.left_margin,
++ fbi->var.hsync_len,
++ fbi->var.right_margin,
++ fbi->var.upper_margin,
++ fbi->var.vsync_len,
++ fbi->var.lower_margin,
++ 0, sig_cfg) != 0) {
++ dev_err(fbi->device,
++ "mxcfb: Error initializing panel.\n");
++ return -EINVAL;
++ }
++
++ fbi->mode =
++ (struct fb_videomode *)fb_match_mode(&fbi->var,
++ &fbi->modelist);
++
++ ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, 0, 0);
++ }
++
++ retval = _setup_disp_channel2(fbi);
++ if (retval) {
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ return retval;
++ }
++
++ if (ovfbi_enable) {
++ if (ov_pos_ret >= 0)
++ ipu_disp_set_window_pos(
++ mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch,
++ ov_pos_x, ov_pos_y);
++ retval = _setup_disp_channel2(mxc_fbi->ovfbi);
++ if (retval) {
++ ipu_uninit_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ return retval;
++ }
++ }
++
++ ipu_enable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ if (ovfbi_enable)
++ ipu_enable_channel(mxc_fbi_fg->ipu, mxc_fbi_fg->ipu_ch);
++
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->enable) {
++ retval = mxc_fbi->dispdrv->drv->enable(mxc_fbi->dispdrv, fbi);
++ if (retval < 0) {
++ dev_err(fbi->device, "enable error, dispdrv:%s.\n",
++ mxc_fbi->dispdrv->drv->name);
++ return -EINVAL;
++ }
++ }
++
++ mxc_fbi->cur_var = fbi->var;
++
++ return retval;
++}
++
++static int _swap_channels(struct fb_info *fbi_from,
++ struct fb_info *fbi_to, bool both_on)
++{
++ int retval, tmp;
++ ipu_channel_t old_ch;
++ struct fb_info *ovfbi;
++ struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
++ struct mxcfb_info *mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
++
++ if (both_on) {
++ ipu_disable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch, true);
++ ipu_uninit_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
++ }
++
++ /* switch the mxc fbi parameters */
++ old_ch = mxc_fbi_from->ipu_ch;
++ mxc_fbi_from->ipu_ch = mxc_fbi_to->ipu_ch;
++ mxc_fbi_to->ipu_ch = old_ch;
++ tmp = mxc_fbi_from->ipu_ch_irq;
++ mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
++ mxc_fbi_to->ipu_ch_irq = tmp;
++ tmp = mxc_fbi_from->ipu_ch_nf_irq;
++ mxc_fbi_from->ipu_ch_nf_irq = mxc_fbi_to->ipu_ch_nf_irq;
++ mxc_fbi_to->ipu_ch_nf_irq = tmp;
++ ovfbi = mxc_fbi_from->ovfbi;
++ mxc_fbi_from->ovfbi = mxc_fbi_to->ovfbi;
++ mxc_fbi_to->ovfbi = ovfbi;
++
++ _setup_disp_channel1(fbi_from);
++ retval = _setup_disp_channel2(fbi_from);
++ if (retval)
++ return retval;
++
++ /* switch between dp and dc, disable old idmac, enable new idmac */
++ retval = ipu_swap_channel(mxc_fbi_from->ipu, old_ch, mxc_fbi_from->ipu_ch);
++ ipu_uninit_channel(mxc_fbi_from->ipu, old_ch);
++
++ if (both_on) {
++ _setup_disp_channel1(fbi_to);
++ retval = _setup_disp_channel2(fbi_to);
++ if (retval)
++ return retval;
++ ipu_enable_channel(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch);
++ }
++
++ return retval;
++}
++
++static int swap_channels(struct fb_info *fbi_from)
++{
++ int i;
++ int swap_mode;
++ ipu_channel_t ch_to;
++ struct mxcfb_info *mxc_fbi_from = (struct mxcfb_info *)fbi_from->par;
++ struct fb_info *fbi_to = NULL;
++ struct mxcfb_info *mxc_fbi_to;
++
++ /* what's the target channel? */
++ if (mxc_fbi_from->ipu_ch == MEM_BG_SYNC)
++ ch_to = MEM_DC_SYNC;
++ else
++ ch_to = MEM_BG_SYNC;
++
++ fbi_to = found_registered_fb(ch_to, mxc_fbi_from->ipu_id);
++ if (!fbi_to)
++ return -1;
++ mxc_fbi_to = (struct mxcfb_info *)fbi_to->par;
++
++ ipu_clear_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
++ ipu_clear_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
++ ipu_free_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq, fbi_from);
++ ipu_free_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq, fbi_to);
++ ipu_clear_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq);
++ ipu_clear_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq);
++ ipu_free_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq, fbi_from);
++ ipu_free_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq, fbi_to);
++
++ if (mxc_fbi_from->cur_blank == FB_BLANK_UNBLANK) {
++ if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
++ swap_mode = BOTH_ON;
++ else
++ swap_mode = SRC_ON;
++ } else {
++ if (mxc_fbi_to->cur_blank == FB_BLANK_UNBLANK)
++ swap_mode = TGT_ON;
++ else
++ swap_mode = BOTH_OFF;
++ }
++
++ switch (swap_mode) {
++ case BOTH_ON:
++ /* disable target->switch src->enable target */
++ _swap_channels(fbi_from, fbi_to, true);
++ break;
++ case SRC_ON:
++ /* just switch src */
++ _swap_channels(fbi_from, fbi_to, false);
++ break;
++ case TGT_ON:
++ /* just switch target */
++ _swap_channels(fbi_to, fbi_from, false);
++ break;
++ case BOTH_OFF:
++ /* switch directly, no more need to do */
++ mxc_fbi_to->ipu_ch = mxc_fbi_from->ipu_ch;
++ mxc_fbi_from->ipu_ch = ch_to;
++ i = mxc_fbi_from->ipu_ch_irq;
++ mxc_fbi_from->ipu_ch_irq = mxc_fbi_to->ipu_ch_irq;
++ mxc_fbi_to->ipu_ch_irq = i;
++ i = mxc_fbi_from->ipu_ch_nf_irq;
++ mxc_fbi_from->ipu_ch_nf_irq = mxc_fbi_to->ipu_ch_nf_irq;
++ mxc_fbi_to->ipu_ch_nf_irq = i;
++ break;
++ default:
++ break;
++ }
++
++ if (ipu_request_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_from) != 0) {
++ dev_err(fbi_from->device, "Error registering irq %d\n",
++ mxc_fbi_from->ipu_ch_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_irq);
++ if (ipu_request_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_to) != 0) {
++ dev_err(fbi_to->device, "Error registering irq %d\n",
++ mxc_fbi_to->ipu_ch_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_irq);
++ if (ipu_request_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_from) != 0) {
++ dev_err(fbi_from->device, "Error registering irq %d\n",
++ mxc_fbi_from->ipu_ch_nf_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_from->ipu, mxc_fbi_from->ipu_ch_nf_irq);
++ if (ipu_request_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi_to) != 0) {
++ dev_err(fbi_to->device, "Error registering irq %d\n",
++ mxc_fbi_to->ipu_ch_nf_irq);
++ return -EBUSY;
++ }
++ ipu_disable_irq(mxc_fbi_to->ipu, mxc_fbi_to->ipu_ch_nf_irq);
++
++ return 0;
++}
++
++/*
++ * Check framebuffer variable parameters and adjust to valid values.
++ *
++ * @param var framebuffer variable parameters
++ *
++ * @param info framebuffer information pointer
++ */
++static int mxcfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ u32 vtotal;
++ u32 htotal;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
++
++
++ if (var->xres == 0 || var->yres == 0)
++ return 0;
++
++ /* fg should not bigger than bg */
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ struct fb_info *fbi_tmp;
++ int bg_xres = 0, bg_yres = 0;
++ int16_t pos_x, pos_y;
++
++ bg_xres = var->xres;
++ bg_yres = var->yres;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp) {
++ bg_xres = fbi_tmp->var.xres;
++ bg_yres = fbi_tmp->var.yres;
++ }
++
++ ipu_disp_get_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch, &pos_x, &pos_y);
++
++ if ((var->xres + pos_x) > bg_xres)
++ var->xres = bg_xres - pos_x;
++ if ((var->yres + pos_y) > bg_yres)
++ var->yres = bg_yres - pos_y;
++ }
++
++ if (var->rotate > IPU_ROTATE_VERT_FLIP)
++ var->rotate = IPU_ROTATE_NONE;
++
++ if (var->xres_virtual < var->xres)
++ var->xres_virtual = var->xres;
++
++ if (var->yres_virtual < var->yres)
++ var->yres_virtual = var->yres * 3;
++
++ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
++ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) &&
++ (var->bits_per_pixel != 8))
++ var->bits_per_pixel = 16;
++
++ if (check_var_pixfmt(var))
++ /* Fall back to default */
++ bpp_to_var(var->bits_per_pixel, var);
++
++ if (var->pixclock < 1000) {
++ htotal = var->xres + var->right_margin + var->hsync_len +
++ var->left_margin;
++ vtotal = var->yres + var->lower_margin + var->vsync_len +
++ var->upper_margin;
++ var->pixclock = (vtotal * htotal * 6UL) / 100UL;
++ var->pixclock = KHZ2PICOS(var->pixclock);
++ dev_dbg(info->device,
++ "pixclock set for 60Hz refresh = %u ps\n",
++ var->pixclock);
++ }
++
++ var->height = -1;
++ var->width = -1;
++ var->grayscale = 0;
++
++ return 0;
++}
++
++static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf)
++{
++ chan &= 0xffff;
++ chan >>= 16 - bf->length;
++ return chan << bf->offset;
++}
++
++static int mxcfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
++ u_int trans, struct fb_info *fbi)
++{
++ unsigned int val;
++ int ret = 1;
++
++ /*
++ * If greyscale is true, then we convert the RGB value
++ * to greyscale no matter what visual we are using.
++ */
++ if (fbi->var.grayscale)
++ red = green = blue = (19595 * red + 38470 * green +
++ 7471 * blue) >> 16;
++ switch (fbi->fix.visual) {
++ case FB_VISUAL_TRUECOLOR:
++ /*
++ * 16-bit True Colour. We encode the RGB value
++ * according to the RGB bitfield information.
++ */
++ if (regno < 16) {
++ u32 *pal = fbi->pseudo_palette;
++
++ val = _chan_to_field(red, &fbi->var.red);
++ val |= _chan_to_field(green, &fbi->var.green);
++ val |= _chan_to_field(blue, &fbi->var.blue);
++
++ pal[regno] = val;
++ ret = 0;
++ }
++ break;
++
++ case FB_VISUAL_STATIC_PSEUDOCOLOR:
++ case FB_VISUAL_PSEUDOCOLOR:
++ break;
++ }
++
++ return ret;
++}
++
++/*
++ * Function to handle custom ioctls for MXC framebuffer.
++ *
++ * @param inode inode struct
++ *
++ * @param file file struct
++ *
++ * @param cmd Ioctl command to handle
++ *
++ * @param arg User pointer to command arguments
++ *
++ * @param fbi framebuffer information pointer
++ */
++static int mxcfb_ioctl(struct fb_info *fbi, unsigned int cmd, unsigned long arg)
++{
++ int retval = 0;
++ int __user *argp = (void __user *)arg;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ switch (cmd) {
++ case MXCFB_SET_GBL_ALPHA:
++ {
++ struct mxcfb_gbl_alpha ga;
++
++ if (copy_from_user(&ga, (void *)arg, sizeof(ga))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (ipu_disp_set_global_alpha(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ (bool)ga.enable,
++ ga.alpha)) {
++ retval = -EINVAL;
++ break;
++ }
++
++ if (ga.enable)
++ mxc_fbi->alpha_chan_en = false;
++
++ if (ga.enable)
++ dev_dbg(fbi->device,
++ "Set global alpha of %s to %d\n",
++ fbi->fix.id, ga.alpha);
++ break;
++ }
++ case MXCFB_SET_LOC_ALPHA:
++ {
++ struct mxcfb_loc_alpha la;
++ bool bad_pixfmt =
++ ipu_ch_param_bad_alpha_pos(fbi_to_pixfmt(fbi));
++
++ if (copy_from_user(&la, (void *)arg, sizeof(la))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (la.enable && !la.alpha_in_pixel) {
++ struct fb_info *fbi_tmp;
++ ipu_channel_t ipu_ch;
++
++ if (bad_pixfmt) {
++ dev_err(fbi->device, "Bad pixel format "
++ "for graphics plane fb\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ mxc_fbi->alpha_chan_en = true;
++
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
++ ipu_ch = MEM_BG_SYNC;
++ else if (mxc_fbi->ipu_ch == MEM_BG_SYNC)
++ ipu_ch = MEM_FG_SYNC;
++ else {
++ retval = -EINVAL;
++ break;
++ }
++
++ fbi_tmp = found_registered_fb(ipu_ch, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ ((struct mxcfb_info *)(fbi_tmp->par))->alpha_chan_en = false;
++ } else
++ mxc_fbi->alpha_chan_en = false;
++
++ if (ipu_disp_set_global_alpha(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ !(bool)la.enable, 0)) {
++ retval = -EINVAL;
++ break;
++ }
++
++ fbi->var.activate = (fbi->var.activate & ~FB_ACTIVATE_MASK) |
++ FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE;
++ mxcfb_set_par(fbi);
++
++ la.alpha_phy_addr0 = mxc_fbi->alpha_phy_addr0;
++ la.alpha_phy_addr1 = mxc_fbi->alpha_phy_addr1;
++ if (copy_to_user((void *)arg, &la, sizeof(la))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ if (la.enable)
++ dev_dbg(fbi->device,
++ "Enable DP local alpha for %s\n",
++ fbi->fix.id);
++ break;
++ }
++ case MXCFB_SET_LOC_ALP_BUF:
++ {
++ unsigned long base;
++ uint32_t ipu_alp_ch_irq;
++
++ if (!(((mxc_fbi->ipu_ch == MEM_FG_SYNC) ||
++ (mxc_fbi->ipu_ch == MEM_BG_SYNC)) &&
++ (mxc_fbi->alpha_chan_en))) {
++ dev_err(fbi->device,
++ "Should use background or overlay "
++ "framebuffer to set the alpha buffer "
++ "number\n");
++ return -EINVAL;
++ }
++
++ if (get_user(base, argp))
++ return -EFAULT;
++
++ if (base != mxc_fbi->alpha_phy_addr0 &&
++ base != mxc_fbi->alpha_phy_addr1) {
++ dev_err(fbi->device,
++ "Wrong alpha buffer physical address "
++ "%lu\n", base);
++ return -EINVAL;
++ }
++
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC)
++ ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
++ else
++ ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
++
++ retval = wait_for_completion_timeout(
++ &mxc_fbi->alpha_flip_complete, HZ/2);
++ if (retval == 0) {
++ dev_err(fbi->device, "timeout when waiting for alpha flip irq\n");
++ retval = -ETIMEDOUT;
++ break;
++ }
++
++ mxc_fbi->cur_ipu_alpha_buf =
++ !mxc_fbi->cur_ipu_alpha_buf;
++ if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->
++ cur_ipu_alpha_buf,
++ base) == 0) {
++ ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf);
++ ipu_clear_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, ipu_alp_ch_irq);
++ } else {
++ dev_err(fbi->device,
++ "Error updating %s SDC alpha buf %d "
++ "to address=0x%08lX\n",
++ fbi->fix.id,
++ mxc_fbi->cur_ipu_alpha_buf, base);
++ }
++ break;
++ }
++ case MXCFB_SET_CLR_KEY:
++ {
++ struct mxcfb_color_key key;
++ if (copy_from_user(&key, (void *)arg, sizeof(key))) {
++ retval = -EFAULT;
++ break;
++ }
++ retval = ipu_disp_set_color_key(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ key.enable,
++ key.color_key);
++ dev_dbg(fbi->device, "Set color key to 0x%08X\n",
++ key.color_key);
++ break;
++ }
++ case MXCFB_SET_GAMMA:
++ {
++ struct mxcfb_gamma gamma;
++ if (copy_from_user(&gamma, (void *)arg, sizeof(gamma))) {
++ retval = -EFAULT;
++ break;
++ }
++ retval = ipu_disp_set_gamma_correction(mxc_fbi->ipu,
++ mxc_fbi->ipu_ch,
++ gamma.enable,
++ gamma.constk,
++ gamma.slopek);
++ break;
++ }
++ case MXCFB_WAIT_FOR_VSYNC:
++ {
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ /* BG should poweron */
++ struct mxcfb_info *bg_mxcfbi = NULL;
++ struct fb_info *fbi_tmp;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
++
++ if (!bg_mxcfbi) {
++ retval = -EINVAL;
++ break;
++ }
++ if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK) {
++ retval = -EINVAL;
++ break;
++ }
++ }
++ if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK) {
++ retval = -EINVAL;
++ break;
++ }
++
++ init_completion(&mxc_fbi->vsync_complete);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq);
++ retval = wait_for_completion_interruptible_timeout(
++ &mxc_fbi->vsync_complete, 1 * HZ);
++ if (retval == 0) {
++ dev_err(fbi->device,
++ "MXCFB_WAIT_FOR_VSYNC: timeout %d\n",
++ retval);
++ retval = -ETIME;
++ } else if (retval > 0) {
++ retval = 0;
++ }
++ break;
++ }
++ case FBIO_ALLOC:
++ {
++ int size;
++ struct mxcfb_alloc_list *mem;
++
++ mem = kzalloc(sizeof(*mem), GFP_KERNEL);
++ if (mem == NULL)
++ return -ENOMEM;
++
++ if (get_user(size, argp))
++ return -EFAULT;
++
++ mem->size = PAGE_ALIGN(size);
++
++ mem->cpu_addr = dma_alloc_coherent(fbi->device, size,
++ &mem->phy_addr,
++ GFP_KERNEL);
++ if (mem->cpu_addr == NULL) {
++ kfree(mem);
++ return -ENOMEM;
++ }
++
++ list_add(&mem->list, &fb_alloc_list);
++
++ dev_dbg(fbi->device, "allocated %d bytes @ 0x%08X\n",
++ mem->size, mem->phy_addr);
++
++ if (put_user(mem->phy_addr, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case FBIO_FREE:
++ {
++ unsigned long offset;
++ struct mxcfb_alloc_list *mem;
++
++ if (get_user(offset, argp))
++ return -EFAULT;
++
++ retval = -EINVAL;
++ list_for_each_entry(mem, &fb_alloc_list, list) {
++ if (mem->phy_addr == offset) {
++ list_del(&mem->list);
++ dma_free_coherent(fbi->device,
++ mem->size,
++ mem->cpu_addr,
++ mem->phy_addr);
++ kfree(mem);
++ retval = 0;
++ break;
++ }
++ }
++
++ break;
++ }
++ case MXCFB_SET_OVERLAY_POS:
++ {
++ struct mxcfb_pos pos;
++ struct fb_info *bg_fbi = NULL;
++ struct mxcfb_info *bg_mxcfbi = NULL;
++
++ if (mxc_fbi->ipu_ch != MEM_FG_SYNC) {
++ dev_err(fbi->device, "Should use the overlay "
++ "framebuffer to set the position of "
++ "the overlay window\n");
++ retval = -EINVAL;
++ break;
++ }
++
++ if (copy_from_user(&pos, (void *)arg, sizeof(pos))) {
++ retval = -EFAULT;
++ break;
++ }
++
++ bg_fbi = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (bg_fbi)
++ bg_mxcfbi = ((struct mxcfb_info *)(bg_fbi->par));
++
++ if (bg_fbi == NULL) {
++ dev_err(fbi->device, "Cannot find the "
++ "background framebuffer\n");
++ retval = -ENOENT;
++ break;
++ }
++
++ /* if fb is unblank, check if the pos fit the display */
++ if (mxc_fbi->cur_blank == FB_BLANK_UNBLANK) {
++ if (fbi->var.xres + pos.x > bg_fbi->var.xres) {
++ if (bg_fbi->var.xres < fbi->var.xres)
++ pos.x = 0;
++ else
++ pos.x = bg_fbi->var.xres - fbi->var.xres;
++ }
++ if (fbi->var.yres + pos.y > bg_fbi->var.yres) {
++ if (bg_fbi->var.yres < fbi->var.yres)
++ pos.y = 0;
++ else
++ pos.y = bg_fbi->var.yres - fbi->var.yres;
++ }
++ }
++
++ retval = ipu_disp_set_window_pos(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ pos.x, pos.y);
++
++ if (copy_to_user((void *)arg, &pos, sizeof(pos))) {
++ retval = -EFAULT;
++ break;
++ }
++ break;
++ }
++ case MXCFB_GET_FB_IPU_CHAN:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_ch, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_DIFMT:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_di_pix_fmt, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_FB_IPU_DI:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->ipu_di, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_GET_FB_BLANK:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (put_user(mxc_fbi->cur_blank, argp))
++ return -EFAULT;
++ break;
++ }
++ case MXCFB_SET_DIFMT:
++ {
++ struct mxcfb_info *mxc_fbi =
++ (struct mxcfb_info *)fbi->par;
++
++ if (get_user(mxc_fbi->ipu_di_pix_fmt, argp))
++ return -EFAULT;
++
++ break;
++ }
++ case MXCFB_CSC_UPDATE:
++ {
++ struct mxcfb_csc_matrix csc;
++
++ if (copy_from_user(&csc, (void *) arg, sizeof(csc)))
++ return -EFAULT;
++
++ if ((mxc_fbi->ipu_ch != MEM_FG_SYNC) &&
++ (mxc_fbi->ipu_ch != MEM_BG_SYNC) &&
++ (mxc_fbi->ipu_ch != MEM_BG_ASYNC0))
++ return -EFAULT;
++ ipu_set_csc_coefficients(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ csc.param);
++ break;
++ }
++ default:
++ retval = -EINVAL;
++ }
++ return retval;
++}
++
++/*
++ * mxcfb_blank():
++ * Blank the display.
++ */
++int mxcfb_blank(int blank, struct fb_info *info)
++{
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par;
++ int ret = 0;
++
++ dev_dbg(info->device, "blank = %d\n", blank);
++
++ if (mxc_fbi->cur_blank == blank)
++ return 0;
++
++ mxc_fbi->next_blank = blank;
++
++ switch (blank) {
++ case FB_BLANK_POWERDOWN:
++ case FB_BLANK_VSYNC_SUSPEND:
++ case FB_BLANK_HSYNC_SUSPEND:
++ case FB_BLANK_NORMAL:
++ if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->disable)
++ mxc_fbi->dispdrv->drv->disable(mxc_fbi->dispdrv, info);
++ ipu_disable_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch, true);
++ if (mxc_fbi->ipu_di >= 0)
++ ipu_uninit_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di);
++ ipu_uninit_channel(mxc_fbi->ipu, mxc_fbi->ipu_ch);
++ break;
++ case FB_BLANK_UNBLANK:
++ info->var.activate = (info->var.activate & ~FB_ACTIVATE_MASK) |
++ FB_ACTIVATE_NOW | FB_ACTIVATE_FORCE;
++ ret = mxcfb_set_par(info);
++ break;
++ }
++ if (!ret)
++ mxc_fbi->cur_blank = blank;
++ return ret;
++}
++EXPORT_SYMBOL(mxcfb_blank);
++
++/*
++ * Pan or Wrap the Display
++ *
++ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
++ *
++ * @param var Variable screen buffer information
++ * @param info Framebuffer information pointer
++ */
++static int
++mxcfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)info->par,
++ *mxc_graphic_fbi = NULL;
++ u_int y_bottom;
++ unsigned int fr_xoff, fr_yoff, fr_w, fr_h;
++ unsigned long base, active_alpha_phy_addr = 0;
++ bool loc_alpha_en = false;
++ int fb_stride;
++ int i;
++ int ret;
++
++ /* no pan display during fb blank */
++ if (mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ struct mxcfb_info *bg_mxcfbi = NULL;
++ struct fb_info *fbi_tmp;
++
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxc_fbi->ipu_id);
++ if (fbi_tmp)
++ bg_mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
++ if (!bg_mxcfbi)
++ return -EINVAL;
++ if (bg_mxcfbi->cur_blank != FB_BLANK_UNBLANK)
++ return -EINVAL;
++ }
++ if (mxc_fbi->cur_blank != FB_BLANK_UNBLANK)
++ return -EINVAL;
++
++ y_bottom = var->yoffset;
++
++ if (y_bottom > info->var.yres_virtual)
++ return -EINVAL;
++
++ switch (fbi_to_pixfmt(info)) {
++ case IPU_PIX_FMT_YUV420P2:
++ case IPU_PIX_FMT_YVU420P:
++ case IPU_PIX_FMT_NV12:
++ case IPU_PIX_FMT_YUV422P:
++ case IPU_PIX_FMT_YVU422P:
++ case IPU_PIX_FMT_YUV420P:
++ case IPU_PIX_FMT_YUV444P:
++ fb_stride = info->var.xres_virtual;
++ break;
++ default:
++ fb_stride = info->fix.line_length;
++ }
++
++ base = info->fix.smem_start;
++ fr_xoff = var->xoffset;
++ fr_w = info->var.xres_virtual;
++ if (!(var->vmode & FB_VMODE_YWRAP)) {
++ dev_dbg(info->device, "Y wrap disabled\n");
++ fr_yoff = var->yoffset % info->var.yres;
++ fr_h = info->var.yres;
++ base += info->fix.line_length * info->var.yres *
++ (var->yoffset / info->var.yres);
++ } else {
++ dev_dbg(info->device, "Y wrap enabled\n");
++ fr_yoff = var->yoffset;
++ fr_h = info->var.yres_virtual;
++ }
++ base += fr_yoff * fb_stride + fr_xoff;
++
++ /* Check if DP local alpha is enabled and find the graphic fb */
++ if (mxc_fbi->ipu_ch == MEM_BG_SYNC || mxc_fbi->ipu_ch == MEM_FG_SYNC) {
++ for (i = 0; i < num_registered_fb; i++) {
++ char bg_id[] = "DISP3 BG";
++ char fg_id[] = "DISP3 FG";
++ char *idstr = registered_fb[i]->fix.id;
++ bg_id[4] += mxc_fbi->ipu_id;
++ fg_id[4] += mxc_fbi->ipu_id;
++ if ((strcmp(idstr, bg_id) == 0 ||
++ strcmp(idstr, fg_id) == 0) &&
++ ((struct mxcfb_info *)
++ (registered_fb[i]->par))->alpha_chan_en) {
++ loc_alpha_en = true;
++ mxc_graphic_fbi = (struct mxcfb_info *)
++ (registered_fb[i]->par);
++ active_alpha_phy_addr =
++ mxc_fbi->cur_ipu_alpha_buf ?
++ mxc_graphic_fbi->alpha_phy_addr1 :
++ mxc_graphic_fbi->alpha_phy_addr0;
++ dev_dbg(info->device, "Updating SDC alpha "
++ "buf %d address=0x%08lX\n",
++ !mxc_fbi->cur_ipu_alpha_buf,
++ active_alpha_phy_addr);
++ break;
++ }
++ }
++ }
++
++ ret = wait_for_completion_timeout(&mxc_fbi->flip_complete, HZ/2);
++ if (ret == 0) {
++ dev_err(info->device, "timeout when waiting for flip irq\n");
++ return -ETIMEDOUT;
++ }
++
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
++
++ dev_dbg(info->device, "Updating SDC %s buf %d address=0x%08lX\n",
++ info->fix.id, mxc_fbi->cur_ipu_buf, base);
++
++ if (ipu_update_channel_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ mxc_fbi->cur_ipu_buf, base) == 0) {
++ /* Update the DP local alpha buffer only for graphic plane */
++ if (loc_alpha_en && mxc_graphic_fbi == mxc_fbi &&
++ ipu_update_channel_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf,
++ active_alpha_phy_addr) == 0) {
++ ipu_select_buffer(mxc_graphic_fbi->ipu, mxc_graphic_fbi->ipu_ch,
++ IPU_ALPHA_IN_BUFFER,
++ mxc_fbi->cur_ipu_alpha_buf);
++ }
++
++ /* update u/v offset */
++ ipu_update_channel_offset(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER,
++ fbi_to_pixfmt(info),
++ fr_w,
++ fr_h,
++ fr_w,
++ 0, 0,
++ fr_yoff,
++ fr_xoff);
++
++ ipu_select_buffer(mxc_fbi->ipu, mxc_fbi->ipu_ch, IPU_INPUT_BUFFER,
++ mxc_fbi->cur_ipu_buf);
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ } else {
++ dev_err(info->device,
++ "Error updating SDC buf %d to address=0x%08lX, "
++ "current buf %d, buf0 ready %d, buf1 ready %d, "
++ "buf2 ready %d\n", mxc_fbi->cur_ipu_buf, base,
++ ipu_get_cur_buffer_idx(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 0),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 1),
++ ipu_check_buffer_ready(mxc_fbi->ipu, mxc_fbi->ipu_ch,
++ IPU_INPUT_BUFFER, 2));
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ ++mxc_fbi->cur_ipu_buf;
++ mxc_fbi->cur_ipu_buf %= 3;
++ mxc_fbi->cur_ipu_alpha_buf = !mxc_fbi->cur_ipu_alpha_buf;
++ ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ ipu_enable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq);
++ return -EBUSY;
++ }
++
++ dev_dbg(info->device, "Update complete\n");
++
++ info->var.yoffset = var->yoffset;
++
++ return 0;
++}
++
++/*
++ * Function to handle custom mmap for MXC framebuffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @param vma Pointer to vm_area_struct
++ */
++static int mxcfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
++{
++ bool found = false;
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++ struct mxcfb_alloc_list *mem;
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ if (offset < fbi->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = fbi->fix.smem_len - offset;
++ vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else if ((vma->vm_pgoff ==
++ (mxc_fbi->alpha_phy_addr0 >> PAGE_SHIFT)) ||
++ (vma->vm_pgoff ==
++ (mxc_fbi->alpha_phy_addr1 >> PAGE_SHIFT))) {
++ len = mxc_fbi->alpha_mem_len;
++ } else {
++ list_for_each_entry(mem, &fb_alloc_list, list) {
++ if (offset == mem->phy_addr) {
++ found = true;
++ len = mem->size;
++ break;
++ }
++ }
++ if (!found)
++ return -EINVAL;
++ }
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ vma->vm_flags |= VM_IO;
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(fbi->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
++ return 0;
++}
++
++/*!
++ * This structure contains the pointers to the control functions that are
++ * invoked by the core framebuffer driver to perform operations like
++ * blitting, rectangle filling, copy regions and cursor definition.
++ */
++static struct fb_ops mxcfb_ops = {
++ .owner = THIS_MODULE,
++ .fb_set_par = mxcfb_set_par,
++ .fb_check_var = mxcfb_check_var,
++ .fb_setcolreg = mxcfb_setcolreg,
++ .fb_pan_display = mxcfb_pan_display,
++ .fb_ioctl = mxcfb_ioctl,
++ .fb_mmap = mxcfb_mmap,
++ .fb_fillrect = cfb_fillrect,
++ .fb_copyarea = cfb_copyarea,
++ .fb_imageblit = cfb_imageblit,
++ .fb_blank = mxcfb_blank,
++};
++
++static irqreturn_t mxcfb_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->flip_complete);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mxcfb_nf_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->vsync_complete);
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t mxcfb_alpha_irq_handler(int irq, void *dev_id)
++{
++ struct fb_info *fbi = dev_id;
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ complete(&mxc_fbi->alpha_flip_complete);
++ return IRQ_HANDLED;
++}
++
++/*
++ * Suspends the framebuffer and blanks the screen. Power management support
++ */
++static int mxcfb_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++ int saved_blank;
++#ifdef CONFIG_FB_MXC_LOW_PWR_DISPLAY
++ void *fbmem;
++#endif
++
++ if (mxc_fbi->ovfbi) {
++ struct mxcfb_info *mxc_fbi_fg =
++ (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++
++ console_lock();
++ fb_set_suspend(mxc_fbi->ovfbi, 1);
++ saved_blank = mxc_fbi_fg->cur_blank;
++ mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
++ mxc_fbi_fg->next_blank = saved_blank;
++ console_unlock();
++ }
++
++ console_lock();
++ fb_set_suspend(fbi, 1);
++ saved_blank = mxc_fbi->cur_blank;
++ mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
++ mxc_fbi->next_blank = saved_blank;
++ console_unlock();
++
++ return 0;
++}
++
++/*
++ * Resumes the framebuffer and unblanks the screen. Power management support
++ */
++static int mxcfb_resume(struct platform_device *pdev)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
++
++ console_lock();
++ mxcfb_blank(mxc_fbi->next_blank, fbi);
++ fb_set_suspend(fbi, 0);
++ console_unlock();
++
++ if (mxc_fbi->ovfbi) {
++ struct mxcfb_info *mxc_fbi_fg =
++ (struct mxcfb_info *)mxc_fbi->ovfbi->par;
++ console_lock();
++ mxcfb_blank(mxc_fbi_fg->next_blank, mxc_fbi->ovfbi);
++ fb_set_suspend(mxc_fbi->ovfbi, 0);
++ console_unlock();
++ }
++
++ return 0;
++}
++
++/*
++ * Main framebuffer functions
++ */
++
++/*!
++ * Allocates the DRAM memory for the frame buffer. This buffer is remapped
++ * into a non-cached, non-buffered, memory region to allow palette and pixel
++ * writes to occur without flushing the cache. Once this area is remapped,
++ * all virtual memory access to the video memory should occur at the new region.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxcfb_map_video_memory(struct fb_info *fbi)
++{
++ if (fbi->fix.smem_len < ALIGN(fbi->var.yres_virtual, 16) * fbi->fix.line_length)
++ fbi->fix.smem_len = ALIGN(fbi->var.yres_virtual, 16) *
++ fbi->fix.line_length;
++
++ fbi->screen_base = dma_alloc_writecombine(fbi->device,
++ fbi->fix.smem_len,
++ (dma_addr_t *)&fbi->fix.smem_start,
++ GFP_DMA | GFP_KERNEL);
++ if (fbi->screen_base == 0) {
++ dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
++ fbi->fix.smem_len = 0;
++ fbi->fix.smem_start = 0;
++ return -EBUSY;
++ }
++
++ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
++ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
++
++ fbi->screen_size = fbi->fix.smem_len;
++
++ /* Clear the screen */
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ return 0;
++}
++
++/*!
++ * De-allocates the DRAM memory for the frame buffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxcfb_unmap_video_memory(struct fb_info *fbi)
++{
++ dma_free_writecombine(fbi->device, fbi->fix.smem_len,
++ fbi->screen_base, fbi->fix.smem_start);
++ fbi->screen_base = 0;
++ fbi->fix.smem_start = 0;
++ fbi->fix.smem_len = 0;
++ return 0;
++}
++
++/*!
++ * Initializes the framebuffer information pointer. After allocating
++ * sufficient memory for the framebuffer structure, the fields are
++ * filled with custom information passed in from the configurable
++ * structures. This includes information such as bits per pixel,
++ * color maps, screen width/height and RGBA offsets.
++ *
++ * @return Framebuffer structure initialized with our information
++ */
++static struct fb_info *mxcfb_init_fbinfo(struct device *dev, struct fb_ops *ops)
++{
++ struct fb_info *fbi;
++ struct mxcfb_info *mxcfbi;
++
++ /*
++ * Allocate sufficient memory for the fb structure
++ */
++ fbi = framebuffer_alloc(sizeof(struct mxcfb_info), dev);
++ if (!fbi)
++ return NULL;
++
++ mxcfbi = (struct mxcfb_info *)fbi->par;
++
++ fbi->var.activate = FB_ACTIVATE_NOW;
++
++ fbi->fbops = ops;
++ fbi->flags = FBINFO_FLAG_DEFAULT;
++ fbi->pseudo_palette = mxcfbi->pseudo_palette;
++
++ /*
++ * Allocate colormap
++ */
++ fb_alloc_cmap(&fbi->cmap, 16, 0);
++
++ return fbi;
++}
++
++static ssize_t show_disp_chan(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++
++ if (mxcfbi->ipu_ch == MEM_BG_SYNC)
++ return sprintf(buf, "2-layer-fb-bg\n");
++ else if (mxcfbi->ipu_ch == MEM_FG_SYNC)
++ return sprintf(buf, "2-layer-fb-fg\n");
++ else if (mxcfbi->ipu_ch == MEM_DC_SYNC)
++ return sprintf(buf, "1-layer-fb\n");
++ else
++ return sprintf(buf, "err: no display chan\n");
++}
++
++static ssize_t swap_disp_chan(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++ struct mxcfb_info *fg_mxcfbi = NULL;
++
++ console_lock();
++ /* swap only happen between DP-BG and DC, while DP-FG disable */
++ if (((mxcfbi->ipu_ch == MEM_BG_SYNC) &&
++ (strstr(buf, "1-layer-fb") != NULL)) ||
++ ((mxcfbi->ipu_ch == MEM_DC_SYNC) &&
++ (strstr(buf, "2-layer-fb-bg") != NULL))) {
++ struct fb_info *fbi_fg;
++
++ fbi_fg = found_registered_fb(MEM_FG_SYNC, mxcfbi->ipu_id);
++ if (fbi_fg)
++ fg_mxcfbi = (struct mxcfb_info *)fbi_fg->par;
++
++ if (!fg_mxcfbi ||
++ fg_mxcfbi->cur_blank == FB_BLANK_UNBLANK) {
++ dev_err(dev,
++ "Can not switch while fb2(fb-fg) is on.\n");
++ console_unlock();
++ return count;
++ }
++
++ if (swap_channels(info) < 0)
++ dev_err(dev, "Swap display channel failed.\n");
++ }
++
++ console_unlock();
++ return count;
++}
++static DEVICE_ATTR(fsl_disp_property, S_IWUSR | S_IRUGO,
++ show_disp_chan, swap_disp_chan);
++
++static ssize_t show_disp_dev(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ struct fb_info *info = dev_get_drvdata(dev);
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)info->par;
++
++ /* foreground */
++ if (mxcfbi->ipu_ch == MEM_FG_SYNC) {
++ struct fb_info *fbi_tmp;
++ fbi_tmp = found_registered_fb(MEM_BG_SYNC, mxcfbi->ipu_id);
++ if (!fbi_tmp)
++ return sprintf(buf, "overlay\n");
++ mxcfbi = ((struct mxcfb_info *)(fbi_tmp->par));
++ return sprintf(buf, "%s overlay\n", mxcfbi->dispdrv->drv->name);
++ }
++ /* background */
++ else
++ return sprintf(buf, "%s\n", mxcfbi->dispdrv->drv->name);
++}
++static DEVICE_ATTR(fsl_disp_dev_property, S_IRUGO, show_disp_dev, NULL);
++
++static int mxcfb_get_crtc(struct device *dev, struct mxcfb_info *mxcfbi,
++ enum crtc crtc)
++{
++ int i = 0;
++
++ for (; i < ARRAY_SIZE(ipu_di_crtc_maps); i++)
++ if (ipu_di_crtc_maps[i].crtc == crtc) {
++ mxcfbi->ipu_id = ipu_di_crtc_maps[i].ipu_id;
++ mxcfbi->ipu_di = ipu_di_crtc_maps[i].ipu_di;
++ return 0;
++ }
++
++ dev_err(dev, "failed to get valid crtc\n");
++ return -EINVAL;
++}
++
++static int mxcfb_dispdrv_init(struct platform_device *pdev,
++ struct fb_info *fbi)
++{
++ struct ipuv3_fb_platform_data *plat_data = pdev->dev.platform_data;
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++ struct mxc_dispdrv_setting setting;
++ char disp_dev[32], *default_dev = "lcd";
++ int ret = 0;
++
++ setting.if_fmt = plat_data->interface_pix_fmt;
++ setting.dft_mode_str = plat_data->mode_str;
++ setting.default_bpp = plat_data->default_bpp;
++ if (!setting.default_bpp)
++ setting.default_bpp = 16;
++ setting.fbi = fbi;
++ if (!strlen(plat_data->disp_dev)) {
++ memcpy(disp_dev, default_dev, strlen(default_dev));
++ disp_dev[strlen(default_dev)] = '\0';
++ } else {
++ memcpy(disp_dev, plat_data->disp_dev,
++ strlen(plat_data->disp_dev));
++ disp_dev[strlen(plat_data->disp_dev)] = '\0';
++ }
++
++ mxcfbi->dispdrv = mxc_dispdrv_gethandle(disp_dev, &setting);
++ if (IS_ERR(mxcfbi->dispdrv)) {
++ ret = PTR_ERR(mxcfbi->dispdrv);
++ dev_err(&pdev->dev, "NO mxc display driver found for %s!\n",
++ disp_dev);
++ return ret;
++ } else {
++ /* fix-up */
++ mxcfbi->ipu_di_pix_fmt = setting.if_fmt;
++ mxcfbi->default_bpp = setting.default_bpp;
++
++ ret = mxcfb_get_crtc(&pdev->dev, mxcfbi, setting.crtc);
++ if (ret)
++ return ret;
++
++ dev_dbg(&pdev->dev, "di_pixfmt:0x%x, bpp:0x%x, di:%d, ipu:%d\n",
++ setting.if_fmt, setting.default_bpp,
++ mxcfbi->ipu_di, mxcfbi->ipu_id);
++ }
++ dev_info(&pdev->dev, "registered mxc display driver %s IPU%d_DISP%d\n",
++ disp_dev, mxcfbi->ipu_id + 1, mxcfbi->ipu_di);
++
++ dev_info(&pdev->dev, "registered mxc display driver %s\n", disp_dev);
++
++ return ret;
++}
++
++/*
++ * Parse user specified options (`video=trident:')
++ * example:
++ * video=mxcfb0:dev=lcd,800x480M-16@55,if=RGB565,bpp=16,noaccel
++ * video=mxcfb0:dev=lcd,800x480M-16@55,if=RGB565,fbpix=RGB565
++ */
++static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi)
++{
++ struct ipuv3_fb_platform_data *pdata = pdev->dev.platform_data;
++ char *options, *opt, *fb_mode_str = NULL;
++ char name[] = "mxcfb0";
++ uint32_t fb_pix_fmt = 0;
++
++ name[5] += pdev->id;
++ if (fb_get_options(name, &options)) {
++ dev_err(&pdev->dev, "Can't get fb option for %s!\n", name);
++ return -ENODEV;
++ }
++
++ if (!options || !*options)
++ return 0;
++
++ while ((opt = strsep(&options, ",")) != NULL) {
++ if (!*opt)
++ continue;
++
++ if (!strncmp(opt, "dev=", 4)) {
++ memcpy(pdata->disp_dev, opt + 4, strlen(opt) - 4);
++ pdata->disp_dev[strlen(opt) - 4] = '\0';
++ } else if (!strncmp(opt, "if=", 3)) {
++ if (!strncmp(opt+3, "RGB24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(opt+3, "BGR24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(opt+3, "GBR24", 5))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(opt+3, "RGB565", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(opt+3, "RGB666", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(opt+3, "YUV444", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(opt+3, "LVDS666", 7))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(opt+3, "YUYV16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(opt+3, "UYVY16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(opt+3, "YVYU16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(opt+3, "VYUY16", 6))
++ pdata->interface_pix_fmt = IPU_PIX_FMT_VYUY;
++ } else if (!strncmp(opt, "fbpix=", 6)) {
++ if (!strncmp(opt+6, "RGB24", 5))
++ fb_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(opt+6, "BGR24", 5))
++ fb_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(opt+6, "RGB32", 5))
++ fb_pix_fmt = IPU_PIX_FMT_RGB32;
++ else if (!strncmp(opt+6, "BGR32", 5))
++ fb_pix_fmt = IPU_PIX_FMT_BGR32;
++ else if (!strncmp(opt+6, "ABGR32", 6))
++ fb_pix_fmt = IPU_PIX_FMT_ABGR32;
++ else if (!strncmp(opt+6, "RGB565", 6))
++ fb_pix_fmt = IPU_PIX_FMT_RGB565;
++
++ if (fb_pix_fmt) {
++ pixfmt_to_var(fb_pix_fmt, &fbi->var);
++ pdata->default_bpp =
++ fbi->var.bits_per_pixel;
++ }
++ } else if (!strncmp(opt, "int_clk", 7)) {
++ pdata->int_clk = true;
++ continue;
++ } else if (!strncmp(opt, "bpp=", 4)) {
++ /* bpp setting cannot overwirte fbpix setting */
++ if (fb_pix_fmt)
++ continue;
++
++ pdata->default_bpp =
++ simple_strtoul(opt + 4, NULL, 0);
++
++ fb_pix_fmt = bpp_to_pixfmt(pdata->default_bpp);
++ if (fb_pix_fmt)
++ pixfmt_to_var(fb_pix_fmt, &fbi->var);
++ } else
++ fb_mode_str = opt;
++ }
++
++ if (fb_mode_str)
++ pdata->mode_str = fb_mode_str;
++
++ return 0;
++}
++
++static int mxcfb_register(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++ struct fb_videomode m;
++ int ret = 0;
++ char bg0_id[] = "DISP3 BG";
++ char bg1_id[] = "DISP3 BG - DI1";
++ char fg_id[] = "DISP3 FG";
++
++ if (mxcfbi->ipu_di == 0) {
++ bg0_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, bg0_id);
++ } else if (mxcfbi->ipu_di == 1) {
++ bg1_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, bg1_id);
++ } else { /* Overlay */
++ fg_id[4] += mxcfbi->ipu_id;
++ strcpy(fbi->fix.id, fg_id);
++ }
++
++ mxcfb_check_var(&fbi->var, fbi);
++
++ mxcfb_set_fix(fbi);
++
++ /* Added first mode to fbi modelist. */
++ if (!fbi->modelist.next || !fbi->modelist.prev)
++ INIT_LIST_HEAD(&fbi->modelist);
++ fb_var_to_videomode(&m, &fbi->var);
++ fb_add_videomode(&m, &fbi->modelist);
++
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq,
++ mxcfb_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering EOF irq handler.\n");
++ ret = -EBUSY;
++ goto err0;
++ }
++ ipu_disable_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq);
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq,
++ mxcfb_nf_irq_handler, IPU_IRQF_ONESHOT, MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering NFACK irq handler.\n");
++ ret = -EBUSY;
++ goto err1;
++ }
++ ipu_disable_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq);
++
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ if (ipu_request_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq,
++ mxcfb_alpha_irq_handler, IPU_IRQF_ONESHOT,
++ MXCFB_NAME, fbi) != 0) {
++ dev_err(fbi->device, "Error registering alpha irq "
++ "handler.\n");
++ ret = -EBUSY;
++ goto err2;
++ }
++
++ if (!mxcfbi->late_init) {
++ fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_set_var(fbi, &fbi->var);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ if (ret < 0) {
++ dev_err(fbi->device, "Error fb_set_var ret:%d\n", ret);
++ goto err3;
++ }
++
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ ret = fb_blank(fbi, FB_BLANK_UNBLANK);
++ console_unlock();
++ if (ret < 0) {
++ dev_err(fbi->device,
++ "Error fb_blank ret:%d\n", ret);
++ goto err4;
++ }
++ }
++ } else {
++ /*
++ * Setup the channel again though bootloader
++ * has done this, then set_par() can stop the
++ * channel neatly and re-initialize it .
++ */
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ _setup_disp_channel1(fbi);
++ ipu_enable_channel(mxcfbi->ipu, mxcfbi->ipu_ch);
++ console_unlock();
++ }
++ }
++
++
++ ret = register_framebuffer(fbi);
++ if (ret < 0)
++ goto err5;
++
++ return ret;
++err5:
++ if (mxcfbi->next_blank == FB_BLANK_UNBLANK) {
++ console_lock();
++ if (!mxcfbi->late_init)
++ fb_blank(fbi, FB_BLANK_POWERDOWN);
++ else {
++ ipu_disable_channel(mxcfbi->ipu, mxcfbi->ipu_ch,
++ true);
++ ipu_uninit_channel(mxcfbi->ipu, mxcfbi->ipu_ch);
++ }
++ console_unlock();
++ }
++err4:
++err3:
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
++err2:
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq, fbi);
++err1:
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
++err0:
++ return ret;
++}
++
++static void mxcfb_unregister(struct fb_info *fbi)
++{
++ struct mxcfb_info *mxcfbi = (struct mxcfb_info *)fbi->par;
++
++ if (mxcfbi->ipu_alp_ch_irq != -1)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_alp_ch_irq, fbi);
++ if (mxcfbi->ipu_ch_irq)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_irq, fbi);
++ if (mxcfbi->ipu_ch_nf_irq)
++ ipu_free_irq(mxcfbi->ipu, mxcfbi->ipu_ch_nf_irq, fbi);
++
++ unregister_framebuffer(fbi);
++}
++
++static int mxcfb_setup_overlay(struct platform_device *pdev,
++ struct fb_info *fbi_bg, struct resource *res)
++{
++ struct fb_info *ovfbi;
++ struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
++ struct mxcfb_info *mxcfbi_fg;
++ int ret = 0;
++
++ ovfbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
++ if (!ovfbi) {
++ ret = -ENOMEM;
++ goto init_ovfbinfo_failed;
++ }
++ mxcfbi_fg = (struct mxcfb_info *)ovfbi->par;
++
++ mxcfbi_fg->ipu = ipu_get_soc(mxcfbi_bg->ipu_id);
++ if (IS_ERR(mxcfbi_fg->ipu)) {
++ ret = -ENODEV;
++ goto get_ipu_failed;
++ }
++ mxcfbi_fg->ipu_id = mxcfbi_bg->ipu_id;
++ mxcfbi_fg->ipu_ch_irq = IPU_IRQ_FG_SYNC_EOF;
++ mxcfbi_fg->ipu_ch_nf_irq = IPU_IRQ_FG_SYNC_NFACK;
++ mxcfbi_fg->ipu_alp_ch_irq = IPU_IRQ_FG_ALPHA_SYNC_EOF;
++ mxcfbi_fg->ipu_ch = MEM_FG_SYNC;
++ mxcfbi_fg->ipu_di = -1;
++ mxcfbi_fg->ipu_di_pix_fmt = mxcfbi_bg->ipu_di_pix_fmt;
++ mxcfbi_fg->overlay = true;
++ mxcfbi_fg->cur_blank = mxcfbi_fg->next_blank = FB_BLANK_POWERDOWN;
++
++ /* Need dummy values until real panel is configured */
++ ovfbi->var.xres = 240;
++ ovfbi->var.yres = 320;
++
++ if (res && res->start && res->end) {
++ ovfbi->fix.smem_len = res->end - res->start + 1;
++ ovfbi->fix.smem_start = res->start;
++ ovfbi->screen_base = ioremap(
++ ovfbi->fix.smem_start,
++ ovfbi->fix.smem_len);
++ }
++
++ ret = mxcfb_register(ovfbi);
++ if (ret < 0)
++ goto register_ov_failed;
++
++ mxcfbi_bg->ovfbi = ovfbi;
++
++ return ret;
++
++register_ov_failed:
++get_ipu_failed:
++ fb_dealloc_cmap(&ovfbi->cmap);
++ framebuffer_release(ovfbi);
++init_ovfbinfo_failed:
++ return ret;
++}
++
++static void mxcfb_unsetup_overlay(struct fb_info *fbi_bg)
++{
++ struct mxcfb_info *mxcfbi_bg = (struct mxcfb_info *)fbi_bg->par;
++ struct fb_info *ovfbi = mxcfbi_bg->ovfbi;
++
++ mxcfb_unregister(ovfbi);
++
++ if (&ovfbi->cmap)
++ fb_dealloc_cmap(&ovfbi->cmap);
++ framebuffer_release(ovfbi);
++}
++
++static bool ipu_usage[2][2];
++static int ipu_test_set_usage(int ipu, int di)
++{
++ if (ipu_usage[ipu][di])
++ return -EBUSY;
++ else
++ ipu_usage[ipu][di] = true;
++ return 0;
++}
++
++static void ipu_clear_usage(int ipu, int di)
++{
++ ipu_usage[ipu][di] = false;
++}
++
++static int mxcfb_get_of_property(struct platform_device *pdev,
++ struct ipuv3_fb_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ const char *disp_dev;
++ const char *mode_str = NULL;
++ const char *pixfmt;
++ int err;
++ int len;
++ u32 bpp, int_clk;
++ u32 late_init;
++
++ err = of_property_read_string(np, "disp_dev", &disp_dev);
++ if (err < 0) {
++ dev_dbg(&pdev->dev, "get of property disp_dev fail\n");
++ return err;
++ }
++ err = of_property_read_string(np, "mode_str", &mode_str);
++ if (err < 0)
++ dev_dbg(&pdev->dev, "get of property mode_str fail\n");
++ err = of_property_read_string(np, "interface_pix_fmt", &pixfmt);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property pix fmt fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "default_bpp", &bpp);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property bpp fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "int_clk", &int_clk);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property int_clk fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "late_init", &late_init);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property late_init fail\n");
++ return err;
++ }
++
++ if (!strncmp(pixfmt, "RGB24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(pixfmt, "BGR24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(pixfmt, "GBR24", 5))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(pixfmt, "RGB565", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(pixfmt, "RGB666", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(pixfmt, "YUV444", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(pixfmt, "LVDS666", 7))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(pixfmt, "YUYV16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(pixfmt, "UYVY16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(pixfmt, "YVYU16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(pixfmt, "VYUY16", 6))
++ plat_data->interface_pix_fmt = IPU_PIX_FMT_VYUY;
++ else {
++ dev_err(&pdev->dev, "err interface_pix_fmt!\n");
++ return -ENOENT;
++ }
++
++ len = min(sizeof(plat_data->disp_dev) - 1, strlen(disp_dev));
++ memcpy(plat_data->disp_dev, disp_dev, len);
++ plat_data->disp_dev[len] = '\0';
++ plat_data->mode_str = (char *)mode_str;
++ plat_data->default_bpp = bpp;
++ plat_data->int_clk = (bool)int_clk;
++ plat_data->late_init = (bool)late_init;
++ return err;
++}
++
++/*!
++ * Probe routine for the framebuffer driver. It is called during the
++ * driver binding process. The following functions are performed in
++ * this routine: Framebuffer initialization, Memory allocation and
++ * mapping, Framebuffer registration, IPU initialization.
++ *
++ * @return Appropriate error code to the kernel common code
++ */
++static int mxcfb_probe(struct platform_device *pdev)
++{
++ struct ipuv3_fb_platform_data *plat_data;
++ struct fb_info *fbi;
++ struct mxcfb_info *mxcfbi;
++ struct resource *res;
++ int ret = 0;
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ pdev->id = of_alias_get_id(pdev->dev.of_node, "mxcfb");
++ if (pdev->id < 0) {
++ dev_err(&pdev->dev, "can not get alias id\n");
++ return pdev->id;
++ }
++
++ plat_data = devm_kzalloc(&pdev->dev, sizeof(struct
++ ipuv3_fb_platform_data), GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++
++ ret = mxcfb_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get mxcfb of property fail\n");
++ return ret;
++ }
++
++ /* Initialize FB structures */
++ fbi = mxcfb_init_fbinfo(&pdev->dev, &mxcfb_ops);
++ if (!fbi) {
++ ret = -ENOMEM;
++ goto init_fbinfo_failed;
++ }
++
++ ret = mxcfb_option_setup(pdev, fbi);
++ if (ret)
++ goto get_fb_option_failed;
++
++ mxcfbi = (struct mxcfb_info *)fbi->par;
++ mxcfbi->ipu_int_clk = plat_data->int_clk;
++ mxcfbi->late_init = plat_data->late_init;
++ mxcfbi->first_set_par = true;
++ ret = mxcfb_dispdrv_init(pdev, fbi);
++ if (ret < 0)
++ goto init_dispdrv_failed;
++
++ ret = ipu_test_set_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "ipu%d-di%d already in use\n",
++ mxcfbi->ipu_id, mxcfbi->ipu_di);
++ goto ipu_in_busy;
++ }
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res && res->start && res->end) {
++ fbi->fix.smem_len = res->end - res->start + 1;
++ fbi->fix.smem_start = res->start;
++ fbi->screen_base = ioremap(fbi->fix.smem_start, fbi->fix.smem_len);
++ /* Do not clear the fb content drawn in bootloader. */
++ if (!mxcfbi->late_init)
++ memset(fbi->screen_base, 0, fbi->fix.smem_len);
++ }
++
++ mxcfbi->ipu = ipu_get_soc(mxcfbi->ipu_id);
++ if (IS_ERR(mxcfbi->ipu)) {
++ ret = -ENODEV;
++ goto get_ipu_failed;
++ }
++
++ /* first user uses DP with alpha feature */
++ if (!g_dp_in_use[mxcfbi->ipu_id]) {
++ mxcfbi->ipu_ch_irq = IPU_IRQ_BG_SYNC_EOF;
++ mxcfbi->ipu_ch_nf_irq = IPU_IRQ_BG_SYNC_NFACK;
++ mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
++ mxcfbi->ipu_ch = MEM_BG_SYNC;
++ /* Unblank the primary fb only by default */
++ if (pdev->id == 0)
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
++ else
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
++
++ ret = mxcfb_register(fbi);
++ if (ret < 0)
++ goto mxcfb_register_failed;
++
++ ipu_disp_set_global_alpha(mxcfbi->ipu, mxcfbi->ipu_ch,
++ true, 0x80);
++ ipu_disp_set_color_key(mxcfbi->ipu, mxcfbi->ipu_ch, false, 0);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ ret = mxcfb_setup_overlay(pdev, fbi, res);
++
++ if (ret < 0) {
++ mxcfb_unregister(fbi);
++ goto mxcfb_setupoverlay_failed;
++ }
++
++ g_dp_in_use[mxcfbi->ipu_id] = true;
++
++ ret = device_create_file(mxcfbi->ovfbi->dev,
++ &dev_attr_fsl_disp_property);
++ if (ret)
++ dev_err(mxcfbi->ovfbi->dev, "Error %d on creating "
++ "file for disp property\n",
++ ret);
++
++ ret = device_create_file(mxcfbi->ovfbi->dev,
++ &dev_attr_fsl_disp_dev_property);
++ if (ret)
++ dev_err(mxcfbi->ovfbi->dev, "Error %d on creating "
++ "file for disp device "
++ "propety\n", ret);
++ } else {
++ mxcfbi->ipu_ch_irq = IPU_IRQ_DC_SYNC_EOF;
++ mxcfbi->ipu_ch_nf_irq = IPU_IRQ_DC_SYNC_NFACK;
++ mxcfbi->ipu_alp_ch_irq = -1;
++ mxcfbi->ipu_ch = MEM_DC_SYNC;
++ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
++
++ ret = mxcfb_register(fbi);
++ if (ret < 0)
++ goto mxcfb_register_failed;
++ }
++
++ platform_set_drvdata(pdev, fbi);
++
++ ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_property);
++ if (ret)
++ dev_err(&pdev->dev, "Error %d on creating file for disp "
++ "property\n", ret);
++
++ ret = device_create_file(fbi->dev, &dev_attr_fsl_disp_dev_property);
++ if (ret)
++ dev_err(&pdev->dev, "Error %d on creating file for disp "
++ " device propety\n", ret);
++
++ return 0;
++
++mxcfb_setupoverlay_failed:
++mxcfb_register_failed:
++get_ipu_failed:
++ ipu_clear_usage(mxcfbi->ipu_id, mxcfbi->ipu_di);
++ipu_in_busy:
++init_dispdrv_failed:
++ fb_dealloc_cmap(&fbi->cmap);
++ framebuffer_release(fbi);
++get_fb_option_failed:
++init_fbinfo_failed:
++ return ret;
++}
++
++static int mxcfb_remove(struct platform_device *pdev)
++{
++ struct fb_info *fbi = platform_get_drvdata(pdev);
++ struct mxcfb_info *mxc_fbi = fbi->par;
++
++ if (!fbi)
++ return 0;
++
++ device_remove_file(fbi->dev, &dev_attr_fsl_disp_dev_property);
++ device_remove_file(fbi->dev, &dev_attr_fsl_disp_property);
++ mxcfb_blank(FB_BLANK_POWERDOWN, fbi);
++ mxcfb_unregister(fbi);
++ mxcfb_unmap_video_memory(fbi);
++
++ if (mxc_fbi->ovfbi) {
++ device_remove_file(mxc_fbi->ovfbi->dev,
++ &dev_attr_fsl_disp_dev_property);
++ device_remove_file(mxc_fbi->ovfbi->dev,
++ &dev_attr_fsl_disp_property);
++ mxcfb_blank(FB_BLANK_POWERDOWN, mxc_fbi->ovfbi);
++ mxcfb_unsetup_overlay(fbi);
++ mxcfb_unmap_video_memory(mxc_fbi->ovfbi);
++ }
++
++ ipu_clear_usage(mxc_fbi->ipu_id, mxc_fbi->ipu_di);
++ if (&fbi->cmap)
++ fb_dealloc_cmap(&fbi->cmap);
++ framebuffer_release(fbi);
++ return 0;
++}
++
++static const struct of_device_id imx_mxcfb_dt_ids[] = {
++ { .compatible = "fsl,mxc_sdc_fb"},
++ { /* sentinel */ }
++};
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxcfb_driver = {
++ .driver = {
++ .name = MXCFB_NAME,
++ .of_match_table = imx_mxcfb_dt_ids,
++ },
++ .probe = mxcfb_probe,
++ .remove = mxcfb_remove,
++ .suspend = mxcfb_suspend,
++ .resume = mxcfb_resume,
++};
++
++/*!
++ * Main entry function for the framebuffer. The function registers the power
++ * management callback functions with the kernel and also registers the MXCFB
++ * callback functions with the core Linux framebuffer driver \b fbmem.c
++ *
++ * @return Error code indicating success or failure
++ */
++int __init mxcfb_init(void)
++{
++ return platform_driver_register(&mxcfb_driver);
++}
++
++void mxcfb_exit(void)
++{
++ platform_driver_unregister(&mxcfb_driver);
++}
++
++module_init(mxcfb_init);
++module_exit(mxcfb_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC framebuffer driver");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("fb");
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxc_lcdif.c linux-3.14.72/drivers/video/mxc/mxc_lcdif.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxc_lcdif.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxc_lcdif.c 2016-06-19 22:11:55.353136857 +0200
+@@ -0,0 +1,243 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/init.h>
++#include <linux/ipu.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/mxcfb.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/platform_device.h>
++
++#include "mxc_dispdrv.h"
++
++struct mxc_lcd_platform_data {
++ u32 default_ifmt;
++ u32 ipu_id;
++ u32 disp_id;
++};
++
++struct mxc_lcdif_data {
++ struct platform_device *pdev;
++ struct mxc_dispdrv_handle *disp_lcdif;
++};
++
++#define DISPDRV_LCD "lcd"
++
++static struct fb_videomode lcdif_modedb[] = {
++ {
++ /* 800x480 @ 57 Hz , pixel clk @ 27MHz */
++ "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
++ FB_SYNC_CLK_LAT_FALL,
++ FB_VMODE_NONINTERLACED,
++ 0,},
++ {
++ /* 800x480 @ 60 Hz , pixel clk @ 32MHz */
++ "SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10,
++ FB_SYNC_CLK_LAT_FALL,
++ FB_VMODE_NONINTERLACED,
++ 0,},
++ {
++ /* 800x480 @ 60 Hz , pixel clk @ 32MHz */
++ "KD050C-WVGA", 60, 800, 480, 30000, 40, 40, 13, 29, 48, 3,
++ FB_SYNC_CLK_LAT_FALL,
++ FB_VMODE_NONINTERLACED,
++ 0,},
++};
++static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb);
++
++static int lcdif_init(struct mxc_dispdrv_handle *disp,
++ struct mxc_dispdrv_setting *setting)
++{
++ int ret, i;
++ struct mxc_lcdif_data *lcdif = mxc_dispdrv_getdata(disp);
++ struct device *dev = &lcdif->pdev->dev;
++ struct mxc_lcd_platform_data *plat_data = dev->platform_data;
++ struct fb_videomode *modedb = lcdif_modedb;
++ int modedb_sz = lcdif_modedb_sz;
++
++ /* use platform defined ipu/di */
++ ret = ipu_di_to_crtc(dev, plat_data->ipu_id,
++ plat_data->disp_id, &setting->crtc);
++ if (ret < 0)
++ return ret;
++
++ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
++ modedb, modedb_sz, NULL, setting->default_bpp);
++ if (!ret) {
++ fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
++ setting->if_fmt = plat_data->default_ifmt;
++ }
++
++ INIT_LIST_HEAD(&setting->fbi->modelist);
++ for (i = 0; i < modedb_sz; i++) {
++ struct fb_videomode m;
++ fb_var_to_videomode(&m, &setting->fbi->var);
++ if (fb_mode_is_equal(&m, &modedb[i])) {
++ fb_add_videomode(&modedb[i],
++ &setting->fbi->modelist);
++ break;
++ }
++ }
++
++ return ret;
++}
++
++void lcdif_deinit(struct mxc_dispdrv_handle *disp)
++{
++ /*TODO*/
++}
++
++static struct mxc_dispdrv_driver lcdif_drv = {
++ .name = DISPDRV_LCD,
++ .init = lcdif_init,
++ .deinit = lcdif_deinit,
++};
++
++static int lcd_get_of_property(struct platform_device *pdev,
++ struct mxc_lcd_platform_data *plat_data)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int err;
++ u32 ipu_id, disp_id;
++ const char *default_ifmt;
++
++ err = of_property_read_string(np, "default_ifmt", &default_ifmt);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property default_ifmt fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "ipu_id", &ipu_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
++ return err;
++ }
++ err = of_property_read_u32(np, "disp_id", &disp_id);
++ if (err) {
++ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
++ return err;
++ }
++
++ plat_data->ipu_id = ipu_id;
++ plat_data->disp_id = disp_id;
++ if (!strncmp(default_ifmt, "RGB24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB24;
++ else if (!strncmp(default_ifmt, "BGR24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_BGR24;
++ else if (!strncmp(default_ifmt, "GBR24", 5))
++ plat_data->default_ifmt = IPU_PIX_FMT_GBR24;
++ else if (!strncmp(default_ifmt, "RGB565", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB565;
++ else if (!strncmp(default_ifmt, "RGB666", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_RGB666;
++ else if (!strncmp(default_ifmt, "YUV444", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YUV444;
++ else if (!strncmp(default_ifmt, "LVDS666", 7))
++ plat_data->default_ifmt = IPU_PIX_FMT_LVDS666;
++ else if (!strncmp(default_ifmt, "YUYV16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YUYV;
++ else if (!strncmp(default_ifmt, "UYVY16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_UYVY;
++ else if (!strncmp(default_ifmt, "YVYU16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_YVYU;
++ else if (!strncmp(default_ifmt, "VYUY16", 6))
++ plat_data->default_ifmt = IPU_PIX_FMT_VYUY;
++ else {
++ dev_err(&pdev->dev, "err default_ifmt!\n");
++ return -ENOENT;
++ }
++
++ return err;
++}
++
++static int mxc_lcdif_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct pinctrl *pinctrl;
++ struct mxc_lcdif_data *lcdif;
++ struct mxc_lcd_platform_data *plat_data;
++
++ dev_dbg(&pdev->dev, "%s enter\n", __func__);
++ lcdif = devm_kzalloc(&pdev->dev, sizeof(struct mxc_lcdif_data),
++ GFP_KERNEL);
++ if (!lcdif)
++ return -ENOMEM;
++ plat_data = devm_kzalloc(&pdev->dev,
++ sizeof(struct mxc_lcd_platform_data),
++ GFP_KERNEL);
++ if (!plat_data)
++ return -ENOMEM;
++ pdev->dev.platform_data = plat_data;
++
++ ret = lcd_get_of_property(pdev, plat_data);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "get lcd of property fail\n");
++ return ret;
++ }
++
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ dev_err(&pdev->dev, "can't get/select pinctrl\n");
++ return PTR_ERR(pinctrl);
++ }
++
++ lcdif->pdev = pdev;
++ lcdif->disp_lcdif = mxc_dispdrv_register(&lcdif_drv);
++ mxc_dispdrv_setdata(lcdif->disp_lcdif, lcdif);
++
++ dev_set_drvdata(&pdev->dev, lcdif);
++ dev_dbg(&pdev->dev, "%s exit\n", __func__);
++
++ return ret;
++}
++
++static int mxc_lcdif_remove(struct platform_device *pdev)
++{
++ struct mxc_lcdif_data *lcdif = dev_get_drvdata(&pdev->dev);
++
++ mxc_dispdrv_puthandle(lcdif->disp_lcdif);
++ mxc_dispdrv_unregister(lcdif->disp_lcdif);
++ kfree(lcdif);
++ return 0;
++}
++
++static const struct of_device_id imx_lcd_dt_ids[] = {
++ { .compatible = "fsl,lcd"},
++ { /* sentinel */ }
++};
++static struct platform_driver mxc_lcdif_driver = {
++ .driver = {
++ .name = "mxc_lcdif",
++ .of_match_table = imx_lcd_dt_ids,
++ },
++ .probe = mxc_lcdif_probe,
++ .remove = mxc_lcdif_remove,
++};
++
++static int __init mxc_lcdif_init(void)
++{
++ return platform_driver_register(&mxc_lcdif_driver);
++}
++
++static void __exit mxc_lcdif_exit(void)
++{
++ platform_driver_unregister(&mxc_lcdif_driver);
++}
++
++module_init(mxc_lcdif_init);
++module_exit(mxc_lcdif_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX ipuv3 LCD extern port driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/video/mxc/mxsfb_sii902x.c linux-3.14.72/drivers/video/mxc/mxsfb_sii902x.c
+--- linux-3.14.72.orig/drivers/video/mxc/mxsfb_sii902x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/mxc/mxsfb_sii902x.c 2016-06-19 22:11:55.353136857 +0200
+@@ -0,0 +1,532 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for Sii902x.
++ */
++
++/*!
++ * @file mxsfb_sii902x.c
++ *
++ * @brief Frame buffer driver for SII902x
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/console.h>
++#include <linux/delay.h>
++#include <linux/errno.h>
++#include <linux/fb.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/i2c.h>
++#include <linux/fsl_devices.h>
++#include <linux/interrupt.h>
++#include <linux/reset.h>
++#include <asm/mach-types.h>
++#include <video/mxc_edid.h>
++
++#define SII_EDID_LEN 512
++#define DRV_NAME "sii902x"
++
++struct sii902x_data {
++ struct i2c_client *client;
++ struct delayed_work det_work;
++ struct fb_info *fbi;
++ struct mxc_edid_cfg edid_cfg;
++ u8 cable_plugin;
++ u8 edid[SII_EDID_LEN];
++ bool waiting_for_fb;
++ bool dft_mode_set;
++ const char *mode_str;
++ int bits_per_pixel;
++} sii902x;
++
++static void sii902x_poweron(void);
++static void sii902x_poweroff(void);
++
++#ifdef DEBUG
++static void dump_fb_videomode(struct fb_videomode *m)
++{
++ pr_debug("fb_videomode = %d %d %d %d %d %d %d %d %d %d %d %d %d\n",
++ m->refresh, m->xres, m->yres, m->pixclock, m->left_margin,
++ m->right_margin, m->upper_margin, m->lower_margin,
++ m->hsync_len, m->vsync_len, m->sync, m->vmode, m->flag);
++}
++#else
++static void dump_fb_videomode(struct fb_videomode *m)
++{}
++#endif
++
++static __attribute__ ((unused)) void dump_regs(u8 reg, int len)
++{
++ u8 buf[50];
++ int i;
++
++ i2c_smbus_read_i2c_block_data(sii902x.client, reg, len, buf);
++ for (i = 0; i < len; i++)
++ dev_dbg(&sii902x.client->dev, "reg[0x%02X]: 0x%02X\n",
++ i+reg, buf[i]);
++}
++
++static ssize_t sii902x_show_name(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ strcpy(buf, sii902x.fbi->fix.id);
++ sprintf(buf+strlen(buf), "\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(fb_name, S_IRUGO, sii902x_show_name, NULL);
++
++static ssize_t sii902x_show_state(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ if (sii902x.cable_plugin == 0)
++ strcpy(buf, "plugout\n");
++ else
++ strcpy(buf, "plugin\n");
++
++ return strlen(buf);
++}
++
++static DEVICE_ATTR(cable_state, S_IRUGO, sii902x_show_state, NULL);
++
++static ssize_t sii902x_show_edid(struct device *dev,
++ struct device_attribute *attr, char *buf)
++{
++ int i, j, len = 0;
++
++ for (j = 0; j < SII_EDID_LEN/16; j++) {
++ for (i = 0; i < 16; i++)
++ len += sprintf(buf+len, "0x%02X ",
++ sii902x.edid[j*16 + i]);
++ len += sprintf(buf+len, "\n");
++ }
++
++ return len;
++}
++
++static DEVICE_ATTR(edid, S_IRUGO, sii902x_show_edid, NULL);
++
++static void sii902x_setup(struct fb_info *fbi)
++{
++ u16 data[4];
++ u32 refresh;
++ u8 *tmp;
++ int i;
++
++ dev_dbg(&sii902x.client->dev, "Sii902x: setup..\n");
++
++ /* Power up */
++ i2c_smbus_write_byte_data(sii902x.client, 0x1E, 0x00);
++
++ /* set TPI video mode */
++ data[0] = PICOS2KHZ(fbi->var.pixclock) / 10;
++ data[2] = fbi->var.hsync_len + fbi->var.left_margin +
++ fbi->var.xres + fbi->var.right_margin;
++ data[3] = fbi->var.vsync_len + fbi->var.upper_margin +
++ fbi->var.yres + fbi->var.lower_margin;
++ refresh = data[2] * data[3];
++ refresh = (PICOS2KHZ(fbi->var.pixclock) * 1000) / refresh;
++ data[1] = refresh * 100;
++ tmp = (u8 *)data;
++ for (i = 0; i < 8; i++)
++ i2c_smbus_write_byte_data(sii902x.client, i, tmp[i]);
++
++ /* input bus/pixel: full pixel wide (24bit), rising edge */
++ i2c_smbus_write_byte_data(sii902x.client, 0x08, 0x70);
++ /* Set input format to RGB */
++ i2c_smbus_write_byte_data(sii902x.client, 0x09, 0x00);
++ /* set output format to RGB */
++ i2c_smbus_write_byte_data(sii902x.client, 0x0A, 0x00);
++ /* audio setup */
++ i2c_smbus_write_byte_data(sii902x.client, 0x25, 0x00);
++ i2c_smbus_write_byte_data(sii902x.client, 0x26, 0x40);
++ i2c_smbus_write_byte_data(sii902x.client, 0x27, 0x00);
++}
++
++#ifdef CONFIG_FB_MODE_HELPERS
++static int sii902x_read_edid(struct fb_info *fbi)
++{
++ int old, dat, ret, cnt = 100;
++ unsigned short addr = 0x50;
++
++ dev_dbg(&sii902x.client->dev, "%s\n", __func__);
++
++ old = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
++
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old | 0x4);
++ do {
++ cnt--;
++ msleep(10);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
++ } while ((!(dat & 0x2)) && cnt);
++
++ if (!cnt) {
++ ret = -1;
++ goto done;
++ }
++
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old | 0x06);
++
++ /* edid reading */
++ ret = mxc_edid_read(sii902x.client->adapter, addr,
++ sii902x.edid, &sii902x.edid_cfg, fbi);
++
++ cnt = 100;
++ do {
++ cnt--;
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old & ~0x6);
++ msleep(10);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1A);
++ } while ((dat & 0x6) && cnt);
++
++ if (!cnt)
++ ret = -1;
++
++done:
++
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, old);
++ return ret;
++}
++#else
++static int sii902x_read_edid(struct fb_info *fbi)
++{
++ return -1;
++}
++#endif
++
++static void sii902x_cable_connected(void)
++{
++ int i;
++ const struct fb_videomode *mode;
++ struct fb_videomode m;
++
++ if (sii902x_read_edid(sii902x.fbi) < 0)
++ dev_err(&sii902x.client->dev,
++ "Sii902x: read edid fail\n");
++ else {
++ if (sii902x.fbi->monspecs.modedb_len > 0) {
++
++ fb_destroy_modelist(&sii902x.fbi->modelist);
++
++ for (i = 0; i < sii902x.fbi->monspecs.modedb_len; i++) {
++
++ mode = &sii902x.fbi->monspecs.modedb[i];
++
++ if (!(mode->vmode & FB_VMODE_INTERLACED)) {
++
++ dev_dbg(&sii902x.client->dev, "Added mode %d:", i);
++ dev_dbg(&sii902x.client->dev,
++ "xres = %d, yres = %d, freq = %d, vmode = %d, flag = %d\n",
++ mode->xres, mode->yres, mode->refresh,
++ mode->vmode, mode->flag);
++
++ fb_add_videomode(mode, &sii902x.fbi->modelist);
++ }
++ }
++
++ /* Set the default mode only once. */
++ if (!sii902x.dft_mode_set &&
++ sii902x.mode_str && sii902x.bits_per_pixel) {
++
++ dev_dbg(&sii902x.client->dev, "%s: setting to default=%s bpp=%d\n",
++ __func__, sii902x.mode_str, sii902x.bits_per_pixel);
++
++ fb_find_mode(&sii902x.fbi->var, sii902x.fbi,
++ sii902x.mode_str, NULL, 0, NULL,
++ sii902x.bits_per_pixel);
++
++ sii902x.dft_mode_set = true;
++ }
++
++ fb_var_to_videomode(&m, &sii902x.fbi->var);
++ dump_fb_videomode(&m);
++
++ mode = fb_find_nearest_mode(&m,
++ &sii902x.fbi->modelist);
++
++ /* update fbi mode */
++ sii902x.fbi->mode = (struct fb_videomode *)mode;
++
++ fb_videomode_to_var(&sii902x.fbi->var, mode);
++
++ sii902x.fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ sii902x.fbi->flags |= FBINFO_MISC_USEREVENT;
++ fb_set_var(sii902x.fbi, &sii902x.fbi->var);
++ sii902x.fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++ }
++ /* Power on sii902x */
++ sii902x_poweron();
++ }
++}
++
++static void det_worker(struct work_struct *work)
++{
++ int dat;
++ char event_string[16];
++ char *envp[] = { event_string, NULL };
++
++ dev_dbg(&sii902x.client->dev, "%s\n", __func__);
++
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x3D);
++ if (dat & 0x1) {
++ /* cable connection changes */
++ if (dat & 0x4) {
++ sii902x.cable_plugin = 1;
++ dev_dbg(&sii902x.client->dev, "EVENT=plugin\n");
++ sprintf(event_string, "EVENT=plugin");
++ sii902x_cable_connected();
++ } else {
++ sii902x.cable_plugin = 0;
++ dev_dbg(&sii902x.client->dev, "EVENT=plugout\n");
++ sprintf(event_string, "EVENT=plugout");
++ /* Power off sii902x */
++ sii902x_poweroff();
++ }
++ kobject_uevent_env(&sii902x.client->dev.kobj, KOBJ_CHANGE, envp);
++ }
++ i2c_smbus_write_byte_data(sii902x.client, 0x3D, dat);
++
++ dev_dbg(&sii902x.client->dev, "exit %s\n", __func__);
++
++}
++
++static irqreturn_t sii902x_detect_handler(int irq, void *data)
++{
++ if (sii902x.fbi)
++ schedule_delayed_work(&(sii902x.det_work), msecs_to_jiffies(20));
++ else
++ sii902x.waiting_for_fb = true;
++
++ return IRQ_HANDLED;
++}
++
++static int sii902x_fb_event(struct notifier_block *nb, unsigned long val, void *v)
++{
++ struct fb_event *event = v;
++ struct fb_info *fbi = event->info;
++
++ dev_dbg(&sii902x.client->dev, "%s event=0x%lx\n", __func__, val);
++
++ switch (val) {
++ case FB_EVENT_FB_REGISTERED:
++ if (sii902x.fbi == NULL) {
++ sii902x.fbi = fbi;
++ if (sii902x.waiting_for_fb)
++ det_worker(NULL);
++ }
++ fb_show_logo(fbi, 0);
++ break;
++ case FB_EVENT_MODE_CHANGE:
++ sii902x_setup(fbi);
++ break;
++ case FB_EVENT_BLANK:
++ if (*((int *)event->data) == FB_BLANK_UNBLANK) {
++ dev_dbg(&sii902x.client->dev, "FB_BLANK_UNBLANK\n");
++ sii902x_poweron();
++ } else {
++ dev_dbg(&sii902x.client->dev, "FB_BLANK_BLANK\n");
++ sii902x_poweroff();
++ }
++ break;
++ }
++ return 0;
++}
++
++static struct notifier_block nb = {
++ .notifier_call = sii902x_fb_event,
++};
++
++static int mxsfb_get_of_property(void)
++{
++ struct device_node *np = sii902x.client->dev.of_node;
++ const char *mode_str;
++ int bits_per_pixel, ret;
++
++ ret = of_property_read_string(np, "mode_str", &mode_str);
++ if (ret < 0) {
++ dev_warn(&sii902x.client->dev, "get of property mode_str fail\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "bits-per-pixel", &bits_per_pixel);
++ if (ret) {
++ dev_warn(&sii902x.client->dev, "get of property bpp fail\n");
++ return ret;
++ }
++
++ sii902x.mode_str = mode_str;
++ sii902x.bits_per_pixel = bits_per_pixel;
++
++ return ret;
++}
++
++static int sii902x_probe(struct i2c_client *client,
++ const struct i2c_device_id *id)
++{
++ int i, dat, ret;
++ struct fb_info edid_fbi;
++
++ memset(&sii902x, 0, sizeof(sii902x));
++
++ sii902x.client = client;
++
++ dev_dbg(&sii902x.client->dev, "%s\n", __func__);;
++
++ /* Reset sii902x */
++ ret = device_reset(&sii902x.client->dev);
++ if (ret) {
++ dev_err(&sii902x.client->dev, "failed to reset: %d\n", ret);
++ return -ENODEV;
++ }
++
++ /* Set 902x in hardware TPI mode on and jump out of D3 state */
++ if (i2c_smbus_write_byte_data(sii902x.client, 0xc7, 0x00) < 0) {
++ dev_err(&sii902x.client->dev,
++ "Sii902x: cound not find device\n");
++ return -ENODEV;
++ }
++
++ /* read device ID */
++ for (i = 10; i > 0; i--) {
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1B);
++ printk(KERN_DEBUG "Sii902x: read id = 0x%02X", dat);
++ if (dat == 0xb0) {
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1C);
++ printk(KERN_DEBUG "-0x%02X", dat);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x1D);
++ printk(KERN_DEBUG "-0x%02X", dat);
++ dat = i2c_smbus_read_byte_data(sii902x.client, 0x30);
++ printk(KERN_DEBUG "-0x%02X\n", dat);
++ break;
++ }
++ }
++ if (i == 0) {
++ dev_err(&sii902x.client->dev,
++ "Sii902x: cound not find device\n");
++ return -ENODEV;
++ }
++
++ /* try to read edid */
++ ret = sii902x_read_edid(&edid_fbi);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev, "Can not read edid\n");
++
++ if (sii902x.client->irq) {
++ ret = request_irq(sii902x.client->irq, sii902x_detect_handler,
++ IRQF_TRIGGER_FALLING,
++ "SII902x_det", &sii902x);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not request det irq %d\n",
++ sii902x.client->irq);
++ else {
++ /*enable cable hot plug irq*/
++ i2c_smbus_write_byte_data(sii902x.client, 0x3c, 0x01);
++ INIT_DELAYED_WORK(&(sii902x.det_work), det_worker);
++ }
++ ret = device_create_file(&sii902x.client->dev, &dev_attr_fb_name);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not create sys node for fb name\n");
++ ret = device_create_file(&sii902x.client->dev, &dev_attr_cable_state);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not create sys node for cable state\n");
++ ret = device_create_file(&sii902x.client->dev, &dev_attr_edid);
++ if (ret < 0)
++ dev_warn(&sii902x.client->dev,
++ "Sii902x: cound not create sys node for edid\n");
++
++ }
++
++ mxsfb_get_of_property();
++ fb_register_client(&nb);
++
++ return 0;
++}
++
++static int sii902x_remove(struct i2c_client *client)
++{
++ fb_unregister_client(&nb);
++ sii902x_poweroff();
++
++ return 0;
++}
++
++static void sii902x_poweron(void)
++{
++ /* Turn on DVI or HDMI */
++ if (sii902x.edid_cfg.hdmi_cap)
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x01);
++ else
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x00);
++ return;
++}
++
++static void sii902x_poweroff(void)
++{
++ /* disable tmds before changing resolution */
++ if (sii902x.edid_cfg.hdmi_cap)
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x11);
++ else
++ i2c_smbus_write_byte_data(sii902x.client, 0x1A, 0x10);
++
++ return;
++}
++
++static const struct i2c_device_id sii902x_id[] = {
++ { DRV_NAME, 0},
++ { },
++};
++MODULE_DEVICE_TABLE(i2c, sii902x_id);
++
++static const struct of_device_id sii902x_dt_ids[] = {
++ { .compatible = "SiI,sii902x", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, sii902x_dt_ids);
++
++static struct i2c_driver sii902x_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = sii902x_dt_ids,
++ },
++ .probe = sii902x_probe,
++ .remove = sii902x_remove,
++ .id_table = sii902x_id,
++};
++
++module_i2c_driver(sii902x_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("SII902x DVI/HDMI driver");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/drivers/video/mxsfb.c linux-3.14.72/drivers/video/mxsfb.c
+--- linux-3.14.72.orig/drivers/video/mxsfb.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/video/mxsfb.c 2016-06-19 22:11:55.353136857 +0200
+@@ -4,7 +4,7 @@
+ * This code is based on:
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+@@ -39,19 +39,26 @@
+ * the required value in the imx_fb_videomode structure.
+ */
+
++#include <linux/busfreq-imx6.h>
++#include <linux/console.h>
+ #include <linux/module.h>
+ #include <linux/kernel.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/interrupt.h>
+ #include <linux/clk.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/io.h>
++#include <linux/pinctrl/consumer.h>
+ #include <linux/fb.h>
++#include <linux/mxcfb.h>
+ #include <linux/regulator/consumer.h>
+ #include <video/of_display_timing.h>
+-#include <video/of_videomode.h>
+ #include <video/videomode.h>
+
++#include "mxc/mxc_dispdrv.h"
++
+ #define REG_SET 4
+ #define REG_CLR 8
+
+@@ -96,9 +103,30 @@
+ #define CTRL_DF24 (1 << 1)
+ #define CTRL_RUN (1 << 0)
+
+-#define CTRL1_FIFO_CLEAR (1 << 21)
+-#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
+-#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
++#define CTRL1_RECOVERY_ON_UNDERFLOW (1 << 24)
++#define CTRL1_FIFO_CLEAR (1 << 21)
++#define CTRL1_SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16)
++#define CTRL1_GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf)
++#define CTRL1_OVERFLOW_IRQ_EN (1 << 15)
++#define CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
++#define CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
++#define CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
++#define CTRL1_OVERFLOW_IRQ (1 << 11)
++#define CTRL1_UNDERFLOW_IRQ (1 << 10)
++#define CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
++#define CTRL1_VSYNC_EDGE_IRQ (1 << 8)
++#define CTRL1_IRQ_ENABLE_MASK (CTRL1_OVERFLOW_IRQ_EN | \
++ CTRL1_UNDERFLOW_IRQ_EN | \
++ CTRL1_CUR_FRAME_DONE_IRQ_EN | \
++ CTRL1_VSYNC_EDGE_IRQ_EN)
++#define CTRL1_IRQ_ENABLE_SHIFT 12
++#define CTRL1_IRQ_STATUS_MASK (CTRL1_OVERFLOW_IRQ | \
++ CTRL1_UNDERFLOW_IRQ | \
++ CTRL1_CUR_FRAME_DONE_IRQ | \
++ CTRL1_VSYNC_EDGE_IRQ)
++#define CTRL1_IRQ_STATUS_SHIFT 8
++
++#define CTRL2_OUTSTANDING_REQS__REQ_16 (3 << 21)
+
+ #define TRANSFER_COUNT_SET_VCOUNT(x) (((x) & 0xffff) << 16)
+ #define TRANSFER_COUNT_GET_VCOUNT(x) (((x) >> 16) & 0xffff)
+@@ -149,8 +177,8 @@
+ #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
+ #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
+
+-#define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6)
+-#define MXSFB_SYNC_DOTCLK_FALLING_ACT (1 << 7) /* negtive edge sampling */
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
+
+ enum mxsfb_devtype {
+ MXSFB_V3,
+@@ -171,15 +199,26 @@
+ struct mxsfb_info {
+ struct fb_info fb_info;
+ struct platform_device *pdev;
+- struct clk *clk;
++ struct clk *clk_pix;
++ struct clk *clk_axi;
++ struct clk *clk_disp_axi;
++ bool clk_axi_enabled;
++ bool clk_disp_axi_enabled;
+ void __iomem *base; /* registers */
+ unsigned allocated_size;
+ int enabled;
+ unsigned ld_intf_width;
+ unsigned dotclk_delay;
+ const struct mxsfb_devdata *devdata;
+- u32 sync;
+ struct regulator *reg_lcd;
++ bool wait4vsync;
++ struct completion vsync_complete;
++ struct semaphore flip_sem;
++ int cur_blank;
++ int restore_blank;
++ char disp_dev[32];
++ struct mxc_dispdrv_handle *dispdrv;
++ int id;
+ };
+
+ #define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
+@@ -208,6 +247,46 @@
+
+ #define to_imxfb_host(x) (container_of(x, struct mxsfb_info, fb_info))
+
++static int mxsfb_map_videomem(struct fb_info *info);
++static int mxsfb_unmap_videomem(struct fb_info *info);
++static int mxsfb_set_par(struct fb_info *fb_info);
++
++/* enable lcdif axi clock */
++static inline void clk_enable_axi(struct mxsfb_info *host)
++{
++ if (!host->clk_axi_enabled && (host->clk_axi != NULL)) {
++ clk_prepare_enable(host->clk_axi);
++ host->clk_axi_enabled = true;
++ }
++}
++
++/* disable lcdif axi clock */
++static inline void clk_disable_axi(struct mxsfb_info *host)
++{
++ if (host->clk_axi_enabled && (host->clk_axi != NULL)) {
++ clk_disable_unprepare(host->clk_axi);
++ host->clk_axi_enabled = false;
++ }
++}
++
++/* enable DISP axi clock */
++static inline void clk_enable_disp_axi(struct mxsfb_info *host)
++{
++ if (!host->clk_disp_axi_enabled && (host->clk_disp_axi != NULL)) {
++ clk_prepare_enable(host->clk_disp_axi);
++ host->clk_disp_axi_enabled = true;
++ }
++}
++
++/* disable DISP axi clock */
++static inline void clk_disable_disp_axi(struct mxsfb_info *host)
++{
++ if (host->clk_disp_axi_enabled && (host->clk_disp_axi != NULL)) {
++ clk_disable_unprepare(host->clk_disp_axi);
++ host->clk_disp_axi_enabled = false;
++ }
++}
++
+ /* mask and shift depends on architecture */
+ static inline u32 set_hsync_pulse_width(struct mxsfb_info *host, unsigned val)
+ {
+@@ -239,6 +318,24 @@
+ }
+ };
+
++static const struct fb_bitfield def_rgb666[] = {
++ [RED] = {
++ .offset = 16,
++ .length = 6,
++ },
++ [GREEN] = {
++ .offset = 8,
++ .length = 6,
++ },
++ [BLUE] = {
++ .offset = 0,
++ .length = 6,
++ },
++ [TRANSP] = { /* no support for transparency */
++ .length = 0,
++ }
++};
++
+ static const struct fb_bitfield def_rgb888[] = {
+ [RED] = {
+ .offset = 16,
+@@ -257,6 +354,19 @@
+ }
+ };
+
++#define bitfield_is_equal(f1, f2) (!memcmp(&(f1), &(f2), sizeof(f1)))
++
++static inline bool pixfmt_is_equal(struct fb_var_screeninfo *var,
++ const struct fb_bitfield *f)
++{
++ if (bitfield_is_equal(var->red, f[RED]) &&
++ bitfield_is_equal(var->green, f[GREEN]) &&
++ bitfield_is_equal(var->blue, f[BLUE]))
++ return true;
++
++ return false;
++}
++
+ static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf)
+ {
+ chan &= 0xffff;
+@@ -264,6 +374,38 @@
+ return chan << bf->offset;
+ }
+
++static irqreturn_t mxsfb_irq_handler(int irq, void *dev_id)
++{
++ struct mxsfb_info *host = dev_id;
++ u32 ctrl1, enable, status, acked_status;
++
++ ctrl1 = readl(host->base + LCDC_CTRL1);
++ enable = (ctrl1 & CTRL1_IRQ_ENABLE_MASK) >> CTRL1_IRQ_ENABLE_SHIFT;
++ status = (ctrl1 & CTRL1_IRQ_STATUS_MASK) >> CTRL1_IRQ_STATUS_SHIFT;
++ acked_status = (enable & status) << CTRL1_IRQ_STATUS_SHIFT;
++
++ if ((acked_status & CTRL1_VSYNC_EDGE_IRQ) && host->wait4vsync) {
++ writel(CTRL1_VSYNC_EDGE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ host->wait4vsync = 0;
++ complete(&host->vsync_complete);
++ }
++
++ if (acked_status & CTRL1_CUR_FRAME_DONE_IRQ) {
++ writel(CTRL1_CUR_FRAME_DONE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ up(&host->flip_sem);
++ }
++
++ if (acked_status & CTRL1_UNDERFLOW_IRQ)
++ writel(CTRL1_UNDERFLOW_IRQ, host->base + LCDC_CTRL1 + REG_CLR);
++
++ if (acked_status & CTRL1_OVERFLOW_IRQ)
++ writel(CTRL1_OVERFLOW_IRQ, host->base + LCDC_CTRL1 + REG_CLR);
++
++ return IRQ_HANDLED;
++}
++
+ static int mxsfb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *fb_info)
+ {
+@@ -275,9 +417,18 @@
+ if (var->yres < MIN_YRES)
+ var->yres = MIN_YRES;
+
+- var->xres_virtual = var->xres;
++ if (var->xres_virtual > var->xres) {
++ dev_dbg(fb_info->device, "stride not supported\n");
++ return -EINVAL;
++ }
++
++ if (var->xres_virtual < var->xres)
++ var->xres_virtual = var->xres;
++ if (var->yres_virtual < var->yres)
++ var->yres_virtual = var->yres;
+
+- var->yres_virtual = var->yres;
++ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 16))
++ var->bits_per_pixel = 32;
+
+ switch (var->bits_per_pixel) {
+ case 16:
+@@ -290,7 +441,16 @@
+ pr_debug("Unsupported LCD bus width mapping\n");
+ break;
+ case STMLCDIF_16BIT:
++ /* 24 bit to 18 bit mapping */
++ rgb = def_rgb666;
++ break;
+ case STMLCDIF_18BIT:
++ if (pixfmt_is_equal(var, def_rgb666))
++ /* 24 bit to 18 bit mapping */
++ rgb = def_rgb666;
++ else
++ rgb = def_rgb888;
++ break;
+ case STMLCDIF_24BIT:
+ /* real 24 bit */
+ rgb = def_rgb888;
+@@ -298,7 +458,7 @@
+ }
+ break;
+ default:
+- pr_err("Unsupported colour depth: %u\n", var->bits_per_pixel);
++ pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel);
+ return -EINVAL;
+ }
+
+@@ -322,6 +482,15 @@
+
+ dev_dbg(&host->pdev->dev, "%s\n", __func__);
+
++ if (host->dispdrv && host->dispdrv->drv->setup) {
++ ret = host->dispdrv->drv->setup(host->dispdrv, fb_info);
++ if (ret < 0) {
++ dev_err(&host->pdev->dev, "failed to setup"
++ "dispdrv:%s\n", host->dispdrv->drv->name);
++ return;
++ }
++ }
++
+ if (host->reg_lcd) {
+ ret = regulator_enable(host->reg_lcd);
+ if (ret) {
+@@ -331,8 +500,38 @@
+ }
+ }
+
+- clk_prepare_enable(host->clk);
+- clk_set_rate(host->clk, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
++ pm_runtime_get_sync(&host->pdev->dev);
++
++ clk_enable_axi(host);
++ clk_enable_disp_axi(host);
++
++ clk_set_rate(host->clk_pix, PICOS2KHZ(fb_info->var.pixclock) * 1000U);
++ ret =
++ clk_set_rate(host->clk_pix,
++ PICOS2KHZ(fb_info->var.pixclock) * 1000U);
++ if (ret) {
++ dev_err(&host->pdev->dev,
++ "lcd pixel rate set failed: %d\n", ret);
++
++ if (host->reg_lcd) {
++ ret = regulator_disable(host->reg_lcd);
++ if (ret)
++ dev_err(&host->pdev->dev,
++ "lcd regulator disable failed: %d\n",
++ ret);
++ }
++ return;
++ }
++ clk_prepare_enable(host->clk_pix);
++
++ /* Clean soft reset and clock gate bit if it was enabled */
++ writel(CTRL_SFTRST | CTRL_CLKGATE, host->base + LCDC_CTRL + REG_CLR);
++
++ /* reconfigure the lcdif after */
++ mxsfb_set_par(&host->fb_info);
++
++ writel(CTRL2_OUTSTANDING_REQS__REQ_16,
++ host->base + LCDC_V4_CTRL2 + REG_SET);
+
+ /* if it was disabled, re-enable the mode again */
+ writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET);
+@@ -342,9 +541,20 @@
+ reg |= VDCTRL4_SYNC_SIGNALS_ON;
+ writel(reg, host->base + LCDC_VDCTRL4);
+
++ writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_SET);
+ writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET);
+
++ /* Recovery on underflow */
++ writel(CTRL1_RECOVERY_ON_UNDERFLOW, host->base + LCDC_CTRL1 + REG_SET);
++
+ host->enabled = 1;
++
++ if (host->dispdrv && host->dispdrv->drv->enable) {
++ ret = host->dispdrv->drv->enable(host->dispdrv, fb_info);
++ if (ret < 0)
++ dev_err(&host->pdev->dev, "failed to enable "
++ "dispdrv:%s\n", host->dispdrv->drv->name);
++ }
+ }
+
+ static void mxsfb_disable_controller(struct fb_info *fb_info)
+@@ -356,6 +566,11 @@
+
+ dev_dbg(&host->pdev->dev, "%s\n", __func__);
+
++ if (host->dispdrv && host->dispdrv->drv->disable)
++ host->dispdrv->drv->disable(host->dispdrv, fb_info);
++
++ clk_enable_axi(host);
++ clk_enable_disp_axi(host);
+ /*
+ * Even if we disable the controller here, it will still continue
+ * until its FIFOs are running out of data
+@@ -370,10 +585,14 @@
+ loop--;
+ }
+
++ writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_CLR);
++
+ reg = readl(host->base + LCDC_VDCTRL4);
+ writel(reg & ~VDCTRL4_SYNC_SIGNALS_ON, host->base + LCDC_VDCTRL4);
+
+- clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk_pix);
++
++ pm_runtime_put_sync_suspend(&host->pdev->dev);
+
+ host->enabled = 0;
+
+@@ -392,14 +611,10 @@
+ int line_size, fb_size;
+ int reenable = 0;
+
+- line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
+- fb_size = fb_info->var.yres_virtual * line_size;
+-
+- if (fb_size > fb_info->fix.smem_len)
+- return -ENOMEM;
+-
+- fb_info->fix.line_length = line_size;
++ clk_enable_axi(host);
++ clk_enable_disp_axi(host);
+
++ dev_dbg(&host->pdev->dev, "%s\n", __func__);
+ /*
+ * It seems, you can't re-program the controller if it is still running.
+ * This may lead into shifted pictures (FIFO issue?).
+@@ -410,9 +625,24 @@
+ mxsfb_disable_controller(fb_info);
+ }
+
++ sema_init(&host->flip_sem, 1);
++
+ /* clear the FIFOs */
+ writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET);
+
++ line_size = fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
++ fb_info->fix.line_length = line_size;
++ fb_size = fb_info->var.yres_virtual * line_size;
++
++ /* Reallocate memory */
++ if (!fb_info->fix.smem_start || (fb_size > fb_info->fix.smem_len)) {
++ if (fb_info->fix.smem_start)
++ mxsfb_unmap_videomem(fb_info);
++
++ if (mxsfb_map_videomem(fb_info) < 0)
++ return -ENOMEM;
++ }
++
+ ctrl = CTRL_BYPASS_COUNT | CTRL_MASTER |
+ CTRL_SET_BUS_WIDTH(host->ld_intf_width);
+
+@@ -427,11 +657,22 @@
+ ctrl |= CTRL_SET_WORD_LENGTH(3);
+ switch (host->ld_intf_width) {
+ case STMLCDIF_8BIT:
+- dev_err(&host->pdev->dev,
++ dev_dbg(&host->pdev->dev,
+ "Unsupported LCD bus width mapping\n");
+ return -EINVAL;
+ case STMLCDIF_16BIT:
++ /* 24 bit to 18 bit mapping */
++ ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
++ * each colour component
++ */
++ break;
+ case STMLCDIF_18BIT:
++ if (pixfmt_is_equal(&fb_info->var, def_rgb666))
++ /* 24 bit to 18 bit mapping */
++ ctrl |= CTRL_DF24; /* ignore the upper 2 bits in
++ * each colour component
++ */
++ break;
+ case STMLCDIF_24BIT:
+ /* real 24 bit */
+ break;
+@@ -440,7 +681,7 @@
+ writel(CTRL1_SET_BYTE_PACKAGING(0x7), host->base + LCDC_CTRL1);
+ break;
+ default:
+- dev_err(&host->pdev->dev, "Unhandled color depth of %u\n",
++ dev_dbg(&host->pdev->dev, "Unhandled color depth of %u\n",
+ fb_info->var.bits_per_pixel);
+ return -EINVAL;
+ }
+@@ -459,9 +700,9 @@
+ vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
+ if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT)
+ vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
+- if (host->sync & MXSFB_SYNC_DATA_ENABLE_HIGH_ACT)
++ if (!(fb_info->var.sync & FB_SYNC_OE_LOW_ACT))
+ vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
+- if (host->sync & MXSFB_SYNC_DOTCLK_FALLING_ACT)
++ if (fb_info->var.sync & FB_SYNC_CLK_LAT_FALL)
+ vdctrl0 |= VDCTRL0_DOTCLK_ACT_FALLING;
+
+ writel(vdctrl0, host->base + LCDC_VDCTRL0);
+@@ -539,10 +780,58 @@
+ return ret;
+ }
+
++static int mxsfb_wait_for_vsync(struct fb_info *fb_info)
++{
++ struct mxsfb_info *host = to_imxfb_host(fb_info);
++ int ret = 0;
++
++ if (host->cur_blank != FB_BLANK_UNBLANK) {
++ dev_err(fb_info->device, "can't wait for VSYNC when fb "
++ "is blank\n");
++ return -EINVAL;
++ }
++
++ init_completion(&host->vsync_complete);
++
++ writel(CTRL1_VSYNC_EDGE_IRQ,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ host->wait4vsync = 1;
++ writel(CTRL1_VSYNC_EDGE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_SET);
++ ret = wait_for_completion_interruptible_timeout(
++ &host->vsync_complete, 1 * HZ);
++ if (ret == 0) {
++ dev_err(fb_info->device,
++ "mxs wait for vsync timeout\n");
++ host->wait4vsync = 0;
++ ret = -ETIME;
++ } else if (ret > 0) {
++ ret = 0;
++ }
++ return ret;
++}
++
++static int mxsfb_ioctl(struct fb_info *fb_info, unsigned int cmd,
++ unsigned long arg)
++{
++ int ret = -EINVAL;
++
++ switch (cmd) {
++ case MXCFB_WAIT_FOR_VSYNC:
++ ret = mxsfb_wait_for_vsync(fb_info);
++ break;
++ default:
++ break;
++ }
++ return ret;
++}
++
+ static int mxsfb_blank(int blank, struct fb_info *fb_info)
+ {
+ struct mxsfb_info *host = to_imxfb_host(fb_info);
+
++ host->cur_blank = blank;
++
+ switch (blank) {
+ case FB_BLANK_POWERDOWN:
+ case FB_BLANK_VSYNC_SUSPEND:
+@@ -550,11 +839,15 @@
+ case FB_BLANK_NORMAL:
+ if (host->enabled)
+ mxsfb_disable_controller(fb_info);
++
++ clk_disable_disp_axi(host);
++ clk_disable_axi(host);
+ break;
+
+ case FB_BLANK_UNBLANK:
+ if (!host->enabled)
+ mxsfb_enable_controller(fb_info);
++ mxsfb_set_par(&host->fb_info);
+ break;
+ }
+ return 0;
+@@ -566,15 +859,69 @@
+ struct mxsfb_info *host = to_imxfb_host(fb_info);
+ unsigned offset;
+
+- if (var->xoffset != 0)
++ if (host->cur_blank != FB_BLANK_UNBLANK) {
++ dev_dbg(fb_info->device, "can't do pan display when fb "
++ "is blank\n");
++ return -EINVAL;
++ }
++
++ if (var->xoffset > 0) {
++ dev_dbg(fb_info->device, "x panning not supported\n");
+ return -EINVAL;
++ }
++
++ if ((var->yoffset + var->yres > var->yres_virtual)) {
++ dev_err(fb_info->device, "y panning exceeds\n");
++ return -EINVAL;
++ }
++
++ clk_enable_axi(host);
++ clk_enable_disp_axi(host);
+
+ offset = fb_info->fix.line_length * var->yoffset;
+
++ if (down_timeout(&host->flip_sem, HZ / 2)) {
++ dev_err(fb_info->device, "timeout when waiting for flip irq\n");
++ return -ETIMEDOUT;
++ }
++
+ /* update on next VSYNC */
+ writel(fb_info->fix.smem_start + offset,
+ host->base + host->devdata->next_buf);
+
++ writel(CTRL1_CUR_FRAME_DONE_IRQ,
++ host->base + LCDC_CTRL1 + REG_CLR);
++ writel(CTRL1_CUR_FRAME_DONE_IRQ_EN,
++ host->base + LCDC_CTRL1 + REG_SET);
++
++ return 0;
++}
++
++static int mxsfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
++{
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++
++ if (offset < info->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = info->fix.smem_len - offset;
++ vma->vm_pgoff = (info->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else
++ return -EINVAL;
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(info->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
+ return 0;
+ }
+
+@@ -583,15 +930,16 @@
+ .fb_check_var = mxsfb_check_var,
+ .fb_set_par = mxsfb_set_par,
+ .fb_setcolreg = mxsfb_setcolreg,
++ .fb_ioctl = mxsfb_ioctl,
+ .fb_blank = mxsfb_blank,
+ .fb_pan_display = mxsfb_pan_display,
++ .fb_mmap = mxsfb_mmap,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ };
+
+-static int mxsfb_restore_mode(struct mxsfb_info *host,
+- struct fb_videomode *vmode)
++static int mxsfb_restore_mode(struct mxsfb_info *host)
+ {
+ struct fb_info *fb_info = &host->fb_info;
+ unsigned line_count;
+@@ -599,6 +947,10 @@
+ unsigned long pa, fbsize;
+ int bits_per_pixel, ofs;
+ u32 transfer_count, vdctrl0, vdctrl2, vdctrl3, vdctrl4, ctrl;
++ struct fb_videomode vmode;
++
++ clk_enable_axi(host);
++ clk_enable_disp_axi(host);
+
+ /* Only restore the mode when the controller is running */
+ ctrl = readl(host->base + LCDC_CTRL);
+@@ -612,8 +964,8 @@
+
+ transfer_count = readl(host->base + host->devdata->transfer_count);
+
+- vmode->xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
+- vmode->yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
++ vmode.xres = TRANSFER_COUNT_GET_HCOUNT(transfer_count);
++ vmode.yres = TRANSFER_COUNT_GET_VCOUNT(transfer_count);
+
+ switch (CTRL_GET_WORD_LENGTH(ctrl)) {
+ case 0:
+@@ -621,7 +973,6 @@
+ break;
+ case 3:
+ bits_per_pixel = 32;
+- break;
+ case 1:
+ default:
+ return -EINVAL;
+@@ -629,39 +980,40 @@
+
+ fb_info->var.bits_per_pixel = bits_per_pixel;
+
+- vmode->pixclock = KHZ2PICOS(clk_get_rate(host->clk) / 1000U);
+- vmode->hsync_len = get_hsync_pulse_width(host, vdctrl2);
+- vmode->left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode->hsync_len;
+- vmode->right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) -
+- vmode->hsync_len - vmode->left_margin - vmode->xres;
+- vmode->vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
++ vmode.pixclock = KHZ2PICOS(clk_get_rate(host->clk_pix) / 1000U);
++ vmode.hsync_len = get_hsync_pulse_width(host, vdctrl2);
++ vmode.left_margin = GET_HOR_WAIT_CNT(vdctrl3) - vmode.hsync_len;
++ vmode.right_margin = VDCTRL2_GET_HSYNC_PERIOD(vdctrl2) - vmode.hsync_len -
++ vmode.left_margin - vmode.xres;
++ vmode.vsync_len = VDCTRL0_GET_VSYNC_PULSE_WIDTH(vdctrl0);
+ period = readl(host->base + LCDC_VDCTRL1);
+- vmode->upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode->vsync_len;
+- vmode->lower_margin = period - vmode->vsync_len -
+- vmode->upper_margin - vmode->yres;
++ vmode.upper_margin = GET_VERT_WAIT_CNT(vdctrl3) - vmode.vsync_len;
++ vmode.lower_margin = period - vmode.vsync_len - vmode.upper_margin - vmode.yres;
+
+- vmode->vmode = FB_VMODE_NONINTERLACED;
++ vmode.vmode = FB_VMODE_NONINTERLACED;
+
+- vmode->sync = 0;
++ vmode.sync = 0;
+ if (vdctrl0 & VDCTRL0_HSYNC_ACT_HIGH)
+- vmode->sync |= FB_SYNC_HOR_HIGH_ACT;
++ vmode.sync |= FB_SYNC_HOR_HIGH_ACT;
+ if (vdctrl0 & VDCTRL0_VSYNC_ACT_HIGH)
+- vmode->sync |= FB_SYNC_VERT_HIGH_ACT;
++ vmode.sync |= FB_SYNC_VERT_HIGH_ACT;
+
+ pr_debug("Reconstructed video mode:\n");
+ pr_debug("%dx%d, hsync: %u left: %u, right: %u, vsync: %u, upper: %u, lower: %u\n",
+- vmode->xres, vmode->yres, vmode->hsync_len, vmode->left_margin,
+- vmode->right_margin, vmode->vsync_len, vmode->upper_margin,
+- vmode->lower_margin);
+- pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode->pixclock));
++ vmode.xres, vmode.yres,
++ vmode.hsync_len, vmode.left_margin, vmode.right_margin,
++ vmode.vsync_len, vmode.upper_margin, vmode.lower_margin);
++ pr_debug("pixclk: %ldkHz\n", PICOS2KHZ(vmode.pixclock));
++
++ fb_add_videomode(&vmode, &fb_info->modelist);
+
+ host->ld_intf_width = CTRL_GET_BUS_WIDTH(ctrl);
+ host->dotclk_delay = VDCTRL4_GET_DOTCLK_DLY(vdctrl4);
+
+- fb_info->fix.line_length = vmode->xres * (bits_per_pixel >> 3);
++ fb_info->fix.line_length = vmode.xres * (bits_per_pixel >> 3);
+
+ pa = readl(host->base + host->devdata->cur_buf);
+- fbsize = fb_info->fix.line_length * vmode->yres;
++ fbsize = fb_info->fix.line_length * vmode.yres;
+ if (pa < fb_info->fix.smem_start)
+ return -EINVAL;
+ if (pa + fbsize > fb_info->fix.smem_start + fb_info->fix.smem_len)
+@@ -675,23 +1027,27 @@
+ line_count = fb_info->fix.smem_len / fb_info->fix.line_length;
+ fb_info->fix.ypanstep = 1;
+
+- clk_prepare_enable(host->clk);
++ clk_prepare_enable(host->clk_pix);
+ host->enabled = 1;
+
+ return 0;
+ }
+
+-static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host,
+- struct fb_videomode *vmode)
++static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
+ {
+ struct fb_info *fb_info = &host->fb_info;
+ struct fb_var_screeninfo *var = &fb_info->var;
+ struct device *dev = &host->pdev->dev;
+ struct device_node *np = host->pdev->dev.of_node;
+ struct device_node *display_np;
+- struct videomode vm;
++ struct device_node *timings_np;
++ struct display_timings *timings;
++ const char *disp_dev;
+ u32 width;
+- int ret;
++ int i;
++ int ret = 0;
++
++ host->id = of_alias_get_id(np, "lcdif");
+
+ display_np = of_parse_phandle(np, "display", 0);
+ if (!display_np) {
+@@ -731,76 +1087,185 @@
+ goto put_display_node;
+ }
+
+- ret = of_get_videomode(display_np, &vm, OF_USE_NATIVE_MODE);
+- if (ret) {
+- dev_err(dev, "failed to get videomode from DT\n");
++ ret = of_property_read_string(np, "disp-dev", &disp_dev);
++ if (!ret) {
++ memcpy(host->disp_dev, disp_dev, strlen(disp_dev));
++ /* Timing is from encoder driver */
+ goto put_display_node;
+ }
+
+- ret = fb_videomode_from_videomode(&vm, vmode);
+- if (ret < 0)
++ timings = of_get_display_timings(display_np);
++ if (!timings) {
++ dev_err(dev, "failed to get display timings\n");
++ ret = -ENOENT;
+ goto put_display_node;
++ }
++
++ timings_np = of_find_node_by_name(display_np,
++ "display-timings");
++ if (!timings_np) {
++ dev_err(dev, "failed to find display-timings node\n");
++ ret = -ENOENT;
++ goto put_display_node;
++ }
+
+- if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
+- host->sync |= MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
+- if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+- host->sync |= MXSFB_SYNC_DOTCLK_FALLING_ACT;
++ for (i = 0; i < of_get_child_count(timings_np); i++) {
++ struct videomode vm;
++ struct fb_videomode fb_vm;
++
++ ret = videomode_from_timings(timings, &vm, i);
++ if (ret < 0)
++ goto put_timings_node;
++ ret = fb_videomode_from_videomode(&vm, &fb_vm);
++ if (ret < 0)
++ goto put_timings_node;
++
++ if (!(vm.flags & DISPLAY_FLAGS_DE_HIGH))
++ fb_vm.sync |= FB_SYNC_OE_LOW_ACT;
++ if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
++ fb_vm.sync |= FB_SYNC_CLK_LAT_FALL;
++ fb_add_videomode(&fb_vm, &fb_info->modelist);
++ }
+
++put_timings_node:
++ of_node_put(timings_np);
+ put_display_node:
+ of_node_put(display_np);
+ return ret;
+ }
+
+-static int mxsfb_init_fbinfo(struct mxsfb_info *host,
+- struct fb_videomode *vmode)
++static int mxsfb_init_fbinfo(struct mxsfb_info *host)
+ {
+- int ret;
+ struct fb_info *fb_info = &host->fb_info;
+ struct fb_var_screeninfo *var = &fb_info->var;
+- dma_addr_t fb_phys;
+- void *fb_virt;
+- unsigned fb_size;
++ struct fb_modelist *modelist;
++ int ret;
+
+ fb_info->fbops = &mxsfb_ops;
+ fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
+- strlcpy(fb_info->fix.id, "mxs", sizeof(fb_info->fix.id));
+ fb_info->fix.type = FB_TYPE_PACKED_PIXELS;
+ fb_info->fix.ypanstep = 1;
+ fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
+ fb_info->fix.accel = FB_ACCEL_NONE;
+
+- ret = mxsfb_init_fbinfo_dt(host, vmode);
++ ret = mxsfb_init_fbinfo_dt(host);
+ if (ret)
+ return ret;
+
++ if (host->id < 0)
++ sprintf(fb_info->fix.id, "mxs-lcdif");
++ else
++ sprintf(fb_info->fix.id, "mxs-lcdif%d", host->id);
++
++ /* first video mode in the modelist as default video mode */
++ modelist = list_first_entry(&fb_info->modelist,
++ struct fb_modelist, list);
++ fb_videomode_to_var(var, &modelist->mode);
++
+ var->nonstd = 0;
+ var->activate = FB_ACTIVATE_NOW;
+ var->accel_flags = 0;
+ var->vmode = FB_VMODE_NONINTERLACED;
+
+- /* Memory allocation for framebuffer */
+- fb_size = SZ_2M;
+- fb_virt = alloc_pages_exact(fb_size, GFP_DMA);
+- if (!fb_virt)
+- return -ENOMEM;
++ /* init the color fields */
++ mxsfb_check_var(var, fb_info);
+
+- fb_phys = virt_to_phys(fb_virt);
++ fb_info->fix.line_length =
++ fb_info->var.xres * (fb_info->var.bits_per_pixel >> 3);
+
+- fb_info->fix.smem_start = fb_phys;
+- fb_info->screen_base = fb_virt;
+- fb_info->screen_size = fb_info->fix.smem_len = fb_size;
++ /* Memory allocation for framebuffer */
++ if (mxsfb_map_videomem(fb_info) < 0)
++ return -ENOMEM;
+
+- if (mxsfb_restore_mode(host, vmode))
+- memset(fb_virt, 0, fb_size);
++ if (mxsfb_restore_mode(host))
++ memset((char *)fb_info->screen_base, 0, fb_info->fix.smem_len);
+
+ return 0;
+ }
+
++static void mxsfb_dispdrv_init(struct platform_device *pdev,
++ struct fb_info *fbi)
++{
++ struct mxsfb_info *host = to_imxfb_host(fbi);
++ struct mxc_dispdrv_setting setting;
++ struct device *dev = &pdev->dev;
++ char disp_dev[32];
++
++ setting.fbi = fbi;
++ memcpy(disp_dev, host->disp_dev, strlen(host->disp_dev));
++ disp_dev[strlen(host->disp_dev)] = '\0';
++
++ host->dispdrv = mxc_dispdrv_gethandle(disp_dev, &setting);
++ if (IS_ERR(host->dispdrv)) {
++ host->dispdrv = NULL;
++ dev_info(dev, "failed to find mxc display driver %s\n",
++ disp_dev);
++ } else {
++ dev_info(dev, "registered mxc display driver %s\n",
++ disp_dev);
++ }
++}
++
+ static void mxsfb_free_videomem(struct mxsfb_info *host)
+ {
+ struct fb_info *fb_info = &host->fb_info;
+
+- free_pages_exact(fb_info->screen_base, fb_info->fix.smem_len);
++ mxsfb_unmap_videomem(fb_info);
++}
++
++/*!
++ * Allocates the DRAM memory for the frame buffer. This buffer is remapped
++ * into a non-cached, non-buffered, memory region to allow palette and pixel
++ * writes to occur without flushing the cache. Once this area is remapped,
++ * all virtual memory access to the video memory should occur at the new region.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxsfb_map_videomem(struct fb_info *fbi)
++{
++ if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
++ fbi->fix.smem_len = fbi->var.yres_virtual *
++ fbi->fix.line_length;
++
++ fbi->screen_base = dma_alloc_writecombine(fbi->device,
++ fbi->fix.smem_len,
++ (dma_addr_t *)&fbi->fix.smem_start,
++ GFP_DMA | GFP_KERNEL);
++ if (fbi->screen_base == 0) {
++ dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
++ fbi->fix.smem_len = 0;
++ fbi->fix.smem_start = 0;
++ return -EBUSY;
++ }
++
++ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
++ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
++
++ fbi->screen_size = fbi->fix.smem_len;
++
++ /* Clear the screen */
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ return 0;
++}
++
++/*!
++ * De-allocates the DRAM memory for the frame buffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int mxsfb_unmap_videomem(struct fb_info *fbi)
++{
++ dma_free_writecombine(fbi->device, fbi->fix.smem_len,
++ fbi->screen_base, fbi->fix.smem_start);
++ fbi->screen_base = 0;
++ fbi->fix.smem_start = 0;
++ fbi->fix.smem_len = 0;
++ return 0;
+ }
+
+ static struct platform_device_id mxsfb_devtype[] = {
+@@ -830,28 +1295,38 @@
+ struct resource *res;
+ struct mxsfb_info *host;
+ struct fb_info *fb_info;
+- struct fb_videomode *mode;
++ struct pinctrl *pinctrl;
++ int irq = platform_get_irq(pdev, 0);
+ int ret;
+
+ if (of_id)
+ pdev->id_entry = of_id->data;
+
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (!res) {
++ dev_err(&pdev->dev, "Cannot get memory IO resource\n");
++ return -ENODEV;
++ }
++
+ fb_info = framebuffer_alloc(sizeof(struct mxsfb_info), &pdev->dev);
+ if (!fb_info) {
+ dev_err(&pdev->dev, "Failed to allocate fbdev\n");
+ return -ENOMEM;
+ }
+
+- mode = devm_kzalloc(&pdev->dev, sizeof(struct fb_videomode),
+- GFP_KERNEL);
+- if (mode == NULL)
+- return -ENOMEM;
+-
+ host = to_imxfb_host(fb_info);
+
+- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ ret = devm_request_irq(&pdev->dev, irq, mxsfb_irq_handler, 0,
++ dev_name(&pdev->dev), host);
++ if (ret) {
++ dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n",
++ irq, ret);
++ return -ENODEV;
++ }
++
+ host->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(host->base)) {
++ dev_err(&pdev->dev, "ioremap failed\n");
+ ret = PTR_ERR(host->base);
+ goto fb_release;
+ }
+@@ -861,9 +1336,24 @@
+
+ host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data];
+
+- host->clk = devm_clk_get(&host->pdev->dev, NULL);
+- if (IS_ERR(host->clk)) {
+- ret = PTR_ERR(host->clk);
++ host->clk_pix = devm_clk_get(&host->pdev->dev, "pix");
++ if (IS_ERR(host->clk_pix)) {
++ host->clk_pix = NULL;
++ ret = PTR_ERR(host->clk_pix);
++ goto fb_release;
++ }
++
++ host->clk_axi = devm_clk_get(&host->pdev->dev, "axi");
++ if (IS_ERR(host->clk_axi)) {
++ host->clk_axi = NULL;
++ ret = PTR_ERR(host->clk_axi);
++ goto fb_release;
++ }
++
++ host->clk_disp_axi = devm_clk_get(&host->pdev->dev, "disp_axi");
++ if (IS_ERR(host->clk_disp_axi)) {
++ host->clk_disp_axi = NULL;
++ ret = PTR_ERR(host->clk_disp_axi);
+ goto fb_release;
+ }
+
+@@ -878,36 +1368,58 @@
+ goto fb_release;
+ }
+
+- ret = mxsfb_init_fbinfo(host, mode);
++ INIT_LIST_HEAD(&fb_info->modelist);
++
++ pm_runtime_enable(&host->pdev->dev);
++
++ ret = mxsfb_init_fbinfo(host);
+ if (ret != 0)
+- goto fb_release;
++ goto fb_pm_runtime_disable;
+
+- fb_videomode_to_var(&fb_info->var, mode);
++ mxsfb_dispdrv_init(pdev, fb_info);
+
+- /* init the color fields */
+- mxsfb_check_var(&fb_info->var, fb_info);
++ if (!host->dispdrv) {
++ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++ if (IS_ERR(pinctrl)) {
++ ret = PTR_ERR(pinctrl);
++ goto fb_pm_runtime_disable;
++ }
++ }
+
+ platform_set_drvdata(pdev, fb_info);
+
++ if (!host->enabled) {
++ writel(0, host->base + LCDC_CTRL);
++ mxsfb_set_par(fb_info);
++ mxsfb_enable_controller(fb_info);
++ }
++
+ ret = register_framebuffer(fb_info);
+ if (ret != 0) {
+- dev_err(&pdev->dev,"Failed to register framebuffer\n");
++ dev_err(&pdev->dev, "Failed to register framebuffer\n");
+ goto fb_destroy;
+ }
+
+- if (!host->enabled) {
+- writel(0, host->base + LCDC_CTRL);
+- mxsfb_set_par(fb_info);
+- mxsfb_enable_controller(fb_info);
++ console_lock();
++ ret = fb_blank(fb_info, FB_BLANK_UNBLANK);
++ console_unlock();
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Failed to unblank framebuffer\n");
++ goto fb_unregister;
+ }
+
+ dev_info(&pdev->dev, "initialized\n");
+
+ return 0;
+
++fb_unregister:
++ unregister_framebuffer(fb_info);
+ fb_destroy:
+ if (host->enabled)
+- clk_disable_unprepare(host->clk);
++ clk_disable_unprepare(host->clk_pix);
++ fb_destroy_modelist(&fb_info->modelist);
++fb_pm_runtime_disable:
++ pm_runtime_disable(&host->pdev->dev);
+ fb_release:
+ framebuffer_release(fb_info);
+
+@@ -922,11 +1434,14 @@
+ if (host->enabled)
+ mxsfb_disable_controller(fb_info);
+
++ pm_runtime_disable(&host->pdev->dev);
+ unregister_framebuffer(fb_info);
+ mxsfb_free_videomem(host);
+
+ framebuffer_release(fb_info);
+
++ platform_set_drvdata(pdev, NULL);
++
+ return 0;
+ }
+
+@@ -935,13 +1450,77 @@
+ struct fb_info *fb_info = platform_get_drvdata(pdev);
+ struct mxsfb_info *host = to_imxfb_host(fb_info);
+
++ clk_enable_axi(host);
++ clk_enable_disp_axi(host);
+ /*
+ * Force stop the LCD controller as keeping it running during reboot
+ * might interfere with the BootROM's boot mode pads sampling.
+ */
+ writel(CTRL_RUN, host->base + LCDC_CTRL + REG_CLR);
++ writel(CTRL_MASTER, host->base + LCDC_CTRL + REG_CLR);
++ clk_disable_disp_axi(host);
++ clk_disable_axi(host);
++}
++
++#ifdef CONFIG_PM_RUNTIME
++static int mxsfb_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "mxsfb busfreq high release.\n");
++
++ return 0;
++}
++
++static int mxsfb_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ dev_dbg(dev, "mxsfb busfreq high request.\n");
++
++ return 0;
++}
++#else
++#define mxsfb_runtime_suspend NULL
++#define mxsfb_runtime_resume NULL
++#endif
++
++#ifdef CONFIG_PM
++static int mxsfb_suspend(struct device *pdev)
++{
++ struct fb_info *fb_info = dev_get_drvdata(pdev);
++ struct mxsfb_info *host = to_imxfb_host(fb_info);
++ int saved_blank;
++
++ console_lock();
++ fb_set_suspend(fb_info, 1);
++ saved_blank = host->cur_blank;
++ mxsfb_blank(FB_BLANK_POWERDOWN, fb_info);
++ host->restore_blank = saved_blank;
++ console_unlock();
++ return 0;
+ }
+
++static int mxsfb_resume(struct device *pdev)
++{
++ struct fb_info *fb_info = dev_get_drvdata(pdev);
++ struct mxsfb_info *host = to_imxfb_host(fb_info);
++
++ console_lock();
++ mxsfb_blank(host->restore_blank, fb_info);
++ fb_set_suspend(fb_info, 0);
++ console_unlock();
++
++ return 0;
++}
++#else
++#define mxsfb_suspend NULL
++#define mxsfb_resume NULL
++#endif
++
++static const struct dev_pm_ops mxsfb_pm_ops = {
++ SET_RUNTIME_PM_OPS(mxsfb_runtime_suspend, mxsfb_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(mxsfb_suspend, mxsfb_resume)
++};
++
+ static struct platform_driver mxsfb_driver = {
+ .probe = mxsfb_probe,
+ .remove = mxsfb_remove,
+@@ -950,6 +1529,7 @@
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = mxsfb_dt_ids,
++ .pm = &mxsfb_pm_ops,
+ },
+ };
+
+diff -Nur linux-3.14.72.orig/drivers/video/vfb_phymem.c linux-3.14.72/drivers/video/vfb_phymem.c
+--- linux-3.14.72.orig/drivers/video/vfb_phymem.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/drivers/video/vfb_phymem.c 2016-06-19 22:11:55.357136594 +0200
+@@ -0,0 +1,498 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for surface sharing.
++ */
++
++/*!
++ * @file virtual_fb.c
++ *
++ * @brief Virtual Frame buffer driver for surface sharing
++ *
++ * @ingroup Framebuffer
++ */
++
++/*!
++ * Include files
++ */
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/sched.h>
++#include <linux/errno.h>
++#include <linux/string.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <linux/fb.h>
++#include <linux/delay.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/dma-mapping.h>
++#include <linux/clk.h>
++#include <linux/console.h>
++#include <linux/io.h>
++#include <linux/uaccess.h>
++#include <asm/mach-types.h>
++
++/*
++ * Driver name
++ */
++#define VIRT_FB_NAME "virtual_fb"
++
++
++static int vfbcount = 1;
++module_param(vfbcount, int, 0);
++static struct fb_info ** g_fb_list;
++
++static int virtfb_map_video_memory(struct fb_info *fbi);
++static int virtfb_unmap_video_memory(struct fb_info *fbi);
++
++/*
++ * Set fixed framebuffer parameters based on variable settings.
++ *
++ * @param info framebuffer information pointer
++ */
++static int virtfb_set_fix(struct fb_info *info)
++{
++ struct fb_fix_screeninfo *fix = &info->fix;
++ struct fb_var_screeninfo *var = &info->var;
++
++ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
++
++ fix->type = FB_TYPE_PACKED_PIXELS;
++ fix->accel = FB_ACCEL_NONE;
++ fix->visual = FB_VISUAL_TRUECOLOR;
++ fix->xpanstep = 1;
++ fix->ywrapstep = 1;
++ fix->ypanstep = 1;
++
++ return 0;
++}
++
++
++/*
++ * Set framebuffer parameters and change the operating mode.
++ *
++ * @param info framebuffer information pointer
++ */
++static int virtfb_set_par(struct fb_info *fbi)
++{
++ int retval = 0;
++ u32 mem_len;
++
++ dev_dbg(fbi->device, "Reconfiguring framebuffer\n");
++
++ virtfb_set_fix(fbi);
++
++ mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
++ if (!fbi->fix.smem_start || (mem_len > fbi->fix.smem_len)) {
++ if (fbi->fix.smem_start)
++ virtfb_unmap_video_memory(fbi);
++
++ if (virtfb_map_video_memory(fbi) < 0)
++ return -ENOMEM;
++ }
++
++
++ return retval;
++}
++
++
++/*
++ * Check framebuffer variable parameters and adjust to valid values.
++ *
++ * @param var framebuffer variable parameters
++ *
++ * @param info framebuffer information pointer
++ */
++static int virtfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++
++ /* fg should not bigger than bg */
++
++ if (var->xres_virtual < var->xres)
++ var->xres_virtual = var->xres;
++
++ if (var->yres_virtual < var->yres)
++ var->yres_virtual = var->yres;
++
++ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
++ (var->bits_per_pixel != 16) && (var->bits_per_pixel != 12) &&
++ (var->bits_per_pixel != 8))
++ var->bits_per_pixel = 16;
++
++ switch (var->bits_per_pixel) {
++ case 8:
++ var->red.length = 3;
++ var->red.offset = 5;
++ var->red.msb_right = 0;
++
++ var->green.length = 3;
++ var->green.offset = 2;
++ var->green.msb_right = 0;
++
++ var->blue.length = 2;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ break;
++ case 16:
++ var->red.length = 5;
++ var->red.offset = 11;
++ var->red.msb_right = 0;
++
++ var->green.length = 6;
++ var->green.offset = 5;
++ var->green.msb_right = 0;
++
++ var->blue.length = 5;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ break;
++ case 24:
++ var->red.length = 8;
++ var->red.offset = 16;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 8;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 0;
++ var->transp.offset = 0;
++ var->transp.msb_right = 0;
++ break;
++ case 32:
++ var->red.length = 8;
++ var->red.offset = 16;
++ var->red.msb_right = 0;
++
++ var->green.length = 8;
++ var->green.offset = 8;
++ var->green.msb_right = 0;
++
++ var->blue.length = 8;
++ var->blue.offset = 0;
++ var->blue.msb_right = 0;
++
++ var->transp.length = 8;
++ var->transp.offset = 24;
++ var->transp.msb_right = 0;
++ break;
++ }
++
++ var->height = -1;
++ var->width = -1;
++ var->grayscale = 0;
++
++ return 0;
++}
++
++/*
++ * Pan or Wrap the Display
++ *
++ * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
++ *
++ * @param var Variable screen buffer information
++ * @param info Framebuffer information pointer
++ */
++static int
++virtfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
++{
++
++ if (info->var.yoffset == var->yoffset)
++ return 0; /* No change, do nothing */
++
++ if ((var->yoffset + info->var.yres) > info->var.yres_virtual)
++ return -EINVAL;
++
++ info->var.yoffset = var->yoffset;
++
++ return 0;
++}
++
++/*
++ * Function to handle custom mmap for virtual framebuffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @param vma Pointer to vm_area_struct
++ */
++static int virtfb_mmap(struct fb_info *fbi, struct vm_area_struct *vma)
++{
++ u32 len;
++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
++
++ if (offset < fbi->fix.smem_len) {
++ /* mapping framebuffer memory */
++ len = fbi->fix.smem_len - offset;
++ vma->vm_pgoff = (fbi->fix.smem_start + offset) >> PAGE_SHIFT;
++ } else {
++ return -EINVAL;
++ }
++
++ len = PAGE_ALIGN(len);
++ if (vma->vm_end - vma->vm_start > len)
++ return -EINVAL;
++
++ /* make buffers bufferable */
++ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
++
++ vma->vm_flags |= VM_IO;
++
++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++ vma->vm_end - vma->vm_start, vma->vm_page_prot)) {
++ dev_dbg(fbi->device, "mmap remap_pfn_range failed\n");
++ return -ENOBUFS;
++ }
++
++ return 0;
++}
++
++/*!
++ * This structure contains the pointers to the control functions that are
++ * invoked by the core framebuffer driver to perform operations like
++ * blitting, rectangle filling, copy regions and cursor definition.
++ */
++static struct fb_ops virtfb_ops = {
++ .owner = THIS_MODULE,
++ .fb_set_par = virtfb_set_par,
++ .fb_check_var = virtfb_check_var,
++ .fb_pan_display = virtfb_pan_display,
++ .fb_mmap = virtfb_mmap,
++};
++
++
++/*
++ * Main framebuffer functions
++ */
++
++/*!
++ * Allocates the DRAM memory for the frame buffer. This buffer is remapped
++ * into a non-cached, non-buffered, memory region to allow palette and pixel
++ * writes to occur without flushing the cache. Once this area is remapped,
++ * all virtual memory access to the video memory should occur at the new region.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int virtfb_map_video_memory(struct fb_info *fbi)
++{
++ if (fbi->fix.smem_len < fbi->var.yres_virtual * fbi->fix.line_length)
++ fbi->fix.smem_len = fbi->var.yres_virtual *
++ fbi->fix.line_length;
++
++ fbi->screen_base = dma_alloc_coherent(fbi->device,
++ fbi->fix.smem_len,
++ (dma_addr_t *)&fbi->fix.smem_start,
++ GFP_DMA | GFP_KERNEL);
++ if (fbi->screen_base == 0) {
++ dev_err(fbi->device, "Unable to allocate framebuffer memory\n");
++ fbi->fix.smem_len = 0;
++ fbi->fix.smem_start = 0;
++ return -EBUSY;
++ }
++
++ dev_dbg(fbi->device, "allocated fb @ paddr=0x%08X, size=%d.\n",
++ (uint32_t) fbi->fix.smem_start, fbi->fix.smem_len);
++
++ fbi->screen_size = fbi->fix.smem_len;
++
++ /* Clear the screen */
++ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
++
++ return 0;
++}
++
++/*!
++ * De-allocates the DRAM memory for the frame buffer.
++ *
++ * @param fbi framebuffer information pointer
++ *
++ * @return Error code indicating success or failure
++ */
++static int virtfb_unmap_video_memory(struct fb_info *fbi)
++{
++ dma_free_coherent(fbi->device, fbi->fix.smem_len,
++ fbi->screen_base, fbi->fix.smem_start);
++ fbi->screen_base = 0;
++ fbi->fix.smem_start = 0;
++ fbi->fix.smem_len = 0;
++ return 0;
++}
++
++/*!
++ * Initializes the framebuffer information pointer. After allocating
++ * sufficient memory for the framebuffer structure, the fields are
++ * filled with custom information passed in from the configurable
++ * structures. This includes information such as bits per pixel,
++ * color maps, screen width/height and RGBA offsets.
++ *
++ * @return Framebuffer structure initialized with our information
++ */
++static struct fb_info *virtfb_init_fbinfo(struct fb_ops *ops)
++{
++ struct fb_info *fbi;
++
++ /*
++ * Allocate sufficient memory for the fb structure
++ */
++ fbi = framebuffer_alloc(sizeof(unsigned int), NULL);
++ if (!fbi)
++ return NULL;
++
++
++ fbi->var.activate = FB_ACTIVATE_NOW;
++
++ fbi->fbops = ops;
++ fbi->flags = FBINFO_FLAG_DEFAULT;
++
++
++ return fbi;
++}
++
++
++static int virtfb_register(struct fb_info *fbi, unsigned int id)
++{
++ struct fb_videomode m;
++ int ret = 0;
++
++ //TODO: Set framebuffer ID
++ sprintf(fbi->fix.id, "virt_fb%d", id);
++
++ //Setup small default resolution
++ fbi->var.xres_virtual = fbi->var.xres = fbi->var.yres_virtual = fbi->var.yres = 128;
++ fbi->var.bits_per_pixel = 16;
++
++ virtfb_check_var(&fbi->var, fbi);
++
++ virtfb_set_fix(fbi);
++
++ /*added first mode to fbi modelist*/
++ if (!fbi->modelist.next || !fbi->modelist.prev)
++ INIT_LIST_HEAD(&fbi->modelist);
++ fb_var_to_videomode(&m, &fbi->var);
++ fb_add_videomode(&m, &fbi->modelist);
++
++ fbi->var.activate |= FB_ACTIVATE_FORCE;
++ console_lock();
++ fbi->flags |= FBINFO_MISC_USEREVENT;
++ ret = fb_set_var(fbi, &fbi->var);
++ fbi->flags &= ~FBINFO_MISC_USEREVENT;
++ console_unlock();
++
++
++ ret = register_framebuffer(fbi);
++ if (ret < 0)
++ goto err0;
++
++ return ret;
++err0:
++ return ret;
++}
++
++static void virtfb_unregister(struct fb_info *fbi)
++{
++
++ unregister_framebuffer(fbi);
++}
++
++/*!
++ * Main entry function for the framebuffer. The function registers the power
++ * management callback functions with the kernel and also registers the MXCFB
++ * callback functions with the core Linux framebuffer driver \b fbmem.c
++ *
++ * @return Error code indicating success or failure
++ */
++int __init virtfb_init(void)
++{
++
++ u32 * fbNum;
++ int i, ret = 0;
++
++ /*
++ * Initialize FB structures
++ */
++
++ g_fb_list = kzalloc(sizeof(struct fb_info*) * vfbcount, GFP_KERNEL);
++ for(i=0;i<vfbcount;i++)
++ {
++ g_fb_list[i] = virtfb_init_fbinfo(&virtfb_ops);
++ if (!g_fb_list[i]) {
++ ret = -ENOMEM;
++ goto init_fbinfo_failed;
++ }
++
++ fbNum = (u32*)g_fb_list[i]->par;
++ *fbNum = i;
++
++ ret = virtfb_register(g_fb_list[i], i);
++ if (ret < 0)
++ goto virtfb_register_failed;
++ }
++
++
++ return 0;
++virtfb_register_failed:
++init_fbinfo_failed:
++ for(i=0;i<vfbcount;i++)
++ {
++ if(g_fb_list[i])
++ {
++ virtfb_unregister(g_fb_list[i]);
++ framebuffer_release(g_fb_list[i]);
++ }
++ }
++ return ret;
++
++}
++
++void virtfb_exit(void)
++{
++
++ int i;
++
++ for(i=0;i<vfbcount;i++)
++ {
++ if(g_fb_list[i])
++ {
++ virtfb_unregister(g_fb_list[i]);
++ virtfb_unmap_video_memory(g_fb_list[i]);
++
++ framebuffer_release(g_fb_list[i]);
++ }
++ }
++
++
++}
++
++module_init(virtfb_init);
++module_exit(virtfb_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Virtual framebuffer driver");
++MODULE_LICENSE("GPL");
++MODULE_SUPPORTED_DEVICE("fb");
+diff -Nur linux-3.14.72.orig/drivers/watchdog/imx2_wdt.c linux-3.14.72/drivers/watchdog/imx2_wdt.c
+--- linux-3.14.72.orig/drivers/watchdog/imx2_wdt.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/drivers/watchdog/imx2_wdt.c 2016-06-19 22:11:55.357136594 +0200
+@@ -2,7 +2,7 @@
+ * Watchdog driver for IMX2 and later processors
+ *
+ * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
+- * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * some parts adapted by similar drivers from Darius Augulis and Vladimir
+ * Zapolskiy, additional improvements by Wim Van Sebroeck.
+@@ -22,6 +22,8 @@
+ */
+
+ #include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
+ #include <linux/kernel.h>
+ #include <linux/miscdevice.h>
+ #include <linux/module.h>
+@@ -43,17 +45,23 @@
+ #define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
+ #define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
+
++
+ #define IMX2_WDT_WSR 0x02 /* Service Register */
+ #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
+ #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
+
+ #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
+ #define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
++#define IMX2_WDT_WICR 0x06 /*Interrupt Control Register*/
++#define IMX2_WDT_WICR_WIE (1 << 15) /* -> Interrupt Enable */
++#define IMX2_WDT_WICR_WTIS (1 << 14) /* -> Interrupt Status */
++#define IMX2_WDT_WICR_WICT (0xFF << 0) /* -> Watchdog Interrupt Timeout Field */
+
+ #define IMX2_WDT_MAX_TIME 128
+ #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
+
+ #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
++#define WDOG_SEC_TO_PRECOUNT(s) (s * 2) /* set WDOG pre timeout count*/
+
+ #define IMX2_WDT_STATUS_OPEN 0
+ #define IMX2_WDT_STATUS_STARTED 1
+@@ -63,6 +71,7 @@
+ struct clk *clk;
+ void __iomem *base;
+ unsigned timeout;
++ unsigned pretimeout;
+ unsigned long status;
+ struct timer_list timer; /* Pings the watchdog when closed */
+ } imx2_wdt;
+@@ -82,7 +91,7 @@
+
+ static const struct watchdog_info imx2_wdt_info = {
+ .identity = "imx2+ watchdog",
+- .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
++ .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_PRETIMEOUT,
+ };
+
+ static inline void imx2_wdt_setup(void)
+@@ -151,6 +160,38 @@
+ __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
+ }
+
++
++static int imx2_wdt_check_pretimeout_set(void)
++{
++ u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WICR);
++ return (val & IMX2_WDT_WICR_WIE) ? 1 : 0;
++}
++
++static void imx2_wdt_set_pretimeout(int new_timeout)
++{
++ u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WICR);
++
++ /* set the new pre-timeout value in the WSR */
++ val &= ~IMX2_WDT_WICR_WICT;
++ val |= WDOG_SEC_TO_PRECOUNT(new_timeout);
++
++ if (!imx2_wdt_check_pretimeout_set())
++ val |= IMX2_WDT_WICR_WIE; /*enable*/
++ __raw_writew(val, imx2_wdt.base + IMX2_WDT_WICR);
++}
++
++static irqreturn_t imx2_wdt_isr(int irq, void *dev_id)
++{
++ u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WICR);
++ if (val & IMX2_WDT_WICR_WTIS) {
++ /*clear interrupt status bit*/
++ __raw_writew(val, imx2_wdt.base + IMX2_WDT_WICR);
++ printk(KERN_INFO "watchdog pre-timeout:%d, %d Seconds remained\n", \
++ imx2_wdt.pretimeout, imx2_wdt.timeout-imx2_wdt.pretimeout);
++ }
++ return IRQ_HANDLED;
++}
++
+ static int imx2_wdt_open(struct inode *inode, struct file *file)
+ {
+ if (test_and_set_bit(IMX2_WDT_STATUS_OPEN, &imx2_wdt.status))
+@@ -164,7 +205,7 @@
+ {
+ if (test_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status) && !nowayout)
+ imx2_wdt_stop();
+- else {
++ else if (!timer_pending(&imx2_wdt.timer)) {
+ dev_crit(imx2_wdt_miscdev.parent,
+ "Unexpected close: Expect reboot!\n");
+ imx2_wdt_ping();
+@@ -213,6 +254,26 @@
+ case WDIOC_GETTIMEOUT:
+ return put_user(imx2_wdt.timeout, p);
+
++ case WDIOC_SETPRETIMEOUT:
++ if (get_user(new_value, p))
++ return -EFAULT;
++ if ((new_value < 0) || (new_value >= imx2_wdt.timeout))
++ return -EINVAL;
++ imx2_wdt_set_pretimeout(new_value);
++ imx2_wdt.pretimeout = new_value;
++
++ case WDIOC_GETPRETIMEOUT:
++ return put_user(imx2_wdt.pretimeout, p);
++
++ case WDIOC_SETOPTIONS:
++ if (get_user(new_value, p))
++ return -EFAULT;
++ if (new_value & WDIOS_DISABLECARD)
++ imx2_wdt_stop();
++ if (new_value & WDIOS_ENABLECARD)
++ imx2_wdt_start();
++ return 0;
++
+ default:
+ return -ENOTTY;
+ }
+@@ -258,6 +319,7 @@
+ static int __init imx2_wdt_probe(struct platform_device *pdev)
+ {
+ int ret;
++ int irq;
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+@@ -271,6 +333,19 @@
+ return PTR_ERR(imx2_wdt.clk);
+ }
+
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ ret = irq;
++ goto fail;
++ }
++
++ ret = devm_request_irq(&pdev->dev, irq, imx2_wdt_isr, 0,
++ dev_name(&pdev->dev), NULL);
++ if (ret) {
++ dev_err(&pdev->dev, "can't get irq %d\n", irq);
++ goto fail;
++ }
++
+ imx2_wdt.timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
+ if (imx2_wdt.timeout != timeout)
+ dev_warn(&pdev->dev, "Initial timeout out of range! "
+diff -Nur linux-3.14.72.orig/firmware/imx/epdc_E060SCM.fw.ihex linux-3.14.72/firmware/imx/epdc_E060SCM.fw.ihex
+--- linux-3.14.72.orig/firmware/imx/epdc_E060SCM.fw.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/firmware/imx/epdc_E060SCM.fw.ihex 2016-06-19 22:11:55.389134495 +0200
+@@ -0,0 +1,61613 @@
++:100000003488C47C012D0100DD0900000706A4002E
++:100010000358211D3CCA018502000000400000FE7B
++:100020004700000100040D00FFFC00000000005428
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++:100060004F0E00000000009800000000000000A0FB
++:1000700065000000000000A8BC000000000000B007
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+diff -Nur linux-3.14.72.orig/firmware/imx/epdc_E60_V220.fw.ihex linux-3.14.72/firmware/imx/epdc_E60_V220.fw.ihex
+--- linux-3.14.72.orig/firmware/imx/epdc_E60_V220.fw.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/firmware/imx/epdc_E60_V220.fw.ihex 2016-06-19 22:11:55.461129770 +0200
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++++ linux-3.14.72/firmware/imx/epdc_E97_V110.fw.ihex 2016-06-19 22:11:55.489127934 +0200
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++:104E000000000000000000000000000000000000A2
++:104E10000000000000000000000000000000000092
++:00000001FF
+diff -Nur linux-3.14.72.orig/firmware/imx/sdma/sdma-imx6q.bin.ihex linux-3.14.72/firmware/imx/sdma/sdma-imx6q.bin.ihex
+--- linux-3.14.72.orig/firmware/imx/sdma/sdma-imx6q.bin.ihex 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/firmware/imx/sdma/sdma-imx6q.bin.ihex 2016-06-19 22:11:55.489127934 +0200
+@@ -0,0 +1,130 @@
++:1000000053444D4103000000010000001C000000AB
++:1000100029000000C0000000480700008202000024
++:10002000FFFFFFFF00000000FFFFFFFFFFFFFFFFDC
++:10003000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD0
++:10004000FFFFFFFFFFFFFFFFFA1900004B04000056
++:10005000EB020000A8180000FFFFFFFF581A000085
++:10006000FFFFFFFFC0030000FFFFFFFFFFFFFFFFD9
++:10007000FFFFFFFFAB020000FFFFFFFF7B0300005D
++:10008000FFFFFFFFFFFFFFFF4C0400006E040000B6
++:10009000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF70
++:1000A00000000000001800004F180000A619000012
++:1000B000071B0000A21A00003E1B000000180000F1
++:1000C000E3C1DB57F352016AFB52D36AFB521C1A9D
++:1000D000C36AE8621102FF3A3008D002337C8F0015
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++:10014000DF6D077F0000EB55004D077DFAC1DB57DF
++:1001500006980700CC680C6813C20AC20198D9C17E
++:10016000E3C1DB57E35FE357F352216A8F00D50009
++:10017000017D8D00A005EB5DFB567804037D7904BD
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++:100190006003057D0965377E0A62357E73980A62C1
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++:1003200006780255045D4F070255245D2F07017CB6
++:100330008D9917006F07017C012093559D000700E0
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++:10036000A00602780255C86D0F7C004E087C690714
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++:100710000B670F7E04080278C86F12070A7CDD6F32
++:10072000087FD169010FC86FDD6F037F01010004ED
++:10073000139B0700FF680C680002139B83DBDB57E9
++:10074000F352056AFB52C76A8F00D500017D8D0008
++:10075000A0057804037D79041C7D157C79041E7C3A
++:10076000EE56C862287E6006027D10021202096AF7
++:10077000227F1202096A1F7F1202096A1C7F03206E
++:100780000048EF7C729B150015000278C8620B6A66
++:10079000719B15000278C8620A6A719B0278C86270
++:1007A000096A097C286A077F004D077DD35201083A
++:1007B00002580004429B77C25404D35201080258E5
++:1007C00001049BDB3F9B700B11031353DB5F0A0794
++:1007D000D3588B00FB5E3CC1157DC05AC85B4EC12F
++:1007E000117C8803F05DFF0D1105FF1DBC05004D58
++:1007F000047D9A9B0807DB5F0A078B00C352CB532B
++:0808000059C1EC7D00028B9B45
++:00000001FF
+diff -Nur linux-3.14.72.orig/firmware/Makefile linux-3.14.72/firmware/Makefile
+--- linux-3.14.72.orig/firmware/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/firmware/Makefile 2016-06-19 22:11:55.493127671 +0200
+@@ -61,6 +61,7 @@
+ radeon/RV770_pfp.bin radeon/RV770_me.bin \
+ radeon/RV730_pfp.bin radeon/RV730_me.bin \
+ radeon/RV710_pfp.bin radeon/RV710_me.bin
++fw-shipped-$(CONFIG_IMX_SDMA) += imx/sdma/sdma-imx6q.bin
+ fw-shipped-$(CONFIG_DVB_AV7110) += av7110/bootcode.bin
+ fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
+ fw-shipped-$(CONFIG_E100) += e100/d101m_ucode.bin e100/d101s_ucode.bin \
+@@ -135,6 +136,10 @@
+ fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
+ fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
+ fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
++fw-shipped-$(CONFIG_FB_MXC_EINK_PANEL) += imx/epdc_E60_V110.fw \
++ imx/epdc_E60_V220.fw \
++ imx/epdc_E97_V110.fw \
++ imx/epdc_E060SCM.fw
+
+ fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
+
+diff -Nur linux-3.14.72.orig/include/asm-generic/early_ioremap.h linux-3.14.72/include/asm-generic/early_ioremap.h
+--- linux-3.14.72.orig/include/asm-generic/early_ioremap.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/asm-generic/early_ioremap.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,42 @@
++#ifndef _ASM_EARLY_IOREMAP_H_
++#define _ASM_EARLY_IOREMAP_H_
++
++#include <linux/types.h>
++
++/*
++ * early_ioremap() and early_iounmap() are for temporary early boot-time
++ * mappings, before the real ioremap() is functional.
++ */
++extern void __iomem *early_ioremap(resource_size_t phys_addr,
++ unsigned long size);
++extern void *early_memremap(resource_size_t phys_addr,
++ unsigned long size);
++extern void early_iounmap(void __iomem *addr, unsigned long size);
++extern void early_memunmap(void *addr, unsigned long size);
++
++/*
++ * Weak function called by early_ioremap_reset(). It does nothing, but
++ * architectures may provide their own version to do any needed cleanups.
++ */
++extern void early_ioremap_shutdown(void);
++
++#if defined(CONFIG_GENERIC_EARLY_IOREMAP) && defined(CONFIG_MMU)
++/* Arch-specific initialization */
++extern void early_ioremap_init(void);
++
++/* Generic initialization called by architecture code */
++extern void early_ioremap_setup(void);
++
++/*
++ * Called as last step in paging_init() so library can act
++ * accordingly for subsequent map/unmap requests.
++ */
++extern void early_ioremap_reset(void);
++
++#else
++static inline void early_ioremap_init(void) { }
++static inline void early_ioremap_setup(void) { }
++static inline void early_ioremap_reset(void) { }
++#endif
++
++#endif /* _ASM_EARLY_IOREMAP_H_ */
+diff -Nur linux-3.14.72.orig/include/dt-bindings/clock/imx6qdl-clock.h linux-3.14.72/include/dt-bindings/clock/imx6qdl-clock.h
+--- linux-3.14.72.orig/include/dt-bindings/clock/imx6qdl-clock.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/dt-bindings/clock/imx6qdl-clock.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,261 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_IMX6QDL_H
++#define __DT_BINDINGS_CLOCK_IMX6QDL_H
++
++#define IMX6QDL_CLK_DUMMY 0
++#define IMX6QDL_CLK_CKIL 1
++#define IMX6QDL_CLK_CKIH 2
++#define IMX6QDL_CLK_OSC 3
++#define IMX6QDL_CLK_PLL2_PFD0_352M 4
++#define IMX6QDL_CLK_PLL2_PFD1_594M 5
++#define IMX6QDL_CLK_PLL2_PFD2_396M 6
++#define IMX6QDL_CLK_PLL3_PFD0_720M 7
++#define IMX6QDL_CLK_PLL3_PFD1_540M 8
++#define IMX6QDL_CLK_PLL3_PFD2_508M 9
++#define IMX6QDL_CLK_PLL3_PFD3_454M 10
++#define IMX6QDL_CLK_PLL2_198M 11
++#define IMX6QDL_CLK_PLL3_120M 12
++#define IMX6QDL_CLK_PLL3_80M 13
++#define IMX6QDL_CLK_PLL3_60M 14
++#define IMX6QDL_CLK_TWD 15
++#define IMX6QDL_CLK_STEP 16
++#define IMX6QDL_CLK_PLL1_SW 17
++#define IMX6QDL_CLK_PERIPH_PRE 18
++#define IMX6QDL_CLK_PERIPH2_PRE 19
++#define IMX6QDL_CLK_PERIPH_CLK2_SEL 20
++#define IMX6QDL_CLK_PERIPH2_CLK2_SEL 21
++#define IMX6QDL_CLK_AXI_SEL 22
++#define IMX6QDL_CLK_ESAI_SEL 23
++#define IMX6QDL_CLK_ASRC_SEL 24
++#define IMX6QDL_CLK_SPDIF_SEL 25
++#define IMX6QDL_CLK_GPU2D_AXI 26
++#define IMX6QDL_CLK_GPU3D_AXI 27
++#define IMX6QDL_CLK_GPU2D_CORE_SEL 28
++#define IMX6QDL_CLK_GPU3D_CORE_SEL 29
++#define IMX6QDL_CLK_GPU3D_SHADER_SEL 30
++#define IMX6QDL_CLK_IPU1_SEL 31
++#define IMX6QDL_CLK_IPU2_SEL 32
++#define IMX6QDL_CLK_LDB_DI0_SEL 33
++#define IMX6QDL_CLK_LDB_DI1_SEL 34
++#define IMX6QDL_CLK_IPU1_DI0_PRE_SEL 35
++#define IMX6QDL_CLK_IPU1_DI1_PRE_SEL 36
++#define IMX6QDL_CLK_IPU2_DI0_PRE_SEL 37
++#define IMX6QDL_CLK_IPU2_DI1_PRE_SEL 38
++#define IMX6QDL_CLK_IPU1_DI0_SEL 39
++#define IMX6QDL_CLK_IPU1_DI1_SEL 40
++#define IMX6QDL_CLK_IPU2_DI0_SEL 41
++#define IMX6QDL_CLK_IPU2_DI1_SEL 42
++#define IMX6QDL_CLK_HSI_TX_SEL 43
++#define IMX6QDL_CLK_PCIE_AXI_SEL 44
++#define IMX6QDL_CLK_SSI1_SEL 45
++#define IMX6QDL_CLK_SSI2_SEL 46
++#define IMX6QDL_CLK_SSI3_SEL 47
++#define IMX6QDL_CLK_USDHC1_SEL 48
++#define IMX6QDL_CLK_USDHC2_SEL 49
++#define IMX6QDL_CLK_USDHC3_SEL 50
++#define IMX6QDL_CLK_USDHC4_SEL 51
++#define IMX6QDL_CLK_ENFC_SEL 52
++#define IMX6QDL_CLK_EMI_SEL 53
++#define IMX6QDL_CLK_EMI_SLOW_SEL 54
++#define IMX6QDL_CLK_VDO_AXI_SEL 55
++#define IMX6QDL_CLK_VPU_AXI_SEL 56
++#define IMX6QDL_CLK_CKO1_SEL 57
++#define IMX6QDL_CLK_PERIPH 58
++#define IMX6QDL_CLK_PERIPH2 59
++#define IMX6QDL_CLK_PERIPH_CLK2 60
++#define IMX6QDL_CLK_PERIPH2_CLK2 61
++#define IMX6QDL_CLK_IPG 62
++#define IMX6QDL_CLK_IPG_PER 63
++#define IMX6QDL_CLK_ESAI_PRED 64
++#define IMX6QDL_CLK_ESAI_PODF 65
++#define IMX6QDL_CLK_ASRC_PRED 66
++#define IMX6QDL_CLK_ASRC_PODF 67
++#define IMX6QDL_CLK_SPDIF_PRED 68
++#define IMX6QDL_CLK_SPDIF_PODF 69
++#define IMX6QDL_CLK_CAN_ROOT 70
++#define IMX6QDL_CLK_ECSPI_ROOT 71
++#define IMX6QDL_CLK_GPU2D_CORE_PODF 72
++#define IMX6QDL_CLK_GPU3D_CORE_PODF 73
++#define IMX6QDL_CLK_GPU3D_SHADER 74
++#define IMX6QDL_CLK_IPU1_PODF 75
++#define IMX6QDL_CLK_IPU2_PODF 76
++#define IMX6QDL_CLK_IPU1_DI0_PRE 79
++#define IMX6QDL_CLK_IPU1_DI1_PRE 80
++#define IMX6QDL_CLK_IPU2_DI0_PRE 81
++#define IMX6QDL_CLK_IPU2_DI1_PRE 82
++#define IMX6QDL_CLK_HSI_TX_PODF 83
++#define IMX6QDL_CLK_SSI1_PRED 84
++#define IMX6QDL_CLK_SSI1_PODF 85
++#define IMX6QDL_CLK_SSI2_PRED 86
++#define IMX6QDL_CLK_SSI2_PODF 87
++#define IMX6QDL_CLK_SSI3_PRED 88
++#define IMX6QDL_CLK_SSI3_PODF 89
++#define IMX6QDL_CLK_UART_SERIAL_PODF 90
++#define IMX6QDL_CLK_USDHC1_PODF 91
++#define IMX6QDL_CLK_USDHC2_PODF 92
++#define IMX6QDL_CLK_USDHC3_PODF 93
++#define IMX6QDL_CLK_USDHC4_PODF 94
++#define IMX6QDL_CLK_ENFC_PRED 95
++#define IMX6QDL_CLK_ENFC_PODF 96
++#define IMX6QDL_CLK_EMI_PODF 97
++#define IMX6QDL_CLK_EMI_SLOW_PODF 98
++#define IMX6QDL_CLK_VPU_AXI_PODF 99
++#define IMX6QDL_CLK_CKO1_PODF 100
++#define IMX6QDL_CLK_AXI 101
++#define IMX6QDL_CLK_ARM 104
++#define IMX6QDL_CLK_AHB 105
++#define IMX6QDL_CLK_APBH_DMA 106
++#define IMX6QDL_CLK_ASRC 107
++#define IMX6QDL_CLK_CAN1_IPG 108
++#define IMX6QDL_CLK_CAN1_SERIAL 109
++#define IMX6QDL_CLK_CAN2_IPG 110
++#define IMX6QDL_CLK_CAN2_SERIAL 111
++#define IMX6QDL_CLK_ECSPI1 112
++#define IMX6QDL_CLK_ECSPI2 113
++#define IMX6QDL_CLK_ECSPI3 114
++#define IMX6QDL_CLK_ECSPI4 115
++#define IMX6Q_CLK_ECSPI5 116
++#define IMX6DL_CLK_I2C4 116
++#define IMX6QDL_CLK_ENET 117
++#define IMX6QDL_CLK_ESAI_EXTAL 118
++#define IMX6QDL_CLK_GPT_IPG 119
++#define IMX6QDL_CLK_GPT_IPG_PER 120
++#define IMX6QDL_CLK_GPU2D_CORE 121
++#define IMX6QDL_CLK_GPU3D_CORE 122
++#define IMX6QDL_CLK_HDMI_IAHB 123
++#define IMX6QDL_CLK_HDMI_ISFR 124
++#define IMX6QDL_CLK_I2C1 125
++#define IMX6QDL_CLK_I2C2 126
++#define IMX6QDL_CLK_I2C3 127
++#define IMX6QDL_CLK_IIM 128
++#define IMX6QDL_CLK_ENFC 129
++#define IMX6QDL_CLK_IPU1 130
++#define IMX6QDL_CLK_IPU1_DI0 131
++#define IMX6QDL_CLK_IPU1_DI1 132
++#define IMX6QDL_CLK_IPU2 133
++#define IMX6QDL_CLK_IPU2_DI0 134
++#define IMX6QDL_CLK_LDB_DI0 135
++#define IMX6QDL_CLK_LDB_DI1 136
++#define IMX6QDL_CLK_IPU2_DI1 137
++#define IMX6QDL_CLK_HSI_TX 138
++#define IMX6QDL_CLK_MLB 139
++#define IMX6QDL_CLK_MMDC_CH0_AXI 140
++#define IMX6QDL_CLK_MMDC_CH1_AXI 141
++#define IMX6QDL_CLK_OCRAM 142
++#define IMX6QDL_CLK_OPENVG_AXI 143
++#define IMX6QDL_CLK_PCIE_AXI 144
++#define IMX6QDL_CLK_PWM1 145
++#define IMX6QDL_CLK_PWM2 146
++#define IMX6QDL_CLK_PWM3 147
++#define IMX6QDL_CLK_PWM4 148
++#define IMX6QDL_CLK_PER1_BCH 149
++#define IMX6QDL_CLK_GPMI_BCH_APB 150
++#define IMX6QDL_CLK_GPMI_BCH 151
++#define IMX6QDL_CLK_GPMI_IO 152
++#define IMX6QDL_CLK_GPMI_APB 153
++#define IMX6QDL_CLK_SATA 154
++#define IMX6QDL_CLK_SDMA 155
++#define IMX6QDL_CLK_SPBA 156
++#define IMX6QDL_CLK_SSI1 157
++#define IMX6QDL_CLK_SSI2 158
++#define IMX6QDL_CLK_SSI3 159
++#define IMX6QDL_CLK_UART_IPG 160
++#define IMX6QDL_CLK_UART_SERIAL 161
++#define IMX6QDL_CLK_USBOH3 162
++#define IMX6QDL_CLK_USDHC1 163
++#define IMX6QDL_CLK_USDHC2 164
++#define IMX6QDL_CLK_USDHC3 165
++#define IMX6QDL_CLK_USDHC4 166
++#define IMX6QDL_CLK_VDO_AXI 167
++#define IMX6QDL_CLK_VPU_AXI 168
++#define IMX6QDL_CLK_CKO1 169
++#define IMX6QDL_CLK_PLL1_SYS 170
++#define IMX6QDL_CLK_PLL2_BUS 171
++#define IMX6QDL_CLK_PLL3_USB_OTG 172
++#define IMX6QDL_CLK_PLL4_AUDIO 173
++#define IMX6QDL_CLK_PLL5_VIDEO 174
++#define IMX6QDL_CLK_PLL8_MLB 175
++#define IMX6QDL_CLK_PLL7_USB_HOST 176
++#define IMX6QDL_CLK_PLL6_ENET 177
++#define IMX6QDL_CLK_SSI1_IPG 178
++#define IMX6QDL_CLK_SSI2_IPG 179
++#define IMX6QDL_CLK_SSI3_IPG 180
++#define IMX6QDL_CLK_ROM 181
++#define IMX6QDL_CLK_USBPHY1 182
++#define IMX6QDL_CLK_USBPHY2 183
++#define IMX6QDL_CLK_LDB_DI0_DIV_3_5 184
++#define IMX6QDL_CLK_LDB_DI1_DIV_3_5 185
++#define IMX6QDL_CLK_SATA_REF 186
++#define IMX6QDL_CLK_SATA_REF_100M 187
++#define IMX6QDL_CLK_PCIE_REF 188
++#define IMX6QDL_CLK_PCIE_REF_125M 189
++#define IMX6QDL_CLK_ENET_REF 190
++#define IMX6QDL_CLK_USBPHY1_GATE 191
++#define IMX6QDL_CLK_USBPHY2_GATE 192
++#define IMX6QDL_CLK_PLL4_POST_DIV 193
++#define IMX6QDL_CLK_PLL5_POST_DIV 194
++#define IMX6QDL_CLK_PLL5_VIDEO_DIV 195
++#define IMX6QDL_CLK_EIM_SLOW 196
++#define IMX6QDL_CLK_SPDIF 197
++#define IMX6QDL_CLK_CKO2_SEL 198
++#define IMX6QDL_CLK_CKO2_PODF 199
++#define IMX6QDL_CLK_CKO2 200
++#define IMX6QDL_CLK_CKO 201
++#define IMX6QDL_CLK_VDOA 202
++#define IMX6QDL_CLK_PLL4_AUDIO_DIV 203
++#define IMX6QDL_CLK_LVDS1_SEL 204
++#define IMX6QDL_CLK_LVDS2_SEL 205
++#define IMX6QDL_CLK_LVDS1_GATE 206
++#define IMX6QDL_CLK_LVDS2_GATE 207
++#define IMX6QDL_CLK_ESAI_MEM 208
++#define IMX6QDL_CLK_LDB_DI0_DIV_7 209
++#define IMX6QDL_CLK_LDB_DI1_DIV_7 210
++#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 211
++#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 212
++#define IMX6QDL_CLK_VIDEO_27M 213
++#define IMX6QDL_CLK_DCIC1 214
++#define IMX6QDL_CLK_DCIC2 215
++#define IMX6QDL_CLK_GPT_3M 216
++#define IMX6QDL_CLK_ESAI_IPG 217
++#define IMX6QDL_CLK_ASRC_IPG 218
++#define IMX6QDL_CLK_ASRC_MEM 219
++#define IMX6QDL_CLK_LVDS1_IN 220
++#define IMX6QDL_CLK_LVDS2_IN 221
++#define IMX6QDL_CLK_ANACLK1 222
++#define IMX6QDL_CLK_ANACLK2 223
++#define IMX6QDL_PLL1_BYPASS_SRC 224
++#define IMX6QDL_PLL2_BYPASS_SRC 225
++#define IMX6QDL_PLL3_BYPASS_SRC 226
++#define IMX6QDL_PLL4_BYPASS_SRC 227
++#define IMX6QDL_PLL5_BYPASS_SRC 228
++#define IMX6QDL_PLL6_BYPASS_SRC 229
++#define IMX6QDL_PLL7_BYPASS_SRC 230
++#define IMX6QDL_CLK_PLL1 231
++#define IMX6QDL_CLK_PLL2 232
++#define IMX6QDL_CLK_PLL3 233
++#define IMX6QDL_CLK_PLL4 234
++#define IMX6QDL_CLK_PLL5 235
++#define IMX6QDL_CLK_PLL6 236
++#define IMX6QDL_CLK_PLL7 237
++#define IMX6QDL_PLL1_BYPASS 238
++#define IMX6QDL_PLL2_BYPASS 239
++#define IMX6QDL_PLL3_BYPASS 240
++#define IMX6QDL_PLL4_BYPASS 241
++#define IMX6QDL_PLL5_BYPASS 242
++#define IMX6QDL_PLL6_BYPASS 243
++#define IMX6QDL_PLL7_BYPASS 244
++#define IMX6QDL_CLK_AXI_ALT_SEL 245
++#define IMX6QDL_CAAM_MEM 246
++#define IMX6QDL_CAAM_ACLK 247
++#define IMX6QDL_CAAM_IPG 248
++#define IMX6QDL_CLK_SPDIF_GCLK 249
++#define IMX6QDL_CLK_END 250
++
++#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
+diff -Nur linux-3.14.72.orig/include/dt-bindings/clock/imx6sl-clock.h linux-3.14.72/include/dt-bindings/clock/imx6sl-clock.h
+--- linux-3.14.72.orig/include/dt-bindings/clock/imx6sl-clock.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/dt-bindings/clock/imx6sl-clock.h 2016-06-19 22:11:55.493127671 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -145,6 +145,37 @@
+ #define IMX6SL_CLK_USDHC4 132
+ #define IMX6SL_CLK_PLL4_AUDIO_DIV 133
+ #define IMX6SL_CLK_SPBA 134
+-#define IMX6SL_CLK_END 135
++#define IMX6SL_CLK_LVDS1_SEL 135
++#define IMX6SL_CLK_LVDS1_OUT 136
++#define IMX6SL_CLK_LVDS1_IN 137
++#define IMX6SL_CLK_ANACLK1 138
++#define IMX6SL_PLL1_BYPASS_SRC 139
++#define IMX6SL_PLL2_BYPASS_SRC 140
++#define IMX6SL_PLL3_BYPASS_SRC 141
++#define IMX6SL_PLL4_BYPASS_SRC 142
++#define IMX6SL_PLL5_BYPASS_SRC 143
++#define IMX6SL_PLL6_BYPASS_SRC 144
++#define IMX6SL_PLL7_BYPASS_SRC 145
++#define IMX6SL_CLK_PLL1 146
++#define IMX6SL_CLK_PLL2 147
++#define IMX6SL_CLK_PLL3 148
++#define IMX6SL_CLK_PLL4 149
++#define IMX6SL_CLK_PLL5 150
++#define IMX6SL_CLK_PLL6 151
++#define IMX6SL_CLK_PLL7 152
++#define IMX6SL_PLL1_BYPASS 153
++#define IMX6SL_PLL2_BYPASS 154
++#define IMX6SL_PLL3_BYPASS 155
++#define IMX6SL_PLL4_BYPASS 156
++#define IMX6SL_PLL5_BYPASS 157
++#define IMX6SL_PLL6_BYPASS 158
++#define IMX6SL_PLL7_BYPASS 159
++#define IMX6SL_CLK_SSI1_IPG 160
++#define IMX6SL_CLK_SSI2_IPG 161
++#define IMX6SL_CLK_SSI3_IPG 162
++#define IMX6SL_CLK_UART_OSC_4M 163
++#define IMX6SL_CLK_SPDIF_GCLK 164
++#define IMX6SL_CLK_END 165
+
++
+ #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
+diff -Nur linux-3.14.72.orig/include/dt-bindings/clock/imx6sx-clock.h linux-3.14.72/include/dt-bindings/clock/imx6sx-clock.h
+--- linux-3.14.72.orig/include/dt-bindings/clock/imx6sx-clock.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/dt-bindings/clock/imx6sx-clock.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,285 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
++#define __DT_BINDINGS_CLOCK_IMX6SX_H
++
++#define IMX6SX_CLK_DUMMY 0
++#define IMX6SX_CLK_CKIL 1
++#define IMX6SX_CLK_CKIH 2
++#define IMX6SX_CLK_OSC 3
++#define IMX6SX_CLK_PLL1_SYS 4
++#define IMX6SX_CLK_PLL2_BUS 5
++#define IMX6SX_CLK_PLL3_USB_OTG 6
++#define IMX6SX_CLK_PLL4_AUDIO 7
++#define IMX6SX_CLK_PLL5_VIDEO 8
++#define IMX6SX_CLK_PLL6_ENET 9
++#define IMX6SX_CLK_PLL7_USB_HOST 10
++#define IMX6SX_CLK_USBPHY1 11
++#define IMX6SX_CLK_USBPHY2 12
++#define IMX6SX_CLK_USBPHY1_GATE 13
++#define IMX6SX_CLK_USBPHY2_GATE 14
++#define IMX6SX_CLK_PCIE_REF 15
++#define IMX6SX_CLK_PCIE_REF_125M 16
++#define IMX6SX_CLK_ENET_REF 17
++#define IMX6SX_CLK_PLL2_PFD0 18
++#define IMX6SX_CLK_PLL2_PFD1 19
++#define IMX6SX_CLK_PLL2_PFD2 20
++#define IMX6SX_CLK_PLL2_PFD3 21
++#define IMX6SX_CLK_PLL3_PFD0 22
++#define IMX6SX_CLK_PLL3_PFD1 23
++#define IMX6SX_CLK_PLL3_PFD2 24
++#define IMX6SX_CLK_PLL3_PFD3 25
++#define IMX6SX_CLK_PLL2_198M 26
++#define IMX6SX_CLK_PLL3_120M 27
++#define IMX6SX_CLK_PLL3_80M 28
++#define IMX6SX_CLK_PLL3_60M 29
++#define IMX6SX_CLK_TWD 30
++#define IMX6SX_CLK_PLL4_POST_DIV 31
++#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
++#define IMX6SX_CLK_PLL5_POST_DIV 33
++#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
++#define IMX6SX_CLK_STEP 35
++#define IMX6SX_CLK_PLL1_SW 36
++#define IMX6SX_CLK_OCRAM_SEL 37
++#define IMX6SX_CLK_PERIPH_PRE 38
++#define IMX6SX_CLK_PERIPH2_PRE 39
++#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
++#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
++#define IMX6SX_CLK_PCIE_AXI_SEL 42
++#define IMX6SX_CLK_GPU_AXI_SEL 43
++#define IMX6SX_CLK_GPU_CORE_SEL 44
++#define IMX6SX_CLK_EIM_SLOW_SEL 45
++#define IMX6SX_CLK_USDHC1_SEL 46
++#define IMX6SX_CLK_USDHC2_SEL 47
++#define IMX6SX_CLK_USDHC3_SEL 48
++#define IMX6SX_CLK_USDHC4_SEL 49
++#define IMX6SX_CLK_SSI1_SEL 50
++#define IMX6SX_CLK_SSI2_SEL 51
++#define IMX6SX_CLK_SSI3_SEL 52
++#define IMX6SX_CLK_QSPI1_SEL 53
++#define IMX6SX_CLK_PERCLK_SEL 54
++#define IMX6SX_CLK_VID_SEL 55
++#define IMX6SX_CLK_ESAI_SEL 56
++#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
++#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
++#define IMX6SX_CLK_CAN_SEL 59
++#define IMX6SX_CLK_UART_SEL 60
++#define IMX6SX_CLK_QSPI2_SEL 61
++#define IMX6SX_CLK_LDB_DI1_SEL 62
++#define IMX6SX_CLK_LDB_DI0_SEL 63
++#define IMX6SX_CLK_SPDIF_SEL 64
++#define IMX6SX_CLK_AUDIO_SEL 65
++#define IMX6SX_CLK_ENET_PRE_SEL 66
++#define IMX6SX_CLK_ENET_SEL 67
++#define IMX6SX_CLK_M4_PRE_SEL 68
++#define IMX6SX_CLK_M4_SEL 69
++#define IMX6SX_CLK_ECSPI_SEL 70
++#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
++#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
++#define IMX6SX_CLK_LCDIF1_SEL 73
++#define IMX6SX_CLK_LCDIF2_SEL 74
++#define IMX6SX_CLK_DISPLAY_SEL 75
++#define IMX6SX_CLK_CSI_SEL 76
++#define IMX6SX_CLK_CKO1_SEL 77
++#define IMX6SX_CLK_CKO2_SEL 78
++#define IMX6SX_CLK_CKO 79
++#define IMX6SX_CLK_PERIPH_CLK2 80
++#define IMX6SX_CLK_PERIPH2_CLK2 81
++#define IMX6SX_CLK_IPG 82
++#define IMX6SX_CLK_GPU_CORE_PODF 83
++#define IMX6SX_CLK_GPU_AXI_PODF 84
++#define IMX6SX_CLK_LCDIF1_PODF 85
++#define IMX6SX_CLK_QSPI1_PODF 86
++#define IMX6SX_CLK_EIM_SLOW_PODF 87
++#define IMX6SX_CLK_LCDIF2_PODF 88
++#define IMX6SX_CLK_PERCLK 89
++#define IMX6SX_CLK_VID_PODF 90
++#define IMX6SX_CLK_CAN_PODF 91
++#define IMX6SX_CLK_USDHC1_PODF 92
++#define IMX6SX_CLK_USDHC2_PODF 93
++#define IMX6SX_CLK_USDHC3_PODF 94
++#define IMX6SX_CLK_USDHC4_PODF 95
++#define IMX6SX_CLK_UART_PODF 96
++#define IMX6SX_CLK_ESAI_PRED 97
++#define IMX6SX_CLK_ESAI_PODF 98
++#define IMX6SX_CLK_SSI3_PRED 99
++#define IMX6SX_CLK_SSI3_PODF 100
++#define IMX6SX_CLK_SSI1_PRED 101
++#define IMX6SX_CLK_SSI1_PODF 102
++#define IMX6SX_CLK_QSPI2_PRED 103
++#define IMX6SX_CLK_QSPI2_PODF 104
++#define IMX6SX_CLK_SSI2_PRED 105
++#define IMX6SX_CLK_SSI2_PODF 106
++#define IMX6SX_CLK_SPDIF_PRED 107
++#define IMX6SX_CLK_SPDIF_PODF 108
++#define IMX6SX_CLK_AUDIO_PRED 109
++#define IMX6SX_CLK_AUDIO_PODF 110
++#define IMX6SX_CLK_ENET_PODF 111
++#define IMX6SX_CLK_M4_PODF 112
++#define IMX6SX_CLK_ECSPI_PODF 113
++#define IMX6SX_CLK_LCDIF1_PRED 114
++#define IMX6SX_CLK_LCDIF2_PRED 115
++#define IMX6SX_CLK_DISPLAY_PODF 116
++#define IMX6SX_CLK_CSI_PODF 117
++#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
++#define IMX6SX_CLK_LDB_DI0_DIV_7 119
++#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
++#define IMX6SX_CLK_LDB_DI1_DIV_7 121
++#define IMX6SX_CLK_CKO1_PODF 122
++#define IMX6SX_CLK_CKO2_PODF 123
++#define IMX6SX_CLK_PERIPH 124
++#define IMX6SX_CLK_PERIPH2 125
++#define IMX6SX_CLK_OCRAM 126
++#define IMX6SX_CLK_AHB 127
++#define IMX6SX_CLK_MMDC_PODF 128
++#define IMX6SX_CLK_ARM 129
++#define IMX6SX_CLK_AIPS_TZ1 130
++#define IMX6SX_CLK_AIPS_TZ2 131
++#define IMX6SX_CLK_APBH_DMA 132
++#define IMX6SX_CLK_ASRC_GATE 133
++#define IMX6SX_CLK_CAAM_MEM 134
++#define IMX6SX_CLK_CAAM_ACLK 135
++#define IMX6SX_CLK_CAAM_IPG 136
++#define IMX6SX_CLK_CAN1_IPG 137
++#define IMX6SX_CLK_CAN1_SERIAL 138
++#define IMX6SX_CLK_CAN2_IPG 139
++#define IMX6SX_CLK_CAN2_SERIAL 140
++#define IMX6SX_CLK_CPU_DEBUG 141
++#define IMX6SX_CLK_DCIC1 142
++#define IMX6SX_CLK_DCIC2 143
++#define IMX6SX_CLK_AIPS_TZ3 144
++#define IMX6SX_CLK_ECSPI1 145
++#define IMX6SX_CLK_ECSPI2 146
++#define IMX6SX_CLK_ECSPI3 147
++#define IMX6SX_CLK_ECSPI4 148
++#define IMX6SX_CLK_ECSPI5 149
++#define IMX6SX_CLK_EPIT1 150
++#define IMX6SX_CLK_EPIT2 151
++#define IMX6SX_CLK_ESAI_EXTAL 152
++#define IMX6SX_CLK_WAKEUP 153
++#define IMX6SX_CLK_GPT_BUS 154
++#define IMX6SX_CLK_GPT_SERIAL 155
++#define IMX6SX_CLK_GPU 156
++#define IMX6SX_CLK_OCRAM_S 157
++#define IMX6SX_CLK_CANFD 158
++#define IMX6SX_CLK_CSI 159
++#define IMX6SX_CLK_I2C1 160
++#define IMX6SX_CLK_I2C2 161
++#define IMX6SX_CLK_I2C3 162
++#define IMX6SX_CLK_OCOTP 163
++#define IMX6SX_CLK_IOMUXC 164
++#define IMX6SX_CLK_IPMUX1 165
++#define IMX6SX_CLK_IPMUX2 166
++#define IMX6SX_CLK_IPMUX3 167
++#define IMX6SX_CLK_TZASC1 168
++#define IMX6SX_CLK_LCDIF_APB 169
++#define IMX6SX_CLK_PXP_AXI 170
++#define IMX6SX_CLK_M4 171
++#define IMX6SX_CLK_ENET 172
++#define IMX6SX_CLK_DISPLAY_AXI 173
++#define IMX6SX_CLK_LCDIF2_PIX 174
++#define IMX6SX_CLK_LCDIF1_PIX 175
++#define IMX6SX_CLK_LDB_DI0 176
++#define IMX6SX_CLK_QSPI1 177
++#define IMX6SX_CLK_MLB 178
++#define IMX6SX_CLK_MMDC_P0_FAST 179
++#define IMX6SX_CLK_MMDC_P0_IPG 180
++#define IMX6SX_CLK_AXI 181
++#define IMX6SX_CLK_PCIE_AXI 182
++#define IMX6SX_CLK_QSPI2 183
++#define IMX6SX_CLK_PER1_BCH 184
++#define IMX6SX_CLK_PER2_MAIN 185
++#define IMX6SX_CLK_PWM1 186
++#define IMX6SX_CLK_PWM2 187
++#define IMX6SX_CLK_PWM3 188
++#define IMX6SX_CLK_PWM4 189
++#define IMX6SX_CLK_GPMI_BCH_APB 190
++#define IMX6SX_CLK_GPMI_BCH 191
++#define IMX6SX_CLK_GPMI_IO 192
++#define IMX6SX_CLK_GPMI_APB 193
++#define IMX6SX_CLK_ROM 194
++#define IMX6SX_CLK_SDMA 195
++#define IMX6SX_CLK_SPBA 196
++#define IMX6SX_CLK_SPDIF 197
++#define IMX6SX_CLK_SSI1_IPG 198
++#define IMX6SX_CLK_SSI2_IPG 199
++#define IMX6SX_CLK_SSI3_IPG 200
++#define IMX6SX_CLK_SSI1 201
++#define IMX6SX_CLK_SSI2 202
++#define IMX6SX_CLK_SSI3 203
++#define IMX6SX_CLK_UART_IPG 204
++#define IMX6SX_CLK_UART_SERIAL 205
++#define IMX6SX_CLK_SAI1 206
++#define IMX6SX_CLK_SAI2 207
++#define IMX6SX_CLK_USBOH3 208
++#define IMX6SX_CLK_USDHC1 209
++#define IMX6SX_CLK_USDHC2 210
++#define IMX6SX_CLK_USDHC3 211
++#define IMX6SX_CLK_USDHC4 212
++#define IMX6SX_CLK_EIM_SLOW 213
++#define IMX6SX_CLK_PWM8 214
++#define IMX6SX_CLK_VADC 215
++#define IMX6SX_CLK_GIS 216
++#define IMX6SX_CLK_I2C4 217
++#define IMX6SX_CLK_PWM5 218
++#define IMX6SX_CLK_PWM6 219
++#define IMX6SX_CLK_PWM7 220
++#define IMX6SX_CLK_CKO1 221
++#define IMX6SX_CLK_CKO2 222
++#define IMX6SX_CLK_IPP_DI0 223
++#define IMX6SX_CLK_IPP_DI1 224
++#define IMX6SX_CLK_ENET_AHB 225
++#define IMX6SX_CLK_OCRAM_PODF 226
++#define IMX6SX_CLK_GPT_3M 227
++#define IMX6SX_CLK_ENET_PTP 228
++#define IMX6SX_CLK_ENET_PTP_REF 229
++#define IMX6SX_CLK_ENET2_REF 230
++#define IMX6SX_CLK_ENET2_REF_125M 231
++#define IMX6SX_CLK_AUDIO 232
++#define IMX6SX_CLK_LVDS1_SEL 233
++#define IMX6SX_CLK_LVDS1_OUT 234
++#define IMX6SX_CLK_ASRC_IPG 235
++#define IMX6SX_CLK_ASRC_MEM 236
++#define IMX6SX_CLK_SAI1_IPG 237
++#define IMX6SX_CLK_SAI2_IPG 238
++#define IMX6SX_CLK_ESAI_IPG 239
++#define IMX6SX_CLK_ESAI_MEM 240
++#define IMX6SX_CLK_LVDS1_IN 241
++#define IMX6SX_CLK_ANACLK1 242
++#define IMX6SX_PLL1_BYPASS_SRC 243
++#define IMX6SX_PLL2_BYPASS_SRC 244
++#define IMX6SX_PLL3_BYPASS_SRC 245
++#define IMX6SX_PLL4_BYPASS_SRC 246
++#define IMX6SX_PLL5_BYPASS_SRC 247
++#define IMX6SX_PLL6_BYPASS_SRC 248
++#define IMX6SX_PLL7_BYPASS_SRC 249
++#define IMX6SX_CLK_PLL1 250
++#define IMX6SX_CLK_PLL2 251
++#define IMX6SX_CLK_PLL3 252
++#define IMX6SX_CLK_PLL4 253
++#define IMX6SX_CLK_PLL5 254
++#define IMX6SX_CLK_PLL6 255
++#define IMX6SX_CLK_PLL7 256
++#define IMX6SX_PLL1_BYPASS 257
++#define IMX6SX_PLL2_BYPASS 258
++#define IMX6SX_PLL3_BYPASS 259
++#define IMX6SX_PLL4_BYPASS 260
++#define IMX6SX_PLL5_BYPASS 261
++#define IMX6SX_PLL6_BYPASS 262
++#define IMX6SX_PLL7_BYPASS 263
++#define IMX6SX_CLK_OCRAM_ALT_SEL 264
++#define IMX6SX_CLK_LVDS2_SEL 265
++#define IMX6SX_CLK_LVDS2_OUT 266
++#define IMX6SX_CLK_LVDS2_IN 267
++#define IMX6SX_CLK_ANACLK2 268
++#define IMX6SX_CLK_SPDIF_GCLK 269
++#define IMX6SX_CLK_CLK_END 270
++
++#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
+diff -Nur linux-3.14.72.orig/include/linux/ahci_platform.h linux-3.14.72/include/linux/ahci_platform.h
+--- linux-3.14.72.orig/include/linux/ahci_platform.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/ahci_platform.h 2016-06-19 22:11:55.493127671 +0200
+@@ -19,15 +19,35 @@
+
+ struct device;
+ struct ata_port_info;
++struct ahci_host_priv;
++struct platform_device;
+
++/*
++ * Note ahci_platform_data is deprecated, it is only kept around for use
++ * by the old da850 and spear13xx ahci code.
++ * New drivers should instead declare their own platform_driver struct, and
++ * use ahci_platform* functions in their own probe, suspend and resume methods.
++ */
+ struct ahci_platform_data {
+ int (*init)(struct device *dev, void __iomem *addr);
+ void (*exit)(struct device *dev);
+ int (*suspend)(struct device *dev);
+ int (*resume)(struct device *dev);
+- const struct ata_port_info *ata_port_info;
+- unsigned int force_port_map;
+- unsigned int mask_port_map;
+ };
+
++int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
++void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
++int ahci_platform_enable_resources(struct ahci_host_priv *hpriv);
++void ahci_platform_disable_resources(struct ahci_host_priv *hpriv);
++struct ahci_host_priv *ahci_platform_get_resources(
++ struct platform_device *pdev);
++int ahci_platform_init_host(struct platform_device *pdev,
++ struct ahci_host_priv *hpriv,
++ const struct ata_port_info *pi_template);
++
++int ahci_platform_suspend_host(struct device *dev);
++int ahci_platform_resume_host(struct device *dev);
++int ahci_platform_suspend(struct device *dev);
++int ahci_platform_resume(struct device *dev);
++
+ #endif /* _AHCI_PLATFORM_H */
+diff -Nur linux-3.14.72.orig/include/linux/backlight.h linux-3.14.72/include/linux/backlight.h
+--- linux-3.14.72.orig/include/linux/backlight.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/backlight.h 2016-06-19 22:11:55.493127671 +0200
+@@ -9,6 +9,7 @@
+ #define _LINUX_BACKLIGHT_H
+
+ #include <linux/device.h>
++#include <linux/fb.h>
+ #include <linux/mutex.h>
+ #include <linux/notifier.h>
+
+@@ -104,6 +105,11 @@
+ struct list_head entry;
+
+ struct device dev;
++
++ /* Multiple framebuffers may share one backlight device */
++ bool fb_bl_on[FB_MAX];
++
++ int use_count;
+ };
+
+ static inline void backlight_update_status(struct backlight_device *bd)
+diff -Nur linux-3.14.72.orig/include/linux/bcma/bcma_driver_pcie2.h linux-3.14.72/include/linux/bcma/bcma_driver_pcie2.h
+--- linux-3.14.72.orig/include/linux/bcma/bcma_driver_pcie2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/bcma/bcma_driver_pcie2.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,158 @@
++#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
++#define LINUX_BCMA_DRIVER_PCIE2_H_
++
++#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
++#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
++#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
++#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
++#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
++#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
++#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
++#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
++#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
++#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
++#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
++#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
++#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
++#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
++#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
++#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
++#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
++#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
++#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
++#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
++#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
++#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
++#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
++#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
++#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
++#define BCMA_CORE_PCIE2_DATAINTF 0x0180
++#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
++#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
++#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
++#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
++#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
++#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
++#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
++#define PCIE2_LTR_ACTIVE 2
++#define PCIE2_LTR_ACTIVE_IDLE 1
++#define PCIE2_LTR_SLEEP 0
++#define PCIE2_LTR_FINAL_MASK 0x300
++#define PCIE2_LTR_FINAL_SHIFT 8
++#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
++#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
++#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
++#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
++#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
++#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
++#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
++#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
++#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
++#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
++#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
++#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
++#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
++#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
++#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
++#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
++#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
++#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
++#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
++#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
++#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
++#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
++#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
++#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
++#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
++#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
++#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
++#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
++#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
++#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
++#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
++#define BCMA_CORE_PCIE2_OARR0 0x0D20
++#define BCMA_CORE_PCIE2_OARR1 0x0D28
++#define BCMA_CORE_PCIE2_OARR2 0x0D30
++#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
++#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
++#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
++#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
++#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
++#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
++#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
++#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
++#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
++#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
++#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
++#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
++#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
++#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
++#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
++#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
++#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
++#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
++#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
++#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
++#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
++#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
++
++/* PCIE gen2 config regs */
++#define PCIE2_INTSTATUS 0x090
++#define PCIE2_INTMASK 0x094
++#define PCIE2_SBMBX 0x098
++
++#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
++
++#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
++#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
++#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
++
++struct bcma_drv_pcie2 {
++ struct bcma_device *core;
++};
++
++#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
++#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
++#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
++#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
++
++#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
++#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
++
++void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
++
++#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
+diff -Nur linux-3.14.72.orig/include/linux/bcma/bcma.h linux-3.14.72/include/linux/bcma/bcma.h
+--- linux-3.14.72.orig/include/linux/bcma/bcma.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/bcma/bcma.h 2016-06-19 22:11:55.493127671 +0200
+@@ -6,6 +6,7 @@
+
+ #include <linux/bcma/bcma_driver_chipcommon.h>
+ #include <linux/bcma/bcma_driver_pci.h>
++#include <linux/bcma/bcma_driver_pcie2.h>
+ #include <linux/bcma/bcma_driver_mips.h>
+ #include <linux/bcma/bcma_driver_gmac_cmn.h>
+ #include <linux/ssb/ssb.h> /* SPROM sharing */
+@@ -333,6 +334,7 @@
+
+ struct bcma_drv_cc drv_cc;
+ struct bcma_drv_pci drv_pci[2];
++ struct bcma_drv_pcie2 drv_pcie2;
+ struct bcma_drv_mips drv_mips;
+ struct bcma_drv_gmac_cmn drv_gmac_cmn;
+
+diff -Nur linux-3.14.72.orig/include/linux/busfreq-imx6.h linux-3.14.72/include/linux/busfreq-imx6.h
+--- linux-3.14.72.orig/include/linux/busfreq-imx6.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/busfreq-imx6.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,31 @@
++/*
++ * Copyright 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __ASM_ARCH_MXC_BUSFREQ_H__
++#define __ASM_ARCH_MXC_BUSFREQ_H__
++
++#include <linux/notifier.h>
++/*
++ * This enumerates busfreq mode.
++ */
++enum busfreq_event {
++ LOW_BUSFREQ_ENTER,
++ LOW_BUSFREQ_EXIT,
++};
++
++enum bus_freq_mode {
++ BUS_FREQ_HIGH,
++ BUS_FREQ_MED,
++ BUS_FREQ_AUDIO,
++ BUS_FREQ_LOW,
++};
++void request_bus_freq(enum bus_freq_mode mode);
++void release_bus_freq(enum bus_freq_mode mode);
++int register_busfreq_notifier(struct notifier_block *nb);
++int unregister_busfreq_notifier(struct notifier_block *nb);
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/can/platform/flexcan.h linux-3.14.72/include/linux/can/platform/flexcan.h
+--- linux-3.14.72.orig/include/linux/can/platform/flexcan.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/can/platform/flexcan.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This file is released under the GPLv2
++ *
++ */
++
++#ifndef __CAN_PLATFORM_FLEXCAN_H
++#define __CAN_PLATFORM_FLEXCAN_H
++
++/**
++ * struct flexcan_platform_data - flex CAN controller platform data
++ * @transceiver_enable: - called to power on/off the transceiver
++ *
++ */
++struct flexcan_platform_data {
++ void (*transceiver_switch)(int enable);
++};
++
++#endif /* __CAN_PLATFORM_FLEXCAN_H */
+diff -Nur linux-3.14.72.orig/include/linux/cgroup_subsys.h linux-3.14.72/include/linux/cgroup_subsys.h
+--- linux-3.14.72.orig/include/linux/cgroup_subsys.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/cgroup_subsys.h 2016-06-19 22:11:55.493127671 +0200
+@@ -39,6 +39,10 @@
+ SUBSYS(blkio)
+ #endif
+
++#if IS_SUBSYS_ENABLED(CONFIG_CGROUP_BFQIO)
++SUBSYS(bfqio)
++#endif
++
+ #if IS_SUBSYS_ENABLED(CONFIG_CGROUP_PERF)
+ SUBSYS(perf)
+ #endif
+diff -Nur linux-3.14.72.orig/include/linux/clk/clk-conf.h linux-3.14.72/include/linux/clk/clk-conf.h
+--- linux-3.14.72.orig/include/linux/clk/clk-conf.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/clk/clk-conf.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,20 @@
++/*
++ * Copyright (C) 2014 Samsung Electronics Co., Ltd.
++ * Sylwester Nawrocki <s.nawrocki@samsung.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++struct device_node;
++
++#if defined(CONFIG_OF) && defined(CONFIG_COMMON_CLK)
++int of_clk_set_defaults(struct device_node *node, bool clk_supplier);
++#else
++static inline int of_clk_set_defaults(struct device_node *node,
++ bool clk_supplier)
++{
++ return 0;
++}
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/clk-provider.h linux-3.14.72/include/linux/clk-provider.h
+--- linux-3.14.72.orig/include/linux/clk-provider.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/clk-provider.h 2016-06-19 22:11:55.493127671 +0200
+@@ -30,6 +30,12 @@
+ #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
+ #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+ #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
++/*
++ * Basic mux clk, can't switch parent while there is another basic mux clk
++ * being its child. Otherwise, a glitch might be propagated to downstream
++ * clocks through this child mux.
++ */
++#define CLK_IS_BASIC_MUX BIT(9)
+
+ struct clk_hw;
+
+diff -Nur linux-3.14.72.orig/include/linux/cma.h linux-3.14.72/include/linux/cma.h
+--- linux-3.14.72.orig/include/linux/cma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/cma.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,27 @@
++#ifndef __CMA_H__
++#define __CMA_H__
++
++/*
++ * There is always at least global CMA area and a few optional
++ * areas configured in kernel .config.
++ */
++#ifdef CONFIG_CMA_AREAS
++#define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
++
++#else
++#define MAX_CMA_AREAS (0)
++
++#endif
++
++struct cma;
++
++extern phys_addr_t cma_get_base(struct cma *cma);
++extern unsigned long cma_get_size(struct cma *cma);
++
++extern int __init cma_declare_contiguous(phys_addr_t size,
++ phys_addr_t base, phys_addr_t limit,
++ phys_addr_t alignment, unsigned int order_per_bit,
++ bool fixed, struct cma **res_cma);
++extern struct page *cma_alloc(struct cma *cma, int count, unsigned int align);
++extern bool cma_release(struct cma *cma, struct page *pages, int count);
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/cpufreq.h linux-3.14.72/include/linux/cpufreq.h
+--- linux-3.14.72.orig/include/linux/cpufreq.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/cpufreq.h 2016-06-19 22:11:55.493127671 +0200
+@@ -432,6 +432,9 @@
+ #elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE)
+ extern struct cpufreq_governor cpufreq_gov_conservative;
+ #define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_conservative)
++#elif defined(CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE)
++extern struct cpufreq_governor cpufreq_gov_interactive;
++#define CPUFREQ_DEFAULT_GOVERNOR (&cpufreq_gov_interactive)
+ #endif
+
+ /*********************************************************************
+diff -Nur linux-3.14.72.orig/include/linux/cpu.h linux-3.14.72/include/linux/cpu.h
+--- linux-3.14.72.orig/include/linux/cpu.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/cpu.h 2016-06-19 22:11:55.493127671 +0200
+@@ -226,4 +226,11 @@
+ void arch_cpu_idle_exit(void);
+ void arch_cpu_idle_dead(void);
+
++#define IDLE_START 1
++#define IDLE_END 2
++
++void idle_notifier_register(struct notifier_block *n);
++void idle_notifier_unregister(struct notifier_block *n);
++void idle_notifier_call_chain(unsigned long val);
++
+ #endif /* _LINUX_CPU_H_ */
+diff -Nur linux-3.14.72.orig/include/linux/device_cooling.h linux-3.14.72/include/linux/device_cooling.h
+--- linux-3.14.72.orig/include/linux/device_cooling.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/device_cooling.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,45 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DEVICE_THERMAL_H__
++#define __DEVICE_THERMAL_H__
++
++#include <linux/thermal.h>
++
++#ifdef CONFIG_DEVICE_THERMAL
++int register_devfreq_cooling_notifier(struct notifier_block *nb);
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb);
++struct thermal_cooling_device *devfreq_cooling_register(unsigned long max_state);
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev);
++#else
++static inline
++int register_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline
++int unregister_devfreq_cooling_notifier(struct notifier_block *nb)
++{
++ return 0;
++}
++
++static inline
++struct thermal_cooling_device *devfreq_cooling_register(unsigned long max_state)
++{
++ return NULL;
++}
++
++static inline
++void devfreq_cooling_unregister(struct thermal_cooling_device *cdev)
++{
++ return;
++}
++#endif
++#endif /* __DEVICE_THERMAL_H__ */
+diff -Nur linux-3.14.72.orig/include/linux/dma-contiguous.h linux-3.14.72/include/linux/dma-contiguous.h
+--- linux-3.14.72.orig/include/linux/dma-contiguous.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/dma-contiguous.h 2016-06-19 22:11:55.493127671 +0200
+@@ -53,18 +53,13 @@
+
+ #ifdef __KERNEL__
+
++#include <linux/device.h>
++
+ struct cma;
+ struct page;
+-struct device;
+
+ #ifdef CONFIG_DMA_CMA
+
+-/*
+- * There is always at least global CMA area and a few optional device
+- * private areas configured in kernel .config.
+- */
+-#define MAX_CMA_AREAS (1 + CONFIG_CMA_AREAS)
+-
+ extern struct cma *dma_contiguous_default_area;
+
+ static inline struct cma *dev_get_cma_area(struct device *dev)
+@@ -88,7 +83,8 @@
+ void dma_contiguous_reserve(phys_addr_t addr_limit);
+
+ int __init dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
+- phys_addr_t limit, struct cma **res_cma);
++ phys_addr_t limit, struct cma **res_cma,
++ bool fixed);
+
+ /**
+ * dma_declare_contiguous() - reserve area for contiguous memory handling
+@@ -108,7 +104,7 @@
+ {
+ struct cma *cma;
+ int ret;
+- ret = dma_contiguous_reserve_area(size, base, limit, &cma);
++ ret = dma_contiguous_reserve_area(size, base, limit, &cma, true);
+ if (ret == 0)
+ dev_set_cma_area(dev, cma);
+
+@@ -122,8 +118,6 @@
+
+ #else
+
+-#define MAX_CMA_AREAS (0)
+-
+ static inline struct cma *dev_get_cma_area(struct device *dev)
+ {
+ return NULL;
+@@ -136,7 +130,9 @@
+ static inline void dma_contiguous_reserve(phys_addr_t limit) { }
+
+ static inline int dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base,
+- phys_addr_t limit, struct cma **res_cma) {
++ phys_addr_t limit, struct cma **res_cma,
++ bool fixed)
++{
+ return -ENOSYS;
+ }
+
+diff -Nur linux-3.14.72.orig/include/linux/ethtool.h linux-3.14.72/include/linux/ethtool.h
+--- linux-3.14.72.orig/include/linux/ethtool.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/ethtool.h 2016-06-19 22:11:55.493127671 +0200
+@@ -154,13 +154,23 @@
+ * @reset: Reset (part of) the device, as specified by a bitmask of
+ * flags from &enum ethtool_reset_flags. Returns a negative
+ * error code or zero.
++ * @get_rxfh_key_size: Get the size of the RX flow hash key.
++ * Returns zero if not supported for this specific device.
+ * @get_rxfh_indir_size: Get the size of the RX flow hash indirection table.
+ * Returns zero if not supported for this specific device.
+ * @get_rxfh_indir: Get the contents of the RX flow hash indirection table.
+ * Will not be called if @get_rxfh_indir_size returns zero.
++ * @get_rxfh: Get the contents of the RX flow hash indirection table and hash
++ * key.
++ * Will not be called if @get_rxfh_indir_size and @get_rxfh_key_size
++ * returns zero.
+ * Returns a negative error code or zero.
+ * @set_rxfh_indir: Set the contents of the RX flow hash indirection table.
+ * Will not be called if @get_rxfh_indir_size returns zero.
++ * @set_rxfh: Set the contents of the RX flow hash indirection table and
++ * hash key.
++ * Will not be called if @get_rxfh_indir_size and @get_rxfh_key_size
++ * returns zero.
+ * Returns a negative error code or zero.
+ * @get_channels: Get number of channels.
+ * @set_channels: Set number of channels. Returns a negative error code or
+@@ -229,7 +239,10 @@
+ int (*set_rxnfc)(struct net_device *, struct ethtool_rxnfc *);
+ int (*flash_device)(struct net_device *, struct ethtool_flash *);
+ int (*reset)(struct net_device *, u32 *);
++ u32 (*get_rxfh_key_size)(struct net_device *);
+ u32 (*get_rxfh_indir_size)(struct net_device *);
++ int (*get_rxfh)(struct net_device *, u32 *, u8 *);
++ int (*set_rxfh)(struct net_device *, u32 *, u8 *);
+ int (*get_rxfh_indir)(struct net_device *, u32 *);
+ int (*set_rxfh_indir)(struct net_device *, const u32 *);
+ void (*get_channels)(struct net_device *, struct ethtool_channels *);
+@@ -245,6 +258,10 @@
+ struct ethtool_eeprom *, u8 *);
+ int (*get_eee)(struct net_device *, struct ethtool_eee *);
+ int (*set_eee)(struct net_device *, struct ethtool_eee *);
++ int (*get_tunable)(struct net_device *,
++ const struct ethtool_tunable *, void *);
++ int (*set_tunable)(struct net_device *,
++ const struct ethtool_tunable *, const void *);
+
+
+ };
+diff -Nur linux-3.14.72.orig/include/linux/fec.h linux-3.14.72/include/linux/fec.h
+--- linux-3.14.72.orig/include/linux/fec.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/fec.h 2016-06-19 22:11:55.493127671 +0200
+@@ -19,6 +19,7 @@
+ struct fec_platform_data {
+ phy_interface_t phy;
+ unsigned char mac[ETH_ALEN];
++ void (*sleep_mode_enable)(int enabled);
+ };
+
+ #endif
+diff -Nur linux-3.14.72.orig/include/linux/fsl_otp.h linux-3.14.72/include/linux/fsl_otp.h
+--- linux-3.14.72.orig/include/linux/fsl_otp.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/fsl_otp.h 2016-06-19 22:11:55.493127671 +0200
+@@ -0,0 +1,6 @@
++#ifndef _LINUX_FSL_OTP_H
++#define _LINUX_FSL_OTP_H
++
++int fsl_otp_readl(unsigned long offset, u32 *value);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/hardirq.h linux-3.14.72/include/linux/hardirq.h
+--- linux-3.14.72.orig/include/linux/hardirq.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/hardirq.h 2016-06-19 22:11:55.493127671 +0200
+@@ -9,6 +9,7 @@
+
+
+ extern void synchronize_irq(unsigned int irq);
++extern void synchronize_hardirq(unsigned int irq);
+
+ #if defined(CONFIG_TINY_RCU)
+
+diff -Nur linux-3.14.72.orig/include/linux/imx_gpc.h linux-3.14.72/include/linux/imx_gpc.h
+--- linux-3.14.72.orig/include/linux/imx_gpc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/imx_gpc.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,25 @@
++/*
++ * Copyright (C) 2015 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*
++ * @file linux/imx_gpc.h
++ *
++ * @brief Global header file for imx GPC
++ *
++ * @ingroup GPC
++ */
++#ifndef __LINUX_IMX_GPC_H__
++#define __LINUX_IMX_GPC_H__
++
++int imx_gpc_mf_request_on(unsigned int irq, unsigned int on);
++#endif /* __LINUX_IMX_GPC_H__ */
+diff -Nur linux-3.14.72.orig/include/linux/imx_sema4.h linux-3.14.72/include/linux/imx_sema4.h
+--- linux-3.14.72.orig/include/linux/imx_sema4.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/imx_sema4.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,66 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __LINUX_IMX_SEMA4_H__
++#define __LINUX_IMX_SEMA4_H__
++
++#define SEMA4_NUM_DEVICES 1
++#define SEMA4_NUM_GATES 16
++
++#define SEMA4_UNLOCK 0x00
++#define SEMA4_A9_LOCK 0x01
++#define SEMA4_GATE_MASK 0x03
++
++#define CORE_MUTEX_VALID (('c'<<24)|('m'<<24)|('t'<<24)|'x')
++
++/*
++ * The enumerates
++ */
++enum {
++ /* sema4 registers offset */
++ SEMA4_CP0INE = 0x40,
++ SEMA4_CP1INE = 0x48,
++ SEMA4_CP0NTF = 0x80,
++ SEMA4_CP1NTF = 0x88,
++};
++
++static const unsigned int idx_sema4[16] = {
++ 1 << 7, 1 << 6, 1 << 5, 1 << 4,
++ 1 << 3, 1 << 2, 1 << 1, 1 << 0,
++ 1 << 15, 1 << 14, 1 << 13, 1 << 12,
++ 1 << 11, 1 << 10, 1 << 9, 1 << 8,
++};
++
++struct imx_sema4_mutex {
++ unsigned int valid;
++ unsigned int gate_num;
++ unsigned char gate_val;
++ wait_queue_head_t wait_q;
++};
++
++struct imx_sema4_mutex_device {
++ struct device *dev;
++ unsigned short cpntf_val;
++ unsigned short cpine_val;
++ void __iomem *ioaddr; /* Mapped address */
++ spinlock_t lock; /* Mutex */
++ int irq;
++
++ unsigned short alloced;
++ struct imx_sema4_mutex *mutex_ptr[16];
++};
++
++extern struct imx_sema4_mutex *mcc_shm_ptr;
++
++struct imx_sema4_mutex *
++ imx_sema4_mutex_create(u32 dev_num, u32 mutex_num);
++int imx_sema4_mutex_destroy(struct imx_sema4_mutex *mutex_ptr);
++int imx_sema4_mutex_trylock(struct imx_sema4_mutex *mutex_ptr);
++int imx_sema4_mutex_lock(struct imx_sema4_mutex *mutex_ptr);
++int imx_sema4_mutex_unlock(struct imx_sema4_mutex *mutex_ptr);
++#endif /* __LINUX_IMX_SEMA4_H__ */
+diff -Nur linux-3.14.72.orig/include/linux/ipu.h linux-3.14.72/include/linux/ipu.h
+--- linux-3.14.72.orig/include/linux/ipu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/ipu.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,38 @@
++/*
++ * Copyright 2005-2013 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @defgroup IPU MXC Image Processing Unit (IPU) Driver
++ */
++/*!
++ * @file linux/ipu.h
++ *
++ * @brief This file contains the IPU driver API declarations.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef __LINUX_IPU_H__
++#define __LINUX_IPU_H__
++
++#include <linux/interrupt.h>
++#include <uapi/linux/ipu.h>
++
++unsigned int fmt_to_bpp(unsigned int pixelformat);
++cs_t colorspaceofpixel(int fmt);
++int need_csc(int ifmt, int ofmt);
++
++int ipu_queue_task(struct ipu_task *task);
++int ipu_check_task(struct ipu_task *task);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/ipu-v3.h linux-3.14.72/include/linux/ipu-v3.h
+--- linux-3.14.72.orig/include/linux/ipu-v3.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/ipu-v3.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,760 @@
++/*
++ * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
++ * for more details.
++ */
++
++#ifndef __LINUX_IPU_V3_H_
++#define __LINUX_IPU_V3_H_
++
++#include <linux/ipu.h>
++
++/* IPU Driver channels definitions. */
++/* Note these are different from IDMA channels */
++#define IPU_MAX_CH 32
++#define _MAKE_CHAN(num, v_in, g_in, a_in, out) \
++ ((num << 24) | (v_in << 18) | (g_in << 12) | (a_in << 6) | out)
++#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
++#define IPU_CHAN_ID(ch) (ch >> 24)
++#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
++#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t) (ch >> 6) & 0x3F)
++#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t) (ch >> 12) & 0x3F)
++#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t) (ch >> 18) & 0x3F)
++#define IPU_CHAN_OUT_DMA(ch) ((uint32_t) (ch & 0x3F))
++#define NO_DMA 0x3F
++#define ALT 1
++/*!
++ * Enumeration of IPU logical channels. An IPU logical channel is defined as a
++ * combination of an input (memory to IPU), output (IPU to memory), and/or
++ * secondary input IDMA channels and in some cases an Image Converter task.
++ * Some channels consist of only an input or output.
++ */
++typedef enum {
++ CHAN_NONE = -1,
++ MEM_ROT_ENC_MEM = _MAKE_CHAN(1, 45, NO_DMA, NO_DMA, 48),
++ MEM_ROT_VF_MEM = _MAKE_CHAN(2, 46, NO_DMA, NO_DMA, 49),
++ MEM_ROT_PP_MEM = _MAKE_CHAN(3, 47, NO_DMA, NO_DMA, 50),
++
++ MEM_PRP_ENC_MEM = _MAKE_CHAN(4, 12, 14, 17, 20),
++ MEM_PRP_VF_MEM = _MAKE_CHAN(5, 12, 14, 17, 21),
++ MEM_PP_MEM = _MAKE_CHAN(6, 11, 15, 18, 22),
++
++ MEM_DC_SYNC = _MAKE_CHAN(7, 28, NO_DMA, NO_DMA, NO_DMA),
++ MEM_DC_ASYNC = _MAKE_CHAN(8, 41, NO_DMA, NO_DMA, NO_DMA),
++ MEM_BG_SYNC = _MAKE_CHAN(9, 23, NO_DMA, 51, NO_DMA),
++ MEM_FG_SYNC = _MAKE_CHAN(10, 27, NO_DMA, 31, NO_DMA),
++
++ MEM_BG_ASYNC0 = _MAKE_CHAN(11, 24, NO_DMA, 52, NO_DMA),
++ MEM_FG_ASYNC0 = _MAKE_CHAN(12, 29, NO_DMA, 33, NO_DMA),
++ MEM_BG_ASYNC1 = _MAKE_ALT_CHAN(MEM_BG_ASYNC0),
++ MEM_FG_ASYNC1 = _MAKE_ALT_CHAN(MEM_FG_ASYNC0),
++
++ DIRECT_ASYNC0 = _MAKE_CHAN(13, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++ DIRECT_ASYNC1 = _MAKE_CHAN(14, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++
++ CSI_MEM0 = _MAKE_CHAN(15, NO_DMA, NO_DMA, NO_DMA, 0),
++ CSI_MEM1 = _MAKE_CHAN(16, NO_DMA, NO_DMA, NO_DMA, 1),
++ CSI_MEM2 = _MAKE_CHAN(17, NO_DMA, NO_DMA, NO_DMA, 2),
++ CSI_MEM3 = _MAKE_CHAN(18, NO_DMA, NO_DMA, NO_DMA, 3),
++
++ CSI_MEM = CSI_MEM0,
++
++ CSI_PRP_ENC_MEM = _MAKE_CHAN(19, NO_DMA, NO_DMA, NO_DMA, 20),
++ CSI_PRP_VF_MEM = _MAKE_CHAN(20, NO_DMA, NO_DMA, NO_DMA, 21),
++
++ /* for vdi mem->vdi->ic->mem , add graphics plane and alpha*/
++ MEM_VDI_PRP_VF_MEM_P = _MAKE_CHAN(21, 8, 14, 17, 21),
++ MEM_VDI_PRP_VF_MEM = _MAKE_CHAN(22, 9, 14, 17, 21),
++ MEM_VDI_PRP_VF_MEM_N = _MAKE_CHAN(23, 10, 14, 17, 21),
++
++ /* for vdi mem->vdi->mem */
++ MEM_VDI_MEM_P = _MAKE_CHAN(24, 8, NO_DMA, NO_DMA, 5),
++ MEM_VDI_MEM = _MAKE_CHAN(25, 9, NO_DMA, NO_DMA, 5),
++ MEM_VDI_MEM_N = _MAKE_CHAN(26, 10, NO_DMA, NO_DMA, 5),
++
++ /* fake channel for vdoa to link with IPU */
++ MEM_VDOA_MEM = _MAKE_CHAN(27, NO_DMA, NO_DMA, NO_DMA, NO_DMA),
++
++ MEM_PP_ADC = CHAN_NONE,
++ ADC_SYS2 = CHAN_NONE,
++
++} ipu_channel_t;
++
++/*!
++ * Enumeration of types of buffers for a logical channel.
++ */
++typedef enum {
++ IPU_OUTPUT_BUFFER = 0, /*!< Buffer for output from IPU */
++ IPU_ALPHA_IN_BUFFER = 1, /*!< Buffer for input to IPU */
++ IPU_GRAPH_IN_BUFFER = 2, /*!< Buffer for input to IPU */
++ IPU_VIDEO_IN_BUFFER = 3, /*!< Buffer for input to IPU */
++ IPU_INPUT_BUFFER = IPU_VIDEO_IN_BUFFER,
++ IPU_SEC_INPUT_BUFFER = IPU_GRAPH_IN_BUFFER,
++} ipu_buffer_t;
++
++#define IPU_PANEL_SERIAL 1
++#define IPU_PANEL_PARALLEL 2
++
++/*!
++ * Enumeration of ADC channel operation mode.
++ */
++typedef enum {
++ Disable,
++ WriteTemplateNonSeq,
++ ReadTemplateNonSeq,
++ WriteTemplateUnCon,
++ ReadTemplateUnCon,
++ WriteDataWithRS,
++ WriteDataWoRS,
++ WriteCmd
++} mcu_mode_t;
++
++/*!
++ * Enumeration of ADC channel addressing mode.
++ */
++typedef enum {
++ FullWoBE,
++ FullWithBE,
++ XY
++} display_addressing_t;
++
++struct mipi_fields {
++ uint32_t id;
++ uint32_t vc;
++ bool en;
++};
++/*!
++ * Union of initialization parameters for a logical channel.
++ */
++typedef union {
++ struct {
++ uint32_t csi;
++ struct mipi_fields mipi;
++ bool interlaced;
++ } csi_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ uint32_t csi;
++ struct mipi_fields mipi;
++ } csi_prp_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ } mem_prp_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ } mem_rot_enc_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ ipu_motion_sel motion_sel;
++ enum v4l2_field field_fmt;
++ uint32_t csi;
++ struct mipi_fields mipi;
++ } csi_prp_vf_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ display_port_t disp;
++ uint32_t out_left;
++ uint32_t out_top;
++ } csi_prp_vf_adc;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ ipu_motion_sel motion_sel;
++ enum v4l2_field field_fmt;
++ } mem_prp_vf_mem;
++ struct {
++ uint32_t temp;
++ } mem_prp_vf_adc;
++ struct {
++ uint32_t temp;
++ } mem_rot_vf_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ uint32_t outh_resize_ratio;
++ uint32_t outv_resize_ratio;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ uint32_t in_g_pixel_fmt;
++ uint8_t alpha;
++ uint32_t key_color;
++ bool alpha_chan_en;
++ } mem_pp_mem;
++ struct {
++ uint32_t temp;
++ } mem_rot_mem;
++ struct {
++ uint32_t in_width;
++ uint32_t in_height;
++ uint32_t in_pixel_fmt;
++ uint32_t out_width;
++ uint32_t out_height;
++ uint32_t out_pixel_fmt;
++ bool graphics_combine_en;
++ bool global_alpha_en;
++ bool key_color_en;
++ display_port_t disp;
++ uint32_t out_left;
++ uint32_t out_top;
++ } mem_pp_adc;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ } mem_dc_sync;
++ struct {
++ uint32_t temp;
++ } mem_sdc_fg;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ bool alpha_chan_en;
++ } mem_dp_bg_sync;
++ struct {
++ uint32_t temp;
++ } mem_sdc_bg;
++ struct {
++ uint32_t di;
++ bool interlaced;
++ uint32_t in_pixel_fmt;
++ uint32_t out_pixel_fmt;
++ bool alpha_chan_en;
++ } mem_dp_fg_sync;
++ struct {
++ uint32_t di;
++ } direct_async;
++ struct {
++ display_port_t disp;
++ mcu_mode_t ch_mode;
++ uint32_t out_left;
++ uint32_t out_top;
++ } adc_sys1;
++ struct {
++ display_port_t disp;
++ mcu_mode_t ch_mode;
++ uint32_t out_left;
++ uint32_t out_top;
++ } adc_sys2;
++} ipu_channel_params_t;
++
++/*
++ * IPU_IRQF_ONESHOT - Interrupt is not reenabled after the irq handler finished.
++ */
++#define IPU_IRQF_NONE 0x00000000
++#define IPU_IRQF_ONESHOT 0x00000001
++
++/*!
++ * Enumeration of IPU interrupt sources.
++ */
++enum ipu_irq_line {
++ IPU_IRQ_CSI0_OUT_EOF = 0,
++ IPU_IRQ_CSI1_OUT_EOF = 1,
++ IPU_IRQ_CSI2_OUT_EOF = 2,
++ IPU_IRQ_CSI3_OUT_EOF = 3,
++ IPU_IRQ_VDIC_OUT_EOF = 5,
++ IPU_IRQ_VDI_P_IN_EOF = 8,
++ IPU_IRQ_VDI_C_IN_EOF = 9,
++ IPU_IRQ_VDI_N_IN_EOF = 10,
++ IPU_IRQ_PP_IN_EOF = 11,
++ IPU_IRQ_PRP_IN_EOF = 12,
++ IPU_IRQ_PRP_GRAPH_IN_EOF = 14,
++ IPU_IRQ_PP_GRAPH_IN_EOF = 15,
++ IPU_IRQ_PRP_ALPHA_IN_EOF = 17,
++ IPU_IRQ_PP_ALPHA_IN_EOF = 18,
++ IPU_IRQ_PRP_ENC_OUT_EOF = 20,
++ IPU_IRQ_PRP_VF_OUT_EOF = 21,
++ IPU_IRQ_PP_OUT_EOF = 22,
++ IPU_IRQ_BG_SYNC_EOF = 23,
++ IPU_IRQ_BG_ASYNC_EOF = 24,
++ IPU_IRQ_FG_SYNC_EOF = 27,
++ IPU_IRQ_DC_SYNC_EOF = 28,
++ IPU_IRQ_FG_ASYNC_EOF = 29,
++ IPU_IRQ_FG_ALPHA_SYNC_EOF = 31,
++
++ IPU_IRQ_FG_ALPHA_ASYNC_EOF = 33,
++ IPU_IRQ_DC_READ_EOF = 40,
++ IPU_IRQ_DC_ASYNC_EOF = 41,
++ IPU_IRQ_DC_CMD1_EOF = 42,
++ IPU_IRQ_DC_CMD2_EOF = 43,
++ IPU_IRQ_DC_MASK_EOF = 44,
++ IPU_IRQ_PRP_ENC_ROT_IN_EOF = 45,
++ IPU_IRQ_PRP_VF_ROT_IN_EOF = 46,
++ IPU_IRQ_PP_ROT_IN_EOF = 47,
++ IPU_IRQ_PRP_ENC_ROT_OUT_EOF = 48,
++ IPU_IRQ_PRP_VF_ROT_OUT_EOF = 49,
++ IPU_IRQ_PP_ROT_OUT_EOF = 50,
++ IPU_IRQ_BG_ALPHA_SYNC_EOF = 51,
++ IPU_IRQ_BG_ALPHA_ASYNC_EOF = 52,
++
++ IPU_IRQ_BG_SYNC_NFACK = 64 + 23,
++ IPU_IRQ_FG_SYNC_NFACK = 64 + 27,
++ IPU_IRQ_DC_SYNC_NFACK = 64 + 28,
++
++ IPU_IRQ_DP_SF_START = 448 + 2,
++ IPU_IRQ_DP_SF_END = 448 + 3,
++ IPU_IRQ_BG_SF_END = IPU_IRQ_DP_SF_END,
++ IPU_IRQ_DC_FC_0 = 448 + 8,
++ IPU_IRQ_DC_FC_1 = 448 + 9,
++ IPU_IRQ_DC_FC_2 = 448 + 10,
++ IPU_IRQ_DC_FC_3 = 448 + 11,
++ IPU_IRQ_DC_FC_4 = 448 + 12,
++ IPU_IRQ_DC_FC_6 = 448 + 13,
++ IPU_IRQ_VSYNC_PRE_0 = 448 + 14,
++ IPU_IRQ_VSYNC_PRE_1 = 448 + 15,
++
++ IPU_IRQ_COUNT
++};
++
++/*!
++ * Bitfield of Display Interface signal polarities.
++ */
++typedef struct {
++ unsigned datamask_en:1;
++ unsigned int_clk:1;
++ unsigned interlaced:1;
++ unsigned odd_field_first:1;
++ unsigned clksel_en:1;
++ unsigned clkidle_en:1;
++ unsigned data_pol:1; /* true = inverted */
++ unsigned clk_pol:1; /* true = rising edge */
++ unsigned enable_pol:1;
++ unsigned Hsync_pol:1; /* true = active high */
++ unsigned Vsync_pol:1;
++} ipu_di_signal_cfg_t;
++
++/*!
++ * Bitfield of CSI signal polarities and modes.
++ */
++
++typedef struct {
++ unsigned data_width:4;
++ unsigned clk_mode:3;
++ unsigned ext_vsync:1;
++ unsigned Vsync_pol:1;
++ unsigned Hsync_pol:1;
++ unsigned pixclk_pol:1;
++ unsigned data_pol:1;
++ unsigned sens_clksrc:1;
++ unsigned pack_tight:1;
++ unsigned force_eof:1;
++ unsigned data_en_pol:1;
++ unsigned data_fmt;
++ unsigned csi;
++ unsigned mclk;
++} ipu_csi_signal_cfg_t;
++
++/*!
++ * Enumeration of CSI data bus widths.
++ */
++enum {
++ IPU_CSI_DATA_WIDTH_4 = 0,
++ IPU_CSI_DATA_WIDTH_8 = 1,
++ IPU_CSI_DATA_WIDTH_10 = 3,
++ IPU_CSI_DATA_WIDTH_16 = 9,
++};
++
++/*!
++ * Enumeration of CSI clock modes.
++ */
++enum {
++ IPU_CSI_CLK_MODE_GATED_CLK,
++ IPU_CSI_CLK_MODE_NONGATED_CLK,
++ IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
++ IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
++ IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
++ IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
++};
++
++enum {
++ IPU_CSI_MIPI_DI0,
++ IPU_CSI_MIPI_DI1,
++ IPU_CSI_MIPI_DI2,
++ IPU_CSI_MIPI_DI3,
++};
++
++typedef enum {
++ RGB,
++ YCbCr,
++ YUV
++} ipu_color_space_t;
++
++/*!
++ * Enumeration of ADC vertical sync mode.
++ */
++typedef enum {
++ VsyncNone,
++ VsyncInternal,
++ VsyncCSI,
++ VsyncExternal
++} vsync_t;
++
++typedef enum {
++ DAT,
++ CMD
++} cmddata_t;
++
++/*!
++ * Enumeration of ADC display update mode.
++ */
++typedef enum {
++ IPU_ADC_REFRESH_NONE,
++ IPU_ADC_AUTO_REFRESH,
++ IPU_ADC_AUTO_REFRESH_SNOOP,
++ IPU_ADC_SNOOPING,
++} ipu_adc_update_mode_t;
++
++/*!
++ * Enumeration of ADC display interface types (serial or parallel).
++ */
++enum {
++ IPU_ADC_IFC_MODE_SYS80_TYPE1,
++ IPU_ADC_IFC_MODE_SYS80_TYPE2,
++ IPU_ADC_IFC_MODE_SYS68K_TYPE1,
++ IPU_ADC_IFC_MODE_SYS68K_TYPE2,
++ IPU_ADC_IFC_MODE_3WIRE_SERIAL,
++ IPU_ADC_IFC_MODE_4WIRE_SERIAL,
++ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CLK,
++ IPU_ADC_IFC_MODE_5WIRE_SERIAL_CS,
++};
++
++enum {
++ IPU_ADC_IFC_WIDTH_8,
++ IPU_ADC_IFC_WIDTH_16,
++};
++
++/*!
++ * Enumeration of ADC display interface burst mode.
++ */
++enum {
++ IPU_ADC_BURST_WCS,
++ IPU_ADC_BURST_WBLCK,
++ IPU_ADC_BURST_NONE,
++ IPU_ADC_BURST_SERIAL,
++};
++
++/*!
++ * Enumeration of ADC display interface RW signal timing modes.
++ */
++enum {
++ IPU_ADC_SER_NO_RW,
++ IPU_ADC_SER_RW_BEFORE_RS,
++ IPU_ADC_SER_RW_AFTER_RS,
++};
++
++/*!
++ * Bitfield of ADC signal polarities and modes.
++ */
++typedef struct {
++ unsigned data_pol:1;
++ unsigned clk_pol:1;
++ unsigned cs_pol:1;
++ unsigned rs_pol:1;
++ unsigned addr_pol:1;
++ unsigned read_pol:1;
++ unsigned write_pol:1;
++ unsigned Vsync_pol:1;
++ unsigned burst_pol:1;
++ unsigned burst_mode:2;
++ unsigned ifc_mode:3;
++ unsigned ifc_width:5;
++ unsigned ser_preamble_len:4;
++ unsigned ser_preamble:8;
++ unsigned ser_rw_mode:2;
++} ipu_adc_sig_cfg_t;
++
++/*!
++ * Enumeration of ADC template commands.
++ */
++enum {
++ RD_DATA,
++ RD_ACK,
++ RD_WAIT,
++ WR_XADDR,
++ WR_YADDR,
++ WR_ADDR,
++ WR_CMND,
++ WR_DATA,
++};
++
++/*!
++ * Enumeration of ADC template command flow control.
++ */
++enum {
++ SINGLE_STEP,
++ PAUSE,
++ STOP,
++};
++
++
++/*Define template constants*/
++#define ATM_ADDR_RANGE 0x20 /*offset address of DISP */
++#define TEMPLATE_BUF_SIZE 0x20 /*size of template */
++
++/*!
++ * Define to create ADC template command entry.
++ */
++#define ipu_adc_template_gen(oc, rs, fc, dat) (((rs) << 29) | ((fc) << 27) | \
++ ((oc) << 24) | (dat))
++
++typedef struct {
++ u32 reg;
++ u32 value;
++} ipu_lpmc_reg_t;
++
++#define IPU_LPMC_REG_READ 0x80000000L
++
++#define CSI_MCLK_VF 1
++#define CSI_MCLK_ENC 2
++#define CSI_MCLK_RAW 4
++#define CSI_MCLK_I2C 8
++
++struct ipu_soc;
++/* Common IPU API */
++struct ipu_soc *ipu_get_soc(int id);
++int32_t ipu_init_channel(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params);
++void ipu_uninit_channel(struct ipu_soc *ipu, ipu_channel_t channel);
++
++struct ipu_chan;
++int32_t ipu_channel_request(struct ipu_soc *ipu, ipu_channel_t channel, ipu_channel_params_t *params, struct ipu_chan **p_ipu_chan);
++void ipu_channel_free(struct ipu_chan **p_ipu_chan);
++int32_t ipu_channel_disable(struct ipu_chan *ipu_chan, bool wait_for_stop);
++
++void ipu_disable_hsp_clk(struct ipu_soc *ipu);
++
++static inline bool ipu_can_rotate_in_place(ipu_rotate_mode_t rot)
++{
++#ifdef CONFIG_MXC_IPU_V3D
++ return (rot < IPU_ROTATE_HORIZ_FLIP);
++#else
++ return (rot < IPU_ROTATE_90_RIGHT);
++#endif
++}
++
++int32_t ipu_init_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ ipu_rotate_mode_t rot_mode,
++ dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
++ dma_addr_t phyaddr_2,
++ uint32_t u_offset, uint32_t v_offset);
++
++int32_t ipu_update_channel_buffer(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum, dma_addr_t phyaddr);
++
++int32_t ipu_update_channel_offset(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t pixel_fmt,
++ uint16_t width, uint16_t height,
++ uint32_t stride,
++ uint32_t u, uint32_t v,
++ uint32_t vertical_offset, uint32_t horizontal_offset);
++
++int32_t ipu_select_buffer(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t bufNum);
++int32_t ipu_select_multi_vdi_buffer(struct ipu_soc *ipu, uint32_t bufNum);
++
++int32_t ipu_link_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
++int32_t ipu_unlink_channels(struct ipu_soc *ipu, ipu_channel_t src_ch, ipu_channel_t dest_ch);
++
++int32_t ipu_is_channel_busy(struct ipu_soc *ipu, ipu_channel_t channel);
++int32_t ipu_check_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum);
++void ipu_clear_buffer_ready(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type,
++ uint32_t bufNum);
++uint32_t ipu_get_cur_buffer_idx(struct ipu_soc *ipu, ipu_channel_t channel, ipu_buffer_t type);
++int32_t ipu_enable_channel(struct ipu_soc *ipu, ipu_channel_t channel);
++int32_t ipu_disable_channel(struct ipu_soc *ipu, ipu_channel_t channel, bool wait_for_stop);
++int32_t ipu_swap_channel(struct ipu_soc *ipu, ipu_channel_t from_ch, ipu_channel_t to_ch);
++uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel);
++
++int32_t ipu_enable_csi(struct ipu_soc *ipu, uint32_t csi);
++int32_t ipu_disable_csi(struct ipu_soc *ipu, uint32_t csi);
++
++int ipu_lowpwr_display_enable(void);
++int ipu_lowpwr_display_disable(void);
++
++int ipu_enable_irq(struct ipu_soc *ipu, uint32_t irq);
++void ipu_disable_irq(struct ipu_soc *ipu, uint32_t irq);
++void ipu_clear_irq(struct ipu_soc *ipu, uint32_t irq);
++int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq,
++ irqreturn_t(*handler) (int, void *),
++ uint32_t irq_flags, const char *devname, void *dev_id);
++void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id);
++bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq);
++void ipu_set_csc_coefficients(struct ipu_soc *ipu, ipu_channel_t channel, int32_t param[][3]);
++int32_t ipu_set_channel_bandmode(struct ipu_soc *ipu, ipu_channel_t channel,
++ ipu_buffer_t type, uint32_t band_height);
++
++/* two stripe calculations */
++struct stripe_param{
++ unsigned int input_width; /* width of the input stripe */
++ unsigned int output_width; /* width of the output stripe */
++ unsigned int input_column; /* the first column on the input stripe */
++ unsigned int output_column; /* the first column on the output stripe */
++ unsigned int idr;
++ /* inverse downisizing ratio parameter; expressed as a power of 2 */
++ unsigned int irr;
++ /* inverse resizing ratio parameter; expressed as a multiple of 2^-13 */
++};
++int ipu_calc_stripes_sizes(const unsigned int input_frame_width,
++ unsigned int output_frame_width,
++ const unsigned int maximal_stripe_width,
++ const unsigned long long cirr,
++ const unsigned int equal_stripes,
++ u32 input_pixelformat,
++ u32 output_pixelformat,
++ struct stripe_param *left,
++ struct stripe_param *right);
++
++/* SDC API */
++int32_t ipu_init_sync_panel(struct ipu_soc *ipu, int disp,
++ uint32_t pixel_clk,
++ uint16_t width, uint16_t height,
++ uint32_t pixel_fmt,
++ uint16_t h_start_width, uint16_t h_sync_width,
++ uint16_t h_end_width, uint16_t v_start_width,
++ uint16_t v_sync_width, uint16_t v_end_width,
++ uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
++
++void ipu_uninit_sync_panel(struct ipu_soc *ipu, int disp);
++
++int32_t ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t x_pos,
++ int16_t y_pos);
++int32_t ipu_disp_get_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, int16_t *x_pos,
++ int16_t *y_pos);
++int32_t ipu_disp_set_global_alpha(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ uint8_t alpha);
++int32_t ipu_disp_set_color_key(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ uint32_t colorKey);
++int32_t ipu_disp_set_gamma_correction(struct ipu_soc *ipu, ipu_channel_t channel, bool enable,
++ int constk[], int slopek[]);
++
++int ipu_init_async_panel(struct ipu_soc *ipu, int disp, int type, uint32_t cycle_time,
++ uint32_t pixel_fmt, ipu_adc_sig_cfg_t sig);
++void ipu_disp_direct_write(struct ipu_soc *ipu, ipu_channel_t channel, u32 value, u32 offset);
++void ipu_reset_disp_panel(struct ipu_soc *ipu);
++
++/* CMOS Sensor Interface API */
++int32_t ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height,
++ uint32_t pixel_fmt, ipu_csi_signal_cfg_t sig);
++
++int32_t ipu_csi_get_sensor_protocol(struct ipu_soc *ipu, uint32_t csi);
++
++int32_t ipu_csi_enable_mclk(struct ipu_soc *ipu, int src, bool flag, bool wait);
++
++static inline int32_t ipu_csi_enable_mclk_if(struct ipu_soc *ipu, int src, uint32_t csi,
++ bool flag, bool wait)
++{
++ return ipu_csi_enable_mclk(ipu, csi, flag, wait);
++}
++
++int ipu_csi_read_mclk_flag(void);
++
++void ipu_csi_flash_strobe(bool flag);
++
++void ipu_csi_get_window_size(struct ipu_soc *ipu, uint32_t *width, uint32_t *height, uint32_t csi);
++
++void ipu_csi_set_window_size(struct ipu_soc *ipu, uint32_t width, uint32_t height, uint32_t csi);
++
++void ipu_csi_set_window_pos(struct ipu_soc *ipu, uint32_t left, uint32_t top, uint32_t csi);
++
++void ipu_csi_window_size_crop(struct ipu_soc *ipu, uint32_t swidth, uint32_t sheight,
++ uint32_t width, uint32_t height, uint32_t left, uint32_t top, uint32_t csi);
++
++uint32_t bytes_per_pixel(uint32_t fmt);
++
++bool ipu_ch_param_bad_alpha_pos(uint32_t fmt);
++
++struct ipuv3_fb_platform_data {
++ char disp_dev[32];
++ u32 interface_pix_fmt;
++ char *mode_str;
++ int default_bpp;
++ bool int_clk;
++
++ /* reserved mem */
++ resource_size_t res_base[2];
++ resource_size_t res_size[2];
++
++ /*
++ * Late init to avoid display channel being
++ * re-initialized as we've probably setup the
++ * channel in bootloader.
++ */
++ bool late_init;
++};
++
++#endif /* __LINUX_IPU_V3_H_ */
+diff -Nur linux-3.14.72.orig/include/linux/isl29023.h linux-3.14.72/include/linux/isl29023.h
+--- linux-3.14.72.orig/include/linux/isl29023.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/isl29023.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __ISL29023_H__
++#define __ISL29023_H__
++
++#include <linux/types.h>
++
++#define ISL29023_PD_MODE 0x0
++#define ISL29023_ALS_ONCE_MODE 0x1
++#define ISL29023_IR_ONCE_MODE 0x2
++#define ISL29023_ALS_CONT_MODE 0x5
++#define ISL29023_IR_CONT_MODE 0x6
++
++#define ISL29023_INT_PERSISTS_1 0x0
++#define ISL29023_INT_PERSISTS_4 0x1
++#define ISL29023_INT_PERSISTS_8 0x2
++#define ISL29023_INT_PERSISTS_16 0x3
++
++#define ISL29023_RES_16 0x0
++#define ISL29023_RES_12 0x1
++#define ISL29023_RES_8 0x2
++#define ISL29023_RES_4 0x3
++
++#define ISL29023_RANGE_1K 0x0
++#define ISL29023_RANGE_4K 0x1
++#define ISL29023_RANGE_16K 0x2
++#define ISL29023_RANGE_64K 0x3
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/libata.h linux-3.14.72/include/linux/libata.h
+--- linux-3.14.72.orig/include/linux/libata.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/libata.h 2016-06-19 22:11:55.497127409 +0200
+@@ -860,7 +860,6 @@
+ struct completion park_req_pending;
+
+ pm_message_t pm_mesg;
+- int *pm_result;
+ enum ata_lpm_policy target_lpm_policy;
+
+ struct timer_list fastdrain_timer;
+@@ -1152,16 +1151,14 @@
+ #ifdef CONFIG_PM
+ extern int ata_host_suspend(struct ata_host *host, pm_message_t mesg);
+ extern void ata_host_resume(struct ata_host *host);
+-extern int ata_sas_port_async_suspend(struct ata_port *ap, int *async);
+-extern int ata_sas_port_async_resume(struct ata_port *ap, int *async);
++extern void ata_sas_port_suspend(struct ata_port *ap);
++extern void ata_sas_port_resume(struct ata_port *ap);
+ #else
+-static inline int ata_sas_port_async_suspend(struct ata_port *ap, int *async)
++static inline void ata_sas_port_suspend(struct ata_port *ap)
+ {
+- return 0;
+ }
+-static inline int ata_sas_port_async_resume(struct ata_port *ap, int *async)
++static inline void ata_sas_port_async_resume(struct ata_port *ap)
+ {
+- return 0;
+ }
+ #endif
+ extern int ata_ratelimit(void);
+diff -Nur linux-3.14.72.orig/include/linux/mcc_api.h linux-3.14.72/include/linux/mcc_api.h
+--- linux-3.14.72.orig/include/linux/mcc_api.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mcc_api.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,36 @@
++/*
++ * This file contains prototypes for MCC library API functions
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#ifndef __MCC_API__
++#define __MCC_API__
++
++int mcc_initialize(MCC_NODE);
++int mcc_destroy(MCC_NODE);
++int mcc_create_endpoint(MCC_ENDPOINT*, MCC_PORT);
++int mcc_destroy_endpoint(MCC_ENDPOINT*);
++int mcc_send(MCC_ENDPOINT*, MCC_ENDPOINT*, void*, MCC_MEM_SIZE, unsigned int);
++int mcc_recv(MCC_ENDPOINT*, MCC_ENDPOINT*, void*, MCC_MEM_SIZE, MCC_MEM_SIZE*, unsigned int);
++int mcc_msgs_available(MCC_ENDPOINT*, unsigned int*);
++int mcc_get_info(MCC_NODE, MCC_INFO_STRUCT*);
++
++#if MCC_SEND_RECV_NOCOPY_API_ENABLED
++int mcc_get_buffer(void**, MCC_MEM_SIZE*, unsigned int);
++int mcc_send_nocopy(MCC_ENDPOINT*, MCC_ENDPOINT*, void*, MCC_MEM_SIZE);
++int mcc_recv_nocopy(MCC_ENDPOINT*, MCC_ENDPOINT*, void**, MCC_MEM_SIZE*, unsigned int);
++int mcc_free_buffer(void*);
++#endif /* MCC_SEND_RECV_NOCOPY_API_ENABLED */
++
++#endif /* __MCC_API__ */
++
+diff -Nur linux-3.14.72.orig/include/linux/mcc_common.h linux-3.14.72/include/linux/mcc_common.h
+--- linux-3.14.72.orig/include/linux/mcc_common.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mcc_common.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,323 @@
++/*
++ * This is the MCC library header file
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#ifndef __MCC_COMMON__
++#define __MCC_COMMON__
++
++#define MCC_INIT_STRING "mccisrd"
++#define MCC_VERSION_STRING "002.000"
++#define null ((void*)0)
++
++/*!
++ * \brief MCC_BOOLEAN type.
++ *
++ * Boolean type definiton for the MCC library.
++ */
++typedef unsigned int MCC_BOOLEAN;
++
++/*!
++ * \brief MCC_MEM_SIZE type.
++ *
++ * Mem size type definiton for the MCC library.
++ */
++typedef unsigned int MCC_MEM_SIZE;
++
++/*!
++ * \brief MCC_CORE type.
++ *
++ * This unsigned integer value specifies the core number for the endpoint definition.
++ *
++ * \see MCC_NODE
++ * \see MCC_PORT
++ * \see MCC_ENDPOINT
++ */
++typedef unsigned int MCC_CORE;
++
++/*!
++ * \brief MCC_NODE type.
++ *
++ * This unsigned integer value specifies the node number for the endpoint definition.
++ *
++ * \see MCC_CORE
++ * \see MCC_PORT
++ * \see MCC_ENDPOINT
++ */
++typedef unsigned int MCC_NODE;
++
++/*!
++ * \brief MCC_PORT type.
++ *
++ * This unsigned integer value specifies the port number for the endpoint definition.
++ *
++ * \see MCC_CORE
++ * \see MCC_NODE
++ * \see MCC_ENDPOINT
++ */
++typedef unsigned int MCC_PORT;
++
++#if defined(__IAR_SYSTEMS_ICC__)
++__packed
++#endif
++/*!
++ * \brief Endpoint structure.
++ *
++ * Endpoints are receive buffer queues, implemented in shared RAM,
++ * and are addressed by a triplet containing core, node, and port.
++ *
++ * \see MCC_BOOKEEPING_STRUCT
++ * \see MCC_CORE
++ * \see MCC_NODE
++ * \see MCC_PORT
++ */
++struct mcc_endpoint {
++ /*! \brief Core number - identifies the core within the processor */
++ MCC_CORE core;
++
++ /*! \brief Node number - in Linux any user process participating in MCC is a unique node;
++ MQX has only one node */
++ MCC_NODE node;
++
++ /*! \brief Port number - both Linux and MQX can have an arbitrary number of ports per node */
++ MCC_PORT port;
++#if defined(__IAR_SYSTEMS_ICC__)
++};
++#else
++}__attribute__((packed));
++#endif
++typedef struct mcc_endpoint MCC_ENDPOINT;
++
++#if defined(__IAR_SYSTEMS_ICC__)
++__packed
++#endif
++/*!
++ * \brief Receive buffer structure.
++ *
++ * This is the receive buffer structure used for exchanging data.
++ *
++ * \see MCC_BOOKEEPING_STRUCT
++ */
++struct mcc_receive_buffer {
++ /*! \brief Pointer to the next receive buffer */
++ struct mcc_receive_buffer *next;
++
++ /*! \brief Source endpoint */
++ MCC_ENDPOINT source;
++
++ /*! \brief Length of data stored in this buffer */
++ MCC_MEM_SIZE data_len;
++
++ /*! \brief Space for data storage */
++ char data [MCC_ATTR_BUFFER_SIZE_IN_BYTES];
++#if defined(__IAR_SYSTEMS_ICC__)
++};
++#else
++}__attribute__((packed));
++#endif
++typedef struct mcc_receive_buffer MCC_RECEIVE_BUFFER;
++
++#if defined(__IAR_SYSTEMS_ICC__)
++__packed
++#endif
++/*!
++ * \brief List of buffers.
++ *
++ * Each endpoint keeps the list of received buffers.
++ * The list of free buffers is kept in bookkeeping data structure.
++ *
++ * \see MCC_RECEIVE_BUFFER
++ * \see MCC_BOOKEEPING_STRUCT
++ */
++struct mcc_receive_list {
++ /*! \brief Head of a buffers list */
++ MCC_RECEIVE_BUFFER * head;
++
++ /*! \brief Tail of a buffers list */
++ MCC_RECEIVE_BUFFER * tail;
++#if defined(__IAR_SYSTEMS_ICC__)
++};
++#else
++}__attribute__((packed));
++#endif
++typedef struct mcc_receive_list MCC_RECEIVE_LIST;
++
++#define BUFFER_QUEUED (0)
++#define BUFFER_FREED (1)
++typedef unsigned int MCC_SIGNAL_TYPE;
++#if defined(__IAR_SYSTEMS_ICC__)
++__packed
++#endif
++/*!
++ * \brief Signals and signal queues.
++ *
++ * This is one item of a signal queue.
++ *
++ * \see MCC_SIGNAL_TYPE
++ * \see MCC_ENDPOINT
++ * \see MCC_BOOKEEPING_STRUCT
++ */
++struct mcc_signal {
++ /*! \brief Signal type - BUFFER_QUEUED or BUFFER_FREED */
++ MCC_SIGNAL_TYPE type;
++
++ /*! \brief Destination endpoint */
++ MCC_ENDPOINT destination;
++#if defined(__IAR_SYSTEMS_ICC__)
++};
++#else
++}__attribute__((packed));
++#endif
++typedef struct mcc_signal MCC_SIGNAL;
++
++#if defined(__IAR_SYSTEMS_ICC__)
++__packed
++#endif
++/*!
++ * \brief Endpoint registration table.
++ *
++ * This is used for matching each endpoint structure with it's list of received buffers.
++ *
++ * \see MCC_ENDPOINT
++ * \see MCC_RECEIVE_LIST
++ * \see MCC_BOOKEEPING_STRUCT
++ */
++struct mcc_endpoint_map_item {
++ /*! \brief Endpoint tripplet */
++ MCC_ENDPOINT endpoint;
++
++ /*! \brief List of received buffers */
++ MCC_RECEIVE_LIST list;
++#if defined(__IAR_SYSTEMS_ICC__)
++};
++#else
++}__attribute__((packed));
++#endif
++typedef struct mcc_endpoint_map_item MCC_ENDPOINT_MAP_ITEM;
++
++#if defined(__IAR_SYSTEMS_ICC__)
++__packed
++#endif
++/*!
++ * \brief MCC info structure.
++ *
++ * This is used for additional information about the MCC implementation.
++ *
++ * \see MCC_BOOKEEPING_STRUCT
++ */
++struct mcc_info_struct {
++ /*! \brief <major>.<minor> - minor is changed whenever patched, major indicates compatibility */
++ char version_string[sizeof(MCC_VERSION_STRING)];
++#if defined(__IAR_SYSTEMS_ICC__)
++};
++#else
++}__attribute__((packed));
++#endif
++typedef struct mcc_info_struct MCC_INFO_STRUCT;
++
++#if defined(__IAR_SYSTEMS_ICC__)
++__packed
++#endif
++/*!
++ * \brief Share Memory data - Bookkeeping data and buffers.
++ *
++ * This is used for "bookkeeping data" such as endpoint and signal queue head
++ * and tail pointers and fixed size data buffers. The whole mcc_bookeeping_struct
++ * as well as each individual structure members has to be defined and stored in the
++ * memory as packed structure. This way, the same structure member offsets will be ensured
++ * on all cores/OSes/compilers. Compiler-specific pragmas for data packing have to be applied.
++ *
++ * \see MCC_RECEIVE_LIST
++ * \see MCC_SIGNAL
++ * \see MCC_ENDPOINT_MAP_ITEM
++ * \see MCC_RECEIVE_BUFFER
++ */
++struct mcc_bookeeping_struct {
++ /*! \brief String that indicates if this structure has been already initialized */
++ char init_string[sizeof(MCC_INIT_STRING)];
++
++ /*! \brief String that indicates the MCC library version */
++ char version_string[sizeof(MCC_VERSION_STRING)];
++
++ /*! \brief List of free buffers */
++ MCC_RECEIVE_LIST free_list;
++
++ /*! \brief Each core has it's own queue of received signals */
++ MCC_SIGNAL signals_received[MCC_NUM_CORES][MCC_MAX_OUTSTANDING_SIGNALS];
++
++ /*! \brief Signal queue head for each core */
++ unsigned int signal_queue_head[MCC_NUM_CORES];
++
++ /*! \brief Signal queue tail for each core */
++ unsigned int signal_queue_tail[MCC_NUM_CORES];
++
++ /*! \brief Endpoint map */
++ MCC_ENDPOINT_MAP_ITEM endpoint_table[MCC_ATTR_MAX_RECEIVE_ENDPOINTS];
++
++ /*! \brief Receive buffers, the number is defined in mcc_config.h (MCC_ATTR_NUM_RECEIVE_BUFFERS) */
++ MCC_RECEIVE_BUFFER r_buffers[MCC_ATTR_NUM_RECEIVE_BUFFERS];
++#if defined(__IAR_SYSTEMS_ICC__)
++};
++#else
++}__attribute__((packed));
++#endif
++typedef struct mcc_bookeeping_struct MCC_BOOKEEPING_STRUCT;
++
++extern MCC_BOOKEEPING_STRUCT * bookeeping_data;
++
++/*
++ * Common Macros
++ */
++#define MCC_RESERVED_PORT_NUMBER (0)
++#define MCC_MAX_RECEIVE_ENDPOINTS_COUNT (255)
++
++/*
++ * Errors
++ */
++#define MCC_SUCCESS (0) /* function returned successfully */
++#define MCC_ERR_TIMEOUT (1) /* blocking function timed out before completing */
++#define MCC_ERR_INVAL (2) /* invalid input parameter */
++#define MCC_ERR_NOMEM (3) /* out of shared memory for message transmission */
++#define MCC_ERR_ENDPOINT (4) /* invalid endpoint / endpoint doesn't exist */
++#define MCC_ERR_SEMAPHORE (5) /* semaphore handling error */
++#define MCC_ERR_DEV (6) /* Device Open Error */
++#define MCC_ERR_INT (7) /* Interrupt Error */
++#define MCC_ERR_SQ_FULL (8) /* Signal queue is full */
++#define MCC_ERR_SQ_EMPTY (9) /* Signal queue is empty */
++#define MCC_ERR_VERSION (10) /* Incorrect MCC version used - compatibility issue */
++#define MCC_ERR_OSSYNC (11) /* OS-dependent synchronization module issue */
++
++/*
++ * OS Selection
++ */
++#define MCC_LINUX (1) /* Linux OS used */
++#define MCC_MQX (2) /* MQX RTOS used */
++
++MCC_RECEIVE_LIST * mcc_get_endpoint_list(MCC_ENDPOINT endpoint);
++MCC_RECEIVE_BUFFER * mcc_dequeue_buffer(MCC_RECEIVE_LIST *list);
++void mcc_queue_buffer(MCC_RECEIVE_LIST *list, MCC_RECEIVE_BUFFER * r_buffer);
++int mcc_remove_endpoint(MCC_ENDPOINT endpoint);
++int mcc_register_endpoint(MCC_ENDPOINT endpoint);
++int mcc_queue_signal(MCC_CORE core, MCC_SIGNAL signal);
++int mcc_dequeue_signal(MCC_CORE core, MCC_SIGNAL *signal);
++
++#define MCC_SIGNAL_QUEUE_FULL(core) (((bookeeping_data->signal_queue_tail[core] + 1) % MCC_MAX_OUTSTANDING_SIGNALS) == bookeeping_data->signal_queue_head[core])
++#define MCC_SIGNAL_QUEUE_EMPTY(core) (bookeeping_data->signal_queue_head[core] == bookeeping_data->signal_queue_tail[core])
++#define MCC_ENDPOINTS_EQUAL(e1, e2) ((e1.core == e2.core) && (e1.node == e2.node) && (e1.port == e2.port))
++
++#if (MCC_ATTR_MAX_RECEIVE_ENDPOINTS > MCC_MAX_RECEIVE_ENDPOINTS_COUNT)
++#error User-defined maximum number of endpoints can not exceed the value of MCC_MAX_RECEIVE_ENDPOINTS_COUNT
++#endif
++
++#endif /* __MCC_COMMON__ */
++
+diff -Nur linux-3.14.72.orig/include/linux/mcc_config_linux.h linux-3.14.72/include/linux/mcc_config_linux.h
+--- linux-3.14.72.orig/include/linux/mcc_config_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mcc_config_linux.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,54 @@
++/*
++ * This is the Linux MCC configuration file
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#ifndef __MCC_LINUX_CONFIG_
++#define __MCC_CLINUX_CONFIG_
++
++/* base address of shared memory */
++#define MCC_BASE_ADDRESS (0xBFF00000)
++
++/* size (in bytes) and number of receive buffers */
++#define MCC_ATTR_NUM_RECEIVE_BUFFERS (10)
++#define MCC_ATTR_BUFFER_SIZE_IN_BYTES (1024)
++
++/* maximum number of receive endpoints (application specific setting),
++ * do not assign it to a value greater than 255 ! */
++#define MCC_ATTR_MAX_RECEIVE_ENDPOINTS (5)
++
++/* size of the signal queue */
++#define MCC_MAX_OUTSTANDING_SIGNALS (10)
++
++/* number of cores */
++#define MCC_NUM_CORES (2)
++
++/* core number */
++#define MCC_CORE_NUMBER (_psp_core_num())
++
++/* node number */
++#define MCC_NODE_NUMBER (_psp_node_num())
++
++/* semaphore number */
++#define MCC_SHMEM_SEMAPHORE_NUMBER (1)
++#define MCC_PRINTF_SEMAPHORE_NUMBER (2)
++#define MCC_I2C_SEMAPHORE_NUMBER (3)
++#define MCC_RESERVED1_SEMAPHORE_NUMBER (4)
++#define MCC_RESERVED2_SEMAPHORE_NUMBER (5)
++#define MCC_POWER_SHMEM_NUMBER (6)
++
++/* data non-copy mechanisms enabled */
++#define MCC_SEND_RECV_NOCOPY_API_ENABLED (1)
++
++#endif /* __MCC_LINUX_CONFIG_*/
++
+diff -Nur linux-3.14.72.orig/include/linux/mcc_imx6sx.h linux-3.14.72/include/linux/mcc_imx6sx.h
+--- linux-3.14.72.orig/include/linux/mcc_imx6sx.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mcc_imx6sx.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,33 @@
++/*
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++/*
++ * Define the phiscal memory address on A9 and shared M4,
++ * This definition should be aligned on both A9 and M4
++ */
++#define MCC_VECTOR_NUMBER_INVALID (0)
++
++enum {
++ INT_CPU_TO_CPU_MU_A2M = 122,
++ INT_CPU_TO_CPU_MU_M2A = 90,
++};
++
++/* Return core num. A9 0, M4 1 */
++unsigned int _psp_core_num(void);
++unsigned int _psp_node_num(void);
++
++unsigned int mcc_get_cpu_to_cpu_vector(unsigned int);
++/* Defined in MU driver */
++void mcc_clear_cpu_to_cpu_interrupt(void);
++int mcc_triger_cpu_to_cpu_interrupt(void);
++int imx_mcc_bsp_int_disable(void);
++int imx_mcc_bsp_int_enable(void);
+diff -Nur linux-3.14.72.orig/include/linux/mcc_linux.h linux-3.14.72/include/linux/mcc_linux.h
+--- linux-3.14.72.orig/include/linux/mcc_linux.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mcc_linux.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,59 @@
++/*
++ * This file contains prototypes for Linux-specific MCC library functions
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ *
++ * SPDX-License-Identifier: GPL-2.0+ and/or BSD-3-Clause
++ * The GPL-2.0+ license for this file can be found in the COPYING.GPL file
++ * included with this distribution or at
++ * http://www.gnu.org/licenses/gpl-2.0.html
++ * The BSD-3-Clause License for this file can be found in the COPYING.BSD file
++ * included with this distribution or at
++ * http://opensource.org/licenses/BSD-3-Clause
++ */
++
++#ifndef __MCC_LINUX__
++#define __MCC_LINUX__
++
++#include <linux/sched.h>
++#include <linux/string.h>
++
++/* Define the kinds of cache macros */
++#define MCC_DCACHE_ENABLE(n)
++#define MCC_DCACHE_DISABLE()
++#define MCC_DCACHE_FLUSH()
++#define MCC_DCACHE_FLUSH_LINE(p)
++#define MCC_DCACHE_FLUSH_MLINES(p, m)
++#define MCC_DCACHE_INVALIDATE()
++#define MCC_DCACHE_INVALIDATE_LINE(p)
++#define MCC_DCACHE_INVALIDATE_MLINES(p, m)
++
++#define MCC_LINUX_NODE_NUMBER (0)
++
++void * mcc_virt_to_phys(void *);
++void * mcc_phys_to_virt(void *);
++#define MCC_MEM_VIRT_TO_PHYS(x) mcc_virt_to_phys(x)
++#define MCC_MEM_PHYS_TO_VIRT(x) mcc_phys_to_virt(x)
++
++/* Semaphore-related functions */
++int mcc_init_semaphore(unsigned int);
++int mcc_deinit_semaphore(unsigned int);
++int mcc_get_semaphore(void);
++int mcc_release_semaphore(void);
++
++/* CPU-to-CPU interrupt-related functions */
++int mcc_register_cpu_to_cpu_isr(void);
++int mcc_generate_cpu_to_cpu_interrupt(void);
++
++/* Memory management-related functions */
++void mcc_memcpy(void *, void *, unsigned int);
++
++int mcc_init_os_sync(void);
++int mcc_deinit_os_sync(void);
++void mcc_clear_os_sync_for_ep(MCC_ENDPOINT *);
++int mcc_wait_for_buffer_freed(MCC_RECEIVE_BUFFER **, unsigned int);
++int mcc_wait_for_buffer_queued(MCC_ENDPOINT *, unsigned int);
++
++MCC_BOOKEEPING_STRUCT *mcc_get_bookeeping_data(void);
++#endif /* __MCC_LINUX__ */
+diff -Nur linux-3.14.72.orig/include/linux/memblock.h linux-3.14.72/include/linux/memblock.h
+--- linux-3.14.72.orig/include/linux/memblock.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/memblock.h 2016-06-19 22:11:55.497127409 +0200
+@@ -221,6 +221,8 @@
+ #define MEMBLOCK_ALLOC_ANYWHERE (~(phys_addr_t)0)
+ #define MEMBLOCK_ALLOC_ACCESSIBLE 0
+
++phys_addr_t __init memblock_alloc_range(phys_addr_t size, phys_addr_t align,
++ phys_addr_t start, phys_addr_t end);
+ phys_addr_t memblock_alloc_base(phys_addr_t size, phys_addr_t align,
+ phys_addr_t max_addr);
+ phys_addr_t __memblock_alloc_base(phys_addr_t size, phys_addr_t align,
+diff -Nur linux-3.14.72.orig/include/linux/mfd/max17135.h linux-3.14.72/include/linux/mfd/max17135.h
+--- linux-3.14.72.orig/include/linux/mfd/max17135.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mfd/max17135.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,220 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef __LINUX_REGULATOR_MAX17135_H_
++#define __LINUX_REGULATOR_MAX17135_H_
++
++/*
++ * PMIC Register Addresses
++ */
++enum {
++ REG_MAX17135_EXT_TEMP = 0x0,
++ REG_MAX17135_CONFIG,
++ REG_MAX17135_INT_TEMP = 0x4,
++ REG_MAX17135_STATUS,
++ REG_MAX17135_PRODUCT_REV,
++ REG_MAX17135_PRODUCT_ID,
++ REG_MAX17135_DVR,
++ REG_MAX17135_ENABLE,
++ REG_MAX17135_FAULT, /*0x0A*/
++ REG_MAX17135_HVINP,
++ REG_MAX17135_PRGM_CTRL,
++ REG_MAX17135_TIMING1 = 0x10, /* Timing regs base address is 0x10 */
++ REG_MAX17135_TIMING2,
++ REG_MAX17135_TIMING3,
++ REG_MAX17135_TIMING4,
++ REG_MAX17135_TIMING5,
++ REG_MAX17135_TIMING6,
++ REG_MAX17135_TIMING7,
++ REG_MAX17135_TIMING8,
++};
++#define MAX17135_REG_NUM 21
++#define MAX17135_MAX_REGISTER 0xFF
++
++/*
++ * Bitfield macros that use rely on bitfield width/shift information.
++ */
++#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
++#define BITFVAL(field, val) ((val) << (field ## _LSH))
++#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
++
++/*
++ * Shift and width values for each register bitfield
++ */
++#define EXT_TEMP_LSH 7
++#define EXT_TEMP_WID 9
++
++#define THERMAL_SHUTDOWN_LSH 0
++#define THERMAL_SHUTDOWN_WID 1
++
++#define INT_TEMP_LSH 7
++#define INT_TEMP_WID 9
++
++#define STAT_BUSY_LSH 0
++#define STAT_BUSY_WID 1
++#define STAT_OPEN_LSH 1
++#define STAT_OPEN_WID 1
++#define STAT_SHRT_LSH 2
++#define STAT_SHRT_WID 1
++
++#define PROD_REV_LSH 0
++#define PROD_REV_WID 8
++
++#define PROD_ID_LSH 0
++#define PROD_ID_WID 8
++
++#define DVR_LSH 0
++#define DVR_WID 8
++
++#define ENABLE_LSH 0
++#define ENABLE_WID 1
++#define VCOM_ENABLE_LSH 1
++#define VCOM_ENABLE_WID 1
++
++#define FAULT_FBPG_LSH 0
++#define FAULT_FBPG_WID 1
++#define FAULT_HVINP_LSH 1
++#define FAULT_HVINP_WID 1
++#define FAULT_HVINN_LSH 2
++#define FAULT_HVINN_WID 1
++#define FAULT_FBNG_LSH 3
++#define FAULT_FBNG_WID 1
++#define FAULT_HVINPSC_LSH 4
++#define FAULT_HVINPSC_WID 1
++#define FAULT_HVINNSC_LSH 5
++#define FAULT_HVINNSC_WID 1
++#define FAULT_OT_LSH 6
++#define FAULT_OT_WID 1
++#define FAULT_POK_LSH 7
++#define FAULT_POK_WID 1
++
++#define HVINP_LSH 0
++#define HVINP_WID 4
++
++#define CTRL_DVR_LSH 0
++#define CTRL_DVR_WID 1
++#define CTRL_TIMING_LSH 1
++#define CTRL_TIMING_WID 1
++
++#define TIMING1_LSH 0
++#define TIMING1_WID 8
++#define TIMING2_LSH 0
++#define TIMING2_WID 8
++#define TIMING3_LSH 0
++#define TIMING3_WID 8
++#define TIMING4_LSH 0
++#define TIMING4_WID 8
++#define TIMING5_LSH 0
++#define TIMING5_WID 8
++#define TIMING6_LSH 0
++#define TIMING6_WID 8
++#define TIMING7_LSH 0
++#define TIMING7_WID 8
++#define TIMING8_LSH 0
++#define TIMING8_WID 8
++
++struct max17135 {
++ /* chip revision */
++ int rev;
++
++ struct device *dev;
++ struct max17135_platform_data *pdata;
++
++ /* Platform connection */
++ struct i2c_client *i2c_client;
++
++ /* Timings */
++ unsigned int gvee_pwrup;
++ unsigned int vneg_pwrup;
++ unsigned int vpos_pwrup;
++ unsigned int gvdd_pwrup;
++ unsigned int gvdd_pwrdn;
++ unsigned int vpos_pwrdn;
++ unsigned int vneg_pwrdn;
++ unsigned int gvee_pwrdn;
++
++ /* GPIOs */
++ int gpio_pmic_pwrgood;
++ int gpio_pmic_vcom_ctrl;
++ int gpio_pmic_wakeup;
++ int gpio_pmic_v3p3;
++ int gpio_pmic_intr;
++
++ /* MAX17135 part variables */
++ int pass_num;
++ int vcom_uV;
++
++ /* One-time VCOM setup marker */
++ bool vcom_setup;
++
++ /* powerup/powerdown wait time */
++ int max_wait;
++};
++
++enum {
++ /* In alphabetical order */
++ MAX17135_DISPLAY, /* virtual master enable */
++ MAX17135_GVDD,
++ MAX17135_GVEE,
++ MAX17135_HVINN,
++ MAX17135_HVINP,
++ MAX17135_VCOM,
++ MAX17135_VNEG,
++ MAX17135_VPOS,
++ MAX17135_V3P3,
++ MAX17135_NUM_REGULATORS,
++};
++
++/*
++ * Declarations
++ */
++struct regulator_init_data;
++struct max17135_regulator_data;
++
++struct max17135_platform_data {
++ unsigned int gvee_pwrup;
++ unsigned int vneg_pwrup;
++ unsigned int vpos_pwrup;
++ unsigned int gvdd_pwrup;
++ unsigned int gvdd_pwrdn;
++ unsigned int vpos_pwrdn;
++ unsigned int vneg_pwrdn;
++ unsigned int gvee_pwrdn;
++ int gpio_pmic_pwrgood;
++ int gpio_pmic_vcom_ctrl;
++ int gpio_pmic_wakeup;
++ int gpio_pmic_v3p3;
++ int gpio_pmic_intr;
++ int pass_num;
++ int vcom_uV;
++
++ /* PMIC */
++ struct max17135_regulator_data *regulators;
++ int num_regulators;
++};
++
++struct max17135_regulator_data {
++ int id;
++ struct regulator_init_data *initdata;
++ struct device_node *reg_node;
++};
++
++int max17135_reg_read(int reg_num, unsigned int *reg_val);
++int max17135_reg_write(int reg_num, const unsigned int reg_val);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mfd/mxc-hdmi-core.h linux-3.14.72/include/linux/mfd/mxc-hdmi-core.h
+--- linux-3.14.72.orig/include/linux/mfd/mxc-hdmi-core.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mfd/mxc-hdmi-core.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef __LINUX_MXC_HDMI_CORE_H_
++#define __LINUX_MXC_HDMI_CORE_H_
++
++#include <video/mxc_edid.h>
++
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#define IRQ_DISABLE_SUCCEED 0
++#define IRQ_DISABLE_FAIL 1
++
++bool hdmi_check_overflow(void);
++
++u8 hdmi_readb(unsigned int reg);
++void hdmi_writeb(u8 value, unsigned int reg);
++void hdmi_mask_writeb(u8 data, unsigned int addr, u8 shift, u8 mask);
++unsigned int hdmi_read4(unsigned int reg);
++void hdmi_write4(unsigned int value, unsigned int reg);
++
++void hdmi_irq_init(void);
++void hdmi_irq_enable(int irq);
++unsigned int hdmi_irq_disable(int irq);
++
++void hdmi_set_sample_rate(unsigned int rate);
++void hdmi_set_dma_mode(unsigned int dma_running);
++void hdmi_init_clk_regenerator(void);
++void hdmi_clk_regenerator_update_pixel_clock(u32 pixclock, u32 vmode);
++
++void hdmi_set_edid_cfg(int edid_status, struct mxc_edid_cfg *cfg);
++int hdmi_get_edid_cfg(struct mxc_edid_cfg *cfg);
++
++extern int mxc_hdmi_ipu_id;
++extern int mxc_hdmi_disp_id;
++
++void hdmi_set_registered(int registered);
++int hdmi_get_registered(void);
++int mxc_hdmi_abort_stream(void);
++int mxc_hdmi_register_audio(struct snd_pcm_substream *substream);
++void mxc_hdmi_unregister_audio(struct snd_pcm_substream *substream);
++void hdmi_set_dvi_mode(unsigned int state);
++unsigned int hdmi_set_cable_state(unsigned int state);
++unsigned int hdmi_set_blank_state(unsigned int state);
++int check_hdmi_state(void);
++
++void hdmi_cec_start_device(void);
++void hdmi_cec_stop_device(void);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h linux-3.14.72/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+--- linux-3.14.72.orig/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h 2016-06-19 22:11:55.497127409 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -123,6 +123,9 @@
+ #define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
+ #define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
+ #define IMX6Q_GPR1_GINT BIT(12)
++#define IMX6Q_GPR1_GINT_MASK BIT(12)
++#define IMX6Q_GPR1_GINT_CLEAR 0x0
++#define IMX6Q_GPR1_GINT_ASSERT BIT(12)
+ #define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
+ #define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
+ #define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
+@@ -242,6 +245,24 @@
+
+ #define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
+
++#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0)
++#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4)
++#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK (0xf << 8)
++#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK (0xf << 12)
++#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK (0xf << 16)
++#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK (0xf << 20)
++#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24)
++#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK (0xf << 28)
++
++#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK (0xf << 0)
++#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK (0xf << 4)
++#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK (0xf << 8)
++#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK (0xf << 12)
++#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK (0xf << 16)
++#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK (0xf << 20)
++#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24)
++#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28)
++
+ #define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
+ #define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
+ #define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
+@@ -266,15 +287,15 @@
+ #define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5)
+ #define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
+ #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
+-#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x0 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS0 (0x1 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_LVDS1 (0x2 << 2)
++#define IMX6Q_GPR10_DCIC2_MUX_CTL_MIPI (0x3 << 2)
+ #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0)
+ #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0)
+-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0)
+-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
+-#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0)
++#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS0 (0x1 << 0)
++#define IMX6Q_GPR10_DCIC1_MUX_CTL_LVDS1 (0x2 << 0)
++#define IMX6Q_GPR10_DCIC1_MUX_CTL_HDMI (0x3 << 0)
+
+ #define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
+ #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
+@@ -283,6 +304,7 @@
+ #define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12)
+ #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
+ #define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4)
++#define IMX6Q_GPR12_LOS_LEVEL_9 (0x9 << 4)
+
+ #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
+ #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
+@@ -373,8 +395,73 @@
+ #define IMX6Q_GPR13_SATA_MPLL_CLK_EN BIT(1)
+ #define IMX6Q_GPR13_SATA_TX_EDGE_RATE BIT(0)
+
++/* For imx6dl iomux gpr register field definitions */
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8)
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8)
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8)
++#define IMX6DL_GPR3_LVDS1_MUX_CTL_LCDIF (0x2 << 8)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
++#define IMX6DL_GPR3_LVDS0_MUX_CTL_LCDIF (0x2 << 6)
++
+ /* For imx6sl iomux gpr register field define */
+ #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+ #define IMX6SL_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+
++/* For imx6sx iomux gpr register field define */
++#define IMX6SX_GPR1_VDEC_SW_RST_MASK (0x1 << 20)
++#define IMX6SX_GPR1_VDEC_SW_RST_RESET (0x1 << 20)
++#define IMX6SX_GPR1_VDEC_SW_RST_RELEASE (0x0 << 20)
++#define IMX6SX_GPR1_VADC_SW_RST_MASK (0x1 << 19)
++#define IMX6SX_GPR1_VADC_SW_RST_RESET (0x1 << 19)
++#define IMX6SX_GPR1_VADC_SW_RST_RELEASE (0x0 << 19)
++#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK (0x3 << 13)
++#define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17)
++#define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13)
++
++#define IMX6SX_GPR2_MQS_OVERSAMPLE_MASK (0x1 << 26)
++#define IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT (26)
++#define IMX6SX_GPR2_MQS_EN_MASK (0x1 << 25)
++#define IMX6SX_GPR2_MQS_EN_SHIFT (25)
++#define IMX6SX_GPR2_MQS_SW_RST_MASK (0x1 << 24)
++#define IMX6SX_GPR2_MQS_SW_RST_SHIFT (24)
++#define IMX6SX_GPR2_MQS_CLK_DIV_MASK (0xFF << 16)
++#define IMX6SX_GPR2_MQS_CLK_DIV_SHIFT (16)
++
++#define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3)
++#define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4)
++
++#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3)
++#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3)
++#define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3)
++
++#define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK (0x3 << 27)
++#define IMX6SX_GPR5_CSI2_MUX_CTRL_EXT_PIN (0x0 << 27)
++#define IMX6SX_GPR5_CSI2_MUX_CTRL_CVD (0x1 << 27)
++#define IMX6SX_GPR5_CSI2_MUX_CTRL_VDAC_TO_CSI (0x2 << 27)
++#define IMX6SX_GPR5_CSI2_MUX_CTRL_GND (0x3 << 27)
++#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_MASK (0x1 << 26)
++#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_ENABLE (0x1 << 26)
++#define IMX6SX_GPR5_VADC_TO_CSI_CAPTURE_EN_DISABLE (0x0 << 26)
++#define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK (0x3 << 4)
++#define IMX6SX_GPR5_CSI1_MUX_CTRL_EXT_PIN (0x0 << 4)
++#define IMX6SX_GPR5_CSI1_MUX_CTRL_CVD (0x1 << 4)
++#define IMX6SX_GPR5_CSI1_MUX_CTRL_VDAC_TO_CSI (0x2 << 4)
++#define IMX6SX_GPR5_CSI1_MUX_CTRL_GND (0x3 << 4)
++
++#define IMX6SX_GPR5_DISP_MUX_DCIC2_LCDIF2 (0x0 << 2)
++#define IMX6SX_GPR5_DISP_MUX_DCIC2_LVDS (0x1 << 2)
++#define IMX6SX_GPR5_DISP_MUX_DCIC2_MASK (0x1 << 2)
++#define IMX6SX_GPR5_DISP_MUX_DCIC1_LCDIF1 (0x0 << 1)
++#define IMX6SX_GPR5_DISP_MUX_DCIC1_LVDS (0x1 << 1)
++#define IMX6SX_GPR5_DISP_MUX_DCIC1_MASK (0x1 << 1)
++
++#define IMX6SX_GPR5_PCIE_BTNRST BIT(19)
++#define IMX6SX_GPR5_PCIE_PERST BIT(18)
++
++#define IMX6SX_GPR12_PCIE_PM_TURN_OFF BIT(16)
++#define IMX6SX_GPR12_PCIE_TEST_PD BIT(30)
++#define IMX6SX_GPR12_RX_EQ_MASK (0x7 << 0)
++#define IMX6SX_GPR12_RX_EQ_2 (0x2 << 0)
+ #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
+diff -Nur linux-3.14.72.orig/include/linux/mfd/tda1997x-core.h linux-3.14.72/include/linux/mfd/tda1997x-core.h
+--- linux-3.14.72.orig/include/linux/mfd/tda1997x-core.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mfd/tda1997x-core.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,225 @@
++/*
++ * tda1997x.h - header for TDA1997X HDMI receiver device
++ *
++ * Copyright (C) 2013 Gateworks Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#ifndef __TDA1997X_H_
++#define __TDA1997X_H_
++
++#include <linux/types.h>
++
++/*
++ * Video Port Configuration:
++ *
++ * 9 byte registers describe the video port output bit mapping (which bits from
++ * the video data stream output on which pins). Each register controls a
++ * 'pin group' of 4 bits (nibble) of the internal 36bit video data bus
++ * with the following bit descriptions:
++ *
++ * 7 - vp_out - video port output enable: 1-active
++ * 6 - vp_hiz - video port output level when not used: 1-HI-Z, 0-Low
++ * 5 - unused
++ * 4 - vp_swap - Swap bit allocation: 1-swap
++ * 3:0 - vp_sel - Select nibble to be routed to this pin-group
++ * 00: D[03:00]
++ * 01: D[07:04]
++ * 02: D[03:08]
++ * 03: D[07:12]
++ * 04: D[11:16]
++ * 05: D[15:20]
++ * 06: D[19:24]
++ * 07: D[23:28]
++ * 08: D[27:32]
++ * 0a: D[31:35]
++ *
++ * The pingroups differ per chip and are as follows:
++ *
++ * Byte Register TDA19971(24bit) TDA19972(36bit)
++ * 1 VP35_32_CTRL VP[24:20] Group8 VP[35:32] Group8
++ * 2 VP31_28_CTRL VP[19:16] Group7 VP[31:28] Group7
++ * 3 VP27_24_CTRL N/A VP[27:24] Group6
++ * 4 VP23_20_CTRL VP[15:12] Group5 VP[23:20] Group5
++ * 5 VP19_16_CTRL VP[11:08] Group4 VP[19:16] Group4
++ * 6 VP15_12_CTRL N/A VP[15:12] Group3
++ * 7 VP11_08_CTRL VP[07:04] Group2 VP[11:08] Group2
++ * 8 VP07_04_CTRL VP[03:00] Group1 VP[07:04] Group1
++ * 9 VP03_00_CTRL N/A VP[03:00] Group0
++ *
++ * Note that the internal 36bit video bus is aligned to the top of the bus,
++ * for example 8bit CCIR656 will be output on D[24:16] internally.
++ *
++ * If you have a TDA19971 (24bit output) pins VP[0:8] connected to
++ * an Soc with an 8bit video port (ie for 8bit CCIR656 data) you would
++ * assign the 9 registers as follows to map D[24:16] to VP[0:8].
++ *
++ * video_out_port = {
++ * 0x00, // VP35_32_CTRL
++ * 0x00, // VP31_28_CTRL
++ * 0x00, // VP27_24_CTRL
++ * 0x82, // VP23_18_CTRL: vp_out=1 vp_hiz=0 vp_swap=0 vp_sel=2 (Group2)
++ * 0x81, // VP19_16_CTRL: vp_out=1 vp_hiz=0 vp_swap=0 vp_sel=1 (Group8)
++ * 0x00, // VP15_12_CTRL
++ * 0x00, // VP11_08_CTRL
++ * 0x00, // VP07_04_CTRL
++ * 0x00, // VP03_00_CTRL
++ * };
++ */
++
++/* Video output clock modes */
++typedef enum {
++ CLOCK_SINGLE_EDGE,
++ CLOCK_DUAL_EDGE,
++ CLOCK_SINGLE_EDGE_TOGGLED,
++ CLOCK_DUAL_EDGE_TOGGLED,
++} tda1997x_videoclkmode_t;
++
++/* Video output data formats */
++typedef enum {
++ VIDEOFMT_444 = 0x00, /* RGB444/YUV444 */
++ VIDEOFMT_422_SMP = 0x01, /* YUV422 semi-planar */
++ VIDEOFMT_422_CCIR = 0x02 /* YUV422 CCIR656 */
++} tda1997x_videofmt_t;
++
++/* HS/HREF signal source */
++typedef enum
++{
++ SYNCOUTPUT_HSYNC_VHREF = 0x00, /* HS from VHREF - do not use (not programmed) */
++ SYNCOUTPUT_HREF_VHREF = 0x01, /* HREF from VHREF */
++ SYNCOUTPUT_HREF_HDMI = 0x02, /* HREF from HDMI */
++} tda1997x_sync_output_hs_t;
++
++/* VS/VREF signal source */
++typedef enum
++{
++ SYNCOUTPUT_VSYNC_VHREF = 0x00, /* VS from VHREF - do not use (not programmed) */
++ SYNCOUTPUT_VREF_VHREF = 0x01, /* VREF from VHREF */
++ SYNCOUTPUT_VREF_HDMI = 0x02, /* VREF from HDMI */
++} tda1997x_sync_output_vs_t;
++
++/* DE/FREF signal source */
++typedef enum
++{
++ SYNCOUTPUT_DE_VHREF = 0x00, /* DE from VHREF (HREF and not VREF) */
++ SYNCOUTPUT_FREF_VHREF = 0x01, /* FREF from VHREF */
++ SYNCOUTPUT_FREF_HDMI = 0x02, /* FREF from HDMI */
++} tda1997x_sync_output_de_t;
++
++/* video details */
++typedef struct {
++ /* video input data (input to the HDMI receiver) */
++ int width;
++ int height;
++ int fps;
++ bool interlaced;
++ bool signal;
++
++ /* video output data (output from the HDMI receiver) */
++ tda1997x_videofmt_t sensor_vidfmt;
++ tda1997x_videoclkmode_t sensor_clkmode;
++} tda1997x_vidout_fmt_t;
++
++/** Obtain current video format details from core */
++int tda1997x_get_vidout_fmt(tda1997x_vidout_fmt_t *);
++
++/*
++ * Audio samples can be output in either S/PDIF or I2S bus formats.
++ * In I2S mode, the TDF1997X is the master with 16bit or 32bit per word.
++ * In either modes, up to 8 audio channels can be controlled using the audio
++ * port pins AP0 to AP3 and A_WS. The audio port mapping depends on the
++ * channel allocation, layout, and audio input type.
++ *
++ * The following table shows the audio port pin usage for the various modes
++ * possible (pins missing should be unconnected)
++ *
++ * | SPDIF | SPDIF | I2S | I2S | HBR demux
++ * | Layout0 | Layout1 | Layout0 | Layout1 | SPDIF | I2S
++ * ------+---------+---------+---------+---------+------------+------------
++ * A_WS | WS | WS | WS | WS | WS | WS
++ * AP3 | | SPDIF3 | | SD3 | SPDIF[x+3] | SD[x+3]
++ * AP2 | | SPDIF2 | | SD2 | SPDIF[x+2] | SD[x+2]
++ * AP1 | | SPDIF1 | | SD1 | SPDIF[x+1] | SD[x+1]
++ * AP0 | | SPDIF0 | | SD0 | SPDIF[x] | SD[x]
++ * A_CLK | (32*Fs) | (32*Fs) |(32*Fs) | (32*Fs) | (32*FsACR) | (32*FsACR)
++ * | (64*Fs) | (64*Fs) |(64*Fs) | (64*Fs) | (64*FsACR) | (64*FsACR)
++ *
++ * Freq(Sysclk) = 2*freq(Aclk)
++ */
++typedef enum {
++ AUDIO_LAYOUT_FORCED_0 = 0x00, /* Layout dictated by packet header? */
++ AUDIO_LAYOUT_FORCED_1 = 0x01, /* layout1? */
++ AUDIO_LAYOUT_FORCED = 0x02, /* layout0? */
++} tda1997x_audiolayout_t;
++
++/* Audio output data formats */
++typedef enum {
++ AUDIO_FMT_I2S16, /* I2S 16 bit */
++ AUDIO_FMT_I2S32, /* I2S 32 bit */
++ AUDIO_FMT_SPDIF, /* SPDIF */
++ AUDIO_FMT_OBA, /* One Bit Audio */
++ AUDIO_FMT_I2S16_HBR_STRAIGHT, /* HBR straight in I2S 16bit mode */
++ AUDIO_FMT_I2S16_HBR_DEMUX, /* HBR demux in I2S 16bit mode */
++ AUDIO_FMT_I2S32_HBR_DEMUX, /* HBR demux in I2S 32bit mode */
++ AUDIO_FMT_SPDIF_HBR_DEMUX, /* HBR demux in SPDIF mode */
++ AUDIO_FMT_DST, /* Direct Stream Transfer */
++} tda1997x_audiofmt_t;
++
++/* Audio output clock frequencies */
++typedef enum
++{
++ AUDIO_SYSCLK_128FS = 0x03,
++ AUDIO_SYSCLK_256FS = 0x04,
++ AUDIO_SYSCLK_512FS = 0x05,
++} tda1997x_audiosysclk_t;
++
++/* Audio output info */
++typedef struct {
++ int samplerate;
++ int channels;
++ int samplesize;
++} tda1997x_audout_fmt_t;
++
++/** Obtain current audio format details from core */
++int tda1997x_get_audout_fmt(tda1997x_audout_fmt_t *);
++
++/* possible states of the state machine */
++typedef enum
++{
++ STATE_NOT_INITIALIZED, /* Driver is not initialized */
++ STATE_INITIALIZED, /* Driver is initialized */
++ STATE_UNLOCKED, /* Driver is not locked on input signal */
++ STATE_LOCKED, /* Driver is locked on input signal */
++ STATE_CONFIGURED /* Driver is configured */
++} tda1997x_state_t;
++
++extern tda1997x_state_t tda1997x_get_state(void);
++
++/* HDMI Inputs:
++ * TDA19971: HDMI-A (single input)
++ * TDA19972: HDMI-A|B (dual input)
++ */
++typedef enum
++{
++ INPUT_HDMI_A,
++ INPUT_HDMI_B, /* TDA19972 only */
++ INPUT_AUTO_DIGITAL, /* TDA19972 only */
++} tda1997x_input_t;
++
++extern int tda1997x_select_input(tda1997x_input_t);
++
++#endif /* End of __TDA1997X_H */
+diff -Nur linux-3.14.72.orig/include/linux/mipi_csi2.h linux-3.14.72/include/linux/mipi_csi2.h
+--- linux-3.14.72.orig/include/linux/mipi_csi2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mipi_csi2.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,87 @@
++/*
++ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __INCLUDE_MIPI_CSI2_H
++#define __INCLUDE_MIPI_CSI2_H
++
++/* MIPI CSI2 registers */
++#define MIPI_CSI2_REG(offset) (offset)
++
++#define MIPI_CSI2_VERSION MIPI_CSI2_REG(0x000)
++#define MIPI_CSI2_N_LANES MIPI_CSI2_REG(0x004)
++#define MIPI_CSI2_PHY_SHUTDOWNZ MIPI_CSI2_REG(0x008)
++#define MIPI_CSI2_DPHY_RSTZ MIPI_CSI2_REG(0x00c)
++#define MIPI_CSI2_CSI2_RESETN MIPI_CSI2_REG(0x010)
++#define MIPI_CSI2_PHY_STATE MIPI_CSI2_REG(0x014)
++#define MIPI_CSI2_DATA_IDS_1 MIPI_CSI2_REG(0x018)
++#define MIPI_CSI2_DATA_IDS_2 MIPI_CSI2_REG(0x01c)
++#define MIPI_CSI2_ERR1 MIPI_CSI2_REG(0x020)
++#define MIPI_CSI2_ERR2 MIPI_CSI2_REG(0x024)
++#define MIPI_CSI2_MASK1 MIPI_CSI2_REG(0x028)
++#define MIPI_CSI2_MASK2 MIPI_CSI2_REG(0x02c)
++#define MIPI_CSI2_PHY_TST_CTRL0 MIPI_CSI2_REG(0x030)
++#define MIPI_CSI2_PHY_TST_CTRL1 MIPI_CSI2_REG(0x034)
++#define MIPI_CSI2_SFT_RESET MIPI_CSI2_REG(0xf00)
++
++/* mipi data type */
++#define MIPI_DT_YUV420 0x18 /* YYY.../UYVY.... */
++#define MIPI_DT_YUV420_LEGACY 0x1a /* UYY.../VYY... */
++#define MIPI_DT_YUV422 0x1e /* UYVY... */
++#define MIPI_DT_RGB444 0x20
++#define MIPI_DT_RGB555 0x21
++#define MIPI_DT_RGB565 0x22
++#define MIPI_DT_RGB666 0x23
++#define MIPI_DT_RGB888 0x24
++#define MIPI_DT_RAW6 0x28
++#define MIPI_DT_RAW7 0x29
++#define MIPI_DT_RAW8 0x2a
++#define MIPI_DT_RAW10 0x2b
++#define MIPI_DT_RAW12 0x2c
++#define MIPI_DT_RAW14 0x2d
++
++
++struct mipi_csi2_info;
++/* mipi csi2 API */
++struct mipi_csi2_info *mipi_csi2_get_info(void);
++
++bool mipi_csi2_enable(struct mipi_csi2_info *info);
++
++bool mipi_csi2_disable(struct mipi_csi2_info *info);
++
++bool mipi_csi2_get_status(struct mipi_csi2_info *info);
++
++int mipi_csi2_set_lanes(struct mipi_csi2_info *info, unsigned lanes);
++
++unsigned int mipi_csi2_set_datatype(struct mipi_csi2_info *info,
++ unsigned int datatype);
++
++unsigned int mipi_csi2_get_datatype(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_dphy_status(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_error1(struct mipi_csi2_info *info);
++
++unsigned int mipi_csi2_get_error2(struct mipi_csi2_info *info);
++
++int mipi_csi2_pixelclk_enable(struct mipi_csi2_info *info);
++
++void mipi_csi2_pixelclk_disable(struct mipi_csi2_info *info);
++
++int mipi_csi2_reset(struct mipi_csi2_info *info);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mipi_dsi.h linux-3.14.72/include/linux/mipi_dsi.h
+--- linux-3.14.72.orig/include/linux/mipi_dsi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mipi_dsi.h 2016-06-19 22:11:55.497127409 +0200
+@@ -0,0 +1,171 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __INCLUDE_MIPI_DSI_H
++#define __INCLUDE_MIPI_DSI_H
++
++#define MIPI_DSI_VERSION (0x000)
++#define MIPI_DSI_PWR_UP (0x004)
++#define MIPI_DSI_CLKMGR_CFG (0x008)
++#define MIPI_DSI_DPI_CFG (0x00c)
++#define MIPI_DSI_DBI_CFG (0x010)
++#define MIPI_DSI_DBIS_CMDSIZE (0x014)
++#define MIPI_DSI_PCKHDL_CFG (0x018)
++#define MIPI_DSI_VID_MODE_CFG (0x01c)
++#define MIPI_DSI_VID_PKT_CFG (0x020)
++#define MIPI_DSI_CMD_MODE_CFG (0x024)
++#define MIPI_DSI_TMR_LINE_CFG (0x028)
++#define MIPI_DSI_VTIMING_CFG (0x02c)
++#define MIPI_DSI_PHY_TMR_CFG (0x030)
++#define MIPI_DSI_GEN_HDR (0x034)
++#define MIPI_DSI_GEN_PLD_DATA (0x038)
++#define MIPI_DSI_CMD_PKT_STATUS (0x03c)
++#define MIPI_DSI_TO_CNT_CFG (0x040)
++#define MIPI_DSI_ERROR_ST0 (0x044)
++#define MIPI_DSI_ERROR_ST1 (0x048)
++#define MIPI_DSI_ERROR_MSK0 (0x04c)
++#define MIPI_DSI_ERROR_MSK1 (0x050)
++#define MIPI_DSI_PHY_RSTZ (0x054)
++#define MIPI_DSI_PHY_IF_CFG (0x058)
++#define MIPI_DSI_PHY_IF_CTRL (0x05c)
++#define MIPI_DSI_PHY_STATUS (0x060)
++#define MIPI_DSI_PHY_TST_CTRL0 (0x064)
++#define MIPI_DSI_PHY_TST_CTRL1 (0x068)
++
++#define DSI_PWRUP_RESET (0x0 << 0)
++#define DSI_PWRUP_POWERUP (0x1 << 0)
++
++#define DSI_DPI_CFG_VID_SHIFT (0)
++#define DSI_DPI_CFG_VID_MASK (0x3)
++#define DSI_DPI_CFG_COLORCODE_SHIFT (2)
++#define DSI_DPI_CFG_COLORCODE_MASK (0x7)
++#define DSI_DPI_CFG_DATAEN_ACT_LOW (0x1 << 5)
++#define DSI_DPI_CFG_DATAEN_ACT_HIGH (0x0 << 5)
++#define DSI_DPI_CFG_VSYNC_ACT_LOW (0x1 << 6)
++#define DSI_DPI_CFG_VSYNC_ACT_HIGH (0x0 << 6)
++#define DSI_DPI_CFG_HSYNC_ACT_LOW (0x1 << 7)
++#define DSI_DPI_CFG_HSYNC_ACT_HIGH (0x0 << 7)
++#define DSI_DPI_CFG_SHUTD_ACT_LOW (0x1 << 8)
++#define DSI_DPI_CFG_SHUTD_ACT_HIGH (0x0 << 8)
++#define DSI_DPI_CFG_COLORMODE_ACT_LOW (0x1 << 9)
++#define DSI_DPI_CFG_COLORMODE_ACT_HIGH (0x0 << 9)
++#define DSI_DPI_CFG_EN18LOOSELY (0x1 << 10)
++
++#define DSI_PCKHDL_CFG_EN_EOTP_TX (0x1 << 0)
++#define DSI_PCKHDL_CFG_EN_EOTP_RX (0x1 << 1)
++#define DSI_PCKHDL_CFG_EN_BTA (0x1 << 2)
++#define DSI_PCKHDL_CFG_EN_ECC_RX (0x1 << 3)
++#define DSI_PCKHDL_CFG_EN_CRC_RX (0x1 << 4)
++#define DSI_PCKHDL_CFG_GEN_VID_RX_MASK (0x3)
++#define DSI_PCKHDL_CFG_GEN_VID_RX_SHIFT (5)
++
++#define DSI_VID_MODE_CFG_EN (0x1 << 0)
++#define DSI_VID_MODE_CFG_EN_BURSTMODE (0x3 << 1)
++#define DSI_VID_MODE_CFG_TYPE_MASK (0x3)
++#define DSI_VID_MODE_CFG_TYPE_SHIFT (1)
++#define DSI_VID_MODE_CFG_EN_LP_VSA (0x1 << 3)
++#define DSI_VID_MODE_CFG_EN_LP_VBP (0x1 << 4)
++#define DSI_VID_MODE_CFG_EN_LP_VFP (0x1 << 5)
++#define DSI_VID_MODE_CFG_EN_LP_VACT (0x1 << 6)
++#define DSI_VID_MODE_CFG_EN_LP_HBP (0x1 << 7)
++#define DSI_VID_MODE_CFG_EN_LP_HFP (0x1 << 8)
++#define DSI_VID_MODE_CFG_EN_MULTI_PKT (0x1 << 9)
++#define DSI_VID_MODE_CFG_EN_NULL_PKT (0x1 << 10)
++#define DSI_VID_MODE_CFG_EN_FRAME_ACK (0x1 << 11)
++#define DSI_VID_MODE_CFG_EN_LP_MODE (DSI_VID_MODE_CFG_EN_LP_VSA | \
++ DSI_VID_MODE_CFG_EN_LP_VBP | \
++ DSI_VID_MODE_CFG_EN_LP_VFP | \
++ DSI_VID_MODE_CFG_EN_LP_HFP | \
++ DSI_VID_MODE_CFG_EN_LP_HBP | \
++ DSI_VID_MODE_CFG_EN_LP_VACT)
++
++
++
++#define DSI_VID_PKT_CFG_VID_PKT_SZ_MASK (0x7ff)
++#define DSI_VID_PKT_CFG_VID_PKT_SZ_SHIFT (0)
++#define DSI_VID_PKT_CFG_NUM_CHUNKS_MASK (0x3ff)
++#define DSI_VID_PKT_CFG_NUM_CHUNKS_SHIFT (11)
++#define DSI_VID_PKT_CFG_NULL_PKT_SZ_MASK (0x3ff)
++#define DSI_VID_PKT_CFG_NULL_PKT_SZ_SHIFT (21)
++
++#define MIPI_DSI_CMD_MODE_CFG_EN_LOWPOWER (0x1FFF)
++#define MIPI_DSI_CMD_MODE_CFG_EN_CMD_MODE (0x1 << 0)
++
++#define DSI_TME_LINE_CFG_HSA_TIME_MASK (0x1ff)
++#define DSI_TME_LINE_CFG_HSA_TIME_SHIFT (0)
++#define DSI_TME_LINE_CFG_HBP_TIME_MASK (0x1ff)
++#define DSI_TME_LINE_CFG_HBP_TIME_SHIFT (9)
++#define DSI_TME_LINE_CFG_HLINE_TIME_MASK (0x3fff)
++#define DSI_TME_LINE_CFG_HLINE_TIME_SHIFT (18)
++
++#define DSI_VTIMING_CFG_VSA_LINES_MASK (0xf)
++#define DSI_VTIMING_CFG_VSA_LINES_SHIFT (0)
++#define DSI_VTIMING_CFG_VBP_LINES_MASK (0x3f)
++#define DSI_VTIMING_CFG_VBP_LINES_SHIFT (4)
++#define DSI_VTIMING_CFG_VFP_LINES_MASK (0x3f)
++#define DSI_VTIMING_CFG_VFP_LINES_SHIFT (10)
++#define DSI_VTIMING_CFG_V_ACT_LINES_MASK (0x7ff)
++#define DSI_VTIMING_CFG_V_ACT_LINES_SHIFT (16)
++
++#define DSI_PHY_TMR_CFG_BTA_TIME_MASK (0xfff)
++#define DSI_PHY_TMR_CFG_BTA_TIME_SHIFT (0)
++#define DSI_PHY_TMR_CFG_LP2HS_TIME_MASK (0xff)
++#define DSI_PHY_TMR_CFG_LP2HS_TIME_SHIFT (12)
++#define DSI_PHY_TMR_CFG_HS2LP_TIME_MASK (0xff)
++#define DSI_PHY_TMR_CFG_HS2LP_TIME_SHIFT (20)
++
++#define DSI_PHY_IF_CFG_N_LANES_MASK (0x3)
++#define DSI_PHY_IF_CFG_N_LANES_SHIFT (0)
++#define DSI_PHY_IF_CFG_WAIT_TIME_MASK (0xff)
++#define DSI_PHY_IF_CFG_WAIT_TIME_SHIFT (2)
++
++#define DSI_PHY_RSTZ_EN_CLK (0x1 << 2)
++#define DSI_PHY_RSTZ_DISABLE_RST (0x1 << 1)
++#define DSI_PHY_RSTZ_DISABLE_SHUTDOWN (0x1 << 0)
++#define DSI_PHY_RSTZ_RST (0x0)
++
++#define DSI_PHY_STATUS_LOCK (0x1 << 0)
++#define DSI_PHY_STATUS_STOPSTATE_CLK_LANE (0x1 << 2)
++
++#define DSI_GEN_HDR_TYPE_MASK (0xff)
++#define DSI_GEN_HDR_TYPE_SHIFT (0)
++#define DSI_GEN_HDR_DATA_MASK (0xffff)
++#define DSI_GEN_HDR_DATA_SHIFT (8)
++
++#define DSI_CMD_PKT_STATUS_GEN_CMD_EMPTY (0x1 << 0)
++#define DSI_CMD_PKT_STATUS_GEN_CMD_FULL (0x1 << 1)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_W_EMPTY (0x1 << 2)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_W_FULL (0x1 << 3)
++#define DSI_CMD_PKT_STATUS_GEN_PLD_R_EMPTY (0x1 << 4)
++#define DSI_CMD_PKT_STATUS_GEN_RD_CMD_BUSY (0x1 << 6)
++
++#define DSI_ERROR_MSK0_ALL_MASK (0x1fffff)
++#define DSI_ERROR_MSK1_ALL_MASK (0x3ffff)
++
++#define DSI_PHY_IF_CTRL_RESET (0x0)
++#define DSI_PHY_IF_CTRL_TX_REQ_CLK_HS (0x1 << 0)
++#define DSI_PHY_IF_CTRL_TX_REQ_CLK_ULPS (0x1 << 1)
++#define DSI_PHY_IF_CTRL_TX_EXIT_CLK_ULPS (0x1 << 2)
++#define DSI_PHY_IF_CTRL_TX_REQ_DATA_ULPS (0x1 << 3)
++#define DSI_PHY_IF_CTRL_TX_EXIT_DATA_ULPS (0x1 << 4)
++#define DSI_PHY_IF_CTRL_TX_TRIG_MASK (0xF)
++#define DSI_PHY_IF_CTRL_TX_TRIG_SHIFT (5)
++
++#define DSI_PHY_CLK_INIT_COMMAND (0x44)
++#define DSI_GEN_PLD_DATA_BUF_SIZE (0x4)
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mmc/card.h linux-3.14.72/include/linux/mmc/card.h
+--- linux-3.14.72.orig/include/linux/mmc/card.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mmc/card.h 2016-06-19 22:11:55.497127409 +0200
+@@ -86,10 +86,12 @@
+ unsigned int data_sector_size; /* 512 bytes or 4KB */
+ unsigned int data_tag_unit_size; /* DATA TAG UNIT size */
+ unsigned int boot_ro_lock; /* ro lock support */
++ unsigned int boot_size;
+ bool boot_ro_lockable;
+ u8 raw_exception_status; /* 54 */
+ u8 raw_partition_support; /* 160 */
+ u8 raw_rpmb_size_mult; /* 168 */
++ u8 boot_bus_width; /* 177 */
+ u8 raw_erased_mem_count; /* 181 */
+ u8 raw_ext_csd_structure; /* 194 */
+ u8 raw_card_type; /* 196 */
+@@ -102,6 +104,7 @@
+ u8 raw_hc_erase_gap_size; /* 221 */
+ u8 raw_erase_timeout_mult; /* 223 */
+ u8 raw_hc_erase_grp_size; /* 224 */
++ u8 boot_info; /* 228 */
+ u8 raw_sec_trim_mult; /* 229 */
+ u8 raw_sec_erase_mult; /* 230 */
+ u8 raw_sec_feature_support;/* 231 */
+@@ -279,6 +282,7 @@
+ unsigned int erase_size; /* erase size in sectors */
+ unsigned int erase_shift; /* if erase unit is power 2 */
+ unsigned int pref_erase; /* in sectors */
++ unsigned int eg_boundary; /* don't cross erase-group boundaries */
+ u8 erased_byte; /* value of erased bytes */
+
+ u32 raw_cid[4]; /* raw card CID */
+diff -Nur linux-3.14.72.orig/include/linux/mmc/core.h linux-3.14.72/include/linux/mmc/core.h
+--- linux-3.14.72.orig/include/linux/mmc/core.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mmc/core.h 2016-06-19 22:11:55.497127409 +0200
+@@ -197,6 +197,9 @@
+
+ extern int mmc_detect_card_removed(struct mmc_host *host);
+
++int mmc_first_nonreserved_index(void);
++int mmc_get_reserved_index(struct mmc_host *host);
++
+ /**
+ * mmc_claim_host - exclusively claim a host
+ * @host: mmc host to claim
+diff -Nur linux-3.14.72.orig/include/linux/mmc/host.h linux-3.14.72/include/linux/mmc/host.h
+--- linux-3.14.72.orig/include/linux/mmc/host.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mmc/host.h 2016-06-19 22:11:55.497127409 +0200
+@@ -58,7 +58,8 @@
+ #define MMC_TIMING_UHS_SDR50 5
+ #define MMC_TIMING_UHS_SDR104 6
+ #define MMC_TIMING_UHS_DDR50 7
+-#define MMC_TIMING_MMC_HS200 8
++#define MMC_TIMING_MMC_DDR52 8
++#define MMC_TIMING_MMC_HS200 9
+
+ #define MMC_SDR_MODE 0
+ #define MMC_1_2V_DDR_MODE 1
+@@ -282,6 +283,7 @@
+ MMC_CAP2_PACKED_WR)
+ #define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */
+ #define MMC_CAP2_SANITIZE (1 << 15) /* Support Sanitize */
++#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 16)
+
+ mmc_pm_flag_t pm_caps; /* supported pm features */
+
+@@ -297,6 +299,11 @@
+ unsigned long clkgate_delay;
+ #endif
+
++ /* card specific properties to deal with power and reset */
++ struct regulator *card_regulator; /* External VCC needed by the card */
++ struct gpio_desc *card_reset_gpios[2]; /* External resets, active low */
++ struct clk *card_clk; /* External clock needed by the card */
++
+ /* host specific block data */
+ unsigned int max_seg_size; /* see blk_queue_max_segment_size */
+ unsigned short max_segs; /* see blk_queue_max_segments */
+@@ -397,6 +404,8 @@
+ wake_up_process(host->sdio_irq_thread);
+ }
+
++void sdio_run_irqs(struct mmc_host *host);
++
+ #ifdef CONFIG_REGULATOR
+ int mmc_regulator_get_ocrmask(struct regulator *supply);
+ int mmc_regulator_set_ocr(struct mmc_host *mmc,
+diff -Nur linux-3.14.72.orig/include/linux/mmc/mmc.h linux-3.14.72/include/linux/mmc/mmc.h
+--- linux-3.14.72.orig/include/linux/mmc/mmc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mmc/mmc.h 2016-06-19 22:11:55.497127409 +0200
+@@ -292,6 +292,7 @@
+ #define EXT_CSD_RPMB_MULT 168 /* RO */
+ #define EXT_CSD_BOOT_WP 173 /* R/W */
+ #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
++#define EXT_CSD_BOOT_BUS_WIDTH 177 /* R/W */
+ #define EXT_CSD_PART_CONFIG 179 /* R/W */
+ #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
+ #define EXT_CSD_BUS_WIDTH 183 /* R/W */
+@@ -313,6 +314,7 @@
+ #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
+ #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
+ #define EXT_CSD_BOOT_MULT 226 /* RO */
++#define EXT_CSD_BOOT_INFO 228 /* RO, 1 bytes */
+ #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
+ #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
+ #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
+@@ -378,6 +380,29 @@
+ #define EXT_CSD_SEC_GB_CL_EN BIT(4)
+ #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
+
++#define EXT_CSD_BOOT_BUS_WIDTH_MASK (0x1F)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_MASK (0x3 << 3)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_NORMAL (0x0)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_SDR_HIGH (0x1)
++#define EXT_CSD_BOOT_BUS_WIDTH_MODE_DDR (0x2)
++#define EXT_CSD_BOOT_BUS_WIDTH_RST_WIDTH (1 << 2)
++#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH_MASK (0x3)
++#define EXT_CSD_BOOT_BUS_WIDTH_1_SDR_4_DDR (0x0)
++#define EXT_CSD_BOOT_BUS_WIDTH_4_SDR_4_DDR (0x1)
++#define EXT_CSD_BOOT_BUS_WIDTH_8_SDR_8_DDR (0x2)
++
++#define EXT_CSD_BOOT_ACK_ENABLE (0x1 << 6)
++#define EXT_CSD_BOOT_PARTITION_ENABLE_MASK (0x7 << 3)
++#define EXT_CSD_BOOT_PARTITION_DISABLE (0x0)
++#define EXT_CSD_BOOT_PARTITION_PART1 (0x1 << 3)
++#define EXT_CSD_BOOT_PARTITION_PART2 (0x2 << 3)
++#define EXT_CSD_BOOT_PARTITION_USER (0x7 << 3)
++
++#define EXT_CSD_BOOT_PARTITION_ACCESS_MASK (0x7)
++#define EXT_CSD_BOOT_PARTITION_ACCESS_DISABLE (0x0)
++#define EXT_CSD_BOOT_PARTITION_ACCESS_PART1 (0x1)
++#define EXT_CSD_BOOT_PARTITION_ACCESS_PART2 (0x2)
++
+ #define EXT_CSD_RST_N_EN_MASK 0x3
+ #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
+
+diff -Nur linux-3.14.72.orig/include/linux/mmc/sdhci.h linux-3.14.72/include/linux/mmc/sdhci.h
+--- linux-3.14.72.orig/include/linux/mmc/sdhci.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mmc/sdhci.h 2016-06-19 22:11:55.497127409 +0200
+@@ -17,6 +17,11 @@
+ #include <linux/io.h>
+ #include <linux/mmc/host.h>
+
++struct sdhci_host_next {
++ unsigned int sg_count;
++ s32 cookie;
++};
++
+ struct sdhci_host {
+ /* Data set by hardware interface driver */
+ const char *hw_name; /* Hardware bus name */
+@@ -57,12 +62,8 @@
+ #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
+ /* Controller reports inverted write-protect state */
+ #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
+-/* Controller has nonstandard clock management */
+-#define SDHCI_QUIRK_NONSTANDARD_CLOCK (1<<17)
+ /* Controller does not like fast PIO transfers */
+ #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
+-/* Controller losing signal/interrupt enable states after reset */
+-#define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET (1<<19)
+ /* Controller has to be forced to use block size of 2048 bytes */
+ #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
+ /* Controller cannot do multi-block transfers */
+@@ -96,6 +97,7 @@
+ #define SDHCI_QUIRK2_NO_1_8_V (1<<2)
+ #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
+ #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
++#define SDHCI_QUIRK2_NOSTD_TIMEOUT_COUNTER (1<<5)
+ /* Controller has a non-standard host control register */
+ #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
+ /* Controller does not support HS200 */
+@@ -145,6 +147,7 @@
+
+ bool runtime_suspended; /* Host is runtime suspended */
+ bool bus_on; /* Bus power prevents runtime suspend */
++ bool preset_enabled; /* Preset is enabled */
+
+ struct mmc_request *mrq; /* Current request */
+ struct mmc_command *cmd; /* Current command */
+@@ -162,8 +165,7 @@
+ dma_addr_t adma_addr; /* Mapped ADMA descr. table */
+ dma_addr_t align_addr; /* Mapped bounce buffer */
+
+- struct tasklet_struct card_tasklet; /* Tasklet structures */
+- struct tasklet_struct finish_tasklet;
++ struct tasklet_struct finish_tasklet; /* Tasklet structures */
+
+ struct timer_list timer; /* Timer for timeouts */
+
+@@ -175,6 +177,13 @@
+ unsigned int ocr_avail_mmc;
+ u32 ocr_mask; /* available voltages */
+
++ unsigned timing; /* Current timing */
++
++ u32 thread_isr;
++
++ /* cached registers */
++ u32 ier;
++
+ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
+ unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
+
+@@ -183,6 +192,7 @@
+ #define SDHCI_TUNING_MODE_1 0
+ struct timer_list tuning_timer; /* Timer for tuning */
+
++ struct sdhci_host_next next_data;
+ unsigned long private[0] ____cacheline_aligned;
+ };
+ #endif /* LINUX_MMC_SDHCI_H */
+diff -Nur linux-3.14.72.orig/include/linux/mmc/sdio_ids.h linux-3.14.72/include/linux/mmc/sdio_ids.h
+--- linux-3.14.72.orig/include/linux/mmc/sdio_ids.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mmc/sdio_ids.h 2016-06-19 22:11:55.497127409 +0200
+@@ -24,13 +24,18 @@
+ * Vendors and devices. Sort key: vendor first, device next.
+ */
+ #define SDIO_VENDOR_ID_BROADCOM 0x02d0
+-#define SDIO_DEVICE_ID_BROADCOM_43143 43143
++#define SDIO_DEVICE_ID_BROADCOM_43143 0xa887
+ #define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
+ #define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
+ #define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
+ #define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
++#define SDIO_DEVICE_ID_BROADCOM_43340 0xa94c
++#define SDIO_DEVICE_ID_BROADCOM_43341 0xa94d
+ #define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
+-#define SDIO_DEVICE_ID_BROADCOM_43362 43362
++#define SDIO_DEVICE_ID_BROADCOM_43362 0xa962
++#define SDIO_DEVICE_ID_BROADCOM_43430 0xa9a6
++#define SDIO_DEVICE_ID_BROADCOM_4345 0x4345
++#define SDIO_DEVICE_ID_BROADCOM_4354 0x4354
+
+ #define SDIO_VENDOR_ID_INTEL 0x0089
+ #define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402
+diff -Nur linux-3.14.72.orig/include/linux/mtd/nand.h linux-3.14.72/include/linux/mtd/nand.h
+--- linux-3.14.72.orig/include/linux/mtd/nand.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/mtd/nand.h 2016-06-19 22:11:55.501127146 +0200
+@@ -52,14 +52,6 @@
+ #define NAND_MAX_CHIPS 8
+
+ /*
+- * This constant declares the max. oobsize / page, which
+- * is supported now. If you add a chip with bigger oobsize/page
+- * adjust this accordingly.
+- */
+-#define NAND_MAX_OOBSIZE 744
+-#define NAND_MAX_PAGESIZE 8192
+-
+-/*
+ * Constants for hardware specific CLE/ALE/NCE function
+ *
+ * These are bits which can be or'ed to set/clear multiple
+@@ -184,6 +176,11 @@
+ /* Chip may not exist, so silence any errors in scan */
+ #define NAND_SCAN_SILENT_NODEV 0x00040000
+ /*
++ * This option could be defined by controller drivers to protect against
++ * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
++ */
++#define NAND_USE_BOUNCE_BUFFER 0x00080000
++/*
+ * Autodetect nand buswidth with readid/onfi.
+ * This suppose the driver will configure the hardware in 8 bits mode
+ * when calling nand_scan_ident, and update its configuration
+@@ -350,6 +347,84 @@
+ u8 param_revision;
+ } __packed;
+
++struct jedec_ecc_info {
++ u8 ecc_bits;
++ u8 codeword_size;
++ __le16 bb_per_lun;
++ __le16 block_endurance;
++ u8 reserved[2];
++} __packed;
++
++/* JEDEC features */
++#define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
++
++struct nand_jedec_params {
++ /* rev info and features block */
++ /* 'J' 'E' 'S' 'D' */
++ u8 sig[4];
++ __le16 revision;
++ __le16 features;
++ u8 opt_cmd[3];
++ __le16 sec_cmd;
++ u8 num_of_param_pages;
++ u8 reserved0[18];
++
++ /* manufacturer information block */
++ char manufacturer[12];
++ char model[20];
++ u8 jedec_id[6];
++ u8 reserved1[10];
++
++ /* memory organization block */
++ __le32 byte_per_page;
++ __le16 spare_bytes_per_page;
++ u8 reserved2[6];
++ __le32 pages_per_block;
++ __le32 blocks_per_lun;
++ u8 lun_count;
++ u8 addr_cycles;
++ u8 bits_per_cell;
++ u8 programs_per_page;
++ u8 multi_plane_addr;
++ u8 multi_plane_op_attr;
++ u8 reserved3[38];
++
++ /* electrical parameter block */
++ __le16 async_sdr_speed_grade;
++ __le16 toggle_ddr_speed_grade;
++ __le16 sync_ddr_speed_grade;
++ u8 async_sdr_features;
++ u8 toggle_ddr_features;
++ u8 sync_ddr_features;
++ __le16 t_prog;
++ __le16 t_bers;
++ __le16 t_r;
++ __le16 t_r_multi_plane;
++ __le16 t_ccs;
++ __le16 io_pin_capacitance_typ;
++ __le16 input_pin_capacitance_typ;
++ __le16 clk_pin_capacitance_typ;
++ u8 driver_strength_support;
++ __le16 t_ald;
++ u8 reserved4[36];
++
++ /* ECC and endurance block */
++ u8 guaranteed_good_blocks;
++ __le16 guaranteed_block_endurance;
++ struct jedec_ecc_info ecc_info[4];
++ u8 reserved5[29];
++
++ /* reserved */
++ u8 reserved6[148];
++
++ /* vendor */
++ __le16 vendor_rev_num;
++ u8 reserved7[88];
++
++ /* CRC for Parameter Page */
++ __le16 crc;
++} __packed;
++
+ /**
+ * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
+ * @lock: protection lock
+@@ -418,7 +493,7 @@
+ int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page);
+ int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+- uint32_t offs, uint32_t len, uint8_t *buf);
++ uint32_t offs, uint32_t len, uint8_t *buf, int page);
+ int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
+ uint32_t offset, uint32_t data_len,
+ const uint8_t *data_buf, int oob_required);
+@@ -435,17 +510,17 @@
+
+ /**
+ * struct nand_buffers - buffer structure for read/write
+- * @ecccalc: buffer for calculated ECC
+- * @ecccode: buffer for ECC read from flash
+- * @databuf: buffer for data - dynamically sized
++ * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
++ * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
++ * @databuf: buffer pointer for data, size is (page size + oobsize).
+ *
+ * Do not change the order of buffers. databuf and oobrbuf must be in
+ * consecutive order.
+ */
+ struct nand_buffers {
+- uint8_t ecccalc[NAND_MAX_OOBSIZE];
+- uint8_t ecccode[NAND_MAX_OOBSIZE];
+- uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
++ uint8_t *ecccalc;
++ uint8_t *ecccode;
++ uint8_t *databuf;
+ };
+
+ /**
+@@ -482,8 +557,7 @@
+ * @ecc: [BOARDSPECIFIC] ECC control structure
+ * @buffers: buffer structure for read/write
+ * @hwcontrol: platform-specific hardware control structure
+- * @erase_cmd: [INTERN] erase command write function, selectable due
+- * to AND support.
++ * @erase: [REPLACEABLE] erase function
+ * @scan_bbt: [REPLACEABLE] function to scan bad block table
+ * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
+ * data from array to read regs (tR).
+@@ -523,8 +597,12 @@
+ * @subpagesize: [INTERN] holds the subpagesize
+ * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
+ * non 0 if ONFI supported.
++ * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
++ * non 0 if JEDEC supported.
+ * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
+ * supported, 0 otherwise.
++ * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
++ * supported, 0 otherwise.
+ * @read_retries: [INTERN] the number of read retry modes supported
+ * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
+@@ -563,7 +641,7 @@
+ void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
+ int page_addr);
+ int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
+- void (*erase_cmd)(struct mtd_info *mtd, int page);
++ int (*erase)(struct mtd_info *mtd, int page);
+ int (*scan_bbt)(struct mtd_info *mtd);
+ int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
+ int status, int page);
+@@ -597,7 +675,11 @@
+ int badblockbits;
+
+ int onfi_version;
+- struct nand_onfi_params onfi_params;
++ int jedec_version;
++ union {
++ struct nand_onfi_params onfi_params;
++ struct nand_jedec_params jedec_params;
++ };
+
+ int read_retries;
+
+@@ -840,4 +922,29 @@
+ {
+ return chip->bits_per_cell == 1;
+ }
++
++/**
++ * Check if the opcode's address should be sent only on the lower 8 bits
++ * @command: opcode to check
++ */
++static inline int nand_opcode_8bits(unsigned int command)
++{
++ switch (command) {
++ case NAND_CMD_READID:
++ case NAND_CMD_PARAM:
++ case NAND_CMD_GET_FEATURES:
++ case NAND_CMD_SET_FEATURES:
++ return 1;
++ default:
++ break;
++ }
++ return 0;
++}
++
++/* return the supported JEDEC features. */
++static inline int jedec_feature(struct nand_chip *chip)
++{
++ return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
++ : 0;
++}
+ #endif /* __LINUX_MTD_NAND_H */
+diff -Nur linux-3.14.72.orig/include/linux/mtd/spi-nor.h linux-3.14.72/include/linux/mtd/spi-nor.h
+--- linux-3.14.72.orig/include/linux/mtd/spi-nor.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mtd/spi-nor.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,213 @@
++#ifndef __LINUX_MTD_SPI_NOR_H
++#define __LINUX_MTD_SPI_NOR_H
++
++/*
++ * Note on opcode nomenclature: some opcodes have a format like
++ * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y, and z stand for the number
++ * of I/O lines used for the opcode, address, and data (respectively). The
++ * FUNCTION has an optional suffix of '4', to represent an opcode which
++ * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
++ * DDR mode.
++ */
++
++/* Flash opcodes. */
++#define SPINOR_OP_WREN 0x06 /* Write enable */
++#define SPINOR_OP_RDSR 0x05 /* Read status register */
++#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
++#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
++#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
++#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
++#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
++#define SPINOR_OP_READ_1_1_4_D 0x6d /* Read data bytes (DDR Quad SPI) */
++#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
++#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
++#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
++#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
++#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
++#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
++#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
++#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
++#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
++
++/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
++#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
++#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
++#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
++#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
++#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
++#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
++#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
++
++/* Used for SST flashes only. */
++#define SPINOR_OP_BP 0x02 /* Byte program */
++#define SPINOR_OP_WRDI 0x04 /* Write disable */
++#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
++
++/* Used for Macronix and Winbond flashes. */
++#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
++#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
++
++/* Used for Spansion flashes only. */
++#define SPINOR_OP_BRWR 0x17 /* Bank register write */
++
++/* Status Register bits. */
++#define SR_WIP 1 /* Write in progress */
++#define SR_WEL 2 /* Write enable latch */
++/* meaning of other SR_* bits may differ between vendors */
++#define SR_BP0 4 /* Block protect 0 */
++#define SR_BP1 8 /* Block protect 1 */
++#define SR_BP2 0x10 /* Block protect 2 */
++#define SR_SRWD 0x80 /* SR write protect */
++
++#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
++
++/* Configuration Register bits. */
++#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
++
++enum read_mode {
++ SPI_NOR_NORMAL = 0,
++ SPI_NOR_FAST,
++ SPI_NOR_DUAL,
++ SPI_NOR_QUAD,
++ SPI_NOR_DDR_QUAD,
++};
++
++/**
++ * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
++ * @wren: command for "Write Enable", or 0x00 for not required
++ * @cmd: command for operation
++ * @cmd_pins: number of pins to send @cmd (1, 2, 4)
++ * @addr: address for operation
++ * @addr_pins: number of pins to send @addr (1, 2, 4)
++ * @addr_width: number of address bytes
++ * (3,4, or 0 for address not required)
++ * @mode: mode data
++ * @mode_pins: number of pins to send @mode (1, 2, 4)
++ * @mode_cycles: number of mode cycles (0 for mode not required)
++ * @dummy_cycles: number of dummy cycles (0 for dummy not required)
++ */
++struct spi_nor_xfer_cfg {
++ u8 wren;
++ u8 cmd;
++ u8 cmd_pins;
++ u32 addr;
++ u8 addr_pins;
++ u8 addr_width;
++ u8 mode;
++ u8 mode_pins;
++ u8 mode_cycles;
++ u8 dummy_cycles;
++};
++
++#define SPI_NOR_MAX_CMD_SIZE 8
++enum spi_nor_ops {
++ SPI_NOR_OPS_READ = 0,
++ SPI_NOR_OPS_WRITE,
++ SPI_NOR_OPS_ERASE,
++ SPI_NOR_OPS_LOCK,
++ SPI_NOR_OPS_UNLOCK,
++};
++
++/**
++ * struct spi_nor - Structure for defining a the SPI NOR layer
++ * @mtd: point to a mtd_info structure
++ * @lock: the lock for the read/write/erase/lock/unlock operations
++ * @dev: point to a spi device, or a spi nor controller device.
++ * @np: If exit, it points to a device_node which stands for the
++ * SPI NOR flash child node.
++ * @page_size: the page size of the SPI NOR
++ * @addr_width: number of address bytes
++ * @erase_opcode: the opcode for erasing a sector
++ * @read_opcode: the read opcode
++ * @read_dummy: the dummy needed by the read operation
++ * @program_opcode: the program opcode
++ * @flash_read: the mode of the read
++ * @sst_write_second: used by the SST write operation
++ * @cfg: used by the read_xfer/write_xfer
++ * @cmd_buf: used by the write_reg
++ * @prepare: [OPTIONAL] do some preparations for the
++ * read/write/erase/lock/unlock operations
++ * @unprepare: [OPTIONAL] do some post work after the
++ * read/write/erase/lock/unlock operations
++ * @read_xfer: [OPTIONAL] the read fundamental primitive
++ * @write_xfer: [OPTIONAL] the writefundamental primitive
++ * @read_reg: [DRIVER-SPECIFIC] read out the register
++ * @write_reg: [DRIVER-SPECIFIC] write data to the register
++ * @read_id: [REPLACEABLE] read out the ID data, and find
++ * the proper spi_device_id
++ * @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready
++ * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
++ * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
++ * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
++ * at the offset @offs
++ * @priv: the private data
++ */
++struct spi_nor {
++ struct mtd_info *mtd;
++ struct mutex lock;
++ struct device *dev;
++ struct device_node *np;
++ u32 page_size;
++ u8 addr_width;
++ u8 erase_opcode;
++ u8 read_opcode;
++ u8 read_dummy;
++ u8 program_opcode;
++ enum read_mode flash_read;
++ bool sst_write_second;
++ struct spi_nor_xfer_cfg cfg;
++ u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
++
++ int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
++ void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
++ int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
++ u8 *buf, size_t len);
++ int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
++ u8 *buf, size_t len);
++ int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
++ int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
++ int write_enable);
++ const struct spi_device_id *(*read_id)(struct spi_nor *nor);
++ int (*wait_till_ready)(struct spi_nor *nor);
++
++ int (*read)(struct spi_nor *nor, loff_t from,
++ size_t len, size_t *retlen, u_char *read_buf);
++ void (*write)(struct spi_nor *nor, loff_t to,
++ size_t len, size_t *retlen, const u_char *write_buf);
++ int (*erase)(struct spi_nor *nor, loff_t offs);
++
++ void *priv;
++};
++
++/**
++ * spi_nor_scan() - scan the SPI NOR
++ * @nor: the spi_nor structure
++ * @id: the spi_device_id provided by the driver
++ * @mode: the read mode supported by the driver
++ *
++ * The drivers can use this fuction to scan the SPI NOR.
++ * In the scanning, it will try to get all the necessary information to
++ * fill the mtd_info{} and the spi_nor{}.
++ *
++ * The board may assigns a spi_device_id with @id which be used to compared with
++ * the spi_device_id detected by the scanning.
++ *
++ * Return: 0 for success, others for failure.
++ */
++int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
++ enum read_mode mode);
++extern const struct spi_device_id spi_nor_ids[];
++
++/**
++ * spi_nor_match_id() - find the spi_device_id by the name
++ * @name: the name of the spi_device_id
++ *
++ * The drivers use this function to find the spi_device_id
++ * specified by the @name.
++ *
++ * Return: returns the right spi_device_id pointer on success,
++ * and returns NULL on failure.
++ */
++const struct spi_device_id *spi_nor_match_id(char *name);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mxc_dcic.h linux-3.14.72/include/linux/mxc_dcic.h
+--- linux-3.14.72.orig/include/linux/mxc_dcic.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mxc_dcic.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,134 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file linux/mxc_dcic.h
++ *
++ * @brief Global header file for the MXC DCIC driver
++ *
++ * @ingroup MXC DCIC
++ */
++
++#ifndef __LINUX_DCIC_H__
++#define __LINUX_DCIC_H__
++
++#include <uapi/linux/mxc_dcic.h>
++
++#define DCICC_IC_ENABLE 0x1
++#define DCICC_IC_DISABLE 0x0
++#define DCICC_IC_MASK 0x1
++#define DCICC_DE_ACTIVE_HIGH 0
++#define DCICC_DE_ACTIVE_LOW (0x1 << 4)
++#define DCICC_DE_ACTIVE_MASK (0x1 << 4)
++#define DCICC_HSYNC_POL_ACTIVE_HIGH 0
++#define DCICC_HSYNC_POL_ACTIVE_LOW (0x1 << 5)
++#define DCICC_HSYNC_POL_ACTIVE_MASK (0x1 << 5)
++#define DCICC_VSYNC_POL_ACTIVE_HIGH 0
++#define DCICC_VSYNC_POL_ACTIVE_LOW (0x1 << 6)
++#define DCICC_VSYNC_POL_ACTIVE_MASK (0x1 << 6)
++#define DCICC_CLK_POL_NO_INVERTED 0
++#define DCICC_CLK_POL_INVERTED (0x1 << 7)
++#define DCICC_CLK_POL_INVERTED_MASK (0x1 << 7)
++
++#define DCICIC_ERROR_INT_DISABLE 1
++#define DCICIC_ERROR_INT_ENABLE 0
++#define DCICIC_ERROR_INT_MASK_MASK 1
++#define DCICIC_FUN_INT_DISABLE (0x1 << 1)
++#define DCICIC_FUN_INT_ENABLE 0
++#define DCICIC_FUN_INT_MASK (0x1 << 1)
++#define DCICIC_FREEZE_MASK_CHANGED 0
++#define DCICIC_FREEZE_MASK_FORZEN (0x1 << 3)
++#define DCICIC_FREEZE_MASK_MASK (0x1 << 3)
++#define DCICIC_EXT_SIG_EX_DISABLE 0
++#define DCICIC_EXT_SIG_EN_ENABLE (0x1 << 16)
++#define DCICIC_EXT_SIG_EN_MASK (0x1 << 16)
++
++#define DCICS_ROI_MATCH_STAT_MASK 0xFFFF
++#define DCICS_EI_STAT_PENDING (0x1 << 16)
++#define DCICS_EI_STAT_NO_PENDING 0
++#define DCICS_FI_STAT_PENDING (0x1 << 17)
++#define DCICS_FI_STAT_NO_PENDING 0
++
++#define DCICRC_ROI_START_OFFSET_X_MASK 0x1FFF
++#define DCICRC_ROI_START_OFFSET_X_SHIFT 0
++#define DCICRC_ROI_START_OFFSET_Y_MASK (0xFFF << 16)
++#define DCICRC_ROI_START_OFFSET_Y_SHIFT 16
++#define DCICRC_ROI_CHANGED 0
++#define DCICRC_ROI_FROZEN (0x1 << 30)
++#define DCICRC_ROI_ENABLE (0x1 << 31)
++#define DCICRC_ROI_DISABLE 0
++
++#define DCICRS_ROI_END_OFFSET_X_MASK 0x1FFF
++#define DCICRS_ROI_END_OFFSET_X_SHIFT 0
++#define DCICRS_ROI_END_OFFSET_Y_MASK (0xFFF << 16)
++#define DCICRS_ROI_END_OFFSET_Y_SHIFT 16
++
++struct roi_regs {
++ u32 dcicrc;
++ u32 dcicrs;
++ u32 dcicrrs;
++ u32 dcicrcs;
++};
++
++struct dcic_regs {
++ u32 dcicc;
++ u32 dcicic;
++ u32 dcics;
++ u32 dcic_reserved;
++ struct roi_regs ROI[16];
++};
++
++struct dcic_mux {
++ char dcic[16];
++ u32 val;
++};
++
++struct bus_mux {
++ char name[16];
++ int reg;
++ int shift;
++ int mask;
++ int dcic_mux_num;
++ const struct dcic_mux *dcics;
++};
++
++struct dcic_info {
++ int bus_mux_num;
++ const struct bus_mux *buses;
++};
++
++struct dcic_data {
++ struct regmap *regmap;
++ struct device *dev;
++ struct dcic_regs *regs;
++ const struct bus_mux *buses;
++ u32 bus_n;
++ u32 mux_n;
++ struct clk *disp_axi_clk;
++ struct clk *dcic_clk;
++ struct mutex lock;
++ struct completion roi_crc_comp;
++ struct class *class;
++ int major;
++ struct cdev cdev; /* Char device structure */
++ dev_t devt;
++ unsigned int result;
++};
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mxcfb_epdc.h linux-3.14.72/include/linux/mxcfb_epdc.h
+--- linux-3.14.72.orig/include/linux/mxcfb_epdc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mxcfb_epdc.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _MXCFB_EPDC_KERNEL
++#define _MXCFB_EPDC_KERNEL
++
++struct imx_epdc_fb_mode {
++ struct fb_videomode *vmode;
++ int vscan_holdoff;
++ int sdoed_width;
++ int sdoed_delay;
++ int sdoez_width;
++ int sdoez_delay;
++ int gdclk_hp_offs;
++ int gdsp_offs;
++ int gdoe_offs;
++ int gdclk_offs;
++ int num_ce;
++};
++
++struct imx_epdc_fb_platform_data {
++ struct imx_epdc_fb_mode *epdc_mode;
++ int num_modes;
++ int (*get_pins) (void);
++ void (*put_pins) (void);
++ void (*enable_pins) (void);
++ void (*disable_pins) (void);
++};
++
++void mxc_epdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
++ struct fb_info *info);
++int mxc_epdc_fb_set_temperature(int temperature, struct fb_info *info);
++int mxc_epdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
++int mxc_epdc_fb_send_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info);
++int mxc_epdc_fb_wait_update_complete(
++ struct mxcfb_update_marker_data *marker_data,
++ struct fb_info *info);
++int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
++ struct fb_info *info);
++int mxc_epdc_get_pwrdown_delay(struct fb_info *info);
++int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
++
++void mxc_spdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes,
++ struct fb_info *info);
++int mxc_spdc_fb_set_temperature(int temperature, struct fb_info *info);
++int mxc_spdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info);
++int mxc_spdc_fb_send_update(struct mxcfb_update_data *upd_data,
++ struct fb_info *info);
++int mxc_spdc_fb_wait_update_complete(
++ struct mxcfb_update_marker_data *marker_data,
++ struct fb_info *info);
++int mxc_spdc_fb_set_pwrdown_delay(u32 pwrdown_delay,
++ struct fb_info *info);
++int mxc_spdc_get_pwrdown_delay(struct fb_info *info);
++int mxc_spdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info);
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mxcfb.h linux-3.14.72/include/linux/mxcfb.h
+--- linux-3.14.72.orig/include/linux/mxcfb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mxcfb.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,57 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*
++ * @file linux/mxcfb.h
++ *
++ * @brief Global header file for the MXC Frame buffer
++ *
++ * @ingroup Framebuffer
++ */
++#ifndef __LINUX_MXCFB_H__
++#define __LINUX_MXCFB_H__
++
++#include <uapi/linux/mxcfb.h>
++
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
++#define FB_SYNC_DATA_INVERT 0x20000000
++#define FB_SYNC_CLK_IDLE_EN 0x10000000
++#define FB_SYNC_SHARP_MODE 0x08000000
++#define FB_SYNC_SWAP_RGB 0x04000000
++
++#define FB_MXC_SYNC_MASK (FB_SYNC_OE_LOW_ACT | FB_SYNC_CLK_LAT_FALL | \
++ FB_SYNC_DATA_INVERT | FB_SYNC_CLK_IDLE_EN | \
++ FB_SYNC_SHARP_MODE | FB_SYNC_SWAP_RGB)
++
++extern struct fb_videomode mxcfb_modedb[];
++extern int mxcfb_modedb_sz;
++
++enum {
++ MXC_DISP_SPEC_DEV = 0,
++ MXC_DISP_DDC_DEV = 1,
++};
++
++enum {
++ MXCFB_REFRESH_OFF,
++ MXCFB_REFRESH_AUTO,
++ MXCFB_REFRESH_PARTIAL,
++};
++
++int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode,
++ struct mxcfb_rect *update_region);
++int mxc_elcdif_frame_addr_setup(dma_addr_t phys);
++void mxcfb_elcdif_register_mode(const struct fb_videomode *modedb,
++ int num_modes, int dev_mode);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mxc_mlb.h linux-3.14.72/include/linux/mxc_mlb.h
+--- linux-3.14.72.orig/include/linux/mxc_mlb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mxc_mlb.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,55 @@
++/*
++ * mxc_mlb.h
++ *
++ * Copyright 2008-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef _MXC_MLB_H
++#define _MXC_MLB_H
++
++/* define IOCTL command */
++#define MLB_DBG_RUNTIME _IO('S', 0x09)
++#define MLB_SET_FPS _IOW('S', 0x10, unsigned int)
++#define MLB_GET_VER _IOR('S', 0x11, unsigned long)
++#define MLB_SET_DEVADDR _IOR('S', 0x12, unsigned char)
++
++/*!
++ * set channel address for each logical channel
++ * the MSB 16bits is for tx channel, the left LSB is for rx channel
++ */
++#define MLB_CHAN_SETADDR _IOW('S', 0x13, unsigned int)
++#define MLB_CHAN_STARTUP _IO('S', 0x14)
++#define MLB_CHAN_SHUTDOWN _IO('S', 0x15)
++#define MLB_CHAN_GETEVENT _IOR('S', 0x16, unsigned long)
++
++#define MLB_SET_ISOC_BLKSIZE_188 _IO('S', 0x17)
++#define MLB_SET_ISOC_BLKSIZE_196 _IO('S', 0x18)
++#define MLB_SET_SYNC_QUAD _IOW('S', 0x19, unsigned int)
++#define MLB_IRQ_ENABLE _IO('S', 0x20)
++#define MLB_IRQ_DISABLE _IO('S', 0x21)
++
++/*!
++ * MLB event define
++ */
++enum {
++ MLB_EVT_TX_PROTO_ERR_CUR = 1 << 0,
++ MLB_EVT_TX_BRK_DETECT_CUR = 1 << 1,
++ MLB_EVT_TX_PROTO_ERR_PREV = 1 << 8,
++ MLB_EVT_TX_BRK_DETECT_PREV = 1 << 9,
++ MLB_EVT_RX_PROTO_ERR_CUR = 1 << 16,
++ MLB_EVT_RX_BRK_DETECT_CUR = 1 << 17,
++ MLB_EVT_RX_PROTO_ERR_PREV = 1 << 24,
++ MLB_EVT_RX_BRK_DETECT_PREV = 1 << 25,
++};
++
++
++#endif /* _MXC_MLB_H */
+diff -Nur linux-3.14.72.orig/include/linux/mxc_v4l2.h linux-3.14.72/include/linux/mxc_v4l2.h
+--- linux-3.14.72.orig/include/linux/mxc_v4l2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mxc_v4l2.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,27 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @file linux/mxc_v4l2.h
++ *
++ * @brief MXC V4L2 private header file
++ *
++ * @ingroup MXC V4L2
++ */
++
++#ifndef __LINUX_MXC_V4L2_H__
++#define __LINUX_MXC_V4L2_H__
++
++#include <uapi/linux/mxc_v4l2.h>
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/mxc_vpu.h linux-3.14.72/include/linux/mxc_vpu.h
+--- linux-3.14.72.orig/include/linux/mxc_vpu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/mxc_vpu.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,118 @@
++/*
++ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++
++/*!
++ * @defgroup VPU Video Processor Unit Driver
++ */
++
++/*!
++ * @file linux/mxc_vpu.h
++ *
++ * @brief VPU system initialization and file operation definition
++ *
++ * @ingroup VPU
++ */
++
++#ifndef __LINUX_MXC_VPU_H__
++#define __LINUX_MXC_VPU_H__
++
++#include <linux/fs.h>
++
++struct mxc_vpu_platform_data {
++ bool iram_enable;
++ int iram_size;
++ void (*reset) (void);
++ void (*pg) (int);
++};
++
++struct vpu_mem_desc {
++ u32 size;
++ dma_addr_t phy_addr;
++ u32 cpu_addr; /* cpu address to free the dma mem */
++ u32 virt_uaddr; /* virtual user space address */
++};
++
++#define VPU_IOC_MAGIC 'V'
++
++#define VPU_IOC_PHYMEM_ALLOC _IO(VPU_IOC_MAGIC, 0)
++#define VPU_IOC_PHYMEM_FREE _IO(VPU_IOC_MAGIC, 1)
++#define VPU_IOC_WAIT4INT _IO(VPU_IOC_MAGIC, 2)
++#define VPU_IOC_PHYMEM_DUMP _IO(VPU_IOC_MAGIC, 3)
++#define VPU_IOC_REG_DUMP _IO(VPU_IOC_MAGIC, 4)
++#define VPU_IOC_IRAM_SETTING _IO(VPU_IOC_MAGIC, 6)
++#define VPU_IOC_CLKGATE_SETTING _IO(VPU_IOC_MAGIC, 7)
++#define VPU_IOC_GET_WORK_ADDR _IO(VPU_IOC_MAGIC, 8)
++#define VPU_IOC_REQ_VSHARE_MEM _IO(VPU_IOC_MAGIC, 9)
++#define VPU_IOC_SYS_SW_RESET _IO(VPU_IOC_MAGIC, 11)
++#define VPU_IOC_GET_SHARE_MEM _IO(VPU_IOC_MAGIC, 12)
++#define VPU_IOC_QUERY_BITWORK_MEM _IO(VPU_IOC_MAGIC, 13)
++#define VPU_IOC_SET_BITWORK_MEM _IO(VPU_IOC_MAGIC, 14)
++#define VPU_IOC_PHYMEM_CHECK _IO(VPU_IOC_MAGIC, 15)
++#define VPU_IOC_LOCK_DEV _IO(VPU_IOC_MAGIC, 16)
++
++#define BIT_CODE_RUN 0x000
++#define BIT_CODE_DOWN 0x004
++#define BIT_INT_CLEAR 0x00C
++#define BIT_INT_STATUS 0x010
++#define BIT_CUR_PC 0x018
++#define BIT_INT_REASON 0x174
++
++#define MJPEG_PIC_STATUS_REG 0x3004
++#define MBC_SET_SUBBLK_EN 0x4A0
++
++#define BIT_WORK_CTRL_BUF_BASE 0x100
++#define BIT_WORK_CTRL_BUF_REG(i) (BIT_WORK_CTRL_BUF_BASE + i * 4)
++#define BIT_CODE_BUF_ADDR BIT_WORK_CTRL_BUF_REG(0)
++#define BIT_WORK_BUF_ADDR BIT_WORK_CTRL_BUF_REG(1)
++#define BIT_PARA_BUF_ADDR BIT_WORK_CTRL_BUF_REG(2)
++#define BIT_BIT_STREAM_CTRL BIT_WORK_CTRL_BUF_REG(3)
++#define BIT_FRAME_MEM_CTRL BIT_WORK_CTRL_BUF_REG(4)
++#define BIT_BIT_STREAM_PARAM BIT_WORK_CTRL_BUF_REG(5)
++
++#ifndef CONFIG_SOC_IMX6Q
++#define BIT_RESET_CTRL 0x11C
++#else
++#define BIT_RESET_CTRL 0x128
++#endif
++
++/* i could be 0, 1, 2, 3 */
++#define BIT_RD_PTR_BASE 0x120
++#define BIT_RD_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8)
++#define BIT_WR_PTR_REG(i) (BIT_RD_PTR_BASE + i * 8 + 4)
++
++/* i could be 0, 1, 2, 3 */
++#define BIT_FRM_DIS_FLG_BASE (cpu_is_mx51() ? 0x150 : 0x140)
++#define BIT_FRM_DIS_FLG_REG(i) (BIT_FRM_DIS_FLG_BASE + i * 4)
++
++#define BIT_BUSY_FLAG 0x160
++#define BIT_RUN_COMMAND 0x164
++#define BIT_INT_ENABLE 0x170
++
++#define BITVAL_PIC_RUN 8
++
++#define VPU_SLEEP_REG_VALUE 10
++#define VPU_WAKE_REG_VALUE 11
++
++int vl2cc_init(u32 vl2cc_hw_base);
++void vl2cc_enable(void);
++void vl2cc_flush(void);
++void vl2cc_disable(void);
++void vl2cc_cleanup(void);
++
++int vl2cc_init(u32 vl2cc_hw_base);
++void vl2cc_enable(void);
++void vl2cc_flush(void);
++void vl2cc_disable(void);
++void vl2cc_cleanup(void);
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/of.h linux-3.14.72/include/linux/of.h
+--- linux-3.14.72.orig/include/linux/of.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/of.h 2016-06-19 22:11:55.501127146 +0200
+@@ -251,6 +251,7 @@
+
+ extern void of_alias_scan(void * (*dt_alloc)(u64 size, u64 align));
+ extern int of_alias_get_id(struct device_node *np, const char *stem);
++extern int of_alias_max_index(const char *stem);
+
+ extern int of_machine_is_compatible(const char *compat);
+
+@@ -488,6 +489,11 @@
+ return -ENOSYS;
+ }
+
++static inline int of_alias_max_index(const char *stem)
++{
++ return -ENODEV;
++}
++
+ static inline int of_machine_is_compatible(const char *compat)
+ {
+ return 0;
+diff -Nur linux-3.14.72.orig/include/linux/of_mdio.h linux-3.14.72/include/linux/of_mdio.h
+--- linux-3.14.72.orig/include/linux/of_mdio.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/of_mdio.h 2016-06-19 22:11:55.501127146 +0200
+@@ -22,9 +22,6 @@
+ struct phy_device *of_phy_attach(struct net_device *dev,
+ struct device_node *phy_np, u32 flags,
+ phy_interface_t iface);
+-extern struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
+- void (*hndlr)(struct net_device *),
+- phy_interface_t iface);
+
+ extern struct mii_bus *of_mdio_find_bus(struct device_node *mdio_np);
+
+@@ -54,17 +51,25 @@
+ return NULL;
+ }
+
+-static inline struct phy_device *of_phy_connect_fixed_link(struct net_device *dev,
+- void (*hndlr)(struct net_device *),
+- phy_interface_t iface)
++static inline struct mii_bus *of_mdio_find_bus(struct device_node *mdio_np)
+ {
+ return NULL;
+ }
++#endif /* CONFIG_OF */
+
+-static inline struct mii_bus *of_mdio_find_bus(struct device_node *mdio_np)
++#if defined(CONFIG_OF) && defined(CONFIG_FIXED_PHY)
++extern int of_phy_register_fixed_link(struct device_node *np);
++extern bool of_phy_is_fixed_link(struct device_node *np);
++#else
++static inline int of_phy_register_fixed_link(struct device_node *np)
+ {
+- return NULL;
++ return -ENOSYS;
+ }
+-#endif /* CONFIG_OF */
++static inline bool of_phy_is_fixed_link(struct device_node *np)
++{
++ return false;
++}
++#endif
++
+
+ #endif /* __LINUX_OF_MDIO_H */
+diff -Nur linux-3.14.72.orig/include/linux/phy_fixed.h linux-3.14.72/include/linux/phy_fixed.h
+--- linux-3.14.72.orig/include/linux/phy_fixed.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/phy_fixed.h 2016-06-19 22:11:55.501127146 +0200
+@@ -9,15 +9,26 @@
+ int asym_pause;
+ };
+
+-#ifdef CONFIG_FIXED_PHY
++struct device_node;
++
++#if IS_ENABLED(CONFIG_FIXED_PHY)
+ extern int fixed_phy_add(unsigned int irq, int phy_id,
+ struct fixed_phy_status *status);
++extern int fixed_phy_register(unsigned int irq,
++ struct fixed_phy_status *status,
++ struct device_node *np);
+ #else
+ static inline int fixed_phy_add(unsigned int irq, int phy_id,
+ struct fixed_phy_status *status)
+ {
+ return -ENODEV;
+ }
++static inline int fixed_phy_register(unsigned int irq,
++ struct fixed_phy_status *status,
++ struct device_node *np)
++{
++ return -ENODEV;
++}
+ #endif /* CONFIG_FIXED_PHY */
+
+ /*
+diff -Nur linux-3.14.72.orig/include/linux/platform_data/ata-samsung_cf.h linux-3.14.72/include/linux/platform_data/ata-samsung_cf.h
+--- linux-3.14.72.orig/include/linux/platform_data/ata-samsung_cf.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/platform_data/ata-samsung_cf.h 2016-06-19 22:11:55.501127146 +0200
+@@ -30,7 +30,6 @@
+
+ /* architecture-specific IDE configuration */
+ extern void s3c64xx_ide_setup_gpio(void);
+-extern void s5pc100_ide_setup_gpio(void);
+ extern void s5pv210_ide_setup_gpio(void);
+
+ #endif /*__ASM_PLAT_ATA_H */
+diff -Nur linux-3.14.72.orig/include/linux/platform_data/dma-imx.h linux-3.14.72/include/linux/platform_data/dma-imx.h
+--- linux-3.14.72.orig/include/linux/platform_data/dma-imx.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/platform_data/dma-imx.h 2016-06-19 22:11:55.501127146 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -40,6 +40,9 @@
+ IMX_DMATYPE_ASRC, /* ASRC */
+ IMX_DMATYPE_ESAI, /* ESAI */
+ IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
++ IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
++ IMX_DMATYPE_HDMI, /* HDMI Audio */
++ IMX_DMATYPE_SAI, /* SAI Audio */
+ };
+
+ enum imx_dma_prio {
+@@ -50,6 +53,7 @@
+
+ struct imx_dma_data {
+ int dma_request; /* DMA request line */
++ int dma_request2; /* secondary DMA request line */
+ enum sdma_peripheral_type peripheral_type;
+ int priority;
+ };
+@@ -59,6 +63,11 @@
+ return !strcmp(dev_name(chan->device->dev), "ipu-core");
+ }
+
++static inline int imx_dma_is_pxp(struct dma_chan *chan)
++{
++ return strstr(dev_name(chan->device->dev), "pxp") != NULL;
++}
++
+ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
+ {
+ return !strcmp(chan->device->dev->driver->name, "imx-sdma") ||
+diff -Nur linux-3.14.72.orig/include/linux/platform_data/dma-imx-sdma.h linux-3.14.72/include/linux/platform_data/dma-imx-sdma.h
+--- linux-3.14.72.orig/include/linux/platform_data/dma-imx-sdma.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/platform_data/dma-imx-sdma.h 2016-06-19 22:11:55.501127146 +0200
+@@ -48,6 +48,10 @@
+ s32 ssish_2_mcu_addr;
+ s32 hdmi_dma_addr;
+ /* End of v2 array */
++ s32 zcanfd_2_mcu_addr;
++ s32 zqspi_2_mcu_addr;
++ s32 mcu_2_ecspi_addr;
++ /* End of v3 array */
+ };
+
+ /**
+diff -Nur linux-3.14.72.orig/include/linux/pm_domain.h linux-3.14.72/include/linux/pm_domain.h
+--- linux-3.14.72.orig/include/linux/pm_domain.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/pm_domain.h 2016-06-19 22:11:55.501127146 +0200
+@@ -35,14 +35,6 @@
+ int (*stop)(struct device *dev);
+ int (*save_state)(struct device *dev);
+ int (*restore_state)(struct device *dev);
+- int (*suspend)(struct device *dev);
+- int (*suspend_late)(struct device *dev);
+- int (*resume_early)(struct device *dev);
+- int (*resume)(struct device *dev);
+- int (*freeze)(struct device *dev);
+- int (*freeze_late)(struct device *dev);
+- int (*thaw_early)(struct device *dev);
+- int (*thaw)(struct device *dev);
+ bool (*active_wakeup)(struct device *dev);
+ };
+
+@@ -71,7 +63,6 @@
+ unsigned int suspended_count; /* System suspend device counter */
+ unsigned int prepared_count; /* Suspend counter of prepared devices */
+ bool suspend_power_off; /* Power status before system suspend */
+- bool dev_irq_safe; /* Device callbacks are IRQ-safe */
+ int (*power_off)(struct generic_pm_domain *domain);
+ s64 power_off_latency_ns;
+ int (*power_on)(struct generic_pm_domain *domain);
+@@ -108,7 +99,6 @@
+
+ struct generic_pm_domain_data {
+ struct pm_domain_data base;
+- struct gpd_dev_ops ops;
+ struct gpd_timing_data td;
+ struct notifier_block nb;
+ struct mutex lock;
+@@ -151,10 +141,6 @@
+ const char *subdomain_name);
+ extern int pm_genpd_remove_subdomain(struct generic_pm_domain *genpd,
+ struct generic_pm_domain *target);
+-extern int pm_genpd_add_callbacks(struct device *dev,
+- struct gpd_dev_ops *ops,
+- struct gpd_timing_data *td);
+-extern int __pm_genpd_remove_callbacks(struct device *dev, bool clear_td);
+ extern int pm_genpd_attach_cpuidle(struct generic_pm_domain *genpd, int state);
+ extern int pm_genpd_name_attach_cpuidle(const char *name, int state);
+ extern int pm_genpd_detach_cpuidle(struct generic_pm_domain *genpd);
+@@ -217,16 +203,6 @@
+ {
+ return -ENOSYS;
+ }
+-static inline int pm_genpd_add_callbacks(struct device *dev,
+- struct gpd_dev_ops *ops,
+- struct gpd_timing_data *td)
+-{
+- return -ENOSYS;
+-}
+-static inline int __pm_genpd_remove_callbacks(struct device *dev, bool clear_td)
+-{
+- return -ENOSYS;
+-}
+ static inline int pm_genpd_attach_cpuidle(struct generic_pm_domain *genpd, int st)
+ {
+ return -ENOSYS;
+@@ -281,33 +257,70 @@
+ return __pm_genpd_name_add_device(domain_name, dev, NULL);
+ }
+
+-static inline int pm_genpd_remove_callbacks(struct device *dev)
+-{
+- return __pm_genpd_remove_callbacks(dev, true);
+-}
+-
+ #ifdef CONFIG_PM_GENERIC_DOMAINS_RUNTIME
+-extern void genpd_queue_power_off_work(struct generic_pm_domain *genpd);
+ extern void pm_genpd_poweroff_unused(void);
+ #else
+-static inline void genpd_queue_power_off_work(struct generic_pm_domain *gpd) {}
+ static inline void pm_genpd_poweroff_unused(void) {}
+ #endif
+
+ #ifdef CONFIG_PM_GENERIC_DOMAINS_SLEEP
+-extern void pm_genpd_syscore_switch(struct device *dev, bool suspend);
++extern void pm_genpd_syscore_poweroff(struct device *dev);
++extern void pm_genpd_syscore_poweron(struct device *dev);
+ #else
+-static inline void pm_genpd_syscore_switch(struct device *dev, bool suspend) {}
++static inline void pm_genpd_syscore_poweroff(struct device *dev) {}
++static inline void pm_genpd_syscore_poweron(struct device *dev) {}
+ #endif
+
+-static inline void pm_genpd_syscore_poweroff(struct device *dev)
++/* OF PM domain providers */
++struct of_device_id;
++
++struct genpd_onecell_data {
++ struct generic_pm_domain **domains;
++ unsigned int num_domains;
++};
++
++typedef struct generic_pm_domain *(*genpd_xlate_t)(struct of_phandle_args *args,
++ void *data);
++
++#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
++int __of_genpd_add_provider(struct device_node *np, genpd_xlate_t xlate,
++ void *data);
++void of_genpd_del_provider(struct device_node *np);
++
++struct generic_pm_domain *__of_genpd_xlate_simple(
++ struct of_phandle_args *genpdspec,
++ void *data);
++struct generic_pm_domain *__of_genpd_xlate_onecell(
++ struct of_phandle_args *genpdspec,
++ void *data);
++
++int genpd_dev_pm_attach(struct device *dev);
++#else /* !CONFIG_PM_GENERIC_DOMAINS_OF */
++static inline int __of_genpd_add_provider(struct device_node *np,
++ genpd_xlate_t xlate, void *data)
++{
++ return 0;
++}
++static inline void of_genpd_del_provider(struct device_node *np) {}
++
++#define __of_genpd_xlate_simple NULL
++#define __of_genpd_xlate_onecell NULL
++
++static inline int genpd_dev_pm_attach(struct device *dev)
+ {
+- pm_genpd_syscore_switch(dev, true);
++ return -ENODEV;
+ }
++#endif /* CONFIG_PM_GENERIC_DOMAINS_OF */
+
+-static inline void pm_genpd_syscore_poweron(struct device *dev)
++static inline int of_genpd_add_provider_simple(struct device_node *np,
++ struct generic_pm_domain *genpd)
++{
++ return __of_genpd_add_provider(np, __of_genpd_xlate_simple, genpd);
++}
++static inline int of_genpd_add_provider_onecell(struct device_node *np,
++ struct genpd_onecell_data *data)
+ {
+- pm_genpd_syscore_switch(dev, false);
++ return __of_genpd_add_provider(np, __of_genpd_xlate_onecell, data);
+ }
+
+ #endif /* _LINUX_PM_DOMAIN_H */
+diff -Nur linux-3.14.72.orig/include/linux/pm.h linux-3.14.72/include/linux/pm.h
+--- linux-3.14.72.orig/include/linux/pm.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/pm.h 2016-06-19 22:11:55.501127146 +0200
+@@ -596,8 +596,20 @@
+ */
+ struct dev_pm_domain {
+ struct dev_pm_ops ops;
++ void (*detach)(struct device *dev, bool power_off);
+ };
+
++#ifdef CONFIG_PM
++extern int dev_pm_domain_attach(struct device *dev, bool power_on);
++extern void dev_pm_domain_detach(struct device *dev, bool power_off);
++#else
++static inline int dev_pm_domain_attach(struct device *dev, bool power_on)
++{
++ return -ENODEV;
++}
++static inline void dev_pm_domain_detach(struct device *dev, bool power_off) {}
++#endif
++
+ /*
+ * The PM_EVENT_ messages are also used by drivers implementing the legacy
+ * suspend framework, based on the ->suspend() and ->resume() callbacks common
+diff -Nur linux-3.14.72.orig/include/linux/pmic_status.h linux-3.14.72/include/linux/pmic_status.h
+--- linux-3.14.72.orig/include/linux/pmic_status.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/pmic_status.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,82 @@
++/*
++ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU Lesser General
++ * Public License. You may obtain a copy of the GNU Lesser General
++ * Public License Version 2.1 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/lgpl-license.html
++ * http://www.gnu.org/copyleft/lgpl.html
++ */
++#ifndef __ASM_ARCH_MXC_PMIC_STATUS_H__
++#define __ASM_ARCH_MXC_PMIC_STATUS_H__
++#include <asm-generic/errno-base.h>
++#ifdef __KERNEL__
++#include <asm/uaccess.h> /* copy_{from,to}_user() */
++#endif
++/*!
++ * @file arch-mxc/pmic_status.h
++ * @brief PMIC APIs return code definition.
++ *
++ * @ingroup PMIC_CORE
++ */
++
++/*!
++ * @enum PMIC_STATUS
++ * @brief Define return values for all PMIC APIs.
++ *
++ * These return values are used by all of the PMIC APIs.
++ *
++ * @ingroup PMIC
++ */
++typedef enum {
++ PMIC_SUCCESS = 0, /*!< The requested operation was successfully
++ completed. */
++ PMIC_ERROR = -1, /*!< The requested operation could not be completed
++ due to an error. */
++ PMIC_PARAMETER_ERROR = -2, /*!< The requested operation failed because
++ one or more of the parameters was
++ invalid. */
++ PMIC_NOT_SUPPORTED = -3, /*!< The requested operation could not be
++ completed because the PMIC hardware
++ does not support it. */
++ PMIC_SYSTEM_ERROR_EINTR = -EINTR,
++
++ PMIC_MALLOC_ERROR = -5, /*!< Error in malloc function */
++ PMIC_UNSUBSCRIBE_ERROR = -6, /*!< Error in un-subscribe event */
++ PMIC_EVENT_NOT_SUBSCRIBED = -7, /*!< Event occur and not subscribed */
++ PMIC_EVENT_CALL_BACK = -8, /*!< Error - bad call back */
++ PMIC_CLIENT_NBOVERFLOW = -9, /*!< The requested operation could not be
++ completed because there are too many
++ PMIC client requests */
++} PMIC_STATUS;
++
++/*
++ * Bitfield macros that use rely on bitfield width/shift information.
++ */
++#define BITFMASK(field) (((1U << (field ## _WID)) - 1) << (field ## _LSH))
++#define BITFVAL(field, val) ((val) << (field ## _LSH))
++#define BITFEXT(var, bit) ((var & BITFMASK(bit)) >> (bit ## _LSH))
++
++/*
++ * Macros implementing error handling
++ */
++#define CHECK_ERROR(a) \
++do { \
++ int ret = (a); \
++ if (ret != PMIC_SUCCESS) \
++ return ret; \
++} while (0)
++
++#define CHECK_ERROR_KFREE(func, freeptrs) \
++do { \
++ int ret = (func); \
++ if (ret != PMIC_SUCCESS) { \
++ freeptrs; \
++ return ret; \
++ } \
++} while (0);
++
++#endif /* __ASM_ARCH_MXC_PMIC_STATUS_H__ */
+diff -Nur linux-3.14.72.orig/include/linux/power/imx6_usb_charger.h linux-3.14.72/include/linux/power/imx6_usb_charger.h
+--- linux-3.14.72.orig/include/linux/power/imx6_usb_charger.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/power/imx6_usb_charger.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,80 @@
++/*
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#ifndef __IMXUSB6_CHARGER_H
++#define __IMXUSB6_CHARGER_H
++
++#include <linux/power_supply.h>
++enum battery_charging_spec {
++ BATTERY_CHARGING_SPEC_NONE = 0,
++ BATTERY_CHARGING_SPEC_UNKNOWN,
++ BATTERY_CHARGING_SPEC_1_0,
++ BATTERY_CHARGING_SPEC_1_1,
++ BATTERY_CHARGING_SPEC_1_2,
++};
++
++struct usb_charger {
++ /* The anatop regmap */
++ struct regmap *anatop;
++ /* USB controller */
++ struct device *dev;
++ struct power_supply psy;
++ struct mutex lock;
++
++ /* Compliant with Battery Charging Specification version (if any) */
++ enum battery_charging_spec bc;
++
++ /* properties */
++ unsigned present:1;
++ unsigned online:1;
++ unsigned max_current;
++ int (*connect)(struct usb_charger *charger);
++ int (*disconnect)(struct usb_charger *charger);
++ int (*set_power)(struct usb_charger *charger, unsigned mA);
++
++ int (*detect)(struct usb_charger *charger);
++};
++
++#ifdef CONFIG_IMX6_USB_CHARGER
++extern void imx6_usb_remove_charger(struct usb_charger *charger);
++extern int imx6_usb_create_charger(struct usb_charger *charger,
++ const char *name);
++extern int imx6_usb_vbus_disconnect(struct usb_charger *charger);
++extern int imx6_usb_vbus_connect(struct usb_charger *charger);
++extern int imx6_usb_charger_detect_post(struct usb_charger *charger);
++#else
++void imx6_usb_remove_charger(struct usb_charger *charger)
++{
++
++}
++
++int imx6_usb_create_charger(struct usb_charger *charger,
++ const char *name)
++{
++ return -ENODEV;
++}
++
++int imx6_usb_vbus_disconnect(struct usb_charger *charger)
++{
++ return -ENODEV;
++}
++
++int imx6_usb_vbus_connect(struct usb_charger *charger)
++{
++ return -ENODEV;
++}
++int imx6_usb_charger_detect_post(struct usb_charger *charger)
++{
++ return -ENODEV;
++}
++#endif
++
++#endif /* __IMXUSB6_CHARGER_H */
+diff -Nur linux-3.14.72.orig/include/linux/power/sabresd_battery.h linux-3.14.72/include/linux/power/sabresd_battery.h
+--- linux-3.14.72.orig/include/linux/power/sabresd_battery.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/power/sabresd_battery.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,65 @@
++/*
++ * sabresd_battery.h - Maxim 8903 USB/Adapter Charger Driver
++ *
++ * Copyright (C) 2011 Samsung Electronics
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ * Based on max8903_charger.h
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#ifndef __MAX8903_SABRESD_H__
++#define __MAX8903_SABRESD_H__
++
++struct max8903_pdata {
++ /*
++ * GPIOs
++ * cen, chg, flt, and usus are optional.
++ * dok, dcm, and uok are not optional depending on the status of
++ * dc_valid and usb_valid.
++ */
++ int cen; /* Charger Enable input */
++ int dok; /* DC(Adapter) Power OK output */
++ int uok; /* USB Power OK output */
++ int chg; /* Charger status output */
++ int flt; /* Fault output */
++ int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */
++ int usus; /* USB Suspend Input (1: suspended) */
++ int feature_flag;/* battery capacity feature(0:enable, 1:disable) */
++
++ /*
++ * DCM wired to Logic High Set this true when DCM pin connect to
++ * Logic high.
++ */
++ bool dcm_always_high;
++
++ /*
++ * DC(Adapter/TA) is wired
++ * When dc_valid is true,
++ * dok and dcm should be valid.
++ *
++ * At least one of dc_valid or usb_valid should be true.
++ */
++ bool dc_valid;
++ /*
++ * USB is wired
++ * When usb_valid is true,
++ * uok should be valid.
++ */
++ bool usb_valid;
++};
++
++#endif /* __SABRESD_BATTERY_H__ */
+diff -Nur linux-3.14.72.orig/include/linux/ptp_clock_kernel.h linux-3.14.72/include/linux/ptp_clock_kernel.h
+--- linux-3.14.72.orig/include/linux/ptp_clock_kernel.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/ptp_clock_kernel.h 2016-06-19 22:11:55.501127146 +0200
+@@ -49,7 +49,11 @@
+ * @n_alarm: The number of programmable alarms.
+ * @n_ext_ts: The number of external time stamp channels.
+ * @n_per_out: The number of programmable periodic signals.
++ * @n_pins: The number of programmable pins.
+ * @pps: Indicates whether the clock supports a PPS callback.
++ * @pin_config: Array of length 'n_pins'. If the number of
++ * programmable pins is nonzero, then drivers must
++ * allocate and initialize this array.
+ *
+ * clock operations
+ *
+@@ -70,6 +74,18 @@
+ * parameter request: Desired resource to enable or disable.
+ * parameter on: Caller passes one to enable or zero to disable.
+ *
++ * @verify: Confirm that a pin can perform a given function. The PTP
++ * Hardware Clock subsystem maintains the 'pin_config'
++ * array on behalf of the drivers, but the PHC subsystem
++ * assumes that every pin can perform every function. This
++ * hook gives drivers a way of telling the core about
++ * limitations on specific pins. This function must return
++ * zero if the function can be assigned to this pin, and
++ * nonzero otherwise.
++ * parameter pin: index of the pin in question.
++ * parameter func: the desired function to use.
++ * parameter chan: the function channel index to use.
++ *
+ * Drivers should embed their ptp_clock_info within a private
+ * structure, obtaining a reference to it using container_of().
+ *
+@@ -83,13 +99,17 @@
+ int n_alarm;
+ int n_ext_ts;
+ int n_per_out;
++ int n_pins;
+ int pps;
++ struct ptp_pin_desc *pin_config;
+ int (*adjfreq)(struct ptp_clock_info *ptp, s32 delta);
+ int (*adjtime)(struct ptp_clock_info *ptp, s64 delta);
+ int (*gettime)(struct ptp_clock_info *ptp, struct timespec *ts);
+ int (*settime)(struct ptp_clock_info *ptp, const struct timespec *ts);
+ int (*enable)(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *request, int on);
++ int (*verify)(struct ptp_clock_info *ptp, unsigned int pin,
++ enum ptp_pin_function func, unsigned int chan);
+ };
+
+ struct ptp_clock;
+@@ -156,4 +176,17 @@
+
+ extern int ptp_clock_index(struct ptp_clock *ptp);
+
++/**
++ * ptp_find_pin() - obtain the pin index of a given auxiliary function
++ *
++ * @ptp: The clock obtained from ptp_clock_register().
++ * @func: One of the ptp_pin_function enumerated values.
++ * @chan: The particular functional channel to find.
++ * Return: Pin index in the range of zero to ptp_clock_caps.n_pins - 1,
++ * or -1 if the auxiliary function cannot be found.
++ */
++
++int ptp_find_pin(struct ptp_clock *ptp,
++ enum ptp_pin_function func, unsigned int chan);
++
+ #endif
+diff -Nur linux-3.14.72.orig/include/linux/pxp_device.h linux-3.14.72/include/linux/pxp_device.h
+--- linux-3.14.72.orig/include/linux/pxp_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/pxp_device.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,68 @@
++/*
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _PXP_DEVICE
++#define _PXP_DEVICE
++
++#include <linux/idr.h>
++#include <linux/hash.h>
++#include <uapi/linux/pxp_device.h>
++
++struct pxp_irq_info {
++ wait_queue_head_t waitq;
++ atomic_t irq_pending;
++ int hist_status;
++};
++
++struct pxp_buffer_hash {
++ struct hlist_head *hash_table;
++ u32 order;
++ spinlock_t hash_lock;
++};
++
++struct pxp_buf_obj {
++ uint32_t handle;
++
++ uint32_t size;
++ uint32_t mem_type;
++
++ unsigned long offset;
++ void *virtual;
++
++ struct hlist_node item;
++};
++
++struct pxp_chan_obj {
++ uint32_t handle;
++ struct dma_chan *chan;
++};
++
++/* File private data */
++struct pxp_file {
++ struct file *filp;
++
++ /* record allocated dma buffer */
++ struct idr buffer_idr;
++ spinlock_t buffer_lock;
++
++ /* record allocated dma channel */
++ struct idr channel_idr;
++ spinlock_t channel_lock;
++};
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/pxp_dma.h linux-3.14.72/include/linux/pxp_dma.h
+--- linux-3.14.72.orig/include/linux/pxp_dma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/linux/pxp_dma.h 2016-06-19 22:11:55.501127146 +0200
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _PXP_DMA
++#define _PXP_DMA
++
++#include <uapi/linux/pxp_dma.h>
++
++struct pxp_tx_desc {
++ struct dma_async_tx_descriptor txd;
++ struct list_head tx_list;
++ struct list_head list;
++ int len;
++ union {
++ struct pxp_layer_param s0_param;
++ struct pxp_layer_param out_param;
++ struct pxp_layer_param ol_param;
++ } layer_param;
++ struct pxp_proc_data proc_data;
++
++ u32 hist_status; /* Histogram output status */
++
++ struct pxp_tx_desc *next;
++};
++
++struct pxp_channel {
++ struct dma_chan dma_chan;
++ dma_cookie_t completed; /* last completed cookie */
++ enum pxp_channel_status status;
++ void *client; /* Only one client per channel */
++ unsigned int n_tx_desc;
++ struct pxp_tx_desc *desc; /* allocated tx-descriptors */
++ struct list_head queue; /* queued tx-descriptors */
++ struct list_head list; /* track queued channel number */
++ spinlock_t lock; /* protects sg[0,1], queue,
++ * status, cookie, free_list
++ */
++ int active_buffer;
++ unsigned int eof_irq;
++ char eof_name[16]; /* EOF IRQ name for request_irq() */
++};
++
++#define to_tx_desc(tx) container_of(tx, struct pxp_tx_desc, txd)
++#define to_pxp_channel(d) container_of(d, struct pxp_channel, dma_chan)
++
++void pxp_txd_ack(struct dma_async_tx_descriptor *txd,
++ struct pxp_channel *pxp_chan);
++
++#ifdef CONFIG_MXC_PXP_CLIENT_DEVICE
++int register_pxp_device(void);
++void unregister_pxp_device(void);
++#else
++int register_pxp_device(void) { return 0; }
++void unregister_pxp_device(void) {}
++#endif
++
++#endif
+diff -Nur linux-3.14.72.orig/include/linux/regmap.h linux-3.14.72/include/linux/regmap.h
+--- linux-3.14.72.orig/include/linux/regmap.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/regmap.h 2016-06-19 22:11:55.501127146 +0200
+@@ -27,6 +27,7 @@
+ struct regmap;
+ struct regmap_range_cfg;
+ struct regmap_field;
++struct snd_ac97;
+
+ /* An enum of all the supported cache types */
+ enum regcache_type {
+@@ -272,6 +273,12 @@
+ typedef int (*regmap_hw_read)(void *context,
+ const void *reg_buf, size_t reg_size,
+ void *val_buf, size_t val_size);
++
++typedef int (*regmap_hw_reg_read)(void *context, unsigned int reg,
++ unsigned int *val);
++typedef int (*regmap_hw_reg_write)(void *context, unsigned int reg,
++ unsigned int val);
++
+ typedef struct regmap_async *(*regmap_hw_async_alloc)(void);
+ typedef void (*regmap_hw_free_context)(void *context);
+
+@@ -305,7 +312,9 @@
+ regmap_hw_write write;
+ regmap_hw_gather_write gather_write;
+ regmap_hw_async_write async_write;
++ regmap_hw_reg_write reg_write;
+ regmap_hw_read read;
++ regmap_hw_reg_read reg_read;
+ regmap_hw_free_context free_context;
+ regmap_hw_async_alloc async_alloc;
+ u8 read_flag_mask;
+@@ -326,6 +335,8 @@
+ struct regmap *regmap_init_mmio_clk(struct device *dev, const char *clk_id,
+ void __iomem *regs,
+ const struct regmap_config *config);
++struct regmap *regmap_init_ac97(struct snd_ac97 *ac97,
++ const struct regmap_config *config);
+
+ struct regmap *devm_regmap_init(struct device *dev,
+ const struct regmap_bus *bus,
+@@ -340,6 +351,10 @@
+ struct regmap *devm_regmap_init_mmio_clk(struct device *dev, const char *clk_id,
+ void __iomem *regs,
+ const struct regmap_config *config);
++struct regmap *devm_regmap_init_ac97(struct snd_ac97 *ac97,
++ const struct regmap_config *config);
++
++bool regmap_ac97_default_volatile(struct device *dev, unsigned int reg);
+
+ /**
+ * regmap_init_mmio(): Initialise register map
+diff -Nur linux-3.14.72.orig/include/linux/regulator/consumer.h linux-3.14.72/include/linux/regulator/consumer.h
+--- linux-3.14.72.orig/include/linux/regulator/consumer.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/regulator/consumer.h 2016-06-19 22:11:55.501127146 +0200
+@@ -105,6 +105,8 @@
+ #define REGULATOR_EVENT_FORCE_DISABLE 0x20
+ #define REGULATOR_EVENT_VOLTAGE_CHANGE 0x40
+ #define REGULATOR_EVENT_DISABLE 0x80
++#define REGULATOR_EVENT_PRE_DISABLE 0x100
++#define REGULATOR_EVENT_PRE_ENABLE 0x200
+
+ struct regulator;
+
+diff -Nur linux-3.14.72.orig/include/linux/regulator/pfuze100.h linux-3.14.72/include/linux/regulator/pfuze100.h
+--- linux-3.14.72.orig/include/linux/regulator/pfuze100.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/regulator/pfuze100.h 2016-06-19 22:11:55.501127146 +0200
+@@ -35,6 +35,20 @@
+ #define PFUZE100_VGEN6 14
+ #define PFUZE100_MAX_REGULATOR 15
+
++#define PFUZE200_SW1AB 0
++#define PFUZE200_SW2 1
++#define PFUZE200_SW3A 2
++#define PFUZE200_SW3B 3
++#define PFUZE200_SWBST 4
++#define PFUZE200_VSNVS 5
++#define PFUZE200_VREFDDR 6
++#define PFUZE200_VGEN1 7
++#define PFUZE200_VGEN2 8
++#define PFUZE200_VGEN3 9
++#define PFUZE200_VGEN4 10
++#define PFUZE200_VGEN5 11
++#define PFUZE200_VGEN6 12
++
+ struct regulator_init_data;
+
+ struct pfuze_regulator_platform_data {
+diff -Nur linux-3.14.72.orig/include/linux/reset.h linux-3.14.72/include/linux/reset.h
+--- linux-3.14.72.orig/include/linux/reset.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/reset.h 2016-06-19 22:11:55.501127146 +0200
+@@ -12,6 +12,13 @@
+ void reset_control_put(struct reset_control *rstc);
+ struct reset_control *devm_reset_control_get(struct device *dev, const char *id);
+
++#ifdef CONFIG_RESET_CONTROLLER
+ int device_reset(struct device *dev);
++#else
++static inline int device_reset(struct device *dev)
++{
++ return 0;
++}
++#endif /* CONFIG_RESET_CONTROLLER */
+
+ #endif
+diff -Nur linux-3.14.72.orig/include/linux/spi/spi.h linux-3.14.72/include/linux/spi/spi.h
+--- linux-3.14.72.orig/include/linux/spi/spi.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/spi/spi.h 2016-06-19 22:11:55.501127146 +0200
+@@ -24,6 +24,9 @@
+ #include <linux/slab.h>
+ #include <linux/kthread.h>
+ #include <linux/completion.h>
++#include <linux/scatterlist.h>
++
++struct dma_chan;
+
+ /*
+ * INTERFACES between SPI master-side drivers and SPI infrastructure.
+@@ -266,6 +269,7 @@
+ * @auto_runtime_pm: the core should ensure a runtime PM reference is held
+ * while the hardware is prepared, using the parent
+ * device for the spidev
++ * @max_dma_len: Maximum length of a DMA transfer for the device.
+ * @prepare_transfer_hardware: a message will soon arrive from the queue
+ * so the subsystem requests the driver to prepare the transfer hardware
+ * by issuing this call
+@@ -348,6 +352,8 @@
+ #define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */
+ #define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */
+ #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */
++#define SPI_MASTER_MUST_RX BIT(3) /* requires rx */
++#define SPI_MASTER_MUST_TX BIT(4) /* requires tx */
+
+ /* lock and mutex for SPI bus locking */
+ spinlock_t bus_lock_spinlock;
+@@ -390,6 +396,17 @@
+ void (*cleanup)(struct spi_device *spi);
+
+ /*
++ * Used to enable core support for DMA handling, if can_dma()
++ * exists and returns true then the transfer will be mapped
++ * prior to transfer_one() being called. The driver should
++ * not modify or store xfer and dma_tx and dma_rx must be set
++ * while the device is prepared.
++ */
++ bool (*can_dma)(struct spi_master *master,
++ struct spi_device *spi,
++ struct spi_transfer *xfer);
++
++ /*
+ * These hooks are for drivers that want to use the generic
+ * master transfer queueing mechanism. If these are used, the
+ * transfer() function above must NOT be specified by the driver.
+@@ -407,7 +424,9 @@
+ bool rt;
+ bool auto_runtime_pm;
+ bool cur_msg_prepared;
++ bool cur_msg_mapped;
+ struct completion xfer_completion;
++ size_t max_dma_len;
+
+ int (*prepare_transfer_hardware)(struct spi_master *master);
+ int (*transfer_one_message)(struct spi_master *master,
+@@ -428,6 +447,14 @@
+
+ /* gpio chip select */
+ int *cs_gpios;
++
++ /* DMA channels for use with core dmaengine helpers */
++ struct dma_chan *dma_tx;
++ struct dma_chan *dma_rx;
++
++ /* dummy data for full duplex devices */
++ void *dummy_rx;
++ void *dummy_tx;
+ };
+
+ static inline void *spi_master_get_devdata(struct spi_master *master)
+@@ -512,6 +539,8 @@
+ * (optionally) changing the chipselect status, then starting
+ * the next transfer or completing this @spi_message.
+ * @transfer_list: transfers are sequenced through @spi_message.transfers
++ * @tx_sg: Scatterlist for transmit, currently not for client use
++ * @rx_sg: Scatterlist for receive, currently not for client use
+ *
+ * SPI transfers always write the same number of bytes as they read.
+ * Protocol drivers should always provide @rx_buf and/or @tx_buf.
+@@ -579,6 +608,8 @@
+
+ dma_addr_t tx_dma;
+ dma_addr_t rx_dma;
++ struct sg_table tx_sg;
++ struct sg_table rx_sg;
+
+ unsigned cs_change:1;
+ unsigned tx_nbits:3;
+diff -Nur linux-3.14.72.orig/include/linux/usb/chipidea.h linux-3.14.72/include/linux/usb/chipidea.h
+--- linux-3.14.72.orig/include/linux/usb/chipidea.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb/chipidea.h 2016-06-19 22:11:55.501127146 +0200
+@@ -13,23 +13,42 @@
+ /* offset of the capability registers */
+ uintptr_t capoffset;
+ unsigned power_budget;
+- struct usb_phy *phy;
++ struct phy *phy;
++ /* old usb_phy interface */
++ struct usb_phy *usb_phy;
+ enum usb_phy_interface phy_mode;
+ unsigned long flags;
+ #define CI_HDRC_REGS_SHARED BIT(0)
+-#define CI_HDRC_REQUIRE_TRANSCEIVER BIT(1)
+-#define CI_HDRC_DISABLE_STREAMING BIT(3)
++#define CI_HDRC_SUPPORTS_RUNTIME_PM BIT(2)
+ /*
+ * Only set it when DCCPARAMS.DC==1 and DCCPARAMS.HC==1,
+ * but otg is not supported (no register otgsc).
+ */
+ #define CI_HDRC_DUAL_ROLE_NOT_OTG BIT(4)
+ #define CI_HDRC_IMX28_WRITE_FIX BIT(5)
++#define CI_HDRC_FORCE_FULLSPEED BIT(6)
++#define CI_HDRC_IMX_EHCI_QUIRK BIT(7)
++#define CI_HDRC_IMX_IS_HSIC BIT(8)
++#define CI_HDRC_DISABLE_DEVICE_STREAMING BIT(9)
++#define CI_HDRC_DISABLE_HOST_STREAMING BIT(10)
++#define CI_HDRC_DISABLE_STREAMING (CI_HDRC_DISABLE_DEVICE_STREAMING | \
++ CI_HDRC_DISABLE_HOST_STREAMING)
++#define CI_HDRC_OVERRIDE_AHB_BURST BIT(11)
++#define CI_HDRC_OVERRIDE_BURST_LENGTH BIT(12)
++#define CI_HDRC_IMX_VBUS_EARLY_ON BIT(13)
+ enum usb_dr_mode dr_mode;
+ #define CI_HDRC_CONTROLLER_RESET_EVENT 0
+ #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
+- void (*notify_event) (struct ci_hdrc *ci, unsigned event);
++#define CI_HDRC_CONTROLLER_VBUS_EVENT 2
++#define CI_HDRC_NOTIFY_RET_DEFER_EVENT 3
++#define CI_HDRC_CONTROLLER_CHARGER_POST_EVENT 4
++#define CI_HDRC_IMX_HSIC_ACTIVE_EVENT 5
++#define CI_HDRC_IMX_HSIC_SUSPEND_EVENT 6
++ int (*notify_event)(struct ci_hdrc *ci, unsigned event);
+ struct regulator *reg_vbus;
++ bool tpl_support;
++ u32 ahbburst_config;
++ u32 burst_length;
+ };
+
+ /* Default offset of capability registers */
+@@ -42,4 +61,6 @@
+ /* Remove ci hdrc device */
+ void ci_hdrc_remove_device(struct platform_device *pdev);
+
++/* Get current available role */
++enum usb_dr_mode ci_hdrc_query_available_role(struct platform_device *pdev);
+ #endif
+diff -Nur linux-3.14.72.orig/include/linux/usb/gadget.h linux-3.14.72/include/linux/usb/gadget.h
+--- linux-3.14.72.orig/include/linux/usb/gadget.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb/gadget.h 2016-06-19 22:11:55.501127146 +0200
+@@ -562,6 +562,7 @@
+ unsigned b_hnp_enable:1;
+ unsigned a_hnp_support:1;
+ unsigned a_alt_hnp_support:1;
++ unsigned host_request_flag:1;
+ unsigned quirk_ep_out_aligned_size:1;
+ };
+ #define work_to_gadget(w) (container_of((w), struct usb_gadget, work))
+diff -Nur linux-3.14.72.orig/include/linux/usb/hcd.h linux-3.14.72/include/linux/usb/hcd.h
+--- linux-3.14.72.orig/include/linux/usb/hcd.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb/hcd.h 2016-06-19 22:11:55.505126884 +0200
+@@ -106,7 +106,8 @@
+ * OTG and some Host controllers need software interaction with phys;
+ * other external phys should be software-transparent
+ */
+- struct usb_phy *phy;
++ struct usb_phy *usb_phy;
++ struct phy *phy;
+
+ /* Flags that need to be manipulated atomically because they can
+ * change while the host controller is running. Always use
+@@ -143,6 +144,7 @@
+ unsigned authorized_default:1;
+ unsigned has_tt:1; /* Integrated TT in root hub */
+ unsigned amd_resume_bug:1; /* AMD remote wakeup quirk */
++ unsigned tpl_support:1; /* OTG & EH TPL support */
+
+ unsigned int irq; /* irq allocated */
+ void __iomem *regs; /* device memory/io */
+@@ -376,6 +378,9 @@
+ int (*disable_usb3_lpm_timeout)(struct usb_hcd *,
+ struct usb_device *, enum usb3_link_state state);
+ int (*find_raw_port_number)(struct usb_hcd *, int);
++ /* Call for power on/off the port if necessary */
++ int (*port_power)(struct usb_hcd *hcd, int portnum, bool enable);
++
+ };
+
+ static inline int hcd_giveback_urb_in_bh(struct usb_hcd *hcd)
+diff -Nur linux-3.14.72.orig/include/linux/usb/of.h linux-3.14.72/include/linux/usb/of.h
+--- linux-3.14.72.orig/include/linux/usb/of.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb/of.h 2016-06-19 22:11:55.505126884 +0200
+@@ -14,6 +14,7 @@
+ #if IS_ENABLED(CONFIG_OF)
+ enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
+ enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np);
++bool of_usb_host_tpl_support(struct device_node *np);
+ #else
+ static inline enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
+ {
+@@ -25,6 +26,10 @@
+ {
+ return USB_SPEED_UNKNOWN;
+ }
++static inline bool of_usb_host_tpl_support(struct device_node *np)
++{
++ return false;
++}
+ #endif
+
+ #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_USB_SUPPORT)
+diff -Nur linux-3.14.72.orig/include/linux/usb/otg-fsm.h linux-3.14.72/include/linux/usb/otg-fsm.h
+--- linux-3.14.72.orig/include/linux/usb/otg-fsm.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb/otg-fsm.h 2016-06-19 22:11:55.505126884 +0200
+@@ -1,4 +1,4 @@
+-/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
++/* Copyright (C) 2007-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+@@ -40,6 +40,14 @@
+ #define PROTO_HOST (1)
+ #define PROTO_GADGET (2)
+
++#define OTG_STS_SELECTOR 0xF000 /* OTG status selector, according to
++ * OTG and EH 2.0 Charpter 6.2.3
++ * Table:6-4
++ */
++#define HOST_REQUEST_FLAG 1 /* Host request flag, according to
++ * OTG and EH 2.0 Charpter 6.2.3
++ * Table:6-5
++ */
+ enum otg_fsm_timer {
+ /* Standard OTG timers */
+ A_WAIT_VRISE,
+@@ -53,6 +61,8 @@
+ B_SE0_SRP,
+ B_SRP_FAIL,
+ A_WAIT_ENUM,
++ A_DP_END,
++ HNP_POLLING,
+
+ NUM_OTG_FSM_TIMERS,
+ };
+@@ -239,6 +249,7 @@
+ return fsm->ops->start_gadget(fsm, on);
+ }
+
++int otg_hnp_polling(struct otg_fsm *fsm);
+ int otg_statemachine(struct otg_fsm *fsm);
+
+ #endif /* __LINUX_USB_OTG_FSM_H */
+diff -Nur linux-3.14.72.orig/include/linux/usb/otg.h linux-3.14.72/include/linux/usb/otg.h
+--- linux-3.14.72.orig/include/linux/usb/otg.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb/otg.h 2016-06-19 22:11:55.505126884 +0200
+@@ -9,15 +9,20 @@
+ #ifndef __LINUX_USB_OTG_H
+ #define __LINUX_USB_OTG_H
+
++#include <linux/phy/phy.h>
+ #include <linux/usb/phy.h>
+
+ struct usb_otg {
+ u8 default_a;
+
+- struct usb_phy *phy;
++ struct phy *phy;
++ /* old usb_phy interface */
++ struct usb_phy *usb_phy;
+ struct usb_bus *host;
+ struct usb_gadget *gadget;
+
++ enum usb_otg_state state;
++
+ /* bind/unbind the host controller */
+ int (*set_host)(struct usb_otg *otg, struct usb_bus *host);
+
+diff -Nur linux-3.14.72.orig/include/linux/usb/phy.h linux-3.14.72/include/linux/usb/phy.h
+--- linux-3.14.72.orig/include/linux/usb/phy.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb/phy.h 2016-06-19 22:11:55.505126884 +0200
+@@ -77,7 +77,6 @@
+ unsigned int flags;
+
+ enum usb_phy_type type;
+- enum usb_otg_state state;
+ enum usb_phy_events last_event;
+
+ struct usb_otg *otg;
+@@ -111,11 +110,23 @@
+ int (*set_suspend)(struct usb_phy *x,
+ int suspend);
+
++ /*
++ * Set wakeup enable for PHY, in that case, the PHY can be
++ * woken up from suspend status due to external events,
++ * like vbus change, dp/dm change and id.
++ */
++ int (*set_wakeup)(struct usb_phy *x, bool enabled);
++
+ /* notify phy connect status change */
+ int (*notify_connect)(struct usb_phy *x,
+ enum usb_device_speed speed);
+ int (*notify_disconnect)(struct usb_phy *x,
+ enum usb_device_speed speed);
++ int (*notify_suspend)(struct usb_phy *x,
++ enum usb_device_speed speed);
++ int (*notify_resume)(struct usb_phy *x,
++ enum usb_device_speed speed);
++
+ };
+
+ /**
+@@ -265,6 +276,15 @@
+ }
+
+ static inline int
++usb_phy_set_wakeup(struct usb_phy *x, bool enabled)
++{
++ if (x && x->set_wakeup)
++ return x->set_wakeup(x, enabled);
++ else
++ return 0;
++}
++
++static inline int
+ usb_phy_notify_connect(struct usb_phy *x, enum usb_device_speed speed)
+ {
+ if (x && x->notify_connect)
+@@ -281,6 +301,24 @@
+ else
+ return 0;
+ }
++
++static inline int usb_phy_notify_suspend
++ (struct usb_phy *x, enum usb_device_speed speed)
++{
++ if (x && x->notify_suspend)
++ return x->notify_suspend(x, speed);
++ else
++ return 0;
++}
++
++static inline int usb_phy_notify_resume
++ (struct usb_phy *x, enum usb_device_speed speed)
++{
++ if (x && x->notify_resume)
++ return x->notify_resume(x, speed);
++ else
++ return 0;
++}
+
+ /* notifiers */
+ static inline int
+diff -Nur linux-3.14.72.orig/include/linux/usb.h linux-3.14.72/include/linux/usb.h
+--- linux-3.14.72.orig/include/linux/usb.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/linux/usb.h 2016-06-19 22:11:55.505126884 +0200
+@@ -355,6 +355,7 @@
+ * Does the host controller use PIO
+ * for control transfers?
+ */
++ struct otg_fsm *otg_fsm; /* usb otg finite state machine */
+ u8 otg_port; /* 0, or number of OTG/HNP port */
+ unsigned is_b_host:1; /* true during some HNP roleswitches */
+ unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
+diff -Nur linux-3.14.72.orig/include/media/tc358743.h linux-3.14.72/include/media/tc358743.h
+--- linux-3.14.72.orig/include/media/tc358743.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/media/tc358743.h 2016-06-19 22:11:55.505126884 +0200
+@@ -0,0 +1,89 @@
++/*
++ * tc358743 - Toshiba HDMI to CSI-2 bridge
++ *
++ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. All rights
++ * reserved.
++ *
++ * This program is free software; you may redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; version 2 of the License.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
++ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
++ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
++ * SOFTWARE.
++ *
++ */
++
++/*
++ * References (c = chapter, p = page):
++ * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
++ * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
++ */
++
++#ifndef _TC358743_
++#define _TC358743_
++
++enum tc358743_ddc5v_delays {
++ DDC5V_DELAY_0MS,
++ DDC5V_DELAY_50MS,
++ DDC5V_DELAY_100MS,
++ DDC5V_DELAY_200MS,
++};
++
++struct tc358743_platform_data {
++ u32 refclk_hz; /* System clock connected to REFCLK (pin H5) */
++ enum tc358743_ddc5v_delays ddc5v_delay; /* DDC +5V debounce delay */
++ bool enable_hdcp;
++ /*
++ * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO
++ * level to somewhere in the middle (eg. 200), so it can cover speed
++ * mismatches in input and output ports.
++ */
++ u16 fifo_level;
++ u16 pll_prd; /* PLLCTL0 */
++ u16 pll_fbd; /*PLLCTL0 */
++
++ /* CSI
++ * Calculate CSI parameters with REF_02 for the highest resolution your
++ * CSI interface can handle. The driver will adjust the number of CSI
++ * lanes in use according to the pixel clock.
++ */
++ u32 bps_pr_lane;
++ u32 lineinitcnt;
++ u32 lptxtimecnt;
++ u32 tclk_headercnt;
++ u32 tclk_trailcnt;
++ u32 ths_headercnt;
++ u32 twakeup;
++ u32 tclk_postcnt;
++ u32 ths_trailcnt;
++ u32 hstxvregcnt;
++
++ /* HDMI PHY */
++ u8 phy_auto_rst; /* PHY_CTL2, default = 0 */
++ u8 hdmi_det_v; /* HDMI_DET, default = 0 */
++ u8 h_pi_rst; /* HV_RST, default = 0 */
++ u8 v_pi_rst; /* HV_RST, default = 0 */
++};
++
++enum tc358743_cable_connection {
++ TC358743_CABLE_PLUGGED,
++ TC358743_CABLE_UNPLUGGED,
++};
++
++/* notify events */
++#define TC358743_FMT_CHANGE 1
++
++/* ioctls */
++#define TC358743_CSI_RESET _IO('a', 1)
++
++/* custom controls */
++#define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0)
++#define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1)
++
++#endif
+diff -Nur linux-3.14.72.orig/include/media/v4l2-chip-ident.h linux-3.14.72/include/media/v4l2-chip-ident.h
+--- linux-3.14.72.orig/include/media/v4l2-chip-ident.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/media/v4l2-chip-ident.h 2016-06-19 22:11:55.505126884 +0200
+@@ -0,0 +1,359 @@
++/*
++ v4l2 chip identifiers header
++
++ This header provides a list of chip identifiers that can be returned
++ through the VIDIOC_DBG_G_CHIP_IDENT ioctl.
++
++ Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 2 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ */
++
++#ifndef V4L2_CHIP_IDENT_H_
++#define V4L2_CHIP_IDENT_H_
++
++/* VIDIOC_DBG_G_CHIP_IDENT: identifies the actual chip installed on the board */
++
++/* KEEP THIS LIST ORDERED BY ID!
++ Otherwise it will be hard to see which ranges are already in use when
++ adding support to a new chip family. */
++enum {
++ /* general idents: reserved range 0-49 */
++ V4L2_IDENT_NONE = 0, /* No chip matched */
++ V4L2_IDENT_AMBIGUOUS = 1, /* Match too general, multiple chips matched */
++ V4L2_IDENT_UNKNOWN = 2, /* Chip found, but cannot identify */
++
++ /* module tvaudio: reserved range 50-99 */
++ V4L2_IDENT_TVAUDIO = 50, /* A tvaudio chip, unknown which it is exactly */
++
++ /* Sony IMX074 */
++ V4L2_IDENT_IMX074 = 74,
++
++ /* module saa7110: just ident 100 */
++ V4L2_IDENT_SAA7110 = 100,
++
++ /* module saa7115: reserved range 101-149 */
++ V4L2_IDENT_SAA7111 = 101,
++ V4L2_IDENT_SAA7111A = 102,
++ V4L2_IDENT_SAA7113 = 103,
++ V4L2_IDENT_SAA7114 = 104,
++ V4L2_IDENT_SAA7115 = 105,
++ V4L2_IDENT_SAA7118 = 108,
++
++ V4L2_IDENT_GM7113C = 140,
++
++ /* module saa7127: reserved range 150-199 */
++ V4L2_IDENT_SAA7127 = 157,
++ V4L2_IDENT_SAA7129 = 159,
++
++ /* module cx25840: reserved range 200-249 */
++ V4L2_IDENT_CX25836 = 236,
++ V4L2_IDENT_CX25837 = 237,
++ V4L2_IDENT_CX25840 = 240,
++ V4L2_IDENT_CX25841 = 241,
++ V4L2_IDENT_CX25842 = 242,
++ V4L2_IDENT_CX25843 = 243,
++
++ /* OmniVision sensors: reserved range 250-299 */
++ V4L2_IDENT_OV7670 = 250,
++ V4L2_IDENT_OV7720 = 251,
++ V4L2_IDENT_OV7725 = 252,
++ V4L2_IDENT_OV7660 = 253,
++ V4L2_IDENT_OV9650 = 254,
++ V4L2_IDENT_OV9655 = 255,
++ V4L2_IDENT_SOI968 = 256,
++ V4L2_IDENT_OV9640 = 257,
++ V4L2_IDENT_OV6650 = 258,
++ V4L2_IDENT_OV2640 = 259,
++ V4L2_IDENT_OV9740 = 260,
++ V4L2_IDENT_OV5642 = 261,
++
++ /* module saa7146: reserved range 300-309 */
++ V4L2_IDENT_SAA7146 = 300,
++
++ /* Conexant MPEG encoder/decoders: reserved range 400-420 */
++ V4L2_IDENT_CX23418_843 = 403, /* Integrated A/V Decoder on the '418 */
++ V4L2_IDENT_CX23415 = 415,
++ V4L2_IDENT_CX23416 = 416,
++ V4L2_IDENT_CX23417 = 417,
++ V4L2_IDENT_CX23418 = 418,
++
++ /* module bt819: reserved range 810-819 */
++ V4L2_IDENT_BT815A = 815,
++ V4L2_IDENT_BT817A = 817,
++ V4L2_IDENT_BT819A = 819,
++
++ /* module au0828 */
++ V4L2_IDENT_AU0828 = 828,
++
++ /* module bttv: ident 848 + 849 */
++ V4L2_IDENT_BT848 = 848,
++ V4L2_IDENT_BT849 = 849,
++
++ /* module bt856: just ident 856 */
++ V4L2_IDENT_BT856 = 856,
++
++ /* module bt866: just ident 866 */
++ V4L2_IDENT_BT866 = 866,
++
++ /* module bttv: ident 878 + 879 */
++ V4L2_IDENT_BT878 = 878,
++ V4L2_IDENT_BT879 = 879,
++
++ /* module ks0127: reserved range 1120-1129 */
++ V4L2_IDENT_KS0122S = 1122,
++ V4L2_IDENT_KS0127 = 1127,
++ V4L2_IDENT_KS0127B = 1128,
++
++ /* module indycam: just ident 2000 */
++ V4L2_IDENT_INDYCAM = 2000,
++
++ /* module vp27smpx: just ident 2700 */
++ V4L2_IDENT_VP27SMPX = 2700,
++
++ /* module vpx3220: reserved range: 3210-3229 */
++ V4L2_IDENT_VPX3214C = 3214,
++ V4L2_IDENT_VPX3216B = 3216,
++ V4L2_IDENT_VPX3220A = 3220,
++
++ /* VX855 just ident 3409 */
++ /* Other via devs could use 3314, 3324, 3327, 3336, 3364, 3353 */
++ V4L2_IDENT_VIA_VX855 = 3409,
++
++ /* module tvp5150 */
++ V4L2_IDENT_TVP5150 = 5150,
++
++ /* module saa5246a: just ident 5246 */
++ V4L2_IDENT_SAA5246A = 5246,
++
++ /* module saa5249: just ident 5249 */
++ V4L2_IDENT_SAA5249 = 5249,
++
++ /* module cs5345: just ident 5345 */
++ V4L2_IDENT_CS5345 = 5345,
++
++ /* module tea6415c: just ident 6415 */
++ V4L2_IDENT_TEA6415C = 6415,
++
++ /* module tea6420: just ident 6420 */
++ V4L2_IDENT_TEA6420 = 6420,
++
++ /* module saa6588: just ident 6588 */
++ V4L2_IDENT_SAA6588 = 6588,
++
++ /* module vs6624: just ident 6624 */
++ V4L2_IDENT_VS6624 = 6624,
++
++ /* module saa6752hs: reserved range 6750-6759 */
++ V4L2_IDENT_SAA6752HS = 6752,
++ V4L2_IDENT_SAA6752HS_AC3 = 6753,
++
++ /* modules tef6862: just ident 6862 */
++ V4L2_IDENT_TEF6862 = 6862,
++
++ /* module tvp7002: just ident 7002 */
++ V4L2_IDENT_TVP7002 = 7002,
++
++ /* module adv7170: just ident 7170 */
++ V4L2_IDENT_ADV7170 = 7170,
++
++ /* module adv7175: just ident 7175 */
++ V4L2_IDENT_ADV7175 = 7175,
++
++ /* module adv7180: just ident 7180 */
++ V4L2_IDENT_ADV7180 = 7180,
++
++ /* module adv7183: just ident 7183 */
++ V4L2_IDENT_ADV7183 = 7183,
++
++ /* module saa7185: just ident 7185 */
++ V4L2_IDENT_SAA7185 = 7185,
++
++ /* module saa7191: just ident 7191 */
++ V4L2_IDENT_SAA7191 = 7191,
++
++ /* module ths7303: just ident 7303 */
++ V4L2_IDENT_THS7303 = 7303,
++
++ /* module adv7343: just ident 7343 */
++ V4L2_IDENT_ADV7343 = 7343,
++
++ /* module ths7353: just ident 7353 */
++ V4L2_IDENT_THS7353 = 7353,
++
++ /* module adv7393: just ident 7393 */
++ V4L2_IDENT_ADV7393 = 7393,
++
++ /* module adv7604: just ident 7604 */
++ V4L2_IDENT_ADV7604 = 7604,
++
++ /* module saa7706h: just ident 7706 */
++ V4L2_IDENT_SAA7706H = 7706,
++
++ /* module mt9v011, just ident 8243 */
++ V4L2_IDENT_MT9V011 = 8243,
++
++ /* module wm8739: just ident 8739 */
++ V4L2_IDENT_WM8739 = 8739,
++
++ /* module wm8775: just ident 8775 */
++ V4L2_IDENT_WM8775 = 8775,
++
++ /* Marvell controllers starting at 8801 */
++ V4L2_IDENT_CAFE = 8801,
++ V4L2_IDENT_ARMADA610 = 8802,
++
++ /* AKM AK8813/AK8814 */
++ V4L2_IDENT_AK8813 = 8813,
++ V4L2_IDENT_AK8814 = 8814,
++
++ /* module cx23885 and cx25840 */
++ V4L2_IDENT_CX23885 = 8850,
++ V4L2_IDENT_CX23885_AV = 8851, /* Integrated A/V decoder */
++ V4L2_IDENT_CX23887 = 8870,
++ V4L2_IDENT_CX23887_AV = 8871, /* Integrated A/V decoder */
++ V4L2_IDENT_CX23888 = 8880,
++ V4L2_IDENT_CX23888_AV = 8881, /* Integrated A/V decoder */
++ V4L2_IDENT_CX23888_IR = 8882, /* Integrated infrared controller */
++
++ /* module ad9389b: just ident 9389 */
++ V4L2_IDENT_AD9389B = 9389,
++
++ /* module tda1997x */
++ V4L2_IDENT_TDA19971 = 19971,
++ V4L2_IDENT_TDA19973 = 19973,
++
++ /* module tda9840: just ident 9840 */
++ V4L2_IDENT_TDA9840 = 9840,
++
++ /* module tw9910: just ident 9910 */
++ V4L2_IDENT_TW9910 = 9910,
++
++ /* module sn9c20x: just ident 10000 */
++ V4L2_IDENT_SN9C20X = 10000,
++
++ /* module cx231xx and cx25840 */
++ V4L2_IDENT_CX2310X_AV = 23099, /* Integrated A/V decoder; not in '100 */
++ V4L2_IDENT_CX23100 = 23100,
++ V4L2_IDENT_CX23101 = 23101,
++ V4L2_IDENT_CX23102 = 23102,
++
++ /* module msp3400: reserved range 34000-34999 for msp34xx */
++ V4L2_IDENT_MSPX4XX = 34000, /* generic MSPX4XX identifier, only
++ use internally (tveeprom.c). */
++
++ V4L2_IDENT_MSP3400B = 34002,
++ V4L2_IDENT_MSP3400C = 34003,
++ V4L2_IDENT_MSP3400D = 34004,
++ V4L2_IDENT_MSP3400G = 34007,
++ V4L2_IDENT_MSP3401G = 34017,
++ V4L2_IDENT_MSP3402G = 34027,
++ V4L2_IDENT_MSP3405D = 34054,
++ V4L2_IDENT_MSP3405G = 34057,
++ V4L2_IDENT_MSP3407D = 34074,
++ V4L2_IDENT_MSP3407G = 34077,
++
++ V4L2_IDENT_MSP3410B = 34102,
++ V4L2_IDENT_MSP3410C = 34103,
++ V4L2_IDENT_MSP3410D = 34104,
++ V4L2_IDENT_MSP3410G = 34107,
++ V4L2_IDENT_MSP3411G = 34117,
++ V4L2_IDENT_MSP3412G = 34127,
++ V4L2_IDENT_MSP3415D = 34154,
++ V4L2_IDENT_MSP3415G = 34157,
++ V4L2_IDENT_MSP3417D = 34174,
++ V4L2_IDENT_MSP3417G = 34177,
++
++ V4L2_IDENT_MSP3420G = 34207,
++ V4L2_IDENT_MSP3421G = 34217,
++ V4L2_IDENT_MSP3422G = 34227,
++ V4L2_IDENT_MSP3425G = 34257,
++ V4L2_IDENT_MSP3427G = 34277,
++
++ V4L2_IDENT_MSP3430G = 34307,
++ V4L2_IDENT_MSP3431G = 34317,
++ V4L2_IDENT_MSP3435G = 34357,
++ V4L2_IDENT_MSP3437G = 34377,
++
++ V4L2_IDENT_MSP3440G = 34407,
++ V4L2_IDENT_MSP3441G = 34417,
++ V4L2_IDENT_MSP3442G = 34427,
++ V4L2_IDENT_MSP3445G = 34457,
++ V4L2_IDENT_MSP3447G = 34477,
++
++ V4L2_IDENT_MSP3450G = 34507,
++ V4L2_IDENT_MSP3451G = 34517,
++ V4L2_IDENT_MSP3452G = 34527,
++ V4L2_IDENT_MSP3455G = 34557,
++ V4L2_IDENT_MSP3457G = 34577,
++
++ V4L2_IDENT_MSP3460G = 34607,
++ V4L2_IDENT_MSP3461G = 34617,
++ V4L2_IDENT_MSP3465G = 34657,
++ V4L2_IDENT_MSP3467G = 34677,
++
++ /* module msp3400: reserved range 44000-44999 for msp44xx */
++ V4L2_IDENT_MSP4400G = 44007,
++ V4L2_IDENT_MSP4408G = 44087,
++ V4L2_IDENT_MSP4410G = 44107,
++ V4L2_IDENT_MSP4418G = 44187,
++ V4L2_IDENT_MSP4420G = 44207,
++ V4L2_IDENT_MSP4428G = 44287,
++ V4L2_IDENT_MSP4440G = 44407,
++ V4L2_IDENT_MSP4448G = 44487,
++ V4L2_IDENT_MSP4450G = 44507,
++ V4L2_IDENT_MSP4458G = 44587,
++
++ /* Micron CMOS sensor chips: 45000-45099 */
++ V4L2_IDENT_MT9M001C12ST = 45000,
++ V4L2_IDENT_MT9M001C12STM = 45005,
++ V4L2_IDENT_MT9M111 = 45007,
++ V4L2_IDENT_MT9M112 = 45008,
++ V4L2_IDENT_MT9V022IX7ATC = 45010, /* No way to detect "normal" I77ATx */
++ V4L2_IDENT_MT9V022IX7ATM = 45015, /* and "lead free" IA7ATx chips */
++ V4L2_IDENT_MT9T031 = 45020,
++ V4L2_IDENT_MT9T111 = 45021,
++ V4L2_IDENT_MT9T112 = 45022,
++ V4L2_IDENT_MT9V111 = 45031,
++ V4L2_IDENT_MT9V112 = 45032,
++
++ /* HV7131R CMOS sensor: just ident 46000 */
++ V4L2_IDENT_HV7131R = 46000,
++
++ /* Sharp RJ54N1CB0C, 0xCB0C = 51980 */
++ V4L2_IDENT_RJ54N1CB0C = 51980,
++
++ /* module m52790: just ident 52790 */
++ V4L2_IDENT_M52790 = 52790,
++
++ /* module cs53132a: just ident 53132 */
++ V4L2_IDENT_CS53l32A = 53132,
++
++ /* modules upd61151 MPEG2 encoder: just ident 54000 */
++ V4L2_IDENT_UPD61161 = 54000,
++ /* modules upd61152 MPEG2 encoder with AC3: just ident 54001 */
++ V4L2_IDENT_UPD61162 = 54001,
++
++ /* module upd64031a: just ident 64031 */
++ V4L2_IDENT_UPD64031A = 64031,
++
++ /* module upd64083: just ident 64083 */
++ V4L2_IDENT_UPD64083 = 64083,
++
++ /* Don't just add new IDs at the end: KEEP THIS LIST ORDERED BY ID! */
++};
++
++#endif
+diff -Nur linux-3.14.72.orig/include/media/v4l2-dev.h linux-3.14.72/include/media/v4l2-dev.h
+--- linux-3.14.72.orig/include/media/v4l2-dev.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/media/v4l2-dev.h 2016-06-19 22:11:55.505126884 +0200
+@@ -96,9 +96,9 @@
+ struct device dev; /* v4l device */
+ struct cdev *cdev; /* character device */
+
++ /* Set either parent or v4l2_dev if your driver uses v4l2_device */
++ struct device *parent; /* device parent */
+ struct v4l2_device *v4l2_dev; /* v4l2_device parent */
+- /* Only set parent if that can't be deduced from v4l2_dev */
+- struct device *dev_parent; /* device parent */
+
+ /* Control handler associated with this device node. May be NULL. */
+ struct v4l2_ctrl_handler *ctrl_handler;
+diff -Nur linux-3.14.72.orig/include/media/v4l2-ioctl.h linux-3.14.72/include/media/v4l2-ioctl.h
+--- linux-3.14.72.orig/include/media/v4l2-ioctl.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/media/v4l2-ioctl.h 2016-06-19 22:11:55.505126884 +0200
+@@ -247,6 +247,8 @@
+ int (*vidioc_g_chip_info) (struct file *file, void *fh,
+ struct v4l2_dbg_chip_info *chip);
+ #endif
++ int (*vidioc_g_chip_ident) (struct file *file, void *fh,
++ struct v4l2_dbg_chip_ident *chip);
+
+ int (*vidioc_enum_framesizes) (struct file *file, void *fh,
+ struct v4l2_frmsizeenum *fsize);
+diff -Nur linux-3.14.72.orig/include/media/v4l2-subdev.h linux-3.14.72/include/media/v4l2-subdev.h
+--- linux-3.14.72.orig/include/media/v4l2-subdev.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/media/v4l2-subdev.h 2016-06-19 22:11:55.505126884 +0200
+@@ -89,6 +89,7 @@
+
+ /* Core ops: it is highly recommended to implement at least these ops:
+
++ g_chip_ident
+ log_status
+ g_register
+ s_register
+@@ -145,6 +146,7 @@
+ performed later. It must not sleep. *Called from an IRQ context*.
+ */
+ struct v4l2_subdev_core_ops {
++ int (*g_chip_ident)(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip);
+ int (*log_status)(struct v4l2_subdev *sd);
+ int (*s_io_pin_config)(struct v4l2_subdev *sd, size_t n,
+ struct v4l2_subdev_io_pin_config *pincfg);
+@@ -680,7 +682,7 @@
+ /* Call an ops of a v4l2_subdev, doing the right checks against
+ NULL pointers.
+
+- Example: err = v4l2_subdev_call(sd, core, s_std, norm);
++ Example: err = v4l2_subdev_call(sd, core, g_chip_ident, &chip);
+ */
+ #define v4l2_subdev_call(sd, o, f, args...) \
+ (!(sd) ? -ENODEV : (((sd)->ops->o && (sd)->ops->o->f) ? \
+diff -Nur linux-3.14.72.orig/include/net/cfg80211.h linux-3.14.72/include/net/cfg80211.h
+--- linux-3.14.72.orig/include/net/cfg80211.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/net/cfg80211.h 2016-06-19 22:11:55.505126884 +0200
+@@ -1729,7 +1729,7 @@
+ u8 *ssid;
+ size_t ssid_len;
+ enum nl80211_auth_type auth_type;
+- u8 *ie;
++ const u8 *ie;
+ size_t ie_len;
+ bool privacy;
+ enum nl80211_mfp mfp;
+@@ -3888,6 +3888,7 @@
+ *
+ * @dev: network device
+ * @bssid: the BSSID of the IBSS joined
++ * @channel: the channel of the IBSS joined
+ * @gfp: allocation flags
+ *
+ * This function notifies cfg80211 that the device joined an IBSS or
+@@ -3897,7 +3898,8 @@
+ * with the locally generated beacon -- this guarantees that there is
+ * always a scan result for this IBSS. cfg80211 will handle the rest.
+ */
+-void cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid, gfp_t gfp);
++void cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid,
++ struct ieee80211_channel *channel, gfp_t gfp);
+
+ /**
+ * cfg80211_notify_new_candidate - notify cfg80211 of a new mesh peer candidate
+diff -Nur linux-3.14.72.orig/include/net/tso.h linux-3.14.72/include/net/tso.h
+--- linux-3.14.72.orig/include/net/tso.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/net/tso.h 2016-06-19 22:11:55.505126884 +0200
+@@ -0,0 +1,20 @@
++#ifndef _TSO_H
++#define _TSO_H
++
++#include <net/ip.h>
++
++struct tso_t {
++ int next_frag_idx;
++ void *data;
++ size_t size;
++ u16 ip_id;
++ u32 tcp_seq;
++};
++
++int tso_count_descs(struct sk_buff *skb);
++void tso_build_hdr(struct sk_buff *skb, char *hdr, struct tso_t *tso,
++ int size, bool is_last);
++void tso_build_data(struct sk_buff *skb, struct tso_t *tso, int size);
++void tso_start(struct sk_buff *skb, struct tso_t *tso);
++
++#endif /* _TSO_H */
+diff -Nur linux-3.14.72.orig/include/scsi/libsas.h linux-3.14.72/include/scsi/libsas.h
+--- linux-3.14.72.orig/include/scsi/libsas.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/scsi/libsas.h 2016-06-19 22:11:55.505126884 +0200
+@@ -172,7 +172,6 @@
+ enum ata_command_set command_set;
+ struct smp_resp rps_resp; /* report_phy_sata_resp */
+ u8 port_no; /* port number, if this is a PM (Port) */
+- int pm_result;
+
+ struct ata_port *ap;
+ struct ata_host ata_host;
+diff -Nur linux-3.14.72.orig/include/sound/dmaengine_pcm.h linux-3.14.72/include/sound/dmaengine_pcm.h
+--- linux-3.14.72.orig/include/sound/dmaengine_pcm.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/sound/dmaengine_pcm.h 2016-06-19 22:11:55.505126884 +0200
+@@ -63,6 +63,8 @@
+ * requesting the DMA channel.
+ * @chan_name: Custom channel name to use when requesting DMA channel.
+ * @fifo_size: FIFO size of the DAI controller in bytes
++ * @check_xrun: check if hardware xrun happen in the cpu dai.
++ * @device_reset: if xrun happened, then do cpu dai reset.
+ */
+ struct snd_dmaengine_dai_dma_data {
+ dma_addr_t addr;
+@@ -72,6 +74,16 @@
+ void *filter_data;
+ const char *chan_name;
+ unsigned int fifo_size;
++ bool (*check_xrun)(struct snd_pcm_substream *substream);
++ void (*device_reset)(struct snd_pcm_substream *substream, bool stop);
++};
++
++struct dmaengine_pcm_runtime_data {
++ struct dma_chan *dma_chan;
++ dma_cookie_t cookie;
++
++ unsigned int pos;
++ dma_async_tx_callback callback;
+ };
+
+ void snd_dmaengine_pcm_set_config_from_dai_data(
+diff -Nur linux-3.14.72.orig/include/sound/soc.h linux-3.14.72/include/sound/soc.h
+--- linux-3.14.72.orig/include/sound/soc.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/sound/soc.h 2016-06-19 22:11:55.505126884 +0200
+@@ -45,6 +45,11 @@
+ ((unsigned long)&(struct soc_mixer_control) \
+ {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \
+ .max = xmax, .platform_max = xmax, .invert = xinvert})
++#define SOC_DOUBLE_R_S_VALUE(xlreg, xrreg, xshift, xmin, xmax, xsign_bit, xinvert) \
++ ((unsigned long)&(struct soc_mixer_control) \
++ {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \
++ .max = xmax, .min = xmin, .platform_max = xmax, .sign_bit = xsign_bit, \
++ .invert = xinvert})
+ #define SOC_DOUBLE_R_RANGE_VALUE(xlreg, xrreg, xshift, xmin, xmax, xinvert) \
+ ((unsigned long)&(struct soc_mixer_control) \
+ {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \
+@@ -152,6 +157,15 @@
+ {.reg = xreg, .rreg = xrreg, \
+ .shift = xshift, .rshift = xshift, \
+ .max = xmax, .min = xmin} }
++#define SOC_DOUBLE_R_S_TLV(xname, reg_left, reg_right, xshift, xmin, xmax, xsign_bit, xinvert, tlv_array) \
++{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
++ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
++ SNDRV_CTL_ELEM_ACCESS_READWRITE,\
++ .tlv.p = (tlv_array), \
++ .info = snd_soc_info_volsw, \
++ .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \
++ .private_value = SOC_DOUBLE_R_S_VALUE(reg_left, reg_right, xshift, \
++ xmin, xmax, xsign_bit, xinvert) }
+ #define SOC_DOUBLE_S8_TLV(xname, xreg, xmin, xmax, tlv_array) \
+ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
+ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
+@@ -369,6 +383,8 @@
+ int snd_soc_poweroff(struct device *dev);
+ int snd_soc_register_platform(struct device *dev,
+ const struct snd_soc_platform_driver *platform_drv);
++int devm_snd_soc_register_platform(struct device *dev,
++ const struct snd_soc_platform_driver *platform_drv);
+ void snd_soc_unregister_platform(struct device *dev);
+ int snd_soc_add_platform(struct device *dev, struct snd_soc_platform *platform,
+ const struct snd_soc_platform_driver *platform_drv);
+@@ -412,6 +428,7 @@
+ const char *dai_link, int stream);
+ struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card,
+ const char *dai_link);
++int soc_ac97_dev_register(struct snd_soc_codec *codec);
+
+ /* Utility functions to get clock rates from various things */
+ int snd_soc_calc_frame_size(int sample_size, int channels, int tdm_slots);
+@@ -1067,6 +1084,7 @@
+ int min, max, platform_max;
+ int reg, rreg;
+ unsigned int shift, rshift;
++ unsigned int sign_bit;
+ unsigned int invert:1;
+ unsigned int autodisable:1;
+ };
+diff -Nur linux-3.14.72.orig/include/sound/wm8962.h linux-3.14.72/include/sound/wm8962.h
+--- linux-3.14.72.orig/include/sound/wm8962.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/sound/wm8962.h 2016-06-19 22:11:55.505126884 +0200
+@@ -37,6 +37,7 @@
+ #define WM8962_GPIO_FN_MICSCD 22
+
+ struct wm8962_pdata {
++ struct clk *mclk;
+ int gpio_base;
+ u32 gpio_init[WM8962_MAX_GPIO];
+
+diff -Nur linux-3.14.72.orig/include/trace/events/cpufreq_interactive.h linux-3.14.72/include/trace/events/cpufreq_interactive.h
+--- linux-3.14.72.orig/include/trace/events/cpufreq_interactive.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/trace/events/cpufreq_interactive.h 2016-06-19 22:11:55.505126884 +0200
+@@ -0,0 +1,112 @@
++#undef TRACE_SYSTEM
++#define TRACE_SYSTEM cpufreq_interactive
++
++#if !defined(_TRACE_CPUFREQ_INTERACTIVE_H) || defined(TRACE_HEADER_MULTI_READ)
++#define _TRACE_CPUFREQ_INTERACTIVE_H
++
++#include <linux/tracepoint.h>
++
++DECLARE_EVENT_CLASS(set,
++ TP_PROTO(u32 cpu_id, unsigned long targfreq,
++ unsigned long actualfreq),
++ TP_ARGS(cpu_id, targfreq, actualfreq),
++
++ TP_STRUCT__entry(
++ __field( u32, cpu_id )
++ __field(unsigned long, targfreq )
++ __field(unsigned long, actualfreq )
++ ),
++
++ TP_fast_assign(
++ __entry->cpu_id = (u32) cpu_id;
++ __entry->targfreq = targfreq;
++ __entry->actualfreq = actualfreq;
++ ),
++
++ TP_printk("cpu=%u targ=%lu actual=%lu",
++ __entry->cpu_id, __entry->targfreq,
++ __entry->actualfreq)
++);
++
++DEFINE_EVENT(set, cpufreq_interactive_setspeed,
++ TP_PROTO(u32 cpu_id, unsigned long targfreq,
++ unsigned long actualfreq),
++ TP_ARGS(cpu_id, targfreq, actualfreq)
++);
++
++DECLARE_EVENT_CLASS(loadeval,
++ TP_PROTO(unsigned long cpu_id, unsigned long load,
++ unsigned long curtarg, unsigned long curactual,
++ unsigned long newtarg),
++ TP_ARGS(cpu_id, load, curtarg, curactual, newtarg),
++
++ TP_STRUCT__entry(
++ __field(unsigned long, cpu_id )
++ __field(unsigned long, load )
++ __field(unsigned long, curtarg )
++ __field(unsigned long, curactual )
++ __field(unsigned long, newtarg )
++ ),
++
++ TP_fast_assign(
++ __entry->cpu_id = cpu_id;
++ __entry->load = load;
++ __entry->curtarg = curtarg;
++ __entry->curactual = curactual;
++ __entry->newtarg = newtarg;
++ ),
++
++ TP_printk("cpu=%lu load=%lu cur=%lu actual=%lu targ=%lu",
++ __entry->cpu_id, __entry->load, __entry->curtarg,
++ __entry->curactual, __entry->newtarg)
++);
++
++DEFINE_EVENT(loadeval, cpufreq_interactive_target,
++ TP_PROTO(unsigned long cpu_id, unsigned long load,
++ unsigned long curtarg, unsigned long curactual,
++ unsigned long newtarg),
++ TP_ARGS(cpu_id, load, curtarg, curactual, newtarg)
++);
++
++DEFINE_EVENT(loadeval, cpufreq_interactive_already,
++ TP_PROTO(unsigned long cpu_id, unsigned long load,
++ unsigned long curtarg, unsigned long curactual,
++ unsigned long newtarg),
++ TP_ARGS(cpu_id, load, curtarg, curactual, newtarg)
++);
++
++DEFINE_EVENT(loadeval, cpufreq_interactive_notyet,
++ TP_PROTO(unsigned long cpu_id, unsigned long load,
++ unsigned long curtarg, unsigned long curactual,
++ unsigned long newtarg),
++ TP_ARGS(cpu_id, load, curtarg, curactual, newtarg)
++);
++
++TRACE_EVENT(cpufreq_interactive_boost,
++ TP_PROTO(const char *s),
++ TP_ARGS(s),
++ TP_STRUCT__entry(
++ __string(s, s)
++ ),
++ TP_fast_assign(
++ __assign_str(s, s);
++ ),
++ TP_printk("%s", __get_str(s))
++);
++
++TRACE_EVENT(cpufreq_interactive_unboost,
++ TP_PROTO(const char *s),
++ TP_ARGS(s),
++ TP_STRUCT__entry(
++ __string(s, s)
++ ),
++ TP_fast_assign(
++ __assign_str(s, s);
++ ),
++ TP_printk("%s", __get_str(s))
++);
++
++#endif /* _TRACE_CPUFREQ_INTERACTIVE_H */
++
++/* This part must be outside protection */
++#include <trace/define_trace.h>
+diff -Nur linux-3.14.72.orig/include/uapi/linux/crypto/cryptodev.h linux-3.14.72/include/uapi/linux/crypto/cryptodev.h
+--- linux-3.14.72.orig/include/uapi/linux/crypto/cryptodev.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/crypto/cryptodev.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,292 @@
++/* This is a source compatible implementation with the original API of
++ * cryptodev by Angelos D. Keromytis, found at openbsd cryptodev.h.
++ * Placed under public domain */
++
++#ifndef L_CRYPTODEV_H
++#define L_CRYPTODEV_H
++
++#include <linux/types.h>
++#ifndef __KERNEL__
++#define __user
++#endif
++
++/* API extensions for linux */
++#define CRYPTO_HMAC_MAX_KEY_LEN 512
++#define CRYPTO_CIPHER_MAX_KEY_LEN 64
++
++/* All the supported algorithms
++ */
++enum cryptodev_crypto_op_t {
++ CRYPTO_DES_CBC = 1,
++ CRYPTO_3DES_CBC = 2,
++ CRYPTO_BLF_CBC = 3,
++ CRYPTO_CAST_CBC = 4,
++ CRYPTO_SKIPJACK_CBC = 5,
++ CRYPTO_MD5_HMAC = 6,
++ CRYPTO_SHA1_HMAC = 7,
++ CRYPTO_RIPEMD160_HMAC = 8,
++ CRYPTO_MD5_KPDK = 9,
++ CRYPTO_SHA1_KPDK = 10,
++ CRYPTO_RIJNDAEL128_CBC = 11,
++ CRYPTO_AES_CBC = CRYPTO_RIJNDAEL128_CBC,
++ CRYPTO_ARC4 = 12,
++ CRYPTO_MD5 = 13,
++ CRYPTO_SHA1 = 14,
++ CRYPTO_DEFLATE_COMP = 15,
++ CRYPTO_NULL = 16,
++ CRYPTO_LZS_COMP = 17,
++ CRYPTO_SHA2_256_HMAC = 18,
++ CRYPTO_SHA2_384_HMAC = 19,
++ CRYPTO_SHA2_512_HMAC = 20,
++ CRYPTO_AES_CTR = 21,
++ CRYPTO_AES_XTS = 22,
++ CRYPTO_AES_ECB = 23,
++ CRYPTO_AES_GCM = 50,
++
++ CRYPTO_CAMELLIA_CBC = 101,
++ CRYPTO_RIPEMD160,
++ CRYPTO_SHA2_224,
++ CRYPTO_SHA2_256,
++ CRYPTO_SHA2_384,
++ CRYPTO_SHA2_512,
++ CRYPTO_SHA2_224_HMAC,
++ CRYPTO_ALGORITHM_ALL, /* Keep updated - see below */
++};
++
++#define CRYPTO_ALGORITHM_MAX (CRYPTO_ALGORITHM_ALL - 1)
++
++/* Values for ciphers */
++#define DES_BLOCK_LEN 8
++#define DES3_BLOCK_LEN 8
++#define RIJNDAEL128_BLOCK_LEN 16
++#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN
++#define CAMELLIA_BLOCK_LEN 16
++#define BLOWFISH_BLOCK_LEN 8
++#define SKIPJACK_BLOCK_LEN 8
++#define CAST128_BLOCK_LEN 8
++
++/* the maximum of the above */
++#define EALG_MAX_BLOCK_LEN 16
++
++/* Values for hashes/MAC */
++#define AALG_MAX_RESULT_LEN 64
++
++/* maximum length of verbose alg names (depends on CRYPTO_MAX_ALG_NAME) */
++#define CRYPTODEV_MAX_ALG_NAME 64
++
++#define HASH_MAX_LEN 64
++
++/* input of CIOCGSESSION */
++struct session_op {
++ /* Specify either cipher or mac
++ */
++ __u32 cipher; /* cryptodev_crypto_op_t */
++ __u32 mac; /* cryptodev_crypto_op_t */
++
++ __u32 keylen;
++ __u8 __user *key;
++ __u32 mackeylen;
++ __u8 __user *mackey;
++
++ __u32 ses; /* session identifier */
++};
++
++struct session_info_op {
++ __u32 ses; /* session identifier */
++
++ /* verbose names for the requested ciphers */
++ struct alg_info {
++ char cra_name[CRYPTODEV_MAX_ALG_NAME];
++ char cra_driver_name[CRYPTODEV_MAX_ALG_NAME];
++ } cipher_info, hash_info;
++
++ __u16 alignmask; /* alignment constraints */
++ __u32 flags; /* SIOP_FLAGS_* */
++};
++
++/* If this flag is set then this algorithm uses
++ * a driver only available in kernel (software drivers,
++ * or drivers based on instruction sets do not set this flag).
++ *
++ * If multiple algorithms are involved (as in AEAD case), then
++ * if one of them is kernel-driver-only this flag will be set.
++ */
++#define SIOP_FLAG_KERNEL_DRIVER_ONLY 1
++
++#define COP_ENCRYPT 0
++#define COP_DECRYPT 1
++
++/* input of CIOCCRYPT */
++struct crypt_op {
++ __u32 ses; /* session identifier */
++ __u16 op; /* COP_ENCRYPT or COP_DECRYPT */
++ __u16 flags; /* see COP_FLAG_* */
++ __u32 len; /* length of source data */
++ __u8 __user *src; /* source data */
++ __u8 __user *dst; /* pointer to output data */
++ /* pointer to output data for hash/MAC operations */
++ __u8 __user *mac;
++ /* initialization vector for encryption operations */
++ __u8 __user *iv;
++};
++
++/* input of CIOCAUTHCRYPT */
++struct crypt_auth_op {
++ __u32 ses; /* session identifier */
++ __u16 op; /* COP_ENCRYPT or COP_DECRYPT */
++ __u16 flags; /* see COP_FLAG_AEAD_* */
++ __u32 len; /* length of source data */
++ __u32 auth_len; /* length of auth data */
++ __u8 __user *auth_src; /* authenticated-only data */
++
++ /* The current implementation is more efficient if data are
++ * encrypted in-place (src==dst). */
++ __u8 __user *src; /* data to be encrypted and authenticated */
++ __u8 __user *dst; /* pointer to output data. Must have
++ * space for tag. For TLS this should be at least
++ * len + tag_size + block_size for padding */
++
++ __u8 __user *tag; /* where the tag will be copied to. TLS mode
++ * doesn't use that as tag is copied to dst.
++ * SRTP mode copies tag there. */
++ __u32 tag_len; /* the length of the tag. Use zero for digest size or max tag. */
++
++ /* initialization vector for encryption operations */
++ __u8 __user *iv;
++ __u32 iv_len;
++};
++
++/* In plain AEAD mode the following are required:
++ * flags : 0
++ * iv : the initialization vector (12 bytes)
++ * auth_len: the length of the data to be authenticated
++ * auth_src: the data to be authenticated
++ * len : length of data to be encrypted
++ * src : the data to be encrypted
++ * dst : space to hold encrypted data. It must have
++ * at least a size of len + tag_size.
++ * tag_size: the size of the desired authentication tag or zero to use
++ * the maximum tag output.
++ *
++ * Note tag isn't being used because the Linux AEAD interface
++ * copies the tag just after data.
++ */
++
++/* In TLS mode (used for CBC ciphers that required padding)
++ * the following are required:
++ * flags : COP_FLAG_AEAD_TLS_TYPE
++ * iv : the initialization vector
++ * auth_len: the length of the data to be authenticated only
++ * len : length of data to be encrypted
++ * auth_src: the data to be authenticated
++ * src : the data to be encrypted
++ * dst : space to hold encrypted data (preferably in-place). It must have
++ * at least a size of len + tag_size + blocksize.
++ * tag_size: the size of the desired authentication tag or zero to use
++ * the default mac output.
++ *
++ * Note that the padding used is the minimum padding.
++ */
++
++/* In SRTP mode the following are required:
++ * flags : COP_FLAG_AEAD_SRTP_TYPE
++ * iv : the initialization vector
++ * auth_len: the length of the data to be authenticated. This must
++ * include the SRTP header + SRTP payload (data to be encrypted) + rest
++ *
++ * len : length of data to be encrypted
++ * auth_src: pointer the data to be authenticated. Should point at the same buffer as src.
++ * src : pointer to the data to be encrypted.
++ * dst : This is mandatory to be the same as src (in-place only).
++ * tag_size: the size of the desired authentication tag or zero to use
++ * the default mac output.
++ * tag : Pointer to an address where the authentication tag will be copied.
++ */
++
++
++/* struct crypt_op flags */
++
++#define COP_FLAG_NONE (0 << 0) /* totally no flag */
++#define COP_FLAG_UPDATE (1 << 0) /* multi-update hash mode */
++#define COP_FLAG_FINAL (1 << 1) /* multi-update final hash mode */
++#define COP_FLAG_WRITE_IV (1 << 2) /* update the IV during operation */
++#define COP_FLAG_NO_ZC (1 << 3) /* do not zero-copy */
++#define COP_FLAG_AEAD_TLS_TYPE (1 << 4) /* authenticate and encrypt using the
++ * TLS protocol rules */
++#define COP_FLAG_AEAD_SRTP_TYPE (1 << 5) /* authenticate and encrypt using the
++ * SRTP protocol rules */
++#define COP_FLAG_RESET (1 << 6) /* multi-update reset the state.
++ * should be used in combination
++ * with COP_FLAG_UPDATE */
++
++
++/* Stuff for bignum arithmetic and public key
++ * cryptography - not supported yet by linux
++ * cryptodev.
++ */
++
++#define CRYPTO_ALG_FLAG_SUPPORTED 1
++#define CRYPTO_ALG_FLAG_RNG_ENABLE 2
++#define CRYPTO_ALG_FLAG_DSA_SHA 4
++
++struct crparam {
++ __u8 *crp_p;
++ __u32 crp_nbits;
++};
++
++#define CRK_MAXPARAM 8
++
++/* input of CIOCKEY */
++struct crypt_kop {
++ __u32 crk_op; /* cryptodev_crk_op_t */
++ __u32 crk_status;
++ __u16 crk_iparams;
++ __u16 crk_oparams;
++ __u32 crk_pad1;
++ struct crparam crk_param[CRK_MAXPARAM];
++};
++
++enum cryptodev_crk_op_t {
++ CRK_MOD_EXP = 0,
++ CRK_MOD_EXP_CRT = 1,
++ CRK_DSA_SIGN = 2,
++ CRK_DSA_VERIFY = 3,
++ CRK_DH_COMPUTE_KEY = 4,
++ CRK_ALGORITHM_ALL
++};
++
++#define CRK_ALGORITHM_MAX (CRK_ALGORITHM_ALL-1)
++
++/* features to be queried with CIOCASYMFEAT ioctl
++ */
++#define CRF_MOD_EXP (1 << CRK_MOD_EXP)
++#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT)
++#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN)
++#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY)
++#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY)
++
++
++/* ioctl's. Compatible with old linux cryptodev.h
++ */
++#define CRIOGET _IOWR('c', 101, __u32)
++#define CIOCGSESSION _IOWR('c', 102, struct session_op)
++#define CIOCFSESSION _IOW('c', 103, __u32)
++#define CIOCCRYPT _IOWR('c', 104, struct crypt_op)
++#define CIOCKEY _IOWR('c', 105, struct crypt_kop)
++#define CIOCASYMFEAT _IOR('c', 106, __u32)
++#define CIOCGSESSINFO _IOWR('c', 107, struct session_info_op)
++
++/* to indicate that CRIOGET is not required in linux
++ */
++#define CRIOGET_NOT_NEEDED 1
++
++/* additional ioctls for AEAD */
++#define CIOCAUTHCRYPT _IOWR('c', 109, struct crypt_auth_op)
++
++/* additional ioctls for asynchronous operation.
++ * These are conditionally enabled since version 1.6.
++ */
++#define CIOCASYNCCRYPT _IOW('c', 110, struct crypt_op)
++#define CIOCASYNCFETCH _IOR('c', 111, struct crypt_op)
++
++#endif /* L_CRYPTODEV_H */
+diff -Nur linux-3.14.72.orig/include/uapi/linux/ethtool.h linux-3.14.72/include/uapi/linux/ethtool.h
+--- linux-3.14.72.orig/include/uapi/linux/ethtool.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/ethtool.h 2016-06-19 22:11:55.509126621 +0200
+@@ -16,37 +16,97 @@
+ #include <linux/types.h>
+ #include <linux/if_ether.h>
+
+-/* This should work for both 32 and 64 bit userland. */
++/* All structures exposed to userland should be defined such that they
++ * have the same layout for 32-bit and 64-bit userland.
++ */
++
++/**
++ * struct ethtool_cmd - link control and status
++ * @cmd: Command number = %ETHTOOL_GSET or %ETHTOOL_SSET
++ * @supported: Bitmask of %SUPPORTED_* flags for the link modes,
++ * physical connectors and other link features for which the
++ * interface supports autonegotiation or auto-detection.
++ * Read-only.
++ * @advertising: Bitmask of %ADVERTISED_* flags for the link modes,
++ * physical connectors and other link features that are
++ * advertised through autonegotiation or enabled for
++ * auto-detection.
++ * @speed: Low bits of the speed
++ * @duplex: Duplex mode; one of %DUPLEX_*
++ * @port: Physical connector type; one of %PORT_*
++ * @phy_address: MDIO address of PHY (transceiver); 0 or 255 if not
++ * applicable. For clause 45 PHYs this is the PRTAD.
++ * @transceiver: Historically used to distinguish different possible
++ * PHY types, but not in a consistent way. Deprecated.
++ * @autoneg: Enable/disable autonegotiation and auto-detection;
++ * either %AUTONEG_DISABLE or %AUTONEG_ENABLE
++ * @mdio_support: Bitmask of %ETH_MDIO_SUPPORTS_* flags for the MDIO
++ * protocols supported by the interface; 0 if unknown.
++ * Read-only.
++ * @maxtxpkt: Historically used to report TX IRQ coalescing; now
++ * obsoleted by &struct ethtool_coalesce. Read-only; deprecated.
++ * @maxrxpkt: Historically used to report RX IRQ coalescing; now
++ * obsoleted by &struct ethtool_coalesce. Read-only; deprecated.
++ * @speed_hi: High bits of the speed
++ * @eth_tp_mdix: Ethernet twisted-pair MDI(-X) status; one of
++ * %ETH_TP_MDI_*. If the status is unknown or not applicable, the
++ * value will be %ETH_TP_MDI_INVALID. Read-only.
++ * @eth_tp_mdix_ctrl: Ethernet twisted pair MDI(-X) control; one of
++ * %ETH_TP_MDI_*. If MDI(-X) control is not implemented, reads
++ * yield %ETH_TP_MDI_INVALID and writes may be ignored or rejected.
++ * When written successfully, the link should be renegotiated if
++ * necessary.
++ * @lp_advertising: Bitmask of %ADVERTISED_* flags for the link modes
++ * and other link features that the link partner advertised
++ * through autonegotiation; 0 if unknown or not applicable.
++ * Read-only.
++ *
++ * The link speed in Mbps is split between @speed and @speed_hi. Use
++ * the ethtool_cmd_speed() and ethtool_cmd_speed_set() functions to
++ * access it.
++ *
++ * If autonegotiation is disabled, the speed and @duplex represent the
++ * fixed link mode and are writable if the driver supports multiple
++ * link modes. If it is enabled then they are read-only; if the link
++ * is up they represent the negotiated link mode; if the link is down,
++ * the speed is 0, %SPEED_UNKNOWN or the highest enabled speed and
++ * @duplex is %DUPLEX_UNKNOWN or the best enabled duplex mode.
++ *
++ * Some hardware interfaces may have multiple PHYs and/or physical
++ * connectors fitted or do not allow the driver to detect which are
++ * fitted. For these interfaces @port and/or @phy_address may be
++ * writable, possibly dependent on @autoneg being %AUTONEG_DISABLE.
++ * Otherwise, attempts to write different values may be ignored or
++ * rejected.
++ *
++ * Users should assume that all fields not marked read-only are
++ * writable and subject to validation by the driver. They should use
++ * %ETHTOOL_GSET to get the current values before making specific
++ * changes and then applying them with %ETHTOOL_SSET.
++ *
++ * Drivers that implement set_settings() should validate all fields
++ * other than @cmd that are not described as read-only or deprecated,
++ * and must ignore all fields described as read-only.
++ *
++ * Deprecated fields should be ignored by both users and drivers.
++ */
+ struct ethtool_cmd {
+ __u32 cmd;
+- __u32 supported; /* Features this interface supports */
+- __u32 advertising; /* Features this interface advertises */
+- __u16 speed; /* The forced speed (lower bits) in
+- * Mbps. Please use
+- * ethtool_cmd_speed()/_set() to
+- * access it */
+- __u8 duplex; /* Duplex, half or full */
+- __u8 port; /* Which connector port */
+- __u8 phy_address; /* MDIO PHY address (PRTAD for clause 45).
+- * May be read-only or read-write
+- * depending on the driver.
+- */
+- __u8 transceiver; /* Which transceiver to use */
+- __u8 autoneg; /* Enable or disable autonegotiation */
+- __u8 mdio_support; /* MDIO protocols supported. Read-only.
+- * Not set by all drivers.
+- */
+- __u32 maxtxpkt; /* Tx pkts before generating tx int */
+- __u32 maxrxpkt; /* Rx pkts before generating rx int */
+- __u16 speed_hi; /* The forced speed (upper
+- * bits) in Mbps. Please use
+- * ethtool_cmd_speed()/_set() to
+- * access it */
+- __u8 eth_tp_mdix; /* twisted pair MDI-X status */
+- __u8 eth_tp_mdix_ctrl; /* twisted pair MDI-X control, when set,
+- * link should be renegotiated if necessary
+- */
+- __u32 lp_advertising; /* Features the link partner advertises */
++ __u32 supported;
++ __u32 advertising;
++ __u16 speed;
++ __u8 duplex;
++ __u8 port;
++ __u8 phy_address;
++ __u8 transceiver;
++ __u8 autoneg;
++ __u8 mdio_support;
++ __u32 maxtxpkt;
++ __u32 maxrxpkt;
++ __u16 speed_hi;
++ __u8 eth_tp_mdix;
++ __u8 eth_tp_mdix_ctrl;
++ __u32 lp_advertising;
+ __u32 reserved[2];
+ };
+
+@@ -79,37 +139,68 @@
+
+ #define ETHTOOL_FWVERS_LEN 32
+ #define ETHTOOL_BUSINFO_LEN 32
+-/* these strings are set to whatever the driver author decides... */
++
++/**
++ * struct ethtool_drvinfo - general driver and device information
++ * @cmd: Command number = %ETHTOOL_GDRVINFO
++ * @driver: Driver short name. This should normally match the name
++ * in its bus driver structure (e.g. pci_driver::name). Must
++ * not be an empty string.
++ * @version: Driver version string; may be an empty string
++ * @fw_version: Firmware version string; may be an empty string
++ * @bus_info: Device bus address. This should match the dev_name()
++ * string for the underlying bus device, if there is one. May be
++ * an empty string.
++ * @n_priv_flags: Number of flags valid for %ETHTOOL_GPFLAGS and
++ * %ETHTOOL_SPFLAGS commands; also the number of strings in the
++ * %ETH_SS_PRIV_FLAGS set
++ * @n_stats: Number of u64 statistics returned by the %ETHTOOL_GSTATS
++ * command; also the number of strings in the %ETH_SS_STATS set
++ * @testinfo_len: Number of results returned by the %ETHTOOL_TEST
++ * command; also the number of strings in the %ETH_SS_TEST set
++ * @eedump_len: Size of EEPROM accessible through the %ETHTOOL_GEEPROM
++ * and %ETHTOOL_SEEPROM commands, in bytes
++ * @regdump_len: Size of register dump returned by the %ETHTOOL_GREGS
++ * command, in bytes
++ *
++ * Users can use the %ETHTOOL_GSSET_INFO command to get the number of
++ * strings in any string set (from Linux 2.6.34).
++ *
++ * Drivers should set at most @driver, @version, @fw_version and
++ * @bus_info in their get_drvinfo() implementation. The ethtool
++ * core fills in the other fields using other driver operations.
++ */
+ struct ethtool_drvinfo {
+ __u32 cmd;
+- char driver[32]; /* driver short name, "tulip", "eepro100" */
+- char version[32]; /* driver version string */
+- char fw_version[ETHTOOL_FWVERS_LEN]; /* firmware version string */
+- char bus_info[ETHTOOL_BUSINFO_LEN]; /* Bus info for this IF. */
+- /* For PCI devices, use pci_name(pci_dev). */
++ char driver[32];
++ char version[32];
++ char fw_version[ETHTOOL_FWVERS_LEN];
++ char bus_info[ETHTOOL_BUSINFO_LEN];
+ char reserved1[32];
+ char reserved2[12];
+- /*
+- * Some struct members below are filled in
+- * using ops->get_sset_count(). Obtaining
+- * this info from ethtool_drvinfo is now
+- * deprecated; Use ETHTOOL_GSSET_INFO
+- * instead.
+- */
+- __u32 n_priv_flags; /* number of flags valid in ETHTOOL_GPFLAGS */
+- __u32 n_stats; /* number of u64's from ETHTOOL_GSTATS */
++ __u32 n_priv_flags;
++ __u32 n_stats;
+ __u32 testinfo_len;
+- __u32 eedump_len; /* Size of data from ETHTOOL_GEEPROM (bytes) */
+- __u32 regdump_len; /* Size of data from ETHTOOL_GREGS (bytes) */
++ __u32 eedump_len;
++ __u32 regdump_len;
+ };
+
+ #define SOPASS_MAX 6
+-/* wake-on-lan settings */
++
++/**
++ * struct ethtool_wolinfo - Wake-On-Lan configuration
++ * @cmd: Command number = %ETHTOOL_GWOL or %ETHTOOL_SWOL
++ * @supported: Bitmask of %WAKE_* flags for supported Wake-On-Lan modes.
++ * Read-only.
++ * @wolopts: Bitmask of %WAKE_* flags for enabled Wake-On-Lan modes.
++ * @sopass: SecureOn(tm) password; meaningful only if %WAKE_MAGICSECURE
++ * is set in @wolopts.
++ */
+ struct ethtool_wolinfo {
+ __u32 cmd;
+ __u32 supported;
+ __u32 wolopts;
+- __u8 sopass[SOPASS_MAX]; /* SecureOn(tm) password */
++ __u8 sopass[SOPASS_MAX];
+ };
+
+ /* for passing single values */
+@@ -118,20 +209,77 @@
+ __u32 data;
+ };
+
+-/* for passing big chunks of data */
++enum tunable_id {
++ ETHTOOL_ID_UNSPEC,
++ ETHTOOL_RX_COPYBREAK,
++};
++
++enum tunable_type_id {
++ ETHTOOL_TUNABLE_UNSPEC,
++ ETHTOOL_TUNABLE_U8,
++ ETHTOOL_TUNABLE_U16,
++ ETHTOOL_TUNABLE_U32,
++ ETHTOOL_TUNABLE_U64,
++ ETHTOOL_TUNABLE_STRING,
++ ETHTOOL_TUNABLE_S8,
++ ETHTOOL_TUNABLE_S16,
++ ETHTOOL_TUNABLE_S32,
++ ETHTOOL_TUNABLE_S64,
++};
++
++struct ethtool_tunable {
++ __u32 cmd;
++ __u32 id;
++ __u32 type_id;
++ __u32 len;
++ void *data[0];
++};
++
++/**
++ * struct ethtool_regs - hardware register dump
++ * @cmd: Command number = %ETHTOOL_GREGS
++ * @version: Dump format version. This is driver-specific and may
++ * distinguish different chips/revisions. Drivers must use new
++ * version numbers whenever the dump format changes in an
++ * incompatible way.
++ * @len: On entry, the real length of @data. On return, the number of
++ * bytes used.
++ * @data: Buffer for the register dump
++ *
++ * Users should use %ETHTOOL_GDRVINFO to find the maximum length of
++ * a register dump for the interface. They must allocate the buffer
++ * immediately following this structure.
++ */
+ struct ethtool_regs {
+ __u32 cmd;
+- __u32 version; /* driver-specific, indicates different chips/revs */
+- __u32 len; /* bytes */
++ __u32 version;
++ __u32 len;
+ __u8 data[0];
+ };
+
+-/* for passing EEPROM chunks */
++/**
++ * struct ethtool_eeprom - EEPROM dump
++ * @cmd: Command number = %ETHTOOL_GEEPROM, %ETHTOOL_GMODULEEEPROM or
++ * %ETHTOOL_SEEPROM
++ * @magic: A 'magic cookie' value to guard against accidental changes.
++ * The value passed in to %ETHTOOL_SEEPROM must match the value
++ * returned by %ETHTOOL_GEEPROM for the same device. This is
++ * unused when @cmd is %ETHTOOL_GMODULEEEPROM.
++ * @offset: Offset within the EEPROM to begin reading/writing, in bytes
++ * @len: On entry, number of bytes to read/write. On successful
++ * return, number of bytes actually read/written. In case of
++ * error, this may indicate at what point the error occurred.
++ * @data: Buffer to read/write from
++ *
++ * Users may use %ETHTOOL_GDRVINFO or %ETHTOOL_GMODULEINFO to find
++ * the length of an on-board or module EEPROM, respectively. They
++ * must allocate the buffer immediately following this structure.
++ */
+ struct ethtool_eeprom {
+ __u32 cmd;
+ __u32 magic;
+- __u32 offset; /* in bytes */
+- __u32 len; /* in bytes */
++ __u32 offset;
++ __u32 len;
+ __u8 data[0];
+ };
+
+@@ -229,17 +377,18 @@
+ * @rate_sample_interval: How often to do adaptive coalescing packet rate
+ * sampling, measured in seconds. Must not be zero.
+ *
+- * Each pair of (usecs, max_frames) fields specifies this exit
+- * condition for interrupt coalescing:
++ * Each pair of (usecs, max_frames) fields specifies that interrupts
++ * should be coalesced until
+ * (usecs > 0 && time_since_first_completion >= usecs) ||
+ * (max_frames > 0 && completed_frames >= max_frames)
++ *
+ * It is illegal to set both usecs and max_frames to zero as this
+ * would cause interrupts to never be generated. To disable
+ * coalescing, set usecs = 0 and max_frames = 1.
+ *
+ * Some implementations ignore the value of max_frames and use the
+- * condition:
+- * time_since_first_completion >= usecs
++ * condition time_since_first_completion >= usecs
++ *
+ * This is deprecated. Drivers for hardware that does not support
+ * counting completions should validate that max_frames == !rx_usecs.
+ *
+@@ -279,22 +428,37 @@
+ __u32 rate_sample_interval;
+ };
+
+-/* for configuring RX/TX ring parameters */
++/**
++ * struct ethtool_ringparam - RX/TX ring parameters
++ * @cmd: Command number = %ETHTOOL_GRINGPARAM or %ETHTOOL_SRINGPARAM
++ * @rx_max_pending: Maximum supported number of pending entries per
++ * RX ring. Read-only.
++ * @rx_mini_max_pending: Maximum supported number of pending entries
++ * per RX mini ring. Read-only.
++ * @rx_jumbo_max_pending: Maximum supported number of pending entries
++ * per RX jumbo ring. Read-only.
++ * @tx_max_pending: Maximum supported number of pending entries per
++ * TX ring. Read-only.
++ * @rx_pending: Current maximum number of pending entries per RX ring
++ * @rx_mini_pending: Current maximum number of pending entries per RX
++ * mini ring
++ * @rx_jumbo_pending: Current maximum number of pending entries per RX
++ * jumbo ring
++ * @tx_pending: Current maximum supported number of pending entries
++ * per TX ring
++ *
++ * If the interface does not have separate RX mini and/or jumbo rings,
++ * @rx_mini_max_pending and/or @rx_jumbo_max_pending will be 0.
++ *
++ * There may also be driver-dependent minimum values for the number
++ * of entries per ring.
++ */
+ struct ethtool_ringparam {
+- __u32 cmd; /* ETHTOOL_{G,S}RINGPARAM */
+-
+- /* Read only attributes. These indicate the maximum number
+- * of pending RX/TX ring entries the driver will allow the
+- * user to set.
+- */
++ __u32 cmd;
+ __u32 rx_max_pending;
+ __u32 rx_mini_max_pending;
+ __u32 rx_jumbo_max_pending;
+ __u32 tx_max_pending;
+-
+- /* Values changeable by the user. The valid values are
+- * in the range 1 to the "*_max_pending" counterpart above.
+- */
+ __u32 rx_pending;
+ __u32 rx_mini_pending;
+ __u32 rx_jumbo_pending;
+@@ -329,51 +493,96 @@
+ __u32 combined_count;
+ };
+
+-/* for configuring link flow control parameters */
++/**
++ * struct ethtool_pauseparam - Ethernet pause (flow control) parameters
++ * @cmd: Command number = %ETHTOOL_GPAUSEPARAM or %ETHTOOL_SPAUSEPARAM
++ * @autoneg: Flag to enable autonegotiation of pause frame use
++ * @rx_pause: Flag to enable reception of pause frames
++ * @tx_pause: Flag to enable transmission of pause frames
++ *
++ * Drivers should reject a non-zero setting of @autoneg when
++ * autoneogotiation is disabled (or not supported) for the link.
++ *
++ * If the link is autonegotiated, drivers should use
++ * mii_advertise_flowctrl() or similar code to set the advertised
++ * pause frame capabilities based on the @rx_pause and @tx_pause flags,
++ * even if @autoneg is zero. They should also allow the advertised
++ * pause frame capabilities to be controlled directly through the
++ * advertising field of &struct ethtool_cmd.
++ *
++ * If @autoneg is non-zero, the MAC is configured to send and/or
++ * receive pause frames according to the result of autonegotiation.
++ * Otherwise, it is configured directly based on the @rx_pause and
++ * @tx_pause flags.
++ */
+ struct ethtool_pauseparam {
+- __u32 cmd; /* ETHTOOL_{G,S}PAUSEPARAM */
+-
+- /* If the link is being auto-negotiated (via ethtool_cmd.autoneg
+- * being true) the user may set 'autoneg' here non-zero to have the
+- * pause parameters be auto-negotiated too. In such a case, the
+- * {rx,tx}_pause values below determine what capabilities are
+- * advertised.
+- *
+- * If 'autoneg' is zero or the link is not being auto-negotiated,
+- * then {rx,tx}_pause force the driver to use/not-use pause
+- * flow control.
+- */
++ __u32 cmd;
+ __u32 autoneg;
+ __u32 rx_pause;
+ __u32 tx_pause;
+ };
+
+ #define ETH_GSTRING_LEN 32
++
++/**
++ * enum ethtool_stringset - string set ID
++ * @ETH_SS_TEST: Self-test result names, for use with %ETHTOOL_TEST
++ * @ETH_SS_STATS: Statistic names, for use with %ETHTOOL_GSTATS
++ * @ETH_SS_PRIV_FLAGS: Driver private flag names, for use with
++ * %ETHTOOL_GPFLAGS and %ETHTOOL_SPFLAGS
++ * @ETH_SS_NTUPLE_FILTERS: Previously used with %ETHTOOL_GRXNTUPLE;
++ * now deprecated
++ * @ETH_SS_FEATURES: Device feature names
++ */
+ enum ethtool_stringset {
+ ETH_SS_TEST = 0,
+ ETH_SS_STATS,
+ ETH_SS_PRIV_FLAGS,
+- ETH_SS_NTUPLE_FILTERS, /* Do not use, GRXNTUPLE is now deprecated */
++ ETH_SS_NTUPLE_FILTERS,
+ ETH_SS_FEATURES,
+ };
+
+-/* for passing string sets for data tagging */
++/**
++ * struct ethtool_gstrings - string set for data tagging
++ * @cmd: Command number = %ETHTOOL_GSTRINGS
++ * @string_set: String set ID; one of &enum ethtool_stringset
++ * @len: On return, the number of strings in the string set
++ * @data: Buffer for strings. Each string is null-padded to a size of
++ * %ETH_GSTRING_LEN.
++ *
++ * Users must use %ETHTOOL_GSSET_INFO to find the number of strings in
++ * the string set. They must allocate a buffer of the appropriate
++ * size immediately following this structure.
++ */
+ struct ethtool_gstrings {
+- __u32 cmd; /* ETHTOOL_GSTRINGS */
+- __u32 string_set; /* string set id e.c. ETH_SS_TEST, etc*/
+- __u32 len; /* number of strings in the string set */
++ __u32 cmd;
++ __u32 string_set;
++ __u32 len;
+ __u8 data[0];
+ };
+
++/**
++ * struct ethtool_sset_info - string set information
++ * @cmd: Command number = %ETHTOOL_GSSET_INFO
++ * @sset_mask: On entry, a bitmask of string sets to query, with bits
++ * numbered according to &enum ethtool_stringset. On return, a
++ * bitmask of those string sets queried that are supported.
++ * @data: Buffer for string set sizes. On return, this contains the
++ * size of each string set that was queried and supported, in
++ * order of ID.
++ *
++ * Example: The user passes in @sset_mask = 0x7 (sets 0, 1, 2) and on
++ * return @sset_mask == 0x6 (sets 1, 2). Then @data[0] contains the
++ * size of set 1 and @data[1] contains the size of set 2.
++ *
++ * Users must allocate a buffer of the appropriate size (4 * number of
++ * sets queried) immediately following this structure.
++ */
+ struct ethtool_sset_info {
+- __u32 cmd; /* ETHTOOL_GSSET_INFO */
++ __u32 cmd;
+ __u32 reserved;
+- __u64 sset_mask; /* input: each bit selects an sset to query */
+- /* output: each bit a returned sset */
+- __u32 data[0]; /* ETH_SS_xxx count, in order, based on bits
+- in sset_mask. One bit implies one
+- __u32, two bits implies two
+- __u32's, etc. */
++ __u64 sset_mask;
++ __u32 data[0];
+ };
+
+ /**
+@@ -393,24 +602,58 @@
+ ETH_TEST_FL_EXTERNAL_LB_DONE = (1 << 3),
+ };
+
+-/* for requesting NIC test and getting results*/
++/**
++ * struct ethtool_test - device self-test invocation
++ * @cmd: Command number = %ETHTOOL_TEST
++ * @flags: A bitmask of flags from &enum ethtool_test_flags. Some
++ * flags may be set by the user on entry; others may be set by
++ * the driver on return.
++ * @len: On return, the number of test results
++ * @data: Array of test results
++ *
++ * Users must use %ETHTOOL_GSSET_INFO or %ETHTOOL_GDRVINFO to find the
++ * number of test results that will be returned. They must allocate a
++ * buffer of the appropriate size (8 * number of results) immediately
++ * following this structure.
++ */
+ struct ethtool_test {
+- __u32 cmd; /* ETHTOOL_TEST */
+- __u32 flags; /* ETH_TEST_FL_xxx */
++ __u32 cmd;
++ __u32 flags;
+ __u32 reserved;
+- __u32 len; /* result length, in number of u64 elements */
++ __u32 len;
+ __u64 data[0];
+ };
+
+-/* for dumping NIC-specific statistics */
++/**
++ * struct ethtool_stats - device-specific statistics
++ * @cmd: Command number = %ETHTOOL_GSTATS
++ * @n_stats: On return, the number of statistics
++ * @data: Array of statistics
++ *
++ * Users must use %ETHTOOL_GSSET_INFO or %ETHTOOL_GDRVINFO to find the
++ * number of statistics that will be returned. They must allocate a
++ * buffer of the appropriate size (8 * number of statistics)
++ * immediately following this structure.
++ */
+ struct ethtool_stats {
+- __u32 cmd; /* ETHTOOL_GSTATS */
+- __u32 n_stats; /* number of u64's being returned */
++ __u32 cmd;
++ __u32 n_stats;
+ __u64 data[0];
+ };
+
++/**
++ * struct ethtool_perm_addr - permanent hardware address
++ * @cmd: Command number = %ETHTOOL_GPERMADDR
++ * @size: On entry, the size of the buffer. On return, the size of the
++ * address. The command fails if the buffer is too small.
++ * @data: Buffer for the address
++ *
++ * Users must allocate the buffer immediately following this structure.
++ * A buffer size of %MAX_ADDR_LEN should be sufficient for any address
++ * type.
++ */
+ struct ethtool_perm_addr {
+- __u32 cmd; /* ETHTOOL_GPERMADDR */
++ __u32 cmd;
+ __u32 size;
+ __u8 data[0];
+ };
+@@ -593,7 +836,7 @@
+ * %ETHTOOL_SRXCLSRLINS may add the rule at any suitable unused
+ * location, and may remove a rule at a later location (lower
+ * priority) that matches exactly the same set of flows. The special
+- * values are: %RX_CLS_LOC_ANY, selecting any location;
++ * values are %RX_CLS_LOC_ANY, selecting any location;
+ * %RX_CLS_LOC_FIRST, selecting the first suitable location (maximum
+ * priority); and %RX_CLS_LOC_LAST, selecting the last suitable
+ * location (minimum priority). Additional special values may be
+@@ -630,6 +873,38 @@
+ };
+
+ /**
++ * struct ethtool_rxfh - command to get/set RX flow hash indir or/and hash key.
++ * @cmd: Specific command number - %ETHTOOL_GRSSH or %ETHTOOL_SRSSH
++ * @rss_context: RSS context identifier.
++ * @indir_size: On entry, the array size of the user buffer for the
++ * indirection table, which may be zero, or (for %ETHTOOL_SRSSH),
++ * %ETH_RXFH_INDIR_NO_CHANGE. On return from %ETHTOOL_GRSSH,
++ * the array size of the hardware indirection table.
++ * @key_size: On entry, the array size of the user buffer for the hash key,
++ * which may be zero. On return from %ETHTOOL_GRSSH, the size of the
++ * hardware hash key.
++ * @rsvd: Reserved for future extensions.
++ * @rss_config: RX ring/queue index for each hash value i.e., indirection table
++ * of @indir_size __u32 elements, followed by hash key of @key_size
++ * bytes.
++ *
++ * For %ETHTOOL_GRSSH, a @indir_size and key_size of zero means that only the
++ * size should be returned. For %ETHTOOL_SRSSH, an @indir_size of
++ * %ETH_RXFH_INDIR_NO_CHANGE means that indir table setting is not requested
++ * and a @indir_size of zero means the indir table should be reset to default
++ * values.
++ */
++struct ethtool_rxfh {
++ __u32 cmd;
++ __u32 rss_context;
++ __u32 indir_size;
++ __u32 key_size;
++ __u32 rsvd[2];
++ __u32 rss_config[0];
++};
++#define ETH_RXFH_INDIR_NO_CHANGE 0xffffffff
++
++/**
+ * struct ethtool_rx_ntuple_flow_spec - specification for RX flow filter
+ * @flow_type: Type of match to perform, e.g. %TCP_V4_FLOW
+ * @h_u: Flow field values to match (dependent on @flow_type)
+@@ -704,9 +979,6 @@
+ * for %ETHTOOL_GET_DUMP_FLAG command
+ * @data: data collected for get dump data operation
+ */
+-
+-#define ETH_FW_DUMP_DISABLE 0
+-
+ struct ethtool_dump {
+ __u32 cmd;
+ __u32 version;
+@@ -715,6 +987,8 @@
+ __u8 data[0];
+ };
+
++#define ETH_FW_DUMP_DISABLE 0
++
+ /* for returning and changing feature sets */
+
+ /**
+@@ -734,8 +1008,9 @@
+ /**
+ * struct ethtool_gfeatures - command to get state of device's features
+ * @cmd: command number = %ETHTOOL_GFEATURES
+- * @size: in: number of elements in the features[] array;
+- * out: number of elements in features[] needed to hold all features
++ * @size: On entry, the number of elements in the features[] array;
++ * on return, the number of elements in features[] needed to hold
++ * all features
+ * @features: state of features
+ */
+ struct ethtool_gfeatures {
+@@ -901,11 +1176,15 @@
+ #define ETHTOOL_GEEE 0x00000044 /* Get EEE settings */
+ #define ETHTOOL_SEEE 0x00000045 /* Set EEE settings */
+
++#define ETHTOOL_GRSSH 0x00000046 /* Get RX flow hash configuration */
++#define ETHTOOL_SRSSH 0x00000047 /* Set RX flow hash configuration */
++#define ETHTOOL_GTUNABLE 0x00000048 /* Get tunable configuration */
++#define ETHTOOL_STUNABLE 0x00000049 /* Set tunable configuration */
++
+ /* compatibility with older code */
+ #define SPARC_ETH_GSET ETHTOOL_GSET
+ #define SPARC_ETH_SSET ETHTOOL_SSET
+
+-/* Indicates what features are supported by the interface. */
+ #define SUPPORTED_10baseT_Half (1 << 0)
+ #define SUPPORTED_10baseT_Full (1 << 1)
+ #define SUPPORTED_100baseT_Half (1 << 2)
+@@ -934,7 +1213,6 @@
+ #define SUPPORTED_40000baseSR4_Full (1 << 25)
+ #define SUPPORTED_40000baseLR4_Full (1 << 26)
+
+-/* Indicates what features are advertised by the interface. */
+ #define ADVERTISED_10baseT_Half (1 << 0)
+ #define ADVERTISED_10baseT_Full (1 << 1)
+ #define ADVERTISED_100baseT_Half (1 << 2)
+@@ -999,9 +1277,7 @@
+ #define XCVR_DUMMY2 0x03
+ #define XCVR_DUMMY3 0x04
+
+-/* Enable or disable autonegotiation. If this is set to enable,
+- * the forced link modes above are completely ignored.
+- */
++/* Enable or disable autonegotiation. */
+ #define AUTONEG_DISABLE 0x00
+ #define AUTONEG_ENABLE 0x01
+
+diff -Nur linux-3.14.72.orig/include/uapi/linux/fb.h linux-3.14.72/include/uapi/linux/fb.h
+--- linux-3.14.72.orig/include/uapi/linux/fb.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/fb.h 2016-06-19 22:11:55.509126621 +0200
+@@ -220,6 +220,7 @@
+ #define FB_VMODE_INTERLACED 1 /* interlaced */
+ #define FB_VMODE_DOUBLE 2 /* double scan */
+ #define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */
++#define FB_VMODE_FRACTIONAL 8
+ #define FB_VMODE_MASK 255
+
+ #define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
+diff -Nur linux-3.14.72.orig/include/uapi/linux/ipu.h linux-3.14.72/include/uapi/linux/ipu.h
+--- linux-3.14.72.orig/include/uapi/linux/ipu.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/ipu.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,282 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @defgroup IPU MXC Image Processing Unit (IPU) Driver
++ */
++/*!
++ * @file uapi/linux/ipu.h
++ *
++ * @brief This file contains the IPU driver API declarations.
++ *
++ * @ingroup IPU
++ */
++
++#ifndef __ASM_ARCH_IPU_H__
++#define __ASM_ARCH_IPU_H__
++
++#include <linux/types.h>
++#include <linux/videodev2.h>
++
++#ifndef __KERNEL__
++#ifndef __cplusplus
++typedef unsigned char bool;
++#endif
++#define irqreturn_t int
++#define dma_addr_t int
++#define uint32_t unsigned int
++#define uint16_t unsigned short
++#define uint8_t unsigned char
++#define u32 unsigned int
++#define u8 unsigned char
++#define __u32 u32
++#endif
++
++/*!
++ * Enumeration of IPU rotation modes
++ */
++typedef enum {
++ /* Note the enum values correspond to BAM value */
++ IPU_ROTATE_NONE = 0,
++ IPU_ROTATE_VERT_FLIP = 1,
++ IPU_ROTATE_HORIZ_FLIP = 2,
++ IPU_ROTATE_180 = 3,
++ IPU_ROTATE_90_RIGHT = 4,
++ IPU_ROTATE_90_RIGHT_VFLIP = 5,
++ IPU_ROTATE_90_RIGHT_HFLIP = 6,
++ IPU_ROTATE_90_LEFT = 7,
++} ipu_rotate_mode_t;
++
++/*!
++ * Enumeration of VDI MOTION select
++ */
++typedef enum {
++ MED_MOTION = 0,
++ LOW_MOTION = 1,
++ HIGH_MOTION = 2,
++} ipu_motion_sel;
++
++/*!
++ * Enumeration of DI ports for ADC.
++ */
++typedef enum {
++ DISP0,
++ DISP1,
++ DISP2,
++ DISP3
++} display_port_t;
++
++/* IPU Pixel format definitions */
++/* Four-character-code (FOURCC) */
++#define fourcc(a, b, c, d)\
++ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
++
++/*!
++ * @name IPU Pixel Formats
++ *
++ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
++ * the same used by V4L2 API.
++ */
++
++/*! @{ */
++/*! @name Generic or Raw Data Formats */
++/*! @{ */
++#define IPU_PIX_FMT_GENERIC fourcc('I', 'P', 'U', '0') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_GENERIC_32 fourcc('I', 'P', 'U', '1') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_GENERIC_16 fourcc('I', 'P', 'U', '2') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_LVDS666 fourcc('L', 'V', 'D', '6') /*!< IPU Generic Data */
++#define IPU_PIX_FMT_LVDS888 fourcc('L', 'V', 'D', '8') /*!< IPU Generic Data */
++/*! @} */
++/*! @name RGB Formats */
++/*! @{ */
++#define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
++#define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
++#define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */
++#define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
++#define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
++#define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
++#define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
++#define IPU_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */
++#define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
++#define IPU_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
++#define IPU_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
++#define IPU_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
++#define IPU_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
++/*! @} */
++/*! @name YUV Interleaved Formats */
++/*! @{ */
++#define IPU_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
++#define IPU_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
++#define IPU_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */
++#define IPU_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */
++#define IPU_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
++#define IPU_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */
++#define IPU_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */
++/* two planes -- one Y, one Cb + Cr interleaved */
++#define IPU_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
++/* two planes -- 12 tiled Y/CbCr 4:2:0 */
++#define IPU_PIX_FMT_TILED_NV12 fourcc('T', 'N', 'V', 'P')
++#define IPU_PIX_FMT_TILED_NV12F fourcc('T', 'N', 'V', 'F')
++
++/*! @} */
++/*! @name YUV Planar Formats */
++/*! @{ */
++#define IPU_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */
++#define IPU_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */
++#define IPU_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */
++#define IPU_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */
++#define IPU_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */
++#define IPU_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
++#define IPU_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */
++#define IPU_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
++/* non-interleaved 4:4:4 */
++#define IPU_PIX_FMT_YUV444P fourcc('4', '4', '4', 'P') /*!< 24 YUV 4:4:4 */
++/*! @} */
++#define IPU_PIX_FMT_TILED_NV12_MBALIGN (16)
++#define TILED_NV12_FRAME_SIZE(w, h) \
++ (ALIGN((w) * (h), SZ_4K) + ALIGN((w) * (h) / 2, SZ_4K))
++/* IPU device */
++typedef enum {
++ RGB_CS,
++ YUV_CS,
++ NULL_CS
++} cs_t;
++
++struct ipu_pos {
++ u32 x;
++ u32 y;
++};
++
++struct ipu_crop {
++ struct ipu_pos pos;
++ u32 w;
++ u32 h;
++};
++
++struct ipu_deinterlace {
++ bool enable;
++ u8 motion; /*see ipu_motion_sel*/
++#define IPU_DEINTERLACE_FIELD_TOP 0
++#define IPU_DEINTERLACE_FIELD_BOTTOM 1
++#define IPU_DEINTERLACE_FIELD_MASK \
++ (IPU_DEINTERLACE_FIELD_TOP | IPU_DEINTERLACE_FIELD_BOTTOM)
++ /* deinterlace frame rate double flags */
++#define IPU_DEINTERLACE_RATE_EN 0x80
++#define IPU_DEINTERLACE_RATE_FRAME1 0x40
++#define IPU_DEINTERLACE_RATE_MASK \
++ (IPU_DEINTERLACE_RATE_EN | IPU_DEINTERLACE_RATE_FRAME1)
++#define IPU_DEINTERLACE_MAX_FRAME 2
++ u8 field_fmt;
++};
++
++struct ipu_input {
++ u32 width;
++ u32 height;
++ u32 format;
++ struct ipu_crop crop;
++ dma_addr_t paddr;
++
++ struct ipu_deinterlace deinterlace;
++ dma_addr_t paddr_n; /*valid when deinterlace enable*/
++};
++
++struct ipu_alpha {
++#define IPU_ALPHA_MODE_GLOBAL 0
++#define IPU_ALPHA_MODE_LOCAL 1
++ u8 mode;
++ u8 gvalue; /* 0~255 */
++ dma_addr_t loc_alp_paddr;
++};
++
++struct ipu_colorkey {
++ bool enable;
++ u32 value; /* RGB 24bit */
++};
++
++struct ipu_overlay {
++ u32 width;
++ u32 height;
++ u32 format;
++ struct ipu_crop crop;
++ struct ipu_alpha alpha;
++ struct ipu_colorkey colorkey;
++ dma_addr_t paddr;
++};
++
++struct ipu_output {
++ u32 width;
++ u32 height;
++ u32 format;
++ u8 rotate;
++ struct ipu_crop crop;
++ dma_addr_t paddr;
++};
++
++struct ipu_task {
++ struct ipu_input input;
++ struct ipu_output output;
++
++ bool overlay_en;
++ struct ipu_overlay overlay;
++
++#define IPU_TASK_PRIORITY_NORMAL 0
++#define IPU_TASK_PRIORITY_HIGH 1
++ u8 priority;
++
++#define IPU_TASK_ID_ANY 0
++#define IPU_TASK_ID_VF 1
++#define IPU_TASK_ID_PP 2
++#define IPU_TASK_ID_MAX 3
++ u8 task_id;
++
++ int timeout;
++};
++
++enum {
++ IPU_CHECK_OK = 0,
++ IPU_CHECK_WARN_INPUT_OFFS_NOT8ALIGN = 0x1,
++ IPU_CHECK_WARN_OUTPUT_OFFS_NOT8ALIGN = 0x2,
++ IPU_CHECK_WARN_OVERLAY_OFFS_NOT8ALIGN = 0x4,
++ IPU_CHECK_ERR_MIN,
++ IPU_CHECK_ERR_INPUT_CROP,
++ IPU_CHECK_ERR_OUTPUT_CROP,
++ IPU_CHECK_ERR_OVERLAY_CROP,
++ IPU_CHECK_ERR_INPUT_OVER_LIMIT,
++ IPU_CHECK_ERR_OV_OUT_NO_FIT,
++ IPU_CHECK_ERR_OVERLAY_WITH_VDI,
++ IPU_CHECK_ERR_PROC_NO_NEED,
++ IPU_CHECK_ERR_SPLIT_INPUTW_OVER,
++ IPU_CHECK_ERR_SPLIT_INPUTH_OVER,
++ IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER,
++ IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER,
++ IPU_CHECK_ERR_SPLIT_WITH_ROT,
++ IPU_CHECK_ERR_NOT_SUPPORT,
++ IPU_CHECK_ERR_NOT16ALIGN,
++ IPU_CHECK_ERR_W_DOWNSIZE_OVER,
++ IPU_CHECK_ERR_H_DOWNSIZE_OVER,
++};
++
++/* IOCTL commands */
++#define IPU_CHECK_TASK _IOWR('I', 0x1, struct ipu_task)
++#define IPU_QUEUE_TASK _IOW('I', 0x2, struct ipu_task)
++#define IPU_ALLOC _IOWR('I', 0x3, int)
++#define IPU_FREE _IOW('I', 0x4, int)
++
++#endif
+diff -Nur linux-3.14.72.orig/include/uapi/linux/isl29023.h linux-3.14.72/include/uapi/linux/isl29023.h
+--- linux-3.14.72.orig/include/uapi/linux/isl29023.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/isl29023.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,47 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __UAPI_LINUX_ISL29023_H__
++#define __UAPI_LINUX_ISL29023_H__
++
++#include <linux/types.h>
++
++#define ISL29023_PD_MODE 0x0
++#define ISL29023_ALS_ONCE_MODE 0x1
++#define ISL29023_IR_ONCE_MODE 0x2
++#define ISL29023_ALS_CONT_MODE 0x5
++#define ISL29023_IR_CONT_MODE 0x6
++
++#define ISL29023_INT_PERSISTS_1 0x0
++#define ISL29023_INT_PERSISTS_4 0x1
++#define ISL29023_INT_PERSISTS_8 0x2
++#define ISL29023_INT_PERSISTS_16 0x3
++
++#define ISL29023_RES_16 0x0
++#define ISL29023_RES_12 0x1
++#define ISL29023_RES_8 0x2
++#define ISL29023_RES_4 0x3
++
++#define ISL29023_RANGE_1K 0x0
++#define ISL29023_RANGE_4K 0x1
++#define ISL29023_RANGE_16K 0x2
++#define ISL29023_RANGE_64K 0x3
++
++#endif
+diff -Nur linux-3.14.72.orig/include/uapi/linux/Kbuild linux-3.14.72/include/uapi/linux/Kbuild
+--- linux-3.14.72.orig/include/uapi/linux/Kbuild 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/Kbuild 2016-06-19 22:11:55.509126621 +0200
+@@ -226,6 +226,7 @@
+ header-y += kvm_para.h
+ endif
+
++header-y += ipu.h
+ header-y += l2tp.h
+ header-y += libc-compat.h
+ header-y += limits.h
+@@ -238,6 +239,7 @@
+ header-y += matroxfb.h
+ header-y += mdio.h
+ header-y += media.h
++header-y += media-bus-format.h
+ header-y += mei.h
+ header-y += mempolicy.h
+ header-y += meye.h
+@@ -253,6 +255,10 @@
+ header-y += msdos_fs.h
+ header-y += msg.h
+ header-y += mtio.h
++header-y += mxcfb.h
++header-y += mxc_v4l2.h
++header-y += mxc_dcic.h
++header-y += ipu.h
+ header-y += n_r3964.h
+ header-y += nbd.h
+ header-y += ncp.h
+@@ -318,6 +324,8 @@
+ header-y += prctl.h
+ header-y += ptp_clock.h
+ header-y += ptrace.h
++header-y += pxp_dma.h
++header-y += pxp_device.h
+ header-y += qnx4_fs.h
+ header-y += qnxtypes.h
+ header-y += quota.h
+diff -Nur linux-3.14.72.orig/include/uapi/linux/media-bus-format.h linux-3.14.72/include/uapi/linux/media-bus-format.h
+--- linux-3.14.72.orig/include/uapi/linux/media-bus-format.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/media-bus-format.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,125 @@
++/*
++ * Media Bus API header
++ *
++ * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#ifndef __LINUX_MEDIA_BUS_FORMAT_H
++#define __LINUX_MEDIA_BUS_FORMAT_H
++
++/*
++ * These bus formats uniquely identify data formats on the data bus. Format 0
++ * is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where
++ * the data format is fixed. Additionally, "2X8" means that one pixel is
++ * transferred in two 8-bit samples, "BE" or "LE" specify in which order those
++ * samples are transferred over the bus: "LE" means that the least significant
++ * bits are transferred first, "BE" means that the most significant bits are
++ * transferred first, and "PADHI" and "PADLO" define which bits - low or high,
++ * in the incomplete high byte, are filled with padding bits.
++ *
++ * The bus formats are grouped by type, bus_width, bits per component, samples
++ * per pixel and order of subsamples. Numerical values are sorted using generic
++ * numerical sort order (8 thus comes before 10).
++ *
++ * As their value can't change when a new bus format is inserted in the
++ * enumeration, the bus formats are explicitly given a numerical value. The next
++ * free values for each category are listed below, update them when inserting
++ * new pixel codes.
++ */
++
++#define MEDIA_BUS_FMT_FIXED 0x0001
++
++/* RGB - next is 0x100e */
++#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001
++#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002
++#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003
++#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004
++#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005
++#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006
++#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007
++#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008
++#define MEDIA_BUS_FMT_RGB666_1X18 0x1009
++#define MEDIA_BUS_FMT_RGB888_1X24 0x100a
++#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b
++#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c
++#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d
++
++/* YUV (including grey) - next is 0x2024 */
++#define MEDIA_BUS_FMT_Y8_1X8 0x2001
++#define MEDIA_BUS_FMT_UV8_1X8 0x2015
++#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002
++#define MEDIA_BUS_FMT_VYUY8_1_5X8 0x2003
++#define MEDIA_BUS_FMT_YUYV8_1_5X8 0x2004
++#define MEDIA_BUS_FMT_YVYU8_1_5X8 0x2005
++#define MEDIA_BUS_FMT_UYVY8_2X8 0x2006
++#define MEDIA_BUS_FMT_VYUY8_2X8 0x2007
++#define MEDIA_BUS_FMT_YUYV8_2X8 0x2008
++#define MEDIA_BUS_FMT_YVYU8_2X8 0x2009
++#define MEDIA_BUS_FMT_Y10_1X10 0x200a
++#define MEDIA_BUS_FMT_UYVY10_2X10 0x2018
++#define MEDIA_BUS_FMT_VYUY10_2X10 0x2019
++#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b
++#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c
++#define MEDIA_BUS_FMT_Y12_1X12 0x2013
++#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f
++#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010
++#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011
++#define MEDIA_BUS_FMT_YVYU8_1X16 0x2012
++#define MEDIA_BUS_FMT_YDYUYDYV8_1X16 0x2014
++#define MEDIA_BUS_FMT_UYVY10_1X20 0x201a
++#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b
++#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d
++#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e
++#define MEDIA_BUS_FMT_YUV10_1X30 0x2016
++#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017
++#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c
++#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d
++#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e
++#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f
++#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020
++#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021
++#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022
++#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023
++
++/* Bayer - next is 0x3019 */
++#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001
++#define MEDIA_BUS_FMT_SGBRG8_1X8 0x3013
++#define MEDIA_BUS_FMT_SGRBG8_1X8 0x3002
++#define MEDIA_BUS_FMT_SRGGB8_1X8 0x3014
++#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8 0x3015
++#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8 0x3016
++#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8 0x3017
++#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8 0x3018
++#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 0x300b
++#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 0x300c
++#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 0x3009
++#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 0x300d
++#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE 0x3003
++#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE 0x3004
++#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE 0x3005
++#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE 0x3006
++#define MEDIA_BUS_FMT_SBGGR10_1X10 0x3007
++#define MEDIA_BUS_FMT_SGBRG10_1X10 0x300e
++#define MEDIA_BUS_FMT_SGRBG10_1X10 0x300a
++#define MEDIA_BUS_FMT_SRGGB10_1X10 0x300f
++#define MEDIA_BUS_FMT_SBGGR12_1X12 0x3008
++#define MEDIA_BUS_FMT_SGBRG12_1X12 0x3010
++#define MEDIA_BUS_FMT_SGRBG12_1X12 0x3011
++#define MEDIA_BUS_FMT_SRGGB12_1X12 0x3012
++
++/* JPEG compressed formats - next is 0x4002 */
++#define MEDIA_BUS_FMT_JPEG_1X8 0x4001
++
++/* Vendor specific formats - next is 0x5002 */
++
++/* S5C73M3 sensor specific interleaved UYVY and JPEG */
++#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8 0x5001
++
++/* HSV - next is 0x6002 */
++#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001
++
++#endif /* __LINUX_MEDIA_BUS_FORMAT_H */
+diff -Nur linux-3.14.72.orig/include/uapi/linux/mxc_asrc.h linux-3.14.72/include/uapi/linux/mxc_asrc.h
+--- linux-3.14.72.orig/include/uapi/linux/mxc_asrc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/mxc_asrc.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,126 @@
++/*
++ * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ *
++ * @file mxc_asrc.h
++ *
++ * @brief i.MX Asynchronous Sample Rate Converter
++ *
++ * @ingroup Audio
++ */
++
++#ifndef __MXC_ASRC_UAPI_H__
++#define __MXC_ASRC_UAPI_H__
++
++#define ASRC_IOC_MAGIC 'C'
++
++#define ASRC_REQ_PAIR _IOWR(ASRC_IOC_MAGIC, 0, struct asrc_req)
++#define ASRC_CONFIG_PAIR _IOWR(ASRC_IOC_MAGIC, 1, struct asrc_config)
++#define ASRC_RELEASE_PAIR _IOW(ASRC_IOC_MAGIC, 2, enum asrc_pair_index)
++#define ASRC_CONVERT _IOW(ASRC_IOC_MAGIC, 3, struct asrc_convert_buffer)
++#define ASRC_START_CONV _IOW(ASRC_IOC_MAGIC, 4, enum asrc_pair_index)
++#define ASRC_STOP_CONV _IOW(ASRC_IOC_MAGIC, 5, enum asrc_pair_index)
++#define ASRC_STATUS _IOW(ASRC_IOC_MAGIC, 6, struct asrc_status_flags)
++#define ASRC_FLUSH _IOW(ASRC_IOC_MAGIC, 7, enum asrc_pair_index)
++
++enum asrc_pair_index {
++ ASRC_INVALID_PAIR = -1,
++ ASRC_PAIR_A = 0,
++ ASRC_PAIR_B = 1,
++ ASRC_PAIR_C = 2,
++};
++
++#define ASRC_PAIR_MAX_NUM (ASRC_PAIR_C + 1)
++
++enum asrc_inclk {
++ INCLK_NONE = 0x03,
++ INCLK_ESAI_RX = 0x00,
++ INCLK_SSI1_RX = 0x01,
++ INCLK_SSI2_RX = 0x02,
++ INCLK_SSI3_RX = 0x07,
++ INCLK_SPDIF_RX = 0x04,
++ INCLK_MLB_CLK = 0x05,
++ INCLK_PAD = 0x06,
++ INCLK_ESAI_TX = 0x08,
++ INCLK_SSI1_TX = 0x09,
++ INCLK_SSI2_TX = 0x0a,
++ INCLK_SSI3_TX = 0x0b,
++ INCLK_SPDIF_TX = 0x0c,
++ INCLK_ASRCK1_CLK = 0x0f,
++};
++
++enum asrc_outclk {
++ OUTCLK_NONE = 0x03,
++ OUTCLK_ESAI_TX = 0x00,
++ OUTCLK_SSI1_TX = 0x01,
++ OUTCLK_SSI2_TX = 0x02,
++ OUTCLK_SSI3_TX = 0x07,
++ OUTCLK_SPDIF_TX = 0x04,
++ OUTCLK_MLB_CLK = 0x05,
++ OUTCLK_PAD = 0x06,
++ OUTCLK_ESAI_RX = 0x08,
++ OUTCLK_SSI1_RX = 0x09,
++ OUTCLK_SSI2_RX = 0x0a,
++ OUTCLK_SSI3_RX = 0x0b,
++ OUTCLK_SPDIF_RX = 0x0c,
++ OUTCLK_ASRCK1_CLK = 0x0f,
++};
++
++enum asrc_word_width {
++ ASRC_WIDTH_24_BIT = 0,
++ ASRC_WIDTH_16_BIT = 1,
++ ASRC_WIDTH_8_BIT = 2,
++};
++
++struct asrc_config {
++ enum asrc_pair_index pair;
++ unsigned int channel_num;
++ unsigned int buffer_num;
++ unsigned int dma_buffer_size;
++ unsigned int input_sample_rate;
++ unsigned int output_sample_rate;
++ enum asrc_word_width input_word_width;
++ enum asrc_word_width output_word_width;
++ enum asrc_inclk inclk;
++ enum asrc_outclk outclk;
++};
++
++struct asrc_req {
++ unsigned int chn_num;
++ enum asrc_pair_index index;
++};
++
++struct asrc_querybuf {
++ unsigned int buffer_index;
++ unsigned int input_length;
++ unsigned int output_length;
++ unsigned long input_offset;
++ unsigned long output_offset;
++};
++
++struct asrc_convert_buffer {
++ void *input_buffer_vaddr;
++ void *output_buffer_vaddr;
++ unsigned int input_buffer_length;
++ unsigned int output_buffer_length;
++};
++
++struct asrc_status_flags {
++ enum asrc_pair_index index;
++ unsigned int overload_error;
++};
++
++enum asrc_error_status {
++ ASRC_TASK_Q_OVERLOAD = 0x01,
++ ASRC_OUTPUT_TASK_OVERLOAD = 0x02,
++ ASRC_INPUT_TASK_OVERLOAD = 0x04,
++ ASRC_OUTPUT_BUFFER_OVERFLOW = 0x08,
++ ASRC_INPUT_BUFFER_UNDERRUN = 0x10,
++};
++#endif/* __MXC_ASRC_UAPI_H__ */
+diff -Nur linux-3.14.72.orig/include/uapi/linux/mxc_dcic.h linux-3.14.72/include/uapi/linux/mxc_dcic.h
+--- linux-3.14.72.orig/include/uapi/linux/mxc_dcic.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/mxc_dcic.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,49 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file uapi/linux/mxc_dcic.h
++ *
++ * @brief MXC DCIC private header file
++ *
++ * @ingroup MXC DCIC
++ */
++#ifndef __ASM_ARCH_MXC_DCIC_H__
++#define __ASM_ARCH_MXC_DCIC_H__
++
++#define DCIC_IOC_ALLOC_ROI_NUM _IO('D', 10)
++#define DCIC_IOC_FREE_ROI_NUM _IO('D', 11)
++#define DCIC_IOC_CONFIG_DCIC _IO('D', 12)
++#define DCIC_IOC_CONFIG_ROI _IO('D', 13)
++#define DCIC_IOC_GET_RESULT _IO('D', 14)
++#define DCIC_IOC_START_VSYNC _IO('D', 15)
++#define DCIC_IOC_STOP_VSYNC _IO('D', 16)
++
++struct roi_params {
++ unsigned int roi_n;
++ unsigned int ref_sig;
++ unsigned int start_y;
++ unsigned int start_x;
++ unsigned int end_y;
++ unsigned int end_x;
++ char freeze;
++};
++
++#endif
+diff -Nur linux-3.14.72.orig/include/uapi/linux/mxcfb.h linux-3.14.72/include/uapi/linux/mxcfb.h
+--- linux-3.14.72.orig/include/uapi/linux/mxcfb.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/mxcfb.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,176 @@
++/*
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*
++ * @file uapi/linux/mxcfb.h
++ *
++ * @brief Global header file for the MXC frame buffer
++ *
++ * @ingroup Framebuffer
++ */
++#ifndef __ASM_ARCH_MXCFB_H__
++#define __ASM_ARCH_MXCFB_H__
++
++#include <linux/fb.h>
++
++#define FB_SYNC_OE_LOW_ACT 0x80000000
++#define FB_SYNC_CLK_LAT_FALL 0x40000000
++#define FB_SYNC_DATA_INVERT 0x20000000
++#define FB_SYNC_CLK_IDLE_EN 0x10000000
++#define FB_SYNC_SHARP_MODE 0x08000000
++#define FB_SYNC_SWAP_RGB 0x04000000
++#define FB_ACCEL_TRIPLE_FLAG 0x00000000
++#define FB_ACCEL_DOUBLE_FLAG 0x00000001
++
++struct mxcfb_gbl_alpha {
++ int enable;
++ int alpha;
++};
++
++struct mxcfb_loc_alpha {
++ int enable;
++ int alpha_in_pixel;
++ unsigned long alpha_phy_addr0;
++ unsigned long alpha_phy_addr1;
++};
++
++struct mxcfb_color_key {
++ int enable;
++ __u32 color_key;
++};
++
++struct mxcfb_pos {
++ __u16 x;
++ __u16 y;
++};
++
++struct mxcfb_gamma {
++ int enable;
++ int constk[16];
++ int slopek[16];
++};
++
++struct mxcfb_rect {
++ __u32 top;
++ __u32 left;
++ __u32 width;
++ __u32 height;
++};
++
++#define GRAYSCALE_8BIT 0x1
++#define GRAYSCALE_8BIT_INVERTED 0x2
++#define GRAYSCALE_4BIT 0x3
++#define GRAYSCALE_4BIT_INVERTED 0x4
++
++#define AUTO_UPDATE_MODE_REGION_MODE 0
++#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1
++
++#define UPDATE_SCHEME_SNAPSHOT 0
++#define UPDATE_SCHEME_QUEUE 1
++#define UPDATE_SCHEME_QUEUE_AND_MERGE 2
++
++#define UPDATE_MODE_PARTIAL 0x0
++#define UPDATE_MODE_FULL 0x1
++
++#define WAVEFORM_MODE_AUTO 257
++
++#define TEMP_USE_AMBIENT 0x1000
++
++#define EPDC_FLAG_ENABLE_INVERSION 0x01
++#define EPDC_FLAG_FORCE_MONOCHROME 0x02
++#define EPDC_FLAG_USE_CMAP 0x04
++#define EPDC_FLAG_USE_ALT_BUFFER 0x100
++#define EPDC_FLAG_TEST_COLLISION 0x200
++#define EPDC_FLAG_GROUP_UPDATE 0x400
++#define EPDC_FLAG_USE_DITHERING_Y1 0x2000
++#define EPDC_FLAG_USE_DITHERING_Y4 0x4000
++
++#define FB_POWERDOWN_DISABLE -1
++
++struct mxcfb_alt_buffer_data {
++ __u32 phys_addr;
++ __u32 width; /* width of entire buffer */
++ __u32 height; /* height of entire buffer */
++ struct mxcfb_rect alt_update_region; /* region within buffer to update */
++};
++
++struct mxcfb_update_data {
++ struct mxcfb_rect update_region;
++ __u32 waveform_mode;
++ __u32 update_mode;
++ __u32 update_marker;
++ int temp;
++ unsigned int flags;
++ struct mxcfb_alt_buffer_data alt_buffer_data;
++};
++
++struct mxcfb_update_marker_data {
++ __u32 update_marker;
++ __u32 collision_test;
++};
++
++/*
++ * Structure used to define waveform modes for driver
++ * Needed for driver to perform auto-waveform selection
++ */
++struct mxcfb_waveform_modes {
++ int mode_init;
++ int mode_du;
++ int mode_gc4;
++ int mode_gc8;
++ int mode_gc16;
++ int mode_gc32;
++};
++
++/*
++ * Structure used to define a 5*3 matrix of parameters for
++ * setting IPU DP CSC module related to this framebuffer.
++ */
++struct mxcfb_csc_matrix {
++ int param[5][3];
++};
++
++#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
++#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha)
++#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key)
++#define MXCFB_SET_OVERLAY_POS _IOWR('F', 0x24, struct mxcfb_pos)
++#define MXCFB_GET_FB_IPU_CHAN _IOR('F', 0x25, u_int32_t)
++#define MXCFB_SET_LOC_ALPHA _IOWR('F', 0x26, struct mxcfb_loc_alpha)
++#define MXCFB_SET_LOC_ALP_BUF _IOW('F', 0x27, unsigned long)
++#define MXCFB_SET_GAMMA _IOW('F', 0x28, struct mxcfb_gamma)
++#define MXCFB_GET_FB_IPU_DI _IOR('F', 0x29, u_int32_t)
++#define MXCFB_GET_DIFMT _IOR('F', 0x2A, u_int32_t)
++#define MXCFB_GET_FB_BLANK _IOR('F', 0x2B, u_int32_t)
++#define MXCFB_SET_DIFMT _IOW('F', 0x2C, u_int32_t)
++#define MXCFB_CSC_UPDATE _IOW('F', 0x2D, struct mxcfb_csc_matrix)
++
++/* IOCTLs for E-ink panel updates */
++#define MXCFB_SET_WAVEFORM_MODES _IOW('F', 0x2B, struct mxcfb_waveform_modes)
++#define MXCFB_SET_TEMPERATURE _IOW('F', 0x2C, int32_t)
++#define MXCFB_SET_AUTO_UPDATE_MODE _IOW('F', 0x2D, __u32)
++#define MXCFB_SEND_UPDATE _IOW('F', 0x2E, struct mxcfb_update_data)
++#define MXCFB_WAIT_FOR_UPDATE_COMPLETE _IOWR('F', 0x2F, struct mxcfb_update_marker_data)
++#define MXCFB_SET_PWRDOWN_DELAY _IOW('F', 0x30, int32_t)
++#define MXCFB_GET_PWRDOWN_DELAY _IOR('F', 0x31, int32_t)
++#define MXCFB_SET_UPDATE_SCHEME _IOW('F', 0x32, __u32)
++#define MXCFB_GET_WORK_BUFFER _IOWR('F', 0x34, unsigned long)
++#define MXCFB_DISABLE_EPDC_ACCESS _IO('F', 0x35)
++#define MXCFB_ENABLE_EPDC_ACCESS _IO('F', 0x36)
++#endif
+diff -Nur linux-3.14.72.orig/include/uapi/linux/mxc_v4l2.h linux-3.14.72/include/uapi/linux/mxc_v4l2.h
+--- linux-3.14.72.orig/include/uapi/linux/mxc_v4l2.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/mxc_v4l2.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++/*!
++ * @file uapi/linux/mxc_v4l2.h
++ *
++ * @brief MXC V4L2 private header file
++ *
++ * @ingroup MXC V4L2
++ */
++
++#ifndef __ASM_ARCH_MXC_V4L2_H__
++#define __ASM_ARCH_MXC_V4L2_H__
++
++/*
++ * For IPUv1 and IPUv3, V4L2_CID_MXC_ROT means encoder ioctl ID.
++ * And V4L2_CID_MXC_VF_ROT is viewfinder ioctl ID only for IPUv1 and IPUv3.
++ */
++#define V4L2_CID_MXC_ROT (V4L2_CID_PRIVATE_BASE + 0)
++#define V4L2_CID_MXC_FLASH (V4L2_CID_PRIVATE_BASE + 1)
++#define V4L2_CID_MXC_VF_ROT (V4L2_CID_PRIVATE_BASE + 2)
++#define V4L2_CID_MXC_MOTION (V4L2_CID_PRIVATE_BASE + 3)
++#define V4L2_CID_MXC_SWITCH_CAM (V4L2_CID_PRIVATE_BASE + 6)
++
++#define V4L2_MXC_ROTATE_NONE 0
++#define V4L2_MXC_ROTATE_VERT_FLIP 1
++#define V4L2_MXC_ROTATE_HORIZ_FLIP 2
++#define V4L2_MXC_ROTATE_180 3
++#define V4L2_MXC_ROTATE_90_RIGHT 4
++#define V4L2_MXC_ROTATE_90_RIGHT_VFLIP 5
++#define V4L2_MXC_ROTATE_90_RIGHT_HFLIP 6
++#define V4L2_MXC_ROTATE_90_LEFT 7
++
++#define V4L2_MXC_CAM_ROTATE_NONE 8
++#define V4L2_MXC_CAM_ROTATE_VERT_FLIP 9
++#define V4L2_MXC_CAM_ROTATE_HORIZ_FLIP 10
++#define V4L2_MXC_CAM_ROTATE_180 11
++
++struct v4l2_mxc_offset {
++ uint32_t u_offset;
++ uint32_t v_offset;
++};
++
++#endif
+diff -Nur linux-3.14.72.orig/include/uapi/linux/ptp_clock.h linux-3.14.72/include/uapi/linux/ptp_clock.h
+--- linux-3.14.72.orig/include/uapi/linux/ptp_clock.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/ptp_clock.h 2016-06-19 22:11:55.509126621 +0200
+@@ -50,7 +50,8 @@
+ int n_ext_ts; /* Number of external time stamp channels. */
+ int n_per_out; /* Number of programmable periodic signals. */
+ int pps; /* Whether the clock supports a PPS callback. */
+- int rsv[15]; /* Reserved for future use. */
++ int n_pins; /* Number of input/output pins. */
++ int rsv[14]; /* Reserved for future use. */
+ };
+
+ struct ptp_extts_request {
+@@ -80,6 +81,40 @@
+ struct ptp_clock_time ts[2 * PTP_MAX_SAMPLES + 1];
+ };
+
++enum ptp_pin_function {
++ PTP_PF_NONE,
++ PTP_PF_EXTTS,
++ PTP_PF_PEROUT,
++ PTP_PF_PHYSYNC,
++};
++
++struct ptp_pin_desc {
++ /*
++ * Hardware specific human readable pin name. This field is
++ * set by the kernel during the PTP_PIN_GETFUNC ioctl and is
++ * ignored for the PTP_PIN_SETFUNC ioctl.
++ */
++ char name[64];
++ /*
++ * Pin index in the range of zero to ptp_clock_caps.n_pins - 1.
++ */
++ unsigned int index;
++ /*
++ * Which of the PTP_PF_xxx functions to use on this pin.
++ */
++ unsigned int func;
++ /*
++ * The specific channel to use for this function.
++ * This corresponds to the 'index' field of the
++ * PTP_EXTTS_REQUEST and PTP_PEROUT_REQUEST ioctls.
++ */
++ unsigned int chan;
++ /*
++ * Reserved for future use.
++ */
++ unsigned int rsv[5];
++};
++
+ #define PTP_CLK_MAGIC '='
+
+ #define PTP_CLOCK_GETCAPS _IOR(PTP_CLK_MAGIC, 1, struct ptp_clock_caps)
+@@ -87,6 +122,8 @@
+ #define PTP_PEROUT_REQUEST _IOW(PTP_CLK_MAGIC, 3, struct ptp_perout_request)
+ #define PTP_ENABLE_PPS _IOW(PTP_CLK_MAGIC, 4, int)
+ #define PTP_SYS_OFFSET _IOW(PTP_CLK_MAGIC, 5, struct ptp_sys_offset)
++#define PTP_PIN_GETFUNC _IOWR(PTP_CLK_MAGIC, 6, struct ptp_pin_desc)
++#define PTP_PIN_SETFUNC _IOW(PTP_CLK_MAGIC, 7, struct ptp_pin_desc)
+
+ struct ptp_extts_event {
+ struct ptp_clock_time t; /* Time event occured. */
+diff -Nur linux-3.14.72.orig/include/uapi/linux/pxp_device.h linux-3.14.72/include/uapi/linux/pxp_device.h
+--- linux-3.14.72.orig/include/uapi/linux/pxp_device.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/pxp_device.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,63 @@
++/*
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _UAPI_PXP_DEVICE
++#define _UAPI_PXP_DEVICE
++
++#include <linux/pxp_dma.h>
++
++struct pxp_chan_handle {
++ unsigned int handle;
++ int hist_status;
++};
++
++struct pxp_mem_desc {
++ unsigned int handle;
++ unsigned int size;
++ dma_addr_t phys_addr;
++ unsigned int virt_uaddr; /* virtual user space address */
++ unsigned int mtype;
++};
++
++struct pxp_mem_flush {
++ unsigned int handle;
++ unsigned int type;
++};
++
++#define PXP_IOC_MAGIC 'P'
++
++#define PXP_IOC_GET_CHAN _IOR(PXP_IOC_MAGIC, 0, struct pxp_mem_desc)
++#define PXP_IOC_PUT_CHAN _IOW(PXP_IOC_MAGIC, 1, struct pxp_mem_desc)
++#define PXP_IOC_CONFIG_CHAN _IOW(PXP_IOC_MAGIC, 2, struct pxp_mem_desc)
++#define PXP_IOC_START_CHAN _IOW(PXP_IOC_MAGIC, 3, struct pxp_mem_desc)
++#define PXP_IOC_GET_PHYMEM _IOWR(PXP_IOC_MAGIC, 4, struct pxp_mem_desc)
++#define PXP_IOC_PUT_PHYMEM _IOW(PXP_IOC_MAGIC, 5, struct pxp_mem_desc)
++#define PXP_IOC_WAIT4CMPLT _IOWR(PXP_IOC_MAGIC, 6, struct pxp_mem_desc)
++#define PXP_IOC_FLUSH_PHYMEM _IOR(PXP_IOC_MAGIC, 7, struct pxp_mem_flush)
++
++/* Memory types supported*/
++#define MEMORY_TYPE_UNCACHED 0x0
++#define MEMORY_TYPE_WC 0x1
++#define MEMORY_TYPE_CACHED 0x2
++
++/* Cache flush operations */
++#define CACHE_CLEAN 0x1
++#define CACHE_INVALIDATE 0x2
++#define CACHE_FLUSH 0x4
++
++#endif
+diff -Nur linux-3.14.72.orig/include/uapi/linux/pxp_dma.h linux-3.14.72/include/uapi/linux/pxp_dma.h
+--- linux-3.14.72.orig/include/uapi/linux/pxp_dma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/uapi/linux/pxp_dma.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,173 @@
++/*
++ * Copyright (C) 2013-2015 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#ifndef _UAPI_PXP_DMA
++#define _UAPI_PXP_DMA
++
++#include <linux/posix_types.h>
++#include <linux/types.h>
++
++#ifndef __KERNEL__
++typedef unsigned long dma_addr_t;
++typedef unsigned char bool;
++#endif
++
++/* PXP Pixel format definitions */
++/* Four-character-code (FOURCC) */
++#define fourcc(a, b, c, d)\
++ (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24))
++
++/*!
++ * @name PXP Pixel Formats
++ *
++ * Pixel formats are defined with ASCII FOURCC code. The pixel format codes are
++ * the same used by V4L2 API.
++ */
++
++/*! @} */
++/*! @name RGB Formats */
++/*! @{ */
++#define PXP_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */
++#define PXP_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */
++#define PXP_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 1 6 RGB-5-6-5 */
++#define PXP_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */
++#define PXP_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */
++#define PXP_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */
++#define PXP_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */
++#define PXP_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */
++#define PXP_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */
++#define PXP_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */
++#define PXP_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */
++#define PXP_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */
++/*! @} */
++/*! @name YUV Interleaved Formats */
++/*! @{ */
++#define PXP_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */
++#define PXP_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */
++#define PXP_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */
++#define PXP_PIX_FMT_VUY444 fourcc('V', 'U', 'Y', 'A') /*!< 32 VUYA 8:8:8 */
++/* two planes -- one Y, one Cb + Cr interleaved */
++#define PXP_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
++#define PXP_PIX_FMT_NV21 fourcc('N', 'V', '2', '1') /* 12 Y/CbCr 4:2:0 */
++#define PXP_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 12 Y/CbCr 4:2:2 */
++#define PXP_PIX_FMT_NV61 fourcc('N', 'V', '6', '1') /* 12 Y/CbCr 4:2:2 */
++/*! @} */
++/*! @name YUV Planar Formats */
++/*! @{ */
++#define PXP_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */
++#define PXP_PIX_FMT_GY04 fourcc('G', 'Y', '0', '4') /*!< 4 Greyscale */
++#define PXP_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */
++#define PXP_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */
++#define PXP_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */
++#define PXP_PIX_FMT_YUV420P fourcc('I', '4', '2', '0') /*!< 12 YUV 4:2:0 */
++#define PXP_PIX_FMT_YUV420P2 fourcc('Y', 'U', '1', '2') /*!< 12 YUV 4:2:0 */
++#define PXP_PIX_FMT_YVU422P fourcc('Y', 'V', '1', '6') /*!< 16 YVU 4:2:2 */
++#define PXP_PIX_FMT_YUV422P fourcc('4', '2', '2', 'P') /*!< 16 YUV 4:2:2 */
++/*! @} */
++
++#define PXP_LUT_NONE 0x0
++#define PXP_LUT_INVERT 0x1
++#define PXP_LUT_BLACK_WHITE 0x2
++#define PXP_LUT_USE_CMAP 0x4
++
++#define NR_PXP_VIRT_CHANNEL 16
++
++/* Order significant! */
++enum pxp_channel_status {
++ PXP_CHANNEL_FREE,
++ PXP_CHANNEL_INITIALIZED,
++ PXP_CHANNEL_READY,
++};
++
++struct rect {
++ int top; /* Upper left coordinate of rectangle */
++ int left;
++ int width;
++ int height;
++};
++
++struct pxp_layer_param {
++ unsigned short width;
++ unsigned short height;
++ unsigned short stride; /* aka pitch */
++ unsigned int pixel_fmt;
++
++ /* layers combining parameters
++ * (these are ignored for S0 and output
++ * layers, and only apply for OL layer)
++ */
++ bool combine_enable;
++ unsigned int color_key_enable;
++ unsigned int color_key;
++ bool global_alpha_enable;
++ /* global alpha is either override or multiply */
++ bool global_override;
++ unsigned char global_alpha;
++ bool alpha_invert;
++ bool local_alpha_enable;
++
++ dma_addr_t paddr;
++};
++
++struct pxp_proc_data {
++ /* S0 Transformation Info */
++ int scaling;
++ int hflip;
++ int vflip;
++ int rotate;
++ int rot_pos;
++ int yuv;
++
++ /* Source rectangle (srect) defines the sub-rectangle
++ * within S0 to undergo processing.
++ */
++ struct rect srect;
++ /* Dest rect (drect) defines how to position the processed
++ * source rectangle (after resizing) within the output frame,
++ * whose dimensions are defined in pxp->pxp_conf_state.out_param
++ */
++ struct rect drect;
++
++ /* Current S0 configuration */
++ unsigned int bgcolor;
++
++ /* Output overlay support */
++ int overlay_state;
++
++ /* LUT transformation on Y data */
++ int lut_transform;
++ unsigned char *lut_map; /* 256 entries */
++ bool lut_map_updated; /* Map recently changed */
++ bool combine_enable;
++};
++
++struct pxp_config_data {
++ struct pxp_layer_param s0_param;
++ struct pxp_layer_param ol_param[8];
++ struct pxp_layer_param out_param;
++ struct pxp_proc_data proc_data;
++ int layer_nr;
++
++ /* Users don't touch */
++ int handle;
++};
++
++
++#endif
+diff -Nur linux-3.14.72.orig/include/uapi/linux/usb/ch9.h linux-3.14.72/include/uapi/linux/usb/ch9.h
+--- linux-3.14.72.orig/include/uapi/linux/usb/ch9.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/usb/ch9.h 2016-06-19 22:11:55.509126621 +0200
+@@ -672,6 +672,12 @@
+ __u8 bDescriptorType;
+
+ __u8 bmAttributes; /* support for HNP, SRP, etc */
++ __le16 bcdOTG; /* OTG and EH supplement release number
++ * in binary-coded decimal (i.e. 2.0 is 0200H).
++ * This field identifies the release of the
++ * OTG and EH supplement with which the device
++ * and its descriptors are compliant.
++ */
+ } __attribute__ ((packed));
+
+ /* from usb_otg_descriptor.bmAttributes */
+diff -Nur linux-3.14.72.orig/include/uapi/linux/v4l2-controls.h linux-3.14.72/include/uapi/linux/v4l2-controls.h
+--- linux-3.14.72.orig/include/uapi/linux/v4l2-controls.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/v4l2-controls.h 2016-06-19 22:11:55.509126621 +0200
+@@ -168,6 +168,10 @@
+ * We reserve 16 controls for this driver. */
+ #define V4L2_CID_USER_SAA7134_BASE (V4L2_CID_USER_BASE + 0x1060)
+
++/* The base for the tc358743 driver controls.
++ * We reserve 16 controls for this driver. */
++#define V4L2_CID_USER_TC358743_BASE (V4L2_CID_USER_BASE + 0x1080)
++
+ /* MPEG-class control IDs */
+ /* The MPEG controls are applicable to all codec controls
+ * and the 'MPEG' part of the define is historical */
+@@ -672,6 +676,14 @@
+ #define V4L2_CID_AUTO_EXPOSURE_BIAS (V4L2_CID_CAMERA_CLASS_BASE+19)
+
+ #define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (V4L2_CID_CAMERA_CLASS_BASE+20)
++
++/* Backported from Samsung Kernel */
++#define V4L2_CID_AUTO_FOCUS_START (V4L2_CID_CAMERA_CLASS_BASE+28)
++#define V4L2_CID_AUTO_FOCUS_STOP (V4L2_CID_CAMERA_CLASS_BASE+29)
++#define V4L2_CID_AUTO_FOCUS_STATUS (V4L2_CID_CAMERA_CLASS_BASE+30)
++#define V4L2_CID_SEND_COMMAND (V4L2_CID_CAMERA_CLASS_BASE+34)
++
++
+ enum v4l2_auto_n_preset_white_balance {
+ V4L2_WHITE_BALANCE_MANUAL = 0,
+ V4L2_WHITE_BALANCE_AUTO = 1,
+diff -Nur linux-3.14.72.orig/include/uapi/linux/v4l2-mediabus.h linux-3.14.72/include/uapi/linux/v4l2-mediabus.h
+--- linux-3.14.72.orig/include/uapi/linux/v4l2-mediabus.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/v4l2-mediabus.h 2016-06-19 22:11:55.509126621 +0200
+@@ -11,108 +11,96 @@
+ #ifndef __LINUX_V4L2_MEDIABUS_H
+ #define __LINUX_V4L2_MEDIABUS_H
+
++#include <linux/media-bus-format.h>
+ #include <linux/types.h>
+ #include <linux/videodev2.h>
+
+-/*
+- * These pixel codes uniquely identify data formats on the media bus. Mostly
+- * they correspond to similarly named V4L2_PIX_FMT_* formats, format 0 is
+- * reserved, V4L2_MBUS_FMT_FIXED shall be used by host-client pairs, where the
+- * data format is fixed. Additionally, "2X8" means that one pixel is transferred
+- * in two 8-bit samples, "BE" or "LE" specify in which order those samples are
+- * transferred over the bus: "LE" means that the least significant bits are
+- * transferred first, "BE" means that the most significant bits are transferred
+- * first, and "PADHI" and "PADLO" define which bits - low or high, in the
+- * incomplete high byte, are filled with padding bits.
+- *
+- * The pixel codes are grouped by type, bus_width, bits per component, samples
+- * per pixel and order of subsamples. Numerical values are sorted using generic
+- * numerical sort order (8 thus comes before 10).
+- *
+- * As their value can't change when a new pixel code is inserted in the
+- * enumeration, the pixel codes are explicitly given a numerical value. The next
+- * free values for each category are listed below, update them when inserting
+- * new pixel codes.
+- */
++#define V4L2_MBUS_FROM_MEDIA_BUS_FMT(name) \
++ V4L2_MBUS_FMT_ ## name = MEDIA_BUS_FMT_ ## name
++
+ enum v4l2_mbus_pixelcode {
+- V4L2_MBUS_FMT_FIXED = 0x0001,
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(FIXED),
+
+- /* RGB - next is 0x100e */
+- V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE = 0x1001,
+- V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE = 0x1002,
+- V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE = 0x1003,
+- V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE = 0x1004,
+- V4L2_MBUS_FMT_BGR565_2X8_BE = 0x1005,
+- V4L2_MBUS_FMT_BGR565_2X8_LE = 0x1006,
+- V4L2_MBUS_FMT_RGB565_2X8_BE = 0x1007,
+- V4L2_MBUS_FMT_RGB565_2X8_LE = 0x1008,
+- V4L2_MBUS_FMT_RGB666_1X18 = 0x1009,
+- V4L2_MBUS_FMT_RGB888_1X24 = 0x100a,
+- V4L2_MBUS_FMT_RGB888_2X12_BE = 0x100b,
+- V4L2_MBUS_FMT_RGB888_2X12_LE = 0x100c,
+- V4L2_MBUS_FMT_ARGB8888_1X32 = 0x100d,
+-
+- /* YUV (including grey) - next is 0x2018 */
+- V4L2_MBUS_FMT_Y8_1X8 = 0x2001,
+- V4L2_MBUS_FMT_UV8_1X8 = 0x2015,
+- V4L2_MBUS_FMT_UYVY8_1_5X8 = 0x2002,
+- V4L2_MBUS_FMT_VYUY8_1_5X8 = 0x2003,
+- V4L2_MBUS_FMT_YUYV8_1_5X8 = 0x2004,
+- V4L2_MBUS_FMT_YVYU8_1_5X8 = 0x2005,
+- V4L2_MBUS_FMT_UYVY8_2X8 = 0x2006,
+- V4L2_MBUS_FMT_VYUY8_2X8 = 0x2007,
+- V4L2_MBUS_FMT_YUYV8_2X8 = 0x2008,
+- V4L2_MBUS_FMT_YVYU8_2X8 = 0x2009,
+- V4L2_MBUS_FMT_Y10_1X10 = 0x200a,
+- V4L2_MBUS_FMT_YUYV10_2X10 = 0x200b,
+- V4L2_MBUS_FMT_YVYU10_2X10 = 0x200c,
+- V4L2_MBUS_FMT_Y12_1X12 = 0x2013,
+- V4L2_MBUS_FMT_UYVY8_1X16 = 0x200f,
+- V4L2_MBUS_FMT_VYUY8_1X16 = 0x2010,
+- V4L2_MBUS_FMT_YUYV8_1X16 = 0x2011,
+- V4L2_MBUS_FMT_YVYU8_1X16 = 0x2012,
+- V4L2_MBUS_FMT_YDYUYDYV8_1X16 = 0x2014,
+- V4L2_MBUS_FMT_YUYV10_1X20 = 0x200d,
+- V4L2_MBUS_FMT_YVYU10_1X20 = 0x200e,
+- V4L2_MBUS_FMT_YUV10_1X30 = 0x2016,
+- V4L2_MBUS_FMT_AYUV8_1X32 = 0x2017,
+-
+- /* Bayer - next is 0x3019 */
+- V4L2_MBUS_FMT_SBGGR8_1X8 = 0x3001,
+- V4L2_MBUS_FMT_SGBRG8_1X8 = 0x3013,
+- V4L2_MBUS_FMT_SGRBG8_1X8 = 0x3002,
+- V4L2_MBUS_FMT_SRGGB8_1X8 = 0x3014,
+- V4L2_MBUS_FMT_SBGGR10_ALAW8_1X8 = 0x3015,
+- V4L2_MBUS_FMT_SGBRG10_ALAW8_1X8 = 0x3016,
+- V4L2_MBUS_FMT_SGRBG10_ALAW8_1X8 = 0x3017,
+- V4L2_MBUS_FMT_SRGGB10_ALAW8_1X8 = 0x3018,
+- V4L2_MBUS_FMT_SBGGR10_DPCM8_1X8 = 0x300b,
+- V4L2_MBUS_FMT_SGBRG10_DPCM8_1X8 = 0x300c,
+- V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8 = 0x3009,
+- V4L2_MBUS_FMT_SRGGB10_DPCM8_1X8 = 0x300d,
+- V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE = 0x3003,
+- V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE = 0x3004,
+- V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE = 0x3005,
+- V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE = 0x3006,
+- V4L2_MBUS_FMT_SBGGR10_1X10 = 0x3007,
+- V4L2_MBUS_FMT_SGBRG10_1X10 = 0x300e,
+- V4L2_MBUS_FMT_SGRBG10_1X10 = 0x300a,
+- V4L2_MBUS_FMT_SRGGB10_1X10 = 0x300f,
+- V4L2_MBUS_FMT_SBGGR12_1X12 = 0x3008,
+- V4L2_MBUS_FMT_SGBRG12_1X12 = 0x3010,
+- V4L2_MBUS_FMT_SGRBG12_1X12 = 0x3011,
+- V4L2_MBUS_FMT_SRGGB12_1X12 = 0x3012,
+-
+- /* JPEG compressed formats - next is 0x4002 */
+- V4L2_MBUS_FMT_JPEG_1X8 = 0x4001,
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB444_2X8_PADHI_BE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB444_2X8_PADHI_LE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB555_2X8_PADHI_BE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB555_2X8_PADHI_LE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(BGR565_2X8_BE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(BGR565_2X8_LE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB565_2X8_BE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB565_2X8_LE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB666_1X18),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_1X24),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_2X12_BE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(RGB888_2X12_LE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(ARGB8888_1X32),
++
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(Y8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UV8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UYVY8_1_5X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY8_1_5X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV8_1_5X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU8_1_5X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UYVY8_2X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY8_2X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV8_2X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU8_2X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(Y10_1X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UYVY10_2X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY10_2X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV10_2X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU10_2X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(Y12_1X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UYVY8_1X16),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY8_1X16),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV8_1X16),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU8_1X16),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YDYUYDYV8_1X16),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UYVY10_1X20),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY10_1X20),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV10_1X20),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU10_1X20),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUV10_1X30),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(AYUV8_1X32),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UYVY12_2X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY12_2X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV12_2X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU12_2X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(UYVY12_1X24),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(VYUY12_1X24),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YUYV12_1X24),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(YVYU12_1X24),
++
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGBRG8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGRBG8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SRGGB8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR10_ALAW8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGBRG10_ALAW8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGRBG10_ALAW8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SRGGB10_ALAW8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR10_DPCM8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGBRG10_DPCM8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGRBG10_DPCM8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SRGGB10_DPCM8_1X8),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR10_2X8_PADHI_BE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR10_2X8_PADHI_LE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR10_2X8_PADLO_BE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR10_2X8_PADLO_LE),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR10_1X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGBRG10_1X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGRBG10_1X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SRGGB10_1X10),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SBGGR12_1X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGBRG12_1X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SGRBG12_1X12),
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(SRGGB12_1X12),
+
+- /* Vendor specific formats - next is 0x5002 */
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(JPEG_1X8),
+
+- /* S5C73M3 sensor specific interleaved UYVY and JPEG */
+- V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8 = 0x5001,
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(S5C_UYVY_JPEG_1X8),
+
+- /* HSV - next is 0x6002 */
+- V4L2_MBUS_FMT_AHSV8888_1X32 = 0x6001,
++ V4L2_MBUS_FROM_MEDIA_BUS_FMT(AHSV8888_1X32),
+ };
+
+ /**
+diff -Nur linux-3.14.72.orig/include/uapi/linux/videodev2.h linux-3.14.72/include/uapi/linux/videodev2.h
+--- linux-3.14.72.orig/include/uapi/linux/videodev2.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/include/uapi/linux/videodev2.h 2016-06-19 22:11:55.509126621 +0200
+@@ -139,6 +139,7 @@
+ #endif
+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE = 9,
+ V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE = 10,
++ V4L2_BUF_TYPE_SENSOR = 11,
+ /* Deprecated, do not use */
+ V4L2_BUF_TYPE_PRIVATE = 0x80,
+ };
+@@ -284,6 +285,13 @@
+ __u32 priv; /* private data, depends on pixelformat */
+ };
+
++struct v4l2_sensor_dimension {
++ __u32 swidth;
++ __u32 sheight;
++ __u32 top;
++ __u32 left;
++};
++
+ /* Pixel format FOURCC depth Description */
+
+ /* RGB formats */
+@@ -1239,6 +1247,13 @@
+ struct v4l2_ext_control *controls;
+ };
+
++struct v4l2_send_command_control {
++ __u32 id;
++ __u32 value0;
++ __u32 value1;
++ char debug[256];
++};
++
+ #define V4L2_CTRL_ID_MASK (0x0fffffff)
+ #define V4L2_CTRL_ID2CLASS(id) ((id) & 0x0fff0000UL)
+ #define V4L2_CTRL_DRIVER_PRIV(id) (((id) & 0xffff) >= 0x1000)
+@@ -1705,6 +1720,7 @@
+ __u32 type;
+ union {
+ struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */
++ struct v4l2_sensor_dimension spix; /* V4L2_BUF_TYPE_SENSOR */
+ struct v4l2_pix_format_mplane pix_mp; /* V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE */
+ struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */
+ struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */
+@@ -1799,13 +1815,11 @@
+ /* VIDIOC_DBG_G_REGISTER and VIDIOC_DBG_S_REGISTER */
+
+ #define V4L2_CHIP_MATCH_BRIDGE 0 /* Match against chip ID on the bridge (0 for the bridge) */
+-#define V4L2_CHIP_MATCH_SUBDEV 4 /* Match against subdev index */
+-
+-/* The following four defines are no longer in use */
+ #define V4L2_CHIP_MATCH_HOST V4L2_CHIP_MATCH_BRIDGE
+ #define V4L2_CHIP_MATCH_I2C_DRIVER 1 /* Match against I2C driver name */
+ #define V4L2_CHIP_MATCH_I2C_ADDR 2 /* Match against I2C 7-bit address */
+ #define V4L2_CHIP_MATCH_AC97 3 /* Match against ancillary AC97 chip */
++#define V4L2_CHIP_MATCH_SUBDEV 4 /* Match against subdev index */
+
+ struct v4l2_dbg_match {
+ __u32 type; /* Match type */
+@@ -1822,6 +1836,13 @@
+ __u64 val;
+ } __attribute__ ((packed));
+
++/* VIDIOC_DBG_G_CHIP_IDENT */
++struct v4l2_dbg_chip_ident {
++ struct v4l2_dbg_match match;
++ __u32 ident; /* chip identifier as specified in <media/v4l2-chip-ident.h> */
++ __u32 revision; /* chip revision, chip specific */
++} __attribute__ ((packed));
++
+ #define V4L2_CHIP_FL_READABLE (1 << 0)
+ #define V4L2_CHIP_FL_WRITABLE (1 << 1)
+
+@@ -1922,6 +1943,12 @@
+ #define VIDIOC_DBG_S_REGISTER _IOW('V', 79, struct v4l2_dbg_register)
+ #define VIDIOC_DBG_G_REGISTER _IOWR('V', 80, struct v4l2_dbg_register)
+
++/* Experimental, meant for debugging, testing and internal use.
++ Never use this ioctl in applications!
++ Note: this ioctl is deprecated in favor of VIDIOC_DBG_G_CHIP_INFO and
++ will go away in the future. */
++#define VIDIOC_DBG_G_CHIP_IDENT _IOWR('V', 81, struct v4l2_dbg_chip_ident)
++
+ #define VIDIOC_S_HW_FREQ_SEEK _IOW('V', 82, struct v4l2_hw_freq_seek)
+
+ #define VIDIOC_S_DV_TIMINGS _IOWR('V', 87, struct v4l2_dv_timings)
+@@ -1958,6 +1985,8 @@
+ Never use these in applications! */
+ #define VIDIOC_DBG_G_CHIP_INFO _IOWR('V', 102, struct v4l2_dbg_chip_info)
+
++#define VIDIOC_SEND_COMMAND _IOWR('V', 103, struct v4l2_send_command_control)
++
+ /* Reminder: when adding new ioctls please add support for them to
+ drivers/media/video/v4l2-compat-ioctl32.c as well! */
+
+diff -Nur linux-3.14.72.orig/include/video/mxc_edid.h linux-3.14.72/include/video/mxc_edid.h
+--- linux-3.14.72.orig/include/video/mxc_edid.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/video/mxc_edid.h 2016-06-19 22:11:55.509126621 +0200
+@@ -0,0 +1,116 @@
++/*
++ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @defgroup Framebuffer Framebuffer Driver for SDC and ADC.
++ */
++
++/*!
++ * @file mxc_edid.h
++ *
++ * @brief MXC EDID tools
++ *
++ * @ingroup Framebuffer
++ */
++
++#ifndef MXC_EDID_H
++#define MXC_EDID_H
++
++#include <linux/fb.h>
++
++#define FB_VMODE_ASPECT_4_3 0x10
++#define FB_VMODE_ASPECT_16_9 0x20
++#define FB_VMODE_ASPECT_MASK (FB_VMODE_ASPECT_4_3 | FB_VMODE_ASPECT_16_9)
++
++enum cea_audio_coding_types {
++ AUDIO_CODING_TYPE_REF_STREAM_HEADER = 0,
++ AUDIO_CODING_TYPE_LPCM = 1,
++ AUDIO_CODING_TYPE_AC3 = 2,
++ AUDIO_CODING_TYPE_MPEG1 = 3,
++ AUDIO_CODING_TYPE_MP3 = 4,
++ AUDIO_CODING_TYPE_MPEG2 = 5,
++ AUDIO_CODING_TYPE_AACLC = 6,
++ AUDIO_CODING_TYPE_DTS = 7,
++ AUDIO_CODING_TYPE_ATRAC = 8,
++ AUDIO_CODING_TYPE_SACD = 9,
++ AUDIO_CODING_TYPE_EAC3 = 10,
++ AUDIO_CODING_TYPE_DTS_HD = 11,
++ AUDIO_CODING_TYPE_MLP = 12,
++ AUDIO_CODING_TYPE_DST = 13,
++ AUDIO_CODING_TYPE_WMAPRO = 14,
++ AUDIO_CODING_TYPE_RESERVED = 15,
++};
++
++struct mxc_hdmi_3d_format {
++ unsigned char vic_order_2d;
++ unsigned char struct_3d;
++ unsigned char detail_3d;
++ unsigned char reserved;
++};
++
++struct mxc_edid_cfg {
++ bool cea_underscan;
++ bool cea_basicaudio;
++ bool cea_ycbcr444;
++ bool cea_ycbcr422;
++ bool hdmi_cap;
++ bool cea_rgb_range_selectable;
++ u8 cea_scan_mode_ce;
++ u8 cea_scan_mode_it;
++ u8 cea_scan_mode_pt;
++
++ /*VSD*/
++ bool vsd_support_ai;
++ bool vsd_dc_48bit;
++ bool vsd_dc_36bit;
++ bool vsd_dc_30bit;
++ bool vsd_dc_y444;
++ bool vsd_dvi_dual;
++
++ bool vsd_cnc0;
++ bool vsd_cnc1;
++ bool vsd_cnc2;
++ bool vsd_cnc3;
++
++ u8 vsd_video_latency;
++ u8 vsd_audio_latency;
++ u8 vsd_I_video_latency;
++ u8 vsd_I_audio_latency;
++
++ u8 physical_address[4];
++ u8 hdmi_vic[64];
++ struct mxc_hdmi_3d_format hdmi_3d_format[64];
++ u16 hdmi_3d_mask_all;
++ u16 hdmi_3d_struct_all;
++ u32 vsd_max_tmdsclk_rate;
++
++ u8 sample_sizes[4];
++ u8 sample_rates[4];
++ u8 speaker_alloc;
++};
++
++static inline unsigned long mxcPICOS2KHZ(u32 pixclock, u32 vmode) {
++ u32 x = (1000000000UL / (pixclock) * 1000 / ((vmode & FB_VMODE_FRACTIONAL) ? 1001 : 1000));
++ return x + ((1000000000UL % x) > (x / 2) ? 1 : 0);
++}
++
++int mxc_edid_var_to_vic(struct fb_var_screeninfo *var);
++int mxc_edid_mode_to_vic(const struct fb_videomode *mode);
++int mxc_edid_read(struct i2c_adapter *adp, unsigned short addr,
++ unsigned char *edid, struct mxc_edid_cfg *cfg, struct fb_info *fbi);
++int mxc_edid_parse_ext_blk(unsigned char *edid, struct mxc_edid_cfg *cfg,
++ struct fb_monspecs *specs);
++const struct fb_videomode *mxc_fb_find_nearest_mode(const struct fb_videomode *mode,
++ struct list_head *head, bool relax);
++int mxc_fb_mode_is_equal_res(const struct fb_videomode *mode1, const struct fb_videomode *mode2);
++#endif
+diff -Nur linux-3.14.72.orig/include/video/mxc_hdmi.h linux-3.14.72/include/video/mxc_hdmi.h
+--- linux-3.14.72.orig/include/video/mxc_hdmi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/include/video/mxc_hdmi.h 2016-06-19 22:11:55.513126359 +0200
+@@ -0,0 +1,1027 @@
++/*
++ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
++ */
++
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __MXC_HDMI_H__
++#define __MXC_HDMI_H__
++
++/*
++ * Hdmi controller registers
++ */
++
++/* Identification Registers */
++#define HDMI_DESIGN_ID 0x0000
++#define HDMI_REVISION_ID 0x0001
++#define HDMI_PRODUCT_ID0 0x0002
++#define HDMI_PRODUCT_ID1 0x0003
++#define HDMI_CONFIG0_ID 0x0004
++#define HDMI_CONFIG1_ID 0x0005
++#define HDMI_CONFIG2_ID 0x0006
++#define HDMI_CONFIG3_ID 0x0007
++
++/* Interrupt Registers */
++#define HDMI_IH_FC_STAT0 0x0100
++#define HDMI_IH_FC_STAT1 0x0101
++#define HDMI_IH_FC_STAT2 0x0102
++#define HDMI_IH_AS_STAT0 0x0103
++#define HDMI_IH_PHY_STAT0 0x0104
++#define HDMI_IH_I2CM_STAT0 0x0105
++#define HDMI_IH_CEC_STAT0 0x0106
++#define HDMI_IH_VP_STAT0 0x0107
++#define HDMI_IH_I2CMPHY_STAT0 0x0108
++#define HDMI_IH_AHBDMAAUD_STAT0 0x0109
++
++#define HDMI_IH_MUTE_FC_STAT0 0x0180
++#define HDMI_IH_MUTE_FC_STAT1 0x0181
++#define HDMI_IH_MUTE_FC_STAT2 0x0182
++#define HDMI_IH_MUTE_AS_STAT0 0x0183
++#define HDMI_IH_MUTE_PHY_STAT0 0x0184
++#define HDMI_IH_MUTE_I2CM_STAT0 0x0185
++#define HDMI_IH_MUTE_CEC_STAT0 0x0186
++#define HDMI_IH_MUTE_VP_STAT0 0x0187
++#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
++#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
++#define HDMI_IH_MUTE 0x01FF
++
++/* Video Sample Registers */
++#define HDMI_TX_INVID0 0x0200
++#define HDMI_TX_INSTUFFING 0x0201
++#define HDMI_TX_GYDATA0 0x0202
++#define HDMI_TX_GYDATA1 0x0203
++#define HDMI_TX_RCRDATA0 0x0204
++#define HDMI_TX_RCRDATA1 0x0205
++#define HDMI_TX_BCBDATA0 0x0206
++#define HDMI_TX_BCBDATA1 0x0207
++
++/* Video Packetizer Registers */
++#define HDMI_VP_STATUS 0x0800
++#define HDMI_VP_PR_CD 0x0801
++#define HDMI_VP_STUFF 0x0802
++#define HDMI_VP_REMAP 0x0803
++#define HDMI_VP_CONF 0x0804
++#define HDMI_VP_STAT 0x0805
++#define HDMI_VP_INT 0x0806
++#define HDMI_VP_MASK 0x0807
++#define HDMI_VP_POL 0x0808
++
++/* Frame Composer Registers */
++#define HDMI_FC_INVIDCONF 0x1000
++#define HDMI_FC_INHACTV0 0x1001
++#define HDMI_FC_INHACTV1 0x1002
++#define HDMI_FC_INHBLANK0 0x1003
++#define HDMI_FC_INHBLANK1 0x1004
++#define HDMI_FC_INVACTV0 0x1005
++#define HDMI_FC_INVACTV1 0x1006
++#define HDMI_FC_INVBLANK 0x1007
++#define HDMI_FC_HSYNCINDELAY0 0x1008
++#define HDMI_FC_HSYNCINDELAY1 0x1009
++#define HDMI_FC_HSYNCINWIDTH0 0x100A
++#define HDMI_FC_HSYNCINWIDTH1 0x100B
++#define HDMI_FC_VSYNCINDELAY 0x100C
++#define HDMI_FC_VSYNCINWIDTH 0x100D
++#define HDMI_FC_INFREQ0 0x100E
++#define HDMI_FC_INFREQ1 0x100F
++#define HDMI_FC_INFREQ2 0x1010
++#define HDMI_FC_CTRLDUR 0x1011
++#define HDMI_FC_EXCTRLDUR 0x1012
++#define HDMI_FC_EXCTRLSPAC 0x1013
++#define HDMI_FC_CH0PREAM 0x1014
++#define HDMI_FC_CH1PREAM 0x1015
++#define HDMI_FC_CH2PREAM 0x1016
++#define HDMI_FC_AVICONF3 0x1017
++#define HDMI_FC_GCP 0x1018
++#define HDMI_FC_AVICONF0 0x1019
++#define HDMI_FC_AVICONF1 0x101A
++#define HDMI_FC_AVICONF2 0x101B
++#define HDMI_FC_AVIVID 0x101C
++#define HDMI_FC_AVIETB0 0x101D
++#define HDMI_FC_AVIETB1 0x101E
++#define HDMI_FC_AVISBB0 0x101F
++#define HDMI_FC_AVISBB1 0x1020
++#define HDMI_FC_AVIELB0 0x1021
++#define HDMI_FC_AVIELB1 0x1022
++#define HDMI_FC_AVISRB0 0x1023
++#define HDMI_FC_AVISRB1 0x1024
++#define HDMI_FC_AUDICONF0 0x1025
++#define HDMI_FC_AUDICONF1 0x1026
++#define HDMI_FC_AUDICONF2 0x1027
++#define HDMI_FC_AUDICONF3 0x1028
++#define HDMI_FC_VSDIEEEID0 0x1029
++#define HDMI_FC_VSDSIZE 0x102A
++#define HDMI_FC_VSDIEEEID1 0x1030
++#define HDMI_FC_VSDIEEEID2 0x1031
++#define HDMI_FC_VSDPAYLOAD0 0x1032
++#define HDMI_FC_VSDPAYLOAD1 0x1033
++#define HDMI_FC_VSDPAYLOAD2 0x1034
++#define HDMI_FC_VSDPAYLOAD3 0x1035
++#define HDMI_FC_VSDPAYLOAD4 0x1036
++#define HDMI_FC_VSDPAYLOAD5 0x1037
++#define HDMI_FC_VSDPAYLOAD6 0x1038
++#define HDMI_FC_VSDPAYLOAD7 0x1039
++#define HDMI_FC_VSDPAYLOAD8 0x103A
++#define HDMI_FC_VSDPAYLOAD9 0x103B
++#define HDMI_FC_VSDPAYLOAD10 0x103C
++#define HDMI_FC_VSDPAYLOAD11 0x103D
++#define HDMI_FC_VSDPAYLOAD12 0x103E
++#define HDMI_FC_VSDPAYLOAD13 0x103F
++#define HDMI_FC_VSDPAYLOAD14 0x1040
++#define HDMI_FC_VSDPAYLOAD15 0x1041
++#define HDMI_FC_VSDPAYLOAD16 0x1042
++#define HDMI_FC_VSDPAYLOAD17 0x1043
++#define HDMI_FC_VSDPAYLOAD18 0x1044
++#define HDMI_FC_VSDPAYLOAD19 0x1045
++#define HDMI_FC_VSDPAYLOAD20 0x1046
++#define HDMI_FC_VSDPAYLOAD21 0x1047
++#define HDMI_FC_VSDPAYLOAD22 0x1048
++#define HDMI_FC_VSDPAYLOAD23 0x1049
++#define HDMI_FC_SPDVENDORNAME0 0x104A
++#define HDMI_FC_SPDVENDORNAME1 0x104B
++#define HDMI_FC_SPDVENDORNAME2 0x104C
++#define HDMI_FC_SPDVENDORNAME3 0x104D
++#define HDMI_FC_SPDVENDORNAME4 0x104E
++#define HDMI_FC_SPDVENDORNAME5 0x104F
++#define HDMI_FC_SPDVENDORNAME6 0x1050
++#define HDMI_FC_SPDVENDORNAME7 0x1051
++#define HDMI_FC_SDPPRODUCTNAME0 0x1052
++#define HDMI_FC_SDPPRODUCTNAME1 0x1053
++#define HDMI_FC_SDPPRODUCTNAME2 0x1054
++#define HDMI_FC_SDPPRODUCTNAME3 0x1055
++#define HDMI_FC_SDPPRODUCTNAME4 0x1056
++#define HDMI_FC_SDPPRODUCTNAME5 0x1057
++#define HDMI_FC_SDPPRODUCTNAME6 0x1058
++#define HDMI_FC_SDPPRODUCTNAME7 0x1059
++#define HDMI_FC_SDPPRODUCTNAME8 0x105A
++#define HDMI_FC_SDPPRODUCTNAME9 0x105B
++#define HDMI_FC_SDPPRODUCTNAME10 0x105C
++#define HDMI_FC_SDPPRODUCTNAME11 0x105D
++#define HDMI_FC_SDPPRODUCTNAME12 0x105E
++#define HDMI_FC_SDPPRODUCTNAME13 0x105F
++#define HDMI_FC_SDPPRODUCTNAME14 0x1060
++#define HDMI_FC_SPDPRODUCTNAME15 0x1061
++#define HDMI_FC_SPDDEVICEINF 0x1062
++#define HDMI_FC_AUDSCONF 0x1063
++#define HDMI_FC_AUDSSTAT 0x1064
++#define HDMI_FC_DATACH0FILL 0x1070
++#define HDMI_FC_DATACH1FILL 0x1071
++#define HDMI_FC_DATACH2FILL 0x1072
++#define HDMI_FC_CTRLQHIGH 0x1073
++#define HDMI_FC_CTRLQLOW 0x1074
++#define HDMI_FC_ACP0 0x1075
++#define HDMI_FC_ACP28 0x1076
++#define HDMI_FC_ACP27 0x1077
++#define HDMI_FC_ACP26 0x1078
++#define HDMI_FC_ACP25 0x1079
++#define HDMI_FC_ACP24 0x107A
++#define HDMI_FC_ACP23 0x107B
++#define HDMI_FC_ACP22 0x107C
++#define HDMI_FC_ACP21 0x107D
++#define HDMI_FC_ACP20 0x107E
++#define HDMI_FC_ACP19 0x107F
++#define HDMI_FC_ACP18 0x1080
++#define HDMI_FC_ACP17 0x1081
++#define HDMI_FC_ACP16 0x1082
++#define HDMI_FC_ACP15 0x1083
++#define HDMI_FC_ACP14 0x1084
++#define HDMI_FC_ACP13 0x1085
++#define HDMI_FC_ACP12 0x1086
++#define HDMI_FC_ACP11 0x1087
++#define HDMI_FC_ACP10 0x1088
++#define HDMI_FC_ACP9 0x1089
++#define HDMI_FC_ACP8 0x108A
++#define HDMI_FC_ACP7 0x108B
++#define HDMI_FC_ACP6 0x108C
++#define HDMI_FC_ACP5 0x108D
++#define HDMI_FC_ACP4 0x108E
++#define HDMI_FC_ACP3 0x108F
++#define HDMI_FC_ACP2 0x1090
++#define HDMI_FC_ACP1 0x1091
++#define HDMI_FC_ISCR1_0 0x1092
++#define HDMI_FC_ISCR1_16 0x1093
++#define HDMI_FC_ISCR1_15 0x1094
++#define HDMI_FC_ISCR1_14 0x1095
++#define HDMI_FC_ISCR1_13 0x1096
++#define HDMI_FC_ISCR1_12 0x1097
++#define HDMI_FC_ISCR1_11 0x1098
++#define HDMI_FC_ISCR1_10 0x1099
++#define HDMI_FC_ISCR1_9 0x109A
++#define HDMI_FC_ISCR1_8 0x109B
++#define HDMI_FC_ISCR1_7 0x109C
++#define HDMI_FC_ISCR1_6 0x109D
++#define HDMI_FC_ISCR1_5 0x109E
++#define HDMI_FC_ISCR1_4 0x109F
++#define HDMI_FC_ISCR1_3 0x10A0
++#define HDMI_FC_ISCR1_2 0x10A1
++#define HDMI_FC_ISCR1_1 0x10A2
++#define HDMI_FC_ISCR2_15 0x10A3
++#define HDMI_FC_ISCR2_14 0x10A4
++#define HDMI_FC_ISCR2_13 0x10A5
++#define HDMI_FC_ISCR2_12 0x10A6
++#define HDMI_FC_ISCR2_11 0x10A7
++#define HDMI_FC_ISCR2_10 0x10A8
++#define HDMI_FC_ISCR2_9 0x10A9
++#define HDMI_FC_ISCR2_8 0x10AA
++#define HDMI_FC_ISCR2_7 0x10AB
++#define HDMI_FC_ISCR2_6 0x10AC
++#define HDMI_FC_ISCR2_5 0x10AD
++#define HDMI_FC_ISCR2_4 0x10AE
++#define HDMI_FC_ISCR2_3 0x10AF
++#define HDMI_FC_ISCR2_2 0x10B0
++#define HDMI_FC_ISCR2_1 0x10B1
++#define HDMI_FC_ISCR2_0 0x10B2
++#define HDMI_FC_DATAUTO0 0x10B3
++#define HDMI_FC_DATAUTO1 0x10B4
++#define HDMI_FC_DATAUTO2 0x10B5
++#define HDMI_FC_DATMAN 0x10B6
++#define HDMI_FC_DATAUTO3 0x10B7
++#define HDMI_FC_RDRB0 0x10B8
++#define HDMI_FC_RDRB1 0x10B9
++#define HDMI_FC_RDRB2 0x10BA
++#define HDMI_FC_RDRB3 0x10BB
++#define HDMI_FC_RDRB4 0x10BC
++#define HDMI_FC_RDRB5 0x10BD
++#define HDMI_FC_RDRB6 0x10BE
++#define HDMI_FC_RDRB7 0x10BF
++#define HDMI_FC_STAT0 0x10D0
++#define HDMI_FC_INT0 0x10D1
++#define HDMI_FC_MASK0 0x10D2
++#define HDMI_FC_POL0 0x10D3
++#define HDMI_FC_STAT1 0x10D4
++#define HDMI_FC_INT1 0x10D5
++#define HDMI_FC_MASK1 0x10D6
++#define HDMI_FC_POL1 0x10D7
++#define HDMI_FC_STAT2 0x10D8
++#define HDMI_FC_INT2 0x10D9
++#define HDMI_FC_MASK2 0x10DA
++#define HDMI_FC_POL2 0x10DB
++#define HDMI_FC_PRCONF 0x10E0
++
++#define HDMI_FC_GMD_STAT 0x1100
++#define HDMI_FC_GMD_EN 0x1101
++#define HDMI_FC_GMD_UP 0x1102
++#define HDMI_FC_GMD_CONF 0x1103
++#define HDMI_FC_GMD_HB 0x1104
++#define HDMI_FC_GMD_PB0 0x1105
++#define HDMI_FC_GMD_PB1 0x1106
++#define HDMI_FC_GMD_PB2 0x1107
++#define HDMI_FC_GMD_PB3 0x1108
++#define HDMI_FC_GMD_PB4 0x1109
++#define HDMI_FC_GMD_PB5 0x110A
++#define HDMI_FC_GMD_PB6 0x110B
++#define HDMI_FC_GMD_PB7 0x110C
++#define HDMI_FC_GMD_PB8 0x110D
++#define HDMI_FC_GMD_PB9 0x110E
++#define HDMI_FC_GMD_PB10 0x110F
++#define HDMI_FC_GMD_PB11 0x1110
++#define HDMI_FC_GMD_PB12 0x1111
++#define HDMI_FC_GMD_PB13 0x1112
++#define HDMI_FC_GMD_PB14 0x1113
++#define HDMI_FC_GMD_PB15 0x1114
++#define HDMI_FC_GMD_PB16 0x1115
++#define HDMI_FC_GMD_PB17 0x1116
++#define HDMI_FC_GMD_PB18 0x1117
++#define HDMI_FC_GMD_PB19 0x1118
++#define HDMI_FC_GMD_PB20 0x1119
++#define HDMI_FC_GMD_PB21 0x111A
++#define HDMI_FC_GMD_PB22 0x111B
++#define HDMI_FC_GMD_PB23 0x111C
++#define HDMI_FC_GMD_PB24 0x111D
++#define HDMI_FC_GMD_PB25 0x111E
++#define HDMI_FC_GMD_PB26 0x111F
++#define HDMI_FC_GMD_PB27 0x1120
++
++#define HDMI_FC_DBGFORCE 0x1200
++#define HDMI_FC_DBGAUD0CH0 0x1201
++#define HDMI_FC_DBGAUD1CH0 0x1202
++#define HDMI_FC_DBGAUD2CH0 0x1203
++#define HDMI_FC_DBGAUD0CH1 0x1204
++#define HDMI_FC_DBGAUD1CH1 0x1205
++#define HDMI_FC_DBGAUD2CH1 0x1206
++#define HDMI_FC_DBGAUD0CH2 0x1207
++#define HDMI_FC_DBGAUD1CH2 0x1208
++#define HDMI_FC_DBGAUD2CH2 0x1209
++#define HDMI_FC_DBGAUD0CH3 0x120A
++#define HDMI_FC_DBGAUD1CH3 0x120B
++#define HDMI_FC_DBGAUD2CH3 0x120C
++#define HDMI_FC_DBGAUD0CH4 0x120D
++#define HDMI_FC_DBGAUD1CH4 0x120E
++#define HDMI_FC_DBGAUD2CH4 0x120F
++#define HDMI_FC_DBGAUD0CH5 0x1210
++#define HDMI_FC_DBGAUD1CH5 0x1211
++#define HDMI_FC_DBGAUD2CH5 0x1212
++#define HDMI_FC_DBGAUD0CH6 0x1213
++#define HDMI_FC_DBGAUD1CH6 0x1214
++#define HDMI_FC_DBGAUD2CH6 0x1215
++#define HDMI_FC_DBGAUD0CH7 0x1216
++#define HDMI_FC_DBGAUD1CH7 0x1217
++#define HDMI_FC_DBGAUD2CH7 0x1218
++#define HDMI_FC_DBGTMDS0 0x1219
++#define HDMI_FC_DBGTMDS1 0x121A
++#define HDMI_FC_DBGTMDS2 0x121B
++
++/* HDMI Source PHY Registers */
++#define HDMI_PHY_CONF0 0x3000
++#define HDMI_PHY_TST0 0x3001
++#define HDMI_PHY_TST1 0x3002
++#define HDMI_PHY_TST2 0x3003
++#define HDMI_PHY_STAT0 0x3004
++#define HDMI_PHY_INT0 0x3005
++#define HDMI_PHY_MASK0 0x3006
++#define HDMI_PHY_POL0 0x3007
++
++/* HDMI Master PHY Registers */
++#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
++#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
++#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
++#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
++#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
++#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
++#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
++#define HDMI_PHY_I2CM_INT_ADDR 0x3027
++#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
++#define HDMI_PHY_I2CM_DIV_ADDR 0x3029
++#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
++#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
++#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
++#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
++#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
++
++/* Audio Sampler Registers */
++#define HDMI_AUD_CONF0 0x3100
++#define HDMI_AUD_CONF1 0x3101
++#define HDMI_AUD_INT 0x3102
++#define HDMI_AUD_CONF2 0x3103
++#define HDMI_AUD_N1 0x3200
++#define HDMI_AUD_N2 0x3201
++#define HDMI_AUD_N3 0x3202
++#define HDMI_AUD_CTS1 0x3203
++#define HDMI_AUD_CTS2 0x3204
++#define HDMI_AUD_CTS3 0x3205
++#define HDMI_AUD_INPUTCLKFS 0x3206
++#define HDMI_AUD_SPDIFINT 0x3302
++#define HDMI_AUD_CONF0_HBR 0x3400
++#define HDMI_AUD_HBR_STATUS 0x3401
++#define HDMI_AUD_HBR_INT 0x3402
++#define HDMI_AUD_HBR_POL 0x3403
++#define HDMI_AUD_HBR_MASK 0x3404
++
++/* Generic Parallel Audio Interface Registers */
++/* Not used as GPAUD interface is not enabled in hw */
++#define HDMI_GP_CONF0 0x3500
++#define HDMI_GP_CONF1 0x3501
++#define HDMI_GP_CONF2 0x3502
++#define HDMI_GP_STAT 0x3503
++#define HDMI_GP_INT 0x3504
++#define HDMI_GP_MASK 0x3505
++#define HDMI_GP_POL 0x3506
++
++/* Audio DMA Registers */
++#define HDMI_AHB_DMA_CONF0 0x3600
++#define HDMI_AHB_DMA_START 0x3601
++#define HDMI_AHB_DMA_STOP 0x3602
++#define HDMI_AHB_DMA_THRSLD 0x3603
++#define HDMI_AHB_DMA_STRADDR0 0x3604
++#define HDMI_AHB_DMA_STRADDR1 0x3605
++#define HDMI_AHB_DMA_STRADDR2 0x3606
++#define HDMI_AHB_DMA_STRADDR3 0x3607
++#define HDMI_AHB_DMA_STPADDR0 0x3608
++#define HDMI_AHB_DMA_STPADDR1 0x3609
++#define HDMI_AHB_DMA_STPADDR2 0x360a
++#define HDMI_AHB_DMA_STPADDR3 0x360b
++#define HDMI_AHB_DMA_BSTADDR0 0x360c
++#define HDMI_AHB_DMA_BSTADDR1 0x360d
++#define HDMI_AHB_DMA_BSTADDR2 0x360e
++#define HDMI_AHB_DMA_BSTADDR3 0x360f
++#define HDMI_AHB_DMA_MBLENGTH0 0x3610
++#define HDMI_AHB_DMA_MBLENGTH1 0x3611
++#define HDMI_AHB_DMA_STAT 0x3612
++#define HDMI_AHB_DMA_INT 0x3613
++#define HDMI_AHB_DMA_MASK 0x3614
++#define HDMI_AHB_DMA_POL 0x3615
++#define HDMI_AHB_DMA_CONF1 0x3616
++#define HDMI_AHB_DMA_BUFFSTAT 0x3617
++#define HDMI_AHB_DMA_BUFFINT 0x3618
++#define HDMI_AHB_DMA_BUFFMASK 0x3619
++#define HDMI_AHB_DMA_BUFFPOL 0x361a
++
++/* Main Controller Registers */
++#define HDMI_MC_SFRDIV 0x4000
++#define HDMI_MC_CLKDIS 0x4001
++#define HDMI_MC_SWRSTZ 0x4002
++#define HDMI_MC_OPCTRL 0x4003
++#define HDMI_MC_FLOWCTRL 0x4004
++#define HDMI_MC_PHYRSTZ 0x4005
++#define HDMI_MC_LOCKONCLOCK 0x4006
++#define HDMI_MC_HEACPHY_RST 0x4007
++
++/* Color Space Converter Registers */
++#define HDMI_CSC_CFG 0x4100
++#define HDMI_CSC_SCALE 0x4101
++#define HDMI_CSC_COEF_A1_MSB 0x4102
++#define HDMI_CSC_COEF_A1_LSB 0x4103
++#define HDMI_CSC_COEF_A2_MSB 0x4104
++#define HDMI_CSC_COEF_A2_LSB 0x4105
++#define HDMI_CSC_COEF_A3_MSB 0x4106
++#define HDMI_CSC_COEF_A3_LSB 0x4107
++#define HDMI_CSC_COEF_A4_MSB 0x4108
++#define HDMI_CSC_COEF_A4_LSB 0x4109
++#define HDMI_CSC_COEF_B1_MSB 0x410A
++#define HDMI_CSC_COEF_B1_LSB 0x410B
++#define HDMI_CSC_COEF_B2_MSB 0x410C
++#define HDMI_CSC_COEF_B2_LSB 0x410D
++#define HDMI_CSC_COEF_B3_MSB 0x410E
++#define HDMI_CSC_COEF_B3_LSB 0x410F
++#define HDMI_CSC_COEF_B4_MSB 0x4110
++#define HDMI_CSC_COEF_B4_LSB 0x4111
++#define HDMI_CSC_COEF_C1_MSB 0x4112
++#define HDMI_CSC_COEF_C1_LSB 0x4113
++#define HDMI_CSC_COEF_C2_MSB 0x4114
++#define HDMI_CSC_COEF_C2_LSB 0x4115
++#define HDMI_CSC_COEF_C3_MSB 0x4116
++#define HDMI_CSC_COEF_C3_LSB 0x4117
++#define HDMI_CSC_COEF_C4_MSB 0x4118
++#define HDMI_CSC_COEF_C4_LSB 0x4119
++
++/* HDCP Interrupt Registers */
++#define HDMI_A_APIINTCLR 0x5006
++#define HDMI_A_APIINTSTAT 0x5007
++#define HDMI_A_APIINTMSK 0x5008
++
++/* CEC Engine Registers */
++#define HDMI_CEC_CTRL 0x7D00
++#define HDMI_CEC_STAT 0x7D01
++#define HDMI_CEC_MASK 0x7D02
++#define HDMI_CEC_POLARITY 0x7D03
++#define HDMI_CEC_INT 0x7D04
++#define HDMI_CEC_ADDR_L 0x7D05
++#define HDMI_CEC_ADDR_H 0x7D06
++#define HDMI_CEC_TX_CNT 0x7D07
++#define HDMI_CEC_RX_CNT 0x7D08
++#define HDMI_CEC_TX_DATA0 0x7D10
++#define HDMI_CEC_TX_DATA1 0x7D11
++#define HDMI_CEC_TX_DATA2 0x7D12
++#define HDMI_CEC_TX_DATA3 0x7D13
++#define HDMI_CEC_TX_DATA4 0x7D14
++#define HDMI_CEC_TX_DATA5 0x7D15
++#define HDMI_CEC_TX_DATA6 0x7D16
++#define HDMI_CEC_TX_DATA7 0x7D17
++#define HDMI_CEC_TX_DATA8 0x7D18
++#define HDMI_CEC_TX_DATA9 0x7D19
++#define HDMI_CEC_TX_DATA10 0x7D1a
++#define HDMI_CEC_TX_DATA11 0x7D1b
++#define HDMI_CEC_TX_DATA12 0x7D1c
++#define HDMI_CEC_TX_DATA13 0x7D1d
++#define HDMI_CEC_TX_DATA14 0x7D1e
++#define HDMI_CEC_TX_DATA15 0x7D1f
++#define HDMI_CEC_RX_DATA0 0x7D20
++#define HDMI_CEC_RX_DATA1 0x7D21
++#define HDMI_CEC_RX_DATA2 0x7D22
++#define HDMI_CEC_RX_DATA3 0x7D23
++#define HDMI_CEC_RX_DATA4 0x7D24
++#define HDMI_CEC_RX_DATA5 0x7D25
++#define HDMI_CEC_RX_DATA6 0x7D26
++#define HDMI_CEC_RX_DATA7 0x7D27
++#define HDMI_CEC_RX_DATA8 0x7D28
++#define HDMI_CEC_RX_DATA9 0x7D29
++#define HDMI_CEC_RX_DATA10 0x7D2a
++#define HDMI_CEC_RX_DATA11 0x7D2b
++#define HDMI_CEC_RX_DATA12 0x7D2c
++#define HDMI_CEC_RX_DATA13 0x7D2d
++#define HDMI_CEC_RX_DATA14 0x7D2e
++#define HDMI_CEC_RX_DATA15 0x7D2f
++#define HDMI_CEC_LOCK 0x7D30
++#define HDMI_CEC_WKUPCTRL 0x7D31
++
++/* I2C Master Registers (E-DDC) */
++#define HDMI_I2CM_SLAVE 0x7E00
++#define HDMI_I2CM_ADDRESS 0x7E01
++#define HDMI_I2CM_DATAO 0x7E02
++#define HDMI_I2CM_DATAI 0x7E03
++#define HDMI_I2CM_OPERATION 0x7E04
++#define HDMI_I2CM_INT 0x7E05
++#define HDMI_I2CM_CTLINT 0x7E06
++#define HDMI_I2CM_DIV 0x7E07
++#define HDMI_I2CM_SEGADDR 0x7E08
++#define HDMI_I2CM_SOFTRSTZ 0x7E09
++#define HDMI_I2CM_SEGPTR 0x7E0A
++#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
++#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
++#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
++#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
++#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
++#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
++#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
++#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
++
++/* Random Number Generator Registers (RNG) */
++#define HDMI_RNG_BASE 0x8000
++
++
++/*
++ * Register field definitions
++ */
++enum {
++/* IH_FC_INT2 field values */
++ HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_FC_STAT2 field values */
++ HDMI_IH_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_PHY_STAT0_HPD = 0x1,
++
++/* IH_CEC_STAT0 field values */
++ HDMI_IH_CEC_STAT0_WAKEUP = 0x40,
++ HDMI_IH_CEC_STAT0_ERROR_FOLL = 0x20,
++ HDMI_IH_CEC_STAT0_ERROR_INIT = 0x10,
++ HDMI_IH_CEC_STAT0_ARB_LOST = 0x8,
++ HDMI_IH_CEC_STAT0_NACK = 0x4,
++ HDMI_IH_CEC_STAT0_EOM = 0x2,
++ HDMI_IH_CEC_STAT0_DONE = 0x1,
++
++
++/* IH_MUTE_I2CMPHY_STAT0 field values */
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYDONE = 0x2,
++ HDMI_IH_MUTE_I2CMPHY_STAT0_I2CMPHYERROR = 0x1,
++
++/* IH_PHY_STAT0 field values */
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE3 = 0x20,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE2 = 0x10,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE1 = 0x8,
++ HDMI_IH_MUTE_PHY_STAT0_RX_SENSE0 = 0x4,
++ HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2,
++ HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1,
++
++/* IH and IH_MUTE convenience macro RX_SENSE | HPD*/
++ HDMI_DVI_IH_STAT = 0x3D,
++
++
++/* IH_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE_FC_STAT2 field values */
++ HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_IH_MUTE_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_IH_MUTE_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* IH_MUTE_AHBDMAAUD_STAT0 field values */
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = 0x20,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = 0x10,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = 0x08,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = 0x04,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = 0x02,
++ HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = 0x01,
++
++/* IH_MUTE field values */
++ HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
++ HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
++
++/* TX_INVID0 field values */
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE = 0x80,
++ HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
++ HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1F,
++ HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
++
++/* TX_INSTUFFING field values */
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
++ HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
++ HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE = 0x0,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
++ HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE = 0x0,
++
++/* VP_PR_CD field values */
++ HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xF0,
++ HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0F,
++ HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
++
++/* VP_STUFF field values */
++ HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
++ HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK = 0x10,
++ HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET = 4,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK = 0x8,
++ HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET = 3,
++ HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
++ HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
++ HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE = 0x0,
++ HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
++ HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE = 0x0,
++
++/* VP_CONF field values */
++ HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
++ HDMI_VP_CONF_BYPASS_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
++ HDMI_VP_CONF_PP_EN_ENABLE = 0x20,
++ HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_PR_EN_MASK = 0x10,
++ HDMI_VP_CONF_PR_EN_ENABLE = 0x10,
++ HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
++ HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
++ HDMI_VP_CONF_YCC422_EN_ENABLE = 0x8,
++ HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
++ HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
++ HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER = 0x0,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 = 0x1,
++ HDMI_VP_CONF_OUTPUT_SELECTOR_PP = 0x0,
++
++/* VP_REMAP field values */
++ HDMI_VP_REMAP_MASK = 0x3,
++ HDMI_VP_REMAP_YCC422_24bit = 0x2,
++ HDMI_VP_REMAP_YCC422_20bit = 0x1,
++ HDMI_VP_REMAP_YCC422_16bit = 0x0,
++
++/* FC_INVIDCONF field values */
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
++ HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
++ HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
++ HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
++ HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
++ HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
++ HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
++ HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
++
++/* FC_AUDICONF0 field values */
++ HDMI_FC_AUDICONF0_CC_OFFSET = 4,
++ HDMI_FC_AUDICONF0_CC_MASK = 0x70,
++ HDMI_FC_AUDICONF0_CT_OFFSET = 0,
++ HDMI_FC_AUDICONF0_CT_MASK = 0xF,
++
++/* FC_AUDICONF1 field values */
++ HDMI_FC_AUDICONF1_SS_OFFSET = 3,
++ HDMI_FC_AUDICONF1_SS_MASK = 0x18,
++ HDMI_FC_AUDICONF1_SF_OFFSET = 0,
++ HDMI_FC_AUDICONF1_SF_MASK = 0x7,
++
++/* FC_AUDICONF3 field values */
++ HDMI_FC_AUDICONF3_LFEPBL_OFFSET = 5,
++ HDMI_FC_AUDICONF3_LFEPBL_MASK = 0x60,
++ HDMI_FC_AUDICONF3_DM_INH_OFFSET = 4,
++ HDMI_FC_AUDICONF3_DM_INH_MASK = 0x10,
++ HDMI_FC_AUDICONF3_LSV_OFFSET = 0,
++ HDMI_FC_AUDICONF3_LSV_MASK = 0xF,
++
++/* FC_AUDSCHNLS0 field values */
++ HDMI_FC_AUDSCHNLS0_CGMSA_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS0_CGMSA_MASK = 0x30,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS0_COPYRIGHT_MASK = 0x01,
++
++/* FC_AUDSCHNLS3-6 field values */
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS3_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS4_OIEC_CH3_MASK = 0xf0,
++
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH0_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS5_OIEC_CH1_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_OFFSET = 0,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH2_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS6_OIEC_CH3_MASK = 0xf0,
++
++/* HDMI_FC_AUDSCHNLS7 field values */
++ HDMI_FC_AUDSCHNLS7_ACCURACY_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS7_ACCURACY_MASK = 0x30,
++
++/* HDMI_FC_AUDSCHNLS8 field values */
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_MASK = 0xf0,
++ HDMI_FC_AUDSCHNLS8_ORIGSAMPFREQ_OFFSET = 4,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_MASK = 0x0f,
++ HDMI_FC_AUDSCHNLS8_WORDLEGNTH_OFFSET = 0,
++
++/* FC_AUDSCONF field values */
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_MASK = 0xF0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_SAMPFIT_OFFSET = 4,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_OFFSET = 0,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1 = 0x1,
++ HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0 = 0x0,
++
++/* FC_STAT2 field values */
++ HDMI_FC_STAT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_STAT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_STAT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_INT2 field values */
++ HDMI_FC_INT2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_INT2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_MASK2 field values */
++ HDMI_FC_MASK2_OVERFLOW_MASK = 0x03,
++ HDMI_FC_MASK2_LOW_PRIORITY_OVERFLOW = 0x02,
++ HDMI_FC_MASK2_HIGH_PRIORITY_OVERFLOW = 0x01,
++
++/* FC_PRCONF field values */
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK = 0xF0,
++ HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET = 4,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK = 0x0F,
++ HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET = 0,
++
++/* FC_AVICONF0-FC_AVICONF3 field values */
++ HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
++ HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
++ HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
++ HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0C,
++ HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
++ HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
++ HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0C,
++ HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
++ HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
++ HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
++ HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
++
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0F,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0A,
++ HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0B,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
++ HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
++ HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xC0,
++ HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
++ HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
++ HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
++ HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xC0,
++
++ HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
++ HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
++ HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
++ HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
++ HDMI_FC_AVICONF2_SCALING_HORIZ_VERT = 0x03,
++ HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0C,
++ HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
++ HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
++ HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
++ HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
++ HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
++ HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
++ HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
++
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
++ HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
++ HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0C,
++ HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
++ HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
++
++/* FC_DBGFORCE field values */
++ HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
++ HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
++
++/* PHY_CONF0 field values */
++ HDMI_PHY_CONF0_PDZ_MASK = 0x80,
++ HDMI_PHY_CONF0_PDZ_OFFSET = 7,
++ HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
++ HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
++ HDMI_PHY_CONF0_SPARECTRL = 0x20,
++ HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
++ HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
++ HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK = 0x4,
++ HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET = 2,
++ HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
++ HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
++ HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
++ HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
++
++/* PHY_TST0 field values */
++ HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
++ HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
++ HDMI_PHY_TST0_TSTEN_MASK = 0x10,
++ HDMI_PHY_TST0_TSTEN_OFFSET = 4,
++ HDMI_PHY_TST0_TSTCLK_MASK = 0x1,
++ HDMI_PHY_TST0_TSTCLK_OFFSET = 0,
++
++/* PHY_STAT0 field values */
++ HDMI_PHY_RX_SENSE3 = 0x80,
++ HDMI_PHY_RX_SENSE2 = 0x40,
++ HDMI_PHY_RX_SENSE1 = 0x20,
++ HDMI_PHY_RX_SENSE0 = 0x10,
++ HDMI_PHY_HPD = 0x02,
++ HDMI_PHY_TX_PHY_LOCK = 0x01,
++
++/* HDMI STAT convenience RX_SENSE | HPD */
++ HDMI_DVI_STAT = 0xF2,
++
++/* PHY_I2CM_SLAVE_ADDR field values */
++ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
++ HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
++
++/* PHY_I2CM_OPERATION_ADDR field values */
++ HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
++ HDMI_PHY_I2CM_OPERATION_ADDR_READ = 0x1,
++
++/* HDMI_PHY_I2CM_INT_ADDR */
++ HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
++ HDMI_PHY_I2CM_INT_ADDR_DONE_MASK = 0x04,
++
++/* HDMI_PHY_I2CM_CTLINT_ADDR */
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
++ HDMI_PHY_I2CM_CTLINT_ADDR_NAC_MASK = 0x40,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
++ HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_MASK = 0x04,
++
++/* AUD_CTS3 field values */
++ HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
++ HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
++ HDMI_AUD_CTS3_N_SHIFT_1 = 0,
++ HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
++ HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
++ HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
++ HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
++ HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
++ /* note that the CTS3 MANUAL bit has been removed
++ from our part. Can't set it, will read as 0. */
++ HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
++ HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
++
++/* AHB_DMA_CONF0 field values */
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_OFFSET = 7,
++ HDMI_AHB_DMA_CONF0_SW_FIFO_RST_MASK = 0x80,
++ HDMI_AHB_DMA_CONF0_HBR_OFFSET = 4,
++ HDMI_AHB_DMA_CONF0_HBR_MASK = 0x10,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_OFFSET = 3,
++ HDMI_AHB_DMA_CONF0_EN_HLOCK_MASK = 0x08,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_OFFSET = 1,
++ HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK = 0x06,
++ HDMI_AHB_DMA_CONF0_INCR4 = 0x0,
++ HDMI_AHB_DMA_CONF0_INCR8 = 0x2,
++ HDMI_AHB_DMA_CONF0_INCR16 = 0x4,
++ HDMI_AHB_DMA_CONF0_BURST_MODE = 0x1,
++
++/* HDMI_AHB_DMA_START field values */
++ HDMI_AHB_DMA_START_START_OFFSET = 0,
++ HDMI_AHB_DMA_START_START_MASK = 0x01,
++
++/* HDMI_AHB_DMA_STOP field values */
++ HDMI_AHB_DMA_STOP_STOP_OFFSET = 0,
++ HDMI_AHB_DMA_STOP_STOP_MASK = 0x01,
++
++/* AHB_DMA_STAT, AHB_DMA_INT, AHB_DMA_MASK, AHB_DMA_POL field values */
++ HDMI_AHB_DMA_DONE = 0x80,
++ HDMI_AHB_DMA_RETRY_SPLIT = 0x40,
++ HDMI_AHB_DMA_LOSTOWNERSHIP = 0x20,
++ HDMI_AHB_DMA_ERROR = 0x10,
++ HDMI_AHB_DMA_FIFO_THREMPTY = 0x04,
++ HDMI_AHB_DMA_FIFO_FULL = 0x02,
++ HDMI_AHB_DMA_FIFO_EMPTY = 0x01,
++
++/* AHB_DMA_BUFFSTAT, AHB_DMA_BUFFINT, AHB_DMA_BUFFMASK, AHB_DMA_BUFFPOL field values */
++ HDMI_AHB_DMA_BUFFSTAT_FULL = 0x02,
++ HDMI_AHB_DMA_BUFFSTAT_EMPTY = 0x01,
++
++/* MC_CLKDIS field values */
++ HDMI_MC_CLKDIS_HDCPCLK_DISABLE = 0x40,
++ HDMI_MC_CLKDIS_CECCLK_DISABLE = 0x20,
++ HDMI_MC_CLKDIS_CSCCLK_DISABLE = 0x10,
++ HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
++ HDMI_MC_CLKDIS_PREPCLK_DISABLE = 0x4,
++ HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
++ HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
++
++/* MC_SWRSTZ field values */
++ HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
++
++/* MC_FLOWCTRL field values */
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
++ HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
++
++/* MC_PHYRSTZ field values */
++ HDMI_MC_PHYRSTZ_ASSERT = 0x0,
++ HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
++
++/* MC_HEACPHY_RST field values */
++ HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
++ HDMI_MC_HEACPHY_RST_DEASSERT = 0x0,
++
++/* CSC_CFG field values */
++ HDMI_CSC_CFG_INTMODE_MASK = 0x30,
++ HDMI_CSC_CFG_INTMODE_OFFSET = 4,
++ HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1 = 0x10,
++ HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA2 = 0x20,
++ HDMI_CSC_CFG_DECMODE_MASK = 0x3,
++ HDMI_CSC_CFG_DECMODE_OFFSET = 0,
++ HDMI_CSC_CFG_DECMODE_DISABLE = 0x0,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA1 = 0x1,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA2 = 0x2,
++ HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3 = 0x3,
++
++/* CSC_SCALE field values */
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xF0,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
++ HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
++ HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
++
++/* I2CM_OPERATION field values */
++ HDMI_I2CM_OPERATION_WRITE = 0x10,
++ HDMI_I2CM_OPERATION_READ_EXT = 0x2,
++ HDMI_I2CM_OPERATION_READ = 0x1,
++
++/* HDMI_I2CM_INT */
++ HDMI_I2CM_INT_DONE_POL = 0x08,
++ HDMI_I2CM_INT_DONE_MASK = 0x04,
++
++/* HDMI_I2CM_CTLINT */
++ HDMI_I2CM_CTLINT_NAC_POL = 0x80,
++ HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
++ HDMI_I2CM_CTLINT_ARBITRATION_POL = 0x08,
++ HDMI_I2CM_CTLINT_ARBITRATION_MASK = 0x04,
++
++};
++
++enum imx_hdmi_type {
++ IMX6DL_HDMI,
++ IMX6Q_HDMI,
++};
++
++/* IOCTL commands */
++#define HDMI_IOC_MAGIC 'H'
++
++#define HDMI_IOC_GET_RESOURCE _IO(HDMI_IOC_MAGIC, 0)
++#define HDMI_IOC_GET_CPU_TYPE _IO(HDMI_IOC_MAGIC, 1)
++
++
++#endif /* __MXC_HDMI_H__ */
+diff -Nur linux-3.14.72.orig/kernel/cpu.c linux-3.14.72/kernel/cpu.c
+--- linux-3.14.72.orig/kernel/cpu.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/kernel/cpu.c 2016-06-19 22:11:55.513126359 +0200
+@@ -722,3 +722,23 @@
+ {
+ cpumask_copy(to_cpumask(cpu_online_bits), src);
+ }
++
++static ATOMIC_NOTIFIER_HEAD(idle_notifier);
++
++void idle_notifier_register(struct notifier_block *n)
++{
++ atomic_notifier_chain_register(&idle_notifier, n);
++}
++EXPORT_SYMBOL_GPL(idle_notifier_register);
++
++void idle_notifier_unregister(struct notifier_block *n)
++{
++ atomic_notifier_chain_unregister(&idle_notifier, n);
++}
++EXPORT_SYMBOL_GPL(idle_notifier_unregister);
++
++void idle_notifier_call_chain(unsigned long val)
++{
++ atomic_notifier_call_chain(&idle_notifier, val, NULL);
++}
++EXPORT_SYMBOL_GPL(idle_notifier_call_chain);
+diff -Nur linux-3.14.72.orig/kernel/irq/manage.c linux-3.14.72/kernel/irq/manage.c
+--- linux-3.14.72.orig/kernel/irq/manage.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/kernel/irq/manage.c 2016-06-19 22:11:55.513126359 +0200
+@@ -32,24 +32,10 @@
+ early_param("threadirqs", setup_forced_irqthreads);
+ #endif
+
+-/**
+- * synchronize_irq - wait for pending IRQ handlers (on other CPUs)
+- * @irq: interrupt number to wait for
+- *
+- * This function waits for any pending IRQ handlers for this interrupt
+- * to complete before returning. If you use this function while
+- * holding a resource the IRQ handler may need you will deadlock.
+- *
+- * This function may be called - with care - from IRQ context.
+- */
+-void synchronize_irq(unsigned int irq)
++static void __synchronize_hardirq(struct irq_desc *desc)
+ {
+- struct irq_desc *desc = irq_to_desc(irq);
+ bool inprogress;
+
+- if (!desc)
+- return;
+-
+ do {
+ unsigned long flags;
+
+@@ -67,12 +53,56 @@
+
+ /* Oops, that failed? */
+ } while (inprogress);
++}
++
++/**
++ * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
++ * @irq: interrupt number to wait for
++ *
++ * This function waits for any pending hard IRQ handlers for this
++ * interrupt to complete before returning. If you use this
++ * function while holding a resource the IRQ handler may need you
++ * will deadlock. It does not take associated threaded handlers
++ * into account.
++ *
++ * Do not use this for shutdown scenarios where you must be sure
++ * that all parts (hardirq and threaded handler) have completed.
++ *
++ * This function may be called - with care - from IRQ context.
++ */
++void synchronize_hardirq(unsigned int irq)
++{
++ struct irq_desc *desc = irq_to_desc(irq);
+
+- /*
+- * We made sure that no hardirq handler is running. Now verify
+- * that no threaded handlers are active.
+- */
+- wait_event(desc->wait_for_threads, !atomic_read(&desc->threads_active));
++ if (desc)
++ __synchronize_hardirq(desc);
++}
++EXPORT_SYMBOL(synchronize_hardirq);
++
++/**
++ * synchronize_irq - wait for pending IRQ handlers (on other CPUs)
++ * @irq: interrupt number to wait for
++ *
++ * This function waits for any pending IRQ handlers for this interrupt
++ * to complete before returning. If you use this function while
++ * holding a resource the IRQ handler may need you will deadlock.
++ *
++ * This function may be called - with care - from IRQ context.
++ */
++void synchronize_irq(unsigned int irq)
++{
++ struct irq_desc *desc = irq_to_desc(irq);
++
++ if (desc) {
++ __synchronize_hardirq(desc);
++ /*
++ * We made sure that no hardirq handler is
++ * running. Now verify that no threaded handlers are
++ * active.
++ */
++ wait_event(desc->wait_for_threads,
++ !atomic_read(&desc->threads_active));
++ }
+ }
+ EXPORT_SYMBOL(synchronize_irq);
+
+diff -Nur linux-3.14.72.orig/kernel/power/Kconfig linux-3.14.72/kernel/power/Kconfig
+--- linux-3.14.72.orig/kernel/power/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/kernel/power/Kconfig 2016-06-19 22:11:55.513126359 +0200
+@@ -306,6 +306,10 @@
+ def_bool y
+ depends on PM_RUNTIME && PM_GENERIC_DOMAINS
+
++config PM_GENERIC_DOMAINS_OF
++ def_bool y
++ depends on PM_GENERIC_DOMAINS && OF && !ARCH_EXYNOS
++
+ config CPU_PM
+ bool
+ depends on SUSPEND || CPU_IDLE
+diff -Nur linux-3.14.72.orig/MAINTAINERS linux-3.14.72/MAINTAINERS
+--- linux-3.14.72.orig/MAINTAINERS 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/MAINTAINERS 2016-06-19 22:11:55.513126359 +0200
+@@ -6618,6 +6618,14 @@
+ F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+ F: drivers/pci/host/pci-tegra.c
+
++PCI DRIVER FOR TI DRA7XX
++M: Kishon Vijay Abraham I <kishon@ti.com>
++L: linux-omap@vger.kernel.org
++L: linux-pci@vger.kernel.org
++S: Supported
++F: Documentation/devicetree/bindings/pci/ti-pci.txt
++F: drivers/pci/host/pci-dra7xx.c
++
+ PCI DRIVER FOR RENESAS R-CAR
+ M: Simon Horman <horms@verge.net.au>
+ L: linux-pci@vger.kernel.org
+@@ -6640,6 +6648,20 @@
+ S: Maintained
+ F: drivers/pci/host/*designware*
+
++PCI DRIVER FOR GENERIC OF HOSTS
++M: Will Deacon <will.deacon@arm.com>
++L: linux-pci@vger.kernel.org
++L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
++S: Maintained
++F: Documentation/devicetree/bindings/pci/host-generic-pci.txt
++F: drivers/pci/host/pci-host-generic.c
++
++PCIE DRIVER FOR ST SPEAR13XX
++M: Mohit Kumar <mohit.kumar@st.com>
++L: linux-pci@vger.kernel.org
++S: Maintained
++F: drivers/pci/host/*spear*
++
+ PCMCIA SUBSYSTEM
+ P: Linux PCMCIA Team
+ L: linux-pcmcia@lists.infradead.org
+@@ -8856,6 +8878,12 @@
+ S: Orphan
+ F: drivers/platform/x86/toshiba_acpi.c
+
++TOSHIBA TC358743 DRIVER
++M: Mats Randgaard <matrandg@cisco.com>
++L: linux-media@vger.kernel.org
++S: Maintained
++F: drivers/media/i2c/tc358743*
++
+ TOSHIBA SMM DRIVER
+ M: Jonathan Buzzard <jonathan@buzzard.org.uk>
+ L: tlinux-users@tce.toshiba-dme.co.jp
+diff -Nur linux-3.14.72.orig/mm/cma.c linux-3.14.72/mm/cma.c
+--- linux-3.14.72.orig/mm/cma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/mm/cma.c 2016-06-19 22:11:55.513126359 +0200
+@@ -0,0 +1,362 @@
++/*
++ * Contiguous Memory Allocator
++ *
++ * Copyright (c) 2010-2011 by Samsung Electronics.
++ * Copyright IBM Corporation, 2013
++ * Copyright LG Electronics Inc., 2014
++ * Written by:
++ * Marek Szyprowski <m.szyprowski@samsung.com>
++ * Michal Nazarewicz <mina86@mina86.com>
++ * Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
++ * Joonsoo Kim <iamjoonsoo.kim@lge.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of the
++ * License or (at your optional) any later version of the license.
++ */
++
++#define pr_fmt(fmt) "cma: " fmt
++
++#ifdef CONFIG_CMA_DEBUG
++#ifndef DEBUG
++# define DEBUG
++#endif
++#endif
++
++#include <linux/memblock.h>
++#include <linux/err.h>
++#include <linux/mm.h>
++#include <linux/mutex.h>
++#include <linux/sizes.h>
++#include <linux/slab.h>
++#include <linux/log2.h>
++#include <linux/cma.h>
++#include <linux/highmem.h>
++
++#include "cma.h"
++
++struct cma cma_areas[MAX_CMA_AREAS];
++unsigned cma_area_count;
++static DEFINE_MUTEX(cma_mutex);
++
++phys_addr_t cma_get_base(struct cma *cma)
++{
++ return PFN_PHYS(cma->base_pfn);
++}
++
++unsigned long cma_get_size(struct cma *cma)
++{
++ return cma->count << PAGE_SHIFT;
++}
++
++static unsigned long cma_bitmap_aligned_mask(struct cma *cma, int align_order)
++{
++ return (1UL << (align_order >> cma->order_per_bit)) - 1;
++}
++
++static unsigned long cma_bitmap_pages_to_bits(struct cma *cma,
++ unsigned long pages)
++{
++ return ALIGN(pages, 1UL << cma->order_per_bit) >> cma->order_per_bit;
++}
++
++static void cma_clear_bitmap(struct cma *cma, unsigned long pfn, int count)
++{
++ unsigned long bitmap_no, bitmap_count;
++
++ bitmap_no = (pfn - cma->base_pfn) >> cma->order_per_bit;
++ bitmap_count = cma_bitmap_pages_to_bits(cma, count);
++
++ mutex_lock(&cma->lock);
++ bitmap_clear(cma->bitmap, bitmap_no, bitmap_count);
++ mutex_unlock(&cma->lock);
++}
++
++static int __init cma_activate_area(struct cma *cma)
++{
++ int bitmap_size = BITS_TO_LONGS(cma_bitmap_maxno(cma)) * sizeof(long);
++ unsigned long base_pfn = cma->base_pfn, pfn = base_pfn;
++ unsigned i = cma->count >> pageblock_order;
++ struct zone *zone;
++
++ cma->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
++
++ if (!cma->bitmap)
++ return -ENOMEM;
++
++ WARN_ON_ONCE(!pfn_valid(pfn));
++ zone = page_zone(pfn_to_page(pfn));
++
++ do {
++ unsigned j;
++
++ base_pfn = pfn;
++ for (j = pageblock_nr_pages; j; --j, pfn++) {
++ WARN_ON_ONCE(!pfn_valid(pfn));
++ /*
++ * alloc_contig_range requires the pfn range
++ * specified to be in the same zone. Make this
++ * simple by forcing the entire CMA resv range
++ * to be in the same zone.
++ */
++ if (page_zone(pfn_to_page(pfn)) != zone)
++ goto err;
++ }
++ init_cma_reserved_pageblock(pfn_to_page(base_pfn));
++ } while (--i);
++
++ mutex_init(&cma->lock);
++ return 0;
++
++err:
++ kfree(cma->bitmap);
++ return -EINVAL;
++}
++
++static int __init cma_init_reserved_areas(void)
++{
++ int i;
++
++ for (i = 0; i < cma_area_count; i++) {
++ int ret = cma_activate_area(&cma_areas[i]);
++
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++core_initcall(cma_init_reserved_areas);
++
++/**
++ * cma_declare_contiguous() - reserve custom contiguous area
++ * @base: Base address of the reserved area optional, use 0 for any
++ * @size: Size of the reserved area (in bytes),
++ * @limit: End address of the reserved memory (optional, 0 for any).
++ * @alignment: Alignment for the CMA area, should be power of 2 or zero
++ * @order_per_bit: Order of pages represented by one bit on bitmap.
++ * @fixed: hint about where to place the reserved area
++ * @res_cma: Pointer to store the created cma region.
++ *
++ * This function reserves memory from early allocator. It should be
++ * called by arch specific code once the early allocator (memblock or bootmem)
++ * has been activated and all other subsystems have already allocated/reserved
++ * memory. This function allows to create custom reserved areas.
++ *
++ * If @fixed is true, reserve contiguous area at exactly @base. If false,
++ * reserve in range from @base to @limit.
++ */
++int __init cma_declare_contiguous(phys_addr_t base,
++ phys_addr_t size, phys_addr_t limit,
++ phys_addr_t alignment, unsigned int order_per_bit,
++ bool fixed, struct cma **res_cma)
++{
++ struct cma *cma;
++ phys_addr_t memblock_end = memblock_end_of_DRAM();
++ phys_addr_t highmem_start = __pa(high_memory);
++ int ret = 0;
++
++ pr_debug("%s(size %lx, base %08lx, limit %08lx alignment %08lx)\n",
++ __func__, (unsigned long)size, (unsigned long)base,
++ (unsigned long)limit, (unsigned long)alignment);
++
++ if (cma_area_count == ARRAY_SIZE(cma_areas)) {
++ pr_err("Not enough slots for CMA reserved regions!\n");
++ return -ENOSPC;
++ }
++
++ if (!size)
++ return -EINVAL;
++
++ if (alignment && !is_power_of_2(alignment))
++ return -EINVAL;
++
++ /*
++ * Sanitise input arguments.
++ * Pages both ends in CMA area could be merged into adjacent unmovable
++ * migratetype page by page allocator's buddy algorithm. In the case,
++ * you couldn't get a contiguous memory, which is not what we want.
++ */
++ alignment = max(alignment,
++ (phys_addr_t)PAGE_SIZE << max(MAX_ORDER - 1, pageblock_order));
++ base = ALIGN(base, alignment);
++ size = ALIGN(size, alignment);
++ limit &= ~(alignment - 1);
++
++ /* size should be aligned with order_per_bit */
++ if (!IS_ALIGNED(size >> PAGE_SHIFT, 1 << order_per_bit))
++ return -EINVAL;
++
++ /*
++ * If allocating at a fixed base the request region must not cross the
++ * low/high memory boundary.
++ */
++ if (fixed && base < highmem_start && base + size > highmem_start) {
++ ret = -EINVAL;
++ pr_err("Region at %08lx defined on low/high memory boundary (%08lx)\n",
++ (unsigned long)base, (unsigned long)highmem_start);
++ goto err;
++ }
++
++ /*
++ * If the limit is unspecified or above the memblock end, its effective
++ * value will be the memblock end. Set it explicitly to simplify further
++ * checks.
++ */
++ if (limit == 0 || limit > memblock_end)
++ limit = memblock_end;
++
++ /* Reserve memory */
++ if (base && fixed) {
++ if (memblock_is_region_reserved(base, size) ||
++ memblock_reserve(base, size) < 0) {
++ ret = -EBUSY;
++ goto err;
++ }
++ } else {
++ phys_addr_t addr = 0;
++
++ /*
++ * All pages in the reserved area must come from the same zone.
++ * If the requested region crosses the low/high memory boundary,
++ * try allocating from high memory first and fall back to low
++ * memory in case of failure.
++ */
++ if (base < highmem_start && limit > highmem_start) {
++ addr = memblock_alloc_range(size, alignment,
++ highmem_start, limit);
++ limit = highmem_start;
++ }
++
++ if (!addr) {
++ addr = memblock_alloc_range(size, alignment, base,
++ limit);
++ if (!addr) {
++ ret = -ENOMEM;
++ goto err;
++ }
++ }
++
++ base = addr;
++ }
++
++ /*
++ * Each reserved area must be initialised later, when more kernel
++ * subsystems (like slab allocator) are available.
++ */
++ cma = &cma_areas[cma_area_count];
++ cma->base_pfn = PFN_DOWN(base);
++ cma->count = size >> PAGE_SHIFT;
++ cma->order_per_bit = order_per_bit;
++ *res_cma = cma;
++ cma_area_count++;
++
++ pr_info("CMA: reserved %ld MiB at %08lx\n", (unsigned long)size / SZ_1M,
++ (unsigned long)base);
++ return 0;
++
++err:
++ pr_err("CMA: failed to reserve %ld MiB\n", (unsigned long)size / SZ_1M);
++ return ret;
++}
++
++/**
++ * cma_alloc() - allocate pages from contiguous area
++ * @cma: Contiguous memory region for which the allocation is performed.
++ * @count: Requested number of pages.
++ * @align: Requested alignment of pages (in PAGE_SIZE order).
++ *
++ * This function allocates part of contiguous memory on specific
++ * contiguous memory area.
++ */
++struct page *cma_alloc(struct cma *cma, int count, unsigned int align)
++{
++ unsigned long mask, pfn, start = 0;
++ unsigned long bitmap_maxno, bitmap_no, bitmap_count;
++ struct page *page = NULL;
++ int ret;
++
++ if (!cma || !cma->count)
++ return NULL;
++
++ pr_debug("%s(cma %p, count %d, align %d)\n", __func__, (void *)cma,
++ count, align);
++
++ if (!count)
++ return NULL;
++
++ mask = cma_bitmap_aligned_mask(cma, align);
++ bitmap_maxno = cma_bitmap_maxno(cma);
++ bitmap_count = cma_bitmap_pages_to_bits(cma, count);
++
++ for (;;) {
++ mutex_lock(&cma->lock);
++ bitmap_no = bitmap_find_next_zero_area(cma->bitmap,
++ bitmap_maxno, start, bitmap_count, mask);
++ if (bitmap_no >= bitmap_maxno) {
++ mutex_unlock(&cma->lock);
++ break;
++ }
++ bitmap_set(cma->bitmap, bitmap_no, bitmap_count);
++ /*
++ * It's safe to drop the lock here. We've marked this region for
++ * our exclusive use. If the migration fails we will take the
++ * lock again and unmark it.
++ */
++ mutex_unlock(&cma->lock);
++
++ pfn = cma->base_pfn + (bitmap_no << cma->order_per_bit);
++ mutex_lock(&cma_mutex);
++ ret = alloc_contig_range(pfn, pfn + count, MIGRATE_CMA);
++ mutex_unlock(&cma_mutex);
++ if (ret == 0) {
++ page = pfn_to_page(pfn);
++ break;
++ }
++
++ cma_clear_bitmap(cma, pfn, count);
++ if (ret != -EBUSY)
++ break;
++
++ pr_debug("%s(): memory range at %p is busy, retrying\n",
++ __func__, pfn_to_page(pfn));
++ /* try again with a bit different memory target */
++ start = bitmap_no + mask + 1;
++ }
++
++ pr_debug("%s(): returned %p\n", __func__, page);
++ return page;
++}
++
++/**
++ * cma_release() - release allocated pages
++ * @cma: Contiguous memory region for which the allocation is performed.
++ * @pages: Allocated pages.
++ * @count: Number of allocated pages.
++ *
++ * This function releases memory allocated by alloc_cma().
++ * It returns false when provided pages do not belong to contiguous area and
++ * true otherwise.
++ */
++bool cma_release(struct cma *cma, struct page *pages, int count)
++{
++ unsigned long pfn;
++
++ if (!cma || !pages)
++ return false;
++
++ pr_debug("%s(page %p)\n", __func__, (void *)pages);
++
++ pfn = page_to_pfn(pages);
++
++ if (pfn < cma->base_pfn || pfn >= cma->base_pfn + cma->count)
++ return false;
++
++ VM_BUG_ON(pfn + count > cma->base_pfn + cma->count);
++
++ free_contig_range(pfn, count);
++ cma_clear_bitmap(cma, pfn, count);
++
++ return true;
++}
+diff -Nur linux-3.14.72.orig/mm/cma_debug.c linux-3.14.72/mm/cma_debug.c
+--- linux-3.14.72.orig/mm/cma_debug.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/mm/cma_debug.c 2016-06-19 22:11:55.513126359 +0200
+@@ -0,0 +1,60 @@
++/*
++ * CMA DebugFS Interface
++ *
++ * Copyright (c) 2015 Sasha Levin <sasha.levin@oracle.com>
++ */
++
++
++#include <linux/debugfs.h>
++#include <linux/cma.h>
++
++#include "cma.h"
++
++static struct dentry *cma_debugfs_root;
++
++static int cma_debugfs_get(void *data, u64 *val)
++{
++ unsigned long *p = data;
++
++ *val = *p;
++
++ return 0;
++}
++
++DEFINE_SIMPLE_ATTRIBUTE(cma_debugfs_fops, cma_debugfs_get, NULL, "%llu\n");
++
++static void cma_debugfs_add_one(struct cma *cma, int idx)
++{
++ struct dentry *tmp;
++ char name[16];
++ int u32s;
++
++ sprintf(name, "cma-%d", idx);
++
++ tmp = debugfs_create_dir(name, cma_debugfs_root);
++
++ debugfs_create_file("base_pfn", S_IRUGO, tmp,
++ &cma->base_pfn, &cma_debugfs_fops);
++ debugfs_create_file("count", S_IRUGO, tmp,
++ &cma->count, &cma_debugfs_fops);
++ debugfs_create_file("order_per_bit", S_IRUGO, tmp,
++ &cma->order_per_bit, &cma_debugfs_fops);
++
++ u32s = DIV_ROUND_UP(cma_bitmap_maxno(cma), BITS_PER_BYTE * sizeof(u32));
++ debugfs_create_u32_array("bitmap", S_IRUGO, tmp, (u32*)cma->bitmap, u32s);
++}
++
++static int __init cma_debugfs_init(void)
++{
++ int i;
++
++ cma_debugfs_root = debugfs_create_dir("cma", NULL);
++ if (!cma_debugfs_root)
++ return -ENOMEM;
++
++ for (i = 0; i < cma_area_count; i++)
++ cma_debugfs_add_one(&cma_areas[i], i);
++
++ return 0;
++}
++late_initcall(cma_debugfs_init);
+diff -Nur linux-3.14.72.orig/mm/cma.h linux-3.14.72/mm/cma.h
+--- linux-3.14.72.orig/mm/cma.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/mm/cma.h 2016-06-19 22:11:55.513126359 +0200
+@@ -0,0 +1,20 @@
++#ifndef __MM_CMA_H__
++#define __MM_CMA_H__
++
++struct cma {
++ unsigned long base_pfn;
++ unsigned long count;
++ unsigned long *bitmap;
++ unsigned int order_per_bit; /* Order of pages represented by one bit */
++ struct mutex lock;
++};
++
++extern struct cma cma_areas[MAX_CMA_AREAS];
++extern unsigned cma_area_count;
++
++static unsigned long cma_bitmap_maxno(struct cma *cma)
++{
++ return cma->count >> cma->order_per_bit;
++}
++
++#endif
+diff -Nur linux-3.14.72.orig/mm/early_ioremap.c linux-3.14.72/mm/early_ioremap.c
+--- linux-3.14.72.orig/mm/early_ioremap.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/mm/early_ioremap.c 2016-06-19 22:11:55.513126359 +0200
+@@ -0,0 +1,245 @@
++/*
++ * Provide common bits of early_ioremap() support for architectures needing
++ * temporary mappings during boot before ioremap() is available.
++ *
++ * This is mostly a direct copy of the x86 early_ioremap implementation.
++ *
++ * (C) Copyright 1995 1996, 2014 Linus Torvalds
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/mm.h>
++#include <linux/vmalloc.h>
++#include <asm/fixmap.h>
++
++#ifdef CONFIG_MMU
++static int early_ioremap_debug __initdata;
++
++static int __init early_ioremap_debug_setup(char *str)
++{
++ early_ioremap_debug = 1;
++
++ return 0;
++}
++early_param("early_ioremap_debug", early_ioremap_debug_setup);
++
++static int after_paging_init __initdata;
++
++void __init __weak early_ioremap_shutdown(void)
++{
++}
++
++void __init early_ioremap_reset(void)
++{
++ early_ioremap_shutdown();
++ after_paging_init = 1;
++}
++
++/*
++ * Generally, ioremap() is available after paging_init() has been called.
++ * Architectures wanting to allow early_ioremap after paging_init() can
++ * define __late_set_fixmap and __late_clear_fixmap to do the right thing.
++ */
++#ifndef __late_set_fixmap
++static inline void __init __late_set_fixmap(enum fixed_addresses idx,
++ phys_addr_t phys, pgprot_t prot)
++{
++ BUG();
++}
++#endif
++
++#ifndef __late_clear_fixmap
++static inline void __init __late_clear_fixmap(enum fixed_addresses idx)
++{
++ BUG();
++}
++#endif
++
++static void __iomem *prev_map[FIX_BTMAPS_SLOTS] __initdata;
++static unsigned long prev_size[FIX_BTMAPS_SLOTS] __initdata;
++static unsigned long slot_virt[FIX_BTMAPS_SLOTS] __initdata;
++
++void __init early_ioremap_setup(void)
++{
++ int i;
++
++ for (i = 0; i < FIX_BTMAPS_SLOTS; i++)
++ if (WARN_ON(prev_map[i]))
++ break;
++
++ for (i = 0; i < FIX_BTMAPS_SLOTS; i++)
++ slot_virt[i] = __fix_to_virt(FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*i);
++}
++
++static int __init check_early_ioremap_leak(void)
++{
++ int count = 0;
++ int i;
++
++ for (i = 0; i < FIX_BTMAPS_SLOTS; i++)
++ if (prev_map[i])
++ count++;
++
++ if (WARN(count, KERN_WARNING
++ "Debug warning: early ioremap leak of %d areas detected.\n"
++ "please boot with early_ioremap_debug and report the dmesg.\n",
++ count))
++ return 1;
++ return 0;
++}
++late_initcall(check_early_ioremap_leak);
++
++static void __init __iomem *
++__early_ioremap(resource_size_t phys_addr, unsigned long size, pgprot_t prot)
++{
++ unsigned long offset;
++ resource_size_t last_addr;
++ unsigned int nrpages;
++ enum fixed_addresses idx;
++ int i, slot;
++
++ WARN_ON(system_state != SYSTEM_BOOTING);
++
++ slot = -1;
++ for (i = 0; i < FIX_BTMAPS_SLOTS; i++) {
++ if (!prev_map[i]) {
++ slot = i;
++ break;
++ }
++ }
++
++ if (WARN(slot < 0, "%s(%08llx, %08lx) not found slot\n",
++ __func__, (u64)phys_addr, size))
++ return NULL;
++
++ /* Don't allow wraparound or zero size */
++ last_addr = phys_addr + size - 1;
++ if (WARN_ON(!size || last_addr < phys_addr))
++ return NULL;
++
++ prev_size[slot] = size;
++ /*
++ * Mappings have to be page-aligned
++ */
++ offset = phys_addr & ~PAGE_MASK;
++ phys_addr &= PAGE_MASK;
++ size = PAGE_ALIGN(last_addr + 1) - phys_addr;
++
++ /*
++ * Mappings have to fit in the FIX_BTMAP area.
++ */
++ nrpages = size >> PAGE_SHIFT;
++ if (WARN_ON(nrpages > NR_FIX_BTMAPS))
++ return NULL;
++
++ /*
++ * Ok, go for it..
++ */
++ idx = FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*slot;
++ while (nrpages > 0) {
++ if (after_paging_init)
++ __late_set_fixmap(idx, phys_addr, prot);
++ else
++ __early_set_fixmap(idx, phys_addr, prot);
++ phys_addr += PAGE_SIZE;
++ --idx;
++ --nrpages;
++ }
++ WARN(early_ioremap_debug, "%s(%08llx, %08lx) [%d] => %08lx + %08lx\n",
++ __func__, (u64)phys_addr, size, slot, offset, slot_virt[slot]);
++
++ prev_map[slot] = (void __iomem *)(offset + slot_virt[slot]);
++ return prev_map[slot];
++}
++
++void __init early_iounmap(void __iomem *addr, unsigned long size)
++{
++ unsigned long virt_addr;
++ unsigned long offset;
++ unsigned int nrpages;
++ enum fixed_addresses idx;
++ int i, slot;
++
++ slot = -1;
++ for (i = 0; i < FIX_BTMAPS_SLOTS; i++) {
++ if (prev_map[i] == addr) {
++ slot = i;
++ break;
++ }
++ }
++
++ if (WARN(slot < 0, "early_iounmap(%p, %08lx) not found slot\n",
++ addr, size))
++ return;
++
++ if (WARN(prev_size[slot] != size,
++ "early_iounmap(%p, %08lx) [%d] size not consistent %08lx\n",
++ addr, size, slot, prev_size[slot]))
++ return;
++
++ WARN(early_ioremap_debug, "early_iounmap(%p, %08lx) [%d]\n",
++ addr, size, slot);
++
++ virt_addr = (unsigned long)addr;
++ if (WARN_ON(virt_addr < fix_to_virt(FIX_BTMAP_BEGIN)))
++ return;
++
++ offset = virt_addr & ~PAGE_MASK;
++ nrpages = PAGE_ALIGN(offset + size) >> PAGE_SHIFT;
++
++ idx = FIX_BTMAP_BEGIN - NR_FIX_BTMAPS*slot;
++ while (nrpages > 0) {
++ if (after_paging_init)
++ __late_clear_fixmap(idx);
++ else
++ __early_set_fixmap(idx, 0, FIXMAP_PAGE_CLEAR);
++ --idx;
++ --nrpages;
++ }
++ prev_map[slot] = NULL;
++}
++
++/* Remap an IO device */
++void __init __iomem *
++early_ioremap(resource_size_t phys_addr, unsigned long size)
++{
++ return __early_ioremap(phys_addr, size, FIXMAP_PAGE_IO);
++}
++
++/* Remap memory */
++void __init *
++early_memremap(resource_size_t phys_addr, unsigned long size)
++{
++ return (__force void *)__early_ioremap(phys_addr, size,
++ FIXMAP_PAGE_NORMAL);
++}
++#else /* CONFIG_MMU */
++
++void __init __iomem *
++early_ioremap(resource_size_t phys_addr, unsigned long size)
++{
++ return (__force void __iomem *)phys_addr;
++}
++
++/* Remap memory */
++void __init *
++early_memremap(resource_size_t phys_addr, unsigned long size)
++{
++ return (void *)phys_addr;
++}
++
++void __init early_iounmap(void __iomem *addr, unsigned long size)
++{
++}
++
++#endif /* CONFIG_MMU */
++
++
++void __init early_memunmap(void *addr, unsigned long size)
++{
++ early_iounmap((__force void __iomem *)addr, size);
++}
+diff -Nur linux-3.14.72.orig/mm/huge_memory.c linux-3.14.72/mm/huge_memory.c
+--- linux-3.14.72.orig/mm/huge_memory.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/mm/huge_memory.c 2016-06-19 22:11:55.513126359 +0200
+@@ -1725,7 +1725,7 @@
+ &page_tail->_count);
+
+ /* after clearing PageTail the gup refcount can be released */
+- smp_mb();
++ smp_mb__after_atomic();
+
+ /*
+ * retain hwpoison flag of the poisoned tail page:
+diff -Nur linux-3.14.72.orig/mm/Kconfig linux-3.14.72/mm/Kconfig
+--- linux-3.14.72.orig/mm/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/mm/Kconfig 2016-06-19 22:11:55.513126359 +0200
+@@ -514,6 +514,23 @@
+ processing calls such as dma_alloc_from_contiguous().
+ This option does not affect warning and error messages.
+
++config CMA_DEBUGFS
++ bool "CMA debugfs interface"
++ depends on CMA && DEBUG_FS
++ help
++ Turns on the DebugFS interface for CMA.
++
++config CMA_AREAS
++ int "Maximum count of the CMA areas"
++ depends on CMA
++ default 7
++ help
++ CMA allows to create CMA areas for particular purpose, mainly,
++ used as device private area. This parameter sets the maximum
++ number of CMA area in the system.
++
++ If unsure, leave the default value "7".
++
+ config ZBUD
+ tristate
+ default n
+@@ -581,6 +598,9 @@
+ You can check speed with zsmalloc benchmark:
+ https://github.com/spartacus06/zsmapbench
+
++config GENERIC_EARLY_IOREMAP
++ bool
++
+ config MAX_STACK_SIZE_MB
+ int "Maximum user stack size for 32-bit processes (MB)"
+ default 80
+diff -Nur linux-3.14.72.orig/mm/Makefile linux-3.14.72/mm/Makefile
+--- linux-3.14.72.orig/mm/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/mm/Makefile 2016-06-19 22:11:55.517126096 +0200
+@@ -61,3 +61,6 @@
+ obj-$(CONFIG_MEMORY_ISOLATION) += page_isolation.o
+ obj-$(CONFIG_ZBUD) += zbud.o
+ obj-$(CONFIG_ZSMALLOC) += zsmalloc.o
++obj-$(CONFIG_GENERIC_EARLY_IOREMAP) += early_ioremap.o
++obj-$(CONFIG_CMA) += cma.o
++obj-$(CONFIG_CMA_DEBUGFS) += cma_debug.o
+diff -Nur linux-3.14.72.orig/mm/memblock.c linux-3.14.72/mm/memblock.c
+--- linux-3.14.72.orig/mm/memblock.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/mm/memblock.c 2016-06-19 22:11:55.517126096 +0200
+@@ -974,22 +974,35 @@
+ }
+ #endif /* CONFIG_HAVE_MEMBLOCK_NODE_MAP */
+
+-static phys_addr_t __init memblock_alloc_base_nid(phys_addr_t size,
+- phys_addr_t align, phys_addr_t max_addr,
+- int nid)
++static phys_addr_t __init memblock_alloc_range_nid(phys_addr_t size,
++ phys_addr_t align, phys_addr_t start,
++ phys_addr_t end, int nid)
+ {
+ phys_addr_t found;
+
+ if (!align)
+ align = SMP_CACHE_BYTES;
+
+- found = memblock_find_in_range_node(size, align, 0, max_addr, nid);
++ found = memblock_find_in_range_node(size, align, start, end, nid);
+ if (found && !memblock_reserve(found, size))
+ return found;
+
+ return 0;
+ }
+
++phys_addr_t __init memblock_alloc_range(phys_addr_t size, phys_addr_t align,
++ phys_addr_t start, phys_addr_t end)
++{
++ return memblock_alloc_range_nid(size, align, start, end, NUMA_NO_NODE);
++}
++
++static phys_addr_t __init memblock_alloc_base_nid(phys_addr_t size,
++ phys_addr_t align, phys_addr_t max_addr,
++ int nid)
++{
++ return memblock_alloc_range_nid(size, align, 0, max_addr, nid);
++}
++
+ phys_addr_t __init memblock_alloc_nid(phys_addr_t size, phys_addr_t align, int nid)
+ {
+ return memblock_alloc_base_nid(size, align, MEMBLOCK_ALLOC_ACCESSIBLE, nid);
+diff -Nur linux-3.14.72.orig/mm/page_alloc.c linux-3.14.72/mm/page_alloc.c
+--- linux-3.14.72.orig/mm/page_alloc.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/mm/page_alloc.c 2016-06-19 22:11:55.517126096 +0200
+@@ -1073,39 +1073,34 @@
+ }
+
+ /*
+- * If breaking a large block of pages, move all free pages to the preferred
+- * allocation list. If falling back for a reclaimable kernel allocation, be
+- * more aggressive about taking ownership of free pages.
++ * When we are falling back to another migratetype during allocation, try to
++ * steal extra free pages from the same pageblocks to satisfy further
++ * allocations, instead of polluting multiple pageblocks.
+ *
+- * On the other hand, never change migration type of MIGRATE_CMA pageblocks
+- * nor move CMA pages to different free lists. We don't want unmovable pages
+- * to be allocated from MIGRATE_CMA areas.
++ * If we are stealing a relatively large buddy page, it is likely there will
++ * be more free pages in the pageblock, so try to steal them all. For
++ * reclaimable and unmovable allocations, we steal regardless of page size,
++ * as fragmentation caused by those allocations polluting movable pageblocks
++ * is worse than movable allocations stealing from unmovable and reclaimable
++ * pageblocks.
+ *
+- * Returns the allocation migratetype if free pages were stolen, or the
+- * fallback migratetype if it was decided not to steal.
++ * If we claim more than half of the pageblock, change pageblock's migratetype
++ * as well.
+ */
+-static int try_to_steal_freepages(struct zone *zone, struct page *page,
++static void try_to_steal_freepages(struct zone *zone, struct page *page,
+ int start_type, int fallback_type)
+ {
+ int current_order = page_order(page);
+
+- /*
+- * When borrowing from MIGRATE_CMA, we need to release the excess
+- * buddy pages to CMA itself. We also ensure the freepage_migratetype
+- * is set to CMA so it is returned to the correct freelist in case
+- * the page ends up being not actually allocated from the pcp lists.
+- */
+- if (is_migrate_cma(fallback_type))
+- return fallback_type;
+-
+ /* Take ownership for orders >= pageblock_order */
+ if (current_order >= pageblock_order) {
+ change_pageblock_range(page, current_order, start_type);
+- return start_type;
++ return;
+ }
+
+ if (current_order >= pageblock_order / 2 ||
+ start_type == MIGRATE_RECLAIMABLE ||
++ start_type == MIGRATE_UNMOVABLE ||
+ page_group_by_mobility_disabled) {
+ int pages;
+
+@@ -1115,11 +1110,7 @@
+ if (pages >= (1 << (pageblock_order-1)) ||
+ page_group_by_mobility_disabled)
+ set_pageblock_migratetype(page, start_type);
+-
+- return start_type;
+ }
+-
+- return fallback_type;
+ }
+
+ /* Remove an element from the buddy allocator from the fallback list */
+@@ -1129,14 +1120,15 @@
+ struct free_area *area;
+ unsigned int current_order;
+ struct page *page;
+- int migratetype, new_type, i;
+
+ /* Find the largest possible block of pages in the other list */
+ for (current_order = MAX_ORDER-1;
+ current_order >= order && current_order <= MAX_ORDER-1;
+ --current_order) {
++ int i;
+ for (i = 0;; i++) {
+- migratetype = fallbacks[start_migratetype][i];
++ int migratetype = fallbacks[start_migratetype][i];
++ int buddy_type = start_migratetype;
+
+ /* MIGRATE_RESERVE handled later if necessary */
+ if (migratetype == MIGRATE_RESERVE)
+@@ -1150,22 +1142,36 @@
+ struct page, lru);
+ area->nr_free--;
+
+- new_type = try_to_steal_freepages(zone, page,
+- start_migratetype,
+- migratetype);
++ if (!is_migrate_cma(migratetype)) {
++ try_to_steal_freepages(zone, page,
++ start_migratetype,
++ migratetype);
++ } else {
++ /*
++ * When borrowing from MIGRATE_CMA, we need to
++ * release the excess buddy pages to CMA
++ * itself, and we do not try to steal extra
++ * free pages.
++ */
++ buddy_type = migratetype;
++ }
+
+ /* Remove the page from the freelists */
+ list_del(&page->lru);
+ rmv_page_order(page);
+
+ expand(zone, page, order, current_order, area,
+- new_type);
+- /* The freepage_migratetype may differ from pageblock's
++ buddy_type);
++
++ /*
++ * The freepage_migratetype may differ from pageblock's
+ * migratetype depending on the decisions in
+- * try_to_steal_freepages. This is OK as long as it does
+- * not differ for MIGRATE_CMA type.
++ * try_to_steal_freepages(). This is OK as long as it
++ * does not differ for MIGRATE_CMA pageblocks. For CMA
++ * we need to make sure unallocated pages flushed from
++ * pcp lists are returned to the correct freelist.
+ */
+- set_freepage_migratetype(page, new_type);
++ set_freepage_migratetype(page, buddy_type);
+
+ trace_mm_page_alloc_extfrag(page, order, current_order,
+ start_migratetype, migratetype);
+diff -Nur linux-3.14.72.orig/net/core/ethtool.c linux-3.14.72/net/core/ethtool.c
+--- linux-3.14.72.orig/net/core/ethtool.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/net/core/ethtool.c 2016-06-19 22:11:55.517126096 +0200
+@@ -556,6 +556,23 @@
+ return ret;
+ }
+
++static int ethtool_copy_validate_indir(u32 *indir, void __user *useraddr,
++ struct ethtool_rxnfc *rx_rings,
++ u32 size)
++{
++ int ret = 0, i;
++
++ if (copy_from_user(indir, useraddr, size * sizeof(indir[0])))
++ ret = -EFAULT;
++
++ /* Validate ring indices */
++ for (i = 0; i < size; i++) {
++ if (indir[i] >= rx_rings->data)
++ ret = -EINVAL;
++ }
++ return ret;
++}
++
+ static noinline_for_stack int ethtool_get_rxfh_indir(struct net_device *dev,
+ void __user *useraddr)
+ {
+@@ -612,6 +629,7 @@
+ u32 *indir;
+ const struct ethtool_ops *ops = dev->ethtool_ops;
+ int ret;
++ u32 ringidx_offset = offsetof(struct ethtool_rxfh_indir, ring_index[0]);
+
+ if (!ops->get_rxfh_indir_size || !ops->set_rxfh_indir ||
+ !ops->get_rxnfc)
+@@ -642,28 +660,198 @@
+ for (i = 0; i < dev_size; i++)
+ indir[i] = ethtool_rxfh_indir_default(i, rx_rings.data);
+ } else {
+- if (copy_from_user(indir,
+- useraddr +
+- offsetof(struct ethtool_rxfh_indir,
+- ring_index[0]),
+- dev_size * sizeof(indir[0]))) {
++ ret = ethtool_copy_validate_indir(indir,
++ useraddr + ringidx_offset,
++ &rx_rings,
++ dev_size);
++ if (ret)
++ goto out;
++ }
++
++ ret = ops->set_rxfh_indir(dev, indir);
++
++out:
++ kfree(indir);
++ return ret;
++}
++
++static noinline_for_stack int ethtool_get_rxfh(struct net_device *dev,
++ void __user *useraddr)
++{
++ int ret;
++ const struct ethtool_ops *ops = dev->ethtool_ops;
++ u32 user_indir_size = 0, user_key_size = 0;
++ u32 dev_indir_size = 0, dev_key_size = 0;
++ u32 total_size;
++ u32 indir_offset, indir_bytes;
++ u32 key_offset;
++ u32 *indir = NULL;
++ u8 *hkey = NULL;
++ u8 *rss_config;
++
++ if (!(dev->ethtool_ops->get_rxfh_indir_size ||
++ dev->ethtool_ops->get_rxfh_key_size) ||
++ !dev->ethtool_ops->get_rxfh)
++ return -EOPNOTSUPP;
++
++ if (ops->get_rxfh_indir_size)
++ dev_indir_size = ops->get_rxfh_indir_size(dev);
++
++ indir_offset = offsetof(struct ethtool_rxfh, indir_size);
++
++ if (copy_from_user(&user_indir_size,
++ useraddr + indir_offset,
++ sizeof(user_indir_size)))
++ return -EFAULT;
++
++ if (copy_to_user(useraddr + indir_offset,
++ &dev_indir_size, sizeof(dev_indir_size)))
++ return -EFAULT;
++
++ if (ops->get_rxfh_key_size)
++ dev_key_size = ops->get_rxfh_key_size(dev);
++
++ if ((dev_key_size + dev_indir_size) == 0)
++ return -EOPNOTSUPP;
++
++ key_offset = offsetof(struct ethtool_rxfh, key_size);
++
++ if (copy_from_user(&user_key_size,
++ useraddr + key_offset,
++ sizeof(user_key_size)))
++ return -EFAULT;
++
++ if (copy_to_user(useraddr + key_offset,
++ &dev_key_size, sizeof(dev_key_size)))
++ return -EFAULT;
++
++ /* If the user buffer size is 0, this is just a query for the
++ * device table size and key size. Otherwise, if the User size is
++ * not equal to device table size or key size it's an error.
++ */
++ if (!user_indir_size && !user_key_size)
++ return 0;
++
++ if ((user_indir_size && (user_indir_size != dev_indir_size)) ||
++ (user_key_size && (user_key_size != dev_key_size)))
++ return -EINVAL;
++
++ indir_bytes = user_indir_size * sizeof(indir[0]);
++ total_size = indir_bytes + user_key_size;
++ rss_config = kzalloc(total_size, GFP_USER);
++ if (!rss_config)
++ return -ENOMEM;
++
++ if (user_indir_size)
++ indir = (u32 *)rss_config;
++
++ if (user_key_size)
++ hkey = rss_config + indir_bytes;
++
++ ret = dev->ethtool_ops->get_rxfh(dev, indir, hkey);
++ if (!ret) {
++ if (copy_to_user(useraddr +
++ offsetof(struct ethtool_rxfh, rss_config[0]),
++ rss_config, total_size))
+ ret = -EFAULT;
++ }
++
++ kfree(rss_config);
++
++ return ret;
++}
++
++static noinline_for_stack int ethtool_set_rxfh(struct net_device *dev,
++ void __user *useraddr)
++{
++ int ret;
++ const struct ethtool_ops *ops = dev->ethtool_ops;
++ struct ethtool_rxnfc rx_rings;
++ u32 user_indir_size = 0, dev_indir_size = 0, i;
++ u32 user_key_size = 0, dev_key_size = 0;
++ u32 *indir = NULL, indir_bytes = 0;
++ u8 *hkey = NULL;
++ u8 *rss_config;
++ u32 indir_offset, key_offset;
++ u32 rss_cfg_offset = offsetof(struct ethtool_rxfh, rss_config[0]);
++
++ if (!(ops->get_rxfh_indir_size || ops->get_rxfh_key_size) ||
++ !ops->get_rxnfc || !ops->set_rxfh)
++ return -EOPNOTSUPP;
++
++ if (ops->get_rxfh_indir_size)
++ dev_indir_size = ops->get_rxfh_indir_size(dev);
++
++ indir_offset = offsetof(struct ethtool_rxfh, indir_size);
++ if (copy_from_user(&user_indir_size,
++ useraddr + indir_offset,
++ sizeof(user_indir_size)))
++ return -EFAULT;
++
++ if (ops->get_rxfh_key_size)
++ dev_key_size = dev->ethtool_ops->get_rxfh_key_size(dev);
++
++ if ((dev_key_size + dev_indir_size) == 0)
++ return -EOPNOTSUPP;
++
++ key_offset = offsetof(struct ethtool_rxfh, key_size);
++ if (copy_from_user(&user_key_size,
++ useraddr + key_offset,
++ sizeof(user_key_size)))
++ return -EFAULT;
++
++ /* If either indir or hash key is valid, proceed further.
++ */
++ if ((user_indir_size &&
++ user_indir_size != ETH_RXFH_INDIR_NO_CHANGE &&
++ user_indir_size != dev_indir_size) ||
++ (user_key_size && (user_key_size != dev_key_size)))
++ return -EINVAL;
++
++ if (user_indir_size != ETH_RXFH_INDIR_NO_CHANGE)
++ indir_bytes = dev_indir_size * sizeof(indir[0]);
++
++ rss_config = kzalloc(indir_bytes + user_key_size, GFP_USER);
++ if (!rss_config)
++ return -ENOMEM;
++
++ rx_rings.cmd = ETHTOOL_GRXRINGS;
++ ret = ops->get_rxnfc(dev, &rx_rings, NULL);
++ if (ret)
++ goto out;
++
++ /* user_indir_size == 0 means reset the indir table to default.
++ * user_indir_size == ETH_RXFH_INDIR_NO_CHANGE means leave it unchanged.
++ */
++ if (user_indir_size &&
++ user_indir_size != ETH_RXFH_INDIR_NO_CHANGE) {
++ indir = (u32 *)rss_config;
++ ret = ethtool_copy_validate_indir(indir,
++ useraddr + rss_cfg_offset,
++ &rx_rings,
++ user_indir_size);
++ if (ret)
+ goto out;
+- }
++ } else if (user_indir_size == 0) {
++ indir = (u32 *)rss_config;
++ for (i = 0; i < dev_indir_size; i++)
++ indir[i] = ethtool_rxfh_indir_default(i, rx_rings.data);
++ }
+
+- /* Validate ring indices */
+- for (i = 0; i < dev_size; i++) {
+- if (indir[i] >= rx_rings.data) {
+- ret = -EINVAL;
+- goto out;
+- }
++ if (user_key_size) {
++ hkey = rss_config + indir_bytes;
++ if (copy_from_user(hkey,
++ useraddr + rss_cfg_offset + indir_bytes,
++ user_key_size)) {
++ ret = -EFAULT;
++ goto out;
+ }
+ }
+
+- ret = ops->set_rxfh_indir(dev, indir);
++ ret = ops->set_rxfh(dev, indir, hkey);
+
+ out:
+- kfree(indir);
++ kfree(rss_config);
+ return ret;
+ }
+
+@@ -1446,6 +1634,80 @@
+ modinfo.eeprom_len);
+ }
+
++static int ethtool_tunable_valid(const struct ethtool_tunable *tuna)
++{
++ switch (tuna->id) {
++ case ETHTOOL_RX_COPYBREAK:
++ if (tuna->len != sizeof(u32) ||
++ tuna->type_id != ETHTOOL_TUNABLE_U32)
++ return -EINVAL;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int ethtool_get_tunable(struct net_device *dev, void __user *useraddr)
++{
++ int ret;
++ struct ethtool_tunable tuna;
++ const struct ethtool_ops *ops = dev->ethtool_ops;
++ void *data;
++
++ if (!ops->get_tunable)
++ return -EOPNOTSUPP;
++ if (copy_from_user(&tuna, useraddr, sizeof(tuna)))
++ return -EFAULT;
++ ret = ethtool_tunable_valid(&tuna);
++ if (ret)
++ return ret;
++ data = kmalloc(tuna.len, GFP_USER);
++ if (!data)
++ return -ENOMEM;
++ ret = ops->get_tunable(dev, &tuna, data);
++ if (ret)
++ goto out;
++ useraddr += sizeof(tuna);
++ ret = -EFAULT;
++ if (copy_to_user(useraddr, data, tuna.len))
++ goto out;
++ ret = 0;
++
++out:
++ kfree(data);
++ return ret;
++}
++
++static int ethtool_set_tunable(struct net_device *dev, void __user *useraddr)
++{
++ int ret;
++ struct ethtool_tunable tuna;
++ const struct ethtool_ops *ops = dev->ethtool_ops;
++ void *data;
++
++ if (!ops->set_tunable)
++ return -EOPNOTSUPP;
++ if (copy_from_user(&tuna, useraddr, sizeof(tuna)))
++ return -EFAULT;
++ ret = ethtool_tunable_valid(&tuna);
++ if (ret)
++ return ret;
++ data = kmalloc(tuna.len, GFP_USER);
++ if (!data)
++ return -ENOMEM;
++ useraddr += sizeof(tuna);
++ ret = -EFAULT;
++ if (copy_from_user(data, useraddr, tuna.len))
++ goto out;
++ ret = ops->set_tunable(dev, &tuna, data);
++
++out:
++ kfree(data);
++ return ret;
++}
++
+ /* The main entry point in this file. Called from net/core/dev_ioctl.c */
+
+ int dev_ethtool(struct net *net, struct ifreq *ifr)
+@@ -1490,10 +1752,12 @@
+ case ETHTOOL_GRXCLSRULE:
+ case ETHTOOL_GRXCLSRLALL:
+ case ETHTOOL_GRXFHINDIR:
++ case ETHTOOL_GRSSH:
+ case ETHTOOL_GFEATURES:
+ case ETHTOOL_GCHANNELS:
+ case ETHTOOL_GET_TS_INFO:
+ case ETHTOOL_GEEE:
++ case ETHTOOL_GTUNABLE:
+ break;
+ default:
+ if (!ns_capable(net->user_ns, CAP_NET_ADMIN))
+@@ -1627,6 +1891,12 @@
+ case ETHTOOL_SRXFHINDIR:
+ rc = ethtool_set_rxfh_indir(dev, useraddr);
+ break;
++ case ETHTOOL_GRSSH:
++ rc = ethtool_get_rxfh(dev, useraddr);
++ break;
++ case ETHTOOL_SRSSH:
++ rc = ethtool_set_rxfh(dev, useraddr);
++ break;
+ case ETHTOOL_GFEATURES:
+ rc = ethtool_get_features(dev, useraddr);
+ break;
+@@ -1675,6 +1945,12 @@
+ case ETHTOOL_GMODULEEEPROM:
+ rc = ethtool_get_module_eeprom(dev, useraddr);
+ break;
++ case ETHTOOL_GTUNABLE:
++ rc = ethtool_get_tunable(dev, useraddr);
++ break;
++ case ETHTOOL_STUNABLE:
++ rc = ethtool_set_tunable(dev, useraddr);
++ break;
+ default:
+ rc = -EOPNOTSUPP;
+ }
+diff -Nur linux-3.14.72.orig/net/core/Makefile linux-3.14.72/net/core/Makefile
+--- linux-3.14.72.orig/net/core/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/net/core/Makefile 2016-06-19 22:11:55.517126096 +0200
+@@ -9,7 +9,7 @@
+
+ obj-y += dev.o ethtool.o dev_addr_lists.o dst.o netevent.o \
+ neighbour.o rtnetlink.o utils.o link_watch.o filter.o \
+- sock_diag.o dev_ioctl.o
++ sock_diag.o dev_ioctl.o tso.o
+
+ obj-$(CONFIG_XFRM) += flow.o
+ obj-y += net-sysfs.o
+diff -Nur linux-3.14.72.orig/net/core/tso.c linux-3.14.72/net/core/tso.c
+--- linux-3.14.72.orig/net/core/tso.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/net/core/tso.c 2016-06-19 22:11:55.517126096 +0200
+@@ -0,0 +1,77 @@
++#include <linux/export.h>
++#include <net/ip.h>
++#include <net/tso.h>
++
++/* Calculate expected number of TX descriptors */
++int tso_count_descs(struct sk_buff *skb)
++{
++ /* The Marvell Way */
++ return skb_shinfo(skb)->gso_segs * 2 + skb_shinfo(skb)->nr_frags;
++}
++EXPORT_SYMBOL(tso_count_descs);
++
++void tso_build_hdr(struct sk_buff *skb, char *hdr, struct tso_t *tso,
++ int size, bool is_last)
++{
++ struct iphdr *iph;
++ struct tcphdr *tcph;
++ int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
++ int mac_hdr_len = skb_network_offset(skb);
++
++ memcpy(hdr, skb->data, hdr_len);
++ iph = (struct iphdr *)(hdr + mac_hdr_len);
++ iph->id = htons(tso->ip_id);
++ iph->tot_len = htons(size + hdr_len - mac_hdr_len);
++ tcph = (struct tcphdr *)(hdr + skb_transport_offset(skb));
++ tcph->seq = htonl(tso->tcp_seq);
++ tso->ip_id++;
++
++ if (!is_last) {
++ /* Clear all special flags for not last packet */
++ tcph->psh = 0;
++ tcph->fin = 0;
++ tcph->rst = 0;
++ }
++}
++EXPORT_SYMBOL(tso_build_hdr);
++
++void tso_build_data(struct sk_buff *skb, struct tso_t *tso, int size)
++{
++ tso->tcp_seq += size;
++ tso->size -= size;
++ tso->data += size;
++
++ if ((tso->size == 0) &&
++ (tso->next_frag_idx < skb_shinfo(skb)->nr_frags)) {
++ skb_frag_t *frag = &skb_shinfo(skb)->frags[tso->next_frag_idx];
++
++ /* Move to next segment */
++ tso->size = frag->size;
++ tso->data = page_address(frag->page.p) + frag->page_offset;
++ tso->next_frag_idx++;
++ }
++}
++EXPORT_SYMBOL(tso_build_data);
++
++void tso_start(struct sk_buff *skb, struct tso_t *tso)
++{
++ int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
++
++ tso->ip_id = ntohs(ip_hdr(skb)->id);
++ tso->tcp_seq = ntohl(tcp_hdr(skb)->seq);
++ tso->next_frag_idx = 0;
++
++ /* Build first data */
++ tso->size = skb_headlen(skb) - hdr_len;
++ tso->data = skb->data + hdr_len;
++ if ((tso->size == 0) &&
++ (tso->next_frag_idx < skb_shinfo(skb)->nr_frags)) {
++ skb_frag_t *frag = &skb_shinfo(skb)->frags[tso->next_frag_idx];
++
++ /* Move to next segment */
++ tso->size = frag->size;
++ tso->data = page_address(frag->page.p) + frag->page_offset;
++ tso->next_frag_idx++;
++ }
++}
++EXPORT_SYMBOL(tso_start);
+diff -Nur linux-3.14.72.orig/net/mac80211/ibss.c linux-3.14.72/net/mac80211/ibss.c
+--- linux-3.14.72.orig/net/mac80211/ibss.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/net/mac80211/ibss.c 2016-06-19 22:11:55.517126096 +0200
+@@ -386,7 +386,7 @@
+ presp->head_len, 0, GFP_KERNEL);
+ cfg80211_put_bss(local->hw.wiphy, bss);
+ netif_carrier_on(sdata->dev);
+- cfg80211_ibss_joined(sdata->dev, ifibss->bssid, GFP_KERNEL);
++ cfg80211_ibss_joined(sdata->dev, ifibss->bssid, chan, GFP_KERNEL);
+ }
+
+ static void ieee80211_sta_join_ibss(struct ieee80211_sub_if_data *sdata,
+diff -Nur linux-3.14.72.orig/net/wireless/core.h linux-3.14.72/net/wireless/core.h
+--- linux-3.14.72.orig/net/wireless/core.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/net/wireless/core.h 2016-06-19 22:11:55.517126096 +0200
+@@ -211,6 +211,7 @@
+ } dc;
+ struct {
+ u8 bssid[ETH_ALEN];
++ struct ieee80211_channel *channel;
+ } ij;
+ };
+ };
+@@ -258,7 +259,8 @@
+ struct net_device *dev, bool nowext);
+ int cfg80211_leave_ibss(struct cfg80211_registered_device *rdev,
+ struct net_device *dev, bool nowext);
+-void __cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid);
++void __cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid,
++ struct ieee80211_channel *channel);
+ int cfg80211_ibss_wext_join(struct cfg80211_registered_device *rdev,
+ struct wireless_dev *wdev);
+
+diff -Nur linux-3.14.72.orig/net/wireless/ibss.c linux-3.14.72/net/wireless/ibss.c
+--- linux-3.14.72.orig/net/wireless/ibss.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/net/wireless/ibss.c 2016-06-19 22:11:55.517126096 +0200
+@@ -14,7 +14,8 @@
+ #include "rdev-ops.h"
+
+
+-void __cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid)
++void __cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid,
++ struct ieee80211_channel *channel)
+ {
+ struct wireless_dev *wdev = dev->ieee80211_ptr;
+ struct cfg80211_bss *bss;
+@@ -28,8 +29,7 @@
+ if (!wdev->ssid_len)
+ return;
+
+- bss = cfg80211_get_bss(wdev->wiphy, NULL, bssid,
+- wdev->ssid, wdev->ssid_len,
++ bss = cfg80211_get_bss(wdev->wiphy, channel, bssid, NULL, 0,
+ WLAN_CAPABILITY_IBSS, WLAN_CAPABILITY_IBSS);
+
+ if (WARN_ON(!bss))
+@@ -54,21 +54,26 @@
+ #endif
+ }
+
+-void cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid, gfp_t gfp)
++void cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid,
++ struct ieee80211_channel *channel, gfp_t gfp)
+ {
+ struct wireless_dev *wdev = dev->ieee80211_ptr;
+ struct cfg80211_registered_device *rdev = wiphy_to_dev(wdev->wiphy);
+ struct cfg80211_event *ev;
+ unsigned long flags;
+
+- trace_cfg80211_ibss_joined(dev, bssid);
++ trace_cfg80211_ibss_joined(dev, bssid, channel);
++
++ if (WARN_ON(!channel))
++ return;
+
+ ev = kzalloc(sizeof(*ev), gfp);
+ if (!ev)
+ return;
+
+ ev->type = EVENT_IBSS_JOINED;
+- memcpy(ev->cr.bssid, bssid, ETH_ALEN);
++ memcpy(ev->ij.bssid, bssid, ETH_ALEN);
++ ev->ij.channel = channel;
+
+ spin_lock_irqsave(&wdev->event_lock, flags);
+ list_add_tail(&ev->list, &wdev->event_list);
+diff -Nur linux-3.14.72.orig/net/wireless/trace.h linux-3.14.72/net/wireless/trace.h
+--- linux-3.14.72.orig/net/wireless/trace.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/net/wireless/trace.h 2016-06-19 22:11:55.517126096 +0200
+@@ -2279,11 +2279,6 @@
+ TP_printk(NETDEV_PR_FMT ", " MAC_PR_FMT, NETDEV_PR_ARG, MAC_PR_ARG(addr))
+ );
+
+-DEFINE_EVENT(cfg80211_rx_evt, cfg80211_ibss_joined,
+- TP_PROTO(struct net_device *netdev, const u8 *addr),
+- TP_ARGS(netdev, addr)
+-);
+-
+ DEFINE_EVENT(cfg80211_rx_evt, cfg80211_rx_spurious_frame,
+ TP_PROTO(struct net_device *netdev, const u8 *addr),
+ TP_ARGS(netdev, addr)
+@@ -2294,6 +2289,24 @@
+ TP_ARGS(netdev, addr)
+ );
+
++TRACE_EVENT(cfg80211_ibss_joined,
++ TP_PROTO(struct net_device *netdev, const u8 *bssid,
++ struct ieee80211_channel *channel),
++ TP_ARGS(netdev, bssid, channel),
++ TP_STRUCT__entry(
++ NETDEV_ENTRY
++ MAC_ENTRY(bssid)
++ CHAN_ENTRY
++ ),
++ TP_fast_assign(
++ NETDEV_ASSIGN;
++ MAC_ASSIGN(bssid, bssid);
++ CHAN_ASSIGN(channel);
++ ),
++ TP_printk(NETDEV_PR_FMT ", bssid: " MAC_PR_FMT ", " CHAN_PR_FMT,
++ NETDEV_PR_ARG, MAC_PR_ARG(bssid), CHAN_PR_ARG)
++);
++
+ TRACE_EVENT(cfg80211_probe_status,
+ TP_PROTO(struct net_device *netdev, const u8 *addr, u64 cookie,
+ bool acked),
+diff -Nur linux-3.14.72.orig/net/wireless/util.c linux-3.14.72/net/wireless/util.c
+--- linux-3.14.72.orig/net/wireless/util.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/net/wireless/util.c 2016-06-19 22:11:55.517126096 +0200
+@@ -820,7 +820,8 @@
+ ev->dc.reason, true);
+ break;
+ case EVENT_IBSS_JOINED:
+- __cfg80211_ibss_joined(wdev->netdev, ev->ij.bssid);
++ __cfg80211_ibss_joined(wdev->netdev, ev->ij.bssid,
++ ev->ij.channel);
+ break;
+ }
+ wdev_unlock(wdev);
+diff -Nur linux-3.14.72.orig/sound/core/pcm_dmaengine.c linux-3.14.72/sound/core/pcm_dmaengine.c
+--- linux-3.14.72.orig/sound/core/pcm_dmaengine.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/core/pcm_dmaengine.c 2016-06-19 22:11:55.517126096 +0200
+@@ -5,6 +5,7 @@
+ * Based on:
+ * imx-pcm-dma-mx2.c, Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
+ * mxs-pcm.c, Copyright (C) 2011 Freescale Semiconductor, Inc.
++ * imx-pcm-dma.c, Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * ep93xx-pcm.c, Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+@@ -28,13 +29,6 @@
+
+ #include <sound/dmaengine_pcm.h>
+
+-struct dmaengine_pcm_runtime_data {
+- struct dma_chan *dma_chan;
+- dma_cookie_t cookie;
+-
+- unsigned int pos;
+-};
+-
+ static inline struct dmaengine_pcm_runtime_data *substream_to_prtd(
+ const struct snd_pcm_substream *substream)
+ {
+@@ -162,7 +156,10 @@
+ if (!desc)
+ return -ENOMEM;
+
+- desc->callback = dmaengine_pcm_dma_complete;
++ if (prtd->callback)
++ desc->callback = prtd->callback;
++ else
++ desc->callback = dmaengine_pcm_dma_complete;
+ desc->callback_param = substream;
+ prtd->cookie = dmaengine_submit(desc);
+
+@@ -186,20 +183,16 @@
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ ret = dmaengine_pcm_prepare_and_submit(substream);
+ if (ret)
+ return ret;
+ dma_async_issue_pending(prtd->dma_chan);
+ break;
+- case SNDRV_PCM_TRIGGER_RESUME:
+- case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+- dmaengine_resume(prtd->dma_chan);
+- break;
++ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+- dmaengine_pause(prtd->dma_chan);
+- break;
+- case SNDRV_PCM_TRIGGER_STOP:
+ dmaengine_terminate_all(prtd->dma_chan);
+ break;
+ default:
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/cs42xx8.c linux-3.14.72/sound/soc/codecs/cs42xx8.c
+--- linux-3.14.72.orig/sound/soc/codecs/cs42xx8.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/codecs/cs42xx8.c 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,685 @@
++/*
++ * Cirrus Logic CS42448/CS42888 Audio CODEC Digital Audio Interface (DAI) driver
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/pm_runtime.h>
++#include <linux/regulator/consumer.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++
++#include "cs42xx8.h"
++
++#define CS42XX8_NUM_SUPPLIES 4
++static const char *const cs42xx8_supply_names[CS42XX8_NUM_SUPPLIES] = {
++ "VA",
++ "VD",
++ "VLS",
++ "VLC",
++};
++
++#define CS42XX8_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
++ SNDRV_PCM_FMTBIT_S20_3LE | \
++ SNDRV_PCM_FMTBIT_S24_LE | \
++ SNDRV_PCM_FMTBIT_S32_LE)
++
++/* codec private data */
++struct cs42xx8_priv {
++ struct regulator_bulk_data supplies[CS42XX8_NUM_SUPPLIES];
++ const struct cs42xx8_driver_data *drvdata;
++ struct regmap *regmap;
++ struct clk *clk;
++
++ bool slave_mode;
++ unsigned long sysclk;
++ int rate[2];
++};
++
++/* -127.5dB to 0dB with step of 0.5dB */
++static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
++/* -64dB to 24dB with step of 0.5dB */
++static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0);
++
++static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" };
++static const char *const cs42xx8_szc[] = { "Immediate Change", "Zero Cross",
++ "Soft Ramp", "Soft Ramp on Zero Cross" };
++
++static const struct soc_enum adc1_single_enum =
++ SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 4, 2, cs42xx8_adc_single);
++static const struct soc_enum adc2_single_enum =
++ SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 3, 2, cs42xx8_adc_single);
++static const struct soc_enum adc3_single_enum =
++ SOC_ENUM_SINGLE(CS42XX8_ADCCTL, 2, 2, cs42xx8_adc_single);
++static const struct soc_enum dac_szc_enum =
++ SOC_ENUM_SINGLE(CS42XX8_TXCTL, 5, 4, cs42xx8_szc);
++static const struct soc_enum adc_szc_enum =
++ SOC_ENUM_SINGLE(CS42XX8_TXCTL, 0, 4, cs42xx8_szc);
++
++static const struct snd_kcontrol_new cs42xx8_snd_controls[] = {
++ SOC_DOUBLE_R_TLV("DAC1 Playback Volume", CS42XX8_VOLAOUT1,
++ CS42XX8_VOLAOUT2, 0, 0xff, 1, dac_tlv),
++ SOC_DOUBLE_R_TLV("DAC2 Playback Volume", CS42XX8_VOLAOUT3,
++ CS42XX8_VOLAOUT4, 0, 0xff, 1, dac_tlv),
++ SOC_DOUBLE_R_TLV("DAC3 Playback Volume", CS42XX8_VOLAOUT5,
++ CS42XX8_VOLAOUT6, 0, 0xff, 1, dac_tlv),
++ SOC_DOUBLE_R_TLV("DAC4 Playback Volume", CS42XX8_VOLAOUT7,
++ CS42XX8_VOLAOUT8, 0, 0xff, 1, dac_tlv),
++ SOC_DOUBLE_R_S_TLV("ADC1 Capture Volume", CS42XX8_VOLAIN1,
++ CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv),
++ SOC_DOUBLE_R_S_TLV("ADC2 Capture Volume", CS42XX8_VOLAIN3,
++ CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv),
++ SOC_DOUBLE("DAC1 Invert Switch", CS42XX8_DACINV, 0, 1, 1, 0),
++ SOC_DOUBLE("DAC2 Invert Switch", CS42XX8_DACINV, 2, 3, 1, 0),
++ SOC_DOUBLE("DAC3 Invert Switch", CS42XX8_DACINV, 4, 5, 1, 0),
++ SOC_DOUBLE("DAC4 Invert Switch", CS42XX8_DACINV, 6, 7, 1, 0),
++ SOC_DOUBLE("ADC1 Invert Switch", CS42XX8_ADCINV, 0, 1, 1, 0),
++ SOC_DOUBLE("ADC2 Invert Switch", CS42XX8_ADCINV, 2, 3, 1, 0),
++ SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1),
++ SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0),
++ SOC_ENUM("ADC1 Single Ended Mode Switch", adc1_single_enum),
++ SOC_ENUM("ADC2 Single Ended Mode Switch", adc2_single_enum),
++ SOC_SINGLE("DAC Single Volume Control Switch", CS42XX8_TXCTL, 7, 1, 0),
++ SOC_ENUM("DAC Soft Ramp & Zero Cross Control Switch", dac_szc_enum),
++ SOC_SINGLE("DAC Auto Mute Switch", CS42XX8_TXCTL, 4, 1, 0),
++ SOC_SINGLE("Mute ADC Serial Port Switch", CS42XX8_TXCTL, 3, 1, 0),
++ SOC_SINGLE("ADC Single Volume Control Switch", CS42XX8_TXCTL, 2, 1, 0),
++ SOC_ENUM("ADC Soft Ramp & Zero Cross Control Switch", adc_szc_enum),
++};
++
++static const struct snd_kcontrol_new cs42xx8_adc3_snd_controls[] = {
++ SOC_DOUBLE_R_S_TLV("ADC3 Capture Volume", CS42XX8_VOLAIN5,
++ CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv),
++ SOC_DOUBLE("ADC3 Invert Switch", CS42XX8_ADCINV, 4, 5, 1, 0),
++ SOC_ENUM("ADC3 Single Ended Mode Switch", adc3_single_enum),
++};
++
++static const struct snd_soc_dapm_widget cs42xx8_dapm_widgets[] = {
++ SND_SOC_DAPM_DAC("DAC1", "Playback", CS42XX8_PWRCTL, 1, 1),
++ SND_SOC_DAPM_DAC("DAC2", "Playback", CS42XX8_PWRCTL, 2, 1),
++ SND_SOC_DAPM_DAC("DAC3", "Playback", CS42XX8_PWRCTL, 3, 1),
++ SND_SOC_DAPM_DAC("DAC4", "Playback", CS42XX8_PWRCTL, 4, 1),
++
++ SND_SOC_DAPM_OUTPUT("AOUT1L"),
++ SND_SOC_DAPM_OUTPUT("AOUT1R"),
++ SND_SOC_DAPM_OUTPUT("AOUT2L"),
++ SND_SOC_DAPM_OUTPUT("AOUT2R"),
++ SND_SOC_DAPM_OUTPUT("AOUT3L"),
++ SND_SOC_DAPM_OUTPUT("AOUT3R"),
++ SND_SOC_DAPM_OUTPUT("AOUT4L"),
++ SND_SOC_DAPM_OUTPUT("AOUT4R"),
++
++ SND_SOC_DAPM_ADC("ADC1", "Capture", CS42XX8_PWRCTL, 5, 1),
++ SND_SOC_DAPM_ADC("ADC2", "Capture", CS42XX8_PWRCTL, 6, 1),
++
++ SND_SOC_DAPM_INPUT("AIN1L"),
++ SND_SOC_DAPM_INPUT("AIN1R"),
++ SND_SOC_DAPM_INPUT("AIN2L"),
++ SND_SOC_DAPM_INPUT("AIN2R"),
++
++ SND_SOC_DAPM_PGA_E("PWR", CS42XX8_PWRCTL, 0, 1, NULL, 0, NULL, 0),
++};
++
++static const struct snd_soc_dapm_widget cs42xx8_adc3_dapm_widgets[] = {
++ SND_SOC_DAPM_ADC("ADC3", "Capture", CS42XX8_PWRCTL, 7, 1),
++
++ SND_SOC_DAPM_INPUT("AIN3L"),
++ SND_SOC_DAPM_INPUT("AIN3R"),
++};
++
++static const struct snd_soc_dapm_route cs42xx8_dapm_routes[] = {
++ /* Playback */
++ { "PWR", NULL, "DAC1" },
++ { "PWR", NULL, "DAC1" },
++
++ { "PWR", NULL, "DAC2" },
++ { "PWR", NULL, "DAC2" },
++
++ { "PWR", NULL, "DAC3" },
++ { "PWR", NULL, "DAC3" },
++
++ { "PWR", NULL, "DAC4" },
++ { "PWR", NULL, "DAC4" },
++
++ { "AOUT1L", NULL, "PWR" },
++ { "AOUT1R", NULL, "PWR" },
++
++ { "AOUT2L", NULL, "PWR" },
++ { "AOUT2R", NULL, "PWR" },
++
++ { "AOUT3L", NULL, "PWR" },
++ { "AOUT3R", NULL, "PWR" },
++
++ { "AOUT4L", NULL, "PWR" },
++ { "AOUT4R", NULL, "PWR" },
++
++ /* Capture */
++ { "PWR", NULL, "AIN1L" },
++ { "PWR", NULL, "AIN1R" },
++
++ { "PWR", NULL, "AIN2L" },
++ { "PWR", NULL, "AIN2R" },
++
++ { "ADC1", NULL, "PWR" },
++ { "ADC1", NULL, "PWR" },
++
++ { "ADC2", NULL, "PWR" },
++ { "ADC2", NULL, "PWR" },
++};
++
++static const struct snd_soc_dapm_route cs42xx8_adc3_dapm_routes[] = {
++ /* Capture */
++ { "ADC3", NULL, "AIN3L" },
++ { "ADC3", NULL, "AIN3R" },
++ { "ADC3", NULL, "PWR" },
++};
++
++struct cs42xx8_ratios {
++ unsigned int mfreq;
++ unsigned int min_mclk;
++ unsigned int max_mclk;
++ unsigned int ratio[3];
++};
++
++static const struct cs42xx8_ratios cs42xx8_ratios[] = {
++ { 0, 1029000, 12800000, {256, 128, 64} },
++ { 2, 1536000, 19200000, {384, 192, 96} },
++ { 4, 2048000, 25600000, {512, 256, 128} },
++ { 6, 3072000, 38400000, {768, 384, 192} },
++ { 8, 4096000, 51200000, {1024, 512, 256} },
++};
++
++static int cs42xx8_set_dai_sysclk(struct snd_soc_dai *codec_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
++
++ cs42xx8->sysclk = freq;
++
++ return 0;
++}
++
++static int cs42xx8_set_dai_fmt(struct snd_soc_dai *codec_dai,
++ unsigned int format)
++{
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
++ u32 val;
++
++ /* Set DAI format */
++ switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_LEFT_J:
++ val = CS42XX8_INTF_DAC_DIF_LEFTJ | CS42XX8_INTF_ADC_DIF_LEFTJ;
++ break;
++ case SND_SOC_DAIFMT_I2S:
++ val = CS42XX8_INTF_DAC_DIF_I2S | CS42XX8_INTF_ADC_DIF_I2S;
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ val = CS42XX8_INTF_DAC_DIF_RIGHTJ | CS42XX8_INTF_ADC_DIF_RIGHTJ;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ val = CS42XX8_INTF_DAC_DIF_TDM | CS42XX8_INTF_ADC_DIF_TDM;
++ break;
++ default:
++ dev_err(codec->dev, "unsupported dai format\n");
++ return -EINVAL;
++ }
++
++ regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF,
++ CS42XX8_INTF_DAC_DIF_MASK |
++ CS42XX8_INTF_ADC_DIF_MASK, val);
++
++ /* Set master/slave audio interface */
++ switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ cs42xx8->slave_mode = true;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFM:
++ cs42xx8->slave_mode = false;
++ break;
++ default:
++ dev_err(codec->dev, "unsupported master/slave mode\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int cs42xx8_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++ u32 rate = params_rate(params);
++ u32 ratio_tx, ratio_rx;
++ u32 rate_tx, rate_rx;
++ u32 fm_tx, fm_rx;
++ u32 i, fm, val, mask;
++
++ rate_tx = tx ? rate : cs42xx8->rate[0];
++ rate_rx = tx ? cs42xx8->rate[1] : rate;
++
++ ratio_tx = rate_tx > 0 ? cs42xx8->sysclk / rate_tx : 0;
++ ratio_rx = rate_rx > 0 ? cs42xx8->sysclk / rate_rx : 0;
++
++ if (cs42xx8->slave_mode) {
++ fm_rx = CS42XX8_FM_AUTO;
++ fm_tx = CS42XX8_FM_AUTO;
++ } else {
++ if (rate_tx >= 0 && rate_tx < 50000)
++ fm_tx = CS42XX8_FM_SINGLE;
++ else if (rate_tx > 50000 && rate_tx < 100000)
++ fm_tx = CS42XX8_FM_DOUBLE;
++ else if (rate_tx > 100000 && rate_tx < 200000)
++ fm_tx = CS42XX8_FM_QUAD;
++ else {
++ dev_err(codec->dev, "unsupported sample rate or rate combine\n");
++ return -EINVAL;
++ }
++
++ if (rate_rx >= 0 && rate_rx < 50000)
++ fm_rx = CS42XX8_FM_SINGLE;
++ else if (rate_rx > 50000 && rate_rx < 100000)
++ fm_rx = CS42XX8_FM_DOUBLE;
++ else if (rate_rx > 100000 && rate_rx < 200000)
++ fm_rx = CS42XX8_FM_QUAD;
++ else {
++ dev_err(codec->dev, "unsupported sample rate or rate combine\n");
++ return -EINVAL;
++ }
++ }
++
++ fm = tx ? fm_tx : fm_rx;
++
++ if (fm == CS42XX8_FM_AUTO) {
++ for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) {
++ if ((ratio_tx > 0 ? (cs42xx8_ratios[i].ratio[0] == ratio_tx ||
++ cs42xx8_ratios[i].ratio[1] == ratio_tx ||
++ cs42xx8_ratios[i].ratio[2] == ratio_tx) : true) &&
++ (ratio_rx > 0 ? (cs42xx8_ratios[i].ratio[0] == ratio_rx ||
++ cs42xx8_ratios[i].ratio[1] == ratio_rx ||
++ cs42xx8_ratios[i].ratio[2] == ratio_rx) : true) &&
++ cs42xx8->sysclk >= cs42xx8_ratios[i].min_mclk &&
++ cs42xx8->sysclk <= cs42xx8_ratios[i].max_mclk)
++ break;
++ }
++ } else {
++ for (i = 0; i < ARRAY_SIZE(cs42xx8_ratios); i++) {
++ if ((ratio_tx > 0 ? (cs42xx8_ratios[i].ratio[fm_tx] == ratio_tx) : true) &&
++ (ratio_rx > 0 ? (cs42xx8_ratios[i].ratio[fm_rx] == ratio_rx) : true) &&
++ cs42xx8->sysclk >= cs42xx8_ratios[i].min_mclk &&
++ cs42xx8->sysclk <= cs42xx8_ratios[i].max_mclk)
++ break;
++ }
++ }
++
++ if (i == ARRAY_SIZE(cs42xx8_ratios)) {
++ dev_err(codec->dev, "unsupported sysclk ratio\n");
++ return -EINVAL;
++ }
++
++ cs42xx8->rate[substream->stream] = rate;
++
++ mask = CS42XX8_FUNCMOD_MFREQ_MASK;
++ val = cs42xx8_ratios[i].mfreq;
++
++ regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
++ CS42XX8_FUNCMOD_xC_FM_MASK(tx) | mask,
++ CS42XX8_FUNCMOD_xC_FM(tx, fm) | val);
++
++ return 0;
++}
++
++static int cs42xx8_hw_free(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_codec *codec = rtd->codec;
++ struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++
++ cs42xx8->rate[substream->stream] = 0;
++
++ regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
++ CS42XX8_FUNCMOD_xC_FM_MASK(tx),
++ CS42XX8_FUNCMOD_xC_FM(tx, CS42XX8_FM_AUTO));
++ return 0;
++}
++
++static int cs42xx8_digital_mute(struct snd_soc_dai *dai, int mute)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
++
++ regmap_update_bits(cs42xx8->regmap, CS42XX8_DACMUTE,
++ CS42XX8_DACMUTE_ALL, mute ? CS42XX8_DACMUTE_ALL : 0);
++
++ return 0;
++}
++
++static const struct snd_soc_dai_ops cs42xx8_dai_ops = {
++ .set_fmt = cs42xx8_set_dai_fmt,
++ .set_sysclk = cs42xx8_set_dai_sysclk,
++ .hw_params = cs42xx8_hw_params,
++ .hw_free = cs42xx8_hw_free,
++ .digital_mute = cs42xx8_digital_mute,
++};
++
++static struct snd_soc_dai_driver cs42xx8_dai = {
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 1,
++ .channels_max = 8,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = CS42XX8_FORMATS,
++ },
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 1,
++ .rates = SNDRV_PCM_RATE_8000_192000,
++ .formats = CS42XX8_FORMATS,
++ },
++ .ops = &cs42xx8_dai_ops,
++};
++
++static const struct reg_default cs42xx8_reg[] = {
++ { 0x01, 0x01 }, /* Chip I.D. and Revision Register */
++ { 0x02, 0x00 }, /* Power Control */
++ { 0x03, 0xF0 }, /* Functional Mode */
++ { 0x04, 0x46 }, /* Interface Formats */
++ { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */
++ { 0x06, 0x10 }, /* Transition Control */
++ { 0x07, 0x00 }, /* DAC Channel Mute */
++ { 0x08, 0x00 }, /* Volume Control AOUT1 */
++ { 0x09, 0x00 }, /* Volume Control AOUT2 */
++ { 0x0a, 0x00 }, /* Volume Control AOUT3 */
++ { 0x0b, 0x00 }, /* Volume Control AOUT4 */
++ { 0x0c, 0x00 }, /* Volume Control AOUT5 */
++ { 0x0d, 0x00 }, /* Volume Control AOUT6 */
++ { 0x0e, 0x00 }, /* Volume Control AOUT7 */
++ { 0x0f, 0x00 }, /* Volume Control AOUT8 */
++ { 0x10, 0x00 }, /* DAC Channel Invert */
++ { 0x11, 0x00 }, /* Volume Control AIN1 */
++ { 0x12, 0x00 }, /* Volume Control AIN2 */
++ { 0x13, 0x00 }, /* Volume Control AIN3 */
++ { 0x14, 0x00 }, /* Volume Control AIN4 */
++ { 0x15, 0x00 }, /* Volume Control AIN5 */
++ { 0x16, 0x00 }, /* Volume Control AIN6 */
++ { 0x17, 0x00 }, /* ADC Channel Invert */
++ { 0x18, 0x00 }, /* Status Control */
++ { 0x1a, 0x00 }, /* Status Mask */
++ { 0x1b, 0x00 }, /* MUTEC Pin Control */
++};
++
++static bool cs42xx8_volatile_register(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case CS42XX8_STATUS:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool cs42xx8_writeable_register(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case CS42XX8_CHIPID:
++ case CS42XX8_STATUS:
++ return false;
++ default:
++ return true;
++ }
++}
++
++const struct regmap_config cs42xx8_regmap_config = {
++ .reg_bits = 8,
++ .val_bits = 8,
++
++ .max_register = CS42XX8_LASTREG,
++ .reg_defaults = cs42xx8_reg,
++ .num_reg_defaults = ARRAY_SIZE(cs42xx8_reg),
++ .volatile_reg = cs42xx8_volatile_register,
++ .writeable_reg = cs42xx8_writeable_register,
++ .cache_type = REGCACHE_RBTREE,
++};
++EXPORT_SYMBOL_GPL(cs42xx8_regmap_config);
++
++static int cs42xx8_codec_probe(struct snd_soc_codec *codec)
++{
++ struct cs42xx8_priv *cs42xx8 = snd_soc_codec_get_drvdata(codec);
++ struct snd_soc_dapm_context *dapm = &codec->dapm;
++
++ switch (cs42xx8->drvdata->num_adcs) {
++ case 3:
++ snd_soc_add_codec_controls(codec, cs42xx8_adc3_snd_controls,
++ ARRAY_SIZE(cs42xx8_adc3_snd_controls));
++ snd_soc_dapm_new_controls(dapm, cs42xx8_adc3_dapm_widgets,
++ ARRAY_SIZE(cs42xx8_adc3_dapm_widgets));
++ snd_soc_dapm_add_routes(dapm, cs42xx8_adc3_dapm_routes,
++ ARRAY_SIZE(cs42xx8_adc3_dapm_routes));
++ break;
++ default:
++ break;
++ }
++
++ /* Mute all DAC channels */
++ regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL);
++
++ return 0;
++}
++
++static const struct snd_soc_codec_driver cs42xx8_driver = {
++ .probe = cs42xx8_codec_probe,
++ .idle_bias_off = true,
++
++ .controls = cs42xx8_snd_controls,
++ .num_controls = ARRAY_SIZE(cs42xx8_snd_controls),
++ .dapm_widgets = cs42xx8_dapm_widgets,
++ .num_dapm_widgets = ARRAY_SIZE(cs42xx8_dapm_widgets),
++ .dapm_routes = cs42xx8_dapm_routes,
++ .num_dapm_routes = ARRAY_SIZE(cs42xx8_dapm_routes),
++};
++
++const struct cs42xx8_driver_data cs42448_data = {
++ .name = "cs42448",
++ .num_adcs = 3,
++};
++EXPORT_SYMBOL_GPL(cs42448_data);
++
++const struct cs42xx8_driver_data cs42888_data = {
++ .name = "cs42888",
++ .num_adcs = 2,
++};
++EXPORT_SYMBOL_GPL(cs42888_data);
++
++static const struct of_device_id cs42xx8_of_match[] = {
++ { .compatible = "cirrus,cs42448", .data = &cs42448_data, },
++ { .compatible = "cirrus,cs42888", .data = &cs42888_data, },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, cs42xx8_of_match);
++EXPORT_SYMBOL_GPL(cs42xx8_of_match);
++
++int cs42xx8_probe(struct device *dev, struct regmap *regmap)
++{
++ const struct of_device_id *of_id = of_match_device(cs42xx8_of_match, dev);
++ struct cs42xx8_priv *cs42xx8;
++ int ret, val, i;
++
++ cs42xx8 = devm_kzalloc(dev, sizeof(*cs42xx8), GFP_KERNEL);
++ if (cs42xx8 == NULL)
++ return -ENOMEM;
++
++ dev_set_drvdata(dev, cs42xx8);
++
++ if (of_id)
++ cs42xx8->drvdata = of_id->data;
++
++ if (!cs42xx8->drvdata) {
++ dev_err(dev, "failed to find driver data\n");
++ return -EINVAL;
++ }
++
++ cs42xx8->clk = devm_clk_get(dev, "mclk");
++ if (IS_ERR(cs42xx8->clk)) {
++ dev_err(dev, "failed to get the clock: %ld\n",
++ PTR_ERR(cs42xx8->clk));
++ return -EINVAL;
++ }
++
++ cs42xx8->sysclk = clk_get_rate(cs42xx8->clk);
++
++ for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++)
++ cs42xx8->supplies[i].supply = cs42xx8_supply_names[i];
++
++ ret = devm_regulator_bulk_get(dev,
++ ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies);
++ if (ret) {
++ dev_err(dev, "failed to request supplies: %d\n", ret);
++ return ret;
++ }
++
++ ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
++ cs42xx8->supplies);
++ if (ret) {
++ dev_err(dev, "failed to enable supplies: %d\n", ret);
++ return ret;
++ }
++
++ /* Make sure hardware reset done */
++ msleep(5);
++
++ cs42xx8->regmap = regmap;
++ if (IS_ERR(cs42xx8->regmap)) {
++ ret = PTR_ERR(cs42xx8->regmap);
++ dev_err(dev, "failed to allocate regmap: %d\n", ret);
++ goto err_enable;
++ }
++
++ /*
++ * We haven't marked the chip revision as volatile due to
++ * sharing a register with the right input volume; explicitly
++ * bypass the cache to read it.
++ */
++ regcache_cache_bypass(cs42xx8->regmap, true);
++
++ /* Validate the chip ID */
++ ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val);
++ if (ret < 0) {
++ dev_err(dev, "failed to get device ID, ret = %d", ret);
++ goto err_enable;
++ }
++
++ /* The top four bits of the chip ID should be 0000 */
++ if (((val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4) != 0x00) {
++ dev_err(dev, "unmatched chip ID: %d\n",
++ (val & CS42XX8_CHIPID_CHIP_ID_MASK) >> 4);
++ ret = -EINVAL;
++ goto err_enable;
++ }
++
++ dev_info(dev, "found device, revision %X\n",
++ val & CS42XX8_CHIPID_REV_ID_MASK);
++
++ regcache_cache_bypass(cs42xx8->regmap, false);
++
++ cs42xx8_dai.name = cs42xx8->drvdata->name;
++
++ /* Each adc supports stereo input */
++ cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2;
++
++ ret = snd_soc_register_codec(dev, &cs42xx8_driver, &cs42xx8_dai, 1);
++ if (ret) {
++ dev_err(dev, "failed to register codec:%d\n", ret);
++ goto err_enable;
++ }
++
++ regcache_cache_only(cs42xx8->regmap, true);
++
++err_enable:
++ regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
++ cs42xx8->supplies);
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(cs42xx8_probe);
++
++#ifdef CONFIG_PM_RUNTIME
++static int cs42xx8_runtime_resume(struct device *dev)
++{
++ struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
++ int ret;
++
++ ret = clk_prepare_enable(cs42xx8->clk);
++ if (ret) {
++ dev_err(dev, "failed to enable mclk: %d\n", ret);
++ return ret;
++ }
++
++ ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
++ cs42xx8->supplies);
++ if (ret) {
++ dev_err(dev, "failed to enable supplies: %d\n", ret);
++ goto err_clk;
++ }
++
++ /* Make sure hardware reset done */
++ msleep(5);
++
++ regcache_cache_only(cs42xx8->regmap, false);
++
++ ret = regcache_sync(cs42xx8->regmap);
++ if (ret) {
++ dev_err(dev, "failed to sync regmap: %d\n", ret);
++ goto err_bulk;
++ }
++
++ return 0;
++
++err_bulk:
++ regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
++ cs42xx8->supplies);
++err_clk:
++ clk_disable_unprepare(cs42xx8->clk);
++
++ return ret;
++}
++
++static int cs42xx8_runtime_suspend(struct device *dev)
++{
++ struct cs42xx8_priv *cs42xx8 = dev_get_drvdata(dev);
++
++ regcache_cache_only(cs42xx8->regmap, true);
++
++ regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
++ cs42xx8->supplies);
++
++ clk_disable_unprepare(cs42xx8->clk);
++
++ return 0;
++}
++#endif
++
++const struct dev_pm_ops cs42xx8_pm = {
++ SET_RUNTIME_PM_OPS(cs42xx8_runtime_suspend, cs42xx8_runtime_resume, NULL)
++};
++EXPORT_SYMBOL_GPL(cs42xx8_pm);
++
++MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec Driver");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/cs42xx8.h linux-3.14.72/sound/soc/codecs/cs42xx8.h
+--- linux-3.14.72.orig/sound/soc/codecs/cs42xx8.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/codecs/cs42xx8.h 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,238 @@
++/*
++ * cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#ifndef _CS42XX8_H
++#define _CS42XX8_H
++
++struct cs42xx8_driver_data {
++ char name[32];
++ int num_adcs;
++};
++
++extern const struct dev_pm_ops cs42xx8_pm;
++extern const struct cs42xx8_driver_data cs42448_data;
++extern const struct cs42xx8_driver_data cs42888_data;
++extern const struct regmap_config cs42xx8_regmap_config;
++int cs42xx8_probe(struct device *dev, struct regmap *regmap);
++
++/* CS42888 register map */
++#define CS42XX8_CHIPID 0x01 /* Chip ID */
++#define CS42XX8_PWRCTL 0x02 /* Power Control */
++#define CS42XX8_FUNCMOD 0x03 /* Functional Mode */
++#define CS42XX8_INTF 0x04 /* Interface Formats */
++#define CS42XX8_ADCCTL 0x05 /* ADC Control */
++#define CS42XX8_TXCTL 0x06 /* Transition Control */
++#define CS42XX8_DACMUTE 0x07 /* DAC Mute Control */
++#define CS42XX8_VOLAOUT1 0x08 /* Volume Control AOUT1 */
++#define CS42XX8_VOLAOUT2 0x09 /* Volume Control AOUT2 */
++#define CS42XX8_VOLAOUT3 0x0A /* Volume Control AOUT3 */
++#define CS42XX8_VOLAOUT4 0x0B /* Volume Control AOUT4 */
++#define CS42XX8_VOLAOUT5 0x0C /* Volume Control AOUT5 */
++#define CS42XX8_VOLAOUT6 0x0D /* Volume Control AOUT6 */
++#define CS42XX8_VOLAOUT7 0x0E /* Volume Control AOUT7 */
++#define CS42XX8_VOLAOUT8 0x0F /* Volume Control AOUT8 */
++#define CS42XX8_DACINV 0x10 /* DAC Channel Invert */
++#define CS42XX8_VOLAIN1 0x11 /* Volume Control AIN1 */
++#define CS42XX8_VOLAIN2 0x12 /* Volume Control AIN2 */
++#define CS42XX8_VOLAIN3 0x13 /* Volume Control AIN3 */
++#define CS42XX8_VOLAIN4 0x14 /* Volume Control AIN4 */
++#define CS42XX8_VOLAIN5 0x15 /* Volume Control AIN5 */
++#define CS42XX8_VOLAIN6 0x16 /* Volume Control AIN6 */
++#define CS42XX8_ADCINV 0x17 /* ADC Channel Invert */
++#define CS42XX8_STATUSCTL 0x18 /* Status Control */
++#define CS42XX8_STATUS 0x19 /* Status */
++#define CS42XX8_STATUSM 0x1A /* Status Mask */
++#define CS42XX8_MUTEC 0x1B /* MUTEC Pin Control */
++
++#define CS42XX8_FIRSTREG CS42XX8_CHIPID
++#define CS42XX8_LASTREG CS42XX8_MUTEC
++#define CS42XX8_NUMREGS (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1)
++#define CS42XX8_I2C_INCR 0x80
++
++/* Chip I.D. and Revision Register (Address 01h) */
++#define CS42XX8_CHIPID_CHIP_ID_MASK 0xF0
++#define CS42XX8_CHIPID_REV_ID_MASK 0x0F
++
++/* Power Control (Address 02h) */
++#define CS42XX8_PWRCTL_PDN_ADC3_SHIFT 7
++#define CS42XX8_PWRCTL_PDN_ADC3_MASK (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
++#define CS42XX8_PWRCTL_PDN_ADC3 (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
++#define CS42XX8_PWRCTL_PDN_ADC2_SHIFT 6
++#define CS42XX8_PWRCTL_PDN_ADC2_MASK (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
++#define CS42XX8_PWRCTL_PDN_ADC2 (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
++#define CS42XX8_PWRCTL_PDN_ADC1_SHIFT 5
++#define CS42XX8_PWRCTL_PDN_ADC1_MASK (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
++#define CS42XX8_PWRCTL_PDN_ADC1 (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC4_SHIFT 4
++#define CS42XX8_PWRCTL_PDN_DAC4_MASK (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC4 (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC3_SHIFT 3
++#define CS42XX8_PWRCTL_PDN_DAC3_MASK (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC3 (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC2_SHIFT 2
++#define CS42XX8_PWRCTL_PDN_DAC2_MASK (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC2 (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC1_SHIFT 1
++#define CS42XX8_PWRCTL_PDN_DAC1_MASK (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
++#define CS42XX8_PWRCTL_PDN_DAC1 (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
++#define CS42XX8_PWRCTL_PDN_SHIFT 0
++#define CS42XX8_PWRCTL_PDN_MASK (1 << CS42XX8_PWRCTL_PDN_SHIFT)
++#define CS42XX8_PWRCTL_PDN (1 << CS42XX8_PWRCTL_PDN_SHIFT)
++
++/* Functional Mode (Address 03h) */
++#define CS42XX8_FUNCMOD_DAC_FM_SHIFT 6
++#define CS42XX8_FUNCMOD_DAC_FM_WIDTH 2
++#define CS42XX8_FUNCMOD_DAC_FM_MASK (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
++#define CS42XX8_FUNCMOD_DAC_FM(v) ((v) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
++#define CS42XX8_FUNCMOD_ADC_FM_SHIFT 4
++#define CS42XX8_FUNCMOD_ADC_FM_WIDTH 2
++#define CS42XX8_FUNCMOD_ADC_FM_MASK (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
++#define CS42XX8_FUNCMOD_ADC_FM(v) ((v) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
++#define CS42XX8_FUNCMOD_xC_FM_MASK(x) ((x) ? CS42XX8_FUNCMOD_DAC_FM_MASK : CS42XX8_FUNCMOD_ADC_FM_MASK)
++#define CS42XX8_FUNCMOD_xC_FM(x, v) ((x) ? CS42XX8_FUNCMOD_DAC_FM(v) : CS42XX8_FUNCMOD_ADC_FM(v))
++#define CS42XX8_FUNCMOD_MFREQ_SHIFT 1
++#define CS42XX8_FUNCMOD_MFREQ_WIDTH 3
++#define CS42XX8_FUNCMOD_MFREQ_MASK (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MFREQ_SHIFT)
++#define CS42XX8_FUNCMOD_MFREQ_256(s) ((0 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
++#define CS42XX8_FUNCMOD_MFREQ_384(s) ((1 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
++#define CS42XX8_FUNCMOD_MFREQ_512(s) ((2 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
++#define CS42XX8_FUNCMOD_MFREQ_768(s) ((3 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
++#define CS42XX8_FUNCMOD_MFREQ_1024(s) ((4 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
++
++#define CS42XX8_FM_SINGLE 0
++#define CS42XX8_FM_DOUBLE 1
++#define CS42XX8_FM_QUAD 2
++#define CS42XX8_FM_AUTO 3
++
++/* Interface Formats (Address 04h) */
++#define CS42XX8_INTF_FREEZE_SHIFT 7
++#define CS42XX8_INTF_FREEZE_MASK (1 << CS42XX8_INTF_FREEZE_SHIFT)
++#define CS42XX8_INTF_FREEZE (1 << CS42XX8_INTF_FREEZE_SHIFT)
++#define CS42XX8_INTF_AUX_DIF_SHIFT 6
++#define CS42XX8_INTF_AUX_DIF_MASK (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
++#define CS42XX8_INTF_AUX_DIF (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_SHIFT 3
++#define CS42XX8_INTF_DAC_DIF_WIDTH 3
++#define CS42XX8_INTF_DAC_DIF_MASK (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_LEFTJ (0 << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_I2S (1 << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_RIGHTJ (2 << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_ONELINE_20 (4 << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_ONELINE_24 (5 << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_DAC_DIF_TDM (6 << CS42XX8_INTF_DAC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_SHIFT 0
++#define CS42XX8_INTF_ADC_DIF_WIDTH 3
++#define CS42XX8_INTF_ADC_DIF_MASK (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_LEFTJ (0 << CS42XX8_INTF_ADC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_I2S (1 << CS42XX8_INTF_ADC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_RIGHTJ (2 << CS42XX8_INTF_ADC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_ADC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_ONELINE_20 (4 << CS42XX8_INTF_ADC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_ONELINE_24 (5 << CS42XX8_INTF_ADC_DIF_SHIFT)
++#define CS42XX8_INTF_ADC_DIF_TDM (6 << CS42XX8_INTF_ADC_DIF_SHIFT)
++
++/* ADC Control & DAC De-Emphasis (Address 05h) */
++#define CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT 7
++#define CS42XX8_ADCCTL_ADC_HPF_FREEZE_MASK (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
++#define CS42XX8_ADCCTL_ADC_HPF_FREEZE (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
++#define CS42XX8_ADCCTL_DAC_DEM_SHIFT 5
++#define CS42XX8_ADCCTL_DAC_DEM_MASK (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
++#define CS42XX8_ADCCTL_DAC_DEM (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
++#define CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT 4
++#define CS42XX8_ADCCTL_ADC1_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
++#define CS42XX8_ADCCTL_ADC1_SINGLE (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
++#define CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT 3
++#define CS42XX8_ADCCTL_ADC2_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
++#define CS42XX8_ADCCTL_ADC2_SINGLE (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
++#define CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT 2
++#define CS42XX8_ADCCTL_ADC3_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
++#define CS42XX8_ADCCTL_ADC3_SINGLE (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
++#define CS42XX8_ADCCTL_AIN5_MUX_SHIFT 1
++#define CS42XX8_ADCCTL_AIN5_MUX_MASK (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
++#define CS42XX8_ADCCTL_AIN5_MUX (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
++#define CS42XX8_ADCCTL_AIN6_MUX_SHIFT 0
++#define CS42XX8_ADCCTL_AIN6_MUX_MASK (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
++#define CS42XX8_ADCCTL_AIN6_MUX (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
++
++/* Transition Control (Address 06h) */
++#define CS42XX8_TXCTL_DAC_SNGVOL_SHIFT 7
++#define CS42XX8_TXCTL_DAC_SNGVOL_MASK (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
++#define CS42XX8_TXCTL_DAC_SNGVOL (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
++#define CS42XX8_TXCTL_DAC_SZC_SHIFT 5
++#define CS42XX8_TXCTL_DAC_SZC_WIDTH 2
++#define CS42XX8_TXCTL_DAC_SZC_MASK (((1 << CS42XX8_TXCTL_DAC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_DAC_SZC_SHIFT)
++#define CS42XX8_TXCTL_DAC_SZC_IC (0 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
++#define CS42XX8_TXCTL_DAC_SZC_ZC (1 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
++#define CS42XX8_TXCTL_DAC_SZC_SR (2 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
++#define CS42XX8_TXCTL_DAC_SZC_SRZC (3 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
++#define CS42XX8_TXCTL_AMUTE_SHIFT 4
++#define CS42XX8_TXCTL_AMUTE_MASK (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
++#define CS42XX8_TXCTL_AMUTE (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
++#define CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT 3
++#define CS42XX8_TXCTL_MUTE_ADC_SP_MASK (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
++#define CS42XX8_TXCTL_MUTE_ADC_SP (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
++#define CS42XX8_TXCTL_ADC_SNGVOL_SHIFT 2
++#define CS42XX8_TXCTL_ADC_SNGVOL_MASK (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
++#define CS42XX8_TXCTL_ADC_SNGVOL (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
++#define CS42XX8_TXCTL_ADC_SZC_SHIFT 0
++#define CS42XX8_TXCTL_ADC_SZC_MASK (((1 << CS42XX8_TXCTL_ADC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_ADC_SZC_SHIFT)
++#define CS42XX8_TXCTL_ADC_SZC_IC (0 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
++#define CS42XX8_TXCTL_ADC_SZC_ZC (1 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
++#define CS42XX8_TXCTL_ADC_SZC_SR (2 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
++#define CS42XX8_TXCTL_ADC_SZC_SRZC (3 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
++
++/* DAC Channel Mute (Address 07h) */
++#define CS42XX8_DACMUTE_AOUT(n) (0x1 << n)
++#define CS42XX8_DACMUTE_ALL 0xff
++
++/* Status Control (Address 18h)*/
++#define CS42XX8_STATUSCTL_INI_SHIFT 2
++#define CS42XX8_STATUSCTL_INI_WIDTH 2
++#define CS42XX8_STATUSCTL_INI_MASK (((1 << CS42XX8_STATUSCTL_INI_WIDTH) - 1) << CS42XX8_STATUSCTL_INI_SHIFT)
++#define CS42XX8_STATUSCTL_INT_ACTIVE_HIGH (0 << CS42XX8_STATUSCTL_INI_SHIFT)
++#define CS42XX8_STATUSCTL_INT_ACTIVE_LOW (1 << CS42XX8_STATUSCTL_INI_SHIFT)
++#define CS42XX8_STATUSCTL_INT_OPEN_DRAIN (2 << CS42XX8_STATUSCTL_INI_SHIFT)
++
++/* Status (Address 19h)*/
++#define CS42XX8_STATUS_DAC_CLK_ERR_SHIFT 4
++#define CS42XX8_STATUS_DAC_CLK_ERR_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_SHIFT)
++#define CS42XX8_STATUS_ADC_CLK_ERR_SHIFT 3
++#define CS42XX8_STATUS_ADC_CLK_ERR_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_SHIFT)
++#define CS42XX8_STATUS_ADC3_OVFL_SHIFT 2
++#define CS42XX8_STATUS_ADC3_OVFL_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_SHIFT)
++#define CS42XX8_STATUS_ADC2_OVFL_SHIFT 1
++#define CS42XX8_STATUS_ADC2_OVFL_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_SHIFT)
++#define CS42XX8_STATUS_ADC1_OVFL_SHIFT 0
++#define CS42XX8_STATUS_ADC1_OVFL_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_SHIFT)
++
++/* Status Mask (Address 1Ah) */
++#define CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT 4
++#define CS42XX8_STATUS_DAC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT)
++#define CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT 3
++#define CS42XX8_STATUS_ADC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT)
++#define CS42XX8_STATUS_ADC3_OVFL_M_SHIFT 2
++#define CS42XX8_STATUS_ADC3_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_M_SHIFT)
++#define CS42XX8_STATUS_ADC2_OVFL_M_SHIFT 1
++#define CS42XX8_STATUS_ADC2_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_M_SHIFT)
++#define CS42XX8_STATUS_ADC1_OVFL_M_SHIFT 0
++#define CS42XX8_STATUS_ADC1_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_M_SHIFT)
++
++/* MUTEC Pin Control (Address 1Bh) */
++#define CS42XX8_MUTEC_MCPOLARITY_SHIFT 1
++#define CS42XX8_MUTEC_MCPOLARITY_MASK (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
++#define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_LOW (0 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
++#define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_HIGH (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
++#define CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT 0
++#define CS42XX8_MUTEC_MUTEC_ACTIVE_MASK (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
++#define CS42XX8_MUTEC_MUTEC_ACTIVE (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
++#endif /* _CS42XX8_H */
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/cs42xx8-i2c.c linux-3.14.72/sound/soc/codecs/cs42xx8-i2c.c
+--- linux-3.14.72.orig/sound/soc/codecs/cs42xx8-i2c.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/codecs/cs42xx8-i2c.c 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,64 @@
++/*
++ * Cirrus Logic CS42448/CS42888 Audio CODEC DAI I2C driver
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * Author: Nicolin Chen <Guangyu.Chen@freescale.com>
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/pm_runtime.h>
++#include <sound/soc.h>
++
++#include "cs42xx8.h"
++
++static int cs42xx8_i2c_probe(struct i2c_client *i2c,
++ const struct i2c_device_id *id)
++{
++ u32 ret = cs42xx8_probe(&i2c->dev,
++ devm_regmap_init_i2c(i2c, &cs42xx8_regmap_config));
++ if (ret)
++ return ret;
++
++ pm_runtime_enable(&i2c->dev);
++ pm_request_idle(&i2c->dev);
++
++ return 0;
++}
++
++static int cs42xx8_i2c_remove(struct i2c_client *i2c)
++{
++ snd_soc_unregister_codec(&i2c->dev);
++ pm_runtime_disable(&i2c->dev);
++
++ return 0;
++}
++
++static struct i2c_device_id cs42xx8_i2c_id[] = {
++ {"cs42448", (kernel_ulong_t)&cs42448_data},
++ {"cs42888", (kernel_ulong_t)&cs42888_data},
++ {}
++};
++MODULE_DEVICE_TABLE(i2c, cs42xx8_i2c_id);
++
++static struct i2c_driver cs42xx8_i2c_driver = {
++ .driver = {
++ .name = "cs42xx8",
++ .owner = THIS_MODULE,
++ .pm = &cs42xx8_pm,
++ },
++ .probe = cs42xx8_i2c_probe,
++ .remove = cs42xx8_i2c_remove,
++ .id_table = cs42xx8_i2c_id,
++};
++
++module_i2c_driver(cs42xx8_i2c_driver);
++
++MODULE_DESCRIPTION("Cirrus Logic CS42448/CS42888 ALSA SoC Codec I2C Driver");
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/fsl_mqs.c linux-3.14.72/sound/soc/codecs/fsl_mqs.c
+--- linux-3.14.72.orig/sound/soc/codecs/fsl_mqs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/codecs/fsl_mqs.c 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,229 @@
++/*
++ * ALSA SoC IMX MQS driver
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
++#include <linux/of.h>
++#include <linux/slab.h>
++#include <sound/soc.h>
++#include <sound/pcm.h>
++#include <sound/initval.h>
++
++
++/* codec private data */
++struct fsl_mqs {
++ struct platform_device *pdev;
++ struct regmap *gpr;
++ struct clk *mclk;
++
++ unsigned long mclk_rate;
++
++ int sysclk_rate;
++ int bclk;
++ int lrclk;
++ char name[32];
++};
++
++#define FSL_MQS_RATES SNDRV_PCM_RATE_8000_192000
++#define FSL_MQS_FORMATS SNDRV_PCM_FMTBIT_S16_LE
++
++static int fsl_mqs_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct fsl_mqs *mqs_priv = snd_soc_codec_get_drvdata(codec);
++ int div, res;
++
++ mqs_priv->bclk = snd_soc_params_to_bclk(params);
++ mqs_priv->lrclk = params_rate(params);
++
++ /*
++ * mclk_rate / (oversample(32,64) * FS * 2 * divider ) = repeat_rate;
++ * if repeat_rate is 8, mqs can achieve better quality.
++ * oversample rate is fix to 32 currently.
++ */
++ div = mqs_priv->mclk_rate / (32 * 2 * mqs_priv->lrclk * 8);
++ res = mqs_priv->mclk_rate % (32 * 2 * mqs_priv->lrclk * 8);
++
++ if (res == 0 && div > 0 && div <= 256) {
++ regmap_update_bits(mqs_priv->gpr, IOMUXC_GPR2,
++ IMX6SX_GPR2_MQS_CLK_DIV_MASK, (div-1) << IMX6SX_GPR2_MQS_CLK_DIV_SHIFT);
++ regmap_update_bits(mqs_priv->gpr, IOMUXC_GPR2,
++ IMX6SX_GPR2_MQS_OVERSAMPLE_MASK, 0 << IMX6SX_GPR2_MQS_OVERSAMPLE_SHIFT);
++ } else
++ dev_err(&mqs_priv->pdev->dev, "can't get proper divider\n");
++
++ return 0;
++}
++
++static int fsl_mqs_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_LEFT_J:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_NB_NF:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBS_CFS:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int fsl_mqs_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
++ unsigned int freq, int dir)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct fsl_mqs *mqs_priv = snd_soc_codec_get_drvdata(codec);
++
++ mqs_priv->sysclk_rate = freq;
++
++ return 0;
++}
++
++static int fsl_mqs_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct fsl_mqs *mqs_priv = snd_soc_codec_get_drvdata(codec);
++
++ regmap_update_bits(mqs_priv->gpr, IOMUXC_GPR2, IMX6SX_GPR2_MQS_EN_MASK,
++ 1 << IMX6SX_GPR2_MQS_EN_SHIFT);
++ return 0;
++}
++
++static void fsl_mqs_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct fsl_mqs *mqs_priv = snd_soc_codec_get_drvdata(codec);
++
++ regmap_update_bits(mqs_priv->gpr, IOMUXC_GPR2,
++ IMX6SX_GPR2_MQS_EN_MASK, 0);
++
++}
++
++
++static struct snd_soc_codec_driver soc_codec_fsl_mqs;
++
++static const struct snd_soc_dai_ops fsl_mqs_dai_ops = {
++ .startup = fsl_mqs_startup,
++ .shutdown = fsl_mqs_shutdown,
++ .hw_params = fsl_mqs_hw_params,
++ .set_fmt = fsl_mqs_set_dai_fmt,
++ .set_sysclk = fsl_mqs_set_dai_sysclk,
++};
++
++static struct snd_soc_dai_driver fsl_mqs_dai = {
++ .name = "fsl-mqs-dai",
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rates = FSL_MQS_RATES,
++ .formats = FSL_MQS_FORMATS,
++ },
++ .ops = &fsl_mqs_dai_ops,
++};
++
++static int fsl_mqs_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct device_node *gpr_np;
++ struct fsl_mqs *mqs_priv;
++ int ret = 0;
++
++ mqs_priv = devm_kzalloc(&pdev->dev, sizeof(*mqs_priv), GFP_KERNEL);
++ if (!mqs_priv)
++ return -ENOMEM;
++
++ mqs_priv->pdev = pdev;
++ strcpy(mqs_priv->name, np->name);
++
++ gpr_np = of_parse_phandle(np, "gpr", 0);
++ if (IS_ERR(gpr_np)) {
++ dev_err(&pdev->dev, "failed to get gpr node by phandle\n");
++ ret = PTR_ERR(gpr_np);
++ goto out;
++ }
++
++ mqs_priv->gpr = syscon_node_to_regmap(gpr_np);
++ if (IS_ERR(mqs_priv->gpr)) {
++ dev_err(&pdev->dev, "failed to get gpr regmap\n");
++ ret = PTR_ERR(mqs_priv->gpr);
++ goto out;
++ }
++
++ mqs_priv->mclk = devm_clk_get(&pdev->dev, "mclk");
++ if (IS_ERR(mqs_priv->mclk)) {
++ dev_err(&pdev->dev, "failed to get the clock: %ld\n",
++ PTR_ERR(mqs_priv->mclk));
++ goto out;
++ }
++
++ mqs_priv->mclk_rate = clk_get_rate(mqs_priv->mclk);
++
++ dev_set_drvdata(&pdev->dev, mqs_priv);
++
++ return snd_soc_register_codec(&pdev->dev, &soc_codec_fsl_mqs,
++ &fsl_mqs_dai, 1);
++
++out:
++ if (!IS_ERR(gpr_np))
++ of_node_put(gpr_np);
++
++ return ret;
++}
++
++static int fsl_mqs_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_codec(&pdev->dev);
++ return 0;
++}
++
++static const struct of_device_id fsl_mqs_dt_ids[] = {
++ { .compatible = "fsl,imx6sx-mqs", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, fsl_mqs_dt_ids);
++
++
++static struct platform_driver fsl_mqs_driver = {
++ .probe = fsl_mqs_probe,
++ .remove = fsl_mqs_remove,
++ .driver = {
++ .name = "fsl-mqs",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_mqs_dt_ids,
++ },
++};
++
++module_platform_driver(fsl_mqs_driver);
++
++MODULE_AUTHOR("shengjiu wang <shengjiu.wang@freescale.com>");
++MODULE_DESCRIPTION("MQS dummy codec driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform: fsl-mqs");
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/hdmi.c linux-3.14.72/sound/soc/codecs/hdmi.c
+--- linux-3.14.72.orig/sound/soc/codecs/hdmi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/codecs/hdmi.c 2016-06-19 22:11:55.521125834 +0200
+@@ -74,6 +74,7 @@
+ .num_dapm_widgets = ARRAY_SIZE(hdmi_widgets),
+ .dapm_routes = hdmi_routes,
+ .num_dapm_routes = ARRAY_SIZE(hdmi_routes),
++ .ignore_pmdown_time = true,
+ };
+
+ static int hdmi_codec_probe(struct platform_device *pdev)
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/Kconfig linux-3.14.72/sound/soc/codecs/Kconfig
+--- linux-3.14.72.orig/sound/soc/codecs/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/codecs/Kconfig 2016-06-19 22:11:55.521125834 +0200
+@@ -37,6 +37,7 @@
+ select SND_SOC_CS42L73 if I2C
+ select SND_SOC_CS4270 if I2C
+ select SND_SOC_CS4271 if SND_SOC_I2C_AND_SPI
++ select SND_SOC_CS42XX8_I2C if I2C
+ select SND_SOC_CX20442 if TTY
+ select SND_SOC_DA7210 if I2C
+ select SND_SOC_DA7213 if I2C
+@@ -62,6 +63,7 @@
+ select SND_SOC_RT5631 if I2C
+ select SND_SOC_RT5640 if I2C
+ select SND_SOC_SGTL5000 if I2C
++ select SND_SOC_VT1613 if SND_SOC_AC97_BUS
+ select SND_SOC_SI476X if MFD_SI476X_CORE
+ select SND_SOC_SN95031 if INTEL_SCU_IPC
+ select SND_SOC_SPDIF
+@@ -254,6 +256,15 @@
+ config SND_SOC_CS4271
+ tristate
+
++config SND_SOC_CS42XX8
++ tristate
++
++config SND_SOC_CS42XX8_I2C
++ tristate "Cirrus Logic CS42448/CS42888 CODEC (I2C)"
++ depends on I2C
++ select SND_SOC_CS42XX8
++ select REGMAP_I2C
++
+ config SND_SOC_CX20442
+ tristate
+ depends on TTY
+@@ -283,6 +294,9 @@
+ config SND_SOC_DMIC
+ tristate
+
++config SND_SOC_FSL_MQS
++ tristate
++
+ config SND_SOC_ISABELLE
+ tristate
+
+@@ -323,6 +337,14 @@
+ config SND_SOC_SGTL5000
+ tristate
+
++config SND_SOC_VT1613
++ select REGMAP_AC97
++ tristate
++
++# NXP TDA1997X HDMI audio codec
++config SND_SOC_TDA1997X
++ tristate
++
+ config SND_SOC_SI476X
+ tristate
+
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/Makefile linux-3.14.72/sound/soc/codecs/Makefile
+--- linux-3.14.72.orig/sound/soc/codecs/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/codecs/Makefile 2016-06-19 22:11:55.521125834 +0200
+@@ -23,6 +23,8 @@
+ snd-soc-cs42l73-objs := cs42l73.o
+ snd-soc-cs4270-objs := cs4270.o
+ snd-soc-cs4271-objs := cs4271.o
++snd-soc-cs42xx8-objs := cs42xx8.o
++snd-soc-cs42xx8-i2c-objs := cs42xx8-i2c.o
+ snd-soc-cx20442-objs := cx20442.o
+ snd-soc-da7210-objs := da7210.o
+ snd-soc-da7213-objs := da7213.o
+@@ -30,6 +32,7 @@
+ snd-soc-da9055-objs := da9055.o
+ snd-soc-bt-sco-objs := bt-sco.o
+ snd-soc-dmic-objs := dmic.o
++snd-soc-fsl-mqs-objs := fsl_mqs.o
+ snd-soc-isabelle-objs := isabelle.o
+ snd-soc-jz4740-codec-objs := jz4740.o
+ snd-soc-l3-objs := l3.o
+@@ -49,6 +52,8 @@
+ snd-soc-rt5631-objs := rt5631.o
+ snd-soc-rt5640-objs := rt5640.o
+ snd-soc-sgtl5000-objs := sgtl5000.o
++snd-soc-vt1613-objs := vt1613.o
++snd-soc-tda1997x-objs := tda1997x.o
+ snd-soc-alc5623-objs := alc5623.o
+ snd-soc-alc5632-objs := alc5632.o
+ snd-soc-sigmadsp-objs := sigmadsp.o
+@@ -156,6 +161,8 @@
+ obj-$(CONFIG_SND_SOC_CS42L73) += snd-soc-cs42l73.o
+ obj-$(CONFIG_SND_SOC_CS4270) += snd-soc-cs4270.o
+ obj-$(CONFIG_SND_SOC_CS4271) += snd-soc-cs4271.o
++obj-$(CONFIG_SND_SOC_CS42XX8) += snd-soc-cs42xx8.o
++obj-$(CONFIG_SND_SOC_CS42XX8_I2C) += snd-soc-cs42xx8-i2c.o
+ obj-$(CONFIG_SND_SOC_CX20442) += snd-soc-cx20442.o
+ obj-$(CONFIG_SND_SOC_DA7210) += snd-soc-da7210.o
+ obj-$(CONFIG_SND_SOC_DA7213) += snd-soc-da7213.o
+@@ -163,6 +170,7 @@
+ obj-$(CONFIG_SND_SOC_DA9055) += snd-soc-da9055.o
+ obj-$(CONFIG_SND_SOC_BT_SCO) += snd-soc-bt-sco.o
+ obj-$(CONFIG_SND_SOC_DMIC) += snd-soc-dmic.o
++obj-$(CONFIG_SND_SOC_FSL_MQS) += snd-soc-fsl-mqs.o
+ obj-$(CONFIG_SND_SOC_ISABELLE) += snd-soc-isabelle.o
+ obj-$(CONFIG_SND_SOC_JZ4740_CODEC) += snd-soc-jz4740-codec.o
+ obj-$(CONFIG_SND_SOC_L3) += snd-soc-l3.o
+@@ -182,6 +190,8 @@
+ obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
+ obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
+ obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
++obj-$(CONFIG_SND_SOC_VT1613) += snd-soc-vt1613.o
++obj-$(CONFIG_SND_SOC_TDA1997X) += snd-soc-tda1997x.o
+ obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
+ obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
+ obj-$(CONFIG_SND_SOC_SN95031) +=snd-soc-sn95031.o
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/sgtl5000.c linux-3.14.72/sound/soc/codecs/sgtl5000.c
+--- linux-3.14.72.orig/sound/soc/codecs/sgtl5000.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/codecs/sgtl5000.c 2016-06-19 22:11:55.521125834 +0200
+@@ -36,18 +36,32 @@
+
+ /* default value of sgtl5000 registers */
+ static const struct reg_default sgtl5000_reg_defaults[] = {
++ { SGTL5000_CHIP_DIG_POWER, 0x0000 },
+ { SGTL5000_CHIP_CLK_CTRL, 0x0008 },
+ { SGTL5000_CHIP_I2S_CTRL, 0x0010 },
+ { SGTL5000_CHIP_SSS_CTRL, 0x0010 },
++ { SGTL5000_CHIP_ADCDAC_CTRL, 0x020c },
+ { SGTL5000_CHIP_DAC_VOL, 0x3c3c },
+ { SGTL5000_CHIP_PAD_STRENGTH, 0x015f },
++ { SGTL5000_CHIP_ANA_ADC_CTRL, 0x0000 },
+ { SGTL5000_CHIP_ANA_HP_CTRL, 0x1818 },
+ { SGTL5000_CHIP_ANA_CTRL, 0x0111 },
++ { SGTL5000_CHIP_LINREG_CTRL, 0x0000 },
++ { SGTL5000_CHIP_REF_CTRL, 0x0000 },
++ { SGTL5000_CHIP_MIC_CTRL, 0x0000 },
++ { SGTL5000_CHIP_LINE_OUT_CTRL, 0x0000 },
+ { SGTL5000_CHIP_LINE_OUT_VOL, 0x0404 },
+ { SGTL5000_CHIP_ANA_POWER, 0x7060 },
+ { SGTL5000_CHIP_PLL_CTRL, 0x5000 },
++ { SGTL5000_CHIP_CLK_TOP_CTRL, 0x0000 },
++ { SGTL5000_CHIP_ANA_STATUS, 0x0000 },
++ { SGTL5000_CHIP_SHORT_CTRL, 0x0000 },
++ { SGTL5000_CHIP_ANA_TEST2, 0x0000 },
++ { SGTL5000_DAP_CTRL, 0x0000 },
++ { SGTL5000_DAP_PEQ, 0x0000 },
+ { SGTL5000_DAP_BASS_ENHANCE, 0x0040 },
+ { SGTL5000_DAP_BASS_ENHANCE_CTRL, 0x051f },
++ { SGTL5000_DAP_AUDIO_EQ, 0x0000 },
+ { SGTL5000_DAP_SURROUND, 0x0040 },
+ { SGTL5000_DAP_EQ_BASS_BAND0, 0x002f },
+ { SGTL5000_DAP_EQ_BASS_BAND1, 0x002f },
+@@ -55,6 +69,7 @@
+ { SGTL5000_DAP_EQ_BASS_BAND3, 0x002f },
+ { SGTL5000_DAP_EQ_BASS_BAND4, 0x002f },
+ { SGTL5000_DAP_MAIN_CHAN, 0x8000 },
++ { SGTL5000_DAP_MIX_CHAN, 0x0000 },
+ { SGTL5000_DAP_AVC_CTRL, 0x0510 },
+ { SGTL5000_DAP_AVC_THRESHOLD, 0x1473 },
+ { SGTL5000_DAP_AVC_ATTACK, 0x0028 },
+@@ -1066,71 +1081,11 @@
+ return 0;
+ }
+
+-/*
+- * restore all sgtl5000 registers,
+- * since a big hole between dap and regular registers,
+- * we will restore them respectively.
+- */
+-static int sgtl5000_restore_regs(struct snd_soc_codec *codec)
+-{
+- u16 *cache = codec->reg_cache;
+- u16 reg;
+-
+- /* restore regular registers */
+- for (reg = 0; reg <= SGTL5000_CHIP_SHORT_CTRL; reg += 2) {
+-
+- /* These regs should restore in particular order */
+- if (reg == SGTL5000_CHIP_ANA_POWER ||
+- reg == SGTL5000_CHIP_CLK_CTRL ||
+- reg == SGTL5000_CHIP_LINREG_CTRL ||
+- reg == SGTL5000_CHIP_LINE_OUT_CTRL ||
+- reg == SGTL5000_CHIP_REF_CTRL)
+- continue;
+-
+- snd_soc_write(codec, reg, cache[reg]);
+- }
+-
+- /* restore dap registers */
+- for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
+- snd_soc_write(codec, reg, cache[reg]);
+-
+- /*
+- * restore these regs according to the power setting sequence in
+- * sgtl5000_set_power_regs() and clock setting sequence in
+- * sgtl5000_set_clock().
+- *
+- * The order of restore is:
+- * 1. SGTL5000_CHIP_CLK_CTRL MCLK_FREQ bits (1:0) should be restore after
+- * SGTL5000_CHIP_ANA_POWER PLL bits set
+- * 2. SGTL5000_CHIP_LINREG_CTRL should be set before
+- * SGTL5000_CHIP_ANA_POWER LINREG_D restored
+- * 3. SGTL5000_CHIP_REF_CTRL controls Analog Ground Voltage,
+- * prefer to resotre it after SGTL5000_CHIP_ANA_POWER restored
+- */
+- snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
+- cache[SGTL5000_CHIP_LINREG_CTRL]);
+-
+- snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
+- cache[SGTL5000_CHIP_ANA_POWER]);
+-
+- snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
+- cache[SGTL5000_CHIP_CLK_CTRL]);
+-
+- snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
+- cache[SGTL5000_CHIP_REF_CTRL]);
+-
+- snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
+- cache[SGTL5000_CHIP_LINE_OUT_CTRL]);
+- return 0;
+-}
+-
+ static int sgtl5000_resume(struct snd_soc_codec *codec)
+ {
+ /* Bring the codec back up to standby to enable regulators */
+ sgtl5000_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+
+- /* Restore registers by cached in memory */
+- sgtl5000_restore_regs(codec);
+ return 0;
+ }
+ #else
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/tda1997x.c linux-3.14.72/sound/soc/codecs/tda1997x.c
+--- linux-3.14.72.orig/sound/soc/codecs/tda1997x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/codecs/tda1997x.c 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,155 @@
++/*
++ * tda1997x.c -- tda1997x ALSA SoC Audio driver
++ *
++ * Copyright (C) 2013 Gateworks Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/clk.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/mfd/tda1997x-core.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/of_device.h>
++#include <linux/pm.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/machine.h>
++#include <linux/slab.h>
++#include <sound/core.h>
++#include <sound/initval.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++
++/* refine sample-rate based on HDMI source */
++static int tda1997x_pcm_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct snd_pcm_runtime *rtd = substream->runtime;
++ tda1997x_audout_fmt_t fmt;
++ int rate, ret;
++
++ ret = tda1997x_get_audout_fmt(&fmt);
++ if (ret) {
++ dev_err(codec->dev, "failed to obtain tda1997x info: %d\n",
++ ret);
++ return -EIO;
++ }
++ rate = fmt.samplerate;
++
++ ret = snd_pcm_hw_constraint_minmax(rtd, SNDRV_PCM_HW_PARAM_RATE,
++ rate, rate);
++ if (ret > 0)
++ dev_info(codec->dev, "set samplerate constraint to %dHz\n",
++ rate);
++ else
++ dev_err(codec->dev, "failed to set samplerate constraint "
++ "to %dHz: %d\n", rate, ret);
++
++ return 0;
++}
++
++static const struct snd_soc_dai_ops tda1997x_ops = {
++ .startup = tda1997x_pcm_startup,
++};
++
++static struct snd_soc_dai_driver tda1997x_codec_dai = {
++ .name = "tda1997x",
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 2,
++ .channels_max = 2,
++ /* rate and foramat are dependent on the HDMI source */
++ .rates = SNDRV_PCM_RATE_32000 |
++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
++ SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ },
++ .ops = &tda1997x_ops,
++};
++
++static int tda1997x_probe(struct snd_soc_codec *codec)
++{
++ pr_debug("%s\n", __func__);
++
++ return 0;
++}
++
++static int tda1997x_remove(struct snd_soc_codec *codec)
++{
++ pr_debug("%s\n", __func__);
++ return 0;
++}
++
++static struct snd_soc_codec_driver tda1997x_codec_driver = {
++ .probe = tda1997x_probe,
++ .remove = tda1997x_remove,
++ .reg_word_size = sizeof(u16),
++};
++
++static int tda1997x_codec_probe(struct platform_device *pdev)
++{
++ int ret = 0;
++
++ dev_info(&pdev->dev, "TDA1997x HDMI Audio In\n");
++
++ ret = snd_soc_register_codec(&pdev->dev,
++ &tda1997x_codec_driver, &tda1997x_codec_dai, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
++ return ret;
++ }
++ pr_debug("%s registered codec and codec_dai\n", __func__);
++
++ return 0;
++}
++
++static int tda1997x_codec_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_codec(&pdev->dev);
++
++ return 0;
++}
++
++static const struct of_device_id tda1997x_dt_ids[] = {
++ { .compatible = "nxp,tda1997x-codec", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, tda1997x_dt_ids);
++
++struct platform_driver tda1997x_driver = {
++ .driver = {
++ .name = "tda1997x_codec",
++ .owner = THIS_MODULE,
++ .of_match_table = tda1997x_dt_ids,
++ },
++ .probe = tda1997x_codec_probe,
++ .remove = tda1997x_codec_remove,
++};
++module_platform_driver(tda1997x_driver);
++
++MODULE_DESCRIPTION("NXP TDA1997x ALSA SoC Codec Driver");
++MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:tda1997x-audio");
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/vt1613.c linux-3.14.72/sound/soc/codecs/vt1613.c
+--- linux-3.14.72.orig/sound/soc/codecs/vt1613.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/codecs/vt1613.c 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,498 @@
++/*
++* vt1613.c -- ALSA SoC VT1613 AC'97 codec support
++*
++* Copyright 2010-2015 Seco s.r.l.
++*
++* This program is free software; you can redistribute it and/or
++* modify it under the terms of the GNU General Public License
++* version 2 as published by the Free Software Foundation.
++*
++* This program is distributed in the hope that it will be useful, but
++* WITHOUT ANY WARRANTY; without even the implied warranty of
++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++* General Public License for more details.
++*
++* You should have received a copy of the GNU General Public License
++* along with this program; if not, write to the Free Software
++* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
++* 02110-1301 USA
++*
++*/
++
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++#include <linux/of_device.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/initval.h>
++#include <sound/tlv.h>
++#include <sound/ac97_codec.h>
++
++#include "vt1613.h"
++#define DRV_NAME "vt1613-codec"
++
++bool vt1613_modules_dep = true;
++
++/* TODO: S/PDIF implementation. As this driver was developed for UDOO board's needs,
++* we skipped S/PDIF features developing*/
++
++static const struct reg_default vt1613_reg_defaults[] = {
++ { 0x00, 0x0140 }, /* Reset */
++ { 0x02, 0x8000 }, /* Stereo Output Volume */
++ { 0x04, 0x8000 }, /* HP Stereo Output Volume */
++ { 0x0A, 0x0000 }, /* PC Beep Volume */
++ { 0x0C, 0x8008 }, /* Phone Volume */
++ { 0x0E, 0x8008 }, /* MIC Volume */
++ { 0x10, 0x8808 }, /* Line In Volume */
++ { 0x12, 0x8808 }, /* CD Volume */
++ { 0x16, 0x8808 }, /* AUX Volume */
++ { 0x18, 0x8808 }, /* PCM out Volume */
++ { 0x1A, 0x0000 }, /* Record Select */
++ { 0x1C, 0x8000 }, /* Record Gain */
++ { 0x20, 0x0000 }, /* General Purpose */
++ { 0x24, 0x0001 }, /* Audio Interrupt & Paging (AC'97 2.3) */
++ { 0x26, 0x0000 }, /* Powerdown control / status */
++ { 0x28, 0x097C }, /* Extended Audio ID */
++ { 0x2A, 0x3830 }, /* Extended Audio Status and Control */
++ { 0x2C, 0xBB80 }, /* PCM Front DAC Rate */
++ { 0x32, 0xBB80 }, /* PCM LR ADC Rate */
++ { 0x3A, 0x2000 }, /* S/PDIF Control */
++ { 0x5A, 0x0000 }, /* Vendor Reserved Register */
++ { 0x5C, 0x00A9 }, /* Vendor Reserved Register */
++ { 0x62, 0xFFFF }, /* PCI SVID Page ID = 01h */
++ { 0x64, 0xFFFF }, /* PCI SID Page ID = 01h */
++ { 0x66, 0x0000 }, /* S/PDIF RX Status Page ID = 00h */
++ { 0x68, 0x0000 }, /* S/PDIF RX Status Page ID = 00h */
++ { 0x6A, 0x0000 }, /* S/PDIF RX Control Page ID = 00h */
++ { 0x6C, 0x376A }, /* DAC Slot Mapping Page ID = 01h */
++ { 0x6E, 0x0000 }, /* ADC Slot Mapping Page ID = 01h */
++ { 0x70, 0x0000 }, /* ADC / SPDIF RX Left Peak */
++ { 0x74, 0x0000 }, /* PLL Setting /Debugging */
++ { 0x76, 0x1182 }, /* Miscellaneous */
++ { 0x78, 0x0070 }, /* GPIO Control */
++ { 0x7A, 0x0070 }, /* GPIO Status */
++ { 0x7C, 0x5649 }, /* Vendor ID1 */
++ { 0x7E, 0x4120 }, /* Vendor ID2 */
++};
++
++static bool vt1613_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case AC97_RESET ... AC97_HEADPHONE:
++ case AC97_PC_BEEP ... AC97_CD:
++ case AC97_AUX ... AC97_GENERAL_PURPOSE:
++ case AC97_INT_PAGING ... AC97_PCM_LR_ADC_RATE:
++ case AC97_SPDIF:
++ case AC97_AD_TEST:
++ case AC97_VT1613_STEREO_MIC:
++ case AC97_PCI_SVID ... AC97_SENSE_INFO:
++ case AC97_VT1613_DAC_SLOT_MAP:
++ case AC97_VT1613_ADC_SLOT_MAP:
++ case AC97_AD_CODEC_CFG:
++ case AC97_AD_SERIAL_CFG:
++ case AC97_AD_MISC:
++ case AC97_VT1613_GPIO_CTRL:
++ case AC97_VT1613_GPIO_STATUS:
++ case AC97_VENDOR_ID1:
++ case AC97_VENDOR_ID2:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool vt1613_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case AC97_RESET:
++ case AC97_EXTENDED_ID:
++ case AC97_PCM_SURR_DAC_RATE:
++ case AC97_PCM_LFE_DAC_RATE:
++ case AC97_FUNC_SELECT:
++ case AC97_FUNC_INFO:
++ case AC97_VT1613_ADC_SLOT_MAP:
++ case AC97_VENDOR_ID1:
++ case AC97_VENDOR_ID2:
++ return false;
++ default:
++ return vt1613_readable_reg(dev, reg);
++ }
++}
++
++static const struct regmap_config vt1613_regmap_config = {
++ .name = "vt1613_regmap",
++ .reg_bits = 16,
++ .reg_stride = 2,
++ .val_bits = 16,
++ .max_register = 0x7E,
++ .cache_type = REGCACHE_RBTREE,
++
++ .volatile_reg = regmap_ac97_default_volatile,
++ .readable_reg = vt1613_readable_reg,
++ .writeable_reg = vt1613_writeable_reg,
++
++ .reg_defaults = vt1613_reg_defaults,
++ .num_reg_defaults = ARRAY_SIZE(vt1613_reg_defaults),
++};
++
++static const char *vt1613_record_mux[] = {"Mic", "CD", "--", "AUX",
++ "Line", "Stereo Mix", "Mono Mix", "Phone"};
++static SOC_ENUM_DOUBLE_DECL(vt1613_record_enum,
++ AC97_REC_SEL, 8, 0, vt1613_record_mux);
++
++static const char *vt1613_mic_mux[] = {"Mic1", "Mic2"};
++static SOC_ENUM_SINGLE_DECL(vt1613_mic_enum,
++ AC97_GENERAL_PURPOSE, 8, vt1613_mic_mux);
++
++static const char *vt1613_boost[] = {"0dB", "20dB"};
++static SOC_ENUM_SINGLE_DECL(vt1613_boost_enum,
++ AC97_MIC, 6, vt1613_boost);
++
++static const char *vt1613_mic_sel[] = {"MonoMic", "StereoMic"};
++static SOC_ENUM_SINGLE_DECL(vt1613_mic_sel_enum,
++ AC97_VT1613_STEREO_MIC, 2, vt1613_mic_sel);
++
++static const DECLARE_TLV_DB_LINEAR(master_tlv, -4650, 0);
++static const DECLARE_TLV_DB_LINEAR(record_tlv, 0, 2250);
++static const DECLARE_TLV_DB_LINEAR(beep_tlv, -4500, 0);
++static const DECLARE_TLV_DB_LINEAR(mix_tlv, -3450, 1200);
++
++static const struct snd_kcontrol_new vt1613_snd_ac97_controls[] = {
++ SOC_DOUBLE_TLV("Speaker Playback Volume", AC97_MASTER, 8, 0, 31, 1, master_tlv),
++ SOC_SINGLE("Speaker Playback Switch", AC97_MASTER, 15, 1, 1),
++
++ SOC_DOUBLE_TLV("Headphone Playback Volume", AC97_HEADPHONE, 8, 0, 31, 1, master_tlv),
++ SOC_SINGLE("Headphone Playback Switch", AC97_HEADPHONE, 15, 1, 1),
++
++ SOC_DOUBLE_TLV("PCM Playback Volume", AC97_PCM, 8, 0, 31, 0, mix_tlv),
++ SOC_SINGLE("PCM Playback Switch", AC97_PCM, 15, 1, 1),
++
++ SOC_DOUBLE_TLV("Record Capture Volume", AC97_REC_GAIN, 8, 0, 15, 0, record_tlv),
++ SOC_SINGLE("Record Capture Switch", AC97_REC_GAIN, 15, 1, 1),
++
++ SOC_SINGLE_TLV("Beep Volume", AC97_PC_BEEP, 1, 15, 1, beep_tlv),
++ SOC_SINGLE("Beep Switch", AC97_PC_BEEP, 15, 1, 1),
++ SOC_SINGLE_TLV("Phone Volume", AC97_PHONE, 0, 31, 0, mix_tlv),
++ SOC_SINGLE("Phone Switch", AC97_PHONE, 15, 1, 1),
++
++ /* Mono Mic and Stereo Mic's right channel controls */
++ SOC_SINGLE_TLV("Mic/StereoMic_R Volume", AC97_MIC, 0, 31, 0, mix_tlv),
++ SOC_SINGLE("Mic/StereoMic_R Switch", AC97_MIC, 15, 1, 1),
++
++ /* Stereo Mic's left channel controls */
++ SOC_SINGLE("StereoMic_L Switch", AC97_MIC, 7, 1, 1),
++ SOC_SINGLE_TLV("StereoMic_L Volume", AC97_MIC, 8, 31, 0, mix_tlv),
++
++ SOC_DOUBLE_TLV("Line Volume", AC97_LINE, 8, 0, 31, 0, mix_tlv),
++ SOC_SINGLE("Line Switch", AC97_LINE, 15, 1, 1),
++ SOC_DOUBLE_TLV("CD Volume", AC97_CD, 8, 0, 31, 0, mix_tlv),
++ SOC_SINGLE("CD Switch", AC97_CD, 15, 1, 1),
++ SOC_DOUBLE_TLV("AUX Volume", AC97_AUX, 8, 0, 31, 0, mix_tlv),
++ SOC_SINGLE("AUX Switch", AC97_AUX, 15, 1, 1),
++
++ SOC_SINGLE("Analog Loopback", AC97_GENERAL_PURPOSE, 7, 1, 0),
++
++ SOC_ENUM("Mic Boost", vt1613_boost_enum),
++ SOC_ENUM("Mic1/2 Mux", vt1613_mic_enum),
++ SOC_ENUM("Mic Select", vt1613_mic_sel_enum),
++ SOC_ENUM("Record Mux", vt1613_record_enum),
++};
++
++static const unsigned int vt1613_rates[] = {
++ 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000
++};
++
++static const struct snd_pcm_hw_constraint_list vt1613_rate_constraints = {
++ .count = ARRAY_SIZE(vt1613_rates),
++ .list = vt1613_rates,
++};
++
++static int vt1613_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
++ snd_pcm_hw_constraint_list(substream->runtime, 0,
++ SNDRV_PCM_HW_PARAM_RATE, &vt1613_rate_constraints);
++ } else {
++ snd_pcm_hw_constraint_list(substream->runtime, 0,
++ SNDRV_PCM_HW_PARAM_RATE, &vt1613_rate_constraints);
++ }
++
++ return 0;
++}
++
++static int ac97_analog_prepare(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ unsigned short reg;
++
++ /* enable variable rate audio (VRA) and disable S/PDIF output */
++ snd_soc_write(codec, AC97_EXTENDED_STATUS,
++ (snd_soc_read(codec, AC97_EXTENDED_STATUS) | 0x1) & ~0x4);
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK){
++ reg = AC97_PCM_FRONT_DAC_RATE;
++ } else {
++ reg = AC97_PCM_LR_ADC_RATE;
++ }
++
++ return snd_soc_write(codec, reg, runtime->rate);
++}
++
++static int ac97_digital_prepare(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_codec *codec = dai->codec;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++
++ snd_soc_write(codec, AC97_SPDIF, 0x2002);
++
++ /* enable VRA and S/PDIF output */
++ snd_soc_write(codec, AC97_EXTENDED_STATUS, snd_soc_read(codec, AC97_EXTENDED_STATUS) | 0x5);
++
++ return snd_soc_write(codec, AC97_PCM_FRONT_DAC_RATE, runtime->rate);
++}
++
++static int vt1613_set_bias_level(struct snd_soc_codec *codec,
++ enum snd_soc_bias_level level)
++{
++ switch (level) {
++ case SND_SOC_BIAS_ON: /* full On */
++ case SND_SOC_BIAS_PREPARE: /* partial On */
++ case SND_SOC_BIAS_STANDBY: /* Off, with power */
++ snd_soc_write(codec, AC97_POWERDOWN, 0x0000);
++ break;
++ case SND_SOC_BIAS_OFF: /* Off, without power */
++ /* disable everything including AC link */
++ snd_soc_write(codec, AC97_POWERDOWN, 0xffff);
++ break;
++ }
++ codec->dapm.bias_level = level;
++ return 0;
++}
++
++static int vt1613_reset(struct snd_soc_codec *codec, int try_warm)
++{
++
++ if (try_warm && soc_ac97_ops->warm_reset) {
++ soc_ac97_ops->warm_reset(codec->ac97);
++ if (snd_soc_read(codec, AC97_RESET) == 0x0140)
++ return 1;
++ }
++ soc_ac97_ops->reset(codec->ac97);
++ if (soc_ac97_ops->warm_reset)
++ soc_ac97_ops->warm_reset(codec->ac97);
++ if (snd_soc_read(codec, AC97_RESET) == 0x0140)
++ return 0;
++
++ return -EIO;
++}
++
++static struct snd_soc_dai_ops vt1613_dai_ops_analog = {
++ .startup = vt1613_startup,
++ .prepare = ac97_analog_prepare,
++};
++
++static struct snd_soc_dai_ops vt1613_dai_ops_digital = {
++ .prepare = ac97_digital_prepare,
++};
++
++struct snd_soc_dai_driver vt1613_dai[] = {
++{
++ .name = "vt1613-hifi-analog",
++ .ac97_control = 1,
++
++ .playback = {
++ .stream_name = "Playback",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_KNOT,
++ .formats = SND_SOC_STD_AC97_FMTS,
++ },
++ .capture = {
++ .stream_name = "Capture",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_KNOT,
++ .formats = SND_SOC_STD_AC97_FMTS,
++ },
++
++ .ops = &vt1613_dai_ops_analog,
++},
++{
++ .name = "vt1613-hifi-IEC958",
++ .ac97_control = 1,
++
++ .playback = {
++ .stream_name = "vt1613 IEC958",
++ .channels_min = 1,
++ .channels_max = 2,
++ .rates = SNDRV_PCM_RATE_32000 |
++ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
++ .formats = SNDRV_PCM_FORMAT_IEC958_SUBFRAME_BE,
++ },
++
++ .ops = &vt1613_dai_ops_digital,
++}
++};
++
++static int vt1613_codec_suspend(struct snd_soc_codec *codec)
++{
++ vt1613_set_bias_level(codec, SND_SOC_BIAS_OFF);
++
++ return 0;
++}
++
++static int vt1613_codec_resume(struct snd_soc_codec *codec)
++{
++ u16 id, reset;
++
++ reset = 0;
++ /* give the codec an AC97 warm reset to start the link */
++reset:
++ if (reset > 5) {
++ printk(KERN_ERR "vt1613 failed to resume");
++ return -EIO;
++ }
++ codec->ac97->bus->ops->warm_reset(codec->ac97);
++ id = soc_ac97_ops->read(codec->ac97, AC97_VENDOR_ID2);
++ if (id != 0x4123) {
++ vt1613_reset(codec, 0);
++ reset++;
++ goto reset;
++ }
++ vt1613_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++
++ return 0;
++}
++
++static int vt1613_codec_probe(struct snd_soc_codec *codec)
++{
++ int ret = 0;
++ struct regmap *regmap;
++
++ ret = snd_soc_new_ac97_codec(codec, soc_ac97_ops, 0);
++ if (ret){
++ dev_err(codec->dev, "Failed to register AC97 codec: %d\n", ret);
++ return ret;
++ }
++
++ soc_ac97_dev_register(codec);
++ if (ret){
++ dev_err(codec->dev, "Failed to register AC97 codec to bus: %d\n", ret);
++ goto free_ac97;
++ }
++ codec->ac97_registered = 1;
++
++ regmap = regmap_init_ac97(codec->ac97, &vt1613_regmap_config);
++ if (IS_ERR(regmap)) {
++ ret = PTR_ERR(regmap);
++ dev_err(codec->dev, "Failed to init register map: %d\n", ret);
++ goto free_ac97;
++ }
++
++ codec->control_data = regmap;
++ ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
++ if (ret < 0) {
++ dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
++ goto free_regmap;
++ }
++ snd_soc_codec_set_drvdata(codec, codec->ac97);
++
++ /* do a cold reset for the controller and then try
++ * a warm reset followed by an optional cold reset for codec */
++
++ vt1613_reset(codec, 0);
++ ret = vt1613_reset(codec, 1);
++ if (ret < 0) {
++ printk(KERN_ERR "Failed to reset VT1613: AC97 link error\n");
++ goto free_regmap;
++ }
++
++ /* Read out vendor IDs */
++ printk(KERN_INFO "VT1613 SoC Audio Codec [ID = %04x - %04x]\n",
++ snd_soc_read(codec, AC97_VENDOR_ID1), snd_soc_read(codec, AC97_VENDOR_ID2));
++
++ vt1613_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
++
++ /* unmute captures and playbacks volume */
++ snd_soc_write(codec, AC97_MASTER, 0x0000);
++ snd_soc_write(codec, AC97_PCM, 0x0000);
++ snd_soc_write(codec, AC97_REC_GAIN, 0x0000);
++
++ /* At 3.3V analog supply, for the bits 3:2 should be set 10b for the lowest power instead of default 00b */
++ snd_soc_write(codec, AC97_AD_TEST, snd_soc_read(codec, AC97_AD_TEST) | 0x0008);
++
++ /* To maximize recording quality by removing white noise */
++ snd_soc_write(codec, AC97_AD_TEST, snd_soc_read(codec, AC97_AD_TEST) | 0x0400);
++
++ snd_soc_add_codec_controls(codec, vt1613_snd_ac97_controls,
++ ARRAY_SIZE(vt1613_snd_ac97_controls));
++
++ return 0;
++
++free_regmap:
++ regmap_exit(regmap);
++free_ac97:
++ snd_soc_free_ac97_codec(codec);
++
++ return ret;
++}
++
++static int vt1613_codec_remove(struct snd_soc_codec *codec)
++{
++ regmap_exit(codec->control_data);
++ snd_soc_free_ac97_codec(codec);
++ return 0;
++}
++
++struct snd_soc_codec_driver vt1613_codec = {
++ .probe = vt1613_codec_probe,
++ .remove = vt1613_codec_remove,
++ .suspend = vt1613_codec_suspend,
++ .resume = vt1613_codec_resume,
++ .set_bias_level = vt1613_set_bias_level,
++};
++
++static int vt1613_probe(struct platform_device *pdev)
++{
++ return snd_soc_register_codec(&pdev->dev,
++ &vt1613_codec, vt1613_dai, ARRAY_SIZE(vt1613_dai));
++}
++
++static int vt1613_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_codec(&pdev->dev);
++ return 0;
++}
++
++static const struct of_device_id vt1613_of_match[] = {
++ { .compatible = "via,vt1613", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, vt1613_of_match);
++
++static struct platform_driver vt1613_codec_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = vt1613_of_match,
++ },
++
++ .probe = vt1613_probe,
++ .remove = vt1613_remove,
++};
++
++module_platform_driver(vt1613_codec_driver);
++
++EXPORT_SYMBOL_GPL(vt1613_modules_dep);
++
++MODULE_DESCRIPTION("ASoC VT1613 codec driver");
++MODULE_AUTHOR("Seco s.r.l.");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRV_NAME);
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/vt1613.h linux-3.14.72/sound/soc/codecs/vt1613.h
+--- linux-3.14.72.orig/sound/soc/codecs/vt1613.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/codecs/vt1613.h 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,29 @@
++/*
++ * vt1613.h - VT1613 audio codec interface
++ *
++ * Copyright 2010-2015 Seco s.r.l.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#ifndef _VT1613_H
++#define _VT1613_H
++
++#define AC97_VT1613_DAC_SLOT_MAP 0x6C
++#define AC97_VT1613_ADC_SLOT_MAP 0x6E
++
++#define AC97_VT1613_GPIO_CTRL 0x78
++#define AC97_VT1613_GPIO_STATUS 0x7A
++
++#define AC97_VT1613_STEREO_MIC 0x5C
++
++/* VT1613 DAI ID's */
++#define VT1613_DAI_AC97_ANALOG 0
++#define VT1613_DAI_AC97_DIGITAL 1
++
++extern bool vt1613_modules_dep;
++
++#endif
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/wm8960.c linux-3.14.72/sound/soc/codecs/wm8960.c
+--- linux-3.14.72.orig/sound/soc/codecs/wm8960.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/codecs/wm8960.c 2016-06-19 22:11:55.521125834 +0200
+@@ -125,9 +125,10 @@
+ struct snd_soc_dapm_widget *out3;
+ bool deemph;
+ int playback_fs;
++ struct wm8960_data pdata;
+ };
+
+-#define wm8960_reset(c) snd_soc_write(c, WM8960_RESET, 0)
++#define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0)
+
+ /* enumerated controls */
+ static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
+@@ -440,8 +441,8 @@
+
+ static int wm8960_add_widgets(struct snd_soc_codec *codec)
+ {
+- struct wm8960_data *pdata = codec->dev->platform_data;
+ struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
++ struct wm8960_data *pdata = &wm8960->pdata;
+ struct snd_soc_dapm_context *dapm = &codec->dapm;
+ struct snd_soc_dapm_widget *w;
+
+@@ -945,36 +946,16 @@
+ .symmetric_rates = 1,
+ };
+
+-static int wm8960_suspend(struct snd_soc_codec *codec)
+-{
+- struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+-
+- wm8960->set_bias_level(codec, SND_SOC_BIAS_OFF);
+- return 0;
+-}
+-
+-static int wm8960_resume(struct snd_soc_codec *codec)
+-{
+- struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+-
+- wm8960->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+- return 0;
+-}
+-
+ static int wm8960_probe(struct snd_soc_codec *codec)
+ {
+ struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+- struct wm8960_data *pdata = dev_get_platdata(codec->dev);
++ struct wm8960_data *pdata = &wm8960->pdata;
+ int ret;
+
+- wm8960->set_bias_level = wm8960_set_bias_level_out3;
+-
+- if (!pdata) {
+- dev_warn(codec->dev, "No platform data supplied\n");
+- } else {
+- if (pdata->capless)
+- wm8960->set_bias_level = wm8960_set_bias_level_capless;
+- }
++ if (pdata->capless)
++ wm8960->set_bias_level = wm8960_set_bias_level_capless;
++ else
++ wm8960->set_bias_level = wm8960_set_bias_level_out3;
+
+ ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
+ if (ret < 0) {
+@@ -982,26 +963,6 @@
+ return ret;
+ }
+
+- ret = wm8960_reset(codec);
+- if (ret < 0) {
+- dev_err(codec->dev, "Failed to issue reset\n");
+- return ret;
+- }
+-
+- wm8960->set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+-
+- /* Latch the update bits */
+- snd_soc_update_bits(codec, WM8960_LINVOL, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_RINVOL, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_LADC, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_RADC, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_LDAC, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_RDAC, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_LOUT1, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_ROUT1, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_LOUT2, 0x100, 0x100);
+- snd_soc_update_bits(codec, WM8960_ROUT2, 0x100, 0x100);
+-
+ snd_soc_add_codec_controls(codec, wm8960_snd_controls,
+ ARRAY_SIZE(wm8960_snd_controls));
+ wm8960_add_widgets(codec);
+@@ -1009,21 +970,10 @@
+ return 0;
+ }
+
+-/* power down chip */
+-static int wm8960_remove(struct snd_soc_codec *codec)
+-{
+- struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
+-
+- wm8960->set_bias_level(codec, SND_SOC_BIAS_OFF);
+- return 0;
+-}
+-
+ static struct snd_soc_codec_driver soc_codec_dev_wm8960 = {
+ .probe = wm8960_probe,
+- .remove = wm8960_remove,
+- .suspend = wm8960_suspend,
+- .resume = wm8960_resume,
+ .set_bias_level = wm8960_set_bias_level,
++ .idle_bias_off = true,
+ };
+
+ static const struct regmap_config wm8960_regmap = {
+@@ -1038,6 +988,18 @@
+ .volatile_reg = wm8960_volatile,
+ };
+
++static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
++ struct wm8960_data *pdata)
++{
++ const struct device_node *np = i2c->dev.of_node;
++
++ if (of_property_read_bool(np, "wlf,capless"))
++ pdata->capless = true;
++
++ if (of_property_read_bool(np, "wlf,shared-lrclk"))
++ pdata->shared_lrclk = true;
++}
++
+ static int wm8960_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+ {
+@@ -1054,7 +1016,18 @@
+ if (IS_ERR(wm8960->regmap))
+ return PTR_ERR(wm8960->regmap);
+
+- if (pdata && pdata->shared_lrclk) {
++ if (pdata)
++ memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
++ else if (i2c->dev.of_node)
++ wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
++
++ ret = wm8960_reset(wm8960->regmap);
++ if (ret != 0) {
++ dev_err(&i2c->dev, "Failed to issue reset\n");
++ return ret;
++ }
++
++ if (wm8960->pdata.shared_lrclk) {
+ ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
+ 0x4, 0x4);
+ if (ret != 0) {
+@@ -1064,6 +1037,18 @@
+ }
+ }
+
++ /* Latch the update bits */
++ regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
++ regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
++
+ i2c_set_clientdata(i2c, wm8960);
+
+ ret = snd_soc_register_codec(&i2c->dev,
+@@ -1084,10 +1069,17 @@
+ };
+ MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
+
++static const struct of_device_id wm8960_of_match[] = {
++ { .compatible = "wlf,wm8960", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, wm8960_of_match);
++
+ static struct i2c_driver wm8960_i2c_driver = {
+ .driver = {
+ .name = "wm8960",
+ .owner = THIS_MODULE,
++ .of_match_table = wm8960_of_match,
+ },
+ .probe = wm8960_i2c_probe,
+ .remove = wm8960_i2c_remove,
+diff -Nur linux-3.14.72.orig/sound/soc/codecs/wm8962.c linux-3.14.72/sound/soc/codecs/wm8962.c
+--- linux-3.14.72.orig/sound/soc/codecs/wm8962.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/codecs/wm8962.c 2016-06-19 22:11:55.521125834 +0200
+@@ -14,6 +14,7 @@
+ #include <linux/module.h>
+ #include <linux/moduleparam.h>
+ #include <linux/init.h>
++#include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/pm.h>
+ #include <linux/gcd.h>
+@@ -2586,16 +2587,16 @@
+ if (wm8962->lrclk % 8000 == 0)
+ adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
+
+- switch (params_format(params)) {
+- case SNDRV_PCM_FORMAT_S16_LE:
++ switch (params_width(params)) {
++ case 16:
+ break;
+- case SNDRV_PCM_FORMAT_S20_3LE:
++ case 20:
+ aif0 |= 0x4;
+ break;
+- case SNDRV_PCM_FORMAT_S24_LE:
++ case 24:
+ aif0 |= 0x8;
+ break;
+- case SNDRV_PCM_FORMAT_S32_LE:
++ case 32:
+ aif0 |= 0xc;
+ break;
+ default:
+@@ -2942,7 +2943,8 @@
+ WM8962_DAC_MUTE, val);
+ }
+
+-#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
++#define WM8962_RATES (SNDRV_PCM_RATE_8000_48000 |\
++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
+
+ #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+@@ -3536,6 +3538,8 @@
+ pdata->gpio_init[i] = 0x0;
+ }
+
++ pdata->mclk = devm_clk_get(&i2c->dev, NULL);
++
+ return 0;
+ }
+
+@@ -3567,6 +3571,14 @@
+ return ret;
+ }
+
++ /* Mark the mclk pointer to NULL if no mclk assigned */
++ if (IS_ERR(wm8962->pdata.mclk)) {
++ /* But do not ignore the request for probe defer */
++ if (PTR_ERR(wm8962->pdata.mclk) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
++ wm8962->pdata.mclk = NULL;
++ }
++
+ for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
+ wm8962->supplies[i].supply = wm8962_supply_names[i];
+
+@@ -3775,6 +3787,12 @@
+ struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
+ int ret;
+
++ ret = clk_prepare_enable(wm8962->pdata.mclk);
++ if (ret) {
++ dev_err(dev, "Failed to enable MCLK: %d\n", ret);
++ return ret;
++ }
++
+ ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
+ wm8962->supplies);
+ if (ret != 0) {
+@@ -3834,6 +3852,8 @@
+ regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
+ wm8962->supplies);
+
++ clk_disable_unprepare(wm8962->pdata.mclk);
++
+ return 0;
+ }
+ #endif
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_asrc.c linux-3.14.72/sound/soc/fsl/fsl_asrc.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_asrc.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/fsl_asrc.c 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,1139 @@
++/*
++ * Freescale ASRC ALSA SoC Digital Audio Interface (DAI) driver
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Author: Nicolin Chen <nicoleotsuka@gmail.com>
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/platform_data/dma-imx.h>
++#include <linux/pm_runtime.h>
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm_params.h>
++
++#include "fsl_asrc.h"
++
++#define IDEAL_RATIO_DECIMAL_DEPTH 26
++
++#define pair_err(fmt, ...) \
++ dev_err(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
++
++#define pair_dbg(fmt, ...) \
++ dev_dbg(&asrc_priv->pdev->dev, "Pair %c: " fmt, 'A' + index, ##__VA_ARGS__)
++
++/* Sample rates are aligned with that defined in pcm.h file */
++static const u8 process_option[][8][2] = {
++ /* 32kHz 44.1kHz 48kHz 64kHz 88.2kHz 96kHz 176kHz 192kHz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 5512Hz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 8kHz */
++ {{0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 11025Hz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 16kHz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0},}, /* 22050Hz */
++ {{0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0}, {0, 0},}, /* 32kHz */
++ {{0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 44.1kHz */
++ {{0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0}, {0, 0},}, /* 48kHz */
++ {{1, 2}, {0, 2}, {0, 2}, {0, 1}, {0, 1}, {0, 1}, {0, 1}, {0, 0},}, /* 64kHz */
++ {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 88.2kHz */
++ {{1, 2}, {1, 2}, {1, 2}, {1, 1}, {1, 1}, {1, 1}, {1, 1}, {1, 1},}, /* 96kHz */
++ {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 176kHz */
++ {{2, 2}, {2, 2}, {2, 2}, {2, 1}, {2, 1}, {2, 1}, {2, 1}, {2, 1},}, /* 192kHz */
++};
++
++/* Corresponding to process_option */
++static int supported_input_rate[] = {
++ 5512, 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 88200,
++ 96000, 176400, 192000,
++};
++
++static int supported_asrc_rate[] = {
++ 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000,
++};
++
++/**
++ * The following tables map the relationship between asrc_inclk/asrc_outclk in
++ * fsl_asrc.h and the registers of ASRCSR
++ */
++static unsigned char input_clk_map_imx35[] = {
++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
++};
++
++static unsigned char output_clk_map_imx35[] = {
++ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
++};
++
++/* i.MX53 uses the same map for input and output */
++static unsigned char input_clk_map_imx53[] = {
++/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
++ 0x0, 0x1, 0x2, 0x7, 0x4, 0x5, 0x6, 0x3, 0x8, 0x9, 0xa, 0xb, 0xc, 0xf, 0xe, 0xd,
++};
++
++static unsigned char output_clk_map_imx53[] = {
++/* 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf */
++ 0x8, 0x9, 0xa, 0x7, 0xc, 0x5, 0x6, 0xb, 0x0, 0x1, 0x2, 0x3, 0x4, 0xf, 0xe, 0xd,
++};
++
++static unsigned char *clk_map[2];
++
++/**
++ * Request ASRC pair
++ *
++ * It assigns pair by the order of A->C->B because allocation of pair B,
++ * within range [ANCA, ANCA+ANCB-1], depends on the channels of pair A
++ * while pair A and pair C are comparatively independent.
++ */
++static int fsl_asrc_request_pair(int channels, struct fsl_asrc_pair *pair)
++{
++ enum asrc_pair_index index = ASRC_INVALID_PAIR;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct device *dev = &asrc_priv->pdev->dev;
++ unsigned long lock_flags;
++ int i, ret = 0;
++
++ spin_lock_irqsave(&asrc_priv->lock, lock_flags);
++
++ for (i = ASRC_PAIR_A; i < ASRC_PAIR_MAX_NUM; i++) {
++ if (asrc_priv->pair[i] != NULL)
++ continue;
++
++ index = i;
++
++ if (i != ASRC_PAIR_B)
++ break;
++ }
++
++ if (index == ASRC_INVALID_PAIR) {
++ dev_err(dev, "all pairs are busy now\n");
++ ret = -EBUSY;
++ } else if (asrc_priv->channel_avail < channels ||
++ (asrc_priv->channel_bits < 4 && channels % 2 != 0)) {
++ dev_err(dev, "can't afford required channels: %d\n", channels);
++ ret = -EINVAL;
++ } else {
++ asrc_priv->channel_avail -= channels;
++ asrc_priv->pair[index] = pair;
++ pair->channels = channels;
++ pair->index = index;
++ }
++
++ spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
++
++ return ret;
++}
++
++/**
++ * Release ASRC pair
++ *
++ * It clears the resource from asrc_priv and releases the occupied channels.
++ */
++static void fsl_asrc_release_pair(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ unsigned long lock_flags;
++
++ /* Make sure the pair is disabled */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEi_MASK(index), 0);
++
++ spin_lock_irqsave(&asrc_priv->lock, lock_flags);
++
++ asrc_priv->channel_avail += pair->channels;
++ asrc_priv->pair[index] = NULL;
++ pair->error = 0;
++
++ spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
++}
++
++/**
++ * Configure input and output thresholds
++ */
++static void fsl_asrc_set_watermarks(struct fsl_asrc_pair *pair, u32 in, u32 out)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++
++ regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
++ ASRMCRi_EXTTHRSHi_MASK |
++ ASRMCRi_INFIFO_THRESHOLD_MASK |
++ ASRMCRi_OUTFIFO_THRESHOLD_MASK,
++ ASRMCRi_EXTTHRSHi |
++ ASRMCRi_INFIFO_THRESHOLD(in) |
++ ASRMCRi_OUTFIFO_THRESHOLD(out));
++}
++
++/**
++ * Calculate the total divisor between asrck clock rate and sample rate
++ *
++ * It follows the formula clk_rate = samplerate * (2 ^ prescaler) * divider
++ */
++static u32 fsl_asrc_cal_asrck_divisor(struct fsl_asrc_pair *pair, u32 div)
++{
++ u32 ps;
++
++ /* Calculate the divisors: prescaler [2^0, 2^7], divder [1, 8] */
++ for (ps = 0; div > 8; ps++)
++ div >>= 1;
++
++ return ((div - 1) << ASRCDRi_AxCPi_WIDTH) | ps;
++}
++
++/**
++ * Calculate and set the ratio for Ideal Ratio mode only
++ *
++ * The ratio is a 32-bit fixed point value with 26 fractional bits.
++ */
++static int fsl_asrc_set_ideal_ratio(struct fsl_asrc_pair *pair,
++ int inrate, int outrate)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ unsigned long ratio;
++ int i;
++
++ if (!outrate) {
++ pair_err("output rate should not be zero\n");
++ return -EINVAL;
++ }
++
++ /* Calculate the intergal part of the ratio */
++ ratio = (inrate / outrate) << IDEAL_RATIO_DECIMAL_DEPTH;
++
++ /* ... and then the 26 depth decimal part */
++ inrate %= outrate;
++
++ for (i = 1; i <= IDEAL_RATIO_DECIMAL_DEPTH; i++) {
++ inrate <<= 1;
++
++ if (inrate < outrate)
++ continue;
++
++ ratio |= 1 << (IDEAL_RATIO_DECIMAL_DEPTH - i);
++ inrate -= outrate;
++
++ if (!inrate)
++ break;
++ }
++
++ regmap_write(asrc_priv->regmap, REG_ASRIDRL(index), ratio);
++ regmap_write(asrc_priv->regmap, REG_ASRIDRH(index), ratio >> 24);
++
++ return 0;
++}
++
++/**
++ * Configure the assigned ASRC pair
++ *
++ * It configures those ASRC registers according to a configuration instance
++ * of struct asrc_config which includes in/output sample rate, width, channel
++ * and clock settings.
++ */
++static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool p2p_in, bool p2p_out)
++{
++ struct asrc_config *config = pair->config;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ u32 inrate, outrate, indiv, outdiv;
++ u32 clk_index[2], div[2];
++ int in, out, channels;
++ struct clk *clk;
++ bool ideal;
++
++ if (!config) {
++ pair_err("invalid pair config\n");
++ return -EINVAL;
++ }
++
++ /* Validate channels */
++ if (config->channel_num < 1 || config->channel_num > 10) {
++ pair_err("does not support %d channels\n", config->channel_num);
++ return -EINVAL;
++ }
++
++ /* Validate output width */
++ if (config->output_word_width == ASRC_WIDTH_8_BIT) {
++ pair_err("does not support 8bit width output\n");
++ return -EINVAL;
++ }
++
++ inrate = config->input_sample_rate;
++ outrate = config->output_sample_rate;
++ ideal = config->inclk == INCLK_NONE;
++
++ /* Validate input and output sample rates */
++ for (in = 0; in < ARRAY_SIZE(supported_input_rate); in++)
++ if (inrate == supported_input_rate[in])
++ break;
++
++ if (in == ARRAY_SIZE(supported_input_rate)) {
++ pair_err("unsupported input sample rate: %dHz\n", inrate);
++ return -EINVAL;
++ }
++
++ for (out = 0; out < ARRAY_SIZE(supported_asrc_rate); out++)
++ if (outrate == supported_asrc_rate[out])
++ break;
++
++ if (out == ARRAY_SIZE(supported_asrc_rate)) {
++ pair_err("unsupported output sample rate: %dHz\n", outrate);
++ return -EINVAL;
++ }
++
++ /* Validate input and output clock sources */
++ clk_index[IN] = clk_map[IN][config->inclk];
++ clk_index[OUT] = clk_map[OUT][config->outclk];
++
++ /* We only have output clock for ideal ratio mode */
++ clk = asrc_priv->asrck_clk[clk_index[ideal ? OUT : IN]];
++
++ div[IN] = clk_get_rate(clk) / inrate;
++ if (div[IN] == 0) {
++ pair_err("failed to support input sample rate %dHz by asrck_%x\n",
++ inrate, clk_index[ideal ? OUT : IN]);
++ return -EINVAL;
++ }
++
++ clk = asrc_priv->asrck_clk[clk_index[OUT]];
++
++ /*
++ * When P2P mode, output rate should align with the out samplerate.
++ * if set too high output rate, there will be lots of Overload.
++ * When M2M mode, output rate should also need to align with the out
++ * samplerate, but M2M must use less time to achieve good performance.
++ */
++ if (p2p_out)
++ div[OUT] = clk_get_rate(clk) / outrate;
++ else
++ div[OUT] = clk_get_rate(clk) / IDEAL_RATIO_RATE;
++
++
++ if (div[OUT] == 0) {
++ pair_err("failed to support output sample rate %dHz by asrck_%x\n",
++ outrate, clk_index[OUT]);
++ return -EINVAL;
++ }
++
++ /* Set the channel number */
++ channels = config->channel_num;
++
++ if (asrc_priv->channel_bits < 4)
++ channels /= 2;
++
++ /* Update channels for current pair */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCNCR,
++ ASRCNCR_ANCi_MASK(index, asrc_priv->channel_bits),
++ ASRCNCR_ANCi(index, channels, asrc_priv->channel_bits));
++
++ /* Default setting: Automatic selection for processing mode */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_ATSi_MASK(index), ASRCTR_ATS(index));
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_USRi_MASK(index), 0);
++
++ /* Set the input and output clock sources */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCSR,
++ ASRCSR_AICSi_MASK(index) | ASRCSR_AOCSi_MASK(index),
++ ASRCSR_AICS(index, clk_index[IN]) |
++ ASRCSR_AOCS(index, clk_index[OUT]));
++
++ /* Calculate the input clock divisors */
++ indiv = fsl_asrc_cal_asrck_divisor(pair, div[IN]);
++ outdiv = fsl_asrc_cal_asrck_divisor(pair, div[OUT]);
++
++ /* Suppose indiv and outdiv includes prescaler, so add its MASK too */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCDR(index),
++ ASRCDRi_AOCPi_MASK(index) | ASRCDRi_AICPi_MASK(index) |
++ ASRCDRi_AOCDi_MASK(index) | ASRCDRi_AICDi_MASK(index),
++ ASRCDRi_AOCP(index, outdiv) | ASRCDRi_AICP(index, indiv));
++
++ /* Implement word_width configurations */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRMCR1(index),
++ ASRMCR1i_OW16_MASK | ASRMCR1i_IWD_MASK,
++ ASRMCR1i_OW16(config->output_word_width) |
++ ASRMCR1i_IWD(config->input_word_width));
++
++ /* Enable BUFFER STALL */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRMCR(index),
++ ASRMCRi_BUFSTALLi_MASK, ASRMCRi_BUFSTALLi);
++
++ /* Set default thresholds for input and output FIFO */
++ fsl_asrc_set_watermarks(pair, ASRC_INPUTFIFO_THRESHOLD,
++ ASRC_INPUTFIFO_THRESHOLD);
++
++ /* Configure the followings only for Ideal Ratio mode */
++ if (!ideal)
++ return 0;
++
++ /* Clear ASTSx bit to use Ideal Ratio mode */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_ATSi_MASK(index), 0);
++
++ /* Enable Ideal Ratio mode */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_IDRi_MASK(index) | ASRCTR_USRi_MASK(index),
++ ASRCTR_IDR(index) | ASRCTR_USR(index));
++
++ /* Apply configurations for pre- and post-processing */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
++ ASRCFG_PREMODi_MASK(index) | ASRCFG_POSTMODi_MASK(index),
++ ASRCFG_PREMOD(index, process_option[in][out][0]) |
++ ASRCFG_POSTMOD(index, process_option[in][out][1]));
++
++ return fsl_asrc_set_ideal_ratio(pair, inrate, outrate);
++}
++
++/**
++ * Start the assigned ASRC pair
++ *
++ * It enables the assigned pair and makes it stopped at the stall level.
++ */
++static void fsl_asrc_start_pair(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ int reg, retry = 10, i;
++
++ /* Enable the current pair */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEi_MASK(index), ASRCTR_ASRCE(index));
++
++ /* Wait for status of initialization */
++ do {
++ udelay(5);
++ regmap_read(asrc_priv->regmap, REG_ASRCFG, &reg);
++ reg &= ASRCFG_INIRQi_MASK(index);
++ } while (!reg && --retry);
++
++ /* Make the input fifo to ASRC STALL level */
++ regmap_read(asrc_priv->regmap, REG_ASRCNCR, &reg);
++ for (i = 0; i < pair->channels * 4; i++)
++ regmap_write(asrc_priv->regmap, REG_ASRDI(index), 0);
++
++ /* Enable overload interrupt */
++ regmap_write(asrc_priv->regmap, REG_ASRIER, ASRIER_AOLIE);
++}
++
++/**
++ * Stop the assigned ASRC pair
++ */
++static void fsl_asrc_stop_pair(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++
++ /* Stop the current pair */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEi_MASK(index), 0);
++}
++
++/**
++ * Get DMA channel according to the pair and direction.
++ */
++struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ char name[4];
++
++ sprintf(name, "%cx%c", dir == IN ? 'r' : 't', index + 'a');
++
++ return dma_request_slave_channel(&asrc_priv->pdev->dev, name);
++}
++EXPORT_SYMBOL_GPL(fsl_asrc_get_dma_channel);
++
++static int fsl_asrc_dai_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params,
++ struct snd_soc_dai *dai)
++{
++ struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
++ int width = snd_pcm_format_width(params_format(params));
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++ unsigned int channels = params_channels(params);
++ unsigned int rate = params_rate(params);
++ struct asrc_config config;
++ int word_width, ret;
++
++ ret = fsl_asrc_request_pair(channels, pair);
++ if (ret) {
++ dev_err(dai->dev, "fail to request asrc pair\n");
++ return ret;
++ }
++
++ pair->config = &config;
++
++ if (width == 16)
++ width = ASRC_WIDTH_16_BIT;
++ else
++ width = ASRC_WIDTH_24_BIT;
++
++ if (asrc_priv->asrc_width == 16)
++ word_width = ASRC_WIDTH_16_BIT;
++ else
++ word_width = ASRC_WIDTH_24_BIT;
++
++ config.pair = pair->index;
++ config.channel_num = channels;
++ config.inclk = INCLK_NONE;
++ config.outclk = OUTCLK_ASRCK1_CLK;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++ config.input_word_width = width;
++ config.output_word_width = word_width;
++ config.input_sample_rate = rate;
++ config.output_sample_rate = asrc_priv->asrc_rate;
++
++ ret = fsl_asrc_config_pair(pair, false, true);
++ if (ret) {
++ dev_err(dai->dev, "fail to config asrc pair\n");
++ return ret;
++ }
++
++ } else {
++ config.input_word_width = word_width;
++ config.output_word_width = width;
++ config.input_sample_rate = asrc_priv->asrc_rate;
++ config.output_sample_rate = rate;
++
++ ret = fsl_asrc_config_pair(pair, true, false);
++ if (ret) {
++ dev_err(dai->dev, "fail to config asrc pair\n");
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static int fsl_asrc_dai_hw_free(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++
++ if (pair)
++ fsl_asrc_release_pair(pair);
++
++ return 0;
++}
++
++static int fsl_asrc_dai_trigger(struct snd_pcm_substream *substream, int cmd,
++ struct snd_soc_dai *dai)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ fsl_asrc_start_pair(pair);
++ /* Output enough data to content the DMA burstsize of BE */
++ mdelay(1);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ fsl_asrc_stop_pair(pair);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int fsl_asrc_dai_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(cpu_dai);
++
++ asrc_priv->substream[substream->stream] = substream;
++ return 0;
++}
++
++static void fsl_asrc_dai_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(cpu_dai);
++
++ asrc_priv->substream[substream->stream] = NULL;
++}
++
++static struct snd_soc_dai_ops fsl_asrc_dai_ops = {
++ .startup = fsl_asrc_dai_startup,
++ .shutdown = fsl_asrc_dai_shutdown,
++ .hw_params = fsl_asrc_dai_hw_params,
++ .hw_free = fsl_asrc_dai_hw_free,
++ .trigger = fsl_asrc_dai_trigger,
++};
++
++static int fsl_asrc_dai_probe(struct snd_soc_dai *dai)
++{
++ struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(dai);
++
++ snd_soc_dai_init_dma_data(dai, &asrc_priv->dma_params_tx,
++ &asrc_priv->dma_params_rx);
++
++ return 0;
++}
++
++#define FSL_ASRC_RATES SNDRV_PCM_RATE_8000_192000
++#define FSL_ASRC_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
++ SNDRV_PCM_FMTBIT_S16_LE | \
++ SNDRV_PCM_FMTBIT_S20_3LE)
++
++static struct snd_soc_dai_driver fsl_asrc_dai = {
++ .probe = fsl_asrc_dai_probe,
++ .playback = {
++ .stream_name = "ASRC-Playback",
++ .channels_min = 1,
++ .channels_max = 10,
++ .rates = FSL_ASRC_RATES,
++ .formats = FSL_ASRC_FORMATS,
++ },
++ .capture = {
++ .stream_name = "ASRC-Capture",
++ .channels_min = 1,
++ .channels_max = 10,
++ .rates = FSL_ASRC_RATES,
++ .formats = FSL_ASRC_FORMATS,
++ },
++ .ops = &fsl_asrc_dai_ops,
++};
++
++static const struct snd_soc_component_driver fsl_asrc_component = {
++ .name = "fsl-asrc-dai",
++};
++
++static bool fsl_asrc_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRCTR:
++ case REG_ASRIER:
++ case REG_ASRCNCR:
++ case REG_ASRCFG:
++ case REG_ASRCSR:
++ case REG_ASRCDR1:
++ case REG_ASRCDR2:
++ case REG_ASRSTR:
++ case REG_ASRPM1:
++ case REG_ASRPM2:
++ case REG_ASRPM3:
++ case REG_ASRPM4:
++ case REG_ASRPM5:
++ case REG_ASRTFR1:
++ case REG_ASRCCR:
++ case REG_ASRDOA:
++ case REG_ASRDOB:
++ case REG_ASRDOC:
++ case REG_ASRIDRHA:
++ case REG_ASRIDRLA:
++ case REG_ASRIDRHB:
++ case REG_ASRIDRLB:
++ case REG_ASRIDRHC:
++ case REG_ASRIDRLC:
++ case REG_ASR76K:
++ case REG_ASR56K:
++ case REG_ASRMCRA:
++ case REG_ASRFSTA:
++ case REG_ASRMCRB:
++ case REG_ASRFSTB:
++ case REG_ASRMCRC:
++ case REG_ASRFSTC:
++ case REG_ASRMCR1A:
++ case REG_ASRMCR1B:
++ case REG_ASRMCR1C:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool fsl_asrc_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRSTR:
++ case REG_ASRDIA:
++ case REG_ASRDIB:
++ case REG_ASRDIC:
++ case REG_ASRDOA:
++ case REG_ASRDOB:
++ case REG_ASRDOC:
++ case REG_ASRFSTA:
++ case REG_ASRFSTB:
++ case REG_ASRFSTC:
++ case REG_ASRCFG:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ASRCTR:
++ case REG_ASRIER:
++ case REG_ASRCNCR:
++ case REG_ASRCFG:
++ case REG_ASRCSR:
++ case REG_ASRCDR1:
++ case REG_ASRCDR2:
++ case REG_ASRSTR:
++ case REG_ASRPM1:
++ case REG_ASRPM2:
++ case REG_ASRPM3:
++ case REG_ASRPM4:
++ case REG_ASRPM5:
++ case REG_ASRTFR1:
++ case REG_ASRCCR:
++ case REG_ASRDIA:
++ case REG_ASRDIB:
++ case REG_ASRDIC:
++ case REG_ASRIDRHA:
++ case REG_ASRIDRLA:
++ case REG_ASRIDRHB:
++ case REG_ASRIDRLB:
++ case REG_ASRIDRHC:
++ case REG_ASRIDRLC:
++ case REG_ASR76K:
++ case REG_ASR56K:
++ case REG_ASRMCRA:
++ case REG_ASRMCRB:
++ case REG_ASRMCRC:
++ case REG_ASRMCR1A:
++ case REG_ASRMCR1B:
++ case REG_ASRMCR1C:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static struct regmap_config fsl_asrc_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++
++ .max_register = REG_ASRMCR1C,
++ .readable_reg = fsl_asrc_readable_reg,
++ .volatile_reg = fsl_asrc_volatile_reg,
++ .writeable_reg = fsl_asrc_writeable_reg,
++ .cache_type = REGCACHE_RBTREE,
++};
++
++#include "fsl_asrc_m2m.c"
++
++static bool fsl_asrc_check_xrun(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_dmaengine_dai_dma_data *dma_params_be = NULL;
++ struct snd_pcm_substream *be_substream;
++ struct snd_soc_dpcm *dpcm;
++ int ret = 0;
++
++ /* find the be for this fe stream */
++ list_for_each_entry(dpcm, &rtd->dpcm[substream->stream].be_clients, list_be) {
++ struct snd_soc_pcm_runtime *be = dpcm->be;
++ struct snd_soc_dai *dai = be->cpu_dai;
++
++ if (dpcm->fe != rtd)
++ continue;
++
++ be_substream = snd_soc_dpcm_get_substream(be, substream->stream);
++ dma_params_be = snd_soc_dai_get_dma_data(dai, be_substream);
++ if (dma_params_be->check_xrun && dma_params_be->check_xrun(be_substream))
++ ret = 1;
++ }
++
++ return ret;
++}
++
++static int stop_lock_stream(struct snd_pcm_substream *substream)
++{
++ if (substream) {
++ snd_pcm_stream_lock_irq(substream);
++ if (substream->runtime->status->state == SNDRV_PCM_STATE_RUNNING)
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP);
++ }
++ return 0;
++}
++
++static int start_unlock_stream(struct snd_pcm_substream *substream)
++{
++ if (substream) {
++ if (substream->runtime->status->state == SNDRV_PCM_STATE_RUNNING)
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
++ snd_pcm_stream_unlock_irq(substream);
++ }
++ return 0;
++}
++
++static void fsl_asrc_reset(struct snd_pcm_substream *substream, bool stop)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct fsl_asrc *asrc_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ struct snd_dmaengine_dai_dma_data *dma_params_be = NULL;
++ struct snd_soc_dpcm *dpcm;
++ struct snd_pcm_substream *be_substream;
++
++ if (stop) {
++ stop_lock_stream(asrc_priv->substream[0]);
++ stop_lock_stream(asrc_priv->substream[1]);
++ }
++
++ /* find the be for this fe stream */
++ list_for_each_entry(dpcm, &rtd->dpcm[substream->stream].be_clients, list_be) {
++ struct snd_soc_pcm_runtime *be = dpcm->be;
++ struct snd_soc_dai *dai = be->cpu_dai;
++
++ if (dpcm->fe != rtd)
++ continue;
++
++ be_substream = snd_soc_dpcm_get_substream(be, substream->stream);
++ dma_params_be = snd_soc_dai_get_dma_data(dai, be_substream);
++ dma_params_be->device_reset(be_substream, 0);
++ break;
++ }
++
++ if (stop) {
++ start_unlock_stream(asrc_priv->substream[1]);
++ start_unlock_stream(asrc_priv->substream[0]);
++ }
++}
++
++/**
++ * Initialize ASRC registers with a default configurations
++ */
++static int fsl_asrc_init(struct fsl_asrc *asrc_priv)
++{
++ /* Halt ASRC internal FP when input FIFO needs data for pair A, B, C */
++ regmap_write(asrc_priv->regmap, REG_ASRCTR, ASRCTR_ASRCEN);
++
++ /* Disable interrupt by default */
++ regmap_write(asrc_priv->regmap, REG_ASRIER, 0x0);
++
++ /* Apply recommended settings for parameters from Reference Manual */
++ regmap_write(asrc_priv->regmap, REG_ASRPM1, 0x7fffff);
++ regmap_write(asrc_priv->regmap, REG_ASRPM2, 0x255555);
++ regmap_write(asrc_priv->regmap, REG_ASRPM3, 0xff7280);
++ regmap_write(asrc_priv->regmap, REG_ASRPM4, 0xff7280);
++ regmap_write(asrc_priv->regmap, REG_ASRPM5, 0xff7280);
++
++ /* Base address for task queue FIFO. Set to 0x7C */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRTFR1,
++ ASRTFR1_TF_BASE_MASK, ASRTFR1_TF_BASE(0xfc));
++
++ /* Set the processing clock for 76KHz to 133M */
++ regmap_write(asrc_priv->regmap, REG_ASR76K, 0x06D6);
++
++ /* Set the processing clock for 56KHz to 133M */
++ return regmap_write(asrc_priv->regmap, REG_ASR56K, 0x0947);
++}
++
++/**
++ * Interrupt handler for ASRC
++ */
++static irqreturn_t fsl_asrc_isr(int irq, void *dev_id)
++{
++ struct fsl_asrc *asrc_priv = (struct fsl_asrc *)dev_id;
++ struct device *dev = &asrc_priv->pdev->dev;
++ enum asrc_pair_index index;
++ u32 status;
++
++ regmap_read(asrc_priv->regmap, REG_ASRSTR, &status);
++
++ /* Clean overload error */
++ regmap_write(asrc_priv->regmap, REG_ASRSTR, ASRSTR_AOLE);
++
++ /*
++ * We here use dev_dbg() for all exceptions because ASRC itself does
++ * not care if FIFO overflowed or underrun while a warning in the
++ * interrupt would result a ridged conversion.
++ */
++ for (index = ASRC_PAIR_A; index < ASRC_PAIR_MAX_NUM; index++) {
++ if (!asrc_priv->pair[index])
++ continue;
++
++ if (status & ASRSTR_ATQOL) {
++ asrc_priv->pair[index]->error |= ASRC_TASK_Q_OVERLOAD;
++ dev_dbg(dev, "ASRC Task Queue FIFO overload\n");
++ }
++
++ if (status & ASRSTR_AOOL(index)) {
++ asrc_priv->pair[index]->error |= ASRC_OUTPUT_TASK_OVERLOAD;
++ pair_dbg("Output Task Overload\n");
++ }
++
++ if (status & ASRSTR_AIOL(index)) {
++ asrc_priv->pair[index]->error |= ASRC_INPUT_TASK_OVERLOAD;
++ pair_dbg("Input Task Overload\n");
++ }
++
++ if (status & ASRSTR_AODO(index)) {
++ asrc_priv->pair[index]->error |= ASRC_OUTPUT_BUFFER_OVERFLOW;
++ pair_dbg("Output Data Buffer has overflowed\n");
++ }
++
++ if (status & ASRSTR_AIDU(index)) {
++ asrc_priv->pair[index]->error |= ASRC_INPUT_BUFFER_UNDERRUN;
++ pair_dbg("Input Data Buffer has underflowed\n");
++ }
++ }
++
++ return IRQ_HANDLED;
++}
++
++static int fsl_asrc_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct fsl_asrc *asrc_priv;
++ struct resource *res;
++ void __iomem *regs;
++ int irq, ret, i;
++ char tmp[16];
++
++ asrc_priv = devm_kzalloc(&pdev->dev, sizeof(*asrc_priv), GFP_KERNEL);
++ if (!asrc_priv)
++ return -ENOMEM;
++
++ asrc_priv->pdev = pdev;
++ strcpy(asrc_priv->name, np->name);
++
++ /* Get the addresses and IRQ */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ regs = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(regs))
++ return PTR_ERR(regs);
++
++ asrc_priv->paddr = res->start;
++
++ /* Register regmap and let it prepare core clock */
++ if (of_property_read_bool(np, "big-endian"))
++ fsl_asrc_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
++
++ asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs,
++ &fsl_asrc_regmap_config);
++ if (IS_ERR(asrc_priv->regmap)) {
++ dev_err(&pdev->dev, "failed to init regmap\n");
++ return PTR_ERR(asrc_priv->regmap);
++ }
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
++ return irq;
++ }
++
++ ret = devm_request_irq(&pdev->dev, irq, fsl_asrc_isr, 0,
++ asrc_priv->name, asrc_priv);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to claim irq %u: %d\n", irq, ret);
++ return ret;
++ }
++
++ asrc_priv->mem_clk = devm_clk_get(&pdev->dev, "mem");
++ if (IS_ERR(asrc_priv->mem_clk)) {
++ dev_err(&pdev->dev, "failed to get mem clock\n");
++ return PTR_ERR(asrc_priv->mem_clk);
++ }
++
++ asrc_priv->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
++ if (IS_ERR(asrc_priv->ipg_clk)) {
++ dev_err(&pdev->dev, "failed to get ipg clock\n");
++ return PTR_ERR(asrc_priv->ipg_clk);
++ }
++
++ asrc_priv->dma_clk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(asrc_priv->dma_clk)) {
++ dev_err(&pdev->dev, "failed to get dma script clock\n");
++ return PTR_ERR(asrc_priv->dma_clk);
++ }
++
++ for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
++ sprintf(tmp, "asrck_%x", i);
++ asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
++ if (IS_ERR(asrc_priv->asrck_clk[i])) {
++ dev_err(&pdev->dev, "failed to get %s clock\n", tmp);
++ return PTR_ERR(asrc_priv->asrck_clk[i]);
++ }
++ }
++
++ if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx35-asrc")) {
++ asrc_priv->channel_bits = 3;
++ clk_map[IN] = input_clk_map_imx35;
++ clk_map[OUT] = output_clk_map_imx35;
++ } else {
++ asrc_priv->channel_bits = 4;
++ clk_map[IN] = input_clk_map_imx53;
++ clk_map[OUT] = output_clk_map_imx53;
++ }
++
++ ret = fsl_asrc_init(asrc_priv);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to init asrc %d\n", ret);
++ return -EINVAL;
++ }
++
++ asrc_priv->channel_avail = 10;
++
++ ret = of_property_read_u32(np, "fsl,asrc-rate",
++ &asrc_priv->asrc_rate);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get output rate\n");
++ return -EINVAL;
++ }
++
++ ret = of_property_read_u32(np, "fsl,asrc-width",
++ &asrc_priv->asrc_width);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get output width\n");
++ return -EINVAL;
++ }
++
++ asrc_priv->dma_params_tx.check_xrun = fsl_asrc_check_xrun;
++ asrc_priv->dma_params_rx.check_xrun = fsl_asrc_check_xrun;
++ asrc_priv->dma_params_tx.device_reset = fsl_asrc_reset;
++ asrc_priv->dma_params_rx.device_reset = fsl_asrc_reset;
++
++ if (asrc_priv->asrc_width != 16 && asrc_priv->asrc_width != 24) {
++ dev_warn(&pdev->dev, "unsupported width, switching to 24bit\n");
++ asrc_priv->asrc_width = 24;
++ }
++
++ platform_set_drvdata(pdev, asrc_priv);
++ pm_runtime_enable(&pdev->dev);
++ spin_lock_init(&asrc_priv->lock);
++
++ ret = devm_snd_soc_register_component(&pdev->dev, &fsl_asrc_component,
++ &fsl_asrc_dai, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register ASoC DAI\n");
++ return ret;
++ }
++
++ ret = devm_snd_soc_register_platform(&pdev->dev, &fsl_asrc_platform);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register ASoC platform\n");
++ return ret;
++ }
++
++ ret = fsl_asrc_m2m_init(asrc_priv);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to init m2m device %d\n", ret);
++ return ret;
++ }
++
++ dev_info(&pdev->dev, "driver registered\n");
++
++ return 0;
++}
++
++#ifdef CONFIG_PM_RUNTIME
++static int fsl_asrc_runtime_resume(struct device *dev)
++{
++ struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
++ int i;
++
++ clk_prepare_enable(asrc_priv->mem_clk);
++ clk_prepare_enable(asrc_priv->ipg_clk);
++ clk_prepare_enable(asrc_priv->dma_clk);
++ for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
++ clk_prepare_enable(asrc_priv->asrck_clk[i]);
++
++ return 0;
++}
++
++static int fsl_asrc_runtime_suspend(struct device *dev)
++{
++ struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
++ int i;
++
++ for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
++ clk_disable_unprepare(asrc_priv->asrck_clk[i]);
++ clk_disable_unprepare(asrc_priv->dma_clk);
++ clk_disable_unprepare(asrc_priv->ipg_clk);
++ clk_disable_unprepare(asrc_priv->mem_clk);
++
++ return 0;
++}
++#endif /* CONFIG_PM_RUNTIME */
++
++#ifdef CONFIG_PM_SLEEP
++static int fsl_asrc_suspend(struct device *dev)
++{
++ struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
++
++ fsl_asrc_m2m_suspend(asrc_priv);
++
++ regmap_read(asrc_priv->regmap, REG_ASRCFG,
++ &asrc_priv->regcache_cfg);
++
++ regcache_cache_only(asrc_priv->regmap, true);
++ regcache_mark_dirty(asrc_priv->regmap);
++
++ return 0;
++}
++
++static int fsl_asrc_resume(struct device *dev)
++{
++ struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
++ u32 asrctr;
++
++ /* Stop all pairs provisionally */
++ regmap_read(asrc_priv->regmap, REG_ASRCTR, &asrctr);
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEi_ALL_MASK, 0);
++
++ /* Restore all registers */
++ regcache_cache_only(asrc_priv->regmap, false);
++ regcache_sync(asrc_priv->regmap);
++
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCFG,
++ 0x1FFFC0, asrc_priv->regcache_cfg);
++
++ /* Restart enabled pairs */
++ regmap_update_bits(asrc_priv->regmap, REG_ASRCTR,
++ ASRCTR_ASRCEi_ALL_MASK, asrctr);
++
++ return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops fsl_asrc_pm = {
++ SET_RUNTIME_PM_OPS(fsl_asrc_runtime_suspend, fsl_asrc_runtime_resume, NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(fsl_asrc_suspend, fsl_asrc_resume)
++};
++
++static const struct of_device_id fsl_asrc_ids[] = {
++ { .compatible = "fsl,imx35-asrc", },
++ { .compatible = "fsl,imx53-asrc", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, fsl_asrc_ids);
++
++static struct platform_driver fsl_asrc_driver = {
++ .probe = fsl_asrc_probe,
++ .remove = fsl_asrc_m2m_remove,
++ .driver = {
++ .name = "fsl-asrc",
++ .of_match_table = fsl_asrc_ids,
++ .pm = &fsl_asrc_pm,
++ },
++};
++module_platform_driver(fsl_asrc_driver);
++
++MODULE_DESCRIPTION("Freescale ASRC ASoC driver");
++MODULE_AUTHOR("Nicolin Chen <nicoleotsuka@gmail.com>");
++MODULE_ALIAS("platform:fsl-asrc");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_asrc_dma.c linux-3.14.72/sound/soc/fsl/fsl_asrc_dma.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_asrc_dma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/fsl_asrc_dma.c 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,398 @@
++/*
++ * Freescale ASRC ALSA SoC Platform (DMA) driver
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * Author: Nicolin Chen <nicoleotsuka@gmail.com>
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/dma-mapping.h>
++#include <linux/module.h>
++#include <linux/platform_data/dma-imx.h>
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm_params.h>
++
++#include "fsl_asrc.h"
++
++#define FSL_ASRC_DMABUF_SIZE (256 * 1024)
++
++static struct snd_pcm_hardware snd_imx_hardware = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID |
++ SNDRV_PCM_INFO_PAUSE |
++ SNDRV_PCM_INFO_RESUME,
++ .buffer_bytes_max = FSL_ASRC_DMABUF_SIZE,
++ .period_bytes_min = 128,
++ .period_bytes_max = 65535, /* Limited by SDMA engine */
++ .periods_min = 2,
++ .periods_max = 255,
++ .fifo_size = 0,
++};
++
++static bool filter(struct dma_chan *chan, void *param)
++{
++ if (!imx_dma_is_general_purpose(chan))
++ return false;
++
++ chan->private = param;
++
++ return true;
++}
++
++static void fsl_asrc_dma_complete(void *arg)
++{
++ struct snd_pcm_substream *substream = arg;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_dmaengine_dai_dma_data *dma_data;
++
++ pair->pos += snd_pcm_lib_period_bytes(substream);
++ if (pair->pos >= snd_pcm_lib_buffer_bytes(substream))
++ pair->pos = 0;
++
++ snd_pcm_period_elapsed(substream);
++
++ dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
++ if (dma_data->check_xrun && dma_data->check_xrun(substream))
++ dma_data->device_reset(substream, 1);
++
++}
++
++static int fsl_asrc_dma_prepare_and_submit(struct snd_pcm_substream *substream)
++{
++ u8 dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? OUT : IN;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++ unsigned long flags = DMA_CTRL_ACK;
++
++ /* Prepare and submit Front-End DMA channel */
++ if (!substream->runtime->no_period_wakeup)
++ flags |= DMA_PREP_INTERRUPT;
++
++ pair->pos = 0;
++ pair->desc[!dir] = dmaengine_prep_dma_cyclic(
++ pair->dma_chan[!dir], runtime->dma_addr,
++ snd_pcm_lib_buffer_bytes(substream),
++ snd_pcm_lib_period_bytes(substream),
++ dir == OUT ? DMA_TO_DEVICE : DMA_FROM_DEVICE, flags);
++ if (!pair->desc[!dir]) {
++ dev_err(dev, "failed to prepare slave DMA for Front-End\n");
++ return -ENOMEM;
++ }
++
++ pair->desc[!dir]->callback = fsl_asrc_dma_complete;
++ pair->desc[!dir]->callback_param = substream;
++
++ dmaengine_submit(pair->desc[!dir]);
++
++ /* Prepare and submit Back-End DMA channel */
++ pair->desc[dir] = dmaengine_prep_dma_cyclic(
++ pair->dma_chan[dir], 0xffff, 64, 64, DMA_DEV_TO_DEV, 0);
++ if (!pair->desc[dir]) {
++ dev_err(dev, "failed to prepare slave DMA for Back-End\n");
++ return -ENOMEM;
++ }
++
++ dmaengine_submit(pair->desc[dir]);
++
++ return 0;
++}
++
++static int fsl_asrc_dma_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++ int ret;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ ret = fsl_asrc_dma_prepare_and_submit(substream);
++ if (ret)
++ return ret;
++ dma_async_issue_pending(pair->dma_chan[IN]);
++ dma_async_issue_pending(pair->dma_chan[OUT]);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ dmaengine_terminate_all(pair->dma_chan[OUT]);
++ dmaengine_terminate_all(pair->dma_chan[IN]);
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int fsl_asrc_dma_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ enum dma_slave_buswidth buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++ struct snd_dmaengine_dai_dma_data *dma_params_fe = NULL;
++ struct snd_dmaengine_dai_dma_data *dma_params_be = NULL;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct dma_slave_config config_fe, config_be;
++ enum asrc_pair_index index = pair->index;
++ struct device *dev = rtd->platform->dev;
++ int stream = substream->stream;
++ struct imx_dma_data *tmp_data;
++ struct snd_soc_dpcm *dpcm;
++ struct dma_chan *tmp_chan;
++ struct device *dev_be;
++ u8 dir = tx ? OUT : IN;
++ dma_cap_mask_t mask;
++ int ret;
++
++ /* Fetch the Back-End dma_data from DPCM */
++ list_for_each_entry(dpcm, &rtd->dpcm[stream].be_clients, list_be) {
++ struct snd_soc_pcm_runtime *be = dpcm->be;
++ struct snd_pcm_substream *substream_be;
++ struct snd_soc_dai *dai = be->cpu_dai;
++
++ if (dpcm->fe != rtd)
++ continue;
++
++ substream_be = snd_soc_dpcm_get_substream(be, stream);
++ dma_params_be = snd_soc_dai_get_dma_data(dai, substream_be);
++ dev_be = dai->dev;
++ break;
++ }
++
++ if (!dma_params_be) {
++ dev_err(dev, "failed to get the substream of Back-End\n");
++ return -EINVAL;
++ }
++
++ /* Override dma_data of the Front-End and config its dmaengine */
++ dma_params_fe = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
++ dma_params_fe->addr = asrc_priv->paddr + REG_ASRDx(!dir, index);
++ dma_params_fe->maxburst = dma_params_be->maxburst;
++
++ pair->dma_chan[!dir] = fsl_asrc_get_dma_channel(pair, !dir);
++ if (!pair->dma_chan[!dir]) {
++ dev_err(dev, "failed to request DMA channel\n");
++ return -EINVAL;
++ }
++
++ memset(&config_fe, 0, sizeof(config_fe));
++ ret = snd_dmaengine_pcm_prepare_slave_config(substream, params, &config_fe);
++ if (ret) {
++ dev_err(dev, "failed to prepare DMA config for Front-End\n");
++ return ret;
++ }
++
++ ret = dmaengine_slave_config(pair->dma_chan[!dir], &config_fe);
++ if (ret) {
++ dev_err(dev, "failed to config DMA channel for Front-End\n");
++ return ret;
++ }
++
++ /* Request and config DMA channel for Back-End */
++ dma_cap_zero(mask);
++ dma_cap_set(DMA_SLAVE, mask);
++ dma_cap_set(DMA_CYCLIC, mask);
++
++ /* Get DMA request of Back-End */
++ tmp_chan = dma_request_slave_channel(dev_be, tx ? "tx" : "rx");
++ tmp_data = tmp_chan->private;
++ pair->dma_data.dma_request = tmp_data->dma_request;
++ dma_release_channel(tmp_chan);
++
++ /* Get DMA request of Front-End */
++ tmp_chan = fsl_asrc_get_dma_channel(pair, dir);
++ tmp_data = tmp_chan->private;
++ pair->dma_data.dma_request2 = tmp_data->dma_request;
++ pair->dma_data.peripheral_type = tmp_data->peripheral_type;
++ pair->dma_data.priority = tmp_data->priority;
++ dma_release_channel(tmp_chan);
++
++ pair->dma_chan[dir] = dma_request_channel(mask, filter, &pair->dma_data);
++ if (!pair->dma_chan[dir]) {
++ dev_err(dev, "failed to request DMA channel for Back-End\n");
++ return -EINVAL;
++ }
++
++ if (asrc_priv->asrc_width == 16)
++ buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ else
++ buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++
++ config_be.direction = DMA_DEV_TO_DEV;
++ config_be.src_addr_width = buswidth;
++ config_be.src_maxburst = dma_params_be->maxburst;
++ config_be.dst_addr_width = buswidth;
++ config_be.dst_maxburst = dma_params_be->maxburst;
++
++ if (tx) {
++ config_be.src_addr = asrc_priv->paddr + REG_ASRDO(index);
++ config_be.dst_addr = dma_params_be->addr;
++ } else {
++ config_be.dst_addr = asrc_priv->paddr + REG_ASRDI(index);
++ config_be.src_addr = dma_params_be->addr;
++ }
++
++ ret = dmaengine_slave_config(pair->dma_chan[dir], &config_be);
++ if (ret) {
++ dev_err(dev, "failed to config DMA channel for Back-End\n");
++ return ret;
++ }
++
++ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
++
++ return 0;
++}
++
++static int fsl_asrc_dma_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++
++ snd_pcm_set_runtime_buffer(substream, NULL);
++
++ if (pair->dma_chan[IN])
++ dma_release_channel(pair->dma_chan[IN]);
++
++ if (pair->dma_chan[OUT])
++ dma_release_channel(pair->dma_chan[OUT]);
++
++ pair->dma_chan[IN] = NULL;
++ pair->dma_chan[OUT] = NULL;
++
++ return 0;
++}
++
++static int fsl_asrc_dma_startup(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct device *dev = rtd->platform->dev;
++ struct fsl_asrc *asrc_priv = dev_get_drvdata(dev);
++ struct fsl_asrc_pair *pair;
++
++ pair = kzalloc(sizeof(struct fsl_asrc_pair), GFP_KERNEL);
++ if (!pair) {
++ dev_err(dev, "failed to allocate pair\n");
++ return -ENOMEM;
++ }
++
++ pair->asrc_priv = asrc_priv;
++
++ runtime->private_data = pair;
++
++ snd_pcm_hw_constraint_integer(substream->runtime,
++ SNDRV_PCM_HW_PARAM_PERIODS);
++ snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
++
++ return 0;
++}
++
++static int fsl_asrc_dma_shutdown(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++ struct fsl_asrc *asrc_priv;
++
++ if (!pair)
++ return 0;
++
++ asrc_priv = pair->asrc_priv;
++
++ if (asrc_priv->pair[pair->index] == pair)
++ asrc_priv->pair[pair->index] = NULL;
++
++ kfree(pair);
++
++ return 0;
++}
++
++static snd_pcm_uframes_t fsl_asrc_dma_pcm_pointer(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct fsl_asrc_pair *pair = runtime->private_data;
++
++ return bytes_to_frames(substream->runtime, pair->pos);
++}
++
++static struct snd_pcm_ops fsl_asrc_dma_pcm_ops = {
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = fsl_asrc_dma_hw_params,
++ .hw_free = fsl_asrc_dma_hw_free,
++ .trigger = fsl_asrc_dma_trigger,
++ .open = fsl_asrc_dma_startup,
++ .close = fsl_asrc_dma_shutdown,
++ .pointer = fsl_asrc_dma_pcm_pointer,
++};
++
++static int fsl_asrc_dma_pcm_new(struct snd_soc_pcm_runtime *rtd)
++{
++ struct snd_card *card = rtd->card->snd_card;
++ struct snd_pcm_substream *substream;
++ struct snd_pcm *pcm = rtd->pcm;
++ int ret, i;
++
++ ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
++ if (ret) {
++ dev_err(card->dev, "failed to set DMA mask\n");
++ return ret;
++ }
++
++ for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_LAST; i++) {
++ substream = pcm->streams[i].substream;
++ if (!substream)
++ continue;
++
++ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
++ FSL_ASRC_DMABUF_SIZE, &substream->dma_buffer);
++ if (ret) {
++ dev_err(card->dev, "failed to allocate DMA buffer\n");
++ goto err;
++ }
++ }
++
++ return 0;
++
++err:
++ if (--i == 0 && pcm->streams[i].substream)
++ snd_dma_free_pages(&pcm->streams[i].substream->dma_buffer);
++
++ return ret;
++}
++
++static void fsl_asrc_dma_pcm_free(struct snd_pcm *pcm)
++{
++ struct snd_pcm_substream *substream;
++ int i;
++
++ for (i = SNDRV_PCM_STREAM_PLAYBACK; i <= SNDRV_PCM_STREAM_LAST; i++) {
++ substream = pcm->streams[i].substream;
++ if (!substream)
++ continue;
++
++ snd_dma_free_pages(&substream->dma_buffer);
++ substream->dma_buffer.area = NULL;
++ substream->dma_buffer.addr = 0;
++ }
++}
++
++struct snd_soc_platform_driver fsl_asrc_platform = {
++ .ops = &fsl_asrc_dma_pcm_ops,
++ .pcm_new = fsl_asrc_dma_pcm_new,
++ .pcm_free = fsl_asrc_dma_pcm_free,
++};
++EXPORT_SYMBOL_GPL(fsl_asrc_platform);
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_asrc.h linux-3.14.72/sound/soc/fsl/fsl_asrc.h
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_asrc.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/fsl_asrc.h 2016-06-19 22:11:55.521125834 +0200
+@@ -0,0 +1,374 @@
++/*
++ * fsl_asrc.h - Freescale ASRC ALSA SoC header file
++ *
++ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Author: Nicolin Chen <nicoleotsuka@gmail.com>
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#ifndef _FSL_ASRC_H
++#define _FSL_ASRC_H
++
++#include <uapi/linux/mxc_asrc.h>
++
++#define IN 0
++#define OUT 1
++
++#define ASRC_DMA_BUFFER_NUM 2
++#define ASRC_INPUTFIFO_THRESHOLD 32
++#define ASRC_OUTPUTFIFO_THRESHOLD 32
++#define ASRC_FIFO_THRESHOLD_MIN 0
++#define ASRC_FIFO_THRESHOLD_MAX 63
++#define ASRC_DMA_BUFFER_SIZE (1024 * 48 * 4)
++#define ASRC_MAX_BUFFER_SIZE (1024 * 48)
++#define ASRC_OUTPUT_LAST_SAMPLE_MAX 32
++#define ASRC_OUTPUT_LAST_SAMPLE 16
++
++#define IDEAL_RATIO_RATE 200000
++
++#define REG_ASRCTR 0x00
++#define REG_ASRIER 0x04
++#define REG_ASRCNCR 0x0C
++#define REG_ASRCFG 0x10
++#define REG_ASRCSR 0x14
++
++#define REG_ASRCDR1 0x18
++#define REG_ASRCDR2 0x1C
++#define REG_ASRCDR(i) ((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
++
++#define REG_ASRSTR 0x20
++#define REG_ASRRA 0x24
++#define REG_ASRRB 0x28
++#define REG_ASRRC 0x2C
++#define REG_ASRPM1 0x40
++#define REG_ASRPM2 0x44
++#define REG_ASRPM3 0x48
++#define REG_ASRPM4 0x4C
++#define REG_ASRPM5 0x50
++#define REG_ASRTFR1 0x54
++#define REG_ASRCCR 0x5C
++
++#define REG_ASRDIA 0x60
++#define REG_ASRDOA 0x64
++#define REG_ASRDIB 0x68
++#define REG_ASRDOB 0x6C
++#define REG_ASRDIC 0x70
++#define REG_ASRDOC 0x74
++#define REG_ASRDI(i) (REG_ASRDIA + (i << 3))
++#define REG_ASRDO(i) (REG_ASRDOA + (i << 3))
++#define REG_ASRDx(x, i) (x == IN ? REG_ASRDI(i) : REG_ASRDO(i))
++
++#define REG_ASRIDRHA 0x80
++#define REG_ASRIDRLA 0x84
++#define REG_ASRIDRHB 0x88
++#define REG_ASRIDRLB 0x8C
++#define REG_ASRIDRHC 0x90
++#define REG_ASRIDRLC 0x94
++#define REG_ASRIDRH(i) (REG_ASRIDRHA + (i << 3))
++#define REG_ASRIDRL(i) (REG_ASRIDRLA + (i << 3))
++
++#define REG_ASR76K 0x98
++#define REG_ASR56K 0x9C
++
++#define REG_ASRMCRA 0xA0
++#define REG_ASRFSTA 0xA4
++#define REG_ASRMCRB 0xA8
++#define REG_ASRFSTB 0xAC
++#define REG_ASRMCRC 0xB0
++#define REG_ASRFSTC 0xB4
++#define REG_ASRMCR(i) (REG_ASRMCRA + (i << 3))
++#define REG_ASRFST(i) (REG_ASRFSTA + (i << 3))
++
++#define REG_ASRMCR1A 0xC0
++#define REG_ASRMCR1B 0xC4
++#define REG_ASRMCR1C 0xC8
++#define REG_ASRMCR1(i) (REG_ASRMCR1A + (i << 2))
++
++
++/* REG0 0x00 REG_ASRCTR */
++#define ASRCTR_ATSi_SHIFT(i) (20 + i)
++#define ASRCTR_ATSi_MASK(i) (1 << ASRCTR_ATSi_SHIFT(i))
++#define ASRCTR_ATS(i) (1 << ASRCTR_ATSi_SHIFT(i))
++#define ASRCTR_USRi_SHIFT(i) (14 + (i << 1))
++#define ASRCTR_USRi_MASK(i) (1 << ASRCTR_USRi_SHIFT(i))
++#define ASRCTR_USR(i) (1 << ASRCTR_USRi_SHIFT(i))
++#define ASRCTR_IDRi_SHIFT(i) (13 + (i << 1))
++#define ASRCTR_IDRi_MASK(i) (1 << ASRCTR_IDRi_SHIFT(i))
++#define ASRCTR_IDR(i) (1 << ASRCTR_IDRi_SHIFT(i))
++#define ASRCTR_SRST_SHIFT 4
++#define ASRCTR_SRST_MASK (1 << ASRCTR_SRST_SHIFT)
++#define ASRCTR_SRST (1 << ASRCTR_SRST_SHIFT)
++#define ASRCTR_ASRCEi_SHIFT(i) (1 + i)
++#define ASRCTR_ASRCEi_MASK(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
++#define ASRCTR_ASRCE(i) (1 << ASRCTR_ASRCEi_SHIFT(i))
++#define ASRCTR_ASRCEi_ALL_MASK (0x7 << ASRCTR_ASRCEi_SHIFT(0))
++#define ASRCTR_ASRCEN_SHIFT 0
++#define ASRCTR_ASRCEN_MASK (1 << ASRCTR_ASRCEN_SHIFT)
++#define ASRCTR_ASRCEN (1 << ASRCTR_ASRCEN_SHIFT)
++
++/* REG1 0x04 REG_ASRIER */
++#define ASRIER_AFPWE_SHIFT 7
++#define ASRIER_AFPWE_MASK (1 << ASRIER_AFPWE_SHIFT)
++#define ASRIER_AFPWE (1 << ASRIER_AFPWE_SHIFT)
++#define ASRIER_AOLIE_SHIFT 6
++#define ASRIER_AOLIE_MASK (1 << ASRIER_AOLIE_SHIFT)
++#define ASRIER_AOLIE (1 << ASRIER_AOLIE_SHIFT)
++#define ASRIER_ADOEi_SHIFT(i) (3 + i)
++#define ASRIER_ADOEi_MASK(i) (1 << ASRIER_ADOEi_SHIFT(i))
++#define ASRIER_ADOE(i) (1 << ASRIER_ADOEi_SHIFT(i))
++#define ASRIER_ADIEi_SHIFT(i) (0 + i)
++#define ASRIER_ADIEi_MASK(i) (1 << ASRIER_ADIEi_SHIFT(i))
++#define ASRIER_ADIE(i) (1 << ASRIER_ADIEi_SHIFT(i))
++
++/* REG2 0x0C REG_ASRCNCR */
++#define ASRCNCR_ANCi_SHIFT(i, b) (b * i)
++#define ASRCNCR_ANCi_MASK(i, b) (((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
++#define ASRCNCR_ANCi(i, v, b) ((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
++
++/* REG3 0x10 REG_ASRCFG */
++#define ASRCFG_INIRQi_SHIFT(i) (21 + i)
++#define ASRCFG_INIRQi_MASK(i) (1 << ASRCFG_INIRQi_SHIFT(i))
++#define ASRCFG_INIRQi (1 << ASRCFG_INIRQi_SHIFT(i))
++#define ASRCFG_NDPRi_SHIFT(i) (18 + i)
++#define ASRCFG_NDPRi_MASK(i) (1 << ASRCFG_NDPRi_SHIFT(i))
++#define ASRCFG_NDPRi (1 << ASRCFG_NDPRi_SHIFT(i))
++#define ASRCFG_POSTMODi_SHIFT(i) (8 + (i << 2))
++#define ASRCFG_POSTMODi_WIDTH 2
++#define ASRCFG_POSTMODi_MASK(i) (((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
++#define ASRCFG_POSTMOD(i, v) ((v) << ASRCFG_POSTMODi_SHIFT(i))
++#define ASRCFG_POSTMODi_UP(i) (0 << ASRCFG_POSTMODi_SHIFT(i))
++#define ASRCFG_POSTMODi_DCON(i) (1 << ASRCFG_POSTMODi_SHIFT(i))
++#define ASRCFG_POSTMODi_DOWN(i) (2 << ASRCFG_POSTMODi_SHIFT(i))
++#define ASRCFG_PREMODi_SHIFT(i) (6 + (i << 2))
++#define ASRCFG_PREMODi_WIDTH 2
++#define ASRCFG_PREMODi_MASK(i) (((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
++#define ASRCFG_PREMOD(i, v) ((v) << ASRCFG_PREMODi_SHIFT(i))
++#define ASRCFG_PREMODi_UP(i) (0 << ASRCFG_PREMODi_SHIFT(i))
++#define ASRCFG_PREMODi_DCON(i) (1 << ASRCFG_PREMODi_SHIFT(i))
++#define ASRCFG_PREMODi_DOWN(i) (2 << ASRCFG_PREMODi_SHIFT(i))
++#define ASRCFG_PREMODi_BYPASS(i) (3 << ASRCFG_PREMODi_SHIFT(i))
++
++/* REG4 0x14 REG_ASRCSR */
++#define ASRCSR_AxCSi_WIDTH 4
++#define ASRCSR_AxCSi_MASK ((1 << ASRCSR_AxCSi_WIDTH) - 1)
++#define ASRCSR_AOCSi_SHIFT(i) (12 + (i << 2))
++#define ASRCSR_AOCSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
++#define ASRCSR_AOCS(i, v) ((v) << ASRCSR_AOCSi_SHIFT(i))
++#define ASRCSR_AICSi_SHIFT(i) (i << 2)
++#define ASRCSR_AICSi_MASK(i) (((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
++#define ASRCSR_AICS(i, v) ((v) << ASRCSR_AICSi_SHIFT(i))
++
++/* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
++#define ASRCDRi_AxCPi_WIDTH 3
++#define ASRCDRi_AICPi_SHIFT(i) (0 + (i % 2) * 6)
++#define ASRCDRi_AICPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
++#define ASRCDRi_AICP(i, v) ((v) << ASRCDRi_AICPi_SHIFT(i))
++#define ASRCDRi_AICDi_SHIFT(i) (3 + (i % 2) * 6)
++#define ASRCDRi_AICDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
++#define ASRCDRi_AICD(i, v) ((v) << ASRCDRi_AICDi_SHIFT(i))
++#define ASRCDRi_AOCPi_SHIFT(i) ((i < 2) ? 12 + i * 6 : 6)
++#define ASRCDRi_AOCPi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
++#define ASRCDRi_AOCP(i, v) ((v) << ASRCDRi_AOCPi_SHIFT(i))
++#define ASRCDRi_AOCDi_SHIFT(i) ((i < 2) ? 15 + i * 6 : 9)
++#define ASRCDRi_AOCDi_MASK(i) (((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
++#define ASRCDRi_AOCD(i, v) ((v) << ASRCDRi_AOCDi_SHIFT(i))
++
++/* REG7 0x20 REG_ASRSTR */
++#define ASRSTR_DSLCNT_SHIFT 21
++#define ASRSTR_DSLCNT_MASK (1 << ASRSTR_DSLCNT_SHIFT)
++#define ASRSTR_DSLCNT (1 << ASRSTR_DSLCNT_SHIFT)
++#define ASRSTR_ATQOL_SHIFT 20
++#define ASRSTR_ATQOL_MASK (1 << ASRSTR_ATQOL_SHIFT)
++#define ASRSTR_ATQOL (1 << ASRSTR_ATQOL_SHIFT)
++#define ASRSTR_AOOLi_SHIFT(i) (17 + i)
++#define ASRSTR_AOOLi_MASK(i) (1 << ASRSTR_AOOLi_SHIFT(i))
++#define ASRSTR_AOOL(i) (1 << ASRSTR_AOOLi_SHIFT(i))
++#define ASRSTR_AIOLi_SHIFT(i) (14 + i)
++#define ASRSTR_AIOLi_MASK(i) (1 << ASRSTR_AIOLi_SHIFT(i))
++#define ASRSTR_AIOL(i) (1 << ASRSTR_AIOLi_SHIFT(i))
++#define ASRSTR_AODOi_SHIFT(i) (11 + i)
++#define ASRSTR_AODOi_MASK(i) (1 << ASRSTR_AODOi_SHIFT(i))
++#define ASRSTR_AODO(i) (1 << ASRSTR_AODOi_SHIFT(i))
++#define ASRSTR_AIDUi_SHIFT(i) (8 + i)
++#define ASRSTR_AIDUi_MASK(i) (1 << ASRSTR_AIDUi_SHIFT(i))
++#define ASRSTR_AIDU(i) (1 << ASRSTR_AIDUi_SHIFT(i))
++#define ASRSTR_FPWT_SHIFT 7
++#define ASRSTR_FPWT_MASK (1 << ASRSTR_FPWT_SHIFT)
++#define ASRSTR_FPWT (1 << ASRSTR_FPWT_SHIFT)
++#define ASRSTR_AOLE_SHIFT 6
++#define ASRSTR_AOLE_MASK (1 << ASRSTR_AOLE_SHIFT)
++#define ASRSTR_AOLE (1 << ASRSTR_AOLE_SHIFT)
++#define ASRSTR_AODEi_SHIFT(i) (3 + i)
++#define ASRSTR_AODFi_MASK(i) (1 << ASRSTR_AODEi_SHIFT(i))
++#define ASRSTR_AODF(i) (1 << ASRSTR_AODEi_SHIFT(i))
++#define ASRSTR_AIDEi_SHIFT(i) (0 + i)
++#define ASRSTR_AIDEi_MASK(i) (1 << ASRSTR_AIDEi_SHIFT(i))
++#define ASRSTR_AIDE(i) (1 << ASRSTR_AIDEi_SHIFT(i))
++
++/* REG10 0x54 REG_ASRTFR1 */
++#define ASRTFR1_TF_BASE_WIDTH 7
++#define ASRTFR1_TF_BASE_SHIFT 6
++#define ASRTFR1_TF_BASE_MASK (((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
++#define ASRTFR1_TF_BASE(i) ((i) << ASRTFR1_TF_BASE_SHIFT)
++
++/*
++ * REG22 0xA0 REG_ASRMCRA
++ * REG24 0xA8 REG_ASRMCRB
++ * REG26 0xB0 REG_ASRMCRC
++ */
++#define ASRMCRi_ZEROBUFi_SHIFT 23
++#define ASRMCRi_ZEROBUFi_MASK (1 << ASRMCRi_ZEROBUFi_SHIFT)
++#define ASRMCRi_ZEROBUFi (1 << ASRMCRi_ZEROBUFi_SHIFT)
++#define ASRMCRi_EXTTHRSHi_SHIFT 22
++#define ASRMCRi_EXTTHRSHi_MASK (1 << ASRMCRi_EXTTHRSHi_SHIFT)
++#define ASRMCRi_EXTTHRSHi (1 << ASRMCRi_EXTTHRSHi_SHIFT)
++#define ASRMCRi_BUFSTALLi_SHIFT 21
++#define ASRMCRi_BUFSTALLi_MASK (1 << ASRMCRi_BUFSTALLi_SHIFT)
++#define ASRMCRi_BUFSTALLi (1 << ASRMCRi_BUFSTALLi_SHIFT)
++#define ASRMCRi_BYPASSPOLYi_SHIFT 20
++#define ASRMCRi_BYPASSPOLYi_MASK (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
++#define ASRMCRi_BYPASSPOLYi (1 << ASRMCRi_BYPASSPOLYi_SHIFT)
++#define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH 6
++#define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT 12
++#define ASRMCRi_OUTFIFO_THRESHOLD_MASK (((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
++#define ASRMCRi_OUTFIFO_THRESHOLD(v) (((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
++#define ASRMCRi_RSYNIFi_SHIFT 11
++#define ASRMCRi_RSYNIFi_MASK (1 << ASRMCRi_RSYNIFi_SHIFT)
++#define ASRMCRi_RSYNIFi (1 << ASRMCRi_RSYNIFi_SHIFT)
++#define ASRMCRi_RSYNOFi_SHIFT 10
++#define ASRMCRi_RSYNOFi_MASK (1 << ASRMCRi_RSYNOFi_SHIFT)
++#define ASRMCRi_RSYNOFi (1 << ASRMCRi_RSYNOFi_SHIFT)
++#define ASRMCRi_INFIFO_THRESHOLD_WIDTH 6
++#define ASRMCRi_INFIFO_THRESHOLD_SHIFT 0
++#define ASRMCRi_INFIFO_THRESHOLD_MASK (((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
++#define ASRMCRi_INFIFO_THRESHOLD(v) (((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
++
++/*
++ * REG23 0xA4 REG_ASRFSTA
++ * REG25 0xAC REG_ASRFSTB
++ * REG27 0xB4 REG_ASRFSTC
++ */
++#define ASRFSTi_OAFi_SHIFT 23
++#define ASRFSTi_OAFi_MASK (1 << ASRFSTi_OAFi_SHIFT)
++#define ASRFSTi_OAFi (1 << ASRFSTi_OAFi_SHIFT)
++#define ASRFSTi_OUTPUT_FIFO_WIDTH 7
++#define ASRFSTi_OUTPUT_FIFO_SHIFT 12
++#define ASRFSTi_OUTPUT_FIFO_MASK (((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
++#define ASRFSTi_IAEi_SHIFT 11
++#define ASRFSTi_IAEi_MASK (1 << ASRFSTi_OAFi_SHIFT)
++#define ASRFSTi_IAEi (1 << ASRFSTi_OAFi_SHIFT)
++#define ASRFSTi_INPUT_FIFO_WIDTH 7
++#define ASRFSTi_INPUT_FIFO_SHIFT 0
++#define ASRFSTi_INPUT_FIFO_MASK ((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
++
++/* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
++#define ASRMCR1i_IWD_WIDTH 3
++#define ASRMCR1i_IWD_SHIFT 9
++#define ASRMCR1i_IWD_MASK (((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
++#define ASRMCR1i_IWD(v) ((v) << ASRMCR1i_IWD_SHIFT)
++#define ASRMCR1i_IMSB_SHIFT 8
++#define ASRMCR1i_IMSB_MASK (1 << ASRMCR1i_IMSB_SHIFT)
++#define ASRMCR1i_IMSB_MSB (1 << ASRMCR1i_IMSB_SHIFT)
++#define ASRMCR1i_IMSB_LSB (0 << ASRMCR1i_IMSB_SHIFT)
++#define ASRMCR1i_OMSB_SHIFT 2
++#define ASRMCR1i_OMSB_MASK (1 << ASRMCR1i_OMSB_SHIFT)
++#define ASRMCR1i_OMSB_MSB (1 << ASRMCR1i_OMSB_SHIFT)
++#define ASRMCR1i_OMSB_LSB (0 << ASRMCR1i_OMSB_SHIFT)
++#define ASRMCR1i_OSGN_SHIFT 1
++#define ASRMCR1i_OSGN_MASK (1 << ASRMCR1i_OSGN_SHIFT)
++#define ASRMCR1i_OSGN (1 << ASRMCR1i_OSGN_SHIFT)
++#define ASRMCR1i_OW16_SHIFT 0
++#define ASRMCR1i_OW16_MASK (1 << ASRMCR1i_OW16_SHIFT)
++#define ASRMCR1i_OW16(v) ((v) << ASRMCR1i_OW16_SHIFT)
++
++#define ASRC_CLK_MAX_NUM 16
++
++
++struct dma_block {
++ dma_addr_t dma_paddr;
++ void *dma_vaddr;
++ unsigned int length;
++};
++
++/**
++ * fsl_asrc_pair: ASRC Pair private data
++ *
++ * @asrc_priv: pointer to its parent module
++ * @config: configuration profile
++ * @error: error record
++ * @index: pair index (ASRC_PAIR_A, ASRC_PAIR_B, ASRC_PAIR_C)
++ * @channels: occupied channel number
++ * @desc: input and output dma descriptors
++ * @dma_chan: inputer and output DMA channels
++ * @dma_data: private dma data
++ * @pos: hardware pointer position
++ * @private: pair private area
++ */
++struct fsl_asrc_pair {
++ struct fsl_asrc *asrc_priv;
++ struct asrc_config *config;
++ unsigned int error;
++
++ enum asrc_pair_index index;
++ unsigned int channels;
++
++ struct dma_async_tx_descriptor *desc[2];
++ struct dma_chan *dma_chan[2];
++ struct imx_dma_data dma_data;
++ unsigned int pos;
++
++ void *private;
++};
++
++/**
++ * fsl_asrc_pair: ASRC private data
++ *
++ * @dma_params_rx: DMA parameters for receive channel
++ * @dma_params_tx: DMA parameters for transmit channel
++ * @pdev: platform device pointer
++ * @regmap: regmap handler
++ * @paddr: physical address to the base address of registers
++ * @mem_clk: clock source to access register
++ * @ipg_clk: clock source to drive peripheral
++ * @asrck_clk: clock sources to driver ASRC internal logic
++ * @lock: spin lock for resource protection
++ * @pair: pair pointers
++ * @channel_bits: width of ASRCNCR register for each pair
++ * @channel_avail: non-occupied channel numbers
++ * @asrc_rate: default sample rate for ASoC Back-Ends
++ * @asrc_width: default sample width for ASoC Back-Ends
++ * @name: driver name
++ */
++struct fsl_asrc {
++ struct snd_dmaengine_dai_dma_data dma_params_rx;
++ struct snd_dmaengine_dai_dma_data dma_params_tx;
++ struct platform_device *pdev;
++ struct regmap *regmap;
++ unsigned long paddr;
++ struct clk *mem_clk;
++ struct clk *ipg_clk;
++ struct clk *dma_clk;
++ struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
++ spinlock_t lock;
++
++ struct snd_pcm_substream *substream[2];
++ struct fsl_asrc_pair *pair[ASRC_PAIR_MAX_NUM];
++ unsigned int channel_bits;
++ unsigned int channel_avail;
++
++ int asrc_rate;
++ int asrc_width;
++
++ u32 regcache_cfg;
++
++ char name[32];
++};
++
++extern struct snd_soc_platform_driver fsl_asrc_platform;
++struct dma_chan *fsl_asrc_get_dma_channel(struct fsl_asrc_pair *pair, bool dir);
++
++#endif /* _FSL_ASRC_H */
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_asrc_m2m.c linux-3.14.72/sound/soc/fsl/fsl_asrc_m2m.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_asrc_m2m.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/fsl_asrc_m2m.c 2016-06-19 22:11:55.525125571 +0200
+@@ -0,0 +1,964 @@
++/*
++ * Freescale ASRC Memory to Memory (M2M) driver
++ *
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#define FSL_ASRC_INPUTFIFO_WML 0x4
++#define FSL_ASRC_OUTPUTFIFO_WML 0x2
++
++#define DIR_STR(dir) dir == IN ? "in" : "out"
++
++struct fsl_asrc_m2m {
++ struct fsl_asrc_pair *pair;
++ struct completion complete[2];
++ struct dma_block dma_block[2];
++ unsigned int pair_hold;
++ unsigned int asrc_active;
++ unsigned int sg_nodes[2];
++ struct scatterlist sg[2][4];
++
++ enum asrc_word_width word_width[2];
++ unsigned int rate[2];
++ unsigned int last_period_size;
++ u32 watermark[2];
++ spinlock_t lock;
++};
++
++static struct miscdevice asrc_miscdev = {
++ .name = "mxc_asrc",
++ .minor = MISC_DYNAMIC_MINOR,
++};
++
++static void fsl_asrc_get_status(struct fsl_asrc_pair *pair,
++ struct asrc_status_flags *flags)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ unsigned long lock_flags;
++
++ spin_lock_irqsave(&asrc_priv->lock, lock_flags);
++
++ flags->overload_error = pair->error;
++
++ spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
++}
++
++#define ASRC_xPUT_DMA_CALLBACK(dir) \
++ ((dir == IN) ? fsl_asrc_input_dma_callback : fsl_asrc_output_dma_callback)
++
++static void fsl_asrc_input_dma_callback(void *data)
++{
++ struct fsl_asrc_pair *pair = (struct fsl_asrc_pair *)data;
++ struct fsl_asrc_m2m *m2m = pair->private;
++
++ complete(&m2m->complete[IN]);
++}
++
++static void fsl_asrc_output_dma_callback(void *data)
++{
++ struct fsl_asrc_pair *pair = (struct fsl_asrc_pair *)data;
++ struct fsl_asrc_m2m *m2m = pair->private;
++
++ complete(&m2m->complete[OUT]);
++}
++
++static unsigned int fsl_asrc_get_output_FIFO_size(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ u32 val;
++
++ regmap_read(asrc_priv->regmap, REG_ASRFST(index), &val);
++
++ val &= ASRFSTi_OUTPUT_FIFO_MASK;
++
++ return val >> ASRFSTi_OUTPUT_FIFO_SHIFT;
++}
++
++static void fsl_asrc_read_last_FIFO(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ struct dma_block *output = &m2m->dma_block[OUT];
++ u32 i, reg, size, t_size = 0;
++ u32 *reg24 = NULL;
++ u16 *reg16 = NULL;
++
++ if (m2m->word_width[OUT] == ASRC_WIDTH_24_BIT)
++ reg24 = output->dma_vaddr + output->length;
++ else
++ reg16 = output->dma_vaddr + output->length;
++
++retry:
++ size = fsl_asrc_get_output_FIFO_size(pair);
++
++ for (i = 0; i < size * pair->channels; i++) {
++ regmap_read(asrc_priv->regmap, REG_ASRDO(index), &reg);
++ if (reg24) {
++ *(reg24) = reg;
++ reg24++;
++ } else {
++ *(reg16) = (u16)reg;
++ reg16++;
++ }
++ }
++ t_size += size;
++
++ if (size)
++ goto retry;
++
++ if (t_size > m2m->last_period_size)
++ t_size = m2m->last_period_size;
++
++ if (reg24)
++ output->length += t_size * pair->channels * 4;
++ else
++ output->length += t_size * pair->channels * 2;
++}
++
++static int fsl_allocate_dma_buf(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct dma_block *input = &m2m->dma_block[IN];
++ struct dma_block *output = &m2m->dma_block[OUT];
++ enum asrc_pair_index index = pair->index;
++
++ input->dma_vaddr = kzalloc(input->length, GFP_KERNEL);
++ if (!input->dma_vaddr) {
++ pair_err("failed to allocate input DMA buffer\n");
++ return -ENOMEM;
++ }
++ input->dma_paddr = virt_to_dma(NULL, input->dma_vaddr);
++
++ output->dma_vaddr = kzalloc(output->length, GFP_KERNEL);
++ if (!output->dma_vaddr) {
++ pair_err("failed to allocate output DMA buffer\n");
++ goto exit;
++ }
++ output->dma_paddr = virt_to_dma(NULL, output->dma_vaddr);
++
++ return 0;
++
++exit:
++ kfree(input->dma_vaddr);
++
++ return -ENOMEM;
++}
++
++static int fsl_asrc_dmaconfig(struct fsl_asrc_pair *pair, struct dma_chan *chan,
++ u32 dma_addr, void *buf_addr, u32 buf_len,
++ bool dir, enum asrc_word_width word_width)
++{
++ struct dma_async_tx_descriptor *desc = pair->desc[dir];
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct fsl_asrc_m2m *m2m = pair->private;
++ unsigned int sg_nent = m2m->sg_nodes[dir];
++ enum asrc_pair_index index = pair->index;
++ struct scatterlist *sg = m2m->sg[dir];
++ struct dma_slave_config slave_config;
++ enum dma_slave_buswidth buswidth;
++ int ret, i;
++
++ switch (word_width) {
++ case ASRC_WIDTH_16_BIT:
++ buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
++ break;
++ case ASRC_WIDTH_24_BIT:
++ buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ break;
++ default:
++ pair_err("invalid word width\n");
++ return -EINVAL;
++ }
++
++ if (dir == IN) {
++ slave_config.direction = DMA_MEM_TO_DEV;
++ slave_config.dst_addr = dma_addr;
++ slave_config.dst_addr_width = buswidth;
++ slave_config.dst_maxburst =
++ m2m->watermark[IN] * pair->channels;
++ } else {
++ slave_config.direction = DMA_DEV_TO_MEM;
++ slave_config.src_addr = dma_addr;
++ slave_config.src_addr_width = buswidth;
++ slave_config.src_maxburst =
++ m2m->watermark[OUT] * pair->channels;
++ }
++
++ ret = dmaengine_slave_config(chan, &slave_config);
++ if (ret) {
++ pair_err("failed to config dmaengine for %sput task: %d\n",
++ DIR_STR(dir), ret);
++ return -EINVAL;
++ }
++
++ sg_init_table(sg, sg_nent);
++ switch (sg_nent) {
++ case 1:
++ sg_init_one(sg, buf_addr, buf_len);
++ break;
++ case 2:
++ case 3:
++ case 4:
++ for (i = 0; i < (sg_nent - 1); i++)
++ sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
++ ASRC_MAX_BUFFER_SIZE);
++
++ sg_set_buf(&sg[i], buf_addr + i * ASRC_MAX_BUFFER_SIZE,
++ buf_len - ASRC_MAX_BUFFER_SIZE * i);
++ break;
++ default:
++ pair_err("invalid input DMA nodes number: %d\n", sg_nent);
++ return -EINVAL;
++ }
++
++ ret = dma_map_sg(NULL, sg, sg_nent, slave_config.direction);
++ if (ret != sg_nent) {
++ pair_err("failed to map DMA sg for %sput task\n", DIR_STR(dir));
++ return -EINVAL;
++ }
++
++ desc = dmaengine_prep_slave_sg(chan, sg, sg_nent,
++ slave_config.direction, DMA_PREP_INTERRUPT);
++ if (!desc) {
++ pair_err("failed to prepare dmaengine for %sput task\n",
++ DIR_STR(dir));
++ return -EINVAL;
++ }
++
++ pair->desc[dir] = desc;
++ pair->desc[dir]->callback = ASRC_xPUT_DMA_CALLBACK(dir);
++
++ desc->callback = ASRC_xPUT_DMA_CALLBACK(dir);
++ desc->callback_param = pair;
++
++ return 0;
++}
++
++static int fsl_asrc_prepare_io_buffer(struct fsl_asrc_pair *pair,
++ struct asrc_convert_buffer *pbuf, bool dir)
++{
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ unsigned int *dma_len = &m2m->dma_block[dir].length;
++ enum asrc_word_width width = m2m->word_width[dir];
++ void *dma_vaddr = m2m->dma_block[dir].dma_vaddr;
++ struct dma_chan *dma_chan = pair->dma_chan[dir];
++ unsigned int buf_len, wm = m2m->watermark[dir];
++ unsigned int *sg_nodes = &m2m->sg_nodes[dir];
++ unsigned int last_period_size = m2m->last_period_size;
++ enum asrc_pair_index index = pair->index;
++ u32 word_size, fifo_addr;
++ void __user *buf_vaddr;
++
++ /* Clean the DMA buffer */
++ memset(dma_vaddr, 0, ASRC_DMA_BUFFER_SIZE);
++
++ if (dir == IN) {
++ buf_vaddr = (void __user *)pbuf->input_buffer_vaddr;
++ buf_len = pbuf->input_buffer_length;
++ } else {
++ buf_vaddr = (void __user *)pbuf->output_buffer_vaddr;
++ buf_len = pbuf->output_buffer_length;
++ }
++
++ if (width == ASRC_WIDTH_24_BIT)
++ word_size = 4;
++ else
++ word_size = 2;
++
++ if (buf_len < word_size * pair->channels * wm) {
++ pair_err("%sput buffer size is too small: [%d]\n",
++ DIR_STR(dir), buf_len);
++ return -EINVAL;
++ }
++
++ /* Copy origin data into input buffer */
++ if (dir == IN && copy_from_user(dma_vaddr, buf_vaddr, buf_len))
++ return -EFAULT;
++
++ *dma_len = buf_len;
++ if (dir == OUT)
++ *dma_len -= last_period_size * word_size * pair->channels;
++
++ *sg_nodes = *dma_len / ASRC_MAX_BUFFER_SIZE + 1;
++
++ fifo_addr = asrc_priv->paddr + REG_ASRDx(dir, index);
++
++ return fsl_asrc_dmaconfig(pair, dma_chan, fifo_addr, dma_vaddr,
++ *dma_len, dir, width);
++}
++
++static int fsl_asrc_prepare_buffer(struct fsl_asrc_pair *pair,
++ struct asrc_convert_buffer *pbuf)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ int ret;
++
++ ret = fsl_asrc_prepare_io_buffer(pair, pbuf, IN);
++ if (ret) {
++ pair_err("failed to prepare input buffer: %d\n", ret);
++ return ret;
++ }
++
++ ret = fsl_asrc_prepare_io_buffer(pair, pbuf, OUT);
++ if (ret) {
++ pair_err("failed to prepare output buffer: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++int fsl_asrc_process_buffer_pre(struct completion *complete,
++ enum asrc_pair_index index, bool dir)
++{
++ if (!wait_for_completion_interruptible_timeout(complete, 10 * HZ)) {
++ pr_err("%sput DMA task timeout\n", DIR_STR(dir));
++ return -ETIME;
++ } else if (signal_pending(current)) {
++ pr_err("%sput task forcibly aborted\n", DIR_STR(dir));
++ return -EBUSY;
++ }
++
++ init_completion(complete);
++
++ return 0;
++}
++
++#define mxc_asrc_dma_umap(m2m) \
++ do { \
++ dma_unmap_sg(NULL, m2m->sg[IN], m2m->sg_nodes[IN], \
++ DMA_MEM_TO_DEV); \
++ dma_unmap_sg(NULL, m2m->sg[OUT], m2m->sg_nodes[OUT], \
++ DMA_DEV_TO_MEM); \
++ } while (0)
++
++int fsl_asrc_process_buffer(struct fsl_asrc_pair *pair,
++ struct asrc_convert_buffer *pbuf)
++{
++ struct fsl_asrc_m2m *m2m = pair->private;
++ enum asrc_pair_index index = pair->index;
++ unsigned long lock_flags;
++ int ret;
++
++ /* Check input task first */
++ ret = fsl_asrc_process_buffer_pre(&m2m->complete[IN], index, OUT);
++ if (ret) {
++ mxc_asrc_dma_umap(m2m);
++ return ret;
++ }
++
++ /* ...then output task*/
++ ret = fsl_asrc_process_buffer_pre(&m2m->complete[OUT], index, IN);
++ if (ret) {
++ mxc_asrc_dma_umap(m2m);
++ return ret;
++ }
++
++ mxc_asrc_dma_umap(m2m);
++
++ /* Fetch the remaining data */
++ spin_lock_irqsave(&m2m->lock, lock_flags);
++ if (!m2m->pair_hold) {
++ spin_unlock_irqrestore(&m2m->lock, lock_flags);
++ return -EFAULT;
++ }
++ spin_unlock_irqrestore(&m2m->lock, lock_flags);
++
++ fsl_asrc_read_last_FIFO(pair);
++
++ /* Update final lengths after getting last FIFO */
++ pbuf->input_buffer_length = m2m->dma_block[IN].length;
++ pbuf->output_buffer_length = m2m->dma_block[OUT].length;
++
++ if (copy_to_user((void __user *)pbuf->output_buffer_vaddr,
++ m2m->dma_block[OUT].dma_vaddr,
++ m2m->dma_block[OUT].length))
++ return -EFAULT;
++
++ return 0;
++}
++
++#ifdef ASRC_POLLING_WITHOUT_DMA
++/* THIS FUNCTION ONLY EXISTS FOR DEBUGGING AND ONLY SUPPORTS TWO CHANNELS */
++static void fsl_asrc_polling_debug(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc_m2m *m2m = pair->private;
++ enum asrc_pair_index index = pair->index;
++ u32 *in24 = m2m->dma_block[IN].dma_vaddr;
++ u32 dma_len = m2m->dma_block[IN].length / (pair->channels * 4);
++ u32 *reg24 = m2m->dma_block[OUT].dma_vaddr;
++ u32 size, i, j, t_size, reg;
++
++ t_size = 0;
++
++ for (i = 0; i < dma_len; ) {
++ for (j = 0; j < 2; j++) {
++ regmap_write(asrc_priv->regmap, REG_ASRDx(index), *in24);
++ in24++;
++ regmap_write(asrc_priv->regmap, REG_ASRDx(index), *in24);
++ in24++;
++ i++;
++ }
++ udelay(50);
++ udelay(50 * m2m->rate[OUT] / m2m->rate[IN]);
++
++ size = fsl_asrc_get_output_FIFO_size(index);
++ for (j = 0; j < size; j++) {
++ regmap_read(asrc_priv->regmap, REG_ASRDO(index), &reg);
++ *(reg24) = reg;
++ reg24++;
++ regmap_read(asrc_priv->regmap, REG_ASRDO(index), &reg);
++ *(reg24) = reg;
++ reg24++;
++ }
++ t_size += size;
++ }
++
++ mdelay(1);
++ size = fsl_asrc_get_output_FIFO_size(index);
++ for (j = 0; j < size; j++) {
++ regmap_read(asrc_priv->regmap, REG_ASRDO(index), &reg);
++ *(reg24) = reg;
++ reg24++;
++ regmap_read(asrc_priv->regmap, REG_ASRDO(index), &reg);
++ *(reg24) = reg;
++ reg24++;
++ }
++ t_size += size;
++
++ m2m->dma_block[OUT].length = t_size * pair->channels * 4;
++
++ complete(&m2m->complete[OUT]);
++ complete(&m2m->complete[IN]);
++}
++#else
++static void fsl_asrc_submit_dma(struct fsl_asrc_pair *pair)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct fsl_asrc_m2m *m2m = pair->private;
++ enum asrc_pair_index index = pair->index;
++ u32 size = fsl_asrc_get_output_FIFO_size(pair);
++ int i;
++
++ /* Read all data in OUTPUT FIFO */
++ while (size) {
++ u32 val;
++ for (i = 0; i < size * pair->channels; i++)
++ regmap_read(asrc_priv->regmap, REG_ASRDO(index), &val);
++ /* Fetch the data every 100us */
++ udelay(100);
++
++ size = fsl_asrc_get_output_FIFO_size(pair);
++ }
++
++ /* Submit DMA request */
++ dmaengine_submit(pair->desc[IN]);
++ dma_async_issue_pending(pair->desc[IN]->chan);
++
++ dmaengine_submit(pair->desc[OUT]);
++ dma_async_issue_pending(pair->desc[OUT]->chan);
++
++ /*
++ * Clear DMA request during the stall state of ASRC:
++ * During STALL state, the remaining in input fifo would never be
++ * smaller than the input threshold while the output fifo would not
++ * be bigger than output one. Thus the DMA request would be cleared.
++ */
++ fsl_asrc_set_watermarks(pair, ASRC_FIFO_THRESHOLD_MIN,
++ ASRC_FIFO_THRESHOLD_MAX);
++
++ /* Update the real input threshold to raise DMA request */
++ fsl_asrc_set_watermarks(pair, m2m->watermark[IN], m2m->watermark[OUT]);
++}
++#endif /* ASRC_POLLING_WITHOUT_DMA */
++
++static long fsl_asrc_ioctl_req_pair(struct fsl_asrc_pair *pair,
++ void __user *user)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct device *dev = &asrc_priv->pdev->dev;
++ struct asrc_req req;
++ unsigned long lock_flags;
++ long ret;
++
++ ret = copy_from_user(&req, user, sizeof(req));
++ if (ret) {
++ dev_err(dev, "failed to get req from user space: %ld\n", ret);
++ return ret;
++ }
++
++ ret = fsl_asrc_request_pair(req.chn_num, pair);
++ if (ret) {
++ dev_err(dev, "failed to request pair: %ld\n", ret);
++ return ret;
++ }
++
++ spin_lock_irqsave(&m2m->lock, lock_flags);
++ m2m->pair_hold = 1;
++ spin_unlock_irqrestore(&m2m->lock, lock_flags);
++ pair->channels = req.chn_num;
++
++ req.index = pair->index;
++
++ ret = copy_to_user(user, &req, sizeof(req));
++ if (ret) {
++ dev_err(dev, "failed to send req to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl_config_pair(struct fsl_asrc_pair *pair,
++ void __user *user)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct device *dev = &asrc_priv->pdev->dev;
++ struct asrc_config config;
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&config, user, sizeof(config));
++ if (ret) {
++ dev_err(dev, "failed to get config from user space: %ld\n", ret);
++ return ret;
++ }
++
++ index = config.pair;
++
++ pair->config = &config;
++ ret = fsl_asrc_config_pair(pair, false, false);
++ if (ret) {
++ pair_err("failed to config pair: %ld\n", ret);
++ return ret;
++ }
++
++ m2m->watermark[IN] = FSL_ASRC_INPUTFIFO_WML;
++ m2m->watermark[OUT] = FSL_ASRC_OUTPUTFIFO_WML;
++
++ fsl_asrc_set_watermarks(pair, m2m->watermark[IN], m2m->watermark[OUT]);
++
++ m2m->dma_block[IN].length = ASRC_DMA_BUFFER_SIZE;
++ m2m->dma_block[OUT].length = ASRC_DMA_BUFFER_SIZE;
++
++ m2m->word_width[IN] = config.input_word_width;
++ m2m->word_width[OUT] = config.output_word_width;
++
++ m2m->rate[IN] = config.input_sample_rate;
++ m2m->rate[OUT] = config.output_sample_rate;
++
++ if (m2m->rate[OUT] > m2m->rate[IN])
++ m2m->last_period_size = ASRC_OUTPUT_LAST_SAMPLE_MAX;
++ else
++ m2m->last_period_size = ASRC_OUTPUT_LAST_SAMPLE;
++
++ ret = fsl_allocate_dma_buf(pair);
++ if (ret) {
++ pair_err("failed to allocate DMA buffer: %ld\n", ret);
++ return ret;
++ }
++
++ /* Request DMA channel for both input and output */
++ pair->dma_chan[IN] = fsl_asrc_get_dma_channel(pair, IN);
++ if (pair->dma_chan[IN] == NULL) {
++ pair_err("failed to request input task DMA channel\n");
++ return -EBUSY;
++ }
++
++ pair->dma_chan[OUT] = fsl_asrc_get_dma_channel(pair, OUT);
++ if (pair->dma_chan[OUT] == NULL) {
++ pair_err("failed to request output task DMA channel\n");
++ return -EBUSY;
++ }
++
++ ret = copy_to_user(user, &config, sizeof(config));
++ if (ret) {
++ pair_err("failed to send config to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl_release_pair(struct fsl_asrc_pair *pair,
++ void __user *user)
++{
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index;
++ unsigned long lock_flags;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ pair_err("failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ /* index might be not valid due to some application failure. */
++ if (index < 0)
++ return -EINVAL;
++
++ m2m->asrc_active = 0;
++
++ spin_lock_irqsave(&m2m->lock, lock_flags);
++ m2m->pair_hold = 0;
++ spin_unlock_irqrestore(&m2m->lock, lock_flags);
++
++ if (pair->dma_chan[IN])
++ dma_release_channel(pair->dma_chan[IN]);
++ if (pair->dma_chan[OUT])
++ dma_release_channel(pair->dma_chan[OUT]);
++ kfree(m2m->dma_block[IN].dma_vaddr);
++ kfree(m2m->dma_block[OUT].dma_vaddr);
++ fsl_asrc_release_pair(pair);
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl_convert(struct fsl_asrc_pair *pair,
++ void __user *user)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ struct asrc_convert_buffer buf;
++ long ret;
++
++ ret = copy_from_user(&buf, user, sizeof(buf));
++ if (ret) {
++ pair_err("failed to get buf from user space: %ld\n", ret);
++ return ret;
++ }
++
++ ret = fsl_asrc_prepare_buffer(pair, &buf);
++ if (ret) {
++ pair_err("failed to prepare buffer: %ld\n", ret);
++ return ret;
++ }
++
++#ifdef ASRC_POLLING_WITHOUT_DMA
++ fsl_asrc_polling_debug(pair);
++#else
++ fsl_asrc_submit_dma(pair);
++#endif
++
++ ret = fsl_asrc_process_buffer(pair, &buf);
++ if (ret) {
++ pair_err("failed to process buffer: %ld\n", ret);
++ return ret;
++ }
++
++ ret = copy_to_user(user, &buf, sizeof(buf));
++ if (ret) {
++ pair_err("failed to send buf to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl_start_conv(struct fsl_asrc_pair *pair,
++ void __user *user)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct fsl_asrc_m2m *m2m = pair->private;
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ pair_err("failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ m2m->asrc_active = 1;
++ fsl_asrc_start_pair(pair);
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl_stop_conv(struct fsl_asrc_pair *pair,
++ void __user *user)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct fsl_asrc_m2m *m2m = pair->private;
++ enum asrc_pair_index index;
++ long ret;
++
++ ret = copy_from_user(&index, user, sizeof(index));
++ if (ret) {
++ pair_err("failed to get index from user space: %ld\n", ret);
++ return ret;
++ }
++
++ dmaengine_terminate_all(pair->dma_chan[IN]);
++ dmaengine_terminate_all(pair->dma_chan[OUT]);
++
++ fsl_asrc_stop_pair(pair);
++ m2m->asrc_active = 0;
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl_status(struct fsl_asrc_pair *pair, void __user *user)
++{
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++ struct asrc_status_flags flags;
++ long ret;
++
++ ret = copy_from_user(&flags, user, sizeof(flags));
++ if (ret) {
++ pair_err("failed to get flags from user space: %ld\n", ret);
++ return ret;
++ }
++
++ fsl_asrc_get_status(pair, &flags);
++
++ ret = copy_to_user(user, &flags, sizeof(flags));
++ if (ret) {
++ pair_err("failed to send flags to user space: %ld\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl_flush(struct fsl_asrc_pair *pair, void __user *user)
++{
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ enum asrc_pair_index index = pair->index;
++
++ init_completion(&m2m->complete[IN]);
++ init_completion(&m2m->complete[OUT]);
++
++ /* Release DMA and request again */
++ dma_release_channel(pair->dma_chan[IN]);
++ dma_release_channel(pair->dma_chan[OUT]);
++
++ pair->dma_chan[IN] = fsl_asrc_get_dma_channel(pair, IN);
++ if (pair->dma_chan[IN] == NULL) {
++ pair_err("failed to request input task DMA channel\n");
++ return -EBUSY;
++ }
++
++ pair->dma_chan[OUT] = fsl_asrc_get_dma_channel(pair, OUT);
++ if (pair->dma_chan[OUT] == NULL) {
++ pair_err("failed to request output task DMA channel\n");
++ return -EBUSY;
++ }
++
++ return 0;
++}
++
++static long fsl_asrc_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
++{
++ struct fsl_asrc_pair *pair = file->private_data;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ void __user *user = (void __user *)arg;
++ long ret = 0;
++
++ switch (cmd) {
++ case ASRC_REQ_PAIR:
++ ret = fsl_asrc_ioctl_req_pair(pair, user);
++ break;
++ case ASRC_CONFIG_PAIR:
++ ret = fsl_asrc_ioctl_config_pair(pair, user);
++ break;
++ case ASRC_RELEASE_PAIR:
++ ret = fsl_asrc_ioctl_release_pair(pair, user);
++ break;
++ case ASRC_CONVERT:
++ ret = fsl_asrc_ioctl_convert(pair, user);
++ break;
++ case ASRC_START_CONV:
++ ret = fsl_asrc_ioctl_start_conv(pair, user);
++ break;
++ case ASRC_STOP_CONV:
++ ret = fsl_asrc_ioctl_stop_conv(pair, user);
++ break;
++ case ASRC_STATUS:
++ ret = fsl_asrc_ioctl_status(pair, user);
++ break;
++ case ASRC_FLUSH:
++ ret = fsl_asrc_ioctl_flush(pair, user);
++ break;
++ default:
++ dev_err(&asrc_priv->pdev->dev, "invalid ioctl cmd!\n");
++ break;
++ }
++
++ return ret;
++}
++
++static int fsl_asrc_open(struct inode *inode, struct file *file)
++{
++ struct fsl_asrc *asrc_priv = dev_get_drvdata(asrc_miscdev.this_device);
++ struct device *dev = &asrc_priv->pdev->dev;
++ struct fsl_asrc_pair *pair;
++ struct fsl_asrc_m2m *m2m;
++ int ret;
++
++ ret = signal_pending(current);
++ if (ret) {
++ dev_err(dev, "current process has a signal pending\n");
++ return ret;
++ }
++
++ pair = kzalloc(sizeof(struct fsl_asrc_pair), GFP_KERNEL);
++ if (!pair) {
++ dev_err(dev, "failed to allocate pair\n");
++ return -ENOMEM;
++ }
++
++ m2m = kzalloc(sizeof(struct fsl_asrc_m2m), GFP_KERNEL);
++ if (!pair) {
++ dev_err(dev, "failed to allocate m2m resource\n");
++ return -ENOMEM;
++ }
++
++ pair->private = m2m;
++ pair->asrc_priv = asrc_priv;
++
++ init_completion(&m2m->complete[IN]);
++ init_completion(&m2m->complete[OUT]);
++
++ spin_lock_init(&m2m->lock);
++
++ file->private_data = pair;
++
++ pm_runtime_get_sync(dev);
++
++ return 0;
++}
++
++static int fsl_asrc_close(struct inode *inode, struct file *file)
++{
++ struct fsl_asrc_pair *pair = file->private_data;
++ struct fsl_asrc_m2m *m2m = pair->private;
++ struct fsl_asrc *asrc_priv = pair->asrc_priv;
++ struct device *dev = &asrc_priv->pdev->dev;
++ unsigned long lock_flags;
++ int i;
++
++ if (!pair)
++ goto out;
++
++ /* Make sure we have clear the pointer */
++ spin_lock_irqsave(&asrc_priv->lock, lock_flags);
++ for (i = 0; i < ASRC_PAIR_MAX_NUM; i++)
++ if (asrc_priv->pair[i] == pair)
++ asrc_priv->pair[i] = NULL;
++ spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
++
++ if (m2m->asrc_active) {
++ m2m->asrc_active = 0;
++
++ dmaengine_terminate_all(pair->dma_chan[IN]);
++ dmaengine_terminate_all(pair->dma_chan[OUT]);
++
++ fsl_asrc_stop_pair(pair);
++ fsl_asrc_input_dma_callback((void *)pair);
++ fsl_asrc_output_dma_callback((void *)pair);
++ }
++
++ spin_lock_irqsave(&m2m->lock, lock_flags);
++ if (m2m->pair_hold) {
++ m2m->pair_hold = 0;
++ spin_unlock_irqrestore(&m2m->lock, lock_flags);
++
++ if (pair->dma_chan[IN])
++ dma_release_channel(pair->dma_chan[IN]);
++ if (pair->dma_chan[OUT])
++ dma_release_channel(pair->dma_chan[OUT]);
++
++ kfree(m2m->dma_block[IN].dma_vaddr);
++ kfree(m2m->dma_block[OUT].dma_vaddr);
++
++ fsl_asrc_release_pair(pair);
++ } else
++ spin_unlock_irqrestore(&m2m->lock, lock_flags);
++
++ spin_lock_irqsave(&asrc_priv->lock, lock_flags);
++ kfree(m2m);
++ kfree(pair);
++ spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
++ file->private_data = NULL;
++
++out:
++ pm_runtime_put_sync(dev);
++
++ return 0;
++}
++
++static const struct file_operations asrc_fops = {
++ .owner = THIS_MODULE,
++ .unlocked_ioctl = fsl_asrc_ioctl,
++ .open = fsl_asrc_open,
++ .release = fsl_asrc_close,
++};
++
++static int fsl_asrc_m2m_init(struct fsl_asrc *asrc_priv)
++{
++ struct device *dev = &asrc_priv->pdev->dev;
++ int ret;
++
++ asrc_miscdev.fops = &asrc_fops,
++ ret = misc_register(&asrc_miscdev);
++ if (ret) {
++ dev_err(dev, "failed to register char device %d\n", ret);
++ return ret;
++ }
++ dev_set_drvdata(asrc_miscdev.this_device, asrc_priv);
++
++ return 0;
++}
++
++static int fsl_asrc_m2m_remove(struct platform_device *pdev)
++{
++ misc_deregister(&asrc_miscdev);
++ return 0;
++}
++
++static void fsl_asrc_m2m_suspend(struct fsl_asrc *asrc_priv)
++{
++ struct fsl_asrc_pair *pair;
++ struct fsl_asrc_m2m *m2m;
++ unsigned long lock_flags;
++ int i;
++
++ for (i = 0; i < ASRC_PAIR_MAX_NUM; i++) {
++ spin_lock_irqsave(&asrc_priv->lock, lock_flags);
++ pair = asrc_priv->pair[i];
++ if (!pair || !pair->private) {
++ spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
++ continue;
++ }
++ m2m = pair->private;
++
++ if (!completion_done(&m2m->complete[IN])) {
++ if (pair->dma_chan[IN])
++ dmaengine_terminate_all(pair->dma_chan[IN]);
++ fsl_asrc_input_dma_callback((void *)pair);
++ }
++ if (!completion_done(&m2m->complete[OUT])) {
++ if (pair->dma_chan[OUT])
++ dmaengine_terminate_all(pair->dma_chan[OUT]);
++ fsl_asrc_output_dma_callback((void *)pair);
++ }
++
++ spin_unlock_irqrestore(&asrc_priv->lock, lock_flags);
++ }
++}
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_dma.c linux-3.14.72/sound/soc/fsl/fsl_dma.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_dma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_dma.c 2016-06-19 22:11:55.525125571 +0200
+@@ -923,8 +923,8 @@
+ dma->dai.pcm_free = fsl_dma_free_dma_buffers;
+
+ /* Store the SSI-specific information that we need */
+- dma->ssi_stx_phys = res.start + offsetof(struct ccsr_ssi, stx0);
+- dma->ssi_srx_phys = res.start + offsetof(struct ccsr_ssi, srx0);
++ dma->ssi_stx_phys = res.start + CCSR_SSI_STX0;
++ dma->ssi_srx_phys = res.start + CCSR_SSI_SRX0;
+
+ iprop = of_get_property(ssi_np, "fsl,fifo-depth", NULL);
+ if (iprop)
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_esai.c linux-3.14.72/sound/soc/fsl/fsl_esai.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_esai.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_esai.c 2016-06-19 22:11:55.525125571 +0200
+@@ -37,7 +37,10 @@
+ * @fsysclk: system clock source to derive HCK, SCK and FS
+ * @fifo_depth: depth of tx/rx FIFO
+ * @slot_width: width of each DAI slot
++ * @slots: number of slots
+ * @hck_rate: clock rate of desired HCKx clock
++ * @sck_rate: clock rate of desired SCKx clock
++ * @hck_dir: the direction of HCKx pads
+ * @sck_div: if using PSR/PM dividers for SCKx clock
+ * @slave_mode: if fully using DAI slave mode
+ * @synchronous: if using tx/rx synchronous mode
+@@ -46,14 +49,21 @@
+ struct fsl_esai {
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
++ struct snd_pcm_substream *substream[2];
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ struct clk *coreclk;
+ struct clk *extalclk;
+ struct clk *fsysclk;
++ struct clk *dmaclk;
+ u32 fifo_depth;
+ u32 slot_width;
++ u32 slots;
++ u32 tx_mask;
++ u32 rx_mask;
+ u32 hck_rate[2];
++ u32 sck_rate[2];
++ bool hck_dir[2];
+ bool sck_div[2];
+ bool slave_mode;
+ bool synchronous;
+@@ -208,8 +218,13 @@
+ struct clk *clksrc = esai_priv->extalclk;
+ bool tx = clk_id <= ESAI_HCKT_EXTAL;
+ bool in = dir == SND_SOC_CLOCK_IN;
+- u32 ret, ratio, ecr = 0;
++ u32 ratio, ecr = 0;
+ unsigned long clk_rate;
++ int ret;
++
++ /* Bypass divider settings if the requirement doesn't change */
++ if (freq == esai_priv->hck_rate[tx] && dir == esai_priv->hck_dir[tx])
++ return 0;
+
+ /* sck_div can be only bypassed if ETO/ERO=0 and SNC_SOC_CLOCK_OUT */
+ esai_priv->sck_div[tx] = true;
+@@ -257,10 +272,16 @@
+ return -EINVAL;
+ }
+
+- if (ratio == 1) {
++ /* Only EXTAL source can be output directly without using PSR and PM */
++ if (ratio == 1 && clksrc == esai_priv->extalclk) {
+ /* Bypass all the dividers if not being needed */
+ ecr |= tx ? ESAI_ECR_ETO : ESAI_ECR_ERO;
+ goto out;
++ } else if (ratio < 2) {
++ /* The ratio should be no less than 2 if using other sources */
++ dev_err(dai->dev, "failed to derive required HCK%c rate\n",
++ tx ? 'T' : 'R');
++ return -EINVAL;
+ }
+
+ ret = fsl_esai_divisor_cal(dai, tx, ratio, false, 0);
+@@ -270,6 +291,7 @@
+ esai_priv->sck_div[tx] = false;
+
+ out:
++ esai_priv->hck_dir[tx] = dir;
+ esai_priv->hck_rate[tx] = freq;
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
+@@ -287,9 +309,10 @@
+ struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
+ u32 hck_rate = esai_priv->hck_rate[tx];
+ u32 sub, ratio = hck_rate / freq;
++ int ret;
+
+- /* Don't apply for fully slave mode*/
+- if (esai_priv->slave_mode)
++ /* Don't apply for fully slave mode or unchanged bclk */
++ if (esai_priv->slave_mode || esai_priv->sck_rate[tx] == freq)
+ return 0;
+
+ if (ratio * freq > hck_rate)
+@@ -306,13 +329,21 @@
+ return -EINVAL;
+ }
+
+- if (esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
++ /* The ratio should be contented by FP alone if bypassing PM and PSR */
++ if (!esai_priv->sck_div[tx] && (ratio > 16 || ratio == 0)) {
+ dev_err(dai->dev, "the ratio is out of range (1 ~ 16)\n");
+ return -EINVAL;
+ }
+
+- return fsl_esai_divisor_cal(dai, tx, ratio, true,
++ ret = fsl_esai_divisor_cal(dai, tx, ratio, true,
+ esai_priv->sck_div[tx] ? 0 : ratio);
++ if (ret)
++ return ret;
++
++ /* Save current bclk rate */
++ esai_priv->sck_rate[tx] = freq;
++
++ return 0;
+ }
+
+ static int fsl_esai_set_dai_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask,
+@@ -323,20 +354,13 @@
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_TCCR,
+ ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
+
+- regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMA,
+- ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(tx_mask));
+- regmap_update_bits(esai_priv->regmap, REG_ESAI_TSMB,
+- ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(tx_mask));
+-
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_RCCR,
+ ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(slots));
+
+- regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMA,
+- ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(rx_mask));
+- regmap_update_bits(esai_priv->regmap, REG_ESAI_RSMB,
+- ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(rx_mask));
+-
+ esai_priv->slot_width = slot_width;
++ esai_priv->slots = slots;
++ esai_priv->tx_mask = tx_mask;
++ esai_priv->rx_mask = rx_mask;
+
+ return 0;
+ }
+@@ -432,24 +456,30 @@
+ struct snd_soc_dai *dai)
+ {
+ struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
++ int ret;
+
+ /*
+ * Some platforms might use the same bit to gate all three or two of
+ * clocks, so keep all clocks open/close at the same time for safety
+ */
+- clk_prepare_enable(esai_priv->coreclk);
+- if (!IS_ERR(esai_priv->extalclk))
+- clk_prepare_enable(esai_priv->extalclk);
+- if (!IS_ERR(esai_priv->fsysclk))
+- clk_prepare_enable(esai_priv->fsysclk);
++ ret = clk_prepare_enable(esai_priv->coreclk);
++ if (ret)
++ return ret;
++ ret = clk_prepare_enable(esai_priv->dmaclk);
++ if (ret)
++ return ret;
++ if (!IS_ERR(esai_priv->extalclk)) {
++ ret = clk_prepare_enable(esai_priv->extalclk);
++ if (ret)
++ goto err_extalck;
++ }
++ if (!IS_ERR(esai_priv->fsysclk)) {
++ ret = clk_prepare_enable(esai_priv->fsysclk);
++ if (ret)
++ goto err_fsysclk;
++ }
+
+ if (!dai->active) {
+- /* Reset Port C */
+- regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
+- ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
+- regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
+- ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
+-
+ /* Set synchronous mode */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_SAICR,
+ ESAI_SAICR_SYNC, esai_priv->synchronous ?
+@@ -462,7 +492,18 @@
+ ESAI_xCCR_xDC_MASK, ESAI_xCCR_xDC(2));
+ }
+
++ esai_priv->substream[substream->stream] = substream;
++
+ return 0;
++
++err_fsysclk:
++ if (!IS_ERR(esai_priv->extalclk))
++ clk_disable_unprepare(esai_priv->extalclk);
++err_extalck:
++ clk_disable_unprepare(esai_priv->dmaclk);
++ clk_disable_unprepare(esai_priv->coreclk);
++
++ return ret;
+ }
+
+ static int fsl_esai_hw_params(struct snd_pcm_substream *substream,
+@@ -473,9 +514,11 @@
+ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+ u32 width = snd_pcm_format_width(params_format(params));
+ u32 channels = params_channels(params);
+- u32 bclk, mask, val, ret;
++ u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
++ u32 bclk, mask, val;
++ int ret;
+
+- bclk = params_rate(params) * esai_priv->slot_width * 2;
++ bclk = params_rate(params) * esai_priv->slot_width * esai_priv->slots;
+
+ ret = fsl_esai_set_bclk(dai, tx, bclk);
+ if (ret)
+@@ -492,7 +535,7 @@
+ mask = ESAI_xFCR_xFR_MASK | ESAI_xFCR_xWA_MASK | ESAI_xFCR_xFWM_MASK |
+ (tx ? ESAI_xFCR_TE_MASK | ESAI_xFCR_TIEN : ESAI_xFCR_RE_MASK);
+ val = ESAI_xFCR_xWA(width) | ESAI_xFCR_xFWM(esai_priv->fifo_depth) |
+- (tx ? ESAI_xFCR_TE(channels) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(channels));
++ (tx ? ESAI_xFCR_TE(pins) | ESAI_xFCR_TIEN : ESAI_xFCR_RE(pins));
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx), mask, val);
+
+@@ -501,6 +544,11 @@
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx), mask, val);
+
++ /* Remove ESAI personal reset by configuring ESAI_PCRC and ESAI_PRRC */
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
++ ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
++ ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
+ return 0;
+ }
+
+@@ -509,10 +557,13 @@
+ {
+ struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
+
++ esai_priv->substream[substream->stream] = NULL;
++
+ if (!IS_ERR(esai_priv->fsysclk))
+ clk_disable_unprepare(esai_priv->fsysclk);
+ if (!IS_ERR(esai_priv->extalclk))
+ clk_disable_unprepare(esai_priv->extalclk);
++ clk_disable_unprepare(esai_priv->dmaclk);
+ clk_disable_unprepare(esai_priv->coreclk);
+ }
+
+@@ -522,6 +573,8 @@
+ struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(dai);
+ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+ u8 i, channels = substream->runtime->channels;
++ u32 pins = DIV_ROUND_UP(channels, esai_priv->slots);
++ u32 mask;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+@@ -536,13 +589,23 @@
+
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
+ tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK,
+- tx ? ESAI_xCR_TE(channels) : ESAI_xCR_RE(channels));
++ tx ? ESAI_xCR_TE(pins) : ESAI_xCR_RE(pins));
++ mask = tx ? esai_priv->tx_mask : esai_priv->rx_mask;
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
++ ESAI_xSMA_xS_MASK, ESAI_xSMA_xS(mask));
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
++ ESAI_xSMB_xS_MASK, ESAI_xSMB_xS(mask));
++
+ break;
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xCR(tx),
+ tx ? ESAI_xCR_TE_MASK : ESAI_xCR_RE_MASK, 0);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMA(tx),
++ ESAI_xSMA_xS_MASK, 0);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_xSMB(tx),
++ ESAI_xSMB_xS_MASK, 0);
+
+ /* Disable and reset FIFO */
+ regmap_update_bits(esai_priv->regmap, REG_ESAI_xFCR(tx),
+@@ -580,12 +643,14 @@
+ static struct snd_soc_dai_driver fsl_esai_dai = {
+ .probe = fsl_esai_dai_probe,
+ .playback = {
++ .stream_name = "CPU-Playback",
+ .channels_min = 1,
+ .channels_max = 12,
+ .rates = FSL_ESAI_RATES,
+ .formats = FSL_ESAI_FORMATS,
+ },
+ .capture = {
++ .stream_name = "CPU-Capture",
+ .channels_min = 1,
+ .channels_max = 8,
+ .rates = FSL_ESAI_RATES,
+@@ -630,6 +695,32 @@
+ }
+ }
+
++static bool fsl_esai_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_ESAI_ETDR:
++ case REG_ESAI_ERDR:
++ case REG_ESAI_ESR:
++ case REG_ESAI_TFSR:
++ case REG_ESAI_RFSR:
++ case REG_ESAI_TX0:
++ case REG_ESAI_TX1:
++ case REG_ESAI_TX2:
++ case REG_ESAI_TX3:
++ case REG_ESAI_TX4:
++ case REG_ESAI_TX5:
++ case REG_ESAI_RX0:
++ case REG_ESAI_RX1:
++ case REG_ESAI_RX2:
++ case REG_ESAI_RX3:
++ case REG_ESAI_SAISR:
++ return true;
++ default:
++ return false;
++ }
++
++}
++
+ static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
+@@ -661,16 +752,121 @@
+ }
+ }
+
+-static const struct regmap_config fsl_esai_regmap_config = {
++static struct regmap_config fsl_esai_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
+ .max_register = REG_ESAI_PCRC,
+ .readable_reg = fsl_esai_readable_reg,
++ .volatile_reg = fsl_esai_volatile_reg,
+ .writeable_reg = fsl_esai_writeable_reg,
++ .cache_type = REGCACHE_RBTREE,
+ };
+
++static bool fsl_esai_check_xrun(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 saisr;
++
++ regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
++
++ return saisr & (ESAI_SAISR_TUE | ESAI_SAISR_ROE) ;
++}
++
++static int stop_lock_stream(struct snd_pcm_substream *substream)
++{
++ if (substream) {
++ snd_pcm_stream_lock_irq(substream);
++ if (substream->runtime->status->state == SNDRV_PCM_STATE_RUNNING
++ && substream->ops)
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_STOP);
++ }
++ return 0;
++}
++
++static int start_unlock_stream(struct snd_pcm_substream *substream)
++{
++ if (substream) {
++ if (substream->runtime->status->state == SNDRV_PCM_STATE_RUNNING
++ && substream->ops)
++ substream->ops->trigger(substream, SNDRV_PCM_TRIGGER_START);
++ snd_pcm_stream_unlock_irq(substream);
++ }
++ return 0;
++}
++
++/*
++ *Here is ESAI underrun reset step:
++ *1. Read "TUE" and got TUE=1
++ *2. stop DMA.
++ *3. stop ESAI TX section.
++ *4. Set the transmitter section individual reset "TPR=1"
++ *5. Reset the ESAI Transmit FIFO (set ESAI_TFCR[1]=1).
++ *6. Config the control registers ESAI_TCCR and ESAI_TCR.config the Transmit FIFO register.
++ *7. clear "TPR"
++ *8. read "TUE"
++ *9. Prefill ESAI TX FIFO.
++ *10.Start DMA.
++ *11 Enable the ESAI
++ */
++static void fsl_esai_reset(struct snd_pcm_substream *substream, bool stop)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct fsl_esai *esai_priv = snd_soc_dai_get_drvdata(cpu_dai);
++ u32 saisr;
++
++ if (stop) {
++ stop_lock_stream(esai_priv->substream[0]);
++ stop_lock_stream(esai_priv->substream[1]);
++ }
++
++
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
++ ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
++ ESAI_ECR_ESAIEN | ESAI_ECR_ERST);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_ECR,
++ ESAI_ECR_ESAIEN_MASK | ESAI_ECR_ERST_MASK,
++ ESAI_ECR_ESAIEN);
++
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, ESAI_xCR_xPR_MASK, ESAI_xCR_xPR);
++
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC, ESAI_PRRC_PDC_MASK, 0);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC, ESAI_PCRC_PC_MASK, 0);
++
++ /*
++ * Add fifo reset here, because the regcache_sync will write one more data to ETDR.
++ * Which will cause channel shift.
++ */
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR_MASK, ESAI_xFCR_xFR);
++
++ regcache_mark_dirty(esai_priv->regmap);
++ regcache_sync(esai_priv->regmap);
++
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR_MASK, 0);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR_MASK, 0);
++
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_TCR, ESAI_xCR_xPR_MASK, 0);
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_RCR, ESAI_xCR_xPR_MASK, 0);
++
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_PRRC,
++ ESAI_PRRC_PDC_MASK, ESAI_PRRC_PDC(ESAI_GPIO));
++ regmap_update_bits(esai_priv->regmap, REG_ESAI_PCRC,
++ ESAI_PCRC_PC_MASK, ESAI_PCRC_PC(ESAI_GPIO));
++
++ regmap_read(esai_priv->regmap, REG_ESAI_SAISR, &saisr);
++
++ if (stop) {
++ start_unlock_stream(esai_priv->substream[1]);
++ start_unlock_stream(esai_priv->substream[0]);
++ }
++}
++
+ static int fsl_esai_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+@@ -687,6 +883,9 @@
+ esai_priv->pdev = pdev;
+ strcpy(esai_priv->name, np->name);
+
++ if (of_property_read_bool(np, "big-endian"))
++ fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
++
+ /* Get the addresses and IRQ */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(&pdev->dev, res);
+@@ -718,6 +917,13 @@
+ dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
+ PTR_ERR(esai_priv->fsysclk));
+
++ esai_priv->dmaclk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(esai_priv->dmaclk)) {
++ dev_err(&pdev->dev, "Cannot get dma clock: %ld\n",
++ PTR_ERR(esai_priv->dmaclk));
++ return PTR_ERR(esai_priv->dmaclk);
++ }
++
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
+@@ -734,6 +940,9 @@
+ /* Set a default slot size */
+ esai_priv->slot_width = 32;
+
++ /* Set a default slot number */
++ esai_priv->slots = 2;
++
+ /* Set a default master/slave state */
+ esai_priv->slave_mode = true;
+
+@@ -749,6 +958,11 @@
+ esai_priv->dma_params_tx.addr = res->start + REG_ESAI_ETDR;
+ esai_priv->dma_params_rx.addr = res->start + REG_ESAI_ERDR;
+
++ esai_priv->dma_params_tx.check_xrun = fsl_esai_check_xrun;
++ esai_priv->dma_params_rx.check_xrun = fsl_esai_check_xrun;
++ esai_priv->dma_params_tx.device_reset = fsl_esai_reset;
++ esai_priv->dma_params_rx.device_reset = fsl_esai_reset;
++
+ esai_priv->synchronous =
+ of_property_read_bool(np, "fsl,esai-synchronous");
+
+@@ -785,7 +999,7 @@
+ return ret;
+ }
+
+- ret = imx_pcm_dma_init(pdev);
++ ret = imx_pcm_dma_init(pdev, IMX_ESAI_DMABUF_SIZE);
+ if (ret)
+ dev_err(&pdev->dev, "failed to init imx pcm dma: %d\n", ret);
+
+@@ -794,15 +1008,57 @@
+
+ static const struct of_device_id fsl_esai_dt_ids[] = {
+ { .compatible = "fsl,imx35-esai", },
++ { .compatible = "fsl,vf610-esai", },
+ {}
+ };
+ MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
+
++#if CONFIG_PM_SLEEP
++static int fsl_esai_suspend(struct device *dev)
++{
++ struct fsl_esai *esai = dev_get_drvdata(dev);
++
++ regcache_cache_only(esai->regmap, true);
++ regcache_mark_dirty(esai->regmap);
++
++ return 0;
++}
++
++static int fsl_esai_resume(struct device *dev)
++{
++ struct fsl_esai *esai = dev_get_drvdata(dev);
++ int ret;
++
++ regcache_cache_only(esai->regmap, false);
++
++ /* FIFO reset for safety */
++ regmap_update_bits(esai->regmap, REG_ESAI_TFCR,
++ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
++ regmap_update_bits(esai->regmap, REG_ESAI_RFCR,
++ ESAI_xFCR_xFR, ESAI_xFCR_xFR);
++
++ ret = regcache_sync(esai->regmap);
++ if (ret)
++ return ret;
++
++ /* FIFO reset done */
++ regmap_update_bits(esai->regmap, REG_ESAI_TFCR, ESAI_xFCR_xFR, 0);
++ regmap_update_bits(esai->regmap, REG_ESAI_RFCR, ESAI_xFCR_xFR, 0);
++
++ return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops fsl_esai_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(fsl_esai_suspend, fsl_esai_resume)
++};
++
+ static struct platform_driver fsl_esai_driver = {
+ .probe = fsl_esai_probe,
+ .driver = {
+ .name = "fsl-esai-dai",
+ .owner = THIS_MODULE,
++ .pm = &fsl_esai_pm_ops,
+ .of_match_table = fsl_esai_dt_ids,
+ },
+ };
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_esai.h linux-3.14.72/sound/soc/fsl/fsl_esai.h
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_esai.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_esai.h 2016-06-19 22:11:55.525125571 +0200
+@@ -130,8 +130,8 @@
+ #define ESAI_xFCR_RE_WIDTH 4
+ #define ESAI_xFCR_TE_MASK (((1 << ESAI_xFCR_TE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)
+ #define ESAI_xFCR_RE_MASK (((1 << ESAI_xFCR_RE_WIDTH) - 1) << ESAI_xFCR_xE_SHIFT)
+-#define ESAI_xFCR_TE(x) ((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - ((x + 1) >> 1))) & ESAI_xFCR_TE_MASK)
+-#define ESAI_xFCR_RE(x) ((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - ((x + 1) >> 1))) & ESAI_xFCR_RE_MASK)
++#define ESAI_xFCR_TE(x) ((ESAI_xFCR_TE_MASK >> (ESAI_xFCR_TE_WIDTH - x)) & ESAI_xFCR_TE_MASK)
++#define ESAI_xFCR_RE(x) ((ESAI_xFCR_RE_MASK >> (ESAI_xFCR_RE_WIDTH - x)) & ESAI_xFCR_RE_MASK)
+ #define ESAI_xFCR_xFR_SHIFT 1
+ #define ESAI_xFCR_xFR_MASK (1 << ESAI_xFCR_xFR_SHIFT)
+ #define ESAI_xFCR_xFR (1 << ESAI_xFCR_xFR_SHIFT)
+@@ -272,8 +272,8 @@
+ #define ESAI_xCR_RE_WIDTH 4
+ #define ESAI_xCR_TE_MASK (((1 << ESAI_xCR_TE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)
+ #define ESAI_xCR_RE_MASK (((1 << ESAI_xCR_RE_WIDTH) - 1) << ESAI_xCR_xE_SHIFT)
+-#define ESAI_xCR_TE(x) ((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - ((x + 1) >> 1))) & ESAI_xCR_TE_MASK)
+-#define ESAI_xCR_RE(x) ((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - ((x + 1) >> 1))) & ESAI_xCR_RE_MASK)
++#define ESAI_xCR_TE(x) ((ESAI_xCR_TE_MASK >> (ESAI_xCR_TE_WIDTH - x)) & ESAI_xCR_TE_MASK)
++#define ESAI_xCR_RE(x) ((ESAI_xCR_RE_MASK >> (ESAI_xCR_RE_WIDTH - x)) & ESAI_xCR_RE_MASK)
+
+ /*
+ * Transmit Clock Control Register -- REG_ESAI_TCCR 0xD8
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_hdmi.c linux-3.14.72/sound/soc/fsl/fsl_hdmi.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/fsl_hdmi.c 2016-06-19 22:11:55.525125571 +0200
+@@ -0,0 +1,817 @@
++/*
++ * ALSA SoC HDMI Audio Layer for Freescale i.MX
++ *
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * Some code from patch_hdmi.c
++ * Copyright (c) 2008-2010 Intel Corporation. All rights reserved.
++ * Copyright (c) 2006 ATI Technologies Inc.
++ * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
++ * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/dma-mapping.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/asoundef.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "imx-hdmi.h"
++
++
++static struct mxc_edid_cfg edid_cfg;
++
++static u32 playback_rates[HDMI_MAX_RATES];
++static u32 playback_sample_size[HDMI_MAX_SAMPLE_SIZE];
++static u32 playback_channels[HDMI_MAX_CHANNEL_CONSTRAINTS];
++
++static struct snd_pcm_hw_constraint_list playback_constraint_rates;
++static struct snd_pcm_hw_constraint_list playback_constraint_bits;
++static struct snd_pcm_hw_constraint_list playback_constraint_channels;
++
++#ifdef DEBUG
++static void dumpregs(struct snd_soc_dai *dai)
++{
++ u32 n, cts;
++
++ cts = (hdmi_readb(HDMI_AUD_CTS3) << 16) |
++ (hdmi_readb(HDMI_AUD_CTS2) << 8) |
++ hdmi_readb(HDMI_AUD_CTS1);
++
++ n = (hdmi_readb(HDMI_AUD_N3) << 16) |
++ (hdmi_readb(HDMI_AUD_N2) << 8) |
++ hdmi_readb(HDMI_AUD_N1);
++
++ dev_debug(dai->dev, "HDMI_PHY_CONF0 0x%02x\n",
++ hdmi_readb(HDMI_PHY_CONF0));
++ dev_debug(dai->dev, "HDMI_MC_CLKDIS 0x%02x\n",
++ hdmi_readb(HDMI_MC_CLKDIS));
++ dev_debug(dai->dev, "HDMI_AUD_N[1-3] 0x%06x (%d)\n",
++ n, n);
++ dev_debug(dai->dev, "HDMI_AUD_CTS[1-3] 0x%06x (%d)\n",
++ cts, cts);
++ dev_debug(dai->dev, "HDMI_FC_AUDSCONF 0x%02x\n",
++ hdmi_readb(HDMI_FC_AUDSCONF));
++}
++#else
++static void dumpregs(struct snd_soc_dai *dai) {}
++#endif
++
++enum cea_speaker_placement {
++ FL = (1 << 0), /* Front Left */
++ FC = (1 << 1), /* Front Center */
++ FR = (1 << 2), /* Front Right */
++ FLC = (1 << 3), /* Front Left Center */
++ FRC = (1 << 4), /* Front Right Center */
++ RL = (1 << 5), /* Rear Left */
++ RC = (1 << 6), /* Rear Center */
++ RR = (1 << 7), /* Rear Right */
++ RLC = (1 << 8), /* Rear Left Center */
++ RRC = (1 << 9), /* Rear Right Center */
++ LFE = (1 << 10), /* Low Frequency Effect */
++ FLW = (1 << 11), /* Front Left Wide */
++ FRW = (1 << 12), /* Front Right Wide */
++ FLH = (1 << 13), /* Front Left High */
++ FCH = (1 << 14), /* Front Center High */
++ FRH = (1 << 15), /* Front Right High */
++ TC = (1 << 16), /* Top Center */
++};
++
++/*
++ * EDID SA bits in the CEA Speaker Allocation data block
++ */
++static int edid_speaker_allocation_bits[] = {
++ [0] = FL | FR,
++ [1] = LFE,
++ [2] = FC,
++ [3] = RL | RR,
++ [4] = RC,
++ [5] = FLC | FRC,
++ [6] = RLC | RRC,
++ [7] = FLW | FRW,
++ [8] = FLH | FRH,
++ [9] = TC,
++ [10] = FCH,
++};
++
++struct cea_channel_speaker_allocation {
++ int ca_index;
++ int speakers[8];
++
++ /* Derived values, just for convenience */
++ int channels;
++ int spk_mask;
++};
++
++/*
++ * This is an ordered list!
++ *
++ * The preceding ones have better chances to be selected by
++ * hdmi_channel_allocation().
++ */
++static struct cea_channel_speaker_allocation channel_allocations[] = {
++ /* channel: 7 6 5 4 3 2 1 0 */
++ { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL },},
++ /* 2.1 */
++ { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL },},
++ /* Dolby Surround */
++ { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL },}, /* Prefer FL/FR/RL/RR over FL/FR/LFE/FC */
++ { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL },},
++ { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL },},
++ { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL },},
++ { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL },},
++ { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL },},
++ { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL },},
++ { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL },},
++ /* surround51 */
++ { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL },},
++ /* 6.1 */
++ { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL },},
++ /* surround71 */
++ { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL },},
++ { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL },},
++ { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL },},
++ { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL },},
++ { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL },},
++ { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL },},
++ { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL },},
++ { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL },},
++ { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL },},
++ { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL },},
++ { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL },},
++ { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL },},
++ { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL },},
++};
++
++/* Compute derived values in channel_allocations[] */
++static void init_channel_allocations(void)
++{
++ struct cea_channel_speaker_allocation *p;
++ int i, j;
++
++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
++ p = channel_allocations + i;
++ p->channels = 0;
++ p->spk_mask = 0;
++ for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
++ if (p->speakers[j]) {
++ p->channels++;
++ p->spk_mask |= p->speakers[j];
++ }
++ }
++}
++
++/*
++ * The transformation takes two steps:
++ *
++ * speaker_alloc => (edid_speaker_allocation_bits[]) => spk_mask
++ * spk_mask => (channel_allocations[]) => CA
++ *
++ * TODO: it could select the wrong CA from multiple candidates.
++*/
++static int hdmi_channel_allocation(int channels)
++{
++ int spk_mask = 0, ca = 0, i, tmpchn, tmpspk;
++
++ /* CA defaults to 0 for basic stereo audio */
++ if (channels <= 2)
++ return 0;
++
++ /*
++ * Expand EDID's speaker allocation mask
++ *
++ * EDID tells the speaker mask in a compact(paired) form,
++ * expand EDID's notions to match the ones used by Audio InfoFrame.
++ */
++ for (i = 0; i < ARRAY_SIZE(edid_speaker_allocation_bits); i++) {
++ if (edid_cfg.speaker_alloc & (1 << i))
++ spk_mask |= edid_speaker_allocation_bits[i];
++ }
++
++ /* Search for the first working match in the CA table */
++ for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
++ tmpchn = channel_allocations[i].channels;
++ tmpspk = channel_allocations[i].spk_mask;
++
++ if (channels == tmpchn && (spk_mask & tmpspk) == tmpspk) {
++ ca = channel_allocations[i].ca_index;
++ break;
++ }
++ }
++
++ return ca;
++}
++
++static void hdmi_set_audio_infoframe(unsigned int channels)
++{
++ u8 audiconf0, audiconf2;
++
++ /*
++ * From CEA-861-D spec:
++ * HDMI requires the CT, SS and SF fields to be set to 0 ("Refer
++ * to Stream Header") as these items are carried in the audio stream.
++ *
++ * So we only set the CC and CA fields.
++ */
++ audiconf0 = ((channels - 1) << HDMI_FC_AUDICONF0_CC_OFFSET) &
++ HDMI_FC_AUDICONF0_CC_MASK;
++
++ audiconf2 = hdmi_channel_allocation(channels);
++
++ hdmi_writeb(audiconf0, HDMI_FC_AUDICONF0);
++ hdmi_writeb(0, HDMI_FC_AUDICONF1);
++ hdmi_writeb(audiconf2, HDMI_FC_AUDICONF2);
++ hdmi_writeb(0, HDMI_FC_AUDICONF3);
++}
++
++static int cea_audio_rates[HDMI_MAX_RATES] = {
++ 32000, 44100, 48000, 88200, 96000, 176400, 192000,
++};
++
++static void fsl_hdmi_get_playback_rates(void)
++{
++ int i, count = 0;
++ u8 rates = edid_cfg.sample_rates[0] | edid_cfg.sample_rates[1] |
++ edid_cfg.sample_rates[2] | edid_cfg.sample_rates[3];
++
++ /* Always assume basic audio support */
++ rates |= 0x07;
++
++ for (i = 0 ; i < HDMI_MAX_RATES ; i++)
++ if ((rates & (1 << i)) != 0)
++ playback_rates[count++] = cea_audio_rates[i];
++
++ playback_constraint_rates.list = playback_rates;
++ playback_constraint_rates.count = count;
++
++ for (i = 0 ; i < playback_constraint_rates.count ; i++)
++ pr_debug("%s: constraint = %d Hz\n", __func__, playback_rates[i]);
++}
++
++static void fsl_hdmi_get_playback_sample_size(void)
++{
++ int i = 0;
++ u8 sizes = edid_cfg.sample_sizes[0] | edid_cfg.sample_sizes[1] |
++ edid_cfg.sample_sizes[2] | edid_cfg.sample_sizes[3];
++
++ /* Always assume basic audio support */
++ playback_sample_size[i++] = 16;
++
++ if (sizes & 0x4)
++ playback_sample_size[i++] = 32;
++
++ playback_constraint_bits.list = playback_sample_size;
++ playback_constraint_bits.count = i;
++
++ for (i = 0 ; i < playback_constraint_bits.count ; i++)
++ pr_debug("%s: constraint = %d bits\n", __func__, playback_sample_size[i]);
++}
++
++static void fsl_hdmi_get_playback_channels(void)
++{
++ int channels = 2, i = 0;
++
++ /* Always assume basic audio support */
++ playback_channels[i++] = channels;
++ channels += 2;
++
++ while (i < HDMI_MAX_CHANNEL_CONSTRAINTS &&
++ i < ARRAY_SIZE(edid_cfg.sample_rates) &&
++ edid_cfg.sample_rates[i] && edid_cfg.sample_sizes[i]) {
++ playback_channels[i++] = channels;
++ channels += 2;
++ }
++
++ playback_constraint_channels.list = playback_channels;
++ playback_constraint_channels.count = i;
++
++ for (i = 0 ; i < playback_constraint_channels.count ; i++)
++ pr_debug("%s: constraint = %d channels\n", __func__, playback_channels[i]);
++}
++
++static int fsl_hw_rule_channels_by_rate(struct snd_pcm_hw_params *params,
++ struct snd_pcm_hw_rule *rule)
++{
++ struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
++ struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
++ int i;
++ u8 m;
++ struct snd_interval n;
++
++ if (snd_interval_single(r)) {
++ m = 0;
++ for (i = 0; i < HDMI_MAX_RATES; i++) {
++ if (snd_interval_min(r) == cea_audio_rates[i]) {
++ m = 1 << i;
++ break;
++ }
++ }
++
++ if (m) {
++ snd_interval_any(&n);
++ n.min = n.max = 2;
++
++ for (i = 1; i < ARRAY_SIZE(edid_cfg.sample_rates); i++) {
++ if (!(edid_cfg.sample_rates[i] & m))
++ break;
++ n.max += 2;
++ }
++
++ pr_debug("%s: rate = %d, channels = %d..%d\n",
++ __func__, r->min, n.min, n.max);
++
++ return snd_interval_refine(c, &n);
++ }
++ }
++
++ return 0;
++}
++
++static int fsl_hw_rule_rate_by_channels(struct snd_pcm_hw_params *params,
++ struct snd_pcm_hw_rule *rule)
++{
++ struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
++ struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
++ int i, rate;
++ u8 m;
++ struct snd_interval n;
++
++ if (snd_interval_single(c)) {
++ i = (snd_interval_min(c) - 1) / 2;
++ m = edid_cfg.sample_rates[i];
++
++ if (m) {
++ snd_interval_any(&n);
++ n.min = 192000;
++ n.max = 32000;
++
++ for (i = 0; i < HDMI_MAX_RATES; i++, m >>= 1) {
++ if (!(m & 1))
++ continue;
++
++ rate = cea_audio_rates[i];
++ if ( rate < n.min)
++ n.min = rate;
++ if ( rate > n.max)
++ n.max = rate;
++ }
++
++ pr_debug("%s: channels = %d, rates = %d..%d\n",
++ __func__, c->min, n.min, n.max);
++
++ return snd_interval_refine(r, &n);
++ }
++ }
++
++ return 0;
++}
++
++static int fsl_hdmi_update_constraints(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ int edid_status, ret;
++
++ edid_status = hdmi_get_edid_cfg(&edid_cfg);
++
++ if (edid_status && !edid_cfg.hdmi_cap)
++ return -1;
++
++ fsl_hdmi_get_playback_rates();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
++ &playback_constraint_rates);
++ if (ret < 0)
++ return ret;
++
++ fsl_hdmi_get_playback_sample_size();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
++ &playback_constraint_bits);
++ if (ret < 0)
++ return ret;
++
++ fsl_hdmi_get_playback_channels();
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
++ &playback_constraint_channels);
++ if (ret < 0)
++ return ret;
++
++ ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
++ if (ret < 0)
++ return ret;
++
++ ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
++ fsl_hw_rule_channels_by_rate, NULL,
++ SNDRV_PCM_HW_PARAM_RATE, -1);
++ if (ret < 0)
++ return ret;
++
++ ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
++ fsl_hw_rule_rate_by_channels, NULL,
++ SNDRV_PCM_HW_PARAM_CHANNELS, -1);
++ if (ret < 0)
++ return ret;
++
++ return 0;
++}
++
++static int fsl_hdmi_soc_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct imx_hdmi *hdmi_data = snd_soc_dai_get_drvdata(dai);
++ int ret;
++
++ ret = fsl_hdmi_update_constraints(substream);
++ if (ret < 0)
++ return ret;
++
++ clk_prepare_enable(hdmi_data->mipi_core_clk);
++ clk_prepare_enable(hdmi_data->isfr_clk);
++ clk_prepare_enable(hdmi_data->iahb_clk);
++
++ dev_dbg(dai->dev, "%s hdmi clks: mipi_core: %d isfr:%d iahb:%d\n", __func__,
++ (int)clk_get_rate(hdmi_data->mipi_core_clk),
++ (int)clk_get_rate(hdmi_data->isfr_clk),
++ (int)clk_get_rate(hdmi_data->iahb_clk));
++
++ /* Indicates the subpacket represents a flatline sample */
++ hdmi_audio_writeb(FC_AUDSCONF, AUD_PACKET_SAMPFIT, 0x0);
++
++ return 0;
++}
++
++static void fsl_hdmi_soc_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct imx_hdmi *hdmi_data = snd_soc_dai_get_drvdata(dai);
++
++ clk_disable_unprepare(hdmi_data->iahb_clk);
++ clk_disable_unprepare(hdmi_data->isfr_clk);
++ clk_disable_unprepare(hdmi_data->mipi_core_clk);
++}
++
++static int fsl_hdmi_soc_prepare(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++
++ hdmi_set_audio_infoframe(runtime->channels);
++ hdmi_audio_writeb(FC_AUDSCONF, AUD_PACKET_LAYOUT,
++ (runtime->channels > 2) ? 0x1 : 0x0);
++ hdmi_set_sample_rate(runtime->rate);
++ dumpregs(dai);
++
++ return 0;
++}
++
++static struct snd_soc_dai_ops fsl_hdmi_soc_dai_ops = {
++ .startup = fsl_hdmi_soc_startup,
++ .shutdown = fsl_hdmi_soc_shutdown,
++ .prepare = fsl_hdmi_soc_prepare,
++};
++
++/* IEC60958 status functions */
++static int fsl_hdmi_iec_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
++ uinfo->count = 1;
++
++ return 0;
++}
++
++
++static int fsl_hdmi_iec_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++
++ for (i = 0 ; i < 6 ; i++)
++ uvalue->value.iec958.status[i] = iec_header.status[i];
++
++ return 0;
++}
++
++static int fsl_hdmi_iec_put(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++
++ /* Do not allow professional mode */
++ if (uvalue->value.iec958.status[0] & IEC958_AES0_PROFESSIONAL)
++ return -EPERM;
++
++ for (i = 0 ; i < 6 ; i++) {
++ iec_header.status[i] = uvalue->value.iec958.status[i];
++ pr_debug("%s status[%d]=0x%02x\n", __func__, i, iec_header.status[i]);
++ }
++
++ return 0;
++}
++
++static int fsl_hdmi_channels_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ hdmi_get_edid_cfg(&edid_cfg);
++ fsl_hdmi_get_playback_channels();
++
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = playback_constraint_channels.count;
++
++ return 0;
++}
++
++
++static int fsl_hdmi_channels_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++ hdmi_get_edid_cfg(&edid_cfg);
++ fsl_hdmi_get_playback_channels();
++
++ for (i = 0 ; i < playback_constraint_channels.count ; i++)
++ uvalue->value.integer.value[i] = playback_channels[i];
++
++ return 0;
++}
++
++static int fsl_hdmi_rates_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ hdmi_get_edid_cfg(&edid_cfg);
++ fsl_hdmi_get_playback_rates();
++
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = playback_constraint_rates.count;
++
++ return 0;
++}
++
++static int fsl_hdmi_rates_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++ hdmi_get_edid_cfg(&edid_cfg);
++ fsl_hdmi_get_playback_rates();
++
++ for (i = 0 ; i < playback_constraint_rates.count ; i++)
++ uvalue->value.integer.value[i] = playback_rates[i];
++
++ return 0;
++}
++
++static int fsl_hdmi_formats_info(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_info *uinfo)
++{
++ hdmi_get_edid_cfg(&edid_cfg);
++ fsl_hdmi_get_playback_sample_size();
++
++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
++ uinfo->count = playback_constraint_bits.count;
++
++ return 0;
++}
++
++static int fsl_hdmi_formats_get(struct snd_kcontrol *kcontrol,
++ struct snd_ctl_elem_value *uvalue)
++{
++ int i;
++ hdmi_get_edid_cfg(&edid_cfg);
++ fsl_hdmi_get_playback_sample_size();
++
++ for (i = 0 ; i < playback_constraint_bits.count ; i++)
++ uvalue->value.integer.value[i] = playback_sample_size[i];
++
++ return 0;
++}
++
++static struct snd_kcontrol_new fsl_hdmi_ctrls[] = {
++ /* Status cchanel controller */
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_WRITE |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_hdmi_iec_info,
++ .get = fsl_hdmi_iec_get,
++ .put = fsl_hdmi_iec_put,
++ },
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "HDMI Support Channels",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_hdmi_channels_info,
++ .get = fsl_hdmi_channels_get,
++ },
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "HDMI Support Rates",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_hdmi_rates_info,
++ .get = fsl_hdmi_rates_get,
++ },
++ {
++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
++ .name = "HDMI Support Formats",
++ .access = SNDRV_CTL_ELEM_ACCESS_READ |
++ SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++ .info = fsl_hdmi_formats_info,
++ .get = fsl_hdmi_formats_get,
++ },
++};
++
++static int fsl_hdmi_soc_dai_probe(struct snd_soc_dai *dai)
++{
++ int ret;
++
++ init_channel_allocations();
++
++ ret = snd_soc_add_dai_controls(dai, fsl_hdmi_ctrls,
++ ARRAY_SIZE(fsl_hdmi_ctrls));
++ if (ret)
++ dev_warn(dai->dev, "failed to add dai controls\n");
++
++ return 0;
++}
++
++static struct snd_soc_dai_driver fsl_hdmi_dai = {
++ .probe = &fsl_hdmi_soc_dai_probe,
++ .playback = {
++ .channels_min = 2,
++ .channels_max = 8,
++ .rates = MXC_HDMI_RATES_PLAYBACK,
++ .formats = MXC_HDMI_FORMATS_PLAYBACK,
++ },
++ .ops = &fsl_hdmi_soc_dai_ops,
++};
++
++static const struct snd_soc_component_driver fsl_hdmi_component = {
++ .name = "fsl-hdmi",
++};
++
++static int fsl_hdmi_dai_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct imx_hdmi *hdmi_data;
++ int ret = 0;
++
++ if (!np)
++ return -ENODEV;
++
++ if (!hdmi_get_registered()) {
++ dev_err(&pdev->dev, "failed to probe. Load HDMI-video first.\n");
++ return -ENOMEM;
++ }
++
++ hdmi_data = devm_kzalloc(&pdev->dev, sizeof(*hdmi_data), GFP_KERNEL);
++ if (!hdmi_data) {
++ dev_err(&pdev->dev, "failed to alloc hdmi_data\n");
++ return -ENOMEM;
++ }
++
++ hdmi_data->pdev = pdev;
++
++ memcpy(&hdmi_data->cpu_dai_drv, &fsl_hdmi_dai, sizeof(fsl_hdmi_dai));
++ hdmi_data->cpu_dai_drv.name = np->name;
++
++ hdmi_data->mipi_core_clk = devm_clk_get(&pdev->dev, "mipi_core");
++ if (IS_ERR(hdmi_data->mipi_core_clk)) {
++ ret = PTR_ERR(hdmi_data->mipi_core_clk);
++ dev_err(&pdev->dev, "failed to get mipi core clk: %d\n", ret);
++ return -EINVAL;
++ }
++
++ hdmi_data->isfr_clk = devm_clk_get(&pdev->dev, "hdmi_isfr");
++ if (IS_ERR(hdmi_data->isfr_clk)) {
++ ret = PTR_ERR(hdmi_data->isfr_clk);
++ dev_err(&pdev->dev, "failed to get HDMI isfr clk: %d\n", ret);
++ return -EINVAL;
++ }
++
++ hdmi_data->iahb_clk = devm_clk_get(&pdev->dev, "hdmi_iahb");
++ if (IS_ERR(hdmi_data->iahb_clk)) {
++ ret = PTR_ERR(hdmi_data->iahb_clk);
++ dev_err(&pdev->dev, "failed to get HDMI ahb clk: %d\n", ret);
++ return -EINVAL;
++ }
++
++ dev_set_drvdata(&pdev->dev, hdmi_data);
++ ret = snd_soc_register_component(&pdev->dev, &fsl_hdmi_component,
++ &hdmi_data->cpu_dai_drv, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "register DAI failed\n");
++ return ret;
++ }
++
++ hdmi_data->codec_dev = platform_device_register_simple(
++ "hdmi-audio-codec", -1, NULL, 0);
++ if (IS_ERR(hdmi_data->codec_dev)) {
++ dev_err(&pdev->dev, "failed to register HDMI audio codec\n");
++ ret = PTR_ERR(hdmi_data->codec_dev);
++ goto fail;
++ }
++
++ hdmi_data->dma_dev = platform_device_alloc("imx-hdmi-audio", -1);
++ if (IS_ERR(hdmi_data->dma_dev)) {
++ ret = PTR_ERR(hdmi_data->dma_dev);
++ goto fail_dma;
++ }
++
++ platform_set_drvdata(hdmi_data->dma_dev, hdmi_data);
++
++ ret = platform_device_add(hdmi_data->dma_dev);
++ if (ret) {
++ platform_device_put(hdmi_data->dma_dev);
++ goto fail_dma;
++ }
++
++ return 0;
++
++fail_dma:
++ platform_device_unregister(hdmi_data->codec_dev);
++fail:
++ snd_soc_unregister_component(&pdev->dev);
++
++ return ret;
++}
++
++static int fsl_hdmi_dai_remove(struct platform_device *pdev)
++{
++ struct imx_hdmi *hdmi_data = platform_get_drvdata(pdev);
++
++ platform_device_unregister(hdmi_data->dma_dev);
++ platform_device_unregister(hdmi_data->codec_dev);
++ snd_soc_unregister_component(&pdev->dev);
++
++ return 0;
++}
++
++static const struct of_device_id fsl_hdmi_dai_dt_ids[] = {
++ { .compatible = "fsl,imx6dl-hdmi-audio", },
++ { .compatible = "fsl,imx6q-hdmi-audio", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, fsl_hdmi_dai_dt_ids);
++
++static struct platform_driver fsl_hdmi_driver = {
++ .probe = fsl_hdmi_dai_probe,
++ .remove = fsl_hdmi_dai_remove,
++ .driver = {
++ .name = "fsl-hdmi-dai",
++ .owner = THIS_MODULE,
++ .of_match_table = fsl_hdmi_dai_dt_ids,
++ },
++};
++module_platform_driver(fsl_hdmi_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX HDMI TX DAI");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:fsl-hdmi-dai");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_sai.c linux-3.14.72/sound/soc/fsl/fsl_sai.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_sai.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_sai.c 2016-06-19 22:11:55.525125571 +0200
+@@ -1,7 +1,7 @@
+ /*
+ * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
+ *
+- * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ * Copyright 2012-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software, you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+@@ -15,54 +15,123 @@
+ #include <linux/dmaengine.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
++#include <linux/regmap.h>
+ #include <linux/slab.h>
+ #include <sound/core.h>
+ #include <sound/dmaengine_pcm.h>
+ #include <sound/pcm_params.h>
+
+ #include "fsl_sai.h"
++#include "imx-pcm.h"
+
+-static inline u32 sai_readl(struct fsl_sai *sai,
+- const void __iomem *addr)
++#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
++ FSL_SAI_CSR_FEIE)
++
++static irqreturn_t fsl_sai_isr(int irq, void *devid)
+ {
+- u32 val;
++ struct fsl_sai *sai = (struct fsl_sai *)devid;
++ struct device *dev = &sai->pdev->dev;
++ u32 flags, xcsr, mask;
++ bool irq_none = true;
++
++ /*
++ * Both IRQ status bits and IRQ mask bits are in the xCSR but
++ * different shifts. And we here create a mask only for those
++ * IRQs that we activated.
++ */
++ mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
++
++ /* Tx IRQ */
++ regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
++ flags = xcsr & mask;
++
++ if (flags)
++ irq_none = false;
++ else
++ goto irq_rx;
++
++ if (flags & FSL_SAI_CSR_WSF)
++ dev_dbg(dev, "isr: Start of Tx word detected\n");
++
++ if (flags & FSL_SAI_CSR_SEF)
++ dev_warn(dev, "isr: Tx Frame sync error detected\n");
++
++ if (flags & FSL_SAI_CSR_FEF) {
++ dev_warn(dev, "isr: Transmit underrun detected\n");
++ /* FIFO reset for safety */
++ xcsr |= FSL_SAI_CSR_FR;
++ }
++
++ if (flags & FSL_SAI_CSR_FWF)
++ dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
++
++ if (flags & FSL_SAI_CSR_FRF)
++ dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
++
++ flags &= FSL_SAI_CSR_xF_W_MASK;
++ xcsr &= ~FSL_SAI_CSR_xF_MASK;
++
++ if (flags)
++ regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
+
+- val = __raw_readl(addr);
++irq_rx:
++ /* Rx IRQ */
++ regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
++ flags = xcsr & mask;
+
+- if (likely(sai->big_endian_regs))
+- val = be32_to_cpu(val);
++ if (flags)
++ irq_none = false;
+ else
+- val = le32_to_cpu(val);
+- rmb();
++ goto out;
+
+- return val;
++ if (flags & FSL_SAI_CSR_WSF)
++ dev_dbg(dev, "isr: Start of Rx word detected\n");
++
++ if (flags & FSL_SAI_CSR_SEF)
++ dev_warn(dev, "isr: Rx Frame sync error detected\n");
++
++ if (flags & FSL_SAI_CSR_FEF) {
++ dev_warn(dev, "isr: Receive overflow detected\n");
++ /* FIFO reset for safety */
++ xcsr |= FSL_SAI_CSR_FR;
++ }
++
++ if (flags & FSL_SAI_CSR_FWF)
++ dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
++
++ if (flags & FSL_SAI_CSR_FRF)
++ dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
++
++ flags &= FSL_SAI_CSR_xF_W_MASK;
++ xcsr &= ~FSL_SAI_CSR_xF_MASK;
++
++ if (flags)
++ regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
++
++out:
++ if (irq_none)
++ return IRQ_NONE;
++ else
++ return IRQ_HANDLED;
+ }
+
+-static inline void sai_writel(struct fsl_sai *sai,
+- u32 val, void __iomem *addr)
++static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
++ u32 rx_mask, int slots, int slot_width)
+ {
+- wmb();
+- if (likely(sai->big_endian_regs))
+- val = cpu_to_be32(val);
+- else
+- val = cpu_to_le32(val);
++ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+
+- __raw_writel(val, addr);
++ sai->slots = slots;
++ sai->slot_width = slot_width;
++
++ return 0;
+ }
+
+ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
+ int clk_id, unsigned int freq, int fsl_dir)
+ {
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+- u32 val_cr2, reg_cr2;
+-
+- if (fsl_dir == FSL_FMT_TRANSMITTER)
+- reg_cr2 = FSL_SAI_TCR2;
+- else
+- reg_cr2 = FSL_SAI_RCR2;
+-
+- val_cr2 = sai_readl(sai, sai->base + reg_cr2);
+- val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK;
++ bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
++ u32 val_cr2 = 0;
+
+ switch (clk_id) {
+ case FSL_SAI_CLK_BUS:
+@@ -81,7 +150,8 @@
+ return -EINVAL;
+ }
+
+- sai_writel(sai, val_cr2, sai->base + reg_cr2);
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
++ FSL_SAI_CR2_MSEL_MASK, val_cr2);
+
+ return 0;
+ }
+@@ -89,32 +159,22 @@
+ static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
+ int clk_id, unsigned int freq, int dir)
+ {
+- struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret;
+
+ if (dir == SND_SOC_CLOCK_IN)
+ return 0;
+
+- ret = clk_prepare_enable(sai->clk);
+- if (ret)
+- return ret;
+-
+ ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
+ FSL_FMT_TRANSMITTER);
+ if (ret) {
+ dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
+- goto err_clk;
++ return ret;
+ }
+
+ ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
+ FSL_FMT_RECEIVER);
+- if (ret) {
++ if (ret)
+ dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
+- goto err_clk;
+- }
+-
+-err_clk:
+- clk_disable_unprepare(sai->clk);
+
+ return ret;
+ }
+@@ -123,97 +183,188 @@
+ unsigned int fmt, int fsl_dir)
+ {
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+- u32 val_cr2, val_cr4, reg_cr2, reg_cr4;
+-
+- if (fsl_dir == FSL_FMT_TRANSMITTER) {
+- reg_cr2 = FSL_SAI_TCR2;
+- reg_cr4 = FSL_SAI_TCR4;
+- } else {
+- reg_cr2 = FSL_SAI_RCR2;
+- reg_cr4 = FSL_SAI_RCR4;
+- }
+-
+- val_cr2 = sai_readl(sai, sai->base + reg_cr2);
+- val_cr4 = sai_readl(sai, sai->base + reg_cr4);
++ bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
++ u32 val_cr2 = 0, val_cr4 = 0;
+
+- if (sai->big_endian_data)
+- val_cr4 &= ~FSL_SAI_CR4_MF;
+- else
++ if (!sai->is_lsb_first)
+ val_cr4 |= FSL_SAI_CR4_MF;
+
++ /* DAI mode */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
++ /*
++ * Frame low, 1clk before data, one word length for frame sync,
++ * frame sync starts one serial clock cycle earlier,
++ * that is, together with the last bit of the previous
++ * data word.
++ */
++ val_cr2 |= FSL_SAI_CR2_BCP;
++ val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
++ break;
++ case SND_SOC_DAIFMT_LEFT_J:
++ /*
++ * Frame high, one word length for frame sync,
++ * frame sync asserts with the first bit of the frame.
++ */
++ val_cr2 |= FSL_SAI_CR2_BCP;
++ break;
++ case SND_SOC_DAIFMT_DSP_A:
++ /*
++ * Frame high, 1clk before data, one bit for frame sync,
++ * frame sync starts one serial clock cycle earlier,
++ * that is, together with the last bit of the previous
++ * data word.
++ */
++ val_cr2 |= FSL_SAI_CR2_BCP;
+ val_cr4 |= FSL_SAI_CR4_FSE;
++ sai->is_dsp_mode = true;
+ break;
++ case SND_SOC_DAIFMT_DSP_B:
++ /*
++ * Frame high, one bit for frame sync,
++ * frame sync asserts with the first bit of the frame.
++ */
++ val_cr2 |= FSL_SAI_CR2_BCP;
++ sai->is_dsp_mode = true;
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ /* To be done */
+ default:
+ return -EINVAL;
+ }
+
++ /* DAI clock inversion */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_IB_IF:
+- val_cr4 |= FSL_SAI_CR4_FSP;
+- val_cr2 &= ~FSL_SAI_CR2_BCP;
++ /* Invert both clocks */
++ val_cr2 ^= FSL_SAI_CR2_BCP;
++ val_cr4 ^= FSL_SAI_CR4_FSP;
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+- val_cr4 &= ~FSL_SAI_CR4_FSP;
+- val_cr2 &= ~FSL_SAI_CR2_BCP;
++ /* Invert bit clock */
++ val_cr2 ^= FSL_SAI_CR2_BCP;
+ break;
+ case SND_SOC_DAIFMT_NB_IF:
+- val_cr4 |= FSL_SAI_CR4_FSP;
+- val_cr2 |= FSL_SAI_CR2_BCP;
++ /* Invert frame clock */
++ val_cr4 ^= FSL_SAI_CR4_FSP;
+ break;
+ case SND_SOC_DAIFMT_NB_NF:
+- val_cr4 &= ~FSL_SAI_CR4_FSP;
+- val_cr2 |= FSL_SAI_CR2_BCP;
++ /* Nothing to do for both normal cases */
+ break;
+ default:
+ return -EINVAL;
+ }
+
++ sai->is_slave_mode = false;
++
++ /* DAI clock master masks */
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
+ val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+- val_cr2 &= ~FSL_SAI_CR2_BCD_MSTR;
+- val_cr4 &= ~FSL_SAI_CR4_FSD_MSTR;
++ sai->is_slave_mode = true;
++ break;
++ case SND_SOC_DAIFMT_CBS_CFM:
++ val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
++ break;
++ case SND_SOC_DAIFMT_CBM_CFS:
++ val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
++ sai->is_slave_mode = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+- sai_writel(sai, val_cr2, sai->base + reg_cr2);
+- sai_writel(sai, val_cr4, sai->base + reg_cr4);
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
++ FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
++ FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
++ FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
+
+ return 0;
+ }
+
+ static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
+ {
+- struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ int ret;
+
+- ret = clk_prepare_enable(sai->clk);
+- if (ret)
+- return ret;
+-
+ ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
+ if (ret) {
+ dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
+- goto err_clk;
++ return ret;
+ }
+
+ ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
+- if (ret) {
++ if (ret)
+ dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
+- goto err_clk;
++
++ return ret;
++}
++
++static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
++{
++ struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
++ unsigned long clk_rate;
++ u32 savediv = 0, ratio, savesub = freq;
++ u32 id;
++ int ret = 0;
++
++ /* Don't apply to slave mode */
++ if (sai->is_slave_mode)
++ return 0;
++
++ for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
++
++ clk_rate = clk_get_rate(sai->mclk_clk[id]);
++ if (!clk_rate)
++ continue;
++
++ ratio = clk_rate / freq;
++
++ ret = clk_rate - ratio * freq;
++
++ /* Drop the source that can not be divided into the required rate */
++ if (ret != 0 && clk_rate / ret < 1000)
++ continue;
++
++ dev_dbg(dai->dev, "ratio %d for freq %dHz based on clock %ldHz\n",
++ ratio, freq, clk_rate);
++
++ ratio /= 2;
++ if (ratio == 0 && ratio > 256)
++ continue;
++
++ if (ret < savesub) {
++ savediv = ratio;
++ sai->mclk_id = id;
++ savesub = ret;
++ }
++ }
++
++ if (savediv == 0) {
++ dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
++ tx ? 'T' : 'R', ret);
++ return -EINVAL;
+ }
+
+-err_clk:
+- clk_disable_unprepare(sai->clk);
++ if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
++ regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_MSEL_MASK,
++ FSL_SAI_CR2_MSEL(sai->mclk_id));
++ regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
++ FSL_SAI_CR2_DIV_MASK, savediv - 1);
++ } else {
++ regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_MSEL_MASK,
++ FSL_SAI_CR2_MSEL(sai->mclk_id));
++ regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
++ FSL_SAI_CR2_DIV_MASK, savediv - 1);
++ }
+
+- return ret;
++ dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
++ sai->mclk_id, savediv, savesub);
++
++ return 0;
+ }
+
+ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
+@@ -221,104 +372,144 @@
+ struct snd_soc_dai *cpu_dai)
+ {
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+- u32 val_cr4, val_cr5, val_mr, reg_cr4, reg_cr5, reg_mr;
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
+ unsigned int channels = params_channels(params);
+ u32 word_width = snd_pcm_format_width(params_format(params));
++ u32 val_cr4 = 0, val_cr5 = 0;
++ int ret;
+
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- reg_cr4 = FSL_SAI_TCR4;
+- reg_cr5 = FSL_SAI_TCR5;
+- reg_mr = FSL_SAI_TMR;
+- } else {
+- reg_cr4 = FSL_SAI_RCR4;
+- reg_cr5 = FSL_SAI_RCR5;
+- reg_mr = FSL_SAI_RMR;
+- }
++ if (!sai->is_slave_mode) {
++ ret = fsl_sai_set_bclk(cpu_dai, tx, sai->slots * word_width * params_rate(params));
++ if (ret)
++ return ret;
++
++ /* Do not enable the clock if it is already enabled */
++ if (!(sai->mclk_streams & BIT(substream->stream))) {
++ ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id]);
++ if (ret)
++ return ret;
+
+- val_cr4 = sai_readl(sai, sai->base + reg_cr4);
+- val_cr4 &= ~FSL_SAI_CR4_SYWD_MASK;
+- val_cr4 &= ~FSL_SAI_CR4_FRSZ_MASK;
++ sai->mclk_streams |= BIT(substream->stream);
++ }
+
+- val_cr5 = sai_readl(sai, sai->base + reg_cr5);
+- val_cr5 &= ~FSL_SAI_CR5_WNW_MASK;
+- val_cr5 &= ~FSL_SAI_CR5_W0W_MASK;
+- val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
++ }
++
++ if (!sai->is_dsp_mode)
++ val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
+
+- val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
+ val_cr5 |= FSL_SAI_CR5_WNW(word_width);
+ val_cr5 |= FSL_SAI_CR5_W0W(word_width);
+
+- val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;
+- if (sai->big_endian_data)
++ if (sai->is_lsb_first)
+ val_cr5 |= FSL_SAI_CR5_FBT(0);
+ else
+ val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
+
+- val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
+- val_mr = ~0UL - ((1 << channels) - 1);
++ val_cr4 |= FSL_SAI_CR4_FRSZ(sai->slots);
+
+- sai_writel(sai, val_cr4, sai->base + reg_cr4);
+- sai_writel(sai, val_cr5, sai->base + reg_cr5);
+- sai_writel(sai, val_mr, sai->base + reg_mr);
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
++ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
++ val_cr4);
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
++ FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
++ FSL_SAI_CR5_FBT_MASK, val_cr5);
++ regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
+
+ return 0;
+ }
+
+-static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
++static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+ {
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+- u32 tcsr, rcsr, val_cr2, val_cr3, reg_cr3;
+
+- val_cr2 = sai_readl(sai, sai->base + FSL_SAI_TCR2);
+- val_cr2 &= ~FSL_SAI_CR2_SYNC;
+- sai_writel(sai, val_cr2, sai->base + FSL_SAI_TCR2);
+-
+- val_cr2 = sai_readl(sai, sai->base + FSL_SAI_RCR2);
+- val_cr2 |= FSL_SAI_CR2_SYNC;
+- sai_writel(sai, val_cr2, sai->base + FSL_SAI_RCR2);
+-
+- tcsr = sai_readl(sai, sai->base + FSL_SAI_TCSR);
+- rcsr = sai_readl(sai, sai->base + FSL_SAI_RCSR);
+-
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- tcsr |= FSL_SAI_CSR_FRDE;
+- rcsr &= ~FSL_SAI_CSR_FRDE;
+- reg_cr3 = FSL_SAI_TCR3;
+- } else {
+- rcsr |= FSL_SAI_CSR_FRDE;
+- tcsr &= ~FSL_SAI_CSR_FRDE;
+- reg_cr3 = FSL_SAI_RCR3;
++ if (!sai->is_slave_mode &&
++ sai->mclk_streams & BIT(substream->stream)) {
++ clk_disable_unprepare(sai->mclk_clk[sai->mclk_id]);
++ sai->mclk_streams &= ~BIT(substream->stream);
+ }
+
+- val_cr3 = sai_readl(sai, sai->base + reg_cr3);
++ return 0;
++}
++
+
++static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++ u8 channels = substream->runtime->channels;
++ u32 xcsr, count = 100;
++ int i;
++
++ /*
++ * Asynchronous mode: Clear SYNC for both Tx and Rx.
++ * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
++ * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
++ */
++ regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0);
++ regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
++ sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
++
++ /*
++ * It is recommended that the transmitter is the last enabled
++ * and the first disabled.
++ */
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+- tcsr |= FSL_SAI_CSR_TERE;
+- rcsr |= FSL_SAI_CSR_TERE;
+- val_cr3 |= FSL_SAI_CR3_TRCE;
+-
+- sai_writel(sai, val_cr3, sai->base + reg_cr3);
+- sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR);
+- sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR);
+- break;
++ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
++ FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
+
++ for (i = 0; tx && i < channels; i++)
++ regmap_write(sai->regmap, FSL_SAI_TDR, 0x0);
++ if (tx)
++ udelay(10);
++
++ regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
++ FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
++ regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
++ FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
++
++ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
++ FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
++ break;
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+- if (!(cpu_dai->playback_active || cpu_dai->capture_active)) {
+- tcsr &= ~FSL_SAI_CSR_TERE;
+- rcsr &= ~FSL_SAI_CSR_TERE;
++ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
++ FSL_SAI_CSR_FRDE, 0);
++ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
++ FSL_SAI_CSR_xIE_MASK, 0);
++
++ /* Check if the opposite FRDE is also disabled */
++ regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
++ if (!(xcsr & FSL_SAI_CSR_FRDE)) {
++ /* Disable both directions and reset their FIFOs */
++ regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
++ FSL_SAI_CSR_TERE, 0);
++ regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
++ FSL_SAI_CSR_TERE, 0);
++
++ /* TERE will remain set till the end of current frame */
++ do {
++ udelay(10);
++ regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
++ } while (--count && xcsr & FSL_SAI_CSR_TERE);
++
++ regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
++ FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
++ regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
++ FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
++
++ /* Software Reset for both Tx and Rx */
++ regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
++ regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
++ /* Clear SR bit to finish the reset */
++ regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
++ regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
+ }
+-
+- val_cr3 &= ~FSL_SAI_CR3_TRCE;
+-
+- sai_writel(sai, tcsr, sai->base + FSL_SAI_TCSR);
+- sai_writel(sai, rcsr, sai->base + FSL_SAI_RCSR);
+- sai_writel(sai, val_cr3, sai->base + reg_cr3);
+ break;
+ default:
+ return -EINVAL;
+@@ -331,22 +522,42 @@
+ struct snd_soc_dai *cpu_dai)
+ {
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++ struct device *dev = &sai->pdev->dev;
++ int ret;
+
+- return clk_prepare_enable(sai->clk);
++ ret = clk_prepare_enable(sai->bus_clk);
++ if (ret) {
++ dev_err(dev, "failed to enable bus clock: %d\n", ret);
++ return ret;
++ }
++
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR1(tx), FSL_SAI_CR1_RFW_MASK,
++ tx ? (FSL_SAI_MAXBURST_TX * 2) : (FSL_SAI_MAXBURST_RX - 1));
++
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
++ FSL_SAI_CR3_TRCE);
++
++ return 0;
+ }
+
+ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *cpu_dai)
+ {
+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++
++ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
+
+- clk_disable_unprepare(sai->clk);
++ clk_disable_unprepare(sai->bus_clk);
+ }
+
+ static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
+ .set_sysclk = fsl_sai_set_dai_sysclk,
+ .set_fmt = fsl_sai_set_dai_fmt,
++ .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
+ .hw_params = fsl_sai_hw_params,
++ .hw_free = fsl_sai_hw_free,
+ .trigger = fsl_sai_trigger,
+ .startup = fsl_sai_startup,
+ .shutdown = fsl_sai_shutdown,
+@@ -355,18 +566,13 @@
+ static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
+ {
+ struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
+- int ret;
+
+- ret = clk_prepare_enable(sai->clk);
+- if (ret)
+- return ret;
+-
+- sai_writel(sai, 0x0, sai->base + FSL_SAI_RCSR);
+- sai_writel(sai, 0x0, sai->base + FSL_SAI_TCSR);
+- sai_writel(sai, FSL_SAI_MAXBURST_TX * 2, sai->base + FSL_SAI_TCR1);
+- sai_writel(sai, FSL_SAI_MAXBURST_RX - 1, sai->base + FSL_SAI_RCR1);
+-
+- clk_disable_unprepare(sai->clk);
++ /* Software Reset for both Tx and Rx */
++ regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
++ regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
++ /* Clear SR bit to finish the reset */
++ regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
++ regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
+
+ snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
+ &sai->dma_params_rx);
+@@ -379,12 +585,14 @@
+ static struct snd_soc_dai_driver fsl_sai_dai = {
+ .probe = fsl_sai_dai_probe,
+ .playback = {
++ .stream_name = "CPU-Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_96000,
+ .formats = FSL_SAI_FORMATS,
+ },
+ .capture = {
++ .stream_name = "CPU-Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_96000,
+@@ -397,26 +605,179 @@
+ .name = "fsl-sai",
+ };
+
++static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case FSL_SAI_TCSR:
++ case FSL_SAI_TCR1:
++ case FSL_SAI_TCR2:
++ case FSL_SAI_TCR3:
++ case FSL_SAI_TCR4:
++ case FSL_SAI_TCR5:
++ case FSL_SAI_TFR:
++ case FSL_SAI_TMR:
++ case FSL_SAI_RCSR:
++ case FSL_SAI_RCR1:
++ case FSL_SAI_RCR2:
++ case FSL_SAI_RCR3:
++ case FSL_SAI_RCR4:
++ case FSL_SAI_RCR5:
++ case FSL_SAI_RDR:
++ case FSL_SAI_RFR:
++ case FSL_SAI_RMR:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case FSL_SAI_TCSR:
++ case FSL_SAI_RCSR:
++ case FSL_SAI_TFR:
++ case FSL_SAI_RFR:
++ case FSL_SAI_TDR:
++ case FSL_SAI_RDR:
++ return true;
++ default:
++ return false;
++ }
++
++}
++
++static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case FSL_SAI_TCSR:
++ case FSL_SAI_TCR1:
++ case FSL_SAI_TCR2:
++ case FSL_SAI_TCR3:
++ case FSL_SAI_TCR4:
++ case FSL_SAI_TCR5:
++ case FSL_SAI_TDR:
++ case FSL_SAI_TMR:
++ case FSL_SAI_RCSR:
++ case FSL_SAI_RCR1:
++ case FSL_SAI_RCR2:
++ case FSL_SAI_RCR3:
++ case FSL_SAI_RCR4:
++ case FSL_SAI_RCR5:
++ case FSL_SAI_RMR:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static const struct regmap_config fsl_sai_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++
++ .max_register = FSL_SAI_RMR,
++ .readable_reg = fsl_sai_readable_reg,
++ .volatile_reg = fsl_sai_volatile_reg,
++ .writeable_reg = fsl_sai_writeable_reg,
++ .cache_type = REGCACHE_RBTREE,
++};
++
+ static int fsl_sai_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+ struct fsl_sai *sai;
+ struct resource *res;
+- int ret;
++ void __iomem *base;
++ char tmp[8];
++ int irq, ret, i;
+
+ sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
+ if (!sai)
+ return -ENOMEM;
+
++ sai->pdev = pdev;
++
++ if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
++ sai->sai_on_imx = true;
++
++ sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
++
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+- sai->base = devm_ioremap_resource(&pdev->dev, res);
+- if (IS_ERR(sai->base))
+- return PTR_ERR(sai->base);
+-
+- sai->clk = devm_clk_get(&pdev->dev, "sai");
+- if (IS_ERR(sai->clk)) {
+- dev_err(&pdev->dev, "Cannot get SAI's clock\n");
+- return PTR_ERR(sai->clk);
++ base = devm_ioremap_resource(&pdev->dev, res);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
++ "bus", base, &fsl_sai_regmap_config);
++
++ /* Compatible with old DTB cases */
++ if (IS_ERR(sai->regmap))
++ sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
++ "sai", base, &fsl_sai_regmap_config);
++ if (IS_ERR(sai->regmap)) {
++ dev_err(&pdev->dev, "regmap init failed\n");
++ return PTR_ERR(sai->regmap);
++ }
++
++ /* No error out for old DTB cases but only mark the clock NULL */
++ sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
++ if (IS_ERR(sai->bus_clk)) {
++ dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
++ PTR_ERR(sai->bus_clk));
++ sai->bus_clk = NULL;
++ }
++
++ sai->mclk_clk[0] = sai->bus_clk;
++ for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
++ sprintf(tmp, "mclk%d", i);
++ sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
++ if (IS_ERR(sai->mclk_clk[i])) {
++ dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
++ i + 1, PTR_ERR(sai->mclk_clk[i]));
++ sai->mclk_clk[i] = NULL;
++ }
++ }
++
++ sai->slots = 2;
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
++ return irq;
++ }
++
++ ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
++ return ret;
++ }
++
++ /* Sync Tx with Rx as default by following old DT binding */
++ sai->synchronous[RX] = true;
++ sai->synchronous[TX] = false;
++ fsl_sai_dai.symmetric_rates = 1;
++ fsl_sai_dai.symmetric_channels = 1;
++ fsl_sai_dai.symmetric_samplebits = 1;
++
++ if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
++ of_find_property(np, "fsl,sai-asynchronous", NULL)) {
++ /* error out if both synchronous and asynchronous are present */
++ dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
++ return -EINVAL;
++ }
++
++ if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
++ /* Sync Rx with Tx */
++ sai->synchronous[RX] = false;
++ sai->synchronous[TX] = true;
++ } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
++ /* Discard all settings for asynchronous mode */
++ sai->synchronous[RX] = false;
++ sai->synchronous[TX] = false;
++ fsl_sai_dai.symmetric_rates = 0;
++ fsl_sai_dai.symmetric_channels = 0;
++ fsl_sai_dai.symmetric_samplebits = 0;
+ }
+
+ sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
+@@ -424,9 +785,6 @@
+ sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
+ sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
+
+- sai->big_endian_regs = of_property_read_bool(np, "big-endian-regs");
+- sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
+-
+ platform_set_drvdata(pdev, sai);
+
+ ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
+@@ -434,20 +792,54 @@
+ if (ret)
+ return ret;
+
+- return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
+- SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
++ if (sai->sai_on_imx)
++ return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
++ else
++ return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
++ SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
+ }
+
+ static const struct of_device_id fsl_sai_ids[] = {
+ { .compatible = "fsl,vf610-sai", },
++ { .compatible = "fsl,imx6sx-sai", },
+ { /* sentinel */ }
+ };
+
++#if CONFIG_PM_SLEEP
++static int fsl_sai_suspend(struct device *dev)
++{
++ struct fsl_sai *sai = dev_get_drvdata(dev);
++
++ regcache_cache_only(sai->regmap, true);
++ regcache_mark_dirty(sai->regmap);
++
++ return 0;
++}
++
++static int fsl_sai_resume(struct device *dev)
++{
++ struct fsl_sai *sai = dev_get_drvdata(dev);
++
++ regcache_cache_only(sai->regmap, false);
++ regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
++ regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
++ msleep(1);
++ regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
++ regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
++ return regcache_sync(sai->regmap);
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops fsl_sai_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
++};
++
+ static struct platform_driver fsl_sai_driver = {
+ .probe = fsl_sai_probe,
+ .driver = {
+ .name = "fsl-sai",
+ .owner = THIS_MODULE,
++ .pm = &fsl_sai_pm_ops,
+ .of_match_table = fsl_sai_ids,
+ },
+ };
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_sai.h linux-3.14.72/sound/soc/fsl/fsl_sai.h
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_sai.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_sai.h 2016-06-19 22:11:55.525125571 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012-2013 Freescale Semiconductor, Inc.
++ * Copyright 2012-2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+@@ -15,50 +15,79 @@
+ SNDRV_PCM_FMTBIT_S20_3LE |\
+ SNDRV_PCM_FMTBIT_S24_LE)
+
++/* SAI Register Map Register */
++#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */
++#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */
++#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */
++#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
++#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
++#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
++#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */
++#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
++#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
++#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
++#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
++#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */
++#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
++#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
++#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
++#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */
++#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */
++#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
++
++#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
++#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1)
++#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2)
++#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3)
++#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4)
++#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5)
++#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR)
++#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR)
++#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
++
+ /* SAI Transmit/Recieve Control Register */
+-#define FSL_SAI_TCSR 0x00
+-#define FSL_SAI_RCSR 0x80
+ #define FSL_SAI_CSR_TERE BIT(31)
++#define FSL_SAI_CSR_FR BIT(25)
++#define FSL_SAI_CSR_SR BIT(24)
++#define FSL_SAI_CSR_xF_SHIFT 16
++#define FSL_SAI_CSR_xF_W_SHIFT 18
++#define FSL_SAI_CSR_xF_MASK (0x1f << FSL_SAI_CSR_xF_SHIFT)
++#define FSL_SAI_CSR_xF_W_MASK (0x7 << FSL_SAI_CSR_xF_W_SHIFT)
++#define FSL_SAI_CSR_WSF BIT(20)
++#define FSL_SAI_CSR_SEF BIT(19)
++#define FSL_SAI_CSR_FEF BIT(18)
+ #define FSL_SAI_CSR_FWF BIT(17)
++#define FSL_SAI_CSR_FRF BIT(16)
++#define FSL_SAI_CSR_xIE_SHIFT 8
++#define FSL_SAI_CSR_xIE_MASK (0x1f << FSL_SAI_CSR_xIE_SHIFT)
++#define FSL_SAI_CSR_WSIE BIT(12)
++#define FSL_SAI_CSR_SEIE BIT(11)
++#define FSL_SAI_CSR_FEIE BIT(10)
++#define FSL_SAI_CSR_FWIE BIT(9)
+ #define FSL_SAI_CSR_FRIE BIT(8)
+ #define FSL_SAI_CSR_FRDE BIT(0)
+
+-/* SAI Transmit Data/FIFO/MASK Register */
+-#define FSL_SAI_TDR 0x20
+-#define FSL_SAI_TFR 0x40
+-#define FSL_SAI_TMR 0x60
+-
+-/* SAI Recieve Data/FIFO/MASK Register */
+-#define FSL_SAI_RDR 0xa0
+-#define FSL_SAI_RFR 0xc0
+-#define FSL_SAI_RMR 0xe0
+-
+ /* SAI Transmit and Recieve Configuration 1 Register */
+-#define FSL_SAI_TCR1 0x04
+-#define FSL_SAI_RCR1 0x84
++#define FSL_SAI_CR1_RFW_MASK 0x1f
+
+ /* SAI Transmit and Recieve Configuration 2 Register */
+-#define FSL_SAI_TCR2 0x08
+-#define FSL_SAI_RCR2 0x88
+ #define FSL_SAI_CR2_SYNC BIT(30)
+-#define FSL_SAI_CR2_MSEL_MASK (0xff << 26)
++#define FSL_SAI_CR2_MSEL_MASK (0x3 << 26)
+ #define FSL_SAI_CR2_MSEL_BUS 0
+ #define FSL_SAI_CR2_MSEL_MCLK1 BIT(26)
+ #define FSL_SAI_CR2_MSEL_MCLK2 BIT(27)
+ #define FSL_SAI_CR2_MSEL_MCLK3 (BIT(26) | BIT(27))
++#define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
+ #define FSL_SAI_CR2_BCP BIT(25)
+ #define FSL_SAI_CR2_BCD_MSTR BIT(24)
++#define FSL_SAI_CR2_DIV_MASK 0xff
+
+ /* SAI Transmit and Recieve Configuration 3 Register */
+-#define FSL_SAI_TCR3 0x0c
+-#define FSL_SAI_RCR3 0x8c
+ #define FSL_SAI_CR3_TRCE BIT(16)
+ #define FSL_SAI_CR3_WDFL(x) (x)
+ #define FSL_SAI_CR3_WDFL_MASK 0x1f
+
+ /* SAI Transmit and Recieve Configuration 4 Register */
+-#define FSL_SAI_TCR4 0x10
+-#define FSL_SAI_RCR4 0x90
+ #define FSL_SAI_CR4_FRSZ(x) (((x) - 1) << 16)
+ #define FSL_SAI_CR4_FRSZ_MASK (0x1f << 16)
+ #define FSL_SAI_CR4_SYWD(x) (((x) - 1) << 8)
+@@ -69,8 +98,6 @@
+ #define FSL_SAI_CR4_FSD_MSTR BIT(0)
+
+ /* SAI Transmit and Recieve Configuration 5 Register */
+-#define FSL_SAI_TCR5 0x14
+-#define FSL_SAI_RCR5 0x94
+ #define FSL_SAI_CR5_WNW(x) (((x) - 1) << 24)
+ #define FSL_SAI_CR5_WNW_MASK (0x1f << 24)
+ #define FSL_SAI_CR5_W0W(x) (((x) - 1) << 16)
+@@ -95,20 +122,34 @@
+ #define FSL_SAI_CLK_MAST2 2
+ #define FSL_SAI_CLK_MAST3 3
+
++#define FSL_SAI_MCLK_MAX 4
++
+ /* SAI data transfer numbers per DMA request */
+ #define FSL_SAI_MAXBURST_TX 6
+ #define FSL_SAI_MAXBURST_RX 6
+
+ struct fsl_sai {
+- struct clk *clk;
+-
+- void __iomem *base;
+-
+- bool big_endian_regs;
+- bool big_endian_data;
++ struct platform_device *pdev;
++ struct regmap *regmap;
++ struct clk *bus_clk;
++ struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
++
++ bool is_slave_mode;
++ bool is_lsb_first;
++ bool is_dsp_mode;
++ bool sai_on_imx;
++ bool synchronous[2];
++
++ unsigned int mclk_id;
++ unsigned int mclk_streams;
++ unsigned int slots;
++ unsigned int slot_width;
+
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ };
+
++#define TX 1
++#define RX 0
++
+ #endif /* __FSL_SAI_H */
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_spdif.c linux-3.14.72/sound/soc/fsl/fsl_spdif.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_spdif.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_spdif.c 2016-06-19 22:11:55.525125571 +0200
+@@ -13,18 +13,20 @@
+ * kind, whether express or implied.
+ */
+
+-#include <linux/module.h>
++#include <linux/bitrev.h>
+ #include <linux/clk.h>
+ #include <linux/clk-private.h>
+-#include <linux/bitrev.h>
+-#include <linux/regmap.h>
++#include <linux/module.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+ #include <linux/of_irq.h>
++#include <linux/regmap.h>
++#include <linux/pm_runtime.h>
++#include <linux/busfreq-imx6.h>
+
+ #include <sound/asoundef.h>
+-#include <sound/soc.h>
+ #include <sound/dmaengine_pcm.h>
++#include <sound/soc.h>
+
+ #include "fsl_spdif.h"
+ #include "imx-pcm.h"
+@@ -32,10 +34,13 @@
+ #define FSL_SPDIF_TXFIFO_WML 0x8
+ #define FSL_SPDIF_RXFIFO_WML 0x8
+
+-#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
+-#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV|\
+- INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR |\
+- INT_RXFIFO_RESYNC | INT_LOSS_LOCK | INT_DPLL_LOCKED)
++#define INTR_FOR_PLAYBACK (INT_TXFIFO_RESYNC)
++#define INTR_FOR_CAPTURE (INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL |\
++ INT_URX_OV | INT_QRX_FUL | INT_QRX_OV |\
++ INT_UQ_SYNC | INT_UQ_ERR | INT_RXFIFO_RESYNC |\
++ INT_LOSS_LOCK | INT_DPLL_LOCKED)
++
++#define SIE_INTR_FOR(tx) (tx ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE)
+
+ /* Index list for the values that has if (DPLL Locked) condition */
+ static u8 srpc_dpll_locked[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0xa, 0xb };
+@@ -53,7 +58,7 @@
+ spinlock_t ctl_lock;
+
+ /* IEC958 channel tx status bit */
+- unsigned char ch_status[4];
++ unsigned char ch_status[6];
+
+ /* User bits */
+ unsigned char subcode[2 * SPDIF_UBITS_SIZE];
+@@ -69,19 +74,47 @@
+ u32 ready_buf;
+ };
+
++/**
++ * fsl_spdif_priv: Freescale SPDIF private data
++ *
++ * @fsl_spdif_control: SPDIF control data
++ * @cpu_dai_drv: cpu dai driver
++ * @pdev: platform device pointer
++ * @regmap: regmap handler
++ * @dpll_locked: dpll lock flag
++ * @txrate: the best rates for playback
++ * @txclk_df: STC_TXCLK_DF dividers value for playback
++ * @sysclk_df: STC_SYSCLK_DF dividers value for playback
++ * @txclk_src: STC_TXCLK_SRC values for playback
++ * @rxclk_src: SRPC_CLKSRC_SEL values for capture
++ * @txclk: tx clock sources for playback
++ * @rxclk: rx clock sources for capture
++ * @coreclk: core clock for register access via DMA
++ * @sysclk: system clock for rx clock rate measurement
++ * @dma_params_tx: DMA parameters for transmit channel
++ * @dma_params_rx: DMA parameters for receive channel
++ * @name: driver name
++ */
+ struct fsl_spdif_priv {
+ struct spdif_mixer_control fsl_spdif_control;
+ struct snd_soc_dai_driver cpu_dai_drv;
+ struct platform_device *pdev;
+ struct regmap *regmap;
+ bool dpll_locked;
+- u8 txclk_div[SPDIF_TXRATE_MAX];
++ u32 txrate[SPDIF_TXRATE_MAX];
++ u8 txclk_df[SPDIF_TXRATE_MAX];
++ u8 sysclk_df[SPDIF_TXRATE_MAX];
+ u8 txclk_src[SPDIF_TXRATE_MAX];
+ u8 rxclk_src;
+ struct clk *txclk[SPDIF_TXRATE_MAX];
+ struct clk *rxclk;
++ struct clk *coreclk;
++ struct clk *sysclk;
++ struct clk *dmaclk;
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
++ /* regcache for SRPC */
++ u32 regcache_srpc;
+
+ /* The name space will be allocated dynamically */
+ char name[0];
+@@ -112,10 +145,9 @@
+
+ dev_dbg(&pdev->dev, "isr: receiver found illegal symbol\n");
+
+- if (!spdif_priv->dpll_locked) {
+- /* DPLL unlocked seems no audio stream */
++ /* Clear illegal symbol if DPLL unlocked since no audio stream */
++ if (!spdif_priv->dpll_locked)
+ regmap_update_bits(regmap, REG_SPDIF_SIE, INT_SYM_ERR, 0);
+- }
+ }
+
+ /* U/Q Channel receive register full */
+@@ -279,6 +311,8 @@
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val, cycle = 1000;
+
++ regcache_cache_bypass(regmap, true);
++
+ regmap_write(regmap, REG_SPDIF_SCR, SCR_SOFT_RESET);
+
+ /*
+@@ -289,17 +323,21 @@
+ regmap_read(regmap, REG_SPDIF_SCR, &val);
+ } while ((val & SCR_SOFT_RESET) && cycle--);
+
++ regcache_cache_bypass(regmap, false);
++ regcache_mark_dirty(regmap);
++ regcache_sync(regmap);
++
+ if (cycle)
+ return 0;
+ else
+ return -EBUSY;
+ }
+
+-static void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
+- u8 mask, u8 cstatus)
++static inline void spdif_set_cstatus(struct spdif_mixer_control *ctrl,
++ u8 byteno, u8 mask, u8 cstatus)
+ {
+- ctrl->ch_status[3] &= ~mask;
+- ctrl->ch_status[3] |= cstatus & mask;
++ ctrl->ch_status[byteno] &= ~mask;
++ ctrl->ch_status[byteno] |= cstatus & mask;
+ }
+
+ static void spdif_write_channel_status(struct fsl_spdif_priv *spdif_priv)
+@@ -310,16 +348,22 @@
+ u32 ch_status;
+
+ ch_status = (bitrev8(ctrl->ch_status[0]) << 16) |
+- (bitrev8(ctrl->ch_status[1]) << 8) |
+- bitrev8(ctrl->ch_status[2]);
++ (bitrev8(ctrl->ch_status[1]) << 8) |
++ bitrev8(ctrl->ch_status[2]);
+ regmap_write(regmap, REG_SPDIF_STCSCH, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCH: 0x%06x\n", ch_status);
+
+- ch_status = bitrev8(ctrl->ch_status[3]) << 16;
++ ch_status = bitrev8(ctrl->ch_status[3]) << 16 |
++ (bitrev8(ctrl->ch_status[4]) << 8) |
++ bitrev8(ctrl->ch_status[5]);
+ regmap_write(regmap, REG_SPDIF_STCSCL, ch_status);
+
+ dev_dbg(&pdev->dev, "STCSCL: 0x%06x\n", ch_status);
++
++ /* Set outgoing validity (0: pcm, 1: non-audio) */
++ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_VAL_MASK,
++ (ctrl->ch_status[0] & IEC958_AES0_NONAUDIO) ? 0 : SCR_VAL_CLEAR);
+ }
+
+ /* Set SPDIF PhaseConfig register for rx clock */
+@@ -347,23 +391,46 @@
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ struct regmap *regmap = spdif_priv->regmap;
+ struct platform_device *pdev = spdif_priv->pdev;
+- unsigned long csfs = 0;
++ unsigned long csfs, csofs = 0;
+ u32 stc, mask, rate;
+- u8 clk, div;
++ u8 clk, txclk_df, sysclk_df;
+ int ret;
+
+ switch (sample_rate) {
+ case 32000:
+ rate = SPDIF_TXRATE_32000;
+ csfs = IEC958_AES3_CON_FS_32000;
++ csofs = IEC958_AES4_CON_ORIGFS_32000;
+ break;
+ case 44100:
+ rate = SPDIF_TXRATE_44100;
+ csfs = IEC958_AES3_CON_FS_44100;
++ csofs = IEC958_AES4_CON_ORIGFS_44100;
+ break;
+ case 48000:
+ rate = SPDIF_TXRATE_48000;
+ csfs = IEC958_AES3_CON_FS_48000;
++ csofs = IEC958_AES4_CON_ORIGFS_48000;
++ break;
++ case 88200:
++ rate = SPDIF_TXRATE_88200;
++ csfs = IEC958_AES3_CON_FS_88200;
++ csofs = IEC958_AES4_CON_ORIGFS_88200;
++ break;
++ case 96000:
++ rate = SPDIF_TXRATE_96000;
++ csfs = IEC958_AES3_CON_FS_96000;
++ csofs = IEC958_AES4_CON_ORIGFS_96000;
++ break;
++ case 176400:
++ rate = SPDIF_TXRATE_176400;
++ csfs = IEC958_AES3_CON_FS_176400;
++ csofs = IEC958_AES4_CON_ORIGFS_176400;
++ break;
++ case 192000:
++ rate = SPDIF_TXRATE_192000;
++ csfs = IEC958_AES3_CON_FS_192000;
++ csofs = IEC958_AES4_CON_ORIGFS_192000;
+ break;
+ default:
+ dev_err(&pdev->dev, "unsupported sample rate %d\n", sample_rate);
+@@ -376,37 +443,47 @@
+ return -EINVAL;
+ }
+
+- div = spdif_priv->txclk_div[rate];
+- if (div == 0) {
+- dev_err(&pdev->dev, "the divisor can't be zero\n");
++ txclk_df = spdif_priv->txclk_df[rate];
++ if (txclk_df == 0) {
++ dev_err(&pdev->dev, "the txclk_df can't be zero\n");
+ return -EINVAL;
+ }
+
++ sysclk_df = spdif_priv->sysclk_df[rate];
++
++ /* Don't mess up the clocks from other modules */
++ if (clk != STC_TXCLK_SPDIF_ROOT)
++ goto clk_set_bypass;
++
+ /*
+- * The S/PDIF block needs a clock of 64 * fs * div. The S/PDIF block
+- * will divide by (div). So request 64 * fs * (div+1) which will
+- * get rounded.
++ * The S/PDIF block needs a clock of 64 * fs * txclk_df.
++ * So request 64 * fs * (txclk_df + 1) to get rounded.
+ */
+- ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (div + 1));
++ ret = clk_set_rate(spdif_priv->txclk[rate], 64 * sample_rate * (txclk_df + 1));
+ if (ret) {
+ dev_err(&pdev->dev, "failed to set tx clock rate\n");
+ return ret;
+ }
+
++clk_set_bypass:
+ dev_dbg(&pdev->dev, "expected clock rate = %d\n",
+- (64 * sample_rate * div));
++ (64 * sample_rate * txclk_df * sysclk_df));
+ dev_dbg(&pdev->dev, "actual clock rate = %ld\n",
+ clk_get_rate(spdif_priv->txclk[rate]));
+
+ /* set fs field in consumer channel status */
+- spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs);
++ spdif_set_cstatus(ctrl, 3, IEC958_AES3_CON_FS, csfs);
++ spdif_set_cstatus(ctrl, 4, IEC958_AES4_CON_ORIGFS, csofs);
+
+ /* select clock source and divisor */
+- stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) | STC_TXCLK_DIV(div);
+- mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK | STC_TXCLK_DIV_MASK;
++ stc = STC_TXCLK_ALL_EN | STC_TXCLK_SRC_SET(clk) |
++ STC_TXCLK_DF(txclk_df) | STC_SYSCLK_DF(sysclk_df);
++ mask = STC_TXCLK_ALL_EN_MASK | STC_TXCLK_SRC_MASK |
++ STC_TXCLK_DF_MASK | STC_SYSCLK_DF_MASK;
+ regmap_update_bits(regmap, REG_SPDIF_STC, mask, stc);
+
+- dev_dbg(&pdev->dev, "set sample rate to %d\n", sample_rate);
++ dev_dbg(&pdev->dev, "set sample rate to %dHz for %dHz playback\n",
++ spdif_priv->txrate[rate], sample_rate);
+
+ return 0;
+ }
+@@ -421,12 +498,26 @@
+ u32 scr, mask, i;
+ int ret;
+
++ pm_runtime_get_sync(cpu_dai->dev);
++
+ /* Reset module and interrupts only for first initialization */
+ if (!cpu_dai->active) {
++ ret = clk_prepare_enable(spdif_priv->coreclk);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to enable core clock\n");
++ return ret;
++ }
++
++ ret = clk_prepare_enable(spdif_priv->dmaclk);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to enable dma clock\n");
++ return ret;
++ }
++
+ ret = spdif_softreset(spdif_priv);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to soft reset\n");
+- return ret;
++ goto err;
+ }
+
+ /* Disable all the interrupts */
+@@ -454,6 +545,11 @@
+ regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0);
+
+ return 0;
++
++err:
++ clk_disable_unprepare(spdif_priv->coreclk);
++
++ return ret;
+ }
+
+ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
+@@ -484,7 +580,11 @@
+ spdif_intr_status_clear(spdif_priv);
+ regmap_update_bits(regmap, REG_SPDIF_SCR,
+ SCR_LOW_POWER, SCR_LOW_POWER);
++ clk_disable_unprepare(spdif_priv->dmaclk);
++ clk_disable_unprepare(spdif_priv->coreclk);
+ }
++
++ pm_runtime_put_sync(cpu_dai->dev);
+ }
+
+ static int fsl_spdif_hw_params(struct snd_pcm_substream *substream,
+@@ -505,8 +605,8 @@
+ __func__, sample_rate);
+ return ret;
+ }
+- spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK,
+- IEC958_AES3_CON_CLOCK_1000PPM);
++ spdif_set_cstatus(ctrl, 3, IEC958_AES3_CON_CLOCK,
++ IEC958_AES3_CON_CLOCK_1000PPM);
+ spdif_write_channel_status(spdif_priv);
+ } else {
+ /* Setup rx clock source */
+@@ -522,9 +622,9 @@
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+ struct regmap *regmap = spdif_priv->regmap;
+- int is_playack = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+- u32 intr = is_playack ? INTR_FOR_PLAYBACK : INTR_FOR_CAPTURE;
+- u32 dmaen = is_playack ? SCR_DMA_TX_EN : SCR_DMA_RX_EN;;
++ bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
++ u32 intr = SIE_INTR_FOR(tx);
++ u32 dmaen = SCR_DMA_xX_EN(tx);
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+@@ -576,14 +676,13 @@
+ static int fsl_spdif_pb_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+ {
++ int i;
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+- uvalue->value.iec958.status[0] = ctrl->ch_status[0];
+- uvalue->value.iec958.status[1] = ctrl->ch_status[1];
+- uvalue->value.iec958.status[2] = ctrl->ch_status[2];
+- uvalue->value.iec958.status[3] = ctrl->ch_status[3];
++ for (i = 0; i < ARRAY_SIZE(ctrl->ch_status); i++)
++ uvalue->value.iec958.status[i] = ctrl->ch_status[i];
+
+ return 0;
+ }
+@@ -591,14 +690,13 @@
+ static int fsl_spdif_pb_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uvalue)
+ {
++ int i;
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+
+- ctrl->ch_status[0] = uvalue->value.iec958.status[0];
+- ctrl->ch_status[1] = uvalue->value.iec958.status[1];
+- ctrl->ch_status[2] = uvalue->value.iec958.status[2];
+- ctrl->ch_status[3] = uvalue->value.iec958.status[3];
++ for (i = 0; i < ARRAY_SIZE(ctrl->ch_status); i++)
++ ctrl->ch_status[i] = uvalue->value.iec958.status[i];
+
+ spdif_write_channel_status(spdif_priv);
+
+@@ -615,9 +713,8 @@
+ u32 cstatus, val;
+
+ regmap_read(regmap, REG_SPDIF_SIS, &val);
+- if (!(val & INT_CNEW)) {
++ if (!(val & INT_CNEW))
+ return -EAGAIN;
+- }
+
+ regmap_read(regmap, REG_SPDIF_SRCSH, &cstatus);
+ ucontrol->value.iec958.status[0] = (cstatus >> 16) & 0xFF;
+@@ -646,15 +743,14 @@
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+- int ret = 0;
++ int ret = -EAGAIN;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE;
+ memcpy(&ucontrol->value.iec958.subcode[0],
+ &ctrl->subcode[idx], SPDIF_UBITS_SIZE);
+- } else {
+- ret = -EAGAIN;
++ ret = 0;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+@@ -679,15 +775,14 @@
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+ struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control;
+ unsigned long flags;
+- int ret = 0;
++ int ret = -EAGAIN;
+
+ spin_lock_irqsave(&ctrl->ctl_lock, flags);
+ if (ctrl->ready_buf) {
+ int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE;
+ memcpy(&ucontrol->value.bytes.data[0],
+ &ctrl->qsub[idx], SPDIF_QSUB_SIZE);
+- } else {
+- ret = -EAGAIN;
++ ret = 0;
+ }
+ spin_unlock_irqrestore(&ctrl->ctl_lock, flags);
+
+@@ -715,7 +810,7 @@
+ struct regmap *regmap = spdif_priv->regmap;
+ u32 val;
+
+- val = regmap_read(regmap, REG_SPDIF_SIS, &val);
++ regmap_read(regmap, REG_SPDIF_SIS, &val);
+ ucontrol->value.integer.value[0] = (val & INT_VAL_NOGOOD) != 0;
+ regmap_write(regmap, REG_SPDIF_SIC, INT_VAL_NOGOOD);
+
+@@ -752,10 +847,10 @@
+ regmap_read(regmap, REG_SPDIF_SRPC, &phaseconf);
+
+ clksrc = (phaseconf >> SRPC_CLKSRC_SEL_OFFSET) & 0xf;
+- if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED)) {
+- /* Get bus clock from system */
+- busclk_freq = clk_get_rate(spdif_priv->rxclk);
+- }
++
++ /* Get bus clock from system */
++ if (srpc_dpll_locked[clksrc] && (phaseconf & SRPC_DPLL_LOCKED))
++ busclk_freq = clk_get_rate(spdif_priv->sysclk);
+
+ /* FreqMeas_CLK = (BUS_CLK * FreqMeas) / 2 ^ 10 / GAINSEL / 128 */
+ tmpval64 = (u64) busclk_freq * freqmeas;
+@@ -779,12 +874,12 @@
+ {
+ struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
+ struct fsl_spdif_priv *spdif_priv = snd_soc_dai_get_drvdata(cpu_dai);
+- int rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
++ int rate = 0;
+
+ if (spdif_priv->dpll_locked)
+- ucontrol->value.integer.value[0] = rate;
+- else
+- ucontrol->value.integer.value[0] = 0;
++ rate = spdif_get_rxclk_rate(spdif_priv, SPDIF_DEFAULT_GAINSEL);
++
++ ucontrol->value.integer.value[0] = rate;
+
+ return 0;
+ }
+@@ -911,8 +1006,8 @@
+ {
+ struct fsl_spdif_priv *spdif_private = snd_soc_dai_get_drvdata(dai);
+
+- dai->playback_dma_data = &spdif_private->dma_params_tx;
+- dai->capture_dma_data = &spdif_private->dma_params_rx;
++ snd_soc_dai_init_dma_data(dai, &spdif_private->dma_params_tx,
++ &spdif_private->dma_params_rx);
+
+ snd_soc_add_dai_controls(dai, fsl_spdif_ctrls, ARRAY_SIZE(fsl_spdif_ctrls));
+
+@@ -922,12 +1017,14 @@
+ static struct snd_soc_dai_driver fsl_spdif_dai = {
+ .probe = &fsl_spdif_dai_probe,
+ .playback = {
++ .stream_name = "CPU-Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_PLAYBACK,
+ .formats = FSL_SPDIF_FORMATS_PLAYBACK,
+ },
+ .capture = {
++ .stream_name = "CPU-Capture",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = FSL_SPDIF_RATES_CAPTURE,
+@@ -966,6 +1063,27 @@
+ }
+ }
+
++static bool fsl_spdif_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case REG_SPDIF_SRPC:
++ case REG_SPDIF_SIS:
++ case REG_SPDIF_SRL:
++ case REG_SPDIF_SRR:
++ case REG_SPDIF_SRCSH:
++ case REG_SPDIF_SRCSL:
++ case REG_SPDIF_SRU:
++ case REG_SPDIF_SRQ:
++ case REG_SPDIF_STL:
++ case REG_SPDIF_STR:
++ case REG_SPDIF_SRFM:
++ return true;
++ default:
++ return false;
++ }
++
++}
++
+ static bool fsl_spdif_writeable_reg(struct device *dev, unsigned int reg)
+ {
+ switch (reg) {
+@@ -985,62 +1103,82 @@
+ }
+ }
+
+-static const struct regmap_config fsl_spdif_regmap_config = {
++static struct regmap_config fsl_spdif_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+
+ .max_register = REG_SPDIF_STC,
+ .readable_reg = fsl_spdif_readable_reg,
++ .volatile_reg = fsl_spdif_volatile_reg,
+ .writeable_reg = fsl_spdif_writeable_reg,
++ .cache_type = REGCACHE_RBTREE,
+ };
+
+ static u32 fsl_spdif_txclk_caldiv(struct fsl_spdif_priv *spdif_priv,
+ struct clk *clk, u64 savesub,
+- enum spdif_txrate index)
++ enum spdif_txrate index, bool round)
+ {
+- const u32 rate[] = { 32000, 44100, 48000 };
++ const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 192000 };
++ bool is_sysclk = clk == spdif_priv->sysclk;
+ u64 rate_ideal, rate_actual, sub;
+- u32 div, arate;
++ u32 sysclk_dfmin, sysclk_dfmax;
++ u32 txclk_df, sysclk_df, arate;
+
+- for (div = 1; div <= 128; div++) {
+- rate_ideal = rate[index] * (div + 1) * 64;
+- rate_actual = clk_round_rate(clk, rate_ideal);
+-
+- arate = rate_actual / 64;
+- arate /= div;
+-
+- if (arate == rate[index]) {
+- /* We are lucky */
+- savesub = 0;
+- spdif_priv->txclk_div[index] = div;
+- break;
+- } else if (arate / rate[index] == 1) {
+- /* A little bigger than expect */
+- sub = (arate - rate[index]) * 100000;
+- do_div(sub, rate[index]);
+- if (sub < savesub) {
++ /* The sysclk has an extra divisor [2, 512] */
++ sysclk_dfmin = is_sysclk ? 2 : 1;
++ sysclk_dfmax = is_sysclk ? 512 : 1;
++
++ for (sysclk_df = sysclk_dfmin; sysclk_df <= sysclk_dfmax; sysclk_df++) {
++ for (txclk_df = 1; txclk_df <= 128; txclk_df++) {
++ rate_ideal = rate[index] * (txclk_df + 1) * 64;
++ if (round)
++ rate_actual = clk_round_rate(clk, rate_ideal);
++ else
++ rate_actual = clk_get_rate(clk);
++
++ arate = rate_actual / 64;
++ arate /= txclk_df * sysclk_df;
++
++ if (arate == rate[index]) {
++ /* We are lucky */
++ savesub = 0;
++ spdif_priv->txclk_df[index] = txclk_df;
++ spdif_priv->sysclk_df[index] = sysclk_df;
++ spdif_priv->txrate[index] = arate;
++ goto out;
++ } else if (arate / rate[index] == 1) {
++ /* A little bigger than expect */
++ sub = (u64)(arate - rate[index]) * 100000;
++ do_div(sub, rate[index]);
++ if (sub >= savesub)
++ continue;
+ savesub = sub;
+- spdif_priv->txclk_div[index] = div;
+- }
+- } else if (rate[index] / arate == 1) {
+- /* A little smaller than expect */
+- sub = (rate[index] - arate) * 100000;
+- do_div(sub, rate[index]);
+- if (sub < savesub) {
++ spdif_priv->txclk_df[index] = txclk_df;
++ spdif_priv->sysclk_df[index] = sysclk_df;
++ spdif_priv->txrate[index] = arate;
++ } else if (rate[index] / arate == 1) {
++ /* A little smaller than expect */
++ sub = (u64)(rate[index] - arate) * 100000;
++ do_div(sub, rate[index]);
++ if (sub >= savesub)
++ continue;
+ savesub = sub;
+- spdif_priv->txclk_div[index] = div;
++ spdif_priv->txclk_df[index] = txclk_df;
++ spdif_priv->sysclk_df[index] = sysclk_df;
++ spdif_priv->txrate[index] = arate;
+ }
+ }
+ }
+
++out:
+ return savesub;
+ }
+
+ static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv,
+ enum spdif_txrate index)
+ {
+- const u32 rate[] = { 32000, 44100, 48000 };
++ const u32 rate[] = { 32000, 44100, 48000, 88200, 96000, 176400, 192000 };
+ struct platform_device *pdev = spdif_priv->pdev;
+ struct device *dev = &pdev->dev;
+ u64 savesub = 100000, ret;
+@@ -1058,7 +1196,8 @@
+ if (!clk_get_rate(clk))
+ continue;
+
+- ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index);
++ ret = fsl_spdif_txclk_caldiv(spdif_priv, clk, savesub, index,
++ i == STC_TXCLK_SPDIF_ROOT);
+ if (savesub == ret)
+ continue;
+
+@@ -1073,8 +1212,13 @@
+
+ dev_dbg(&pdev->dev, "use rxtx%d as tx clock source for %dHz sample rate\n",
+ spdif_priv->txclk_src[index], rate[index]);
+- dev_dbg(&pdev->dev, "use divisor %d for %dHz sample rate\n",
+- spdif_priv->txclk_div[index], rate[index]);
++ dev_dbg(&pdev->dev, "use txclk df %d for %dHz sample rate\n",
++ spdif_priv->txclk_df[index], rate[index]);
++ if (spdif_priv->txclk[index] == spdif_priv->sysclk)
++ dev_dbg(&pdev->dev, "use sysclk df %d for %dHz sample rate\n",
++ spdif_priv->sysclk_df[index], rate[index]);
++ dev_dbg(&pdev->dev, "the best rate for %dHz sample rate is %dHz\n",
++ rate[index], spdif_priv->txrate[index]);
+
+ return 0;
+ }
+@@ -1105,6 +1249,9 @@
+ memcpy(&spdif_priv->cpu_dai_drv, &fsl_spdif_dai, sizeof(fsl_spdif_dai));
+ spdif_priv->cpu_dai_drv.name = spdif_priv->name;
+
++ if (of_property_read_bool(np, "big-endian"))
++ fsl_spdif_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
++
+ /* Get the addresses and IRQ */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(&pdev->dev, res);
+@@ -1131,6 +1278,27 @@
+ return ret;
+ }
+
++ /* Get system clock for rx clock rate calculation */
++ spdif_priv->sysclk = devm_clk_get(&pdev->dev, "rxtx5");
++ if (IS_ERR(spdif_priv->sysclk)) {
++ dev_err(&pdev->dev, "no sys clock (rxtx5) in devicetree\n");
++ return PTR_ERR(spdif_priv->sysclk);
++ }
++
++ /* Get core clock for data register access via DMA */
++ spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core");
++ if (IS_ERR(spdif_priv->coreclk)) {
++ dev_err(&pdev->dev, "no core clock in devicetree\n");
++ return PTR_ERR(spdif_priv->coreclk);
++ }
++
++ /* Get dma clock for dma script operation */
++ spdif_priv->dmaclk = devm_clk_get(&pdev->dev, "dma");
++ if (IS_ERR(spdif_priv->dmaclk)) {
++ dev_err(&pdev->dev, "no dma clock in devicetree\n");
++ return PTR_ERR(spdif_priv->dmaclk);
++ }
++
+ /* Select clock source for rx/tx clock */
+ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
+ if (IS_ERR(spdif_priv->rxclk)) {
+@@ -1150,12 +1318,13 @@
+ spin_lock_init(&ctrl->ctl_lock);
+
+ /* Init tx channel status default value */
+- ctrl->ch_status[0] =
+- IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_5015;
++ ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
+ ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID;
+ ctrl->ch_status[2] = 0x00;
+- ctrl->ch_status[3] =
+- IEC958_AES3_CON_FS_44100 | IEC958_AES3_CON_CLOCK_1000PPM;
++ ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 |
++ IEC958_AES3_CON_CLOCK_1000PPM;
++ ctrl->ch_status[4] = IEC958_AES4_CON_ORIGFS_44100;
++ ctrl->ch_status[5] = IEC958_AES5_CON_CGMSA_COPYFREELY;
+
+ spdif_priv->dpll_locked = false;
+
+@@ -1164,6 +1333,8 @@
+ spdif_priv->dma_params_tx.addr = res->start + REG_SPDIF_STL;
+ spdif_priv->dma_params_rx.addr = res->start + REG_SPDIF_SRL;
+
++ pm_runtime_enable(&pdev->dev);
++
+ /* Register with ASoC */
+ dev_set_drvdata(&pdev->dev, spdif_priv);
+
+@@ -1174,15 +1345,65 @@
+ return ret;
+ }
+
+- ret = imx_pcm_dma_init(pdev);
++ ret = imx_pcm_dma_init(pdev, IMX_SPDIF_DMABUF_SIZE);
+ if (ret)
+ dev_err(&pdev->dev, "imx_pcm_dma_init failed: %d\n", ret);
+
+ return ret;
+ }
+
++#ifdef CONFIG_PM_RUNTIME
++static int fsl_spdif_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++
++static int fsl_spdif_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_HIGH);
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_PM_SLEEP
++static int fsl_spdif_suspend(struct device *dev)
++{
++ struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
++
++ regmap_read(spdif_priv->regmap, REG_SPDIF_SRPC,
++ &spdif_priv->regcache_srpc);
++
++ regcache_cache_only(spdif_priv->regmap, true);
++ regcache_mark_dirty(spdif_priv->regmap);
++
++ return 0;
++}
++
++static int fsl_spdif_resume(struct device *dev)
++{
++ struct fsl_spdif_priv *spdif_priv = dev_get_drvdata(dev);
++
++ regcache_cache_only(spdif_priv->regmap, false);
++
++ regmap_update_bits(spdif_priv->regmap, REG_SPDIF_SRPC,
++ SRPC_CLKSRC_SEL_MASK | SRPC_GAINSEL_MASK,
++ spdif_priv->regcache_srpc);
++
++ return regcache_sync(spdif_priv->regmap);
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops fsl_spdif_pm = {
++ SET_RUNTIME_PM_OPS(fsl_spdif_runtime_suspend,
++ fsl_spdif_runtime_resume,
++ NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(fsl_spdif_suspend, fsl_spdif_resume)
++};
++
+ static const struct of_device_id fsl_spdif_dt_ids[] = {
+ { .compatible = "fsl,imx35-spdif", },
++ { .compatible = "fsl,vf610-spdif", },
+ {}
+ };
+ MODULE_DEVICE_TABLE(of, fsl_spdif_dt_ids);
+@@ -1192,6 +1413,7 @@
+ .name = "fsl-spdif-dai",
+ .owner = THIS_MODULE,
+ .of_match_table = fsl_spdif_dt_ids,
++ .pm = &fsl_spdif_pm,
+ },
+ .probe = fsl_spdif_probe,
+ };
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_spdif.h linux-3.14.72/sound/soc/fsl/fsl_spdif.h
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_spdif.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_spdif.h 2016-06-19 22:11:55.525125571 +0200
+@@ -93,6 +93,8 @@
+ #define SCR_USRC_SEL_RECV (0x1 << SCR_USRC_SEL_OFFSET)
+ #define SCR_USRC_SEL_CHIP (0x3 << SCR_USRC_SEL_OFFSET)
+
++#define SCR_DMA_xX_EN(tx) (tx ? SCR_DMA_TX_EN : SCR_DMA_RX_EN)
++
+ /* SPDIF CDText control */
+ #define SRCD_CD_USER_OFFSET 1
+ #define SRCD_CD_USER (1 << SRCD_CD_USER_OFFSET)
+@@ -143,27 +145,33 @@
+ #define INT_RXFIFO_FUL (1 << 0)
+
+ /* SPDIF Clock register */
+-#define STC_SYSCLK_DIV_OFFSET 11
+-#define STC_SYSCLK_DIV_MASK (0x1ff << STC_TXCLK_SRC_OFFSET)
+-#define STC_SYSCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_SYSCLK_DIV_MASK)
++#define STC_SYSCLK_DF_OFFSET 11
++#define STC_SYSCLK_DF_MASK (0x1ff << STC_SYSCLK_DF_OFFSET)
++#define STC_SYSCLK_DF(x) ((((x) - 1) << STC_SYSCLK_DF_OFFSET) & STC_SYSCLK_DF_MASK)
+ #define STC_TXCLK_SRC_OFFSET 8
+ #define STC_TXCLK_SRC_MASK (0x7 << STC_TXCLK_SRC_OFFSET)
+ #define STC_TXCLK_SRC_SET(x) ((x << STC_TXCLK_SRC_OFFSET) & STC_TXCLK_SRC_MASK)
+ #define STC_TXCLK_ALL_EN_OFFSET 7
+ #define STC_TXCLK_ALL_EN_MASK (1 << STC_TXCLK_ALL_EN_OFFSET)
+ #define STC_TXCLK_ALL_EN (1 << STC_TXCLK_ALL_EN_OFFSET)
+-#define STC_TXCLK_DIV_OFFSET 0
+-#define STC_TXCLK_DIV_MASK (0x7ff << STC_TXCLK_DIV_OFFSET)
+-#define STC_TXCLK_DIV(x) ((((x) - 1) << STC_TXCLK_DIV_OFFSET) & STC_TXCLK_DIV_MASK)
++#define STC_TXCLK_DF_OFFSET 0
++#define STC_TXCLK_DF_MASK (0x7ff << STC_TXCLK_DF_OFFSET)
++#define STC_TXCLK_DF(x) ((((x) - 1) << STC_TXCLK_DF_OFFSET) & STC_TXCLK_DF_MASK)
+ #define STC_TXCLK_SRC_MAX 8
+
++#define STC_TXCLK_SPDIF_ROOT 1
++
+ /* SPDIF tx rate */
+ enum spdif_txrate {
+ SPDIF_TXRATE_32000 = 0,
+ SPDIF_TXRATE_44100,
+ SPDIF_TXRATE_48000,
++ SPDIF_TXRATE_88200,
++ SPDIF_TXRATE_96000,
++ SPDIF_TXRATE_176400,
++ SPDIF_TXRATE_192000,
+ };
+-#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_48000 + 1)
++#define SPDIF_TXRATE_MAX (SPDIF_TXRATE_192000 + 1)
+
+
+ #define SPDIF_CSTATUS_BYTE 6
+@@ -173,7 +181,11 @@
+
+ #define FSL_SPDIF_RATES_PLAYBACK (SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | \
+- SNDRV_PCM_RATE_48000)
++ SNDRV_PCM_RATE_48000 | \
++ SNDRV_PCM_RATE_88200 | \
++ SNDRV_PCM_RATE_96000 | \
++ SNDRV_PCM_RATE_176400| \
++ SNDRV_PCM_RATE_192000)
+
+ #define FSL_SPDIF_RATES_CAPTURE (SNDRV_PCM_RATE_16000 | \
+ SNDRV_PCM_RATE_32000 | \
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_ssi.c linux-3.14.72/sound/soc/fsl/fsl_ssi.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_ssi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_ssi.c 2016-06-19 22:11:55.529125309 +0200
+@@ -3,7 +3,7 @@
+ *
+ * Author: Timur Tabi <timur@freescale.com>
+ *
+- * Copyright 2007-2010 Freescale Semiconductor, Inc.
++ * Copyright 2007-2015 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+@@ -35,14 +35,16 @@
+ #include <linux/module.h>
+ #include <linux/interrupt.h>
+ #include <linux/clk.h>
+-#include <linux/debugfs.h>
+ #include <linux/device.h>
+ #include <linux/delay.h>
+ #include <linux/slab.h>
+ #include <linux/spinlock.h>
++#include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+ #include <linux/of_platform.h>
++#include <linux/pm_runtime.h>
++#include <linux/busfreq-imx6.h>
+
+ #include <sound/core.h>
+ #include <sound/pcm.h>
+@@ -54,25 +56,6 @@
+ #include "fsl_ssi.h"
+ #include "imx-pcm.h"
+
+-#ifdef PPC
+-#define read_ssi(addr) in_be32(addr)
+-#define write_ssi(val, addr) out_be32(addr, val)
+-#define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
+-#else
+-#define read_ssi(addr) readl(addr)
+-#define write_ssi(val, addr) writel(val, addr)
+-/*
+- * FIXME: Proper locking should be added at write_ssi_mask caller level
+- * to ensure this register read/modify/write sequence is race free.
+- */
+-static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
+-{
+- u32 val = readl(addr);
+- val = (val & ~clear) | set;
+- writel(val, addr);
+-}
+-#endif
+-
+ /**
+ * FSLSSI_I2S_RATES: sample rates supported by the I2S
+ *
+@@ -113,8 +96,6 @@
+ #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
+ CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
+ CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
+-#define FSLSSI_SISR_MASK (FSLSSI_SIER_DBG_RX_FLAGS | FSLSSI_SIER_DBG_TX_FLAGS)
+-
+
+ enum fsl_ssi_type {
+ FSL_SSI_MCP8610,
+@@ -135,86 +116,249 @@
+ struct fsl_ssi_reg_val tx;
+ };
+
++static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case CCSR_SSI_STX0:
++ case CCSR_SSI_STX1:
++ case CCSR_SSI_SRX0:
++ case CCSR_SSI_SRX1:
++ case CCSR_SSI_SCR:
++ case CCSR_SSI_SISR:
++ case CCSR_SSI_SIER:
++ case CCSR_SSI_STCR:
++ case CCSR_SSI_SRCR:
++ case CCSR_SSI_STCCR:
++ case CCSR_SSI_SRCCR:
++ case CCSR_SSI_SFCSR:
++ case CCSR_SSI_STR:
++ case CCSR_SSI_SOR:
++ case CCSR_SSI_SACNT:
++ case CCSR_SSI_SACADD:
++ case CCSR_SSI_SACDAT:
++ case CCSR_SSI_SATAG:
++ case CCSR_SSI_STMSK:
++ case CCSR_SSI_SRMSK:
++ case CCSR_SSI_SACCST:
++ case CCSR_SSI_SACCEN:
++ case CCSR_SSI_SACCDIS:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case CCSR_SSI_STX0:
++ case CCSR_SSI_STX1:
++ case CCSR_SSI_SRX0:
++ case CCSR_SSI_SRX1:
++ case CCSR_SSI_SISR:
++ case CCSR_SSI_SFCSR:
++ case CCSR_SSI_SACADD:
++ case CCSR_SSI_SACDAT:
++ case CCSR_SSI_SATAG:
++ case CCSR_SSI_SACCST:
++ return true;
++ default:
++ return false;
++ }
++
++}
++
++static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case CCSR_SSI_STX0:
++ case CCSR_SSI_STX1:
++ case CCSR_SSI_SCR:
++ case CCSR_SSI_SISR:
++ case CCSR_SSI_SIER:
++ case CCSR_SSI_STCR:
++ case CCSR_SSI_SRCR:
++ case CCSR_SSI_STCCR:
++ case CCSR_SSI_SRCCR:
++ case CCSR_SSI_SFCSR:
++ case CCSR_SSI_STR:
++ case CCSR_SSI_SOR:
++ case CCSR_SSI_SACNT:
++ case CCSR_SSI_SACADD:
++ case CCSR_SSI_SACDAT:
++ case CCSR_SSI_SATAG:
++ case CCSR_SSI_STMSK:
++ case CCSR_SSI_SRMSK:
++ case CCSR_SSI_SACCEN:
++ case CCSR_SSI_SACCDIS:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static const struct regmap_config fsl_ssi_regconfig = {
++ .max_register = CCSR_SSI_SACCDIS,
++ .reg_bits = 32,
++ .val_bits = 32,
++ .reg_stride = 4,
++ .val_format_endian = REGMAP_ENDIAN_NATIVE,
++ .readable_reg = fsl_ssi_readable_reg,
++ .volatile_reg = fsl_ssi_volatile_reg,
++ .writeable_reg = fsl_ssi_writeable_reg,
++ .cache_type = REGCACHE_RBTREE,
++};
++
++static const struct regmap_config fsl_ssi_regconfig_ac97 = {
++ .max_register = CCSR_SSI_SACCDIS,
++ .reg_bits = 32,
++ .val_bits = 32,
++ .reg_stride = 4,
++ .val_format_endian = REGMAP_ENDIAN_NATIVE,
++};
++
++struct fsl_ssi_soc_data {
++ bool imx;
++ bool offline_config;
++ u32 sisr_write_mask;
++};
++
+ /**
+ * fsl_ssi_private: per-SSI private data
+ *
+- * @ssi: pointer to the SSI's registers
+- * @ssi_phys: physical address of the SSI registers
++ * @reg: Pointer to the regmap registers
+ * @irq: IRQ of this SSI
+- * @playback: the number of playback streams opened
+- * @capture: the number of capture streams opened
+- * @cpu_dai: the CPU DAI for this device
+- * @dev_attr: the sysfs device attribute structure
+- * @stats: SSI statistics
+- * @name: name for this device
++ * @cpu_dai_drv: CPU DAI driver for this device
++ *
++ * @dai_fmt: DAI configuration this device is currently used with
++ * @i2s_mode: i2s and network mode configuration of the device. Is used to
++ * switch between normal and i2s/network mode
++ * mode depending on the number of channels
++ * @use_dma: DMA is used or FIQ with stream filter
++ * @use_dual_fifo: DMA with support for both FIFOs used
++ * @fifo_deph: Depth of the SSI FIFOs
++ * @rxtx_reg_val: Specific register settings for receive/transmit configuration
++ *
++ * @clk: SSI clock
++ * @baudclk: SSI baud clock for master mode
++ * @baudclk_streams: Active streams that are using baudclk
++ * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
++ *
++ * @dma_params_tx: DMA transmit parameters
++ * @dma_params_rx: DMA receive parameters
++ * @ssi_phys: physical address of the SSI registers
++ *
++ * @fiq_params: FIQ stream filtering parameters
++ *
++ * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
++ *
++ * @dbg_stats: Debugging statistics
++ *
++ * @soc: SoC specifc data
+ */
+ struct fsl_ssi_private {
+- struct ccsr_ssi __iomem *ssi;
+- dma_addr_t ssi_phys;
++ struct regmap *regs;
+ unsigned int irq;
+- unsigned int fifo_depth;
+ struct snd_soc_dai_driver cpu_dai_drv;
+- struct platform_device *pdev;
+
+- enum fsl_ssi_type hw_type;
+- bool new_binding;
+- bool ssi_on_imx;
+- bool imx_ac97;
++ unsigned int dai_fmt;
++ u8 i2s_mode;
+ bool use_dma;
+- bool baudclk_locked;
+- bool irq_stats;
+- bool offline_config;
+ bool use_dual_fifo;
+- u8 i2s_mode;
+- spinlock_t baudclk_lock;
+- struct clk *baudclk;
++ bool has_ipg_clk_name;
++ unsigned int fifo_depth;
++ struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
++
+ struct clk *clk;
++ struct clk *baudclk;
++ unsigned int baudclk_streams;
++ unsigned int bitclk_freq;
++
++ /*regcache for SFCSR*/
++ u32 regcache_sfcsr;
++
++ /* DMA params */
+ struct snd_dmaengine_dai_dma_data dma_params_tx;
+ struct snd_dmaengine_dai_dma_data dma_params_rx;
+- struct imx_dma_data filter_data_tx;
+- struct imx_dma_data filter_data_rx;
++ dma_addr_t ssi_phys;
++
++ /* params for non-dma FIQ stream filtered mode */
+ struct imx_pcm_fiq_params fiq_params;
+- /* Register values for rx/tx configuration */
+- struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
+
+- struct {
+- unsigned int rfrc;
+- unsigned int tfrc;
+- unsigned int cmdau;
+- unsigned int cmddu;
+- unsigned int rxt;
+- unsigned int rdr1;
+- unsigned int rdr0;
+- unsigned int tde1;
+- unsigned int tde0;
+- unsigned int roe1;
+- unsigned int roe0;
+- unsigned int tue1;
+- unsigned int tue0;
+- unsigned int tfs;
+- unsigned int rfs;
+- unsigned int tls;
+- unsigned int rls;
+- unsigned int rff1;
+- unsigned int rff0;
+- unsigned int tfe1;
+- unsigned int tfe0;
+- } stats;
+- struct dentry *dbg_dir;
+- struct dentry *dbg_stats;
++ /* Used when using fsl-ssi as sound-card. This is only used by ppc and
++ * should be replaced with simple-sound-card. */
++ struct platform_device *pdev;
++
++ struct fsl_ssi_dbg dbg_stats;
++
++ const struct fsl_ssi_soc_data *soc;
++};
++
++/*
++ * imx51 and later SoCs have a slightly different IP that allows the
++ * SSI configuration while the SSI unit is running.
++ *
++ * More important, it is necessary on those SoCs to configure the
++ * sperate TX/RX DMA bits just before starting the stream
++ * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
++ * sends any DMA requests to the SDMA unit, otherwise it is not defined
++ * how the SDMA unit handles the DMA request.
++ *
++ * SDMA units are present on devices starting at imx35 but the imx35
++ * reference manual states that the DMA bits should not be changed
++ * while the SSI unit is running (SSIEN). So we support the necessary
++ * online configuration of fsl-ssi starting at imx51.
++ */
++
++static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
++ .imx = false,
++ .offline_config = true,
++ .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
++ CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
++ CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
++};
+
+- char name[1];
++static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
++ .imx = true,
++ .offline_config = true,
++ .sisr_write_mask = 0,
++};
++
++static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
++ .imx = true,
++ .offline_config = true,
++ .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
++ CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
++ CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
++};
++
++static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
++ .imx = true,
++ .offline_config = false,
++ .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
++ CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
+ };
+
+ static const struct of_device_id fsl_ssi_ids[] = {
+- { .compatible = "fsl,mpc8610-ssi", .data = (void *) FSL_SSI_MCP8610},
+- { .compatible = "fsl,imx51-ssi", .data = (void *) FSL_SSI_MX51},
+- { .compatible = "fsl,imx35-ssi", .data = (void *) FSL_SSI_MX35},
+- { .compatible = "fsl,imx21-ssi", .data = (void *) FSL_SSI_MX21},
++ { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
++ { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
++ { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
++ { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
+ {}
+ };
+ MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
+
++static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
++{
++ return !!(ssi_private->dai_fmt & SND_SOC_DAIFMT_AC97);
++}
++
++static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
++{
++ return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
++ SND_SOC_DAIFMT_CBS_CFS;
++}
++
+ /**
+ * fsl_ssi_isr: SSI interrupt handler
+ *
+@@ -230,278 +374,98 @@
+ static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
+ {
+ struct fsl_ssi_private *ssi_private = dev_id;
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+- irqreturn_t ret = IRQ_NONE;
++ struct regmap *regs = ssi_private->regs;
+ __be32 sisr;
+ __be32 sisr2;
+- __be32 sisr_write_mask = 0;
+-
+- switch (ssi_private->hw_type) {
+- case FSL_SSI_MX21:
+- sisr_write_mask = 0;
+- break;
+-
+- case FSL_SSI_MCP8610:
+- case FSL_SSI_MX35:
+- sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
+- CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
+- CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
+- break;
+-
+- case FSL_SSI_MX51:
+- sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
+- CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1;
+- break;
+- }
+
+ /* We got an interrupt, so read the status register to see what we
+ were interrupted for. We mask it with the Interrupt Enable register
+ so that we only check for events that we're interested in.
+ */
+- sisr = read_ssi(&ssi->sisr) & FSLSSI_SISR_MASK;
+-
+- if (sisr & CCSR_SSI_SISR_RFRC) {
+- ssi_private->stats.rfrc++;
+- ret = IRQ_HANDLED;
+- }
++ regmap_read(regs, CCSR_SSI_SISR, &sisr);
+
+- if (sisr & CCSR_SSI_SISR_TFRC) {
+- ssi_private->stats.tfrc++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_CMDAU) {
+- ssi_private->stats.cmdau++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_CMDDU) {
+- ssi_private->stats.cmddu++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_RXT) {
+- ssi_private->stats.rxt++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_RDR1) {
+- ssi_private->stats.rdr1++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_RDR0) {
+- ssi_private->stats.rdr0++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TDE1) {
+- ssi_private->stats.tde1++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TDE0) {
+- ssi_private->stats.tde0++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_ROE1) {
+- ssi_private->stats.roe1++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_ROE0) {
+- ssi_private->stats.roe0++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TUE1) {
+- ssi_private->stats.tue1++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TUE0) {
+- ssi_private->stats.tue0++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TFS) {
+- ssi_private->stats.tfs++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_RFS) {
+- ssi_private->stats.rfs++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TLS) {
+- ssi_private->stats.tls++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_RLS) {
+- ssi_private->stats.rls++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_RFF1) {
+- ssi_private->stats.rff1++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_RFF0) {
+- ssi_private->stats.rff0++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TFE1) {
+- ssi_private->stats.tfe1++;
+- ret = IRQ_HANDLED;
+- }
+-
+- if (sisr & CCSR_SSI_SISR_TFE0) {
+- ssi_private->stats.tfe0++;
+- ret = IRQ_HANDLED;
+- }
+-
+- sisr2 = sisr & sisr_write_mask;
++ sisr2 = sisr & ssi_private->soc->sisr_write_mask;
+ /* Clear the bits that we set */
+ if (sisr2)
+- write_ssi(sisr2, &ssi->sisr);
++ regmap_write(regs, CCSR_SSI_SISR, sisr2);
+
+- return ret;
+-}
+-
+-#if IS_ENABLED(CONFIG_DEBUG_FS)
+-/* Show the statistics of a flag only if its interrupt is enabled. The
+- * compiler will optimze this code to a no-op if the interrupt is not
+- * enabled.
+- */
+-#define SIER_SHOW(flag, name) \
+- do { \
+- if (FSLSSI_SISR_MASK & CCSR_SSI_SIER_##flag) \
+- seq_printf(s, #name "=%u\n", ssi_private->stats.name); \
+- } while (0)
++ fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
+
+-
+-/**
+- * fsl_sysfs_ssi_show: display SSI statistics
+- *
+- * Display the statistics for the current SSI device. To avoid confusion,
+- * we only show those counts that are enabled.
+- */
+-static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
+-{
+- struct fsl_ssi_private *ssi_private = s->private;
+-
+- SIER_SHOW(RFRC_EN, rfrc);
+- SIER_SHOW(TFRC_EN, tfrc);
+- SIER_SHOW(CMDAU_EN, cmdau);
+- SIER_SHOW(CMDDU_EN, cmddu);
+- SIER_SHOW(RXT_EN, rxt);
+- SIER_SHOW(RDR1_EN, rdr1);
+- SIER_SHOW(RDR0_EN, rdr0);
+- SIER_SHOW(TDE1_EN, tde1);
+- SIER_SHOW(TDE0_EN, tde0);
+- SIER_SHOW(ROE1_EN, roe1);
+- SIER_SHOW(ROE0_EN, roe0);
+- SIER_SHOW(TUE1_EN, tue1);
+- SIER_SHOW(TUE0_EN, tue0);
+- SIER_SHOW(TFS_EN, tfs);
+- SIER_SHOW(RFS_EN, rfs);
+- SIER_SHOW(TLS_EN, tls);
+- SIER_SHOW(RLS_EN, rls);
+- SIER_SHOW(RFF1_EN, rff1);
+- SIER_SHOW(RFF0_EN, rff0);
+- SIER_SHOW(TFE1_EN, tfe1);
+- SIER_SHOW(TFE0_EN, tfe0);
+-
+- return 0;
+-}
+-
+-static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
+-{
+- return single_open(file, fsl_ssi_stats_show, inode->i_private);
+-}
+-
+-static const struct file_operations fsl_ssi_stats_ops = {
+- .open = fsl_ssi_stats_open,
+- .read = seq_read,
+- .llseek = seq_lseek,
+- .release = single_release,
+-};
+-
+-static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
+- struct device *dev)
+-{
+- ssi_private->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
+- if (!ssi_private->dbg_dir)
+- return -ENOMEM;
+-
+- ssi_private->dbg_stats = debugfs_create_file("stats", S_IRUGO,
+- ssi_private->dbg_dir, ssi_private, &fsl_ssi_stats_ops);
+- if (!ssi_private->dbg_stats) {
+- debugfs_remove(ssi_private->dbg_dir);
+- return -ENOMEM;
+- }
+-
+- return 0;
++ return IRQ_HANDLED;
+ }
+
+-static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
+-{
+- debugfs_remove(ssi_private->dbg_stats);
+- debugfs_remove(ssi_private->dbg_dir);
+-}
+-
+-#else
+-
+-static int fsl_ssi_debugfs_create(struct fsl_ssi_private *ssi_private,
+- struct device *dev)
+-{
+- return 0;
+-}
+-
+-static void fsl_ssi_debugfs_remove(struct fsl_ssi_private *ssi_private)
+-{
+-}
+-
+-#endif /* IS_ENABLED(CONFIG_DEBUG_FS) */
+-
+ /*
+ * Enable/Disable all rx/tx config flags at once.
+ */
+ static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
+ bool enable)
+ {
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ struct regmap *regs = ssi_private->regs;
+ struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
+
+ if (enable) {
+- write_ssi_mask(&ssi->sier, 0, vals->rx.sier | vals->tx.sier);
+- write_ssi_mask(&ssi->srcr, 0, vals->rx.srcr | vals->tx.srcr);
+- write_ssi_mask(&ssi->stcr, 0, vals->rx.stcr | vals->tx.stcr);
++ regmap_update_bits(regs, CCSR_SSI_SIER,
++ vals->rx.sier | vals->tx.sier,
++ vals->rx.sier | vals->tx.sier);
++ regmap_update_bits(regs, CCSR_SSI_SRCR,
++ vals->rx.srcr | vals->tx.srcr,
++ vals->rx.srcr | vals->tx.srcr);
++ regmap_update_bits(regs, CCSR_SSI_STCR,
++ vals->rx.stcr | vals->tx.stcr,
++ vals->rx.stcr | vals->tx.stcr);
+ } else {
+- write_ssi_mask(&ssi->srcr, vals->rx.srcr | vals->tx.srcr, 0);
+- write_ssi_mask(&ssi->stcr, vals->rx.stcr | vals->tx.stcr, 0);
+- write_ssi_mask(&ssi->sier, vals->rx.sier | vals->tx.sier, 0);
++ regmap_update_bits(regs, CCSR_SSI_SRCR,
++ vals->rx.srcr | vals->tx.srcr, 0);
++ regmap_update_bits(regs, CCSR_SSI_STCR,
++ vals->rx.stcr | vals->tx.stcr, 0);
++ regmap_update_bits(regs, CCSR_SSI_SIER,
++ vals->rx.sier | vals->tx.sier, 0);
+ }
+ }
+
+ /*
++ * Calculate the bits that have to be disabled for the current stream that is
++ * getting disabled. This keeps the bits enabled that are necessary for the
++ * second stream to work if 'stream_active' is true.
++ *
++ * Detailed calculation:
++ * These are the values that need to be active after disabling. For non-active
++ * second stream, this is 0:
++ * vals_stream * !!stream_active
++ *
++ * The following computes the overall differences between the setup for the
++ * to-disable stream and the active stream, a simple XOR:
++ * vals_disable ^ (vals_stream * !!(stream_active))
++ *
++ * The full expression adds a mask on all values we care about
++ */
++#define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
++ ((vals_disable) & \
++ ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
++
++/*
+ * Enable/Disable a ssi configuration. You have to pass either
+ * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
+ */
+ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
+ struct fsl_ssi_reg_val *vals)
+ {
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ struct regmap *regs = ssi_private->regs;
+ struct fsl_ssi_reg_val *avals;
+- u32 scr_val = read_ssi(&ssi->scr);
+- int nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
++ int nr_active_streams;
++ u32 scr_val;
++ int keep_active;
++
++ regmap_read(regs, CCSR_SSI_SCR, &scr_val);
++
++ nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
+ !!(scr_val & CCSR_SSI_SCR_RE);
+
++ if (nr_active_streams - 1 > 0)
++ keep_active = 1;
++ else
++ keep_active = 0;
++
+ /* Find the other direction values rx or tx which we do not want to
+ * modify */
+ if (&ssi_private->rxtx_reg_val.rx == vals)
+@@ -511,8 +475,9 @@
+
+ /* If vals should be disabled, start with disabling the unit */
+ if (!enable) {
+- u32 scr = vals->scr & (vals->scr ^ avals->scr);
+- write_ssi_mask(&ssi->scr, scr, 0);
++ u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
++ keep_active);
++ regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
+ }
+
+ /*
+@@ -520,9 +485,9 @@
+ * reconfiguration, so we have to enable all necessary flags at once
+ * even if we do not use them later (capture and playback configuration)
+ */
+- if (ssi_private->offline_config) {
++ if (ssi_private->soc->offline_config) {
+ if ((enable && !nr_active_streams) ||
+- (!enable && nr_active_streams == 1))
++ (!enable && !keep_active))
+ fsl_ssi_rxtx_config(ssi_private, enable);
+
+ goto config_done;
+@@ -533,9 +498,9 @@
+ * (online configuration)
+ */
+ if (enable) {
+- write_ssi_mask(&ssi->sier, 0, vals->sier);
+- write_ssi_mask(&ssi->srcr, 0, vals->srcr);
+- write_ssi_mask(&ssi->stcr, 0, vals->stcr);
++ regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
++ regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
++ regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
+ } else {
+ u32 sier;
+ u32 srcr;
+@@ -551,19 +516,22 @@
+ */
+
+ /* These assignments are simply vals without bits set in avals*/
+- sier = vals->sier & (vals->sier ^ avals->sier);
+- srcr = vals->srcr & (vals->srcr ^ avals->srcr);
+- stcr = vals->stcr & (vals->stcr ^ avals->stcr);
+-
+- write_ssi_mask(&ssi->srcr, srcr, 0);
+- write_ssi_mask(&ssi->stcr, stcr, 0);
+- write_ssi_mask(&ssi->sier, sier, 0);
++ sier = fsl_ssi_disable_val(vals->sier, avals->sier,
++ keep_active);
++ srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
++ keep_active);
++ stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
++ keep_active);
++
++ regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
++ regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
++ regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
+ }
+
+ config_done:
+ /* Enabling of subunits is done after configuration */
+ if (enable)
+- write_ssi_mask(&ssi->scr, 0, vals->scr);
++ regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
+ }
+
+
+@@ -593,7 +561,7 @@
+ reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
+ reg->tx.scr = 0;
+
+- if (!ssi_private->imx_ac97) {
++ if (!fsl_ssi_is_ac97(ssi_private)) {
+ reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
+ reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
+ reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
+@@ -614,124 +582,35 @@
+
+ static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
+ {
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ struct regmap *regs = ssi_private->regs;
+
+ /*
+ * Setup the clock control register
+ */
+- write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
+- &ssi->stccr);
+- write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
+- &ssi->srccr);
++ regmap_write(regs, CCSR_SSI_STCCR,
++ CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
++ regmap_write(regs, CCSR_SSI_SRCCR,
++ CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
+
+ /*
+ * Enable AC97 mode and startup the SSI
+ */
+- write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
+- &ssi->sacnt);
+- write_ssi(0xff, &ssi->saccdis);
+- write_ssi(0x300, &ssi->saccen);
++ regmap_write(regs, CCSR_SSI_SACNT,
++ CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
++ regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
++ regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
+
+ /*
+ * Enable SSI, Transmit and Receive. AC97 has to communicate with the
+ * codec before a stream is started.
+ */
+- write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
+- CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
++ regmap_update_bits(regs, CCSR_SSI_SCR,
++ CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
++ CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
+
+- write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
++ regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
+ }
+
+-static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
+-{
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+- u8 wm;
+- int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
+-
+- fsl_ssi_setup_reg_vals(ssi_private);
+-
+- if (ssi_private->imx_ac97)
+- ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
+- else
+- ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
+-
+- /*
+- * Section 16.5 of the MPC8610 reference manual says that the SSI needs
+- * to be disabled before updating the registers we set here.
+- */
+- write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
+-
+- /*
+- * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
+- * enable the transmit and receive FIFO.
+- *
+- * FIXME: Little-endian samples require a different shift dir
+- */
+- write_ssi_mask(&ssi->scr,
+- CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
+- CCSR_SSI_SCR_TFR_CLK_DIS |
+- ssi_private->i2s_mode |
+- (synchronous ? CCSR_SSI_SCR_SYN : 0));
+-
+- write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFSI |
+- CCSR_SSI_STCR_TEFS | CCSR_SSI_STCR_TSCKP, &ssi->stcr);
+-
+- write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFSI |
+- CCSR_SSI_SRCR_REFS | CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
+-
+- /*
+- * The DC and PM bits are only used if the SSI is the clock master.
+- */
+-
+- /*
+- * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
+- * use FIFO 1. We program the transmit water to signal a DMA transfer
+- * if there are only two (or fewer) elements left in the FIFO. Two
+- * elements equals one frame (left channel, right channel). This value,
+- * however, depends on the depth of the transmit buffer.
+- *
+- * We set the watermark on the same level as the DMA burstsize. For
+- * fiq it is probably better to use the biggest possible watermark
+- * size.
+- */
+- if (ssi_private->use_dma)
+- wm = ssi_private->fifo_depth - 2;
+- else
+- wm = ssi_private->fifo_depth;
+-
+- write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
+- CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
+- &ssi->sfcsr);
+-
+- /*
+- * For ac97 interrupts are enabled with the startup of the substream
+- * because it is also running without an active substream. Normally SSI
+- * is only enabled when there is a substream.
+- */
+- if (ssi_private->imx_ac97)
+- fsl_ssi_setup_ac97(ssi_private);
+-
+- /*
+- * Set a default slot number so that there is no need for those common
+- * cases like I2S mode to call the extra set_tdm_slot() any more.
+- */
+- if (!ssi_private->imx_ac97) {
+- write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
+- CCSR_SSI_SxCCR_DC(2));
+- write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
+- CCSR_SSI_SxCCR_DC(2));
+- }
+-
+- if (ssi_private->use_dual_fifo) {
+- write_ssi_mask(&ssi->srcr, 0, CCSR_SSI_SRCR_RFEN1);
+- write_ssi_mask(&ssi->stcr, 0, CCSR_SSI_STCR_TFEN1);
+- write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_TCH_EN);
+- }
+-
+- return 0;
+-}
+-
+-
+ /**
+ * fsl_ssi_startup: create a new substream
+ *
+@@ -746,18 +625,13 @@
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_ssi_private *ssi_private =
+ snd_soc_dai_get_drvdata(rtd->cpu_dai);
+- unsigned long flags;
++ int ret;
+
+- /* First, we only do fsl_ssi_setup() when SSI is going to be active.
+- * Second, fsl_ssi_setup was already called by ac97_init earlier if
+- * the driver is in ac97 mode.
+- */
+- if (!dai->active && !ssi_private->imx_ac97) {
+- fsl_ssi_setup(ssi_private);
+- spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
+- ssi_private->baudclk_locked = false;
+- spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
+- }
++ ret = clk_prepare_enable(ssi_private->clk);
++ if (ret)
++ return ret;
++
++ pm_runtime_get_sync(dai->dev);
+
+ /* When using dual fifo mode, it is safer to ensure an even period
+ * size. If appearing to an odd number while DMA always starts its
+@@ -772,6 +646,139 @@
+ }
+
+ /**
++ * fsl_ssi_shutdown: shutdown the SSI
++ *
++ */
++static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_ssi_private *ssi_private =
++ snd_soc_dai_get_drvdata(rtd->cpu_dai);
++
++ pm_runtime_put_sync(dai->dev);
++
++ clk_disable_unprepare(ssi_private->clk);
++
++}
++
++/**
++ * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
++ *
++ * Note: This function can be only called when using SSI as DAI master
++ *
++ * Quick instruction for parameters:
++ * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
++ * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
++ */
++static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai,
++ struct snd_pcm_hw_params *hw_params)
++{
++ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++ struct regmap *regs = ssi_private->regs;
++ int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
++ u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
++ unsigned long clkrate, baudrate, tmprate;
++ u64 sub, savesub = 100000;
++ unsigned int freq;
++ bool baudclk_is_used;
++
++ /* Prefer the explicitly set bitclock frequency */
++ if (ssi_private->bitclk_freq)
++ freq = ssi_private->bitclk_freq;
++ else
++ freq = params_channels(hw_params) * 32 * params_rate(hw_params);
++
++ /* Don't apply it to any non-baudclk circumstance */
++ if (IS_ERR(ssi_private->baudclk))
++ return -EINVAL;
++
++ baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
++
++ /* It should be already enough to divide clock by setting pm alone */
++ psr = 0;
++ div2 = 0;
++
++ factor = (div2 + 1) * (7 * psr + 1) * 2;
++
++ for (i = 0; i < 255; i++) {
++ /* The bclk rate must be smaller than 1/5 sysclk rate */
++ if (factor * (i + 1) < 5)
++ continue;
++
++ tmprate = freq * factor * (i + 2);
++
++ if (baudclk_is_used)
++ clkrate = clk_get_rate(ssi_private->baudclk);
++ else
++ clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
++
++ clkrate /= factor;
++ afreq = clkrate / (i + 1);
++
++ if (freq == afreq)
++ sub = 0;
++ else if (freq / afreq == 1)
++ sub = freq - afreq;
++ else if (afreq / freq == 1)
++ sub = afreq - freq;
++ else
++ continue;
++
++ /* Calculate the fraction */
++ sub *= 100000;
++ do_div(sub, freq);
++
++ if (sub < savesub) {
++ baudrate = tmprate;
++ savesub = sub;
++ pm = i;
++ }
++
++ /* We are lucky */
++ if (savesub == 0)
++ break;
++ }
++
++ /* No proper pm found if it is still remaining the initial value */
++ if (pm == 999) {
++ dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
++ return -EINVAL;
++ }
++
++ stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
++ (psr ? CCSR_SSI_SxCCR_PSR : 0);
++ mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
++ CCSR_SSI_SxCCR_PSR;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
++ regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
++ else
++ regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
++
++ if (!baudclk_is_used) {
++ ret = clk_set_rate(ssi_private->baudclk, baudrate);
++ if (ret) {
++ dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
++ return -EINVAL;
++ }
++ }
++
++ return 0;
++}
++
++static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
++
++ ssi_private->bitclk_freq = freq;
++
++ return 0;
++}
++
++/**
+ * fsl_ssi_hw_params - program the sample size
+ *
+ * Most of the SSI registers have been programmed in the startup function,
+@@ -788,12 +795,17 @@
+ struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
+ {
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ struct regmap *regs = ssi_private->regs;
+ unsigned int channels = params_channels(hw_params);
+ unsigned int sample_size =
+ snd_pcm_format_width(params_format(hw_params));
+ u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
+- int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
++ int ret;
++ u32 scr_val;
++ int enabled;
++
++ regmap_read(regs, CCSR_SSI_SCR, &scr_val);
++ enabled = scr_val & CCSR_SSI_SCR_SSIEN;
+
+ /*
+ * If we're in synchronous mode, and the SSI is already enabled,
+@@ -802,6 +814,21 @@
+ if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
+ return 0;
+
++ if (fsl_ssi_is_i2s_master(ssi_private)) {
++ ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
++ if (ret)
++ return ret;
++
++ /* Do not enable the clock if it is already enabled */
++ if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
++ ret = clk_prepare_enable(ssi_private->baudclk);
++ if (ret)
++ return ret;
++
++ ssi_private->baudclk_streams |= BIT(substream->stream);
++ }
++ }
++
+ /*
+ * FIXME: The documentation says that SxCCR[WL] should not be
+ * modified while the SSI is enabled. The only time this can
+@@ -815,49 +842,83 @@
+ /* In synchronous mode, the SSI uses STCCR for capture */
+ if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
+ ssi_private->cpu_dai_drv.symmetric_rates)
+- write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
++ regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
++ wl);
+ else
+- write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
++ regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
++ wl);
+
+- if (!ssi_private->imx_ac97)
+- write_ssi_mask(&ssi->scr,
++ if (!fsl_ssi_is_ac97(ssi_private))
++ regmap_update_bits(regs, CCSR_SSI_SCR,
+ CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
+ channels == 1 ? 0 : ssi_private->i2s_mode);
+
+ return 0;
+ }
+
+-/**
+- * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
+- */
+-static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
++static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *cpu_dai)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct fsl_ssi_private *ssi_private =
++ snd_soc_dai_get_drvdata(rtd->cpu_dai);
++
++ if (fsl_ssi_is_i2s_master(ssi_private) &&
++ ssi_private->baudclk_streams & BIT(substream->stream)) {
++ clk_disable_unprepare(ssi_private->baudclk);
++ ssi_private->baudclk_streams &= ~BIT(substream->stream);
++ }
++
++ return 0;
++}
++
++static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private,
++ unsigned int fmt)
+ {
+- struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ struct regmap *regs = ssi_private->regs;
+ u32 strcr = 0, stcr, srcr, scr, mask;
++ u8 wm;
++
++ ssi_private->dai_fmt = fmt;
+
+- scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
+- scr |= CCSR_SSI_SCR_NET;
++ if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
++ dev_err(&ssi_private->pdev->dev, "baudclk is missing which is necessary for master mode\n");
++ return -EINVAL;
++ }
++
++ fsl_ssi_setup_reg_vals(ssi_private);
++
++ regmap_read(regs, CCSR_SSI_SCR, &scr);
++ scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
++ scr |= CCSR_SSI_SCR_SYNC_TX_FS;
+
+ mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
+ CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
+ CCSR_SSI_STCR_TEFS;
+- stcr = read_ssi(&ssi->stcr) & ~mask;
+- srcr = read_ssi(&ssi->srcr) & ~mask;
++ regmap_read(regs, CCSR_SSI_STCR, &stcr);
++ regmap_read(regs, CCSR_SSI_SRCR, &srcr);
++ stcr &= ~mask;
++ srcr &= ~mask;
+
++ ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+- ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_MASTER;
++ ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
++ regmap_update_bits(regs, CCSR_SSI_STCCR,
++ CCSR_SSI_SxCCR_DC_MASK,
++ CCSR_SSI_SxCCR_DC(2));
++ regmap_update_bits(regs, CCSR_SSI_SRCCR,
++ CCSR_SSI_SxCCR_DC_MASK,
++ CCSR_SSI_SxCCR_DC(2));
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+- ssi_private->i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
++ ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
+ break;
+ default:
+ return -EINVAL;
+ }
+- scr |= ssi_private->i2s_mode;
+
+ /* Data on rising edge of bclk, frame low, 1clk before data */
+ strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
+@@ -877,9 +938,13 @@
+ strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
+ CCSR_SSI_STCR_TXBIT0;
+ break;
++ case SND_SOC_DAIFMT_AC97:
++ ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
++ break;
+ default:
+ return -EINVAL;
+ }
++ scr |= ssi_private->i2s_mode;
+
+ /* DAI clock inversion */
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+@@ -912,6 +977,11 @@
+ case SND_SOC_DAIFMT_CBM_CFM:
+ scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
+ break;
++ case SND_SOC_DAIFMT_CBM_CFS:
++ strcr &= ~CCSR_SSI_STCR_TXDIR; /* transmit clock is external */
++ strcr |= CCSR_SSI_STCR_TFDIR; /* frame sync generated internally */
++ scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
++ break;
+ default:
+ return -EINVAL;
+ }
+@@ -925,105 +995,54 @@
+ scr |= CCSR_SSI_SCR_SYN;
+ }
+
+- write_ssi(stcr, &ssi->stcr);
+- write_ssi(srcr, &ssi->srcr);
+- write_ssi(scr, &ssi->scr);
+-
+- return 0;
+-}
+-
+-/**
+- * fsl_ssi_set_dai_sysclk - configure Digital Audio Interface bit clock
+- *
+- * Note: This function can be only called when using SSI as DAI master
+- *
+- * Quick instruction for parameters:
+- * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
+- * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
+- */
+-static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
+- int clk_id, unsigned int freq, int dir)
+-{
+- struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+- int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
+- u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
+- unsigned long flags, clkrate, baudrate, tmprate;
+- u64 sub, savesub = 100000;
+-
+- /* Don't apply it to any non-baudclk circumstance */
+- if (IS_ERR(ssi_private->baudclk))
+- return -EINVAL;
+-
+- /* It should be already enough to divide clock by setting pm alone */
+- psr = 0;
+- div2 = 0;
+-
+- factor = (div2 + 1) * (7 * psr + 1) * 2;
+-
+- for (i = 0; i < 255; i++) {
+- /* The bclk rate must be smaller than 1/5 sysclk rate */
+- if (factor * (i + 1) < 5)
+- continue;
+-
+- tmprate = freq * factor * (i + 2);
+- clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
+-
+- do_div(clkrate, factor);
+- afreq = (u32)clkrate / (i + 1);
+-
+- if (freq == afreq)
+- sub = 0;
+- else if (freq / afreq == 1)
+- sub = freq - afreq;
+- else if (afreq / freq == 1)
+- sub = afreq - freq;
+- else
+- continue;
++ regmap_write(regs, CCSR_SSI_STCR, stcr);
++ regmap_write(regs, CCSR_SSI_SRCR, srcr);
++ regmap_write(regs, CCSR_SSI_SCR, scr);
+
+- /* Calculate the fraction */
+- sub *= 100000;
+- do_div(sub, freq);
++ /*
++ * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
++ * use FIFO 1. We program the transmit water to signal a DMA transfer
++ * if there are only two (or fewer) elements left in the FIFO. Two
++ * elements equals one frame (left channel, right channel). This value,
++ * however, depends on the depth of the transmit buffer.
++ *
++ * We set the watermark on the same level as the DMA burstsize. For
++ * fiq it is probably better to use the biggest possible watermark
++ * size.
++ */
++ if (ssi_private->use_dma)
++ wm = ssi_private->fifo_depth - 2;
++ else
++ wm = ssi_private->fifo_depth;
+
+- if (sub < savesub) {
+- baudrate = tmprate;
+- savesub = sub;
+- pm = i;
+- }
++ regmap_write(regs, CCSR_SSI_SFCSR,
++ CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
++ CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
+
+- /* We are lucky */
+- if (savesub == 0)
+- break;
++ if (ssi_private->use_dual_fifo) {
++ regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
++ CCSR_SSI_SRCR_RFEN1);
++ regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
++ CCSR_SSI_STCR_TFEN1);
++ regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
++ CCSR_SSI_SCR_TCH_EN);
+ }
+
+- /* No proper pm found if it is still remaining the initial value */
+- if (pm == 999) {
+- dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
+- return -EINVAL;
+- }
++ if (fmt & SND_SOC_DAIFMT_AC97)
++ fsl_ssi_setup_ac97(ssi_private);
+
+- stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
+- (psr ? CCSR_SSI_SxCCR_PSR : 0);
+- mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 | CCSR_SSI_SxCCR_PSR;
++ return 0;
+
+- if (dir == SND_SOC_CLOCK_OUT || synchronous)
+- write_ssi_mask(&ssi->stccr, mask, stccr);
+- else
+- write_ssi_mask(&ssi->srccr, mask, stccr);
++}
+
+- spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
+- if (!ssi_private->baudclk_locked) {
+- ret = clk_set_rate(ssi_private->baudclk, baudrate);
+- if (ret) {
+- spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
+- dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
+- return -EINVAL;
+- }
+- ssi_private->baudclk_locked = true;
+- }
+- spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
++/**
++ * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
++ */
++static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
++{
++ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+
+- return 0;
++ return _fsl_ssi_set_dai_fmt(ssi_private, fmt);
+ }
+
+ /**
+@@ -1035,31 +1054,34 @@
+ u32 rx_mask, int slots, int slot_width)
+ {
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
++ struct regmap *regs = ssi_private->regs;
+ u32 val;
+
+ /* The slot number should be >= 2 if using Network mode or I2S mode */
+- val = read_ssi(&ssi->scr) & (CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET);
++ regmap_read(regs, CCSR_SSI_SCR, &val);
++ val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
+ if (val && slots < 2) {
+ dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
+ return -EINVAL;
+ }
+
+- write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_DC_MASK,
++ regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
+ CCSR_SSI_SxCCR_DC(slots));
+- write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_DC_MASK,
++ regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
+ CCSR_SSI_SxCCR_DC(slots));
+
+ /* The register SxMSKs needs SSI to provide essential clock due to
+ * hardware design. So we here temporarily enable SSI to set them.
+ */
+- val = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
+- write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN);
++ regmap_read(regs, CCSR_SSI_SCR, &val);
++ val &= CCSR_SSI_SCR_SSIEN;
++ regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
++ CCSR_SSI_SCR_SSIEN);
+
+- write_ssi(tx_mask, &ssi->stmsk);
+- write_ssi(rx_mask, &ssi->srmsk);
++ regmap_write(regs, CCSR_SSI_STMSK, tx_mask);
++ regmap_write(regs, CCSR_SSI_SRMSK, rx_mask);
+
+- write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, val);
++ regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
+
+ return 0;
+ }
+@@ -1078,11 +1100,11 @@
+ {
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
+- struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
+- unsigned long flags;
++ struct regmap *regs = ssi_private->regs;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ fsl_ssi_tx_config(ssi_private, true);
+@@ -1091,29 +1113,23 @@
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ fsl_ssi_tx_config(ssi_private, false);
+ else
+ fsl_ssi_rx_config(ssi_private, false);
+-
+- if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
+- (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) {
+- spin_lock_irqsave(&ssi_private->baudclk_lock, flags);
+- ssi_private->baudclk_locked = false;
+- spin_unlock_irqrestore(&ssi_private->baudclk_lock, flags);
+- }
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+- if (ssi_private->imx_ac97) {
++ if (fsl_ssi_is_ac97(ssi_private)) {
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+- write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
++ regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
+ else
+- write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
++ regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
+ }
+
+ return 0;
+@@ -1123,7 +1139,7 @@
+ {
+ struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
+
+- if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
++ if (ssi_private->soc->imx && ssi_private->use_dma) {
+ dai->playback_dma_data = &ssi_private->dma_params_tx;
+ dai->capture_dma_data = &ssi_private->dma_params_rx;
+ }
+@@ -1133,7 +1149,9 @@
+
+ static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
+ .startup = fsl_ssi_startup,
++ .shutdown = fsl_ssi_shutdown,
+ .hw_params = fsl_ssi_hw_params,
++ .hw_free = fsl_ssi_hw_free,
+ .set_fmt = fsl_ssi_set_dai_fmt,
+ .set_sysclk = fsl_ssi_set_dai_sysclk,
+ .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
+@@ -1144,12 +1162,14 @@
+ static struct snd_soc_dai_driver fsl_ssi_dai_template = {
+ .probe = fsl_ssi_dai_probe,
+ .playback = {
++ .stream_name = "CPU-Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = FSLSSI_I2S_RATES,
+ .formats = FSLSSI_I2S_FORMATS,
+ },
+ .capture = {
++ .stream_name = "CPU-Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = FSLSSI_I2S_RATES,
+@@ -1163,6 +1183,7 @@
+ };
+
+ static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
++ .probe = fsl_ssi_dai_probe,
+ .ac97_control = 1,
+ .playback = {
+ .stream_name = "AC97 Playback",
+@@ -1184,15 +1205,10 @@
+
+ static struct fsl_ssi_private *fsl_ac97_data;
+
+-static void fsl_ssi_ac97_init(void)
+-{
+- fsl_ssi_setup(fsl_ac97_data);
+-}
+-
+ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
+ unsigned short val)
+ {
+- struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
++ struct regmap *regs = fsl_ac97_data->regs;
+ unsigned int lreg;
+ unsigned int lval;
+
+@@ -1201,12 +1217,12 @@
+
+
+ lreg = reg << 12;
+- write_ssi(lreg, &ssi->sacadd);
++ regmap_write(regs, CCSR_SSI_SACADD, lreg);
+
+ lval = val << 4;
+- write_ssi(lval , &ssi->sacdat);
++ regmap_write(regs, CCSR_SSI_SACDAT, lval);
+
+- write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
++ regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
+ CCSR_SSI_SACNT_WR);
+ udelay(100);
+ }
+@@ -1214,19 +1230,21 @@
+ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
+ unsigned short reg)
+ {
+- struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
++ struct regmap *regs = fsl_ac97_data->regs;
+
+ unsigned short val = -1;
++ u32 reg_val;
+ unsigned int lreg;
+
+ lreg = (reg & 0x7f) << 12;
+- write_ssi(lreg, &ssi->sacadd);
+- write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
++ regmap_write(regs, CCSR_SSI_SACADD, lreg);
++ regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
+ CCSR_SSI_SACNT_RD);
+
+ udelay(100);
+
+- val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
++ regmap_read(regs, CCSR_SSI_SACDAT, &reg_val);
++ val = (reg_val >> 4) & 0xffff;
+
+ return val;
+ }
+@@ -1251,20 +1269,113 @@
+ }
+ }
+
++static int fsl_ssi_imx_probe(struct platform_device *pdev,
++ struct fsl_ssi_private *ssi_private, void __iomem *iomem)
++{
++ struct device_node *np = pdev->dev.of_node;
++ u32 dmas[4];
++ int ret;
++
++ if (ssi_private->has_ipg_clk_name)
++ ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
++ else
++ ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
++ if (IS_ERR(ssi_private->clk)) {
++ ret = PTR_ERR(ssi_private->clk);
++ dev_err(&pdev->dev, "could not get clock: %d\n", ret);
++ return ret;
++ }
++
++ if (!ssi_private->has_ipg_clk_name) {
++ ret = clk_prepare_enable(ssi_private->clk);
++ if (ret) {
++ dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
++ return ret;
++ }
++ }
++
++ /* For those SLAVE implementations, we ingore non-baudclk cases
++ * and, instead, abandon MASTER mode that needs baud clock.
++ */
++ ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
++ if (IS_ERR(ssi_private->baudclk))
++ dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
++ PTR_ERR(ssi_private->baudclk));
++
++ /*
++ * We have burstsize be "fifo_depth - 2" to match the SSI
++ * watermark setting in fsl_ssi_startup().
++ */
++ ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
++ ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
++ ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
++ ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
++
++ ret = !of_property_read_u32_array(np, "dmas", dmas, 4);
++ if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
++ ssi_private->use_dual_fifo = true;
++ /* When using dual fifo mode, we need to keep watermark
++ * as even numbers due to dma script limitation.
++ */
++ ssi_private->dma_params_tx.maxburst &= ~0x1;
++ ssi_private->dma_params_rx.maxburst &= ~0x1;
++ }
++
++ if (!ssi_private->use_dma) {
++
++ /*
++ * Some boards use an incompatible codec. To get it
++ * working, we are using imx-fiq-pcm-audio, that
++ * can handle those codecs. DMA is not possible in this
++ * situation.
++ */
++
++ ssi_private->fiq_params.irq = ssi_private->irq;
++ ssi_private->fiq_params.base = iomem;
++ ssi_private->fiq_params.dma_params_rx =
++ &ssi_private->dma_params_rx;
++ ssi_private->fiq_params.dma_params_tx =
++ &ssi_private->dma_params_tx;
++
++ ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
++ if (ret)
++ goto error_pcm;
++ } else {
++ ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
++ if (ret)
++ goto error_pcm;
++ }
++
++ return 0;
++
++error_pcm:
++
++ if (!ssi_private->has_ipg_clk_name)
++ clk_disable_unprepare(ssi_private->clk);
++ return ret;
++}
++
++static void fsl_ssi_imx_clean(struct platform_device *pdev,
++ struct fsl_ssi_private *ssi_private)
++{
++ if (!ssi_private->use_dma)
++ imx_pcm_fiq_exit(pdev);
++ if (!ssi_private->has_ipg_clk_name)
++ clk_disable_unprepare(ssi_private->clk);
++}
++
+ static int fsl_ssi_probe(struct platform_device *pdev)
+ {
+ struct fsl_ssi_private *ssi_private;
+ int ret = 0;
+- struct device_attribute *dev_attr = NULL;
+ struct device_node *np = pdev->dev.of_node;
+ const struct of_device_id *of_id;
+- enum fsl_ssi_type hw_type;
+ const char *p, *sprop;
+ const uint32_t *iprop;
+ struct resource res;
++ void __iomem *iomem;
+ char name[64];
+- bool shared;
+- bool ac97 = false;
++ const struct regmap_config *pfsl_ssi_regconfig;
+
+ /* SSIs that are not connected on the board should have a
+ * status = "disabled"
+@@ -1274,39 +1385,35 @@
+ return -ENODEV;
+
+ of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
+- if (!of_id)
+- return -EINVAL;
+- hw_type = (enum fsl_ssi_type) of_id->data;
+-
+- sprop = of_get_property(np, "fsl,mode", NULL);
+- if (!sprop) {
+- dev_err(&pdev->dev, "fsl,mode property is necessary\n");
++ if (!of_id || !of_id->data)
+ return -EINVAL;
+- }
+- if (!strcmp(sprop, "ac97-slave"))
+- ac97 = true;
+
+- /* The DAI name is the last part of the full name of the node. */
+- p = strrchr(np->full_name, '/') + 1;
+- ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
+- GFP_KERNEL);
++ ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
++ GFP_KERNEL);
+ if (!ssi_private) {
+ dev_err(&pdev->dev, "could not allocate DAI object\n");
+ return -ENOMEM;
+ }
+
+- strcpy(ssi_private->name, p);
++ ssi_private->soc = of_id->data;
++
++ sprop = of_get_property(np, "fsl,mode", NULL);
++ if (sprop) {
++ if (!strcmp(sprop, "ac97-slave"))
++ ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97 | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFS;
++ else if (!strcmp(sprop, "i2s-slave"))
++ ssi_private->dai_fmt = SND_SOC_DAIFMT_I2S |
++ SND_SOC_DAIFMT_CBM_CFM;
++ }
+
+ ssi_private->use_dma = !of_property_read_bool(np,
+ "fsl,fiq-stream-filter");
+- ssi_private->hw_type = hw_type;
+
+- if (ac97) {
++ if (fsl_ssi_is_ac97(ssi_private)) {
+ memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
+ sizeof(fsl_ssi_ac97_dai));
+
+ fsl_ac97_data = ssi_private;
+- ssi_private->imx_ac97 = true;
+
+ snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
+ } else {
+@@ -1314,7 +1421,7 @@
+ memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
+ sizeof(fsl_ssi_dai_template));
+ }
+- ssi_private->cpu_dai_drv.name = ssi_private->name;
++ ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
+
+ /* Get the addresses and IRQ */
+ ret = of_address_to_resource(np, 0, &res);
+@@ -1322,12 +1429,33 @@
+ dev_err(&pdev->dev, "could not determine device resources\n");
+ return ret;
+ }
+- ssi_private->ssi = of_iomap(np, 0);
+- if (!ssi_private->ssi) {
++ ssi_private->ssi_phys = res.start;
++
++ iomem = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
++ if (!iomem) {
+ dev_err(&pdev->dev, "could not map device resources\n");
+ return -ENOMEM;
+ }
+- ssi_private->ssi_phys = res.start;
++
++ if (!fsl_ssi_is_ac97(ssi_private))
++ pfsl_ssi_regconfig = &fsl_ssi_regconfig;
++ else
++ pfsl_ssi_regconfig = &fsl_ssi_regconfig_ac97;
++
++ ret = of_property_match_string(np, "clock-names", "ipg");
++ if (ret < 0) {
++ ssi_private->has_ipg_clk_name = false;
++ ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
++ pfsl_ssi_regconfig);
++ } else {
++ ssi_private->has_ipg_clk_name = true;
++ ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
++ "ipg", iomem, pfsl_ssi_regconfig);
++ }
++ if (IS_ERR(ssi_private->regs)) {
++ dev_err(&pdev->dev, "Failed to init register map\n");
++ return PTR_ERR(ssi_private->regs);
++ }
+
+ ssi_private->irq = irq_of_parse_and_map(np, 0);
+ if (!ssi_private->irq) {
+@@ -1350,180 +1478,51 @@
+ /* Older 8610 DTs didn't have the fifo-depth property */
+ ssi_private->fifo_depth = 8;
+
+- ssi_private->baudclk_locked = false;
+- spin_lock_init(&ssi_private->baudclk_lock);
+-
+- /*
+- * imx51 and later SoCs have a slightly different IP that allows the
+- * SSI configuration while the SSI unit is running.
+- *
+- * More important, it is necessary on those SoCs to configure the
+- * sperate TX/RX DMA bits just before starting the stream
+- * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
+- * sends any DMA requests to the SDMA unit, otherwise it is not defined
+- * how the SDMA unit handles the DMA request.
+- *
+- * SDMA units are present on devices starting at imx35 but the imx35
+- * reference manual states that the DMA bits should not be changed
+- * while the SSI unit is running (SSIEN). So we support the necessary
+- * online configuration of fsl-ssi starting at imx51.
+- */
+- switch (hw_type) {
+- case FSL_SSI_MCP8610:
+- case FSL_SSI_MX21:
+- case FSL_SSI_MX35:
+- ssi_private->offline_config = true;
+- break;
+- case FSL_SSI_MX51:
+- ssi_private->offline_config = false;
+- break;
+- }
++ pm_runtime_enable(&pdev->dev);
+
+- if (hw_type == FSL_SSI_MX21 || hw_type == FSL_SSI_MX51 ||
+- hw_type == FSL_SSI_MX35) {
+- u32 dma_events[2], dmas[4];
+- ssi_private->ssi_on_imx = true;
++ dev_set_drvdata(&pdev->dev, ssi_private);
+
+- ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
+- if (IS_ERR(ssi_private->clk)) {
+- ret = PTR_ERR(ssi_private->clk);
+- dev_err(&pdev->dev, "could not get clock: %d\n", ret);
+- goto error_irqmap;
+- }
+- ret = clk_prepare_enable(ssi_private->clk);
+- if (ret) {
+- dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
+- ret);
++ if (ssi_private->soc->imx) {
++ ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
++ if (ret)
+ goto error_irqmap;
+- }
+-
+- /* For those SLAVE implementations, we ingore non-baudclk cases
+- * and, instead, abandon MASTER mode that needs baud clock.
+- */
+- ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
+- if (IS_ERR(ssi_private->baudclk))
+- dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
+- PTR_ERR(ssi_private->baudclk));
+- else
+- clk_prepare_enable(ssi_private->baudclk);
+-
+- /*
+- * We have burstsize be "fifo_depth - 2" to match the SSI
+- * watermark setting in fsl_ssi_startup().
+- */
+- ssi_private->dma_params_tx.maxburst =
+- ssi_private->fifo_depth - 2;
+- ssi_private->dma_params_rx.maxburst =
+- ssi_private->fifo_depth - 2;
+- ssi_private->dma_params_tx.addr =
+- ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
+- ssi_private->dma_params_rx.addr =
+- ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
+- ssi_private->dma_params_tx.filter_data =
+- &ssi_private->filter_data_tx;
+- ssi_private->dma_params_rx.filter_data =
+- &ssi_private->filter_data_rx;
+- if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
+- ssi_private->use_dma) {
+- /*
+- * FIXME: This is a temporary solution until all
+- * necessary dma drivers support the generic dma
+- * bindings.
+- */
+- ret = of_property_read_u32_array(pdev->dev.of_node,
+- "fsl,ssi-dma-events", dma_events, 2);
+- if (ret && ssi_private->use_dma) {
+- dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
+- goto error_clk;
+- }
+- }
+- /* Should this be merge with the above? */
+- if (!of_property_read_u32_array(pdev->dev.of_node, "dmas", dmas, 4)
+- && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
+- ssi_private->use_dual_fifo = true;
+- /* When using dual fifo mode, we need to keep watermark
+- * as even numbers due to dma script limitation.
+- */
+- ssi_private->dma_params_tx.maxburst &= ~0x1;
+- ssi_private->dma_params_rx.maxburst &= ~0x1;
+- }
++ }
+
+- shared = of_device_is_compatible(of_get_parent(np),
+- "fsl,spba-bus");
++ if (fsl_ssi_is_ac97(ssi_private)) {
++ ret = clk_prepare_enable(fsl_ac97_data->clk);
++ if (ret)
++ goto error_asoc_register;
++ }
+
+- imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
+- dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
+- imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
+- dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
++ ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
++ &ssi_private->cpu_dai_drv, 1);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
++ goto error_asoc_register;
+ }
+
+- /*
+- * Enable interrupts only for MCP8610 and MX51. The other MXs have
+- * different writeable interrupt status registers.
+- */
+ if (ssi_private->use_dma) {
+- /* The 'name' should not have any slashes in it. */
+ ret = devm_request_irq(&pdev->dev, ssi_private->irq,
+- fsl_ssi_isr, 0, ssi_private->name,
++ fsl_ssi_isr, 0, dev_name(&pdev->dev),
+ ssi_private);
+- ssi_private->irq_stats = true;
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not claim irq %u\n",
+ ssi_private->irq);
+- goto error_clk;
++ goto error_irq;
+ }
+ }
+
+- /* Register with ASoC */
+- dev_set_drvdata(&pdev->dev, ssi_private);
+-
+- ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
+- &ssi_private->cpu_dai_drv, 1);
+- if (ret) {
+- dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
+- goto error_dev;
+- }
+-
+- ret = fsl_ssi_debugfs_create(ssi_private, &pdev->dev);
++ ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
+ if (ret)
+- goto error_dbgfs;
+-
+- if (ssi_private->ssi_on_imx) {
+- if (!ssi_private->use_dma) {
+-
+- /*
+- * Some boards use an incompatible codec. To get it
+- * working, we are using imx-fiq-pcm-audio, that
+- * can handle those codecs. DMA is not possible in this
+- * situation.
+- */
+-
+- ssi_private->fiq_params.irq = ssi_private->irq;
+- ssi_private->fiq_params.base = ssi_private->ssi;
+- ssi_private->fiq_params.dma_params_rx =
+- &ssi_private->dma_params_rx;
+- ssi_private->fiq_params.dma_params_tx =
+- &ssi_private->dma_params_tx;
+-
+- ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
+- if (ret)
+- goto error_pcm;
+- } else {
+- ret = imx_pcm_dma_init(pdev);
+- if (ret)
+- goto error_pcm;
+- }
+- }
++ goto error_asoc_register;
+
+ /*
+ * If codec-handle property is missing from SSI node, we assume
+ * that the machine driver uses new binding which does not require
+ * SSI driver to trigger machine driver's probe.
+ */
+- if (!of_get_property(np, "codec-handle", NULL)) {
+- ssi_private->new_binding = true;
++ if (!of_get_property(np, "codec-handle", NULL))
+ goto done;
+- }
+
+ /* Trigger the machine driver's probe function. The platform driver
+ * name of the machine driver is taken from /compatible property of the
+@@ -1543,37 +1542,27 @@
+ if (IS_ERR(ssi_private->pdev)) {
+ ret = PTR_ERR(ssi_private->pdev);
+ dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
+- goto error_dai;
++ goto error_sound_card;
+ }
+
+ done:
+- if (ssi_private->imx_ac97)
+- fsl_ssi_ac97_init();
++ if (ssi_private->dai_fmt)
++ _fsl_ssi_set_dai_fmt(ssi_private, ssi_private->dai_fmt);
+
+ return 0;
+
+-error_dai:
+- if (ssi_private->ssi_on_imx && !ssi_private->use_dma)
+- imx_pcm_fiq_exit(pdev);
+-
+-error_pcm:
+- fsl_ssi_debugfs_remove(ssi_private);
++error_sound_card:
++ fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
+
+-error_dbgfs:
++error_irq:
+ snd_soc_unregister_component(&pdev->dev);
+
+-error_dev:
+- device_remove_file(&pdev->dev, dev_attr);
+-
+-error_clk:
+- if (ssi_private->ssi_on_imx) {
+- if (!IS_ERR(ssi_private->baudclk))
+- clk_disable_unprepare(ssi_private->baudclk);
+- clk_disable_unprepare(ssi_private->clk);
+- }
++error_asoc_register:
++ if (ssi_private->soc->imx)
++ fsl_ssi_imx_clean(pdev, ssi_private);
+
+ error_irqmap:
+- if (ssi_private->irq_stats)
++ if (ssi_private->use_dma)
+ irq_dispose_mapping(ssi_private->irq);
+
+ return ret;
+@@ -1583,27 +1572,79 @@
+ {
+ struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
+
+- fsl_ssi_debugfs_remove(ssi_private);
++ fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
+
+- if (!ssi_private->new_binding)
++ if (ssi_private->pdev)
+ platform_device_unregister(ssi_private->pdev);
+ snd_soc_unregister_component(&pdev->dev);
+- if (ssi_private->ssi_on_imx) {
+- if (!IS_ERR(ssi_private->baudclk))
+- clk_disable_unprepare(ssi_private->baudclk);
+- clk_disable_unprepare(ssi_private->clk);
+- }
+- if (ssi_private->irq_stats)
++
++ if (ssi_private->soc->imx)
++ fsl_ssi_imx_clean(pdev, ssi_private);
++
++ if (ssi_private->use_dma)
+ irq_dispose_mapping(ssi_private->irq);
+
+ return 0;
+ }
+
++#ifdef CONFIG_PM_RUNTIME
++static int fsl_ssi_runtime_resume(struct device *dev)
++{
++ request_bus_freq(BUS_FREQ_AUDIO);
++ return 0;
++}
++
++static int fsl_ssi_runtime_suspend(struct device *dev)
++{
++ release_bus_freq(BUS_FREQ_AUDIO);
++ return 0;
++}
++#endif
++
++#ifdef CONFIG_PM_SLEEP
++static int fsl_ssi_suspend(struct device *dev)
++{
++ struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
++ struct regmap *regs = ssi_private->regs;
++
++ regmap_read(regs, CCSR_SSI_SFCSR,
++ &ssi_private->regcache_sfcsr);
++
++ regcache_cache_only(regs, true);
++ regcache_mark_dirty(regs);
++
++ return 0;
++}
++
++static int fsl_ssi_resume(struct device *dev)
++{
++ struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
++ struct regmap *regs = ssi_private->regs;
++
++ regcache_cache_only(regs, false);
++
++ regmap_update_bits(regs, CCSR_SSI_SFCSR,
++ CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
++ CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
++ ssi_private->regcache_sfcsr);
++
++ return regcache_sync(regs);
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops fsl_ssi_pm = {
++ SET_RUNTIME_PM_OPS(fsl_ssi_runtime_suspend,
++ fsl_ssi_runtime_resume,
++ NULL)
++ SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
++};
++
+ static struct platform_driver fsl_ssi_driver = {
+ .driver = {
+ .name = "fsl-ssi-dai",
+ .owner = THIS_MODULE,
+ .of_match_table = fsl_ssi_ids,
++ .pm = &fsl_ssi_pm,
+ },
+ .probe = fsl_ssi_probe,
+ .remove = fsl_ssi_remove,
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_ssi_dbg.c linux-3.14.72/sound/soc/fsl/fsl_ssi_dbg.c
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_ssi_dbg.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/fsl_ssi_dbg.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,163 @@
++/*
++ * Freescale SSI ALSA SoC Digital Audio Interface (DAI) debugging functions
++ *
++ * Copyright 2014 Markus Pargmann <mpa@pengutronix.de>, Pengutronix
++ *
++ * Splitted from fsl_ssi.c
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/debugfs.h>
++#include <linux/device.h>
++#include <linux/kernel.h>
++
++#include "fsl_ssi.h"
++
++void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *dbg, u32 sisr)
++{
++ if (sisr & CCSR_SSI_SISR_RFRC)
++ dbg->stats.rfrc++;
++
++ if (sisr & CCSR_SSI_SISR_TFRC)
++ dbg->stats.tfrc++;
++
++ if (sisr & CCSR_SSI_SISR_CMDAU)
++ dbg->stats.cmdau++;
++
++ if (sisr & CCSR_SSI_SISR_CMDDU)
++ dbg->stats.cmddu++;
++
++ if (sisr & CCSR_SSI_SISR_RXT)
++ dbg->stats.rxt++;
++
++ if (sisr & CCSR_SSI_SISR_RDR1)
++ dbg->stats.rdr1++;
++
++ if (sisr & CCSR_SSI_SISR_RDR0)
++ dbg->stats.rdr0++;
++
++ if (sisr & CCSR_SSI_SISR_TDE1)
++ dbg->stats.tde1++;
++
++ if (sisr & CCSR_SSI_SISR_TDE0)
++ dbg->stats.tde0++;
++
++ if (sisr & CCSR_SSI_SISR_ROE1)
++ dbg->stats.roe1++;
++
++ if (sisr & CCSR_SSI_SISR_ROE0)
++ dbg->stats.roe0++;
++
++ if (sisr & CCSR_SSI_SISR_TUE1)
++ dbg->stats.tue1++;
++
++ if (sisr & CCSR_SSI_SISR_TUE0)
++ dbg->stats.tue0++;
++
++ if (sisr & CCSR_SSI_SISR_TFS)
++ dbg->stats.tfs++;
++
++ if (sisr & CCSR_SSI_SISR_RFS)
++ dbg->stats.rfs++;
++
++ if (sisr & CCSR_SSI_SISR_TLS)
++ dbg->stats.tls++;
++
++ if (sisr & CCSR_SSI_SISR_RLS)
++ dbg->stats.rls++;
++
++ if (sisr & CCSR_SSI_SISR_RFF1)
++ dbg->stats.rff1++;
++
++ if (sisr & CCSR_SSI_SISR_RFF0)
++ dbg->stats.rff0++;
++
++ if (sisr & CCSR_SSI_SISR_TFE1)
++ dbg->stats.tfe1++;
++
++ if (sisr & CCSR_SSI_SISR_TFE0)
++ dbg->stats.tfe0++;
++}
++
++/* Show the statistics of a flag only if its interrupt is enabled. The
++ * compiler will optimze this code to a no-op if the interrupt is not
++ * enabled.
++ */
++#define SIER_SHOW(flag, name) \
++ do { \
++ if (CCSR_SSI_SIER_##flag) \
++ seq_printf(s, #name "=%u\n", ssi_dbg->stats.name); \
++ } while (0)
++
++
++/**
++ * fsl_sysfs_ssi_show: display SSI statistics
++ *
++ * Display the statistics for the current SSI device. To avoid confusion,
++ * we only show those counts that are enabled.
++ */
++static int fsl_ssi_stats_show(struct seq_file *s, void *unused)
++{
++ struct fsl_ssi_dbg *ssi_dbg = s->private;
++
++ SIER_SHOW(RFRC_EN, rfrc);
++ SIER_SHOW(TFRC_EN, tfrc);
++ SIER_SHOW(CMDAU_EN, cmdau);
++ SIER_SHOW(CMDDU_EN, cmddu);
++ SIER_SHOW(RXT_EN, rxt);
++ SIER_SHOW(RDR1_EN, rdr1);
++ SIER_SHOW(RDR0_EN, rdr0);
++ SIER_SHOW(TDE1_EN, tde1);
++ SIER_SHOW(TDE0_EN, tde0);
++ SIER_SHOW(ROE1_EN, roe1);
++ SIER_SHOW(ROE0_EN, roe0);
++ SIER_SHOW(TUE1_EN, tue1);
++ SIER_SHOW(TUE0_EN, tue0);
++ SIER_SHOW(TFS_EN, tfs);
++ SIER_SHOW(RFS_EN, rfs);
++ SIER_SHOW(TLS_EN, tls);
++ SIER_SHOW(RLS_EN, rls);
++ SIER_SHOW(RFF1_EN, rff1);
++ SIER_SHOW(RFF0_EN, rff0);
++ SIER_SHOW(TFE1_EN, tfe1);
++ SIER_SHOW(TFE0_EN, tfe0);
++
++ return 0;
++}
++
++static int fsl_ssi_stats_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, fsl_ssi_stats_show, inode->i_private);
++}
++
++static const struct file_operations fsl_ssi_stats_ops = {
++ .open = fsl_ssi_stats_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev)
++{
++ ssi_dbg->dbg_dir = debugfs_create_dir(dev_name(dev), NULL);
++ if (!ssi_dbg->dbg_dir)
++ return -ENOMEM;
++
++ ssi_dbg->dbg_stats = debugfs_create_file("stats", S_IRUGO,
++ ssi_dbg->dbg_dir, ssi_dbg, &fsl_ssi_stats_ops);
++ if (!ssi_dbg->dbg_stats) {
++ debugfs_remove(ssi_dbg->dbg_dir);
++ return -ENOMEM;
++ }
++
++ return 0;
++}
++
++void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
++{
++ debugfs_remove(ssi_dbg->dbg_stats);
++ debugfs_remove(ssi_dbg->dbg_dir);
++}
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/fsl_ssi.h linux-3.14.72/sound/soc/fsl/fsl_ssi.h
+--- linux-3.14.72.orig/sound/soc/fsl/fsl_ssi.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/fsl_ssi.h 2016-06-19 22:11:55.529125309 +0200
+@@ -12,33 +12,32 @@
+ #ifndef _MPC8610_I2S_H
+ #define _MPC8610_I2S_H
+
+-/* SSI Register Map */
+-struct ccsr_ssi {
+- __be32 stx0; /* 0x.0000 - SSI Transmit Data Register 0 */
+- __be32 stx1; /* 0x.0004 - SSI Transmit Data Register 1 */
+- __be32 srx0; /* 0x.0008 - SSI Receive Data Register 0 */
+- __be32 srx1; /* 0x.000C - SSI Receive Data Register 1 */
+- __be32 scr; /* 0x.0010 - SSI Control Register */
+- __be32 sisr; /* 0x.0014 - SSI Interrupt Status Register Mixed */
+- __be32 sier; /* 0x.0018 - SSI Interrupt Enable Register */
+- __be32 stcr; /* 0x.001C - SSI Transmit Configuration Register */
+- __be32 srcr; /* 0x.0020 - SSI Receive Configuration Register */
+- __be32 stccr; /* 0x.0024 - SSI Transmit Clock Control Register */
+- __be32 srccr; /* 0x.0028 - SSI Receive Clock Control Register */
+- __be32 sfcsr; /* 0x.002C - SSI FIFO Control/Status Register */
+- __be32 str; /* 0x.0030 - SSI Test Register */
+- __be32 sor; /* 0x.0034 - SSI Option Register */
+- __be32 sacnt; /* 0x.0038 - SSI AC97 Control Register */
+- __be32 sacadd; /* 0x.003C - SSI AC97 Command Address Register */
+- __be32 sacdat; /* 0x.0040 - SSI AC97 Command Data Register */
+- __be32 satag; /* 0x.0044 - SSI AC97 Tag Register */
+- __be32 stmsk; /* 0x.0048 - SSI Transmit Time Slot Mask Register */
+- __be32 srmsk; /* 0x.004C - SSI Receive Time Slot Mask Register */
+- __be32 saccst; /* 0x.0050 - SSI AC97 Channel Status Register */
+- __be32 saccen; /* 0x.0054 - SSI AC97 Channel Enable Register */
+- __be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */
+-};
++/* SSI registers */
++#define CCSR_SSI_STX0 0x00
++#define CCSR_SSI_STX1 0x04
++#define CCSR_SSI_SRX0 0x08
++#define CCSR_SSI_SRX1 0x0c
++#define CCSR_SSI_SCR 0x10
++#define CCSR_SSI_SISR 0x14
++#define CCSR_SSI_SIER 0x18
++#define CCSR_SSI_STCR 0x1c
++#define CCSR_SSI_SRCR 0x20
++#define CCSR_SSI_STCCR 0x24
++#define CCSR_SSI_SRCCR 0x28
++#define CCSR_SSI_SFCSR 0x2c
++#define CCSR_SSI_STR 0x30
++#define CCSR_SSI_SOR 0x34
++#define CCSR_SSI_SACNT 0x38
++#define CCSR_SSI_SACADD 0x3c
++#define CCSR_SSI_SACDAT 0x40
++#define CCSR_SSI_SATAG 0x44
++#define CCSR_SSI_STMSK 0x48
++#define CCSR_SSI_SRMSK 0x4c
++#define CCSR_SSI_SACCST 0x50
++#define CCSR_SSI_SACCEN 0x54
++#define CCSR_SSI_SACCDIS 0x58
+
++#define CCSR_SSI_SCR_SYNC_TX_FS 0x00001000
+ #define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800
+ #define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400
+ #define CCSR_SSI_SCR_TCH_EN 0x00000100
+@@ -206,5 +205,64 @@
+ #define CCSR_SSI_SACNT_FV 0x00000002
+ #define CCSR_SSI_SACNT_AC97EN 0x00000001
+
+-#endif
+
++struct device;
++
++#if IS_ENABLED(CONFIG_DEBUG_FS)
++
++struct fsl_ssi_dbg {
++ struct dentry *dbg_dir;
++ struct dentry *dbg_stats;
++
++ struct {
++ unsigned int rfrc;
++ unsigned int tfrc;
++ unsigned int cmdau;
++ unsigned int cmddu;
++ unsigned int rxt;
++ unsigned int rdr1;
++ unsigned int rdr0;
++ unsigned int tde1;
++ unsigned int tde0;
++ unsigned int roe1;
++ unsigned int roe0;
++ unsigned int tue1;
++ unsigned int tue0;
++ unsigned int tfs;
++ unsigned int rfs;
++ unsigned int tls;
++ unsigned int rls;
++ unsigned int rff1;
++ unsigned int rff0;
++ unsigned int tfe1;
++ unsigned int tfe0;
++ } stats;
++};
++
++void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *ssi_dbg, u32 sisr);
++
++int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg, struct device *dev);
++
++void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg);
++
++#else
++
++struct fsl_ssi_dbg {
++};
++
++static inline void fsl_ssi_dbg_isr(struct fsl_ssi_dbg *stats, u32 sisr)
++{
++}
++
++static inline int fsl_ssi_debugfs_create(struct fsl_ssi_dbg *ssi_dbg,
++ struct device *dev)
++{
++ return 0;
++}
++
++static inline void fsl_ssi_debugfs_remove(struct fsl_ssi_dbg *ssi_dbg)
++{
++}
++#endif /* ! IS_ENABLED(CONFIG_DEBUG_FS) */
++
++#endif
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/hdmi_pcm.S linux-3.14.72/sound/soc/fsl/hdmi_pcm.S
+--- linux-3.14.72.orig/sound/soc/fsl/hdmi_pcm.S 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/hdmi_pcm.S 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,246 @@
++/**
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++.section .text
++
++.global hdmi_dma_copy_16_neon_lut
++.global hdmi_dma_copy_16_neon_fast
++.global hdmi_dma_copy_24_neon_lut
++.global hdmi_dma_copy_24_neon_fast
++
++
++/**
++ * hdmi_dma_copy_16_neon_lut
++ * Convert pcm sample to iec sample. Pcm sample is 16 bits.
++ * Frame index's between 0 and 47 inclusively. Channel count can be 1, 2, 4, 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_16_neon_lut(unsigned short *src, unsigned int *dst,
++ * int samples, unsigned char *lookup_table);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM16 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ * lookup_table Preconstructed header table. Channels interleaved.
++ */
++
++hdmi_dma_copy_16_neon_lut:
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d6, r12
++
++hdmi_dma_copy_16_neon_lut_start:
++
++ /* get 8 samples to q0 */
++ vld1.16 {d0, d1}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q1, q0 /* count of 1s */
++ vpadd.i8 d2, d2, d3 /* only care about the LST in every element */
++ vand d2, d2, d6 /* clear other bits while keep the least bit */
++ vshl.u8 d2, d2, #3 /* bit p: d2 = d2 << 3 */
++
++ /* get packet header */
++ vld1.8 {d5}, [r3]!
++ veor d4, d5, d2 /* xor bit c */
++
++ /* store: (d4 << 16 | q0) << 8 */
++ vmovl.u8 q2, d4 /* expand from char to short */
++ vzip.16 q0, q2
++ vshl.u32 q0, q0, #8
++ vshl.u32 q1, q2, #8
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_16_neon_lut_start
++
++ mov pc, lr
++
++/**
++ * hdmi_dma_copy_16_neon_fast
++ * Convert pcm sample to iec sample. Pcm sample is 16 bits.
++ * Frame index's between 48 and 191 inclusively.
++ * Channel count can be 1, 2, 4 or 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_16_neon_fast(unsigned short *src,
++ * unsigned int *dst, int samples);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM16 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ */
++
++hdmi_dma_copy_16_neon_fast:
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d6, r12
++
++hdmi_dma_copy_16_neon_fast_start:
++ /* get 8 samples to q0 */
++ vld1.16 {d0, d1}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q1, q0 /* count of 1s */
++ vpadd.i8 d2, d2, d3
++ vand d2, d2, d6 /* clear other bits while keep the LST */
++ /* finally we construct packet header */
++ vshl.u8 d4, d2, #3 /* bit p: d2 = d2 << 3 */
++
++ /* get packet header: always 0 */
++
++ /* store: (d4 << 16 | q0) << 8 */
++ vmovl.u8 q2, d4 /* expand from char to short */
++ vzip.16 q0, q2
++ vshl.u32 q0, q0, #8
++ vshl.u32 q1, q2, #8
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_16_neon_fast_start
++
++ mov pc, lr
++
++
++
++/**
++ * hdmi_dma_copy_24_neon_lut
++ * Convert pcm sample to iec sample. Pcm sample is 24 bits.
++ * Frame index's between 0 and 47 inclusively. Channel count can be 1, 2, 4, 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_24_neon_lut(unsigned int *src, unsigned int *dst,
++ * int samples, unsigned char *lookup_table);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM24 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ * lookup_table Preconstructed header table. Channels interleaved.
++ */
++
++hdmi_dma_copy_24_neon_lut:
++ vpush {d8}
++
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d8, r12
++
++hdmi_dma_copy_24_neon_lut_start:
++
++ /* get 8 samples to q0 and q1 */
++ vld1.32 {d0, d1, d2, d3}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q2, q0 /* count of 1s */
++ vpadd.i8 d4, d4, d5 /* only care about the LSB in every element */
++ vcnt.8 q3, q1
++ vpadd.i8 d6, d6, d7
++ vpadd.i8 d4, d4, d6 /* d4: contains xor result and other dirty bits */
++ vand d4, d4, d8 /* clear other bits while keep the least bit */
++ vshl.u8 d4, d4, #3 /* bit p: d4 = d4 << 3 */
++
++ /* get packet header */
++ vld1.8 {d5}, [r3]!/* d5: original header */
++ veor d5, d5, d4 /* fix bit p */
++
++ /* store: (d5 << 24 | q0) */
++ vmovl.u8 q3, d5 /* expand from char to short */
++ vmovl.u16 q2, d6 /* expand from short to int */
++ vmovl.u16 q3, d7
++ vshl.u32 q2, q2, #24
++ vshl.u32 q3, q3, #24
++ vorr q0, q0, q2
++ vorr q1, q1, q3
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_24_neon_lut_start
++
++ vpop {d8}
++ mov pc, lr
++
++/**
++ * hdmi_dma_copy_24_neon_fast
++ * Convert pcm sample to iec sample. Pcm sample is 24 bits.
++ * Frame index's between 48 and 191 inclusively.
++ * Channel count can be 1, 2, 4 or 8.
++ * Frame count should be multipliable by 4, and Sample count by 8.
++ *
++ * C Prototype
++ * void hdmi_dma_copy_24_neon_fast(unsigned int *src,
++ * unsigned int *dst, int samples);
++ * Return value
++ * None
++ * Parameters
++ * src Source PCM24 samples
++ * dst Dest buffer to store pcm with header
++ * samples Contains sample count (=frame_count * channel_count)
++ */
++
++hdmi_dma_copy_24_neon_fast:
++ vpush {d8}
++
++ mov r12, #1 /* construct vector(1) */
++ vdup.8 d8, r12
++
++hdmi_dma_copy_24_neon_fast_start:
++ /* get 8 samples to q0 and q1 */
++ vld1.32 {d0, d1, d2, d3}, [r0]! /* TODO: aligned */
++
++ /* pld [r1, #(64*4)] */
++
++ /* xor every bit */
++ vcnt.8 q2, q0 /* count of 1s */
++ vpadd.i8 d4, d4, d5 /* only care about the LSB in every element */
++ vcnt.8 q3, q1
++ vpadd.i8 d6, d6, d7
++ vpadd.i8 d4, d4, d6 /* d4: contains xor result and other dirty bits */
++ vand d4, d4, d8 /* clear other bits while keep the least bit */
++ vshl.u8 d4, d4, #3 /* bit p: d4 = d4 << 3 */
++
++ /* store: (d4 << 24 | q0) */
++ vmovl.u8 q3, d4 /* expand from char to short */
++ vmovl.u16 q2, d6 /* expand from short to int */
++ vmovl.u16 q3, d7
++ vshl.u32 q2, q2, #24
++ vshl.u32 q3, q3, #24
++ vorr q0, q0, q2
++ vorr q1, q1, q3
++ vst1.32 {d0, d1, d2, d3}, [r1]!
++
++ /* decrease sample count */
++ subs r2, r2, #8
++ bne hdmi_dma_copy_24_neon_fast_start
++
++ vpop {d8}
++ mov pc, lr
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-ac97-vt1613.c linux-3.14.72/sound/soc/fsl/imx-ac97-vt1613.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-ac97-vt1613.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-ac97-vt1613.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,207 @@
++/*
++ * imx-ac97-vt1613.c -- SoC audio for i.MX Seco UDOO board with
++ * VT1613 AC'97 codec
++ * Copyright: Seco s.r.l.
++
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++
++#include "../codecs/vt1613.h"
++#include "imx-audmux.h"
++#include "fsl_ssi.h"
++
++#define DRV_NAME "imx-ac97-vt1613"
++
++static int imx_vt1613_audio_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ int ret;
++
++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_AC97
++ | SND_SOC_DAIFMT_NB_NF
++ | SND_SOC_DAIFMT_CBM_CFS);
++ if (ret < 0) {
++ dev_err(cpu_dai->dev,
++ "Failed to set cpu dai format: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++static struct snd_soc_ops imx_vt1613_audio_ops = {
++ .hw_params = imx_vt1613_audio_params,
++};
++
++
++static struct snd_soc_dai_link imx_vt1613_dai = {
++ .name = "vt1613-AC97",
++ .stream_name = "AC97-analog",
++ .codec_dai_name = "vt1613-hifi-analog",
++};
++
++static struct snd_soc_card imx_vt1613_card = {
++ .name = "imx-vt1613-audio",
++ .owner = THIS_MODULE,
++ .dai_link = &imx_vt1613_dai,
++ .num_links = 1,
++};
++
++static int imx_audmux_ac97_config(struct platform_device *pdev, int intPort, int extPort)
++{
++ int ret;
++ unsigned int ptcr, pdcr;
++
++ intPort = intPort - 1;
++ extPort = extPort - 1;
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR | IMX_AUDMUX_V2_PTCR_TCSEL(extPort);
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(extPort);
++
++ ret = imx_audmux_v2_configure_port(intPort, ptcr, pdcr);
++ if (ret) {
++ dev_err(&pdev->dev, "Audmux internal port setup failed\n");
++ return ret;
++ }
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_TFSDIR | IMX_AUDMUX_V2_PTCR_TFSEL(intPort);
++
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(intPort);
++
++ ret = imx_audmux_v2_configure_port(extPort, ptcr, pdcr);
++ if (ret) {
++ dev_err(&pdev->dev, "Audmux external port setup failed\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_vt1613_probe(struct platform_device *pdev)
++{
++ struct device_node *ssi_np, *codec_np, *np = pdev->dev.of_node;
++
++ struct platform_device *codec_pdev;
++ struct platform_device *ssi_pdev;
++ int int_port, ext_port;
++ int ret;
++
++ if (!of_machine_is_compatible("udoo,imx6q-udoo") && !of_machine_is_compatible("udoo,imx6dl-udoo"))
++ return -ENODEV;
++
++ if (vt1613_modules_dep) {
++ dev_dbg(&pdev->dev, "module dependency (codec module) ok\n");
++ } else {
++ dev_err(&pdev->dev, "module dependency (codec module) failed\n");
++ }
++ ret = of_property_read_u32(np, "mux-int-port", &int_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-int-port property missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-ext-port property missing or invalid\n");
++ return ret;
++ }
++
++ ret = imx_audmux_ac97_config(pdev, int_port, ext_port);
++ if (ret) {
++ dev_err(&pdev->dev, "Audmux port setup failed\n");
++ return ret;
++ }
++
++ ssi_np = of_parse_phandle(np, "ssi-controller", 0);
++ if (!ssi_np) {
++ dev_err(&pdev->dev, "ssi-controller phandle missing or invalid\n");
++ return -EINVAL;
++ }
++ ssi_pdev = of_find_device_by_node(ssi_np);
++ if (!ssi_pdev) {
++ dev_err(&pdev->dev, "Failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ codec_np = of_parse_phandle(np, "audio-codec", 0);
++ if (!codec_np) {
++ dev_err(&pdev->dev, "audio-codec phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++ codec_pdev = of_find_device_by_node(codec_np);
++ if (!codec_pdev) {
++ dev_err(&pdev->dev, "Failed to find codec device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ imx_vt1613_dai.codec_name = dev_name(&codec_pdev->dev);
++ imx_vt1613_dai.cpu_of_node = ssi_np;
++ imx_vt1613_dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
++ imx_vt1613_dai.platform_of_node = ssi_np;
++ imx_vt1613_dai.ops = &imx_vt1613_audio_ops;
++ imx_vt1613_dai.dai_fmt = SND_SOC_DAIFMT_AC97 | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFS;
++
++ imx_vt1613_card.dev = &pdev->dev;
++
++ platform_set_drvdata(pdev, &imx_vt1613_card);
++
++ ret = snd_soc_register_card(&imx_vt1613_card);
++ if (ret)
++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret);
++
++fail:
++ if (ssi_np)
++ of_node_put(ssi_np);
++ if (codec_np)
++ of_node_put(codec_np);
++
++ return ret;
++
++}
++
++static int imx_vt1613_remove(struct platform_device *pdev)
++{
++ int ret;
++ struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++ ret = snd_soc_unregister_card(card);
++
++ return ret;
++}
++
++static const struct of_device_id imx_vt1613_audio_match[] = {
++ { .compatible = "udoo,imx-vt1613-audio", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, imx_vt1613_audio_match);
++
++static struct platform_driver imx_vt1613_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ .of_match_table = imx_vt1613_audio_match,
++ },
++ .probe = imx_vt1613_probe,
++ .remove = imx_vt1613_remove,
++};
++module_platform_driver(imx_vt1613_driver);
++
++MODULE_AUTHOR("Seco <info@seco.it>");
++MODULE_DESCRIPTION(DRV_NAME ": Freescale i.MX VT1613 AC97 ASoC machine driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:imx-vt1613");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-audmux.c linux-3.14.72/sound/soc/fsl/imx-audmux.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-audmux.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/imx-audmux.c 2016-06-19 22:11:55.529125309 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012-2014 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+@@ -33,6 +33,8 @@
+
+ static struct clk *audmux_clk;
+ static void __iomem *audmux_base;
++static u32 *regcache;
++static u32 reg_max;
+
+ #define IMX_AUDMUX_V2_PTCR(x) ((x) * 8)
+ #define IMX_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
+@@ -67,7 +69,7 @@
+ {
+ ssize_t ret;
+ char *buf;
+- int port = (int)file->private_data;
++ uintptr_t port = (uintptr_t)file->private_data;
+ u32 pdcr, ptcr;
+
+ if (audmux_clk) {
+@@ -145,9 +147,9 @@
+ .llseek = default_llseek,
+ };
+
+-static void __init audmux_debugfs_init(void)
++static void audmux_debugfs_init(void)
+ {
+- int i;
++ uintptr_t i;
+ char buf[20];
+
+ audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
+@@ -157,10 +159,10 @@
+ }
+
+ for (i = 0; i < MX31_AUDMUX_PORT7_SSI_PINS_7 + 1; i++) {
+- snprintf(buf, sizeof(buf), "ssi%d", i);
++ snprintf(buf, sizeof(buf), "ssi%lu", i);
+ if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
+ (void *)i, &audmux_debugfs_fops))
+- pr_warning("Failed to create AUDMUX port %d debugfs file\n",
++ pr_warning("Failed to create AUDMUX port %lu debugfs file\n",
+ i);
+ }
+ }
+@@ -333,8 +335,22 @@
+ if (of_id)
+ pdev->id_entry = of_id->data;
+ audmux_type = pdev->id_entry->driver_data;
+- if (audmux_type == IMX31_AUDMUX)
++
++ switch (audmux_type) {
++ case IMX31_AUDMUX:
+ audmux_debugfs_init();
++ reg_max = 14;
++ break;
++ case IMX21_AUDMUX:
++ reg_max = 6;
++ default:
++ dev_err(&pdev->dev, "unsupported version!\n");
++ return -EINVAL;
++ }
++
++ regcache = devm_kzalloc(&pdev->dev, sizeof(u32) * reg_max, GFP_KERNEL);
++ if (!regcache)
++ return -ENOMEM;
+
+ if (of_id)
+ imx_audmux_parse_dt_defaults(pdev, pdev->dev.of_node);
+@@ -350,6 +366,40 @@
+ return 0;
+ }
+
++#ifdef CONFIG_PM_SLEEP
++static int imx_audmux_suspend(struct device *dev)
++{
++ int i;
++
++ clk_prepare_enable(audmux_clk);
++
++ for (i = 0; i < reg_max; i++)
++ regcache[i] = readl(audmux_base + i * 4);
++
++ clk_disable_unprepare(audmux_clk);
++
++ return 0;
++}
++
++static int imx_audmux_resume(struct device *dev)
++{
++ int i;
++
++ clk_prepare_enable(audmux_clk);
++
++ for (i = 0; i < reg_max; i++)
++ writel(regcache[i], audmux_base + i * 4);
++
++ clk_disable_unprepare(audmux_clk);
++
++ return 0;
++}
++#endif /* CONFIG_PM_SLEEP */
++
++static const struct dev_pm_ops imx_audmux_pm = {
++ SET_SYSTEM_SLEEP_PM_OPS(imx_audmux_suspend, imx_audmux_resume)
++};
++
+ static struct platform_driver imx_audmux_driver = {
+ .probe = imx_audmux_probe,
+ .remove = imx_audmux_remove,
+@@ -357,6 +407,7 @@
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
++ .pm = &imx_audmux_pm,
+ .of_match_table = imx_audmux_dt_ids,
+ }
+ };
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-cs42888.c linux-3.14.72/sound/soc/fsl/imx-cs42888.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-cs42888.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-cs42888.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,333 @@
++/*
++ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/slab.h>
++#include <linux/device.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/soc.h>
++#include <sound/initval.h>
++#include <sound/pcm_params.h>
++
++#include "fsl_esai.h"
++
++#define CODEC_CLK_EXTER_OSC 1
++#define CODEC_CLK_ESAI_HCKT 2
++#define SUPPORT_RATE_NUM 10
++
++struct imx_priv {
++ unsigned int mclk_freq;
++ struct platform_device *pdev;
++ struct platform_device *asrc_pdev;
++ u32 asrc_rate;
++ u32 asrc_format;
++};
++
++static struct imx_priv card_priv;
++
++static int imx_cs42888_surround_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct imx_priv *priv = &card_priv;
++ u32 dai_format = 0;
++
++ dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS;
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ snd_soc_dai_set_sysclk(cpu_dai, ESAI_HCKT_EXTAL,
++ priv->mclk_freq, SND_SOC_CLOCK_OUT);
++ else
++ snd_soc_dai_set_sysclk(cpu_dai, ESAI_HCKR_EXTAL,
++ priv->mclk_freq, SND_SOC_CLOCK_OUT);
++ snd_soc_dai_set_sysclk(codec_dai, 0, priv->mclk_freq, SND_SOC_CLOCK_IN);
++
++ /* set cpu DAI configuration */
++ snd_soc_dai_set_fmt(cpu_dai, dai_format);
++ /* set i.MX active slot mask */
++ snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, 32);
++
++ /* set codec DAI configuration */
++ snd_soc_dai_set_fmt(codec_dai, dai_format);
++ return 0;
++}
++
++static int imx_cs42888_surround_startup(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ static struct snd_pcm_hw_constraint_list constraint_rates;
++ struct imx_priv *priv = &card_priv;
++ struct device *dev = &priv->pdev->dev;
++ static u32 support_rates[SUPPORT_RATE_NUM];
++ int ret;
++
++ if (priv->mclk_freq == 24576000) {
++ support_rates[0] = 48000;
++ support_rates[1] = 96000;
++ support_rates[2] = 192000;
++ constraint_rates.list = support_rates;
++ constraint_rates.count = 3;
++
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
++ &constraint_rates);
++ if (ret)
++ return ret;
++ } else
++ dev_warn(dev, "mclk may be not supported %d\n", priv->mclk_freq);
++
++ return 0;
++}
++
++static struct snd_soc_ops imx_cs42888_surround_ops = {
++ .startup = imx_cs42888_surround_startup,
++ .hw_params = imx_cs42888_surround_hw_params,
++};
++
++/**
++ * imx_cs42888_surround_startup() is to set constrain for hw parameter, but
++ * backend use same runtime as frontend, for p2p backend need to use different
++ * parameter, so backend can't use the startup.
++ */
++static struct snd_soc_ops imx_cs42888_surround_ops_be = {
++ .hw_params = imx_cs42888_surround_hw_params,
++};
++
++
++static const struct snd_soc_dapm_widget imx_cs42888_dapm_widgets[] = {
++ SND_SOC_DAPM_LINE("Line Out Jack", NULL),
++ SND_SOC_DAPM_LINE("Line In Jack", NULL),
++};
++
++static const struct snd_soc_dapm_route audio_map[] = {
++ /* Line out jack */
++ {"Line Out Jack", NULL, "AOUT1L"},
++ {"Line Out Jack", NULL, "AOUT1R"},
++ {"Line Out Jack", NULL, "AOUT2L"},
++ {"Line Out Jack", NULL, "AOUT2R"},
++ {"Line Out Jack", NULL, "AOUT3L"},
++ {"Line Out Jack", NULL, "AOUT3R"},
++ {"Line Out Jack", NULL, "AOUT4L"},
++ {"Line Out Jack", NULL, "AOUT4R"},
++ {"AIN1L", NULL, "Line In Jack"},
++ {"AIN1R", NULL, "Line In Jack"},
++ {"AIN2L", NULL, "Line In Jack"},
++ {"AIN2R", NULL, "Line In Jack"},
++ {"CPU-Playback", NULL, "ASRC-Playback"},
++ {"Playback", NULL, "CPU-Playback"},/* dai route for be and fe */
++ {"ASRC-Capture", NULL, "CPU-Capture"},
++ {"CPU-Capture", NULL, "Capture"},
++};
++
++static int be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
++ struct snd_pcm_hw_params *params) {
++
++ struct imx_priv *priv = &card_priv;
++ struct snd_interval *rate;
++ struct snd_mask *mask;
++
++ if (!priv->asrc_pdev)
++ return -EINVAL;
++
++ rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
++ rate->max = rate->min = priv->asrc_rate;
++
++ mask = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
++ snd_mask_none(mask);
++ snd_mask_set(mask, priv->asrc_format);
++
++ return 0;
++}
++
++static struct snd_soc_dai_link imx_cs42888_dai[] = {
++ {
++ .name = "HiFi",
++ .stream_name = "HiFi",
++ .codec_dai_name = "cs42888",
++ .ops = &imx_cs42888_surround_ops,
++ .ignore_pmdown_time = 1,
++ },
++ {
++ .name = "HiFi-ASRC-FE",
++ .stream_name = "HiFi-ASRC-FE",
++ .codec_name = "snd-soc-dummy",
++ .codec_dai_name = "snd-soc-dummy-dai",
++ .dynamic = 1,
++ .ignore_pmdown_time = 1,
++ .dpcm_playback = 1,
++ .dpcm_capture = 1,
++ },
++ {
++ .name = "HiFi-ASRC-BE",
++ .stream_name = "HiFi-ASRC-BE",
++ .codec_dai_name = "cs42888",
++ .platform_name = "snd-soc-dummy",
++ .no_pcm = 1,
++ .ignore_pmdown_time = 1,
++ .dpcm_playback = 1,
++ .dpcm_capture = 1,
++ .ops = &imx_cs42888_surround_ops_be,
++ .be_hw_params_fixup = be_hw_params_fixup,
++ },
++};
++
++static struct snd_soc_card snd_soc_card_imx_cs42888 = {
++ .name = "cs42888-audio",
++ .dai_link = imx_cs42888_dai,
++ .dapm_widgets = imx_cs42888_dapm_widgets,
++ .num_dapm_widgets = ARRAY_SIZE(imx_cs42888_dapm_widgets),
++ .dapm_routes = audio_map,
++ .num_dapm_routes = ARRAY_SIZE(audio_map),
++};
++
++/*
++ * This function will register the snd_soc_pcm_link drivers.
++ */
++static int imx_cs42888_probe(struct platform_device *pdev)
++{
++ struct device_node *esai_np, *codec_np;
++ struct device_node *asrc_np;
++ struct platform_device *esai_pdev;
++ struct platform_device *asrc_pdev = NULL;
++ struct i2c_client *codec_dev;
++ struct imx_priv *priv = &card_priv;
++ struct clk *codec_clk = NULL;
++ int ret;
++ u32 width;
++
++ priv->pdev = pdev;
++ priv->asrc_pdev = NULL;
++
++ esai_np = of_parse_phandle(pdev->dev.of_node, "esai-controller", 0);
++ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
++ if (!esai_np || !codec_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ asrc_np = of_parse_phandle(pdev->dev.of_node, "asrc-controller", 0);
++ if (asrc_np) {
++ asrc_pdev = of_find_device_by_node(asrc_np);
++ priv->asrc_pdev = asrc_pdev;
++ }
++
++ esai_pdev = of_find_device_by_node(esai_np);
++ if (!esai_pdev) {
++ dev_err(&pdev->dev, "failed to find ESAI platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++ codec_dev = of_find_i2c_device_by_node(codec_np);
++ if (!codec_dev || !codec_dev->dev.driver) {
++ dev_err(&pdev->dev, "failed to find codec platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ /*if there is no asrc controller, we only enable one device*/
++ if (!asrc_pdev) {
++ imx_cs42888_dai[0].codec_of_node = codec_np;
++ imx_cs42888_dai[0].cpu_dai_name = dev_name(&esai_pdev->dev);
++ imx_cs42888_dai[0].platform_of_node = esai_np;
++ snd_soc_card_imx_cs42888.num_links = 1;
++ } else {
++ imx_cs42888_dai[0].codec_of_node = codec_np;
++ imx_cs42888_dai[0].cpu_dai_name = dev_name(&esai_pdev->dev);
++ imx_cs42888_dai[0].platform_of_node = esai_np;
++ imx_cs42888_dai[1].cpu_of_node = asrc_np;
++ imx_cs42888_dai[1].platform_of_node = asrc_np;
++ imx_cs42888_dai[2].codec_of_node = codec_np;
++ imx_cs42888_dai[2].cpu_dai_name = dev_name(&esai_pdev->dev);
++ snd_soc_card_imx_cs42888.num_links = 3;
++
++ ret = of_property_read_u32(asrc_np, "fsl,asrc-rate",
++ &priv->asrc_rate);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get output rate\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ ret = of_property_read_u32(asrc_np, "fsl,asrc-width", &width);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get output rate\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ if (width == 24)
++ priv->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
++ else
++ priv->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
++ }
++
++ codec_clk = devm_clk_get(&codec_dev->dev, NULL);
++ if (IS_ERR(codec_clk)) {
++ ret = PTR_ERR(codec_clk);
++ dev_err(&codec_dev->dev, "failed to get codec clk: %d\n", ret);
++ goto fail;
++ }
++ priv->mclk_freq = clk_get_rate(codec_clk);
++
++ snd_soc_card_imx_cs42888.dev = &pdev->dev;
++
++ platform_set_drvdata(pdev, &snd_soc_card_imx_cs42888);
++
++ ret = snd_soc_register_card(&snd_soc_card_imx_cs42888);
++ if (ret)
++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
++fail:
++ if (asrc_np)
++ of_node_put(asrc_np);
++ if (esai_np)
++ of_node_put(esai_np);
++ if (codec_np)
++ of_node_put(codec_np);
++ return ret;
++}
++
++static int imx_cs42888_remove(struct platform_device *pdev)
++{
++ snd_soc_unregister_card(&snd_soc_card_imx_cs42888);
++ return 0;
++}
++
++static const struct of_device_id imx_cs42888_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-cs42888", },
++ { /* sentinel */ }
++};
++
++static struct platform_driver imx_cs42888_driver = {
++ .probe = imx_cs42888_probe,
++ .remove = imx_cs42888_remove,
++ .driver = {
++ .name = "imx-cs42888",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ .of_match_table = imx_cs42888_dt_ids,
++ },
++};
++module_platform_driver(imx_cs42888_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("ALSA SoC cs42888 Machine Layer Driver");
++MODULE_ALIAS("platform:imx-cs42888");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-hdmi.c linux-3.14.72/sound/soc/fsl/imx-hdmi.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-hdmi.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-hdmi.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,113 @@
++/*
++ * ASoC HDMI Transmitter driver for IMX development boards
++ *
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * based on stmp3780_devb_hdmi.c
++ *
++ * Vladimir Barinov <vbarinov@embeddedalley.com>
++ *
++ * Copyright 2008 SigmaTel, Inc
++ * Copyright 2008 Embedded Alley Solutions, Inc
++ *
++ * This file is licensed under the terms of the GNU General Public License
++ * version 2. This program is licensed "as is" without any warranty of any
++ * kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <sound/soc.h>
++
++#include "imx-hdmi.h"
++
++/* imx digital audio interface glue - connects codec <--> CPU */
++static struct snd_soc_dai_link imx_hdmi_dai_link = {
++ .name = "i.MX HDMI Audio Tx",
++ .stream_name = "i.MX HDMI Audio Tx",
++ .codec_dai_name = "hdmi-hifi",
++ .codec_name = "hdmi-audio-codec",
++ .platform_name = "imx-hdmi-audio",
++};
++
++static struct snd_soc_card snd_soc_card_imx_hdmi = {
++ .name = "imx-hdmi-soc",
++ .dai_link = &imx_hdmi_dai_link,
++ .num_links = 1,
++};
++
++static int imx_hdmi_audio_probe(struct platform_device *pdev)
++{
++ struct device_node *hdmi_np, *np = pdev->dev.of_node;
++ struct snd_soc_card *card = &snd_soc_card_imx_hdmi;
++ struct platform_device *hdmi_pdev;
++ int ret = 0;
++
++ if (!hdmi_get_registered()) {
++ dev_err(&pdev->dev, "initialize HDMI-audio failed. load HDMI-video first!\n");
++ return -ENODEV;
++ }
++
++ hdmi_np = of_parse_phandle(np, "hdmi-controller", 0);
++ if (!hdmi_np) {
++ dev_err(&pdev->dev, "failed to find hdmi-audio cpudai\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ hdmi_pdev = of_find_device_by_node(hdmi_np);
++ if (!hdmi_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ card->dev = &pdev->dev;
++ card->dai_link->cpu_dai_name = dev_name(&hdmi_pdev->dev);
++
++ platform_set_drvdata(pdev, card);
++
++ ret = snd_soc_register_card(card);
++ if (ret)
++ dev_err(&pdev->dev, "failed to register card: %d\n", ret);
++
++end:
++ if (hdmi_np)
++ of_node_put(hdmi_np);
++
++ return ret;
++}
++
++static int imx_hdmi_audio_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++ snd_soc_unregister_card(card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_hdmi_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-hdmi", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_dt_ids);
++
++static struct platform_driver imx_hdmi_audio_driver = {
++ .probe = imx_hdmi_audio_probe,
++ .remove = imx_hdmi_audio_remove,
++ .driver = {
++ .of_match_table = imx_hdmi_dt_ids,
++ .name = "imx-audio-hdmi",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ },
++};
++
++module_platform_driver(imx_hdmi_audio_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("IMX HDMI TX ASoC driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-audio-hdmi");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-hdmi-dma.c linux-3.14.72/sound/soc/fsl/imx-hdmi-dma.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-hdmi-dma.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-hdmi-dma.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,1298 @@
++/*
++ * imx-hdmi-dma.c -- HDMI DMA driver for ALSA Soc Audio Layer
++ *
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * based on imx-pcm-dma-mx2.c
++ * Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
++ *
++ * This code is based on code copyrighted by Freescale,
++ * Liam Girdwood, Javier Martin and probably others.
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/mfd/mxc-hdmi-core.h>
++#include <linux/platform_data/dma-imx.h>
++
++#include <video/mxc_hdmi.h>
++
++#include "imx-hdmi.h"
++
++#define HDMI_DMA_BURST_UNSPECIFIED_LEGNTH 0
++#define HDMI_DMA_BURST_INCR4 1
++#define HDMI_DMA_BURST_INCR8 2
++#define HDMI_DMA_BURST_INCR16 3
++
++#define HDMI_BASE_ADDR 0x00120000
++
++struct hdmi_sdma_script {
++ int control_reg_addr;
++ int status_reg_addr;
++ int dma_start_addr;
++ u32 buffer[20];
++};
++
++struct hdmi_dma_priv {
++ struct snd_pcm_substream *substream;
++ struct platform_device *pdev;
++
++ struct snd_dma_buffer hw_buffer;
++ unsigned long buffer_bytes;
++ unsigned long appl_bytes;
++
++ int periods;
++ int period_time;
++ int period_bytes;
++ int dma_period_bytes;
++ int buffer_ratio;
++
++ unsigned long offset;
++
++ snd_pcm_format_t format;
++ int sample_align;
++ int sample_bits;
++ int channels;
++ int rate;
++
++ int frame_idx;
++
++ bool tx_active;
++ spinlock_t irq_lock;
++
++ /* SDMA part */
++ dma_addr_t phy_hdmi_sdma_t;
++ struct hdmi_sdma_script *hdmi_sdma_t;
++ struct dma_chan *dma_channel;
++ struct dma_async_tx_descriptor *desc;
++ struct imx_hdmi_sdma_params sdma_params;
++};
++
++/* bit 0:0:0:b:p(0):c:(u)0:(v)0 */
++/* max 8 channels supported; channels are interleaved */
++static u8 g_packet_head_table[48 * 8];
++
++void hdmi_dma_copy_16_neon_lut(unsigned short *src, unsigned int *dst,
++ int samples, unsigned char *lookup_table);
++void hdmi_dma_copy_16_neon_fast(unsigned short *src, unsigned int *dst,
++ int samples);
++void hdmi_dma_copy_24_neon_lut(unsigned int *src, unsigned int *dst,
++ int samples, unsigned char *lookup_table);
++void hdmi_dma_copy_24_neon_fast(unsigned int *src, unsigned int *dst,
++ int samples);
++static void hdmi_dma_irq_enable(struct hdmi_dma_priv *priv);
++static void hdmi_dma_irq_disable(struct hdmi_dma_priv *priv);
++
++/* channel remapping for hdmi_dma_copy_xxxx() */
++static u8 g_channel_remap_table[24];
++
++/* default mapping tables */
++static const u8 channel_maps_alsa_cea[5][8] = {
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 0CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 2CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 4CH: no remapping */
++ { 0, 1, 4, 5, 3, 2, 6, 7 }, /* 6CH: ALSA5.1 to CEA */
++ { 0, 1, 6, 7, 3, 2, 4, 5 } /* 8CH: ALSA7.1 to CEA */
++};
++
++static const u8 channel_maps_cea_alsa[5][8] = {
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 0CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 2CH: no remapping */
++ { 0, 1, 2, 3, 4, 5, 6, 7 }, /* 4CH: no remapping */
++ { 0, 1, 5, 4, 2, 3, 6, 7 }, /* 6CH: CEA to ALSA5.1 */
++ { 0, 1, 5, 4, 6, 7, 2, 3 } /* 8CH: CEA to ALSA7.1 */
++};
++
++union hdmi_audio_header_t iec_header;
++EXPORT_SYMBOL(iec_header);
++
++/*
++ * Note that the period size for DMA != period size for ALSA because the
++ * driver adds iec frame info to the audio samples (in hdmi_dma_copy).
++ *
++ * Each 4 byte subframe = 1 byte of iec data + 3 byte audio sample.
++ *
++ * A 16 bit audio sample becomes 32 bits including the frame info. Ratio=2
++ * A 24 bit audio sample becomes 32 bits including the frame info. Ratio=3:4
++ * If the 24 bit raw audio is in 32 bit words, the
++ *
++ * Original Packed into subframe Ratio of size Format
++ * sample how many size of DMA buffer
++ * (bits) bits to ALSA buffer
++ * -------- ----------- -------- -------------- ------------------------
++ * 16 16 32 2 SNDRV_PCM_FORMAT_S16_LE
++ * 24 24 32 1.33 SNDRV_PCM_FORMAT_S24_3LE*
++ * 24 32 32 1 SNDRV_PCM_FORMAT_S24_LE
++ *
++ * *so SNDRV_PCM_FORMAT_S24_3LE is not supported.
++ */
++
++/*
++ * The minimum dma period is one IEC audio frame (192 * 4 * channels).
++ * The maximum dma period for the HDMI DMA is 8K.
++ *
++ * channels minimum maximum
++ * dma period dma period
++ * -------- ------------------ ----------
++ * 2 192 * 4 * 2 = 1536 * 4 = 6144
++ * 4 192 * 4 * 4 = 3072 * 2 = 6144
++ * 6 192 * 4 * 6 = 4608 * 1 = 4608
++ * 8 192 * 4 * 8 = 6144 * 1 = 6144
++ *
++ * Bottom line:
++ * 1. Must keep the ratio of DMA buffer to ALSA buffer consistent.
++ * 2. frame_idx is saved in the private data, so even if a frame cannot be
++ * transmitted in a period, it can be continued in the next period. This
++ * is necessary for 6 ch.
++ */
++#define HDMI_DMA_PERIOD_BYTES (12288)
++#define HDMI_DMA_BUF_SIZE (1280 * 1024)
++#define HDMI_PCM_BUF_SIZE (1280 * 1024)
++
++#define hdmi_audio_debug(dev, reg) \
++ dev_dbg(dev, #reg ": 0x%02x\n", hdmi_readb(reg))
++
++#ifdef DEBUG
++static void dumpregs(struct device *dev)
++{
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_CONF0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_START);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STOP);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_THRSLD);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STRADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STPADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BSTADDR0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MBLENGTH0);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MBLENGTH1);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_STAT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_INT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_MASK);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_POL);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_CONF1);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFSTAT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFINT);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFMASK);
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_BUFFPOL);
++ hdmi_audio_debug(dev, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_audio_debug(dev, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_audio_debug(dev, HDMI_IH_MUTE);
++}
++
++static void dumppriv(struct device *dev, struct hdmi_dma_priv *priv)
++{
++ dev_dbg(dev, "channels = %d\n", priv->channels);
++ dev_dbg(dev, "periods = %d\n", priv->periods);
++ dev_dbg(dev, "period_bytes = %d\n", priv->period_bytes);
++ dev_dbg(dev, "dma period_bytes = %d\n", priv->dma_period_bytes);
++ dev_dbg(dev, "buffer_ratio = %d\n", priv->buffer_ratio);
++ dev_dbg(dev, "hw dma buffer = 0x%08x\n", (int)priv->hw_buffer.addr);
++ dev_dbg(dev, "dma buf size = %d\n", (int)priv->buffer_bytes);
++ dev_dbg(dev, "sample_rate = %d\n", (int)priv->rate);
++}
++#else
++static void dumpregs(struct device *dev) {}
++static void dumppriv(struct device *dev, struct hdmi_dma_priv *priv) {}
++#endif
++
++/*
++ * Conditions for DMA to work:
++ * ((final_addr - initial_addr)>>2)+1) < 2k. So max period is 8k.
++ * (inital_addr & 0x3) == 0
++ * (final_addr & 0x3) == 0x3
++ *
++ * The DMA Period should be an integer multiple of the IEC 60958 audio
++ * frame size, which is 768 bytes (192 * 4).
++ */
++static void hdmi_dma_set_addr(int start_addr, int dma_period_bytes)
++{
++ int final_addr = start_addr + dma_period_bytes - 1;
++
++ hdmi_write4(start_addr, HDMI_AHB_DMA_STRADDR0);
++ hdmi_write4(final_addr, HDMI_AHB_DMA_STPADDR0);
++}
++
++static void hdmi_dma_irq_set(bool set)
++{
++ u8 val = hdmi_readb(HDMI_AHB_DMA_MASK);
++
++ if (set)
++ val |= HDMI_AHB_DMA_DONE;
++ else
++ val &= (u8)~HDMI_AHB_DMA_DONE;
++
++ hdmi_writeb(val, HDMI_AHB_DMA_MASK);
++}
++
++static void hdmi_mask(int mask)
++{
++ u8 regval = hdmi_readb(HDMI_AHB_DMA_MASK);
++
++ if (mask)
++ regval |= HDMI_AHB_DMA_ERROR | HDMI_AHB_DMA_FIFO_EMPTY;
++ else
++ regval &= (u8)~(HDMI_AHB_DMA_ERROR | HDMI_AHB_DMA_FIFO_EMPTY);
++
++ hdmi_writeb(regval, HDMI_AHB_DMA_MASK);
++}
++
++static inline int odd_ones(unsigned a)
++{
++ a ^= a >> 16;
++ a ^= a >> 8;
++ a ^= a >> 4;
++ a ^= a >> 2;
++ a ^= a >> 1;
++
++ return a & 1;
++}
++
++/* Add frame information for one pcm subframe */
++static u32 hdmi_dma_add_frame_info(struct hdmi_dma_priv *priv,
++ u32 pcm_data, int subframe_idx)
++{
++ union hdmi_audio_dma_data_t subframe;
++ union hdmi_audio_header_t tmp_header;
++
++ subframe.U = 0;
++
++ if (priv->frame_idx < 42) {
++ tmp_header = iec_header;
++
++ /* fill v (validity) */
++ subframe.B.v = tmp_header.B.linear_pcm;
++
++ /* fill c (channel status) */
++ if (tmp_header.B.linear_pcm == 0)
++ tmp_header.B.channel = subframe_idx + 1;
++ subframe.B.c = tmp_header.U >> priv->frame_idx;
++ } else {
++ /* fill v (validity), c is always zero */
++ subframe.B.v = iec_header.B.linear_pcm;
++ }
++
++ /* fill data */
++ if (priv->sample_bits == 16)
++ pcm_data <<= 8;
++ subframe.B.data = pcm_data;
++
++ /* fill p (parity) Note: Do not include b ! */
++ subframe.B.p = odd_ones(subframe.U);
++
++ /* fill b (start-of-block) */
++ if (priv->frame_idx == 0)
++ subframe.B.b = 1;
++
++ return subframe.U;
++}
++
++static void init_table(int channels)
++{
++ int i, map_sel, ch;
++ unsigned char *p = g_packet_head_table;
++ union hdmi_audio_header_t tmp_header = iec_header;
++
++ for (i = 0; i < 48; i++) {
++ int b = 0;
++ if (i == 0)
++ b = 1;
++
++ for (ch = 0; ch < channels; ch++) {
++ int c = 0;
++ if (i < 42) {
++ tmp_header.B.channel = ch + 1;
++ c = (tmp_header.U >> i) & 0x1;
++ }
++ /* preset bit p as c */
++ *p++ = (b << 4) | (c << 2) | (c << 3);
++ }
++ }
++
++ map_sel = channels / 2;
++ for (i = 0; i < 24; i++) {
++ g_channel_remap_table[i] = (i / channels) * channels +
++ channel_maps_cea_alsa[map_sel][i % channels];
++ }
++}
++
++/*
++ * FIXME: Disable NEON Optimization in hdmi, or it will cause crash of
++ * pulseaudio in the userspace. There is no issue for the Optimization
++ * implemenation, if only use "VPUSH, VPOP" in the function, the pulseaudio
++ * will crash also. So for my assumption, we can't use the NEON in the
++ * interrupt.(tasklet is implemented by softirq.)
++ * Disable SMP, preempt, change the dma buffer to nocached, add protection of
++ * Dn register and fpscr, all these operation have no effect to the result.
++ */
++#define HDMI_DMA_NO_NEON
++
++#ifdef HDMI_DMA_NO_NEON
++/* Optimization for IEC head */
++static void hdmi_dma_copy_16_c_lut(u16 *src, u32 *dst, int samples,
++ u8 *lookup_table)
++{
++ u32 sample, head;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]];
++
++ /* get packet header and p-bit */
++ head = *lookup_table++ ^ (odd_ones(sample) << 3);
++
++ /* store sample and header */
++ *dst++ = (head << 24) | (sample << 8);
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_dma_copy_16_c_fast(u16 *src, u32 *dst, int samples)
++{
++ u32 sample;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]];
++
++ /* store sample and p-bit */
++ *dst++ = (odd_ones(sample) << (3+24)) | (sample << 8);
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_dma_copy_24_c_lut(u32 *src, u32 *dst, int samples,
++ u8 *lookup_table)
++{
++ u32 sample, head;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]] & 0x00ffffff;
++
++ /* get packet header and p-bit */
++ head = *lookup_table++ ^ (odd_ones(sample) << 3);
++
++ /* store sample and header */
++ *dst++ = (head << 24) | sample;
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_dma_copy_24_c_fast(u32 *src, u32 *dst, int samples)
++{
++ u32 sample;
++ int i = 0;
++
++ while (samples--) {
++ /* get source sample */
++ sample = src[g_channel_remap_table[i]] & 0x00ffffff;
++
++ /* store sample and p-bit */
++ *dst++ = (odd_ones(sample) << (3+24)) | sample;
++
++ if (++i == 24) {
++ src += 24;
++ i = 0;
++ }
++ }
++}
++
++static void hdmi_mmap_copy(u8 *src, int samplesize, u32 *dst, int framecnt, int channelcnt)
++{
++ /* split input frames into 192-frame each */
++ int count_in_192 = (framecnt + 191) / 192;
++ int i;
++
++ typedef void (*fn_copy_lut)(u8 *src, u32 *dst, int samples, u8 *lookup_table);
++ typedef void (*fn_copy_fast)(u8 *src, u32 *dst, int samples);
++ fn_copy_lut copy_lut;
++ fn_copy_fast copy_fast;
++
++ if (samplesize == 4) {
++ copy_lut = (fn_copy_lut)hdmi_dma_copy_24_c_lut;
++ copy_fast = (fn_copy_fast)hdmi_dma_copy_24_c_fast;
++ } else {
++ copy_lut = (fn_copy_lut)hdmi_dma_copy_16_c_lut;
++ copy_fast = (fn_copy_fast)hdmi_dma_copy_16_c_fast;
++ }
++
++ for (i = 0; i < count_in_192; i++) {
++ int count, samples;
++
++ /* handles frame index [0, 48) */
++ count = (framecnt < 48) ? framecnt : 48;
++ samples = count * channelcnt;
++ copy_lut(src, dst, samples, g_packet_head_table);
++ framecnt -= count;
++ if (framecnt == 0)
++ break;
++
++ src += samples * samplesize;
++ dst += samples;
++
++ /* handles frame index [48, 192) */
++ count = (framecnt < 192 - 48) ? framecnt : 192 - 48;
++ samples = count * channelcnt;
++ copy_fast(src, dst, samples);
++ framecnt -= count;
++ src += samples * samplesize;
++ dst += samples;
++ }
++}
++#else
++/* NEON optimization for IEC head*/
++
++/**
++ * Convert pcm samples to iec samples suitable for HDMI transfer.
++ * PCM sample is 16 bits length.
++ * Frame index always starts from 0.
++ * Channel count can be 1, 2, 4, 6, or 8
++ * Sample count (frame_count * channel_count) is multipliable by 8.
++ */
++static void hdmi_dma_copy_16(u16 *src, u32 *dst, int framecount, int channelcount)
++{
++ /* split input frames into 192-frame each */
++ int i, count_in_192 = (framecount + 191) / 192;
++
++ for (i = 0; i < count_in_192; i++) {
++ int count, samples;
++
++ /* handles frame index [0, 48) */
++ count = (framecount < 48) ? framecount : 48;
++ samples = count * channelcount;
++ hdmi_dma_copy_16_neon_lut(src, dst, samples, g_packet_head_table);
++ framecount -= count;
++ if (framecount == 0)
++ break;
++
++ src += samples;
++ dst += samples;
++
++ /* handles frame index [48, 192) */
++ count = (framecount < 192 - 48) ? framecount : (192 - 48);
++ samples = count * channelcount;
++ hdmi_dma_copy_16_neon_fast(src, dst, samples);
++ framecount -= count;
++ src += samples;
++ dst += samples;
++ }
++}
++#endif
++
++static void hdmi_dma_mmap_copy(struct snd_pcm_substream *substream,
++ int offset, int count)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++ u32 framecount, *dst;
++
++ framecount = count / (priv->sample_align * priv->channels);
++
++ /* hw_buffer is the destination for pcm data plus frame info. */
++ dst = (u32 *)(priv->hw_buffer.area + (offset * priv->buffer_ratio));
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ case SNDRV_PCM_FORMAT_S24_LE:
++ /* dma_buffer is the mmapped buffer we are copying pcm from. */
++ hdmi_mmap_copy(runtime->dma_area + offset,
++ priv->sample_align, dst, framecount, priv->channels);
++ break;
++ default:
++ dev_err(dev, "unsupported sample format %s\n",
++ snd_pcm_format_name(priv->format));
++ return;
++ }
++}
++
++static void hdmi_dma_data_copy(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv, char type)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ unsigned long offset, count, appl_bytes, space_to_end;
++
++ if (runtime->access != SNDRV_PCM_ACCESS_MMAP_INTERLEAVED)
++ return;
++
++ appl_bytes = runtime->status->hw_ptr * (runtime->frame_bits / 8);
++
++ switch (type) {
++ case 'p':
++ offset = (appl_bytes + 2 * priv->period_bytes) % priv->buffer_bytes;
++ count = priv->period_bytes;
++ space_to_end = priv->period_bytes;
++ break;
++ case 'b':
++ offset = appl_bytes % priv->buffer_bytes;
++ count = priv->buffer_bytes;
++ space_to_end = priv->buffer_bytes - offset;
++
++ break;
++ default:
++ return;
++ }
++
++ if (count <= space_to_end) {
++ hdmi_dma_mmap_copy(substream, offset, count);
++ } else {
++ hdmi_dma_mmap_copy(substream, offset, space_to_end);
++ hdmi_dma_mmap_copy(substream, 0, count - space_to_end);
++ }
++}
++
++static void hdmi_sdma_callback(void *data)
++{
++ struct hdmi_dma_priv *priv = (struct hdmi_dma_priv *)data;
++ struct snd_pcm_substream *substream = priv->substream;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ if (runtime && runtime->dma_area && priv->tx_active) {
++ priv->offset += priv->period_bytes;
++ priv->offset %= priv->period_bytes * priv->periods;
++
++ /* Copy data by period_bytes */
++ hdmi_dma_data_copy(substream, priv, 'p');
++
++ snd_pcm_period_elapsed(substream);
++ }
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++
++ return;
++}
++
++static int hdmi_dma_set_thrsld_incrtype(struct device *dev, int channels)
++{
++ u8 mask = HDMI_AHB_DMA_CONF0_BURST_MODE | HDMI_AHB_DMA_CONF0_INCR_TYPE_MASK;
++ u8 val = hdmi_readb(HDMI_AHB_DMA_CONF0) & ~mask;
++ int incr_type, threshold;
++
++ switch (hdmi_readb(HDMI_REVISION_ID)) {
++ case 0x0a:
++ incr_type = HDMI_DMA_BURST_INCR4;
++ if (channels == 2)
++ threshold = 126;
++ else
++ threshold = 124;
++ break;
++ case 0x1a:
++ incr_type = HDMI_DMA_BURST_INCR8;
++ threshold = 128;
++ break;
++ default:
++ dev_err(dev, "unknown hdmi controller!\n");
++ return -ENODEV;
++ }
++
++ hdmi_writeb(threshold, HDMI_AHB_DMA_THRSLD);
++
++ switch (incr_type) {
++ case HDMI_DMA_BURST_UNSPECIFIED_LEGNTH:
++ break;
++ case HDMI_DMA_BURST_INCR4:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE;
++ break;
++ case HDMI_DMA_BURST_INCR8:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR8;
++ break;
++ case HDMI_DMA_BURST_INCR16:
++ val |= HDMI_AHB_DMA_CONF0_BURST_MODE |
++ HDMI_AHB_DMA_CONF0_INCR16;
++ break;
++ default:
++ dev_err(dev, "invalid increment type: %d!", incr_type);
++ return -EINVAL;
++ }
++
++ hdmi_writeb(val, HDMI_AHB_DMA_CONF0);
++
++ hdmi_audio_debug(dev, HDMI_AHB_DMA_THRSLD);
++
++ return 0;
++}
++
++static int hdmi_dma_configure_dma(struct device *dev, int channels)
++{
++ int ret;
++ static u8 chan_enable[] = { 0x00, 0x03, 0x33, 0x3f, 0xff };
++
++ if (channels <= 0 || channels > 8 || channels % 2 != 0) {
++ dev_err(dev, "unsupported channel number: %d\n", channels);
++ return -EINVAL;
++ }
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, EN_HLOCK, 0x1);
++
++ ret = hdmi_dma_set_thrsld_incrtype(dev, channels);
++ if (ret)
++ return ret;
++
++ hdmi_writeb(chan_enable[channels / 2], HDMI_AHB_DMA_CONF1);
++
++ return 0;
++}
++
++static void hdmi_dma_init_iec_header(void)
++{
++ iec_header.U = 0;
++
++ iec_header.B.consumer = 0; /* Consumer use */
++ iec_header.B.linear_pcm = 0; /* linear pcm audio */
++ iec_header.B.copyright = 1; /* no copyright */
++ iec_header.B.pre_emphasis = 0; /* 2 channels without pre-emphasis */
++ iec_header.B.mode = 0; /* Mode 0 */
++
++ iec_header.B.category_code = 0;
++
++ iec_header.B.source = 2; /* stereo */
++ iec_header.B.channel = 0;
++
++ iec_header.B.sample_freq = 0x02; /* 48 KHz */
++ iec_header.B.clock_acc = 0; /* Level II */
++
++ iec_header.B.word_length = 0x02; /* 16 bits */
++ iec_header.B.org_sample_freq = 0x0D; /* 48 KHz */
++
++ iec_header.B.cgms_a = 0; /* Copying is permitted without restriction */
++}
++
++static int hdmi_dma_update_iec_header(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++
++ iec_header.B.source = priv->channels;
++
++ switch (priv->rate) {
++ case 32000:
++ iec_header.B.sample_freq = 0x03;
++ iec_header.B.org_sample_freq = 0x0C;
++ break;
++ case 44100:
++ iec_header.B.sample_freq = 0x00;
++ iec_header.B.org_sample_freq = 0x0F;
++ break;
++ case 48000:
++ iec_header.B.sample_freq = 0x02;
++ iec_header.B.org_sample_freq = 0x0D;
++ break;
++ case 88200:
++ iec_header.B.sample_freq = 0x08;
++ iec_header.B.org_sample_freq = 0x07;
++ break;
++ case 96000:
++ iec_header.B.sample_freq = 0x0A;
++ iec_header.B.org_sample_freq = 0x05;
++ break;
++ case 176400:
++ iec_header.B.sample_freq = 0x0C;
++ iec_header.B.org_sample_freq = 0x03;
++ break;
++ case 192000:
++ iec_header.B.sample_freq = 0x0E;
++ iec_header.B.org_sample_freq = 0x01;
++ break;
++ default:
++ dev_err(dev, "unsupported sample rate\n");
++ return -EFAULT;
++ }
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ iec_header.B.word_length = 0x02;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ iec_header.B.word_length = 0x0b;
++ break;
++ default:
++ return -EFAULT;
++ }
++
++ return 0;
++}
++
++/*
++ * The HDMI block transmits the audio data without adding any of the audio
++ * frame bits. So we have to copy the raw dma data from the ALSA buffer
++ * to the DMA buffer, adding the frame information.
++ */
++static int hdmi_dma_copy(struct snd_pcm_substream *substream, int channel,
++ snd_pcm_uframes_t pos, void __user *buf,
++ snd_pcm_uframes_t frames)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ unsigned int count = frames_to_bytes(runtime, frames);
++ unsigned int pos_bytes = frames_to_bytes(runtime, pos);
++ int channel_no, pcm_idx, subframe_idx, bits_left, sample_bits, map_sel;
++ u32 pcm_data[8], pcm_temp, *hw_buf, sample_block, inc_mask;
++
++ /* Adding frame info to pcm data from userspace and copy to hw_buffer */
++ hw_buf = (u32 *)(priv->hw_buffer.area + (pos_bytes * priv->buffer_ratio));
++
++ sample_bits = priv->sample_align * 8;
++ sample_block = priv->sample_align * priv->channels;
++
++ if (iec_header.B.linear_pcm == 0) {
++ map_sel = priv->channels / 2;
++ inc_mask = 1 << (priv->channels - 1);
++ } else {
++ map_sel = 0;
++ inc_mask = 0xaa;
++ }
++
++ while (count > 0) {
++ if (copy_from_user(pcm_data, buf, sample_block))
++ return -EFAULT;
++
++ buf += sample_block;
++ count -= sample_block;
++
++ channel_no = pcm_idx = 0;
++ do {
++ pcm_temp = pcm_data[pcm_idx++];
++ bits_left = 32;
++ for (;;) {
++ /* re-map channels */
++ subframe_idx = channel_maps_alsa_cea[map_sel][channel_no];
++
++ /* Save the header info to the audio dma buffer */
++ hw_buf[subframe_idx] = hdmi_dma_add_frame_info(
++ priv, pcm_temp, subframe_idx);
++
++ if (inc_mask & (1 << channel_no)) {
++ if (++priv->frame_idx == 192)
++ priv->frame_idx = 0;
++ }
++
++ channel_no++;
++
++ if (bits_left <= sample_bits)
++ break;
++
++ bits_left -= sample_bits;
++ pcm_temp >>= sample_bits;
++ }
++ } while (channel_no < priv->channels);
++
++ hw_buf += priv->channels;
++ }
++
++ return 0;
++}
++
++static int hdmi_sdma_initbuf(struct device *dev, struct hdmi_dma_priv *priv)
++{
++ struct hdmi_sdma_script *hdmi_sdma_t = priv->hdmi_sdma_t;
++ u32 *head, *tail, i;
++
++ if (!hdmi_sdma_t) {
++ dev_err(dev, "hdmi private addr invalid!!!\n");
++ return -EINVAL;
++ }
++
++ hdmi_sdma_t->control_reg_addr = HDMI_BASE_ADDR + HDMI_AHB_DMA_START;
++ hdmi_sdma_t->status_reg_addr = HDMI_BASE_ADDR + HDMI_IH_AHBDMAAUD_STAT0;
++ hdmi_sdma_t->dma_start_addr = HDMI_BASE_ADDR + HDMI_AHB_DMA_STRADDR0;
++
++ head = &hdmi_sdma_t->buffer[0];
++ tail = &hdmi_sdma_t->buffer[1];
++
++ for (i = 0; i < priv->sdma_params.buffer_num; i++) {
++ *head = priv->hw_buffer.addr + i * priv->period_bytes * priv->buffer_ratio;
++ *tail = *head + priv->dma_period_bytes - 1;
++ head += 2;
++ tail += 2;
++ }
++
++ return 0;
++}
++
++static int hdmi_sdma_config(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dai_dev = &priv->pdev->dev;
++ struct device *dev = rtd->platform->dev;
++ struct dma_slave_config slave_config;
++ int ret;
++
++ priv->dma_channel = dma_request_slave_channel(dai_dev, "tx");
++ if (priv->dma_channel == NULL) {
++ dev_err(dev, "failed to alloc dma channel\n");
++ return -EBUSY;
++ }
++
++ slave_config.direction = DMA_TRANS_NONE;
++ slave_config.src_addr = (dma_addr_t)priv->sdma_params.buffer_num;
++ slave_config.dst_addr = (dma_addr_t)priv->sdma_params.phyaddr;
++
++ ret = dmaengine_slave_config(priv->dma_channel, &slave_config);
++ if (ret) {
++ dev_err(dev, "failed to config slave dma\n");
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int hdmi_dma_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ if (priv->dma_channel) {
++ dma_release_channel(priv->dma_channel);
++ priv->dma_channel = NULL;
++ }
++
++ return 0;
++}
++
++static int hdmi_dma_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++ int ret;
++
++ priv->buffer_bytes = params_buffer_bytes(params);
++ priv->periods = params_periods(params);
++ priv->period_bytes = params_period_bytes(params);
++ priv->channels = params_channels(params);
++ priv->format = params_format(params);
++ priv->rate = params_rate(params);
++
++ priv->offset = 0;
++ priv->period_time = HZ / (priv->rate / params_period_size(params));
++
++ switch (priv->format) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ priv->buffer_ratio = 2;
++ priv->sample_align = 2;
++ priv->sample_bits = 16;
++ break;
++ case SNDRV_PCM_FORMAT_S24_LE:
++ /* 24 bit audio in 32 bit word */
++ priv->buffer_ratio = 1;
++ priv->sample_align = 4;
++ priv->sample_bits = 24;
++ break;
++ default:
++ dev_err(dev, "unsupported sample format: %d\n", priv->format);
++ return -EINVAL;
++ }
++
++ priv->dma_period_bytes = priv->period_bytes * priv->buffer_ratio;
++ priv->sdma_params.buffer_num = priv->periods;
++ priv->sdma_params.phyaddr = priv->phy_hdmi_sdma_t;
++
++ ret = hdmi_sdma_initbuf(dev, priv);
++ if (ret)
++ return ret;
++
++ ret = hdmi_sdma_config(substream, priv);
++ if (ret)
++ return ret;
++
++ snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
++
++ ret = hdmi_dma_configure_dma(dev, priv->channels);
++ if (ret)
++ return ret;
++
++ hdmi_dma_set_addr(priv->hw_buffer.addr, priv->dma_period_bytes);
++
++ dumppriv(dev, priv);
++
++ hdmi_dma_update_iec_header(substream);
++
++ /* Init par for mmap optimizate */
++ init_table(priv->channels);
++
++ priv->appl_bytes = 0;
++ priv->frame_idx = 0;
++
++ return 0;
++}
++
++static void hdmi_dma_trigger_init(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ unsigned long status;
++ bool hbr;
++
++ /*
++ * Set HBR mode (>192kHz IEC-61937 HD audio bitstreaming).
++ * This is done this late because userspace may alter the AESx
++ * parameters until the stream is finally prepared.
++ */
++ hbr = (iec_header.B.linear_pcm != 0 && priv->channels == 8);
++ hdmi_audio_writeb(AHB_DMA_CONF0, HBR, !!hbr);
++
++ /*
++ * Override AES3 - parameter: This is a temporary hack for
++ * callers that provide incorrect information when opening
++ * the device. 0x09 (i.e. 768K) is the only acceptable value.
++ */
++ if (hbr) {
++ iec_header.B.sample_freq = 0x09;
++ iec_header.B.org_sample_freq = 0x00;
++ }
++
++ priv->offset = 0;
++
++ /* Copy data by buffer_bytes */
++ hdmi_dma_data_copy(substream, priv, 'b');
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, SW_FIFO_RST, 0x1);
++
++ /* Delay after reset */
++ udelay(1);
++
++ status = hdmi_readb(HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_writeb(status, HDMI_IH_AHBDMAAUD_STAT0);
++}
++
++static int hdmi_dma_prepare_and_submit(struct snd_pcm_substream *substream,
++ struct hdmi_dma_priv *priv)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++
++ priv->desc = dmaengine_prep_dma_cyclic(priv->dma_channel, 0, 0, 0,
++ DMA_TRANS_NONE, 0);
++ if (!priv->desc) {
++ dev_err(dev, "failed to prepare slave dma\n");
++ return -EINVAL;
++ }
++
++ priv->desc->callback = hdmi_sdma_callback;
++ priv->desc->callback_param = (void *)priv;
++ dmaengine_submit(priv->desc);
++
++ return 0;
++}
++
++static int hdmi_dma_trigger(struct snd_pcm_substream *substream, int cmd)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++ struct device *dev = rtd->platform->dev;
++ int ret;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ if (!check_hdmi_state())
++ return 0;
++ hdmi_dma_trigger_init(substream, priv);
++
++ dumpregs(dev);
++
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ priv->tx_active = true;
++ hdmi_audio_writeb(AHB_DMA_START, START, 0x1);
++ hdmi_dma_irq_set(false);
++ hdmi_set_dma_mode(1);
++ ret = hdmi_dma_prepare_and_submit(substream, priv);
++ if (ret)
++ return ret;
++ dma_async_issue_pending(priv->desc->chan);
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ dmaengine_terminate_all(priv->dma_channel);
++ hdmi_set_dma_mode(0);
++ hdmi_dma_irq_set(true);
++ hdmi_audio_writeb(AHB_DMA_STOP, STOP, 0x1);
++ priv->tx_active = false;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static snd_pcm_uframes_t hdmi_dma_pointer(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ return bytes_to_frames(runtime, priv->offset);
++}
++
++static struct snd_pcm_hardware snd_imx_hardware = {
++ .info = SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER |
++ SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID |
++ SNDRV_PCM_INFO_PAUSE |
++ SNDRV_PCM_INFO_RESUME,
++ .formats = MXC_HDMI_FORMATS_PLAYBACK,
++ .rate_min = 32000,
++ .channels_min = 2,
++ .channels_max = 8,
++ .buffer_bytes_max = HDMI_PCM_BUF_SIZE,
++ .period_bytes_min = HDMI_DMA_PERIOD_BYTES / 2,
++ .period_bytes_max = HDMI_DMA_PERIOD_BYTES / 2,
++ .periods_min = 8,
++ .periods_max = HDMI_DMA_BUF_SIZE / HDMI_DMA_PERIOD_BYTES,
++ .fifo_size = 0,
++};
++
++static void hdmi_dma_irq_enable(struct hdmi_dma_priv *priv)
++{
++ unsigned long flags;
++
++ hdmi_writeb(0xff, HDMI_AHB_DMA_POL);
++ hdmi_writeb(0xff, HDMI_AHB_DMA_BUFFPOL);
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ hdmi_writeb(0xff, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_dma_irq_set(false);
++ hdmi_mask(0);
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++}
++
++static void hdmi_dma_irq_disable(struct hdmi_dma_priv *priv)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->irq_lock, flags);
++
++ hdmi_dma_irq_set(true);
++ hdmi_writeb(0x0, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
++ hdmi_writeb(0xff, HDMI_IH_AHBDMAAUD_STAT0);
++ hdmi_mask(1);
++
++ spin_unlock_irqrestore(&priv->irq_lock, flags);
++}
++
++static int hdmi_dma_open(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct device *dev = rtd->platform->dev;
++ struct hdmi_dma_priv *priv = dev_get_drvdata(dev);
++ int ret;
++
++ runtime->private_data = priv;
++
++ ret = mxc_hdmi_register_audio(substream);
++ if (ret < 0) {
++ dev_err(dev, "HDMI Video is not ready!\n");
++ return ret;
++ }
++
++ hdmi_audio_writeb(AHB_DMA_CONF0, SW_FIFO_RST, 0x1);
++
++ ret = snd_pcm_hw_constraint_integer(substream->runtime,
++ SNDRV_PCM_HW_PARAM_PERIODS);
++ if (ret < 0)
++ return ret;
++
++ snd_soc_set_runtime_hwparams(substream, &snd_imx_hardware);
++
++ hdmi_dma_irq_enable(priv);
++
++ return 0;
++}
++
++static int hdmi_dma_close(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ struct hdmi_dma_priv *priv = runtime->private_data;
++
++ hdmi_dma_irq_disable(priv);
++ mxc_hdmi_unregister_audio(substream);
++
++ return 0;
++}
++
++static struct snd_pcm_ops imx_hdmi_dma_pcm_ops = {
++ .open = hdmi_dma_open,
++ .close = hdmi_dma_close,
++ .ioctl = snd_pcm_lib_ioctl,
++ .hw_params = hdmi_dma_hw_params,
++ .hw_free = hdmi_dma_hw_free,
++ .trigger = hdmi_dma_trigger,
++ .pointer = hdmi_dma_pointer,
++ .copy = hdmi_dma_copy,
++};
++
++static int imx_hdmi_dma_pcm_new(struct snd_soc_pcm_runtime *rtd)
++{
++ struct hdmi_dma_priv *priv = dev_get_drvdata(rtd->platform->dev);
++ struct snd_card *card = rtd->card->snd_card;
++ struct snd_pcm_substream *substream;
++ struct snd_pcm *pcm = rtd->pcm;
++ u64 dma_mask = DMA_BIT_MASK(32);
++ int ret = 0;
++
++ if (!card->dev->dma_mask)
++ card->dev->dma_mask = &dma_mask;
++ if (!card->dev->coherent_dma_mask)
++ card->dev->coherent_dma_mask = DMA_BIT_MASK(32);
++
++ substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
++
++ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
++ HDMI_PCM_BUF_SIZE, &substream->dma_buffer);
++ if (ret) {
++ dev_err(card->dev, "failed to alloc playback dma buffer\n");
++ return ret;
++ }
++
++ priv->substream = substream;
++
++ /* Alloc the hw_buffer */
++ ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, pcm->card->dev,
++ HDMI_DMA_BUF_SIZE, &priv->hw_buffer);
++ if (ret) {
++ dev_err(card->dev, "failed to alloc hw dma buffer\n");
++ return ret;
++ }
++
++ return ret;
++}
++
++static void imx_hdmi_dma_pcm_free(struct snd_pcm *pcm)
++{
++ int stream = SNDRV_PCM_STREAM_PLAYBACK;
++ struct snd_pcm_substream *substream = pcm->streams[stream].substream;
++ struct snd_soc_pcm_runtime *rtd = pcm->private_data;
++ struct hdmi_dma_priv *priv = dev_get_drvdata(rtd->platform->dev);
++
++ if (substream) {
++ snd_dma_free_pages(&substream->dma_buffer);
++ substream->dma_buffer.area = NULL;
++ substream->dma_buffer.addr = 0;
++ }
++
++ /* Free the hw_buffer */
++ snd_dma_free_pages(&priv->hw_buffer);
++ priv->hw_buffer.area = NULL;
++ priv->hw_buffer.addr = 0;
++}
++
++static struct snd_soc_platform_driver imx_hdmi_platform = {
++ .ops = &imx_hdmi_dma_pcm_ops,
++ .pcm_new = imx_hdmi_dma_pcm_new,
++ .pcm_free = imx_hdmi_dma_pcm_free,
++};
++
++static int imx_soc_platform_probe(struct platform_device *pdev)
++{
++ struct imx_hdmi *hdmi_drvdata = platform_get_drvdata(pdev);
++ struct hdmi_dma_priv *priv;
++ int ret = 0;
++
++ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv) {
++ dev_err(&pdev->dev, "Failed to alloc hdmi_dma\n");
++ return -ENOMEM;
++ }
++
++ priv->hdmi_sdma_t = dma_alloc_coherent(NULL,
++ sizeof(struct hdmi_sdma_script),
++ &priv->phy_hdmi_sdma_t, GFP_KERNEL);
++ if (!priv->hdmi_sdma_t) {
++ dev_err(&pdev->dev, "Failed to alloc hdmi_sdma_t\n");
++ return -ENOMEM;
++ }
++
++ priv->tx_active = false;
++ spin_lock_init(&priv->irq_lock);
++
++ priv->pdev = hdmi_drvdata->pdev;
++
++ hdmi_dma_init_iec_header();
++
++ dev_set_drvdata(&pdev->dev, priv);
++
++ switch (hdmi_readb(HDMI_REVISION_ID)) {
++ case 0x0a:
++ snd_imx_hardware.period_bytes_max = HDMI_DMA_PERIOD_BYTES / 4;
++ snd_imx_hardware.period_bytes_min = HDMI_DMA_PERIOD_BYTES / 4;
++ snd_imx_hardware.periods_max = HDMI_DMA_BUF_SIZE / (HDMI_DMA_PERIOD_BYTES / 2);
++ break;
++ default:
++ break;
++ }
++
++ ret = snd_soc_register_platform(&pdev->dev, &imx_hdmi_platform);
++ if (ret)
++ goto err_plat;
++
++ return 0;
++
++err_plat:
++ dma_free_coherent(NULL, sizeof(struct hdmi_sdma_script),
++ priv->hdmi_sdma_t, priv->phy_hdmi_sdma_t);
++
++ return ret;
++}
++
++static int imx_soc_platform_remove(struct platform_device *pdev)
++{
++ struct hdmi_dma_priv *priv = dev_get_drvdata(&pdev->dev);
++
++ dma_free_coherent(NULL, sizeof(struct hdmi_sdma_script),
++ priv->hdmi_sdma_t, priv->phy_hdmi_sdma_t);
++
++ snd_soc_unregister_platform(&pdev->dev);
++
++ return 0;
++}
++
++static struct platform_driver imx_hdmi_dma_driver = {
++ .driver = {
++ .name = "imx-hdmi-audio",
++ .owner = THIS_MODULE,
++ },
++ .probe = imx_soc_platform_probe,
++ .remove = imx_soc_platform_remove,
++};
++
++module_platform_driver(imx_hdmi_dma_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("i.MX HDMI audio DMA");
++MODULE_LICENSE("GPL");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-hdmi.h linux-3.14.72/sound/soc/fsl/imx-hdmi.h
+--- linux-3.14.72.orig/sound/soc/fsl/imx-hdmi.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-hdmi.h 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,106 @@
++/*
++ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __IMX_HDMI_H
++#define __IMX_HDMI_H
++
++struct imx_hdmi_sdma_params {
++ dma_addr_t phyaddr;
++ u32 buffer_num;
++ int dma;
++};
++
++struct imx_hdmi {
++ struct snd_soc_dai_driver cpu_dai_drv;
++ struct platform_device *codec_dev;
++ struct platform_device *dma_dev;
++ struct platform_device *pdev;
++ struct clk *isfr_clk;
++ struct clk *iahb_clk;
++ struct clk *mipi_core_clk;
++};
++
++#define HDMI_MAX_RATES 7
++#define HDMI_MAX_SAMPLE_SIZE 3
++#define HDMI_MAX_CHANNEL_CONSTRAINTS 4
++
++#define MXC_HDMI_RATES_PLAYBACK \
++ (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \
++ SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
++ SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
++
++#define MXC_HDMI_FORMATS_PLAYBACK \
++ (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
++
++union hdmi_audio_header_t {
++ uint64_t U;
++ struct {
++ unsigned consumer:1;
++ unsigned linear_pcm:1;
++ unsigned copyright:1;
++ unsigned pre_emphasis:3;
++ unsigned mode:2;
++
++ unsigned category_code:8;
++
++ unsigned source:4;
++ unsigned channel:4;
++
++ unsigned sample_freq:4;
++ unsigned clock_acc:2;
++ unsigned reserved0:2;
++
++ unsigned word_length:4;
++ unsigned org_sample_freq:4;
++
++ unsigned cgms_a:2;
++ unsigned reserved1:6;
++
++ unsigned reserved2:8;
++
++ unsigned reserved3:8;
++ } B;
++ unsigned char status[8];
++};
++
++union hdmi_audio_dma_data_t {
++ uint32_t U;
++ struct {
++ unsigned data:24;
++ unsigned v:1;
++ unsigned u:1;
++ unsigned c:1;
++ unsigned p:1;
++ unsigned b:1;
++ unsigned reserved:3;
++ } B;
++};
++
++extern union hdmi_audio_header_t iec_header;
++
++#define hdmi_audio_writeb(reg, bit, val) \
++ do { \
++ hdmi_mask_writeb(val, HDMI_ ## reg, \
++ HDMI_ ## reg ## _ ## bit ## _OFFSET, \
++ HDMI_ ## reg ## _ ## bit ## _MASK); \
++ pr_debug("Set reg: HDMI_" #reg " (0x%x) "\
++ "bit: HDMI_" #reg "_" #bit " (%d) to val: %x\n", \
++ HDMI_ ## reg, HDMI_ ## reg ## _ ## bit ## _OFFSET, val); \
++ } while (0)
++
++#endif /* __IMX_HDMI_H */
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-mqs.c linux-3.14.72/sound/soc/fsl/imx-mqs.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-mqs.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-mqs.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,152 @@
++/*
++ * Copyright 2012, 2014 Freescale Semiconductor, Inc.
++ * Copyright 2012 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/clk.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <sound/soc.h>
++
++#define SUPPORT_RATE_NUM 10
++
++struct imx_priv {
++ unsigned int mclk_freq;
++ struct platform_device *pdev;
++};
++
++static struct imx_priv card_priv;
++
++static int imx_mqs_startup(struct snd_pcm_substream *substream)
++{
++ struct snd_pcm_runtime *runtime = substream->runtime;
++ static struct snd_pcm_hw_constraint_list constraint_rates;
++ struct imx_priv *priv = &card_priv;
++ struct device *dev = &priv->pdev->dev;
++ static u32 support_rates[SUPPORT_RATE_NUM];
++ int ret;
++
++ if (priv->mclk_freq == 24576000) {
++ support_rates[0] = 48000;
++ support_rates[1] = 96000;
++ support_rates[2] = 192000;
++ constraint_rates.list = support_rates;
++ constraint_rates.count = 3;
++
++ ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
++ &constraint_rates);
++ if (ret)
++ return ret;
++ } else
++ dev_warn(dev, "mclk may be not supported %d\n", priv->mclk_freq);
++
++ return 0;
++}
++
++static struct snd_soc_ops imx_mqs_ops = {
++ .startup = imx_mqs_startup,
++};
++
++
++
++static struct snd_soc_dai_link imx_mqs_dai = {
++ .name = "HiFi",
++ .stream_name = "HiFi",
++ .dai_fmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS,
++ .ops = &imx_mqs_ops,
++};
++
++static struct snd_soc_card snd_soc_card_imx_mqs = {
++ .name = "mqs-audio",
++ .dai_link = &imx_mqs_dai,
++ .owner = THIS_MODULE,
++ .num_links = 1,
++};
++
++static int imx_mqs_probe(struct platform_device *pdev)
++{
++ struct device_node *cpu_np, *codec_np;
++ struct imx_priv *priv = &card_priv;
++ struct clk *codec_clk = NULL;
++ struct platform_device *codec_dev;
++ int ret;
++
++ priv->pdev = pdev;
++
++ cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0);
++ if (!cpu_np) {
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
++ if (!codec_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ codec_dev = of_find_device_by_node(codec_np);
++ if (!codec_dev) {
++ dev_err(&codec_dev->dev, "failed to find codec device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ codec_clk = devm_clk_get(&codec_dev->dev, NULL);
++ if (IS_ERR(codec_clk)) {
++ ret = PTR_ERR(codec_clk);
++ dev_err(&codec_dev->dev, "failed to get codec clk: %d\n", ret);
++ goto fail;
++ }
++ priv->mclk_freq = clk_get_rate(codec_clk);
++
++
++ imx_mqs_dai.cpu_of_node = cpu_np;
++ imx_mqs_dai.platform_of_node = cpu_np;
++ imx_mqs_dai.codec_dai_name = "fsl-mqs-dai";
++ imx_mqs_dai.codec_of_node = codec_np;
++ snd_soc_card_imx_mqs.dev = &pdev->dev;
++
++ ret = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_imx_mqs);
++ if (ret) {
++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
++ goto fail;
++ }
++
++fail:
++ if (cpu_np)
++ of_node_put(cpu_np);
++
++ return ret;
++}
++
++static const struct of_device_id imx_mqs_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-mqs", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_mqs_dt_ids);
++
++static struct platform_driver imx_mqs_driver = {
++ .driver = {
++ .name = "imx-mqs",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_mqs_dt_ids,
++ },
++ .probe = imx_mqs_probe,
++};
++module_platform_driver(imx_mqs_driver);
++
++MODULE_AUTHOR("Nicolin Chen <Guangyu.Chen@freescale.com>");
++MODULE_DESCRIPTION("Freescale i.MX MQS ASoC machine driver");
++MODULE_ALIAS("platform:imx-mqs");
++MODULE_LICENSE("GPL v2");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-pcm-dma.c linux-3.14.72/sound/soc/fsl/imx-pcm-dma.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-pcm-dma.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/imx-pcm-dma.c 2016-06-19 22:11:55.529125309 +0200
+@@ -40,27 +40,82 @@
+ SNDRV_PCM_INFO_MMAP_VALID |
+ SNDRV_PCM_INFO_PAUSE |
+ SNDRV_PCM_INFO_RESUME,
+- .formats = SNDRV_PCM_FMTBIT_S16_LE,
+- .buffer_bytes_max = IMX_SSI_DMABUF_SIZE,
++ .buffer_bytes_max = IMX_DEFAULT_DMABUF_SIZE,
+ .period_bytes_min = 128,
+ .period_bytes_max = 65535, /* Limited by SDMA engine */
+- .periods_min = 2,
++ .periods_min = 4,
+ .periods_max = 255,
+ .fifo_size = 0,
+ };
+
++static void imx_pcm_dma_complete(void *arg)
++{
++ struct snd_pcm_substream *substream = arg;
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct dmaengine_pcm_runtime_data *prtd = substream->runtime->private_data;
++ struct snd_dmaengine_dai_dma_data *dma_data;
++
++ prtd->pos += snd_pcm_lib_period_bytes(substream);
++ if (prtd->pos >= snd_pcm_lib_buffer_bytes(substream))
++ prtd->pos = 0;
++
++ snd_pcm_period_elapsed(substream);
++
++ dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
++ if (dma_data->check_xrun && dma_data->check_xrun(substream))
++ dma_data->device_reset(substream, 1);
++}
++
++static int imx_pcm_dma_prepare_slave_config(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params, struct dma_slave_config *slave_config)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_dmaengine_dai_dma_data *dma_data;
++ struct dmaengine_pcm_runtime_data *prtd = substream->runtime->private_data;
++ int ret;
++
++ dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
++ prtd->callback = imx_pcm_dma_complete;
++
++ ret = snd_hwparams_to_dma_slave_config(substream, params, slave_config);
++ if (ret)
++ return ret;
++
++ snd_dmaengine_pcm_set_config_from_dai_data(substream, dma_data,
++ slave_config);
++
++ return 0;
++
++}
++
+ static const struct snd_dmaengine_pcm_config imx_dmaengine_pcm_config = {
+ .pcm_hardware = &imx_pcm_hardware,
+- .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++ .prepare_slave_config = imx_pcm_dma_prepare_slave_config,
+ .compat_filter_fn = filter,
+- .prealloc_buffer_size = IMX_SSI_DMABUF_SIZE,
++ .prealloc_buffer_size = IMX_DEFAULT_DMABUF_SIZE,
+ };
+
+-int imx_pcm_dma_init(struct platform_device *pdev)
++int imx_pcm_dma_init(struct platform_device *pdev, size_t size)
+ {
++ struct snd_dmaengine_pcm_config *config;
++ struct snd_pcm_hardware *pcm_hardware;
++
++ config = devm_kzalloc(&pdev->dev,
++ sizeof(struct snd_dmaengine_pcm_config), GFP_KERNEL);
++ *config = imx_dmaengine_pcm_config;
++ if (size)
++ config->prealloc_buffer_size = size;
++
++ pcm_hardware = devm_kzalloc(&pdev->dev,
++ sizeof(struct snd_pcm_hardware), GFP_KERNEL);
++ *pcm_hardware = imx_pcm_hardware;
++ if (size)
++ pcm_hardware->buffer_bytes_max = size;
++
++ config->pcm_hardware = pcm_hardware;
++
+ return devm_snd_dmaengine_pcm_register(&pdev->dev,
+- &imx_dmaengine_pcm_config,
+- SND_DMAENGINE_PCM_FLAG_NO_RESIDUE |
++ config,
+ SND_DMAENGINE_PCM_FLAG_COMPAT);
+ }
+ EXPORT_SYMBOL_GPL(imx_pcm_dma_init);
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-pcm-fiq.c linux-3.14.72/sound/soc/fsl/imx-pcm-fiq.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-pcm-fiq.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/imx-pcm-fiq.c 2016-06-19 22:11:55.529125309 +0200
+@@ -270,18 +270,17 @@
+ ret = imx_pcm_preallocate_dma_buffer(pcm,
+ SNDRV_PCM_STREAM_PLAYBACK);
+ if (ret)
+- goto out;
++ return ret;
+ }
+
+ if (pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream) {
+ ret = imx_pcm_preallocate_dma_buffer(pcm,
+ SNDRV_PCM_STREAM_CAPTURE);
+ if (ret)
+- goto out;
++ return ret;
+ }
+
+-out:
+- return ret;
++ return 0;
+ }
+
+ static int ssi_irq = 0;
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-pcm.h linux-3.14.72/sound/soc/fsl/imx-pcm.h
+--- linux-3.14.72.orig/sound/soc/fsl/imx-pcm.h 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/imx-pcm.h 2016-06-19 22:11:55.529125309 +0200
+@@ -18,7 +18,12 @@
+ /*
+ * Do not change this as the FIQ handler depends on this size
+ */
++#define IMX_DEFAULT_DMABUF_SIZE (256 * 1024)
+ #define IMX_SSI_DMABUF_SIZE (64 * 1024)
++#define IMX_SAI_DMABUF_SIZE (64 * 1024)
++#define IMX_SPDIF_DMABUF_SIZE (64 * 1024)
++#define IMX_ESAI_DMABUF_SIZE (256 * 1024)
++#define IMX_ASRC_DMABUF_SIZE (256 * 1024)
+
+ static inline void
+ imx_pcm_dma_params_init_data(struct imx_dma_data *dma_data,
+@@ -39,9 +44,9 @@
+ };
+
+ #if IS_ENABLED(CONFIG_SND_SOC_IMX_PCM_DMA)
+-int imx_pcm_dma_init(struct platform_device *pdev);
++int imx_pcm_dma_init(struct platform_device *pdev, size_t size);
+ #else
+-static inline int imx_pcm_dma_init(struct platform_device *pdev)
++static inline int imx_pcm_dma_init(struct platform_device *pdev, size_t size)
+ {
+ return -ENODEV;
+ }
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-sgtl5000.c linux-3.14.72/sound/soc/fsl/imx-sgtl5000.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-sgtl5000.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/imx-sgtl5000.c 2016-06-19 22:11:55.529125309 +0200
+@@ -1,5 +1,5 @@
+ /*
+- * Copyright 2012 Freescale Semiconductor, Inc.
++ * Copyright 2012, 2014 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+@@ -55,13 +55,9 @@
+ SND_SOC_DAPM_SPK("Ext Spk", NULL),
+ };
+
+-static int imx_sgtl5000_probe(struct platform_device *pdev)
++static int imx_sgtl5000_audmux_config(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+- struct device_node *ssi_np, *codec_np;
+- struct platform_device *ssi_pdev;
+- struct i2c_client *codec_dev;
+- struct imx_sgtl5000_data *data = NULL;
+ int int_port, ext_port;
+ int ret;
+
+@@ -101,16 +97,33 @@
+ return ret;
+ }
+
+- ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
++ return 0;
++}
++
++static int imx_sgtl5000_probe(struct platform_device *pdev)
++{
++ struct device_node *cpu_np, *codec_np;
++ struct platform_device *cpu_pdev;
++ struct i2c_client *codec_dev;
++ struct imx_sgtl5000_data *data = NULL;
++ int ret;
++
++ cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0);
+ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
+- if (!ssi_np || !codec_np) {
++ if (!cpu_np || !codec_np) {
+ dev_err(&pdev->dev, "phandle missing or invalid\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+- ssi_pdev = of_find_device_by_node(ssi_np);
+- if (!ssi_pdev) {
++ if (strstr(cpu_np->name, "ssi")) {
++ ret = imx_sgtl5000_audmux_config(pdev);
++ if (ret)
++ goto fail;
++ }
++
++ cpu_pdev = of_find_device_by_node(cpu_np);
++ if (!cpu_pdev) {
+ dev_err(&pdev->dev, "failed to find SSI platform device\n");
+ ret = -EPROBE_DEFER;
+ goto fail;
+@@ -139,8 +152,8 @@
+ data->dai.stream_name = "HiFi";
+ data->dai.codec_dai_name = "sgtl5000";
+ data->dai.codec_of_node = codec_np;
+- data->dai.cpu_of_node = ssi_np;
+- data->dai.platform_of_node = ssi_np;
++ data->dai.cpu_of_node = cpu_np;
++ data->dai.platform_of_node = cpu_np;
+ data->dai.init = &imx_sgtl5000_dai_init;
+ data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM;
+@@ -167,7 +180,7 @@
+ goto fail;
+ }
+
+- of_node_put(ssi_np);
++ of_node_put(cpu_np);
+ of_node_put(codec_np);
+
+ return 0;
+@@ -175,8 +188,8 @@
+ fail:
+ if (data && !IS_ERR(data->codec_clk))
+ clk_put(data->codec_clk);
+- if (ssi_np)
+- of_node_put(ssi_np);
++ if (cpu_np)
++ of_node_put(cpu_np);
+ if (codec_np)
+ of_node_put(codec_np);
+
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-si476x.c linux-3.14.72/sound/soc/fsl/imx-si476x.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-si476x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-si476x.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,205 @@
++/*
++ * Copyright (C) 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/i2c.h>
++#include <sound/soc.h>
++
++#include "imx-audmux.h"
++
++static int imx_audmux_config(int slave, int master)
++{
++ unsigned int ptcr, pdcr;
++ slave = slave - 1;
++ master = master - 1;
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_TFSDIR |
++ IMX_AUDMUX_V2_PTCR_TFSEL(slave) |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR |
++ IMX_AUDMUX_V2_PTCR_TCSEL(slave);
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave);
++ imx_audmux_v2_configure_port(master, ptcr, pdcr);
++
++ /*
++ * According to RM, RCLKDIR and SYN should not be changed at same time.
++ * So separate to two step for configuring this port.
++ */
++ ptcr |= IMX_AUDMUX_V2_PTCR_RFSDIR |
++ IMX_AUDMUX_V2_PTCR_RFSEL(slave) |
++ IMX_AUDMUX_V2_PTCR_RCLKDIR |
++ IMX_AUDMUX_V2_PTCR_RCSEL(slave);
++ imx_audmux_v2_configure_port(master, ptcr, pdcr);
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN;
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master);
++ imx_audmux_v2_configure_port(slave, ptcr, pdcr);
++
++ return 0;
++}
++
++static int imx_si476x_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ u32 channels = params_channels(params);
++ u32 rate = params_rate(params);
++ u32 bclk = rate * channels * 32;
++ int ret = 0;
++
++ /* set cpu DAI configuration */
++ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S
++ | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS);
++ if (ret) {
++ dev_err(cpu_dai->dev, "failed to set dai fmt\n");
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_tdm_slot(cpu_dai,
++ channels == 1 ? 0xfffffffe : 0xfffffffc,
++ channels == 1 ? 0xfffffffe : 0xfffffffc,
++ 2, 32);
++ if (ret) {
++ dev_err(cpu_dai->dev, "failed to set dai tdm slot\n");
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, bclk, SND_SOC_CLOCK_OUT);
++ if (ret)
++ dev_err(cpu_dai->dev, "failed to set sysclk\n");
++
++ return ret;
++}
++
++static struct snd_soc_ops imx_si476x_ops = {
++ .hw_params = imx_si476x_hw_params,
++};
++
++static struct snd_soc_dai_link imx_dai = {
++ .name = "imx-si476x",
++ .stream_name = "imx-si476x",
++ .codec_dai_name = "si476x-codec",
++ .ops = &imx_si476x_ops,
++};
++
++static struct snd_soc_card snd_soc_card_imx_3stack = {
++ .name = "imx-audio-si476x",
++ .dai_link = &imx_dai,
++ .num_links = 1,
++};
++
++static int imx_si476x_probe(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = &snd_soc_card_imx_3stack;
++ struct device_node *ssi_np, *np = pdev->dev.of_node;
++ struct platform_device *ssi_pdev;
++ struct i2c_client *fm_dev;
++ struct device_node *fm_np;
++ int int_port, ext_port, ret;
++
++ ret = of_property_read_u32(np, "mux-int-port", &int_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
++ return ret;
++ }
++
++ ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
++ return ret;
++ }
++
++ imx_audmux_config(int_port, ext_port);
++
++ ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
++ if (!ssi_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ return -EINVAL;
++ }
++
++ ssi_pdev = of_find_device_by_node(ssi_np);
++ if (!ssi_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ fm_np = of_parse_phandle(pdev->dev.of_node, "fm-controller", 0);
++ if (!fm_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ fm_dev = of_find_i2c_device_by_node(fm_np->parent);
++ if (!fm_dev || !fm_dev->dev.driver) {
++ dev_err(&pdev->dev, "failed to find FM platform device\n");
++ ret = -EINVAL;
++ goto end;
++ }
++
++ card->dev = &pdev->dev;
++ card->dai_link->cpu_dai_name = dev_name(&ssi_pdev->dev);
++ card->dai_link->platform_of_node = ssi_np;
++ card->dai_link->codec_of_node = fm_np;
++
++ platform_set_drvdata(pdev, card);
++
++ ret = snd_soc_register_card(card);
++ if (ret)
++ dev_err(&pdev->dev, "Failed to register card: %d\n", ret);
++
++end:
++ if (ssi_np)
++ of_node_put(ssi_np);
++ if (fm_np)
++ of_node_put(fm_np);
++
++ return ret;
++}
++
++static int imx_si476x_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = &snd_soc_card_imx_3stack;
++
++ snd_soc_unregister_card(card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_si476x_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-si476x", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_si476x_dt_ids);
++
++static struct platform_driver imx_si476x_driver = {
++ .driver = {
++ .name = "imx-tuner-si476x",
++ .owner = THIS_MODULE,
++ .pm = &snd_soc_pm_ops,
++ .of_match_table = imx_si476x_dt_ids,
++ },
++ .probe = imx_si476x_probe,
++ .remove = imx_si476x_remove,
++};
++
++module_platform_driver(imx_si476x_driver);
++
++/* Module information */
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("ALSA SoC i.MX si476x");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:imx-tuner-si476x");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-ssi.c linux-3.14.72/sound/soc/fsl/imx-ssi.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-ssi.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/imx-ssi.c 2016-06-19 22:11:55.529125309 +0200
+@@ -602,7 +602,7 @@
+ ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
+
+ ssi->fiq_init = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
+- ssi->dma_init = imx_pcm_dma_init(pdev);
++ ssi->dma_init = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
+
+ if (ssi->fiq_init && ssi->dma_init) {
+ ret = ssi->fiq_init;
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-tda1997x.c linux-3.14.72/sound/soc/fsl/imx-tda1997x.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-tda1997x.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-tda1997x.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,195 @@
++/*
++ * SoC audio for i.MX boards with tda1997x HDMI receiver
++ * based off sound/soc/fsl/imx-sgtl5000.c
++ *
++ * Copyright 2013 Tim Harvey, Gateworks Corporation <tharvey@gateworks.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
++ *
++ */
++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
++
++#include <linux/clk.h>
++#include <linux/mfd/tda1997x-core.h>
++#include <linux/module.h>
++#include <linux/gpio.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <sound/core.h>
++#include <sound/soc.h>
++
++#include "imx-audmux.h"
++
++#define DAI_NAME_SIZE 32
++
++struct imx_tda1997x_data {
++ struct snd_soc_dai_link dai;
++ struct snd_soc_card card;
++ char codec_dai_name[DAI_NAME_SIZE];
++ char platform_name[DAI_NAME_SIZE];
++};
++
++static int imx_tda1997x_dai_init(struct snd_soc_pcm_runtime *rtd)
++{
++ return 0;
++}
++
++static int imx_tda1997x_audmux_config(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ int int_port, ext_port;
++ int ret;
++
++ ret = of_property_read_u32(np, "mux-int-port", &int_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
++ return ret;
++ }
++ ret = of_property_read_u32(np, "mux-ext-port", &ext_port);
++ if (ret) {
++ dev_err(&pdev->dev, "mux-ext-port missing or invalid\n");
++ return ret;
++ }
++
++ /*
++ * The port numbering in the hardware manual starts at 1, while
++ * the audmux API expects it starts at 0.
++ */
++ int_port--;
++ ext_port--;
++ ret = imx_audmux_v2_configure_port(int_port,
++ IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_TFSEL(ext_port) |
++ IMX_AUDMUX_V2_PTCR_TCSEL(ext_port) |
++ IMX_AUDMUX_V2_PTCR_TFSDIR |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR |
++ (1<<30) | /* use RXFS from port instead of TXFS */
++ (1<<25), /* use RXC from port instead of TXC */
++ IMX_AUDMUX_V2_PDCR_RXDSEL(ext_port));
++ if (ret) {
++ dev_err(&pdev->dev, "audmux internal port setup failed\n");
++ return ret;
++ }
++ ret = imx_audmux_v2_configure_port(ext_port,
++ IMX_AUDMUX_V2_PTCR_SYN,
++ IMX_AUDMUX_V2_PDCR_RXDSEL(int_port));
++ if (ret) {
++ dev_err(&pdev->dev, "audmux external port setup failed\n");
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_tda1997x_probe(struct platform_device *pdev)
++{
++ struct device_node *cpu_np, *codec_np;
++ struct platform_device *cpu_pdev;
++ struct imx_tda1997x_data *data;
++ int ret;
++
++ cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0);
++ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
++ if (!cpu_np || !codec_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ if (strstr(cpu_np->name, "ssi")) {
++ ret = imx_tda1997x_audmux_config(pdev);
++ if (ret)
++ goto fail;
++ }
++
++ cpu_pdev = of_find_device_by_node(cpu_np);
++ if (!cpu_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ data->dai.name = "i.MX HDMI Audio Rx";
++ data->dai.stream_name = "i.MX HDMI Audio Rx";
++ data->dai.codec_dai_name = "tda1997x";
++ data->dai.codec_of_node = codec_np;
++ data->dai.cpu_of_node = cpu_np;
++ data->dai.platform_of_node = cpu_np;
++ data->dai.init = &imx_tda1997x_dai_init;
++ data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ data->card.dev = &pdev->dev;
++ ret = snd_soc_of_parse_card_name(&data->card, "model");
++ if (ret)
++ goto fail;
++ data->card.num_links = 1;
++ data->card.owner = THIS_MODULE;
++ data->card.dai_link = &data->dai;
++
++ /* register card with ASoC core */
++ ret = snd_soc_register_card(&data->card);
++ if (ret) {
++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
++ goto fail;
++ }
++
++ platform_set_drvdata(pdev, data);
++fail:
++ if (cpu_np)
++ of_node_put(cpu_np);
++ if (codec_np)
++ of_node_put(codec_np);
++
++ return ret;
++}
++
++static int imx_tda1997x_remove(struct platform_device *pdev)
++{
++ struct imx_tda1997x_data *data = platform_get_drvdata(pdev);
++
++ snd_soc_unregister_card(&data->card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_tda1997x_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-tda1997x", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_tda1997x_dt_ids);
++
++static struct platform_driver imx_tda1997x_audio_driver = {
++ .driver = {
++ .name = "imx-tda1997x-audio",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_tda1997x_dt_ids,
++ },
++ .probe = imx_tda1997x_probe,
++ .remove = imx_tda1997x_remove,
++};
++
++module_platform_driver(imx_tda1997x_audio_driver);
++
++MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
++MODULE_DESCRIPTION("Freescale i.MX TDA1997X RX ASoC machine driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:imx-tda1997x-audio");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-wm8731.c linux-3.14.72/sound/soc/fsl/imx-wm8731.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-wm8731.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-3.14.72/sound/soc/fsl/imx-wm8731.c 2016-06-19 22:11:55.529125309 +0200
+@@ -0,0 +1,682 @@
++/*
++ * Copyright (C) 2014 Freescale Semiconductor, Inc.
++ *
++ * Based on imx-sgtl5000.c
++ * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012 Linaro Ltd.
++ *
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++
++#include "../codecs/wm8731.h"
++#include "imx-audmux.h"
++#include "imx-ssi.h"
++
++#define DAI_NAME_SIZE 32
++#define WM8731_MCLK_FREQ (24000000 / 2)
++
++struct imx_wm8731_data {
++ struct snd_soc_dai_link dai;
++ struct snd_soc_card card;
++ char codec_dai_name[DAI_NAME_SIZE];
++ char platform_name[DAI_NAME_SIZE];
++ struct i2c_client *codec_dev;
++ /* audio_clocking_data */
++ struct clk *pll;
++ struct clk *clock_root;
++ long sysclk;
++ long current_rate;
++ /* apis */
++ int (*clock_enable)(int enable,struct imx_wm8731_data *data);
++};
++
++static int imx_wm8731_init(struct snd_soc_pcm_runtime *rtd);
++static int imx_hifi_hw_params_slv_mode(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params);
++static void imx_hifi_shutdown(struct snd_pcm_substream *substream);
++
++struct imx_priv {
++ struct platform_device *pdev;
++ struct imx_wm8731_data *data;
++};
++
++static struct imx_priv card_priv;
++
++static struct snd_soc_ops imx_hifi_ops = {
++ .shutdown = imx_hifi_shutdown,
++};
++
++/* imx card dapm widgets */
++static const struct snd_soc_dapm_widget imx_dapm_widgets[] = {
++ SND_SOC_DAPM_HP("Headphone Jack", NULL),
++ SND_SOC_DAPM_SPK("Ext Spk", NULL),
++ SND_SOC_DAPM_LINE("Line Jack", NULL),
++ SND_SOC_DAPM_MIC("Mic Jack", NULL),
++};
++
++/* imx machine connections to the codec pins */
++static const struct snd_soc_dapm_route audio_map[] = {
++ { "Headphone Jack", NULL, "LHPOUT" },
++ { "Headphone Jack", NULL, "RHPOUT" },
++
++ { "Ext Spk", NULL, "LOUT" },
++ { "Ext Spk", NULL, "ROUT" },
++
++ { "LLINEIN", NULL, "Line Jack" },
++ { "RLINEIN", NULL, "Line Jack" },
++
++ { "MICIN", NULL, "Mic Bias" },
++ { "Mic Bias", NULL, "Mic Jack"},
++};
++
++static int wm8731_slv_mode_init(struct imx_wm8731_data *data)
++{
++ struct clk *new_parent;
++ struct clk *ssi_clk;
++ struct i2c_client *codec_dev = data->codec_dev;
++
++ new_parent = devm_clk_get(&codec_dev->dev, "pll4");
++ if (IS_ERR(new_parent)) {
++ pr_err("Could not get \"pll4\" clock \n");
++ return PTR_ERR(new_parent);
++ }
++
++ ssi_clk = devm_clk_get(&codec_dev->dev, "imx-ssi.1");
++ if (IS_ERR(ssi_clk)) {
++ pr_err("Could not get \"imx-ssi.1\" clock \n");
++ return PTR_ERR(ssi_clk);
++ }
++
++ clk_set_parent(ssi_clk, new_parent);
++
++ data->pll = new_parent;
++ data->clock_root = ssi_clk;
++ data->current_rate = 0;
++
++ data->sysclk = 0;
++
++ return 0;
++}
++
++static int wm8731_slv_mode_clock_enable(int enable, struct imx_wm8731_data *data)
++{
++ long pll_rate;
++ long rate_req;
++ long rate_avail;
++
++ if (!enable)
++ return 0;
++
++ if (data->sysclk == data->current_rate)
++ return 0;
++
++ switch (data->sysclk) {
++ case 11289600:
++ pll_rate = 632217600;
++ break;
++
++ case 12288000:
++ pll_rate = 688128000;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ rate_req = pll_rate;
++ rate_avail = clk_round_rate(data->pll, rate_req);
++ clk_set_rate(data->pll, rate_avail);
++
++ rate_req = data->sysclk;
++ rate_avail = clk_round_rate(data->clock_root,
++ rate_req);
++ clk_set_rate(data->clock_root, rate_avail);
++
++ pr_info("%s: \"imx-ssi.1\" rate = %ld (= %ld)\n",
++ __func__, rate_avail, rate_req);
++
++ data->current_rate = data->sysclk;
++
++ return 0;
++}
++
++static int imx_hifi_startup_slv_mode(struct snd_pcm_substream *substream)
++{
++ /*
++ * As SSI's sys clock rate depends on sampling rate,
++ * the clock enabling code is moved to imx_hifi_hw_params().
++ */
++ return 0;
++}
++
++static int wm8731_mst_mode_init(struct imx_wm8731_data *data)
++{
++ long rate;
++ struct clk *new_parent;
++ struct clk *ssi_clk;
++ struct i2c_client *codec_dev = data->codec_dev;
++
++ new_parent = devm_clk_get(&codec_dev->dev, "cko2");
++ if (IS_ERR(new_parent)) {
++ pr_err("Could not get \"cko2\" clock \n");
++ return PTR_ERR(new_parent);
++ }
++
++ ssi_clk = devm_clk_get(&codec_dev->dev, "cko");
++ if (IS_ERR(ssi_clk)) {
++ pr_err("Could not get \"cko\" clock \n");
++ return PTR_ERR(ssi_clk);
++ }
++
++ rate = clk_round_rate(new_parent, WM8731_MCLK_FREQ);
++ clk_set_rate(new_parent, rate);
++
++ clk_set_parent(ssi_clk, new_parent);
++
++ rate = clk_round_rate(ssi_clk, WM8731_MCLK_FREQ);
++ clk_set_rate(ssi_clk, rate);
++
++ pr_info("%s: \"CLKO\" rate = %ld (= %d)\n",
++ __func__, rate, WM8731_MCLK_FREQ);
++
++ data->pll = new_parent;
++ data->clock_root = ssi_clk;
++ data->sysclk = rate;
++
++ return 0;
++}
++
++static int wm8731_mst_mode_clock_enable(int enable, struct imx_wm8731_data *data)
++{
++ struct clk *clko = data->clock_root;
++
++ if (enable)
++ clk_enable(clko);
++ else
++ clk_disable(clko);
++
++ return 0;
++}
++
++static int imx_hifi_startup_mst_mode(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_card *card = codec_dai->codec->card;
++ struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
++
++ if (!codec_dai->active)
++ data->clock_enable(1,data);
++
++ return 0;
++}
++
++
++static int imx_hifi_hw_params_slv_mode(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_card *card = codec_dai->codec->card;
++ struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
++
++ u32 dai_format;
++ snd_pcm_format_t sample_format;
++ unsigned int channels;
++ unsigned int tx_mask, rx_mask;
++ unsigned int sampling_rate;
++ unsigned int div_2, div_psr, div_pm;
++ int ret;
++
++ sampling_rate = params_rate(params);
++ sample_format = params_format(params);
++
++ channels = params_channels(params);
++ printk("%s:%s sampling rate = %u channels = %u \n", __FUNCTION__,
++ (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "Playback" : "Capture"),
++ sampling_rate, channels);
++
++ /* set CPU DAI configuration */
++ switch (sampling_rate) {
++ case 8000:
++ case 32000:
++ case 48000:
++ case 96000:
++ data->sysclk = 12288000;
++ break;
++
++ case 44100:
++ case 88200:
++ data->sysclk = 11289600;
++ break;
++
++ default:
++ return -EINVAL;
++ }
++
++ wm8731_slv_mode_clock_enable(1,data);
++
++ dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
++ SND_SOC_DAIFMT_CBS_CFS;
++
++ ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);
++ if (ret < 0)
++ return ret;
++
++ /* set i.MX active slot mask */
++ /* S[TR]CCR:DC */
++ tx_mask = ~((1 << channels) - 1);
++ rx_mask = tx_mask;
++ snd_soc_dai_set_tdm_slot(cpu_dai, tx_mask, rx_mask, 2, 32);
++
++ /*
++ * SSI sysclk divider:
++ * div_2: /1 or /2
++ * div_psr: /1 or /8
++ * div_pm: /1 .. /256
++ */
++ div_2 = 0;
++ div_psr = 0;
++ switch (sampling_rate) {
++ case 8000:
++ // 1x1x12
++ div_pm = 11;
++ break;
++ case 32000:
++ // 1x1x3
++ div_pm = 2;
++ break;
++ case 48000:
++ // 1x1x2
++ div_pm = 1;
++ break;
++ case 96000:
++ // 1x1x1
++ div_pm = 0;
++ break;
++ case 44100:
++ // 1x1x2
++ div_pm = 1;
++ break;
++ case 88200:
++ // 1x1x1
++ div_pm = 0;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* sync mode: a single clock controls both playback and capture */
++ snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, (div_2 ? SSI_STCCR_DIV2 : 0));
++ snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, (div_psr ? SSI_STCCR_PSR : 0));
++ snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, div_pm);
++
++ /* set codec DAI configuration */
++ dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBS_CFS;
++
++ ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
++ if (ret < 0)
++ return ret;
++
++ ret = snd_soc_dai_set_sysclk(codec_dai,
++ WM8731_SYSCLK_MCLK,
++ data->sysclk,
++ SND_SOC_CLOCK_IN);
++
++ if (ret < 0) {
++ pr_err("Failed to set codec master clock to %lu: %d \n",
++ data->sysclk, ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_hifi_hw_params_mst_mode(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_card *card = codec_dai->codec->card;
++ struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
++ u32 dai_format;
++ unsigned int channels;
++ unsigned int tx_mask, rx_mask;
++ unsigned int sampling_rate;
++ int ret;
++
++
++ sampling_rate = params_rate(params);
++ channels = params_channels(params);
++ pr_debug("%s:%s sampling rate = %u channels = %u \n", __FUNCTION__,
++ (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? "Playback" : "Capture"),
++ sampling_rate, channels);
++
++ /* set cpu DAI configuration */
++ dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ ret = snd_soc_dai_set_fmt(cpu_dai, dai_format);
++ if (ret < 0)
++ return ret;
++
++ /* set i.MX active slot mask */
++ /* S[TR]CCR:DC */
++ tx_mask = ~((1 << channels) - 1);
++ rx_mask = tx_mask;
++ snd_soc_dai_set_tdm_slot(cpu_dai, tx_mask, rx_mask, 2, 32);
++
++ /* set codec DAI configuration */
++ dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
++ if (ret < 0)
++ return ret;
++
++ ret = snd_soc_dai_set_sysclk(codec_dai,
++ WM8731_SYSCLK_MCLK,
++ data->sysclk,
++ SND_SOC_CLOCK_IN);
++
++ if (ret < 0) {
++ pr_err("Failed to set codec master clock to %lu: %d \n",
++ data->sysclk, ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static void imx_hifi_shutdown(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct snd_soc_card *card = codec_dai->codec->card;
++ struct imx_wm8731_data *data = snd_soc_card_get_drvdata(card);
++
++ if (!codec_dai->active)
++ data->clock_enable(0,data);
++
++ return;
++}
++
++static int imx_wm8731_init(struct snd_soc_pcm_runtime *rtd)
++{
++ int ret = 0;
++ struct snd_soc_codec *codec = rtd->codec;
++
++ /* Add imx specific widgets */
++ ret = snd_soc_dapm_new_controls(&codec->dapm, imx_dapm_widgets,
++ ARRAY_SIZE(imx_dapm_widgets));
++ if (ret)
++ goto out_retcode;
++
++ /* Set up imx specific audio path audio_map */
++ ret = snd_soc_dapm_add_routes(&codec->dapm, audio_map, ARRAY_SIZE(audio_map));
++ if (ret)
++ goto out_retcode;
++
++ ret = snd_soc_dapm_enable_pin(&codec->dapm, "Headphone Jack");
++ if (ret)
++ goto out_retcode;
++
++ ret = snd_soc_dapm_nc_pin(&codec->dapm, "Ext Spk");
++ if (ret)
++ goto out_retcode;
++
++out_retcode:
++
++ if (ret)
++ pr_err("%s: failed with error code: %d \n", __FUNCTION__, ret);
++ else
++ pr_info("%s: success \n", __FUNCTION__);
++
++ return ret;
++}
++
++/**
++ * Configure AUDMUX interconnection between
++ * _slave (CPU side) and _master (codec size)
++ *
++ * When SSI operates in master mode, 5-wire interconnect with
++ * audio codec is required:
++ * TXC - BCLK
++ * TXD - DAC data
++ * RXD - ADC data
++ * TXFS - {DAC|ADC}LRC, i.e. word clock
++ * RXC - MCLK, i.e. oversampling clock
++ * Audmux is operated in asynchronous mode to enable 6-wire
++ * interface (as opposed to 4-wire interface in sync mode).
++ */
++static int imx_audmux_config_slv_mode(int _slave, int _master)
++{
++ unsigned int ptcr, pdcr;
++ int slave = _slave - 1;
++ int master = _master - 1;
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_TFSDIR |
++ IMX_AUDMUX_V2_PTCR_TFSEL(slave) |
++ IMX_AUDMUX_V2_PTCR_RCLKDIR |
++ IMX_AUDMUX_V2_PTCR_RCSEL(slave | 0x8) |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR |
++ IMX_AUDMUX_V2_PTCR_TCSEL(slave);
++
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave);
++ imx_audmux_v2_configure_port(master, ptcr, pdcr);
++ ptcr = ptcr & ~IMX_AUDMUX_V2_PTCR_SYN;
++ imx_audmux_v2_configure_port(master, ptcr, pdcr);
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN |
++ IMX_AUDMUX_V2_PTCR_RCLKDIR |
++ IMX_AUDMUX_V2_PTCR_RCSEL(master | 0x8) |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR |
++ IMX_AUDMUX_V2_PTCR_TCSEL(master);
++
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master);
++ imx_audmux_v2_configure_port(slave, ptcr, pdcr);
++ ptcr = ptcr & ~IMX_AUDMUX_V2_PTCR_SYN;
++ imx_audmux_v2_configure_port(slave, ptcr, pdcr);
++
++ return 0;
++}
++
++static int imx_audmux_config_mst_mode(int _slave, int _master)
++{
++ unsigned int ptcr, pdcr;
++ int slave = _slave - 1;
++ int master = _master - 1;
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN;
++ ptcr |= IMX_AUDMUX_V2_PTCR_TFSDIR |
++ IMX_AUDMUX_V2_PTCR_TFSEL(master) |
++ IMX_AUDMUX_V2_PTCR_TCLKDIR |
++ IMX_AUDMUX_V2_PTCR_TCSEL(master);
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(master);
++ imx_audmux_v2_configure_port(slave, ptcr, pdcr);
++
++ ptcr = IMX_AUDMUX_V2_PTCR_SYN;
++ pdcr = IMX_AUDMUX_V2_PDCR_RXDSEL(slave);
++ imx_audmux_v2_configure_port(master, ptcr, pdcr);
++
++ return 0;
++}
++
++static int imx_wm8731_probe(struct platform_device *pdev)
++{
++ struct device_node *ssi_np, *codec_np;
++ struct platform_device *ssi_pdev;
++ struct imx_priv *priv = &card_priv;
++ struct i2c_client *codec_dev;
++ struct imx_wm8731_data *data;
++ unsigned int src_port, ext_port;
++ unsigned int ssi_mode;
++ const char *ssi_mode_str;
++
++ int ret;
++
++ priv->pdev = pdev;
++
++ ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
++ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
++ if (!ssi_np || !codec_np) {
++ dev_err(&pdev->dev, "phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ ssi_pdev = of_find_device_by_node(ssi_np);
++ if (!ssi_pdev) {
++ dev_err(&pdev->dev, "failed to find SSI platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ codec_dev = of_find_i2c_device_by_node(codec_np);
++ if (!codec_dev) {
++ dev_err(&pdev->dev, "failed to find codec platform device\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
++ if (!data) {
++ ret = -ENOMEM;
++ goto fail;
++ }
++
++ card_priv.data = data;
++
++ data->codec_dev = codec_dev;
++
++ data->dai.name = "HiFi";
++ data->dai.stream_name = "HiFi";
++ data->dai.codec_dai_name = "wm8731-hifi";
++ data->dai.codec_of_node = codec_np;
++ data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
++ data->dai.platform_of_node = ssi_np;
++ data->dai.ops = &imx_hifi_ops;
++ data->dai.init = &imx_wm8731_init;
++
++ ret = of_property_read_u32(pdev->dev.of_node, "src-port", &src_port);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get \"src-port\" value\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ ret = of_property_read_u32(pdev->dev.of_node, "ext-port", &ext_port);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get \"ext-port\" value\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ ret = of_property_read_string(ssi_np, "fsl,mode", &ssi_mode_str);
++ if (ret) {
++ dev_err(&pdev->dev, "failed to get \"fsl,mode\" value\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ ssi_mode = strcmp(ssi_mode_str, "i2s-master");
++
++ if (ssi_mode) {
++ /* Master Mode */
++ imx_audmux_config_mst_mode(src_port, ext_port);
++ wm8731_mst_mode_init(data);
++ data->clock_enable = wm8731_mst_mode_clock_enable;
++ imx_hifi_ops.hw_params = imx_hifi_hw_params_mst_mode;
++ imx_hifi_ops.startup = imx_hifi_startup_mst_mode;
++ } else {
++ /* Slave Mode */
++ imx_audmux_config_slv_mode(src_port, ext_port);
++ wm8731_slv_mode_init(data);
++ data->clock_enable = wm8731_slv_mode_clock_enable;
++ imx_hifi_ops.hw_params = imx_hifi_hw_params_slv_mode;
++ imx_hifi_ops.startup = imx_hifi_startup_slv_mode;
++ }
++
++ data->card.dev = &pdev->dev;
++ ret = snd_soc_of_parse_card_name(&data->card, "model");
++ if (ret)
++ goto fail;
++
++ ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
++ if (ret)
++ goto fail;
++
++ data->card.num_links = 1;
++ data->card.dai_link = &data->dai;
++
++ data->card.dapm_widgets = imx_dapm_widgets;
++ data->card.num_dapm_widgets = ARRAY_SIZE(imx_dapm_widgets);
++
++ platform_set_drvdata(pdev, &data->card);
++ snd_soc_card_set_drvdata(&data->card, data);
++
++ ret = snd_soc_register_card(&data->card);
++ if (ret) {
++ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
++ goto fail;
++ }
++
++ return 0;
++
++fail:
++
++ if (ssi_np)
++ of_node_put(ssi_np);
++
++ if (codec_np)
++ of_node_put(codec_np);
++
++ return ret;
++}
++
++static int imx_wm8731_remove(struct platform_device *pdev)
++{
++ struct snd_soc_card *card = platform_get_drvdata(pdev);
++ snd_soc_unregister_card(card);
++
++ return 0;
++}
++
++static const struct of_device_id imx_wm8731_dt_ids[] = {
++ { .compatible = "fsl,imx-audio-wm8731", },
++ { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, imx_wm8731_dt_ids);
++
++static struct platform_driver imx_wm8731_driver = {
++ .driver = {
++ .name = "imx-wm8731",
++ .owner = THIS_MODULE,
++ .of_match_table = imx_wm8731_dt_ids,
++ },
++ .probe = imx_wm8731_probe,
++ .remove = imx_wm8731_remove,
++};
++module_platform_driver(imx_wm8731_driver);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("Freescale i.MX WM8731 ASoC machine driver");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS("platform:imx-wm8731");
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/imx-wm8962.c linux-3.14.72/sound/soc/fsl/imx-wm8962.c
+--- linux-3.14.72.orig/sound/soc/fsl/imx-wm8962.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/imx-wm8962.c 2016-06-19 22:11:55.533125046 +0200
+@@ -1,9 +1,9 @@
+ /*
+- * Copyright 2013 Freescale Semiconductor, Inc.
++ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
+ *
+ * Based on imx-sgtl5000.c
+- * Copyright 2012 Freescale Semiconductor, Inc.
+- * Copyright 2012 Linaro Ltd.
++ * Copyright (C) 2012 Freescale Semiconductor, Inc.
++ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+@@ -16,9 +16,13 @@
+ #include <linux/module.h>
+ #include <linux/of_platform.h>
+ #include <linux/i2c.h>
++#include <linux/of_gpio.h>
+ #include <linux/slab.h>
++#include <linux/gpio.h>
+ #include <linux/clk.h>
+ #include <sound/soc.h>
++#include <sound/jack.h>
++#include <sound/control.h>
+ #include <sound/pcm_params.h>
+ #include <sound/soc-dapm.h>
+ #include <linux/pinctrl/consumer.h>
+@@ -33,15 +37,143 @@
+ struct snd_soc_card card;
+ char codec_dai_name[DAI_NAME_SIZE];
+ char platform_name[DAI_NAME_SIZE];
+- struct clk *codec_clk;
+ unsigned int clk_frequency;
+ };
+
+ struct imx_priv {
++ int hp_gpio;
++ int hp_active_low;
++ int mic_gpio;
++ int mic_active_low;
++ bool amic_mono;
++ bool dmic_mono;
++ struct snd_soc_codec *codec;
+ struct platform_device *pdev;
++ struct snd_pcm_substream *first_stream;
++ struct snd_pcm_substream *second_stream;
++ struct snd_kcontrol *headphone_kctl;
++ struct snd_card *snd_card;
+ };
+ static struct imx_priv card_priv;
+
++#ifdef CONFIG_SND_SOC_IMX_WM8962_ANDROID
++static int sample_rate = 44100;
++static snd_pcm_format_t sample_format = SNDRV_PCM_FORMAT_S16_LE;
++#endif
++
++static struct snd_soc_jack imx_hp_jack;
++static struct snd_soc_jack_pin imx_hp_jack_pins[] = {
++ {
++ .pin = "Headphone Jack",
++ .mask = SND_JACK_HEADPHONE,
++ },
++};
++static struct snd_soc_jack_gpio imx_hp_jack_gpio = {
++ .name = "headphone detect",
++ .report = SND_JACK_HEADPHONE,
++ .debounce_time = 250,
++ .invert = 0,
++};
++
++static struct snd_soc_jack imx_mic_jack;
++static struct snd_soc_jack_pin imx_mic_jack_pins[] = {
++ {
++ .pin = "AMIC",
++ .mask = SND_JACK_MICROPHONE,
++ },
++};
++static struct snd_soc_jack_gpio imx_mic_jack_gpio = {
++ .name = "microphone detect",
++ .report = SND_JACK_MICROPHONE,
++ .debounce_time = 250,
++ .invert = 0,
++};
++
++static int hpjack_status_check(void)
++{
++ struct imx_priv *priv = &card_priv;
++ struct platform_device *pdev = priv->pdev;
++ char *envp[3], *buf;
++ int hp_status, ret;
++
++ if (!gpio_is_valid(priv->hp_gpio))
++ return 0;
++
++ hp_status = gpio_get_value(priv->hp_gpio) ? 1 : 0;
++
++ buf = kmalloc(32, GFP_ATOMIC);
++ if (!buf) {
++ dev_err(&pdev->dev, "%s kmalloc failed\n", __func__);
++ return -ENOMEM;
++ }
++
++ if (hp_status != priv->hp_active_low) {
++ snprintf(buf, 32, "STATE=%d", 2);
++ snd_soc_dapm_disable_pin(&priv->codec->dapm, "Ext Spk");
++ ret = imx_hp_jack_gpio.report;
++ snd_kctl_jack_report(priv->snd_card, priv->headphone_kctl, 1);
++ } else {
++ snprintf(buf, 32, "STATE=%d", 0);
++ snd_soc_dapm_enable_pin(&priv->codec->dapm, "Ext Spk");
++ ret = 0;
++ snd_kctl_jack_report(priv->snd_card, priv->headphone_kctl, 0);
++ }
++
++ envp[0] = "NAME=headphone";
++ envp[1] = buf;
++ envp[2] = NULL;
++ kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, envp);
++ kfree(buf);
++
++ return ret;
++}
++
++static int micjack_status_check(void)
++{
++ struct imx_priv *priv = &card_priv;
++ struct platform_device *pdev = priv->pdev;
++ char *envp[3], *buf;
++ int mic_status, ret;
++
++ if (!gpio_is_valid(priv->mic_gpio))
++ return 0;
++
++ mic_status = gpio_get_value(priv->mic_gpio) ? 1 : 0;
++
++ if ((mic_status != priv->mic_active_low && priv->amic_mono)
++ || (mic_status == priv->mic_active_low && priv->dmic_mono))
++ snd_soc_update_bits(priv->codec, WM8962_THREED1,
++ WM8962_ADC_MONOMIX_MASK, WM8962_ADC_MONOMIX);
++ else
++ snd_soc_update_bits(priv->codec, WM8962_THREED1,
++ WM8962_ADC_MONOMIX_MASK, 0);
++
++ buf = kmalloc(32, GFP_ATOMIC);
++ if (!buf) {
++ dev_err(&pdev->dev, "%s kmalloc failed\n", __func__);
++ return -ENOMEM;
++ }
++
++ if (mic_status != priv->mic_active_low) {
++ snprintf(buf, 32, "STATE=%d", 2);
++ snd_soc_dapm_disable_pin(&priv->codec->dapm, "DMIC");
++ ret = imx_mic_jack_gpio.report;
++ } else {
++ snprintf(buf, 32, "STATE=%d", 0);
++ snd_soc_dapm_enable_pin(&priv->codec->dapm, "DMIC");
++ ret = 0;
++ }
++
++ envp[0] = "NAME=microphone";
++ envp[1] = buf;
++ envp[2] = NULL;
++ kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, envp);
++ kfree(buf);
++
++ return ret;
++}
++
++
+ static const struct snd_soc_dapm_widget imx_wm8962_dapm_widgets[] = {
+ SND_SOC_DAPM_HP("Headphone Jack", NULL),
+ SND_SOC_DAPM_SPK("Ext Spk", NULL),
+@@ -49,15 +181,30 @@
+ SND_SOC_DAPM_MIC("DMIC", NULL),
+ };
+
+-static int sample_rate = 44100;
+-static snd_pcm_format_t sample_format = SNDRV_PCM_FORMAT_S16_LE;
+-
++#ifdef CONFIG_SND_SOC_IMX_WM8962_ANDROID
+ static int imx_hifi_hw_params(struct snd_pcm_substream *substream,
+- struct snd_pcm_hw_params *params)
++ struct snd_pcm_hw_params *params)
+ {
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct imx_priv *priv = &card_priv;
++ struct device *dev = &priv->pdev->dev;
++ u32 dai_format;
++ int ret = 0;
++
+ sample_rate = params_rate(params);
+ sample_format = params_format(params);
+
++ dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ /* set codec DAI configuration */
++ ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
++ if (ret) {
++ dev_err(dev, "failed to set codec dai fmt: %d\n", ret);
++ return ret;
++ }
++
+ return 0;
+ }
+
+@@ -133,6 +280,200 @@
+ return 0;
+ }
+
++#else
++
++static int imx_hifi_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct imx_priv *priv = &card_priv;
++ struct device *dev = &priv->pdev->dev;
++ struct snd_soc_card *card = platform_get_drvdata(priv->pdev);
++ struct imx_wm8962_data *data = snd_soc_card_get_drvdata(card);
++ unsigned int sample_rate = params_rate(params);
++ snd_pcm_format_t sample_format = params_format(params);
++ u32 dai_format, pll_out;
++ int ret = 0;
++
++ if (!priv->first_stream) {
++ priv->first_stream = substream;
++ } else {
++ priv->second_stream = substream;
++
++ /* We suppose the two substream are using same params */
++ return 0;
++ }
++
++ dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
++ SND_SOC_DAIFMT_CBM_CFM;
++
++ /* set codec DAI configuration */
++ ret = snd_soc_dai_set_fmt(codec_dai, dai_format);
++ if (ret) {
++ dev_err(dev, "failed to set codec dai fmt: %d\n", ret);
++ return ret;
++ }
++
++ if (sample_format == SNDRV_PCM_FORMAT_S24_LE)
++ pll_out = sample_rate * 384;
++ else
++ pll_out = sample_rate * 256;
++
++ ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL, WM8962_FLL_MCLK,
++ data->clk_frequency, pll_out);
++ if (ret) {
++ dev_err(dev, "failed to start FLL: %d\n", ret);
++ return ret;
++ }
++
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_FLL,
++ pll_out, SND_SOC_CLOCK_IN);
++ if (ret) {
++ dev_err(dev, "failed to set SYSCLK: %d\n", ret);
++ return ret;
++ }
++
++ return 0;
++}
++
++static int imx_hifi_hw_free(struct snd_pcm_substream *substream)
++{
++ struct snd_soc_pcm_runtime *rtd = substream->private_data;
++ struct snd_soc_dai *codec_dai = rtd->codec_dai;
++ struct imx_priv *priv = &card_priv;
++ struct device *dev = &priv->pdev->dev;
++ int ret;
++
++ /* We don't need to handle anything if there's no substream running */
++ if (!priv->first_stream)
++ return 0;
++
++ if (priv->first_stream == substream)
++ priv->first_stream = priv->second_stream;
++ priv->second_stream = NULL;
++
++ if (!priv->first_stream) {
++ /*
++ * Continuously setting FLL would cause playback distortion.
++ * We can fix it just by mute codec after playback.
++ */
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ snd_soc_dai_digital_mute(codec_dai, 1, substream->stream);
++
++ /*
++ * WM8962 doesn't allow us to continuously setting FLL,
++ * So we set MCLK as sysclk once, which'd remove the limitation.
++ */
++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
++ 0, SND_SOC_CLOCK_IN);
++ if (ret < 0) {
++ dev_err(dev, "failed to switch away from FLL: %d\n", ret);
++ return ret;
++ }
++
++ /* Disable FLL and let codec do pm_runtime_put() */
++ ret = snd_soc_dai_set_pll(codec_dai, WM8962_FLL,
++ WM8962_FLL_MCLK, 0, 0);
++ if (ret < 0) {
++ dev_err(dev, "failed to stop FLL: %d\n", ret);
++ return ret;
++ }
++ }
++
++ return 0;
++}
++
++static struct snd_soc_ops imx_hifi_ops = {
++ .hw_params = imx_hifi_hw_params,
++ .hw_free = imx_hifi_hw_free,
++};
++#endif /* CONFIG_SND_SOC_IMX_WM8962_ANDROID */
++
++static int imx_wm8962_gpio_init(struct snd_soc_card *card)
++{
++ struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
++ struct snd_soc_codec *codec = codec_dai->codec;
++ struct imx_priv *priv = &card_priv;
++
++ priv->codec = codec;
++
++ if (gpio_is_valid(priv->hp_gpio)) {
++ imx_hp_jack_gpio.gpio = priv->hp_gpio;
++ imx_hp_jack_gpio.jack_status_check = hpjack_status_check;
++
++ snd_soc_jack_new(codec, "Headphone Jack", SND_JACK_HEADPHONE, &imx_hp_jack);
++ snd_soc_jack_add_pins(&imx_hp_jack,
++ ARRAY_SIZE(imx_hp_jack_pins), imx_hp_jack_pins);
++ snd_soc_jack_add_gpios(&imx_hp_jack, 1, &imx_hp_jack_gpio);
++ }
++
++ if (gpio_is_valid(priv->mic_gpio)) {
++ imx_mic_jack_gpio.gpio = priv->mic_gpio;
++ imx_mic_jack_gpio.jack_status_check = micjack_status_check;
++
++ snd_soc_jack_new(codec, "AMIC", SND_JACK_MICROPHONE, &imx_mic_jack);
++ snd_soc_jack_add_pins(&imx_mic_jack,
++ ARRAY_SIZE(imx_mic_jack_pins), imx_mic_jack_pins);
++ snd_soc_jack_add_gpios(&imx_mic_jack, 1, &imx_mic_jack_gpio);
++ } else if (priv->amic_mono || priv->dmic_mono) {
++ /*
++ * Permanent set monomix bit if only one microphone
++ * is present on the board while it needs monomix.
++ */
++ snd_soc_update_bits(priv->codec, WM8962_THREED1,
++ WM8962_ADC_MONOMIX_MASK, WM8962_ADC_MONOMIX);
++ }
++
++ return 0;
++}
++
++static ssize_t show_headphone(struct device_driver *dev, char *buf)
++{
++ struct imx_priv *priv = &card_priv;
++ int hp_status;
++
++ if (!gpio_is_valid(priv->hp_gpio)) {
++ strcpy(buf, "no detect gpio connected\n");
++ return strlen(buf);
++ }
++
++ /* Check if headphone is plugged in */
++ hp_status = gpio_get_value(priv->hp_gpio) ? 1 : 0;
++
++ if (hp_status != priv->hp_active_low)
++ strcpy(buf, "headphone\n");
++ else
++ strcpy(buf, "speaker\n");
++
++ return strlen(buf);
++}
++
++static DRIVER_ATTR(headphone, S_IRUGO | S_IWUSR, show_headphone, NULL);
++
++static ssize_t show_mic(struct device_driver *dev, char *buf)
++{
++ struct imx_priv *priv = &card_priv;
++ int mic_status;
++
++ if (!gpio_is_valid(priv->mic_gpio)) {
++ strcpy(buf, "no detect gpio connected\n");
++ return strlen(buf);
++ }
++
++ /* Check if analog microphone is plugged in */
++ mic_status = gpio_get_value(priv->mic_gpio) ? 1 : 0;
++
++ if (mic_status != priv->mic_active_low)
++ strcpy(buf, "amic\n");
++ else
++ strcpy(buf, "dmic\n");
++
++ return strlen(buf);
++}
++
++static DRIVER_ATTR(microphone, S_IRUGO | S_IWUSR, show_mic, NULL);
++
+ static int imx_wm8962_late_probe(struct snd_soc_card *card)
+ {
+ struct snd_soc_dai *codec_dai = card->rtd[0].codec_dai;
+@@ -152,16 +493,27 @@
+ static int imx_wm8962_probe(struct platform_device *pdev)
+ {
+ struct device_node *np = pdev->dev.of_node;
+- struct device_node *ssi_np, *codec_np;
+- struct platform_device *ssi_pdev;
++ struct device_node *cpu_np, *codec_np;
++ struct platform_device *cpu_pdev;
+ struct imx_priv *priv = &card_priv;
+ struct i2c_client *codec_dev;
+ struct imx_wm8962_data *data;
++ struct clk *codec_clk = NULL;
+ int int_port, ext_port;
+ int ret;
+
+ priv->pdev = pdev;
+
++ cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0);
++ if (!cpu_np) {
++ dev_err(&pdev->dev, "cpu dai phandle missing or invalid\n");
++ ret = -EINVAL;
++ goto fail;
++ }
++
++ if (!strstr(cpu_np->name, "ssi"))
++ goto audmux_bypass;
++
+ ret = of_property_read_u32(np, "mux-int-port", &int_port);
+ if (ret) {
+ dev_err(&pdev->dev, "mux-int-port missing or invalid\n");
+@@ -198,16 +550,16 @@
+ return ret;
+ }
+
+- ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
++audmux_bypass:
+ codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
+- if (!ssi_np || !codec_np) {
++ if (!codec_np) {
+ dev_err(&pdev->dev, "phandle missing or invalid\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+
+- ssi_pdev = of_find_device_by_node(ssi_np);
+- if (!ssi_pdev) {
++ cpu_pdev = of_find_device_by_node(cpu_np);
++ if (!cpu_pdev) {
+ dev_err(&pdev->dev, "failed to find SSI platform device\n");
+ ret = -EINVAL;
+ goto fail;
+@@ -219,32 +571,38 @@
+ goto fail;
+ }
+
++ priv->first_stream = NULL;
++ priv->second_stream = NULL;
++
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+- data->codec_clk = devm_clk_get(&codec_dev->dev, NULL);
+- if (IS_ERR(data->codec_clk)) {
+- ret = PTR_ERR(data->codec_clk);
++ codec_clk = devm_clk_get(&codec_dev->dev, NULL);
++ if (IS_ERR(codec_clk)) {
++ ret = PTR_ERR(codec_clk);
+ dev_err(&codec_dev->dev, "failed to get codec clk: %d\n", ret);
+ goto fail;
+ }
+
+- data->clk_frequency = clk_get_rate(data->codec_clk);
+- ret = clk_prepare_enable(data->codec_clk);
+- if (ret) {
+- dev_err(&codec_dev->dev, "failed to enable codec clk: %d\n", ret);
+- goto fail;
+- }
++ data->clk_frequency = clk_get_rate(codec_clk);
++
++ priv->amic_mono = of_property_read_bool(codec_np, "amic-mono");
++ priv->dmic_mono = of_property_read_bool(codec_np, "dmic-mono");
++
++ priv->hp_gpio = of_get_named_gpio_flags(np, "hp-det-gpios", 0,
++ (enum of_gpio_flags *)&priv->hp_active_low);
++ priv->mic_gpio = of_get_named_gpio_flags(np, "mic-det-gpios", 0,
++ (enum of_gpio_flags *)&priv->mic_active_low);
+
+ data->dai.name = "HiFi";
+ data->dai.stream_name = "HiFi";
+ data->dai.codec_dai_name = "wm8962";
+ data->dai.codec_of_node = codec_np;
+- data->dai.cpu_dai_name = dev_name(&ssi_pdev->dev);
+- data->dai.platform_of_node = ssi_np;
++ data->dai.cpu_dai_name = dev_name(&cpu_pdev->dev);
++ data->dai.platform_of_node = cpu_np;
+ data->dai.ops = &imx_hifi_ops;
+ data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM;
+@@ -252,37 +610,61 @@
+ data->card.dev = &pdev->dev;
+ ret = snd_soc_of_parse_card_name(&data->card, "model");
+ if (ret)
+- goto clk_fail;
++ goto fail;
+ ret = snd_soc_of_parse_audio_routing(&data->card, "audio-routing");
+ if (ret)
+- goto clk_fail;
++ goto fail;
+ data->card.num_links = 1;
+ data->card.dai_link = &data->dai;
+ data->card.dapm_widgets = imx_wm8962_dapm_widgets;
+ data->card.num_dapm_widgets = ARRAY_SIZE(imx_wm8962_dapm_widgets);
+
+ data->card.late_probe = imx_wm8962_late_probe;
+- data->card.set_bias_level = imx_wm8962_set_bias_level;
+
++#ifdef CONFIG_SND_SOC_IMX_WM8962_ANDROID
++ data->card.set_bias_level = imx_wm8962_set_bias_level;
++#endif
+ platform_set_drvdata(pdev, &data->card);
+ snd_soc_card_set_drvdata(&data->card, data);
+
+ ret = devm_snd_soc_register_card(&pdev->dev, &data->card);
+ if (ret) {
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
+- goto clk_fail;
++ goto fail;
+ }
+
+- of_node_put(ssi_np);
+- of_node_put(codec_np);
++ priv->snd_card = data->card.snd_card;
++ priv->headphone_kctl = snd_kctl_jack_new("Headphone", 0, NULL);
++ ret = snd_ctl_add(data->card.snd_card, priv->headphone_kctl);
++ if (ret)
++ goto fail;
+
+- return 0;
++ imx_wm8962_gpio_init(&data->card);
+
+-clk_fail:
+- clk_disable_unprepare(data->codec_clk);
++ if (gpio_is_valid(priv->hp_gpio)) {
++ ret = driver_create_file(pdev->dev.driver, &driver_attr_headphone);
++ if (ret) {
++ dev_err(&pdev->dev, "create hp attr failed (%d)\n", ret);
++ goto fail_hp;
++ }
++ }
++
++ if (gpio_is_valid(priv->mic_gpio)) {
++ ret = driver_create_file(pdev->dev.driver, &driver_attr_microphone);
++ if (ret) {
++ dev_err(&pdev->dev, "create mic attr failed (%d)\n", ret);
++ goto fail_mic;
++ }
++ }
++
++ goto fail;
++
++fail_mic:
++ driver_remove_file(pdev->dev.driver, &driver_attr_headphone);
++fail_hp:
+ fail:
+- if (ssi_np)
+- of_node_put(ssi_np);
++ if (cpu_np)
++ of_node_put(cpu_np);
+ if (codec_np)
+ of_node_put(codec_np);
+
+@@ -291,11 +673,8 @@
+
+ static int imx_wm8962_remove(struct platform_device *pdev)
+ {
+- struct snd_soc_card *card = platform_get_drvdata(pdev);
+- struct imx_wm8962_data *data = snd_soc_card_get_drvdata(card);
+-
+- if (!IS_ERR(data->codec_clk))
+- clk_disable_unprepare(data->codec_clk);
++ driver_remove_file(pdev->dev.driver, &driver_attr_microphone);
++ driver_remove_file(pdev->dev.driver, &driver_attr_headphone);
+
+ return 0;
+ }
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/Kconfig linux-3.14.72/sound/soc/fsl/Kconfig
+--- linux-3.14.72.orig/sound/soc/fsl/Kconfig 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/Kconfig 2016-06-19 22:11:55.533125046 +0200
+@@ -1,26 +1,92 @@
++menu "SoC Audio for Freescale CPUs"
++
++comment "Common SoC Audio options for Freescale CPUs:"
++
++config SND_SOC_FSL_ASRC
++ tristate "Asynchronous Sample Rate Converter (ASRC) module support"
++ select REGMAP_MMIO
++ select SND_SOC_GENERIC_DMAENGINE_PCM
++ help
++ Say Y if you want to add Asynchronous Sample Rate Converter (ASRC)
++ support for the Freescale CPUs.
++ This option is only useful for out-of-tree drivers since
++ in-tree drivers select it automatically.
++
+ config SND_SOC_FSL_SAI
+- tristate
++ tristate "Synchronous Audio Interface (SAI) module support"
++ select REGMAP_MMIO
++ select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
+ select SND_SOC_GENERIC_DMAENGINE_PCM
++ help
++ Say Y if you want to add Synchronous Audio Interface (SAI)
++ support for the Freescale CPUs.
++ This option is only useful for out-of-tree drivers since
++ in-tree drivers select it automatically.
+
+ config SND_SOC_FSL_SSI
+- tristate
++ tristate "Synchronous Serial Interface module support"
++ select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
++ select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC != n && (MXC_TZIC || MXC_AVIC)
++ select REGMAP_MMIO
++ help
++ Say Y if you want to add Synchronous Serial Interface (SSI)
++ support for the Freescale CPUs.
++ This option is only useful for out-of-tree drivers since
++ in-tree drivers select it automatically.
+
+ config SND_SOC_FSL_SPDIF
+- tristate
++ tristate "Sony/Philips Digital Interface module support"
++ select REGMAP_MMIO
++ select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
++ select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC != n && (MXC_TZIC || MXC_AVIC)
++ help
++ Say Y if you want to add Sony/Philips Digital Interface (SPDIF)
++ support for the Freescale CPUs.
++ This option is only useful for out-of-tree drivers since
++ in-tree drivers select it automatically.
+
+ config SND_SOC_FSL_ESAI
+- tristate
++ tristate "Enhanced Serial Audio Interface (ESAI) module support"
++ select REGMAP_MMIO
++ select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
++ help
++ Say Y if you want to add Enhanced Synchronous Audio Interface
++ (ESAI) support for the Freescale CPUs.
++ This option is only useful for out-of-tree drivers since
++ in-tree drivers select it automatically.
+
+ config SND_SOC_FSL_UTILS
+ tristate
+
+-menuconfig SND_POWERPC_SOC
++config SND_SOC_FSL_HDMI
++ tristate
++
++config SND_SOC_IMX_PCM_DMA
++ tristate
++ select SND_SOC_GENERIC_DMAENGINE_PCM
++
++config SND_SOC_IMX_AUDMUX
++ tristate "Digital Audio Mux module support"
++ help
++ Say Y if you want to add Digital Audio Mux (AUDMUX) support
++ for the ARM i.MX CPUs.
++ This option is only useful for out-of-tree drivers since
++ in-tree drivers select it automatically.
++
++config SND_POWERPC_SOC
+ tristate "SoC Audio for Freescale PowerPC CPUs"
+ depends on FSL_SOC || PPC_MPC52xx
+ help
+ Say Y or M if you want to add support for codecs attached to
+ the PowerPC CPUs.
+
++config SND_IMX_SOC
++ tristate "SoC Audio for Freescale i.MX CPUs"
++ depends on ARCH_MXC || COMPILE_TEST
++ help
++ Say Y or M if you want to add support for codecs attached to
++ the i.MX CPUs.
++
+ if SND_POWERPC_SOC
+
+ config SND_MPC52xx_DMA
+@@ -29,6 +95,8 @@
+ config SND_SOC_POWERPC_DMA
+ tristate
+
++comment "SoC Audio support for Freescale PPC boards:"
++
+ config SND_SOC_MPC8610_HPCD
+ tristate "ALSA SoC support for the Freescale MPC8610 HPCD board"
+ # I2C is necessary for the CS4270 driver
+@@ -106,13 +174,6 @@
+
+ endif # SND_POWERPC_SOC
+
+-menuconfig SND_IMX_SOC
+- tristate "SoC Audio for Freescale i.MX CPUs"
+- depends on ARCH_MXC || COMPILE_TEST
+- help
+- Say Y or M if you want to add support for codecs attached to
+- the i.MX CPUs.
+-
+ if SND_IMX_SOC
+
+ config SND_SOC_IMX_SSI
+@@ -122,12 +183,12 @@
+ tristate
+ select FIQ
+
+-config SND_SOC_IMX_PCM_DMA
+- tristate
++config SND_SOC_IMX_HDMI_DMA
++ bool
+ select SND_SOC_GENERIC_DMAENGINE_PCM
++ select SND_SOC_IMX_PCM_DMA
+
+-config SND_SOC_IMX_AUDMUX
+- tristate
++comment "SoC Audio support for Freescale i.MX boards:"
+
+ config SND_MXC_SOC_WM1133_EV1
+ tristate "Audio on the i.MX31ADS with WM1133-EV1 fitted"
+@@ -178,33 +239,87 @@
+ Enable I2S based access to the TLV320AIC23B codec attached
+ to the SSI interface
+
++config SND_SOC_IMX_CS42888
++ tristate "SoC Audio support for i.MX boards with cs42888"
++ depends on OF && I2C
++ select SND_SOC_CS42XX8_I2C
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_FSL_ESAI
++ select SND_SOC_FSL_ASRC
++ select SND_SOC_FSL_UTILS
++ help
++ SoC Audio support for i.MX boards with cs42888
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a cs42888 codec.
++
++config SND_SOC_IMX_WM8731
++ tristate "SoC Audio support for i.MX boards with wm8731"
++ depends on OF && I2C
++ select SND_SOC_WM8731
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SSI
++ select SND_SOC_FSL_UTILS
++ help
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a wm8731 codec.
++
+ config SND_SOC_IMX_WM8962
+ tristate "SoC Audio support for i.MX boards with wm8962"
+ depends on OF && I2C
+ select SND_SOC_WM8962
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SAI
+ select SND_SOC_FSL_SSI
++ select SND_KCTL_JACK
+ help
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a wm8962 codec.
+
++config SND_SOC_IMX_WM8962_ANDROID
++ tristate "SoC Audio support for i.MX boards with wm8962 in android"
++ depends on SND_SOC_IMX_WM8962=y
++ help
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a wm8962 codec in android.
++
+ config SND_SOC_IMX_SGTL5000
+ tristate "SoC Audio support for i.MX boards with sgtl5000"
+ depends on OF && I2C
+ select SND_SOC_SGTL5000
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SAI
+ select SND_SOC_FSL_SSI
+ help
+ Say Y if you want to add support for SoC audio on an i.MX board with
+ a sgtl5000 codec.
++
++config SND_SOC_IMX_AC97_VT1613
++ tristate "SoC Audio support for i.MX boards with VT1613 AC'97"
++ depends on OF
++ select SND_SOC_AC97_BUS
++ select SND_SOC_VT1613
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SSI
++ help
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a VT1613 codec in AC97 mode.
++
++config SND_SOC_IMX_MQS
++ tristate "SoC Audio support for i.MX boards with MQS"
++ depends on OF
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_FSL_SAI
++ select SND_SOC_FSL_MQS
++ select SND_SOC_FSL_UTILS
+
+ config SND_SOC_IMX_SPDIF
+ tristate "SoC Audio support for i.MX boards with S/PDIF"
+ select SND_SOC_IMX_PCM_DMA
+ select SND_SOC_FSL_SPDIF
+- select REGMAP_MMIO
+ help
+ SoC Audio support for i.MX boards with S/PDIF
+ Say Y if you want to add support for SoC audio on an i.MX board with
+@@ -218,4 +333,42 @@
+ select SND_SOC_MC13783
+ select SND_SOC_IMX_PCM_DMA
+
++config SND_SOC_IMX_HDMI
++ tristate "SoC Audio support for i.MX boards with HDMI port"
++ depends on MFD_MXC_HDMI
++ select SND_SOC_IMX_HDMI_DMA
++ select SND_SOC_FSL_HDMI
++ select SND_SOC_HDMI_CODEC
++ help
++ SoC Audio support for i.MX boards with HDMI audio
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ IMX HDMI.
++
++config SND_SOC_IMX_SI476X
++ tristate "SoC Audio support for i.MX boards with si476x"
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SSI
++ select SND_SOC_FSL_UTILS
++ select SND_SOC_SI476X
++ help
++ SoC Audio support for i.MX boards with SI476x
++ Say Y if you want to add support for Soc audio for the AMFM Tuner chip
++ SI476x module.
++
++config SND_SOC_IMX_TDA1997X
++ tristate "SoC Audio support for i.MX boards with tda1997x"
++ depends on OF && I2C
++ select SND_SOC_TDA1997X
++ select SND_SOC_IMX_PCM_DMA
++ select SND_SOC_IMX_AUDMUX
++ select SND_SOC_FSL_SSI
++ select SND_SOC_FSL_UTILS
++ help
++ SoC Audio support for i.MX boards with TDA1997x
++ Say Y if you want to add support for SoC audio on an i.MX board with
++ a tda1997x codec.
++
+ endif # SND_IMX_SOC
++
++endmenu
+diff -Nur linux-3.14.72.orig/sound/soc/fsl/Makefile linux-3.14.72/sound/soc/fsl/Makefile
+--- linux-3.14.72.orig/sound/soc/fsl/Makefile 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/fsl/Makefile 2016-06-19 22:11:55.533125046 +0200
+@@ -11,17 +11,22 @@
+ obj-$(CONFIG_SND_SOC_P1022_RDK) += snd-soc-p1022-rdk.o
+
+ # Freescale SSI/DMA/SAI/SPDIF Support
++snd-soc-fsl-asrc-objs := fsl_asrc.o fsl_asrc_dma.o
+ snd-soc-fsl-sai-objs := fsl_sai.o
+-snd-soc-fsl-ssi-objs := fsl_ssi.o
++snd-soc-fsl-ssi-y := fsl_ssi.o
++snd-soc-fsl-ssi-$(CONFIG_DEBUG_FS) += fsl_ssi_dbg.o
+ snd-soc-fsl-spdif-objs := fsl_spdif.o
+ snd-soc-fsl-esai-objs := fsl_esai.o
+ snd-soc-fsl-utils-objs := fsl_utils.o
+ snd-soc-fsl-dma-objs := fsl_dma.o
++snd-soc-fsl-hdmi-objs := fsl_hdmi.o
++obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc.o
+ obj-$(CONFIG_SND_SOC_FSL_SAI) += snd-soc-fsl-sai.o
+ obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
+ obj-$(CONFIG_SND_SOC_FSL_SPDIF) += snd-soc-fsl-spdif.o
+ obj-$(CONFIG_SND_SOC_FSL_ESAI) += snd-soc-fsl-esai.o
+ obj-$(CONFIG_SND_SOC_FSL_UTILS) += snd-soc-fsl-utils.o
++obj-$(CONFIG_SND_SOC_FSL_HDMI) += snd-soc-fsl-hdmi.o
+ obj-$(CONFIG_SND_SOC_POWERPC_DMA) += snd-soc-fsl-dma.o
+
+ # MPC5200 Platform Support
+@@ -41,22 +46,39 @@
+
+ obj-$(CONFIG_SND_SOC_IMX_PCM_FIQ) += imx-pcm-fiq.o
+ obj-$(CONFIG_SND_SOC_IMX_PCM_DMA) += imx-pcm-dma.o
++obj-$(CONFIG_SND_SOC_IMX_HDMI_DMA) += imx-hdmi-dma.o hdmi_pcm.o
+
+ # i.MX Machine Support
+ snd-soc-eukrea-tlv320-objs := eukrea-tlv320.o
+ snd-soc-phycore-ac97-objs := phycore-ac97.o
+ snd-soc-mx27vis-aic32x4-objs := mx27vis-aic32x4.o
+ snd-soc-wm1133-ev1-objs := wm1133-ev1.o
++snd-soc-imx-cs42888-objs := imx-cs42888.o
+ snd-soc-imx-sgtl5000-objs := imx-sgtl5000.o
++snd-soc-imx-ac97-vt1613-objs := imx-ac97-vt1613.o
++snd-soc-imx-tda1997x-objs := imx-tda1997x.o
++snd-soc-imx-wm8731-objs := imx-wm8731.o
+ snd-soc-imx-wm8962-objs := imx-wm8962.o
+ snd-soc-imx-spdif-objs := imx-spdif.o
+ snd-soc-imx-mc13783-objs := imx-mc13783.o
++snd-soc-imx-hdmi-objs := imx-hdmi.o
++snd-soc-imx-si476x-objs := imx-si476x.o
++snd-soc-imx-mqs-objs := imx-mqs.o
+
+ obj-$(CONFIG_SND_SOC_EUKREA_TLV320) += snd-soc-eukrea-tlv320.o
+ obj-$(CONFIG_SND_SOC_PHYCORE_AC97) += snd-soc-phycore-ac97.o
+ obj-$(CONFIG_SND_SOC_MX27VIS_AIC32X4) += snd-soc-mx27vis-aic32x4.o
+ obj-$(CONFIG_SND_MXC_SOC_WM1133_EV1) += snd-soc-wm1133-ev1.o
++obj-$(CONFIG_SND_SOC_IMX_CS42888) += snd-soc-imx-cs42888.o
+ obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o
++obj-$(CONFIG_SND_SOC_IMX_AC97_VT1613) += snd-soc-imx-ac97-vt1613.o
++obj-$(CONFIG_SND_SOC_IMX_TDA1997X) += snd-soc-imx-tda1997x.o
+ obj-$(CONFIG_SND_SOC_IMX_WM8962) += snd-soc-imx-wm8962.o
++obj-$(CONFIG_SND_SOC_IMX_WM8731) += snd-soc-imx-wm8731.o
+ obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o
+ obj-$(CONFIG_SND_SOC_IMX_MC13783) += snd-soc-imx-mc13783.o
++obj-$(CONFIG_SND_SOC_IMX_HDMI) += snd-soc-imx-hdmi.o
++obj-$(CONFIG_SND_SOC_IMX_SI476X) += snd-soc-imx-si476x.o
++obj-$(CONFIG_SND_SOC_IMX_MQS) += snd-soc-imx-mqs.o
++
++AFLAGS_hdmi_pcm.o := -march=armv7-a -mtune=cortex-a9 -mfpu=neon -mfloat-abi=softfp
+diff -Nur linux-3.14.72.orig/sound/soc/soc-core.c linux-3.14.72/sound/soc/soc-core.c
+--- linux-3.14.72.orig/sound/soc/soc-core.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/soc-core.c 2016-06-19 22:11:55.533125046 +0200
+@@ -523,7 +523,7 @@
+ static void soc_ac97_device_release(struct device *dev){}
+
+ /* register ac97 codec to bus */
+-static int soc_ac97_dev_register(struct snd_soc_codec *codec)
++int soc_ac97_dev_register(struct snd_soc_codec *codec)
+ {
+ int err;
+
+@@ -541,6 +541,7 @@
+ }
+ return 0;
+ }
++EXPORT_SYMBOL_GPL(soc_ac97_dev_register);
+ #endif
+
+ static void codec2codec_close_delayed_work(struct work_struct *work)
+@@ -2716,6 +2717,48 @@
+ EXPORT_SYMBOL_GPL(snd_soc_put_value_enum_double);
+
+ /**
++ * snd_soc_read_signed - Read a codec register and interprete as signed value
++ * @codec: codec
++ * @reg: Register to read
++ * @mask: Mask to use after shifting the register value
++ * @shift: Right shift of register value
++ * @sign_bit: Bit that describes if a number is negative or not.
++ *
++ * This functions reads a codec register. The register value is shifted right
++ * by 'shift' bits and masked with the given 'mask'. Afterwards it translates
++ * the given registervalue into a signed integer if sign_bit is non-zero.
++ *
++ * Returns the register value as signed int.
++ */
++static int snd_soc_read_signed(struct snd_soc_codec *codec, unsigned int reg,
++ unsigned int mask, unsigned int shift, unsigned int sign_bit)
++{
++ int ret;
++ unsigned int val;
++
++ val = (snd_soc_read(codec, reg) >> shift) & mask;
++
++ if (!sign_bit)
++ return val;
++
++ /* non-negative number */
++ if (!(val & BIT(sign_bit)))
++ return val;
++
++ ret = val;
++
++ /*
++ * The register most probably does not contain a full-sized int.
++ * Instead we have an arbitrary number of bits in a signed
++ * representation which has to be translated into a full-sized int.
++ * This is done by filling up all bits above the sign-bit.
++ */
++ ret |= ~((int)(BIT(sign_bit) - 1));
++
++ return ret;
++}
++
++/**
+ * snd_soc_info_volsw - single mixer info callback
+ * @kcontrol: mixer control
+ * @uinfo: control element information
+@@ -2743,7 +2786,7 @@
+
+ uinfo->count = snd_soc_volsw_is_stereo(mc) ? 2 : 1;
+ uinfo->value.integer.min = 0;
+- uinfo->value.integer.max = platform_max;
++ uinfo->value.integer.max = platform_max - mc->min;
+ return 0;
+ }
+ EXPORT_SYMBOL_GPL(snd_soc_info_volsw);
+@@ -2769,11 +2812,16 @@
+ unsigned int shift = mc->shift;
+ unsigned int rshift = mc->rshift;
+ int max = mc->max;
++ int min = mc->min;
++ int sign_bit = mc->sign_bit;
+ unsigned int mask = (1 << fls(max)) - 1;
+ unsigned int invert = mc->invert;
+
+- ucontrol->value.integer.value[0] =
+- (snd_soc_read(codec, reg) >> shift) & mask;
++ if (sign_bit)
++ mask = BIT(sign_bit + 1) - 1;
++
++ ucontrol->value.integer.value[0] = snd_soc_read_signed(codec, reg, mask,
++ shift, sign_bit) - min;
+ if (invert)
+ ucontrol->value.integer.value[0] =
+ max - ucontrol->value.integer.value[0];
+@@ -2781,10 +2829,12 @@
+ if (snd_soc_volsw_is_stereo(mc)) {
+ if (reg == reg2)
+ ucontrol->value.integer.value[1] =
+- (snd_soc_read(codec, reg) >> rshift) & mask;
++ snd_soc_read_signed(codec, reg, mask, rshift,
++ sign_bit) - min;
+ else
+ ucontrol->value.integer.value[1] =
+- (snd_soc_read(codec, reg2) >> shift) & mask;
++ snd_soc_read_signed(codec, reg2, mask, shift,
++ sign_bit) - min;
+ if (invert)
+ ucontrol->value.integer.value[1] =
+ max - ucontrol->value.integer.value[1];
+@@ -2815,6 +2865,8 @@
+ unsigned int shift = mc->shift;
+ unsigned int rshift = mc->rshift;
+ int max = mc->max;
++ int min = mc->min;
++ unsigned int sign_bit = mc->sign_bit;
+ unsigned int mask = (1 << fls(max)) - 1;
+ unsigned int invert = mc->invert;
+ int err;
+@@ -2822,13 +2874,16 @@
+ unsigned int val2 = 0;
+ unsigned int val, val_mask;
+
+- val = (ucontrol->value.integer.value[0] & mask);
++ if (sign_bit)
++ mask = BIT(sign_bit + 1) - 1;
++
++ val = ((ucontrol->value.integer.value[0] + min) & mask);
+ if (invert)
+ val = max - val;
+ val_mask = mask << shift;
+ val = val << shift;
+ if (snd_soc_volsw_is_stereo(mc)) {
+- val2 = (ucontrol->value.integer.value[1] & mask);
++ val2 = ((ucontrol->value.integer.value[1] + min) & mask);
+ if (invert)
+ val2 = max - val2;
+ if (reg == reg2) {
+diff -Nur linux-3.14.72.orig/sound/soc/soc-devres.c linux-3.14.72/sound/soc/soc-devres.c
+--- linux-3.14.72.orig/sound/soc/soc-devres.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/soc-devres.c 2016-06-19 22:11:55.533125046 +0200
+@@ -52,6 +52,41 @@
+ }
+ EXPORT_SYMBOL_GPL(devm_snd_soc_register_component);
+
++static void devm_platform_release(struct device *dev, void *res)
++{
++ snd_soc_unregister_platform(*(struct device **)res);
++}
++
++/**
++ * devm_snd_soc_register_platform - resource managed platform registration
++ * @dev: Device used to manage platform
++ * @platform: platform to register
++ *
++ * Register a platform driver with automatic unregistration when the device is
++ * unregistered.
++ */
++int devm_snd_soc_register_platform(struct device *dev,
++ const struct snd_soc_platform_driver *platform_drv)
++{
++ struct device **ptr;
++ int ret;
++
++ ptr = devres_alloc(devm_platform_release, sizeof(*ptr), GFP_KERNEL);
++ if (!ptr)
++ return -ENOMEM;
++
++ ret = snd_soc_register_platform(dev, platform_drv);
++ if (ret == 0) {
++ *ptr = dev;
++ devres_add(dev, ptr);
++ } else {
++ devres_free(ptr);
++ }
++
++ return ret;
++}
++EXPORT_SYMBOL_GPL(devm_snd_soc_register_platform);
++
+ static void devm_card_release(struct device *dev, void *res)
+ {
+ snd_soc_unregister_card(*(struct snd_soc_card **)res);
+diff -Nur linux-3.14.72.orig/sound/soc/soc-pcm.c linux-3.14.72/sound/soc/soc-pcm.c
+--- linux-3.14.72.orig/sound/soc/soc-pcm.c 2016-06-08 02:22:20.000000000 +0200
++++ linux-3.14.72/sound/soc/soc-pcm.c 2016-06-19 22:11:55.533125046 +0200
+@@ -945,7 +945,7 @@
+ }
+ }
+
+- dev_err(card->dev, "ASoC: can't get %s BE for %s\n",
++ dev_dbg(card->dev, "ASoC: can't get %s BE for %s\n",
+ stream ? "capture" : "playback", widget->name);
+ return NULL;
+ }
+@@ -1062,7 +1062,7 @@
+ /* is there a valid BE rtd for this widget */
+ be = dpcm_get_be(card, list->widgets[i], stream);
+ if (!be) {
+- dev_err(fe->dev, "ASoC: no BE found for %s\n",
++ dev_dbg(fe->dev, "ASoC: no BE found for %s\n",
+ list->widgets[i]->name);
+ continue;
+ }
+@@ -1638,7 +1638,7 @@
+ be->dpcm[stream].state = SND_SOC_DPCM_STATE_STOP;
+ break;
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+- if (be->dpcm[stream].state != SND_SOC_DPCM_STATE_STOP)
++ if (be->dpcm[stream].state != SND_SOC_DPCM_STATE_START)
+ continue;
+
+ if (!snd_soc_dpcm_can_be_free_stop(fe, be, stream))
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 18:06:14 +0000